diff --git a/.travis.yml b/.travis.yml index bef14898d4233dc1efc8ea54a32a78ee76498a68..362ee0d73eedff7c311aa4753516f06b1670cff2 100644 --- a/.travis.yml +++ b/.travis.yml @@ -41,6 +41,7 @@ env: - RTT_BSP='lm3s8962' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='lm3s9b9x' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='lm4f232' RTT_TOOL_CHAIN='sourcery-arm' + - RTT_BSP='tm4c123bsp' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='tm4c129x' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='lpc43xx/M4' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='lpc176x' RTT_TOOL_CHAIN='sourcery-arm' @@ -103,13 +104,14 @@ env: - RTT_BSP='stm32/stm32f767-atk-apollo' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='stm32/stm32f767-fire-challenger' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='stm32/stm32f767-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm' + - RTT_BSP='stm32/stm32g070-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='stm32/stm32g071-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='stm32/stm32g431-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='stm32/stm32h743-atk-apollo' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='stm32/stm32h743-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='stm32/stm32h747-st-discovery' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='stm32/stm32l4r9-st-eval' RTT_TOOL_CHAIN='sourcery-arm' - - RTT_BSP='stm32/stm32l010-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm' + - RTT_BSP='stm32/stm32l010-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='stm32/stm32l053-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='stm32/stm32l412-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='stm32/stm32l432-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm' diff --git a/bsp/gd32vf103v-eval/board/Kconfig b/bsp/gd32vf103v-eval/board/Kconfig index fad38abdc06c0c2f52122a4452e93c98a0919348..36ad60465804884d85ad979b383ff221af53f81d 100644 --- a/bsp/gd32vf103v-eval/board/Kconfig +++ b/bsp/gd32vf103v-eval/board/Kconfig @@ -16,6 +16,11 @@ endmenu menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + menuconfig BSP_USING_UART bool "Enable USART" default y @@ -24,7 +29,8 @@ menu "On-chip Peripheral Drivers" config BSP_USING_UART0 bool "Enable USART0" default y - endif + endif + endmenu menu "Board extended module Drivers" diff --git a/bsp/gd32vf103v-eval/drivers/drv_gpio.c b/bsp/gd32vf103v-eval/drivers/drv_gpio.c new file mode 100644 index 0000000000000000000000000000000000000000..03b27aef9cd655ab3a6d705fa33dd5a9dad9fdd2 --- /dev/null +++ b/bsp/gd32vf103v-eval/drivers/drv_gpio.c @@ -0,0 +1,570 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-27 BalanceTWK first version + */ + +#include "drv_gpio.h" +#include + +#ifdef RT_USING_PIN + +#define EXTI_(x) BIT(x) + +static const struct pin_index pins[] = +{ +#if defined(GPIOA) + __GD32VF_PIN(0 , A, 0 ), + __GD32VF_PIN(1 , A, 1 ), + __GD32VF_PIN(2 , A, 2 ), + __GD32VF_PIN(3 , A, 3 ), + __GD32VF_PIN(4 , A, 4 ), + __GD32VF_PIN(5 , A, 5 ), + __GD32VF_PIN(6 , A, 6 ), + __GD32VF_PIN(7 , A, 7 ), + __GD32VF_PIN(8 , A, 8 ), + __GD32VF_PIN(9 , A, 9 ), + __GD32VF_PIN(10, A, 10), + __GD32VF_PIN(11, A, 11), + __GD32VF_PIN(12, A, 12), + __GD32VF_PIN(13, A, 13), + __GD32VF_PIN(14, A, 14), + __GD32VF_PIN(15, A, 15), +#if defined(GPIOB) + __GD32VF_PIN(16, B, 0), + __GD32VF_PIN(17, B, 1), + __GD32VF_PIN(18, B, 2), + __GD32VF_PIN(19, B, 3), + __GD32VF_PIN(20, B, 4), + __GD32VF_PIN(21, B, 5), + __GD32VF_PIN(22, B, 6), + __GD32VF_PIN(23, B, 7), + __GD32VF_PIN(24, B, 8), + __GD32VF_PIN(25, B, 9), + __GD32VF_PIN(26, B, 10), + __GD32VF_PIN(27, B, 11), + __GD32VF_PIN(28, B, 12), + __GD32VF_PIN(29, B, 13), + __GD32VF_PIN(30, B, 14), + __GD32VF_PIN(31, B, 15), +#if defined(GPIOC) + __GD32VF_PIN(32, C, 0), + __GD32VF_PIN(33, C, 1), + __GD32VF_PIN(34, C, 2), + __GD32VF_PIN(35, C, 3), + __GD32VF_PIN(36, C, 4), + __GD32VF_PIN(37, C, 5), + __GD32VF_PIN(38, C, 6), + __GD32VF_PIN(39, C, 7), + __GD32VF_PIN(40, C, 8), + __GD32VF_PIN(41, C, 9), + __GD32VF_PIN(42, C, 10), + __GD32VF_PIN(43, C, 11), + __GD32VF_PIN(44, C, 12), + __GD32VF_PIN(45, C, 13), + __GD32VF_PIN(46, C, 14), + __GD32VF_PIN(47, C, 15), +#if defined(GPIOD) + __GD32VF_PIN(48, D, 0), + __GD32VF_PIN(49, D, 1), + __GD32VF_PIN(50, D, 2), + __GD32VF_PIN(51, D, 3), + __GD32VF_PIN(52, D, 4), + __GD32VF_PIN(53, D, 5), + __GD32VF_PIN(54, D, 6), + __GD32VF_PIN(55, D, 7), + __GD32VF_PIN(56, D, 8), + __GD32VF_PIN(57, D, 9), + __GD32VF_PIN(58, D, 10), + __GD32VF_PIN(59, D, 11), + __GD32VF_PIN(60, D, 12), + __GD32VF_PIN(61, D, 13), + __GD32VF_PIN(62, D, 14), + __GD32VF_PIN(63, D, 15), +#if defined(GPIOE) + __GD32VF_PIN(64, E, 0), + __GD32VF_PIN(65, E, 1), + __GD32VF_PIN(66, E, 2), + __GD32VF_PIN(67, E, 3), + __GD32VF_PIN(68, E, 4), + __GD32VF_PIN(69, E, 5), + __GD32VF_PIN(70, E, 6), + __GD32VF_PIN(71, E, 7), + __GD32VF_PIN(72, E, 8), + __GD32VF_PIN(73, E, 9), + __GD32VF_PIN(74, E, 10), + __GD32VF_PIN(75, E, 11), + __GD32VF_PIN(76, E, 12), + __GD32VF_PIN(77, E, 13), + __GD32VF_PIN(78, E, 14), + __GD32VF_PIN(79, E, 15), +#endif /* defined(GPIOE) */ +#endif /* defined(GPIOD) */ +#endif /* defined(GPIOC) */ +#endif /* defined(GPIOB) */ +#endif /* defined(GPIOA) */ +}; + +static const struct pin_irq_map pin_irq_map[] = +{ + {GPIO_PIN_0, EXTI0_IRQn}, + {GPIO_PIN_1, EXTI1_IRQn}, + {GPIO_PIN_2, EXTI2_IRQn}, + {GPIO_PIN_3, EXTI3_IRQn}, + {GPIO_PIN_4, EXTI4_IRQn}, + {GPIO_PIN_5, EXTI5_9_IRQn}, + {GPIO_PIN_6, EXTI5_9_IRQn}, + {GPIO_PIN_7, EXTI5_9_IRQn}, + {GPIO_PIN_8, EXTI5_9_IRQn}, + {GPIO_PIN_9, EXTI5_9_IRQn}, + {GPIO_PIN_10, EXTI10_15_IRQn}, + {GPIO_PIN_11, EXTI10_15_IRQn}, + {GPIO_PIN_12, EXTI10_15_IRQn}, + {GPIO_PIN_13, EXTI10_15_IRQn}, + {GPIO_PIN_14, EXTI10_15_IRQn}, + {GPIO_PIN_15, EXTI10_15_IRQn}, +}; + +static struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, +}; +static uint32_t pin_irq_enable_mask=0; + +#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) +static const struct pin_index *get_pin(uint8_t pin) +{ + const struct pin_index *index; + + if (pin < ITEM_NUM(pins)) + { + index = &pins[pin]; + if (index->index == -1) + index = RT_NULL; + } + else + { + index = RT_NULL; + } + + return index; +}; + +static void gd32vf_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + const struct pin_index *index; + + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + gpio_bit_write(index->gpio_periph, index->pin, (bit_status)value); +} + +static int gd32vf_pin_read(rt_device_t dev, rt_base_t pin) +{ + int value; + const struct pin_index *index; + + index = get_pin(pin); + if (index == RT_NULL) + { + return PIN_LOW; + } + + value = gpio_input_bit_get(index->gpio_periph, index->pin); + return value; +} + +static void gd32vf_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + const struct pin_index *index; + + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + /* Configure GPIO_InitStructure */ + if (mode == PIN_MODE_OUTPUT) + { + /* output setting */ + gpio_init(index->gpio_periph, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, index->pin); + gpio_bit_reset(index->gpio_periph, index->pin); + } + else if (mode == PIN_MODE_INPUT) + { + /* input setting: not pull. */ + gpio_init(index->gpio_periph, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, index->pin); + gpio_bit_reset(index->gpio_periph, index->pin); + } + else if (mode == PIN_MODE_INPUT_PULLUP) + { + /* input setting: pull up. */ + gpio_init(index->gpio_periph, GPIO_MODE_IPU, GPIO_OSPEED_50MHZ, index->pin); + gpio_bit_reset(index->gpio_periph, index->pin); + } + else if (mode == PIN_MODE_INPUT_PULLDOWN) + { + /* input setting: pull down. */ + gpio_init(index->gpio_periph, GPIO_MODE_IPD, GPIO_OSPEED_50MHZ, index->pin); + gpio_bit_reset(index->gpio_periph, index->pin); + } + else if (mode == PIN_MODE_OUTPUT_OD) + { + /* output setting: od. */ + gpio_init(index->gpio_periph, GPIO_MODE_OUT_OD, GPIO_OSPEED_50MHZ, index->pin); + gpio_bit_reset(index->gpio_periph, index->pin); + } +} + +rt_inline rt_int32_t bit2bitno(rt_uint32_t bit) +{ + int i; + for (i = 0; i < 32; i++) + { + if ((0x01 << i) == bit) + { + return i; + } + } + return -1; +} + +rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit) +{ + rt_int32_t mapindex = bit2bitno(pinbit); + if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map)) + { + return RT_NULL; + } + return &pin_irq_map[mapindex]; +}; + +static rt_err_t gd32vf_pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t irqindex = -1; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + irqindex = bit2bitno(index->pin); + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == pin && + pin_irq_hdr_tab[irqindex].hdr == hdr && + pin_irq_hdr_tab[irqindex].mode == mode && + pin_irq_hdr_tab[irqindex].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + if (pin_irq_hdr_tab[irqindex].pin != -1) + { + rt_hw_interrupt_enable(level); + return RT_EBUSY; + } + pin_irq_hdr_tab[irqindex].pin = pin; + pin_irq_hdr_tab[irqindex].hdr = hdr; + pin_irq_hdr_tab[irqindex].mode = mode; + pin_irq_hdr_tab[irqindex].args = args; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t gd32vf_pin_dettach_irq(struct rt_device *device, rt_int32_t pin) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t irqindex = -1; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + irqindex = bit2bitno(index->pin); + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[irqindex].pin = -1; + pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + pin_irq_hdr_tab[irqindex].mode = 0; + pin_irq_hdr_tab[irqindex].args = RT_NULL; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t gd32vf_pin_irq_enable(struct rt_device *device, rt_base_t pin, + rt_uint32_t enabled) +{ + const struct pin_index *index; + const struct pin_irq_map *irqmap; + rt_base_t level; + rt_int32_t irqindex = -1; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + + /* configure pin as input */ + gpio_init(index->gpio_periph, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, index->pin); + if (enabled == PIN_IRQ_ENABLE) + { + irqindex = bit2bitno(index->pin); + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_ENOSYS; + } + + irqmap = &pin_irq_map[irqindex]; + + /* enable and set EXTI interrupt to the lowest priority */ + eclic_irq_enable(irqmap->irqno, 1, 1); + gpio_exti_source_select(GPIO_PORT_SOURCE_GPIOA, GPIO_PIN_SOURCE_0); + /* Configure GPIO_InitStructure */ + switch (pin_irq_hdr_tab[irqindex].mode) + { + case PIN_IRQ_MODE_RISING: + exti_init(EXTI_(irqindex), EXTI_INTERRUPT, EXTI_TRIG_RISING); + break; + case PIN_IRQ_MODE_FALLING: + exti_init(EXTI_(irqindex), EXTI_INTERRUPT, EXTI_TRIG_FALLING); + break; + case PIN_IRQ_MODE_RISING_FALLING: + exti_init(EXTI_(irqindex), EXTI_INTERRUPT, EXTI_TRIG_BOTH); + break; + } + + pin_irq_enable_mask |= irqmap->pinbit; + + exti_interrupt_flag_clear(EXTI_(index->pin)); + + rt_hw_interrupt_enable(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + irqmap = get_pin_irq_map(index->pin); + if (irqmap == RT_NULL) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + + gpio_bit_reset(index->gpio_periph, index->pin); + + pin_irq_enable_mask &= ~irqmap->pinbit; + + eclic_irq_disable(irqmap->irqno); + exti_interrupt_flag_clear(EXTI_(index->pin)); + + rt_hw_interrupt_enable(level); + } + else + { + return -RT_ENOSYS; + } + + return RT_EOK; +} +const static struct rt_pin_ops _gd32vf_pin_ops = +{ + gd32vf_pin_mode, + gd32vf_pin_write, + gd32vf_pin_read, + gd32vf_pin_attach_irq, + gd32vf_pin_dettach_irq, + gd32vf_pin_irq_enable, +}; + +rt_inline void pin_irq_hdr(int irqno) +{ + if (pin_irq_hdr_tab[irqno].hdr) + { + pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); + } +} + +/* IRQHandler start */ +void EXTI0_IRQHandler(void) +{ + if(EXTI_PD & (uint32_t) EXTI_0) + { + exti_interrupt_flag_clear(EXTI_0); + pin_irq_hdr(bit2bitno(GPIO_PIN_0)); + } +} +void EXTI1_IRQHandler(void) +{ + if(EXTI_PD & (uint32_t) EXTI_1) + { + exti_interrupt_flag_clear(EXTI_1); + pin_irq_hdr(bit2bitno(GPIO_PIN_1)); + } +} +void EXTI2_IRQHandler(void) +{ + if(EXTI_PD & (uint32_t) EXTI_2) + { + exti_interrupt_flag_clear(EXTI_2); + pin_irq_hdr(bit2bitno(GPIO_PIN_2)); + } +} +void EXTI3_IRQHandler(void) +{ + if(EXTI_PD & (uint32_t) EXTI_3) + { + exti_interrupt_flag_clear(EXTI_3); + pin_irq_hdr(bit2bitno(GPIO_PIN_3)); + } +} +void EXTI4_IRQHandler(void) +{ + if(EXTI_PD & (uint32_t) EXTI_4) + { + exti_interrupt_flag_clear(EXTI_4); + pin_irq_hdr(bit2bitno(GPIO_PIN_4)); + } +} +void EXTI5_9_IRQHandler(void) +{ + if(EXTI_PD & (uint32_t) EXTI_5) + { + exti_interrupt_flag_clear(EXTI_5); + pin_irq_hdr(bit2bitno(GPIO_PIN_5)); + } + + if(EXTI_PD & (uint32_t) EXTI_6) + { + exti_interrupt_flag_clear(EXTI_6); + pin_irq_hdr(bit2bitno(GPIO_PIN_6)); + } + + if(EXTI_PD & (uint32_t) EXTI_7) + { + exti_interrupt_flag_clear(EXTI_7); + pin_irq_hdr(bit2bitno(GPIO_PIN_7)); + } + + if(EXTI_PD & (uint32_t) EXTI_8) + { + exti_interrupt_flag_clear(EXTI_8); + pin_irq_hdr(bit2bitno(GPIO_PIN_8)); + } + + if(EXTI_PD & (uint32_t) EXTI_9) + { + exti_interrupt_flag_clear(EXTI_9); + pin_irq_hdr(bit2bitno(GPIO_PIN_9)); + } +} +void EXTI10_15_IRQHandler(void) +{ + if(EXTI_PD & (uint32_t) EXTI_10) + { + exti_interrupt_flag_clear(EXTI_10); + pin_irq_hdr(bit2bitno(GPIO_PIN_10)); + } + + if(EXTI_PD & (uint32_t) EXTI_11) + { + exti_interrupt_flag_clear(EXTI_11); + pin_irq_hdr(bit2bitno(GPIO_PIN_11)); + } + + if(EXTI_PD & (uint32_t) EXTI_12) + { + exti_interrupt_flag_clear(EXTI_12); + pin_irq_hdr(bit2bitno(GPIO_PIN_12)); + } + + if(EXTI_PD & (uint32_t) EXTI_13) + { + exti_interrupt_flag_clear(EXTI_13); + pin_irq_hdr(bit2bitno(GPIO_PIN_13)); + } + + if(EXTI_PD & (uint32_t) EXTI_14) + { + exti_interrupt_flag_clear(EXTI_14); + pin_irq_hdr(bit2bitno(GPIO_PIN_14)); + } + + if(EXTI_PD & (uint32_t) EXTI_15) + { + exti_interrupt_flag_clear(EXTI_15); + pin_irq_hdr(bit2bitno(GPIO_PIN_15)); + } +} +/* IRQHandler end */ + +int rt_hw_pin_init(void) +{ + /* enable the global interrupt */ + eclic_global_interrupt_enable(); + eclic_priority_group_set(ECLIC_PRIGROUP_LEVEL3_PRIO1); + + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_GPIOB); + rcu_periph_clock_enable(RCU_GPIOC); + rcu_periph_clock_enable(RCU_GPIOD); + rcu_periph_clock_enable(RCU_GPIOE); + + rcu_periph_clock_enable(RCU_AF); + return rt_device_pin_register("pin", &_gd32vf_pin_ops, RT_NULL); +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +#endif /* RT_USING_PIN */ diff --git a/bsp/gd32vf103v-eval/drivers/drv_gpio.h b/bsp/gd32vf103v-eval/drivers/drv_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..ccb8ea92a3e647d502ff43e650552b144f0ea81d --- /dev/null +++ b/bsp/gd32vf103v-eval/drivers/drv_gpio.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-27 BalanceTWK first version + */ + +#ifndef __DRV_GPIO__H__ +#define __DRV_GPIO__H__ + +#include +#include +#include "board.h" + +/* GD32VF GPIO driver */ +struct pin_index +{ + int index; + uint32_t gpio_periph; + uint32_t pin; +}; + +#define __GD32VF_PIN(index, gpio, gpio_index) \ + { \ + index, GPIO##gpio, GPIO_PIN_##gpio_index \ + } + +struct pin_irq_map +{ + rt_uint16_t pinbit; + IRQn_Type irqno; +}; + +int rt_hw_gpio_init(void); + +#endif /* __DRV_GPIO__H__ */ + +/******************* end of file *******************/ \ No newline at end of file diff --git a/bsp/ls2kdev/drivers/drv_pwm.c b/bsp/ls2kdev/drivers/drv_pwm.c new file mode 100644 index 0000000000000000000000000000000000000000..f703d7834aa37dc8f07d0aa171d4ee2206780b86 --- /dev/null +++ b/bsp/ls2kdev/drivers/drv_pwm.c @@ -0,0 +1,136 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright(c) 2020, Du Huanpeng<548708880@qq.com> + * + */ + +#include +#include +#include + +#ifdef RT_USING_PWM + +#define PWM0_BASE (0xFFFFFFFFBFe02000) +#define PWM1_BASE (0xFFFFFFFFBFe02010) +#define PWM2_BASE (0xFFFFFFFFBFe02020) +#define PWM3_BASE (0xFFFFFFFFBFe02030) + +#define CTRL_EN (1UL<<0) +#define CTRL_OE (1UL<<3) +#define CTRL_SINGL (1UL<<4) +#define CTRL_INTE (1UL<<5) +#define CTRL_INT (1UL<<6) +#define CTRL_RST (1UL<<7) +#define CTRL_CAPTE (1UL<<8) +#define CTRL_INVERT (1UL<<9) +#define CTRL_DZONE (1UL<<10) + +struct loongson_pwm { + rt_uint32_t __PAD0; + rt_uint32_t low_buffer; + rt_uint32_t full_buffer; + rt_uint32_t ctrl; +}; + +rt_err_t loongson_pwm_enable(struct rt_device_pwm *device, int channel) +{ + int **priv; + struct loongson_pwm *chip; + volatile rt_uint64_t *config0; + rt_uint64_t m; + + channel %= 4; + + config0 = (void *)GEN_CONFIG0_REG; + m = 1ULL << 12 << channel; + *config0 |= m; + + priv = device->parent.user_data; + chip = (void *)priv[channel]; + chip->ctrl = CTRL_EN; + + return RT_EOK; +} + +rt_err_t loongson_pwm_disable(struct rt_device_pwm *device, int channel) +{ + struct loongson_pwm **chip; + rt_uint64_t m; + + chip = device->parent.user_data; + channel %= 4; + chip[channel]->ctrl &= ~CTRL_EN; + + return RT_EOK; +} + +rt_err_t loongson_pwm_set(struct rt_device_pwm *device, int channel, rt_uint32_t period, rt_uint32_t pulse) +{ + struct loongson_pwm *chip; + rt_uint32_t **priv; + + priv = device->parent.user_data; + channel %= 4; + chip = (void *)priv[channel]; + + chip->ctrl &= ~CTRL_EN; + chip->full_buffer = period; + chip->low_buffer = pulse; + chip->ctrl |= CTRL_EN; + + return RT_EOK; +} + +static rt_err_t loongson_pwm_ioctl(struct rt_device_pwm *device, int cmd, void *arg) +{ + rt_err_t rc; + struct rt_pwm_configuration *cfg; + + cfg = (void *)arg; + + switch (cmd) { + case PWM_CMD_ENABLE: + rc = loongson_pwm_enable(device, cfg->channel); + break; + case PWM_CMD_DISABLE: + rc = loongson_pwm_disable(device, cfg->channel); + break; + case PWM_CMD_SET: + rc = loongson_pwm_set(device, cfg->channel, cfg->period, cfg->pulse); + break; + case PWM_CMD_GET: + rc = RT_ENOSYS; + break; + default: + rc = RT_EINVAL; + break; + } + return rc; +} + +struct rt_pwm_ops loongson_pwm_ops = { + .control = loongson_pwm_ioctl, +}; + +struct rt_device_pwm loongson_pwm = { + .ops = &loongson_pwm_ops, +}; + +int loongson_pwm_init(void) +{ + int rc = RT_EOK; + static rt_uint32_t *priv[] = { + (void *)PWM0_BASE, + (void *)PWM1_BASE, + (void *)PWM2_BASE, + (void *)PWM3_BASE + }; + rc = rt_device_pwm_register(&loongson_pwm, "pwm0", &loongson_pwm_ops, &priv); + return rc; +} +INIT_DEVICE_EXPORT(loongson_pwm_init); + +#endif /*RT_USING_PWM*/ diff --git a/bsp/ls2kdev/drivers/drv_rtc.c b/bsp/ls2kdev/drivers/drv_rtc.c new file mode 100644 index 0000000000000000000000000000000000000000..3a873cc6fcd3d89a28f941ae0b407fe583b94918 --- /dev/null +++ b/bsp/ls2kdev/drivers/drv_rtc.c @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2020, Du Huanpeng <548708880@qq.com> + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-01-30 armink the first version + * 2020-06-23 Du Huanpeng based on components/drivers/rtc/soft_rtc.c + */ + + +#include +#include +#include +#include +#include "ls2k1000.h" + +struct loongson_rtc { + rt_uint32_t sys_toytrim; + rt_uint32_t sys_toywrite0; + rt_uint32_t sys_toywrite1; + rt_uint32_t sys_toyread0; + rt_uint32_t sys_toyread1; + rt_uint32_t sys_toymatch0; + rt_uint32_t sys_toymatch1; + rt_uint32_t sys_toymatch2; + rt_uint32_t sys_rtcctrl; + rt_uint32_t __pad4[3]; + rt_uint32_t __pad5[4]; + rt_uint32_t sys_rtctrim; + rt_uint32_t sys_rtcwrite0; + rt_uint32_t sys_rtcread0; + rt_uint32_t sys_rtcmatch0; + rt_uint32_t sys_rtcmatch1; + rt_uint32_t sys_rtcmatch2; +}; + +/* bit field helpers. */ +#define __M(n) (~(~0<<(n))) +#define __RBF(number, n) ((number)&__M(n)) +#define __BF(number, n, m) __RBF((number>>m), (n-m+1)) +#define BF(number, n, m) (msys_toyread0, 3, 0); + msec *= 100; + + time.tm_sec = BF(rtctp->sys_toyread0, 9, 4); + time.tm_min = BF(rtctp->sys_toyread0, 15, 10); + time.tm_hour = BF(rtctp->sys_toyread0, 20, 16); + time.tm_mday = BF(rtctp->sys_toyread0, 21, 25); + time.tm_mon = BF(rtctp->sys_toyread0, 26, 31); + /* struct tm has three more members: + time.tm_isdst + time.tm_wday + time.tm_yday + */ + time.tm_mon -= 1; + time.tm_year = rtctp->sys_toyread1; + return &time; +} + +rtctime_t mkrtctime(struct tm *tm) +{ + rtctime_t rtctm; + struct tm tmptime; + + rtctm.sys_toyread0 <<= 31 - 26 + 1; + rtctm.sys_toyread0 |= tm->tm_mon + 1; + rtctm.sys_toyread0 <<= 25 - 21 + 1; + rtctm.sys_toyread0 |= tm->tm_mday; + rtctm.sys_toyread0 <<= 20 - 16 + 1; + rtctm.sys_toyread0 |= tm->tm_hour; + rtctm.sys_toyread0 <<= 15 - 10 + 1; + rtctm.sys_toyread0 |= tm->tm_min; + rtctm.sys_toyread0 <<= 9 - 4 + 1; + rtctm.sys_toyread0 |= tm->tm_sec; + /* Fixme: 0.1 second */ + rtctm.sys_toyread0 <<= 3 - 0 + 1; + rtctm.sys_toyread0 |= 0; + + rtctm.sys_toyread1 = tm->tm_year; + + tmptime = *localrtctime(&rtctm); + + return rtctm; +} + +static rt_err_t rt_rtc_open(rt_device_t dev, rt_uint16_t oflag) +{ + return RT_EOK; +} + +static rt_size_t rt_rtc_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) +{ + return 0; +} + +static rt_err_t rt_rtc_ioctl(rt_device_t dev, int cmd, void *args) +{ + rt_err_t err = RT_ENOSYS; + + static int count = 0; + + struct loongson_rtc *hw_rtc; + rtctime_t rtctm; + struct tm time; + struct tm tmptime; + time_t *t; + + hw_rtc = dev->user_data; + + t = (time_t *)args; + time = *localtime(t); + + rtctm.sys_toyread0 = hw_rtc->sys_toyread0; + rtctm.sys_toyread1 = hw_rtc->sys_toyread1; + rtctm.sys_rtcread0 = hw_rtc->sys_rtcread0; + tmptime = *localrtctime(&rtctm); + + switch (cmd) { + case RT_DEVICE_CTRL_RTC_GET_TIME: + *t = mktime(&tmptime); + break; + case RT_DEVICE_CTRL_RTC_SET_TIME: + tmptime.tm_hour = time.tm_hour; + tmptime.tm_min = time.tm_min; + tmptime.tm_sec = time.tm_sec; + + tmptime.tm_year = time.tm_year; + tmptime.tm_mon = time.tm_mon; + tmptime.tm_mday = time.tm_mday; + + rtctm = mkrtctime(&tmptime); + /* write to hw RTC */ + hw_rtc->sys_toywrite0 = rtctm.sys_toyread0; + hw_rtc->sys_toywrite1 = rtctm.sys_toyread1; + break; + case RT_DEVICE_CTRL_RTC_GET_ALARM: + break; + case RT_DEVICE_CTRL_RTC_SET_ALARM: + break; + default: + break; + } + + return RT_EOK; +} + +int rt_hw_rtc_init(void) +{ + static struct rt_device rtc = { + .type = RT_Device_Class_RTC, + .init = RT_NULL, + .open = rt_rtc_open, + .close = RT_NULL, + .read = rt_rtc_read, + .write = RT_NULL, + .control = rt_rtc_ioctl, + .user_data = (void *)RTC_BASE, + }; + rt_device_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR); +} + +INIT_DEVICE_EXPORT(rt_hw_rtc_init); diff --git a/bsp/ls2kdev/drivers/ls2k1000.h b/bsp/ls2kdev/drivers/ls2k1000.h index cb6586525e916760319a7de0edf47704bb68b21a..24396e7d3b9a3b5d8fb14fb6b6611f997beab9d5 100644 --- a/bsp/ls2kdev/drivers/ls2k1000.h +++ b/bsp/ls2kdev/drivers/ls2k1000.h @@ -20,6 +20,9 @@ #define GPIO_BASE 0xFFFFFFFFBFE10500 #define PLL_SYS_BASE 0xFFFFFFFFBFE10480 +#define RTC_BASE 0xFFFFFFFFBFE07820 + +#define GEN_CONFIG0_REG 0xFFFFFFFFBfe10420 void rt_hw_timer_handler(void); void rt_hw_uart_init(void); diff --git a/bsp/nrf5x/libraries/drivers/drv_gpio.c b/bsp/nrf5x/libraries/drivers/drv_gpio.c new file mode 100644 index 0000000000000000000000000000000000000000..f320fb81f2bd95c31b7683df4063e18b2ba6acf1 --- /dev/null +++ b/bsp/nrf5x/libraries/drivers/drv_gpio.c @@ -0,0 +1,375 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-16 guohp1128 first version + */ + +#include "drv_gpio.h" + +#ifdef RT_USING_PIN + +static const struct pin_index pins[] = +{ + __NRF5X_PIN(0 , 0, 0 ), + __NRF5X_PIN(1 , 0, 1 ), + __NRF5X_PIN(2 , 0, 2 ), + __NRF5X_PIN(3 , 0, 3 ), + __NRF5X_PIN(4 , 0, 4 ), + __NRF5X_PIN(5 , 0, 5 ), + __NRF5X_PIN(6 , 0, 6 ), + __NRF5X_PIN(7 , 0, 7 ), + __NRF5X_PIN(8 , 0, 8 ), + __NRF5X_PIN(9 , 0, 9 ), + __NRF5X_PIN(10, 0, 10), + __NRF5X_PIN(11, 0, 11), + __NRF5X_PIN(12, 0, 12), + __NRF5X_PIN(13, 0, 13), + __NRF5X_PIN(14, 0, 14), + __NRF5X_PIN(15, 0, 15), + __NRF5X_PIN(16, 0, 16), + __NRF5X_PIN(17, 0, 17), + __NRF5X_PIN(18, 0, 18), + __NRF5X_PIN(19, 0, 19), + __NRF5X_PIN(20, 0, 20), + __NRF5X_PIN(21, 0, 21), + __NRF5X_PIN(22, 0, 22), + __NRF5X_PIN(23, 0, 23), + __NRF5X_PIN(24, 0, 24), + __NRF5X_PIN(25, 0, 25), + __NRF5X_PIN(26, 0, 26), + __NRF5X_PIN(27, 0, 27), + __NRF5X_PIN(28, 0, 28), + __NRF5X_PIN(29, 0, 29), + __NRF5X_PIN(30, 0, 30), + __NRF5X_PIN(31, 0, 31), + __NRF5X_PIN(32, 1, 0 ), + __NRF5X_PIN(33, 1, 1 ), + __NRF5X_PIN(34, 1, 2 ), + __NRF5X_PIN(35, 1, 3 ), + __NRF5X_PIN(36, 1, 4 ), + __NRF5X_PIN(37, 1, 5 ), + __NRF5X_PIN(38, 1, 6 ), + __NRF5X_PIN(39, 1, 7 ), + __NRF5X_PIN(40, 1, 8 ), + __NRF5X_PIN(41, 1, 9 ), + __NRF5X_PIN(42, 1, 10), + __NRF5X_PIN(43, 1, 11), + __NRF5X_PIN(44, 1, 12), + __NRF5X_PIN(45, 1, 13), + __NRF5X_PIN(46, 1, 14), + __NRF5X_PIN(47, 1, 15), +}; + +/* EVENTS_IN[n](n=0..7) and EVENTS_PORT */ +static struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, +}; + +#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) + +/* pin: the number of pins */ +static const struct pin_index *get_pin(uint8_t pin) +{ + const struct pin_index *index; + + if (pin < ITEM_NUM(pins)) + { + index = &pins[pin]; + if (index->index == -1) + index = RT_NULL; + } + else + { + index = RT_NULL; + } + + return index; +}; + +static void nrf5x_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + const struct pin_index *index; + + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + nrf_gpio_pin_write(pin, value); +} + +static int nrf5x_pin_read(rt_device_t dev, rt_base_t pin) +{ + int value; + const struct pin_index *index; + + value = PIN_LOW; + + index = get_pin(pin); + if (index == RT_NULL) + { + return value; + } + + value = nrf_gpio_pin_read(pin); + + return value; +} + +static void nrf5x_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + const struct pin_index *index; + + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + if (mode == PIN_MODE_OUTPUT) + { + /* output setting */ + nrf_gpio_cfg_output(pin); + } + else if (mode == PIN_MODE_INPUT) + { + /* input setting: not pull. */ + nrf_gpio_cfg_input(pin, NRF_GPIO_PIN_NOPULL); + } + else if (mode == PIN_MODE_INPUT_PULLUP) + { + /* input setting: pull up. */ + nrf_gpio_cfg_input(pin, NRF_GPIO_PIN_PULLUP); + } + else if (mode == PIN_MODE_INPUT_PULLDOWN) + { + /* input setting: pull down. */ + nrf_gpio_cfg_input(pin, NRF_GPIO_PIN_PULLDOWN); + } + else if (mode == PIN_MODE_OUTPUT_OD) + { + /* output setting: od. */ + nrf_gpio_cfg( + pin, + NRF_GPIO_PIN_DIR_OUTPUT, + NRF_GPIO_PIN_INPUT_DISCONNECT, + NRF_GPIO_PIN_NOPULL, + NRF_GPIO_PIN_S0D1, + NRF_GPIO_PIN_NOSENSE); + } +} + +static void pin_irq_hdr(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) +{ + int i; + int irq_quantity; + + irq_quantity = ITEM_NUM(pin_irq_hdr_tab); + for(i = 0; i < irq_quantity; i++) + { + if(pin_irq_hdr_tab[i].pin == pin) + { + pin_irq_hdr_tab[i].hdr(pin_irq_hdr_tab[i].args); + } + } +} + +/* args = true : hi_accuracy(IN_EVENT) + * args = false: lo_accuracy(PORT_EVENT) + */ +static rt_err_t nrf5x_pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + const struct pin_index *index; + rt_int32_t irqindex = -1; + rt_base_t level; + nrfx_err_t err_code; + int i; + int irq_quantity; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + + irq_quantity = ITEM_NUM(pin_irq_hdr_tab); + for(i = 0; i < irq_quantity; i++) + { + if(pin_irq_hdr_tab[i].pin != -1) + { + irqindex = -1; + continue; + } + else + { + irqindex = i; + break; + } + } + if(irqindex == -1) + { + return RT_ENOMEM; + } + + level = rt_hw_interrupt_disable(); + pin_irq_hdr_tab[irqindex].pin = pin; + pin_irq_hdr_tab[irqindex].hdr = hdr; + pin_irq_hdr_tab[irqindex].mode = mode; + pin_irq_hdr_tab[irqindex].args = args; + + if(mode == PIN_IRQ_MODE_RISING) + { + nrfx_gpiote_in_config_t inConfig = NRFX_GPIOTE_CONFIG_IN_SENSE_LOTOHI(args); + inConfig.pull = NRF_GPIO_PIN_PULLDOWN; + err_code = nrfx_gpiote_in_init(pin, &inConfig, pin_irq_hdr); + } + + else if(mode == PIN_IRQ_MODE_FALLING) + { + nrfx_gpiote_in_config_t inConfig = NRFX_GPIOTE_CONFIG_IN_SENSE_HITOLO(args); + inConfig.pull = NRF_GPIO_PIN_PULLUP; + err_code = nrfx_gpiote_in_init(pin, &inConfig, pin_irq_hdr); + } + + else if(mode == PIN_IRQ_MODE_RISING_FALLING) + { + nrfx_gpiote_in_config_t inConfig = NRFX_GPIOTE_CONFIG_IN_SENSE_TOGGLE(args); + inConfig.pull = NRF_GPIO_PIN_PULLUP; + err_code = nrfx_gpiote_in_init(pin, &inConfig, pin_irq_hdr); + } + + rt_hw_interrupt_enable(level); + + switch(err_code) + { + case NRFX_ERROR_BUSY: + return RT_EBUSY; + case NRFX_SUCCESS: + return RT_EOK; + case NRFX_ERROR_NO_MEM: + return RT_ENOMEM; + default: + return RT_ERROR; + } +} + +static rt_err_t nrf5x_pin_dettach_irq(struct rt_device *device, rt_int32_t pin) +{ + const struct pin_index *index; + rt_base_t level; + int i; + int irq_quantity; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + + irq_quantity = ITEM_NUM(pin_irq_hdr_tab); + for(i = 0; i < irq_quantity; i++) + { + if(pin_irq_hdr_tab[i].pin == pin) + { + level = rt_hw_interrupt_disable(); + pin_irq_hdr_tab[i].pin = -1; + pin_irq_hdr_tab[i].hdr = RT_NULL; + pin_irq_hdr_tab[i].mode = 0; + pin_irq_hdr_tab[i].args = RT_NULL; + nrfx_gpiote_in_uninit(pin); + rt_hw_interrupt_enable(level); + break; + } + } + if(i >= irq_quantity) + { + return RT_ENOSYS; + } + return RT_EOK; +} + +static rt_err_t nrf5x_pin_irq_enable(struct rt_device *device, rt_base_t pin, + rt_uint32_t enabled) +{ + const struct pin_index *index; + rt_base_t level; + int i; + int irq_quantity; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + + irq_quantity = ITEM_NUM(pin_irq_hdr_tab); + for(i = 0; i < irq_quantity; i++) + { + if(pin_irq_hdr_tab[i].pin == pin) + { + level = rt_hw_interrupt_disable(); + if(enabled == PIN_IRQ_ENABLE) + { + nrfx_gpiote_in_event_enable(pin,enabled); + } + else if(enabled == PIN_IRQ_DISABLE) + { + nrfx_gpiote_in_event_disable(pin); + } + rt_hw_interrupt_enable(level); + break; + } + } + + if(i >= irq_quantity) + { + return RT_ENOSYS; + } + return RT_EOK; +} + +const static struct rt_pin_ops _nrf5x_pin_ops = +{ + nrf5x_pin_mode, + nrf5x_pin_write, + nrf5x_pin_read, + nrf5x_pin_attach_irq, + nrf5x_pin_dettach_irq, + nrf5x_pin_irq_enable, +}; + +int rt_hw_pin_init(void) +{ + nrfx_err_t err_code; + + err_code = (nrfx_err_t)rt_device_pin_register("pin", &_nrf5x_pin_ops, RT_NULL); + err_code = nrfx_gpiote_init(NRFX_GPIOTE_CONFIG_IRQ_PRIORITY); + + switch(err_code) + { + case NRFX_ERROR_INVALID_STATE: + return RT_EINVAL; + case NRFX_SUCCESS: + return RT_EOK; + default: + return RT_ERROR;; + } + +} + +#endif /* RT_USING_PIN */ diff --git a/bsp/nrf5x/libraries/drivers/drv_gpio.h b/bsp/nrf5x/libraries/drivers/drv_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..28eca1a810f81dd0fc8a12b85168b0c8c5769eb1 --- /dev/null +++ b/bsp/nrf5x/libraries/drivers/drv_gpio.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-16 guohp1128 first version + */ + +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ + +#include +#include +#include +#include +#include + +#define __NRF5X_PORT(port) NRF_P##port##_BASE + +#define GET_PIN(PORTx,PIN) (rt_base_t)((32 * ( ((rt_base_t)__NRF5X_PORT(PORTx) - (rt_base_t)NRF_P0_BASE)/(0x0300UL) )) + PIN) + +#define __NRF5X_PIN(index, gpio, gpio_index) \ + { \ + index, NRF_P##gpio, gpio_index \ + } + +#define __NRF5X_PIN_RESERVE \ + { \ + -1, 0, 0 \ + } + +/* nrf5x GPIO driver */ +struct pin_index +{ + int index; + NRF_GPIO_Type *gpio;//NRF_P0 or NRF_P1 + uint32_t pin; +}; + +static void nrf5x_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value); +static int nrf5x_pin_read(rt_device_t dev, rt_base_t pin); +static void nrf5x_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode); +static rt_err_t nrf5x_pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args); +static rt_err_t nrf5x_pin_dettach_irq(struct rt_device *device, rt_int32_t pin); +static rt_err_t nrf5x_pin_irq_enable(struct rt_device *device, rt_base_t pin, + rt_uint32_t enabled); +int rt_hw_pin_init(void); + +#endif /* __DRV_GPIO_H__ */ + diff --git a/bsp/nrf5x/nrf52840/applications/application.c b/bsp/nrf5x/nrf52840/applications/application.c index ce53a6dce9ad4e69f7b478627ed292d7cf95358b..e11be12225d0818b6b7e37f599b1e154181df648 100644 --- a/bsp/nrf5x/nrf52840/applications/application.c +++ b/bsp/nrf5x/nrf52840/applications/application.c @@ -25,25 +25,23 @@ #include #endif -#include +#include #define DK_BOARD_LED_1 13 int main(void) { - int count = 1; - nrf_gpio_cfg_output(DK_BOARD_LED_1); - + int count = 1; + rt_pin_mode(DK_BOARD_LED_1, PIN_MODE_OUTPUT); + while (count++) - { - nrf_gpio_pin_set(DK_BOARD_LED_1); + { + rt_pin_write(DK_BOARD_LED_1, PIN_HIGH); rt_thread_mdelay(500); - nrf_gpio_pin_clear(DK_BOARD_LED_1); - rt_thread_mdelay(500); - + rt_pin_write(DK_BOARD_LED_1, PIN_LOW); + rt_thread_mdelay(500); } return RT_EOK; } - /*@}*/ diff --git a/bsp/nrf5x/nrf52840/board/board.c b/bsp/nrf5x/nrf52840/board/board.c index d62fbee9f3aeb9ca9b1ba546a1c4549c762e1c53..18723be78d79058cc923ba65b90ba7460c2b97d9 100644 --- a/bsp/nrf5x/nrf52840/board/board.c +++ b/bsp/nrf5x/nrf52840/board/board.c @@ -3,6 +3,7 @@ #include #include "board.h" +#include "drv_gpio.h" #include "drv_uart.h" void SysTick_Configuration(void) @@ -47,6 +48,11 @@ void rt_hw_board_init(void) rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); #endif +/* Pin driver initialization is open by default */ +#ifdef RT_USING_PIN + rt_hw_pin_init(); +#endif + #ifdef RT_USING_SERIAL rt_hw_uart_init(); #endif diff --git a/bsp/nrf5x/nrf52840/board/board.h b/bsp/nrf5x/nrf52840/board/board.h index 669f903e55593ff813b69b047bb45371815afae6..f80896078074199fdac2d85c2d23d3631d053b19 100644 --- a/bsp/nrf5x/nrf52840/board/board.h +++ b/bsp/nrf5x/nrf52840/board/board.h @@ -2,7 +2,7 @@ #define _BOARD_H_ #include - +#include #include "nrf.h" #define MCU_FLASH_SIZE MCU_FLASH_SIZE_KB*1024 diff --git a/bsp/nrf5x/nrf52840/board/sdk_config.h b/bsp/nrf5x/nrf52840/board/sdk_config.h index 3ad63df3ea974d73578a083341e757112aaa69a3..619e06d23f2c5ad63afd487afe44c9b150f49e1d 100644 --- a/bsp/nrf5x/nrf52840/board/sdk_config.h +++ b/bsp/nrf5x/nrf52840/board/sdk_config.h @@ -1898,7 +1898,7 @@ // NRFX_GPIOTE_ENABLED - nrfx_gpiote - GPIOTE peripheral driver //========================================================== #ifndef NRFX_GPIOTE_ENABLED -#define NRFX_GPIOTE_ENABLED 0 +#define NRFX_GPIOTE_ENABLED 1 #endif // NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins #ifndef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS diff --git a/bsp/nuvoton/README.md b/bsp/nuvoton/README.md new file mode 100644 index 0000000000000000000000000000000000000000..f4dc82222356c73f8be377abd94db5db2903fc7e --- /dev/null +++ b/bsp/nuvoton/README.md @@ -0,0 +1,7 @@ +# Nuvoton BSP descriptions +Current supported BSP shown in below table: + +| **BSP folder** | **Board name** | +|:------------------------- |:-------------------------- | +| [numaker-iot-m487](numaker-iot-m487) | Nuvoton NuMaker-IoT-m487 | +| [numaker-pfm-m487](numaker-pfm-m487) | Nuvoton NuMaker-PFM-m487 | diff --git a/bsp/nuvoton/libraries/Kconfig b/bsp/nuvoton/libraries/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..5c40662883764d77352a61a0696ad896ec89b077 --- /dev/null +++ b/bsp/nuvoton/libraries/Kconfig @@ -0,0 +1,2 @@ +config SOC_FAMILY_NUMICRO + bool diff --git a/bsp/nuvoton/libraries/m480/CMSIS/Include/arm_common_tables.h b/bsp/nuvoton/libraries/m480/CMSIS/Include/arm_common_tables.h new file mode 100644 index 0000000000000000000000000000000000000000..8742a5699153c3d67e998d300ecb9045ec1b5962 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/CMSIS/Include/arm_common_tables.h @@ -0,0 +1,136 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 19. October 2015 +* $Revision: V.1.4.5 a +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.h +* +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +/* extern const q31_t realCoefAQ31[1024]; */ +/* extern const q31_t realCoefBQ31[1024]; */ +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_4096_q15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + + +/* floating-point bit reversal tables */ +#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) +#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) +#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) +#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; + +/* fixed-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) +#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) +#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) +#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) +#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) +#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/bsp/nuvoton/libraries/m480/CMSIS/Include/arm_const_structs.h b/bsp/nuvoton/libraries/m480/CMSIS/Include/arm_const_structs.h new file mode 100644 index 0000000000000000000000000000000000000000..726d06eb692f0539165e4e0f675eab0b1f2b59c4 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/CMSIS/Include/arm_const_structs.h @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 19. March 2015 +* $Revision: V.1.4.5 +* +* Project: CMSIS DSP Library +* Title: arm_const_structs.h +* +* Description: This file has constant structs that are initialized for +* user convenience. For example, some can be given as +* arguments to the arm_cfft_f32() function. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/bsp/nuvoton/libraries/m480/CMSIS/Include/arm_math.h b/bsp/nuvoton/libraries/m480/CMSIS/Include/arm_math.h new file mode 100644 index 0000000000000000000000000000000000000000..d33f8a9b3b57f9b146dc5da036b06281d17a4594 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/CMSIS/Include/arm_math.h @@ -0,0 +1,7154 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2015 ARM Limited. All rights reserved. +* +* $Date: 20. October 2015 +* $Revision: V1.4.5 b +* +* Project: CMSIS DSP Library +* Title: arm_math.h +* +* Description: Public header file for CMSIS DSP Library +* +* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7l_math.lib (Little endian on Cortex-M7) + * - arm_cortexM7b_math.lib (Big endian on Cortex-M7) + * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) + * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) + * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) + * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) + * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+) + * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK-ARM version 5.14.0.0 + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. + * + * Pre-processor Macros + * ------------ + * + * Each library project have differant pre-processor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and + * ARM_MATH_CM7 for building the library on cortex-M7. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2015 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +/* ignore some GCC warnings */ +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) + #include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI +#define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined __CC_ARM + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED __attribute__((unused)) + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + +#elif defined __GNUC__ + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + +#elif defined __ICCARM__ + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED + +#elif defined __CSMC__ + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED + +#elif defined __TASKING__ + #define __SIMD32_TYPE __unaligned int32_t + #define CMSIS_UNUSED + +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif + + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + static __INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + static __INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + static __INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + static __INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + static __INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + +/* + #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) + #define __CLZ __clz + #endif + */ +/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */ +#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ) + static __INLINE uint32_t __CLZ( + q31_t data); + + static __INLINE uint32_t __CLZ( + q31_t data) + { + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } + + return (count); + } +#endif + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + static __INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if(in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + static __INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if(in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + + + /* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0_FAMILY) + static __INLINE q31_t __SSAT( + q31_t x, + uint32_t y) + { + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) + { + posMax = posMax * 2; + } + + if(x > 0) + { + posMax = (posMax - 1); + + if(x > posMax) + { + x = posMax; + } + } + else + { + negMin = -posMax; + + if(x < negMin) + { + x = negMin; + } + } + return (x); + } +#endif /* end of ARM_MATH_CM0_FAMILY */ + + + /* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + static __INLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + static __INLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + static __INLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + static __INLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + static __INLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + static __INLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + static __INLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + static __INLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + static __INLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + static __INLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + static __INLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + static __INLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + static __INLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + static __INLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + static __INLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + static __INLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + static __INLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + static __INLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + static __INLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + static __INLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + static __INLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + static __INLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + +#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#ifdef ARM_MATH_CM0_FAMILY + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] S points to an instance of the floating-point FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + static __INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + static __INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + static __INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#ifndef ARM_MATH_CM0_FAMILY + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + */ + static __INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + } + + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + static __INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + */ + static __INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + static __INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * The function implements the forward Park transform. + * + */ + static __INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + static __INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + */ + static __INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + static __INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + static __INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if(i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + static __INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + } + } + + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + static __INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + static __INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if(index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + static __INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if(in >= 0.0f) + { + +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined(__GNUC__) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + /** + * @brief floating-point Circular write function. + */ + static __INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + static __INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + static __INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + static __INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + static __INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + static __INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + static __INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + static __INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + static __INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + static __INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__GNUC__) + #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ICCARM__) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__CSMC__) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__TASKING__) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/bsp/nuvoton/libraries/m480/CMSIS/Include/cmsis_armcc.h b/bsp/nuvoton/libraries/m480/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 0000000000000000000000000000000000000000..74c49c67defb6382f28a359d5678c5996add541c --- /dev/null +++ b/bsp/nuvoton/libraries/m480/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,734 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return(result); +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/nuvoton/libraries/m480/CMSIS/Include/cmsis_armcc_V6.h b/bsp/nuvoton/libraries/m480/CMSIS/Include/cmsis_armcc_V6.h new file mode 100644 index 0000000000000000000000000000000000000000..cd13240ce360250f496f1fd8c04df7ee23c0a8c9 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/CMSIS/Include/cmsis_armcc_V6.h @@ -0,0 +1,1800 @@ +/**************************************************************************//** + * @file cmsis_armcc_V6.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_ARMCC_V6_H +#define __CMSIS_ARMCC_V6_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get IPSR Register (non-secure) + \details Returns the content of the non-secure IPSR Register when in secure state. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get APSR Register (non-secure) + \details Returns the content of the non-secure APSR Register when in secure state. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get xPSR Register (non-secure) + \details Returns the content of the non-secure xPSR Register when in secure state. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : "sp"); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : "sp"); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t value) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (value) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Base Priority with condition (non_secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value) +{ + __ASM volatile ("MSR basepri_max_ns, %0" : : "r" (value) : "memory"); +} +#endif + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + + +#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + +#if (__ARM_ARCH_8M__ == 1U) + +/** + \brief Get Process Stack Pointer Limit + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Get Process Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Get Main Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Set Main Stack Pointer Limit (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +} +#endif + +#endif /* (__ARM_ARCH_8M__ == 1U) */ + + +#if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=4 */ + +/** + \brief Get FPSCR + \details eturns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#define __get_FPSCR __builtin_arm_get_fpscr +#if 0 +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} +#endif + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get FPSCR (non-secure) + \details Returns the current value of the non-secure Floating Point Status/Control register when in secure state. + \return Floating Point Status/Control register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMRS %0, fpscr_ns" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} +#endif + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#define __set_FPSCR __builtin_arm_set_fpscr +#if 0 +__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} +#endif + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set FPSCR (non-secure) + \details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMSR fpscr_ns, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} +#endif + +#endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __builtin_bswap32 + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16 __builtin_bswap16 /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ +#if 0 +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} +#endif + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ + /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ + /* ToDo: ARMCC_V6: check if __builtin_arm_rbit is supported */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +/*#define __SSAT __builtin_arm_ssat*/ +#define __SSAT(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat +#if 0 +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) +#endif + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + +#if (__ARM_ARCH_8M__ == 1U) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* (__ARM_ARCH_8M__ == 1U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__ARM_FEATURE_DSP == 1U) /* ToDo: ARMCC_V6: This should be ARCH >= ARMv7-M + SIMD */ + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1U) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_V6_H */ diff --git a/bsp/nuvoton/libraries/m480/CMSIS/Include/cmsis_gcc.h b/bsp/nuvoton/libraries/m480/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 0000000000000000000000000000000000000000..bb89fbba9e40005859e15a8d584e998cbdb6ae59 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,1373 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/nuvoton/libraries/m480/CMSIS/Include/core_cm0.h b/bsp/nuvoton/libraries/m480/CMSIS/Include/core_cm0.h new file mode 100644 index 0000000000000000000000000000000000000000..711dad551702720712e7933bb693699e5ea745fa --- /dev/null +++ b/bsp/nuvoton/libraries/m480/CMSIS/Include/core_cm0.h @@ -0,0 +1,798 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nuvoton/libraries/m480/CMSIS/Include/core_cm0plus.h b/bsp/nuvoton/libraries/m480/CMSIS/Include/core_cm0plus.h new file mode 100644 index 0000000000000000000000000000000000000000..b04aa3905323c5a0376c26989c1a3c9b8f3afe6a --- /dev/null +++ b/bsp/nuvoton/libraries/m480/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,914 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nuvoton/libraries/m480/CMSIS/Include/core_cm3.h b/bsp/nuvoton/libraries/m480/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000000000000000000000000000000000000..b4ac4c7b05a799590575c0b5c8e24c51748ee20b --- /dev/null +++ b/bsp/nuvoton/libraries/m480/CMSIS/Include/core_cm3.h @@ -0,0 +1,1763 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U)) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nuvoton/libraries/m480/CMSIS/Include/core_cm4.h b/bsp/nuvoton/libraries/m480/CMSIS/Include/core_cm4.h new file mode 100644 index 0000000000000000000000000000000000000000..dc840ebf2221382b8ca8e9ed8ce72b99e4027ad1 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/CMSIS/Include/core_cm4.h @@ -0,0 +1,1937 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ +#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1U) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nuvoton/libraries/m480/CMSIS/Include/core_cm7.h b/bsp/nuvoton/libraries/m480/CMSIS/Include/core_cm7.h new file mode 100644 index 0000000000000000000000000000000000000000..3b7530ad505b57d283cc6f07e7f51b9a54be9a0b --- /dev/null +++ b/bsp/nuvoton/libraries/m480/CMSIS/Include/core_cm7.h @@ -0,0 +1,2512 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x07U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ +#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1U) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & 0x00000FF0UL) == 0x220UL) + { + return 2UL; /* Double + Single precision FPU */ + } + else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) + { + return 1UL; /* Single precision FPU */ + } + else + { + return 0UL; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCIMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nuvoton/libraries/m480/CMSIS/Include/core_cmFunc.h b/bsp/nuvoton/libraries/m480/CMSIS/Include/core_cmFunc.h new file mode 100644 index 0000000000000000000000000000000000000000..652a48af07a93d9a48ea9bfa818eebd6429045da --- /dev/null +++ b/bsp/nuvoton/libraries/m480/CMSIS/Include/core_cmFunc.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/nuvoton/libraries/m480/CMSIS/Include/core_cmInstr.h b/bsp/nuvoton/libraries/m480/CMSIS/Include/core_cmInstr.h new file mode 100644 index 0000000000000000000000000000000000000000..f474b0e6f362c73223e59af36ad30d2b87b9a61d --- /dev/null +++ b/bsp/nuvoton/libraries/m480/CMSIS/Include/core_cmInstr.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/nuvoton/libraries/m480/CMSIS/Include/core_cmSimd.h b/bsp/nuvoton/libraries/m480/CMSIS/Include/core_cmSimd.h new file mode 100644 index 0000000000000000000000000000000000000000..66bf5c2a725b6d1986ce32f2bd765ebe5aa481ea --- /dev/null +++ b/bsp/nuvoton/libraries/m480/CMSIS/Include/core_cmSimd.h @@ -0,0 +1,96 @@ +/**************************************************************************//** + * @file core_cmSimd.h + * @brief CMSIS Cortex-M SIMD Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMSIMD_H +#define __CORE_CMSIMD_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CMSIMD_H */ diff --git a/bsp/nuvoton/libraries/m480/CMSIS/Include/core_sc000.h b/bsp/nuvoton/libraries/m480/CMSIS/Include/core_sc000.h new file mode 100644 index 0000000000000000000000000000000000000000..514dbd81b9f776af5e0f29e65d075866c05a4b5a --- /dev/null +++ b/bsp/nuvoton/libraries/m480/CMSIS/Include/core_sc000.h @@ -0,0 +1,926 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of SC000 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nuvoton/libraries/m480/CMSIS/Include/core_sc300.h b/bsp/nuvoton/libraries/m480/CMSIS/Include/core_sc300.h new file mode 100644 index 0000000000000000000000000000000000000000..8bd18aa318a982b66863b4e413672eed272d2657 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/CMSIS/Include/core_sc300.h @@ -0,0 +1,1745 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1U]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nuvoton/libraries/m480/CMSIS/SConscript b/bsp/nuvoton/libraries/m480/CMSIS/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..904fca4146305571f7b12f37102ced3ffb275488 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/CMSIS/SConscript @@ -0,0 +1,16 @@ +import rtconfig +Import('RTT_ROOT') +from building import * + +# get current directory +cwd = GetCurrentDir() + +# The set of source files associated with this SConscript file. +src = Split(""" +""") + +path = [cwd + '/Include',] + +group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/M480.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/M480.h new file mode 100644 index 0000000000000000000000000000000000000000..782ee01aa9ac321bb57c4c030482422287aa9e33 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/M480.h @@ -0,0 +1,713 @@ +/**************************************************************************//** + * @file M480.h + * @version V1.00 + * @brief M480 peripheral access layer header file. + * This file contains all the peripheral register's definitions, + * bits definitions and memory mapping for NuMicro M480 MCU. + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +/** + \mainpage NuMicro M480 Driver Reference Guide + * + * Introduction + * + * This user manual describes the usage of M480 Series MCU device driver + * + * Disclaimer + * + * The Software is furnished "AS IS", without warranty as to performance or results, and + * the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all + * warranties, express, implied or otherwise, with regard to the Software, its use, or + * operation, including without limitation any and all warranties of merchantability, fitness + * for a particular purpose, and non-infringement of intellectual property rights. + * + * Important Notice + * + * Nuvoton Products are neither intended nor warranted for usage in systems or equipment, + * any malfunction or failure of which may cause loss of human life, bodily injury or severe + * property damage. Such applications are deemed, "Insecure Usage". + * + * Insecure usage includes, but is not limited to: equipment for surgical implementation, + * atomic energy control instruments, airplane or spaceship instruments, the control or + * operation of dynamic, brake or safety systems designed for vehicular use, traffic signal + * instruments, all types of safety devices, and other applications intended to support or + * sustain life. + * + * All Insecure Usage shall be made at customer's risk, and in the event that third parties + * lay claims to Nuvoton as a result of customer's Insecure Usage, customer shall indemnify + * the damages and liabilities thus incurred by Nuvoton. + * + * Please note that all data and specifications are subject to change without notice. All the + * trademarks of products and companies mentioned in this datasheet belong to their respective + * owners. + * + * Copyright Notice + * + * Copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + */ +#ifndef __M480_H__ +#define __M480_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************/ +/* Processor and Core Peripherals */ +/******************************************************************************/ +/** @addtogroup CMSIS_Device Device CMSIS Definitions + Configuration of the Cortex-M4 Processor and Core Peripherals + @{ +*/ + +/** + * @details Interrupt Number Definition. + */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */ + + /****** M480 Specific Interrupt Numbers ********************************************************/ + + BOD_IRQn = 0, /*!< Brown Out detection Interrupt */ + IRC_IRQn = 1, /*!< Internal RC Interrupt */ + PWRWU_IRQn = 2, /*!< Power Down Wake Up Interrupt */ + RAMPE_IRQn = 3, /*!< SRAM parity check failed Interrupt */ + CKFAIL_IRQn = 4, /*!< Clock failed Interrupt */ + RTC_IRQn = 6, /*!< Real Time Clock Interrupt */ + TAMPER_IRQn = 7, /*!< Tamper detection Interrupt */ + WDT_IRQn = 8, /*!< Watchdog timer Interrupt */ + WWDT_IRQn = 9, /*!< Window Watchdog timer Interrupt */ + EINT0_IRQn = 10, /*!< External Input 0 Interrupt */ + EINT1_IRQn = 11, /*!< External Input 1 Interrupt */ + EINT2_IRQn = 12, /*!< External Input 2 Interrupt */ + EINT3_IRQn = 13, /*!< External Input 3 Interrupt */ + EINT4_IRQn = 14, /*!< External Input 4 Interrupt */ + EINT5_IRQn = 15, /*!< External Input 5 Interrupt */ + GPA_IRQn = 16, /*!< GPIO Port A Interrupt */ + GPB_IRQn = 17, /*!< GPIO Port B Interrupt */ + GPC_IRQn = 18, /*!< GPIO Port C Interrupt */ + GPD_IRQn = 19, /*!< GPIO Port D Interrupt */ + GPE_IRQn = 20, /*!< GPIO Port E Interrupt */ + GPF_IRQn = 21, /*!< GPIO Port F Interrupt */ + QSPI0_IRQn = 22, /*!< QSPI0 Interrupt */ + SPI0_IRQn = 23, /*!< SPI0 Interrupt */ + BRAKE0_IRQn = 24, /*!< BRAKE0 Interrupt */ + EPWM0P0_IRQn = 25, /*!< EPWM0P0 Interrupt */ + EPWM0P1_IRQn = 26, /*!< EPWM0P1 Interrupt */ + EPWM0P2_IRQn = 27, /*!< EPWM0P2 Interrupt */ + BRAKE1_IRQn = 28, /*!< BRAKE1 Interrupt */ + EPWM1P0_IRQn = 29, /*!< EPWM1P0 Interrupt */ + EPWM1P1_IRQn = 30, /*!< EPWM1P1 Interrupt */ + EPWM1P2_IRQn = 31, /*!< EPWM1P2 Interrupt */ + TMR0_IRQn = 32, /*!< Timer 0 Interrupt */ + TMR1_IRQn = 33, /*!< Timer 1 Interrupt */ + TMR2_IRQn = 34, /*!< Timer 2 Interrupt */ + TMR3_IRQn = 35, /*!< Timer 3 Interrupt */ + UART0_IRQn = 36, /*!< UART 0 Interrupt */ + UART1_IRQn = 37, /*!< UART 1 Interrupt */ + I2C0_IRQn = 38, /*!< I2C 0 Interrupt */ + I2C1_IRQn = 39, /*!< I2C 1 Interrupt */ + PDMA_IRQn = 40, /*!< Peripheral DMA Interrupt */ + DAC_IRQn = 41, /*!< DAC Interrupt */ + EADC00_IRQn = 42, /*!< EADC00 Interrupt */ + EADC01_IRQn = 43, /*!< EADC01 Interrupt */ + ACMP01_IRQn = 44, /*!< Analog Comparator 0 and 1 Interrupt */ + EADC02_IRQn = 46, /*!< EADC02 Interrupt */ + EADC03_IRQn = 47, /*!< EADC03 Interrupt */ + UART2_IRQn = 48, /*!< UART2 Interrupt */ + UART3_IRQn = 49, /*!< UART3 Interrupt */ + QSPI1_IRQn = 50, /*!< QSPI1 Interrupt */ + SPI1_IRQn = 51, /*!< SPI1 Interrupt */ + SPI2_IRQn = 52, /*!< SPI2 Interrupt */ + USBD_IRQn = 53, /*!< USB device Interrupt */ + USBH_IRQn = 54, /*!< USB host Interrupt */ + USBOTG_IRQn = 55, /*!< USB OTG Interrupt */ + CAN0_IRQn = 56, /*!< CAN0 Interrupt */ + CAN1_IRQn = 57, /*!< CAN1 Interrupt */ + SC0_IRQn = 58, /*!< Smart Card 0 Interrupt */ + SC1_IRQn = 59, /*!< Smart Card 1 Interrupt */ + SC2_IRQn = 60, /*!< Smart Card 2 Interrupt */ + SPI3_IRQn = 62, /*!< SPI3 Interrupt */ + EMAC_TX_IRQn = 66, /*!< Ethernet MAC TX Interrupt */ + EMAC_RX_IRQn = 67, /*!< Ethernet MAC RX Interrupt */ + SDH0_IRQn = 64, /*!< Secure Digital Host Controller 0 Interrupt */ + USBD20_IRQn = 65, /*!< High Speed USB device Interrupt */ + I2S0_IRQn = 68, /*!< I2S0 Interrupt */ + OPA_IRQn = 70, /*!< OPA Interrupt */ + CRPT_IRQn = 71, /*!< CRPT Interrupt */ + GPG_IRQn = 72, /*!< GPIO Port G Interrupt */ + EINT6_IRQn = 73, /*!< External Input 6 Interrupt */ + UART4_IRQn = 74, /*!< UART4 Interrupt */ + UART5_IRQn = 75, /*!< UART5 Interrupt */ + USCI0_IRQn = 76, /*!< USCI0 Interrupt */ + USCI1_IRQn = 77, /*!< USCI1 Interrupt */ + BPWM0_IRQn = 78, /*!< BPWM0 Interrupt */ + BPWM1_IRQn = 79, /*!< BPWM1 Interrupt */ + SPIM_IRQn = 80, /*!< SPIM Interrupt */ + CCAP_IRQn = 81, /*!< CCAP Interrupt */ + I2C2_IRQn = 82, /*!< I2C2 Interrupt */ + QEI0_IRQn = 84, /*!< QEI0 Interrupt */ + QEI1_IRQn = 85, /*!< QEI1 Interrupt */ + ECAP0_IRQn = 86, /*!< ECAP0 Interrupt */ + ECAP1_IRQn = 87, /*!< ECAP1 Interrupt */ + GPH_IRQn = 88, /*!< GPIO Port H Interrupt */ + EINT7_IRQn = 89, /*!< External Input 7 Interrupt */ + SDH1_IRQn = 90, /*!< Secure Digital Host Controller 1 Interrupt */ + HSUSBH_IRQn = 92, /*!< High speed USB host Interrupt */ + USBOTG20_IRQn = 93, /*!< High speed USB OTG Interrupt */ + TRNG_IRQn = 101, /*!< TRNG Interrupt */ + UART6_IRQn = 102, /*!< UART6 Interrupt */ + UART7_IRQn = 103, /*!< UART7 Interrupt */ + EADC10_IRQn = 104, /*!< EADC10 Interrupt */ + EADC11_IRQn = 105, /*!< EADC11 Interrupt */ + EADC12_IRQn = 106, /*!< EADC12 Interrupt */ + EADC13_IRQn = 107, /*!< EADC13 Interrupt */ + CAN2_IRQn = 108, /*!< CAN2 Interrupt */ +} +IRQn_Type; + + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* Configuration of the Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0201UL /*!< Core Revision r2p1 */ +#define __NVIC_PRIO_BITS 4UL /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0UL /*!< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1UL /*!< MPU present or not */ +#ifdef __FPU_PRESENT +#undef __FPU_PRESENT +#define __FPU_PRESENT 1UL /*!< FPU present or not */ +#else +#define __FPU_PRESENT 1UL /*!< FPU present or not */ +#endif + +/*@}*/ /* end of group CMSIS_Device */ + + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_M480.h" /* System include file */ +#include + + + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/******************************************************************************/ +/* Register definitions */ +/******************************************************************************/ + +#include "sys_reg.h" +#include "clk_reg.h" +#include "fmc_reg.h" +#include "gpio_reg.h" +#include "pdma_reg.h" +#include "timer_reg.h" +#include "wdt_reg.h" +#include "wwdt_reg.h" +#include "rtc_reg.h" +#include "epwm_reg.h" +#include "bpwm_reg.h" +#include "qei_reg.h" +#include "ecap_reg.h" +#include "uart_reg.h" +#include "emac_reg.h" +#include "sc_reg.h" +#include "i2s_reg.h" +#include "spi_reg.h" +#include "qspi_reg.h" +#include "spim_reg.h" +#include "i2c_reg.h" +#include "uuart_reg.h" +#include "uspi_reg.h" +#include "ui2c_reg.h" +#include "can_reg.h" +#include "sdh_reg.h" +#include "ebi_reg.h" +#include "usbd_reg.h" +#include "hsusbd_reg.h" +#include "usbh_reg.h" +#include "hsusbh_reg.h" +#include "otg_reg.h" +#include "hsotg_reg.h" +#include "crc_reg.h" +#include "crypto_reg.h" +#include "trng_reg.h" +#include "eadc_reg.h" +#include "dac_reg.h" +#include "acmp_reg.h" +#include "opa_reg.h" +#include "ccap_reg.h" + + +/** @addtogroup PERIPHERAL_MEM_MAP Peripheral Memory Base + Memory Mapped Structure for Peripherals + @{ + */ +/* Peripheral and SRAM base address */ +#define FLASH_BASE ((uint32_t)0x00000000) /*!< Flash base address */ +#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM Base Address */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral Base Address */ +#define AHBPERIPH_BASE PERIPH_BASE /*!< AHB Base Address */ +#define APBPERIPH_BASE (PERIPH_BASE + (uint32_t)0x00040000) /*!< APB Base Address */ + +/*!< AHB peripherals */ +#define SYS_BASE (AHBPERIPH_BASE + 0x00000UL) +#define CLK_BASE (AHBPERIPH_BASE + 0x00200UL) +#define NMI_BASE (AHBPERIPH_BASE + 0x00300UL) +#define GPIOA_BASE (AHBPERIPH_BASE + 0x04000UL) +#define GPIOB_BASE (AHBPERIPH_BASE + 0x04040UL) +#define GPIOC_BASE (AHBPERIPH_BASE + 0x04080UL) +#define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0UL) +#define GPIOE_BASE (AHBPERIPH_BASE + 0x04100UL) +#define GPIOF_BASE (AHBPERIPH_BASE + 0x04140UL) +#define GPIOG_BASE (AHBPERIPH_BASE + 0x04180UL) +#define GPIOH_BASE (AHBPERIPH_BASE + 0x041C0UL) +#define GPIOI_BASE (AHBPERIPH_BASE + 0x04200UL) +#define GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440UL) +#define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800UL) +#define PDMA_BASE (AHBPERIPH_BASE + 0x08000UL) +#define USBH_BASE (AHBPERIPH_BASE + 0x09000UL) +#define HSUSBH_BASE (AHBPERIPH_BASE + 0x1A000UL) +#define EMAC_BASE (AHBPERIPH_BASE + 0x0B000UL) +#define FMC_BASE (AHBPERIPH_BASE + 0x0C000UL) +#define SDH0_BASE (AHBPERIPH_BASE + 0x0D000UL) +#define SDH1_BASE (AHBPERIPH_BASE + 0x0E000UL) +#define EBI_BASE (AHBPERIPH_BASE + 0x10000UL) +#define HSUSBD_BASE (AHBPERIPH_BASE + 0x19000UL) +#define CCAP_BASE (AHBPERIPH_BASE + 0x30000UL) +#define CRC_BASE (AHBPERIPH_BASE + 0x31000UL) +#define TAMPER_BASE (AHBPERIPH_BASE + 0xE1000UL) + +/*!< APB2 peripherals */ +#define WDT_BASE (APBPERIPH_BASE + 0x00000UL) +#define WWDT_BASE (APBPERIPH_BASE + 0x00100UL) +#define OPA_BASE (APBPERIPH_BASE + 0x06000UL) +#define I2S_BASE (APBPERIPH_BASE + 0x08000UL) +#define EADC1_BASE (APBPERIPH_BASE + 0x0B000UL) +#define TIMER0_BASE (APBPERIPH_BASE + 0x10000UL) +#define TIMER1_BASE (APBPERIPH_BASE + 0x10100UL) +#define EPWM0_BASE (APBPERIPH_BASE + 0x18000UL) +#define BPWM0_BASE (APBPERIPH_BASE + 0x1A000UL) +#define QSPI0_BASE (APBPERIPH_BASE + 0x20000UL) +#define SPI1_BASE (APBPERIPH_BASE + 0x22000UL) +#define SPI3_BASE (APBPERIPH_BASE + 0x24000UL) +#define UART0_BASE (APBPERIPH_BASE + 0x30000UL) +#define UART2_BASE (APBPERIPH_BASE + 0x32000UL) +#define UART4_BASE (APBPERIPH_BASE + 0x34000UL) +#define UART6_BASE (APBPERIPH_BASE + 0x36000UL) +#define I2C0_BASE (APBPERIPH_BASE + 0x40000UL) +#define I2C2_BASE (APBPERIPH_BASE + 0x42000UL) +#define CAN0_BASE (APBPERIPH_BASE + 0x60000UL) +#define CAN2_BASE (APBPERIPH_BASE + 0x62000UL) +#define QEI0_BASE (APBPERIPH_BASE + 0x70000UL) +#define ECAP0_BASE (APBPERIPH_BASE + 0x74000UL) +#define USCI0_BASE (APBPERIPH_BASE + 0x90000UL) + + +/*!< APB1 peripherals */ +#define RTC_BASE (APBPERIPH_BASE + 0x01000UL) +#define EADC_BASE (APBPERIPH_BASE + 0x03000UL) +#define ACMP01_BASE (APBPERIPH_BASE + 0x05000UL) +#define USBD_BASE (APBPERIPH_BASE + 0x80000UL) +#define OTG_BASE (APBPERIPH_BASE + 0x0D000UL) +#define HSOTG_BASE (APBPERIPH_BASE + 0x0F000UL) +#define TIMER2_BASE (APBPERIPH_BASE + 0x11000UL) +#define TIMER3_BASE (APBPERIPH_BASE + 0x11100UL) +#define EPWM1_BASE (APBPERIPH_BASE + 0x19000UL) +#define BPWM1_BASE (APBPERIPH_BASE + 0x1B000UL) +#define SPI0_BASE (APBPERIPH_BASE + 0x21000UL) +#define SPI2_BASE (APBPERIPH_BASE + 0x23000UL) +#define QSPI1_BASE (APBPERIPH_BASE + 0x29000UL) +#define UART1_BASE (APBPERIPH_BASE + 0x31000UL) +#define UART3_BASE (APBPERIPH_BASE + 0x33000UL) +#define UART5_BASE (APBPERIPH_BASE + 0x35000UL) +#define UART7_BASE (APBPERIPH_BASE + 0x37000UL) +#define I2C1_BASE (APBPERIPH_BASE + 0x41000UL) +#define CAN1_BASE (APBPERIPH_BASE + 0x61000UL) +#define QEI1_BASE (APBPERIPH_BASE + 0x71000UL) +#define ECAP1_BASE (APBPERIPH_BASE + 0x75000UL) +#define TRNG_BASE (APBPERIPH_BASE + 0x79000UL) +#define USCI1_BASE (APBPERIPH_BASE + 0x91000UL) +#define CRPT_BASE (0x50080000UL) +#define SPIM_BASE (0x40007000UL) + +#define SC0_BASE (APBPERIPH_BASE + 0x50000UL) +#define SC1_BASE (APBPERIPH_BASE + 0x51000UL) +#define SC2_BASE (APBPERIPH_BASE + 0x52000UL) +#define DAC0_BASE (APBPERIPH_BASE + 0x07000UL) +#define DAC1_BASE (APBPERIPH_BASE + 0x07040UL) +#define DACDBG_BASE (APBPERIPH_BASE + 0x07FECUL) +#define OPA0_BASE (APBPERIPH_BASE + 0x06000UL) + +/*@}*/ /* end of group PERIPHERAL_MEM_MAP */ + + +/** @addtogroup PERIPHERAL_DECLARATION Peripheral Pointer + The Declaration of Peripherals + @{ + */ + +#define SYS ((SYS_T *) SYS_BASE) +#define CLK ((CLK_T *) CLK_BASE) +#define NMI ((NMI_T *) NMI_BASE) +#define PA ((GPIO_T *) GPIOA_BASE) +#define PB ((GPIO_T *) GPIOB_BASE) +#define PC ((GPIO_T *) GPIOC_BASE) +#define PD ((GPIO_T *) GPIOD_BASE) +#define PE ((GPIO_T *) GPIOE_BASE) +#define PF ((GPIO_T *) GPIOF_BASE) +#define PG ((GPIO_T *) GPIOG_BASE) +#define PH ((GPIO_T *) GPIOH_BASE) +#define GPA ((GPIO_T *) GPIOA_BASE) +#define GPB ((GPIO_T *) GPIOB_BASE) +#define GPC ((GPIO_T *) GPIOC_BASE) +#define GPD ((GPIO_T *) GPIOD_BASE) +#define GPE ((GPIO_T *) GPIOE_BASE) +#define GPF ((GPIO_T *) GPIOF_BASE) +#define GPG ((GPIO_T *) GPIOG_BASE) +#define GPH ((GPIO_T *) GPIOH_BASE) +#define GPIO ((GPIO_DBCTL_T *) GPIO_DBCTL_BASE) +#define PDMA ((PDMA_T *) PDMA_BASE) +#define USBH ((USBH_T *) USBH_BASE) +#define HSUSBH ((HSUSBH_T *) HSUSBH_BASE) +#define EMAC ((EMAC_T *) EMAC_BASE) +#define FMC ((FMC_T *) FMC_BASE) +#define SDH0 ((SDH_T *) SDH0_BASE) +#define SDH1 ((SDH_T *) SDH1_BASE) +#define EBI ((EBI_T *) EBI_BASE) +#define CRC ((CRC_T *) CRC_BASE) +#define TAMPER ((TAMPER_T *) TAMPER_BASE) + +#define WDT ((WDT_T *) WDT_BASE) +#define WWDT ((WWDT_T *) WWDT_BASE) +#define RTC ((RTC_T *) RTC_BASE) +#define EADC ((EADC_T *) EADC_BASE) +#define EADC0 ((EADC_T *) EADC_BASE) +#define EADC1 ((EADC_T *) EADC1_BASE) +#define ACMP01 ((ACMP_T *) ACMP01_BASE) + +#define I2S0 ((I2S_T *) I2S_BASE) +#define USBD ((USBD_T *) USBD_BASE) +#define OTG ((OTG_T *) OTG_BASE) +#define HSUSBD ((HSUSBD_T *)HSUSBD_BASE) +#define HSOTG ((HSOTG_T *) HSOTG_BASE) +#define TIMER0 ((TIMER_T *) TIMER0_BASE) +#define TIMER1 ((TIMER_T *) TIMER1_BASE) +#define TIMER2 ((TIMER_T *) TIMER2_BASE) +#define TIMER3 ((TIMER_T *) TIMER3_BASE) +#define EPWM0 ((EPWM_T *) EPWM0_BASE) +#define EPWM1 ((EPWM_T *) EPWM1_BASE) +#define BPWM0 ((BPWM_T *) BPWM0_BASE) +#define BPWM1 ((BPWM_T *) BPWM1_BASE) +#define ECAP0 ((ECAP_T *) ECAP0_BASE) +#define ECAP1 ((ECAP_T *) ECAP1_BASE) +#define QEI0 ((QEI_T *) QEI0_BASE) +#define QEI1 ((QEI_T *) QEI1_BASE) +#define QSPI0 ((QSPI_T *) QSPI0_BASE) +#define QSPI1 ((QSPI_T *) QSPI1_BASE) +#define SPI0 ((SPI_T *) SPI0_BASE) +#define SPI1 ((SPI_T *) SPI1_BASE) +#define SPI2 ((SPI_T *) SPI2_BASE) +#define SPI3 ((SPI_T *) SPI3_BASE) +#define UART0 ((UART_T *) UART0_BASE) +#define UART1 ((UART_T *) UART1_BASE) +#define UART2 ((UART_T *) UART2_BASE) +#define UART3 ((UART_T *) UART3_BASE) +#define UART4 ((UART_T *) UART4_BASE) +#define UART5 ((UART_T *) UART5_BASE) +#define UART6 ((UART_T *) UART6_BASE) +#define UART7 ((UART_T *) UART7_BASE) +#define I2C0 ((I2C_T *) I2C0_BASE) +#define I2C1 ((I2C_T *) I2C1_BASE) +#define I2C2 ((I2C_T *) I2C2_BASE) +#define SC0 ((SC_T *) SC0_BASE) +#define SC1 ((SC_T *) SC1_BASE) +#define SC2 ((SC_T *) SC2_BASE) +#define CAN0 ((CAN_T *) CAN0_BASE) +#define CAN1 ((CAN_T *) CAN1_BASE) +#define CAN2 ((CAN_T *) CAN2_BASE) +#define CRPT ((CRPT_T *) CRPT_BASE) +#define TRNG ((TRNG_T *) TRNG_BASE) +#define SPIM ((volatile SPIM_T *) SPIM_BASE) +#define DAC0 ((DAC_T *) DAC0_BASE) +#define DAC1 ((DAC_T *) DAC1_BASE) +#define USPI0 ((USPI_T *) USCI0_BASE) /*!< USPI0 Configuration Struct */ +#define USPI1 ((USPI_T *) USCI1_BASE) /*!< USPI1 Configuration Struct */ +#define OPA ((OPA_T *) OPA_BASE) +#define UI2C0 ((UI2C_T *) USCI0_BASE) /*!< UI2C0 Configuration Struct */ +#define UI2C1 ((UI2C_T *) USCI1_BASE) /*!< UI2C1 Configuration Struct */ +#define UUART0 ((UUART_T *) USCI0_BASE) /*!< UUART0 Configuration Struct */ +#define UUART1 ((UUART_T *) USCI1_BASE) /*!< UUART1 Configuration Struct */ +#define CCAP ((CCAP_T *) CCAP_BASE) + +/*@}*/ /* end of group ERIPHERAL_DECLARATION */ + +/** @addtogroup IO_ROUTINE I/O Routines + The Declaration of I/O Routines + @{ + */ + +typedef volatile unsigned char vu8; ///< Define 8-bit unsigned volatile data type +typedef volatile unsigned short vu16; ///< Define 16-bit unsigned volatile data type +typedef volatile unsigned long vu32; ///< Define 32-bit unsigned volatile data type + +/** + * @brief Get a 8-bit unsigned value from specified address + * @param[in] addr Address to get 8-bit data from + * @return 8-bit unsigned value stored in specified address + */ +#define M8(addr) (*((vu8 *) (addr))) + +/** + * @brief Get a 16-bit unsigned value from specified address + * @param[in] addr Address to get 16-bit data from + * @return 16-bit unsigned value stored in specified address + * @note The input address must be 16-bit aligned + */ +#define M16(addr) (*((vu16 *) (addr))) + +/** + * @brief Get a 32-bit unsigned value from specified address + * @param[in] addr Address to get 32-bit data from + * @return 32-bit unsigned value stored in specified address + * @note The input address must be 32-bit aligned + */ +#define M32(addr) (*((vu32 *) (addr))) + +/** + * @brief Set a 32-bit unsigned value to specified I/O port + * @param[in] port Port address to set 32-bit data + * @param[in] value Value to write to I/O port + * @return None + * @note The output port must be 32-bit aligned + */ +#define outpw(port,value) *((volatile unsigned int *)(port)) = (value) + +/** + * @brief Get a 32-bit unsigned value from specified I/O port + * @param[in] port Port address to get 32-bit data from + * @return 32-bit unsigned value stored in specified I/O port + * @note The input port must be 32-bit aligned + */ +#define inpw(port) (*((volatile unsigned int *)(port))) + +/** + * @brief Set a 16-bit unsigned value to specified I/O port + * @param[in] port Port address to set 16-bit data + * @param[in] value Value to write to I/O port + * @return None + * @note The output port must be 16-bit aligned + */ +#define outps(port,value) *((volatile unsigned short *)(port)) = (value) + +/** + * @brief Get a 16-bit unsigned value from specified I/O port + * @param[in] port Port address to get 16-bit data from + * @return 16-bit unsigned value stored in specified I/O port + * @note The input port must be 16-bit aligned + */ +#define inps(port) (*((volatile unsigned short *)(port))) + +/** + * @brief Set a 8-bit unsigned value to specified I/O port + * @param[in] port Port address to set 8-bit data + * @param[in] value Value to write to I/O port + * @return None + */ +#define outpb(port,value) *((volatile unsigned char *)(port)) = (value) + +/** + * @brief Get a 8-bit unsigned value from specified I/O port + * @param[in] port Port address to get 8-bit data from + * @return 8-bit unsigned value stored in specified I/O port + */ +#define inpb(port) (*((volatile unsigned char *)(port))) + +/** + * @brief Set a 32-bit unsigned value to specified I/O port + * @param[in] port Port address to set 32-bit data + * @param[in] value Value to write to I/O port + * @return None + * @note The output port must be 32-bit aligned + */ +#define outp32(port,value) *((volatile unsigned int *)(port)) = (value) + +/** + * @brief Get a 32-bit unsigned value from specified I/O port + * @param[in] port Port address to get 32-bit data from + * @return 32-bit unsigned value stored in specified I/O port + * @note The input port must be 32-bit aligned + */ +#define inp32(port) (*((volatile unsigned int *)(port))) + +/** + * @brief Set a 16-bit unsigned value to specified I/O port + * @param[in] port Port address to set 16-bit data + * @param[in] value Value to write to I/O port + * @return None + * @note The output port must be 16-bit aligned + */ +#define outp16(port,value) *((volatile unsigned short *)(port)) = (value) + +/** + * @brief Get a 16-bit unsigned value from specified I/O port + * @param[in] port Port address to get 16-bit data from + * @return 16-bit unsigned value stored in specified I/O port + * @note The input port must be 16-bit aligned + */ +#define inp16(port) (*((volatile unsigned short *)(port))) + +/** + * @brief Set a 8-bit unsigned value to specified I/O port + * @param[in] port Port address to set 8-bit data + * @param[in] value Value to write to I/O port + * @return None + */ +#define outp8(port,value) *((volatile unsigned char *)(port)) = (value) + +/** + * @brief Get a 8-bit unsigned value from specified I/O port + * @param[in] port Port address to get 8-bit data from + * @return 8-bit unsigned value stored in specified I/O port + */ +#define inp8(port) (*((volatile unsigned char *)(port))) + + +/*@}*/ /* end of group IO_ROUTINE */ + +/******************************************************************************/ +/* Legacy Constants */ +/******************************************************************************/ +/** @addtogroup Legacy_Constants Legacy Constants + Legacy Constants + @{ +*/ + +#ifndef NULL +#define NULL (0) ///< NULL pointer +#endif + +#define TRUE (1UL) ///< Boolean true, define to use in API parameters or return value +#define FALSE (0UL) ///< Boolean false, define to use in API parameters or return value + +#define ENABLE (1UL) ///< Enable, define to use in API parameters +#define DISABLE (0UL) ///< Disable, define to use in API parameters + +/* Define one bit mask */ +#define BIT0 (0x00000001UL) ///< Bit 0 mask of an 32 bit integer +#define BIT1 (0x00000002UL) ///< Bit 1 mask of an 32 bit integer +#define BIT2 (0x00000004UL) ///< Bit 2 mask of an 32 bit integer +#define BIT3 (0x00000008UL) ///< Bit 3 mask of an 32 bit integer +#define BIT4 (0x00000010UL) ///< Bit 4 mask of an 32 bit integer +#define BIT5 (0x00000020UL) ///< Bit 5 mask of an 32 bit integer +#define BIT6 (0x00000040UL) ///< Bit 6 mask of an 32 bit integer +#define BIT7 (0x00000080UL) ///< Bit 7 mask of an 32 bit integer +#define BIT8 (0x00000100UL) ///< Bit 8 mask of an 32 bit integer +#define BIT9 (0x00000200UL) ///< Bit 9 mask of an 32 bit integer +#define BIT10 (0x00000400UL) ///< Bit 10 mask of an 32 bit integer +#define BIT11 (0x00000800UL) ///< Bit 11 mask of an 32 bit integer +#define BIT12 (0x00001000UL) ///< Bit 12 mask of an 32 bit integer +#define BIT13 (0x00002000UL) ///< Bit 13 mask of an 32 bit integer +#define BIT14 (0x00004000UL) ///< Bit 14 mask of an 32 bit integer +#define BIT15 (0x00008000UL) ///< Bit 15 mask of an 32 bit integer +#define BIT16 (0x00010000UL) ///< Bit 16 mask of an 32 bit integer +#define BIT17 (0x00020000UL) ///< Bit 17 mask of an 32 bit integer +#define BIT18 (0x00040000UL) ///< Bit 18 mask of an 32 bit integer +#define BIT19 (0x00080000UL) ///< Bit 19 mask of an 32 bit integer +#define BIT20 (0x00100000UL) ///< Bit 20 mask of an 32 bit integer +#define BIT21 (0x00200000UL) ///< Bit 21 mask of an 32 bit integer +#define BIT22 (0x00400000UL) ///< Bit 22 mask of an 32 bit integer +#define BIT23 (0x00800000UL) ///< Bit 23 mask of an 32 bit integer +#define BIT24 (0x01000000UL) ///< Bit 24 mask of an 32 bit integer +#define BIT25 (0x02000000UL) ///< Bit 25 mask of an 32 bit integer +#define BIT26 (0x04000000UL) ///< Bit 26 mask of an 32 bit integer +#define BIT27 (0x08000000UL) ///< Bit 27 mask of an 32 bit integer +#define BIT28 (0x10000000UL) ///< Bit 28 mask of an 32 bit integer +#define BIT29 (0x20000000UL) ///< Bit 29 mask of an 32 bit integer +#define BIT30 (0x40000000UL) ///< Bit 30 mask of an 32 bit integer +#define BIT31 (0x80000000UL) ///< Bit 31 mask of an 32 bit integer + +/* Byte Mask Definitions */ +#define BYTE0_Msk (0x000000FFUL) ///< Mask to get bit0~bit7 from a 32 bit integer +#define BYTE1_Msk (0x0000FF00UL) ///< Mask to get bit8~bit15 from a 32 bit integer +#define BYTE2_Msk (0x00FF0000UL) ///< Mask to get bit16~bit23 from a 32 bit integer +#define BYTE3_Msk (0xFF000000UL) ///< Mask to get bit24~bit31 from a 32 bit integer + +#define GET_BYTE0(u32Param) (((u32Param) & BYTE0_Msk) ) /*!< Extract Byte 0 (Bit 0~ 7) from parameter u32Param */ +#define GET_BYTE1(u32Param) (((u32Param) & BYTE1_Msk) >> 8) /*!< Extract Byte 1 (Bit 8~15) from parameter u32Param */ +#define GET_BYTE2(u32Param) (((u32Param) & BYTE2_Msk) >> 16) /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */ +#define GET_BYTE3(u32Param) (((u32Param) & BYTE3_Msk) >> 24) /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */ + +/*@}*/ /* end of group Legacy_Constants */ + + +/******************************************************************************/ +/* Peripheral header files */ +/******************************************************************************/ +#include "nu_sys.h" +#include "nu_clk.h" + +#include "nu_acmp.h" +#include "nu_dac.h" +#include "nu_emac.h" +#include "nu_uart.h" +#include "nu_usci_spi.h" +#include "nu_gpio.h" +#include "nu_ccap.h" +#include "nu_ecap.h" +#include "nu_qei.h" +#include "nu_timer.h" +#include "nu_timer_pwm.h" +#include "nu_pdma.h" +#include "nu_crypto.h" +#include "nu_trng.h" +#include "nu_fmc.h" +#include "nu_spim.h" +#include "nu_i2c.h" +#include "nu_i2s.h" +#include "nu_epwm.h" +#include "nu_eadc.h" +#include "nu_bpwm.h" +#include "nu_wdt.h" +#include "nu_wwdt.h" +#include "nu_opa.h" +#include "nu_crc.h" +#include "nu_ebi.h" +#include "nu_usci_i2c.h" +#include "nu_scuart.h" +#include "nu_sc.h" +#include "nu_spi.h" +#include "nu_qspi.h" +#include "nu_can.h" +#include "nu_rtc.h" +#include "nu_usci_uart.h" +#include "nu_sdh.h" +#include "nu_usbd.h" +#include "nu_hsusbd.h" +#include "nu_otg.h" +#include "nu_hsotg.h" + + +#ifdef __cplusplus +} +#endif + +#endif /* __M480_H__ */ + diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/NuMicro.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/NuMicro.h new file mode 100644 index 0000000000000000000000000000000000000000..c627d8af7c4b9bfe8d81f5fd7e958b7078830735 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/NuMicro.h @@ -0,0 +1,17 @@ +/**************************************************************************//** + * @file NuMicro.h + * @version V1.00 + * @brief NuMicro peripheral access layer header file. + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NUMICRO_H__ +#define __NUMICRO_H__ + +#include "nutool_clkcfg.h" +#include "M480.h" + +#endif /* __NUMICRO_H__ */ + + diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/acmp_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/acmp_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..663f86292a7ef5393e8e3e1540bd166676c00c06 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/acmp_reg.h @@ -0,0 +1,240 @@ +/**************************************************************************//** + * @file acmp_reg.h + * @version V1.00 + * @brief ACMP register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __ACMP_REG_H__ +#define __ACMP_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup ACMP Analog Comparator Controller(ACMP) + Memory Mapped Structure for ACMP Controller +@{ */ + +typedef struct +{ + + + /** + * @var ACMP_T::CTL + * Offset: 0x00~0x04 Analog Comparator 0/1 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ACMPEN |Comparator Enable Bit + * | | |0 = Comparator x Disabled. + * | | |1 = Comparator x Enabled. + * |[1] |ACMPIE |Comparator Interrupt Enable Bit + * | | |0 = Comparator x interrupt Disabled. + * | | |1 = Comparator x interrupt Enabled + * | | |If WKEN (ACMP_CTL0[16]) is set to 1, the wake-up interrupt function will be enabled as well. + * |[3] |ACMPOINV |Comparator Output Inverse + * | | |0 = Comparator x output inverse Disabled. + * | | |1 = Comparator x output inverse Enabled. + * |[5:4] |NEGSEL |Comparator Negative Input Selection + * | | |00 = ACMPx_N pin. + * | | |01 = Internal comparator reference voltage (CRV). + * | | |10 = Band-gap voltage. + * | | |11 = DAC output. + * |[7:6] |POSSEL |Comparator Positive Input Selection + * | | |00 = Input from ACMPx_P0. + * | | |01 = Input from ACMPx_P1. + * | | |10 = Input from ACMPx_P2. + * | | |11 = Input from ACMPx_P3. + * |[9:8] |INTPOL |Interrupt Condition Polarity Selection + * | | |ACMPIFx will be set to 1 when comparator output edge condition is detected. + * | | |00 = Rising edge or falling edge. + * | | |01 = Rising edge. + * | | |10 = Falling edge. + * | | |11 = Reserved. + * |[12] |OUTSEL |Comparator Output Select + * | | |0 = Comparator x output to ACMPx_O pin is unfiltered comparator output. + * | | |1 = Comparator x output to ACMPx_O pin is from filter output. + * |[15:13] |FILTSEL |Comparator Output Filter Count Selection + * | | |000 = Filter function is Disabled. + * | | |001 = ACMPx output is sampled 1 consecutive PCLK. + * | | |010 = ACMPx output is sampled 2 consecutive PCLKs. + * | | |011 = ACMPx output is sampled 4 consecutive PCLKs. + * | | |100 = ACMPx output is sampled 8 consecutive PCLKs. + * | | |101 = ACMPx output is sampled 16 consecutive PCLKs. + * | | |110 = ACMPx output is sampled 32 consecutive PCLKs. + * | | |111 = ACMPx output is sampled 64 consecutive PCLKs. + * |[16] |WKEN |Power-down Wake-up Enable Bit + * | | |0 = Wake-up function Disabled. + * | | |1 = Wake-up function Enabled. + * |[17] |WLATEN |Window Latch Mode Enable Bit + * | | |0 = Window Latch Mode Disabled. + * | | |1 = Window Latch Mode Enabled. + * |[18] |WCMPSEL |Window Compare Mode Selection + * | | |0 = Window Compare Mode Disabled. + * | | |1 = Window Compare Mode is Selected. + * |[25:24] |HYSSEL |Hysteresis Mode Selection + * | | |00 = Hysteresis is 0mV. + * | | |01 = Hysteresis is 10mV. + * | | |10 = Hysteresis is 20mV. + * | | |11 = Hysteresis is 30mV. + * |[29:28] |MODESEL |Propagation Delay Mode Selection + * | | |00 = Max propagation delay is 4.5uS, operation current is 1.2uA. + * | | |01 = Max propagation delay is 2uS, operation current is 3uA. + * | | |10 = Max propagation delay is 600nS, operation current is 10uA. + * | | |11 = Max propagation delay is 200nS, operation current is 75uA. + * @var ACMP_T::STATUS + * Offset: 0x08 Analog Comparator Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ACMPIF0 |Comparator 0 Interrupt Flag + * | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8]) + * | | |is detected on comparator 0 output. + * | | |This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1. + * | | |Note: Write 1 to clear this bit to 0. + * |[1] |ACMPIF1 |Comparator 1 Interrupt Flag + * | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8]) + * | | |is detected on comparator 1 output. + * | | |This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1. + * | | |Note: Write 1 to clear this bit to 0. + * |[4] |ACMPO0 |Comparator 0 Output + * | | |Synchronized to the PCLK to allow reading by software + * | | |Cleared when the comparator 0 is disabled, i.e. + * | | |ACMPEN (ACMP_CTL0[0]) is cleared to 0. + * |[5] |ACMPO1 |Comparator 1 Output + * | | |Synchronized to the PCLK to allow reading by software. + * | | |Cleared when the comparator 1 is disabled, i.e. + * | | |ACMPEN (ACMP_CTL1[0]) is cleared to 0. + * |[8] |WKIF0 |Comparator 0 Power-down Wake-up Interrupt Flag + * | | |This bit will be set to 1 when ACMP0 wake-up interrupt event occurs. + * | | |0 = No power-down wake-up occurred. + * | | |1 = Power-down wake-up occurred. + * | | |Note: Write 1 to clear this bit to 0. + * |[9] |WKIF1 |Comparator 1 Power-down Wake-up Interrupt Flag + * | | |This bit will be set to 1 when ACMP1 wake-up interrupt event occurs. + * | | |0 = No power-down wake-up occurred. + * | | |1 = Power-down wake-up occurred. + * | | |Note: Write 1 to clear this bit to 0. + * |[12] |ACMPS0 |Comparator 0 Status + * | | |Synchronized to the PCLK to allow reading by software + * | | |Cleared when the comparator 0 is disabled, i.e. + * | | |ACMPEN (ACMP_CTL0[0]) is cleared to 0. + * |[13] |ACMPS1 |Comparator 1 Status + * | | |Synchronized to the PCLK to allow reading by software + * | | |Cleared when the comparator 1 is disabled, i.e. + * | | |ACMPEN (ACMP_CTL1[0]) is cleared to 0. + * |[16] |ACMPWO |Comparator Window Output + * | | |This bit shows the output status of window compare mode + * | | |0 = The positive input voltage is outside the window. + * | | |1 = The positive input voltage is in the window. + * @var ACMP_T::VREF + * Offset: 0x0C Analog Comparator Reference Voltage Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |CRVCTL |Comparator Reference Voltage Setting + * | | |CRV = CRV source voltage * (1/6+CRVCTL/24). + * |[6] |CRVSSEL |CRV Source Voltage Selection + * | | |0 = VDDA is selected as CRV source voltage. + * | | |1 = The reference voltage defined by SYS_VREFCTL register is selected as CRV source voltage. + */ + __IO uint32_t CTL[2]; /*!< [0x0000~0x0004] Analog Comparator 0/1 Control Register */ + __IO uint32_t STATUS; /*!< [0x0008] Analog Comparator Status Register */ + __IO uint32_t VREF; /*!< [0x000c] Analog Comparator Reference Voltage Control Register */ + +} ACMP_T; + +/** + @addtogroup ACMP_CONST ACMP Bit Field Definition + Constant Definitions for ACMP Controller +@{ */ + +#define ACMP_CTL_ACMPEN_Pos (0) /*!< ACMP_T::CTL: ACMPEN Position */ +#define ACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos) /*!< ACMP_T::CTL: ACMPEN Mask */ + +#define ACMP_CTL_ACMPIE_Pos (1) /*!< ACMP_T::CTL: ACMPIE Position */ +#define ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos) /*!< ACMP_T::CTL: ACMPIE Mask */ + +#define ACMP_CTL_ACMPOINV_Pos (3) /*!< ACMP_T::CTL: ACMPOINV Position */ +#define ACMP_CTL_ACMPOINV_Msk (0x1ul << ACMP_CTL_ACMPOINV_Pos) /*!< ACMP_T::CTL: ACMPOINV Mask */ + +#define ACMP_CTL_NEGSEL_Pos (4) /*!< ACMP_T::CTL: NEGSEL Position */ +#define ACMP_CTL_NEGSEL_Msk (0x3ul << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_T::CTL: NEGSEL Mask */ + +#define ACMP_CTL_POSSEL_Pos (6) /*!< ACMP_T::CTL: POSSEL Position */ +#define ACMP_CTL_POSSEL_Msk (0x3ul << ACMP_CTL_POSSEL_Pos) /*!< ACMP_T::CTL: POSSEL Mask */ + +#define ACMP_CTL_INTPOL_Pos (8) /*!< ACMP_T::CTL: INTPOL Position */ +#define ACMP_CTL_INTPOL_Msk (0x3ul << ACMP_CTL_INTPOL_Pos) /*!< ACMP_T::CTL: INTPOL Mask */ + +#define ACMP_CTL_OUTSEL_Pos (12) /*!< ACMP_T::CTL: OUTSEL Position */ +#define ACMP_CTL_OUTSEL_Msk (0x1ul << ACMP_CTL_OUTSEL_Pos) /*!< ACMP_T::CTL: OUTSEL Mask */ + +#define ACMP_CTL_FILTSEL_Pos (13) /*!< ACMP_T::CTL: FILTSEL Position */ +#define ACMP_CTL_FILTSEL_Msk (0x7ul << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_T::CTL: FILTSEL Mask */ + +#define ACMP_CTL_WKEN_Pos (16) /*!< ACMP_T::CTL: WKEN Position */ +#define ACMP_CTL_WKEN_Msk (0x1ul << ACMP_CTL_WKEN_Pos) /*!< ACMP_T::CTL: WKEN Mask */ + +#define ACMP_CTL_WLATEN_Pos (17) /*!< ACMP_T::CTL: WLATEN Position */ +#define ACMP_CTL_WLATEN_Msk (0x1ul << ACMP_CTL_WLATEN_Pos) /*!< ACMP_T::CTL: WLATEN Mask */ + +#define ACMP_CTL_WCMPSEL_Pos (18) /*!< ACMP_T::CTL: WCMPSEL Position */ +#define ACMP_CTL_WCMPSEL_Msk (0x1ul << ACMP_CTL_WCMPSEL_Pos) /*!< ACMP_T::CTL: WCMPSEL Mask */ + +#define ACMP_CTL_HYSSEL_Pos (24) /*!< ACMP_T::CTL: HYSSEL Position */ +#define ACMP_CTL_HYSSEL_Msk (0x3ul << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_T::CTL: HYSSEL Mask */ + +#define ACMP_CTL_MODESEL_Pos (28) /*!< ACMP_T::CTL: MODESEL Position */ +#define ACMP_CTL_MODESEL_Msk (0x3ul << ACMP_CTL_MODESEL_Pos) /*!< ACMP_T::CTL: MODESEL Mask */ + +#define ACMP_STATUS_ACMPIF0_Pos (0) /*!< ACMP_T::STATUS: ACMPIF0 Position */ +#define ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos) /*!< ACMP_T::STATUS: ACMPIF0 Mask */ + +#define ACMP_STATUS_ACMPIF1_Pos (1) /*!< ACMP_T::STATUS: ACMPIF1 Position */ +#define ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos) /*!< ACMP_T::STATUS: ACMPIF1 Mask */ + +#define ACMP_STATUS_ACMPO0_Pos (4) /*!< ACMP_T::STATUS: ACMPO0 Position */ +#define ACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos) /*!< ACMP_T::STATUS: ACMPO0 Mask */ + +#define ACMP_STATUS_ACMPO1_Pos (5) /*!< ACMP_T::STATUS: ACMPO1 Position */ +#define ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos) /*!< ACMP_T::STATUS: ACMPO1 Mask */ + +#define ACMP_STATUS_WKIF0_Pos (8) /*!< ACMP_T::STATUS: WKIF0 Position */ +#define ACMP_STATUS_WKIF0_Msk (0x1ul << ACMP_STATUS_WKIF0_Pos) /*!< ACMP_T::STATUS: WKIF0 Mask */ + +#define ACMP_STATUS_WKIF1_Pos (9) /*!< ACMP_T::STATUS: WKIF1 Position */ +#define ACMP_STATUS_WKIF1_Msk (0x1ul << ACMP_STATUS_WKIF1_Pos) /*!< ACMP_T::STATUS: WKIF1 Mask */ + +#define ACMP_STATUS_ACMPS0_Pos (12) /*!< ACMP_T::STATUS: ACMPS0 Position */ +#define ACMP_STATUS_ACMPS0_Msk (0x1ul << ACMP_STATUS_ACMPS0_Pos) /*!< ACMP_T::STATUS: ACMPS0 Mask */ + +#define ACMP_STATUS_ACMPS1_Pos (13) /*!< ACMP_T::STATUS: ACMPS1 Position */ +#define ACMP_STATUS_ACMPS1_Msk (0x1ul << ACMP_STATUS_ACMPS1_Pos) /*!< ACMP_T::STATUS: ACMPS1 Mask */ + +#define ACMP_STATUS_ACMPWO_Pos (16) /*!< ACMP_T::STATUS: ACMPWO Position */ +#define ACMP_STATUS_ACMPWO_Msk (0x1ul << ACMP_STATUS_ACMPWO_Pos) /*!< ACMP_T::STATUS: ACMPWO Mask */ + +#define ACMP_VREF_CRVCTL_Pos (0) /*!< ACMP_T::VREF: CRVCTL Position */ +#define ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos) /*!< ACMP_T::VREF: CRVCTL Mask */ + +#define ACMP_VREF_CRVSSEL_Pos (6) /*!< ACMP_T::VREF: CRVSSEL Position */ +#define ACMP_VREF_CRVSSEL_Msk (0x1ul << ACMP_VREF_CRVSSEL_Pos) /*!< ACMP_T::VREF: CRVSSEL Mask */ + +/**@}*/ /* ACMP_CONST */ +/**@}*/ /* end of ACMP register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __ACMP_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/bpwm_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/bpwm_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..3a4fc35fdd36bfa0c1f1aa88cf2c34792526e4dd --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/bpwm_reg.h @@ -0,0 +1,1835 @@ +/**************************************************************************//** + * @file bpwm_reg.h + * @version V1.00 + * @brief BPWM register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __BPWM_REG_H__ +#define __BPWM_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup BPWM Basic Pulse Width Modulation Controller(BPWM) + Memory Mapped Structure for BPWM Controller +@{ */ + +typedef struct +{ + /** + * @var BCAPDAT_T::RCAPDAT + * Offset: 0x20C BPWM Rising Capture Data Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RCAPDAT |BPWM Rising Capture Data (Read Only) + * | | |When rising capture condition happened, the BPWM counter value will be saved in this register. + * @var BCAPDAT_T::FCAPDAT + * Offset: 0x210 BPWM Falling Capture Data Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FCAPDAT |BPWM Falling Capture Data (Read Only) + * | | |When falling capture condition happened, the BPWM counter value will be saved in this register. + */ + __IO uint32_t RCAPDAT; /*!< [0x20C/0x214/0x21C/0x224/0x22C/0x234] BPWM Rising Capture Data Register 0~5 */ + __IO uint32_t FCAPDAT; /*!< [0x210/0x218/0x220/0x228/0x230/0x238] BPWM Falling Capture Data Register 0~5 */ +} BCAPDAT_T; + +typedef struct +{ + + + /** + * @var BPWM_T::CTL0 + * Offset: 0x00 BPWM Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CTRLD0 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[1] |CTRLD1 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[2] |CTRLD2 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[3] |CTRLD3 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[4] |CTRLD4 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[5] |CTRLD5 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[16] |IMMLDEN0 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[17] |IMMLDEN1 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[18] |IMMLDEN2 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[19] |IMMLDEN3 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[20] |IMMLDEN4 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[21] |IMMLDEN5 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect) + * | | |If counter halt is enabled, BPWM all counters will keep current value until exit ICE debug mode. + * | | |0 = ICE debug mode counter halt Disabled. + * | | |1 = ICE debug mode counter halt Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable (Write Protect) + * | | |0 = ICE debug mode acknowledgement effects BPWM output. + * | | |BPWM pin will be forced as tri-state while ICE debug mode acknowledged. + * | | |1 = ICE debug mode acknowledgement Disabled. + * | | |BPWM pin will keep output no matter ICE debug mode acknowledged or not. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * @var BPWM_T::CTL1 + * Offset: 0x04 BPWM Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CNTTYPE0 |BPWM Counter Behavior Type 0 + * | | |Each bit n controls corresponding BPWM channel n. + * | | |00 = Up counter type (supports in capture mode). + * | | |01 = Down count type (supports in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * @var BPWM_T::CLKSRC + * Offset: 0x10 BPWM Clock Source Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |ECLKSRC0 |BPWM_CH01 External Clock Source Select + * | | |000 = BPWMx_CLK, x denotes 0 or 1. + * | | |001 = TIMER0 overflow. + * | | |010 = TIMER1 overflow. + * | | |011 = TIMER2 overflow. + * | | |100 = TIMER3 overflow. + * | | |Others = Reserved. + * @var BPWM_T::CLKPSC + * Offset: 0x14 BPWM Clock Prescale Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CLKPSC |BPWM Counter Clock Prescale + * | | |The clock of BPWM counter is decided by clock prescaler + * | | |Each BPWM pair share one BPWM counter clock prescaler + * | | |The clock of BPWM counter is divided by (CLKPSC+ 1) + * @var BPWM_T::CNTEN + * Offset: 0x20 BPWM Counter Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTEN0 |BPWM Counter 0 Enable Bit + * | | |0 = BPWM Counter and clock prescaler stop running. + * | | |1 = BPWM Counter and clock prescaler start running. + * @var BPWM_T::CNTCLR + * Offset: 0x24 BPWM Clear Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTCLR0 |Clear BPWM Counter Control Bit 0 + * | | |It is automatically cleared by hardware. + * | | |0 = No effect. + * | | |1 = Clear 16-bit BPWM counter to 0000H. + * @var BPWM_T::PERIOD + * Offset: 0x30 BPWM Period Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PERIOD |BPWM Period Register + * | | |Up-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, and restarts from 0. + * | | |Down-Count mode: In this mode, BPWM counter counts from PERIOD to 0, and restarts from PERIOD. + * | | |BPWM period time = (PERIOD+1) * BPWM_CLK period. + * | | |Up-Down-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. + * | | |BPWM period time = 2 * PERIOD * BPWM_CLK period. + * @var BPWM_T::CMPDAT[6] + * Offset: 0x50 BPWM Comparator Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMPDAT |BPWM Comparator Register + * | | |CMPDAT use to compare with CNTR to generate BPWM waveform, interrupt and trigger EADC. + * | | |In independent mode, CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point. + * @var BPWM_T::CNT + * Offset: 0x90 BPWM Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CNT |BPWM Data Register (Read Only) + * | | |User can monitor CNTR to know the current value in 16-bit period counter. + * |[16] |DIRF |BPWM Direction Indicator Flag (Read Only) + * | | |0 = Counter is Down count. + * | | |1 = Counter is UP count. + * @var BPWM_T::WGCTL0 + * Offset: 0xB0 BPWM Generation Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |ZPCTL0 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[3:2] |ZPCTL1 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[5:4] |ZPCTL2 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[7:6] |ZPCTL3 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[9:8] |ZPCTL4 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[11:10] |ZPCTL5 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[17:16] |PRDPCTL0 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * |[19:18] |PRDPCTL1 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * |[21:20] |PRDPCTL2 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * |[23:22] |PRDPCTL3 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * |[25:24] |PRDPCTL4 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * |[27:26] |PRDPCTL5 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * @var BPWM_T::WGCTL1 + * Offset: 0xB4 BPWM Generation Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CMPUCTL0 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[3:2] |CMPUCTL1 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[5:4] |CMPUCTL2 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[7:6] |CMPUCTL3 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[9:8] |CMPUCTL4 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[11:10] |CMPUCTL5 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[17:16] |CMPDCTL0 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * |[19:18] |CMPDCTL1 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * |[21:20] |CMPDCTL2 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * |[23:22] |CMPDCTL3 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * |[25:24] |CMPDCTL4 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * |[27:26] |CMPDCTL5 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * @var BPWM_T::MSKEN + * Offset: 0xB8 BPWM Mask Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKEN0 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * |[1] |MSKEN1 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * |[2] |MSKEN2 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * |[3] |MSKEN3 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * |[4] |MSKEN4 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * |[5] |MSKEN5 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * @var BPWM_T::MSK + * Offset: 0xBC BPWM Mask Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKDAT0 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * |[1] |MSKDAT1 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * |[2] |MSKDAT2 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * |[3] |MSKDAT3 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * |[4] |MSKDAT4 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * |[5] |MSKDAT5 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * @var BPWM_T::POLCTL + * Offset: 0xD4 BPWM Pin Polar Inverse Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PINV0 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * |[1] |PINV1 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * |[2] |PINV2 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * |[3] |PINV3 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * |[4] |PINV4 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * |[5] |PINV5 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * @var BPWM_T::POEN + * Offset: 0xD8 BPWM Output Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |POEN0 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * |[1] |POEN1 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * |[2] |POEN2 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * |[3] |POEN3 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * |[4] |POEN4 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * |[5] |POEN5 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * @var BPWM_T::INTEN + * Offset: 0xE0 BPWM Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIEN0 |BPWM Zero Point Interrupt 0 Enable Bit + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * |[8] |PIEN0 |BPWM Period Point Interrupt 0 Enable Bit + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note: When up-down counter type period point means center point. + * |[16] |CMPUIEN0 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[17] |CMPUIEN1 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[18] |CMPUIEN2 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[19] |CMPUIEN3 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[20] |CMPUIEN4 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[21] |CMPUIEN5 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[24] |CMPDIEN0 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * |[25] |CMPDIEN1 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * |[26] |CMPDIEN2 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * |[27] |CMPDIEN3 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * |[28] |CMPDIEN4 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * |[29] |CMPDIEN5 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * @var BPWM_T::INTSTS + * Offset: 0xE8 BPWM Interrupt Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIF0 |BPWM Zero Point Interrupt Flag 0 + * | | |This bit is set by hardware when BPWM_CH0 counter reaches zero, software can write 1 to clear this bit to zero. + * |[8] |PIF0 |BPWM Period Point Interrupt Flag 0 + * | | |This bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0, software can write 1 to clear this bit to zero. + * |[16] |CMPUIF0 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[17] |CMPUIF1 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[18] |CMPUIF2 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[19] |CMPUIF3 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[20] |CMPUIF4 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[21] |CMPUIF5 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[24] |CMPDIF0 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * |[25] |CMPDIF1 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * |[26] |CMPDIF2 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * |[27] |CMPDIF3 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * |[28] |CMPDIF4 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * |[29] |CMPDIF5 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * @var BPWM_T::EADCTS0 + * Offset: 0xF8 BPWM Trigger EADC Source Select Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |TRGSEL0 |BPWM_CH0 Trigger EADC Source Select + * | | |0000 = BPWM_CH0 zero point. + * | | |0001 = BPWM_CH0 period point. + * | | |0010 = BPWM_CH0 zero or period point. + * | | |0011 = BPWM_CH0 up-count CMPDAT point. + * | | |0100 = BPWM_CH0 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH1 up-count CMPDAT point. + * | | |1001 = BPWM_CH1 down-count CMPDAT point. + * | | |Others reserved + * |[7] |TRGEN0 |BPWM_CH0 Trigger EADC Enable Bit + * |[11:8] |TRGSEL1 |BPWM_CH1 Trigger EADC Source Select + * | | |0000 = BPWM_CH0 zero point. + * | | |0001 = BPWM_CH0 period point. + * | | |0010 = BPWM_CH0 zero or period point. + * | | |0011 = BPWM_CH0 up-count CMPDAT point. + * | | |0100 = BPWM_CH0 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH1 up-count CMPDAT point. + * | | |1001 = BPWM_CH1 down-count CMPDAT point. + * | | |Others reserved + * |[15] |TRGEN1 |BPWM_CH1 Trigger EADC Enable Bit + * |[19:16] |TRGSEL2 |BPWM_CH2 Trigger EADC Source Select + * | | |0000 = BPWM_CH2 zero point. + * | | |0001 = BPWM_CH2 period point. + * | | |0010 = BPWM_CH2 zero or period point. + * | | |0011 = BPWM_CH2 up-count CMPDAT point. + * | | |0100 = BPWM_CH2 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH3 up-count CMPDAT point. + * | | |1001 = BPWM_CH3 down-count CMPDAT point. + * | | |Others reserved + * |[23] |TRGEN2 |BPWM_CH2 Trigger EADC Enable Bit + * |[27:24] |TRGSEL3 |BPWM_CH3 Trigger EADC Source Select + * | | |0000 = BPWM_CH2 zero point. + * | | |0001 = BPWM_CH2 period point. + * | | |0010 = BPWM_CH2 zero or period point. + * | | |0011 = BPWM_CH2 up-count CMPDAT point. + * | | |0100 = BPWM_CH2 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH3 up-count CMPDAT point. + * | | |1001 = BPWM_CH3 down-count CMPDAT point. + * | | |Others reserved. + * |[31] |TRGEN3 |BPWM_CH3 Trigger EADC Enable Bit + * @var BPWM_T::EADCTS1 + * Offset: 0xFC BPWM Trigger EADC Source Select Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |TRGSEL4 |BPWM_CH4 Trigger EADC Source Select + * | | |0000 = BPWM_CH4 zero point. + * | | |0001 = BPWM_CH4 period point. + * | | |0010 = BPWM_CH4 zero or period point. + * | | |0011 = BPWM_CH4 up-count CMPDAT point. + * | | |0100 = BPWM_CH4 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH5 up-count CMPDAT point. + * | | |1001 = BPWM_CH5 down-count CMPDAT point. + * | | |Others reserved + * |[7] |TRGEN4 |BPWM_CH4 Trigger EADC Enable Bit + * |[11:8] |TRGSEL5 |BPWM_CH5 Trigger EADC Source Select + * | | |0000 = BPWM_CH4 zero point. + * | | |0001 = BPWM_CH4 period point. + * | | |0010 = BPWM_CH4 zero or period point. + * | | |0011 = BPWM_CH4 up-count CMPDAT point. + * | | |0100 = BPWM_CH4 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH5 up-count CMPDAT point. + * | | |1001 = BPWM_CH5 down-count CMPDAT point. + * | | |Others reserved + * |[15] |TRGEN5 |BPWM_CH5 Trigger EADC Enable Bit + * @var BPWM_T::SSCTL + * Offset: 0x110 BPWM Synchronous Start Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SSEN0 |BPWM Synchronous Start Function 0 Enable Bit + * | | |When synchronous start function is enabled, the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN). + * | | |0 = BPWM synchronous start function Disabled. + * | | |1 = BPWM synchronous start function Enabled. + * |[9:8] |SSRC |BPWM Synchronous Start Source Select + * | | |00 = Synchronous start source come from PWM0. + * | | |01 = Synchronous start source come from PWM1. + * | | |10 = Synchronous start source come from BPWM0. + * | | |11 = Synchronous start source come from BPWM1. + * @var BPWM_T::SSTRG + * Offset: 0x114 BPWM Synchronous Start Trigger Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTSEN |BPWM Counter Synchronous Start Enable Bit(Write Only) + * | | |BPMW counter synchronous enable function is used to make PWM or BPWM channels start counting at the same time. + * | | |Writing this bit to 1 will also set the counter enable bit if correlated BPWM channel counter synchronous start function is enabled. + * @var BPWM_T::STATUS + * Offset: 0x120 BPWM Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTMAX0 |Time-base Counter 0 Equal to 0xFFFF Latched Status + * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. + * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. + * |[16] |EADCTRG0 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[17] |EADCTRG1 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[18] |EADCTRG2 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[19] |EADCTRG3 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[20] |EADCTRG4 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[21] |EADCTRG5 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * @var BPWM_T::CAPINEN + * Offset: 0x200 BPWM Capture Input Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPINEN0 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * |[1] |CAPINEN1 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * |[2] |CAPINEN2 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * |[3] |CAPINEN3 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * |[4] |CAPINEN4 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * |[5] |CAPINEN5 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * @var BPWM_T::CAPCTL + * Offset: 0x204 BPWM Capture Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPEN0 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[1] |CAPEN1 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[2] |CAPEN2 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[3] |CAPEN3 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[4] |CAPEN4 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[5] |CAPEN5 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[8] |CAPINV0 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[9] |CAPINV1 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[10] |CAPINV2 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[11] |CAPINV3 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[12] |CAPINV4 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[13] |CAPINV5 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[16] |RCRLDEN0 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[17] |RCRLDEN1 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[18] |RCRLDEN2 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[19] |RCRLDEN3 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[20] |RCRLDEN4 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[21] |RCRLDEN5 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[24] |FCRLDEN0 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[25] |FCRLDEN1 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[26] |FCRLDEN2 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[27] |FCRLDEN3 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[28] |FCRLDEN4 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[29] |FCRLDEN5 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * @var BPWM_T::CAPSTS + * Offset: 0x208 BPWM Capture Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CRIFOV0 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[1] |CRIFOV1 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[2] |CRIFOV2 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[3] |CRIFOV3 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[4] |CRIFOV4 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[5] |CRIFOV5 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[8] |CFIFOV0 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * |[9] |CFIFOV1 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * |[10] |CFIFOV2 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * |[11] |CFIFOV3 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * |[12] |CFIFOV4 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * |[13] |CFIFOV5 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * @var BPWM_T::CAPIEN + * Offset: 0x250 BPWM Capture Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |CAPRIENn |BPWM Capture Rising Latch Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[13:8] |CAPFIENn |BPWM Capture Falling Latch Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * @var BPWM_T::CAPIF + * Offset: 0x254 BPWM Capture Interrupt Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPRIF0 |BPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * |[1] |CAPRIF1 |BPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * |[2] |CAPRIF2 |BPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * |[3] |CAPRIF3 |BPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * |[4] |CAPRIF4 |BPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * |[5] |CAPRIF5 |BPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * |[8] |CAPFIF0 |BPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * |[9] |CAPFIF1 |BPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * |[10] |CAPFIF2 |BPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * |[11] |CAPFIF3 |BPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * |[12] |CAPFIF4 |BPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * |[13] |CAPFIF5 |BPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * @var BPWM_T::PBUF + * Offset: 0x304 BPWM PERIOD Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PBUF |BPWM Period Buffer (Read Only) + * | | |Used as PERIOD active register. + * @var BPWM_T::CMPBUF[6] + * Offset: 0x31C BPWM CMPDAT 0~5 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMPBUF |BPWM Comparator Buffer (Read Only) + * | | |Used as CMP active register. + */ + __IO uint32_t CTL0; /*!< [0x0000] BPWM Control Register 0 */ + __IO uint32_t CTL1; /*!< [0x0004] BPWM Control Register 1 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CLKSRC; /*!< [0x0010] BPWM Clock Source Register */ + __IO uint32_t CLKPSC; /*!< [0x0014] BPWM Clock Prescale Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CNTEN; /*!< [0x0020] BPWM Counter Enable Register */ + __IO uint32_t CNTCLR; /*!< [0x0024] BPWM Clear Counter Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t PERIOD; /*!< [0x0030] BPWM Period Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[7]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CMPDAT[6]; /*!< [0x0050] BPWM Comparator Register 0~5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE4[10]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t CNT; /*!< [0x0090] BPWM Counter Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE5[7]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t WGCTL0; /*!< [0x00b0] BPWM Generation Register 0 */ + __IO uint32_t WGCTL1; /*!< [0x00b4] BPWM Generation Register 1 */ + __IO uint32_t MSKEN; /*!< [0x00b8] BPWM Mask Enable Register */ + __IO uint32_t MSK; /*!< [0x00bc] BPWM Mask Data Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE6[5]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t POLCTL; /*!< [0x00d4] BPWM Pin Polar Inverse Register */ + __IO uint32_t POEN; /*!< [0x00d8] BPWM Output Enable Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE7[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t INTEN; /*!< [0x00e0] BPWM Interrupt Enable Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE8[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t INTSTS; /*!< [0x00e8] BPWM Interrupt Flag Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE9[3]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t EADCTS0; /*!< [0x00f8] BPWM Trigger EADC Source Select Register 0 */ + __IO uint32_t EADCTS1; /*!< [0x00fc] BPWM Trigger EADC Source Select Register 1 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE10[4]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t SSCTL; /*!< [0x0110] BPWM Synchronous Start Control Register */ + __O uint32_t SSTRG; /*!< [0x0114] BPWM Synchronous Start Trigger Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE11[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t STATUS; /*!< [0x0120] BPWM Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE12[55]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CAPINEN; /*!< [0x0200] BPWM Capture Input Enable Register */ + __IO uint32_t CAPCTL; /*!< [0x0204] BPWM Capture Control Register */ + __I uint32_t CAPSTS; /*!< [0x0208] BPWM Capture Status Register */ + BCAPDAT_T CAPDAT[6]; /*!< [0x020C] BPWM Rising and Falling Capture Data Register 0~5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE13[5]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CAPIEN; /*!< [0x0250] BPWM Capture Interrupt Enable Register */ + __IO uint32_t CAPIF; /*!< [0x0254] BPWM Capture Interrupt Flag Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE14[43]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t PBUF; /*!< [0x0304] BPWM PERIOD Buffer */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE15[5]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t CMPBUF[6]; /*!< [0x031c] BPWM CMPDAT 0~5 Buffer */ + +} BPWM_T; + +/** + @addtogroup BPWM_CONST BPWM Bit Field Definition + Constant Definitions for BPWM Controller +@{ */ + +#define BPWM_CTL0_CTRLD0_Pos (0) /*!< BPWM_T::CTL0: CTRLD0 Position */ +#define BPWM_CTL0_CTRLD0_Msk (0x1ul << BPWM_CTL0_CTRLD0_Pos) /*!< BPWM_T::CTL0: CTRLD0 Mask */ + +#define BPWM_CTL0_CTRLD1_Pos (1) /*!< BPWM_T::CTL0: CTRLD1 Position */ +#define BPWM_CTL0_CTRLD1_Msk (0x1ul << BPWM_CTL0_CTRLD1_Pos) /*!< BPWM_T::CTL0: CTRLD1 Mask */ + +#define BPWM_CTL0_CTRLD2_Pos (2) /*!< BPWM_T::CTL0: CTRLD2 Position */ +#define BPWM_CTL0_CTRLD2_Msk (0x1ul << BPWM_CTL0_CTRLD2_Pos) /*!< BPWM_T::CTL0: CTRLD2 Mask */ + +#define BPWM_CTL0_CTRLD3_Pos (3) /*!< BPWM_T::CTL0: CTRLD3 Position */ +#define BPWM_CTL0_CTRLD3_Msk (0x1ul << BPWM_CTL0_CTRLD3_Pos) /*!< BPWM_T::CTL0: CTRLD3 Mask */ + +#define BPWM_CTL0_CTRLD4_Pos (4) /*!< BPWM_T::CTL0: CTRLD4 Position */ +#define BPWM_CTL0_CTRLD4_Msk (0x1ul << BPWM_CTL0_CTRLD4_Pos) /*!< BPWM_T::CTL0: CTRLD4 Mask */ + +#define BPWM_CTL0_CTRLD5_Pos (5) /*!< BPWM_T::CTL0: CTRLD5 Position */ +#define BPWM_CTL0_CTRLD5_Msk (0x1ul << BPWM_CTL0_CTRLD5_Pos) /*!< BPWM_T::CTL0: CTRLD5 Mask */ + +#define BPWM_CTL0_IMMLDEN0_Pos (16) /*!< BPWM_T::CTL0: IMMLDEN0 Position */ +#define BPWM_CTL0_IMMLDEN0_Msk (0x1ul << BPWM_CTL0_IMMLDEN0_Pos) /*!< BPWM_T::CTL0: IMMLDEN0 Mask */ + +#define BPWM_CTL0_IMMLDEN1_Pos (17) /*!< BPWM_T::CTL0: IMMLDEN1 Position */ +#define BPWM_CTL0_IMMLDEN1_Msk (0x1ul << BPWM_CTL0_IMMLDEN1_Pos) /*!< BPWM_T::CTL0: IMMLDEN1 Mask */ + +#define BPWM_CTL0_IMMLDEN2_Pos (18) /*!< BPWM_T::CTL0: IMMLDEN2 Position */ +#define BPWM_CTL0_IMMLDEN2_Msk (0x1ul << BPWM_CTL0_IMMLDEN2_Pos) /*!< BPWM_T::CTL0: IMMLDEN2 Mask */ + +#define BPWM_CTL0_IMMLDEN3_Pos (19) /*!< BPWM_T::CTL0: IMMLDEN3 Position */ +#define BPWM_CTL0_IMMLDEN3_Msk (0x1ul << BPWM_CTL0_IMMLDEN3_Pos) /*!< BPWM_T::CTL0: IMMLDEN3 Mask */ + +#define BPWM_CTL0_IMMLDEN4_Pos (20) /*!< BPWM_T::CTL0: IMMLDEN4 Position */ +#define BPWM_CTL0_IMMLDEN4_Msk (0x1ul << BPWM_CTL0_IMMLDEN4_Pos) /*!< BPWM_T::CTL0: IMMLDEN4 Mask */ + +#define BPWM_CTL0_IMMLDEN5_Pos (21) /*!< BPWM_T::CTL0: IMMLDEN5 Position */ +#define BPWM_CTL0_IMMLDEN5_Msk (0x1ul << BPWM_CTL0_IMMLDEN5_Pos) /*!< BPWM_T::CTL0: IMMLDEN5 Mask */ + +#define BPWM_CTL0_DBGHALT_Pos (30) /*!< BPWM_T::CTL0: DBGHALT Position */ +#define BPWM_CTL0_DBGHALT_Msk (0x1ul << BPWM_CTL0_DBGHALT_Pos) /*!< BPWM_T::CTL0: DBGHALT Mask */ + +#define BPWM_CTL0_DBGTRIOFF_Pos (31) /*!< BPWM_T::CTL0: DBGTRIOFF Position */ +#define BPWM_CTL0_DBGTRIOFF_Msk (0x1ul << BPWM_CTL0_DBGTRIOFF_Pos) /*!< BPWM_T::CTL0: DBGTRIOFF Mask */ + +#define BPWM_CTL1_CNTTYPE0_Pos (0) /*!< BPWM_T::CTL1: CNTTYPE0 Position */ +#define BPWM_CTL1_CNTTYPE0_Msk (0x3ul << BPWM_CTL1_CNTTYPE0_Pos) /*!< BPWM_T::CTL1: CNTTYPE0 Mask */ + +#define BPWM_CLKSRC_ECLKSRC0_Pos (0) /*!< BPWM_T::CLKSRC: ECLKSRC0 Position */ +#define BPWM_CLKSRC_ECLKSRC0_Msk (0x7ul << BPWM_CLKSRC_ECLKSRC0_Pos) /*!< BPWM_T::CLKSRC: ECLKSRC0 Mask */ + +#define BPWM_CLKPSC_CLKPSC_Pos (0) /*!< BPWM_T::CLKPSC: CLKPSC Position */ +#define BPWM_CLKPSC_CLKPSC_Msk (0xffful << BPWM_CLKPSC_CLKPSC_Pos) /*!< BPWM_T::CLKPSC: CLKPSC Mask */ + +#define BPWM_CNTEN_CNTEN0_Pos (0) /*!< BPWM_T::CNTEN: CNTEN0 Position */ +#define BPWM_CNTEN_CNTEN0_Msk (0x1ul << BPWM_CNTEN_CNTEN0_Pos) /*!< BPWM_T::CNTEN: CNTEN0 Mask */ + +#define BPWM_CNTCLR_CNTCLR0_Pos (0) /*!< BPWM_T::CNTCLR: CNTCLR0 Position */ +#define BPWM_CNTCLR_CNTCLR0_Msk (0x1ul << BPWM_CNTCLR_CNTCLR0_Pos) /*!< BPWM_T::CNTCLR: CNTCLR0 Mask */ + +#define BPWM_PERIOD_PERIOD_Pos (0) /*!< BPWM_T::PERIOD: PERIOD Position */ +#define BPWM_PERIOD_PERIOD_Msk (0xfffful << BPWM_PERIOD_PERIOD_Pos) /*!< BPWM_T::PERIOD: PERIOD Mask */ + +#define BPWM_CMPDAT0_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT0: CMPDAT Position */ +#define BPWM_CMPDAT0_CMPDAT_Msk (0xfffful << BPWM_CMPDAT0_CMPDAT_Pos) /*!< BPWM_T::CMPDAT0: CMPDAT Mask */ + +#define BPWM_CMPDAT1_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT1: CMPDAT Position */ +#define BPWM_CMPDAT1_CMPDAT_Msk (0xfffful << BPWM_CMPDAT1_CMPDAT_Pos) /*!< BPWM_T::CMPDAT1: CMPDAT Mask */ + +#define BPWM_CMPDAT2_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT2: CMPDAT Position */ +#define BPWM_CMPDAT2_CMPDAT_Msk (0xfffful << BPWM_CMPDAT2_CMPDAT_Pos) /*!< BPWM_T::CMPDAT2: CMPDAT Mask */ + +#define BPWM_CMPDAT3_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT3: CMPDAT Position */ +#define BPWM_CMPDAT3_CMPDAT_Msk (0xfffful << BPWM_CMPDAT3_CMPDAT_Pos) /*!< BPWM_T::CMPDAT3: CMPDAT Mask */ + +#define BPWM_CMPDAT4_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT4: CMPDAT Position */ +#define BPWM_CMPDAT4_CMPDAT_Msk (0xfffful << BPWM_CMPDAT4_CMPDAT_Pos) /*!< BPWM_T::CMPDAT4: CMPDAT Mask */ + +#define BPWM_CMPDAT5_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT5: CMPDAT Position */ +#define BPWM_CMPDAT5_CMPDAT_Msk (0xfffful << BPWM_CMPDAT5_CMPDAT_Pos) /*!< BPWM_T::CMPDAT5: CMPDAT Mask */ + +#define BPWM_CNT_CNT_Pos (0) /*!< BPWM_T::CNT: CNT Position */ +#define BPWM_CNT_CNT_Msk (0xfffful << BPWM_CNT_CNT_Pos) /*!< BPWM_T::CNT: CNT Mask */ + +#define BPWM_CNT_DIRF_Pos (16) /*!< BPWM_T::CNT: DIRF Position */ +#define BPWM_CNT_DIRF_Msk (0x1ul << BPWM_CNT_DIRF_Pos) /*!< BPWM_T::CNT: DIRF Mask */ + +#define BPWM_WGCTL0_ZPCTL0_Pos (0) /*!< BPWM_T::WGCTL0: ZPCTL0 Position */ +#define BPWM_WGCTL0_ZPCTL0_Msk (0x3ul << BPWM_WGCTL0_ZPCTL0_Pos) /*!< BPWM_T::WGCTL0: ZPCTL0 Mask */ + +#define BPWM_WGCTL0_ZPCTL1_Pos (2) /*!< BPWM_T::WGCTL0: ZPCTL1 Position */ +#define BPWM_WGCTL0_ZPCTL1_Msk (0x3ul << BPWM_WGCTL0_ZPCTL1_Pos) /*!< BPWM_T::WGCTL0: ZPCTL1 Mask */ + +#define BPWM_WGCTL0_ZPCTL2_Pos (4) /*!< BPWM_T::WGCTL0: ZPCTL2 Position */ +#define BPWM_WGCTL0_ZPCTL2_Msk (0x3ul << BPWM_WGCTL0_ZPCTL2_Pos) /*!< BPWM_T::WGCTL0: ZPCTL2 Mask */ + +#define BPWM_WGCTL0_ZPCTL3_Pos (6) /*!< BPWM_T::WGCTL0: ZPCTL3 Position */ +#define BPWM_WGCTL0_ZPCTL3_Msk (0x3ul << BPWM_WGCTL0_ZPCTL3_Pos) /*!< BPWM_T::WGCTL0: ZPCTL3 Mask */ + +#define BPWM_WGCTL0_ZPCTL4_Pos (8) /*!< BPWM_T::WGCTL0: ZPCTL4 Position */ +#define BPWM_WGCTL0_ZPCTL4_Msk (0x3ul << BPWM_WGCTL0_ZPCTL4_Pos) /*!< BPWM_T::WGCTL0: ZPCTL4 Mask */ + +#define BPWM_WGCTL0_ZPCTL5_Pos (10) /*!< BPWM_T::WGCTL0: ZPCTL5 Position */ +#define BPWM_WGCTL0_ZPCTL5_Msk (0x3ul << BPWM_WGCTL0_ZPCTL5_Pos) /*!< BPWM_T::WGCTL0: ZPCTL5 Mask */ + +#define BPWM_WGCTL0_ZPCTLn_Pos (0) /*!< BPWM_T::WGCTL0: ZPCTLn Position */ +#define BPWM_WGCTL0_ZPCTLn_Msk (0xffful << BPWM_WGCTL0_ZPCTLn_Pos) /*!< BPWM_T::WGCTL0: ZPCTLn Mask */ + +#define BPWM_WGCTL0_PRDPCTL0_Pos (16) /*!< BPWM_T::WGCTL0: PRDPCTL0 Position */ +#define BPWM_WGCTL0_PRDPCTL0_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL0_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL0 Mask */ + +#define BPWM_WGCTL0_PRDPCTL1_Pos (18) /*!< BPWM_T::WGCTL0: PRDPCTL1 Position */ +#define BPWM_WGCTL0_PRDPCTL1_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL1_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL1 Mask */ + +#define BPWM_WGCTL0_PRDPCTL2_Pos (20) /*!< BPWM_T::WGCTL0: PRDPCTL2 Position */ +#define BPWM_WGCTL0_PRDPCTL2_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL2_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL2 Mask */ + +#define BPWM_WGCTL0_PRDPCTL3_Pos (22) /*!< BPWM_T::WGCTL0: PRDPCTL3 Position */ +#define BPWM_WGCTL0_PRDPCTL3_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL3_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL3 Mask */ + +#define BPWM_WGCTL0_PRDPCTL4_Pos (24) /*!< BPWM_T::WGCTL0: PRDPCTL4 Position */ +#define BPWM_WGCTL0_PRDPCTL4_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL4_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL4 Mask */ + +#define BPWM_WGCTL0_PRDPCTL5_Pos (26) /*!< BPWM_T::WGCTL0: PRDPCTL5 Position */ +#define BPWM_WGCTL0_PRDPCTL5_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL5_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL5 Mask */ + +#define BPWM_WGCTL0_PRDPCTLn_Pos (16) /*!< BPWM_T::WGCTL0: PRDPCTLn Position */ +#define BPWM_WGCTL0_PRDPCTLn_Msk (0xffful << BPWM_WGCTL0_PRDPCTLn_Pos) /*!< BPWM_T::WGCTL0: PRDPCTLn Mask */ + +#define BPWM_WGCTL1_CMPUCTL0_Pos (0) /*!< BPWM_T::WGCTL1: CMPUCTL0 Position */ +#define BPWM_WGCTL1_CMPUCTL0_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL0_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL0 Mask */ + +#define BPWM_WGCTL1_CMPUCTL1_Pos (2) /*!< BPWM_T::WGCTL1: CMPUCTL1 Position */ +#define BPWM_WGCTL1_CMPUCTL1_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL1_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL1 Mask */ + +#define BPWM_WGCTL1_CMPUCTL2_Pos (4) /*!< BPWM_T::WGCTL1: CMPUCTL2 Position */ +#define BPWM_WGCTL1_CMPUCTL2_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL2_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL2 Mask */ + +#define BPWM_WGCTL1_CMPUCTL3_Pos (6) /*!< BPWM_T::WGCTL1: CMPUCTL3 Position */ +#define BPWM_WGCTL1_CMPUCTL3_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL3_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL3 Mask */ + +#define BPWM_WGCTL1_CMPUCTL4_Pos (8) /*!< BPWM_T::WGCTL1: CMPUCTL4 Position */ +#define BPWM_WGCTL1_CMPUCTL4_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL4_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL4 Mask */ + +#define BPWM_WGCTL1_CMPUCTL5_Pos (10) /*!< BPWM_T::WGCTL1: CMPUCTL5 Position */ +#define BPWM_WGCTL1_CMPUCTL5_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL5_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL5 Mask */ + +#define BPWM_WGCTL1_CMPUCTLn_Pos (0) /*!< BPWM_T::WGCTL1: CMPUCTLn Position */ +#define BPWM_WGCTL1_CMPUCTLn_Msk (0xffful << BPWM_WGCTL1_CMPUCTLn_Pos) /*!< BPWM_T::WGCTL1: CMPUCTLn Mask */ + +#define BPWM_WGCTL1_CMPDCTL0_Pos (16) /*!< BPWM_T::WGCTL1: CMPDCTL0 Position */ +#define BPWM_WGCTL1_CMPDCTL0_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL0_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL0 Mask */ + +#define BPWM_WGCTL1_CMPDCTL1_Pos (18) /*!< BPWM_T::WGCTL1: CMPDCTL1 Position */ +#define BPWM_WGCTL1_CMPDCTL1_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL1_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL1 Mask */ + +#define BPWM_WGCTL1_CMPDCTL2_Pos (20) /*!< BPWM_T::WGCTL1: CMPDCTL2 Position */ +#define BPWM_WGCTL1_CMPDCTL2_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL2_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL2 Mask */ + +#define BPWM_WGCTL1_CMPDCTL3_Pos (22) /*!< BPWM_T::WGCTL1: CMPDCTL3 Position */ +#define BPWM_WGCTL1_CMPDCTL3_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL3_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL3 Mask */ + +#define BPWM_WGCTL1_CMPDCTL4_Pos (24) /*!< BPWM_T::WGCTL1: CMPDCTL4 Position */ +#define BPWM_WGCTL1_CMPDCTL4_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL4_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL4 Mask */ + +#define BPWM_WGCTL1_CMPDCTL5_Pos (26) /*!< BPWM_T::WGCTL1: CMPDCTL5 Position */ +#define BPWM_WGCTL1_CMPDCTL5_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL5_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL5 Mask */ + +#define BPWM_WGCTL1_CMPDCTLn_Pos (16) /*!< BPWM_T::WGCTL1: CMPDCTLn Position */ +#define BPWM_WGCTL1_CMPDCTLn_Msk (0xffful << BPWM_WGCTL1_CMPDCTLn_Pos) /*!< BPWM_T::WGCTL1: CMPDCTLn Mask */ + +#define BPWM_MSKEN_MSKEN0_Pos (0) /*!< BPWM_T::MSKEN: MSKEN0 Position */ +#define BPWM_MSKEN_MSKEN0_Msk (0x1ul << BPWM_MSKEN_MSKEN0_Pos) /*!< BPWM_T::MSKEN: MSKEN0 Mask */ + +#define BPWM_MSKEN_MSKEN1_Pos (1) /*!< BPWM_T::MSKEN: MSKEN1 Position */ +#define BPWM_MSKEN_MSKEN1_Msk (0x1ul << BPWM_MSKEN_MSKEN1_Pos) /*!< BPWM_T::MSKEN: MSKEN1 Mask */ + +#define BPWM_MSKEN_MSKEN2_Pos (2) /*!< BPWM_T::MSKEN: MSKEN2 Position */ +#define BPWM_MSKEN_MSKEN2_Msk (0x1ul << BPWM_MSKEN_MSKEN2_Pos) /*!< BPWM_T::MSKEN: MSKEN2 Mask */ + +#define BPWM_MSKEN_MSKEN3_Pos (3) /*!< BPWM_T::MSKEN: MSKEN3 Position */ +#define BPWM_MSKEN_MSKEN3_Msk (0x1ul << BPWM_MSKEN_MSKEN3_Pos) /*!< BPWM_T::MSKEN: MSKEN3 Mask */ + +#define BPWM_MSKEN_MSKEN4_Pos (4) /*!< BPWM_T::MSKEN: MSKEN4 Position */ +#define BPWM_MSKEN_MSKEN4_Msk (0x1ul << BPWM_MSKEN_MSKEN4_Pos) /*!< BPWM_T::MSKEN: MSKEN4 Mask */ + +#define BPWM_MSKEN_MSKEN5_Pos (5) /*!< BPWM_T::MSKEN: MSKEN5 Position */ +#define BPWM_MSKEN_MSKEN5_Msk (0x1ul << BPWM_MSKEN_MSKEN5_Pos) /*!< BPWM_T::MSKEN: MSKEN5 Mask */ + +#define BPWM_MSKEN_MSKENn_Pos (0) /*!< BPWM_T::MSKEN: MSKENn Position */ +#define BPWM_MSKEN_MSKENn_Msk (0x3ful << BPWM_MSKEN_MSKENn_Pos) /*!< BPWM_T::MSKEN: MSKENn Mask */ + +#define BPWM_MSK_MSKDAT0_Pos (0) /*!< BPWM_T::MSK: MSKDAT0 Position */ +#define BPWM_MSK_MSKDAT0_Msk (0x1ul << BPWM_MSK_MSKDAT0_Pos) /*!< BPWM_T::MSK: MSKDAT0 Mask */ + +#define BPWM_MSK_MSKDAT1_Pos (1) /*!< BPWM_T::MSK: MSKDAT1 Position */ +#define BPWM_MSK_MSKDAT1_Msk (0x1ul << BPWM_MSK_MSKDAT1_Pos) /*!< BPWM_T::MSK: MSKDAT1 Mask */ + +#define BPWM_MSK_MSKDAT2_Pos (2) /*!< BPWM_T::MSK: MSKDAT2 Position */ +#define BPWM_MSK_MSKDAT2_Msk (0x1ul << BPWM_MSK_MSKDAT2_Pos) /*!< BPWM_T::MSK: MSKDAT2 Mask */ + +#define BPWM_MSK_MSKDAT3_Pos (3) /*!< BPWM_T::MSK: MSKDAT3 Position */ +#define BPWM_MSK_MSKDAT3_Msk (0x1ul << BPWM_MSK_MSKDAT3_Pos) /*!< BPWM_T::MSK: MSKDAT3 Mask */ + +#define BPWM_MSK_MSKDAT4_Pos (4) /*!< BPWM_T::MSK: MSKDAT4 Position */ +#define BPWM_MSK_MSKDAT4_Msk (0x1ul << BPWM_MSK_MSKDAT4_Pos) /*!< BPWM_T::MSK: MSKDAT4 Mask */ + +#define BPWM_MSK_MSKDAT5_Pos (5) /*!< BPWM_T::MSK: MSKDAT5 Position */ +#define BPWM_MSK_MSKDAT5_Msk (0x1ul << BPWM_MSK_MSKDAT5_Pos) /*!< BPWM_T::MSK: MSKDAT5 Mask */ + +#define BPWM_MSK_MSKDATn_Pos (0) /*!< BPWM_T::MSK: MSKDATn Position */ +#define BPWM_MSK_MSKDATn_Msk (0x3ful << BPWM_MSK_MSKDATn_Pos) /*!< BPWM_T::MSK: MSKDATn Mask */ + +#define BPWM_POLCTL_PINV0_Pos (0) /*!< BPWM_T::POLCTL: PINV0 Position */ +#define BPWM_POLCTL_PINV0_Msk (0x1ul << BPWM_POLCTL_PINV0_Pos) /*!< BPWM_T::POLCTL: PINV0 Mask */ + +#define BPWM_POLCTL_PINV1_Pos (1) /*!< BPWM_T::POLCTL: PINV1 Position */ +#define BPWM_POLCTL_PINV1_Msk (0x1ul << BPWM_POLCTL_PINV1_Pos) /*!< BPWM_T::POLCTL: PINV1 Mask */ + +#define BPWM_POLCTL_PINV2_Pos (2) /*!< BPWM_T::POLCTL: PINV2 Position */ +#define BPWM_POLCTL_PINV2_Msk (0x1ul << BPWM_POLCTL_PINV2_Pos) /*!< BPWM_T::POLCTL: PINV2 Mask */ + +#define BPWM_POLCTL_PINV3_Pos (3) /*!< BPWM_T::POLCTL: PINV3 Position */ +#define BPWM_POLCTL_PINV3_Msk (0x1ul << BPWM_POLCTL_PINV3_Pos) /*!< BPWM_T::POLCTL: PINV3 Mask */ + +#define BPWM_POLCTL_PINV4_Pos (4) /*!< BPWM_T::POLCTL: PINV4 Position */ +#define BPWM_POLCTL_PINV4_Msk (0x1ul << BPWM_POLCTL_PINV4_Pos) /*!< BPWM_T::POLCTL: PINV4 Mask */ + +#define BPWM_POLCTL_PINV5_Pos (5) /*!< BPWM_T::POLCTL: PINV5 Position */ +#define BPWM_POLCTL_PINV5_Msk (0x1ul << BPWM_POLCTL_PINV5_Pos) /*!< BPWM_T::POLCTL: PINV5 Mask */ + +#define BPWM_POLCTL_PINVn_Pos (0) /*!< BPWM_T::POLCTL: PINVn Position */ +#define BPWM_POLCTL_PINVn_Msk (0x3ful << BPWM_POLCTL_PINVn_Pos) /*!< BPWM_T::POLCTL: PINVn Mask */ + +#define BPWM_POEN_POEN0_Pos (0) /*!< BPWM_T::POEN: POEN0 Position */ +#define BPWM_POEN_POEN0_Msk (0x1ul << BPWM_POEN_POEN0_Pos) /*!< BPWM_T::POEN: POEN0 Mask */ + +#define BPWM_POEN_POEN1_Pos (1) /*!< BPWM_T::POEN: POEN1 Position */ +#define BPWM_POEN_POEN1_Msk (0x1ul << BPWM_POEN_POEN1_Pos) /*!< BPWM_T::POEN: POEN1 Mask */ + +#define BPWM_POEN_POEN2_Pos (2) /*!< BPWM_T::POEN: POEN2 Position */ +#define BPWM_POEN_POEN2_Msk (0x1ul << BPWM_POEN_POEN2_Pos) /*!< BPWM_T::POEN: POEN2 Mask */ + +#define BPWM_POEN_POEN3_Pos (3) /*!< BPWM_T::POEN: POEN3 Position */ +#define BPWM_POEN_POEN3_Msk (0x1ul << BPWM_POEN_POEN3_Pos) /*!< BPWM_T::POEN: POEN3 Mask */ + +#define BPWM_POEN_POEN4_Pos (4) /*!< BPWM_T::POEN: POEN4 Position */ +#define BPWM_POEN_POEN4_Msk (0x1ul << BPWM_POEN_POEN4_Pos) /*!< BPWM_T::POEN: POEN4 Mask */ + +#define BPWM_POEN_POEN5_Pos (5) /*!< BPWM_T::POEN: POEN5 Position */ +#define BPWM_POEN_POEN5_Msk (0x1ul << BPWM_POEN_POEN5_Pos) /*!< BPWM_T::POEN: POEN5 Mask */ + +#define BPWM_POEN_POENn_Pos (0) /*!< BPWM_T::POEN: POENn Position */ +#define BPWM_POEN_POENn_Msk (0x3ful << BPWM_POEN_POENn_Pos) /*!< BPWM_T::POEN: POENn Mask */ + +#define BPWM_INTEN_ZIEN0_Pos (0) /*!< BPWM_T::INTEN: ZIEN0 Position */ +#define BPWM_INTEN_ZIEN0_Msk (0x1ul << BPWM_INTEN_ZIEN0_Pos) /*!< BPWM_T::INTEN: ZIEN0 Mask */ + +#define BPWM_INTEN_PIEN0_Pos (8) /*!< BPWM_T::INTEN: PIEN0 Position */ +#define BPWM_INTEN_PIEN0_Msk (0x1ul << BPWM_INTEN_PIEN0_Pos) /*!< BPWM_T::INTEN: PIEN0 Mask */ + +#define BPWM_INTEN_CMPUIEN0_Pos (16) /*!< BPWM_T::INTEN: CMPUIEN0 Position */ +#define BPWM_INTEN_CMPUIEN0_Msk (0x1ul << BPWM_INTEN_CMPUIEN0_Pos) /*!< BPWM_T::INTEN: CMPUIEN0 Mask */ + +#define BPWM_INTEN_CMPUIEN1_Pos (17) /*!< BPWM_T::INTEN: CMPUIEN1 Position */ +#define BPWM_INTEN_CMPUIEN1_Msk (0x1ul << BPWM_INTEN_CMPUIEN1_Pos) /*!< BPWM_T::INTEN: CMPUIEN1 Mask */ + +#define BPWM_INTEN_CMPUIEN2_Pos (18) /*!< BPWM_T::INTEN: CMPUIEN2 Position */ +#define BPWM_INTEN_CMPUIEN2_Msk (0x1ul << BPWM_INTEN_CMPUIEN2_Pos) /*!< BPWM_T::INTEN: CMPUIEN2 Mask */ + +#define BPWM_INTEN_CMPUIEN3_Pos (19) /*!< BPWM_T::INTEN: CMPUIEN3 Position */ +#define BPWM_INTEN_CMPUIEN3_Msk (0x1ul << BPWM_INTEN_CMPUIEN3_Pos) /*!< BPWM_T::INTEN: CMPUIEN3 Mask */ + +#define BPWM_INTEN_CMPUIEN4_Pos (20) /*!< BPWM_T::INTEN: CMPUIEN4 Position */ +#define BPWM_INTEN_CMPUIEN4_Msk (0x1ul << BPWM_INTEN_CMPUIEN4_Pos) /*!< BPWM_T::INTEN: CMPUIEN4 Mask */ + +#define BPWM_INTEN_CMPUIEN5_Pos (21) /*!< BPWM_T::INTEN: CMPUIEN5 Position */ +#define BPWM_INTEN_CMPUIEN5_Msk (0x1ul << BPWM_INTEN_CMPUIEN5_Pos) /*!< BPWM_T::INTEN: CMPUIEN5 Mask */ + +#define BPWM_INTEN_CMPUIENn_Pos (16) /*!< BPWM_T::INTEN: CMPUIENn Position */ +#define BPWM_INTEN_CMPUIENn_Msk (0x3ful << BPWM_INTEN_CMPUIENn_Pos) /*!< BPWM_T::INTEN: CMPUIENn Mask */ + +#define BPWM_INTEN_CMPDIEN0_Pos (24) /*!< BPWM_T::INTEN: CMPDIEN0 Position */ +#define BPWM_INTEN_CMPDIEN0_Msk (0x1ul << BPWM_INTEN_CMPDIEN0_Pos) /*!< BPWM_T::INTEN: CMPDIEN0 Mask */ + +#define BPWM_INTEN_CMPDIEN1_Pos (25) /*!< BPWM_T::INTEN: CMPDIEN1 Position */ +#define BPWM_INTEN_CMPDIEN1_Msk (0x1ul << BPWM_INTEN_CMPDIEN1_Pos) /*!< BPWM_T::INTEN: CMPDIEN1 Mask */ + +#define BPWM_INTEN_CMPDIEN2_Pos (26) /*!< BPWM_T::INTEN: CMPDIEN2 Position */ +#define BPWM_INTEN_CMPDIEN2_Msk (0x1ul << BPWM_INTEN_CMPDIEN2_Pos) /*!< BPWM_T::INTEN: CMPDIEN2 Mask */ + +#define BPWM_INTEN_CMPDIEN3_Pos (27) /*!< BPWM_T::INTEN: CMPDIEN3 Position */ +#define BPWM_INTEN_CMPDIEN3_Msk (0x1ul << BPWM_INTEN_CMPDIEN3_Pos) /*!< BPWM_T::INTEN: CMPDIEN3 Mask */ + +#define BPWM_INTEN_CMPDIEN4_Pos (28) /*!< BPWM_T::INTEN: CMPDIEN4 Position */ +#define BPWM_INTEN_CMPDIEN4_Msk (0x1ul << BPWM_INTEN_CMPDIEN4_Pos) /*!< BPWM_T::INTEN: CMPDIEN4 Mask */ + +#define BPWM_INTEN_CMPDIEN5_Pos (29) /*!< BPWM_T::INTEN: CMPDIEN5 Position */ +#define BPWM_INTEN_CMPDIEN5_Msk (0x1ul << BPWM_INTEN_CMPDIEN5_Pos) /*!< BPWM_T::INTEN: CMPDIEN5 Mask */ + +#define BPWM_INTEN_CMPDIENn_Pos (24) /*!< BPWM_T::INTEN: CMPDIENn Position */ +#define BPWM_INTEN_CMPDIENn_Msk (0x3ful << BPWM_INTEN_CMPDIENn_Pos) /*!< BPWM_T::INTEN: CMPDIENn Mask */ + +#define BPWM_INTSTS_ZIF0_Pos (0) /*!< BPWM_T::INTSTS: ZIF0 Position */ +#define BPWM_INTSTS_ZIF0_Msk (0x1ul << BPWM_INTSTS_ZIF0_Pos) /*!< BPWM_T::INTSTS: ZIF0 Mask */ + +#define BPWM_INTSTS_PIF0_Pos (8) /*!< BPWM_T::INTSTS: PIF0 Position */ +#define BPWM_INTSTS_PIF0_Msk (0x1ul << BPWM_INTSTS_PIF0_Pos) /*!< BPWM_T::INTSTS: PIF0 Mask */ + +#define BPWM_INTSTS_CMPUIF0_Pos (16) /*!< BPWM_T::INTSTS: CMPUIF0 Position */ +#define BPWM_INTSTS_CMPUIF0_Msk (0x1ul << BPWM_INTSTS_CMPUIF0_Pos) /*!< BPWM_T::INTSTS: CMPUIF0 Mask */ + +#define BPWM_INTSTS_CMPUIF1_Pos (17) /*!< BPWM_T::INTSTS: CMPUIF1 Position */ +#define BPWM_INTSTS_CMPUIF1_Msk (0x1ul << BPWM_INTSTS_CMPUIF1_Pos) /*!< BPWM_T::INTSTS: CMPUIF1 Mask */ + +#define BPWM_INTSTS_CMPUIF2_Pos (18) /*!< BPWM_T::INTSTS: CMPUIF2 Position */ +#define BPWM_INTSTS_CMPUIF2_Msk (0x1ul << BPWM_INTSTS_CMPUIF2_Pos) /*!< BPWM_T::INTSTS: CMPUIF2 Mask */ + +#define BPWM_INTSTS_CMPUIF3_Pos (19) /*!< BPWM_T::INTSTS: CMPUIF3 Position */ +#define BPWM_INTSTS_CMPUIF3_Msk (0x1ul << BPWM_INTSTS_CMPUIF3_Pos) /*!< BPWM_T::INTSTS: CMPUIF3 Mask */ + +#define BPWM_INTSTS_CMPUIF4_Pos (20) /*!< BPWM_T::INTSTS: CMPUIF4 Position */ +#define BPWM_INTSTS_CMPUIF4_Msk (0x1ul << BPWM_INTSTS_CMPUIF4_Pos) /*!< BPWM_T::INTSTS: CMPUIF4 Mask */ + +#define BPWM_INTSTS_CMPUIF5_Pos (21) /*!< BPWM_T::INTSTS: CMPUIF5 Position */ +#define BPWM_INTSTS_CMPUIF5_Msk (0x1ul << BPWM_INTSTS_CMPUIF5_Pos) /*!< BPWM_T::INTSTS: CMPUIF5 Mask */ + +#define BPWM_INTSTS_CMPUIFn_Pos (16) /*!< BPWM_T::INTSTS: CMPUIFn Position */ +#define BPWM_INTSTS_CMPUIFn_Msk (0x3ful << BPWM_INTSTS_CMPUIFn_Pos) /*!< BPWM_T::INTSTS: CMPUIFn Mask */ + +#define BPWM_INTSTS_CMPDIF0_Pos (24) /*!< BPWM_T::INTSTS: CMPDIF0 Position */ +#define BPWM_INTSTS_CMPDIF0_Msk (0x1ul << BPWM_INTSTS_CMPDIF0_Pos) /*!< BPWM_T::INTSTS: CMPDIF0 Mask */ + +#define BPWM_INTSTS_CMPDIF1_Pos (25) /*!< BPWM_T::INTSTS: CMPDIF1 Position */ +#define BPWM_INTSTS_CMPDIF1_Msk (0x1ul << BPWM_INTSTS_CMPDIF1_Pos) /*!< BPWM_T::INTSTS: CMPDIF1 Mask */ + +#define BPWM_INTSTS_CMPDIF2_Pos (26) /*!< BPWM_T::INTSTS: CMPDIF2 Position */ +#define BPWM_INTSTS_CMPDIF2_Msk (0x1ul << BPWM_INTSTS_CMPDIF2_Pos) /*!< BPWM_T::INTSTS: CMPDIF2 Mask */ + +#define BPWM_INTSTS_CMPDIF3_Pos (27) /*!< BPWM_T::INTSTS: CMPDIF3 Position */ +#define BPWM_INTSTS_CMPDIF3_Msk (0x1ul << BPWM_INTSTS_CMPDIF3_Pos) /*!< BPWM_T::INTSTS: CMPDIF3 Mask */ + +#define BPWM_INTSTS_CMPDIF4_Pos (28) /*!< BPWM_T::INTSTS: CMPDIF4 Position */ +#define BPWM_INTSTS_CMPDIF4_Msk (0x1ul << BPWM_INTSTS_CMPDIF4_Pos) /*!< BPWM_T::INTSTS: CMPDIF4 Mask */ + +#define BPWM_INTSTS_CMPDIF5_Pos (29) /*!< BPWM_T::INTSTS: CMPDIF5 Position */ +#define BPWM_INTSTS_CMPDIF5_Msk (0x1ul << BPWM_INTSTS_CMPDIF5_Pos) /*!< BPWM_T::INTSTS: CMPDIF5 Mask */ + +#define BPWM_INTSTS_CMPDIFn_Pos (24) /*!< BPWM_T::INTSTS: CMPDIFn Position */ +#define BPWM_INTSTS_CMPDIFn_Msk (0x3ful << BPWM_INTSTS_CMPDIFn_Pos) /*!< BPWM_T::INTSTS: CMPDIFn Mask */ + +#define BPWM_EADCTS0_TRGSEL0_Pos (0) /*!< BPWM_T::EADCTS0: TRGSEL0 Position */ +#define BPWM_EADCTS0_TRGSEL0_Msk (0xful << BPWM_EADCTS0_TRGSEL0_Pos) /*!< BPWM_T::EADCTS0: TRGSEL0 Mask */ + +#define BPWM_EADCTS0_TRGEN0_Pos (7) /*!< BPWM_T::EADCTS0: TRGEN0 Position */ +#define BPWM_EADCTS0_TRGEN0_Msk (0x1ul << BPWM_EADCTS0_TRGEN0_Pos) /*!< BPWM_T::EADCTS0: TRGEN0 Mask */ + +#define BPWM_EADCTS0_TRGSEL1_Pos (8) /*!< BPWM_T::EADCTS0: TRGSEL1 Position */ +#define BPWM_EADCTS0_TRGSEL1_Msk (0xful << BPWM_EADCTS0_TRGSEL1_Pos) /*!< BPWM_T::EADCTS0: TRGSEL1 Mask */ + +#define BPWM_EADCTS0_TRGEN1_Pos (15) /*!< BPWM_T::EADCTS0: TRGEN1 Position */ +#define BPWM_EADCTS0_TRGEN1_Msk (0x1ul << BPWM_EADCTS0_TRGEN1_Pos) /*!< BPWM_T::EADCTS0: TRGEN1 Mask */ + +#define BPWM_EADCTS0_TRGSEL2_Pos (16) /*!< BPWM_T::EADCTS0: TRGSEL2 Position */ +#define BPWM_EADCTS0_TRGSEL2_Msk (0xful << BPWM_EADCTS0_TRGSEL2_Pos) /*!< BPWM_T::EADCTS0: TRGSEL2 Mask */ + +#define BPWM_EADCTS0_TRGEN2_Pos (23) /*!< BPWM_T::EADCTS0: TRGEN2 Position */ +#define BPWM_EADCTS0_TRGEN2_Msk (0x1ul << BPWM_EADCTS0_TRGEN2_Pos) /*!< BPWM_T::EADCTS0: TRGEN2 Mask */ + +#define BPWM_EADCTS0_TRGSEL3_Pos (24) /*!< BPWM_T::EADCTS0: TRGSEL3 Position */ +#define BPWM_EADCTS0_TRGSEL3_Msk (0xful << BPWM_EADCTS0_TRGSEL3_Pos) /*!< BPWM_T::EADCTS0: TRGSEL3 Mask */ + +#define BPWM_EADCTS0_TRGEN3_Pos (31) /*!< BPWM_T::EADCTS0: TRGEN3 Position */ +#define BPWM_EADCTS0_TRGEN3_Msk (0x1ul << BPWM_EADCTS0_TRGEN3_Pos) /*!< BPWM_T::EADCTS0: TRGEN3 Mask */ + +#define BPWM_EADCTS1_TRGSEL4_Pos (0) /*!< BPWM_T::EADCTS1: TRGSEL4 Position */ +#define BPWM_EADCTS1_TRGSEL4_Msk (0xful << BPWM_EADCTS1_TRGSEL4_Pos) /*!< BPWM_T::EADCTS1: TRGSEL4 Mask */ + +#define BPWM_EADCTS1_TRGEN4_Pos (7) /*!< BPWM_T::EADCTS1: TRGEN4 Position */ +#define BPWM_EADCTS1_TRGEN4_Msk (0x1ul << BPWM_EADCTS1_TRGEN4_Pos) /*!< BPWM_T::EADCTS1: TRGEN4 Mask */ + +#define BPWM_EADCTS1_TRGSEL5_Pos (8) /*!< BPWM_T::EADCTS1: TRGSEL5 Position */ +#define BPWM_EADCTS1_TRGSEL5_Msk (0xful << BPWM_EADCTS1_TRGSEL5_Pos) /*!< BPWM_T::EADCTS1: TRGSEL5 Mask */ + +#define BPWM_EADCTS1_TRGEN5_Pos (15) /*!< BPWM_T::EADCTS1: TRGEN5 Position */ +#define BPWM_EADCTS1_TRGEN5_Msk (0x1ul << BPWM_EADCTS1_TRGEN5_Pos) /*!< BPWM_T::EADCTS1: TRGEN5 Mask */ + +#define BPWM_SSCTL_SSEN0_Pos (0) /*!< BPWM_T::SSCTL: SSEN0 Position */ +#define BPWM_SSCTL_SSEN0_Msk (0x1ul << BPWM_SSCTL_SSEN0_Pos) /*!< BPWM_T::SSCTL: SSEN0 Mask */ + +#define BPWM_SSCTL_SSRC_Pos (8) /*!< BPWM_T::SSCTL: SSRC Position */ +#define BPWM_SSCTL_SSRC_Msk (0x3ul << BPWM_SSCTL_SSRC_Pos) /*!< BPWM_T::SSCTL: SSRC Mask */ + +#define BPWM_SSTRG_CNTSEN_Pos (0) /*!< BPWM_T::SSTRG: CNTSEN Position */ +#define BPWM_SSTRG_CNTSEN_Msk (0x1ul << BPWM_SSTRG_CNTSEN_Pos) /*!< BPWM_T::SSTRG: CNTSEN Mask */ + +#define BPWM_STATUS_CNTMAX0_Pos (0) /*!< BPWM_T::STATUS: CNTMAX0 Position */ +#define BPWM_STATUS_CNTMAX0_Msk (0x1ul << BPWM_STATUS_CNTMAX0_Pos) /*!< BPWM_T::STATUS: CNTMAX0 Mask */ + +#define BPWM_STATUS_EADCTRG0_Pos (16) /*!< BPWM_T::STATUS: EADCTRG0 Position */ +#define BPWM_STATUS_EADCTRG0_Msk (0x1ul << BPWM_STATUS_EADCTRG0_Pos) /*!< BPWM_T::STATUS: EADCTRG0 Mask */ + +#define BPWM_STATUS_EADCTRG1_Pos (17) /*!< BPWM_T::STATUS: EADCTRG1 Position */ +#define BPWM_STATUS_EADCTRG1_Msk (0x1ul << BPWM_STATUS_EADCTRG1_Pos) /*!< BPWM_T::STATUS: EADCTRG1 Mask */ + +#define BPWM_STATUS_EADCTRG2_Pos (18) /*!< BPWM_T::STATUS: EADCTRG2 Position */ +#define BPWM_STATUS_EADCTRG2_Msk (0x1ul << BPWM_STATUS_EADCTRG2_Pos) /*!< BPWM_T::STATUS: EADCTRG2 Mask */ + +#define BPWM_STATUS_EADCTRG3_Pos (19) /*!< BPWM_T::STATUS: EADCTRG3 Position */ +#define BPWM_STATUS_EADCTRG3_Msk (0x1ul << BPWM_STATUS_EADCTRG3_Pos) /*!< BPWM_T::STATUS: EADCTRG3 Mask */ + +#define BPWM_STATUS_EADCTRG4_Pos (20) /*!< BPWM_T::STATUS: EADCTRG4 Position */ +#define BPWM_STATUS_EADCTRG4_Msk (0x1ul << BPWM_STATUS_EADCTRG4_Pos) /*!< BPWM_T::STATUS: EADCTRG4 Mask */ + +#define BPWM_STATUS_EADCTRG5_Pos (21) /*!< BPWM_T::STATUS: EADCTRG5 Position */ +#define BPWM_STATUS_EADCTRG5_Msk (0x1ul << BPWM_STATUS_EADCTRG5_Pos) /*!< BPWM_T::STATUS: EADCTRG5 Mask */ + +#define BPWM_STATUS_EADCTRGn_Pos (16) /*!< BPWM_T::STATUS: EADCTRGn Position */ +#define BPWM_STATUS_EADCTRGn_Msk (0x3ful << BPWM_STATUS_EADCTRGn_Pos) /*!< BPWM_T::STATUS: EADCTRGn Mask */ + +#define BPWM_CAPINEN_CAPINEN0_Pos (0) /*!< BPWM_T::CAPINEN: CAPINEN0 Position */ +#define BPWM_CAPINEN_CAPINEN0_Msk (0x1ul << BPWM_CAPINEN_CAPINEN0_Pos) /*!< BPWM_T::CAPINEN: CAPINEN0 Mask */ + +#define BPWM_CAPINEN_CAPINEN1_Pos (1) /*!< BPWM_T::CAPINEN: CAPINEN1 Position */ +#define BPWM_CAPINEN_CAPINEN1_Msk (0x1ul << BPWM_CAPINEN_CAPINEN1_Pos) /*!< BPWM_T::CAPINEN: CAPINEN1 Mask */ + +#define BPWM_CAPINEN_CAPINEN2_Pos (2) /*!< BPWM_T::CAPINEN: CAPINEN2 Position */ +#define BPWM_CAPINEN_CAPINEN2_Msk (0x1ul << BPWM_CAPINEN_CAPINEN2_Pos) /*!< BPWM_T::CAPINEN: CAPINEN2 Mask */ + +#define BPWM_CAPINEN_CAPINEN3_Pos (3) /*!< BPWM_T::CAPINEN: CAPINEN3 Position */ +#define BPWM_CAPINEN_CAPINEN3_Msk (0x1ul << BPWM_CAPINEN_CAPINEN3_Pos) /*!< BPWM_T::CAPINEN: CAPINEN3 Mask */ + +#define BPWM_CAPINEN_CAPINEN4_Pos (4) /*!< BPWM_T::CAPINEN: CAPINEN4 Position */ +#define BPWM_CAPINEN_CAPINEN4_Msk (0x1ul << BPWM_CAPINEN_CAPINEN4_Pos) /*!< BPWM_T::CAPINEN: CAPINEN4 Mask */ + +#define BPWM_CAPINEN_CAPINEN5_Pos (5) /*!< BPWM_T::CAPINEN: CAPINEN5 Position */ +#define BPWM_CAPINEN_CAPINEN5_Msk (0x1ul << BPWM_CAPINEN_CAPINEN5_Pos) /*!< BPWM_T::CAPINEN: CAPINEN5 Mask */ + +#define BPWM_CAPINEN_CAPINENn_Pos (0) /*!< BPWM_T::CAPINEN: CAPINENn Position */ +#define BPWM_CAPINEN_CAPINENn_Msk (0x3ful << BPWM_CAPINEN_CAPINENn_Pos) /*!< BPWM_T::CAPINEN: CAPINENn Mask */ + +#define BPWM_CAPCTL_CAPEN0_Pos (0) /*!< BPWM_T::CAPCTL: CAPEN0 Position */ +#define BPWM_CAPCTL_CAPEN0_Msk (0x1ul << BPWM_CAPCTL_CAPEN0_Pos) /*!< BPWM_T::CAPCTL: CAPEN0 Mask */ + +#define BPWM_CAPCTL_CAPEN1_Pos (1) /*!< BPWM_T::CAPCTL: CAPEN1 Position */ +#define BPWM_CAPCTL_CAPEN1_Msk (0x1ul << BPWM_CAPCTL_CAPEN1_Pos) /*!< BPWM_T::CAPCTL: CAPEN1 Mask */ + +#define BPWM_CAPCTL_CAPEN2_Pos (2) /*!< BPWM_T::CAPCTL: CAPEN2 Position */ +#define BPWM_CAPCTL_CAPEN2_Msk (0x1ul << BPWM_CAPCTL_CAPEN2_Pos) /*!< BPWM_T::CAPCTL: CAPEN2 Mask */ + +#define BPWM_CAPCTL_CAPEN3_Pos (3) /*!< BPWM_T::CAPCTL: CAPEN3 Position */ +#define BPWM_CAPCTL_CAPEN3_Msk (0x1ul << BPWM_CAPCTL_CAPEN3_Pos) /*!< BPWM_T::CAPCTL: CAPEN3 Mask */ + +#define BPWM_CAPCTL_CAPEN4_Pos (4) /*!< BPWM_T::CAPCTL: CAPEN4 Position */ +#define BPWM_CAPCTL_CAPEN4_Msk (0x1ul << BPWM_CAPCTL_CAPEN4_Pos) /*!< BPWM_T::CAPCTL: CAPEN4 Mask */ + +#define BPWM_CAPCTL_CAPEN5_Pos (5) /*!< BPWM_T::CAPCTL: CAPEN5 Position */ +#define BPWM_CAPCTL_CAPEN5_Msk (0x1ul << BPWM_CAPCTL_CAPEN5_Pos) /*!< BPWM_T::CAPCTL: CAPEN5 Mask */ + +#define BPWM_CAPCTL_CAPENn_Pos (0) /*!< BPWM_T::CAPCTL: CAPENn Position */ +#define BPWM_CAPCTL_CAPENn_Msk (0x3ful << BPWM_CAPCTL_CAPENn_Pos) /*!< BPWM_T::CAPCTL: CAPENn Mask */ + +#define BPWM_CAPCTL_CAPINV0_Pos (8) /*!< BPWM_T::CAPCTL: CAPINV0 Position */ +#define BPWM_CAPCTL_CAPINV0_Msk (0x1ul << BPWM_CAPCTL_CAPINV0_Pos) /*!< BPWM_T::CAPCTL: CAPINV0 Mask */ + +#define BPWM_CAPCTL_CAPINV1_Pos (9) /*!< BPWM_T::CAPCTL: CAPINV1 Position */ +#define BPWM_CAPCTL_CAPINV1_Msk (0x1ul << BPWM_CAPCTL_CAPINV1_Pos) /*!< BPWM_T::CAPCTL: CAPINV1 Mask */ + +#define BPWM_CAPCTL_CAPINV2_Pos (10) /*!< BPWM_T::CAPCTL: CAPINV2 Position */ +#define BPWM_CAPCTL_CAPINV2_Msk (0x1ul << BPWM_CAPCTL_CAPINV2_Pos) /*!< BPWM_T::CAPCTL: CAPINV2 Mask */ + +#define BPWM_CAPCTL_CAPINV3_Pos (11) /*!< BPWM_T::CAPCTL: CAPINV3 Position */ +#define BPWM_CAPCTL_CAPINV3_Msk (0x1ul << BPWM_CAPCTL_CAPINV3_Pos) /*!< BPWM_T::CAPCTL: CAPINV3 Mask */ + +#define BPWM_CAPCTL_CAPINV4_Pos (12) /*!< BPWM_T::CAPCTL: CAPINV4 Position */ +#define BPWM_CAPCTL_CAPINV4_Msk (0x1ul << BPWM_CAPCTL_CAPINV4_Pos) /*!< BPWM_T::CAPCTL: CAPINV4 Mask */ + +#define BPWM_CAPCTL_CAPINV5_Pos (13) /*!< BPWM_T::CAPCTL: CAPINV5 Position */ +#define BPWM_CAPCTL_CAPINV5_Msk (0x1ul << BPWM_CAPCTL_CAPINV5_Pos) /*!< BPWM_T::CAPCTL: CAPINV5 Mask */ + +#define BPWM_CAPCTL_CAPINVn_Pos (8) /*!< BPWM_T::CAPCTL: CAPINVn Position */ +#define BPWM_CAPCTL_CAPINVn_Msk (0x3ful << BPWM_CAPCTL_CAPINVn_Pos) /*!< BPWM_T::CAPCTL: CAPINVn Mask */ + +#define BPWM_CAPCTL_RCRLDEN0_Pos (16) /*!< BPWM_T::CAPCTL: RCRLDEN0 Position */ +#define BPWM_CAPCTL_RCRLDEN0_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN0_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN0 Mask */ + +#define BPWM_CAPCTL_RCRLDEN1_Pos (17) /*!< BPWM_T::CAPCTL: RCRLDEN1 Position */ +#define BPWM_CAPCTL_RCRLDEN1_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN1_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN1 Mask */ + +#define BPWM_CAPCTL_RCRLDEN2_Pos (18) /*!< BPWM_T::CAPCTL: RCRLDEN2 Position */ +#define BPWM_CAPCTL_RCRLDEN2_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN2_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN2 Mask */ + +#define BPWM_CAPCTL_RCRLDEN3_Pos (19) /*!< BPWM_T::CAPCTL: RCRLDEN3 Position */ +#define BPWM_CAPCTL_RCRLDEN3_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN3_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN3 Mask */ + +#define BPWM_CAPCTL_RCRLDEN4_Pos (20) /*!< BPWM_T::CAPCTL: RCRLDEN4 Position */ +#define BPWM_CAPCTL_RCRLDEN4_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN4_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN4 Mask */ + +#define BPWM_CAPCTL_RCRLDEN5_Pos (21) /*!< BPWM_T::CAPCTL: RCRLDEN5 Position */ +#define BPWM_CAPCTL_RCRLDEN5_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN5_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN5 Mask */ + +#define BPWM_CAPCTL_RCRLDENn_Pos (16) /*!< BPWM_T::CAPCTL: RCRLDENn Position */ +#define BPWM_CAPCTL_RCRLDENn_Msk (0x3ful << BPWM_CAPCTL_RCRLDENn_Pos) /*!< BPWM_T::CAPCTL: RCRLDENn Mask */ + +#define BPWM_CAPCTL_FCRLDEN0_Pos (24) /*!< BPWM_T::CAPCTL: FCRLDEN0 Position */ +#define BPWM_CAPCTL_FCRLDEN0_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN0_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN0 Mask */ + +#define BPWM_CAPCTL_FCRLDEN1_Pos (25) /*!< BPWM_T::CAPCTL: FCRLDEN1 Position */ +#define BPWM_CAPCTL_FCRLDEN1_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN1_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN1 Mask */ + +#define BPWM_CAPCTL_FCRLDEN2_Pos (26) /*!< BPWM_T::CAPCTL: FCRLDEN2 Position */ +#define BPWM_CAPCTL_FCRLDEN2_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN2_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN2 Mask */ + +#define BPWM_CAPCTL_FCRLDEN3_Pos (27) /*!< BPWM_T::CAPCTL: FCRLDEN3 Position */ +#define BPWM_CAPCTL_FCRLDEN3_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN3_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN3 Mask */ + +#define BPWM_CAPCTL_FCRLDEN4_Pos (28) /*!< BPWM_T::CAPCTL: FCRLDEN4 Position */ +#define BPWM_CAPCTL_FCRLDEN4_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN4_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN4 Mask */ + +#define BPWM_CAPCTL_FCRLDEN5_Pos (29) /*!< BPWM_T::CAPCTL: FCRLDEN5 Position */ +#define BPWM_CAPCTL_FCRLDEN5_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN5_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN5 Mask */ + +#define BPWM_CAPCTL_FCRLDENn_Pos (24) /*!< BPWM_T::CAPCTL: FCRLDENn Position */ +#define BPWM_CAPCTL_FCRLDENn_Msk (0x3ful << BPWM_CAPCTL_FCRLDENn_Pos) /*!< BPWM_T::CAPCTL: FCRLDENn Mask */ + +#define BPWM_CAPSTS_CRIFOV0_Pos (0) /*!< BPWM_T::CAPSTS: CRIFOV0 Position */ +#define BPWM_CAPSTS_CRIFOV0_Msk (0x1ul << BPWM_CAPSTS_CRIFOV0_Pos) /*!< BPWM_T::CAPSTS: CRIFOV0 Mask */ + +#define BPWM_CAPSTS_CRIFOV1_Pos (1) /*!< BPWM_T::CAPSTS: CRIFOV1 Position */ +#define BPWM_CAPSTS_CRIFOV1_Msk (0x1ul << BPWM_CAPSTS_CRIFOV1_Pos) /*!< BPWM_T::CAPSTS: CRIFOV1 Mask */ + +#define BPWM_CAPSTS_CRIFOV2_Pos (2) /*!< BPWM_T::CAPSTS: CRIFOV2 Position */ +#define BPWM_CAPSTS_CRIFOV2_Msk (0x1ul << BPWM_CAPSTS_CRIFOV2_Pos) /*!< BPWM_T::CAPSTS: CRIFOV2 Mask */ + +#define BPWM_CAPSTS_CRIFOV3_Pos (3) /*!< BPWM_T::CAPSTS: CRIFOV3 Position */ +#define BPWM_CAPSTS_CRIFOV3_Msk (0x1ul << BPWM_CAPSTS_CRIFOV3_Pos) /*!< BPWM_T::CAPSTS: CRIFOV3 Mask */ + +#define BPWM_CAPSTS_CRIFOV4_Pos (4) /*!< BPWM_T::CAPSTS: CRIFOV4 Position */ +#define BPWM_CAPSTS_CRIFOV4_Msk (0x1ul << BPWM_CAPSTS_CRIFOV4_Pos) /*!< BPWM_T::CAPSTS: CRIFOV4 Mask */ + +#define BPWM_CAPSTS_CRIFOV5_Pos (5) /*!< BPWM_T::CAPSTS: CRIFOV5 Position */ +#define BPWM_CAPSTS_CRIFOV5_Msk (0x1ul << BPWM_CAPSTS_CRIFOV5_Pos) /*!< BPWM_T::CAPSTS: CRIFOV5 Mask */ + +#define BPWM_CAPSTS_CRIFOVn_Pos (0) /*!< BPWM_T::CAPSTS: CRIFOVn Position */ +#define BPWM_CAPSTS_CRIFOVn_Msk (0x3ful << BPWM_CAPSTS_CRIFOVn_Pos) /*!< BPWM_T::CAPSTS: CRIFOVn Mask */ + +#define BPWM_CAPSTS_CFIFOV0_Pos (8) /*!< BPWM_T::CAPSTS: CFIFOV0 Position */ +#define BPWM_CAPSTS_CFIFOV0_Msk (0x1ul << BPWM_CAPSTS_CFIFOV0_Pos) /*!< BPWM_T::CAPSTS: CFIFOV0 Mask */ + +#define BPWM_CAPSTS_CFIFOV1_Pos (9) /*!< BPWM_T::CAPSTS: CFIFOV1 Position */ +#define BPWM_CAPSTS_CFIFOV1_Msk (0x1ul << BPWM_CAPSTS_CFIFOV1_Pos) /*!< BPWM_T::CAPSTS: CFIFOV1 Mask */ + +#define BPWM_CAPSTS_CFIFOV2_Pos (10) /*!< BPWM_T::CAPSTS: CFIFOV2 Position */ +#define BPWM_CAPSTS_CFIFOV2_Msk (0x1ul << BPWM_CAPSTS_CFIFOV2_Pos) /*!< BPWM_T::CAPSTS: CFIFOV2 Mask */ + +#define BPWM_CAPSTS_CFIFOV3_Pos (11) /*!< BPWM_T::CAPSTS: CFIFOV3 Position */ +#define BPWM_CAPSTS_CFIFOV3_Msk (0x1ul << BPWM_CAPSTS_CFIFOV3_Pos) /*!< BPWM_T::CAPSTS: CFIFOV3 Mask */ + +#define BPWM_CAPSTS_CFIFOV4_Pos (12) /*!< BPWM_T::CAPSTS: CFIFOV4 Position */ +#define BPWM_CAPSTS_CFIFOV4_Msk (0x1ul << BPWM_CAPSTS_CFIFOV4_Pos) /*!< BPWM_T::CAPSTS: CFIFOV4 Mask */ + +#define BPWM_CAPSTS_CFIFOV5_Pos (13) /*!< BPWM_T::CAPSTS: CFIFOV5 Position */ +#define BPWM_CAPSTS_CFIFOV5_Msk (0x1ul << BPWM_CAPSTS_CFIFOV5_Pos) /*!< BPWM_T::CAPSTS: CFIFOV5 Mask */ + +#define BPWM_CAPSTS_CFIFOVn_Pos (8) /*!< BPWM_T::CAPSTS: CFIFOVn Position */ +#define BPWM_CAPSTS_CFIFOVn_Msk (0x3ful << BPWM_CAPSTS_CFIFOVn_Pos) /*!< BPWM_T::CAPSTS: CFIFOVn Mask */ + +#define BPWM_RCAPDAT0_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT0: RCAPDAT Position */ +#define BPWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT0_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT0: RCAPDAT Mask */ + +#define BPWM_FCAPDAT0_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT0: FCAPDAT Position */ +#define BPWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT0_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT0: FCAPDAT Mask */ + +#define BPWM_RCAPDAT1_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT1: RCAPDAT Position */ +#define BPWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT1_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT1: RCAPDAT Mask */ + +#define BPWM_FCAPDAT1_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT1: FCAPDAT Position */ +#define BPWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT1_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT1: FCAPDAT Mask */ + +#define BPWM_RCAPDAT2_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT2: RCAPDAT Position */ +#define BPWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT2_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT2: RCAPDAT Mask */ + +#define BPWM_FCAPDAT2_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT2: FCAPDAT Position */ +#define BPWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT2_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT2: FCAPDAT Mask */ + +#define BPWM_RCAPDAT3_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT3: RCAPDAT Position */ +#define BPWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT3_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT3: RCAPDAT Mask */ + +#define BPWM_FCAPDAT3_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT3: FCAPDAT Position */ +#define BPWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT3_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT3: FCAPDAT Mask */ + +#define BPWM_RCAPDAT4_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT4: RCAPDAT Position */ +#define BPWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT4_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT4: RCAPDAT Mask */ + +#define BPWM_FCAPDAT4_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT4: FCAPDAT Position */ +#define BPWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT4_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT4: FCAPDAT Mask */ + +#define BPWM_RCAPDAT5_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT5: RCAPDAT Position */ +#define BPWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT5_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT5: RCAPDAT Mask */ + +#define BPWM_FCAPDAT5_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT5: FCAPDAT Position */ +#define BPWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT5_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT5: FCAPDAT Mask */ + +#define BPWM_CAPIEN_CAPRIENn_Pos (0) /*!< BPWM_T::CAPIEN: CAPRIENn Position */ +#define BPWM_CAPIEN_CAPRIENn_Msk (0x3ful << BPWM_CAPIEN_CAPRIENn_Pos) /*!< BPWM_T::CAPIEN: CAPRIENn Mask */ + +#define BPWM_CAPIEN_CAPFIENn_Pos (8) /*!< BPWM_T::CAPIEN: CAPFIENn Position */ +#define BPWM_CAPIEN_CAPFIENn_Msk (0x3ful << BPWM_CAPIEN_CAPFIENn_Pos) /*!< BPWM_T::CAPIEN: CAPFIENn Mask */ + +#define BPWM_CAPIF_CAPRIF0_Pos (0) /*!< BPWM_T::CAPIF: CAPRIF0 Position */ +#define BPWM_CAPIF_CAPRIF0_Msk (0x1ul << BPWM_CAPIF_CAPRIF0_Pos) /*!< BPWM_T::CAPIF: CAPRIF0 Mask */ + +#define BPWM_CAPIF_CAPRIF1_Pos (1) /*!< BPWM_T::CAPIF: CAPRIF1 Position */ +#define BPWM_CAPIF_CAPRIF1_Msk (0x1ul << BPWM_CAPIF_CAPRIF1_Pos) /*!< BPWM_T::CAPIF: CAPRIF1 Mask */ + +#define BPWM_CAPIF_CAPRIF2_Pos (2) /*!< BPWM_T::CAPIF: CAPRIF2 Position */ +#define BPWM_CAPIF_CAPRIF2_Msk (0x1ul << BPWM_CAPIF_CAPRIF2_Pos) /*!< BPWM_T::CAPIF: CAPRIF2 Mask */ + +#define BPWM_CAPIF_CAPRIF3_Pos (3) /*!< BPWM_T::CAPIF: CAPRIF3 Position */ +#define BPWM_CAPIF_CAPRIF3_Msk (0x1ul << BPWM_CAPIF_CAPRIF3_Pos) /*!< BPWM_T::CAPIF: CAPRIF3 Mask */ + +#define BPWM_CAPIF_CAPRIF4_Pos (4) /*!< BPWM_T::CAPIF: CAPRIF4 Position */ +#define BPWM_CAPIF_CAPRIF4_Msk (0x1ul << BPWM_CAPIF_CAPRIF4_Pos) /*!< BPWM_T::CAPIF: CAPRIF4 Mask */ + +#define BPWM_CAPIF_CAPRIF5_Pos (5) /*!< BPWM_T::CAPIF: CAPRIF5 Position */ +#define BPWM_CAPIF_CAPRIF5_Msk (0x1ul << BPWM_CAPIF_CAPRIF5_Pos) /*!< BPWM_T::CAPIF: CAPRIF5 Mask */ + +#define BPWM_CAPIF_CAPRIFn_Pos (0) /*!< BPWM_T::CAPIF: CAPRIFn Position */ +#define BPWM_CAPIF_CAPRIFn_Msk (0x3ful << BPWM_CAPIF_CAPRIFn_Pos) /*!< BPWM_T::CAPIF: CAPRIFn Mask */ + +#define BPWM_CAPIF_CAPFIF0_Pos (8) /*!< BPWM_T::CAPIF: CAPFIF0 Position */ +#define BPWM_CAPIF_CAPFIF0_Msk (0x1ul << BPWM_CAPIF_CAPFIF0_Pos) /*!< BPWM_T::CAPIF: CAPFIF0 Mask */ + +#define BPWM_CAPIF_CAPFIF1_Pos (9) /*!< BPWM_T::CAPIF: CAPFIF1 Position */ +#define BPWM_CAPIF_CAPFIF1_Msk (0x1ul << BPWM_CAPIF_CAPFIF1_Pos) /*!< BPWM_T::CAPIF: CAPFIF1 Mask */ + +#define BPWM_CAPIF_CAPFIF2_Pos (10) /*!< BPWM_T::CAPIF: CAPFIF2 Position */ +#define BPWM_CAPIF_CAPFIF2_Msk (0x1ul << BPWM_CAPIF_CAPFIF2_Pos) /*!< BPWM_T::CAPIF: CAPFIF2 Mask */ + +#define BPWM_CAPIF_CAPFIF3_Pos (11) /*!< BPWM_T::CAPIF: CAPFIF3 Position */ +#define BPWM_CAPIF_CAPFIF3_Msk (0x1ul << BPWM_CAPIF_CAPFIF3_Pos) /*!< BPWM_T::CAPIF: CAPFIF3 Mask */ + +#define BPWM_CAPIF_CAPFIF4_Pos (12) /*!< BPWM_T::CAPIF: CAPFIF4 Position */ +#define BPWM_CAPIF_CAPFIF4_Msk (0x1ul << BPWM_CAPIF_CAPFIF4_Pos) /*!< BPWM_T::CAPIF: CAPFIF4 Mask */ + +#define BPWM_CAPIF_CAPFIF5_Pos (13) /*!< BPWM_T::CAPIF: CAPFIF5 Position */ +#define BPWM_CAPIF_CAPFIF5_Msk (0x1ul << BPWM_CAPIF_CAPFIF5_Pos) /*!< BPWM_T::CAPIF: CAPFIF5 Mask */ + +#define BPWM_CAPIF_CAPFIFn_Pos (8) /*!< BPWM_T::CAPIF: CAPFIFn Position */ +#define BPWM_CAPIF_CAPFIFn_Msk (0x3ful << BPWM_CAPIF_CAPFIFn_Pos) /*!< BPWM_T::CAPIF: CAPFIFn Mask */ + +#define BPWM_PBUF_PBUF_Pos (0) /*!< BPWM_T::PBUF: PBUF Position */ +#define BPWM_PBUF_PBUF_Msk (0xfffful << BPWM_PBUF_PBUF_Pos) /*!< BPWM_T::PBUF: PBUF Mask */ + +#define BPWM_CMPBUF0_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF0: CMPBUF Position */ +#define BPWM_CMPBUF0_CMPBUF_Msk (0xfffful << BPWM_CMPBUF0_CMPBUF_Pos) /*!< BPWM_T::CMPBUF0: CMPBUF Mask */ + +#define BPWM_CMPBUF1_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF1: CMPBUF Position */ +#define BPWM_CMPBUF1_CMPBUF_Msk (0xfffful << BPWM_CMPBUF1_CMPBUF_Pos) /*!< BPWM_T::CMPBUF1: CMPBUF Mask */ + +#define BPWM_CMPBUF2_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF2: CMPBUF Position */ +#define BPWM_CMPBUF2_CMPBUF_Msk (0xfffful << BPWM_CMPBUF2_CMPBUF_Pos) /*!< BPWM_T::CMPBUF2: CMPBUF Mask */ + +#define BPWM_CMPBUF3_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF3: CMPBUF Position */ +#define BPWM_CMPBUF3_CMPBUF_Msk (0xfffful << BPWM_CMPBUF3_CMPBUF_Pos) /*!< BPWM_T::CMPBUF3: CMPBUF Mask */ + +#define BPWM_CMPBUF4_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF4: CMPBUF Position */ +#define BPWM_CMPBUF4_CMPBUF_Msk (0xfffful << BPWM_CMPBUF4_CMPBUF_Pos) /*!< BPWM_T::CMPBUF4: CMPBUF Mask */ + +#define BPWM_CMPBUF5_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF5: CMPBUF Position */ +#define BPWM_CMPBUF5_CMPBUF_Msk (0xfffful << BPWM_CMPBUF5_CMPBUF_Pos) /*!< BPWM_T::CMPBUF5: CMPBUF Mask */ + +/**@}*/ /* BPWM_CONST */ +/**@}*/ /* end of BPWM register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __BPWM_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/can_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/can_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..86340d99d8520ed95567c25c5b9eab14744a6421 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/can_reg.h @@ -0,0 +1,759 @@ +/**************************************************************************//** + * @file can_reg.h + * @version V1.00 + * @brief CAN register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CAN_REG_H__ +#define __CAN_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup CAN Controller Area Network Controller(CAN) + Memory Mapped Structure for CAN Controller +@{ */ + + +typedef struct +{ + + /** + * @var CAN_IF_T::CREQ + * Offset: 0x20, 0x80 IFn Command Request Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |MessageNumber|Message Number + * | | |0x01-0x20: Valid Message Number, the Message Object in the Message + * | | |RAM is selected for data transfer. + * | | |0x00: Not a valid Message Number, interpreted as 0x20. + * | | |0x21-0x3F: Not a valid Message Number, interpreted as 0x01-0x1F. + * |[15] |Busy |Busy Flag + * | | |0 = Read/write action has finished. + * | | |1 = Writing to the IFn Command Request Register is in progress + * | | |This bit can only be read by the software. + * @var CAN_IF_T::CMASK + * Offset: 0x24, 0x84 IFn Command Mask Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DAT_B |Access Data Bytes [7:4] + * | | |Write Operation: + * | | |0 = Data Bytes [7:4] unchanged. + * | | |1 = Transfer Data Bytes [7:4] to Message Object. + * | | |Read Operation: + * | | |0 = Data Bytes [7:4] unchanged. + * | | |1 = Transfer Data Bytes [7:4] to IFn Message Buffer Register. + * |[1] |DAT_A |Access Data Bytes [3:0] + * | | |Write Operation: + * | | |0 = Data Bytes [3:0] unchanged. + * | | |1 = Transfer Data Bytes [3:0] to Message Object. + * | | |Read Operation: + * | | |0 = Data Bytes [3:0] unchanged. + * | | |1 = Transfer Data Bytes [3:0] to IFn Message Buffer Register. + * |[2] |TxRqst_NewDat|Access Transmission Request Bit When Write Operation + * | | |0 = TxRqst bit unchanged. + * | | |1 = Set TxRqst bit. + * | | |Note: If a transmission is requested by programming bit TxRqst/NewDat in the IFn Command Mask Register, bit TxRqst in the IFn Message Control Register will be ignored. + * | | |Access New Data Bit when Read Operation. + * | | |0 = NewDat bit remains unchanged. + * | | |1 = Clear NewDat bit in the Message Object. + * | | |Note: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat + * | | |The values of these bits transferred to the IFn Message Control Register always reflect the status before resetting these bits. + * |[3] |ClrIntPnd |Clear Interrupt Pending Bit + * | | |Write Operation: + * | | |When writing to a Message Object, this bit is ignored. + * | | |Read Operation: + * | | |0 = IntPnd bit (CAN_IFn_MCON[13]) remains unchanged. + * | | |1 = Clear IntPnd bit in the Message Object. + * |[4] |Control |Control Access Control Bits + * | | |Write Operation: + * | | |0 = Control Bits unchanged. + * | | |1 = Transfer Control Bits to Message Object. + * | | |Read Operation: + * | | |0 = Control Bits unchanged. + * | | |1 = Transfer Control Bits to IFn Message Buffer Register. + * |[5] |Arb |Access Arbitration Bits + * | | |Write Operation: + * | | |0 = Arbitration bits unchanged. + * | | |1 = Transfer Identifier + Dir (CAN_IFn_ARB2[13]) + Xtd (CAN_IFn_ARB2[14]) + MsgVal (CAN_IFn_ARB2[15]) to Message Object. + * | | |Read Operation: + * | | |0 = Arbitration bits unchanged. + * | | |1 = Transfer Identifier + Dir + Xtd + MsgVal to IFn Message Buffer Register. + * |[6] |Mask |Access Mask Bits + * | | |Write Operation: + * | | |0 = Mask bits unchanged. + * | | |1 = Transfer Identifier Mask + MDir + MXtd to Message Object. + * | | |Read Operation: + * | | |0 = Mask bits unchanged. + * | | |1 = Transfer Identifier Mask + MDir + MXtd to IFn Message Buffer Register. + * |[7] |WR_RD |Write / Read Mode + * | | |0 = Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers. + * | | |1 = Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register. + * @var CAN_IF_T::MASK1 + * Offset: 0x28, 0x88 IFn Mask 1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |Msk |Identifier Mask 15-0 + * | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering. + * | | |1 = The corresponding identifier bit is used for acceptance filtering. + * @var CAN_IF_T::MASK2 + * Offset: 0x2C, 0x8C IFn Mask 2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[12:0] |Msk |Identifier Mask 28-16 + * | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering. + * | | |1 = The corresponding identifier bit is used for acceptance filtering. + * |[14] |MDir |Mask Message Direction + * | | |0 = The message direction bit (Dir (CAN_IFn_ARB2[13])) has no effect on the acceptance filtering. + * | | |1 = The message direction bit (Dir) is used for acceptance filtering. + * |[15] |MXtd |Mask Extended Identifier + * | | |0 = The extended identifier bit (IDE) has no effect on the acceptance filtering. + * | | |1 = The extended identifier bit (IDE) is used for acceptance filtering. + * | | |Note: When 11-bit (standard) Identifiers are used for a Message Object, the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2]) + * | | |For acceptance filtering, only these bits together with mask bits Msk28 to Msk18 (CAN_IFn_MASK2[12:2]) are considered. + * @var CAN_IF_T::ARB1 + * Offset: 0x30, 0x90 IFn Arbitration 1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |ID |Message Identifier 15-0 + * | | |ID28 - ID0, 29-bit Identifier (Extended Frame) + * | | |ID28 - ID18, 11-bit Identifier (Standard Frame) + * @var CAN_IF_T::ARB2 + * Offset: 0x34, 0x94 IFn Arbitration 2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[12:0] |ID |Message Identifier 28-16 + * | | |ID28 - ID0, 29-bit Identifier (Extended Frame) + * | | |ID28 - ID18, 11-bit Identifier (Standard Frame) + * |[13] |Dir |Message Direction + * | | |0 = Direction is receive. + * | | |On TxRqst, a Remote Frame with the identifier of this Message Object is transmitted + * | | |On reception of a Data Frame with matching identifier, that message is stored in this Message Object. + * | | |1 = Direction is transmit. + * | | |On TxRqst, the respective Message Object is transmitted as a Data Frame + * | | |On reception of a Remote Frame with matching identifier, the TxRqst bit (CAN_IFn_CMASK[2]) of this Message Object is set (if RmtEn (CAN_IFn_MCON[9]) = one). + * |[14] |Xtd |Extended Identifier + * | | |0 = The 11-bit (standard) Identifier will be used for this Message Object. + * | | |1 = The 29-bit (extended) Identifier will be used for this Message Object. + * |[15] |MsgVal |Message Valid + * | | |0 = The Message Object is ignored by the Message Handler. + * | | |1 = The Message Object is configured and should be considered by the Message Handler. + * | | |Note: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0]) + * | | |This bit must also be reset before the identifier Id28-0 (CAN_IFn_ARB1/2), the control bits Xtd (CAN_IFn_ARB2[14]), Dir (CAN_IFn_ARB2[13]), or the Data Length Code DLC3-0 (CAN_IFn_MCON[3:0]) are modified, or if the Messages Object is no longer required. + * @var CAN_IF_T::MCON + * Offset: 0x38, 0x98 IFn Message Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |DLC |Data Length Code + * | | |0-8: Data Frame has 0-8 data bytes. + * | | |9-15: Data Frame has 8 data bytes + * | | |Note: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes + * | | |When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. + * | | |Data(0): 1st data byte of a CAN Data Frame + * | | |Data(1): 2nd data byte of a CAN Data Frame + * | | |Data(2): 3rd data byte of a CAN Data Frame + * | | |Data(3): 4th data byte of a CAN Data Frame + * | | |Data(4): 5th data byte of a CAN Data Frame + * | | |Data(5): 6th data byte of a CAN Data Frame + * | | |Data(6): 7th data byte of a CAN Data Frame + * | | |Data(7): 8th data byte of a CAN Data Frame + * | | |Note: The Data(0) byte is the first data byte shifted into the shift register of the CAN Core during a reception while the Data(7) byte is the last + * | | |When the Message Handler stores a Data Frame, it will write all the eight data bytes into a Message Object + * | | |If the Data Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by unspecified values. + * |[7] |EoB |End of Buffer + * | | |0 = Message Object belongs to a FIFO Buffer and is not the last Message Object of that FIFO Buffer. + * | | |1 = Single Message Object or last Message Object of a FIFO Buffer. + * | | |Note: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer + * | | |For single Message Objects (not belonging to a FIFO Buffer), this bit must always be set to one + * |[8] |TxRqst |Transmit Request + * | | |0 = This Message Object is not waiting for transmission. + * | | |1 = The transmission of this Message Object is requested and is not yet done. + * |[9] |RmtEn |Remote Enable Bit + * | | |0 = At the reception of a Remote Frame, TxRqst (CAN_IFn_MCON[8]) is left unchanged. + * | | |1 = At the reception of a Remote Frame, TxRqst is set. + * |[10] |RxIE |Receive Interrupt Enable Bit + * | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after a successful reception of a frame. + * | | |1 = IntPnd will be set after a successful reception of a frame. + * |[11] |TxIE |Transmit Interrupt Enable Bit + * | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after the successful transmission of a frame. + * | | |1 = IntPnd will be set after a successful transmission of a frame. + * |[12] |UMask |Use Acceptance Mask + * | | |0 = Mask ignored. + * | | |1 = Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering. + * | | |Note: If the UMask bit is set to one, the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_ARB2[15]) is set to one. + * |[13] |IntPnd |Interrupt Pending + * | | |0 = This message object is not the source of an interrupt. + * | | |1 = This message object is the source of an interrupt + * | | |The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority. + * |[14] |MsgLst |Message Lost (only valid for Message Objects with direction = receive). + * | | |0 = No message lost since last time this bit was reset by the CPU. + * | | |1 = The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message. + * |[15] |NewDat |New Data + * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the application software. + * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object. + * @var CAN_IF_T::DAT_A1 + * Offset: 0x3C, 0x9C IFn Data A1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |Data_0_ |Data Byte 0 + * | | |1st data byte of a CAN Data Frame + * |[15:8] |Data_1_ |Data Byte 1 + * | | |2nd data byte of a CAN Data Frame + * @var CAN_IF_T::DAT_A2 + * Offset: 0x40, 0xA0 IFn Data A2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |Data_2_ |Data Byte 2 + * | | |3rd data byte of CAN Data Frame + * |[15:8] |Data_3_ |Data Byte 3 + * | | |4th data byte of CAN Data Frame + * @var CAN_IF_T::DAT_B1 + * Offset: 0x44, 0xA4 IFn Data B1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |Data_4_ |Data Byte 4 + * | | |5th data byte of CAN Data Frame + * |[15:8] |Data_5_ |Data Byte 5 + * | | |6th data byte of CAN Data Frame + * @var CAN_IF_T::DAT_B2 + * Offset: 0x48, 0xA8 IFn Data B2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |Data_6_ |Data Byte 6 + * | | |7th data byte of CAN Data Frame. + * |[15:8] |Data_7_ |Data Byte 7 + * | | |8th data byte of CAN Data Frame. + */ + __IO uint32_t CREQ; /*!< [0x0020] IFn Command Request Register */ + __IO uint32_t CMASK; /*!< [0x0024] IFn Command Mask Register */ + __IO uint32_t MASK1; /*!< [0x0028] IFn Mask 1 Register */ + __IO uint32_t MASK2; /*!< [0x002c] IFn Mask 2 Register */ + __IO uint32_t ARB1; /*!< [0x0030] IFn Arbitration 1 Register */ + __IO uint32_t ARB2; /*!< [0x0034] IFn Arbitration 2 Register */ + __IO uint32_t MCON; /*!< [0x0038] IFn Message Control Register */ + __IO uint32_t DAT_A1; /*!< [0x003c] IFn Data A1 Register */ + __IO uint32_t DAT_A2; /*!< [0x0040] IFn Data A2 Register */ + __IO uint32_t DAT_B1; /*!< [0x0044] IFn Data B1 Register */ + __IO uint32_t DAT_B2; /*!< [0x0048] IFn Data B2 Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[13]; + /// @endcond //HIDDEN_SYMBOLS +} CAN_IF_T; + + +typedef struct +{ + + + /** + * @var CAN_T::CON + * Offset: 0x00 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |Init |Init Initialization + * | | |0 = Normal Operation. + * | | |1 = Initialization is started. + * |[1] |IE |Module Interrupt Enable Bit + * | | |0 = Function interrupt is Disabled. + * | | |1 = Function interrupt is Enabled. + * |[2] |SIE |Status Change Interrupt Enable Bit + * | | |0 = Disabled - No Status Change Interrupt will be generated. + * | | |1 = Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected. + * |[3] |EIE |Error Interrupt Enable Bit + * | | |0 = Disabled - No Error Status Interrupt will be generated. + * | | |1 = Enabled - A change in the bits BOff (CAN_STATUS[7]) or EWarn (CAN_STATUS[6]) in the Status Register will generate an interrupt. + * |[5] |DAR |Automatic Re-transmission Disable Bit + * | | |0 = Automatic Retransmission of disturbed messages Enabled. + * | | |1 = Automatic Retransmission Disabled. + * |[6] |CCE |Configuration Change Enable Bit + * | | |0 = No write access to the Bit Timing Register. + * | | |1 = Write access to the Bit Timing Register (CAN_BTIME) allowed. (while Init bit (CAN_CON[0]) = 1). + * |[7] |Test |Test Mode Enable Bit + * | | |0 = Normal Operation. + * | | |1 = Test Mode. + * @var CAN_T::STATUS + * Offset: 0x04 Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |LEC |Last Error Code (Type of the Last Error to Occur on the CAN Bus) + * | | |The LEC field holds a code, which indicates the type of the last error to occur on the CAN bus + * | | |This field will be cleared to '0' when a message has been transferred (reception or transmission) without error + * | | |The unused code '7' may be written by the CPU to check for updates + * | | |The Error! Reference source not found + * | | |describes the error code. + * |[3] |TxOK |Transmitted a Message Successfully + * | | |0 = Since this bit was reset by the CPU, no message has been successfully transmitted + * | | |This bit is never reset by the CAN Core. + * | | |1 = Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted. + * |[4] |RxOK |Received a Message Successfully + * | | |0 = No message has been successfully received since this bit was last reset by the CPU + * | | |This bit is never reset by the CAN Core. + * | | |1 = A message has been successfully received since this bit was last reset by the CPU (independent of the result of acceptance filtering). + * |[5] |EPass |Error Passive (Read Only) + * | | |0 = The CAN Core is error active. + * | | |1 = The CAN Core is in the error passive state as defined in the CAN Specification. + * |[6] |EWarn |Error Warning Status (Read Only) + * | | |0 = Both error counters are below the error warning limit of 96. + * | | |1 = At least one of the error counters in the EML has reached the error warning limit of 96. + * |[7] |BOff |Bus-off Status (Read Only) + * | | |0 = The CAN module is not in bus-off state. + * | | |1 = The CAN module is in bus-off state. + * @var CAN_T::ERR + * Offset: 0x08 Error Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |TEC |Transmit Error Counter + * | | |Actual state of the Transmit Error Counter. Values between 0 and 255. + * |[14:8] |REC |Receive Error Counter + * | | |Actual state of the Receive Error Counter. Values between 0 and 127. + * |[15] |RP |Receive Error Passive + * | | |0 = The Receive Error Counter is below the error passive level. + * | | |1 = The Receive Error Counter has reached the error passive level as defined in the CAN Specification. + * @var CAN_T::BTIME + * Offset: 0x0C Bit Timing Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |BRP |Baud Rate Prescaler + * | | |0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta + * | | |The bit time is built up from a multiple of this quanta + * | | |Valid values for the Baud Rate Prescaler are [0...63] + * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + * |[7:6] |SJW |(Re)Synchronization Jump Width + * | | |0x0-0x3: Valid programmed values are [0...3] + * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + * |[11:8] |TSeg1 |Time Segment Before the Sample Point Minus Sync_Seg + * | | |0x01-0x0F: valid values for TSeg1 are [1...15] + * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed is used. + * |[14:12] |TSeg2 |Time Segment After Sample Point + * | | |0x0-0x7: Valid values for TSeg2 are [0...7] + * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + * @var CAN_T::IIDR + * Offset: 0x10 Interrupt Identifier Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |IntId |Interrupt Identifier (Indicates the Source of the Interrupt) + * | | |If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order + * | | |An interrupt remains pending until the application software has cleared it + * | | |If IntId is different from 0x0000 and IE (CAN_CON[1]) is set, the IRQ interrupt signal to the EIC is active + * | | |The interrupt remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset. + * | | |The Status Interrupt has the highest priority + * | | |Among the message interrupts, the Message Object' s interrupt priority decreases with increasing message number. + * | | |A message interrupt is cleared by clearing the Message Object's IntPnd bit (CAN_IFn_MCON[13]) + * | | |The Status Interrupt is cleared by reading the Status Register. + * @var CAN_T::TEST + * Offset: 0x14 Test Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2] |Basic |Basic Mode + * | | |0 = Basic Mode Disabled. + * | | |1= IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer. + * |[3] |Silent |Silent Mode + * | | |0 = Normal operation. + * | | |1 = The module is in Silent Mode. + * |[4] |LBack |Loop Back Mode Enable Bit + * | | |0 = Loop Back Mode is Disabled. + * | | |1 = Loop Back Mode is Enabled. + * |[6:5] |Tx |Tx[1:0]: Control of CAN_TX Pin + * | | |00 = Reset value, CAN_TX pin is controlled by the CAN Core. + * | | |01 = Sample Point can be monitored at CAN_TX pin. + * | | |10 = CAN_TX pin drives a dominant ('0') value. + * | | |11 = CAN_TX pin drives a recessive ('1') value. + * |[7] |Rx |Monitors the Actual Value of CAN_RX Pin (Read Only) *(1) + * | | |0 = The CAN bus is dominant (CAN_RX = '0'). + * | | |1 = The CAN bus is recessive (CAN_RX = '1'). + * @var CAN_T::BRPE + * Offset: 0x18 Baud Rate Prescaler Extension Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |BRPE |BRPE: Baud Rate Prescaler Extension + * | | |0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to 1023 + * | | |The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BTIME (LSBs) is used. + * @var CAN_T::TXREQ1 + * Offset: 0x100 Transmission Request Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TxRqst16_1|Transmission Request Bits 16-1 (of All Message Objects) + * | | |0 = This Message Object is not waiting for transmission. + * | | |1 = The transmission of this Message Object is requested and is not yet done. + * | | |These bits are read only. + * @var CAN_T::TXREQ2 + * Offset: 0x104 Transmission Request Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TxRqst32_17|Transmission Request Bits 32-17 (of All Message Objects) + * | | |0 = This Message Object is not waiting for transmission. + * | | |1 = The transmission of this Message Object is requested and is not yet done. + * | | |These bits are read only. + * @var CAN_T::NDAT1 + * Offset: 0x120 New Data Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |NewData16_1|New Data Bits 16-1 (of All Message Objects) + * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software. + * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object. + * @var CAN_T::NDAT2 + * Offset: 0x124 New Data Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |NewData32_17|New Data Bits 32-17 (of All Message Objects) + * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software. + * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object. + * @var CAN_T::IPND1 + * Offset: 0x140 Interrupt Pending Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |IntPnd16_1|Interrupt Pending Bits 16-1 (of All Message Objects) + * | | |0 = This message object is not the source of an interrupt. + * | | |1 = This message object is the source of an interrupt. + * @var CAN_T::IPND2 + * Offset: 0x144 Interrupt Pending Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |IntPnd32_17|Interrupt Pending Bits 32-17 (of All Message Objects) + * | | |0 = This message object is not the source of an interrupt. + * | | |1 = This message object is the source of an interrupt. + * @var CAN_T::MVLD1 + * Offset: 0x160 Message Valid Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |MsgVal16_1|Message Valid Bits 16-1 (of All Message Objects) (Read Only) + * | | |0 = This Message Object is ignored by the Message Handler. + * | | |1 = This Message Object is configured and should be considered by the Message Handler. + * | | |Ex + * | | |CAN_MVLD1[0] means Message object No.1 is valid or not + * | | |If CAN_MVLD1[0] is set, message object No.1 is configured. + * @var CAN_T::MVLD2 + * Offset: 0x164 Message Valid Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |MsgVal32_17|Message Valid Bits 32-17 (of All Message Objects) (Read Only) + * | | |0 = This Message Object is ignored by the Message Handler. + * | | |1 = This Message Object is configured and should be considered by the Message Handler. + * | | |Ex.CAN_MVLD2[15] means Message object No.32 is valid or not + * | | |If CAN_MVLD2[15] is set, message object No.32 is configured. + * @var CAN_T::WU_EN + * Offset: 0x168 Wake-up Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WAKUP_EN |Wake-up Enable Bit + * | | |0 = The wake-up function Disabled. + * | | |1 = The wake-up function Enabled. + * | | |Note: User can wake-up system when there is a falling edge in the CAN_Rx pin. + * @var CAN_T::WU_STATUS + * Offset: 0x16C Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WAKUP_STS |Wake-up Status + * | | |0 = No wake-up event occurred. + * | | |1 = Wake-up event occurred. + * | | |Note: This bit can be cleared by writing '0'. + */ + __IO uint32_t CON; /*!< [0x0000] Control Register */ + __IO uint32_t STATUS; /*!< [0x0004] Status Register */ + __I uint32_t ERR; /*!< [0x0008] Error Counter Register */ + __IO uint32_t BTIME; /*!< [0x000c] Bit Timing Register */ + __I uint32_t IIDR; /*!< [0x0010] Interrupt Identifier Register */ + __IO uint32_t TEST; /*!< [0x0014] Test Register */ + __IO uint32_t BRPE; /*!< [0x0018] Baud Rate Prescaler Extension Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO CAN_IF_T IF[2]; + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[8]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t TXREQ1; /*!< [0x0100] Transmission Request Register 1 */ + __I uint32_t TXREQ2; /*!< [0x0104] Transmission Request Register 2 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[6]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t NDAT1; /*!< [0x0120] New Data Register 1 */ + __I uint32_t NDAT2; /*!< [0x0124] New Data Register 2 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE4[6]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t IPND1; /*!< [0x0140] Interrupt Pending Register 1 */ + __I uint32_t IPND2; /*!< [0x0144] Interrupt Pending Register 2 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE5[6]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t MVLD1; /*!< [0x0160] Message Valid Register 1 */ + __I uint32_t MVLD2; /*!< [0x0164] Message Valid Register 2 */ + __IO uint32_t WU_EN; /*!< [0x0168] Wake-up Enable Control Register */ + __IO uint32_t WU_STATUS; /*!< [0x016c] Wake-up Status Register */ + +} CAN_T; + +/** + @addtogroup CAN_CONST CAN Bit Field Definition + Constant Definitions for CAN Controller +@{ */ + +#define CAN_CON_INIT_Pos (0) /*!< CAN_T::CON: Init Position */ +#define CAN_CON_INIT_Msk (0x1ul << CAN_CON_INIT_Pos) /*!< CAN_T::CON: Init Mask */ + +#define CAN_CON_IE_Pos (1) /*!< CAN_T::CON: IE Position */ +#define CAN_CON_IE_Msk (0x1ul << CAN_CON_IE_Pos) /*!< CAN_T::CON: IE Mask */ + +#define CAN_CON_SIE_Pos (2) /*!< CAN_T::CON: SIE Position */ +#define CAN_CON_SIE_Msk (0x1ul << CAN_CON_SIE_Pos) /*!< CAN_T::CON: SIE Mask */ + +#define CAN_CON_EIE_Pos (3) /*!< CAN_T::CON: EIE Position */ +#define CAN_CON_EIE_Msk (0x1ul << CAN_CON_EIE_Pos) /*!< CAN_T::CON: EIE Mask */ + +#define CAN_CON_DAR_Pos (5) /*!< CAN_T::CON: DAR Position */ +#define CAN_CON_DAR_Msk (0x1ul << CAN_CON_DAR_Pos) /*!< CAN_T::CON: DAR Mask */ + +#define CAN_CON_CCE_Pos (6) /*!< CAN_T::CON: CCE Position */ +#define CAN_CON_CCE_Msk (0x1ul << CAN_CON_CCE_Pos) /*!< CAN_T::CON: CCE Mask */ + +#define CAN_CON_TEST_Pos (7) /*!< CAN_T::CON: Test Position */ +#define CAN_CON_TEST_Msk (0x1ul << CAN_CON_TEST_Pos) /*!< CAN_T::CON: Test Mask */ + +#define CAN_STATUS_LEC_Pos (0) /*!< CAN_T::STATUS: LEC Position */ +#define CAN_STATUS_LEC_Msk (0x7ul << CAN_STATUS_LEC_Pos) /*!< CAN_T::STATUS: LEC Mask */ + +#define CAN_STATUS_TXOK_Pos (3) /*!< CAN_T::STATUS: TxOK Position */ +#define CAN_STATUS_TXOK_Msk (0x1ul << CAN_STATUS_TXOK_Pos) /*!< CAN_T::STATUS: TxOK Mask */ + +#define CAN_STATUS_RXOK_Pos (4) /*!< CAN_T::STATUS: RxOK Position */ +#define CAN_STATUS_RXOK_Msk (0x1ul << CAN_STATUS_RXOK_Pos) /*!< CAN_T::STATUS: RxOK Mask */ + +#define CAN_STATUS_EPASS_Pos (5) /*!< CAN_T::STATUS: EPass Position */ +#define CAN_STATUS_EPASS_Msk (0x1ul << CAN_STATUS_EPASS_Pos) /*!< CAN_T::STATUS: EPass Mask */ + +#define CAN_STATUS_EWARN_Pos (6) /*!< CAN_T::STATUS: EWarn Position */ +#define CAN_STATUS_EWARN_Msk (0x1ul << CAN_STATUS_EWARN_Pos) /*!< CAN_T::STATUS: EWarn Mask */ + +#define CAN_STATUS_BOFF_Pos (7) /*!< CAN_T::STATUS: BOff Position */ +#define CAN_STATUS_BOFF_Msk (0x1ul << CAN_STATUS_BOFF_Pos) /*!< CAN_T::STATUS: BOff Mask */ + +#define CAN_ERR_TEC_Pos (0) /*!< CAN_T::ERR: TEC Position */ +#define CAN_ERR_TEC_Msk (0xfful << CAN_ERR_TEC_Pos) /*!< CAN_T::ERR: TEC Mask */ + +#define CAN_ERR_REC_Pos (8) /*!< CAN_T::ERR: REC Position */ +#define CAN_ERR_REC_Msk (0x7ful << CAN_ERR_REC_Pos) /*!< CAN_T::ERR: REC Mask */ + +#define CAN_ERR_RP_Pos (15) /*!< CAN_T::ERR: RP Position */ +#define CAN_ERR_RP_Msk (0x1ul << CAN_ERR_RP_Pos) /*!< CAN_T::ERR: RP Mask */ + +#define CAN_BTIME_BRP_Pos (0) /*!< CAN_T::BTIME: BRP Position */ +#define CAN_BTIME_BRP_Msk (0x3ful << CAN_BTIME_BRP_Pos) /*!< CAN_T::BTIME: BRP Mask */ + +#define CAN_BTIME_SJW_Pos (6) /*!< CAN_T::BTIME: SJW Position */ +#define CAN_BTIME_SJW_Msk (0x3ul << CAN_BTIME_SJW_Pos) /*!< CAN_T::BTIME: SJW Mask */ + +#define CAN_BTIME_TSEG1_Pos (8) /*!< CAN_T::BTIME: TSeg1 Position */ +#define CAN_BTIME_TSEG1_Msk (0xful << CAN_BTIME_TSEG1_Pos) /*!< CAN_T::BTIME: TSeg1 Mask */ + +#define CAN_BTIME_TSEG2_Pos (12) /*!< CAN_T::BTIME: TSeg2 Position */ +#define CAN_BTIME_TSEG2_Msk (0x7ul << CAN_BTIME_TSEG2_Pos) /*!< CAN_T::BTIME: TSeg2 Mask */ + +#define CAN_IIDR_IntId_Pos (0) /*!< CAN_T::IIDR: IntId Position */ +#define CAN_IIDR_IntId_Msk (0xfffful << CAN_IIDR_IntId_Pos) /*!< CAN_T::IIDR: IntId Mask */ + +#define CAN_TEST_BASIC_Pos (2) /*!< CAN_T::TEST: Basic Position */ +#define CAN_TEST_BASIC_Msk (0x1ul << CAN_TEST_BASIC_Pos) /*!< CAN_T::TEST: Basic Mask */ + +#define CAN_TEST_SILENT_Pos (3) /*!< CAN_T::TEST: Silent Position */ +#define CAN_TEST_SILENT_Msk (0x1ul << CAN_TEST_SILENT_Pos) /*!< CAN_T::TEST: Silent Mask */ + +#define CAN_TEST_LBACK_Pos (4) /*!< CAN_T::TEST: LBack Position */ +#define CAN_TEST_LBACK_Msk (0x1ul << CAN_TEST_LBACK_Pos) /*!< CAN_T::TEST: LBack Mask */ + +#define CAN_TEST_Tx_Pos (5) /*!< CAN_T::TEST: Tx Position */ +#define CAN_TEST_Tx_Msk (0x3ul << CAN_TEST_Tx_Pos) /*!< CAN_T::TEST: Tx Mask */ + +#define CAN_TEST_Rx_Pos (7) /*!< CAN_T::TEST: Rx Position */ +#define CAN_TEST_Rx_Msk (0x1ul << CAN_TEST_Rx_Pos) /*!< CAN_T::TEST: Rx Mask */ + +#define CAN_BRPE_BRPE_Pos (0) /*!< CAN_T::BRPE: BRPE Position */ +#define CAN_BRPE_BRPE_Msk (0xful << CAN_BRPE_BRPE_Pos) /*!< CAN_T::BRPE: BRPE Mask */ + +#define CAN_IF_CREQ_MSGNUM_Pos (0) /*!< CAN_IF_T::CREQ: MessageNumber Position*/ +#define CAN_IF_CREQ_MSGNUM_Msk (0x3ful << CAN_IF_CREQ_MSGNUM_Pos) /*!< CAN_IF_T::CREQ: MessageNumber Mask */ + +#define CAN_IF_CREQ_BUSY_Pos (15) /*!< CAN_IF_T::CREQ: Busy Position */ +#define CAN_IF_CREQ_BUSY_Msk (0x1ul << CAN_IF_CREQ_BUSY_Pos) /*!< CAN_IF_T::CREQ: Busy Mask */ + +#define CAN_IF_CMASK_DATAB_Pos (0) /*!< CAN_IF_T::CMASK: DAT_B Position */ +#define CAN_IF_CMASK_DATAB_Msk (0x1ul << CAN_IF_CMASK_DATAB_Pos) /*!< CAN_IF_T::CMASK: DAT_B Mask */ + +#define CAN_IF_CMASK_DATAA_Pos (1) /*!< CAN_IF_T::CMASK: DAT_A Position */ +#define CAN_IF_CMASK_DATAA_Msk (0x1ul << CAN_IF_CMASK_DATAA_Pos) /*!< CAN_IF_T::CMASK: DAT_A Mask */ + +#define CAN_IF_CMASK_TXRQSTNEWDAT_Pos (2) /*!< CAN_IF_T::CMASK: TxRqst_NewDat Position*/ +#define CAN_IF_CMASK_TXRQSTNEWDAT_Msk (0x1ul << CAN_IF_CMASK_TXRQSTNEWDAT_Pos) /*!< CAN_IF_T::CMASK: TxRqst_NewDat Mask */ + +#define CAN_IF_CMASK_CLRINTPND_Pos (3) /*!< CAN_IF_T::CMASK: ClrIntPnd Position */ +#define CAN_IF_CMASK_CLRINTPND_Msk (0x1ul << CAN_IF_CMASK_CLRINTPND_Pos) /*!< CAN_IF_T::CMASK: ClrIntPnd Mask */ + +#define CAN_IF_CMASK_CONTROL_Pos (4) /*!< CAN_IF_T::CMASK: Control Position */ +#define CAN_IF_CMASK_CONTROL_Msk (0x1ul << CAN_IF_CMASK_CONTROL_Pos) /*!< CAN_IF_T::CMASK: Control Mask */ + +#define CAN_IF_CMASK_ARB_Pos (5) /*!< CAN_IF_T::CMASK: Arb Position */ +#define CAN_IF_CMASK_ARB_Msk (0x1ul << CAN_IF_CMASK_ARB_Pos) /*!< CAN_IF_T::CMASK: Arb Mask */ + +#define CAN_IF_CMASK_MASK_Pos (6) /*!< CAN_IF_T::CMASK: Mask Position */ +#define CAN_IF_CMASK_MASK_Msk (0x1ul << CAN_IF_CMASK_MASK_Pos) /*!< CAN_IF_T::CMASK: Mask Mask */ + +#define CAN_IF_CMASK_WRRD_Pos (7) /*!< CAN_IF_T::CMASK: WR_RD Position */ +#define CAN_IF_CMASK_WRRD_Msk (0x1ul << CAN_IF_CMASK_WRRD_Pos) /*!< CAN_IF_T::CMASK: WR_RD Mask */ + +#define CAN_IF_MASK1_Msk_Pos (0) /*!< CAN_IF_T::MASK1: Msk Position */ +#define CAN_IF_MASK1_Msk_Msk (0xfffful << CAN_IF_MASK1_Msk_Pos) /*!< CAN_IF_T::MASK1: Msk Mask */ + +#define CAN_IF_MASK2_Msk_Pos (0) /*!< CAN_IF_T::MASK2: Msk Position */ +#define CAN_IF_MASK2_Msk_Msk (0x1ffful << CAN_IF_MASK2_Msk_Pos) /*!< CAN_IF_T::MASK2: Msk Mask */ + +#define CAN_IF_MASK2_MDIR_Pos (14) /*!< CAN_IF_T::MASK2: MDir Position */ +#define CAN_IF_MASK2_MDIR_Msk (0x1ul << CAN_IF_MASK2_MDIR_Pos) /*!< CAN_IF_T::MASK2: MDir Mask */ + +#define CAN_IF_MASK2_MXTD_Pos (15) /*!< CAN_IF_T::MASK2: MXtd Position */ +#define CAN_IF_MASK2_MXTD_Msk (0x1ul << CAN_IF_MASK2_MXTD_Pos) /*!< CAN_IF_T::MASK2: MXtd Mask */ + +#define CAN_IF_ARB1_ID_Pos (0) /*!< CAN_IF_T::ARB1: ID Position */ +#define CAN_IF_ARB1_ID_Msk (0xfffful << CAN_IF_ARB1_ID_Pos) /*!< CAN_IF_T::ARB1: ID Mask */ + +#define CAN_IF_ARB2_ID_Pos (0) /*!< CAN_IF_T::ARB2: ID Position */ +#define CAN_IF_ARB2_ID_Msk (0x1ffful << CAN_IF_ARB2_ID_Pos) /*!< CAN_IF_T::ARB2: ID Mask */ + +#define CAN_IF_ARB2_DIR_Pos (13) /*!< CAN_IF_T::ARB2: Dir Position */ +#define CAN_IF_ARB2_DIR_Msk (0x1ul << CAN_IF_ARB2_DIR_Pos) /*!< CAN_IF_T::ARB2: Dir Mask */ + +#define CAN_IF_ARB2_XTD_Pos (14) /*!< CAN_IF_T::ARB2: Xtd Position */ +#define CAN_IF_ARB2_XTD_Msk (0x1ul << CAN_IF_ARB2_XTD_Pos) /*!< CAN_IF_T::ARB2: Xtd Mask */ + +#define CAN_IF_ARB2_MSGVAL_Pos (15) /*!< CAN_IF_T::ARB2: MsgVal Position */ +#define CAN_IF_ARB2_MSGVAL_Msk (0x1ul << CAN_IF_ARB2_MSGVAL_Pos) /*!< CAN_IF_T::ARB2: MsgVal Mask */ + +#define CAN_IF_MCON_DLC_Pos (0) /*!< CAN_IF_T::MCON: DLC Position */ +#define CAN_IF_MCON_DLC_Msk (0xful << CAN_IF_MCON_DLC_Pos) /*!< CAN_IF_T::MCON: DLC Mask */ + +#define CAN_IF_MCON_EOB_Pos (7) /*!< CAN_IF_T::MCON: EoB Position */ +#define CAN_IF_MCON_EOB_Msk (0x1ul << CAN_IF_MCON_EOB_Pos) /*!< CAN_IF_T::MCON: EoB Mask */ + +#define CAN_IF_MCON_TxRqst_Pos (8) /*!< CAN_IF_T::MCON: TxRqst Position */ +#define CAN_IF_MCON_TxRqst_Msk (0x1ul << CAN_IF_MCON_TxRqst_Pos) /*!< CAN_IF_T::MCON: TxRqst Mask */ + +#define CAN_IF_MCON_RmtEn_Pos (9) /*!< CAN_IF_T::MCON: RmtEn Position */ +#define CAN_IF_MCON_RmtEn_Msk (0x1ul << CAN_IF_MCON_RmtEn_Pos) /*!< CAN_IF_T::MCON: RmtEn Mask */ + +#define CAN_IF_MCON_RXIE_Pos (10) /*!< CAN_IF_T::MCON: RxIE Position */ +#define CAN_IF_MCON_RXIE_Msk (0x1ul << CAN_IF_MCON_RXIE_Pos) /*!< CAN_IF_T::MCON: RxIE Mask */ + +#define CAN_IF_MCON_TXIE_Pos (11) /*!< CAN_IF_T::MCON: TxIE Position */ +#define CAN_IF_MCON_TXIE_Msk (0x1ul << CAN_IF_MCON_TXIE_Pos) /*!< CAN_IF_T::MCON: TxIE Mask */ + +#define CAN_IF_MCON_UMASK_Pos (12) /*!< CAN_IF_T::MCON: UMask Position */ +#define CAN_IF_MCON_UMASK_Msk (0x1ul << CAN_IF_MCON_UMASK_Pos) /*!< CAN_IF_T::MCON: UMask Mask */ + +#define CAN_IF_MCON_IntPnd_Pos (13) /*!< CAN_IF_T::MCON: IntPnd Position */ +#define CAN_IF_MCON_IntPnd_Msk (0x1ul << CAN_IF_MCON_IntPnd_Pos) /*!< CAN_IF_T::MCON: IntPnd Mask */ + +#define CAN_IF_MCON_MsgLst_Pos (14) /*!< CAN_IF_T::MCON: MsgLst Position */ +#define CAN_IF_MCON_MsgLst_Msk (0x1ul << CAN_IF_MCON_MsgLst_Pos) /*!< CAN_IF_T::MCON: MsgLst Mask */ + +#define CAN_IF_MCON_NEWDAT_Pos (15) /*!< CAN_IF_T::MCON: NewDat Position */ +#define CAN_IF_MCON_NEWDAT_Msk (0x1ul << CAN_IF_MCON_NEWDAT_Pos) /*!< CAN_IF_T::MCON: NewDat Mask */ + +#define CAN_IF_DAT_A1_DATA0_Pos (0) /*!< CAN_IF_T::DAT_A1: Data_0_ Position */ +#define CAN_IF_DAT_A1_DATA0_Msk (0xfful << CAN_IF_DAT_A1_DATA0_Pos) /*!< CAN_IF_T::DAT_A1: Data_0_ Mask */ + +#define CAN_IF_DAT_A1_DATA1_Pos (8) /*!< CAN_IF_T::DAT_A1: Data_1_ Position */ +#define CAN_IF_DAT_A1_DATA1_Msk (0xfful << CAN_IF_DAT_A1_DATA1_Pos) /*!< CAN_IF_T::DAT_A1: Data_1_ Mask */ + +#define CAN_IF_DAT_A2_DATA2_Pos (0) /*!< CAN_IF_T::DAT_A2: Data_2_ Position */ +#define CAN_IF_DAT_A2_DATA2_Msk (0xfful << CAN_IF_DAT_A2_DATA2_Pos) /*!< CAN_IF_T::DAT_A2: Data_2_ Mask */ + +#define CAN_IF_DAT_A2_DATA3_Pos (8) /*!< CAN_IF_T::DAT_A2: Data_3_ Position */ +#define CAN_IF_DAT_A2_DATA3_Msk (0xfful << CAN_IF_DAT_A2_DATA3_Pos) /*!< CAN_IF_T::DAT_A2: Data_3_ Mask */ + +#define CAN_IF_DAT_B1_DATA4_Pos (0) /*!< CAN_IF_T::DAT_B1: Data_4_ Position */ +#define CAN_IF_DAT_B1_DATA4_Msk (0xfful << CAN_IF_DAT_B1_DATA4_Pos) /*!< CAN_IF_T::DAT_B1: Data_4_ Mask */ + +#define CAN_IF_DAT_B1_DATA5_Pos (8) /*!< CAN_IF_T::DAT_B1: Data_5_ Position */ +#define CAN_IF_DAT_B1_DATA5_Msk (0xfful << CAN_IF_DAT_B1_DATA5_Pos) /*!< CAN_IF_T::DAT_B1: Data_5_ Mask */ + +#define CAN_IF_DAT_B2_DATA6_Pos (0) /*!< CAN_IF_T::DAT_B2: Data_6_ Position */ +#define CAN_IF_DAT_B2_DATA6_Msk (0xfful << CAN_IF_DAT_B2_DATA6_Pos) /*!< CAN_IF_T::DAT_B2: Data_6_ Mask */ + +#define CAN_IF_DAT_B2_DATA7_Pos (8) /*!< CAN_IF_T::DAT_B2: Data_7_ Position */ +#define CAN_IF_DAT_B2_DATA7_Msk (0xfful << CAN_IF_DAT_B2_DATA7_Pos) /*!< CAN_IF_T::DAT_B2: Data_7_ Mask */ + +#define CAN_TXREQ1_TXRQST16_1_Pos (0) /*!< CAN_T::TXREQ1: TxRqst16_1 Position */ +#define CAN_TXREQ1_TXRQST16_1_Msk (0xfffful << CAN_TXREQ1_TXRQST16_1_Pos) /*!< CAN_T::TXREQ1: TxRqst16_1 Mask */ + +#define CAN_TXREQ2_TXRQST32_17_Pos (0) /*!< CAN_T::TXREQ2: TxRqst32_17 Position */ +#define CAN_TXREQ2_TXRQST32_17_Msk (0xfffful << CAN_TXREQ2_TXRQST32_17_Pos) /*!< CAN_T::TXREQ2: TxRqst32_17 Mask */ + +#define CAN_NDAT1_NewData16_1_Pos (0) /*!< CAN_T::NDAT1: NewData16_1 Position */ +#define CAN_NDAT1_NewData16_1_Msk (0xfffful << CAN_NDAT1_NewData16_1_Pos) /*!< CAN_T::NDAT1: NewData16_1 Mask */ + +#define CAN_NDAT2_NewData32_17_Pos (0) /*!< CAN_T::NDAT2: NewData32_17 Position */ +#define CAN_NDAT2_NewData32_17_Msk (0xfffful << CAN_NDAT2_NewData32_17_Pos) /*!< CAN_T::NDAT2: NewData32_17 Mask */ + +#define CAN_IPND1_IntPnd16_1_Pos (0) /*!< CAN_T::IPND1: IntPnd16_1 Position */ +#define CAN_IPND1_IntPnd16_1_Msk (0xfffful << CAN_IPND1_IntPnd16_1_Pos) /*!< CAN_T::IPND1: IntPnd16_1 Mask */ + +#define CAN_IPND2_IntPnd32_17_Pos (0) /*!< CAN_T::IPND2: IntPnd32_17 Position */ +#define CAN_IPND2_IntPnd32_17_Msk (0xfffful << CAN_IPND2_IntPnd32_17_Pos) /*!< CAN_T::IPND2: IntPnd32_17 Mask */ + +#define CAN_MVLD1_MsgVal16_1_Pos (0) /*!< CAN_T::MVLD1: MsgVal16_1 Position */ +#define CAN_MVLD1_MsgVal16_1_Msk (0xfffful << CAN_MVLD1_MsgVal16_1_Pos) /*!< CAN_T::MVLD1: MsgVal16_1 Mask */ + +#define CAN_MVLD2_MsgVal32_17_Pos (0) /*!< CAN_T::MVLD2: MsgVal32_17 Position */ +#define CAN_MVLD2_MsgVal32_17_Msk (0xfffful << CAN_MVLD2_MsgVal32_17_Pos) /*!< CAN_T::MVLD2: MsgVal32_17 Mask */ + +#define CAN_WU_EN_WAKUP_EN_Pos (0) /*!< CAN_T::WU_EN: WAKUP_EN Position */ +#define CAN_WU_EN_WAKUP_EN_Msk (0x1ul << CAN_WU_EN_WAKUP_EN_Pos) /*!< CAN_T::WU_EN: WAKUP_EN Mask */ + +#define CAN_WU_STATUS_WAKUP_STS_Pos (0) /*!< CAN_T::WU_STATUS: WAKUP_STS Position */ +#define CAN_WU_STATUS_WAKUP_STS_Msk (0x1ul << CAN_WU_STATUS_WAKUP_STS_Pos) /*!< CAN_T::WU_STATUS: WAKUP_STS Mask */ + +/**@}*/ /* CAN_CONST */ +/**@}*/ /* end of CAN register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __CAN_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/ccap_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/ccap_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..3798f50b96ef09d4f4c997a13d8ba3f609d6bcf8 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/ccap_reg.h @@ -0,0 +1,496 @@ +/**************************************************************************//** + * @file ccap_reg.h + * @version V1.00 + * @brief CCAP register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CCAP_REG_H__ +#define __CCAP_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup CCAP Camera Capture Interface Controller (CCAP) + Memory Mapped Structure for CCAP Controller +@{ */ + + +typedef struct { + + + /** + * @var CCAP_T::CTL + * Offset: 0x00 Camera Capture Interface Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CCAPEN |Camera Capture Interface Enable + * | | |0 = Camera Capture Interface Disabled. + * | | |1 = Camera Capture Interface Enabled. + * |[3] |ADDRSW |Packet Buffer Address Switch + * | | |0 = Packet buffer address switch Disabled. + * | | |1 = Packet buffer address switch Enabled. + * |[6] |PKTEN |Packet Output Enable + * | | |0 = Packet output Disabled. + * | | |1 = Packet output Enabled. + * |[7] |MONO |Monochrome CMOS Sensor Select + * | | |0 = Color CMOS Sensor. + * | | |1 = Monochrome CMOS Sensor. The U/V components are ignored when the MONO is enabled. + * |[16] |SHUTTER |Image Capture Interface Automatically Disable The Capture Interface After A Frame Had Been Captured + * | | |0 = Shutter Disabled. + * | | |1 = Shutter Enabled. + * |[20] |UPDATE |Update Register At New Frame + * | | |0 = Update register at new frame Disabled. + * | | |1 = Update register at new frame Enabled (Auto clear to 0 when register updated). + * |[24] |VPRST |Capture Interface Reset + * | | |0 = Capture interface reset Disabled. + * | | |1 = Capture interface reset Enabled. + * @var CCAP_T::PAR + * Offset: 0x04 Camera Capture Interface Parameter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |INFMT |Sensor Input Data Format + * | | |0 = YCbCr422. + * | | |1 = RGB565. + * |[1] |SENTYPE |Sensor Input Type + * | | |0 = CCIR601. + * | | |1 = CCIR656, VSync & Hsync embedded in the data signal. + * |[2:3] |INDATORD |Sensor Input Data Order + * | | |If INFMT = 0 (YCbCr),. + * | | | Byte 0 1 2 3 + * | | |00 = Y0 U0 Y1 V0. + * | | |01 = Y0 V0 Y1 U0. + * | | |10 = U0 Y0 V0 Y1. + * | | |11 = V0 Y0 U0 Y1. + * | | |If INFMT = 1 (RGB565),. + * | | |00 = Byte0[R[4:0] G[5:3]] Byte1[G[2:0] B[4:0]] + * | | |01 = Byte0[B[4:0] G[5:3]] Byte1[G[2:0] R[4:0]] + * | | |10 = Byte0[G[2:0] B[4:0]] Byte1[R[4:0] G[5:3]] + * | | |11 = Byte0[G[2:0] R[4:0]] Byte1[B[4:0] G[5:3]] + * |[4:5] |OUTFMT |Image Data Format Output To System Memory + * | | |00 = YCbCr422. + * | | |01 = Only output Y. + * | | |10 = RGB555. + * | | |11 = RGB565. + * |[6] |RANGE |Scale Input YUV CCIR601 Color Range To Full Range + * | | |0 = default. + * | | |1 = Scale to full range. + * |[8] |PCLKP |Sensor Pixel Clock Polarity + * | | |0 = Input video data and signals are latched by falling edge of Pixel Clock. + * | | |1 = Input video data and signals are latched by rising edge of Pixel Clock. + * |[9] |HSP |Sensor Hsync Polarity + * | | |0 = Sync Low. + * | | |1 = Sync High. + * |[10] |VSP |Sensor Vsync Polarity + * | | |0 = Sync Low. + * | | |1 = Sync High. + * |[18] |FBB |Field By Blank + * | | |Hardware will tag field0 or field1 by vertical blanking instead of FIELD flag in CCIR-656 mode. + * | | |0 = Field by blank Disabled. + * | | |1 = Field by blank Enabled. + * @var CCAP_T::INT + * Offset: 0x08 Camera Capture Interface Interrupt Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |VINTF |Video Frame End Interrupt + * | | |If this bit shows 1, receiving a frame completed. + * | | |Write 1 to clear it. + * |[1] |MEINTF |Bus Master Transfer Error Interrupt + * | | |If this bit shows 1, Transfer Error occurred. Write 1 to clear it. + * |[3] |ADDRMINTF |Memory Address Match Interrupt + * | | |If this bit shows 1, Memory Address Match Interrupt occurred. + * | | |Write 1 to clear it. + * |[4] |MDINTF |Motion Detection Output Finish Interrupt + * | | |If this bit shows 1, Motion Detection Output Finish Interrupt occurred. + * | | |Write 1 to clear it. + * |[16] |VIEN |Video Frame End Interrupt Enable + * | | |0 = Video frame end interrupt Disabled. + * | | |1 = Video frame end interrupt Enabled. + * |[17] |MEIEN |System Memory Error Interrupt Enable + * | | |0 = System memory error interrupt Disabled. + * | | |1 = System memory error interrupt Enabled. + * |[19] |ADDRMIEN |Address Match Interrupt Enable + * | | |0 = Address match interrupt Disabled. + * | | |1 = Address match interrupt Enabled. + * @var CCAP_T::POSTERIZE + * Offset: 0x0C YUV Component Posterizing Factor Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0:7] |VCOMP |V Component Posterizing Factor + * | | |Final_V_Out = Original_V[7:0] & V_Posterizing_Factor. + * |[8:15] |UCOMP |U Component Posterizing Factor + * | | |Final_U_Out = Original_U[7:0] & U_Posterizing_Factor. + * |[16:23] |YCOMP |Y Component Posterizing Factor + * | | |Final_Y_Out = Original_Y[7:0] & Y_Posterizing_Factor. + * @var CCAP_T::MD + * Offset: 0x10 Motion Detection Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MDEN |Motion Detection Enable + * | | |0 = CCAP_MD Disabled. + * | | |1 = CCAP_MD Enabled. + * |[8] |MDBS |Motion Detection Block Size + * | | |0 = 16x16. + * | | |1 = 8x8. + * |[9] |MDSM |Motion Detection Save Mode + * | | |0 = 1 bit DIFF + 7 bit Y Differential. + * | | |1 = 1 bit DIFF only. + * |[10:11] |MDDF |Motion Detection Detect Frequency + * | | |00 = Each frame. + * | | |01 = Every 2 frame. + * | | |10 = Every 3 frame. + * | | |11 = Every 4 frame. + * |[16:20] |MDTHR |Motion Detection Differential Threshold + * @var CCAP_T::MDADDR + * Offset: 0x14 Motion Detection Output Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0:31] |MDADDR |Motion Detection Output Address Register (Word Alignment) + * @var CCAP_T::MDYADDR + * Offset: 0x18 Motion Detection Temp Y Output Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0:31] |MDYADDR |Motion Detection Temp Y Output Address Register (Word Alignment) + * @var CCAP_T::SEPIA + * Offset: 0x1C Sepia Effect Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0:7] |VCOMP |Define the constant V component while Sepia color effect is turned on. + * |[8:15] |UCOMP |Define the constant U component while Sepia color effect is turned on. + * @var CCAP_T::CWSP + * Offset: 0x20 Cropping Window Starting Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0:11] |CWSADDRH |Cropping Window Horizontal Starting Address + * |[16:26] |CWSADDRV |Cropping Window Vertical Starting Address + * @var CCAP_T::CWS + * Offset: 0x24 Cropping Window Size Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0:11] |CIWW |Cropping Image Window Width + * |[16:26] |CIWH |Cropping Image Window Height + * @var CCAP_T::PKTSL + * Offset: 0x28 Packet Scaling Vertical/Horizontal Factor Register (LSB) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0:7] |PKTSHML |Packet Scaling Horizontal Factor M (Lower 8-Bit) + * | | |Specifies the lower 8-bit of denominator part (M) of the horizontal scaling factor. + * | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSHMH) to form a 16-bit denominator (M) of vertical factor. + * | | |The output image width will be equal to the image width * N/M. + * | | |Note: The value of N must be equal to or less than M. + * |[8:15] |PKTSHNL |Packet Scaling Horizontal Factor N (Lower 8-Bit) + * | | |Specify the lower 8-bit of numerator part (N) of the horizontal scaling factor. + * | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSHNH) to form a 16-bit numerator of horizontal factor. + * |[16:23] |PKTSVML |Packet Scaling Vertical Factor M (Lower 8-Bit) + * | | |Specify the lower 8-bit of denominator part (M) of the vertical scaling factor. + * | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSVMH) to form a 16-bit denominator (M) of vertical factor. + * | | |The output image width will be equal to the image height * N/M. + * | | |Note: The value of N must be equal to or less than M. + * |[24:31] |PKTSVNL |Packet Scaling Vertical Factor N (Lower 8-Bit) + * | | |Specify the lower 8-bit of numerator part (N) of the vertical scaling factor. + * | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSVNH) to form a 16-bit numerator of vertical factor + * @var CCAP_T::PLNSL + * Offset: 0x2C Planar Scaling Vertical/Horizontal Factor Register (LSB) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0:7] |PLNSHML |Planar Scaling Horizontal Factor M (Lower 8-Bit) + * | | |Specify the lower 8-bit of denominator part (M) of the horizontal scaling factor. + * | | |The lower 8-bit will be cascaded with higher 8-bit (PNDSHMH) to form a 16-bit denominator (M) of vertical factor. + * | | |The output image width will be equal to the image width * N/M. + * | | |Note: The value of N must be equal to or less than M. + * |[8:15] |PLNSHNL |Planar Scaling Horizontal Factor N (Lower 8-Bit) + * | | |Specify the lower 8-bit of numerator part (N) of the horizontal scaling factor. + * | | |The lower 8-bit will be cascaded with higher 8-bit (PNDSHNH) to form a 16-bit numerator of horizontal factor. + * |[16:23] |PLNSVML |Planar Scaling Vertical Factor M (Lower 8-Bit) + * | | |Specify the lower 8-bit of denominator part (M) of the vertical scaling factor. + * | | |The lower 8-bit will be cascaded with higher 8-bit (PNDSVMH) to form a 16-bit denominator (M) of vertical factor. + * | | |The output image width will be equal to the image height * N/M. + * | | |Note: The value of N must be equal to or less than M. + * |[24:31] |PLNSVNL |Planar Scaling Vertical Factor N (Lower 8-Bit) + * | | |Specify the lower 8-bit of numerator part (N) of the vertical scaling factor. + * | | |The lower 8-bit will be cascaded with higher 8-bit (PNDSVNH) to form a 16-bit numerator of vertical factor. + * @var CCAP_T::FRCTL + * Offset: 0x30 Scaling Frame Rate Factor Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0:5] |FRM |Scaling Frame Rate Factor M + * | | |Specify the denominator part (M) of the frame rate scaling factor. + * | | |The output image frame rate will be equal to input image frame rate * (N/M). + * | | |Note: The value of N must be equal to or less than M. + * |[8:13] |FRN |Scaling Frame Rate Factor N + * | | |Specify the denominator part (N) of the frame rate scaling factor. + * @var CCAP_T::STRIDE + * Offset: 0x34 Frame Output Pixel Stride Width Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0:13] |PKTSTRIDE |Packet Frame Output Pixel Stride Width + * | | |The output pixel stride size of packet pipe. + * |[16:29] |PLNSTRIDE |Planar Frame Output Pixel Stride Width + * | | |The output pixel stride size of planar pipe. + * @var CCAP_T::FIFOTH + * Offset: 0x3C FIFO Threshold Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0:3] |PLNVFTH |Planar V FIFO Threshold + * |[8:11] |PLNUFTH |Planar U FIFO Threshold + * |[16:20] |PLNYFTH |Planar Y FIFO Threshold + * |[24:28] |PKTFTH |Packet FIFO Threshold + * |[31] |OVF |FIFO Overflow Flag + * @var CCAP_T::CMPADDR + * Offset: 0x40 Compare Memory Base Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0:31] |CMPADDR |Compare Memory Base Address + * | | |Word aligns address; ignore the bits [1:0]. + * @var CCAP_T::LUMA_Y1_THD + * Offset: 0x44 Luminance Y8 to Y1 Threshold Value Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :-----------: | :---- | + * |[0:8] |LUMA_Y1_THRESH |Luminance Y8 to Y1 Threshold Value + * | | |Specify the 8-bit threshold value for the luminance Y bit-8 to the luminance Y 1-bit conversion. + * @var CCAP_T::PKTSM + * Offset: 0x48 Packet Scaling Vertical/Horizontal Factor Register (MSB) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0:7] |PKTSHMH |Packet Scaling Horizontal Factor M (Higher 8-Bit) + * | | |Specify the lower 8-bit of denominator part (M) of the horizontal scaling factor. + * | | |Please refer to the register CCAP_PKTSL?for the detailed operation. + * |[8:15] |PKTSHNH |Packet Scaling Horizontal Factor N (Higher 8-Bit) + * | | |Specify the lower 8-bit of numerator part (N) of the horizontal scaling factor. + * | | |Please refer to the register CCAP_PKTSL for the detailed operation. + * |[16:23] |PKTSVMH |Packet Scaling Vertical Factor M (Higher 8-Bit) + * | | |Specify the lower 8-bit of denominator part (M) of the vertical scaling factor. + * | | |Please refer to the register CCAP_PKTSL to check the cooperation between these two registers. + * |[24:31] |PKTSVNH |Packet Scaling Vertical Factor N (Higher 8-Bit) + * | | |Specify the higher 8-bit of numerator part (N) of the vertical scaling factor. + * | | |Please refer to the register CCAP_PKTSL?to check the cooperation between these two registers. + * @var CCAP_T::PKTBA0 + * Offset: 0x60 System Memory Packet Base Address 0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0:31] |BASEADDR |System Memory Packet Base Address 0 + * | | |Word aligns address; ignore the bits [1:0]. + */ + __IO uint32_t CTL; + __IO uint32_t PAR; + __IO uint32_t INT; + __IO uint32_t POSTERIZE; + __IO uint32_t MD; + __IO uint32_t MDADDR; + __IO uint32_t MDYADDR; + __IO uint32_t SEPIA; + __IO uint32_t CWSP; + __IO uint32_t CWS; + __IO uint32_t PKTSL; + __IO uint32_t PLNSL; + __IO uint32_t FRCTL; + __IO uint32_t STRIDE; + /// @cond HIDDEN_SYMBOLS + uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t FIFOTH; + __IO uint32_t CMPADDR; + __IO uint32_t LUMA_Y1_THD; + __IO uint32_t PKTSM; + /// @cond HIDDEN_SYMBOLS + uint32_t RESERVE2[5]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t PKTBA0; +} CCAP_T; + +/** + @addtogroup CCAP_CONST CCAP Bit Field Definition + Constant Definitions for CCAP Controller +@{ */ + +#define CCAP_CTL_CCAPEN_Pos (0) /*!< CCAP_T::CTL: CCAPEN Position */ +#define CCAP_CTL_CCAPEN_Msk (0x1ul << CCAP_CTL_CCAPEN_Pos) /*!< CCAP_T::CTL: CCAPEN Mask */ + +#define CCAP_CTL_ADDRSW_Pos (3) /*!< CCAP_T::CTL: ADDRSW Position */ +#define CCAP_CTL_ADDRSW_Msk (0x1ul << CCAP_CTL_ADDRSW_Pos) /*!< CCAP_T::CTL: ADDRSW Mask */ + +#define CCAP_CTL_PLNEN_Pos (5) /*!< CCAP_T::CTL: PLNEN Position */ +#define CCAP_CTL_PLNEN_Msk (0x1ul << CCAP_CTL_PLNEN_Pos) /*!< CCAP_T::CTL: PLNEN Mask */ + +#define CCAP_CTL_PKTEN_Pos (6) /*!< CCAP_T::CTL: PKTEN Position */ +#define CCAP_CTL_PKTEN_Msk (0x1ul << CCAP_CTL_PKTEN_Pos) /*!< CCAP_T::CTL: PKTEN Mask */ + +#define CCAP_CTL_MONO_Pos (7) /*!< CCAP_T::CTL: MONO Position */ +#define CCAP_CTL_MONO_Msk (0x1ul << CCAP_CTL_MONO_Pos) /*!< CCAP_T::CTL: MONO Mask */ + +#define CCAP_CTL_SHUTTER_Pos (16) /*!< CCAP_T::CTL: SHUTTER Position */ +#define CCAP_CTL_SHUTTER_Msk (0x1ul << CCAP_CTL_SHUTTER_Pos) /*!< CCAP_T::CTL: SHUTTER Mask */ + +#define CCAP_CTL_MY4_SWAP_Pos (17) /*!< CCAP_T::CTL: MY4_SWAP Position */ +#define CCAP_CTL_MY4_SWAP_Msk (0x1ul << CCAP_CTL_MY4_SWAP_Pos) /*!< CCAP_T::CTL: MY4_SWAP Mask */ + +#define CCAP_CTL_MY8_MY4_Pos (18) /*!< CCAP_T::CTL: MY8_MY4 Position */ +#define CCAP_CTL_MY8_MY4_Msk (0x1ul << CCAP_CTL_MY8_MY4_Pos) /*!< CCAP_T::CTL: MY8_MY4 Mask */ + +#define CCAP_CTL_Luma_Y_One_Pos (19) /*!< CCAP_T::CTL: Luma_Y_One Position */ +#define CCAP_CTL_Luma_Y_One_Msk (0x1ul << CCAP_CTL_Luma_Y_One_Pos) /*!< CCAP_T::CTL: Luma_Y_One Mask */ + +#define CCAP_CTL_UPDATE_Pos (20) /*!< CCAP_T::CTL: UPDATE Position */ +#define CCAP_CTL_UPDATE_Msk (0x1ul << CCAP_CTL_UPDATE_Pos) /*!< CCAP_T::CTL: UPDATE Mask */ + +#define CCAP_CTL_VPRST_Pos (24) /*!< CCAP_T::CTL: VPRST Position */ +#define CCAP_CTL_VPRST_Msk (0x1ul << CCAP_CTL_VPRST_Pos) /*!< CCAP_T::CTL: VPRST Mask */ + +#define CCAP_PAR_INFMT_Pos (0) /*!< CCAP_T::PAR: INFMT Position */ +#define CCAP_PAR_INFMT_Msk (0x1ul << CCAP_PAR_INFMT_Pos) /*!< CCAP_T::PAR: INFMT Mask */ + +#define CCAP_PAR_SENTYPE_Pos (1) /*!< CCAP_T::PAR: SENTYPE Position */ +#define CCAP_PAR_SENTYPE_Msk (0x1ul << CCAP_PAR_SENTYPE_Pos) /*!< CCAP_T::PAR: SENTYPE Mask */ + +#define CCAP_PAR_INDATORD_Pos (2) /*!< CCAP_T::PAR: INDATORD Position */ +#define CCAP_PAR_INDATORD_Msk (0x3ul << CCAP_PAR_INDATORD_Pos) /*!< CCAP_T::PAR: INDATORD Mask */ + +#define CCAP_PAR_OUTFMT_Pos (4) /*!< CCAP_T::PAR: OUTFMT Position */ +#define CCAP_PAR_OUTFMT_Msk (0x3ul << CCAP_PAR_OUTFMT_Pos) /*!< CCAP_T::PAR: OUTFMT Mask */ + +#define CCAP_PAR_RANGE_Pos (6) /*!< CCAP_T::PAR: RANGE Position */ +#define CCAP_PAR_RANGE_Msk (0x1ul << CCAP_PAR_RANGE_Pos) /*!< CCAP_T::PAR: RANGE Mask */ + +#define CCAP_PAR_PLNFMT_Pos (7) /*!< CCAP_T::PAR: PLNFMT Position */ +#define CCAP_PAR_PLNFMT_Msk (0x1ul << CCAP_PAR_PLNFMT_Pos) /*!< CCAP_T::PAR: PLNFMT Mask */ + +#define CCAP_PAR_PCLKP_Pos (8) /*!< CCAP_T::PAR: PCLKP Position */ +#define CCAP_PAR_PCLKP_Msk (0x1ul << CCAP_PAR_PCLKP_Pos) /*!< CCAP_T::PAR: PCLKP Mask */ + +#define CCAP_PAR_HSP_Pos (9) /*!< CCAP_T::PAR: HSP Position */ +#define CCAP_PAR_HSP_Msk (0x1ul << CCAP_PAR_HSP_Pos) /*!< CCAP_T::PAR: HSP Mask */ + +#define CCAP_PAR_VSP_Pos (10) /*!< CCAP_T::PAR: VSP Position */ +#define CCAP_PAR_VSP_Msk (0x1ul << CCAP_PAR_VSP_Pos) /*!< CCAP_T::PAR: VSP Mask */ + +#define CCAP_PAR_COLORCTL_Pos (11) /*!< CCAP_T::PAR: COLORCTL Position */ +#define CCAP_PAR_COLORCTL_Msk (0x3ul << CCAP_PAR_COLORCTL_Pos) /*!< CCAP_T::PAR: COLORCTL Mask */ + +#define CCAP_PAR_FBB_Pos (18) /*!< CCAP_T::PAR: FBB Position */ +#define CCAP_PAR_FBB_Msk (0x1ul << CCAP_PAR_FBB_Pos) /*!< CCAP_T::PAR: FBB Mask */ + +#define CCAP_INT_VINTF_Pos (0) /*!< CCAP_T::INT: VINTF Position */ +#define CCAP_INT_VINTF_Msk (0x1ul << CCAP_INT_VINTF_Pos) /*!< CCAP_T::INT: VINTF Mask */ + +#define CCAP_INT_MEINTF_Pos (1) /*!< CCAP_T::INT: MEINTF Position */ +#define CCAP_INT_MEINTF_Msk (0x1ul << CCAP_INT_MEINTF_Pos) /*!< CCAP_T::INT: MEINTF Mask */ + +#define CCAP_INT_ADDRMINTF_Pos (3) /*!< CCAP_T::INT: ADDRMINTF Position */ +#define CCAP_INT_ADDRMINTF_Msk (0x1ul << CCAP_INT_ADDRMINTF_Pos) /*!< CCAP_T::INT: ADDRMINTF Mask */ + +#define CCAP_INT_MDINTF_Pos (4) /*!< CCAP_T::INT: MDINTF Position */ +#define CCAP_INT_MDINTF_Msk (0x1ul << CCAP_INT_MDINTF_Pos) /*!< CCAP_T::INT: MDINTF Mask */ + +#define CCAP_INT_VIEN_Pos (16) /*!< CCAP_T::INT: VIEN Position */ +#define CCAP_INT_VIEN_Msk (0x1ul << CCAP_INT_VIEN_Pos) /*!< CCAP_T::INT: VIEN Mask */ + +#define CCAP_INT_MEIEN_Pos (17) /*!< CCAP_T::INT: MEIEN Position */ +#define CCAP_INT_MEIEN_Msk (0x1ul << CCAP_INT_MEIEN_Pos) /*!< CCAP_T::INT: MEIEN Mask */ + +#define CCAP_INT_ADDRMIEN_Pos (19) /*!< CCAP_T::INT: ADDRMIEN Position */ +#define CCAP_INT_ADDRMIEN_Msk (0x1ul << CCAP_INT_ADDRMIEN_Pos) /*!< CCAP_T::INT: ADDRMIEN Mask */ + +#define CCAP_CWSP_CWSADDRH_Pos (0) /*!< CCAP_T::CWSP: CWSADDRH Position */ +#define CCAP_CWSP_CWSADDRH_Msk (0xffful << CCAP_CWSP_CWSADDRH_Pos) /*!< CCAP_T::CWSP: CWSADDRH Mask */ + +#define CCAP_CWSP_CWSADDRV_Pos (16) /*!< CCAP_T::CWSP: CWSADDRV Position */ +#define CCAP_CWSP_CWSADDRV_Msk (0x7fful << CCAP_CWSP_CWSADDRV_Pos) /*!< CCAP_T::CWSP: CWSADDRV Mask */ + +#define CCAP_CWS_CWW_Pos (0) /*!< CCAP_T::CWS: CWW Position */ +#define CCAP_CWS_CWW_Msk (0xffful << CCAP_CWS_CWW_Pos) /*!< CCAP_T::CWS: CWW Mask */ +#define CCAP_CWS_CWH_Pos (16) /*!< CCAP_T::CWS: CIWH Position */ +#define CCAP_CWS_CWH_Msk (0x7fful << CCAP_CWS_CWH_Pos) /*!< CCAP_T::CWS: CIWH Mask */ + +#define CCAP_PKTSL_PKTSHML_Pos (0) /*!< CCAP_T::PKTSL: PKTSHML Position */ +#define CCAP_PKTSL_PKTSHML_Msk (0xfful << CCAP_PKTSL_PKTSHML_Pos) /*!< CCAP_T::PKTSL: PKTSHML Mask */ + +#define CCAP_PKTSL_PKTSHNL_Pos (8) /*!< CCAP_T::PKTSL: PKTSHNL Position */ +#define CCAP_PKTSL_PKTSHNL_Msk (0xfful << CCAP_PKTSL_PKTSHNL_Pos) /*!< CCAP_T::PKTSL: PKTSHNL Mask */ + +#define CCAP_PKTSL_PKTSVML_Pos (16) /*!< CCAP_T::PKTSL: PKTSVML Position */ +#define CCAP_PKTSL_PKTSVML_Msk (0xfful << CCAP_PKTSL_PKTSVML_Pos) /*!< CCAP_T::PKTSL: PKTSVML Mask */ + +#define CCAP_PKTSL_PKTSVNL_Pos (24) /*!< CCAP_T::PKTSL: PKTSVNL Position */ +#define CCAP_PKTSL_PKTSVNL_Msk (0xfful << CCAP_PKTSL_PKTSVNL_Pos) /*!< CCAP_T::PKTSL: PKTSVNL Mask */ + +#define CCAP_FRCTL_FRM_Pos (0) /*!< CCAP_T::FRCTL: FRM Position */ +#define CCAP_FRCTL_FRM_Msk (0x3ful << CCAP_FRCTL_FRM_Pos) /*!< CCAP_T::FRCTL: FRM Mask */ + +#define CCAP_FRCTL_FRN_Pos (8) /*!< CCAP_T::FRCTL: FRN Position */ +#define CCAP_FRCTL_FRN_Msk (0x3ful << CCAP_FRCTL_FRN_Pos) /*!< CCAP_T::FRCTL: FRN Mask */ + +#define CCAP_STRIDE_PKTSTRIDE_Pos (0) /*!< CCAP_T::STRIDE: PKTSTRIDE Position */ +#define CCAP_STRIDE_PKTSTRIDE_Msk (0x3ffful << CCAP_STRIDE_PKTSTRIDE_Pos) /*!< CCAP_T::STRIDE: PKTSTRIDE Mask */ + +#define CCAP_STRIDE_PLNSTRIDE_Pos (16) /*!< CCAP_T::STRIDE: PLNSTRIDE Position */ +#define CCAP_STRIDE_PLNSTRIDE_Msk (0x3ffful << CCAP_STRIDE_PLNSTRIDE_Pos) /*!< CCAP_T::STRIDE: PLNSTRIDE Mask */ + +#define CCAP_FIFOTH_PLNVFTH_Pos (0) /*!< CCAP_T::FIFOTH: PLNVFTH Position */ +#define CCAP_FIFOTH_PLNVFTH_Msk (0xful << CCAP_FIFOTH_PLNVFTH_Pos) /*!< CCAP_T::FIFOTH: PLNVFTH Mask */ + +#define CCAP_FIFOTH_PLNUFTH_Pos (8) /*!< CCAP_T::FIFOTH: PLNUFTH Position */ +#define CCAP_FIFOTH_PLNUFTH_Msk (0xful << CCAP_FIFOTH_PLNUFTH_Pos) /*!< CCAP_T::FIFOTH: PLNUFTH Mask */ + +#define CCAP_FIFOTH_PLNYFTH_Pos (16) /*!< CCAP_T::FIFOTH: PLNYFTH Position */ +#define CCAP_FIFOTH_PLNYFTH_Msk (0x1ful << CCAP_FIFOTH_PLNYFTH_Pos) /*!< CCAP_T::FIFOTH: PLNYFTH Mask */ + +#define CCAP_FIFOTH_PKTFTH_Pos (24) /*!< CCAP_T::FIFOTH: PKTFTH Position */ +#define CCAP_FIFOTH_PKTFTH_Msk (0x1ful << CCAP_FIFOTH_PKTFTH_Pos) /*!< CCAP_T::FIFOTH: PKTFTH Mask */ + +#define CCAP_FIFOTH_OVF_Pos (31) /*!< CCAP_T::FIFOTH: OVF Position */ +#define CCAP_FIFOTH_OVF_Msk (0x1ul << CCAP_FIFOTH_OVF_Pos) /*!< CCAP_T::FIFOTH: OVF Mask */ + +#define CCAP_CMPADDR_CMPADDR_Pos (0) /*!< CCAP_T::CMPADDR: CMPADDR Position */ +#define CCAP_CMPADDR_CMPADDR_Msk (0xfffffffful << CCAP_CMPADDR_CMPADDR_Pos) /*!< CCAP_T::CMPADDR: CMPADDR Mask */ + +#define CCAP_PKTSM_PKTSHMH_Pos (0) /*!< CCAP_T::PKTSM: PKTSHMH Position */ +#define CCAP_PKTSM_PKTSHMH_Msk (0xfful << CCAP_PKTSM_PKTSHMH_Pos) /*!< CCAP_T::PKTSM: PKTSHMH Mask */ + +#define CCAP_PKTSM_PKTSHNH_Pos (8) /*!< CCAP_T::PKTSM: PKTSHNH Position */ +#define CCAP_PKTSM_PKTSHNH_Msk (0xfful << CCAP_PKTSM_PKTSHNH_Pos) /*!< CCAP_T::PKTSM: PKTSHNH Mask */ + +#define CCAP_PKTSM_PKTSVMH_Pos (16) /*!< CCAP_T::PKTSM: PKTSVMH Position */ +#define CCAP_PKTSM_PKTSVMH_Msk (0xfful << CCAP_PKTSM_PKTSVMH_Pos) /*!< CCAP_T::PKTSM: PKTSVMH Mask */ + +#define CCAP_PKTSM_PKTSVNH_Pos (24) /*!< CCAP_T::PKTSM: PKTSVNH Position */ +#define CCAP_PKTSM_PKTSVNH_Msk (0xfful << CCAP_PKTSM_PKTSVNH_Pos) /*!< CCAP_T::PKTSM: PKTSVNH Mask */ + +#define CCAP_PKTBA0_BASEADDR_Pos (0) /*!< CCAP_T::PKTBA0: BASEADDR Position */ +#define CCAP_PKTBA0_BASEADDR_Msk (0xfffffffful << CCAP_PKTBA0_BASEADDR_Pos) /*!< CCAP_T::PKTBA0: BASEADDR Mask */ + +/**@}*/ /* CCAP_CONST */ +/**@}*/ /* end of CCAP register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __CCAP_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/clk_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/clk_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..68016d805c57acd1cd8ed544ace7373e4913662b --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/clk_reg.h @@ -0,0 +1,1698 @@ +/**************************************************************************//** + * @file clk_reg.h + * @version V1.00 + * @brief CLK register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CLK_REG_H__ +#define __CLK_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup CLK System Clock Controller(CLK) + Memory Mapped Structure for CLK Controller +@{ */ + +typedef struct +{ + + + /** + * @var CLK_T::PWRCTL + * Offset: 0x00 System Power-down Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |HXTEN |HXT Enable Bit (Write Protect) + * | | |The bit default value is set by flash controller user configuration register CONFIG0 [26] + * | | |When the default clock source is from HXT, this bit is set to 1 automatically. + * | | |0 = 4~24 MHz external high speed crystal (HXT) Disabled. + * | | |1 = 4~24 MHz external high speed crystal (HXT) Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[1] |LXTEN |LXT Enable Bit (Write Protect) + * | | |0 = 32.768 kHz external low speed crystal (LXT) Disabled. + * | | |1 = 32.768 kHz external low speed crystal (LXT) Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[2] |HIRCEN |HIRC Enable Bit (Write Protect) + * | | |0 = 12 MHz internal high speed RC oscillator (HIRC) Disabled. + * | | |1 = 12 MHz internal high speed RC oscillator (HIRC) Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |LIRCEN |LIRC Enable Bit (Write Protect) + * | | |0 = 10 kHz internal low speed RC oscillator (LIRC) Disabled. + * | | |1 = 10 kHz internal low speed RC oscillator (LIRC) Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[4] |PDWKDLY |Enable the Wake-up Delay Counter (Write Protect) + * | | |When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable. + * | | |The delayed clock cycle is 4096 clock cycles when chip works at 4~24 MHz external high speed crystal oscillator (HXT), and 256 clock cycles when chip works at 12 MHz internal high speed RC oscillator (HIRC). + * | | |0 = Clock cycles delay Disabled. + * | | |1 = Clock cycles delay Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[5] |PDWKIEN |Power-down Mode Wake-up Interrupt Enable Bit (Write Protect) + * | | |0 = Power-down mode wake-up interrupt Disabled. + * | | |1 = Power-down mode wake-up interrupt Enabled. + * | | |Note1: The interrupt will occur when both PDWKIF and PDWKIEN are high. + * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[6] |PDWKIF |Power-down Mode Wake-up Interrupt Status + * | | |Set by "Power-down wake-up event", it indicates that resume from Power-down mode. + * | | |The flag is set if any wake-up source is occurred. Refer Power Modes and Wake-up Sources chapter. + * | | |Note1: Write 1 to clear the bit to 0. + * | | |Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1. + * |[7] |PDEN |System Power-down Enable (Write Protect) + * | | |When this bit is set to 1, Power-down mode is enabled and chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode. + * | | |When chip wakes up from Power-down mode, this bit is auto cleared + * | | |Users need to set this bit again for next Power-down. + * | | |In Power-down mode, HXT and the HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode. + * | | |In Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection + * | | |The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC. + * | | |0 = Chip will not enter Power-down mode after CPU sleep command WFI. + * | | |1 = Chip enters Power-down mode after CPU sleep command WFI. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[11:10] |HXTGAIN |HXT Gain Control Bit (Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |Gain control is used to enlarge the gain of crystal to make sure crystal work normally + * | | |If gain control is enabled, crystal will consume more power than gain control off. + * | | |00 = HXT frequency is lower than from 8 MHz. + * | | |01 = HXT frequency is from 8 MHz to 12 MHz. + * | | |10 = HXT frequency is from 12 MHz to 16 MHz. + * | | |11 = HXT frequency is higher than 16 MHz. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[12] |HXTSELTYP |HXT Crystal Type Select Bit (Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |0 = Select INV type. + * | | |1 = Select GM type. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[13] |HXTTBEN |HXT Crystal TURBO Mode (Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |0 = HXT Crystal TURBO mode disabled. + * | | |1 = HXT Crystal TURBO mode enabled. + * |[17:16] |HIRCSTBS |HIRC Stable Count Select (Write Protect) + * | | |00 = HIRC stable count is 64 clocks. + * | | |01 = HIRC stable count is 24 clocks. + * | | |others = Reserved. + * |[18] |HIRCEN |HIRC48M Enable Bit (Write Protect) + * | | |0 = 48 MHz internal high speed RC oscillator (HIRC) Disabled. + * | | |1 = 48 MHz internal high speed RC oscillator (HIRC) Enabled. + * @var CLK_T::AHBCLK + * Offset: 0x04 AHB Devices Clock Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |PDMACKEN |PDMA Controller Clock Enable Bit + * | | |0 = PDMA peripheral clock Disabled. + * | | |1 = PDMA peripheral clock Enabled. + * |[2] |ISPCKEN |Flash ISP Controller Clock Enable Bit + * | | |0 = Flash ISP peripheral clock Disabled. + * | | |1 = Flash ISP peripheral clock Enabled. + * |[3] |EBICKEN |EBI Controller Clock Enable Bit + * | | |0 = EBI peripheral clock Disabled. + * | | |1 = EBI peripheral clock Enabled. + * |[5] |EMACCKEN |Ethernet Controller Clock Enable Bit + * | | |0 = Ethernet Controller engine clock Disabled. + * | | |1 = Ethernet Controller engine clock Enabled. + * |[6] |SDH0CKEN |SD0 Controller Clock Enable Bit + * | | |0 = SD0 engine clock Disabled. + * | | |1 = SD0 engine clock Enabled. + * |[7] |CRCCKEN |CRC Generator Controller Clock Enable Bit + * | | |0 = CRC peripheral clock Disabled. + * | | |1 = CRC peripheral clock Enabled. + * |[10] |HSUSBDCKEN|HSUSB Device Clock Enable Bit + * | | |0 = HSUSB device controller's clock Disabled. + * | | |1 = HSUSB device controller's clock Enabled. + * |[12] |CRPTCKEN |Cryptographic Accelerator Clock Enable Bit + * | | |0 = Cryptographic Accelerator clock Disabled. + * | | |1 = Cryptographic Accelerator clock Enabled. + * |[14] |SPIMCKEN |SPIM Controller Clock Enable Bit + * | | |0 = SPIM controller clock Disabled. + * | | |1 = SPIM controller clock Enabled. + * |[15] |FMCIDLE |Flash Memory Controller Clock Enable Bit in IDLE Mode + * | | |0 = FMC clock Disabled when chip is under IDLE mode. + * | | |1 = FMC clock Enabled when chip is under IDLE mode. + * |[16] |USBHCKEN |USB HOST Controller Clock Enable Bit + * | | |0 = USB HOST peripheral clock Disabled. + * | | |1 = USB HOST peripheral clock Enabled. + * |[17] |SDH1CKEN |SD1 Controller Clock Enable Bit + * | | |0 = SD1 engine clock Disabled. + * | | |1 = SD1 engine clock Enabled. + * @var CLK_T::APBCLK0 + * Offset: 0x08 APB Devices Clock Enable Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WDTCKEN |Watchdog Timer Clock Enable Bit (Write Protect) + * | | |0 = Watchdog timer clock Disabled. + * | | |1 = Watchdog timer clock Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[1] |RTCCKEN |Real-time-clock APB Interface Clock Enable Bit + * | | |This bit is used to control the RTC APB clock only + * | | |The RTC peripheral clock source is selected from RTCSEL(CLK_CLKSEL3[8]) + * | | |It can be selected to 32.768 kHz external low speed crystal or 10 kHz internal low speed RC oscillator (LIRC). + * | | |0 = RTC clock Disabled. + * | | |1 = RTC clock Enabled. + * |[2] |TMR0CKEN |Timer0 Clock Enable Bit + * | | |0 = Timer0 clock Disabled. + * | | |1 = Timer0 clock Enabled. + * |[3] |TMR1CKEN |Timer1 Clock Enable Bit + * | | |0 = Timer1 clock Disabled. + * | | |1 = Timer1 clock Enabled. + * |[4] |TMR2CKEN |Timer2 Clock Enable Bit + * | | |0 = Timer2 clock Disabled. + * | | |1 = Timer2 clock Enabled. + * |[5] |TMR3CKEN |Timer3 Clock Enable Bit + * | | |0 = Timer3 clock Disabled. + * | | |1 = Timer3 clock Enabled. + * |[6] |CLKOCKEN |CLKO Clock Enable Bit + * | | |0 = CLKO clock Disabled. + * | | |1 = CLKO clock Enabled. + * |[7] |ACMP01CKEN|Analog Comparator 0/1 Clock Enable Bit + * | | |0 = Analog comparator 0/1 clock Disabled. + * | | |1 = Analog comparator 0/1 clock Enabled. + * |[8] |I2C0CKEN |I2C0 Clock Enable Bit + * | | |0 = I2C0 clock Disabled. + * | | |1 = I2C0 clock Enabled. + * |[9] |I2C1CKEN |I2C1 Clock Enable Bit + * | | |0 = I2C1 clock Disabled. + * | | |1 = I2C1 clock Enabled. + * |[10] |I2C2CKEN |I2C2 Clock Enable Bit + * | | |0 = I2C2 clock Disabled. + * | | |1 = I2C2 clock Enabled. + * |[12] |QSPI0CKEN |QSPI0 Clock Enable Bit + * | | |0 = QSPI0 clock Disabled. + * | | |1 = QSPI0 clock Enabled. + * |[13] |SPI0CKEN |SPI0 Clock Enable Bit + * | | |0 = SPI0 clock Disabled. + * | | |1 = SPI0 clock Enabled. + * |[14] |SPI1CKEN |SPI1 Clock Enable Bit + * | | |0 = SPI1 clock Disabled. + * | | |1 = SPI1 clock Enabled. + * |[15] |SPI2CKEN |SPI2 Clock Enable Bit + * | | |0 = SPI2 clock Disabled. + * | | |1 = SPI2 clock Enabled. + * |[16] |UART0CKEN |UART0 Clock Enable Bit + * | | |0 = UART0 clock Disabled. + * | | |1 = UART0 clock Enabled. + * |[17] |UART1CKEN |UART1 Clock Enable Bit + * | | |0 = UART1 clock Disabled. + * | | |1 = UART1 clock Enabled. + * |[18] |UART2CKEN |UART2 Clock Enable Bit + * | | |0 = UART2 clock Disabled. + * | | |1 = UART2 clock Enabled. + * |[19] |UART3CKEN |UART3 Clock Enable Bit + * | | |0 = UART3 clock Disabled. + * | | |1 = UART3 clock Enabled. + * |[20] |UART4CKEN |UART4 Clock Enable Bit + * | | |0 = UART4 clock Disabled. + * | | |1 = UART4 clock Enabled. + * |[21] |UART5CKEN |UART5 Clock Enable Bit + * | | |0 = UART5 clock Disabled. + * | | |1 = UART5 clock Enabled. + * |[24] |CAN0CKEN |CAN0 Clock Enable Bit + * | | |0 = CAN0 clock Disabled. + * | | |1 = CAN0 clock Enabled. + * |[25] |CAN1CKEN |CAN1 Clock Enable Bit + * | | |0 = CAN1 clock Disabled. + * | | |1 = CAN1 clock Enabled. + * |[26] |OTGCKEN |USB OTG Clock Enable Bit + * | | |0 = USB OTG clock Disabled. + * | | |1 = USB OTG clock Enabled. + * |[27] |USBDCKEN |USB Device Clock Enable Bit + * | | |0 = USB Device clock Disabled. + * | | |1 = USB Device clock Enabled. + * |[28] |EADCCKEN |Enhanced Analog-digital-converter (EADC) Clock Enable Bit + * | | |0 = EADC clock Disabled. + * | | |1 = EADC clock Enabled. + * |[29] |I2S0CKEN |I2S0 Clock Enable Bit + * | | |0 = I2S0 Clock Disabled. + * | | |1 = I2S0 Clock Enabled. + * |[30] |HSOTGCKEN |HSUSB OTG Clock Enable Bit + * | | |0 = HSUSB OTG clock Disabled. + * | | |1 = HSUSB OTG clock Enabled. + * @var CLK_T::APBCLK1 + * Offset: 0x0C APB Devices Clock Enable Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SC0CKEN |SC0 Clock Enable Bit + * | | |0 = SC0 clock Disabled. + * | | |1 = SC0 clock Enabled. + * |[1] |SC1CKEN |SC1 Clock Enable Bit + * | | |0 = SC1 clock Disabled. + * | | |1 = SC1 clock Enabled. + * |[2] |SC2CKEN |SC2 Clock Enable Bit + * | | |0 = SC2 clock Disabled. + * | | |1 = SC2 clock Enabled. + * |[6] |SPI3CKEN |SPI3 Clock Enable Bit + * | | |0 = SPI3 clock Disabled. + * | | |1 = SPI3 clock Enabled. + * |[8] |USCI0CKEN |USCI0 Clock Enable Bit + * | | |0 = USCI0 clock Disabled. + * | | |1 = USCI0 clock Enabled. + * |[9] |USCI1CKEN |USCI1 Clock Enable Bit + * | | |0 = USCI1 clock Disabled. + * | | |1 = USCI1 clock Enabled. + * |[12] |DACCKEN |DAC Clock Enable Bit + * | | |0 = DAC clock Disabled. + * | | |1 = DAC clock Enabled. + * |[16] |EPWM0CKEN |EPWM0 Clock Enable Bit + * | | |0 = EPWM0 clock Disabled. + * | | |1 = EPWM0 clock Enabled. + * |[17] |EPWM1CKEN |EPWM1 Clock Enable Bit + * | | |0 = EPWM1 clock Disabled. + * | | |1 = EPWM1 clock Enabled. + * |[18] |BPWM0CKEN |BPWM0 Clock Enable Bit + * | | |0 = BPWM0 clock Disabled. + * | | |1 = BPWM0 clock Enabled. + * |[19] |BPWM1CKEN |BPWM1 Clock Enable Bit + * | | |0 = BPWM1 clock Disabled. + * | | |1 = BPWM1 clock Enabled. + * |[22] |QEI0CKEN |QEI0 Clock Enable Bit + * | | |0 = QEI0 clock Disabled. + * | | |1 = QEI0 clock Enabled. + * |[23] |QEI1CKEN |QEI1 Clock Enable Bit + * | | |0 = QEI1 clock Disabled. + * | | |1 = QEI1 clock Enabled. + * |[26] |ECAP0CKEN |ECAP0 Clock Enable Bit + * | | |0 = ECAP0 clock Disabled. + * | | |1 = ECAP0 clock Enabled. + * |[27] |ECAP1CKEN |ECAP1 Clock Enable Bit + * | | |0 = ECAP1 clock Disabled. + * | | |1 = ECAP1 clock Enabled. + * |[30] |OPACKEN |OP Amplifier (OPA) Clock Enable Bit + * | | |0 = OPA clock Disabled. + * | | |1 = OPA clock Enabled. + * @var CLK_T::CLKSEL0 + * Offset: 0x10 Clock Source Select Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |HCLKSEL |HCLK Clock Source Selection (Write Protect) + * | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on. + * | | |The default value is reloaded from the value of CFOSC (CONFIG0[26]) in user configuration register of Flash controller by any reset + * | | |Therefore the default value is either 000b or 111b. + * | | |000 = Clock source from HXT. + * | | |001 = Clock source from LXT. + * | | |010 = Clock source from PLL. + * | | |011 = Clock source from LIRC. + * | | |111 = Clock source from HIRC. + * | | |Other = Reserved. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[5:3] |STCLKSEL |Cortex-M4 SysTick Clock Source Selection (Write Protect) + * | | |If SYST_CTRL[2]=0, SysTick uses listed clock source below. + * | | |000 = Clock source from HXT. + * | | |001 = Clock source from LXT. + * | | |010 = Clock source from HXT/2. + * | | |011 = Clock source from HCLK/2. + * | | |111 = Clock source from HIRC/2. + * | | |Note: if SysTick clock source is not from HCLK (i.e + * | | |SYST_CTRL[2] = 0), SysTick clock source must less than or equal to HCLK/2. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[8] |USBSEL |USB Clock Source Selection (Write Protect) + * | | |0 = Clock source from RC48M. + * | | |1 = Clock source from PLL. + * |[21:20] |SDH0SEL |SD0 Engine Clock Source Selection (Write Protect) + * | | |00 = Clock source from HXT clock. + * | | |01 = Clock source from PLL clock. + * | | |10 = Clock source from HCLK. + * | | |11 = Clock source from HIRC clock. + * |[23:22] |SDH1SEL |SD1 Engine Clock Source Selection (Write Protect) + * | | |00 = Clock source from HXT clock. + * | | |01 = Clock source from PLL clock. + * | | |10 = Clock source from HCLK. + * | | |11 = Clock source from HIRC clock. + * @var CLK_T::CLKSEL1 + * Offset: 0x14 Clock Source Select Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |WDTSEL |Watchdog Timer Clock Source Selection (Write Protect) + * | | |00 = Reserved. + * | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |10 = Clock source from HCLK/2048. + * | | |11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[10:8] |TMR0SEL |TIMER0 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK0. + * | | |011 = Clock source from external clock TM0 pin. + * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[14:12] |TMR1SEL |TIMER1 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK0. + * | | |011 = Clock source from external clock TM1 pin. + * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[18:16] |TMR2SEL |TIMER2 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK1. + * | | |011 = Clock source from external clock TM2 pin. + * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[22:20] |TMR3SEL |TIMER3 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK1. + * | | |011 = Clock source from external clock TM3 pin. + * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[25:24] |UART0SEL |UART0 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[27:26] |UART1SEL |UART1 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[29:28] |CLKOSEL |Clock Divider Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |10 = Clock source from HCLK. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[31:30] |WWDTSEL |Window Watchdog Timer Clock Source Selection + * | | |10 = Clock source from HCLK/2048. + * | | |11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). + * | | |Others = Reserved. + * @var CLK_T::CLKSEL2 + * Offset: 0x18 Clock Source Select Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |EPWM0SEL |EPWM0 Clock Source Selection + * | | |The peripheral clock source of EPWM0 is defined by EPWM0SEL. + * | | |0 = Clock source from PLL. + * | | |1 = Clock source from PCLK0. + * |[1] |EPWM1SEL |EPWM1 Clock Source Selection + * | | |The peripheral clock source of EPWM1 is defined by EPWM1SEL. + * | | |0 = Clock source from PLL. + * | | |1 = Clock source from PCLK1. + * |[3:2] |QSPI0SEL |QSPI0 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK0. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[5:4] |SPI0SEL |SPI0 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK1. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[7:6] |SPI1SEL |SPI1 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK0. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[8] |BPWM0SEL |BPWM0 Clock Source Selection + * | | |The peripheral clock source of BPWM0 is defined by BPWM0SEL. + * | | |0 = Clock source from PLL. + * | | |1 = Clock source from PCLK0. + * |[9] |BPWM1SEL |BPWM1 Clock Source Selection + * | | |The peripheral clock source of BPWM1 is defined by BPWM1SEL. + * | | |0 = Clock source from PLL. + * | | |1 = Clock source from PCLK1. + * |[11:10] |SPI2SEL |SPI2 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK1. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[13:12] |SPI3SEL |SPI3 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK0. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * @var CLK_T::CLKSEL3 + * Offset: 0x1C Clock Source Select Control Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |SC0SEL |SC0 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK0. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[3:2] |SC1SEL |SC0 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK1. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[5:4] |SC2SEL |SC2 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK0. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[8] |RTCSEL |RTC Clock Source Selection + * | | |0 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |1 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). + * |[17:16] |I2S0SEL |I2S0 Clock Source Selection + * | | |00 = Clock source from HXT clock. + * | | |01 = Clock source from PLL clock. + * | | |10 = Clock source from PCLK. + * | | |11 = Clock source from HIRC clock. + * |[25:24] |UART2SEL |UART2 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[27:26] |UART3SEL |UART3 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[29:28] |UART4SEL |UART4 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[31:30] |UART5SEL |UART5 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * @var CLK_T::CLKDIV0 + * Offset: 0x20 Clock Divider Number Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |HCLKDIV |HCLK Clock Divide Number From HCLK Clock Source + * | | |HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1). + * |[7:4] |USBDIV |USB Clock Divide Number From PLL Clock + * | | |USB clock frequency = (PLL frequency) / (USBDIV + 1). + * |[11:8] |UART0DIV |UART0 Clock Divide Number From UART0 Clock Source + * | | |UART0 clock frequency = (UART0 clock source frequency) / (UART0DIV + 1). + * |[15:12] |UART1DIV |UART1 Clock Divide Number From UART1 Clock Source + * | | |UART1 clock frequency = (UART1 clock source frequency) / (UART1DIV + 1). + * |[23:16] |EADCDIV |EADC Clock Divide Number From EADC Clock Source + * | | |EADC clock frequency = (EADC clock source frequency) / (EADCDIV + 1). + * |[31:24] |SDH0DIV |SD0 Clock Divide Number From SD0 Clock Source + * | | |SD0 clock frequency = (SD0 clock source frequency) / (SDH0DIV + 1). + * @var CLK_T::CLKDIV1 + * Offset: 0x24 Clock Divider Number Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SC0DIV |SC0 Clock Divide Number From SC0 Clock Source + * | | |SC0 clock frequency = (SC0 clock source frequency ) / (SC0DIV + 1). + * |[15:8] |SC1DIV |SC1 Clock Divide Number From SC1 Clock Source + * | | |SC1 clock frequency = (SC1 clock source frequency ) / (SC1DIV + 1). + * |[23:16] |SC2DIV |SC2 Clock Divide Number From SC2 Clock Source + * | | |SC2 clock frequency = (SC2 clock source frequency ) / (SC2DIV + 1). + * @var CLK_T::CLKDIV3 + * Offset: 0x2C Clock Divider Number Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |EMACDIV |Ethernet Clock Divide Number Form HCLK + * | | |EMAC MDCLK clock frequency = (HCLK) / (EMACDIV + 1). + * |[31:24] |SDH1DIV |SD1 Clock Divide Number From SD1 Clock Source + * | | |SD1 clock frequency = (SD1 clock source frequency) / (SDH1DIV + 1). + * @var CLK_T::CLKDIV4 + * Offset: 0x30 Clock Divider Number Register 4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |UART2DIV |UART2 Clock Divide Number From UART2 Clock Source + * | | |UART2 clock frequency = (UART2 clock source frequency) / (UART2DIV + 1). + * |[7:4] |UART3DIV |UART3 Clock Divide Number From UART3 Clock Source + * | | |UART3 clock frequency = (UART3 clock source frequency) / (UART3DIV + 1). + * |[11:8] |UART4DIV |UART4 Clock Divide Number From UART4 Clock Source + * | | |UART4 clock frequency = (UART4 clock source frequency) / (UART4DIV + 1). + * |[15:12] |UART5DIV |UART5 Clock Divide Number From UART5 Clock Source + * | | |UART5 clock frequency = (UART5 clock source frequency) / (UART5DIV + 1). + * @var CLK_T::PCLKDIV + * Offset: 0x34 APB Clock Divider Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |APB0DIV |APB0 Clock Divider + * | | |APB0 clock can be divided from HCLK + * | | |000: PCLK0 = HCLK. + * | | |001: PCLK0 = 1/2 HCLK. + * | | |010: PCLK0 = 1/4 HCLK. + * | | |011: PCLK0 = 1/8 HCLK. + * | | |100: PCLK0 = 1/16 HCLK. + * | | |Others: Reserved. + * |[6:4] |APB1DIV |APB1 Clock Divider + * | | |APB1 clock can be divided from HCLK + * | | |000: PCLK1 = HCLK. + * | | |001: PCLK1 = 1/2 HCLK. + * | | |010: PCLK1 = 1/4 HCLK. + * | | |011: PCLK1 = 1/8 HCLK. + * | | |100: PCLK1 = 1/16 HCLK. + * | | |Others: Reserved. + * @var CLK_T::PLLCTL + * Offset: 0x40 PLL Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |FBDIV |PLL Feedback Divider Control (Write Protect) + * | | |Refer to the formulas below the table. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[13:9] |INDIV |PLL Input Divider Control (Write Protect) + * | | |Refer to the formulas below the table. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[15:14] |OUTDIV |PLL Output Divider Control (Write Protect) + * | | |Refer to the formulas below the table. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[16] |PD |Power-down Mode (Write Protect) + * | | |If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too. + * | | |0 = PLL is in normal mode. + * | | |1 = PLL is in Power-down mode (default). + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[17] |BP |PLL Bypass Control (Write Protect) + * | | |0 = PLL is in normal mode (default). + * | | |1 = PLL clock output is same as PLL input clock FIN. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[18] |OE |PLL OE (FOUT Enable) Pin Control (Write Protect) + * | | |0 = PLL FOUT Enabled. + * | | |1 = PLL FOUT is fixed low. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[19] |PLLSRC |PLL Source Clock Selection (Write Protect) + * | | |0 = PLL source clock from 4~24 MHz external high-speed crystal oscillator (HXT). + * | | |1 = PLL source clock from 12 MHz internal high-speed oscillator (HIRC). + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[23] |STBSEL |PLL Stable Counter Selection (Write Protect) + * | | |0 = PLL stable time is 6144 PLL source clock (suitable for source clock is equal to or less than 12 MHz). + * | | |1 = PLL stable time is 12288 PLL source clock (suitable for source clock is larger than 12 MHz). + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var CLK_T::STATUS + * Offset: 0x50 Clock Status Monitor Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |HXTSTB |HXT Clock Source Stable Flag (Read Only) + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock is stable and enabled. + * |[1] |LXTSTB |LXT Clock Source Stable Flag (Read Only) + * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled. + * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled. + * |[2] |PLLSTB |Internal PLL Clock Source Stable Flag (Read Only) + * | | |0 = Internal PLL clock is not stable or disabled. + * | | |1 = Internal PLL clock is stable and enabled. + * |[3] |LIRCSTB |LIRC Clock Source Stable Flag (Read Only) + * | | |0 = 10 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled. + * | | |1 = 10 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled. + * |[4] |HIRCSTB |HIRC Clock Source Stable Flag (Read Only) + * | | |0 = 12 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled. + * | | |1 = 12 MHz internal high speed RC oscillator (HIRC) clock is stable and enabled. + * | | |Note: This bit is read only. + * |[6] |HIRC48MSTB|HIRC 48MHz Clock Source Stable Flag (Read Only) + * | | |0 = 48 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled. + * | | |1 = 48 MHz internal high speed RC oscillator (HIRC) clock is stable and enabled. + * | | |Note: This bit is read only. + * |[7] |CLKSFAIL |Clock Switching Fail Flag (Read Only) + * | | |This bit is updated when software switches system clock source + * | | |If switch target clock is stable, this bit will be set to 0 + * | | |If switch target clock is not stable, this bit will be set to 1. + * | | |0 = Clock switching success. + * | | |1 = Clock switching failure. + * | | |Note: Write 1 to clear the bit to 0. + * @var CLK_T::CLKOCTL + * Offset: 0x60 Clock Output Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |FREQSEL |Clock Output Frequency Selection + * | | |The formula of output frequency is + * | | |Fout = Fin/2(N+1). + * | | |Fin is the input clock frequency. + * | | |Fout is the frequency of divider output clock. + * | | |N is the 4-bit value of FREQSEL[3:0]. + * |[4] |CLKOEN |Clock Output Enable Bit + * | | |0 = Clock Output function Disabled. + * | | |1 = Clock Output function Enabled. + * |[5] |DIV1EN |Clock Output Divide One Enable Bit + * | | |0 = Clock Output will output clock with source frequency divided by FREQSEL. + * | | |1 = Clock Output will output clock with source frequency. + * |[6] |CLK1HZEN |Clock Output 1Hz Enable Bit + * | | |0 = 1 Hz clock output for 32.768 kHz frequency compensation Disabled. + * | | |1 = 1 Hz clock output for 32.768 kHz frequency compensation Enabled. + * @var CLK_T::CLKDCTL + * Offset: 0x70 Clock Fail Detector Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4] |HXTFDEN |HXT Clock Fail Detector Enable Bit + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Disabled. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Enabled. + * |[5] |HXTFIEN |HXT Clock Fail Interrupt Enable Bit + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Disabled. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Enabled. + * |[12] |LXTFDEN |LXT Clock Fail Detector Enable Bit + * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Disabled. + * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Enabled. + * |[13] |LXTFIEN |LXT Clock Fail Interrupt Enable Bit + * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Disabled. + * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Enabled. + * |[16] |HXTFQDEN |HXT Clock Frequency Range Detector Enable Bit + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector Disabled. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector Enabled. + * |[17] |HXTFQIEN |HXT Clock Frequency Range Detector Interrupt Enable Bit + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Disabled. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Enabled. + * @var CLK_T::CLKDSTS + * Offset: 0x74 Clock Fail Detector Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |HXTFIF |HXT Clock Fail Interrupt Flag + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is normal. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock stops. + * | | |Note: Write 1 to clear the bit to 0. + * |[1] |LXTFIF |LXT Clock Fail Interrupt Flag + * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is normal. + * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) stops. + * | | |Note: Write 1 to clear the bit to 0. + * |[8] |HXTFQIF |HXT Clock Frequency Range Detector Interrupt Flag + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency is normal. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency is abnormal. + * | | |Note: Write 1 to clear the bit to 0. + * @var CLK_T::CDUPB + * Offset: 0x78 Clock Frequency Range Detector Upper Boundary Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |UPERBD |HXT Clock Frequency Range Detector Upper Boundary Value + * | | |The bits define the maximum value of frequency range detector window. + * | | |When HXT frequency higher than this maximum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1. + * @var CLK_T::CDLOWB + * Offset: 0x7C Clock Frequency Range Detector Lower Boundary Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |LOWERBD |HXT Clock Frequency Range Detector Lower Boundary Value + * | | |The bits define the minimum value of frequency range detector window. + * | | |When HXT frequency lower than this minimum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1. + * @var CLK_T::PMUCTL + * Offset: 0x90 Power Manager Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |PDMSEL |Power-down Mode Selection (Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |These bits control chip power-down mode grade selection when CPU execute WFI/WFE instruction. + * | | |000 = Power-down mode is selected. (PD) + * | | |001 = Low leakage Power-down mode is selected (LLPD). + * | | |010 =Fast wake-up Power-down mode is selected (FWPD). + * | | |011 = Reserved. + * | | |100 = Standby Power-down mode 0 is selected (SPD0) (SRAM retention). + * | | |101 = Standby Power-down mode 1 is selected (SPD1). + * | | |110 = Deep Power-down mode is selected (DPD). + * | | |111 = Reserved. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |DPDHOLDEN |Deep-Power-Down Mode GPIO Hold Enable + * | | |0 = When GPIO enters deep power-down mode, all I/O status are tri-state. + * | | |1 = When GPIO enters deep power-down mode, all I/O status are hold to keep normal operating status. + * | | | After chip was waked up from deep power-down mode, the I/O are still keep hold status until user set CLK_IOPDCTL[0] + * | | | to release I/O hold status. + * |[8] |WKTMREN |Wake-up Timer Enable (Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |0 = Wake-up timer disable at DPD/SPD mode. + * | | |1 = Wake-up timer enabled at DPD/SPD mode. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[11:9] |WKTMRIS |Wake-up Timer Time-out Interval Select (Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |These bits control wake-up timer time-out interval when chip at DPD/SPD mode. + * | | |000 = Time-out interval is 128 OSC10K clocks (12.8 ms). + * | | |001 = Time-out interval is 256 OSC10K clocks (25.6 ms). + * | | |010 = Time-out interval is 512 OSC10K clocks (51.2 ms). + * | | |011 = Time-out interval is 1024 OSC10K clocks (102.4ms). + * | | |100 = Time-out interval is 4096 OSC10K clocks (409.6ms). + * | | |101 = Time-out interval is 8192 OSC10K clocks (819.2ms). + * | | |110 = Time-out interval is 16384 OSC10K clocks (1638.4ms). + * | | |111 = Time-out interval is 65536 OSC10K clocks (6553.6ms). + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[17:16] |WKPINEN |Wake-up Pin Enable (Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |00 = Wake-up pin disable at Deep Power-down mode. + * | | |01 = Wake-up pin rising edge enabled at Deep Power-down mode. + * | | |10 = Wake-up pin falling edge enabled at Deep Power-down mode. + * | | |11 = Wake-up pin both edge enabled at Deep Power-down mode. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[18] |ACMPSPWK |ACMP Standby Power-down Mode Wake-up Enable (Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |0 = ACMP wake-up disable at Standby Power-down mode. + * | | |1 = ACMP wake-up enabled at Standby Power-down mode. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[23] |RTCWKEN |RTC Wake-up Enable (Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |0 = RTC wake-up disable at Deep Power-down mode or Standby Power-down mode. + * | | |1 = RTC wake-up enabled at Deep Power-down mode or Standby Power-down mode. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var CLK_T::PMUSTS + * Offset: 0x94 Power Manager Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PINWK |Pin Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (GPC.0) + * | | |This flag is cleared when DPD mode is entered. + * |[1] |TMRWK |Timer Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested by wakeup timer time-out + * | | |This flag is cleared when DPD or SPD mode is entered. + * |[2] |RTCWK |RTC Wake-up Flag (Read Only) + * | | |This flag indicates that wakeup of device from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested with a RTC alarm, tick time or tamper happened + * | | |This flag is cleared when DPD or SPD mode is entered. + * |[8] |GPAWK |GPA Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPA group pins + * | | |This flag is cleared when SPD mode is entered. + * |[9] |GPBWK |GPB Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPB group pins + * | | |This flag is cleared when SPD mode is entered. + * |[10] |GPCWK |GPC Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPC group pins + * | | |This flag is cleared when SPD mode is entered. + * |[11] |GPDWK |GPD Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPD group pins + * | | |This flag is cleared when SPD mode is entered. + * |[12] |LVRWK |LVR Wake-up Flag (Read Only) + * | | |This flag indicates that wakeup of device from Standby Power-down mode was requested with a LVR happened + * | | |This flag is cleared when SPD mode is entered. + * |[13] |BODWK |BOD Wake-up Flag (Read Only) + * | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a BOD happened + * | | |This flag is cleared when SPD mode is entered. + * |[14] |ACMPWK |ACMP Wake-up Flag (Read Only) + * | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a ACMP transition + * | | |This flag is cleared when SPD mode is entered. + * |[31] |CLRWK |Clear Wake-up Flag + * | | |0 = No clear. + * | | |1 = Clear all wake-up flag. + * @var CLK_T::LDOCTL + * Offset: 0x98 LDO Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[18] |PDBIASEN |Power-down Bias Enable Bit + * | | |0 = Reserved. + * | | |1 = Power-down bias enabled. + * | | |Note: This bit should set to 1 before chip enter power-down mode. + * @var CLK_T::SWKDBCTL + * Offset: 0x9C Standby Power-down Wake-up De-bounce Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |SWKDBCLKSEL|Standby Power-down Wake-up De-bounce Sampling Cycle Selection + * | | |0000 = Sample wake-up input once per 1 clocks. + * | | |0001 = Sample wake-up input once per 2 clocks. + * | | |0010 = Sample wake-up input once per 4 clocks. + * | | |0011 = Sample wake-up input once per 8 clocks. + * | | |0100 = Sample wake-up input once per 16 clocks. + * | | |0101 = Sample wake-up input once per 32 clocks. + * | | |0110 = Sample wake-up input once per 64 clocks. + * | | |0111 = Sample wake-up input once per 128 clocks. + * | | |1000 = Sample wake-up input once per 256 clocks. + * | | |1001 = Sample wake-up input once per 2*256 clocks. + * | | |1010 = Sample wake-up input once per 4*256 clocks. + * | | |1011 = Sample wake-up input once per 8*256 clocks. + * | | |1100 = Sample wake-up input once per 16*256 clocks. + * | | |1101 = Sample wake-up input once per 32*256 clocks. + * | | |1110 = Sample wake-up input once per 64*256 clocks. + * | | |1111 = Sample wake-up input once per 128*256 clocks. + * | | |Note: De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC). + * @var CLK_T::PASWKCTL + * Offset: 0xA0 GPA Standby Power-down Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit + * | | |0 = GPA group pin wake-up function disabled. + * | | |1 = GPA group pin wake-up function enabled. + * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit + * | | |0 = GPA group pin rising edge wake-up function disabled. + * | | |1 = GPA group pin rising edge wake-up function enabled. + * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit + * | | |0 = GPA group pin falling edge wake-up function disabled. + * | | |1 = GPA group pin falling edge wake-up function enabled. + * |[7:4] |WKPSEL |GPA Standby Power-down Wake-up Pin Select + * | | |0000 = GPA.0 wake-up function enabled. + * | | |0001 = GPA.1 wake-up function enabled. + * | | |0010 = GPA.2 wake-up function enabled. + * | | |0011 = GPA.3 wake-up function enabled. + * | | |0100 = GPA.4 wake-up function enabled. + * | | |0101 = GPA.5 wake-up function enabled. + * | | |0110 = GPA.6 wake-up function enabled. + * | | |0111 = GPA.7 wake-up function enabled. + * | | |1000 = GPA.8 wake-up function enabled. + * | | |1001 = GPA.9 wake-up function enabled. + * | | |1010 = GPA.10 wake-up function enabled. + * | | |1011 = GPA.11 wake-up function enabled. + * | | |1100 = GPA.12 wake-up function enabled. + * | | |1101 = GPA.13 wake-up function enabled. + * | | |1110 = GPA.14 wake-up function enabled. + * | | |1111 = GPA.15 wake-up function enabled. + * |[8] |DBEN |GPA Input Signal De-bounce Enable Bit + * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO + * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up + * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator. + * | | |0 = Standby power-down wake-up pin De-bounce function disable. + * | | |1 = Standby power-down wake-up pin De-bounce function enable. + * | | |The de-bounce function is valid only for edge triggered. + * @var CLK_T::PBSWKCTL + * Offset: 0xA4 GPB Standby Power-down Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit + * | | |0 = GPB group pin wake-up function disabled. + * | | |1 = GPB group pin wake-up function enabled. + * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit + * | | |0 = GPB group pin rising edge wake-up function disabled. + * | | |1 = GPB group pin rising edge wake-up function enabled. + * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit + * | | |0 = GPB group pin falling edge wake-up function disabled. + * | | |1 = GPB group pin falling edge wake-up function enabled. + * |[7:4] |WKPSEL |GPB Standby Power-down Wake-up Pin Select + * | | |0000 = GPB.0 wake-up function enabled. + * | | |0001 = GPB.1 wake-up function enabled. + * | | |0010 = GPB.2 wake-up function enabled. + * | | |0011 = GPB.3 wake-up function enabled. + * | | |0100 = GPB.4 wake-up function enabled. + * | | |0101 = GPB.5 wake-up function enabled. + * | | |0110 = GPB.6 wake-up function enabled. + * | | |0111 = GPB.7 wake-up function enabled. + * | | |1000 = GPB.8 wake-up function enabled. + * | | |1001 = GPB.9 wake-up function enabled. + * | | |1010 = GPB.10 wake-up function enabled. + * | | |1011 = GPB.11 wake-up function enabled. + * | | |1100 = GPB.12 wake-up function enabled. + * | | |1101 = GPB.13 wake-up function enabled. + * | | |1110 = GPB.14 wake-up function enabled. + * | | |1111 = GPB.15 wake-up function enabled. + * |[8] |DBEN |GPB Input Signal De-bounce Enable Bit + * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO + * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up + * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator. + * | | |0 = Standby power-down wake-up pin De-bounce function disable. + * | | |1 = Standby power-down wake-up pin De-bounce function enable. + * | | |The de-bounce function is valid only for edge triggered. + * @var CLK_T::PCSWKCTL + * Offset: 0xA8 GPC Standby Power-down Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit + * | | |0 = GPC group pin wake-up function disabled. + * | | |1 = GPC group pin wake-up function enabled. + * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit + * | | |0 = GPC group pin rising edge wake-up function disabled. + * | | |1 = GPC group pin rising edge wake-up function enabled. + * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit + * | | |0 = GPC group pin falling edge wake-up function disabled. + * | | |1 = GPC group pin falling edge wake-up function enabled. + * |[7:4] |WKPSEL |GPC Standby Power-down Wake-up Pin Select + * | | |0000 = GPC.0 wake-up function enabled. + * | | |0001 = GPC.1 wake-up function enabled. + * | | |0010 = GPC.2 wake-up function enabled. + * | | |0011 = GPC.3 wake-up function enabled. + * | | |0100 = GPC.4 wake-up function enabled. + * | | |0101 = GPC.5 wake-up function enabled. + * | | |0110 = GPC.6 wake-up function enabled. + * | | |0111 = GPC.7 wake-up function enabled. + * | | |1000 = GPC.8 wake-up function enabled. + * | | |1001 = GPC.9 wake-up function enabled. + * | | |1010 = GPC.10 wake-up function enabled. + * | | |1011 = GPC.11 wake-up function enabled. + * | | |1100 = GPC.12 wake-up function enabled. + * | | |1101 = GPC.13 wake-up function enabled. + * | | |1110 = GPC.14 wake-up function enabled. + * | | |1111 = GPC.15 wake-up function enabled. + * |[8] |DBEN |GPC Input Signal De-bounce Enable Bit + * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO + * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up + * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator. + * | | |0 = Standby power-down wake-up pin De-bounce function disable. + * | | |1 = Standby power-down wake-up pin De-bounce function enable. + * | | |The de-bounce function is valid only for edge triggered. + * @var CLK_T::PDSWKCTL + * Offset: 0xAC GPD Standby Power-down Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit + * | | |0 = GPD group pin wake-up function disabled. + * | | |1 = GPD group pin wake-up function enabled. + * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit + * | | |0 = GPD group pin rising edge wake-up function disabled. + * | | |1 = GPD group pin rising edge wake-up function enabled. + * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit + * | | |0 = GPD group pin falling edge wake-up function disabled. + * | | |1 = GPD group pin falling edge wake-up function enabled. + * |[7:4] |WKPSEL |GPD Standby Power-down Wake-up Pin Select + * | | |0000 = GPD.0 wake-up function enabled. + * | | |0001 = GPD.1 wake-up function enabled. + * | | |0010 = GPD.2 wake-up function enabled. + * | | |0011 = GPD.3 wake-up function enabled. + * | | |0100 = GPD.4 wake-up function enabled. + * | | |0101 = GPD.5 wake-up function enabled. + * | | |0110 = GPD.6 wake-up function enabled. + * | | |0111 = GPD.7 wake-up function enabled. + * | | |1000 = GPD.8 wake-up function enabled. + * | | |1001 = GPD.9 wake-up function enabled. + * | | |1010 = GPD.10 wake-up function enabled. + * | | |1011 = GPD.11 wake-up function enabled. + * | | |1100 = GPD.12 wake-up function enabled. + * | | |1101 = GPD.13 wake-up function enabled. + * | | |1110 = GPD.14 wake-up function enabled. + * | | |1111 = GPD.15 wake-up function enabled. + * |[8] |DBEN |GPD Input Signal De-bounce Enable Bit + * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO + * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up + * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator. + * | | |0 = Standby power-down wake-up pin De-bounce function disable. + * | | |1 = Standby power-down wake-up pin De-bounce function enable. + * | | |The de-bounce function is valid only for edge triggered. + * @var CLK_T::IOPDCTL + * Offset: 0xB0 GPIO Standby Power-down Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |IOHR |GPIO Hold Release + * | | |When GPIO enter standby power-down mode, all I/O status are hold to keep normal operating status + * | | |After chip was waked up from standby power-down mode, the I/O are still keep hold status until user set this bit to release I/O hold status. + * | | |This bit is auto cleared by hardware. + */ + __IO uint32_t PWRCTL; /*!< [0x0000] System Power-down Control Register */ + __IO uint32_t AHBCLK; /*!< [0x0004] AHB Devices Clock Enable Control Register */ + __IO uint32_t APBCLK0; /*!< [0x0008] APB Devices Clock Enable Control Register 0 */ + __IO uint32_t APBCLK1; /*!< [0x000c] APB Devices Clock Enable Control Register 1 */ + __IO uint32_t CLKSEL0; /*!< [0x0010] Clock Source Select Control Register 0 */ + __IO uint32_t CLKSEL1; /*!< [0x0014] Clock Source Select Control Register 1 */ + __IO uint32_t CLKSEL2; /*!< [0x0018] Clock Source Select Control Register 2 */ + __IO uint32_t CLKSEL3; /*!< [0x001c] Clock Source Select Control Register 3 */ + __IO uint32_t CLKDIV0; /*!< [0x0020] Clock Divider Number Register 0 */ + __IO uint32_t CLKDIV1; /*!< [0x0024] Clock Divider Number Register 1 */ + __IO uint32_t CLKDIV2; /*!< [0x0028] Clock Divider Number Register 2 */ + __IO uint32_t CLKDIV3; /*!< [0x002c] Clock Divider Number Register 3 */ + __IO uint32_t CLKDIV4; /*!< [0x0030] Clock Divider Number Register 4 */ + __IO uint32_t PCLKDIV; /*!< [0x0034] APB Clock Divider Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE1[2]; + /** @endcond */ + __IO uint32_t PLLCTL; /*!< [0x0040] PLL Control Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE2[3]; + /** @endcond */ + __I uint32_t STATUS; /*!< [0x0050] Clock Status Monitor Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE3[3]; + /** @endcond */ + __IO uint32_t CLKOCTL; /*!< [0x0060] Clock Output Control Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE4[3]; + /** @endcond */ + __IO uint32_t CLKDCTL; /*!< [0x0070] Clock Fail Detector Control Register */ + __IO uint32_t CLKDSTS; /*!< [0x0074] Clock Fail Detector Status Register */ + __IO uint32_t CDUPB; /*!< [0x0078] Clock Frequency Range Detector Upper Boundary Register */ + __IO uint32_t CDLOWB; /*!< [0x007c] Clock Frequency Range Detector Lower Boundary Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE5[4]; + /** @endcond */ + __IO uint32_t PMUCTL; /*!< [0x0090] Power Manager Control Register */ + __IO uint32_t PMUSTS; /*!< [0x0094] Power Manager Status Register */ + __IO uint32_t LDOCTL; /*!< [0x0098] LDO Control Register */ + __IO uint32_t SWKDBCTL; /*!< [0x009c] Standby Power-down Wake-up De-bounce Control Register */ + __IO uint32_t PASWKCTL; /*!< [0x00a0] GPA Standby Power-down Wake-up Control Register */ + __IO uint32_t PBSWKCTL; /*!< [0x00a4] GPB Standby Power-down Wake-up Control Register */ + __IO uint32_t PCSWKCTL; /*!< [0x00a8] GPC Standby Power-down Wake-up Control Register */ + __IO uint32_t PDSWKCTL; /*!< [0x00ac] GPD Standby Power-down Wake-up Control Register */ + __IO uint32_t IOPDCTL; /*!< [0x00b0] GPIO Standby Power-down Control Register */ + +} CLK_T; + +/** + @addtogroup CLK_CONST CLK Bit Field Definition + Constant Definitions for CLK Controller +@{ */ + +#define CLK_PWRCTL_HXTEN_Pos (0) /*!< CLK_T::PWRCTL: HXTEN Position */ +#define CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos) /*!< CLK_T::PWRCTL: HXTEN Mask */ + +#define CLK_PWRCTL_LXTEN_Pos (1) /*!< CLK_T::PWRCTL: LXTEN Position */ +#define CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos) /*!< CLK_T::PWRCTL: LXTEN Mask */ + +#define CLK_PWRCTL_HIRCEN_Pos (2) /*!< CLK_T::PWRCTL: HIRCEN Position */ +#define CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos) /*!< CLK_T::PWRCTL: HIRCEN Mask */ + +#define CLK_PWRCTL_LIRCEN_Pos (3) /*!< CLK_T::PWRCTL: LIRCEN Position */ +#define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos) /*!< CLK_T::PWRCTL: LIRCEN Mask */ + +#define CLK_PWRCTL_PDWKDLY_Pos (4) /*!< CLK_T::PWRCTL: PDWKDLY Position */ +#define CLK_PWRCTL_PDWKDLY_Msk (0x1ul << CLK_PWRCTL_PDWKDLY_Pos) /*!< CLK_T::PWRCTL: PDWKDLY Mask */ + +#define CLK_PWRCTL_PDWKIEN_Pos (5) /*!< CLK_T::PWRCTL: PDWKIEN Position */ +#define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos) /*!< CLK_T::PWRCTL: PDWKIEN Mask */ + +#define CLK_PWRCTL_PDWKIF_Pos (6) /*!< CLK_T::PWRCTL: PDWKIF Position */ +#define CLK_PWRCTL_PDWKIF_Msk (0x1ul << CLK_PWRCTL_PDWKIF_Pos) /*!< CLK_T::PWRCTL: PDWKIF Mask */ + +#define CLK_PWRCTL_PDEN_Pos (7) /*!< CLK_T::PWRCTL: PDEN Position */ +#define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos) /*!< CLK_T::PWRCTL: PDEN Mask */ + +#define CLK_PWRCTL_HXTGAIN_Pos (10) /*!< CLK_T::PWRCTL: HXTGAIN Position */ +#define CLK_PWRCTL_HXTGAIN_Msk (0x3ul << CLK_PWRCTL_HXTGAIN_Pos) /*!< CLK_T::PWRCTL: HXTGAIN Mask */ + +#define CLK_PWRCTL_HXTSELTYP_Pos (12) /*!< CLK_T::PWRCTL: HXTSELTYP Position */ +#define CLK_PWRCTL_HXTSELTYP_Msk (0x1ul << CLK_PWRCTL_HXTSELTYP_Pos) /*!< CLK_T::PWRCTL: HXTSELTYP Mask */ + +#define CLK_PWRCTL_HXTTBEN_Pos (13) /*!< CLK_T::PWRCTL: HXTTBEN Position */ +#define CLK_PWRCTL_HXTTBEN_Msk (0x1ul << CLK_PWRCTL_HXTTBEN_Pos) /*!< CLK_T::PWRCTL: HXTTBEN Mask */ + +#define CLK_PWRCTL_HIRCSTBS_Pos (16) /*!< CLK_T::PWRCTL: HIRCSTBS Position */ +#define CLK_PWRCTL_HIRCSTBS_Msk (0x3ul << CLK_PWRCTL_HIRCSTBS_Pos) /*!< CLK_T::PWRCTL: HIRCSTBS Mask */ + +#define CLK_PWRCTL_HIRC48MEN_Pos (18) /*!< CLK_T::PWRCTL: HIRC48MEN Position */ +#define CLK_PWRCTL_HIRC48MEN_Msk (0x1ul << CLK_PWRCTL_HIRC48MEN_Pos) /*!< CLK_T::PWRCTL: HIRC48MEN Mask */ + +#define CLK_AHBCLK_PDMACKEN_Pos (1) /*!< CLK_T::AHBCLK: PDMACKEN Position */ +#define CLK_AHBCLK_PDMACKEN_Msk (0x1ul << CLK_AHBCLK_PDMACKEN_Pos) /*!< CLK_T::AHBCLK: PDMACKEN Mask */ + +#define CLK_AHBCLK_ISPCKEN_Pos (2) /*!< CLK_T::AHBCLK: ISPCKEN Position */ +#define CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos) /*!< CLK_T::AHBCLK: ISPCKEN Mask */ + +#define CLK_AHBCLK_EBICKEN_Pos (3) /*!< CLK_T::AHBCLK: EBICKEN Position */ +#define CLK_AHBCLK_EBICKEN_Msk (0x1ul << CLK_AHBCLK_EBICKEN_Pos) /*!< CLK_T::AHBCLK: EBICKEN Mask */ + +#define CLK_AHBCLK_EMACCKEN_Pos (5) /*!< CLK_T::AHBCLK: EMACCKEN Position */ +#define CLK_AHBCLK_EMACCKEN_Msk (0x1ul << CLK_AHBCLK_EMACCKEN_Pos) /*!< CLK_T::AHBCLK: EMACCKEN Mask */ + +#define CLK_AHBCLK_SDH0CKEN_Pos (6) /*!< CLK_T::AHBCLK: SDH0CKEN Position */ +#define CLK_AHBCLK_SDH0CKEN_Msk (0x1ul << CLK_AHBCLK_SDH0CKEN_Pos) /*!< CLK_T::AHBCLK: SDH0CKEN Mask */ + +#define CLK_AHBCLK_CRCCKEN_Pos (7) /*!< CLK_T::AHBCLK: CRCCKEN Position */ +#define CLK_AHBCLK_CRCCKEN_Msk (0x1ul << CLK_AHBCLK_CRCCKEN_Pos) /*!< CLK_T::AHBCLK: CRCCKEN Mask */ + +#define CLK_AHBCLK_CCAPCKEN_Pos (8) /*!< CLK_T::AHBCLK: CCAPCKEN Position */ +#define CLK_AHBCLK_CCAPCKEN_Msk (0x1ul << CLK_AHBCLK_CCAPCKEN_Pos) /*!< CLK_T::AHBCLK: CCAPCKEN Mask */ + +#define CLK_AHBCLK_SENCKEN_Pos (9) /*!< CLK_T::AHBCLK: SENCKEN Position */ +#define CLK_AHBCLK_SENCKEN_Msk (0x1ul << CLK_AHBCLK_SENCKEN_Pos) /*!< CLK_T::AHBCLK: SENCKEN Mask */ + +#define CLK_AHBCLK_HSUSBDCKEN_Pos (10) /*!< CLK_T::AHBCLK: HSUSBDCKEN Position */ +#define CLK_AHBCLK_HSUSBDCKEN_Msk (0x1ul << CLK_AHBCLK_HSUSBDCKEN_Pos) /*!< CLK_T::AHBCLK: HSUSBDCKEN Mask */ + +#define CLK_AHBCLK_CRPTCKEN_Pos (12) /*!< CLK_T::AHBCLK: CRPTCKEN Position */ +#define CLK_AHBCLK_CRPTCKEN_Msk (0x1ul << CLK_AHBCLK_CRPTCKEN_Pos) /*!< CLK_T::AHBCLK: CRPTCKEN Mask */ + +#define CLK_AHBCLK_SPIMCKEN_Pos (14) /*!< CLK_T::AHBCLK: SPIMCKEN Position */ +#define CLK_AHBCLK_SPIMCKEN_Msk (0x1ul << CLK_AHBCLK_SPIMCKEN_Pos) /*!< CLK_T::AHBCLK: SPIMCKEN Mask */ + +#define CLK_AHBCLK_FMCIDLE_Pos (15) /*!< CLK_T::AHBCLK: FMCIDLE Position */ +#define CLK_AHBCLK_FMCIDLE_Msk (0x1ul << CLK_AHBCLK_FMCIDLE_Pos) /*!< CLK_T::AHBCLK: FMCIDLE Mask */ + +#define CLK_AHBCLK_USBHCKEN_Pos (16) /*!< CLK_T::AHBCLK: USBHCKEN Position */ +#define CLK_AHBCLK_USBHCKEN_Msk (0x1ul << CLK_AHBCLK_USBHCKEN_Pos) /*!< CLK_T::AHBCLK: USBHCKEN Mask */ + +#define CLK_AHBCLK_SDH1CKEN_Pos (17) /*!< CLK_T::AHBCLK: SDH1CKEN Position */ +#define CLK_AHBCLK_SDH1CKEN_Msk (0x1ul << CLK_AHBCLK_SDH1CKEN_Pos) /*!< CLK_T::AHBCLK: SDH1CKEN Mask */ + +#define CLK_APBCLK0_WDTCKEN_Pos (0) /*!< CLK_T::APBCLK0: WDTCKEN Position */ +#define CLK_APBCLK0_WDTCKEN_Msk (0x1ul << CLK_APBCLK0_WDTCKEN_Pos) /*!< CLK_T::APBCLK0: WDTCKEN Mask */ + +#define CLK_APBCLK0_RTCCKEN_Pos (1) /*!< CLK_T::APBCLK0: RTCCKEN Position */ +#define CLK_APBCLK0_RTCCKEN_Msk (0x1ul << CLK_APBCLK0_RTCCKEN_Pos) /*!< CLK_T::APBCLK0: RTCCKEN Mask */ + +#define CLK_APBCLK0_TMR0CKEN_Pos (2) /*!< CLK_T::APBCLK0: TMR0CKEN Position */ +#define CLK_APBCLK0_TMR0CKEN_Msk (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos) /*!< CLK_T::APBCLK0: TMR0CKEN Mask */ + +#define CLK_APBCLK0_TMR1CKEN_Pos (3) /*!< CLK_T::APBCLK0: TMR1CKEN Position */ +#define CLK_APBCLK0_TMR1CKEN_Msk (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos) /*!< CLK_T::APBCLK0: TMR1CKEN Mask */ + +#define CLK_APBCLK0_TMR2CKEN_Pos (4) /*!< CLK_T::APBCLK0: TMR2CKEN Position */ +#define CLK_APBCLK0_TMR2CKEN_Msk (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos) /*!< CLK_T::APBCLK0: TMR2CKEN Mask */ + +#define CLK_APBCLK0_TMR3CKEN_Pos (5) /*!< CLK_T::APBCLK0: TMR3CKEN Position */ +#define CLK_APBCLK0_TMR3CKEN_Msk (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos) /*!< CLK_T::APBCLK0: TMR3CKEN Mask */ + +#define CLK_APBCLK0_CLKOCKEN_Pos (6) /*!< CLK_T::APBCLK0: CLKOCKEN Position */ +#define CLK_APBCLK0_CLKOCKEN_Msk (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos) /*!< CLK_T::APBCLK0: CLKOCKEN Mask */ + +#define CLK_APBCLK0_ACMP01CKEN_Pos (7) /*!< CLK_T::APBCLK0: ACMP01CKEN Position */ +#define CLK_APBCLK0_ACMP01CKEN_Msk (0x1ul << CLK_APBCLK0_ACMP01CKEN_Pos) /*!< CLK_T::APBCLK0: ACMP01CKEN Mask */ + +#define CLK_APBCLK0_I2C0CKEN_Pos (8) /*!< CLK_T::APBCLK0: I2C0CKEN Position */ +#define CLK_APBCLK0_I2C0CKEN_Msk (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos) /*!< CLK_T::APBCLK0: I2C0CKEN Mask */ + +#define CLK_APBCLK0_I2C1CKEN_Pos (9) /*!< CLK_T::APBCLK0: I2C1CKEN Position */ +#define CLK_APBCLK0_I2C1CKEN_Msk (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos) /*!< CLK_T::APBCLK0: I2C1CKEN Mask */ + +#define CLK_APBCLK0_I2C2CKEN_Pos (10) /*!< CLK_T::APBCLK0: I2C2CKEN Position */ +#define CLK_APBCLK0_I2C2CKEN_Msk (0x1ul << CLK_APBCLK0_I2C2CKEN_Pos) /*!< CLK_T::APBCLK0: I2C2CKEN Mask */ + +#define CLK_APBCLK0_QSPI0CKEN_Pos (12) /*!< CLK_T::APBCLK0: QSPI0CKEN Position */ +#define CLK_APBCLK0_QSPI0CKEN_Msk (0x1ul << CLK_APBCLK0_QSPI0CKEN_Pos) /*!< CLK_T::APBCLK0: QSPI0CKEN Mask */ + +#define CLK_APBCLK0_SPI0CKEN_Pos (13) /*!< CLK_T::APBCLK0: SPI0CKEN Position */ +#define CLK_APBCLK0_SPI0CKEN_Msk (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos) /*!< CLK_T::APBCLK0: SPI0CKEN Mask */ + +#define CLK_APBCLK0_SPI1CKEN_Pos (14) /*!< CLK_T::APBCLK0: SPI1CKEN Position */ +#define CLK_APBCLK0_SPI1CKEN_Msk (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos) /*!< CLK_T::APBCLK0: SPI1CKEN Mask */ + +#define CLK_APBCLK0_SPI2CKEN_Pos (15) /*!< CLK_T::APBCLK0: SPI2CKEN Position */ +#define CLK_APBCLK0_SPI2CKEN_Msk (0x1ul << CLK_APBCLK0_SPI2CKEN_Pos) /*!< CLK_T::APBCLK0: SPI2CKEN Mask */ + +#define CLK_APBCLK0_UART0CKEN_Pos (16) /*!< CLK_T::APBCLK0: UART0CKEN Position */ +#define CLK_APBCLK0_UART0CKEN_Msk (0x1ul << CLK_APBCLK0_UART0CKEN_Pos) /*!< CLK_T::APBCLK0: UART0CKEN Mask */ + +#define CLK_APBCLK0_UART1CKEN_Pos (17) /*!< CLK_T::APBCLK0: UART1CKEN Position */ +#define CLK_APBCLK0_UART1CKEN_Msk (0x1ul << CLK_APBCLK0_UART1CKEN_Pos) /*!< CLK_T::APBCLK0: UART1CKEN Mask */ + +#define CLK_APBCLK0_UART2CKEN_Pos (18) /*!< CLK_T::APBCLK0: UART2CKEN Position */ +#define CLK_APBCLK0_UART2CKEN_Msk (0x1ul << CLK_APBCLK0_UART2CKEN_Pos) /*!< CLK_T::APBCLK0: UART2CKEN Mask */ + +#define CLK_APBCLK0_UART3CKEN_Pos (19) /*!< CLK_T::APBCLK0: UART3CKEN Position */ +#define CLK_APBCLK0_UART3CKEN_Msk (0x1ul << CLK_APBCLK0_UART3CKEN_Pos) /*!< CLK_T::APBCLK0: UART3CKEN Mask */ + +#define CLK_APBCLK0_UART4CKEN_Pos (20) /*!< CLK_T::APBCLK0: UART4CKEN Position */ +#define CLK_APBCLK0_UART4CKEN_Msk (0x1ul << CLK_APBCLK0_UART4CKEN_Pos) /*!< CLK_T::APBCLK0: UART4CKEN Mask */ + +#define CLK_APBCLK0_UART5CKEN_Pos (21) /*!< CLK_T::APBCLK0: UART5CKEN Position */ +#define CLK_APBCLK0_UART5CKEN_Msk (0x1ul << CLK_APBCLK0_UART5CKEN_Pos) /*!< CLK_T::APBCLK0: UART5CKEN Mask */ + +#define CLK_APBCLK0_UART6CKEN_Pos (22) /*!< CLK_T::APBCLK0: UART6CKEN Position */ +#define CLK_APBCLK0_UART6CKEN_Msk (0x1ul << CLK_APBCLK0_UART6CKEN_Pos) /*!< CLK_T::APBCLK0: UART6CKEN Mask */ + +#define CLK_APBCLK0_UART7CKEN_Pos (23) /*!< CLK_T::APBCLK0: UART7CKEN Position */ +#define CLK_APBCLK0_UART7CKEN_Msk (0x1ul << CLK_APBCLK0_UART7CKEN_Pos) /*!< CLK_T::APBCLK0: UART7CKEN Mask */ + +#define CLK_APBCLK0_CAN0CKEN_Pos (24) /*!< CLK_T::APBCLK0: CAN0CKEN Position */ +#define CLK_APBCLK0_CAN0CKEN_Msk (0x1ul << CLK_APBCLK0_CAN0CKEN_Pos) /*!< CLK_T::APBCLK0: CAN0CKEN Mask */ + +#define CLK_APBCLK0_CAN1CKEN_Pos (25) /*!< CLK_T::APBCLK0: CAN1CKEN Position */ +#define CLK_APBCLK0_CAN1CKEN_Msk (0x1ul << CLK_APBCLK0_CAN1CKEN_Pos) /*!< CLK_T::APBCLK0: CAN1CKEN Mask */ + +#define CLK_APBCLK0_OTGCKEN_Pos (26) /*!< CLK_T::APBCLK0: OTGCKEN Position */ +#define CLK_APBCLK0_OTGCKEN_Msk (0x1ul << CLK_APBCLK0_OTGCKEN_Pos) /*!< CLK_T::APBCLK0: OTGCKEN Mask */ + +#define CLK_APBCLK0_USBDCKEN_Pos (27) /*!< CLK_T::APBCLK0: USBDCKEN Position */ +#define CLK_APBCLK0_USBDCKEN_Msk (0x1ul << CLK_APBCLK0_USBDCKEN_Pos) /*!< CLK_T::APBCLK0: USBDCKEN Mask */ + +#define CLK_APBCLK0_EADCCKEN_Pos (28) /*!< CLK_T::APBCLK0: EADCCKEN Position */ +#define CLK_APBCLK0_EADCCKEN_Msk (0x1ul << CLK_APBCLK0_EADCCKEN_Pos) /*!< CLK_T::APBCLK0: EADCCKEN Mask */ + +#define CLK_APBCLK0_I2S0CKEN_Pos (29) /*!< CLK_T::APBCLK0: I2S0CKEN Position */ +#define CLK_APBCLK0_I2S0CKEN_Msk (0x1ul << CLK_APBCLK0_I2S0CKEN_Pos) /*!< CLK_T::APBCLK0: I2S0CKEN Mask */ + +#define CLK_APBCLK0_HSOTGCKEN_Pos (30) /*!< CLK_T::APBCLK0: HSOTGCKEN Position */ +#define CLK_APBCLK0_HSOTGCKEN_Msk (0x1ul << CLK_APBCLK0_HSOTGCKEN_Pos) /*!< CLK_T::APBCLK0: HSOTGCKEN Mask */ + +#define CLK_APBCLK1_SC0CKEN_Pos (0) /*!< CLK_T::APBCLK1: SC0CKEN Position */ +#define CLK_APBCLK1_SC0CKEN_Msk (0x1ul << CLK_APBCLK1_SC0CKEN_Pos) /*!< CLK_T::APBCLK1: SC0CKEN Mask */ + +#define CLK_APBCLK1_SC1CKEN_Pos (1) /*!< CLK_T::APBCLK1: SC1CKEN Position */ +#define CLK_APBCLK1_SC1CKEN_Msk (0x1ul << CLK_APBCLK1_SC1CKEN_Pos) /*!< CLK_T::APBCLK1: SC1CKEN Mask */ + +#define CLK_APBCLK1_SC2CKEN_Pos (2) /*!< CLK_T::APBCLK1: SC2CKEN Position */ +#define CLK_APBCLK1_SC2CKEN_Msk (0x1ul << CLK_APBCLK1_SC2CKEN_Pos) /*!< CLK_T::APBCLK1: SC2CKEN Mask */ + +#define CLK_APBCLK1_QSPI1CKEN_Pos (4) /*!< CLK_T::APBCLK1: QSPI1CKEN Position */ +#define CLK_APBCLK1_QSPI1CKEN_Msk (0x1ul << CLK_APBCLK1_QSPI1CKEN_Pos) /*!< CLK_T::APBCLK1: QSPI1CKEN Mask */ + +#define CLK_APBCLK1_SPI3CKEN_Pos (6) /*!< CLK_T::APBCLK1: SPI3CKEN Position */ +#define CLK_APBCLK1_SPI3CKEN_Msk (0x1ul << CLK_APBCLK1_SPI3CKEN_Pos) /*!< CLK_T::APBCLK1: SPI3CKEN Mask */ + +#define CLK_APBCLK1_USCI0CKEN_Pos (8) /*!< CLK_T::APBCLK1: USCI0CKEN Position */ +#define CLK_APBCLK1_USCI0CKEN_Msk (0x1ul << CLK_APBCLK1_USCI0CKEN_Pos) /*!< CLK_T::APBCLK1: USCI0CKEN Mask */ + +#define CLK_APBCLK1_USCI1CKEN_Pos (9) /*!< CLK_T::APBCLK1: USCI1CKEN Position */ +#define CLK_APBCLK1_USCI1CKEN_Msk (0x1ul << CLK_APBCLK1_USCI1CKEN_Pos) /*!< CLK_T::APBCLK1: USCI1CKEN Mask */ + +#define CLK_APBCLK1_DACCKEN_Pos (12) /*!< CLK_T::APBCLK1: DACCKEN Position */ +#define CLK_APBCLK1_DACCKEN_Msk (0x1ul << CLK_APBCLK1_DACCKEN_Pos) /*!< CLK_T::APBCLK1: DACCKEN Mask */ + +#define CLK_APBCLK1_EPWM0CKEN_Pos (16) /*!< CLK_T::APBCLK1: EPWM0CKEN Position */ +#define CLK_APBCLK1_EPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM0CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM0CKEN Mask */ + +#define CLK_APBCLK1_EPWM1CKEN_Pos (17) /*!< CLK_T::APBCLK1: EPWM1CKEN Position */ +#define CLK_APBCLK1_EPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM1CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM1CKEN Mask */ + +#define CLK_APBCLK1_BPWM0CKEN_Pos (18) /*!< CLK_T::APBCLK1: BPWM0CKEN Position */ +#define CLK_APBCLK1_BPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM0CKEN_Pos) /*!< CLK_T::APBCLK1: BPWM0CKEN Mask */ + +#define CLK_APBCLK1_BPWM1CKEN_Pos (19) /*!< CLK_T::APBCLK1: BPWM1CKEN Position */ +#define CLK_APBCLK1_BPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM1CKEN_Pos) /*!< CLK_T::APBCLK1: BPWM1CKEN Mask */ + +#define CLK_APBCLK1_QEI0CKEN_Pos (22) /*!< CLK_T::APBCLK1: QEI0CKEN Position */ +#define CLK_APBCLK1_QEI0CKEN_Msk (0x1ul << CLK_APBCLK1_QEI0CKEN_Pos) /*!< CLK_T::APBCLK1: QEI0CKEN Mask */ + +#define CLK_APBCLK1_QEI1CKEN_Pos (23) /*!< CLK_T::APBCLK1: QEI1CKEN Position */ +#define CLK_APBCLK1_QEI1CKEN_Msk (0x1ul << CLK_APBCLK1_QEI1CKEN_Pos) /*!< CLK_T::APBCLK1: QEI1CKEN Mask */ + +#define CLK_APBCLK1_TRNGCKEN_Pos (25) /*!< CLK_T::APBCLK1: TRNGCKEN Position */ +#define CLK_APBCLK1_TRNGCKEN_Msk (0x1ul << CLK_APBCLK1_TRNGCKEN_Pos) /*!< CLK_T::APBCLK1: TRNGCKEN Mask */ + +#define CLK_APBCLK1_ECAP0CKEN_Pos (26) /*!< CLK_T::APBCLK1: ECAP0CKEN Position */ +#define CLK_APBCLK1_ECAP0CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP0CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP0CKEN Mask */ + +#define CLK_APBCLK1_ECAP1CKEN_Pos (27) /*!< CLK_T::APBCLK1: ECAP1CKEN Position */ +#define CLK_APBCLK1_ECAP1CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP1CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP1CKEN Mask */ + +#define CLK_APBCLK1_CAN2CKEN_Pos (28) /*!< CLK_T::APBCLK1: CAN2CKEN Position */ +#define CLK_APBCLK1_CAN2CKEN_Msk (0x1ul << CLK_APBCLK1_CAN2CKEN_Pos) /*!< CLK_T::APBCLK1: CAN2CKEN Mask */ + +#define CLK_APBCLK1_OPACKEN_Pos (30) /*!< CLK_T::APBCLK1: OPACKEN Position */ +#define CLK_APBCLK1_OPACKEN_Msk (0x1ul << CLK_APBCLK1_OPACKEN_Pos) /*!< CLK_T::APBCLK1: OPACKEN Mask */ + +#define CLK_APBCLK1_EADC1CKEN_Pos (31) /*!< CLK_T::APBCLK1: EADC1CKEN Position */ +#define CLK_APBCLK1_EADC1CKEN_Msk (0x1ul << CLK_APBCLK1_EADC1CKEN_Pos) /*!< CLK_T::APBCLK1: EADC1CKEN Mask */ + +#define CLK_CLKSEL0_HCLKSEL_Pos (0) /*!< CLK_T::CLKSEL0: HCLKSEL Position */ +#define CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos) /*!< CLK_T::CLKSEL0: HCLKSEL Mask */ + +#define CLK_CLKSEL0_STCLKSEL_Pos (3) /*!< CLK_T::CLKSEL0: STCLKSEL Position */ +#define CLK_CLKSEL0_STCLKSEL_Msk (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos) /*!< CLK_T::CLKSEL0: STCLKSEL Mask */ + +#define CLK_CLKSEL0_USBSEL_Pos (8) /*!< CLK_T::CLKSEL0: PCLK0SEL Position */ +#define CLK_CLKSEL0_USBSEL_Msk (0x1ul << CLK_CLKSEL0_USBSEL_Pos) /*!< CLK_T::CLKSEL0: PCLK0SEL Mask */ + +#define CLK_CLKSEL0_CCAPSEL_Pos (16) /*!< CLK_T::CLKSEL0: CCAPSEL Position */ +#define CLK_CLKSEL0_CCAPSEL_Msk (0x3ul << CLK_CLKSEL0_CCAPSEL_Pos) /*!< CLK_T::CLKSEL0: CCAPSEL Mask */ + +#define CLK_CLKSEL0_SDH0SEL_Pos (20) /*!< CLK_T::CLKSEL0: SDH0SEL Position */ +#define CLK_CLKSEL0_SDH0SEL_Msk (0x3ul << CLK_CLKSEL0_SDH0SEL_Pos) /*!< CLK_T::CLKSEL0: SDH0SEL Mask */ + +#define CLK_CLKSEL0_SDH1SEL_Pos (22) /*!< CLK_T::CLKSEL0: SDH1SEL Position */ +#define CLK_CLKSEL0_SDH1SEL_Msk (0x3ul << CLK_CLKSEL0_SDH1SEL_Pos) /*!< CLK_T::CLKSEL0: SDH1SEL Mask */ + +#define CLK_CLKSEL1_WDTSEL_Pos (0) /*!< CLK_T::CLKSEL1: WDTSEL Position */ +#define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos) /*!< CLK_T::CLKSEL1: WDTSEL Mask */ + +#define CLK_CLKSEL1_TMR0SEL_Pos (8) /*!< CLK_T::CLKSEL1: TMR0SEL Position */ +#define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) /*!< CLK_T::CLKSEL1: TMR0SEL Mask */ + +#define CLK_CLKSEL1_TMR1SEL_Pos (12) /*!< CLK_T::CLKSEL1: TMR1SEL Position */ +#define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos) /*!< CLK_T::CLKSEL1: TMR1SEL Mask */ + +#define CLK_CLKSEL1_TMR2SEL_Pos (16) /*!< CLK_T::CLKSEL1: TMR2SEL Position */ +#define CLK_CLKSEL1_TMR2SEL_Msk (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos) /*!< CLK_T::CLKSEL1: TMR2SEL Mask */ + +#define CLK_CLKSEL1_TMR3SEL_Pos (20) /*!< CLK_T::CLKSEL1: TMR3SEL Position */ +#define CLK_CLKSEL1_TMR3SEL_Msk (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos) /*!< CLK_T::CLKSEL1: TMR3SEL Mask */ + +#define CLK_CLKSEL1_UART0SEL_Pos (24) /*!< CLK_T::CLKSEL1: UART0SEL Position */ +#define CLK_CLKSEL1_UART0SEL_Msk (0x3ul << CLK_CLKSEL1_UART0SEL_Pos) /*!< CLK_T::CLKSEL1: UART0SEL Mask */ + +#define CLK_CLKSEL1_UART1SEL_Pos (26) /*!< CLK_T::CLKSEL1: UART1SEL Position */ +#define CLK_CLKSEL1_UART1SEL_Msk (0x3ul << CLK_CLKSEL1_UART1SEL_Pos) /*!< CLK_T::CLKSEL1: UART1SEL Mask */ + +#define CLK_CLKSEL1_CLKOSEL_Pos (28) /*!< CLK_T::CLKSEL1: CLKOSEL Position */ +#define CLK_CLKSEL1_CLKOSEL_Msk (0x3ul << CLK_CLKSEL1_CLKOSEL_Pos) /*!< CLK_T::CLKSEL1: CLKOSEL Mask */ + +#define CLK_CLKSEL1_WWDTSEL_Pos (30) /*!< CLK_T::CLKSEL1: WWDTSEL Position */ +#define CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos) /*!< CLK_T::CLKSEL1: WWDTSEL Mask */ + +#define CLK_CLKSEL2_EPWM0SEL_Pos (0) /*!< CLK_T::CLKSEL2: EPWM0SEL Position */ +#define CLK_CLKSEL2_EPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< CLK_T::CLKSEL2: EPWM0SEL Mask */ + +#define CLK_CLKSEL2_EPWM1SEL_Pos (1) /*!< CLK_T::CLKSEL2: EPWM1SEL Position */ +#define CLK_CLKSEL2_EPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< CLK_T::CLKSEL2: EPWM1SEL Mask */ + +#define CLK_CLKSEL2_QSPI0SEL_Pos (2) /*!< CLK_T::CLKSEL2: QSPI0SEL Position */ +#define CLK_CLKSEL2_QSPI0SEL_Msk (0x3ul << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< CLK_T::CLKSEL2: QSPI0SEL Mask */ + +#define CLK_CLKSEL2_SPI0SEL_Pos (4) /*!< CLK_T::CLKSEL2: SPI0SEL Position */ +#define CLK_CLKSEL2_SPI0SEL_Msk (0x3ul << CLK_CLKSEL2_SPI0SEL_Pos) /*!< CLK_T::CLKSEL2: SPI0SEL Mask */ + +#define CLK_CLKSEL2_SPI1SEL_Pos (6) /*!< CLK_T::CLKSEL2: SPI1SEL Position */ +#define CLK_CLKSEL2_SPI1SEL_Msk (0x3ul << CLK_CLKSEL2_SPI1SEL_Pos) /*!< CLK_T::CLKSEL2: SPI1SEL Mask */ + +#define CLK_CLKSEL2_BPWM0SEL_Pos (8) /*!< CLK_T::CLKSEL2: BPWM0SEL Position */ +#define CLK_CLKSEL2_BPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM0SEL_Pos) /*!< CLK_T::CLKSEL2: BPWM0SEL Mask */ + +#define CLK_CLKSEL2_BPWM1SEL_Pos (9) /*!< CLK_T::CLKSEL2: BPWM1SEL Position */ +#define CLK_CLKSEL2_BPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM1SEL_Pos) /*!< CLK_T::CLKSEL2: BPWM1SEL Mask */ + +#define CLK_CLKSEL2_SPI2SEL_Pos (10) /*!< CLK_T::CLKSEL2: SPI2SEL Position */ +#define CLK_CLKSEL2_SPI2SEL_Msk (0x3ul << CLK_CLKSEL2_SPI2SEL_Pos) /*!< CLK_T::CLKSEL2: SPI2SEL Mask */ + +#define CLK_CLKSEL2_SPI3SEL_Pos (12) /*!< CLK_T::CLKSEL2: SPI3SEL Position */ +#define CLK_CLKSEL2_SPI3SEL_Msk (0x3ul << CLK_CLKSEL2_SPI3SEL_Pos) /*!< CLK_T::CLKSEL2: SPI3SEL Mask */ + +#define CLK_CLKSEL3_SC0SEL_Pos (0) /*!< CLK_T::CLKSEL3: SC0SEL Position */ +#define CLK_CLKSEL3_SC0SEL_Msk (0x3ul << CLK_CLKSEL3_SC0SEL_Pos) /*!< CLK_T::CLKSEL3: SC0SEL Mask */ + +#define CLK_CLKSEL3_SC1SEL_Pos (2) /*!< CLK_T::CLKSEL3: SC1SEL Position */ +#define CLK_CLKSEL3_SC1SEL_Msk (0x3ul << CLK_CLKSEL3_SC1SEL_Pos) /*!< CLK_T::CLKSEL3: SC1SEL Mask */ + +#define CLK_CLKSEL3_SC2SEL_Pos (4) /*!< CLK_T::CLKSEL3: SC2SEL Position */ +#define CLK_CLKSEL3_SC2SEL_Msk (0x3ul << CLK_CLKSEL3_SC2SEL_Pos) /*!< CLK_T::CLKSEL3: SC2SEL Mask */ + +#define CLK_CLKSEL3_RTCSEL_Pos (8) /*!< CLK_T::CLKSEL3: RTCSEL Position */ +#define CLK_CLKSEL3_RTCSEL_Msk (0x1ul << CLK_CLKSEL3_RTCSEL_Pos) /*!< CLK_T::CLKSEL3: RTCSEL Mask */ + +#define CLK_CLKSEL3_QSPI1SEL_Pos (12) /*!< CLK_T::CLKSEL3: QSPI1SEL Position */ +#define CLK_CLKSEL3_QSPI1SEL_Msk (0x3ul << CLK_CLKSEL3_QSPI1SEL_Pos) /*!< CLK_T::CLKSEL3: QSPI1SEL Mask */ + +#define CLK_CLKSEL3_I2S0SEL_Pos (16) /*!< CLK_T::CLKSEL3: I2S0SEL Position */ +#define CLK_CLKSEL3_I2S0SEL_Msk (0x3ul << CLK_CLKSEL3_I2S0SEL_Pos) /*!< CLK_T::CLKSEL3: I2S0SEL Mask */ + +#define CLK_CLKSEL3_UART6SEL_Pos (20) /*!< CLK_T::CLKSEL3: UART6SEL Position */ +#define CLK_CLKSEL3_UART6SEL_Msk (0x3ul << CLK_CLKSEL3_UART6SEL_Pos) /*!< CLK_T::CLKSEL3: UART6SEL Mask */ + +#define CLK_CLKSEL3_UART7SEL_Pos (22) /*!< CLK_T::CLKSEL3: UART7SEL Position */ +#define CLK_CLKSEL3_UART7SEL_Msk (0x3ul << CLK_CLKSEL3_UART7SEL_Pos) /*!< CLK_T::CLKSEL3: UART7SEL Mask */ + +#define CLK_CLKSEL3_UART2SEL_Pos (24) /*!< CLK_T::CLKSEL3: UART2SEL Position */ +#define CLK_CLKSEL3_UART2SEL_Msk (0x3ul << CLK_CLKSEL3_UART2SEL_Pos) /*!< CLK_T::CLKSEL3: UART2SEL Mask */ + +#define CLK_CLKSEL3_UART3SEL_Pos (26) /*!< CLK_T::CLKSEL3: UART3SEL Position */ +#define CLK_CLKSEL3_UART3SEL_Msk (0x3ul << CLK_CLKSEL3_UART3SEL_Pos) /*!< CLK_T::CLKSEL3: UART3SEL Mask */ + +#define CLK_CLKSEL3_UART4SEL_Pos (28) /*!< CLK_T::CLKSEL3: UART4SEL Position */ +#define CLK_CLKSEL3_UART4SEL_Msk (0x3ul << CLK_CLKSEL3_UART4SEL_Pos) /*!< CLK_T::CLKSEL3: UART4SEL Mask */ + +#define CLK_CLKSEL3_UART5SEL_Pos (30) /*!< CLK_T::CLKSEL3: UART5SEL Position */ +#define CLK_CLKSEL3_UART5SEL_Msk (0x3ul << CLK_CLKSEL3_UART5SEL_Pos) /*!< CLK_T::CLKSEL3: UART5SEL Mask */ + +#define CLK_CLKDIV0_HCLKDIV_Pos (0) /*!< CLK_T::CLKDIV0: HCLKDIV Position */ +#define CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLK_T::CLKDIV0: HCLKDIV Mask */ + +#define CLK_CLKDIV0_USBDIV_Pos (4) /*!< CLK_T::CLKDIV0: USBDIV Position */ +#define CLK_CLKDIV0_USBDIV_Msk (0xful << CLK_CLKDIV0_USBDIV_Pos) /*!< CLK_T::CLKDIV0: USBDIV Mask */ + +#define CLK_CLKDIV0_UART0DIV_Pos (8) /*!< CLK_T::CLKDIV0: UART0DIV Position */ +#define CLK_CLKDIV0_UART0DIV_Msk (0xful << CLK_CLKDIV0_UART0DIV_Pos) /*!< CLK_T::CLKDIV0: UART0DIV Mask */ + +#define CLK_CLKDIV0_UART1DIV_Pos (12) /*!< CLK_T::CLKDIV0: UART1DIV Position */ +#define CLK_CLKDIV0_UART1DIV_Msk (0xful << CLK_CLKDIV0_UART1DIV_Pos) /*!< CLK_T::CLKDIV0: UART1DIV Mask */ + +#define CLK_CLKDIV0_EADCDIV_Pos (16) /*!< CLK_T::CLKDIV0: EADCDIV Position */ +#define CLK_CLKDIV0_EADCDIV_Msk (0xfful << CLK_CLKDIV0_EADCDIV_Pos) /*!< CLK_T::CLKDIV0: EADCDIV Mask */ + +#define CLK_CLKDIV0_SDH0DIV_Pos (24) /*!< CLK_T::CLKDIV0: SDH0DIV Position */ +#define CLK_CLKDIV0_SDH0DIV_Msk (0xfful << CLK_CLKDIV0_SDH0DIV_Pos) /*!< CLK_T::CLKDIV0: SDH0DIV Mask */ + +#define CLK_CLKDIV1_SC0DIV_Pos (0) /*!< CLK_T::CLKDIV1: SC0DIV Position */ +#define CLK_CLKDIV1_SC0DIV_Msk (0xfful << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLK_T::CLKDIV1: SC0DIV Mask */ + +#define CLK_CLKDIV1_SC1DIV_Pos (8) /*!< CLK_T::CLKDIV1: SC1DIV Position */ +#define CLK_CLKDIV1_SC1DIV_Msk (0xfful << CLK_CLKDIV1_SC1DIV_Pos) /*!< CLK_T::CLKDIV1: SC1DIV Mask */ + +#define CLK_CLKDIV1_SC2DIV_Pos (16) /*!< CLK_T::CLKDIV1: SC2DIV Position */ +#define CLK_CLKDIV1_SC2DIV_Msk (0xfful << CLK_CLKDIV1_SC2DIV_Pos) /*!< CLK_T::CLKDIV1: SC2DIV Mask */ + +#define CLK_CLKDIV2_I2SDIV_Pos (0) /*!< CLK_T::CLKDIV2: I2SDIV Position */ +#define CLK_CLKDIV2_I2SDIV_Msk (0xful << CLK_CLKDIV2_I2SDIV_Pos) /*!< CLK_T::CLKDIV2: I2SDIV Mask */ + +#define CLK_CLKDIV2_EADC1DIV_Pos (24) /*!< CLK_T::CLKDIV2: EADC1DIV Position */ +#define CLK_CLKDIV2_EADC1DIV_Msk (0xfful << CLK_CLKDIV2_EADC1DIV_Pos) /*!< CLK_T::CLKDIV2: EADC1DIV Mask */ + +#define CLK_CLKDIV3_CCAPDIV_Pos (0) /*!< CLK_T::CLKDIV3: CCAPDIV Position */ +#define CLK_CLKDIV3_CCAPDIV_Msk (0xfful << CLK_CLKDIV3_CCAPDIV_Pos) /*!< CLK_T::CLKDIV3: CCAPDIV Mask */ + +#define CLK_CLKDIV3_VSENSEDIV_Pos (8) /*!< CLK_T::CLKDIV3: VSENSEDIV Position */ +#define CLK_CLKDIV3_VSENSEDIV_Msk (0xfful << CLK_CLKDIV3_VSENSEDIV_Pos) /*!< CLK_T::CLKDIV3: VSENSEDIV Mask */ + +#define CLK_CLKDIV3_EMACDIV_Pos (16) /*!< CLK_T::CLKDIV3: EMACDIV Position */ +#define CLK_CLKDIV3_EMACDIV_Msk (0xfful << CLK_CLKDIV3_EMACDIV_Pos) /*!< CLK_T::CLKDIV3: EMACDIV Mask */ + +#define CLK_CLKDIV3_SDH1DIV_Pos (24) /*!< CLK_T::CLKDIV3: SDH1DIV Position */ +#define CLK_CLKDIV3_SDH1DIV_Msk (0xfful << CLK_CLKDIV3_SDH1DIV_Pos) /*!< CLK_T::CLKDIV3: SDH1DIV Mask */ + +#define CLK_CLKDIV4_UART2DIV_Pos (0) /*!< CLK_T::CLKDIV4: UART2DIV Position */ +#define CLK_CLKDIV4_UART2DIV_Msk (0xful << CLK_CLKDIV4_UART2DIV_Pos) /*!< CLK_T::CLKDIV4: UART2DIV Mask */ + +#define CLK_CLKDIV4_UART3DIV_Pos (4) /*!< CLK_T::CLKDIV4: UART3DIV Position */ +#define CLK_CLKDIV4_UART3DIV_Msk (0xful << CLK_CLKDIV4_UART3DIV_Pos) /*!< CLK_T::CLKDIV4: UART3DIV Mask */ + +#define CLK_CLKDIV4_UART4DIV_Pos (8) /*!< CLK_T::CLKDIV4: UART4DIV Position */ +#define CLK_CLKDIV4_UART4DIV_Msk (0xful << CLK_CLKDIV4_UART4DIV_Pos) /*!< CLK_T::CLKDIV4: UART4DIV Mask */ + +#define CLK_CLKDIV4_UART5DIV_Pos (12) /*!< CLK_T::CLKDIV4: UART5DIV Position */ +#define CLK_CLKDIV4_UART5DIV_Msk (0xful << CLK_CLKDIV4_UART5DIV_Pos) /*!< CLK_T::CLKDIV4: UART5DIV Mask */ + +#define CLK_CLKDIV4_UART6DIV_Pos (16) /*!< CLK_T::CLKDIV4: UART6DIV Position */ +#define CLK_CLKDIV4_UART6DIV_Msk (0xful << CLK_CLKDIV4_UART6DIV_Pos) /*!< CLK_T::CLKDIV4: UART6DIV Mask */ + +#define CLK_CLKDIV4_UART7DIV_Pos (20) /*!< CLK_T::CLKDIV4: UART7DIV Position */ +#define CLK_CLKDIV4_UART7DIV_Msk (0xful << CLK_CLKDIV4_UART7DIV_Pos) /*!< CLK_T::CLKDIV4: UART7DIV Mask */ + +#define CLK_PCLKDIV_APB0DIV_Pos (0) /*!< CLK_T::PCLKDIV: APB0DIV Position */ +#define CLK_PCLKDIV_APB0DIV_Msk (0x7ul << CLK_PCLKDIV_APB0DIV_Pos) /*!< CLK_T::PCLKDIV: APB0DIV Mask */ + +#define CLK_PCLKDIV_APB1DIV_Pos (4) /*!< CLK_T::PCLKDIV: APB1DIV Position */ +#define CLK_PCLKDIV_APB1DIV_Msk (0x7ul << CLK_PCLKDIV_APB1DIV_Pos) /*!< CLK_T::PCLKDIV: APB1DIV Mask */ + +#define CLK_PLLCTL_FBDIV_Pos (0) /*!< CLK_T::PLLCTL: FBDIV Position */ +#define CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos) /*!< CLK_T::PLLCTL: FBDIV Mask */ + +#define CLK_PLLCTL_INDIV_Pos (9) /*!< CLK_T::PLLCTL: INDIV Position */ +#define CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos) /*!< CLK_T::PLLCTL: INDIV Mask */ + +#define CLK_PLLCTL_OUTDIV_Pos (14) /*!< CLK_T::PLLCTL: OUTDIV Position */ +#define CLK_PLLCTL_OUTDIV_Msk (0x3ul << CLK_PLLCTL_OUTDIV_Pos) /*!< CLK_T::PLLCTL: OUTDIV Mask */ + +#define CLK_PLLCTL_PD_Pos (16) /*!< CLK_T::PLLCTL: PD Position */ +#define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos) /*!< CLK_T::PLLCTL: PD Mask */ + +#define CLK_PLLCTL_BP_Pos (17) /*!< CLK_T::PLLCTL: BP Position */ +#define CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos) /*!< CLK_T::PLLCTL: BP Mask */ + +#define CLK_PLLCTL_OE_Pos (18) /*!< CLK_T::PLLCTL: OE Position */ +#define CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos) /*!< CLK_T::PLLCTL: OE Mask */ + +#define CLK_PLLCTL_PLLSRC_Pos (19) /*!< CLK_T::PLLCTL: PLLSRC Position */ +#define CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos) /*!< CLK_T::PLLCTL: PLLSRC Mask */ + +#define CLK_PLLCTL_STBSEL_Pos (23) /*!< CLK_T::PLLCTL: STBSEL Position */ +#define CLK_PLLCTL_STBSEL_Msk (0x1ul << CLK_PLLCTL_STBSEL_Pos) /*!< CLK_T::PLLCTL: STBSEL Mask */ + +#define CLK_STATUS_HXTSTB_Pos (0) /*!< CLK_T::STATUS: HXTSTB Position */ +#define CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos) /*!< CLK_T::STATUS: HXTSTB Mask */ + +#define CLK_STATUS_LXTSTB_Pos (1) /*!< CLK_T::STATUS: LXTSTB Position */ +#define CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos) /*!< CLK_T::STATUS: LXTSTB Mask */ + +#define CLK_STATUS_PLLSTB_Pos (2) /*!< CLK_T::STATUS: PLLSTB Position */ +#define CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos) /*!< CLK_T::STATUS: PLLSTB Mask */ + +#define CLK_STATUS_LIRCSTB_Pos (3) /*!< CLK_T::STATUS: LIRCSTB Position */ +#define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos) /*!< CLK_T::STATUS: LIRCSTB Mask */ + +#define CLK_STATUS_HIRCSTB_Pos (4) /*!< CLK_T::STATUS: HIRCSTB Position */ +#define CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos) /*!< CLK_T::STATUS: HIRCSTB Mask */ + +#define CLK_STATUS_HIRC48MSTB_Pos (6) /*!< CLK_T::STATUS: HIRC48MSTB Position */ +#define CLK_STATUS_HIRC48MSTB_Msk (0x1ul << CLK_STATUS_HIRC48MSTB_Pos) /*!< CLK_T::STATUS: HIRC48MSTB Mask */ + +#define CLK_STATUS_CLKSFAIL_Pos (7) /*!< CLK_T::STATUS: CLKSFAIL Position */ +#define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos) /*!< CLK_T::STATUS: CLKSFAIL Mask */ + +#define CLK_CLKOCTL_FREQSEL_Pos (0) /*!< CLK_T::CLKOCTL: FREQSEL Position */ +#define CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos) /*!< CLK_T::CLKOCTL: FREQSEL Mask */ + +#define CLK_CLKOCTL_CLKOEN_Pos (4) /*!< CLK_T::CLKOCTL: CLKOEN Position */ +#define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos) /*!< CLK_T::CLKOCTL: CLKOEN Mask */ + +#define CLK_CLKOCTL_DIV1EN_Pos (5) /*!< CLK_T::CLKOCTL: DIV1EN Position */ +#define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos) /*!< CLK_T::CLKOCTL: DIV1EN Mask */ + +#define CLK_CLKOCTL_CLK1HZEN_Pos (6) /*!< CLK_T::CLKOCTL: CLK1HZEN Position */ +#define CLK_CLKOCTL_CLK1HZEN_Msk (0x1ul << CLK_CLKOCTL_CLK1HZEN_Pos) /*!< CLK_T::CLKOCTL: CLK1HZEN Mask */ + +#define CLK_CLKDCTL_HXTFDEN_Pos (4) /*!< CLK_T::CLKDCTL: HXTFDEN Position */ +#define CLK_CLKDCTL_HXTFDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFDEN Mask */ + +#define CLK_CLKDCTL_HXTFIEN_Pos (5) /*!< CLK_T::CLKDCTL: HXTFIEN Position */ +#define CLK_CLKDCTL_HXTFIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFIEN Mask */ + +#define CLK_CLKDCTL_LXTFDEN_Pos (12) /*!< CLK_T::CLKDCTL: LXTFDEN Position */ +#define CLK_CLKDCTL_LXTFDEN_Msk (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos) /*!< CLK_T::CLKDCTL: LXTFDEN Mask */ + +#define CLK_CLKDCTL_LXTFIEN_Pos (13) /*!< CLK_T::CLKDCTL: LXTFIEN Position */ +#define CLK_CLKDCTL_LXTFIEN_Msk (0x1ul << CLK_CLKDCTL_LXTFIEN_Pos) /*!< CLK_T::CLKDCTL: LXTFIEN Mask */ + +#define CLK_CLKDCTL_HXTFQDEN_Pos (16) /*!< CLK_T::CLKDCTL: HXTFQDEN Position */ +#define CLK_CLKDCTL_HXTFQDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQDEN Mask */ + +#define CLK_CLKDCTL_HXTFQIEN_Pos (17) /*!< CLK_T::CLKDCTL: HXTFQIEN Position */ +#define CLK_CLKDCTL_HXTFQIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQIEN Mask */ + +#define CLK_CLKDSTS_HXTFIF_Pos (0) /*!< CLK_T::CLKDSTS: HXTFIF Position */ +#define CLK_CLKDSTS_HXTFIF_Msk (0x1ul << CLK_CLKDSTS_HXTFIF_Pos) /*!< CLK_T::CLKDSTS: HXTFIF Mask */ + +#define CLK_CLKDSTS_LXTFIF_Pos (1) /*!< CLK_T::CLKDSTS: LXTFIF Position */ +#define CLK_CLKDSTS_LXTFIF_Msk (0x1ul << CLK_CLKDSTS_LXTFIF_Pos) /*!< CLK_T::CLKDSTS: LXTFIF Mask */ + +#define CLK_CLKDSTS_HXTFQIF_Pos (8) /*!< CLK_T::CLKDSTS: HXTFQIF Position */ +#define CLK_CLKDSTS_HXTFQIF_Msk (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos) /*!< CLK_T::CLKDSTS: HXTFQIF Mask */ + +#define CLK_CDUPB_UPERBD_Pos (0) /*!< CLK_T::CDUPB: UPERBD Position */ +#define CLK_CDUPB_UPERBD_Msk (0x3fful << CLK_CDUPB_UPERBD_Pos) /*!< CLK_T::CDUPB: UPERBD Mask */ + +#define CLK_CDLOWB_LOWERBD_Pos (0) /*!< CLK_T::CDLOWB: LOWERBD Position */ +#define CLK_CDLOWB_LOWERBD_Msk (0x3fful << CLK_CDLOWB_LOWERBD_Pos) /*!< CLK_T::CDLOWB: LOWERBD Mask */ + +#define CLK_PMUCTL_PDMSEL_Pos (0) /*!< CLK_T::PMUCTL: PDMSEL Position */ +#define CLK_PMUCTL_PDMSEL_Msk (0x7ul << CLK_PMUCTL_PDMSEL_Pos) /*!< CLK_T::PMUCTL: PDMSEL Mask */ + +#define CLK_PMUCTL_DPDHOLDEN_Pos (3) /*!< CLK_T::PMUCTL: DPDHOLDEN Position */ +#define CLK_PMUCTL_DPDHOLDEN_Msk (0x1ul << CLK_PMUCTL_DPDHOLDEN_Pos) /*!< CLK_T::PMUCTL: DPDHOLDEN Mask */ + +#define CLK_PMUCTL_SRETSEL_Pos (4) /*!< CLK_T::PMUCTL: SRETSEL Position */ +#define CLK_PMUCTL_SRETSEL_Msk (0x7ul << CLK_PMUCTL_SRETSEL_Pos) /*!< CLK_T::PMUCTL: SRETSEL Mask */ + +#define CLK_PMUCTL_WKTMREN_Pos (8) /*!< CLK_T::PMUCTL: WKTMREN Position */ +#define CLK_PMUCTL_WKTMREN_Msk (0x1ul << CLK_PMUCTL_WKTMREN_Pos) /*!< CLK_T::PMUCTL: WKTMREN Mask */ + +#define CLK_PMUCTL_WKTMRIS_Pos (9) /*!< CLK_T::PMUCTL: WKTMRIS Position */ +#define CLK_PMUCTL_WKTMRIS_Msk (0xful << CLK_PMUCTL_WKTMRIS_Pos) /*!< CLK_T::PMUCTL: WKTMRIS Mask */ + +#define CLK_PMUCTL_WKPINEN_Pos (16) /*!< CLK_T::PMUCTL: WKPINEN Position */ +#define CLK_PMUCTL_WKPINEN_Msk (0x3ul << CLK_PMUCTL_WKPINEN_Pos) /*!< CLK_T::PMUCTL: WKPINEN Mask */ + +#define CLK_PMUCTL_ACMPSPWK_Pos (18) /*!< CLK_T::PMUCTL: ACMPSPWK Position */ +#define CLK_PMUCTL_ACMPSPWK_Msk (0x1ul << CLK_PMUCTL_ACMPSPWK_Pos) /*!< CLK_T::PMUCTL: ACMPSPWK Mask */ + +#define CLK_PMUCTL_RTCWKEN_Pos (23) /*!< CLK_T::PMUCTL: RTCWKEN Position */ +#define CLK_PMUCTL_RTCWKEN_Msk (0x1ul << CLK_PMUCTL_RTCWKEN_Pos) /*!< CLK_T::PMUCTL: RTCWKEN Mask */ + +#define CLK_PMUCTL_WKPINEN1_Pos (24) /*!< CLK_T::PMUCTL: WKPINEN1 Position */ +#define CLK_PMUCTL_WKPINEN1_Msk (0x3ul << CLK_PMUCTL_WKPINEN1_Pos) /*!< CLK_T::PMUCTL: WKPINEN1 Mask */ + +#define CLK_PMUCTL_WKPINEN2_Pos (26) /*!< CLK_T::PMUCTL: WKPINEN2 Position */ +#define CLK_PMUCTL_WKPINEN2_Msk (0x3ul << CLK_PMUCTL_WKPINEN2_Pos) /*!< CLK_T::PMUCTL: WKPINEN2 Mask */ + +#define CLK_PMUCTL_WKPINEN3_Pos (28) /*!< CLK_T::PMUCTL: WKPINEN3 Position */ +#define CLK_PMUCTL_WKPINEN3_Msk (0x3ul << CLK_PMUCTL_WKPINEN3_Pos) /*!< CLK_T::PMUCTL: WKPINEN3 Mask */ + +#define CLK_PMUCTL_WKPINEN4_Pos (30) /*!< CLK_T::PMUCTL: WKPINEN4 Position */ +#define CLK_PMUCTL_WKPINEN4_Msk (0x3ul << CLK_PMUCTL_WKPINEN4_Pos) /*!< CLK_T::PMUCTL: WKPINEN4 Mask */ + +#define CLK_PMUSTS_PINWK_Pos (0) /*!< CLK_T::PMUSTS: PINWK Position */ +#define CLK_PMUSTS_PINWK_Msk (0x1ul << CLK_PMUSTS_PINWK_Pos) /*!< CLK_T::PMUSTS: PINWK Mask */ + +#define CLK_PMUSTS_TMRWK_Pos (1) /*!< CLK_T::PMUSTS: TMRWK Position */ +#define CLK_PMUSTS_TMRWK_Msk (0x1ul << CLK_PMUSTS_TMRWK_Pos) /*!< CLK_T::PMUSTS: TMRWK Mask */ + +#define CLK_PMUSTS_RTCWK_Pos (2) /*!< CLK_T::PMUSTS: RTCWK Position */ +#define CLK_PMUSTS_RTCWK_Msk (0x1ul << CLK_PMUSTS_RTCWK_Pos) /*!< CLK_T::PMUSTS: RTCWK Mask */ + +#define CLK_PMUSTS_PINWK1_Pos (3) /*!< CLK_T::PMUSTS: PINWK1 Position */ +#define CLK_PMUSTS_PINWK1_Msk (0x1ul << CLK_PMUSTS_PINWK1_Pos) /*!< CLK_T::PMUSTS: PINWK1 Mask */ + +#define CLK_PMUSTS_PINWK2_Pos (4) /*!< CLK_T::PMUSTS: PINWK2 Position */ +#define CLK_PMUSTS_PINWK2_Msk (0x1ul << CLK_PMUSTS_PINWK2_Pos) /*!< CLK_T::PMUSTS: PINWK2 Mask */ + +#define CLK_PMUSTS_PINWK3_Pos (5) /*!< CLK_T::PMUSTS: PINWK3 Position */ +#define CLK_PMUSTS_PINWK3_Msk (0x1ul << CLK_PMUSTS_PINWK3_Pos) /*!< CLK_T::PMUSTS: PINWK3 Mask */ + +#define CLK_PMUSTS_PINWK4_Pos (6) /*!< CLK_T::PMUSTS: PINWK4 Position */ +#define CLK_PMUSTS_PINWK4_Msk (0x1ul << CLK_PMUSTS_PINWK4_Pos) /*!< CLK_T::PMUSTS: PINWK4 Mask */ + +#define CLK_PMUSTS_GPAWK_Pos (8) /*!< CLK_T::PMUSTS: GPAWK Position */ +#define CLK_PMUSTS_GPAWK_Msk (0x1ul << CLK_PMUSTS_GPAWK_Pos) /*!< CLK_T::PMUSTS: GPAWK Mask */ + +#define CLK_PMUSTS_GPBWK_Pos (9) /*!< CLK_T::PMUSTS: GPBWK Position */ +#define CLK_PMUSTS_GPBWK_Msk (0x1ul << CLK_PMUSTS_GPBWK_Pos) /*!< CLK_T::PMUSTS: GPBWK Mask */ + +#define CLK_PMUSTS_GPCWK_Pos (10) /*!< CLK_T::PMUSTS: GPCWK Position */ +#define CLK_PMUSTS_GPCWK_Msk (0x1ul << CLK_PMUSTS_GPCWK_Pos) /*!< CLK_T::PMUSTS: GPCWK Mask */ + +#define CLK_PMUSTS_GPDWK_Pos (11) /*!< CLK_T::PMUSTS: GPDWK Position */ +#define CLK_PMUSTS_GPDWK_Msk (0x1ul << CLK_PMUSTS_GPDWK_Pos) /*!< CLK_T::PMUSTS: GPDWK Mask */ + +#define CLK_PMUSTS_LVRWK_Pos (12) /*!< CLK_T::PMUSTS: LVRWK Position */ +#define CLK_PMUSTS_LVRWK_Msk (0x1ul << CLK_PMUSTS_LVRWK_Pos) /*!< CLK_T::PMUSTS: LVRWK Mask */ + +#define CLK_PMUSTS_BODWK_Pos (13) /*!< CLK_T::PMUSTS: BODWK Position */ +#define CLK_PMUSTS_BODWK_Msk (0x1ul << CLK_PMUSTS_BODWK_Pos) /*!< CLK_T::PMUSTS: BODWK Mask */ + +#define CLK_PMUSTS_ACMPWK_Pos (14) /*!< CLK_T::PMUSTS: ACMPWK Position */ +#define CLK_PMUSTS_ACMPWK_Msk (0x1ul << CLK_PMUSTS_ACMPWK_Pos) /*!< CLK_T::PMUSTS: ACMPWK Mask */ + +#define CLK_PMUSTS_CLRWK_Pos (31) /*!< CLK_T::PMUSTS: CLRWK Position */ +#define CLK_PMUSTS_CLRWK_Msk (0x1ul << CLK_PMUSTS_CLRWK_Pos) /*!< CLK_T::PMUSTS: CLRWK Mask */ + +#define CLK_LDOCTL_PDBIASEN_Pos (18) /*!< CLK_T::LDOCTL: PDBIASEN Position */ +#define CLK_LDOCTL_PDBIASEN_Msk (0x1ul << CLK_LDOCTL_PDBIASEN_Pos) /*!< CLK_T::LDOCTL: PDBIASEN Mask */ + +#define CLK_SWKDBCTL_SWKDBCLKSEL_Pos (0) /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Position */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_Msk (0xful << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Mask */ + +#define CLK_PASWKCTL_WKEN_Pos (0) /*!< CLK_T::PASWKCTL: WKEN Position */ +#define CLK_PASWKCTL_WKEN_Msk (0x1ul << CLK_PASWKCTL_WKEN_Pos) /*!< CLK_T::PASWKCTL: WKEN Mask */ + +#define CLK_PASWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PASWKCTL: PRWKEN Position */ +#define CLK_PASWKCTL_PRWKEN_Msk (0x1ul << CLK_PASWKCTL_PRWKEN_Pos) /*!< CLK_T::PASWKCTL: PRWKEN Mask */ + +#define CLK_PASWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PASWKCTL: PFWKEN Position */ +#define CLK_PASWKCTL_PFWKEN_Msk (0x1ul << CLK_PASWKCTL_PFWKEN_Pos) /*!< CLK_T::PASWKCTL: PFWKEN Mask */ + +#define CLK_PASWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PASWKCTL: WKPSEL Position */ +#define CLK_PASWKCTL_WKPSEL_Msk (0xful << CLK_PASWKCTL_WKPSEL_Pos) /*!< CLK_T::PASWKCTL: WKPSEL Mask */ + +#define CLK_PASWKCTL_DBEN_Pos (8) /*!< CLK_T::PASWKCTL: DBEN Position */ +#define CLK_PASWKCTL_DBEN_Msk (0x1ul << CLK_PASWKCTL_DBEN_Pos) /*!< CLK_T::PASWKCTL: DBEN Mask */ + +#define CLK_PBSWKCTL_WKEN_Pos (0) /*!< CLK_T::PBSWKCTL: WKEN Position */ +#define CLK_PBSWKCTL_WKEN_Msk (0x1ul << CLK_PBSWKCTL_WKEN_Pos) /*!< CLK_T::PBSWKCTL: WKEN Mask */ + +#define CLK_PBSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PBSWKCTL: PRWKEN Position */ +#define CLK_PBSWKCTL_PRWKEN_Msk (0x1ul << CLK_PBSWKCTL_PRWKEN_Pos) /*!< CLK_T::PBSWKCTL: PRWKEN Mask */ + +#define CLK_PBSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PBSWKCTL: PFWKEN Position */ +#define CLK_PBSWKCTL_PFWKEN_Msk (0x1ul << CLK_PBSWKCTL_PFWKEN_Pos) /*!< CLK_T::PBSWKCTL: PFWKEN Mask */ + +#define CLK_PBSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PBSWKCTL: WKPSEL Position */ +#define CLK_PBSWKCTL_WKPSEL_Msk (0xful << CLK_PBSWKCTL_WKPSEL_Pos) /*!< CLK_T::PBSWKCTL: WKPSEL Mask */ + +#define CLK_PBSWKCTL_DBEN_Pos (8) /*!< CLK_T::PBSWKCTL: DBEN Position */ +#define CLK_PBSWKCTL_DBEN_Msk (0x1ul << CLK_PBSWKCTL_DBEN_Pos) /*!< CLK_T::PBSWKCTL: DBEN Mask */ + +#define CLK_PCSWKCTL_WKEN_Pos (0) /*!< CLK_T::PCSWKCTL: WKEN Position */ +#define CLK_PCSWKCTL_WKEN_Msk (0x1ul << CLK_PCSWKCTL_WKEN_Pos) /*!< CLK_T::PCSWKCTL: WKEN Mask */ + +#define CLK_PCSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PCSWKCTL: PRWKEN Position */ +#define CLK_PCSWKCTL_PRWKEN_Msk (0x1ul << CLK_PCSWKCTL_PRWKEN_Pos) /*!< CLK_T::PCSWKCTL: PRWKEN Mask */ + +#define CLK_PCSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PCSWKCTL: PFWKEN Position */ +#define CLK_PCSWKCTL_PFWKEN_Msk (0x1ul << CLK_PCSWKCTL_PFWKEN_Pos) /*!< CLK_T::PCSWKCTL: PFWKEN Mask */ + +#define CLK_PCSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PCSWKCTL: WKPSEL Position */ +#define CLK_PCSWKCTL_WKPSEL_Msk (0xful << CLK_PCSWKCTL_WKPSEL_Pos) /*!< CLK_T::PCSWKCTL: WKPSEL Mask */ + +#define CLK_PCSWKCTL_DBEN_Pos (8) /*!< CLK_T::PCSWKCTL: DBEN Position */ +#define CLK_PCSWKCTL_DBEN_Msk (0x1ul << CLK_PCSWKCTL_DBEN_Pos) /*!< CLK_T::PCSWKCTL: DBEN Mask */ + +#define CLK_PDSWKCTL_WKEN_Pos (0) /*!< CLK_T::PDSWKCTL: WKEN Position */ +#define CLK_PDSWKCTL_WKEN_Msk (0x1ul << CLK_PDSWKCTL_WKEN_Pos) /*!< CLK_T::PDSWKCTL: WKEN Mask */ + +#define CLK_PDSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PDSWKCTL: PRWKEN Position */ +#define CLK_PDSWKCTL_PRWKEN_Msk (0x1ul << CLK_PDSWKCTL_PRWKEN_Pos) /*!< CLK_T::PDSWKCTL: PRWKEN Mask */ + +#define CLK_PDSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PDSWKCTL: PFWKEN Position */ +#define CLK_PDSWKCTL_PFWKEN_Msk (0x1ul << CLK_PDSWKCTL_PFWKEN_Pos) /*!< CLK_T::PDSWKCTL: PFWKEN Mask */ + +#define CLK_PDSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PDSWKCTL: WKPSEL Position */ +#define CLK_PDSWKCTL_WKPSEL_Msk (0xful << CLK_PDSWKCTL_WKPSEL_Pos) /*!< CLK_T::PDSWKCTL: WKPSEL Mask */ + +#define CLK_PDSWKCTL_DBEN_Pos (8) /*!< CLK_T::PDSWKCTL: DBEN Position */ +#define CLK_PDSWKCTL_DBEN_Msk (0x1ul << CLK_PDSWKCTL_DBEN_Pos) /*!< CLK_T::PDSWKCTL: DBEN Mask */ + +#define CLK_IOPDCTL_IOHR_Pos (0) /*!< CLK_T::IOPDCTL: IOHR Position */ +#define CLK_IOPDCTL_IOHR_Msk (0x1ul << CLK_IOPDCTL_IOHR_Pos) /*!< CLK_T::IOPDCTL: IOHR Mask */ + +/**@}*/ /* CLK_CONST */ +/**@}*/ /* end of CLK register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __CLK_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/crc_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/crc_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..118f79739a3315f43b155ea434f63e522b4b34d5 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/crc_reg.h @@ -0,0 +1,150 @@ +/**************************************************************************//** + * @file crc_reg.h + * @version V1.00 + * @brief CRC register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CRC_REG_H__ +#define __CRC_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup CRC Cyclic Redundancy Check Controller(CRC) + Memory Mapped Structure for CRC Controller +@{ */ + +typedef struct +{ + + + /** + * @var CRC_T::CTL + * Offset: 0x00 CRC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CRCEN |CRC Channel Enable Bit + * | | |0 = No effect. + * | | |1 = CRC operation Enabled. + * |[1] |CHKSINIT |Checksum Initialization + * | | |0 = No effect. + * | | |1 = Initial checksum value by auto reload CRC_SEED register value to CRC_CHECKSUM register value. + * | | |Note: This bit will be cleared automatically. + * |[24] |DATREV |Write Data Bit Order Reverse + * | | |This bit is used to enable the bit order reverse function per byte for write data value in CRC_DAT register. + * | | |0 = Bit order reversed for CRC write data in Disabled. + * | | |1 = Bit order reversed for CRC write data in Enabled (per byte). + * | | |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB. + * |[25] |CHKSREV |Checksum Bit Order Reverse + * | | |This bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register. + * | | |0 = Bit order reverse for CRC checksum Disabled. + * | | |1 = Bit order reverse for CRC checksum Enabled. + * | | |Note: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB. + * |[26] |DATFMT |Write Data 1's Complement + * | | |This bit is used to enable the 1's complement function for write data value in CRC_DAT register. + * | | |0 = 1's complement for CRC writes data in Disabled. + * | | |1 = 1's complement for CRC writes data in Enabled. + * |[27] |CHKSFMT |Checksum 1's Complement + * | | |This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register. + * | | |0 = 1's complement for CRC checksum Disabled. + * | | |1 = 1's complement for CRC checksum Enabled. + * |[29:28] |DATLEN |CPU Write Data Length + * | | |This field indicates the write data length. + * | | |00 = Data length is 8-bit mode. + * | | |01 = Data length is 16-bit mode. + * | | |1x = Data length is 32-bit mode. + * | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0] + * |[31:30] |CRCMODE |CRC Polynomial Mode + * | | |This field indicates the CRC operation polynomial mode. + * | | |00 = CRC-CCITT Polynomial mode. + * | | |01 = CRC-8 Polynomial mode. + * | | |10 = CRC-16 Polynomial mode. + * | | |11 = CRC-32 Polynomial mode. + * @var CRC_T::DAT + * Offset: 0x04 CRC Write Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |CRC Write Data Bits + * | | |User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation. + * | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]. + * @var CRC_T::SEED + * Offset: 0x08 CRC Seed Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEED |CRC Seed Value + * | | |This field indicates the CRC seed value. + * | | |Note: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after perform CHKSINIT (CRC_CTL[1]). + * @var CRC_T::CHECKSUM + * Offset: 0x0C CRC Checksum Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CHECKSUM |CRC Checksum Results + * | | |This field indicates the CRC checksum result. + */ + __IO uint32_t CTL; /*!< [0x0000] CRC Control Register */ + __IO uint32_t DAT; /*!< [0x0004] CRC Write Data Register */ + __IO uint32_t SEED; /*!< [0x0008] CRC Seed Register */ + __I uint32_t CHECKSUM; /*!< [0x000c] CRC Checksum Register */ + +} CRC_T; + +/** + @addtogroup CRC_CONST CRC Bit Field Definition + Constant Definitions for CRC Controller +@{ */ + +#define CRC_CTL_CRCEN_Pos (0) /*!< CRC_T::CTL: CRCEN Position */ +#define CRC_CTL_CRCEN_Msk (0x1ul << CRC_CTL_CRCEN_Pos) /*!< CRC_T::CTL: CRCEN Mask */ + +#define CRC_CTL_CHKSINIT_Pos (1) /*!< CRC_T::CTL: CHKSINIT Position */ +#define CRC_CTL_CHKSINIT_Msk (0x1ul << CRC_CTL_CHKSINIT_Pos) /*!< CRC_T::CTL: CHKSINIT Mask */ + +#define CRC_CTL_DATREV_Pos (24) /*!< CRC_T::CTL: DATREV Position */ +#define CRC_CTL_DATREV_Msk (0x1ul << CRC_CTL_DATREV_Pos) /*!< CRC_T::CTL: DATREV Mask */ + +#define CRC_CTL_CHKSREV_Pos (25) /*!< CRC_T::CTL: CHKSREV Position */ +#define CRC_CTL_CHKSREV_Msk (0x1ul << CRC_CTL_CHKSREV_Pos) /*!< CRC_T::CTL: CHKSREV Mask */ + +#define CRC_CTL_DATFMT_Pos (26) /*!< CRC_T::CTL: DATFMT Position */ +#define CRC_CTL_DATFMT_Msk (0x1ul << CRC_CTL_DATFMT_Pos) /*!< CRC_T::CTL: DATFMT Mask */ + +#define CRC_CTL_CHKSFMT_Pos (27) /*!< CRC_T::CTL: CHKSFMT Position */ +#define CRC_CTL_CHKSFMT_Msk (0x1ul << CRC_CTL_CHKSFMT_Pos) /*!< CRC_T::CTL: CHKSFMT Mask */ + +#define CRC_CTL_DATLEN_Pos (28) /*!< CRC_T::CTL: DATLEN Position */ +#define CRC_CTL_DATLEN_Msk (0x3ul << CRC_CTL_DATLEN_Pos) /*!< CRC_T::CTL: DATLEN Mask */ + +#define CRC_CTL_CRCMODE_Pos (30) /*!< CRC_T::CTL: CRCMODE Position */ +#define CRC_CTL_CRCMODE_Msk (0x3ul << CRC_CTL_CRCMODE_Pos) /*!< CRC_T::CTL: CRCMODE Mask */ + +#define CRC_DAT_DATA_Pos (0) /*!< CRC_T::DAT: DATA Position */ +#define CRC_DAT_DATA_Msk (0xfffffffful << CRC_DAT_DATA_Pos) /*!< CRC_T::DAT: DATA Mask */ + +#define CRC_SEED_SEED_Pos (0) /*!< CRC_T::SEED: SEED Position */ +#define CRC_SEED_SEED_Msk (0xfffffffful << CRC_SEED_SEED_Pos) /*!< CRC_T::SEED: SEED Mask */ + +#define CRC_CHECKSUM_CHECKSUM_Pos (0) /*!< CRC_T::CHECKSUM: CHECKSUM Position */ +#define CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos) /*!< CRC_T::CHECKSUM: CHECKSUM Mask */ + +/**@}*/ /* CRC_CONST */ +/**@}*/ /* end of CRC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __CRC_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/crypto_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/crypto_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..f385975cb4db7311ca18498a04832b2cbf44a321 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/crypto_reg.h @@ -0,0 +1,2219 @@ +/**************************************************************************//** + * @file crypto_reg.h + * @version V1.00 + * @brief CRYPTO register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CRYPTO_REG_H__ +#define __CRYPTO_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup CRPT Cryptographic Accelerator(CRPT) + Memory Mapped Structure for Cryptographic Accelerator +@{ */ + +typedef struct +{ + + /** + * @var CRPT_T::INTEN + * Offset: 0x00 Crypto Interrupt Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |AESIEN |AES Interrupt Enable Control + * | | |0 = AES interrupt Disabled. + * | | |1 = AES interrupt Enabled. + * | | |In DMA mode, an interrupt will be triggered when amount of data set in AES_DMA_CNT is fed into the AES engine. + * | | |In Non-DMA mode, an interrupt will be triggered when the AES engine finishes the operation. + * |[1] |AESEIEN |AES Error Flag Enable Control + * | | |0 = AES error interrupt flag Disabled. + * | | |1 = AES error interrupt flag Enabled. + * |[8] |TDESIEN |TDES/DES Interrupt Enable Control + * | | |0 = TDES/DES interrupt Disabled. + * | | |1 = TDES/DES interrupt Enabled. + * | | |In DMA mode, an interrupt will be triggered when amount of data set in TDES_DMA_CNT is fed into the TDES engine. + * | | |In Non-DMA mode, an interrupt will be triggered when the TDES engine finishes the operation. + * |[9] |TDESEIEN |TDES/DES Error Flag Enable Control + * | | |0 = TDES/DES error interrupt flag Disabled. + * | | |1 = TDES/DES error interrupt flag Enabled. + * |[16] |PRNGIEN |PRNG Interrupt Enable Control + * | | |0 = PRNG interrupt Disabled. + * | | |1 = PRNG interrupt Enabled. + * |[22] |ECCIEN |ECC Interrupt Enable Control + * | | |0 = ECC interrupt Disabled. + * | | |1 = ECC interrupt Enabled. + * | | |In DMA mode, an interrupt will be triggered when amount of data set in ECC_DMA_CNT is fed into the ECC engine. + * | | |In Non-DMA mode, an interrupt will be triggered when the ECC engine finishes the operation. + * |[23] |ECCEIEN |ECC Error Interrupt Enable Control + * | | |0 = ECC error interrupt flag Disabled. + * | | |1 = ECC error interrupt flag Enabled. + * |[24] |HMACIEN |SHA/HMAC Interrupt Enable Control + * | | |0 = SHA/HMAC interrupt Disabled. + * | | |1 = SHA/HMAC interrupt Enabled. + * | | |In DMA mode, an interrupt will be triggered when amount of data set in SHA _DMA_CNT is fed into the SHA/HMAC engine + * | | |In Non-DMA mode, an interrupt will be triggered when the SHA/HMAC engine finishes the operation. + * |[25] |HMACEIEN |SHA/HMAC Error Interrupt Enable Control + * | | |0 = SHA/HMAC error interrupt flag Disabled. + * | | |1 = SHA/HMAC error interrupt flag Enabled. + * @var CRPT_T::INTSTS + * Offset: 0x04 Crypto Interrupt Flag + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |AESIF |AES Finish Interrupt Flag + * | | |This bit is cleared by writing 1, and it has no effect by writing 0. + * | | |0 = No AES interrupt. + * | | |= AES encryption/decryption done interrupt. + * |[1] |AESEIF |AES Error Flag + * | | |This bit is cleared by writing 1, and it has no effect by writing 0. + * | | |0 = No AES error. + * | | |1 = AES encryption/decryption done interrupt. + * |[8] |TDESIF |TDES/DES Finish Interrupt Flag + * | | |This bit is cleared by writing 1, and it has no effect by writing 0. + * | | |0 = No TDES/DES interrupt. + * | | |1 = TDES/DES encryption/decryption done interrupt. + * |[9] |TDESEIF |TDES/DES Error Flag + * | | |This bit includes the operating and setting error + * | | |The detailed flag is shown in the CRPT_TDES_STS register + * | | |This includes operating and setting error. + * | | |This bit is cleared by writing 1, and it has no effect by writing 0. + * | | |0 = No TDES/DES error. + * | | |1 = TDES/DES encryption/decryption error interrupt. + * |[16] |PRNGIF |PRNG Finish Interrupt Flag + * | | |This bit is cleared by writing 1, and it has no effect by writing 0. + * | | |0 = No PRNG interrupt. + * | | |1 = PRNG key generation done interrupt. + * |[22] |ECCIF |ECC Finish Interrupt Flag + * | | |This bit is cleared by writing 1, and it has no effect by writing 0. + * | | |0 = No ECC interrupt. + * | | |1 = ECC operation done interrupt. + * |[23] |ECCEIF |ECC Error Flag + * | | |This register includes operating and setting error. The detail flag is shown in CRPT_ECC_STS register. + * | | |This bit is cleared by writing 1, and it has no effect by writing 0. + * | | |0 = No ECC error. + * | | |1 = ECC error interrupt. + * |[24] |HMACIF |SHA/HMAC Finish Interrupt Flag + * | | |This bit is cleared by writing 1, and it has no effect by writing 0. + * | | |0 = No SHA/HMAC interrupt. + * | | |1 = SHA/HMAC operation done interrupt. + * |[25] |HMACEIF |SHA/HMAC Error Flag + * | | |This register includes operating and setting error. The detail flag is shown in CRPT_HMAC_STS register. + * | | |This bit is cleared by writing 1, and it has no effect by writing 0. + * | | |0 = No SHA/HMAC error. + * | | |1 = SHA/HMAC error interrupt. + * @var CRPT_T::PRNG_CTL + * Offset: 0x08 PRNG Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |Start PRNG Engine + * | | |0 = Stop PRNG engine. + * | | |1 = Generate new key and store the new key to register CRPT_PRNG_KEYx , which will be cleared when the new key is generated. + * |[1] |SEEDRLD |Reload New Seed for PRNG Engine + * | | |0 = Generating key based on the current seed. + * | | |1 = Reload new seed. + * |[3:2] |KEYSZ |PRNG Generate Key Size + * | | |00 = 64 bits. + * | | |01 = 128 bits. + * | | |10 = 192 bits. + * | | |11 = 256 bits. + * |[8] |BUSY |PRNG Busy (Read Only) + * | | |0 = PRNG engine is idle. + * | | |1 = Indicate that the PRNG engine is generating CRPT_PRNG_KEYx. + * @var CRPT_T::PRNG_SEED + * Offset: 0x0C Seed for PRNG + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEED |Seed for PRNG (Write Only) + * | | |The bits store the seed for PRNG engine. + * @var CRPT_T::PRNG_KEY[8] + * Offset: 0x10 ~ 0x2C PRNG Generated Key0 ~ Key7 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Store PRNG Generated Key (Read Only) + * | | |The bits store the key that is generated by PRNG. + * @var CRPT_T::AES_FDBCK[4] + * Offset: 0x50 ~ 0x5C AES Engine Output Feedback Data after Cryptographic Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |AES Feedback Information + * | | |The feedback value is 128 bits in size. + * | | |The AES engine uses the data from CRPT_AES_FDBCKx as the data inputted to CRPT_AESn_IVx for the next block in DMA cascade mode. + * | | |The AES engine outputs feedback information for IV in the next block's operation + * | | |Software can use this feedback information to implement more than four DMA channels + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to this register in the same channel operation, and then continue the operation with the original setting. + * @var CRPT_T::TDES_FDBCKH + * Offset: 0x60 TDES/DES Engine Output Feedback High Word Data after Cryptographic Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |TDES/DES Feedback + * | | |The feedback value is 64 bits in size. + * | | |The TDES/DES engine uses the data from {CRPT_TDES_FDBCKH, CRPT_TDES_FDBCKL} as the data inputted to {CRPT_TDESn_IVH, CRPT_TDESn_IVL} for the next block in DMA cascade mode + * | | |The feedback register is for CBC, CFB, and OFB mode. + * | | |TDES/DES engine outputs feedback information for IV in the next block's operation + * | | |Software can use this feedback information to implement more than four DMA channels + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to this register in the same channel operation + * | | |Then can continue the operation with the original setting. + * @var CRPT_T::TDES_FDBCKL + * Offset: 0x64 TDES/DES Engine Output Feedback Low Word Data after Cryptographic Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |TDES/DES Feedback + * | | |The feedback value is 64 bits in size. + * | | |The TDES/DES engine uses the data from {CRPT_TDES_FDBCKH, CRPT_TDES_FDBCKL} as the data inputted to {CRPT_TDESn_IVH, CRPT_TDESn_IVL} for the next block in DMA cascade mode + * | | |The feedback register is for CBC, CFB, and OFB mode. + * | | |TDES/DES engine outputs feedback information for IV in the next block's operation + * | | |Software can use this feedback information to implement more than four DMA channels + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to this register in the same channel operation + * | | |Then can continue the operation with the original setting. + * @var CRPT_T::AES_CTL + * Offset: 0x100 AES Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |AES Engine Start + * | | |0 = No effect. + * | | |1 = Start AES engine. BUSY flag will be set. + * | | |Note: This bit is always 0 when it's read back. + * |[1] |STOP |AES Engine Stop + * | | |0 = No effect. + * | | |1 = Stop AES engine. + * | | |Note: This bit is always 0 when it's read back. + * |[3:2] |KEYSZ |AES Key Size + * | | |This bit defines three different key size for AES operation. + * | | |2'b00 = 128 bits key. + * | | |2'b01 = 192 bits key. + * | | |2'b10 = 256 bits key. + * | | |2'b11 = Reserved. + * | | |If the AES accelerator is operating and the corresponding flag BUSY is 1, updating this register has no effect. + * |[5] |DMALAST |AES Last Block + * | | |In DMA mode, this bit must be set as beginning the last DMA cascade round. + * | | |In Non-DMA mode, this bit must be set when feeding in the last block of data in ECB, CBC, CTR, OFB, and CFB mode, and feeding in the (last-1) block of data at CBC-CS1, CBC-CS2, and CBC-CS3 mode. + * | | |This bit is always 0 when it's read back. Must be written again once START is triggered. + * |[6] |DMACSCAD |AES Engine DMA with Cascade Mode + * | | |0 = DMA cascade function Disabled. + * | | |1 = In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation. + * |[7] |DMAEN |AES Engine DMA Enable Control + * | | |0 = AES DMA engine Disabled. + * | | |The AES engine operates in Non-DMA mode, and gets data from the port CRPT_AES_DATIN. + * | | |1 = AES_DMA engine Enabled. + * | | |The AES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic. + * |[15:8] |OPMODE |AES Engine Operation Modes + * | | |0x00 = ECB (Electronic Codebook Mode) 0x01 = CBC (Cipher Block Chaining Mode). + * | | |0x02 = CFB (Cipher Feedback Mode). + * | | |0x03 = OFB (Output Feedback Mode). + * | | |0x04 = CTR (Counter Mode). + * | | |0x10 = CBC-CS1 (CBC Ciphertext-Stealing 1 Mode). + * | | |0x11 = CBC-CS2 (CBC Ciphertext-Stealing 2 Mode). + * | | |0x12 = CBC-CS3 (CBC Ciphertext-Stealing 3 Mode). + * |[16] |ENCRPT |AES Encryption/Decryption + * | | |0 = AES engine executes decryption operation. + * | | |1 = AES engine executes encryption operation. + * |[22] |OUTSWAP |AES Engine Output Data Swap + * | | |0 = Keep the original order. + * | | |1 = The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[23] |INSWAP |AES Engine Input Data Swap + * | | |0 = Keep the original order. + * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[25:24] |CHANNEL |AES Engine Working Channel + * | | |00 = Current control register setting is for channel 0. + * | | |01 = Current control register setting is for channel 1. + * | | |10 = Current control register setting is for channel 2. + * | | |11 = Current control register setting is for channel 3. + * |[30:26] |KEYUNPRT |Unprotect Key + * | | |Writing 0 to CRPT_AES_CTL[31] and "10110" to CRPT_AES_CTL[30:26] is to unprotect the AES key. + * | | |The KEYUNPRT can be read and written + * | | |When it is written as the AES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT. + * |[31] |KEYPRT |Protect Key + * | | |Read as a flag to reflect KEYPRT. + * | | |0 = No effect. + * | | |1 = Protect the content of the AES key from reading + * | | |The return value for reading CRPT_AESn_KEYx is not the content of the registers CRPT_AESn_KEYx + * | | |Once it is set, it can be cleared by asserting KEYUNPRT + * | | |And the key content would be cleared as well. + * @var CRPT_T::AES_STS + * Offset: 0x104 AES Engine Flag + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |AES Engine Busy + * | | |0 = The AES engine is idle or finished. + * | | |1 = The AES engine is under processing. + * |[8] |INBUFEMPTY|AES Input Buffer Empty + * | | |0 = There are some data in input buffer waiting for the AES engine to process. + * | | |1 = AES input buffer is empty + * | | |Software needs to feed data to the AES engine + * | | |Otherwise, the AES engine will be pending to wait for input data. + * |[9] |INBUFFULL |AES Input Buffer Full Flag + * | | |0 = AES input buffer is not full. Software can feed the data into the AES engine. + * | | |1 = AES input buffer is full + * | | |Software cannot feed data to the AES engine + * | | |Otherwise, the flag INBUFERR will be set to 1. + * |[10] |INBUFERR |AES Input Buffer Error Flag + * | | |0 = No error. + * | | |1 = Error happens during feeding data to the AES engine. + * |[12] |CNTERR |CRPT_AESn_CNT Setting Error + * | | |0 = No error in CRPT_AESn_CNT setting. + * | | |1 = CRPT_AESn_CNT is not a multiply of 16 in ECB, CBC, CFB, OFB, and CTR mode. + * |[16] |OUTBUFEMPTY|AES Out Buffer Empty + * | | |0 = AES output buffer is not empty. There are some valid data kept in output buffer. + * | | |1 = AES output buffer is empty + * | | |Software cannot get data from CRPT_AES_DATOUT + * | | |Otherwise, the flag OUTBUFERR will be set to 1 since the output buffer is empty. + * |[17] |OUTBUFFULL|AES Out Buffer Full Flag + * | | |0 = AES output buffer is not full. + * | | |1 = AES output buffer is full, and software needs to get data from CRPT_AES_DATOUT + * | | |Otherwise, the AES engine will be pending since the output buffer is full. + * |[18] |OUTBUFERR |AES Out Buffer Error Flag + * | | |0 = No error. + * | | |1 = Error happens during getting the result from AES engine. + * |[20] |BUSERR |AES DMA Access Bus Error Flag + * | | |0 = No error. + * | | |1 = Bus error will stop DMA operation and AES engine. + * @var CRPT_T::AES_DATIN + * Offset: 0x108 AES Engine Data Input Port Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATIN |AES Engine Input Port + * | | |CPU feeds data to AES engine through this port by checking CRPT_AES_STS. Feed data as INBUFFULL is 0. + * @var CRPT_T::AES_DATOUT + * Offset: 0x10C AES Engine Data Output Port Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATOUT |AES Engine Output Port + * | | |CPU gets results from the AES engine through this port by checking CRPT_AES_STS + * | | |Get data as OUTBUFEMPTY is 0. + * @var CRPT_T::AES0_KEY[8] + * Offset: 0x110 ~ 0x12C AES Key Word 0 ~ 7 Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |CRPT_AESn_KEYx + * | | |The KEY keeps the security key for AES operation. + * | | |n = 0, 1..3. + * | | |x = 0, 1..7. + * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key + * | | |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation + * | | |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation + * | | |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation. + * @var CRPT_T::AES0_IV[4] + * Offset: 0x130 ~ 0x13C AES Initial Vector Word 0 ~ 3 Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |AES Initial Vectors + * | | |n = 0, 1..3. + * | | |x = 0, 1..3. + * | | |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode + * | | |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode. + * @var CRPT_T::AES0_SADDR + * Offset: 0x140 AES DMA Source Address Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |AES DMA Source Address + * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO + * | | |The SADDR keeps the source address of the data buffer where the source text is stored + * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation + * | | |The start of source address should be located at word boundary + * | | |In other words, bit 1 and 0 of SADDR are ignored. + * | | |SADDR can be read and written + * | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of SADDR will be updated later on + * | | |Consequently, software can prepare the DMA source address for the next AES operation. + * | | |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START. + * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. + * @var CRPT_T::AES0_DADDR + * Offset: 0x144 AES DMA Destination Address Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |AES DMA Destination Address + * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO + * | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored + * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished + * | | |The start of destination address should be located at word boundary + * | | |In other words, bit 1 and 0 of DADDR are ignored. + * | | |DADDR can be read and written + * | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of DADDR will be updated later on + * | | |Consequently, software can prepare the destination address for the next AES operation. + * | | |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START. + * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. + * @var CRPT_T::AES0_CNT + * Offset: 0x148 AES Byte Count Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |AES Byte Count + * | | |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode + * | | |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes. + * | | |CRPT_AESn_CNT can be read and written + * | | |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of CRPT_AESn_CNT will be updated later on + * | | |Consequently, software can prepare the byte count of data for the next AES operation. + * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block + * | | |Operations that are less than one block will output unexpected result. + * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data + * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data. + * @var CRPT_T::AES1_KEY[8] + * Offset: 0x14C ~ 0x168 AES Key Word 0 ~ 7 Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |CRPT_AESn_KEYx + * | | |The KEY keeps the security key for AES operation. + * | | |n = 0, 1..3. + * | | |x = 0, 1..7. + * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key + * | | |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation + * | | |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation + * | | |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation. + * @var CRPT_T::AES1_IV[4] + * Offset: 0x16C ~ 0x178 AES Initial Vector Word 0 ~ 3 Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |AES Initial Vectors + * | | |n = 0, 1..3. + * | | |x = 0, 1..3. + * | | |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode + * | | |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode. + * @var CRPT_T::AES1_SADDR + * Offset: 0x17C AES DMA Source Address Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |AES DMA Source Address + * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO + * | | |The SADDR keeps the source address of the data buffer where the source text is stored + * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation + * | | |The start of source address should be located at word boundary + * | | |In other words, bit 1 and 0 of SADDR are ignored. + * | | |SADDR can be read and written + * | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of SADDR will be updated later on + * | | |Consequently, software can prepare the DMA source address for the next AES operation. + * | | |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START. + * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. + * @var CRPT_T::AES1_DADDR + * Offset: 0x180 AES DMA Destination Address Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |AES DMA Destination Address + * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO + * | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored + * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished + * | | |The start of destination address should be located at word boundary + * | | |In other words, bit 1 and 0 of DADDR are ignored. + * | | |DADDR can be read and written + * | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of DADDR will be updated later on + * | | |Consequently, software can prepare the destination address for the next AES operation. + * | | |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START. + * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. + * @var CRPT_T::AES1_CNT + * Offset: 0x184 AES Byte Count Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |AES Byte Count + * | | |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode + * | | |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes. + * | | |CRPT_AESn_CNT can be read and written + * | | |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of CRPT_AESn_CNT will be updated later on + * | | |Consequently, software can prepare the byte count of data for the next AES operation. + * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block + * | | |Operations that are less than one block will output unexpected result. + * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data + * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data. + * @var CRPT_T::AES2_KEY[8] + * Offset: 0x188 ~ 0x1A4 AES Key Word 0 ~ 7 Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |CRPT_AESn_KEYx + * | | |The KEY keeps the security key for AES operation. + * | | |n = 0, 1..3. + * | | |x = 0, 1..7. + * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key + * | | |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation + * | | |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation + * | | |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation. + * @var CRPT_T::AES2_IV[4] + * Offset: 0x1A8 ~ 0x1B4 AES Initial Vector Word 0 ~ 3 Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |AES Initial Vectors + * | | |n = 0, 1..3. + * | | |x = 0, 1..3. + * | | |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode + * | | |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode. + * @var CRPT_T::AES2_SADDR + * Offset: 0x1B8 AES DMA Source Address Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |AES DMA Source Address + * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO + * | | |The SADDR keeps the source address of the data buffer where the source text is stored + * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation + * | | |The start of source address should be located at word boundary + * | | |In other words, bit 1 and 0 of SADDR are ignored. + * | | |SADDR can be read and written + * | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of SADDR will be updated later on + * | | |Consequently, software can prepare the DMA source address for the next AES operation. + * | | |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START. + * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. + * @var CRPT_T::AES2_DADDR + * Offset: 0x1BC AES DMA Destination Address Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |AES DMA Destination Address + * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO + * | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored + * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished + * | | |The start of destination address should be located at word boundary + * | | |In other words, bit 1 and 0 of DADDR are ignored. + * | | |DADDR can be read and written + * | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of DADDR will be updated later on + * | | |Consequently, software can prepare the destination address for the next AES operation. + * | | |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START. + * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. + * @var CRPT_T::AES2_CNT + * Offset: 0x1C0 AES Byte Count Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |AES Byte Count + * | | |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode + * | | |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes. + * | | |CRPT_AESn_CNT can be read and written + * | | |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of CRPT_AESn_CNT will be updated later on + * | | |Consequently, software can prepare the byte count of data for the next AES operation. + * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block + * | | |Operations that are less than one block will output unexpected result. + * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data + * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data. + * @var CRPT_T::AES3_KEY[8] + * Offset: 0x1C4 ~ 0x1E0 AES Key Word 0 ~ 7 Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |CRPT_AESn_KEYx + * | | |The KEY keeps the security key for AES operation. + * | | |n = 0, 1..3. + * | | |x = 0, 1..7. + * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key + * | | |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation + * | | |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation + * | | |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation. + * @var CRPT_T::AES3_IV[4] + * Offset: 0x1E4 ~ 0x1F0 AES Initial Vector Word 0 ~ 3 Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |AES Initial Vectors + * | | |n = 0, 1..3. + * | | |x = 0, 1..3. + * | | |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode + * | | |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode. + * @var CRPT_T::AES3_SADDR + * Offset: 0x1F4 AES DMA Source Address Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |AES DMA Source Address + * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO + * | | |The SADDR keeps the source address of the data buffer where the source text is stored + * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation + * | | |The start of source address should be located at word boundary + * | | |In other words, bit 1 and 0 of SADDR are ignored. + * | | |SADDR can be read and written + * | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of SADDR will be updated later on + * | | |Consequently, software can prepare the DMA source address for the next AES operation. + * | | |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START. + * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. + * @var CRPT_T::AES3_DADDR + * Offset: 0x1F8 AES DMA Destination Address Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |AES DMA Destination Address + * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO + * | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored + * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished + * | | |The start of destination address should be located at word boundary + * | | |In other words, bit 1 and 0 of DADDR are ignored. + * | | |DADDR can be read and written + * | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of DADDR will be updated later on + * | | |Consequently, software can prepare the destination address for the next AES operation. + * | | |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START. + * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. + * @var CRPT_T::AES3_CNT + * Offset: 0x1FC AES Byte Count Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |AES Byte Count + * | | |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode + * | | |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes. + * | | |CRPT_AESn_CNT can be read and written + * | | |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of CRPT_AESn_CNT will be updated later on + * | | |Consequently, software can prepare the byte count of data for the next AES operation. + * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block + * | | |Operations that are less than one block will output unexpected result. + * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data + * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data. + * @var CRPT_T::TDES_CTL + * Offset: 0x200 TDES/DES Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |TDES/DES Engine Start + * | | |0 = No effect. + * | | |1 = Start TDES/DES engine. The flag BUSY would be set. + * | | |Note: The bit is always 0 when it's read back. + * |[1] |STOP |TDES/DES Engine Stop + * | | |0 = No effect. + * | | |1 = Stop TDES/DES engine. + * | | |Note: The bit is always 0 when it's read back. + * |[2] |TMODE |TDES/DES Engine Operating Mode + * | | |0 = Set DES mode for TDES/DES engine. + * | | |1 = Set Triple DES mode for TDES/DES engine. + * |[3] |3KEYS |TDES/DES Key Number + * | | |0 = Select KEY1 and KEY2 in TDES/DES engine. + * | | |1 = Triple keys in TDES/DES engine Enabled. + * |[5] |DMALAST |TDES/DES Engine Start for the Last Block + * | | |In DMA mode, this bit must be set as beginning the last DMA cascade round. + * | | |In Non-DMA mode, this bit must be set as feeding in last block of data. + * |[6] |DMACSCAD |TDES/DES Engine DMA with Cascade Mode + * | | |0 = DMA cascade function Disabled. + * | | |1 = In DMA Cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation. + * |[7] |DMAEN |TDES/DES Engine DMA Enable Control + * | | |0 = TDES_DMA engine Disabled. + * | | |TDES engine operates in Non-DMA mode, and get data from the port CRPT_TDES_DATIN. + * | | |1 = TDES_DMA engine Enabled. + * | | |TDES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic. + * |[10:8] |OPMODE |TDES/DES Engine Operation Mode + * | | |0x00 = ECB (Electronic Codebook Mode). + * | | |0x01 = CBC (Cipher Block Chaining Mode). + * | | |0x02 = CFB (Cipher Feedback Mode). + * | | |0x03 = OFB (Output Feedback Mode). + * | | |0x04 = CTR (Counter Mode). + * | | |Others = CTR (Counter Mode). + * |[16] |ENCRPT |TDES/DES Encryption/Decryption + * | | |0 = TDES engine executes decryption operation. + * | | |1 = TDES engine executes encryption operation. + * |[21] |BLKSWAP |TDES/DES Engine Block Double Word Endian Swap + * | | |0 = Keep the original order, e.g. {WORD_H, WORD_L}. + * | | |1 = When this bit is set to 1, the TDES engine would exchange high and low word in the sequence {WORD_L, WORD_H}. + * |[22] |OUTSWAP |TDES/DES Engine Output Data Swap + * | | |0 = Keep the original order. + * | | |1 = The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[23] |INSWAP |TDES/DES Engine Input Data Swap + * | | |0 = Keep the original order. + * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[25:24] |CHANNEL |TDES/DES Engine Working Channel + * | | |00 = Current control register setting is for channel 0. + * | | |01 = Current control register setting is for channel 1. + * | | |10 = Current control register setting is for channel 2. + * | | |11 = Current control register setting is for channel 3. + * |[30:26] |KEYUNPRT |Unprotect Key + * | | |Writing 0 to CRPT_TDES_CTL [31] and "10110" to CRPT_TDES_CTL [30:26] is to unprotect TDES key. + * | | |The KEYUNPRT can be read and written + * | | |When it is written as the TDES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT. + * |[31] |KEYPRT |Protect Key + * | | |Read as a flag to reflect KEYPRT. + * | | |0 = No effect. + * | | |1 = This bit is to protect the content of TDES key from reading + * | | |The return value for reading CRPT_ TDESn_KEYxH/L is not the content in the registers CRPT_ TDESn_KEYxH/L + * | | |Once it is set, it can be cleared by asserting KEYUNPRT + * | | |The key content would be cleared as well. + * @var CRPT_T::TDES_STS + * Offset: 0x204 TDES/DES Engine Flag + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |TDES/DES Engine Busy + * | | |0 = TDES/DES engine is idle or finished. + * | | |1 = TDES/DES engine is under processing. + * |[8] |INBUFEMPTY|TDES/DES in Buffer Empty + * | | |0 = There are some data in input buffer waiting for the TDES/DES engine to process. + * | | |1 = TDES/DES input buffer is empty + * | | |Software needs to feed data to the TDES/DES engine + * | | |Otherwise, the TDES/DES engine will be pending to wait for input data. + * |[9] |INBUFFULL |TDES/DES in Buffer Full Flag + * | | |0 = TDES/DES input buffer is not full. Software can feed the data into the TDES/DES engine. + * | | |1 = TDES input buffer is full + * | | |Software cannot feed data to the TDES/DES engine + * | | |Otherwise, the flag INBUFERR will be set to 1. + * |[10] |INBUFERR |TDES/DES in Buffer Error Flag + * | | |0 = No error. + * | | |1 = Error happens during feeding data to the TDES/DES engine. + * |[16] |OUTBUFEMPTY|TDES/DES Output Buffer Empty Flag + * | | |0 = TDES/DES output buffer is not empty. There are some valid data kept in output buffer. + * | | |1 = TDES/DES output buffer is empty, Software cannot get data from TDES_DATA_OUT + * | | |Otherwise the flag OUTBUFERR will be set to 1, since output buffer is empty. + * |[17] |OUTBUFFULL|TDES/DES Output Buffer Full Flag + * | | |0 = TDES/DES output buffer is not full. + * | | |1 = TDES/DES output buffer is full, and software needs to get data from TDES_DATA_OUT + * | | |Otherwise, the TDES/DES engine will be pending since output buffer is full. + * |[18] |OUTBUFERR |TDES/DES Out Buffer Error Flag + * | | |0 = No error. + * | | |1 = Error happens during getting test result from TDES/DES engine. + * |[20] |BUSERR |TDES/DES DMA Access Bus Error Flag + * | | |0 = No error. + * | | |1 = Bus error will stop DMA operation and TDES/DES engine. + * @var CRPT_T::TDES0_KEY1H + * Offset: 0x208 TDES/DES Key 1 High Word Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 1 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES0_KEY1L + * Offset: 0x20C TDES/DES Key 1 Low Word Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 1 Low Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES0_KEY2H + * Offset: 0x210 TDES Key 2 High Word Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 2 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES0_KEY2L + * Offset: 0x214 TDES Key 2 Low Word Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 2 Low Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES0_KEY3H + * Offset: 0x218 TDES Key 3 High Word Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 3 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES0_KEY3L + * Offset: 0x21C TDES Key 3 Low Word Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 3 Low Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES0_IVH + * Offset: 0x220 TDES/DES Initial Vector High Word Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |TDES/DES Initial Vector High Word + * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode + * | | |IV is Nonce counter for TDES/DES engine in CTR mode. + * @var CRPT_T::TDES0_IVL + * Offset: 0x224 TDES/DES Initial Vector Low Word Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |TDES/DES Initial Vector Low Word + * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode + * | | |IV is Nonce counter for TDES/DES engine in CTR mode. + * @var CRPT_T::TDES0_SA + * Offset: 0x228 TDES/DES DMA Source Address Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |TDES/DES DMA Source Address + * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO + * | | |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored + * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation + * | | |The start of source address should be located at word boundary + * | | |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored. + * | | |CRPT_TDESn_SA can be read and written + * | | |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation + * | | |But the value of CRPT_TDESn_SA will be updated later on + * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation. + * | | |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START. + * | | |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value. + * @var CRPT_T::TDES0_DA + * Offset: 0x22C TDES/DES DMA Destination Address Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |TDES/DES DMA Destination Address + * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO + * | | |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored + * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished + * | | |The start of destination address should be located at word boundary + * | | |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored. + * | | |CRPT_TDESn_DA can be read and written + * | | |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation + * | | |But the value of CRPT_TDESn_DA will be updated later on + * | | |Consequently, software can prepare the destination address for the next TDES/DES operation. + * | | |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START. + * | | |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value. + * @var CRPT_T::TDES0_CNT + * Offset: 0x230 TDES/DES Byte Count Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |TDES/DES Byte Count + * | | |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode + * | | |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes. + * | | |CRPT_TDESn_CNT can be read and written + * | | |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation + * | | |But the value of CRPT_TDESn_CNT will be updated later on + * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation. + * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data. + * @var CRPT_T::TDES_DATIN + * Offset: 0x234 TDES/DES Engine Input data Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATIN |TDES/DES Engine Input Port + * | | |CPU feeds data to TDES/DES engine through this port by checking CRPT_TDES_STS + * | | |Feed data as INBUFFULL is 0. + * @var CRPT_T::TDES_DATOUT + * Offset: 0x238 TDES/DES Engine Output data Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATOUT |TDES/DES Engine Output Port + * | | |CPU gets result from the TDES/DES engine through this port by checking CRPT_TDES_STS + * | | |Get data as OUTBUFEMPTY is 0. + * @var CRPT_T::TDES1_KEY1H + * Offset: 0x248 TDES/DES Key 1 High Word Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 1 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES1_KEY1L + * Offset: 0x24C TDES/DES Key 1 Low Word Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 1 Low Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES1_KEY2H + * Offset: 0x250 TDES Key 2 High Word Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 2 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES1_KEY2L + * Offset: 0x254 TDES Key 2 Low Word Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 2 Low Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES1_KEY3H + * Offset: 0x258 TDES Key 3 High Word Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 3 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES1_KEY3L + * Offset: 0x25C TDES Key 3 Low Word Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 3 Low Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES1_IVH + * Offset: 0x260 TDES/DES Initial Vector High Word Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |TDES/DES Initial Vector High Word + * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode + * | | |IV is Nonce counter for TDES/DES engine in CTR mode. + * @var CRPT_T::TDES1_IVL + * Offset: 0x264 TDES/DES Initial Vector Low Word Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |TDES/DES Initial Vector Low Word + * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode + * | | |IV is Nonce counter for TDES/DES engine in CTR mode. + * @var CRPT_T::TDES1_SA + * Offset: 0x268 TDES/DES DMA Source Address Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |TDES/DES DMA Source Address + * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO + * | | |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored + * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation + * | | |The start of source address should be located at word boundary + * | | |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored. + * | | |CRPT_TDESn_SA can be read and written + * | | |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation + * | | |But the value of CRPT_TDESn_SA will be updated later on + * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation. + * | | |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START. + * | | |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value. + * @var CRPT_T::TDES1_DA + * Offset: 0x26C TDES/DES DMA Destination Address Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |TDES/DES DMA Destination Address + * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO + * | | |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored + * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished + * | | |The start of destination address should be located at word boundary + * | | |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored. + * | | |CRPT_TDESn_DA can be read and written + * | | |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation + * | | |But the value of CRPT_TDESn_DA will be updated later on + * | | |Consequently, software can prepare the destination address for the next TDES/DES operation. + * | | |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START. + * | | |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value. + * @var CRPT_T::TDES1_CNT + * Offset: 0x270 TDES/DES Byte Count Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |TDES/DES Byte Count + * | | |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode + * | | |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes. + * | | |CRPT_TDESn_CNT can be read and written + * | | |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation + * | | |But the value of CRPT_TDESn_CNT will be updated later on + * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation. + * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data. + * @var CRPT_T::TDES2_KEY1H + * Offset: 0x288 TDES/DES Key 1 High Word Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 1 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES2_KEY1L + * Offset: 0x28C TDES/DES Key 1 Low Word Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 1 Low Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES2_KEY2H + * Offset: 0x290 TDES Key 2 High Word Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 2 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES2_KEY2L + * Offset: 0x294 TDES Key 2 Low Word Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 2 Low Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES2_KEY3H + * Offset: 0x298 TDES Key 3 High Word Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 3 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES2_KEY3L + * Offset: 0x29C TDES Key 3 Low Word Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 3 Low Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES2_IVH + * Offset: 0x2A0 TDES/DES Initial Vector High Word Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |TDES/DES Initial Vector High Word + * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode + * | | |IV is Nonce counter for TDES/DES engine in CTR mode. + * @var CRPT_T::TDES2_IVL + * Offset: 0x2A4 TDES/DES Initial Vector Low Word Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |TDES/DES Initial Vector Low Word + * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode + * | | |IV is Nonce counter for TDES/DES engine in CTR mode. + * @var CRPT_T::TDES2_SA + * Offset: 0x2A8 TDES/DES DMA Source Address Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |TDES/DES DMA Source Address + * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO + * | | |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored + * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation + * | | |The start of source address should be located at word boundary + * | | |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored. + * | | |CRPT_TDESn_SA can be read and written + * | | |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation + * | | |But the value of CRPT_TDESn_SA will be updated later on + * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation. + * | | |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START. + * | | |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value. + * @var CRPT_T::TDES2_DA + * Offset: 0x2AC TDES/DES DMA Destination Address Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |TDES/DES DMA Destination Address + * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO + * | | |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored + * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished + * | | |The start of destination address should be located at word boundary + * | | |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored. + * | | |CRPT_TDESn_DA can be read and written + * | | |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation + * | | |But the value of CRPT_TDESn_DA will be updated later on + * | | |Consequently, software can prepare the destination address for the next TDES/DES operation. + * | | |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START. + * | | |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value. + * @var CRPT_T::TDES2_CNT + * Offset: 0x2B0 TDES/DES Byte Count Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |TDES/DES Byte Count + * | | |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode + * | | |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes. + * | | |CRPT_TDESn_CNT can be read and written + * | | |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation + * | | |But the value of CRPT_TDESn_CNT will be updated later on + * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation. + * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data. + * @var CRPT_T::TDES3_KEY1H + * Offset: 0x2C8 TDES/DES Key 1 High Word Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 1 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES3_KEY1L + * Offset: 0x2CC TDES/DES Key 1 Low Word Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 1 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES3_KEY2H + * Offset: 0x2D0 TDES Key 2 High Word Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 2 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES3_KEY2L + * Offset: 0x2D4 TDES Key 2 Low Word Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 2 Low Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES3_KEY3H + * Offset: 0x2D8 TDES Key 3 High Word Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 3 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES3_KEY3L + * Offset: 0x2DC TDES Key 3 Low Word Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 3 Low Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES3_IVH + * Offset: 0x2E0 TDES/DES Initial Vector High Word Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |TDES/DES Initial Vector High Word + * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode + * | | |IV is Nonce counter for TDES/DES engine in CTR mode. + * @var CRPT_T::TDES3_IVL + * Offset: 0x2E4 TDES/DES Initial Vector Low Word Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |TDES/DES Initial Vector Low Word + * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode + * | | |IV is Nonce counter for TDES/DES engine in CTR mode. + * @var CRPT_T::TDES3_SA + * Offset: 0x2E8 TDES/DES DMA Source Address Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |TDES/DES DMA Source Address + * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO + * | | |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored + * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation + * | | |The start of source address should be located at word boundary + * | | |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored. + * | | |CRPT_TDESn_SA can be read and written + * | | |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation + * | | |But the value of CRPT_TDESn_SA will be updated later on + * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation. + * | | |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START. + * | | |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value. + * @var CRPT_T::TDES3_DA + * Offset: 0x2EC TDES/DES DMA Destination Address Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |TDES/DES DMA Destination Address + * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO + * | | |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored + * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished + * | | |The start of destination address should be located at word boundary + * | | |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored. + * | | |CRPT_TDESn_DA can be read and written + * | | |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation + * | | |But the value of CRPT_TDESn_DA will be updated later on + * | | |Consequently, software can prepare the destination address for the next TDES/DES operation. + * | | |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START. + * | | |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value. + * @var CRPT_T::TDES3_CNT + * Offset: 0x2F0 TDES/DES Byte Count Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |TDES/DES Byte Count + * | | |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode + * | | |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes. + * | | |CRPT_TDESn_CNT can be read and written + * | | |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation + * | | |But the value of CRPT_TDESn_CNT will be updated later on + * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation. + * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data. + * @var CRPT_T::HMAC_CTL + * Offset: 0x300 SHA/HMAC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |SHA/HMAC Engine Start + * | | |0 = No effect. + * | | |1 = Start SHA/HMAC engine. BUSY flag will be set. + * | | |This bit is always 0 when it's read back. + * |[1] |STOP |SHA/HMAC Engine Stop + * | | |0 = No effect. + * | | |1 = Stop SHA/HMAC engine. + * | | |This bit is always 0 when it's read back. + * |[4] |HMACEN |HMAC_SHA Engine Operating Mode + * | | |0 = execute SHA function. + * | | |1 = execute HMAC function. + * |[5] |DMALAST |SHA/HMAC Last Block + * | | |This bit must be set as feeding in last byte of data. + * |[7] |DMAEN |SHA/HMAC Engine DMA Enable Control + * | | |0 = SHA/HMAC DMA engine Disabled. + * | | |SHA/HMAC engine operates in Non-DMA mode, and gets data from the port CRPT_HMAC_DATIN. + * | | |1 = SHA/HMAC DMA engine Enabled. + * | | |SHA/HMAC engine operates in DMA mode, and data movement from/to the engine is done by DMA logic. + * |[10:8] |OPMODE |SHA/HMAC Engine Operation Modes + * | | |0x0xx: SHA160 + * | | |0x100: SHA256 + * | | |0x101: SHA224 + * | | |0x110: SHA512 + * | | |0x111: SHA384 + * | | |These bits can be read and written. But writing to them wouldn't take effect as BUSY is 1. + * |[22] |OUTSWAP |SHA/HMAC Engine Output Data Swap + * | | |0 = Keep the original order. + * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[23] |INSWAP |SHA/HMAC Engine Input Data Swap + * | | |0 = Keep the original order. + * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * @var CRPT_T::HMAC_STS + * Offset: 0x304 SHA/HMAC Status Flag + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |SHA/HMAC Engine Busy + * | | |0 = SHA/HMAC engine is idle or finished. + * | | |1 = SHA/HMAC engine is busy. + * |[1] |DMABUSY |SHA/HMAC Engine DMA Busy Flag + * | | |0 = SHA/HMAC DMA engine is idle or finished. + * | | |1 = SHA/HMAC DMA engine is busy. + * |[8] |DMAERR |SHA/HMAC Engine DMA Error Flag + * | | |0 = Show the SHA/HMAC engine access normal. + * | | |1 = Show the SHA/HMAC engine access error. + * |[16] |DATINREQ |SHA/HMAC Non-DMA Mode Data Input Request + * | | |0 = No effect. + * | | |1 = Request SHA/HMAC Non-DMA mode data input. + * @var CRPT_T::HMAC_DGST[16] + * Offset: 0x308 ~ 0x344 SHA/HMAC Digest Message 0 ~ 15 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC Digest Message Output Register + * | | |For SHA-160, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST4. + * | | |For SHA-224, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST6. + * | | |For SHA-256, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST7. + * | | |For SHA-384, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST11. + * | | |For SHA-512, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST15. + * @var CRPT_T::HMAC_KEYCNT + * Offset: 0x348 SHA/HMAC Key Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEYCNT |SHA/HMAC Key Byte Count + * | | |The CRPT_HMAC_KEYCNT keeps the byte count of key that SHA/HMAC engine operates + * | | |The register is 32-bit and the maximum byte count is 4G bytes + * | | |It can be read and written. + * | | |Writing to the register CRPT_HMAC_KEYCNT as the SHA/HMAC accelerator operating doesn't affect the current SHA/HMAC operation + * | | |But the value of CRPT_SHA _KEYCNT will be updated later on + * | | |Consequently, software can prepare the key count for the next SHA/HMAC operation. + * @var CRPT_T::HMAC_SADDR + * Offset: 0x34C SHA/HMAC DMA Source Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |SHA/HMAC DMA Source Address + * | | |The SHA/HMAC accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO + * | | |The CRPT_HMAC_SADDR keeps the source address of the data buffer where the source text is stored + * | | |Based on the source address, the SHA/HMAC accelerator can read the plain text from system memory and do SHA/HMAC operation + * | | |The start of source address should be located at word boundary + * | | |In other words, bit 1 and 0 of CRPT_HMAC_SADDR are ignored. + * | | |CRPT_HMAC_SADDR can be read and written + * | | |Writing to CRPT_HMAC_SADDR while the SHA/HMAC accelerator is operating doesn't affect the current SHA/HMAC operation + * | | |But the value of CRPT_HMAC_SADDR will be updated later on + * | | |Consequently, software can prepare the DMA source address for the next SHA/HMAC operation. + * | | |In DMA mode, software can update the next CRPT_HMAC_SADDR before triggering START. + * | | |CRPT_HMAC_SADDR and CRPT_HMAC_DADDR can be the same in the value. + * @var CRPT_T::HMAC_DMACNT + * Offset: 0x350 SHA/HMAC Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DMACNT |SHA/HMAC Operation Byte Count + * | | |The CRPT_HMAC_DMACNT keeps the byte count of source text that is for the SHA/HMAC engine operating in DMA mode + * | | |The CRPT_HMAC_DMACNT is 32-bit and the maximum of byte count is 4G bytes. + * | | |CRPT_HMAC_DMACNT can be read and written + * | | |Writing to CRPT_HMAC_DMACNT while the SHA/HMAC accelerator is operating doesn't affect the current SHA/HMAC operation + * | | |But the value of CRPT_HMAC_DMACNT will be updated later on + * | | |Consequently, software can prepare the byte count of data for the next SHA/HMAC operation. + * | | |In Non-DMA mode, CRPT_HMAC_DMACNT must be set as the byte count of the last block before feeding in the last block of data. + * @var CRPT_T::HMAC_DATIN + * Offset: 0x354 SHA/HMAC Engine Non-DMA Mode Data Input Port Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATIN |SHA/HMAC Engine Input Port + * | | |CPU feeds data to SHA/HMAC engine through this port by checking CRPT_HMAC_STS + * | | |Feed data as DATINREQ is 1. + * @var CRPT_T::ECC_CTL + * Offset: 0x800 ECC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |ECC Accelerator Start + * | | |0 = No effect. + * | | |1 = Start ECC accelerator. BUSY flag will be set. + * | | |This bit is always 0 when it's read back. + * | | |ECC accelerator will ignore this START signal when BUSY flag is 1. + * |[1] |STOP |ECC Accelerator Stop + * | | |0 = No effect. + * | | |1 = Abort ECC accelerator and make it into idle state. + * | | |This bit is always 0 when it's read back. + * | | |Remember to clear ECC interrupt flag after stopping ECC accelerator. + * |[7] |DMAEN |ECC Accelerator DMA Enable Control + * | | |0 = ECC DMA engine Disabled. + * | | |1 = ECC DMA engine Enabled. + * | | |Only when START and DMAEN are 1, ECC DMA engine will be active + * |[8] |FSEL |Field Selection + * | | |0 = Binary Field (GF(2^m)). + * | | |1 = Prime Field (GF(p)). + * |[10:9] |ECCOP |Point Operation for BF and PF + * | | |00 = Point multiplication :. + * | | |(POINTX1, POINTY1) = SCALARK * (POINTX1, POINTY1). + * | | |01 = Modulus operation : choose by MODOP (CRPT_ECC_CTL[12:11]). + * | | |10 = Point addition :. + * | | |(POINTX1, POINTY1) = (POINTX1, POINTY1) +. + * | | |(POINTX2, POINTY2) + * | | |11 = Point doubling :. + * | | |(POINTX1, POINTY1) = 2 * (POINTX1, POINTY1). + * | | |Besides above three input data, point operations still need the parameters of elliptic curve (CURVEA, CURVEB, CURVEN and CURVEM) as shown in Figure 6.27-11 + * |[12:11] |MODOP |Modulus Operation for PF + * | | |00 = Division :. + * | | |POINTX1 = (POINTY1 / POINTX1) % CURVEN. + * | | |01 = Multiplication :. + * | | |POINTX1 = (POINTX1 * POINTY1) % CURVEN. + * | | |10 = Addition :. + * | | |POINTX1 = (POINTX1 + POINTY1) % CURVEN. + * | | |11 = Subtraction :. + * | | |POINTX1 = (POINTX1 - POINTY1) % CURVEN. + * | | |MODOP is active only when ECCOP = 01. + * |[16] |LDP1 |The Control Signal of Register for the X and Y Coordinate of the First Point (POINTX1, POINTY1) + * | | |0 = The register for POINTX1 and POINTY1 is not modified by DMA or user. + * | | |1 = The register for POINTX1 and POINTY1 is modified by DMA or user. + * |[17] |LDP2 |The Control Signal of Register for the X and Y Coordinate of the Second Point (POINTX2, POINTY2) + * | | |0 = The register for POINTX2 and POINTY2 is not modified by DMA or user. + * | | |1 = The register for POINTX2 and POINTY2 is modified by DMA or user. + * |[18] |LDA |The Control Signal of Register for the Parameter CURVEA of Elliptic Curve + * | | |0 = The register for CURVEA is not modified by DMA or user. + * | | |1 = The register for CURVEA is modified by DMA or user. + * |[19] |LDB |The Control Signal of Register for the Parameter CURVEB of Elliptic Curve + * | | |0 = The register for CURVEB is not modified by DMA or user. + * | | |1 = The register for CURVEB is modified by DMA or user. + * |[20] |LDN |The Control Signal of Register for the Parameter CURVEN of Elliptic Curve + * | | |0 = The register for CURVEN is not modified by DMA or user. + * | | |1 = The register for CURVEN is modified by DMA or user. + * |[21] |LDK |The Control Signal of Register for SCALARK + * | | |0 = The register for SCALARK is not modified by DMA or user. + * | | |1 = The register for SCALARK is modified by DMA or user. + * |[31:22] |CURVEM |The key length of elliptic curve. + * @var CRPT_T::ECC_STS + * Offset: 0x804 ECC Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |ECC Accelerator Busy Flag + * | | |0 = The ECC accelerator is idle or finished. + * | | |1 = The ECC accelerator is under processing and protects all registers. + * | | |Remember to clear ECC interrupt flag after ECC accelerator finished + * |[1] |DMABUSY |ECC DMA Busy Flag + * | | |0 = ECC DMA is idle or finished. + * | | |1 = ECC DMA is busy. + * |[16] |BUSERR |ECC DMA Access Bus Error Flag + * | | |0 = No error. + * | | |1 = Bus error will stop DMA operation and ECC accelerator. + * @var CRPT_T::ECC_X1[18] + * Offset: 0x808 ~ 0x84C ECC The X-coordinate word 0 ~ 17 of the first point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the x-coordinate Value of the First Point (POINTX1) + * | | |For B-163 or K-163, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_06 + * | | |For P-256, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_16 + * @var CRPT_T::ECC_Y1[18] + * Offset: 0x850 ~ 0x894 ECC The Y-coordinate word 0 ~ 17 of the first point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point (POINTY1) + * | | |For B-163 or K-163, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_06 + * | | |For P-256, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_16 + * @var CRPT_T::ECC_X2[18] + * Offset: 0x898 ~ 0x8DC ECC The X-coordinate word 0 ~ 17 of the second point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the x-coordinate Value of the Second Point (POINTX2) + * | | |For B-163 or K-163, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_06 + * | | |For P-256, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_16 + * @var CRPT_T::ECC_Y2[18] + * Offset: 0x8E0 ~ 0x924 ECC The Y-coordinate word 0 ~ 17 of the second point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point (POINTY2) + * | | |For B-163 or K-163, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_06 + * | | |For P-256, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_16 + * @var CRPT_T::ECC_A[18] + * Offset: 0x928 ~ 0x96C ECC The parameter CURVEA word 0 ~ 17 of elliptic curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA) + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2^m). + * | | |For B-163 or K-163, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_06 + * | | |For P-256, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_16 + * @var CRPT_T::ECC_B[18] + * Offset: 0x970 ~ 0x9B4 ECC The parameter CURVEB word 0 ~ 17 of elliptic curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA) + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2^m). + * | | |For B-163 or K-163, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_06 + * | | |For P-256, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_16 + * @var CRPT_T::ECC_N[18] + * Offset: 0x9B8 ~ 0x9FC ECC The parameter CURVEN word 0 ~ 17 of elliptic curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN) + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2^m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_06 + * | | |For P-256, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_16 + * @var CRPT_T::ECC_K[18] + * Offset: 0xA00 ~ 0xA44 ECC The scalar SCALARK word0 of point multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication(SCALARK) + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_06 + * | | |For P-256, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_16 + * @var CRPT_T::ECC_SADDR + * Offset: 0xA48 ECC DMA Source Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |ECC DMA Source Address + * | | |The ECC accelerator supports DMA function to transfer the DATA and PARAMETER between + * | | |SRAM memory space and ECC accelerator. The SADDR keeps the source address of the data + * | | |buffer where the source text is stored. Based on the source address, the ECC accelerator + * | | |can read the DATA and PARAMETER from SRAM memory space and do ECC operation. The start + * | | |of source address should be located at word boundary. That is, bit 1 and 0 of SADDR are + * | | |ignored. SADDR can be read and written. In DMA mode, software must update the CRPT_ECC_SADDR + * | | |before triggering START. + * @var CRPT_T::ECC_DADDR + * Offset: 0xA4C ECC DMA Destination Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |ECC DMA Destination Address + * | | |The ECC accelerator supports DMA function to transfer the DATA and PARAMETER between system memory and ECC accelerator + * | | |The DADDR keeps the destination address of the data buffer where output data of ECC engine will be stored + * | | |Based on the destination address, the ECC accelerator can write the result data back to system memory after the ECC operation is finished + * | | |The start of destination address should be located at word boundary + * | | |That is, bit 1 and 0 of DADDR are ignored + * | | |DADDR can be read and written + * | | |In DMA mode, software must update the CRPT_ECC_DADDR before triggering START + * @var CRPT_T::ECC_STARTREG + * Offset: 0xA50 ECC Starting Address of Updated Registers + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |STARTREG |ECC Starting Address of Updated Registers + * | | |The address of the updated registers that DMA feeds the first data or parameter to ECC engine + * | | |When ECC engine is active, ECC accelerator does not allow users to modify STARTREG + * | | |For example, we want to updated input data from register CRPT_ECC POINTX1 + * | | |Thus, the value of STARTREG is 0x808. + * @var CRPT_T::ECC_WORDCNT + * Offset: 0xA54 ECC DMA Word Count + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |WORDCNT |ECC DMA Word Count + * | | |The CRPT_ECC_WORDCNT keeps the word count of source data that is for the required input data of ECC accelerator with various operations in DMA mode + * | | |Although CRPT_ECC_WORDCNT is 32-bit, the maximum of word count in ECC accelerator is 144 words + * | | |CRPT_ECC_WORDCNT can be read and written + */ + __IO uint32_t INTEN; /*!< [0x0000] Crypto Interrupt Enable Control Register */ + __IO uint32_t INTSTS; /*!< [0x0004] Crypto Interrupt Flag */ + __IO uint32_t PRNG_CTL; /*!< [0x0008] PRNG Control Register */ + __O uint32_t PRNG_SEED; /*!< [0x000c] Seed for PRNG */ + __I uint32_t PRNG_KEY[8]; /*!< [0x0010] ~ [0x002c] PRNG Generated Key0 ~ Key7 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[8]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t AES_FDBCK[4]; /*!< [0x0050] ~ [0x005c] AES Engine Output Feedback Data after Cryptographic Operation */ + __I uint32_t TDES_FDBCKH; /*!< [0x0060] TDES/DES Engine Output Feedback High Word Data after Cryptographic Operation */ + __I uint32_t TDES_FDBCKL; /*!< [0x0064] TDES/DES Engine Output Feedback Low Word Data after Cryptographic Operation */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[38]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t AES_CTL; /*!< [0x0100] AES Control Register */ + __I uint32_t AES_STS; /*!< [0x0104] AES Engine Flag */ + __IO uint32_t AES_DATIN; /*!< [0x0108] AES Engine Data Input Port Register */ + __I uint32_t AES_DATOUT; /*!< [0x010c] AES Engine Data Output Port Register */ + __IO uint32_t AES0_KEY[8]; /*!< [0x0110] ~ [0x012c] AES Key Word 0~7 Register for Channel 0 */ + __IO uint32_t AES0_IV[4]; /*!< [0x0130] ~ [0x013c] AES Initial Vector Word 0 ~ 3 Register for Channel 0 */ + __IO uint32_t AES0_SADDR; /*!< [0x0140] AES DMA Source Address Register for Channel 0 */ + __IO uint32_t AES0_DADDR; /*!< [0x0144] AES DMA Destination Address Register for Channel 0 */ + __IO uint32_t AES0_CNT; /*!< [0x0148] AES Byte Count Register for Channel 0 */ + __IO uint32_t AES1_KEY[8]; /*!< [0x014c] ~ [0x0168] AES Key Word 0~7 Register for Channel 1 */ + __IO uint32_t AES1_IV[4]; /*!< [0x016c] ~ [0x0178] AES Initial Vector Word 0~3 Register for Channel 1 */ + __IO uint32_t AES1_SADDR; /*!< [0x017c] AES DMA Source Address Register for Channel 1 */ + __IO uint32_t AES1_DADDR; /*!< [0x0180] AES DMA Destination Address Register for Channel 1 */ + __IO uint32_t AES1_CNT; /*!< [0x0184] AES Byte Count Register for Channel 1 */ + __IO uint32_t AES2_KEY[8]; /*!< [0x0188] ~ [0x01a4] AES Key Word 0~7 Register for Channel 2 */ + __IO uint32_t AES2_IV[4]; /*!< [0x01a8] ~ [0x01b4] AES Initial Vector Word 0~3 Register for Channel 2 */ + __IO uint32_t AES2_SADDR; /*!< [0x01b8] AES DMA Source Address Register for Channel 2 */ + __IO uint32_t AES2_DADDR; /*!< [0x01bc] AES DMA Destination Address Register for Channel 2 */ + __IO uint32_t AES2_CNT; /*!< [0x01c0] AES Byte Count Register for Channel 2 */ + __IO uint32_t AES3_KEY[8]; /*!< [0x01c4] ~ [0x01e0] AES Key Word 0~7 Register for Channel 3 */ + __IO uint32_t AES3_IV[4]; /*!< [0x01e4] ~ [0x01f0] AES Initial Vector Word 0~3 Register for Channel 3 */ + __IO uint32_t AES3_SADDR; /*!< [0x01f4] AES DMA Source Address Register for Channel 3 */ + __IO uint32_t AES3_DADDR; /*!< [0x01f8] AES DMA Destination Address Register for Channel 3 */ + __IO uint32_t AES3_CNT; /*!< [0x01fc] AES Byte Count Register for Channel 3 */ + __IO uint32_t TDES_CTL; /*!< [0x0200] TDES/DES Control Register */ + __I uint32_t TDES_STS; /*!< [0x0204] TDES/DES Engine Flag */ + __IO uint32_t TDES0_KEY1H; /*!< [0x0208] TDES/DES Key 1 High Word Register for Channel 0 */ + __IO uint32_t TDES0_KEY1L; /*!< [0x020c] TDES/DES Key 1 Low Word Register for Channel 0 */ + __IO uint32_t TDES0_KEY2H; /*!< [0x0210] TDES Key 2 High Word Register for Channel 0 */ + __IO uint32_t TDES0_KEY2L; /*!< [0x0214] TDES Key 2 Low Word Register for Channel 0 */ + __IO uint32_t TDES0_KEY3H; /*!< [0x0218] TDES Key 3 High Word Register for Channel 0 */ + __IO uint32_t TDES0_KEY3L; /*!< [0x021c] TDES Key 3 Low Word Register for Channel 0 */ + __IO uint32_t TDES0_IVH; /*!< [0x0220] TDES/DES Initial Vector High Word Register for Channel 0 */ + __IO uint32_t TDES0_IVL; /*!< [0x0224] TDES/DES Initial Vector Low Word Register for Channel 0 */ + __IO uint32_t TDES0_SA; /*!< [0x0228] TDES/DES DMA Source Address Register for Channel 0 */ + __IO uint32_t TDES0_DA; /*!< [0x022c] TDES/DES DMA Destination Address Register for Channel 0 */ + __IO uint32_t TDES0_CNT; /*!< [0x0230] TDES/DES Byte Count Register for Channel 0 */ + __IO uint32_t TDES_DATIN; /*!< [0x0234] TDES/DES Engine Input data Word Register */ + __I uint32_t TDES_DATOUT; /*!< [0x0238] TDES/DES Engine Output data Word Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[3]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t TDES1_KEY1H; /*!< [0x0248] TDES/DES Key 1 High Word Register for Channel 1 */ + __IO uint32_t TDES1_KEY1L; /*!< [0x024c] TDES/DES Key 1 Low Word Register for Channel 1 */ + __IO uint32_t TDES1_KEY2H; /*!< [0x0250] TDES Key 2 High Word Register for Channel 1 */ + __IO uint32_t TDES1_KEY2L; /*!< [0x0254] TDES Key 2 Low Word Register for Channel 1 */ + __IO uint32_t TDES1_KEY3H; /*!< [0x0258] TDES Key 3 High Word Register for Channel 1 */ + __IO uint32_t TDES1_KEY3L; /*!< [0x025c] TDES Key 3 Low Word Register for Channel 1 */ + __IO uint32_t TDES1_IVH; /*!< [0x0260] TDES/DES Initial Vector High Word Register for Channel 1 */ + __IO uint32_t TDES1_IVL; /*!< [0x0264] TDES/DES Initial Vector Low Word Register for Channel 1 */ + __IO uint32_t TDES1_SA; /*!< [0x0268] TDES/DES DMA Source Address Register for Channel 1 */ + __IO uint32_t TDES1_DA; /*!< [0x026c] TDES/DES DMA Destination Address Register for Channel 1 */ + __IO uint32_t TDES1_CNT; /*!< [0x0270] TDES/DES Byte Count Register for Channel 1 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[5]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t TDES2_KEY1H; /*!< [0x0288] TDES/DES Key 1 High Word Register for Channel 2 */ + __IO uint32_t TDES2_KEY1L; /*!< [0x028c] TDES/DES Key 1 Low Word Register for Channel 2 */ + __IO uint32_t TDES2_KEY2H; /*!< [0x0290] TDES Key 2 High Word Register for Channel 2 */ + __IO uint32_t TDES2_KEY2L; /*!< [0x0294] TDES Key 2 Low Word Register for Channel 2 */ + __IO uint32_t TDES2_KEY3H; /*!< [0x0298] TDES Key 3 High Word Register for Channel 2 */ + __IO uint32_t TDES2_KEY3L; /*!< [0x029c] TDES Key 3 Low Word Register for Channel 2 */ + __IO uint32_t TDES2_IVH; /*!< [0x02a0] TDES/DES Initial Vector High Word Register for Channel 2 */ + __IO uint32_t TDES2_IVL; /*!< [0x02a4] TDES/DES Initial Vector Low Word Register for Channel 2 */ + __IO uint32_t TDES2_SA; /*!< [0x02a8] TDES/DES DMA Source Address Register for Channel 2 */ + __IO uint32_t TDES2_DA; /*!< [0x02ac] TDES/DES DMA Destination Address Register for Channel 2 */ + __IO uint32_t TDES2_CNT; /*!< [0x02b0] TDES/DES Byte Count Register for Channel 2 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE4[5]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t TDES3_KEY1H; /*!< [0x02c8] TDES/DES Key 1 High Word Register for Channel 3 */ + __IO uint32_t TDES3_KEY1L; /*!< [0x02cc] TDES/DES Key 1 Low Word Register for Channel 3 */ + __IO uint32_t TDES3_KEY2H; /*!< [0x02d0] TDES Key 2 High Word Register for Channel 3 */ + __IO uint32_t TDES3_KEY2L; /*!< [0x02d4] TDES Key 2 Low Word Register for Channel 3 */ + __IO uint32_t TDES3_KEY3H; /*!< [0x02d8] TDES Key 3 High Word Register for Channel 3 */ + __IO uint32_t TDES3_KEY3L; /*!< [0x02dc] TDES Key 3 Low Word Register for Channel 3 */ + __IO uint32_t TDES3_IVH; /*!< [0x02e0] TDES/DES Initial Vector High Word Register for Channel 3 */ + __IO uint32_t TDES3_IVL; /*!< [0x02e4] TDES/DES Initial Vector Low Word Register for Channel 3 */ + __IO uint32_t TDES3_SA; /*!< [0x02e8] TDES/DES DMA Source Address Register for Channel 3 */ + __IO uint32_t TDES3_DA; /*!< [0x02ec] TDES/DES DMA Destination Address Register for Channel 3 */ + __IO uint32_t TDES3_CNT; /*!< [0x02f0] TDES/DES Byte Count Register for Channel 3 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE5[3]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t HMAC_CTL; /*!< [0x0300] SHA/HMAC Control Register */ + __I uint32_t HMAC_STS; /*!< [0x0304] SHA/HMAC Status Flag */ + __I uint32_t HMAC_DGST[16]; /*!< [0x0308] ~ [0x0344] SHA/HMAC Digest Message 0~15 */ + __IO uint32_t HMAC_KEYCNT; /*!< [0x0348] SHA/HMAC Key Byte Count Register */ + __IO uint32_t HMAC_SADDR; /*!< [0x034c] SHA/HMAC DMA Source Address Register */ + __IO uint32_t HMAC_DMACNT; /*!< [0x0350] SHA/HMAC Byte Count Register */ + __IO uint32_t HMAC_DATIN; /*!< [0x0354] SHA/HMAC Engine Non-DMA Mode Data Input Port Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE6[298]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t ECC_CTL; /*!< [0x0800] ECC Control Register */ + __I uint32_t ECC_STS; /*!< [0x0804] ECC Status Register */ + __IO uint32_t ECC_X1[18]; /*!< [0x0808] ~ [0x084c] ECC The X-coordinate word 0~17 of the first point */ + __IO uint32_t ECC_Y1[18]; /*!< [0x0850] ~ [0x0894] ECC The Y-coordinate word 0~17 of the first point */ + __IO uint32_t ECC_X2[18]; /*!< [0x0898] ~ [0x08dc] ECC The X-coordinate word 0~17 of the second point */ + __IO uint32_t ECC_Y2[18]; /*!< [0x08e0] ~ [0x0924] ECC The Y-coordinate word 0~17 of the second point */ + __IO uint32_t ECC_A[18]; /*!< [0x0928] ~ [0x096c] ECC The parameter CURVEA word 0~17 of elliptic curve */ + __IO uint32_t ECC_B[18]; /*!< [0x0970] ~ [0x09b4] ECC The parameter CURVEB word 0~17 of elliptic curve */ + __IO uint32_t ECC_N[18]; /*!< [0x09b8] ~ [0x09fc] ECC The parameter CURVEN word 0~17 of elliptic curve */ + __O uint32_t ECC_K[18]; /*!< [0x0a00] ~ [0x0a44] ECC The scalar SCALARK word 0~17 of point multiplication */ + __IO uint32_t ECC_SADDR; /*!< [0x0a48] ECC DMA Source Address Register */ + __IO uint32_t ECC_DADDR; /*!< [0x0a4c] ECC DMA Destination Address Register */ + __IO uint32_t ECC_STARTREG; /*!< [0x0a50] ECC Starting Address of Updated Registers */ + __IO uint32_t ECC_WORDCNT; /*!< [0x0a54] ECC DMA Word Count */ + +} CRPT_T; + +/** + @addtogroup CRPT_CONST CRPT Bit Field Definition + Constant Definitions for CRPT Controller +@{ */ + +#define CRPT_INTEN_AESIEN_Pos (0) /*!< CRPT_T::INTEN: AESIEN Position */ +#define CRPT_INTEN_AESIEN_Msk (0x1ul << CRPT_INTEN_AESIEN_Pos) /*!< CRPT_T::INTEN: AESIEN Mask */ + +#define CRPT_INTEN_AESEIEN_Pos (1) /*!< CRPT_T::INTEN: AESEIEN Position */ +#define CRPT_INTEN_AESEIEN_Msk (0x1ul << CRPT_INTEN_AESEIEN_Pos) /*!< CRPT_T::INTEN: AESEIEN Mask */ + +#define CRPT_INTEN_TDESIEN_Pos (8) /*!< CRPT_T::INTEN: TDESIEN Position */ +#define CRPT_INTEN_TDESIEN_Msk (0x1ul << CRPT_INTEN_TDESIEN_Pos) /*!< CRPT_T::INTEN: TDESIEN Mask */ + +#define CRPT_INTEN_TDESEIEN_Pos (9) /*!< CRPT_T::INTEN: TDESEIEN Position */ +#define CRPT_INTEN_TDESEIEN_Msk (0x1ul << CRPT_INTEN_TDESEIEN_Pos) /*!< CRPT_T::INTEN: TDESEIEN Mask */ + +#define CRPT_INTEN_PRNGIEN_Pos (16) /*!< CRPT_T::INTEN: PRNGIEN Position */ +#define CRPT_INTEN_PRNGIEN_Msk (0x1ul << CRPT_INTEN_PRNGIEN_Pos) /*!< CRPT_T::INTEN: PRNGIEN Mask */ + +#define CRPT_INTEN_ECCIEN_Pos (22) /*!< CRPT_T::INTEN: ECCIEN Position */ +#define CRPT_INTEN_ECCIEN_Msk (0x1ul << CRPT_INTEN_ECCIEN_Pos) /*!< CRPT_T::INTEN: ECCIEN Mask */ + +#define CRPT_INTEN_ECCEIEN_Pos (23) /*!< CRPT_T::INTEN: ECCEIEN Position */ +#define CRPT_INTEN_ECCEIEN_Msk (0x1ul << CRPT_INTEN_ECCEIEN_Pos) /*!< CRPT_T::INTEN: ECCEIEN Mask */ + +#define CRPT_INTEN_HMACIEN_Pos (24) /*!< CRPT_T::INTEN: HMACIEN Position */ +#define CRPT_INTEN_HMACIEN_Msk (0x1ul << CRPT_INTEN_HMACIEN_Pos) /*!< CRPT_T::INTEN: HMACIEN Mask */ + +#define CRPT_INTEN_HMACEIEN_Pos (25) /*!< CRPT_T::INTEN: HMACEIEN Position */ +#define CRPT_INTEN_HMACEIEN_Msk (0x1ul << CRPT_INTEN_HMACEIEN_Pos) /*!< CRPT_T::INTEN: HMACEIEN Mask */ + +#define CRPT_INTSTS_AESIF_Pos (0) /*!< CRPT_T::INTSTS: AESIF Position */ +#define CRPT_INTSTS_AESIF_Msk (0x1ul << CRPT_INTSTS_AESIF_Pos) /*!< CRPT_T::INTSTS: AESIF Mask */ + +#define CRPT_INTSTS_AESEIF_Pos (1) /*!< CRPT_T::INTSTS: AESEIF Position */ +#define CRPT_INTSTS_AESEIF_Msk (0x1ul << CRPT_INTSTS_AESEIF_Pos) /*!< CRPT_T::INTSTS: AESEIF Mask */ + +#define CRPT_INTSTS_TDESIF_Pos (8) /*!< CRPT_T::INTSTS: TDESIF Position */ +#define CRPT_INTSTS_TDESIF_Msk (0x1ul << CRPT_INTSTS_TDESIF_Pos) /*!< CRPT_T::INTSTS: TDESIF Mask */ + +#define CRPT_INTSTS_TDESEIF_Pos (9) /*!< CRPT_T::INTSTS: TDESEIF Position */ +#define CRPT_INTSTS_TDESEIF_Msk (0x1ul << CRPT_INTSTS_TDESEIF_Pos) /*!< CRPT_T::INTSTS: TDESEIF Mask */ + +#define CRPT_INTSTS_PRNGIF_Pos (16) /*!< CRPT_T::INTSTS: PRNGIF Position */ +#define CRPT_INTSTS_PRNGIF_Msk (0x1ul << CRPT_INTSTS_PRNGIF_Pos) /*!< CRPT_T::INTSTS: PRNGIF Mask */ + +#define CRPT_INTSTS_ECCIF_Pos (22) /*!< CRPT_T::INTSTS: ECCIF Position */ +#define CRPT_INTSTS_ECCIF_Msk (0x1ul << CRPT_INTSTS_ECCIF_Pos) /*!< CRPT_T::INTSTS: ECCIF Mask */ + +#define CRPT_INTSTS_ECCEIF_Pos (23) /*!< CRPT_T::INTSTS: ECCEIF Position */ +#define CRPT_INTSTS_ECCEIF_Msk (0x1ul << CRPT_INTSTS_ECCEIF_Pos) /*!< CRPT_T::INTSTS: ECCEIF Mask */ + +#define CRPT_INTSTS_HMACIF_Pos (24) /*!< CRPT_T::INTSTS: HMACIF Position */ +#define CRPT_INTSTS_HMACIF_Msk (0x1ul << CRPT_INTSTS_HMACIF_Pos) /*!< CRPT_T::INTSTS: HMACIF Mask */ + +#define CRPT_INTSTS_HMACEIF_Pos (25) /*!< CRPT_T::INTSTS: HMACEIF Position */ +#define CRPT_INTSTS_HMACEIF_Msk (0x1ul << CRPT_INTSTS_HMACEIF_Pos) /*!< CRPT_T::INTSTS: HMACEIF Mask */ + +#define CRPT_PRNG_CTL_START_Pos (0) /*!< CRPT_T::PRNG_CTL: START Position */ +#define CRPT_PRNG_CTL_START_Msk (0x1ul << CRPT_PRNG_CTL_START_Pos) /*!< CRPT_T::PRNG_CTL: START Mask */ + +#define CRPT_PRNG_CTL_SEEDRLD_Pos (1) /*!< CRPT_T::PRNG_CTL: SEEDRLD Position */ +#define CRPT_PRNG_CTL_SEEDRLD_Msk (0x1ul << CRPT_PRNG_CTL_SEEDRLD_Pos) /*!< CRPT_T::PRNG_CTL: SEEDRLD Mask */ + +#define CRPT_PRNG_CTL_KEYSZ_Pos (2) /*!< CRPT_T::PRNG_CTL: KEYSZ Position */ +#define CRPT_PRNG_CTL_KEYSZ_Msk (0x3ul << CRPT_PRNG_CTL_KEYSZ_Pos) /*!< CRPT_T::PRNG_CTL: KEYSZ Mask */ + +#define CRPT_PRNG_CTL_BUSY_Pos (8) /*!< CRPT_T::PRNG_CTL: BUSY Position */ +#define CRPT_PRNG_CTL_BUSY_Msk (0x1ul << CRPT_PRNG_CTL_BUSY_Pos) /*!< CRPT_T::PRNG_CTL: BUSY Mask */ + +#define CRPT_PRNG_SEED_SEED_Pos (0) /*!< CRPT_T::PRNG_SEED: SEED Position */ +#define CRPT_PRNG_SEED_SEED_Msk (0xfffffffful << CRPT_PRNG_SEED_SEED_Pos) /*!< CRPT_T::PRNG_SEED: SEED Mask */ + +#define CRPT_PRNG_KEYx_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY[8]: KEY Position */ +#define CRPT_PRNG_KEYx_KEY_Msk (0xfffffffful << CRPT_PRNG_KEYx_KEY_Pos) /*!< CRPT_T::PRNG_KEY[8]: KEY Mask */ + +#define CRPT_AES_FDBCKx_FDBCK_Pos (0) /*!< CRPT_T::AES_FDBCK[4]: FDBCK Position */ +#define CRPT_AES_FDBCKx_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCKx_FDBCK_Pos) /*!< CRPT_T::AES_FDBCK[4]: FDBCK Mask */ + +#define CRPT_TDES_FDBCKH_FDBCK_Pos (0) /*!< CRPT_T::TDES_FDBCKH: FDBCK Position */ +#define CRPT_TDES_FDBCKH_FDBCK_Msk (0xfffffffful << CRPT_TDES_FDBCKH_FDBCK_Pos) /*!< CRPT_T::TDES_FDBCKH: FDBCK Mask */ + +#define CRPT_TDES_FDBCKL_FDBCK_Pos (0) /*!< CRPT_T::TDES_FDBCKL: FDBCK Position */ +#define CRPT_TDES_FDBCKL_FDBCK_Msk (0xfffffffful << CRPT_TDES_FDBCKL_FDBCK_Pos) /*!< CRPT_T::TDES_FDBCKL: FDBCK Mask */ + +#define CRPT_AES_CTL_START_Pos (0) /*!< CRPT_T::AES_CTL: START Position */ +#define CRPT_AES_CTL_START_Msk (0x1ul << CRPT_AES_CTL_START_Pos) /*!< CRPT_T::AES_CTL: START Mask */ + +#define CRPT_AES_CTL_STOP_Pos (1) /*!< CRPT_T::AES_CTL: STOP Position */ +#define CRPT_AES_CTL_STOP_Msk (0x1ul << CRPT_AES_CTL_STOP_Pos) /*!< CRPT_T::AES_CTL: STOP Mask */ + +#define CRPT_AES_CTL_KEYSZ_Pos (2) /*!< CRPT_T::AES_CTL: KEYSZ Position */ +#define CRPT_AES_CTL_KEYSZ_Msk (0x3ul << CRPT_AES_CTL_KEYSZ_Pos) /*!< CRPT_T::AES_CTL: KEYSZ Mask */ + +#define CRPT_AES_CTL_DMALAST_Pos (5) /*!< CRPT_T::AES_CTL: DMALAST Position */ +#define CRPT_AES_CTL_DMALAST_Msk (0x1ul << CRPT_AES_CTL_DMALAST_Pos) /*!< CRPT_T::AES_CTL: DMALAST Mask */ + +#define CRPT_AES_CTL_DMACSCAD_Pos (6) /*!< CRPT_T::AES_CTL: DMACSCAD Position */ +#define CRPT_AES_CTL_DMACSCAD_Msk (0x1ul << CRPT_AES_CTL_DMACSCAD_Pos) /*!< CRPT_T::AES_CTL: DMACSCAD Mask */ + +#define CRPT_AES_CTL_DMAEN_Pos (7) /*!< CRPT_T::AES_CTL: DMAEN Position */ +#define CRPT_AES_CTL_DMAEN_Msk (0x1ul << CRPT_AES_CTL_DMAEN_Pos) /*!< CRPT_T::AES_CTL: DMAEN Mask */ + +#define CRPT_AES_CTL_OPMODE_Pos (8) /*!< CRPT_T::AES_CTL: OPMODE Position */ +#define CRPT_AES_CTL_OPMODE_Msk (0xfful << CRPT_AES_CTL_OPMODE_Pos) /*!< CRPT_T::AES_CTL: OPMODE Mask */ + +#define CRPT_AES_CTL_ENCRPT_Pos (16) /*!< CRPT_T::AES_CTL: ENCRPT Position */ +#define CRPT_AES_CTL_ENCRPT_Msk (0x1ul << CRPT_AES_CTL_ENCRPT_Pos) /*!< CRPT_T::AES_CTL: ENCRPT Mask */ + +#define CRPT_AES_CTL_OUTSWAP_Pos (22) /*!< CRPT_T::AES_CTL: OUTSWAP Position */ +#define CRPT_AES_CTL_OUTSWAP_Msk (0x1ul << CRPT_AES_CTL_OUTSWAP_Pos) /*!< CRPT_T::AES_CTL: OUTSWAP Mask */ + +#define CRPT_AES_CTL_INSWAP_Pos (23) /*!< CRPT_T::AES_CTL: INSWAP Position */ +#define CRPT_AES_CTL_INSWAP_Msk (0x1ul << CRPT_AES_CTL_INSWAP_Pos) /*!< CRPT_T::AES_CTL: INSWAP Mask */ + +#define CRPT_AES_CTL_CHANNEL_Pos (24) /*!< CRPT_T::AES_CTL: CHANNEL Position */ +#define CRPT_AES_CTL_CHANNEL_Msk (0x3ul << CRPT_AES_CTL_CHANNEL_Pos) /*!< CRPT_T::AES_CTL: CHANNEL Mask */ + +#define CRPT_AES_CTL_KEYUNPRT_Pos (26) /*!< CRPT_T::AES_CTL: KEYUNPRT Position */ +#define CRPT_AES_CTL_KEYUNPRT_Msk (0x1ful << CRPT_AES_CTL_KEYUNPRT_Pos) /*!< CRPT_T::AES_CTL: KEYUNPRT Mask */ + +#define CRPT_AES_CTL_KEYPRT_Pos (31) /*!< CRPT_T::AES_CTL: KEYPRT Position */ +#define CRPT_AES_CTL_KEYPRT_Msk (0x1ul << CRPT_AES_CTL_KEYPRT_Pos) /*!< CRPT_T::AES_CTL: KEYPRT Mask */ + +#define CRPT_AES_STS_BUSY_Pos (0) /*!< CRPT_T::AES_STS: BUSY Position */ +#define CRPT_AES_STS_BUSY_Msk (0x1ul << CRPT_AES_STS_BUSY_Pos) /*!< CRPT_T::AES_STS: BUSY Mask */ + +#define CRPT_AES_STS_INBUFEMPTY_Pos (8) /*!< CRPT_T::AES_STS: INBUFEMPTY Position */ +#define CRPT_AES_STS_INBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_INBUFEMPTY_Pos) /*!< CRPT_T::AES_STS: INBUFEMPTY Mask */ + +#define CRPT_AES_STS_INBUFFULL_Pos (9) /*!< CRPT_T::AES_STS: INBUFFULL Position */ +#define CRPT_AES_STS_INBUFFULL_Msk (0x1ul << CRPT_AES_STS_INBUFFULL_Pos) /*!< CRPT_T::AES_STS: INBUFFULL Mask */ + +#define CRPT_AES_STS_INBUFERR_Pos (10) /*!< CRPT_T::AES_STS: INBUFERR Position */ +#define CRPT_AES_STS_INBUFERR_Msk (0x1ul << CRPT_AES_STS_INBUFERR_Pos) /*!< CRPT_T::AES_STS: INBUFERR Mask */ + +#define CRPT_AES_STS_CNTERR_Pos (12) /*!< CRPT_T::AES_STS: CNTERR Position */ +#define CRPT_AES_STS_CNTERR_Msk (0x1ul << CRPT_AES_STS_CNTERR_Pos) /*!< CRPT_T::AES_STS: CNTERR Mask */ + +#define CRPT_AES_STS_OUTBUFEMPTY_Pos (16) /*!< CRPT_T::AES_STS: OUTBUFEMPTY Position */ +#define CRPT_AES_STS_OUTBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_OUTBUFEMPTY_Pos) /*!< CRPT_T::AES_STS: OUTBUFEMPTY Mask */ + +#define CRPT_AES_STS_OUTBUFFULL_Pos (17) /*!< CRPT_T::AES_STS: OUTBUFFULL Position */ +#define CRPT_AES_STS_OUTBUFFULL_Msk (0x1ul << CRPT_AES_STS_OUTBUFFULL_Pos) /*!< CRPT_T::AES_STS: OUTBUFFULL Mask */ + +#define CRPT_AES_STS_OUTBUFERR_Pos (18) /*!< CRPT_T::AES_STS: OUTBUFERR Position */ +#define CRPT_AES_STS_OUTBUFERR_Msk (0x1ul << CRPT_AES_STS_OUTBUFERR_Pos) /*!< CRPT_T::AES_STS: OUTBUFERR Mask */ + +#define CRPT_AES_STS_BUSERR_Pos (20) /*!< CRPT_T::AES_STS: BUSERR Position */ +#define CRPT_AES_STS_BUSERR_Msk (0x1ul << CRPT_AES_STS_BUSERR_Pos) /*!< CRPT_T::AES_STS: BUSERR Mask */ + +#define CRPT_AES_DATIN_DATIN_Pos (0) /*!< CRPT_T::AES_DATIN: DATIN Position */ +#define CRPT_AES_DATIN_DATIN_Msk (0xfffffffful << CRPT_AES_DATIN_DATIN_Pos) /*!< CRPT_T::AES_DATIN: DATIN Mask */ + +#define CRPT_AES_DATOUT_DATOUT_Pos (0) /*!< CRPT_T::AES_DATOUT: DATOUT Position */ +#define CRPT_AES_DATOUT_DATOUT_Msk (0xfffffffful << CRPT_AES_DATOUT_DATOUT_Pos) /*!< CRPT_T::AES_DATOUT: DATOUT Mask */ + +#define CRPT_AES0_KEYx_KEY_Pos (0) /*!< CRPT_T::AES0_KEY[8]: KEY Position */ +#define CRPT_AES0_KEYx_KEY_Msk (0xfffffffful << CRPT_AES0_KEYx_KEY_Pos) /*!< CRPT_T::AES0_KEY[8]: KEY Mask */ + +#define CRPT_AES0_IVx_IV_Pos (0) /*!< CRPT_T::AES0_IV[4]: IV Position */ +#define CRPT_AES0_IVx_IV_Msk (0xfffffffful << CRPT_AES0_IVx_IV_Pos) /*!< CRPT_T::AES0_IV[4]: IV Mask */ + +#define CRPT_AES0_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES0_SADDR: SADDR Position */ +#define CRPT_AES0_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES0_SADDR_SADDR_Pos) /*!< CRPT_T::AES0_SADDR: SADDR Mask */ + +#define CRPT_AES0_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES0_DADDR: DADDR Position */ +#define CRPT_AES0_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES0_DADDR_DADDR_Pos) /*!< CRPT_T::AES0_DADDR: DADDR Mask */ + +#define CRPT_AES0_CNT_CNT_Pos (0) /*!< CRPT_T::AES0_CNT: CNT Position */ +#define CRPT_AES0_CNT_CNT_Msk (0xfffffffful << CRPT_AES0_CNT_CNT_Pos) /*!< CRPT_T::AES0_CNT: CNT Mask */ + +#define CRPT_AES1_KEYx_KEY_Pos (0) /*!< CRPT_T::AES1_KEY[8]: KEY Position */ +#define CRPT_AES1_KEYx_KEY_Msk (0xfffffffful << CRPT_AES1_KEYx_KEY_Pos) /*!< CRPT_T::AES1_KEY[8]: KEY Mask */ + +#define CRPT_AES1_IVx_IV_Pos (0) /*!< CRPT_T::AES1_IV[4]: IV Position */ +#define CRPT_AES1_IVx_IV_Msk (0xfffffffful << CRPT_AES1_IVx_IV_Pos) /*!< CRPT_T::AES1_IV[4]: IV Mask */ + +#define CRPT_AES1_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES1_SADDR: SADDR Position */ +#define CRPT_AES1_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES1_SADDR_SADDR_Pos) /*!< CRPT_T::AES1_SADDR: SADDR Mask */ + +#define CRPT_AES1_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES1_DADDR: DADDR Position */ +#define CRPT_AES1_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES1_DADDR_DADDR_Pos) /*!< CRPT_T::AES1_DADDR: DADDR Mask */ + +#define CRPT_AES1_CNT_CNT_Pos (0) /*!< CRPT_T::AES1_CNT: CNT Position */ +#define CRPT_AES1_CNT_CNT_Msk (0xfffffffful << CRPT_AES1_CNT_CNT_Pos) /*!< CRPT_T::AES1_CNT: CNT Mask */ + +#define CRPT_AES2_KEYx_KEY_Pos (0) /*!< CRPT_T::AES2_KEY[8]: KEY Position */ +#define CRPT_AES2_KEYx_KEY_Msk (0xfffffffful << CRPT_AES2_KEYx_KEY_Pos) /*!< CRPT_T::AES2_KEY[8]: KEY Mask */ + +#define CRPT_AES2_IVx_IV_Pos (0) /*!< CRPT_T::AES2_IV[4]: IV Position */ +#define CRPT_AES2_IVx_IV_Msk (0xfffffffful << CRPT_AES2_IVx_IV_Pos) /*!< CRPT_T::AES2_IV[4]: IV Mask */ + +#define CRPT_AES2_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES2_SADDR: SADDR Position */ +#define CRPT_AES2_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES2_SADDR_SADDR_Pos) /*!< CRPT_T::AES2_SADDR: SADDR Mask */ + +#define CRPT_AES2_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES2_DADDR: DADDR Position */ +#define CRPT_AES2_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES2_DADDR_DADDR_Pos) /*!< CRPT_T::AES2_DADDR: DADDR Mask */ + +#define CRPT_AES2_CNT_CNT_Pos (0) /*!< CRPT_T::AES2_CNT: CNT Position */ +#define CRPT_AES2_CNT_CNT_Msk (0xfffffffful << CRPT_AES2_CNT_CNT_Pos) /*!< CRPT_T::AES2_CNT: CNT Mask */ + +#define CRPT_AES3_KEYx_KEY_Pos (0) /*!< CRPT_T::AES3_KEY[8]: KEY Position */ +#define CRPT_AES3_KEYx_KEY_Msk (0xfffffffful << CRPT_AES3_KEYx_KEY_Pos) /*!< CRPT_T::AES3_KEY[8]: KEY Mask */ + +#define CRPT_AES3_IVx_IV_Pos (0) /*!< CRPT_T::AES3_IV[4]: IV Position */ +#define CRPT_AES3_IVx_IV_Msk (0xfffffffful << CRPT_AES3_IVx_IV_Pos) /*!< CRPT_T::AES3_IV[4]: IV Mask */ + +#define CRPT_AES3_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES3_SADDR: SADDR Position */ +#define CRPT_AES3_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES3_SADDR_SADDR_Pos) /*!< CRPT_T::AES3_SADDR: SADDR Mask */ + +#define CRPT_AES3_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES3_DADDR: DADDR Position */ +#define CRPT_AES3_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES3_DADDR_DADDR_Pos) /*!< CRPT_T::AES3_DADDR: DADDR Mask */ + +#define CRPT_AES3_CNT_CNT_Pos (0) /*!< CRPT_T::AES3_CNT: CNT Position */ +#define CRPT_AES3_CNT_CNT_Msk (0xfffffffful << CRPT_AES3_CNT_CNT_Pos) /*!< CRPT_T::AES3_CNT: CNT Mask */ + +#define CRPT_TDES_CTL_START_Pos (0) /*!< CRPT_T::TDES_CTL: START Position */ +#define CRPT_TDES_CTL_START_Msk (0x1ul << CRPT_TDES_CTL_START_Pos) /*!< CRPT_T::TDES_CTL: START Mask */ + +#define CRPT_TDES_CTL_STOP_Pos (1) /*!< CRPT_T::TDES_CTL: STOP Position */ +#define CRPT_TDES_CTL_STOP_Msk (0x1ul << CRPT_TDES_CTL_STOP_Pos) /*!< CRPT_T::TDES_CTL: STOP Mask */ + +#define CRPT_TDES_CTL_TMODE_Pos (2) /*!< CRPT_T::TDES_CTL: TMODE Position */ +#define CRPT_TDES_CTL_TMODE_Msk (0x1ul << CRPT_TDES_CTL_TMODE_Pos) /*!< CRPT_T::TDES_CTL: TMODE Mask */ + +#define CRPT_TDES_CTL_3KEYS_Pos (3) /*!< CRPT_T::TDES_CTL: 3KEYS Position */ +#define CRPT_TDES_CTL_3KEYS_Msk (0x1ul << CRPT_TDES_CTL_3KEYS_Pos) /*!< CRPT_T::TDES_CTL: 3KEYS Mask */ + +#define CRPT_TDES_CTL_DMALAST_Pos (5) /*!< CRPT_T::TDES_CTL: DMALAST Position */ +#define CRPT_TDES_CTL_DMALAST_Msk (0x1ul << CRPT_TDES_CTL_DMALAST_Pos) /*!< CRPT_T::TDES_CTL: DMALAST Mask */ + +#define CRPT_TDES_CTL_DMACSCAD_Pos (6) /*!< CRPT_T::TDES_CTL: DMACSCAD Position */ +#define CRPT_TDES_CTL_DMACSCAD_Msk (0x1ul << CRPT_TDES_CTL_DMACSCAD_Pos) /*!< CRPT_T::TDES_CTL: DMACSCAD Mask */ + +#define CRPT_TDES_CTL_DMAEN_Pos (7) /*!< CRPT_T::TDES_CTL: DMAEN Position */ +#define CRPT_TDES_CTL_DMAEN_Msk (0x1ul << CRPT_TDES_CTL_DMAEN_Pos) /*!< CRPT_T::TDES_CTL: DMAEN Mask */ + +#define CRPT_TDES_CTL_OPMODE_Pos (8) /*!< CRPT_T::TDES_CTL: OPMODE Position */ +#define CRPT_TDES_CTL_OPMODE_Msk (0x7ul << CRPT_TDES_CTL_OPMODE_Pos) /*!< CRPT_T::TDES_CTL: OPMODE Mask */ + +#define CRPT_TDES_CTL_ENCRPT_Pos (16) /*!< CRPT_T::TDES_CTL: ENCRPT Position */ +#define CRPT_TDES_CTL_ENCRPT_Msk (0x1ul << CRPT_TDES_CTL_ENCRPT_Pos) /*!< CRPT_T::TDES_CTL: ENCRPT Mask */ + +#define CRPT_TDES_CTL_BLKSWAP_Pos (21) /*!< CRPT_T::TDES_CTL: BLKSWAP Position */ +#define CRPT_TDES_CTL_BLKSWAP_Msk (0x1ul << CRPT_TDES_CTL_BLKSWAP_Pos) /*!< CRPT_T::TDES_CTL: BLKSWAP Mask */ + +#define CRPT_TDES_CTL_OUTSWAP_Pos (22) /*!< CRPT_T::TDES_CTL: OUTSWAP Position */ +#define CRPT_TDES_CTL_OUTSWAP_Msk (0x1ul << CRPT_TDES_CTL_OUTSWAP_Pos) /*!< CRPT_T::TDES_CTL: OUTSWAP Mask */ + +#define CRPT_TDES_CTL_INSWAP_Pos (23) /*!< CRPT_T::TDES_CTL: INSWAP Position */ +#define CRPT_TDES_CTL_INSWAP_Msk (0x1ul << CRPT_TDES_CTL_INSWAP_Pos) /*!< CRPT_T::TDES_CTL: INSWAP Mask */ + +#define CRPT_TDES_CTL_CHANNEL_Pos (24) /*!< CRPT_T::TDES_CTL: CHANNEL Position */ +#define CRPT_TDES_CTL_CHANNEL_Msk (0x3ul << CRPT_TDES_CTL_CHANNEL_Pos) /*!< CRPT_T::TDES_CTL: CHANNEL Mask */ + +#define CRPT_TDES_CTL_KEYUNPRT_Pos (26) /*!< CRPT_T::TDES_CTL: KEYUNPRT Position */ +#define CRPT_TDES_CTL_KEYUNPRT_Msk (0x1ful << CRPT_TDES_CTL_KEYUNPRT_Pos) /*!< CRPT_T::TDES_CTL: KEYUNPRT Mask */ + +#define CRPT_TDES_CTL_KEYPRT_Pos (31) /*!< CRPT_T::TDES_CTL: KEYPRT Position */ +#define CRPT_TDES_CTL_KEYPRT_Msk (0x1ul << CRPT_TDES_CTL_KEYPRT_Pos) /*!< CRPT_T::TDES_CTL: KEYPRT Mask */ + +#define CRPT_TDES_STS_BUSY_Pos (0) /*!< CRPT_T::TDES_STS: BUSY Position */ +#define CRPT_TDES_STS_BUSY_Msk (0x1ul << CRPT_TDES_STS_BUSY_Pos) /*!< CRPT_T::TDES_STS: BUSY Mask */ + +#define CRPT_TDES_STS_INBUFEMPTY_Pos (8) /*!< CRPT_T::TDES_STS: INBUFEMPTY Position */ +#define CRPT_TDES_STS_INBUFEMPTY_Msk (0x1ul << CRPT_TDES_STS_INBUFEMPTY_Pos) /*!< CRPT_T::TDES_STS: INBUFEMPTY Mask */ + +#define CRPT_TDES_STS_INBUFFULL_Pos (9) /*!< CRPT_T::TDES_STS: INBUFFULL Position */ +#define CRPT_TDES_STS_INBUFFULL_Msk (0x1ul << CRPT_TDES_STS_INBUFFULL_Pos) /*!< CRPT_T::TDES_STS: INBUFFULL Mask */ + +#define CRPT_TDES_STS_INBUFERR_Pos (10) /*!< CRPT_T::TDES_STS: INBUFERR Position */ +#define CRPT_TDES_STS_INBUFERR_Msk (0x1ul << CRPT_TDES_STS_INBUFERR_Pos) /*!< CRPT_T::TDES_STS: INBUFERR Mask */ + +#define CRPT_TDES_STS_OUTBUFEMPTY_Pos (16) /*!< CRPT_T::TDES_STS: OUTBUFEMPTY Position */ +#define CRPT_TDES_STS_OUTBUFEMPTY_Msk (0x1ul << CRPT_TDES_STS_OUTBUFEMPTY_Pos) /*!< CRPT_T::TDES_STS: OUTBUFEMPTY Mask */ + +#define CRPT_TDES_STS_OUTBUFFULL_Pos (17) /*!< CRPT_T::TDES_STS: OUTBUFFULL Position */ +#define CRPT_TDES_STS_OUTBUFFULL_Msk (0x1ul << CRPT_TDES_STS_OUTBUFFULL_Pos) /*!< CRPT_T::TDES_STS: OUTBUFFULL Mask */ + +#define CRPT_TDES_STS_OUTBUFERR_Pos (18) /*!< CRPT_T::TDES_STS: OUTBUFERR Position */ +#define CRPT_TDES_STS_OUTBUFERR_Msk (0x1ul << CRPT_TDES_STS_OUTBUFERR_Pos) /*!< CRPT_T::TDES_STS: OUTBUFERR Mask */ + +#define CRPT_TDES_STS_BUSERR_Pos (20) /*!< CRPT_T::TDES_STS: BUSERR Position */ +#define CRPT_TDES_STS_BUSERR_Msk (0x1ul << CRPT_TDES_STS_BUSERR_Pos) /*!< CRPT_T::TDES_STS: BUSERR Mask */ + +#define CRPT_TDES0_KEYxH_KEY_Pos (0) /*!< CRPT_T::TDES0_KEYxH: KEY Position */ +#define CRPT_TDES0_KEYxH_KEY_Msk (0xfffffffful << CRPT_TDES0_KEYxH_KEY_Pos) /*!< CRPT_T::TDES0_KEYxH: KEY Mask */ + +#define CRPT_TDES0_KEYxL_KEY_Pos (0) /*!< CRPT_T::TDES0_KEYxL: KEY Position */ +#define CRPT_TDES0_KEYxL_KEY_Msk (0xfffffffful << CRPT_TDES0_KEYxL_KEY_Pos) /*!< CRPT_T::TDES0_KEYxL: KEY Mask */ + +#define CRPT_TDES0_IVH_IV_Pos (0) /*!< CRPT_T::TDES0_IVH: IV Position */ +#define CRPT_TDES0_IVH_IV_Msk (0xfffffffful << CRPT_TDES0_IVH_IV_Pos) /*!< CRPT_T::TDES0_IVH: IV Mask */ + +#define CRPT_TDES0_IVL_IV_Pos (0) /*!< CRPT_T::TDES0_IVL: IV Position */ +#define CRPT_TDES0_IVL_IV_Msk (0xfffffffful << CRPT_TDES0_IVL_IV_Pos) /*!< CRPT_T::TDES0_IVL: IV Mask */ + +#define CRPT_TDES0_SADDR_SADDR_Pos (0) /*!< CRPT_T::TDES0_SADDR: SADDR Position */ +#define CRPT_TDES0_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES0_SADDR_SADDR_Pos) /*!< CRPT_T::TDES0_SADDR: SADDR Mask */ + +#define CRPT_TDES0_DADDR_DADDR_Pos (0) /*!< CRPT_T::TDES0_DADDR: DADDR Position */ +#define CRPT_TDES0_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES0_DADDR_DADDR_Pos) /*!< CRPT_T::TDES0_DADDR: DADDR Mask */ + +#define CRPT_TDES0_CNT_CNT_Pos (0) /*!< CRPT_T::TDES0_CNT: CNT Position */ +#define CRPT_TDES0_CNT_CNT_Msk (0xfffffffful << CRPT_TDES0_CNT_CNT_Pos) /*!< CRPT_T::TDES0_CNT: CNT Mask */ + +#define CRPT_TDES_DATIN_DATIN_Pos (0) /*!< CRPT_T::TDES_DATIN: DATIN Position */ +#define CRPT_TDES_DATIN_DATIN_Msk (0xfffffffful << CRPT_TDES_DATIN_DATIN_Pos) /*!< CRPT_T::TDES_DATIN: DATIN Mask */ + +#define CRPT_TDES_DATOUT_DATOUT_Pos (0) /*!< CRPT_T::TDES_DATOUT: DATOUT Position */ +#define CRPT_TDES_DATOUT_DATOUT_Msk (0xfffffffful << CRPT_TDES_DATOUT_DATOUT_Pos) /*!< CRPT_T::TDES_DATOUT: DATOUT Mask */ + +#define CRPT_TDES1_KEYxH_KEY_Pos (0) /*!< CRPT_T::TDES1_KEYxH: KEY Position */ +#define CRPT_TDES1_KEYxH_KEY_Msk (0xfffffffful << CRPT_TDES1_KEYxH_KEY_Pos) /*!< CRPT_T::TDES1_KEYxH: KEY Mask */ + +#define CRPT_TDES1_KEYxL_KEY_Pos (0) /*!< CRPT_T::TDES1_KEYxL: KEY Position */ +#define CRPT_TDES1_KEYxL_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY1L_KEY_Pos) /*!< CRPT_T::TDES1_KEYxL: KEY Mask */ + +#define CRPT_TDES1_IVH_IV_Pos (0) /*!< CRPT_T::TDES1_IVH: IV Position */ +#define CRPT_TDES1_IVH_IV_Msk (0xfffffffful << CRPT_TDES1_IVH_IV_Pos) /*!< CRPT_T::TDES1_IVH: IV Mask */ + +#define CRPT_TDES1_IVL_IV_Pos (0) /*!< CRPT_T::TDES1_IVL: IV Position */ +#define CRPT_TDES1_IVL_IV_Msk (0xfffffffful << CRPT_TDES1_IVL_IV_Pos) /*!< CRPT_T::TDES1_IVL: IV Mask */ + +#define CRPT_TDES1_SADDR_SADDR_Pos (0) /*!< CRPT_T::TDES1_SADDR: SADDR Position */ +#define CRPT_TDES1_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES1_SADDR_SADDR_Pos) /*!< CRPT_T::TDES1_SADDR: SADDR Mask */ + +#define CRPT_TDES1_DADDR_DADDR_Pos (0) /*!< CRPT_T::TDES1_DADDR: DADDR Position */ +#define CRPT_TDES1_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES1_DADDR_DADDR_Pos) /*!< CRPT_T::TDES1_DADDR: DADDR Mask */ + +#define CRPT_TDES1_CNT_CNT_Pos (0) /*!< CRPT_T::TDES1_CNT: CNT Position */ +#define CRPT_TDES1_CNT_CNT_Msk (0xfffffffful << CRPT_TDES1_CNT_CNT_Pos) /*!< CRPT_T::TDES1_CNT: CNT Mask */ + +#define CRPT_TDES2_KEYxH_KEY_Pos (0) /*!< CRPT_T::TDES2_KEYxH: KEY Position */ +#define CRPT_TDES2_KEYxH_KEY_Msk (0xfffffffful << CRPT_TDES2_KEYxH_KEY_Pos) /*!< CRPT_T::TDES2_KEYxH: KEY Mask */ + +#define CRPT_TDES2_KEYxL_KEY_Pos (0) /*!< CRPT_T::TDES2_KEYxL: KEY Position */ +#define CRPT_TDES2_KEYxL_KEY_Msk (0xfffffffful << CRPT_TDES2_KEYxL_KEY_Pos) /*!< CRPT_T::TDES2_KEYxL: KEY Mask */ + +#define CRPT_TDES2_IVH_IV_Pos (0) /*!< CRPT_T::TDES2_IVH: IV Position */ +#define CRPT_TDES2_IVH_IV_Msk (0xfffffffful << CRPT_TDES2_IVH_IV_Pos) /*!< CRPT_T::TDES2_IVH: IV Mask */ + +#define CRPT_TDES2_IVL_IV_Pos (0) /*!< CRPT_T::TDES2_IVL: IV Position */ +#define CRPT_TDES2_IVL_IV_Msk (0xfffffffful << CRPT_TDES2_IVL_IV_Pos) /*!< CRPT_T::TDES2_IVL: IV Mask */ + +#define CRPT_TDES2_SADDR_SADDR_Pos (0) /*!< CRPT_T::TDES2_SADDR: SADDR Position */ +#define CRPT_TDES2_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES2_SADDR_SADDR_Pos) /*!< CRPT_T::TDES2_SADDR: SADDR Mask */ + +#define CRPT_TDES2_DADDR_DADDR_Pos (0) /*!< CRPT_T::TDES2_DADDR: DADDR Position */ +#define CRPT_TDES2_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES2_DADDR_DADDR_Pos) /*!< CRPT_T::TDES2_DADDR: DADDR Mask */ + +#define CRPT_TDES2_CNT_CNT_Pos (0) /*!< CRPT_T::TDES2_CNT: CNT Position */ +#define CRPT_TDES2_CNT_CNT_Msk (0xfffffffful << CRPT_TDES2_CNT_CNT_Pos) /*!< CRPT_T::TDES2_CNT: CNT Mask */ + +#define CRPT_TDES3_KEYxH_KEY_Pos (0) /*!< CRPT_T::TDES3_KEYxH: KEY Position */ +#define CRPT_TDES3_KEYxH_KEY_Msk (0xfffffffful << CRPT_TDES3_KEYxH_KEY_Pos) /*!< CRPT_T::TDES3_KEYxH: KEY Mask */ + +#define CRPT_TDES3_KEYxL_KEY_Pos (0) /*!< CRPT_T::TDES3_KEYxL: KEY Position */ +#define CRPT_TDES3_KEYxL_KEY_Msk (0xfffffffful << CRPT_TDES3_KEYxL_KEY_Pos) /*!< CRPT_T::TDES3_KEYxL: KEY Mask */ + +#define CRPT_TDES3_IVH_IV_Pos (0) /*!< CRPT_T::TDES3_IVH: IV Position */ +#define CRPT_TDES3_IVH_IV_Msk (0xfffffffful << CRPT_TDES3_IVH_IV_Pos) /*!< CRPT_T::TDES3_IVH: IV Mask */ + +#define CRPT_TDES3_IVL_IV_Pos (0) /*!< CRPT_T::TDES3_IVL: IV Position */ +#define CRPT_TDES3_IVL_IV_Msk (0xfffffffful << CRPT_TDES3_IVL_IV_Pos) /*!< CRPT_T::TDES3_IVL: IV Mask */ + +#define CRPT_TDES3_SADDR_SADDR_Pos (0) /*!< CRPT_T::TDES3_SADDR: SADDR Position */ +#define CRPT_TDES3_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES3_SADDR_SADDR_Pos) /*!< CRPT_T::TDES3_SADDR: SADDR Mask */ + +#define CRPT_TDES3_DADDR_DADDR_Pos (0) /*!< CRPT_T::TDES3_DADDR: DADDR Position */ +#define CRPT_TDES3_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES3_DADDR_DADDR_Pos) /*!< CRPT_T::TDES3_DADDR: DADDR Mask */ + +#define CRPT_TDES3_CNT_CNT_Pos (0) /*!< CRPT_T::TDES3_CNT: CNT Position */ +#define CRPT_TDES3_CNT_CNT_Msk (0xfffffffful << CRPT_TDES3_CNT_CNT_Pos) /*!< CRPT_T::TDES3_CNT: CNT Mask */ + +#define CRPT_HMAC_CTL_START_Pos (0) /*!< CRPT_T::HMAC_CTL: START Position */ +#define CRPT_HMAC_CTL_START_Msk (0x1ul << CRPT_HMAC_CTL_START_Pos) /*!< CRPT_T::HMAC_CTL: START Mask */ + +#define CRPT_HMAC_CTL_STOP_Pos (1) /*!< CRPT_T::HMAC_CTL: STOP Position */ +#define CRPT_HMAC_CTL_STOP_Msk (0x1ul << CRPT_HMAC_CTL_STOP_Pos) /*!< CRPT_T::HMAC_CTL: STOP Mask */ + +#define CRPT_HMAC_CTL_HMACEN_Pos (4) /*!< CRPT_T::HMAC_CTL: HMACEN Position */ +#define CRPT_HMAC_CTL_HMACEN_Msk (0x1ul << CRPT_HMAC_CTL_HMACEN_Pos) /*!< CRPT_T::HMAC_CTL: HMACEN Mask */ + +#define CRPT_HMAC_CTL_DMALAST_Pos (5) /*!< CRPT_T::HMAC_CTL: DMALAST Position */ +#define CRPT_HMAC_CTL_DMALAST_Msk (0x1ul << CRPT_HMAC_CTL_DMALAST_Pos) /*!< CRPT_T::HMAC_CTL: DMALAST Mask */ + +#define CRPT_HMAC_CTL_DMAEN_Pos (7) /*!< CRPT_T::HMAC_CTL: DMAEN Position */ +#define CRPT_HMAC_CTL_DMAEN_Msk (0x1ul << CRPT_HMAC_CTL_DMAEN_Pos) /*!< CRPT_T::HMAC_CTL: DMAEN Mask */ + +#define CRPT_HMAC_CTL_OPMODE_Pos (8) /*!< CRPT_T::HMAC_CTL: OPMODE Position */ +#define CRPT_HMAC_CTL_OPMODE_Msk (0x7ul << CRPT_HMAC_CTL_OPMODE_Pos) /*!< CRPT_T::HMAC_CTL: OPMODE Mask */ + +#define CRPT_HMAC_CTL_OUTSWAP_Pos (22) /*!< CRPT_T::HMAC_CTL: OUTSWAP Position */ +#define CRPT_HMAC_CTL_OUTSWAP_Msk (0x1ul << CRPT_HMAC_CTL_OUTSWAP_Pos) /*!< CRPT_T::HMAC_CTL: OUTSWAP Mask */ + +#define CRPT_HMAC_CTL_INSWAP_Pos (23) /*!< CRPT_T::HMAC_CTL: INSWAP Position */ +#define CRPT_HMAC_CTL_INSWAP_Msk (0x1ul << CRPT_HMAC_CTL_INSWAP_Pos) /*!< CRPT_T::HMAC_CTL: INSWAP Mask */ + +#define CRPT_HMAC_STS_BUSY_Pos (0) /*!< CRPT_T::HMAC_STS: BUSY Position */ +#define CRPT_HMAC_STS_BUSY_Msk (0x1ul << CRPT_HMAC_STS_BUSY_Pos) /*!< CRPT_T::HMAC_STS: BUSY Mask */ + +#define CRPT_HMAC_STS_DMABUSY_Pos (1) /*!< CRPT_T::HMAC_STS: DMABUSY Position */ +#define CRPT_HMAC_STS_DMABUSY_Msk (0x1ul << CRPT_HMAC_STS_DMABUSY_Pos) /*!< CRPT_T::HMAC_STS: DMABUSY Mask */ + +#define CRPT_HMAC_STS_DMAERR_Pos (8) /*!< CRPT_T::HMAC_STS: DMAERR Position */ +#define CRPT_HMAC_STS_DMAERR_Msk (0x1ul << CRPT_HMAC_STS_DMAERR_Pos) /*!< CRPT_T::HMAC_STS: DMAERR Mask */ + +#define CRPT_HMAC_STS_DATINREQ_Pos (16) /*!< CRPT_T::HMAC_STS: DATINREQ Position */ +#define CRPT_HMAC_STS_DATINREQ_Msk (0x1ul << CRPT_HMAC_STS_DATINREQ_Pos) /*!< CRPT_T::HMAC_STS: DATINREQ Mask */ + +#define CRPT_HMAC_DGSTx_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST[16]: DGST Position */ +#define CRPT_HMAC_DGSTx_DGST_Msk (0xfffffffful << CRPT_HMAC_DGSTx_DGST_Pos) /*!< CRPT_T::HMAC_DGST[16]: DGST Mask */ + +#define CRPT_HMAC_KEYCNT_KEYCNT_Pos (0) /*!< CRPT_T::HMAC_KEYCNT: KEYCNT Position */ +#define CRPT_HMAC_KEYCNT_KEYCNT_Msk (0xfffffffful << CRPT_HMAC_KEYCNT_KEYCNT_Pos) /*!< CRPT_T::HMAC_KEYCNT: KEYCNT Mask */ + +#define CRPT_HMAC_SADDR_SADDR_Pos (0) /*!< CRPT_T::HMAC_SADDR: SADDR Position */ +#define CRPT_HMAC_SADDR_SADDR_Msk (0xfffffffful << CRPT_HMAC_SADDR_SADDR_Pos) /*!< CRPT_T::HMAC_SADDR: SADDR Mask */ + +#define CRPT_HMAC_DMACNT_DMACNT_Pos (0) /*!< CRPT_T::HMAC_DMACNT: DMACNT Position */ +#define CRPT_HMAC_DMACNT_DMACNT_Msk (0xfffffffful << CRPT_HMAC_DMACNT_DMACNT_Pos) /*!< CRPT_T::HMAC_DMACNT: DMACNT Mask */ + +#define CRPT_HMAC_DATIN_DATIN_Pos (0) /*!< CRPT_T::HMAC_DATIN: DATIN Position */ +#define CRPT_HMAC_DATIN_DATIN_Msk (0xfffffffful << CRPT_HMAC_DATIN_DATIN_Pos) /*!< CRPT_T::HMAC_DATIN: DATIN Mask */ + +#define CRPT_ECC_CTL_START_Pos (0) /*!< CRPT_T::ECC_CTL: START Position */ +#define CRPT_ECC_CTL_START_Msk (0x1ul << CRPT_ECC_CTL_START_Pos) /*!< CRPT_T::ECC_CTL: START Mask */ + +#define CRPT_ECC_CTL_STOP_Pos (1) /*!< CRPT_T::ECC_CTL: STOP Position */ +#define CRPT_ECC_CTL_STOP_Msk (0x1ul << CRPT_ECC_CTL_STOP_Pos) /*!< CRPT_T::ECC_CTL: STOP Mask */ + +#define CRPT_ECC_CTL_DMAEN_Pos (7) /*!< CRPT_T::ECC_CTL: DMAEN Position */ +#define CRPT_ECC_CTL_DMAEN_Msk (0x1ul << CRPT_ECC_CTL_DMAEN_Pos) /*!< CRPT_T::ECC_CTL: DMAEN Mask */ + +#define CRPT_ECC_CTL_FSEL_Pos (8) /*!< CRPT_T::ECC_CTL: FSEL Position */ +#define CRPT_ECC_CTL_FSEL_Msk (0x1ul << CRPT_ECC_CTL_FSEL_Pos) /*!< CRPT_T::ECC_CTL: FSEL Mask */ + +#define CRPT_ECC_CTL_ECCOP_Pos (9) /*!< CRPT_T::ECC_CTL: ECCOP Position */ +#define CRPT_ECC_CTL_ECCOP_Msk (0x3ul << CRPT_ECC_CTL_ECCOP_Pos) /*!< CRPT_T::ECC_CTL: ECCOP Mask */ + +#define CRPT_ECC_CTL_MODOP_Pos (11) /*!< CRPT_T::ECC_CTL: MODOP Position */ +#define CRPT_ECC_CTL_MODOP_Msk (0x3ul << CRPT_ECC_CTL_MODOP_Pos) /*!< CRPT_T::ECC_CTL: MODOP Mask */ + +#define CRPT_ECC_CTL_LDP1_Pos (16) /*!< CRPT_T::ECC_CTL: LDP1 Position */ +#define CRPT_ECC_CTL_LDP1_Msk (0x1ul << CRPT_ECC_CTL_LDP1_Pos) /*!< CRPT_T::ECC_CTL: LDP1 Mask */ + +#define CRPT_ECC_CTL_LDP2_Pos (17) /*!< CRPT_T::ECC_CTL: LDP2 Position */ +#define CRPT_ECC_CTL_LDP2_Msk (0x1ul << CRPT_ECC_CTL_LDP2_Pos) /*!< CRPT_T::ECC_CTL: LDP2 Mask */ + +#define CRPT_ECC_CTL_LDA_Pos (18) /*!< CRPT_T::ECC_CTL: LDA Position */ +#define CRPT_ECC_CTL_LDA_Msk (0x1ul << CRPT_ECC_CTL_LDA_Pos) /*!< CRPT_T::ECC_CTL: LDA Mask */ + +#define CRPT_ECC_CTL_LDB_Pos (19) /*!< CRPT_T::ECC_CTL: LDB Position */ +#define CRPT_ECC_CTL_LDB_Msk (0x1ul << CRPT_ECC_CTL_LDB_Pos) /*!< CRPT_T::ECC_CTL: LDB Mask */ + +#define CRPT_ECC_CTL_LDN_Pos (20) /*!< CRPT_T::ECC_CTL: LDN Position */ +#define CRPT_ECC_CTL_LDN_Msk (0x1ul << CRPT_ECC_CTL_LDN_Pos) /*!< CRPT_T::ECC_CTL: LDN Mask */ + +#define CRPT_ECC_CTL_LDK_Pos (21) /*!< CRPT_T::ECC_CTL: LDK Position */ +#define CRPT_ECC_CTL_LDK_Msk (0x1ul << CRPT_ECC_CTL_LDK_Pos) /*!< CRPT_T::ECC_CTL: LDK Mask */ + +#define CRPT_ECC_CTL_CURVEM_Pos (22) /*!< CRPT_T::ECC_CTL: CURVEM Position */ +#define CRPT_ECC_CTL_CURVEM_Msk (0x3fful << CRPT_ECC_CTL_CURVEM_Pos) /*!< CRPT_T::ECC_CTL: CURVEM Mask */ + +#define CRPT_ECC_STS_BUSY_Pos (0) /*!< CRPT_T::ECC_STS: BUSY Position */ +#define CRPT_ECC_STS_BUSY_Msk (0x1ul << CRPT_ECC_STS_BUSY_Pos) /*!< CRPT_T::ECC_STS: BUSY Mask */ + +#define CRPT_ECC_STS_DMABUSY_Pos (1) /*!< CRPT_T::ECC_STS: DMABUSY Position */ +#define CRPT_ECC_STS_DMABUSY_Msk (0x1ul << CRPT_ECC_STS_DMABUSY_Pos) /*!< CRPT_T::ECC_STS: DMABUSY Mask */ + +#define CRPT_ECC_STS_BUSERR_Pos (16) /*!< CRPT_T::ECC_STS: BUSERR Position */ +#define CRPT_ECC_STS_BUSERR_Msk (0x1ul << CRPT_ECC_STS_BUSERR_Pos) /*!< CRPT_T::ECC_STS: BUSERR Mask */ + +#define CRPT_ECC_X1_POINTX1_Pos (0) /*!< CRPT_T::ECC_X1[18]: POINTX1 Position */ +#define CRPT_ECC_X1_POINTX1_Msk (0xfffffffful << CRPT_ECC_X1_POINTX1_Pos) /*!< CRPT_T::ECC_X1[18]: POINTX1 Mask */ + +#define CRPT_ECC_Y1_POINTY1_Pos (0) /*!< CRPT_T::ECC_Y1[18]: POINTY1 Position */ +#define CRPT_ECC_Y1_POINTY1_Msk (0xfffffffful << CRPT_ECC_Y1_POINTY1_Pos) /*!< CRPT_T::ECC_Y1[18]: POINTY1 Mask */ + +#define CRPT_ECC_X2_POINTX2_Pos (0) /*!< CRPT_T::ECC_X2[18]: POINTX2 Position */ +#define CRPT_ECC_X2_POINTX2_Msk (0xfffffffful << CRPT_ECC_X2_POINTX2_Pos) /*!< CRPT_T::ECC_X2[18]: POINTX2 Mask */ + +#define CRPT_ECC_Y2_POINTY2_Pos (0) /*!< CRPT_T::ECC_Y2[18]: POINTY2 Position */ +#define CRPT_ECC_Y2_POINTY2_Msk (0xfffffffful << CRPT_ECC_Y2_POINTY2_Pos) /*!< CRPT_T::ECC_Y2[18]: POINTY2 Mask */ + +#define CRPT_ECC_A_CURVEA_Pos (0) /*!< CRPT_T::ECC_A[18]: CURVEA Position */ +#define CRPT_ECC_A_CURVEA_Msk (0xfffffffful << CRPT_ECC_A_CURVEA_Pos) /*!< CRPT_T::ECC_A[18]: CURVEA Mask */ + +#define CRPT_ECC_B_CURVEB_Pos (0) /*!< CRPT_T::ECC_B[18]: CURVEB Position */ +#define CRPT_ECC_B_CURVEB_Msk (0xfffffffful << CRPT_ECC_B_CURVEB_Pos) /*!< CRPT_T::ECC_B[18]: CURVEB Mask */ + +#define CRPT_ECC_N_CURVEN_Pos (0) /*!< CRPT_T::ECC_N[18]: CURVEN Position */ +#define CRPT_ECC_N_CURVEN_Msk (0xfffffffful << CRPT_ECC_N_CURVEN_Pos) /*!< CRPT_T::ECC_N[18]: CURVEN Mask */ + +#define CRPT_ECC_K_SCALARK_Pos (0) /*!< CRPT_T::ECC_K[18]: SCALARK Position */ +#define CRPT_ECC_K_SCALARK_Msk (0xfffffffful << CRPT_ECC_K_SCALARK_Pos) /*!< CRPT_T::ECC_K[18]: SCALARK Mask */ + +#define CRPT_ECC_DADDR_DADDR_Pos (0) /*!< CRPT_T::ECC_DADDR: DADDR Position */ +#define CRPT_ECC_DADDR_DADDR_Msk (0xfffffffful << CRPT_ECC_DADDR_DADDR_Pos) /*!< CRPT_T::ECC_DADDR: DADDR Mask */ + +#define CRPT_ECC_STARTREG_STARTREG_Pos (0) /*!< CRPT_T::ECC_STARTREG: STARTREG Position*/ +#define CRPT_ECC_STARTREG_STARTREG_Msk (0xfffffffful << CRPT_ECC_STARTREG_STARTREG_Pos) /*!< CRPT_T::ECC_STARTREG: STARTREG Mask */ + +#define CRPT_ECC_WORDCNT_WORDCNT_Pos (0) /*!< CRPT_T::ECC_WORDCNT: WORDCNT Position */ +#define CRPT_ECC_WORDCNT_WORDCNT_Msk (0xfffffffful << CRPT_ECC_WORDCNT_WORDCNT_Pos) /*!< CRPT_T::ECC_WORDCNT: WORDCNT Mask */ + +/**@}*/ /* CRPT_CONST CRYPTO */ +/**@}*/ /* end of CRYPTO register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __CRYPTO_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/dac_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/dac_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..bf2f67a5f1fba7c951b81c81d627effd15674009 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/dac_reg.h @@ -0,0 +1,210 @@ +/**************************************************************************//** + * @file dac_reg.h + * @version V1.00 + * @brief DAC register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __DAC_REG_H__ +#define __DAC_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup DAC Digital to Analog Converter(DAC) + Memory Mapped Structure for DAC Controller +@{ */ + +typedef struct +{ + + + /** + * @var DAC_T::CTL + * Offset: 0x00 DAC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DACEN |DAC Enable Bit + * | | |0 = DAC is Disabled. + * | | |1 = DAC is Enabled. + * |[1] |DACIEN |DAC Interrupt Enable Bit + * | | |0 = Interrupt is Disabled. + * | | |1 = Interrupt is Enabled. + * |[2] |DMAEN |DMA Mode Enable Bit + * | | |0 = DMA mode Disabled. + * | | |1 = DMA mode Enabled. + * |[3] |DMAURIEN |DMA Under-run Interrupt Enable Bit + * | | |0 = DMA under-run interrupt Disabled. + * | | |1 = DMA under-run interrupt Enabled. + * |[4] |TRGEN |Trigger Mode Enable Bit + * | | |0 = DAC event trigger mode Disabled. + * | | |1 = DAC event trigger mode Enabled. + * |[7:5] |TRGSEL |Trigger Source Selection + * | | |000 = Software trigger. + * | | |001 = External pin DAC0_ST trigger. + * | | |010 = Timer 0 trigger. + * | | |011 = Timer 1 trigger. + * | | |100 = Timer 2 trigger. + * | | |101 = Timer 3 trigger. + * | | |110 = EPWM0 trigger. + * | | |111 = EPWM1 trigger. + * |[8] |BYPASS |Bypass Buffer Mode + * | | |0 = Output voltage buffer Enabled. + * | | |1 = Output voltage buffer Disabled. + * |[10] |LALIGN |DAC Data Left-aligned Enabled Control + * | | |0 = Right alignment. + * | | |1 = Left alignment. + * |[13:12] |ETRGSEL |External Pin Trigger Selection + * | | |00 = Low level trigger. + * | | |01 = High level trigger. + * | | |10 = Falling edge trigger. + * | | |11 = Rising edge trigger. + * |[15:14] |BWSEL |DAC Data Bit-width Selection + * | | |00 = data is 12 bits. + * | | |01 = data is 8 bits. + * | | |Others = reserved. + * |[16] |GRPEN |DAC Group Mode Enable Bit + * | | |0 = DAC0 and DAC1 are not grouped. + * | | |1 = DAC0 and DAC1 are grouped. + * @var DAC_T::SWTRG + * Offset: 0x04 DAC Software Trigger Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SWTRG |Software Trigger + * | | |0 = Software trigger Disabled. + * | | |1 = Software trigger Enabled. + * | | |User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically; Reading this bit will always get 0. + * @var DAC_T::DAT + * Offset: 0x08 DAC Data Holding Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |DACDAT |DAC 12-bit Holding Data + * | | |These bits are written by user software which specifies 12-bit conversion data for DAC output + * | | |The unused bits (DAC_DAT[3:0] in left-alignment mode and DAC_DAT[15:12] in right alignment mode) are ignored by DAC controller hardware. + * | | |12 bit left alignment: user has to load data into DAC_DAT[15:4] bits. + * | | |12 bit right alignment: user has to load data into DAC_DAT[11:0] bits. + * @var DAC_T::DATOUT + * Offset: 0x0C DAC Data Output Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |DATOUT |DAC 12-bit Output Data + * | | |These bits are current digital data for DAC output conversion. + * | | |It is loaded from DAC_DAT register and user cannot write it directly. + * @var DAC_T::STATUS + * Offset: 0x10 DAC Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FINISH |DAC Conversion Complete Finish Flag + * | | |0 = DAC is in conversion state. + * | | |1 = DAC conversion finish. + * | | |This bit set to 1 when conversion time counter counts to SETTLET + * | | |It is cleared to 0 when DAC starts a new conversion + * | | |User writes 1 to clear this bit to 0. + * |[1] |DMAUDR |DMA Under-run Interrupt Flag + * | | |0 = No DMA under-run error condition occurred. + * | | |1 = DMA under-run error condition occurred. + * | | |User writes 1 to clear this bit. + * |[8] |BUSY |DAC Busy Flag (Read Only) + * | | |0 = DAC is ready for next conversion. + * | | |1 = DAC is busy in conversion. + * | | |This is read only bit. + * @var DAC_T::TCTL + * Offset: 0x14 DAC Timing Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |SETTLET |DAC Output Settling Time + * | | |User software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed. + * | | |For example, DAC controller clock speed is 80MHz and DAC conversion settling time is 1 us, SETTLETvalue must be greater than 0x50. + * | | |SELTTLET = DAC controller clock speed x settling time. + */ + __IO uint32_t CTL; /*!< [0x0000] DAC Control Register */ + __IO uint32_t SWTRG; /*!< [0x0004] DAC Software Trigger Control Register */ + __IO uint32_t DAT; /*!< [0x0008] DAC Data Holding Register */ + __I uint32_t DATOUT; /*!< [0x000c] DAC Data Output Register */ + __IO uint32_t STATUS; /*!< [0x0010] DAC Status Register */ + __IO uint32_t TCTL; /*!< [0x0014] DAC Timing Control Register */ + +} DAC_T; + +/** + @addtogroup DAC_CONST DAC Bit Field Definition + Constant Definitions for DAC Controller +@{ */ + +#define DAC_CTL_DACEN_Pos (0) /*!< DAC_T::CTL: DACEN Position */ +#define DAC_CTL_DACEN_Msk (0x1ul << DAC_CTL_DACEN_Pos) /*!< DAC_T::CTL: DACEN Mask */ + +#define DAC_CTL_DACIEN_Pos (1) /*!< DAC_T::CTL: DACIEN Position */ +#define DAC_CTL_DACIEN_Msk (0x1ul << DAC_CTL_DACIEN_Pos) /*!< DAC_T::CTL: DACIEN Mask */ + +#define DAC_CTL_DMAEN_Pos (2) /*!< DAC_T::CTL: DMAEN Position */ +#define DAC_CTL_DMAEN_Msk (0x1ul << DAC_CTL_DMAEN_Pos) /*!< DAC_T::CTL: DMAEN Mask */ + +#define DAC_CTL_DMAURIEN_Pos (3) /*!< DAC_T::CTL: DMAURIEN Position */ +#define DAC_CTL_DMAURIEN_Msk (0x1ul << DAC_CTL_DMAURIEN_Pos) /*!< DAC_T::CTL: DMAURIEN Mask */ + +#define DAC_CTL_TRGEN_Pos (4) /*!< DAC_T::CTL: TRGEN Position */ +#define DAC_CTL_TRGEN_Msk (0x1ul << DAC_CTL_TRGEN_Pos) /*!< DAC_T::CTL: TRGEN Mask */ + +#define DAC_CTL_TRGSEL_Pos (5) /*!< DAC_T::CTL: TRGSEL Position */ +#define DAC_CTL_TRGSEL_Msk (0x7ul << DAC_CTL_TRGSEL_Pos) /*!< DAC_T::CTL: TRGSEL Mask */ + +#define DAC_CTL_BYPASS_Pos (8) /*!< DAC_T::CTL: BYPASS Position */ +#define DAC_CTL_BYPASS_Msk (0x1ul << DAC_CTL_BYPASS_Pos) /*!< DAC_T::CTL: BYPASS Mask */ + +#define DAC_CTL_LALIGN_Pos (10) /*!< DAC_T::CTL: LALIGN Position */ +#define DAC_CTL_LALIGN_Msk (0x1ul << DAC_CTL_LALIGN_Pos) /*!< DAC_T::CTL: LALIGN Mask */ + +#define DAC_CTL_ETRGSEL_Pos (12) /*!< DAC_T::CTL: ETRGSEL Position */ +#define DAC_CTL_ETRGSEL_Msk (0x3ul << DAC_CTL_ETRGSEL_Pos) /*!< DAC_T::CTL: ETRGSEL Mask */ + +#define DAC_CTL_BWSEL_Pos (14) /*!< DAC_T::CTL: BWSEL Position */ +#define DAC_CTL_BWSEL_Msk (0x3ul << DAC_CTL_BWSEL_Pos) /*!< DAC_T::CTL: BWSEL Mask */ + +#define DAC_CTL_GRPEN_Pos (16) /*!< DAC_T::CTL: GRPEN Position */ +#define DAC_CTL_GRPEN_Msk (0x1ul << DAC_CTL_GRPEN_Pos) /*!< DAC_T::CTL: GRPEN Mask */ + +#define DAC_SWTRG_SWTRG_Pos (0) /*!< DAC_T::SWTRG: SWTRG Position */ +#define DAC_SWTRG_SWTRG_Msk (0x1ul << DAC_SWTRG_SWTRG_Pos) /*!< DAC_T::SWTRG: SWTRG Mask */ + +#define DAC_DAT_DACDAT_Pos (0) /*!< DAC_T::DAT: DACDAT Position */ +#define DAC_DAT_DACDAT_Msk (0xfffful << DAC_DAT_DACDAT_Pos) /*!< DAC_T::DAT: DACDAT Mask */ + +#define DAC_DATOUT_DATOUT_Pos (0) /*!< DAC_T::DATOUT: DATOUT Position */ +#define DAC_DATOUT_DATOUT_Msk (0xffful << DAC_DATOUT_DATOUT_Pos) /*!< DAC_T::DATOUT: DATOUT Mask */ + +#define DAC_STATUS_FINISH_Pos (0) /*!< DAC_T::STATUS: FINISH Position */ +#define DAC_STATUS_FINISH_Msk (0x1ul << DAC_STATUS_FINISH_Pos) /*!< DAC_T::STATUS: FINISH Mask */ + +#define DAC_STATUS_DMAUDR_Pos (1) /*!< DAC_T::STATUS: DMAUDR Position */ +#define DAC_STATUS_DMAUDR_Msk (0x1ul << DAC_STATUS_DMAUDR_Pos) /*!< DAC_T::STATUS: DMAUDR Mask */ + +#define DAC_STATUS_BUSY_Pos (8) /*!< DAC_T::STATUS: BUSY Position */ +#define DAC_STATUS_BUSY_Msk (0x1ul << DAC_STATUS_BUSY_Pos) /*!< DAC_T::STATUS: BUSY Mask */ + +#define DAC_TCTL_SETTLET_Pos (0) /*!< DAC_T::TCTL: SETTLET Position */ +#define DAC_TCTL_SETTLET_Msk (0x3fful << DAC_TCTL_SETTLET_Pos) /*!< DAC_T::TCTL: SETTLET Mask */ + +/**@}*/ /* DAC_CONST */ +/**@}*/ /* end of DAC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __DAC_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/eadc_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/eadc_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..ee500f6ec90d5d5ce84830d8f9f38183d1542a34 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/eadc_reg.h @@ -0,0 +1,1714 @@ +/**************************************************************************//** + * @file eadc_reg.h + * @version V1.00 + * @brief EADC register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EADC_REG_H__ +#define __EADC_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup EADC Enhanced Analog to Digital Converter(EADC) + Memory Mapped Structure for EADC Controller +@{ */ + +typedef struct +{ + + + /** + * @var EADC_T::DAT[19] + * Offset: 0x00 ADC Data Register 0~18 for Sample Module 0~18 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RESULT |ADC Conversion Result + * | | |This field contains 12 bits conversion result. + * | | |When DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12]. + * | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12]. + * |[16] |OV |Overrun Flag + * | | |If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1. + * | | |0 = Data in RESULT[11:0] is recent conversion result. + * | | |1 = Data in RESULT[11:0] is overwrite. + * | | |Note: It is cleared by hardware after EADC_DAT register is read. + * |[17] |VALID |Valid Flag + * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read. + * | | |0 = Data in RESULT[11:0] bits is not valid. + * | | |1 = Data in RESULT[11:0] bits is valid. + * @var EADC_T::CURDAT + * Offset: 0x4C ADC PDMA Current Transfer Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[17:0] |CURDAT |ADC PDMA Current Transfer Data Register + * | | |This register is a shadow register of EADC_DATn (n=0~18) for PDMA support. + * | | |This is a read only register. + * @var EADC_T::CTL + * Offset: 0x50 ADC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADCEN |ADC Converter Enable Bit + * | | |0 = Disabled EADC. + * | | |1 = Enabled EADC. + * | | |Note: Before starting ADC conversion function, this bit should be set to 1 + * | | |Clear it to 0 to disable ADC converter analog circuit power consumption. + * |[1] |ADCRST |ADC Converter Control Circuits Reset + * | | |0 = No effect. + * | | |1 = Cause ADC control circuits reset to initial state, but not change the ADC registers value. + * | | |Note: ADCRST bit remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0. + * |[2] |ADCIEN0 |Specific Sample Module ADC ADINT0 Interrupt Enable Bit + * | | |The ADC converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module ADC conversion + * | | |If ADCIEN0 bit is set then conversion end interrupt request ADINT0 is generated. + * | | |0 = Specific sample module ADC ADINT0 interrupt function Disabled. + * | | |1 = Specific sample module ADC ADINT0 interrupt function Enabled. + * |[3] |ADCIEN1 |Specific Sample Module ADC ADINT1 Interrupt Enable Bit + * | | |The ADC converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module ADC conversion + * | | |If ADCIEN1 bit is set then conversion end interrupt request ADINT1 is generated. + * | | |0 = Specific sample module ADC ADINT1 interrupt function Disabled. + * | | |1 = Specific sample module ADC ADINT1 interrupt function Enabled. + * |[4] |ADCIEN2 |Specific Sample Module ADC ADINT2 Interrupt Enable Bit + * | | |The ADC converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module ADC conversion + * | | |If ADCIEN2 bit is set then conversion end interrupt request ADINT2 is generated. + * | | |0 = Specific sample module ADC ADINT2 interrupt function Disabled. + * | | |1 = Specific sample module ADC ADINT2 interrupt function Enabled. + * |[5] |ADCIEN3 |Specific Sample Module ADC ADINT3 Interrupt Enable Bit + * | | |The ADC converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module ADC conversion + * | | |If ADCIEN3 bit is set then conversion end interrupt request ADINT3 is generated. + * | | |0 = Specific sample module ADC ADINT3 interrupt function Disabled. + * | | |1 = Specific sample module ADC ADINT3 interrupt function Enabled. + * |[7:6] |RESSEL |Resolution Selection + * | | |00 = 6-bit ADC result will be put at RESULT (EADC_DATn[5:0]). + * | | |01 = 8-bit ADC result will be put at RESULT (EADC_DATn[7:0]). + * | | |10 = 10-bit ADC result will be put at RESULT (EADC_DATn[9:0]). + * | | |11 = 12-bit ADC result will be put at RESULT (EADC_DATn[11:0]). + * |[8] |DIFFEN |Differential Analog Input Mode Enable Bit + * | | |0 = Single-end analog input mode. + * | | |1 = Differential analog input mode. + * |[9] |DMOF |ADC Differential Input Mode Output Format + * | | |0 = ADC conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with unsigned format. + * | | |1 = ADC conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with 2'complement format. + * |[11] |PDMAEN |PDMA Transfer Enable Bit + * | | |When ADC conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, user can enable this bit to generate a PDMA data transfer request. + * | | |0 = PDMA data transfer Disabled. + * | | |1 = PDMA data transfer Enabled. + * | | |Note: When set this bit field to 1, user must set ADCIENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt. + * @var EADC_T::SWTRG + * Offset: 0x54 ADC Sample Module Software Start Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[18:0] |SWTRG |ADC Sample Module 0~18 Software Force to Start ADC Conversion + * | | |0 = No effect. + * | | |1 = Cause an ADC conversion when the priority is given to sample module. + * | | |Note: After write this register to start ADC conversion, the EADC_PENDSTS register will show which sample module will conversion + * | | |If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it. + * @var EADC_T::PENDSTS + * Offset: 0x58 ADC Start of Conversion Pending Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[18:0] |STPF |ADC Sample Module 0~18 Start of Conversion Pending Flag + * | | |Read: + * | | |0 = There is no pending conversion for sample module. + * | | |1 = Sample module ADC start of conversion is pending. + * | | |Write: + * | | |1 = clear pending flag & cancel the conversion for sample module. + * | | |Note: This bit remains 1 during pending state, when the respective ADC conversion is end, the STPFn (n=0~18) bit is automatically cleared to 0 + * @var EADC_T::OVSTS + * Offset: 0x5C ADC Sample Module Start of Conversion Overrun Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[18:0] |SPOVF |ADC SAMPLE0~18 Overrun Flag + * | | |0 = No sample module event overrun. + * | | |1 = Indicates a new sample module event is generated while an old one event is pending. + * | | |Note: This bit is cleared by writing 1 to it. + * @var EADC_T::SCTL[19] + * Offset: 0x80 ADC Sample Module 0~18 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |CHSEL |ADC Sample Module Channel Selection + * | | |00H = EADC_CH0 (slow channel). + * | | |01H = EADC_CH1 (slow channel). + * | | |02H = EADC_CH2 (slow channel). + * | | |03H = EADC_CH3 (slow channel). + * | | |04H = EADC_CH4 (slow channel). + * | | |05H = EADC_CH5 (slow channel). + * | | |06H = EADC_CH6 (slow channel). + * | | |07H = EADC_CH7 (slow channel). + * | | |08H = EADC_CH8 (slow channel). + * | | |09H = EADC_CH9 (slow channel). + * | | |0AH = EADC_CH10 (fast channel). + * | | |0BH = EADC_CH11 (fast channel). + * | | |0CH = EADC_CH12 (fast channel). + * | | |0DH = EADC_CH13 (fast channel). + * | | |0EH = EADC_CH14 (fast channel). + * | | |0FH = EADC_CH15 (fast channel). + * |[4] |EXTREN |ADC External Trigger Rising Edge Enable Bit + * | | |0 = Rising edge Disabled when ADC selects EADC0_ST as trigger source. + * | | |1 = Rising edge Enabled when ADC selects EADC0_ST as trigger source. + * |[5] |EXTFEN |ADC External Trigger Falling Edge Enable Bit + * | | |0 = Falling edge Disabled when ADC selects EADC0_ST as trigger source. + * | | |1 = Falling edge Enabled when ADC selects EADC0_ST as trigger source. + * |[7:6] |TRGDLYDIV |ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection + * | | |Trigger delay clock frequency: + * | | |00 = ADC_CLK/1. + * | | |01 = ADC_CLK/2. + * | | |10 = ADC_CLK/4. + * | | |11 = ADC_CLK/16. + * |[15:8] |TRGDLYCNT |ADC Sample Module Start of Conversion Trigger Delay Time + * | | |Trigger delay time = TRGDLYCNT x ADC_CLK x n (n=1,2,4,16 from TRGDLYDIV setting). + * |[20:16] |TRGSEL |ADC Sample Module Start of Conversion Trigger Source Selection + * | | |0H = Disable trigger. + * | | |1H = External trigger from EADC0_ST pin input. + * | | |2H = ADC ADINT0 interrupt EOC (End of conversion) pulse trigger. + * | | |3H = ADC ADINT1 interrupt EOC (End of conversion) pulse trigger. + * | | |4H = Timer0 overflow pulse trigger. + * | | |5H = Timer1 overflow pulse trigger. + * | | |6H = Timer2 overflow pulse trigger. + * | | |7H = Timer3 overflow pulse trigger. + * | | |8H = EPWM0TG0. + * | | |9H = EPWM0TG1. + * | | |AH = EPWM0TG2. + * | | |BH = EPWM0TG3. + * | | |CH = EPWM0TG4. + * | | |DH = EPWM0TG5. + * | | |EH = EPWM1TG0. + * | | |FH = EPWM1TG1. + * | | |10H = EPWM1TG2. + * | | |11H = EPWM1TG3. + * | | |12H = EPWM1TG4. + * | | |13H = EPWM1TG5. + * | | |14H = BPWM0TG. + * | | |15H = BPWM1TG. + * | | |other = Reserved. + * |[22] |INTPOS |Interrupt Flag Position Select + * | | |0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC end of conversion. + * | | |1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC start of conversion. + * |[23] |DBMEN |Double Buffer Mode Enable Bit + * | | |0 = Sample has one sample result register. (default). + * | | |1 = Sample has two sample result registers. + * |[31:24] |EXTSMPT |ADC Sampling Time Extend + * | | |When ADC converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend ADC sampling time after trigger source is coming to get enough sampling time. + * | | |The range of start delay time is from 0~255 ADC clock. + * @var EADC_T::INTSRC[4] + * Offset: 0xD0 ADC interrupt 0~3 Source Enable Control Register. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SPLIE0 |Sample Module 0 Interrupt Enable Bit + * | | |0 = Sample Module 0 interrupt Disabled. + * | | |1 = Sample Module 0 interrupt Enabled. + * |[1] |SPLIE1 |Sample Module 1 Interrupt Enable Bit + * | | |0 = Sample Module 1 interrupt Disabled. + * | | |1 = Sample Module 1 interrupt Enabled. + * |[2] |SPLIE2 |Sample Module 2 Interrupt Enable Bit + * | | |0 = Sample Module 2 interrupt Disabled. + * | | |1 = Sample Module 2 interrupt Enabled. + * |[3] |SPLIE3 |Sample Module 3 Interrupt Enable Bit + * | | |0 = Sample Module 3 interrupt Disabled. + * | | |1 = Sample Module 3 interrupt Enabled. + * |[4] |SPLIE4 |Sample Module 4 Interrupt Enable Bit + * | | |0 = Sample Module 4 interrupt Disabled. + * | | |1 = Sample Module 4 interrupt Enabled. + * |[5] |SPLIE5 |Sample Module 5 Interrupt Enable Bit + * | | |0 = Sample Module 5 interrupt Disabled. + * | | |1 = Sample Module 5 interrupt Enabled. + * |[6] |SPLIE6 |Sample Module 6 Interrupt Enable Bit + * | | |0 = Sample Module 6 interrupt Disabled. + * | | |1 = Sample Module 6 interrupt Enabled. + * |[7] |SPLIE7 |Sample Module 7 Interrupt Enable Bit + * | | |0 = Sample Module 7 interrupt Disabled. + * | | |1 = Sample Module 7 interrupt Enabled. + * |[8] |SPLIE8 |Sample Module 8 Interrupt Enable Bit + * | | |0 = Sample Module 8 interrupt Disabled. + * | | |1 = Sample Module 8 interrupt Enabled. + * |[9] |SPLIE9 |Sample Module 9 Interrupt Enable Bit + * | | |0 = Sample Module 9 interrupt Disabled. + * | | |1 = Sample Module 9 interrupt Enabled. + * |[10] |SPLIE10 |Sample Module 10 Interrupt Enable Bit + * | | |0 = Sample Module 10 interrupt Disabled. + * | | |1 = Sample Module 10 interrupt Enabled. + * |[11] |SPLIE11 |Sample Module 11 Interrupt Enable Bit + * | | |0 = Sample Module 11 interrupt Disabled. + * | | |1 = Sample Module 11 interrupt Enabled. + * |[12] |SPLIE12 |Sample Module 12 Interrupt Enable Bit + * | | |0 = Sample Module 12 interrupt Disabled. + * | | |1 = Sample Module 12 interrupt Enabled. + * |[13] |SPLIE13 |Sample Module 13 Interrupt Enable Bit + * | | |0 = Sample Module 13 interrupt Disabled. + * | | |1 = Sample Module 13 interrupt Enabled. + * |[14] |SPLIE14 |Sample Module 14 Interrupt Enable Bit + * | | |0 = Sample Module 14 interrupt Disabled. + * | | |1 = Sample Module 14 interrupt Enabled. + * |[15] |SPLIE15 |Sample Module 15 Interrupt Enable Bit + * | | |0 = Sample Module 15 interrupt Disabled. + * | | |1 = Sample Module 15 interrupt Enabled. + * |[16] |SPLIE16 |Sample Module 16 Interrupt Enable Bit + * | | |0 = Sample Module 16 interrupt Disabled. + * | | |1 = Sample Module 16 interrupt Enabled. + * |[17] |SPLIE17 |Sample Module 17 Interrupt Enable Bit + * | | |0 = Sample Module 17 interrupt Disabled. + * | | |1 = Sample Module 17 interrupt Enabled. + * |[18] |SPLIE18 |Sample Module 18 Interrupt Enable Bit + * | | |0 = Sample Module 18 interrupt Disabled. + * | | |1 = Sample Module 18 interrupt Enabled. + * @var EADC_T::CMP[4] + * Offset: 0xE0 ADC Result Compare Register 0~3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADCMPEN |ADC Result Compare Enable Bit + * | | |0 = Compare Disabled. + * | | |1 = Compare Enabled. + * | | |Set this bit to 1 to enable compare CMPDAT (EADC_CMPn[27:16], n=0~3) with specified sample module conversion result when converted data is loaded into EADC_DAT register. + * |[1] |ADCMPIE |ADC Result Compare Interrupt Enable Bit + * | | |0 = Compare function interrupt Disabled. + * | | |1 = Compare function interrupt Enabled. + * | | |If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated. + * |[2] |CMPCOND |Compare Condition + * | | |0= Set the compare condition as that when a 12-bit ADC conversion result is less than the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one. + * | | |1= Set the compare condition as that when a 12-bit ADC conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one. + * | | |Note: When the internal counter reaches the value to (CMPMCNT (EADC_CMPn[11:8], n=0~3) +1), the CMPF bit will be set. + * |[7:3] |CMPSPL |Compare Sample Module Selection + * | | |00000 = Sample Module 0 conversion result EADC_DAT0 is selected to be compared. + * | | |00001 = Sample Module 1 conversion result EADC_DAT1 is selected to be compared. + * | | |00010 = Sample Module 2 conversion result EADC_DAT2 is selected to be compared. + * | | |00011 = Sample Module 3 conversion result EADC_DAT3 is selected to be compared. + * | | |00100 = Sample Module 4 conversion result EADC_DAT4 is selected to be compared. + * | | |00101 = Sample Module 5 conversion result EADC_DAT5 is selected to be compared. + * | | |00110 = Sample Module 6 conversion result EADC_DAT6 is selected to be compared. + * | | |00111 = Sample Module 7 conversion result EADC_DAT7 is selected to be compared. + * | | |01000 = Sample Module 8 conversion result EADC_DAT8 is selected to be compared. + * | | |01001 = Sample Module 9 conversion result EADC_DAT9 is selected to be compared. + * | | |01010 = Sample Module 10 conversion result EADC_DAT10 is selected to be compared. + * | | |01011 = Sample Module 11 conversion result EADC_DAT11 is selected to be compared. + * | | |01100 = Sample Module 12 conversion result EADC_DAT12 is selected to be compared. + * | | |01101 = Sample Module 13 conversion result EADC_DAT13 is selected to be compared. + * | | |01110 = Sample Module 14 conversion result EADC_DAT14 is selected to be compared. + * | | |01111 = Sample Module 15 conversion result EADC_DAT15 is selected to be compared. + * | | |10000 = Sample Module 16 conversion result EADC_DAT16 is selected to be compared. + * | | |10001 = Sample Module 17 conversion result EADC_DAT17 is selected to be compared. + * | | |10010 = Sample Module 18 conversion result EADC_DAT18 is selected to be compared. + * |[11:8] |CMPMCNT |Compare Match Count + * | | |When the specified ADC sample module analog conversion result matches the compare condition defined by CMPCOND (EADC_CMPn[2], n=0~3), the internal match counter will increase 1 + * | | |If the compare result does not meet the compare condition, the internal compare match counter will reset to 0 + * | | |When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be set. + * |[15] |CMPWEN |Compare Window Mode Enable Bit + * | | |0 = ADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched + * | | |ADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched + * | | |1 = ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched + * | | |ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched. + * | | |Note: This bit is only present in EADC_CMP0 and EADC_CMP2 register. + * |[27:16] |CMPDAT |Comparison Data + * | | |The 12 bits data is used to compare with conversion result of specified sample module + * | | |User can use it to monitor the external analog input pin voltage transition without imposing a load on software. + * @var EADC_T::STATUS0 + * Offset: 0xF0 ADC Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |VALID |EADC_DAT0~15 Data Valid Flag + * | | |It is a mirror of VALID bit in sample module ADC result data register EADC_DATn. (n=0~18). + * |[31:16] |OV |EADC_DAT0~15 Overrun Flag + * | | |It is a mirror to OV bit in sample module ADC result data register EADC_DATn. (n=0~18). + * @var EADC_T::STATUS1 + * Offset: 0xF4 ADC Status Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |VALID |EADC_DAT16~18 Data Valid Flag + * | | |It is a mirror of VALID bit in sample module ADC result data register EADC_DATn. (n=0~18). + * |[18:16] |OV |EADC_DAT16~18 Overrun Flag + * | | |It is a mirror to OV bit in sample module ADC result data register EADC_DATn. (n=0~18). + * @var EADC_T::STATUS2 + * Offset: 0xF8 ADC Status Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADIF0 |ADC ADINT0 Interrupt Flag + * | | |0 = No ADINT0 interrupt pulse received. + * | | |1 = ADINT0 interrupt pulse has been received. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed + * |[1] |ADIF1 |ADC ADINT1 Interrupt Flag + * | | |0 = No ADINT1 interrupt pulse received. + * | | |1 = ADINT1 interrupt pulse has been received. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed + * |[2] |ADIF2 |ADC ADINT2 Interrupt Flag + * | | |0 = No ADINT2 interrupt pulse received. + * | | |1 = ADINT2 interrupt pulse has been received. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed + * |[3] |ADIF3 |ADC ADINT3 Interrupt Flag + * | | |0 = No ADINT3 interrupt pulse received. + * | | |1 = ADINT3 interrupt pulse has been received. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed + * |[4] |ADCMPF0 |ADC Compare 0 Flag + * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP0 then this bit is set to 1. + * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP0 register setting. + * | | |1 = Conversion result in EADC_DAT meets EADC_CMP0 register setting. + * | | |Note: This bit is cleared by writing 1 to it. + * |[5] |ADCMPF1 |ADC Compare 1 Flag + * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP1 then this bit is set to 1. + * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP1 register setting. + * | | |1 = Conversion result in EADC_DAT meets EADC_CMP1 register setting. + * | | |Note: This bit is cleared by writing 1 to it. + * |[6] |ADCMPF2 |ADC Compare 2 Flag + * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP2 then this bit is set to 1. + * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP2 register setting. + * | | |1 = Conversion result in EADC_DAT meets EADC_CMP2 register setting. + * | | |Note: This bit is cleared by writing 1 to it. + * |[7] |ADCMPF3 |ADC Compare 3 Flag + * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP3 then this bit is set to 1. + * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP3 register setting. + * | | |1 = Conversion result in EADC_DAT meets EADC_CMP3 register setting. + * | | |Note: This bit is cleared by writing 1 to it. + * |[8] |ADOVIF0 |ADC ADINT0 Interrupt Flag Overrun + * | | |0 = ADINT0 interrupt flag is not overwritten to 1. + * | | |1 = ADINT0 interrupt flag is overwritten to 1. + * | | |Note: This bit is cleared by writing 1 to it. + * |[9] |ADOVIF1 |ADC ADINT1 Interrupt Flag Overrun + * | | |0 = ADINT1 interrupt flag is not overwritten to 1. + * | | |1 = ADINT1 interrupt flag is overwritten to 1. + * | | |Note: This bit is cleared by writing 1 to it. + * |[10] |ADOVIF2 |ADC ADINT2 Interrupt Flag Overrun + * | | |0 = ADINT2 interrupt flag is not overwritten to 1. + * | | |1 = ADINT2 interrupt flag is s overwritten to 1. + * | | |Note: This bit is cleared by writing 1 to it. + * |[11] |ADOVIF3 |ADC ADINT3 Interrupt Flag Overrun + * | | |0 = ADINT3 interrupt flag is not overwritten to 1. + * | | |1 = ADINT3 interrupt flag is overwritten to 1. + * | | |Note: This bit is cleared by writing 1 to it. + * |[12] |ADCMPO0 |ADC Compare 0 Output Status (Read Only) + * | | |The 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module + * | | |User can use it to monitor the external analog input pin voltage status. + * | | |0 = Conversion result in EADC_DAT less than CMPDAT0 setting. + * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT0 setting. + * |[13] |ADCMPO1 |ADC Compare 1 Output Status (Read Only) + * | | |The 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module + * | | |User can use it to monitor the external analog input pin voltage status. + * | | |0 = Conversion result in EADC_DAT less than CMPDAT1 setting. + * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT1 setting. + * |[14] |ADCMPO2 |ADC Compare 2 Output Status (Read Only) + * | | |The 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module + * | | |User can use it to monitor the external analog input pin voltage status. + * | | |0 = Conversion result in EADC_DAT less than CMPDAT2 setting. + * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT2 setting. + * |[15] |ADCMPO3 |ADC Compare 3 Output Status (Read Only) + * | | |The 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module + * | | |User can use it to monitor the external analog input pin voltage status. + * | | |0 = Conversion result in EADC_DAT less than CMPDAT3 setting. + * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT3 setting. + * |[20:16] |CHANNEL |Current Conversion Channel (Read Only) + * | | |This filed reflects ADC current conversion channel when BUSY=1. + * | | |It is read only. + * | | |00H = EADC_CH0. + * | | |01H = EADC_CH1. + * | | |02H = EADC_CH2. + * | | |03H = EADC_CH3. + * | | |04H = EADC_CH4. + * | | |05H = EADC_CH5. + * | | |06H = EADC_CH6. + * | | |07H = EADC_CH7. + * | | |08H = EADC_CH8. + * | | |09H = EADC_CH9. + * | | |0AH = EADC_CH10. + * | | |0BH = EADC_CH11. + * | | |0CH = EADC_CH12. + * | | |0DH = EADC_CH13. + * | | |0EH = EADC_CH14. + * | | |0FH = EADC_CH15. + * | | |10H = VBG. + * | | |11H = VTEMP. + * | | |12H = VBAT/4. + * |[23] |BUSY |Busy/Idle (Read Only) + * | | |0 = EADC is in idle state. + * | | |1 = EADC is busy at conversion. + * |[24] |ADOVIF |All ADC Interrupt Flag Overrun Bits Check (Read Only) + * | | |n=0~3. + * | | |0 = None of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1. + * | | |1 = Any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1. + * | | |Note: This bit will keep 1 when any ADOVIFn Flag is equal to 1. + * |[25] |STOVF |for All ADC Sample Module Start of Conversion Overrun Flags Check (Read Only) + * | | |n=0~18. + * | | |0 = None of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1. + * | | |1 = Any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1. + * | | |Note: This bit will keep 1 when any SPOVFn Flag is equal to 1. + * |[26] |AVALID |for All Sample Module ADC Result Data Register EADC_DAT Data Valid Flag Check (Read Only) + * | | |n=0~18. + * | | |0 = None of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1. + * | | |1 = Any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1. + * | | |Note: This bit will keep 1 when any VALIDn Flag is equal to 1. + * |[27] |AOV |for All Sample Module ADC Result Data Register Overrun Flags Check (Read Only) + * | | |n=0~18. + * | | |0 = None of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1. + * | | |1 = Any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1. + * | | |Note: This bit will keep 1 when any OVn Flag is equal to 1. + * @var EADC_T::STATUS3 + * Offset: 0xFC ADC Status Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |CURSPL |ADC Current Sample Module + * | | |This register show the current ADC is controlled by which sample module control logic modules. + * | | |If the ADC is Idle, this bit filed will set to 0x1F. + * | | |This is a read only register. + * @var EADC_T::DDAT[4] + * Offset: 0x100 ADC Double Data Register 0 for Sample Module 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RESULT |ADC Conversion Results + * | | |This field contains 12 bits conversion results. + * | | |When the DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12]. + * | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT [11:0] and signed bits to will be filled in RESULT [15:12]. + * |[16] |OV |Overrun Flag + * | | |0 = Data in RESULT (EADC_DATn[15:0], n=0~3) is recent conversion result. + * | | |1 = Data in RESULT (EADC_DATn[15:0], n=0~3) is overwrite. + * | | |If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1 + * | | |It is cleared by hardware after EADC_DDAT register is read. + * |[17] |VALID |Valid Flag + * | | |0 = Double data in RESULT (EADC_DDATn[15:0]) is not valid. + * | | |1 = Double data in RESULT (EADC_DDATn[15:0]) is valid. + * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DDATn register is read + * | | |(n=0~3). + * @var EADC_T::PWRM + * Offset: 0x110 ADC Power Management Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PWUPRDY |ADC Power-up Sequence Completed and Ready for Conversion (Read Only) + * | | |0 = ADC is not ready for conversion may be in power down state or in the progress of start up. + * | | |1 = ADC is ready for conversion. + * |[1] |PWUCALEN |Power Up Calibration Function Enable Control + * | | |0 = Disable the function of calibration at power up. + * | | |1 = Enable the function of calibration at power up. + * | | |Note: This bit work together with CALSEL (EADC_CALCTL [3]), see the following + * | | |{PWUCALEN, CALSEL } Description: + * | | |PWUCALEN is 0 and CALSEL is 0: No need to calibrate. + * | | |PWUCALEN is 0 and CALSEL is 1: No need to calibrate. + * | | |PWUCALEN is 1 and CALSEL is 0: Load calibration word when power up. + * | | |PWUCALEN is 1 and CALSEL is 1: Calibrate when power up. + * |[3:2] |PWDMOD |ADC Power-down Mode + * | | |Set this bit fields to select ADC power down mode when system power-down. + * | | |00 = ADC Deep power down mode. + * | | |01 = ADC Power down. + * | | |10 = ADC Standby mode. + * | | |11 = ADC Deep power down mode. + * | | |Note: Different PWDMOD has different power down/up sequence, in order to avoid ADC powering up with wrong sequence; user must keep PWMOD consistent each time in power down and start up + * |[19:8] |LDOSUT |ADC Internal LDO Start-up Time + * | | |Set this bit fields to control LDO start-up time + * | | |The minimum required LDO start-up time is 20us + * | | |LDO start-up time = (1/ADC_CLK) x LDOSUT. + * @var EADC_T::CALCTL + * Offset: 0x114 ADC Calibration Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |CALSTART |Calibration Functional Block Start + * | | |0 = Stops calibration functional block. + * | | |1 = Starts calibration functional block. + * | | |Note: This bit is set by SW and clear by HW after re-calibration finish + * |[2] |CALDONE |Calibration Functional Block Complete (Read Only) + * | | |0 = During a calibration. + * | | |1 = Calibration is completed. + * |[3] |CALSEL |Select Calibration Functional Block + * | | |0 = Load calibration word when calibration functional block is active. + * | | |1 = Execute calibration when calibration functional block is active. + * @var EADC_T::CALDWRD + * Offset: 0x118 ADC Calibration Load Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |CALWORD |Calibration Word Bits + * | | |Write to this register with the previous calibration word before load calibration action. + * | | |Read this register after calibration done. + * | | |Note: The calibration block contains two parts CALIBRATION and LOAD CALIBRATION; if the calibration block configure as CALIBRATION; then this register represent the result of calibration when calibration is completed; if configure as LOAD CALIBRATION ; configure this register before loading calibration action, after loading calibration complete, the laoded calibration word will apply to the ADC; while in loading calibration function the loaded value will not be equal to the original CALWORD until calibration is done. + */ + __I uint32_t DAT[19]; /*!< [0x0000] ADC Data Register 0~18 for Sample Module 0~18 */ + __I uint32_t CURDAT; /*!< [0x004c] ADC PDMA Current Transfer Data Register */ + __IO uint32_t CTL; /*!< [0x0050] ADC Control Register */ + __O uint32_t SWTRG; /*!< [0x0054] ADC Sample Module Software Start Register */ + __IO uint32_t PENDSTS; /*!< [0x0058] ADC Start of Conversion Pending Flag Register */ + __IO uint32_t OVSTS; /*!< [0x005c] ADC Sample Module Start of Conversion Overrun Flag Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[8]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t SCTL[19]; /*!< [0x0080] ADC Sample Module 0~18 Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t INTSRC[4]; /*!< [0x00d0] ADC interrupt 0~3 Source Enable Control Register. */ + __IO uint32_t CMP[4]; /*!< [0x00e0] ADC Result Compare Register 0~3 */ + __I uint32_t STATUS0; /*!< [0x00f0] ADC Status Register 0 */ + __I uint32_t STATUS1; /*!< [0x00f4] ADC Status Register 1 */ + __IO uint32_t STATUS2; /*!< [0x00f8] ADC Status Register 2 */ + __I uint32_t STATUS3; /*!< [0x00fc] ADC Status Register 3 */ + __I uint32_t DDAT[4]; /*!< [0x0100] ADC Double Data Register 0~3 for Sample Module 0~3 */ + __IO uint32_t PWRM; /*!< [0x0110] ADC Power Management Register */ + __IO uint32_t CALCTL; /*!< [0x0114] ADC Calibration Control Register */ + __IO uint32_t CALDWRD; /*!< [0x0118] ADC Calibration Load Word Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[5]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t PDMACTL; /*!< [0x0130] ADC PDMA Control Register */ +} EADC_T; + +/** + @addtogroup EADC_CONST EADC Bit Field Definition + Constant Definitions for EADC Controller +@{ */ + +#define EADC_DAT_RESULT_Pos (0) /*!< EADC_T::DAT: RESULT Position */ +#define EADC_DAT_RESULT_Msk (0xfffful << EADC_DAT_RESULT_Pos) /*!< EADC_T::DAT: RESULT Mask */ + +#define EADC_DAT_OV_Pos (16) /*!< EADC_T::DAT: OV Position */ +#define EADC_DAT_OV_Msk (0x1ul << EADC_DAT_OV_Pos) /*!< EADC_T::DAT: OV Mask */ + +#define EADC_DAT_VALID_Pos (17) /*!< EADC_T::DAT: VALID Position */ +#define EADC_DAT_VALID_Msk (0x1ul << EADC_DAT_VALID_Pos) /*!< EADC_T::DAT: VALID Mask */ + +#define EADC_DAT0_RESULT_Pos (0) /*!< EADC_T::DAT0: RESULT Position */ +#define EADC_DAT0_RESULT_Msk (0xfffful << EADC_DAT0_RESULT_Pos) /*!< EADC_T::DAT0: RESULT Mask */ + +#define EADC_DAT0_OV_Pos (16) /*!< EADC_T::DAT0: OV Position */ +#define EADC_DAT0_OV_Msk (0x1ul << EADC_DAT0_OV_Pos) /*!< EADC_T::DAT0: OV Mask */ + +#define EADC_DAT0_VALID_Pos (17) /*!< EADC_T::DAT0: VALID Position */ +#define EADC_DAT0_VALID_Msk (0x1ul << EADC_DAT0_VALID_Pos) /*!< EADC_T::DAT0: VALID Mask */ + +#define EADC_DAT1_RESULT_Pos (0) /*!< EADC_T::DAT1: RESULT Position */ +#define EADC_DAT1_RESULT_Msk (0xfffful << EADC_DAT1_RESULT_Pos) /*!< EADC_T::DAT1: RESULT Mask */ + +#define EADC_DAT1_OV_Pos (16) /*!< EADC_T::DAT1: OV Position */ +#define EADC_DAT1_OV_Msk (0x1ul << EADC_DAT1_OV_Pos) /*!< EADC_T::DAT1: OV Mask */ + +#define EADC_DAT1_VALID_Pos (17) /*!< EADC_T::DAT1: VALID Position */ +#define EADC_DAT1_VALID_Msk (0x1ul << EADC_DAT1_VALID_Pos) /*!< EADC_T::DAT1: VALID Mask */ + +#define EADC_DAT2_RESULT_Pos (0) /*!< EADC_T::DAT2: RESULT Position */ +#define EADC_DAT2_RESULT_Msk (0xfffful << EADC_DAT2_RESULT_Pos) /*!< EADC_T::DAT2: RESULT Mask */ + +#define EADC_DAT2_OV_Pos (16) /*!< EADC_T::DAT2: OV Position */ +#define EADC_DAT2_OV_Msk (0x1ul << EADC_DAT2_OV_Pos) /*!< EADC_T::DAT2: OV Mask */ + +#define EADC_DAT2_VALID_Pos (17) /*!< EADC_T::DAT2: VALID Position */ +#define EADC_DAT2_VALID_Msk (0x1ul << EADC_DAT2_VALID_Pos) /*!< EADC_T::DAT2: VALID Mask */ + +#define EADC_DAT3_RESULT_Pos (0) /*!< EADC_T::DAT3: RESULT Position */ +#define EADC_DAT3_RESULT_Msk (0xfffful << EADC_DAT3_RESULT_Pos) /*!< EADC_T::DAT3: RESULT Mask */ + +#define EADC_DAT3_OV_Pos (16) /*!< EADC_T::DAT3: OV Position */ +#define EADC_DAT3_OV_Msk (0x1ul << EADC_DAT3_OV_Pos) /*!< EADC_T::DAT3: OV Mask */ + +#define EADC_DAT3_VALID_Pos (17) /*!< EADC_T::DAT3: VALID Position */ +#define EADC_DAT3_VALID_Msk (0x1ul << EADC_DAT3_VALID_Pos) /*!< EADC_T::DAT3: VALID Mask */ + +#define EADC_DAT4_RESULT_Pos (0) /*!< EADC_T::DAT4: RESULT Position */ +#define EADC_DAT4_RESULT_Msk (0xfffful << EADC_DAT4_RESULT_Pos) /*!< EADC_T::DAT4: RESULT Mask */ + +#define EADC_DAT4_OV_Pos (16) /*!< EADC_T::DAT4: OV Position */ +#define EADC_DAT4_OV_Msk (0x1ul << EADC_DAT4_OV_Pos) /*!< EADC_T::DAT4: OV Mask */ + +#define EADC_DAT4_VALID_Pos (17) /*!< EADC_T::DAT4: VALID Position */ +#define EADC_DAT4_VALID_Msk (0x1ul << EADC_DAT4_VALID_Pos) /*!< EADC_T::DAT4: VALID Mask */ + +#define EADC_DAT5_RESULT_Pos (0) /*!< EADC_T::DAT5: RESULT Position */ +#define EADC_DAT5_RESULT_Msk (0xfffful << EADC_DAT5_RESULT_Pos) /*!< EADC_T::DAT5: RESULT Mask */ + +#define EADC_DAT5_OV_Pos (16) /*!< EADC_T::DAT5: OV Position */ +#define EADC_DAT5_OV_Msk (0x1ul << EADC_DAT5_OV_Pos) /*!< EADC_T::DAT5: OV Mask */ + +#define EADC_DAT5_VALID_Pos (17) /*!< EADC_T::DAT5: VALID Position */ +#define EADC_DAT5_VALID_Msk (0x1ul << EADC_DAT5_VALID_Pos) /*!< EADC_T::DAT5: VALID Mask */ + +#define EADC_DAT6_RESULT_Pos (0) /*!< EADC_T::DAT6: RESULT Position */ +#define EADC_DAT6_RESULT_Msk (0xfffful << EADC_DAT6_RESULT_Pos) /*!< EADC_T::DAT6: RESULT Mask */ + +#define EADC_DAT6_OV_Pos (16) /*!< EADC_T::DAT6: OV Position */ +#define EADC_DAT6_OV_Msk (0x1ul << EADC_DAT6_OV_Pos) /*!< EADC_T::DAT6: OV Mask */ + +#define EADC_DAT6_VALID_Pos (17) /*!< EADC_T::DAT6: VALID Position */ +#define EADC_DAT6_VALID_Msk (0x1ul << EADC_DAT6_VALID_Pos) /*!< EADC_T::DAT6: VALID Mask */ + +#define EADC_DAT7_RESULT_Pos (0) /*!< EADC_T::DAT7: RESULT Position */ +#define EADC_DAT7_RESULT_Msk (0xfffful << EADC_DAT7_RESULT_Pos) /*!< EADC_T::DAT7: RESULT Mask */ + +#define EADC_DAT7_OV_Pos (16) /*!< EADC_T::DAT7: OV Position */ +#define EADC_DAT7_OV_Msk (0x1ul << EADC_DAT7_OV_Pos) /*!< EADC_T::DAT7: OV Mask */ + +#define EADC_DAT7_VALID_Pos (17) /*!< EADC_T::DAT7: VALID Position */ +#define EADC_DAT7_VALID_Msk (0x1ul << EADC_DAT7_VALID_Pos) /*!< EADC_T::DAT7: VALID Mask */ + +#define EADC_DAT8_RESULT_Pos (0) /*!< EADC_T::DAT8: RESULT Position */ +#define EADC_DAT8_RESULT_Msk (0xfffful << EADC_DAT8_RESULT_Pos) /*!< EADC_T::DAT8: RESULT Mask */ + +#define EADC_DAT8_OV_Pos (16) /*!< EADC_T::DAT8: OV Position */ +#define EADC_DAT8_OV_Msk (0x1ul << EADC_DAT8_OV_Pos) /*!< EADC_T::DAT8: OV Mask */ + +#define EADC_DAT8_VALID_Pos (17) /*!< EADC_T::DAT8: VALID Position */ +#define EADC_DAT8_VALID_Msk (0x1ul << EADC_DAT8_VALID_Pos) /*!< EADC_T::DAT8: VALID Mask */ + +#define EADC_DAT9_RESULT_Pos (0) /*!< EADC_T::DAT9: RESULT Position */ +#define EADC_DAT9_RESULT_Msk (0xfffful << EADC_DAT9_RESULT_Pos) /*!< EADC_T::DAT9: RESULT Mask */ + +#define EADC_DAT9_OV_Pos (16) /*!< EADC_T::DAT9: OV Position */ +#define EADC_DAT9_OV_Msk (0x1ul << EADC_DAT9_OV_Pos) /*!< EADC_T::DAT9: OV Mask */ + +#define EADC_DAT9_VALID_Pos (17) /*!< EADC_T::DAT9: VALID Position */ +#define EADC_DAT9_VALID_Msk (0x1ul << EADC_DAT9_VALID_Pos) /*!< EADC_T::DAT9: VALID Mask */ + +#define EADC_DAT10_RESULT_Pos (0) /*!< EADC_T::DAT10: RESULT Position */ +#define EADC_DAT10_RESULT_Msk (0xfffful << EADC_DAT10_RESULT_Pos) /*!< EADC_T::DAT10: RESULT Mask */ + +#define EADC_DAT10_OV_Pos (16) /*!< EADC_T::DAT10: OV Position */ +#define EADC_DAT10_OV_Msk (0x1ul << EADC_DAT10_OV_Pos) /*!< EADC_T::DAT10: OV Mask */ + +#define EADC_DAT10_VALID_Pos (17) /*!< EADC_T::DAT10: VALID Position */ +#define EADC_DAT10_VALID_Msk (0x1ul << EADC_DAT10_VALID_Pos) /*!< EADC_T::DAT10: VALID Mask */ + +#define EADC_DAT11_RESULT_Pos (0) /*!< EADC_T::DAT11: RESULT Position */ +#define EADC_DAT11_RESULT_Msk (0xfffful << EADC_DAT11_RESULT_Pos) /*!< EADC_T::DAT11: RESULT Mask */ + +#define EADC_DAT11_OV_Pos (16) /*!< EADC_T::DAT11: OV Position */ +#define EADC_DAT11_OV_Msk (0x1ul << EADC_DAT11_OV_Pos) /*!< EADC_T::DAT11: OV Mask */ + +#define EADC_DAT11_VALID_Pos (17) /*!< EADC_T::DAT11: VALID Position */ +#define EADC_DAT11_VALID_Msk (0x1ul << EADC_DAT11_VALID_Pos) /*!< EADC_T::DAT11: VALID Mask */ + +#define EADC_DAT12_RESULT_Pos (0) /*!< EADC_T::DAT12: RESULT Position */ +#define EADC_DAT12_RESULT_Msk (0xfffful << EADC_DAT12_RESULT_Pos) /*!< EADC_T::DAT12: RESULT Mask */ + +#define EADC_DAT12_OV_Pos (16) /*!< EADC_T::DAT12: OV Position */ +#define EADC_DAT12_OV_Msk (0x1ul << EADC_DAT12_OV_Pos) /*!< EADC_T::DAT12: OV Mask */ + +#define EADC_DAT12_VALID_Pos (17) /*!< EADC_T::DAT12: VALID Position */ +#define EADC_DAT12_VALID_Msk (0x1ul << EADC_DAT12_VALID_Pos) /*!< EADC_T::DAT12: VALID Mask */ + +#define EADC_DAT13_RESULT_Pos (0) /*!< EADC_T::DAT13: RESULT Position */ +#define EADC_DAT13_RESULT_Msk (0xfffful << EADC_DAT13_RESULT_Pos) /*!< EADC_T::DAT13: RESULT Mask */ + +#define EADC_DAT13_OV_Pos (16) /*!< EADC_T::DAT13: OV Position */ +#define EADC_DAT13_OV_Msk (0x1ul << EADC_DAT13_OV_Pos) /*!< EADC_T::DAT13: OV Mask */ + +#define EADC_DAT13_VALID_Pos (17) /*!< EADC_T::DAT13: VALID Position */ +#define EADC_DAT13_VALID_Msk (0x1ul << EADC_DAT13_VALID_Pos) /*!< EADC_T::DAT13: VALID Mask */ + +#define EADC_DAT14_RESULT_Pos (0) /*!< EADC_T::DAT14: RESULT Position */ +#define EADC_DAT14_RESULT_Msk (0xfffful << EADC_DAT14_RESULT_Pos) /*!< EADC_T::DAT14: RESULT Mask */ + +#define EADC_DAT14_OV_Pos (16) /*!< EADC_T::DAT14: OV Position */ +#define EADC_DAT14_OV_Msk (0x1ul << EADC_DAT14_OV_Pos) /*!< EADC_T::DAT14: OV Mask */ + +#define EADC_DAT14_VALID_Pos (17) /*!< EADC_T::DAT14: VALID Position */ +#define EADC_DAT14_VALID_Msk (0x1ul << EADC_DAT14_VALID_Pos) /*!< EADC_T::DAT14: VALID Mask */ + +#define EADC_DAT15_RESULT_Pos (0) /*!< EADC_T::DAT15: RESULT Position */ +#define EADC_DAT15_RESULT_Msk (0xfffful << EADC_DAT15_RESULT_Pos) /*!< EADC_T::DAT15: RESULT Mask */ + +#define EADC_DAT15_OV_Pos (16) /*!< EADC_T::DAT15: OV Position */ +#define EADC_DAT15_OV_Msk (0x1ul << EADC_DAT15_OV_Pos) /*!< EADC_T::DAT15: OV Mask */ + +#define EADC_DAT15_VALID_Pos (17) /*!< EADC_T::DAT15: VALID Position */ +#define EADC_DAT15_VALID_Msk (0x1ul << EADC_DAT15_VALID_Pos) /*!< EADC_T::DAT15: VALID Mask */ + +#define EADC_DAT16_RESULT_Pos (0) /*!< EADC_T::DAT16: RESULT Position */ +#define EADC_DAT16_RESULT_Msk (0xfffful << EADC_DAT16_RESULT_Pos) /*!< EADC_T::DAT16: RESULT Mask */ + +#define EADC_DAT16_OV_Pos (16) /*!< EADC_T::DAT16: OV Position */ +#define EADC_DAT16_OV_Msk (0x1ul << EADC_DAT16_OV_Pos) /*!< EADC_T::DAT16: OV Mask */ + +#define EADC_DAT16_VALID_Pos (17) /*!< EADC_T::DAT16: VALID Position */ +#define EADC_DAT16_VALID_Msk (0x1ul << EADC_DAT16_VALID_Pos) /*!< EADC_T::DAT16: VALID Mask */ + +#define EADC_DAT17_RESULT_Pos (0) /*!< EADC_T::DAT17: RESULT Position */ +#define EADC_DAT17_RESULT_Msk (0xfffful << EADC_DAT17_RESULT_Pos) /*!< EADC_T::DAT17: RESULT Mask */ + +#define EADC_DAT17_OV_Pos (16) /*!< EADC_T::DAT17: OV Position */ +#define EADC_DAT17_OV_Msk (0x1ul << EADC_DAT17_OV_Pos) /*!< EADC_T::DAT17: OV Mask */ + +#define EADC_DAT17_VALID_Pos (17) /*!< EADC_T::DAT17: VALID Position */ +#define EADC_DAT17_VALID_Msk (0x1ul << EADC_DAT17_VALID_Pos) /*!< EADC_T::DAT17: VALID Mask */ + +#define EADC_DAT18_RESULT_Pos (0) /*!< EADC_T::DAT18: RESULT Position */ +#define EADC_DAT18_RESULT_Msk (0xfffful << EADC_DAT18_RESULT_Pos) /*!< EADC_T::DAT18: RESULT Mask */ + +#define EADC_DAT18_OV_Pos (16) /*!< EADC_T::DAT18: OV Position */ +#define EADC_DAT18_OV_Msk (0x1ul << EADC_DAT18_OV_Pos) /*!< EADC_T::DAT18: OV Mask */ + +#define EADC_DAT18_VALID_Pos (17) /*!< EADC_T::DAT18: VALID Position */ +#define EADC_DAT18_VALID_Msk (0x1ul << EADC_DAT18_VALID_Pos) /*!< EADC_T::DAT18: VALID Mask */ + +#define EADC_CURDAT_CURDAT_Pos (0) /*!< EADC_T::CURDAT: CURDAT Position */ +#define EADC_CURDAT_CURDAT_Msk (0x3fffful << EADC_CURDAT_CURDAT_Pos) /*!< EADC_T::CURDAT: CURDAT Mask */ + +#define EADC_CTL_ADCEN_Pos (0) /*!< EADC_T::CTL: ADCEN Position */ +#define EADC_CTL_ADCEN_Msk (0x1ul << EADC_CTL_ADCEN_Pos) /*!< EADC_T::CTL: ADCEN Mask */ + +#define EADC_CTL_ADCRST_Pos (1) /*!< EADC_T::CTL: ADCRST Position */ +#define EADC_CTL_ADCRST_Msk (0x1ul << EADC_CTL_ADCRST_Pos) /*!< EADC_T::CTL: ADCRST Mask */ + +#define EADC_CTL_ADCIEN0_Pos (2) /*!< EADC_T::CTL: ADCIEN0 Position */ +#define EADC_CTL_ADCIEN0_Msk (0x1ul << EADC_CTL_ADCIEN0_Pos) /*!< EADC_T::CTL: ADCIEN0 Mask */ + +#define EADC_CTL_ADCIEN1_Pos (3) /*!< EADC_T::CTL: ADCIEN1 Position */ +#define EADC_CTL_ADCIEN1_Msk (0x1ul << EADC_CTL_ADCIEN1_Pos) /*!< EADC_T::CTL: ADCIEN1 Mask */ + +#define EADC_CTL_ADCIEN2_Pos (4) /*!< EADC_T::CTL: ADCIEN2 Position */ +#define EADC_CTL_ADCIEN2_Msk (0x1ul << EADC_CTL_ADCIEN2_Pos) /*!< EADC_T::CTL: ADCIEN2 Mask */ + +#define EADC_CTL_ADCIEN3_Pos (5) /*!< EADC_T::CTL: ADCIEN3 Position */ +#define EADC_CTL_ADCIEN3_Msk (0x1ul << EADC_CTL_ADCIEN3_Pos) /*!< EADC_T::CTL: ADCIEN3 Mask */ + +#define EADC_CTL_RESSEL_Pos (6) /*!< EADC_T::CTL: RESSEL Position */ +#define EADC_CTL_RESSEL_Msk (0x3ul << EADC_CTL_RESSEL_Pos) /*!< EADC_T::CTL: RESSEL Mask */ + +#define EADC_CTL_DIFFEN_Pos (8) /*!< EADC_T::CTL: DIFFEN Position */ +#define EADC_CTL_DIFFEN_Msk (0x1ul << EADC_CTL_DIFFEN_Pos) /*!< EADC_T::CTL: DIFFEN Mask */ + +#define EADC_CTL_DMOF_Pos (9) /*!< EADC_T::CTL: DMOF Position */ +#define EADC_CTL_DMOF_Msk (0x1ul << EADC_CTL_DMOF_Pos) /*!< EADC_T::CTL: DMOF Mask */ + +#define EADC_CTL_PDMAEN_Pos (11) /*!< EADC_T::CTL: PDMAEN Position */ +#define EADC_CTL_PDMAEN_Msk (0x1ul << EADC_CTL_PDMAEN_Pos) /*!< EADC_T::CTL: PDMAEN Mask */ + +#define EADC_SWTRG_SWTRG_Pos (0) /*!< EADC_T::SWTRG: SWTRG Position */ +#define EADC_SWTRG_SWTRG_Msk (0x7fffful << EADC_SWTRG_SWTRG_Pos) /*!< EADC_T::SWTRG: SWTRG Mask */ + +#define EADC_PENDSTS_STPF_Pos (0) /*!< EADC_T::PENDSTS: STPF Position */ +#define EADC_PENDSTS_STPF_Msk (0x7fffful << EADC_PENDSTS_STPF_Pos) /*!< EADC_T::PENDSTS: STPF Mask */ + +#define EADC_OVSTS_SPOVF_Pos (0) /*!< EADC_T::OVSTS: SPOVF Position */ +#define EADC_OVSTS_SPOVF_Msk (0x7fffful << EADC_OVSTS_SPOVF_Pos) /*!< EADC_T::OVSTS: SPOVF Mask */ + +#define EADC_SCTL_CHSEL_Pos (0) /*!< EADC_T::SCTL: CHSEL Position */ +#define EADC_SCTL_CHSEL_Msk (0xful << EADC_SCTL_CHSEL_Pos) /*!< EADC_T::SCTL: CHSEL Mask */ + +#define EADC_SCTL_EXTREN_Pos (4) /*!< EADC_T::SCTL: EXTREN Position */ +#define EADC_SCTL_EXTREN_Msk (0x1ul << EADC_SCTL_EXTREN_Pos) /*!< EADC_T::SCTL: EXTREN Mask */ + +#define EADC_SCTL_EXTFEN_Pos (5) /*!< EADC_T::SCTL: EXTFEN Position */ +#define EADC_SCTL_EXTFEN_Msk (0x1ul << EADC_SCTL_EXTFEN_Pos) /*!< EADC_T::SCTL: EXTFEN Mask */ + +#define EADC_SCTL_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL: TRGDLYDIV Position */ +#define EADC_SCTL_TRGDLYDIV_Msk (0x3ul << EADC_SCTL_TRGDLYDIV_Pos) /*!< EADC_T::SCTL: TRGDLYDIV Mask */ + +#define EADC_SCTL_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL: TRGDLYCNT Position */ +#define EADC_SCTL_TRGDLYCNT_Msk (0xfful << EADC_SCTL_TRGDLYCNT_Pos) /*!< EADC_T::SCTL: TRGDLYCNT Mask */ + +#define EADC_SCTL_TRGSEL_Pos (16) /*!< EADC_T::SCTL: TRGSEL Position */ +#define EADC_SCTL_TRGSEL_Msk (0x1ful << EADC_SCTL_TRGSEL_Pos) /*!< EADC_T::SCTL: TRGSEL Mask */ + +#define EADC_SCTL_INTPOS_Pos (22) /*!< EADC_T::SCTL: INTPOS Position */ +#define EADC_SCTL_INTPOS_Msk (0x1ul << EADC_SCTL_INTPOS_Pos) /*!< EADC_T::SCTL: INTPOS Mask */ + +#define EADC_SCTL_DBMEN_Pos (23) /*!< EADC_T::SCTL: DBMEN Position */ +#define EADC_SCTL_DBMEN_Msk (0x1ul << EADC_SCTL_DBMEN_Pos) /*!< EADC_T::SCTL: DBMEN Mask */ + +#define EADC_SCTL_EXTSMPT_Pos (24) /*!< EADC_T::SCTL: EXTSMPT Position */ +#define EADC_SCTL_EXTSMPT_Msk (0xfful << EADC_SCTL_EXTSMPT_Pos) /*!< EADC_T::SCTL: EXTSMPT Mask */ + +#define EADC_SCTL0_CHSEL_Pos (0) /*!< EADC_T::SCTL0: CHSEL Position */ +#define EADC_SCTL0_CHSEL_Msk (0xful << EADC_SCTL0_CHSEL_Pos) /*!< EADC_T::SCTL0: CHSEL Mask */ + +#define EADC_SCTL0_EXTREN_Pos (4) /*!< EADC_T::SCTL0: EXTREN Position */ +#define EADC_SCTL0_EXTREN_Msk (0x1ul << EADC_SCTL0_EXTREN_Pos) /*!< EADC_T::SCTL0: EXTREN Mask */ + +#define EADC_SCTL0_EXTFEN_Pos (5) /*!< EADC_T::SCTL0: EXTFEN Position */ +#define EADC_SCTL0_EXTFEN_Msk (0x1ul << EADC_SCTL0_EXTFEN_Pos) /*!< EADC_T::SCTL0: EXTFEN Mask */ + +#define EADC_SCTL0_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL0: TRGDLYDIV Position */ +#define EADC_SCTL0_TRGDLYDIV_Msk (0x3ul << EADC_SCTL0_TRGDLYDIV_Pos) /*!< EADC_T::SCTL0: TRGDLYDIV Mask */ + +#define EADC_SCTL0_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL0: TRGDLYCNT Position */ +#define EADC_SCTL0_TRGDLYCNT_Msk (0xfful << EADC_SCTL0_TRGDLYCNT_Pos) /*!< EADC_T::SCTL0: TRGDLYCNT Mask */ + +#define EADC_SCTL0_TRGSEL_Pos (16) /*!< EADC_T::SCTL0: TRGSEL Position */ +#define EADC_SCTL0_TRGSEL_Msk (0x1ful << EADC_SCTL0_TRGSEL_Pos) /*!< EADC_T::SCTL0: TRGSEL Mask */ + +#define EADC_SCTL0_INTPOS_Pos (22) /*!< EADC_T::SCTL0: INTPOS Position */ +#define EADC_SCTL0_INTPOS_Msk (0x1ul << EADC_SCTL0_INTPOS_Pos) /*!< EADC_T::SCTL0: INTPOS Mask */ + +#define EADC_SCTL0_DBMEN_Pos (23) /*!< EADC_T::SCTL0: DBMEN Position */ +#define EADC_SCTL0_DBMEN_Msk (0x1ul << EADC_SCTL0_DBMEN_Pos) /*!< EADC_T::SCTL0: DBMEN Mask */ + +#define EADC_SCTL0_EXTSMPT_Pos (24) /*!< EADC_T::SCTL0: EXTSMPT Position */ +#define EADC_SCTL0_EXTSMPT_Msk (0xfful << EADC_SCTL0_EXTSMPT_Pos) /*!< EADC_T::SCTL0: EXTSMPT Mask */ + +#define EADC_SCTL1_CHSEL_Pos (0) /*!< EADC_T::SCTL1: CHSEL Position */ +#define EADC_SCTL1_CHSEL_Msk (0xful << EADC_SCTL1_CHSEL_Pos) /*!< EADC_T::SCTL1: CHSEL Mask */ + +#define EADC_SCTL1_EXTREN_Pos (4) /*!< EADC_T::SCTL1: EXTREN Position */ +#define EADC_SCTL1_EXTREN_Msk (0x1ul << EADC_SCTL1_EXTREN_Pos) /*!< EADC_T::SCTL1: EXTREN Mask */ + +#define EADC_SCTL1_EXTFEN_Pos (5) /*!< EADC_T::SCTL1: EXTFEN Position */ +#define EADC_SCTL1_EXTFEN_Msk (0x1ul << EADC_SCTL1_EXTFEN_Pos) /*!< EADC_T::SCTL1: EXTFEN Mask */ + +#define EADC_SCTL1_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL1: TRGDLYDIV Position */ +#define EADC_SCTL1_TRGDLYDIV_Msk (0x3ul << EADC_SCTL1_TRGDLYDIV_Pos) /*!< EADC_T::SCTL1: TRGDLYDIV Mask */ + +#define EADC_SCTL1_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL1: TRGDLYCNT Position */ +#define EADC_SCTL1_TRGDLYCNT_Msk (0xfful << EADC_SCTL1_TRGDLYCNT_Pos) /*!< EADC_T::SCTL1: TRGDLYCNT Mask */ + +#define EADC_SCTL1_TRGSEL_Pos (16) /*!< EADC_T::SCTL1: TRGSEL Position */ +#define EADC_SCTL1_TRGSEL_Msk (0x1ful << EADC_SCTL1_TRGSEL_Pos) /*!< EADC_T::SCTL1: TRGSEL Mask */ + +#define EADC_SCTL1_INTPOS_Pos (22) /*!< EADC_T::SCTL1: INTPOS Position */ +#define EADC_SCTL1_INTPOS_Msk (0x1ul << EADC_SCTL1_INTPOS_Pos) /*!< EADC_T::SCTL1: INTPOS Mask */ + +#define EADC_SCTL1_DBMEN_Pos (23) /*!< EADC_T::SCTL1: DBMEN Position */ +#define EADC_SCTL1_DBMEN_Msk (0x1ul << EADC_SCTL1_DBMEN_Pos) /*!< EADC_T::SCTL1: DBMEN Mask */ + +#define EADC_SCTL1_EXTSMPT_Pos (24) /*!< EADC_T::SCTL1: EXTSMPT Position */ +#define EADC_SCTL1_EXTSMPT_Msk (0xfful << EADC_SCTL1_EXTSMPT_Pos) /*!< EADC_T::SCTL1: EXTSMPT Mask */ + +#define EADC_SCTL2_CHSEL_Pos (0) /*!< EADC_T::SCTL2: CHSEL Position */ +#define EADC_SCTL2_CHSEL_Msk (0xful << EADC_SCTL2_CHSEL_Pos) /*!< EADC_T::SCTL2: CHSEL Mask */ + +#define EADC_SCTL2_EXTREN_Pos (4) /*!< EADC_T::SCTL2: EXTREN Position */ +#define EADC_SCTL2_EXTREN_Msk (0x1ul << EADC_SCTL2_EXTREN_Pos) /*!< EADC_T::SCTL2: EXTREN Mask */ + +#define EADC_SCTL2_EXTFEN_Pos (5) /*!< EADC_T::SCTL2: EXTFEN Position */ +#define EADC_SCTL2_EXTFEN_Msk (0x1ul << EADC_SCTL2_EXTFEN_Pos) /*!< EADC_T::SCTL2: EXTFEN Mask */ + +#define EADC_SCTL2_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL2: TRGDLYDIV Position */ +#define EADC_SCTL2_TRGDLYDIV_Msk (0x3ul << EADC_SCTL2_TRGDLYDIV_Pos) /*!< EADC_T::SCTL2: TRGDLYDIV Mask */ + +#define EADC_SCTL2_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL2: TRGDLYCNT Position */ +#define EADC_SCTL2_TRGDLYCNT_Msk (0xfful << EADC_SCTL2_TRGDLYCNT_Pos) /*!< EADC_T::SCTL2: TRGDLYCNT Mask */ + +#define EADC_SCTL2_TRGSEL_Pos (16) /*!< EADC_T::SCTL2: TRGSEL Position */ +#define EADC_SCTL2_TRGSEL_Msk (0x1ful << EADC_SCTL2_TRGSEL_Pos) /*!< EADC_T::SCTL2: TRGSEL Mask */ + +#define EADC_SCTL2_INTPOS_Pos (22) /*!< EADC_T::SCTL2: INTPOS Position */ +#define EADC_SCTL2_INTPOS_Msk (0x1ul << EADC_SCTL2_INTPOS_Pos) /*!< EADC_T::SCTL2: INTPOS Mask */ + +#define EADC_SCTL2_DBMEN_Pos (23) /*!< EADC_T::SCTL2: DBMEN Position */ +#define EADC_SCTL2_DBMEN_Msk (0x1ul << EADC_SCTL2_DBMEN_Pos) /*!< EADC_T::SCTL2: DBMEN Mask */ + +#define EADC_SCTL2_EXTSMPT_Pos (24) /*!< EADC_T::SCTL2: EXTSMPT Position */ +#define EADC_SCTL2_EXTSMPT_Msk (0xfful << EADC_SCTL2_EXTSMPT_Pos) /*!< EADC_T::SCTL2: EXTSMPT Mask */ + +#define EADC_SCTL3_CHSEL_Pos (0) /*!< EADC_T::SCTL3: CHSEL Position */ +#define EADC_SCTL3_CHSEL_Msk (0xful << EADC_SCTL3_CHSEL_Pos) /*!< EADC_T::SCTL3: CHSEL Mask */ + +#define EADC_SCTL3_EXTREN_Pos (4) /*!< EADC_T::SCTL3: EXTREN Position */ +#define EADC_SCTL3_EXTREN_Msk (0x1ul << EADC_SCTL3_EXTREN_Pos) /*!< EADC_T::SCTL3: EXTREN Mask */ + +#define EADC_SCTL3_EXTFEN_Pos (5) /*!< EADC_T::SCTL3: EXTFEN Position */ +#define EADC_SCTL3_EXTFEN_Msk (0x1ul << EADC_SCTL3_EXTFEN_Pos) /*!< EADC_T::SCTL3: EXTFEN Mask */ + +#define EADC_SCTL3_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL3: TRGDLYDIV Position */ +#define EADC_SCTL3_TRGDLYDIV_Msk (0x3ul << EADC_SCTL3_TRGDLYDIV_Pos) /*!< EADC_T::SCTL3: TRGDLYDIV Mask */ + +#define EADC_SCTL3_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL3: TRGDLYCNT Position */ +#define EADC_SCTL3_TRGDLYCNT_Msk (0xfful << EADC_SCTL3_TRGDLYCNT_Pos) /*!< EADC_T::SCTL3: TRGDLYCNT Mask */ + +#define EADC_SCTL3_TRGSEL_Pos (16) /*!< EADC_T::SCTL3: TRGSEL Position */ +#define EADC_SCTL3_TRGSEL_Msk (0x1ful << EADC_SCTL3_TRGSEL_Pos) /*!< EADC_T::SCTL3: TRGSEL Mask */ + +#define EADC_SCTL3_INTPOS_Pos (22) /*!< EADC_T::SCTL3: INTPOS Position */ +#define EADC_SCTL3_INTPOS_Msk (0x1ul << EADC_SCTL3_INTPOS_Pos) /*!< EADC_T::SCTL3: INTPOS Mask */ + +#define EADC_SCTL3_DBMEN_Pos (23) /*!< EADC_T::SCTL3: DBMEN Position */ +#define EADC_SCTL3_DBMEN_Msk (0x1ul << EADC_SCTL3_DBMEN_Pos) /*!< EADC_T::SCTL3: DBMEN Mask */ + +#define EADC_SCTL3_EXTSMPT_Pos (24) /*!< EADC_T::SCTL3: EXTSMPT Position */ +#define EADC_SCTL3_EXTSMPT_Msk (0xfful << EADC_SCTL3_EXTSMPT_Pos) /*!< EADC_T::SCTL3: EXTSMPT Mask */ + +#define EADC_SCTL4_CHSEL_Pos (0) /*!< EADC_T::SCTL4: CHSEL Position */ +#define EADC_SCTL4_CHSEL_Msk (0xful << EADC_SCTL4_CHSEL_Pos) /*!< EADC_T::SCTL4: CHSEL Mask */ + +#define EADC_SCTL4_EXTREN_Pos (4) /*!< EADC_T::SCTL4: EXTREN Position */ +#define EADC_SCTL4_EXTREN_Msk (0x1ul << EADC_SCTL4_EXTREN_Pos) /*!< EADC_T::SCTL4: EXTREN Mask */ + +#define EADC_SCTL4_EXTFEN_Pos (5) /*!< EADC_T::SCTL4: EXTFEN Position */ +#define EADC_SCTL4_EXTFEN_Msk (0x1ul << EADC_SCTL4_EXTFEN_Pos) /*!< EADC_T::SCTL4: EXTFEN Mask */ + +#define EADC_SCTL4_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL4: TRGDLYDIV Position */ +#define EADC_SCTL4_TRGDLYDIV_Msk (0x3ul << EADC_SCTL4_TRGDLYDIV_Pos) /*!< EADC_T::SCTL4: TRGDLYDIV Mask */ + +#define EADC_SCTL4_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL4: TRGDLYCNT Position */ +#define EADC_SCTL4_TRGDLYCNT_Msk (0xfful << EADC_SCTL4_TRGDLYCNT_Pos) /*!< EADC_T::SCTL4: TRGDLYCNT Mask */ + +#define EADC_SCTL4_TRGSEL_Pos (16) /*!< EADC_T::SCTL4: TRGSEL Position */ +#define EADC_SCTL4_TRGSEL_Msk (0x1ful << EADC_SCTL4_TRGSEL_Pos) /*!< EADC_T::SCTL4: TRGSEL Mask */ + +#define EADC_SCTL4_INTPOS_Pos (22) /*!< EADC_T::SCTL4: INTPOS Position */ +#define EADC_SCTL4_INTPOS_Msk (0x1ul << EADC_SCTL4_INTPOS_Pos) /*!< EADC_T::SCTL4: INTPOS Mask */ + +#define EADC_SCTL4_EXTSMPT_Pos (24) /*!< EADC_T::SCTL4: EXTSMPT Position */ +#define EADC_SCTL4_EXTSMPT_Msk (0xfful << EADC_SCTL4_EXTSMPT_Pos) /*!< EADC_T::SCTL4: EXTSMPT Mask */ + +#define EADC_SCTL5_CHSEL_Pos (0) /*!< EADC_T::SCTL5: CHSEL Position */ +#define EADC_SCTL5_CHSEL_Msk (0xful << EADC_SCTL5_CHSEL_Pos) /*!< EADC_T::SCTL5: CHSEL Mask */ + +#define EADC_SCTL5_EXTREN_Pos (4) /*!< EADC_T::SCTL5: EXTREN Position */ +#define EADC_SCTL5_EXTREN_Msk (0x1ul << EADC_SCTL5_EXTREN_Pos) /*!< EADC_T::SCTL5: EXTREN Mask */ + +#define EADC_SCTL5_EXTFEN_Pos (5) /*!< EADC_T::SCTL5: EXTFEN Position */ +#define EADC_SCTL5_EXTFEN_Msk (0x1ul << EADC_SCTL5_EXTFEN_Pos) /*!< EADC_T::SCTL5: EXTFEN Mask */ + +#define EADC_SCTL5_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL5: TRGDLYDIV Position */ +#define EADC_SCTL5_TRGDLYDIV_Msk (0x3ul << EADC_SCTL5_TRGDLYDIV_Pos) /*!< EADC_T::SCTL5: TRGDLYDIV Mask */ + +#define EADC_SCTL5_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL5: TRGDLYCNT Position */ +#define EADC_SCTL5_TRGDLYCNT_Msk (0xfful << EADC_SCTL5_TRGDLYCNT_Pos) /*!< EADC_T::SCTL5: TRGDLYCNT Mask */ + +#define EADC_SCTL5_TRGSEL_Pos (16) /*!< EADC_T::SCTL5: TRGSEL Position */ +#define EADC_SCTL5_TRGSEL_Msk (0x1ful << EADC_SCTL5_TRGSEL_Pos) /*!< EADC_T::SCTL5: TRGSEL Mask */ + +#define EADC_SCTL5_INTPOS_Pos (22) /*!< EADC_T::SCTL5: INTPOS Position */ +#define EADC_SCTL5_INTPOS_Msk (0x1ul << EADC_SCTL5_INTPOS_Pos) /*!< EADC_T::SCTL5: INTPOS Mask */ + +#define EADC_SCTL5_EXTSMPT_Pos (24) /*!< EADC_T::SCTL5: EXTSMPT Position */ +#define EADC_SCTL5_EXTSMPT_Msk (0xfful << EADC_SCTL5_EXTSMPT_Pos) /*!< EADC_T::SCTL5: EXTSMPT Mask */ + +#define EADC_SCTL6_CHSEL_Pos (0) /*!< EADC_T::SCTL6: CHSEL Position */ +#define EADC_SCTL6_CHSEL_Msk (0xful << EADC_SCTL6_CHSEL_Pos) /*!< EADC_T::SCTL6: CHSEL Mask */ + +#define EADC_SCTL6_EXTREN_Pos (4) /*!< EADC_T::SCTL6: EXTREN Position */ +#define EADC_SCTL6_EXTREN_Msk (0x1ul << EADC_SCTL6_EXTREN_Pos) /*!< EADC_T::SCTL6: EXTREN Mask */ + +#define EADC_SCTL6_EXTFEN_Pos (5) /*!< EADC_T::SCTL6: EXTFEN Position */ +#define EADC_SCTL6_EXTFEN_Msk (0x1ul << EADC_SCTL6_EXTFEN_Pos) /*!< EADC_T::SCTL6: EXTFEN Mask */ + +#define EADC_SCTL6_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL6: TRGDLYDIV Position */ +#define EADC_SCTL6_TRGDLYDIV_Msk (0x3ul << EADC_SCTL6_TRGDLYDIV_Pos) /*!< EADC_T::SCTL6: TRGDLYDIV Mask */ + +#define EADC_SCTL6_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL6: TRGDLYCNT Position */ +#define EADC_SCTL6_TRGDLYCNT_Msk (0xfful << EADC_SCTL6_TRGDLYCNT_Pos) /*!< EADC_T::SCTL6: TRGDLYCNT Mask */ + +#define EADC_SCTL6_TRGSEL_Pos (16) /*!< EADC_T::SCTL6: TRGSEL Position */ +#define EADC_SCTL6_TRGSEL_Msk (0x1ful << EADC_SCTL6_TRGSEL_Pos) /*!< EADC_T::SCTL6: TRGSEL Mask */ + +#define EADC_SCTL6_INTPOS_Pos (22) /*!< EADC_T::SCTL6: INTPOS Position */ +#define EADC_SCTL6_INTPOS_Msk (0x1ul << EADC_SCTL6_INTPOS_Pos) /*!< EADC_T::SCTL6: INTPOS Mask */ + +#define EADC_SCTL6_EXTSMPT_Pos (24) /*!< EADC_T::SCTL6: EXTSMPT Position */ +#define EADC_SCTL6_EXTSMPT_Msk (0xfful << EADC_SCTL6_EXTSMPT_Pos) /*!< EADC_T::SCTL6: EXTSMPT Mask */ + +#define EADC_SCTL7_CHSEL_Pos (0) /*!< EADC_T::SCTL7: CHSEL Position */ +#define EADC_SCTL7_CHSEL_Msk (0xful << EADC_SCTL7_CHSEL_Pos) /*!< EADC_T::SCTL7: CHSEL Mask */ + +#define EADC_SCTL7_EXTREN_Pos (4) /*!< EADC_T::SCTL7: EXTREN Position */ +#define EADC_SCTL7_EXTREN_Msk (0x1ul << EADC_SCTL7_EXTREN_Pos) /*!< EADC_T::SCTL7: EXTREN Mask */ + +#define EADC_SCTL7_EXTFEN_Pos (5) /*!< EADC_T::SCTL7: EXTFEN Position */ +#define EADC_SCTL7_EXTFEN_Msk (0x1ul << EADC_SCTL7_EXTFEN_Pos) /*!< EADC_T::SCTL7: EXTFEN Mask */ + +#define EADC_SCTL7_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL7: TRGDLYDIV Position */ +#define EADC_SCTL7_TRGDLYDIV_Msk (0x3ul << EADC_SCTL7_TRGDLYDIV_Pos) /*!< EADC_T::SCTL7: TRGDLYDIV Mask */ + +#define EADC_SCTL7_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL7: TRGDLYCNT Position */ +#define EADC_SCTL7_TRGDLYCNT_Msk (0xfful << EADC_SCTL7_TRGDLYCNT_Pos) /*!< EADC_T::SCTL7: TRGDLYCNT Mask */ + +#define EADC_SCTL7_TRGSEL_Pos (16) /*!< EADC_T::SCTL7: TRGSEL Position */ +#define EADC_SCTL7_TRGSEL_Msk (0x1ful << EADC_SCTL7_TRGSEL_Pos) /*!< EADC_T::SCTL7: TRGSEL Mask */ + +#define EADC_SCTL7_INTPOS_Pos (22) /*!< EADC_T::SCTL7: INTPOS Position */ +#define EADC_SCTL7_INTPOS_Msk (0x1ul << EADC_SCTL7_INTPOS_Pos) /*!< EADC_T::SCTL7: INTPOS Mask */ + +#define EADC_SCTL7_EXTSMPT_Pos (24) /*!< EADC_T::SCTL7: EXTSMPT Position */ +#define EADC_SCTL7_EXTSMPT_Msk (0xfful << EADC_SCTL7_EXTSMPT_Pos) /*!< EADC_T::SCTL7: EXTSMPT Mask */ + +#define EADC_SCTL8_CHSEL_Pos (0) /*!< EADC_T::SCTL8: CHSEL Position */ +#define EADC_SCTL8_CHSEL_Msk (0xful << EADC_SCTL8_CHSEL_Pos) /*!< EADC_T::SCTL8: CHSEL Mask */ + +#define EADC_SCTL8_EXTREN_Pos (4) /*!< EADC_T::SCTL8: EXTREN Position */ +#define EADC_SCTL8_EXTREN_Msk (0x1ul << EADC_SCTL8_EXTREN_Pos) /*!< EADC_T::SCTL8: EXTREN Mask */ + +#define EADC_SCTL8_EXTFEN_Pos (5) /*!< EADC_T::SCTL8: EXTFEN Position */ +#define EADC_SCTL8_EXTFEN_Msk (0x1ul << EADC_SCTL8_EXTFEN_Pos) /*!< EADC_T::SCTL8: EXTFEN Mask */ + +#define EADC_SCTL8_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL8: TRGDLYDIV Position */ +#define EADC_SCTL8_TRGDLYDIV_Msk (0x3ul << EADC_SCTL8_TRGDLYDIV_Pos) /*!< EADC_T::SCTL8: TRGDLYDIV Mask */ + +#define EADC_SCTL8_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL8: TRGDLYCNT Position */ +#define EADC_SCTL8_TRGDLYCNT_Msk (0xfful << EADC_SCTL8_TRGDLYCNT_Pos) /*!< EADC_T::SCTL8: TRGDLYCNT Mask */ + +#define EADC_SCTL8_TRGSEL_Pos (16) /*!< EADC_T::SCTL8: TRGSEL Position */ +#define EADC_SCTL8_TRGSEL_Msk (0x1ful << EADC_SCTL8_TRGSEL_Pos) /*!< EADC_T::SCTL8: TRGSEL Mask */ + +#define EADC_SCTL8_INTPOS_Pos (22) /*!< EADC_T::SCTL8: INTPOS Position */ +#define EADC_SCTL8_INTPOS_Msk (0x1ul << EADC_SCTL8_INTPOS_Pos) /*!< EADC_T::SCTL8: INTPOS Mask */ + +#define EADC_SCTL8_EXTSMPT_Pos (24) /*!< EADC_T::SCTL8: EXTSMPT Position */ +#define EADC_SCTL8_EXTSMPT_Msk (0xfful << EADC_SCTL8_EXTSMPT_Pos) /*!< EADC_T::SCTL8: EXTSMPT Mask */ + +#define EADC_SCTL9_CHSEL_Pos (0) /*!< EADC_T::SCTL9: CHSEL Position */ +#define EADC_SCTL9_CHSEL_Msk (0xful << EADC_SCTL9_CHSEL_Pos) /*!< EADC_T::SCTL9: CHSEL Mask */ + +#define EADC_SCTL9_EXTREN_Pos (4) /*!< EADC_T::SCTL9: EXTREN Position */ +#define EADC_SCTL9_EXTREN_Msk (0x1ul << EADC_SCTL9_EXTREN_Pos) /*!< EADC_T::SCTL9: EXTREN Mask */ + +#define EADC_SCTL9_EXTFEN_Pos (5) /*!< EADC_T::SCTL9: EXTFEN Position */ +#define EADC_SCTL9_EXTFEN_Msk (0x1ul << EADC_SCTL9_EXTFEN_Pos) /*!< EADC_T::SCTL9: EXTFEN Mask */ + +#define EADC_SCTL9_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL9: TRGDLYDIV Position */ +#define EADC_SCTL9_TRGDLYDIV_Msk (0x3ul << EADC_SCTL9_TRGDLYDIV_Pos) /*!< EADC_T::SCTL9: TRGDLYDIV Mask */ + +#define EADC_SCTL9_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL9: TRGDLYCNT Position */ +#define EADC_SCTL9_TRGDLYCNT_Msk (0xfful << EADC_SCTL9_TRGDLYCNT_Pos) /*!< EADC_T::SCTL9: TRGDLYCNT Mask */ + +#define EADC_SCTL9_TRGSEL_Pos (16) /*!< EADC_T::SCTL9: TRGSEL Position */ +#define EADC_SCTL9_TRGSEL_Msk (0x1ful << EADC_SCTL9_TRGSEL_Pos) /*!< EADC_T::SCTL9: TRGSEL Mask */ + +#define EADC_SCTL9_INTPOS_Pos (22) /*!< EADC_T::SCTL9: INTPOS Position */ +#define EADC_SCTL9_INTPOS_Msk (0x1ul << EADC_SCTL9_INTPOS_Pos) /*!< EADC_T::SCTL9: INTPOS Mask */ + +#define EADC_SCTL9_EXTSMPT_Pos (24) /*!< EADC_T::SCTL9: EXTSMPT Position */ +#define EADC_SCTL9_EXTSMPT_Msk (0xfful << EADC_SCTL9_EXTSMPT_Pos) /*!< EADC_T::SCTL9: EXTSMPT Mask */ + +#define EADC_SCTL10_CHSEL_Pos (0) /*!< EADC_T::SCTL10: CHSEL Position */ +#define EADC_SCTL10_CHSEL_Msk (0xful << EADC_SCTL10_CHSEL_Pos) /*!< EADC_T::SCTL10: CHSEL Mask */ + +#define EADC_SCTL10_EXTREN_Pos (4) /*!< EADC_T::SCTL10: EXTREN Position */ +#define EADC_SCTL10_EXTREN_Msk (0x1ul << EADC_SCTL10_EXTREN_Pos) /*!< EADC_T::SCTL10: EXTREN Mask */ + +#define EADC_SCTL10_EXTFEN_Pos (5) /*!< EADC_T::SCTL10: EXTFEN Position */ +#define EADC_SCTL10_EXTFEN_Msk (0x1ul << EADC_SCTL10_EXTFEN_Pos) /*!< EADC_T::SCTL10: EXTFEN Mask */ + +#define EADC_SCTL10_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL10: TRGDLYDIV Position */ +#define EADC_SCTL10_TRGDLYDIV_Msk (0x3ul << EADC_SCTL10_TRGDLYDIV_Pos) /*!< EADC_T::SCTL10: TRGDLYDIV Mask */ + +#define EADC_SCTL10_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL10: TRGDLYCNT Position */ +#define EADC_SCTL10_TRGDLYCNT_Msk (0xfful << EADC_SCTL10_TRGDLYCNT_Pos) /*!< EADC_T::SCTL10: TRGDLYCNT Mask */ + +#define EADC_SCTL10_TRGSEL_Pos (16) /*!< EADC_T::SCTL10: TRGSEL Position */ +#define EADC_SCTL10_TRGSEL_Msk (0x1ful << EADC_SCTL10_TRGSEL_Pos) /*!< EADC_T::SCTL10: TRGSEL Mask */ + +#define EADC_SCTL10_INTPOS_Pos (22) /*!< EADC_T::SCTL10: INTPOS Position */ +#define EADC_SCTL10_INTPOS_Msk (0x1ul << EADC_SCTL10_INTPOS_Pos) /*!< EADC_T::SCTL10: INTPOS Mask */ + +#define EADC_SCTL10_EXTSMPT_Pos (24) /*!< EADC_T::SCTL10: EXTSMPT Position */ +#define EADC_SCTL10_EXTSMPT_Msk (0xfful << EADC_SCTL10_EXTSMPT_Pos) /*!< EADC_T::SCTL10: EXTSMPT Mask */ + +#define EADC_SCTL11_CHSEL_Pos (0) /*!< EADC_T::SCTL11: CHSEL Position */ +#define EADC_SCTL11_CHSEL_Msk (0xful << EADC_SCTL11_CHSEL_Pos) /*!< EADC_T::SCTL11: CHSEL Mask */ + +#define EADC_SCTL11_EXTREN_Pos (4) /*!< EADC_T::SCTL11: EXTREN Position */ +#define EADC_SCTL11_EXTREN_Msk (0x1ul << EADC_SCTL11_EXTREN_Pos) /*!< EADC_T::SCTL11: EXTREN Mask */ + +#define EADC_SCTL11_EXTFEN_Pos (5) /*!< EADC_T::SCTL11: EXTFEN Position */ +#define EADC_SCTL11_EXTFEN_Msk (0x1ul << EADC_SCTL11_EXTFEN_Pos) /*!< EADC_T::SCTL11: EXTFEN Mask */ + +#define EADC_SCTL11_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL11: TRGDLYDIV Position */ +#define EADC_SCTL11_TRGDLYDIV_Msk (0x3ul << EADC_SCTL11_TRGDLYDIV_Pos) /*!< EADC_T::SCTL11: TRGDLYDIV Mask */ + +#define EADC_SCTL11_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL11: TRGDLYCNT Position */ +#define EADC_SCTL11_TRGDLYCNT_Msk (0xfful << EADC_SCTL11_TRGDLYCNT_Pos) /*!< EADC_T::SCTL11: TRGDLYCNT Mask */ + +#define EADC_SCTL11_TRGSEL_Pos (16) /*!< EADC_T::SCTL11: TRGSEL Position */ +#define EADC_SCTL11_TRGSEL_Msk (0x1ful << EADC_SCTL11_TRGSEL_Pos) /*!< EADC_T::SCTL11: TRGSEL Mask */ + +#define EADC_SCTL11_INTPOS_Pos (22) /*!< EADC_T::SCTL11: INTPOS Position */ +#define EADC_SCTL11_INTPOS_Msk (0x1ul << EADC_SCTL11_INTPOS_Pos) /*!< EADC_T::SCTL11: INTPOS Mask */ + +#define EADC_SCTL11_EXTSMPT_Pos (24) /*!< EADC_T::SCTL11: EXTSMPT Position */ +#define EADC_SCTL11_EXTSMPT_Msk (0xfful << EADC_SCTL11_EXTSMPT_Pos) /*!< EADC_T::SCTL11: EXTSMPT Mask */ + +#define EADC_SCTL12_CHSEL_Pos (0) /*!< EADC_T::SCTL12: CHSEL Position */ +#define EADC_SCTL12_CHSEL_Msk (0xful << EADC_SCTL12_CHSEL_Pos) /*!< EADC_T::SCTL12: CHSEL Mask */ + +#define EADC_SCTL12_EXTREN_Pos (4) /*!< EADC_T::SCTL12: EXTREN Position */ +#define EADC_SCTL12_EXTREN_Msk (0x1ul << EADC_SCTL12_EXTREN_Pos) /*!< EADC_T::SCTL12: EXTREN Mask */ + +#define EADC_SCTL12_EXTFEN_Pos (5) /*!< EADC_T::SCTL12: EXTFEN Position */ +#define EADC_SCTL12_EXTFEN_Msk (0x1ul << EADC_SCTL12_EXTFEN_Pos) /*!< EADC_T::SCTL12: EXTFEN Mask */ + +#define EADC_SCTL12_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL12: TRGDLYDIV Position */ +#define EADC_SCTL12_TRGDLYDIV_Msk (0x3ul << EADC_SCTL12_TRGDLYDIV_Pos) /*!< EADC_T::SCTL12: TRGDLYDIV Mask */ + +#define EADC_SCTL12_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL12: TRGDLYCNT Position */ +#define EADC_SCTL12_TRGDLYCNT_Msk (0xfful << EADC_SCTL12_TRGDLYCNT_Pos) /*!< EADC_T::SCTL12: TRGDLYCNT Mask */ + +#define EADC_SCTL12_TRGSEL_Pos (16) /*!< EADC_T::SCTL12: TRGSEL Position */ +#define EADC_SCTL12_TRGSEL_Msk (0x1ful << EADC_SCTL12_TRGSEL_Pos) /*!< EADC_T::SCTL12: TRGSEL Mask */ + +#define EADC_SCTL12_INTPOS_Pos (22) /*!< EADC_T::SCTL12: INTPOS Position */ +#define EADC_SCTL12_INTPOS_Msk (0x1ul << EADC_SCTL12_INTPOS_Pos) /*!< EADC_T::SCTL12: INTPOS Mask */ + +#define EADC_SCTL12_EXTSMPT_Pos (24) /*!< EADC_T::SCTL12: EXTSMPT Position */ +#define EADC_SCTL12_EXTSMPT_Msk (0xfful << EADC_SCTL12_EXTSMPT_Pos) /*!< EADC_T::SCTL12: EXTSMPT Mask */ + +#define EADC_SCTL13_CHSEL_Pos (0) /*!< EADC_T::SCTL13: CHSEL Position */ +#define EADC_SCTL13_CHSEL_Msk (0xful << EADC_SCTL13_CHSEL_Pos) /*!< EADC_T::SCTL13: CHSEL Mask */ + +#define EADC_SCTL13_EXTREN_Pos (4) /*!< EADC_T::SCTL13: EXTREN Position */ +#define EADC_SCTL13_EXTREN_Msk (0x1ul << EADC_SCTL13_EXTREN_Pos) /*!< EADC_T::SCTL13: EXTREN Mask */ + +#define EADC_SCTL13_EXTFEN_Pos (5) /*!< EADC_T::SCTL13: EXTFEN Position */ +#define EADC_SCTL13_EXTFEN_Msk (0x1ul << EADC_SCTL13_EXTFEN_Pos) /*!< EADC_T::SCTL13: EXTFEN Mask */ + +#define EADC_SCTL13_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL13: TRGDLYDIV Position */ +#define EADC_SCTL13_TRGDLYDIV_Msk (0x3ul << EADC_SCTL13_TRGDLYDIV_Pos) /*!< EADC_T::SCTL13: TRGDLYDIV Mask */ + +#define EADC_SCTL13_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL13: TRGDLYCNT Position */ +#define EADC_SCTL13_TRGDLYCNT_Msk (0xfful << EADC_SCTL13_TRGDLYCNT_Pos) /*!< EADC_T::SCTL13: TRGDLYCNT Mask */ + +#define EADC_SCTL13_TRGSEL_Pos (16) /*!< EADC_T::SCTL13: TRGSEL Position */ +#define EADC_SCTL13_TRGSEL_Msk (0x1ful << EADC_SCTL13_TRGSEL_Pos) /*!< EADC_T::SCTL13: TRGSEL Mask */ + +#define EADC_SCTL13_INTPOS_Pos (22) /*!< EADC_T::SCTL13: INTPOS Position */ +#define EADC_SCTL13_INTPOS_Msk (0x1ul << EADC_SCTL13_INTPOS_Pos) /*!< EADC_T::SCTL13: INTPOS Mask */ + +#define EADC_SCTL13_EXTSMPT_Pos (24) /*!< EADC_T::SCTL13: EXTSMPT Position */ +#define EADC_SCTL13_EXTSMPT_Msk (0xfful << EADC_SCTL13_EXTSMPT_Pos) /*!< EADC_T::SCTL13: EXTSMPT Mask */ + +#define EADC_SCTL14_CHSEL_Pos (0) /*!< EADC_T::SCTL14: CHSEL Position */ +#define EADC_SCTL14_CHSEL_Msk (0xful << EADC_SCTL14_CHSEL_Pos) /*!< EADC_T::SCTL14: CHSEL Mask */ + +#define EADC_SCTL14_EXTREN_Pos (4) /*!< EADC_T::SCTL14: EXTREN Position */ +#define EADC_SCTL14_EXTREN_Msk (0x1ul << EADC_SCTL14_EXTREN_Pos) /*!< EADC_T::SCTL14: EXTREN Mask */ + +#define EADC_SCTL14_EXTFEN_Pos (5) /*!< EADC_T::SCTL14: EXTFEN Position */ +#define EADC_SCTL14_EXTFEN_Msk (0x1ul << EADC_SCTL14_EXTFEN_Pos) /*!< EADC_T::SCTL14: EXTFEN Mask */ + +#define EADC_SCTL14_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL14: TRGDLYDIV Position */ +#define EADC_SCTL14_TRGDLYDIV_Msk (0x3ul << EADC_SCTL14_TRGDLYDIV_Pos) /*!< EADC_T::SCTL14: TRGDLYDIV Mask */ + +#define EADC_SCTL14_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL14: TRGDLYCNT Position */ +#define EADC_SCTL14_TRGDLYCNT_Msk (0xfful << EADC_SCTL14_TRGDLYCNT_Pos) /*!< EADC_T::SCTL14: TRGDLYCNT Mask */ + +#define EADC_SCTL14_TRGSEL_Pos (16) /*!< EADC_T::SCTL14: TRGSEL Position */ +#define EADC_SCTL14_TRGSEL_Msk (0x1ful << EADC_SCTL14_TRGSEL_Pos) /*!< EADC_T::SCTL14: TRGSEL Mask */ + +#define EADC_SCTL14_INTPOS_Pos (22) /*!< EADC_T::SCTL14: INTPOS Position */ +#define EADC_SCTL14_INTPOS_Msk (0x1ul << EADC_SCTL14_INTPOS_Pos) /*!< EADC_T::SCTL14: INTPOS Mask */ + +#define EADC_SCTL14_EXTSMPT_Pos (24) /*!< EADC_T::SCTL14: EXTSMPT Position */ +#define EADC_SCTL14_EXTSMPT_Msk (0xfful << EADC_SCTL14_EXTSMPT_Pos) /*!< EADC_T::SCTL14: EXTSMPT Mask */ + +#define EADC_SCTL15_CHSEL_Pos (0) /*!< EADC_T::SCTL15: CHSEL Position */ +#define EADC_SCTL15_CHSEL_Msk (0xful << EADC_SCTL15_CHSEL_Pos) /*!< EADC_T::SCTL15: CHSEL Mask */ + +#define EADC_SCTL15_EXTREN_Pos (4) /*!< EADC_T::SCTL15: EXTREN Position */ +#define EADC_SCTL15_EXTREN_Msk (0x1ul << EADC_SCTL15_EXTREN_Pos) /*!< EADC_T::SCTL15: EXTREN Mask */ + +#define EADC_SCTL15_EXTFEN_Pos (5) /*!< EADC_T::SCTL15: EXTFEN Position */ +#define EADC_SCTL15_EXTFEN_Msk (0x1ul << EADC_SCTL15_EXTFEN_Pos) /*!< EADC_T::SCTL15: EXTFEN Mask */ + +#define EADC_SCTL15_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL15: TRGDLYDIV Position */ +#define EADC_SCTL15_TRGDLYDIV_Msk (0x3ul << EADC_SCTL15_TRGDLYDIV_Pos) /*!< EADC_T::SCTL15: TRGDLYDIV Mask */ + +#define EADC_SCTL15_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL15: TRGDLYCNT Position */ +#define EADC_SCTL15_TRGDLYCNT_Msk (0xfful << EADC_SCTL15_TRGDLYCNT_Pos) /*!< EADC_T::SCTL15: TRGDLYCNT Mask */ + +#define EADC_SCTL15_TRGSEL_Pos (16) /*!< EADC_T::SCTL15: TRGSEL Position */ +#define EADC_SCTL15_TRGSEL_Msk (0x1ful << EADC_SCTL15_TRGSEL_Pos) /*!< EADC_T::SCTL15: TRGSEL Mask */ + +#define EADC_SCTL15_INTPOS_Pos (22) /*!< EADC_T::SCTL15: INTPOS Position */ +#define EADC_SCTL15_INTPOS_Msk (0x1ul << EADC_SCTL15_INTPOS_Pos) /*!< EADC_T::SCTL15: INTPOS Mask */ + +#define EADC_SCTL15_EXTSMPT_Pos (24) /*!< EADC_T::SCTL15: EXTSMPT Position */ +#define EADC_SCTL15_EXTSMPT_Msk (0xfful << EADC_SCTL15_EXTSMPT_Pos) /*!< EADC_T::SCTL15: EXTSMPT Mask */ + +#define EADC_SCTL16_EXTSMPT_Pos (24) /*!< EADC_T::SCTL16: EXTSMPT Position */ +#define EADC_SCTL16_EXTSMPT_Msk (0xfful << EADC_SCTL16_EXTSMPT_Pos) /*!< EADC_T::SCTL16: EXTSMPT Mask */ + +#define EADC_SCTL17_EXTSMPT_Pos (24) /*!< EADC_T::SCTL17: EXTSMPT Position */ +#define EADC_SCTL17_EXTSMPT_Msk (0xfful << EADC_SCTL17_EXTSMPT_Pos) /*!< EADC_T::SCTL17: EXTSMPT Mask */ + +#define EADC_SCTL18_EXTSMPT_Pos (24) /*!< EADC_T::SCTL18: EXTSMPT Position */ +#define EADC_SCTL18_EXTSMPT_Msk (0xfful << EADC_SCTL18_EXTSMPT_Pos) /*!< EADC_T::SCTL18: EXTSMPT Mask */ + +#define EADC_INTSRC0_SPLIE0_Pos (0) /*!< EADC_T::INTSRC0: SPLIE0 Position */ +#define EADC_INTSRC0_SPLIE0_Msk (0x1ul << EADC_INTSRC0_SPLIE0_Pos) /*!< EADC_T::INTSRC0: SPLIE0 Mask */ + +#define EADC_INTSRC0_SPLIE1_Pos (1) /*!< EADC_T::INTSRC0: SPLIE1 Position */ +#define EADC_INTSRC0_SPLIE1_Msk (0x1ul << EADC_INTSRC0_SPLIE1_Pos) /*!< EADC_T::INTSRC0: SPLIE1 Mask */ + +#define EADC_INTSRC0_SPLIE2_Pos (2) /*!< EADC_T::INTSRC0: SPLIE2 Position */ +#define EADC_INTSRC0_SPLIE2_Msk (0x1ul << EADC_INTSRC0_SPLIE2_Pos) /*!< EADC_T::INTSRC0: SPLIE2 Mask */ + +#define EADC_INTSRC0_SPLIE3_Pos (3) /*!< EADC_T::INTSRC0: SPLIE3 Position */ +#define EADC_INTSRC0_SPLIE3_Msk (0x1ul << EADC_INTSRC0_SPLIE3_Pos) /*!< EADC_T::INTSRC0: SPLIE3 Mask */ + +#define EADC_INTSRC0_SPLIE4_Pos (4) /*!< EADC_T::INTSRC0: SPLIE4 Position */ +#define EADC_INTSRC0_SPLIE4_Msk (0x1ul << EADC_INTSRC0_SPLIE4_Pos) /*!< EADC_T::INTSRC0: SPLIE4 Mask */ + +#define EADC_INTSRC0_SPLIE5_Pos (5) /*!< EADC_T::INTSRC0: SPLIE5 Position */ +#define EADC_INTSRC0_SPLIE5_Msk (0x1ul << EADC_INTSRC0_SPLIE5_Pos) /*!< EADC_T::INTSRC0: SPLIE5 Mask */ + +#define EADC_INTSRC0_SPLIE6_Pos (6) /*!< EADC_T::INTSRC0: SPLIE6 Position */ +#define EADC_INTSRC0_SPLIE6_Msk (0x1ul << EADC_INTSRC0_SPLIE6_Pos) /*!< EADC_T::INTSRC0: SPLIE6 Mask */ + +#define EADC_INTSRC0_SPLIE7_Pos (7) /*!< EADC_T::INTSRC0: SPLIE7 Position */ +#define EADC_INTSRC0_SPLIE7_Msk (0x1ul << EADC_INTSRC0_SPLIE7_Pos) /*!< EADC_T::INTSRC0: SPLIE7 Mask */ + +#define EADC_INTSRC0_SPLIE8_Pos (8) /*!< EADC_T::INTSRC0: SPLIE8 Position */ +#define EADC_INTSRC0_SPLIE8_Msk (0x1ul << EADC_INTSRC0_SPLIE8_Pos) /*!< EADC_T::INTSRC0: SPLIE8 Mask */ + +#define EADC_INTSRC0_SPLIE9_Pos (9) /*!< EADC_T::INTSRC0: SPLIE9 Position */ +#define EADC_INTSRC0_SPLIE9_Msk (0x1ul << EADC_INTSRC0_SPLIE9_Pos) /*!< EADC_T::INTSRC0: SPLIE9 Mask */ + +#define EADC_INTSRC0_SPLIE10_Pos (10) /*!< EADC_T::INTSRC0: SPLIE10 Position */ +#define EADC_INTSRC0_SPLIE10_Msk (0x1ul << EADC_INTSRC0_SPLIE10_Pos) /*!< EADC_T::INTSRC0: SPLIE10 Mask */ + +#define EADC_INTSRC0_SPLIE11_Pos (11) /*!< EADC_T::INTSRC0: SPLIE11 Position */ +#define EADC_INTSRC0_SPLIE11_Msk (0x1ul << EADC_INTSRC0_SPLIE11_Pos) /*!< EADC_T::INTSRC0: SPLIE11 Mask */ + +#define EADC_INTSRC0_SPLIE12_Pos (12) /*!< EADC_T::INTSRC0: SPLIE12 Position */ +#define EADC_INTSRC0_SPLIE12_Msk (0x1ul << EADC_INTSRC0_SPLIE12_Pos) /*!< EADC_T::INTSRC0: SPLIE12 Mask */ + +#define EADC_INTSRC0_SPLIE13_Pos (13) /*!< EADC_T::INTSRC0: SPLIE13 Position */ +#define EADC_INTSRC0_SPLIE13_Msk (0x1ul << EADC_INTSRC0_SPLIE13_Pos) /*!< EADC_T::INTSRC0: SPLIE13 Mask */ + +#define EADC_INTSRC0_SPLIE14_Pos (14) /*!< EADC_T::INTSRC0: SPLIE14 Position */ +#define EADC_INTSRC0_SPLIE14_Msk (0x1ul << EADC_INTSRC0_SPLIE14_Pos) /*!< EADC_T::INTSRC0: SPLIE14 Mask */ + +#define EADC_INTSRC0_SPLIE15_Pos (15) /*!< EADC_T::INTSRC0: SPLIE15 Position */ +#define EADC_INTSRC0_SPLIE15_Msk (0x1ul << EADC_INTSRC0_SPLIE15_Pos) /*!< EADC_T::INTSRC0: SPLIE15 Mask */ + +#define EADC_INTSRC0_SPLIE16_Pos (16) /*!< EADC_T::INTSRC0: SPLIE16 Position */ +#define EADC_INTSRC0_SPLIE16_Msk (0x1ul << EADC_INTSRC0_SPLIE16_Pos) /*!< EADC_T::INTSRC0: SPLIE16 Mask */ + +#define EADC_INTSRC0_SPLIE17_Pos (17) /*!< EADC_T::INTSRC0: SPLIE17 Position */ +#define EADC_INTSRC0_SPLIE17_Msk (0x1ul << EADC_INTSRC0_SPLIE17_Pos) /*!< EADC_T::INTSRC0: SPLIE17 Mask */ + +#define EADC_INTSRC0_SPLIE18_Pos (18) /*!< EADC_T::INTSRC0: SPLIE18 Position */ +#define EADC_INTSRC0_SPLIE18_Msk (0x1ul << EADC_INTSRC0_SPLIE18_Pos) /*!< EADC_T::INTSRC0: SPLIE18 Mask */ + +#define EADC_INTSRC1_SPLIE0_Pos (0) /*!< EADC_T::INTSRC1: SPLIE0 Position */ +#define EADC_INTSRC1_SPLIE0_Msk (0x1ul << EADC_INTSRC1_SPLIE0_Pos) /*!< EADC_T::INTSRC1: SPLIE0 Mask */ + +#define EADC_INTSRC1_SPLIE1_Pos (1) /*!< EADC_T::INTSRC1: SPLIE1 Position */ +#define EADC_INTSRC1_SPLIE1_Msk (0x1ul << EADC_INTSRC1_SPLIE1_Pos) /*!< EADC_T::INTSRC1: SPLIE1 Mask */ + +#define EADC_INTSRC1_SPLIE2_Pos (2) /*!< EADC_T::INTSRC1: SPLIE2 Position */ +#define EADC_INTSRC1_SPLIE2_Msk (0x1ul << EADC_INTSRC1_SPLIE2_Pos) /*!< EADC_T::INTSRC1: SPLIE2 Mask */ + +#define EADC_INTSRC1_SPLIE3_Pos (3) /*!< EADC_T::INTSRC1: SPLIE3 Position */ +#define EADC_INTSRC1_SPLIE3_Msk (0x1ul << EADC_INTSRC1_SPLIE3_Pos) /*!< EADC_T::INTSRC1: SPLIE3 Mask */ + +#define EADC_INTSRC1_SPLIE4_Pos (4) /*!< EADC_T::INTSRC1: SPLIE4 Position */ +#define EADC_INTSRC1_SPLIE4_Msk (0x1ul << EADC_INTSRC1_SPLIE4_Pos) /*!< EADC_T::INTSRC1: SPLIE4 Mask */ + +#define EADC_INTSRC1_SPLIE5_Pos (5) /*!< EADC_T::INTSRC1: SPLIE5 Position */ +#define EADC_INTSRC1_SPLIE5_Msk (0x1ul << EADC_INTSRC1_SPLIE5_Pos) /*!< EADC_T::INTSRC1: SPLIE5 Mask */ + +#define EADC_INTSRC1_SPLIE6_Pos (6) /*!< EADC_T::INTSRC1: SPLIE6 Position */ +#define EADC_INTSRC1_SPLIE6_Msk (0x1ul << EADC_INTSRC1_SPLIE6_Pos) /*!< EADC_T::INTSRC1: SPLIE6 Mask */ + +#define EADC_INTSRC1_SPLIE7_Pos (7) /*!< EADC_T::INTSRC1: SPLIE7 Position */ +#define EADC_INTSRC1_SPLIE7_Msk (0x1ul << EADC_INTSRC1_SPLIE7_Pos) /*!< EADC_T::INTSRC1: SPLIE7 Mask */ + +#define EADC_INTSRC1_SPLIE8_Pos (8) /*!< EADC_T::INTSRC1: SPLIE8 Position */ +#define EADC_INTSRC1_SPLIE8_Msk (0x1ul << EADC_INTSRC1_SPLIE8_Pos) /*!< EADC_T::INTSRC1: SPLIE8 Mask */ + +#define EADC_INTSRC1_SPLIE9_Pos (9) /*!< EADC_T::INTSRC1: SPLIE9 Position */ +#define EADC_INTSRC1_SPLIE9_Msk (0x1ul << EADC_INTSRC1_SPLIE9_Pos) /*!< EADC_T::INTSRC1: SPLIE9 Mask */ + +#define EADC_INTSRC1_SPLIE10_Pos (10) /*!< EADC_T::INTSRC1: SPLIE10 Position */ +#define EADC_INTSRC1_SPLIE10_Msk (0x1ul << EADC_INTSRC1_SPLIE10_Pos) /*!< EADC_T::INTSRC1: SPLIE10 Mask */ + +#define EADC_INTSRC1_SPLIE11_Pos (11) /*!< EADC_T::INTSRC1: SPLIE11 Position */ +#define EADC_INTSRC1_SPLIE11_Msk (0x1ul << EADC_INTSRC1_SPLIE11_Pos) /*!< EADC_T::INTSRC1: SPLIE11 Mask */ + +#define EADC_INTSRC1_SPLIE12_Pos (12) /*!< EADC_T::INTSRC1: SPLIE12 Position */ +#define EADC_INTSRC1_SPLIE12_Msk (0x1ul << EADC_INTSRC1_SPLIE12_Pos) /*!< EADC_T::INTSRC1: SPLIE12 Mask */ + +#define EADC_INTSRC1_SPLIE13_Pos (13) /*!< EADC_T::INTSRC1: SPLIE13 Position */ +#define EADC_INTSRC1_SPLIE13_Msk (0x1ul << EADC_INTSRC1_SPLIE13_Pos) /*!< EADC_T::INTSRC1: SPLIE13 Mask */ + +#define EADC_INTSRC1_SPLIE14_Pos (14) /*!< EADC_T::INTSRC1: SPLIE14 Position */ +#define EADC_INTSRC1_SPLIE14_Msk (0x1ul << EADC_INTSRC1_SPLIE14_Pos) /*!< EADC_T::INTSRC1: SPLIE14 Mask */ + +#define EADC_INTSRC1_SPLIE15_Pos (15) /*!< EADC_T::INTSRC1: SPLIE15 Position */ +#define EADC_INTSRC1_SPLIE15_Msk (0x1ul << EADC_INTSRC1_SPLIE15_Pos) /*!< EADC_T::INTSRC1: SPLIE15 Mask */ + +#define EADC_INTSRC1_SPLIE16_Pos (16) /*!< EADC_T::INTSRC1: SPLIE16 Position */ +#define EADC_INTSRC1_SPLIE16_Msk (0x1ul << EADC_INTSRC1_SPLIE16_Pos) /*!< EADC_T::INTSRC1: SPLIE16 Mask */ + +#define EADC_INTSRC1_SPLIE17_Pos (17) /*!< EADC_T::INTSRC1: SPLIE17 Position */ +#define EADC_INTSRC1_SPLIE17_Msk (0x1ul << EADC_INTSRC1_SPLIE17_Pos) /*!< EADC_T::INTSRC1: SPLIE17 Mask */ + +#define EADC_INTSRC1_SPLIE18_Pos (18) /*!< EADC_T::INTSRC1: SPLIE18 Position */ +#define EADC_INTSRC1_SPLIE18_Msk (0x1ul << EADC_INTSRC1_SPLIE18_Pos) /*!< EADC_T::INTSRC1: SPLIE18 Mask */ + +#define EADC_INTSRC2_SPLIE0_Pos (0) /*!< EADC_T::INTSRC2: SPLIE0 Position */ +#define EADC_INTSRC2_SPLIE0_Msk (0x1ul << EADC_INTSRC2_SPLIE0_Pos) /*!< EADC_T::INTSRC2: SPLIE0 Mask */ + +#define EADC_INTSRC2_SPLIE1_Pos (1) /*!< EADC_T::INTSRC2: SPLIE1 Position */ +#define EADC_INTSRC2_SPLIE1_Msk (0x1ul << EADC_INTSRC2_SPLIE1_Pos) /*!< EADC_T::INTSRC2: SPLIE1 Mask */ + +#define EADC_INTSRC2_SPLIE2_Pos (2) /*!< EADC_T::INTSRC2: SPLIE2 Position */ +#define EADC_INTSRC2_SPLIE2_Msk (0x1ul << EADC_INTSRC2_SPLIE2_Pos) /*!< EADC_T::INTSRC2: SPLIE2 Mask */ + +#define EADC_INTSRC2_SPLIE3_Pos (3) /*!< EADC_T::INTSRC2: SPLIE3 Position */ +#define EADC_INTSRC2_SPLIE3_Msk (0x1ul << EADC_INTSRC2_SPLIE3_Pos) /*!< EADC_T::INTSRC2: SPLIE3 Mask */ + +#define EADC_INTSRC2_SPLIE4_Pos (4) /*!< EADC_T::INTSRC2: SPLIE4 Position */ +#define EADC_INTSRC2_SPLIE4_Msk (0x1ul << EADC_INTSRC2_SPLIE4_Pos) /*!< EADC_T::INTSRC2: SPLIE4 Mask */ + +#define EADC_INTSRC2_SPLIE5_Pos (5) /*!< EADC_T::INTSRC2: SPLIE5 Position */ +#define EADC_INTSRC2_SPLIE5_Msk (0x1ul << EADC_INTSRC2_SPLIE5_Pos) /*!< EADC_T::INTSRC2: SPLIE5 Mask */ + +#define EADC_INTSRC2_SPLIE6_Pos (6) /*!< EADC_T::INTSRC2: SPLIE6 Position */ +#define EADC_INTSRC2_SPLIE6_Msk (0x1ul << EADC_INTSRC2_SPLIE6_Pos) /*!< EADC_T::INTSRC2: SPLIE6 Mask */ + +#define EADC_INTSRC2_SPLIE7_Pos (7) /*!< EADC_T::INTSRC2: SPLIE7 Position */ +#define EADC_INTSRC2_SPLIE7_Msk (0x1ul << EADC_INTSRC2_SPLIE7_Pos) /*!< EADC_T::INTSRC2: SPLIE7 Mask */ + +#define EADC_INTSRC2_SPLIE8_Pos (8) /*!< EADC_T::INTSRC2: SPLIE8 Position */ +#define EADC_INTSRC2_SPLIE8_Msk (0x1ul << EADC_INTSRC2_SPLIE8_Pos) /*!< EADC_T::INTSRC2: SPLIE8 Mask */ + +#define EADC_INTSRC2_SPLIE9_Pos (9) /*!< EADC_T::INTSRC2: SPLIE9 Position */ +#define EADC_INTSRC2_SPLIE9_Msk (0x1ul << EADC_INTSRC2_SPLIE9_Pos) /*!< EADC_T::INTSRC2: SPLIE9 Mask */ + +#define EADC_INTSRC2_SPLIE10_Pos (10) /*!< EADC_T::INTSRC2: SPLIE10 Position */ +#define EADC_INTSRC2_SPLIE10_Msk (0x1ul << EADC_INTSRC2_SPLIE10_Pos) /*!< EADC_T::INTSRC2: SPLIE10 Mask */ + +#define EADC_INTSRC2_SPLIE11_Pos (11) /*!< EADC_T::INTSRC2: SPLIE11 Position */ +#define EADC_INTSRC2_SPLIE11_Msk (0x1ul << EADC_INTSRC2_SPLIE11_Pos) /*!< EADC_T::INTSRC2: SPLIE11 Mask */ + +#define EADC_INTSRC2_SPLIE12_Pos (12) /*!< EADC_T::INTSRC2: SPLIE12 Position */ +#define EADC_INTSRC2_SPLIE12_Msk (0x1ul << EADC_INTSRC2_SPLIE12_Pos) /*!< EADC_T::INTSRC2: SPLIE12 Mask */ + +#define EADC_INTSRC2_SPLIE13_Pos (13) /*!< EADC_T::INTSRC2: SPLIE13 Position */ +#define EADC_INTSRC2_SPLIE13_Msk (0x1ul << EADC_INTSRC2_SPLIE13_Pos) /*!< EADC_T::INTSRC2: SPLIE13 Mask */ + +#define EADC_INTSRC2_SPLIE14_Pos (14) /*!< EADC_T::INTSRC2: SPLIE14 Position */ +#define EADC_INTSRC2_SPLIE14_Msk (0x1ul << EADC_INTSRC2_SPLIE14_Pos) /*!< EADC_T::INTSRC2: SPLIE14 Mask */ + +#define EADC_INTSRC2_SPLIE15_Pos (15) /*!< EADC_T::INTSRC2: SPLIE15 Position */ +#define EADC_INTSRC2_SPLIE15_Msk (0x1ul << EADC_INTSRC2_SPLIE15_Pos) /*!< EADC_T::INTSRC2: SPLIE15 Mask */ + +#define EADC_INTSRC2_SPLIE16_Pos (16) /*!< EADC_T::INTSRC2: SPLIE16 Position */ +#define EADC_INTSRC2_SPLIE16_Msk (0x1ul << EADC_INTSRC2_SPLIE16_Pos) /*!< EADC_T::INTSRC2: SPLIE16 Mask */ + +#define EADC_INTSRC2_SPLIE17_Pos (17) /*!< EADC_T::INTSRC2: SPLIE17 Position */ +#define EADC_INTSRC2_SPLIE17_Msk (0x1ul << EADC_INTSRC2_SPLIE17_Pos) /*!< EADC_T::INTSRC2: SPLIE17 Mask */ + +#define EADC_INTSRC2_SPLIE18_Pos (18) /*!< EADC_T::INTSRC2: SPLIE18 Position */ +#define EADC_INTSRC2_SPLIE18_Msk (0x1ul << EADC_INTSRC2_SPLIE18_Pos) /*!< EADC_T::INTSRC2: SPLIE18 Mask */ + +#define EADC_INTSRC3_SPLIE0_Pos (0) /*!< EADC_T::INTSRC3: SPLIE0 Position */ +#define EADC_INTSRC3_SPLIE0_Msk (0x1ul << EADC_INTSRC3_SPLIE0_Pos) /*!< EADC_T::INTSRC3: SPLIE0 Mask */ + +#define EADC_INTSRC3_SPLIE1_Pos (1) /*!< EADC_T::INTSRC3: SPLIE1 Position */ +#define EADC_INTSRC3_SPLIE1_Msk (0x1ul << EADC_INTSRC3_SPLIE1_Pos) /*!< EADC_T::INTSRC3: SPLIE1 Mask */ + +#define EADC_INTSRC3_SPLIE2_Pos (2) /*!< EADC_T::INTSRC3: SPLIE2 Position */ +#define EADC_INTSRC3_SPLIE2_Msk (0x1ul << EADC_INTSRC3_SPLIE2_Pos) /*!< EADC_T::INTSRC3: SPLIE2 Mask */ + +#define EADC_INTSRC3_SPLIE3_Pos (3) /*!< EADC_T::INTSRC3: SPLIE3 Position */ +#define EADC_INTSRC3_SPLIE3_Msk (0x1ul << EADC_INTSRC3_SPLIE3_Pos) /*!< EADC_T::INTSRC3: SPLIE3 Mask */ + +#define EADC_INTSRC3_SPLIE4_Pos (4) /*!< EADC_T::INTSRC3: SPLIE4 Position */ +#define EADC_INTSRC3_SPLIE4_Msk (0x1ul << EADC_INTSRC3_SPLIE4_Pos) /*!< EADC_T::INTSRC3: SPLIE4 Mask */ + +#define EADC_INTSRC3_SPLIE5_Pos (5) /*!< EADC_T::INTSRC3: SPLIE5 Position */ +#define EADC_INTSRC3_SPLIE5_Msk (0x1ul << EADC_INTSRC3_SPLIE5_Pos) /*!< EADC_T::INTSRC3: SPLIE5 Mask */ + +#define EADC_INTSRC3_SPLIE6_Pos (6) /*!< EADC_T::INTSRC3: SPLIE6 Position */ +#define EADC_INTSRC3_SPLIE6_Msk (0x1ul << EADC_INTSRC3_SPLIE6_Pos) /*!< EADC_T::INTSRC3: SPLIE6 Mask */ + +#define EADC_INTSRC3_SPLIE7_Pos (7) /*!< EADC_T::INTSRC3: SPLIE7 Position */ +#define EADC_INTSRC3_SPLIE7_Msk (0x1ul << EADC_INTSRC3_SPLIE7_Pos) /*!< EADC_T::INTSRC3: SPLIE7 Mask */ + +#define EADC_INTSRC3_SPLIE8_Pos (8) /*!< EADC_T::INTSRC3: SPLIE8 Position */ +#define EADC_INTSRC3_SPLIE8_Msk (0x1ul << EADC_INTSRC3_SPLIE8_Pos) /*!< EADC_T::INTSRC3: SPLIE8 Mask */ + +#define EADC_INTSRC3_SPLIE9_Pos (9) /*!< EADC_T::INTSRC3: SPLIE9 Position */ +#define EADC_INTSRC3_SPLIE9_Msk (0x1ul << EADC_INTSRC3_SPLIE9_Pos) /*!< EADC_T::INTSRC3: SPLIE9 Mask */ + +#define EADC_INTSRC3_SPLIE10_Pos (10) /*!< EADC_T::INTSRC3: SPLIE10 Position */ +#define EADC_INTSRC3_SPLIE10_Msk (0x1ul << EADC_INTSRC3_SPLIE10_Pos) /*!< EADC_T::INTSRC3: SPLIE10 Mask */ + +#define EADC_INTSRC3_SPLIE11_Pos (11) /*!< EADC_T::INTSRC3: SPLIE11 Position */ +#define EADC_INTSRC3_SPLIE11_Msk (0x1ul << EADC_INTSRC3_SPLIE11_Pos) /*!< EADC_T::INTSRC3: SPLIE11 Mask */ + +#define EADC_INTSRC3_SPLIE12_Pos (12) /*!< EADC_T::INTSRC3: SPLIE12 Position */ +#define EADC_INTSRC3_SPLIE12_Msk (0x1ul << EADC_INTSRC3_SPLIE12_Pos) /*!< EADC_T::INTSRC3: SPLIE12 Mask */ + +#define EADC_INTSRC3_SPLIE13_Pos (13) /*!< EADC_T::INTSRC3: SPLIE13 Position */ +#define EADC_INTSRC3_SPLIE13_Msk (0x1ul << EADC_INTSRC3_SPLIE13_Pos) /*!< EADC_T::INTSRC3: SPLIE13 Mask */ + +#define EADC_INTSRC3_SPLIE14_Pos (14) /*!< EADC_T::INTSRC3: SPLIE14 Position */ +#define EADC_INTSRC3_SPLIE14_Msk (0x1ul << EADC_INTSRC3_SPLIE14_Pos) /*!< EADC_T::INTSRC3: SPLIE14 Mask */ + +#define EADC_INTSRC3_SPLIE15_Pos (15) /*!< EADC_T::INTSRC3: SPLIE15 Position */ +#define EADC_INTSRC3_SPLIE15_Msk (0x1ul << EADC_INTSRC3_SPLIE15_Pos) /*!< EADC_T::INTSRC3: SPLIE15 Mask */ + +#define EADC_INTSRC3_SPLIE16_Pos (16) /*!< EADC_T::INTSRC3: SPLIE16 Position */ +#define EADC_INTSRC3_SPLIE16_Msk (0x1ul << EADC_INTSRC3_SPLIE16_Pos) /*!< EADC_T::INTSRC3: SPLIE16 Mask */ + +#define EADC_INTSRC3_SPLIE17_Pos (17) /*!< EADC_T::INTSRC3: SPLIE17 Position */ +#define EADC_INTSRC3_SPLIE17_Msk (0x1ul << EADC_INTSRC3_SPLIE17_Pos) /*!< EADC_T::INTSRC3: SPLIE17 Mask */ + +#define EADC_INTSRC3_SPLIE18_Pos (18) /*!< EADC_T::INTSRC3: SPLIE18 Position */ +#define EADC_INTSRC3_SPLIE18_Msk (0x1ul << EADC_INTSRC3_SPLIE18_Pos) /*!< EADC_T::INTSRC3: SPLIE18 Mask */ + +#define EADC_CMP_ADCMPEN_Pos (0) /*!< EADC_T::CMP: ADCMPEN Position */ +#define EADC_CMP_ADCMPEN_Msk (0x1ul << EADC_CMP_ADCMPEN_Pos) /*!< EADC_T::CMP: ADCMPEN Mask */ + +#define EADC_CMP_ADCMPIE_Pos (1) /*!< EADC_T::CMP: ADCMPIE Position */ +#define EADC_CMP_ADCMPIE_Msk (0x1ul << EADC_CMP_ADCMPIE_Pos) /*!< EADC_T::CMP: ADCMPIE Mask */ + +#define EADC_CMP_CMPCOND_Pos (2) /*!< EADC_T::CMP: CMPCOND Position */ +#define EADC_CMP_CMPCOND_Msk (0x1ul << EADC_CMP_CMPCOND_Pos) /*!< EADC_T::CMP: CMPCOND Mask */ + +#define EADC_CMP_CMPSPL_Pos (3) /*!< EADC_T::CMP: CMPSPL Position */ +#define EADC_CMP_CMPSPL_Msk (0x1ful << EADC_CMP_CMPSPL_Pos) /*!< EADC_T::CMP: CMPSPL Mask */ + +#define EADC_CMP_CMPMCNT_Pos (8) /*!< EADC_T::CMP: CMPMCNT Position */ +#define EADC_CMP_CMPMCNT_Msk (0xful << EADC_CMP_CMPMCNT_Pos) /*!< EADC_T::CMP: CMPMCNT Mask */ + +#define EADC_CMP_CMPWEN_Pos (15) /*!< EADC_T::CMP: CMPWEN Position */ +#define EADC_CMP_CMPWEN_Msk (0x1ul << EADC_CMP_CMPWEN_Pos) /*!< EADC_T::CMP: CMPWEN Mask */ + +#define EADC_CMP_CMPDAT_Pos (16) /*!< EADC_T::CMP: CMPDAT Position */ +#define EADC_CMP_CMPDAT_Msk (0xffful << EADC_CMP_CMPDAT_Pos) /*!< EADC_T::CMP: CMPDAT Mask */ + +#define EADC_CMP0_ADCMPEN_Pos (0) /*!< EADC_T::CMP0: ADCMPEN Position */ +#define EADC_CMP0_ADCMPEN_Msk (0x1ul << EADC_CMP0_ADCMPEN_Pos) /*!< EADC_T::CMP0: ADCMPEN Mask */ + +#define EADC_CMP0_ADCMPIE_Pos (1) /*!< EADC_T::CMP0: ADCMPIE Position */ +#define EADC_CMP0_ADCMPIE_Msk (0x1ul << EADC_CMP0_ADCMPIE_Pos) /*!< EADC_T::CMP0: ADCMPIE Mask */ + +#define EADC_CMP0_CMPCOND_Pos (2) /*!< EADC_T::CMP0: CMPCOND Position */ +#define EADC_CMP0_CMPCOND_Msk (0x1ul << EADC_CMP0_CMPCOND_Pos) /*!< EADC_T::CMP0: CMPCOND Mask */ + +#define EADC_CMP0_CMPSPL_Pos (3) /*!< EADC_T::CMP0: CMPSPL Position */ +#define EADC_CMP0_CMPSPL_Msk (0x1ful << EADC_CMP0_CMPSPL_Pos) /*!< EADC_T::CMP0: CMPSPL Mask */ + +#define EADC_CMP0_CMPMCNT_Pos (8) /*!< EADC_T::CMP0: CMPMCNT Position */ +#define EADC_CMP0_CMPMCNT_Msk (0xful << EADC_CMP0_CMPMCNT_Pos) /*!< EADC_T::CMP0: CMPMCNT Mask */ + +#define EADC_CMP0_CMPWEN_Pos (15) /*!< EADC_T::CMP0: CMPWEN Position */ +#define EADC_CMP0_CMPWEN_Msk (0x1ul << EADC_CMP0_CMPWEN_Pos) /*!< EADC_T::CMP0: CMPWEN Mask */ + +#define EADC_CMP0_CMPDAT_Pos (16) /*!< EADC_T::CMP0: CMPDAT Position */ +#define EADC_CMP0_CMPDAT_Msk (0xffful << EADC_CMP0_CMPDAT_Pos) /*!< EADC_T::CMP0: CMPDAT Mask */ + +#define EADC_CMP1_ADCMPEN_Pos (0) /*!< EADC_T::CMP1: ADCMPEN Position */ +#define EADC_CMP1_ADCMPEN_Msk (0x1ul << EADC_CMP1_ADCMPEN_Pos) /*!< EADC_T::CMP1: ADCMPEN Mask */ + +#define EADC_CMP1_ADCMPIE_Pos (1) /*!< EADC_T::CMP1: ADCMPIE Position */ +#define EADC_CMP1_ADCMPIE_Msk (0x1ul << EADC_CMP1_ADCMPIE_Pos) /*!< EADC_T::CMP1: ADCMPIE Mask */ + +#define EADC_CMP1_CMPCOND_Pos (2) /*!< EADC_T::CMP1: CMPCOND Position */ +#define EADC_CMP1_CMPCOND_Msk (0x1ul << EADC_CMP1_CMPCOND_Pos) /*!< EADC_T::CMP1: CMPCOND Mask */ + +#define EADC_CMP1_CMPSPL_Pos (3) /*!< EADC_T::CMP1: CMPSPL Position */ +#define EADC_CMP1_CMPSPL_Msk (0x1ful << EADC_CMP1_CMPSPL_Pos) /*!< EADC_T::CMP1: CMPSPL Mask */ + +#define EADC_CMP1_CMPMCNT_Pos (8) /*!< EADC_T::CMP1: CMPMCNT Position */ +#define EADC_CMP1_CMPMCNT_Msk (0xful << EADC_CMP1_CMPMCNT_Pos) /*!< EADC_T::CMP1: CMPMCNT Mask */ + +#define EADC_CMP1_CMPWEN_Pos (15) /*!< EADC_T::CMP1: CMPWEN Position */ +#define EADC_CMP1_CMPWEN_Msk (0x1ul << EADC_CMP1_CMPWEN_Pos) /*!< EADC_T::CMP1: CMPWEN Mask */ + +#define EADC_CMP1_CMPDAT_Pos (16) /*!< EADC_T::CMP1: CMPDAT Position */ +#define EADC_CMP1_CMPDAT_Msk (0xffful << EADC_CMP1_CMPDAT_Pos) /*!< EADC_T::CMP1: CMPDAT Mask */ + +#define EADC_CMP2_ADCMPEN_Pos (0) /*!< EADC_T::CMP2: ADCMPEN Position */ +#define EADC_CMP2_ADCMPEN_Msk (0x1ul << EADC_CMP2_ADCMPEN_Pos) /*!< EADC_T::CMP2: ADCMPEN Mask */ + +#define EADC_CMP2_ADCMPIE_Pos (1) /*!< EADC_T::CMP2: ADCMPIE Position */ +#define EADC_CMP2_ADCMPIE_Msk (0x1ul << EADC_CMP2_ADCMPIE_Pos) /*!< EADC_T::CMP2: ADCMPIE Mask */ + +#define EADC_CMP2_CMPCOND_Pos (2) /*!< EADC_T::CMP2: CMPCOND Position */ +#define EADC_CMP2_CMPCOND_Msk (0x1ul << EADC_CMP2_CMPCOND_Pos) /*!< EADC_T::CMP2: CMPCOND Mask */ + +#define EADC_CMP2_CMPSPL_Pos (3) /*!< EADC_T::CMP2: CMPSPL Position */ +#define EADC_CMP2_CMPSPL_Msk (0x1ful << EADC_CMP2_CMPSPL_Pos) /*!< EADC_T::CMP2: CMPSPL Mask */ + +#define EADC_CMP2_CMPMCNT_Pos (8) /*!< EADC_T::CMP2: CMPMCNT Position */ +#define EADC_CMP2_CMPMCNT_Msk (0xful << EADC_CMP2_CMPMCNT_Pos) /*!< EADC_T::CMP2: CMPMCNT Mask */ + +#define EADC_CMP2_CMPWEN_Pos (15) /*!< EADC_T::CMP2: CMPWEN Position */ +#define EADC_CMP2_CMPWEN_Msk (0x1ul << EADC_CMP2_CMPWEN_Pos) /*!< EADC_T::CMP2: CMPWEN Mask */ + +#define EADC_CMP2_CMPDAT_Pos (16) /*!< EADC_T::CMP2: CMPDAT Position */ +#define EADC_CMP2_CMPDAT_Msk (0xffful << EADC_CMP2_CMPDAT_Pos) /*!< EADC_T::CMP2: CMPDAT Mask */ + +#define EADC_CMP3_ADCMPEN_Pos (0) /*!< EADC_T::CMP3: ADCMPEN Position */ +#define EADC_CMP3_ADCMPEN_Msk (0x1ul << EADC_CMP3_ADCMPEN_Pos) /*!< EADC_T::CMP3: ADCMPEN Mask */ + +#define EADC_CMP3_ADCMPIE_Pos (1) /*!< EADC_T::CMP3: ADCMPIE Position */ +#define EADC_CMP3_ADCMPIE_Msk (0x1ul << EADC_CMP3_ADCMPIE_Pos) /*!< EADC_T::CMP3: ADCMPIE Mask */ + +#define EADC_CMP3_CMPCOND_Pos (2) /*!< EADC_T::CMP3: CMPCOND Position */ +#define EADC_CMP3_CMPCOND_Msk (0x1ul << EADC_CMP3_CMPCOND_Pos) /*!< EADC_T::CMP3: CMPCOND Mask */ + +#define EADC_CMP3_CMPSPL_Pos (3) /*!< EADC_T::CMP3: CMPSPL Position */ +#define EADC_CMP3_CMPSPL_Msk (0x1ful << EADC_CMP3_CMPSPL_Pos) /*!< EADC_T::CMP3: CMPSPL Mask */ + +#define EADC_CMP3_CMPMCNT_Pos (8) /*!< EADC_T::CMP3: CMPMCNT Position */ +#define EADC_CMP3_CMPMCNT_Msk (0xful << EADC_CMP3_CMPMCNT_Pos) /*!< EADC_T::CMP3: CMPMCNT Mask */ + +#define EADC_CMP3_CMPWEN_Pos (15) /*!< EADC_T::CMP3: CMPWEN Position */ +#define EADC_CMP3_CMPWEN_Msk (0x1ul << EADC_CMP3_CMPWEN_Pos) /*!< EADC_T::CMP3: CMPWEN Mask */ + +#define EADC_CMP3_CMPDAT_Pos (16) /*!< EADC_T::CMP3: CMPDAT Position */ +#define EADC_CMP3_CMPDAT_Msk (0xffful << EADC_CMP3_CMPDAT_Pos) /*!< EADC_T::CMP3: CMPDAT Mask */ + +#define EADC_STATUS0_VALID_Pos (0) /*!< EADC_T::STATUS0: VALID Position */ +#define EADC_STATUS0_VALID_Msk (0xfffful << EADC_STATUS0_VALID_Pos) /*!< EADC_T::STATUS0: VALID Mask */ + +#define EADC_STATUS0_OV_Pos (16) /*!< EADC_T::STATUS0: OV Position */ +#define EADC_STATUS0_OV_Msk (0xfffful << EADC_STATUS0_OV_Pos) /*!< EADC_T::STATUS0: OV Mask */ + +#define EADC_STATUS1_VALID_Pos (0) /*!< EADC_T::STATUS1: VALID Position */ +#define EADC_STATUS1_VALID_Msk (0x7ul << EADC_STATUS1_VALID_Pos) /*!< EADC_T::STATUS1: VALID Mask */ + +#define EADC_STATUS1_OV_Pos (16) /*!< EADC_T::STATUS1: OV Position */ +#define EADC_STATUS1_OV_Msk (0x7ul << EADC_STATUS1_OV_Pos) /*!< EADC_T::STATUS1: OV Mask */ + +#define EADC_STATUS2_ADIF0_Pos (0) /*!< EADC_T::STATUS2: ADIF0 Position */ +#define EADC_STATUS2_ADIF0_Msk (0x1ul << EADC_STATUS2_ADIF0_Pos) /*!< EADC_T::STATUS2: ADIF0 Mask */ + +#define EADC_STATUS2_ADIF1_Pos (1) /*!< EADC_T::STATUS2: ADIF1 Position */ +#define EADC_STATUS2_ADIF1_Msk (0x1ul << EADC_STATUS2_ADIF1_Pos) /*!< EADC_T::STATUS2: ADIF1 Mask */ + +#define EADC_STATUS2_ADIF2_Pos (2) /*!< EADC_T::STATUS2: ADIF2 Position */ +#define EADC_STATUS2_ADIF2_Msk (0x1ul << EADC_STATUS2_ADIF2_Pos) /*!< EADC_T::STATUS2: ADIF2 Mask */ + +#define EADC_STATUS2_ADIF3_Pos (3) /*!< EADC_T::STATUS2: ADIF3 Position */ +#define EADC_STATUS2_ADIF3_Msk (0x1ul << EADC_STATUS2_ADIF3_Pos) /*!< EADC_T::STATUS2: ADIF3 Mask */ + +#define EADC_STATUS2_ADCMPF0_Pos (4) /*!< EADC_T::STATUS2: ADCMPF0 Position */ +#define EADC_STATUS2_ADCMPF0_Msk (0x1ul << EADC_STATUS2_ADCMPF0_Pos) /*!< EADC_T::STATUS2: ADCMPF0 Mask */ + +#define EADC_STATUS2_ADCMPF1_Pos (5) /*!< EADC_T::STATUS2: ADCMPF1 Position */ +#define EADC_STATUS2_ADCMPF1_Msk (0x1ul << EADC_STATUS2_ADCMPF1_Pos) /*!< EADC_T::STATUS2: ADCMPF1 Mask */ + +#define EADC_STATUS2_ADCMPF2_Pos (6) /*!< EADC_T::STATUS2: ADCMPF2 Position */ +#define EADC_STATUS2_ADCMPF2_Msk (0x1ul << EADC_STATUS2_ADCMPF2_Pos) /*!< EADC_T::STATUS2: ADCMPF2 Mask */ + +#define EADC_STATUS2_ADCMPF3_Pos (7) /*!< EADC_T::STATUS2: ADCMPF3 Position */ +#define EADC_STATUS2_ADCMPF3_Msk (0x1ul << EADC_STATUS2_ADCMPF3_Pos) /*!< EADC_T::STATUS2: ADCMPF3 Mask */ + +#define EADC_STATUS2_ADOVIF0_Pos (8) /*!< EADC_T::STATUS2: ADOVIF0 Position */ +#define EADC_STATUS2_ADOVIF0_Msk (0x1ul << EADC_STATUS2_ADOVIF0_Pos) /*!< EADC_T::STATUS2: ADOVIF0 Mask */ + +#define EADC_STATUS2_ADOVIF1_Pos (9) /*!< EADC_T::STATUS2: ADOVIF1 Position */ +#define EADC_STATUS2_ADOVIF1_Msk (0x1ul << EADC_STATUS2_ADOVIF1_Pos) /*!< EADC_T::STATUS2: ADOVIF1 Mask */ + +#define EADC_STATUS2_ADOVIF2_Pos (10) /*!< EADC_T::STATUS2: ADOVIF2 Position */ +#define EADC_STATUS2_ADOVIF2_Msk (0x1ul << EADC_STATUS2_ADOVIF2_Pos) /*!< EADC_T::STATUS2: ADOVIF2 Mask */ + +#define EADC_STATUS2_ADOVIF3_Pos (11) /*!< EADC_T::STATUS2: ADOVIF3 Position */ +#define EADC_STATUS2_ADOVIF3_Msk (0x1ul << EADC_STATUS2_ADOVIF3_Pos) /*!< EADC_T::STATUS2: ADOVIF3 Mask */ + +#define EADC_STATUS2_ADCMPO0_Pos (12) /*!< EADC_T::STATUS2: ADCMPO0 Position */ +#define EADC_STATUS2_ADCMPO0_Msk (0x1ul << EADC_STATUS2_ADCMPO0_Pos) /*!< EADC_T::STATUS2: ADCMPO0 Mask */ + +#define EADC_STATUS2_ADCMPO1_Pos (13) /*!< EADC_T::STATUS2: ADCMPO1 Position */ +#define EADC_STATUS2_ADCMPO1_Msk (0x1ul << EADC_STATUS2_ADCMPO1_Pos) /*!< EADC_T::STATUS2: ADCMPO1 Mask */ + +#define EADC_STATUS2_ADCMPO2_Pos (14) /*!< EADC_T::STATUS2: ADCMPO2 Position */ +#define EADC_STATUS2_ADCMPO2_Msk (0x1ul << EADC_STATUS2_ADCMPO2_Pos) /*!< EADC_T::STATUS2: ADCMPO2 Mask */ + +#define EADC_STATUS2_ADCMPO3_Pos (15) /*!< EADC_T::STATUS2: ADCMPO3 Position */ +#define EADC_STATUS2_ADCMPO3_Msk (0x1ul << EADC_STATUS2_ADCMPO3_Pos) /*!< EADC_T::STATUS2: ADCMPO3 Mask */ + +#define EADC_STATUS2_CHANNEL_Pos (16) /*!< EADC_T::STATUS2: CHANNEL Position */ +#define EADC_STATUS2_CHANNEL_Msk (0x1ful << EADC_STATUS2_CHANNEL_Pos) /*!< EADC_T::STATUS2: CHANNEL Mask */ + +#define EADC_STATUS2_BUSY_Pos (23) /*!< EADC_T::STATUS2: BUSY Position */ +#define EADC_STATUS2_BUSY_Msk (0x1ul << EADC_STATUS2_BUSY_Pos) /*!< EADC_T::STATUS2: BUSY Mask */ + +#define EADC_STATUS2_ADOVIF_Pos (24) /*!< EADC_T::STATUS2: ADOVIF Position */ +#define EADC_STATUS2_ADOVIF_Msk (0x1ul << EADC_STATUS2_ADOVIF_Pos) /*!< EADC_T::STATUS2: ADOVIF Mask */ + +#define EADC_STATUS2_STOVF_Pos (25) /*!< EADC_T::STATUS2: STOVF Position */ +#define EADC_STATUS2_STOVF_Msk (0x1ul << EADC_STATUS2_STOVF_Pos) /*!< EADC_T::STATUS2: STOVF Mask */ + +#define EADC_STATUS2_AVALID_Pos (26) /*!< EADC_T::STATUS2: AVALID Position */ +#define EADC_STATUS2_AVALID_Msk (0x1ul << EADC_STATUS2_AVALID_Pos) /*!< EADC_T::STATUS2: AVALID Mask */ + +#define EADC_STATUS2_AOV_Pos (27) /*!< EADC_T::STATUS2: AOV Position */ +#define EADC_STATUS2_AOV_Msk (0x1ul << EADC_STATUS2_AOV_Pos) /*!< EADC_T::STATUS2: AOV Mask */ + +#define EADC_STATUS3_CURSPL_Pos (0) /*!< EADC_T::STATUS3: CURSPL Position */ +#define EADC_STATUS3_CURSPL_Msk (0x1ful << EADC_STATUS3_CURSPL_Pos) /*!< EADC_T::STATUS3: CURSPL Mask */ + +#define EADC_DDAT0_RESULT_Pos (0) /*!< EADC_T::DDAT0: RESULT Position */ +#define EADC_DDAT0_RESULT_Msk (0xfffful << EADC_DDAT0_RESULT_Pos) /*!< EADC_T::DDAT0: RESULT Mask */ + +#define EADC_DDAT0_OV_Pos (16) /*!< EADC_T::DDAT0: OV Position */ +#define EADC_DDAT0_OV_Msk (0x1ul << EADC_DDAT0_OV_Pos) /*!< EADC_T::DDAT0: OV Mask */ + +#define EADC_DDAT0_VALID_Pos (17) /*!< EADC_T::DDAT0: VALID Position */ +#define EADC_DDAT0_VALID_Msk (0x1ul << EADC_DDAT0_VALID_Pos) /*!< EADC_T::DDAT0: VALID Mask */ + +#define EADC_DDAT1_RESULT_Pos (0) /*!< EADC_T::DDAT1: RESULT Position */ +#define EADC_DDAT1_RESULT_Msk (0xfffful << EADC_DDAT1_RESULT_Pos) /*!< EADC_T::DDAT1: RESULT Mask */ + +#define EADC_DDAT1_OV_Pos (16) /*!< EADC_T::DDAT1: OV Position */ +#define EADC_DDAT1_OV_Msk (0x1ul << EADC_DDAT1_OV_Pos) /*!< EADC_T::DDAT1: OV Mask */ + +#define EADC_DDAT1_VALID_Pos (17) /*!< EADC_T::DDAT1: VALID Position */ +#define EADC_DDAT1_VALID_Msk (0x1ul << EADC_DDAT1_VALID_Pos) /*!< EADC_T::DDAT1: VALID Mask */ + +#define EADC_DDAT2_RESULT_Pos (0) /*!< EADC_T::DDAT2: RESULT Position */ +#define EADC_DDAT2_RESULT_Msk (0xfffful << EADC_DDAT2_RESULT_Pos) /*!< EADC_T::DDAT2: RESULT Mask */ + +#define EADC_DDAT2_OV_Pos (16) /*!< EADC_T::DDAT2: OV Position */ +#define EADC_DDAT2_OV_Msk (0x1ul << EADC_DDAT2_OV_Pos) /*!< EADC_T::DDAT2: OV Mask */ + +#define EADC_DDAT2_VALID_Pos (17) /*!< EADC_T::DDAT2: VALID Position */ +#define EADC_DDAT2_VALID_Msk (0x1ul << EADC_DDAT2_VALID_Pos) /*!< EADC_T::DDAT2: VALID Mask */ + +#define EADC_DDAT3_RESULT_Pos (0) /*!< EADC_T::DDAT3: RESULT Position */ +#define EADC_DDAT3_RESULT_Msk (0xfffful << EADC_DDAT3_RESULT_Pos) /*!< EADC_T::DDAT3: RESULT Mask */ + +#define EADC_DDAT3_OV_Pos (16) /*!< EADC_T::DDAT3: OV Position */ +#define EADC_DDAT3_OV_Msk (0x1ul << EADC_DDAT3_OV_Pos) /*!< EADC_T::DDAT3: OV Mask */ + +#define EADC_DDAT3_VALID_Pos (17) /*!< EADC_T::DDAT3: VALID Position */ +#define EADC_DDAT3_VALID_Msk (0x1ul << EADC_DDAT3_VALID_Pos) /*!< EADC_T::DDAT3: VALID Mask */ + +#define EADC_PWRM_PWUPRDY_Pos (0) /*!< EADC_T::PWRM: PWUPRDY Position */ +#define EADC_PWRM_PWUPRDY_Msk (0x1ul << EADC_PWRM_PWUPRDY_Pos) /*!< EADC_T::PWRM: PWUPRDY Mask */ + +#define EADC_PWRM_PWUCALEN_Pos (1) /*!< EADC_T::PWRM: PWUCALEN Position */ +#define EADC_PWRM_PWUCALEN_Msk (0x1ul << EADC_PWRM_PWUCALEN_Pos) /*!< EADC_T::PWRM: PWUCALEN Mask */ + +#define EADC_PWRM_PWDMOD_Pos (2) /*!< EADC_T::PWRM: PWDMOD Position */ +#define EADC_PWRM_PWDMOD_Msk (0x3ul << EADC_PWRM_PWDMOD_Pos) /*!< EADC_T::PWRM: PWDMOD Mask */ + +#define EADC_PWRM_LDOSUT_Pos (8) /*!< EADC_T::PWRM: LDOSUT Position */ +#define EADC_PWRM_LDOSUT_Msk (0xffful << EADC_PWRM_LDOSUT_Pos) /*!< EADC_T::PWRM: LDOSUT Mask */ + +#define EADC_CALCTL_CALSTART_Pos (1) /*!< EADC_T::CALCTL: CALSTART Position */ +#define EADC_CALCTL_CALSTART_Msk (0x1ul << EADC_CALCTL_CALSTART_Pos) /*!< EADC_T::CALCTL: CALSTART Mask */ + +#define EADC_CALCTL_CALDONE_Pos (2) /*!< EADC_T::CALCTL: CALDONE Position */ +#define EADC_CALCTL_CALDONE_Msk (0x1ul << EADC_CALCTL_CALDONE_Pos) /*!< EADC_T::CALCTL: CALDONE Mask */ + +#define EADC_CALCTL_CALSEL_Pos (3) /*!< EADC_T::CALCTL: CALSEL Position */ +#define EADC_CALCTL_CALSEL_Msk (0x1ul << EADC_CALCTL_CALSEL_Pos) /*!< EADC_T::CALCTL: CALSEL Mask */ + +#define EADC_CALDWRD_CALWORD_Pos (0) /*!< EADC_T::CALDWRD: CALWORD Position */ +#define EADC_CALDWRD_CALWORD_Msk (0x7ful << EADC_CALDWRD_CALWORD_Pos) /*!< EADC_T::CALDWRD: CALWORD Mask */ + +/**@}*/ /* EADC_CONST */ +/**@}*/ /* end of EADC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __EADC_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/ebi_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/ebi_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..9a48d3c286ddbdcc2f6726fe199c5c3c5f352a5e --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/ebi_reg.h @@ -0,0 +1,429 @@ +/**************************************************************************//** + * @file ebi_reg.h + * @version V1.00 + * @brief EBI register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EBI_REG_H__ +#define __EBI_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup EBI External Bus Interface Controller(EBI) + Memory Mapped Structure for EBI Controller +@{ */ + +typedef struct +{ + + + /** + * @var EBI_T::CTL0 + * Offset: 0x00 External Bus Interface Bank0 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |EN |EBI Enable Bit + * | | |This bit is the functional enable bit for EBI. + * | | |0 = EBI function Disabled. + * | | |1 = EBI function Enabled. + * |[1] |DW16 |EBI Data Width 16-bit Select + * | | |This bit defines if the EBI data width is 8-bit or 16-bit. + * | | |0 = EBI data width is 8-bit. + * | | |1 = EBI data width is 16-bit. + * |[2] |CSPOLINV |Chip Select Pin Polar Inverse + * | | |This bit defines the active level of EBI chip select pin (EBI_nCS). + * | | |0 = Chip select pin (EBI_nCS) is active low. + * | | |1 = Chip select pin (EBI_nCS) is active high. + * |[3] |ADSEPEN |EBI Address/Data Bus Separating Mode Enable Bit + * | | |0 = Address/Data Bus Separating Mode Disabled. + * | | |1 = Address/Data Bus Separating Mode Enabled. + * |[4] |CACCESS |Continuous Data Access Mode + * | | |When con tenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request. + * | | |0 = Continuous data access mode Disabled. + * | | |1 = Continuous data access mode Enabled. + * |[10:8] |MCLKDIV |External Output Clock Divider + * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow: + * | | |000 = HCLK/1. + * | | |001 = HCLK/2. + * | | |010 = HCLK/4. + * | | |011 = HCLK/8. + * | | |100 = HCLK/16. + * | | |101 = HCLK/32. + * | | |110 = HCLK/64. + * | | |111 = HCLK/128. + * |[18:16] |TALE |Extend Time of ALE + * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE. + * | | |tALE = (TALE+1)*EBI_MCLK. + * | | |Note: This field only available in EBI_CTL0 register + * |[24] |WBUFEN |EBI Write Buffer Enable Bit + * | | |0 = EBI write buffer Disabled. + * | | |1 = EBI write buffer Enabled. + * | | |Note: This bit only available in EBI_CTL0 register + * @var EBI_T::TCTL0 + * Offset: 0x04 External Bus Interface Bank0 Timing Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:3] |TACC |EBI Data Access Time + * | | |TACC define data access time (tACC). + * | | |tACC = (TACC +1) * EBI_MCLK. + * |[10:8] |TAHD |EBI Data Access Hold Time + * | | |TAHD define data access hold time (tAHD). + * | | |tAHD = (TAHD +1) * EBI_MCLK. + * |[15:12] |W2X |Idle Cycle After Write + * | | |This field defines the number of W2X idle cycle. + * | | |W2X idle cycle = (W2X * EBI_MCLK). + * | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state. + * |[22] |RAHDOFF |Access Hold Time Disable Control When Read + * | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled. + * | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled. + * |[23] |WAHDOFF |Access Hold Time Disable Control When Write + * | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled. + * | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled. + * |[27:24] |R2R |Idle Cycle Between Read-to-read + * | | |This field defines the number of R2R idle cycle. + * | | |R2R idle cycle = (R2R * EBI_MCLK). + * | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state. + * @var EBI_T::CTL1 + * Offset: 0x10 External Bus Interface Bank1 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |EN |EBI Enable Bit + * | | |This bit is the functional enable bit for EBI. + * | | |0 = EBI function Disabled. + * | | |1 = EBI function Enabled. + * |[1] |DW16 |EBI Data Width 16-bit Select + * | | |This bit defines if the EBI data width is 8-bit or 16-bit. + * | | |0 = EBI data width is 8-bit. + * | | |1 = EBI data width is 16-bit. + * |[2] |CSPOLINV |Chip Select Pin Polar Inverse + * | | |This bit defines the active level of EBI chip select pin (EBI_nCS). + * | | |0 = Chip select pin (EBI_nCS) is active low. + * | | |1 = Chip select pin (EBI_nCS) is active high. + * |[3] |ADSEPEN |EBI Address/Data Bus Separating Mode Enable Bit + * | | |0 = Address/Data Bus Separating Mode Disabled. + * | | |1 = Address/Data Bus Separating Mode Enabled. + * |[4] |CACCESS |Continuous Data Access Mode + * | | |When con tenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request. + * | | |0 = Continuous data access mode Disabled. + * | | |1 = Continuous data access mode Enabled. + * |[10:8] |MCLKDIV |External Output Clock Divider + * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow: + * | | |000 = HCLK/1. + * | | |001 = HCLK/2. + * | | |010 = HCLK/4. + * | | |011 = HCLK/8. + * | | |100 = HCLK/16. + * | | |101 = HCLK/32. + * | | |110 = HCLK/64. + * | | |111 = HCLK/128. + * |[18:16] |TALE |Extend Time of ALE + * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE. + * | | |tALE = (TALE+1)*EBI_MCLK. + * | | |Note: This field only available in EBI_CTL0 register + * |[24] |WBUFEN |EBI Write Buffer Enable Bit + * | | |0 = EBI write buffer Disabled. + * | | |1 = EBI write buffer Enabled. + * | | |Note: This bit only available in EBI_CTL0 register + * @var EBI_T::TCTL1 + * Offset: 0x14 External Bus Interface Bank1 Timing Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:3] |TACC |EBI Data Access Time + * | | |TACC define data access time (tACC). + * | | |tACC = (TACC +1) * EBI_MCLK. + * |[10:8] |TAHD |EBI Data Access Hold Time + * | | |TAHD define data access hold time (tAHD). + * | | |tAHD = (TAHD +1) * EBI_MCLK. + * |[15:12] |W2X |Idle Cycle After Write + * | | |This field defines the number of W2X idle cycle. + * | | |W2X idle cycle = (W2X * EBI_MCLK). + * | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state. + * |[22] |RAHDOFF |Access Hold Time Disable Control When Read + * | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled. + * | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled. + * |[23] |WAHDOFF |Access Hold Time Disable Control When Write + * | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled. + * | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled. + * |[27:24] |R2R |Idle Cycle Between Read-to-read + * | | |This field defines the number of R2R idle cycle. + * | | |R2R idle cycle = (R2R * EBI_MCLK). + * | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state. + * @var EBI_T::CTL2 + * Offset: 0x20 External Bus Interface Bank2 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |EN |EBI Enable Bit + * | | |This bit is the functional enable bit for EBI. + * | | |0 = EBI function Disabled. + * | | |1 = EBI function Enabled. + * |[1] |DW16 |EBI Data Width 16-bit Select + * | | |This bit defines if the EBI data width is 8-bit or 16-bit. + * | | |0 = EBI data width is 8-bit. + * | | |1 = EBI data width is 16-bit. + * |[2] |CSPOLINV |Chip Select Pin Polar Inverse + * | | |This bit defines the active level of EBI chip select pin (EBI_nCS). + * | | |0 = Chip select pin (EBI_nCS) is active low. + * | | |1 = Chip select pin (EBI_nCS) is active high. + * |[3] |ADSEPEN |EBI Address/Data Bus Separating Mode Enable Bit + * | | |0 = Address/Data Bus Separating Mode Disabled. + * | | |1 = Address/Data Bus Separating Mode Enabled. + * |[4] |CACCESS |Continuous Data Access Mode + * | | |When con tenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request. + * | | |0 = Continuous data access mode Disabled. + * | | |1 = Continuous data access mode Enabled. + * |[10:8] |MCLKDIV |External Output Clock Divider + * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow: + * | | |000 = HCLK/1. + * | | |001 = HCLK/2. + * | | |010 = HCLK/4. + * | | |011 = HCLK/8. + * | | |100 = HCLK/16. + * | | |101 = HCLK/32. + * | | |110 = HCLK/64. + * | | |111 = HCLK/128. + * |[18:16] |TALE |Extend Time of ALE + * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE. + * | | |tALE = (TALE+1)*EBI_MCLK. + * | | |Note: This field only available in EBI_CTL0 register + * |[24] |WBUFEN |EBI Write Buffer Enable Bit + * | | |0 = EBI write buffer Disabled. + * | | |1 = EBI write buffer Enabled. + * | | |Note: This bit only available in EBI_CTL0 register + * @var EBI_T::TCTL2 + * Offset: 0x24 External Bus Interface Bank2 Timing Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:3] |TACC |EBI Data Access Time + * | | |TACC define data access time (tACC). + * | | |tACC = (TACC +1) * EBI_MCLK. + * |[10:8] |TAHD |EBI Data Access Hold Time + * | | |TAHD define data access hold time (tAHD). + * | | |tAHD = (TAHD +1) * EBI_MCLK. + * |[15:12] |W2X |Idle Cycle After Write + * | | |This field defines the number of W2X idle cycle. + * | | |W2X idle cycle = (W2X * EBI_MCLK). + * | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state. + * |[22] |RAHDOFF |Access Hold Time Disable Control When Read + * | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled. + * | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled. + * |[23] |WAHDOFF |Access Hold Time Disable Control When Write + * | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled. + * | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled. + * |[27:24] |R2R |Idle Cycle Between Read-to-read + * | | |This field defines the number of R2R idle cycle. + * | | |R2R idle cycle = (R2R * EBI_MCLK). + * | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state. + */ + __IO uint32_t CTL0; /*!< [0x0000] External Bus Interface Bank0 Control Register */ + __IO uint32_t TCTL0; /*!< [0x0004] External Bus Interface Bank0 Timing Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CTL1; /*!< [0x0010] External Bus Interface Bank1 Control Register */ + __IO uint32_t TCTL1; /*!< [0x0014] External Bus Interface Bank1 Timing Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CTL2; /*!< [0x0020] External Bus Interface Bank2 Control Register */ + __IO uint32_t TCTL2; /*!< [0x0024] External Bus Interface Bank2 Timing Control Register */ + +} EBI_T; + +/** + @addtogroup EBI_CONST EBI Bit Field Definition + Constant Definitions for EBI Controller +@{ */ + +#define EBI_CTL_EN_Pos (0) /*!< EBI_T::CTL: EN Position */ +#define EBI_CTL_EN_Msk (0x1ul << EBI_CTL_EN_Pos) /*!< EBI_T::CTL: EN Mask */ + +#define EBI_CTL_DW16_Pos (1) /*!< EBI_T::CTL: DW16 Position */ +#define EBI_CTL_DW16_Msk (0x1ul << EBI_CTL_DW16_Pos) /*!< EBI_T::CTL: DW16 Mask */ + +#define EBI_CTL_CSPOLINV_Pos (2) /*!< EBI_T::CTL: CSPOLINV Position */ +#define EBI_CTL_CSPOLINV_Msk (0x1ul << EBI_CTL_CSPOLINV_Pos) /*!< EBI_T::CTL: CSPOLINV Mask */ + +#define EBI_CTL_ADSEPEN_Pos (3) /*!< EBI_T::CTL: ADSEPEN Position */ +#define EBI_CTL_ADSEPEN_Msk (0x1ul << EBI_CTL_ADSEPEN_Pos) /*!< EBI_T::CTL: ADSEPEN Mask */ + +#define EBI_CTL_CACCESS_Pos (4) /*!< EBI_T::CTL: CACCESS Position */ +#define EBI_CTL_CACCESS_Msk (0x1ul << EBI_CTL_CACCESS_Pos) /*!< EBI_T::CTL: CACCESS Mask */ + +#define EBI_CTL_MCLKDIV_Pos (8) /*!< EBI_T::CTL: MCLKDIV Position */ +#define EBI_CTL_MCLKDIV_Msk (0x7ul << EBI_CTL_MCLKDIV_Pos) /*!< EBI_T::CTL: MCLKDIV Mask */ + +#define EBI_CTL_TALE_Pos (16) /*!< EBI_T::CTL: TALE Position */ +#define EBI_CTL_TALE_Msk (0x7ul << EBI_CTL_TALE_Pos) /*!< EBI_T::CTL: TALE Mask */ + +#define EBI_CTL_WBUFEN_Pos (24) /*!< EBI_T::CTL: WBUFEN Position */ +#define EBI_CTL_WBUFEN_Msk (0x1ul << EBI_CTL_WBUFEN_Pos) /*!< EBI_T::CTL: WBUFEN Mask */ + +#define EBI_TCTL_TACC_Pos (3) /*!< EBI_T::TCTL: TACC Position */ +#define EBI_TCTL_TACC_Msk (0x1ful << EBI_TCTL_TACC_Pos) /*!< EBI_T::TCTL: TACC Mask */ + +#define EBI_TCTL_TAHD_Pos (8) /*!< EBI_T::TCTL: TAHD Position */ +#define EBI_TCTL_TAHD_Msk (0x7ul << EBI_TCTL_TAHD_Pos) /*!< EBI_T::TCTL: TAHD Mask */ + +#define EBI_TCTL_W2X_Pos (12) /*!< EBI_T::TCTL: W2X Position */ +#define EBI_TCTL_W2X_Msk (0xful << EBI_TCTL_W2X_Pos) /*!< EBI_T::TCTL: W2X Mask */ + +#define EBI_TCTL_RAHDOFF_Pos (22) /*!< EBI_T::TCTL: RAHDOFF Position */ +#define EBI_TCTL_RAHDOFF_Msk (0x1ul << EBI_TCTL_RAHDOFF_Pos) /*!< EBI_T::TCTL: RAHDOFF Mask */ + +#define EBI_TCTL_WAHDOFF_Pos (23) /*!< EBI_T::TCTL: WAHDOFF Position */ +#define EBI_TCTL_WAHDOFF_Msk (0x1ul << EBI_TCTL_WAHDOFF_Pos) /*!< EBI_T::TCTL: WAHDOFF Mask */ + +#define EBI_TCTL_R2R_Pos (24) /*!< EBI_T::TCTL: R2R Position */ +#define EBI_TCTL_R2R_Msk (0xful << EBI_TCTL_R2R_Pos) /*!< EBI_T::TCTL: R2R Mask */ + +#define EBI_CTL0_EN_Pos (0) /*!< EBI_T::CTL0: EN Position */ +#define EBI_CTL0_EN_Msk (0x1ul << EBI_CTL0_EN_Pos) /*!< EBI_T::CTL0: EN Mask */ + +#define EBI_CTL0_DW16_Pos (1) /*!< EBI_T::CTL0: DW16 Position */ +#define EBI_CTL0_DW16_Msk (0x1ul << EBI_CTL0_DW16_Pos) /*!< EBI_T::CTL0: DW16 Mask */ + +#define EBI_CTL0_CSPOLINV_Pos (2) /*!< EBI_T::CTL0: CSPOLINV Position */ +#define EBI_CTL0_CSPOLINV_Msk (0x1ul << EBI_CTL0_CSPOLINV_Pos) /*!< EBI_T::CTL0: CSPOLINV Mask */ + +#define EBI_CTL0_ADSEPEN_Pos (3) /*!< EBI_T::CTL0: ADSEPEN Position */ +#define EBI_CTL0_ADSEPEN_Msk (0x1ul << EBI_CTL0_ADSEPEN_Pos) /*!< EBI_T::CTL0: ADSEPEN Mask */ + +#define EBI_CTL0_CACCESS_Pos (4) /*!< EBI_T::CTL0: CACCESS Position */ +#define EBI_CTL0_CACCESS_Msk (0x1ul << EBI_CTL0_CACCESS_Pos) /*!< EBI_T::CTL0: CACCESS Mask */ + +#define EBI_CTL0_MCLKDIV_Pos (8) /*!< EBI_T::CTL0: MCLKDIV Position */ +#define EBI_CTL0_MCLKDIV_Msk (0x7ul << EBI_CTL0_MCLKDIV_Pos) /*!< EBI_T::CTL0: MCLKDIV Mask */ + +#define EBI_CTL0_TALE_Pos (16) /*!< EBI_T::CTL0: TALE Position */ +#define EBI_CTL0_TALE_Msk (0x7ul << EBI_CTL0_TALE_Pos) /*!< EBI_T::CTL0: TALE Mask */ + +#define EBI_CTL0_WBUFEN_Pos (24) /*!< EBI_T::CTL0: WBUFEN Position */ +#define EBI_CTL0_WBUFEN_Msk (0x1ul << EBI_CTL0_WBUFEN_Pos) /*!< EBI_T::CTL0: WBUFEN Mask */ + +#define EBI_TCTL0_TACC_Pos (3) /*!< EBI_T::TCTL0: TACC Position */ +#define EBI_TCTL0_TACC_Msk (0x1ful << EBI_TCTL0_TACC_Pos) /*!< EBI_T::TCTL0: TACC Mask */ + +#define EBI_TCTL0_TAHD_Pos (8) /*!< EBI_T::TCTL0: TAHD Position */ +#define EBI_TCTL0_TAHD_Msk (0x7ul << EBI_TCTL0_TAHD_Pos) /*!< EBI_T::TCTL0: TAHD Mask */ + +#define EBI_TCTL0_W2X_Pos (12) /*!< EBI_T::TCTL0: W2X Position */ +#define EBI_TCTL0_W2X_Msk (0xful << EBI_TCTL0_W2X_Pos) /*!< EBI_T::TCTL0: W2X Mask */ + +#define EBI_TCTL0_RAHDOFF_Pos (22) /*!< EBI_T::TCTL0: RAHDOFF Position */ +#define EBI_TCTL0_RAHDOFF_Msk (0x1ul << EBI_TCTL0_RAHDOFF_Pos) /*!< EBI_T::TCTL0: RAHDOFF Mask */ + +#define EBI_TCTL0_WAHDOFF_Pos (23) /*!< EBI_T::TCTL0: WAHDOFF Position */ +#define EBI_TCTL0_WAHDOFF_Msk (0x1ul << EBI_TCTL0_WAHDOFF_Pos) /*!< EBI_T::TCTL0: WAHDOFF Mask */ + +#define EBI_TCTL0_R2R_Pos (24) /*!< EBI_T::TCTL0: R2R Position */ +#define EBI_TCTL0_R2R_Msk (0xful << EBI_TCTL0_R2R_Pos) /*!< EBI_T::TCTL0: R2R Mask */ + +#define EBI_CTL1_EN_Pos (0) /*!< EBI_T::CTL1: EN Position */ +#define EBI_CTL1_EN_Msk (0x1ul << EBI_CTL1_EN_Pos) /*!< EBI_T::CTL1: EN Mask */ + +#define EBI_CTL1_DW16_Pos (1) /*!< EBI_T::CTL1: DW16 Position */ +#define EBI_CTL1_DW16_Msk (0x1ul << EBI_CTL1_DW16_Pos) /*!< EBI_T::CTL1: DW16 Mask */ + +#define EBI_CTL1_CSPOLINV_Pos (2) /*!< EBI_T::CTL1: CSPOLINV Position */ +#define EBI_CTL1_CSPOLINV_Msk (0x1ul << EBI_CTL1_CSPOLINV_Pos) /*!< EBI_T::CTL1: CSPOLINV Mask */ + +#define EBI_CTL1_ADSEPEN_Pos (3) /*!< EBI_T::CTL1: ADSEPEN Position */ +#define EBI_CTL1_ADSEPEN_Msk (0x1ul << EBI_CTL1_ADSEPEN_Pos) /*!< EBI_T::CTL1: ADSEPEN Mask */ + +#define EBI_CTL1_CACCESS_Pos (4) /*!< EBI_T::CTL1: CACCESS Position */ +#define EBI_CTL1_CACCESS_Msk (0x1ul << EBI_CTL1_CACCESS_Pos) /*!< EBI_T::CTL1: CACCESS Mask */ + +#define EBI_CTL1_MCLKDIV_Pos (8) /*!< EBI_T::CTL1: MCLKDIV Position */ +#define EBI_CTL1_MCLKDIV_Msk (0x7ul << EBI_CTL1_MCLKDIV_Pos) /*!< EBI_T::CTL1: MCLKDIV Mask */ + +#define EBI_CTL1_TALE_Pos (16) /*!< EBI_T::CTL1: TALE Position */ +#define EBI_CTL1_TALE_Msk (0x7ul << EBI_CTL1_TALE_Pos) /*!< EBI_T::CTL1: TALE Mask */ + +#define EBI_CTL1_WBUFEN_Pos (24) /*!< EBI_T::CTL1: WBUFEN Position */ +#define EBI_CTL1_WBUFEN_Msk (0x1ul << EBI_CTL1_WBUFEN_Pos) /*!< EBI_T::CTL1: WBUFEN Mask */ + +#define EBI_TCTL1_TACC_Pos (3) /*!< EBI_T::TCTL1: TACC Position */ +#define EBI_TCTL1_TACC_Msk (0x1ful << EBI_TCTL1_TACC_Pos) /*!< EBI_T::TCTL1: TACC Mask */ + +#define EBI_TCTL1_TAHD_Pos (8) /*!< EBI_T::TCTL1: TAHD Position */ +#define EBI_TCTL1_TAHD_Msk (0x7ul << EBI_TCTL1_TAHD_Pos) /*!< EBI_T::TCTL1: TAHD Mask */ + +#define EBI_TCTL1_W2X_Pos (12) /*!< EBI_T::TCTL1: W2X Position */ +#define EBI_TCTL1_W2X_Msk (0xful << EBI_TCTL1_W2X_Pos) /*!< EBI_T::TCTL1: W2X Mask */ + +#define EBI_TCTL1_RAHDOFF_Pos (22) /*!< EBI_T::TCTL1: RAHDOFF Position */ +#define EBI_TCTL1_RAHDOFF_Msk (0x1ul << EBI_TCTL1_RAHDOFF_Pos) /*!< EBI_T::TCTL1: RAHDOFF Mask */ + +#define EBI_TCTL1_WAHDOFF_Pos (23) /*!< EBI_T::TCTL1: WAHDOFF Position */ +#define EBI_TCTL1_WAHDOFF_Msk (0x1ul << EBI_TCTL1_WAHDOFF_Pos) /*!< EBI_T::TCTL1: WAHDOFF Mask */ + +#define EBI_TCTL1_R2R_Pos (24) /*!< EBI_T::TCTL1: R2R Position */ +#define EBI_TCTL1_R2R_Msk (0xful << EBI_TCTL1_R2R_Pos) /*!< EBI_T::TCTL1: R2R Mask */ + +#define EBI_CTL2_EN_Pos (0) /*!< EBI_T::CTL2: EN Position */ +#define EBI_CTL2_EN_Msk (0x1ul << EBI_CTL2_EN_Pos) /*!< EBI_T::CTL2: EN Mask */ + +#define EBI_CTL2_DW16_Pos (1) /*!< EBI_T::CTL2: DW16 Position */ +#define EBI_CTL2_DW16_Msk (0x1ul << EBI_CTL2_DW16_Pos) /*!< EBI_T::CTL2: DW16 Mask */ + +#define EBI_CTL2_CSPOLINV_Pos (2) /*!< EBI_T::CTL2: CSPOLINV Position */ +#define EBI_CTL2_CSPOLINV_Msk (0x1ul << EBI_CTL2_CSPOLINV_Pos) /*!< EBI_T::CTL2: CSPOLINV Mask */ + +#define EBI_CTL2_ADSEPEN_Pos (3) /*!< EBI_T::CTL2: ADSEPEN Position */ +#define EBI_CTL2_ADSEPEN_Msk (0x1ul << EBI_CTL2_ADSEPEN_Pos) /*!< EBI_T::CTL2: ADSEPEN Mask */ + +#define EBI_CTL2_CACCESS_Pos (4) /*!< EBI_T::CTL2: CACCESS Position */ +#define EBI_CTL2_CACCESS_Msk (0x1ul << EBI_CTL2_CACCESS_Pos) /*!< EBI_T::CTL2: CACCESS Mask */ + +#define EBI_CTL2_MCLKDIV_Pos (8) /*!< EBI_T::CTL2: MCLKDIV Position */ +#define EBI_CTL2_MCLKDIV_Msk (0x7ul << EBI_CTL2_MCLKDIV_Pos) /*!< EBI_T::CTL2: MCLKDIV Mask */ + +#define EBI_CTL2_TALE_Pos (16) /*!< EBI_T::CTL2: TALE Position */ +#define EBI_CTL2_TALE_Msk (0x7ul << EBI_CTL2_TALE_Pos) /*!< EBI_T::CTL2: TALE Mask */ + +#define EBI_CTL2_WBUFEN_Pos (24) /*!< EBI_T::CTL2: WBUFEN Position */ +#define EBI_CTL2_WBUFEN_Msk (0x1ul << EBI_CTL2_WBUFEN_Pos) /*!< EBI_T::CTL2: WBUFEN Mask */ + +#define EBI_TCTL2_TACC_Pos (3) /*!< EBI_T::TCTL2: TACC Position */ +#define EBI_TCTL2_TACC_Msk (0x1ful << EBI_TCTL2_TACC_Pos) /*!< EBI_T::TCTL2: TACC Mask */ + +#define EBI_TCTL2_TAHD_Pos (8) /*!< EBI_T::TCTL2: TAHD Position */ +#define EBI_TCTL2_TAHD_Msk (0x7ul << EBI_TCTL2_TAHD_Pos) /*!< EBI_T::TCTL2: TAHD Mask */ + +#define EBI_TCTL2_W2X_Pos (12) /*!< EBI_T::TCTL2: W2X Position */ +#define EBI_TCTL2_W2X_Msk (0xful << EBI_TCTL2_W2X_Pos) /*!< EBI_T::TCTL2: W2X Mask */ + +#define EBI_TCTL2_RAHDOFF_Pos (22) /*!< EBI_T::TCTL2: RAHDOFF Position */ +#define EBI_TCTL2_RAHDOFF_Msk (0x1ul << EBI_TCTL2_RAHDOFF_Pos) /*!< EBI_T::TCTL2: RAHDOFF Mask */ + +#define EBI_TCTL2_WAHDOFF_Pos (23) /*!< EBI_T::TCTL2: WAHDOFF Position */ +#define EBI_TCTL2_WAHDOFF_Msk (0x1ul << EBI_TCTL2_WAHDOFF_Pos) /*!< EBI_T::TCTL2: WAHDOFF Mask */ + +#define EBI_TCTL2_R2R_Pos (24) /*!< EBI_T::TCTL2: R2R Position */ +#define EBI_TCTL2_R2R_Msk (0xful << EBI_TCTL2_R2R_Pos) /*!< EBI_T::TCTL2: R2R Mask */ + +/**@}*/ /* EBI_CONST */ +/**@}*/ /* end of EBI register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __EBI_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/ecap_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/ecap_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..d22d9dc4de8daf7bd11dddb4e2395bed76f54980 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/ecap_reg.h @@ -0,0 +1,390 @@ +/**************************************************************************//** + * @file ecap_reg.h + * @version V1.00 + * @brief ECAP register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __ECAP_REG_H__ +#define __ECAP_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup ECAP Enhanced Input Capture Timer(ECAP) + Memory Mapped Structure for ECAP Controller +@{ */ + +typedef struct +{ + + /** + * @var ECAP_T::CNT + * Offset: 0x00 Input Capture Counter (24-bit up counter) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CNT |Input Capture Timer/Counter + * | | |The input Capture Timer/Counter is a 24-bit up-counting counter + * | | |The clock source for the counter is from the clock divider + * @var ECAP_T::HLD0 + * Offset: 0x04 Input Capture Hold Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |HOLD |Input Capture Counter Hold Register + * | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register + * | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively. + * @var ECAP_T::HLD1 + * Offset: 0x08 Input Capture Hold Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |HOLD |Input Capture Counter Hold Register + * | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register + * | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively. + * @var ECAP_T::HLD2 + * Offset: 0x0C Input Capture Hold Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |HOLD |Input Capture Counter Hold Register + * | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register + * | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively. + * @var ECAP_T::CNTCMP + * Offset: 0x10 Input Capture Compare Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CNTCMP |Input Capture Counter Compare Register + * | | |If the compare function is enabled (CMPEN = 1), this register (ECAP_CNTCMP) is used to compare with the capture counter (ECAP_CNT). + * | | |If the reload control is enabled (RLDEN[n] = 1, n=0~3), an overflow event or capture events will trigger the hardware to load the value of this register (ECAP_CNTCMP) into ECAP_CNT. + * @var ECAP_T::CTL0 + * Offset: 0x14 Input Capture Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |NFCLKSEL |Noise Filter Clock Pre-divide Selection + * | | |To determine the sampling frequency of the Noise Filter clock + * | | |000 = CAP_CLK. + * | | |001 = CAP_CLK/2. + * | | |010 = CAP_CLK/4. + * | | |011 = CAP_CLK/16. + * | | |100 = CAP_CLK/32. + * | | |101 = CAP_CLK/64. + * |[3] |CAPNFDIS |Input Capture Noise Filter Disable Control + * | | |0 = Noise filter of Input Capture Enabled. + * | | |1 = Noise filter of Input Capture Disabled (Bypass). + * |[4] |IC0EN |Port Pin IC0 Input to Input Capture Unit Enable Control + * | | |0 = IC0 input to Input Capture Unit Disabled. + * | | |1 = IC0 input to Input Capture Unit Enabled. + * |[5] |IC1EN |Port Pin IC1 Input to Input Capture Unit Enable Control + * | | |0 = IC1 input to Input Capture Unit Disabled. + * | | |1 = IC1 input to Input Capture Unit Enabled. + * |[6] |IC2EN |Port Pin IC2 Input to Input Capture Unit Enable Control + * | | |0 = IC2 input to Input Capture Unit Disabled. + * | | |1 = IC2 input to Input Capture Unit Enabled. + * |[9:8] |CAPSEL0 |CAP0 Input Source Selection + * | | |00 = CAP0 input is from port pin ICAP0. + * | | |01 = Reserved. + * | | |10 = CAP0 input is from signal CHA of QEI controller unit n. + * | | |11 = Reserved. + * | | |Note: Input capture unit n matches QEIn, where n = 0~1. + * |[11:10] |CAPSEL1 |CAP1 Input Source Selection + * | | |00 = CAP1 input is from port pin ICAP1. + * | | |01 = Reserved. + * | | |10 = CAP1 input is from signal CHB of QEI controller unit n. + * | | |11 = Reserved. + * | | |Note: Input capture unit n matches QEIn, where n = 0~1. + * |[13:12] |CAPSEL2 |CAP2 Input Source Selection + * | | |00 = CAP2 input is from port pin ICAP2. + * | | |01 = Reserved. + * | | |10 = CAP2 input is from signal CHX of QEI controller unit n. + * | | |11 = Reserved. + * | | |Note: Input capture unit n matches QEIn, where n = 0~1. + * |[16] |CAPIEN0 |Input Capture Channel 0 Interrupt Enable Control + * | | |0 = The flag CAPTF0 can trigger Input Capture interrupt Disabled. + * | | |1 = The flag CAPTF0 can trigger Input Capture interrupt Enabled. + * |[17] |CAPIEN1 |Input Capture Channel 1 Interrupt Enable Control + * | | |0 = The flag CAPTF1 can trigger Input Capture interrupt Disabled. + * | | |1 = The flag CAPTF1 can trigger Input Capture interrupt Enabled. + * |[18] |CAPIEN2 |Input Capture Channel 2 Interrupt Enable Control + * | | |0 = The flag CAPTF2 can trigger Input Capture interrupt Disabled. + * | | |1 = The flag CAPTF2 can trigger Input Capture interrupt Enabled. + * |[20] |OVIEN |CAPOVF Trigger Input Capture Interrupt Enable Control + * | | |0 = The flag CAPOVF can trigger Input Capture interrupt Disabled. + * | | |1 = The flag CAPOVF can trigger Input Capture interrupt Enabled. + * |[21] |CMPIEN |CAPCMPF Trigger Input Capture Interrupt Enable Control + * | | |0 = The flag CAPCMPF can trigger Input Capture interrupt Disabled. + * | | |1 = The flag CAPCMPF can trigger Input Capture interrupt Enabled. + * |[24] |CNTEN |Input Capture Counter Start Counting Control + * | | |Setting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with the clock from the . + * | | |0 = ECAP_CNT stop counting. + * | | |1 = ECAP_CNT starts up-counting. + * |[25] |CMPCLREN |Input Capture Counter Cleared by Compare-match Control + * | | |If this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to 0 when the compare-match event (CAPCMPF = 1) occurs. + * | | |0 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Disabled. + * | | |1 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Enabled. + * |[28] |CMPEN |Compare Function Enable Control + * | | |The compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CAPCMPF will be set. + * | | |0 = The compare function Disabled. + * | | |1 = The compare function Enabled. + * |[29] |CAPEN |Input Capture Timer/Counter Enable Control + * | | |0 = Input Capture function Disabled. + * | | |1 = Input Capture function Enabled. + * @var ECAP_T::CTL1 + * Offset: 0x18 Input Capture Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |EDGESEL0 |Channel 0 Captured Edge Selection + * | | |Input capture0 can detect falling edge change only, rising edge change only or both edge change + * | | |00 = Detect rising edge only. + * | | |01 = Detect falling edge only. + * | | |1x = Detect both rising and falling edge. + * |[3:2] |EDGESEL1 |Channel 1 Captured Edge Selection + * | | |Input capture1 can detect falling edge change only, rising edge change only or both edge change + * | | |00 = Detect rising edge only. + * | | |01 = Detect falling edge only. + * | | |1x = Detect both rising and falling edge. + * |[5:4] |EDGESEL2 |Channel 2 Captured Edge Selection + * | | |Input capture2 can detect falling edge change only, rising edge change only or both edge changes + * | | |00 = Detect rising edge only. + * | | |01 = Detect falling edge only. + * | | |1x = Detect both rising and falling edge. + * |[8] |CAP0RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE0 Enable Bit + * | | |0 = The reload triggered by Event CAPTE0 Disabled. + * | | |1 = The reload triggered by Event CAPTE0 Enabled. + * |[9] |CAP1RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE1 Enable Bit + * | | |0 = The reload triggered by Event CAPTE1 Disabled. + * | | |1 = The reload triggered by Event CAPTE1 Enabled. + * |[10] |CAP2RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE2 Enable Bit + * | | |0 = The reload triggered by Event CAPTE2 Disabled. + * | | |1 = The reload triggered by Event CAPTE2 Enabled. + * |[11] |OVRLDEN |Capture Counteru2019s Reload Function Triggered by Overflow Enable Bit + * | | |0 = The reload triggered by CAPOV Disabled. + * | | |1 = The reload triggered by CAPOV Enabled. + * |[14:12] |CLKSEL |Capture Timer Clock Divide Selection + * | | |The capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[2:0]. + * | | |000 = CAP_CLK/1. + * | | |001 = CAP_CLK/4. + * | | |010 = CAP_CLK/16. + * | | |011 = CAP_CLK/32. + * | | |100 = CAP_CLK/64. + * | | |101 = CAP_CLK/96. + * | | |110 = CAP_CLK/112. + * | | |111 = CAP_CLK/128. + * |[17:16] |CNTSRCSEL |Capture Timer/Counter Clock Source Selection + * | | |Select the capture timer/counter clock source. + * | | |00 = CAP_CLK (default). + * | | |01 = CAP0. + * | | |10 = CAP1. + * | | |11 = CAP2. + * |[20] |CAP0CLREN |Capture Counter Cleared by Capture Event0 Control + * | | |0 = Event CAPTE0 can clear capture counter (ECAP_CNT) Disabled. + * | | |1 = Event CAPTE0 can clear capture counter (ECAP_CNT) Enabled. + * |[21] |CAP1CLREN |Capture Counter Cleared by Capture Event1 Control + * | | |0 = Event CAPTE1 can clear capture counter (ECAP_CNT) Disabled. + * | | |1 = Event CAPTE1 can clear capture counter (ECAP_CNT) Enabled. + * |[22] |CAP2CLREN |Capture Counter Cleared by Capture Event2 Control + * | | |0 = Event CAPTE2 can clear capture counter (ECAP_CNT) Disabled. + * | | |1 = Event CAPTE2 can clear capture counter (ECAP_CNT) Enabled. + * @var ECAP_T::STATUS + * Offset: 0x1C Input Capture Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPTF0 |Input Capture Channel 0 Triggered Flag + * | | |When the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPTF0 to high. + * | | |0 = No valid edge change has been detected at CAP0 input since last clear. + * | | |1 = At least a valid edge change has been detected at CAP0 input since last clear. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[1] |CAPTF1 |Input Capture Channel 1 Triggered Flag + * | | |When the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPTF1 to high. + * | | |0 = No valid edge change has been detected at CAP1 input since last clear. + * | | |1 = At least a valid edge change has been detected at CAP1 input since last clear. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[2] |CAPTF2 |Input Capture Channel 2 Triggered Flag + * | | |When the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPTF2 to high. + * | | |0 = No valid edge change has been detected at CAP2 input since last clear. + * | | |1 = At least a valid edge change has been detected at CAP2 input since last clear. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[4] |CAPCMPF |Input Capture Compare-match Flag + * | | |If the input capture compare function is enabled, the flag is set by hardware when capture counter (ECAP_CNT) up counts and reaches the ECAP_CNTCMP value. + * | | |0 = ECAP_CNT has not matched ECAP_CNTCMP value since last clear. + * | | |1 = ECAP_CNT has matched ECAP_CNTCMP value at least once since last clear. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[5] |CAPOVF |Input Capture Counter Overflow Flag + * | | |Flag is set by hardware when counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero. + * | | |0 = No overflow event has occurred since last clear. + * | | |1 = Overflow event(s) has/have occurred since last clear. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[6] |CAP0 |Value of Input Channel 0, CAP0 (Read Only) + * | | |Reflecting the value of input channel 0, CAP0 + * | | |(The bit is read only and write is ignored) + * |[7] |CAP1 |Value of Input Channel 1, CAP1 (Read Only) + * | | |Reflecting the value of input channel 1, CAP1 + * | | |(The bit is read only and write is ignored) + * |[8] |CAP2 |Value of Input Channel 2, CAP2 (Read Only) + * | | |Reflecting the value of input channel 2, CAP2. + * | | |(The bit is read only and write is ignored) + */ + __IO uint32_t CNT; /*!< [0x0000] Input Capture Counter */ + __IO uint32_t HLD0; /*!< [0x0004] Input Capture Hold Register 0 */ + __IO uint32_t HLD1; /*!< [0x0008] Input Capture Hold Register 1 */ + __IO uint32_t HLD2; /*!< [0x000c] Input Capture Hold Register 2 */ + __IO uint32_t CNTCMP; /*!< [0x0010] Input Capture Compare Register */ + __IO uint32_t CTL0; /*!< [0x0014] Input Capture Control Register 0 */ + __IO uint32_t CTL1; /*!< [0x0018] Input Capture Control Register 1 */ + __IO uint32_t STATUS; /*!< [0x001c] Input Capture Status Register */ + +} ECAP_T; + +/** + @addtogroup ECAP_CONST ECAP Bit Field Definition + Constant Definitions for ECAP Controller +@{ */ + +#define ECAP_CNT_CNT_Pos (0) /*!< ECAP_T::CNT: CNT Position */ +#define ECAP_CNT_CNT_Msk (0xfffffful << ECAP_CNT_CNT_Pos) /*!< ECAP_T::CNT: CNT Mask */ + +#define ECAP_HLD0_HOLD_Pos (0) /*!< ECAP_T::HLD0: HOLD Position */ +#define ECAP_HLD0_HOLD_Msk (0xfffffful << ECAP_HLD0_HOLD_Pos) /*!< ECAP_T::HLD0: HOLD Mask */ + +#define ECAP_HLD1_HOLD_Pos (0) /*!< ECAP_T::HLD1: HOLD Position */ +#define ECAP_HLD1_HOLD_Msk (0xfffffful << ECAP_HLD1_HOLD_Pos) /*!< ECAP_T::HLD1: HOLD Mask */ + +#define ECAP_HLD2_HOLD_Pos (0) /*!< ECAP_T::HLD2: HOLD Position */ +#define ECAP_HLD2_HOLD_Msk (0xfffffful << ECAP_HLD2_HOLD_Pos) /*!< ECAP_T::HLD2: HOLD Mask */ + +#define ECAP_CNTCMP_CNTCMP_Pos (0) /*!< ECAP_T::CNTCMP: CNTCMP Position */ +#define ECAP_CNTCMP_CNTCMP_Msk (0xfffffful << ECAP_CNTCMP_CNTCMP_Pos) /*!< ECAP_T::CNTCMP: CNTCMP Mask */ + +#define ECAP_CTL0_NFCLKSEL_Pos (0) /*!< ECAP_T::CTL0: NFCLKSEL Position */ +#define ECAP_CTL0_NFCLKSEL_Msk (0x7ul << ECAP_CTL0_NFCLKSEL_Pos) /*!< ECAP_T::CTL0: NFCLKSEL Mask */ + +#define ECAP_CTL0_CAPNFDIS_Pos (3) /*!< ECAP_T::CTL0: CAPNFDIS Position */ +#define ECAP_CTL0_CAPNFDIS_Msk (0x1ul << ECAP_CTL0_CAPNFDIS_Pos) /*!< ECAP_T::CTL0: CAPNFDIS Mask */ + +#define ECAP_CTL0_IC0EN_Pos (4) /*!< ECAP_T::CTL0: IC0EN Position */ +#define ECAP_CTL0_IC0EN_Msk (0x1ul << ECAP_CTL0_IC0EN_Pos) /*!< ECAP_T::CTL0: IC0EN Mask */ + +#define ECAP_CTL0_IC1EN_Pos (5) /*!< ECAP_T::CTL0: IC1EN Position */ +#define ECAP_CTL0_IC1EN_Msk (0x1ul << ECAP_CTL0_IC1EN_Pos) /*!< ECAP_T::CTL0: IC1EN Mask */ + +#define ECAP_CTL0_IC2EN_Pos (6) /*!< ECAP_T::CTL0: IC2EN Position */ +#define ECAP_CTL0_IC2EN_Msk (0x1ul << ECAP_CTL0_IC2EN_Pos) /*!< ECAP_T::CTL0: IC2EN Mask */ + +#define ECAP_CTL0_CAPSEL0_Pos (8) /*!< ECAP_T::CTL0: CAPSEL0 Position */ +#define ECAP_CTL0_CAPSEL0_Msk (0x3ul << ECAP_CTL0_CAPSEL0_Pos) /*!< ECAP_T::CTL0: CAPSEL0 Mask */ + +#define ECAP_CTL0_CAPSEL1_Pos (10) /*!< ECAP_T::CTL0: CAPSEL1 Position */ +#define ECAP_CTL0_CAPSEL1_Msk (0x3ul << ECAP_CTL0_CAPSEL1_Pos) /*!< ECAP_T::CTL0: CAPSEL1 Mask */ + +#define ECAP_CTL0_CAPSEL2_Pos (12) /*!< ECAP_T::CTL0: CAPSEL2 Position */ +#define ECAP_CTL0_CAPSEL2_Msk (0x3ul << ECAP_CTL0_CAPSEL2_Pos) /*!< ECAP_T::CTL0: CAPSEL2 Mask */ + +#define ECAP_CTL0_CAPIEN0_Pos (16) /*!< ECAP_T::CTL0: CAPIEN0 Position */ +#define ECAP_CTL0_CAPIEN0_Msk (0x1ul << ECAP_CTL0_CAPIEN0_Pos) /*!< ECAP_T::CTL0: CAPIEN0 Mask */ + +#define ECAP_CTL0_CAPIEN1_Pos (17) /*!< ECAP_T::CTL0: CAPIEN1 Position */ +#define ECAP_CTL0_CAPIEN1_Msk (0x1ul << ECAP_CTL0_CAPIEN1_Pos) /*!< ECAP_T::CTL0: CAPIEN1 Mask */ + +#define ECAP_CTL0_CAPIEN2_Pos (18) /*!< ECAP_T::CTL0: CAPIEN2 Position */ +#define ECAP_CTL0_CAPIEN2_Msk (0x1ul << ECAP_CTL0_CAPIEN2_Pos) /*!< ECAP_T::CTL0: CAPIEN2 Mask */ + +#define ECAP_CTL0_OVIEN_Pos (20) /*!< ECAP_T::CTL0: OVIEN Position */ +#define ECAP_CTL0_OVIEN_Msk (0x1ul << ECAP_CTL0_OVIEN_Pos) /*!< ECAP_T::CTL0: OVIEN Mask */ + +#define ECAP_CTL0_CMPIEN_Pos (21) /*!< ECAP_T::CTL0: CMPIEN Position */ +#define ECAP_CTL0_CMPIEN_Msk (0x1ul << ECAP_CTL0_CMPIEN_Pos) /*!< ECAP_T::CTL0: CMPIEN Mask */ + +#define ECAP_CTL0_CNTEN_Pos (24) /*!< ECAP_T::CTL0: CNTEN Position */ +#define ECAP_CTL0_CNTEN_Msk (0x1ul << ECAP_CTL0_CNTEN_Pos) /*!< ECAP_T::CTL0: CNTEN Mask */ + +#define ECAP_CTL0_CMPCLREN_Pos (25) /*!< ECAP_T::CTL0: CMPCLREN Position */ +#define ECAP_CTL0_CMPCLREN_Msk (0x1ul << ECAP_CTL0_CMPCLREN_Pos) /*!< ECAP_T::CTL0: CMPCLREN Mask */ + +#define ECAP_CTL0_CMPEN_Pos (28) /*!< ECAP_T::CTL0: CMPEN Position */ +#define ECAP_CTL0_CMPEN_Msk (0x1ul << ECAP_CTL0_CMPEN_Pos) /*!< ECAP_T::CTL0: CMPEN Mask */ + +#define ECAP_CTL0_CAPEN_Pos (29) /*!< ECAP_T::CTL0: CAPEN Position */ +#define ECAP_CTL0_CAPEN_Msk (0x1ul << ECAP_CTL0_CAPEN_Pos) /*!< ECAP_T::CTL0: CAPEN Mask */ + +#define ECAP_CTL1_EDGESEL0_Pos (0) /*!< ECAP_T::CTL1: EDGESEL0 Position */ +#define ECAP_CTL1_EDGESEL0_Msk (0x3ul << ECAP_CTL1_EDGESEL0_Pos) /*!< ECAP_T::CTL1: EDGESEL0 Mask */ + +#define ECAP_CTL1_EDGESEL1_Pos (2) /*!< ECAP_T::CTL1: EDGESEL1 Position */ +#define ECAP_CTL1_EDGESEL1_Msk (0x3ul << ECAP_CTL1_EDGESEL1_Pos) /*!< ECAP_T::CTL1: EDGESEL1 Mask */ + +#define ECAP_CTL1_EDGESEL2_Pos (4) /*!< ECAP_T::CTL1: EDGESEL2 Position */ +#define ECAP_CTL1_EDGESEL2_Msk (0x3ul << ECAP_CTL1_EDGESEL2_Pos) /*!< ECAP_T::CTL1: EDGESEL2 Mask */ + +#define ECAP_CTL1_CAP0RLDEN_Pos (8) /*!< ECAP_T::CTL1: CAP0RLDEN Position */ +#define ECAP_CTL1_CAP0RLDEN_Msk (0x1ul << ECAP_CTL1_CAP0RLDEN_Pos) /*!< ECAP_T::CTL1: CAP0RLDEN Mask */ + +#define ECAP_CTL1_CAP1RLDEN_Pos (9) /*!< ECAP_T::CTL1: CAP1RLDEN Position */ +#define ECAP_CTL1_CAP1RLDEN_Msk (0x1ul << ECAP_CTL1_CAP1RLDEN_Pos) /*!< ECAP_T::CTL1: CAP1RLDEN Mask */ + +#define ECAP_CTL1_CAP2RLDEN_Pos (10) /*!< ECAP_T::CTL1: CAP2RLDEN Position */ +#define ECAP_CTL1_CAP2RLDEN_Msk (0x1ul << ECAP_CTL1_CAP2RLDEN_Pos) /*!< ECAP_T::CTL1: CAP2RLDEN Mask */ + +#define ECAP_CTL1_OVRLDEN_Pos (11) /*!< ECAP_T::CTL1: OVRLDEN Position */ +#define ECAP_CTL1_OVRLDEN_Msk (0x1ul << ECAP_CTL1_OVRLDEN_Pos) /*!< ECAP_T::CTL1: OVRLDEN Mask */ + +#define ECAP_CTL1_CLKSEL_Pos (12) /*!< ECAP_T::CTL1: CLKSEL Position */ +#define ECAP_CTL1_CLKSEL_Msk (0x7ul << ECAP_CTL1_CLKSEL_Pos) /*!< ECAP_T::CTL1: CLKSEL Mask */ + +#define ECAP_CTL1_CNTSRCSEL_Pos (16) /*!< ECAP_T::CTL1: CNTSRCSEL Position */ +#define ECAP_CTL1_CNTSRCSEL_Msk (0x3ul << ECAP_CTL1_CNTSRCSEL_Pos) /*!< ECAP_T::CTL1: CNTSRCSEL Mask */ + +#define ECAP_CTL1_CAP0CLREN_Pos (20) /*!< ECAP_T::CTL1: CAP0CLREN Position */ +#define ECAP_CTL1_CAP0CLREN_Msk (0x1ul << ECAP_CTL1_CAP0CLREN_Pos) /*!< ECAP_T::CTL1: CAP0CLREN Mask */ + +#define ECAP_CTL1_CAP1CLREN_Pos (21) /*!< ECAP_T::CTL1: CAP1CLREN Position */ +#define ECAP_CTL1_CAP1CLREN_Msk (0x1ul << ECAP_CTL1_CAP1CLREN_Pos) /*!< ECAP_T::CTL1: CAP1CLREN Mask */ + +#define ECAP_CTL1_CAP2CLREN_Pos (22) /*!< ECAP_T::CTL1: CAP2CLREN Position */ +#define ECAP_CTL1_CAP2CLREN_Msk (0x1ul << ECAP_CTL1_CAP2CLREN_Pos) /*!< ECAP_T::CTL1: CAP2CLREN Mask */ + +#define ECAP_STATUS_CAPTF0_Pos (0) /*!< ECAP_T::STATUS: CAPTF0 Position */ +#define ECAP_STATUS_CAPTF0_Msk (0x1ul << ECAP_STATUS_CAPTF0_Pos) /*!< ECAP_T::STATUS: CAPTF0 Mask */ + +#define ECAP_STATUS_CAPTF1_Pos (1) /*!< ECAP_T::STATUS: CAPTF1 Position */ +#define ECAP_STATUS_CAPTF1_Msk (0x1ul << ECAP_STATUS_CAPTF1_Pos) /*!< ECAP_T::STATUS: CAPTF1 Mask */ + +#define ECAP_STATUS_CAPTF2_Pos (2) /*!< ECAP_T::STATUS: CAPTF2 Position */ +#define ECAP_STATUS_CAPTF2_Msk (0x1ul << ECAP_STATUS_CAPTF2_Pos) /*!< ECAP_T::STATUS: CAPTF2 Mask */ + +#define ECAP_STATUS_CAPCMPF_Pos (4) /*!< ECAP_T::STATUS: CAPCMPF Position */ +#define ECAP_STATUS_CAPCMPF_Msk (0x1ul << ECAP_STATUS_CAPCMPF_Pos) /*!< ECAP_T::STATUS: CAPCMPF Mask */ + +#define ECAP_STATUS_CAPOVF_Pos (5) /*!< ECAP_T::STATUS: CAPOVF Position */ +#define ECAP_STATUS_CAPOVF_Msk (0x1ul << ECAP_STATUS_CAPOVF_Pos) /*!< ECAP_T::STATUS: CAPOVF Mask */ + +#define ECAP_STATUS_CAP0_Pos (8) /*!< ECAP_T::STATUS: CAP0 Position */ +#define ECAP_STATUS_CAP0_Msk (0x1ul << ECAP_STATUS_CAP0_Pos) /*!< ECAP_T::STATUS: CAP0 Mask */ + +#define ECAP_STATUS_CAP1_Pos (9) /*!< ECAP_T::STATUS: CAP1 Position */ +#define ECAP_STATUS_CAP1_Msk (0x1ul << ECAP_STATUS_CAP1_Pos) /*!< ECAP_T::STATUS: CAP1 Mask */ + +#define ECAP_STATUS_CAP2_Pos (10) /*!< ECAP_T::STATUS: CAP2 Position */ +#define ECAP_STATUS_CAP2_Msk (0x1ul << ECAP_STATUS_CAP2_Pos) /*!< ECAP_T::STATUS: CAP2 Mask */ + +/**@}*/ /* ECAP_CONST */ +/**@}*/ /* end of ECAP register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __ECAP_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/emac_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/emac_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..831df4a3a1f5ee7d93fb984cb45c0cbebf0f7aaa --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/emac_reg.h @@ -0,0 +1,2063 @@ +/**************************************************************************//** + * @file emac_reg.h + * @version V1.00 + * @brief EMAC register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EMAC_REG_H__ +#define __EMAC_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup EMAC Ethernet MAC Controller(EMAC) + Memory Mapped Structure for EMAC Controller +@{ */ + +typedef struct +{ + + /** + * @var EMAC_T::CAMCTL + * Offset: 0x00 CAM Comparison Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |AUP |Accept Unicast Packet + * | | |The AUP controls the unicast packet reception + * | | |If AUP is enabled, EMAC receives all incoming packet its destination MAC address is a unicast address. + * | | |0 = EMAC receives packet depends on the CAM comparison result. + * | | |1 = EMAC receives all unicast packets. + * |[1] |AMP |Accept Multicast Packet + * | | |The AMP controls the multicast packet reception + * | | |If AMP is enabled, EMAC receives all incoming packet its destination MAC address is a multicast address. + * | | |0 = EMAC receives packet depends on the CAM comparison result. + * | | |1 = EMAC receives all multicast packets. + * |[2] |ABP |Accept Broadcast Packet + * | | |The ABP controls the broadcast packet reception + * | | |If ABP is enabled, EMAC receives all incoming packet its destination MAC address is a broadcast address. + * | | |0 = EMAC receives packet depends on the CAM comparison result. + * | | |1 = EMAC receives all broadcast packets. + * |[3] |COMPEN |Complement CAM Comparison Enable Bit + * | | |The COMPEN controls the complement of the CAM comparison result + * | | |If the CMPEN and COMPEN are both enabled, the incoming packet with specific destination MAC address + * | | |configured in CAM entry will be dropped + * | | |And the incoming packet with destination MAC address does not configured in any CAM entry will be received. + * | | |0 = Complement CAM comparison result Disabled. + * | | |1 = Complement CAM comparison result Enabled. + * |[4] |CMPEN |CAM Compare Enable Bit + * | | |The CMPEN controls the enable of CAM comparison function for destination MAC address recognition + * | | |If software wants to receive a packet with specific destination MAC address, configures the MAC address + * | | |into CAM 12~0, then enables that CAM entry and set CMPEN to 1. + * | | |0 = CAM comparison function for destination MAC address recognition Disabled. + * | | |1 = CAM comparison function for destination MAC address recognition Enabled. + * @var EMAC_T::CAMEN + * Offset: 0x04 CAM Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAMxEN |CAM Entry X Enable Bit + * | | |The CAMxEN controls the validation of CAM entry x. + * | | |The CAM entry 13, 14 and 15 are for PAUSE control frame transmission + * | | |If software wants to transmit a PAUSE control frame out to network, the enable bits of these three CAM + * | | |entries all must be enabled first. + * | | |0 = CAM entry x Disabled. + * | | |1 = CAM entry x Enabled. + * @var EMAC_T::CAM0M + * Offset: 0x08 CAM0 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM0L + * Offset: 0x0C CAM0 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM1M + * Offset: 0x10 CAM1 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM1L + * Offset: 0x14 CAM1 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM2M + * Offset: 0x18 CAM2 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM2L + * Offset: 0x1C CAM2 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM3M + * Offset: 0x20 CAM3 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM3L + * Offset: 0x24 CAM3 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM4M + * Offset: 0x28 CAM4 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM4L + * Offset: 0x2C CAM4 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM5M + * Offset: 0x30 CAM5 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM5L + * Offset: 0x34 CAM5 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM6M + * Offset: 0x38 CAM6 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM6L + * Offset: 0x3C CAM6 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM7M + * Offset: 0x40 CAM7 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM7L + * Offset: 0x44 CAM7 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM8M + * Offset: 0x48 CAM8 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM8L + * Offset: 0x4C CAM8 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM9M + * Offset: 0x50 CAM9 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM9L + * Offset: 0x54 CAM9 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM10M + * Offset: 0x58 CAM10 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM10L + * Offset: 0x5C CAM10 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM11M + * Offset: 0x60 CAM11 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM11L + * Offset: 0x64 CAM11 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM12M + * Offset: 0x68 CAM12 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM12L + * Offset: 0x6C CAM12 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM13M + * Offset: 0x70 CAM13 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM13L + * Offset: 0x74 CAM13 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM14M + * Offset: 0x78 CAM14 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM14L + * Offset: 0x7C CAM14 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM15MSB + * Offset: 0x80 CAM15 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |OPCODE |OP Code Field of PAUSE Control Frame + * | | |In the PAUSE control frame, an op code field defined and is 0x0001. + * |[31:16] |LENGTH |LENGTH Field of PAUSE Control Frame + * | | |In the PAUSE control frame, a LENGTH field defined and is 0x8808. + * @var EMAC_T::CAM15LSB + * Offset: 0x84 CAM15 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:24] |OPERAND |Pause Parameter + * | | |In the PAUSE control frame, an OPERAND field defined and controls how much time the destination + * | | |Ethernet MAC Controller paused + * | | |The unit of the OPERAND is a slot time, the 512-bit time. + * @var EMAC_T::TXDSA + * Offset: 0x88 Transmit Descriptor Link List Start Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TXDSA |Transmit Descriptor Link-list Start Address + * | | |The TXDSA keeps the start address of transmit descriptor link-list + * | | |If the software enables the bit TXON (EMAC_CTL[8]), the content of TXDSA will be loaded into the + * | | |current transmit descriptor start address register (EMAC_CTXDSA) + * | | |The TXDSA does not be updated by EMAC + * | | |During the operation, EMAC will ignore the bits [1:0] of TXDSA + * | | |This means that TX descriptors must locate at word boundary memory address. + * @var EMAC_T::RXDSA + * Offset: 0x8C Receive Descriptor Link List Start Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RXDSA |Receive Descriptor Link-list Start Address + * | | |The RXDSA keeps the start address of receive descriptor link-list + * | | |If the S/W enables the bit RXON (EMAC_CTL[0]), the content of RXDSA will be loaded into the current + * | | |receive descriptor start address register (EMAC_CRXDSA) + * | | |The RXDSA does not be updated by EMAC + * | | |During the operation, EMAC will ignore the bits [1:0] of RXDSA + * | | |This means that RX descriptors must locate at word boundary memory address. + * @var EMAC_T::CTL + * Offset: 0x90 MAC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXON |Frame Reception ON + * | | |The RXON controls the normal packet reception of EMAC + * | | |If the RXON is set to high, the EMAC starts the packet reception process, including the RX + * | | |descriptor fetching, packet reception and RX descriptor modification. + * | | |It is necessary to finish EMAC initial sequence before enable RXON + * | | |Otherwise, the EMAC operation is undefined. + * | | |If the RXON is disabled during EMAC is receiving an incoming packet, the EMAC stops the packet + * | | |reception process after the current packet reception finished. + * | | |0 = Packet reception process stopped. + * | | |1 = Packet reception process started. + * |[1] |ALP |Accept Long Packet + * | | |The ALP controls the long packet, which packet length is greater than 1518 bytes, reception + * | | |If the ALP is set to high, the EMAC will accept the long packet. + * | | |Otherwise, the long packet will be dropped. + * | | |0 = Ethernet MAC controller dropped the long packet. + * | | |1 = Ethernet MAC controller received the long packet. + * |[2] |ARP |Accept Runt Packet + * | | |The ARP controls the runt packet, which length is less than 64 bytes, reception + * | | |If the ARP is set to high, the EMAC will accept the runt packet. + * | | |Otherwise, the runt packet will be dropped. + * | | |0 = Ethernet MAC controller dropped the runt packet. + * | | |1 = Ethernet MAC controller received the runt packet. + * |[3] |ACP |Accept Control Packet + * | | |The ACP controls the control frame reception + * | | |If the ACP is set to high, the EMAC will accept the control frame + * | | |Otherwise, the control frame will be dropped + * | | |It is recommended that S/W only enable ACP while EMAC is operating on full duplex mode. + * | | |0 = Ethernet MAC controller dropped the control frame. + * | | |1 = Ethernet MAC controller received the control frame. + * |[4] |AEP |Accept CRC Error Packet + * | | |The AEP controls the EMAC accepts or drops the CRC error packet + * | | |If the AEP is set to high, the incoming packet with CRC error will be received by EMAC as a good packet. + * | | |0 = Ethernet MAC controller dropped the CRC error packet. + * | | |1 = Ethernet MAC controller received the CRC error packet. + * |[5] |STRIPCRC |Strip CRC Checksum + * | | |The STRIPCRC controls if the length of incoming packet is calculated with 4 bytes CRC checksum + * | | |If the STRIPCRC is set to high, 4 bytes CRC checksum is excluded from length calculation of incoming packet. + * | | |0 = The 4 bytes CRC checksum is included in packet length calculation. + * | | |1 = The 4 bytes CRC checksum is excluded in packet length calculation. + * |[6] |WOLEN |Wake on LAN Enable Bit + * | | |The WOLEN high enables the functionality that Ethernet MAC controller checked if the incoming packet + * | | |is Magic Packet and wakeup system from Power-down mode. + * | | |If incoming packet was a Magic Packet and the system was in Power-down, the Ethernet MAC controller + * | | |would generate a wakeup event to wake system up from Power-down mode. + * | | |0 = Wake-up by Magic Packet function Disabled. + * | | |1 = Wake-up by Magic Packet function Enabled. + * |[8] |TXON |Frame Transmission ON + * | | |The TXON controls the normal packet transmission of EMAC + * | | |If the TXON is set to high, the EMAC starts the packet transmission process, including the TX + * | | |descriptor fetching, packet transmission and TX descriptor modification. + * | | |It is must to finish EMAC initial sequence before enable TXON + * | | |Otherwise, the EMAC operation is undefined. + * | | |If the TXON is disabled during EMAC is transmitting a packet out, the EMAC stops the packet + * | | |transmission process after the current packet transmission finished. + * | | |0 = Packet transmission process stopped. + * | | |1 = Packet transmission process started. + * |[9] |NODEF |No Deferral + * | | |The NODEF controls the enable of deferral exceed counter + * | | |If NODEF is set to high, the deferral exceed counter is disabled + * | | |The NODEF is only useful while EMAC is operating on half duplex mode. + * | | |0 = The deferral exceed counter Enabled. + * | | |1 = The deferral exceed counter Disabled. + * |[16] |SDPZ |Send PAUSE Frame + * | | |The SDPZ controls the PAUSE control frame transmission. + * | | |If S/W wants to send a PAUSE control frame out, the CAM entry 13, 14 and 15 must be configured + * | | |first and the corresponding CAM enable bit of CAMEN register also must be set. + * | | |Then, set SDPZ to 1 enables the PAUSE control frame transmission. + * | | |The SDPZ is a self-clear bit + * | | |This means after the PAUSE control frame transmission has completed, the SDPZ will be cleared automatically. + * | | |It is recommended that only enabling SNDPAUSE while EMAC is operating in Full Duplex mode. + * | | |0 = PAUSE control frame transmission completed. + * | | |1 = PAUSE control frame transmission Enabled. + * |[17] |SQECHKEN |SQE Checking Enable Bit + * | | |The SQECHKEN controls the enable of SQE checking + * | | |The SQE checking is only available while EMAC is operating on 10M bps and half duplex mode + * | | |In other words, the SQECHKEN cannot affect EMAC operation, if the EMAC is operating on 100Mbps + * | | |or full duplex mode. + * | | |0 = SQE checking Disabled while EMAC is operating in 10Mbps and Half Duplex mode. + * | | |1 = SQE checking Enabled while EMAC is operating in 10Mbps and Half Duplex mode. + * |[18] |FUDUP |Full Duplex Mode Selection + * | | |The FUDUP controls that if EMAC is operating on full or half duplex mode. + * | | |0 = EMAC operates in half duplex mode. + * | | |1 = EMAC operates in full duplex mode. + * |[19] |RMIIRXCTL |RMII RX Control + * | | |The RMIIRXCTL control the receive data sample in RMII mode + * | | |It's necessary to set this bit high when RMIIEN (EMAC_CTL[ [22]) is high. + * | | |0 = RMII RX control disabled. + * | | |1 = RMII RX control enabled. + * |[20] |OPMODE |Operation Mode Selection + * | | |The OPMODE defines that if the EMAC is operating on 10M or 100M bps mode + * | | |The RST (EMAC_CTL[24]) would not affect OPMODE value. + * | | |0 = EMAC operates in 10Mbps mode. + * | | |1 = EMAC operates in 100Mbps mode. + * |[22] |RMIIEN |RMII Mode Enable Bit + * | | |This bit controls if Ethernet MAC controller connected with off-chip Ethernet PHY by MII + * | | |interface or RMII interface + * | | |The RST (EMAC_CTL[24]) would not affect RMIIEN value. + * | | |0 = Ethernet MAC controller RMII mode Disabled. + * | | |1 = Ethernet MAC controller RMII mode Enabled. + * | | |NOTE: This field must keep 1. + * |[24] |RST |Software Reset + * | | |The RST implements a reset function to make the EMAC return default state + * | | |The RST is a self-clear bit + * | | |This means after the software reset finished, the RST will be cleared automatically + * | | |Enable RST can also reset all control and status registers, exclusive of the control bits + * | | |RMIIEN (EMAC_CTL[22]), and OPMODE (EMAC_CTL[20]). + * | | |The EMAC re-initial is necessary after the software reset completed. + * | | |0 = Software reset completed. + * | | |1 = Software reset Enabled. + * @var EMAC_T::MIIMDAT + * Offset: 0x94 MII Management Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |DATA |MII Management Data + * | | |The DATA is the 16 bits data that will be written into the registers of external PHY for MII + * | | |Management write command or the data from the registers of external PHY for MII Management read command. + * @var EMAC_T::MIIMCTL + * Offset: 0x98 MII Management Control and Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PHYREG |PHY Register Address + * | | |The PHYREG keeps the address to indicate which register of external PHY is the target of the + * | | |MII management command. + * |[12:8] |PHYADDR |PHY Address + * | | |The PHYADDR keeps the address to differentiate which external PHY is the target of the MII management command. + * |[16] |WRITE |Write Command + * | | |The Write defines the MII management command is a read or write. + * | | |0 = MII management command is a read command. + * | | |1 = MII management command is a write command. + * |[17] |BUSY |Busy Bit + * | | |The BUSY controls the enable of the MII management frame generation + * | | |If S/W wants to access registers of external PHY, it set BUSY to high and EMAC generates + * | | |the MII management frame to external PHY through MII Management I/F + * | | |The BUSY is a self-clear bit + * | | |This means the BUSY will be cleared automatically after the MII management command finished. + * | | |0 = MII management command generation finished. + * | | |1 = MII management command generation Enabled. + * |[18] |PREAMSP |Preamble Suppress + * | | |The PREAMSP controls the preamble field generation of MII management frame + * | | |If the PREAMSP is set to high, the preamble field generation of MII management frame is skipped. + * | | |0 = Preamble field generation of MII management frame not skipped. + * | | |1 = Preamble field generation of MII management frame skipped. + * |[19] |MDCON |MDC Clock ON + * | | |The MDC controls the MDC clock generation. If the MDCON is set to high, the MDC clock is turned on. + * | | |0 = MDC clock off. + * | | |1 = MDC clock on. + * @var EMAC_T::FIFOCTL + * Offset: 0x9C FIFO Threshold Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |RXFIFOTH |RXFIFO Low Threshold + * | | |The RXFIFOTH controls when RXDMA requests internal arbiter for data transfer between RXFIFO + * | | |and system memory + * | | |The RXFIFOTH defines not only the high threshold of RXFIFO, but also the low threshold + * | | |The low threshold is the half of high threshold always + * | | |During the packet reception, if the RXFIFO reaches the high threshold, the RXDMA starts to + * | | |transfer frame data from RXFIFO to system memory + * | | |If the frame data in RXFIFO is less than low threshold, RXDMA stops to transfer the frame + * | | |data to system memory. + * | | |00 = Depend on the burst length setting + * | | |If the burst length is 8 words, high threshold is 8 words, too. + * | | |01 = RXFIFO high threshold is 64B and low threshold is 32B. + * | | |10 = RXFIFO high threshold is 128B and low threshold is 64B. + * | | |11 = RXFIFO high threshold is 192B and low threshold is 96B. + * |[9:8] |TXFIFOTH |TXFIFO Low Threshold + * | | |The TXFIFOTH controls when TXDMA requests internal arbiter for data transfer between system + * | | |memory and TXFIFO + * | | |The TXFIFOTH defines not only the low threshold of TXFIFO, but also the high threshold + * | | |The high threshold is the twice of low threshold always + * | | |During the packet transmission, if the TXFIFO reaches the high threshold, the TXDMA stops + * | | |generate request to transfer frame data from system memory to TXFIFO + * | | |If the frame data in TXFIFO is less than low threshold, TXDMA starts to transfer frame data + * | | |from system memory to TXFIFO. + * | | |The TXFIFOTH also defines when the TXMAC starts to transmit frame out to network + * | | |The TXMAC starts to transmit the frame out while the TXFIFO first time reaches the high threshold + * | | |during the transmission of the frame + * | | |If the frame data length is less than TXFIFO high threshold, the TXMAC starts to transmit the frame + * | | |out after the frame data are all inside the TXFIFO. + * | | |00 = Undefined. + * | | |01 = TXFIFO low threshold is 64B and high threshold is 128B. + * | | |10 = TXFIFO low threshold is 80B and high threshold is 160B. + * | | |11 = TXFIFO low threshold is 96B and high threshold is 192B. + * |[21:20] |BURSTLEN |DMA Burst Length + * | | |This defines the burst length of AHB bus cycle while EMAC accesses system memory. + * | | |00 = 4 words. + * | | |01 = 8 words. + * | | |10 = 16 words. + * | | |11 = 16 words. + * @var EMAC_T::TXST + * Offset: 0xA0 Transmit Start Demand Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TXST |Transmit Start Demand + * | | |If the TX descriptor is not available for use of TXDMA after the TXON (EMAC_CTL[8]) is enabled, + * | | |the FSM (Finite State Machine) of TXDMA enters the Halt state and the frame transmission is halted + * | | |After the S/W has prepared the new TX descriptor for frame transmission, it must issue a write + * | | |command to EMAC_TXST register to make TXDMA to leave Halt state and continue the frame transmission. + * | | |The EMAC_TXST is a write only register and read from this register is undefined. + * | | |The write to EMAC_TXST register takes effect only when TXDMA stayed at Halt state. + * @var EMAC_T::RXST + * Offset: 0xA4 Receive Start Demand Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RXST |Receive Start Demand + * | | |If the RX descriptor is not available for use of RXDMA after the RXON (EMAC_CTL[0]) is enabled, + * | | |the FSM (Finite State Machine) of RXDMA enters the Halt state and the frame reception is halted + * | | |After the S/W has prepared the new RX descriptor for frame reception, it must issue a write + * | | |command to EMAC_RXST register to make RXDMA to leave Halt state and continue the frame reception. + * | | |The EMAC_RXST is a write only register and read from this register is undefined. + * | | |The write to EMAC_RXST register take effect only when RXDMA stayed at Halt state. + * @var EMAC_T::MRFL + * Offset: 0xA8 Maximum Receive Frame Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |MRFL |Maximum Receive Frame Length + * | | |The MRFL defines the maximum frame length for received frame + * | | |If the frame length of received frame is greater than MRFL, and bit MFLEIEN (EMAC_INTEN[8]) + * | | |is also enabled, the bit MFLEIF (EMAC_INTSTS[8]) is set and the RX interrupt is triggered. + * | | |It is recommended that only use MRFL to qualify the length of received frame while S/W wants to + * | | |receive a frame which length is greater than 1518 bytes. + * @var EMAC_T::INTEN + * Offset: 0xAC MAC Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXIEN |Receive Interrupt Enable Bit + * | | |The RXIEN controls the RX interrupt generation. + * | | |If RXIEN is enabled and RXIF (EMAC_INTSTS[0]) is high, EMAC generates the RX interrupt to CPU + * | | |If RXIEN is disabled, no RX interrupt is generated to CPU even any status bit EMAC_INTSTS[15:1] + * | | |is set and the corresponding bit of EMAC_INTEN is enabled + * | | |In other words, if S/W wants to receive RX interrupt from EMAC, this bit must be enabled + * | | |And, if S/W doesn't want to receive any RX interrupt from EMAC, disables this bit. + * | | |0 = RXIF (EMAC_INTSTS[0]) is masked and RX interrupt generation Disabled. + * | | |1 = RXIF (EMAC_INTSTS[0]) is not masked and RX interrupt generation Enabled. + * |[1] |CRCEIEN |CRC Error Interrupt Enable Bit + * | | |The CRCEIEN controls the CRCEIF (EMAC_INTSTS[1]) interrupt generation + * | | |If CRCEIF (EMAC_INTSTS[1]) is set, and both CRCEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the + * | | |EMAC generates the RX interrupt to CPU + * | | |If CRCEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |CRCEIF (EMAC_INTSTS[1]) is set. + * | | |0 = CRCEIF (EMAC_INTSTS[1]) trigger RX interrupt Disabled. + * | | |1 = CRCEIF (EMAC_INTSTS[1]) trigger RX interrupt Enabled. + * |[2] |RXOVIEN |Receive FIFO Overflow Interrupt Enable Bit + * | | |The RXOVIEN controls the RXOVIF (EMAC_INTSTS[2]) interrupt generation + * | | |If RXOVIF (EMAC_INTSTS[2]) is set, and both RXOVIEN and RXIEN (EMAC_INTEN[0]) are enabled, the + * | | |EMAC generates the RX interrupt to CPU + * | | |If RXOVIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |RXOVIF (EMAC_INTSTS[2]) is set. + * | | |0 = RXOVIF (EMAC_INTSTS[2]) trigger RX interrupt Disabled. + * | | |1 = RXOVIF (EMAC_INTSTS[2]) trigger RX interrupt Enabled. + * |[3] |LPIEN |Long Packet Interrupt Enable Bit + * | | |The LPIEN controls the LPIF (EMAC_INTSTS[3]) interrupt generation + * | | |If LPIF (EMAC_INTSTS[3]) is set, and both LPIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC + * | | |generates the RX interrupt to CPU + * | | |If LPIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the LPIF + * | | |(EMAC_INTSTS[3]) is set. + * | | |0 = LPIF (EMAC_INTSTS[3]) trigger RX interrupt Disabled. + * | | |1 = LPIF (EMAC_INTSTS[3]) trigger RX interrupt Enabled. + * |[4] |RXGDIEN |Receive Good Interrupt Enable Bit + * | | |The RXGDIEN controls the RXGDIF (EMAC_INTSTS[4]) interrupt generation + * | | |If RXGDIF (EMAC_INTSTS[4]) is set, and both RXGDIEN and RXIEN (EMAC_INTEN[0]) are enabled, the + * | | |EMAC generates the RX interrupt to CPU + * | | |If RXGDIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |RXGDIF (EMAC_INTSTS[4]) is set. + * | | |0 = RXGDIF (EMAC_INTSTS[4]) trigger RX interrupt Disabled. + * | | |1 = RXGDIF (EMAC_INTSTS[4]) trigger RX interrupt Enabled. + * |[5] |ALIEIEN |Alignment Error Interrupt Enable Bit + * | | |The ALIEIEN controls the ALIEIF (EMAC_INTSTS[5]) interrupt generation + * | | |If ALIEIF (EMAC_INTSTS[5]) is set, and both ALIEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the + * | | |EMAC generates the RX interrupt to CPU + * | | |If ALIEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |ALIEIF (EMAC_INTSTS[5]) is set. + * | | |0 = ALIEIF (EMAC_INTSTS[5]) trigger RX interrupt Disabled. + * | | |1 = ALIEIF (EMAC_INTSTS[5]) trigger RX interrupt Enabled. + * |[6] |RPIEN |Runt Packet Interrupt Enable Bit + * | | |The RPIEN controls the RPIF (EMAC_INTSTS[6]) interrupt generation + * | | |If RPIF (EMAC_INTSTS[6]) is set, and both RPIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC + * | | |generates the RX interrupt to CPU + * | | |If RPIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |RPIF (EMAC_INTSTS[6]) is set. + * | | |0 = RPIF (EMAC_INTSTS[6]) trigger RX interrupt Disabled. + * | | |1 = RPIF (EMAC_INTSTS[6]) trigger RX interrupt Enabled. + * |[7] |MPCOVIEN |Miss Packet Counter Overrun Interrupt Enable Bit + * | | |The MPCOVIEN controls the MPCOVIF (EMAC_INTSTS[7]) interrupt generation + * | | |If MPCOVIF (EMAC_INTSTS[7]) is set, and both MPCOVIEN and RXIEN (EMAC_INTEN[0]) are enabled, + * | | |the EMAC generates the RX interrupt to CPU + * | | |If MPCOVIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |MPCOVIF (EMAC_INTSTS[7]) is set. + * | | |0 = MPCOVIF (EMAC_INTSTS[7]) trigger RX interrupt Disabled. + * | | |1 = MPCOVIF (EMAC_INTSTS[7]) trigger RX interrupt Enabled. + * |[8] |MFLEIEN |Maximum Frame Length Exceed Interrupt Enable Bit + * | | |The MFLEIEN controls the MFLEIF (EMAC_INTSTS[8]) interrupt generation + * | | |If MFLEIF (EMAC_INTSTS[8]) is set, and both MFLEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the + * | | |EMAC generates the RX interrupt to CPU + * | | |If MFLEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |MFLEIF (EMAC_INTSTS[8]) is set. + * | | |0 = MFLEIF (EMAC_INTSTS[8]) trigger RX interrupt Disabled. + * | | |1 = MFLEIF (EMAC_INTSTS[8]) trigger RX interrupt Enabled. + * |[9] |DENIEN |DMA Early Notification Interrupt Enable Bit + * | | |The DENIEN controls the DENIF (EMAC_INTSTS[9]) interrupt generation + * | | |If DENIF (EMAC_INTSTS[9]) is set, and both DENIEN and RXIEN (EMAC_INTEN[0]) are enabled, the + * | | |EMAC generates the RX interrupt to CPU + * | | |If DENIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |DENIF (EMAC_INTSTS[9]) is set. + * | | |0 = TDENIF (EMAC_INTSTS[9]) trigger RX interrupt Disabled. + * | | |1 = TDENIF (EMAC_INTSTS[9]) trigger RX interrupt Enabled. + * |[10] |RDUIEN |Receive Descriptor Unavailable Interrupt Enable Bit + * | | |The RDUIEN controls the RDUIF (EMAC_INTSTS[10]) interrupt generation + * | | |If RDUIF (EMAC_INTSTS[10]) is set, and both RDUIEN and RXIEN (EMAC_INTEN[0]) are enabled, the + * | | |EMAC generates the RX interrupt to CPU + * | | |If RDUIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |RDUIF (EMAC_MIOSTA[10]) register is set. + * | | |0 = RDUIF (EMAC_INTSTS[10]) trigger RX interrupt Disabled. + * | | |1 = RDUIF (EMAC_INTSTS[10]) trigger RX interrupt Enabled. + * |[11] |RXBEIEN |Receive Bus Error Interrupt Enable Bit + * | | |The RXBEIEN controls the RXBEIF (EMAC_INTSTS[11]) interrupt generation + * | | |If RXBEIF (EMAC_INTSTS[11]) is set, and both RXBEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the + * | | |EMAC generates the RX interrupt to CPU + * | | |If RXBEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |RXBEIF (EMAC_INTSTS[11]) is set. + * | | |0 = RXBEIF (EMAC_INTSTS[11]) trigger RX interrupt Disabled. + * | | |1 = RXBEIF (EMAC_INTSTS[11]) trigger RX interrupt Enabled. + * |[14] |CFRIEN |Control Frame Receive Interrupt Enable Bit + * | | |The CFRIEN controls the CFRIF (EMAC_INTSTS[14]) interrupt generation + * | | |If CFRIF (EMAC_INTSTS[14]) is set, and both CFRIEN and RXIEN (EMAC_INTEN[0]) are enabled, the + * | | |EMAC generates the RX interrupt to CPU + * | | |If CFRIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |CFRIF (EMAC_INTSTS[14]) register is set. + * | | |0 = CFRIF (EMAC_INTSTS[14]) trigger RX interrupt Disabled. + * | | |1 = CFRIF (EMAC_INTSTS[14]) trigger RX interrupt Enabled. + * |[15] |WOLIEN |Wake on LAN Interrupt Enable Bit + * | | |The WOLIEN controls the WOLIF (EMAC_INTSTS[15]) interrupt generation + * | | |If WOLIF (EMAC_INTSTS[15]) is set, and both WOLIEN and RXIEN (EMAC_INTEN[0]) are enabled, + * | | |the EMAC generates the RX interrupt to CPU + * | | |If WOLIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |WOLIF (EMAC_INTSTS[15]) is set. + * | | |0 = WOLIF (EMAC_INTSTS[15]) trigger RX interrupt Disabled. + * | | |1 = WOLIF (EMAC_INTSTS[15]) trigger RX interrupt Enabled. + * |[16] |TXIEN |Transmit Interrupt Enable Bit + * | | |The TXIEN controls the TX interrupt generation. + * | | |If TXIEN is enabled and TXIF (EMAC_INTSTS[16]) is high, EMAC generates the TX interrupt to CPU + * | | |If TXIEN is disabled, no TX interrupt is generated to CPU even any status bit of + * | | |EMAC_INTSTS[24:17] set and the corresponding bit of EMAC_INTEN is enabled + * | | |In other words, if S/W wants to receive TX interrupt from EMAC, this bit must be enabled + * | | |And, if S/W doesn't want to receive any TX interrupt from EMAC, disables this bit. + * | | |0 = TXIF (EMAC_INTSTS[16]) is masked and TX interrupt generation Disabled. + * | | |1 = TXIF (EMAC_INTSTS[16]) is not masked and TX interrupt generation Enabled. + * |[17] |TXUDIEN |Transmit FIFO Underflow Interrupt Enable Bit + * | | |The TXUDIEN controls the TXUDIF (EMAC_INTSTS[17]) interrupt generation + * | | |If TXUDIF (EMAC_INTSTS[17]) is set, and both TXUDIEN and TXIEN (EMAC_INTEN[16]) are enabled, + * | | |the EMAC generates the TX interrupt to CPU + * | | |If TXUDIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even + * | | |the TXUDIF (EMAC_INTSTS[17]) is set. + * | | |0 = TXUDIF (EMAC_INTSTS[17]) TX interrupt Disabled. + * | | |1 = TXUDIF (EMAC_INTSTS[17]) TX interrupt Enabled. + * |[18] |TXCPIEN |Transmit Completion Interrupt Enable Bit + * | | |The TXCPIEN controls the TXCPIF (EMAC_INTSTS[18]) interrupt generation + * | | |If TXCPIF (EMAC_INTSTS[18]) is set, and both TXCPIEN and TXIEN (EMAC_INTEN[16]) are enabled, + * | | |the EMAC generates the TX interrupt to CPU + * | | |If TXCPIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the + * | | |TXCPIF (EMAC_INTSTS[18]) is set. + * | | |0 = TXCPIF (EMAC_INTSTS[18]) trigger TX interrupt Disabled. + * | | |1 = TXCPIF (EMAC_INTSTS[18]) trigger TX interrupt Enabled. + * |[19] |EXDEFIEN |Defer Exceed Interrupt Enable Bit + * | | |The EXDEFIEN controls the EXDEFIF (EMAC_INTSTS[19]) interrupt generation + * | | |If EXDEFIF (EMAC_INTSTS[19]) is set, and both EXDEFIEN and TXIEN (EMAC_INTEN[16]) are enabled, + * | | |the EMAC generates the TX interrupt to CPU + * | | |If EXDEFIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the + * | | |EXDEFIF (EMAC_INTSTS[19]) is set. + * | | |0 = EXDEFIF (EMAC_INTSTS[19]) trigger TX interrupt Disabled. + * | | |1 = EXDEFIF (EMAC_INTSTS[19]) trigger TX interrupt Enabled. + * |[20] |NCSIEN |No Carrier Sense Interrupt Enable Bit + * | | |The NCSIEN controls the NCSIF (EMAC_INTSTS[20]) interrupt generation + * | | |If NCSIF (EMAC_INTSTS[20]) is set, and both NCSIEN and TXIEN (EMAC_INTEN[16]) are enabled, the + * | | |EMAC generates the TX interrupt to CPU + * | | |If NCSIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the + * | | |NCSIF (EMAC_INTSTS[20]) is set. + * | | |0 = NCSIF (EMAC_INTSTS[20]) trigger TX interrupt Disabled. + * | | |1 = NCSIF (EMAC_INTSTS[20]) trigger TX interrupt Enabled. + * |[21] |TXABTIEN |Transmit Abort Interrupt Enable Bit + * | | |The TXABTIEN controls the TXABTIF (EMAC_INTSTS[21]) interrupt generation + * | | |If TXABTIF (EMAC_INTSTS[21]) is set, and both TXABTIEN and TXIEN (EMAC_INTEN[16]) are enabled, + * | | |the EMAC generates the TX interrupt to CPU + * | | |If TXABTIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the + * | | |TXABTIF (EMAC_INTSTS[21]) is set. + * | | |0 = TXABTIF (EMAC_INTSTS[21]) trigger TX interrupt Disabled. + * | | |1 = TXABTIF (EMAC_INTSTS[21]) trigger TX interrupt Enabled. + * |[22] |LCIEN |Late Collision Interrupt Enable Bit + * | | |The LCIEN controls the LCIF (EMAC_INTSTS[22]) interrupt generation + * | | |If LCIF (EMAC_INTSTS[22]) is set, and both LCIEN and TXIEN (EMAC_INTEN[16]) are enabled, the + * | | |EMAC generates the TX interrupt to CPU + * | | |If LCIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the + * | | |LCIF (EMAC_INTSTS[22]) is set. + * | | |0 = LCIF (EMAC_INTSTS[22]) trigger TX interrupt Disabled. + * | | |1 = LCIF (EMAC_INTSTS[22]) trigger TX interrupt Enabled. + * |[23] |TDUIEN |Transmit Descriptor Unavailable Interrupt Enable Bit + * | | |The TDUIEN controls the TDUIF (EMAC_INTSTS[23]) interrupt generation + * | | |If TDUIF (EMAC_INTSTS[23]) is set, and both TDUIEN and TXIEN (EMAC_INTEN[16]) are enabled, the + * | | |EMAC generates the TX interrupt to CPU + * | | |If TDUIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the + * | | |TDUIF (EMAC_INTSTS[23]) is set. + * | | |0 = TDUIF (EMAC_INTSTS[23]) trigger TX interrupt Disabled. + * | | |1 = TDUIF (EMAC_INTSTS[23]) trigger TX interrupt Enabled. + * |[24] |TXBEIEN |Transmit Bus Error Interrupt Enable Bit + * | | |The TXBEIEN controls the TXBEIF (EMAC_INTSTS[24]) interrupt generation + * | | |If TXBEIF (EMAC_INTSTS[24]) is set, and both TXBEIEN and TXIEN (EMAC_INTEN[16]) are enabled, the + * | | |EMAC generates the TX interrupt to CPU + * | | |If TXBEIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the + * | | |TXBEIF (EMAC_INTSTS[24]) is set. + * | | |0 = TXBEIF (EMAC_INTSTS[24]) trigger TX interrupt Disabled. + * | | |1 = TXBEIF (EMAC_INTSTS[24]) trigger TX interrupt Enabled. + * |[28] |TSALMIEN |Time Stamp Alarm Interrupt Enable Bit + * | | |The TSALMIEN controls the TSALMIF (EMAC_INTSTS[28]) interrupt generation + * | | |If TSALMIF (EMAC_INTSTS[28]) is set, and both TSALMIEN and TXIEN (EMAC_INTEN[16]) enabled, the + * | | |EMAC generates the TX interrupt to CPU + * | | |If TSALMIEN or TXIEN (EMAC_INTEN[16]) disabled, no TX interrupt generated to CPU even the + * | | |TXTSALMIF (EMAC_INTEN[28]) is set. + * | | |0 = TXTSALMIF (EMAC_INTSTS[28]) trigger TX interrupt Disabled. + * | | |1 = TXTSALMIF (EMAC_INTSTS[28]) trigger TX interrupt Enabled. + * @var EMAC_T::INTSTS + * Offset: 0xB0 MAC Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXIF |Receive Interrupt + * | | |The RXIF indicates the RX interrupt status. + * | | |If RXIF high and its corresponding enable bit, RXIEN (EMAC_INTEN[0]), is also high indicates + * | | |the EMAC generates RX interrupt to CPU + * | | |If RXIF is high but RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated. + * | | |The RXIF is logic OR result of bit logic AND result of EMAC_INTSTS[15:1] and EMAC_INTEN[15:1] + * | | |In other words, if any bit of EMAC_INTSTS[15:1] is high and its corresponding enable bit in + * | | |EMAC_INTEN[15:1] is also enabled, the RXIF will be high. + * | | |Because the RXIF is a logic OR result, clears EMAC_INTSTS[15:1] makes RXIF be cleared, too. + * | | |0 = No status bit in EMAC_INTSTS[15:1] is set or no enable bit in EMAC_INTEN[15:1] is enabled. + * | | |1 = At least one status in EMAC_INTSTS[15:1] is set and its corresponding enable bit in + * | | |EMAC_INTEN[15:1] is enabled, too. + * |[1] |CRCEIF |CRC Error Interrupt + * | | |The CRCEIF high indicates the incoming packet incurred the CRC error and the packet is dropped + * | | |If the AEP (EMAC_CTL[4]) is set, the CRC error packet will be regarded as a good packet and + * | | |CRCEIF will not be set. + * | | |If the CRCEIF is high and CRCEIEN (EMAC_INTEN[1]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the CRCEIF status. + * | | |0 = The frame does not incur CRC error. + * | | |1 = The frame incurred CRC error. + * |[2] |RXOVIF |Receive FIFO Overflow Interrupt + * | | |The RXOVIF high indicates the RXFIFO overflow occurred during packet reception + * | | |While the RXFIFO overflow occurred, the EMAC drops the current receiving packer + * | | |If the RXFIFO overflow occurred often, it is recommended that modify RXFIFO threshold control, + * | | |the RXFIFOTH of FFTCR register, to higher level. + * | | |If the RXOVIF is high and RXOVIEN (EMAC_INTEN[2]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the RXOVIF status. + * | | |0 = No RXFIFO overflow occurred during packet reception. + * | | |1 = RXFIFO overflow occurred during packet reception. + * |[3] |LPIF |Long Packet Interrupt Flag + * | | |The LPIF high indicates the length of the incoming packet is greater than 1518 bytes and the + * | | |incoming packet is dropped + * | | |If the ALP (EMAC_CTL[1]) is set, the long packet will be regarded as a good packet and LPIF will not be set. + * | | |If the LPIF is high and LPIEN (EMAC_INTEN[3]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the LPIF status. + * | | |0 = The incoming frame is not a long frame or S/W wants to receive a long frame. + * | | |1 = The incoming frame is a long frame and dropped. + * |[4] |RXGDIF |Receive Good Interrupt + * | | |The RXGDIF high indicates the frame reception has completed. + * | | |If the RXGDIF is high and RXGDIEN (EAMC_MIEN[4]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the RXGDIF status. + * | | |0 = The frame reception has not complete yet. + * | | |1 = The frame reception has completed. + * |[5] |ALIEIF |Alignment Error Interrupt + * | | |The ALIEIF high indicates the length of the incoming frame is not a multiple of byte + * | | |If the ALIEIF is high and ALIEIEN (EMAC_INTEN[5]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the ALIEIF status. + * | | |0 = The frame length is a multiple of byte. + * | | |1 = The frame length is not a multiple of byte. + * |[6] |RPIF |Runt Packet Interrupt + * | | |The RPIF high indicates the length of the incoming packet is less than 64 bytes and the packet is dropped + * | | |If the ARP (EMAC_CTL[2]) is set, the short packet is regarded as a good packet and RPIF will not be set. + * | | |If the RPIF is high and RPIEN (EMAC_INTEN[6]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the RPIF status. + * | | |0 = The incoming frame is not a short frame or S/W wants to receive a short frame. + * | | |1 = The incoming frame is a short frame and dropped. + * |[7] |MPCOVIF |Missed Packet Counter Overrun Interrupt Flag + * | | |The MPCOVIF high indicates the MPCNT, Missed Packet Count, has overflow + * | | |If the MPCOVIF is high and MPCOVIEN (EMAC_INTEN[7]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the MPCOVIF status. + * | | |0 = The MPCNT has not rolled over yet. + * | | |1 = The MPCNT has rolled over yet. + * |[8] |MFLEIF |Maximum Frame Length Exceed Interrupt Flag + * | | |The MFLEIF high indicates the length of the incoming packet has exceeded the length limitation + * | | |configured in DMARFC register and the incoming packet is dropped + * | | |If the MFLEIF is high and MFLEIEN (EMAC_INTEN[8]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the MFLEIF status. + * | | |0 = The length of the incoming packet does not exceed the length limitation configured in DMARFC. + * | | |1 = The length of the incoming packet has exceeded the length limitation configured in DMARFC. + * |[9] |DENIF |DMA Early Notification Interrupt + * | | |The DENIF high indicates the EMAC has received the LENGTH field of the incoming packet. + * | | |If the DENIF is high and DENIENI (EMAC_INTEN[9]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the DENIF status. + * | | |0 = The LENGTH field of incoming packet has not received yet. + * | | |1 = The LENGTH field of incoming packet has received. + * |[10] |RDUIF |Receive Descriptor Unavailable Interrupt + * | | |The RDUIF high indicates that there is no available RX descriptor for packet reception and + * | | |RXDMA will stay at Halt state + * | | |Once, the RXDMA enters the Halt state, S/W must issues a write command to RSDR register to + * | | |make RXDMA leave Halt state while new RX descriptor is available. + * | | |If the RDUIF is high and RDUIEN (EMAC_INTEN[10]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the RDUIF status. + * | | |0 = RX descriptor is available. + * | | |1 = RX descriptor is unavailable. + * |[11] |RXBEIF |Receive Bus Error Interrupt + * | | |The RXBEIF high indicates the memory controller replies ERROR response while EMAC access + * | | |system memory through RXDMA during packet reception process + * | | |Reset EMAC is recommended while RXBEIF status is high. + * | | |If the RXBEIF is high and RXBEIEN (EMAC_INTEN[11]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the RXBEIF status. + * | | |0 = No ERROR response is received. + * | | |1 = ERROR response is received. + * |[14] |CFRIF |Control Frame Receive Interrupt + * | | |The CFRIF high indicates EMAC receives a flow control frame + * | | |The CFRIF only available while EMAC is operating on full duplex mode. + * | | |If the CFRIF is high and CFRIEN (EMAC_INTEN[14]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the CFRIF status. + * | | |0 = The EMAC does not receive the flow control frame. + * | | |1 = The EMAC receives a flow control frame. + * |[15] |WOLIF |Wake on LAN Interrupt Flag + * | | |The WOLIF high indicates EMAC receives a Magic Packet + * | | |The CFRIF only available while system is in power down mode and WOLEN is set high. + * | | |If the WOLIF is high and WOLIEN (EMAC_INTEN[15]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the WOLIF status. + * | | |0 = The EMAC does not receive the Magic Packet. + * | | |1 = The EMAC receives a Magic Packet. + * |[16] |TXIF |Transmit Interrupt + * | | |The TXIF indicates the TX interrupt status. + * | | |If TXIF high and its corresponding enable bit, TXIEN (EMAC_INTEN[16]), is also high indicates + * | | |the EMAC generates TX interrupt to CPU + * | | |If TXIF is high but TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated. + * | | |The TXIF is logic OR result of bit logic AND result of EMAC_INTSTS[28:17] and EMAC_INTEN[28:17] + * | | |In other words, if any bit of EMAC_INTSTS[28:17] is high and its corresponding enable bit + * | | |in EMAC_INTEN[28:17] is also enabled, the TXIF will be high + * | | |Because the TXIF is a logic OR result, clears EMAC_INTSTS[28:17] makes TXIF be cleared, too. + * | | |0 = No status bit in EMAC_INTSTS[28:17] is set or no enable bit in EMAC_INTEN[28:17] is enabled. + * | | |1 = At least one status in EMAC_INTSTS[28:17] is set and its corresponding enable bit + * | | |in EMAC_INTEN[28:17] is enabled, too. + * |[17] |TXUDIF |Transmit FIFO Underflow Interrupt + * | | |The TXUDIF high indicates the TXFIFO underflow occurred during packet transmission + * | | |While the TXFIFO underflow occurred, the EMAC will retransmit the packet automatically + * | | |without S/W intervention + * | | |If the TXFIFO underflow occurred often, it is recommended that modify TXFIFO threshold control, + * | | |the TXFIFOTH of FFTCR register, to higher level. + * | | |If the TXUDIF is high and TXUDIEN (EMAC_INTEN[17]) is enabled, the TXIF will be high + * | | |Write 1 to this bit clears the TXUDIF status. + * | | |0 = No TXFIFO underflow occurred during packet transmission. + * | | |1 = TXFIFO underflow occurred during packet transmission. + * |[18] |TXCPIF |Transmit Completion Interrupt + * | | |The TXCPIF indicates the packet transmission has completed correctly. + * | | |If the TXCPIF is high and TXCPIEN (EMAC_INTEN[18]) is enabled, the TXIF will be high + * | | |Write 1 to this bit clears the TXCPIF status. + * | | |0 = The packet transmission not completed. + * | | |1 = The packet transmission has completed. + * |[19] |EXDEFIF |Defer Exceed Interrupt + * | | |The EXDEFIF high indicates the frame waiting for transmission has deferred over 0.32768ms + * | | |on 100Mbps mode, or 3.2768ms on 10Mbps mode. + * | | |The deferral exceed check will only be done while bit NODEF of MCMDR is disabled, and EMAC + * | | |is operating on half-duplex mode. + * | | |If the EXDEFIF is high and EXDEFIEN (EMAC_INTEN[19]) is enabled, the TXIF will be high + * | | |Write 1 to this bit clears the EXDEFIF status. + * | | |0 = Frame waiting for transmission has not deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps). + * | | |1 = Frame waiting for transmission has deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps). + * |[20] |NCSIF |No Carrier Sense Interrupt + * | | |The NCSIF high indicates the MII I/F signal CRS does not active at the start of or during + * | | |the packet transmission + * | | |The NCSIF is only available while EMAC is operating on half-duplex mode + * | | |If the NCSIF is high and NCSIEN (EMAC_INTEN[20]) is enabled, the TXIF will be high. + * | | |Write 1 to this bit clears the NCSIF status. + * | | |0 = CRS signal actives correctly. + * | | |1 = CRS signal does not active at the start of or during the packet transmission. + * |[21] |TXABTIF |Transmit Abort Interrupt + * | | |The TXABTIF high indicates the packet incurred 16 consecutive collisions during transmission, + * | | |and then the transmission process for this packet is aborted + * | | |The transmission abort is only available while EMAC is operating on half-duplex mode. + * | | |If the TXABTIF is high and TXABTIEN (EMAC_INTEN[21]) is enabled, the TXIF will be high + * | | |Write 1 to this bit clears the TXABTIF status. + * | | |0 = Packet does not incur 16 consecutive collisions during transmission. + * | | |1 = Packet incurred 16 consecutive collisions during transmission. + * |[22] |LCIF |Late Collision Interrupt + * | | |The LCIF high indicates the collision occurred in the outside of 64 bytes collision window + * | | |This means after the 64 bytes of a frame has been transmitted out to the network, the collision + * | | |still occurred. + * | | |The late collision check will only be done while EMAC is operating on half-duplex mode + * | | |If the LCIF is high and LCIEN (EMAC_INTEN[22]) is enabled, the TXIF will be high. + * | | |Write 1 to this bit clears the LCIF status. + * | | |0 = No collision occurred in the outside of 64 bytes collision window. + * | | |1 = Collision occurred in the outside of 64 bytes collision window. + * |[23] |TDUIF |Transmit Descriptor Unavailable Interrupt + * | | |The TDUIF high indicates that there is no available TX descriptor for packet transmission and + * | | |TXDMA will stay at Halt state. + * | | |Once, the TXDMA enters the Halt state, S/W must issues a write command to TSDR register to make + * | | |TXDMA leave Halt state while new TX descriptor is available. + * | | |If the TDUIF is high and TDUIEN (EMAC_INTEN[23]) is enabled, the TXIF will be high. + * | | |Write 1 to this bit clears the TDUIF status. + * | | |0 = TX descriptor is available. + * | | |1 = TX descriptor is unavailable. + * |[24] |TXBEIF |Transmit Bus Error Interrupt + * | | |The TXBEIF high indicates the memory controller replies ERROR response while EMAC access system + * | | |memory through TXDMA during packet transmission process + * | | |Reset EMAC is recommended while TXBEIF status is high. + * | | |If the TXBEIF is high and TXBEIEN (EMAC_INTEN[24]) is enabled, the TXIF will be high. + * | | |Write 1 to this bit clears the TXBEIF status. + * | | |0 = No ERROR response is received. + * | | |1 = ERROR response is received. + * |[28] |TSALMIF |Time Stamp Alarm Interrupt + * | | |The TSALMIF high indicates the EMAC_TSSEC register value equals to EMAC_ALMSEC register and + * | | |EMAC_TSSUBSEC register value equals to register EMAC_ALMSUBLSR. + * | | |If TSALMIF is high and TSALMIEN (EMAC_INTEN[28]) enabled, the TXIF will be high. + * | | |Write 1 to this bit clears the TSALMIF status. + * | | |0 = EMAC_TSSEC did not equal EMAC_ALMSEC or EMAC_TSSUBSEC did not equal EMAC_ALMSUBSEC. + * | | |1 = EMAC_TSSEC equals EMAC_ALMSEC and EMAC_TSSUBSEC equals EMAC_ALMSUBSEC. + * @var EMAC_T::GENSTS + * Offset: 0xB4 MAC General Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CFR |Control Frame Received + * | | |The CFRIF high indicates EMAC receives a flow control frame + * | | |The CFRIF only available while EMAC is operating on full duplex mode. + * | | |0 = The EMAC does not receive the flow control frame. + * | | |1 = The EMAC receives a flow control frame. + * |[1] |RXHALT |Receive Halted + * | | |The RXHALT high indicates the next normal packet reception process will be halted because + * | | |the bit RXON of MCMDR is disabled be S/W. + * | | |0 = Next normal packet reception process will go on. + * | | |1 = Next normal packet reception process will be halted. + * |[2] |RXFFULL |RXFIFO Full + * | | |The RXFFULL indicates the RXFIFO is full due to four 64-byte packets are kept in RXFIFO + * | | |and the following incoming packet will be dropped. + * | | |0 = The RXFIFO is not full. + * | | |1 = The RXFIFO is full and the following incoming packet will be dropped. + * |[7:4] |COLCNT |Collision Count + * | | |The COLCNT indicates that how many collisions occurred consecutively during a packet transmission + * | | |If the packet incurred 16 consecutive collisions during transmission, the COLCNT will be + * | | |0 and bit TXABTIF will be set to 1. + * |[8] |DEF |Deferred Transmission + * | | |The DEF high indicates the packet transmission has deferred once + * | | |The DEF is only available while EMAC is operating on half-duplex mode. + * | | |0 = Packet transmission does not defer. + * | | |1 = Packet transmission has deferred once. + * |[9] |TXPAUSED |Transmission Paused + * | | |The TXPAUSED high indicates the next normal packet transmission process will be paused temporally + * | | |because EMAC received a PAUSE control frame. + * | | |0 = Next normal packet transmission process will go on. + * | | |1 = Next normal packet transmission process will be paused. + * |[10] |SQE |Signal Quality Error + * | | |The SQE high indicates the SQE error found at end of packet transmission on 10Mbps half-duplex mode + * | | |The SQE error check will only be done while both bit SQECHKEN (EMAC_CTL[17]) is enabled and EMAC + * | | |is operating on 10Mbps half-duplex mode. + * | | |0 = No SQE error found at end of packet transmission. + * | | |1 = SQE error found at end of packet transmission. + * |[11] |TXHALT |Transmission Halted + * | | |The TXHALT high indicates the next normal packet transmission process will be halted because + * | | |the bit TXON (EMAC_CTL[8]) is disabled be S/W. + * | | |0 = Next normal packet transmission process will go on. + * | | |1 = Next normal packet transmission process will be halted. + * |[12] |RPSTS |Remote Pause Status + * | | |The RPSTS indicates that remote pause counter down counting actives. + * | | |After Ethernet MAC controller sent PAUSE frame out successfully, it starts the remote pause + * | | |counter down counting + * | | |When this bit high, it's predictable that remote Ethernet MAC controller wouldn't start the packet + * | | |transmission until the down counting done. + * | | |0 = Remote pause counter down counting done. + * | | |1 = Remote pause counter down counting actives. + * @var EMAC_T::MPCNT + * Offset: 0xB8 Missed Packet Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |MPCNT |Miss Packet Count + * | | |The MPCNT indicates the number of packets that were dropped due to various types of receive errors + * | | |The following type of receiving error makes missed packet counter increase: + * | | |1. Incoming packet is incurred RXFIFO overflow. + * | | |2. Incoming packet is dropped due to RXON is disabled. + * | | |3. Incoming packet is incurred CRC error. + * @var EMAC_T::RPCNT + * Offset: 0xBC MAC Receive Pause Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RPCNT |MAC Receive Pause Count + * | | |The RPCNT keeps the OPERAND field of the PAUSE control frame + * | | |It indicates how many slot time (512 bit time) the TX of EMAC will be paused. + * @var EMAC_T::FRSTS + * Offset: 0xC8 DMA Receive Frame Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RXFLT |Receive Frame LENGTH + * | | |The RXFLT keeps the LENGTH field of each incoming Ethernet packet + * | | |If the bit DENIEN (EMAC_INTEN[9]) is enabled and the LENGTH field of incoming packet has + * | | |received, the bit DENIF (EMAC_INTSTS[9]) will be set and trigger interrupt. + * | | |And, the content of LENGTH field will be stored in RXFLT. + * @var EMAC_T::CTXDSA + * Offset: 0xCC Current Transmit Descriptor Start Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CTXDSA |Current Transmit Descriptor Start Address + * | | |The CTXDSA keeps the start address of TX descriptor that is used by TXDMA currently + * | | |The CTXDSA is read only and write to this register has no effect. + * @var EMAC_T::CTXBSA + * Offset: 0xD0 Current Transmit Buffer Start Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CTXBSA |Current Transmit Buffer Start Address + * | | |The CTXDSA keeps the start address of TX frame buffer that is used by TXDMA currently + * | | |The CTXBSA is read only and write to this register has no effect. + * @var EMAC_T::CRXDSA + * Offset: 0xD4 Current Receive Descriptor Start Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CRXDSA |Current Receive Descriptor Start Address + * | | |The CRXDSA keeps the start address of RX descriptor that is used by RXDMA currently + * | | |The CRXDSA is read only and write to this register has no effect. + * @var EMAC_T::CRXBSA + * Offset: 0xD8 Current Receive Buffer Start Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CRXBSA |Current Receive Buffer Start Address + * | | |The CRXBSA keeps the start address of RX frame buffer that is used by RXDMA currently + * | | |The CRXBSA is read only and write to this register has no effect. + * @var EMAC_T::TSCTL + * Offset: 0x100 Time Stamp Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TSEN |Time Stamp Function Enable Bit + * | | |This bit controls if the IEEE 1588 PTP time stamp function is enabled or not. + * | | |Set this bit high to enable IEEE 1588 PTP time stamp function while set this bit low + * | | |to disable IEEE 1588 PTP time stamp function. + * | | |0 = I EEE 1588 PTP time stamp function Disabled. + * | | |1 = IEEE 1588 PTP time stamp function Enabled. + * |[1] |TSIEN |Time Stamp Counter Initialization Enable Bit + * | | |Set this bit high enables Ethernet MAC controller to load value of register EMAC_UPDSEC + * | | |and EMAC_UPDSUBSEC to PTP time stamp counter. + * | | |After the load operation finished, Ethernet MAC controller clear this bit to low automatically. + * | | |0 = Time stamp counter initialization done. + * | | |1 = Time stamp counter initialization Enabled. + * |[2] |TSMODE |Time Stamp Fine Update Enable Bit + * | | |This bit chooses the time stamp counter update mode. + * | | |0 = Time stamp counter is in coarse update mode. + * | | |1 = Time stamp counter is in fine update mode. + * |[3] |TSUPDATE |Time Stamp Counter Time Update Enable Bit + * | | |Set this bit high enables Ethernet MAC controller to add value of register EMAC_UPDSEC and + * | | |EMAC_UPDSUBSEC to PTP time stamp counter. + * | | |After the add operation finished, Ethernet MAC controller clear this bit to low automatically. + * | | |0 = No action. + * | | |1 = EMAC_UPDSEC updated to EMAC_TSSEC and EMAC_UPDSUBSEC updated to EMAC_TSSUBSEC. + * |[5] |TSALMEN |Time Stamp Alarm Enable Bit + * | | |Set this bit high enable Ethernet MAC controller to set TSALMIF (EMAC_INTSTS[28]) high when + * | | |EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC. + * | | |0 = Alarm disabled when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC. + * | | |1 = Alarm enabled when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC. + * @var EMAC_T::TSSEC + * Offset: 0x110 Time Stamp Counter Second Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEC |Time Stamp Counter Second + * | | |This register reflects the bit [63:32] value of 64-bit reference timing counter + * | | |This 32-bit value is used as the second part of time stamp when TSEN (EMAC_TSCTL[0]) is high. + * @var EMAC_T::TSSUBSEC + * Offset: 0x114 Time Stamp Counter Sub Second Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SUBSEC |Time Stamp Counter Sub-second + * | | |This register reflects the bit [31:0] value of 64-bit reference timing counter + * | | |This 32-bit value is used as the sub-second part of time stamp when TSEN (EMAC_TSCTL[0]) is high. + * @var EMAC_T::TSINC + * Offset: 0x118 Time Stamp Increment Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |CNTINC |Time Stamp Counter Increment + * | | |Time stamp counter increment value. + * | | |If TSEN (EMAC_TSCTL[0]) is high, EMAC adds EMAC_TSSUBSEC with this 8-bit value every + * | | |time when it wants to increase the EMAC_TSSUBSEC value. + * @var EMAC_T::TSADDEND + * Offset: 0x11C Time Stamp Addend Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ADDEND |Time Stamp Counter Addend + * | | |This register keeps a 32-bit value for accumulator to enable increment of EMAC_TSSUBSEC. + * | | |If TSEN (EMAC_TSCTL[0]) and TSMODE (EMAC_TSCTL[2]) are both high, EMAC increases accumulator + * | | |with this 32-bit value in each HCLK + * | | |Once the accumulator is overflow, it generates a enable to increase EMAC_TSSUBSEC with an 8-bit + * | | |value kept in register EMAC_TSINC. + * @var EMAC_T::UPDSEC + * Offset: 0x120 Time Stamp Update Second Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEC |Time Stamp Counter Second Update + * | | |When TSIEN (EMAC_TSCTL[1]) is high + * | | |EMAC loads this 32-bit value to EMAC_TSSEC directly + * | | |When TSUPDATE (EMAC_TSCTL[3]) is high, EMAC increases EMAC_TSSEC with this 32-bit value. + * @var EMAC_T::UPDSUBSEC + * Offset: 0x124 Time Stamp Update Sub Second Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SUBSEC |Time Stamp Counter Sub-second Update + * | | |When TSIEN (EMAC_TSCTL[1]) is high + * | | |EMAC loads this 32-bit value to EMAC_TSSUBSEC directly + * | | |When TSUPDATE (EMAC_TSCTL[3]) is high, EMAC increases EMAC_TSSUBSEC with this 32-bit value. + * @var EMAC_T::ALMSEC + * Offset: 0x128 Time Stamp Alarm Second Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEC |Time Stamp Counter Second Alarm + * | | |Time stamp counter second part alarm value. + * | | |This value is only useful when ALMEN (EMAC_TSCTL[5]) high + * | | |If ALMEN (EMAC_TSCTL[5]) is high, EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to + * | | |EMAC_ALMSUBSEC, Ethernet MAC controller set TSALMIF (EMAC_INTSTS[28]) high. + * @var EMAC_T::ALMSUBSEC + * Offset: 0x12C Time Stamp Alarm Sub Second Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SUBSEC |Time Stamp Counter Sub-second Alarm + * | | |Time stamp counter sub-second part alarm value. + * | | |This value is only useful when ALMEN (EMAC_TSCTL[5]) high + * | | |If ALMEN (EMAC_TSCTL[5]) is high, EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to + * | | |EMAC_ALMSUBSEC, Ethernet MAC controller set TSALMIF (EMAC_INTSTS[28]) high. + */ + __IO uint32_t CAMCTL; /*!< [0x0000] CAM Comparison Control Register */ + __IO uint32_t CAMEN; /*!< [0x0004] CAM Enable Register */ + __IO uint32_t CAM0M; /*!< [0x0008] CAM0 Most Significant Word Register */ + __IO uint32_t CAM0L; /*!< [0x000c] CAM0 Least Significant Word Register */ + __IO uint32_t CAM1M; /*!< [0x0010] CAM1 Most Significant Word Register */ + __IO uint32_t CAM1L; /*!< [0x0014] CAM1 Least Significant Word Register */ + __IO uint32_t CAM2M; /*!< [0x0018] CAM2 Most Significant Word Register */ + __IO uint32_t CAM2L; /*!< [0x001c] CAM2 Least Significant Word Register */ + __IO uint32_t CAM3M; /*!< [0x0020] CAM3 Most Significant Word Register */ + __IO uint32_t CAM3L; /*!< [0x0024] CAM3 Least Significant Word Register */ + __IO uint32_t CAM4M; /*!< [0x0028] CAM4 Most Significant Word Register */ + __IO uint32_t CAM4L; /*!< [0x002c] CAM4 Least Significant Word Register */ + __IO uint32_t CAM5M; /*!< [0x0030] CAM5 Most Significant Word Register */ + __IO uint32_t CAM5L; /*!< [0x0034] CAM5 Least Significant Word Register */ + __IO uint32_t CAM6M; /*!< [0x0038] CAM6 Most Significant Word Register */ + __IO uint32_t CAM6L; /*!< [0x003c] CAM6 Least Significant Word Register */ + __IO uint32_t CAM7M; /*!< [0x0040] CAM7 Most Significant Word Register */ + __IO uint32_t CAM7L; /*!< [0x0044] CAM7 Least Significant Word Register */ + __IO uint32_t CAM8M; /*!< [0x0048] CAM8 Most Significant Word Register */ + __IO uint32_t CAM8L; /*!< [0x004c] CAM8 Least Significant Word Register */ + __IO uint32_t CAM9M; /*!< [0x0050] CAM9 Most Significant Word Register */ + __IO uint32_t CAM9L; /*!< [0x0054] CAM9 Least Significant Word Register */ + __IO uint32_t CAM10M; /*!< [0x0058] CAM10 Most Significant Word Register */ + __IO uint32_t CAM10L; /*!< [0x005c] CAM10 Least Significant Word Register */ + __IO uint32_t CAM11M; /*!< [0x0060] CAM11 Most Significant Word Register */ + __IO uint32_t CAM11L; /*!< [0x0064] CAM11 Least Significant Word Register */ + __IO uint32_t CAM12M; /*!< [0x0068] CAM12 Most Significant Word Register */ + __IO uint32_t CAM12L; /*!< [0x006c] CAM12 Least Significant Word Register */ + __IO uint32_t CAM13M; /*!< [0x0070] CAM13 Most Significant Word Register */ + __IO uint32_t CAM13L; /*!< [0x0074] CAM13 Least Significant Word Register */ + __IO uint32_t CAM14M; /*!< [0x0078] CAM14 Most Significant Word Register */ + __IO uint32_t CAM14L; /*!< [0x007c] CAM14 Least Significant Word Register */ + __IO uint32_t CAM15MSB; /*!< [0x0080] CAM15 Most Significant Word Register */ + __IO uint32_t CAM15LSB; /*!< [0x0084] CAM15 Least Significant Word Register */ + __IO uint32_t TXDSA; /*!< [0x0088] Transmit Descriptor Link List Start Address Register */ + __IO uint32_t RXDSA; /*!< [0x008c] Receive Descriptor Link List Start Address Register */ + __IO uint32_t CTL; /*!< [0x0090] MAC Control Register */ + __IO uint32_t MIIMDAT; /*!< [0x0094] MII Management Data Register */ + __IO uint32_t MIIMCTL; /*!< [0x0098] MII Management Control and Address Register */ + __IO uint32_t FIFOCTL; /*!< [0x009c] FIFO Threshold Control Register */ + __O uint32_t TXST; /*!< [0x00a0] Transmit Start Demand Register */ + __O uint32_t RXST; /*!< [0x00a4] Receive Start Demand Register */ + __IO uint32_t MRFL; /*!< [0x00a8] Maximum Receive Frame Control Register */ + __IO uint32_t INTEN; /*!< [0x00ac] MAC Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x00b0] MAC Interrupt Status Register */ + __IO uint32_t GENSTS; /*!< [0x00b4] MAC General Status Register */ + __IO uint32_t MPCNT; /*!< [0x00b8] Missed Packet Count Register */ + __I uint32_t RPCNT; /*!< [0x00bc] MAC Receive Pause Count Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE0[2]; + /** @endcond */ + __IO uint32_t FRSTS; /*!< [0x00c8] DMA Receive Frame Status Register */ + __I uint32_t CTXDSA; /*!< [0x00cc] Current Transmit Descriptor Start Address Register */ + __I uint32_t CTXBSA; /*!< [0x00d0] Current Transmit Buffer Start Address Register */ + __I uint32_t CRXDSA; /*!< [0x00d4] Current Receive Descriptor Start Address Register */ + __I uint32_t CRXBSA; /*!< [0x00d8] Current Receive Buffer Start Address Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE1[9]; + /** @endcond */ + __IO uint32_t TSCTL; /*!< [0x0100] Time Stamp Control Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE2[3]; + /** @endcond */ + __I uint32_t TSSEC; /*!< [0x0110] Time Stamp Counter Second Register */ + __I uint32_t TSSUBSEC; /*!< [0x0114] Time Stamp Counter Sub Second Register */ + __IO uint32_t TSINC; /*!< [0x0118] Time Stamp Increment Register */ + __IO uint32_t TSADDEND; /*!< [0x011c] Time Stamp Addend Register */ + __IO uint32_t UPDSEC; /*!< [0x0120] Time Stamp Update Second Register */ + __IO uint32_t UPDSUBSEC; /*!< [0x0124] Time Stamp Update Sub Second Register */ + __IO uint32_t ALMSEC; /*!< [0x0128] Time Stamp Alarm Second Register */ + __IO uint32_t ALMSUBSEC; /*!< [0x012c] Time Stamp Alarm Sub Second Register */ + +} EMAC_T; + +/** + @addtogroup EMAC_CONST EMAC Bit Field Definition + Constant Definitions for EMAC Controller +@{ */ + +#define EMAC_CAMCTL_AUP_Pos (0) /*!< EMAC_T::CAMCTL: AUP Position */ +#define EMAC_CAMCTL_AUP_Msk (0x1ul << EMAC_CAMCTL_AUP_Pos) /*!< EMAC_T::CAMCTL: AUP Mask */ + +#define EMAC_CAMCTL_AMP_Pos (1) /*!< EMAC_T::CAMCTL: AMP Position */ +#define EMAC_CAMCTL_AMP_Msk (0x1ul << EMAC_CAMCTL_AMP_Pos) /*!< EMAC_T::CAMCTL: AMP Mask */ + +#define EMAC_CAMCTL_ABP_Pos (2) /*!< EMAC_T::CAMCTL: ABP Position */ +#define EMAC_CAMCTL_ABP_Msk (0x1ul << EMAC_CAMCTL_ABP_Pos) /*!< EMAC_T::CAMCTL: ABP Mask */ + +#define EMAC_CAMCTL_COMPEN_Pos (3) /*!< EMAC_T::CAMCTL: COMPEN Position */ +#define EMAC_CAMCTL_COMPEN_Msk (0x1ul << EMAC_CAMCTL_COMPEN_Pos) /*!< EMAC_T::CAMCTL: COMPEN Mask */ + +#define EMAC_CAMCTL_CMPEN_Pos (4) /*!< EMAC_T::CAMCTL: CMPEN Position */ +#define EMAC_CAMCTL_CMPEN_Msk (0x1ul << EMAC_CAMCTL_CMPEN_Pos) /*!< EMAC_T::CAMCTL: CMPEN Mask */ + +#define EMAC_CAMEN_CAMxEN_Pos (0) /*!< EMAC_T::CAMEN: CAMxEN Position */ +#define EMAC_CAMEN_CAMxEN_Msk (0x1ul << EMAC_CAMEN_CAMxEN_Pos) /*!< EMAC_T::CAMEN: CAMxEN Mask */ + +#define EMAC_CAM0M_MACADDR2_Pos (0) /*!< EMAC_T::CAM0M: MACADDR2 Position */ +#define EMAC_CAM0M_MACADDR2_Msk (0xfful << EMAC_CAM0M_MACADDR2_Pos) /*!< EMAC_T::CAM0M: MACADDR2 Mask */ + +#define EMAC_CAM0M_MACADDR3_Pos (8) /*!< EMAC_T::CAM0M: MACADDR3 Position */ +#define EMAC_CAM0M_MACADDR3_Msk (0xfful << EMAC_CAM0M_MACADDR3_Pos) /*!< EMAC_T::CAM0M: MACADDR3 Mask */ + +#define EMAC_CAM0M_MACADDR4_Pos (16) /*!< EMAC_T::CAM0M: MACADDR4 Position */ +#define EMAC_CAM0M_MACADDR4_Msk (0xfful << EMAC_CAM0M_MACADDR4_Pos) /*!< EMAC_T::CAM0M: MACADDR4 Mask */ + +#define EMAC_CAM0M_MACADDR5_Pos (24) /*!< EMAC_T::CAM0M: MACADDR5 Position */ +#define EMAC_CAM0M_MACADDR5_Msk (0xfful << EMAC_CAM0M_MACADDR5_Pos) /*!< EMAC_T::CAM0M: MACADDR5 Mask */ + +#define EMAC_CAM0L_MACADDR0_Pos (16) /*!< EMAC_T::CAM0L: MACADDR0 Position */ +#define EMAC_CAM0L_MACADDR0_Msk (0xfful << EMAC_CAM0L_MACADDR0_Pos) /*!< EMAC_T::CAM0L: MACADDR0 Mask */ + +#define EMAC_CAM0L_MACADDR1_Pos (24) /*!< EMAC_T::CAM0L: MACADDR1 Position */ +#define EMAC_CAM0L_MACADDR1_Msk (0xfful << EMAC_CAM0L_MACADDR1_Pos) /*!< EMAC_T::CAM0L: MACADDR1 Mask */ + +#define EMAC_CAM1M_MACADDR2_Pos (0) /*!< EMAC_T::CAM1M: MACADDR2 Position */ +#define EMAC_CAM1M_MACADDR2_Msk (0xfful << EMAC_CAM1M_MACADDR2_Pos) /*!< EMAC_T::CAM1M: MACADDR2 Mask */ + +#define EMAC_CAM1M_MACADDR3_Pos (8) /*!< EMAC_T::CAM1M: MACADDR3 Position */ +#define EMAC_CAM1M_MACADDR3_Msk (0xfful << EMAC_CAM1M_MACADDR3_Pos) /*!< EMAC_T::CAM1M: MACADDR3 Mask */ + +#define EMAC_CAM1M_MACADDR4_Pos (16) /*!< EMAC_T::CAM1M: MACADDR4 Position */ +#define EMAC_CAM1M_MACADDR4_Msk (0xfful << EMAC_CAM1M_MACADDR4_Pos) /*!< EMAC_T::CAM1M: MACADDR4 Mask */ + +#define EMAC_CAM1M_MACADDR5_Pos (24) /*!< EMAC_T::CAM1M: MACADDR5 Position */ +#define EMAC_CAM1M_MACADDR5_Msk (0xfful << EMAC_CAM1M_MACADDR5_Pos) /*!< EMAC_T::CAM1M: MACADDR5 Mask */ + +#define EMAC_CAM1L_MACADDR0_Pos (16) /*!< EMAC_T::CAM1L: MACADDR0 Position */ +#define EMAC_CAM1L_MACADDR0_Msk (0xfful << EMAC_CAM1L_MACADDR0_Pos) /*!< EMAC_T::CAM1L: MACADDR0 Mask */ + +#define EMAC_CAM1L_MACADDR1_Pos (24) /*!< EMAC_T::CAM1L: MACADDR1 Position */ +#define EMAC_CAM1L_MACADDR1_Msk (0xfful << EMAC_CAM1L_MACADDR1_Pos) /*!< EMAC_T::CAM1L: MACADDR1 Mask */ + +#define EMAC_CAM2M_MACADDR2_Pos (0) /*!< EMAC_T::CAM2M: MACADDR2 Position */ +#define EMAC_CAM2M_MACADDR2_Msk (0xfful << EMAC_CAM2M_MACADDR2_Pos) /*!< EMAC_T::CAM2M: MACADDR2 Mask */ + +#define EMAC_CAM2M_MACADDR3_Pos (8) /*!< EMAC_T::CAM2M: MACADDR3 Position */ +#define EMAC_CAM2M_MACADDR3_Msk (0xfful << EMAC_CAM2M_MACADDR3_Pos) /*!< EMAC_T::CAM2M: MACADDR3 Mask */ + +#define EMAC_CAM2M_MACADDR4_Pos (16) /*!< EMAC_T::CAM2M: MACADDR4 Position */ +#define EMAC_CAM2M_MACADDR4_Msk (0xfful << EMAC_CAM2M_MACADDR4_Pos) /*!< EMAC_T::CAM2M: MACADDR4 Mask */ + +#define EMAC_CAM2M_MACADDR5_Pos (24) /*!< EMAC_T::CAM2M: MACADDR5 Position */ +#define EMAC_CAM2M_MACADDR5_Msk (0xfful << EMAC_CAM2M_MACADDR5_Pos) /*!< EMAC_T::CAM2M: MACADDR5 Mask */ + +#define EMAC_CAM2L_MACADDR0_Pos (16) /*!< EMAC_T::CAM2L: MACADDR0 Position */ +#define EMAC_CAM2L_MACADDR0_Msk (0xfful << EMAC_CAM2L_MACADDR0_Pos) /*!< EMAC_T::CAM2L: MACADDR0 Mask */ + +#define EMAC_CAM2L_MACADDR1_Pos (24) /*!< EMAC_T::CAM2L: MACADDR1 Position */ +#define EMAC_CAM2L_MACADDR1_Msk (0xfful << EMAC_CAM2L_MACADDR1_Pos) /*!< EMAC_T::CAM2L: MACADDR1 Mask */ + +#define EMAC_CAM3M_MACADDR2_Pos (0) /*!< EMAC_T::CAM3M: MACADDR2 Position */ +#define EMAC_CAM3M_MACADDR2_Msk (0xfful << EMAC_CAM3M_MACADDR2_Pos) /*!< EMAC_T::CAM3M: MACADDR2 Mask */ + +#define EMAC_CAM3M_MACADDR3_Pos (8) /*!< EMAC_T::CAM3M: MACADDR3 Position */ +#define EMAC_CAM3M_MACADDR3_Msk (0xfful << EMAC_CAM3M_MACADDR3_Pos) /*!< EMAC_T::CAM3M: MACADDR3 Mask */ + +#define EMAC_CAM3M_MACADDR4_Pos (16) /*!< EMAC_T::CAM3M: MACADDR4 Position */ +#define EMAC_CAM3M_MACADDR4_Msk (0xfful << EMAC_CAM3M_MACADDR4_Pos) /*!< EMAC_T::CAM3M: MACADDR4 Mask */ + +#define EMAC_CAM3M_MACADDR5_Pos (24) /*!< EMAC_T::CAM3M: MACADDR5 Position */ +#define EMAC_CAM3M_MACADDR5_Msk (0xfful << EMAC_CAM3M_MACADDR5_Pos) /*!< EMAC_T::CAM3M: MACADDR5 Mask */ + +#define EMAC_CAM3L_MACADDR0_Pos (16) /*!< EMAC_T::CAM3L: MACADDR0 Position */ +#define EMAC_CAM3L_MACADDR0_Msk (0xfful << EMAC_CAM3L_MACADDR0_Pos) /*!< EMAC_T::CAM3L: MACADDR0 Mask */ + +#define EMAC_CAM3L_MACADDR1_Pos (24) /*!< EMAC_T::CAM3L: MACADDR1 Position */ +#define EMAC_CAM3L_MACADDR1_Msk (0xfful << EMAC_CAM3L_MACADDR1_Pos) /*!< EMAC_T::CAM3L: MACADDR1 Mask */ + +#define EMAC_CAM4M_MACADDR2_Pos (0) /*!< EMAC_T::CAM4M: MACADDR2 Position */ +#define EMAC_CAM4M_MACADDR2_Msk (0xfful << EMAC_CAM4M_MACADDR2_Pos) /*!< EMAC_T::CAM4M: MACADDR2 Mask */ + +#define EMAC_CAM4M_MACADDR3_Pos (8) /*!< EMAC_T::CAM4M: MACADDR3 Position */ +#define EMAC_CAM4M_MACADDR3_Msk (0xfful << EMAC_CAM4M_MACADDR3_Pos) /*!< EMAC_T::CAM4M: MACADDR3 Mask */ + +#define EMAC_CAM4M_MACADDR4_Pos (16) /*!< EMAC_T::CAM4M: MACADDR4 Position */ +#define EMAC_CAM4M_MACADDR4_Msk (0xfful << EMAC_CAM4M_MACADDR4_Pos) /*!< EMAC_T::CAM4M: MACADDR4 Mask */ + +#define EMAC_CAM4M_MACADDR5_Pos (24) /*!< EMAC_T::CAM4M: MACADDR5 Position */ +#define EMAC_CAM4M_MACADDR5_Msk (0xfful << EMAC_CAM4M_MACADDR5_Pos) /*!< EMAC_T::CAM4M: MACADDR5 Mask */ + +#define EMAC_CAM4L_MACADDR0_Pos (16) /*!< EMAC_T::CAM4L: MACADDR0 Position */ +#define EMAC_CAM4L_MACADDR0_Msk (0xfful << EMAC_CAM4L_MACADDR0_Pos) /*!< EMAC_T::CAM4L: MACADDR0 Mask */ + +#define EMAC_CAM4L_MACADDR1_Pos (24) /*!< EMAC_T::CAM4L: MACADDR1 Position */ +#define EMAC_CAM4L_MACADDR1_Msk (0xfful << EMAC_CAM4L_MACADDR1_Pos) /*!< EMAC_T::CAM4L: MACADDR1 Mask */ + +#define EMAC_CAM5M_MACADDR2_Pos (0) /*!< EMAC_T::CAM5M: MACADDR2 Position */ +#define EMAC_CAM5M_MACADDR2_Msk (0xfful << EMAC_CAM5M_MACADDR2_Pos) /*!< EMAC_T::CAM5M: MACADDR2 Mask */ + +#define EMAC_CAM5M_MACADDR3_Pos (8) /*!< EMAC_T::CAM5M: MACADDR3 Position */ +#define EMAC_CAM5M_MACADDR3_Msk (0xfful << EMAC_CAM5M_MACADDR3_Pos) /*!< EMAC_T::CAM5M: MACADDR3 Mask */ + +#define EMAC_CAM5M_MACADDR4_Pos (16) /*!< EMAC_T::CAM5M: MACADDR4 Position */ +#define EMAC_CAM5M_MACADDR4_Msk (0xfful << EMAC_CAM5M_MACADDR4_Pos) /*!< EMAC_T::CAM5M: MACADDR4 Mask */ + +#define EMAC_CAM5M_MACADDR5_Pos (24) /*!< EMAC_T::CAM5M: MACADDR5 Position */ +#define EMAC_CAM5M_MACADDR5_Msk (0xfful << EMAC_CAM5M_MACADDR5_Pos) /*!< EMAC_T::CAM5M: MACADDR5 Mask */ + +#define EMAC_CAM5L_MACADDR0_Pos (16) /*!< EMAC_T::CAM5L: MACADDR0 Position */ +#define EMAC_CAM5L_MACADDR0_Msk (0xfful << EMAC_CAM5L_MACADDR0_Pos) /*!< EMAC_T::CAM5L: MACADDR0 Mask */ + +#define EMAC_CAM5L_MACADDR1_Pos (24) /*!< EMAC_T::CAM5L: MACADDR1 Position */ +#define EMAC_CAM5L_MACADDR1_Msk (0xfful << EMAC_CAM5L_MACADDR1_Pos) /*!< EMAC_T::CAM5L: MACADDR1 Mask */ + +#define EMAC_CAM6M_MACADDR2_Pos (0) /*!< EMAC_T::CAM6M: MACADDR2 Position */ +#define EMAC_CAM6M_MACADDR2_Msk (0xfful << EMAC_CAM6M_MACADDR2_Pos) /*!< EMAC_T::CAM6M: MACADDR2 Mask */ + +#define EMAC_CAM6M_MACADDR3_Pos (8) /*!< EMAC_T::CAM6M: MACADDR3 Position */ +#define EMAC_CAM6M_MACADDR3_Msk (0xfful << EMAC_CAM6M_MACADDR3_Pos) /*!< EMAC_T::CAM6M: MACADDR3 Mask */ + +#define EMAC_CAM6M_MACADDR4_Pos (16) /*!< EMAC_T::CAM6M: MACADDR4 Position */ +#define EMAC_CAM6M_MACADDR4_Msk (0xfful << EMAC_CAM6M_MACADDR4_Pos) /*!< EMAC_T::CAM6M: MACADDR4 Mask */ + +#define EMAC_CAM6M_MACADDR5_Pos (24) /*!< EMAC_T::CAM6M: MACADDR5 Position */ +#define EMAC_CAM6M_MACADDR5_Msk (0xfful << EMAC_CAM6M_MACADDR5_Pos) /*!< EMAC_T::CAM6M: MACADDR5 Mask */ + +#define EMAC_CAM6L_MACADDR0_Pos (16) /*!< EMAC_T::CAM6L: MACADDR0 Position */ +#define EMAC_CAM6L_MACADDR0_Msk (0xfful << EMAC_CAM6L_MACADDR0_Pos) /*!< EMAC_T::CAM6L: MACADDR0 Mask */ + +#define EMAC_CAM6L_MACADDR1_Pos (24) /*!< EMAC_T::CAM6L: MACADDR1 Position */ +#define EMAC_CAM6L_MACADDR1_Msk (0xfful << EMAC_CAM6L_MACADDR1_Pos) /*!< EMAC_T::CAM6L: MACADDR1 Mask */ + +#define EMAC_CAM7M_MACADDR2_Pos (0) /*!< EMAC_T::CAM7M: MACADDR2 Position */ +#define EMAC_CAM7M_MACADDR2_Msk (0xfful << EMAC_CAM7M_MACADDR2_Pos) /*!< EMAC_T::CAM7M: MACADDR2 Mask */ + +#define EMAC_CAM7M_MACADDR3_Pos (8) /*!< EMAC_T::CAM7M: MACADDR3 Position */ +#define EMAC_CAM7M_MACADDR3_Msk (0xfful << EMAC_CAM7M_MACADDR3_Pos) /*!< EMAC_T::CAM7M: MACADDR3 Mask */ + +#define EMAC_CAM7M_MACADDR4_Pos (16) /*!< EMAC_T::CAM7M: MACADDR4 Position */ +#define EMAC_CAM7M_MACADDR4_Msk (0xfful << EMAC_CAM7M_MACADDR4_Pos) /*!< EMAC_T::CAM7M: MACADDR4 Mask */ + +#define EMAC_CAM7M_MACADDR5_Pos (24) /*!< EMAC_T::CAM7M: MACADDR5 Position */ +#define EMAC_CAM7M_MACADDR5_Msk (0xfful << EMAC_CAM7M_MACADDR5_Pos) /*!< EMAC_T::CAM7M: MACADDR5 Mask */ + +#define EMAC_CAM7L_MACADDR0_Pos (16) /*!< EMAC_T::CAM7L: MACADDR0 Position */ +#define EMAC_CAM7L_MACADDR0_Msk (0xfful << EMAC_CAM7L_MACADDR0_Pos) /*!< EMAC_T::CAM7L: MACADDR0 Mask */ + +#define EMAC_CAM7L_MACADDR1_Pos (24) /*!< EMAC_T::CAM7L: MACADDR1 Position */ +#define EMAC_CAM7L_MACADDR1_Msk (0xfful << EMAC_CAM7L_MACADDR1_Pos) /*!< EMAC_T::CAM7L: MACADDR1 Mask */ + +#define EMAC_CAM8M_MACADDR2_Pos (0) /*!< EMAC_T::CAM8M: MACADDR2 Position */ +#define EMAC_CAM8M_MACADDR2_Msk (0xfful << EMAC_CAM8M_MACADDR2_Pos) /*!< EMAC_T::CAM8M: MACADDR2 Mask */ + +#define EMAC_CAM8M_MACADDR3_Pos (8) /*!< EMAC_T::CAM8M: MACADDR3 Position */ +#define EMAC_CAM8M_MACADDR3_Msk (0xfful << EMAC_CAM8M_MACADDR3_Pos) /*!< EMAC_T::CAM8M: MACADDR3 Mask */ + +#define EMAC_CAM8M_MACADDR4_Pos (16) /*!< EMAC_T::CAM8M: MACADDR4 Position */ +#define EMAC_CAM8M_MACADDR4_Msk (0xfful << EMAC_CAM8M_MACADDR4_Pos) /*!< EMAC_T::CAM8M: MACADDR4 Mask */ + +#define EMAC_CAM8M_MACADDR5_Pos (24) /*!< EMAC_T::CAM8M: MACADDR5 Position */ +#define EMAC_CAM8M_MACADDR5_Msk (0xfful << EMAC_CAM8M_MACADDR5_Pos) /*!< EMAC_T::CAM8M: MACADDR5 Mask */ + +#define EMAC_CAM8L_MACADDR0_Pos (16) /*!< EMAC_T::CAM8L: MACADDR0 Position */ +#define EMAC_CAM8L_MACADDR0_Msk (0xfful << EMAC_CAM8L_MACADDR0_Pos) /*!< EMAC_T::CAM8L: MACADDR0 Mask */ + +#define EMAC_CAM8L_MACADDR1_Pos (24) /*!< EMAC_T::CAM8L: MACADDR1 Position */ +#define EMAC_CAM8L_MACADDR1_Msk (0xfful << EMAC_CAM8L_MACADDR1_Pos) /*!< EMAC_T::CAM8L: MACADDR1 Mask */ + +#define EMAC_CAM9M_MACADDR2_Pos (0) /*!< EMAC_T::CAM9M: MACADDR2 Position */ +#define EMAC_CAM9M_MACADDR2_Msk (0xfful << EMAC_CAM9M_MACADDR2_Pos) /*!< EMAC_T::CAM9M: MACADDR2 Mask */ + +#define EMAC_CAM9M_MACADDR3_Pos (8) /*!< EMAC_T::CAM9M: MACADDR3 Position */ +#define EMAC_CAM9M_MACADDR3_Msk (0xfful << EMAC_CAM9M_MACADDR3_Pos) /*!< EMAC_T::CAM9M: MACADDR3 Mask */ + +#define EMAC_CAM9M_MACADDR4_Pos (16) /*!< EMAC_T::CAM9M: MACADDR4 Position */ +#define EMAC_CAM9M_MACADDR4_Msk (0xfful << EMAC_CAM9M_MACADDR4_Pos) /*!< EMAC_T::CAM9M: MACADDR4 Mask */ + +#define EMAC_CAM9M_MACADDR5_Pos (24) /*!< EMAC_T::CAM9M: MACADDR5 Position */ +#define EMAC_CAM9M_MACADDR5_Msk (0xfful << EMAC_CAM9M_MACADDR5_Pos) /*!< EMAC_T::CAM9M: MACADDR5 Mask */ + +#define EMAC_CAM9L_MACADDR0_Pos (16) /*!< EMAC_T::CAM9L: MACADDR0 Position */ +#define EMAC_CAM9L_MACADDR0_Msk (0xfful << EMAC_CAM9L_MACADDR0_Pos) /*!< EMAC_T::CAM9L: MACADDR0 Mask */ + +#define EMAC_CAM9L_MACADDR1_Pos (24) /*!< EMAC_T::CAM9L: MACADDR1 Position */ +#define EMAC_CAM9L_MACADDR1_Msk (0xfful << EMAC_CAM9L_MACADDR1_Pos) /*!< EMAC_T::CAM9L: MACADDR1 Mask */ + +#define EMAC_CAM10M_MACADDR2_Pos (0) /*!< EMAC_T::CAM10M: MACADDR2 Position */ +#define EMAC_CAM10M_MACADDR2_Msk (0xfful << EMAC_CAM10M_MACADDR2_Pos) /*!< EMAC_T::CAM10M: MACADDR2 Mask */ + +#define EMAC_CAM10M_MACADDR3_Pos (8) /*!< EMAC_T::CAM10M: MACADDR3 Position */ +#define EMAC_CAM10M_MACADDR3_Msk (0xfful << EMAC_CAM10M_MACADDR3_Pos) /*!< EMAC_T::CAM10M: MACADDR3 Mask */ + +#define EMAC_CAM10M_MACADDR4_Pos (16) /*!< EMAC_T::CAM10M: MACADDR4 Position */ +#define EMAC_CAM10M_MACADDR4_Msk (0xfful << EMAC_CAM10M_MACADDR4_Pos) /*!< EMAC_T::CAM10M: MACADDR4 Mask */ + +#define EMAC_CAM10M_MACADDR5_Pos (24) /*!< EMAC_T::CAM10M: MACADDR5 Position */ +#define EMAC_CAM10M_MACADDR5_Msk (0xfful << EMAC_CAM10M_MACADDR5_Pos) /*!< EMAC_T::CAM10M: MACADDR5 Mask */ + +#define EMAC_CAM10L_MACADDR0_Pos (16) /*!< EMAC_T::CAM10L: MACADDR0 Position */ +#define EMAC_CAM10L_MACADDR0_Msk (0xfful << EMAC_CAM10L_MACADDR0_Pos) /*!< EMAC_T::CAM10L: MACADDR0 Mask */ + +#define EMAC_CAM10L_MACADDR1_Pos (24) /*!< EMAC_T::CAM10L: MACADDR1 Position */ +#define EMAC_CAM10L_MACADDR1_Msk (0xfful << EMAC_CAM10L_MACADDR1_Pos) /*!< EMAC_T::CAM10L: MACADDR1 Mask */ + +#define EMAC_CAM11M_MACADDR2_Pos (0) /*!< EMAC_T::CAM11M: MACADDR2 Position */ +#define EMAC_CAM11M_MACADDR2_Msk (0xfful << EMAC_CAM11M_MACADDR2_Pos) /*!< EMAC_T::CAM11M: MACADDR2 Mask */ + +#define EMAC_CAM11M_MACADDR3_Pos (8) /*!< EMAC_T::CAM11M: MACADDR3 Position */ +#define EMAC_CAM11M_MACADDR3_Msk (0xfful << EMAC_CAM11M_MACADDR3_Pos) /*!< EMAC_T::CAM11M: MACADDR3 Mask */ + +#define EMAC_CAM11M_MACADDR4_Pos (16) /*!< EMAC_T::CAM11M: MACADDR4 Position */ +#define EMAC_CAM11M_MACADDR4_Msk (0xfful << EMAC_CAM11M_MACADDR4_Pos) /*!< EMAC_T::CAM11M: MACADDR4 Mask */ + +#define EMAC_CAM11M_MACADDR5_Pos (24) /*!< EMAC_T::CAM11M: MACADDR5 Position */ +#define EMAC_CAM11M_MACADDR5_Msk (0xfful << EMAC_CAM11M_MACADDR5_Pos) /*!< EMAC_T::CAM11M: MACADDR5 Mask */ + +#define EMAC_CAM11L_MACADDR0_Pos (16) /*!< EMAC_T::CAM11L: MACADDR0 Position */ +#define EMAC_CAM11L_MACADDR0_Msk (0xfful << EMAC_CAM11L_MACADDR0_Pos) /*!< EMAC_T::CAM11L: MACADDR0 Mask */ + +#define EMAC_CAM11L_MACADDR1_Pos (24) /*!< EMAC_T::CAM11L: MACADDR1 Position */ +#define EMAC_CAM11L_MACADDR1_Msk (0xfful << EMAC_CAM11L_MACADDR1_Pos) /*!< EMAC_T::CAM11L: MACADDR1 Mask */ + +#define EMAC_CAM12M_MACADDR2_Pos (0) /*!< EMAC_T::CAM12M: MACADDR2 Position */ +#define EMAC_CAM12M_MACADDR2_Msk (0xfful << EMAC_CAM12M_MACADDR2_Pos) /*!< EMAC_T::CAM12M: MACADDR2 Mask */ + +#define EMAC_CAM12M_MACADDR3_Pos (8) /*!< EMAC_T::CAM12M: MACADDR3 Position */ +#define EMAC_CAM12M_MACADDR3_Msk (0xfful << EMAC_CAM12M_MACADDR3_Pos) /*!< EMAC_T::CAM12M: MACADDR3 Mask */ + +#define EMAC_CAM12M_MACADDR4_Pos (16) /*!< EMAC_T::CAM12M: MACADDR4 Position */ +#define EMAC_CAM12M_MACADDR4_Msk (0xfful << EMAC_CAM12M_MACADDR4_Pos) /*!< EMAC_T::CAM12M: MACADDR4 Mask */ + +#define EMAC_CAM12M_MACADDR5_Pos (24) /*!< EMAC_T::CAM12M: MACADDR5 Position */ +#define EMAC_CAM12M_MACADDR5_Msk (0xfful << EMAC_CAM12M_MACADDR5_Pos) /*!< EMAC_T::CAM12M: MACADDR5 Mask */ + +#define EMAC_CAM12L_MACADDR0_Pos (16) /*!< EMAC_T::CAM12L: MACADDR0 Position */ +#define EMAC_CAM12L_MACADDR0_Msk (0xfful << EMAC_CAM12L_MACADDR0_Pos) /*!< EMAC_T::CAM12L: MACADDR0 Mask */ + +#define EMAC_CAM12L_MACADDR1_Pos (24) /*!< EMAC_T::CAM12L: MACADDR1 Position */ +#define EMAC_CAM12L_MACADDR1_Msk (0xfful << EMAC_CAM12L_MACADDR1_Pos) /*!< EMAC_T::CAM12L: MACADDR1 Mask */ + +#define EMAC_CAM13M_MACADDR2_Pos (0) /*!< EMAC_T::CAM13M: MACADDR2 Position */ +#define EMAC_CAM13M_MACADDR2_Msk (0xfful << EMAC_CAM13M_MACADDR2_Pos) /*!< EMAC_T::CAM13M: MACADDR2 Mask */ + +#define EMAC_CAM13M_MACADDR3_Pos (8) /*!< EMAC_T::CAM13M: MACADDR3 Position */ +#define EMAC_CAM13M_MACADDR3_Msk (0xfful << EMAC_CAM13M_MACADDR3_Pos) /*!< EMAC_T::CAM13M: MACADDR3 Mask */ + +#define EMAC_CAM13M_MACADDR4_Pos (16) /*!< EMAC_T::CAM13M: MACADDR4 Position */ +#define EMAC_CAM13M_MACADDR4_Msk (0xfful << EMAC_CAM13M_MACADDR4_Pos) /*!< EMAC_T::CAM13M: MACADDR4 Mask */ + +#define EMAC_CAM13M_MACADDR5_Pos (24) /*!< EMAC_T::CAM13M: MACADDR5 Position */ +#define EMAC_CAM13M_MACADDR5_Msk (0xfful << EMAC_CAM13M_MACADDR5_Pos) /*!< EMAC_T::CAM13M: MACADDR5 Mask */ + +#define EMAC_CAM13L_MACADDR0_Pos (16) /*!< EMAC_T::CAM13L: MACADDR0 Position */ +#define EMAC_CAM13L_MACADDR0_Msk (0xfful << EMAC_CAM13L_MACADDR0_Pos) /*!< EMAC_T::CAM13L: MACADDR0 Mask */ + +#define EMAC_CAM13L_MACADDR1_Pos (24) /*!< EMAC_T::CAM13L: MACADDR1 Position */ +#define EMAC_CAM13L_MACADDR1_Msk (0xfful << EMAC_CAM13L_MACADDR1_Pos) /*!< EMAC_T::CAM13L: MACADDR1 Mask */ + +#define EMAC_CAM14M_MACADDR2_Pos (0) /*!< EMAC_T::CAM14M: MACADDR2 Position */ +#define EMAC_CAM14M_MACADDR2_Msk (0xfful << EMAC_CAM14M_MACADDR2_Pos) /*!< EMAC_T::CAM14M: MACADDR2 Mask */ + +#define EMAC_CAM14M_MACADDR3_Pos (8) /*!< EMAC_T::CAM14M: MACADDR3 Position */ +#define EMAC_CAM14M_MACADDR3_Msk (0xfful << EMAC_CAM14M_MACADDR3_Pos) /*!< EMAC_T::CAM14M: MACADDR3 Mask */ + +#define EMAC_CAM14M_MACADDR4_Pos (16) /*!< EMAC_T::CAM14M: MACADDR4 Position */ +#define EMAC_CAM14M_MACADDR4_Msk (0xfful << EMAC_CAM14M_MACADDR4_Pos) /*!< EMAC_T::CAM14M: MACADDR4 Mask */ + +#define EMAC_CAM14M_MACADDR5_Pos (24) /*!< EMAC_T::CAM14M: MACADDR5 Position */ +#define EMAC_CAM14M_MACADDR5_Msk (0xfful << EMAC_CAM14M_MACADDR5_Pos) /*!< EMAC_T::CAM14M: MACADDR5 Mask */ + +#define EMAC_CAM14L_MACADDR0_Pos (16) /*!< EMAC_T::CAM14L: MACADDR0 Position */ +#define EMAC_CAM14L_MACADDR0_Msk (0xfful << EMAC_CAM14L_MACADDR0_Pos) /*!< EMAC_T::CAM14L: MACADDR0 Mask */ + +#define EMAC_CAM14L_MACADDR1_Pos (24) /*!< EMAC_T::CAM14L: MACADDR1 Position */ +#define EMAC_CAM14L_MACADDR1_Msk (0xfful << EMAC_CAM14L_MACADDR1_Pos) /*!< EMAC_T::CAM14L: MACADDR1 Mask */ + +#define EMAC_CAM15MSB_OPCODE_Pos (0) /*!< EMAC_T::CAM15MSB: OPCODE Position */ +#define EMAC_CAM15MSB_OPCODE_Msk (0xfffful << EMAC_CAM15MSB_OPCODE_Pos) /*!< EMAC_T::CAM15MSB: OPCODE Mask */ + +#define EMAC_CAM15MSB_LENGTH_Pos (16) /*!< EMAC_T::CAM15MSB: LENGTH Position */ +#define EMAC_CAM15MSB_LENGTH_Msk (0xfffful << EMAC_CAM15MSB_LENGTH_Pos) /*!< EMAC_T::CAM15MSB: LENGTH Mask */ + +#define EMAC_CAM15LSB_OPERAND_Pos (24) /*!< EMAC_T::CAM15LSB: OPERAND Position */ +#define EMAC_CAM15LSB_OPERAND_Msk (0xfful << EMAC_CAM15LSB_OPERAND_Pos) /*!< EMAC_T::CAM15LSB: OPERAND Mask */ + +#define EMAC_TXDSA_TXDSA_Pos (0) /*!< EMAC_T::TXDSA: TXDSA Position */ +#define EMAC_TXDSA_TXDSA_Msk (0xfffffffful << EMAC_TXDSA_TXDSA_Pos) /*!< EMAC_T::TXDSA: TXDSA Mask */ + +#define EMAC_RXDSA_RXDSA_Pos (0) /*!< EMAC_T::RXDSA: RXDSA Position */ +#define EMAC_RXDSA_RXDSA_Msk (0xfffffffful << EMAC_RXDSA_RXDSA_Pos) /*!< EMAC_T::RXDSA: RXDSA Mask */ + +#define EMAC_CTL_RXON_Pos (0) /*!< EMAC_T::CTL: RXON Position */ +#define EMAC_CTL_RXON_Msk (0x1ul << EMAC_CTL_RXON_Pos) /*!< EMAC_T::CTL: RXON Mask */ + +#define EMAC_CTL_ALP_Pos (1) /*!< EMAC_T::CTL: ALP Position */ +#define EMAC_CTL_ALP_Msk (0x1ul << EMAC_CTL_ALP_Pos) /*!< EMAC_T::CTL: ALP Mask */ + +#define EMAC_CTL_ARP_Pos (2) /*!< EMAC_T::CTL: ARP Position */ +#define EMAC_CTL_ARP_Msk (0x1ul << EMAC_CTL_ARP_Pos) /*!< EMAC_T::CTL: ARP Mask */ + +#define EMAC_CTL_ACP_Pos (3) /*!< EMAC_T::CTL: ACP Position */ +#define EMAC_CTL_ACP_Msk (0x1ul << EMAC_CTL_ACP_Pos) /*!< EMAC_T::CTL: ACP Mask */ + +#define EMAC_CTL_AEP_Pos (4) /*!< EMAC_T::CTL: AEP Position */ +#define EMAC_CTL_AEP_Msk (0x1ul << EMAC_CTL_AEP_Pos) /*!< EMAC_T::CTL: AEP Mask */ + +#define EMAC_CTL_STRIPCRC_Pos (5) /*!< EMAC_T::CTL: STRIPCRC Position */ +#define EMAC_CTL_STRIPCRC_Msk (0x1ul << EMAC_CTL_STRIPCRC_Pos) /*!< EMAC_T::CTL: STRIPCRC Mask */ + +#define EMAC_CTL_WOLEN_Pos (6) /*!< EMAC_T::CTL: WOLEN Position */ +#define EMAC_CTL_WOLEN_Msk (0x1ul << EMAC_CTL_WOLEN_Pos) /*!< EMAC_T::CTL: WOLEN Mask */ + +#define EMAC_CTL_TXON_Pos (8) /*!< EMAC_T::CTL: TXON Position */ +#define EMAC_CTL_TXON_Msk (0x1ul << EMAC_CTL_TXON_Pos) /*!< EMAC_T::CTL: TXON Mask */ + +#define EMAC_CTL_NODEF_Pos (9) /*!< EMAC_T::CTL: NODEF Position */ +#define EMAC_CTL_NODEF_Msk (0x1ul << EMAC_CTL_NODEF_Pos) /*!< EMAC_T::CTL: NODEF Mask */ + +#define EMAC_CTL_SDPZ_Pos (16) /*!< EMAC_T::CTL: SDPZ Position */ +#define EMAC_CTL_SDPZ_Msk (0x1ul << EMAC_CTL_SDPZ_Pos) /*!< EMAC_T::CTL: SDPZ Mask */ + +#define EMAC_CTL_SQECHKEN_Pos (17) /*!< EMAC_T::CTL: SQECHKEN Position */ +#define EMAC_CTL_SQECHKEN_Msk (0x1ul << EMAC_CTL_SQECHKEN_Pos) /*!< EMAC_T::CTL: SQECHKEN Mask */ + +#define EMAC_CTL_FUDUP_Pos (18) /*!< EMAC_T::CTL: FUDUP Position */ +#define EMAC_CTL_FUDUP_Msk (0x1ul << EMAC_CTL_FUDUP_Pos) /*!< EMAC_T::CTL: FUDUP Mask */ + +#define EMAC_CTL_RMIIRXCTL_Pos (19) /*!< EMAC_T::CTL: RMIIRXCTL Position */ +#define EMAC_CTL_RMIIRXCTL_Msk (0x1ul << EMAC_CTL_RMIIRXCTL_Pos) /*!< EMAC_T::CTL: RMIIRXCTL Mask */ + +#define EMAC_CTL_OPMODE_Pos (20) /*!< EMAC_T::CTL: OPMODE Position */ +#define EMAC_CTL_OPMODE_Msk (0x1ul << EMAC_CTL_OPMODE_Pos) /*!< EMAC_T::CTL: OPMODE Mask */ + +#define EMAC_CTL_RMIIEN_Pos (22) /*!< EMAC_T::CTL: RMIIEN Position */ +#define EMAC_CTL_RMIIEN_Msk (0x1ul << EMAC_CTL_RMIIEN_Pos) /*!< EMAC_T::CTL: RMIIEN Mask */ + +#define EMAC_CTL_RST_Pos (24) /*!< EMAC_T::CTL: RST Position */ +#define EMAC_CTL_RST_Msk (0x1ul << EMAC_CTL_RST_Pos) /*!< EMAC_T::CTL: RST Mask */ + +#define EMAC_MIIMDAT_DATA_Pos (0) /*!< EMAC_T::MIIMDAT: DATA Position */ +#define EMAC_MIIMDAT_DATA_Msk (0xfffful << EMAC_MIIMDAT_DATA_Pos) /*!< EMAC_T::MIIMDAT: DATA Mask */ + +#define EMAC_MIIMCTL_PHYREG_Pos (0) /*!< EMAC_T::MIIMCTL: PHYREG Position */ +#define EMAC_MIIMCTL_PHYREG_Msk (0x1ful << EMAC_MIIMCTL_PHYREG_Pos) /*!< EMAC_T::MIIMCTL: PHYREG Mask */ + +#define EMAC_MIIMCTL_PHYADDR_Pos (8) /*!< EMAC_T::MIIMCTL: PHYADDR Position */ +#define EMAC_MIIMCTL_PHYADDR_Msk (0x1ful << EMAC_MIIMCTL_PHYADDR_Pos) /*!< EMAC_T::MIIMCTL: PHYADDR Mask */ + +#define EMAC_MIIMCTL_WRITE_Pos (16) /*!< EMAC_T::MIIMCTL: WRITE Position */ +#define EMAC_MIIMCTL_WRITE_Msk (0x1ul << EMAC_MIIMCTL_WRITE_Pos) /*!< EMAC_T::MIIMCTL: WRITE Mask */ + +#define EMAC_MIIMCTL_BUSY_Pos (17) /*!< EMAC_T::MIIMCTL: BUSY Position */ +#define EMAC_MIIMCTL_BUSY_Msk (0x1ul << EMAC_MIIMCTL_BUSY_Pos) /*!< EMAC_T::MIIMCTL: BUSY Mask */ + +#define EMAC_MIIMCTL_PREAMSP_Pos (18) /*!< EMAC_T::MIIMCTL: PREAMSP Position */ +#define EMAC_MIIMCTL_PREAMSP_Msk (0x1ul << EMAC_MIIMCTL_PREAMSP_Pos) /*!< EMAC_T::MIIMCTL: PREAMSP Mask */ + +#define EMAC_MIIMCTL_MDCON_Pos (19) /*!< EMAC_T::MIIMCTL: MDCON Position */ +#define EMAC_MIIMCTL_MDCON_Msk (0x1ul << EMAC_MIIMCTL_MDCON_Pos) /*!< EMAC_T::MIIMCTL: MDCON Mask */ + +#define EMAC_FIFOCTL_RXFIFOTH_Pos (0) /*!< EMAC_T::FIFOCTL: RXFIFOTH Position */ +#define EMAC_FIFOCTL_RXFIFOTH_Msk (0x3ul << EMAC_FIFOCTL_RXFIFOTH_Pos) /*!< EMAC_T::FIFOCTL: RXFIFOTH Mask */ + +#define EMAC_FIFOCTL_TXFIFOTH_Pos (8) /*!< EMAC_T::FIFOCTL: TXFIFOTH Position */ +#define EMAC_FIFOCTL_TXFIFOTH_Msk (0x3ul << EMAC_FIFOCTL_TXFIFOTH_Pos) /*!< EMAC_T::FIFOCTL: TXFIFOTH Mask */ + +#define EMAC_FIFOCTL_BURSTLEN_Pos (20) /*!< EMAC_T::FIFOCTL: BURSTLEN Position */ +#define EMAC_FIFOCTL_BURSTLEN_Msk (0x3ul << EMAC_FIFOCTL_BURSTLEN_Pos) /*!< EMAC_T::FIFOCTL: BURSTLEN Mask */ + +#define EMAC_TXST_TXST_Pos (0) /*!< EMAC_T::TXST: TXST Position */ +#define EMAC_TXST_TXST_Msk (0xfffffffful << EMAC_TXST_TXST_Pos) /*!< EMAC_T::TXST: TXST Mask */ + +#define EMAC_RXST_RXST_Pos (0) /*!< EMAC_T::RXST: RXST Position */ +#define EMAC_RXST_RXST_Msk (0xfffffffful << EMAC_RXST_RXST_Pos) /*!< EMAC_T::RXST: RXST Mask */ + +#define EMAC_MRFL_MRFL_Pos (0) /*!< EMAC_T::MRFL: MRFL Position */ +#define EMAC_MRFL_MRFL_Msk (0xfffful << EMAC_MRFL_MRFL_Pos) /*!< EMAC_T::MRFL: MRFL Mask */ + +#define EMAC_INTEN_RXIEN_Pos (0) /*!< EMAC_T::INTEN: RXIEN Position */ +#define EMAC_INTEN_RXIEN_Msk (0x1ul << EMAC_INTEN_RXIEN_Pos) /*!< EMAC_T::INTEN: RXIEN Mask */ + +#define EMAC_INTEN_CRCEIEN_Pos (1) /*!< EMAC_T::INTEN: CRCEIEN Position */ +#define EMAC_INTEN_CRCEIEN_Msk (0x1ul << EMAC_INTEN_CRCEIEN_Pos) /*!< EMAC_T::INTEN: CRCEIEN Mask */ + +#define EMAC_INTEN_RXOVIEN_Pos (2) /*!< EMAC_T::INTEN: RXOVIEN Position */ +#define EMAC_INTEN_RXOVIEN_Msk (0x1ul << EMAC_INTEN_RXOVIEN_Pos) /*!< EMAC_T::INTEN: RXOVIEN Mask */ + +#define EMAC_INTEN_LPIEN_Pos (3) /*!< EMAC_T::INTEN: LPIEN Position */ +#define EMAC_INTEN_LPIEN_Msk (0x1ul << EMAC_INTEN_LPIEN_Pos) /*!< EMAC_T::INTEN: LPIEN Mask */ + +#define EMAC_INTEN_RXGDIEN_Pos (4) /*!< EMAC_T::INTEN: RXGDIEN Position */ +#define EMAC_INTEN_RXGDIEN_Msk (0x1ul << EMAC_INTEN_RXGDIEN_Pos) /*!< EMAC_T::INTEN: RXGDIEN Mask */ + +#define EMAC_INTEN_ALIEIEN_Pos (5) /*!< EMAC_T::INTEN: ALIEIEN Position */ +#define EMAC_INTEN_ALIEIEN_Msk (0x1ul << EMAC_INTEN_ALIEIEN_Pos) /*!< EMAC_T::INTEN: ALIEIEN Mask */ + +#define EMAC_INTEN_RPIEN_Pos (6) /*!< EMAC_T::INTEN: RPIEN Position */ +#define EMAC_INTEN_RPIEN_Msk (0x1ul << EMAC_INTEN_RPIEN_Pos) /*!< EMAC_T::INTEN: RPIEN Mask */ + +#define EMAC_INTEN_MPCOVIEN_Pos (7) /*!< EMAC_T::INTEN: MPCOVIEN Position */ +#define EMAC_INTEN_MPCOVIEN_Msk (0x1ul << EMAC_INTEN_MPCOVIEN_Pos) /*!< EMAC_T::INTEN: MPCOVIEN Mask */ + +#define EMAC_INTEN_MFLEIEN_Pos (8) /*!< EMAC_T::INTEN: MFLEIEN Position */ +#define EMAC_INTEN_MFLEIEN_Msk (0x1ul << EMAC_INTEN_MFLEIEN_Pos) /*!< EMAC_T::INTEN: MFLEIEN Mask */ + +#define EMAC_INTEN_DENIEN_Pos (9) /*!< EMAC_T::INTEN: DENIEN Position */ +#define EMAC_INTEN_DENIEN_Msk (0x1ul << EMAC_INTEN_DENIEN_Pos) /*!< EMAC_T::INTEN: DENIEN Mask */ + +#define EMAC_INTEN_RDUIEN_Pos (10) /*!< EMAC_T::INTEN: RDUIEN Position */ +#define EMAC_INTEN_RDUIEN_Msk (0x1ul << EMAC_INTEN_RDUIEN_Pos) /*!< EMAC_T::INTEN: RDUIEN Mask */ + +#define EMAC_INTEN_RXBEIEN_Pos (11) /*!< EMAC_T::INTEN: RXBEIEN Position */ +#define EMAC_INTEN_RXBEIEN_Msk (0x1ul << EMAC_INTEN_RXBEIEN_Pos) /*!< EMAC_T::INTEN: RXBEIEN Mask */ + +#define EMAC_INTEN_CFRIEN_Pos (14) /*!< EMAC_T::INTEN: CFRIEN Position */ +#define EMAC_INTEN_CFRIEN_Msk (0x1ul << EMAC_INTEN_CFRIEN_Pos) /*!< EMAC_T::INTEN: CFRIEN Mask */ + +#define EMAC_INTEN_WOLIEN_Pos (15) /*!< EMAC_T::INTEN: WOLIEN Position */ +#define EMAC_INTEN_WOLIEN_Msk (0x1ul << EMAC_INTEN_WOLIEN_Pos) /*!< EMAC_T::INTEN: WOLIEN Mask */ + +#define EMAC_INTEN_TXIEN_Pos (16) /*!< EMAC_T::INTEN: TXIEN Position */ +#define EMAC_INTEN_TXIEN_Msk (0x1ul << EMAC_INTEN_TXIEN_Pos) /*!< EMAC_T::INTEN: TXIEN Mask */ + +#define EMAC_INTEN_TXUDIEN_Pos (17) /*!< EMAC_T::INTEN: TXUDIEN Position */ +#define EMAC_INTEN_TXUDIEN_Msk (0x1ul << EMAC_INTEN_TXUDIEN_Pos) /*!< EMAC_T::INTEN: TXUDIEN Mask */ + +#define EMAC_INTEN_TXCPIEN_Pos (18) /*!< EMAC_T::INTEN: TXCPIEN Position */ +#define EMAC_INTEN_TXCPIEN_Msk (0x1ul << EMAC_INTEN_TXCPIEN_Pos) /*!< EMAC_T::INTEN: TXCPIEN Mask */ + +#define EMAC_INTEN_EXDEFIEN_Pos (19) /*!< EMAC_T::INTEN: EXDEFIEN Position */ +#define EMAC_INTEN_EXDEFIEN_Msk (0x1ul << EMAC_INTEN_EXDEFIEN_Pos) /*!< EMAC_T::INTEN: EXDEFIEN Mask */ + +#define EMAC_INTEN_NCSIEN_Pos (20) /*!< EMAC_T::INTEN: NCSIEN Position */ +#define EMAC_INTEN_NCSIEN_Msk (0x1ul << EMAC_INTEN_NCSIEN_Pos) /*!< EMAC_T::INTEN: NCSIEN Mask */ + +#define EMAC_INTEN_TXABTIEN_Pos (21) /*!< EMAC_T::INTEN: TXABTIEN Position */ +#define EMAC_INTEN_TXABTIEN_Msk (0x1ul << EMAC_INTEN_TXABTIEN_Pos) /*!< EMAC_T::INTEN: TXABTIEN Mask */ + +#define EMAC_INTEN_LCIEN_Pos (22) /*!< EMAC_T::INTEN: LCIEN Position */ +#define EMAC_INTEN_LCIEN_Msk (0x1ul << EMAC_INTEN_LCIEN_Pos) /*!< EMAC_T::INTEN: LCIEN Mask */ + +#define EMAC_INTEN_TDUIEN_Pos (23) /*!< EMAC_T::INTEN: TDUIEN Position */ +#define EMAC_INTEN_TDUIEN_Msk (0x1ul << EMAC_INTEN_TDUIEN_Pos) /*!< EMAC_T::INTEN: TDUIEN Mask */ + +#define EMAC_INTEN_TXBEIEN_Pos (24) /*!< EMAC_T::INTEN: TXBEIEN Position */ +#define EMAC_INTEN_TXBEIEN_Msk (0x1ul << EMAC_INTEN_TXBEIEN_Pos) /*!< EMAC_T::INTEN: TXBEIEN Mask */ + +#define EMAC_INTEN_TSALMIEN_Pos (28) /*!< EMAC_T::INTEN: TSALMIEN Position */ +#define EMAC_INTEN_TSALMIEN_Msk (0x1ul << EMAC_INTEN_TSALMIEN_Pos) /*!< EMAC_T::INTEN: TSALMIEN Mask */ + +#define EMAC_INTSTS_RXIF_Pos (0) /*!< EMAC_T::INTSTS: RXIF Position */ +#define EMAC_INTSTS_RXIF_Msk (0x1ul << EMAC_INTSTS_RXIF_Pos) /*!< EMAC_T::INTSTS: RXIF Mask */ + +#define EMAC_INTSTS_CRCEIF_Pos (1) /*!< EMAC_T::INTSTS: CRCEIF Position */ +#define EMAC_INTSTS_CRCEIF_Msk (0x1ul << EMAC_INTSTS_CRCEIF_Pos) /*!< EMAC_T::INTSTS: CRCEIF Mask */ + +#define EMAC_INTSTS_RXOVIF_Pos (2) /*!< EMAC_T::INTSTS: RXOVIF Position */ +#define EMAC_INTSTS_RXOVIF_Msk (0x1ul << EMAC_INTSTS_RXOVIF_Pos) /*!< EMAC_T::INTSTS: RXOVIF Mask */ + +#define EMAC_INTSTS_LPIF_Pos (3) /*!< EMAC_T::INTSTS: LPIF Position */ +#define EMAC_INTSTS_LPIF_Msk (0x1ul << EMAC_INTSTS_LPIF_Pos) /*!< EMAC_T::INTSTS: LPIF Mask */ + +#define EMAC_INTSTS_RXGDIF_Pos (4) /*!< EMAC_T::INTSTS: RXGDIF Position */ +#define EMAC_INTSTS_RXGDIF_Msk (0x1ul << EMAC_INTSTS_RXGDIF_Pos) /*!< EMAC_T::INTSTS: RXGDIF Mask */ + +#define EMAC_INTSTS_ALIEIF_Pos (5) /*!< EMAC_T::INTSTS: ALIEIF Position */ +#define EMAC_INTSTS_ALIEIF_Msk (0x1ul << EMAC_INTSTS_ALIEIF_Pos) /*!< EMAC_T::INTSTS: ALIEIF Mask */ + +#define EMAC_INTSTS_RPIF_Pos (6) /*!< EMAC_T::INTSTS: RPIF Position */ +#define EMAC_INTSTS_RPIF_Msk (0x1ul << EMAC_INTSTS_RPIF_Pos) /*!< EMAC_T::INTSTS: RPIF Mask */ + +#define EMAC_INTSTS_MPCOVIF_Pos (7) /*!< EMAC_T::INTSTS: MPCOVIF Position */ +#define EMAC_INTSTS_MPCOVIF_Msk (0x1ul << EMAC_INTSTS_MPCOVIF_Pos) /*!< EMAC_T::INTSTS: MPCOVIF Mask */ + +#define EMAC_INTSTS_MFLEIF_Pos (8) /*!< EMAC_T::INTSTS: MFLEIF Position */ +#define EMAC_INTSTS_MFLEIF_Msk (0x1ul << EMAC_INTSTS_MFLEIF_Pos) /*!< EMAC_T::INTSTS: MFLEIF Mask */ + +#define EMAC_INTSTS_DENIF_Pos (9) /*!< EMAC_T::INTSTS: DENIF Position */ +#define EMAC_INTSTS_DENIF_Msk (0x1ul << EMAC_INTSTS_DENIF_Pos) /*!< EMAC_T::INTSTS: DENIF Mask */ + +#define EMAC_INTSTS_RDUIF_Pos (10) /*!< EMAC_T::INTSTS: RDUIF Position */ +#define EMAC_INTSTS_RDUIF_Msk (0x1ul << EMAC_INTSTS_RDUIF_Pos) /*!< EMAC_T::INTSTS: RDUIF Mask */ + +#define EMAC_INTSTS_RXBEIF_Pos (11) /*!< EMAC_T::INTSTS: RXBEIF Position */ +#define EMAC_INTSTS_RXBEIF_Msk (0x1ul << EMAC_INTSTS_RXBEIF_Pos) /*!< EMAC_T::INTSTS: RXBEIF Mask */ + +#define EMAC_INTSTS_CFRIF_Pos (14) /*!< EMAC_T::INTSTS: CFRIF Position */ +#define EMAC_INTSTS_CFRIF_Msk (0x1ul << EMAC_INTSTS_CFRIF_Pos) /*!< EMAC_T::INTSTS: CFRIF Mask */ + +#define EMAC_INTSTS_WOLIF_Pos (15) /*!< EMAC_T::INTSTS: WOLIF Position */ +#define EMAC_INTSTS_WOLIF_Msk (0x1ul << EMAC_INTSTS_WOLIF_Pos) /*!< EMAC_T::INTSTS: WOLIF Mask */ + +#define EMAC_INTSTS_TXIF_Pos (16) /*!< EMAC_T::INTSTS: TXIF Position */ +#define EMAC_INTSTS_TXIF_Msk (0x1ul << EMAC_INTSTS_TXIF_Pos) /*!< EMAC_T::INTSTS: TXIF Mask */ + +#define EMAC_INTSTS_TXUDIF_Pos (17) /*!< EMAC_T::INTSTS: TXUDIF Position */ +#define EMAC_INTSTS_TXUDIF_Msk (0x1ul << EMAC_INTSTS_TXUDIF_Pos) /*!< EMAC_T::INTSTS: TXUDIF Mask */ + +#define EMAC_INTSTS_TXCPIF_Pos (18) /*!< EMAC_T::INTSTS: TXCPIF Position */ +#define EMAC_INTSTS_TXCPIF_Msk (0x1ul << EMAC_INTSTS_TXCPIF_Pos) /*!< EMAC_T::INTSTS: TXCPIF Mask */ + +#define EMAC_INTSTS_EXDEFIF_Pos (19) /*!< EMAC_T::INTSTS: EXDEFIF Position */ +#define EMAC_INTSTS_EXDEFIF_Msk (0x1ul << EMAC_INTSTS_EXDEFIF_Pos) /*!< EMAC_T::INTSTS: EXDEFIF Mask */ + +#define EMAC_INTSTS_NCSIF_Pos (20) /*!< EMAC_T::INTSTS: NCSIF Position */ +#define EMAC_INTSTS_NCSIF_Msk (0x1ul << EMAC_INTSTS_NCSIF_Pos) /*!< EMAC_T::INTSTS: NCSIF Mask */ + +#define EMAC_INTSTS_TXABTIF_Pos (21) /*!< EMAC_T::INTSTS: TXABTIF Position */ +#define EMAC_INTSTS_TXABTIF_Msk (0x1ul << EMAC_INTSTS_TXABTIF_Pos) /*!< EMAC_T::INTSTS: TXABTIF Mask */ + +#define EMAC_INTSTS_LCIF_Pos (22) /*!< EMAC_T::INTSTS: LCIF Position */ +#define EMAC_INTSTS_LCIF_Msk (0x1ul << EMAC_INTSTS_LCIF_Pos) /*!< EMAC_T::INTSTS: LCIF Mask */ + +#define EMAC_INTSTS_TDUIF_Pos (23) /*!< EMAC_T::INTSTS: TDUIF Position */ +#define EMAC_INTSTS_TDUIF_Msk (0x1ul << EMAC_INTSTS_TDUIF_Pos) /*!< EMAC_T::INTSTS: TDUIF Mask */ + +#define EMAC_INTSTS_TXBEIF_Pos (24) /*!< EMAC_T::INTSTS: TXBEIF Position */ +#define EMAC_INTSTS_TXBEIF_Msk (0x1ul << EMAC_INTSTS_TXBEIF_Pos) /*!< EMAC_T::INTSTS: TXBEIF Mask */ + +#define EMAC_INTSTS_TSALMIF_Pos (28) /*!< EMAC_T::INTSTS: TSALMIF Position */ +#define EMAC_INTSTS_TSALMIF_Msk (0x1ul << EMAC_INTSTS_TSALMIF_Pos) /*!< EMAC_T::INTSTS: TSALMIF Mask */ + +#define EMAC_GENSTS_CFR_Pos (0) /*!< EMAC_T::GENSTS: CFR Position */ +#define EMAC_GENSTS_CFR_Msk (0x1ul << EMAC_GENSTS_CFR_Pos) /*!< EMAC_T::GENSTS: CFR Mask */ + +#define EMAC_GENSTS_RXHALT_Pos (1) /*!< EMAC_T::GENSTS: RXHALT Position */ +#define EMAC_GENSTS_RXHALT_Msk (0x1ul << EMAC_GENSTS_RXHALT_Pos) /*!< EMAC_T::GENSTS: RXHALT Mask */ + +#define EMAC_GENSTS_RXFFULL_Pos (2) /*!< EMAC_T::GENSTS: RXFFULL Position */ +#define EMAC_GENSTS_RXFFULL_Msk (0x1ul << EMAC_GENSTS_RXFFULL_Pos) /*!< EMAC_T::GENSTS: RXFFULL Mask */ + +#define EMAC_GENSTS_COLCNT_Pos (4) /*!< EMAC_T::GENSTS: COLCNT Position */ +#define EMAC_GENSTS_COLCNT_Msk (0xful << EMAC_GENSTS_COLCNT_Pos) /*!< EMAC_T::GENSTS: COLCNT Mask */ + +#define EMAC_GENSTS_DEF_Pos (8) /*!< EMAC_T::GENSTS: DEF Position */ +#define EMAC_GENSTS_DEF_Msk (0x1ul << EMAC_GENSTS_DEF_Pos) /*!< EMAC_T::GENSTS: DEF Mask */ + +#define EMAC_GENSTS_TXPAUSED_Pos (9) /*!< EMAC_T::GENSTS: TXPAUSED Position */ +#define EMAC_GENSTS_TXPAUSED_Msk (0x1ul << EMAC_GENSTS_TXPAUSED_Pos) /*!< EMAC_T::GENSTS: TXPAUSED Mask */ + +#define EMAC_GENSTS_SQE_Pos (10) /*!< EMAC_T::GENSTS: SQE Position */ +#define EMAC_GENSTS_SQE_Msk (0x1ul << EMAC_GENSTS_SQE_Pos) /*!< EMAC_T::GENSTS: SQE Mask */ + +#define EMAC_GENSTS_TXHALT_Pos (11) /*!< EMAC_T::GENSTS: TXHALT Position */ +#define EMAC_GENSTS_TXHALT_Msk (0x1ul << EMAC_GENSTS_TXHALT_Pos) /*!< EMAC_T::GENSTS: TXHALT Mask */ + +#define EMAC_GENSTS_RPSTS_Pos (12) /*!< EMAC_T::GENSTS: RPSTS Position */ +#define EMAC_GENSTS_RPSTS_Msk (0x1ul << EMAC_GENSTS_RPSTS_Pos) /*!< EMAC_T::GENSTS: RPSTS Mask */ + +#define EMAC_MPCNT_MPCNT_Pos (0) /*!< EMAC_T::MPCNT: MPCNT Position */ +#define EMAC_MPCNT_MPCNT_Msk (0xfffful << EMAC_MPCNT_MPCNT_Pos) /*!< EMAC_T::MPCNT: MPCNT Mask */ + +#define EMAC_RPCNT_RPCNT_Pos (0) /*!< EMAC_T::RPCNT: RPCNT Position */ +#define EMAC_RPCNT_RPCNT_Msk (0xfffful << EMAC_RPCNT_RPCNT_Pos) /*!< EMAC_T::RPCNT: RPCNT Mask */ + +#define EMAC_FRSTS_RXFLT_Pos (0) /*!< EMAC_T::FRSTS: RXFLT Position */ +#define EMAC_FRSTS_RXFLT_Msk (0xfffful << EMAC_FRSTS_RXFLT_Pos) /*!< EMAC_T::FRSTS: RXFLT Mask */ + +#define EMAC_CTXDSA_CTXDSA_Pos (0) /*!< EMAC_T::CTXDSA: CTXDSA Position */ +#define EMAC_CTXDSA_CTXDSA_Msk (0xfffffffful << EMAC_CTXDSA_CTXDSA_Pos) /*!< EMAC_T::CTXDSA: CTXDSA Mask */ + +#define EMAC_CTXBSA_CTXBSA_Pos (0) /*!< EMAC_T::CTXBSA: CTXBSA Position */ +#define EMAC_CTXBSA_CTXBSA_Msk (0xfffffffful << EMAC_CTXBSA_CTXBSA_Pos) /*!< EMAC_T::CTXBSA: CTXBSA Mask */ + +#define EMAC_CRXDSA_CRXDSA_Pos (0) /*!< EMAC_T::CRXDSA: CRXDSA Position */ +#define EMAC_CRXDSA_CRXDSA_Msk (0xfffffffful << EMAC_CRXDSA_CRXDSA_Pos) /*!< EMAC_T::CRXDSA: CRXDSA Mask */ + +#define EMAC_CRXBSA_CRXBSA_Pos (0) /*!< EMAC_T::CRXBSA: CRXBSA Position */ +#define EMAC_CRXBSA_CRXBSA_Msk (0xfffffffful << EMAC_CRXBSA_CRXBSA_Pos) /*!< EMAC_T::CRXBSA: CRXBSA Mask */ + +#define EMAC_TSCTL_TSEN_Pos (0) /*!< EMAC_T::TSCTL: TSEN Position */ +#define EMAC_TSCTL_TSEN_Msk (0x1ul << EMAC_TSCTL_TSEN_Pos) /*!< EMAC_T::TSCTL: TSEN Mask */ + +#define EMAC_TSCTL_TSIEN_Pos (1) /*!< EMAC_T::TSCTL: TSIEN Position */ +#define EMAC_TSCTL_TSIEN_Msk (0x1ul << EMAC_TSCTL_TSIEN_Pos) /*!< EMAC_T::TSCTL: TSIEN Mask */ + +#define EMAC_TSCTL_TSMODE_Pos (2) /*!< EMAC_T::TSCTL: TSMODE Position */ +#define EMAC_TSCTL_TSMODE_Msk (0x1ul << EMAC_TSCTL_TSMODE_Pos) /*!< EMAC_T::TSCTL: TSMODE Mask */ + +#define EMAC_TSCTL_TSUPDATE_Pos (3) /*!< EMAC_T::TSCTL: TSUPDATE Position */ +#define EMAC_TSCTL_TSUPDATE_Msk (0x1ul << EMAC_TSCTL_TSUPDATE_Pos) /*!< EMAC_T::TSCTL: TSUPDATE Mask */ + +#define EMAC_TSCTL_TSALMEN_Pos (5) /*!< EMAC_T::TSCTL: TSALMEN Position */ +#define EMAC_TSCTL_TSALMEN_Msk (0x1ul << EMAC_TSCTL_TSALMEN_Pos) /*!< EMAC_T::TSCTL: TSALMEN Mask */ + +#define EMAC_TSSEC_SEC_Pos (0) /*!< EMAC_T::TSSEC: SEC Position */ +#define EMAC_TSSEC_SEC_Msk (0xfffffffful << EMAC_TSSEC_SEC_Pos) /*!< EMAC_T::TSSEC: SEC Mask */ + +#define EMAC_TSSUBSEC_SUBSEC_Pos (0) /*!< EMAC_T::TSSUBSEC: SUBSEC Position */ +#define EMAC_TSSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_TSSUBSEC_SUBSEC_Pos) /*!< EMAC_T::TSSUBSEC: SUBSEC Mask */ + +#define EMAC_TSINC_CNTINC_Pos (0) /*!< EMAC_T::TSINC: CNTINC Position */ +#define EMAC_TSINC_CNTINC_Msk (0xfful << EMAC_TSINC_CNTINC_Pos) /*!< EMAC_T::TSINC: CNTINC Mask */ + +#define EMAC_TSADDEND_ADDEND_Pos (0) /*!< EMAC_T::TSADDEND: ADDEND Position */ +#define EMAC_TSADDEND_ADDEND_Msk (0xfffffffful << EMAC_TSADDEND_ADDEND_Pos) /*!< EMAC_T::TSADDEND: ADDEND Mask */ + +#define EMAC_UPDSEC_SEC_Pos (0) /*!< EMAC_T::UPDSEC: SEC Position */ +#define EMAC_UPDSEC_SEC_Msk (0xfffffffful << EMAC_UPDSEC_SEC_Pos) /*!< EMAC_T::UPDSEC: SEC Mask */ + +#define EMAC_UPDSUBSEC_SUBSEC_Pos (0) /*!< EMAC_T::UPDSUBSEC: SUBSEC Position */ +#define EMAC_UPDSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_UPDSUBSEC_SUBSEC_Pos) /*!< EMAC_T::UPDSUBSEC: SUBSEC Mask */ + +#define EMAC_ALMSEC_SEC_Pos (0) /*!< EMAC_T::ALMSEC: SEC Position */ +#define EMAC_ALMSEC_SEC_Msk (0xfffffffful << EMAC_ALMSEC_SEC_Pos) /*!< EMAC_T::ALMSEC: SEC Mask */ + +#define EMAC_ALMSUBSEC_SUBSEC_Pos (0) /*!< EMAC_T::ALMSUBSEC: SUBSEC Position */ +#define EMAC_ALMSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_ALMSUBSEC_SUBSEC_Pos) /*!< EMAC_T::ALMSUBSEC: SUBSEC Mask */ + +/**@}*/ /* EMAC_CONST */ +/**@}*/ /* end of EMAC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __EMAC_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/epwm_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/epwm_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..aa4ba4a478be21ff271a3875e1821670f6e16091 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/epwm_reg.h @@ -0,0 +1,4023 @@ +/**************************************************************************//** + * @file epwm_reg.h + * @version V1.00 + * @brief EPWM register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EPWM_REG_H__ +#define __EPWM_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup EPWM Pulse Width Modulation Controller(EPWM) + Memory Mapped Structure for EPWM Controller +@{ */ + +typedef struct +{ + /** + * @var ECAPDAT_T::RCAPDAT + * Offset: 0x20C EPWM Rising Capture Data Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RCAPDAT |EPWM Rising Capture Data (Read Only) + * | | |When rising capture condition happened, the EPWM counter value will be saved in this register. + * @var ECAPDAT_T::FCAPDAT + * Offset: 0x210 EPWM Falling Capture Data Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FCAPDAT |EPWM Falling Capture Data (Read Only) + * | | |When falling capture condition happened, the EPWM counter value will be saved in this register. + */ + __IO uint32_t RCAPDAT; /*!< [0x20C/0x214/0x21C/0x224/0x22C/0x234] EPWM Rising Capture Data Register 0~5 */ + __IO uint32_t FCAPDAT; /*!< [0x210/0x218/0x220/0x228/0x230/0x238] EPWM Falling Capture Data Register 0~5 */ +} ECAPDAT_T; + +typedef struct +{ + + + /** + * @var EPWM_T::CTL0 + * Offset: 0x00 EPWM Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CTRLD0 |Center Re-load + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[1] |CTRLD1 |Center Re-load + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[2] |CTRLD2 |Center Re-load + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[3] |CTRLD3 |Center Re-load + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[4] |CTRLD4 |Center Re-load + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[5] |CTRLD5 |Center Re-load + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[8] |WINLDEN0 |Window Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. + * |[9] |WINLDEN1 |Window Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. + * |[10] |WINLDEN2 |Window Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. + * |[11] |WINLDEN3 |Window Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. + * |[12] |WINLDEN4 |Window Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. + * |[13] |WINLDEN5 |Window Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. + * |[16] |IMMLDEN0 |Immediately Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. + * |[17] |IMMLDEN1 |Immediately Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. + * |[18] |IMMLDEN2 |Immediately Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. + * |[19] |IMMLDEN3 |Immediately Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. + * |[20] |IMMLDEN4 |Immediately Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. + * |[21] |IMMLDEN5 |Immediately Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. + * |[24] |GROUPEN |Group Function Enable Bit(S) + * | | |0 = The output waveform of each EPWM channel are independent. + * | | |1 = Unify the EPWM_CH2 and EPWM_CH4 to output the same waveform as EPWM_CH0 and unify the EPWM_CH3 and EPWM_CH5 to output the same waveform as EPWM_CH1. + * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect) + * | | |If counter halt is enabled, EPWM all counters will keep current value until exit ICE debug mode. + * | | |0 = ICE debug mode counter halt disable. + * | | |1 = ICE debug mode counter halt enable. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable (Write Protect) + * | | |0 = ICE debug mode acknowledgement effects EPWM output. + * | | |EPWM pin will be forced as tri-state while ICE debug mode acknowledged. + * | | |1 = ICE debug mode acknowledgement disabled. + * | | |EPWM pin will keep output no matter ICE debug mode acknowledged or not. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * @var EPWM_T::CTL1 + * Offset: 0x04 EPWM Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CNTTYPE0 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supports in capture mode). + * | | |01 = Down count type (supports in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[3:2] |CNTTYPE1 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supports in capture mode). + * | | |01 = Down count type (supports in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[5:4] |CNTTYPE2 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supports in capture mode). + * | | |01 = Down count type (supports in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[7:6] |CNTTYPE3 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supports in capture mode). + * | | |01 = Down count type (supports in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[9:8] |CNTTYPE4 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supports in capture mode). + * | | |01 = Down count type (supports in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[11:10] |CNTTYPE5 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supports in capture mode). + * | | |01 = Down count type (supports in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[16] |CNTMODE0 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[17] |CNTMODE1 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[18] |CNTMODE2 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[19] |CNTMODE3 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[20] |CNTMODE4 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[21] |CNTMODE5 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[24] |OUTMODE0 |EPWM Output Mode + * | | |Each bit n controls the output mode of corresponding EPWM channel n. + * | | |0 = EPWM independent mode. + * | | |1 = EPWM complementary mode. + * | | |Note: When operating in group function, these bits must all set to the same mode. + * |[25] |OUTMODE2 |EPWM Output Mode + * | | |Each bit n controls the output mode of corresponding EPWM channel n. + * | | |0 = EPWM independent mode. + * | | |1 = EPWM complementary mode. + * | | |Note: When operating in group function, these bits must all set to the same mode. + * |[26] |OUTMODE4 |EPWM Output Mode + * | | |Each bit n controls the output mode of corresponding EPWM channel n. + * | | |0 = EPWM independent mode. + * | | |1 = EPWM complementary mode. + * | | |Note: When operating in group function, these bits must all set to the same mode. + * @var EPWM_T::SYNC + * Offset: 0x08 EPWM Synchronization Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PHSEN0 |SYNC Phase Enable Bits + * | | |0 = EPWM counter disable to load PHS value. + * | | |1 = EPWM counter enable to load PHS value. + * |[1] |PHSEN2 |SYNC Phase Enable Bits + * | | |0 = EPWM counter disable to load PHS value. + * | | |1 = EPWM counter enable to load PHS value. + * |[2] |PHSEN4 |SYNC Phase Enable Bits + * | | |0 = EPWM counter disable to load PHS value. + * | | |1 = EPWM counter enable to load PHS value. + * |[9:8] |SINSRC0 |EPWM0_SYNC_IN Source Selection + * | | |00 = Synchronize source from SYNC_IN or SWSYNC. + * | | |01 = Counter equal to 0. + * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5. + * | | |11 = SYNC_OUT will not be generated. + * |[11:10] |SINSRC2 |EPWM0_SYNC_IN Source Selection + * | | |00 = Synchronize source from SYNC_IN or SWSYNC. + * | | |01 = Counter equal to 0. + * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5. + * | | |11 = SYNC_OUT will not be generated. + * |[13:12] |SINSRC4 |EPWM0_SYNC_IN Source Selection + * | | |00 = Synchronize source from SYNC_IN or SWSYNC. + * | | |01 = Counter equal to 0. + * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5. + * | | |11 = SYNC_OUT will not be generated. + * |[16] |SNFLTEN |EPWM0_SYNC_IN Noise Filter Enable Bits + * | | |0 = Noise filter of input pin EPWM0_SYNC_IN is Disabled. + * | | |1 = Noise filter of input pin EPWM0_SYNC_IN is Enabled. + * |[19:17] |SFLTCSEL |SYNC Edge Detector Filter Clock Selection + * | | |000 = Filter clock = HCLK. + * | | |001 = Filter clock = HCLK/2. + * | | |010 = Filter clock = HCLK/4. + * | | |011 = Filter clock = HCLK/8. + * | | |100 = Filter clock = HCLK/16. + * | | |101 = Filter clock = HCLK/32. + * | | |110 = Filter clock = HCLK/64. + * | | |111 = Filter clock = HCLK/128. + * |[22:20] |SFLTCNT |SYNC Edge Detector Filter Count + * | | |The register bits control the counter number of edge detector. + * |[23] |SINPINV |SYNC Input Pin Inverse + * | | |0 = The state of pin SYNC is passed to the negative edge detector. + * | | |1 = The inversed state of pin SYNC is passed to the negative edge detector. + * |[24] |PHSDIR0 |EPWM Phase Direction Control + * | | |0 = Control EPWM counter count decrement after synchronizing. + * | | |1 = Control EPWM counter count increment after synchronizing. + * |[25] |PHSDIR2 |EPWM Phase Direction Control + * | | |0 = Control EPWM counter count decrement after synchronizing. + * | | |1 = Control EPWM counter count increment after synchronizing. + * |[26] |PHSDIR4 |EPWM Phase Direction Control + * | | |0 = Control EPWM counter count decrement after synchronizing. + * | | |1 = Control EPWM counter count increment after synchronizing. + * @var EPWM_T::SWSYNC + * Offset: 0x0C EPWM Software Control Synchronization Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SWSYNC0 |Software SYNC Function + * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit. + * |[1] |SWSYNC2 |Software SYNC Function + * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit. + * |[2] |SWSYNC4 |Software SYNC Function + * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit. + * @var EPWM_T::CLKSRC + * Offset: 0x10 EPWM Clock Source Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |ECLKSRC0 |EPWM_CH01 External Clock Source Select + * | | |000 = EPWMx_CLK, x denotes 0 or 1. + * | | |001 = TIMER0 overflow. + * | | |010 = TIMER1 overflow. + * | | |011 = TIMER2 overflow. + * | | |100 = TIMER3 overflow. + * | | |Others = Reserved. + * |[10:8] |ECLKSRC2 |EPWM_CH23 External Clock Source Select + * | | |000 = EPWMx_CLK, x denotes 0 or 1. + * | | |001 = TIMER0 overflow. + * | | |010 = TIMER1 overflow. + * | | |011 = TIMER2 overflow. + * | | |100 = TIMER3 overflow. + * | | |Others = Reserved. + * |[18:16] |ECLKSRC4 |EPWM_CH45 External Clock Source Select + * | | |000 = EPWMx_CLK, x denotes 0 or 1. + * | | |001 = TIMER0 overflow. + * | | |010 = TIMER1 overflow. + * | | |011 = TIMER2 overflow. + * | | |100 = TIMER3 overflow. + * | | |Others = Reserved. + * @var EPWM_T::CLKPSC[3] + * Offset: 0x14 EPWM Clock Prescale Register 0/1, 2/3, 4/5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CLKPSC |EPWM Counter Clock Prescale + * | | |The clock of EPWM counter is decided by clock prescaler + * | | |Each EPWM pair share one EPWM counter clock prescaler + * | | |The clock of EPWM counter is divided by (CLKPSC+ 1) + * @var EPWM_T::CNTEN + * Offset: 0x20 EPWM Counter Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTEN0 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler Stop Running. + * | | |1 = EPWM Counter and clock prescaler Start Running. + * |[1] |CNTEN1 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler Stop Running. + * | | |1 = EPWM Counter and clock prescaler Start Running. + * |[2] |CNTEN2 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler Stop Running. + * | | |1 = EPWM Counter and clock prescaler Start Running. + * |[3] |CNTEN3 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler Stop Running. + * | | |1 = EPWM Counter and clock prescaler Start Running. + * |[4] |CNTEN4 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler Stop Running. + * | | |1 = EPWM Counter and clock prescaler Start Running. + * |[5] |CNTEN5 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler Stop Running. + * | | |1 = EPWM Counter and clock prescaler Start Running. + * @var EPWM_T::CNTCLR + * Offset: 0x24 EPWM Clear Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTCLR0 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * |[1] |CNTCLR1 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * |[2] |CNTCLR2 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * |[3] |CNTCLR3 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * |[4] |CNTCLR4 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * |[5] |CNTCLR5 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * @var EPWM_T::LOAD + * Offset: 0x28 EPWM Load Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LOAD0 |Re-load EPWM Comparator Register (CMPDAT) Control Bit + * | | |This bit is software write, hardware clear when current EPWM period end. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. + * |[1] |LOAD1 |Re-load EPWM Comparator Register (CMPDAT) Control Bit + * | | |This bit is software write, hardware clear when current EPWM period end. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. + * |[2] |LOAD2 |Re-load EPWM Comparator Register (CMPDAT) Control Bit + * | | |This bit is software write, hardware clear when current EPWM period end. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. + * |[3] |LOAD3 |Re-load EPWM Comparator Register (CMPDAT) Control Bit + * | | |This bit is software write, hardware clear when current EPWM period end. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. + * |[4] |LOAD4 |Re-load EPWM Comparator Register (CMPDAT) Control Bit + * | | |This bit is software write, hardware clear when current EPWM period end. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. + * |[5] |LOAD5 |Re-load EPWM Comparator Register (CMPDAT) Control Bit + * | | |This bit is software write, hardware clear when current EPWM period end. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. + * @var EPWM_T::PERIOD[6] + * Offset: 0x30 EPWM Period Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PERIOD |EPWM Period Register + * | | |Up-Count mode: In this mode, EPWM counter counts from 0 to PERIOD, and restarts from 0. + * | | |Down-Count mode: In this mode, EPWM counter counts from PERIOD to 0, and restarts from PERIOD. + * | | |EPWM period time = (PERIOD+1) * EPWM_CLK period. + * | | |Up-Down-Count mode: In this mode, EPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. + * | | |EPWM period time = 2 * PERIOD * EPWM_CLK period. + * @var EPWM_T::CMPDAT[6] + * Offset: 0x50 EPWM Comparator Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMP |EPWM Comparator Register + * | | |CMP use to compare with CNTR to generate EPWM waveform, interrupt and trigger EADC/DAC. + * | | |In independent mode, CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point. + * | | |In complementary mode, CMPDAT0, 2, 4 denote as first compared point, and CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5. + * @var EPWM_T::DTCTL[3] + * Offset: 0x70 EPWM Dead-Time Control Register 0/1,2/3,4/5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |DTCNT |Dead-time Counter (Write Protect) + * | | |The dead-time can be calculated from the following formula: + * | | |Dead-time = (DTCNT[11:0]+1) * EPWM_CLK period. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[16] |DTEN |Enable Dead-time Insertion for EPWM Pair (EPWM_CH0, EPWM_CH1) (EPWM_CH2, EPWM_CH3) (EPWM_CH4, EPWM_CH5) (Write Protect) + * | | |Dead-time insertion is only active when this pair of complementary EPWM is enabled + * | | |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. + * | | |0 = Dead-time insertion Disabled on the pin pair. + * | | |1 = Dead-time insertion Enabled on the pin pair. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[24] |DTCKSEL |Dead-time Clock Select (Write Protect) + * | | |0 = Dead-time clock source from EPWM_CLK. + * | | |1 = Dead-time clock source from prescaler output. + * | | |Note: This register is write protected. Refer toREGWRPROT register. + * @var EPWM_T::PHS[3] + * Offset: 0x80 EPWM Counter Phase Register 0/1,2/3,4/5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PHS |EPWM Synchronous Start Phase Bits + * | | |PHS determines the EPWM synchronous start phase value. These bits only use in synchronous function. + * @var EPWM_T::CNT[6] + * Offset: 0x90 EPWM Counter Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CNT |EPWM Data Register (Read Only) + * | | |User can monitor CNTR to know the current value in 16-bit period counter. + * |[16] |DIRF |EPWM Direction Indicator Flag (Read Only) + * | | |0 = Counter is Down count. + * | | |1 = Counter is UP count. + * @var EPWM_T::WGCTL0 + * Offset: 0xB0 EPWM Generation Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |ZPCTL0 |EPWM Zero Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * | | |EPWM can control output level when EPWM counter count to zero. + * |[3:2] |ZPCTL1 |EPWM Zero Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * | | |EPWM can control output level when EPWM counter count to zero. + * |[5:4] |ZPCTL2 |EPWM Zero Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * | | |EPWM can control output level when EPWM counter count to zero. + * |[7:6] |ZPCTL3 |EPWM Zero Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * | | |EPWM can control output level when EPWM counter count to zero. + * |[9:8] |ZPCTL4 |EPWM Zero Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * | | |EPWM can control output level when EPWM counter count to zero. + * |[11:10] |ZPCTL5 |EPWM Zero Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * | | |EPWM can control output level when EPWM counter count to zero. + * |[17:16] |PRDPCTL0 |EPWM Period (Center) Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |EPWM can control output level when EPWM counter count to (PERIODn+1). + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * |[19:18] |PRDPCTL1 |EPWM Period (Center) Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |EPWM can control output level when EPWM counter count to (PERIODn+1). + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * |[21:20] |PRDPCTL2 |EPWM Period (Center) Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |EPWM can control output level when EPWM counter count to (PERIODn+1). + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * |[23:22] |PRDPCTL3 |EPWM Period (Center) Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |EPWM can control output level when EPWM counter count to (PERIODn+1). + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * |[25:24] |PRDPCTL4 |EPWM Period (Center) Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |EPWM can control output level when EPWM counter count to (PERIODn+1). + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * |[27:26] |PRDPCTL5 |EPWM Period (Center) Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |EPWM can control output level when EPWM counter count to (PERIODn+1). + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * @var EPWM_T::WGCTL1 + * Offset: 0xB4 EPWM Generation Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CMPUCTL0 |EPWM Compare Up Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |EPWM can control output level when EPWM counter up count to CMPDAT. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. + * |[3:2] |CMPUCTL1 |EPWM Compare Up Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |EPWM can control output level when EPWM counter up count to CMPDAT. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. + * |[5:4] |CMPUCTL2 |EPWM Compare Up Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |EPWM can control output level when EPWM counter up count to CMPDAT. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. + * |[7:6] |CMPUCTL3 |EPWM Compare Up Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |EPWM can control output level when EPWM counter up count to CMPDAT. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. + * |[9:8] |CMPUCTL4 |EPWM Compare Up Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |EPWM can control output level when EPWM counter up count to CMPDAT. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. + * |[11:10] |CMPUCTL5 |EPWM Compare Up Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |EPWM can control output level when EPWM counter up count to CMPDAT. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. + * |[17:16] |CMPDCTL0 |EPWM Compare Down Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |EPWM can control output level when EPWM counter down count to CMPDAT. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. + * |[19:18] |CMPDCTL1 |EPWM Compare Down Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |EPWM can control output level when EPWM counter down count to CMPDAT. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. + * |[21:20] |CMPDCTL2 |EPWM Compare Down Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |EPWM can control output level when EPWM counter down count to CMPDAT. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. + * |[23:22] |CMPDCTL3 |EPWM Compare Down Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |EPWM can control output level when EPWM counter down count to CMPDAT. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. + * |[25:24] |CMPDCTL4 |EPWM Compare Down Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |EPWM can control output level when EPWM counter down count to CMPDAT. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. + * |[27:26] |CMPDCTL5 |EPWM Compare Down Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |EPWM can control output level when EPWM counter down count to CMPDAT. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. + * @var EPWM_T::MSKEN + * Offset: 0xB8 EPWM Mask Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKEN0 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled + * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDATn data. + * |[1] |MSKEN1 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled + * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDATn data. + * |[2] |MSKEN2 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled + * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDATn data. + * |[3] |MSKEN3 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled + * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDATn data. + * |[4] |MSKEN4 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled + * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDATn data. + * |[5] |MSKEN5 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled + * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDATn data. + * @var EPWM_T::MSK + * Offset: 0xBC EPWM Mask Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKDAT0 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM channel n. + * | | |1 = Output logic high to EPWM channel n. + * |[1] |MSKDAT1 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM channel n. + * | | |1 = Output logic high to EPWM channel n. + * |[2] |MSKDAT2 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM channel n. + * | | |1 = Output logic high to EPWM channel n. + * |[3] |MSKDAT3 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM channel n. + * | | |1 = Output logic high to EPWM channel n. + * |[4] |MSKDAT4 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM channel n. + * | | |1 = Output logic high to EPWM channel n. + * |[5] |MSKDAT5 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM channel n. + * | | |1 = Output logic high to EPWM channel n. + * @var EPWM_T::BNF + * Offset: 0xC0 EPWM Brake Noise Filter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRK0NFEN |EPWM Brake 0 Noise Filter Enable Bit + * | | |0 = Noise filter of EPWM Brake 0 Disabled. + * | | |1 = Noise filter of EPWM Brake 0 Enabled. + * |[3:1] |BRK0NFSEL |Brake 0 Edge Detector Filter Clock Selection + * | | |000 = Filter clock = HCLK. + * | | |001 = Filter clock = HCLK/2. + * | | |010 = Filter clock = HCLK/4. + * | | |011 = Filter clock = HCLK/8. + * | | |100 = Filter clock = HCLK/16. + * | | |101 = Filter clock = HCLK/32. + * | | |110 = Filter clock = HCLK/64. + * | | |111 = Filter clock = HCLK/128. + * |[6:4] |BRK0FCNT |Brake 0 Edge Detector Filter Count + * | | |The register bits control the Brake0 filter counter to count from 0 to BRK1FCNT. + * |[7] |BRK0PINV |Brake 0 Pin Inverse + * | | |0 = The state of pin EPWMx_BRAKE0 is passed to the negative edge detector. + * | | |1 = The inversed state of pin EPWMx_BRAKE10 is passed to the negative edge detector. + * |[8] |BRK1NFEN |EPWM Brake 1 Noise Filter Enable Bit + * | | |0 = Noise filter of EPWM Brake 1 Disabled. + * | | |1 = Noise filter of EPWM Brake 1 Enabled. + * |[11:9] |BRK1NFSEL |Brake 1 Edge Detector Filter Clock Selection + * | | |000 = Filter clock = HCLK. + * | | |001 = Filter clock = HCLK/2. + * | | |010 = Filter clock = HCLK/4. + * | | |011 = Filter clock = HCLK/8. + * | | |100 = Filter clock = HCLK/16. + * | | |101 = Filter clock = HCLK/32. + * | | |110 = Filter clock = HCLK/64. + * | | |111 = Filter clock = HCLK/128. + * |[14:12] |BRK1FCNT |Brake 1 Edge Detector Filter Count + * | | |The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT. + * |[15] |BRK1PINV |Brake 1 Pin Inverse + * | | |0 = The state of pin EPWMx_BRAKE1 is passed to the negative edge detector. + * | | |1 = The inversed state of pin EPWMx_BRAKE1 is passed to the negative edge detector. + * |[16] |BK0SRC |Brake 0 Pin Source Select + * | | |For EPWM0 setting: + * | | |0 = Brake 0 pin source come from EPWM0_BRAKE0. + * | | |1 = Brake 0 pin source come from EPWM1_BRAKE0. + * | | |For EPWM1 setting: + * | | |0 = Brake 0 pin source come from EPWM1_BRAKE0. + * | | |1 = Brake 0 pin source come from EPWM0_BRAKE0. + * |[24] |BK1SRC |Brake 1 Pin Source Select + * | | |For EPWM0 setting: + * | | |0 = Brake 1 pin source come from EPWM0_BRAKE1. + * | | |1 = Brake 1 pin source come from EPWM1_BRAKE1. + * | | |For EPWM1 setting: + * | | |0 = Brake 1 pin source come from EPWM1_BRAKE1. + * | | |1 = Brake 1 pin source come from EPWM0_BRAKE1. + * @var EPWM_T::FAILBRK + * Offset: 0xC4 EPWM System Fail Brake Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CSSBRKEN |Clock Security System Detection Trigger EPWM Brake Function 0 Enable Bit + * | | |0 = Brake Function triggered by CSS detection Disabled. + * | | |1 = Brake Function triggered by CSS detection Enabled. + * |[1] |BODBRKEN |Brown-out Detection Trigger EPWM Brake Function 0 Enable Bit + * | | |0 = Brake Function triggered by BOD Disabled. + * | | |1 = Brake Function triggered by BOD Enabled. + * |[2] |RAMBRKEN |SRAM Parity Error Detection Trigger EPWM Brake Function 0 Enable Bit + * | | |0 = Brake Function triggered by SRAM parity error detection Disabled. + * | | |1 = Brake Function triggered by SRAM parity error detection Enabled. + * |[3] |CORBRKEN |Core Lockup Detection Trigger EPWM Brake Function 0 Enable Bit + * | | |0 = Brake Function triggered by Core lockup detection Disabled. + * | | |1 = Brake Function triggered by Core lockup detection Enabled. + * @var EPWM_T::BRKCTL[3] + * Offset: 0xC8 EPWM Brake Edge Detect Control Register 0/1,2/3,4/5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CPO0EBEN |Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect) + * | | |0 = ACMP0_O as edge-detect brake source Disabled. + * | | |1 = ACMP0_O as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[1] |CPO1EBEN |Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect) + * | | |0 = ACMP1_O as edge-detect brake source Disabled. + * | | |1 = ACMP1_O as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[4] |BRKP0EEN |Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect) + * | | |0 = EPWMx_BRAKE0 pin as edge-detect brake source Disabled. + * | | |1 = EPWMx_BRAKE0 pin as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[5] |BRKP1EEN |Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect) + * | | |0 = EPWMx_BRAKE1 pin as edge-detect brake source Disabled. + * | | |1 = EPWMx_BRAKE1 pin as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[7] |SYSEBEN |Enable System Fail As Edge-detect Brake Source (Write Protect) + * | | |0 = System Fail condition as edge-detect brake source Disabled. + * | | |1 = System Fail condition as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[8] |CPO0LBEN |Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect) + * | | |0 = ACMP0_O as level-detect brake source Disabled. + * | | |1 = ACMP0_O as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[9] |CPO1LBEN |Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect) + * | | |0 = ACMP1_O as level-detect brake source Disabled. + * | | |1 = ACMP1_O as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[12] |BRKP0LEN |Enable BKP0 Pin As Level-detect Brake Source (Write Protect) + * | | |0 = EPWMx_BRAKE0 pin as level-detect brake source Disabled. + * | | |1 = EPWMx_BRAKE0 pin as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[13] |BRKP1LEN |Enable BKP1 Pin As Level-detect Brake Source (Write Protect) + * | | |0 = EPWMx_BRAKE1 pin as level-detect brake source Disabled. + * | | |1 = EPWMx_BRAKE1 pin as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[15] |SYSLBEN |Enable System Fail As Level-detect Brake Source (Write Protect) + * | | |0 = System Fail condition as level-detect brake source Disabled. + * | | |1 = System Fail condition as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[17:16] |BRKAEVEN |EPWM Brake Action Select for Even Channel (Write Protect) + * | | |00 = EPWMx brake event will not affect even channels output. + * | | |01 = EPWM even channel output tri-state when EPWMx brake event happened. + * | | |10 = EPWM even channel output low level when EPWMx brake event happened. + * | | |11 = EPWM even channel output high level when EPWMx brake event happened. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[19:18] |BRKAODD |EPWM Brake Action Select for Odd Channel (Write Protect) + * | | |00 = EPWMx brake event will not affect odd channels output. + * | | |01 = EPWM odd channel output tri-state when EPWMx brake event happened. + * | | |10 = EPWM odd channel output low level when EPWMx brake event happened. + * | | |11 = EPWM odd channel output high level when EPWMx brake event happened. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[20] |EADCEBEN |Enable EADC Result Monitor (EADCRM) As Edge-detect Brake Source (Write Protect) + * | | |0 = EADCRM as edge-detect brake source Disabled. + * | | |1 = EADCRM as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[28] |EADCLBEN |Enable EADC Result Monitor (EADCRM) As Level-detect Brake Source (Write Protect) + * | | |0 = EADCRM as level-detect brake source Disabled. + * | | |1 = EADCRM as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * @var EPWM_T::POLCTL + * Offset: 0xD4 EPWM Pin Polar Inverse Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PINV0 |EPWM PIN Polar Inverse Control + * | | |The register controls polarity state of EPWM output. + * | | |0 = EPWM output polar inverse Disabled. + * | | |1 = EPWM output polar inverse Enabled. + * |[1] |PINV1 |EPWM PIN Polar Inverse Control + * | | |The register controls polarity state of EPWM output. + * | | |0 = EPWM output polar inverse Disabled. + * | | |1 = EPWM output polar inverse Enabled. + * |[2] |PINV2 |EPWM PIN Polar Inverse Control + * | | |The register controls polarity state of EPWM output. + * | | |0 = EPWM output polar inverse Disabled. + * | | |1 = EPWM output polar inverse Enabled. + * |[3] |PINV3 |EPWM PIN Polar Inverse Control + * | | |The register controls polarity state of EPWM output. + * | | |0 = EPWM output polar inverse Disabled. + * | | |1 = EPWM output polar inverse Enabled. + * |[4] |PINV4 |EPWM PIN Polar Inverse Control + * | | |The register controls polarity state of EPWM output. + * | | |0 = EPWM output polar inverse Disabled. + * | | |1 = EPWM output polar inverse Enabled. + * |[5] |PINV5 |EPWM PIN Polar Inverse Control + * | | |The register controls polarity state of EPWM output. + * | | |0 = EPWM output polar inverse Disabled. + * | | |1 = EPWM output polar inverse Enabled. + * @var EPWM_T::POEN + * Offset: 0xD8 EPWM Output Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |POEN0 |EPWM Pin Output Enable Bits + * | | |0 = EPWM pin at tri-state. + * | | |1 = EPWM pin in output mode. + * |[1] |POEN1 |EPWM Pin Output Enable Bits + * | | |0 = EPWM pin at tri-state. + * | | |1 = EPWM pin in output mode. + * |[2] |POEN2 |EPWM Pin Output Enable Bits + * | | |0 = EPWM pin at tri-state. + * | | |1 = EPWM pin in output mode. + * |[3] |POEN3 |EPWM Pin Output Enable Bits + * | | |0 = EPWM pin at tri-state. + * | | |1 = EPWM pin in output mode. + * |[4] |POEN4 |EPWM Pin Output Enable Bits + * | | |0 = EPWM pin at tri-state. + * | | |1 = EPWM pin in output mode. + * |[5] |POEN5 |EPWM Pin Output Enable Bits + * | | |0 = EPWM pin at tri-state. + * | | |1 = EPWM pin in output mode. + * @var EPWM_T::SWBRK + * Offset: 0xDC EPWM Software Brake Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKETRG0 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[1] |BRKETRG2 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[2] |BRKETRG4 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[8] |BRKLTRG0 |EPWM Level Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[9] |BRKLTRG2 |EPWM Level Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[10] |BRKLTRG4 |EPWM Level Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * @var EPWM_T::INTEN0 + * Offset: 0xE0 EPWM Interrupt Enable Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIEN0 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[1] |ZIEN1 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[2] |ZIEN2 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[3] |ZIEN3 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[4] |ZIEN4 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[5] |ZIEN5 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[8] |PIEN0 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note1: When up-down counter type period point means center point. + * | | |Note2: Odd channels will read always 0 at complementary mode. + * |[9] |PIEN1 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note1: When up-down counter type period point means center point. + * | | |Note2: Odd channels will read always 0 at complementary mode. + * |[10] |PIEN2 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note1: When up-down counter type period point means center point. + * | | |Note2: Odd channels will read always 0 at complementary mode. + * |[11] |PIEN3 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note1: When up-down counter type period point means center point. + * | | |Note2: Odd channels will read always 0 at complementary mode. + * |[12] |PIEN4 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note1: When up-down counter type period point means center point. + * | | |Note2: Odd channels will read always 0 at complementary mode. + * |[13] |PIEN5 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note1: When up-down counter type period point means center point. + * | | |Note2: Odd channels will read always 0 at complementary mode. + * |[16] |CMPUIEN0 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. + * |[17] |CMPUIEN1 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. + * |[18] |CMPUIEN2 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. + * |[19] |CMPUIEN3 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. + * |[20] |CMPUIEN4 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. + * |[21] |CMPUIEN5 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. + * |[24] |CMPDIEN0 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. + * |[25] |CMPDIEN1 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. + * |[26] |CMPDIEN2 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. + * |[27] |CMPDIEN3 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. + * |[28] |CMPDIEN4 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. + * |[29] |CMPDIEN5 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. + * @var EPWM_T::INTEN1 + * Offset: 0xE4 EPWM Interrupt Enable Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKEIEN0_1|EPWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect) + * | | |0 = Edge-detect Brake interrupt for channel0/1 Disabled. + * | | |1 = Edge-detect Brake interrupt for channel0/1 Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[1] |BRKEIEN2_3|EPWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect) + * | | |0 = Edge-detect Brake interrupt for channel2/3 Disabled. + * | | |1 = Edge-detect Brake interrupt for channel2/3 Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[2] |BRKEIEN4_5|EPWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect) + * | | |0 = Edge-detect Brake interrupt for channel4/5 Disabled. + * | | |1 = Edge-detect Brake interrupt for channel4/5 Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[8] |BRKLIEN0_1|EPWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect) + * | | |0 = Level-detect Brake interrupt for channel0/1 Disabled. + * | | |1 = Level-detect Brake interrupt for channel0/1 Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[9] |BRKLIEN2_3|EPWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect) + * | | |0 = Level-detect Brake interrupt for channel2/3 Disabled. + * | | |1 = Level-detect Brake interrupt for channel2/3 Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[10] |BRKLIEN4_5|EPWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect) + * | | |0 = Level-detect Brake interrupt for channel4/5 Disabled. + * | | |1 = Level-detect Brake interrupt for channel4/5 Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * @var EPWM_T::INTSTS0 + * Offset: 0xE8 EPWM Interrupt Flag Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIF0 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. + * |[1] |ZIF1 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. + * |[2] |ZIF2 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. + * |[3] |ZIF3 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. + * |[4] |ZIF4 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. + * |[5] |ZIF5 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. + * |[8] |PIF0 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero. + * |[9] |PIF1 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero. + * |[10] |PIF2 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero. + * |[11] |PIF3 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero. + * |[12] |PIF4 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero. + * |[13] |PIF5 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero. + * |[16] |CMPUIF0 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. + * |[17] |CMPUIF1 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. + * |[18] |CMPUIF2 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. + * |[19] |CMPUIF3 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. + * |[20] |CMPUIF4 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. + * |[21] |CMPUIF5 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. + * |[24] |CMPDIF0 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. + * |[25] |CMPDIF1 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. + * |[26] |CMPDIF2 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. + * |[27] |CMPDIF3 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. + * |[28] |CMPDIF4 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. + * |[29] |CMPDIF5 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. + * @var EPWM_T::INTSTS1 + * Offset: 0xEC EPWM Interrupt Flag Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKEIF0 |EPWM Channel0 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel0 edge-detect brake event do not happened. + * | | |1 = When EPWM channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[1] |BRKEIF1 |EPWM Channel1 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel1 edge-detect brake event do not happened. + * | | |1 = When EPWM channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[2] |BRKEIF2 |EPWM Channel2 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel2 edge-detect brake event do not happened. + * | | |1 = When EPWM channel2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[3] |BRKEIF3 |EPWM Channel3 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel3 edge-detect brake event do not happened. + * | | |1 = When EPWM channel3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[4] |BRKEIF4 |EPWM Channel4 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel4 edge-detect brake event do not happened. + * | | |1 = When EPWM channel4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[5] |BRKEIF5 |EPWM Channel5 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel5 edge-detect brake event do not happened. + * | | |1 = When EPWM channel5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[8] |BRKLIF0 |EPWM Channel0 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel0 level-detect brake event do not happened. + * | | |1 = When EPWM channel0 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[9] |BRKLIF1 |EPWM Channel1 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel1 level-detect brake event do not happened. + * | | |1 = When EPWM channel1 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[10] |BRKLIF2 |EPWM Channel2 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel2 level-detect brake event do not happened. + * | | |1 = When EPWM channel2 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[11] |BRKLIF3 |EPWM Channel3 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel3 level-detect brake event do not happened. + * | | |1 = When EPWM channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[12] |BRKLIF4 |EPWM Channel4 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel4 level-detect brake event do not happened. + * | | |1 = When EPWM channel4 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[13] |BRKLIF5 |EPWM Channel5 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel5 level-detect brake event do not happened. + * | | |1 = When EEPWM channel5 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[16] |BRKESTS0 |EPWM Channel0 Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel0 edge-detect brake state is released. + * | | |1 = When EPWM channel0 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel0 at brake state, writing 1 to clear. + * |[17] |BRKESTS1 |EPWM Channel1 Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel1 edge-detect brake state is released. + * | | |1 = When EPWM channel1 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel1 at brake state, writing 1 to clear. + * |[18] |BRKESTS2 |EPWM Channel2 Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel2 edge-detect brake state is released. + * | | |1 = When EPWM channel2 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel2 at brake state, writing 1 to clear. + * |[19] |BRKESTS3 |EPWM Channel3 Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel3 edge-detect brake state is released. + * | | |1 = When EPWM channel3 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel3 at brake state, writing 1 to clear. + * |[20] |BRKESTS4 |EPWM Channel4 Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel4 edge-detect brake state is released. + * | | |1 = When EPWM channel4 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel4 at brake state, writing 1 to clear. + * |[21] |BRKESTS5 |EPWM Channel5 Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel5 edge-detect brake state is released. + * | | |1 = When EPWM channel5 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel5 at brake state, writing 1 to clear. + * |[24] |BRKLSTS0 |EPWM Channel0 Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel0 level-detect brake state is released. + * | | |1 = When EPWM channel0 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel0 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[25] |BRKLSTS1 |EPWM Channel1 Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel1 level-detect brake state is released. + * | | |1 = When EPWM channel1 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel1 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[26] |BRKLSTS2 |EPWM Channel2 Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel2 level-detect brake state is released. + * | | |1 = When EPWM channel2 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel2 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[27] |BRKLSTS3 |EPWM Channel3 Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel3 level-detect brake state is released. + * | | |1 = When EPWM channel3 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel3 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[28] |BRKLSTS4 |EPWM Channel4 Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel4 level-detect brake state is released. + * | | |1 = When EPWM channel4 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel4 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[29] |BRKLSTS5 |EPWM Channel5 Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel5 level-detect brake state is released. + * | | |1 = When EPWM channel5 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel5 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * @var EPWM_T::DACTRGEN + * Offset: 0xF4 EPWM Trigger DAC Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZTE0 |EPWM Zero Point Trigger DAC Enable Bits + * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[1] |ZTE1 |EPWM Zero Point Trigger DAC Enable Bits + * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[2] |ZTE2 |EPWM Zero Point Trigger DAC Enable Bits + * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[3] |ZTE3 |EPWM Zero Point Trigger DAC Enable Bits + * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[4] |ZTE4 |EPWM Zero Point Trigger DAC Enable Bits + * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[5] |ZTE5 |EPWM Zero Point Trigger DAC Enable Bits + * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[8] |PTE0 |EPWM Period Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[9] |PTE1 |EPWM Period Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[10] |PTE2 |EPWM Period Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[11] |PTE3 |EPWM Period Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[12] |PTE4 |EPWM Period Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[13] |PTE5 |EPWM Period Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[16] |CUTRGE0 |EPWM Compare Up Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Up point trigger DAC function Disabled. + * | | |1 = EPWM Compare Up point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. + * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. + * |[17] |CUTRGE1 |EPWM Compare Up Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Up point trigger DAC function Disabled. + * | | |1 = EPWM Compare Up point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. + * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. + * |[18] |CUTRGE2 |EPWM Compare Up Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Up point trigger DAC function Disabled. + * | | |1 = EPWM Compare Up point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. + * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. + * |[19] |CUTRGE3 |EPWM Compare Up Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Up point trigger DAC function Disabled. + * | | |1 = EPWM Compare Up point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. + * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. + * |[20] |CUTRGE4 |EPWM Compare Up Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Up point trigger DAC function Disabled. + * | | |1 = EPWM Compare Up point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. + * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. + * |[21] |CUTRGE5 |EPWM Compare Up Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Up point trigger DAC function Disabled. + * | | |1 = EPWM Compare Up point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. + * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. + * |[24] |CDTRGE0 |EPWM Compare Down Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. + * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. + * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. + * |[25] |CDTRGE1 |EPWM Compare Down Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. + * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. + * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. + * |[26] |CDTRGE2 |EPWM Compare Down Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. + * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. + * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. + * |[27] |CDTRGE3 |EPWM Compare Down Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. + * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. + * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. + * |[28] |CDTRGE4 |EPWM Compare Down Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. + * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. + * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. + * |[29] |CDTRGE5 |EPWM Compare Down Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. + * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. + * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. + * @var EPWM_T::EADCTS0 + * Offset: 0xF8 EPWM Trigger EADC Source Select Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |TRGSEL0 |EPWM_CH0 Trigger EADC Source Select + * | | |0000 = EPWM_CH0 zero point. + * | | |0001 = EPWM_CH0 period point. + * | | |0010 = EPWM_CH0 zero or period point. + * | | |0011 = EPWM_CH0 up-count CMPDAT point. + * | | |0100 = EPWM_CH0 down-count CMPDAT point. + * | | |0101 = EPWM_CH1 zero point. + * | | |0110 = EPWM_CH1 period point. + * | | |0111 = EPWM_CH1 zero or period point. + * | | |1000 = EPWM_CH1 up-count CMPDAT point. + * | | |1001 = EPWM_CH1 down-count CMPDAT point. + * | | |1010 = EPWM_CH0 up-count free CMPDAT point. + * | | |1011 = EPWM_CH0 down-count free CMPDAT point. + * | | |1100 = EPWM_CH2 up-count free CMPDAT point. + * | | |1101 = EPWM_CH2 down-count free CMPDAT point. + * | | |1110 = EPWM_CH4 up-count free CMPDAT point. + * | | |1111 = EPWM_CH4 down-count free CMPDAT point. + * |[7] |TRGEN0 |EPWM_CH0 Trigger EADC enable bit + * |[11:8] |TRGSEL1 |EPWM_CH1 Trigger EADC Source Select + * | | |0000 = EPWM_CH0 zero point. + * | | |0001 = EPWM_CH0 period point. + * | | |0010 = EPWM_CH0 zero or period point. + * | | |0011 = EPWM_CH0 up-count CMPDAT point. + * | | |0100 = EPWM_CH0 down-count CMPDAT point. + * | | |0101 = EPWM_CH1 zero point. + * | | |0110 = EPWM_CH1 period point. + * | | |0111 = EPWM_CH1 zero or period point. + * | | |1000 = EPWM_CH1 up-count CMPDAT point. + * | | |1001 = EPWM_CH1 down-count CMPDAT point. + * | | |1010 = EPWM_CH0 up-count free CMPDAT point. + * | | |1011 = EPWM_CH0 down-count free CMPDAT point. + * | | |1100 = EPWM_CH2 up-count free CMPDAT point. + * | | |1101 = EPWM_CH2 down-count free CMPDAT point. + * | | |1110 = EPWM_CH4 up-count free CMPDAT point. + * | | |1111 = EPWM_CH4 down-count free CMPDAT point. + * |[15] |TRGEN1 |EPWM_CH1 Trigger EADC enable bit + * |[19:16] |TRGSEL2 |EPWM_CH2 Trigger EADC Source Select + * | | |0000 = EPWM_CH2 zero point. + * | | |0001 = EPWM_CH2 period point. + * | | |0010 = EPWM_CH2 zero or period point. + * | | |0011 = EPWM_CH2 up-count CMPDAT point. + * | | |0100 = EPWM_CH2 down-count CMPDAT point. + * | | |0101 = EPWM_CH3 zero point. + * | | |0110 = EPWM_CH3 period point. + * | | |0111 = EPWM_CH3 zero or period point. + * | | |1000 = EPWM_CH3 up-count CMPDAT point. + * | | |1001 = EPWM_CH3 down-count CMPDAT point. + * | | |1010 = EPWM_CH0 up-count free CMPDAT point. + * | | |1011 = EPWM_CH0 down-count free CMPDAT point. + * | | |1100 = EPWM_CH2 up-count free CMPDAT point. + * | | |1101 = EPWM_CH2 down-count free CMPDAT point. + * | | |1110 = EPWM_CH4 up-count free CMPDAT point. + * | | |1111 = EPWM_CH4 down-count free CMPDAT point. + * |[23] |TRGEN2 |EPWM_CH2 Trigger EADC enable bit + * |[27:24] |TRGSEL3 |EPWM_CH3 Trigger EADC Source Select + * | | |0000 = EPWM_CH2 zero point. + * | | |0001 = EPWM_CH2 period point. + * | | |0010 = EPWM_CH2 zero or period point. + * | | |0011 = EPWM_CH2 up-count CMPDAT point. + * | | |0100 = EPWM_CH2 down-count CMPDAT point. + * | | |0101 = EPWM_CH3 zero point. + * | | |0110 = EPWM_CH3 period point. + * | | |0111 = EPWM_CH3 zero or period point. + * | | |1000 = EPWM_CH3 up-count CMPDAT point. + * | | |1001 = EPWM_CH3 down-count CMPDAT point. + * | | |1010 = EPWM_CH0 up-count free CMPDAT point. + * | | |1011 = EPWM_CH0 down-count free CMPDAT point. + * | | |1100 = EPWM_CH2 up-count free CMPDAT point. + * | | |1101 = EPWM_CH2 down-count free CMPDAT point. + * | | |1110 = EPWM_CH4 up-count free CMPDAT point. + * | | |1111 = EPWM_CH4 down-count free CMPDAT point. + * |[31] |TRGEN3 |EPWM_CH3 Trigger EADC enable bit + * @var EPWM_T::EADCTS1 + * Offset: 0xFC EPWM Trigger EADC Source Select Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |TRGSEL4 |EPWM_CH4 Trigger EADC Source Select + * | | |0000 = EPWM_CH4 zero point. + * | | |0001 = EPWM_CH4 period point. + * | | |0010 = EPWM_CH4 zero or period point. + * | | |0011 = EPWM_CH4 up-count CMPDAT point. + * | | |0100 = EPWM_CH4 down-count CMPDAT point. + * | | |0101 = EPWM_CH5 zero point. + * | | |0110 = EPWM_CH5 period point. + * | | |0111 = EPWM_CH5 zero or period point. + * | | |1000 = EPWM_CH5 up-count CMPDAT point. + * | | |1001 = EPWM_CH5 down-count CMPDAT point. + * | | |1010 = EPWM_CH0 up-count free CMPDAT point. + * | | |1011 = EPWM_CH0 down-count free CMPDAT point. + * | | |1100 = EPWM_CH2 up-count free CMPDAT point. + * | | |1101 = EPWM_CH2 down-count free CMPDAT point. + * | | |1110 = EPWM_CH4 up-count free CMPDAT point. + * | | |1111 = EPWM_CH4 down-count free CMPDAT point. + * |[7] |TRGEN4 |EPWM_CH4 Trigger EADC enable bit + * |[11:8] |TRGSEL5 |EPWM_CH5 Trigger EADC Source Select + * | | |0000 = EPWM_CH4 zero point. + * | | |0001 = EPWM_CH4 period point. + * | | |0010 = EPWM_CH4 zero or period point. + * | | |0011 = EPWM_CH4 up-count CMPDAT point. + * | | |0100 = EPWM_CH4 down-count CMPDAT point. + * | | |0101 = EPWM_CH5 zero point. + * | | |0110 = EPWM_CH5 period point. + * | | |0111 = EPWM_CH5 zero or period point. + * | | |1000 = EPWM_CH5 up-count CMPDAT point. + * | | |1001 = EPWM_CH5 down-count CMPDAT point. + * | | |1010 = EPWM_CH0 up-count free CMPDAT point. + * | | |1011 = EPWM_CH0 down-count free CMPDAT point. + * | | |1100 = EPWM_CH2 up-count free CMPDAT point. + * | | |1101 = EPWM_CH2 down-count free CMPDAT point. + * | | |1110 = EPWM_CH4 up-count free CMPDAT point. + * | | |1111 = EPWM_CH4 down-count free CMPDAT point. + * |[15] |TRGEN5 |EPWM_CH5 Trigger EADC enable bit + * @var EPWM_T::FTCMPDAT[3] + * Offset: 0x100 EPWM Free Trigger Compare Register 0/1,2/3,4/5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FTCMP |EPWM Free Trigger Compare Register + * | | |FTCMP use to compare with even CNTR to trigger EADC + * | | |FTCMPDAT0, 2, 4 corresponding complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5. + * @var EPWM_T::SSCTL + * Offset: 0x110 EPWM Synchronous Start Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SSEN0 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[1] |SSEN1 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[2] |SSEN2 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[3] |SSEN3 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[4] |SSEN4 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[5] |SSEN5 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[9:8] |SSRC |EPWM Synchronous Start Source Select Bits + * | | |00 = Synchronous start source come from EPWM0. + * | | |01 = Synchronous start source come from EPWM1. + * | | |10 = Synchronous start source come from BPWM0. + * | | |11 = Synchronous start source come from BPWM1. + * @var EPWM_T::SSTRG + * Offset: 0x114 EPWM Synchronous Start Trigger Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTSEN |EPWM Counter Synchronous Start Enable (Write Only) + * | | |PMW counter synchronous enable function is used to make selected EPWM channels (include EPWM0_CHx and EPWM1_CHx) start counting at the same time. + * | | |Writing this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated EPWM channel counter synchronous start function is enabled. + * @var EPWM_T::LEBCTL + * Offset: 0x118 EPWM Leading Edge Blanking Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LEBEN |EPWM Leading Edge Blanking Enable Bit + * | | |0 = EPWM Leading Edge Blanking Disabled. + * | | |1 = EPWM Leading Edge Blanking Enabled. + * |[8] |SRCEN0 |EPWM Leading Edge Blanking Source From EPWM_CH0 Enable Bit + * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH0 Disabled. + * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH0 Enabled. + * |[9] |SRCEN2 |EPWM Leading Edge Blanking Source From EPWM_CH2 Enable Bit + * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH2 Disabled. + * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH2 Enabled. + * |[10] |SRCEN4 |EPWM Leading Edge Blanking Source From EPWM_CH4 Enable Bit + * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH4 Disabled. + * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH4 Enabled. + * |[17:16] |TRGTYPE |EPWM Leading Edge Blanking Trigger Type + * | | |0 = When detect leading edge blanking source rising edge, blanking counter start counting. + * | | |1 = When detect leading edge blanking source falling edge, blanking counter start counting. + * | | |2 = When detect leading edge blanking source rising or falling edge, blanking counter start counting. + * | | |3 = Reserved. + * @var EPWM_T::LEBCNT + * Offset: 0x11C EPWM Leading Edge Blanking Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |LEBCNT |EPWM Leading Edge Blanking Counter + * | | |This counter value decides leading edge blanking window size + * | | |Blanking window size = LEBCNT+1, and LEB counter clock base is ECLK. + * @var EPWM_T::STATUS + * Offset: 0x120 EPWM Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTMAXF0 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. + * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. + * |[1] |CNTMAXF1 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. + * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. + * |[2] |CNTMAXF2 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. + * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. + * |[3] |CNTMAXF3 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. + * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. + * |[4] |CNTMAXF4 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. + * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. + * |[5] |CNTMAXF5 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. + * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. + * |[8] |SYNCINF0 |Input Synchronization Latched Flag + * | | |0 = Indicates no SYNC_IN event has occurred. + * | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit. + * |[9] |SYNCINF2 |Input Synchronization Latched Flag + * | | |0 = Indicates no SYNC_IN event has occurred. + * | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit. + * |[10] |SYNCINF4 |Input Synchronization Latched Flag + * | | |0 = Indicates no SYNC_IN event has occurred. + * | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit. + * |[16] |EADCTRGF0 |EADC Start of Conversion Flag + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[17] |EADCTRGF1 |EADC Start of Conversion Flag + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[18] |EADCTRGF2 |EADC Start of Conversion Flag + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[19] |EADCTRGF3 |EADC Start of Conversion Flag + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[20] |EADCTRGF4 |EADC Start of Conversion Flag + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[21] |EADCTRGF5 |EADC Start of Conversion Flag + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[24] |DACTRGF |DAC Start of Conversion Flag + * | | |0 = Indicates no DAC start of conversion trigger event has occurred. + * | | |1 = Indicates an DAC start of conversion trigger event has occurred, software can write 1 to clear this bit + * @var EPWM_T::IFA[6] + * Offset: 0x130 EPWM Interrupt Flag Accumulator Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |IFACNT |EPWM_CHn Interrupt Flag Counter + * | | |The register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt. + * | | |EPWM flag will be set in every IFACNT[15:0] times of EPWM period. + * |[24] |STPMOD |EPWM_CHn Interrupt Flag Accumulator Stop Mode Enable Bits + * | | |0 = EPWM_CHn interrupt flag accumulator stop mode disable. + * | | |1 = EPWM_CHn interrupt flag accumulator stop mode enable. + * |[29:28] |IFASEL |EPWM_CHn Interrupt Flag Accumulator Source Select + * | | |00 = CNT equal to Zero in channel n. + * | | |01 = CNT equal to PERIOD in channel n. + * | | |10 = CNT equal to CMPU in channel n. + * | | |11 = CNT equal to CMPD in channel n. + * |[31] |IFAEN |EPWM_CHn Interrupt Flag Accumulator Enable Bits + * | | |0 = EPWM_CHn interrupt flag accumulator disable. + * | | |1 = EPWM_CHn interrupt flag accumulator enable. + * @var EPWM_T::AINTSTS + * Offset: 0x150 EPWM Accumulator Interrupt Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |IFAIF0 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * |[1] |IFAIF1 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * |[2] |IFAIF2 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * |[3] |IFAIF3 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * |[4] |IFAIF4 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * |[5] |IFAIF5 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * @var EPWM_T::AINTEN + * Offset: 0x154 EPWM Accumulator Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |IFAIEN0 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * |[1] |IFAIEN1 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * |[2] |IFAIEN2 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * |[3] |IFAIEN3 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * |[4] |IFAIEN4 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * |[5] |IFAIEN5 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * @var EPWM_T::APDMACTL + * Offset: 0x158 EPWM Accumulator PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |APDMAEN0 |Channel N Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * |[1] |APDMAEN1 |Channel N Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * |[2] |APDMAEN2 |Channel N Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * |[3] |APDMAEN3 |Channel N Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * |[4] |APDMAEN4 |Channel N Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * |[5] |APDMAEN5 |Channel N Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * @var EPWM_T::CAPINEN + * Offset: 0x200 EPWM Capture Input Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPINEN0 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * |[1] |CAPINEN1 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * |[2] |CAPINEN2 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * |[3] |CAPINEN3 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * |[4] |CAPINEN4 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * |[5] |CAPINEN5 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * @var EPWM_T::CAPCTL + * Offset: 0x204 EPWM Capture Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPEN0 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[1] |CAPEN1 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[2] |CAPEN2 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[3] |CAPEN3 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[4] |CAPEN4 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[5] |CAPEN5 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[8] |CAPINV0 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[9] |CAPINV1 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[10] |CAPINV2 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[11] |CAPINV3 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[12] |CAPINV4 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[13] |CAPINV5 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[16] |RCRLDEN0 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[17] |RCRLDEN1 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[18] |RCRLDEN2 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[19] |RCRLDEN3 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[20] |RCRLDEN4 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[21] |RCRLDEN5 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[24] |FCRLDEN0 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[25] |FCRLDEN1 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[26] |FCRLDEN2 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[27] |FCRLDEN3 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[28] |FCRLDEN4 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[29] |FCRLDEN5 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * @var EPWM_T::CAPSTS + * Offset: 0x208 EPWM Capture Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CRLIFOV0 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[1] |CRLIFOV1 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[2] |CRLIFOV2 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[3] |CRLIFOV3 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[4] |CRLIFOV4 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[5] |CRLIFOV5 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[8] |CFLIFOV0 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * |[9] |CFLIFOV1 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * |[10] |CFLIFOV2 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * |[11] |CFLIFOV3 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * |[12] |CFLIFOV4 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * |[13] |CFLIFOV5 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * @var EPWM_T::PDMACTL + * Offset: 0x23C EPWM PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CHEN0_1 |Channel 0/1 PDMA Enable + * | | |0 = Channel 0/1 PDMA function Disabled. + * | | |1 = Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory. + * |[2:1] |CAPMOD0_1 |Select EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 to Do PDMA Transfer + * | | |00 = Reserved. + * | | |01 = EPWM_RCAPDAT0/1. + * | | |10 = EPWM_FCAPDAT0/1. + * | | |11 = Both EPWM_RCAPDAT0/1 and EPWM_FCAPDAT0/1. + * |[3] |CAPORD0_1 |Capture Channel 0/1 Rising/Falling Order + * | | |Set this bit to determine whether the EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 is the first captured data transferred to memory through PDMA when CAPMOD0_1 =11. + * | | |0 = EPWM_FCAPDAT0/1 is the first captured data to memory. + * | | |1 = EPWM_RCAPDAT0/1 is the first captured data to memory. + * |[4] |CHSEL0_1 |Select Channel 0/1 to Do PDMA Transfer + * | | |0 = Channel0. + * | | |1 = Channel1. + * |[8] |CHEN2_3 |Channel 2/3 PDMA Enable + * | | |0 = Channel 2/3 PDMA function Disabled. + * | | |1 = Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory. + * |[10:9] |CAPMOD2_3 |Select EPWM_RCAPDAT2/3 or EPWM_FCAODAT2/3 to Do PDMA Transfer + * | | |00 = Reserved. + * | | |01 = EPWM_RCAPDAT2/3. + * | | |10 = EPWM_FCAPDAT2/3. + * | | |11 = Both EPWM_RCAPDAT2/3 and EPWM_FCAPDAT2/3. + * |[11] |CAPORD2_3 |Capture Channel 2/3 Rising/Falling Order + * | | |Set this bit to determine whether the EPWM_RCAPDAT2/3 or EPWM_FCAPDAT2/3 is the first captured data transferred to memory through PDMA when CAPMOD2_3 =11. + * | | |0 = EPWM_FCAPDAT2/3 is the first captured data to memory. + * | | |1 = EPWM_RCAPDAT2/3 is the first captured data to memory. + * |[12] |CHSEL2_3 |Select Channel 2/3 to Do PDMA Transfer + * | | |0 = Channel2. + * | | |1 = Channel3. + * |[16] |CHEN4_5 |Channel 4/5 PDMA Enable + * | | |0 = Channel 4/5 PDMA function Disabled. + * | | |1 = Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory. + * |[18:17] |CAPMOD4_5 |Select EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 to Do PDMA Transfer + * | | |00 = Reserved. + * | | |01 = EPWM_RCAPDAT4/5. + * | | |10 = EPWM_FCAPDAT4/5. + * | | |11 = Both EPWM_RCAPDAT4/5 and EPWM_FCAPDAT4/5. + * |[19] |CAPORD4_5 |Capture Channel 4/5 Rising/Falling Order + * | | |Set this bit to determine whether the EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 is the first captured data transferred to memory through PDMA when CAPMOD4_5 =11. + * | | |0 = EPWM_FCAPDAT4/5 is the first captured data to memory. + * | | |1 = EPWM_RCAPDAT4/5 is the first captured data to memory. + * |[20] |CHSEL4_5 |Select Channel 4/5 to Do PDMA Transfer + * | | |0 = Channel4. + * | | |1 = Channel5. + * @var EPWM_T::PDMACAP[3] + * Offset: 0x240 EPWM Capture Channel 01 PDMA Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CAPBUF |EPWM Capture PDMA Register (Read Only) + * | | |This register is use as a buffer to transfer EPWM capture rising or falling data to memory by PDMA. + * @var EPWM_T::CAPIEN + * Offset: 0x250 EPWM Capture Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPRIEN0 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[1] |CAPRIEN1 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[2] |CAPRIEN2 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[3] |CAPRIEN3 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[4] |CAPRIEN4 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[5] |CAPRIEN5 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[8] |CAPFIEN0 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * |[9] |CAPFIEN1 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * |[10] |CAPFIEN2 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * |[11] |CAPFIEN3 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * |[12] |CAPFIEN4 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * |[13] |CAPFIEN5 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * @var EPWM_T::CAPIF + * Offset: 0x254 EPWM Capture Interrupt Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CRLIF0 |EPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data. + * |[1] |CRLIF1 |EPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data. + * |[2] |CRLIF2 |EPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data. + * |[3] |CRLIF3 |EPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data. + * |[4] |CRLIF4 |EPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data. + * |[5] |CRLIF5 |EPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data. + * |[8] |CFLIF0 |EPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data. + * |[9] |CFLIF1 |EPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data. + * |[10] |CFLIF2 |EPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data. + * |[11] |CFLIF3 |EPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data. + * |[12] |CFLIF4 |EPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data. + * |[13] |CFLIF5 |EPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data. + * @var EPWM_T::PBUF[6] + * Offset: 0x304 EPWM PERIOD0~5 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PBUF |EPWM Period Register Buffer (Read Only) + * | | |Used as PERIOD active register. + * @var EPWM_T::CMPBUF[6] + * Offset: 0x31C EPWM CMPDAT0~5 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMPBUF |EPWM Comparator Register Buffer (Read Only) + * | | |Used as CMP active register. + * @var EPWM_T::CPSCBUF[3] + * Offset: 0x334 EPWM CLKPSC0_1/2_3/4_5 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CPSCBUF |EPWM Counter Clock Prescale Buffer + * | | |Use as EPWM counter clock prescale active register. + * @var EPWM_T::FTCBUF[3] + * Offset: 0x340 EPWM FTCMPDAT0_1/2_3/4_5 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FTCMPBUF |EPWM FTCMPDAT Buffer (Read Only) + * | | |Used as FTCMPDAT active register. + * @var EPWM_T::FTCI + * Offset: 0x34C EPWM FTCMPDAT Indicator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FTCMU0 |EPWM FTCMPDAT Up Indicator + * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit. + * |[1] |FTCMU2 |EPWM FTCMPDAT Up Indicator + * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit. + * |[2] |FTCMU4 |EPWM FTCMPDAT Up Indicator + * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit. + * |[8] |FTCMD0 |EPWM FTCMPDAT Down Indicator + * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit. + * |[9] |FTCMD2 |EPWM FTCMPDAT Down Indicator + * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit. + * |[10] |FTCMD4 |EPWM FTCMPDAT Down Indicator + * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit. + */ + __IO uint32_t CTL0; /*!< [0x0000] EPWM Control Register 0 */ + __IO uint32_t CTL1; /*!< [0x0004] EPWM Control Register 1 */ + __IO uint32_t SYNC; /*!< [0x0008] EPWM Synchronization Register */ + __IO uint32_t SWSYNC; /*!< [0x000c] EPWM Software Control Synchronization Register */ + __IO uint32_t CLKSRC; /*!< [0x0010] EPWM Clock Source Register */ + __IO uint32_t CLKPSC[3]; /*!< [0x0014] EPWM Clock Prescale Register 0/1,2/3,4/5 */ + __IO uint32_t CNTEN; /*!< [0x0020] EPWM Counter Enable Register */ + __IO uint32_t CNTCLR; /*!< [0x0024] EPWM Clear Counter Register */ + __IO uint32_t LOAD; /*!< [0x0028] EPWM Load Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t PERIOD[6]; /*!< [0x0030] EPWM Period Register 0~5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CMPDAT[6]; /*!< [0x0050] EPWM Comparator Register 0~5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t DTCTL[3]; /*!< [0x0070] EPWM Dead-Time Control Register 0/1,2/3,4/5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t PHS[3]; /*!< [0x0080] EPWM Counter Phase Register 0/1,2/3,4/5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE4[1]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t CNT[6]; /*!< [0x0090] EPWM Counter Register 0~5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE5[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t WGCTL0; /*!< [0x00b0] EPWM Generation Register 0 */ + __IO uint32_t WGCTL1; /*!< [0x00b4] EPWM Generation Register 1 */ + __IO uint32_t MSKEN; /*!< [0x00b8] EPWM Mask Enable Register */ + __IO uint32_t MSK; /*!< [0x00bc] EPWM Mask Data Register */ + __IO uint32_t BNF; /*!< [0x00c0] EPWM Brake Noise Filter Register */ + __IO uint32_t FAILBRK; /*!< [0x00c4] EPWM System Fail Brake Control Register */ + __IO uint32_t BRKCTL[3]; /*!< [0x00c8] EPWM Brake Edge Detect Control Register 0/1,2/3,4/5 */ + __IO uint32_t POLCTL; /*!< [0x00d4] EPWM Pin Polar Inverse Register */ + __IO uint32_t POEN; /*!< [0x00d8] EPWM Output Enable Register */ + __O uint32_t SWBRK; /*!< [0x00dc] EPWM Software Brake Control Register */ + __IO uint32_t INTEN0; /*!< [0x00e0] EPWM Interrupt Enable Register 0 */ + __IO uint32_t INTEN1; /*!< [0x00e4] EPWM Interrupt Enable Register 1 */ + __IO uint32_t INTSTS0; /*!< [0x00e8] EPWM Interrupt Flag Register 0 */ + __IO uint32_t INTSTS1; /*!< [0x00ec] EPWM Interrupt Flag Register 1 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE6[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t DACTRGEN; /*!< [0x00f4] EPWM Trigger DAC Enable Register */ + __IO uint32_t EADCTS0; /*!< [0x00f8] EPWM Trigger EADC Source Select Register 0 */ + __IO uint32_t EADCTS1; /*!< [0x00fc] EPWM Trigger EADC Source Select Register 1 */ + __IO uint32_t FTCMPDAT[3]; /*!< [0x0100] EPWM Free Trigger Compare Register 0/1,2/3,4/5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE7[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t SSCTL; /*!< [0x0110] EPWM Synchronous Start Control Register */ + __O uint32_t SSTRG; /*!< [0x0114] EPWM Synchronous Start Trigger Register */ + __IO uint32_t LEBCTL; /*!< [0x0118] EPWM Leading Edge Blanking Control Register */ + __IO uint32_t LEBCNT; /*!< [0x011c] EPWM Leading Edge Blanking Counter Register */ + __IO uint32_t STATUS; /*!< [0x0120] EPWM Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE8[3]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t IFA[6]; /*!< [0x0130] EPWM Interrupt Flag Accumulator Register 0~5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE9[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t AINTSTS; /*!< [0x0150] EPWM Accumulator Interrupt Flag Register */ + __IO uint32_t AINTEN; /*!< [0x0154] EPWM Accumulator Interrupt Enable Register */ + __IO uint32_t APDMACTL; /*!< [0x0158] EPWM Accumulator PDMA Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE10[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t FDEN; /*!< [0x0160] EPWM Fault Detect Enable Register */ + __IO uint32_t FDCTL[6]; /*!< [0x0164~0x178] EPWM Fault Detect Control Register 0~5 */ + __IO uint32_t FDIEN; /*!< [0x017C] EPWM Fault Detect Interrupt Enable Register */ + __IO uint32_t FDSTS; /*!< [0x0180] EPWM Fault Detect Interrupt Flag Register */ + __IO uint32_t EADCPSCCTL; /*!< [0x0184] EPWM Trigger EADC Prescale Control Register */ + __IO uint32_t EADCPSC0; /*!< [0x0188] EPWM Trigger EADC Prescale Register 0 */ + __IO uint32_t EADCPSC1; /*!< [0x018C] EPWM Trigger EADC Prescale Register 1 */ + __IO uint32_t EADCPSCNT0; /*!< [0x0190] EPWM Trigger EADC Prescale Counter Register 0 */ + __IO uint32_t EADCPSCNT1; /*!< [0x0194] EPWM Trigger EADC Prescale Counter Register 1 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE11[26]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CAPINEN; /*!< [0x0200] EPWM Capture Input Enable Register */ + __IO uint32_t CAPCTL; /*!< [0x0204] EPWM Capture Control Register */ + __I uint32_t CAPSTS; /*!< [0x0208] EPWM Capture Status Register */ + ECAPDAT_T CAPDAT[6]; /*!< [0x020C] EPWM Rising and Falling Capture Data Register 0~5 */ + __IO uint32_t PDMACTL; /*!< [0x023c] EPWM PDMA Control Register */ + __I uint32_t PDMACAP[3]; /*!< [0x0240] EPWM Capture Channel 01,23,45 PDMA Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE12[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CAPIEN; /*!< [0x0250] EPWM Capture Interrupt Enable Register */ + __IO uint32_t CAPIF; /*!< [0x0254] EPWM Capture Interrupt Flag Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE13[43]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t PBUF[6]; /*!< [0x0304] EPWM PERIOD0~5 Buffer */ + __I uint32_t CMPBUF[6]; /*!< [0x031c] EPWM CMPDAT0~5 Buffer */ + __I uint32_t CPSCBUF[3]; /*!< [0x0334] EPWM CLKPSC0_1/2_3/4_5 Buffer */ + __I uint32_t FTCBUF[3]; /*!< [0x0340] EPWM FTCMPDAT0_1/2_3/4_5 Buffer */ + __IO uint32_t FTCI; /*!< [0x034c] EPWM FTCMPDAT Indicator Register */ + +} EPWM_T; + +/** + @addtogroup EPWM_CONST EPWM Bit Field Definition + Constant Definitions for EPWM Controller +@{ */ + +#define EPWM_CTL0_CTRLD0_Pos (0) /*!< EPWM_T::CTL0: CTRLD0 Position */ +#define EPWM_CTL0_CTRLD0_Msk (0x1ul << EPWM_CTL0_CTRLD0_Pos) /*!< EPWM_T::CTL0: CTRLD0 Mask */ + +#define EPWM_CTL0_CTRLD1_Pos (1) /*!< EPWM_T::CTL0: CTRLD1 Position */ +#define EPWM_CTL0_CTRLD1_Msk (0x1ul << EPWM_CTL0_CTRLD1_Pos) /*!< EPWM_T::CTL0: CTRLD1 Mask */ + +#define EPWM_CTL0_CTRLD2_Pos (2) /*!< EPWM_T::CTL0: CTRLD2 Position */ +#define EPWM_CTL0_CTRLD2_Msk (0x1ul << EPWM_CTL0_CTRLD2_Pos) /*!< EPWM_T::CTL0: CTRLD2 Mask */ + +#define EPWM_CTL0_CTRLD3_Pos (3) /*!< EPWM_T::CTL0: CTRLD3 Position */ +#define EPWM_CTL0_CTRLD3_Msk (0x1ul << EPWM_CTL0_CTRLD3_Pos) /*!< EPWM_T::CTL0: CTRLD3 Mask */ + +#define EPWM_CTL0_CTRLD4_Pos (4) /*!< EPWM_T::CTL0: CTRLD4 Position */ +#define EPWM_CTL0_CTRLD4_Msk (0x1ul << EPWM_CTL0_CTRLD4_Pos) /*!< EPWM_T::CTL0: CTRLD4 Mask */ + +#define EPWM_CTL0_CTRLD5_Pos (5) /*!< EPWM_T::CTL0: CTRLD5 Position */ +#define EPWM_CTL0_CTRLD5_Msk (0x1ul << EPWM_CTL0_CTRLD5_Pos) /*!< EPWM_T::CTL0: CTRLD5 Mask */ + +#define EPWM_CTL0_WINLDEN0_Pos (8) /*!< EPWM_T::CTL0: WINLDEN0 Position */ +#define EPWM_CTL0_WINLDEN0_Msk (0x1ul << EPWM_CTL0_WINLDEN0_Pos) /*!< EPWM_T::CTL0: WINLDEN0 Mask */ + +#define EPWM_CTL0_WINLDEN1_Pos (9) /*!< EPWM_T::CTL0: WINLDEN1 Position */ +#define EPWM_CTL0_WINLDEN1_Msk (0x1ul << EPWM_CTL0_WINLDEN1_Pos) /*!< EPWM_T::CTL0: WINLDEN1 Mask */ + +#define EPWM_CTL0_WINLDEN2_Pos (10) /*!< EPWM_T::CTL0: WINLDEN2 Position */ +#define EPWM_CTL0_WINLDEN2_Msk (0x1ul << EPWM_CTL0_WINLDEN2_Pos) /*!< EPWM_T::CTL0: WINLDEN2 Mask */ + +#define EPWM_CTL0_WINLDEN3_Pos (11) /*!< EPWM_T::CTL0: WINLDEN3 Position */ +#define EPWM_CTL0_WINLDEN3_Msk (0x1ul << EPWM_CTL0_WINLDEN3_Pos) /*!< EPWM_T::CTL0: WINLDEN3 Mask */ + +#define EPWM_CTL0_WINLDEN4_Pos (12) /*!< EPWM_T::CTL0: WINLDEN4 Position */ +#define EPWM_CTL0_WINLDEN4_Msk (0x1ul << EPWM_CTL0_WINLDEN4_Pos) /*!< EPWM_T::CTL0: WINLDEN4 Mask */ + +#define EPWM_CTL0_WINLDEN5_Pos (13) /*!< EPWM_T::CTL0: WINLDEN5 Position */ +#define EPWM_CTL0_WINLDEN5_Msk (0x1ul << EPWM_CTL0_WINLDEN5_Pos) /*!< EPWM_T::CTL0: WINLDEN5 Mask */ + +#define EPWM_CTL0_IMMLDEN0_Pos (16) /*!< EPWM_T::CTL0: IMMLDEN0 Position */ +#define EPWM_CTL0_IMMLDEN0_Msk (0x1ul << EPWM_CTL0_IMMLDEN0_Pos) /*!< EPWM_T::CTL0: IMMLDEN0 Mask */ + +#define EPWM_CTL0_IMMLDEN1_Pos (17) /*!< EPWM_T::CTL0: IMMLDEN1 Position */ +#define EPWM_CTL0_IMMLDEN1_Msk (0x1ul << EPWM_CTL0_IMMLDEN1_Pos) /*!< EPWM_T::CTL0: IMMLDEN1 Mask */ + +#define EPWM_CTL0_IMMLDEN2_Pos (18) /*!< EPWM_T::CTL0: IMMLDEN2 Position */ +#define EPWM_CTL0_IMMLDEN2_Msk (0x1ul << EPWM_CTL0_IMMLDEN2_Pos) /*!< EPWM_T::CTL0: IMMLDEN2 Mask */ + +#define EPWM_CTL0_IMMLDEN3_Pos (19) /*!< EPWM_T::CTL0: IMMLDEN3 Position */ +#define EPWM_CTL0_IMMLDEN3_Msk (0x1ul << EPWM_CTL0_IMMLDEN3_Pos) /*!< EPWM_T::CTL0: IMMLDEN3 Mask */ + +#define EPWM_CTL0_IMMLDEN4_Pos (20) /*!< EPWM_T::CTL0: IMMLDEN4 Position */ +#define EPWM_CTL0_IMMLDEN4_Msk (0x1ul << EPWM_CTL0_IMMLDEN4_Pos) /*!< EPWM_T::CTL0: IMMLDEN4 Mask */ + +#define EPWM_CTL0_IMMLDEN5_Pos (21) /*!< EPWM_T::CTL0: IMMLDEN5 Position */ +#define EPWM_CTL0_IMMLDEN5_Msk (0x1ul << EPWM_CTL0_IMMLDEN5_Pos) /*!< EPWM_T::CTL0: IMMLDEN5 Mask */ + +#define EPWM_CTL0_GROUPEN_Pos (24) /*!< EPWM_T::CTL0: GROUPEN Position */ +#define EPWM_CTL0_GROUPEN_Msk (0x1ul << EPWM_CTL0_GROUPEN_Pos) /*!< EPWM_T::CTL0: GROUPEN Mask */ + +#define EPWM_CTL0_DBGHALT_Pos (30) /*!< EPWM_T::CTL0: DBGHALT Position */ +#define EPWM_CTL0_DBGHALT_Msk (0x1ul << EPWM_CTL0_DBGHALT_Pos) /*!< EPWM_T::CTL0: DBGHALT Mask */ + +#define EPWM_CTL0_DBGTRIOFF_Pos (31) /*!< EPWM_T::CTL0: DBGTRIOFF Position */ +#define EPWM_CTL0_DBGTRIOFF_Msk (0x1ul << EPWM_CTL0_DBGTRIOFF_Pos) /*!< EPWM_T::CTL0: DBGTRIOFF Mask */ + +#define EPWM_CTL1_CNTTYPE0_Pos (0) /*!< EPWM_T::CTL1: CNTTYPE0 Position */ +#define EPWM_CTL1_CNTTYPE0_Msk (0x3ul << EPWM_CTL1_CNTTYPE0_Pos) /*!< EPWM_T::CTL1: CNTTYPE0 Mask */ + +#define EPWM_CTL1_CNTTYPE1_Pos (2) /*!< EPWM_T::CTL1: CNTTYPE1 Position */ +#define EPWM_CTL1_CNTTYPE1_Msk (0x3ul << EPWM_CTL1_CNTTYPE1_Pos) /*!< EPWM_T::CTL1: CNTTYPE1 Mask */ + +#define EPWM_CTL1_CNTTYPE2_Pos (4) /*!< EPWM_T::CTL1: CNTTYPE2 Position */ +#define EPWM_CTL1_CNTTYPE2_Msk (0x3ul << EPWM_CTL1_CNTTYPE2_Pos) /*!< EPWM_T::CTL1: CNTTYPE2 Mask */ + +#define EPWM_CTL1_CNTTYPE3_Pos (6) /*!< EPWM_T::CTL1: CNTTYPE3 Position */ +#define EPWM_CTL1_CNTTYPE3_Msk (0x3ul << EPWM_CTL1_CNTTYPE3_Pos) /*!< EPWM_T::CTL1: CNTTYPE3 Mask */ + +#define EPWM_CTL1_CNTTYPE4_Pos (8) /*!< EPWM_T::CTL1: CNTTYPE4 Position */ +#define EPWM_CTL1_CNTTYPE4_Msk (0x3ul << EPWM_CTL1_CNTTYPE4_Pos) /*!< EPWM_T::CTL1: CNTTYPE4 Mask */ + +#define EPWM_CTL1_CNTTYPE5_Pos (10) /*!< EPWM_T::CTL1: CNTTYPE5 Position */ +#define EPWM_CTL1_CNTTYPE5_Msk (0x3ul << EPWM_CTL1_CNTTYPE5_Pos) /*!< EPWM_T::CTL1: CNTTYPE5 Mask */ + +#define EPWM_CTL1_CNTMODE0_Pos (16) /*!< EPWM_T::CTL1: CNTMODE0 Position */ +#define EPWM_CTL1_CNTMODE0_Msk (0x1ul << EPWM_CTL1_CNTMODE0_Pos) /*!< EPWM_T::CTL1: CNTMODE0 Mask */ + +#define EPWM_CTL1_CNTMODE1_Pos (17) /*!< EPWM_T::CTL1: CNTMODE1 Position */ +#define EPWM_CTL1_CNTMODE1_Msk (0x1ul << EPWM_CTL1_CNTMODE1_Pos) /*!< EPWM_T::CTL1: CNTMODE1 Mask */ + +#define EPWM_CTL1_CNTMODE2_Pos (18) /*!< EPWM_T::CTL1: CNTMODE2 Position */ +#define EPWM_CTL1_CNTMODE2_Msk (0x1ul << EPWM_CTL1_CNTMODE2_Pos) /*!< EPWM_T::CTL1: CNTMODE2 Mask */ + +#define EPWM_CTL1_CNTMODE3_Pos (19) /*!< EPWM_T::CTL1: CNTMODE3 Position */ +#define EPWM_CTL1_CNTMODE3_Msk (0x1ul << EPWM_CTL1_CNTMODE3_Pos) /*!< EPWM_T::CTL1: CNTMODE3 Mask */ + +#define EPWM_CTL1_CNTMODE4_Pos (20) /*!< EPWM_T::CTL1: CNTMODE4 Position */ +#define EPWM_CTL1_CNTMODE4_Msk (0x1ul << EPWM_CTL1_CNTMODE4_Pos) /*!< EPWM_T::CTL1: CNTMODE4 Mask */ + +#define EPWM_CTL1_CNTMODE5_Pos (21) /*!< EPWM_T::CTL1: CNTMODE5 Position */ +#define EPWM_CTL1_CNTMODE5_Msk (0x1ul << EPWM_CTL1_CNTMODE5_Pos) /*!< EPWM_T::CTL1: CNTMODE5 Mask */ + +#define EPWM_CTL1_OUTMODE0_Pos (24) /*!< EPWM_T::CTL1: OUTMODE0 Position */ +#define EPWM_CTL1_OUTMODE0_Msk (0x1ul << EPWM_CTL1_OUTMODE0_Pos) /*!< EPWM_T::CTL1: OUTMODE0 Mask */ + +#define EPWM_CTL1_OUTMODE2_Pos (25) /*!< EPWM_T::CTL1: OUTMODE2 Position */ +#define EPWM_CTL1_OUTMODE2_Msk (0x1ul << EPWM_CTL1_OUTMODE2_Pos) /*!< EPWM_T::CTL1: OUTMODE2 Mask */ + +#define EPWM_CTL1_OUTMODE4_Pos (26) /*!< EPWM_T::CTL1: OUTMODE4 Position */ +#define EPWM_CTL1_OUTMODE4_Msk (0x1ul << EPWM_CTL1_OUTMODE4_Pos) /*!< EPWM_T::CTL1: OUTMODE4 Mask */ + +#define EPWM_SYNC_PHSEN0_Pos (0) /*!< EPWM_T::SYNC: PHSEN0 Position */ +#define EPWM_SYNC_PHSEN0_Msk (0x1ul << EPWM_SYNC_PHSEN0_Pos) /*!< EPWM_T::SYNC: PHSEN0 Mask */ + +#define EPWM_SYNC_PHSEN2_Pos (1) /*!< EPWM_T::SYNC: PHSEN2 Position */ +#define EPWM_SYNC_PHSEN2_Msk (0x1ul << EPWM_SYNC_PHSEN2_Pos) /*!< EPWM_T::SYNC: PHSEN2 Mask */ + +#define EPWM_SYNC_PHSEN4_Pos (2) /*!< EPWM_T::SYNC: PHSEN4 Position */ +#define EPWM_SYNC_PHSEN4_Msk (0x1ul << EPWM_SYNC_PHSEN4_Pos) /*!< EPWM_T::SYNC: PHSEN4 Mask */ + +#define EPWM_SYNC_SINSRC0_Pos (8) /*!< EPWM_T::SYNC: SINSRC0 Position */ +#define EPWM_SYNC_SINSRC0_Msk (0x3ul << EPWM_SYNC_SINSRC0_Pos) /*!< EPWM_T::SYNC: SINSRC0 Mask */ + +#define EPWM_SYNC_SINSRC2_Pos (10) /*!< EPWM_T::SYNC: SINSRC2 Position */ +#define EPWM_SYNC_SINSRC2_Msk (0x3ul << EPWM_SYNC_SINSRC2_Pos) /*!< EPWM_T::SYNC: SINSRC2 Mask */ + +#define EPWM_SYNC_SINSRC4_Pos (12) /*!< EPWM_T::SYNC: SINSRC4 Position */ +#define EPWM_SYNC_SINSRC4_Msk (0x3ul << EPWM_SYNC_SINSRC4_Pos) /*!< EPWM_T::SYNC: SINSRC4 Mask */ + +#define EPWM_SYNC_SNFLTEN_Pos (16) /*!< EPWM_T::SYNC: SNFLTEN Position */ +#define EPWM_SYNC_SNFLTEN_Msk (0x1ul << EPWM_SYNC_SNFLTEN_Pos) /*!< EPWM_T::SYNC: SNFLTEN Mask */ + +#define EPWM_SYNC_SFLTCSEL_Pos (17) /*!< EPWM_T::SYNC: SFLTCSEL Position */ +#define EPWM_SYNC_SFLTCSEL_Msk (0x7ul << EPWM_SYNC_SFLTCSEL_Pos) /*!< EPWM_T::SYNC: SFLTCSEL Mask */ + +#define EPWM_SYNC_SFLTCNT_Pos (20) /*!< EPWM_T::SYNC: SFLTCNT Position */ +#define EPWM_SYNC_SFLTCNT_Msk (0x7ul << EPWM_SYNC_SFLTCNT_Pos) /*!< EPWM_T::SYNC: SFLTCNT Mask */ + +#define EPWM_SYNC_SINPINV_Pos (23) /*!< EPWM_T::SYNC: SINPINV Position */ +#define EPWM_SYNC_SINPINV_Msk (0x1ul << EPWM_SYNC_SINPINV_Pos) /*!< EPWM_T::SYNC: SINPINV Mask */ + +#define EPWM_SYNC_PHSDIR0_Pos (24) /*!< EPWM_T::SYNC: PHSDIR0 Position */ +#define EPWM_SYNC_PHSDIR0_Msk (0x1ul << EPWM_SYNC_PHSDIR0_Pos) /*!< EPWM_T::SYNC: PHSDIR0 Mask */ + +#define EPWM_SYNC_PHSDIR2_Pos (25) /*!< EPWM_T::SYNC: PHSDIR2 Position */ +#define EPWM_SYNC_PHSDIR2_Msk (0x1ul << EPWM_SYNC_PHSDIR2_Pos) /*!< EPWM_T::SYNC: PHSDIR2 Mask */ + +#define EPWM_SYNC_PHSDIR4_Pos (26) /*!< EPWM_T::SYNC: PHSDIR4 Position */ +#define EPWM_SYNC_PHSDIR4_Msk (0x1ul << EPWM_SYNC_PHSDIR4_Pos) /*!< EPWM_T::SYNC: PHSDIR4 Mask */ + +#define EPWM_SWSYNC_SWSYNC0_Pos (0) /*!< EPWM_T::SWSYNC: SWSYNC0 Position */ +#define EPWM_SWSYNC_SWSYNC0_Msk (0x1ul << EPWM_SWSYNC_SWSYNC0_Pos) /*!< EPWM_T::SWSYNC: SWSYNC0 Mask */ + +#define EPWM_SWSYNC_SWSYNC2_Pos (1) /*!< EPWM_T::SWSYNC: SWSYNC2 Position */ +#define EPWM_SWSYNC_SWSYNC2_Msk (0x1ul << EPWM_SWSYNC_SWSYNC2_Pos) /*!< EPWM_T::SWSYNC: SWSYNC2 Mask */ + +#define EPWM_SWSYNC_SWSYNC4_Pos (2) /*!< EPWM_T::SWSYNC: SWSYNC4 Position */ +#define EPWM_SWSYNC_SWSYNC4_Msk (0x1ul << EPWM_SWSYNC_SWSYNC4_Pos) /*!< EPWM_T::SWSYNC: SWSYNC4 Mask */ + +#define EPWM_CLKSRC_ECLKSRC0_Pos (0) /*!< EPWM_T::CLKSRC: ECLKSRC0 Position */ +#define EPWM_CLKSRC_ECLKSRC0_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC0_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC0 Mask */ + +#define EPWM_CLKSRC_ECLKSRC2_Pos (8) /*!< EPWM_T::CLKSRC: ECLKSRC2 Position */ +#define EPWM_CLKSRC_ECLKSRC2_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC2_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC2 Mask */ + +#define EPWM_CLKSRC_ECLKSRC4_Pos (16) /*!< EPWM_T::CLKSRC: ECLKSRC4 Position */ +#define EPWM_CLKSRC_ECLKSRC4_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC4_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC4 Mask */ + +#define EPWM_CLKPSC0_1_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC0_1: CLKPSC Position */ +#define EPWM_CLKPSC0_1_CLKPSC_Msk (0xffful << EPWM_CLKPSC0_1_CLKPSC_Pos) /*!< EPWM_T::CLKPSC0_1: CLKPSC Mask */ + +#define EPWM_CLKPSC2_3_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC2_3: CLKPSC Position */ +#define EPWM_CLKPSC2_3_CLKPSC_Msk (0xffful << EPWM_CLKPSC2_3_CLKPSC_Pos) /*!< EPWM_T::CLKPSC2_3: CLKPSC Mask */ + +#define EPWM_CLKPSC4_5_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC4_5: CLKPSC Position */ +#define EPWM_CLKPSC4_5_CLKPSC_Msk (0xffful << EPWM_CLKPSC4_5_CLKPSC_Pos) /*!< EPWM_T::CLKPSC4_5: CLKPSC Mask */ + +#define EPWM_CNTEN_CNTEN0_Pos (0) /*!< EPWM_T::CNTEN: CNTEN0 Position */ +#define EPWM_CNTEN_CNTEN0_Msk (0x1ul << EPWM_CNTEN_CNTEN0_Pos) /*!< EPWM_T::CNTEN: CNTEN0 Mask */ + +#define EPWM_CNTEN_CNTEN1_Pos (1) /*!< EPWM_T::CNTEN: CNTEN1 Position */ +#define EPWM_CNTEN_CNTEN1_Msk (0x1ul << EPWM_CNTEN_CNTEN1_Pos) /*!< EPWM_T::CNTEN: CNTEN1 Mask */ + +#define EPWM_CNTEN_CNTEN2_Pos (2) /*!< EPWM_T::CNTEN: CNTEN2 Position */ +#define EPWM_CNTEN_CNTEN2_Msk (0x1ul << EPWM_CNTEN_CNTEN2_Pos) /*!< EPWM_T::CNTEN: CNTEN2 Mask */ + +#define EPWM_CNTEN_CNTEN3_Pos (3) /*!< EPWM_T::CNTEN: CNTEN3 Position */ +#define EPWM_CNTEN_CNTEN3_Msk (0x1ul << EPWM_CNTEN_CNTEN3_Pos) /*!< EPWM_T::CNTEN: CNTEN3 Mask */ + +#define EPWM_CNTEN_CNTEN4_Pos (4) /*!< EPWM_T::CNTEN: CNTEN4 Position */ +#define EPWM_CNTEN_CNTEN4_Msk (0x1ul << EPWM_CNTEN_CNTEN4_Pos) /*!< EPWM_T::CNTEN: CNTEN4 Mask */ + +#define EPWM_CNTEN_CNTEN5_Pos (5) /*!< EPWM_T::CNTEN: CNTEN5 Position */ +#define EPWM_CNTEN_CNTEN5_Msk (0x1ul << EPWM_CNTEN_CNTEN5_Pos) /*!< EPWM_T::CNTEN: CNTEN5 Mask */ + +#define EPWM_CNTCLR_CNTCLR0_Pos (0) /*!< EPWM_T::CNTCLR: CNTCLR0 Position */ +#define EPWM_CNTCLR_CNTCLR0_Msk (0x1ul << EPWM_CNTCLR_CNTCLR0_Pos) /*!< EPWM_T::CNTCLR: CNTCLR0 Mask */ + +#define EPWM_CNTCLR_CNTCLR1_Pos (1) /*!< EPWM_T::CNTCLR: CNTCLR1 Position */ +#define EPWM_CNTCLR_CNTCLR1_Msk (0x1ul << EPWM_CNTCLR_CNTCLR1_Pos) /*!< EPWM_T::CNTCLR: CNTCLR1 Mask */ + +#define EPWM_CNTCLR_CNTCLR2_Pos (2) /*!< EPWM_T::CNTCLR: CNTCLR2 Position */ +#define EPWM_CNTCLR_CNTCLR2_Msk (0x1ul << EPWM_CNTCLR_CNTCLR2_Pos) /*!< EPWM_T::CNTCLR: CNTCLR2 Mask */ + +#define EPWM_CNTCLR_CNTCLR3_Pos (3) /*!< EPWM_T::CNTCLR: CNTCLR3 Position */ +#define EPWM_CNTCLR_CNTCLR3_Msk (0x1ul << EPWM_CNTCLR_CNTCLR3_Pos) /*!< EPWM_T::CNTCLR: CNTCLR3 Mask */ + +#define EPWM_CNTCLR_CNTCLR4_Pos (4) /*!< EPWM_T::CNTCLR: CNTCLR4 Position */ +#define EPWM_CNTCLR_CNTCLR4_Msk (0x1ul << EPWM_CNTCLR_CNTCLR4_Pos) /*!< EPWM_T::CNTCLR: CNTCLR4 Mask */ + +#define EPWM_CNTCLR_CNTCLR5_Pos (5) /*!< EPWM_T::CNTCLR: CNTCLR5 Position */ +#define EPWM_CNTCLR_CNTCLR5_Msk (0x1ul << EPWM_CNTCLR_CNTCLR5_Pos) /*!< EPWM_T::CNTCLR: CNTCLR5 Mask */ + +#define EPWM_LOAD_LOAD0_Pos (0) /*!< EPWM_T::LOAD: LOAD0 Position */ +#define EPWM_LOAD_LOAD0_Msk (0x1ul << EPWM_LOAD_LOAD0_Pos) /*!< EPWM_T::LOAD: LOAD0 Mask */ + +#define EPWM_LOAD_LOAD1_Pos (1) /*!< EPWM_T::LOAD: LOAD1 Position */ +#define EPWM_LOAD_LOAD1_Msk (0x1ul << EPWM_LOAD_LOAD1_Pos) /*!< EPWM_T::LOAD: LOAD1 Mask */ + +#define EPWM_LOAD_LOAD2_Pos (2) /*!< EPWM_T::LOAD: LOAD2 Position */ +#define EPWM_LOAD_LOAD2_Msk (0x1ul << EPWM_LOAD_LOAD2_Pos) /*!< EPWM_T::LOAD: LOAD2 Mask */ + +#define EPWM_LOAD_LOAD3_Pos (3) /*!< EPWM_T::LOAD: LOAD3 Position */ +#define EPWM_LOAD_LOAD3_Msk (0x1ul << EPWM_LOAD_LOAD3_Pos) /*!< EPWM_T::LOAD: LOAD3 Mask */ + +#define EPWM_LOAD_LOAD4_Pos (4) /*!< EPWM_T::LOAD: LOAD4 Position */ +#define EPWM_LOAD_LOAD4_Msk (0x1ul << EPWM_LOAD_LOAD4_Pos) /*!< EPWM_T::LOAD: LOAD4 Mask */ + +#define EPWM_LOAD_LOAD5_Pos (5) /*!< EPWM_T::LOAD: LOAD5 Position */ +#define EPWM_LOAD_LOAD5_Msk (0x1ul << EPWM_LOAD_LOAD5_Pos) /*!< EPWM_T::LOAD: LOAD5 Mask */ + +#define EPWM_PERIOD0_PERIOD_Pos (0) /*!< EPWM_T::PERIOD0: PERIOD Position */ +#define EPWM_PERIOD0_PERIOD_Msk (0xfffful << EPWM_PERIOD0_PERIOD_Pos) /*!< EPWM_T::PERIOD0: PERIOD Mask */ + +#define EPWM_PERIOD1_PERIOD_Pos (0) /*!< EPWM_T::PERIOD1: PERIOD Position */ +#define EPWM_PERIOD1_PERIOD_Msk (0xfffful << EPWM_PERIOD1_PERIOD_Pos) /*!< EPWM_T::PERIOD1: PERIOD Mask */ + +#define EPWM_PERIOD2_PERIOD_Pos (0) /*!< EPWM_T::PERIOD2: PERIOD Position */ +#define EPWM_PERIOD2_PERIOD_Msk (0xfffful << EPWM_PERIOD2_PERIOD_Pos) /*!< EPWM_T::PERIOD2: PERIOD Mask */ + +#define EPWM_PERIOD3_PERIOD_Pos (0) /*!< EPWM_T::PERIOD3: PERIOD Position */ +#define EPWM_PERIOD3_PERIOD_Msk (0xfffful << EPWM_PERIOD3_PERIOD_Pos) /*!< EPWM_T::PERIOD3: PERIOD Mask */ + +#define EPWM_PERIOD4_PERIOD_Pos (0) /*!< EPWM_T::PERIOD4: PERIOD Position */ +#define EPWM_PERIOD4_PERIOD_Msk (0xfffful << EPWM_PERIOD4_PERIOD_Pos) /*!< EPWM_T::PERIOD4: PERIOD Mask */ + +#define EPWM_PERIOD5_PERIOD_Pos (0) /*!< EPWM_T::PERIOD5: PERIOD Position */ +#define EPWM_PERIOD5_PERIOD_Msk (0xfffful << EPWM_PERIOD5_PERIOD_Pos) /*!< EPWM_T::PERIOD5: PERIOD Mask */ + +#define EPWM_CMPDAT0_CMP_Pos (0) /*!< EPWM_T::CMPDAT0: CMP Position */ +#define EPWM_CMPDAT0_CMP_Msk (0xfffful << EPWM_CMPDAT0_CMP_Pos) /*!< EPWM_T::CMPDAT0: CMP Mask */ + +#define EPWM_CMPDAT1_CMP_Pos (0) /*!< EPWM_T::CMPDAT1: CMP Position */ +#define EPWM_CMPDAT1_CMP_Msk (0xfffful << EPWM_CMPDAT1_CMP_Pos) /*!< EPWM_T::CMPDAT1: CMP Mask */ + +#define EPWM_CMPDAT2_CMP_Pos (0) /*!< EPWM_T::CMPDAT2: CMP Position */ +#define EPWM_CMPDAT2_CMP_Msk (0xfffful << EPWM_CMPDAT2_CMP_Pos) /*!< EPWM_T::CMPDAT2: CMP Mask */ + +#define EPWM_CMPDAT3_CMP_Pos (0) /*!< EPWM_T::CMPDAT3: CMP Position */ +#define EPWM_CMPDAT3_CMP_Msk (0xfffful << EPWM_CMPDAT3_CMP_Pos) /*!< EPWM_T::CMPDAT3: CMP Mask */ + +#define EPWM_CMPDAT4_CMP_Pos (0) /*!< EPWM_T::CMPDAT4: CMP Position */ +#define EPWM_CMPDAT4_CMP_Msk (0xfffful << EPWM_CMPDAT4_CMP_Pos) /*!< EPWM_T::CMPDAT4: CMP Mask */ + +#define EPWM_CMPDAT5_CMP_Pos (0) /*!< EPWM_T::CMPDAT5: CMP Position */ +#define EPWM_CMPDAT5_CMP_Msk (0xfffful << EPWM_CMPDAT5_CMP_Pos) /*!< EPWM_T::CMPDAT5: CMP Mask */ + +#define EPWM_DTCTL0_1_DTCNT_Pos (0) /*!< EPWM_T::DTCTL0_1: DTCNT Position */ +#define EPWM_DTCTL0_1_DTCNT_Msk (0xffful << EPWM_DTCTL0_1_DTCNT_Pos) /*!< EPWM_T::DTCTL0_1: DTCNT Mask */ + +#define EPWM_DTCTL0_1_DTEN_Pos (16) /*!< EPWM_T::DTCTL0_1: DTEN Position */ +#define EPWM_DTCTL0_1_DTEN_Msk (0x1ul << EPWM_DTCTL0_1_DTEN_Pos) /*!< EPWM_T::DTCTL0_1: DTEN Mask */ + +#define EPWM_DTCTL0_1_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL0_1: DTCKSEL Position */ +#define EPWM_DTCTL0_1_DTCKSEL_Msk (0x1ul << EPWM_DTCTL0_1_DTCKSEL_Pos) /*!< EPWM_T::DTCTL0_1: DTCKSEL Mask */ + +#define EPWM_DTCTL2_3_DTCNT_Pos (0) /*!< EPWM_T::DTCTL2_3: DTCNT Position */ +#define EPWM_DTCTL2_3_DTCNT_Msk (0xffful << EPWM_DTCTL2_3_DTCNT_Pos) /*!< EPWM_T::DTCTL2_3: DTCNT Mask */ + +#define EPWM_DTCTL2_3_DTEN_Pos (16) /*!< EPWM_T::DTCTL2_3: DTEN Position */ +#define EPWM_DTCTL2_3_DTEN_Msk (0x1ul << EPWM_DTCTL2_3_DTEN_Pos) /*!< EPWM_T::DTCTL2_3: DTEN Mask */ + +#define EPWM_DTCTL2_3_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL2_3: DTCKSEL Position */ +#define EPWM_DTCTL2_3_DTCKSEL_Msk (0x1ul << EPWM_DTCTL2_3_DTCKSEL_Pos) /*!< EPWM_T::DTCTL2_3: DTCKSEL Mask */ + +#define EPWM_DTCTL4_5_DTCNT_Pos (0) /*!< EPWM_T::DTCTL4_5: DTCNT Position */ +#define EPWM_DTCTL4_5_DTCNT_Msk (0xffful << EPWM_DTCTL4_5_DTCNT_Pos) /*!< EPWM_T::DTCTL4_5: DTCNT Mask */ + +#define EPWM_DTCTL4_5_DTEN_Pos (16) /*!< EPWM_T::DTCTL4_5: DTEN Position */ +#define EPWM_DTCTL4_5_DTEN_Msk (0x1ul << EPWM_DTCTL4_5_DTEN_Pos) /*!< EPWM_T::DTCTL4_5: DTEN Mask */ + +#define EPWM_DTCTL4_5_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL4_5: DTCKSEL Position */ +#define EPWM_DTCTL4_5_DTCKSEL_Msk (0x1ul << EPWM_DTCTL4_5_DTCKSEL_Pos) /*!< EPWM_T::DTCTL4_5: DTCKSEL Mask */ + +#define EPWM_PHS0_1_PHS_Pos (0) /*!< EPWM_T::PHS0_1: PHS Position */ +#define EPWM_PHS0_1_PHS_Msk (0xfffful << EPWM_PHS0_1_PHS_Pos) /*!< EPWM_T::PHS0_1: PHS Mask */ + +#define EPWM_PHS2_3_PHS_Pos (0) /*!< EPWM_T::PHS2_3: PHS Position */ +#define EPWM_PHS2_3_PHS_Msk (0xfffful << EPWM_PHS2_3_PHS_Pos) /*!< EPWM_T::PHS2_3: PHS Mask */ + +#define EPWM_PHS4_5_PHS_Pos (0) /*!< EPWM_T::PHS4_5: PHS Position */ +#define EPWM_PHS4_5_PHS_Msk (0xfffful << EPWM_PHS4_5_PHS_Pos) /*!< EPWM_T::PHS4_5: PHS Mask */ + +#define EPWM_CNT0_CNT_Pos (0) /*!< EPWM_T::CNT0: CNT Position */ +#define EPWM_CNT0_CNT_Msk (0xfffful << EPWM_CNT0_CNT_Pos) /*!< EPWM_T::CNT0: CNT Mask */ + +#define EPWM_CNT0_DIRF_Pos (16) /*!< EPWM_T::CNT0: DIRF Position */ +#define EPWM_CNT0_DIRF_Msk (0x1ul << EPWM_CNT0_DIRF_Pos) /*!< EPWM_T::CNT0: DIRF Mask */ + +#define EPWM_CNT1_CNT_Pos (0) /*!< EPWM_T::CNT1: CNT Position */ +#define EPWM_CNT1_CNT_Msk (0xfffful << EPWM_CNT1_CNT_Pos) /*!< EPWM_T::CNT1: CNT Mask */ + +#define EPWM_CNT1_DIRF_Pos (16) /*!< EPWM_T::CNT1: DIRF Position */ +#define EPWM_CNT1_DIRF_Msk (0x1ul << EPWM_CNT1_DIRF_Pos) /*!< EPWM_T::CNT1: DIRF Mask */ + +#define EPWM_CNT2_CNT_Pos (0) /*!< EPWM_T::CNT2: CNT Position */ +#define EPWM_CNT2_CNT_Msk (0xfffful << EPWM_CNT2_CNT_Pos) /*!< EPWM_T::CNT2: CNT Mask */ + +#define EPWM_CNT2_DIRF_Pos (16) /*!< EPWM_T::CNT2: DIRF Position */ +#define EPWM_CNT2_DIRF_Msk (0x1ul << EPWM_CNT2_DIRF_Pos) /*!< EPWM_T::CNT2: DIRF Mask */ + +#define EPWM_CNT3_CNT_Pos (0) /*!< EPWM_T::CNT3: CNT Position */ +#define EPWM_CNT3_CNT_Msk (0xfffful << EPWM_CNT3_CNT_Pos) /*!< EPWM_T::CNT3: CNT Mask */ + +#define EPWM_CNT3_DIRF_Pos (16) /*!< EPWM_T::CNT3: DIRF Position */ +#define EPWM_CNT3_DIRF_Msk (0x1ul << EPWM_CNT3_DIRF_Pos) /*!< EPWM_T::CNT3: DIRF Mask */ + +#define EPWM_CNT4_CNT_Pos (0) /*!< EPWM_T::CNT4: CNT Position */ +#define EPWM_CNT4_CNT_Msk (0xfffful << EPWM_CNT4_CNT_Pos) /*!< EPWM_T::CNT4: CNT Mask */ + +#define EPWM_CNT4_DIRF_Pos (16) /*!< EPWM_T::CNT4: DIRF Position */ +#define EPWM_CNT4_DIRF_Msk (0x1ul << EPWM_CNT4_DIRF_Pos) /*!< EPWM_T::CNT4: DIRF Mask */ + +#define EPWM_CNT5_CNT_Pos (0) /*!< EPWM_T::CNT5: CNT Position */ +#define EPWM_CNT5_CNT_Msk (0xfffful << EPWM_CNT5_CNT_Pos) /*!< EPWM_T::CNT5: CNT Mask */ + +#define EPWM_CNT5_DIRF_Pos (16) /*!< EPWM_T::CNT5: DIRF Position */ +#define EPWM_CNT5_DIRF_Msk (0x1ul << EPWM_CNT5_DIRF_Pos) /*!< EPWM_T::CNT5: DIRF Mask */ + +#define EPWM_WGCTL0_ZPCTL0_Pos (0) /*!< EPWM_T::WGCTL0: ZPCTL0 Position */ +#define EPWM_WGCTL0_ZPCTL0_Msk (0x3ul << EPWM_WGCTL0_ZPCTL0_Pos) /*!< EPWM_T::WGCTL0: ZPCTL0 Mask */ + +#define EPWM_WGCTL0_ZPCTL1_Pos (2) /*!< EPWM_T::WGCTL0: ZPCTL1 Position */ +#define EPWM_WGCTL0_ZPCTL1_Msk (0x3ul << EPWM_WGCTL0_ZPCTL1_Pos) /*!< EPWM_T::WGCTL0: ZPCTL1 Mask */ + +#define EPWM_WGCTL0_ZPCTL2_Pos (4) /*!< EPWM_T::WGCTL0: ZPCTL2 Position */ +#define EPWM_WGCTL0_ZPCTL2_Msk (0x3ul << EPWM_WGCTL0_ZPCTL2_Pos) /*!< EPWM_T::WGCTL0: ZPCTL2 Mask */ + +#define EPWM_WGCTL0_ZPCTL3_Pos (6) /*!< EPWM_T::WGCTL0: ZPCTL3 Position */ +#define EPWM_WGCTL0_ZPCTL3_Msk (0x3ul << EPWM_WGCTL0_ZPCTL3_Pos) /*!< EPWM_T::WGCTL0: ZPCTL3 Mask */ + +#define EPWM_WGCTL0_ZPCTL4_Pos (8) /*!< EPWM_T::WGCTL0: ZPCTL4 Position */ +#define EPWM_WGCTL0_ZPCTL4_Msk (0x3ul << EPWM_WGCTL0_ZPCTL4_Pos) /*!< EPWM_T::WGCTL0: ZPCTL4 Mask */ + +#define EPWM_WGCTL0_ZPCTL5_Pos (10) /*!< EPWM_T::WGCTL0: ZPCTL5 Position */ +#define EPWM_WGCTL0_ZPCTL5_Msk (0x3ul << EPWM_WGCTL0_ZPCTL5_Pos) /*!< EPWM_T::WGCTL0: ZPCTL5 Mask */ + +#define EPWM_WGCTL0_PRDPCTL0_Pos (16) /*!< EPWM_T::WGCTL0: PRDPCTL0 Position */ +#define EPWM_WGCTL0_PRDPCTL0_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL0_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL0 Mask */ + +#define EPWM_WGCTL0_PRDPCTL1_Pos (18) /*!< EPWM_T::WGCTL0: PRDPCTL1 Position */ +#define EPWM_WGCTL0_PRDPCTL1_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL1_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL1 Mask */ + +#define EPWM_WGCTL0_PRDPCTL2_Pos (20) /*!< EPWM_T::WGCTL0: PRDPCTL2 Position */ +#define EPWM_WGCTL0_PRDPCTL2_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL2_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL2 Mask */ + +#define EPWM_WGCTL0_PRDPCTL3_Pos (22) /*!< EPWM_T::WGCTL0: PRDPCTL3 Position */ +#define EPWM_WGCTL0_PRDPCTL3_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL3_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL3 Mask */ + +#define EPWM_WGCTL0_PRDPCTL4_Pos (24) /*!< EPWM_T::WGCTL0: PRDPCTL4 Position */ +#define EPWM_WGCTL0_PRDPCTL4_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL4_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL4 Mask */ + +#define EPWM_WGCTL0_PRDPCTL5_Pos (26) /*!< EPWM_T::WGCTL0: PRDPCTL5 Position */ +#define EPWM_WGCTL0_PRDPCTL5_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL5_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL5 Mask */ + +#define EPWM_WGCTL1_CMPUCTL0_Pos (0) /*!< EPWM_T::WGCTL1: CMPUCTL0 Position */ +#define EPWM_WGCTL1_CMPUCTL0_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL0_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL0 Mask */ + +#define EPWM_WGCTL1_CMPUCTL1_Pos (2) /*!< EPWM_T::WGCTL1: CMPUCTL1 Position */ +#define EPWM_WGCTL1_CMPUCTL1_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL1_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL1 Mask */ + +#define EPWM_WGCTL1_CMPUCTL2_Pos (4) /*!< EPWM_T::WGCTL1: CMPUCTL2 Position */ +#define EPWM_WGCTL1_CMPUCTL2_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL2_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL2 Mask */ + +#define EPWM_WGCTL1_CMPUCTL3_Pos (6) /*!< EPWM_T::WGCTL1: CMPUCTL3 Position */ +#define EPWM_WGCTL1_CMPUCTL3_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL3_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL3 Mask */ + +#define EPWM_WGCTL1_CMPUCTL4_Pos (8) /*!< EPWM_T::WGCTL1: CMPUCTL4 Position */ +#define EPWM_WGCTL1_CMPUCTL4_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL4_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL4 Mask */ + +#define EPWM_WGCTL1_CMPUCTL5_Pos (10) /*!< EPWM_T::WGCTL1: CMPUCTL5 Position */ +#define EPWM_WGCTL1_CMPUCTL5_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL5_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL5 Mask */ + +#define EPWM_WGCTL1_CMPDCTL0_Pos (16) /*!< EPWM_T::WGCTL1: CMPDCTL0 Position */ +#define EPWM_WGCTL1_CMPDCTL0_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL0_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL0 Mask */ + +#define EPWM_WGCTL1_CMPDCTL1_Pos (18) /*!< EPWM_T::WGCTL1: CMPDCTL1 Position */ +#define EPWM_WGCTL1_CMPDCTL1_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL1_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL1 Mask */ + +#define EPWM_WGCTL1_CMPDCTL2_Pos (20) /*!< EPWM_T::WGCTL1: CMPDCTL2 Position */ +#define EPWM_WGCTL1_CMPDCTL2_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL2_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL2 Mask */ + +#define EPWM_WGCTL1_CMPDCTL3_Pos (22) /*!< EPWM_T::WGCTL1: CMPDCTL3 Position */ +#define EPWM_WGCTL1_CMPDCTL3_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL3_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL3 Mask */ + +#define EPWM_WGCTL1_CMPDCTL4_Pos (24) /*!< EPWM_T::WGCTL1: CMPDCTL4 Position */ +#define EPWM_WGCTL1_CMPDCTL4_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL4_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL4 Mask */ + +#define EPWM_WGCTL1_CMPDCTL5_Pos (26) /*!< EPWM_T::WGCTL1: CMPDCTL5 Position */ +#define EPWM_WGCTL1_CMPDCTL5_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL5_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL5 Mask */ + +#define EPWM_MSKEN_MSKEN0_Pos (0) /*!< EPWM_T::MSKEN: MSKEN0 Position */ +#define EPWM_MSKEN_MSKEN0_Msk (0x1ul << EPWM_MSKEN_MSKEN0_Pos) /*!< EPWM_T::MSKEN: MSKEN0 Mask */ + +#define EPWM_MSKEN_MSKEN1_Pos (1) /*!< EPWM_T::MSKEN: MSKEN1 Position */ +#define EPWM_MSKEN_MSKEN1_Msk (0x1ul << EPWM_MSKEN_MSKEN1_Pos) /*!< EPWM_T::MSKEN: MSKEN1 Mask */ + +#define EPWM_MSKEN_MSKEN2_Pos (2) /*!< EPWM_T::MSKEN: MSKEN2 Position */ +#define EPWM_MSKEN_MSKEN2_Msk (0x1ul << EPWM_MSKEN_MSKEN2_Pos) /*!< EPWM_T::MSKEN: MSKEN2 Mask */ + +#define EPWM_MSKEN_MSKEN3_Pos (3) /*!< EPWM_T::MSKEN: MSKEN3 Position */ +#define EPWM_MSKEN_MSKEN3_Msk (0x1ul << EPWM_MSKEN_MSKEN3_Pos) /*!< EPWM_T::MSKEN: MSKEN3 Mask */ + +#define EPWM_MSKEN_MSKEN4_Pos (4) /*!< EPWM_T::MSKEN: MSKEN4 Position */ +#define EPWM_MSKEN_MSKEN4_Msk (0x1ul << EPWM_MSKEN_MSKEN4_Pos) /*!< EPWM_T::MSKEN: MSKEN4 Mask */ + +#define EPWM_MSKEN_MSKEN5_Pos (5) /*!< EPWM_T::MSKEN: MSKEN5 Position */ +#define EPWM_MSKEN_MSKEN5_Msk (0x1ul << EPWM_MSKEN_MSKEN5_Pos) /*!< EPWM_T::MSKEN: MSKEN5 Mask */ + +#define EPWM_MSK_MSKDAT0_Pos (0) /*!< EPWM_T::MSK: MSKDAT0 Position */ +#define EPWM_MSK_MSKDAT0_Msk (0x1ul << EPWM_MSK_MSKDAT0_Pos) /*!< EPWM_T::MSK: MSKDAT0 Mask */ + +#define EPWM_MSK_MSKDAT1_Pos (1) /*!< EPWM_T::MSK: MSKDAT1 Position */ +#define EPWM_MSK_MSKDAT1_Msk (0x1ul << EPWM_MSK_MSKDAT1_Pos) /*!< EPWM_T::MSK: MSKDAT1 Mask */ + +#define EPWM_MSK_MSKDAT2_Pos (2) /*!< EPWM_T::MSK: MSKDAT2 Position */ +#define EPWM_MSK_MSKDAT2_Msk (0x1ul << EPWM_MSK_MSKDAT2_Pos) /*!< EPWM_T::MSK: MSKDAT2 Mask */ + +#define EPWM_MSK_MSKDAT3_Pos (3) /*!< EPWM_T::MSK: MSKDAT3 Position */ +#define EPWM_MSK_MSKDAT3_Msk (0x1ul << EPWM_MSK_MSKDAT3_Pos) /*!< EPWM_T::MSK: MSKDAT3 Mask */ + +#define EPWM_MSK_MSKDAT4_Pos (4) /*!< EPWM_T::MSK: MSKDAT4 Position */ +#define EPWM_MSK_MSKDAT4_Msk (0x1ul << EPWM_MSK_MSKDAT4_Pos) /*!< EPWM_T::MSK: MSKDAT4 Mask */ + +#define EPWM_MSK_MSKDAT5_Pos (5) /*!< EPWM_T::MSK: MSKDAT5 Position */ +#define EPWM_MSK_MSKDAT5_Msk (0x1ul << EPWM_MSK_MSKDAT5_Pos) /*!< EPWM_T::MSK: MSKDAT5 Mask */ + +#define EPWM_BNF_BRK0NFEN_Pos (0) /*!< EPWM_T::BNF: BRK0NFEN Position */ +#define EPWM_BNF_BRK0NFEN_Msk (0x1ul << EPWM_BNF_BRK0NFEN_Pos) /*!< EPWM_T::BNF: BRK0NFEN Mask */ + +#define EPWM_BNF_BRK0NFSEL_Pos (1) /*!< EPWM_T::BNF: BRK0NFSEL Position */ +#define EPWM_BNF_BRK0NFSEL_Msk (0x7ul << EPWM_BNF_BRK0NFSEL_Pos) /*!< EPWM_T::BNF: BRK0NFSEL Mask */ + +#define EPWM_BNF_BRK0FCNT_Pos (4) /*!< EPWM_T::BNF: BRK0FCNT Position */ +#define EPWM_BNF_BRK0FCNT_Msk (0x7ul << EPWM_BNF_BRK0FCNT_Pos) /*!< EPWM_T::BNF: BRK0FCNT Mask */ + +#define EPWM_BNF_BRK0PINV_Pos (7) /*!< EPWM_T::BNF: BRK0PINV Position */ +#define EPWM_BNF_BRK0PINV_Msk (0x1ul << EPWM_BNF_BRK0PINV_Pos) /*!< EPWM_T::BNF: BRK0PINV Mask */ + +#define EPWM_BNF_BRK1NFEN_Pos (8) /*!< EPWM_T::BNF: BRK1NFEN Position */ +#define EPWM_BNF_BRK1NFEN_Msk (0x1ul << EPWM_BNF_BRK1NFEN_Pos) /*!< EPWM_T::BNF: BRK1NFEN Mask */ + +#define EPWM_BNF_BRK1NFSEL_Pos (9) /*!< EPWM_T::BNF: BRK1NFSEL Position */ +#define EPWM_BNF_BRK1NFSEL_Msk (0x7ul << EPWM_BNF_BRK1NFSEL_Pos) /*!< EPWM_T::BNF: BRK1NFSEL Mask */ + +#define EPWM_BNF_BRK1FCNT_Pos (12) /*!< EPWM_T::BNF: BRK1FCNT Position */ +#define EPWM_BNF_BRK1FCNT_Msk (0x7ul << EPWM_BNF_BRK1FCNT_Pos) /*!< EPWM_T::BNF: BRK1FCNT Mask */ + +#define EPWM_BNF_BRK1PINV_Pos (15) /*!< EPWM_T::BNF: BRK1PINV Position */ +#define EPWM_BNF_BRK1PINV_Msk (0x1ul << EPWM_BNF_BRK1PINV_Pos) /*!< EPWM_T::BNF: BRK1PINV Mask */ + +#define EPWM_BNF_BK0SRC_Pos (16) /*!< EPWM_T::BNF: BK0SRC Position */ +#define EPWM_BNF_BK0SRC_Msk (0x1ul << EPWM_BNF_BK0SRC_Pos) /*!< EPWM_T::BNF: BK0SRC Mask */ + +#define EPWM_BNF_BK1SRC_Pos (24) /*!< EPWM_T::BNF: BK1SRC Position */ +#define EPWM_BNF_BK1SRC_Msk (0x1ul << EPWM_BNF_BK1SRC_Pos) /*!< EPWM_T::BNF: BK1SRC Mask */ + +#define EPWM_FAILBRK_CSSBRKEN_Pos (0) /*!< EPWM_T::FAILBRK: CSSBRKEN Position */ +#define EPWM_FAILBRK_CSSBRKEN_Msk (0x1ul << EPWM_FAILBRK_CSSBRKEN_Pos) /*!< EPWM_T::FAILBRK: CSSBRKEN Mask */ + +#define EPWM_FAILBRK_BODBRKEN_Pos (1) /*!< EPWM_T::FAILBRK: BODBRKEN Position */ +#define EPWM_FAILBRK_BODBRKEN_Msk (0x1ul << EPWM_FAILBRK_BODBRKEN_Pos) /*!< EPWM_T::FAILBRK: BODBRKEN Mask */ + +#define EPWM_FAILBRK_RAMBRKEN_Pos (2) /*!< EPWM_T::FAILBRK: RAMBRKEN Position */ +#define EPWM_FAILBRK_RAMBRKEN_Msk (0x1ul << EPWM_FAILBRK_RAMBRKEN_Pos) /*!< EPWM_T::FAILBRK: RAMBRKEN Mask */ + +#define EPWM_FAILBRK_CORBRKEN_Pos (3) /*!< EPWM_T::FAILBRK: CORBRKEN Position */ +#define EPWM_FAILBRK_CORBRKEN_Msk (0x1ul << EPWM_FAILBRK_CORBRKEN_Pos) /*!< EPWM_T::FAILBRK: CORBRKEN Mask */ + +#define EPWM_BRKCTL0_1_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL0_1: CPO0EBEN Position */ +#define EPWM_BRKCTL0_1_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO0EBEN Mask */ + +#define EPWM_BRKCTL0_1_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL0_1: CPO1EBEN Position */ +#define EPWM_BRKCTL0_1_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO1EBEN Mask */ + +#define EPWM_BRKCTL0_1_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL0_1: BRKP0EEN Position */ +#define EPWM_BRKCTL0_1_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP0EEN Mask */ + +#define EPWM_BRKCTL0_1_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL0_1: BRKP1EEN Position */ +#define EPWM_BRKCTL0_1_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP1EEN Mask */ + +#define EPWM_BRKCTL0_1_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL0_1: SYSEBEN Position */ +#define EPWM_BRKCTL0_1_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL0_1_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL0_1: SYSEBEN Mask */ + +#define EPWM_BRKCTL0_1_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL0_1: CPO0LBEN Position */ +#define EPWM_BRKCTL0_1_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO0LBEN Mask */ + +#define EPWM_BRKCTL0_1_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL0_1: CPO1LBEN Position */ +#define EPWM_BRKCTL0_1_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO1LBEN Mask */ + +#define EPWM_BRKCTL0_1_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL0_1: BRKP0LEN Position */ +#define EPWM_BRKCTL0_1_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP0LEN Mask */ + +#define EPWM_BRKCTL0_1_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL0_1: BRKP1LEN Position */ +#define EPWM_BRKCTL0_1_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP1LEN Mask */ + +#define EPWM_BRKCTL0_1_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL0_1: SYSLBEN Position */ +#define EPWM_BRKCTL0_1_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL0_1_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL0_1: SYSLBEN Mask */ + +#define EPWM_BRKCTL0_1_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL0_1: BRKAEVEN Position */ +#define EPWM_BRKCTL0_1_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL0_1_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKAEVEN Mask */ + +#define EPWM_BRKCTL0_1_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL0_1: BRKAODD Position */ +#define EPWM_BRKCTL0_1_BRKAODD_Msk (0x3ul << EPWM_BRKCTL0_1_BRKAODD_Pos) /*!< EPWM_T::BRKCTL0_1: BRKAODD Mask */ + +#define EPWM_BRKCTL0_1_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL0_1: EADCEBEN Position */ +#define EPWM_BRKCTL0_1_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL0_1: EADCEBEN Mask */ + +#define EPWM_BRKCTL0_1_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL0_1: EADCLBEN Position */ +#define EPWM_BRKCTL0_1_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL0_1: EADCLBEN Mask */ + +#define EPWM_BRKCTL2_3_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL2_3: CPO0EBEN Position */ +#define EPWM_BRKCTL2_3_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO0EBEN Mask */ + +#define EPWM_BRKCTL2_3_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL2_3: CPO1EBEN Position */ +#define EPWM_BRKCTL2_3_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO1EBEN Mask */ + +#define EPWM_BRKCTL2_3_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL2_3: BRKP0EEN Position */ +#define EPWM_BRKCTL2_3_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP0EEN Mask */ + +#define EPWM_BRKCTL2_3_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL2_3: BRKP1EEN Position */ +#define EPWM_BRKCTL2_3_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP1EEN Mask */ + +#define EPWM_BRKCTL2_3_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL2_3: SYSEBEN Position */ +#define EPWM_BRKCTL2_3_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL2_3_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL2_3: SYSEBEN Mask */ + +#define EPWM_BRKCTL2_3_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL2_3: CPO0LBEN Position */ +#define EPWM_BRKCTL2_3_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO0LBEN Mask */ + +#define EPWM_BRKCTL2_3_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL2_3: CPO1LBEN Position */ +#define EPWM_BRKCTL2_3_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO1LBEN Mask */ + +#define EPWM_BRKCTL2_3_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL2_3: BRKP0LEN Position */ +#define EPWM_BRKCTL2_3_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP0LEN Mask */ + +#define EPWM_BRKCTL2_3_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL2_3: BRKP1LEN Position */ +#define EPWM_BRKCTL2_3_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP1LEN Mask */ + +#define EPWM_BRKCTL2_3_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL2_3: SYSLBEN Position */ +#define EPWM_BRKCTL2_3_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL2_3_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL2_3: SYSLBEN Mask */ + +#define EPWM_BRKCTL2_3_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL2_3: BRKAEVEN Position */ +#define EPWM_BRKCTL2_3_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL2_3_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKAEVEN Mask */ + +#define EPWM_BRKCTL2_3_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL2_3: BRKAODD Position */ +#define EPWM_BRKCTL2_3_BRKAODD_Msk (0x3ul << EPWM_BRKCTL2_3_BRKAODD_Pos) /*!< EPWM_T::BRKCTL2_3: BRKAODD Mask */ + +#define EPWM_BRKCTL2_3_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL2_3: EADCEBEN Position */ +#define EPWM_BRKCTL2_3_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL2_3: EADCEBEN Mask */ + +#define EPWM_BRKCTL2_3_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL2_3: EADCLBEN Position */ +#define EPWM_BRKCTL2_3_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL2_3: EADCLBEN Mask */ + +#define EPWM_BRKCTL4_5_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL4_5: CPO0EBEN Position */ +#define EPWM_BRKCTL4_5_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO0EBEN Mask */ + +#define EPWM_BRKCTL4_5_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL4_5: CPO1EBEN Position */ +#define EPWM_BRKCTL4_5_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO1EBEN Mask */ + +#define EPWM_BRKCTL4_5_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL4_5: BRKP0EEN Position */ +#define EPWM_BRKCTL4_5_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP0EEN Mask */ + +#define EPWM_BRKCTL4_5_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL4_5: BRKP1EEN Position */ +#define EPWM_BRKCTL4_5_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP1EEN Mask */ + +#define EPWM_BRKCTL4_5_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL4_5: SYSEBEN Position */ +#define EPWM_BRKCTL4_5_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL4_5_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL4_5: SYSEBEN Mask */ + +#define EPWM_BRKCTL4_5_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL4_5: CPO0LBEN Position */ +#define EPWM_BRKCTL4_5_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO0LBEN Mask */ + +#define EPWM_BRKCTL4_5_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL4_5: CPO1LBEN Position */ +#define EPWM_BRKCTL4_5_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO1LBEN Mask */ + +#define EPWM_BRKCTL4_5_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL4_5: BRKP0LEN Position */ +#define EPWM_BRKCTL4_5_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP0LEN Mask */ + +#define EPWM_BRKCTL4_5_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL4_5: BRKP1LEN Position */ +#define EPWM_BRKCTL4_5_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP1LEN Mask */ + +#define EPWM_BRKCTL4_5_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL4_5: SYSLBEN Position */ +#define EPWM_BRKCTL4_5_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL4_5_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL4_5: SYSLBEN Mask */ + +#define EPWM_BRKCTL4_5_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL4_5: BRKAEVEN Position */ +#define EPWM_BRKCTL4_5_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL4_5_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKAEVEN Mask */ + +#define EPWM_BRKCTL4_5_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL4_5: BRKAODD Position */ +#define EPWM_BRKCTL4_5_BRKAODD_Msk (0x3ul << EPWM_BRKCTL4_5_BRKAODD_Pos) /*!< EPWM_T::BRKCTL4_5: BRKAODD Mask */ + +#define EPWM_BRKCTL4_5_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL4_5: EADCEBEN Position */ +#define EPWM_BRKCTL4_5_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL4_5: EADCEBEN Mask */ + +#define EPWM_BRKCTL4_5_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL4_5: EADCLBEN Position */ +#define EPWM_BRKCTL4_5_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL4_5: EADCLBEN Mask */ + +#define EPWM_POLCTL_PINV0_Pos (0) /*!< EPWM_T::POLCTL: PINV0 Position */ +#define EPWM_POLCTL_PINV0_Msk (0x1ul << EPWM_POLCTL_PINV0_Pos) /*!< EPWM_T::POLCTL: PINV0 Mask */ + +#define EPWM_POLCTL_PINV1_Pos (1) /*!< EPWM_T::POLCTL: PINV1 Position */ +#define EPWM_POLCTL_PINV1_Msk (0x1ul << EPWM_POLCTL_PINV1_Pos) /*!< EPWM_T::POLCTL: PINV1 Mask */ + +#define EPWM_POLCTL_PINV2_Pos (2) /*!< EPWM_T::POLCTL: PINV2 Position */ +#define EPWM_POLCTL_PINV2_Msk (0x1ul << EPWM_POLCTL_PINV2_Pos) /*!< EPWM_T::POLCTL: PINV2 Mask */ + +#define EPWM_POLCTL_PINV3_Pos (3) /*!< EPWM_T::POLCTL: PINV3 Position */ +#define EPWM_POLCTL_PINV3_Msk (0x1ul << EPWM_POLCTL_PINV3_Pos) /*!< EPWM_T::POLCTL: PINV3 Mask */ + +#define EPWM_POLCTL_PINV4_Pos (4) /*!< EPWM_T::POLCTL: PINV4 Position */ +#define EPWM_POLCTL_PINV4_Msk (0x1ul << EPWM_POLCTL_PINV4_Pos) /*!< EPWM_T::POLCTL: PINV4 Mask */ + +#define EPWM_POLCTL_PINV5_Pos (5) /*!< EPWM_T::POLCTL: PINV5 Position */ +#define EPWM_POLCTL_PINV5_Msk (0x1ul << EPWM_POLCTL_PINV5_Pos) /*!< EPWM_T::POLCTL: PINV5 Mask */ + +#define EPWM_POEN_POEN0_Pos (0) /*!< EPWM_T::POEN: POEN0 Position */ +#define EPWM_POEN_POEN0_Msk (0x1ul << EPWM_POEN_POEN0_Pos) /*!< EPWM_T::POEN: POEN0 Mask */ + +#define EPWM_POEN_POEN1_Pos (1) /*!< EPWM_T::POEN: POEN1 Position */ +#define EPWM_POEN_POEN1_Msk (0x1ul << EPWM_POEN_POEN1_Pos) /*!< EPWM_T::POEN: POEN1 Mask */ + +#define EPWM_POEN_POEN2_Pos (2) /*!< EPWM_T::POEN: POEN2 Position */ +#define EPWM_POEN_POEN2_Msk (0x1ul << EPWM_POEN_POEN2_Pos) /*!< EPWM_T::POEN: POEN2 Mask */ + +#define EPWM_POEN_POEN3_Pos (3) /*!< EPWM_T::POEN: POEN3 Position */ +#define EPWM_POEN_POEN3_Msk (0x1ul << EPWM_POEN_POEN3_Pos) /*!< EPWM_T::POEN: POEN3 Mask */ + +#define EPWM_POEN_POEN4_Pos (4) /*!< EPWM_T::POEN: POEN4 Position */ +#define EPWM_POEN_POEN4_Msk (0x1ul << EPWM_POEN_POEN4_Pos) /*!< EPWM_T::POEN: POEN4 Mask */ + +#define EPWM_POEN_POEN5_Pos (5) /*!< EPWM_T::POEN: POEN5 Position */ +#define EPWM_POEN_POEN5_Msk (0x1ul << EPWM_POEN_POEN5_Pos) /*!< EPWM_T::POEN: POEN5 Mask */ + +#define EPWM_SWBRK_BRKETRG0_Pos (0) /*!< EPWM_T::SWBRK: BRKETRG0 Position */ +#define EPWM_SWBRK_BRKETRG0_Msk (0x1ul << EPWM_SWBRK_BRKETRG0_Pos) /*!< EPWM_T::SWBRK: BRKETRG0 Mask */ + +#define EPWM_SWBRK_BRKETRG2_Pos (1) /*!< EPWM_T::SWBRK: BRKETRG2 Position */ +#define EPWM_SWBRK_BRKETRG2_Msk (0x1ul << EPWM_SWBRK_BRKETRG2_Pos) /*!< EPWM_T::SWBRK: BRKETRG2 Mask */ + +#define EPWM_SWBRK_BRKETRG4_Pos (2) /*!< EPWM_T::SWBRK: BRKETRG4 Position */ +#define EPWM_SWBRK_BRKETRG4_Msk (0x1ul << EPWM_SWBRK_BRKETRG4_Pos) /*!< EPWM_T::SWBRK: BRKETRG4 Mask */ + +#define EPWM_SWBRK_BRKLTRG0_Pos (8) /*!< EPWM_T::SWBRK: BRKLTRG0 Position */ +#define EPWM_SWBRK_BRKLTRG0_Msk (0x1ul << EPWM_SWBRK_BRKLTRG0_Pos) /*!< EPWM_T::SWBRK: BRKLTRG0 Mask */ + +#define EPWM_SWBRK_BRKLTRG2_Pos (9) /*!< EPWM_T::SWBRK: BRKLTRG2 Position */ +#define EPWM_SWBRK_BRKLTRG2_Msk (0x1ul << EPWM_SWBRK_BRKLTRG2_Pos) /*!< EPWM_T::SWBRK: BRKLTRG2 Mask */ + +#define EPWM_SWBRK_BRKLTRG4_Pos (10) /*!< EPWM_T::SWBRK: BRKLTRG4 Position */ +#define EPWM_SWBRK_BRKLTRG4_Msk (0x1ul << EPWM_SWBRK_BRKLTRG4_Pos) /*!< EPWM_T::SWBRK: BRKLTRG4 Mask */ + +#define EPWM_INTEN0_ZIEN0_Pos (0) /*!< EPWM_T::INTEN0: ZIEN0 Position */ +#define EPWM_INTEN0_ZIEN0_Msk (0x1ul << EPWM_INTEN0_ZIEN0_Pos) /*!< EPWM_T::INTEN0: ZIEN0 Mask */ + +#define EPWM_INTEN0_ZIEN1_Pos (1) /*!< EPWM_T::INTEN0: ZIEN1 Position */ +#define EPWM_INTEN0_ZIEN1_Msk (0x1ul << EPWM_INTEN0_ZIEN1_Pos) /*!< EPWM_T::INTEN0: ZIEN1 Mask */ + +#define EPWM_INTEN0_ZIEN2_Pos (2) /*!< EPWM_T::INTEN0: ZIEN2 Position */ +#define EPWM_INTEN0_ZIEN2_Msk (0x1ul << EPWM_INTEN0_ZIEN2_Pos) /*!< EPWM_T::INTEN0: ZIEN2 Mask */ + +#define EPWM_INTEN0_ZIEN3_Pos (3) /*!< EPWM_T::INTEN0: ZIEN3 Position */ +#define EPWM_INTEN0_ZIEN3_Msk (0x1ul << EPWM_INTEN0_ZIEN3_Pos) /*!< EPWM_T::INTEN0: ZIEN3 Mask */ + +#define EPWM_INTEN0_ZIEN4_Pos (4) /*!< EPWM_T::INTEN0: ZIEN4 Position */ +#define EPWM_INTEN0_ZIEN4_Msk (0x1ul << EPWM_INTEN0_ZIEN4_Pos) /*!< EPWM_T::INTEN0: ZIEN4 Mask */ + +#define EPWM_INTEN0_ZIEN5_Pos (5) /*!< EPWM_T::INTEN0: ZIEN5 Position */ +#define EPWM_INTEN0_ZIEN5_Msk (0x1ul << EPWM_INTEN0_ZIEN5_Pos) /*!< EPWM_T::INTEN0: ZIEN5 Mask */ + +#define EPWM_INTEN0_PIEN0_Pos (8) /*!< EPWM_T::INTEN0: PIEN0 Position */ +#define EPWM_INTEN0_PIEN0_Msk (0x1ul << EPWM_INTEN0_PIEN0_Pos) /*!< EPWM_T::INTEN0: PIEN0 Mask */ + +#define EPWM_INTEN0_PIEN1_Pos (9) /*!< EPWM_T::INTEN0: PIEN1 Position */ +#define EPWM_INTEN0_PIEN1_Msk (0x1ul << EPWM_INTEN0_PIEN1_Pos) /*!< EPWM_T::INTEN0: PIEN1 Mask */ + +#define EPWM_INTEN0_PIEN2_Pos (10) /*!< EPWM_T::INTEN0: PIEN2 Position */ +#define EPWM_INTEN0_PIEN2_Msk (0x1ul << EPWM_INTEN0_PIEN2_Pos) /*!< EPWM_T::INTEN0: PIEN2 Mask */ + +#define EPWM_INTEN0_PIEN3_Pos (11) /*!< EPWM_T::INTEN0: PIEN3 Position */ +#define EPWM_INTEN0_PIEN3_Msk (0x1ul << EPWM_INTEN0_PIEN3_Pos) /*!< EPWM_T::INTEN0: PIEN3 Mask */ + +#define EPWM_INTEN0_PIEN4_Pos (12) /*!< EPWM_T::INTEN0: PIEN4 Position */ +#define EPWM_INTEN0_PIEN4_Msk (0x1ul << EPWM_INTEN0_PIEN4_Pos) /*!< EPWM_T::INTEN0: PIEN4 Mask */ + +#define EPWM_INTEN0_PIEN5_Pos (13) /*!< EPWM_T::INTEN0: PIEN5 Position */ +#define EPWM_INTEN0_PIEN5_Msk (0x1ul << EPWM_INTEN0_PIEN5_Pos) /*!< EPWM_T::INTEN0: PIEN5 Mask */ + +#define EPWM_INTEN0_CMPUIEN0_Pos (16) /*!< EPWM_T::INTEN0: CMPUIEN0 Position */ +#define EPWM_INTEN0_CMPUIEN0_Msk (0x1ul << EPWM_INTEN0_CMPUIEN0_Pos) /*!< EPWM_T::INTEN0: CMPUIEN0 Mask */ + +#define EPWM_INTEN0_CMPUIEN1_Pos (17) /*!< EPWM_T::INTEN0: CMPUIEN1 Position */ +#define EPWM_INTEN0_CMPUIEN1_Msk (0x1ul << EPWM_INTEN0_CMPUIEN1_Pos) /*!< EPWM_T::INTEN0: CMPUIEN1 Mask */ + +#define EPWM_INTEN0_CMPUIEN2_Pos (18) /*!< EPWM_T::INTEN0: CMPUIEN2 Position */ +#define EPWM_INTEN0_CMPUIEN2_Msk (0x1ul << EPWM_INTEN0_CMPUIEN2_Pos) /*!< EPWM_T::INTEN0: CMPUIEN2 Mask */ + +#define EPWM_INTEN0_CMPUIEN3_Pos (19) /*!< EPWM_T::INTEN0: CMPUIEN3 Position */ +#define EPWM_INTEN0_CMPUIEN3_Msk (0x1ul << EPWM_INTEN0_CMPUIEN3_Pos) /*!< EPWM_T::INTEN0: CMPUIEN3 Mask */ + +#define EPWM_INTEN0_CMPUIEN4_Pos (20) /*!< EPWM_T::INTEN0: CMPUIEN4 Position */ +#define EPWM_INTEN0_CMPUIEN4_Msk (0x1ul << EPWM_INTEN0_CMPUIEN4_Pos) /*!< EPWM_T::INTEN0: CMPUIEN4 Mask */ + +#define EPWM_INTEN0_CMPUIEN5_Pos (21) /*!< EPWM_T::INTEN0: CMPUIEN5 Position */ +#define EPWM_INTEN0_CMPUIEN5_Msk (0x1ul << EPWM_INTEN0_CMPUIEN5_Pos) /*!< EPWM_T::INTEN0: CMPUIEN5 Mask */ + +#define EPWM_INTEN0_CMPDIEN0_Pos (24) /*!< EPWM_T::INTEN0: CMPDIEN0 Position */ +#define EPWM_INTEN0_CMPDIEN0_Msk (0x1ul << EPWM_INTEN0_CMPDIEN0_Pos) /*!< EPWM_T::INTEN0: CMPDIEN0 Mask */ + +#define EPWM_INTEN0_CMPDIEN1_Pos (25) /*!< EPWM_T::INTEN0: CMPDIEN1 Position */ +#define EPWM_INTEN0_CMPDIEN1_Msk (0x1ul << EPWM_INTEN0_CMPDIEN1_Pos) /*!< EPWM_T::INTEN0: CMPDIEN1 Mask */ + +#define EPWM_INTEN0_CMPDIEN2_Pos (26) /*!< EPWM_T::INTEN0: CMPDIEN2 Position */ +#define EPWM_INTEN0_CMPDIEN2_Msk (0x1ul << EPWM_INTEN0_CMPDIEN2_Pos) /*!< EPWM_T::INTEN0: CMPDIEN2 Mask */ + +#define EPWM_INTEN0_CMPDIEN3_Pos (27) /*!< EPWM_T::INTEN0: CMPDIEN3 Position */ +#define EPWM_INTEN0_CMPDIEN3_Msk (0x1ul << EPWM_INTEN0_CMPDIEN3_Pos) /*!< EPWM_T::INTEN0: CMPDIEN3 Mask */ + +#define EPWM_INTEN0_CMPDIEN4_Pos (28) /*!< EPWM_T::INTEN0: CMPDIEN4 Position */ +#define EPWM_INTEN0_CMPDIEN4_Msk (0x1ul << EPWM_INTEN0_CMPDIEN4_Pos) /*!< EPWM_T::INTEN0: CMPDIEN4 Mask */ + +#define EPWM_INTEN0_CMPDIEN5_Pos (29) /*!< EPWM_T::INTEN0: CMPDIEN5 Position */ +#define EPWM_INTEN0_CMPDIEN5_Msk (0x1ul << EPWM_INTEN0_CMPDIEN5_Pos) /*!< EPWM_T::INTEN0: CMPDIEN5 Mask */ + +#define EPWM_INTEN1_BRKEIEN0_1_Pos (0) /*!< EPWM_T::INTEN1: BRKEIEN0_1 Position */ +#define EPWM_INTEN1_BRKEIEN0_1_Msk (0x1ul << EPWM_INTEN1_BRKEIEN0_1_Pos) /*!< EPWM_T::INTEN1: BRKEIEN0_1 Mask */ + +#define EPWM_INTEN1_BRKEIEN2_3_Pos (1) /*!< EPWM_T::INTEN1: BRKEIEN2_3 Position */ +#define EPWM_INTEN1_BRKEIEN2_3_Msk (0x1ul << EPWM_INTEN1_BRKEIEN2_3_Pos) /*!< EPWM_T::INTEN1: BRKEIEN2_3 Mask */ + +#define EPWM_INTEN1_BRKEIEN4_5_Pos (2) /*!< EPWM_T::INTEN1: BRKEIEN4_5 Position */ +#define EPWM_INTEN1_BRKEIEN4_5_Msk (0x1ul << EPWM_INTEN1_BRKEIEN4_5_Pos) /*!< EPWM_T::INTEN1: BRKEIEN4_5 Mask */ + +#define EPWM_INTEN1_BRKLIEN0_1_Pos (8) /*!< EPWM_T::INTEN1: BRKLIEN0_1 Position */ +#define EPWM_INTEN1_BRKLIEN0_1_Msk (0x1ul << EPWM_INTEN1_BRKLIEN0_1_Pos) /*!< EPWM_T::INTEN1: BRKLIEN0_1 Mask */ + +#define EPWM_INTEN1_BRKLIEN2_3_Pos (9) /*!< EPWM_T::INTEN1: BRKLIEN2_3 Position */ +#define EPWM_INTEN1_BRKLIEN2_3_Msk (0x1ul << EPWM_INTEN1_BRKLIEN2_3_Pos) /*!< EPWM_T::INTEN1: BRKLIEN2_3 Mask */ + +#define EPWM_INTEN1_BRKLIEN4_5_Pos (10) /*!< EPWM_T::INTEN1: BRKLIEN4_5 Position */ +#define EPWM_INTEN1_BRKLIEN4_5_Msk (0x1ul << EPWM_INTEN1_BRKLIEN4_5_Pos) /*!< EPWM_T::INTEN1: BRKLIEN4_5 Mask */ + +#define EPWM_INTSTS0_ZIF0_Pos (0) /*!< EPWM_T::INTSTS0: ZIF0 Position */ +#define EPWM_INTSTS0_ZIF0_Msk (0x1ul << EPWM_INTSTS0_ZIF0_Pos) /*!< EPWM_T::INTSTS0: ZIF0 Mask */ + +#define EPWM_INTSTS0_ZIF1_Pos (1) /*!< EPWM_T::INTSTS0: ZIF1 Position */ +#define EPWM_INTSTS0_ZIF1_Msk (0x1ul << EPWM_INTSTS0_ZIF1_Pos) /*!< EPWM_T::INTSTS0: ZIF1 Mask */ + +#define EPWM_INTSTS0_ZIF2_Pos (2) /*!< EPWM_T::INTSTS0: ZIF2 Position */ +#define EPWM_INTSTS0_ZIF2_Msk (0x1ul << EPWM_INTSTS0_ZIF2_Pos) /*!< EPWM_T::INTSTS0: ZIF2 Mask */ + +#define EPWM_INTSTS0_ZIF3_Pos (3) /*!< EPWM_T::INTSTS0: ZIF3 Position */ +#define EPWM_INTSTS0_ZIF3_Msk (0x1ul << EPWM_INTSTS0_ZIF3_Pos) /*!< EPWM_T::INTSTS0: ZIF3 Mask */ + +#define EPWM_INTSTS0_ZIF4_Pos (4) /*!< EPWM_T::INTSTS0: ZIF4 Position */ +#define EPWM_INTSTS0_ZIF4_Msk (0x1ul << EPWM_INTSTS0_ZIF4_Pos) /*!< EPWM_T::INTSTS0: ZIF4 Mask */ + +#define EPWM_INTSTS0_ZIF5_Pos (5) /*!< EPWM_T::INTSTS0: ZIF5 Position */ +#define EPWM_INTSTS0_ZIF5_Msk (0x1ul << EPWM_INTSTS0_ZIF5_Pos) /*!< EPWM_T::INTSTS0: ZIF5 Mask */ + +#define EPWM_INTSTS0_PIF0_Pos (8) /*!< EPWM_T::INTSTS0: PIF0 Position */ +#define EPWM_INTSTS0_PIF0_Msk (0x1ul << EPWM_INTSTS0_PIF0_Pos) /*!< EPWM_T::INTSTS0: PIF0 Mask */ + +#define EPWM_INTSTS0_PIF1_Pos (9) /*!< EPWM_T::INTSTS0: PIF1 Position */ +#define EPWM_INTSTS0_PIF1_Msk (0x1ul << EPWM_INTSTS0_PIF1_Pos) /*!< EPWM_T::INTSTS0: PIF1 Mask */ + +#define EPWM_INTSTS0_PIF2_Pos (10) /*!< EPWM_T::INTSTS0: PIF2 Position */ +#define EPWM_INTSTS0_PIF2_Msk (0x1ul << EPWM_INTSTS0_PIF2_Pos) /*!< EPWM_T::INTSTS0: PIF2 Mask */ + +#define EPWM_INTSTS0_PIF3_Pos (11) /*!< EPWM_T::INTSTS0: PIF3 Position */ +#define EPWM_INTSTS0_PIF3_Msk (0x1ul << EPWM_INTSTS0_PIF3_Pos) /*!< EPWM_T::INTSTS0: PIF3 Mask */ + +#define EPWM_INTSTS0_PIF4_Pos (12) /*!< EPWM_T::INTSTS0: PIF4 Position */ +#define EPWM_INTSTS0_PIF4_Msk (0x1ul << EPWM_INTSTS0_PIF4_Pos) /*!< EPWM_T::INTSTS0: PIF4 Mask */ + +#define EPWM_INTSTS0_PIF5_Pos (13) /*!< EPWM_T::INTSTS0: PIF5 Position */ +#define EPWM_INTSTS0_PIF5_Msk (0x1ul << EPWM_INTSTS0_PIF5_Pos) /*!< EPWM_T::INTSTS0: PIF5 Mask */ + +#define EPWM_INTSTS0_CMPUIF0_Pos (16) /*!< EPWM_T::INTSTS0: CMPUIF0 Position */ +#define EPWM_INTSTS0_CMPUIF0_Msk (0x1ul << EPWM_INTSTS0_CMPUIF0_Pos) /*!< EPWM_T::INTSTS0: CMPUIF0 Mask */ + +#define EPWM_INTSTS0_CMPUIF1_Pos (17) /*!< EPWM_T::INTSTS0: CMPUIF1 Position */ +#define EPWM_INTSTS0_CMPUIF1_Msk (0x1ul << EPWM_INTSTS0_CMPUIF1_Pos) /*!< EPWM_T::INTSTS0: CMPUIF1 Mask */ + +#define EPWM_INTSTS0_CMPUIF2_Pos (18) /*!< EPWM_T::INTSTS0: CMPUIF2 Position */ +#define EPWM_INTSTS0_CMPUIF2_Msk (0x1ul << EPWM_INTSTS0_CMPUIF2_Pos) /*!< EPWM_T::INTSTS0: CMPUIF2 Mask */ + +#define EPWM_INTSTS0_CMPUIF3_Pos (19) /*!< EPWM_T::INTSTS0: CMPUIF3 Position */ +#define EPWM_INTSTS0_CMPUIF3_Msk (0x1ul << EPWM_INTSTS0_CMPUIF3_Pos) /*!< EPWM_T::INTSTS0: CMPUIF3 Mask */ + +#define EPWM_INTSTS0_CMPUIF4_Pos (20) /*!< EPWM_T::INTSTS0: CMPUIF4 Position */ +#define EPWM_INTSTS0_CMPUIF4_Msk (0x1ul << EPWM_INTSTS0_CMPUIF4_Pos) /*!< EPWM_T::INTSTS0: CMPUIF4 Mask */ + +#define EPWM_INTSTS0_CMPUIF5_Pos (21) /*!< EPWM_T::INTSTS0: CMPUIF5 Position */ +#define EPWM_INTSTS0_CMPUIF5_Msk (0x1ul << EPWM_INTSTS0_CMPUIF5_Pos) /*!< EPWM_T::INTSTS0: CMPUIF5 Mask */ + +#define EPWM_INTSTS0_CMPDIF0_Pos (24) /*!< EPWM_T::INTSTS0: CMPDIF0 Position */ +#define EPWM_INTSTS0_CMPDIF0_Msk (0x1ul << EPWM_INTSTS0_CMPDIF0_Pos) /*!< EPWM_T::INTSTS0: CMPDIF0 Mask */ + +#define EPWM_INTSTS0_CMPDIF1_Pos (25) /*!< EPWM_T::INTSTS0: CMPDIF1 Position */ +#define EPWM_INTSTS0_CMPDIF1_Msk (0x1ul << EPWM_INTSTS0_CMPDIF1_Pos) /*!< EPWM_T::INTSTS0: CMPDIF1 Mask */ + +#define EPWM_INTSTS0_CMPDIF2_Pos (26) /*!< EPWM_T::INTSTS0: CMPDIF2 Position */ +#define EPWM_INTSTS0_CMPDIF2_Msk (0x1ul << EPWM_INTSTS0_CMPDIF2_Pos) /*!< EPWM_T::INTSTS0: CMPDIF2 Mask */ + +#define EPWM_INTSTS0_CMPDIF3_Pos (27) /*!< EPWM_T::INTSTS0: CMPDIF3 Position */ +#define EPWM_INTSTS0_CMPDIF3_Msk (0x1ul << EPWM_INTSTS0_CMPDIF3_Pos) /*!< EPWM_T::INTSTS0: CMPDIF3 Mask */ + +#define EPWM_INTSTS0_CMPDIF4_Pos (28) /*!< EPWM_T::INTSTS0: CMPDIF4 Position */ +#define EPWM_INTSTS0_CMPDIF4_Msk (0x1ul << EPWM_INTSTS0_CMPDIF4_Pos) /*!< EPWM_T::INTSTS0: CMPDIF4 Mask */ + +#define EPWM_INTSTS0_CMPDIF5_Pos (29) /*!< EPWM_T::INTSTS0: CMPDIF5 Position */ +#define EPWM_INTSTS0_CMPDIF5_Msk (0x1ul << EPWM_INTSTS0_CMPDIF5_Pos) /*!< EPWM_T::INTSTS0: CMPDIF5 Mask */ + +#define EPWM_INTSTS1_BRKEIF0_Pos (0) /*!< EPWM_T::INTSTS1: BRKEIF0 Position */ +#define EPWM_INTSTS1_BRKEIF0_Msk (0x1ul << EPWM_INTSTS1_BRKEIF0_Pos) /*!< EPWM_T::INTSTS1: BRKEIF0 Mask */ + +#define EPWM_INTSTS1_BRKEIF1_Pos (1) /*!< EPWM_T::INTSTS1: BRKEIF1 Position */ +#define EPWM_INTSTS1_BRKEIF1_Msk (0x1ul << EPWM_INTSTS1_BRKEIF1_Pos) /*!< EPWM_T::INTSTS1: BRKEIF1 Mask */ + +#define EPWM_INTSTS1_BRKEIF2_Pos (2) /*!< EPWM_T::INTSTS1: BRKEIF2 Position */ +#define EPWM_INTSTS1_BRKEIF2_Msk (0x1ul << EPWM_INTSTS1_BRKEIF2_Pos) /*!< EPWM_T::INTSTS1: BRKEIF2 Mask */ + +#define EPWM_INTSTS1_BRKEIF3_Pos (3) /*!< EPWM_T::INTSTS1: BRKEIF3 Position */ +#define EPWM_INTSTS1_BRKEIF3_Msk (0x1ul << EPWM_INTSTS1_BRKEIF3_Pos) /*!< EPWM_T::INTSTS1: BRKEIF3 Mask */ + +#define EPWM_INTSTS1_BRKEIF4_Pos (4) /*!< EPWM_T::INTSTS1: BRKEIF4 Position */ +#define EPWM_INTSTS1_BRKEIF4_Msk (0x1ul << EPWM_INTSTS1_BRKEIF4_Pos) /*!< EPWM_T::INTSTS1: BRKEIF4 Mask */ + +#define EPWM_INTSTS1_BRKEIF5_Pos (5) /*!< EPWM_T::INTSTS1: BRKEIF5 Position */ +#define EPWM_INTSTS1_BRKEIF5_Msk (0x1ul << EPWM_INTSTS1_BRKEIF5_Pos) /*!< EPWM_T::INTSTS1: BRKEIF5 Mask */ + +#define EPWM_INTSTS1_BRKLIF0_Pos (8) /*!< EPWM_T::INTSTS1: BRKLIF0 Position */ +#define EPWM_INTSTS1_BRKLIF0_Msk (0x1ul << EPWM_INTSTS1_BRKLIF0_Pos) /*!< EPWM_T::INTSTS1: BRKLIF0 Mask */ + +#define EPWM_INTSTS1_BRKLIF1_Pos (9) /*!< EPWM_T::INTSTS1: BRKLIF1 Position */ +#define EPWM_INTSTS1_BRKLIF1_Msk (0x1ul << EPWM_INTSTS1_BRKLIF1_Pos) /*!< EPWM_T::INTSTS1: BRKLIF1 Mask */ + +#define EPWM_INTSTS1_BRKLIF2_Pos (10) /*!< EPWM_T::INTSTS1: BRKLIF2 Position */ +#define EPWM_INTSTS1_BRKLIF2_Msk (0x1ul << EPWM_INTSTS1_BRKLIF2_Pos) /*!< EPWM_T::INTSTS1: BRKLIF2 Mask */ + +#define EPWM_INTSTS1_BRKLIF3_Pos (11) /*!< EPWM_T::INTSTS1: BRKLIF3 Position */ +#define EPWM_INTSTS1_BRKLIF3_Msk (0x1ul << EPWM_INTSTS1_BRKLIF3_Pos) /*!< EPWM_T::INTSTS1: BRKLIF3 Mask */ + +#define EPWM_INTSTS1_BRKLIF4_Pos (12) /*!< EPWM_T::INTSTS1: BRKLIF4 Position */ +#define EPWM_INTSTS1_BRKLIF4_Msk (0x1ul << EPWM_INTSTS1_BRKLIF4_Pos) /*!< EPWM_T::INTSTS1: BRKLIF4 Mask */ + +#define EPWM_INTSTS1_BRKLIF5_Pos (13) /*!< EPWM_T::INTSTS1: BRKLIF5 Position */ +#define EPWM_INTSTS1_BRKLIF5_Msk (0x1ul << EPWM_INTSTS1_BRKLIF5_Pos) /*!< EPWM_T::INTSTS1: BRKLIF5 Mask */ + +#define EPWM_INTSTS1_BRKESTS0_Pos (16) /*!< EPWM_T::INTSTS1: BRKESTS0 Position */ +#define EPWM_INTSTS1_BRKESTS0_Msk (0x1ul << EPWM_INTSTS1_BRKESTS0_Pos) /*!< EPWM_T::INTSTS1: BRKESTS0 Mask */ + +#define EPWM_INTSTS1_BRKESTS1_Pos (17) /*!< EPWM_T::INTSTS1: BRKESTS1 Position */ +#define EPWM_INTSTS1_BRKESTS1_Msk (0x1ul << EPWM_INTSTS1_BRKESTS1_Pos) /*!< EPWM_T::INTSTS1: BRKESTS1 Mask */ + +#define EPWM_INTSTS1_BRKESTS2_Pos (18) /*!< EPWM_T::INTSTS1: BRKESTS2 Position */ +#define EPWM_INTSTS1_BRKESTS2_Msk (0x1ul << EPWM_INTSTS1_BRKESTS2_Pos) /*!< EPWM_T::INTSTS1: BRKESTS2 Mask */ + +#define EPWM_INTSTS1_BRKESTS3_Pos (19) /*!< EPWM_T::INTSTS1: BRKESTS3 Position */ +#define EPWM_INTSTS1_BRKESTS3_Msk (0x1ul << EPWM_INTSTS1_BRKESTS3_Pos) /*!< EPWM_T::INTSTS1: BRKESTS3 Mask */ + +#define EPWM_INTSTS1_BRKESTS4_Pos (20) /*!< EPWM_T::INTSTS1: BRKESTS4 Position */ +#define EPWM_INTSTS1_BRKESTS4_Msk (0x1ul << EPWM_INTSTS1_BRKESTS4_Pos) /*!< EPWM_T::INTSTS1: BRKESTS4 Mask */ + +#define EPWM_INTSTS1_BRKESTS5_Pos (21) /*!< EPWM_T::INTSTS1: BRKESTS5 Position */ +#define EPWM_INTSTS1_BRKESTS5_Msk (0x1ul << EPWM_INTSTS1_BRKESTS5_Pos) /*!< EPWM_T::INTSTS1: BRKESTS5 Mask */ + +#define EPWM_INTSTS1_BRKLSTS0_Pos (24) /*!< EPWM_T::INTSTS1: BRKLSTS0 Position */ +#define EPWM_INTSTS1_BRKLSTS0_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS0_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS0 Mask */ + +#define EPWM_INTSTS1_BRKLSTS1_Pos (25) /*!< EPWM_T::INTSTS1: BRKLSTS1 Position */ +#define EPWM_INTSTS1_BRKLSTS1_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS1_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS1 Mask */ + +#define EPWM_INTSTS1_BRKLSTS2_Pos (26) /*!< EPWM_T::INTSTS1: BRKLSTS2 Position */ +#define EPWM_INTSTS1_BRKLSTS2_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS2_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS2 Mask */ + +#define EPWM_INTSTS1_BRKLSTS3_Pos (27) /*!< EPWM_T::INTSTS1: BRKLSTS3 Position */ +#define EPWM_INTSTS1_BRKLSTS3_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS3_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS3 Mask */ + +#define EPWM_INTSTS1_BRKLSTS4_Pos (28) /*!< EPWM_T::INTSTS1: BRKLSTS4 Position */ +#define EPWM_INTSTS1_BRKLSTS4_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS4_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS4 Mask */ + +#define EPWM_INTSTS1_BRKLSTS5_Pos (29) /*!< EPWM_T::INTSTS1: BRKLSTS5 Position */ +#define EPWM_INTSTS1_BRKLSTS5_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS5_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS5 Mask */ + +#define EPWM_DACTRGEN_ZTE0_Pos (0) /*!< EPWM_T::DACTRGEN: ZTE0 Position */ +#define EPWM_DACTRGEN_ZTE0_Msk (0x1ul << EPWM_DACTRGEN_ZTE0_Pos) /*!< EPWM_T::DACTRGEN: ZTE0 Mask */ + +#define EPWM_DACTRGEN_ZTE1_Pos (1) /*!< EPWM_T::DACTRGEN: ZTE1 Position */ +#define EPWM_DACTRGEN_ZTE1_Msk (0x1ul << EPWM_DACTRGEN_ZTE1_Pos) /*!< EPWM_T::DACTRGEN: ZTE1 Mask */ + +#define EPWM_DACTRGEN_ZTE2_Pos (2) /*!< EPWM_T::DACTRGEN: ZTE2 Position */ +#define EPWM_DACTRGEN_ZTE2_Msk (0x1ul << EPWM_DACTRGEN_ZTE2_Pos) /*!< EPWM_T::DACTRGEN: ZTE2 Mask */ + +#define EPWM_DACTRGEN_ZTE3_Pos (3) /*!< EPWM_T::DACTRGEN: ZTE3 Position */ +#define EPWM_DACTRGEN_ZTE3_Msk (0x1ul << EPWM_DACTRGEN_ZTE3_Pos) /*!< EPWM_T::DACTRGEN: ZTE3 Mask */ + +#define EPWM_DACTRGEN_ZTE4_Pos (4) /*!< EPWM_T::DACTRGEN: ZTE4 Position */ +#define EPWM_DACTRGEN_ZTE4_Msk (0x1ul << EPWM_DACTRGEN_ZTE4_Pos) /*!< EPWM_T::DACTRGEN: ZTE4 Mask */ + +#define EPWM_DACTRGEN_ZTE5_Pos (5) /*!< EPWM_T::DACTRGEN: ZTE5 Position */ +#define EPWM_DACTRGEN_ZTE5_Msk (0x1ul << EPWM_DACTRGEN_ZTE5_Pos) /*!< EPWM_T::DACTRGEN: ZTE5 Mask */ + +#define EPWM_DACTRGEN_PTE0_Pos (8) /*!< EPWM_T::DACTRGEN: PTE0 Position */ +#define EPWM_DACTRGEN_PTE0_Msk (0x1ul << EPWM_DACTRGEN_PTE0_Pos) /*!< EPWM_T::DACTRGEN: PTE0 Mask */ + +#define EPWM_DACTRGEN_PTE1_Pos (9) /*!< EPWM_T::DACTRGEN: PTE1 Position */ +#define EPWM_DACTRGEN_PTE1_Msk (0x1ul << EPWM_DACTRGEN_PTE1_Pos) /*!< EPWM_T::DACTRGEN: PTE1 Mask */ + +#define EPWM_DACTRGEN_PTE2_Pos (10) /*!< EPWM_T::DACTRGEN: PTE2 Position */ +#define EPWM_DACTRGEN_PTE2_Msk (0x1ul << EPWM_DACTRGEN_PTE2_Pos) /*!< EPWM_T::DACTRGEN: PTE2 Mask */ + +#define EPWM_DACTRGEN_PTE3_Pos (11) /*!< EPWM_T::DACTRGEN: PTE3 Position */ +#define EPWM_DACTRGEN_PTE3_Msk (0x1ul << EPWM_DACTRGEN_PTE3_Pos) /*!< EPWM_T::DACTRGEN: PTE3 Mask */ + +#define EPWM_DACTRGEN_PTE4_Pos (12) /*!< EPWM_T::DACTRGEN: PTE4 Position */ +#define EPWM_DACTRGEN_PTE4_Msk (0x1ul << EPWM_DACTRGEN_PTE4_Pos) /*!< EPWM_T::DACTRGEN: PTE4 Mask */ + +#define EPWM_DACTRGEN_PTE5_Pos (13) /*!< EPWM_T::DACTRGEN: PTE5 Position */ +#define EPWM_DACTRGEN_PTE5_Msk (0x1ul << EPWM_DACTRGEN_PTE5_Pos) /*!< EPWM_T::DACTRGEN: PTE5 Mask */ + +#define EPWM_DACTRGEN_CUTRGE0_Pos (16) /*!< EPWM_T::DACTRGEN: CUTRGE0 Position */ +#define EPWM_DACTRGEN_CUTRGE0_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE0_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE0 Mask */ + +#define EPWM_DACTRGEN_CUTRGE1_Pos (17) /*!< EPWM_T::DACTRGEN: CUTRGE1 Position */ +#define EPWM_DACTRGEN_CUTRGE1_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE1_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE1 Mask */ + +#define EPWM_DACTRGEN_CUTRGE2_Pos (18) /*!< EPWM_T::DACTRGEN: CUTRGE2 Position */ +#define EPWM_DACTRGEN_CUTRGE2_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE2_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE2 Mask */ + +#define EPWM_DACTRGEN_CUTRGE3_Pos (19) /*!< EPWM_T::DACTRGEN: CUTRGE3 Position */ +#define EPWM_DACTRGEN_CUTRGE3_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE3_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE3 Mask */ + +#define EPWM_DACTRGEN_CUTRGE4_Pos (20) /*!< EPWM_T::DACTRGEN: CUTRGE4 Position */ +#define EPWM_DACTRGEN_CUTRGE4_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE4_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE4 Mask */ + +#define EPWM_DACTRGEN_CUTRGE5_Pos (21) /*!< EPWM_T::DACTRGEN: CUTRGE5 Position */ +#define EPWM_DACTRGEN_CUTRGE5_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE5_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE5 Mask */ + +#define EPWM_DACTRGEN_CDTRGE0_Pos (24) /*!< EPWM_T::DACTRGEN: CDTRGE0 Position */ +#define EPWM_DACTRGEN_CDTRGE0_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE0_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE0 Mask */ + +#define EPWM_DACTRGEN_CDTRGE1_Pos (25) /*!< EPWM_T::DACTRGEN: CDTRGE1 Position */ +#define EPWM_DACTRGEN_CDTRGE1_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE1_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE1 Mask */ + +#define EPWM_DACTRGEN_CDTRGE2_Pos (26) /*!< EPWM_T::DACTRGEN: CDTRGE2 Position */ +#define EPWM_DACTRGEN_CDTRGE2_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE2_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE2 Mask */ + +#define EPWM_DACTRGEN_CDTRGE3_Pos (27) /*!< EPWM_T::DACTRGEN: CDTRGE3 Position */ +#define EPWM_DACTRGEN_CDTRGE3_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE3_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE3 Mask */ + +#define EPWM_DACTRGEN_CDTRGE4_Pos (28) /*!< EPWM_T::DACTRGEN: CDTRGE4 Position */ +#define EPWM_DACTRGEN_CDTRGE4_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE4_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE4 Mask */ + +#define EPWM_DACTRGEN_CDTRGE5_Pos (29) /*!< EPWM_T::DACTRGEN: CDTRGE5 Position */ +#define EPWM_DACTRGEN_CDTRGE5_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE5_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE5 Mask */ + +#define EPWM_EADCTS0_TRGSEL0_Pos (0) /*!< EPWM_T::EADCTS0: TRGSEL0 Position */ +#define EPWM_EADCTS0_TRGSEL0_Msk (0xful << EPWM_EADCTS0_TRGSEL0_Pos) /*!< EPWM_T::EADCTS0: TRGSEL0 Mask */ + +#define EPWM_EADCTS0_TRGEN0_Pos (7) /*!< EPWM_T::EADCTS0: TRGEN0 Position */ +#define EPWM_EADCTS0_TRGEN0_Msk (0x1ul << EPWM_EADCTS0_TRGEN0_Pos) /*!< EPWM_T::EADCTS0: TRGEN0 Mask */ + +#define EPWM_EADCTS0_TRGSEL1_Pos (8) /*!< EPWM_T::EADCTS0: TRGSEL1 Position */ +#define EPWM_EADCTS0_TRGSEL1_Msk (0xful << EPWM_EADCTS0_TRGSEL1_Pos) /*!< EPWM_T::EADCTS0: TRGSEL1 Mask */ + +#define EPWM_EADCTS0_TRGEN1_Pos (15) /*!< EPWM_T::EADCTS0: TRGEN1 Position */ +#define EPWM_EADCTS0_TRGEN1_Msk (0x1ul << EPWM_EADCTS0_TRGEN1_Pos) /*!< EPWM_T::EADCTS0: TRGEN1 Mask */ + +#define EPWM_EADCTS0_TRGSEL2_Pos (16) /*!< EPWM_T::EADCTS0: TRGSEL2 Position */ +#define EPWM_EADCTS0_TRGSEL2_Msk (0xful << EPWM_EADCTS0_TRGSEL2_Pos) /*!< EPWM_T::EADCTS0: TRGSEL2 Mask */ + +#define EPWM_EADCTS0_TRGEN2_Pos (23) /*!< EPWM_T::EADCTS0: TRGEN2 Position */ +#define EPWM_EADCTS0_TRGEN2_Msk (0x1ul << EPWM_EADCTS0_TRGEN2_Pos) /*!< EPWM_T::EADCTS0: TRGEN2 Mask */ + +#define EPWM_EADCTS0_TRGSEL3_Pos (24) /*!< EPWM_T::EADCTS0: TRGSEL3 Position */ +#define EPWM_EADCTS0_TRGSEL3_Msk (0xful << EPWM_EADCTS0_TRGSEL3_Pos) /*!< EPWM_T::EADCTS0: TRGSEL3 Mask */ + +#define EPWM_EADCTS0_TRGEN3_Pos (31) /*!< EPWM_T::EADCTS0: TRGEN3 Position */ +#define EPWM_EADCTS0_TRGEN3_Msk (0x1ul << EPWM_EADCTS0_TRGEN3_Pos) /*!< EPWM_T::EADCTS0: TRGEN3 Mask */ + +#define EPWM_EADCTS1_TRGSEL4_Pos (0) /*!< EPWM_T::EADCTS1: TRGSEL4 Position */ +#define EPWM_EADCTS1_TRGSEL4_Msk (0xful << EPWM_EADCTS1_TRGSEL4_Pos) /*!< EPWM_T::EADCTS1: TRGSEL4 Mask */ + +#define EPWM_EADCTS1_TRGEN4_Pos (7) /*!< EPWM_T::EADCTS1: TRGEN4 Position */ +#define EPWM_EADCTS1_TRGEN4_Msk (0x1ul << EPWM_EADCTS1_TRGEN4_Pos) /*!< EPWM_T::EADCTS1: TRGEN4 Mask */ + +#define EPWM_EADCTS1_TRGSEL5_Pos (8) /*!< EPWM_T::EADCTS1: TRGSEL5 Position */ +#define EPWM_EADCTS1_TRGSEL5_Msk (0xful << EPWM_EADCTS1_TRGSEL5_Pos) /*!< EPWM_T::EADCTS1: TRGSEL5 Mask */ + +#define EPWM_EADCTS1_TRGEN5_Pos (15) /*!< EPWM_T::EADCTS1: TRGEN5 Position */ +#define EPWM_EADCTS1_TRGEN5_Msk (0x1ul << EPWM_EADCTS1_TRGEN5_Pos) /*!< EPWM_T::EADCTS1: TRGEN5 Mask */ + +#define EPWM_FTCMPDAT0_1_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT0_1: FTCMP Position */ +#define EPWM_FTCMPDAT0_1_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT0_1_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT0_1: FTCMP Mask */ + +#define EPWM_FTCMPDAT2_3_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT2_3: FTCMP Position */ +#define EPWM_FTCMPDAT2_3_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT2_3_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT2_3: FTCMP Mask */ + +#define EPWM_FTCMPDAT4_5_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT4_5: FTCMP Position */ +#define EPWM_FTCMPDAT4_5_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT4_5_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT4_5: FTCMP Mask */ + +#define EPWM_SSCTL_SSEN0_Pos (0) /*!< EPWM_T::SSCTL: SSEN0 Position */ +#define EPWM_SSCTL_SSEN0_Msk (0x1ul << EPWM_SSCTL_SSEN0_Pos) /*!< EPWM_T::SSCTL: SSEN0 Mask */ + +#define EPWM_SSCTL_SSEN1_Pos (1) /*!< EPWM_T::SSCTL: SSEN1 Position */ +#define EPWM_SSCTL_SSEN1_Msk (0x1ul << EPWM_SSCTL_SSEN1_Pos) /*!< EPWM_T::SSCTL: SSEN1 Mask */ + +#define EPWM_SSCTL_SSEN2_Pos (2) /*!< EPWM_T::SSCTL: SSEN2 Position */ +#define EPWM_SSCTL_SSEN2_Msk (0x1ul << EPWM_SSCTL_SSEN2_Pos) /*!< EPWM_T::SSCTL: SSEN2 Mask */ + +#define EPWM_SSCTL_SSEN3_Pos (3) /*!< EPWM_T::SSCTL: SSEN3 Position */ +#define EPWM_SSCTL_SSEN3_Msk (0x1ul << EPWM_SSCTL_SSEN3_Pos) /*!< EPWM_T::SSCTL: SSEN3 Mask */ + +#define EPWM_SSCTL_SSEN4_Pos (4) /*!< EPWM_T::SSCTL: SSEN4 Position */ +#define EPWM_SSCTL_SSEN4_Msk (0x1ul << EPWM_SSCTL_SSEN4_Pos) /*!< EPWM_T::SSCTL: SSEN4 Mask */ + +#define EPWM_SSCTL_SSEN5_Pos (5) /*!< EPWM_T::SSCTL: SSEN5 Position */ +#define EPWM_SSCTL_SSEN5_Msk (0x1ul << EPWM_SSCTL_SSEN5_Pos) /*!< EPWM_T::SSCTL: SSEN5 Mask */ + +#define EPWM_SSCTL_SSRC_Pos (8) /*!< EPWM_T::SSCTL: SSRC Position */ +#define EPWM_SSCTL_SSRC_Msk (0x3ul << EPWM_SSCTL_SSRC_Pos) /*!< EPWM_T::SSCTL: SSRC Mask */ + +#define EPWM_SSTRG_CNTSEN_Pos (0) /*!< EPWM_T::SSTRG: CNTSEN Position */ +#define EPWM_SSTRG_CNTSEN_Msk (0x1ul << EPWM_SSTRG_CNTSEN_Pos) /*!< EPWM_T::SSTRG: CNTSEN Mask */ + +#define EPWM_LEBCTL_LEBEN_Pos (0) /*!< EPWM_T::LEBCTL: LEBEN Position */ +#define EPWM_LEBCTL_LEBEN_Msk (0x1ul << EPWM_LEBCTL_LEBEN_Pos) /*!< EPWM_T::LEBCTL: LEBEN Mask */ + +#define EPWM_LEBCTL_SRCEN0_Pos (8) /*!< EPWM_T::LEBCTL: SRCEN0 Position */ +#define EPWM_LEBCTL_SRCEN0_Msk (0x1ul << EPWM_LEBCTL_SRCEN0_Pos) /*!< EPWM_T::LEBCTL: SRCEN0 Mask */ + +#define EPWM_LEBCTL_SRCEN2_Pos (9) /*!< EPWM_T::LEBCTL: SRCEN2 Position */ +#define EPWM_LEBCTL_SRCEN2_Msk (0x1ul << EPWM_LEBCTL_SRCEN2_Pos) /*!< EPWM_T::LEBCTL: SRCEN2 Mask */ + +#define EPWM_LEBCTL_SRCEN4_Pos (10) /*!< EPWM_T::LEBCTL: SRCEN4 Position */ +#define EPWM_LEBCTL_SRCEN4_Msk (0x1ul << EPWM_LEBCTL_SRCEN4_Pos) /*!< EPWM_T::LEBCTL: SRCEN4 Mask */ + +#define EPWM_LEBCTL_TRGTYPE_Pos (16) /*!< EPWM_T::LEBCTL: TRGTYPE Position */ +#define EPWM_LEBCTL_TRGTYPE_Msk (0x3ul << EPWM_LEBCTL_TRGTYPE_Pos) /*!< EPWM_T::LEBCTL: TRGTYPE Mask */ + +#define EPWM_LEBCNT_LEBCNT_Pos (0) /*!< EPWM_T::LEBCNT: LEBCNT Position */ +#define EPWM_LEBCNT_LEBCNT_Msk (0x1fful << EPWM_LEBCNT_LEBCNT_Pos) /*!< EPWM_T::LEBCNT: LEBCNT Mask */ + +#define EPWM_STATUS_CNTMAXF0_Pos (0) /*!< EPWM_T::STATUS: CNTMAXF0 Position */ +#define EPWM_STATUS_CNTMAXF0_Msk (0x1ul << EPWM_STATUS_CNTMAXF0_Pos) /*!< EPWM_T::STATUS: CNTMAXF0 Mask */ + +#define EPWM_STATUS_CNTMAXF1_Pos (1) /*!< EPWM_T::STATUS: CNTMAXF1 Position */ +#define EPWM_STATUS_CNTMAXF1_Msk (0x1ul << EPWM_STATUS_CNTMAXF1_Pos) /*!< EPWM_T::STATUS: CNTMAXF1 Mask */ + +#define EPWM_STATUS_CNTMAXF2_Pos (2) /*!< EPWM_T::STATUS: CNTMAXF2 Position */ +#define EPWM_STATUS_CNTMAXF2_Msk (0x1ul << EPWM_STATUS_CNTMAXF2_Pos) /*!< EPWM_T::STATUS: CNTMAXF2 Mask */ + +#define EPWM_STATUS_CNTMAXF3_Pos (3) /*!< EPWM_T::STATUS: CNTMAXF3 Position */ +#define EPWM_STATUS_CNTMAXF3_Msk (0x1ul << EPWM_STATUS_CNTMAXF3_Pos) /*!< EPWM_T::STATUS: CNTMAXF3 Mask */ + +#define EPWM_STATUS_CNTMAXF4_Pos (4) /*!< EPWM_T::STATUS: CNTMAXF4 Position */ +#define EPWM_STATUS_CNTMAXF4_Msk (0x1ul << EPWM_STATUS_CNTMAXF4_Pos) /*!< EPWM_T::STATUS: CNTMAXF4 Mask */ + +#define EPWM_STATUS_CNTMAXF5_Pos (5) /*!< EPWM_T::STATUS: CNTMAXF5 Position */ +#define EPWM_STATUS_CNTMAXF5_Msk (0x1ul << EPWM_STATUS_CNTMAXF5_Pos) /*!< EPWM_T::STATUS: CNTMAXF5 Mask */ + +#define EPWM_STATUS_SYNCINF0_Pos (8) /*!< EPWM_T::STATUS: SYNCINF0 Position */ +#define EPWM_STATUS_SYNCINF0_Msk (0x1ul << EPWM_STATUS_SYNCINF0_Pos) /*!< EPWM_T::STATUS: SYNCINF0 Mask */ + +#define EPWM_STATUS_SYNCINF2_Pos (9) /*!< EPWM_T::STATUS: SYNCINF2 Position */ +#define EPWM_STATUS_SYNCINF2_Msk (0x1ul << EPWM_STATUS_SYNCINF2_Pos) /*!< EPWM_T::STATUS: SYNCINF2 Mask */ + +#define EPWM_STATUS_SYNCINF4_Pos (10) /*!< EPWM_T::STATUS: SYNCINF4 Position */ +#define EPWM_STATUS_SYNCINF4_Msk (0x1ul << EPWM_STATUS_SYNCINF4_Pos) /*!< EPWM_T::STATUS: SYNCINF4 Mask */ + +#define EPWM_STATUS_EADCTRGF0_Pos (16) /*!< EPWM_T::STATUS: EADCTRGF0 Position */ +#define EPWM_STATUS_EADCTRGF0_Msk (0x1ul << EPWM_STATUS_EADCTRGF0_Pos) /*!< EPWM_T::STATUS: EADCTRGF0 Mask */ + +#define EPWM_STATUS_EADCTRGF1_Pos (17) /*!< EPWM_T::STATUS: EADCTRGF1 Position */ +#define EPWM_STATUS_EADCTRGF1_Msk (0x1ul << EPWM_STATUS_EADCTRGF1_Pos) /*!< EPWM_T::STATUS: EADCTRGF1 Mask */ + +#define EPWM_STATUS_EADCTRGF2_Pos (18) /*!< EPWM_T::STATUS: EADCTRGF2 Position */ +#define EPWM_STATUS_EADCTRGF2_Msk (0x1ul << EPWM_STATUS_EADCTRGF2_Pos) /*!< EPWM_T::STATUS: EADCTRGF2 Mask */ + +#define EPWM_STATUS_EADCTRGF3_Pos (19) /*!< EPWM_T::STATUS: EADCTRGF3 Position */ +#define EPWM_STATUS_EADCTRGF3_Msk (0x1ul << EPWM_STATUS_EADCTRGF3_Pos) /*!< EPWM_T::STATUS: EADCTRGF3 Mask */ + +#define EPWM_STATUS_EADCTRGF4_Pos (20) /*!< EPWM_T::STATUS: EADCTRGF4 Position */ +#define EPWM_STATUS_EADCTRGF4_Msk (0x1ul << EPWM_STATUS_EADCTRGF4_Pos) /*!< EPWM_T::STATUS: EADCTRGF4 Mask */ + +#define EPWM_STATUS_EADCTRGF5_Pos (21) /*!< EPWM_T::STATUS: EADCTRGF5 Position */ +#define EPWM_STATUS_EADCTRGF5_Msk (0x1ul << EPWM_STATUS_EADCTRGF5_Pos) /*!< EPWM_T::STATUS: EADCTRGF5 Mask */ + +#define EPWM_STATUS_DACTRGF_Pos (24) /*!< EPWM_T::STATUS: DACTRGF Position */ +#define EPWM_STATUS_DACTRGF_Msk (0x1ul << EPWM_STATUS_DACTRGF_Pos) /*!< EPWM_T::STATUS: DACTRGF Mask */ + +#define EPWM_IFA0_IFACNT_Pos (0) /*!< EPWM_T::IFA0: IFACNT Position */ +#define EPWM_IFA0_IFACNT_Msk (0xfffful << EPWM_IFA0_IFACNT_Pos) /*!< EPWM_T::IFA0: IFACNT Mask */ + +#define EPWM_IFA0_STPMOD_Pos (24) /*!< EPWM_T::IFA0: STPMOD Position */ +#define EPWM_IFA0_STPMOD_Msk (0x1ul << EPWM_IFA0_STPMOD_Pos) /*!< EPWM_T::IFA0: STPMOD Mask */ + +#define EPWM_IFA0_IFASEL_Pos (28) /*!< EPWM_T::IFA0: IFASEL Position */ +#define EPWM_IFA0_IFASEL_Msk (0x3ul << EPWM_IFA0_IFASEL_Pos) /*!< EPWM_T::IFA0: IFASEL Mask */ + +#define EPWM_IFA0_IFAEN_Pos (31) /*!< EPWM_T::IFA0: IFAEN Position */ +#define EPWM_IFA0_IFAEN_Msk (0x1ul << EPWM_IFA0_IFAEN_Pos) /*!< EPWM_T::IFA0: IFAEN Mask */ + +#define EPWM_IFA1_IFACNT_Pos (0) /*!< EPWM_T::IFA1: IFACNT Position */ +#define EPWM_IFA1_IFACNT_Msk (0xfffful << EPWM_IFA1_IFACNT_Pos) /*!< EPWM_T::IFA1: IFACNT Mask */ + +#define EPWM_IFA1_STPMOD_Pos (24) /*!< EPWM_T::IFA1: STPMOD Position */ +#define EPWM_IFA1_STPMOD_Msk (0x1ul << EPWM_IFA1_STPMOD_Pos) /*!< EPWM_T::IFA1: STPMOD Mask */ + +#define EPWM_IFA1_IFASEL_Pos (28) /*!< EPWM_T::IFA1: IFASEL Position */ +#define EPWM_IFA1_IFASEL_Msk (0x3ul << EPWM_IFA1_IFASEL_Pos) /*!< EPWM_T::IFA1: IFASEL Mask */ + +#define EPWM_IFA1_IFAEN_Pos (31) /*!< EPWM_T::IFA1: IFAEN Position */ +#define EPWM_IFA1_IFAEN_Msk (0x1ul << EPWM_IFA1_IFAEN_Pos) /*!< EPWM_T::IFA1: IFAEN Mask */ + +#define EPWM_IFA2_IFACNT_Pos (0) /*!< EPWM_T::IFA2: IFACNT Position */ +#define EPWM_IFA2_IFACNT_Msk (0xfffful << EPWM_IFA2_IFACNT_Pos) /*!< EPWM_T::IFA2: IFACNT Mask */ + +#define EPWM_IFA2_STPMOD_Pos (24) /*!< EPWM_T::IFA2: STPMOD Position */ +#define EPWM_IFA2_STPMOD_Msk (0x1ul << EPWM_IFA2_STPMOD_Pos) /*!< EPWM_T::IFA2: STPMOD Mask */ + +#define EPWM_IFA2_IFASEL_Pos (28) /*!< EPWM_T::IFA2: IFASEL Position */ +#define EPWM_IFA2_IFASEL_Msk (0x3ul << EPWM_IFA2_IFASEL_Pos) /*!< EPWM_T::IFA2: IFASEL Mask */ + +#define EPWM_IFA2_IFAEN_Pos (31) /*!< EPWM_T::IFA2: IFAEN Position */ +#define EPWM_IFA2_IFAEN_Msk (0x1ul << EPWM_IFA2_IFAEN_Pos) /*!< EPWM_T::IFA2: IFAEN Mask */ + +#define EPWM_IFA3_IFACNT_Pos (0) /*!< EPWM_T::IFA3: IFACNT Position */ +#define EPWM_IFA3_IFACNT_Msk (0xfffful << EPWM_IFA3_IFACNT_Pos) /*!< EPWM_T::IFA3: IFACNT Mask */ + +#define EPWM_IFA3_STPMOD_Pos (24) /*!< EPWM_T::IFA3: STPMOD Position */ +#define EPWM_IFA3_STPMOD_Msk (0x1ul << EPWM_IFA3_STPMOD_Pos) /*!< EPWM_T::IFA3: STPMOD Mask */ + +#define EPWM_IFA3_IFASEL_Pos (28) /*!< EPWM_T::IFA3: IFASEL Position */ +#define EPWM_IFA3_IFASEL_Msk (0x3ul << EPWM_IFA3_IFASEL_Pos) /*!< EPWM_T::IFA3: IFASEL Mask */ + +#define EPWM_IFA3_IFAEN_Pos (31) /*!< EPWM_T::IFA3: IFAEN Position */ +#define EPWM_IFA3_IFAEN_Msk (0x1ul << EPWM_IFA3_IFAEN_Pos) /*!< EPWM_T::IFA3: IFAEN Mask */ + +#define EPWM_IFA4_IFACNT_Pos (0) /*!< EPWM_T::IFA4: IFACNT Position */ +#define EPWM_IFA4_IFACNT_Msk (0xfffful << EPWM_IFA4_IFACNT_Pos) /*!< EPWM_T::IFA4: IFACNT Mask */ + +#define EPWM_IFA4_STPMOD_Pos (24) /*!< EPWM_T::IFA4: STPMOD Position */ +#define EPWM_IFA4_STPMOD_Msk (0x1ul << EPWM_IFA4_STPMOD_Pos) /*!< EPWM_T::IFA4: STPMOD Mask */ + +#define EPWM_IFA4_IFASEL_Pos (28) /*!< EPWM_T::IFA4: IFASEL Position */ +#define EPWM_IFA4_IFASEL_Msk (0x3ul << EPWM_IFA4_IFASEL_Pos) /*!< EPWM_T::IFA4: IFASEL Mask */ + +#define EPWM_IFA4_IFAEN_Pos (31) /*!< EPWM_T::IFA4: IFAEN Position */ +#define EPWM_IFA4_IFAEN_Msk (0x1ul << EPWM_IFA4_IFAEN_Pos) /*!< EPWM_T::IFA4: IFAEN Mask */ + +#define EPWM_IFA5_IFACNT_Pos (0) /*!< EPWM_T::IFA5: IFACNT Position */ +#define EPWM_IFA5_IFACNT_Msk (0xfffful << EPWM_IFA5_IFACNT_Pos) /*!< EPWM_T::IFA5: IFACNT Mask */ + +#define EPWM_IFA5_STPMOD_Pos (24) /*!< EPWM_T::IFA5: STPMOD Position */ +#define EPWM_IFA5_STPMOD_Msk (0x1ul << EPWM_IFA5_STPMOD_Pos) /*!< EPWM_T::IFA5: STPMOD Mask */ + +#define EPWM_IFA5_IFASEL_Pos (28) /*!< EPWM_T::IFA5: IFASEL Position */ +#define EPWM_IFA5_IFASEL_Msk (0x3ul << EPWM_IFA5_IFASEL_Pos) /*!< EPWM_T::IFA5: IFASEL Mask */ + +#define EPWM_IFA5_IFAEN_Pos (31) /*!< EPWM_T::IFA5: IFAEN Position */ +#define EPWM_IFA5_IFAEN_Msk (0x1ul << EPWM_IFA5_IFAEN_Pos) /*!< EPWM_T::IFA5: IFAEN Mask */ + +#define EPWM_AINTSTS_IFAIF0_Pos (0) /*!< EPWM_T::AINTSTS: IFAIF0 Position */ +#define EPWM_AINTSTS_IFAIF0_Msk (0x1ul << EPWM_AINTSTS_IFAIF0_Pos) /*!< EPWM_T::AINTSTS: IFAIF0 Mask */ + +#define EPWM_AINTSTS_IFAIF1_Pos (1) /*!< EPWM_T::AINTSTS: IFAIF1 Position */ +#define EPWM_AINTSTS_IFAIF1_Msk (0x1ul << EPWM_AINTSTS_IFAIF1_Pos) /*!< EPWM_T::AINTSTS: IFAIF1 Mask */ + +#define EPWM_AINTSTS_IFAIF2_Pos (2) /*!< EPWM_T::AINTSTS: IFAIF2 Position */ +#define EPWM_AINTSTS_IFAIF2_Msk (0x1ul << EPWM_AINTSTS_IFAIF2_Pos) /*!< EPWM_T::AINTSTS: IFAIF2 Mask */ + +#define EPWM_AINTSTS_IFAIF3_Pos (3) /*!< EPWM_T::AINTSTS: IFAIF3 Position */ +#define EPWM_AINTSTS_IFAIF3_Msk (0x1ul << EPWM_AINTSTS_IFAIF3_Pos) /*!< EPWM_T::AINTSTS: IFAIF3 Mask */ + +#define EPWM_AINTSTS_IFAIF4_Pos (4) /*!< EPWM_T::AINTSTS: IFAIF4 Position */ +#define EPWM_AINTSTS_IFAIF4_Msk (0x1ul << EPWM_AINTSTS_IFAIF4_Pos) /*!< EPWM_T::AINTSTS: IFAIF4 Mask */ + +#define EPWM_AINTSTS_IFAIF5_Pos (5) /*!< EPWM_T::AINTSTS: IFAIF5 Position */ +#define EPWM_AINTSTS_IFAIF5_Msk (0x1ul << EPWM_AINTSTS_IFAIF5_Pos) /*!< EPWM_T::AINTSTS: IFAIF5 Mask */ + +#define EPWM_AINTEN_IFAIEN0_Pos (0) /*!< EPWM_T::AINTEN: IFAIEN0 Position */ +#define EPWM_AINTEN_IFAIEN0_Msk (0x1ul << EPWM_AINTEN_IFAIEN0_Pos) /*!< EPWM_T::AINTEN: IFAIEN0 Mask */ + +#define EPWM_AINTEN_IFAIEN1_Pos (1) /*!< EPWM_T::AINTEN: IFAIEN1 Position */ +#define EPWM_AINTEN_IFAIEN1_Msk (0x1ul << EPWM_AINTEN_IFAIEN1_Pos) /*!< EPWM_T::AINTEN: IFAIEN1 Mask */ + +#define EPWM_AINTEN_IFAIEN2_Pos (2) /*!< EPWM_T::AINTEN: IFAIEN2 Position */ +#define EPWM_AINTEN_IFAIEN2_Msk (0x1ul << EPWM_AINTEN_IFAIEN2_Pos) /*!< EPWM_T::AINTEN: IFAIEN2 Mask */ + +#define EPWM_AINTEN_IFAIEN3_Pos (3) /*!< EPWM_T::AINTEN: IFAIEN3 Position */ +#define EPWM_AINTEN_IFAIEN3_Msk (0x1ul << EPWM_AINTEN_IFAIEN3_Pos) /*!< EPWM_T::AINTEN: IFAIEN3 Mask */ + +#define EPWM_AINTEN_IFAIEN4_Pos (4) /*!< EPWM_T::AINTEN: IFAIEN4 Position */ +#define EPWM_AINTEN_IFAIEN4_Msk (0x1ul << EPWM_AINTEN_IFAIEN4_Pos) /*!< EPWM_T::AINTEN: IFAIEN4 Mask */ + +#define EPWM_AINTEN_IFAIEN5_Pos (5) /*!< EPWM_T::AINTEN: IFAIEN5 Position */ +#define EPWM_AINTEN_IFAIEN5_Msk (0x1ul << EPWM_AINTEN_IFAIEN5_Pos) /*!< EPWM_T::AINTEN: IFAIEN5 Mask */ + +#define EPWM_APDMACTL_APDMAEN0_Pos (0) /*!< EPWM_T::APDMACTL: APDMAEN0 Position */ +#define EPWM_APDMACTL_APDMAEN0_Msk (0x1ul << EPWM_APDMACTL_APDMAEN0_Pos) /*!< EPWM_T::APDMACTL: APDMAEN0 Mask */ + +#define EPWM_APDMACTL_APDMAEN1_Pos (1) /*!< EPWM_T::APDMACTL: APDMAEN1 Position */ +#define EPWM_APDMACTL_APDMAEN1_Msk (0x1ul << EPWM_APDMACTL_APDMAEN1_Pos) /*!< EPWM_T::APDMACTL: APDMAEN1 Mask */ + +#define EPWM_APDMACTL_APDMAEN2_Pos (2) /*!< EPWM_T::APDMACTL: APDMAEN2 Position */ +#define EPWM_APDMACTL_APDMAEN2_Msk (0x1ul << EPWM_APDMACTL_APDMAEN2_Pos) /*!< EPWM_T::APDMACTL: APDMAEN2 Mask */ + +#define EPWM_APDMACTL_APDMAEN3_Pos (3) /*!< EPWM_T::APDMACTL: APDMAEN3 Position */ +#define EPWM_APDMACTL_APDMAEN3_Msk (0x1ul << EPWM_APDMACTL_APDMAEN3_Pos) /*!< EPWM_T::APDMACTL: APDMAEN3 Mask */ + +#define EPWM_APDMACTL_APDMAEN4_Pos (4) /*!< EPWM_T::APDMACTL: APDMAEN4 Position */ +#define EPWM_APDMACTL_APDMAEN4_Msk (0x1ul << EPWM_APDMACTL_APDMAEN4_Pos) /*!< EPWM_T::APDMACTL: APDMAEN4 Mask */ + +#define EPWM_APDMACTL_APDMAEN5_Pos (5) /*!< EPWM_T::APDMACTL: APDMAEN5 Position */ +#define EPWM_APDMACTL_APDMAEN5_Msk (0x1ul << EPWM_APDMACTL_APDMAEN5_Pos) /*!< EPWM_T::APDMACTL: APDMAEN5 Mask */ + +#define EPWM_FDEN_FDEN0_Pos (0) /*!< EPWM_T::FDEN: FDEN0 Position */ +#define EPWM_FDEN_FDEN0_Msk (0x1ul << EPWM_FDEN_FDEN0_Pos) /*!< EPWM_T::FDEN: FDEN0 Mask */ + +#define EPWM_FDEN_FDEN1_Pos (1) /*!< EPWM_T::FDEN: FDEN1 Position */ +#define EPWM_FDEN_FDEN1_Msk (0x1ul << EPWM_FDEN_FDEN1_Pos) /*!< EPWM_T::FDEN: FDEN1 Mask */ + +#define EPWM_FDEN_FDEN2_Pos (2) /*!< EPWM_T::FDEN: FDEN2 Position */ +#define EPWM_FDEN_FDEN2_Msk (0x1ul << EPWM_FDEN_FDEN2_Pos) /*!< EPWM_T::FDEN: FDEN2 Mask */ + +#define EPWM_FDEN_FDEN3_Pos (3) /*!< EPWM_T::FDEN: FDEN3 Position */ +#define EPWM_FDEN_FDEN3_Msk (0x1ul << EPWM_FDEN_FDEN3_Pos) /*!< EPWM_T::FDEN: FDEN3 Mask */ + +#define EPWM_FDEN_FDEN4_Pos (4) /*!< EPWM_T::FDEN: FDEN4 Position */ +#define EPWM_FDEN_FDEN4_Msk (0x1ul << EPWM_FDEN_FDEN4_Pos) /*!< EPWM_T::FDEN: FDEN4 Mask */ + +#define EPWM_FDEN_FDEN5_Pos (5) /*!< EPWM_T::FDEN: FDEN5 Position */ +#define EPWM_FDEN_FDEN5_Msk (0x1ul << EPWM_FDEN_FDEN5_Pos) /*!< EPWM_T::FDEN: FDEN5 Mask */ + +#define EPWM_FDEN_FDODIS0_Pos (8) /*!< EPWM_T::FDEN: FDODIS0 Position */ +#define EPWM_FDEN_FDODIS0_Msk (0x1ul << EPWM_FDEN_FDODIS0_Pos) /*!< EPWM_T::FDEN: FDODIS0 Mask */ + +#define EPWM_FDEN_FDODIS1_Pos (9) /*!< EPWM_T::FDEN: FDODIS1 Position */ +#define EPWM_FDEN_FDODIS1_Msk (0x1ul << EPWM_FDEN_FDODIS1_Pos) /*!< EPWM_T::FDEN: FDODIS1 Mask */ + +#define EPWM_FDEN_FDODIS2_Pos (10) /*!< EPWM_T::FDEN: FDODIS2 Position */ +#define EPWM_FDEN_FDODIS2_Msk (0x1ul << EPWM_FDEN_FDODIS2_Pos) /*!< EPWM_T::FDEN: FDODIS2 Mask */ + +#define EPWM_FDEN_FDODIS3_Pos (11) /*!< EPWM_T::FDEN: FDODIS3 Position */ +#define EPWM_FDEN_FDODIS3_Msk (0x1ul << EPWM_FDEN_FDODIS3_Pos) /*!< EPWM_T::FDEN: FDODIS3 Mask */ + +#define EPWM_FDEN_FDODIS4_Pos (12) /*!< EPWM_T::FDEN: FDODIS4 Position */ +#define EPWM_FDEN_FDODIS4_Msk (0x1ul << EPWM_FDEN_FDODIS4_Pos) /*!< EPWM_T::FDEN: FDODIS4 Mask */ + +#define EPWM_FDEN_FDODIS5_Pos (13) /*!< EPWM_T::FDEN: FDODIS5 Position */ +#define EPWM_FDEN_FDODIS5_Msk (0x1ul << EPWM_FDEN_FDODIS5_Pos) /*!< EPWM_T::FDEN: FDODIS5 Mask */ + +#define EPWM_FDEN_FDCKS0_Pos (16) /*!< EPWM_T::FDEN: FDCKS0 Position */ +#define EPWM_FDEN_FDCKS0_Msk (0x1ul << EPWM_FDEN_FDCKS0_Pos) /*!< EPWM_T::FDEN: FDCKS0 Mask */ + +#define EPWM_FDEN_FDCKS1_Pos (17) /*!< EPWM_T::FDEN: FDCKS1 Position */ +#define EPWM_FDEN_FDCKS1_Msk (0x1ul << EPWM_FDEN_FDCKS1_Pos) /*!< EPWM_T::FDEN: FDCKS1 Mask */ + +#define EPWM_FDEN_FDCKS2_Pos (18) /*!< EPWM_T::FDEN: FDCKS2 Position */ +#define EPWM_FDEN_FDCKS2_Msk (0x1ul << EPWM_FDEN_FDCKS2_Pos) /*!< EPWM_T::FDEN: FDCKS2 Mask */ + +#define EPWM_FDEN_FDCKS3_Pos (19) /*!< EPWM_T::FDEN: FDCKS3 Position */ +#define EPWM_FDEN_FDCKS3_Msk (0x1ul << EPWM_FDEN_FDCKS3_Pos) /*!< EPWM_T::FDEN: FDCKS3 Mask */ + +#define EPWM_FDEN_FDCKS4_Pos (20) /*!< EPWM_T::FDEN: FDCKS4 Position */ +#define EPWM_FDEN_FDCKS4_Msk (0x1ul << EPWM_FDEN_FDCKS4_Pos) /*!< EPWM_T::FDEN: FDCKS4 Mask */ + +#define EPWM_FDEN_FDCKS5_Pos (21) /*!< EPWM_T::FDEN: FDCKS5 Position */ +#define EPWM_FDEN_FDCKS5_Msk (0x1ul << EPWM_FDEN_FDCKS5_Pos) /*!< EPWM_T::FDEN: FDCKS5 Mask */ + +#define EPWM_FDCTL0_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL0: TRMSKCNT Position */ +#define EPWM_FDCTL0_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL0_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL0: TRMSKCNT Mask */ + +#define EPWM_FDCTL0_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL0: FDMSKEN Position */ +#define EPWM_FDCTL0_FDMSKEN_Msk (0x1ul << EPWM_FDCTL0_FDMSKEN_Pos) /*!< EPWM_T::FDCTL0: FDMSKEN Mask */ + +#define EPWM_FDCTL0_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL0: DGSMPCYC Position */ +#define EPWM_FDCTL0_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL0_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL0: DGSMPCYC Mask */ + +#define EPWM_FDCTL0_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL0: FDCKSEL Position */ +#define EPWM_FDCTL0_FDCKSEL_Msk (0x3ul << EPWM_FDCTL0_FDCKSEL_Pos) /*!< EPWM_T::FDCTL0: FDCKSEL Mask */ + +#define EPWM_FDCTL0_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL0: FDDGEN Position */ +#define EPWM_FDCTL0_FDDGEN_Msk (0x1ul << EPWM_FDCTL0_FDDGEN_Pos) /*!< EPWM_T::FDCTL0: FDDGEN Mask */ + +#define EPWM_FDCTL1_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL1: TRMSKCNT Position */ +#define EPWM_FDCTL1_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL1_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL1: TRMSKCNT Mask */ + +#define EPWM_FDCTL1_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL1: FDMSKEN Position */ +#define EPWM_FDCTL1_FDMSKEN_Msk (0x1ul << EPWM_FDCTL1_FDMSKEN_Pos) /*!< EPWM_T::FDCTL1: FDMSKEN Mask */ + +#define EPWM_FDCTL1_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL1: DGSMPCYC Position */ +#define EPWM_FDCTL1_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL1_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL1: DGSMPCYC Mask */ + +#define EPWM_FDCTL1_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL1: FDCKSEL Position */ +#define EPWM_FDCTL1_FDCKSEL_Msk (0x3ul << EPWM_FDCTL1_FDCKSEL_Pos) /*!< EPWM_T::FDCTL1: FDCKSEL Mask */ + +#define EPWM_FDCTL1_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL1: FDDGEN Position */ +#define EPWM_FDCTL1_FDDGEN_Msk (0x1ul << EPWM_FDCTL1_FDDGEN_Pos) /*!< EPWM_T::FDCTL1: FDDGEN Mask */ + +#define EPWM_FDCTL2_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL2: TRMSKCNT Position */ +#define EPWM_FDCTL2_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL2_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL2: TRMSKCNT Mask */ + +#define EPWM_FDCTL2_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL2: FDMSKEN Position */ +#define EPWM_FDCTL2_FDMSKEN_Msk (0x1ul << EPWM_FDCTL2_FDMSKEN_Pos) /*!< EPWM_T::FDCTL2: FDMSKEN Mask */ + +#define EPWM_FDCTL2_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL2: DGSMPCYC Position */ +#define EPWM_FDCTL2_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL2_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL2: DGSMPCYC Mask */ + +#define EPWM_FDCTL2_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL2: FDCKSEL Position */ +#define EPWM_FDCTL2_FDCKSEL_Msk (0x3ul << EPWM_FDCTL2_FDCKSEL_Pos) /*!< EPWM_T::FDCTL2: FDCKSEL Mask */ + +#define EPWM_FDCTL2_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL2: FDDGEN Position */ +#define EPWM_FDCTL2_FDDGEN_Msk (0x1ul << EPWM_FDCTL2_FDDGEN_Pos) /*!< EPWM_T::FDCTL2: FDDGEN Mask */ + +#define EPWM_FDCTL3_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL3: TRMSKCNT Position */ +#define EPWM_FDCTL3_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL3_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL3: TRMSKCNT Mask */ + +#define EPWM_FDCTL3_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL3: FDMSKEN Position */ +#define EPWM_FDCTL3_FDMSKEN_Msk (0x1ul << EPWM_FDCTL3_FDMSKEN_Pos) /*!< EPWM_T::FDCTL3: FDMSKEN Mask */ + +#define EPWM_FDCTL3_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL3: DGSMPCYC Position */ +#define EPWM_FDCTL3_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL3_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL3: DGSMPCYC Mask */ + +#define EPWM_FDCTL3_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL3: FDCKSEL Position */ +#define EPWM_FDCTL3_FDCKSEL_Msk (0x3ul << EPWM_FDCTL3_FDCKSEL_Pos) /*!< EPWM_T::FDCTL3: FDCKSEL Mask */ + +#define EPWM_FDCTL3_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL3: FDDGEN Position */ +#define EPWM_FDCTL3_FDDGEN_Msk (0x1ul << EPWM_FDCTL3_FDDGEN_Pos) /*!< EPWM_T::FDCTL3: FDDGEN Mask */ + +#define EPWM_FDCTL4_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL4: TRMSKCNT Position */ +#define EPWM_FDCTL4_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL4_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL4: TRMSKCNT Mask */ + +#define EPWM_FDCTL4_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL4: FDMSKEN Position */ +#define EPWM_FDCTL4_FDMSKEN_Msk (0x1ul << EPWM_FDCTL4_FDMSKEN_Pos) /*!< EPWM_T::FDCTL4: FDMSKEN Mask */ + +#define EPWM_FDCTL4_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL4: DGSMPCYC Position */ +#define EPWM_FDCTL4_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL4_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL4: DGSMPCYC Mask */ + +#define EPWM_FDCTL4_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL4: FDCKSEL Position */ +#define EPWM_FDCTL4_FDCKSEL_Msk (0x3ul << EPWM_FDCTL4_FDCKSEL_Pos) /*!< EPWM_T::FDCTL4: FDCKSEL Mask */ + +#define EPWM_FDCTL4_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL4: FDDGEN Position */ +#define EPWM_FDCTL4_FDDGEN_Msk (0x1ul << EPWM_FDCTL4_FDDGEN_Pos) /*!< EPWM_T::FDCTL4: FDDGEN Mask */ + +#define EPWM_FDCTL5_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL5: TRMSKCNT Position */ +#define EPWM_FDCTL5_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL5_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL5: TRMSKCNT Mask */ + +#define EPWM_FDCTL5_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL5: FDMSKEN Position */ +#define EPWM_FDCTL5_FDMSKEN_Msk (0x1ul << EPWM_FDCTL5_FDMSKEN_Pos) /*!< EPWM_T::FDCTL5: FDMSKEN Mask */ + +#define EPWM_FDCTL5_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL5: DGSMPCYC Position */ +#define EPWM_FDCTL5_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL5_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL5: DGSMPCYC Mask */ + +#define EPWM_FDCTL5_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL5: FDCKSEL Position */ +#define EPWM_FDCTL5_FDCKSEL_Msk (0x3ul << EPWM_FDCTL5_FDCKSEL_Pos) /*!< EPWM_T::FDCTL5: FDCKSEL Mask */ + +#define EPWM_FDCTL5_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL5: FDDGEN Position */ +#define EPWM_FDCTL5_FDDGEN_Msk (0x1ul << EPWM_FDCTL5_FDDGEN_Pos) /*!< EPWM_T::FDCTL5: FDDGEN Mask */ + +#define EPWM_FDIEN_FDIEN0_Pos (0) /*!< EPWM_T::FDIEN: FDIEN0 Position */ +#define EPWM_FDIEN_FDIEN0_Msk (0x1ul << EPWM_FDIEN_FDIEN0_Pos) /*!< EPWM_T::FDIEN: FDIEN0 Mask */ + +#define EPWM_FDIEN_FDIEN1_Pos (1) /*!< EPWM_T::FDIEN: FDIEN1 Position */ +#define EPWM_FDIEN_FDIEN1_Msk (0x1ul << EPWM_FDIEN_FDIEN1_Pos) /*!< EPWM_T::FDIEN: FDIEN1 Mask */ + +#define EPWM_FDIEN_FDIEN2_Pos (2) /*!< EPWM_T::FDIEN: FDIEN2 Position */ +#define EPWM_FDIEN_FDIEN2_Msk (0x1ul << EPWM_FDIEN_FDIEN2_Pos) /*!< EPWM_T::FDIEN: FDIEN2 Mask */ + +#define EPWM_FDIEN_FDIEN3_Pos (3) /*!< EPWM_T::FDIEN: FDIEN3 Position */ +#define EPWM_FDIEN_FDIEN3_Msk (0x1ul << EPWM_FDIEN_FDIEN3_Pos) /*!< EPWM_T::FDIEN: FDIEN3 Mask */ + +#define EPWM_FDIEN_FDIEN4_Pos (4) /*!< EPWM_T::FDIEN: FDIEN4 Position */ +#define EPWM_FDIEN_FDIEN4_Msk (0x1ul << EPWM_FDIEN_FDIEN4_Pos) /*!< EPWM_T::FDIEN: FDIEN4 Mask */ + +#define EPWM_FDIEN_FDIEN5_Pos (5) /*!< EPWM_T::FDIEN: FDIEN5 Position */ +#define EPWM_FDIEN_FDIEN5_Msk (0x1ul << EPWM_FDIEN_FDIEN5_Pos) /*!< EPWM_T::FDIEN: FDIEN5 Mask */ + +#define EPWM_FDSTS_FDIF0_Pos (0) /*!< EPWM_T::FDSTS: FDIF0 Position */ +#define EPWM_FDSTS_FDIF0_Msk (0x1ul << EPWM_FDSTS_FDIF0_Pos) /*!< EPWM_T::FDSTS: FDIF0 Mask */ + +#define EPWM_FDSTS_FDIF1_Pos (1) /*!< EPWM_T::FDSTS: FDIF1 Position */ +#define EPWM_FDSTS_FDIF1_Msk (0x1ul << EPWM_FDSTS_FDIF1_Pos) /*!< EPWM_T::FDSTS: FDIF1 Mask */ + +#define EPWM_FDSTS_FDIF2_Pos (2) /*!< EPWM_T::FDSTS: FDIF2 Position */ +#define EPWM_FDSTS_FDIF2_Msk (0x1ul << EPWM_FDSTS_FDIF2_Pos) /*!< EPWM_T::FDSTS: FDIF2 Mask */ + +#define EPWM_FDSTS_FDIF3_Pos (3) /*!< EPWM_T::FDSTS: FDIF3 Position */ +#define EPWM_FDSTS_FDIF3_Msk (0x1ul << EPWM_FDSTS_FDIF3_Pos) /*!< EPWM_T::FDSTS: FDIF3 Mask */ + +#define EPWM_FDSTS_FDIF4_Pos (4) /*!< EPWM_T::FDSTS: FDIF4 Position */ +#define EPWM_FDSTS_FDIF4_Msk (0x1ul << EPWM_FDSTS_FDIF4_Pos) /*!< EPWM_T::FDSTS: FDIF4 Mask */ + +#define EPWM_FDSTS_FDIF5_Pos (5) /*!< EPWM_T::FDSTS: FDIF5 Position */ +#define EPWM_FDSTS_FDIF5_Msk (0x1ul << EPWM_FDSTS_FDIF5_Pos) /*!< EPWM_T::FDSTS: FDIF5 Mask */ + +#define EPWM_EADCPSCCTL_PSCEN0_Pos (0) /*!< EPWM_T::EADCPSCCTL: PSCEN0 Position */ +#define EPWM_EADCPSCCTL_PSCEN0_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN0_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN0 Mask */ + +#define EPWM_EADCPSCCTL_PSCEN1_Pos (1) /*!< EPWM_T::EADCPSCCTL: PSCEN1 Position */ +#define EPWM_EADCPSCCTL_PSCEN1_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN1_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN1 Mask */ + +#define EPWM_EADCPSCCTL_PSCEN2_Pos (2) /*!< EPWM_T::EADCPSCCTL: PSCEN2 Position */ +#define EPWM_EADCPSCCTL_PSCEN2_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN2_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN2 Mask */ + +#define EPWM_EADCPSCCTL_PSCEN3_Pos (3) /*!< EPWM_T::EADCPSCCTL: PSCEN3 Position */ +#define EPWM_EADCPSCCTL_PSCEN3_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN3_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN3 Mask */ + +#define EPWM_EADCPSCCTL_PSCEN4_Pos (4) /*!< EPWM_T::EADCPSCCTL: PSCEN4 Position */ +#define EPWM_EADCPSCCTL_PSCEN4_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN4_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN4 Mask */ + +#define EPWM_EADCPSCCTL_PSCEN5_Pos (5) /*!< EPWM_T::EADCPSCCTL: PSCEN5 Position */ +#define EPWM_EADCPSCCTL_PSCEN5_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN5_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN5 Mask */ + +#define EPWM_EADCPSC0_EADCPSC0_Pos (0) /*!< EPWM_T::EADCPSC0: EADCPSC0 Position */ +#define EPWM_EADCPSC0_EADCPSC0_Msk (0xful << EPWM_EADCPSC0_EADCPSC0_Pos) /*!< EPWM_T::EADCPSC0: EADCPSC0 Mask */ + +#define EPWM_EADCPSC0_EADCPSC1_Pos (8) /*!< EPWM_T::EADCPSC0: EADCPSC1 Position */ +#define EPWM_EADCPSC0_EADCPSC1_Msk (0xful << EPWM_EADCPSC0_EADCPSC1_Pos) /*!< EPWM_T::EADCPSC0: EADCPSC1 Mask */ + +#define EPWM_EADCPSC0_EADCPSC2_Pos (16) /*!< EPWM_T::EADCPSC0: EADCPSC2 Position */ +#define EPWM_EADCPSC0_EADCPSC2_Msk (0xful << EPWM_EADCPSC0_EADCPSC2_Pos) /*!< EPWM_T::EADCPSC0: EADCPSC2 Mask */ + +#define EPWM_EADCPSC0_EADCPSC3_Pos (24) /*!< EPWM_T::EADCPSC0: EADCPSC3 Position */ +#define EPWM_EADCPSC0_EADCPSC3_Msk (0xful << EPWM_EADCPSC0_EADCPSC3_Pos) /*!< EPWM_T::EADCPSC0: EADCPSC3 Mask */ + +#define EPWM_EADCPSC1_EADCPSC4_Pos (0) /*!< EPWM_T::EADCPSC1: EADCPSC4 Position */ +#define EPWM_EADCPSC1_EADCPSC4_Msk (0xful << EPWM_EADCPSC1_EADCPSC4_Pos) /*!< EPWM_T::EADCPSC1: EADCPSC4 Mask */ + +#define EPWM_EADCPSC1_EADCPSC5_Pos (8) /*!< EPWM_T::EADCPSC1: EADCPSC5 Position */ +#define EPWM_EADCPSC1_EADCPSC5_Msk (0xful << EPWM_EADCPSC1_EADCPSC5_Pos) /*!< EPWM_T::EADCPSC1: EADCPSC5 Mask */ + +#define EPWM_EADCPSCNT0_PSCNT0_Pos (0) /*!< EPWM_T::EADCPSCNT0: PSCNT0 Position */ +#define EPWM_EADCPSCNT0_PSCNT0_Msk (0xful << EPWM_EADCPSCNT0_PSCNT0_Pos) /*!< EPWM_T::EADCPSCNT0: PSCNT0 Mask */ + +#define EPWM_EADCPSCNT0_PSCNT1_Pos (8) /*!< EPWM_T::EADCPSCNT0: PSCNT1 Position */ +#define EPWM_EADCPSCNT0_PSCNT1_Msk (0xful << EPWM_EADCPSCNT0_PSCNT1_Pos) /*!< EPWM_T::EADCPSCNT0: PSCNT1 Mask */ + +#define EPWM_EADCPSCNT0_PSCNT2_Pos (16) /*!< EPWM_T::EADCPSCNT0: PSCNT2 Position */ +#define EPWM_EADCPSCNT0_PSCNT2_Msk (0xful << EPWM_EADCPSCNT0_PSCNT2_Pos) /*!< EPWM_T::EADCPSCNT0: PSCNT2 Mask */ + +#define EPWM_EADCPSCNT0_PSCNT3_Pos (24) /*!< EPWM_T::EADCPSCNT0: PSCNT3 Position */ +#define EPWM_EADCPSCNT0_PSCNT3_Msk (0xful << EPWM_EADCPSCNT0_PSCNT3_Pos) /*!< EPWM_T::EADCPSCNT0: PSCNT3 Mask */ + +#define EPWM_EADCPSCNT1_PSCNT4_Pos (0) /*!< EPWM_T::EADCPSCNT1: PSCNT4 Position */ +#define EPWM_EADCPSCNT1_PSCNT4_Msk (0xful << EPWM_EADCPSCNT1_PSCNT4_Pos) /*!< EPWM_T::EADCPSCNT1: PSCNT4 Mask */ + +#define EPWM_EADCPSCNT1_PSCNT5_Pos (8) /*!< EPWM_T::EADCPSCNT1: PSCNT5 Position */ +#define EPWM_EADCPSCNT1_PSCNT5_Msk (0xful << EPWM_EADCPSCNT1_PSCNT5_Pos) /*!< EPWM_T::EADCPSCNT1: PSCNT5 Mask */ + +#define EPWM_CAPINEN_CAPINEN0_Pos (0) /*!< EPWM_T::CAPINEN: CAPINEN0 Position */ +#define EPWM_CAPINEN_CAPINEN0_Msk (0x1ul << EPWM_CAPINEN_CAPINEN0_Pos) /*!< EPWM_T::CAPINEN: CAPINEN0 Mask */ + +#define EPWM_CAPINEN_CAPINEN1_Pos (1) /*!< EPWM_T::CAPINEN: CAPINEN1 Position */ +#define EPWM_CAPINEN_CAPINEN1_Msk (0x1ul << EPWM_CAPINEN_CAPINEN1_Pos) /*!< EPWM_T::CAPINEN: CAPINEN1 Mask */ + +#define EPWM_CAPINEN_CAPINEN2_Pos (2) /*!< EPWM_T::CAPINEN: CAPINEN2 Position */ +#define EPWM_CAPINEN_CAPINEN2_Msk (0x1ul << EPWM_CAPINEN_CAPINEN2_Pos) /*!< EPWM_T::CAPINEN: CAPINEN2 Mask */ + +#define EPWM_CAPINEN_CAPINEN3_Pos (3) /*!< EPWM_T::CAPINEN: CAPINEN3 Position */ +#define EPWM_CAPINEN_CAPINEN3_Msk (0x1ul << EPWM_CAPINEN_CAPINEN3_Pos) /*!< EPWM_T::CAPINEN: CAPINEN3 Mask */ + +#define EPWM_CAPINEN_CAPINEN4_Pos (4) /*!< EPWM_T::CAPINEN: CAPINEN4 Position */ +#define EPWM_CAPINEN_CAPINEN4_Msk (0x1ul << EPWM_CAPINEN_CAPINEN4_Pos) /*!< EPWM_T::CAPINEN: CAPINEN4 Mask */ + +#define EPWM_CAPINEN_CAPINEN5_Pos (5) /*!< EPWM_T::CAPINEN: CAPINEN5 Position */ +#define EPWM_CAPINEN_CAPINEN5_Msk (0x1ul << EPWM_CAPINEN_CAPINEN5_Pos) /*!< EPWM_T::CAPINEN: CAPINEN5 Mask */ + +#define EPWM_CAPCTL_CAPEN0_Pos (0) /*!< EPWM_T::CAPCTL: CAPEN0 Position */ +#define EPWM_CAPCTL_CAPEN0_Msk (0x1ul << EPWM_CAPCTL_CAPEN0_Pos) /*!< EPWM_T::CAPCTL: CAPEN0 Mask */ + +#define EPWM_CAPCTL_CAPEN1_Pos (1) /*!< EPWM_T::CAPCTL: CAPEN1 Position */ +#define EPWM_CAPCTL_CAPEN1_Msk (0x1ul << EPWM_CAPCTL_CAPEN1_Pos) /*!< EPWM_T::CAPCTL: CAPEN1 Mask */ + +#define EPWM_CAPCTL_CAPEN2_Pos (2) /*!< EPWM_T::CAPCTL: CAPEN2 Position */ +#define EPWM_CAPCTL_CAPEN2_Msk (0x1ul << EPWM_CAPCTL_CAPEN2_Pos) /*!< EPWM_T::CAPCTL: CAPEN2 Mask */ + +#define EPWM_CAPCTL_CAPEN3_Pos (3) /*!< EPWM_T::CAPCTL: CAPEN3 Position */ +#define EPWM_CAPCTL_CAPEN3_Msk (0x1ul << EPWM_CAPCTL_CAPEN3_Pos) /*!< EPWM_T::CAPCTL: CAPEN3 Mask */ + +#define EPWM_CAPCTL_CAPEN4_Pos (4) /*!< EPWM_T::CAPCTL: CAPEN4 Position */ +#define EPWM_CAPCTL_CAPEN4_Msk (0x1ul << EPWM_CAPCTL_CAPEN4_Pos) /*!< EPWM_T::CAPCTL: CAPEN4 Mask */ + +#define EPWM_CAPCTL_CAPEN5_Pos (5) /*!< EPWM_T::CAPCTL: CAPEN5 Position */ +#define EPWM_CAPCTL_CAPEN5_Msk (0x1ul << EPWM_CAPCTL_CAPEN5_Pos) /*!< EPWM_T::CAPCTL: CAPEN5 Mask */ + +#define EPWM_CAPCTL_CAPINV0_Pos (8) /*!< EPWM_T::CAPCTL: CAPINV0 Position */ +#define EPWM_CAPCTL_CAPINV0_Msk (0x1ul << EPWM_CAPCTL_CAPINV0_Pos) /*!< EPWM_T::CAPCTL: CAPINV0 Mask */ + +#define EPWM_CAPCTL_CAPINV1_Pos (9) /*!< EPWM_T::CAPCTL: CAPINV1 Position */ +#define EPWM_CAPCTL_CAPINV1_Msk (0x1ul << EPWM_CAPCTL_CAPINV1_Pos) /*!< EPWM_T::CAPCTL: CAPINV1 Mask */ + +#define EPWM_CAPCTL_CAPINV2_Pos (10) /*!< EPWM_T::CAPCTL: CAPINV2 Position */ +#define EPWM_CAPCTL_CAPINV2_Msk (0x1ul << EPWM_CAPCTL_CAPINV2_Pos) /*!< EPWM_T::CAPCTL: CAPINV2 Mask */ + +#define EPWM_CAPCTL_CAPINV3_Pos (11) /*!< EPWM_T::CAPCTL: CAPINV3 Position */ +#define EPWM_CAPCTL_CAPINV3_Msk (0x1ul << EPWM_CAPCTL_CAPINV3_Pos) /*!< EPWM_T::CAPCTL: CAPINV3 Mask */ + +#define EPWM_CAPCTL_CAPINV4_Pos (12) /*!< EPWM_T::CAPCTL: CAPINV4 Position */ +#define EPWM_CAPCTL_CAPINV4_Msk (0x1ul << EPWM_CAPCTL_CAPINV4_Pos) /*!< EPWM_T::CAPCTL: CAPINV4 Mask */ + +#define EPWM_CAPCTL_CAPINV5_Pos (13) /*!< EPWM_T::CAPCTL: CAPINV5 Position */ +#define EPWM_CAPCTL_CAPINV5_Msk (0x1ul << EPWM_CAPCTL_CAPINV5_Pos) /*!< EPWM_T::CAPCTL: CAPINV5 Mask */ + +#define EPWM_CAPCTL_RCRLDEN0_Pos (16) /*!< EPWM_T::CAPCTL: RCRLDEN0 Position */ +#define EPWM_CAPCTL_RCRLDEN0_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN0_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN0 Mask */ + +#define EPWM_CAPCTL_RCRLDEN1_Pos (17) /*!< EPWM_T::CAPCTL: RCRLDEN1 Position */ +#define EPWM_CAPCTL_RCRLDEN1_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN1_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN1 Mask */ + +#define EPWM_CAPCTL_RCRLDEN2_Pos (18) /*!< EPWM_T::CAPCTL: RCRLDEN2 Position */ +#define EPWM_CAPCTL_RCRLDEN2_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN2_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN2 Mask */ + +#define EPWM_CAPCTL_RCRLDEN3_Pos (19) /*!< EPWM_T::CAPCTL: RCRLDEN3 Position */ +#define EPWM_CAPCTL_RCRLDEN3_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN3_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN3 Mask */ + +#define EPWM_CAPCTL_RCRLDEN4_Pos (20) /*!< EPWM_T::CAPCTL: RCRLDEN4 Position */ +#define EPWM_CAPCTL_RCRLDEN4_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN4_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN4 Mask */ + +#define EPWM_CAPCTL_RCRLDEN5_Pos (21) /*!< EPWM_T::CAPCTL: RCRLDEN5 Position */ +#define EPWM_CAPCTL_RCRLDEN5_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN5_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN5 Mask */ + +#define EPWM_CAPCTL_FCRLDEN0_Pos (24) /*!< EPWM_T::CAPCTL: FCRLDEN0 Position */ +#define EPWM_CAPCTL_FCRLDEN0_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN0_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN0 Mask */ + +#define EPWM_CAPCTL_FCRLDEN1_Pos (25) /*!< EPWM_T::CAPCTL: FCRLDEN1 Position */ +#define EPWM_CAPCTL_FCRLDEN1_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN1_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN1 Mask */ + +#define EPWM_CAPCTL_FCRLDEN2_Pos (26) /*!< EPWM_T::CAPCTL: FCRLDEN2 Position */ +#define EPWM_CAPCTL_FCRLDEN2_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN2_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN2 Mask */ + +#define EPWM_CAPCTL_FCRLDEN3_Pos (27) /*!< EPWM_T::CAPCTL: FCRLDEN3 Position */ +#define EPWM_CAPCTL_FCRLDEN3_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN3_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN3 Mask */ + +#define EPWM_CAPCTL_FCRLDEN4_Pos (28) /*!< EPWM_T::CAPCTL: FCRLDEN4 Position */ +#define EPWM_CAPCTL_FCRLDEN4_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN4_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN4 Mask */ + +#define EPWM_CAPCTL_FCRLDEN5_Pos (29) /*!< EPWM_T::CAPCTL: FCRLDEN5 Position */ +#define EPWM_CAPCTL_FCRLDEN5_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN5_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN5 Mask */ + +#define EPWM_CAPSTS_CRLIFOV0_Pos (0) /*!< EPWM_T::CAPSTS: CRLIFOV0 Position */ +#define EPWM_CAPSTS_CRLIFOV0_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV0_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV0 Mask */ + +#define EPWM_CAPSTS_CRLIFOV1_Pos (1) /*!< EPWM_T::CAPSTS: CRLIFOV1 Position */ +#define EPWM_CAPSTS_CRLIFOV1_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV1_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV1 Mask */ + +#define EPWM_CAPSTS_CRLIFOV2_Pos (2) /*!< EPWM_T::CAPSTS: CRLIFOV2 Position */ +#define EPWM_CAPSTS_CRLIFOV2_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV2_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV2 Mask */ + +#define EPWM_CAPSTS_CRLIFOV3_Pos (3) /*!< EPWM_T::CAPSTS: CRLIFOV3 Position */ +#define EPWM_CAPSTS_CRLIFOV3_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV3_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV3 Mask */ + +#define EPWM_CAPSTS_CRLIFOV4_Pos (4) /*!< EPWM_T::CAPSTS: CRLIFOV4 Position */ +#define EPWM_CAPSTS_CRLIFOV4_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV4_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV4 Mask */ + +#define EPWM_CAPSTS_CRLIFOV5_Pos (5) /*!< EPWM_T::CAPSTS: CRLIFOV5 Position */ +#define EPWM_CAPSTS_CRLIFOV5_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV5_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV5 Mask */ + +#define EPWM_CAPSTS_CFLIFOV0_Pos (8) /*!< EPWM_T::CAPSTS: CFLIFOV0 Position */ +#define EPWM_CAPSTS_CFLIFOV0_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV0_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV0 Mask */ + +#define EPWM_CAPSTS_CFLIFOV1_Pos (9) /*!< EPWM_T::CAPSTS: CFLIFOV1 Position */ +#define EPWM_CAPSTS_CFLIFOV1_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV1_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV1 Mask */ + +#define EPWM_CAPSTS_CFLIFOV2_Pos (10) /*!< EPWM_T::CAPSTS: CFLIFOV2 Position */ +#define EPWM_CAPSTS_CFLIFOV2_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV2_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV2 Mask */ + +#define EPWM_CAPSTS_CFLIFOV3_Pos (11) /*!< EPWM_T::CAPSTS: CFLIFOV3 Position */ +#define EPWM_CAPSTS_CFLIFOV3_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV3_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV3 Mask */ + +#define EPWM_CAPSTS_CFLIFOV4_Pos (12) /*!< EPWM_T::CAPSTS: CFLIFOV4 Position */ +#define EPWM_CAPSTS_CFLIFOV4_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV4_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV4 Mask */ + +#define EPWM_CAPSTS_CFLIFOV5_Pos (13) /*!< EPWM_T::CAPSTS: CFLIFOV5 Position */ +#define EPWM_CAPSTS_CFLIFOV5_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV5_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV5 Mask */ + +#define EPWM_RCAPDAT0_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT0: RCAPDAT Position */ +#define EPWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT0_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT0: RCAPDAT Mask */ + +#define EPWM_FCAPDAT0_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT0: FCAPDAT Position */ +#define EPWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT0_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT0: FCAPDAT Mask */ + +#define EPWM_RCAPDAT1_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT1: RCAPDAT Position */ +#define EPWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT1_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT1: RCAPDAT Mask */ + +#define EPWM_FCAPDAT1_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT1: FCAPDAT Position */ +#define EPWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT1_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT1: FCAPDAT Mask */ + +#define EPWM_RCAPDAT2_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT2: RCAPDAT Position */ +#define EPWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT2_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT2: RCAPDAT Mask */ + +#define EPWM_FCAPDAT2_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT2: FCAPDAT Position */ +#define EPWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT2_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT2: FCAPDAT Mask */ + +#define EPWM_RCAPDAT3_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT3: RCAPDAT Position */ +#define EPWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT3_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT3: RCAPDAT Mask */ + +#define EPWM_FCAPDAT3_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT3: FCAPDAT Position */ +#define EPWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT3_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT3: FCAPDAT Mask */ + +#define EPWM_RCAPDAT4_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT4: RCAPDAT Position */ +#define EPWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT4_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT4: RCAPDAT Mask */ + +#define EPWM_FCAPDAT4_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT4: FCAPDAT Position */ +#define EPWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT4_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT4: FCAPDAT Mask */ + +#define EPWM_RCAPDAT5_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT5: RCAPDAT Position */ +#define EPWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT5_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT5: RCAPDAT Mask */ + +#define EPWM_FCAPDAT5_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT5: FCAPDAT Position */ +#define EPWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT5_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT5: FCAPDAT Mask */ + +#define EPWM_PDMACTL_CHEN0_1_Pos (0) /*!< EPWM_T::PDMACTL: CHEN0_1 Position */ +#define EPWM_PDMACTL_CHEN0_1_Msk (0x1ul << EPWM_PDMACTL_CHEN0_1_Pos) /*!< EPWM_T::PDMACTL: CHEN0_1 Mask */ + +#define EPWM_PDMACTL_CAPMOD0_1_Pos (1) /*!< EPWM_T::PDMACTL: CAPMOD0_1 Position */ +#define EPWM_PDMACTL_CAPMOD0_1_Msk (0x3ul << EPWM_PDMACTL_CAPMOD0_1_Pos) /*!< EPWM_T::PDMACTL: CAPMOD0_1 Mask */ + +#define EPWM_PDMACTL_CAPORD0_1_Pos (3) /*!< EPWM_T::PDMACTL: CAPORD0_1 Position */ +#define EPWM_PDMACTL_CAPORD0_1_Msk (0x1ul << EPWM_PDMACTL_CAPORD0_1_Pos) /*!< EPWM_T::PDMACTL: CAPORD0_1 Mask */ + +#define EPWM_PDMACTL_CHSEL0_1_Pos (4) /*!< EPWM_T::PDMACTL: CHSEL0_1 Position */ +#define EPWM_PDMACTL_CHSEL0_1_Msk (0x1ul << EPWM_PDMACTL_CHSEL0_1_Pos) /*!< EPWM_T::PDMACTL: CHSEL0_1 Mask */ + +#define EPWM_PDMACTL_CHEN2_3_Pos (8) /*!< EPWM_T::PDMACTL: CHEN2_3 Position */ +#define EPWM_PDMACTL_CHEN2_3_Msk (0x1ul << EPWM_PDMACTL_CHEN2_3_Pos) /*!< EPWM_T::PDMACTL: CHEN2_3 Mask */ + +#define EPWM_PDMACTL_CAPMOD2_3_Pos (9) /*!< EPWM_T::PDMACTL: CAPMOD2_3 Position */ +#define EPWM_PDMACTL_CAPMOD2_3_Msk (0x3ul << EPWM_PDMACTL_CAPMOD2_3_Pos) /*!< EPWM_T::PDMACTL: CAPMOD2_3 Mask */ + +#define EPWM_PDMACTL_CAPORD2_3_Pos (11) /*!< EPWM_T::PDMACTL: CAPORD2_3 Position */ +#define EPWM_PDMACTL_CAPORD2_3_Msk (0x1ul << EPWM_PDMACTL_CAPORD2_3_Pos) /*!< EPWM_T::PDMACTL: CAPORD2_3 Mask */ + +#define EPWM_PDMACTL_CHSEL2_3_Pos (12) /*!< EPWM_T::PDMACTL: CHSEL2_3 Position */ +#define EPWM_PDMACTL_CHSEL2_3_Msk (0x1ul << EPWM_PDMACTL_CHSEL2_3_Pos) /*!< EPWM_T::PDMACTL: CHSEL2_3 Mask */ + +#define EPWM_PDMACTL_CHEN4_5_Pos (16) /*!< EPWM_T::PDMACTL: CHEN4_5 Position */ +#define EPWM_PDMACTL_CHEN4_5_Msk (0x1ul << EPWM_PDMACTL_CHEN4_5_Pos) /*!< EPWM_T::PDMACTL: CHEN4_5 Mask */ + +#define EPWM_PDMACTL_CAPMOD4_5_Pos (17) /*!< EPWM_T::PDMACTL: CAPMOD4_5 Position */ +#define EPWM_PDMACTL_CAPMOD4_5_Msk (0x3ul << EPWM_PDMACTL_CAPMOD4_5_Pos) /*!< EPWM_T::PDMACTL: CAPMOD4_5 Mask */ + +#define EPWM_PDMACTL_CAPORD4_5_Pos (19) /*!< EPWM_T::PDMACTL: CAPORD4_5 Position */ +#define EPWM_PDMACTL_CAPORD4_5_Msk (0x1ul << EPWM_PDMACTL_CAPORD4_5_Pos) /*!< EPWM_T::PDMACTL: CAPORD4_5 Mask */ + +#define EPWM_PDMACTL_CHSEL4_5_Pos (20) /*!< EPWM_T::PDMACTL: CHSEL4_5 Position */ +#define EPWM_PDMACTL_CHSEL4_5_Msk (0x1ul << EPWM_PDMACTL_CHSEL4_5_Pos) /*!< EPWM_T::PDMACTL: CHSEL4_5 Mask */ + +#define EPWM_PDMACAP0_1_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP0_1: CAPBUF Position */ +#define EPWM_PDMACAP0_1_CAPBUF_Msk (0xfffful << EPWM_PDMACAP0_1_CAPBUF_Pos) /*!< EPWM_T::PDMACAP0_1: CAPBUF Mask */ + +#define EPWM_PDMACAP2_3_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP2_3: CAPBUF Position */ +#define EPWM_PDMACAP2_3_CAPBUF_Msk (0xfffful << EPWM_PDMACAP2_3_CAPBUF_Pos) /*!< EPWM_T::PDMACAP2_3: CAPBUF Mask */ + +#define EPWM_PDMACAP4_5_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP4_5: CAPBUF Position */ +#define EPWM_PDMACAP4_5_CAPBUF_Msk (0xfffful << EPWM_PDMACAP4_5_CAPBUF_Pos) /*!< EPWM_T::PDMACAP4_5: CAPBUF Mask */ + +#define EPWM_CAPIEN_CAPRIEN0_Pos (0) /*!< EPWM_T::CAPIEN: CAPRIEN0 Position */ +#define EPWM_CAPIEN_CAPRIEN0_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN0_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN0 Mask */ + +#define EPWM_CAPIEN_CAPRIEN1_Pos (1) /*!< EPWM_T::CAPIEN: CAPRIEN1 Position */ +#define EPWM_CAPIEN_CAPRIEN1_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN1_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN1 Mask */ + +#define EPWM_CAPIEN_CAPRIEN2_Pos (2) /*!< EPWM_T::CAPIEN: CAPRIEN2 Position */ +#define EPWM_CAPIEN_CAPRIEN2_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN2_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN2 Mask */ + +#define EPWM_CAPIEN_CAPRIEN3_Pos (3) /*!< EPWM_T::CAPIEN: CAPRIEN3 Position */ +#define EPWM_CAPIEN_CAPRIEN3_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN3_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN3 Mask */ + +#define EPWM_CAPIEN_CAPRIEN4_Pos (4) /*!< EPWM_T::CAPIEN: CAPRIEN4 Position */ +#define EPWM_CAPIEN_CAPRIEN4_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN4_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN4 Mask */ + +#define EPWM_CAPIEN_CAPRIEN5_Pos (5) /*!< EPWM_T::CAPIEN: CAPRIEN5 Position */ +#define EPWM_CAPIEN_CAPRIEN5_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN5_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN5 Mask */ + +#define EPWM_CAPIEN_CAPFIEN0_Pos (8) /*!< EPWM_T::CAPIEN: CAPFIEN0 Position */ +#define EPWM_CAPIEN_CAPFIEN0_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN0_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN0 Mask */ + +#define EPWM_CAPIEN_CAPFIEN1_Pos (9) /*!< EPWM_T::CAPIEN: CAPFIEN1 Position */ +#define EPWM_CAPIEN_CAPFIEN1_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN1_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN1 Mask */ + +#define EPWM_CAPIEN_CAPFIEN2_Pos (10) /*!< EPWM_T::CAPIEN: CAPFIEN2 Position */ +#define EPWM_CAPIEN_CAPFIEN2_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN2_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN2 Mask */ + +#define EPWM_CAPIEN_CAPFIEN3_Pos (11) /*!< EPWM_T::CAPIEN: CAPFIEN3 Position */ +#define EPWM_CAPIEN_CAPFIEN3_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN3_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN3 Mask */ + +#define EPWM_CAPIEN_CAPFIEN4_Pos (12) /*!< EPWM_T::CAPIEN: CAPFIEN4 Position */ +#define EPWM_CAPIEN_CAPFIEN4_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN4_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN4 Mask */ + +#define EPWM_CAPIEN_CAPFIEN5_Pos (13) /*!< EPWM_T::CAPIEN: CAPFIEN5 Position */ +#define EPWM_CAPIEN_CAPFIEN5_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN5_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN5 Mask */ + +#define EPWM_CAPIF_CRLIF0_Pos (0) /*!< EPWM_T::CAPIF: CRLIF0 Position */ +#define EPWM_CAPIF_CRLIF0_Msk (0x1ul << EPWM_CAPIF_CRLIF0_Pos) /*!< EPWM_T::CAPIF: CRLIF0 Mask */ + +#define EPWM_CAPIF_CRLIF1_Pos (1) /*!< EPWM_T::CAPIF: CRLIF1 Position */ +#define EPWM_CAPIF_CRLIF1_Msk (0x1ul << EPWM_CAPIF_CRLIF1_Pos) /*!< EPWM_T::CAPIF: CRLIF1 Mask */ + +#define EPWM_CAPIF_CRLIF2_Pos (2) /*!< EPWM_T::CAPIF: CRLIF2 Position */ +#define EPWM_CAPIF_CRLIF2_Msk (0x1ul << EPWM_CAPIF_CRLIF2_Pos) /*!< EPWM_T::CAPIF: CRLIF2 Mask */ + +#define EPWM_CAPIF_CRLIF3_Pos (3) /*!< EPWM_T::CAPIF: CRLIF3 Position */ +#define EPWM_CAPIF_CRLIF3_Msk (0x1ul << EPWM_CAPIF_CRLIF3_Pos) /*!< EPWM_T::CAPIF: CRLIF3 Mask */ + +#define EPWM_CAPIF_CRLIF4_Pos (4) /*!< EPWM_T::CAPIF: CRLIF4 Position */ +#define EPWM_CAPIF_CRLIF4_Msk (0x1ul << EPWM_CAPIF_CRLIF4_Pos) /*!< EPWM_T::CAPIF: CRLIF4 Mask */ + +#define EPWM_CAPIF_CRLIF5_Pos (5) /*!< EPWM_T::CAPIF: CRLIF5 Position */ +#define EPWM_CAPIF_CRLIF5_Msk (0x1ul << EPWM_CAPIF_CRLIF5_Pos) /*!< EPWM_T::CAPIF: CRLIF5 Mask */ + +#define EPWM_CAPIF_CFLIF0_Pos (8) /*!< EPWM_T::CAPIF: CFLIF0 Position */ +#define EPWM_CAPIF_CFLIF0_Msk (0x1ul << EPWM_CAPIF_CFLIF0_Pos) /*!< EPWM_T::CAPIF: CFLIF0 Mask */ + +#define EPWM_CAPIF_CFLIF1_Pos (9) /*!< EPWM_T::CAPIF: CFLIF1 Position */ +#define EPWM_CAPIF_CFLIF1_Msk (0x1ul << EPWM_CAPIF_CFLIF1_Pos) /*!< EPWM_T::CAPIF: CFLIF1 Mask */ + +#define EPWM_CAPIF_CFLIF2_Pos (10) /*!< EPWM_T::CAPIF: CFLIF2 Position */ +#define EPWM_CAPIF_CFLIF2_Msk (0x1ul << EPWM_CAPIF_CFLIF2_Pos) /*!< EPWM_T::CAPIF: CFLIF2 Mask */ + +#define EPWM_CAPIF_CFLIF3_Pos (11) /*!< EPWM_T::CAPIF: CFLIF3 Position */ +#define EPWM_CAPIF_CFLIF3_Msk (0x1ul << EPWM_CAPIF_CFLIF3_Pos) /*!< EPWM_T::CAPIF: CFLIF3 Mask */ + +#define EPWM_CAPIF_CFLIF4_Pos (12) /*!< EPWM_T::CAPIF: CFLIF4 Position */ +#define EPWM_CAPIF_CFLIF4_Msk (0x1ul << EPWM_CAPIF_CFLIF4_Pos) /*!< EPWM_T::CAPIF: CFLIF4 Mask */ + +#define EPWM_CAPIF_CFLIF5_Pos (13) /*!< EPWM_T::CAPIF: CFLIF5 Position */ +#define EPWM_CAPIF_CFLIF5_Msk (0x1ul << EPWM_CAPIF_CFLIF5_Pos) /*!< EPWM_T::CAPIF: CFLIF5 Mask */ + +#define EPWM_PBUF0_PBUF_Pos (0) /*!< EPWM_T::PBUF0: PBUF Position */ +#define EPWM_PBUF0_PBUF_Msk (0xfffful << EPWM_PBUF0_PBUF_Pos) /*!< EPWM_T::PBUF0: PBUF Mask */ + +#define EPWM_PBUF1_PBUF_Pos (0) /*!< EPWM_T::PBUF1: PBUF Position */ +#define EPWM_PBUF1_PBUF_Msk (0xfffful << EPWM_PBUF1_PBUF_Pos) /*!< EPWM_T::PBUF1: PBUF Mask */ + +#define EPWM_PBUF2_PBUF_Pos (0) /*!< EPWM_T::PBUF2: PBUF Position */ +#define EPWM_PBUF2_PBUF_Msk (0xfffful << EPWM_PBUF2_PBUF_Pos) /*!< EPWM_T::PBUF2: PBUF Mask */ + +#define EPWM_PBUF3_PBUF_Pos (0) /*!< EPWM_T::PBUF3: PBUF Position */ +#define EPWM_PBUF3_PBUF_Msk (0xfffful << EPWM_PBUF3_PBUF_Pos) /*!< EPWM_T::PBUF3: PBUF Mask */ + +#define EPWM_PBUF4_PBUF_Pos (0) /*!< EPWM_T::PBUF4: PBUF Position */ +#define EPWM_PBUF4_PBUF_Msk (0xfffful << EPWM_PBUF4_PBUF_Pos) /*!< EPWM_T::PBUF4: PBUF Mask */ + +#define EPWM_PBUF5_PBUF_Pos (0) /*!< EPWM_T::PBUF5: PBUF Position */ +#define EPWM_PBUF5_PBUF_Msk (0xfffful << EPWM_PBUF5_PBUF_Pos) /*!< EPWM_T::PBUF5: PBUF Mask */ + +#define EPWM_CMPBUF0_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF0: CMPBUF Position */ +#define EPWM_CMPBUF0_CMPBUF_Msk (0xfffful << EPWM_CMPBUF0_CMPBUF_Pos) /*!< EPWM_T::CMPBUF0: CMPBUF Mask */ + +#define EPWM_CMPBUF1_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF1: CMPBUF Position */ +#define EPWM_CMPBUF1_CMPBUF_Msk (0xfffful << EPWM_CMPBUF1_CMPBUF_Pos) /*!< EPWM_T::CMPBUF1: CMPBUF Mask */ + +#define EPWM_CMPBUF2_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF2: CMPBUF Position */ +#define EPWM_CMPBUF2_CMPBUF_Msk (0xfffful << EPWM_CMPBUF2_CMPBUF_Pos) /*!< EPWM_T::CMPBUF2: CMPBUF Mask */ + +#define EPWM_CMPBUF3_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF3: CMPBUF Position */ +#define EPWM_CMPBUF3_CMPBUF_Msk (0xfffful << EPWM_CMPBUF3_CMPBUF_Pos) /*!< EPWM_T::CMPBUF3: CMPBUF Mask */ + +#define EPWM_CMPBUF4_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF4: CMPBUF Position */ +#define EPWM_CMPBUF4_CMPBUF_Msk (0xfffful << EPWM_CMPBUF4_CMPBUF_Pos) /*!< EPWM_T::CMPBUF4: CMPBUF Mask */ + +#define EPWM_CMPBUF5_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF5: CMPBUF Position */ +#define EPWM_CMPBUF5_CMPBUF_Msk (0xfffful << EPWM_CMPBUF5_CMPBUF_Pos) /*!< EPWM_T::CMPBUF5: CMPBUF Mask */ + +#define EPWM_CPSCBUF0_1_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF0_1: CPSCBUF Position */ +#define EPWM_CPSCBUF0_1_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF0_1_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF0_1: CPSCBUF Mask */ + +#define EPWM_CPSCBUF2_3_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF2_3: CPSCBUF Position */ +#define EPWM_CPSCBUF2_3_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF2_3_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF2_3: CPSCBUF Mask */ + +#define EPWM_CPSCBUF4_5_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF4_5: CPSCBUF Position */ +#define EPWM_CPSCBUF4_5_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF4_5_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF4_5: CPSCBUF Mask */ + +#define EPWM_FTCBUF0_1_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF0_1: FTCMPBUF Position */ +#define EPWM_FTCBUF0_1_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF0_1_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF0_1: FTCMPBUF Mask */ + +#define EPWM_FTCBUF2_3_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF2_3: FTCMPBUF Position */ +#define EPWM_FTCBUF2_3_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF2_3_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF2_3: FTCMPBUF Mask */ + +#define EPWM_FTCBUF4_5_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF4_5: FTCMPBUF Position */ +#define EPWM_FTCBUF4_5_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF4_5_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF4_5: FTCMPBUF Mask */ + +#define EPWM_FTCI_FTCMU0_Pos (0) /*!< EPWM_T::FTCI: FTCMU0 Position */ +#define EPWM_FTCI_FTCMU0_Msk (0x1ul << EPWM_FTCI_FTCMU0_Pos) /*!< EPWM_T::FTCI: FTCMU0 Mask */ + +#define EPWM_FTCI_FTCMU2_Pos (1) /*!< EPWM_T::FTCI: FTCMU2 Position */ +#define EPWM_FTCI_FTCMU2_Msk (0x1ul << EPWM_FTCI_FTCMU2_Pos) /*!< EPWM_T::FTCI: FTCMU2 Mask */ + +#define EPWM_FTCI_FTCMU4_Pos (2) /*!< EPWM_T::FTCI: FTCMU4 Position */ +#define EPWM_FTCI_FTCMU4_Msk (0x1ul << EPWM_FTCI_FTCMU4_Pos) /*!< EPWM_T::FTCI: FTCMU4 Mask */ + +#define EPWM_FTCI_FTCMD0_Pos (8) /*!< EPWM_T::FTCI: FTCMD0 Position */ +#define EPWM_FTCI_FTCMD0_Msk (0x1ul << EPWM_FTCI_FTCMD0_Pos) /*!< EPWM_T::FTCI: FTCMD0 Mask */ + +#define EPWM_FTCI_FTCMD2_Pos (9) /*!< EPWM_T::FTCI: FTCMD2 Position */ +#define EPWM_FTCI_FTCMD2_Msk (0x1ul << EPWM_FTCI_FTCMD2_Pos) /*!< EPWM_T::FTCI: FTCMD2 Mask */ + +#define EPWM_FTCI_FTCMD4_Pos (10) /*!< EPWM_T::FTCI: FTCMD4 Position */ +#define EPWM_FTCI_FTCMD4_Msk (0x1ul << EPWM_FTCI_FTCMD4_Pos) /*!< EPWM_T::FTCI: FTCMD4 Mask */ + +/**@}*/ /* EPWM_CONST */ +/**@}*/ /* end of EPWM register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __EPWM_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/fmc_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/fmc_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..af50c0bfb39185ed9ac03604e0b12cd53eaec4c7 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/fmc_reg.h @@ -0,0 +1,688 @@ +/**************************************************************************//** + * @file fmc_reg.h + * @version V1.00 + * @brief FMC register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __FMC_REG_H__ +#define __FMC_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup FMC Flash Memory Controller(FMC) + Memory Mapped Structure for FMC Controller +@{ */ + +typedef struct +{ + /** + * @var FMC_T::ISPCTL + * Offset: 0x00 ISP Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ISPEN |ISP Enable Bit (Write Protect) + * | | |ISP function enable bit. Set this bit to enable ISP function. + * | | |0 = ISP function Disabled. + * | | |1 = ISP function Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[1] |BS |Boot Select (Write Protect) + * | | |When MBS in CONFIG0 is 1, set/clear this bit to select next booting from LDROM/APROM, respectively + * | | |This bit also functions as chip booting status flag, which can be used to check where chip booted from + * | | |This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened + * | | |0 = Booting from APROM when MBS (CONFIG0[5]) is 1. + * | | |1 = Booting from LDROM when MBS (CONFIG0[5]) is 1. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[2] |SPUEN |SPROM Update Enable Bit (Write Protect) + * | | |0 = SPROM cannot be updated. + * | | |1 = SPROM can be updated. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |APUEN |APROM Update Enable Bit (Write Protect) + * | | |0 = APROM cannot be updated when the chip runs in APROM. + * | | |1 = APROM can be updated when the chip runs in APROM. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[4] |CFGUEN |CONFIG Update Enable Bit (Write Protect) + * | | |0 = CONFIG cannot be updated. + * | | |1 = CONFIG can be updated. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[5] |LDUEN |LDROM Update Enable Bit (Write Protect) + * | | |LDROM update enable bit. + * | | |0 = LDROM cannot be updated. + * | | |1 = LDROM can be updated. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[6] |ISPFF |ISP Fail Flag (Write Protect) + * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: + * | | |This bit needs to be cleared by writing 1 to it. + * | | |(1) APROM writes to itself if APUEN is set to 0. + * | | |(2) LDROM writes to itself if LDUEN is set to 0. + * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0. + * | | |(4) SPROM is erased/programmed if SPUEN is set to 0 + * | | |(5) SPROM is programmed at SPROM secured mode. + * | | |(6) Page Erase command at LOCK mode with ICE connection + * | | |(7) Erase or Program command at brown-out detected + * | | |(8) Destination address is illegal, such as over an available range. + * | | |(9) Invalid ISP commands + * | | |(10) Vector address is mapping to SPROM region + * | | |(11) KPROM is erased/programmed if KEYLOCK is set to 1 + * | | |(12) APROM(except for Data Flash) is erased/programmed if KEYLOCK is set to 1 + * | | |(13) LDROM is erased/programmed if KEYLOCK is set to 1 + * | | |(14) SPROM is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1. + * | | |(15) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1 + * | | |(16) Invalid operations (except for chip erase) with ICE connection if SBLOCK is not 0x5A + * | | |(17) Read any content of boot loader with ICE connection + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[16] |BL |Boot Loader Booting (Write Protect) + * | | |This bit is initiated with the inversed value of MBS (CONFIG0[5]) + * | | |Any reset, except CPU reset (CPU is 1) or system reset (SYS), BL will be reloaded + * | | |This bit is used to check chip boot from Boot Loader or not + * | | |User should keep original value of this bit when updating FMC_ISPCTL register. + * | | |0 = Booting from APROM or LDROM. + * | | |1 = Booting from Boot Loader. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var FMC_T::ISPADDR + * Offset: 0x04 ISP Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPADDR |ISP Address + * | | |The NuMicro M480 series is equipped with embedded flash + * | | |ISPADDR[1:0] must be kept 00 for ISP 32-bit operation + * | | |ISPADDR[2:0] must be kept 000 for ISP 64-bit operation. + * | | |For CRC32 Checksum Calculation command, this field is the flash starting address for checksum calculation, 4 Kbytes alignment is necessary for CRC32 checksum calculation. + * | | |For FLASH 32-bit Program, ISP address needs word alignment (4-byte) + * | | |For FLASH 64-bit Program, ISP address needs double word alignment (8-byte). + * @var FMC_T::ISPDAT + * Offset: 0x08 ISP Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPDAT |ISP Data + * | | |Write data to this register before ISP program operation. + * | | |Read data from this register after ISP read operation. + * | | |When ISPFF (FMC_ISPCTL[6]) is 1, ISPDAT = 0xffff_ffff + * | | |For Run CRC32 Checksum Calculation command, ISPDAT is the memory size (byte) and 4 Kbytes alignment + * | | |For ISP Read CRC32 Checksum command, ISPDAT is the checksum result + * | | |If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, or (2) the memory range for checksum calculation is incorrect + * @var FMC_T::ISPCMD + * Offset: 0x0C ISP Command Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |CMD |ISP Command + * | | |ISP command table is shown below: + * | | |0x00= FLASH Read. + * | | |0x04= Read Unique ID. + * | | |0x08= Read Flash All-One Result. + * | | |0x0B= Read Company ID. + * | | |0x0C= Read Device ID. + * | | |0x0D= Read Checksum. + * | | |0x21= FLASH 32-bit Program. + * | | |0x22= FLASH Page Erase. Erase any page in two banks, except for OTP. + * | | |0x23= FLASH Bank Erase. Erase all pages of APROM in BANK0 or BANK1. + * | | |0x25= FLASH Block Erase. Erase four pages alignment of APROM in BANK0 or BANK1.. + * | | |0x27= FLASH Multi-Word Program. + * | | |0x28= Run Flash All-One Verification. + * | | |0x2D= Run Checksum Calculation. + * | | |0x2E= Vector Remap. + * | | |0x40= FLASH 64-bit Read. + * | | |0x61= FLASH 64-bit Program. + * | | |The other commands are invalid. + * @var FMC_T::ISPTRG + * Offset: 0x10 ISP Trigger Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ISPGO |ISP Start Trigger (Write Protect) + * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. + * | | |0 = ISP operation is finished. + * | | |1 = ISP is progressed. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var FMC_T::DFBA + * Offset: 0x14 Data Flash Base Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DFBA |Data Flash Base Address + * | | |This register indicates Data Flash start address. It is a read only register. + * | | |The Data Flash is shared with APROM. the content of this register is loaded from CONFIG1 + * | | |This register is valid when DFEN (CONFIG0[0]) =0 . + * @var FMC_T::ISPSTS + * Offset: 0x40 ISP Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ISPBUSY |ISP Busy Flag (Read Only) + * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. + * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]). + * | | |0 = ISP operation is finished. + * | | |1 = ISP is progressed. + * |[2:1] |CBS |Boot Selection of CONFIG (Read Only) + * | | |This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened. + * | | |The following function is valid when MBS (FMC_ISPSTS[3])= 1. + * | | |00 = LDROM with IAP mode. + * | | |01 = LDROM without IAP mode. + * | | |10 = APROM with IAP mode. + * | | |11 = APROM without IAP mode. + * |[3] |MBS |Boot From Boot Loader Selection Flag (Read Only) + * | | |This bit is initiated with the MBS (CONFIG0[5]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened + * | | |0 = Booting from Boot Loader. + * | | |1 = Booting from LDROM/APROM.(.see CBS bit setting) + * |[4] |FCYCDIS |Flash Access Cycle Auto-tuning Disabled Flag (Read Only) + * | | |This bit is set if flash access cycle auto-tuning function is disabled + * | | |The auto-tunning function is disabled by FADIS(FMC_CYCCTL[8]) or HIRC clock is not ready. + * | | |0 = Flash access cycle auto-tuning is enabled. + * | | |1 = Flash access cycle auto-tuning is disabled. + * |[5] |PGFF |Flash Program with Fast Verification Flag (Read Only) + * | | |This bit is set if data is mismatched at ISP programming verification + * | | |This bit is clear by performing ISP flash erase or ISP read CID operation + * | | |0 = Flash Program is success. + * | | |1 = Flash Program is fail. Program data is different with data in the flash memory + * |[6] |ISPFF |ISP Fail Flag (Write Protect) + * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6] + * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: + * | | |(1) APROM writes to itself if APUEN is set to 0. + * | | |(2) LDROM writes to itself if LDUEN is set to 0. + * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0. + * | | |(4) SPROM is erased/programmed if SPUEN is set to 0 + * | | |(5) SPROM is programmed at SPROM secured mode. + * | | |(6) Page Erase command at LOCK mode with ICE connection + * | | |(7) Erase or Program command at brown-out detected + * | | |(8) Destination address is illegal, such as over an available range. + * | | |(9) Invalid ISP commands + * | | |(10) Vector address is mapping to SPROM region. + * | | |(11) KPROM is erased/programmed if KEYLOCK is set to 1 + * | | |(12) APROM(except for Data Flash) is erased/programmed if KEYLOCK is set to 1 + * | | |(13) LDROM is erased/programmed if KEYLOCK is set to 1 + * | | |(14) SPROM is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1. + * | | |(15) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1. + * | | |(16) Invalid operations (except for chip erase) with ICE connection if SBLOCK is not 0x5A + * | | |(17) Read any content of boot loader with ICE connection + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7] |ALLONE |Flash All-one Verification Flag + * | | |This bit is set by hardware if all of flash bits are 1, and clear if flash bits are not all 1 after "Run Flash All-One Verification" complete; this bit also can be clear by writing 1 + * | | |0 = All of flash bits are 1 after "Run Flash All-One Verification" complete. + * | | |1 = Flash bits are not all 1 after "Run Flash All-One Verification" complete. + * |[23:9] |VECMAP |Vector Page Mapping Address (Read Only) + * | | |All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[14:0], 9u2019h000} ~ {VECMAP[14:0], 9u2019h1FF} + * |[31] |SCODE |Security Code Active Flag + * | | |This bit is set by hardware when detecting SPROM secured code is active at flash initiation, or software writes 1 to this bit to make secured code active; this bit is clear by SPROM page erase operation. + * | | |0 = Secured code is inactive. + * | | |1 = Secured code is active. + * @var FMC_T::CYCCTL + * Offset: 0x4C Flash Access Cycle Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |CYCLE |Flash Access Cycle Control (Write Protect) + * | | |0001 = CPU access with one wait cycle if cache miss; flash access cycle is 1;. + * | | |The HCLK working frequency range range is<27MHz + * | | |0010 = CPU access with two wait cycles if cache miss; flash access cycle is 2;. + * | | | The optimized HCLK working frequency range is 27~54 MHz + * | | |0011 = CPU access with three wait cycles if cache miss; flash access cycle is 3;. + * | | |The optimized HCLK working frequency range is 54~81MHz + * | | |0100 = CPU access with four wait cycles if cache miss; flash access cycle is 4;. + * | | | The optimized HCLK working frequency range is81~108MHz + * | | |0101 = CPU access with five wait cycles if cache miss; flash access cycle is 5;. + * | | |The optimized HCLK working frequency range is 108~135MHz + * | | |0110 = CPU access with six wait cycles if cache miss; flash access cycle is 6;. + * | | | The optimized HCLK working frequency range is 135~162MHz + * | | |0111 = CPU access with seven wait cycles if cache miss; flash access cycle is 7;. + * | | | The optimized HCLK working frequency range is 162~192MHz + * | | |1000 = CPU access with eight wait cycles if cache miss; flash access cycle is 8;. + * | | |The optimized HCLK working frequency range is >192MHz + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var FMC_T::KPKEY0 + * Offset: 0x50 KPROM KEY0 Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KPKEY0 |KPROM KEY0 Data (Write Only) + * | | |Write KPKEY0 data to this register before KEY Comparison operation. + * @var FMC_T::KPKEY1 + * Offset: 0x54 KPROM KEY1 Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KPKEY1 |KPROM KEY1 Data (Write Only) + * | | |Write KPKEY1 data to this register before KEY Comparison operation. + * @var FMC_T::KPKEY2 + * Offset: 0x58 KPROM KEY2 Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KPKEY2 |KPROM KEY2 Data (Write Only) + * | | |Write KPKEY2 data to this register before KEY Comparison operation. + * @var FMC_T::KPKEYTRG + * Offset: 0x5C KPROM KEY Comparison Trigger Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |KPKEYGO |KPROM KEY Comparison Start Trigger (Write Protection) + * | | |Write 1 to start KEY comparison operation and this bit will be cleared to 0 by hardware automatically when KEY comparison operation is finished + * | | |This trigger operation is valid while FORBID (FMC_KPKEYSTS [3]) is 0. + * | | |0 = KEY comparison operation is finished. + * | | |1 = KEY comparison is progressed. + * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register. + * |[1] |TCEN |Timeout Counting Enable (Write Protection) + * | | |0 = Timeout counting is disabled. + * | | |1 = Timeout counting is enabled if input key is matched after key comparison finish. + * | | |10 minutes is at least for timeout, and average is about 20 minutes. + * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register. + * @var FMC_T::KPKEYSTS + * Offset: 0x60 KPROM KEY Comparison Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |KEYBUSY |KEY Comparison Busy (Read Only) + * | | |0 = KEY comparison is finished. + * | | |1 = KEY comparison is busy. + * |[1] |KEYLOCK |KEY LOCK Flag + * | | |This bit is set to 1 if KEYMATCH (FMC_KPKEYSTS [2]) is 0 and cleared to 0 if KEYMATCH is 1 in Security Key protection + * | | |After Mass Erase operation, users must reset or power on /off to clear this bit to 0 + * | | |This bit also can be set to 1 while + * | | | - CPU write 1 to KEYLOCK(FMC_KPKEYSTS[1]) or + * | | | - KEYFLAG(FMC_KPKEYSTS[4]) is 1 at power-on or reset or + * | | | - KEYENROM is programmed a non-0xFF value or + * | | | - Timeout event or + * | | | - FORBID(FMC_KPKEYSTS[3]) is 1 + * | | |0 = KPROM, LDROM and APROM (not include Data Flash) is not in write protection. + * | | |1 = KPROM, LDROM and APROM (not include Data Flash) is in write protection. + * | | |SPROM write protect is depended on SPFLAG. + * | | |CONFIG write protect is depended on CFGFLAG + * |[2] |KEYMATCH |KEY Match Flag (Read Only) + * | | |This bit is set to 1 after KEY comparison complete if the KEY0, KEY1 and KEY2 are matched with the 96-bit security keys in KPROM; and cleared to 0 if KEYs are unmatched + * | | |This bit is also cleared to 0 while + * | | | - CPU writing 1 to KEYLOCK(FMC_KPKEYSTS[1]) or + * | | | - Timeout event or + * | | | - KPROM is erased or + * | | | - KEYENROM is programmed to a non-0xFF value. + * | | | - Chip is in power down mode. + * | | |0 = KEY0, KEY1, and KEY2 are unmatched with the KPROM setting. + * | | |1 = KEY0, KEY1, and KEY2 are matched with the KPROM setting. + * |[3] |FORBID |KEY Comparison Forbidden Flag (Read Only) + * | | |This bit is set to 1 when KPKECNT(FMC_KPKEY0[4:0]) is more than KPKEMAX (FMC_KPKEY0[12:8]) or KPCNT (FMC_KPCNT [2:0]) is more than KPMAX (FMC_KPCNT [10:8]). + * | | |0 = KEY comparison is not forbidden. + * | | |1 = KEY comparison is forbidden, KEYGO (FMC_KEYTRG [0]) cannot trigger. + * |[4] |KEYFLAG |KEY Protection Enabled Flag (Read Only) + * | | |This bit is set while the KEYENROM [7:0] is not 0xFF at power-on or reset + * | | |This bit is cleared to 0 by hardware while KPROM is erased + * | | |This bit is set to 1 by hardware while KEYENROM is programmed to a non-0xFF value. + * | | |0 = Security Key protection is disabled. + * | | |1 = Security Key protection is enabled. + * |[5] |CFGFLAG |CONFIG Write-protection Enabled Flag (Read Only) + * | | |This bit is set while the KEYENROM [0] is 0 at power-on or reset + * | | |This bit is cleared to 0 by hardware while KPROM is erased + * | | |This bit is set to 1 by hardware while KEYENROM[0] is programmed to 0. + * | | |0 = CONFIG write-protection is disabled. + * | | |1 = CONFIG write-protection is enabled. + * |[6] |SPFLAG |SPROM Write-protection Enabled Flag (Read Only) + * | | |This bit is set while the KEYENROM [1] is 0 at power-on or reset + * | | |This bit is cleared to 0 by hardware while KPROM is erased + * | | |This bit is set to 1 by hardware while KEYENROM[1] is programmed to 0. + * | | |0 = SPROM write-protection is disabled. + * | | |1 = SPROM write-protection is enabled. + * @var FMC_T::KPKEYCNT + * Offset: 0x64 KPROM KEY-Unmatched Counting Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |KPKECNT |Error Key Entry Counter at Each Power-on (Read Only) + * | | |KPKECNT is increased when entry keys is wrong in Security Key protection + * | | |KPKECNT is cleared to 0 if key comparison is matched or system power-on. + * |[13:8] |KPKEMAX |Maximum Number for Error Key Entry at Each Power-on (Read Only) + * | | |KPKEMAX is the maximum error key entry number at each power-on + * | | |When KPKEMAXROM of KPROM is erased or programmed, KPKEMAX will also be updated + * | | |KPKEMAX is used to limit KPKECNT(FMC_KPKEY0[5:0]) maximum counting + * | | |The FORBID (FMC_KPKEYSTS [3]) will be set to 1 when KPKECNT is more than KPKEMAX. + * @var FMC_T::KPCNT + * Offset: 0x68 KPROM KEY-Unmatched Power-On Counting Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |KPCNT |Power-on Counter for Error Key Entry(Read Only) + * | | |KPCNT is the power-on counting for error key entry in Security Key protection + * | | |KPCNT is cleared to 0 if key comparison is matched. + * |[11:8] |KPMAX |Power-on Maximum Number for Error Key Entry (Read Only) + * | | |KPMAX is the power-on maximum number for error key entry + * | | |When KPMAXROM of KPROM is erased or programmed, KPMAX will also be updated + * | | |KPMAX is used to limit KPCNT (FMC_KPCNT [3:0]) maximum counting + * | | |The FORBID(FMC_KPKEYSTS[3]) will be set to 1 when KPCNT is more than KPMAX + * @var FMC_T::MPDAT0 + * Offset: 0x80 ISP Data0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPDAT0 |ISP Data 0 + * | | |This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data + * @var FMC_T::MPDAT1 + * Offset: 0x84 ISP Data1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPDAT1 |ISP Data 1 + * | | |This register is the second 32-bit data for 64-bit/multi-word programming. + * @var FMC_T::MPDAT2 + * Offset: 0x88 ISP Data2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPDAT2 |ISP Data 2 + * | | |This register is the third 32-bit data for multi-word programming. + * @var FMC_T::MPDAT3 + * Offset: 0x8C ISP Data3 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPDAT3 |ISP Data 3 + * | | |This register is the fourth 32-bit data for multi-word programming. + * @var FMC_T::MPSTS + * Offset: 0xC0 ISP Multi-Program Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MPBUSY |ISP Multi-word Program Busy Flag (Read Only) + * | | |Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished. + * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]). + * | | |0 = ISP Multi-Word program operation is finished. + * | | |1 = ISP Multi-Word program operation is progressed. + * |[1] |PPGO |ISP Multi-program Status (Read Only) + * | | |0 = ISP multi-word program operation is not active. + * | | |1 = ISP multi-word program operation is in progress. + * |[2] |ISPFF |ISP Fail Flag (Read Only) + * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6] + * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: + * | | |(1) APROM writes to itself if APUEN is set to 0. + * | | |(2) LDROM writes to itself if LDUEN is set to 0. + * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0. + * | | |(4) SPROM is erased/programmed if SPUEN is set to 0 + * | | |(5) SPROM is programmed at SPROM secured mode. + * | | |(6) Page Erase command at LOCK mode with ICE connection + * | | |(7) Erase or Program command at brown-out detected + * | | |(8) Destination address is illegal, such as over an available range. + * | | |(9) Invalid ISP commands + * | | |(10) Vector address is mapping to SPROM region. + * |[4] |D0 |ISP DATA 0 Flag (Read Only) + * | | |This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to flash complete. + * | | |0 = FMC_MPDAT0 register is empty, or program to flash complete. + * | | |1 = FMC_MPDAT0 register has been written, and not program to flash complete. + * |[5] |D1 |ISP DATA 1 Flag (Read Only) + * | | |This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to flash complete. + * | | |0 = FMC_MPDAT1 register is empty, or program to flash complete. + * | | |1 = FMC_MPDAT1 register has been written, and not program to flash complete. + * |[6] |D2 |ISP DATA 2 Flag (Read Only) + * | | |This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to flash complete. + * | | |0 = FMC_MPDAT2 register is empty, or program to flash complete. + * | | |1 = FMC_MPDAT2 register has been written, and not program to flash complete. + * |[7] |D3 |ISP DATA 3 Flag (Read Only) + * | | |This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to flash complete. + * | | |0 = FMC_MPDAT3 register is empty, or program to flash complete. + * | | |1 = FMC_MPDAT3 register has been written, and not program to flash complete. + * @var FMC_T::MPADDR + * Offset: 0xC4 ISP Multi-Program Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |MPADDR |ISP Multi-word Program Address + * | | |MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1. + * | | |MPADDR will keep the final ISP address when ISP multi-word program is complete. + */ + __IO uint32_t ISPCTL; /*!< [0x0000] ISP Control Register */ + __IO uint32_t ISPADDR; /*!< [0x0004] ISP Address Register */ + __IO uint32_t ISPDAT; /*!< [0x0008] ISP Data Register */ + __IO uint32_t ISPCMD; /*!< [0x000c] ISP Command Register */ + __IO uint32_t ISPTRG; /*!< [0x0010] ISP Trigger Control Register */ + __I uint32_t DFBA; /*!< [0x0014] Data Flash Base Address */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[10]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t ISPSTS; /*!< [0x0040] ISP Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CYCCTL; /*!< [0x004c] Flash Access Cycle Control Register */ + __O uint32_t KPKEY0; /*!< [0x0050] KPROM KEY0 Data Register */ + __O uint32_t KPKEY1; /*!< [0x0054] KPROM KEY1 Data Register */ + __O uint32_t KPKEY2; /*!< [0x0058] KPROM KEY2 Data Register */ + __IO uint32_t KPKEYTRG; /*!< [0x005c] KPROM KEY Comparison Trigger Control Register */ + __IO uint32_t KPKEYSTS; /*!< [0x0060] KPROM KEY Comparison Status Register */ + __I uint32_t KPKEYCNT; /*!< [0x0064] KPROM KEY-Unmatched Counting Register */ + __I uint32_t KPCNT; /*!< [0x0068] KPROM KEY-Unmatched Power-On Counting Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[5]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t MPDAT0; /*!< [0x0080] ISP Data0 Register */ + __IO uint32_t MPDAT1; /*!< [0x0084] ISP Data1 Register */ + __IO uint32_t MPDAT2; /*!< [0x0088] ISP Data2 Register */ + __IO uint32_t MPDAT3; /*!< [0x008c] ISP Data3 Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[12]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t MPSTS; /*!< [0x00c0] ISP Multi-Program Status Register */ + __I uint32_t MPADDR; /*!< [0x00c4] ISP Multi-Program Address Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE4[2]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t XOMR0STS; /*!< [0x00d0] XOM Region 0 Status Register */ + __I uint32_t XOMR1STS; /*!< [0x00d4] XOM Region 1 Status Register */ + __I uint32_t XOMR2STS; /*!< [0x00d8] XOM Region 2 Status Register */ + __I uint32_t XOMR3STS; /*!< [0x00dc] XOM Region 3 Status Register */ + __I uint32_t XOMSTS; /*!< [0x00e0] XOM Status Register */ + +} FMC_T; + +/** + @addtogroup FMC_CONST FMC Bit Field Definition + Constant Definitions for FMC Controller +@{ */ + +#define FMC_ISPCTL_ISPEN_Pos (0) /*!< FMC_T::ISPCTL: ISPEN Position */ +#define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) /*!< FMC_T::ISPCTL: ISPEN Mask */ + +#define FMC_ISPCTL_BS_Pos (1) /*!< FMC_T::ISPCTL: BS Position */ +#define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) /*!< FMC_T::ISPCTL: BS Mask */ + +#define FMC_ISPCTL_SPUEN_Pos (2) /*!< FMC_T::ISPCTL: SPUEN Position */ +#define FMC_ISPCTL_SPUEN_Msk (0x1ul << FMC_ISPCTL_SPUEN_Pos) /*!< FMC_T::ISPCTL: SPUEN Mask */ + +#define FMC_ISPCTL_APUEN_Pos (3) /*!< FMC_T::ISPCTL: APUEN Position */ +#define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) /*!< FMC_T::ISPCTL: APUEN Mask */ + +#define FMC_ISPCTL_CFGUEN_Pos (4) /*!< FMC_T::ISPCTL: CFGUEN Position */ +#define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) /*!< FMC_T::ISPCTL: CFGUEN Mask */ + +#define FMC_ISPCTL_LDUEN_Pos (5) /*!< FMC_T::ISPCTL: LDUEN Position */ +#define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) /*!< FMC_T::ISPCTL: LDUEN Mask */ + +#define FMC_ISPCTL_ISPFF_Pos (6) /*!< FMC_T::ISPCTL: ISPFF Position */ +#define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) /*!< FMC_T::ISPCTL: ISPFF Mask */ + +#define FMC_ISPCTL_BL_Pos (16) /*!< FMC_T::ISPCTL: BL Position */ +#define FMC_ISPCTL_BL_Msk (0x1ul << FMC_ISPCTL_BL_Pos) /*!< FMC_T::ISPCTL: BL Mask */ + +#define FMC_ISPADDR_ISPADDR_Pos (0) /*!< FMC_T::ISPADDR: ISPADDR Position */ +#define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) /*!< FMC_T::ISPADDR: ISPADDR Mask */ + +#define FMC_ISPDAT_ISPDAT_Pos (0) /*!< FMC_T::ISPDAT: ISPDAT Position */ +#define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) /*!< FMC_T::ISPDAT: ISPDAT Mask */ + +#define FMC_ISPCMD_CMD_Pos (0) /*!< FMC_T::ISPCMD: CMD Position */ +#define FMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos) /*!< FMC_T::ISPCMD: CMD Mask */ + +#define FMC_ISPTRG_ISPGO_Pos (0) /*!< FMC_T::ISPTRG: ISPGO Position */ +#define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) /*!< FMC_T::ISPTRG: ISPGO Mask */ + +#define FMC_DFBA_DFBA_Pos (0) /*!< FMC_T::DFBA: DFBA Position */ +#define FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos) /*!< FMC_T::DFBA: DFBA Mask */ + +#define FMC_ISPSTS_ISPBUSY_Pos (0) /*!< FMC_T::ISPSTS: ISPBUSY Position */ +#define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) /*!< FMC_T::ISPSTS: ISPBUSY Mask */ + +#define FMC_ISPSTS_CBS_Pos (1) /*!< FMC_T::ISPSTS: CBS Position */ +#define FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos) /*!< FMC_T::ISPSTS: CBS Mask */ + +#define FMC_ISPSTS_MBS_Pos (3) /*!< FMC_T::ISPSTS: MBS Position */ +#define FMC_ISPSTS_MBS_Msk (0x1ul << FMC_ISPSTS_MBS_Pos) /*!< FMC_T::ISPSTS: MBS Mask */ + +#define FMC_ISPSTS_FCYCDIS_Pos (4) /*!< FMC_T::ISPSTS: FCYCDIS Position */ +#define FMC_ISPSTS_FCYCDIS_Msk (0x1ul << FMC_ISPSTS_FCYCDIS_Pos) /*!< FMC_T::ISPSTS: FCYCDIS Mask */ + +#define FMC_ISPSTS_PGFF_Pos (5) /*!< FMC_T::ISPSTS: PGFF Position */ +#define FMC_ISPSTS_PGFF_Msk (0x1ul << FMC_ISPSTS_PGFF_Pos) /*!< FMC_T::ISPSTS: PGFF Mask */ + +#define FMC_ISPSTS_ISPFF_Pos (6) /*!< FMC_T::ISPSTS: ISPFF Position */ +#define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) /*!< FMC_T::ISPSTS: ISPFF Mask */ + +#define FMC_ISPSTS_ALLONE_Pos (7) /*!< FMC_T::ISPSTS: ALLONE Position */ +#define FMC_ISPSTS_ALLONE_Msk (0x1ul << FMC_ISPSTS_ALLONE_Pos) /*!< FMC_T::ISPSTS: ALLONE Mask */ + +#define FMC_ISPSTS_VECMAP_Pos (9) /*!< FMC_T::ISPSTS: VECMAP Position */ +#define FMC_ISPSTS_VECMAP_Msk (0x7ffful << FMC_ISPSTS_VECMAP_Pos) /*!< FMC_T::ISPSTS: VECMAP Mask */ + +#define FMC_ISPSTS_SCODE_Pos (31) /*!< FMC_T::ISPSTS: SCODE Position */ +#define FMC_ISPSTS_SCODE_Msk (0x1ul << FMC_ISPSTS_SCODE_Pos) /*!< FMC_T::ISPSTS: SCODE Mask */ + +#define FMC_CYCCTL_CYCLE_Pos (0) /*!< FMC_T::CYCCTL: CYCLE Position */ +#define FMC_CYCCTL_CYCLE_Msk (0xful << FMC_CYCCTL_CYCLE_Pos) /*!< FMC_T::CYCCTL: CYCLE Mask */ + +#define FMC_KPKEY0_KPKEY0_Pos (0) /*!< FMC_T::KPKEY0: KPKEY0 Position */ +#define FMC_KPKEY0_KPKEY0_Msk (0xfffffffful << FMC_KPKEY0_KPKEY0_Pos) /*!< FMC_T::KPKEY0: KPKEY0 Mask */ + +#define FMC_KPKEY1_KPKEY1_Pos (0) /*!< FMC_T::KPKEY1: KPKEY1 Position */ +#define FMC_KPKEY1_KPKEY1_Msk (0xfffffffful << FMC_KPKEY1_KPKEY1_Pos) /*!< FMC_T::KPKEY1: KPKEY1 Mask */ + +#define FMC_KPKEY2_KPKEY2_Pos (0) /*!< FMC_T::KPKEY2: KPKEY2 Position */ +#define FMC_KPKEY2_KPKEY2_Msk (0xfffffffful << FMC_KPKEY2_KPKEY2_Pos) /*!< FMC_T::KPKEY2: KPKEY2 Mask */ + +#define FMC_KPKEYTRG_KPKEYGO_Pos (0) /*!< FMC_T::KPKEYTRG: KPKEYGO Position */ +#define FMC_KPKEYTRG_KPKEYGO_Msk (0x1ul << FMC_KPKEYTRG_KPKEYGO_Pos) /*!< FMC_T::KPKEYTRG: KPKEYGO Mask */ + +#define FMC_KPKEYTRG_TCEN_Pos (1) /*!< FMC_T::KPKEYTRG: TCEN Position */ +#define FMC_KPKEYTRG_TCEN_Msk (0x1ul << FMC_KPKEYTRG_TCEN_Pos) /*!< FMC_T::KPKEYTRG: TCEN Mask */ + +#define FMC_KPKEYSTS_KEYBUSY_Pos (0) /*!< FMC_T::KPKEYSTS: KEYBUSY Position */ +#define FMC_KPKEYSTS_KEYBUSY_Msk (0x1ul << FMC_KPKEYSTS_KEYBUSY_Pos) /*!< FMC_T::KPKEYSTS: KEYBUSY Mask */ + +#define FMC_KPKEYSTS_KEYLOCK_Pos (1) /*!< FMC_T::KPKEYSTS: KEYLOCK Position */ +#define FMC_KPKEYSTS_KEYLOCK_Msk (0x1ul << FMC_KPKEYSTS_KEYLOCK_Pos) /*!< FMC_T::KPKEYSTS: KEYLOCK Mask */ + +#define FMC_KPKEYSTS_KEYMATCH_Pos (2) /*!< FMC_T::KPKEYSTS: KEYMATCH Position */ +#define FMC_KPKEYSTS_KEYMATCH_Msk (0x1ul << FMC_KPKEYSTS_KEYMATCH_Pos) /*!< FMC_T::KPKEYSTS: KEYMATCH Mask */ + +#define FMC_KPKEYSTS_FORBID_Pos (3) /*!< FMC_T::KPKEYSTS: FORBID Position */ +#define FMC_KPKEYSTS_FORBID_Msk (0x1ul << FMC_KPKEYSTS_FORBID_Pos) /*!< FMC_T::KPKEYSTS: FORBID Mask */ + +#define FMC_KPKEYSTS_KEYFLAG_Pos (4) /*!< FMC_T::KPKEYSTS: KEYFLAG Position */ +#define FMC_KPKEYSTS_KEYFLAG_Msk (0x1ul << FMC_KPKEYSTS_KEYFLAG_Pos) /*!< FMC_T::KPKEYSTS: KEYFLAG Mask */ + +#define FMC_KPKEYSTS_CFGFLAG_Pos (5) /*!< FMC_T::KPKEYSTS: CFGFLAG Position */ +#define FMC_KPKEYSTS_CFGFLAG_Msk (0x1ul << FMC_KPKEYSTS_CFGFLAG_Pos) /*!< FMC_T::KPKEYSTS: CFGFLAG Mask */ + +#define FMC_KPKEYSTS_SPFLAG_Pos (6) /*!< FMC_T::KPKEYSTS: SPFLAG Position */ +#define FMC_KPKEYSTS_SPFLAG_Msk (0x1ul << FMC_KPKEYSTS_SPFLAG_Pos) /*!< FMC_T::KPKEYSTS: SPFLAG Mask */ + +#define FMC_KPKEYCNT_KPKECNT_Pos (0) /*!< FMC_T::KPKEYCNT: KPKECNT Position */ +#define FMC_KPKEYCNT_KPKECNT_Msk (0x3ful << FMC_KPKEYCNT_KPKECNT_Pos) /*!< FMC_T::KPKEYCNT: KPKECNT Mask */ + +#define FMC_KPKEYCNT_KPKEMAX_Pos (8) /*!< FMC_T::KPKEYCNT: KPKEMAX Position */ +#define FMC_KPKEYCNT_KPKEMAX_Msk (0x3ful << FMC_KPKEYCNT_KPKEMAX_Pos) /*!< FMC_T::KPKEYCNT: KPKEMAX Mask */ + +#define FMC_KPCNT_KPCNT_Pos (0) /*!< FMC_T::KPCNT: KPCNT Position */ +#define FMC_KPCNT_KPCNT_Msk (0xful << FMC_KPCNT_KPCNT_Pos) /*!< FMC_T::KPCNT: KPCNT Mask */ + +#define FMC_KPCNT_KPMAX_Pos (8) /*!< FMC_T::KPCNT: KPMAX Position */ +#define FMC_KPCNT_KPMAX_Msk (0xful << FMC_KPCNT_KPMAX_Pos) /*!< FMC_T::KPCNT: KPMAX Mask */ + +#define FMC_MPDAT0_ISPDAT0_Pos (0) /*!< FMC_T::MPDAT0: ISPDAT0 Position */ +#define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos) /*!< FMC_T::MPDAT0: ISPDAT0 Mask */ + +#define FMC_MPDAT1_ISPDAT1_Pos (0) /*!< FMC_T::MPDAT1: ISPDAT1 Position */ +#define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos) /*!< FMC_T::MPDAT1: ISPDAT1 Mask */ + +#define FMC_MPDAT2_ISPDAT2_Pos (0) /*!< FMC_T::MPDAT2: ISPDAT2 Position */ +#define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos) /*!< FMC_T::MPDAT2: ISPDAT2 Mask */ + +#define FMC_MPDAT3_ISPDAT3_Pos (0) /*!< FMC_T::MPDAT3: ISPDAT3 Position */ +#define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos) /*!< FMC_T::MPDAT3: ISPDAT3 Mask */ + +#define FMC_MPSTS_MPBUSY_Pos (0) /*!< FMC_T::MPSTS: MPBUSY Position */ +#define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos) /*!< FMC_T::MPSTS: MPBUSY Mask */ + +#define FMC_MPSTS_PPGO_Pos (1) /*!< FMC_T::MPSTS: PPGO Position */ +#define FMC_MPSTS_PPGO_Msk (0x1ul << FMC_MPSTS_PPGO_Pos) /*!< FMC_T::MPSTS: PPGO Mask */ + +#define FMC_MPSTS_ISPFF_Pos (2) /*!< FMC_T::MPSTS: ISPFF Position */ +#define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos) /*!< FMC_T::MPSTS: ISPFF Mask */ + +#define FMC_MPSTS_D0_Pos (4) /*!< FMC_T::MPSTS: D0 Position */ +#define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos) /*!< FMC_T::MPSTS: D0 Mask */ + +#define FMC_MPSTS_D1_Pos (5) /*!< FMC_T::MPSTS: D1 Position */ +#define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos) /*!< FMC_T::MPSTS: D1 Mask */ + +#define FMC_MPSTS_D2_Pos (6) /*!< FMC_T::MPSTS: D2 Position */ +#define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos) /*!< FMC_T::MPSTS: D2 Mask */ + +#define FMC_MPSTS_D3_Pos (7) /*!< FMC_T::MPSTS: D3 Position */ +#define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos) /*!< FMC_T::MPSTS: D3 Mask */ + +#define FMC_MPADDR_MPADDR_Pos (0) /*!< FMC_T::MPADDR: MPADDR Position */ +#define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) /*!< FMC_T::MPADDR: MPADDR Mask */ + +#define FMC_XOMR0STS_SIZE_Pos (0) /*!< FMC_T::XOMR0STS: SIZE Position */ +#define FMC_XOMR0STS_SIZE_Msk (0xfful << FMC_XOMR0STS_SIZE_Pos) /*!< FMC_T::XOMR0STS: SIZE Mask */ + +#define FMC_XOMR0STS_BASE_Pos (8) /*!< FMC_T::XOMR0STS: BASE Position */ +#define FMC_XOMR0STS_BASE_Msk (0xfffffful << FMC_XOMR0STS_BASE_Pos) /*!< FMC_T::XOMR0STS: BASE Mask */ + +#define FMC_XOMR1STS_SIZE_Pos (0) /*!< FMC_T::XOMR1STS: SIZE Position */ +#define FMC_XOMR1STS_SIZE_Msk (0xfful << FMC_XOMR1STS_SIZE_Pos) /*!< FMC_T::XOMR1STS: SIZE Mask */ + +#define FMC_XOMR1STS_BASE_Pos (8) /*!< FMC_T::XOMR1STS: BASE Position */ +#define FMC_XOMR1STS_BASE_Msk (0xfffffful << FMC_XOMR1STS_BASE_Pos) /*!< FMC_T::XOMR1STS: BASE Mask */ + +#define FMC_XOMR2STS_SIZE_Pos (0) /*!< FMC_T::XOMR2STS: SIZE Position */ +#define FMC_XOMR2STS_SIZE_Msk (0xfful << FMC_XOMR2STS_SIZE_Pos) /*!< FMC_T::XOMR2STS: SIZE Mask */ + +#define FMC_XOMR2STS_BASE_Pos (8) /*!< FMC_T::XOMR2STS: BASE Position */ +#define FMC_XOMR2STS_BASE_Msk (0xfffffful << FMC_XOM20STS_BASE_Pos) /*!< FMC_T::XOMR2STS: BASE Mask */ + +#define FMC_XOMR3STS_SIZE_Pos (0) /*!< FMC_T::XOMR3STS: SIZE Position */ +#define FMC_XOMR3STS_SIZE_Msk (0xfful << FMC_XOMR3STS_SIZE_Pos) /*!< FMC_T::XOMR3STS: SIZE Mask */ + +#define FMC_XOMR3STS_BASE_Pos (8) /*!< FMC_T::XOMR3STS: BASE Position */ +#define FMC_XOMR3STS_BASE_Msk (0xfffffful << FMC_XOMR3STS_BASE_Pos) /*!< FMC_T::XOMR3STS: BASE Mask */ + +#define FMC_XOMSTS_XOMR0ON_Pos (0) /*!< FMC_T::XOMSTS: XOMR0ON Position */ +#define FMC_XOMSTS_XOMR0ON_Msk (0x1ul << FMC_XOMSTS_XOMR0ON_Pos) /*!< FMC_T::XOMSTS: XOMR0ON Mask */ + +#define FMC_XOMSTS_XOMR1ON_Pos (1) /*!< FMC_T::XOMSTS: XOMR1ON Position */ +#define FMC_XOMSTS_XOMR1ON_Msk (0x1ul << FMC_XOMSTS_XOMR1ON_Pos) /*!< FMC_T::XOMSTS: XOMR1ON Mask */ + +#define FMC_XOMSTS_XOMR2ON_Pos (2) /*!< FMC_T::XOMSTS: XOMR2ON Position */ +#define FMC_XOMSTS_XOMR2ON_Msk (0x1ul << FMC_XOMSTS_XOMR2ON_Pos) /*!< FMC_T::XOMSTS: XOMR2ON Mask */ + +#define FMC_XOMSTS_XOMR3ON_Pos (3) /*!< FMC_T::XOMSTS: XOMR3ON Position */ +#define FMC_XOMSTS_XOMR3ON_Msk (0x1ul << FMC_XOMSTS_XOMR3ON_Pos) /*!< FMC_T::XOMSTS: XOMR3ON Mask */ + +#define FMC_XOMSTS_XOMPEF_Pos (4) /*!< FMC_T::XOMSTS: XOMPEF Position */ +#define FMC_XOMSTS_XOMPEF_Msk (0x1ul << FMC_XOMSTS_XOMPEF_Pos) /*!< FMC_T::XOMSTS: XOMPEF Mask */ + +/**@}*/ /* FMC_CONST */ +/**@}*/ /* end of FMC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __FMC_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/gpio_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/gpio_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..9876f972845d0e3a30deb32582c91db675e66e05 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/gpio_reg.h @@ -0,0 +1,936 @@ +/**************************************************************************//** + * @file gpio_reg.h + * @version V1.00 + * @brief GPIO register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __GPIO_REG_H__ +#define __GPIO_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup GPIO General Purpose Input/Output Controller(GPIO) + Memory Mapped Structure for GPIO Controller +@{ */ + + +typedef struct +{ + + /** + * @var GPIO_T::MODE + * Offset: 0x00/0x40/0x80/0xC0/0x100/0x140/0x180/0x1C0 Port A-H I/O Mode Control + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2n+1:2n]|MODEn |Port A-H I/O Pin[n] Mode Control + * | | |Determine each I/O mode of Px.n pins. + * | | |00 = Px.n is in Input mode. + * | | |01 = Px.n is in Push-pull Output mode. + * | | |10 = Px.n is in Open-drain Output mode. + * | | |11 = Px.n is in Quasi-bidirectional mode. + * | | |Note1: The initial value of this field is defined by CIOINI (CONFIG0 [10]). + * | | |If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on. + * | | |If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. + * | | |Note2: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var GPIO_T::DINOFF + * Offset: 0x04/0x44/0x84/0xC4/0x104/0x144/0x184/0x1C4 Port A-H Digital Input Path Disable Control + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n+16] |DINOFFn |Port A-H Pin[n] Digital Input Path Disable Control + * | | |Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. + * | | |If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. + * | | |0 = Px.n digital input path Enabled. + * | | |1 = Px.n digital input path Disabled (digital input tied to low). + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var GPIO_T::DOUT + * Offset: 0x08/0x48/0x88/0xC8/0x108/0x148/0x188/0x1C8 Port A-H Data Output Value + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |DOUTn |Port A-H Pin[n] Output Value + * | | |Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. + * | | |0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. + * | | |1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var GPIO_T::DATMSK + * Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C/0x18C/0x1CC Port A-H Data Output Write Mask + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |DATMSKn |Port A-H Pin[n] Data Output Write Mask + * | | |These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. + * | | |When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. + * | | |If the write signal is masked, writing data to the protect bit is ignored. + * | | |0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. + * | | |1 = Corresponding DOUT (Px_DOUT[n]) bit protected. + * | | |Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[n]) bit. + * | | |Note2: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var GPIO_T::PIN + * Offset: 0x10/0x50/0x90/0xD0/0x110/0x150/0x190/0x1D0 Port A-H Pin Value + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |PINn |Port A-H Pin[n] Pin Value + * | | |Each bit of the register reflects the actual status of the respective Px.n pin. + * | | |If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var GPIO_T::DBEN + * Offset: 0x14/0x54/0x94/0xD4/0x114/0x154/0x194/0x1D4 Port A-H De-Bounce Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |DBENn |Port A-H Pin[n] Input Signal De-Bounce Enable Bit + * | | |The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. + * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. + * | | |The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). + * | | |0 = Px.n de-bounce function Disabled. + * | | |1 = Px.n de-bounce function Enabled. + * | | |The de-bounce function is valid only for edge triggered interrupt. + * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var GPIO_T::INTTYPE + * Offset: 0x18/0x58/0x98/0xD8/0x118/0x158/0x198/0x1D8 Port A-H Interrupt Trigger Type Control + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |TYPEn |Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control + * | | |TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. + * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. + * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. + * | | |0 = Edge trigger interrupt. + * | | |1 = Level trigger interrupt. + * | | |If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). + * | | |If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. + * | | |The de-bounce function is valid only for edge triggered interrupt. + * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var GPIO_T::INTEN + * Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C/0x19C/0x1DC Port A-H Interrupt Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |FLIENn |Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit + * | | |The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. + * | | |Set bit to 1 also enable the pin wake-up function. + * | | |When setting the FLIEN (Px_INTEN[n]) bit to 1 : + * | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. + * | | |If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. + * | | |0 = Px.n level low or high to low interrupt Disabled. + * | | |1 = Px.n level low or high to low interrupt Enabled. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[n+16] |RHIENn |Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit + * | | |The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin + * | | |Set bit to 1 also enable the pin wake-up function. + * | | |When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : + * | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. + * | | |If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. + * | | |0 = Px.n level high or low to high interrupt Disabled. + * | | |1 = Px.n level high or low to high interrupt Enabled. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var GPIO_T::INTSRC + * Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160/0x1A0/0x1E0 Port A-H Interrupt Source Flag + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |INTSRCn |Port A-H Pin[n] Interrupt Source Flag + * | | |Write Operation : + * | | |0 = No action. + * | | |1 = Clear the corresponding pending interrupt. + * | | |Read Operation : + * | | |0 = No interrupt at Px.n. + * | | |1 = Px.n generates an interrupt. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var GPIO_T::SMTEN + * Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164/0x1A4/0x1E4 Port A-H Input Schmitt Trigger Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |SMTENn |Port A-H Pin[n] Input Schmitt Trigger Enable Bit + * | | |0 = Px.n input Schmitt trigger function Disabled. + * | | |1 = Px.n input Schmitt trigger function Enabled. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var GPIO_T::SLEWCTL + * Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168/0x1A8/0x1E8 Port A-H High Slew Rate Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2n+1:2n]|HSRENn |Port A-H Pin[n] High Slew Rate Control + * | | |00 = Px.n output with normal slew rate mode (maximum 40 MHz at 2.7V). + * | | |01 = Px.n output with high slew rate mode (maximum 80 MHz at 2.7V). + * | | |10 = Px.n output with fast slew rate mode (maximum 100 MHz at 2.7V. + * | | |11 = Reserved. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var GPIO_T::PUSEL + * Offset: 0x30/0x70/0xB0/0xF0/0x130/0x170/0x1B0/0x1F0 Port A-H Pull-up and Pull-down Selection Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2n+1:2n]|PUSELn |Port A-H Pin[n] Pull-up and Pull-down Enable Register + * | | |Determine each I/O Pull-up/pull-down of Px.n pins. + * | | |00 = Px.n pull-up and pull-up disable. + * | | |01 = Px.n pull-up enable. + * | | |10 = Px.n pull-down enable. + * | | |11 = Reserved. + * | | |Note1: + * | | |Basically, the pull-up control and pull-down control has following behavior limitation + * | | |The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode + * | | |The independent pull-down control register only valid when MODEn set as tri-state mode + * | | |When both pull-up pull-down is set as 1 at tri-state mode, keep I/O in tri-state mode + * | | |Note2: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + */ + + __IO uint32_t MODE; /* Offset: 0x00/0x40/0x80/0xC0/0x100/0x140/0x180/0x1C0 Port A-H I/O Mode Control */ + __IO uint32_t DINOFF; /* Offset: 0x04/0x44/0x84/0xC4/0x104/0x144/0x184/0x1C4 Port A-H Digital Input Path Disable Control */ + __IO uint32_t DOUT; /* Offset: 0x08/0x48/0x88/0xC8/0x108/0x148/0x188/0x1C8 Port A-H Data Output Value */ + __IO uint32_t DATMSK; /* Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C/0x18C/0x1CC Port A-H Data Output Write Mask */ + __I uint32_t PIN; /* Offset: 0x10/0x50/0x90/0xD0/0x110/0x150/0x190/0x1D0 Port A-H Pin Value */ + __IO uint32_t DBEN; /* Offset: 0x14/0x54/0x94/0xD4/0x114/0x154/0x194/0x1D4 Port A-H De-Bounce Enable Control Register */ + __IO uint32_t INTTYPE; /* Offset: 0x18/0x58/0x98/0xD8/0x118/0x158/0x198/0x1D8 Port A-H Interrupt Trigger Type Control */ + __IO uint32_t INTEN; /* Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C/0x19C/0x1DC Port A-H Interrupt Enable Control Register */ + __IO uint32_t INTSRC; /* Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160/0x1A0/0x1E0 Port A-H Interrupt Source Flag */ + __IO uint32_t SMTEN; /* Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164/0x1A4/0x1E4 Port A-H Input Schmitt Trigger Enable Register */ + __IO uint32_t SLEWCTL; /* Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168/0x1A8/0x1E8 Port A-H High Slew Rate Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t PUSEL; /* Offset: 0x30/0x70/0xB0/0xF0/0x130/0x170/0x1B0/0x1F0 Port A-H Pull-up and Pull-down Enable Register */ + +} GPIO_T; + +typedef struct +{ + + /** + * @var GPIO_DBCTL_T::DBCTL + * Offset: 0x440 Interrupt De-bounce Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |DBCLKSEL |De-Bounce Sampling Cycle Selection + * | | |0000 = Sample interrupt input once per 1 clocks. + * | | |0001 = Sample interrupt input once per 2 clocks. + * | | |0010 = Sample interrupt input once per 4 clocks. + * | | |0011 = Sample interrupt input once per 8 clocks. + * | | |0100 = Sample interrupt input once per 16 clocks. + * | | |0101 = Sample interrupt input once per 32 clocks. + * | | |0110 = Sample interrupt input once per 64 clocks. + * | | |0111 = Sample interrupt input once per 128 clocks. + * | | |1000 = Sample interrupt input once per 256 clocks. + * | | |1001 = Sample interrupt input once per 2*256 clocks. + * | | |1010 = Sample interrupt input once per 4*256 clocks. + * | | |1011 = Sample interrupt input once per 8*256 clocks. + * | | |1100 = Sample interrupt input once per 16*256 clocks. + * | | |1101 = Sample interrupt input once per 32*256 clocks. + * | | |1110 = Sample interrupt input once per 64*256 clocks. + * | | |1111 = Sample interrupt input once per 128*256 clocks. + * |[4] |DBCLKSRC |De-Bounce Counter Clock Source Selection + * | | |0 = De-bounce counter clock source is the HCLK. + * | | |1 = De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC). + * |[5] |ICLKON |Interrupt Clock On Mode + * | | |0 = Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1. + * | | |1 = All I/O pins edge detection circuit is always active after reset. + * | | |Note: It is recommended to disable this bit to save system power if no special application concern. + */ + + __IO uint32_t DBCTL; /* Offset: 0x440 Interrupt De-bounce Control Register */ + +} GPIO_DBCTL_T; + +/** + @addtogroup GPIO_CONST GPIO Bit Field Definition + Constant Definitions for GPIO Controller +@{ */ + +#define GPIO_MODE_MODE0_Pos (0) /*!< GPIO_T::MODE: MODE0 Position */ +#define GPIO_MODE_MODE0_Msk (0x3ul << GPIO_MODE_MODE0_Pos) /*!< GPIO_T::MODE: MODE0 Mask */ + +#define GPIO_MODE_MODE1_Pos (2) /*!< GPIO_T::MODE: MODE1 Position */ +#define GPIO_MODE_MODE1_Msk (0x3ul << GPIO_MODE_MODE1_Pos) /*!< GPIO_T::MODE: MODE1 Mask */ + +#define GPIO_MODE_MODE2_Pos (4) /*!< GPIO_T::MODE: MODE2 Position */ +#define GPIO_MODE_MODE2_Msk (0x3ul << GPIO_MODE_MODE2_Pos) /*!< GPIO_T::MODE: MODE2 Mask */ + +#define GPIO_MODE_MODE3_Pos (6) /*!< GPIO_T::MODE: MODE3 Position */ +#define GPIO_MODE_MODE3_Msk (0x3ul << GPIO_MODE_MODE3_Pos) /*!< GPIO_T::MODE: MODE3 Mask */ + +#define GPIO_MODE_MODE4_Pos (8) /*!< GPIO_T::MODE: MODE4 Position */ +#define GPIO_MODE_MODE4_Msk (0x3ul << GPIO_MODE_MODE4_Pos) /*!< GPIO_T::MODE: MODE4 Mask */ + +#define GPIO_MODE_MODE5_Pos (10) /*!< GPIO_T::MODE: MODE5 Position */ +#define GPIO_MODE_MODE5_Msk (0x3ul << GPIO_MODE_MODE5_Pos) /*!< GPIO_T::MODE: MODE5 Mask */ + +#define GPIO_MODE_MODE6_Pos (12) /*!< GPIO_T::MODE: MODE6 Position */ +#define GPIO_MODE_MODE6_Msk (0x3ul << GPIO_MODE_MODE6_Pos) /*!< GPIO_T::MODE: MODE6 Mask */ + +#define GPIO_MODE_MODE7_Pos (14) /*!< GPIO_T::MODE: MODE7 Position */ +#define GPIO_MODE_MODE7_Msk (0x3ul << GPIO_MODE_MODE7_Pos) /*!< GPIO_T::MODE: MODE7 Mask */ + +#define GPIO_MODE_MODE8_Pos (16) /*!< GPIO_T::MODE: MODE8 Position */ +#define GPIO_MODE_MODE8_Msk (0x3ul << GPIO_MODE_MODE8_Pos) /*!< GPIO_T::MODE: MODE8 Mask */ + +#define GPIO_MODE_MODE9_Pos (18) /*!< GPIO_T::MODE: MODE9 Position */ +#define GPIO_MODE_MODE9_Msk (0x3ul << GPIO_MODE_MODE9_Pos) /*!< GPIO_T::MODE: MODE9 Mask */ + +#define GPIO_MODE_MODE10_Pos (20) /*!< GPIO_T::MODE: MODE10 Position */ +#define GPIO_MODE_MODE10_Msk (0x3ul << GPIO_MODE_MODE10_Pos) /*!< GPIO_T::MODE: MODE10 Mask */ + +#define GPIO_MODE_MODE11_Pos (22) /*!< GPIO_T::MODE: MODE11 Position */ +#define GPIO_MODE_MODE11_Msk (0x3ul << GPIO_MODE_MODE11_Pos) /*!< GPIO_T::MODE: MODE11 Mask */ + +#define GPIO_MODE_MODE12_Pos (24) /*!< GPIO_T::MODE: MODE12 Position */ +#define GPIO_MODE_MODE12_Msk (0x3ul << GPIO_MODE_MODE12_Pos) /*!< GPIO_T::MODE: MODE12 Mask */ + +#define GPIO_MODE_MODE13_Pos (26) /*!< GPIO_T::MODE: MODE13 Position */ +#define GPIO_MODE_MODE13_Msk (0x3ul << GPIO_MODE_MODE13_Pos) /*!< GPIO_T::MODE: MODE13 Mask */ + +#define GPIO_MODE_MODE14_Pos (28) /*!< GPIO_T::MODE: MODE14 Position */ +#define GPIO_MODE_MODE14_Msk (0x3ul << GPIO_MODE_MODE14_Pos) /*!< GPIO_T::MODE: MODE14 Mask */ + +#define GPIO_MODE_MODE15_Pos (30) /*!< GPIO_T::MODE: MODE15 Position */ +#define GPIO_MODE_MODE15_Msk (0x3ul << GPIO_MODE_MODE15_Pos) /*!< GPIO_T::MODE: MODE15 Mask */ + +#define GPIO_DINOFF_DINOFF0_Pos (16) /*!< GPIO_T::DINOFF: DINOFF0 Position */ +#define GPIO_DINOFF_DINOFF0_Msk (0x1ul << GPIO_DINOFF_DINOFF0_Pos) /*!< GPIO_T::DINOFF: DINOFF0 Mask */ + +#define GPIO_DINOFF_DINOFF1_Pos (17) /*!< GPIO_T::DINOFF: DINOFF1 Position */ +#define GPIO_DINOFF_DINOFF1_Msk (0x1ul << GPIO_DINOFF_DINOFF1_Pos) /*!< GPIO_T::DINOFF: DINOFF1 Mask */ + +#define GPIO_DINOFF_DINOFF2_Pos (18) /*!< GPIO_T::DINOFF: DINOFF2 Position */ +#define GPIO_DINOFF_DINOFF2_Msk (0x1ul << GPIO_DINOFF_DINOFF2_Pos) /*!< GPIO_T::DINOFF: DINOFF2 Mask */ + +#define GPIO_DINOFF_DINOFF3_Pos (19) /*!< GPIO_T::DINOFF: DINOFF3 Position */ +#define GPIO_DINOFF_DINOFF3_Msk (0x1ul << GPIO_DINOFF_DINOFF3_Pos) /*!< GPIO_T::DINOFF: DINOFF3 Mask */ + +#define GPIO_DINOFF_DINOFF4_Pos (20) /*!< GPIO_T::DINOFF: DINOFF4 Position */ +#define GPIO_DINOFF_DINOFF4_Msk (0x1ul << GPIO_DINOFF_DINOFF4_Pos) /*!< GPIO_T::DINOFF: DINOFF4 Mask */ + +#define GPIO_DINOFF_DINOFF5_Pos (21) /*!< GPIO_T::DINOFF: DINOFF5 Position */ +#define GPIO_DINOFF_DINOFF5_Msk (0x1ul << GPIO_DINOFF_DINOFF5_Pos) /*!< GPIO_T::DINOFF: DINOFF5 Mask */ + +#define GPIO_DINOFF_DINOFF6_Pos (22) /*!< GPIO_T::DINOFF: DINOFF6 Position */ +#define GPIO_DINOFF_DINOFF6_Msk (0x1ul << GPIO_DINOFF_DINOFF6_Pos) /*!< GPIO_T::DINOFF: DINOFF6 Mask */ + +#define GPIO_DINOFF_DINOFF7_Pos (23) /*!< GPIO_T::DINOFF: DINOFF7 Position */ +#define GPIO_DINOFF_DINOFF7_Msk (0x1ul << GPIO_DINOFF_DINOFF7_Pos) /*!< GPIO_T::DINOFF: DINOFF7 Mask */ + +#define GPIO_DINOFF_DINOFF8_Pos (24) /*!< GPIO_T::DINOFF: DINOFF8 Position */ +#define GPIO_DINOFF_DINOFF8_Msk (0x1ul << GPIO_DINOFF_DINOFF8_Pos) /*!< GPIO_T::DINOFF: DINOFF8 Mask */ + +#define GPIO_DINOFF_DINOFF9_Pos (25) /*!< GPIO_T::DINOFF: DINOFF9 Position */ +#define GPIO_DINOFF_DINOFF9_Msk (0x1ul << GPIO_DINOFF_DINOFF9_Pos) /*!< GPIO_T::DINOFF: DINOFF9 Mask */ + +#define GPIO_DINOFF_DINOFF10_Pos (26) /*!< GPIO_T::DINOFF: DINOFF10 Position */ +#define GPIO_DINOFF_DINOFF10_Msk (0x1ul << GPIO_DINOFF_DINOFF10_Pos) /*!< GPIO_T::DINOFF: DINOFF10 Mask */ + +#define GPIO_DINOFF_DINOFF11_Pos (27) /*!< GPIO_T::DINOFF: DINOFF11 Position */ +#define GPIO_DINOFF_DINOFF11_Msk (0x1ul << GPIO_DINOFF_DINOFF11_Pos) /*!< GPIO_T::DINOFF: DINOFF11 Mask */ + +#define GPIO_DINOFF_DINOFF12_Pos (28) /*!< GPIO_T::DINOFF: DINOFF12 Position */ +#define GPIO_DINOFF_DINOFF12_Msk (0x1ul << GPIO_DINOFF_DINOFF12_Pos) /*!< GPIO_T::DINOFF: DINOFF12 Mask */ + +#define GPIO_DINOFF_DINOFF13_Pos (29) /*!< GPIO_T::DINOFF: DINOFF13 Position */ +#define GPIO_DINOFF_DINOFF13_Msk (0x1ul << GPIO_DINOFF_DINOFF13_Pos) /*!< GPIO_T::DINOFF: DINOFF13 Mask */ + +#define GPIO_DINOFF_DINOFF14_Pos (30) /*!< GPIO_T::DINOFF: DINOFF14 Position */ +#define GPIO_DINOFF_DINOFF14_Msk (0x1ul << GPIO_DINOFF_DINOFF14_Pos) /*!< GPIO_T::DINOFF: DINOFF14 Mask */ + +#define GPIO_DINOFF_DINOFF15_Pos (31) /*!< GPIO_T::DINOFF: DINOFF15 Position */ +#define GPIO_DINOFF_DINOFF15_Msk (0x1ul << GPIO_DINOFF_DINOFF15_Pos) /*!< GPIO_T::DINOFF: DINOFF15 Mask */ + +#define GPIO_DOUT_DOUT0_Pos (0) /*!< GPIO_T::DOUT: DOUT0 Position */ +#define GPIO_DOUT_DOUT0_Msk (0x1ul << GPIO_DOUT_DOUT0_Pos) /*!< GPIO_T::DOUT: DOUT0 Mask */ + +#define GPIO_DOUT_DOUT1_Pos (1) /*!< GPIO_T::DOUT: DOUT1 Position */ +#define GPIO_DOUT_DOUT1_Msk (0x1ul << GPIO_DOUT_DOUT1_Pos) /*!< GPIO_T::DOUT: DOUT1 Mask */ + +#define GPIO_DOUT_DOUT2_Pos (2) /*!< GPIO_T::DOUT: DOUT2 Position */ +#define GPIO_DOUT_DOUT2_Msk (0x1ul << GPIO_DOUT_DOUT2_Pos) /*!< GPIO_T::DOUT: DOUT2 Mask */ + +#define GPIO_DOUT_DOUT3_Pos (3) /*!< GPIO_T::DOUT: DOUT3 Position */ +#define GPIO_DOUT_DOUT3_Msk (0x1ul << GPIO_DOUT_DOUT3_Pos) /*!< GPIO_T::DOUT: DOUT3 Mask */ + +#define GPIO_DOUT_DOUT4_Pos (4) /*!< GPIO_T::DOUT: DOUT4 Position */ +#define GPIO_DOUT_DOUT4_Msk (0x1ul << GPIO_DOUT_DOUT4_Pos) /*!< GPIO_T::DOUT: DOUT4 Mask */ + +#define GPIO_DOUT_DOUT5_Pos (5) /*!< GPIO_T::DOUT: DOUT5 Position */ +#define GPIO_DOUT_DOUT5_Msk (0x1ul << GPIO_DOUT_DOUT5_Pos) /*!< GPIO_T::DOUT: DOUT5 Mask */ + +#define GPIO_DOUT_DOUT6_Pos (6) /*!< GPIO_T::DOUT: DOUT6 Position */ +#define GPIO_DOUT_DOUT6_Msk (0x1ul << GPIO_DOUT_DOUT6_Pos) /*!< GPIO_T::DOUT: DOUT6 Mask */ + +#define GPIO_DOUT_DOUT7_Pos (7) /*!< GPIO_T::DOUT: DOUT7 Position */ +#define GPIO_DOUT_DOUT7_Msk (0x1ul << GPIO_DOUT_DOUT7_Pos) /*!< GPIO_T::DOUT: DOUT7 Mask */ + +#define GPIO_DOUT_DOUT8_Pos (8) /*!< GPIO_T::DOUT: DOUT8 Position */ +#define GPIO_DOUT_DOUT8_Msk (0x1ul << GPIO_DOUT_DOUT8_Pos) /*!< GPIO_T::DOUT: DOUT8 Mask */ + +#define GPIO_DOUT_DOUT9_Pos (9) /*!< GPIO_T::DOUT: DOUT9 Position */ +#define GPIO_DOUT_DOUT9_Msk (0x1ul << GPIO_DOUT_DOUT9_Pos) /*!< GPIO_T::DOUT: DOUT9 Mask */ + +#define GPIO_DOUT_DOUT10_Pos (10) /*!< GPIO_T::DOUT: DOUT10 Position */ +#define GPIO_DOUT_DOUT10_Msk (0x1ul << GPIO_DOUT_DOUT10_Pos) /*!< GPIO_T::DOUT: DOUT10 Mask */ + +#define GPIO_DOUT_DOUT11_Pos (11) /*!< GPIO_T::DOUT: DOUT11 Position */ +#define GPIO_DOUT_DOUT11_Msk (0x1ul << GPIO_DOUT_DOUT11_Pos) /*!< GPIO_T::DOUT: DOUT11 Mask */ + +#define GPIO_DOUT_DOUT12_Pos (12) /*!< GPIO_T::DOUT: DOUT12 Position */ +#define GPIO_DOUT_DOUT12_Msk (0x1ul << GPIO_DOUT_DOUT12_Pos) /*!< GPIO_T::DOUT: DOUT12 Mask */ + +#define GPIO_DOUT_DOUT13_Pos (13) /*!< GPIO_T::DOUT: DOUT13 Position */ +#define GPIO_DOUT_DOUT13_Msk (0x1ul << GPIO_DOUT_DOUT13_Pos) /*!< GPIO_T::DOUT: DOUT13 Mask */ + +#define GPIO_DOUT_DOUT14_Pos (14) /*!< GPIO_T::DOUT: DOUT14 Position */ +#define GPIO_DOUT_DOUT14_Msk (0x1ul << GPIO_DOUT_DOUT14_Pos) /*!< GPIO_T::DOUT: DOUT14 Mask */ + +#define GPIO_DOUT_DOUT15_Pos (15) /*!< GPIO_T::DOUT: DOUT15 Position */ +#define GPIO_DOUT_DOUT15_Msk (0x1ul << GPIO_DOUT_DOUT15_Pos) /*!< GPIO_T::DOUT: DOUT15 Mask */ + +#define GPIO_DATMSK_DATMSK0_Pos (0) /*!< GPIO_T::DATMSK: DATMSK0 Position */ +#define GPIO_DATMSK_DATMSK0_Msk (0x1ul << GPIO_DATMSK_DATMSK0_Pos) /*!< GPIO_T::DATMSK: DATMSK0 Mask */ + +#define GPIO_DATMSK_DATMSK1_Pos (1) /*!< GPIO_T::DATMSK: DATMSK1 Position */ +#define GPIO_DATMSK_DATMSK1_Msk (0x1ul << GPIO_DATMSK_DATMSK1_Pos) /*!< GPIO_T::DATMSK: DATMSK1 Mask */ + +#define GPIO_DATMSK_DATMSK2_Pos (2) /*!< GPIO_T::DATMSK: DATMSK2 Position */ +#define GPIO_DATMSK_DATMSK2_Msk (0x1ul << GPIO_DATMSK_DATMSK2_Pos) /*!< GPIO_T::DATMSK: DATMSK2 Mask */ + +#define GPIO_DATMSK_DATMSK3_Pos (3) /*!< GPIO_T::DATMSK: DATMSK3 Position */ +#define GPIO_DATMSK_DATMSK3_Msk (0x1ul << GPIO_DATMSK_DATMSK3_Pos) /*!< GPIO_T::DATMSK: DATMSK3 Mask */ + +#define GPIO_DATMSK_DATMSK4_Pos (4) /*!< GPIO_T::DATMSK: DATMSK4 Position */ +#define GPIO_DATMSK_DATMSK4_Msk (0x1ul << GPIO_DATMSK_DATMSK4_Pos) /*!< GPIO_T::DATMSK: DATMSK4 Mask */ + +#define GPIO_DATMSK_DATMSK5_Pos (5) /*!< GPIO_T::DATMSK: DATMSK5 Position */ +#define GPIO_DATMSK_DATMSK5_Msk (0x1ul << GPIO_DATMSK_DATMSK5_Pos) /*!< GPIO_T::DATMSK: DATMSK5 Mask */ + +#define GPIO_DATMSK_DATMSK6_Pos (6) /*!< GPIO_T::DATMSK: DATMSK6 Position */ +#define GPIO_DATMSK_DATMSK6_Msk (0x1ul << GPIO_DATMSK_DATMSK6_Pos) /*!< GPIO_T::DATMSK: DATMSK6 Mask */ + +#define GPIO_DATMSK_DATMSK7_Pos (7) /*!< GPIO_T::DATMSK: DATMSK7 Position */ +#define GPIO_DATMSK_DATMSK7_Msk (0x1ul << GPIO_DATMSK_DATMSK7_Pos) /*!< GPIO_T::DATMSK: DATMSK7 Mask */ + +#define GPIO_DATMSK_DATMSK8_Pos (8) /*!< GPIO_T::DATMSK: DATMSK8 Position */ +#define GPIO_DATMSK_DATMSK8_Msk (0x1ul << GPIO_DATMSK_DATMSK8_Pos) /*!< GPIO_T::DATMSK: DATMSK8 Mask */ + +#define GPIO_DATMSK_DATMSK9_Pos (9) /*!< GPIO_T::DATMSK: DATMSK9 Position */ +#define GPIO_DATMSK_DATMSK9_Msk (0x1ul << GPIO_DATMSK_DATMSK9_Pos) /*!< GPIO_T::DATMSK: DATMSK9 Mask */ + +#define GPIO_DATMSK_DATMSK10_Pos (10) /*!< GPIO_T::DATMSK: DATMSK10 Position */ +#define GPIO_DATMSK_DATMSK10_Msk (0x1ul << GPIO_DATMSK_DATMSK10_Pos) /*!< GPIO_T::DATMSK: DATMSK10 Mask */ + +#define GPIO_DATMSK_DATMSK11_Pos (11) /*!< GPIO_T::DATMSK: DATMSK11 Position */ +#define GPIO_DATMSK_DATMSK11_Msk (0x1ul << GPIO_DATMSK_DATMSK11_Pos) /*!< GPIO_T::DATMSK: DATMSK11 Mask */ + +#define GPIO_DATMSK_DATMSK12_Pos (12) /*!< GPIO_T::DATMSK: DATMSK12 Position */ +#define GPIO_DATMSK_DATMSK12_Msk (0x1ul << GPIO_DATMSK_DATMSK12_Pos) /*!< GPIO_T::DATMSK: DATMSK12 Mask */ + +#define GPIO_DATMSK_DATMSK13_Pos (13) /*!< GPIO_T::DATMSK: DATMSK13 Position */ +#define GPIO_DATMSK_DATMSK13_Msk (0x1ul << GPIO_DATMSK_DATMSK13_Pos) /*!< GPIO_T::DATMSK: DATMSK13 Mask */ + +#define GPIO_DATMSK_DATMSK14_Pos (14) /*!< GPIO_T::DATMSK: DATMSK14 Position */ +#define GPIO_DATMSK_DATMSK14_Msk (0x1ul << GPIO_DATMSK_DATMSK14_Pos) /*!< GPIO_T::DATMSK: DATMSK14 Mask */ + +#define GPIO_DATMSK_DATMSK15_Pos (15) /*!< GPIO_T::DATMSK: DATMSK15 Position */ +#define GPIO_DATMSK_DATMSK15_Msk (0x1ul << GPIO_DATMSK_DATMSK15_Pos) /*!< GPIO_T::DATMSK: DATMSK15 Mask */ + +#define GPIO_PIN_PIN0_Pos (0) /*!< GPIO_T::PIN: PIN0 Position */ +#define GPIO_PIN_PIN0_Msk (0x1ul << GPIO_PIN_PIN0_Pos) /*!< GPIO_T::PIN: PIN0 Mask */ + +#define GPIO_PIN_PIN1_Pos (1) /*!< GPIO_T::PIN: PIN1 Position */ +#define GPIO_PIN_PIN1_Msk (0x1ul << GPIO_PIN_PIN1_Pos) /*!< GPIO_T::PIN: PIN1 Mask */ + +#define GPIO_PIN_PIN2_Pos (2) /*!< GPIO_T::PIN: PIN2 Position */ +#define GPIO_PIN_PIN2_Msk (0x1ul << GPIO_PIN_PIN2_Pos) /*!< GPIO_T::PIN: PIN2 Mask */ + +#define GPIO_PIN_PIN3_Pos (3) /*!< GPIO_T::PIN: PIN3 Position */ +#define GPIO_PIN_PIN3_Msk (0x1ul << GPIO_PIN_PIN3_Pos) /*!< GPIO_T::PIN: PIN3 Mask */ + +#define GPIO_PIN_PIN4_Pos (4) /*!< GPIO_T::PIN: PIN4 Position */ +#define GPIO_PIN_PIN4_Msk (0x1ul << GPIO_PIN_PIN4_Pos) /*!< GPIO_T::PIN: PIN4 Mask */ + +#define GPIO_PIN_PIN5_Pos (5) /*!< GPIO_T::PIN: PIN5 Position */ +#define GPIO_PIN_PIN5_Msk (0x1ul << GPIO_PIN_PIN5_Pos) /*!< GPIO_T::PIN: PIN5 Mask */ + +#define GPIO_PIN_PIN6_Pos (6) /*!< GPIO_T::PIN: PIN6 Position */ +#define GPIO_PIN_PIN6_Msk (0x1ul << GPIO_PIN_PIN6_Pos) /*!< GPIO_T::PIN: PIN6 Mask */ + +#define GPIO_PIN_PIN7_Pos (7) /*!< GPIO_T::PIN: PIN7 Position */ +#define GPIO_PIN_PIN7_Msk (0x1ul << GPIO_PIN_PIN7_Pos) /*!< GPIO_T::PIN: PIN7 Mask */ + +#define GPIO_PIN_PIN8_Pos (8) /*!< GPIO_T::PIN: PIN8 Position */ +#define GPIO_PIN_PIN8_Msk (0x1ul << GPIO_PIN_PIN8_Pos) /*!< GPIO_T::PIN: PIN8 Mask */ + +#define GPIO_PIN_PIN9_Pos (9) /*!< GPIO_T::PIN: PIN9 Position */ +#define GPIO_PIN_PIN9_Msk (0x1ul << GPIO_PIN_PIN9_Pos) /*!< GPIO_T::PIN: PIN9 Mask */ + +#define GPIO_PIN_PIN10_Pos (10) /*!< GPIO_T::PIN: PIN10 Position */ +#define GPIO_PIN_PIN10_Msk (0x1ul << GPIO_PIN_PIN10_Pos) /*!< GPIO_T::PIN: PIN10 Mask */ + +#define GPIO_PIN_PIN11_Pos (11) /*!< GPIO_T::PIN: PIN11 Position */ +#define GPIO_PIN_PIN11_Msk (0x1ul << GPIO_PIN_PIN11_Pos) /*!< GPIO_T::PIN: PIN11 Mask */ + +#define GPIO_PIN_PIN12_Pos (12) /*!< GPIO_T::PIN: PIN12 Position */ +#define GPIO_PIN_PIN12_Msk (0x1ul << GPIO_PIN_PIN12_Pos) /*!< GPIO_T::PIN: PIN12 Mask */ + +#define GPIO_PIN_PIN13_Pos (13) /*!< GPIO_T::PIN: PIN13 Position */ +#define GPIO_PIN_PIN13_Msk (0x1ul << GPIO_PIN_PIN13_Pos) /*!< GPIO_T::PIN: PIN13 Mask */ + +#define GPIO_PIN_PIN14_Pos (14) /*!< GPIO_T::PIN: PIN14 Position */ +#define GPIO_PIN_PIN14_Msk (0x1ul << GPIO_PIN_PIN14_Pos) /*!< GPIO_T::PIN: PIN14 Mask */ + +#define GPIO_PIN_PIN15_Pos (15) /*!< GPIO_T::PIN: PIN15 Position */ +#define GPIO_PIN_PIN15_Msk (0x1ul << GPIO_PIN_PIN15_Pos) /*!< GPIO_T::PIN: PIN15 Mask */ + +#define GPIO_DBEN_DBEN0_Pos (0) /*!< GPIO_T::DBEN: DBEN0 Position */ +#define GPIO_DBEN_DBEN0_Msk (0x1ul << GPIO_DBEN_DBEN0_Pos) /*!< GPIO_T::DBEN: DBEN0 Mask */ + +#define GPIO_DBEN_DBEN1_Pos (1) /*!< GPIO_T::DBEN: DBEN1 Position */ +#define GPIO_DBEN_DBEN1_Msk (0x1ul << GPIO_DBEN_DBEN1_Pos) /*!< GPIO_T::DBEN: DBEN1 Mask */ + +#define GPIO_DBEN_DBEN2_Pos (2) /*!< GPIO_T::DBEN: DBEN2 Position */ +#define GPIO_DBEN_DBEN2_Msk (0x1ul << GPIO_DBEN_DBEN2_Pos) /*!< GPIO_T::DBEN: DBEN2 Mask */ + +#define GPIO_DBEN_DBEN3_Pos (3) /*!< GPIO_T::DBEN: DBEN3 Position */ +#define GPIO_DBEN_DBEN3_Msk (0x1ul << GPIO_DBEN_DBEN3_Pos) /*!< GPIO_T::DBEN: DBEN3 Mask */ + +#define GPIO_DBEN_DBEN4_Pos (4) /*!< GPIO_T::DBEN: DBEN4 Position */ +#define GPIO_DBEN_DBEN4_Msk (0x1ul << GPIO_DBEN_DBEN4_Pos) /*!< GPIO_T::DBEN: DBEN4 Mask */ + +#define GPIO_DBEN_DBEN5_Pos (5) /*!< GPIO_T::DBEN: DBEN5 Position */ +#define GPIO_DBEN_DBEN5_Msk (0x1ul << GPIO_DBEN_DBEN5_Pos) /*!< GPIO_T::DBEN: DBEN5 Mask */ + +#define GPIO_DBEN_DBEN6_Pos (6) /*!< GPIO_T::DBEN: DBEN6 Position */ +#define GPIO_DBEN_DBEN6_Msk (0x1ul << GPIO_DBEN_DBEN6_Pos) /*!< GPIO_T::DBEN: DBEN6 Mask */ + +#define GPIO_DBEN_DBEN7_Pos (7) /*!< GPIO_T::DBEN: DBEN7 Position */ +#define GPIO_DBEN_DBEN7_Msk (0x1ul << GPIO_DBEN_DBEN7_Pos) /*!< GPIO_T::DBEN: DBEN7 Mask */ + +#define GPIO_DBEN_DBEN8_Pos (8) /*!< GPIO_T::DBEN: DBEN8 Position */ +#define GPIO_DBEN_DBEN8_Msk (0x1ul << GPIO_DBEN_DBEN8_Pos) /*!< GPIO_T::DBEN: DBEN8 Mask */ + +#define GPIO_DBEN_DBEN9_Pos (9) /*!< GPIO_T::DBEN: DBEN9 Position */ +#define GPIO_DBEN_DBEN9_Msk (0x1ul << GPIO_DBEN_DBEN9_Pos) /*!< GPIO_T::DBEN: DBEN9 Mask */ + +#define GPIO_DBEN_DBEN10_Pos (10) /*!< GPIO_T::DBEN: DBEN10 Position */ +#define GPIO_DBEN_DBEN10_Msk (0x1ul << GPIO_DBEN_DBEN10_Pos) /*!< GPIO_T::DBEN: DBEN10 Mask */ + +#define GPIO_DBEN_DBEN11_Pos (11) /*!< GPIO_T::DBEN: DBEN11 Position */ +#define GPIO_DBEN_DBEN11_Msk (0x1ul << GPIO_DBEN_DBEN11_Pos) /*!< GPIO_T::DBEN: DBEN11 Mask */ + +#define GPIO_DBEN_DBEN12_Pos (12) /*!< GPIO_T::DBEN: DBEN12 Position */ +#define GPIO_DBEN_DBEN12_Msk (0x1ul << GPIO_DBEN_DBEN12_Pos) /*!< GPIO_T::DBEN: DBEN12 Mask */ + +#define GPIO_DBEN_DBEN13_Pos (13) /*!< GPIO_T::DBEN: DBEN13 Position */ +#define GPIO_DBEN_DBEN13_Msk (0x1ul << GPIO_DBEN_DBEN13_Pos) /*!< GPIO_T::DBEN: DBEN13 Mask */ + +#define GPIO_DBEN_DBEN14_Pos (14) /*!< GPIO_T::DBEN: DBEN14 Position */ +#define GPIO_DBEN_DBEN14_Msk (0x1ul << GPIO_DBEN_DBEN14_Pos) /*!< GPIO_T::DBEN: DBEN14 Mask */ + +#define GPIO_DBEN_DBEN15_Pos (15) /*!< GPIO_T::DBEN: DBEN15 Position */ +#define GPIO_DBEN_DBEN15_Msk (0x1ul << GPIO_DBEN_DBEN15_Pos) /*!< GPIO_T::DBEN: DBEN15 Mask */ + +#define GPIO_INTTYPE_TYPE0_Pos (0) /*!< GPIO_T::INTTYPE: TYPE0 Position */ +#define GPIO_INTTYPE_TYPE0_Msk (0x1ul << GPIO_INTTYPE_TYPE0_Pos) /*!< GPIO_T::INTTYPE: TYPE0 Mask */ + +#define GPIO_INTTYPE_TYPE1_Pos (1) /*!< GPIO_T::INTTYPE: TYPE1 Position */ +#define GPIO_INTTYPE_TYPE1_Msk (0x1ul << GPIO_INTTYPE_TYPE1_Pos) /*!< GPIO_T::INTTYPE: TYPE1 Mask */ + +#define GPIO_INTTYPE_TYPE2_Pos (2) /*!< GPIO_T::INTTYPE: TYPE2 Position */ +#define GPIO_INTTYPE_TYPE2_Msk (0x1ul << GPIO_INTTYPE_TYPE2_Pos) /*!< GPIO_T::INTTYPE: TYPE2 Mask */ + +#define GPIO_INTTYPE_TYPE3_Pos (3) /*!< GPIO_T::INTTYPE: TYPE3 Position */ +#define GPIO_INTTYPE_TYPE3_Msk (0x1ul << GPIO_INTTYPE_TYPE3_Pos) /*!< GPIO_T::INTTYPE: TYPE3 Mask */ + +#define GPIO_INTTYPE_TYPE4_Pos (4) /*!< GPIO_T::INTTYPE: TYPE4 Position */ +#define GPIO_INTTYPE_TYPE4_Msk (0x1ul << GPIO_INTTYPE_TYPE4_Pos) /*!< GPIO_T::INTTYPE: TYPE4 Mask */ + +#define GPIO_INTTYPE_TYPE5_Pos (5) /*!< GPIO_T::INTTYPE: TYPE5 Position */ +#define GPIO_INTTYPE_TYPE5_Msk (0x1ul << GPIO_INTTYPE_TYPE5_Pos) /*!< GPIO_T::INTTYPE: TYPE5 Mask */ + +#define GPIO_INTTYPE_TYPE6_Pos (6) /*!< GPIO_T::INTTYPE: TYPE6 Position */ +#define GPIO_INTTYPE_TYPE6_Msk (0x1ul << GPIO_INTTYPE_TYPE6_Pos) /*!< GPIO_T::INTTYPE: TYPE6 Mask */ + +#define GPIO_INTTYPE_TYPE7_Pos (7) /*!< GPIO_T::INTTYPE: TYPE7 Position */ +#define GPIO_INTTYPE_TYPE7_Msk (0x1ul << GPIO_INTTYPE_TYPE7_Pos) /*!< GPIO_T::INTTYPE: TYPE7 Mask */ + +#define GPIO_INTTYPE_TYPE8_Pos (8) /*!< GPIO_T::INTTYPE: TYPE8 Position */ +#define GPIO_INTTYPE_TYPE8_Msk (0x1ul << GPIO_INTTYPE_TYPE8_Pos) /*!< GPIO_T::INTTYPE: TYPE8 Mask */ + +#define GPIO_INTTYPE_TYPE9_Pos (9) /*!< GPIO_T::INTTYPE: TYPE9 Position */ +#define GPIO_INTTYPE_TYPE9_Msk (0x1ul << GPIO_INTTYPE_TYPE9_Pos) /*!< GPIO_T::INTTYPE: TYPE9 Mask */ + +#define GPIO_INTTYPE_TYPE10_Pos (10) /*!< GPIO_T::INTTYPE: TYPE10 Position */ +#define GPIO_INTTYPE_TYPE10_Msk (0x1ul << GPIO_INTTYPE_TYPE10_Pos) /*!< GPIO_T::INTTYPE: TYPE10 Mask */ + +#define GPIO_INTTYPE_TYPE11_Pos (11) /*!< GPIO_T::INTTYPE: TYPE11 Position */ +#define GPIO_INTTYPE_TYPE11_Msk (0x1ul << GPIO_INTTYPE_TYPE11_Pos) /*!< GPIO_T::INTTYPE: TYPE11 Mask */ + +#define GPIO_INTTYPE_TYPE12_Pos (12) /*!< GPIO_T::INTTYPE: TYPE12 Position */ +#define GPIO_INTTYPE_TYPE12_Msk (0x1ul << GPIO_INTTYPE_TYPE12_Pos) /*!< GPIO_T::INTTYPE: TYPE12 Mask */ + +#define GPIO_INTTYPE_TYPE13_Pos (13) /*!< GPIO_T::INTTYPE: TYPE13 Position */ +#define GPIO_INTTYPE_TYPE13_Msk (0x1ul << GPIO_INTTYPE_TYPE13_Pos) /*!< GPIO_T::INTTYPE: TYPE13 Mask */ + +#define GPIO_INTTYPE_TYPE14_Pos (14) /*!< GPIO_T::INTTYPE: TYPE14 Position */ +#define GPIO_INTTYPE_TYPE14_Msk (0x1ul << GPIO_INTTYPE_TYPE14_Pos) /*!< GPIO_T::INTTYPE: TYPE14 Mask */ + +#define GPIO_INTTYPE_TYPE15_Pos (15) /*!< GPIO_T::INTTYPE: TYPE15 Position */ +#define GPIO_INTTYPE_TYPE15_Msk (0x1ul << GPIO_INTTYPE_TYPE15_Pos) /*!< GPIO_T::INTTYPE: TYPE15 Mask */ + +#define GPIO_INTEN_FLIEN0_Pos (0) /*!< GPIO_T::INTEN: FLIEN0 Position */ +#define GPIO_INTEN_FLIEN0_Msk (0x1ul << GPIO_INTEN_FLIEN0_Pos) /*!< GPIO_T::INTEN: FLIEN0 Mask */ + +#define GPIO_INTEN_FLIEN1_Pos (1) /*!< GPIO_T::INTEN: FLIEN1 Position */ +#define GPIO_INTEN_FLIEN1_Msk (0x1ul << GPIO_INTEN_FLIEN1_Pos) /*!< GPIO_T::INTEN: FLIEN1 Mask */ + +#define GPIO_INTEN_FLIEN2_Pos (2) /*!< GPIO_T::INTEN: FLIEN2 Position */ +#define GPIO_INTEN_FLIEN2_Msk (0x1ul << GPIO_INTEN_FLIEN2_Pos) /*!< GPIO_T::INTEN: FLIEN2 Mask */ + +#define GPIO_INTEN_FLIEN3_Pos (3) /*!< GPIO_T::INTEN: FLIEN3 Position */ +#define GPIO_INTEN_FLIEN3_Msk (0x1ul << GPIO_INTEN_FLIEN3_Pos) /*!< GPIO_T::INTEN: FLIEN3 Mask */ + +#define GPIO_INTEN_FLIEN4_Pos (4) /*!< GPIO_T::INTEN: FLIEN4 Position */ +#define GPIO_INTEN_FLIEN4_Msk (0x1ul << GPIO_INTEN_FLIEN4_Pos) /*!< GPIO_T::INTEN: FLIEN4 Mask */ + +#define GPIO_INTEN_FLIEN5_Pos (5) /*!< GPIO_T::INTEN: FLIEN5 Position */ +#define GPIO_INTEN_FLIEN5_Msk (0x1ul << GPIO_INTEN_FLIEN5_Pos) /*!< GPIO_T::INTEN: FLIEN5 Mask */ + +#define GPIO_INTEN_FLIEN6_Pos (6) /*!< GPIO_T::INTEN: FLIEN6 Position */ +#define GPIO_INTEN_FLIEN6_Msk (0x1ul << GPIO_INTEN_FLIEN6_Pos) /*!< GPIO_T::INTEN: FLIEN6 Mask */ + +#define GPIO_INTEN_FLIEN7_Pos (7) /*!< GPIO_T::INTEN: FLIEN7 Position */ +#define GPIO_INTEN_FLIEN7_Msk (0x1ul << GPIO_INTEN_FLIEN7_Pos) /*!< GPIO_T::INTEN: FLIEN7 Mask */ + +#define GPIO_INTEN_FLIEN8_Pos (8) /*!< GPIO_T::INTEN: FLIEN8 Position */ +#define GPIO_INTEN_FLIEN8_Msk (0x1ul << GPIO_INTEN_FLIEN8_Pos) /*!< GPIO_T::INTEN: FLIEN8 Mask */ + +#define GPIO_INTEN_FLIEN9_Pos (9) /*!< GPIO_T::INTEN: FLIEN9 Position */ +#define GPIO_INTEN_FLIEN9_Msk (0x1ul << GPIO_INTEN_FLIEN9_Pos) /*!< GPIO_T::INTEN: FLIEN9 Mask */ + +#define GPIO_INTEN_FLIEN10_Pos (10) /*!< GPIO_T::INTEN: FLIEN10 Position */ +#define GPIO_INTEN_FLIEN10_Msk (0x1ul << GPIO_INTEN_FLIEN10_Pos) /*!< GPIO_T::INTEN: FLIEN10 Mask */ + +#define GPIO_INTEN_FLIEN11_Pos (11) /*!< GPIO_T::INTEN: FLIEN11 Position */ +#define GPIO_INTEN_FLIEN11_Msk (0x1ul << GPIO_INTEN_FLIEN11_Pos) /*!< GPIO_T::INTEN: FLIEN11 Mask */ + +#define GPIO_INTEN_FLIEN12_Pos (12) /*!< GPIO_T::INTEN: FLIEN12 Position */ +#define GPIO_INTEN_FLIEN12_Msk (0x1ul << GPIO_INTEN_FLIEN12_Pos) /*!< GPIO_T::INTEN: FLIEN12 Mask */ + +#define GPIO_INTEN_FLIEN13_Pos (13) /*!< GPIO_T::INTEN: FLIEN13 Position */ +#define GPIO_INTEN_FLIEN13_Msk (0x1ul << GPIO_INTEN_FLIEN13_Pos) /*!< GPIO_T::INTEN: FLIEN13 Mask */ + +#define GPIO_INTEN_FLIEN14_Pos (14) /*!< GPIO_T::INTEN: FLIEN14 Position */ +#define GPIO_INTEN_FLIEN14_Msk (0x1ul << GPIO_INTEN_FLIEN14_Pos) /*!< GPIO_T::INTEN: FLIEN14 Mask */ + +#define GPIO_INTEN_FLIEN15_Pos (15) /*!< GPIO_T::INTEN: FLIEN15 Position */ +#define GPIO_INTEN_FLIEN15_Msk (0x1ul << GPIO_INTEN_FLIEN15_Pos) /*!< GPIO_T::INTEN: FLIEN15 Mask */ + +#define GPIO_INTEN_RHIEN0_Pos (16) /*!< GPIO_T::INTEN: RHIEN0 Position */ +#define GPIO_INTEN_RHIEN0_Msk (0x1ul << GPIO_INTEN_RHIEN0_Pos) /*!< GPIO_T::INTEN: RHIEN0 Mask */ + +#define GPIO_INTEN_RHIEN1_Pos (17) /*!< GPIO_T::INTEN: RHIEN1 Position */ +#define GPIO_INTEN_RHIEN1_Msk (0x1ul << GPIO_INTEN_RHIEN1_Pos) /*!< GPIO_T::INTEN: RHIEN1 Mask */ + +#define GPIO_INTEN_RHIEN2_Pos (18) /*!< GPIO_T::INTEN: RHIEN2 Position */ +#define GPIO_INTEN_RHIEN2_Msk (0x1ul << GPIO_INTEN_RHIEN2_Pos) /*!< GPIO_T::INTEN: RHIEN2 Mask */ + +#define GPIO_INTEN_RHIEN3_Pos (19) /*!< GPIO_T::INTEN: RHIEN3 Position */ +#define GPIO_INTEN_RHIEN3_Msk (0x1ul << GPIO_INTEN_RHIEN3_Pos) /*!< GPIO_T::INTEN: RHIEN3 Mask */ + +#define GPIO_INTEN_RHIEN4_Pos (20) /*!< GPIO_T::INTEN: RHIEN4 Position */ +#define GPIO_INTEN_RHIEN4_Msk (0x1ul << GPIO_INTEN_RHIEN4_Pos) /*!< GPIO_T::INTEN: RHIEN4 Mask */ + +#define GPIO_INTEN_RHIEN5_Pos (21) /*!< GPIO_T::INTEN: RHIEN5 Position */ +#define GPIO_INTEN_RHIEN5_Msk (0x1ul << GPIO_INTEN_RHIEN5_Pos) /*!< GPIO_T::INTEN: RHIEN5 Mask */ + +#define GPIO_INTEN_RHIEN6_Pos (22) /*!< GPIO_T::INTEN: RHIEN6 Position */ +#define GPIO_INTEN_RHIEN6_Msk (0x1ul << GPIO_INTEN_RHIEN6_Pos) /*!< GPIO_T::INTEN: RHIEN6 Mask */ + +#define GPIO_INTEN_RHIEN7_Pos (23) /*!< GPIO_T::INTEN: RHIEN7 Position */ +#define GPIO_INTEN_RHIEN7_Msk (0x1ul << GPIO_INTEN_RHIEN7_Pos) /*!< GPIO_T::INTEN: RHIEN7 Mask */ + +#define GPIO_INTEN_RHIEN8_Pos (24) /*!< GPIO_T::INTEN: RHIEN8 Position */ +#define GPIO_INTEN_RHIEN8_Msk (0x1ul << GPIO_INTEN_RHIEN8_Pos) /*!< GPIO_T::INTEN: RHIEN8 Mask */ + +#define GPIO_INTEN_RHIEN9_Pos (25) /*!< GPIO_T::INTEN: RHIEN9 Position */ +#define GPIO_INTEN_RHIEN9_Msk (0x1ul << GPIO_INTEN_RHIEN9_Pos) /*!< GPIO_T::INTEN: RHIEN9 Mask */ + +#define GPIO_INTEN_RHIEN10_Pos (26) /*!< GPIO_T::INTEN: RHIEN10 Position */ +#define GPIO_INTEN_RHIEN10_Msk (0x1ul << GPIO_INTEN_RHIEN10_Pos) /*!< GPIO_T::INTEN: RHIEN10 Mask */ + +#define GPIO_INTEN_RHIEN11_Pos (27) /*!< GPIO_T::INTEN: RHIEN11 Position */ +#define GPIO_INTEN_RHIEN11_Msk (0x1ul << GPIO_INTEN_RHIEN11_Pos) /*!< GPIO_T::INTEN: RHIEN11 Mask */ + +#define GPIO_INTEN_RHIEN12_Pos (28) /*!< GPIO_T::INTEN: RHIEN12 Position */ +#define GPIO_INTEN_RHIEN12_Msk (0x1ul << GPIO_INTEN_RHIEN12_Pos) /*!< GPIO_T::INTEN: RHIEN12 Mask */ + +#define GPIO_INTEN_RHIEN13_Pos (29) /*!< GPIO_T::INTEN: RHIEN13 Position */ +#define GPIO_INTEN_RHIEN13_Msk (0x1ul << GPIO_INTEN_RHIEN13_Pos) /*!< GPIO_T::INTEN: RHIEN13 Mask */ + +#define GPIO_INTEN_RHIEN14_Pos (30) /*!< GPIO_T::INTEN: RHIEN14 Position */ +#define GPIO_INTEN_RHIEN14_Msk (0x1ul << GPIO_INTEN_RHIEN14_Pos) /*!< GPIO_T::INTEN: RHIEN14 Mask */ + +#define GPIO_INTEN_RHIEN15_Pos (31) /*!< GPIO_T::INTEN: RHIEN15 Position */ +#define GPIO_INTEN_RHIEN15_Msk (0x1ul << GPIO_INTEN_RHIEN15_Pos) /*!< GPIO_T::INTEN: RHIEN15 Mask */ + +#define GPIO_INTSRC_INTSRC0_Pos (0) /*!< GPIO_T::INTSRC: INTSRC0 Position */ +#define GPIO_INTSRC_INTSRC0_Msk (0x1ul << GPIO_INTSRC_INTSRC0_Pos) /*!< GPIO_T::INTSRC: INTSRC0 Mask */ + +#define GPIO_INTSRC_INTSRC1_Pos (1) /*!< GPIO_T::INTSRC: INTSRC1 Position */ +#define GPIO_INTSRC_INTSRC1_Msk (0x1ul << GPIO_INTSRC_INTSRC1_Pos) /*!< GPIO_T::INTSRC: INTSRC1 Mask */ + +#define GPIO_INTSRC_INTSRC2_Pos (2) /*!< GPIO_T::INTSRC: INTSRC2 Position */ +#define GPIO_INTSRC_INTSRC2_Msk (0x1ul << GPIO_INTSRC_INTSRC2_Pos) /*!< GPIO_T::INTSRC: INTSRC2 Mask */ + +#define GPIO_INTSRC_INTSRC3_Pos (3) /*!< GPIO_T::INTSRC: INTSRC3 Position */ +#define GPIO_INTSRC_INTSRC3_Msk (0x1ul << GPIO_INTSRC_INTSRC3_Pos) /*!< GPIO_T::INTSRC: INTSRC3 Mask */ + +#define GPIO_INTSRC_INTSRC4_Pos (4) /*!< GPIO_T::INTSRC: INTSRC4 Position */ +#define GPIO_INTSRC_INTSRC4_Msk (0x1ul << GPIO_INTSRC_INTSRC4_Pos) /*!< GPIO_T::INTSRC: INTSRC4 Mask */ + +#define GPIO_INTSRC_INTSRC5_Pos (5) /*!< GPIO_T::INTSRC: INTSRC5 Position */ +#define GPIO_INTSRC_INTSRC5_Msk (0x1ul << GPIO_INTSRC_INTSRC5_Pos) /*!< GPIO_T::INTSRC: INTSRC5 Mask */ + +#define GPIO_INTSRC_INTSRC6_Pos (6) /*!< GPIO_T::INTSRC: INTSRC6 Position */ +#define GPIO_INTSRC_INTSRC6_Msk (0x1ul << GPIO_INTSRC_INTSRC6_Pos) /*!< GPIO_T::INTSRC: INTSRC6 Mask */ + +#define GPIO_INTSRC_INTSRC7_Pos (7) /*!< GPIO_T::INTSRC: INTSRC7 Position */ +#define GPIO_INTSRC_INTSRC7_Msk (0x1ul << GPIO_INTSRC_INTSRC7_Pos) /*!< GPIO_T::INTSRC: INTSRC7 Mask */ + +#define GPIO_INTSRC_INTSRC8_Pos (8) /*!< GPIO_T::INTSRC: INTSRC8 Position */ +#define GPIO_INTSRC_INTSRC8_Msk (0x1ul << GPIO_INTSRC_INTSRC8_Pos) /*!< GPIO_T::INTSRC: INTSRC8 Mask */ + +#define GPIO_INTSRC_INTSRC9_Pos (9) /*!< GPIO_T::INTSRC: INTSRC9 Position */ +#define GPIO_INTSRC_INTSRC9_Msk (0x1ul << GPIO_INTSRC_INTSRC9_Pos) /*!< GPIO_T::INTSRC: INTSRC9 Mask */ + +#define GPIO_INTSRC_INTSRC10_Pos (10) /*!< GPIO_T::INTSRC: INTSRC10 Position */ +#define GPIO_INTSRC_INTSRC10_Msk (0x1ul << GPIO_INTSRC_INTSRC10_Pos) /*!< GPIO_T::INTSRC: INTSRC10 Mask */ + +#define GPIO_INTSRC_INTSRC11_Pos (11) /*!< GPIO_T::INTSRC: INTSRC11 Position */ +#define GPIO_INTSRC_INTSRC11_Msk (0x1ul << GPIO_INTSRC_INTSRC11_Pos) /*!< GPIO_T::INTSRC: INTSRC11 Mask */ + +#define GPIO_INTSRC_INTSRC12_Pos (12) /*!< GPIO_T::INTSRC: INTSRC12 Position */ +#define GPIO_INTSRC_INTSRC12_Msk (0x1ul << GPIO_INTSRC_INTSRC12_Pos) /*!< GPIO_T::INTSRC: INTSRC12 Mask */ + +#define GPIO_INTSRC_INTSRC13_Pos (13) /*!< GPIO_T::INTSRC: INTSRC13 Position */ +#define GPIO_INTSRC_INTSRC13_Msk (0x1ul << GPIO_INTSRC_INTSRC13_Pos) /*!< GPIO_T::INTSRC: INTSRC13 Mask */ + +#define GPIO_INTSRC_INTSRC14_Pos (14) /*!< GPIO_T::INTSRC: INTSRC14 Position */ +#define GPIO_INTSRC_INTSRC14_Msk (0x1ul << GPIO_INTSRC_INTSRC14_Pos) /*!< GPIO_T::INTSRC: INTSRC14 Mask */ + +#define GPIO_INTSRC_INTSRC15_Pos (15) /*!< GPIO_T::INTSRC: INTSRC15 Position */ +#define GPIO_INTSRC_INTSRC15_Msk (0x1ul << GPIO_INTSRC_INTSRC15_Pos) /*!< GPIO_T::INTSRC: INTSRC15 Mask */ + +#define GPIO_SMTEN_SMTEN0_Pos (0) /*!< GPIO_T::SMTEN: SMTEN0 Position */ +#define GPIO_SMTEN_SMTEN0_Msk (0x1ul << GPIO_SMTEN_SMTEN0_Pos) /*!< GPIO_T::SMTEN: SMTEN0 Mask */ + +#define GPIO_SMTEN_SMTEN1_Pos (1) /*!< GPIO_T::SMTEN: SMTEN1 Position */ +#define GPIO_SMTEN_SMTEN1_Msk (0x1ul << GPIO_SMTEN_SMTEN1_Pos) /*!< GPIO_T::SMTEN: SMTEN1 Mask */ + +#define GPIO_SMTEN_SMTEN2_Pos (2) /*!< GPIO_T::SMTEN: SMTEN2 Position */ +#define GPIO_SMTEN_SMTEN2_Msk (0x1ul << GPIO_SMTEN_SMTEN2_Pos) /*!< GPIO_T::SMTEN: SMTEN2 Mask */ + +#define GPIO_SMTEN_SMTEN3_Pos (3) /*!< GPIO_T::SMTEN: SMTEN3 Position */ +#define GPIO_SMTEN_SMTEN3_Msk (0x1ul << GPIO_SMTEN_SMTEN3_Pos) /*!< GPIO_T::SMTEN: SMTEN3 Mask */ + +#define GPIO_SMTEN_SMTEN4_Pos (4) /*!< GPIO_T::SMTEN: SMTEN4 Position */ +#define GPIO_SMTEN_SMTEN4_Msk (0x1ul << GPIO_SMTEN_SMTEN4_Pos) /*!< GPIO_T::SMTEN: SMTEN4 Mask */ + +#define GPIO_SMTEN_SMTEN5_Pos (5) /*!< GPIO_T::SMTEN: SMTEN5 Position */ +#define GPIO_SMTEN_SMTEN5_Msk (0x1ul << GPIO_SMTEN_SMTEN5_Pos) /*!< GPIO_T::SMTEN: SMTEN5 Mask */ + +#define GPIO_SMTEN_SMTEN6_Pos (6) /*!< GPIO_T::SMTEN: SMTEN6 Position */ +#define GPIO_SMTEN_SMTEN6_Msk (0x1ul << GPIO_SMTEN_SMTEN6_Pos) /*!< GPIO_T::SMTEN: SMTEN6 Mask */ + +#define GPIO_SMTEN_SMTEN7_Pos (7) /*!< GPIO_T::SMTEN: SMTEN7 Position */ +#define GPIO_SMTEN_SMTEN7_Msk (0x1ul << GPIO_SMTEN_SMTEN7_Pos) /*!< GPIO_T::SMTEN: SMTEN7 Mask */ + +#define GPIO_SMTEN_SMTEN8_Pos (8) /*!< GPIO_T::SMTEN: SMTEN8 Position */ +#define GPIO_SMTEN_SMTEN8_Msk (0x1ul << GPIO_SMTEN_SMTEN8_Pos) /*!< GPIO_T::SMTEN: SMTEN8 Mask */ + +#define GPIO_SMTEN_SMTEN9_Pos (9) /*!< GPIO_T::SMTEN: SMTEN9 Position */ +#define GPIO_SMTEN_SMTEN9_Msk (0x1ul << GPIO_SMTEN_SMTEN9_Pos) /*!< GPIO_T::SMTEN: SMTEN9 Mask */ + +#define GPIO_SMTEN_SMTEN10_Pos (10) /*!< GPIO_T::SMTEN: SMTEN10 Position */ +#define GPIO_SMTEN_SMTEN10_Msk (0x1ul << GPIO_SMTEN_SMTEN10_Pos) /*!< GPIO_T::SMTEN: SMTEN10 Mask */ + +#define GPIO_SMTEN_SMTEN11_Pos (11) /*!< GPIO_T::SMTEN: SMTEN11 Position */ +#define GPIO_SMTEN_SMTEN11_Msk (0x1ul << GPIO_SMTEN_SMTEN11_Pos) /*!< GPIO_T::SMTEN: SMTEN11 Mask */ + +#define GPIO_SMTEN_SMTEN12_Pos (12) /*!< GPIO_T::SMTEN: SMTEN12 Position */ +#define GPIO_SMTEN_SMTEN12_Msk (0x1ul << GPIO_SMTEN_SMTEN12_Pos) /*!< GPIO_T::SMTEN: SMTEN12 Mask */ + +#define GPIO_SMTEN_SMTEN13_Pos (13) /*!< GPIO_T::SMTEN: SMTEN13 Position */ +#define GPIO_SMTEN_SMTEN13_Msk (0x1ul << GPIO_SMTEN_SMTEN13_Pos) /*!< GPIO_T::SMTEN: SMTEN13 Mask */ + +#define GPIO_SMTEN_SMTEN14_Pos (14) /*!< GPIO_T::SMTEN: SMTEN14 Position */ +#define GPIO_SMTEN_SMTEN14_Msk (0x1ul << GPIO_SMTEN_SMTEN14_Pos) /*!< GPIO_T::SMTEN: SMTEN14 Mask */ + +#define GPIO_SMTEN_SMTEN15_Pos (15) /*!< GPIO_T::SMTEN: SMTEN15 Position */ +#define GPIO_SMTEN_SMTEN15_Msk (0x1ul << GPIO_SMTEN_SMTEN15_Pos) /*!< GPIO_T::SMTEN: SMTEN15 Mask */ + +#define GPIO_SLEWCTL_HSREN0_Pos (0) /*!< GPIO_T::SLEWCTL: HSREN0 Position */ +#define GPIO_SLEWCTL_HSREN0_Msk (0x3ul << GPIO_SLEWCTL_HSREN0_Pos) /*!< GPIO_T::SLEWCTL: HSREN0 Mask */ + +#define GPIO_SLEWCTL_HSREN1_Pos (2) /*!< GPIO_T::SLEWCTL: HSREN1 Position */ +#define GPIO_SLEWCTL_HSREN1_Msk (0x3ul << GPIO_SLEWCTL_HSREN1_Pos) /*!< GPIO_T::SLEWCTL: HSREN1 Mask */ + +#define GPIO_SLEWCTL_HSREN2_Pos (4) /*!< GPIO_T::SLEWCTL: HSREN2 Position */ +#define GPIO_SLEWCTL_HSREN2_Msk (0x3ul << GPIO_SLEWCTL_HSREN2_Pos) /*!< GPIO_T::SLEWCTL: HSREN2 Mask */ + +#define GPIO_SLEWCTL_HSREN3_Pos (6) /*!< GPIO_T::SLEWCTL: HSREN3 Position */ +#define GPIO_SLEWCTL_HSREN3_Msk (0x3ul << GPIO_SLEWCTL_HSREN3_Pos) /*!< GPIO_T::SLEWCTL: HSREN3 Mask */ + +#define GPIO_SLEWCTL_HSREN4_Pos (8) /*!< GPIO_T::SLEWCTL: HSREN4 Position */ +#define GPIO_SLEWCTL_HSREN4_Msk (0x3ul << GPIO_SLEWCTL_HSREN4_Pos) /*!< GPIO_T::SLEWCTL: HSREN4 Mask */ + +#define GPIO_SLEWCTL_HSREN5_Pos (10) /*!< GPIO_T::SLEWCTL: HSREN5 Position */ +#define GPIO_SLEWCTL_HSREN5_Msk (0x3ul << GPIO_SLEWCTL_HSREN5_Pos) /*!< GPIO_T::SLEWCTL: HSREN5 Mask */ + +#define GPIO_SLEWCTL_HSREN6_Pos (12) /*!< GPIO_T::SLEWCTL: HSREN6 Position */ +#define GPIO_SLEWCTL_HSREN6_Msk (0x3ul << GPIO_SLEWCTL_HSREN6_Pos) /*!< GPIO_T::SLEWCTL: HSREN6 Mask */ + +#define GPIO_SLEWCTL_HSREN7_Pos (14) /*!< GPIO_T::SLEWCTL: HSREN7 Position */ +#define GPIO_SLEWCTL_HSREN7_Msk (0x3ul << GPIO_SLEWCTL_HSREN7_Pos) /*!< GPIO_T::SLEWCTL: HSREN7 Mask */ + +#define GPIO_SLEWCTL_HSREN8_Pos (16) /*!< GPIO_T::SLEWCTL: HSREN8 Position */ +#define GPIO_SLEWCTL_HSREN8_Msk (0x3ul << GPIO_SLEWCTL_HSREN8_Pos) /*!< GPIO_T::SLEWCTL: HSREN8 Mask */ + +#define GPIO_SLEWCTL_HSREN9_Pos (18) /*!< GPIO_T::SLEWCTL: HSREN9 Position */ +#define GPIO_SLEWCTL_HSREN9_Msk (0x3ul << GPIO_SLEWCTL_HSREN9_Pos) /*!< GPIO_T::SLEWCTL: HSREN9 Mask */ + +#define GPIO_SLEWCTL_HSREN10_Pos (20) /*!< GPIO_T::SLEWCTL: HSREN10 Position */ +#define GPIO_SLEWCTL_HSREN10_Msk (0x3ul << GPIO_SLEWCTL_HSREN10_Pos) /*!< GPIO_T::SLEWCTL: HSREN10 Mask */ + +#define GPIO_SLEWCTL_HSREN11_Pos (22) /*!< GPIO_T::SLEWCTL: HSREN11 Position */ +#define GPIO_SLEWCTL_HSREN11_Msk (0x3ul << GPIO_SLEWCTL_HSREN11_Pos) /*!< GPIO_T::SLEWCTL: HSREN11 Mask */ + +#define GPIO_SLEWCTL_HSREN12_Pos (24) /*!< GPIO_T::SLEWCTL: HSREN12 Position */ +#define GPIO_SLEWCTL_HSREN12_Msk (0x3ul << GPIO_SLEWCTL_HSREN12_Pos) /*!< GPIO_T::SLEWCTL: HSREN12 Mask */ + +#define GPIO_SLEWCTL_HSREN13_Pos (26) /*!< GPIO_T::SLEWCTL: HSREN13 Position */ +#define GPIO_SLEWCTL_HSREN13_Msk (0x3ul << GPIO_SLEWCTL_HSREN13_Pos) /*!< GPIO_T::SLEWCTL: HSREN13 Mask */ + +#define GPIO_SLEWCTL_HSREN14_Pos (28) /*!< GPIO_T::SLEWCTL: HSREN14 Position */ +#define GPIO_SLEWCTL_HSREN14_Msk (0x3ul << GPIO_SLEWCTL_HSREN14_Pos) /*!< GPIO_T::SLEWCTL: HSREN14 Mask */ + +#define GPIO_SLEWCTL_HSREN15_Pos (30) /*!< GPIO_T::SLEWCTL: HSREN15 Position */ +#define GPIO_SLEWCTL_HSREN15_Msk (0x3ul << GPIO_SLEWCTL_HSREN15_Pos) /*!< GPIO_T::SLEWCTL: HSREN15 Mask */ + +#define GPIO_PUSEL_PUSEL0_Pos (0) /*!< GPIO_T::PUSEL: PUSEL0 Position */ +#define GPIO_PUSEL_PUSEL0_Msk (0x3ul << GPIO_PUSEL_PUSEL0_Pos) /*!< GPIO_T::PUSEL: PUSEL0 Mask */ + +#define GPIO_PUSEL_PUSEL1_Pos (2) /*!< GPIO_T::PUSEL: PUSEL1 Position */ +#define GPIO_PUSEL_PUSEL1_Msk (0x3ul << GPIO_PUSEL_PUSEL1_Pos) /*!< GPIO_T::PUSEL: PUSEL1 Mask */ + +#define GPIO_PUSEL_PUSEL2_Pos (4) /*!< GPIO_T::PUSEL: PUSEL2 Position */ +#define GPIO_PUSEL_PUSEL2_Msk (0x3ul << GPIO_PUSEL_PUSEL2_Pos) /*!< GPIO_T::PUSEL: PUSEL2 Mask */ + +#define GPIO_PUSEL_PUSEL3_Pos (6) /*!< GPIO_T::PUSEL: PUSEL3 Position */ +#define GPIO_PUSEL_PUSEL3_Msk (0x3ul << GPIO_PUSEL_PUSEL3_Pos) /*!< GPIO_T::PUSEL: PUSEL3 Mask */ + +#define GPIO_PUSEL_PUSEL4_Pos (8) /*!< GPIO_T::PUSEL: PUSEL4 Position */ +#define GPIO_PUSEL_PUSEL4_Msk (0x3ul << GPIO_PUSEL_PUSEL4_Pos) /*!< GPIO_T::PUSEL: PUSEL4 Mask */ + +#define GPIO_PUSEL_PUSEL5_Pos (10) /*!< GPIO_T::PUSEL: PUSEL5 Position */ +#define GPIO_PUSEL_PUSEL5_Msk (0x3ul << GPIO_PUSEL_PUSEL5_Pos) /*!< GPIO_T::PUSEL: PUSEL5 Mask */ + +#define GPIO_PUSEL_PUSEL6_Pos (12) /*!< GPIO_T::PUSEL: PUSEL6 Position */ +#define GPIO_PUSEL_PUSEL6_Msk (0x3ul << GPIO_PUSEL_PUSEL6_Pos) /*!< GPIO_T::PUSEL: PUSEL6 Mask */ + +#define GPIO_PUSEL_PUSEL7_Pos (14) /*!< GPIO_T::PUSEL: PUSEL7 Position */ +#define GPIO_PUSEL_PUSEL7_Msk (0x3ul << GPIO_PUSEL_PUSEL7_Pos) /*!< GPIO_T::PUSEL: PUSEL7 Mask */ + +#define GPIO_PUSEL_PUSEL8_Pos (16) /*!< GPIO_T::PUSEL: PUSEL8 Position */ +#define GPIO_PUSEL_PUSEL8_Msk (0x3ul << GPIO_PUSEL_PUSEL8_Pos) /*!< GPIO_T::PUSEL: PUSEL8 Mask */ + +#define GPIO_PUSEL_PUSEL9_Pos (18) /*!< GPIO_T::PUSEL: PUSEL9 Position */ +#define GPIO_PUSEL_PUSEL9_Msk (0x3ul << GPIO_PUSEL_PUSEL9_Pos) /*!< GPIO_T::PUSEL: PUSEL9 Mask */ + +#define GPIO_PUSEL_PUSEL10_Pos (20) /*!< GPIO_T::PUSEL: PUSEL10 Position */ +#define GPIO_PUSEL_PUSEL10_Msk (0x3ul << GPIO_PUSEL_PUSEL10_Pos) /*!< GPIO_T::PUSEL: PUSEL10 Mask */ + +#define GPIO_PUSEL_PUSEL11_Pos (22) /*!< GPIO_T::PUSEL: PUSEL11 Position */ +#define GPIO_PUSEL_PUSEL11_Msk (0x3ul << GPIO_PUSEL_PUSEL11_Pos) /*!< GPIO_T::PUSEL: PUSEL11 Mask */ + +#define GPIO_PUSEL_PUSEL12_Pos (24) /*!< GPIO_T::PUSEL: PUSEL12 Position */ +#define GPIO_PUSEL_PUSEL12_Msk (0x3ul << GPIO_PUSEL_PUSEL12_Pos) /*!< GPIO_T::PUSEL: PUSEL12 Mask */ + +#define GPIO_PUSEL_PUSEL13_Pos (26) /*!< GPIO_T::PUSEL: PUSEL13 Position */ +#define GPIO_PUSEL_PUSEL13_Msk (0x3ul << GPIO_PUSEL_PUSEL13_Pos) /*!< GPIO_T::PUSEL: PUSEL13 Mask */ + +#define GPIO_PUSEL_PUSEL14_Pos (28) /*!< GPIO_T::PUSEL: PUSEL14 Position */ +#define GPIO_PUSEL_PUSEL14_Msk (0x3ul << GPIO_PUSEL_PUSEL14_Pos) /*!< GPIO_T::PUSEL: PUSEL14 Mask */ + +#define GPIO_PUSEL_PUSEL15_Pos (30) /*!< GPIO_T::PUSEL: PUSEL15 Position */ +#define GPIO_PUSEL_PUSEL15_Msk (0x3ul << GPIO_PUSEL_PUSEL15_Pos) /*!< GPIO_T::PUSEL: PUSEL15 Mask */ + +#define GPIO_DBCTL_DBCLKSEL_Pos (0) /*!< GPIO_T::DBCTL: DBCLKSEL Position */ +#define GPIO_DBCTL_DBCLKSEL_Msk (0xFul << GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO_T::DBCTL: DBCLKSEL Mask */ + +#define GPIO_DBCTL_DBCLKSRC_Pos (4) /*!< GPIO_T::DBCTL: DBCLKSRC Position */ +#define GPIO_DBCTL_DBCLKSRC_Msk (1ul << GPIO_DBCTL_DBCLKSRC_Pos) /*!< GPIO_T::DBCTL: DBCLKSRC Mask */ + +#define GPIO_DBCTL_ICLKON_Pos (5) /*!< GPIO_T::DBCTL: ICLKON Position */ +#define GPIO_DBCTL_ICLKON_Msk (1ul << GPIO_DBCTL_ICLKON_Pos) /*!< GPIO_T::DBCTL: ICLKON Mask */ + +/**@}*/ /* GPIO_CONST */ +/**@}*/ /* end of GPIO register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __GPIO_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/hsotg_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/hsotg_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..52c6a4341558a5e6d296c9921dcd94c9d5a1f220 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/hsotg_reg.h @@ -0,0 +1,398 @@ +/**************************************************************************//** + * @file hsotg_reg.h + * @version V1.00 + * @brief HSOTG register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __HSOTG_REG_H__ +#define __HSOTG_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup HSOTG High Speed USB On-The-Go Controller(HSOTG) + Memory Mapped Structure for HSOTG Controller +@{ */ + +typedef struct +{ + + + /** + * @var HSOTG_T::CTL + * Offset: 0x00 HSOTG Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |VBUSDROP |Drop VBUS Control + * | | |If user application running on this OTG A-device wants to conserve power, set this bit to drop VBUS + * | | |BUSREQ (OTG_CTL[1]) will be also cleared no matter A-device or B-device. + * | | |0 = Not drop the VBUS. + * | | |1 = Drop the VBUS. + * |[1] |BUSREQ |OTG Bus Request + * | | |If OTG A-device wants to do data transfers via USB bus, setting this bit will drive VBUS high to detect USB device connection + * | | |If user won't use the bus any more, clearing this bit will drop VBUS to save power + * | | |This bit will be cleared when A-device goes to A_wait_vfall state + * | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed. + * | | |If user of an OTG-B Device wants to request VBUS, setting this bit will run SRP protocol + * | | |This bit will be cleared if SRP failure (OTG A-device does not provide VBUS after B-device issues ARP in specified interval, defined in OTG specification) + * | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set IDSTS (OTG_STATUS[1]) changed. + * | | |0 = Not launch VBUS in OTG A-device or not request SRP in OTG B-device. + * | | |1 = Launch VBUS in OTG A-device or request SRP in OTG B-device. + * |[2] |HNPREQEN |OTG HNP Request Enable Bit + * | | |When USB frame as A-device, set this bit when A-device allows to process HNP protocol -- A-device changes role from Host to Peripheral + * | | |This bit will be cleared when OTG state changes from a_suspend to a_peripheral or goes back to a_idle state + * | | |When USB frame as B-device, set this bit after the OTG A-device successfully sends a SetFeature (b_hnp_enable) command to the OTG B-device to start role change -- B-device changes role from Peripheral to Host + * | | |This bit will be cleared when OTG state changes from b_peripheral to b_wait_acon or goes back to b_idle state. + * | | |0 = HNP request Disabled. + * | | |1 = HNP request Enabled (A-device can change role from Host to Peripheral or B-device can change role from Peripheral to Host). + * | | |Note: Refer to OTG specification to get a_suspend, a_peripheral, a_idle and b_idle state. + * |[4] |OTGEN |OTG Function Enable Bit + * | | |User needs to set this bit to enable OTG function while USB frame configured as OTG device + * | | |When USB frame not configured as OTG device, this bit is must be low. + * | | |0= OTG function Disabled. + * | | |1 = OTG function Enabled. + * |[5] |WKEN |OTG ID Pin Wake-up Enable Bit + * | | |0 = OTG ID pin status change wake-up function Disabled. + * | | |1 = OTG ID pin status change wake-up function Enabled. + * @var HSOTG_T::PHYCTL + * Offset: 0x04 HSOTG PHY Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |OTGPHYEN |OTG PHY Enable + * | | |When USB frame is configured as OTG-device or ID-dependent, user needs to set this bit before using OTG function + * | | |If device is not configured as OTG-device nor ID-dependent, this bit is "don't care". + * | | |0 = OTG PHY Disabled. + * | | |1 = OTG PHY Enabled. + * |[1] |IDDETEN |ID Detection Enable Bit + * | | |0 = Detect ID pin status Disabled. + * | | |1 = Detect ID pin status Enabled. + * |[4] |VBENPOL |Off-chip USB VBUS Power Switch Enable Polarity + * | | |The OTG controller will enable off-chip USB VBUS power switch to provide VBUS power when need + * | | |A USB_VBUS_EN pin is used to control the off-chip USB VBUS power switch. + * | | |The polarity of enabling off-chip USB VBUS power switch (high active or low active) depends on the selected component + * | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch. + * | | |0 = The off-chip USB VBUS power switch enable is active high. + * | | |1 = The off-chip USB VBUS power switch enable is active low. + * |[5] |VBSTSPOL |Off-chip USB VBUS Power Switch Status Polarity + * | | |The polarity of off-chip USB VBUS power switch valid signal depends on the selected component + * | | |A USB_VBUS_ST pin is used to monitor the valid signal of the off-chip USB VBUS power switch + * | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch. + * | | |0 = The polarity of off-chip USB VBUS power switch valid status is high. + * | | |1 = The polarity of off-chip USB VBUS power switch valid status is low. + * @var HSOTG_T::INTEN + * Offset: 0x08 HSOTG Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ROLECHGIEN|Role (Host or Peripheral) Changed Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[1] |VBEIEN |VBUS Error Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG spec. + * |[2] |SRPFIEN |SRP Fail Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[3] |HNPFIEN |HNP Fail Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[4] |GOIDLEIEN |OTG Device Goes to IDLE State Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Going to idle state means going to a_idle or b_idle state + * | | |Please refer to A-device state diagram and B-device state diagram in OTG spec. + * |[5] |IDCHGIEN |IDSTS Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and IDSTS (OTG_STATUS[1]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[6] |PDEVIEN |Act As Peripheral Interrupt Enable Bit + * | | |If this bit is set to 1 and the device is changed as a peripheral, a interrupt will be asserted. + * | | |0 = This device as a peripheral interrupt Disabled. + * | | |1 = This device as a peripheral interrupt Enabled. + * |[7] |HOSTIEN |Act As Host Interrupt Enable Bit + * | | |If this bit is set to 1 and the device is changed as a host, a interrupt will be asserted. + * | | |0 = This device as a host interrupt Disabled. + * | | |1 = This device as a host interrupt Enabled. + * |[8] |BVLDCHGIEN|B-device Session Valid Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and BVLD (OTG_STATUS[3]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[9] |AVLDCHGIEN|A-device Session Valid Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and AVLD (OTG_STATUS[4]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[10] |VBCHGIEN |VBUSVLD Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and VBUSVLD (OTG_STATUS[5]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[11] |SECHGIEN |SESSEND Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and SESSEND (OTG_STATUS[2]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[13] |SRPDETIEN |SRP Detected Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * @var HSOTG_T::INTSTS + * Offset: 0x0C HSOTG Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ROLECHGIF |OTG Role Change Interrupt Status + * | | |This flag is set when the role of an OTG device changed from a host to a peripheral, or changed from a peripheral to a host while USB_ID pin status does not change. + * | | |0 = OTG device role not changed. + * | | |1 = OTG device role changed. + * | | |Note: Write 1 to clear this flag. + * |[1] |VBEIF |VBUS Error Interrupt Status + * | | |This bit will be set when voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A-device starting to drive VBUS high. + * | | |0 = OTG A-device drives VBUS over threshold voltage before this interval expires. + * | | |1 = OTG A-device cannot drive VBUS over threshold voltage before this interval expires. + * | | |Note: Write 1 to clear this flag and recover from the VBUS error state. + * |[2] |SRPFIF |SRP Fail Interrupt Status + * | | |After initiating SRP, an OTG B-device will wait for the OTG A-device to drive VBUS high at least TB_SRP_FAIL minimum, defined in OTG specification + * | | |This flag is set when the OTG B-device does not get VBUS high after this interval. + * | | |0 = OTG B-device gets VBUS high before this interval. + * | | |1 = OTG B-device does not get VBUS high before this interval. + * | | |Note: Write 1 to clear this flag. + * |[3] |HNPFIF |HNP Fail Interrupt Status + * | | |When A-device has granted B-device to be host and USB bus is in SE0 (both USB_D+ and USB_D- low) state, this bit will be set when A-device does not connect after specified interval expires. + * | | |0 = A-device connects to B-device before specified interval expires. + * | | |1 = A-device does not connect to B-device before specified interval expires. + * | | |Note: Write 1 to clear this flag. + * |[4] |GOIDLEIF |OTG Device Goes to IDLE Interrupt Status + * | | |Flag is set if the OTG device transfers from non-idle state to idle state + * | | |The OTG device will be neither a host nor a peripheral. + * | | |0 = OTG device does not go back to idle state (a_idle or b_idle). + * | | |1 = OTG device goes back to idle state(a_idle or b_idle). + * | | |Note 1: Going to idle state means going to a_idle or b_idle state. Please refer to OTG specification. + * | | |Note 2: Write 1 to clear this flag. + * |[5] |IDCHGIF |ID State Change Interrupt Status + * | | |0 = IDSTS (OTG_STATUS[1]) not toggled. + * | | |1 = IDSTS (OTG_STATUS[1]) from high to low or from low to high. + * | | |Note: Write 1 to clear this flag. + * |[6] |PDEVIF |Act As Peripheral Interrupt Status + * | | |0= This device does not act as a peripheral. + * | | |1 = This device acts as a peripheral. + * | | |Note: Write 1 to clear this flag. + * |[7] |HOSTIF |Act As Host Interrupt Status + * | | |0= This device does not act as a host. + * | | |1 = This device acts as a host. + * | | |Note: Write 1 to clear this flag. + * |[8] |BVLDCHGIF |B-device Session Valid State Change Interrupt Status + * | | |0 = BVLD (OTG_STATUS[3]) is not toggled. + * | | |1 = BVLD (OTG_STATUS[3]) from high to low or low to high. + * | | |Note: Write 1 to clear this status. + * |[9] |AVLDCHGIF |A-device Session Valid State Change Interrupt Status + * | | |0 = AVLD (OTG_STATUS[4]) not toggled. + * | | |1 = AVLD (OTG_STATUS[4]) from high to low or low to high. + * | | |Note: Write 1 to clear this status. + * |[10] |VBCHGIF |VBUSVLD State Change Interrupt Status + * | | |0 = VBUSVLD (OTG_STATUS[5]) not toggled. + * | | |1 = VBUSVLD (OTG_STATUS[5]) from high to low or from low to high. + * | | |Note: Write 1 to clear this status. + * |[11] |SECHGIF |SESSEND State Change Interrupt Status + * | | |0 = SESSEND (OTG_STATUS[2]) not toggled. + * | | |1 = SESSEND (OTG_STATUS[2]) from high to low or from low to high. + * | | |Note: Write 1 to clear this flag. + * |[13] |SRPDETIF |SRP Detected Interrupt Status + * | | |0 = SRP not detected. + * | | |1 = SRP detected. + * | | |Note: Write 1 to clear this status. + * @var HSOTG_T::STATUS + * Offset: 0x10 HSOTG Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |OVERCUR |over Current Condition + * | | |The voltage on VBUS cannot reach a minimum VBUS valid threshold, 4.4V minimum, within a maximum time of 100ms after OTG A-device drives VBUS high. + * | | |0 = OTG A-device drives VBUS successfully. + * | | |1 = OTG A-device cannot drives VBUS high in this interval. + * |[1] |IDSTS |USB_ID Pin State of Mini-b/Micro-plug + * | | |0 = Mini-A/Micro-A plug is attached. + * | | |1 = Mini-B/Micro-B plug is attached. + * |[2] |SESSEND |Session End Status + * | | |When VBUS voltage is lower than 0.4V, this bit will be set to 1 + * | | |Session end means no meaningful power on VBUS. + * | | |0 = Session is not end. + * | | |1 = Session is end. + * |[3] |BVLD |B-device Session Valid Status + * | | |0 = B-device session is not valid. + * | | |1 = B-device session is valid. + * |[4] |AVLD |A-device Session Valid Status + * | | |0 = A-device session is not valid. + * | | |1 = A-device session is valid. + * |[5] |VBUSVLD |VBUS Valid Status + * | | |When VBUS is larger than 4.7V and A-device drives VBUS , this bit will be set to 1. + * | | |0 = VBUS is not valid. + * | | |1 = VBUS is valid. + * |[6] |ASPERI |As Peripheral Status + * | | |When OTG as peripheral, this bit is set. + * | | |0: OTG not as peripheral + * | | |1: OTG as peripheral + * |[7] |ASHOST |As Host Status + * | | |When OTG as Host, this bit is set. + * | | |0: OTG not as Host + * | | |1: OTG as Host + */ + __IO uint32_t CTL; /*!< [0x0000] HSOTG Control Register */ + __IO uint32_t PHYCTL; /*!< [0x0004] HSOTG PHY Control Register */ + __IO uint32_t INTEN; /*!< [0x0008] HSOTG Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x000c] HSOTG Interrupt Status Register */ + __I uint32_t STATUS; /*!< [0x0010] HSOTG Status Register */ + +} HSOTG_T; + +/** + @addtogroup HSOTG_CONST HSOTG Bit Field Definition + Constant Definitions for HSOTG Controller +@{ */ + +#define HSOTG_CTL_VBUSDROP_Pos (0) /*!< HSOTG_T::CTL: VBUSDROP Position */ +#define HSOTG_CTL_VBUSDROP_Msk (0x1ul << HSOTG_CTL_VBUSDROP_Pos) /*!< HSOTG_T::CTL: VBUSDROP Mask */ + +#define HSOTG_CTL_BUSREQ_Pos (1) /*!< HSOTG_T::CTL: BUSREQ Position */ +#define HSOTG_CTL_BUSREQ_Msk (0x1ul << HSOTG_CTL_BUSREQ_Pos) /*!< HSOTG_T::CTL: BUSREQ Mask */ + +#define HSOTG_CTL_HNPREQEN_Pos (2) /*!< HSOTG_T::CTL: HNPREQEN Position */ +#define HSOTG_CTL_HNPREQEN_Msk (0x1ul << HSOTG_CTL_HNPREQEN_Pos) /*!< HSOTG_T::CTL: HNPREQEN Mask */ + +#define HSOTG_CTL_OTGEN_Pos (4) /*!< HSOTG_T::CTL: OTGEN Position */ +#define HSOTG_CTL_OTGEN_Msk (0x1ul << HSOTG_CTL_OTGEN_Pos) /*!< HSOTG_T::CTL: OTGEN Mask */ + +#define HSOTG_CTL_WKEN_Pos (5) /*!< HSOTG_T::CTL: WKEN Position */ +#define HSOTG_CTL_WKEN_Msk (0x1ul << HSOTG_CTL_WKEN_Pos) /*!< HSOTG_T::CTL: WKEN Mask */ + +#define HSOTG_PHYCTL_OTGPHYEN_Pos (0) /*!< HSOTG_T::PHYCTL: OTGPHYEN Position */ +#define HSOTG_PHYCTL_OTGPHYEN_Msk (0x1ul << HSOTG_PHYCTL_OTGPHYEN_Pos) /*!< HSOTG_T::PHYCTL: OTGPHYEN Mask */ + +#define HSOTG_PHYCTL_IDDETEN_Pos (1) /*!< HSOTG_T::PHYCTL: IDDETEN Position */ +#define HSOTG_PHYCTL_IDDETEN_Msk (0x1ul << HSOTG_PHYCTL_IDDETEN_Pos) /*!< HSOTG_T::PHYCTL: IDDETEN Mask */ + +#define HSOTG_PHYCTL_VBENPOL_Pos (4) /*!< HSOTG_T::PHYCTL: VBENPOL Position */ +#define HSOTG_PHYCTL_VBENPOL_Msk (0x1ul << HSOTG_PHYCTL_VBENPOL_Pos) /*!< HSOTG_T::PHYCTL: VBENPOL Mask */ + +#define HSOTG_PHYCTL_VBSTSPOL_Pos (5) /*!< HSOTG_T::PHYCTL: VBSTSPOL Position */ +#define HSOTG_PHYCTL_VBSTSPOL_Msk (0x1ul << HSOTG_PHYCTL_VBSTSPOL_Pos) /*!< HSOTG_T::PHYCTL: VBSTSPOL Mask */ + +#define HSOTG_INTEN_ROLECHGIEN_Pos (0) /*!< HSOTG_T::INTEN: ROLECHGIEN Position */ +#define HSOTG_INTEN_ROLECHGIEN_Msk (0x1ul << HSOTG_INTEN_ROLECHGIEN_Pos) /*!< HSOTG_T::INTEN: ROLECHGIEN Mask */ + +#define HSOTG_INTEN_VBEIEN_Pos (1) /*!< HSOTG_T::INTEN: VBEIEN Position */ +#define HSOTG_INTEN_VBEIEN_Msk (0x1ul << HSOTG_INTEN_VBEIEN_Pos) /*!< HSOTG_T::INTEN: VBEIEN Mask */ + +#define HSOTG_INTEN_SRPFIEN_Pos (2) /*!< HSOTG_T::INTEN: SRPFIEN Position */ +#define HSOTG_INTEN_SRPFIEN_Msk (0x1ul << HSOTG_INTEN_SRPFIEN_Pos) /*!< HSOTG_T::INTEN: SRPFIEN Mask */ + +#define HSOTG_INTEN_HNPFIEN_Pos (3) /*!< HSOTG_T::INTEN: HNPFIEN Position */ +#define HSOTG_INTEN_HNPFIEN_Msk (0x1ul << HSOTG_INTEN_HNPFIEN_Pos) /*!< HSOTG_T::INTEN: HNPFIEN Mask */ + +#define HSOTG_INTEN_GOIDLEIEN_Pos (4) /*!< HSOTG_T::INTEN: GOIDLEIEN Position */ +#define HSOTG_INTEN_GOIDLEIEN_Msk (0x1ul << HSOTG_INTEN_GOIDLEIEN_Pos) /*!< HSOTG_T::INTEN: GOIDLEIEN Mask */ + +#define HSOTG_INTEN_IDCHGIEN_Pos (5) /*!< HSOTG_T::INTEN: IDCHGIEN Position */ +#define HSOTG_INTEN_IDCHGIEN_Msk (0x1ul << HSOTG_INTEN_IDCHGIEN_Pos) /*!< HSOTG_T::INTEN: IDCHGIEN Mask */ + +#define HSOTG_INTEN_PDEVIEN_Pos (6) /*!< HSOTG_T::INTEN: PDEVIEN Position */ +#define HSOTG_INTEN_PDEVIEN_Msk (0x1ul << HSOTG_INTEN_PDEVIEN_Pos) /*!< HSOTG_T::INTEN: PDEVIEN Mask */ + +#define HSOTG_INTEN_HOSTIEN_Pos (7) /*!< HSOTG_T::INTEN: HOSTIEN Position */ +#define HSOTG_INTEN_HOSTIEN_Msk (0x1ul << HSOTG_INTEN_HOSTIEN_Pos) /*!< HSOTG_T::INTEN: HOSTIEN Mask */ + +#define HSOTG_INTEN_BVLDCHGIEN_Pos (8) /*!< HSOTG_T::INTEN: BVLDCHGIEN Position */ +#define HSOTG_INTEN_BVLDCHGIEN_Msk (0x1ul << HSOTG_INTEN_BVLDCHGIEN_Pos) /*!< HSOTG_T::INTEN: BVLDCHGIEN Mask */ + +#define HSOTG_INTEN_AVLDCHGIEN_Pos (9) /*!< HSOTG_T::INTEN: AVLDCHGIEN Position */ +#define HSOTG_INTEN_AVLDCHGIEN_Msk (0x1ul << HSOTG_INTEN_AVLDCHGIEN_Pos) /*!< HSOTG_T::INTEN: AVLDCHGIEN Mask */ + +#define HSOTG_INTEN_VBCHGIEN_Pos (10) /*!< HSOTG_T::INTEN: VBCHGIEN Position */ +#define HSOTG_INTEN_VBCHGIEN_Msk (0x1ul << HSOTG_INTEN_VBCHGIEN_Pos) /*!< HSOTG_T::INTEN: VBCHGIEN Mask */ + +#define HSOTG_INTEN_SECHGIEN_Pos (11) /*!< HSOTG_T::INTEN: SECHGIEN Position */ +#define HSOTG_INTEN_SECHGIEN_Msk (0x1ul << HSOTG_INTEN_SECHGIEN_Pos) /*!< HSOTG_T::INTEN: SECHGIEN Mask */ + +#define HSOTG_INTEN_SRPDETIEN_Pos (13) /*!< HSOTG_T::INTEN: SRPDETIEN Position */ +#define HSOTG_INTEN_SRPDETIEN_Msk (0x1ul << HSOTG_INTEN_SRPDETIEN_Pos) /*!< HSOTG_T::INTEN: SRPDETIEN Mask */ + +#define HSOTG_INTSTS_ROLECHGIF_Pos (0) /*!< HSOTG_T::INTSTS: ROLECHGIF Position */ +#define HSOTG_INTSTS_ROLECHGIF_Msk (0x1ul << HSOTG_INTSTS_ROLECHGIF_Pos) /*!< HSOTG_T::INTSTS: ROLECHGIF Mask */ + +#define HSOTG_INTSTS_VBEIF_Pos (1) /*!< HSOTG_T::INTSTS: VBEIF Position */ +#define HSOTG_INTSTS_VBEIF_Msk (0x1ul << HSOTG_INTSTS_VBEIF_Pos) /*!< HSOTG_T::INTSTS: VBEIF Mask */ + +#define HSOTG_INTSTS_SRPFIF_Pos (2) /*!< HSOTG_T::INTSTS: SRPFIF Position */ +#define HSOTG_INTSTS_SRPFIF_Msk (0x1ul << HSOTG_INTSTS_SRPFIF_Pos) /*!< HSOTG_T::INTSTS: SRPFIF Mask */ + +#define HSOTG_INTSTS_HNPFIF_Pos (3) /*!< HSOTG_T::INTSTS: HNPFIF Position */ +#define HSOTG_INTSTS_HNPFIF_Msk (0x1ul << HSOTG_INTSTS_HNPFIF_Pos) /*!< HSOTG_T::INTSTS: HNPFIF Mask */ + +#define HSOTG_INTSTS_GOIDLEIF_Pos (4) /*!< HSOTG_T::INTSTS: GOIDLEIF Position */ +#define HSOTG_INTSTS_GOIDLEIF_Msk (0x1ul << HSOTG_INTSTS_GOIDLEIF_Pos) /*!< HSOTG_T::INTSTS: GOIDLEIF Mask */ + +#define HSOTG_INTSTS_IDCHGIF_Pos (5) /*!< HSOTG_T::INTSTS: IDCHGIF Position */ +#define HSOTG_INTSTS_IDCHGIF_Msk (0x1ul << HSOTG_INTSTS_IDCHGIF_Pos) /*!< HSOTG_T::INTSTS: IDCHGIF Mask */ + +#define HSOTG_INTSTS_PDEVIF_Pos (6) /*!< HSOTG_T::INTSTS: PDEVIF Position */ +#define HSOTG_INTSTS_PDEVIF_Msk (0x1ul << HSOTG_INTSTS_PDEVIF_Pos) /*!< HSOTG_T::INTSTS: PDEVIF Mask */ + +#define HSOTG_INTSTS_HOSTIF_Pos (7) /*!< HSOTG_T::INTSTS: HOSTIF Position */ +#define HSOTG_INTSTS_HOSTIF_Msk (0x1ul << HSOTG_INTSTS_HOSTIF_Pos) /*!< HSOTG_T::INTSTS: HOSTIF Mask */ + +#define HSOTG_INTSTS_BVLDCHGIF_Pos (8) /*!< HSOTG_T::INTSTS: BVLDCHGIF Position */ +#define HSOTG_INTSTS_BVLDCHGIF_Msk (0x1ul << HSOTG_INTSTS_BVLDCHGIF_Pos) /*!< HSOTG_T::INTSTS: BVLDCHGIF Mask */ + +#define HSOTG_INTSTS_AVLDCHGIF_Pos (9) /*!< HSOTG_T::INTSTS: AVLDCHGIF Position */ +#define HSOTG_INTSTS_AVLDCHGIF_Msk (0x1ul << HSOTG_INTSTS_AVLDCHGIF_Pos) /*!< HSOTG_T::INTSTS: AVLDCHGIF Mask */ + +#define HSOTG_INTSTS_VBCHGIF_Pos (10) /*!< HSOTG_T::INTSTS: VBCHGIF Position */ +#define HSOTG_INTSTS_VBCHGIF_Msk (0x1ul << HSOTG_INTSTS_VBCHGIF_Pos) /*!< HSOTG_T::INTSTS: VBCHGIF Mask */ + +#define HSOTG_INTSTS_SECHGIF_Pos (11) /*!< HSOTG_T::INTSTS: SECHGIF Position */ +#define HSOTG_INTSTS_SECHGIF_Msk (0x1ul << HSOTG_INTSTS_SECHGIF_Pos) /*!< HSOTG_T::INTSTS: SECHGIF Mask */ + +#define HSOTG_INTSTS_SRPDETIF_Pos (13) /*!< HSOTG_T::INTSTS: SRPDETIF Position */ +#define HSOTG_INTSTS_SRPDETIF_Msk (0x1ul << HSOTG_INTSTS_SRPDETIF_Pos) /*!< HSOTG_T::INTSTS: SRPDETIF Mask */ + +#define HSOTG_STATUS_OVERCUR_Pos (0) /*!< HSOTG_T::STATUS: OVERCUR Position */ +#define HSOTG_STATUS_OVERCUR_Msk (0x1ul << HSOTG_STATUS_OVERCUR_Pos) /*!< HSOTG_T::STATUS: OVERCUR Mask */ + +#define HSOTG_STATUS_IDSTS_Pos (1) /*!< HSOTG_T::STATUS: IDSTS Position */ +#define HSOTG_STATUS_IDSTS_Msk (0x1ul << HSOTG_STATUS_IDSTS_Pos) /*!< HSOTG_T::STATUS: IDSTS Mask */ + +#define HSOTG_STATUS_SESSEND_Pos (2) /*!< HSOTG_T::STATUS: SESSEND Position */ +#define HSOTG_STATUS_SESSEND_Msk (0x1ul << HSOTG_STATUS_SESSEND_Pos) /*!< HSOTG_T::STATUS: SESSEND Mask */ + +#define HSOTG_STATUS_BVLD_Pos (3) /*!< HSOTG_T::STATUS: BVLD Position */ +#define HSOTG_STATUS_BVLD_Msk (0x1ul << HSOTG_STATUS_BVLD_Pos) /*!< HSOTG_T::STATUS: BVLD Mask */ + +#define HSOTG_STATUS_AVLD_Pos (4) /*!< HSOTG_T::STATUS: AVLD Position */ +#define HSOTG_STATUS_AVLD_Msk (0x1ul << HSOTG_STATUS_AVLD_Pos) /*!< HSOTG_T::STATUS: AVLD Mask */ + +#define HSOTG_STATUS_VBUSVLD_Pos (5) /*!< HSOTG_T::STATUS: VBUSVLD Position */ +#define HSOTG_STATUS_VBUSVLD_Msk (0x1ul << HSOTG_STATUS_VBUSVLD_Pos) /*!< HSOTG_T::STATUS: VBUSVLD Mask */ + +#define HSOTG_STATUS_ASPERI_Pos (6) /*!< HSOTG_T::STATUS: ASPERI Position */ +#define HSOTG_STATUS_ASPERI_Msk (0x1ul << HSOTG_STATUS_ASPERI_Pos) /*!< HSOTG_T::STATUS: ASPERI Mask */ + +#define HSOTG_STATUS_ASHOST_Pos (7) /*!< HSOTG_T::STATUS: ASHOST Position */ +#define HSOTG_STATUS_ASHOST_Msk (0x1ul << HSOTG_STATUS_ASHOST_Pos) /*!< HSOTG_T::STATUS: ASHOST Mask */ + +/**@}*/ /* HSOTG_CONST */ +/**@}*/ /* end of HSOTG register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __HSOTG_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/hsusbd_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/hsusbd_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..7c30180239722eb84f0acabe0a2fa0a3dddc61dc --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/hsusbd_reg.h @@ -0,0 +1,1381 @@ +/**************************************************************************//** + * @file hsusbd_reg.h + * @version V1.00 + * @brief HSUSBD register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __HSUSBD_REG_H__ +#define __HSUSBD_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup HSUSBD USB 2.0 Device Controller(HSUSBD) + Memory Mapped Structure for HSUSBD Controller +@{ */ + +typedef struct +{ + + /** + * @var HSUSBD_EP_T::EPDAT + * Offset: 0x00 Endpoint n Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |EPDAT |Endpoint A~L Data Register + * | | |Endpoint A~L data buffer for the buffer transaction (read or write). + * | | |Note: Only word access is supported. + * @var HSUSBD_EP_T::EPDAT_BYTE + * Offset: 0x00 Endpoint n Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |EPDAT |Endpoint A~L Data Register + * | | |Endpoint A~L data buffer for the buffer transaction (read or write). + * | | |Note: Only byte access is supported. + * @var HSUSBD_EP_T::EPINTSTS + * Offset: 0x04 Endpoint n Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUFFULLIF |Buffer Full + * | | |For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write) + * | | |For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading). + * | | |0 = The endpoint packet buffer is not full. + * | | |1 = The endpoint packet buffer is full. + * | | |Note: This bit is read-only. + * |[1] |BUFEMPTYIF|Buffer Empty + * | | |For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes. + * | | |0 = The endpoint buffer is not empty. + * | | |1 = The endpoint buffer is empty. + * | | |For an OUT endpoint: + * | | |0 = The currently selected buffer has not a count of 0. + * | | |1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read). + * | | |Note: This bit is read-only. + * |[2] |SHORTTXIF |Short Packet Transferred Interrupt + * | | |0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS). + * | | |1 = The length of the last packet was less than the Maximum Packet Size (EPMPS). + * | | |Note: Write 1 to clear this bit to 0. + * |[3] |TXPKIF |Data Packet Transmitted Interrupt + * | | |0 = Not a data packet is transmitted from the endpoint to the host. + * | | |1 = A data packet is transmitted from the endpoint to the host. + * | | |Note: Write 1 to clear this bit to 0. + * |[4] |RXPKIF |Data Packet Received Interrupt + * | | |0 = No data packet is received from the host by the endpoint. + * | | |1 = A data packet is received from the host by the endpoint. + * | | |Note: Write 1 to clear this bit to 0. + * |[5] |OUTTKIF |Data OUT Token Interrupt + * | | |0 = A Data OUT token has not been received from the host. + * | | |1 = A Data OUT token has been received from the host + * | | |This bit also set by PING token (in high-speed only). + * | | |Note: Write 1 to clear this bit to 0. + * |[6] |INTKIF |Data IN Token Interrupt + * | | |0 = Not Data IN token has been received from the host. + * | | |1 = A Data IN token has been received from the host. + * | | |Note: Write 1 to clear this bit to 0. + * |[7] |PINGIF |PING Token Interrupt + * | | |0 = A Data PING token has not been received from the host. + * | | |1 = A Data PING token has been received from the host. + * | | |Note: Write 1 to clear this bit to 0. + * |[8] |NAKIF |USB NAK Sent + * | | |0 = The last USB IN packet could be provided, and was acknowledged with an ACK. + * | | |1 = The last USB IN packet could not be provided, and was acknowledged with a NAK. + * | | |Note: Write 1 to clear this bit to 0. + * |[9] |STALLIF |USB STALL Sent + * | | |0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL. + * | | |1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL. + * | | |Note: Write 1 to clear this bit to 0. + * |[10] |NYETIF |NYET Sent + * | | |0 = The space available in the RAM is sufficient to accommodate the next on coming data packet. + * | | |1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet. + * | | |Note: Write 1 to clear this bit to 0. + * |[11] |ERRIF |ERR Sent + * | | |0 = No any error in the transaction. + * | | |1 = There occurs any error in the transaction. + * | | |Note: Write 1 to clear this bit to 0. + * |[12] |SHORTRXIF |Bulk Out Short Packet Received + * | | |0 = No bulk out short packet is received. + * | | |1 = Received bulk out short packet (including zero length packet). + * | | |Note: Write 1 to clear this bit to 0. + * @var HSUSBD_EP_T::EPINTEN + * Offset: 0x08 Endpoint n Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUFFULLIEN|Buffer Full Interrupt + * | | |When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus. + * | | |0 = Buffer full interrupt Disabled. + * | | |1 = Buffer full interrupt Enabled. + * |[1] |BUFEMPTYIEN|Buffer Empty Interrupt + * | | |When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus. + * | | |0 = Buffer empty interrupt Disabled. + * | | |1 = Buffer empty interrupt Enabled. + * |[2] |SHORTTXIEN|Short Packet Transferred Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host. + * | | |0 = Short data packet interrupt Disabled. + * | | |1 = Short data packet interrupt Enabled. + * |[3] |TXPKIEN |Data Packet Transmitted Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set when a data packet has been received from the host. + * | | |0 = Data packet has been received from the host interrupt Disabled. + * | | |1 = Data packet has been received from the host interrupt Enabled. + * |[4] |RXPKIEN |Data Packet Received Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host. + * | | |0 = Data packet has been transmitted to the host interrupt Disabled. + * | | |1 = Data packet has been transmitted to the host interrupt Enabled. + * |[5] |OUTTKIEN |Data OUT Token Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host. + * | | |0 = Data OUT token interrupt Disabled. + * | | |1 = Data OUT token interrupt Enabled. + * |[6] |INTKIEN |Data IN Token Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host. + * | | |0 = Data IN token interrupt Disabled. + * | | |1 = Data IN token interrupt Enabled. + * |[7] |PINGIEN |PING Token Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set when a PING token has been received from the host. + * | | |0 = PING token interrupt Disabled. + * | | |1 = PING token interrupt Enabled. + * |[8] |NAKIEN |USB NAK Sent Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set when a NAK token is sent to the host. + * | | |0 = NAK token interrupt Disabled. + * | | |1 = NAK token interrupt Enabled. + * |[9] |STALLIEN |USB STALL Sent Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set when a stall token is sent to the host. + * | | |0 = STALL token interrupt Disabled. + * | | |1 = STALL token interrupt Enabled. + * |[10] |NYETIEN |NYET Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint. + * | | |0 = NYET condition interrupt Disabled. + * | | |1 = NYET condition interrupt Enabled. + * |[11] |ERRIEN |ERR Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint. + * | | |0 = Error event interrupt Disabled. + * | | |1 = Error event interrupt Enabled. + * |[12] |SHORTRXIEN|Bulk Out Short Packet Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint. + * | | |0 = Bulk out interrupt Disabled. + * | | |1 = Bulk out interrupt Enabled. + * @var HSUSBD_EP_T::EPDATCNT + * Offset: 0x0C Endpoint n Data Available Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |DATCNT |Data Count + * | | |For an IN endpoint (EPDIR(USBD_EPxCFG[3] is high.), this register returns the number of valid bytes in the IN endpoint packet buffer. + * | | |For an OUT endpoint (EPDIR(USBD_EPxCFG[3] is low.), this register returns the number of received valid bytes in the Host OUT transfer. + * |[30:16] |DMALOOP |DMA Loop + * | | |This register is the remaining DMA loop to complete. Each loop means 32-byte transfer. + * @var HSUSBD_EP_T::EPRSPCTL + * Offset: 0x10 Endpoint n Response Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FLUSH |Buffer Flush + * | | |Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared + * | | |This bit is self-clearing + * | | |This bit should always be written after an configuration event. + * | | |0 = The packet buffer is not flushed. + * | | |1 = The packet buffer is flushed by user. + * |[2:1] |MODE |Mode Control + * | | |The two bits decide the operation mode of the in-endpoint. + * | | |00: Auto-Validate Mode + * | | |01: Manual-Validate Mode + * | | |10: Fly Mode + * | | |11: Reserved + * | | |These bits are not valid for an out-endpoint + * | | |The auto validate mode will be activated when the reserved mode is selected + * |[3] |TOGGLE |Endpoint Toggle + * | | |This bit is used to clear the endpoint data toggle bit + * | | |Reading this bit returns the current state of the endpoint data toggle bit. + * | | |The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host + * | | |Only when toggle bit is "1", this bit can be written into the inversed write data bit[3]. + * | | |0 = Not clear the endpoint data toggle bit. + * | | |1 = Clear the endpoint data toggle bit. + * |[4] |HALT |Endpoint Halt + * | | |This bit is used to send a STALL handshake as response to the token from the host + * | | |When an Endpoint Set Feature (ep_halt) is detected by the local CPU, it must write a '1' to this bit. + * | | |0 = Not send a STALL handshake as response to the token from the host. + * | | |1 = Send a STALL handshake as response to the token from the host. + * |[5] |ZEROLEN |Zero Length + * | | |This bit is used to send a zero-length packet response to an IN-token + * | | |When this bit is set, a zero packet is sent to the host on reception of an IN-token + * | | |This bit gets cleared once the zero length data packet is sent. + * | | |0 = A zero packet is not sent to the host on reception of an IN-token. + * | | |1 = A zero packet is sent to the host on reception of an IN-token. + * |[6] |SHORTTXEN |Short Packet Transfer Enable + * | | |This bit is applicable only in case of Auto-Validate Method + * | | |This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer + * | | |This bit gets cleared once the data packet is sent. + * | | |0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint. + * | | |1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint. + * |[7] |DISBUF |Buffer Disable Bit + * | | |This bit is used to receive unknown size OUT short packet + * | | |The received packet size is reference USBD_EPxDATCNT register. + * | | |0 = Buffer Not Disabled when Bulk-OUT short packet is received. + * | | |1 = Buffer Disabled when Bulk-OUT short packet is received. + * @var HSUSBD_EP_T::EPMPS + * Offset: 0x14 Endpoint n Maximum Packet Size Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |EPMPS |Endpoint Maximum Packet Size + * | | |This field determines the Maximum Packet Size of the Endpoint. + * @var HSUSBD_EP_T::EPTXCNT + * Offset: 0x18 Endpoint n Transfer Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |TXCNT |Endpoint Transfer Count + * | | |For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method. + * | | |For OUT endpoints, this field has no effect. + * @var HSUSBD_EP_T::EPCFG + * Offset: 0x1C Endpoint n Configuration Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |EPEN |Endpoint Valid + * | | |When set, this bit enables this endpoint + * | | |This bit has no effect on Endpoint 0, which is always enabled. + * | | |0 = The endpoint Disabled. + * | | |1 = The endpoint Enabled. + * |[2:1] |EPTYPE |Endpoint Type + * | | |This field selects the type of this endpoint. Endpoint 0 is forced to a Control type. + * | | |00 = Reserved. + * | | |01 = Bulk. + * | | |10 = Interrupt. + * | | |11 = Isochronous. + * |[3] |EPDIR |Endpoint Direction + * | | |0 = out-endpoint (Host OUT to Device). + * | | |1 = in-endpoint (Host IN to Device). + * | | |Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number. + * |[7:4] |EPNUM |Endpoint Number + * | | |This field selects the number of the endpoint. Valid numbers 1 to 15. + * | | |Note: Do not support two endpoints have same endpoint number. + * @var HSUSBD_EP_T::EPBUFST + * Offset: 0x20 Endpoint n RAM Start Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |SADDR |Endpoint Start Address + * | | |This is the start-address of the RAM space allocated for the endpoint A~L. + * @var HSUSBD_EP_T::EPBUFEND + * Offset: 0x24 Endpoint n RAM End Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |EADDR |Endpoint End Address + * | | |This is the end-address of the RAM space allocated for the endpoint A~L. + */ + + union + { + __IO uint32_t EPDAT; + __IO uint8_t EPDAT_BYTE; + + }; /*!< [0x0000] Endpoint n Data Register */ + + __IO uint32_t EPINTSTS; /*!< [0x0004] Endpoint n Interrupt Status Register */ + __IO uint32_t EPINTEN; /*!< [0x0008] Endpoint n Interrupt Enable Register */ + __I uint32_t EPDATCNT; /*!< [0x000c] Endpoint n Data Available Count Register */ + __IO uint32_t EPRSPCTL; /*!< [0x0010] Endpoint n Response Control Register */ + __IO uint32_t EPMPS; /*!< [0x0014] Endpoint n Maximum Packet Size Register */ + __IO uint32_t EPTXCNT; /*!< [0x0018] Endpoint n Transfer Count Register */ + __IO uint32_t EPCFG; /*!< [0x001c] Endpoint n Configuration Register */ + __IO uint32_t EPBUFST; /*!< [0x0020] Endpoint n RAM Start Address Register */ + __IO uint32_t EPBUFEND; /*!< [0x0024] Endpoint n RAM End Address Register */ + +} HSUSBD_EP_T; + +typedef struct +{ + + /** + * @var HSUSBD_T::GINTSTS + * Offset: 0x00 Global Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |USBIF |USB Interrupt + * | | |This bit conveys the interrupt status for USB specific events endpoint + * | | |When set, USB interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[1] |CEPIF |Control Endpoint Interrupt + * | | |This bit conveys the interrupt status for control endpoint + * | | |When set, Control-ep's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[2] |EPAIF |Endpoint a Interrupt + * | | |When set, the corresponding Endpoint A's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[3] |EPBIF |Endpoint B Interrupt + * | | |When set, the corresponding Endpoint B's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[4] |EPCIF |Endpoint C Interrupt + * | | |When set, the corresponding Endpoint C's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[5] |EPDIF |Endpoint D Interrupt + * | | |When set, the corresponding Endpoint D's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[6] |EPEIF |Endpoint E Interrupt + * | | |When set, the corresponding Endpoint E's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[7] |EPFIF |Endpoint F Interrupt + * | | |When set, the corresponding Endpoint F's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[8] |EPGIF |Endpoint G Interrupt + * | | |When set, the corresponding Endpoint G's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[9] |EPHIF |Endpoint H Interrupt + * | | |When set, the corresponding Endpoint H's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[10] |EPIIF |Endpoint I Interrupt + * | | |When set, the corresponding Endpoint I's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[11] |EPJIF |Endpoint J Interrupt + * | | |When set, the corresponding Endpoint J's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[12] |EPKIF |Endpoint K Interrupt + * | | |When set, the corresponding Endpoint K's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[13] |EPLIF |Endpoint L Interrupt + * | | |When set, the corresponding Endpoint L's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * @var HSUSBD_T::GINTEN + * Offset: 0x08 Global Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |USBIEN |USB Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be generated when a USB event occurs on the bus. + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[1] |CEPIEN |Control Endpoint Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the control endpoint. + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[2] |EPAIEN |Interrupt Enable Control for Endpoint a + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint A. + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[3] |EPBIEN |Interrupt Enable Control for Endpoint B + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint B + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[4] |EPCIEN |Interrupt Enable Control for Endpoint C + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint C + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[5] |EPDIEN |Interrupt Enable Control for Endpoint D + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint D + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[6] |EPEIEN |Interrupt Enable Control for Endpoint E + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint E + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[7] |EPFIEN |Interrupt Enable Control for Endpoint F + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint F + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[8] |EPGIEN |Interrupt Enable Control for Endpoint G + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint G + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[9] |EPHIEN |Interrupt Enable Control for Endpoint H + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint H + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[10] |EPIIEN |Interrupt Enable Control for Endpoint I + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint I + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[11] |EPJIEN |Interrupt Enable Control for Endpoint J + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint J + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[12] |EPKIEN |Interrupt Enable Control for Endpoint K + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint K + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[13] |EPLIEN |Interrupt Enable Control for Endpoint L + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint L + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * @var HSUSBD_T::BUSINTSTS + * Offset: 0x10 USB Bus Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SOFIF |SOF Receive Control + * | | |This bit indicates when a start-of-frame packet has been received. + * | | |0 = No start-of-frame packet has been received. + * | | |1 = Start-of-frame packet has been received. + * | | |Note: Write 1 to clear this bit to 0. + * |[1] |RSTIF |Reset Status + * | | |When set, this bit indicates that either the USB root port reset is end. + * | | |0 = No USB root port reset is end. + * | | |1 = USB root port reset is end. + * | | |Note: Write 1 to clear this bit to 0. + * |[2] |RESUMEIF |Resume + * | | |When set, this bit indicates that a device resume has occurred. + * | | |0 = No device resume has occurred. + * | | |1 = Device resume has occurred. + * | | |Note: Write 1 to clear this bit to 0. + * |[3] |SUSPENDIF |Suspend Request + * | | |This bit is set as default and it has to be cleared by writing '1' before the USB reset + * | | |This bit is also set when a USB Suspend request is detected from the host. + * | | |0 = No USB Suspend request is detected from the host. + * | | |1= USB Suspend request is detected from the host. + * | | |Note: Write 1 to clear this bit to 0. + * |[4] |HISPDIF |High-speed Settle + * | | |0 = No valid high-speed reset protocol is detected. + * | | |1 = Valid high-speed reset protocol is over and the device has settled in high-speed. + * | | |Note: Write 1 to clear this bit to 0. + * |[5] |DMADONEIF |DMA Completion Interrupt + * | | |0 = No DMA transfer over. + * | | |1 = DMA transfer is over. + * | | |Note: Write 1 to clear this bit to 0. + * |[6] |PHYCLKVLDIF|Usable Clock Interrupt + * | | |0 = Usable clock is not available. + * | | |1 = Usable clock is available from the transceiver. + * | | |Note: Write 1 to clear this bit to 0. + * |[8] |VBUSDETIF |VBUS Detection Interrupt Status + * | | |0 = No VBUS is plug-in. + * | | |1 = VBUS is plug-in. + * | | |Note: Write 1 to clear this bit to 0. + * @var HSUSBD_T::BUSINTEN + * Offset: 0x14 USB Bus Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SOFIEN |SOF Interrupt + * | | |This bit enables the SOF interrupt. + * | | |0 = SOF interrupt Disabled. + * | | |1 = SOF interrupt Enabled. + * |[1] |RSTIEN |Reset Status + * | | |This bit enables the USB-Reset interrupt. + * | | |0 = USB-Reset interrupt Disabled. + * | | |1 = USB-Reset interrupt Enabled. + * |[2] |RESUMEIEN |Resume + * | | |This bit enables the Resume interrupt. + * | | |0 = Resume interrupt Disabled. + * | | |1 = Resume interrupt Enabled. + * |[3] |SUSPENDIEN|Suspend Request + * | | |This bit enables the Suspend interrupt. + * | | |0 = Suspend interrupt Disabled. + * | | |1 = Suspend interrupt Enabled. + * |[4] |HISPDIEN |High-speed Settle + * | | |This bit enables the high-speed settle interrupt. + * | | |0 = High-speed settle interrupt Disabled. + * | | |1 = High-speed settle interrupt Enabled. + * |[5] |DMADONEIEN|DMA Completion Interrupt + * | | |This bit enables the DMA completion interrupt + * | | |0 = DMA completion interrupt Disabled. + * | | |1 = DMA completion interrupt Enabled. + * |[6] |PHYCLKVLDIEN|Usable Clock Interrupt + * | | |This bit enables the usable clock interrupt. + * | | |0 = Usable clock interrupt Disabled. + * | | |1 = Usable clock interrupt Enabled. + * |[8] |VBUSDETIEN|VBUS Detection Interrupt Enable Bit + * | | |This bit enables the VBUS floating detection interrupt. + * | | |0 = VBUS floating detection interrupt Disabled. + * | | |1 = VBUS floating detection interrupt Enabled. + * @var HSUSBD_T::OPER + * Offset: 0x18 USB Operational Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RESUMEEN |Generate Resume + * | | |0 = No Resume sequence to be initiated to the host. + * | | |1 = A Resume sequence to be initiated to the host if device remote wakeup is enabled + * | | |This bit is self-clearing. + * |[1] |HISPDEN |USB High-speed + * | | |0 = The USB device controller to suppress the chirp-sequence during reset protocol, thereby allowing the USB device controller to settle in full-speed, even though it is connected to a USB2.0 Host. + * | | |1 = The USB device controller to initiate a chirp-sequence during reset protocol. + * |[2] |CURSPD |USB Current Speed + * | | |0 = The device has settled in Full Speed. + * | | |1 = The USB device controller has settled in High-speed. + * @var HSUSBD_T::FRAMECNT + * Offset: 0x1C USB Frame Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |MFRAMECNT |Micro-frame Counter + * | | |This field contains the micro-frame number for the frame number in the frame counter field. + * |[13:3] |FRAMECNT |Frame Counter + * | | |This field contains the frame count from the most recent start-of-frame packet. + * @var HSUSBD_T::FADDR + * Offset: 0x20 USB Function Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |FADDR |USB Function Address + * | | |This field contains the current USB address of the device + * | | |This field is cleared when a root port reset is detected + * @var HSUSBD_T::TEST + * Offset: 0x24 USB Test Mode Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |TESTMODE |Test Mode Selection + * | | |000 = Normal Operation. + * | | |001 = Test_J. + * | | |010 = Test_K. + * | | |011 = Test_SE0_NAK. + * | | |100 = Test_Packet. + * | | |101 = Test_Force_Enable. + * | | |110 = Reserved. + * | | |111 = Reserved. + * | | |Note: This field is cleared when root port reset is detected. + * @var HSUSBD_T::CEPDAT + * Offset: 0x28 Control-Endpoint Data Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DAT |Control-endpoint Data Buffer + * | | |Control endpoint data buffer for the buffer transaction (read or write). + * | | |Note: Only word access is supported. + * @var HSUSBD_T::CEPDAT_BYTE + * Offset: 0x28 Control-Endpoint Data Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DAT |Control-endpoint Data Buffer + * | | |Control endpoint data buffer for the buffer transaction (read or write). + * | | |Note: Only byte access is supported. + * @var HSUSBD_T::CEPCTL + * Offset: 0x2C Control-Endpoint Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |NAKCLR |No Acknowledge Control + * | | |This bit plays a crucial role in any control transfer. + * | | |0 = The bit is being cleared by the local CPU by writing zero, the USB device controller will be responding with NAKs for the subsequent status phase + * | | |This mechanism holds the host from moving to the next request, until the local CPU is also ready to process the next request. + * | | |1 = This bit is set to one by the USB device controller, whenever a setup token is received + * | | |The local CPU can take its own time to finish off any house-keeping work based on the request and then clear this bit. + * | | |Note: Only when CPU writes data[1:0] is 2'b10 or 2'b00, this bit can be updated. + * |[1] |STALLEN |Stall Enable Bit + * | | |When this stall bit is set, the control endpoint sends a stall handshake in response to any in or out token thereafter + * | | |This is typically used for response to invalid/unsupported requests + * | | |When this bit is being set the NAK clear bit has to be cleared at the same time since the NAK clear bit has highest priority than STALL + * | | |It is automatically cleared on receipt of a next setup-token + * | | |So, the local CPU need not write again to clear this bit. + * | | |0 = No sends a stall handshake in response to any in or out token thereafter. + * | | |1 = The control endpoint sends a stall handshake in response to any in or out token thereafter. + * | | |Note: Only when CPU writes data[1:0] is 2'b10 or 2'b00, this bit can be updated. + * |[2] |ZEROLEN |Zero Packet Length + * | | |This bit is valid for Auto Validation mode only. + * | | |0 = No zero length packet to the host during Data stage to an IN token. + * | | |1 = USB device controller can send a zero length packet to the host during Data stage to an IN token + * | | |This bit gets cleared once the zero length data packet is sent + * | | |So, the local CPU need not write again to clear this bit. + * |[3] |FLUSH |CEP-flush Bit + * | | |0 = No the packet buffer and its corresponding USBD_CEPDATCNT register to be cleared. + * | | |1 = The packet buffer and its corresponding USBD_CEPDATCNT register to be cleared + * | | |This bit is self-cleaning. + * @var HSUSBD_T::CEPINTEN + * Offset: 0x30 Control-Endpoint Interrupt Enable + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SETUPTKIEN|Setup Token Interrupt Enable Bit + * | | |0 = The SETUP token interrupt in Control Endpoint Disabled. + * | | |1 = The SETUP token interrupt in Control Endpoint Enabled. + * |[1] |SETUPPKIEN|Setup Packet Interrupt + * | | |0 = The SETUP packet interrupt in Control Endpoint Disabled. + * | | |1 = The SETUP packet interrupt in Control Endpoint Enabled. + * |[2] |OUTTKIEN |Out Token Interrupt + * | | |0 = The OUT token interrupt in Control Endpoint Disabled. + * | | |1 = The OUT token interrupt in Control Endpoint Enabled. + * |[3] |INTKIEN |In Token Interrupt + * | | |0 = The IN token interrupt in Control Endpoint Disabled. + * | | |1 = The IN token interrupt in Control Endpoint Enabled. + * |[4] |PINGIEN |Ping Token Interrupt + * | | |0 = The ping token interrupt in Control Endpoint Disabled. + * | | |1 = The ping token interrupt Control Endpoint Enabled. + * |[5] |TXPKIEN |Data Packet Transmitted Interrupt + * | | |0 = The data packet transmitted interrupt in Control Endpoint Disabled. + * | | |1 = The data packet transmitted interrupt in Control Endpoint Enabled. + * |[6] |RXPKIEN |Data Packet Received Interrupt + * | | |0 = The data received interrupt in Control Endpoint Disabled. + * | | |1 = The data received interrupt in Control Endpoint Enabled. + * |[7] |NAKIEN |NAK Sent Interrupt + * | | |0 = The NAK sent interrupt in Control Endpoint Disabled. + * | | |1 = The NAK sent interrupt in Control Endpoint Enabled. + * |[8] |STALLIEN |STALL Sent Interrupt + * | | |0 = The STALL sent interrupt in Control Endpoint Disabled. + * | | |1 = The STALL sent interrupt in Control Endpoint Enabled. + * |[9] |ERRIEN |USB Error Interrupt + * | | |0 = The USB Error interrupt in Control Endpoint Disabled. + * | | |1 = The USB Error interrupt in Control Endpoint Enabled. + * |[10] |STSDONEIEN|Status Completion Interrupt + * | | |0 = The Status Completion interrupt in Control Endpoint Disabled. + * | | |1 = The Status Completion interrupt in Control Endpoint Enabled. + * |[11] |BUFFULLIEN|Buffer Full Interrupt + * | | |0 = The buffer full interrupt in Control Endpoint Disabled. + * | | |1 = The buffer full interrupt in Control Endpoint Enabled. + * |[12] |BUFEMPTYIEN|Buffer Empty Interrupt + * | | |0 = The buffer empty interrupt in Control Endpoint Disabled. + * | | |1= The buffer empty interrupt in Control Endpoint Enabled. + * @var HSUSBD_T::CEPINTSTS + * Offset: 0x34 Control-Endpoint Interrupt Status + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SETUPTKIF |Setup Token Interrupt + * | | |0 = Not a Setup token is received. + * | | |1 = A Setup token is received. Writing 1 clears this status bit + * | | |Note: Write 1 to clear this bit to 0. + * |[1] |SETUPPKIF |Setup Packet Interrupt + * | | |This bit must be cleared (by writing 1) before the next setup packet can be received + * | | |If the bit is not cleared, then the successive setup packets will be overwritten in the setup packet buffer. + * | | |0 = Not a Setup packet has been received from the host. + * | | |1 = A Setup packet has been received from the host. + * | | |Note: Write 1 to clear this bit to 0. + * |[2] |OUTTKIF |Out Token Interrupt + * | | |0 = The control-endpoint does not received an OUT token from the host. + * | | |1 = The control-endpoint receives an OUT token from the host. + * | | |Note: Write 1 to clear this bit to 0. + * |[3] |INTKIF |in Token Interrupt + * | | |0 = The control-endpoint does not received an IN token from the host. + * | | |1 = The control-endpoint receives an IN token from the host. + * | | |Note: Write 1 to clear this bit to 0. + * |[4] |PINGIF |Ping Token Interrupt + * | | |0 = The control-endpoint does not received a ping token from the host. + * | | |1 = The control-endpoint receives a ping token from the host. + * | | |Note: Write 1 to clear this bit to 0. + * |[5] |TXPKIF |Data Packet Transmitted Interrupt + * | | |0 = Not a data packet is successfully transmitted to the host in response to an IN-token and an ACK-token is received for the same. + * | | |1 = A data packet is successfully transmitted to the host in response to an IN-token and an ACK-token is received for the same. + * | | |Note: Write 1 to clear this bit to 0. + * |[6] |RXPKIF |Data Packet Received Interrupt + * | | |0 = Not a data packet is successfully received from the host for an OUT-token and an ACK is sent to the host. + * | | |1 = A data packet is successfully received from the host for an OUT-token and an ACK is sent to the host. + * | | |Note: Write 1 to clear this bit to 0. + * |[7] |NAKIF |NAK Sent Interrupt + * | | |0 = Not a NAK-token is sent in response to an IN/OUT token. + * | | |1 = A NAK-token is sent in response to an IN/OUT token. + * | | |Note: Write 1 to clear this bit to 0. + * |[8] |STALLIF |STALL Sent Interrupt + * | | |0 = Not a stall-token is sent in response to an IN/OUT token. + * | | |1 = A stall-token is sent in response to an IN/OUT token. + * | | |Note: Write 1 to clear this bit to 0. + * |[9] |ERRIF |USB Error Interrupt + * | | |0 = No error had occurred during the transaction. + * | | |1 = An error had occurred during the transaction. + * | | |Note: Write 1 to clear this bit to 0. + * |[10] |STSDONEIF |Status Completion Interrupt + * | | |0 = Not a USB transaction has completed successfully. + * | | |1 = The status stage of a USB transaction has completed successfully. + * | | |Note: Write 1 to clear this bit to 0. + * |[11] |BUFFULLIF |Buffer Full Interrupt + * | | |0 = The control-endpoint buffer is not full. + * | | |1 = The control-endpoint buffer is full. + * | | |Note: Write 1 to clear this bit to 0. + * |[12] |BUFEMPTYIF|Buffer Empty Interrupt + * | | |0 = The control-endpoint buffer is not empty. + * | | |1 = The control-endpoint buffer is empty. + * | | |Note: Write 1 to clear this bit to 0. + * @var HSUSBD_T::CEPTXCNT + * Offset: 0x38 Control-Endpoint In-transfer Data Count + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |TXCNT |In-transfer Data Count + * | | |There is no mode selection for the control endpoint (but it operates like manual mode).The local-CPU has to fill the control-endpoint buffer with the data to be sent for an in-token and to write the count of bytes in this register + * | | |When zero is written into this field, a zero length packet is sent to the host + * | | |When the count written in the register is more than the MPS, the data sent will be of only MPS. + * @var HSUSBD_T::CEPRXCNT + * Offset: 0x3C Control-Endpoint Out-transfer Data Count + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |RXCNT |Out-transfer Data Count + * | | |The USB device controller maintains the count of the data received in case of an out transfer, during the control transfer. + * @var HSUSBD_T::CEPDATCNT + * Offset: 0x40 Control-Endpoint data count + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |DATCNT |Control-endpoint Data Count + * | | |The USB device controller maintains the count of the data of control-endpoint. + * @var HSUSBD_T::SETUP1_0 + * Offset: 0x44 Setup1 & Setup0 bytes + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SETUP0 |Setup Byte 0[7:0] + * | | |This register provides byte 0 of the last setup packet received + * | | |For a Standard Device Request, the following bmRequestType information is returned. + * | | |Bit 7(Direction): + * | | | 0: Host to device + * | | | 1: Device to host + * | | |Bit 6-5 (Type): + * | | | 00: Standard + * | | | 01: Class + * | | | 10: Vendor + * | | | 11: Reserved + * | | |Bit 4-0 (Recipient) + * | | | 00000: Device + * | | | 00001: Interface + * | | | 00010: Endpoint + * | | | 00011: Other + * | | | Others: Reserved + * |[15:8] |SETUP1 |Setup Byte 1[15:8] + * | | |This register provides byte 1 of the last setup packet received + * | | |For a Standard Device Request, the following bRequest Code information is returned. + * | | |00000000 = Get Status. + * | | |00000001 = Clear Feature. + * | | |00000010 = Reserved. + * | | |00000011 = Set Feature. + * | | |00000100 = Reserved. + * | | |00000101 = Set Address. + * | | |00000110 = Get Descriptor. + * | | |00000111 = Set Descriptor. + * | | |00001000 = Get Configuration. + * | | |00001001 = Set Configuration. + * | | |00001010 = Get Interface. + * | | |00001011 = Set Interface. + * | | |00001100 = Sync Frame. + * @var HSUSBD_T::SETUP3_2 + * Offset: 0x48 Setup3 & Setup2 Bytes + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SETUP2 |Setup Byte 2 [7:0] + * | | |This register provides byte 2 of the last setup packet received + * | | |For a Standard Device Request, the least significant byte of the wValue field is returned + * |[15:8] |SETUP3 |Setup Byte 3 [15:8] + * | | |This register provides byte 3 of the last setup packet received + * | | |For a Standard Device Request, the most significant byte of the wValue field is returned. + * @var HSUSBD_T::SETUP5_4 + * Offset: 0x4C Setup5 & Setup4 Bytes + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SETUP4 |Setup Byte 4[7:0] + * | | |This register provides byte 4 of the last setup packet received + * | | |For a Standard Device Request, the least significant byte of the wIndex is returned. + * |[15:8] |SETUP5 |Setup Byte 5[15:8] + * | | |This register provides byte 5 of the last setup packet received + * | | |For a Standard Device Request, the most significant byte of the wIndex field is returned. + * @var HSUSBD_T::SETUP7_6 + * Offset: 0x50 Setup7 & Setup6 Bytes + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SETUP6 |Setup Byte 6[7:0] + * | | |This register provides byte 6 of the last setup packet received + * | | |For a Standard Device Request, the least significant byte of the wLength field is returned. + * |[15:8] |SETUP7 |Setup Byte 7[15:8] + * | | |This register provides byte 7 of the last setup packet received + * | | |For a Standard Device Request, the most significant byte of the wLength field is returned. + * @var HSUSBD_T::CEPBUFST + * Offset: 0x54 Control Endpoint RAM Start Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |SADDR |Control-endpoint Start Address + * | | |This is the start-address of the RAM space allocated for the control-endpoint. + * @var HSUSBD_T::CEPBUFEND + * Offset: 0x58 Control Endpoint RAM End Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |EADDR |Control-endpoint End Address + * | | |This is the end-address of the RAM space allocated for the control-endpoint. + * @var HSUSBD_T::DMACTL + * Offset: 0x5C DMA Control Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |EPNUM |DMA Endpoint Address Bits + * | | |Used to define the Endpoint Address + * |[4] |DMARD |DMA Operation + * | | |0 : The operation is a DMA write (read from USB buffer) + * | | |DMA will check endpoint data available count (USBD_EPxDATCNT) according to EPNM setting before to perform DMA write operation. + * | | |1 : The operation is a DMA read (write to USB buffer). + * |[5] |DMAEN |DMA Enable Bit + * | | |0 : DMA function Disabled. + * | | |1 : DMA function Enabled. + * |[6] |SGEN |Scatter Gather Function Enable Bit + * | | |0 : Scatter gather function Disabled. + * | | |1 : Scatter gather function Enabled. + * |[7] |DMARST |Reset DMA State Machine + * | | |0 : No reset the DMA state machine. + * | | |1 : Reset the DMA state machine. + * |[8] |SVINEP |Serve IN Endpoint + * | | |This bit is used to specify DMA serving endpoint-IN endpoint or OUT endpoint. + * | | |0: DMA serves OUT endpoint + * | | |1: DMA serves IN endpoint + * @var HSUSBD_T::DMACNT + * Offset: 0x60 DMA Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[19:0] |DMACNT |DMA Transfer Count + * | | |The transfer count of the DMA operation to be performed is written to this register. + * @var HSUSBD_T::DMAADDR + * Offset: 0x700 AHB DMA Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DMAADDR |DMAADDR + * | | |The register specifies the address from which the DMA has to read / write + * | | |The address must WORD (32-bit) aligned. + * @var HSUSBD_T::PHYCTL + * Offset: 0x704 USB PHY Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8] |DPPUEN |DP Pull-up + * | | |0 = Pull-up resistor on D+ Disabled. + * | | |1 = Pull-up resistor on D+ Enabled. + * |[9] |PHYEN |PHY Suspend Enable Bit + * | | |0 = The USB PHY is suspend. + * | | |1 = The USB PHY is not suspend. + * |[24] |WKEN |Wake-up Enable Bit + * | | |0 = The wake-up function Disabled. + * | | |1 = The wake-up function Enabled. + * |[31] |VBUSDET |VBUS Status + * | | |0 = The VBUS is not detected yet. + * | | |1 = The VBUS is detected. + */ + + __I uint32_t GINTSTS; /*!< [0x0000] Global Interrupt Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t GINTEN; /*!< [0x0008] Global Interrupt Enable Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t BUSINTSTS; /*!< [0x0010] USB Bus Interrupt Status Register */ + __IO uint32_t BUSINTEN; /*!< [0x0014] USB Bus Interrupt Enable Register */ + __IO uint32_t OPER; /*!< [0x0018] USB Operational Register */ + __I uint32_t FRAMECNT; /*!< [0x001c] USB Frame Count Register */ + __IO uint32_t FADDR; /*!< [0x0020] USB Function Address Register */ + __IO uint32_t TEST; /*!< [0x0024] USB Test Mode Register */ + + union + { + __IO uint32_t CEPDAT; + __IO uint8_t CEPDAT_BYTE; + + }; /*!< [0x0028] Control-Endpoint Data Buffer */ + + __IO uint32_t CEPCTL; /*!< [0x002c] Control-Endpoint Control Register */ + __IO uint32_t CEPINTEN; /*!< [0x0030] Control-Endpoint Interrupt Enable */ + __IO uint32_t CEPINTSTS; /*!< [0x0034] Control-Endpoint Interrupt Status */ + __IO uint32_t CEPTXCNT; /*!< [0x0038] Control-Endpoint In-transfer Data Count */ + __I uint32_t CEPRXCNT; /*!< [0x003c] Control-Endpoint Out-transfer Data Count */ + __I uint32_t CEPDATCNT; /*!< [0x0040] Control-Endpoint data count */ + __I uint32_t SETUP1_0; /*!< [0x0044] Setup1 & Setup0 bytes */ + __I uint32_t SETUP3_2; /*!< [0x0048] Setup3 & Setup2 Bytes */ + __I uint32_t SETUP5_4; /*!< [0x004c] Setup5 & Setup4 Bytes */ + __I uint32_t SETUP7_6; /*!< [0x0050] Setup7 & Setup6 Bytes */ + __IO uint32_t CEPBUFST; /*!< [0x0054] Control Endpoint RAM Start Address Register */ + __IO uint32_t CEPBUFEND; /*!< [0x0058] Control Endpoint RAM End Address Register */ + __IO uint32_t DMACTL; /*!< [0x005c] DMA Control Status Register */ + __IO uint32_t DMACNT; /*!< [0x0060] DMA Count Register */ + + HSUSBD_EP_T EP[12]; + + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[303]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t DMAADDR; /*!< [0x0700] AHB DMA Address Register */ + __IO uint32_t PHYCTL; /*!< [0x0704] USB PHY Control Register */ + +} HSUSBD_T; + +/** + @addtogroup HSUSBD_CONST HSUSBD Bit Field Definition + Constant Definitions for HSUSBD Controller +@{ */ + +#define HSUSBD_GINTSTS_USBIF_Pos (0) /*!< HSUSBD_T::GINTSTS: USBIF Position */ +#define HSUSBD_GINTSTS_USBIF_Msk (0x1ul << HSUSBD_GINTSTS_USBIF_Pos) /*!< HSUSBD_T::GINTSTS: USBIF Mask */ + +#define HSUSBD_GINTSTS_CEPIF_Pos (1) /*!< HSUSBD_T::GINTSTS: CEPIF Position */ +#define HSUSBD_GINTSTS_CEPIF_Msk (0x1ul << HSUSBD_GINTSTS_CEPIF_Pos) /*!< HSUSBD_T::GINTSTS: CEPIF Mask */ + +#define HSUSBD_GINTSTS_EPAIF_Pos (2) /*!< HSUSBD_T::GINTSTS: EPAIF Position */ +#define HSUSBD_GINTSTS_EPAIF_Msk (0x1ul << HSUSBD_GINTSTS_EPAIF_Pos) /*!< HSUSBD_T::GINTSTS: EPAIF Mask */ + +#define HSUSBD_GINTSTS_EPBIF_Pos (3) /*!< HSUSBD_T::GINTSTS: EPBIF Position */ +#define HSUSBD_GINTSTS_EPBIF_Msk (0x1ul << HSUSBD_GINTSTS_EPBIF_Pos) /*!< HSUSBD_T::GINTSTS: EPBIF Mask */ + +#define HSUSBD_GINTSTS_EPCIF_Pos (4) /*!< HSUSBD_T::GINTSTS: EPCIF Position */ +#define HSUSBD_GINTSTS_EPCIF_Msk (0x1ul << HSUSBD_GINTSTS_EPCIF_Pos) /*!< HSUSBD_T::GINTSTS: EPCIF Mask */ + +#define HSUSBD_GINTSTS_EPDIF_Pos (5) /*!< HSUSBD_T::GINTSTS: EPDIF Position */ +#define HSUSBD_GINTSTS_EPDIF_Msk (0x1ul << HSUSBD_GINTSTS_EPDIF_Pos) /*!< HSUSBD_T::GINTSTS: EPDIF Mask */ + +#define HSUSBD_GINTSTS_EPEIF_Pos (6) /*!< HSUSBD_T::GINTSTS: EPEIF Position */ +#define HSUSBD_GINTSTS_EPEIF_Msk (0x1ul << HSUSBD_GINTSTS_EPEIF_Pos) /*!< HSUSBD_T::GINTSTS: EPEIF Mask */ + +#define HSUSBD_GINTSTS_EPFIF_Pos (7) /*!< HSUSBD_T::GINTSTS: EPFIF Position */ +#define HSUSBD_GINTSTS_EPFIF_Msk (0x1ul << HSUSBD_GINTSTS_EPFIF_Pos) /*!< HSUSBD_T::GINTSTS: EPFIF Mask */ + +#define HSUSBD_GINTSTS_EPGIF_Pos (8) /*!< HSUSBD_T::GINTSTS: EPGIF Position */ +#define HSUSBD_GINTSTS_EPGIF_Msk (0x1ul << HSUSBD_GINTSTS_EPGIF_Pos) /*!< HSUSBD_T::GINTSTS: EPGIF Mask */ + +#define HSUSBD_GINTSTS_EPHIF_Pos (9) /*!< HSUSBD_T::GINTSTS: EPHIF Position */ +#define HSUSBD_GINTSTS_EPHIF_Msk (0x1ul << HSUSBD_GINTSTS_EPHIF_Pos) /*!< HSUSBD_T::GINTSTS: EPHIF Mask */ + +#define HSUSBD_GINTSTS_EPIIF_Pos (10) /*!< HSUSBD_T::GINTSTS: EPIIF Position */ +#define HSUSBD_GINTSTS_EPIIF_Msk (0x1ul << HSUSBD_GINTSTS_EPIIF_Pos) /*!< HSUSBD_T::GINTSTS: EPIIF Mask */ + +#define HSUSBD_GINTSTS_EPJIF_Pos (11) /*!< HSUSBD_T::GINTSTS: EPJIF Position */ +#define HSUSBD_GINTSTS_EPJIF_Msk (0x1ul << HSUSBD_GINTSTS_EPJIF_Pos) /*!< HSUSBD_T::GINTSTS: EPJIF Mask */ + +#define HSUSBD_GINTSTS_EPKIF_Pos (12) /*!< HSUSBD_T::GINTSTS: EPKIF Position */ +#define HSUSBD_GINTSTS_EPKIF_Msk (0x1ul << HSUSBD_GINTSTS_EPKIF_Pos) /*!< HSUSBD_T::GINTSTS: EPKIF Mask */ + +#define HSUSBD_GINTSTS_EPLIF_Pos (13) /*!< HSUSBD_T::GINTSTS: EPLIF Position */ +#define HSUSBD_GINTSTS_EPLIF_Msk (0x1ul << HSUSBD_GINTSTS_EPLIF_Pos) /*!< HSUSBD_T::GINTSTS: EPLIF Mask */ + +#define HSUSBD_GINTEN_USBIEN_Pos (0) /*!< HSUSBD_T::GINTEN: USBIEN Position */ +#define HSUSBD_GINTEN_USBIEN_Msk (0x1ul << HSUSBD_GINTEN_USBIEN_Pos) /*!< HSUSBD_T::GINTEN: USBIEN Mask */ + +#define HSUSBD_GINTEN_CEPIEN_Pos (1) /*!< HSUSBD_T::GINTEN: CEPIEN Position */ +#define HSUSBD_GINTEN_CEPIEN_Msk (0x1ul << HSUSBD_GINTEN_CEPIEN_Pos) /*!< HSUSBD_T::GINTEN: CEPIEN Mask */ + +#define HSUSBD_GINTEN_EPAIEN_Pos (2) /*!< HSUSBD_T::GINTEN: EPAIEN Position */ +#define HSUSBD_GINTEN_EPAIEN_Msk (0x1ul << HSUSBD_GINTEN_EPAIEN_Pos) /*!< HSUSBD_T::GINTEN: EPAIEN Mask */ + +#define HSUSBD_GINTEN_EPBIEN_Pos (3) /*!< HSUSBD_T::GINTEN: EPBIEN Position */ +#define HSUSBD_GINTEN_EPBIEN_Msk (0x1ul << HSUSBD_GINTEN_EPBIEN_Pos) /*!< HSUSBD_T::GINTEN: EPBIEN Mask */ + +#define HSUSBD_GINTEN_EPCIEN_Pos (4) /*!< HSUSBD_T::GINTEN: EPCIEN Position */ +#define HSUSBD_GINTEN_EPCIEN_Msk (0x1ul << HSUSBD_GINTEN_EPCIEN_Pos) /*!< HSUSBD_T::GINTEN: EPCIEN Mask */ + +#define HSUSBD_GINTEN_EPDIEN_Pos (5) /*!< HSUSBD_T::GINTEN: EPDIEN Position */ +#define HSUSBD_GINTEN_EPDIEN_Msk (0x1ul << HSUSBD_GINTEN_EPDIEN_Pos) /*!< HSUSBD_T::GINTEN: EPDIEN Mask */ + +#define HSUSBD_GINTEN_EPEIEN_Pos (6) /*!< HSUSBD_T::GINTEN: EPEIEN Position */ +#define HSUSBD_GINTEN_EPEIEN_Msk (0x1ul << HSUSBD_GINTEN_EPEIEN_Pos) /*!< HSUSBD_T::GINTEN: EPEIEN Mask */ + +#define HSUSBD_GINTEN_EPFIEN_Pos (7) /*!< HSUSBD_T::GINTEN: EPFIEN Position */ +#define HSUSBD_GINTEN_EPFIEN_Msk (0x1ul << HSUSBD_GINTEN_EPFIEN_Pos) /*!< HSUSBD_T::GINTEN: EPFIEN Mask */ + +#define HSUSBD_GINTEN_EPGIEN_Pos (8) /*!< HSUSBD_T::GINTEN: EPGIEN Position */ +#define HSUSBD_GINTEN_EPGIEN_Msk (0x1ul << HSUSBD_GINTEN_EPGIEN_Pos) /*!< HSUSBD_T::GINTEN: EPGIEN Mask */ + +#define HSUSBD_GINTEN_EPHIEN_Pos (9) /*!< HSUSBD_T::GINTEN: EPHIEN Position */ +#define HSUSBD_GINTEN_EPHIEN_Msk (0x1ul << HSUSBD_GINTEN_EPHIEN_Pos) /*!< HSUSBD_T::GINTEN: EPHIEN Mask */ + +#define HSUSBD_GINTEN_EPIIEN_Pos (10) /*!< HSUSBD_T::GINTEN: EPIIEN Position */ +#define HSUSBD_GINTEN_EPIIEN_Msk (0x1ul << HSUSBD_GINTEN_EPIIEN_Pos) /*!< HSUSBD_T::GINTEN: EPIIEN Mask */ + +#define HSUSBD_GINTEN_EPJIEN_Pos (11) /*!< HSUSBD_T::GINTEN: EPJIEN Position */ +#define HSUSBD_GINTEN_EPJIEN_Msk (0x1ul << HSUSBD_GINTEN_EPJIEN_Pos) /*!< HSUSBD_T::GINTEN: EPJIEN Mask */ + +#define HSUSBD_GINTEN_EPKIEN_Pos (12) /*!< HSUSBD_T::GINTEN: EPKIEN Position */ +#define HSUSBD_GINTEN_EPKIEN_Msk (0x1ul << HSUSBD_GINTEN_EPKIEN_Pos) /*!< HSUSBD_T::GINTEN: EPKIEN Mask */ + +#define HSUSBD_GINTEN_EPLIEN_Pos (13) /*!< HSUSBD_T::GINTEN: EPLIEN Position */ +#define HSUSBD_GINTEN_EPLIEN_Msk (0x1ul << HSUSBD_GINTEN_EPLIEN_Pos) /*!< HSUSBD_T::GINTEN: EPLIEN Mask */ + +#define HSUSBD_BUSINTSTS_SOFIF_Pos (0) /*!< HSUSBD_T::BUSINTSTS: SOFIF Position */ +#define HSUSBD_BUSINTSTS_SOFIF_Msk (0x1ul << HSUSBD_BUSINTSTS_SOFIF_Pos) /*!< HSUSBD_T::BUSINTSTS: SOFIF Mask */ + +#define HSUSBD_BUSINTSTS_RSTIF_Pos (1) /*!< HSUSBD_T::BUSINTSTS: RSTIF Position */ +#define HSUSBD_BUSINTSTS_RSTIF_Msk (0x1ul << HSUSBD_BUSINTSTS_RSTIF_Pos) /*!< HSUSBD_T::BUSINTSTS: RSTIF Mask */ + +#define HSUSBD_BUSINTSTS_RESUMEIF_Pos (2) /*!< HSUSBD_T::BUSINTSTS: RESUMEIF Position */ +#define HSUSBD_BUSINTSTS_RESUMEIF_Msk (0x1ul << HSUSBD_BUSINTSTS_RESUMEIF_Pos) /*!< HSUSBD_T::BUSINTSTS: RESUMEIF Mask */ + +#define HSUSBD_BUSINTSTS_SUSPENDIF_Pos (3) /*!< HSUSBD_T::BUSINTSTS: SUSPENDIF Position*/ +#define HSUSBD_BUSINTSTS_SUSPENDIF_Msk (0x1ul << HSUSBD_BUSINTSTS_SUSPENDIF_Pos) /*!< HSUSBD_T::BUSINTSTS: SUSPENDIF Mask */ + +#define HSUSBD_BUSINTSTS_HISPDIF_Pos (4) /*!< HSUSBD_T::BUSINTSTS: HISPDIF Position */ +#define HSUSBD_BUSINTSTS_HISPDIF_Msk (0x1ul << HSUSBD_BUSINTSTS_HISPDIF_Pos) /*!< HSUSBD_T::BUSINTSTS: HISPDIF Mask */ + +#define HSUSBD_BUSINTSTS_DMADONEIF_Pos (5) /*!< HSUSBD_T::BUSINTSTS: DMADONEIF Position*/ +#define HSUSBD_BUSINTSTS_DMADONEIF_Msk (0x1ul << HSUSBD_BUSINTSTS_DMADONEIF_Pos) /*!< HSUSBD_T::BUSINTSTS: DMADONEIF Mask */ + +#define HSUSBD_BUSINTSTS_PHYCLKVLDIF_Pos (6) /*!< HSUSBD_T::BUSINTSTS: PHYCLKVLDIF Position*/ +#define HSUSBD_BUSINTSTS_PHYCLKVLDIF_Msk (0x1ul << HSUSBD_BUSINTSTS_PHYCLKVLDIF_Pos) /*!< HSUSBD_T::BUSINTSTS: PHYCLKVLDIF Mask */ + +#define HSUSBD_BUSINTSTS_VBUSDETIF_Pos (8) /*!< HSUSBD_T::BUSINTSTS: VBUSDETIF Position*/ +#define HSUSBD_BUSINTSTS_VBUSDETIF_Msk (0x1ul << HSUSBD_BUSINTSTS_VBUSDETIF_Pos) /*!< HSUSBD_T::BUSINTSTS: VBUSDETIF Mask */ + +#define HSUSBD_BUSINTEN_SOFIEN_Pos (0) /*!< HSUSBD_T::BUSINTEN: SOFIEN Position */ +#define HSUSBD_BUSINTEN_SOFIEN_Msk (0x1ul << HSUSBD_BUSINTEN_SOFIEN_Pos) /*!< HSUSBD_T::BUSINTEN: SOFIEN Mask */ + +#define HSUSBD_BUSINTEN_RSTIEN_Pos (1) /*!< HSUSBD_T::BUSINTEN: RSTIEN Position */ +#define HSUSBD_BUSINTEN_RSTIEN_Msk (0x1ul << HSUSBD_BUSINTEN_RSTIEN_Pos) /*!< HSUSBD_T::BUSINTEN: RSTIEN Mask */ + +#define HSUSBD_BUSINTEN_RESUMEIEN_Pos (2) /*!< HSUSBD_T::BUSINTEN: RESUMEIEN Position */ +#define HSUSBD_BUSINTEN_RESUMEIEN_Msk (0x1ul << HSUSBD_BUSINTEN_RESUMEIEN_Pos) /*!< HSUSBD_T::BUSINTEN: RESUMEIEN Mask */ + +#define HSUSBD_BUSINTEN_SUSPENDIEN_Pos (3) /*!< HSUSBD_T::BUSINTEN: SUSPENDIEN Position*/ +#define HSUSBD_BUSINTEN_SUSPENDIEN_Msk (0x1ul << HSUSBD_BUSINTEN_SUSPENDIEN_Pos) /*!< HSUSBD_T::BUSINTEN: SUSPENDIEN Mask */ + +#define HSUSBD_BUSINTEN_HISPDIEN_Pos (4) /*!< HSUSBD_T::BUSINTEN: HISPDIEN Position */ +#define HSUSBD_BUSINTEN_HISPDIEN_Msk (0x1ul << HSUSBD_BUSINTEN_HISPDIEN_Pos) /*!< HSUSBD_T::BUSINTEN: HISPDIEN Mask */ + +#define HSUSBD_BUSINTEN_DMADONEIEN_Pos (5) /*!< HSUSBD_T::BUSINTEN: DMADONEIEN Position*/ +#define HSUSBD_BUSINTEN_DMADONEIEN_Msk (0x1ul << HSUSBD_BUSINTEN_DMADONEIEN_Pos) /*!< HSUSBD_T::BUSINTEN: DMADONEIEN Mask */ + +#define HSUSBD_BUSINTEN_PHYCLKVLDIEN_Pos (6) /*!< HSUSBD_T::BUSINTEN: PHYCLKVLDIEN Position*/ +#define HSUSBD_BUSINTEN_PHYCLKVLDIEN_Msk (0x1ul << HSUSBD_BUSINTEN_PHYCLKVLDIEN_Pos) /*!< HSUSBD_T::BUSINTEN: PHYCLKVLDIEN Mask */ + +#define HSUSBD_BUSINTEN_VBUSDETIEN_Pos (8) /*!< HSUSBD_T::BUSINTEN: VBUSDETIEN Position*/ +#define HSUSBD_BUSINTEN_VBUSDETIEN_Msk (0x1ul << HSUSBD_BUSINTEN_VBUSDETIEN_Pos) /*!< HSUSBD_T::BUSINTEN: VBUSDETIEN Mask */ + +#define HSUSBD_OPER_RESUMEEN_Pos (0) /*!< HSUSBD_T::OPER: RESUMEEN Position */ +#define HSUSBD_OPER_RESUMEEN_Msk (0x1ul << HSUSBD_OPER_RESUMEEN_Pos) /*!< HSUSBD_T::OPER: RESUMEEN Mask */ + +#define HSUSBD_OPER_HISPDEN_Pos (1) /*!< HSUSBD_T::OPER: HISPDEN Position */ +#define HSUSBD_OPER_HISPDEN_Msk (0x1ul << HSUSBD_OPER_HISPDEN_Pos) /*!< HSUSBD_T::OPER: HISPDEN Mask */ + +#define HSUSBD_OPER_CURSPD_Pos (2) /*!< HSUSBD_T::OPER: CURSPD Position */ +#define HSUSBD_OPER_CURSPD_Msk (0x1ul << HSUSBD_OPER_CURSPD_Pos) /*!< HSUSBD_T::OPER: CURSPD Mask */ + +#define HSUSBD_FRAMECNT_MFRAMECNT_Pos (0) /*!< HSUSBD_T::FRAMECNT: MFRAMECNT Position */ +#define HSUSBD_FRAMECNT_MFRAMECNT_Msk (0x7ul << HSUSBD_FRAMECNT_MFRAMECNT_Pos) /*!< HSUSBD_T::FRAMECNT: MFRAMECNT Mask */ + +#define HSUSBD_FRAMECNT_FRAMECNT_Pos (3) /*!< HSUSBD_T::FRAMECNT: FRAMECNT Position */ +#define HSUSBD_FRAMECNT_FRAMECNT_Msk (0x7fful << HSUSBD_FRAMECNT_FRAMECNT_Pos) /*!< HSUSBD_T::FRAMECNT: FRAMECNT Mask */ + +#define HSUSBD_FADDR_FADDR_Pos (0) /*!< HSUSBD_T::FADDR: FADDR Position */ +#define HSUSBD_FADDR_FADDR_Msk (0x7ful << HSUSBD_FADDR_FADDR_Pos) /*!< HSUSBD_T::FADDR: FADDR Mask */ + +#define HSUSBD_TEST_TESTMODE_Pos (0) /*!< HSUSBD_T::TEST: TESTMODE Position */ +#define HSUSBD_TEST_TESTMODE_Msk (0x7ul << HSUSBD_TEST_TESTMODE_Pos) /*!< HSUSBD_T::TEST: TESTMODE Mask */ + +#define HSUSBD_CEPDAT_DAT_Pos (0) /*!< HSUSBD_T::CEPDAT: DAT Position */ +#define HSUSBD_CEPDAT_DAT_Msk (0xfffffffful << HSUSBD_CEPDAT_DAT_Pos) /*!< HSUSBD_T::CEPDAT: DAT Mask */ + +#define HSUSBD_CEPCTL_NAKCLR_Pos (0) /*!< HSUSBD_T::CEPCTL: NAKCLR Position */ +#define HSUSBD_CEPCTL_NAKCLR_Msk (0x1ul << HSUSBD_CEPCTL_NAKCLR_Pos) /*!< HSUSBD_T::CEPCTL: NAKCLR Mask */ + +#define HSUSBD_CEPCTL_STALLEN_Pos (1) /*!< HSUSBD_T::CEPCTL: STALLEN Position */ +#define HSUSBD_CEPCTL_STALLEN_Msk (0x1ul << HSUSBD_CEPCTL_STALLEN_Pos) /*!< HSUSBD_T::CEPCTL: STALLEN Mask */ + +#define HSUSBD_CEPCTL_ZEROLEN_Pos (2) /*!< HSUSBD_T::CEPCTL: ZEROLEN Position */ +#define HSUSBD_CEPCTL_ZEROLEN_Msk (0x1ul << HSUSBD_CEPCTL_ZEROLEN_Pos) /*!< HSUSBD_T::CEPCTL: ZEROLEN Mask */ + +#define HSUSBD_CEPCTL_FLUSH_Pos (3) /*!< HSUSBD_T::CEPCTL: FLUSH Position */ +#define HSUSBD_CEPCTL_FLUSH_Msk (0x1ul << HSUSBD_CEPCTL_FLUSH_Pos) /*!< HSUSBD_T::CEPCTL: FLUSH Mask */ + +#define HSUSBD_CEPINTEN_SETUPTKIEN_Pos (0) /*!< HSUSBD_T::CEPINTEN: SETUPTKIEN Position*/ +#define HSUSBD_CEPINTEN_SETUPTKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_SETUPTKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: SETUPTKIEN Mask */ + +#define HSUSBD_CEPINTEN_SETUPPKIEN_Pos (1) /*!< HSUSBD_T::CEPINTEN: SETUPPKIEN Position*/ +#define HSUSBD_CEPINTEN_SETUPPKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_SETUPPKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: SETUPPKIEN Mask */ + +#define HSUSBD_CEPINTEN_OUTTKIEN_Pos (2) /*!< HSUSBD_T::CEPINTEN: OUTTKIEN Position */ +#define HSUSBD_CEPINTEN_OUTTKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_OUTTKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: OUTTKIEN Mask */ + +#define HSUSBD_CEPINTEN_INTKIEN_Pos (3) /*!< HSUSBD_T::CEPINTEN: INTKIEN Position */ +#define HSUSBD_CEPINTEN_INTKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_INTKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: INTKIEN Mask */ + +#define HSUSBD_CEPINTEN_PINGIEN_Pos (4) /*!< HSUSBD_T::CEPINTEN: PINGIEN Position */ +#define HSUSBD_CEPINTEN_PINGIEN_Msk (0x1ul << HSUSBD_CEPINTEN_PINGIEN_Pos) /*!< HSUSBD_T::CEPINTEN: PINGIEN Mask */ + +#define HSUSBD_CEPINTEN_TXPKIEN_Pos (5) /*!< HSUSBD_T::CEPINTEN: TXPKIEN Position */ +#define HSUSBD_CEPINTEN_TXPKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_TXPKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: TXPKIEN Mask */ + +#define HSUSBD_CEPINTEN_RXPKIEN_Pos (6) /*!< HSUSBD_T::CEPINTEN: RXPKIEN Position */ +#define HSUSBD_CEPINTEN_RXPKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_RXPKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: RXPKIEN Mask */ + +#define HSUSBD_CEPINTEN_NAKIEN_Pos (7) /*!< HSUSBD_T::CEPINTEN: NAKIEN Position */ +#define HSUSBD_CEPINTEN_NAKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_NAKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: NAKIEN Mask */ + +#define HSUSBD_CEPINTEN_STALLIEN_Pos (8) /*!< HSUSBD_T::CEPINTEN: STALLIEN Position */ +#define HSUSBD_CEPINTEN_STALLIEN_Msk (0x1ul << HSUSBD_CEPINTEN_STALLIEN_Pos) /*!< HSUSBD_T::CEPINTEN: STALLIEN Mask */ + +#define HSUSBD_CEPINTEN_ERRIEN_Pos (9) /*!< HSUSBD_T::CEPINTEN: ERRIEN Position */ +#define HSUSBD_CEPINTEN_ERRIEN_Msk (0x1ul << HSUSBD_CEPINTEN_ERRIEN_Pos) /*!< HSUSBD_T::CEPINTEN: ERRIEN Mask */ + +#define HSUSBD_CEPINTEN_STSDONEIEN_Pos (10) /*!< HSUSBD_T::CEPINTEN: STSDONEIEN Position*/ +#define HSUSBD_CEPINTEN_STSDONEIEN_Msk (0x1ul << HSUSBD_CEPINTEN_STSDONEIEN_Pos) /*!< HSUSBD_T::CEPINTEN: STSDONEIEN Mask */ + +#define HSUSBD_CEPINTEN_BUFFULLIEN_Pos (11) /*!< HSUSBD_T::CEPINTEN: BUFFULLIEN Position*/ +#define HSUSBD_CEPINTEN_BUFFULLIEN_Msk (0x1ul << HSUSBD_CEPINTEN_BUFFULLIEN_Pos) /*!< HSUSBD_T::CEPINTEN: BUFFULLIEN Mask */ + +#define HSUSBD_CEPINTEN_BUFEMPTYIEN_Pos (12) /*!< HSUSBD_T::CEPINTEN: BUFEMPTYIEN Position*/ +#define HSUSBD_CEPINTEN_BUFEMPTYIEN_Msk (0x1ul << HSUSBD_CEPINTEN_BUFEMPTYIEN_Pos) /*!< HSUSBD_T::CEPINTEN: BUFEMPTYIEN Mask */ + +#define HSUSBD_CEPINTSTS_SETUPTKIF_Pos (0) /*!< HSUSBD_T::CEPINTSTS: SETUPTKIF Position*/ +#define HSUSBD_CEPINTSTS_SETUPTKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_SETUPTKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: SETUPTKIF Mask */ + +#define HSUSBD_CEPINTSTS_SETUPPKIF_Pos (1) /*!< HSUSBD_T::CEPINTSTS: SETUPPKIF Position*/ +#define HSUSBD_CEPINTSTS_SETUPPKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_SETUPPKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: SETUPPKIF Mask */ + +#define HSUSBD_CEPINTSTS_OUTTKIF_Pos (2) /*!< HSUSBD_T::CEPINTSTS: OUTTKIF Position */ +#define HSUSBD_CEPINTSTS_OUTTKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_OUTTKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: OUTTKIF Mask */ + +#define HSUSBD_CEPINTSTS_INTKIF_Pos (3) /*!< HSUSBD_T::CEPINTSTS: INTKIF Position */ +#define HSUSBD_CEPINTSTS_INTKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_INTKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: INTKIF Mask */ + +#define HSUSBD_CEPINTSTS_PINGIF_Pos (4) /*!< HSUSBD_T::CEPINTSTS: PINGIF Position */ +#define HSUSBD_CEPINTSTS_PINGIF_Msk (0x1ul << HSUSBD_CEPINTSTS_PINGIF_Pos) /*!< HSUSBD_T::CEPINTSTS: PINGIF Mask */ + +#define HSUSBD_CEPINTSTS_TXPKIF_Pos (5) /*!< HSUSBD_T::CEPINTSTS: TXPKIF Position */ +#define HSUSBD_CEPINTSTS_TXPKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_TXPKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: TXPKIF Mask */ + +#define HSUSBD_CEPINTSTS_RXPKIF_Pos (6) /*!< HSUSBD_T::CEPINTSTS: RXPKIF Position */ +#define HSUSBD_CEPINTSTS_RXPKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_RXPKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: RXPKIF Mask */ + +#define HSUSBD_CEPINTSTS_NAKIF_Pos (7) /*!< HSUSBD_T::CEPINTSTS: NAKIF Position */ +#define HSUSBD_CEPINTSTS_NAKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_NAKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: NAKIF Mask */ + +#define HSUSBD_CEPINTSTS_STALLIF_Pos (8) /*!< HSUSBD_T::CEPINTSTS: STALLIF Position */ +#define HSUSBD_CEPINTSTS_STALLIF_Msk (0x1ul << HSUSBD_CEPINTSTS_STALLIF_Pos) /*!< HSUSBD_T::CEPINTSTS: STALLIF Mask */ + +#define HSUSBD_CEPINTSTS_ERRIF_Pos (9) /*!< HSUSBD_T::CEPINTSTS: ERRIF Position */ +#define HSUSBD_CEPINTSTS_ERRIF_Msk (0x1ul << HSUSBD_CEPINTSTS_ERRIF_Pos) /*!< HSUSBD_T::CEPINTSTS: ERRIF Mask */ + +#define HSUSBD_CEPINTSTS_STSDONEIF_Pos (10) /*!< HSUSBD_T::CEPINTSTS: STSDONEIF Position*/ +#define HSUSBD_CEPINTSTS_STSDONEIF_Msk (0x1ul << HSUSBD_CEPINTSTS_STSDONEIF_Pos) /*!< HSUSBD_T::CEPINTSTS: STSDONEIF Mask */ + +#define HSUSBD_CEPINTSTS_BUFFULLIF_Pos (11) /*!< HSUSBD_T::CEPINTSTS: BUFFULLIF Position*/ +#define HSUSBD_CEPINTSTS_BUFFULLIF_Msk (0x1ul << HSUSBD_CEPINTSTS_BUFFULLIF_Pos) /*!< HSUSBD_T::CEPINTSTS: BUFFULLIF Mask */ + +#define HSUSBD_CEPINTSTS_BUFEMPTYIF_Pos (12) /*!< HSUSBD_T::CEPINTSTS: BUFEMPTYIF Position*/ +#define HSUSBD_CEPINTSTS_BUFEMPTYIF_Msk (0x1ul << HSUSBD_CEPINTSTS_BUFEMPTYIF_Pos) /*!< HSUSBD_T::CEPINTSTS: BUFEMPTYIF Mask */ + +#define HSUSBD_CEPTXCNT_TXCNT_Pos (0) /*!< HSUSBD_T::CEPTXCNT: TXCNT Position */ +#define HSUSBD_CEPTXCNT_TXCNT_Msk (0xfful << HSUSBD_CEPTXCNT_TXCNT_Pos) /*!< HSUSBD_T::CEPTXCNT: TXCNT Mask */ + +#define HSUSBD_CEPRXCNT_RXCNT_Pos (0) /*!< HSUSBD_T::CEPRXCNT: RXCNT Position */ +#define HSUSBD_CEPRXCNT_RXCNT_Msk (0xfful << HSUSBD_CEPRXCNT_RXCNT_Pos) /*!< HSUSBD_T::CEPRXCNT: RXCNT Mask */ + +#define HSUSBD_CEPDATCNT_DATCNT_Pos (0) /*!< HSUSBD_T::CEPDATCNT: DATCNT Position */ +#define HSUSBD_CEPDATCNT_DATCNT_Msk (0xfffful << HSUSBD_CEPDATCNT_DATCNT_Pos) /*!< HSUSBD_T::CEPDATCNT: DATCNT Mask */ + +#define HSUSBD_SETUP1_0_SETUP0_Pos (0) /*!< HSUSBD_T::SETUP1_0: SETUP0 Position */ +#define HSUSBD_SETUP1_0_SETUP0_Msk (0xfful << HSUSBD_SETUP1_0_SETUP0_Pos) /*!< HSUSBD_T::SETUP1_0: SETUP0 Mask */ + +#define HSUSBD_SETUP1_0_SETUP1_Pos (8) /*!< HSUSBD_T::SETUP1_0: SETUP1 Position */ +#define HSUSBD_SETUP1_0_SETUP1_Msk (0xfful << HSUSBD_SETUP1_0_SETUP1_Pos) /*!< HSUSBD_T::SETUP1_0: SETUP1 Mask */ + +#define HSUSBD_SETUP3_2_SETUP2_Pos (0) /*!< HSUSBD_T::SETUP3_2: SETUP2 Position */ +#define HSUSBD_SETUP3_2_SETUP2_Msk (0xfful << HSUSBD_SETUP3_2_SETUP2_Pos) /*!< HSUSBD_T::SETUP3_2: SETUP2 Mask */ + +#define HSUSBD_SETUP3_2_SETUP3_Pos (8) /*!< HSUSBD_T::SETUP3_2: SETUP3 Position */ +#define HSUSBD_SETUP3_2_SETUP3_Msk (0xfful << HSUSBD_SETUP3_2_SETUP3_Pos) /*!< HSUSBD_T::SETUP3_2: SETUP3 Mask */ + +#define HSUSBD_SETUP5_4_SETUP4_Pos (0) /*!< HSUSBD_T::SETUP5_4: SETUP4 Position */ +#define HSUSBD_SETUP5_4_SETUP4_Msk (0xfful << HSUSBD_SETUP5_4_SETUP4_Pos) /*!< HSUSBD_T::SETUP5_4: SETUP4 Mask */ + +#define HSUSBD_SETUP5_4_SETUP5_Pos (8) /*!< HSUSBD_T::SETUP5_4: SETUP5 Position */ +#define HSUSBD_SETUP5_4_SETUP5_Msk (0xfful << HSUSBD_SETUP5_4_SETUP5_Pos) /*!< HSUSBD_T::SETUP5_4: SETUP5 Mask */ + +#define HSUSBD_SETUP7_6_SETUP6_Pos (0) /*!< HSUSBD_T::SETUP7_6: SETUP6 Position */ +#define HSUSBD_SETUP7_6_SETUP6_Msk (0xfful << HSUSBD_SETUP7_6_SETUP6_Pos) /*!< HSUSBD_T::SETUP7_6: SETUP6 Mask */ + +#define HSUSBD_SETUP7_6_SETUP7_Pos (8) /*!< HSUSBD_T::SETUP7_6: SETUP7 Position */ +#define HSUSBD_SETUP7_6_SETUP7_Msk (0xfful << HSUSBD_SETUP7_6_SETUP7_Pos) /*!< HSUSBD_T::SETUP7_6: SETUP7 Mask */ + +#define HSUSBD_CEPBUFST_SADDR_Pos (0) /*!< HSUSBD_T::CEPBUFST: SADDR Position */ +#define HSUSBD_CEPBUFST_SADDR_Msk (0xffful << HSUSBD_CEPBUFST_SADDR_Pos) /*!< HSUSBD_T::CEPBUFST: SADDR Mask */ + +#define HSUSBD_CEPBUFEND_EADDR_Pos (0) /*!< HSUSBD_T::CEPBUFEND: EADDR Position */ +#define HSUSBD_CEPBUFEND_EADDR_Msk (0xffful << HSUSBD_CEPBUFEND_EADDR_Pos) /*!< HSUSBD_T::CEPBUFEND: EADDR Mask */ + +#define HSUSBD_DMACTL_EPNUM_Pos (0) /*!< HSUSBD_T::DMACTL: EPNUM Position */ +#define HSUSBD_DMACTL_EPNUM_Msk (0xful << HSUSBD_DMACTL_EPNUM_Pos) /*!< HSUSBD_T::DMACTL: EPNUM Mask */ + +#define HSUSBD_DMACTL_DMARD_Pos (4) /*!< HSUSBD_T::DMACTL: DMARD Position */ +#define HSUSBD_DMACTL_DMARD_Msk (0x1ul << HSUSBD_DMACTL_DMARD_Pos) /*!< HSUSBD_T::DMACTL: DMARD Mask */ + +#define HSUSBD_DMACTL_DMAEN_Pos (5) /*!< HSUSBD_T::DMACTL: DMAEN Position */ +#define HSUSBD_DMACTL_DMAEN_Msk (0x1ul << HSUSBD_DMACTL_DMAEN_Pos) /*!< HSUSBD_T::DMACTL: DMAEN Mask */ + +#define HSUSBD_DMACTL_SGEN_Pos (6) /*!< HSUSBD_T::DMACTL: SGEN Position */ +#define HSUSBD_DMACTL_SGEN_Msk (0x1ul << HSUSBD_DMACTL_SGEN_Pos) /*!< HSUSBD_T::DMACTL: SGEN Mask */ + +#define HSUSBD_DMACTL_DMARST_Pos (7) /*!< HSUSBD_T::DMACTL: DMARST Position */ +#define HSUSBD_DMACTL_DMARST_Msk (0x1ul << HSUSBD_DMACTL_DMARST_Pos) /*!< HSUSBD_T::DMACTL: DMARST Mask */ + +#define HSUSBD_DMACTL_SVINEP_Pos (8) /*!< HSUSBD_T::DMACTL: SVINEP Position */ +#define HSUSBD_DMACTL_SVINEP_Msk (0x1ul << HSUSBD_DMACTL_SVINEP_Pos) /*!< HSUSBD_T::DMACTL: SVINEP Mask */ + +#define HSUSBD_DMACNT_DMACNT_Pos (0) /*!< HSUSBD_T::DMACNT: DMACNT Position */ +#define HSUSBD_DMACNT_DMACNT_Msk (0xffffful << HSUSBD_DMACNT_DMACNT_Pos) /*!< HSUSBD_T::DMACNT: DMACNT Mask */ + +#define HSUSBD_EPDAT_EPDAT_Pos (0) /*!< HSUSBD_T::EPDAT: EPDAT Position */ +#define HSUSBD_EPDAT_EPDAT_Msk (0xfffffffful << HSUSBD_EPDAT_EPDAT_Pos) /*!< HSUSBD_T::EPDAT: EPDAT Mask */ + +#define HSUSBD_EPINTSTS_BUFFULLIF_Pos (0) /*!< HSUSBD_T::EPINTSTS: BUFFULLIF Position */ +#define HSUSBD_EPINTSTS_BUFFULLIF_Msk (0x1ul << HSUSBD_EPINTSTS_BUFFULLIF_Pos) /*!< HSUSBD_T::EPINTSTS: BUFFULLIF Mask */ + +#define HSUSBD_EPINTSTS_BUFEMPTYIF_Pos (1) /*!< HSUSBD_T::EPINTSTS: BUFEMPTYIF Position*/ +#define HSUSBD_EPINTSTS_BUFEMPTYIF_Msk (0x1ul << HSUSBD_EPINTSTS_BUFEMPTYIF_Pos) /*!< HSUSBD_T::EPINTSTS: BUFEMPTYIF Mask */ + +#define HSUSBD_EPINTSTS_SHORTTXIF_Pos (2) /*!< HSUSBD_T::EPINTSTS: SHORTTXIF Position */ +#define HSUSBD_EPINTSTS_SHORTTXIF_Msk (0x1ul << HSUSBD_EPINTSTS_SHORTTXIF_Pos) /*!< HSUSBD_T::EPINTSTS: SHORTTXIF Mask */ + +#define HSUSBD_EPINTSTS_TXPKIF_Pos (3) /*!< HSUSBD_T::EPINTSTS: TXPKIF Position */ +#define HSUSBD_EPINTSTS_TXPKIF_Msk (0x1ul << HSUSBD_EPINTSTS_TXPKIF_Pos) /*!< HSUSBD_T::EPINTSTS: TXPKIF Mask */ + +#define HSUSBD_EPINTSTS_RXPKIF_Pos (4) /*!< HSUSBD_T::EPINTSTS: RXPKIF Position */ +#define HSUSBD_EPINTSTS_RXPKIF_Msk (0x1ul << HSUSBD_EPINTSTS_RXPKIF_Pos) /*!< HSUSBD_T::EPINTSTS: RXPKIF Mask */ + +#define HSUSBD_EPINTSTS_OUTTKIF_Pos (5) /*!< HSUSBD_T::EPINTSTS: OUTTKIF Position */ +#define HSUSBD_EPINTSTS_OUTTKIF_Msk (0x1ul << HSUSBD_EPINTSTS_OUTTKIF_Pos) /*!< HSUSBD_T::EPINTSTS: OUTTKIF Mask */ + +#define HSUSBD_EPINTSTS_INTKIF_Pos (6) /*!< HSUSBD_T::EPINTSTS: INTKIF Position */ +#define HSUSBD_EPINTSTS_INTKIF_Msk (0x1ul << HSUSBD_EPINTSTS_INTKIF_Pos) /*!< HSUSBD_T::EPINTSTS: INTKIF Mask */ + +#define HSUSBD_EPINTSTS_PINGIF_Pos (7) /*!< HSUSBD_T::EPINTSTS: PINGIF Position */ +#define HSUSBD_EPINTSTS_PINGIF_Msk (0x1ul << HSUSBD_EPINTSTS_PINGIF_Pos) /*!< HSUSBD_T::EPINTSTS: PINGIF Mask */ + +#define HSUSBD_EPINTSTS_NAKIF_Pos (8) /*!< HSUSBD_T::EPINTSTS: NAKIF Position */ +#define HSUSBD_EPINTSTS_NAKIF_Msk (0x1ul << HSUSBD_EPINTSTS_NAKIF_Pos) /*!< HSUSBD_T::EPINTSTS: NAKIF Mask */ + +#define HSUSBD_EPINTSTS_STALLIF_Pos (9) /*!< HSUSBD_T::EPINTSTS: STALLIF Position */ +#define HSUSBD_EPINTSTS_STALLIF_Msk (0x1ul << HSUSBD_EPINTSTS_STALLIF_Pos) /*!< HSUSBD_T::EPINTSTS: STALLIF Mask */ + +#define HSUSBD_EPINTSTS_NYETIF_Pos (10) /*!< HSUSBD_T::EPINTSTS: NYETIF Position */ +#define HSUSBD_EPINTSTS_NYETIF_Msk (0x1ul << HSUSBD_EPINTSTS_NYETIF_Pos) /*!< HSUSBD_T::EPINTSTS: NYETIF Mask */ + +#define HSUSBD_EPINTSTS_ERRIF_Pos (11) /*!< HSUSBD_T::EPINTSTS: ERRIF Position */ +#define HSUSBD_EPINTSTS_ERRIF_Msk (0x1ul << HSUSBD_EPINTSTS_ERRIF_Pos) /*!< HSUSBD_T::EPINTSTS: ERRIF Mask */ + +#define HSUSBD_EPINTSTS_SHORTRXIF_Pos (12) /*!< HSUSBD_T::EPINTSTS: SHORTRXIF Position */ +#define HSUSBD_EPINTSTS_SHORTRXIF_Msk (0x1ul << HSUSBD_EPINTSTS_SHORTRXIF_Pos) /*!< HSUSBD_T::EPINTSTS: SHORTRXIF Mask */ + +#define HSUSBD_EPINTEN_BUFFULLIEN_Pos (0) /*!< HSUSBD_T::EPINTEN: BUFFULLIEN Position */ +#define HSUSBD_EPINTEN_BUFFULLIEN_Msk (0x1ul << HSUSBD_EPINTEN_BUFFULLIEN_Pos) /*!< HSUSBD_T::EPINTEN: BUFFULLIEN Mask */ + +#define HSUSBD_EPINTEN_BUFEMPTYIEN_Pos (1) /*!< HSUSBD_T::EPINTEN: BUFEMPTYIEN Position*/ +#define HSUSBD_EPINTEN_BUFEMPTYIEN_Msk (0x1ul << HSUSBD_EPINTEN_BUFEMPTYIEN_Pos) /*!< HSUSBD_T::EPINTEN: BUFEMPTYIEN Mask */ + +#define HSUSBD_EPINTEN_SHORTTXIEN_Pos (2) /*!< HSUSBD_T::EPINTEN: SHORTTXIEN Position */ +#define HSUSBD_EPINTEN_SHORTTXIEN_Msk (0x1ul << HSUSBD_EPINTEN_SHORTTXIEN_Pos) /*!< HSUSBD_T::EPINTEN: SHORTTXIEN Mask */ + +#define HSUSBD_EPINTEN_TXPKIEN_Pos (3) /*!< HSUSBD_T::EPINTEN: TXPKIEN Position */ +#define HSUSBD_EPINTEN_TXPKIEN_Msk (0x1ul << HSUSBD_EPINTEN_TXPKIEN_Pos) /*!< HSUSBD_T::EPINTEN: TXPKIEN Mask */ + +#define HSUSBD_EPINTEN_RXPKIEN_Pos (4) /*!< HSUSBD_T::EPINTEN: RXPKIEN Position */ +#define HSUSBD_EPINTEN_RXPKIEN_Msk (0x1ul << HSUSBD_EPINTEN_RXPKIEN_Pos) /*!< HSUSBD_T::EPINTEN: RXPKIEN Mask */ + +#define HSUSBD_EPINTEN_OUTTKIEN_Pos (5) /*!< HSUSBD_T::EPINTEN: OUTTKIEN Position */ +#define HSUSBD_EPINTEN_OUTTKIEN_Msk (0x1ul << HSUSBD_EPINTEN_OUTTKIEN_Pos) /*!< HSUSBD_T::EPINTEN: OUTTKIEN Mask */ + +#define HSUSBD_EPINTEN_INTKIEN_Pos (6) /*!< HSUSBD_T::EPINTEN: INTKIEN Position */ +#define HSUSBD_EPINTEN_INTKIEN_Msk (0x1ul << HSUSBD_EPINTEN_INTKIEN_Pos) /*!< HSUSBD_T::EPINTEN: INTKIEN Mask */ + +#define HSUSBD_EPINTEN_PINGIEN_Pos (7) /*!< HSUSBD_T::EPINTEN: PINGIEN Position */ +#define HSUSBD_EPINTEN_PINGIEN_Msk (0x1ul << HSUSBD_EPINTEN_PINGIEN_Pos) /*!< HSUSBD_T::EPINTEN: PINGIEN Mask */ + +#define HSUSBD_EPINTEN_NAKIEN_Pos (8) /*!< HSUSBD_T::EPINTEN: NAKIEN Position */ +#define HSUSBD_EPINTEN_NAKIEN_Msk (0x1ul << HSUSBD_EPINTEN_NAKIEN_Pos) /*!< HSUSBD_T::EPINTEN: NAKIEN Mask */ + +#define HSUSBD_EPINTEN_STALLIEN_Pos (9) /*!< HSUSBD_T::EPINTEN: STALLIEN Position */ +#define HSUSBD_EPINTEN_STALLIEN_Msk (0x1ul << HSUSBD_EPINTEN_STALLIEN_Pos) /*!< HSUSBD_T::EPINTEN: STALLIEN Mask */ + +#define HSUSBD_EPINTEN_NYETIEN_Pos (10) /*!< HSUSBD_T::EPINTEN: NYETIEN Position */ +#define HSUSBD_EPINTEN_NYETIEN_Msk (0x1ul << HSUSBD_EPINTEN_NYETIEN_Pos) /*!< HSUSBD_T::EPINTEN: NYETIEN Mask */ + +#define HSUSBD_EPINTEN_ERRIEN_Pos (11) /*!< HSUSBD_T::EPINTEN: ERRIEN Position */ +#define HSUSBD_EPINTEN_ERRIEN_Msk (0x1ul << HSUSBD_EPINTEN_ERRIEN_Pos) /*!< HSUSBD_T::EPINTEN: ERRIEN Mask */ + +#define HSUSBD_EPINTEN_SHORTRXIEN_Pos (12) /*!< HSUSBD_T::EPINTEN: SHORTRXIEN Position */ +#define HSUSBD_EPINTEN_SHORTRXIEN_Msk (0x1ul << HSUSBD_EPINTEN_SHORTRXIEN_Pos) /*!< HSUSBD_T::EPINTEN: SHORTRXIEN Mask */ + +#define HSUSBD_EPDATCNT_DATCNT_Pos (0) /*!< HSUSBD_T::EPDATCNT: DATCNT Position */ +#define HSUSBD_EPDATCNT_DATCNT_Msk (0xfffful << HSUSBD_EPDATCNT_DATCNT_Pos) /*!< HSUSBD_T::EPDATCNT: DATCNT Mask */ + +#define HSUSBD_EPDATCNT_DMALOOP_Pos (16) /*!< HSUSBD_T::EPDATCNT: DMALOOP Position */ +#define HSUSBD_EPDATCNT_DMALOOP_Msk (0x7ffful << HSUSBD_EPDATCNT_DMALOOP_Pos) /*!< HSUSBD_T::EPDATCNT: DMALOOP Mask */ + +#define HSUSBD_EPRSPCTL_FLUSH_Pos (0) /*!< HSUSBD_T::EPRSPCTL: FLUSH Position */ +#define HSUSBD_EPRSPCTL_FLUSH_Msk (0x1ul << HSUSBD_EPRSPCTL_FLUSH_Pos) /*!< HSUSBD_T::EPRSPCTL: FLUSH Mask */ + +#define HSUSBD_EPRSPCTL_MODE_Pos (1) /*!< HSUSBD_T::EPRSPCTL: MODE Position */ +#define HSUSBD_EPRSPCTL_MODE_Msk (0x3ul << HSUSBD_EPRSPCTL_MODE_Pos) /*!< HSUSBD_T::EPRSPCTL: MODE Mask */ + +#define HSUSBD_EPRSPCTL_TOGGLE_Pos (3) /*!< HSUSBD_T::EPRSPCTL: TOGGLE Position */ +#define HSUSBD_EPRSPCTL_TOGGLE_Msk (0x1ul << HSUSBD_EPRSPCTL_TOGGLE_Pos) /*!< HSUSBD_T::EPRSPCTL: TOGGLE Mask */ + +#define HSUSBD_EPRSPCTL_HALT_Pos (4) /*!< HSUSBD_T::EPRSPCTL: HALT Position */ +#define HSUSBD_EPRSPCTL_HALT_Msk (0x1ul << HSUSBD_EPRSPCTL_HALT_Pos) /*!< HSUSBD_T::EPRSPCTL: HALT Mask */ + +#define HSUSBD_EPRSPCTL_ZEROLEN_Pos (5) /*!< HSUSBD_T::EPRSPCTL: ZEROLEN Position */ +#define HSUSBD_EPRSPCTL_ZEROLEN_Msk (0x1ul << HSUSBD_EPRSPCTL_ZEROLEN_Pos) /*!< HSUSBD_T::EPRSPCTL: ZEROLEN Mask */ + +#define HSUSBD_EPRSPCTL_SHORTTXEN_Pos (6) /*!< HSUSBD_T::EPRSPCTL: SHORTTXEN Position */ +#define HSUSBD_EPRSPCTL_SHORTTXEN_Msk (0x1ul << HSUSBD_EPRSPCTL_SHORTTXEN_Pos) /*!< HSUSBD_T::EPRSPCTL: SHORTTXEN Mask */ + +#define HSUSBD_EPRSPCTL_DISBUF_Pos (7) /*!< HSUSBD_T::EPRSPCTL: DISBUF Position */ +#define HSUSBD_EPRSPCTL_DISBUF_Msk (0x1ul << HSUSBD_EPRSPCTL_DISBUF_Pos) /*!< HSUSBD_T::EPRSPCTL: DISBUF Mask */ + +#define HSUSBD_EPMPS_EPMPS_Pos (0) /*!< HSUSBD_T::EPMPS: EPMPS Position */ +#define HSUSBD_EPMPS_EPMPS_Msk (0x7fful << HSUSBD_EPMPS_EPMPS_Pos) /*!< HSUSBD_T::EPMPS: EPMPS Mask */ + +#define HSUSBD_EPTXCNT_TXCNT_Pos (0) /*!< HSUSBD_T::EPTXCNT: TXCNT Position */ +#define HSUSBD_EPTXCNT_TXCNT_Msk (0x7fful << HSUSBD_EPTXCNT_TXCNT_Pos) /*!< HSUSBD_T::EPTXCNT: TXCNT Mask */ + +#define HSUSBD_EPCFG_EPEN_Pos (0) /*!< HSUSBD_T::EPCFG: EPEN Position */ +#define HSUSBD_EPCFG_EPEN_Msk (0x1ul << HSUSBD_EPCFG_EPEN_Pos) /*!< HSUSBD_T::EPCFG: EPEN Mask */ + +#define HSUSBD_EPCFG_EPTYPE_Pos (1) /*!< HSUSBD_T::EPCFG: EPTYPE Position */ +#define HSUSBD_EPCFG_EPTYPE_Msk (0x3ul << HSUSBD_EPCFG_EPTYPE_Pos) /*!< HSUSBD_T::EPCFG: EPTYPE Mask */ + +#define HSUSBD_EPCFG_EPDIR_Pos (3) /*!< HSUSBD_T::EPCFG: EPDIR Position */ +#define HSUSBD_EPCFG_EPDIR_Msk (0x1ul << HSUSBD_EPCFG_EPDIR_Pos) /*!< HSUSBD_T::EPCFG: EPDIR Mask */ + +#define HSUSBD_EPCFG_EPNUM_Pos (4) /*!< HSUSBD_T::EPCFG: EPNUM Position */ +#define HSUSBD_EPCFG_EPNUM_Msk (0xful << HSUSBD_EPCFG_EPNUM_Pos) /*!< HSUSBD_T::EPCFG: EPNUM Mask */ + +#define HSUSBD_EPBUFST_SADDR_Pos (0) /*!< HSUSBD_T::EPBUFST: SADDR Position */ +#define HSUSBD_EPBUFST_SADDR_Msk (0xffful << HSUSBD_EPBUFST_SADDR_Pos) /*!< HSUSBD_T::EPBUFST: SADDR Mask */ + +#define HSUSBD_EPBUFEND_EADDR_Pos (0) /*!< HSUSBD_T::EPBUFEND: EADDR Position */ +#define HSUSBD_EPBUFEND_EADDR_Msk (0xffful << HSUSBD_EPBUFEND_EADDR_Pos) /*!< HSUSBD_T::EPBUFEND: EADDR Mask */ + +#define HSUSBD_DMAADDR_DMAADDR_Pos (0) /*!< HSUSBD_T::DMAADDR: DMAADDR Position */ +#define HSUSBD_DMAADDR_DMAADDR_Msk (0xfffffffful << HSUSBD_DMAADDR_DMAADDR_Pos) /*!< HSUSBD_T::DMAADDR: DMAADDR Mask */ + +#define HSUSBD_PHYCTL_DPPUEN_Pos (8) /*!< HSUSBD_T::PHYCTL: DPPUEN Position */ +#define HSUSBD_PHYCTL_DPPUEN_Msk (0x1ul << HSUSBD_PHYCTL_DPPUEN_Pos) /*!< HSUSBD_T::PHYCTL: DPPUEN Mask */ + +#define HSUSBD_PHYCTL_PHYEN_Pos (9) /*!< HSUSBD_T::PHYCTL: PHYEN Position */ +#define HSUSBD_PHYCTL_PHYEN_Msk (0x1ul << HSUSBD_PHYCTL_PHYEN_Pos) /*!< HSUSBD_T::PHYCTL: PHYEN Mask */ + +#define HSUSBD_PHYCTL_WKEN_Pos (24) /*!< HSUSBD_T::PHYCTL: WKEN Position */ +#define HSUSBD_PHYCTL_WKEN_Msk (0x1ul << HSUSBD_PHYCTL_WKEN_Pos) /*!< HSUSBD_T::PHYCTL: WKEN Mask */ + +#define HSUSBD_PHYCTL_VBUSDET_Pos (31) /*!< HSUSBD_T::PHYCTL: VBUSDET Position */ +#define HSUSBD_PHYCTL_VBUSDET_Msk (0x1ul << HSUSBD_PHYCTL_VBUSDET_Pos) /*!< HSUSBD_T::PHYCTL: VBUSDET Mask */ + +/**@}*/ /* HSUSBD_CONST */ +/**@}*/ /* end of HSUSBD register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __HSUSBD_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/hsusbh_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/hsusbh_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..57cc5d037604cf2ec1e6bcbd643883a98d859332 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/hsusbh_reg.h @@ -0,0 +1,653 @@ +/**************************************************************************//** + * @file hsusbh_reg.h + * @version V1.00 + * @brief HSUSBH register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __HSUSBH_REG_H__ +#define __HSUSBH_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup HSUSBH High Speed USB Host Controller (HSUSBH) + Memory Mapped Structure for HSUSBH Controller +@{ */ + +typedef struct +{ + + + /** + * @var HSUSBH_T::EHCVNR + * Offset: 0x00 EHCI Version Number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |CRLEN |Capability Registers Length + * | | |This register is used as an offset to add to register base to find the beginning of the Operational Register Space. + * |[31:16] |VERSION |Host Controller Interface Version Number + * | | |This is a two-byte register containing a BCD encoding of the EHCI revision number supported by this host controller + * | | |The most significant byte of this register represents a major revision and the least significant byte is the minor revision. + * @var HSUSBH_T::EHCSPR + * Offset: 0x04 EHCI Structural Parameters Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |N_PORTS |Number of Physical Downstream Ports + * | | |This field specifies the number of physical downstream ports implemented on this host controller + * | | |The value of this field determines how many port registers are addressable in the Operational Register Space (see Table 2-8) + * | | |Valid values are in the range of 1H to FH. + * | | |A zero in this field is undefined. + * |[4] |PPC |Port Power Control + * | | |This field indicates whether the host controller implementation includes port power control + * | | |A one in this bit indicates the ports have port power switches + * | | |A zero in this bit indicates the port do not have port power stitches + * | | |The value of this field affects the functionality of the Port Power field in each port status and control register. + * |[11:8] |N_PCC |Number of Ports Per Companion Controller + * | | |This field indicates the number of ports supported per companion host controller + * | | |It is used to indicate the port routing configuration to system software. + * | | |For example, if N_PORTS has a value of 6 and N_CC has a value of 2 then N_PCC could have a value of 3 + * | | |The convention is that the first N_PCC ports are assumed to be routed to companion controller 1, the next N_PCC ports to companion controller 2, etc + * | | |In the previous example, the N_PCC could have been 4, where the first 4 are routed to companion controller 1 and the last two are routed to companion controller 2. + * | | |The number in this field must be consistent with N_PORTS and N_CC. + * |[15:12] |N_CC |Number of Companion Controller + * | | |This field indicates the number of companion controllers associated with this USB 2.0 host controller. + * | | |A zero in this field indicates there are no companion host controllers + * | | |Port-ownership hand-off is not supported + * | | |Only high-speed devices are supported on the host controller root ports. + * | | |A value larger than zero in this field indicates there are companion USB 1.1 host controller(s) + * | | |Port-ownership hand-offs are supported + * | | |High, Full- and Low-speed devices are supported on the host controller root ports. + * @var HSUSBH_T::EHCCPR + * Offset: 0x08 EHCI Capability Parameters Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |AC64 |64-bit Addressing Capability + * | | |0 = Data structure using 32-bit address memory pointers. + * |[1] |PFLF |Programmable Frame List Flag + * | | |0 = System software must use a frame list length of 1024 elements with this EHCI host controller. + * |[2] |ASPC |Asynchronous Schedule Park Capability + * | | |0 = This EHCI host controller doesn't support park feature of high-speed queue heads in the Asynchronous Schedule. + * |[7:4] |IST |Isochronous Scheduling Threshold + * | | |This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule. + * | | |When bit [7] is zero, the value of the least significant 3 bits indicates the number of micro-frames a host controller can hold a set of isochronous data structures (one or more) before flushing the state. + * |[15:8] |EECP |EHCI Extended Capabilities Pointer (EECP) + * | | |0 = No extended capabilities are implemented. + * @var HSUSBH_T::UCMDR + * Offset: 0x20 USB Command Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RUN |Run/Stop (R/W) + * | | |When set to a 1, the Host Controller proceeds with execution of the schedule + * | | |The Host Controller continues execution as long as this bit is set to a 1 + * | | |When this bit is set to 0, the Host Controller completes the current and any actively pipelined transactions on the USB and then halts + * | | |The Host Controller must halt within 16 micro-frames after software clears the Run bit + * | | |The HC Halted bit in the status register indicates when the Host Controller has finished its pending pipelined transactions and has entered the stopped state + * | | |Software must not write a one to this field unless the host controller is in the Halted state (i.e. + * | | |HCHalted in the USBSTS register is a one) + * | | |Doing so will yield undefined results. + * | | |0 = Stop. + * | | |1 = Run. + * |[1] |HCRST |Host Controller Reset (HCRESET) (R/W) + * | | |This control bit is used by software to reset the host controller + * | | |The effects of this on Root Hub registers are similar to a Chip Hardware Reset. + * | | |When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines, etc + * | | |to their initial value + * | | |Any transaction currently in progress on USB is immediately terminated + * | | |A USB reset is not driven on downstream ports. + * | | |All operational registers, including port registers and port state machines are set to their initial values + * | | |Port ownership reverts to the companion host controller(s), with the side effects + * | | |Software must reinitialize the host controller in order to return the host controller to an operational state. + * | | |This bit is set to zero by the Host Controller when the reset process is complete + * | | |Software cannot terminate the reset process early by writing a zero to this register. + * | | |Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero + * | | |Attempting to reset an actively running host controller will result in undefined behavior. + * |[3:2] |FLSZ |Frame List Size (R/W or RO) + * | | |This field is R/W only if Programmable Frame List Flag in the HCCPARAMS registers is set to a one + * | | |This field specifies the size of the frame list + * | | |The size the frame list controls which bits in the Frame Index Register should be used for the Frame List Current index + * | | |Values mean: + * | | |00 = 1024 elements (4096 bytes) Default value. + * | | |01 = 512 elements (2048 bytes). + * | | |10 = 256 elements (1024 bytes) u2013 for resource-constrained environment. + * | | |11 = Reserved. + * |[4] |PSEN |Periodic Schedule Enable (R/W) + * | | |This bit controls whether the host controller skips processing the Periodic Schedule. Values mean: + * | | |0 = Do not process the Periodic Schedule. + * | | |1 = Use the PERIODICLISTBASE register to access the Periodic Schedule. + * |[5] |ASEN |Asynchronous Schedule Enable (R/W) + * | | |This bit controls whether the host controller skips processing the Asynchronous Schedule. Values mean: + * | | |0 = Do not process the Asynchronous Schedule. + * | | |1 = Use the ASYNCLISTADDR register to access the Asynchronous Schedule. + * |[6] |IAAD |Interrupt on Asynchronous Advance Doorbell (R/W) + * | | |This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule + * | | |Software must write a 1 to this bit to ring the doorbell. + * | | |When the host controller has evicted all appropriate cached schedule state, it sets the Interrupt on Asynchronous Advance status bit in the USBSTS register + * | | |If the Interrupt on Asynchronous Advance Enable bit in the USBINTR register is a one then the host controller will assert an interrupt at the next interrupt threshold. + * | | |The host controller sets this bit to a zero after it has set the Interrupt on Asynchronous Advance status bit in the USBSTS register to a one. + * | | |Software should not write a one to this bit when the asynchronous schedule is disabled + * | | |Doing so will yield undefined results. + * |[23:16] |ITC |Interrupt Threshold Control (R/W) + * | | |This field is used by system software to select the maximum rate at which the host controller will issue interrupts + * | | |The only valid values are defined below + * | | |If software writes an invalid value to this register, the results are undefined + * | | |Value Maximum Interrupt Interval + * | | |0x00 = Reserved. + * | | |0x01 = 1 micro-frame. + * | | |0x02 = 2 micro-frames. + * | | |0x04 = 4 micro-frames. + * | | |0x08 = 8 micro-frames (default, equates to 1 ms). + * | | |0x10 = 16 micro-frames (2 ms). + * | | |0x20 = 32 micro-frames (4 ms). + * | | |0x40 = 64 micro-frames (8 ms). + * | | |Any other value in this register yields undefined results. + * | | |Software modifications to this bit while HCHalted bit is equal to zero results in undefined behavior. + * @var HSUSBH_T::USTSR + * Offset: 0x24 USB Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |USBINT |USB Interrupt (USBINT) (R/WC) + * | | |The Host Controller sets this bit to 1 on the completion of a USB transaction, which results in the retirement of a Transfer Descriptor that had its IOC bit set. + * | | |The Host Controller also sets this bit to 1 when a short packet is detected (actual number of bytes received was less than the expected number of bytes). + * |[1] |UERRINT |USB Error Interrupt (USBERRINT) (R/WC) + * | | |The Host Controller sets this bit to 1 when completion of a USB transaction results in an error condition (e.g., error counter underflow) + * | | |If the TD on which the error interrupt occurred also had its IOC bit set, both this bit and USBINT bit are set. + * |[2] |PCD |Port Change Detect (R/WC) + * | | |The Host Controller sets this bit to a one when any port for which the Port Owner bit is set to zero has a change bit transition from a zero to a one or a Force Port Resume bit transition from a zero to a one as a result of a J-K transition detected on a suspended port + * | | |This bit will also be set as a result of the Connect Status Change being set to a one after system software has relinquished ownership of a connected port by writing a one to a port's Port Owner bit. + * | | |This bit is allowed to be maintained in the Auxiliary power well + * | | |Alternatively, it is also acceptable that on a D3 to D0 transition of the EHCI HC device, this bit is loaded with the OR of all of the PORTSC change bits (including: Force port resume, over-current change, enable/disable change and connect status change). + * |[3] |FLR |Frame List Rollover (R/WC) + * | | |The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero + * | | |The exact value at which the rollover occurs depends on the frame list size + * | | |For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX[13] toggles + * | | |Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX[12] toggles. + * |[4] |HSERR |Host System Error (R/WC) + * | | |The Host Controller sets this bit to 1 when a serious error occurs during a host system access involving the Host Controller module. + * |[5] |IAA |Interrupt on Asynchronous Advance (R/WC) + * | | |System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Asynchronous Advance Doorbell bit in the USBCMD register + * | | |This status bit indicates the assertion of that interrupt source. + * |[12] |HCHalted |HCHalted (RO) + * | | |This bit is a zero whenever the Run/Stop bit is a one + * | | |The Host Controller sets this bit to one after it has stopped executing as a result of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. + * | | |internal error). + * |[13] |RECLA |Reclamation (RO) + * | | |This is a read-only status bit, which is used to detect an empty asynchronous schedule. + * |[14] |PSS |Periodic Schedule Status (RO) + * | | |The bit reports the current real status of the Periodic Schedule + * | | |If this bit is a zero then the status of the Periodic Schedule is disabled + * | | |If this bit is a one then the status of the Periodic Schedule is enabled + * | | |The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register + * | | |When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). + * |[15] |ASS |Asynchronous Schedule Status (RO) + * | | |The bit reports the current real status of the Asynchronous Schedule + * | | |If this bit is a zero then the status of them Asynchronous Schedule is disabled + * | | |If this bit is a one then the status of the Asynchronous Schedule is enabled + * | | |The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register + * | | |When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). + * @var HSUSBH_T::UIENR + * Offset: 0x28 USB Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |USBIEN |USB Interrupt Enable or Disable Bit + * | | |When this bit is a one, and the USBINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold + * | | |The interrupt is acknowledged by software clearing the USBINT bit. + * | | |0 = USB interrupt Disabled. + * | | |1 = USB interrupt Enabled. + * |[1] |UERRIEN |USB Error Interrupt Enable or Disable Bit + * | | |When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host t controller will issue an interrupt at the next interrupt threshold + * | | |The interrupt is acknowledged by software clearing the USBERRINT bit. + * | | |0 = USB Error interrupt Disabled. + * | | |1 = USB Error interrupt Enabled. + * |[2] |PCIEN |Port Change Interrupt Enable or Disable Bit + * | | |When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host controller will issue an interrupt + * | | |The interrupt is acknowledged by software clearing the Port Change Detect bit. + * | | |0 = Port Change interrupt Disabled. + * | | |1 = Port Change interrupt Enabled. + * |[3] |FLREN |Frame List Rollover Enable or Disable Bit + * | | |When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt + * | | |The interrupt is acknowledged by software clearing the Frame List Rollover bit. + * | | |0 = Frame List Rollover interrupt Disabled. + * | | |1 = Frame List Rollover interrupt Enabled. + * |[4] |HSERREN |Host System Error Enable or Disable Bit + * | | |When this bit is a one, and the Host System Error Status bit in the USBSTS register is a one, the host controller will issue an interrupt + * | | |The interrupt is acknowledged by software clearing the Host System Error bit. + * | | |0 = Host System Error interrupt Disabled. + * | | |1 = Host System Error interrupt Enabled. + * |[5] |IAAEN |Interrupt on Asynchronous Advance Enable or Disable Bit + * | | |When this bit is a one, and the Interrupt on Asynchronous Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold + * | | |The interrupt is acknowledged by software clearing the Interrupt on Asynchronous Advance bit. + * | | |0 = Interrupt on Asynchronous Advance Disabled. + * | | |1 = Interrupt on Asynchronous Advance Enabled. + * @var HSUSBH_T::UFINDR + * Offset: 0x2C USB Frame Index Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[13:0] |FI |Frame Index + * | | |The value in this register increment at the end of each time frame (e.g. + * | | |micro-frame) + * | | |Bits [N:3] are used for the Frame List current index + * | | |This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index + * | | |The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register. + * | | |FLSZ (UCMDR[3:2] Number Elements N + * | | |0x0 1024 12 + * | | |0x1 512 11 + * | | |0x2 256 10 + * | | |0x3 Reserved + * @var HSUSBH_T::UPFLBAR + * Offset: 0x34 USB Periodic Frame List Base Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:12] |BADDR |Base Address + * | | |These bits correspond to memory address signals [31:12], respectively. + * @var HSUSBH_T::UCALAR + * Offset: 0x38 USB Current Asynchronous List Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:5] |LPL |Link Pointer Low (LPL) + * | | |These bits correspond to memory address signals [31:5], respectively + * | | |This field may only reference a Queue Head (QH). + * @var HSUSBH_T::UASSTR + * Offset: 0x3C USB Asynchronous Schedule Sleep Timer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |ASSTMR |Asynchronous Schedule Sleep Timer + * | | |This field defines the AsyncSchedSleepTime of EHCI spec. + * | | |The asynchronous schedule sleep timer is used to control how often the host controller fetches asynchronous schedule list from system memory while the asynchronous schedule is empty. + * | | |The default value of this timer is 12'hBD6 + * | | |Because this timer is implemented in UTMI clock (30MHz) domain, the default sleeping time will be about 100us. + * @var HSUSBH_T::UCFGR + * Offset: 0x60 USB Configure Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CF |Configure Flag (CF) + * | | |Host software sets this bit as the last action in its process of configuring the Host Controller + * | | |This bit controls the default port-routing control logic + * | | |Bit values and side-effects are listed below. + * | | |0 = Port routing control logic default-routes each port to an implementation dependent classic host controller. + * | | |1 = Port routing control logic default-routes all ports to this host controller. + * @var HSUSBH_T::UPSCR[2] + * Offset: 0x64~0x68 USB Port 0~1 Status and Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CCS |Current Connect Status (RO) + * | | |This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. + * | | |This field is zero if Port Power is zero. + * | | |0 = No device is present. + * | | |1 = Device is present on port. + * |[1] |CSC |Connect Status Change (R/W) + * | | |Indicates a change has occurred in the port's Current Connect Status + * | | |The host controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change + * | | |For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be "setting" an already-set bit (i.e., the bit will remain set).Software sets this bit to 0 by writing a 1 to it. + * | | |This field is zero if Port Power is zero. + * | | |0 = No change. + * | | |1 = Change in Current Connect Status. + * |[2] |PE |Port Enabled/Disabled (R/W) + * | | |Ports can only be enabled by the host controller as a part of the reset and enable + * | | |Software cannot enable a port by writing a one to this field + * | | |The host controller will only set this bit to a one when the reset sequence determines that the attached device is a high-speed device. + * | | |Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by host software + * | | |Note that the bit status does not change until the port state actually changes + * | | |There may be a delay in disabling or enabling a port due to other host controller and bus events. + * | | |When the port is disabled (0b) downstream propagation of data is blocked on this port, except for reset. + * | | |This field is zero if Port Power is zero. + * | | |0 = Port Disabled. + * | | |1 = Port Enabled. + * |[3] |PEC |Port Enable/Disable Change (R/WC) + * | | |For the root hub, this bit gets set to a one only when a port is disabled due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification for the definition of a Port Error) + * | | |Software clears this bit by writing a 1 to it. + * | | |This field is zero if Port Power is zero. + * | | |0 = No change. + * | | |1 = Port enabled/disabled status has changed. + * |[4] |OCA |Over-current Active (RO) + * | | |This bit will automatically transition from a one to a zero when the over current condition is removed. + * | | |0 = This port does not have an over-current condition. + * | | |1 = This port currently has an over-current condition. + * |[5] |OCC |Over-current Change (R/WC) + * | | |1 = This bit gets set to a one when there is a change to Over-current Active + * | | |Software clears this bit by writing a one to this bit position. + * |[6] |FPR |Force Port Resume (R/W) + * | | |This functionality defined for manipulating this bit depends on the value of the Suspend bit + * | | |For example, if the port is not suspended (Suspend and Enabled bits are a one) and software transitions this bit to a one, then the effects on the bus are undefined. + * | | |Software sets this bit to a 1 to drive resume signaling + * | | |The Host Controller sets this bit to a 1 if a J-to-K transition is detected while the port is in the Suspend state + * | | |When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to a one + * | | |If software sets this bit to a one, the host controller must not set the Port Change Detect bit. + * | | |Note that when the EHCI controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0 + * | | |The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one + * | | |Software must appropriately time the Resume and set this bit to a zero when the appropriate amount of time has elapsed + * | | |Writing a zero (from one) causes the port to return to high-speed mode (forcing the bus below the port into a high-speed idle) + * | | |This bit will remain a one until the port has switched to the high-speed idle + * | | |The host controller must complete this transition within 2 milliseconds of software setting this bit to a zero. + * | | |This field is zero if Port Power is zero. + * | | |0 = No resume (K-state) detected/driven on port. + * | | |1 = Resume detected/driven on port. + * |[7] |SUSPEND |Suspend (R/W) + * | | |Port Enabled Bit and Suspend bit of this register define the port states as follows: + * | | |Port enable is 0 and suspend is 0 = Disable. + * | | |Port enable is 0 and suspend is 1 = Disable. + * | | |Port enable is 1 and suspend is 0 = Enable. + * | | |Port enable is 1 and suspend is 1 = Suspend. + * | | |When in suspend state, downstream propagation of data is blocked on this port, except for port reset + * | | |The blocking occurs at the end of the current transaction, if a transaction was in progress when this bit was written to 1 + * | | |In the suspend state, the port is sensitive to resume detection + * | | |Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. + * | | |A write of zero to this bit is ignored by the host controller + * | | |The host controller will unconditionally set this bit to a zero when: + * | | |Software sets the Force Port Resume bit to a zero (from a one). + * | | |Software sets the Port Reset bit to a one (from a zero). + * | | |If host software sets this bit to a one when the port is not enabled (i.e. + * | | |Port enabled bit is a zero) the results are undefined. + * | | |This field is zero if Port Power is zero. + * | | |0 = Port not in suspend state. + * | | |1 = Port in suspend state. + * |[8] |PRST |Port Reset (R/W) + * | | |When software writes a one to this bit (from a zero), the bus reset sequence as defined in the USB Specification Revision 2.0 is started + * | | |Software writes a zero to this bit to terminate the bus reset sequence + * | | |Software must keep this bit at a one long enough to ensure the reset sequence, as specified in the USB Specification Revision 2.0, completes + * | | |Note: when software writes this bit to a one, it must also write a zero to the Port Enable bit. + * | | |Note that when software writes a zero to this bit there may be a delay before the bit status changes to a zero + * | | |The bit status will not read as a zero until after the reset has completed + * | | |If the port is in high-speed mode after reset is complete, the host controller will automatically enable this port (e.g. + * | | |set the Port Enable bit to a one) + * | | |A host controller must terminate the reset and stabilize the state of the port within 2 milliseconds of software transitioning this bit from a one to a zero + * | | |For example: if the port detects that the attached device is high-speed during reset, then the host controller must have the port in the enabled state within 2ms of software writing this bit to a zero. + * | | |The HCHalted bit in the USBSTS register should be a zero before software attempts to use this bit + * | | |The host controller may hold Port Reset asserted to a one when the HCHalted bit is a one. + * | | |This field is zero if Port Power is zero. + * | | |0 = Port is not in Reset. + * | | |1 = Port is in Reset. + * |[11:10] |LSTS |Line Status (RO) + * | | |These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal lines + * | | |These bits are used for detection of low-speed USB devices prior to the port reset and enable sequence + * | | |This field is valid only when the port enable bit is zero and the current connect status bit is set to a one. + * | | |The encoding of the bits are: + * | | |Bits[11:10] USB State Interpretation + * | | |00 = SE0 Not Low-speed device, perform EHCI reset. + * | | |01 = K-state Low-speed device, release ownership of port. + * | | |10 = J-state Not Low-speed device, perform EHCI reset. + * | | |11 = Undefined Not Low-speed device, perform EHCI reset. + * | | |This value of this field is undefined if Port Power is zero. + * |[12] |PP |Port Power (PP) + * | | |Host controller has port power control switches + * | | |This bit represents the Current setting of the switch (0 = off, 1 = on) + * | | |When power is not available on a port (i.e. + * | | |PP equals a 0), the port is nonfunctional and will not report attaches, detaches, etc. + * | | |When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller from a 1 to 0 (removing power from the port). + * |[13] |PO |Port Owner (R/W) + * | | |This bit unconditionally goes to a 0b when the Configured bit in the CONFIGFLAG register makes a 0 to 1 transition + * | | |This bit unconditionally goes to 1 whenever the Configured bit is zero. + * | | |System software uses this field to release ownership of the port to a selected host controller (in the event that the attached device is not a high-speed device) + * | | |Software writes a one to this bit when the attached device is not a high-speed device + * | | |A one in this bit means that a companion host controller owns and controls the port. + * |[19:16] |PTC |Port Test Control (R/W) + * | | |When this field is zero, the port is NOT operating in a test mode + * | | |A non-zero value indicates that it is operating in test mode and the specific test mode is indicated by the specific value + * | | |The encoding of the test mode bits are (0x6 ~ 0xF are reserved): + * | | |Bits Test Mode + * | | |0x0 = Test mode not enabled. + * | | |0x1 = Test J_STATE. + * | | |0x2 = Test K_STATE. + * | | |0x3 = Test SE0_NAK. + * | | |0x4 = Test Packet. + * | | |0x5 = Test FORCE_ENABLE. + * @var HSUSBH_T::USBPCR0 + * Offset: 0xC4 USB PHY 0 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8] |SUSPEND |Suspend Assertion + * | | |This bit controls the suspend mode of USB PHY 0. + * | | |While PHY was suspended, all circuits of PHY were powered down and outputs are tri-state. + * | | |This bit is 1'b0 in default + * | | |This means the USB PHY 0 is suspended in default + * | | |It is necessary to set this bit 1'b1 to make USB PHY 0 leave suspend mode before doing configuration of USB host. + * | | |0 = USB PHY 0 was suspended. + * | | |1 = USB PHY 0 was not suspended. + * |[11] |CLKVALID |UTMI Clock Valid + * | | |This bit is a flag to indicate if the UTMI clock from USB 2.0 PHY is ready + * | | |S/W program must prevent to write other control registers before this UTMI clock valid flag is active. + * | | |0 = UTMI clock is not valid. + * | | |1 = UTMI clock is valid. + * @var HSUSBH_T::USBPCR1 + * Offset: 0xC8 USB PHY 1 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8] |SUSPEND |Suspend Assertion + * | | |This bit controls the suspend mode of USB PHY 1. + * | | |While PHY was suspended, all circuits of PHY were powered down and outputs are tri-state. + * | | |This bit is 1'b0 in default + * | | |This means the USB PHY 0 is suspended in default + * | | |It is necessary to set this bit 1'b1 to make USB PHY 0 leave suspend mode before doing configuration of USB host. + * | | |0 = USB PHY 1 was suspended. + * | | |1 = USB PHY 1 was not suspended. + */ + __I uint32_t EHCVNR; /*!< [0x0000] EHCI Version Number Register */ + __I uint32_t EHCSPR; /*!< [0x0004] EHCI Structural Parameters Register */ + __I uint32_t EHCCPR; /*!< [0x0008] EHCI Capability Parameters Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[5]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t UCMDR; /*!< [0x0020] USB Command Register */ + __IO uint32_t USTSR; /*!< [0x0024] USB Status Register */ + __IO uint32_t UIENR; /*!< [0x0028] USB Interrupt Enable Register */ + __IO uint32_t UFINDR; /*!< [0x002c] USB Frame Index Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t UPFLBAR; /*!< [0x0034] USB Periodic Frame List Base Address Register */ + __IO uint32_t UCALAR; /*!< [0x0038] USB Current Asynchronous List Address Register */ + __IO uint32_t UASSTR; /*!< [0x003c] USB Asynchronous Schedule Sleep Timer Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[8]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t UCFGR; /*!< [0x0060] USB Configure Flag Register */ + __IO uint32_t UPSCR[2]; /*!< [0x0064] ~ [0x0068] USB Port 0 & 1 Status and Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[22]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t USBPCR0; /*!< [0x00c4] USB PHY 0 Control Register */ + __IO uint32_t USBPCR1; /*!< [0x00c8] USB PHY 1 Control Register */ + +} HSUSBH_T; + +/** + @addtogroup HSUSBH_CONST HSUSBH Bit Field Definition + Constant Definitions for HSUSBH Controller +@{ */ + +#define HSUSBH_EHCVNR_CRLEN_Pos (0) /*!< HSUSBH_T::EHCVNR: CRLEN Position */ +#define HSUSBH_EHCVNR_CRLEN_Msk (0xfful << HSUSBH_EHCVNR_CRLEN_Pos) /*!< HSUSBH_T::EHCVNR: CRLEN Mask */ + +#define HSUSBH_EHCVNR_VERSION_Pos (16) /*!< HSUSBH_T::EHCVNR: VERSION Position */ +#define HSUSBH_EHCVNR_VERSION_Msk (0xfffful << HSUSBH_EHCVNR_VERSION_Pos) /*!< HSUSBH_T::EHCVNR: VERSION Mask */ + +#define HSUSBH_EHCSPR_N_PORTS_Pos (0) /*!< HSUSBH_T::EHCSPR: N_PORTS Position */ +#define HSUSBH_EHCSPR_N_PORTS_Msk (0xful << HSUSBH_EHCSPR_N_PORTS_Pos) /*!< HSUSBH_T::EHCSPR: N_PORTS Mask */ + +#define HSUSBH_EHCSPR_PPC_Pos (4) /*!< HSUSBH_T::EHCSPR: PPC Position */ +#define HSUSBH_EHCSPR_PPC_Msk (0x1ul << HSUSBH_EHCSPR_PPC_Pos) /*!< HSUSBH_T::EHCSPR: PPC Mask */ + +#define HSUSBH_EHCSPR_N_PCC_Pos (8) /*!< HSUSBH_T::EHCSPR: N_PCC Position */ +#define HSUSBH_EHCSPR_N_PCC_Msk (0xful << HSUSBH_EHCSPR_N_PCC_Pos) /*!< HSUSBH_T::EHCSPR: N_PCC Mask */ + +#define HSUSBH_EHCSPR_N_CC_Pos (12) /*!< HSUSBH_T::EHCSPR: N_CC Position */ +#define HSUSBH_EHCSPR_N_CC_Msk (0xful << HSUSBH_EHCSPR_N_CC_Pos) /*!< HSUSBH_T::EHCSPR: N_CC Mask */ + +#define HSUSBH_EHCCPR_AC64_Pos (0) /*!< HSUSBH_T::EHCCPR: AC64 Position */ +#define HSUSBH_EHCCPR_AC64_Msk (0x1ul << HSUSBH_EHCCPR_AC64_Pos) /*!< HSUSBH_T::EHCCPR: AC64 Mask */ + +#define HSUSBH_EHCCPR_PFLF_Pos (1) /*!< HSUSBH_T::EHCCPR: PFLF Position */ +#define HSUSBH_EHCCPR_PFLF_Msk (0x1ul << HSUSBH_EHCCPR_PFLF_Pos) /*!< HSUSBH_T::EHCCPR: PFLF Mask */ + +#define HSUSBH_EHCCPR_ASPC_Pos (2) /*!< HSUSBH_T::EHCCPR: ASPC Position */ +#define HSUSBH_EHCCPR_ASPC_Msk (0x1ul << HSUSBH_EHCCPR_ASPC_Pos) /*!< HSUSBH_T::EHCCPR: ASPC Mask */ + +#define HSUSBH_EHCCPR_IST_Pos (4) /*!< HSUSBH_T::EHCCPR: IST Position */ +#define HSUSBH_EHCCPR_IST_Msk (0xful << HSUSBH_EHCCPR_IST_Pos) /*!< HSUSBH_T::EHCCPR: IST Mask */ + +#define HSUSBH_EHCCPR_EECP_Pos (8) /*!< HSUSBH_T::EHCCPR: EECP Position */ +#define HSUSBH_EHCCPR_EECP_Msk (0xfful << HSUSBH_EHCCPR_EECP_Pos) /*!< HSUSBH_T::EHCCPR: EECP Mask */ + +#define HSUSBH_UCMDR_RUN_Pos (0) /*!< HSUSBH_T::UCMDR: RUN Position */ +#define HSUSBH_UCMDR_RUN_Msk (0x1ul << HSUSBH_UCMDR_RUN_Pos) /*!< HSUSBH_T::UCMDR: RUN Mask */ + +#define HSUSBH_UCMDR_HCRST_Pos (1) /*!< HSUSBH_T::UCMDR: HCRST Position */ +#define HSUSBH_UCMDR_HCRST_Msk (0x1ul << HSUSBH_UCMDR_HCRST_Pos) /*!< HSUSBH_T::UCMDR: HCRST Mask */ + +#define HSUSBH_UCMDR_FLSZ_Pos (2) /*!< HSUSBH_T::UCMDR: FLSZ Position */ +#define HSUSBH_UCMDR_FLSZ_Msk (0x3ul << HSUSBH_UCMDR_FLSZ_Pos) /*!< HSUSBH_T::UCMDR: FLSZ Mask */ + +#define HSUSBH_UCMDR_PSEN_Pos (4) /*!< HSUSBH_T::UCMDR: PSEN Position */ +#define HSUSBH_UCMDR_PSEN_Msk (0x1ul << HSUSBH_UCMDR_PSEN_Pos) /*!< HSUSBH_T::UCMDR: PSEN Mask */ + +#define HSUSBH_UCMDR_ASEN_Pos (5) /*!< HSUSBH_T::UCMDR: ASEN Position */ +#define HSUSBH_UCMDR_ASEN_Msk (0x1ul << HSUSBH_UCMDR_ASEN_Pos) /*!< HSUSBH_T::UCMDR: ASEN Mask */ + +#define HSUSBH_UCMDR_IAAD_Pos (6) /*!< HSUSBH_T::UCMDR: IAAD Position */ +#define HSUSBH_UCMDR_IAAD_Msk (0x1ul << HSUSBH_UCMDR_IAAD_Pos) /*!< HSUSBH_T::UCMDR: IAAD Mask */ + +#define HSUSBH_UCMDR_ITC_Pos (16) /*!< HSUSBH_T::UCMDR: ITC Position */ +#define HSUSBH_UCMDR_ITC_Msk (0xfful << HSUSBH_UCMDR_ITC_Pos) /*!< HSUSBH_T::UCMDR: ITC Mask */ + +#define HSUSBH_USTSR_USBINT_Pos (0) /*!< HSUSBH_T::USTSR: USBINT Position */ +#define HSUSBH_USTSR_USBINT_Msk (0x1ul << HSUSBH_USTSR_USBINT_Pos) /*!< HSUSBH_T::USTSR: USBINT Mask */ + +#define HSUSBH_USTSR_UERRINT_Pos (1) /*!< HSUSBH_T::USTSR: UERRINT Position */ +#define HSUSBH_USTSR_UERRINT_Msk (0x1ul << HSUSBH_USTSR_UERRINT_Pos) /*!< HSUSBH_T::USTSR: UERRINT Mask */ + +#define HSUSBH_USTSR_PCD_Pos (2) /*!< HSUSBH_T::USTSR: PCD Position */ +#define HSUSBH_USTSR_PCD_Msk (0x1ul << HSUSBH_USTSR_PCD_Pos) /*!< HSUSBH_T::USTSR: PCD Mask */ + +#define HSUSBH_USTSR_FLR_Pos (3) /*!< HSUSBH_T::USTSR: FLR Position */ +#define HSUSBH_USTSR_FLR_Msk (0x1ul << HSUSBH_USTSR_FLR_Pos) /*!< HSUSBH_T::USTSR: FLR Mask */ + +#define HSUSBH_USTSR_HSERR_Pos (4) /*!< HSUSBH_T::USTSR: HSERR Position */ +#define HSUSBH_USTSR_HSERR_Msk (0x1ul << HSUSBH_USTSR_HSERR_Pos) /*!< HSUSBH_T::USTSR: HSERR Mask */ + +#define HSUSBH_USTSR_IAA_Pos (5) /*!< HSUSBH_T::USTSR: IAA Position */ +#define HSUSBH_USTSR_IAA_Msk (0x1ul << HSUSBH_USTSR_IAA_Pos) /*!< HSUSBH_T::USTSR: IAA Mask */ + +#define HSUSBH_USTSR_HCHalted_Pos (12) /*!< HSUSBH_T::USTSR: HCHalted Position */ +#define HSUSBH_USTSR_HCHalted_Msk (0x1ul << HSUSBH_USTSR_HCHalted_Pos) /*!< HSUSBH_T::USTSR: HCHalted Mask */ + +#define HSUSBH_USTSR_RECLA_Pos (13) /*!< HSUSBH_T::USTSR: RECLA Position */ +#define HSUSBH_USTSR_RECLA_Msk (0x1ul << HSUSBH_USTSR_RECLA_Pos) /*!< HSUSBH_T::USTSR: RECLA Mask */ + +#define HSUSBH_USTSR_PSS_Pos (14) /*!< HSUSBH_T::USTSR: PSS Position */ +#define HSUSBH_USTSR_PSS_Msk (0x1ul << HSUSBH_USTSR_PSS_Pos) /*!< HSUSBH_T::USTSR: PSS Mask */ + +#define HSUSBH_USTSR_ASS_Pos (15) /*!< HSUSBH_T::USTSR: ASS Position */ +#define HSUSBH_USTSR_ASS_Msk (0x1ul << HSUSBH_USTSR_ASS_Pos) /*!< HSUSBH_T::USTSR: ASS Mask */ + +#define HSUSBH_UIENR_USBIEN_Pos (0) /*!< HSUSBH_T::UIENR: USBIEN Position */ +#define HSUSBH_UIENR_USBIEN_Msk (0x1ul << HSUSBH_UIENR_USBIEN_Pos) /*!< HSUSBH_T::UIENR: USBIEN Mask */ + +#define HSUSBH_UIENR_UERRIEN_Pos (1) /*!< HSUSBH_T::UIENR: UERRIEN Position */ +#define HSUSBH_UIENR_UERRIEN_Msk (0x1ul << HSUSBH_UIENR_UERRIEN_Pos) /*!< HSUSBH_T::UIENR: UERRIEN Mask */ + +#define HSUSBH_UIENR_PCIEN_Pos (2) /*!< HSUSBH_T::UIENR: PCIEN Position */ +#define HSUSBH_UIENR_PCIEN_Msk (0x1ul << HSUSBH_UIENR_PCIEN_Pos) /*!< HSUSBH_T::UIENR: PCIEN Mask */ + +#define HSUSBH_UIENR_FLREN_Pos (3) /*!< HSUSBH_T::UIENR: FLREN Position */ +#define HSUSBH_UIENR_FLREN_Msk (0x1ul << HSUSBH_UIENR_FLREN_Pos) /*!< HSUSBH_T::UIENR: FLREN Mask */ + +#define HSUSBH_UIENR_HSERREN_Pos (4) /*!< HSUSBH_T::UIENR: HSERREN Position */ +#define HSUSBH_UIENR_HSERREN_Msk (0x1ul << HSUSBH_UIENR_HSERREN_Pos) /*!< HSUSBH_T::UIENR: HSERREN Mask */ + +#define HSUSBH_UIENR_IAAEN_Pos (5) /*!< HSUSBH_T::UIENR: IAAEN Position */ +#define HSUSBH_UIENR_IAAEN_Msk (0x1ul << HSUSBH_UIENR_IAAEN_Pos) /*!< HSUSBH_T::UIENR: IAAEN Mask */ + +#define HSUSBH_UFINDR_FI_Pos (0) /*!< HSUSBH_T::UFINDR: FI Position */ +#define HSUSBH_UFINDR_FI_Msk (0x3ffful << HSUSBH_UFINDR_FI_Pos) /*!< HSUSBH_T::UFINDR: FI Mask */ + +#define HSUSBH_UPFLBAR_BADDR_Pos (12) /*!< HSUSBH_T::UPFLBAR: BADDR Position */ +#define HSUSBH_UPFLBAR_BADDR_Msk (0xffffful << HSUSBH_UPFLBAR_BADDR_Pos) /*!< HSUSBH_T::UPFLBAR: BADDR Mask */ + +#define HSUSBH_UCALAR_LPL_Pos (5) /*!< HSUSBH_T::UCALAR: LPL Position */ +#define HSUSBH_UCALAR_LPL_Msk (0x7fffffful << HSUSBH_UCALAR_LPL_Pos) /*!< HSUSBH_T::UCALAR: LPL Mask */ + +#define HSUSBH_UASSTR_ASSTMR_Pos (0) /*!< HSUSBH_T::UASSTR: ASSTMR Position */ +#define HSUSBH_UASSTR_ASSTMR_Msk (0xffful << HSUSBH_UASSTR_ASSTMR_Pos) /*!< HSUSBH_T::UASSTR: ASSTMR Mask */ + +#define HSUSBH_UCFGR_CF_Pos (0) /*!< HSUSBH_T::UCFGR: CF Position */ +#define HSUSBH_UCFGR_CF_Msk (0x1ul << HSUSBH_UCFGR_CF_Pos) /*!< HSUSBH_T::UCFGR: CF Mask */ + +#define HSUSBH_UPSCR_CCS_Pos (0) /*!< HSUSBH_T::UPSCR[2]: CCS Position */ +#define HSUSBH_UPSCR_CCS_Msk (0x1ul << HSUSBH_UPSCR_CCS_Pos) /*!< HSUSBH_T::UPSCR[2]: CCS Mask */ + +#define HSUSBH_UPSCR_CSC_Pos (1) /*!< HSUSBH_T::UPSCR[2]: CSC Position */ +#define HSUSBH_UPSCR_CSC_Msk (0x1ul << HSUSBH_UPSCR_CSC_Pos) /*!< HSUSBH_T::UPSCR[2]: CSC Mask */ + +#define HSUSBH_UPSCR_PE_Pos (2) /*!< HSUSBH_T::UPSCR[2]: PE Position */ +#define HSUSBH_UPSCR_PE_Msk (0x1ul << HSUSBH_UPSCR_PE_Pos) /*!< HSUSBH_T::UPSCR[2]: PE Mask */ + +#define HSUSBH_UPSCR_PEC_Pos (3) /*!< HSUSBH_T::UPSCR[2]: PEC Position */ +#define HSUSBH_UPSCR_PEC_Msk (0x1ul << HSUSBH_UPSCR_PEC_Pos) /*!< HSUSBH_T::UPSCR[2]: PEC Mask */ + +#define HSUSBH_UPSCR_OCA_Pos (4) /*!< HSUSBH_T::UPSCR[2]: OCA Position */ +#define HSUSBH_UPSCR_OCA_Msk (0x1ul << HSUSBH_UPSCR_OCA_Pos) /*!< HSUSBH_T::UPSCR[2]: OCA Mask */ + +#define HSUSBH_UPSCR_OCC_Pos (5) /*!< HSUSBH_T::UPSCR[2]: OCC Position */ +#define HSUSBH_UPSCR_OCC_Msk (0x1ul << HSUSBH_UPSCR_OCC_Pos) /*!< HSUSBH_T::UPSCR[2]: OCC Mask */ + +#define HSUSBH_UPSCR_FPR_Pos (6) /*!< HSUSBH_T::UPSCR[2]: FPR Position */ +#define HSUSBH_UPSCR_FPR_Msk (0x1ul << HSUSBH_UPSCR_FPR_Pos) /*!< HSUSBH_T::UPSCR[2]: FPR Mask */ + +#define HSUSBH_UPSCR_SUSPEND_Pos (7) /*!< HSUSBH_T::UPSCR[2]: SUSPEND Position */ +#define HSUSBH_UPSCR_SUSPEND_Msk (0x1ul << HSUSBH_UPSCR_SUSPEND_Pos) /*!< HSUSBH_T::UPSCR[2]: SUSPEND Mask */ + +#define HSUSBH_UPSCR_PRST_Pos (8) /*!< HSUSBH_T::UPSCR[2]: PRST Position */ +#define HSUSBH_UPSCR_PRST_Msk (0x1ul << HSUSBH_UPSCR_PRST_Pos) /*!< HSUSBH_T::UPSCR[2]: PRST Mask */ + +#define HSUSBH_UPSCR_LSTS_Pos (10) /*!< HSUSBH_T::UPSCR[2]: LSTS Position */ +#define HSUSBH_UPSCR_LSTS_Msk (0x3ul << HSUSBH_UPSCR_LSTS_Pos) /*!< HSUSBH_T::UPSCR[2]: LSTS Mask */ + +#define HSUSBH_UPSCR_PP_Pos (12) /*!< HSUSBH_T::UPSCR[2]: PP Position */ +#define HSUSBH_UPSCR_PP_Msk (0x1ul << HSUSBH_UPSCR_PP_Pos) /*!< HSUSBH_T::UPSCR[2]: PP Mask */ + +#define HSUSBH_UPSCR_PO_Pos (13) /*!< HSUSBH_T::UPSCR[2]: PO Position */ +#define HSUSBH_UPSCR_PO_Msk (0x1ul << HSUSBH_UPSCR_PO_Pos) /*!< HSUSBH_T::UPSCR[2]: PO Mask */ + +#define HSUSBH_UPSCR_PTC_Pos (16) /*!< HSUSBH_T::UPSCR[2]: PTC Position */ +#define HSUSBH_UPSCR_PTC_Msk (0xful << HSUSBH_UPSCR_PTC_Pos) /*!< HSUSBH_T::UPSCR[2]: PTC Mask */ + +#define HSUSBH_USBPCR0_SUSPEND_Pos (8) /*!< HSUSBH_T::USBPCR0: SUSPEND Position */ +#define HSUSBH_USBPCR0_SUSPEND_Msk (0x1ul << HSUSBH_USBPCR0_SUSPEND_Pos) /*!< HSUSBH_T::USBPCR0: SUSPEND Mask */ + +#define HSUSBH_USBPCR0_CLKVALID_Pos (11) /*!< HSUSBH_T::USBPCR0: CLKVALID Position */ +#define HSUSBH_USBPCR0_CLKVALID_Msk (0x1ul << HSUSBH_USBPCR0_CLKVALID_Pos) /*!< HSUSBH_T::USBPCR0: CLKVALID Mask */ + +#define HSUSBH_USBPCR1_SUSPEND_Pos (8) /*!< HSUSBH_T::USBPCR1: SUSPEND Position */ +#define HSUSBH_USBPCR1_SUSPEND_Msk (0x1ul << HSUSBH_USBPCR1_SUSPEND_Pos) /*!< HSUSBH_T::USBPCR1: SUSPEND Mask */ + +/**@}*/ /* HSUSBH_CONST */ +/**@}*/ /* end of HSUSBH register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __HSUSBH_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/i2c_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/i2c_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..adbd03fa572a7f43ef540d5ae21c79be558ad58c --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/i2c_reg.h @@ -0,0 +1,725 @@ +/**************************************************************************//** + * @file i2c_reg.h + * @version V1.00 + * @brief I2C register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __I2C_REG_H__ +#define __I2C_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup I2C Inter-IC Bus Controller(I2C) + Memory Mapped Structure for I2C Controller +@{ */ + +typedef struct +{ + + + /** + * @var I2C_T::CTL0 + * Offset: 0x00 I2C Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2] |AA |Assert Acknowledge Control + * | | |When AA =1 prior to address or data is received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter + * | | |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line + * |[3] |SI |I2C Interrupt Flag + * | | |When a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware + * | | |If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested + * | | |SI must be cleared by software + * | | |Clear SI by writing 1 to this bit. + * | | |For ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer. + * |[4] |STO |I2C STOP Control + * | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected + * | | |This bit will be cleared by hardware automatically. + * |[5] |STA |I2C START Control + * | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. + * |[6] |I2CEN |I2C Controller Enable Bit + * | | |Set to enable I2C serial function controller + * | | |When I2CEN=1 the I2C serial function enable + * | | |The multi-function pin function must set to SDA, and SCL of I2C function first. + * | | |0 = I2C controller Disabled. + * | | |1 = I2C controller Enabled. + * |[7] |INTEN |Enable Interrupt + * | | |0 = I2C interrupt Disabled. + * | | |1 = I2C interrupt Enabled. + * @var I2C_T::ADDR0 + * Offset: 0x04 I2C Slave Address Register0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GC |General Call Function + * | | |0 = General Call Function Disabled. + * | | |1 = General Call Function Enabled. + * |[10:1] |ADDR |I2C Address + * | | |The content of this register is irrelevant when I2C is in Master mode + * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address + * | | |The I2C hardware will react if either of the address is matched. + * | | |Note: When software set 10'h000, the address can not be used. + * @var I2C_T::DAT + * Offset: 0x08 I2C Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DAT |I2C Data + * | | |Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port. + * @var I2C_T::STATUS0 + * Offset: 0x0C I2C Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |STATUS |I2C Status + * | | |The three least significant bits are always 0 + * | | |The five most significant bits contain the status code + * | | |There are 28 possible status codes + * | | |When the content of I2C_STATUS is F8H, no serial interrupt is requested + * | | |Others I2C_STATUS values correspond to defined I2C states + * | | |When each of these states is entered, a status interrupt is requested (SI = 1) + * | | |A valid status code is present in I2C_STATUS one cycle after SI is set by hardware and is still present one cycle after SI has been reset by software + * | | |In addition, states 00H stands for a Bus Error + * | | |A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame + * | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit. + * @var I2C_T::CLKDIV + * Offset: 0x10 I2C Clock Divided Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |DIVIDER |I2C Clock Divided + * | | |Indicates the I2C clock rate: Data Baud Rate of I2C = (system clock) / (4x (I2C_CLKDIV+1)). + * | | |Note: The minimum value of I2C_CLKDIV is 4. + * @var I2C_T::TOCTL + * Offset: 0x14 I2C Time-out Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TOIF |Time-out Flag + * | | |This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1. + * | | |Note: Software can write 1 to clear this bit. + * |[1] |TOCDIV4 |Time-out Counter Input Clock Divided by 4 + * | | |When Enabled, The time-out period is extend 4 times. + * | | |0 = Time-out period is extend 4 times Disabled. + * | | |1 = Time-out period is extend 4 times Enabled. + * |[2] |TOCEN |Time-out Counter Enable Bit + * | | |When Enabled, the 14-bit time-out counter will start counting when SI is clear + * | | |Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared. + * | | |0 = Time-out counter Disabled. + * | | |1 = Time-out counter Enabled. + * @var I2C_T::ADDR1 + * Offset: 0x18 I2C Slave Address Register1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GC |General Call Function + * | | |0 = General Call Function Disabled. + * | | |1 = General Call Function Enabled. + * |[10:1] |ADDR |I2C Address + * | | |The content of this register is irrelevant when I2C is in Master mode + * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address + * | | |The I2C hardware will react if either of the address is matched. + * | | |Note: When software set 10'h000, the address can not be used. + * @var I2C_T::ADDR2 + * Offset: 0x1C I2C Slave Address Register2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GC |General Call Function + * | | |0 = General Call Function Disabled. + * | | |1 = General Call Function Enabled. + * |[10:1] |ADDR |I2C Address + * | | |The content of this register is irrelevant when I2C is in Master mode + * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address + * | | |The I2C hardware will react if either of the address is matched. + * | | |Note: When software set 10'h000, the address can not be used. + * @var I2C_T::ADDR3 + * Offset: 0x20 I2C Slave Address Register3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GC |General Call Function + * | | |0 = General Call Function Disabled. + * | | |1 = General Call Function Enabled. + * |[10:1] |ADDR |I2C Address + * | | |The content of this register is irrelevant when I2C is in Master mode + * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address + * | | |The I2C hardware will react if either of the address is matched. + * | | |Note: When software set 10'h000, the address can not be used. + * @var I2C_T::ADDRMSK0 + * Offset: 0x24 I2C Slave Address Mask Register0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:1] |ADDRMSK |I2C Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |I2C bus controllers support multiple address recognition with four address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not use address mask. + * @var I2C_T::ADDRMSK1 + * Offset: 0x28 I2C Slave Address Mask Register1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:1] |ADDRMSK |I2C Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |I2C bus controllers support multiple address recognition with four address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not use address mask. + * @var I2C_T::ADDRMSK2 + * Offset: 0x2C I2C Slave Address Mask Register2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:1] |ADDRMSK |I2C Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |I2C bus controllers support multiple address recognition with four address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not use address mask. + * @var I2C_T::ADDRMSK3 + * Offset: 0x30 I2C Slave Address Mask Register3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:1] |ADDRMSK |I2C Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |I2C bus controllers support multiple address recognition with four address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not use address mask. + * @var I2C_T::WKCTL + * Offset: 0x3C I2C Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |I2C Wake-up Enable Bit + * | | |0 = I2C wake-up function Disabled. + * | | |1 = I2C wake-up function Enabled. + * |[7] |NHDBUSEN |I2C No Hold BUS Enable Bit + * | | |0 = I2C hold bus after wake-up. + * | | |1 = I2C don't hold bus after wake-up. + * | | |Note: I2C controller could response when WKIF event is not clear, it may cause error data transmitted or received + * | | |If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again. + * @var I2C_T::WKSTS + * Offset: 0x40 I2C Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKIF |I2C Wake-up Flag + * | | |When chip is woken up from Power-down mode by I2C, this bit is set to 1 + * | | |Software can write 1 to clear this bit. + * |[1] |WKAKDONE |Wakeup Address Frame Acknowledge Bit Done + * | | |0 = The ACK bit cycle of address match frame isn't done. + * | | |1 = The ACK bit cycle of address match frame is done in power-down. + * | | |Note: This bit can't release WKIF. Software can write 1 to clear this bit. + * |[2] |WRSTSWK |Read/Write Status Bit in Address Wakeup Frame + * | | |0 = Write command be record on the address match wakeup frame. + * | | |1 = Read command be record on the address match wakeup frame. + * | | |Note: This bit will be cleared when software can write 1 to WKAKDONE bit. + * @var I2C_T::CTL1 + * Offset: 0x44 I2C Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TXPDMAEN |PDMA Transmit Channel Available + * | | |0 = Transmit PDMA function disable. + * | | |1 = Transmit PDMA function enable. + * |[1] |RXPDMAEN |PDMA Receive Channel Available + * | | |0 = Receive PDMA function disable. + * | | |1 = Receive PDMA function enable. + * |[2] |PDMARST |PDMA Reset + * | | |0 = No effect. + * | | |1 = Reset the I2C request to PDMA. + * |[8] |PDMASTR |PDMA Stretch Bit + * | | |0 = I2C send STOP automatically after PDMA transfer done. (only master TX) + * | | |1 = I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared + * | | |(only master TX) + * |[9] |ADDR10EN |Address 10-bit Function Enable + * | | |0 = Address match 10-bit function is disabled. + * | | |1 = Address match 10-bit function is enabled. + * @var I2C_T::STATUS1 + * Offset: 0x48 I2C Status Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADMAT0 |I2C Address 0 Match Status Register + * | | |When address 0 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * |[1] |ADMAT1 |I2C Address 1 Match Status Register + * | | |When address 1 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * |[2] |ADMAT2 |I2C Address 2 Match Status Register + * | | |When address 2 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * |[3] |ADMAT3 |I2C Address 3 Match Status Register + * | | |When address 3 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * |[8] |ONBUSY |On Bus Busy + * | | |Indicates that a communication is in progress on the bus + * | | |It is set by hardware when a START condition is detected + * | | |It is cleared by hardware when a STOP condition is detected. + * | | |0 = The bus is IDLE (both SCLK and SDA High). + * | | |1 = The bus is busy. + * | | |Note:This bit is read only. + * @var I2C_T::TMCTL + * Offset: 0x4C I2C Timing Configure Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |STCTL |Setup Time Configure Control Register + * | | |This field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode. + * | | |The delay setup time is numbers of peripheral clock = STCTL x PCLK. + * | | |Note: Setup time setting should not make SCL output less than three PCLKs. + * |[24:16] |HTCTL |Hold Time Configure Control Register + * | | |This field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode. + * | | |The delay hold time is numbers of peripheral clock = HTCTL x PCLK. + * @var I2C_T::BUSCTL + * Offset: 0x50 I2C Bus Management Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ACKMEN |Acknowledge Control by Manual + * | | |In order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit. + * | | |0 = Slave byte control Disabled. + * | | |1 = Slave byte control Enabled + * | | |The 9th bit can response the ACK or NACK according the received data by user + * | | |When the byte is received, stretching the SCLK signal low between the 8th and 9th SCLK pulse. + * | | |Note: If the BMDEN=1 and this bit is enabled, the information of I2C_STATUS will be fixed as 0xF0 in slave receive condition. + * |[1] |PECEN |Packet Error Checking Calculation Enable Bit + * | | |0 = Packet Error Checking Calculation Disabled. + * | | |1 = Packet Error Checking Calculation Enabled. + * | | |Note: When I2C enter power down mode, the bit should be enabled after wake-up if needed PEC calculation. + * |[2] |BMDEN |Bus Management Device Default Address Enable Bit + * | | |0 = Device default address Disable + * | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses NACKed + * | | |1 = Device default address Enabled + * | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses ACKed. + * |[3] |BMHEN |Bus Management Host Enable Bit + * | | |0 = Host function Disabled. + * | | |1 = Host function Enabled. + * |[4] |ALERTEN |Bus Management Alert Enable Bit + * | | |Device Mode (BMHEN=0). + * | | |0 = Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled. + * | | |1 = Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled. + * | | |Host Mode (BMHEN=1). + * | | |0 = BM_ALERT pin not supported. + * | | |1 = BM_ALERT pin supported. + * |[5] |SCTLOSTS |Suspend/Control Data Output Status + * | | |0 = The output of SUSCON pin is low. + * | | |1 = The output of SUSCON pin is high. + * |[6] |SCTLOEN |Suspend or Control Pin Output Enable Bit + * | | |0 = The SUSCON pin in input. + * | | |1 = The output enable is active on the SUSCON pin. + * |[7] |BUSEN |BUS Enable Bit + * | | |0 = The system management function is Disabled. + * | | |1 = The system management function is Enable. + * | | |Note: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition. + * |[8] |PECTXEN |Packet Error Checking Byte Transmission/Reception + * | | |0 = No PEC transfer. + * | | |1 = PEC transmission is requested. + * | | |Note: This bit has no effect in slave mode when ACKMEN=0. + * |[9] |TIDLE |Timer Check in Idle State + * | | |The BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle + * | | |This bit is used to define which condition is enabled. + * | | |0 = The BUSTOUT is used to calculate the clock low period in bus active. + * | | |1 = The BUSTOUT is used to calculate the IDLE period in bus Idle. + * | | |Note: The BUSY (I2C_BUSSTS[0]) indicate the current bus state. + * |[10] |PECCLR |PEC Clear at Repeat Start + * | | |The calculation of PEC starts when PECEN is set to 1 and it is clear when the STA or STO bit is detected + * | | |This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation. + * | | |0 = The PEC calculation is cleared by "Repeat Start" function is Disabled. + * | | |1 = The PEC calculation is cleared by "Repeat Start"" function is Enabled. + * |[11] |ACKM9SI |Acknowledge Manual Enable Extra SI Interrupt + * | | |0 = There is no SI interrupt in the 9th clock cycle when the BUSEN=1 and ACKMEN=1. + * | | |1 = There is SI interrupt in the 9th clock cycle when the BUSEN=1 and ACKMEN=1. + * |[12] |BCDIEN |Packet Error Checking Byte Count Done Interrupt Enable Bit + * | | |0 = Indicates the byte count done interrupt is Disabled. + * | | |1 = Indicates the byte count done interrupt is Enabled. + * | | |Note: This bit is used in PECEN=1. + * |[13] |PECDIEN |Packet Error Checking Byte Transfer Done Interrupt Enable Bit + * | | |0 = Indicates the PEC transfer done interrupt is Disabled. + * | | |1 = Indicates the PEC transfer done interrupt is Enabled. + * | | |Note: This bit is used in PECEN=1. + * @var I2C_T::BUSTCTL + * Offset: 0x54 I2C Bus Management Timer Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSTOEN |Bus Time Out Enable Bit + * | | |0 = Indicates the bus clock low time-out detection is Disabled. + * | | |1 = Indicates the bus clock low time-out detection is Enabled (bus clock is low for more than TTime-out (in BIDLE=0) or high more than TTime-out(in BIDLE =1) + * |[1] |CLKTOEN |Cumulative Clock Low Time Out Enable Bit + * | | |0 = Indicates the cumulative clock low time-out detection is Disabled. + * | | |1 = Indicates the cumulative clock low time-out detection is Enabled. + * | | |For Master, it calculates the period from START to ACK + * | | |For Slave, it calculates the period from START to STOP + * |[2] |BUSTOIEN |Time-out Interrupt Enable Bit + * | | |BUSY =1. + * | | |0 = Indicates the SCLK low time-out interrupt is Disabled. + * | | |1 = Indicates the SCLK low time-out interrupt is Enabled. + * | | |BUSY =0. + * | | |0 = Indicates the bus IDLE time-out interrupt is Disabled. + * | | |1 = Indicates the bus IDLE time-out interrupt is Enabled. + * |[3] |CLKTOIEN |Extended Clock Time Out Interrupt Enable Bit + * | | |0 = Indicates the clock time out interrupt is Disabled. + * | | |1 = Indicates the clock time out interrupt is Enabled. + * |[4] |TORSTEN |Time Out Reset Enable Bit + * | | |0 = Indicates the I2C state machine reset is Disable. + * | | |1 = Indicates the I2C state machine reset is Enable. (The clock and data bus will be released to high) + * @var I2C_T::BUSSTS + * Offset: 0x58 I2C Bus Management Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |Bus Busy + * | | |Indicates that a communication is in progress on the bus + * | | |It is set by hardware when a START condition is detected + * | | |It is cleared by hardware when a STOP condition is detected + * | | |0 = The bus is IDLE (both SCLK and SDA High). + * | | |1 = The bus is busy. + * |[1] |BCDONE |Byte Count Transmission/Receive Done + * | | |0 = Indicates the byte count transmission/ receive is not finished when the PECEN is set. + * | | |1 = Indicates the byte count transmission/ receive is finished when the PECEN is set. + * | | |Note: Software can write 1 to clear this bit. + * |[2] |PECERR |PEC Error in Reception + * | | |0 = Indicates the PEC value equal the received PEC data packet. + * | | |1 = Indicates the PEC value doesn't match the receive PEC data packet. + * | | |Note: Software can write 1 to clear this bit. + * |[3] |ALERT |SMBus Alert Status + * | | |Device Mode (BMHEN =0). + * | | |0 = Indicates SMBALERT pin state is low. + * | | |1 = Indicates SMBALERT pin state is high. + * | | |Host Mode (BMHEN =1). + * | | |0 = No SMBALERT event. + * | | |1 = Indicates there is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1. + * | | |Note: + * | | |1. The SMBALERT pin is an open-drain pin, the pull-high resistor is must in the system + * | | |2. Software can write 1 to clear this bit. + * |[4] |SCTLDIN |Bus Suspend or Control Signal Input Status + * | | |0 = The input status of SUSCON pin is 0. + * | | |1 = The input status of SUSCON pin is 1. + * |[5] |BUSTO |Bus Time-out Status + * | | |0 = Indicates that there is no any time-out or external clock time-out. + * | | |1 = Indicates that a time-out or external clock time-out occurred. + * | | |In bus busy, the bit indicates the total clock low time-out event occurred otherwise, it indicates the bus idle time-out event occurred. + * | | |Note: Software can write 1 to clear this bit. + * |[6] |CLKTO |Clock Low Cumulate Time-out Status + * | | |0 = Indicates that the cumulative clock low is no any time-out. + * | | |1 = Indicates that the cumulative clock low time-out occurred. + * | | |Note: Software can write 1 to clear this bit. + * |[7] |PECDONE |PEC Byte Transmission/Receive Done + * | | |0 = Indicates the PEC transmission/ receive is not finished when the PECEN is set. + * | | |1 = Indicates the PEC transmission/ receive is finished when the PECEN is set. + * | | |Note: Software can write 1 to clear this bit. + * @var I2C_T::PKTSIZE + * Offset: 0x5C I2C Packet Error Checking Byte Number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |PLDSIZE |Transfer Byte Number + * | | |The transmission or receive byte number in one transaction when the PECEN is set + * | | |The maximum transaction or receive byte is 256 Bytes. + * | | |Notice: The byte number counting includes address, command code, and data frame. + * @var I2C_T::PKTCRC + * Offset: 0x60 I2C Packet Error Checking Byte Value Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |PECCRC |Packet Error Checking Byte Value + * | | |This byte indicates the packet error checking content after transmission or receive byte count by using the C(x) = X8 + X2 + X + 1 + * | | |It is read only. + * @var I2C_T::BUSTOUT + * Offset: 0x64 I2C Bus Management Timer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |BUSTO |Bus Management Time-out Value + * | | |Indicate the bus time-out value in bus is IDLE or SCLK low. + * | | |Note: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]) is set. + * @var I2C_T::CLKTOUT + * Offset: 0x68 I2C Bus Management Clock Low Timer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |CLKTO |Bus Clock Low Timer + * | | |The field is used to configure the cumulative clock extension time-out. + * | | |Note: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and clear to 0 first in the BUSEN is set. + */ + __IO uint32_t CTL0; /*!< [0x0000] I2C Control Register 0 */ + __IO uint32_t ADDR0; /*!< [0x0004] I2C Slave Address Register0 */ + __IO uint32_t DAT; /*!< [0x0008] I2C Data Register */ + __I uint32_t STATUS0; /*!< [0x000c] I2C Status Register 0 */ + __IO uint32_t CLKDIV; /*!< [0x0010] I2C Clock Divided Register */ + __IO uint32_t TOCTL; /*!< [0x0014] I2C Time-out Control Register */ + __IO uint32_t ADDR1; /*!< [0x0018] I2C Slave Address Register1 */ + __IO uint32_t ADDR2; /*!< [0x001c] I2C Slave Address Register2 */ + __IO uint32_t ADDR3; /*!< [0x0020] I2C Slave Address Register3 */ + __IO uint32_t ADDRMSK0; /*!< [0x0024] I2C Slave Address Mask Register0 */ + __IO uint32_t ADDRMSK1; /*!< [0x0028] I2C Slave Address Mask Register1 */ + __IO uint32_t ADDRMSK2; /*!< [0x002c] I2C Slave Address Mask Register2 */ + __IO uint32_t ADDRMSK3; /*!< [0x0030] I2C Slave Address Mask Register3 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t WKCTL; /*!< [0x003c] I2C Wake-up Control Register */ + __IO uint32_t WKSTS; /*!< [0x0040] I2C Wake-up Status Register */ + __IO uint32_t CTL1; /*!< [0x0044] I2C Control Register 1 */ + __IO uint32_t STATUS1; /*!< [0x0048] I2C Status Register 1 */ + __IO uint32_t TMCTL; /*!< [0x004c] I2C Timing Configure Control Register */ + __IO uint32_t BUSCTL; /*!< [0x0050] I2C Bus Management Control Register */ + __IO uint32_t BUSTCTL; /*!< [0x0054] I2C Bus Management Timer Control Register */ + __IO uint32_t BUSSTS; /*!< [0x0058] I2C Bus Management Status Register */ + __IO uint32_t PKTSIZE; /*!< [0x005c] I2C Packet Error Checking Byte Number Register */ + __I uint32_t PKTCRC; /*!< [0x0060] I2C Packet Error Checking Byte Value Register */ + __IO uint32_t BUSTOUT; /*!< [0x0064] I2C Bus Management Timer Register */ + __IO uint32_t CLKTOUT; /*!< [0x0068] I2C Bus Management Clock Low Timer Register */ + +} I2C_T; + +/** + @addtogroup I2C_CONST I2C Bit Field Definition + Constant Definitions for I2C Controller +@{ */ + +#define I2C_CTL0_AA_Pos (2) /*!< I2C_T::CTL: AA Position */ +#define I2C_CTL0_AA_Msk (0x1ul << I2C_CTL0_AA_Pos) /*!< I2C_T::CTL: AA Mask */ + +#define I2C_CTL0_SI_Pos (3) /*!< I2C_T::CTL: SI Position */ +#define I2C_CTL0_SI_Msk (0x1ul << I2C_CTL0_SI_Pos) /*!< I2C_T::CTL: SI Mask */ + +#define I2C_CTL0_STO_Pos (4) /*!< I2C_T::CTL: STO Position */ +#define I2C_CTL0_STO_Msk (0x1ul << I2C_CTL0_STO_Pos) /*!< I2C_T::CTL: STO Mask */ + +#define I2C_CTL0_STA_Pos (5) /*!< I2C_T::CTL: STA Position */ +#define I2C_CTL0_STA_Msk (0x1ul << I2C_CTL0_STA_Pos) /*!< I2C_T::CTL: STA Mask */ + +#define I2C_CTL0_I2CEN_Pos (6) /*!< I2C_T::CTL: I2CEN Position */ +#define I2C_CTL0_I2CEN_Msk (0x1ul << I2C_CTL0_I2CEN_Pos) /*!< I2C_T::CTL: I2CEN Mask */ + +#define I2C_CTL0_INTEN_Pos (7) /*!< I2C_T::CTL: INTEN Position */ +#define I2C_CTL0_INTEN_Msk (0x1ul << I2C_CTL0_INTEN_Pos) /*!< I2C_T::CTL: INTEN Mask */ + +#define I2C_ADDR0_GC_Pos (0) /*!< I2C_T::ADDR0: GC Position */ +#define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos) /*!< I2C_T::ADDR0: GC Mask */ + +#define I2C_ADDR0_ADDR_Pos (1) /*!< I2C_T::ADDR0: ADDR Position */ +#define I2C_ADDR0_ADDR_Msk (0x3fful << I2C_ADDR0_ADDR_Pos) /*!< I2C_T::ADDR0: ADDR Mask */ + +#define I2C_DAT_DAT_Pos (0) /*!< I2C_T::DAT: DAT Position */ +#define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos) /*!< I2C_T::DAT: DAT Mask */ + +#define I2C_STATUS0_STATUS_Pos (0) /*!< I2C_T::STATUS: STATUS Position */ +#define I2C_STATUS0_STATUS_Msk (0xfful << I2C_STATUS_STATUS0_Pos) /*!< I2C_T::STATUS: STATUS Mask */ + +#define I2C_CLKDIV_DIVIDER_Pos (0) /*!< I2C_T::CLKDIV: DIVIDER Position */ +#define I2C_CLKDIV_DIVIDER_Msk (0x3fful << I2C_CLKDIV_DIVIDER_Pos) /*!< I2C_T::CLKDIV: DIVIDER Mask */ + +#define I2C_TOCTL_TOIF_Pos (0) /*!< I2C_T::TOCTL: TOIF Position */ +#define I2C_TOCTL_TOIF_Msk (0x1ul << I2C_TOCTL_TOIF_Pos) /*!< I2C_T::TOCTL: TOIF Mask */ + +#define I2C_TOCTL_TOCDIV4_Pos (1) /*!< I2C_T::TOCTL: TOCDIV4 Position */ +#define I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos) /*!< I2C_T::TOCTL: TOCDIV4 Mask */ + +#define I2C_TOCTL_TOCEN_Pos (2) /*!< I2C_T::TOCTL: TOCEN Position */ +#define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos) /*!< I2C_T::TOCTL: TOCEN Mask */ + +#define I2C_ADDR1_GC_Pos (0) /*!< I2C_T::ADDR1: GC Position */ +#define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos) /*!< I2C_T::ADDR1: GC Mask */ + +#define I2C_ADDR1_ADDR_Pos (1) /*!< I2C_T::ADDR1: ADDR Position */ +#define I2C_ADDR1_ADDR_Msk (0x3fful << I2C_ADDR1_ADDR_Pos) /*!< I2C_T::ADDR1: ADDR Mask */ + +#define I2C_ADDR2_GC_Pos (0) /*!< I2C_T::ADDR2: GC Position */ +#define I2C_ADDR2_GC_Msk (0x1ul << I2C_ADDR2_GC_Pos) /*!< I2C_T::ADDR2: GC Mask */ + +#define I2C_ADDR2_ADDR_Pos (1) /*!< I2C_T::ADDR2: ADDR Position */ +#define I2C_ADDR2_ADDR_Msk (0x3fful << I2C_ADDR2_ADDR_Pos) /*!< I2C_T::ADDR2: ADDR Mask */ + +#define I2C_ADDR3_GC_Pos (0) /*!< I2C_T::ADDR3: GC Position */ +#define I2C_ADDR3_GC_Msk (0x1ul << I2C_ADDR3_GC_Pos) /*!< I2C_T::ADDR3: GC Mask */ + +#define I2C_ADDR3_ADDR_Pos (1) /*!< I2C_T::ADDR3: ADDR Position */ +#define I2C_ADDR3_ADDR_Msk (0x3fful << I2C_ADDR3_ADDR_Pos) /*!< I2C_T::ADDR3: ADDR Mask */ + +#define I2C_ADDRMSK0_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK0: ADDRMSK Position */ +#define I2C_ADDRMSK0_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK0_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK0: ADDRMSK Mask */ + +#define I2C_ADDRMSK1_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK1: ADDRMSK Position */ +#define I2C_ADDRMSK1_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK1_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK1: ADDRMSK Mask */ + +#define I2C_ADDRMSK2_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK2: ADDRMSK Position */ +#define I2C_ADDRMSK2_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK2_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK2: ADDRMSK Mask */ + +#define I2C_ADDRMSK3_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK3: ADDRMSK Position */ +#define I2C_ADDRMSK3_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK3_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK3: ADDRMSK Mask */ + +#define I2C_WKCTL_WKEN_Pos (0) /*!< I2C_T::WKCTL: WKEN Position */ +#define I2C_WKCTL_WKEN_Msk (0x1ul << I2C_WKCTL_WKEN_Pos) /*!< I2C_T::WKCTL: WKEN Mask */ + +#define I2C_WKCTL_NHDBUSEN_Pos (7) /*!< I2C_T::WKCTL: NHDBUSEN Position */ +#define I2C_WKCTL_NHDBUSEN_Msk (0x1ul << I2C_WKCTL_NHDBUSEN_Pos) /*!< I2C_T::WKCTL: NHDBUSEN Mask */ + +#define I2C_WKSTS_WKIF_Pos (0) /*!< I2C_T::WKSTS: WKIF Position */ +#define I2C_WKSTS_WKIF_Msk (0x1ul << I2C_WKSTS_WKIF_Pos) /*!< I2C_T::WKSTS: WKIF Mask */ + +#define I2C_WKSTS_WKAKDONE_Pos (1) /*!< I2C_T::WKSTS: WKAKDONE Position */ +#define I2C_WKSTS_WKAKDONE_Msk (0x1ul << I2C_WKSTS_WKAKDONE_Pos) /*!< I2C_T::WKSTS: WKAKDONE Mask */ + +#define I2C_WKSTS_WRSTSWK_Pos (2) /*!< I2C_T::WKSTS: WRSTSWK Position */ +#define I2C_WKSTS_WRSTSWK_Msk (0x1ul << I2C_WKSTS_WRSTSWK_Pos) /*!< I2C_T::WKSTS: WRSTSWK Mask */ + +#define I2C_CTL1_TXPDMAEN_Pos (0) /*!< I2C_T::CTL1: TXPDMAEN Position */ +#define I2C_CTL1_TXPDMAEN_Msk (0x1ul << I2C_CTL1_TXPDMAEN_Pos) /*!< I2C_T::CTL1: TXPDMAEN Mask */ + +#define I2C_CTL1_RXPDMAEN_Pos (1) /*!< I2C_T::CTL1: RXPDMAEN Position */ +#define I2C_CTL1_RXPDMAEN_Msk (0x1ul << I2C_CTL1_RXPDMAEN_Pos) /*!< I2C_T::CTL1: RXPDMAEN Mask */ + +#define I2C_CTL1_PDMARST_Pos (2) /*!< I2C_T::CTL1: PDMARST Position */ +#define I2C_CTL1_PDMARST_Msk (0x1ul << I2C_CTL1_PDMARST_Pos) /*!< I2C_T::CTL1: PDMARST Mask */ + +#define I2C_CTL1_PDMASTR_Pos (8) /*!< I2C_T::CTL1: PDMASTR Position */ +#define I2C_CTL1_PDMASTR_Msk (0x1ul << I2C_CTL1_PDMASTR_Pos) /*!< I2C_T::CTL1: PDMASTR Mask */ + +#define I2C_CTL1_ADDR10EN_Pos (9) /*!< I2C_T::CTL1: ADDR10EN Position */ +#define I2C_CTL1_ADDR10EN_Msk (0x1ul << I2C_CTL1_ADDR10EN_Pos) /*!< I2C_T::CTL1: ADDR10EN Mask */ + +#define I2C_STATUS1_ADMAT0_Pos (0) /*!< I2C_T::STATUS1: ADMAT0 Position */ +#define I2C_STATUS1_ADMAT0_Msk (0x1ul << I2C_STATUS1_ADMAT0_Pos) /*!< I2C_T::STATUS1: ADMAT0 Mask */ + +#define I2C_STATUS1_ADMAT1_Pos (1) /*!< I2C_T::STATUS1: ADMAT1 Position */ +#define I2C_STATUS1_ADMAT1_Msk (0x1ul << I2C_STATUS1_ADMAT1_Pos) /*!< I2C_T::STATUS1: ADMAT1 Mask */ + +#define I2C_STATUS1_ADMAT2_Pos (2) /*!< I2C_T::STATUS1: ADMAT2 Position */ +#define I2C_STATUS1_ADMAT2_Msk (0x1ul << I2C_STATUS1_ADMAT2_Pos) /*!< I2C_T::STATUS1: ADMAT2 Mask */ + +#define I2C_STATUS1_ADMAT3_Pos (3) /*!< I2C_T::STATUS1: ADMAT3 Position */ +#define I2C_STATUS1_ADMAT3_Msk (0x1ul << I2C_STATUS1_ADMAT3_Pos) /*!< I2C_T::STATUS1: ADMAT3 Mask */ + +#define I2C_STATUS1_ONBUSY_Pos (8) /*!< I2C_T::STATUS1: ONBUSY Position */ +#define I2C_STATUS1_ONBUSY_Msk (0x1ul << I2C_STATUS1_ONBUSY_Pos) /*!< I2C_T::STATUS1: ONBUSY Mask */ + +#define I2C_TMCTL_STCTL_Pos (0) /*!< I2C_T::TMCTL: STCTL Position */ +#define I2C_TMCTL_STCTL_Msk (0x1fful << I2C_TMCTL_STCTL_Pos) /*!< I2C_T::TMCTL: STCTL Mask */ + +#define I2C_TMCTL_HTCTL_Pos (16) /*!< I2C_T::TMCTL: HTCTL Position */ +#define I2C_TMCTL_HTCTL_Msk (0x1fful << I2C_TMCTL_HTCTL_Pos) /*!< I2C_T::TMCTL: HTCTL Mask */ + +#define I2C_BUSCTL_ACKMEN_Pos (0) /*!< I2C_T::BUSCTL: ACKMEN Position */ +#define I2C_BUSCTL_ACKMEN_Msk (0x1ul << I2C_BUSCTL_ACKMEN_Pos) /*!< I2C_T::BUSCTL: ACKMEN Mask */ + +#define I2C_BUSCTL_PECEN_Pos (1) /*!< I2C_T::BUSCTL: PECEN Position */ +#define I2C_BUSCTL_PECEN_Msk (0x1ul << I2C_BUSCTL_PECEN_Pos) /*!< I2C_T::BUSCTL: PECEN Mask */ + +#define I2C_BUSCTL_BMDEN_Pos (2) /*!< I2C_T::BUSCTL: BMDEN Position */ +#define I2C_BUSCTL_BMDEN_Msk (0x1ul << I2C_BUSCTL_BMDEN_Pos) /*!< I2C_T::BUSCTL: BMDEN Mask */ + +#define I2C_BUSCTL_BMHEN_Pos (3) /*!< I2C_T::BUSCTL: BMHEN Position */ +#define I2C_BUSCTL_BMHEN_Msk (0x1ul << I2C_BUSCTL_BMHEN_Pos) /*!< I2C_T::BUSCTL: BMHEN Mask */ + +#define I2C_BUSCTL_ALERTEN_Pos (4) /*!< I2C_T::BUSCTL: ALERTEN Position */ +#define I2C_BUSCTL_ALERTEN_Msk (0x1ul << I2C_BUSCTL_ALERTEN_Pos) /*!< I2C_T::BUSCTL: ALERTEN Mask */ + +#define I2C_BUSCTL_SCTLOSTS_Pos (5) /*!< I2C_T::BUSCTL: SCTLOSTS Position */ +#define I2C_BUSCTL_SCTLOSTS_Msk (0x1ul << I2C_BUSCTL_SCTLOSTS_Pos) /*!< I2C_T::BUSCTL: SCTLOSTS Mask */ + +#define I2C_BUSCTL_SCTLOEN_Pos (6) /*!< I2C_T::BUSCTL: SCTLOEN Position */ +#define I2C_BUSCTL_SCTLOEN_Msk (0x1ul << I2C_BUSCTL_SCTLOEN_Pos) /*!< I2C_T::BUSCTL: SCTLOEN Mask */ + +#define I2C_BUSCTL_BUSEN_Pos (7) /*!< I2C_T::BUSCTL: BUSEN Position */ +#define I2C_BUSCTL_BUSEN_Msk (0x1ul << I2C_BUSCTL_BUSEN_Pos) /*!< I2C_T::BUSCTL: BUSEN Mask */ + +#define I2C_BUSCTL_PECTXEN_Pos (8) /*!< I2C_T::BUSCTL: PECTXEN Position */ +#define I2C_BUSCTL_PECTXEN_Msk (0x1ul << I2C_BUSCTL_PECTXEN_Pos) /*!< I2C_T::BUSCTL: PECTXEN Mask */ + +#define I2C_BUSCTL_TIDLE_Pos (9) /*!< I2C_T::BUSCTL: TIDLE Position */ +#define I2C_BUSCTL_TIDLE_Msk (0x1ul << I2C_BUSCTL_TIDLE_Pos) /*!< I2C_T::BUSCTL: TIDLE Mask */ + +#define I2C_BUSCTL_PECCLR_Pos (10) /*!< I2C_T::BUSCTL: PECCLR Position */ +#define I2C_BUSCTL_PECCLR_Msk (0x1ul << I2C_BUSCTL_PECCLR_Pos) /*!< I2C_T::BUSCTL: PECCLR Mask */ + +#define I2C_BUSCTL_ACKM9SI_Pos (11) /*!< I2C_T::BUSCTL: ACKM9SI Position */ +#define I2C_BUSCTL_ACKM9SI_Msk (0x1ul << I2C_BUSCTL_ACKM9SI_Pos) /*!< I2C_T::BUSCTL: ACKM9SI Mask */ + +#define I2C_BUSCTL_BCDIEN_Pos (12) /*!< I2C_T::BUSCTL: BCDIEN Position */ +#define I2C_BUSCTL_BCDIEN_Msk (0x1ul << I2C_BUSCTL_BCDIEN_Pos) /*!< I2C_T::BUSCTL: BCDIEN Mask */ + +#define I2C_BUSCTL_PECDIEN_Pos (13) /*!< I2C_T::BUSCTL: PECDIEN Position */ +#define I2C_BUSCTL_PECDIEN_Msk (0x1ul << I2C_BUSCTL_PECDIEN_Pos) /*!< I2C_T::BUSCTL: PECDIEN Mask */ + +#define I2C_BUSTCTL_BUSTOEN_Pos (0) /*!< I2C_T::BUSTCTL: BUSTOEN Position */ +#define I2C_BUSTCTL_BUSTOEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOEN Mask */ + +#define I2C_BUSTCTL_CLKTOEN_Pos (1) /*!< I2C_T::BUSTCTL: CLKTOEN Position */ +#define I2C_BUSTCTL_CLKTOEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOEN Mask */ + +#define I2C_BUSTCTL_BUSTOIEN_Pos (2) /*!< I2C_T::BUSTCTL: BUSTOIEN Position */ +#define I2C_BUSTCTL_BUSTOIEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOIEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOIEN Mask */ + +#define I2C_BUSTCTL_CLKTOIEN_Pos (3) /*!< I2C_T::BUSTCTL: CLKTOIEN Position */ +#define I2C_BUSTCTL_CLKTOIEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOIEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOIEN Mask */ + +#define I2C_BUSTCTL_TORSTEN_Pos (4) /*!< I2C_T::BUSTCTL: TORSTEN Position */ +#define I2C_BUSTCTL_TORSTEN_Msk (0x1ul << I2C_BUSTCTL_TORSTEN_Pos) /*!< I2C_T::BUSTCTL: TORSTEN Mask */ + +#define I2C_BUSSTS_BUSY_Pos (0) /*!< I2C_T::BUSSTS: BUSY Position */ +#define I2C_BUSSTS_BUSY_Msk (0x1ul << I2C_BUSSTS_BUSY_Pos) /*!< I2C_T::BUSSTS: BUSY Mask */ + +#define I2C_BUSSTS_BCDONE_Pos (1) /*!< I2C_T::BUSSTS: BCDONE Position */ +#define I2C_BUSSTS_BCDONE_Msk (0x1ul << I2C_BUSSTS_BCDONE_Pos) /*!< I2C_T::BUSSTS: BCDONE Mask */ + +#define I2C_BUSSTS_PECERR_Pos (2) /*!< I2C_T::BUSSTS: PECERR Position */ +#define I2C_BUSSTS_PECERR_Msk (0x1ul << I2C_BUSSTS_PECERR_Pos) /*!< I2C_T::BUSSTS: PECERR Mask */ + +#define I2C_BUSSTS_ALERT_Pos (3) /*!< I2C_T::BUSSTS: ALERT Position */ +#define I2C_BUSSTS_ALERT_Msk (0x1ul << I2C_BUSSTS_ALERT_Pos) /*!< I2C_T::BUSSTS: ALERT Mask */ + +#define I2C_BUSSTS_SCTLDIN_Pos (4) /*!< I2C_T::BUSSTS: SCTLDIN Position */ +#define I2C_BUSSTS_SCTLDIN_Msk (0x1ul << I2C_BUSSTS_SCTLDIN_Pos) /*!< I2C_T::BUSSTS: SCTLDIN Mask */ + +#define I2C_BUSSTS_BUSTO_Pos (5) /*!< I2C_T::BUSSTS: BUSTO Position */ +#define I2C_BUSSTS_BUSTO_Msk (0x1ul << I2C_BUSSTS_BUSTO_Pos) /*!< I2C_T::BUSSTS: BUSTO Mask */ + +#define I2C_BUSSTS_CLKTO_Pos (6) /*!< I2C_T::BUSSTS: CLKTO Position */ +#define I2C_BUSSTS_CLKTO_Msk (0x1ul << I2C_BUSSTS_CLKTO_Pos) /*!< I2C_T::BUSSTS: CLKTO Mask */ + +#define I2C_BUSSTS_PECDONE_Pos (7) /*!< I2C_T::BUSSTS: PECDONE Position */ +#define I2C_BUSSTS_PECDONE_Msk (0x1ul << I2C_BUSSTS_PECDONE_Pos) /*!< I2C_T::BUSSTS: PECDONE Mask */ + +#define I2C_PKTSIZE_PLDSIZE_Pos (0) /*!< I2C_T::PKTSIZE: PLDSIZE Position */ +#define I2C_PKTSIZE_PLDSIZE_Msk (0x1fful << I2C_PKTSIZE_PLDSIZE_Pos) /*!< I2C_T::PKTSIZE: PLDSIZE Mask */ + +#define I2C_PKTCRC_PECCRC_Pos (0) /*!< I2C_T::PKTCRC: PECCRC Position */ +#define I2C_PKTCRC_PECCRC_Msk (0xfful << I2C_PKTCRC_PECCRC_Pos) /*!< I2C_T::PKTCRC: PECCRC Mask */ + +#define I2C_BUSTOUT_BUSTO_Pos (0) /*!< I2C_T::BUSTOUT: BUSTO Position */ +#define I2C_BUSTOUT_BUSTO_Msk (0xfful << I2C_BUSTOUT_BUSTO_Pos) /*!< I2C_T::BUSTOUT: BUSTO Mask */ + +#define I2C_CLKTOUT_CLKTO_Pos (0) /*!< I2C_T::CLKTOUT: CLKTO Position */ +#define I2C_CLKTOUT_CLKTO_Msk (0xfful << I2C_CLKTOUT_CLKTO_Pos) /*!< I2C_T::CLKTOUT: CLKTO Mask */ + +/**@}*/ /* I2C_CONST */ +/**@}*/ /* end of I2C register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __I2C_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/i2s_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/i2s_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..ed8e34b6c32e08fc46ae82fcfd64b31fddb77f31 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/i2s_reg.h @@ -0,0 +1,707 @@ +/**************************************************************************//** + * @file i2s_reg.h + * @version V1.00 + * @brief I2S register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __I2S_REG_H__ +#define __I2S_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup I2S I2S Interface Controller(I2S) + Memory Mapped Structure for I2S Controller +@{ */ + +typedef struct +{ + + + /** + * @var I2S_T::CTL0 + * Offset: 0x00 I2S Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |I2SEN |I2S Controller Enable Control + * | | |0 = I2S controller Disabled. + * | | |1 = I2S controller Enabled. + * |[1] |TXEN |Transmit Enable Control + * | | |0 = Data transmission Disabled. + * | | |1 = Data transmission Enabled. + * |[2] |RXEN |Receive Enable Control + * | | |0 = Data receiving Disabled. + * | | |1 = Data receiving Enabled. + * |[3] |MUTE |Transmit Mute Enable Control + * | | |0 = Transmit data is shifted from buffer. + * | | |1 = Send zero on transmit channel. + * |[5:4] |DATWIDTH |Data Width + * | | |This bit field is used to define the bit-width of data word in each audio channel + * | | |00 = The bit-width of data word is 8-bit. + * | | |01 = The bit-width of data word is 16-bit. + * | | |10 = The bit-width of data word is 24-bit. + * | | |11 = The bit-width of data word is 32-bit. + * |[6] |MONO |Monaural Data Control + * | | |0 = Data is stereo format. + * | | |1 = Data is monaural format. + * | | |Note: when chip records data, RXLCH (I2S_CTL0[23]) indicates which channel data will be saved if monaural format is selected. + * |[7] |ORDER |Stereo Data Order in FIFO + * | | |In 8-bit/16-bit data width, this bit is used to select whether the even or odd channel data is stored in higher byte + * | | |In 24-bit data width, this is used to select the left/right alignment method of audio data which is stored in data memory consisted of 32-bit FIFO entries. + * | | |0 = Even channel data at high byte in 8-bit/16-bit data width. + * | | |LSB of 24-bit audio data in each channel is aligned to right side in 32-bit FIFO entries. + * | | |1 = Even channel data at low byte. + * | | | MSB of 24-bit audio data in each channel is aligned to left side in 32-bit FIFO entries. + * |[8] |SLAVE |Slave Mode Enable Control + * | | |0 = Master mode. + * | | |1 = Slave mode. + * | | |Note: I2S can operate as master or slave + * | | |For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send out bit clock to Audio CODEC chip + * | | |In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip. + * |[15] |MCLKEN |Master Clock Enable Control + * | | |If MCLKEN is set to 1, I2S controller will generate master clock on I2S_MCLK pin for external audio devices. + * | | |0 = Master clock Disabled. + * | | |1 = Master clock Enabled. + * |[18] |TXFBCLR |Transmit FIFO Buffer Clear + * | | |0 = No Effect. + * | | |1 = Clear TX FIFO. + * | | |Note1: Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXCNT (I2S_STATUS1[12:8]) returns 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed. + * | | |Note2: This bit is clear by hardware automatically, read it return zero. + * |[19] |RXFBCLR |Receive FIFO Buffer Clear + * | | |0 = No Effect. + * | | |1 = Clear RX FIFO. + * | | |Note1: Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXCNT (I2S_STATUS1[20:16]) returns 0 and receive FIFO becomes empty. + * | | |Note2: This bit is cleared by hardware automatically, read it return zero. + * |[20] |TXPDMAEN |Transmit PDMA Enable Control + * | | |0 = Transmit PDMA function Disabled. + * | | |1 = Transmit PDMA function Enabled. + * |[21] |RXPDMAEN |Receive PDMA Enable Control + * | | |0 = Receiver PDMA function Disabled. + * | | |1 = Receiver PDMA function Enabled. + * |[23] |RXLCH |Receive Left Channel Enable Control + * | | |When monaural format is selected (MONO = 1), I2S will receive channel1 data if RXLCH is set to 0, and receive channel0 data if RXLCH is set to 1. + * | | |0 = Receives channel1 data in MONO mode. + * | | |1 = Receives channel0 data in MONO mode. + * |[26:24] |FORMAT |Data Format Selection + * | | |000 = I2S standard data format. + * | | |001 = I2S with MSB justified. + * | | |010 = I2S with LSB justified. + * | | |011 = Reserved. + * | | |100 = PCM standard data format. + * | | |101 = PCM with MSB justified. + * | | |110 = PCM with LSB justified. + * | | |111 = Reserved. + * |[27] |PCMSYNC |PCM Synchronization Pulse Length Selection + * | | |This bit field is used to select the high pulse length of frame synchronization signal in PCM protocol + * | | |0 = One BCLK period. + * | | |1 = One channel period. + * | | |Note: This bit is only available in master mode + * |[29:28] |CHWIDTH |Channel Width + * | | |This bit fields are used to define the length of audio channel + * | | |If CHWIDTH < DATWIDTH, the hardware will set the real channel length as the bit-width of audio data which is defined by DATWIDTH. + * | | |00 = The bit-width of each audio channel is 8-bit. + * | | |01 = The bit-width of each audio channel is 16-bit. + * | | |10 = The bit-width of each audio channel is 24-bit. + * | | |11 = The bit-width of each audio channel is 32-bit. + * |[31:30] |TDMCHNUM |TDM Channel Number + * | | |This bit fields are used to define the TDM channel number in one audio frame while PCM mode (FORMAT[2] = 1). + * | | |00 = 2 channels in audio frame. + * | | |01 = 4 channels in audio frame. + * | | |10 = 6 channels in audio frame. + * | | |11 = 8 channels in audio frame. + * @var I2S_T::CLKDIV + * Offset: 0x04 I2S Clock Divider Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |MCLKDIV |Master Clock Divider + * | | |If chip external crystal frequency is (2xMCLKDIV)*256fs then software can program these bits to generate 256fs clock frequency to audio codec chip + * | | |If MCLKDIV is set to 0, MCLK is the same as external clock input. + * | | |For example, sampling rate is 24 kHz and chip external crystal clock is 12.288 MHz, set MCLKDIV = 1. + * | | |F_MCLK = F_I2SCLK/(2x(MCLKDIV)) (When MCLKDIV is >= 1 ). + * | | |F_MCLK = F_I2SCLK (When MCLKDIV is set to 0 ). + * | | |Note: F_MCLK is the frequency of MCLK, and F_I2SCLK is the frequency of the I2S_CLK + * |[16:8] |BCLKDIV |Bit Clock Divider + * | | |The I2S controller will generate bit clock in Master mode + * | | |Software can program these bit fields to generate sampling rate clock frequency. + * | | |F_BCLK= F_I2SCLK / (2*(BCLKDIV + 1)). + * | | |Note: F_BCLK is the frequency of BCLK and F_I2SCLK is the frequency of I2S_CLK + * @var I2S_T::IEN + * Offset: 0x08 I2S Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXUDFIEN |Receive FIFO Underflow Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: If software reads receive FIFO when it is empty then RXUDIF (I2S_STATUS0[8]) flag is set to 1. + * |[1] |RXOVFIEN |Receive FIFO Overflow Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Interrupt occurs if this bit is set to 1 and RXOVIF (I2S_STATUS0[9]) flag is set to 1 + * |[2] |RXTHIEN |Receive FIFO Threshold Level Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: When data word in receive FIFO is equal or higher than RXTH (I2S_CTL1[19:16]) and the RXTHIF (I2S_STATUS0[10]) bit is set to 1 + * | | |If RXTHIEN bit is enabled, interrupt occur. + * |[8] |TXUDFIEN |Transmit FIFO Underflow Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Interrupt occur if this bit is set to 1 and TXUDIF (I2S_STATUS0[16]) flag is set to 1. + * |[9] |TXOVFIEN |Transmit FIFO Overflow Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Interrupt occurs if this bit is set to 1 and TXOVIF (I2S_STATUS0[17]) flag is set to 1 + * |[10] |TXTHIEN |Transmit FIFO Threshold Level Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH (I2S_CTL1[11:8]). + * |[16] |CH0ZCIEN |Channel0 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note1: Interrupt occurs if this bit is set to 1 and channel0 zero-cross + * | | |Note2: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * |[17] |CH1ZCIEN |Channel1 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note1: Interrupt occurs if this bit is set to 1 and channel1 zero-cross + * | | |Note2: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * |[18] |CH2ZCIEN |Channel2 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note1: Interrupt occurs if this bit is set to 1 and channel2 zero-cross + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[19] |CH3ZCIEN |Channel3 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note1: Interrupt occurs if this bit is set to 1 and channel3 zero-cross + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[20] |CH4ZCIEN |Channel4 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note1: Interrupt occurs if this bit is set to 1 and channel4 zero-cross + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[21] |CH5ZCIEN |Channel5 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note1: Interrupt occurs if this bit is set to 1 and channel5 zero-cross + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[22] |CH6ZCIEN |Channel6 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note1: Interrupt occurs if this bit is set to 1 and channel6 zero-cross + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[23] |CH7ZCIEN |Channel7 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note1: Interrupt occurs if this bit is set to 1 and channel7 zero-cross + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * @var I2S_T::STATUS0 + * Offset: 0x0C I2S Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |I2SINT |I2S Interrupt Flag (Read Only) + * | | |0 = No I2S interrupt. + * | | |1 = I2S interrupt. + * | | |Note: It is wire-OR of I2STXINT and I2SRXINT bits. + * |[1] |I2SRXINT |I2S Receive Interrupt (Read Only) + * | | |0 = No receive interrupt. + * | | |1 = Receive interrupt. + * |[2] |I2STXINT |I2S Transmit Interrupt (Read Only) + * | | |0 = No transmit interrupt. + * | | |1 = Transmit interrupt. + * |[5:3] |DATACH |Transmission Data Channel (Read Only) + * | | |This bit fields are used to indicate which audio channel is current transmit data belong. + * | | |000 = channel0 (means left channel while 2-channel I2S/PCM mode). + * | | |001 = channel1 (means right channel while 2-channel I2S/PCM mode). + * | | |010 = channel2 (available while 4-channel TDM PCM mode). + * | | |011 = channel3 (available while 4-channel TDM PCM mode). + * | | |100 = channel4 (available while 6-channel TDM PCM mode). + * | | |101 = channel5 (available while 6-channel TDM PCM mode). + * | | |110 = channel6 (available while 8-channel TDM PCM mode). + * | | |111 = channel7 (available while 8-channel TDM PCM mode). + * |[8] |RXUDIF |Receive FIFO Underflow Interrupt Flag + * | | |0 = No underflow occur. + * | | |1 = Underflow occur. + * | | |Note1: When receive FIFO is empty, and software reads the receive FIFO again + * | | |This bit will be set to 1, and it indicates underflow situation occurs. + * | | |Note2: Write 1 to clear this bit to zero + * |[9] |RXOVIF |Receive FIFO Overflow Interrupt Flag + * | | |0 = No overflow occur. + * | | |1 = Overflow occur. + * | | |Note1: When receive FIFO is full and receive hardware attempt to write data into receive FIFO then this bit is set to 1, data in 1st buffer is overwrote. + * | | |Note2: Write 1 to clear this bit to 0. + * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = Data word(s) in FIFO is not higher than threshold level. + * | | |1 = Data word(s) in FIFO is higher than threshold level. + * | | |Note: When data word(s) in receive FIFO is higher than threshold value set in RXTH (I2S_CTL1[19:16]) the RXTHIF bit becomes to 1 + * | | |It keeps at 1 till RXCNT (I2S_STATUS1[20:16]) is not higher than RXTH (I2S_CTL1[19:16]) after software read RXFIFO register. + * |[11] |RXFULL |Receive FIFO Full (Read Only) + * | | |0 = Not full. + * | | |1 = Full. + * | | |Note: This bit reflects data words number in receive FIFO is 16. + * |[12] |RXEMPTY |Receive FIFO Empty (Read Only) + * | | |0 = Not empty. + * | | |1 = Empty. + * | | |Note: This bit reflects data words number in receive FIFO is zero + * |[16] |TXUDIF |Transmit FIFO Underflow Interrupt Flag + * | | |0 = No underflow. + * | | |1 = Underflow. + * | | |Note1: This bit will be set to 1 when shift logic hardware read data from transmitting FIFO and the filling data level in transmitting FIFO is not enough for one audio frame. + * | | |Note2: Write 1 to clear this bit to 0. + * |[17] |TXOVIF |Transmit FIFO Overflow Interrupt Flag + * | | |0 = No overflow. + * | | |1 = Overflow. + * | | |Note1: Write data to transmit FIFO when it is full and this bit set to 1 + * | | |Note2: Write 1 to clear this bit to 0. + * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = Data word(s) in FIFO is higher than threshold level. + * | | |1 = Data word(s) in FIFO is equal or lower than threshold level. + * | | |Note: When data word(s) in transmit FIFO is equal or lower than threshold value set in TXTH (I2S_CTL1[11:8]) the TXTHIF bit becomes to 1 + * | | |It keeps at 1 till TXCNT (I2S_STATUS1[12:8]) is higher than TXTH (I2S_CTL1[11:8]) after software write TXFIFO register. + * |[19] |TXFULL |Transmit FIFO Full (Read Only) + * | | |This bit reflect data word number in transmit FIFO is 16 + * | | |0 = Not full. + * | | |1 = Full. + * |[20] |TXEMPTY |Transmit FIFO Empty (Read Only) + * | | |This bit reflect data word number in transmit FIFO is zero + * | | |0 = Not empty. + * | | |1 = Empty. + * |[21] |TXBUSY |Transmit Busy (Read Only) + * | | |0 = Transmit shift buffer is empty. + * | | |1 = Transmit shift buffer is busy. + * | | |Note: This bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out + * | | |And set to 1 when 1st data is load to shift buffer + * @var I2S_T::TXFIFO + * Offset: 0x10 I2S Transmit FIFO Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TXFIFO |Transmit FIFO Bits + * | | |I2S contains 16 words (16x32 bit) data buffer for data transmit + * | | |Write data to this register to prepare data for transmit + * | | |The remaining word number is indicated by TXCNT (I2S_STATUS1[12:8]). + * @var I2S_T::RXFIFO + * Offset: 0x14 I2S Receive FIFO Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RXFIFO |Receive FIFO Bits + * | | |I2S contains 16 words (16x32 bit) data buffer for data receive + * | | |Read this register to get data in FIFO + * | | |The remaining data word number is indicated by RXCNT (I2S_STATUS1[20:16]). + * @var I2S_T::CTL1 + * Offset: 0x20 I2S Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CH0ZCEN |Channel0 Zero-cross Detection Enable Control + * | | |0 = channel0 zero-cross detect Disabled. + * | | |1 = channel0 zero-cross detect Enabled. + * | | |Note1: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * | | |Note2: If this bit is set to 1, when channel0 data sign bit change or next shift data bits are all zero then CH0ZCIF(I2S_STATUS1[0]) flag is set to 1. + * | | |Note3: If CH0ZCIF Flag is set to 1, the channel0 will be mute. + * |[1] |CH1ZCEN |Channel1 Zero-cross Detect Enable Control + * | | |0 = channel1 zero-cross detect Disabled. + * | | |1 = channel1 zero-cross detect Enabled. + * | | |Note1: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * | | |Note2: If this bit is set to 1, when channel1 data sign bit change or next shift data bits are all zero then CH1ZCIF(I2S_STATUS1[1]) flag is set to 1. + * | | |Note3: If CH1ZCIF Flag is set to 1, the channel1 will be mute. + * |[2] |CH2ZCEN |Channel2 Zero-cross Detect Enable Control + * | | |0 = channel2 zero-cross detect Disabled. + * | | |1 = channel2 zero-cross detect Enabled. + * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * | | |Note2: If this bit is set to 1, when channel2 data sign bit change or next shift data bits are all zero then CH2ZCIF(I2S_STATUS1[2]) flag is set to 1. + * | | |Note3: If CH2ZCIF Flag is set to 1, the channel2 will be mute. + * |[3] |CH3ZCEN |Channel3 Zero-cross Detect Enable Control + * | | |0 = channel3 zero-cross detect Disabled. + * | | |1 = channel3 zero-cross detect Enabled. + * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * | | |Note2: If this bit is set to 1, when channel3 data sign bit change or next shift data bits are all zero then CH3ZCIF(I2S_STATUS1[3]) flag is set to 1. + * | | |Note3: If CH3ZCIF Flag is set to 1, the channel3 will be mute. + * |[4] |CH4ZCEN |Channel4 Zero-cross Detect Enable Control + * | | |0 = channel4 zero-cross detect Disabled. + * | | |1 = channel4 zero-cross detect Enabled. + * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * | | |Note2: If this bit is set to 1, when channel4 data sign bit change or next shift data bits are all zero then CH4ZCIF(I2S_STATUS1[4]) flag is set to 1. + * | | |Note3: If CH4ZCIF Flag is set to 1, the channel4 will be mute. + * |[5] |CH5ZCEN |Channel5 Zero-cross Detect Enable Control + * | | |0 = channel5 zero-cross detect Disabled. + * | | |1 = channel5 zero-cross detect Enabled. + * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * | | |Note2: If this bit is set to 1, when channel5 data sign bit change or next shift data bits are all zero then CH5ZCIF(I2S_STATUS1[5]) flag is set to 1. + * | | |Note3: If CH5ZCIF Flag is set to 1, the channel5 will be mute. + * |[6] |CH6ZCEN |Channel6 Zero-cross Detect Enable Control + * | | |0 = channel6 zero-cross detect Disabled. + * | | |1 = channel6 zero-cross detect Enabled. + * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * | | |Note2: If this bit is set to 1, when channel6 data sign bit change or next shift data bits are all zero then CH6ZCIF(I2S_STATUS1[6]) flag is set to 1. + * | | |Note3: If CH6ZCIF Flag is set to 1, the channel6 will be mute. + * |[7] |CH7ZCEN |Channel7 Zero-cross Detect Enable Control + * | | |0 = channel7 zero-cross detect Disabled. + * | | |1 = channel7 zero-cross detect Enabled. + * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * | | |Note2: If this bit is set to 1, when channel7 data sign bit change or next shift data bits are all zero then CH7ZCIF (I2S_STATUS1[7]) flag is set to 1. + * | | |Note3: If CH7ZCIF Flag is set to 1, the channel7 will be mute. + * |[11:8] |TXTH |Transmit FIFO Threshold Level + * | | |0000 = 0 data word in transmit FIFO. + * | | |0001 = 1 data word in transmit FIFO. + * | | |0010 = 2 data words in transmit FIFO. + * | | |... + * | | |1110 = 14 data words in transmit FIFO. + * | | |1111 = 15 data words in transmit FIFO. + * | | |Note: If remain data word number in transmit FIFO is the same or less than threshold level then TXTHIF (I2S_STATUS0[18]) flag is set. + * |[19:16] |RXTH |Receive FIFO Threshold Level + * | | |0000 = 1 data word in receive FIFO. + * | | |0001 = 2 data words in receive FIFO. + * | | |0010 = 3 data words in receive FIFO. + * | | |... + * | | |1110 = 15 data words in receive FIFO. + * | | |1111 = 16 data words in receive FIFO. + * | | |Note: When received data word number in receive buffer is greater than threshold level then RXTHIF (I2S_STATUS0[10]) flag is set. + * |[24] |PBWIDTH |Peripheral Bus Data Width Selection + * | | |This bit is used to choice the available data width of APB bus + * | | |It must be set to 1 while PDMA function is enable and it is set to 16-bit transmission mode + * | | |0 = 32 bits data width. + * | | |1 = 16 bits data width. + * | | |Note1: If PBWIDTH=1, the low 16 bits of 32-bit data bus are available. + * | | |Note2: If PBWIDTH=1, the transmitting FIFO level will be increased after two FIFO write operations. + * | | |Note3: If PBWIDTH=1, the receiving FIFO level will be decreased after two FIFO read operations. + * |[25] |PB16ORD |FIFO Read/Write Order in 16-bit Width of Peripheral Bus + * | | |When PBWIDTH = 1, the data FIFO will be increased or decreased by two peripheral bus access + * | | |This bit is used to select the order of FIFO access operations to meet the 32-bit transmitting/receiving FIFO entries. + * | | |0 = Low 16-bit read/write access first. + * | | |1 = High 16-bit read/write access first. + * | | |Note: This bit is available while PBWIDTH = 1. + * @var I2S_T::STATUS1 + * Offset: 0x24 I2S Status Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CH0ZCIF |Channel0 Zero-cross Interrupt Flag + * | | |It indicates channel0 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel0. + * | | |1 = Channel0 zero-cross is detected. + * | | |Note1: Write 1 to clear this bit to 0. + * | | |Note2: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * |[1] |CH1ZCIF |Channel1 Zero-cross Interrupt Flag + * | | |It indicates channel1 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel1. + * | | |1 = Channel1 zero-cross is detected. + * | | |Note1: Write 1 to clear this bit to 0. + * | | |Note2: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * |[2] |CH2ZCIF |Channel2 Zero-cross Interrupt Flag + * | | |It indicates channel2 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel2. + * | | |1 = Channel2 zero-cross is detected. + * | | |Note1: Write 1 to clear this bit to 0. + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[3] |CH3ZCIF |Channel3 Zero-cross Interrupt Flag + * | | |It indicates channel3 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel3. + * | | |1 = Channel3 zero-cross is detected. + * | | |Note1: Write 1 to clear this bit to 0. + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[4] |CH4ZCIF |Channel4 Zero-cross Interrupt Flag + * | | |It indicates channel4 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel4. + * | | |1 = Channel4 zero-cross is detected. + * | | |Note1: Write 1 to clear this bit to 0. + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[5] |CH5ZCIF |Channel5 Zero-cross Interrupt Flag + * | | |It indicates channel5 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel5. + * | | |1 = Channel5 zero-cross is detected. + * | | |Note1: Write 1 to clear this bit to 0. + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[6] |CH6ZCIF |Channel6 Zero-cross Interrupt Flag + * | | |It indicates channel6 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel6. + * | | |1 = Channel6 zero-cross is detected. + * | | |Note1: Write 1 to clear this bit to 0. + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[7] |CH7ZCIF |Channel7 Zero-cross Interrupt Flag + * | | |It indicates channel7 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel7. + * | | |1 = Channel7 zero-cross is detected. + * | | |Note1: Write 1 to clear this bit to 0. + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[12:8] |TXCNT |Transmit FIFO Level (Read Only) + * | | |These bits indicate the number of available entries in transmit FIFO + * | | |00000 = No data. + * | | |00001 = 1 word in transmit FIFO. + * | | |00010 = 2 words in transmit FIFO. + * | | |... + * | | |01110 = 14 words in transmit FIFO. + * | | |01111 = 15 words in transmit FIFO. + * | | |10000 = 16 words in transmit FIFO. + * | | |Others are reserved. + * |[20:16] |RXCNT |Receive FIFO Level (Read Only) + * | | |These bits indicate the number of available entries in receive FIFO + * | | |00000 = No data. + * | | |00001 = 1 word in receive FIFO. + * | | |00010 = 2 words in receive FIFO. + * | | |... + * | | |01110 = 14 words in receive FIFO. + * | | |01111 = 15 words in receive FIFO. + * | | |10000 = 16 words in receive FIFO. + * | | |Others are reserved. + */ + __IO uint32_t CTL0; /*!< [0x0000] I2S Control Register 0 */ + __IO uint32_t CLKDIV; /*!< [0x0004] I2S Clock Divider Register */ + __IO uint32_t IEN; /*!< [0x0008] I2S Interrupt Enable Register */ + __IO uint32_t STATUS0; /*!< [0x000c] I2S Status Register 0 */ + __O uint32_t TXFIFO; /*!< [0x0010] I2S Transmit FIFO Register */ + __I uint32_t RXFIFO; /*!< [0x0014] I2S Receive FIFO Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CTL1; /*!< [0x0020] I2S Control Register 1 */ + __IO uint32_t STATUS1; /*!< [0x0024] I2S Status Register 1 */ + +} I2S_T; + +/** + @addtogroup I2S_CONST I2S Bit Field Definition + Constant Definitions for I2S Controller +@{ */ + +#define I2S_CTL0_I2SEN_Pos (0) /*!< I2S_T::CTL0: I2SEN Position */ +#define I2S_CTL0_I2SEN_Msk (0x1ul << I2S_CTL0_I2SEN_Pos) /*!< I2S_T::CTL0: I2SEN Mask */ + +#define I2S_CTL0_TXEN_Pos (1) /*!< I2S_T::CTL0: TXEN Position */ +#define I2S_CTL0_TXEN_Msk (0x1ul << I2S_CTL0_TXEN_Pos) /*!< I2S_T::CTL0: TXEN Mask */ + +#define I2S_CTL0_RXEN_Pos (2) /*!< I2S_T::CTL0: RXEN Position */ +#define I2S_CTL0_RXEN_Msk (0x1ul << I2S_CTL0_RXEN_Pos) /*!< I2S_T::CTL0: RXEN Mask */ + +#define I2S_CTL0_MUTE_Pos (3) /*!< I2S_T::CTL0: MUTE Position */ +#define I2S_CTL0_MUTE_Msk (0x1ul << I2S_CTL0_MUTE_Pos) /*!< I2S_T::CTL0: MUTE Mask */ + +#define I2S_CTL0_DATWIDTH_Pos (4) /*!< I2S_T::CTL0: DATWIDTH Position */ +#define I2S_CTL0_DATWIDTH_Msk (0x3ul << I2S_CTL0_DATWIDTH_Pos) /*!< I2S_T::CTL0: DATWIDTH Mask */ + +#define I2S_CTL0_MONO_Pos (6) /*!< I2S_T::CTL0: MONO Position */ +#define I2S_CTL0_MONO_Msk (0x1ul << I2S_CTL0_MONO_Pos) /*!< I2S_T::CTL0: MONO Mask */ + +#define I2S_CTL0_ORDER_Pos (7) /*!< I2S_T::CTL0: ORDER Position */ +#define I2S_CTL0_ORDER_Msk (0x1ul << I2S_CTL0_ORDER_Pos) /*!< I2S_T::CTL0: ORDER Mask */ + +#define I2S_CTL0_SLAVE_Pos (8) /*!< I2S_T::CTL0: SLAVE Position */ +#define I2S_CTL0_SLAVE_Msk (0x1ul << I2S_CTL0_SLAVE_Pos) /*!< I2S_T::CTL0: SLAVE Mask */ + +#define I2S_CTL0_MCLKEN_Pos (15) /*!< I2S_T::CTL0: MCLKEN Position */ +#define I2S_CTL0_MCLKEN_Msk (0x1ul << I2S_CTL0_MCLKEN_Pos) /*!< I2S_T::CTL0: MCLKEN Mask */ + +#define I2S_CTL0_TXFBCLR_Pos (18) /*!< I2S_T::CTL0: TXFBCLR Position */ +#define I2S_CTL0_TXFBCLR_Msk (0x1ul << I2S_CTL0_TXFBCLR_Pos) /*!< I2S_T::CTL0: TXFBCLR Mask */ + +#define I2S_CTL0_RXFBCLR_Pos (19) /*!< I2S_T::CTL0: RXFBCLR Position */ +#define I2S_CTL0_RXFBCLR_Msk (0x1ul << I2S_CTL0_RXFBCLR_Pos) /*!< I2S_T::CTL0: RXFBCLR Mask */ + +#define I2S_CTL0_TXPDMAEN_Pos (20) /*!< I2S_T::CTL0: TXPDMAEN Position */ +#define I2S_CTL0_TXPDMAEN_Msk (0x1ul << I2S_CTL0_TXPDMAEN_Pos) /*!< I2S_T::CTL0: TXPDMAEN Mask */ + +#define I2S_CTL0_RXPDMAEN_Pos (21) /*!< I2S_T::CTL0: RXPDMAEN Position */ +#define I2S_CTL0_RXPDMAEN_Msk (0x1ul << I2S_CTL0_RXPDMAEN_Pos) /*!< I2S_T::CTL0: RXPDMAEN Mask */ + +#define I2S_CTL0_RXLCH_Pos (23) /*!< I2S_T::CTL0: RXLCH Position */ +#define I2S_CTL0_RXLCH_Msk (0x1ul << I2S_CTL0_RXLCH_Pos) /*!< I2S_T::CTL0: RXLCH Mask */ + +#define I2S_CTL0_FORMAT_Pos (24) /*!< I2S_T::CTL0: FORMAT Position */ +#define I2S_CTL0_FORMAT_Msk (0x7ul << I2S_CTL0_FORMAT_Pos) /*!< I2S_T::CTL0: FORMAT Mask */ + +#define I2S_CTL0_PCMSYNC_Pos (27) /*!< I2S_T::CTL0: PCMSYNC Position */ +#define I2S_CTL0_PCMSYNC_Msk (0x1ul << I2S_CTL0_PCMSYNC_Pos) /*!< I2S_T::CTL0: PCMSYNC Mask */ + +#define I2S_CTL0_CHWIDTH_Pos (28) /*!< I2S_T::CTL0: CHWIDTH Position */ +#define I2S_CTL0_CHWIDTH_Msk (0x3ul << I2S_CTL0_CHWIDTH_Pos) /*!< I2S_T::CTL0: CHWIDTH Mask */ + +#define I2S_CTL0_TDMCHNUM_Pos (30) /*!< I2S_T::CTL0: TDMCHNUM Position */ +#define I2S_CTL0_TDMCHNUM_Msk (0x3ul << I2S_CTL0_TDMCHNUM_Pos) /*!< I2S_T::CTL0: TDMCHNUM Mask */ + +#define I2S_CLKDIV_MCLKDIV_Pos (0) /*!< I2S_T::CLKDIV: MCLKDIV Position */ +#define I2S_CLKDIV_MCLKDIV_Msk (0x3ful << I2S_CLKDIV_MCLKDIV_Pos) /*!< I2S_T::CLKDIV: MCLKDIV Mask */ + +#define I2S_CLKDIV_BCLKDIV_Pos (8) /*!< I2S_T::CLKDIV: BCLKDIV Position */ +#define I2S_CLKDIV_BCLKDIV_Msk (0x1fful << I2S_CLKDIV_BCLKDIV_Pos) /*!< I2S_T::CLKDIV: BCLKDIV Mask */ + +#define I2S_IEN_RXUDFIEN_Pos (0) /*!< I2S_T::IEN: RXUDFIEN Position */ +#define I2S_IEN_RXUDFIEN_Msk (0x1ul << I2S_IEN_RXUDFIEN_Pos) /*!< I2S_T::IEN: RXUDFIEN Mask */ + +#define I2S_IEN_RXOVFIEN_Pos (1) /*!< I2S_T::IEN: RXOVFIEN Position */ +#define I2S_IEN_RXOVFIEN_Msk (0x1ul << I2S_IEN_RXOVFIEN_Pos) /*!< I2S_T::IEN: RXOVFIEN Mask */ + +#define I2S_IEN_RXTHIEN_Pos (2) /*!< I2S_T::IEN: RXTHIEN Position */ +#define I2S_IEN_RXTHIEN_Msk (0x1ul << I2S_IEN_RXTHIEN_Pos) /*!< I2S_T::IEN: RXTHIEN Mask */ + +#define I2S_IEN_TXUDFIEN_Pos (8) /*!< I2S_T::IEN: TXUDFIEN Position */ +#define I2S_IEN_TXUDFIEN_Msk (0x1ul << I2S_IEN_TXUDFIEN_Pos) /*!< I2S_T::IEN: TXUDFIEN Mask */ + +#define I2S_IEN_TXOVFIEN_Pos (9) /*!< I2S_T::IEN: TXOVFIEN Position */ +#define I2S_IEN_TXOVFIEN_Msk (0x1ul << I2S_IEN_TXOVFIEN_Pos) /*!< I2S_T::IEN: TXOVFIEN Mask */ + +#define I2S_IEN_TXTHIEN_Pos (10) /*!< I2S_T::IEN: TXTHIEN Position */ +#define I2S_IEN_TXTHIEN_Msk (0x1ul << I2S_IEN_TXTHIEN_Pos) /*!< I2S_T::IEN: TXTHIEN Mask */ + +#define I2S_IEN_CH0ZCIEN_Pos (16) /*!< I2S_T::IEN: CH0ZCIEN Position */ +#define I2S_IEN_CH0ZCIEN_Msk (0x1ul << I2S_IEN_CH0ZCIEN_Pos) /*!< I2S_T::IEN: CH0ZCIEN Mask */ + +#define I2S_IEN_CH1ZCIEN_Pos (17) /*!< I2S_T::IEN: CH1ZCIEN Position */ +#define I2S_IEN_CH1ZCIEN_Msk (0x1ul << I2S_IEN_CH1ZCIEN_Pos) /*!< I2S_T::IEN: CH1ZCIEN Mask */ + +#define I2S_IEN_CH2ZCIEN_Pos (18) /*!< I2S_T::IEN: CH2ZCIEN Position */ +#define I2S_IEN_CH2ZCIEN_Msk (0x1ul << I2S_IEN_CH2ZCIEN_Pos) /*!< I2S_T::IEN: CH2ZCIEN Mask */ + +#define I2S_IEN_CH3ZCIEN_Pos (19) /*!< I2S_T::IEN: CH3ZCIEN Position */ +#define I2S_IEN_CH3ZCIEN_Msk (0x1ul << I2S_IEN_CH3ZCIEN_Pos) /*!< I2S_T::IEN: CH3ZCIEN Mask */ + +#define I2S_IEN_CH4ZCIEN_Pos (20) /*!< I2S_T::IEN: CH4ZCIEN Position */ +#define I2S_IEN_CH4ZCIEN_Msk (0x1ul << I2S_IEN_CH4ZCIEN_Pos) /*!< I2S_T::IEN: CH4ZCIEN Mask */ + +#define I2S_IEN_CH5ZCIEN_Pos (21) /*!< I2S_T::IEN: CH5ZCIEN Position */ +#define I2S_IEN_CH5ZCIEN_Msk (0x1ul << I2S_IEN_CH5ZCIEN_Pos) /*!< I2S_T::IEN: CH5ZCIEN Mask */ + +#define I2S_IEN_CH6ZCIEN_Pos (22) /*!< I2S_T::IEN: CH6ZCIEN Position */ +#define I2S_IEN_CH6ZCIEN_Msk (0x1ul << I2S_IEN_CH6ZCIEN_Pos) /*!< I2S_T::IEN: CH6ZCIEN Mask */ + +#define I2S_IEN_CH7ZCIEN_Pos (23) /*!< I2S_T::IEN: CH7ZCIEN Position */ +#define I2S_IEN_CH7ZCIEN_Msk (0x1ul << I2S_IEN_CH7ZCIEN_Pos) /*!< I2S_T::IEN: CH7ZCIEN Mask */ + +#define I2S_STATUS0_I2SINT_Pos (0) /*!< I2S_T::STATUS0: I2SINT Position */ +#define I2S_STATUS0_I2SINT_Msk (0x1ul << I2S_STATUS0_I2SINT_Pos) /*!< I2S_T::STATUS0: I2SINT Mask */ + +#define I2S_STATUS0_I2SRXINT_Pos (1) /*!< I2S_T::STATUS0: I2SRXINT Position */ +#define I2S_STATUS0_I2SRXINT_Msk (0x1ul << I2S_STATUS0_I2SRXINT_Pos) /*!< I2S_T::STATUS0: I2SRXINT Mask */ + +#define I2S_STATUS0_I2STXINT_Pos (2) /*!< I2S_T::STATUS0: I2STXINT Position */ +#define I2S_STATUS0_I2STXINT_Msk (0x1ul << I2S_STATUS0_I2STXINT_Pos) /*!< I2S_T::STATUS0: I2STXINT Mask */ + +#define I2S_STATUS0_DATACH_Pos (3) /*!< I2S_T::STATUS0: DATACH Position */ +#define I2S_STATUS0_DATACH_Msk (0x7ul << I2S_STATUS0_DATACH_Pos) /*!< I2S_T::STATUS0: DATACH Mask */ + +#define I2S_STATUS0_RXUDIF_Pos (8) /*!< I2S_T::STATUS0: RXUDIF Position */ +#define I2S_STATUS0_RXUDIF_Msk (0x1ul << I2S_STATUS0_RXUDIF_Pos) /*!< I2S_T::STATUS0: RXUDIF Mask */ + +#define I2S_STATUS0_RXOVIF_Pos (9) /*!< I2S_T::STATUS0: RXOVIF Position */ +#define I2S_STATUS0_RXOVIF_Msk (0x1ul << I2S_STATUS0_RXOVIF_Pos) /*!< I2S_T::STATUS0: RXOVIF Mask */ + +#define I2S_STATUS0_RXTHIF_Pos (10) /*!< I2S_T::STATUS0: RXTHIF Position */ +#define I2S_STATUS0_RXTHIF_Msk (0x1ul << I2S_STATUS0_RXTHIF_Pos) /*!< I2S_T::STATUS0: RXTHIF Mask */ + +#define I2S_STATUS0_RXFULL_Pos (11) /*!< I2S_T::STATUS0: RXFULL Position */ +#define I2S_STATUS0_RXFULL_Msk (0x1ul << I2S_STATUS0_RXFULL_Pos) /*!< I2S_T::STATUS0: RXFULL Mask */ + +#define I2S_STATUS0_RXEMPTY_Pos (12) /*!< I2S_T::STATUS0: RXEMPTY Position */ +#define I2S_STATUS0_RXEMPTY_Msk (0x1ul << I2S_STATUS0_RXEMPTY_Pos) /*!< I2S_T::STATUS0: RXEMPTY Mask */ + +#define I2S_STATUS0_TXUDIF_Pos (16) /*!< I2S_T::STATUS0: TXUDIF Position */ +#define I2S_STATUS0_TXUDIF_Msk (0x1ul << I2S_STATUS0_TXUDIF_Pos) /*!< I2S_T::STATUS0: TXUDIF Mask */ + +#define I2S_STATUS0_TXOVIF_Pos (17) /*!< I2S_T::STATUS0: TXOVIF Position */ +#define I2S_STATUS0_TXOVIF_Msk (0x1ul << I2S_STATUS0_TXOVIF_Pos) /*!< I2S_T::STATUS0: TXOVIF Mask */ + +#define I2S_STATUS0_TXTHIF_Pos (18) /*!< I2S_T::STATUS0: TXTHIF Position */ +#define I2S_STATUS0_TXTHIF_Msk (0x1ul << I2S_STATUS0_TXTHIF_Pos) /*!< I2S_T::STATUS0: TXTHIF Mask */ + +#define I2S_STATUS0_TXFULL_Pos (19) /*!< I2S_T::STATUS0: TXFULL Position */ +#define I2S_STATUS0_TXFULL_Msk (0x1ul << I2S_STATUS0_TXFULL_Pos) /*!< I2S_T::STATUS0: TXFULL Mask */ + +#define I2S_STATUS0_TXEMPTY_Pos (20) /*!< I2S_T::STATUS0: TXEMPTY Position */ +#define I2S_STATUS0_TXEMPTY_Msk (0x1ul << I2S_STATUS0_TXEMPTY_Pos) /*!< I2S_T::STATUS0: TXEMPTY Mask */ + +#define I2S_STATUS0_TXBUSY_Pos (21) /*!< I2S_T::STATUS0: TXBUSY Position */ +#define I2S_STATUS0_TXBUSY_Msk (0x1ul << I2S_STATUS0_TXBUSY_Pos) /*!< I2S_T::STATUS0: TXBUSY Mask */ + +#define I2S_TXFIFO_TXFIFO_Pos (0) /*!< I2S_T::TXFIFO: TXFIFO Position */ +#define I2S_TXFIFO_TXFIFO_Msk (0xfffffffful << I2S_TXFIFO_TXFIFO_Pos) /*!< I2S_T::TXFIFO: TXFIFO Mask */ + +#define I2S_RXFIFO_RXFIFO_Pos (0) /*!< I2S_T::RXFIFO: RXFIFO Position */ +#define I2S_RXFIFO_RXFIFO_Msk (0xfffffffful << I2S_RXFIFO_RXFIFO_Pos) /*!< I2S_T::RXFIFO: RXFIFO Mask */ + +#define I2S_CTL1_CH0ZCEN_Pos (0) /*!< I2S_T::CTL1: CH0ZCEN Position */ +#define I2S_CTL1_CH0ZCEN_Msk (0x1ul << I2S_CTL1_CH0ZCEN_Pos) /*!< I2S_T::CTL1: CH0ZCEN Mask */ + +#define I2S_CTL1_CH1ZCEN_Pos (1) /*!< I2S_T::CTL1: CH1ZCEN Position */ +#define I2S_CTL1_CH1ZCEN_Msk (0x1ul << I2S_CTL1_CH1ZCEN_Pos) /*!< I2S_T::CTL1: CH1ZCEN Mask */ + +#define I2S_CTL1_CH2ZCEN_Pos (2) /*!< I2S_T::CTL1: CH2ZCEN Position */ +#define I2S_CTL1_CH2ZCEN_Msk (0x1ul << I2S_CTL1_CH2ZCEN_Pos) /*!< I2S_T::CTL1: CH2ZCEN Mask */ + +#define I2S_CTL1_CH3ZCEN_Pos (3) /*!< I2S_T::CTL1: CH3ZCEN Position */ +#define I2S_CTL1_CH3ZCEN_Msk (0x1ul << I2S_CTL1_CH3ZCEN_Pos) /*!< I2S_T::CTL1: CH3ZCEN Mask */ + +#define I2S_CTL1_CH4ZCEN_Pos (4) /*!< I2S_T::CTL1: CH4ZCEN Position */ +#define I2S_CTL1_CH4ZCEN_Msk (0x1ul << I2S_CTL1_CH4ZCEN_Pos) /*!< I2S_T::CTL1: CH4ZCEN Mask */ + +#define I2S_CTL1_CH5ZCEN_Pos (5) /*!< I2S_T::CTL1: CH5ZCEN Position */ +#define I2S_CTL1_CH5ZCEN_Msk (0x1ul << I2S_CTL1_CH5ZCEN_Pos) /*!< I2S_T::CTL1: CH5ZCEN Mask */ + +#define I2S_CTL1_CH6ZCEN_Pos (6) /*!< I2S_T::CTL1: CH6ZCEN Position */ +#define I2S_CTL1_CH6ZCEN_Msk (0x1ul << I2S_CTL1_CH6ZCEN_Pos) /*!< I2S_T::CTL1: CH6ZCEN Mask */ + +#define I2S_CTL1_CH7ZCEN_Pos (7) /*!< I2S_T::CTL1: CH7ZCEN Position */ +#define I2S_CTL1_CH7ZCEN_Msk (0x1ul << I2S_CTL1_CH7ZCEN_Pos) /*!< I2S_T::CTL1: CH7ZCEN Mask */ + +#define I2S_CTL1_TXTH_Pos (8) /*!< I2S_T::CTL1: TXTH Position */ +#define I2S_CTL1_TXTH_Msk (0xful << I2S_CTL1_TXTH_Pos) /*!< I2S_T::CTL1: TXTH Mask */ + +#define I2S_CTL1_RXTH_Pos (16) /*!< I2S_T::CTL1: RXTH Position */ +#define I2S_CTL1_RXTH_Msk (0xful << I2S_CTL1_RXTH_Pos) /*!< I2S_T::CTL1: RXTH Mask */ + +#define I2S_CTL1_PBWIDTH_Pos (24) /*!< I2S_T::CTL1: PBWIDTH Position */ +#define I2S_CTL1_PBWIDTH_Msk (0x1ul << I2S_CTL1_PBWIDTH_Pos) /*!< I2S_T::CTL1: PBWIDTH Mask */ + +#define I2S_CTL1_PB16ORD_Pos (25) /*!< I2S_T::CTL1: PB16ORD Position */ +#define I2S_CTL1_PB16ORD_Msk (0x1ul << I2S_CTL1_PB16ORD_Pos) /*!< I2S_T::CTL1: PB16ORD Mask */ + +#define I2S_STATUS1_CH0ZCIF_Pos (0) /*!< I2S_T::STATUS1: CH0ZCIF Position */ +#define I2S_STATUS1_CH0ZCIF_Msk (0x1ul << I2S_STATUS1_CH0ZCIF_Pos) /*!< I2S_T::STATUS1: CH0ZCIF Mask */ + +#define I2S_STATUS1_CH1ZCIF_Pos (1) /*!< I2S_T::STATUS1: CH1ZCIF Position */ +#define I2S_STATUS1_CH1ZCIF_Msk (0x1ul << I2S_STATUS1_CH1ZCIF_Pos) /*!< I2S_T::STATUS1: CH1ZCIF Mask */ + +#define I2S_STATUS1_CH2ZCIF_Pos (2) /*!< I2S_T::STATUS1: CH2ZCIF Position */ +#define I2S_STATUS1_CH2ZCIF_Msk (0x1ul << I2S_STATUS1_CH2ZCIF_Pos) /*!< I2S_T::STATUS1: CH2ZCIF Mask */ + +#define I2S_STATUS1_CH3ZCIF_Pos (3) /*!< I2S_T::STATUS1: CH3ZCIF Position */ +#define I2S_STATUS1_CH3ZCIF_Msk (0x1ul << I2S_STATUS1_CH3ZCIF_Pos) /*!< I2S_T::STATUS1: CH3ZCIF Mask */ + +#define I2S_STATUS1_CH4ZCIF_Pos (4) /*!< I2S_T::STATUS1: CH4ZCIF Position */ +#define I2S_STATUS1_CH4ZCIF_Msk (0x1ul << I2S_STATUS1_CH4ZCIF_Pos) /*!< I2S_T::STATUS1: CH4ZCIF Mask */ + +#define I2S_STATUS1_CH5ZCIF_Pos (5) /*!< I2S_T::STATUS1: CH5ZCIF Position */ +#define I2S_STATUS1_CH5ZCIF_Msk (0x1ul << I2S_STATUS1_CH5ZCIF_Pos) /*!< I2S_T::STATUS1: CH5ZCIF Mask */ + +#define I2S_STATUS1_CH6ZCIF_Pos (6) /*!< I2S_T::STATUS1: CH6ZCIF Position */ +#define I2S_STATUS1_CH6ZCIF_Msk (0x1ul << I2S_STATUS1_CH6ZCIF_Pos) /*!< I2S_T::STATUS1: CH6ZCIF Mask */ + +#define I2S_STATUS1_CH7ZCIF_Pos (7) /*!< I2S_T::STATUS1: CH7ZCIF Position */ +#define I2S_STATUS1_CH7ZCIF_Msk (0x1ul << I2S_STATUS1_CH7ZCIF_Pos) /*!< I2S_T::STATUS1: CH7ZCIF Mask */ + +#define I2S_STATUS1_TXCNT_Pos (8) /*!< I2S_T::STATUS1: TXCNT Position */ +#define I2S_STATUS1_TXCNT_Msk (0x1ful << I2S_STATUS1_TXCNT_Pos) /*!< I2S_T::STATUS1: TXCNT Mask */ + +#define I2S_STATUS1_RXCNT_Pos (16) /*!< I2S_T::STATUS1: RXCNT Position */ +#define I2S_STATUS1_RXCNT_Msk (0x1ful << I2S_STATUS1_RXCNT_Pos) /*!< I2S_T::STATUS1: RXCNT Mask */ + +/**@}*/ /* I2S_CONST */ +/**@}*/ /* end of I2S register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __I2S_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/opa_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/opa_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..c28268a8236483644a430cb617cff5f2ed8eb942 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/opa_reg.h @@ -0,0 +1,268 @@ +/**************************************************************************//** + * @file opa_reg.h + * @version V1.00 + * @brief OPA register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __OPA_REG_H__ +#define __OPA_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup OPA OP Amplifier(OPA) + Memory Mapped Structure for OPA Controller +@{ */ + +typedef struct +{ + + + /** + * @var OPA_T::CTL + * Offset: 0x00 OP Amplifier Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |OPEN0 |OP Amplifier 0 Enable Bit + * | | |0 = OP amplifier0 Disabled. + * | | |1 = OP amplifier0 Enabled. + * | | |Note: OP Amplifier 0 output needs wait stable 20u03BCs after OPEN0 is set. + * |[1] |OPEN1 |OP Amplifier 1 Enable Bit + * | | |0 = OP amplifier1 Disabled. + * | | |1 = OP amplifier1 Enabled. + * | | |Note: OP Amplifier 1 output needs wait stable 20u03BCs after OPEN1 is set. + * |[2] |OPEN2 |OP Amplifier 2 Enable Bit + * | | |0 = OP amplifier2 Disabled. + * | | |1 = OP amplifier2 Enabled. + * | | |Note: OP Amplifier 2 output needs wait stable 20u03BCs after OPEN2 is set. + * |[4] |OPDOEN0 |OP Amplifier 0 Schmitt Trigger Non-inverting Buffer Enable Bit + * | | |0 = OP amplifier0 Schmitt Trigger non-invert buffer Disabled. + * | | |1 = OP amplifier0 Schmitt Trigger non-invert buffer Enabled. + * |[5] |OPDOEN1 |OP Amplifier 1 Schmitt Trigger Non-inverting Buffer Enable Bit + * | | |0 = OP amplifier1 Schmitt Trigger non-invert buffer Disabled. + * | | |1 = OP amplifier1 Schmitt Trigger non-invert buffer Enabled. + * |[6] |OPDOEN2 |OP Amplifier 2 Schmitt Trigger Non-inverting Buffer Enable Bit + * | | |0 = OP amplifier2 Schmitt Trigger non-invert buffer Disabled. + * | | |1 = OP amplifier2 Schmitt Trigger non-invert buffer Enabled. + * |[8] |OPDOIEN0 |OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Enable Bit + * | | |0 = OP Amplifier 0 digital output interrupt function Disabled. + * | | |1 = OP Amplifier 0 digital output interrupt function Enabled. + * | | |The OPDOIF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt Trigger non-inverting buffer digital output changes state, in the meanwhile, if OPDOIEN0 is set to 1, a comparator interrupt request is generated. + * |[9] |OPDOIEN1 |OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Enable Bit + * | | |0 = OP Amplifier 1 digital output interrupt function Disabled. + * | | |1 = OP Amplifier 1 digital output interrupt function Enabled. + * | | |OPDOIF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state, in the meanwhile, if OPDOIEN1 is set to 1, a comparator interrupt request is generated. + * |[10] |OPDOIEN2 |OP Amplifier 2 Schmitt Trigger Digital Output Interrupt Enable Bit + * | | |0 = OP Amplifier 2 digital output interrupt function Disabled. + * | | |1 = OP Amplifier 2 digital output interrupt function Enabled. + * | | |OPDOIF2 interrupt flag is set by hardware whenever the OP amplifier 2 Schmitt Trigger non-inverting buffer digital output changes state, in the meanwhile, if OPDOIEN2 is set to 1, a comparator interrupt request is generated. + * @var OPA_T::STATUS + * Offset: 0x04 OP Amplifier Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |OPDO0 |OP Amplifier 0 Digital Output + * | | |Synchronized to the APB clock to allow reading by software + * | | |Cleared when the Schmitt Trigger buffer is disabled (OPDOEN0 = 0) + * |[1] |OPDO1 |OP Amplifier 1 Digital Output + * | | |Synchronized to the APB clock to allow reading by software + * | | |Cleared when the Schmitt Trigger buffer is disabled (OPDOEN1 = 0) + * |[2] |OPDO2 |OP Amplifier 2 Digital Output + * | | |Synchronized to the APB clock to allow reading by software + * | | |Cleared when the Schmitt Trigger buffer is disabled (OPDOEN2 = 0) + * |[4] |OPDOIF0 |OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Flag + * | | |OPDOIF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt Trigger non-inverting buffer digital output changes state + * | | |This bit is cleared by writing 1 to it. + * |[5] |OPDOIF1 |OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Flag + * | | |OPDOIF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt Trigger non-inverting buffer digital output changes state + * | | |This bit is cleared by writing 1 to it. + * |[6] |OPDOIF2 |OP Amplifier 2 Schmitt Trigger Digital Output Interrupt Flag + * | | |OPDOIF2 interrupt flag is set by hardware whenever the OP amplifier 2 Schmitt Trigger non-inverting buffer digital output changes state + * | | |This bit is cleared by writing 1 to it. + * @var OPA_T::CALCTL + * Offset: 0x08 OP Amplifier Calibration Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CALTRG0 |OP Amplifier 0 Calibration Trigger Bit + * | | |0 = Stop, hardware auto clear. + * | | |1 = Start. Note: Before enable this bit, it should set OPEN0 in advance. + * |[1] |CALTRG1 |OP Amplifier 1 Calibration Trigger Bit + * | | |0 = Stop, hardware auto clear. + * | | |1 = Start. Note: Before enable this bit, it should set OPEN1 in advance. + * |[2] |CALTRG2 |OP Amplifier 2 Calibration Trigger Bit + * | | |0 = Stop, hardware auto clear. + * | | |1 = Start. Note: Before enable this bit, it should set OPEN2 in advance. + * |[16] |CALRVS0 |OPA0 Calibration Reference Voltage Selection + * | | |0 = VREF is AVDD. + * | | |1 = VREF from high vcm to low vcm. + * |[17] |CALRVS1 |OPA1 Calibration Reference Voltage Selection + * | | |0 = VREF is AVDD. + * | | |1 = VREF from high vcm to low vcm. + * |[18] |CALRVS2 |OPA2 Calibration Reference Voltage Selection + * | | |0 = VREF is AVDD. + * | | |1 = VREF from high vcm to low vcm. + * @var OPA_T::CALST + * Offset: 0x0C OP Amplifier Calibration Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DONE0 |OP Amplifier 0 Calibration Done Status + * | | |0 = Calibrating. + * | | |1 = Calibration Done. + * |[1] |CALNS0 |OP Amplifier 0 Calibration Result Status for NMOS + * | | |0 = Pass. + * | | |1 = Fail. + * |[2] |CALPS0 |OP Amplifier 0 Calibration Result Status for PMOS + * | | |0 = Pass. + * | | |1 = Fail. + * |[4] |DONE1 |OP Amplifier 1 Calibration Done Status + * | | |0 = Calibrating. + * | | |1 = Calibration Done. + * |[5] |CALNS1 |OP Amplifier 1 Calibration Result Status for NMOS + * | | |0 = Pass. + * | | |1 = Fail. + * |[6] |CALPS1 |OP Amplifier 1 Calibration Result Status for PMOS + * | | |0 = Pass. + * | | |1 = Fail. + * |[8] |DONE2 |OP Amplifier 2 Calibration Done Status + * | | |0 = Calibrating. + * | | |1 = Calibration Done. + * |[9] |CALNS2 |OP Amplifier 2 Calibration Result Status for NMOS + * | | |0 = Pass. + * | | |1 = Fail. + * |[10] |CALPS2 |OP Amplifier 2 Calibration Result Status for PMOS + * | | |0 = Pass. + * | | |1 = Fail. + */ + __IO uint32_t CTL; /*!< [0x0000] OP Amplifier Control Register */ + __IO uint32_t STATUS; /*!< [0x0004] OP Amplifier Status Register */ + __IO uint32_t CALCTL; /*!< [0x0008] OP Amplifier Calibration Control Register */ + __I uint32_t CALST; /*!< [0x000c] OP Amplifier Calibration Status Register */ + +} OPA_T; + +/** + @addtogroup OPA_CONST OPA Bit Field Definition + Constant Definitions for OPA Controller +@{ */ + +#define OPA_CTL_OPEN0_Pos (0) /*!< OPA_T::CTL: OPEN0 Position */ +#define OPA_CTL_OPEN0_Msk (0x1ul << OPA_CTL_OPEN0_Pos) /*!< OPA_T::CTL: OPEN0 Mask */ + +#define OPA_CTL_OPEN1_Pos (1) /*!< OPA_T::CTL: OPEN1 Position */ +#define OPA_CTL_OPEN1_Msk (0x1ul << OPA_CTL_OPEN1_Pos) /*!< OPA_T::CTL: OPEN1 Mask */ + +#define OPA_CTL_OPEN2_Pos (2) /*!< OPA_T::CTL: OPEN2 Position */ +#define OPA_CTL_OPEN2_Msk (0x1ul << OPA_CTL_OPEN2_Pos) /*!< OPA_T::CTL: OPEN2 Mask */ + +#define OPA_CTL_OPDOEN0_Pos (4) /*!< OPA_T::CTL: OPDOEN0 Position */ +#define OPA_CTL_OPDOEN0_Msk (0x1ul << OPA_CTL_OPDOEN0_Pos) /*!< OPA_T::CTL: OPDOEN0 Mask */ + +#define OPA_CTL_OPDOEN1_Pos (5) /*!< OPA_T::CTL: OPDOEN1 Position */ +#define OPA_CTL_OPDOEN1_Msk (0x1ul << OPA_CTL_OPDOEN1_Pos) /*!< OPA_T::CTL: OPDOEN1 Mask */ + +#define OPA_CTL_OPDOEN2_Pos (6) /*!< OPA_T::CTL: OPDOEN2 Position */ +#define OPA_CTL_OPDOEN2_Msk (0x1ul << OPA_CTL_OPDOEN2_Pos) /*!< OPA_T::CTL: OPDOEN2 Mask */ + +#define OPA_CTL_OPDOIEN0_Pos (8) /*!< OPA_T::CTL: OPDOIEN0 Position */ +#define OPA_CTL_OPDOIEN0_Msk (0x1ul << OPA_CTL_OPDOIEN0_Pos) /*!< OPA_T::CTL: OPDOIEN0 Mask */ + +#define OPA_CTL_OPDOIEN1_Pos (9) /*!< OPA_T::CTL: OPDOIEN1 Position */ +#define OPA_CTL_OPDOIEN1_Msk (0x1ul << OPA_CTL_OPDOIEN1_Pos) /*!< OPA_T::CTL: OPDOIEN1 Mask */ + +#define OPA_CTL_OPDOIEN2_Pos (10) /*!< OPA_T::CTL: OPDOIEN2 Position */ +#define OPA_CTL_OPDOIEN2_Msk (0x1ul << OPA_CTL_OPDOIEN2_Pos) /*!< OPA_T::CTL: OPDOIEN2 Mask */ + +#define OPA_STATUS_OPDO0_Pos (0) /*!< OPA_T::STATUS: OPDO0 Position */ +#define OPA_STATUS_OPDO0_Msk (0x1ul << OPA_STATUS_OPDO0_Pos) /*!< OPA_T::STATUS: OPDO0 Mask */ + +#define OPA_STATUS_OPDO1_Pos (1) /*!< OPA_T::STATUS: OPDO1 Position */ +#define OPA_STATUS_OPDO1_Msk (0x1ul << OPA_STATUS_OPDO1_Pos) /*!< OPA_T::STATUS: OPDO1 Mask */ + +#define OPA_STATUS_OPDO2_Pos (2) /*!< OPA_T::STATUS: OPDO2 Position */ +#define OPA_STATUS_OPDO2_Msk (0x1ul << OPA_STATUS_OPDO2_Pos) /*!< OPA_T::STATUS: OPDO2 Mask */ + +#define OPA_STATUS_OPDOIF0_Pos (4) /*!< OPA_T::STATUS: OPDOIF0 Position */ +#define OPA_STATUS_OPDOIF0_Msk (0x1ul << OPA_STATUS_OPDOIF0_Pos) /*!< OPA_T::STATUS: OPDOIF0 Mask */ + +#define OPA_STATUS_OPDOIF1_Pos (5) /*!< OPA_T::STATUS: OPDOIF1 Position */ +#define OPA_STATUS_OPDOIF1_Msk (0x1ul << OPA_STATUS_OPDOIF1_Pos) /*!< OPA_T::STATUS: OPDOIF1 Mask */ + +#define OPA_STATUS_OPDOIF2_Pos (6) /*!< OPA_T::STATUS: OPDOIF2 Position */ +#define OPA_STATUS_OPDOIF2_Msk (0x1ul << OPA_STATUS_OPDOIF2_Pos) /*!< OPA_T::STATUS: OPDOIF2 Mask */ + +#define OPA_CALCTL_CALTRG0_Pos (0) /*!< OPA_T::CALCTL: CALTRG0 Position */ +#define OPA_CALCTL_CALTRG0_Msk (0x1ul << OPA_CALCTL_CALTRG0_Pos) /*!< OPA_T::CALCTL: CALTRG0 Mask */ + +#define OPA_CALCTL_CALTRG1_Pos (1) /*!< OPA_T::CALCTL: CALTRG1 Position */ +#define OPA_CALCTL_CALTRG1_Msk (0x1ul << OPA_CALCTL_CALTRG1_Pos) /*!< OPA_T::CALCTL: CALTRG1 Mask */ + +#define OPA_CALCTL_CALTRG2_Pos (2) /*!< OPA_T::CALCTL: CALTRG2 Position */ +#define OPA_CALCTL_CALTRG2_Msk (0x1ul << OPA_CALCTL_CALTRG2_Pos) /*!< OPA_T::CALCTL: CALTRG2 Mask */ + +#define OPA_CALCTL_CALCLK0_Pos (4) /*!< OPA_T::CALCTL: CALCLK0 Position */ +#define OPA_CALCTL_CALCLK0_Msk (0x3ul << OPA_CALCTL_CALCLK0_Pos) /*!< OPA_T::CALCTL: CALCLK0 Mask */ + +#define OPA_CALCTL_CALCLK1_Pos (6) /*!< OPA_T::CALCTL: CALCLK1 Position */ +#define OPA_CALCTL_CALCLK1_Msk (0x3ul << OPA_CALCTL_CALCLK1_Pos) /*!< OPA_T::CALCTL: CALCLK1 Mask */ + +#define OPA_CALCTL_CALCLK2_Pos (8) /*!< OPA_T::CALCTL: CALCLK2 Position */ +#define OPA_CALCTL_CALCLK2_Msk (0x3ul << OPA_CALCTL_CALCLK2_Pos) /*!< OPA_T::CALCTL: CALCLK2 Mask */ + +#define OPA_CALCTL_CALRVS0_Pos (16) /*!< OPA_T::CALCTL: CALRVS0 Position */ +#define OPA_CALCTL_CALRVS0_Msk (0x1ul << OPA_CALCTL_CALRVS0_Pos) /*!< OPA_T::CALCTL: CALRVS0 Mask */ + +#define OPA_CALCTL_CALRVS1_Pos (17) /*!< OPA_T::CALCTL: CALRVS1 Position */ +#define OPA_CALCTL_CALRVS1_Msk (0x1ul << OPA_CALCTL_CALRVS1_Pos) /*!< OPA_T::CALCTL: CALRVS1 Mask */ + +#define OPA_CALCTL_CALRVS2_Pos (18) /*!< OPA_T::CALCTL: CALRVS2 Position */ +#define OPA_CALCTL_CALRVS2_Msk (0x1ul << OPA_CALCTL_CALRVS2_Pos) /*!< OPA_T::CALCTL: CALRVS2 Mask */ + +#define OPA_CALST_DONE0_Pos (0) /*!< OPA_T::CALST: DONE0 Position */ +#define OPA_CALST_DONE0_Msk (0x1ul << OPA_CALST_DONE0_Pos) /*!< OPA_T::CALST: DONE0 Mask */ + +#define OPA_CALST_CALNS0_Pos (1) /*!< OPA_T::CALST: CALNS0 Position */ +#define OPA_CALST_CALNS0_Msk (0x1ul << OPA_CALST_CALNS0_Pos) /*!< OPA_T::CALST: CALNS0 Mask */ + +#define OPA_CALST_CALPS0_Pos (2) /*!< OPA_T::CALST: CALPS0 Position */ +#define OPA_CALST_CALPS0_Msk (0x1ul << OPA_CALST_CALPS0_Pos) /*!< OPA_T::CALST: CALPS0 Mask */ + +#define OPA_CALST_DONE1_Pos (4) /*!< OPA_T::CALST: DONE1 Position */ +#define OPA_CALST_DONE1_Msk (0x1ul << OPA_CALST_DONE1_Pos) /*!< OPA_T::CALST: DONE1 Mask */ + +#define OPA_CALST_CALNS1_Pos (5) /*!< OPA_T::CALST: CALNS1 Position */ +#define OPA_CALST_CALNS1_Msk (0x1ul << OPA_CALST_CALNS1_Pos) /*!< OPA_T::CALST: CALNS1 Mask */ + +#define OPA_CALST_CALPS1_Pos (6) /*!< OPA_T::CALST: CALPS1 Position */ +#define OPA_CALST_CALPS1_Msk (0x1ul << OPA_CALST_CALPS1_Pos) /*!< OPA_T::CALST: CALPS1 Mask */ + +#define OPA_CALST_DONE2_Pos (8) /*!< OPA_T::CALST: DONE2 Position */ +#define OPA_CALST_DONE2_Msk (0x1ul << OPA_CALST_DONE2_Pos) /*!< OPA_T::CALST: DONE2 Mask */ + +#define OPA_CALST_CALNS2_Pos (9) /*!< OPA_T::CALST: CALNS2 Position */ +#define OPA_CALST_CALNS2_Msk (0x1ul << OPA_CALST_CALNS2_Pos) /*!< OPA_T::CALST: CALNS2 Mask */ + +#define OPA_CALST_CALPS2_Pos (10) /*!< OPA_T::CALST: CALPS2 Position */ +#define OPA_CALST_CALPS2_Msk (0x1ul << OPA_CALST_CALPS2_Pos) /*!< OPA_T::CALST: CALPS2 Mask */ + +/**@}*/ /* OPA_CONST */ +/**@}*/ /* end of OPA register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __OPA_REG_H__ */ + diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/otg_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/otg_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..03900262008530db15e471096c6ad2a2bcd57768 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/otg_reg.h @@ -0,0 +1,399 @@ +/**************************************************************************//** + * @file otg_reg.h + * @version V1.00 + * @brief OTG register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __OTG_REG_H__ +#define __OTG_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup OTG USB On-The-Go Controller(OTG) + Memory Mapped Structure for OTG Controller +@{ */ + +typedef struct +{ + + + /** + * @var OTG_T::CTL + * Offset: 0x00 OTG Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |VBUSDROP |Drop VBUS Control + * | | |If user application running on this OTG A-device wants to conserve power, set this bit to drop VBUS + * | | |BUSREQ (OTG_CTL[1]) will be also cleared no matter A-device or B-device. + * | | |0 = Not drop the VBUS. + * | | |1 = Drop the VBUS. + * |[1] |BUSREQ |OTG Bus Request + * | | |If OTG A-device wants to do data transfers via USB bus, setting this bit will drive VBUS high to detect USB device connection + * | | |If user won't use the bus any more, clearing this bit will drop VBUS to save power + * | | |This bit will be cleared when A-device goes to A_wait_vfall state + * | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed. + * | | |If user of an OTG-B Device wants to request VBUS, setting this bit will run SRP protocol + * | | |This bit will be cleared if SRP failure (OTG A-device does not provide VBUS after B-device issues ARP in specified interval, defined in OTG specification) + * | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set IDSTS (OTG_STATUS[1]) changed. + * | | |0 = Not launch VBUS in OTG A-device or not request SRP in OTG B-device. + * | | |1 = Launch VBUS in OTG A-device or request SRP in OTG B-device. + * |[2] |HNPREQEN |OTG HNP Request Enable Bit + * | | |When USB frame as A-device, set this bit when A-device allows to process HNP protocol -- A-device changes role from Host to Peripheral + * | | |This bit will be cleared when OTG state changes from a_suspend to a_peripheral or goes back to a_idle state + * | | |When USB frame as B-device, set this bit after the OTG A-device successfully sends a SetFeature (b_hnp_enable) command to the OTG B-device to start role change -- B-device changes role from Peripheral to Host + * | | |This bit will be cleared when OTG state changes from b_peripheral to b_wait_acon or goes back to b_idle state. + * | | |0 = HNP request Disabled. + * | | |1 = HNP request Enabled (A-device can change role from Host to Peripheral or B-device can change role from Peripheral to Host). + * | | |Note: Refer to OTG specification to get a_suspend, a_peripheral, a_idle and b_idle state. + * |[4] |OTGEN |OTG Function Enable Bit + * | | |User needs to set this bit to enable OTG function while USB frame configured as OTG device + * | | |When USB frame not configured as OTG device, this bit is must be low. + * | | |0= OTG function Disabled. + * | | |1 = OTG function Enabled. + * |[5] |WKEN |OTG ID Pin Wake-up Enable Bit + * | | |0 = OTG ID pin status change wake-up function Disabled. + * | | |1 = OTG ID pin status change wake-up function Enabled. + * @var OTG_T::PHYCTL + * Offset: 0x04 OTG PHY Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |OTGPHYEN |OTG PHY Enable + * | | |When USB frame is configured as OTG-device or ID-dependent, user needs to set this bit before using OTG function + * | | |If device is not configured as OTG-device nor ID-dependent , this bit is "don't care". + * | | |0 = OTG PHY Disabled. + * | | |1 = OTG PHY Enabled. + * |[1] |IDDETEN |ID Detection Enable Bit + * | | |0 = Detect ID pin status Disabled. + * | | |1 = Detect ID pin status Enabled. + * |[4] |VBENPOL |Off-chip USB VBUS Power Switch Enable Polarity + * | | |The OTG controller will enable off-chip USB VBUS power switch to provide VBUS power when need + * | | |A USB_VBUS_EN pin is used to control the off-chip USB VBUS power switch. + * | | |The polarity of enabling off-chip USB VBUS power switch (high active or low active) depends on the selected component + * | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch. + * | | |0 = The off-chip USB VBUS power switch enable is active high. + * | | |1 = The off-chip USB VBUS power switch enable is active low. + * |[5] |VBSTSPOL |Off-chip USB VBUS Power Switch Status Polarity + * | | |The polarity of off-chip USB VBUS power switch valid signal depends on the selected component + * | | |A USB_VBUS_ST pin is used to monitor the valid signal of the off-chip USB VBUS power switch + * | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch. + * | | |0 = The polarity of off-chip USB VBUS power switch valid status is high. + * | | |1 = The polarity of off-chip USB VBUS power switch valid status is low. + * @var OTG_T::INTEN + * Offset: 0x08 OTG Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ROLECHGIEN|Role (Host or Peripheral) Changed Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[1] |VBEIEN |VBUS Error Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG spec. + * |[2] |SRPFIEN |SRP Fail Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[3] |HNPFIEN |HNP Fail Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[4] |GOIDLEIEN |OTG Device Goes to IDLE State Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Going to idle state means going to a_idle or b_idle state + * | | |Please refer to A-device state diagram and B-device state diagram in OTG spec. + * |[5] |IDCHGIEN |IDSTS Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and IDSTS (OTG_STATUS[1]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[6] |PDEVIEN |Act As Peripheral Interrupt Enable Bit + * | | |If this bit is set to 1 and the device is changed as a peripheral, a interrupt will be asserted. + * | | |0 = This device as a peripheral interrupt Disabled. + * | | |1 = This device as a peripheral interrupt Enabled. + * |[7] |HOSTIEN |Act As Host Interrupt Enable Bit + * | | |If this bit is set to 1 and the device is changed as a host, a interrupt will be asserted. + * | | |0 = This device as a host interrupt Disabled. + * | | |1 = This device as a host interrupt Enabled. + * |[8] |BVLDCHGIEN|B-device Session Valid Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and BVLD (OTG_STATUS[3]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[9] |AVLDCHGIEN|A-device Session Valid Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and AVLD (OTG_STATUS[4]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[10] |VBCHGIEN |VBUSVLD Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and VBUSVLD (OTG_STATUS[5]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[11] |SECHGIEN |SESSEND Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and SESSEND (OTG_STATUS[2]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[13] |SRPDETIEN |SRP Detected Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * @var OTG_T::INTSTS + * Offset: 0x0C OTG Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ROLECHGIF |OTG Role Change Interrupt Status + * | | |This flag is set when the role of an OTG device changed from a host to a peripheral, or changed from a peripheral to a host while USB_ID pin status does not change. + * | | |0 = OTG device role not changed. + * | | |1 = OTG device role changed. + * | | |Note: Write 1 to clear this flag. + * |[1] |VBEIF |VBUS Error Interrupt Status + * | | |This bit will be set when voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A-device starting to drive VBUS high. + * | | |0 = OTG A-device drives VBUS over threshold voltage before this interval expires. + * | | |1 = OTG A-device cannot drive VBUS over threshold voltage before this interval expires. + * | | |Note: Write 1 to clear this flag and recover from the VBUS error state. + * |[2] |SRPFIF |SRP Fail Interrupt Status + * | | |After initiating SRP, an OTG B-device will wait for the OTG A-device to drive VBUS high at least TB_SRP_FAIL minimum, defined in OTG specification + * | | |This flag is set when the OTG B-device does not get VBUS high after this interval. + * | | |0 = OTG B-device gets VBUS high before this interval. + * | | |1 = OTG B-device does not get VBUS high before this interval. + * | | |Note: Write 1 to clear this flag. + * |[3] |HNPFIF |HNP Fail Interrupt Status + * | | |When A-device has granted B-device to be host and USB bus is in SE0 (both USB_D+ and USB_D- low) state, this bit will be set when A-device does not connect after specified interval expires. + * | | |0 = A-device connects to B-device before specified interval expires. + * | | |1 = A-device does not connect to B-device before specified interval expires. + * | | |Note: Write 1 to clear this flag. + * |[4] |GOIDLEIF |OTG Device Goes to IDLE Interrupt Status + * | | |Flag is set if the OTG device transfers from non-idle state to idle state + * | | |The OTG device will be neither a host nor a peripheral. + * | | |0 = OTG device does not go back to idle state (a_idle or b_idle). + * | | |1 = OTG device goes back to idle state(a_idle or b_idle). + * | | |Note 1: Going to idle state means going to a_idle or b_idle state. Please refer to OTG specification. + * | | |Note 2: Write 1 to clear this flag. + * |[5] |IDCHGIF |ID State Change Interrupt Status + * | | |0 = IDSTS (OTG_STATUS[1]) not toggled. + * | | |1 = IDSTS (OTG_STATUS[1]) from high to low or from low to high. + * | | |Note: Write 1 to clear this flag. + * |[6] |PDEVIF |Act As Peripheral Interrupt Status + * | | |0= This device does not act as a peripheral. + * | | |1 = This device acts as a peripheral. + * | | |Note: Write 1 to clear this flag. + * |[7] |HOSTIF |Act As Host Interrupt Status + * | | |0= This device does not act as a host. + * | | |1 = This device acts as a host. + * | | |Note: Write 1 to clear this flag. + * |[8] |BVLDCHGIF |B-device Session Valid State Change Interrupt Status + * | | |0 = BVLD (OTG_STATUS[3]) is not toggled. + * | | |1 = BVLD (OTG_STATUS[3]) from high to low or low to high. + * | | |Note: Write 1 to clear this status. + * |[9] |AVLDCHGIF |A-device Session Valid State Change Interrupt Status + * | | |0 = AVLD (OTG_STATUS[4]) not toggled. + * | | |1 = AVLD (OTG_STATUS[4]) from high to low or low to high. + * | | |Note: Write 1 to clear this status. + * |[10] |VBCHGIF |VBUSVLD State Change Interrupt Status + * | | |0 = VBUSVLD (OTG_STATUS[5]) not toggled. + * | | |1 = VBUSVLD (OTG_STATUS[5]) from high to low or from low to high. + * | | |Note: Write 1 to clear this status. + * |[11] |SECHGIF |SESSEND State Change Interrupt Status + * | | |0 = SESSEND (OTG_STATUS[2]) not toggled. + * | | |1 = SESSEND (OTG_STATUS[2]) from high to low or from low to high. + * | | |Note: Write 1 to clear this flag. + * |[13] |SRPDETIF |SRP Detected Interrupt Status + * | | |0 = SRP not detected. + * | | |1 = SRP detected. + * | | |Note: Write 1 to clear this status. + * @var OTG_T::STATUS + * Offset: 0x10 OTG Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |OVERCUR |over Current Condition + * | | |The voltage on VBUS cannot reach a minimum VBUS valid threshold, 4.4V minimum, within a maximum time of 100ms after OTG A-device drives VBUS high. + * | | |0 = OTG A-device drives VBUS successfully. + * | | |1 = OTG A-device cannot drives VBUS high in this interval. + * |[1] |IDSTS |USB_ID Pin State of Mini-b/Micro-plug + * | | |0 = Mini-A/Micro-A plug is attached. + * | | |1 = Mini-B/Micro-B plug is attached. + * |[2] |SESSEND |Session End Status + * | | |When VBUS voltage is lower than 0.4V, this bit will be set to 1 + * | | |Session end means no meaningful power on VBUS. + * | | |0 = Session is not end. + * | | |1 = Session is end. + * |[3] |BVLD |B-device Session Valid Status + * | | |0 = B-device session is not valid. + * | | |1 = B-device session is valid. + * |[4] |AVLD |A-device Session Valid Status + * | | |0 = A-device session is not valid. + * | | |1 = A-device session is valid. + * |[5] |VBUSVLD |VBUS Valid Status + * | | |When VBUS is larger than 4.7V, this bit will be set to 1. + * | | |0 = VBUS is not valid. + * | | |1 = VBUS is valid. + * |[6] |ASPERI |As Peripheral Status + * | | |When OTG as peripheral, this bit is set. + * | | |0: OTG not as peripheral + * | | |1: OTG as peripheral + * |[7] |ASHOST |As Host Status + * | | |When OTG as Host, this bit is set. + * | | |0: OTG not as Host + * | | |1: OTG as Host + */ + __IO uint32_t CTL; /*!< [0x0000] OTG Control Register */ + __IO uint32_t PHYCTL; /*!< [0x0004] OTG PHY Control Register */ + __IO uint32_t INTEN; /*!< [0x0008] OTG Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x000c] OTG Interrupt Status Register */ + __I uint32_t STATUS; /*!< [0x0010] OTG Status Register */ + +} OTG_T; + + +/** + @addtogroup OTG_CONST OTG Bit Field Definition + Constant Definitions for OTG Controller +@{ */ + +#define OTG_CTL_VBUSDROP_Pos (0) /*!< OTG_T::CTL: VBUSDROP Position */ +#define OTG_CTL_VBUSDROP_Msk (0x1ul << OTG_CTL_VBUSDROP_Pos) /*!< OTG_T::CTL: VBUSDROP Mask */ + +#define OTG_CTL_BUSREQ_Pos (1) /*!< OTG_T::CTL: BUSREQ Position */ +#define OTG_CTL_BUSREQ_Msk (0x1ul << OTG_CTL_BUSREQ_Pos) /*!< OTG_T::CTL: BUSREQ Mask */ + +#define OTG_CTL_HNPREQEN_Pos (2) /*!< OTG_T::CTL: HNPREQEN Position */ +#define OTG_CTL_HNPREQEN_Msk (0x1ul << OTG_CTL_HNPREQEN_Pos) /*!< OTG_T::CTL: HNPREQEN Mask */ + +#define OTG_CTL_OTGEN_Pos (4) /*!< OTG_T::CTL: OTGEN Position */ +#define OTG_CTL_OTGEN_Msk (0x1ul << OTG_CTL_OTGEN_Pos) /*!< OTG_T::CTL: OTGEN Mask */ + +#define OTG_CTL_WKEN_Pos (5) /*!< OTG_T::CTL: WKEN Position */ +#define OTG_CTL_WKEN_Msk (0x1ul << OTG_CTL_WKEN_Pos) /*!< OTG_T::CTL: WKEN Mask */ + +#define OTG_PHYCTL_OTGPHYEN_Pos (0) /*!< OTG_T::PHYCTL: OTGPHYEN Position */ +#define OTG_PHYCTL_OTGPHYEN_Msk (0x1ul << OTG_PHYCTL_OTGPHYEN_Pos) /*!< OTG_T::PHYCTL: OTGPHYEN Mask */ + +#define OTG_PHYCTL_IDDETEN_Pos (1) /*!< OTG_T::PHYCTL: IDDETEN Position */ +#define OTG_PHYCTL_IDDETEN_Msk (0x1ul << OTG_PHYCTL_IDDETEN_Pos) /*!< OTG_T::PHYCTL: IDDETEN Mask */ + +#define OTG_PHYCTL_VBENPOL_Pos (4) /*!< OTG_T::PHYCTL: VBENPOL Position */ +#define OTG_PHYCTL_VBENPOL_Msk (0x1ul << OTG_PHYCTL_VBENPOL_Pos) /*!< OTG_T::PHYCTL: VBENPOL Mask */ + +#define OTG_PHYCTL_VBSTSPOL_Pos (5) /*!< OTG_T::PHYCTL: VBSTSPOL Position */ +#define OTG_PHYCTL_VBSTSPOL_Msk (0x1ul << OTG_PHYCTL_VBSTSPOL_Pos) /*!< OTG_T::PHYCTL: VBSTSPOL Mask */ + +#define OTG_INTEN_ROLECHGIEN_Pos (0) /*!< OTG_T::INTEN: ROLECHGIEN Position */ +#define OTG_INTEN_ROLECHGIEN_Msk (0x1ul << OTG_INTEN_ROLECHGIEN_Pos) /*!< OTG_T::INTEN: ROLECHGIEN Mask */ + +#define OTG_INTEN_VBEIEN_Pos (1) /*!< OTG_T::INTEN: VBEIEN Position */ +#define OTG_INTEN_VBEIEN_Msk (0x1ul << OTG_INTEN_VBEIEN_Pos) /*!< OTG_T::INTEN: VBEIEN Mask */ + +#define OTG_INTEN_SRPFIEN_Pos (2) /*!< OTG_T::INTEN: SRPFIEN Position */ +#define OTG_INTEN_SRPFIEN_Msk (0x1ul << OTG_INTEN_SRPFIEN_Pos) /*!< OTG_T::INTEN: SRPFIEN Mask */ + +#define OTG_INTEN_HNPFIEN_Pos (3) /*!< OTG_T::INTEN: HNPFIEN Position */ +#define OTG_INTEN_HNPFIEN_Msk (0x1ul << OTG_INTEN_HNPFIEN_Pos) /*!< OTG_T::INTEN: HNPFIEN Mask */ + +#define OTG_INTEN_GOIDLEIEN_Pos (4) /*!< OTG_T::INTEN: GOIDLEIEN Position */ +#define OTG_INTEN_GOIDLEIEN_Msk (0x1ul << OTG_INTEN_GOIDLEIEN_Pos) /*!< OTG_T::INTEN: GOIDLEIEN Mask */ + +#define OTG_INTEN_IDCHGIEN_Pos (5) /*!< OTG_T::INTEN: IDCHGIEN Position */ +#define OTG_INTEN_IDCHGIEN_Msk (0x1ul << OTG_INTEN_IDCHGIEN_Pos) /*!< OTG_T::INTEN: IDCHGIEN Mask */ + +#define OTG_INTEN_PDEVIEN_Pos (6) /*!< OTG_T::INTEN: PDEVIEN Position */ +#define OTG_INTEN_PDEVIEN_Msk (0x1ul << OTG_INTEN_PDEVIEN_Pos) /*!< OTG_T::INTEN: PDEVIEN Mask */ + +#define OTG_INTEN_HOSTIEN_Pos (7) /*!< OTG_T::INTEN: HOSTIEN Position */ +#define OTG_INTEN_HOSTIEN_Msk (0x1ul << OTG_INTEN_HOSTIEN_Pos) /*!< OTG_T::INTEN: HOSTIEN Mask */ + +#define OTG_INTEN_BVLDCHGIEN_Pos (8) /*!< OTG_T::INTEN: BVLDCHGIEN Position */ +#define OTG_INTEN_BVLDCHGIEN_Msk (0x1ul << OTG_INTEN_BVLDCHGIEN_Pos) /*!< OTG_T::INTEN: BVLDCHGIEN Mask */ + +#define OTG_INTEN_AVLDCHGIEN_Pos (9) /*!< OTG_T::INTEN: AVLDCHGIEN Position */ +#define OTG_INTEN_AVLDCHGIEN_Msk (0x1ul << OTG_INTEN_AVLDCHGIEN_Pos) /*!< OTG_T::INTEN: AVLDCHGIEN Mask */ + +#define OTG_INTEN_VBCHGIEN_Pos (10) /*!< OTG_T::INTEN: VBCHGIEN Position */ +#define OTG_INTEN_VBCHGIEN_Msk (0x1ul << OTG_INTEN_VBCHGIEN_Pos) /*!< OTG_T::INTEN: VBCHGIEN Mask */ + +#define OTG_INTEN_SECHGIEN_Pos (11) /*!< OTG_T::INTEN: SECHGIEN Position */ +#define OTG_INTEN_SECHGIEN_Msk (0x1ul << OTG_INTEN_SECHGIEN_Pos) /*!< OTG_T::INTEN: SECHGIEN Mask */ + +#define OTG_INTEN_SRPDETIEN_Pos (13) /*!< OTG_T::INTEN: SRPDETIEN Position */ +#define OTG_INTEN_SRPDETIEN_Msk (0x1ul << OTG_INTEN_SRPDETIEN_Pos) /*!< OTG_T::INTEN: SRPDETIEN Mask */ + +#define OTG_INTSTS_ROLECHGIF_Pos (0) /*!< OTG_T::INTSTS: ROLECHGIF Position */ +#define OTG_INTSTS_ROLECHGIF_Msk (0x1ul << OTG_INTSTS_ROLECHGIF_Pos) /*!< OTG_T::INTSTS: ROLECHGIF Mask */ + +#define OTG_INTSTS_VBEIF_Pos (1) /*!< OTG_T::INTSTS: VBEIF Position */ +#define OTG_INTSTS_VBEIF_Msk (0x1ul << OTG_INTSTS_VBEIF_Pos) /*!< OTG_T::INTSTS: VBEIF Mask */ + +#define OTG_INTSTS_SRPFIF_Pos (2) /*!< OTG_T::INTSTS: SRPFIF Position */ +#define OTG_INTSTS_SRPFIF_Msk (0x1ul << OTG_INTSTS_SRPFIF_Pos) /*!< OTG_T::INTSTS: SRPFIF Mask */ + +#define OTG_INTSTS_HNPFIF_Pos (3) /*!< OTG_T::INTSTS: HNPFIF Position */ +#define OTG_INTSTS_HNPFIF_Msk (0x1ul << OTG_INTSTS_HNPFIF_Pos) /*!< OTG_T::INTSTS: HNPFIF Mask */ + +#define OTG_INTSTS_GOIDLEIF_Pos (4) /*!< OTG_T::INTSTS: GOIDLEIF Position */ +#define OTG_INTSTS_GOIDLEIF_Msk (0x1ul << OTG_INTSTS_GOIDLEIF_Pos) /*!< OTG_T::INTSTS: GOIDLEIF Mask */ + +#define OTG_INTSTS_IDCHGIF_Pos (5) /*!< OTG_T::INTSTS: IDCHGIF Position */ +#define OTG_INTSTS_IDCHGIF_Msk (0x1ul << OTG_INTSTS_IDCHGIF_Pos) /*!< OTG_T::INTSTS: IDCHGIF Mask */ + +#define OTG_INTSTS_PDEVIF_Pos (6) /*!< OTG_T::INTSTS: PDEVIF Position */ +#define OTG_INTSTS_PDEVIF_Msk (0x1ul << OTG_INTSTS_PDEVIF_Pos) /*!< OTG_T::INTSTS: PDEVIF Mask */ + +#define OTG_INTSTS_HOSTIF_Pos (7) /*!< OTG_T::INTSTS: HOSTIF Position */ +#define OTG_INTSTS_HOSTIF_Msk (0x1ul << OTG_INTSTS_HOSTIF_Pos) /*!< OTG_T::INTSTS: HOSTIF Mask */ + +#define OTG_INTSTS_BVLDCHGIF_Pos (8) /*!< OTG_T::INTSTS: BVLDCHGIF Position */ +#define OTG_INTSTS_BVLDCHGIF_Msk (0x1ul << OTG_INTSTS_BVLDCHGIF_Pos) /*!< OTG_T::INTSTS: BVLDCHGIF Mask */ + +#define OTG_INTSTS_AVLDCHGIF_Pos (9) /*!< OTG_T::INTSTS: AVLDCHGIF Position */ +#define OTG_INTSTS_AVLDCHGIF_Msk (0x1ul << OTG_INTSTS_AVLDCHGIF_Pos) /*!< OTG_T::INTSTS: AVLDCHGIF Mask */ + +#define OTG_INTSTS_VBCHGIF_Pos (10) /*!< OTG_T::INTSTS: VBCHGIF Position */ +#define OTG_INTSTS_VBCHGIF_Msk (0x1ul << OTG_INTSTS_VBCHGIF_Pos) /*!< OTG_T::INTSTS: VBCHGIF Mask */ + +#define OTG_INTSTS_SECHGIF_Pos (11) /*!< OTG_T::INTSTS: SECHGIF Position */ +#define OTG_INTSTS_SECHGIF_Msk (0x1ul << OTG_INTSTS_SECHGIF_Pos) /*!< OTG_T::INTSTS: SECHGIF Mask */ + +#define OTG_INTSTS_SRPDETIF_Pos (13) /*!< OTG_T::INTSTS: SRPDETIF Position */ +#define OTG_INTSTS_SRPDETIF_Msk (0x1ul << OTG_INTSTS_SRPDETIF_Pos) /*!< OTG_T::INTSTS: SRPDETIF Mask */ + +#define OTG_STATUS_OVERCUR_Pos (0) /*!< OTG_T::STATUS: OVERCUR Position */ +#define OTG_STATUS_OVERCUR_Msk (0x1ul << OTG_STATUS_OVERCUR_Pos) /*!< OTG_T::STATUS: OVERCUR Mask */ + +#define OTG_STATUS_IDSTS_Pos (1) /*!< OTG_T::STATUS: IDSTS Position */ +#define OTG_STATUS_IDSTS_Msk (0x1ul << OTG_STATUS_IDSTS_Pos) /*!< OTG_T::STATUS: IDSTS Mask */ + +#define OTG_STATUS_SESSEND_Pos (2) /*!< OTG_T::STATUS: SESSEND Position */ +#define OTG_STATUS_SESSEND_Msk (0x1ul << OTG_STATUS_SESSEND_Pos) /*!< OTG_T::STATUS: SESSEND Mask */ + +#define OTG_STATUS_BVLD_Pos (3) /*!< OTG_T::STATUS: BVLD Position */ +#define OTG_STATUS_BVLD_Msk (0x1ul << OTG_STATUS_BVLD_Pos) /*!< OTG_T::STATUS: BVLD Mask */ + +#define OTG_STATUS_AVLD_Pos (4) /*!< OTG_T::STATUS: AVLD Position */ +#define OTG_STATUS_AVLD_Msk (0x1ul << OTG_STATUS_AVLD_Pos) /*!< OTG_T::STATUS: AVLD Mask */ + +#define OTG_STATUS_VBUSVLD_Pos (5) /*!< OTG_T::STATUS: VBUSVLD Position */ +#define OTG_STATUS_VBUSVLD_Msk (0x1ul << OTG_STATUS_VBUSVLD_Pos) /*!< OTG_T::STATUS: VBUSVLD Mask */ + +#define OTG_STATUS_ASPERI_Pos (6) /*!< OTG_T::STATUS: ASPERI Position */ +#define OTG_STATUS_ASPERI_Msk (0x1ul << OTG_STATUS_ASPERI_Pos) /*!< OTG_T::STATUS: ASPERI Mask */ + +#define OTG_STATUS_ASHOST_Pos (7) /*!< OTG_T::STATUS: ASHOST Position */ +#define OTG_STATUS_ASHOST_Msk (0x1ul << OTG_STATUS_ASHOST_Pos) /*!< OTG_T::STATUS: ASHOST Mask */ + +/**@}*/ /* OTG_CONST */ +/**@}*/ /* end of OTG register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __OTG_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/pdma_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/pdma_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..a849d6bdcf5b0122e4891aec280d1f1031e12ed8 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/pdma_reg.h @@ -0,0 +1,886 @@ +/**************************************************************************//** + * @file pdma_reg.h + * @version V1.00 + * @brief PDMA register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __PDMA_REG_H__ +#define __PDMA_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup PDMA Peripheral Direct Memory Access Controller(PDMA) + Memory Mapped Structure for PDMA Controller +@{ */ + + +typedef struct +{ + + /** + * @var DSCT_T::CTL + * Offset: 0x00 Descriptor Table Control Register of PDMA Channel n. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |OPMODE |PDMA Operation Mode Selection + * | | |00 = Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically. + * | | |01 = Basic mode: The descriptor table only has one task + * | | |When this task is finished, the PDMA_INTSTS[n] will be asserted. + * | | |10 = Scatter-Gather mode: When operating in this mode, user must give the next descriptor table address in PDMA_DSCT_NEXT register; PDMA controller will ignore this task, then load the next task to execute. + * | | |11 = Reserved. + * | | |Note: Before filling transfer task in the Descriptor Table, user must check if the descriptor table is complete. + * |[2] |TXTYPE |Transfer Type + * | | |0 = Burst transfer type. + * | | |1 = Single transfer type. + * |[6:4] |BURSIZE |Burst Size + * | | |This field is used for peripheral to determine the burst size or used for determine the re-arbitration size. + * | | |000 = 128 Transfers. + * | | |001 = 64 Transfers. + * | | |010 = 32 Transfers. + * | | |011 = 16 Transfers. + * | | |100 = 8 Transfers. + * | | |101 = 4 Transfers. + * | | |110 = 2 Transfers. + * | | |111 = 1 Transfers. + * | | |Note: This field is only useful in burst transfer type. + * |[7] |TBINTDIS |Table Interrupt Disable Bit + * | | |This field can be used to decide whether to enable table interrupt or not + * | | |If the TBINTDIS bit is enabled when PDMA controller finishes transfer task, it will not generates transfer done interrupt. + * | | |0 = Table interrupt Enabled. + * | | |1 = Table interrupt Disabled. + * |[9:8] |SAINC |Source Address Increment + * | | |This field is used to set the source address increment size. + * | | |11 = No increment (fixed address). + * | | |Others = Increment and size is depended on TXWIDTH selection. + * |[11:10] |DAINC |Destination Address Increment + * | | |This field is used to set the destination address increment size. + * | | |11 = No increment (fixed address). + * | | |Others = Increment and size is depended on TXWIDTH selection. + * |[13:12] |TXWIDTH |Transfer Width Selection + * | | |This field is used for transfer width. + * | | |00 = One byte (8 bit) is transferred for every operation. + * | | |01= One half-word (16 bit) is transferred for every operation. + * | | |10 = One word (32-bit) is transferred for every operation. + * | | |11 = Reserved. + * | | |Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection + * |[14] |TXACK |Transfer Acknowledge Selection + * | | |0 = transfer ack when transfer done. + * | | |1 = transfer ack when PDMA get transfer data. + * |[15] |STRIDEEN |Stride Mode Enable Bit + * | | |0 = Stride transfer mode Disabled. + * | | |1 = Stride transfer mode Enabled. + * |[31:16] |TXCNT |Transfer Count + * | | |The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 , every transfer may be byte, half-word or word that is dependent on TXWIDTH field. + * | | |Note: When PDMA finish each transfer data, this field will be decrease immediately. + * @var DSCT_T::SA + * Offset: 0x04 Source Address Register of PDMA Channel n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SA |PDMA Transfer Source Address Register + * | | |This field indicates a 32-bit source address of PDMA controller. + * @var DSCT_T::DA + * Offset: 0x08 Destination Address Register of PDMA Channel n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DA |PDMA Transfer Destination Address Register + * | | |This field indicates a 32-bit destination address of PDMA controller. + * @var DSCT_T::NEXT + * Offset: 0x0C Next Scatter-Gather Descriptor Table Offset Address of PDMA Channel n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |EXENEXT |PDMA Execution Next Descriptor Table Offset + * | | |This field indicates the offset of next descriptor table address of current execution descriptor table in system memory. + * | | |Note: write operation is useless in this field. + * |[31:16] |NEXT |PDMA Next Descriptor Table Offset. + * | | |This field indicates the offset of the next descriptor table address in system memory. + * | | |Write Operation: + * | | |If the system memory based address is 0x2000_0000 (PDMA_SCATBA), and the next descriptor table is start from 0x2000_0100, then this field must fill in 0x0100. + * | | |Read Operation: + * | | |When operating in scatter-gather mode, the last two bits NEXT[1:0] will become reserved, and indicate the first next address of system memory. + * | | |Note1: The descriptor table address must be word boundary. + * | | |Note2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete. + */ + __IO uint32_t CTL; /*!< [0x0000] Descriptor Table Control Register of PDMA Channel n. */ + __IO uint32_t SA; /*!< [0x0004] Source Address Register of PDMA Channel n */ + __IO uint32_t DA; /*!< [0x0008] Destination Address Register of PDMA Channel n */ + __IO uint32_t NEXT; /*!< [0x000c] First Scatter-Gather Descriptor Table Offset Address of PDMA Channel n */ +} DSCT_T; + + +typedef struct +{ + /** + * @var STRIDE_T::STCR + * Offset: 0x500 Stride Transfer Count Register of PDMA Channel n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |STC |PDMA Stride Transfer Count + * | | |The 16-bit register defines the stride transfer count of each row. + * @var STRIDE_T::ASOCR + * Offset: 0x504 Address Stride Offset Register of PDMA Channel n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |SASOL |VDMA Source Address Stride Offset Length + * | | |The 16-bit register defines the source address stride transfer offset count of each row. + * |[31:16] |DASOL |VDMA Destination Address Stride Offset Length + * | | |The 16-bit register defines the destination address stride transfer offset count of each row. + */ + __IO uint32_t STCR; /*!< [0x0500] Stride Transfer Count Register of PDMA Channel 0 */ + __IO uint32_t ASOCR; /*!< [0x0504] Address Stride Offset Register of PDMA Channel 0 */ +} STRIDE_T; + +typedef struct +{ + /** + * @var REPEAT_T::AICTL + * Offset: 0x600 Address Interval Control Register of PDMA Channel n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |SAICNT |PDMA Source Address Interval Count + * | | |The 16-bit register defines the source address interval count of each row. + * |[31:16] |DAICNT |PDMA Destination Address Interval Count + * | | |The 16-bit register defines the destination address interval count of each row. + * @var REPEAT_T::RCNT + * Offset: 0x604 Repeat Count Register of PDMA Channe n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RCNT |PDMA Repeat Count + * | | |The 16-bit register defines the repeat times of block transfer. + */ + __IO uint32_t AICTL; /*!< [0x0600] Address Interval Control Register of PDMA Channel 0 */ + __IO uint32_t RCNT; /*!< [0x0604] Repeat Count Register of PDMA Channel 0 */ +} REPEAT_T; + +typedef struct +{ + + + /** + * @var PDMA_T::CURSCAT + * Offset: 0x100 Current Scatter-Gather Descriptor Table Address of PDMA Channel n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURADDR |PDMA Current Description Address Register (Read Only) + * | | |This field indicates a 32-bit current external description address of PDMA controller. + * | | |Note: This field is read only and only used for Scatter-Gather mode to indicate the current external description address. + * @var PDMA_T::CHCTL + * Offset: 0x400 PDMA Channel Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CHENn |PDMA Channel Enable Bit + * | | |Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled. + * | | |0 = PDMA channel [n] Disabled. + * | | |1 = PDMA channel [n] Enabled. + * | | |Note: Set corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit. + * @var PDMA_T::PAUSE + * Offset: 0x404 PDMA Transfer Stop Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PAUSEn |PDMA Transfer Pause Control Register (Write Only) + * | | |User can set PAUSEn bit field to pause the PDMA transfer + * | | |When user sets PAUSEn bit, the PDMA controller will pause the on-going transfer, then clear the channel enable bit CHEN(PDMA_CHCTL [n], n=0,1..7) and clear request active flag + * | | |If re-enable the paused channel again, the remaining transfers will be processed. + * | | |0 = No effect. + * | | |1 = Pause PDMA channel n transfer. + * @var PDMA_T::SWREQ + * Offset: 0x408 PDMA Software Request Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |SWREQn |PDMA Software Request Register (Write Only) + * | | |Set this bit to 1 to generate a software request to PDMA [n]. + * | | |0 = No effect. + * | | |1 = Generate a software request. + * | | |Note1: User can read PDMA_TRGSTS register to know which channel is on active + * | | |Active flag may be triggered by software request or peripheral request. + * | | |Note2: If user does not enable corresponding PDMA channel, the software request will be ignored. + * @var PDMA_T::TRGSTS + * Offset: 0x40C PDMA Channel Request Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |REQSTSn |PDMA Channel Request Status (Read Only) + * | | |This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral + * | | |When PDMA controller finishes channel transfer, this bit will be cleared automatically. + * | | |0 = PDMA Channel n has no request. + * | | |1 = PDMA Channel n has a request. + * | | |Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer. + * @var PDMA_T::PRISET + * Offset: 0x410 PDMA Fixed Priority Setting Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FPRISETn |PDMA Fixed Priority Setting Register + * | | |Set this bit to 1 to enable fixed priority level. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set PDMA channel [n] to fixed priority channel. + * | | |Read Operation: + * | | |0 = Corresponding PDMA channel is round-robin priority. + * | | |1 = Corresponding PDMA channel is fixed priority. + * | | |Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register. + * @var PDMA_T::PRICLR + * Offset: 0x414 PDMA Fixed Priority Clear Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FPRICLRn |PDMA Fixed Priority Clear Register (Write Only) + * | | |Set this bit to 1 to clear fixed priority level. + * | | |0 = No effect. + * | | |1 = Clear PDMA channel [n] fixed priority setting. + * | | |Note: User can read PDMA_PRISET register to know the channel priority. + * @var PDMA_T::INTEN + * Offset: 0x418 PDMA Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |INTENn |PDMA Interrupt Enable Register + * | | |This field is used for enabling PDMA channel[n] interrupt. + * | | |0 = PDMA channel n interrupt Disabled. + * | | |1 = PDMA channel n interrupt Enabled. + * @var PDMA_T::INTSTS + * Offset: 0x41C PDMA Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ABTIF |PDMA Read/Write Target Abort Interrupt Flag (Read-only) + * | | |This bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error. + * | | |0 = No AHB bus ERROR response received. + * | | |1 = AHB bus ERROR response received. + * |[1] |TDIF |Transfer Done Interrupt Flag (Read Only) + * | | |This bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer. + * | | |0 = Not finished yet. + * | | |1 = PDMA channel has finished transmission. + * |[2] |ALIGNF |Transfer Alignment Interrupt Flag (Read Only) + * | | |0 = PDMA channel source address and destination address both follow transfer width setting. + * | | |1 = PDMA channel source address or destination address is not follow transfer width setting. + * |[8] |REQTOF0 |Request Time-out Flag for Channel 0 + * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0, user can write 1 to clear these bits. + * | | |0 = No request time-out. + * | | |1 = Peripheral request time-out. + * |[9] |REQTOF1 |Request Time-out Flag for Channel 1 + * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC1, user can write 1 to clear these bits. + * | | |0 = No request time-out. + * | | |1 = Peripheral request time-out. + * @var PDMA_T::ABTSTS + * Offset: 0x420 PDMA Channel Read/Write Target Abort Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |ABTIFn |PDMA Read/Write Target Abort Interrupt Status Flag + * | | |This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits. + * | | |0 = No AHB bus ERROR response received when channel n transfer. + * | | |1 = AHB bus ERROR response received when channel n transfer. + * @var PDMA_T::TDSTS + * Offset: 0x424 PDMA Channel Transfer Done Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TDIFn |Transfer Done Flag Register + * | | |This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. + * | | |0 = PDMA channel transfer has not finished. + * | | |1 = PDMA channel has finished transmission. + * @var PDMA_T::ALIGN + * Offset: 0x428 PDMA Transfer Alignment Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |ALIGNn |Transfer Alignment Flag Register + * | | |0 = PDMA channel source address and destination address both follow transfer width setting. + * | | |1 = PDMA channel source address or destination address is not follow transfer width setting. + * @var PDMA_T::TACTSTS + * Offset: 0x42C PDMA Transfer Active Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TXACTFn |Transfer on Active Flag Register (Read Only) + * | | |This bit indicates which PDMA channel is in active. + * | | |0 = PDMA channel is not finished. + * | | |1 = PDMA channel is active. + * @var PDMA_T::TOUTPSC + * Offset: 0x430 PDMA Time-out Prescaler Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |TOUTPSC0 |PDMA Channel 0 Time-out Clock Source Prescaler Bits + * | | |000 = PDMA channel 0 time-out clock source is HCLK/28. + * | | |001 = PDMA channel 0 time-out clock source is HCLK/29. + * | | |010 = PDMA channel 0 time-out clock source is HCLK/210. + * | | |011 = PDMA channel 0 time-out clock source is HCLK/211. + * | | |100 = PDMA channel 0 time-out clock source is HCLK/212. + * | | |101 = PDMA channel 0 time-out clock source is HCLK/213. + * | | |110 = PDMA channel 0 time-out clock source is HCLK/214. + * | | |111 = PDMA channel 0 time-out clock source is HCLK/215. + * |[6:4] |TOUTPSC1 |PDMA Channel 1 Time-out Clock Source Prescaler Bits + * | | |000 = PDMA channel 1 time-out clock source is HCLK/28. + * | | |001 = PDMA channel 1 time-out clock source is HCLK/29. + * | | |010 = PDMA channel 1 time-out clock source is HCLK/210. + * | | |011 = PDMA channel 1 time-out clock source is HCLK/211. + * | | |100 = PDMA channel 1 time-out clock source is HCLK/212. + * | | |101 = PDMA channel 1 time-out clock source is HCLK/213. + * | | |110 = PDMA channel 1 time-out clock source is HCLK/214. + * | | |111 = PDMA channel 1 time-out clock source is HCLK/215. + * @var PDMA_T::TOUTEN + * Offset: 0x434 PDMA Time-out Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |TOUTENn |PDMA Time-out Enable Bits + * | | |0 = PDMA Channel n time-out function Disable. + * | | |1 = PDMA Channel n time-out function Enable. + * @var PDMA_T::TOUTIEN + * Offset: 0x438 PDMA Time-out Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |TOUTIENn |PDMA Time-out Interrupt Enable Bits + * | | |0 = PDMA Channel n time-out interrupt Disable. + * | | |1 = PDMA Channel n time-out interrupt Enable. + * @var PDMA_T::SCATBA + * Offset: 0x43C PDMA Scatter-Gather Descriptor Table Base Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:16] |SCATBA |PDMA Scatter-gather Descriptor Table Address Register + * | | |In Scatter-Gather mode, this is the base address for calculating the next link - list address + * | | |The next link address equation is + * | | |Next Link Address = PDMA_SCATBA + PDMA_DSCT_NEXT. + * | | |Note: Only useful in Scatter-Gather mode. + * @var PDMA_T::TOC0_1 + * Offset: 0x440 PDMA Time-out Counter Ch1 and Ch0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TOC0 |Time-out Counter for Channel 0 + * | | |This controls the period of time-out function for channel 0 + * | | |The calculation unit is based on 10 kHz clock. + * |[31:16] |TOC1 |Time-out Counter for Channel 1 + * | | |This controls the period of time-out function for channel 1 + * | | |The calculation unit is based on 10 kHz clock. + * @var PDMA_T::CHRST + * Offset: 0x460 PDMA Channel Reset Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CHnRST |Channel N Reset + * | | |0 = corresponding channel n not reset. + * | | |1 = corresponding channel n is reset. + * @var PDMA_T::REQSEL0_3 + * Offset: 0x480 PDMA Request Source Select Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |REQSRC0 |Channel 0 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 0 + * | | |User can configure the peripheral by setting REQSRC0. + * | | |0 = Disable PDMA peripheral request. + * | | |1 = Reserved. + * | | |2 = Channel connects to USB_TX. + * | | |3 = Channel connects to USB_RX. + * | | |4 = Channel connects to UART0_TX. + * | | |5 = Channel connects to UART0_RX. + * | | |6 = Channel connects to UART1_TX. + * | | |7 = Channel connects to UART1_RX. + * | | |8 = Channel connects to UART2_TX. + * | | |9 = Channel connects to UART2_RX. + * | | |10=Channel connects to UART3_TX. + * | | |11 = Channel connects to UART3_RX. + * | | |12 = Channel connects to UART4_TX. + * | | |13 = Channel connects to UART4_RX. + * | | |14 = Channel connects to UART5_TX. + * | | |15 = Channel connects to UART5_RX. + * | | |16 = Channel connects to USCI0_TX. + * | | |17 = Channel connects to USCI0_RX. + * | | |18 = Channel connects to USCI1_TX. + * | | |19 = Channel connects to USCI1_RX. + * | | |20 = Channel connects to QSPI0_TX. + * | | |21 = Channel connects to QSPI0_RX. + * | | |22 = Channel connects to SPI0_TX. + * | | |23 = Channel connects to SPI0_RX. + * | | |24 = Channel connects to SPI1_TX. + * | | |25 = Channel connects to SPI1_RX. + * | | |26 = Channel connects to SPI2_TX. + * | | |27 = Channel connects to SPI2_RX. + * | | |28 = Channel connects to SPI3_TX. + * | | |29 = Channel connects to SPI3_RX. + * | | |30 = Reserved. + * | | |31 = Reserved. + * | | |32 = Channel connects to EPWM0_P1_RX. + * | | |33 = Channel connects to EPWM0_P2_RX. + * | | |34 = Channel connects to EPWM0_P3_RX. + * | | |35 = Channel connects to EPWM1_P1_RX. + * | | |36 = Channel connects to EPWM1_P2_RX. + * | | |37 = Channel connects to EPWM1_P3_RX. + * | | |38 = Channel connects to I2C0_TX. + * | | |39 = Channel connects to I2C0_RX. + * | | |40 = Channel connects to I2C1_TX. + * | | |41 = Channel connects to I2C1_RX. + * | | |42 = Channel connects to I2C2_TX. + * | | |43 = Channel connects to I2C2_RX. + * | | |44 = Channel connects to I2S0_TX. + * | | |45 = Channel connects to I2S0_RX. + * | | |46 = Channel connects to TMR0. + * | | |47 = Channel connects to TMR1. + * | | |48 = Channel connects to TMR2. + * | | |49 = Channel connects to TMR3. + * | | |50 = Channel connects to ADC_RX. + * | | |51 = Channel connects to DAC0_TX. + * | | |52 = Channel connects to DAC1_TX. + * | | |53 = Channel connects to EPWM0_CH0_TX. + * | | |54 = Channel connects to EPWM0_CH1_TX. + * | | |55 = Channel connects to EPWM0_CH2_TX. + * | | |56 = Channel connects to EPWM0_CH3_TX. + * | | |57 = Channel connects to EPWM0_CH4_TX. + * | | |58 = Channel connects to EPWM0_CH5_TX. + * | | |59 = Channel connects to EPWM1_CH0_TX. + * | | |60 = Channel connects to EPWM1_CH1_TX. + * | | |61 = Channel connects to EPWM1_CH2_TX. + * | | |62 = Channel connects to EPWM1_CH3_TX. + * | | |63 = Channel connects to EPWM1_CH4_TX. + * | | |64 = Channel connects to EPWM1_CH5_TX. + * | | |65 = Channel connects to ETMC_RX. + * | | |Others = Reserved. + * | | |Note 1: A peripheral can't assign to two channels at the same time. + * | | |Note 2: This field is useless when transfer between memory and memory. + * |[14:8] |REQSRC1 |Channel 1 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 1 + * | | |User can configure the peripheral setting by REQSRC1. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[22:16] |REQSRC2 |Channel 2 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 2 + * | | |User can configure the peripheral setting by REQSRC2. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[30:24] |REQSRC3 |Channel 3 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 3 + * | | |User can configure the peripheral setting by REQSRC3. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * @var PDMA_T::REQSEL4_7 + * Offset: 0x484 PDMA Request Source Select Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |REQSRC4 |Channel 4 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 4 + * | | |User can configure the peripheral setting by REQSRC4. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[14:8] |REQSRC5 |Channel 5 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 5 + * | | |User can configure the peripheral setting by REQSRC5. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[22:16] |REQSRC6 |Channel 6 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 6 + * | | |User can configure the peripheral setting by REQSRC6. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[30:24] |REQSRC7 |Channel 7 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 7 + * | | |User can configure the peripheral setting by REQSRC7. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * @var PDMA_T::REQSEL8_11 + * Offset: 0x488 PDMA Request Source Select Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |REQSRC8 |Channel 8 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 8 + * | | |User can configure the peripheral setting by REQSRC8. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[14:8] |REQSRC9 |Channel 9 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 9 + * | | |User can configure the peripheral setting by REQSRC9. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[22:16] |REQSRC10 |Channel 10 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 10 + * | | |User can configure the peripheral setting by REQSRC10. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[30:24] |REQSRC11 |Channel 11 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 11 + * | | |User can configure the peripheral setting by REQSRC11. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * @var PDMA_T::REQSEL12_15 + * Offset: 0x48C PDMA Request Source Select Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |REQSRC12 |Channel 12 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 12 + * | | |User can configure the peripheral setting by REQSRC12. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[14:8] |REQSRC13 |Channel 13 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 13 + * | | |User can configure the peripheral setting by REQSRC13. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[22:16] |REQSRC14 |Channel 14 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 14 + * | | |User can configure the peripheral setting by REQSRC14. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[30:24] |REQSRC15 |Channel 15 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 15 + * | | |User can configure the peripheral setting by REQSRC15. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + */ + DSCT_T DSCT[16]; + __I uint32_t CURSCAT[16]; /*!< [0x0100] Current Scatter-Gather Descriptor Table Address of PDMA Channel n */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[176]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CHCTL; /*!< [0x0400] PDMA Channel Control Register */ + __O uint32_t PAUSE; /*!< [0x0404] PDMA Transfer Pause Control Register */ + __O uint32_t SWREQ; /*!< [0x0408] PDMA Software Request Register */ + __I uint32_t TRGSTS; /*!< [0x040c] PDMA Channel Request Status Register */ + __IO uint32_t PRISET; /*!< [0x0410] PDMA Fixed Priority Setting Register */ + __O uint32_t PRICLR; /*!< [0x0414] PDMA Fixed Priority Clear Register */ + __IO uint32_t INTEN; /*!< [0x0418] PDMA Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x041c] PDMA Interrupt Status Register */ + __IO uint32_t ABTSTS; /*!< [0x0420] PDMA Channel Read/Write Target Abort Flag Register */ + __IO uint32_t TDSTS; /*!< [0x0424] PDMA Channel Transfer Done Flag Register */ + __IO uint32_t ALIGN; /*!< [0x0428] PDMA Transfer Alignment Status Register */ + __I uint32_t TACTSTS; /*!< [0x042c] PDMA Transfer Active Flag Register */ + __IO uint32_t TOUTPSC; /*!< [0x0430] PDMA Time-out Prescaler Register */ + __IO uint32_t TOUTEN; /*!< [0x0434] PDMA Time-out Enable Register */ + __IO uint32_t TOUTIEN; /*!< [0x0438] PDMA Time-out Interrupt Enable Register */ + __IO uint32_t SCATBA; /*!< [0x043c] PDMA Scatter-Gather Descriptor Table Base Address Register */ + __IO uint32_t TOC0_1; /*!< [0x0440] PDMA Time-out Counter Ch1 and Ch0 Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[7]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CHRST; /*!< [0x0460] PDMA Channel Reset Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[7]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t REQSEL0_3; /*!< [0x0480] PDMA Request Source Select Register 0 */ + __IO uint32_t REQSEL4_7; /*!< [0x0484] PDMA Request Source Select Register 1 */ + __IO uint32_t REQSEL8_11; /*!< [0x0488] PDMA Request Source Select Register 2 */ + __IO uint32_t REQSEL12_15; /*!< [0x048c] PDMA Request Source Select Register 3 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE4[28]; + /// @endcond //HIDDEN_SYMBOLS + STRIDE_T STRIDE[6]; + /// @cond HIDDEN_SYMBOLS + __IO uint32_t RESERVE5[52]; + /// @endcond //HIDDEN_SYMBOLS + REPEAT_T REPEAT[2]; +} PDMA_T; + +/** + @addtogroup PDMA_CONST PDMA Bit Field Definition + Constant Definitions for PDMA Controller +@{ */ + +#define PDMA_DSCT_CTL_OPMODE_Pos (0) /*!< PDMA_T::DSCT_CTL: OPMODE Position */ +#define PDMA_DSCT_CTL_OPMODE_Msk (0x3ul << PDMA_DSCT_CTL_OPMODE_Pos) /*!< PDMA_T::DSCT_CTL: OPMODE Mask */ + +#define PDMA_DSCT_CTL_TXTYPE_Pos (2) /*!< PDMA_T::DSCT_CTL: TXTYPE Position */ +#define PDMA_DSCT_CTL_TXTYPE_Msk (0x1ul << PDMA_DSCT_CTL_TXTYPE_Pos) /*!< PDMA_T::DSCT_CTL: TXTYPE Mask */ + +#define PDMA_DSCT_CTL_BURSIZE_Pos (4) /*!< PDMA_T::DSCT_CTL: BURSIZE Position */ +#define PDMA_DSCT_CTL_BURSIZE_Msk (0x7ul << PDMA_DSCT_CTL_BURSIZE_Pos) /*!< PDMA_T::DSCT_CTL: BURSIZE Mask */ + +#define PDMA_DSCT_CTL_TBINTDIS_Pos (7) /*!< PDMA_T::DSCT_CTL: TBINTDIS Position */ +#define PDMA_DSCT_CTL_TBINTDIS_Msk (0x1ul << PDMA_DSCT_CTL_TBINTDIS_Pos) /*!< PDMA_T::DSCT_CTL: TBINTDIS Mask */ + +#define PDMA_DSCT_CTL_SAINC_Pos (8) /*!< PDMA_T::DSCT_CTL: SAINC Position */ +#define PDMA_DSCT_CTL_SAINC_Msk (0x3ul << PDMA_DSCT_CTL_SAINC_Pos) /*!< PDMA_T::DSCT_CTL: SAINC Mask */ + +#define PDMA_DSCT_CTL_DAINC_Pos (10) /*!< PDMA_T::DSCT_CTL: DAINC Position */ +#define PDMA_DSCT_CTL_DAINC_Msk (0x3ul << PDMA_DSCT_CTL_DAINC_Pos) /*!< PDMA_T::DSCT_CTL: DAINC Mask */ + +#define PDMA_DSCT_CTL_TXWIDTH_Pos (12) /*!< PDMA_T::DSCT_CTL: TXWIDTH Position */ +#define PDMA_DSCT_CTL_TXWIDTH_Msk (0x3ul << PDMA_DSCT_CTL_TXWIDTH_Pos) /*!< PDMA_T::DSCT_CTL: TXWIDTH Mask */ + +#define PDMA_DSCT_CTL_TXACK_Pos (14) /*!< PDMA_T::DSCT_CTL: TXACK Position */ +#define PDMA_DSCT_CTL_TXACK_Msk (0x1ul << PDMA_DSCT_CTL_TXACK_Pos) /*!< PDMA_T::DSCT_CTL: TXACK Mask */ + +#define PDMA_DSCT_CTL_STRIDEEN_Pos (15) /*!< PDMA_T::DSCT_CTL: STRIDEEN Position */ +#define PDMA_DSCT_CTL_STRIDEEN_Msk (0x1ul << PDMA_DSCT_CTL_STRIDEEN_Pos) /*!< PDMA_T::DSCT_CTL: STRIDEEN Mask */ + +#define PDMA_DSCT_CTL_TXCNT_Pos (16) /*!< PDMA_T::DSCT_CTL: TXCNT Position */ +#define PDMA_DSCT_CTL_TXCNT_Msk (0xfffful << PDMA_DSCT_CTL_TXCNT_Pos) /*!< PDMA_T::DSCT_CTL: TXCNT Mask */ + +#define PDMA_DSCT_SA_SA_Pos (0) /*!< PDMA_T::DSCT_SA: SA Position */ +#define PDMA_DSCT_SA_SA_Msk (0xfffffffful << PDMA_DSCT_SA_SA_Pos) /*!< PDMA_T::DSCT_SA: SA Mask */ + +#define PDMA_DSCT_DA_DA_Pos (0) /*!< PDMA_T::DSCT_DA: DA Position */ +#define PDMA_DSCT_DA_DA_Msk (0xfffffffful << PDMA_DSCT_DA_DA_Pos) /*!< PDMA_T::DSCT_DA: DA Mask */ + +#define PDMA_DSCT_NEXT_NEXT_Pos (0) /*!< PDMA_T::DSCT_NEXT: NEXT Position */ +#define PDMA_DSCT_NEXT_NEXT_Msk (0xfffful << PDMA_DSCT_NEXT_NEXT_Pos) /*!< PDMA_T::DSCT_NEXT: NEXT Mask */ + +#define PDMA_DSCT_NEXT_EXENEXT_Pos (16) /*!< PDMA_T::DSCT_FIRST: NEXT Position */ +#define PDMA_DSCT_NEXT_EXENEXT_Msk (0xfffful << PDMA_DSCT_NEXT_EXENEXT_Pos) /*!< PDMA_T::DSCT_FIRST: NEXT Mask */ + +#define PDMA_CURSCAT_CURADDR_Pos (0) /*!< PDMA_T::CURSCAT: CURADDR Position */ +#define PDMA_CURSCAT_CURADDR_Msk (0xfffffffful << PDMA_CURSCAT_CURADDR_Pos) /*!< PDMA_T::CURSCAT: CURADDR Mask */ + +#define PDMA_CHCTL_CHENn_Pos (0) /*!< PDMA_T::CHCTL: CHENn Position */ +#define PDMA_CHCTL_CHENn_Msk (0xfffful << PDMA_CHCTL_CHENn_Pos) /*!< PDMA_T::CHCTL: CHENn Mask */ + +#define PDMA_PAUSE_PAUSEn_Pos (0) /*!< PDMA_T::PAUSE: PAUSEn Position */ +#define PDMA_PAUSE_PAUSEn_Msk (0xfffful << PDMA_PAUSE_PAUSEn_Pos) /*!< PDMA_T::PAUSE: PAUSEn Mask */ + +#define PDMA_SWREQ_SWREQn_Pos (0) /*!< PDMA_T::SWREQ: SWREQn Position */ +#define PDMA_SWREQ_SWREQn_Msk (0xfffful << PDMA_SWREQ_SWREQn_Pos) /*!< PDMA_T::SWREQ: SWREQn Mask */ + +#define PDMA_TRGSTS_REQSTSn_Pos (0) /*!< PDMA_T::TRGSTS: REQSTSn Position */ +#define PDMA_TRGSTS_REQSTSn_Msk (0xfffful << PDMA_TRGSTS_REQSTSn_Pos) /*!< PDMA_T::TRGSTS: REQSTSn Mask */ + +#define PDMA_PRISET_FPRISETn_Pos (0) /*!< PDMA_T::PRISET: FPRISETn Position */ +#define PDMA_PRISET_FPRISETn_Msk (0xfffful << PDMA_PRISET_FPRISETn_Pos) /*!< PDMA_T::PRISET: FPRISETn Mask */ + +#define PDMA_PRICLR_FPRICLRn_Pos (0) /*!< PDMA_T::PRICLR: FPRICLRn Position */ +#define PDMA_PRICLR_FPRICLRn_Msk (0xfffful << PDMA_PRICLR_FPRICLRn_Pos) /*!< PDMA_T::PRICLR: FPRICLRn Mask */ + +#define PDMA_INTEN_INTENn_Pos (0) /*!< PDMA_T::INTEN: INTENn Position */ +#define PDMA_INTEN_INTENn_Msk (0xfffful << PDMA_INTEN_INTENn_Pos) /*!< PDMA_T::INTEN: INTENn Mask */ + +#define PDMA_INTSTS_ABTIF_Pos (0) /*!< PDMA_T::INTSTS: ABTIF Position */ +#define PDMA_INTSTS_ABTIF_Msk (0x1ul << PDMA_INTSTS_ABTIF_Pos) /*!< PDMA_T::INTSTS: ABTIF Mask */ + +#define PDMA_INTSTS_TDIF_Pos (1) /*!< PDMA_T::INTSTS: TDIF Position */ +#define PDMA_INTSTS_TDIF_Msk (0x1ul << PDMA_INTSTS_TDIF_Pos) /*!< PDMA_T::INTSTS: TDIF Mask */ + +#define PDMA_INTSTS_ALIGNF_Pos (2) /*!< PDMA_T::INTSTS: ALIGNF Position */ +#define PDMA_INTSTS_ALIGNF_Msk (0x1ul << PDMA_INTSTS_ALIGNF_Pos) /*!< PDMA_T::INTSTS: ALIGNF Mask */ + +#define PDMA_INTSTS_REQTOF0_Pos (8) /*!< PDMA_T::INTSTS: REQTOF0 Position */ +#define PDMA_INTSTS_REQTOF0_Msk (0x1ul << PDMA_INTSTS_REQTOF0_Pos) /*!< PDMA_T::INTSTS: REQTOF0 Mask */ + +#define PDMA_INTSTS_REQTOF1_Pos (9) /*!< PDMA_T::INTSTS: REQTOF1 Position */ +#define PDMA_INTSTS_REQTOF1_Msk (0x1ul << PDMA_INTSTS_REQTOF1_Pos) /*!< PDMA_T::INTSTS: REQTOF1 Mask */ + +#define PDMA_ABTSTS_ABTIF0_Pos (0) /*!< PDMA_T::ABTSTS: ABTIF0 Position */ +#define PDMA_ABTSTS_ABTIF0_Msk (0x1ul << PDMA_ABTSTS_ABTIF0_Pos) /*!< PDMA_T::ABTSTS: ABTIF0 Mask */ + +#define PDMA_ABTSTS_ABTIF1_Pos (1) /*!< PDMA_T::ABTSTS: ABTIF1 Position */ +#define PDMA_ABTSTS_ABTIF1_Msk (0x1ul << PDMA_ABTSTS_ABTIF1_Pos) /*!< PDMA_T::ABTSTS: ABTIF1 Mask */ + +#define PDMA_ABTSTS_ABTIF2_Pos (2) /*!< PDMA_T::ABTSTS: ABTIF2 Position */ +#define PDMA_ABTSTS_ABTIF2_Msk (0x1ul << PDMA_ABTSTS_ABTIF2_Pos) /*!< PDMA_T::ABTSTS: ABTIF2 Mask */ + +#define PDMA_ABTSTS_ABTIF3_Pos (3) /*!< PDMA_T::ABTSTS: ABTIF3 Position */ +#define PDMA_ABTSTS_ABTIF3_Msk (0x1ul << PDMA_ABTSTS_ABTIF3_Pos) /*!< PDMA_T::ABTSTS: ABTIF3 Mask */ + +#define PDMA_ABTSTS_ABTIF4_Pos (4) /*!< PDMA_T::ABTSTS: ABTIF4 Position */ +#define PDMA_ABTSTS_ABTIF4_Msk (0x1ul << PDMA_ABTSTS_ABTIF4_Pos) /*!< PDMA_T::ABTSTS: ABTIF4 Mask */ + +#define PDMA_ABTSTS_ABTIF5_Pos (5) /*!< PDMA_T::ABTSTS: ABTIF5 Position */ +#define PDMA_ABTSTS_ABTIF5_Msk (0x1ul << PDMA_ABTSTS_ABTIF5_Pos) /*!< PDMA_T::ABTSTS: ABTIF5 Mask */ + +#define PDMA_ABTSTS_ABTIF6_Pos (6) /*!< PDMA_T::ABTSTS: ABTIF6 Position */ +#define PDMA_ABTSTS_ABTIF6_Msk (0x1ul << PDMA_ABTSTS_ABTIF6_Pos) /*!< PDMA_T::ABTSTS: ABTIF6 Mask */ + +#define PDMA_ABTSTS_ABTIF7_Pos (7) /*!< PDMA_T::ABTSTS: ABTIF7 Position */ +#define PDMA_ABTSTS_ABTIF7_Msk (0x1ul << PDMA_ABTSTS_ABTIF7_Pos) /*!< PDMA_T::ABTSTS: ABTIF7 Mask */ + +#define PDMA_ABTSTS_ABTIF8_Pos (8) /*!< PDMA_T::ABTSTS: ABTIF8 Position */ +#define PDMA_ABTSTS_ABTIF8_Msk (0x1ul << PDMA_ABTSTS_ABTIF8_Pos) /*!< PDMA_T::ABTSTS: ABTIF8 Mask */ + +#define PDMA_ABTSTS_ABTIF9_Pos (9) /*!< PDMA_T::ABTSTS: ABTIF9 Position */ +#define PDMA_ABTSTS_ABTIF9_Msk (0x1ul << PDMA_ABTSTS_ABTIF9_Pos) /*!< PDMA_T::ABTSTS: ABTIF9 Mask */ + +#define PDMA_ABTSTS_ABTIF10_Pos (10) /*!< PDMA_T::ABTSTS: ABTIF10 Position */ +#define PDMA_ABTSTS_ABTIF10_Msk (0x1ul << PDMA_ABTSTS_ABTIF10_Pos) /*!< PDMA_T::ABTSTS: ABTIF10 Mask */ + +#define PDMA_ABTSTS_ABTIF11_Pos (11) /*!< PDMA_T::ABTSTS: ABTIF11 Position */ +#define PDMA_ABTSTS_ABTIF11_Msk (0x1ul << PDMA_ABTSTS_ABTIF11_Pos) /*!< PDMA_T::ABTSTS: ABTIF11 Mask */ + +#define PDMA_ABTSTS_ABTIF12_Pos (12) /*!< PDMA_T::ABTSTS: ABTIF12 Position */ +#define PDMA_ABTSTS_ABTIF12_Msk (0x1ul << PDMA_ABTSTS_ABTIF12_Pos) /*!< PDMA_T::ABTSTS: ABTIF12 Mask */ + +#define PDMA_ABTSTS_ABTIF13_Pos (13) /*!< PDMA_T::ABTSTS: ABTIF13 Position */ +#define PDMA_ABTSTS_ABTIF13_Msk (0x1ul << PDMA_ABTSTS_ABTIF13_Pos) /*!< PDMA_T::ABTSTS: ABTIF13 Mask */ + +#define PDMA_ABTSTS_ABTIF14_Pos (14) /*!< PDMA_T::ABTSTS: ABTIF14 Position */ +#define PDMA_ABTSTS_ABTIF14_Msk (0x1ul << PDMA_ABTSTS_ABTIF14_Pos) /*!< PDMA_T::ABTSTS: ABTIF14 Mask */ + +#define PDMA_ABTSTS_ABTIF15_Pos (15) /*!< PDMA_T::ABTSTS: ABTIF15 Position */ +#define PDMA_ABTSTS_ABTIF15_Msk (0x1ul << PDMA_ABTSTS_ABTIF15_Pos) /*!< PDMA_T::ABTSTS: ABTIF15 Mask */ + +#define PDMA_TDSTS_TDIF0_Pos (0) /*!< PDMA_T::TDSTS: TDIF0 Position */ +#define PDMA_TDSTS_TDIF0_Msk (0x1ul << PDMA_TDSTS_TDIF0_Pos) /*!< PDMA_T::TDSTS: TDIF0 Mask */ + +#define PDMA_TDSTS_TDIF1_Pos (1) /*!< PDMA_T::TDSTS: TDIF1 Position */ +#define PDMA_TDSTS_TDIF1_Msk (0x1ul << PDMA_TDSTS_TDIF1_Pos) /*!< PDMA_T::TDSTS: TDIF1 Mask */ + +#define PDMA_TDSTS_TDIF2_Pos (2) /*!< PDMA_T::TDSTS: TDIF2 Position */ +#define PDMA_TDSTS_TDIF2_Msk (0x1ul << PDMA_TDSTS_TDIF2_Pos) /*!< PDMA_T::TDSTS: TDIF2 Mask */ + +#define PDMA_TDSTS_TDIF3_Pos (3) /*!< PDMA_T::TDSTS: TDIF3 Position */ +#define PDMA_TDSTS_TDIF3_Msk (0x1ul << PDMA_TDSTS_TDIF3_Pos) /*!< PDMA_T::TDSTS: TDIF3 Mask */ + +#define PDMA_TDSTS_TDIF4_Pos (4) /*!< PDMA_T::TDSTS: TDIF4 Position */ +#define PDMA_TDSTS_TDIF4_Msk (0x1ul << PDMA_TDSTS_TDIF4_Pos) /*!< PDMA_T::TDSTS: TDIF4 Mask */ + +#define PDMA_TDSTS_TDIF5_Pos (5) /*!< PDMA_T::TDSTS: TDIF5 Position */ +#define PDMA_TDSTS_TDIF5_Msk (0x1ul << PDMA_TDSTS_TDIF5_Pos) /*!< PDMA_T::TDSTS: TDIF5 Mask */ + +#define PDMA_TDSTS_TDIF6_Pos (6) /*!< PDMA_T::TDSTS: TDIF6 Position */ +#define PDMA_TDSTS_TDIF6_Msk (0x1ul << PDMA_TDSTS_TDIF6_Pos) /*!< PDMA_T::TDSTS: TDIF6 Mask */ + +#define PDMA_TDSTS_TDIF7_Pos (7) /*!< PDMA_T::TDSTS: TDIF7 Position */ +#define PDMA_TDSTS_TDIF7_Msk (0x1ul << PDMA_TDSTS_TDIF7_Pos) /*!< PDMA_T::TDSTS: TDIF7 Mask */ + +#define PDMA_TDSTS_TDIF8_Pos (8) /*!< PDMA_T::TDSTS: TDIF8 Position */ +#define PDMA_TDSTS_TDIF8_Msk (0x1ul << PDMA_TDSTS_TDIF8_Pos) /*!< PDMA_T::TDSTS: TDIF8 Mask */ + +#define PDMA_TDSTS_TDIF9_Pos (9) /*!< PDMA_T::TDSTS: TDIF9 Position */ +#define PDMA_TDSTS_TDIF9_Msk (0x1ul << PDMA_TDSTS_TDIF9_Pos) /*!< PDMA_T::TDSTS: TDIF9 Mask */ + +#define PDMA_TDSTS_TDIF10_Pos (10) /*!< PDMA_T::TDSTS: TDIF10 Position */ +#define PDMA_TDSTS_TDIF10_Msk (0x1ul << PDMA_TDSTS_TDIF10_Pos) /*!< PDMA_T::TDSTS: TDIF10 Mask */ + +#define PDMA_TDSTS_TDIF11_Pos (11) /*!< PDMA_T::TDSTS: TDIF11 Position */ +#define PDMA_TDSTS_TDIF11_Msk (0x1ul << PDMA_TDSTS_TDIF11_Pos) /*!< PDMA_T::TDSTS: TDIF11 Mask */ + +#define PDMA_TDSTS_TDIF12_Pos (12) /*!< PDMA_T::TDSTS: TDIF12 Position */ +#define PDMA_TDSTS_TDIF12_Msk (0x1ul << PDMA_TDSTS_TDIF12_Pos) /*!< PDMA_T::TDSTS: TDIF12 Mask */ + +#define PDMA_TDSTS_TDIF13_Pos (13) /*!< PDMA_T::TDSTS: TDIF13 Position */ +#define PDMA_TDSTS_TDIF13_Msk (0x1ul << PDMA_TDSTS_TDIF13_Pos) /*!< PDMA_T::TDSTS: TDIF13 Mask */ + +#define PDMA_TDSTS_TDIF14_Pos (14) /*!< PDMA_T::TDSTS: TDIF14 Position */ +#define PDMA_TDSTS_TDIF14_Msk (0x1ul << PDMA_TDSTS_TDIF14_Pos) /*!< PDMA_T::TDSTS: TDIF14 Mask */ + +#define PDMA_TDSTS_TDIF15_Pos (15) /*!< PDMA_T::TDSTS: TDIF15 Position */ +#define PDMA_TDSTS_TDIF15_Msk (0x1ul << PDMA_TDSTS_TDIF15_Pos) /*!< PDMA_T::TDSTS: TDIF15 Mask */ + +#define PDMA_ALIGN_ALIGNn_Pos (0) /*!< PDMA_T::ALIGN: ALIGNn Position */ +#define PDMA_ALIGN_ALIGNn_Msk (0xfffful << PDMA_ALIGN_ALIGNn_Pos) /*!< PDMA_T::ALIGN: ALIGNn Mask */ + +#define PDMA_TACTSTS_TXACTFn_Pos (0) /*!< PDMA_T::TACTSTS: TXACTFn Position */ +#define PDMA_TACTSTS_TXACTFn_Msk (0xfffful << PDMA_TACTSTS_TXACTFn_Pos) /*!< PDMA_T::TACTSTS: TXACTFn Mask */ + +#define PDMA_TOUTPSC_TOUTPSC0_Pos (0) /*!< PDMA_T::TOUTPSC: TOUTPSC0 Position */ +#define PDMA_TOUTPSC_TOUTPSC0_Msk (0x7ul << PDMA_TOUTPSC_TOUTPSC0_Pos) /*!< PDMA_T::TOUTPSC: TOUTPSC0 Mask */ + +#define PDMA_TOUTPSC_TOUTPSC1_Pos (4) /*!< PDMA_T::TOUTPSC: TOUTPSC1 Position */ +#define PDMA_TOUTPSC_TOUTPSC1_Msk (0x7ul << PDMA_TOUTPSC_TOUTPSC1_Pos) /*!< PDMA_T::TOUTPSC: TOUTPSC1 Mask */ + +#define PDMA_TOUTEN_TOUTENn_Pos (0) /*!< PDMA_T::TOUTEN: TOUTENn Position */ +#define PDMA_TOUTEN_TOUTENn_Msk (0x3ul << PDMA_TOUTEN_TOUTENn_Pos) /*!< PDMA_T::TOUTEN: TOUTENn Mask */ + +#define PDMA_TOUTIEN_TOUTIENn_Pos (0) /*!< PDMA_T::TOUTIEN: TOUTIENn Position */ +#define PDMA_TOUTIEN_TOUTIENn_Msk (0x3ul << PDMA_TOUTIEN_TOUTIENn_Pos) /*!< PDMA_T::TOUTIEN: TOUTIENn Mask */ + +#define PDMA_SCATBA_SCATBA_Pos (16) /*!< PDMA_T::SCATBA: SCATBA Position */ +#define PDMA_SCATBA_SCATBA_Msk (0xfffful << PDMA_SCATBA_SCATBA_Pos) /*!< PDMA_T::SCATBA: SCATBA Mask */ + +#define PDMA_TOC0_1_TOC0_Pos (0) /*!< PDMA_T::TOC0_1: TOC0 Position */ +#define PDMA_TOC0_1_TOC0_Msk (0xfffful << PDMA_TOC0_1_TOC0_Pos) /*!< PDMA_T::TOC0_1: TOC0 Mask */ + +#define PDMA_TOC0_1_TOC1_Pos (16) /*!< PDMA_T::TOC0_1: TOC1 Position */ +#define PDMA_TOC0_1_TOC1_Msk (0xfffful << PDMA_TOC0_1_TOC1_Pos) /*!< PDMA_T::TOC0_1: TOC1 Mask */ + +#define PDMA_CHRST_CHnRST_Pos (0) /*!< PDMA_T::CHRST: CHnRST Position */ +#define PDMA_CHRST_CHnRST_Msk (0xfffful << PDMA_CHRST_CHnRST_Pos) /*!< PDMA_T::CHRST: CHnRST Mask */ + +#define PDMA_REQSEL0_3_REQSRC0_Pos (0) /*!< PDMA_T::REQSEL0_3: REQSRC0 Position */ +#define PDMA_REQSEL0_3_REQSRC0_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC0_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC0 Mask */ + +#define PDMA_REQSEL0_3_REQSRC1_Pos (8) /*!< PDMA_T::REQSEL0_3: REQSRC1 Position */ +#define PDMA_REQSEL0_3_REQSRC1_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC1_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC1 Mask */ + +#define PDMA_REQSEL0_3_REQSRC2_Pos (16) /*!< PDMA_T::REQSEL0_3: REQSRC2 Position */ +#define PDMA_REQSEL0_3_REQSRC2_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC2_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC2 Mask */ + +#define PDMA_REQSEL0_3_REQSRC3_Pos (24) /*!< PDMA_T::REQSEL0_3: REQSRC3 Position */ +#define PDMA_REQSEL0_3_REQSRC3_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC3_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC3 Mask */ + +#define PDMA_REQSEL4_7_REQSRC4_Pos (0) /*!< PDMA_T::REQSEL4_7: REQSRC4 Position */ +#define PDMA_REQSEL4_7_REQSRC4_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC4_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC4 Mask */ + +#define PDMA_REQSEL4_7_REQSRC5_Pos (8) /*!< PDMA_T::REQSEL4_7: REQSRC5 Position */ +#define PDMA_REQSEL4_7_REQSRC5_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC5_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC5 Mask */ + +#define PDMA_REQSEL4_7_REQSRC6_Pos (16) /*!< PDMA_T::REQSEL4_7: REQSRC6 Position */ +#define PDMA_REQSEL4_7_REQSRC6_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC6_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC6 Mask */ + +#define PDMA_REQSEL4_7_REQSRC7_Pos (24) /*!< PDMA_T::REQSEL4_7: REQSRC7 Position */ +#define PDMA_REQSEL4_7_REQSRC7_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC7_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC7 Mask */ + +#define PDMA_REQSEL8_11_REQSRC8_Pos (0) /*!< PDMA_T::REQSEL8_11: REQSRC8 Position */ +#define PDMA_REQSEL8_11_REQSRC8_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC8_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC8 Mask */ + +#define PDMA_REQSEL8_11_REQSRC9_Pos (8) /*!< PDMA_T::REQSEL8_11: REQSRC9 Position */ +#define PDMA_REQSEL8_11_REQSRC9_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC9_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC9 Mask */ + +#define PDMA_REQSEL8_11_REQSRC10_Pos (16) /*!< PDMA_T::REQSEL8_11: REQSRC10 Position */ +#define PDMA_REQSEL8_11_REQSRC10_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC10_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC10 Mask */ + +#define PDMA_REQSEL8_11_REQSRC11_Pos (24) /*!< PDMA_T::REQSEL8_11: REQSRC11 Position */ +#define PDMA_REQSEL8_11_REQSRC11_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC11_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC11 Mask */ + +#define PDMA_REQSEL12_15_REQSRC12_Pos (0) /*!< PDMA_T::REQSEL12_15: REQSRC12 Position */ +#define PDMA_REQSEL12_15_REQSRC12_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC12_Pos) /*!< PDMA_T::REQSEL12_15: REQSRC12 Mask */ + +#define PDMA_REQSEL12_15_REQSRC13_Pos (8) /*!< PDMA_T::REQSEL12_15: REQSRC13 Position */ +#define PDMA_REQSEL12_15_REQSRC13_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC13_Pos) /*!< PDMA_T::REQSEL12_15: REQSRC13 Mask */ + +#define PDMA_REQSEL12_15_REQSRC14_Pos (16) /*!< PDMA_T::REQSEL12_15: REQSRC14 Position */ +#define PDMA_REQSEL12_15_REQSRC14_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC14_Pos) /*!< PDMA_T::REQSEL12_15: REQSRC14 Mask */ + +#define PDMA_REQSEL12_15_REQSRC15_Pos (24) /*!< PDMA_T::REQSEL12_15: REQSRC15 Position */ +#define PDMA_REQSEL12_15_REQSRC15_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC15_Pos) /*!< PDMA_T::REQSEL12_15: REQSRC15 Mask */ + +#define PDMA_STCRn_STC_Pos (0) /*!< PDMA_T::STCRn: STC Position */ +#define PDMA_STCRn_STC_Msk (0xfffful << PDMA_STCRn_STC_Pos) /*!< PDMA_T::STCRn: STC Mask */ + +#define PDMA_ASOCRn_SASOL_Pos (0) /*!< PDMA_T::ASOCRn: SASOL Position */ +#define PDMA_ASOCRn_SASOL_Msk (0xfffful << PDMA_ASOCRn_SASOL_Pos) /*!< PDMA_T::ASOCRn: SASOL Mask */ + +#define PDMA_ASOCRn_DASOL_Pos (16) /*!< PDMA_T::ASOCRn: DASOL Position */ +#define PDMA_ASOCRn_DASOL_Msk (0xfffful << PDMA_ASOCRn_DASOL_Pos) /*!< PDMA_T::ASOCRn: DASOL Mask */ + +#define PDMA_RCNTn_RCNT_Pos (0) /*!< PDMA_T::RCNTn: RCNT Position */ +#define PDMA_RCNTn_RCNT_Msk (0xfffful << PDMA_STCRn_RCNT_Pos) /*!< PDMA_T::RCNTn: RCNT Mask */ + +#define PDMA_AICTLn_SAICNT_Pos (0) /*!< PDMA_T::AICTLn: SAICNT Position */ +#define PDMA_AICTLn_SAICNT_Msk (0xfffful << PDMA_ASOCRn_SASOL_Pos) /*!< PDMA_T::AICTLn: SAICNT Mask */ + +#define PDMA_AICTLn_DAICNT_Pos (16) /*!< PDMA_T::AICTLn: DAICNT Position */ +#define PDMA_AICTLn_DAICNT_Msk (0xfffful << PDMA_ASOCRn_DASOL_Pos) /*!< PDMA_T::AICTLn: DAICNT Mask */ + +/**@}*/ /* PDMA_CONST */ +/**@}*/ /* end of PDMA register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __PDMA_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/qei_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/qei_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..19de07545e2a700a30b8b7e2a5543e1a76f10fb7 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/qei_reg.h @@ -0,0 +1,315 @@ +/**************************************************************************//** + * @file qei_reg.h + * @version V1.00 + * @brief QEI register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __QEI_REG_H__ +#define __QEI_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup QEI Quadrature Encoder Interface(QEI) + Memory Mapped Structure for QEI Controller +@{ */ + +typedef struct +{ + + + /** + * @var QEI_T::CNT + * Offset: 0x00 QEI Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |Quadrature Encoder Interface Counter + * | | |A 32-bit up/down counter + * | | |When an effective phase pulse is detected, this counter is increased by one if the bit DIRF (QEI_STATUS[8]) is one or decreased by one if the bit DIRF(QEI_STATUS[8]) is zero + * | | |This register performs an integrator which count value is proportional to the encoder position + * | | |The pulse counter may be initialized to a predetermined value by one of three events occurs: + * | | |1. Software is written if QEIEN (QEI_CTL[29]) = 0. + * | | |2. Compare-match event if QEIEN(QEI_CTL[29])=1 and QEI is in compare-counting mode. + * | | |3. Index signal change if QEIEN(QEI_CTL[29])=1 and IDXRLDEN (QEI_CTL[27])=1. + * @var QEI_T::CNTHOLD + * Offset: 0x04 QEI Counter Hold Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNTHOLD |Quadrature Encoder Interface Counter Hold + * | | |When bit HOLDCNT (QEI_CTL[24]) goes from low to high, the CNT(QEI_CNT[31:0]) is copied into CNTHOLD (QEI_CNTHOLD[31:0]) register. + * @var QEI_T::CNTLATCH + * Offset: 0x08 QEI Counter Index Latch Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNTLATCH |Quadrature Encoder Interface Counter Index Latch + * | | |When the IDXF (QEI_STATUS[0]) bit is set, the CNT(QEI_CNT[31:0]) is copied into CNTLATCH (QEI_CNTLATCH[31:0]) register. + * @var QEI_T::CNTCMP + * Offset: 0x0C QEI Counter Compare Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNTCMP |Quadrature Encoder Interface Counter Compare + * | | |If the QEI controller is in the compare-counting mode CMPEN (QEI_CTL[28]) =1, when the value of CNT(QEI_CNT[31:0]) matches CNTCMP(QEI_CNTCMP[31:0]), CMPF will be set + * | | |This register is software writable. + * @var QEI_T::CNTMAX + * Offset: 0x14 QEI Pre-set Maximum Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNTMAX |Quadrature Encoder Interface Preset Maximum Count + * | | |This register value determined by user stores the maximum value which may be the number of the QEI counter for the QEI controller compare-counting mode + * @var QEI_T::CTL + * Offset: 0x18 QEI Controller Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |NFCLKSEL |Noise Filter Clock Pre-divide Selection + * | | |To determine the sampling frequency of the Noise Filter clock . + * | | |000 = QEI_CLK. + * | | |001 = QEI_CLK/2. + * | | |010 = QEI_CLK/4. + * | | |011 = QEI_CLK/16. + * | | |100 = QEI_CLK/32. + * | | |101 = QEI_CLK/64. + * |[3] |NFDIS |QEI Controller Input Noise Filter Disable Bit + * | | |0 = The noise filter of QEI controller Enabled. + * | | |1 = The noise filter of QEI controller Disabled. + * |[4] |CHAEN |QEA Input to QEI Controller Enable Bit + * | | |0 = QEA input to QEI Controller Disabled. + * | | |1 = QEA input to QEI Controller Enabled. + * |[5] |CHBEN |QEB Input to QEI Controller Enable Bit + * | | |0 = QEB input to QEI Controller Disabled. + * | | |1 = QEB input to QEI Controller Enabled. + * |[6] |IDXEN |IDX Input to QEI Controller Enable Bit + * | | |0 = IDX input to QEI Controller Disabled. + * | | |1 = IDX input to QEI Controller Enabled. + * |[9:8] |MODE |QEI Counting Mode Selection + * | | |There are four quadrature encoder pulse counter operation modes. + * | | |00 = X4 Free-counting Mode. + * | | |01 = X2 Free-counting Mode. + * | | |10 = X4 Compare-counting Mode. + * | | |11 = X2 Compare-counting Mode. + * |[12] |CHAINV |Inverse QEA Input Polarity + * | | |0 = Not inverse QEA input polarity. + * | | |1 = QEA input polarity is inversed to QEI controller. + * |[13] |CHBINV |Inverse QEB Input Polarity + * | | |0 = Not inverse QEB input polarity. + * | | |1 = QEB input polarity is inversed to QEI controller. + * |[14] |IDXINV |Inverse IDX Input Polarity + * | | |0 = Not inverse IDX input polarity. + * | | |1 = IDX input polarity is inversed to QEI controller. + * |[16] |OVUNIEN |OVUNF Trigger QEI Interrupt Enable Bit + * | | |0 = OVUNF can trigger QEI controller interrupt Disabled. + * | | |1 = OVUNF can trigger QEI controller interrupt Enabled. + * |[17] |DIRIEN |DIRCHGF Trigger QEI Interrupt Enable Bit + * | | |0 = DIRCHGF can trigger QEI controller interrupt Disabled. + * | | |1 = DIRCHGF can trigger QEI controller interrupt Enabled. + * |[18] |CMPIEN |CMPF Trigger QEI Interrupt Enable Bit + * | | |0 = CMPF can trigger QEI controller interrupt Disabled. + * | | |1 = CMPF can trigger QEI controller interrupt Enabled. + * |[19] |IDXIEN |IDXF Trigger QEI Interrupt Enable Bit + * | | |0 = The IDXF can trigger QEI interrupt Disabled. + * | | |1 = The IDXF can trigger QEI interrupt Enabled. + * |[20] |HOLDTMR0 |Hold QEI_CNT by Timer 0 + * | | |0 = TIF (TIMER0_INTSTS[0]) has no effect on HOLDCNT. + * | | |1 = A rising edge of bit TIF(TIMER0_INTSTS[0]) in timer 0 sets HOLDCNT to 1. + * |[21] |HOLDTMR1 |Hold QEI_CNT by Timer 1 + * | | |0 = TIF(TIMER1_INTSTS[0]) has no effect on HOLDCNT. + * | | |1 = A rising edge of bit TIF (TIMER1_INTSTS[0]) in timer 1 sets HOLDCNT to 1. + * |[22] |HOLDTMR2 |Hold QEI_CNT by Timer 2 + * | | |0 = TIF(TIMER2_INTSTS[0]) has no effect on HOLDCNT. + * | | |1 = A rising edge of bit TIF(TIMER2_INTSTS[0]) in timer 2 sets HOLDCNT to 1. + * |[23] |HOLDTMR3 |Hold QEI_CNT by Timer 3 + * | | |0 = TIF (TIMER3_INTSTS[0]) has no effect on HOLDCNT. + * | | |1 = A rising edge of bit TIF(TIMER3_INTSTS[0]) in timer 3 sets HOLDCNT to 1. + * |[24] |HOLDCNT |Hold QEI_CNT Control + * | | |When this bit is set from low to high, the CNT(QEI_CNT[31:0]) is copied into CNTHOLD(QEI_CNTHOLD[31:0]) + * | | |This bit may be set by writing 1 to it or Timer0~Timer3 interrupt flag TIF (TIMERx_INTSTS[0]). + * | | |0 = No operation. + * | | |1 = QEI_CNT content is captured and stored in CNTHOLD(QEI_CNTHOLD[31:0]). + * | | |Note: This bit is automatically cleared after QEI_CNTHOLD holds QEI_CNT value. + * |[25] |IDXLATEN |Index Latch QEI_CNT Enable Bit + * | | |If this bit is set to high, the CNT(QEI_CNT[31:0]) content will be latched into CNTLATCH (QEI_CNTLATCH[31:0]) at every rising on signal CHX. + * | | |0 = The index signal latch QEI counter function Disabled. + * | | |1 = The index signal latch QEI counter function Enabled. + * |[27] |IDXRLDEN |Index Trigger QEI_CNT Reload Enable Bit + * | | |When this bit is high and a rising edge comes on signal CHX, the CNT(QEI_CNT[31:0]) will be reset to zero if the counter is in up-counting type (DIRF(QEI_STATUS[8]) = 1); while the CNT(QEI_CNT[31:0]) will be reloaded with CNTMAX (QEI_CNTMAX[31:0]) content if the counter is in down-counting type (DIRF(QEI_STATUS[8]) = 0). + * | | |0 = Reload function Disabled. + * | | |1 = QEI_CNT re-initialized by Index signal Enabled. + * |[28] |CMPEN |The Compare Function Enable Bit + * | | |The compare function in QEI controller is to compare the dynamic counting QEI_CNT with the compare register CNTCMP( QEI_CNTCMP[31:0]), if CNT(QEI_CNT[31:0]) reaches CNTCMP( QEI_CNTCMP[31:0]), the flag CMPF will be set. + * | | |0 = Compare function Disabled. + * | | |1 = Compare function Enabled. + * |[29] |QEIEN |Quadrature Encoder Interface Controller Enable Bit + * | | |0 = QEI controller function Disabled. + * | | |1 = QEI controller function Enabled. + * @var QEI_T::STATUS + * Offset: 0x2C QEI Controller Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |IDXF |IDX Detected Flag + * | | |When the QEI controller detects a rising edge on signal CHX it will set flag IDXF to high. + * | | |0 = No rising edge detected on signal CHX. + * | | |1 = A rising edge occurs on signal CHX. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[1] |CMPF |Compare-match Flag + * | | |If the QEI compare function is enabled, the flag is set by hardware while QEI counter up or down counts and reach to the CNTCMP(QEI_CNTCMP[31:0]). + * | | |0 = QEI counter does not match with CNTCMP(QEI_CNTCMP[31:0]). + * | | |1 = QEI counter counts to the same as CNTCMP(QEI_CNTCMP[31:0]). + * | | |Note: This bit is only cleared by writing 1 to it. + * |[2] |OVUNF |QEI Counter Overflow or Underflow Flag + * | | |Flag is set by hardware while CNT(QEI_CNT[31:0]) overflows from 0xFFFF_FFFF to zero in free-counting mode or from the CNTMAX (QEI_CNTMAX[31:0]) to zero in compare-counting mode + * | | |Similarly, the flag is set while QEI counter underflows from zero to 0xFFFF_FFFF or CNTMAX (QEI_CNTMAX[31:0]). + * | | |0 = No overflow or underflow occurs in QEI counter. + * | | |1 = QEI counter occurs counting overflow or underflow. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[3] |DIRCHGF |Direction Change Flag + * | | |Flag is set by hardware while QEI counter counting direction is changed. + * | | |Software can clear this bit by writing 1 to it. + * | | |0 = No change in QEI counter counting direction. + * | | |1 = QEI counter counting direction is changed. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[8] |DIRF |QEI Counter Counting Direction Indication + * | | |0 = QEI Counter is in down-counting. + * | | |1 = QEI Counter is in up-counting. + * | | |Note: This bit is set/reset by hardware according to the phase detection between CHA and CHB. + */ + __IO uint32_t CNT; /*!< [0x0000] QEI Counter Register */ + __IO uint32_t CNTHOLD; /*!< [0x0004] QEI Counter Hold Register */ + __IO uint32_t CNTLATCH; /*!< [0x0008] QEI Counter Index Latch Register */ + __IO uint32_t CNTCMP; /*!< [0x000c] QEI Counter Compare Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CNTMAX; /*!< [0x0014] QEI Pre-set Maximum Count Register */ + __IO uint32_t CTL; /*!< [0x0018] QEI Controller Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[4]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t STATUS; /*!< [0x002c] QEI Controller Status Register */ + +} QEI_T; + +/** + @addtogroup QEI_CONST QEI Bit Field Definition + Constant Definitions for QEI Controller +@{ */ + +#define QEI_CNT_CNT_Pos (0) /*!< QEI_T::CNT: CNT Position */ +#define QEI_CNT_CNT_Msk (0xfffffffful << QEI_CNT_CNT_Pos) /*!< QEI_T::CNT: CNT Mask */ + +#define QEI_CNTHOLD_CNTHOLD_Pos (0) /*!< QEI_T::CNTHOLD: CNTHOLD Position */ +#define QEI_CNTHOLD_CNTHOLD_Msk (0xfffffffful << QEI_CNTHOLD_CNTHOLD_Pos) /*!< QEI_T::CNTHOLD: CNTHOLD Mask */ + +#define QEI_CNTLATCH_CNTLATCH_Pos (0) /*!< QEI_T::CNTLATCH: CNTLATCH Position */ +#define QEI_CNTLATCH_CNTLATCH_Msk (0xfffffffful << QEI_CNTLATCH_CNTLATCH_Pos) /*!< QEI_T::CNTLATCH: CNTLATCH Mask */ + +#define QEI_CNTCMP_CNTCMP_Pos (0) /*!< QEI_T::CNTCMP: CNTCMP Position */ +#define QEI_CNTCMP_CNTCMP_Msk (0xfffffffful << QEI_CNTCMP_CNTCMP_Pos) /*!< QEI_T::CNTCMP: CNTCMP Mask */ + +#define QEI_CNTMAX_CNTMAX_Pos (0) /*!< QEI_T::CNTMAX: CNTMAX Position */ +#define QEI_CNTMAX_CNTMAX_Msk (0xfffffffful << QEI_CNTMAX_CNTMAX_Pos) /*!< QEI_T::CNTMAX: CNTMAX Mask */ + +#define QEI_CTL_NFCLKSEL_Pos (0) /*!< QEI_T::CTL: NFCLKSEL Position */ +#define QEI_CTL_NFCLKSEL_Msk (0x7ul << QEI_CTL_NFCLKSEL_Pos) /*!< QEI_T::CTL: NFCLKSEL Mask */ + +#define QEI_CTL_NFDIS_Pos (3) /*!< QEI_T::CTL: NFDIS Position */ +#define QEI_CTL_NFDIS_Msk (0x1ul << QEI_CTL_NFDIS_Pos) /*!< QEI_T::CTL: NFDIS Mask */ + +#define QEI_CTL_CHAEN_Pos (4) /*!< QEI_T::CTL: CHAEN Position */ +#define QEI_CTL_CHAEN_Msk (0x1ul << QEI_CTL_CHAEN_Pos) /*!< QEI_T::CTL: CHAEN Mask */ + +#define QEI_CTL_CHBEN_Pos (5) /*!< QEI_T::CTL: CHBEN Position */ +#define QEI_CTL_CHBEN_Msk (0x1ul << QEI_CTL_CHBEN_Pos) /*!< QEI_T::CTL: CHBEN Mask */ + +#define QEI_CTL_IDXEN_Pos (6) /*!< QEI_T::CTL: IDXEN Position */ +#define QEI_CTL_IDXEN_Msk (0x1ul << QEI_CTL_IDXEN_Pos) /*!< QEI_T::CTL: IDXEN Mask */ + +#define QEI_CTL_MODE_Pos (8) /*!< QEI_T::CTL: MODE Position */ +#define QEI_CTL_MODE_Msk (0x3ul << QEI_CTL_MODE_Pos) /*!< QEI_T::CTL: MODE Mask */ + +#define QEI_CTL_CHAINV_Pos (12) /*!< QEI_T::CTL: CHAINV Position */ +#define QEI_CTL_CHAINV_Msk (0x1ul << QEI_CTL_CHAINV_Pos) /*!< QEI_T::CTL: CHAINV Mask */ + +#define QEI_CTL_CHBINV_Pos (13) /*!< QEI_T::CTL: CHBINV Position */ +#define QEI_CTL_CHBINV_Msk (0x1ul << QEI_CTL_CHBINV_Pos) /*!< QEI_T::CTL: CHBINV Mask */ + +#define QEI_CTL_IDXINV_Pos (14) /*!< QEI_T::CTL: IDXINV Position */ +#define QEI_CTL_IDXINV_Msk (0x1ul << QEI_CTL_IDXINV_Pos) /*!< QEI_T::CTL: IDXINV Mask */ + +#define QEI_CTL_OVUNIEN_Pos (16) /*!< QEI_T::CTL: OVUNIEN Position */ +#define QEI_CTL_OVUNIEN_Msk (0x1ul << QEI_CTL_OVUNIEN_Pos) /*!< QEI_T::CTL: OVUNIEN Mask */ + +#define QEI_CTL_DIRIEN_Pos (17) /*!< QEI_T::CTL: DIRIEN Position */ +#define QEI_CTL_DIRIEN_Msk (0x1ul << QEI_CTL_DIRIEN_Pos) /*!< QEI_T::CTL: DIRIEN Mask */ + +#define QEI_CTL_CMPIEN_Pos (18) /*!< QEI_T::CTL: CMPIEN Position */ +#define QEI_CTL_CMPIEN_Msk (0x1ul << QEI_CTL_CMPIEN_Pos) /*!< QEI_T::CTL: CMPIEN Mask */ + +#define QEI_CTL_IDXIEN_Pos (19) /*!< QEI_T::CTL: IDXIEN Position */ +#define QEI_CTL_IDXIEN_Msk (0x1ul << QEI_CTL_IDXIEN_Pos) /*!< QEI_T::CTL: IDXIEN Mask */ + +#define QEI_CTL_HOLDTMR0_Pos (20) /*!< QEI_T::CTL: HOLDTMR0 Position */ +#define QEI_CTL_HOLDTMR0_Msk (0x1ul << QEI_CTL_HOLDTMR0_Pos) /*!< QEI_T::CTL: HOLDTMR0 Mask */ + +#define QEI_CTL_HOLDTMR1_Pos (21) /*!< QEI_T::CTL: HOLDTMR1 Position */ +#define QEI_CTL_HOLDTMR1_Msk (0x1ul << QEI_CTL_HOLDTMR1_Pos) /*!< QEI_T::CTL: HOLDTMR1 Mask */ + +#define QEI_CTL_HOLDTMR2_Pos (22) /*!< QEI_T::CTL: HOLDTMR2 Position */ +#define QEI_CTL_HOLDTMR2_Msk (0x1ul << QEI_CTL_HOLDTMR2_Pos) /*!< QEI_T::CTL: HOLDTMR2 Mask */ + +#define QEI_CTL_HOLDTMR3_Pos (23) /*!< QEI_T::CTL: HOLDTMR3 Position */ +#define QEI_CTL_HOLDTMR3_Msk (0x1ul << QEI_CTL_HOLDTMR3_Pos) /*!< QEI_T::CTL: HOLDTMR3 Mask */ + +#define QEI_CTL_HOLDCNT_Pos (24) /*!< QEI_T::CTL: HOLDCNT Position */ +#define QEI_CTL_HOLDCNT_Msk (0x1ul << QEI_CTL_HOLDCNT_Pos) /*!< QEI_T::CTL: HOLDCNT Mask */ + +#define QEI_CTL_IDXLATEN_Pos (25) /*!< QEI_T::CTL: IDXLATEN Position */ +#define QEI_CTL_IDXLATEN_Msk (0x1ul << QEI_CTL_IDXLATEN_Pos) /*!< QEI_T::CTL: IDXLATEN Mask */ + +#define QEI_CTL_IDXRLDEN_Pos (27) /*!< QEI_T::CTL: IDXRLDEN Position */ +#define QEI_CTL_IDXRLDEN_Msk (0x1ul << QEI_CTL_IDXRLDEN_Pos) /*!< QEI_T::CTL: IDXRLDEN Mask */ + +#define QEI_CTL_CMPEN_Pos (28) /*!< QEI_T::CTL: CMPEN Position */ +#define QEI_CTL_CMPEN_Msk (0x1ul << QEI_CTL_CMPEN_Pos) /*!< QEI_T::CTL: CMPEN Mask */ + +#define QEI_CTL_QEIEN_Pos (29) /*!< QEI_T::CTL: QEIEN Position */ +#define QEI_CTL_QEIEN_Msk (0x1ul << QEI_CTL_QEIEN_Pos) /*!< QEI_T::CTL: QEIEN Mask */ + +#define QEI_STATUS_IDXF_Pos (0) /*!< QEI_T::STATUS: IDXF Position */ +#define QEI_STATUS_IDXF_Msk (0x1ul << QEI_STATUS_IDXF_Pos) /*!< QEI_T::STATUS: IDXF Mask */ + +#define QEI_STATUS_CMPF_Pos (1) /*!< QEI_T::STATUS: CMPF Position */ +#define QEI_STATUS_CMPF_Msk (0x1ul << QEI_STATUS_CMPF_Pos) /*!< QEI_T::STATUS: CMPF Mask */ + +#define QEI_STATUS_OVUNF_Pos (2) /*!< QEI_T::STATUS: OVUNF Position */ +#define QEI_STATUS_OVUNF_Msk (0x1ul << QEI_STATUS_OVUNF_Pos) /*!< QEI_T::STATUS: OVUNF Mask */ + +#define QEI_STATUS_DIRCHGF_Pos (3) /*!< QEI_T::STATUS: DIRCHGF Position */ +#define QEI_STATUS_DIRCHGF_Msk (0x1ul << QEI_STATUS_DIRCHGF_Pos) /*!< QEI_T::STATUS: DIRCHGF Mask */ + +#define QEI_STATUS_DIRF_Pos (8) /*!< QEI_T::STATUS: DIRF Position */ +#define QEI_STATUS_DIRF_Msk (0x1ul << QEI_STATUS_DIRF_Pos) /*!< QEI_T::STATUS: DIRF Mask */ + +/**@}*/ /* QEI_CONST */ +/**@}*/ /* end of QEI register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __QEI_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/qspi_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/qspi_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..890fe5c78de58c07f6ed5f486222a6547a2a6d4e --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/qspi_reg.h @@ -0,0 +1,592 @@ +/**************************************************************************//** + * @file qspi_reg.h + * @version V1.00 + * @brief QSPI register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __QSPI_REG_H__ +#define __QSPI_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup QSPI Serial Peripheral Interface Controller(QSPI) + Memory Mapped Structure for QSPI Controller +@{ */ + +typedef struct +{ + + + /** + * @var QSPI_T::CTL + * Offset: 0x00 QSPI Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |QSPIEN |QSPI Transfer Control Enable Bit + * | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1 + * | | |In Slave mode, this device is ready to receive data when this bit is set to 1. + * | | |0 = Transfer control Disabled. + * | | |1 = Transfer control Enabled. + * | | |Note: Before changing the configurations of QSPIx_CTL, QSPIx_CLKDIV, QSPIx_SSCTL and QSPIx_FIFOCTL registers, user shall clear the QSPIEN (QSPIx_CTL[0]) and confirm the QSPIENSTS (QSPIx_STATUS[15]) is 0. + * |[1] |RXNEG |Receive on Negative Edge + * | | |0 = Received data input signal is latched on the rising edge of QSPI bus clock. + * | | |1 = Received data input signal is latched on the falling edge of QSPI bus clock. + * |[2] |TXNEG |Transmit on Negative Edge + * | | |0 = Transmitted data output signal is changed on the rising edge of QSPI bus clock. + * | | |1 = Transmitted data output signal is changed on the falling edge of QSPI bus clock. + * |[3] |CLKPOL |Clock Polarity + * | | |0 = QSPI bus clock is idle low. + * | | |1 = QSPI bus clock is idle high. + * |[7:4] |SUSPITV |Suspend Interval (Master Only) + * | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer + * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word + * | | |The default value is 0x3 + * | | |The period of the suspend interval is obtained according to the following equation. + * | | |(SUSPITV[3:0] + 0.5) * period of QSPICLK clock cycle + * | | |Example: + * | | |SUSPITV = 0x0 .... 0.5 QSPICLK clock cycle. + * | | |SUSPITV = 0x1 .... 1.5 QSPICLK clock cycle. + * | | |..... + * | | |SUSPITV = 0xE .... 14.5 QSPICLK clock cycle. + * | | |SUSPITV = 0xF .... 15.5 QSPICLK clock cycle. + * |[12:8] |DWIDTH |Data Width + * | | |This field specifies how many bits can be transmitted / received in one transaction + * | | |The minimum bit length is 8 bits and can up to 32 bits. + * | | |DWIDTH = 0x08 .... 8 bits. + * | | |DWIDTH = 0x09 .... 9 bits. + * | | |..... + * | | |DWIDTH = 0x1F .... 31 bits. + * | | |DWIDTH = 0x00 .... 32 bits. + * |[13] |LSB |Send LSB First + * | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first. + * | | |1 = The LSB, bit 0 of the QSPI TX register, is sent first to the QSPI data output pin, and the first bit received from the QSPI data input pin will be put in the LSB position of the RX register (bit 0 of QSPI_RX). + * |[14] |HALFDPX |QSPI Half-duplex Transfer Enable Bit + * | | |This bit is used to select full-duplex or half-duplex for QSPI transfer + * | | |The bit field DATDIR (QSPIx_CTL[20]) can be used to set the data direction in half-duplex transfer. + * | | |0 = QSPI operates in full-duplex transfer. + * | | |1 = QSPI operates in half-duplex transfer. + * |[15] |RXONLY |Receive-only Mode Enable Bit (Master Only) + * | | |This bit field is only available in Master mode + * | | |In receive-only mode, QSPI Master will generate QSPI bus clock continuously for receiving data bit from QSPI slave device and assert the BUSY status. + * | | |0 = Receive-only mode Disabled. + * | | |1 = Receive-only mode Enabled. + * |[16] |TWOBIT |2-bit Transfer Mode Enable Bit (Only Supported in QSPI0) + * | | |0 = 2-Bit Transfer mode Disabled. + * | | |1 = 2-Bit Transfer mode Enabled. + * | | |Note: When 2-Bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data + * | | |As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time. + * |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit + * | | |0 = QSPI unit transfer interrupt Disabled. + * | | |1 = QSPI unit transfer interrupt Enabled. + * |[18] |SLAVE |Slave Mode Control + * | | |0 = Master mode. + * | | |1 = Slave mode. + * |[19] |REORDER |Byte Reorder Function Enable Bit + * | | |0 = Byte Reorder function Disabled. + * | | |1 = Byte Reorder function Enabled + * | | |A byte suspend interval will be inserted among each byte + * | | |The period of the byte suspend interval depends on the setting of SUSPITV. + * | | |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits. + * |[20] |DATDIR |Data Port Direction Control + * | | |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer + * | | |0 = QSPI data is input direction. + * | | |1 = QSPI data is output direction. + * |[21] |DUALIOEN |Dual I/O Mode Enable Bit (Only Supported in QSPI0) + * | | |0 = Dual I/O mode Disabled. + * | | |1 = Dual I/O mode Enabled. + * |[22] |QUADIOEN |Quad I/O Mode Enable Bit (Only Supported in QSPI0) + * | | |0 = Quad I/O mode Disabled. + * | | |1 = Quad I/O mode Enabled. + * @var QSPI_T::CLKDIV + * Offset: 0x04 QSPI Clock Divider Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |DIVIDER |Clock Divider + * | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the QSPI bus clock of QSPI Master + * | | |The frequency is obtained according to the following equation. + * | | |where + * | | |is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2. + * @var QSPI_T::SSCTL + * Offset: 0x08 QSPI Slave Select Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SS |Slave Selection Control (Master Only) + * | | |If AUTOSS bit is cleared to 0, + * | | |0 = set the QSPIx_SS line to inactive state. + * | | |1 = set the QSPIx_SS line to active state. + * | | |If the AUTOSS bit is set to 1, + * | | |0 = Keep the QSPIx_SS line at inactive state. + * | | |1 = QSPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time + * | | |The active state of QSPIx_SS is specified in SSACTPOL (QSPIx_SSCTL[2]). + * |[2] |SSACTPOL |Slave Selection Active Polarity + * | | |This bit defines the active polarity of slave selection signal (QSPIx_SS). + * | | |0 = The slave selection signal QSPIx_SS is active low. + * | | |1 = The slave selection signal QSPIx_SS is active high. + * |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit (Master Only) + * | | |0 = Automatic slave selection function Disabled + * | | |Slave selection signal will be asserted/de-asserted according to SS (QSPIx_SSCTL[0]). + * | | |1 = Automatic slave selection function Enabled. + * |[4] |SLV3WIRE |Slave 3-wire Mode Enable Bit (Only Supported in QSPI0) + * | | |Slave 3-wire mode is only available in QSPI0 + * | | |In Slave 3-wire mode, the QSPI controller can work with 3-wire interface including QSPI0_CLK, QSPI0_MISO and QSPI0_MOSI pins. + * | | |0 = 4-wire bi-direction interface. + * | | |1 = 3-wire bi-direction interface. + * |[5] |SLVTOIEN |Slave Mode Time-out Interrupt Enable Bit (Only Supported in QSPI0) + * | | |0 = Slave mode time-out interrupt Disabled. + * | | |1 = Slave mode time-out interrupt Enabled. + * |[6] |SLVTORST |Slave Mode Time-out Reset Control (Only Supported in QSPI0) + * | | |0 = When Slave mode time-out event occurs, the TX and RX control circuit will not be reset. + * | | |1 = When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware. + * |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit + * | | |0 = Slave mode bit count error interrupt Disabled. + * | | |1 = Slave mode bit count error interrupt Enabled. + * |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit + * | | |0 = Slave mode TX under run interrupt Disabled. + * | | |1 = Slave mode TX under run interrupt Enabled. + * |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit + * | | |0 = Slave select active interrupt Disabled. + * | | |1 = Slave select active interrupt Enabled. + * |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit + * | | |0 = Slave select inactive interrupt Disabled. + * | | |1 = Slave select inactive interrupt Enabled. + * |[31:16] |SLVTOCNT |Slave Mode Time-out Period (Only Supported in QSPI0) + * | | |In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active + * | | |The clock source of the time-out counter is Slave peripheral clock + * | | |If the value is 0, it indicates the slave mode time-out function is disabled. + * @var QSPI_T::PDMACTL + * Offset: 0x0C QSPI PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TXPDMAEN |Transmit PDMA Enable Bit + * | | |0 = Transmit PDMA function Disabled. + * | | |1 = Transmit PDMA function Enabled. + * | | |Note: In QSPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function + * | | |User can enable TX PDMA function firstly or enable both functions simultaneously. + * |[1] |RXPDMAEN |Receive PDMA Enable Bit + * | | |0 = Receive PDMA function Disabled. + * | | |1 = Receive PDMA function Enabled. + * |[2] |PDMARST |PDMA Reset + * | | |0 = No effect. + * | | |1 = Reset the PDMA control logic of the QSPI controller. This bit will be automatically cleared to 0. + * @var QSPI_T::FIFOCTL + * Offset: 0x10 QSPI FIFO Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXRST |Receive Reset + * | | |0 = No effect. + * | | |1 = Reset receive FIFO pointer and receive circuit + * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 + * | | |User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not. + * |[1] |TXRST |Transmit Reset + * | | |0 = No effect. + * | | |1 = Reset transmit FIFO pointer and transmit circuit + * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 + * | | |User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not. + * | | |Note: If TX underflow event occurs in QSPI Slave mode, this bit can be used to make QSPI return to idle state. + * |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit + * | | |0 = RX FIFO threshold interrupt Disabled. + * | | |1 = RX FIFO threshold interrupt Enabled. + * |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit + * | | |0 = TX FIFO threshold interrupt Disabled. + * | | |1 = TX FIFO threshold interrupt Enabled. + * |[4] |RXTOIEN |Slave Receive Time-out Interrupt Enable Bit + * | | |0 = Receive time-out interrupt Disabled. + * | | |1 = Receive time-out interrupt Enabled. + * |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit + * | | |0 = Receive FIFO overrun interrupt Disabled. + * | | |1 = Receive FIFO overrun interrupt Enabled. + * |[6] |TXUFPOL |TX Underflow Data Polarity + * | | |0 = The QSPI data out is keep 0 if there is TX underflow event in Slave mode. + * | | |1 = The QSPI data out is keep 1 if there is TX underflow event in Slave mode. + * | | |Note: + * | | |1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active. + * | | |2. When TX underflow event occurs, QSPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward + * | | |Data stored in TX FIFO will be sent through QSPIx_MISO pin in the next transfer frame. + * |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit + * | | |When TX underflow event occurs in Slave mode, TXUFIF (QSPIx_STATUS[19]) will be set to 1 + * | | |This bit is used to enable the TX underflow interrupt. + * | | |0 = Slave TX underflow interrupt Disabled. + * | | |1 = Slave TX underflow interrupt Enabled. + * |[8] |RXFBCLR |Receive FIFO Buffer Clear + * | | |0 = No effect. + * | | |1 = Clear receive FIFO pointer + * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. + * | | |Note: The RX shift register will not be cleared. + * |[9] |TXFBCLR |Transmit FIFO Buffer Clear + * | | |0 = No effect. + * | | |1 = Clear transmit FIFO pointer + * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. + * | | |Note: The TX shift register will not be cleared. + * |[26:24] |RXTH |Receive FIFO Threshold + * | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0 + * |[30:28] |TXTH |Transmit FIFO Threshold + * | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0 + * @var QSPI_T::STATUS + * Offset: 0x14 QSPI Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |Busy Status (Read Only) + * | | |0 = QSPI controller is in idle state. + * | | |1 = QSPI controller is in busy state. + * | | |The following listing are the bus busy conditions: + * | | |a. QSPIx_CTL[0] = 1 and TXEMPTY = 0. + * | | |b + * | | |For QSPI Master mode, QSPIx_CTL[0] = 1 and TXEMPTY = 1 but the current transaction is not finished yet. + * | | |c. For QSPI Master mode, QSPIx_CTL[0] = 1 and RXONLY = 1. + * | | |d + * | | |For QSPI Slave mode, the QSPIx_CTL[0] = 1 and there is serial clock input into the QSPI core logic when slave select is active. + * | | |For QSPI Slave mode, the QSPIx_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive. + * |[1] |UNITIF |Unit Transfer Interrupt Flag + * | | |0 = No transaction has been finished since this bit was cleared to 0. + * | | |1 = QSPI controller has finished one unit transfer. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[2] |SSACTIF |Slave Select Active Interrupt Flag + * | | |0 = Slave select active interrupt was cleared or not occurred. + * | | |1 = Slave select active interrupt event occurred. + * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. + * |[3] |SSINAIF |Slave Select Inactive Interrupt Flag + * | | |0 = Slave select inactive interrupt was cleared or not occurred. + * | | |1 = Slave select inactive interrupt event occurred. + * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. + * |[4] |SSLINE |Slave Select Line Bus Status (Read Only) + * | | |0 = The slave select line status is 0. + * | | |1 = The slave select line status is 1. + * | | |Note: This bit is only available in Slave mode + * | | |If SSACTPOL (QSPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the QSPI slave select is in inactive status. + * |[5] |SLVTOIF |Slave Time-out Interrupt Flag (Only Supported in QSPI0) + * | | |When the slave select is active and the value of SLVTOCNT is not 0, as the bus clock is detected, the slave time-out counter in QSPI controller logic will be started + * | | |When the value of time-out counter is greater than or equal to the value of SLVTOCNT (QSPI_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted. + * | | |0 = Slave time-out is not active. + * | | |1 = Slave time-out is active. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag + * | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1. + * | | |0 = No Slave mode bit count error event. + * | | |1 = Slave mode bit count error event occurs. + * | | |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state + * | | |This bit will be cleared by writing 1 to it. + * |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag + * | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1. + * | | |0 = No Slave TX under run event. + * | | |1 = Slave TX under run event occurs. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not empty. + * | | |1 = Receive FIFO buffer is empty. + * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not full. + * | | |1 = Receive FIFO buffer is full. + * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH. + * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH. + * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag + * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. + * | | |0 = No FIFO is overrun. + * | | |1 = Receive FIFO is overrun. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[12] |RXTOIF |Receive Time-out Interrupt Flag + * | | |0 = No receive FIFO time-out event. + * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 QSPI peripheral clock periods in Master mode or over 576 QSPI peripheral clock periods in Slave mode + * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[15] |QSPIENSTS |QSPI Enable Status (Read Only) + * | | |0 = The QSPI controller is disabled. + * | | |1 = The QSPI controller is enabled. + * | | |Note: The QSPI peripheral clock is asynchronous with the system clock + * | | |In order to make sure the QSPI control logic is disabled, this bit indicates the real status of QSPI controller. + * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not empty. + * | | |1 = Transmit FIFO buffer is empty. + * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not full. + * | | |1 = Transmit FIFO buffer is full. + * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH. + * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH. + * |[19] |TXUFIF |TX Underflow Interrupt Flag + * | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL. + * | | |0 = No effect. + * | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active. + * | | |Note 1: This bit will be cleared by writing 1 to it. + * | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done. + * |[23] |TXRXRST |TX or RX Reset Status (Read Only) + * | | |0 = The reset function of TXRST or RXRST is done. + * | | |1 = Doing the reset function of TXRST or RXRST. + * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles + * | | |User can check the status of this bit to monitor the reset function is doing or done. + * |[27:24] |RXCNT |Receive FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of receive FIFO buffer. + * |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of transmit FIFO buffer. + * @var QSPI_T::TX + * Offset: 0x20 QSPI Data Transmit Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TX |Data Transmit Register + * | | |The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers + * | | |The number of valid bits depends on the setting of DWIDTH (QSPIx_CTL[12:8]) in SPI mode. + * | | |In SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted + * | | |If DWIDTH is set to 0x00 , the QSPI controller will perform a 32-bit transfer. + * | | |If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid + * | | |Note: In Master mode, QSPI controller will start to transfer the QSPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register. + * @var QSPI_T::RX + * Offset: 0x30 QSPI Data Receive Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RX |Data Receive Register + * | | |There are 4-level FIFO buffers in this controller + * | | |The data receive register holds the data received from QSPI data input pin + * | | |This is a read only register. + */ + __IO uint32_t CTL; /*!< [0x0000] QSPI Control Register */ + __IO uint32_t CLKDIV; /*!< [0x0004] QSPI Clock Divider Register */ + __IO uint32_t SSCTL; /*!< [0x0008] QSPI Slave Select Control Register */ + __IO uint32_t PDMACTL; /*!< [0x000c] QSPI PDMA Control Register */ + __IO uint32_t FIFOCTL; /*!< [0x0010] QSPI FIFO Control Register */ + __IO uint32_t STATUS; /*!< [0x0014] QSPI Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[2]; + /// @endcond //HIDDEN_SYMBOLS + __O uint32_t TX; /*!< [0x0020] QSPI Data Transmit Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[3]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t RX; /*!< [0x0030] QSPI Data Receive Register */ + +} QSPI_T; + +/** + @addtogroup QSPI_CONST QSPI Bit Field Definition + Constant Definitions for QSPI Controller +@{ */ + +#define QSPI_CTL_QSPIEN_Pos (0) /*!< QSPI_T::CTL: QSPIEN Position */ +#define QSPI_CTL_QSPIEN_Msk (0x1ul << QSPI_CTL_QSPIEN_Pos) /*!< QSPI_T::CTL: QSPIEN Mask */ + +#define QSPI_CTL_RXNEG_Pos (1) /*!< QSPI_T::CTL: RXNEG Position */ +#define QSPI_CTL_RXNEG_Msk (0x1ul << QSPI_CTL_RXNEG_Pos) /*!< QSPI_T::CTL: RXNEG Mask */ + +#define QSPI_CTL_TXNEG_Pos (2) /*!< QSPI_T::CTL: TXNEG Position */ +#define QSPI_CTL_TXNEG_Msk (0x1ul << QSPI_CTL_TXNEG_Pos) /*!< QSPI_T::CTL: TXNEG Mask */ + +#define QSPI_CTL_CLKPOL_Pos (3) /*!< QSPI_T::CTL: CLKPOL Position */ +#define QSPI_CTL_CLKPOL_Msk (0x1ul << QSPI_CTL_CLKPOL_Pos) /*!< QSPI_T::CTL: CLKPOL Mask */ + +#define QSPI_CTL_SUSPITV_Pos (4) /*!< QSPI_T::CTL: SUSPITV Position */ +#define QSPI_CTL_SUSPITV_Msk (0xful << QSPI_CTL_SUSPITV_Pos) /*!< QSPI_T::CTL: SUSPITV Mask */ + +#define QSPI_CTL_DWIDTH_Pos (8) /*!< QSPI_T::CTL: DWIDTH Position */ +#define QSPI_CTL_DWIDTH_Msk (0x1ful << QSPI_CTL_DWIDTH_Pos) /*!< QSPI_T::CTL: DWIDTH Mask */ + +#define QSPI_CTL_LSB_Pos (13) /*!< QSPI_T::CTL: LSB Position */ +#define QSPI_CTL_LSB_Msk (0x1ul << QSPI_CTL_LSB_Pos) /*!< QSPI_T::CTL: LSB Mask */ + +#define QSPI_CTL_HALFDPX_Pos (14) /*!< QSPI_T::CTL: HALFDPX Position */ +#define QSPI_CTL_HALFDPX_Msk (0x1ul << QSPI_CTL_HALFDPX_Pos) /*!< QSPI_T::CTL: HALFDPX Mask */ + +#define QSPI_CTL_RXONLY_Pos (15) /*!< QSPI_T::CTL: RXONLY Position */ +#define QSPI_CTL_RXONLY_Msk (0x1ul << QSPI_CTL_RXONLY_Pos) /*!< QSPI_T::CTL: RXONLY Mask */ + +#define QSPI_CTL_TWOBIT_Pos (16) /*!< QSPI_T::CTL: TWOBIT Position */ +#define QSPI_CTL_TWOBIT_Msk (0x1ul << QSPI_CTL_TWOBIT_Pos) /*!< QSPI_T::CTL: TWOBIT Mask */ + +#define QSPI_CTL_UNITIEN_Pos (17) /*!< QSPI_T::CTL: UNITIEN Position */ +#define QSPI_CTL_UNITIEN_Msk (0x1ul << QSPI_CTL_UNITIEN_Pos) /*!< QSPI_T::CTL: UNITIEN Mask */ + +#define QSPI_CTL_SLAVE_Pos (18) /*!< QSPI_T::CTL: SLAVE Position */ +#define QSPI_CTL_SLAVE_Msk (0x1ul << QSPI_CTL_SLAVE_Pos) /*!< QSPI_T::CTL: SLAVE Mask */ + +#define QSPI_CTL_REORDER_Pos (19) /*!< QSPI_T::CTL: REORDER Position */ +#define QSPI_CTL_REORDER_Msk (0x1ul << QSPI_CTL_REORDER_Pos) /*!< QSPI_T::CTL: REORDER Mask */ + +#define QSPI_CTL_DATDIR_Pos (20) /*!< QSPI_T::CTL: DATDIR Position */ +#define QSPI_CTL_DATDIR_Msk (0x1ul << QSPI_CTL_DATDIR_Pos) /*!< QSPI_T::CTL: DATDIR Mask */ + +#define QSPI_CTL_DUALIOEN_Pos (21) /*!< QSPI_T::CTL: DUALIOEN Position */ +#define QSPI_CTL_DUALIOEN_Msk (0x1ul << QSPI_CTL_DUALIOEN_Pos) /*!< QSPI_T::CTL: DUALIOEN Mask */ + +#define QSPI_CTL_QUADIOEN_Pos (22) /*!< QSPI_T::CTL: QUADIOEN Position */ +#define QSPI_CTL_QUADIOEN_Msk (0x1ul << QSPI_CTL_QUADIOEN_Pos) /*!< QSPI_T::CTL: QUADIOEN Mask */ + +#define QSPI_CLKDIV_DIVIDER_Pos (0) /*!< QSPI_T::CLKDIV: DIVIDER Position */ +#define QSPI_CLKDIV_DIVIDER_Msk (0x1fful << QSPI_CLKDIV_DIVIDER_Pos) /*!< QSPI_T::CLKDIV: DIVIDER Mask */ + +#define QSPI_SSCTL_SS_Pos (0) /*!< QSPI_T::SSCTL: SS Position */ +#define QSPI_SSCTL_SS_Msk (0x1ul << QSPI_SSCTL_SS_Pos) /*!< QSPI_T::SSCTL: SS Mask */ + +#define QSPI_SSCTL_SSACTPOL_Pos (2) /*!< QSPI_T::SSCTL: SSACTPOL Position */ +#define QSPI_SSCTL_SSACTPOL_Msk (0x1ul << QSPI_SSCTL_SSACTPOL_Pos) /*!< QSPI_T::SSCTL: SSACTPOL Mask */ + +#define QSPI_SSCTL_AUTOSS_Pos (3) /*!< QSPI_T::SSCTL: AUTOSS Position */ +#define QSPI_SSCTL_AUTOSS_Msk (0x1ul << QSPI_SSCTL_AUTOSS_Pos) /*!< QSPI_T::SSCTL: AUTOSS Mask */ + +#define QSPI_SSCTL_SLV3WIRE_Pos (4) /*!< QSPI_T::SSCTL: SLV3WIRE Position */ +#define QSPI_SSCTL_SLV3WIRE_Msk (0x1ul << QSPI_SSCTL_SLV3WIRE_Pos) /*!< QSPI_T::SSCTL: SLV3WIRE Mask */ + +#define QSPI_SSCTL_SLVTOIEN_Pos (5) /*!< QSPI_T::SSCTL: SLVTOIEN Position */ +#define QSPI_SSCTL_SLVTOIEN_Msk (0x1ul << QSPI_SSCTL_SLVTOIEN_Pos) /*!< QSPI_T::SSCTL: SLVTOIEN Mask */ + +#define QSPI_SSCTL_SLVTORST_Pos (6) /*!< QSPI_T::SSCTL: SLVTORST Position */ +#define QSPI_SSCTL_SLVTORST_Msk (0x1ul << QSPI_SSCTL_SLVTORST_Pos) /*!< QSPI_T::SSCTL: SLVTORST Mask */ + +#define QSPI_SSCTL_SLVBEIEN_Pos (8) /*!< QSPI_T::SSCTL: SLVBEIEN Position */ +#define QSPI_SSCTL_SLVBEIEN_Msk (0x1ul << QSPI_SSCTL_SLVBEIEN_Pos) /*!< QSPI_T::SSCTL: SLVBEIEN Mask */ + +#define QSPI_SSCTL_SLVURIEN_Pos (9) /*!< QSPI_T::SSCTL: SLVURIEN Position */ +#define QSPI_SSCTL_SLVURIEN_Msk (0x1ul << QSPI_SSCTL_SLVURIEN_Pos) /*!< QSPI_T::SSCTL: SLVURIEN Mask */ + +#define QSPI_SSCTL_SSACTIEN_Pos (12) /*!< QSPI_T::SSCTL: SSACTIEN Position */ +#define QSPI_SSCTL_SSACTIEN_Msk (0x1ul << QSPI_SSCTL_SSACTIEN_Pos) /*!< QSPI_T::SSCTL: SSACTIEN Mask */ + +#define QSPI_SSCTL_SSINAIEN_Pos (13) /*!< QSPI_T::SSCTL: SSINAIEN Position */ +#define QSPI_SSCTL_SSINAIEN_Msk (0x1ul << QSPI_SSCTL_SSINAIEN_Pos) /*!< QSPI_T::SSCTL: SSINAIEN Mask */ + +#define QSPI_SSCTL_SLVTOCNT_Pos (16) /*!< QSPI_T::SSCTL: SLVTOCNT Position */ +#define QSPI_SSCTL_SLVTOCNT_Msk (0xfffful << QSPI_SSCTL_SLVTOCNT_Pos) /*!< QSPI_T::SSCTL: SLVTOCNT Mask */ + +#define QSPI_PDMACTL_TXPDMAEN_Pos (0) /*!< QSPI_T::PDMACTL: TXPDMAEN Position */ +#define QSPI_PDMACTL_TXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_TXPDMAEN_Pos) /*!< QSPI_T::PDMACTL: TXPDMAEN Mask */ + +#define QSPI_PDMACTL_RXPDMAEN_Pos (1) /*!< QSPI_T::PDMACTL: RXPDMAEN Position */ +#define QSPI_PDMACTL_RXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_RXPDMAEN_Pos) /*!< QSPI_T::PDMACTL: RXPDMAEN Mask */ + +#define QSPI_PDMACTL_PDMARST_Pos (2) /*!< QSPI_T::PDMACTL: PDMARST Position */ +#define QSPI_PDMACTL_PDMARST_Msk (0x1ul << QSPI_PDMACTL_PDMARST_Pos) /*!< QSPI_T::PDMACTL: PDMARST Mask */ + +#define QSPI_FIFOCTL_RXRST_Pos (0) /*!< QSPI_T::FIFOCTL: RXRST Position */ +#define QSPI_FIFOCTL_RXRST_Msk (0x1ul << QSPI_FIFOCTL_RXRST_Pos) /*!< QSPI_T::FIFOCTL: RXRST Mask */ + +#define QSPI_FIFOCTL_TXRST_Pos (1) /*!< QSPI_T::FIFOCTL: TXRST Position */ +#define QSPI_FIFOCTL_TXRST_Msk (0x1ul << QSPI_FIFOCTL_TXRST_Pos) /*!< QSPI_T::FIFOCTL: TXRST Mask */ + +#define QSPI_FIFOCTL_RXTHIEN_Pos (2) /*!< QSPI_T::FIFOCTL: RXTHIEN Position */ +#define QSPI_FIFOCTL_RXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTHIEN_Pos) /*!< QSPI_T::FIFOCTL: RXTHIEN Mask */ + +#define QSPI_FIFOCTL_TXTHIEN_Pos (3) /*!< QSPI_T::FIFOCTL: TXTHIEN Position */ +#define QSPI_FIFOCTL_TXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_TXTHIEN_Pos) /*!< QSPI_T::FIFOCTL: TXTHIEN Mask */ + +#define QSPI_FIFOCTL_RXTOIEN_Pos (4) /*!< QSPI_T::FIFOCTL: RXTOIEN Position */ +#define QSPI_FIFOCTL_RXTOIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTOIEN_Pos) /*!< QSPI_T::FIFOCTL: RXTOIEN Mask */ + +#define QSPI_FIFOCTL_RXOVIEN_Pos (5) /*!< QSPI_T::FIFOCTL: RXOVIEN Position */ +#define QSPI_FIFOCTL_RXOVIEN_Msk (0x1ul << QSPI_FIFOCTL_RXOVIEN_Pos) /*!< QSPI_T::FIFOCTL: RXOVIEN Mask */ + +#define QSPI_FIFOCTL_TXUFPOL_Pos (6) /*!< QSPI_T::FIFOCTL: TXUFPOL Position */ +#define QSPI_FIFOCTL_TXUFPOL_Msk (0x1ul << QSPI_FIFOCTL_TXUFPOL_Pos) /*!< QSPI_T::FIFOCTL: TXUFPOL Mask */ + +#define QSPI_FIFOCTL_TXUFIEN_Pos (7) /*!< QSPI_T::FIFOCTL: TXUFIEN Position */ +#define QSPI_FIFOCTL_TXUFIEN_Msk (0x1ul << QSPI_FIFOCTL_TXUFIEN_Pos) /*!< QSPI_T::FIFOCTL: TXUFIEN Mask */ + +#define QSPI_FIFOCTL_RXFBCLR_Pos (8) /*!< QSPI_T::FIFOCTL: RXFBCLR Position */ +#define QSPI_FIFOCTL_RXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_RXFBCLR_Pos) /*!< QSPI_T::FIFOCTL: RXFBCLR Mask */ + +#define QSPI_FIFOCTL_TXFBCLR_Pos (9) /*!< QSPI_T::FIFOCTL: TXFBCLR Position */ +#define QSPI_FIFOCTL_TXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_TXFBCLR_Pos) /*!< QSPI_T::FIFOCTL: TXFBCLR Mask */ + +#define QSPI_FIFOCTL_RXTH_Pos (24) /*!< QSPI_T::FIFOCTL: RXTH Position */ +#define QSPI_FIFOCTL_RXTH_Msk (0x7ul << QSPI_FIFOCTL_RXTH_Pos) /*!< QSPI_T::FIFOCTL: RXTH Mask */ + +#define QSPI_FIFOCTL_TXTH_Pos (28) /*!< QSPI_T::FIFOCTL: TXTH Position */ +#define QSPI_FIFOCTL_TXTH_Msk (0x7ul << QSPI_FIFOCTL_TXTH_Pos) /*!< QSPI_T::FIFOCTL: TXTH Mask */ + +#define QSPI_STATUS_BUSY_Pos (0) /*!< QSPI_T::STATUS: BUSY Position */ +#define QSPI_STATUS_BUSY_Msk (0x1ul << QSPI_STATUS_BUSY_Pos) /*!< QSPI_T::STATUS: BUSY Mask */ + +#define QSPI_STATUS_UNITIF_Pos (1) /*!< QSPI_T::STATUS: UNITIF Position */ +#define QSPI_STATUS_UNITIF_Msk (0x1ul << QSPI_STATUS_UNITIF_Pos) /*!< QSPI_T::STATUS: UNITIF Mask */ + +#define QSPI_STATUS_SSACTIF_Pos (2) /*!< QSPI_T::STATUS: SSACTIF Position */ +#define QSPI_STATUS_SSACTIF_Msk (0x1ul << QSPI_STATUS_SSACTIF_Pos) /*!< QSPI_T::STATUS: SSACTIF Mask */ + +#define QSPI_STATUS_SSINAIF_Pos (3) /*!< QSPI_T::STATUS: SSINAIF Position */ +#define QSPI_STATUS_SSINAIF_Msk (0x1ul << QSPI_STATUS_SSINAIF_Pos) /*!< QSPI_T::STATUS: SSINAIF Mask */ + +#define QSPI_STATUS_SSLINE_Pos (4) /*!< QSPI_T::STATUS: SSLINE Position */ +#define QSPI_STATUS_SSLINE_Msk (0x1ul << QSPI_STATUS_SSLINE_Pos) /*!< QSPI_T::STATUS: SSLINE Mask */ + +#define QSPI_STATUS_SLVTOIF_Pos (5) /*!< QSPI_T::STATUS: SLVTOIF Position */ +#define QSPI_STATUS_SLVTOIF_Msk (0x1ul << QSPI_STATUS_SLVTOIF_Pos) /*!< QSPI_T::STATUS: SLVTOIF Mask */ + +#define QSPI_STATUS_SLVBEIF_Pos (6) /*!< QSPI_T::STATUS: SLVBEIF Position */ +#define QSPI_STATUS_SLVBEIF_Msk (0x1ul << QSPI_STATUS_SLVBEIF_Pos) /*!< QSPI_T::STATUS: SLVBEIF Mask */ + +#define QSPI_STATUS_SLVURIF_Pos (7) /*!< QSPI_T::STATUS: SLVURIF Position */ +#define QSPI_STATUS_SLVURIF_Msk (0x1ul << QSPI_STATUS_SLVURIF_Pos) /*!< QSPI_T::STATUS: SLVURIF Mask */ + +#define QSPI_STATUS_RXEMPTY_Pos (8) /*!< QSPI_T::STATUS: RXEMPTY Position */ +#define QSPI_STATUS_RXEMPTY_Msk (0x1ul << QSPI_STATUS_RXEMPTY_Pos) /*!< QSPI_T::STATUS: RXEMPTY Mask */ + +#define QSPI_STATUS_RXFULL_Pos (9) /*!< QSPI_T::STATUS: RXFULL Position */ +#define QSPI_STATUS_RXFULL_Msk (0x1ul << QSPI_STATUS_RXFULL_Pos) /*!< QSPI_T::STATUS: RXFULL Mask */ + +#define QSPI_STATUS_RXTHIF_Pos (10) /*!< QSPI_T::STATUS: RXTHIF Position */ +#define QSPI_STATUS_RXTHIF_Msk (0x1ul << QSPI_STATUS_RXTHIF_Pos) /*!< QSPI_T::STATUS: RXTHIF Mask */ + +#define QSPI_STATUS_RXOVIF_Pos (11) /*!< QSPI_T::STATUS: RXOVIF Position */ +#define QSPI_STATUS_RXOVIF_Msk (0x1ul << QSPI_STATUS_RXOVIF_Pos) /*!< QSPI_T::STATUS: RXOVIF Mask */ + +#define QSPI_STATUS_RXTOIF_Pos (12) /*!< QSPI_T::STATUS: RXTOIF Position */ +#define QSPI_STATUS_RXTOIF_Msk (0x1ul << QSPI_STATUS_RXTOIF_Pos) /*!< QSPI_T::STATUS: RXTOIF Mask */ + +#define QSPI_STATUS_QSPIENSTS_Pos (15) /*!< QSPI_T::STATUS: QSPIENSTS Position */ +#define QSPI_STATUS_QSPIENSTS_Msk (0x1ul << QSPI_STATUS_QSPIENSTS_Pos) /*!< QSPI_T::STATUS: QSPIENSTS Mask */ + +#define QSPI_STATUS_TXEMPTY_Pos (16) /*!< QSPI_T::STATUS: TXEMPTY Position */ +#define QSPI_STATUS_TXEMPTY_Msk (0x1ul << QSPI_STATUS_TXEMPTY_Pos) /*!< QSPI_T::STATUS: TXEMPTY Mask */ + +#define QSPI_STATUS_TXFULL_Pos (17) /*!< QSPI_T::STATUS: TXFULL Position */ +#define QSPI_STATUS_TXFULL_Msk (0x1ul << QSPI_STATUS_TXFULL_Pos) /*!< QSPI_T::STATUS: TXFULL Mask */ + +#define QSPI_STATUS_TXTHIF_Pos (18) /*!< QSPI_T::STATUS: TXTHIF Position */ +#define QSPI_STATUS_TXTHIF_Msk (0x1ul << QSPI_STATUS_TXTHIF_Pos) /*!< QSPI_T::STATUS: TXTHIF Mask */ + +#define QSPI_STATUS_TXUFIF_Pos (19) /*!< QSPI_T::STATUS: TXUFIF Position */ +#define QSPI_STATUS_TXUFIF_Msk (0x1ul << QSPI_STATUS_TXUFIF_Pos) /*!< QSPI_T::STATUS: TXUFIF Mask */ + +#define QSPI_STATUS_TXRXRST_Pos (23) /*!< QSPI_T::STATUS: TXRXRST Position */ +#define QSPI_STATUS_TXRXRST_Msk (0x1ul << QSPI_STATUS_TXRXRST_Pos) /*!< QSPI_T::STATUS: TXRXRST Mask */ + +#define QSPI_STATUS_RXCNT_Pos (24) /*!< QSPI_T::STATUS: RXCNT Position */ +#define QSPI_STATUS_RXCNT_Msk (0xful << QSPI_STATUS_RXCNT_Pos) /*!< QSPI_T::STATUS: RXCNT Mask */ + +#define QSPI_STATUS_TXCNT_Pos (28) /*!< QSPI_T::STATUS: TXCNT Position */ +#define QSPI_STATUS_TXCNT_Msk (0xful << QSPI_STATUS_TXCNT_Pos) /*!< QSPI_T::STATUS: TXCNT Mask */ + +#define QSPI_TX_TX_Pos (0) /*!< QSPI_T::TX: TX Position */ +#define QSPI_TX_TX_Msk (0xfffffffful << QSPI_TX_TX_Pos) /*!< QSPI_T::TX: TX Mask */ + +#define QSPI_RX_RX_Pos (0) /*!< QSPI_T::RX: RX Position */ +#define QSPI_RX_RX_Msk (0xfffffffful << QSPI_RX_RX_Pos) /*!< QSPI_T::RX: RX Mask */ + + +/**@}*/ /* QSPI_CONST */ +/**@}*/ /* end of QSPI register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __QSPI_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/rtc_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/rtc_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..644d8e48566295a70d6f09461e3afe905f541f96 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/rtc_reg.h @@ -0,0 +1,1274 @@ +/**************************************************************************//** + * @file rtc_reg.h + * @version V1.00 + * @brief RTC register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __RTC_REG_H__ +#define __RTC_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup RTC Real Time Clock Controller(RTC) + Memory Mapped Structure for RTC Controller +@{ */ + +typedef struct +{ + + + /** + * @var RTC_T::INIT + * Offset: 0x00 RTC Initiation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |INIT_ACTIVE|RTC Active Status (Read Only) + * | | |0 = RTC is at reset state. + * | | |1 = RTC is at normal active state. + * |[31:1] |INIT |RTC Initiation (Write Only) + * | | |When RTC block is powered on, RTC is at reset state + * | | |User has to write a number (0xa5eb1357) to INIT to make RTC leaving reset state + * | | |Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently. + * | | |The INIT is a write-only field and read value will be always 0. + * @var RTC_T::RWEN + * Offset: 0x04 RTC Access Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[16] |RWENF |RTC Register Access Enable Flag (Read Only) + * | | |0 = RTC register read/write Disabled. + * | | |1 = RTC register read/write Enabled. + * | | |Note: RWENF will be mask to 0 during RTCBUSY is 1, and first turn on RTCCKEN (CLK_APBCLK[1]) also. + * |[24] |RTCBUSY |RTC Write Busy Flag + * | | |This bit indicates RTC registers are writable or not. + * | | |0: RTC registers are writable. + * | | |1: RTC registers can't write, RTC under Busy Status. + * | | |Note: RTCBUSY flag will be set when execute write RTC register command exceed 6 times within 1120 PCLK cycles. + * @var RTC_T::FREQADJ + * Offset: 0x08 RTC Frequency Compensation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[21:0] |FREQADJ |Frequency Compensation Register (M480) + * | | |User must to get actual LXT frequency for RTC application. + * | | |FCR = 0x200000 * (32768 / LXT frequency). + * | | |Note: This formula is suitable only when RTC clock source is from LXT, RTCSEL (CLK_CLKSEL3[8]) is 0. + * |[5:0] |FRACTION |Fraction Part (M480LD) + * | | |Formula: FRACTION = (fraction part of detected value) X 64. + * | | |Note: Digit in FCR must be expressed as hexadecimal number. + * |[12:8] |INTEGER |Integer Part (M480LD) + * | | |00000 = Integer part of detected value is 32752. + * | | |00001 = Integer part of detected value is 32753. + * | | |00010 = Integer part of detected value is 32754. + * | | |00011 = Integer part of detected value is 32755. + * | | |00100 = Integer part of detected value is 32756. + * | | |00101 = Integer part of detected value is 32757. + * | | |00110 = Integer part of detected value is 32758. + * | | |00111 = Integer part of detected value is 32759. + * | | |01000 = Integer part of detected value is 32760. + * | | |01001 = Integer part of detected value is 32761. + * | | |01010 = Integer part of detected value is 32762. + * | | |01011 = Integer part of detected value is 32763. + * | | |01100 = Integer part of detected value is 32764. + * | | |01101 = Integer part of detected value is 32765. + * | | |01110 = Integer part of detected value is 32766. + * | | |01111 = Integer part of detected value is 32767. + * | | |10000 = Integer part of detected value is 32768. + * | | |10001 = Integer part of detected value is 32769. + * | | |10010 = Integer part of detected value is 32770. + * | | |10011 = Integer part of detected value is 32771. + * | | |10100 = Integer part of detected value is 32772. + * | | |10101 = Integer part of detected value is 32773. + * | | |10110 = Integer part of detected value is 32774. + * | | |10111 = Integer part of detected value is 32775. + * | | |11000 = Integer part of detected value is 32776. + * | | |11001 = Integer part of detected value is 32777. + * | | |11010 = Integer part of detected value is 32778. + * | | |11011 = Integer part of detected value is 32779. + * | | |11100 = Integer part of detected value is 32780. + * | | |11101 = Integer part of detected value is 32781. + * | | |11110 = Integer part of detected value is 32782. + * | | |11111 = Integer part of detected value is 32783. + * |[31] |FCR_BUSY |Frequency Compensation Register Write Operation Busy (Read Only) (M480LD) + * | | |0 = The new register write operation is acceptable. + * | | |1 = The last write operation is in progress and new register write operation prohibited. + * | | |Note: This bit is only used when DYN_COMP_EN(RTC_CLKFMT[16]) enabled. + * @var RTC_T::TIME + * Offset: 0x0C RTC Time Loading Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |SEC |1-Sec Time Digit (0~9) + * |[6:4] |TENSEC |10-Sec Time Digit (0~5) + * |[11:8] |MIN |1-Min Time Digit (0~9) + * |[14:12] |TENMIN |10-Min Time Digit (0~5) + * |[19:16] |HR |1-Hour Time Digit (0~9) + * |[21:20] |TENHR |10-Hour Time Digit (0~2) + * | | |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication + * | | |(If RTC_TIME[21] is 1, it indicates PM time message). + * @var RTC_T::CAL + * Offset: 0x10 RTC Calendar Loading Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |DAY |1-Day Calendar Digit (0~9) + * |[5:4] |TENDAY |10-Day Calendar Digit (0~3) + * |[11:8] |MON |1-Month Calendar Digit (0~9) + * |[12] |TENMON |10-Month Calendar Digit (0~1) + * |[19:16] |YEAR |1-Year Calendar Digit (0~9) + * |[23:20] |TENYEAR |10-Year Calendar Digit (0~9) + * @var RTC_T::CLKFMT + * Offset: 0x14 RTC Time Scale Selection Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |24HEN |24-hour / 12-hour Time Scale Selection + * | | |Indicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale + * | | |0 = 12-hour time scale with AM and PM indication selected. + * | | |1 = 24-hour time scale selected. + * @var RTC_T::WEEKDAY + * Offset: 0x18 RTC Day of the Week Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |WEEKDAY |Day of the Week Register + * | | |000 = Sunday. + * | | |001 = Monday. + * | | |010 = Tuesday. + * | | |011 = Wednesday. + * | | |100 = Thursday. + * | | |101 = Friday. + * | | |110 = Saturday. + * | | |111 = Reserved. + * @var RTC_T::TALM + * Offset: 0x1C RTC Time Alarm Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |SEC |1-Sec Time Digit of Alarm Setting (0~9) + * |[6:4] |TENSEC |10-Sec Time Digit of Alarm Setting (0~5) + * |[11:8] |MIN |1-Min Time Digit of Alarm Setting (0~9) + * |[14:12] |TENMIN |10-Min Time Digit of Alarm Setting (0~5) + * |[19:16] |HR |1-Hour Time Digit of Alarm Setting (0~9) + * |[21:20] |TENHR |10-Hour Time Digit of Alarm Setting (0~2) + * | | |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication + * | | |(If RTC_TIME[21] is 1, it indicates PM time message). + * @var RTC_T::CALM + * Offset: 0x20 RTC Calendar Alarm Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |DAY |1-Day Calendar Digit of Alarm Setting (0~9) + * |[5:4] |TENDAY |10-Day Calendar Digit of Alarm Setting (0~3) + * |[11:8] |MON |1-Month Calendar Digit of Alarm Setting (0~9) + * |[12] |TENMON |10-Month Calendar Digit of Alarm Setting (0~1) + * |[19:16] |YEAR |1-Year Calendar Digit of Alarm Setting (0~9) + * |[23:20] |TENYEAR |10-Year Calendar Digit of Alarm Setting (0~9) + * @var RTC_T::LEAPYEAR + * Offset: 0x24 RTC Leap Year Indicator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LEAPYEAR |Leap Year Indication Register (Read Only) + * | | |0 = This year is not a leap year. + * | | |1 = This year is leap year. + * @var RTC_T::INTEN + * Offset: 0x28 RTC Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ALMIEN |Alarm Interrupt Enable Bit + * | | |Set ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated. + * | | |0 = RTC Alarm interrupt Disabled. + * | | |1 = RTC Alarm interrupt Enabled. + * |[1] |TICKIEN |Time Tick Interrupt Enable Bit + * | | |Set TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated. + * | | |0 = RTC Time Tick interrupt Disabled. + * | | |1 = RTC Time Tick interrupt Enabled. + * |[8] |TAMP0IEN |Tamper 0 Interrupt Enable Bit + * | | |Set TAMP0IEN to 1 can also enable chip wake-up function when tamper 0 interrupt event is generated. + * | | |0 = Tamper 0 interrupt Disabled. + * | | |1 = Tamper 0 interrupt Enabled. + * |[9] |TAMP1IEN |Tamper 1 or Pair 0 Interrupt Enable Bit + * | | |Set TAMP1IEN to 1 can also enable chip wake-up function when tamper 1 interrupt event is generated. + * | | |0 = Tamper 1 or Pair 0 interrupt Disabled. + * | | |1 = Tamper 1 or Pair 0 interrupt Enabled. + * |[10] |TAMP2IEN |Tamper 2 Interrupt Enable Bit + * | | |Set TAMP2IEN to 1 can also enable chip wake-up function when tamper 2 interrupt event is generated. + * | | |0 = Tamper 2 interrupt Disabled. + * | | |1 = Tamper 2 interrupt Enabled. + * |[11] |TAMP3IEN |Tamper 3 or Pair 1 Interrupt Enable Bit + * | | |Set TAMP3IEN to 1 can also enable chip wake-up function when tamper 3 interrupt event is generated. + * | | |0 = Tamper 3 or Pair 1 interrupt Disabled. + * | | |1 = Tamper 3 or Pair 1 interrupt Enabled. + * |[12] |TAMP4IEN |Tamper 4 Interrupt Enable Bit + * | | |Set TAMP4IEN to 1 can also enable chip wake-up function when tamper 4 interrupt event is generated. + * | | |0 = Tamper 4 interrupt Disabled. + * | | |1 = Tamper 4 interrupt Enabled. + * |[13] |TAMP5IEN |Tamper 5 or Pair 2 Interrupt Enable Bit + * | | |Set TAMP5IEN to 1 can also enable chip wake-up function when tamper 5 interrupt event is generated. + * | | |0 = Tamper 5 or Pair 2 interrupt Disabled. + * | | |1 = Tamper 5 or Pair 2 interrupt Enabled. + * @var RTC_T::INTSTS + * Offset: 0x2C RTC Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ALMIF |RTC Alarm Interrupt Flag + * | | |0 = Alarm condition is not matched. + * | | |1 = Alarm condition is matched. + * | | |Note: Write 1 to clear this bit. + * |[1] |TICKIF |RTC Time Tick Interrupt Flag + * | | |0 = Tick condition does not occur. + * | | |1 = Tick condition occur. + * | | |Note: Write 1 to clear this bit. + * |[8] |TAMP0IF |Tamper 0 Interrupt Flag + * | | |This bit is set when TAMP0_PIN detected level non-equal TAMP0LV (RTC_TAMPCTL[9]). + * | | |0 = No Tamper 0 interrupt flag is generated. + * | | |1 = Tamper 0 interrupt flag is generated. + * | | |Note1: Write 1 to clear this bit. + * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. + * |[9] |TAMP1IF |Tamper 1 or Pair 0 Interrupt Flag + * | | |This bit is set when TAMP1_PIN detected level non-equal TAMP1LV (RTC_TAMPCTL[13]) + * | | |or TAMP0_PIN and TAMP1_PIN disconnected during DYNPR0EN (RTC_TAMPCTL[15]) is activated. + * | | |0 = No Tamper 1 or Pair 0 interrupt flag is generated. + * | | |1 = Tamper 1 or Pair 0 interrupt flag is generated. + * | | |Note1: Write 1 to clear this bit. + * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. + * |[10] |TAMP2IF |Tamper 2 Interrupt Flag + * | | |This bit is set when TAMP2_PIN detected level non-equal TAMP2LV (RTC_TAMPCTL[17]). + * | | |0 = No Tamper 2 interrupt flag is generated. + * | | |1 = Tamper 2 interrupt flag is generated. + * | | |Note1: Write 1 to clear this bit. + * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. + * |[11] |TAMP3IF |Tamper 3 or Pair 1 Interrupt Flag + * | | |This bit is set when TAMP3_PIN detected level non-equal TAMP3LV (RTC_TAMPCTL[21]) + * | | |or TAMP2_PIN and TAMP3_PIN disconnected during DYNPR1EN (RTC_TAMPCTL[23]) is activated + * | | |or TAMP0_PIN and TAMP3_PIN disconnected during DYNPR1EN (RTC_TAMPCTL[23]) and DYN1ISS (RTC_TAMPCTL[0]) are activated. + * | | |0 = No Tamper 3 or Pair 1 interrupt flag is generated. + * | | |1 = Tamper 3 or Pair 1 interrupt flag is generated. + * | | |Note1: Write 1 to clear this bit. + * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. + * |[12] |TAMP4IF |Tamper 4 Interrupt Flag + * | | |This bit is set when TAMP4_PIN detected level non-equal TAMP4LV (RTC_TAMPCTL[25]). + * | | |0 = No Tamper 4 interrupt flag is generated. + * | | |1 = Tamper 4 interrupt flag is generated. + * | | |Note1: Write 1 to clear this bit. + * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. + * |[13] |TAMP5IF |Tamper 5 or Pair 2 Interrupt Flag + * | | |This bit is set when TAMP5_PIN detected level non-equal TAMP5LV (RTC_TAMPCTL[29]) + * | | |or TAMP4_PIN and TAMP5_PIN disconnected during DYNPR2EN (RTC_TAMPCTL[31]) is activated + * | | |or TAMP0_PIN and TAMP5_PIN disconnected during DYNPR2EN (RTC_TAMPCTL[31]) and DYN2ISS (RTC_TAMPCTL[1]) are activated. + * | | |0 = No Tamper 5 or Pair 2 interrupt flag is generated. + * | | |1 = Tamper 5 or Pair 2 interrupt flag is generated. + * | | |Note1: Write 1 to clear this bit. + * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. + * @var RTC_T::TICK + * Offset: 0x30 RTC Time Tick Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |TICK |Time Tick Register + * | | |These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request. + * | | |000 = Time tick is 1 second. + * | | |001 = Time tick is 1/2 second. + * | | |010 = Time tick is 1/4 second. + * | | |011 = Time tick is 1/8 second. + * | | |100 = Time tick is 1/16 second. + * | | |101 = Time tick is 1/32 second. + * | | |110 = Time tick is 1/64 second. + * | | |111 = Time tick is 1/128 second. + * | | |Note: This register can be read back after the RTC register access enable bit RWENF (RTC_RWEN[16]) is active. + * @var RTC_T::TAMSK + * Offset: 0x34 RTC Time Alarm Mask Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSEC |Mask 1-Sec Time Digit of Alarm Setting (0~9) + * |[1] |MTENSEC |Mask 10-Sec Time Digit of Alarm Setting (0~5) + * |[2] |MMIN |Mask 1-Min Time Digit of Alarm Setting (0~9) + * |[3] |MTENMIN |Mask 10-Min Time Digit of Alarm Setting (0~5) + * |[4] |MHR |Mask 1-Hour Time Digit of Alarm Setting (0~9) + * |[5] |MTENHR |Mask 10-Hour Time Digit of Alarm Setting (0~2) + * @var RTC_T::CAMSK + * Offset: 0x38 RTC Calendar Alarm Mask Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MDAY |Mask 1-Day Calendar Digit of Alarm Setting (0~9) + * |[1] |MTENDAY |Mask 10-Day Calendar Digit of Alarm Setting (0~3) + * |[2] |MMON |Mask 1-Month Calendar Digit of Alarm Setting (0~9) + * |[3] |MTENMON |Mask 10-Month Calendar Digit of Alarm Setting (0~1) + * |[4] |MYEAR |Mask 1-Year Calendar Digit of Alarm Setting (0~9) + * |[5] |MTENYEAR |Mask 10-Year Calendar Digit of Alarm Setting (0~9) + * @var RTC_T::SPRCTL + * Offset: 0x3C RTC Spare Functional Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2] |SPRRWEN |Spare Register Enable Bit + * | | |0 = Spare register is Disabled. + * | | |1 = Spare register is Enabled. + * | | |Note: When spare register is disabled, RTC_SPR0 ~ RTC_SPR19 cannot be accessed. + * |[5] |SPRCSTS |SPR Clear Flag + * | | |This bit indicates if the RTC_SPR0 ~RTC_SPR19 content is cleared when specify tamper event is detected. + * | | |0 = Spare register content is not cleared. + * | | |1 = Spare register content is cleared. + * | | |Writes 1 to clear this bit. + * | | |Note: This bit keep 1 when RTC_INTSTS[13:8] not equal zero. + * @var RTC_T::SPR[20] + * Offset: 0x40 ~ 0x8C RTC Spare Register 0 ~ 19 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SPARE |Spare Register + * | | |This field is used to store back-up information defined by user. + * | | |This field will be cleared by hardware automatically once a tamper pin event is detected. + * | | |Before storing back-up information in to RTC_SPRx register, + * | | |user should check REWNF (RTC_RWEN[16]) is enabled. + * @var RTC_T::LXTCTL + * Offset: 0x100 RTC 32.768 kHz Oscillator Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:1] |GAIN |Oscillator Gain Option + * | | |User can select oscillator gain according to crystal external loading and operating temperature range + * | | |The larger gain value corresponding to stronger driving capability and higher power consumption. + * | | |00 = L0 mode. + * | | |01 = L1 mode. + * | | |10 = L2 mode. + * | | |11 = L3 mode. + * @var RTC_T::GPIOCTL0 + * Offset: 0x104 RTC GPIO Control 0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |OPMODE0 |IO Operation Mode + * | | |00 = PF.4 is input only mode, without pull-up resistor. + * | | |01 = PF.4 is output push pull mode. + * | | |10 = PF.4 is open drain mode. + * | | |11 = PF.4 is quasi-bidirectional mode with internal pull up. + * |[2] |DOUT0 |IO Output Data + * | | |0 = PF.4 output low. + * | | |1 = PF.4 output high. + * |[3] |CTLSEL0 |IO Pin State Backup Selection + * | | |When low speed 32 kHz oscillator is disabled, PF.4 pin (X32KO pin) can be used as GPIO function + * | | |User can program CTLSEL0 to decide PF.4 I/O function is controlled by system power domain GPIO module or + * | | |VBAT power domain RTC_GPIOCTL0 control register. + * | | |0 = PF.4 pin I/O function is controlled by GPIO module. + * | | |Hardware auto becomes CTLSEL0 = 1 when system power is turned off. + * | | |1 = PF.4 pin I/O function is controlled by VBAT power domain. + * | | |PF.4 pin function and I/O status are controlled by OPMODE0[1:0] and DOUT0 after CTLSEL0 is set to 1. + * | | |Note: CTLSEL0 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1. + * |[5:4] |PUSEL0 |IO Pull-up and Pull-down Enable + * | | |Determine PF.4 I/O pull-up or pull-down. + * | | |00 = PF.4 pull-up and pull-up disable. + * | | |01 = PF.4 pull-down enable. + * | | |10 = PF.4 pull-up enable. + * | | |11 = PF.4 pull-up and pull-up disable. + * | | |Note: + * | | |Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up control register only valid when OPMODE0 set as input tri-state and open-drain mode. + * | | |The independent pull-down control register only valid when OPMODE0 set as input tri-state mode. + * |[9:8] |OPMODE1 |IO Operation Mode + * | | |00 = PF.5 is input only mode, without pull-up resistor. + * | | |01 = PF.5 is output push pull mode. + * | | |10 = PF.5 is open drain mode. + * | | |11 = PF.5 is quasi-bidirectional mode with internal pull up. + * |[10] |DOUT1 |IO Output Data + * | | |0 = PF.5 output low. + * | | |1 = PF.5 output high. + * |[11] |CTLSEL1 |IO Pin State Backup Selection + * | | |When low speed 32 kHz oscillator is disabled, PF.5 pin (X32KI pin) can be used as GPIO function + * | | |User can program CTLSEL1 to decide PF.5 I/O function is controlled by system power domain GPIO module or + * | | |VBAT power domain RTC_GPIOCTL0 control register. + * | | |0 = PF.5 pin I/O function is controlled by GPIO module. + * | | |Hardware auto becomes CTLSEL1 = 1 when system power is turned off. + * | | |1 = PF.5 pin I/O function is controlled by VBAT power domain. + * | | |PF.5 pin function and I/O status are controlled by OPMODE1[1:0] and DOUT1 after CTLSEL1 is set to 1. + * | | |Note: CTLSEL1 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1. + * |[13:12] |PUSEL1 |IO Pull-up and Pull-down Enable + * | | |Determine PF.5 I/O pull-up or pull-down. + * | | |00 = PF.5 pull-up and pull-up disable. + * | | |01 = PF.5 pull-down enable. + * | | |10 = PF.5 pull-up enable. + * | | |11 = PF.5 pull-up and pull-up disable. + * | | |Note: + * | | |Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up control register only valid when OPMODE1 set as input tri-state and open-drain mode. + * | | |The independent pull-down control register only valid when OPMODE1 set as input tri-state mode. + * |[17:16] |OPMODE2 |IO Operation Mode + * | | |00 = PF.6 is input only mode, without pull-up resistor. + * | | |01 = PF.6 is output push pull mode. + * | | |10 = PF.6 is open drain mode. + * | | |11 = PF.6 is quasi-bidirectional mode with internal pull up. + * |[18] |DOUT2 |IO Output Data + * | | |0 = PF.6 output low. + * | | |1 = PF.6 output high. + * |[19] |CTLSEL2 |IO Pin State Backup Selection + * | | |When TAMP0EN is disabled, PF.6 pin (TAMPER0 pin) can be used as GPIO function + * | | |User can program CTLSEL2 to decide PF.6 I/O function is controlled by system power domain GPIO module or + * | | |VBAT power domain RTC_GPIOCTL0 control register. + * | | |0 = PF.6 pin I/O function is controlled by GPIO module. + * | | |Hardware auto becomes CTLSEL2 = 1 when system power is turned off. + * | | |1 = PF.6 pin I/O function is controlled by VBAT power domain. + * | | |PF.6 pin function and I/O status are controlled by OPMODE2[1:0] and DOUT2 after CTLSEL2 is set to 1. + * | | |Note: CTLSEL2 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1. + * |[21:20] |PUSEL2 |IO Pull-up and Pull-down Enable + * | | |Determine PF.6 I/O pull-up or pull-down. + * | | |00 = PF.6 pull-up and pull-up disable. + * | | |01 = PF.6 pull-down enable. + * | | |10 = PF.6 pull-up enable. + * | | |11 = PF.6 pull-up and pull-up disable. + * | | |Note1: + * | | |Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up control register only valid when OPMODE2 set as input tri-state and open-drain mode. + * | | |The independent pull-down control register only valid when OPMODE2 set as input tri-state mode. + * |[25:24] |OPMODE3 |IO Operation Mode + * | | |00 = PF.7 is input only mode, without pull-up resistor. + * | | |01 = PF.7 is output push pull mode. + * | | |10 = PF.7 is open drain mode. + * | | |11 = PF.7 is quasi-bidirectional mode. + * |[26] |DOUT3 |IO Output Data + * | | |0 = PF.7 output low. + * | | |1 = PF.7 output high. + * |[27] |CTLSEL3 |IO Pin State Backup Selection + * | | |When TAMP1EN is disabled, PF.7 pin (TAMPER1 pin) can be used as GPIO function + * | | |User can program CTLSEL3 to decide PF.7 I/O function is controlled by system power domain GPIO module or + * | | |VBAT power domain RTC_GPIOCTL0 control register. + * | | |0 = PF.7 pin I/O function is controlled by GPIO module. + * | | |Hardware auto becomes CTLSEL3 = 1 when system power is turned off. + * | | |1 = PF.7 pin I/O function is controlled by VBAT power domain. + * | | |PF.7 pin function and I/O status are controlled by OPMODE3[1:0] and DOUT3 after CTLSEL3 is set to 1. + * | | |Note: CTLSEL3 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1. + * |[29:28] |PUSEL3 |IO Pull-up and Pull-down Enable + * | | |Determine PF.7 I/O pull-up or pull-down. + * | | |00 = PF.7 pull-up and pull-down disable. + * | | |01 = PF.7 pull-down enable. + * | | |10 = PF.7 pull-up enable. + * | | |11 = PF.7 pull-up and pull-down disable. + * | | |Note: + * | | |Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up control register only valid when OPMODE3 set as input tri-state and open-drain mode. + * | | |The independent pull-down control register only valid when OPMODE3 set as input tri-state mode. + * @var RTC_T::GPIOCTL1 + * Offset: 0x108 RTC GPIO Control 1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |OPMODE4 |IO Operation Mode + * | | |00 = PF.8 is input only mode, without pull-up resistor. + * | | |01 = PF.8 is output push pull mode. + * | | |10 = PF.8 is open drain mode. + * | | |11 = PF.8 is quasi-bidirectional mode. + * |[2] |DOUT4 |IO Output Data + * | | |0 = PF.8 output low. + * | | |1 = PF.8 output high. + * |[3] |CTLSEL4 |IO Pin State Backup Selection + * | | |When TAMP2EN is disabled, PF.8 pin (TAMPER2 pin) can be used as GPIO function + * | | |User can program CTLSEL4 to decide PF.8 I/O function is controlled by system power domain GPIO module or + * | | |VBAT power domain RTC_GPIOCTL1 control register. + * | | |0 = PF.8 pin I/O function is controlled by GPIO module. + * | | |Hardware auto becomes CTLSEL4 = 1 when system power is turned off. + * | | |1 = PF.8 pin I/O function is controlled by VBAT power domain. + * | | |PF.8 pin function and I/O status are controlled by OPMODE4[1:0] and DOUT4 after CTLSEL4 is set to 1. + * | | |Note: CTLSEL4 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1. + * |[5:4] |PUSEL4 |IO Pull-up and Pull-down Enable + * | | |Determine PF.8 I/O pull-up or pull-down. + * | | |00 = PF.8 pull-up and pull-down disable. + * | | |01 = PF.8 pull-down enable. + * | | |10 = PF.8 pull-up enable. + * | | |11 = PF.8 pull-up and pull-down disable. + * | | |Note: + * | | |Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up control register only valid when OPMODE4 set as input tri-state and open-drain mode. + * | | |The independent pull-down control register only valid when OPMODE4 set as input tri-state mode. + * |[9:8] |OPMODE5 |IO Operation Mode + * | | |00 = PF.9 is input only mode, without pull-up resistor. + * | | |01 = PF.9 is output push pull mode. + * | | |10 = PF.9 is open drain mode. + * | | |11 = PF.9 is quasi-bidirectional mode. + * |[10] |DOUT5 |IO Output Data + * | | |0 = PF.9 output low. + * | | |1 = PF.9 output high. + * |[11] |CTLSEL5 |IO Pin State Backup Selection + * | | |When TAMP3EN is disabled, PF.9 pin (TAMPER3 pin) can be used as GPIO function + * | | |User can program CTLSEL5 to decide PF.9 I/O function is controlled by system power domain GPIO module or + * | | |VBAT power domain RTC_GPIOCTL1 control register. + * | | |0 = PF.9 pin I/O function is controlled by GPIO module. + * | | |Hardware auto becomes CTLSEL5 = 1 when system power is turned off. + * | | |1 = PF.9 pin I/O function is controlled by VBAT power domain. + * | | |PF.9 pin function and I/O status are controlled by OPMODE5[1:0] and DOUT5 after CTLSEL5 is set to 1. + * | | |Note: CTLSEL5 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1. + * |[13:12] |PUSEL5 |IO Pull-up and Pull-down Enable + * | | |Determine PF.9 I/O pull-up or pull-down. + * | | |00 = PF.9 pull-up and pull-down disable. + * | | |01 = PF.9 pull-down enable. + * | | |10 = PF.9 pull-up enable. + * | | |11 = PF.9 pull-up and pull-down disable. + * | | |Note: + * | | |Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up control register only valid when OPMODE5 set as input tri-state and open-drain mode. + * | | |The independent pull-down control register only valid when OPMODE5 set as input tri-state mode. + * |[17:16] |OPMODE6 |IO Operation Mode + * | | |00 = PF.10 is input only mode, without pull-up resistor. + * | | |01 = PF.10 is output push pull mode. + * | | |10 = PF.10 is open drain mode. + * | | |11 = PF.10 is quasi-bidirectional mode. + * |[18] |DOUT6 |IO Output Data + * | | |0 = PF.10 output low. + * | | |1 = PF.10 output high. + * |[19] |CTLSEL6 |IO Pin State Backup Selection + * | | |When TAMP4EN is disabled, PF.10 pin (TAMPER4 pin) can be used as GPIO function + * | | |User can program CTLSEL6 to decide PF.10 I/O function is controlled by system power domain GPIO module or + * | | |VBAT power domain RTC_GPIOCTL1 control register. + * | | |0 = PF.10 pin I/O function is controlled by GPIO module. + * | | |Hardware auto becomes CTLSEL6 = 1 when system power is turned off. + * | | |1 = PF.10 pin I/O function is controlled by VBAT power domain. + * | | |PF.10 pin function and I/O status are controlled by OPMODE6[1:0] and DOUT6 after CTLSEL6 is set to 1. + * | | |Note: CTLSEL6 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1. + * |[21:20] |PUSEL6 |IO Pull-up and Pull-down Enable + * | | |Determine PF.10 I/O pull-up or pull-down. + * | | |00 = PF.10 pull-up and pull-down disable. + * | | |01 = PF.10 pull-down enable. + * | | |10 = PF.10 pull-up enable. + * | | |11 = PF.10 pull-up and pull-down disable. + * | | |Note: + * | | |Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up control register only valid when OPMODE6 set as input tri-state and open-drain mode. + * | | |The independent pull-down control register only valid when OPMODE6 set as input tri-state mode. + * |[25:24] |OPMODE7 |IO Operation Mode + * | | |00 = PF.11 is input only mode, without pull-up resistor. + * | | |01 = PF.11 is output push pull mode. + * | | |10 = PF.11 is open drain mode. + * | | |11 = PF.11 is quasi-bidirectional mode. + * |[26] |DOUT7 |IO Output Data + * | | |0 = PF.11 output low. + * | | |1 = PF.11 output high. + * |[27] |CTLSEL7 |IO Pin State Backup Selection + * | | |When TAMP5EN is disabled, PF.11 pin (TAMPER5 pin) can be used as GPIO function + * | | |User can program CTLSEL7 to decide PF.11 I/O function is controlled by system power domain GPIO module or + * | | |VBAT power domain RTC_GPIOCTL1 control register. + * | | |0 = PF.11 pin I/O function is controlled by GPIO module. + * | | |Hardware auto becomes CTLSEL7 = 1 when system power is turned off. + * | | |1 = PF.11 pin I/O function is controlled by VBAT power domain. + * | | |PF.11 pin function and I/O status are controlled by OPMODE7[1:0] and DOUT7 after CTLSEL7 is set to 1. + * | | |Note: CTLSEL7 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1. + * |[29:28] |PUSEL7 |IO Pull-up and Pull-down Enable + * | | |Determine PF.11 I/O pull-up or pull-down. + * | | |00 = PF.11 pull-up and pull-down disable. + * | | |01 = PF.11 pull-down enable. + * | | |10 = PF.11 pull-up enable. + * | | |11 = PF.11 pull-up and pull-down disable. + * | | |Note: + * | | |Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up control register only valid when OPMODE7 set as input tri-state and open-drain mode. + * | | |The independent pull-down control register only valid when OPMODE7 set as input tri-state mode. + * @var RTC_T::DSTCTL + * Offset: 0x110 RTC Daylight Saving Time Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADDHR |Add 1 Hour + * | | |0 = No effect. + * | | |1 = Indicates RTC hour digit has been added one hour for summer time change. + * |[1] |SUBHR |Subtract 1 Hour + * | | |0 = No effect. + * | | |1 = Indicates RTC hour digit has been subtracted one hour for winter time change. + * |[2] |DSBAK |Daylight Saving Back + * | | |0= Normal mode. + * | | |1= Daylight saving mode. + * @var RTC_T::TAMPCTL + * Offset: 0x120 RTC Tamper Pin Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DYN1ISS |Dynamic Pair 1 Input Source Select + * | | |This bit determine Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode. + * | | |0 = Tamper input is from Tamper 2. + * | | |1 = Tamper input is from Tamper 0. + * | | |Note: This bit has effect only when DYNPR1EN (RTC_TAMPCTL[16]) and DYNPR0EN (RTC_TAMPCTL[15]) are set + * |[1] |DYN2ISS |Dynamic Pair 2 Input Source Select + * | | |This bit determine Tamper 5 input is from Tamper 4 or Tamper 0 in dynamic mode. + * | | |0 = Tamper input is from Tamper 4. + * | | |1 = Tamper input is from Tamper 0. + * | | |Note: This bit has effect only when DYNPR2EN (RTC_TAMPCTL[24]) and DYNPR0EN (RTC_TAMPCTL[15]) are set + * |[3:2] |DYNSRC |Dynamic Reference Pattern + * | | |This fields determine the new reference pattern when current pattern run out in dynamic pair mode. + * | | |00 or 10 = The new reference pattern is generated by random number generator when the reference pattern run out. + * | | |01 = The new reference pattern is repeated previous random value when the reference pattern run out. + * | | |11 = The new reference pattern is repeated from SEED (RTC_TAMPSEED[31:0]) when the reference pattern run out. + * | | |Note: After revise this bit, the SEEDRLD (RTC_TAMPCTL[4]) should be set. + * |[4] |SEEDRLD |Reload New Seed for PRNG Engine + * | | |Setting this bit, the tamper configuration will be reload. + * | | |0 = Generating key based on the current seed. + * | | |1 = Reload new seed. + * | | |Note: Before set this bit, the tamper configuration should be set to complete. + * |[7:5] |DYNRATE |Dynamic Change Rate + * | | |This item is choice the dynamic tamper output change rate. + * | | |000 = 210 * RTC_CLK. + * | | |001 = 211 * RTC_CLK. + * | | |010 = 212 * RTC_CLK. + * | | |011 = 213 * RTC_CLK. + * | | |100 = 214 * RTC_CLK. + * | | |101 = 215 * RTC_CLK. + * | | |110 = 216 * RTC_CLK. + * | | |111 = 217 * RTC_CLK. + * | | |Note: After revise this field, set SEEDRLD (RTC_TAMPCTL[4]) can reload change rate immediately. + * |[8] |TAMP0EN |Tamper0 Detect Enable Bit + * | | |0 = Tamper 0 detect Disabled. + * | | |1 = Tamper 0 detect Enabled. + * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock. + * |[9] |TAMP0LV |Tamper 0 Level + * | | |This bit depend on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[10] |TAMP0DBEN |Tamper 0 De-bounce Enable Bit + * | | |0 = Tamper 0 de-bounce Disabled. + * | | |1 = Tamper 0 de-bounce Enabled. + * |[12] |TAMP1EN |Tamper 1 Detect Enable Bit + * | | |0 = Tamper 1 detect Disabled. + * | | |1 = Tamper 1 detect Enabled. + * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock. + * |[13] |TAMP1LV |Tamper 1 Level + * | | |This bit depend on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[14] |TAMP1DBEN |Tamper 1 De-bounce Enable Bit + * | | |0 = Tamper 1 de-bounce Disabled. + * | | |1 = Tamper 1 de-bounce Enabled. + * |[15] |DYNPR0EN |Dynamic Pair 0 Enable Bit + * | | |0 = Static detect. + * | | |1 = Dynamic detect. + * |[16] |TAMP2EN |Tamper 2 Detect Enable Bit + * | | |0 = Tamper 2 detect Disabled. + * | | |1 = Tamper 2 detect Enabled. + * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock. + * |[17] |TAMP2LV |Tamper 2 Level + * | | |This bit depend on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[18] |TAMP2DBEN |Tamper 2 De-bounce Enable Bit + * | | |0 = Tamper 2 de-bounce Disabled. + * | | |1 = Tamper 2 de-bounce Enabled. + * |[20] |TAMP3EN |Tamper 3 Detect Enable Bit + * | | |0 = Tamper 3 detect Disabled. + * | | |1 = Tamper 3 detect Enabled. + * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock. + * |[21] |TAMP3LV |Tamper 3 Level + * | | |This bit depend on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[22] |TAMP3DBEN |Tamper 3 De-bounce Enable Bit + * | | |0 = Tamper 3 de-bounce Disabled. + * | | |1 = Tamper 3 de-bounce Enabled. + * |[23] |DYNPR1EN |Dynamic Pair 1 Enable Bit + * | | |0 = Static detect. + * | | |1 = Dynamic detect. + * |[24] |TAMP4EN |Tamper4 Detect Enable Bit + * | | |0 = Tamper 4 detect Disabled. + * | | |1 = Tamper 4 detect Enabled. + * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock. + * |[25] |TAMP4LV |Tamper 4 Level + * | | |This bit depends on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[26] |TAMP4DBEN |Tamper 4 De-bounce Enable Bit + * | | |0 = Tamper 4 de-bounce Disabled. + * | | |1 = Tamper 4 de-bounce Enabled. + * |[28] |TAMP5EN |Tamper 5 Detect Enable Bit + * | | |0 = Tamper 5 detect Disabled. + * | | |1 = Tamper 5 detect Enabled. + * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock. + * |[29] |TAMP5LV |Tamper 5 Level + * | | |This bit depend on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[30] |TAMP5DBEN |Tamper 5 De-bounce Enable Bit + * | | |0 = Tamper 5 de-bounce Disabled. + * | | |1 = Tamper 5 de-bounce Enabled. + * |[31] |DYNPR2EN |Dynamic Pair 2 Enable Bit + * | | |0 = Static detect. + * | | |1 = Dynamic detect. + * @var RTC_T::TAMPSEED + * Offset: 0x128 RTC Tamper Dynamic Seed Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEED |Seed Value + * @var RTC_T::TAMPTIME + * Offset: 0x130 RTC Tamper Time Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |SEC |1-Sec Time Digit of TAMPER Time (0~9) + * |[6:4] |TENSEC |10-Sec Time Digit of TAMPER Time (0~5) + * |[11:8] |MIN |1-Min Time Digit of TAMPER Time (0~9) + * |[14:12] |TENMIN |10-Min Time Digit of TAMPER Time (0~5) + * |[19:16] |HR |1-Hour Time Digit of TAMPER Time (0~9) + * |[21:20] |TENHR |10-Hour Time Digit of TAMPER Time (0~2) + * | | |Note: 24-hour time scale only. + * @var RTC_T::TAMPCAL + * Offset: 0x134 RTC Tamper Calendar Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |DAY |1-Day Calendar Digit of TAMPER Calendar (0~9) + * |[5:4] |TENDAY |10-Day Calendar Digit of TAMPER Calendar (0~3) + * |[11:8] |MON |1-Month Calendar Digit of TAMPER Calendar (0~9) + * |[12] |TENMON |10-Month Calendar Digit of TAMPER Calendar (0~1) + * |[19:16] |YEAR |1-Year Calendar Digit of TAMPER Calendar (0~9) + * |[23:20] |TENYEAR |10-Year Calendar Digit of TAMPER Calendar (0~9) + */ + __IO uint32_t INIT; /*!< [0x0000] RTC Initiation Register */ + __IO uint32_t RWEN; /*!< [0x0004] RTC Access Enable Register */ + __IO uint32_t FREQADJ; /*!< [0x0008] RTC Frequency Compensation Register */ + __IO uint32_t TIME; /*!< [0x000c] RTC Time Loading Register */ + __IO uint32_t CAL; /*!< [0x0010] RTC Calendar Loading Register */ + __IO uint32_t CLKFMT; /*!< [0x0014] RTC Time Scale Selection Register */ + __IO uint32_t WEEKDAY; /*!< [0x0018] RTC Day of the Week Register */ + __IO uint32_t TALM; /*!< [0x001c] RTC Time Alarm Register */ + __IO uint32_t CALM; /*!< [0x0020] RTC Calendar Alarm Register */ + __I uint32_t LEAPYEAR; /*!< [0x0024] RTC Leap Year Indicator Register */ + __IO uint32_t INTEN; /*!< [0x0028] RTC Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x002c] RTC Interrupt Status Register */ + __IO uint32_t TICK; /*!< [0x0030] RTC Time Tick Register */ + __IO uint32_t TAMSK; /*!< [0x0034] RTC Time Alarm Mask Register */ + __IO uint32_t CAMSK; /*!< [0x0038] RTC Calendar Alarm Mask Register */ + __IO uint32_t SPRCTL; /*!< [0x003c] RTC Spare Functional Control Register */ + __IO uint32_t SPR[20]; /*!< [0x0040] ~ [0x008c] RTC Spare Register 0 ~ 19 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[28]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t LXTCTL; /*!< [0x0100] RTC 32.768 kHz Oscillator Control Register */ + __IO uint32_t GPIOCTL0; /*!< [0x0104] RTC GPIO Control 0 Register */ + __IO uint32_t GPIOCTL1; /*!< [0x0108] RTC GPIO Control 1 Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t DSTCTL; /*!< [0x0110] RTC Daylight Saving Time Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[3]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t TAMPCTL; /*!< [0x0120] RTC Tamper Pin Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t TAMPSEED; /*!< [0x0128] RTC Tamper Dynamic Seed Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE4[1]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t TAMPTIME; /*!< [0x0130] RTC Tamper Time Register */ + __I uint32_t TAMPCAL; /*!< [0x0134] RTC Tamper Calendar Register */ + +} RTC_T; + +/** + @addtogroup RTC_CONST RTC Bit Field Definition + Constant Definitions for RTC Controller +@{ */ + +#define RTC_INIT_ACTIVE_Pos (0) /*!< RTC_T::INIT: INIT_ACTIVE Position */ +#define RTC_INIT_ACTIVE_Msk (0x1ul << RTC_INIT_ACTIVE_Pos) /*!< RTC_T::INIT: INIT_ACTIVE Mask */ + +#define RTC_INIT_INIT_Pos (1) /*!< RTC_T::INIT: INIT Position */ +#define RTC_INIT_INIT_Msk (0x7ffffffful << RTC_INIT_INIT_Pos) /*!< RTC_T::INIT: INIT Mask */ + +#define RTC_RWEN_RWENF_Pos (16) /*!< RTC_T::RWEN: RWENF Position */ +#define RTC_RWEN_RWENF_Msk (0x1ul << RTC_RWEN_RWENF_Pos) /*!< RTC_T::RWEN: RWENF Mask */ + +#define RTC_RWEN_RTCBUSY_Pos (24) /*!< RTC_T::RWEN: RTCBUSY Position */ +#define RTC_RWEN_RTCBUSY_Msk (0x1ul << RTC_RWEN_RTCBUSY_Pos) /*!< RTC_T::RWEN: RTCBUSY Mask */ + +#define RTC_FREQADJ_FREQADJ_Pos (0) /*!< RTC_T::FREQADJ: FREQADJ Position */ +#define RTC_FREQADJ_FREQADJ_Msk (0x3ffffful << RTC_FREQADJ_FREQADJ_Pos) /*!< RTC_T::FREQADJ: FREQADJ Mask */ + +#define RTC_FREQADJ_FRACTION_Pos (0) /*!< RTC_T::FREQADJ: FRACTION Position */ +#define RTC_FREQADJ_FRACTION_Msk (0x3ful << RTC_FREQADJ_FRACTION_Pos) /*!< RTC_T::FREQADJ: FRACTION Mask */ + +#define RTC_FREQADJ_INTEGER_Pos (8) /*!< RTC_T::FREQADJ: INTEGER Position */ +#define RTC_FREQADJ_INTEGER_Msk (0x1ful << RTC_FREQADJ_INTEGER_Pos) /*!< RTC_T::FREQADJ: INTEGER Mask */ + +#define RTC_FREQADJ_FCR_BUSY_Pos (31) /*!< RTC_T::FREQADJ: FCR_BUSY Position */ +#define RTC_FREQADJ_FCR_BUSY_Msk (0x1ul << RTC_FREQADJ_FCR_BUSY_Pos) /*!< RTC_T::FREQADJ: FCR_BUSY Mask */ + +#define RTC_TIME_SEC_Pos (0) /*!< RTC_T::TIME: SEC Position */ +#define RTC_TIME_SEC_Msk (0xful << RTC_TIME_SEC_Pos) /*!< RTC_T::TIME: SEC Mask */ + +#define RTC_TIME_TENSEC_Pos (4) /*!< RTC_T::TIME: TENSEC Position */ +#define RTC_TIME_TENSEC_Msk (0x7ul << RTC_TIME_TENSEC_Pos) /*!< RTC_T::TIME: TENSEC Mask */ + +#define RTC_TIME_MIN_Pos (8) /*!< RTC_T::TIME: MIN Position */ +#define RTC_TIME_MIN_Msk (0xful << RTC_TIME_MIN_Pos) /*!< RTC_T::TIME: MIN Mask */ + +#define RTC_TIME_TENMIN_Pos (12) /*!< RTC_T::TIME: TENMIN Position */ +#define RTC_TIME_TENMIN_Msk (0x7ul << RTC_TIME_TENMIN_Pos) /*!< RTC_T::TIME: TENMIN Mask */ + +#define RTC_TIME_HR_Pos (16) /*!< RTC_T::TIME: HR Position */ +#define RTC_TIME_HR_Msk (0xful << RTC_TIME_HR_Pos) /*!< RTC_T::TIME: HR Mask */ + +#define RTC_TIME_TENHR_Pos (20) /*!< RTC_T::TIME: TENHR Position */ +#define RTC_TIME_TENHR_Msk (0x3ul << RTC_TIME_TENHR_Pos) /*!< RTC_T::TIME: TENHR Mask */ + +#define RTC_CAL_DAY_Pos (0) /*!< RTC_T::CAL: DAY Position */ +#define RTC_CAL_DAY_Msk (0xful << RTC_CAL_DAY_Pos) /*!< RTC_T::CAL: DAY Mask */ + +#define RTC_CAL_TENDAY_Pos (4) /*!< RTC_T::CAL: TENDAY Position */ +#define RTC_CAL_TENDAY_Msk (0x3ul << RTC_CAL_TENDAY_Pos) /*!< RTC_T::CAL: TENDAY Mask */ + +#define RTC_CAL_MON_Pos (8) /*!< RTC_T::CAL: MON Position */ +#define RTC_CAL_MON_Msk (0xful << RTC_CAL_MON_Pos) /*!< RTC_T::CAL: MON Mask */ + +#define RTC_CAL_TENMON_Pos (12) /*!< RTC_T::CAL: TENMON Position */ +#define RTC_CAL_TENMON_Msk (0x1ul << RTC_CAL_TENMON_Pos) /*!< RTC_T::CAL: TENMON Mask */ + +#define RTC_CAL_YEAR_Pos (16) /*!< RTC_T::CAL: YEAR Position */ +#define RTC_CAL_YEAR_Msk (0xful << RTC_CAL_YEAR_Pos) /*!< RTC_T::CAL: YEAR Mask */ + +#define RTC_CAL_TENYEAR_Pos (20) /*!< RTC_T::CAL: TENYEAR Position */ +#define RTC_CAL_TENYEAR_Msk (0xful << RTC_CAL_TENYEAR_Pos) /*!< RTC_T::CAL: TENYEAR Mask */ + +#define RTC_CLKFMT_24HEN_Pos (0) /*!< RTC_T::CLKFMT: 24HEN Position */ +#define RTC_CLKFMT_24HEN_Msk (0x1ul << RTC_CLKFMT_24HEN_Pos) /*!< RTC_T::CLKFMT: 24HEN Mask */ + +#define RTC_WEEKDAY_WEEKDAY_Pos (0) /*!< RTC_T::WEEKDAY: WEEKDAY Position */ +#define RTC_WEEKDAY_WEEKDAY_Msk (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos) /*!< RTC_T::WEEKDAY: WEEKDAY Mask */ + +#define RTC_TALM_SEC_Pos (0) /*!< RTC_T::TALM: SEC Position */ +#define RTC_TALM_SEC_Msk (0xful << RTC_TALM_SEC_Pos) /*!< RTC_T::TALM: SEC Mask */ + +#define RTC_TALM_TENSEC_Pos (4) /*!< RTC_T::TALM: TENSEC Position */ +#define RTC_TALM_TENSEC_Msk (0x7ul << RTC_TALM_TENSEC_Pos) /*!< RTC_T::TALM: TENSEC Mask */ + +#define RTC_TALM_MIN_Pos (8) /*!< RTC_T::TALM: MIN Position */ +#define RTC_TALM_MIN_Msk (0xful << RTC_TALM_MIN_Pos) /*!< RTC_T::TALM: MIN Mask */ + +#define RTC_TALM_TENMIN_Pos (12) /*!< RTC_T::TALM: TENMIN Position */ +#define RTC_TALM_TENMIN_Msk (0x7ul << RTC_TALM_TENMIN_Pos) /*!< RTC_T::TALM: TENMIN Mask */ + +#define RTC_TALM_HR_Pos (16) /*!< RTC_T::TALM: HR Position */ +#define RTC_TALM_HR_Msk (0xful << RTC_TALM_HR_Pos) /*!< RTC_T::TALM: HR Mask */ + +#define RTC_TALM_TENHR_Pos (20) /*!< RTC_T::TALM: TENHR Position */ +#define RTC_TALM_TENHR_Msk (0x3ul << RTC_TALM_TENHR_Pos) /*!< RTC_T::TALM: TENHR Mask */ + +#define RTC_CALM_DAY_Pos (0) /*!< RTC_T::CALM: DAY Position */ +#define RTC_CALM_DAY_Msk (0xful << RTC_CALM_DAY_Pos) /*!< RTC_T::CALM: DAY Mask */ + +#define RTC_CALM_TENDAY_Pos (4) /*!< RTC_T::CALM: TENDAY Position */ +#define RTC_CALM_TENDAY_Msk (0x3ul << RTC_CALM_TENDAY_Pos) /*!< RTC_T::CALM: TENDAY Mask */ + +#define RTC_CALM_MON_Pos (8) /*!< RTC_T::CALM: MON Position */ +#define RTC_CALM_MON_Msk (0xful << RTC_CALM_MON_Pos) /*!< RTC_T::CALM: MON Mask */ + +#define RTC_CALM_TENMON_Pos (12) /*!< RTC_T::CALM: TENMON Position */ +#define RTC_CALM_TENMON_Msk (0x1ul << RTC_CALM_TENMON_Pos) /*!< RTC_T::CALM: TENMON Mask */ + +#define RTC_CALM_YEAR_Pos (16) /*!< RTC_T::CALM: YEAR Position */ +#define RTC_CALM_YEAR_Msk (0xful << RTC_CALM_YEAR_Pos) /*!< RTC_T::CALM: YEAR Mask */ + +#define RTC_CALM_TENYEAR_Pos (20) /*!< RTC_T::CALM: TENYEAR Position */ +#define RTC_CALM_TENYEAR_Msk (0xful << RTC_CALM_TENYEAR_Pos) /*!< RTC_T::CALM: TENYEAR Mask */ + +#define RTC_LEAPYEAR_LEAPYEAR_Pos (0) /*!< RTC_T::LEAPYEAR: LEAPYEAR Position */ +#define RTC_LEAPYEAR_LEAPYEAR_Msk (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos) /*!< RTC_T::LEAPYEAR: LEAPYEAR Mask */ + +#define RTC_INTEN_ALMIEN_Pos (0) /*!< RTC_T::INTEN: ALMIEN Position */ +#define RTC_INTEN_ALMIEN_Msk (0x1ul << RTC_INTEN_ALMIEN_Pos) /*!< RTC_T::INTEN: ALMIEN Mask */ + +#define RTC_INTEN_TICKIEN_Pos (1) /*!< RTC_T::INTEN: TICKIEN Position */ +#define RTC_INTEN_TICKIEN_Msk (0x1ul << RTC_INTEN_TICKIEN_Pos) /*!< RTC_T::INTEN: TICKIEN Mask */ + +#define RTC_INTEN_TAMP0IEN_Pos (8) /*!< RTC_T::INTEN: TAMP0IEN Position */ +#define RTC_INTEN_TAMP0IEN_Msk (0x1ul << RTC_INTEN_TAMP0IEN_Pos) /*!< RTC_T::INTEN: TAMP0IEN Mask */ + +#define RTC_INTEN_TAMP1IEN_Pos (9) /*!< RTC_T::INTEN: TAMP1IEN Position */ +#define RTC_INTEN_TAMP1IEN_Msk (0x1ul << RTC_INTEN_TAMP1IEN_Pos) /*!< RTC_T::INTEN: TAMP1IEN Mask */ + +#define RTC_INTEN_TAMP2IEN_Pos (10) /*!< RTC_T::INTEN: TAMP2IEN Position */ +#define RTC_INTEN_TAMP2IEN_Msk (0x1ul << RTC_INTEN_TAMP2IEN_Pos) /*!< RTC_T::INTEN: TAMP2IEN Mask */ + +#define RTC_INTEN_TAMP3IEN_Pos (11) /*!< RTC_T::INTEN: TAMP3IEN Position */ +#define RTC_INTEN_TAMP3IEN_Msk (0x1ul << RTC_INTEN_TAMP3IEN_Pos) /*!< RTC_T::INTEN: TAMP3IEN Mask */ + +#define RTC_INTEN_TAMP4IEN_Pos (12) /*!< RTC_T::INTEN: TAMP4IEN Position */ +#define RTC_INTEN_TAMP4IEN_Msk (0x1ul << RTC_INTEN_TAMP4IEN_Pos) /*!< RTC_T::INTEN: TAMP4IEN Mask */ + +#define RTC_INTEN_TAMP5IEN_Pos (13) /*!< RTC_T::INTEN: TAMP5IEN Position */ +#define RTC_INTEN_TAMP5IEN_Msk (0x1ul << RTC_INTEN_TAMP5IEN_Pos) /*!< RTC_T::INTEN: TAMP5IEN Mask */ + +#define RTC_INTSTS_ALMIF_Pos (0) /*!< RTC_T::INTSTS: ALMIF Position */ +#define RTC_INTSTS_ALMIF_Msk (0x1ul << RTC_INTSTS_ALMIF_Pos) /*!< RTC_T::INTSTS: ALMIF Mask */ + +#define RTC_INTSTS_TICKIF_Pos (1) /*!< RTC_T::INTSTS: TICKIF Position */ +#define RTC_INTSTS_TICKIF_Msk (0x1ul << RTC_INTSTS_TICKIF_Pos) /*!< RTC_T::INTSTS: TICKIF Mask */ + +#define RTC_INTSTS_TAMP0IF_Pos (8) /*!< RTC_T::INTSTS: TAMP0IF Position */ +#define RTC_INTSTS_TAMP0IF_Msk (0x1ul << RTC_INTSTS_TAMP0IF_Pos) /*!< RTC_T::INTSTS: TAMP0IF Mask */ + +#define RTC_INTSTS_TAMP1IF_Pos (9) /*!< RTC_T::INTSTS: TAMP1IF Position */ +#define RTC_INTSTS_TAMP1IF_Msk (0x1ul << RTC_INTSTS_TAMP1IF_Pos) /*!< RTC_T::INTSTS: TAMP1IF Mask */ + +#define RTC_INTSTS_TAMP2IF_Pos (10) /*!< RTC_T::INTSTS: TAMP2IF Position */ +#define RTC_INTSTS_TAMP2IF_Msk (0x1ul << RTC_INTSTS_TAMP2IF_Pos) /*!< RTC_T::INTSTS: TAMP2IF Mask */ + +#define RTC_INTSTS_TAMP3IF_Pos (11) /*!< RTC_T::INTSTS: TAMP3IF Position */ +#define RTC_INTSTS_TAMP3IF_Msk (0x1ul << RTC_INTSTS_TAMP3IF_Pos) /*!< RTC_T::INTSTS: TAMP3IF Mask */ + +#define RTC_INTSTS_TAMP4IF_Pos (12) /*!< RTC_T::INTSTS: TAMP4IF Position */ +#define RTC_INTSTS_TAMP4IF_Msk (0x1ul << RTC_INTSTS_TAMP4IF_Pos) /*!< RTC_T::INTSTS: TAMP4IF Mask */ + +#define RTC_INTSTS_TAMP5IF_Pos (13) /*!< RTC_T::INTSTS: TAMP5IF Position */ +#define RTC_INTSTS_TAMP5IF_Msk (0x1ul << RTC_INTSTS_TAMP5IF_Pos) /*!< RTC_T::INTSTS: TAMP5IF Mask */ + +#define RTC_TICK_TICK_Pos (0) /*!< RTC_T::TICK: TICK Position */ +#define RTC_TICK_TICK_Msk (0x7ul << RTC_TICK_TICK_Pos) /*!< RTC_T::TICK: TICK Mask */ + +#define RTC_TAMSK_MSEC_Pos (0) /*!< RTC_T::TAMSK: MSEC Position */ +#define RTC_TAMSK_MSEC_Msk (0x1ul << RTC_TAMSK_MSEC_Pos) /*!< RTC_T::TAMSK: MSEC Mask */ + +#define RTC_TAMSK_MTENSEC_Pos (1) /*!< RTC_T::TAMSK: MTENSEC Position */ +#define RTC_TAMSK_MTENSEC_Msk (0x1ul << RTC_TAMSK_MTENSEC_Pos) /*!< RTC_T::TAMSK: MTENSEC Mask */ + +#define RTC_TAMSK_MMIN_Pos (2) /*!< RTC_T::TAMSK: MMIN Position */ +#define RTC_TAMSK_MMIN_Msk (0x1ul << RTC_TAMSK_MMIN_Pos) /*!< RTC_T::TAMSK: MMIN Mask */ + +#define RTC_TAMSK_MTENMIN_Pos (3) /*!< RTC_T::TAMSK: MTENMIN Position */ +#define RTC_TAMSK_MTENMIN_Msk (0x1ul << RTC_TAMSK_MTENMIN_Pos) /*!< RTC_T::TAMSK: MTENMIN Mask */ + +#define RTC_TAMSK_MHR_Pos (4) /*!< RTC_T::TAMSK: MHR Position */ +#define RTC_TAMSK_MHR_Msk (0x1ul << RTC_TAMSK_MHR_Pos) /*!< RTC_T::TAMSK: MHR Mask */ + +#define RTC_TAMSK_MTENHR_Pos (5) /*!< RTC_T::TAMSK: MTENHR Position */ +#define RTC_TAMSK_MTENHR_Msk (0x1ul << RTC_TAMSK_MTENHR_Pos) /*!< RTC_T::TAMSK: MTENHR Mask */ + +#define RTC_CAMSK_MDAY_Pos (0) /*!< RTC_T::CAMSK: MDAY Position */ +#define RTC_CAMSK_MDAY_Msk (0x1ul << RTC_CAMSK_MDAY_Pos) /*!< RTC_T::CAMSK: MDAY Mask */ + +#define RTC_CAMSK_MTENDAY_Pos (1) /*!< RTC_T::CAMSK: MTENDAY Position */ +#define RTC_CAMSK_MTENDAY_Msk (0x1ul << RTC_CAMSK_MTENDAY_Pos) /*!< RTC_T::CAMSK: MTENDAY Mask */ + +#define RTC_CAMSK_MMON_Pos (2) /*!< RTC_T::CAMSK: MMON Position */ +#define RTC_CAMSK_MMON_Msk (0x1ul << RTC_CAMSK_MMON_Pos) /*!< RTC_T::CAMSK: MMON Mask */ + +#define RTC_CAMSK_MTENMON_Pos (3) /*!< RTC_T::CAMSK: MTENMON Position */ +#define RTC_CAMSK_MTENMON_Msk (0x1ul << RTC_CAMSK_MTENMON_Pos) /*!< RTC_T::CAMSK: MTENMON Mask */ + +#define RTC_CAMSK_MYEAR_Pos (4) /*!< RTC_T::CAMSK: MYEAR Position */ +#define RTC_CAMSK_MYEAR_Msk (0x1ul << RTC_CAMSK_MYEAR_Pos) /*!< RTC_T::CAMSK: MYEAR Mask */ + +#define RTC_CAMSK_MTENYEAR_Pos (5) /*!< RTC_T::CAMSK: MTENYEAR Position */ +#define RTC_CAMSK_MTENYEAR_Msk (0x1ul << RTC_CAMSK_MTENYEAR_Pos) /*!< RTC_T::CAMSK: MTENYEAR Mask */ + +#define RTC_SPRCTL_SPRRWEN_Pos (2) /*!< RTC_T::SPRCTL: SPRRWEN Position */ +#define RTC_SPRCTL_SPRRWEN_Msk (0x1ul << RTC_SPRCTL_SPRRWEN_Pos) /*!< RTC_T::SPRCTL: SPRRWEN Mask */ + +#define RTC_SPRCTL_SPRCSTS_Pos (5) /*!< RTC_T::SPRCTL: SPRCSTS Position */ +#define RTC_SPRCTL_SPRCSTS_Msk (0x1ul << RTC_SPRCTL_SPRCSTS_Pos) /*!< RTC_T::SPRCTL: SPRCSTS Mask */ + +#define RTC_SPR0_SPARE_Pos (0) /*!< RTC_T::SPR0: SPARE Position */ +#define RTC_SPR0_SPARE_Msk (0xfffffffful << RTC_SPR0_SPARE_Pos) /*!< RTC_T::SPR0: SPARE Mask */ + +#define RTC_SPR1_SPARE_Pos (0) /*!< RTC_T::SPR1: SPARE Position */ +#define RTC_SPR1_SPARE_Msk (0xfffffffful << RTC_SPR1_SPARE_Pos) /*!< RTC_T::SPR1: SPARE Mask */ + +#define RTC_SPR2_SPARE_Pos (0) /*!< RTC_T::SPR2: SPARE Position */ +#define RTC_SPR2_SPARE_Msk (0xfffffffful << RTC_SPR2_SPARE_Pos) /*!< RTC_T::SPR2: SPARE Mask */ + +#define RTC_SPR3_SPARE_Pos (0) /*!< RTC_T::SPR3: SPARE Position */ +#define RTC_SPR3_SPARE_Msk (0xfffffffful << RTC_SPR3_SPARE_Pos) /*!< RTC_T::SPR3: SPARE Mask */ + +#define RTC_SPR4_SPARE_Pos (0) /*!< RTC_T::SPR4: SPARE Position */ +#define RTC_SPR4_SPARE_Msk (0xfffffffful << RTC_SPR4_SPARE_Pos) /*!< RTC_T::SPR4: SPARE Mask */ + +#define RTC_SPR5_SPARE_Pos (0) /*!< RTC_T::SPR5: SPARE Position */ +#define RTC_SPR5_SPARE_Msk (0xfffffffful << RTC_SPR5_SPARE_Pos) /*!< RTC_T::SPR5: SPARE Mask */ + +#define RTC_SPR6_SPARE_Pos (0) /*!< RTC_T::SPR6: SPARE Position */ +#define RTC_SPR6_SPARE_Msk (0xfffffffful << RTC_SPR6_SPARE_Pos) /*!< RTC_T::SPR6: SPARE Mask */ + +#define RTC_SPR7_SPARE_Pos (0) /*!< RTC_T::SPR7: SPARE Position */ +#define RTC_SPR7_SPARE_Msk (0xfffffffful << RTC_SPR7_SPARE_Pos) /*!< RTC_T::SPR7: SPARE Mask */ + +#define RTC_SPR8_SPARE_Pos (0) /*!< RTC_T::SPR8: SPARE Position */ +#define RTC_SPR8_SPARE_Msk (0xfffffffful << RTC_SPR8_SPARE_Pos) /*!< RTC_T::SPR8: SPARE Mask */ + +#define RTC_SPR9_SPARE_Pos (0) /*!< RTC_T::SPR9: SPARE Position */ +#define RTC_SPR9_SPARE_Msk (0xfffffffful << RTC_SPR9_SPARE_Pos) /*!< RTC_T::SPR9: SPARE Mask */ + +#define RTC_SPR10_SPARE_Pos (0) /*!< RTC_T::SPR10: SPARE Position */ +#define RTC_SPR10_SPARE_Msk (0xfffffffful << RTC_SPR10_SPARE_Pos) /*!< RTC_T::SPR10: SPARE Mask */ + +#define RTC_SPR11_SPARE_Pos (0) /*!< RTC_T::SPR11: SPARE Position */ +#define RTC_SPR11_SPARE_Msk (0xfffffffful << RTC_SPR11_SPARE_Pos) /*!< RTC_T::SPR11: SPARE Mask */ + +#define RTC_SPR12_SPARE_Pos (0) /*!< RTC_T::SPR12: SPARE Position */ +#define RTC_SPR12_SPARE_Msk (0xfffffffful << RTC_SPR12_SPARE_Pos) /*!< RTC_T::SPR12: SPARE Mask */ + +#define RTC_SPR13_SPARE_Pos (0) /*!< RTC_T::SPR13: SPARE Position */ +#define RTC_SPR13_SPARE_Msk (0xfffffffful << RTC_SPR13_SPARE_Pos) /*!< RTC_T::SPR13: SPARE Mask */ + +#define RTC_SPR14_SPARE_Pos (0) /*!< RTC_T::SPR14: SPARE Position */ +#define RTC_SPR14_SPARE_Msk (0xfffffffful << RTC_SPR14_SPARE_Pos) /*!< RTC_T::SPR14: SPARE Mask */ + +#define RTC_SPR15_SPARE_Pos (0) /*!< RTC_T::SPR15: SPARE Position */ +#define RTC_SPR15_SPARE_Msk (0xfffffffful << RTC_SPR15_SPARE_Pos) /*!< RTC_T::SPR15: SPARE Mask */ + +#define RTC_SPR16_SPARE_Pos (0) /*!< RTC_T::SPR16: SPARE Position */ +#define RTC_SPR16_SPARE_Msk (0xfffffffful << RTC_SPR16_SPARE_Pos) /*!< RTC_T::SPR16: SPARE Mask */ + +#define RTC_SPR17_SPARE_Pos (0) /*!< RTC_T::SPR17: SPARE Position */ +#define RTC_SPR17_SPARE_Msk (0xfffffffful << RTC_SPR17_SPARE_Pos) /*!< RTC_T::SPR17: SPARE Mask */ + +#define RTC_SPR18_SPARE_Pos (0) /*!< RTC_T::SPR18: SPARE Position */ +#define RTC_SPR18_SPARE_Msk (0xfffffffful << RTC_SPR18_SPARE_Pos) /*!< RTC_T::SPR18: SPARE Mask */ + +#define RTC_SPR19_SPARE_Pos (0) /*!< RTC_T::SPR19: SPARE Position */ +#define RTC_SPR19_SPARE_Msk (0xfffffffful << RTC_SPR19_SPARE_Pos) /*!< RTC_T::SPR19: SPARE Mask */ + +#define RTC_LXTCTL_GAIN_Pos (1) /*!< RTC_T::LXTCTL: GAIN Position */ +#define RTC_LXTCTL_GAIN_Msk (0x3ul << RTC_LXTCTL_GAIN_Pos) /*!< RTC_T::LXTCTL: GAIN Mask */ + +#define RTC_GPIOCTL0_OPMODE0_Pos (0) /*!< RTC_T::GPIOCTL0: OPMODE0 Position */ +#define RTC_GPIOCTL0_OPMODE0_Msk (0x3ul << RTC_GPIOCTL0_OPMODE0_Pos) /*!< RTC_T::GPIOCTL0: OPMODE0 Mask */ + +#define RTC_GPIOCTL0_DOUT0_Pos (2) /*!< RTC_T::GPIOCTL0: DOUT0 Position */ +#define RTC_GPIOCTL0_DOUT0_Msk (0x1ul << RTC_GPIOCTL0_DOUT0_Pos) /*!< RTC_T::GPIOCTL0: DOUT0 Mask */ + +#define RTC_GPIOCTL0_CTLSEL0_Pos (3) /*!< RTC_T::GPIOCTL0: CTLSEL0 Position */ +#define RTC_GPIOCTL0_CTLSEL0_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL0_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL0 Mask */ + +#define RTC_GPIOCTL0_PUSEL0_Pos (4) /*!< RTC_T::GPIOCTL0: PUSEL0 Position */ +#define RTC_GPIOCTL0_PUSEL0_Msk (0x3ul << RTC_GPIOCTL0_PUSEL0_Pos) /*!< RTC_T::GPIOCTL0: PUSEL0 Mask */ + +#define RTC_GPIOCTL0_OPMODE1_Pos (8) /*!< RTC_T::GPIOCTL0: OPMODE1 Position */ +#define RTC_GPIOCTL0_OPMODE1_Msk (0x3ul << RTC_GPIOCTL0_OPMODE1_Pos) /*!< RTC_T::GPIOCTL0: OPMODE1 Mask */ + +#define RTC_GPIOCTL0_DOUT1_Pos (10) /*!< RTC_T::GPIOCTL0: DOUT1 Position */ +#define RTC_GPIOCTL0_DOUT1_Msk (0x1ul << RTC_GPIOCTL0_DOUT1_Pos) /*!< RTC_T::GPIOCTL0: DOUT1 Mask */ + +#define RTC_GPIOCTL0_CTLSEL1_Pos (11) /*!< RTC_T::GPIOCTL0: CTLSEL1 Position */ +#define RTC_GPIOCTL0_CTLSEL1_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL1_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL1 Mask */ + +#define RTC_GPIOCTL0_PUSEL1_Pos (12) /*!< RTC_T::GPIOCTL0: PUSEL1 Position */ +#define RTC_GPIOCTL0_PUSEL1_Msk (0x3ul << RTC_GPIOCTL0_PUSEL1_Pos) /*!< RTC_T::GPIOCTL0: PUSEL1 Mask */ + +#define RTC_GPIOCTL0_OPMODE2_Pos (16) /*!< RTC_T::GPIOCTL0: OPMODE2 Position */ +#define RTC_GPIOCTL0_OPMODE2_Msk (0x3ul << RTC_GPIOCTL0_OPMODE2_Pos) /*!< RTC_T::GPIOCTL0: OPMODE2 Mask */ + +#define RTC_GPIOCTL0_DOUT2_Pos (18) /*!< RTC_T::GPIOCTL0: DOUT2 Position */ +#define RTC_GPIOCTL0_DOUT2_Msk (0x1ul << RTC_GPIOCTL0_DOUT2_Pos) /*!< RTC_T::GPIOCTL0: DOUT2 Mask */ + +#define RTC_GPIOCTL0_CTLSEL2_Pos (19) /*!< RTC_T::GPIOCTL0: CTLSEL2 Position */ +#define RTC_GPIOCTL0_CTLSEL2_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL2_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL2 Mask */ + +#define RTC_GPIOCTL0_PUSEL2_Pos (20) /*!< RTC_T::GPIOCTL0: PUSEL2 Position */ +#define RTC_GPIOCTL0_PUSEL2_Msk (0x3ul << RTC_GPIOCTL0_PUSEL2_Pos) /*!< RTC_T::GPIOCTL0: PUSEL2 Mask */ + +#define RTC_GPIOCTL0_OPMODE3_Pos (24) /*!< RTC_T::GPIOCTL0: OPMODE3 Position */ +#define RTC_GPIOCTL0_OPMODE3_Msk (0x3ul << RTC_GPIOCTL0_OPMODE3_Pos) /*!< RTC_T::GPIOCTL0: OPMODE3 Mask */ + +#define RTC_GPIOCTL0_DOUT3_Pos (26) /*!< RTC_T::GPIOCTL0: DOUT3 Position */ +#define RTC_GPIOCTL0_DOUT3_Msk (0x1ul << RTC_GPIOCTL0_DOUT3_Pos) /*!< RTC_T::GPIOCTL0: DOUT3 Mask */ + +#define RTC_GPIOCTL0_CTLSEL3_Pos (27) /*!< RTC_T::GPIOCTL0: CTLSEL3 Position */ +#define RTC_GPIOCTL0_CTLSEL3_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL3_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL3 Mask */ + +#define RTC_GPIOCTL0_PUSEL3_Pos (28) /*!< RTC_T::GPIOCTL0: PUSEL3 Position */ +#define RTC_GPIOCTL0_PUSEL3_Msk (0x3ul << RTC_GPIOCTL0_PUSEL3_Pos) /*!< RTC_T::GPIOCTL0: PUSEL3 Mask */ + +#define RTC_GPIOCTL1_OPMODE4_Pos (0) /*!< RTC_T::GPIOCTL1: OPMODE4 Position */ +#define RTC_GPIOCTL1_OPMODE4_Msk (0x3ul << RTC_GPIOCTL1_OPMODE4_Pos) /*!< RTC_T::GPIOCTL1: OPMODE4 Mask */ + +#define RTC_GPIOCTL1_DOUT4_Pos (2) /*!< RTC_T::GPIOCTL1: DOUT4 Position */ +#define RTC_GPIOCTL1_DOUT4_Msk (0x1ul << RTC_GPIOCTL1_DOUT4_Pos) /*!< RTC_T::GPIOCTL1: DOUT4 Mask */ + +#define RTC_GPIOCTL1_CTLSEL4_Pos (3) /*!< RTC_T::GPIOCTL1: CTLSEL4 Position */ +#define RTC_GPIOCTL1_CTLSEL4_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL4_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL4 Mask */ + +#define RTC_GPIOCTL1_PUSEL4_Pos (4) /*!< RTC_T::GPIOCTL1: PUSEL4 Position */ +#define RTC_GPIOCTL1_PUSEL4_Msk (0x3ul << RTC_GPIOCTL1_PUSEL4_Pos) /*!< RTC_T::GPIOCTL1: PUSEL4 Mask */ + +#define RTC_GPIOCTL1_OPMODE5_Pos (8) /*!< RTC_T::GPIOCTL1: OPMODE5 Position */ +#define RTC_GPIOCTL1_OPMODE5_Msk (0x3ul << RTC_GPIOCTL1_OPMODE5_Pos) /*!< RTC_T::GPIOCTL1: OPMODE5 Mask */ + +#define RTC_GPIOCTL1_DOUT5_Pos (10) /*!< RTC_T::GPIOCTL1: DOUT5 Position */ +#define RTC_GPIOCTL1_DOUT5_Msk (0x1ul << RTC_GPIOCTL1_DOUT5_Pos) /*!< RTC_T::GPIOCTL1: DOUT5 Mask */ + +#define RTC_GPIOCTL1_CTLSEL5_Pos (11) /*!< RTC_T::GPIOCTL1: CTLSEL5 Position */ +#define RTC_GPIOCTL1_CTLSEL5_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL5_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL5 Mask */ + +#define RTC_GPIOCTL1_PUSEL5_Pos (12) /*!< RTC_T::GPIOCTL1: PUSEL5 Position */ +#define RTC_GPIOCTL1_PUSEL5_Msk (0x3ul << RTC_GPIOCTL1_PUSEL5_Pos) /*!< RTC_T::GPIOCTL1: PUSEL5 Mask */ + +#define RTC_GPIOCTL1_OPMODE6_Pos (16) /*!< RTC_T::GPIOCTL1: OPMODE6 Position */ +#define RTC_GPIOCTL1_OPMODE6_Msk (0x3ul << RTC_GPIOCTL1_OPMODE6_Pos) /*!< RTC_T::GPIOCTL1: OPMODE6 Mask */ + +#define RTC_GPIOCTL1_DOUT6_Pos (18) /*!< RTC_T::GPIOCTL1: DOUT6 Position */ +#define RTC_GPIOCTL1_DOUT6_Msk (0x1ul << RTC_GPIOCTL1_DOUT6_Pos) /*!< RTC_T::GPIOCTL1: DOUT6 Mask */ + +#define RTC_GPIOCTL1_CTLSEL6_Pos (19) /*!< RTC_T::GPIOCTL1: CTLSEL6 Position */ +#define RTC_GPIOCTL1_CTLSEL6_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL6_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL6 Mask */ + +#define RTC_GPIOCTL1_PUSEL6_Pos (20) /*!< RTC_T::GPIOCTL1: PUSEL6 Position */ +#define RTC_GPIOCTL1_PUSEL6_Msk (0x3ul << RTC_GPIOCTL1_PUSEL6_Pos) /*!< RTC_T::GPIOCTL1: PUSEL6 Mask */ + +#define RTC_GPIOCTL1_OPMODE7_Pos (24) /*!< RTC_T::GPIOCTL1: OPMODE7 Position */ +#define RTC_GPIOCTL1_OPMODE7_Msk (0x3ul << RTC_GPIOCTL1_OPMODE7_Pos) /*!< RTC_T::GPIOCTL1: OPMODE7 Mask */ + +#define RTC_GPIOCTL1_DOUT7_Pos (26) /*!< RTC_T::GPIOCTL1: DOUT7 Position */ +#define RTC_GPIOCTL1_DOUT7_Msk (0x1ul << RTC_GPIOCTL1_DOUT7_Pos) /*!< RTC_T::GPIOCTL1: DOUT7 Mask */ + +#define RTC_GPIOCTL1_CTLSEL7_Pos (27) /*!< RTC_T::GPIOCTL1: CTLSEL7 Position */ +#define RTC_GPIOCTL1_CTLSEL7_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL7_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL7 Mask */ + +#define RTC_GPIOCTL1_PUSEL7_Pos (28) /*!< RTC_T::GPIOCTL1: PUSEL7 Position */ +#define RTC_GPIOCTL1_PUSEL7_Msk (0x3ul << RTC_GPIOCTL1_PUSEL7_Pos) /*!< RTC_T::GPIOCTL1: PUSEL7 Mask */ + +#define RTC_DSTCTL_ADDHR_Pos (0) /*!< RTC_T::DSTCTL: ADDHR Position */ +#define RTC_DSTCTL_ADDHR_Msk (0x1ul << RTC_DSTCTL_ADDHR_Pos) /*!< RTC_T::DSTCTL: ADDHR Mask */ + +#define RTC_DSTCTL_SUBHR_Pos (1) /*!< RTC_T::DSTCTL: SUBHR Position */ +#define RTC_DSTCTL_SUBHR_Msk (0x1ul << RTC_DSTCTL_SUBHR_Pos) /*!< RTC_T::DSTCTL: SUBHR Mask */ + +#define RTC_DSTCTL_DSBAK_Pos (2) /*!< RTC_T::DSTCTL: DSBAK Position */ +#define RTC_DSTCTL_DSBAK_Msk (0x1ul << RTC_DSTCTL_DSBAK_Pos) /*!< RTC_T::DSTCTL: DSBAK Mask */ + +#define RTC_TAMPCTL_DYN1ISS_Pos (0) /*!< RTC_T::TAMPCTL: DYN1ISS Position */ +#define RTC_TAMPCTL_DYN1ISS_Msk (0x1ul << RTC_TAMPCTL_DYN1ISS_Pos) /*!< RTC_T::TAMPCTL: DYN1ISS Mask */ + +#define RTC_TAMPCTL_DYN2ISS_Pos (1) /*!< RTC_T::TAMPCTL: DYN2ISS Position */ +#define RTC_TAMPCTL_DYN2ISS_Msk (0x1ul << RTC_TAMPCTL_DYN2ISS_Pos) /*!< RTC_T::TAMPCTL: DYN2ISS Mask */ + +#define RTC_TAMPCTL_DYNSRC_Pos (2) /*!< RTC_T::TAMPCTL: DYNSRC Position */ +#define RTC_TAMPCTL_DYNSRC_Msk (0x3ul << RTC_TAMPCTL_DYNSRC_Pos) /*!< RTC_T::TAMPCTL: DYNSRC Mask */ + +#define RTC_TAMPCTL_SEEDRLD_Pos (4) /*!< RTC_T::TAMPCTL: SEEDRLD Position */ +#define RTC_TAMPCTL_SEEDRLD_Msk (0x1ul << RTC_TAMPCTL_SEEDRLD_Pos) /*!< RTC_T::TAMPCTL: SEEDRLD Mask */ + +#define RTC_TAMPCTL_DYNRATE_Pos (5) /*!< RTC_T::TAMPCTL: DYNRATE Position */ +#define RTC_TAMPCTL_DYNRATE_Msk (0x7ul << RTC_TAMPCTL_DYNRATE_Pos) /*!< RTC_T::TAMPCTL: DYNRATE Mask */ + +#define RTC_TAMPCTL_TAMP0EN_Pos (8) /*!< RTC_T::TAMPCTL: TAMP0EN Position */ +#define RTC_TAMPCTL_TAMP0EN_Msk (0x1ul << RTC_TAMPCTL_TAMP0EN_Pos) /*!< RTC_T::TAMPCTL: TAMP0EN Mask */ + +#define RTC_TAMPCTL_TAMP0LV_Pos (9) /*!< RTC_T::TAMPCTL: TAMP0LV Position */ +#define RTC_TAMPCTL_TAMP0LV_Msk (0x1ul << RTC_TAMPCTL_TAMP0LV_Pos) /*!< RTC_T::TAMPCTL: TAMP0LV Mask */ + +#define RTC_TAMPCTL_TAMP0DBEN_Pos (10) /*!< RTC_T::TAMPCTL: TAMP0DBEN Position */ +#define RTC_TAMPCTL_TAMP0DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP0DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP0DBEN Mask */ + +#define RTC_TAMPCTL_TAMP1EN_Pos (12) /*!< RTC_T::TAMPCTL: TAMP1EN Position */ +#define RTC_TAMPCTL_TAMP1EN_Msk (0x1ul << RTC_TAMPCTL_TAMP1EN_Pos) /*!< RTC_T::TAMPCTL: TAMP1EN Mask */ + +#define RTC_TAMPCTL_TAMP1LV_Pos (13) /*!< RTC_T::TAMPCTL: TAMP1LV Position */ +#define RTC_TAMPCTL_TAMP1LV_Msk (0x1ul << RTC_TAMPCTL_TAMP1LV_Pos) /*!< RTC_T::TAMPCTL: TAMP1LV Mask */ + +#define RTC_TAMPCTL_TAMP1DBEN_Pos (14) /*!< RTC_T::TAMPCTL: TAMP1DBEN Position */ +#define RTC_TAMPCTL_TAMP1DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP1DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP1DBEN Mask */ + +#define RTC_TAMPCTL_DYNPR0EN_Pos (15) /*!< RTC_T::TAMPCTL: DYNPR0EN Position */ +#define RTC_TAMPCTL_DYNPR0EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR0EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR0EN Mask */ + +#define RTC_TAMPCTL_TAMP2EN_Pos (16) /*!< RTC_T::TAMPCTL: TAMP2EN Position */ +#define RTC_TAMPCTL_TAMP2EN_Msk (0x1ul << RTC_TAMPCTL_TAMP2EN_Pos) /*!< RTC_T::TAMPCTL: TAMP2EN Mask */ + +#define RTC_TAMPCTL_TAMP2LV_Pos (17) /*!< RTC_T::TAMPCTL: TAMP2LV Position */ +#define RTC_TAMPCTL_TAMP2LV_Msk (0x1ul << RTC_TAMPCTL_TAMP2LV_Pos) /*!< RTC_T::TAMPCTL: TAMP2LV Mask */ + +#define RTC_TAMPCTL_TAMP2DBEN_Pos (18) /*!< RTC_T::TAMPCTL: TAMP2DBEN Position */ +#define RTC_TAMPCTL_TAMP2DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP2DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP2DBEN Mask */ + +#define RTC_TAMPCTL_TAMP3EN_Pos (20) /*!< RTC_T::TAMPCTL: TAMP3EN Position */ +#define RTC_TAMPCTL_TAMP3EN_Msk (0x1ul << RTC_TAMPCTL_TAMP3EN_Pos) /*!< RTC_T::TAMPCTL: TAMP3EN Mask */ + +#define RTC_TAMPCTL_TAMP3LV_Pos (21) /*!< RTC_T::TAMPCTL: TAMP3LV Position */ +#define RTC_TAMPCTL_TAMP3LV_Msk (0x1ul << RTC_TAMPCTL_TAMP3LV_Pos) /*!< RTC_T::TAMPCTL: TAMP3LV Mask */ + +#define RTC_TAMPCTL_TAMP3DBEN_Pos (22) /*!< RTC_T::TAMPCTL: TAMP3DBEN Position */ +#define RTC_TAMPCTL_TAMP3DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP3DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP3DBEN Mask */ + +#define RTC_TAMPCTL_DYNPR1EN_Pos (23) /*!< RTC_T::TAMPCTL: DYNPR1EN Position */ +#define RTC_TAMPCTL_DYNPR1EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR1EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR1EN Mask */ + +#define RTC_TAMPCTL_TAMP4EN_Pos (24) /*!< RTC_T::TAMPCTL: TAMP4EN Position */ +#define RTC_TAMPCTL_TAMP4EN_Msk (0x1ul << RTC_TAMPCTL_TAMP4EN_Pos) /*!< RTC_T::TAMPCTL: TAMP4EN Mask */ + +#define RTC_TAMPCTL_TAMP4LV_Pos (25) /*!< RTC_T::TAMPCTL: TAMP4LV Position */ +#define RTC_TAMPCTL_TAMP4LV_Msk (0x1ul << RTC_TAMPCTL_TAMP4LV_Pos) /*!< RTC_T::TAMPCTL: TAMP4LV Mask */ + +#define RTC_TAMPCTL_TAMP4DBEN_Pos (26) /*!< RTC_T::TAMPCTL: TAMP4DBEN Position */ +#define RTC_TAMPCTL_TAMP4DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP4DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP4DBEN Mask */ + +#define RTC_TAMPCTL_TAMP5EN_Pos (28) /*!< RTC_T::TAMPCTL: TAMP5EN Position */ +#define RTC_TAMPCTL_TAMP5EN_Msk (0x1ul << RTC_TAMPCTL_TAMP5EN_Pos) /*!< RTC_T::TAMPCTL: TAMP5EN Mask */ + +#define RTC_TAMPCTL_TAMP5LV_Pos (29) /*!< RTC_T::TAMPCTL: TAMP5LV Position */ +#define RTC_TAMPCTL_TAMP5LV_Msk (0x1ul << RTC_TAMPCTL_TAMP5LV_Pos) /*!< RTC_T::TAMPCTL: TAMP5LV Mask */ + +#define RTC_TAMPCTL_TAMP5DBEN_Pos (30) /*!< RTC_T::TAMPCTL: TAMP5DBEN Position */ +#define RTC_TAMPCTL_TAMP5DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP5DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP5DBEN Mask */ + +#define RTC_TAMPCTL_DYNPR2EN_Pos (31) /*!< RTC_T::TAMPCTL: DYNPR2EN Position */ +#define RTC_TAMPCTL_DYNPR2EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR2EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR2EN Mask */ + +#define RTC_TAMPSEED_SEED_Pos (0) /*!< RTC_T::TAMPSEED: SEED Position */ +#define RTC_TAMPSEED_SEED_Msk (0xfffffffful << RTC_TAMPSEED_SEED_Pos) /*!< RTC_T::TAMPSEED: SEED Mask */ + +#define RTC_TAMPTIME_SEC_Pos (0) /*!< RTC_T::TAMPTIME: SEC Position */ +#define RTC_TAMPTIME_SEC_Msk (0xful << RTC_TAMPTIME_SEC_Pos) /*!< RTC_T::TAMPTIME: SEC Mask */ + +#define RTC_TAMPTIME_TENSEC_Pos (4) /*!< RTC_T::TAMPTIME: TENSEC Position */ +#define RTC_TAMPTIME_TENSEC_Msk (0x7ul << RTC_TAMPTIME_TENSEC_Pos) /*!< RTC_T::TAMPTIME: TENSEC Mask */ + +#define RTC_TAMPTIME_MIN_Pos (8) /*!< RTC_T::TAMPTIME: MIN Position */ +#define RTC_TAMPTIME_MIN_Msk (0xful << RTC_TAMPTIME_MIN_Pos) /*!< RTC_T::TAMPTIME: MIN Mask */ + +#define RTC_TAMPTIME_TENMIN_Pos (12) /*!< RTC_T::TAMPTIME: TENMIN Position */ +#define RTC_TAMPTIME_TENMIN_Msk (0x7ul << RTC_TAMPTIME_TENMIN_Pos) /*!< RTC_T::TAMPTIME: TENMIN Mask */ + +#define RTC_TAMPTIME_HR_Pos (16) /*!< RTC_T::TAMPTIME: HR Position */ +#define RTC_TAMPTIME_HR_Msk (0xful << RTC_TAMPTIME_HR_Pos) /*!< RTC_T::TAMPTIME: HR Mask */ + +#define RTC_TAMPTIME_TENHR_Pos (20) /*!< RTC_T::TAMPTIME: TENHR Position */ +#define RTC_TAMPTIME_TENHR_Msk (0x3ul << RTC_TAMPTIME_TENHR_Pos) /*!< RTC_T::TAMPTIME: TENHR Mask */ + +#define RTC_TAMPCAL_DAY_Pos (0) /*!< RTC_T::TAMPCAL: DAY Position */ +#define RTC_TAMPCAL_DAY_Msk (0xful << RTC_TAMPCAL_DAY_Pos) /*!< RTC_T::TAMPCAL: DAY Mask */ + +#define RTC_TAMPCAL_TENDAY_Pos (4) /*!< RTC_T::TAMPCAL: TENDAY Position */ +#define RTC_TAMPCAL_TENDAY_Msk (0x3ul << RTC_TAMPCAL_TENDAY_Pos) /*!< RTC_T::TAMPCAL: TENDAY Mask */ + +#define RTC_TAMPCAL_MON_Pos (8) /*!< RTC_T::TAMPCAL: MON Position */ +#define RTC_TAMPCAL_MON_Msk (0xful << RTC_TAMPCAL_MON_Pos) /*!< RTC_T::TAMPCAL: MON Mask */ + +#define RTC_TAMPCAL_TENMON_Pos (12) /*!< RTC_T::TAMPCAL: TENMON Position */ +#define RTC_TAMPCAL_TENMON_Msk (0x1ul << RTC_TAMPCAL_TENMON_Pos) /*!< RTC_T::TAMPCAL: TENMON Mask */ + +#define RTC_TAMPCAL_YEAR_Pos (16) /*!< RTC_T::TAMPCAL: YEAR Position */ +#define RTC_TAMPCAL_YEAR_Msk (0xful << RTC_TAMPCAL_YEAR_Pos) /*!< RTC_T::TAMPCAL: YEAR Mask */ + +#define RTC_TAMPCAL_TENYEAR_Pos (20) /*!< RTC_T::TAMPCAL: TENYEAR Position */ +#define RTC_TAMPCAL_TENYEAR_Msk (0xful << RTC_TAMPCAL_TENYEAR_Pos) /*!< RTC_T::TAMPCAL: TENYEAR Mask */ + + +/**@}*/ /* RTC_CONST */ +/**@}*/ /* end of RTC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __RTC_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/sc_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/sc_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..af930b950d14c7c44eb02606048abbfa7f516043 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/sc_reg.h @@ -0,0 +1,1019 @@ +/**************************************************************************//** + * @file sc_reg.h + * @version V1.00 + * @brief SC register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SC_REG_H__ +#define __SC_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup SC Smart Card Host Interface Controller(SC) + Memory Mapped Structure for SC Controller +@{ */ + +typedef struct +{ + + + /** + * @var SC_T::DAT + * Offset: 0x00 SC Receive/Transmit Holding Buffer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DAT |Receive/Transmit Holding Buffer + * | | |Write Operation: + * | | |By writing data to DAT, the SC will send out an 8-bit data. + * | | |Note: If SCEN (SCn_CTL[0]) is not enabled, DAT cannot be programmed. + * | | |Read Operation: + * | | |By reading DAT, the SC will return an 8-bit received data. + * @var SC_T::CTL + * Offset: 0x04 SC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SCEN |SC Controller Enable Bit + * | | |Set this bit to 1 to enable SC operation. If this bit is cleared, + * | | |0 = SC will force all transition to IDLE state. + * | | |1 = SC controller is enabled and all function can work correctly. + * | | |Note1: SCEN must be set to 1 before filling in other SC registers, or smart card will not work properly. + * |[1] |RXOFF |RX Transition Disable Control Bit + * | | |This bit is used for disable Rx transition function. + * | | |0 = The receiver Enabled. + * | | |1 = The receiver Disabled. + * | | |Note1: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored. + * |[2] |TXOFF |TX Transition Disable Control Bit + * | | |This bit is used for disable Tx transition function. + * | | |0 = The transceiver Enabled. + * | | |1 = The transceiver Disabled. + * |[3] |AUTOCEN |Auto Convention Enable Bit + * | | |This bit is used for enable auto convention function. + * | | |0 = Auto-convention Disabled. + * | | |1 = Auto-convention Enabled. + * | | |If user enables auto convention function, the setting step must be done before Answer to Reset (ATR) + * | | |state and the first data must be 0x3B or 0x3F. + * | | |After hardware received first data and stored it at buffer, hardware will decided the convention and + * | | |change the CONSEL (SCn_CTL[5:4]) bits automatically when received first data is 0x3B or 0x3F. + * | | |If received first byte is 0x3B, TS is direct convention, CONSEL (SCn_CTL[5:4]) will be set to 00 + * | | |automatically, otherwise the TS is inverse convention, and CONSEL (SCn_CTL[5:4]) will be set to 11. + * | | |If the first data is not 0x3B or 0x3F, hardware will set ACERRIF (SCn_INTSTS[10]) and generate an + * | | |interrupt to CPU when ACERRIEN (SCn_INTEN[10]) is enabled. + * |[5:4] |CONSEL |Convention Selection + * | | |00 = Direct convention. + * | | |01 = Reserved. + * | | |10 = Reserved. + * | | |11 = Inverse convention. + * | | |Note: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored. + * |[7:6] |RXTRGLV |Rx Buffer Trigger Level + * | | |When the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set + * | | |If RDAIEN (SCn_INTEN[0]) is enabled, an interrupt will be generated to CPU. + * | | |00 = Rx Buffer Trigger Level with 01 bytes. + * | | |01 = Rx Buffer Trigger Level with 02 bytes. + * | | |10 = Rx Buffer Trigger Level with 03 bytes. + * | | |11 = Reserved. + * |[12:8] |BGT |Block Guard Time (BGT) + * | | |Block guard time means the minimum interval between the leading edges of two consecutive characters + * | | |between different transfer directions + * | | |This field indicates the counter for the bit length of block guard time + * | | |According to ISO 7816-3, in T = 0 mode, user must fill 15 (real block guard time = 16.5) to this + * | | |field; in T = 1 mode, user must fill 21 (real block guard time = 22.5) to it. + * | | |Note: The real block guard time is BGT + 1. + * |[14:13] |TMRSEL |Timer Channel Selection + * | | |00 = All internal timer function Disabled. + * | | |11 = Internal 24 bit timer and two 8 bit timers Enabled + * | | |User can configure them by setting SCn_TMRCTL0[23:0], SCn_TMRCTL1[7:0] and SCn_TMRCTL2[7:0]. + * | | |Other configurations are reserved + * |[15] |NSB |Stop Bit Length + * | | |This field indicates the length of stop bit. + * | | |0 = The stop bit length is 2 ETU. + * | | |1= The stop bit length is 1 ETU. + * | | |Note1: The default stop bit length is 2. SC and UART adopts NSB to program the stop bit length. + * | | |Note2: In UART mode, RX can receive the data sequence in 1 stop bit or 2 stop bits with NSB is set to 0. + * |[18:16] |RXRTY |RX Error Retry Count Number + * | | |This field indicates the maximum number of receiver retries that are allowed when parity error has occurred. + * | | |Note1: The real retry number is RXRTY + 1, so 8 is the maximum retry number. + * | | |Note2: This field cannot be changed when RXRTYEN enabled + * | | |The change flow is to disable RXRTYEN first and then fill in new retry value. + * |[19] |RXRTYEN |RX Error Retry Enable Bit + * | | |This bit enables receiver retry function when parity error has occurred. + * | | |0 = RX error retry function Disabled. + * | | |1 = RX error retry function Enabled. + * | | |Note: User must fill in the RXRTY value before enabling this bit. + * |[22:20] |TXRTY |TX Error Retry Count Number + * | | |This field indicates the maximum number of transmitter retries that are allowed when parity + * | | |error has occurred. + * | | |Note1: The real retry number is TXRTY + 1, so 8 is the maximum retry number. + * | | |Note2: This field cannot be changed when TXRTYEN enabled + * | | |The change flow is to disable TXRTYEN first and then fill in new retry value. + * |[23] |TXRTYEN |TX Error Retry Enable Bit + * | | |This bit enables transmitter retry function when parity error has occurred. + * | | |0 = TX error retry function Disabled. + * | | |1 = TX error retry function Enabled. + * |[25:24] |CDDBSEL |Card Detect De-bounce Selection + * | | |This field indicates the card detect de-bounce selection. + * | | |00 = De-bounce sample card insert once per 384 (128 * 3) SC module clocks and de-bounce + * | | |sample card removal once per 128 SC module clocks. + * | | |Other configurations are reserved. + * |[26] |CDLV |Card Detect Level Selection + * | | |0 = When hardware detects the card detect pin (SCn_CD) from high to low, it indicates a card is detected. + * | | |1 = When hardware detects the card detect pin (SCn_CD) from low to high, it indicates a card is detected. + * | | |Note: User must select card detect level before Smart Card controller enabled. + * |[30] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, user should check this bit before writing a new value to RXRTY and TXRTY fields. + * | | |0 = Synchronizing is completion, user can write new data to RXRTY and TXRTY. + * | | |1 = Last value is synchronizing. + * @var SC_T::ALTCTL + * Offset: 0x08 SC Alternate Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TXRST |TX Software Reset + * | | |When TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared. + * | | |0 = No effect. + * | | |1 = Reset the TX internal state machine and pointers. + * | | |Note: This bit will be auto cleared after reset is complete. + * |[1] |RXRST |Rx Software Reset + * | | |When RXRST is set, all the bytes in the receive buffer and Rx internal state machine will be cleared. + * | | |0 = No effect. + * | | |1 = Reset the Rx internal state machine and pointers. + * | | |Note: This bit will be auto cleared after reset is complete. + * |[2] |DACTEN |Deactivation Sequence Generator Enable Bit + * | | |This bit enables SC controller to initiate the card by deactivation sequence. + * | | |0 = No effect. + * | | |1 = Deactivation sequence generator Enabled. + * | | |Note1: When the deactivation sequence completed, this bit will be cleared automatically and + * | | |the INITIF (SCn_INTSTS[8]) will be set to 1. + * | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]) + * | | |Thus, do not fill in this bit DACTEN, TXRST and RXRST at the same time. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * |[3] |ACTEN |Activation Sequence Generator Enable Bit + * | | |This bit enables SC controller to initiate the card by activation sequence. + * | | |0 = No effect. + * | | |1 = Activation sequence generator Enabled. + * | | |Note1: When the activation sequence completed, this bit will be cleared automatically and the + * | | |INITIF (SCn_INTSTS[8]) will be set to 1. + * | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]) + * | | |Thus, do not fill in this bit ACTEN, TXRST and RXRST at the same time. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * | | |Note4: During the activation sequence, RX is disabled automatically and can not receive data + * | | |After the activation sequence completion, RXOFF (SCn_CTL[1]) keeps the state before hardware activation. + * |[4] |WARSTEN |Warm Reset Sequence Generator Enable Bit + * | | |This bit enables SC controller to initiate the card by warm reset sequence. + * | | |0 = No effect. + * | | |1 = Warm reset sequence generator Enabled. + * | | |Note1: When the warm reset sequence completed, this bit will be cleared automatically and the + * | | |INITIF (SCn_INTSTS[8]) will be set to 1. + * | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]) + * | | |Thus, do not fill in this bit WARSTEN, TXRST and RXRST at the same time. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * | | |Note4: During the warm reset sequence, RX is disabled automatically and can not receive data + * | | |After the warm reset sequence completion, RXOFF (SCn_CTL[1]) keeps the state before perform + * | | |warm reset sequence. + * |[5] |CNTEN0 |Internal Timer0 Start Enable Bit + * | | |This bit enables Timer 0 to start counting + * | | |User can fill 0 to stop it and set 1 to reload and count + * | | |The counter unit is ETU base. + * | | |0 = Stops counting. + * | | |1 = Start counting. + * | | |Note1: This field is used for internal 24 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only. + * | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL0[26] = 0), this bit will + * | | |be auto-cleared by hardware. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * |[6] |CNTEN1 |Internal Timer1 Start Enable Bit + * | | |This bit enables Timer 1 to start counting + * | | |User can fill 0 to stop it and set 1 to reload and count + * | | |The counter unit is ETU base. + * | | |0 = Stops counting. + * | | |1 = Start counting. + * | | |Note1: This field is used for internal 8 bit timer when TMRSEL(SCn_CTL[14:13]) is 11 only + * | | |Do not fill CNTEN1 when TMRSEL (SCn_CTL[14:13]) is not equal to 11. + * | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL1[26] = 0), this bit will + * | | |be auto-cleared by hardware. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * |[7] |CNTEN2 |Internal Timer2 Start Enable Bit + * | | |This bit enables Timer 2 to start counting + * | | |User can fill 0 to stop it and set 1 to reload and count + * | | |The counter unit is ETU base. + * | | |0 = Stops counting. + * | | |1 = Start counting. + * | | |Note1: This field is used for internal 8 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only + * | | |Do not fill in CNTEN2 when TMRSEL (SCn_CTL[14:13]) is not equal to 11. + * | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL2[26] = 0), this bit will + * | | |be auto-cleared by hardware. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * |[9:8] |INITSEL |Initial Timing Selection + * | | |This fields indicates the initial timing of hardware activation, warm-reset or deactivation. + * | | |The unit of initial timing is SC module clock. + * | | |Activation: refer to SC Activation Sequence in Figure 7.17-54. + * | | |Warm-reset: refer to Warm-Reset Sequence in Figure 7.17-5. + * | | |Deactivation: refer to Deactivation Sequence in Figure 7.17-56. + * | | |Note: When set activation and warm reset in Timer0 operation mode 0011, it may have deviation + * | | |at most 128 SC module clock cycles. + * |[11] |ADACEN |Auto Deactivation When Card Removal + * | | |This bit is used for enable hardware auto deactivation when smart card is removed. + * | | |0 = Auto deactivation Disabled. + * | | |1 = Auto deactivation Enabled. + * | | |Note: When the card is removed, hardware will stop any process and then do deactivation sequence + * | | |if this bit is set + * | | |If auto deactivation process completes, hardware will set INITIF (SCn_INTSTS[8]) also. + * |[12] |RXBGTEN |Receiver Block Guard Time Function Enable Bit + * | | |This bit enables the receiver block guard time function. + * | | |0 = Receiver block guard time function Disabled. + * | | |1 = Receiver block guard time function Enabled. + * |[13] |ACTSTS0 |Internal Timer0 Active Status (Read Only) + * | | |This bit indicates the timer counter status of timer0. + * | | |0 = Timer0 is not active. + * | | |1 = Timer0 is active. + * | | |Note: Timer0 is active does not always mean timer0 is counting the CNT (SCn_TMRCTL0[23:0]). + * |[14] |ACTSTS1 |Internal Timer1 Active Status (Read Only) + * | | |This bit indicates the timer counter status of timer1. + * | | |0 = Timer1 is not active. + * | | |1 = Timer1 is active. + * | | |Note: Timer1 is active does not always mean timer1 is counting the CNT (SCn_TMRCTL1[7:0]). + * |[15] |ACTSTS2 |Internal Timer2 Active Status (Read Only) + * | | |This bit indicates the timer counter status of timer2. + * | | |0 = Timer2 is not active. + * | | |1 = Timer2 is active. + * | | |Note: Timer2 is active does not always mean timer2 is counting the CNT (SCn_TMRCTL2[7:0]). + * |[31] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, user should check this bit when writing a new value to SCn_ALTCTL register. + * | | |0 = Synchronizing is completion, user can write new data to SCn_ALTCTL register. + * | | |1 = Last value is synchronizing. + * @var SC_T::EGT + * Offset: 0x0C SC Extra Guard Time Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |EGT |Extra Guard Time + * | | |This field indicates the extra guard time value. + * | | |Note: The extra guard time unit is ETU base. + * @var SC_T::RXTOUT + * Offset: 0x10 SC Receive Buffer Time-out Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |RFTM |SC Receiver FIFO Time-out Counter + * | | |The time-out down counter resets and starts counting whenever the RX buffer received a new data + * | | |Once the counter decrease to 1 and no new data is received or CPU does not read data by + * | | |reading SCn_DAT, a receiver time-out flag RBTOIF (SCn_INTSTS[9]) will be set, and hardware will + * | | |generate an interrupt to CPU when RBTOIEN (SCn_INTEN[9]) is enabled. + * | | |Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5. + * | | |Note2: Filling in all 0 to this field indicates to disable this function. + * @var SC_T::ETUCTL + * Offset: 0x14 SC Element Time Unit Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |ETURDIV |ETU Rate Divider + * | | |The field is used for ETU clock rate divider. + * | | |The real ETU is ETURDIV + 1. + * | | |Note: User can configure this field, but this field must be greater than 0x04. + * @var SC_T::INTEN + * Offset: 0x18 SC Interrupt Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDAIEN |Receive Data Reach Interrupt Enable Bit + * | | |This field is used to enable received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt. + * | | |0 = Receive data reach trigger level interrupt Disabled. + * | | |1 = Receive data reach trigger level interrupt Enabled. + * |[1] |TBEIEN |Transmit Buffer Empty Interrupt Enable Bit + * | | |This field is used to enable transmit buffer empty interrupt. + * | | |0 = Transmit buffer empty interrupt Disabled. + * | | |1 = Transmit buffer empty interrupt Enabled. + * |[2] |TERRIEN |Transfer Error Interrupt Enable Bit + * | | |This field is used to enable transfer error interrupt + * | | |The transfer error states is at SCn_STATUS register which includes receiver break error + * | | |BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5]), parity error PEF (SCn_STATUS[4]), receive + * | | |buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), + * | | |receiver retry over limit error RXOVERR (SCn_STATUS[22]) and transmitter retry over limit error + * | | |TXOVERR (SCn_STATUS[30]). + * | | |0 = Transfer error interrupt Disabled. + * | | |1 = Transfer error interrupt Enabled. + * |[3] |TMR0IEN |Timer0 Interrupt Enable Bit + * | | |This field is used to enable Timer0 interrupt function. + * | | |0 = Timer0 interrupt Disabled. + * | | |1 = Timer0 interrupt Enabled. + * |[4] |TMR1IEN |Timer1 Interrupt Enable Bit + * | | |This field is used to enable the Timer1 interrupt function. + * | | |0 = Timer1 interrupt Disabled. + * | | |1 = Timer1 interrupt Enabled. + * |[5] |TMR2IEN |Timer2 Interrupt Enable Bit + * | | |This field is used to enable Timer2 interrupt function. + * | | |0 = Timer2 interrupt Disabled. + * | | |1 = Timer2 interrupt Enabled. + * |[6] |BGTIEN |Block Guard Time Interrupt Enable Bit + * | | |This field is used to enable block guard time interrupt in receive direction. + * | | |0 = Block guard time interrupt Disabled. + * | | |1 = Block guard time interrupt Enabled. + * | | |Note: This bit is valid only for receive direction block guard time. + * |[7] |CDIEN |Card Detect Interrupt Enable Bit + * | | |This field is used to enable card detect interrupt + * | | |The card detect status is CDPINSTS (SCn_STATUS[13]). + * | | |0 = Card detect interrupt Disabled. + * | | |1 = Card detect interrupt Enabled. + * |[8] |INITIEN |Initial End Interrupt Enable Bit + * | | |This field is used to enable activation (ACTEN (SCn_ALTCTL[3] = 1)), deactivation + * | | |(DACTEN (SCn_ALTCTL[2] = 1)) and warm reset (WARSTEN (SCn_ALTCTL [4])) sequence complete interrupt. + * | | |0 = Initial end interrupt Disabled. + * | | |1 = Initial end interrupt Enabled. + * |[9] |RXTOIEN |Receiver Buffer Time-out Interrupt Enable Bit + * | | |This field is used to enable receiver buffer time-out interrupt. + * | | |0 = Receiver buffer time-out interrupt Disabled. + * | | |1 = Receiver buffer time-out interrupt Enabled. + * |[10] |ACERRIEN |Auto Convention Error Interrupt Enable Bit + * | | |This field is used to enable auto-convention error interrupt. + * | | |0 = Auto-convention error interrupt Disabled. + * | | |1 = Auto-convention error interrupt Enabled. + * @var SC_T::INTSTS + * Offset: 0x1C SC Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDAIF |Receive Data Reach Interrupt Status Flag (Read Only) + * | | |This field is used for received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt status flag. + * | | |0 = Number of receive buffer is less than RXTRGLV setting. + * | | |1 = Number of receive buffer data equals the RXTRGLV setting. + * | | |Note: This bit is read only + * | | |If user reads data from SCn_DAT and receiver buffer data byte number is less than RXTRGLV, + * | | |this bit will be cleared automatically. + * |[1] |TBEIF |Transmit Buffer Empty Interrupt Status Flag (Read Only) + * | | |This field is used for transmit buffer empty interrupt status flag. + * | | |0 = Transmit buffer is not empty. + * | | |1 = Transmit buffer is empty. + * | | |Note: This bit is read only + * | | |If user wants to clear this bit, user must write data to DAT (SCn_DAT[7:0]) and then this bit + * | | |will be cleared automatically. + * |[2] |TERRIF |Transfer Error Interrupt Status Flag + * | | |This field is used for transfer error interrupt status flag + * | | |The transfer error states is at SCn_STATUS register which includes receiver break error + * | | |BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5], parity error PEF (SCn_STATUS[4] and receive + * | | |buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), + * | | |receiver retry over limit error RXOVERR (SCn_STATUS[22] or transmitter retry over limit error + * | | |TXOVERR (SCn_STATUS[30]). + * | | |0 = Transfer error interrupt did not occur. + * | | |1 = Transfer error interrupt occurred. + * | | |Note1: This field is the status flag of BEF, FEF, PEF, RXOV, TXOV, RXOVERR or TXOVERR. + * | | |Note2: This bit can be cleared by writing 1 to it. + * |[3] |TMR0IF |Timer0 Interrupt Status Flag + * | | |This field is used for Timer0 interrupt status flag. + * | | |0 = Timer0 interrupt did not occur. + * | | |1 = Timer0 interrupt occurred. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[4] |TMR1IF |Timer1 Interrupt Status Flag + * | | |This field is used for Timer1 interrupt status flag. + * | | |0 = Timer1 interrupt did not occur. + * | | |1 = Timer1 interrupt occurred. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[5] |TMR2IF |Timer2 Interrupt Status Flag + * | | |This field is used for Timer2 interrupt status flag. + * | | |0 = Timer2 interrupt did not occur. + * | | |1 = Timer2 interrupt occurred. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[6] |BGTIF |Block Guard Time Interrupt Status Flag + * | | |This field is used for indicate block guard time interrupt status flag in receive direction. + * | | |0 = Block guard time interrupt did not occur. + * | | |1 = Block guard time interrupt occurred. + * | | |Note1: This bit is valid only when RXBGTEN (SCn_ALTCTL[12]) is enabled. + * | | |Note2: This bit can be cleared by writing 1 to it. + * |[7] |CDIF |Card Detect Interrupt Status Flag (Read Only) + * | | |This field is used for card detect interrupt status flag + * | | |The card detect status is CINSERT (SCn_STATUS[12]) and CREMOVE (SCn_STATUS[11]). + * | | |0 = Card detect event did not occur. + * | | |1 = Card detect event occurred. + * | | |Note: This bit is read only, user must to clear CINSERT or CREMOVE status to clear it. + * |[8] |INITIF |Initial End Interrupt Status Flag + * | | |This field is used for activation (ACTEN (SCn_ALTCTL[3])), deactivation (DACTEN (SCn_ALTCTL[2])) + * | | |and warm reset (WARSTEN (SCn_ALTCTL[4])) sequence interrupt status flag. + * | | |0 = Initial sequence is not complete. + * | | |1 = Initial sequence is completed. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[9] |RXTOIF |Receive Buffer Time-out Interrupt Status Flag (Read Only) + * | | |This field is used for indicate receive buffer time-out interrupt status flag. + * | | |0 = Receive buffer time-out interrupt did not occur. + * | | |1 = Receive buffer time-out interrupt occurred. + * | | |Note: This bit is read only, user must read all receive buffer remaining data by reading SCn_DAT + * | | |register to clear it. + * |[10] |ACERRIF |Auto Convention Error Interrupt Status Flag + * | | |This field indicates auto convention sequence error. + * | | |0 = Received TS at ATR state is 0x3B or 0x3F. + * | | |1 = Received TS at ATR state is neither 0x3B nor 0x3F. + * | | |Note: This bit can be cleared by writing 1 to it. + * @var SC_T::STATUS + * Offset: 0x20 SC Transfer Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXOV |Receive Overflow Error Status Flag + * | | |This bit is set when Rx buffer overflow. + * | | |0 = Rx buffer is not overflow. + * | | |1 = Rx buffer is overflow when the number of received bytes is greater than Rx buffer size (4 bytes). + * | | |Note: This bit can be cleared by writing 1 to it. + * |[1] |RXEMPTY |Receive Buffer Empty Status Flag (Read Only) + * | | |This bit indicates Rx buffer empty or not. + * | | |0 = Rx buffer is not empty. + * | | |1 = Rx buffer is empty, it means the last byte of Rx buffer has read from DAT (SCn_DAT[7:0]) by CPU. + * |[2] |RXFULL |Receive Buffer Full Status Flag (Read Only) + * | | |This bit indicates Rx buffer full or not. + * | | |0 = Rx buffer count is less than 4. + * | | |1 = Rx buffer count equals to 4. + * |[4] |PEF |Receiver Parity Error Status Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid parity bit. + * | | |0 = Receiver parity error flag did not occur. + * | | |1 = Receiver parity error flag occurred. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not + * | | |set this flag. + * |[5] |FEF |Receiver Frame Error Status Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, + * | | |the stop bit following the last data bit or parity bit is detected as logic 0). + * | | |0 = Receiver frame error flag did not occur. + * | | |1 = Receiver frame error flag occurred. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not + * | | |set this flag. + * |[6] |BEF |Receiver Break Error Status Flag + * | | |This bit is set to logic 1 whenever the received data input (Rx) held in the spacing state + * | | |(logic 0) is longer than a full word transmission time (that is, the total time of start bit + + * | | |data bits + parity bit + stop bit). + * | | |0 = Receiver break error flag did not occur. + * | | |1 = Receiver break error flag occurred. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set + * | | |this flag. + * |[8] |TXOV |Transmit Overflow Error Interrupt Status Flag + * | | |This bit is set when Tx buffer overflow. + * | | |0 = Tx buffer is not overflow. + * | | |1 = Tx buffer is overflow when Tx buffer is full and an additional write operation to DAT (SCn_DAT[7:0]). + * | | |Note: This bit can be cleared by writing 1 to it. + * |[9] |TXEMPTY |Transmit Buffer Empty Status Flag (Read Only) + * | | |This bit indicates TX buffer empty or not. + * | | |0 = Tx buffer is not empty. + * | | |1 = Tx buffer is empty, it means the last byte of Tx buffer has been transferred to Transmitter + * | | |Shift Register. + * | | |Note: This bit will be cleared when writing data into DAT (SCn_DAT[7:0]). + * |[10] |TXFULL |Transmit Buffer Full Status Flag (Read Only) + * | | |This bit indicates Tx buffer full or not. + * | | |0 = Tx buffer count is less than 4. + * | | |1 = Tx buffer count equals to 4. + * |[11] |CREMOVE |Card Removal Status of SCn_CD Pin + * | | |This bit is set whenever card has been removal. + * | | |0 = No effect. + * | | |1 = Card removed. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: Card detect function will start after SCEN (SCn_CTL[0]) set. + * |[12] |CINSERT |Card Insert Status of SCn_CD Pin + * | | |This bit is set whenever card has been inserted. + * | | |0 = No effect. + * | | |1 = Card insert. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: The card detect function will start after SCEN (SCn_CTL[0]) set. + * |[13] |CDPINSTS |Card Detect Pin Status (Read Only) + * | | |This bit is the pin status of SCn_CD. + * | | |0 = The SCn_CD pin state at low. + * | | |1 = The SCn_CD pin state at high. + * |[18:16] |RXPOINT |Receive Buffer Pointer Status (Read Only) + * | | |This field indicates the Rx buffer pointer status + * | | |When SC controller receives one byte from external device, RXPOINT increases one + * | | |When one byte of Rx buffer is read by CPU, RXPOINT decreases one. + * |[21] |RXRERR |Receiver Retry Error + * | | |This bit is used for receiver error retry and set by hardware. + * | | |0 = No Rx retry transfer. + * | | |1 = Rx has any error and retries transfer. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2 This bit is a flag and cannot generate any interrupt to CPU. + * | | |Note3: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), + * | | |hardware will not set this flag. + * |[22] |RXOVERR |Receiver over Retry Error + * | | |This bit is used for receiver retry counts over than retry number limitation. + * | | |0 = Receiver retries counts is not over than RXRTY (SCn_CTL[18:16]) + 1. + * | | |1 = Receiver retries counts over than RXRTY (SCn_CTL[18:16]) + 1. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware + * | | |will not set this flag. + * |[23] |RXACT |Receiver in Active Status Flag (Read Only) + * | | |This bit indicates Rx transfer status. + * | | |0 = This bit is cleared automatically when Rx transfer is finished. + * | | |1 = This bit is set by hardware when Rx transfer is in active. + * | | |Note: This bit is read only. + * |[26:24] |TXPOINT |Transmit Buffer Pointer Status (Read Only) + * | | |This field indicates the Tx buffer pointer status + * | | |When CPU writes data into SCn_DAT, TXPOINT increases one + * | | |When one byte of Tx buffer is transferred to transmitter shift register, TXPOINT decreases one. + * |[29] |TXRERR |Transmitter Retry Error + * | | |This bit is used for indicate transmitter error retry and set by hardware. + * | | |0 = No Tx retry transfer. + * | | |1 = Tx has any error and retries transfer. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: This bit is a flag and cannot generate any interrupt to CPU. + * |[30] |TXOVERR |Transmitter over Retry Error + * | | |This bit is used for transmitter retry counts over than retry number limitation. + * | | |0 = Transmitter retries counts is not over than TXRTY (SCn_CTL[22:20]) + 1. + * | | |1 = Transmitter retries counts over than TXRTY (SCn_CTL[22:20]) + 1. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[31] |TXACT |Transmit in Active Status Flag (Read Only) + * | | |This bit indicates Tx transmit status. + * | | |0 = This bit is cleared automatically when Tx transfer is finished or the last byte transmission + * | | |has completed. + * | | |1 = Transmit is active and this bit is set by hardware when Tx transfer is in active and the STOP + * | | |bit of the last byte has not been transmitted. + * | | |Note: This bit is read only. + * @var SC_T::PINCTL + * Offset: 0x24 SC Pin Control State Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PWREN |SCn_PWR Pin Signal + * | | |User can set PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]) to decide SCn_PWR pin is in high or low level. + * | | |Write this field to drive SCn_PWR pin + * | | |Refer PWRINV (SCn_PINCTL[11]) description for programming SCn_PWR pin voltage level. + * | | |Read this field to get SCn_PWR signal status. + * | | |0 = SCn_PWR signal status is low. + * | | |1 = SCn_PWR signal status is high. + * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. + * | | |Thus, do not fill in this field when operating in these modes. + * |[1] |RSTEN |SCn_RST Pin Signal + * | | |User can set RSTEN (SCn_PINCTL[1]) to decide SCn_RST pin is in high or low level. + * | | |Write this field to drive SCn_RST pin. + * | | |0 = Drive SCn_RST pin to low. + * | | |1 = Drive SCn_RST pin to high. + * | | |Read this field to get SCn_RST signal status. + * | | |0 = SCn_RST signal status is low. + * | | |1 = SCn_RST signal status is high. + * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. + * | | |Thus, do not fill in this field when operating in these modes. + * |[6] |CLKKEEP |SC Clock Enable Bit + * | | |0 = SC clock generation Disabled. + * | | |1 = SC clock always keeps free running. + * | | |Note: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically. + * | | |Thus, do not fill in this field when operating in these modes. + * |[9] |SCDATA |SCn_DATA Pin Signal + * | | |This bit is the signal status of SCn_DATA but user can drive SCn_DATA pin to high or low by setting this bit. + * | | |0 = Drive SCn_DATA pin to low. + * | | |1 = Drive SCn_DATA pin to high. + * | | |Read this field to get SCn_DATA signal status. + * | | |0 = SCn_DATA signal status is low. + * | | |1 = SCn_DATA signal status is high. + * | | |Note: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically. + * | | |Thus, do not fill in this field when SC is in these modes. + * |[11] |PWRINV |SCn_PWR Pin Inverse + * | | |This bit is used for inverse the SCn_PWR pin. + * | | |There are four kinds of combination for SCn_PWR pin setting by PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]). + * | | |PWRINV is 0 and PWREN is 0, SCn_PWR pin is 0. + * | | |PWRINV is 0 and PWREN is 1, SCn_PWR pin is 1. + * | | |PWRINV is 1 and PWREN is 0, SCn_PWR pin is 1. + * | | |PWRINV is 1 and PWREN is 1, SCn_PWR pin is 0. + * | | |Note: User must select PWRINV (SCn_PINCTL[11]) before smart card is enabled by SCEN (SCn_CTL[0]). + * |[16] |DATASTS |SCn_DATA Pin Status (Read Only) + * | | |This bit is the pin status of SCn_DATA. + * | | |0 = The SCn_DATA pin status is low. + * | | |1 = The SCn_DATA pin status is high. + * |[17] |PWRSTS |SCn_PWR Pin Status (Read Only) + * | | |This bit is the pin status of SCn_PWR. + * | | |0 = SCn_PWR pin to low. + * | | |1 = SCn_PWR pin to high. + * |[18] |RSTSTS |SCn_RST Pin Status (Read Only) + * | | |This bit is the pin status of SCn_RST. + * | | |0 = SCn_RST pin is low. + * | | |1 = SCn_RST pin is high. + * |[30] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, user should check this bit when writing a new value to SCn_PINCTL register. + * | | |0 = Synchronizing is completion, user can write new data to SCn_PINCTL register. + * | | |1 = Last value is synchronizing. + * @var SC_T::TMRCTL0 + * Offset: 0x28 SC Internal Timer0 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CNT |Timer0 Counter Value + * | | |This field indicates the internal Timer0 counter values. + * | | |Note: Unit of Timer0 counter is ETU base. + * |[27:24] |OPMODE |Timer0 Operation Mode Selection + * | | |This field indicates the internal 24-bit Timer0 operation selection. + * | | |Refer to Table 7.17-3 for programming Timer0. + * |[31] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, user should check this bit when writing a new value to the SCn_TMRCTL0 register. + * | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL0 register. + * | | |1 = Last value is synchronizing. + * @var SC_T::TMRCTL1 + * Offset: 0x2C SC Internal Timer1 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |CNT |Timer 1 Counter Value + * | | |This field indicates the internal Timer1 counter values. + * | | |Note: Unit of Timer1 counter is ETU base. + * |[27:24] |OPMODE |Timer 1 Operation Mode Selection + * | | |This field indicates the internal 8-bit Timer1 operation selection. + * | | |Refer to Table 7.17-3 for programming Timer1. + * |[31] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, software should check this bit when writing a new value to SCn_TMRCTL1 register. + * | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL1 register. + * | | |1 = Last value is synchronizing. + * @var SC_T::TMRCTL2 + * Offset: 0x30 SC Internal Timer2 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |CNT |Timer 2 Counter Value + * | | |This field indicates the internal Timer2 counter values. + * | | |Note: Unit of Timer2 counter is ETU base. + * |[27:24] |OPMODE |Timer 2 Operation Mode Selection + * | | |This field indicates the internal 8-bit Timer2 operation selection + * | | |Refer to Table 7.17-3 for programming Timer2. + * |[31] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, user should check this bit when writing a new value to SCn_TMRCTL2 register. + * | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL2 register. + * | | |1 = Last value is synchronizing. + * @var SC_T::UARTCTL + * Offset: 0x34 SC UART Mode Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |UARTEN |UART Mode Enable Bit + * | | |Sets this bit to enable UART mode function. + * | | |0 = Smart Card mode. + * | | |1 = UART mode. + * | | |Note1: When operating in UART mode, user must set CONSEL (SCn_CTL[5:4]) = 00 and AUTOCEN (SCn_CTL[3]) = 0. + * | | |Note2: When operating in Smart Card mode, user must set UARTEN (SCn_UARTCTL[0]) = 0. + * | | |Note3: When UART mode is enabled, hardware will generate a reset to reset FIFO and internal state machine. + * |[5:4] |WLS |Word Length Selection + * | | |This field is used for select UART data length. + * | | |00 = Word length is 8 bits. + * | | |01 = Word length is 7 bits. + * | | |10 = Word length is 6 bits. + * | | |11 = Word length is 5 bits. + * | | |Note: In smart card mode, this WLS must be '00'. + * |[6] |PBOFF |Parity Bit Disable Control + * | | |Sets this bit is used for disable parity check function. + * | | |0 = Parity bit is generated or checked between the last data word bit and stop bit of the serial data. + * | | |1 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer. + * | | |Note: In smart card mode, this field must be '0' (default setting is with parity bit). + * |[7] |OPE |Odd Parity Enable Bit + * | | |This is used for odd/even parity selection. + * | | |0 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode. + * | | |1 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode. + * | | |Note: This bit has effect only when PBOFF bit is '0'. + * @var SC_T::ACTCTL + * Offset: 0x4C SC Activation Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |T1EXT |T1 Extend Time of Hardware Activation + * | | |This field provide the configurable cycles to extend the activation time T1 period. + * | | |The cycle scaling factor is 2048. + * | | |Extend cycles = (filled value * 2048) cycles. + * | | |Refer to SC activation sequence in Figure 7.17-4. + * | | |For example, + * | | |SCLK = 4MHz, each cycle = 0.25us,. + * | | |Filled 20 to this field + * | | |Extend time = 20 * 2048 * 0.25us = 10.24 ms. + * | | |Note: Setting 0 to this field conforms to the protocol ISO/IEC 7816-3 + */ + __IO uint32_t DAT; /*!< [0x0000] SC Receive/Transmit Holding Buffer Register */ + __IO uint32_t CTL; /*!< [0x0004] SC Control Register */ + __IO uint32_t ALTCTL; /*!< [0x0008] SC Alternate Control Register */ + __IO uint32_t EGT; /*!< [0x000c] SC Extra Guard Time Register */ + __IO uint32_t RXTOUT; /*!< [0x0010] SC Receive Buffer Time-out Counter Register */ + __IO uint32_t ETUCTL; /*!< [0x0014] SC Element Time Unit Control Register */ + __IO uint32_t INTEN; /*!< [0x0018] SC Interrupt Enable Control Register */ + __IO uint32_t INTSTS; /*!< [0x001c] SC Interrupt Status Register */ + __IO uint32_t STATUS; /*!< [0x0020] SC Transfer Status Register */ + __IO uint32_t PINCTL; /*!< [0x0024] SC Pin Control State Register */ + __IO uint32_t TMRCTL0; /*!< [0x0028] SC Internal Timer0 Control Register */ + __IO uint32_t TMRCTL1; /*!< [0x002c] SC Internal Timer1 Control Register */ + __IO uint32_t TMRCTL2; /*!< [0x0030] SC Internal Timer2 Control Register */ + __IO uint32_t UARTCTL; /*!< [0x0034] SC UART Mode Control Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE0[5]; + /** @endcond */ + __IO uint32_t ACTCTL; /*!< [0x004c] SC Activation Control Register */ + +} SC_T; + +/** + @addtogroup SC_CONST SC Bit Field Definition + Constant Definitions for SC Controller +@{ */ + +#define SC_DAT_DAT_Pos (0) /*!< SC_T::DAT: DAT Position */ +#define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos) /*!< SC_T::DAT: DAT Mask */ + +#define SC_CTL_SCEN_Pos (0) /*!< SC_T::CTL: SCEN Position */ +#define SC_CTL_SCEN_Msk (0x1ul << SC_CTL_SCEN_Pos) /*!< SC_T::CTL: SCEN Mask */ + +#define SC_CTL_RXOFF_Pos (1) /*!< SC_T::CTL: RXOFF Position */ +#define SC_CTL_RXOFF_Msk (0x1ul << SC_CTL_RXOFF_Pos) /*!< SC_T::CTL: RXOFF Mask */ + +#define SC_CTL_TXOFF_Pos (2) /*!< SC_T::CTL: TXOFF Position */ +#define SC_CTL_TXOFF_Msk (0x1ul << SC_CTL_TXOFF_Pos) /*!< SC_T::CTL: TXOFF Mask */ + +#define SC_CTL_AUTOCEN_Pos (3) /*!< SC_T::CTL: AUTOCEN Position */ +#define SC_CTL_AUTOCEN_Msk (0x1ul << SC_CTL_AUTOCEN_Pos) /*!< SC_T::CTL: AUTOCEN Mask */ + +#define SC_CTL_CONSEL_Pos (4) /*!< SC_T::CTL: CONSEL Position */ +#define SC_CTL_CONSEL_Msk (0x3ul << SC_CTL_CONSEL_Pos) /*!< SC_T::CTL: CONSEL Mask */ + +#define SC_CTL_RXTRGLV_Pos (6) /*!< SC_T::CTL: RXTRGLV Position */ +#define SC_CTL_RXTRGLV_Msk (0x3ul << SC_CTL_RXTRGLV_Pos) /*!< SC_T::CTL: RXTRGLV Mask */ + +#define SC_CTL_BGT_Pos (8) /*!< SC_T::CTL: BGT Position */ +#define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos) /*!< SC_T::CTL: BGT Mask */ + +#define SC_CTL_TMRSEL_Pos (13) /*!< SC_T::CTL: TMRSEL Position */ +#define SC_CTL_TMRSEL_Msk (0x3ul << SC_CTL_TMRSEL_Pos) /*!< SC_T::CTL: TMRSEL Mask */ + +#define SC_CTL_NSB_Pos (15) /*!< SC_T::CTL: NSB Position */ +#define SC_CTL_NSB_Msk (0x1ul << SC_CTL_NSB_Pos) /*!< SC_T::CTL: NSB Mask */ + +#define SC_CTL_RXRTY_Pos (16) /*!< SC_T::CTL: RXRTY Position */ +#define SC_CTL_RXRTY_Msk (0x7ul << SC_CTL_RXRTY_Pos) /*!< SC_T::CTL: RXRTY Mask */ + +#define SC_CTL_RXRTYEN_Pos (19) /*!< SC_T::CTL: RXRTYEN Position */ +#define SC_CTL_RXRTYEN_Msk (0x1ul << SC_CTL_RXRTYEN_Pos) /*!< SC_T::CTL: RXRTYEN Mask */ + +#define SC_CTL_TXRTY_Pos (20) /*!< SC_T::CTL: TXRTY Position */ +#define SC_CTL_TXRTY_Msk (0x7ul << SC_CTL_TXRTY_Pos) /*!< SC_T::CTL: TXRTY Mask */ + +#define SC_CTL_TXRTYEN_Pos (23) /*!< SC_T::CTL: TXRTYEN Position */ +#define SC_CTL_TXRTYEN_Msk (0x1ul << SC_CTL_TXRTYEN_Pos) /*!< SC_T::CTL: TXRTYEN Mask */ + +#define SC_CTL_CDDBSEL_Pos (24) /*!< SC_T::CTL: CDDBSEL Position */ +#define SC_CTL_CDDBSEL_Msk (0x3ul << SC_CTL_CDDBSEL_Pos) /*!< SC_T::CTL: CDDBSEL Mask */ + +#define SC_CTL_CDLV_Pos (26) /*!< SC_T::CTL: CDLV Position */ +#define SC_CTL_CDLV_Msk (0x1ul << SC_CTL_CDLV_Pos) /*!< SC_T::CTL: CDLV Mask */ + +#define SC_CTL_SYNC_Pos (30) /*!< SC_T::CTL: SYNC Position */ +#define SC_CTL_SYNC_Msk (0x1ul << SC_CTL_SYNC_Pos) /*!< SC_T::CTL: SYNC Mask */ + +#define SC_ALTCTL_TXRST_Pos (0) /*!< SC_T::ALTCTL: TXRST Position */ +#define SC_ALTCTL_TXRST_Msk (0x1ul << SC_ALTCTL_TXRST_Pos) /*!< SC_T::ALTCTL: TXRST Mask */ + +#define SC_ALTCTL_RXRST_Pos (1) /*!< SC_T::ALTCTL: RXRST Position */ +#define SC_ALTCTL_RXRST_Msk (0x1ul << SC_ALTCTL_RXRST_Pos) /*!< SC_T::ALTCTL: RXRST Mask */ + +#define SC_ALTCTL_DACTEN_Pos (2) /*!< SC_T::ALTCTL: DACTEN Position */ +#define SC_ALTCTL_DACTEN_Msk (0x1ul << SC_ALTCTL_DACTEN_Pos) /*!< SC_T::ALTCTL: DACTEN Mask */ + +#define SC_ALTCTL_ACTEN_Pos (3) /*!< SC_T::ALTCTL: ACTEN Position */ +#define SC_ALTCTL_ACTEN_Msk (0x1ul << SC_ALTCTL_ACTEN_Pos) /*!< SC_T::ALTCTL: ACTEN Mask */ + +#define SC_ALTCTL_WARSTEN_Pos (4) /*!< SC_T::ALTCTL: WARSTEN Position */ +#define SC_ALTCTL_WARSTEN_Msk (0x1ul << SC_ALTCTL_WARSTEN_Pos) /*!< SC_T::ALTCTL: WARSTEN Mask */ + +#define SC_ALTCTL_CNTEN0_Pos (5) /*!< SC_T::ALTCTL: CNTEN0 Position */ +#define SC_ALTCTL_CNTEN0_Msk (0x1ul << SC_ALTCTL_CNTEN0_Pos) /*!< SC_T::ALTCTL: CNTEN0 Mask */ + +#define SC_ALTCTL_CNTEN1_Pos (6) /*!< SC_T::ALTCTL: CNTEN1 Position */ +#define SC_ALTCTL_CNTEN1_Msk (0x1ul << SC_ALTCTL_CNTEN1_Pos) /*!< SC_T::ALTCTL: CNTEN1 Mask */ + +#define SC_ALTCTL_CNTEN2_Pos (7) /*!< SC_T::ALTCTL: CNTEN2 Position */ +#define SC_ALTCTL_CNTEN2_Msk (0x1ul << SC_ALTCTL_CNTEN2_Pos) /*!< SC_T::ALTCTL: CNTEN2 Mask */ + +#define SC_ALTCTL_INITSEL_Pos (8) /*!< SC_T::ALTCTL: INITSEL Position */ +#define SC_ALTCTL_INITSEL_Msk (0x3ul << SC_ALTCTL_INITSEL_Pos) /*!< SC_T::ALTCTL: INITSEL Mask */ + +#define SC_ALTCTL_ADACEN_Pos (11) /*!< SC_T::ALTCTL: ADACEN Position */ +#define SC_ALTCTL_ADACEN_Msk (0x1ul << SC_ALTCTL_ADACEN_Pos) /*!< SC_T::ALTCTL: ADACEN Mask */ + +#define SC_ALTCTL_RXBGTEN_Pos (12) /*!< SC_T::ALTCTL: RXBGTEN Position */ +#define SC_ALTCTL_RXBGTEN_Msk (0x1ul << SC_ALTCTL_RXBGTEN_Pos) /*!< SC_T::ALTCTL: RXBGTEN Mask */ + +#define SC_ALTCTL_ACTSTS0_Pos (13) /*!< SC_T::ALTCTL: ACTSTS0 Position */ +#define SC_ALTCTL_ACTSTS0_Msk (0x1ul << SC_ALTCTL_ACTSTS0_Pos) /*!< SC_T::ALTCTL: ACTSTS0 Mask */ + +#define SC_ALTCTL_ACTSTS1_Pos (14) /*!< SC_T::ALTCTL: ACTSTS1 Position */ +#define SC_ALTCTL_ACTSTS1_Msk (0x1ul << SC_ALTCTL_ACTSTS1_Pos) /*!< SC_T::ALTCTL: ACTSTS1 Mask */ + +#define SC_ALTCTL_ACTSTS2_Pos (15) /*!< SC_T::ALTCTL: ACTSTS2 Position */ +#define SC_ALTCTL_ACTSTS2_Msk (0x1ul << SC_ALTCTL_ACTSTS2_Pos) /*!< SC_T::ALTCTL: ACTSTS2 Mask */ + +#define SC_ALTCTL_SYNC_Pos (31) /*!< SC_T::ALTCTL: SYNC Position */ +#define SC_ALTCTL_SYNC_Msk (0x1ul << SC_ALTCTL_SYNC_Pos) /*!< SC_T::ALTCTL: SYNC Mask */ + +#define SC_EGT_EGT_Pos (0) /*!< SC_T::EGT: EGT Position */ +#define SC_EGT_EGT_Msk (0xfful << SC_EGT_EGT_Pos) /*!< SC_T::EGT: EGT Mask */ + +#define SC_RXTOUT_RFTM_Pos (0) /*!< SC_T::RXTOUT: RFTM Position */ +#define SC_RXTOUT_RFTM_Msk (0x1fful << SC_RXTOUT_RFTM_Pos) /*!< SC_T::RXTOUT: RFTM Mask */ + +#define SC_ETUCTL_ETURDIV_Pos (0) /*!< SC_T::ETUCTL: ETURDIV Position */ +#define SC_ETUCTL_ETURDIV_Msk (0xffful << SC_ETUCTL_ETURDIV_Pos) /*!< SC_T::ETUCTL: ETURDIV Mask */ + +#define SC_INTEN_RDAIEN_Pos (0) /*!< SC_T::INTEN: RDAIEN Position */ +#define SC_INTEN_RDAIEN_Msk (0x1ul << SC_INTEN_RDAIEN_Pos) /*!< SC_T::INTEN: RDAIEN Mask */ + +#define SC_INTEN_TBEIEN_Pos (1) /*!< SC_T::INTEN: TBEIEN Position */ +#define SC_INTEN_TBEIEN_Msk (0x1ul << SC_INTEN_TBEIEN_Pos) /*!< SC_T::INTEN: TBEIEN Mask */ + +#define SC_INTEN_TERRIEN_Pos (2) /*!< SC_T::INTEN: TERRIEN Position */ +#define SC_INTEN_TERRIEN_Msk (0x1ul << SC_INTEN_TERRIEN_Pos) /*!< SC_T::INTEN: TERRIEN Mask */ + +#define SC_INTEN_TMR0IEN_Pos (3) /*!< SC_T::INTEN: TMR0IEN Position */ +#define SC_INTEN_TMR0IEN_Msk (0x1ul << SC_INTEN_TMR0IEN_Pos) /*!< SC_T::INTEN: TMR0IEN Mask */ + +#define SC_INTEN_TMR1IEN_Pos (4) /*!< SC_T::INTEN: TMR1IEN Position */ +#define SC_INTEN_TMR1IEN_Msk (0x1ul << SC_INTEN_TMR1IEN_Pos) /*!< SC_T::INTEN: TMR1IEN Mask */ + +#define SC_INTEN_TMR2IEN_Pos (5) /*!< SC_T::INTEN: TMR2IEN Position */ +#define SC_INTEN_TMR2IEN_Msk (0x1ul << SC_INTEN_TMR2IEN_Pos) /*!< SC_T::INTEN: TMR2IEN Mask */ + +#define SC_INTEN_BGTIEN_Pos (6) /*!< SC_T::INTEN: BGTIEN Position */ +#define SC_INTEN_BGTIEN_Msk (0x1ul << SC_INTEN_BGTIEN_Pos) /*!< SC_T::INTEN: BGTIEN Mask */ + +#define SC_INTEN_CDIEN_Pos (7) /*!< SC_T::INTEN: CDIEN Position */ +#define SC_INTEN_CDIEN_Msk (0x1ul << SC_INTEN_CDIEN_Pos) /*!< SC_T::INTEN: CDIEN Mask */ + +#define SC_INTEN_INITIEN_Pos (8) /*!< SC_T::INTEN: INITIEN Position */ +#define SC_INTEN_INITIEN_Msk (0x1ul << SC_INTEN_INITIEN_Pos) /*!< SC_T::INTEN: INITIEN Mask */ + +#define SC_INTEN_RXTOIEN_Pos (9) /*!< SC_T::INTEN: RXTOIEN Position */ +#define SC_INTEN_RXTOIEN_Msk (0x1ul << SC_INTEN_RXTOIEN_Pos) /*!< SC_T::INTEN: RXTOIEN Mask */ + +#define SC_INTEN_ACERRIEN_Pos (10) /*!< SC_T::INTEN: ACERRIEN Position */ +#define SC_INTEN_ACERRIEN_Msk (0x1ul << SC_INTEN_ACERRIEN_Pos) /*!< SC_T::INTEN: ACERRIEN Mask */ + +#define SC_INTSTS_RDAIF_Pos (0) /*!< SC_T::INTSTS: RDAIF Position */ +#define SC_INTSTS_RDAIF_Msk (0x1ul << SC_INTSTS_RDAIF_Pos) /*!< SC_T::INTSTS: RDAIF Mask */ + +#define SC_INTSTS_TBEIF_Pos (1) /*!< SC_T::INTSTS: TBEIF Position */ +#define SC_INTSTS_TBEIF_Msk (0x1ul << SC_INTSTS_TBEIF_Pos) /*!< SC_T::INTSTS: TBEIF Mask */ + +#define SC_INTSTS_TERRIF_Pos (2) /*!< SC_T::INTSTS: TERRIF Position */ +#define SC_INTSTS_TERRIF_Msk (0x1ul << SC_INTSTS_TERRIF_Pos) /*!< SC_T::INTSTS: TERRIF Mask */ + +#define SC_INTSTS_TMR0IF_Pos (3) /*!< SC_T::INTSTS: TMR0IF Position */ +#define SC_INTSTS_TMR0IF_Msk (0x1ul << SC_INTSTS_TMR0IF_Pos) /*!< SC_T::INTSTS: TMR0IF Mask */ + +#define SC_INTSTS_TMR1IF_Pos (4) /*!< SC_T::INTSTS: TMR1IF Position */ +#define SC_INTSTS_TMR1IF_Msk (0x1ul << SC_INTSTS_TMR1IF_Pos) /*!< SC_T::INTSTS: TMR1IF Mask */ + +#define SC_INTSTS_TMR2IF_Pos (5) /*!< SC_T::INTSTS: TMR2IF Position */ +#define SC_INTSTS_TMR2IF_Msk (0x1ul << SC_INTSTS_TMR2IF_Pos) /*!< SC_T::INTSTS: TMR2IF Mask */ + +#define SC_INTSTS_BGTIF_Pos (6) /*!< SC_T::INTSTS: BGTIF Position */ +#define SC_INTSTS_BGTIF_Msk (0x1ul << SC_INTSTS_BGTIF_Pos) /*!< SC_T::INTSTS: BGTIF Mask */ + +#define SC_INTSTS_CDIF_Pos (7) /*!< SC_T::INTSTS: CDIF Position */ +#define SC_INTSTS_CDIF_Msk (0x1ul << SC_INTSTS_CDIF_Pos) /*!< SC_T::INTSTS: CDIF Mask */ + +#define SC_INTSTS_INITIF_Pos (8) /*!< SC_T::INTSTS: INITIF Position */ +#define SC_INTSTS_INITIF_Msk (0x1ul << SC_INTSTS_INITIF_Pos) /*!< SC_T::INTSTS: INITIF Mask */ + +#define SC_INTSTS_RXTOIF_Pos (9) /*!< SC_T::INTSTS: RXTOIF Position */ +#define SC_INTSTS_RXTOIF_Msk (0x1ul << SC_INTSTS_RXTOIF_Pos) /*!< SC_T::INTSTS: RXTOIF Mask */ + +#define SC_INTSTS_ACERRIF_Pos (10) /*!< SC_T::INTSTS: ACERRIF Position */ +#define SC_INTSTS_ACERRIF_Msk (0x1ul << SC_INTSTS_ACERRIF_Pos) /*!< SC_T::INTSTS: ACERRIF Mask */ + +#define SC_STATUS_RXOV_Pos (0) /*!< SC_T::STATUS: RXOV Position */ +#define SC_STATUS_RXOV_Msk (0x1ul << SC_STATUS_RXOV_Pos) /*!< SC_T::STATUS: RXOV Mask */ + +#define SC_STATUS_RXEMPTY_Pos (1) /*!< SC_T::STATUS: RXEMPTY Position */ +#define SC_STATUS_RXEMPTY_Msk (0x1ul << SC_STATUS_RXEMPTY_Pos) /*!< SC_T::STATUS: RXEMPTY Mask */ + +#define SC_STATUS_RXFULL_Pos (2) /*!< SC_T::STATUS: RXFULL Position */ +#define SC_STATUS_RXFULL_Msk (0x1ul << SC_STATUS_RXFULL_Pos) /*!< SC_T::STATUS: RXFULL Mask */ + +#define SC_STATUS_PEF_Pos (4) /*!< SC_T::STATUS: PEF Position */ +#define SC_STATUS_PEF_Msk (0x1ul << SC_STATUS_PEF_Pos) /*!< SC_T::STATUS: PEF Mask */ + +#define SC_STATUS_FEF_Pos (5) /*!< SC_T::STATUS: FEF Position */ +#define SC_STATUS_FEF_Msk (0x1ul << SC_STATUS_FEF_Pos) /*!< SC_T::STATUS: FEF Mask */ + +#define SC_STATUS_BEF_Pos (6) /*!< SC_T::STATUS: BEF Position */ +#define SC_STATUS_BEF_Msk (0x1ul << SC_STATUS_BEF_Pos) /*!< SC_T::STATUS: BEF Mask */ + +#define SC_STATUS_TXOV_Pos (8) /*!< SC_T::STATUS: TXOV Position */ +#define SC_STATUS_TXOV_Msk (0x1ul << SC_STATUS_TXOV_Pos) /*!< SC_T::STATUS: TXOV Mask */ + +#define SC_STATUS_TXEMPTY_Pos (9) /*!< SC_T::STATUS: TXEMPTY Position */ +#define SC_STATUS_TXEMPTY_Msk (0x1ul << SC_STATUS_TXEMPTY_Pos) /*!< SC_T::STATUS: TXEMPTY Mask */ + +#define SC_STATUS_TXFULL_Pos (10) /*!< SC_T::STATUS: TXFULL Position */ +#define SC_STATUS_TXFULL_Msk (0x1ul << SC_STATUS_TXFULL_Pos) /*!< SC_T::STATUS: TXFULL Mask */ + +#define SC_STATUS_CREMOVE_Pos (11) /*!< SC_T::STATUS: CREMOVE Position */ +#define SC_STATUS_CREMOVE_Msk (0x1ul << SC_STATUS_CREMOVE_Pos) /*!< SC_T::STATUS: CREMOVE Mask */ + +#define SC_STATUS_CINSERT_Pos (12) /*!< SC_T::STATUS: CINSERT Position */ +#define SC_STATUS_CINSERT_Msk (0x1ul << SC_STATUS_CINSERT_Pos) /*!< SC_T::STATUS: CINSERT Mask */ + +#define SC_STATUS_CDPINSTS_Pos (13) /*!< SC_T::STATUS: CDPINSTS Position */ +#define SC_STATUS_CDPINSTS_Msk (0x1ul << SC_STATUS_CDPINSTS_Pos) /*!< SC_T::STATUS: CDPINSTS Mask */ + +#define SC_STATUS_RXPOINT_Pos (16) /*!< SC_T::STATUS: RXPOINT Position */ +#define SC_STATUS_RXPOINT_Msk (0x7ul << SC_STATUS_RXPOINT_Pos) /*!< SC_T::STATUS: RXPOINT Mask */ + +#define SC_STATUS_RXRERR_Pos (21) /*!< SC_T::STATUS: RXRERR Position */ +#define SC_STATUS_RXRERR_Msk (0x1ul << SC_STATUS_RXRERR_Pos) /*!< SC_T::STATUS: RXRERR Mask */ + +#define SC_STATUS_RXOVERR_Pos (22) /*!< SC_T::STATUS: RXOVERR Position */ +#define SC_STATUS_RXOVERR_Msk (0x1ul << SC_STATUS_RXOVERR_Pos) /*!< SC_T::STATUS: RXOVERR Mask */ + +#define SC_STATUS_RXACT_Pos (23) /*!< SC_T::STATUS: RXACT Position */ +#define SC_STATUS_RXACT_Msk (0x1ul << SC_STATUS_RXACT_Pos) /*!< SC_T::STATUS: RXACT Mask */ + +#define SC_STATUS_TXPOINT_Pos (24) /*!< SC_T::STATUS: TXPOINT Position */ +#define SC_STATUS_TXPOINT_Msk (0x7ul << SC_STATUS_TXPOINT_Pos) /*!< SC_T::STATUS: TXPOINT Mask */ + +#define SC_STATUS_TXRERR_Pos (29) /*!< SC_T::STATUS: TXRERR Position */ +#define SC_STATUS_TXRERR_Msk (0x1ul << SC_STATUS_TXRERR_Pos) /*!< SC_T::STATUS: TXRERR Mask */ + +#define SC_STATUS_TXOVERR_Pos (30) /*!< SC_T::STATUS: TXOVERR Position */ +#define SC_STATUS_TXOVERR_Msk (0x1ul << SC_STATUS_TXOVERR_Pos) /*!< SC_T::STATUS: TXOVERR Mask */ + +#define SC_STATUS_TXACT_Pos (31) /*!< SC_T::STATUS: TXACT Position */ +#define SC_STATUS_TXACT_Msk (0x1ul << SC_STATUS_TXACT_Pos) /*!< SC_T::STATUS: TXACT Mask */ + +#define SC_PINCTL_PWREN_Pos (0) /*!< SC_T::PINCTL: PWREN Position */ +#define SC_PINCTL_PWREN_Msk (0x1ul << SC_PINCTL_PWREN_Pos) /*!< SC_T::PINCTL: PWREN Mask */ + +#define SC_PINCTL_RSTEN_Pos (1) /*!< SC_T::PINCTL: RSTEN Position */ +#define SC_PINCTL_RSTEN_Msk (0x1ul << SC_PINCTL_RSTEN_Pos) /*!< SC_T::PINCTL: RSTEN Mask */ + +#define SC_PINCTL_CLKKEEP_Pos (6) /*!< SC_T::PINCTL: CLKKEEP Position */ +#define SC_PINCTL_CLKKEEP_Msk (0x1ul << SC_PINCTL_CLKKEEP_Pos) /*!< SC_T::PINCTL: CLKKEEP Mask */ + +#define SC_PINCTL_SCDATA_Pos (9) /*!< SC_T::PINCTL: SCDATA Position */ +#define SC_PINCTL_SCDATA_Msk (0x1ul << SC_PINCTL_SCDATA_Pos) /*!< SC_T::PINCTL: SCDATA Mask */ + +#define SC_PINCTL_PWRINV_Pos (11) /*!< SC_T::PINCTL: PWRINV Position */ +#define SC_PINCTL_PWRINV_Msk (0x1ul << SC_PINCTL_PWRINV_Pos) /*!< SC_T::PINCTL: PWRINV Mask */ + +#define SC_PINCTL_DATASTS_Pos (16) /*!< SC_T::PINCTL: DATASTS Position */ +#define SC_PINCTL_DATASTS_Msk (0x1ul << SC_PINCTL_DATASTS_Pos) /*!< SC_T::PINCTL: DATASTS Mask */ + +#define SC_PINCTL_PWRSTS_Pos (17) /*!< SC_T::PINCTL: PWRSTS Position */ +#define SC_PINCTL_PWRSTS_Msk (0x1ul << SC_PINCTL_PWRSTS_Pos) /*!< SC_T::PINCTL: PWRSTS Mask */ + +#define SC_PINCTL_RSTSTS_Pos (18) /*!< SC_T::PINCTL: RSTSTS Position */ +#define SC_PINCTL_RSTSTS_Msk (0x1ul << SC_PINCTL_RSTSTS_Pos) /*!< SC_T::PINCTL: RSTSTS Mask */ + +#define SC_PINCTL_SYNC_Pos (30) /*!< SC_T::PINCTL: SYNC Position */ +#define SC_PINCTL_SYNC_Msk (0x1ul << SC_PINCTL_SYNC_Pos) /*!< SC_T::PINCTL: SYNC Mask */ + +#define SC_TMRCTL0_CNT_Pos (0) /*!< SC_T::TMRCTL0: CNT Position */ +#define SC_TMRCTL0_CNT_Msk (0xfffffful << SC_TMRCTL0_CNT_Pos) /*!< SC_T::TMRCTL0: CNT Mask */ + +#define SC_TMRCTL0_OPMODE_Pos (24) /*!< SC_T::TMRCTL0: OPMODE Position */ +#define SC_TMRCTL0_OPMODE_Msk (0xful << SC_TMRCTL0_OPMODE_Pos) /*!< SC_T::TMRCTL0: OPMODE Mask */ + +#define SC_TMRCTL0_SYNC_Pos (31) /*!< SC_T::TMRCTL0: SYNC Position */ +#define SC_TMRCTL0_SYNC_Msk (0x1ul << SC_TMRCTL0_SYNC_Pos) /*!< SC_T::TMRCTL0: SYNC Mask */ + +#define SC_TMRCTL1_CNT_Pos (0) /*!< SC_T::TMRCTL1: CNT Position */ +#define SC_TMRCTL1_CNT_Msk (0xfful << SC_TMRCTL1_CNT_Pos) /*!< SC_T::TMRCTL1: CNT Mask */ + +#define SC_TMRCTL1_OPMODE_Pos (24) /*!< SC_T::TMRCTL1: OPMODE Position */ +#define SC_TMRCTL1_OPMODE_Msk (0xful << SC_TMRCTL1_OPMODE_Pos) /*!< SC_T::TMRCTL1: OPMODE Mask */ + +#define SC_TMRCTL1_SYNC_Pos (31) /*!< SC_T::TMRCTL1: SYNC Position */ +#define SC_TMRCTL1_SYNC_Msk (0x1ul << SC_TMRCTL1_SYNC_Pos) /*!< SC_T::TMRCTL1: SYNC Mask */ + +#define SC_TMRCTL2_CNT_Pos (0) /*!< SC_T::TMRCTL2: CNT Position */ +#define SC_TMRCTL2_CNT_Msk (0xfful << SC_TMRCTL2_CNT_Pos) /*!< SC_T::TMRCTL2: CNT Mask */ + +#define SC_TMRCTL2_OPMODE_Pos (24) /*!< SC_T::TMRCTL2: OPMODE Position */ +#define SC_TMRCTL2_OPMODE_Msk (0xful << SC_TMRCTL2_OPMODE_Pos) /*!< SC_T::TMRCTL2: OPMODE Mask */ + +#define SC_TMRCTL2_SYNC_Pos (31) /*!< SC_T::TMRCTL2: SYNC Position */ +#define SC_TMRCTL2_SYNC_Msk (0x1ul << SC_TMRCTL2_SYNC_Pos) /*!< SC_T::TMRCTL2: SYNC Mask */ + +#define SC_UARTCTL_UARTEN_Pos (0) /*!< SC_T::UARTCTL: UARTEN Position */ +#define SC_UARTCTL_UARTEN_Msk (0x1ul << SC_UARTCTL_UARTEN_Pos) /*!< SC_T::UARTCTL: UARTEN Mask */ + +#define SC_UARTCTL_WLS_Pos (4) /*!< SC_T::UARTCTL: WLS Position */ +#define SC_UARTCTL_WLS_Msk (0x3ul << SC_UARTCTL_WLS_Pos) /*!< SC_T::UARTCTL: WLS Mask */ + +#define SC_UARTCTL_PBOFF_Pos (6) /*!< SC_T::UARTCTL: PBOFF Position */ +#define SC_UARTCTL_PBOFF_Msk (0x1ul << SC_UARTCTL_PBOFF_Pos) /*!< SC_T::UARTCTL: PBOFF Mask */ + +#define SC_UARTCTL_OPE_Pos (7) /*!< SC_T::UARTCTL: OPE Position */ +#define SC_UARTCTL_OPE_Msk (0x1ul << SC_UARTCTL_OPE_Pos) /*!< SC_T::UARTCTL: OPE Mask */ + +#define SC_ACTCTL_T1EXT_Pos (0) /*!< SC_T::ACTCTL: T1EXT Position */ +#define SC_ACTCTL_T1EXT_Msk (0x1ful << SC_ACTCTL_T1EXT_Pos) /*!< SC_T::ACTCTL: T1EXT Mask */ + +/**@}*/ /* SC_CONST */ +/**@}*/ /* end of SC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __SC_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/sdh_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/sdh_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..56f42e82005b4a72d50f2e5a2b33f716e497e5c2 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/sdh_reg.h @@ -0,0 +1,541 @@ +/**************************************************************************//** + * @file sdh_reg.h + * @version V1.00 + * @brief SDH register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SDH_REG_H__ +#define __SDH_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup SDH SD Card Host Interface(SDH) + Memory Mapped Structure for SDH Controller +@{ */ + +typedef struct +{ + + /** + * @var SDH_T::FB + * Offset: 0x00~0x7C Shared Buffer (FIFO) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |BUFFER |Shared Buffer + * | | |Buffer for DMA transfer + * @var SDH_T::DMACTL + * Offset: 0x400 DMA Control and Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DMAEN |DMA Engine Enable Bit + * | | |0 = DMA Disabled. + * | | |1 = DMA Enabled. + * | | |If this bit is cleared, DMA will ignore all requests from SD host and force bus master into IDLE state. + * | | |Note: If target abort is occurred, DMAEN will be cleared. + * |[1] |DMARST |Software Engine Reset + * | | |0 = No effect. + * | | |1 = Reset internal state machine and pointers + * | | |The contents of control register will not be cleared + * | | |This bit will auto be cleared after few clock cycles. + * | | |Note: The software reset DMA related registers. + * |[3] |SGEN |Scatter-gather Function Enable Bit + * | | |0 = Scatter-gather function Disabled (DMA will treat the starting address in DMASAR as starting pointer of a single block memory). + * | | |1 = Scatter-gather function Enabled (DMA will treat the starting address in DMASAR as a starting address of Physical Address Descriptor (PAD) table + * | | |The format of these Pads' will be described later). + * |[9] |DMABUSY |DMA Transfer Is in Progress + * | | |This bit indicates if SD Host is granted and doing DMA transfer or not. + * | | |0 = DMA transfer is not in progress. + * | | |1 = DMA transfer is in progress. + * @var SDH_T::DMASA + * Offset: 0x408 DMA Transfer Starting Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ORDER |Determined to the PAD Table Fetching Is in Order or Out of Order + * | | |0 = PAD table is fetched in order. + * | | |1 = PAD table is fetched out of order. + * | | |Note: the bit0 is valid in scatter-gather mode when SGEN = 1. + * |[31:1] |DMASA |DMA Transfer Starting Address + * | | |This field pads 0 as least significant bit indicates a 32-bit starting address of system memory (SRAM) for DMA to retrieve or fill in data. + * | | |If DMA is not in normal mode, this field will be interpreted as a starting address of Physical Address Descriptor (PAD) table. + * | | |Note: Starting address of the SRAM must be word aligned, for example, 0x0000_0000, 0x0000_0004. + * @var SDH_T::DMABCNT + * Offset: 0x40C DMA Transfer Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[25:0] |BCNT |DMA Transfer Byte Count (Read Only) + * | | |This field indicates the remained byte count of DMA transfer + * | | |The value of this field is valid only when DMA is busy; otherwise, it is 0. + * @var SDH_T::DMAINTEN + * Offset: 0x410 DMA Interrupt Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ABORTIEN |DMA Read/Write Target Abort Interrupt Enable Bit + * | | |0 = Target abort interrupt generation Disabled during DMA transfer. + * | | |1 = Target abort interrupt generation Enabled during DMA transfer. + * |[1] |WEOTIEN |Wrong EOT Encountered Interrupt Enable Bit + * | | |0 = Interrupt generation Disabled when wrong EOT is encountered. + * | | |1 = Interrupt generation Enabled when wrong EOT is encountered. + * @var SDH_T::DMAINTSTS + * Offset: 0x414 DMA Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ABORTIF |DMA Read/Write Target Abort Interrupt Flag + * | | |0 = No bus ERROR response received. + * | | |1 = Bus ERROR response received. + * | | |Note1: This bit is read only, but can be cleared by writing '1' to it. + * | | |Note2: When DMA's bus master received ERROR response, it means that target abort is happened + * | | |DMA will stop transfer and respond this event and then go to IDLE state + * | | |When target abort occurred or WEOTIF is set, software must reset DMA and SD host, and then transfer those data again. + * |[1] |WEOTIF |Wrong EOT Encountered Interrupt Flag + * | | |When DMA Scatter-Gather function is enabled, and EOT of the descriptor is encountered before DMA transfer finished (that means the total sector count of all PAD is less than the sector count of SD host), this bit will be set. + * | | |0 = No EOT encountered before DMA transfer finished. + * | | |1 = EOT encountered before DMA transfer finished. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * @var SDH_T::GCTL + * Offset: 0x800 Global Control and Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GCTLRST |Software Engine Reset + * | | |0 = No effect. + * | | |1 = Reset SD host + * | | |The contents of control register will not be cleared + * | | |This bit will auto cleared after reset complete. + * |[1] |SDEN |Secure Digital Functionality Enable Bit + * | | |0 = SD functionality disabled. + * | | |1 = SD functionality enabled. + * @var SDH_T::GINTEN + * Offset: 0x804 Global Interrupt Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DTAIEN |DMA READ/WRITE Target Abort Interrupt Enable Bit + * | | |0 = DMA READ/WRITE target abort interrupt generation disabled. + * | | |1 = DMA READ/WRITE target abort interrupt generation enabled. + * @var SDH_T::GINTSTS + * Offset: 0x808 Global Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DTAIF |DMA READ/WRITE Target Abort Interrupt Flag (Read Only) + * | | |This bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation + * | | |When Target Abort is occurred, please reset all engine. + * | | |0 = No bus ERROR response received. + * | | |1 = Bus ERROR response received. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * @var SDH_T::CTL + * Offset: 0x820 SD Control and Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |COEN |Command Output Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will output a command to SD card. + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[1] |RIEN |Response Input Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will wait to receive a response from SD card. + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[2] |DIEN |Data Input Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will wait to receive block data and the CRC16 value from SD card. + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[3] |DOEN |Data Output Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will transfer block data and the CRC16 value to SD card. + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[4] |R2EN |Response R2 Input Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will wait to receive a response R2 from SD card and store the response data into DMC's flash buffer (exclude CRC7). + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[5] |CLK74OEN |Initial 74 Clock Cycles Output Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will output 74 clock cycles to SD card. + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[6] |CLK8OEN |Generating 8 Clock Cycles Output Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will output 8 clock cycles. + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[7] |CLKKEEP |SD Clock Enable Control + * | | |0 = SD host decided when to output clock and when to disable clock output automatically. + * | | |1 = SD clock always keeps free running. + * |[13:8] |CMDCODE |SD Command Code + * | | |This register contains the SD command code (0x00 - 0x3F). + * |[14] |CTLRST |Software Engine Reset + * | | |0 = No effect. + * | | |1 = Reset the internal state machine and counters + * | | |The contents of control register will not be cleared (but RIEN, DIEN, DOEN and R2_EN will be cleared) + * | | |This bit will be auto cleared after few clock cycles. + * |[15] |DBW |SD Data Bus Width (for 1-bit / 4-bit Selection) + * | | |0 = Data bus width is 1-bit. + * | | |1 = Data bus width is 4-bit. + * |[23:16] |BLKCNT |Block Counts to Be Transferred or Received + * | | |This field contains the block counts for data-in and data-out transfer + * | | |For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, software can use this function to accelerate data transfer and improve performance + * | | |Don't fill 0x0 to this field. + * | | |Note: For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, the actual total length is BLKCNT * (BLKLEN +1). + * |[27:24] |SDNWR |NWR Parameter for Block Write Operation + * | | |This value indicates the NWR parameter for data block write operation in SD clock counts + * | | |The actual clock cycle will be SDNWR+1. + * @var SDH_T::CMDARG + * Offset: 0x824 SD Command Argument Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ARGUMENT |SD Command Argument + * | | |This register contains a 32-bit value specifies the argument of SD command from host controller to SD card + * | | |Before trigger COEN (SDH_CTL [0]), software should fill argument in this field. + * @var SDH_T::INTEN + * Offset: 0x828 SD Interrupt Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BLKDIEN |Block Transfer Done Interrupt Enable Bit + * | | |0 = BLKDIF (SDH_INTEN[0]) trigger interrupt Disable. + * | | |1 = BLKDIF (SDH_INTEN[0]) trigger interrupt Enabled. + * |[1] |CRCIEN |CRC7, CRC16 and CRC Status Error Interrupt Enable Bit + * | | |0 = CRCIF (SDH_INTEN[1]) trigger interrupt Disable. + * | | |1 = CRCIF (SDH_INTEN[1]) trigger interrupt Enabled. + * |[8] |CDIEN |SD Card Detection Interrupt Enable Bit + * | | |Enable/Disable interrupts generation of SD controller when card is inserted or removed. + * | | |0 = CDIF (SDH_INTEN[8]) trigger interrupt Disable. + * | | |1 = CDIF (SDH_INTEN[8]) trigger interrupt Enabled. + * |[12] |RTOIEN |Response Time-out Interrupt Enable Bit + * | | |Enable/Disable interrupts generation of SD controller when receiving response or R2 time-out + * | | |Time-out value is specified at TOUT register. + * | | |0 = RTOIF (SDH_INTEN[12]) trigger interrupt Disabled. + * | | |1 = RTOIF (SDH_INTEN[12]) trigger interrupt Enabled. + * |[13] |DITOIEN |Data Input Time-out Interrupt Enable Bit + * | | |Enable/Disable interrupts generation of SD controller when data input time-out + * | | |Time-out value is specified at TOUT register. + * | | |0 = DITOIF (SDH_INTEN[13]) trigger interrupt Disabled. + * | | |1 = DITOIF (SDH_INTEN[13]) trigger interrupt Enabled. + * |[14] |WKIEN |Wake-up Signal Generating Enable Bit + * | | |Enable/Disable wake-up signal generating of SD host when current using SD card issues an interrupt (wake-up) via DAT [1] to host. + * | | |0 = SD Card interrupt to wake-up chip Disabled. + * | | |1 = SD Card interrupt to wake-up chip Enabled. + * |[30] |CDSRC |SD Card Detect Source Selection + * | | |0 = From SD card's DAT3 pin. + * | | |Host need clock to got data on pin DAT3 + * | | |Please make sure CLKKEEP (SDH_CTL[7]) is 1 in order to generate free running clock for DAT3 pin. + * | | |1 = From GPIO pin. + * @var SDH_T::INTSTS + * Offset: 0x82C SD Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BLKDIF |Block Transfer Done Interrupt Flag (Read Only) + * | | |This bit indicates that SD host has finished all data-in or data-out block transfer + * | | |If there is a CRC16 error or incorrect CRC status during multiple block data transfer, the transfer will be broken and this bit will also be set. + * | | |0 = Not finished yet. + * | | |1 = Done. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * |[1] |CRCIF |CRC7, CRC16 and CRC Status Error Interrupt Flag (Read Only) + * | | |This bit indicates that SD host has occurred CRC error during response in, data-in or data-out (CRC status error) transfer + * | | |When CRC error is occurred, software should reset SD engine + * | | |Some response (ex + * | | |R3) doesn't have CRC7 information with it; SD host will still calculate CRC7, get CRC error and set this flag + * | | |In this condition, software should ignore CRC error and clears this bit manually. + * | | |0 = No CRC error is occurred. + * | | |1 = CRC error is occurred. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * |[2] |CRC7 |CRC7 Check Status (Read Only) + * | | |SD host will check CRC7 correctness during each response in + * | | |If that response does not contain CRC7 information (ex + * | | |R3), then software should turn off CRCIEN (SDH_INTEN[1]) and ignore this bit. + * | | |0 = Fault. + * | | |1 = OK. + * |[3] |CRC16 |CRC16 Check Status of Data-in Transfer (Read Only) + * | | |SD host will check CRC16 correctness after data-in transfer. + * | | |0 = Fault. + * | | |1 = OK. + * |[6:4] |CRCSTS |CRC Status Value of Data-out Transfer (Read Only) + * | | |SD host will record CRC status of data-out transfer + * | | |Software could use this value to identify what type of error is during data-out transfer. + * | | |010 = Positive CRC status. + * | | |101 = Negative CRC status. + * | | |111 = SD card programming error occurs. + * |[7] |DAT0STS |DAT0 Pin Status of Current Selected SD Port (Read Only) + * | | |This bit is the DAT0 pin status of current selected SD port. + * |[8] |CDIF |SD Card Detection Interrupt Flag (Read Only) + * | | |This bit indicates that SD card is inserted or removed + * | | |Only when CDIEN (SDH_INTEN[8]) is set to 1, this bit is active. + * | | |0 = No card is inserted or removed. + * | | |1 = There is a card inserted in or removed from SD. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * |[12] |RTOIF |Response Time-out Interrupt Flag (Read Only) + * | | |This bit indicates that SD host counts to time-out value when receiving response or R2 (waiting start bit). + * | | |0 = Not time-out. + * | | |1 = Response time-out. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * |[13] |DITOIF |Data Input Time-out Interrupt Flag (Read Only) + * | | |This bit indicates that SD host counts to time-out value when receiving data (waiting start bit). + * | | |0 = Not time-out. + * | | |1 = Data input time-out. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * |[16] |CDSTS |Card Detect Status of SD (Read Only) + * | | |This bit indicates the card detect pin status of SD, and is used for card detection + * | | |When there is a card inserted in or removed from SD, software should check this bit to confirm if there is really a card insertion or removal. + * | | |If CDSRC (SDH_INTEN[30]) = 0, to select DAT3 for card detection:. + * | | |0 = Card removed. + * | | |1 = Card inserted. + * | | |If CDSRC (SDH_INTEN[30]) = 1, to select GPIO for card detection:. + * | | |0 = Card inserted. + * | | |1 = Card removed. + * |[18] |DAT1STS |DAT1 Pin Status of SD Port (Read Only) + * | | |This bit indicates the DAT1 pin status of SD port. + * @var SDH_T::RESP0 + * Offset: 0x830 SD Receiving Response Token Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RESPTK0 |SD Receiving Response Token 0 + * | | |SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set + * | | |This field contains response bit 47-16 of the response token. + * @var SDH_T::RESP1 + * Offset: 0x834 SD Receiving Response Token Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |RESPTK1 |SD Receiving Response Token 1 + * | | |SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set + * | | |This register contains the bit 15-8 of the response token. + * @var SDH_T::BLEN + * Offset: 0x838 SD Block Length Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |BLKLEN |SD BLOCK LENGTH in Byte Unit + * | | |An 11-bit value specifies the SD transfer byte count of a block + * | | |The actual byte count is equal to BLKLEN+1. + * | | |Note: The default SD block length is 512 bytes + * @var SDH_T::TOUT + * Offset: 0x83C SD Response/Data-in Time-out Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |TOUT |SD Response/Data-in Time-out Value + * | | |A 24-bit value specifies the time-out counts of response and data input + * | | |SD host controller will wait start bit of response or data-in until this value reached + * | | |The time period depends on SD engine clock frequency + * | | |Do not write a small number into this field, or you may never get response or data due to time-out. + * | | |Note: Filling 0x0 into this field will disable hardware time-out function. + */ + + __IO uint32_t FB[32]; /*!< Shared Buffer (FIFO) */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[224]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t DMACTL; /*!< [0x0400] DMA Control and Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t DMASA; /*!< [0x0408] DMA Transfer Starting Address Register */ + __I uint32_t DMABCNT; /*!< [0x040c] DMA Transfer Byte Count Register */ + __IO uint32_t DMAINTEN; /*!< [0x0410] DMA Interrupt Enable Control Register */ + __IO uint32_t DMAINTSTS; /*!< [0x0414] DMA Interrupt Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[250]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t GCTL; /*!< [0x0800] Global Control and Status Register */ + __IO uint32_t GINTEN; /*!< [0x0804] Global Interrupt Control Register */ + __I uint32_t GINTSTS; /*!< [0x0808] Global Interrupt Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[5]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CTL; /*!< [0x0820] SD Control and Status Register */ + __IO uint32_t CMDARG; /*!< [0x0824] SD Command Argument Register */ + __IO uint32_t INTEN; /*!< [0x0828] SD Interrupt Control Register */ + __IO uint32_t INTSTS; /*!< [0x082c] SD Interrupt Status Register */ + __I uint32_t RESP0; /*!< [0x0830] SD Receiving Response Token Register 0 */ + __I uint32_t RESP1; /*!< [0x0834] SD Receiving Response Token Register 1 */ + __IO uint32_t BLEN; /*!< [0x0838] SD Block Length Register */ + __IO uint32_t TOUT; /*!< [0x083c] SD Response/Data-in Time-out Register */ + +} SDH_T; + + +/** + @addtogroup SDH_CONST SDH Bit Field Definition + Constant Definitions for SDH Controller +@{ */ + +#define SDH_DMACTL_DMAEN_Pos (0) /*!< SDH_T::DMACTL: DMAEN Position */ +#define SDH_DMACTL_DMAEN_Msk (0x1ul << SDH_DMACTL_DMAEN_Pos) /*!< SDH_T::DMACTL: DMAEN Mask */ + +#define SDH_DMACTL_DMARST_Pos (1) /*!< SDH_T::DMACTL: DMARST Position */ +#define SDH_DMACTL_DMARST_Msk (0x1ul << SDH_DMACTL_DMARST_Pos) /*!< SDH_T::DMACTL: DMARST Mask */ + +#define SDH_DMACTL_SGEN_Pos (3) /*!< SDH_T::DMACTL: SGEN Position */ +#define SDH_DMACTL_SGEN_Msk (0x1ul << SDH_DMACTL_SGEN_Pos) /*!< SDH_T::DMACTL: SGEN Mask */ + +#define SDH_DMACTL_DMABUSY_Pos (9) /*!< SDH_T::DMACTL: DMABUSY Position */ +#define SDH_DMACTL_DMABUSY_Msk (0x1ul << SDH_DMACTL_DMABUSY_Pos) /*!< SDH_T::DMACTL: DMABUSY Mask */ + +#define SDH_DMASA_ORDER_Pos (0) /*!< SDH_T::DMASA: ORDER Position */ +#define SDH_DMASA_ORDER_Msk (0x1ul << SDH_DMASA_ORDER_Pos) /*!< SDH_T::DMASA: ORDER Mask */ + +#define SDH_DMASA_DMASA_Pos (1) /*!< SDH_T::DMASA: DMASA Position */ +#define SDH_DMASA_DMASA_Msk (0x7ffffffful << SDH_DMASA_DMASA_Pos) /*!< SDH_T::DMASA: DMASA Mask */ + +#define SDH_DMABCNT_BCNT_Pos (0) /*!< SDH_T::DMABCNT: BCNT Position */ +#define SDH_DMABCNT_BCNT_Msk (0x3fffffful << SDH_DMABCNT_BCNT_Pos) /*!< SDH_T::DMABCNT: BCNT Mask */ + +#define SDH_DMAINTEN_ABORTIEN_Pos (0) /*!< SDH_T::DMAINTEN: ABORTIEN Position */ +#define SDH_DMAINTEN_ABORTIEN_Msk (0x1ul << SDH_DMAINTEN_ABORTIEN_Pos) /*!< SDH_T::DMAINTEN: ABORTIEN Mask */ + +#define SDH_DMAINTEN_WEOTIEN_Pos (1) /*!< SDH_T::DMAINTEN: WEOTIEN Position */ +#define SDH_DMAINTEN_WEOTIEN_Msk (0x1ul << SDH_DMAINTEN_WEOTIEN_Pos) /*!< SDH_T::DMAINTEN: WEOTIEN Mask */ + +#define SDH_DMAINTSTS_ABORTIF_Pos (0) /*!< SDH_T::DMAINTSTS: ABORTIF Position */ +#define SDH_DMAINTSTS_ABORTIF_Msk (0x1ul << SDH_DMAINTSTS_ABORTIF_Pos) /*!< SDH_T::DMAINTSTS: ABORTIF Mask */ + +#define SDH_DMAINTSTS_WEOTIF_Pos (1) /*!< SDH_T::DMAINTSTS: WEOTIF Position */ +#define SDH_DMAINTSTS_WEOTIF_Msk (0x1ul << SDH_DMAINTSTS_WEOTIF_Pos) /*!< SDH_T::DMAINTSTS: WEOTIF Mask */ + +#define SDH_GCTL_GCTLRST_Pos (0) /*!< SDH_T::GCTL: GCTLRST Position */ +#define SDH_GCTL_GCTLRST_Msk (0x1ul << SDH_GCTL_GCTLRST_Pos) /*!< SDH_T::GCTL: GCTLRST Mask */ + +#define SDH_GCTL_SDEN_Pos (1) /*!< SDH_T::GCTL: SDEN Position */ +#define SDH_GCTL_SDEN_Msk (0x1ul << SDH_GCTL_SDEN_Pos) /*!< SDH_T::GCTL: SDEN Mask */ + +#define SDH_GINTEN_DTAIEN_Pos (0) /*!< SDH_T::GINTEN: DTAIEN Position */ +#define SDH_GINTEN_DTAIEN_Msk (0x1ul << SDH_GINTEN_DTAIEN_Pos) /*!< SDH_T::GINTEN: DTAIEN Mask */ + +#define SDH_GINTSTS_DTAIF_Pos (0) /*!< SDH_T::GINTSTS: DTAIF Position */ +#define SDH_GINTSTS_DTAIF_Msk (0x1ul << SDH_GINTSTS_DTAIF_Pos) /*!< SDH_T::GINTSTS: DTAIF Mask */ + +#define SDH_CTL_COEN_Pos (0) /*!< SDH_T::CTL: COEN Position */ +#define SDH_CTL_COEN_Msk (0x1ul << SDH_CTL_COEN_Pos) /*!< SDH_T::CTL: COEN Mask */ + +#define SDH_CTL_RIEN_Pos (1) /*!< SDH_T::CTL: RIEN Position */ +#define SDH_CTL_RIEN_Msk (0x1ul << SDH_CTL_RIEN_Pos) /*!< SDH_T::CTL: RIEN Mask */ + +#define SDH_CTL_DIEN_Pos (2) /*!< SDH_T::CTL: DIEN Position */ +#define SDH_CTL_DIEN_Msk (0x1ul << SDH_CTL_DIEN_Pos) /*!< SDH_T::CTL: DIEN Mask */ + +#define SDH_CTL_DOEN_Pos (3) /*!< SDH_T::CTL: DOEN Position */ +#define SDH_CTL_DOEN_Msk (0x1ul << SDH_CTL_DOEN_Pos) /*!< SDH_T::CTL: DOEN Mask */ + +#define SDH_CTL_R2EN_Pos (4) /*!< SDH_T::CTL: R2EN Position */ +#define SDH_CTL_R2EN_Msk (0x1ul << SDH_CTL_R2EN_Pos) /*!< SDH_T::CTL: R2EN Mask */ + +#define SDH_CTL_CLK74OEN_Pos (5) /*!< SDH_T::CTL: CLK74OEN Position */ +#define SDH_CTL_CLK74OEN_Msk (0x1ul << SDH_CTL_CLK74OEN_Pos) /*!< SDH_T::CTL: CLK74OEN Mask */ + +#define SDH_CTL_CLK8OEN_Pos (6) /*!< SDH_T::CTL: CLK8OEN Position */ +#define SDH_CTL_CLK8OEN_Msk (0x1ul << SDH_CTL_CLK8OEN_Pos) /*!< SDH_T::CTL: CLK8OEN Mask */ + +#define SDH_CTL_CLKKEEP_Pos (7) /*!< SDH_T::CTL: CLKKEEP Position */ +#define SDH_CTL_CLKKEEP_Msk (0x1ul << SDH_CTL_CLKKEEP_Pos) /*!< SDH_T::CTL: CLKKEEP Mask */ + +#define SDH_CTL_CMDCODE_Pos (8) /*!< SDH_T::CTL: CMDCODE Position */ +#define SDH_CTL_CMDCODE_Msk (0x3ful << SDH_CTL_CMDCODE_Pos) /*!< SDH_T::CTL: CMDCODE Mask */ + +#define SDH_CTL_CTLRST_Pos (14) /*!< SDH_T::CTL: CTLRST Position */ +#define SDH_CTL_CTLRST_Msk (0x1ul << SDH_CTL_CTLRST_Pos) /*!< SDH_T::CTL: CTLRST Mask */ + +#define SDH_CTL_DBW_Pos (15) /*!< SDH_T::CTL: DBW Position */ +#define SDH_CTL_DBW_Msk (0x1ul << SDH_CTL_DBW_Pos) /*!< SDH_T::CTL: DBW Mask */ + +#define SDH_CTL_BLKCNT_Pos (16) /*!< SDH_T::CTL: BLKCNT Position */ +#define SDH_CTL_BLKCNT_Msk (0xfful << SDH_CTL_BLKCNT_Pos) /*!< SDH_T::CTL: BLKCNT Mask */ + +#define SDH_CTL_SDNWR_Pos (24) /*!< SDH_T::CTL: SDNWR Position */ +#define SDH_CTL_SDNWR_Msk (0xful << SDH_CTL_SDNWR_Pos) /*!< SDH_T::CTL: SDNWR Mask */ + +#define SDH_CMDARG_ARGUMENT_Pos (0) /*!< SDH_T::CMDARG: ARGUMENT Position */ +#define SDH_CMDARG_ARGUMENT_Msk (0xfffffffful << SDH_CMDARG_ARGUMENT_Pos) /*!< SDH_T::CMDARG: ARGUMENT Mask */ + +#define SDH_INTEN_BLKDIEN_Pos (0) /*!< SDH_T::INTEN: BLKDIEN Position */ +#define SDH_INTEN_BLKDIEN_Msk (0x1ul << SDH_INTEN_BLKDIEN_Pos) /*!< SDH_T::INTEN: BLKDIEN Mask */ + +#define SDH_INTEN_CRCIEN_Pos (1) /*!< SDH_T::INTEN: CRCIEN Position */ +#define SDH_INTEN_CRCIEN_Msk (0x1ul << SDH_INTEN_CRCIEN_Pos) /*!< SDH_T::INTEN: CRCIEN Mask */ + +#define SDH_INTEN_CDIEN_Pos (8) /*!< SDH_T::INTEN: CDIEN Position */ +#define SDH_INTEN_CDIEN_Msk (0x1ul << SDH_INTEN_CDIEN_Pos) /*!< SDH_T::INTEN: CDIEN Mask */ + +#define SDH_INTEN_RTOIEN_Pos (12) /*!< SDH_T::INTEN: RTOIEN Position */ +#define SDH_INTEN_RTOIEN_Msk (0x1ul << SDH_INTEN_RTOIEN_Pos) /*!< SDH_T::INTEN: RTOIEN Mask */ + +#define SDH_INTEN_DITOIEN_Pos (13) /*!< SDH_T::INTEN: DITOIEN Position */ +#define SDH_INTEN_DITOIEN_Msk (0x1ul << SDH_INTEN_DITOIEN_Pos) /*!< SDH_T::INTEN: DITOIEN Mask */ + +#define SDH_INTEN_WKIEN_Pos (14) /*!< SDH_T::INTEN: WKIEN Position */ +#define SDH_INTEN_WKIEN_Msk (0x1ul << SDH_INTEN_WKIEN_Pos) /*!< SDH_T::INTEN: WKIEN Mask */ + +#define SDH_INTEN_CDSRC_Pos (30) /*!< SDH_T::INTEN: CDSRC Position */ +#define SDH_INTEN_CDSRC_Msk (0x1ul << SDH_INTEN_CDSRC_Pos) /*!< SDH_T::INTEN: CDSRC Mask */ + +#define SDH_INTSTS_BLKDIF_Pos (0) /*!< SDH_T::INTSTS: BLKDIF Position */ +#define SDH_INTSTS_BLKDIF_Msk (0x1ul << SDH_INTSTS_BLKDIF_Pos) /*!< SDH_T::INTSTS: BLKDIF Mask */ + +#define SDH_INTSTS_CRCIF_Pos (1) /*!< SDH_T::INTSTS: CRCIF Position */ +#define SDH_INTSTS_CRCIF_Msk (0x1ul << SDH_INTSTS_CRCIF_Pos) /*!< SDH_T::INTSTS: CRCIF Mask */ + +#define SDH_INTSTS_CRC7_Pos (2) /*!< SDH_T::INTSTS: CRC7 Position */ +#define SDH_INTSTS_CRC7_Msk (0x1ul << SDH_INTSTS_CRC7_Pos) /*!< SDH_T::INTSTS: CRC7 Mask */ + +#define SDH_INTSTS_CRC16_Pos (3) /*!< SDH_T::INTSTS: CRC16 Position */ +#define SDH_INTSTS_CRC16_Msk (0x1ul << SDH_INTSTS_CRC16_Pos) /*!< SDH_T::INTSTS: CRC16 Mask */ + +#define SDH_INTSTS_CRCSTS_Pos (4) /*!< SDH_T::INTSTS: CRCSTS Position */ +#define SDH_INTSTS_CRCSTS_Msk (0x7ul << SDH_INTSTS_CRCSTS_Pos) /*!< SDH_T::INTSTS: CRCSTS Mask */ + +#define SDH_INTSTS_DAT0STS_Pos (7) /*!< SDH_T::INTSTS: DAT0STS Position */ +#define SDH_INTSTS_DAT0STS_Msk (0x1ul << SDH_INTSTS_DAT0STS_Pos) /*!< SDH_T::INTSTS: DAT0STS Mask */ + +#define SDH_INTSTS_CDIF_Pos (8) /*!< SDH_T::INTSTS: CDIF Position */ +#define SDH_INTSTS_CDIF_Msk (0x1ul << SDH_INTSTS_CDIF_Pos) /*!< SDH_T::INTSTS: CDIF Mask */ + +#define SDH_INTSTS_RTOIF_Pos (12) /*!< SDH_T::INTSTS: RTOIF Position */ +#define SDH_INTSTS_RTOIF_Msk (0x1ul << SDH_INTSTS_RTOIF_Pos) /*!< SDH_T::INTSTS: RTOIF Mask */ + +#define SDH_INTSTS_DITOIF_Pos (13) /*!< SDH_T::INTSTS: DITOIF Position */ +#define SDH_INTSTS_DITOIF_Msk (0x1ul << SDH_INTSTS_DITOIF_Pos) /*!< SDH_T::INTSTS: DITOIF Mask */ + +#define SDH_INTSTS_CDSTS_Pos (16) /*!< SDH_T::INTSTS: CDSTS Position */ +#define SDH_INTSTS_CDSTS_Msk (0x1ul << SDH_INTSTS_CDSTS_Pos) /*!< SDH_T::INTSTS: CDSTS Mask */ + +#define SDH_INTSTS_DAT1STS_Pos (18) /*!< SDH_T::INTSTS: DAT1STS Position */ +#define SDH_INTSTS_DAT1STS_Msk (0x1ul << SDH_INTSTS_DAT1STS_Pos) /*!< SDH_T::INTSTS: DAT1STS Mask */ + +#define SDH_RESP0_RESPTK0_Pos (0) /*!< SDH_T::RESP0: RESPTK0 Position */ +#define SDH_RESP0_RESPTK0_Msk (0xfffffffful << SDH_RESP0_RESPTK0_Pos) /*!< SDH_T::RESP0: RESPTK0 Mask */ + +#define SDH_RESP1_RESPTK1_Pos (0) /*!< SDH_T::RESP1: RESPTK1 Position */ +#define SDH_RESP1_RESPTK1_Msk (0xfful << SDH_RESP1_RESPTK1_Pos) /*!< SDH_T::RESP1: RESPTK1 Mask */ + +#define SDH_BLEN_BLKLEN_Pos (0) /*!< SDH_T::BLEN: BLKLEN Position */ +#define SDH_BLEN_BLKLEN_Msk (0x7fful << SDH_BLEN_BLKLEN_Pos) /*!< SDH_T::BLEN: BLKLEN Mask */ + +#define SDH_TOUT_TOUT_Pos (0) /*!< SDH_T::TOUT: TOUT Position */ +#define SDH_TOUT_TOUT_Msk (0xfffffful << SDH_TOUT_TOUT_Pos) /*!< SDH_T::TOUT: TOUT Mask */ + +/**@}*/ /* SDH_CONST */ +/**@}*/ /* end of SDH register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __SDH_REG_H__ */ + diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/spi_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/spi_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..9bb647fe144f36897162cd26414ce4ef0a838971 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/spi_reg.h @@ -0,0 +1,800 @@ +/**************************************************************************//** + * @file spi_reg.h + * @version V1.00 + * @brief SPI register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SPI_REG_H__ +#define __SPI_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup SPI Serial Peripheral Interface Controller(SPI) + Memory Mapped Structure for SPI Controller +@{ */ + +typedef struct +{ + + + /** + * @var SPI_T::CTL + * Offset: 0x00 SPI Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SPIEN |SPI Transfer Control Enable Bit + * | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1 + * | | |In Slave mode, this device is ready to receive data when this bit is set to 1. + * | | |0 = Transfer control Disabled. + * | | |1 = Transfer control Enabled. + * | | |Note: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers, user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0. + * |[1] |RXNEG |Receive on Negative Edge + * | | |0 = Received data input signal is latched on the rising edge of SPI bus clock. + * | | |1 = Received data input signal is latched on the falling edge of SPI bus clock. + * |[2] |TXNEG |Transmit on Negative Edge + * | | |0 = Transmitted data output signal is changed on the rising edge of SPI bus clock. + * | | |1 = Transmitted data output signal is changed on the falling edge of SPI bus clock. + * |[3] |CLKPOL |Clock Polarity + * | | |0 = SPI bus clock is idle low. + * | | |1 = SPI bus clock is idle high. + * |[7:4] |SUSPITV |Suspend Interval (Master Only) + * | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer + * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word + * | | |The default value is 0x3 + * | | |The period of the suspend interval is obtained according to the following equation. + * | | |(SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle + * | | |Example: + * | | |SUSPITV = 0x0 .... 0.5 SPICLK clock cycle. + * | | |SUSPITV = 0x1 .... 1.5 SPICLK clock cycle. + * | | |..... + * | | |SUSPITV = 0xE .... 14.5 SPICLK clock cycle. + * | | |SUSPITV = 0xF .... 15.5 SPICLK clock cycle. + * |[12:8] |DWIDTH |Data Width + * | | |This field specifies how many bits can be transmitted / received in one transaction + * | | |The minimum bit length is 8 bits and can up to 32 bits. + * | | |DWIDTH = 0x08 .... 8 bits. + * | | |DWIDTH = 0x09 .... 9 bits. + * | | |..... + * | | |DWIDTH = 0x1F .... 31 bits. + * | | |DWIDTH = 0x00 .... 32 bits. + * | | |Note: For SPI1~SPI4, this bit field will decide the depth of TX/RX FIFO configuration in SPI mode + * | | |Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically in SPI1~SPI4. + * |[13] |LSB |Send LSB First + * | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first. + * | | |1 = The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX). + * |[14] |HALFDPX |SPI Half-duplex Transfer Enable Bit + * | | |This bit is used to select full-duplex or half-duplex for SPI transfer + * | | |The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer. + * | | |0 = SPI operates in full-duplex transfer. + * | | |1 = SPI operates in half-duplex transfer. + * |[15] |RXONLY |Receive-only Mode Enable Bit (Master Only) + * | | |This bit field is only available in Master mode + * | | |In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status. + * | | |0 = Receive-only mode Disabled. + * | | |1 = Receive-only mode Enabled. + * |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit + * | | |0 = SPI unit transfer interrupt Disabled. + * | | |1 = SPI unit transfer interrupt Enabled. + * |[18] |SLAVE |Slave Mode Control + * | | |0 = Master mode. + * | | |1 = Slave mode. + * |[19] |REORDER |Byte Reorder Function Enable Bit + * | | |0 = Byte Reorder function Disabled. + * | | |1 = Byte Reorder function Enabled + * | | |A byte suspend interval will be inserted among each byte + * | | |The period of the byte suspend interval depends on the setting of SUSPITV. + * | | |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits. + * |[20] |DATDIR |Data Port Direction Control + * | | |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer + * | | |0 = SPI data is input direction. + * | | |1 = SPI data is output direction. + * @var SPI_T::CLKDIV + * Offset: 0x04 SPI Clock Divider Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |DIVIDER |Clock Divider + * | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master + * | | |The frequency is obtained according to the following equation. + * | | |where + * | | |is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2. + * | | |Note: Not supported in I2S mode. + * @var SPI_T::SSCTL + * Offset: 0x08 SPI Slave Select Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SS |Slave Selection Control (Master Only) + * | | |If AUTOSS bit is cleared to 0, + * | | |0 = set the SPIx_SS line to inactive state. + * | | |1 = set the SPIx_SS line to active state. + * | | |If the AUTOSS bit is set to 1, + * | | |0 = Keep the SPIx_SS line at inactive state. + * | | |1 = SPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time + * | | |The active state of SPIx_SS is specified in SSACTPOL (SPIx_SSCTL[2]). + * |[2] |SSACTPOL |Slave Selection Active Polarity + * | | |This bit defines the active polarity of slave selection signal (SPIx_SS). + * | | |0 = The slave selection signal SPIx_SS is active low. + * | | |1 = The slave selection signal SPIx_SS is active high. + * |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit (Master Only) + * | | |0 = Automatic slave selection function Disabled + * | | |Slave selection signal will be asserted/de-asserted according to SS (SPIx_SSCTL[0]). + * | | |1 = Automatic slave selection function Enabled. + * |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit + * | | |0 = Slave mode bit count error interrupt Disabled. + * | | |1 = Slave mode bit count error interrupt Enabled. + * |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit + * | | |0 = Slave mode TX under run interrupt Disabled. + * | | |1 = Slave mode TX under run interrupt Enabled. + * |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit + * | | |0 = Slave select active interrupt Disabled. + * | | |1 = Slave select active interrupt Enabled. + * |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit + * | | |0 = Slave select inactive interrupt Disabled. + * | | |1 = Slave select inactive interrupt Enabled. + * @var SPI_T::PDMACTL + * Offset: 0x0C SPI PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TXPDMAEN |Transmit PDMA Enable Bit + * | | |0 = Transmit PDMA function Disabled. + * | | |1 = Transmit PDMA function Enabled. + * | | |Note: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function + * | | |User can enable TX PDMA function firstly or enable both functions simultaneously. + * |[1] |RXPDMAEN |Receive PDMA Enable Bit + * | | |0 = Receive PDMA function Disabled. + * | | |1 = Receive PDMA function Enabled. + * |[2] |PDMARST |PDMA Reset + * | | |0 = No effect. + * | | |1 = Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0. + * @var SPI_T::FIFOCTL + * Offset: 0x10 SPI FIFO Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXRST |Receive Reset + * | | |0 = No effect. + * | | |1 = Reset receive FIFO pointer and receive circuit + * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 + * | | |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not. + * |[1] |TXRST |Transmit Reset + * | | |0 = No effect. + * | | |1 = Reset transmit FIFO pointer and transmit circuit + * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 + * | | |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not. + * | | |Note: If TX underflow event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state. + * |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit + * | | |0 = RX FIFO threshold interrupt Disabled. + * | | |1 = RX FIFO threshold interrupt Enabled. + * |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit + * | | |0 = TX FIFO threshold interrupt Disabled. + * | | |1 = TX FIFO threshold interrupt Enabled. + * |[4] |RXTOIEN |Slave Receive Time-out Interrupt Enable Bit + * | | |0 = Receive time-out interrupt Disabled. + * | | |1 = Receive time-out interrupt Enabled. + * |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit + * | | |0 = Receive FIFO overrun interrupt Disabled. + * | | |1 = Receive FIFO overrun interrupt Enabled. + * |[6] |TXUFPOL |TX Underflow Data Polarity + * | | |0 = The SPI data out is keep 0 if there is TX underflow event in Slave mode. + * | | |1 = The SPI data out is keep 1 if there is TX underflow event in Slave mode. + * | | |Note: + * | | |1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active. + * | | |2. This bit should be set as 0 in I2S mode. + * | | |3. When TX underflow event occurs, SPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward + * | | |Data stored in TX FIFO will be sent through SPIx_MISO pin in the next transfer frame. + * |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit + * | | |When TX underflow event occurs in Slave mode, TXUFIF (SPIx_STATUS[19]) will be set to 1 + * | | |This bit is used to enable the TX underflow interrupt. + * | | |0 = Slave TX underflow interrupt Disabled. + * | | |1 = Slave TX underflow interrupt Enabled. + * |[8] |RXFBCLR |Receive FIFO Buffer Clear + * | | |0 = No effect. + * | | |1 = Clear receive FIFO pointer + * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. + * | | |Note: The RX shift register will not be cleared. + * |[9] |TXFBCLR |Transmit FIFO Buffer Clear + * | | |0 = No effect. + * | | |1 = Clear transmit FIFO pointer + * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. + * | | |Note: The TX shift register will not be cleared. + * |[26:24] |RXTH |Receive FIFO Threshold + * | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0 + * | | |For SPI1~SPI4, the MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length. + * |[30:28] |TXTH |Transmit FIFO Threshold + * | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0 + * | | |For SPI1~SPI4, the MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length + * @var SPI_T::STATUS + * Offset: 0x14 SPI Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |Busy Status (Read Only) + * | | |0 = SPI controller is in idle state. + * | | |1 = SPI controller is in busy state. + * | | |The following listing are the bus busy conditions: + * | | |a. SPIx_CTL[0] = 1 and TXEMPTY = 0. + * | | |b + * | | |For SPI Master mode, SPIx_CTL[0] = 1 and TXEMPTY = 1 but the current transaction is not finished yet. + * | | |c. For SPI Master mode, SPIx_CTL[0] = 1 and RXONLY = 1. + * | | |d + * | | |For SPI Slave mode, the SPIx_CTL[0] = 1 and there is serial clock input into the SPI core logic when slave select is active. + * | | |For SPI Slave mode, the SPIx_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive. + * |[1] |UNITIF |Unit Transfer Interrupt Flag + * | | |0 = No transaction has been finished since this bit was cleared to 0. + * | | |1 = SPI controller has finished one unit transfer. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[2] |SSACTIF |Slave Select Active Interrupt Flag + * | | |0 = Slave select active interrupt was cleared or not occurred. + * | | |1 = Slave select active interrupt event occurred. + * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. + * |[3] |SSINAIF |Slave Select Inactive Interrupt Flag + * | | |0 = Slave select inactive interrupt was cleared or not occurred. + * | | |1 = Slave select inactive interrupt event occurred. + * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. + * |[4] |SSLINE |Slave Select Line Bus Status (Read Only) + * | | |0 = The slave select line status is 0. + * | | |1 = The slave select line status is 1. + * | | |Note: This bit is only available in Slave mode + * | | |If SSACTPOL (SPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status. + * |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag + * | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1. + * | | |0 = No Slave mode bit count error event. + * | | |1 = Slave mode bit count error event occurs. + * | | |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state + * | | |This bit will be cleared by writing 1 to it. + * |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag + * | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1. + * | | |0 = No Slave TX under run event. + * | | |1 = Slave TX under run event occurs. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not empty. + * | | |1 = Receive FIFO buffer is empty. + * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not full. + * | | |1 = Receive FIFO buffer is full. + * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH. + * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH. + * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag + * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. + * | | |0 = No FIFO is overrun. + * | | |1 = Receive FIFO is overrun. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[12] |RXTOIF |Receive Time-out Interrupt Flag + * | | |0 = No receive FIFO time-out event. + * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode + * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[15] |SPIENSTS |SPI Enable Status (Read Only) + * | | |0 = The SPI controller is disabled. + * | | |1 = The SPI controller is enabled. + * | | |Note: The SPI peripheral clock is asynchronous with the system clock + * | | |In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller. + * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not empty. + * | | |1 = Transmit FIFO buffer is empty. + * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not full. + * | | |1 = Transmit FIFO buffer is full. + * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH. + * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH. + * |[19] |TXUFIF |TX Underflow Interrupt Flag + * | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL. + * | | |0 = No effect. + * | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active. + * | | |Note 1: This bit will be cleared by writing 1 to it. + * | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done. + * |[23] |TXRXRST |TX or RX Reset Status (Read Only) + * | | |0 = The reset function of TXRST or RXRST is done. + * | | |1 = Doing the reset function of TXRST or RXRST. + * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles + * | | |User can check the status of this bit to monitor the reset function is doing or done. + * |[27:24] |RXCNT |Receive FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of receive FIFO buffer. + * |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of transmit FIFO buffer. + * @var SPI_T::TX + * Offset: 0x20 SPI Data Transmit Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TX |Data Transmit Register + * | | |The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers + * | | |The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S mode. + * | | |In SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted + * | | |If DWIDTH is set to 0x00 , the SPI controller will perform a 32-bit transfer. + * | | |In I2S mode, if WDWIDTH (SPIx_I2SCTL[5:4]) is set to 0x2, the data width of audio channel is 24-bit and corresponding to TX[23:0] + * | | |If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid and referred to the data arrangement in I2S mode FIFO operation section + * | | |Note: In Master mode, SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register. + * @var SPI_T::RX + * Offset: 0x30 SPI Data Receive Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RX |Data Receive Register + * | | |There are 4-level FIFO buffers in this controller + * | | |The data receive register holds the data received from SPI data input pin + * | | |If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register + * | | |This is a read only register. + * @var SPI_T::I2SCTL + * Offset: 0x60 I2S Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |I2SEN |I2S Controller Enable Bit + * | | |0 = Disabled I2S mode. + * | | |1 = Enabled I2S mode. + * | | |Note: + * | | |1. If enable this bit, I2Sx_BCLK will start to output in Master mode. + * | | |2 + * | | |Before changing the configurations of SPIx_I2SCTL, SPIx_I2SCLK, and SPIx_FIFOCTL registers, user shall clear the I2SEN (SPIx_I2SCTL[0]) and confirm the I2SENSTS (SPIx_I2SSTS[15]) is 0. + * |[1] |TXEN |Transmit Enable Bit + * | | |0 = Data transmit Disabled. + * | | |1 = Data transmit Enabled. + * |[2] |RXEN |Receive Enable Bit + * | | |0 = Data receive Disabled. + * | | |1 = Data receive Enabled. + * |[3] |MUTE |Transmit Mute Enable Bit + * | | |0 = Transmit data is shifted from buffer. + * | | |1 = Transmit channel zero. + * |[5:4] |WDWIDTH |Word Width + * | | |00 = data size is 8-bit. + * | | |01 = data size is 16-bit. + * | | |10 = data size is 24-bit. + * | | |11 = data size is 32-bit. + * |[6] |MONO |Monaural Data + * | | |0 = Data is stereo format. + * | | |1 = Data is monaural format. + * |[7] |ORDER |Stereo Data Order in FIFO + * | | |0 = Left channel data at high byte. + * | | |1 = Left channel data at low byte. + * |[8] |SLAVE |Slave Mode + * | | |I2S can operate as master or slave + * | | |For Master mode, I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from NuMicro M480 series to audio CODEC chip + * | | |In Slave mode, I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and I2Sx_LRCLK signals are received from outer audio CODEC chip. + * | | |0 = Master mode. + * | | |1 = Slave mode. + * |[15] |MCLKEN |Master Clock Enable Bit + * | | |If MCLKEN is set to 1, I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices. + * | | |0 = Master clock Disabled. + * | | |1 = Master clock Enabled. + * |[16] |RZCEN |Right Channel Zero Cross Detection Enable Bit + * | | |If this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1 + * | | |This function is only available in transmit operation. + * | | |0 = Right channel zero cross detection Disabled. + * | | |1 = Right channel zero cross detection Enabled. + * |[17] |LZCEN |Left Channel Zero Cross Detection Enable Bit + * | | |If this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1 + * | | |This function is only available in transmit operation. + * | | |0 = Left channel zero cross detection Disabled. + * | | |1 = Left channel zero cross detection Enabled. + * |[23] |RXLCH |Receive Left Channel Enable Bit + * | | |When monaural format is selected (MONO = 1), I2S controller will receive right channel data if RXLCH is set to 0, and receive left channel data if RXLCH is set to 1. + * | | |0 = Receive right channel data in Mono mode. + * | | |1 = Receive left channel data in Mono mode. + * |[24] |RZCIEN |Right Channel Zero Cross Interrupt Enable Bit + * | | |Interrupt occurs if this bit is set to 1 and right channel zero cross event occurs. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[25] |LZCIEN |Left Channel Zero Cross Interrupt Enable Bit + * | | |Interrupt occurs if this bit is set to 1 and left channel zero cross event occurs. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[29:28] |FORMAT |Data Format Selection + * | | |00 = I2S data format. + * | | |01 = MSB justified data format. + * | | |10 = PCM mode A. + * | | |11 = PCM mode B. + * @var SPI_T::I2SCLK + * Offset: 0x64 I2S Clock Divider Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |MCLKDIV |Master Clock Divider + * | | |If MCLKEN is set to 1, I2S controller will generate master clock for external audio devices + * | | |The frequency of master clock, fMCLK, is determined by the following expressions: + * | | |If MCLKDIV >= 1,. + * | | |If MCLKDIV = 0,. + * | | |where + * | | |is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2 + * | | |In general, the master clock rate is 256 times sampling clock rate. + * |[17:8] |BCLKDIV |Bit Clock Divider + * | | |The I2S controller will generate bit clock in Master mode + * | | |The clock frequency of bit clock , fBCLK, is determined by the following expression: + * | | |where + * | | |is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2. + * | | |In I2S Slave mode, this field is used to define the frequency of peripheral clock and it's determined by . + * | | |The peripheral clock frequency in I2S Slave mode must be equal to or faster than 6 times of input bit clock. + * @var SPI_T::I2SSTS + * Offset: 0x68 I2S Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4] |RIGHT |Right Channel (Read Only) + * | | |This bit indicates the current transmit data is belong to which channel. + * | | |0 = Left channel. + * | | |1 = Right channel. + * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not empty. + * | | |1 = Receive FIFO buffer is empty. + * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not full. + * | | |1 = Receive FIFO buffer is full. + * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH. + * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH. + * | | |Note: If RXTHIEN = 1 and RXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request. + * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag + * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[12] |RXTOIF |Receive Time-out Interrupt Flag + * | | |0 = No receive FIFO time-out event. + * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock period in Master mode or over 576 SPI peripheral clock period in Slave mode + * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[15] |I2SENSTS |I2S Enable Status (Read Only) + * | | |0 = The SPI/I2S control logic is disabled. + * | | |1 = The SPI/I2S control logic is enabled. + * | | |Note: The SPI peripheral clock is asynchronous with the system clock + * | | |In order to make sure the SPI/I2S control logic is disabled, this bit indicates the real status of SPI/I2S control logic for user. + * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not empty. + * | | |1 = Transmit FIFO buffer is empty. + * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not full. + * | | |1 = Transmit FIFO buffer is full. + * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH. + * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH. + * | | |Note: If TXTHIEN = 1 and TXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request. + * |[19] |TXUFIF |Transmit FIFO Underflow Interrupt Flag + * | | |When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, this bit will be set to 1. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[20] |RZCIF |Right Channel Zero Cross Interrupt Flag + * | | |0 = No zero cross event occurred on right channel. + * | | |1 = Zero cross event occurred on right channel. + * |[21] |LZCIF |Left Channel Zero Cross Interrupt Flag + * | | |0 = No zero cross event occurred on left channel. + * | | |1 = Zero cross event occurred on left channel. + * |[23] |TXRXRST |TX or RX Reset Status (Read Only) + * | | |0 = The reset function of TXRST or RXRST is done. + * | | |1 = Doing the reset function of TXRST or RXRST. + * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles + * | | |User can check the status of this bit to monitor the reset function is doing or done. + * |[26:24] |RXCNT |Receive FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of receive FIFO buffer. + * |[30:28] |TXCNT |Transmit FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of transmit FIFO buffer. + */ + __IO uint32_t CTL; /*!< [0x0000] SPI Control Register */ + __IO uint32_t CLKDIV; /*!< [0x0004] SPI Clock Divider Register */ + __IO uint32_t SSCTL; /*!< [0x0008] SPI Slave Select Control Register */ + __IO uint32_t PDMACTL; /*!< [0x000c] SPI PDMA Control Register */ + __IO uint32_t FIFOCTL; /*!< [0x0010] SPI FIFO Control Register */ + __IO uint32_t STATUS; /*!< [0x0014] SPI Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[2]; + /// @endcond //HIDDEN_SYMBOLS + __O uint32_t TX; /*!< [0x0020] SPI Data Transmit Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[3]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t RX; /*!< [0x0030] SPI Data Receive Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[11]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t I2SCTL; /*!< [0x0060] I2S Control Register */ + __IO uint32_t I2SCLK; /*!< [0x0064] I2S Clock Divider Control Register */ + __IO uint32_t I2SSTS; /*!< [0x0068] I2S Status Register */ + +} SPI_T; + +/** + @addtogroup SPI_CONST SPI Bit Field Definition + Constant Definitions for SPI Controller +@{ */ + +#define SPI_CTL_SPIEN_Pos (0) /*!< SPI_T::CTL: SPIEN Position */ +#define SPI_CTL_SPIEN_Msk (0x1ul << SPI_CTL_SPIEN_Pos) /*!< SPI_T::CTL: SPIEN Mask */ + +#define SPI_CTL_RXNEG_Pos (1) /*!< SPI_T::CTL: RXNEG Position */ +#define SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos) /*!< SPI_T::CTL: RXNEG Mask */ + +#define SPI_CTL_TXNEG_Pos (2) /*!< SPI_T::CTL: TXNEG Position */ +#define SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos) /*!< SPI_T::CTL: TXNEG Mask */ + +#define SPI_CTL_CLKPOL_Pos (3) /*!< SPI_T::CTL: CLKPOL Position */ +#define SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos) /*!< SPI_T::CTL: CLKPOL Mask */ + +#define SPI_CTL_SUSPITV_Pos (4) /*!< SPI_T::CTL: SUSPITV Position */ +#define SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos) /*!< SPI_T::CTL: SUSPITV Mask */ + +#define SPI_CTL_DWIDTH_Pos (8) /*!< SPI_T::CTL: DWIDTH Position */ +#define SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos) /*!< SPI_T::CTL: DWIDTH Mask */ + +#define SPI_CTL_LSB_Pos (13) /*!< SPI_T::CTL: LSB Position */ +#define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos) /*!< SPI_T::CTL: LSB Mask */ + +#define SPI_CTL_HALFDPX_Pos (14) /*!< SPI_T::CTL: HALFDPX Position */ +#define SPI_CTL_HALFDPX_Msk (0x1ul << SPI_CTL_HALFDPX_Pos) /*!< SPI_T::CTL: HALFDPX Mask */ + +#define SPI_CTL_RXONLY_Pos (15) /*!< SPI_T::CTL: RXONLY Position */ +#define SPI_CTL_RXONLY_Msk (0x1ul << SPI_CTL_RXONLY_Pos) /*!< SPI_T::CTL: RXONLY Mask */ + +#define SPI_CTL_UNITIEN_Pos (17) /*!< SPI_T::CTL: UNITIEN Position */ +#define SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos) /*!< SPI_T::CTL: UNITIEN Mask */ + +#define SPI_CTL_SLAVE_Pos (18) /*!< SPI_T::CTL: SLAVE Position */ +#define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos) /*!< SPI_T::CTL: SLAVE Mask */ + +#define SPI_CTL_REORDER_Pos (19) /*!< SPI_T::CTL: REORDER Position */ +#define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos) /*!< SPI_T::CTL: REORDER Mask */ + +#define SPI_CTL_DATDIR_Pos (20) /*!< SPI_T::CTL: DATDIR Position */ +#define SPI_CTL_DATDIR_Msk (0x1ul << SPI_CTL_DATDIR_Pos) /*!< SPI_T::CTL: DATDIR Mask */ + +#define SPI_CLKDIV_DIVIDER_Pos (0) /*!< SPI_T::CLKDIV: DIVIDER Position */ +#define SPI_CLKDIV_DIVIDER_Msk (0x1fful << SPI_CLKDIV_DIVIDER_Pos) /*!< SPI_T::CLKDIV: DIVIDER Mask */ + +#define SPI_SSCTL_SS_Pos (0) /*!< SPI_T::SSCTL: SS Position */ +#define SPI_SSCTL_SS_Msk (0x1ul << SPI_SSCTL_SS_Pos) /*!< SPI_T::SSCTL: SS Mask */ + +#define SPI_SSCTL_SSACTPOL_Pos (2) /*!< SPI_T::SSCTL: SSACTPOL Position */ +#define SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos) /*!< SPI_T::SSCTL: SSACTPOL Mask */ + +#define SPI_SSCTL_AUTOSS_Pos (3) /*!< SPI_T::SSCTL: AUTOSS Position */ +#define SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos) /*!< SPI_T::SSCTL: AUTOSS Mask */ + +#define SPI_SSCTL_SLVBEIEN_Pos (8) /*!< SPI_T::SSCTL: SLVBEIEN Position */ +#define SPI_SSCTL_SLVBEIEN_Msk (0x1ul << SPI_SSCTL_SLVBEIEN_Pos) /*!< SPI_T::SSCTL: SLVBEIEN Mask */ + +#define SPI_SSCTL_SLVURIEN_Pos (9) /*!< SPI_T::SSCTL: SLVURIEN Position */ +#define SPI_SSCTL_SLVURIEN_Msk (0x1ul << SPI_SSCTL_SLVURIEN_Pos) /*!< SPI_T::SSCTL: SLVURIEN Mask */ + +#define SPI_SSCTL_SSACTIEN_Pos (12) /*!< SPI_T::SSCTL: SSACTIEN Position */ +#define SPI_SSCTL_SSACTIEN_Msk (0x1ul << SPI_SSCTL_SSACTIEN_Pos) /*!< SPI_T::SSCTL: SSACTIEN Mask */ + +#define SPI_SSCTL_SSINAIEN_Pos (13) /*!< SPI_T::SSCTL: SSINAIEN Position */ +#define SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos) /*!< SPI_T::SSCTL: SSINAIEN Mask */ + +#define SPI_SSCTL_SLVTOCNT_Pos (16) /*!< SPI_T::SSCTL: SLVTOCNT Position */ +#define SPI_SSCTL_SLVTOCNT_Msk (0xfffful << SPI_SSCTL_SLVTOCNT_Pos) /*!< SPI_T::SSCTL: SLVTOCNT Mask */ + +#define SPI_PDMACTL_TXPDMAEN_Pos (0) /*!< SPI_T::PDMACTL: TXPDMAEN Position */ +#define SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos) /*!< SPI_T::PDMACTL: TXPDMAEN Mask */ + +#define SPI_PDMACTL_RXPDMAEN_Pos (1) /*!< SPI_T::PDMACTL: RXPDMAEN Position */ +#define SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos) /*!< SPI_T::PDMACTL: RXPDMAEN Mask */ + +#define SPI_PDMACTL_PDMARST_Pos (2) /*!< SPI_T::PDMACTL: PDMARST Position */ +#define SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos) /*!< SPI_T::PDMACTL: PDMARST Mask */ + +#define SPI_FIFOCTL_RXRST_Pos (0) /*!< SPI_T::FIFOCTL: RXRST Position */ +#define SPI_FIFOCTL_RXRST_Msk (0x1ul << SPI_FIFOCTL_RXRST_Pos) /*!< SPI_T::FIFOCTL: RXRST Mask */ + +#define SPI_FIFOCTL_TXRST_Pos (1) /*!< SPI_T::FIFOCTL: TXRST Position */ +#define SPI_FIFOCTL_TXRST_Msk (0x1ul << SPI_FIFOCTL_TXRST_Pos) /*!< SPI_T::FIFOCTL: TXRST Mask */ + +#define SPI_FIFOCTL_RXTHIEN_Pos (2) /*!< SPI_T::FIFOCTL: RXTHIEN Position */ +#define SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos) /*!< SPI_T::FIFOCTL: RXTHIEN Mask */ + +#define SPI_FIFOCTL_TXTHIEN_Pos (3) /*!< SPI_T::FIFOCTL: TXTHIEN Position */ +#define SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos) /*!< SPI_T::FIFOCTL: TXTHIEN Mask */ + +#define SPI_FIFOCTL_RXTOIEN_Pos (4) /*!< SPI_T::FIFOCTL: RXTOIEN Position */ +#define SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos) /*!< SPI_T::FIFOCTL: RXTOIEN Mask */ + +#define SPI_FIFOCTL_RXOVIEN_Pos (5) /*!< SPI_T::FIFOCTL: RXOVIEN Position */ +#define SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos) /*!< SPI_T::FIFOCTL: RXOVIEN Mask */ + +#define SPI_FIFOCTL_TXUFPOL_Pos (6) /*!< SPI_T::FIFOCTL: TXUFPOL Position */ +#define SPI_FIFOCTL_TXUFPOL_Msk (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos) /*!< SPI_T::FIFOCTL: TXUFPOL Mask */ + +#define SPI_FIFOCTL_TXUFIEN_Pos (7) /*!< SPI_T::FIFOCTL: TXUFIEN Position */ +#define SPI_FIFOCTL_TXUFIEN_Msk (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos) /*!< SPI_T::FIFOCTL: TXUFIEN Mask */ + +#define SPI_FIFOCTL_RXFBCLR_Pos (8) /*!< SPI_T::FIFOCTL: RXFBCLR Position */ +#define SPI_FIFOCTL_RXFBCLR_Msk (0x1ul << SPI_FIFOCTL_RXFBCLR_Pos) /*!< SPI_T::FIFOCTL: RXFBCLR Mask */ + +#define SPI_FIFOCTL_TXFBCLR_Pos (9) /*!< SPI_T::FIFOCTL: TXFBCLR Position */ +#define SPI_FIFOCTL_TXFBCLR_Msk (0x1ul << SPI_FIFOCTL_TXFBCLR_Pos) /*!< SPI_T::FIFOCTL: TXFBCLR Mask */ + +#define SPI_FIFOCTL_RXTH_Pos (24) /*!< SPI_T::FIFOCTL: RXTH Position */ +#define SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos) /*!< SPI_T::FIFOCTL: RXTH Mask */ + +#define SPI_FIFOCTL_TXTH_Pos (28) /*!< SPI_T::FIFOCTL: TXTH Position */ +#define SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos) /*!< SPI_T::FIFOCTL: TXTH Mask */ + +#define SPI_STATUS_BUSY_Pos (0) /*!< SPI_T::STATUS: BUSY Position */ +#define SPI_STATUS_BUSY_Msk (0x1ul << SPI_STATUS_BUSY_Pos) /*!< SPI_T::STATUS: BUSY Mask */ + +#define SPI_STATUS_UNITIF_Pos (1) /*!< SPI_T::STATUS: UNITIF Position */ +#define SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos) /*!< SPI_T::STATUS: UNITIF Mask */ + +#define SPI_STATUS_SSACTIF_Pos (2) /*!< SPI_T::STATUS: SSACTIF Position */ +#define SPI_STATUS_SSACTIF_Msk (0x1ul << SPI_STATUS_SSACTIF_Pos) /*!< SPI_T::STATUS: SSACTIF Mask */ + +#define SPI_STATUS_SSINAIF_Pos (3) /*!< SPI_T::STATUS: SSINAIF Position */ +#define SPI_STATUS_SSINAIF_Msk (0x1ul << SPI_STATUS_SSINAIF_Pos) /*!< SPI_T::STATUS: SSINAIF Mask */ + +#define SPI_STATUS_SSLINE_Pos (4) /*!< SPI_T::STATUS: SSLINE Position */ +#define SPI_STATUS_SSLINE_Msk (0x1ul << SPI_STATUS_SSLINE_Pos) /*!< SPI_T::STATUS: SSLINE Mask */ + +#define SPI_STATUS_SLVBEIF_Pos (6) /*!< SPI_T::STATUS: SLVBEIF Position */ +#define SPI_STATUS_SLVBEIF_Msk (0x1ul << SPI_STATUS_SLVBEIF_Pos) /*!< SPI_T::STATUS: SLVBEIF Mask */ + +#define SPI_STATUS_SLVURIF_Pos (7) /*!< SPI_T::STATUS: SLVURIF Position */ +#define SPI_STATUS_SLVURIF_Msk (0x1ul << SPI_STATUS_SLVURIF_Pos) /*!< SPI_T::STATUS: SLVURIF Mask */ + +#define SPI_STATUS_RXEMPTY_Pos (8) /*!< SPI_T::STATUS: RXEMPTY Position */ +#define SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos) /*!< SPI_T::STATUS: RXEMPTY Mask */ + +#define SPI_STATUS_RXFULL_Pos (9) /*!< SPI_T::STATUS: RXFULL Position */ +#define SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos) /*!< SPI_T::STATUS: RXFULL Mask */ + +#define SPI_STATUS_RXTHIF_Pos (10) /*!< SPI_T::STATUS: RXTHIF Position */ +#define SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos) /*!< SPI_T::STATUS: RXTHIF Mask */ + +#define SPI_STATUS_RXOVIF_Pos (11) /*!< SPI_T::STATUS: RXOVIF Position */ +#define SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos) /*!< SPI_T::STATUS: RXOVIF Mask */ + +#define SPI_STATUS_RXTOIF_Pos (12) /*!< SPI_T::STATUS: RXTOIF Position */ +#define SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos) /*!< SPI_T::STATUS: RXTOIF Mask */ + +#define SPI_STATUS_SPIENSTS_Pos (15) /*!< SPI_T::STATUS: SPIENSTS Position */ +#define SPI_STATUS_SPIENSTS_Msk (0x1ul << SPI_STATUS_SPIENSTS_Pos) /*!< SPI_T::STATUS: SPIENSTS Mask */ + +#define SPI_STATUS_TXEMPTY_Pos (16) /*!< SPI_T::STATUS: TXEMPTY Position */ +#define SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos) /*!< SPI_T::STATUS: TXEMPTY Mask */ + +#define SPI_STATUS_TXFULL_Pos (17) /*!< SPI_T::STATUS: TXFULL Position */ +#define SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos) /*!< SPI_T::STATUS: TXFULL Mask */ + +#define SPI_STATUS_TXTHIF_Pos (18) /*!< SPI_T::STATUS: TXTHIF Position */ +#define SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos) /*!< SPI_T::STATUS: TXTHIF Mask */ + +#define SPI_STATUS_TXUFIF_Pos (19) /*!< SPI_T::STATUS: TXUFIF Position */ +#define SPI_STATUS_TXUFIF_Msk (0x1ul << SPI_STATUS_TXUFIF_Pos) /*!< SPI_T::STATUS: TXUFIF Mask */ + +#define SPI_STATUS_TXRXRST_Pos (23) /*!< SPI_T::STATUS: TXRXRST Position */ +#define SPI_STATUS_TXRXRST_Msk (0x1ul << SPI_STATUS_TXRXRST_Pos) /*!< SPI_T::STATUS: TXRXRST Mask */ + +#define SPI_STATUS_RXCNT_Pos (24) /*!< SPI_T::STATUS: RXCNT Position */ +#define SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos) /*!< SPI_T::STATUS: RXCNT Mask */ + +#define SPI_STATUS_TXCNT_Pos (28) /*!< SPI_T::STATUS: TXCNT Position */ +#define SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos) /*!< SPI_T::STATUS: TXCNT Mask */ + +#define SPI_TX_TX_Pos (0) /*!< SPI_T::TX: TX Position */ +#define SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos) /*!< SPI_T::TX: TX Mask */ + +#define SPI_RX_RX_Pos (0) /*!< SPI_T::RX: RX Position */ +#define SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos) /*!< SPI_T::RX: RX Mask */ + +#define SPI_I2SCTL_I2SEN_Pos (0) /*!< SPI_T::I2SCTL: I2SEN Position */ +#define SPI_I2SCTL_I2SEN_Msk (0x1ul << SPI_I2SCTL_I2SEN_Pos) /*!< SPI_T::I2SCTL: I2SEN Mask */ + +#define SPI_I2SCTL_TXEN_Pos (1) /*!< SPI_T::I2SCTL: TXEN Position */ +#define SPI_I2SCTL_TXEN_Msk (0x1ul << SPI_I2SCTL_TXEN_Pos) /*!< SPI_T::I2SCTL: TXEN Mask */ + +#define SPI_I2SCTL_RXEN_Pos (2) /*!< SPI_T::I2SCTL: RXEN Position */ +#define SPI_I2SCTL_RXEN_Msk (0x1ul << SPI_I2SCTL_RXEN_Pos) /*!< SPI_T::I2SCTL: RXEN Mask */ + +#define SPI_I2SCTL_MUTE_Pos (3) /*!< SPI_T::I2SCTL: MUTE Position */ +#define SPI_I2SCTL_MUTE_Msk (0x1ul << SPI_I2SCTL_MUTE_Pos) /*!< SPI_T::I2SCTL: MUTE Mask */ + +#define SPI_I2SCTL_WDWIDTH_Pos (4) /*!< SPI_T::I2SCTL: WDWIDTH Position */ +#define SPI_I2SCTL_WDWIDTH_Msk (0x3ul << SPI_I2SCTL_WDWIDTH_Pos) /*!< SPI_T::I2SCTL: WDWIDTH Mask */ + +#define SPI_I2SCTL_MONO_Pos (6) /*!< SPI_T::I2SCTL: MONO Position */ +#define SPI_I2SCTL_MONO_Msk (0x1ul << SPI_I2SCTL_MONO_Pos) /*!< SPI_T::I2SCTL: MONO Mask */ + +#define SPI_I2SCTL_ORDER_Pos (7) /*!< SPI_T::I2SCTL: ORDER Position */ +#define SPI_I2SCTL_ORDER_Msk (0x1ul << SPI_I2SCTL_ORDER_Pos) /*!< SPI_T::I2SCTL: ORDER Mask */ + +#define SPI_I2SCTL_SLAVE_Pos (8) /*!< SPI_T::I2SCTL: SLAVE Position */ +#define SPI_I2SCTL_SLAVE_Msk (0x1ul << SPI_I2SCTL_SLAVE_Pos) /*!< SPI_T::I2SCTL: SLAVE Mask */ + +#define SPI_I2SCTL_MCLKEN_Pos (15) /*!< SPI_T::I2SCTL: MCLKEN Position */ +#define SPI_I2SCTL_MCLKEN_Msk (0x1ul << SPI_I2SCTL_MCLKEN_Pos) /*!< SPI_T::I2SCTL: MCLKEN Mask */ + +#define SPI_I2SCTL_RZCEN_Pos (16) /*!< SPI_T::I2SCTL: RZCEN Position */ +#define SPI_I2SCTL_RZCEN_Msk (0x1ul << SPI_I2SCTL_RZCEN_Pos) /*!< SPI_T::I2SCTL: RZCEN Mask */ + +#define SPI_I2SCTL_LZCEN_Pos (17) /*!< SPI_T::I2SCTL: LZCEN Position */ +#define SPI_I2SCTL_LZCEN_Msk (0x1ul << SPI_I2SCTL_LZCEN_Pos) /*!< SPI_T::I2SCTL: LZCEN Mask */ + +#define SPI_I2SCTL_RXLCH_Pos (23) /*!< SPI_T::I2SCTL: RXLCH Position */ +#define SPI_I2SCTL_RXLCH_Msk (0x1ul << SPI_I2SCTL_RXLCH_Pos) /*!< SPI_T::I2SCTL: RXLCH Mask */ + +#define SPI_I2SCTL_RZCIEN_Pos (24) /*!< SPI_T::I2SCTL: RZCIEN Position */ +#define SPI_I2SCTL_RZCIEN_Msk (0x1ul << SPI_I2SCTL_RZCIEN_Pos) /*!< SPI_T::I2SCTL: RZCIEN Mask */ + +#define SPI_I2SCTL_LZCIEN_Pos (25) /*!< SPI_T::I2SCTL: LZCIEN Position */ +#define SPI_I2SCTL_LZCIEN_Msk (0x1ul << SPI_I2SCTL_LZCIEN_Pos) /*!< SPI_T::I2SCTL: LZCIEN Mask */ + +#define SPI_I2SCTL_FORMAT_Pos (28) /*!< SPI_T::I2SCTL: FORMAT Position */ +#define SPI_I2SCTL_FORMAT_Msk (0x3ul << SPI_I2SCTL_FORMAT_Pos) /*!< SPI_T::I2SCTL: FORMAT Mask */ + +#define SPI_I2SCLK_MCLKDIV_Pos (0) /*!< SPI_T::I2SCLK: MCLKDIV Position */ +#define SPI_I2SCLK_MCLKDIV_Msk (0x7ful << SPI_I2SCLK_MCLKDIV_Pos) /*!< SPI_T::I2SCLK: MCLKDIV Mask */ + +#define SPI_I2SCLK_BCLKDIV_Pos (8) /*!< SPI_T::I2SCLK: BCLKDIV Position */ +#define SPI_I2SCLK_BCLKDIV_Msk (0x3fful << SPI_I2SCLK_BCLKDIV_Pos) /*!< SPI_T::I2SCLK: BCLKDIV Mask */ + +#define SPI_I2SSTS_RIGHT_Pos (4) /*!< SPI_T::I2SSTS: RIGHT Position */ +#define SPI_I2SSTS_RIGHT_Msk (0x1ul << SPI_I2SSTS_RIGHT_Pos) /*!< SPI_T::I2SSTS: RIGHT Mask */ + +#define SPI_I2SSTS_RXEMPTY_Pos (8) /*!< SPI_T::I2SSTS: RXEMPTY Position */ +#define SPI_I2SSTS_RXEMPTY_Msk (0x1ul << SPI_I2SSTS_RXEMPTY_Pos) /*!< SPI_T::I2SSTS: RXEMPTY Mask */ + +#define SPI_I2SSTS_RXFULL_Pos (9) /*!< SPI_T::I2SSTS: RXFULL Position */ +#define SPI_I2SSTS_RXFULL_Msk (0x1ul << SPI_I2SSTS_RXFULL_Pos) /*!< SPI_T::I2SSTS: RXFULL Mask */ + +#define SPI_I2SSTS_RXTHIF_Pos (10) /*!< SPI_T::I2SSTS: RXTHIF Position */ +#define SPI_I2SSTS_RXTHIF_Msk (0x1ul << SPI_I2SSTS_RXTHIF_Pos) /*!< SPI_T::I2SSTS: RXTHIF Mask */ + +#define SPI_I2SSTS_RXOVIF_Pos (11) /*!< SPI_T::I2SSTS: RXOVIF Position */ +#define SPI_I2SSTS_RXOVIF_Msk (0x1ul << SPI_I2SSTS_RXOVIF_Pos) /*!< SPI_T::I2SSTS: RXOVIF Mask */ + +#define SPI_I2SSTS_RXTOIF_Pos (12) /*!< SPI_T::I2SSTS: RXTOIF Position */ +#define SPI_I2SSTS_RXTOIF_Msk (0x1ul << SPI_I2SSTS_RXTOIF_Pos) /*!< SPI_T::I2SSTS: RXTOIF Mask */ + +#define SPI_I2SSTS_I2SENSTS_Pos (15) /*!< SPI_T::I2SSTS: I2SENSTS Position */ +#define SPI_I2SSTS_I2SENSTS_Msk (0x1ul << SPI_I2SSTS_I2SENSTS_Pos) /*!< SPI_T::I2SSTS: I2SENSTS Mask */ + +#define SPI_I2SSTS_TXEMPTY_Pos (16) /*!< SPI_T::I2SSTS: TXEMPTY Position */ +#define SPI_I2SSTS_TXEMPTY_Msk (0x1ul << SPI_I2SSTS_TXEMPTY_Pos) /*!< SPI_T::I2SSTS: TXEMPTY Mask */ + +#define SPI_I2SSTS_TXFULL_Pos (17) /*!< SPI_T::I2SSTS: TXFULL Position */ +#define SPI_I2SSTS_TXFULL_Msk (0x1ul << SPI_I2SSTS_TXFULL_Pos) /*!< SPI_T::I2SSTS: TXFULL Mask */ + +#define SPI_I2SSTS_TXTHIF_Pos (18) /*!< SPI_T::I2SSTS: TXTHIF Position */ +#define SPI_I2SSTS_TXTHIF_Msk (0x1ul << SPI_I2SSTS_TXTHIF_Pos) /*!< SPI_T::I2SSTS: TXTHIF Mask */ + +#define SPI_I2SSTS_TXUFIF_Pos (19) /*!< SPI_T::I2SSTS: TXUFIF Position */ +#define SPI_I2SSTS_TXUFIF_Msk (0x1ul << SPI_I2SSTS_TXUFIF_Pos) /*!< SPI_T::I2SSTS: TXUFIF Mask */ + +#define SPI_I2SSTS_RZCIF_Pos (20) /*!< SPI_T::I2SSTS: RZCIF Position */ +#define SPI_I2SSTS_RZCIF_Msk (0x1ul << SPI_I2SSTS_RZCIF_Pos) /*!< SPI_T::I2SSTS: RZCIF Mask */ + +#define SPI_I2SSTS_LZCIF_Pos (21) /*!< SPI_T::I2SSTS: LZCIF Position */ +#define SPI_I2SSTS_LZCIF_Msk (0x1ul << SPI_I2SSTS_LZCIF_Pos) /*!< SPI_T::I2SSTS: LZCIF Mask */ + +#define SPI_I2SSTS_TXRXRST_Pos (23) /*!< SPI_T::I2SSTS: TXRXRST Position */ +#define SPI_I2SSTS_TXRXRST_Msk (0x1ul << SPI_I2SSTS_TXRXRST_Pos) /*!< SPI_T::I2SSTS: TXRXRST Mask */ + +#define SPI_I2SSTS_RXCNT_Pos (24) /*!< SPI_T::I2SSTS: RXCNT Position */ +#define SPI_I2SSTS_RXCNT_Msk (0x7ul << SPI_I2SSTS_RXCNT_Pos) /*!< SPI_T::I2SSTS: RXCNT Mask */ + +#define SPI_I2SSTS_TXCNT_Pos (28) /*!< SPI_T::I2SSTS: TXCNT Position */ +#define SPI_I2SSTS_TXCNT_Msk (0x7ul << SPI_I2SSTS_TXCNT_Pos) /*!< SPI_T::I2SSTS: TXCNT Mask */ + +/**@}*/ /* SPI_CONST */ +/**@}*/ /* end of SPI register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __SPI_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/spim_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/spim_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..59a9a343f18c94ab3ba88a42622cb40fda88b147 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/spim_reg.h @@ -0,0 +1,557 @@ +/**************************************************************************//** + * @file spim_reg.h + * @version V1.00 + * @brief SPIM register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SPIM_REG_H__ +#define __SPIM_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup SPIM Serial Peripheral Interface Controller Master Mode (SPIM) + Memory Mapped Structure for SPIM Controller +@{ */ + +typedef struct +{ + + + /** + * @var SPIM_T::CTL0 + * Offset: 0x00 Control and Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CIPHOFF |Cipher Disable Control + * | | |0 = Cipher function Enabled. + * | | |1 = Cipher function Disabled. + * | | |Note1: If there is not any KEY1(SPIM_KEY1[31:0]) or KEY2(SPIM_KEY2[31:0]) (KEY1 is 0x0000_0000 or KEY2 is 0x0000_0000), the cipher function will be disabled automatically. + * | | |Note2: When CIPHOFF(SPIM_CTL0[0]) is 0, both of KEY1(SPIM_KEY1[31:0]) and KEY2(SPIM_KEY2[31:0]) do not equal to 0x0000_0000 (i.e. + * | | |KEY1 != 0x0000_0000 and KEY2 != 0x0000_0000), cipher encryption/decryption is enabled. + * | | |Note3 : When cipher encryption/decryption is enabled, please set DESELTIM (SPIM_DMMCTL[20:16]) >= 0x10. + * | | |When cipher encryption/decryption is disabled, please set DESELTIM(SPIM_DMMCTL[20:16]) >= 0x8. + * |[2] |BALEN |Balance the AHB Control Time Between Cipher Enable and Disable Control + * | | |When cipher is enabled, the AHB control signal will delay some time caused by the encoding or decoding calculation + * | | |Therefore, if set BALEN to 1, it will make the AHB signal processing time with cipher disabled be equal to that with cipher enabled. + * | | |Note: Only useful when cipher is disabled. + * |[5] |B4ADDREN |4-byte Address Mode Enable Control + * | | |0 = 4-byte address mode is disabled, and 3-byte address mode is enabled. + * | | |1 = 4-byte address mode is enabled. + * | | |Note: Used for DMA write mode, DMA read mode, and DMM mode. + * |[6] |IEN |Interrupt Enable Control + * | | |0 = SPIM Interrupt Disabled. + * | | |1 = SPIM Interrupt Enabled. + * |[7] |IF |Interrupt Flag + * | | |(1) Write Operation : + * | | |0 = No effect. + * | | |1 = Write 1 to clear. + * | | |(2) Read Operation : + * | | |0 = The transfer has not finished yet. + * | | |1 = The transfer has done. + * |[12:8] |DWIDTH |Transmit/Receive Bit Length + * | | |This specifies how many bits are transmitted/received in one transmit/receive transaction. + * | | |0x7 = 8 bits. + * | | |0xF = 16 bits. + * | | |0x17 = 24 bits. + * | | |0x1F = 32 bits. + * | | |Others = Incorrect transfer result. + * | | |Note1: Only used for normal I/O mode. + * | | |Note2: Only 8, 16, 24, and 32 bits are allowed. Other bit length will result in incorrect transfer. + * |[14:13] |BURSTNUM |Transmit/Receive Burst Number + * | | |This field specifies how many transmit/receive transactions should be executed continuously in one transfer. + * | | |0x0 = Only one transmit/receive transaction will be executed in one transfer. + * | | |0x1 = Two successive transmit/receive transactions will be executed in one transfer. + * | | |0x2 = Three successive transmit/receive transactions will be executed in one transfer. + * | | |0x3 = Four successive transmit/receive transactions will be executed in one transfer. + * | | |Note: Only used for normal I/O Mode. + * |[15] |QDIODIR |SPI Interface Direction Select for Quad/Dual Mode + * | | |0 = Interface signals are input. + * | | |1 = Interface signals are output. + * | | |Note: Only used for normal I/O mode. + * |[19:16] |SUSPITV |Suspend Interval + * | | |These four bits provide the configuration of suspend interval between two successive transmit/receive transactions in a transfer + * | | |The default value is 0x00 + * | | |When BURSTNUM = 00, setting this field has no effect on transfer + * | | |The desired interval is obtained according to the following equation (from the last falling edge of current SPI clock to the first rising edge of next SPI clock): + * | | | (SUSPITV+2)*period of AHB clock + * | | | 0x0 = 2 AHB clock cycles. + * | | | 0x1 = 3 AHB clock cycles. + * | | | ...... + * | | | 0xE = 16 AHB clock cycles. + * | | | 0xF = 17 AHB clock cycles. + * | | | Note: Only used for normal I/O mode. + * |[21:20] |BITMODE |SPI Interface Bit Mode + * | | |0x0 = Standard mode. + * | | |0x1 = Dual mode. + * | | |0x2 = Quad mode. + * | | |0x3 = Reserved. + * | | |Note: Only used for normal I/O mode. + * |[23:22] |OPMODE |SPI Function Operation Mode + * | | |0x0 = Normal I/O mode. (Note1) (Note3) + * | | |0x1 = DMA write mode. (Note2) (Note3) + * | | |0x2 = DMA read mode. (Note3) + * | | |0x3 = Direct Memory Mapping mode (DMM mode) (Default). (Note4) + * | | |Note1 : After user uses Normal I/O mode of SPI flash controller to program the content of external SPI flash, please set CDINVAL(SPIM_CTL1[3]) to 0x1 (Set all cache data to be invalid). + * | | |Note2 : In DMA write mode, hardware will send just one page program command per operation + * | | |Users must take care of cross-page cases + * | | |After user uses DMA write mode of SPI flash controller to program the content of external SPI flash, please set CDINVAL(SPIM_CTL1[3]) to 0x1 (Set all cache data to be invalid). + * | | |Note3 : For external SPI flash with 32 MB, access address range of external SPI flash address is from 0x00000000 to 0x01FFFFFF when user uses Normal I/O mode, DMA write mode, and DMA read mode to write/read external SPI flash data + * | | |Please user check size of used SPI flash component to know access address range of external SPI flash. + * | | |Note4 : For external SPI flash with 32 MB, access address range of external SPI flash address is from 0x08000000 to 0x09FFFFFF when user uses Direct Memory mapping mode (DMM mode) to read external SPI flash data + * | | |Please user check size of used SPI flash component to know access address range of external SPI flash. + * |[31:24] |CMDCODE |Page Program Command Code (Note4) + * | | |(1) 0x02 = Page program (Used for DMA Write mode). + * | | |(2) 0x32 = Quad page program with TYPE_1 program flow (Used for DMA Write mode). (Note3) + * | | |(3) 0x38 = Quad page program with TYPE_2 program flow (Used for DMA Write mode). (Note3) + * | | |(4) 0x40 = Quad page program with TYPE_3 program flow (Used for DMA Write mode). (Note3) + * | | |The Others = Reserved. + * | | |Read Command Code : + * | | |(1) 0x03 = Standard Read (Used for DMA Read/DMM mode). + * | | |(2) 0x0B = Fast Read (Used for DMA Read/DMM mode). + * | | |The fast read command code "0x0B" is similar to command code of standard read "0x03" except it can operate at highest possible frequency + * | | |(Note2) + * | | |(3) 0x3B = Fast Read Dual Output (Used for DMA Read/DMM mode). + * | | |(4) 0xBB = Fast Read Dual I/O (Used for DMA Read/DMM mode). + * | | |The fast read dual I/O command code "0xBB" is similar to command code of fast read dual output "0x3B" but with capability to input the address bits two bits per clock + * | | |(Note2) + * | | |(5) 0xEB = Fast quad read (Used for DMA Read/DMM mode). + * | | |(6) 0xE7 = Word quad read (Used for DMA Read/DMM mode). + * | | |The command code of word quad read "0xE7" is similar to command code of fast quad read "0xEB" except that the lowest address bit must equal to 0 and the number of dummy cycles is less than fast quad read + * | | |(Note2) + * | | |(7) 0x0D = DTR/DDR Fast read (Used for DMA Read/DMM mode). + * | | |(8) 0xBD = DTR/DDR dual read (Used for DMA Read/DMM mode). + * | | |(9) 0xED = DTR/DDR quad read (Used for DMA Read/DMM mode). + * | | |The Others command codes are Reserved. + * | | |The DTR/DDR read commands "0x0D,0xBD,0xED" improves throughput by transferring address and data on both the falling and rising edge of SPI flash clock (SPIM_CLK) + * | | |It is similar to those commands "0x0B, 0xBB, 0xEB" but allows transfer of address and data on rising edge and falling edge of SPI flash output clock + * | | |(Note2) + * | | |Note1: Quad mode of SPI Flash must be enabled first by normal I/O mode before using quad page program/quad read commands. + * | | |Note2: See SPI flash specifications for support items. + * | | |Note3: For TYPE_1, TYPE_2, and TYPE_3 of page program command code, refer to Figure 7.19-3, Figure 7.19-4, and Figure 7.19-5. + * | | |Note4: Please disable "continuous read mode" and "burst wrap mode" before DMA write mode of SPI flash controller is used to program data of external SPI flash + * | | |After user uses DMA write mode of SPI flash controller to program the content of external SPI flash, please set CDINVAL(SPIM_CTL1[3]) to 0x1 (Set all cache data to be invalid). + * @var SPIM_T::CTL1 + * Offset: 0x04 Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SPIMEN |Go and Busy Status + * | | |(1) Write Operation : + * | | |0 = No effect. + * | | |1 = Start the transfer + * | | |This bit remains set during the transfer and is automatically cleared after transfer finished. + * | | |(2) Read Operation : + * | | |0 = The transfer has done. + * | | |1 = The transfer has not finished yet. + * | | |Note: All registers should be set before writing 1 to the SPIMEN bit + * | | |When a transfer is in progress, you should not write to any register of this peripheral. + * |[1] |CACHEOFF |Cache Memory Function Disable Control + * | | |0 = Cache memory function enable. (Default value) + * | | |1 = Cache memory function disable. + * | | |Note: When CCM mode is enabled, the cache function will be disable by hardware automatically + * | | |When CCM mode is disabled, the cache function can be enable or disable by user. + * |[2] |CCMEN |CCM (Core Coupled Memory) Mode Enable Control + * | | |0 = CCM mode disable. (Default value) + * | | |1 = CCM mode enable. + * | | |Note1: When CCM mode is enabled, the cache function will be disable by hardware automatically + * | | |When CCM mode is disabled, the cache function can be enabled or disabled by user. + * | | |Note2: When CCM mode is disabled, user accesses the core coupled memory by bus master + * | | |In this case, the SPI flash controller will send error response via HRESP bus signal to bus master. + * | | |Note3: When CCM mode needs to be enabled, user sets CCMEN to 1 and needs to read this register to show the current hardware status + * | | |When reading data of CCMEN is 1, MCU can start to read data from CCM memory space or write data to CCM memory space. + * |[3] |CDINVAL |Cache Data Invalid Enable Control + * | | |(1) Write Operation: + * | | |0 = No effect. + * | | |1 = Set all cache data to be invalid. This bit is cleared by hardware automatically. + * | | |(2) Read Operation : No effect + * | | |Note: When SPI flash memory is page erasing or whole flash erasing, please set CDINVAL to 0x1 + * | | |After user uses normal I/O mode or DMA write mode of SPI flash controller to program or erase the content of external SPI flash, please set CDINVAL to 0x1. + * |[4] |SS |Slave Select Active Enable Control + * | | |0 = SPIM_SS is in active level. + * | | |1 = SPIM_SS is in inactive level (Default). + * | | |Note: This interface can only drive one device/slave at a given time + * | | |Therefore, the slave selects of the selected device must be set to its active level before starting any read or write transfer + * | | |Functional description of SSACTPOL(SPIM_CTL1[5]) and SS is shown in Table 2. + * |[5] |SSACTPOL |Slave Select Active Level + * | | |It defines the active level of device/slave select signal (SPIM_SS), and we show in Table 2. + * | | |0 = The SPIM_SS slave select signal is active low. + * | | |1 = The SPIM_SS slave select signal is active high. + * |[11:8] |IDLETIME |Idle Time Interval + * | | |In DMM mode, IDLETIME is set to control the minimum idle time between two SPI Flash accesses. + * | | |Minimum idle time = (IDLETIME + 1) * AHB clock cycle time. + * | | |Note1: Only used for DMM mode. + * | | |Note2 : AHB clock cycle time = 1/AHB clock frequency. + * |[31:16] |DIVIDER |Clock Divider Register + * | | |The value in this field is the frequency divider of the AHB clock (HCLK) to generate the serial SPI output clock "SCLK" on the output SPIM_CLK pin + * | | |The desired frequency is obtained according to the following equation: + * | | |Note1: When set DIVIDER to zero, the frequency of SPIM_CLK will be equal to the frequency of HCLK. + * | | |Note2: SCLK is serial SPI output clock. + * | | |Note3: Please check the specification of the used SPI flash component to decide the frequency of SPI flash clock. + * | | |Note4: For DTR/DDR read commands "0x0D, 0xBD, 0xED", the setting values of DIVIDER are only 1,2,4,8,16,32,..., where n = 0,1,2,3,4, ... + * @var SPIM_T::RXCLKDLY + * Offset: 0x0C RX Clock Delay Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DWDELSEL |SPI flash deselect time interval of DMA write mode + * | | |For DMA write mode only + * | | |This register sets the deselect time interval of SPI flash (i.e. + * | | |time interval of inactive level of SPIM_SS) when SPI flash controller operates on DMA write mode + * | | |(Note1) + * | | |Deselect time interval of DMA write mode = (DWDELSEL + 1) * AHB clock cycle time (Note2). + * | | |Note1: Please user check the used external SPI flash component to set this register value + * | | |In general case, the deselect time interval of SPI flash is greater than 50 ns when SPI flash performs the program operation. + * | | |Note2: AHB clock cycle time = 1/AHB clock frequency. + * |[18:16] |RDDLYSEL |Sampling Clock Delay Selection for Received Data + * | | |For Normal I/O mode, DMA read mode, DMA write mode, and direct memory mapping mode + * | | |Determine the number of inserted delay cycles + * | | |Used to adjust the sampling clock of received data to latch the correct data. + * | | |0x0 : No delay. (Default Value) + * | | |0x1 : Delay 1 SPI flash clock. + * | | |0x2 : Delay 2 SPI flash clocks. + * | | |0x3 : Delay 3 SPI flash clocks. + * | | |... + * | | |0x7 : Delay 7 SPI flash clocks + * | | |Note : We can use manufacturer id or device id of external SPI flash component to determine the correct setting value of RDDLYSEL, and we give example as follows. + * | | |For example, manufacturer id and device id of external SPI flash for some vendor are 0xEF and 0x1234 separately + * | | |Firstly, we set RDDLYSEL to 0x0, and use read manufacturer id/device id command to read the manufacturer id of external SPI flash by using normal I/O mode (the manufacturer id is 0xEF (1110_1111) in this example). + * | | |If manufacturer id which reads from external SPI flash is 0xF7 (1111_0111), it denotes that manufacturer id is shifted the right by 1 bit and most significant bit (MSB) of manufacturer id is assigned to 1 + * | | |According to manufacturer id reads from external SPI flash, we need to set RDDLYSEL to 0x1 to receive SPI flash data correctly. + * |[20] |RDEDGE |Sampling Clock Edge Selection for Received Data + * | | |For Normal I/O mode, DMA read mode, DMA write mode, and direct memory mapping mode + * | | |0 : Use SPI input clock rising edge to sample received data. (Default Value) + * | | |1 : Use SPI input clock falling edge to sample received data. + * @var SPIM_T::RX[4] + * Offset: 0x10 ~ 0x1C Data Receive Register 0 ~ 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RXDAT |Data Receive Register + * | | |The Data Receive Registers hold the received data of the last executed transfer. + * | | |Number of valid RX registers is specified in SPIM_CTL0[BURSTNUM] + * | | |If BURSTNUM > 0, received data are held in the most significant RXDAT register first. + * | | |Number of valid-bit is specified in SPIM_CTL0[DWIDTH] + * | | |If DWIDTH is 16, 24, or 32, received data are held in the least significant byte of RXDAT register first. + * | | |In a byte, received data are held in the most significant bit of RXDAT register first. + * | | |Example 1: If SPIM_CTL0[BURSTNUM] = 0x3 and SPIM_CTL1[DWIDTH] = 0x17, received data will be held in the order SPIM_RX3[23:0], SPIM_RX2[23:0], SPIM_RX1[23:0], SPIM_RX0[23:0]. + * | | |Example 2: If SPIM_CTL0[BURSTNUM = 0x0 and SPIM_CTL0[DWIDTH] = 0x17, received data will be held in the order SPIM_RX0[7:0], SPIM_RX0[15:8], SPIM_RX0[23:16]. + * | | |Example 3: If SPIM_CTL0[BURSTNUM = 0x0 and SPIM_CTL0[DWIDTH] = 0x07, received data will be held in the order SPIM_RX0[7], SPIM_RX0[6], ..., + * | | |SPIM_RX0[0]. + * @var SPIM_T::TX[4] + * Offset: 0x20 ~ 0x2C Data Transmit Register 0 ~ 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TXDAT |Data Transmit Register + * | | |The Data Transmit Registers hold the data to be transmitted in next transfer. + * | | |Number of valid TXDAT registers is specified in SPIM_CTL0[BURSTNUM] + * | | |If BURSTNUM > 0, data are transmitted in the most significant TXDAT register first. + * | | |Number of valid-bit is specified in SPIM_CTL0[DWIDTH] + * | | |If DWIDTH is 16, 24, or 32, data are transmitted in the least significant byte of TXDAT register first. + * | | |In a byte, data are transmitted in the most significant bit of TXDAT register first. + * | | |Example 1: If SPIM_CTL0[BURSTNUM] = 0x3 and SPIM_CTL1[DWIDTH] = 0x17, data will be transmitted in the order SPIM_TX3[23:0], SPIM_TX2[23:0], SPIM_TX1[23:0], SPIM_TX0[23:0] in next transfer. + * | | |Example 2: If SPIM_CTL0[BURSTNUM] = 0x0 and SPIM_CTL0[DWIDTH] = 0x17, data will be transmitted in the order SPIM_TX0[7:0], SPIM_TX0[15:8], SPIM_TX0[23:16] in next transfer. + * | | |Example 3: If SPIM_CTL0[BURSTNUM] = 0x0 and SPIM_CTL0[DWIDTH] = 0x07, data will be transmitted in the order SPIM_TX0[7], SPIM_TX0[6], ..., + * | | |SPIM_TX0[0] in next transfer. + * @var SPIM_T::SRAMADDR + * Offset: 0x30 SRAM Memory Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ADDR |SRAM Memory Address + * | | |For DMA Read mode, this is the destination address for DMA transfer. + * | | |For DMA Write mode, this is the source address for DMA transfer. + * | | |Note: This address must be word-aligned. + * @var SPIM_T::DMACNT + * Offset: 0x34 DMA Transfer Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |DMACNT |DMA Transfer Byte Count Register + * | | |It indicates the transfer length for DMA process. + * | | |Note1: The unit for counting is byte. + * | | |Note2: The number must be the multiple of 4. + * | | |Note3: Please check specification of used SPI flash to know maximum byte length of page program. + * @var SPIM_T::FADDR + * Offset: 0x38 SPI Flash Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ADDR |SPI Flash Address Register + * | | |For DMA Read mode, this is the source address for DMA transfer. + * | | |For DMA Write mode, this is the destination address for DMA transfer. + * | | |Note 1 : This address must be word-aligned. + * | | |Note 2 : For external SPI flash with 32 MB, the value of this SPI flash address register "ADDR" is from 0x00000000 to 0x01FFFFFF when user uses DMA write mode and DMA read mode to write/read external SPI flash data + * | | |Please user check size of used SPI flash component to know access address range of external SPI flash. + * @var SPIM_T::KEY1 + * Offset: 0x3C Cipher Key1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY1 |Cipher Key1 Register + * | | |This is the KEY1 data for cipher function. + * | | |Note1: If there is not any KEY1(SPIM_KEY1[31:0]) or KEY2(SPIM_KEY2[31:0]) (KEY1 is 0x0000_0000 or KEY2 is 0x0000_0000), the cipher function will be disabled automatically. + * | | |Note2: When CIPHOFF(SPIM_CTL0[0]) is 0, both of KEY1(SPIM_KEY1[31:0]) and KEY2(SPIM_KEY2[31:0]) do not equal to 0x0000_0000 (i.e. + * | | |KEY1 != 0x0000_0000 and KEY2 != 0x0000_0000), cipher encryption/decryption is enabled. + * @var SPIM_T::KEY2 + * Offset: 0x40 Cipher Key2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY2 |Cipher Key2 Register + * | | |This is the KEY2 data for cipher function. + * | | |Note1: If there is not any KEY1(SPIM_KEY1[31:0]) or KEY2(SPIM_KEY2[31:0]) (KEY1 is 0x0000_0000 or KEY2 is 0x0000_0000), the cipher function will be disabled automatically. + * | | |Note2: When CIPHOFF(SPIM_CTL0[0]) is 0, both of KEY1(SPIM_KEY1[31:0]) and KEY2(SPIM_KEY2[31:0]) do not equal to 0x0000_0000 (i.e. + * | | |KEY1 != 0x0000_0000 and KEY2 != 0x0000_0000), cipher encryption/decryption is enabled. + * @var SPIM_T::DMMCTL + * Offset: 0x44 Direct Memory Mapping Mode Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:8] |CRMDAT |Mode bits data for Continuous Read Mode (or performance enhance mode) (Default value = 0) + * | | |Only for direct memory mapping mode + * | | |Set the mode bits data for continuous read mode (or performance enhance mode). + * | | |When we set this mode bits currently (Note1) and set CREN(SPIM_DMMCTL[25]), this reduces the command phase by eight clocks and allows the read address to be immediately entered after SPIM_SS asserted to active + * | | |(Note1) + * | | |Note1 : Please check the used SPI flash specification to know the setting value of this mode bits data, and different SPI flash vendor may use different setting values. + * | | |Note2 : CRMDAT needs to used with CREN(SPIM_DMMCTL[25]). + * |[20:16] |DESELTIM |SPI Flash Deselect Time + * | | |Only for direct memory mapping mode + * | | |Set the minimum time width of SPI flash deselect time (i.e. + * | | |Minimum SPIM_SS deselect time), and we show in Figure 7.19-8. + * | | |(1) Cache function disable : + * | | |Minimum time width of SPIM_SS deselect time = (DESELTIM + 1) * AHB clock cycle time. + * | | |(2) Cache function enable : + * | | |Minimum time width of SPIM_SS deselect time = (DESELTIM + 4) * AHB clock cycle time. + * | | |Note1 : AHB clock cycle time = 1/AHB clock frequency. + * | | |Note2 : When cipher encryption/decryption is enabled, please set this register value >= 0x10 + * | | |When cipher encryption/decryption is disabled, please set this register value >= 0x8. + * | | |Note3 : Please check the used SPI flash specification to know the setting value of this register, and different SPI flash vendor may use different setting values. + * |[24] |BWEN |16 bytes Burst Wrap Mode Enable Control Register (Default value = 0) + * | | |Only for WINBOND SPI flash, direct memory mapping mode, Cache enable, and read command code "0xEB, and 0xE7" + * | | |0 = Burst Wrap Mode Disable. (Default) + * | | |1 = Burst Wrap Mode Enable. + * | | |In direct memory mapping mode, both of quad read commands "0xEB" and "0xE7" support burst wrap mode for cache application and performance enhance + * | | |For cache application, the burst wrap mode can be used to fill the cache line quickly (In this SPI flash controller, we use cache data line with 16 bytes size) + * | | |For performance enhance with direct memory mapping mode and cache enable, when cache data is miss, the burst wrap mode can let MCU get the required SPI flash data quickly. + * |[25] |CREN |Continuous Read Mode Enable Control + * | | |Only for direct memory mapping mode, read command codes 0xBB, 0xEB, 0xE7, 0x0D, 0xBD, 0xED (Note2) + * | | |0 = Continuous Read Mode Disable. (Default) + * | | |1 = Continuous Read Mode Enable. + * | | |For read operations of SPI flash, commands of fast read quad I/O (0xEB), word read quad I/O (0xE7 in Winbond SPI flash), fast read dual I/O (0xBB), DTR/DDR fast read (0x0D), DTR/DDR fast read dual I/O (0xBD), and DTR/DDR fast read quad I/O (0xED) can further reduce command overhead through setting the "continuous read mode" bits (8 bits) after the input address data. + * | | |Note: When user uses function of continuous read mode and sets USETEN (SPIM_CTL2[16]) to 1, CRMDAT(SPIM_DMMCTL[15:8]) must be set by used SPI flash specifications + * | | |When user uses function of continuous read mode and sets USETEN(SPIM_CTL2[16]) to 0, CRMDAT(SPIM_DMMCTL[15:8]) is set by default value of WINBOND SPI flash. + * |[26] |UACTSCLK |User Sets SPI Flash Active SCLK Time + * | | |Only for direct memory mapping mode, DMA write mode, and DMA read mode + * | | |0 = According to DIVIDER(SPIM_CTL1[31:16]), ACTSCLKT(SPIM_DMMCTL[31:28]) is set by hardware automatically + * | | |(Default value) + * | | |1 = Set ACTSCLKT(SPIM_DMMCTL[31:28]) by user manually. + * | | |When user wants to set ACTSCLKT(SPIM_DMMCTL[31:28]) manually, please set UACTSCLK to 1. + * |[31:28] |ACTSCLKT |SPI Flash Active SCLK Time + * | | |Only for direct memory mapping mode, DMA write mode, and DMA read mode + * | | |This register sets time interval between SPIM SS active edge and the position edge of the first serial SPI output clock, and we show in Figure 7.19-8. + * | | |(1) ACTSCLKT = 0 (function disable) :. + * | | |Time interval = 1 AHB clock cycle time. + * | | |(2) ACTSCLKT != 0 (function enable) : + * | | |Time interval = (ACTSCLKT + 3) * AHB clock cycle time. + * | | |Note1 : AHB clock cycle time = 1/AHB clock frequency. + * | | |Note2 : SCLK is SPI output clock + * | | |Note3 : Please check the used SPI flash specification to know the setting value of this register, and different SPI flash vendor may use different setting values. + * @var SPIM_T::CTL2 + * Offset: 0x48 Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[16] |USETEN |User Set Value Enable Control + * | | |Only for direct memory mapping mode and DMA read mode with read commands 0x03,0x0B,0x3B,0xBB,0xEB,0xE7 + * | | |0 = Hardware circuit of SPI flash controller will use the following default values of DCNUM(SPIM_CTL2[28:24]) and CRMDAT(SPIM_DMMCTL[15:8]) to configure SPI flash operations automatically. + * | | |Dummy cycle number (DCNUM) : + * | | |Dummy cycle number for read command 0x03 : 0x0 + * | | |Dummy cycle number for read command 0x0B : 0x8 + * | | |Dummy cycle number for read command 0x3B : 0x8 + * | | |Dummy cycle number for read command 0xBB : 0x0 + * | | |Dummy cycle number for read command 0xEB : 0x4 + * | | |Dummy cycle number for read command 0xE7 : 0x2 + * | | |Mode bits data for continuous read mode (CRMDAT) : 0x20 + * | | |1 = If DCNUM(SPIM_CTL2[28:24]) and CRMDAT(SPIM_DMMCTL[15:8]) are not set as above default values, user must set USETEN to 0x1, DCNUM(SPIM_CTL2[28:24]) and CRMDAT(SPIM_DMMCTL[15:8]) to configure SPI flash operations manually. + * | | |For DTR/DDR command codes 0x0D, 0xBD, and 0xED, please set USETEN to 0x1. + * |[20] |DTRMPOFF |Mode Phase OFF for DTR/DDR Command Codes 0x0D, 0xBD, and 0xED + * | | |Only for direct memory mapping mode and DMA read mode (Note1) + * | | |0 = mode cycle number (or performance enhance cycle number) does not equal to 0x0 in DTR/DDR read command codes 0x0D, 0xBD, and 0xED. + * | | |1 = mode cycle number (or performance enhance cycle number) equals to 0x0 in DTR/DDR read command codes 0x0D, 0xBD, and 0xED. + * | | |Note1 : Please check the used SPI flash specification to know the mode cycle number (or performance enhance cycle number) for DTR/DDR command codes 0x0D, 0xBD, and 0xED. + * |[28:24] |DCNUM |Dummy Cycle Number + * | | |Only for direct memory mapping mode and DMA read mode (Note1) + * | | |Set number of dummy cycles + * | | |(1) For non-DTR/non-DDR command codes 0x03, 0x0B, 0x3B, 0xBB, 0xEB, and 0xE7 : + * | | |When read command code do not need any dummy cycles (i.e. + * | | |dummy cycle number = 0x0), user must set DCNUM to 0x0. + * | | |For command code 0xBB, if both mode cycle number (or performance enhance cycle number) and dummy cycle number do not equal to 0x0 simultaneously, user must set DCNUM to "mode cycle number + dummy cycle number" by used SPI flash specification. + * | | |For command code 0xBB, if there is only dummy cycle number (i.e. + * | | |dummy cycle number != 0x0 and mode cycle number = 0x0 (or performance enhance cycle number = 0x0)), user set DCNUM to dummy cycle number by used SPI flash specification. + * | | |For command codes 0x0B, 0x3B, 0xEB, and 0xE7, user only set DCNUM to dummy cycle number by used SPI flash specification. + * | | |(2) For DTR/DDR command codes 0x0D, 0xBD, and 0xED : + * | | |user sets DCNUM to dummy cycle number and DTRMPOFF(SPIM_CTL2[20]) by used SPI flash specification. + * | | |Note1 : Number of dummy cycles depends on the frequency of SPI output clock, SPI flash vendor, and read command types + * | | |Please check the used SPI flash specification to know the setting value of this number of dummy cycles. + */ + __IO uint32_t CTL0; /*!< [0x0000] Control and Status Register 0 */ + __IO uint32_t CTL1; /*!< [0x0004] Control Register 1 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t RXCLKDLY; /*!< [0x000c] RX Clock Delay Control Register */ + __I uint32_t RX[4]; /*!< [0x0010] ~ [0x001C] Data Receive Register 0~3 */ + __IO uint32_t TX[4]; /*!< [0x0020] ~ [0x002C] Data Transmit Register 0~3 */ + __IO uint32_t SRAMADDR; /*!< [0x0030] SRAM Memory Address Register */ + __IO uint32_t DMACNT; /*!< [0x0034] DMA Transfer Byte Count Register */ + __IO uint32_t FADDR; /*!< [0x0038] SPI Flash Address Register */ + __O uint32_t KEY1; /*!< [0x003c] Cipher Key1 Register */ + __O uint32_t KEY2; /*!< [0x0040] Cipher Key2 Register */ + __IO uint32_t DMMCTL; /*!< [0x0044] Direct Memory Mapping Mode Control Register */ + __IO uint32_t CTL2; /*!< [0x0048] Control Register 2 */ + +} SPIM_T; + +/** + @addtogroup SPIM_CONST SPIM Bit Field Definition + Constant Definitions for SPIM Controller +@{ */ + +#define SPIM_CTL0_CIPHOFF_Pos (0) /*!< SPIM_T::CTL0: CIPHOFF Position */ +#define SPIM_CTL0_CIPHOFF_Msk (0x1ul << SPIM_CTL0_CIPHOFF_Pos) /*!< SPIM_T::CTL0: CIPHOFF Mask */ + +#define SPIM_CTL0_BALEN_Pos (2) /*!< SPIM_T::CTL0: BALEN Position */ +#define SPIM_CTL0_BALEN_Msk (0x1ul << SPIM_CTL0_BALEN_Pos) /*!< SPIM_T::CTL0: BALEN Mask */ + +#define SPIM_CTL0_B4ADDREN_Pos (5) /*!< SPIM_T::CTL0: B4ADDREN Position */ +#define SPIM_CTL0_B4ADDREN_Msk (0x1ul << SPIM_CTL0_B4ADDREN_Pos) /*!< SPIM_T::CTL0: B4ADDREN Mask */ + +#define SPIM_CTL0_IEN_Pos (6) /*!< SPIM_T::CTL0: IEN Position */ +#define SPIM_CTL0_IEN_Msk (0x1ul << SPIM_CTL0_IEN_Pos) /*!< SPIM_T::CTL0: IEN Mask */ + +#define SPIM_CTL0_IF_Pos (7) /*!< SPIM_T::CTL0: IF Position */ +#define SPIM_CTL0_IF_Msk (0x1ul << SPIM_CTL0_IF_Pos) /*!< SPIM_T::CTL0: IF Mask */ + +#define SPIM_CTL0_DWIDTH_Pos (8) /*!< SPIM_T::CTL0: DWIDTH Position */ +#define SPIM_CTL0_DWIDTH_Msk (0x1ful << SPIM_CTL0_DWIDTH_Pos) /*!< SPIM_T::CTL0: DWIDTH Mask */ + +#define SPIM_CTL0_BURSTNUM_Pos (13) /*!< SPIM_T::CTL0: BURSTNUM Position */ +#define SPIM_CTL0_BURSTNUM_Msk (0x3ul << SPIM_CTL0_BURSTNUM_Pos) /*!< SPIM_T::CTL0: BURSTNUM Mask */ + +#define SPIM_CTL0_QDIODIR_Pos (15) /*!< SPIM_T::CTL0: QDIODIR Position */ +#define SPIM_CTL0_QDIODIR_Msk (0x1ul << SPIM_CTL0_QDIODIR_Pos) /*!< SPIM_T::CTL0: QDIODIR Mask */ + +#define SPIM_CTL0_SUSPITV_Pos (16) /*!< SPIM_T::CTL0: SUSPITV Position */ +#define SPIM_CTL0_SUSPITV_Msk (0xful << SPIM_CTL0_SUSPITV_Pos) /*!< SPIM_T::CTL0: SUSPITV Mask */ + +#define SPIM_CTL0_BITMODE_Pos (20) /*!< SPIM_T::CTL0: BITMODE Position */ +#define SPIM_CTL0_BITMODE_Msk (0x3ul << SPIM_CTL0_BITMODE_Pos) /*!< SPIM_T::CTL0: BITMODE Mask */ + +#define SPIM_CTL0_OPMODE_Pos (22) /*!< SPIM_T::CTL0: OPMODE Position */ +#define SPIM_CTL0_OPMODE_Msk (0x3ul << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_T::CTL0: OPMODE Mask */ + +#define SPIM_CTL0_CMDCODE_Pos (24) /*!< SPIM_T::CTL0: CMDCODE Position */ +#define SPIM_CTL0_CMDCODE_Msk (0xfful << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_T::CTL0: CMDCODE Mask */ + +#define SPIM_CTL1_SPIMEN_Pos (0) /*!< SPIM_T::CTL1: SPIMEN Position */ +#define SPIM_CTL1_SPIMEN_Msk (0x1ul << SPIM_CTL1_SPIMEN_Pos) /*!< SPIM_T::CTL1: SPIMEN Mask */ + +#define SPIM_CTL1_CACHEOFF_Pos (1) /*!< SPIM_T::CTL1: CACHEOFF Position */ +#define SPIM_CTL1_CACHEOFF_Msk (0x1ul << SPIM_CTL1_CACHEOFF_Pos) /*!< SPIM_T::CTL1: CACHEOFF Mask */ + +#define SPIM_CTL1_CCMEN_Pos (2) /*!< SPIM_T::CTL1: CCMEN Position */ +#define SPIM_CTL1_CCMEN_Msk (0x1ul << SPIM_CTL1_CCMEN_Pos) /*!< SPIM_T::CTL1: CCMEN Mask */ + +#define SPIM_CTL1_CDINVAL_Pos (3) /*!< SPIM_T::CTL1: CDINVAL Position */ +#define SPIM_CTL1_CDINVAL_Msk (0x1ul << SPIM_CTL1_CDINVAL_Pos) /*!< SPIM_T::CTL1: CDINVAL Mask */ + +#define SPIM_CTL1_SS_Pos (4) /*!< SPIM_T::CTL1: SS Position */ +#define SPIM_CTL1_SS_Msk (0x1ul << SPIM_CTL1_SS_Pos) /*!< SPIM_T::CTL1: SS Mask */ + +#define SPIM_CTL1_SSACTPOL_Pos (5) /*!< SPIM_T::CTL1: SSACTPOL Position */ +#define SPIM_CTL1_SSACTPOL_Msk (0x1ul << SPIM_CTL1_SSACTPOL_Pos) /*!< SPIM_T::CTL1: SSACTPOL Mask */ + +#define SPIM_CTL1_IDLETIME_Pos (8) /*!< SPIM_T::CTL1: IDLETIME Position */ +#define SPIM_CTL1_IDLETIME_Msk (0xful << SPIM_CTL1_IDLETIME_Pos) /*!< SPIM_T::CTL1: IDLETIME Mask */ + +#define SPIM_CTL1_DIVIDER_Pos (16) /*!< SPIM_T::CTL1: DIVIDER Position */ +#define SPIM_CTL1_DIVIDER_Msk (0xfffful << SPIM_CTL1_DIVIDER_Pos) /*!< SPIM_T::CTL1: DIVIDER Mask */ + +#define SPIM_RXCLKDLY_DWDELSEL_Pos (0) /*!< SPIM_T::RXCLKDLY: DWDELSEL Position */ +#define SPIM_RXCLKDLY_DWDELSEL_Msk (0xfful << SPIM_RXCLKDLY_DWDELSEL_Pos) /*!< SPIM_T::RXCLKDLY: DWDELSEL Mask */ + +#define SPIM_RXCLKDLY_RDDLYSEL_Pos (16) /*!< SPIM_T::RXCLKDLY: RDDLYSEL Position */ +#define SPIM_RXCLKDLY_RDDLYSEL_Msk (0x7ul << SPIM_RXCLKDLY_RDDLYSEL_Pos) /*!< SPIM_T::RXCLKDLY: RDDLYSEL Mask */ + +#define SPIM_RXCLKDLY_RDEDGE_Pos (20) /*!< SPIM_T::RXCLKDLY: RDEDGE Position */ +#define SPIM_RXCLKDLY_RDEDGE_Msk (0x1ul << SPIM_RXCLKDLY_RDEDGE_Pos) /*!< SPIM_T::RXCLKDLY: RDEDGE Mask */ + +#define SPIM_RX_RXDAT_Pos (0) /*!< SPIM_T::RX[4]: RXDAT Position */ +#define SPIM_RX_RXDAT_Msk (0xfffffffful << SPIM_RX_RXDAT_Pos) /*!< SPIM_T::RX[4]: RXDAT Mask */ + +#define SPIM_TX_TXDAT_Pos (0) /*!< SPIM_T::TX[4]: TXDAT Position */ +#define SPIM_TX_TXDAT_Msk (0xfffffffful << SPIM_TX_TXDAT_Pos) /*!< SPIM_T::TX[4]: TXDAT Mask */ + +#define SPIM_SRAMADDR_ADDR_Pos (0) /*!< SPIM_T::SRAMADDR: ADDR Position */ +#define SPIM_SRAMADDR_ADDR_Msk (0xfffffffful << SPIM_SRAMADDR_ADDR_Pos) /*!< SPIM_T::SRAMADDR: ADDR Mask */ + +#define SPIM_DMACNT_DMACNT_Pos (0) /*!< SPIM_T::DMACNT: DMACNT Position */ +#define SPIM_DMACNT_DMACNT_Msk (0xfffffful << SPIM_DMACNT_DMACNT_Pos) /*!< SPIM_T::DMACNT: DMACNT Mask */ + +#define SPIM_FADDR_ADDR_Pos (0) /*!< SPIM_T::FADDR: ADDR Position */ +#define SPIM_FADDR_ADDR_Msk (0xfffffffful << SPIM_FADDR_ADDR_Pos) /*!< SPIM_T::FADDR: ADDR Mask */ + +#define SPIM_KEY1_KEY1_Pos (0) /*!< SPIM_T::KEY1: KEY1 Position */ +#define SPIM_KEY1_KEY1_Msk (0xfffffffful << SPIM_KEY1_KEY1_Pos) /*!< SPIM_T::KEY1: KEY1 Mask */ + +#define SPIM_KEY2_KEY2_Pos (0) /*!< SPIM_T::KEY2: KEY2 Position */ +#define SPIM_KEY2_KEY2_Msk (0xfffffffful << SPIM_KEY2_KEY2_Pos) /*!< SPIM_T::KEY2: KEY2 Mask */ + +#define SPIM_DMMCTL_CRMDAT_Pos (8) /*!< SPIM_T::DMMCTL: CRMDAT Position */ +#define SPIM_DMMCTL_CRMDAT_Msk (0xfful << SPIM_DMMCTL_CRMDAT_Pos) /*!< SPIM_T::DMMCTL: CRMDAT Mask */ + +#define SPIM_DMMCTL_DESELTIM_Pos (16) /*!< SPIM_T::DMMCTL: DESELTIM Position */ +#define SPIM_DMMCTL_DESELTIM_Msk (0x1ful << SPIM_DMMCTL_DESELTIM_Pos) /*!< SPIM_T::DMMCTL: DESELTIM Mask */ + +#define SPIM_DMMCTL_BWEN_Pos (24) /*!< SPIM_T::DMMCTL: BWEN Position */ +#define SPIM_DMMCTL_BWEN_Msk (0x1ul << SPIM_DMMCTL_BWEN_Pos) /*!< SPIM_T::DMMCTL: BWEN Mask */ + +#define SPIM_DMMCTL_CREN_Pos (25) /*!< SPIM_T::DMMCTL: CREN Position */ +#define SPIM_DMMCTL_CREN_Msk (0x1ul << SPIM_DMMCTL_CREN_Pos) /*!< SPIM_T::DMMCTL: CREN Mask */ + +#define SPIM_DMMCTL_UACTSCLK_Pos (26) /*!< SPIM_T::DMMCTL: UACTSCLK Position */ +#define SPIM_DMMCTL_UACTSCLK_Msk (0x1ul << SPIM_DMMCTL_UACTSCLK_Pos) /*!< SPIM_T::DMMCTL: UACTSCLK Mask */ + +#define SPIM_DMMCTL_ACTSCLKT_Pos (28) /*!< SPIM_T::DMMCTL: ACTSCLKT Position */ +#define SPIM_DMMCTL_ACTSCLKT_Msk (0xful << SPIM_DMMCTL_ACTSCLKT_Pos) /*!< SPIM_T::DMMCTL: ACTSCLKT Mask */ + +#define SPIM_CTL2_USETEN_Pos (16) /*!< SPIM_T::CTL2: USETEN Position */ +#define SPIM_CTL2_USETEN_Msk (0x1ul << SPIM_CTL2_USETEN_Pos) /*!< SPIM_T::CTL2: USETEN Mask */ + +#define SPIM_CTL2_DTRMPOFF_Pos (20) /*!< SPIM_T::CTL2: DTRMPOFF Position */ +#define SPIM_CTL2_DTRMPOFF_Msk (0x1ul << SPIM_CTL2_DTRMPOFF_Pos) /*!< SPIM_T::CTL2: DTRMPOFF Mask */ + +#define SPIM_CTL2_DCNUM_Pos (24) /*!< SPIM_T::CTL2: DCNUM Position */ +#define SPIM_CTL2_DCNUM_Msk (0x1ful << SPIM_CTL2_DCNUM_Pos) /*!< SPIM_T::CTL2: DCNUM Mask */ + +/**@}*/ /* SPIM_CONST */ +/**@}*/ /* end of SPIM register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __SPIM_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/sys_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/sys_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..2bf3288d245af3ce4f8ed6fdf3643a264642e552 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/sys_reg.h @@ -0,0 +1,3662 @@ +/**************************************************************************//** + * @file sys_reg.h + * @version V1.00 + * @brief SYS register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SYS_REG_H__ +#define __SYS_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup SYS System Manger Controller(SYS) + Memory Mapped Structure for SYS Controller +@{ */ + +typedef struct +{ + + + /** + * @var SYS_T::PDID + * Offset: 0x00 Part Device Identification Number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PDID |Part Device Identification Number (Read Only) + * | | |This register reflects device part number code + * | | |Software can read this register to identify which device is used. + * @var SYS_T::RSTSTS + * Offset: 0x04 System Reset Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PORF |POR Reset Flag + * | | |The POR reset flag is set by the "Reset Signal" from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source. + * | | |0 = No reset from POR or CHIPRST. + * | | |1 = Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system. + * | | |Note: Write 1 to clear this bit to 0. + * |[1] |PINRF |NRESET Pin Reset Flag + * | | |The nRESET pin reset flag is set by the "Reset Signal" from the nRESET Pin to indicate the previous reset source. + * | | |0 = No reset from nRESET pin. + * | | |1 = Pin nRESET had issued the reset signal to reset the system. + * | | |Note: Write 1 to clear this bit to 0. + * |[2] |WDTRF |WDT Reset Flag + * | | |The WDT reset flag is set by the "Reset Signal" from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source. + * | | |0 = No reset from watchdog timer or window watchdog timer. + * | | |1 = The watchdog timer or window watchdog timer had issued the reset signal to reset the system. + * | | |Note1: Write 1 to clear this bit to 0. + * | | |Note2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset + * | | |Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset. + * |[3] |LVRF |LVR Reset Flag + * | | |The LVR reset flag is set by the "Reset Signal" from the Low Voltage Reset Controller to indicate the previous reset source. + * | | |0 = No reset from LVR. + * | | |1 = LVR controller had issued the reset signal to reset the system. + * | | |Note: Write 1 to clear this bit to 0. + * |[4] |BODRF |BOD Reset Flag + * | | |The BOD reset flag is set by the "Reset Signal" from the Brown-Out Detector to indicate the previous reset source. + * | | |0 = No reset from BOD. + * | | |1 = The BOD had issued the reset signal to reset the system. + * | | |Note: Write 1 to clear this bit to 0. + * |[5] |SYSRF |System Reset Flag + * | | |The system reset flag is set by the "Reset Signal" from the Cortex-M4 Core to indicate the previous reset source. + * | | |0 = No reset from Cortex-M4. + * | | |1 = The Cortex-M4 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M4 core. + * | | |Note: Write 1 to clear this bit to 0. + * |[7] |CPURF |CPU Reset Flag + * | | |The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M4 Core and Flash Memory Controller (FMC). + * | | |0 = No reset from CPU. + * | | |1 = The Cortex-M4 Core and FMC are reset by software setting CPURST to 1. + * | | |Note: Write to clear this bit to 0. + * |[8] |CPULKRF |CPU Lock-up Reset Flag + * | | |0 = No reset from CPU lock-up happened. + * | | |1 = The Cortex-M4 lock-up happened and chip is reset. + * | | |Note: Write 1 to clear this bit to 0. + * | | |Note2: When CPU lock-up happened under ICE is connected, This flag will set to 1 but chip will not reset. + * @var SYS_T::IPRST0 + * Offset: 0x08 Peripheral Reset Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CHIPRST |Chip One-shot Reset (Write Protect) + * | | |Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. + * | | |The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload. + * | | |About the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 6.2.2 + * | | |0 = Chip normal operation. + * | | |1 = Chip one-shot reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[1] |CPURST |Processor Core One-shot Reset (Write Protect) + * | | |Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles. + * | | |0 = Processor core normal operation. + * | | |1 = Processor core one-shot reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[2] |PDMARST |PDMA Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the PDMA + * | | |User needs to set this bit to 0 to release from reset state. + * | | |0 = PDMA controller normal operation. + * | | |1 = PDMA controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |EBIRST |EBI Controller Reset (Write Protect) + * | | |Set this bit to 1 will generate a reset signal to the EBI + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = EBI controller normal operation. + * | | |1 = EBI controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[5] |EMACRST |EMAC Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the EMAC controller + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = EMAC controller normal operation. + * | | |1 = EMAC controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[6] |SDH0RST |SDHOST0 Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the SDHOST0 controller + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = SDHOST0 controller normal operation. + * | | |1 = SDHOST0 controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7] |CRCRST |CRC Calculation Controller Reset (Write Protect) + * | | |Set this bit to 1 will generate a reset signal to the CRC calculation controller + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = CRC calculation controller normal operation. + * | | |1 = CRC calculation controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[8] |CCAPRST |CCAP Controller Reset (Write Protect) + * | | |Set this bit to 1 will generate a reset signal to the CCAP controller. + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = CCAP controller normal operation. + * | | |1 = CCAP controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[10] |HSUSBDRST |HSUSBD Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the HSUSBD controller + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = HSUSBD controller normal operation. + * | | |1 = HSUSBD controller reset. + * |[12] |CRPTRST |CRYPTO Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the CRYPTO controller + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = CRYPTO controller normal operation. + * | | |1 = CRYPTO controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[14] |SPIMRST |SPIM Controller Reset + * | | |Setting this bit to 1 will generate a reset signal to the SPIM controller + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = SPIM controller normal operation. + * | | |1 = SPIM controller reset. + * |[16] |USBHRST |USBH Controller Reset (Write Protect) + * | | |Set this bit to 1 will generate a reset signal to the USBH controller + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = USBH controller normal operation. + * | | |1 = USBH controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[17] |SDH1RST |SDHOST1 Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the SDHOST1 controller + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = SDHOST1 controller normal operation. + * | | |1 = SDHOST1 controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var SYS_T::IPRST1 + * Offset: 0x0C Peripheral Reset Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |GPIORST |GPIO Controller Reset + * | | |0 = GPIO controller normal operation. + * | | |1 = GPIO controller reset. + * |[2] |TMR0RST |Timer0 Controller Reset + * | | |0 = Timer0 controller normal operation. + * | | |1 = Timer0 controller reset. + * |[3] |TMR1RST |Timer1 Controller Reset + * | | |0 = Timer1 controller normal operation. + * | | |1 = Timer1 controller reset. + * |[4] |TMR2RST |Timer2 Controller Reset + * | | |0 = Timer2 controller normal operation. + * | | |1 = Timer2 controller reset. + * |[5] |TMR3RST |Timer3 Controller Reset + * | | |0 = Timer3 controller normal operation. + * | | |1 = Timer3 controller reset. + * |[7] |ACMP01RST |Analog Comparator 0/1 Controller Reset + * | | |0 = Analog Comparator 0/1 controller normal operation. + * | | |1 = Analog Comparator 0/1 controller reset. + * |[8] |I2C0RST |I2C0 Controller Reset + * | | |0 = I2C0 controller normal operation. + * | | |1 = I2C0 controller reset. + * |[9] |I2C1RST |I2C1 Controller Reset + * | | |0 = I2C1 controller normal operation. + * | | |1 = I2C1 controller reset. + * |[10] |I2C2RST |I2C2 Controller Reset + * | | |0 = I2C2 controller normal operation. + * | | |1 = I2C2 controller reset. + * |[12] |QSPI0RST |QSPI0 Controller Reset + * | | |0 = QSPI0 controller normal operation. + * | | |1 = QSPI0 controller reset. + * |[13] |SPI0RST |SPI0 Controller Reset + * | | |0 = SPI0 controller normal operation. + * | | |1 = SPI0 controller reset. + * |[14] |SPI1RST |SPI1 Controller Reset + * | | |0 = SPI1 controller normal operation. + * | | |1 = SPI1 controller reset. + * |[15] |SPI2RST |SPI2 Controller Reset + * | | |0 = SPI2 controller normal operation. + * | | |1 = SPI2 controller reset. + * |[16] |UART0RST |UART0 Controller Reset + * | | |0 = UART0 controller normal operation. + * | | |1 = UART0 controller reset. + * |[17] |UART1RST |UART1 Controller Reset + * | | |0 = UART1 controller normal operation. + * | | |1 = UART1 controller reset. + * |[18] |UART2RST |UART2 Controller Reset + * | | |0 = UART2 controller normal operation. + * | | |1 = UART2 controller reset. + * |[19] |UART3RST |UART3 Controller Reset + * | | |0 = UART3 controller normal operation. + * | | |1 = UART3 controller reset. + * |[20] |UART4RST |UART4 Controller Reset + * | | |0 = UART4 controller normal operation. + * | | |1 = UART4 controller reset. + * |[21] |UART5RST |UART5 Controller Reset + * | | |0 = UART5 controller normal operation. + * | | |1 = UART5 controller reset. + * |[24] |CAN0RST |CAN0 Controller Reset + * | | |0 = CAN0 controller normal operation. + * | | |1 = CAN0 controller reset. + * |[25] |CAN1RST |CAN1 Controller Reset + * | | |0 = CAN1 controller normal operation. + * | | |1 = CAN1 controller reset. + * |[27] |USBDRST |USBD Controller Reset + * | | |0 = USBD controller normal operation. + * | | |1 = USBD controller reset. + * |[28] |EADCRST |EADC Controller Reset + * | | |0 = EADC controller normal operation. + * | | |1 = EADC controller reset. + * |[29] |I2S0RST |I2S0 Controller Reset + * | | |0 = I2S0 controller normal operation. + * | | |1 = I2S0 controller reset. + * @var SYS_T::IPRST2 + * Offset: 0x10 Peripheral Reset Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SC0RST |SC0 Controller Reset + * | | |0 = SC0 controller normal operation. + * | | |1 = SC0 controller reset. + * |[1] |SC1RST |SC1 Controller Reset + * | | |0 = SC1 controller normal operation. + * | | |1 = SC1 controller reset. + * |[2] |SC2RST |SC2 Controller Reset + * | | |0 = SC2 controller normal operation. + * | | |1 = SC2 controller reset. + * |[6] |SPI3RST |SPI3 Controller Reset + * | | |0 = SPI3 controller normal operation. + * | | |1 = SPI3 controller reset. + * |[8] |USCI0RST |USCI0 Controller Reset + * | | |0 = USCI0 controller normal operation. + * | | |1 = USCI0 controller reset. + * |[9] |USCI1RST |USCI1 Controller Reset + * | | |0 = USCI1 controller normal operation. + * | | |1 = USCI1 controller reset. + * |[12] |DACRST |DAC Controller Reset + * | | |0 = DAC controller normal operation. + * | | |1 = DAC controller reset. + * |[16] |EPWM0RST |EPWM0 Controller Reset + * | | |0 = EPWM0 controller normal operation. + * | | |1 = EPWM0 controller reset. + * |[17] |EPWM1RST |EPWM1 Controller Reset + * | | |0 = EPWM1 controller normal operation. + * | | |1 = EPWM1 controller reset. + * |[18] |BPWM0RST |BPWM0 Controller Reset + * | | |0 = BPWM0 controller normal operation. + * | | |1 = BPWM0 controller reset. + * |[19] |BPWM1RST |BPWM1 Controller Reset + * | | |0 = BPWM1 controller normal operation. + * | | |1 = BPWM1 controller reset. + * |[22] |QEI0RST |QEI0 Controller Reset + * | | |0 = QEI0 controller normal operation. + * | | |1 = QEI0 controller reset. + * |[23] |QEI1RST |QEI1 Controller Reset + * | | |0 = QEI1 controller normal operation. + * | | |1 = QEI1 controller reset. + * |[26] |ECAP0RST |ECAP0 Controller Reset + * | | |0 = ECAP0 controller normal operation. + * | | |1 = ECAP0 controller reset. + * |[27] |ECAP1RST |ECAP1 Controller Reset + * | | |0 = ECAP1 controller normal operation. + * | | |1 = ECAP1 controller reset. + * |[28] |CAN2RST |CAN2 Controller Reset + * | | |0 = CAN2 controller normal operation. + * | | |1 = CAN2 controller reset. + * |[30] |OPARST |OP Amplifier (OPA) Controller Reset + * | | |0 = OPA controller normal operation. + * | | |1 = OPA controller reset. + * @var SYS_T::BODCTL + * Offset: 0x18 Brown-Out Detector Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BODEN |Brown-out Detector Enable Bit (Write Protect) + * | | |The default value is set by flash controller user configuration register CBODEN(CONFIG0 [19]). + * | | |0 = Brown-out Detector function Disabled. + * | | |1 = Brown-out Detector function Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |BODRSTEN |Brown-out Reset Enable Bit (Write Protect) + * | | |The default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit . + * | | |0 = Brown-out INTERRUPT function Enabled. + * | | |1 = Brown-out RESET function Enabled. + * | | |Note1: + * | | |While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high). + * | | |While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high + * | | |BOD interrupt will keep till to the BODEN set to 0 + * | | |BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low). + * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[4] |BODIF |Brown-out Detector Interrupt Flag + * | | |0 = Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting. + * | | |1 = When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled. + * | | |Note: Write 1 to clear this bit to 0. + * |[5] |BODLPM |Brown-out Detector Low Power Mode (Write Protect) + * | | |0 = BOD operate in normal mode (default). + * | | |1 = BOD Low Power mode Enabled. + * | | |Note1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response. + * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[6] |BODOUT |Brown-out Detector Output Status + * | | |0 = Brown-out Detector output status is 0. + * | | |It means the detected voltage is higher than BODVL setting or BODEN is 0. + * | | |1 = Brown-out Detector output status is 1. + * | | |It means the detected voltage is lower than BODVL setting + * | | |If the BODEN is 0, BOD function disabled , this bit always responds 0000. + * |[7] |LVREN |Low Voltage Reset Enable Bit (Write Protect) + * | | |The LVR function resets the chip when the input power voltage is lower than LVR circuit setting + * | | |LVR function is enabled by default. + * | | |0 = Low Voltage Reset function Disabled. + * | | |1 = Low Voltage Reset function Enabled. + * | | |Note1: After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default). + * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[10:8] |BODDGSEL |Brown-out Detector Output De-glitch Time Select (Write Protect) + * | | |000 = BOD output is sampled by RC10K clock. + * | | |001 = 4 system clock (HCLK). + * | | |010 = 8 system clock (HCLK). + * | | |011 = 16 system clock (HCLK). + * | | |100 = 32 system clock (HCLK). + * | | |101 = 64 system clock (HCLK). + * | | |110 = 128 system clock (HCLK). + * | | |111 = 256 system clock (HCLK). + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[14:12] |LVRDGSEL |LVR Output De-glitch Time Select (Write Protect) + * | | |000 = Without de-glitch function. + * | | |001 = 4 system clock (HCLK). + * | | |010 = 8 system clock (HCLK). + * | | |011 = 16 system clock (HCLK). + * | | |100 = 32 system clock (HCLK). + * | | |101 = 64 system clock (HCLK). + * | | |110 = 128 system clock (HCLK). + * | | |111 = 256 system clock (HCLK). + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[18:16] |BODVL |Brown-out Detector Threshold Voltage Selection (Write Protect) + * | | |The default value is set by flash controller user configuration register CBOV (CONFIG0 [23:21]). + * | | |000 = Brown-Out Detector threshold voltage is 1.6V. + * | | |001 = Brown-Out Detector threshold voltage is 1.8V. + * | | |010 = Brown-Out Detector threshold voltage is 2.0V. + * | | |011 = Brown-Out Detector threshold voltage is 2.2V. + * | | |100 = Brown-Out Detector threshold voltage is 2.4V. + * | | |101 = Brown-Out Detector threshold voltage is 2.6V. + * | | |110 = Brown-Out Detector threshold voltage is 2.8V. + * | | |111 = Brown-Out Detector threshold voltage is 3.0V. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var SYS_T::IVSCTL + * Offset: 0x1C Internal Voltage Source Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |VTEMPEN |Temperature Sensor Enable Bit + * | | |This bit is used to enable/disable temperature sensor function. + * | | |0 = Temperature sensor function Disabled (default). + * | | |1 = Temperature sensor function Enabled. + * | | |Note: After this bit is set to 1, the value of temperature sensor output can be obtained through GPC.9. + * |[1] |VBATUGEN |VBAT Unity Gain Buffer Enable Bit + * | | |This bit is used to enable/disable VBAT unity gain buffer function. + * | | |0 = VBAT unity gain buffer function Disabled (default). + * | | |1 = VBAT unity gain buffer function Enabled. + * | | |Note: After this bit is set to 1, the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result + * @var SYS_T::PORCTL + * Offset: 0x24 Power-On-Reset Controller Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |POROFF |Power-on Reset Enable Bit (Write Protect) + * | | |When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again + * | | |User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. + * | | |The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: + * | | |nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var SYS_T::VREFCTL + * Offset: 0x28 VREF Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |VREFCTL |VREF Control Bits (Write Protect) + * | | |00000 = VREF is from external pin. + * | | |00011 = VREF is internal 1.6V. + * | | |00111 = VREF is internal 2.0V. + * | | |01011 = VREF is internal 2.5V. + * | | |01111 = VREF is internal 3.0V. + * | | |Others = Reserved. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7:6] |PRELOAD_SEL|Pre-load Timing Selection. + * | | |00 = pre-load time is 60us for 0.1uF Capacitor. + * | | |01 = pre-load time is 310us for 1uF Capacitor. + * | | |10 = pre-load time is 1270us for 4.7uF Capacitor. + * | | |11 = pre-load time is 2650us for 10uF Capacitor. + * @var SYS_T::USBPHY + * Offset: 0x2C USB PHY Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |USBROLE |USB Role Option (Write Protect) + * | | |These two bits are used to select the role of USB. + * | | |00 = Standard USB Device mode. + * | | |01 = Standard USB Host mode. + * | | |10 = ID dependent mode. + * | | |11 = Reserved. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[2] |SBO |Note: This bit must always be kept 1. If set to 0, the result is unpredictable + * |[8] |USBEN |USB PHY Enable (Write Protect) + * | | |This bit is used to enable/disable USB PHY. + * | | |0 = USB PHY Disabled. + * | | |1 = USB PHY Enabled. + * |[17:16] |HSUSBROLE |HSUSB Role Option (Write Protect) + * | | |These two bits are used to select the role of HSUSB + * | | |00 = Standard HSUSB Device mode. + * | | |01 = Standard HSUSB Host mode. + * | | |10 = ID dependent mode. + * | | |11 = Reserved. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[24] |HSUSBEN |HSUSB PHY Enable (Write Protect) + * | | |This bit is used to enable/disable HSUSB PHY. + * | | |0 = HSUSB PHY Disabled. + * | | |1 = HSUSB PHY Enabled. + * |[25] |HSUSBACT |HSUSB PHY Active Control + * | | |This bit is used to control HSUSB PHY at reset state or active state. + * | | |0 = HSUSB PHY at reset state. + * | | |1 = HSUSB PHY at active state. + * | | |Note: After set HSUSBEN (SYS_USBPHY[24]) to enable HSUSB PHY, user should keep HSUSB PHY at reset mode at lease 10uS before changing to active mode. + * @var SYS_T::GPA_MFPL + * Offset: 0x30 GPIOA Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PA0MFP |PA.0 Multi-function Pin Selection + * |[7:4] |PA1MFP |PA.1 Multi-function Pin Selection + * |[11:8] |PA2MFP |PA.2 Multi-function Pin Selection + * |[15:12] |PA3MFP |PA.3 Multi-function Pin Selection + * |[19:16] |PA4MFP |PA.4 Multi-function Pin Selection + * |[23:20] |PA5MFP |PA.5 Multi-function Pin Selection + * |[27:24] |PA6MFP |PA.6 Multi-function Pin Selection + * |[31:28] |PA7MFP |PA.7 Multi-function Pin Selection + * @var SYS_T::GPA_MFPH + * Offset: 0x34 GPIOA High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PA8MFP |PA.8 Multi-function Pin Selection + * |[7:4] |PA9MFP |PA.9 Multi-function Pin Selection + * |[11:8] |PA10MFP |PA.10 Multi-function Pin Selection + * |[15:12] |PA11MFP |PA.11 Multi-function Pin Selection + * |[19:16] |PA12MFP |PA.12 Multi-function Pin Selection + * |[23:20] |PA13MFP |PA.13 Multi-function Pin Selection + * |[27:24] |PA14MFP |PA.14 Multi-function Pin Selection + * |[31:28] |PA15MFP |PA.15 Multi-function Pin Selection + * @var SYS_T::GPB_MFPL + * Offset: 0x38 GPIOB Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PB0MFP |PB.0 Multi-function Pin Selection + * |[7:4] |PB1MFP |PB.1 Multi-function Pin Selection + * |[11:8] |PB2MFP |PB.2 Multi-function Pin Selection + * |[15:12] |PB3MFP |PB.3 Multi-function Pin Selection + * |[19:16] |PB4MFP |PB.4 Multi-function Pin Selection + * |[23:20] |PB5MFP |PB.5 Multi-function Pin Selection + * |[27:24] |PB6MFP |PB.6 Multi-function Pin Selection + * |[31:28] |PB7MFP |PB.7 Multi-function Pin Selection + * @var SYS_T::GPB_MFPH + * Offset: 0x3C GPIOB High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PB8MFP |PB.8 Multi-function Pin Selection + * |[7:4] |PB9MFP |PB.9 Multi-function Pin Selection + * |[11:8] |PB10MFP |PB.10 Multi-function Pin Selection + * |[15:12] |PB11MFP |PB.11 Multi-function Pin Selection + * |[19:16] |PB12MFP |PB.12 Multi-function Pin Selection + * |[23:20] |PB13MFP |PB.13 Multi-function Pin Selection + * |[27:24] |PB14MFP |PB.14 Multi-function Pin Selection + * |[31:28] |PB15MFP |PB.15 Multi-function Pin Selection + * @var SYS_T::GPC_MFPL + * Offset: 0x40 GPIOC Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PC0MFP |PC.0 Multi-function Pin Selection + * |[7:4] |PC1MFP |PC.1 Multi-function Pin Selection + * |[11:8] |PC2MFP |PC.2 Multi-function Pin Selection + * |[15:12] |PC3MFP |PC.3 Multi-function Pin Selection + * |[19:16] |PC4MFP |PC.4 Multi-function Pin Selection + * |[23:20] |PC5MFP |PC.5 Multi-function Pin Selection + * |[27:24] |PC6MFP |PC.6 Multi-function Pin Selection + * |[31:28] |PC7MFP |PC.7 Multi-function Pin Selection + * @var SYS_T::GPC_MFPH + * Offset: 0x44 GPIOC High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PC8MFP |PC.8 Multi-function Pin Selection + * |[7:4] |PC9MFP |PC.9 Multi-function Pin Selection + * |[11:8] |PC10MFP |PC.10 Multi-function Pin Selection + * |[15:12] |PC11MFP |PC.11 Multi-function Pin Selection + * |[19:16] |PC12MFP |PC.12 Multi-function Pin Selection + * |[23:20] |PC13MFP |PC.13 Multi-function Pin Selection + * |[27:24] |PC14MFP |PC.14 Multi-function Pin Selection + * |[31:28] |PC15MFP |PC.15 Multi-function Pin Selection + * @var SYS_T::GPD_MFPL + * Offset: 0x48 GPIOD Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PD0MFP |PD.0 Multi-function Pin Selection + * |[7:4] |PD1MFP |PD.1 Multi-function Pin Selection + * |[11:8] |PD2MFP |PD.2 Multi-function Pin Selection + * |[15:12] |PD3MFP |PD.3 Multi-function Pin Selection + * |[19:16] |PD4MFP |PD.4 Multi-function Pin Selection + * |[23:20] |PD5MFP |PD.5 Multi-function Pin Selection + * |[27:24] |PD6MFP |PD.6 Multi-function Pin Selection + * |[31:28] |PD7MFP |PD.7 Multi-function Pin Selection + * @var SYS_T::GPD_MFPH + * Offset: 0x4C GPIOD High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PD8MFP |PD.8 Multi-function Pin Selection + * |[7:4] |PD9MFP |PD.9 Multi-function Pin Selection + * |[11:8] |PD10MFP |PD.10 Multi-function Pin Selection + * |[15:12] |PD11MFP |PD.11 Multi-function Pin Selection + * |[19:16] |PD12MFP |PD.12 Multi-function Pin Selection + * |[23:20] |PD13MFP |PD.13 Multi-function Pin Selection + * |[27:24] |PD14MFP |PD.14 Multi-function Pin Selection + * |[31:28] |PD15MFP |PD.15 Multi-function Pin Selection + * @var SYS_T::GPE_MFPL + * Offset: 0x50 GPIOE Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PE0MFP |PE.0 Multi-function Pin Selection + * |[7:4] |PE1MFP |PE.1 Multi-function Pin Selection + * |[11:8] |PE2MFP |PE.2 Multi-function Pin Selection + * |[15:12] |PE3MFP |PE.3 Multi-function Pin Selection + * |[19:16] |PE4MFP |PE.4 Multi-function Pin Selection + * |[23:20] |PE5MFP |PE.5 Multi-function Pin Selection + * |[27:24] |PE6MFP |PE.6 Multi-function Pin Selection + * |[31:28] |PE7MFP |PE.7 Multi-function Pin Selection + * @var SYS_T::GPE_MFPH + * Offset: 0x54 GPIOE High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PE8MFP |PE.8 Multi-function Pin Selection + * |[7:4] |PE9MFP |PE.9 Multi-function Pin Selection + * |[11:8] |PE10MFP |PE.10 Multi-function Pin Selection + * |[15:12] |PE11MFP |PE.11 Multi-function Pin Selection + * |[19:16] |PE12MFP |PE.12 Multi-function Pin Selection + * |[23:20] |PE13MFP |PE.13 Multi-function Pin Selection + * |[27:24] |PE14MFP |PE.14 Multi-function Pin Selection + * |[31:28] |PE15MFP |PE.15 Multi-function Pin Selection + * @var SYS_T::GPF_MFPL + * Offset: 0x58 GPIOF Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PF0MFP |PF.0 Multi-function Pin Selection + * |[7:4] |PF1MFP |PF.1 Multi-function Pin Selection + * |[11:8] |PF2MFP |PF.2 Multi-function Pin Selection + * |[15:12] |PF3MFP |PF.3 Multi-function Pin Selection + * |[19:16] |PF4MFP |PF.4 Multi-function Pin Selection + * |[23:20] |PF5MFP |PF.5 Multi-function Pin Selection + * |[27:24] |PF6MFP |PF.6 Multi-function Pin Selection + * |[31:28] |PF7MFP |PF.7 Multi-function Pin Selection + * @var SYS_T::GPF_MFPH + * Offset: 0x5C GPIOF High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PF8MFP |PF.8 Multi-function Pin Selection + * |[7:4] |PF9MFP |PF.9 Multi-function Pin Selection + * |[11:8] |PF10MFP |PF.10 Multi-function Pin Selection + * |[15:12] |PF11MFP |PF.11 Multi-function Pin Selection + * |[19:16] |PF12MFP |PF.12 Multi-function Pin Selection + * |[23:20] |PF13MFP |PF.13 Multi-function Pin Selection + * |[27:24] |PF14MFP |PF.14 Multi-function Pin Selection + * |[31:28] |PF15MFP |PF.15 Multi-function Pin Selection + * @var SYS_T::GPG_MFPL + * Offset: 0x60 GPIOG Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PG0MFP |PG.0 Multi-function Pin Selection + * |[7:4] |PG1MFP |PG.1 Multi-function Pin Selection + * |[11:8] |PG2MFP |PG.2 Multi-function Pin Selection + * |[15:12] |PG3MFP |PG.3 Multi-function Pin Selection + * |[19:16] |PG4MFP |PG.4 Multi-function Pin Selection + * |[23:20] |PG5MFP |PG.5 Multi-function Pin Selection + * |[27:24] |PG6MFP |PG.6 Multi-function Pin Selection + * |[31:28] |PG7MFP |PG.7 Multi-function Pin Selection + * @var SYS_T::GPG_MFPH + * Offset: 0x64 GPIOG High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PG8MFP |PG.8 Multi-function Pin Selection + * |[7:4] |PG9MFP |PG.9 Multi-function Pin Selection + * |[11:8] |PG10MFP |PG.10 Multi-function Pin Selection + * |[15:12] |PG11MFP |PG.11 Multi-function Pin Selection + * |[19:16] |PG12MFP |PG.12 Multi-function Pin Selection + * |[23:20] |PG13MFP |PG.13 Multi-function Pin Selection + * |[27:24] |PG14MFP |PG.14 Multi-function Pin Selection + * |[31:28] |PG15MFP |PG.15 Multi-function Pin Selection + * @var SYS_T::GPH_MFPL + * Offset: 0x68 GPIOH Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PH0MFP |PH.0 Multi-function Pin Selection + * |[7:4] |PH1MFP |PH.1 Multi-function Pin Selection + * |[11:8] |PH2MFP |PH.2 Multi-function Pin Selection + * |[15:12] |PH3MFP |PH.3 Multi-function Pin Selection + * |[19:16] |PH4MFP |PH.4 Multi-function Pin Selection + * |[23:20] |PH5MFP |PH.5 Multi-function Pin Selection + * |[27:24] |PH6MFP |PH.6 Multi-function Pin Selection + * |[31:28] |PH7MFP |PH.7 Multi-function Pin Selection + * @var SYS_T::GPH_MFPH + * Offset: 0x6C GPIOH High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PH8MFP |PH.8 Multi-function Pin Selection + * |[7:4] |PH9MFP |PH.9 Multi-function Pin Selection + * |[11:8] |PH10MFP |PH.10 Multi-function Pin Selection + * |[15:12] |PH11MFP |PH.11 Multi-function Pin Selection + * |[19:16] |PH12MFP |PH.12 Multi-function Pin Selection + * |[23:20] |PH13MFP |PH.13 Multi-function Pin Selection + * |[27:24] |PH14MFP |PH.14 Multi-function Pin Selection + * |[31:28] |PH15MFP |PH.15 Multi-function Pin Selection + * @var SYS_T::GPA_MFOS + * Offset: 0x80 GPIOA Multiple Function Output Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var SYS_T::GPB_MFOS + * Offset: 0x84 GPIOB Multiple Function Output Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var SYS_T::GPC_MFOS + * Offset: 0x88 GPIOC Multiple Function Output Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var SYS_T::GPD_MFOS + * Offset: 0x8C GPIOD Multiple Function Output Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var SYS_T::GPE_MFOS + * Offset: 0x90 GPIOE Multiple Function Output Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var SYS_T::GPF_MFOS + * Offset: 0x94 GPIOF Multiple Function Output Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var SYS_T::GPG_MFOS + * Offset: 0x98 GPIOG Multiple Function Output Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var SYS_T::GPH_MFOS + * Offset: 0x9C GPIOH Multiple Function Output Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var SYS_T::SRAM_INTCTL + * Offset: 0xC0 System SRAM Interrupt Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PERRIEN |SRAM Parity Check Error Interrupt Enable Bit + * | | |0 = SRAM parity check error interrupt Disabled. + * | | |1 = SRAM parity check error interrupt Enabled. + * @var SYS_T::SRAM_STATUS + * Offset: 0xC4 System SRAM Parity Error Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PERRIF |SRAM Parity Check Error Flag + * | | |This bit indicates the System SRAM parity error occurred. Write 1 to clear this to 0. + * | | |0 = No System SRAM parity error. + * | | |1 = System SRAM parity error occur. + * @var SYS_T::SRAM_ERRADDR + * Offset: 0xC8 System SRAM Parity Check Error Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ERRADDR |System SRAM Parity Error Address + * | | |This register shows system SRAM parity error byte address. + * @var SYS_T::SRAM_BISTCTL + * Offset: 0xD0 System SRAM BIST Test Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SRBIST0 |SRAM Bank0 BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for SRAM bank0. + * | | |0 = system SRAM bank0 BIST Disabled. + * | | |1 = system SRAM bank0 BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[1] |SRBIST1 |SRAM Bank1 BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for SRAM bank1. + * | | |0 = system SRAM bank1 BIST Disabled. + * | | |1 = system SRAM bank1 BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[2] |CRBIST |CACHE BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for CACHE RAM + * | | |0 = system CACHE BIST Disabled. + * | | |1 = system CACHE BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |CANBIST |CAN BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for CAN RAM + * | | |0 = system CAN BIST Disabled. + * | | |1 = system CAN BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[4] |USBBIST |USB BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for USB RAM + * | | |0 = system USB BIST Disabled. + * | | |1 = system USB BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[5] |SPIMBIST |SPIM BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for SPIM RAM + * | | |0 = system SPIM BIST Disabled. + * | | |1 = system SPIM BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[6] |EMCBIST |EMC BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for EMC RAM + * | | |0 = system EMC BIST Disabled. + * | | |1 = system EMC BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7] |PDMABIST |PDMA BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for PDMA RAM + * | | |0 = system PDMA BIST Disabled. + * | | |1 = system PDMA BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[8] |HSUSBDBIST|HSUSBD BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for HSUSBD RAM + * | | |0 = system HSUSBD BIST Disabled. + * | | |1 = system HSUSBD BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[9] |HSUSBHBIST|HSUSBH BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for HSUSBH RAM + * | | |0 = system HSUSBH BIST Disabled. + * | | |1 = system HSUSBH BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[16] |SRB0S0 |SRAM Bank0 Section 0 BIST Select (Write Protect) + * | | |This bit define if the first 16KB section of SRAM bank0 is selected or not when doing bist test. + * | | |0 = SRAM bank0 section 0 is deselected when doing bist test. + * | | |1 = SRAM bank0 section 0 is selected when doing bist test. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note: At least one section of SRAM bank0 should be selected when doing SRAM bank0 bist test. + * |[17] |SRB0S1 |SRAM Bank0 Section 1 BIST Select (Write Protect) + * | | |This bit define if the second 16KB section of SRAM bank0 is selected or not when doing bist test. + * | | |0 = SRAM bank0 section 1 is deselected when doing bist test. + * | | |1 = SRAM bank0 section 1 is selected when doing bist test. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note: At least one section of SRAM bank0 should be selected when doing SRAM bank0 bist test. + * |[18] |SRB1S0 |SRAM Bank1 Section 0 BIST Select (Write Protect) + * | | |This bit define if the first 16KB section of SRAM bank1 is selected or not when doing bist test. + * | | |0 = SRAM bank1 first 16KB section is deselected when doing bist test. + * | | |1 = SRAM bank1 first 16KB section is selected when doing bist test. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test. + * |[19] |SRB1S1 |SRAM Bank1 Section 1 BIST Select (Write Protect) + * | | |This bit define if the second 16KB section of SRAM bank1 is selected or not when doing bist test. + * | | |0 = SRAM bank1 second 16KB section is deselected when doing bist test. + * | | |1 = SRAM bank1 second 16KB section is selected when doing bist test. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test. + * |[20] |SRB1S2 |SRAM Bank1 Section 0 BIST Select (Write Protect) + * | | |This bit define if the third 16KB section of SRAM bank1 is selected or not when doing bist test. + * | | |0 = SRAM bank1 third 16KB section is deselected when doing bist test. + * | | |1 = SRAM bank1 third 16KB section is selected when doing bist test. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test. + * |[21] |SRB1S3 |SRAM Bank1 Section 1 BIST Select (Write Protect) + * | | |This bit define if the fourth 16KB section of SRAM bank1 is selected or not when doing bist test. + * | | |0 = SRAM bank1 fourth 16KB section is deselected when doing bist test. + * | | |1 = SRAM bank1 fourth 16KB section is selected when doing bist test. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test. + * |[22] |SRB1S4 |SRAM Bank1 Section 0 BIST Select (Write Protect) + * | | |This bit define if the fifth 16KB section of SRAM bank1 is selected or not when doing bist test. + * | | |0 = SRAM bank1 fifth 16KB section is deselected when doing bist test. + * | | |1 = SRAM bank1 fifth 16KB section is selected when doing bist test. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test. + * |[23] |SRB1S5 |SRAM Bank1 Section 1 BIST Select (Write Protect) + * | | |This bit define if the sixth 16KB section of SRAM bank1 is selected or not when doing bist test. + * | | |0 = SRAM bank1 sixth 16KB section is deselected when doing bist test. + * | | |1 = SRAM bank1 sixth 16KB section is selected when doing bist test. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test. + * @var SYS_T::SRAM_BISTSTS + * Offset: 0xD4 System SRAM BIST Test Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SRBISTEF0 |1st System SRAM BIST Fail Flag + * | | |0 = 1st system SRAM BIST test pass. + * | | |1 = 1st system SRAM BIST test fail. + * |[1] |SRBISTEF1 |2nd System SRAM BIST Fail Flag + * | | |0 = 2nd system SRAM BIST test pass. + * | | |1 = 2nd system SRAM BIST test fail. + * |[2] |CRBISTEF |CACHE SRAM BIST Fail Flag + * | | |0 = System CACHE RAM BIST test pass. + * | | |1 = System CACHE RAM BIST test fail. + * |[3] |CANBEF |CAN SRAM BIST Fail Flag + * | | |0 = CAN SRAM BIST test pass. + * | | |1 = CAN SRAM BIST test fail. + * |[4] |USBBEF |USB SRAM BIST Fail Flag + * | | |0 = USB SRAM BIST test pass. + * | | |1 = USB SRAM BIST test fail. + * |[16] |SRBEND0 |1st SRAM BIST Test Finish + * | | |0 = 1st system SRAM BIST active. + * | | |1 =1st system SRAM BIST finish. + * |[17] |SRBEND1 |2nd SRAM BIST Test Finish + * | | |0 = 2nd system SRAM BIST is active. + * | | |1 = 2nd system SRAM BIST finish. + * |[18] |CRBEND |CACHE SRAM BIST Test Finish + * | | |0 = System CACHE RAM BIST is active. + * | | |1 = System CACHE RAM BIST test finish. + * |[19] |CANBEND |CAN SRAM BIST Test Finish + * | | |0 = CAN SRAM BIST is active. + * | | |1 = CAN SRAM BIST test finish. + * |[20] |USBBEND |USB SRAM BIST Test Finish + * | | |0 = USB SRAM BIST is active. + * | | |1 = USB SRAM BIST test finish. + * @var SYS_T::HIRCTCTL + * Offset: 0xE4 HIRC48M Trim Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |FREQSEL |Trim Frequency Selection + * | | |This field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC) auto trim. + * | | |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. + * | | |00 = Disable HIRC auto trim function. + * | | |01 = Enable HIRC auto trim function and trim HIRC to 48 MHz. + * | | |10 = Reserved.. + * | | |11 = Reserved. + * |[5:4] |LOOPSEL |Trim Calculation Loop Selection + * | | |This field defines that trim value calculation is based on how many reference clocks. + * | | |00 = Trim value calculation is based on average difference in 4 clocks of reference clock. + * | | |01 = Trim value calculation is based on average difference in 8 clocks of reference clock. + * | | |10 = Trim value calculation is based on average difference in 16 clocks of reference clock. + * | | |11 = Trim value calculation is based on average difference in 32 clocks of reference clock. + * | | |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock. + * |[7:6] |RETRYCNT |Trim Value Update Limitation Count + * | | |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked. + * | | |Once the HIRC locked, the internal trim value update counter will be reset. + * | | |If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00. + * | | |00 = Trim retry count limitation is 64 loops. + * | | |01 = Trim retry count limitation is 128 loops. + * | | |10 = Trim retry count limitation is 256 loops. + * | | |11 = Trim retry count limitation is 512 loops. + * |[8] |CESTOPEN |Clock Error Stop Enable Bit + * | | |0 = The trim operation is keep going if clock is inaccuracy. + * | | |1 = The trim operation is stopped if clock is inaccuracy. + * |[9] |BOUNDEN |Boundary Enable Bit + * | | |0 = Boundary function is disable. + * | | |1 = Boundary function is enable. + * |[10] |REFCKSEL |Reference Clock Selection + * | | |0 = HIRC trim reference from external 32.768 kHz crystal oscillator. + * | | |1 = HIRC trim reference from internal USB synchronous mode. + * | | |Note: HIRC trim reference clock is 20Khz in test mode. + * |[20:16 |BOUNDARY |Boundary Selection + * | | |Fill the boundary range from 0x1 to 0x31, 0x0 is reserved. + * | | |Note1: This field is effective only when the BOUNDEN(SYS_HIRCTRIMCTL[9]) is enable. + * @var SYS_T::HIRCTIEN + * Offset: 0xE8 HIRC48M Trim Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TFAILIEN |Trim Failure Interrupt Enable Bit + * | | |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_HIRCTCTL[1:0]). + * | | |If this bit is high and TFAILIF(SYS_HIRCTISTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. + * | | |0 = Disable TFAILIF(SYS_HIRCTISTS[1]) status to trigger an interrupt to CPU. + * | | |1 = Enable TFAILIF(SYS_HIRCTISTS[1]) status to trigger an interrupt to CPU. + * |[2] |CLKEIEN |Clock Error Interrupt Enable Bit + * | | |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. + * | | |If this bit is set to1, and CLKERRIF(SYS_HIRCTISTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. + * | | |0 = Disable CLKERRIF(SYS_HIRCTISTS[2]) status to trigger an interrupt to CPU. + * | | |1 = Enable CLKERRIF(SYS_HIRCTISTS[2]) status to trigger an interrupt to CPU. + * @var SYS_T::HIRCTISTS + * Offset: 0xEC HIRC48M Trim Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FREQLOCK |HIRC Frequency Lock Status + * | | |This bit indicates the HIRC frequency is locked. + * | | |This is a status bit and doesn't trigger any interrupt + * | | |Write 1 to clear this to 0 + * | | |This bit will be set automatically, if the frequency is lock and the RC_TRIM is enabled. + * | | |0 = The internal high-speed oscillator frequency doesn't lock at 48 MHz yet. + * | | |1 = The internal high-speed oscillator frequency locked at 48 MHz. + * |[1] |TFAILIF |Trim Failure Interrupt Status + * | | |This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked + * | | |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_HIRCTCTL[1:0]) will be cleared to 00 by hardware automatically. + * | | |If this bit is set and TFAILIEN(SYS_HIRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached + * | | |Write 1 to clear this to 0. + * | | |0 = Trim value update limitation count does not reach. + * | | |1 = Trim value update limitation count reached and HIRC frequency still not locked. + * |[2] |CLKERRIF |Clock Error Interrupt Status + * | | |When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 48MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy. + * | | |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_HIRCTCL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_HIRCTCTL[8]) is set to 1. + * | | |If this bit is set and CLKEIEN(SYS_HIRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. + * | | |Write 1 to clear this to 0. + * | | |0 = Clock frequency is accurate. + * | | |1 = Clock frequency is inaccurate. + * |[3] |OVBDIF |Over Boundary Status + * | | |When the over boundary function is set, if there occurs the over boundary condition, this flag will be set. + * | | |Note1: Write 1 to clear this flag. + * | | |Note2: This function is only supported in M48xGC/M48xG8. + * | | |0 = Over boundary condition did not occur. + * | | |1 = Over boundary condition occurred. + * @var SYS_T::IRCTCTL + * Offset: 0xF0 HIRC Trim Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |FREQSEL |Trim Frequency Selection + * | | |This field indicates the target frequency of 12 MHz internal high speed RC oscillator (HIRC) auto trim. + * | | |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. + * | | |00 = Disable HIRC auto trim function. + * | | |01 = Enable HIRC auto trim function and trim HIRC to 12 MHz. + * | | |10 = Reserved.. + * | | |11 = Reserved. + * |[5:4] |LOOPSEL |Trim Calculation Loop Selection + * | | |This field defines that trim value calculation is based on how many reference clocks. + * | | |00 = Trim value calculation is based on average difference in 4 clocks of reference clock. + * | | |01 = Trim value calculation is based on average difference in 8 clocks of reference clock. + * | | |10 = Trim value calculation is based on average difference in 16 clocks of reference clock. + * | | |11 = Trim value calculation is based on average difference in 32 clocks of reference clock. + * | | |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock. + * |[7:6] |RETRYCNT |Trim Value Update Limitation Count + * | | |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked. + * | | |Once the HIRC locked, the internal trim value update counter will be reset. + * | | |If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00. + * | | |00 = Trim retry count limitation is 64 loops. + * | | |01 = Trim retry count limitation is 128 loops. + * | | |10 = Trim retry count limitation is 256 loops. + * | | |11 = Trim retry count limitation is 512 loops. + * |[8] |CESTOPEN |Clock Error Stop Enable Bit + * | | |0 = The trim operation is keep going if clock is inaccuracy. + * | | |1 = The trim operation is stopped if clock is inaccuracy. + * |[10] |REFCKSEL |Reference Clock Selection + * | | |0 = HIRC trim reference from external 32.768 kHz crystal oscillator. + * | | |1 = HIRC trim reference from internal USB synchronous mode. + * | | |Note: HIRC trim reference clock is 20Khz in test mode. + * @var SYS_T::IRCTIEN + * Offset: 0xF4 HIRC Trim Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TFAILIEN |Trim Failure Interrupt Enable Bit + * | | |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]). + * | | |If this bit is high and TFAILIF(SYS_IRCTISTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. + * | | |0 = Disable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU. + * | | |1 = Enable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU. + * |[2] |CLKEIEN |Clock Error Interrupt Enable Bit + * | | |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. + * | | |If this bit is set to1, and CLKERRIF(SYS_IRCTISTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. + * | | |0 = Disable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU. + * | | |1 = Enable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU. + * @var SYS_T::IRCTISTS + * Offset: 0xF8 HIRC Trim Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FREQLOCK |HIRC Frequency Lock Status + * | | |This bit indicates the HIRC frequency is locked. + * | | |This is a status bit and doesn't trigger any interrupt + * | | |Write 1 to clear this to 0 + * | | |This bit will be set automatically, if the frequency is lock and the RC_TRIM is enabled. + * | | |0 = The internal high-speed oscillator frequency doesn't lock at 12 MHz yet. + * | | |1 = The internal high-speed oscillator frequency locked at 12 MHz. + * |[1] |TFAILIF |Trim Failure Interrupt Status + * | | |This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked + * | | |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_IRCTCTL[1:0]) will be cleared to 00 by hardware automatically. + * | | |If this bit is set and TFAILIEN(SYS_IRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached + * | | |Write 1 to clear this to 0. + * | | |0 = Trim value update limitation count does not reach. + * | | |1 = Trim value update limitation count reached and HIRC frequency still not locked. + * |[2] |CLKERRIF |Clock Error Interrupt Status + * | | |When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 12MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy. + * | | |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRCTCL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRCTCTL[8]) is set to 1. + * | | |If this bit is set and CLKEIEN(SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. + * | | |Write 1 to clear this to 0. + * | | |0 = Clock frequency is accurate. + * | | |1 = Clock frequency is inaccurate. + * @var SYS_T::REGLCTL + * Offset: 0x100 Register Lock Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |REGLCTL |Register Lock Control Code + * | | |Some registers have write-protection function + * | | |Writing these registers have to disable the protected function by writing the sequence value "59h", "16h", "88h" to this field. + * | | |After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write. + * | | |Register Lock Control Code + * | | |0 = Write-protection Enabled for writing protected registers + * | | |Any write to the protected register is ignored. + * | | |1 = Write-protection Disabled for writing protected registers. + * @var SYS_T::PORDISAN + * Offset: 0x1EC Analog POR Disable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |POROFFAN |Power-on Reset Enable Bit (Write Protect) + * | | |After powered on, User can turn off internal analog POR circuit to save power by writing 0x5AA5 to this field. + * | | |The analog POR circuit will be active again when this field is set to another value or chip is reset by other reset source, including: + * | | |nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var SYS_T::PLCTL + * Offset: 0x1F8 Power Level Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |PLSEL |Power Level Select(Write Protect) + * | | |00 = Power level is PL0. + * | | |01 = Power level is PL1. + * | | |Others = Reserved. + * |[21:16] |LVSSTEP |LDO Voltage Scaling Step(Write Protect) + * | | |The LVSSTEP value is LDO voltage rising step. + * | | |Core voltage scaling voltage step = (LVSSTEP + 1) * 10mV. + * |[31:24] |LVSPRD |LDO Voltage Scaling Period(Write Protect) + * | | |The LVSPRD value is the period of each LDO voltage rising step. + * | | |LDO voltage scaling period = (LVSPRD + 1) * 1us. + * @var SYS_T::PLSTS + * Offset: 0x1FC Power Level Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PLCBUSY |Power Level Change Busy Bit (Read Only) + * | | |This bit is set by hardware when core voltage is changing + * | | |After core voltage change is completed, this bit will be cleared automatically by hardware. + * | | |0 = Core voltage change is completed. + * | | |1 = Core voltage change is ongoing. + * |[9:8] |PLSTATUS |Power Level Status (Read Only) + * | | |00 = Power level is PL0. + * | | |01 = Power level is PL1. + * | | |Others = Reserved. + * @var SYS_T::AHBMCTL + * Offset: 0x400 AHB Bus Matrix Priority Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |INTACTEN |Highest AHB Bus Priority of Cortex M4 Core Enable Bit (Write Protect) + * | | |Enable Cortex-M4 Core With Highest AHB Bus Priority In AHB Bus Matrix + * | | |0 = Run robin mode. + * | | |1 = Cortex-M4 CPU with highest bus priority when interrupt occurred. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + */ + __I uint32_t PDID; /*!< [0x0000] Part Device Identification Number Register */ + __IO uint32_t RSTSTS; /*!< [0x0004] System Reset Status Register */ + __IO uint32_t IPRST0; /*!< [0x0008] Peripheral Reset Control Register 0 */ + __IO uint32_t IPRST1; /*!< [0x000c] Peripheral Reset Control Register 1 */ + __IO uint32_t IPRST2; /*!< [0x0010] Peripheral Reset Control Register 2 */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE0[1]; + /** @endcond */ + __IO uint32_t BODCTL; /*!< [0x0018] Brown-Out Detector Control Register */ + __IO uint32_t IVSCTL; /*!< [0x001c] Internal Voltage Source Control Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE1[1]; + /** @endcond */ + __IO uint32_t PORCTL; /*!< [0x0024] Power-On-Reset Controller Register */ + __IO uint32_t VREFCTL; /*!< [0x0028] VREF Control Register */ + __IO uint32_t USBPHY; /*!< [0x002c] USB PHY Control Register */ + __IO uint32_t GPA_MFPL; /*!< [0x0030] GPIOA Low Byte Multiple Function Control Register */ + __IO uint32_t GPA_MFPH; /*!< [0x0034] GPIOA High Byte Multiple Function Control Register */ + __IO uint32_t GPB_MFPL; /*!< [0x0038] GPIOB Low Byte Multiple Function Control Register */ + __IO uint32_t GPB_MFPH; /*!< [0x003c] GPIOB High Byte Multiple Function Control Register */ + __IO uint32_t GPC_MFPL; /*!< [0x0040] GPIOC Low Byte Multiple Function Control Register */ + __IO uint32_t GPC_MFPH; /*!< [0x0044] GPIOC High Byte Multiple Function Control Register */ + __IO uint32_t GPD_MFPL; /*!< [0x0048] GPIOD Low Byte Multiple Function Control Register */ + __IO uint32_t GPD_MFPH; /*!< [0x004c] GPIOD High Byte Multiple Function Control Register */ + __IO uint32_t GPE_MFPL; /*!< [0x0050] GPIOE Low Byte Multiple Function Control Register */ + __IO uint32_t GPE_MFPH; /*!< [0x0054] GPIOE High Byte Multiple Function Control Register */ + __IO uint32_t GPF_MFPL; /*!< [0x0058] GPIOF Low Byte Multiple Function Control Register */ + __IO uint32_t GPF_MFPH; /*!< [0x005c] GPIOF High Byte Multiple Function Control Register */ + __IO uint32_t GPG_MFPL; /*!< [0x0060] GPIOG Low Byte Multiple Function Control Register */ + __IO uint32_t GPG_MFPH; /*!< [0x0064] GPIOG High Byte Multiple Function Control Register */ + __IO uint32_t GPH_MFPL; /*!< [0x0068] GPIOH Low Byte Multiple Function Control Register */ + __IO uint32_t GPH_MFPH; /*!< [0x006c] GPIOH High Byte Multiple Function Control Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE2[4]; + /** @endcond */ + __IO uint32_t GPA_MFOS; /*!< [0x0080] GPIOA Multiple Function Output Select Register */ + __IO uint32_t GPB_MFOS; /*!< [0x0084] GPIOB Multiple Function Output Select Register */ + __IO uint32_t GPC_MFOS; /*!< [0x0088] GPIOC Multiple Function Output Select Register */ + __IO uint32_t GPD_MFOS; /*!< [0x008c] GPIOD Multiple Function Output Select Register */ + __IO uint32_t GPE_MFOS; /*!< [0x0090] GPIOE Multiple Function Output Select Register */ + __IO uint32_t GPF_MFOS; /*!< [0x0094] GPIOF Multiple Function Output Select Register */ + __IO uint32_t GPG_MFOS; /*!< [0x0098] GPIOG Multiple Function Output Select Register */ + __IO uint32_t GPH_MFOS; /*!< [0x009c] GPIOH Multiple Function Output Select Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE3[8]; + /** @endcond */ + __IO uint32_t SRAM_INTCTL; /*!< [0x00c0] System SRAM Interrupt Enable Control Register */ + __IO uint32_t SRAM_STATUS; /*!< [0x00c4] System SRAM Parity Error Status Register */ + __I uint32_t SRAM_ERRADDR; /*!< [0x00c8] System SRAM Parity Check Error Address Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE4[1]; + /** @endcond */ + __IO uint32_t SRAM_BISTCTL; /*!< [0x00d0] System SRAM BIST Test Control Register */ + __I uint32_t SRAM_BISTSTS; /*!< [0x00d4] System SRAM BIST Test Status Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE5[3]; + /** @endcond */ + __IO uint32_t HIRCTCTL; /*!< [0x00e4] HIRC48M Trim Control Register */ + __IO uint32_t HIRCTIEN; /*!< [0x00e8] HIRC48M Trim Interrupt Enable Register */ + __IO uint32_t HIRCTISTS; /*!< [0x00ec] HIRC48M Trim Interrupt Status Register */ + __IO uint32_t IRCTCTL; /*!< [0x00f0] HIRC Trim Control Register */ + __IO uint32_t IRCTIEN; /*!< [0x00f4] HIRC Trim Interrupt Enable Register */ + __IO uint32_t IRCTISTS; /*!< [0x00f8] HIRC Trim Interrupt Status Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE6[1]; + /** @endcond */ + __IO uint32_t REGLCTL; /*!< [0x0100] Register Lock Control Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE7[58]; + /** @endcond */ + __IO uint32_t PORDISAN; /*!< [0x01ec] Analog POR Disable Control Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE8; + /** @endcond */ + __I uint32_t CSERVER; /*!< [0x01f4] Chip Series Version Register */ + __IO uint32_t PLCTL; /*!< [0x01f8] Power Level Control Register */ + __I uint32_t PLSTS; /*!< [0x01fc] Power Level Status Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE9[128]; + /** @endcond */ + __IO uint32_t AHBMCTL; /*!< [0x0400] AHB Bus Matrix Priority Control Register */ + +} SYS_T; + +/** + @addtogroup SYS_CONST SYS Bit Field Definition + Constant Definitions for SYS Controller +@{ */ + +#define SYS_PDID_PDID_Pos (0) /*!< SYS_T::PDID: PDID Position */ +#define SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos) /*!< SYS_T::PDID: PDID Mask */ + +#define SYS_RSTSTS_PORF_Pos (0) /*!< SYS_T::RSTSTS: PORF Position */ +#define SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos) /*!< SYS_T::RSTSTS: PORF Mask */ + +#define SYS_RSTSTS_PINRF_Pos (1) /*!< SYS_T::RSTSTS: PINRF Position */ +#define SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos) /*!< SYS_T::RSTSTS: PINRF Mask */ + +#define SYS_RSTSTS_WDTRF_Pos (2) /*!< SYS_T::RSTSTS: WDTRF Position */ +#define SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos) /*!< SYS_T::RSTSTS: WDTRF Mask */ + +#define SYS_RSTSTS_LVRF_Pos (3) /*!< SYS_T::RSTSTS: LVRF Position */ +#define SYS_RSTSTS_LVRF_Msk (0x1ul << SYS_RSTSTS_LVRF_Pos) /*!< SYS_T::RSTSTS: LVRF Mask */ + +#define SYS_RSTSTS_BODRF_Pos (4) /*!< SYS_T::RSTSTS: BODRF Position */ +#define SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos) /*!< SYS_T::RSTSTS: BODRF Mask */ + +#define SYS_RSTSTS_SYSRF_Pos (5) /*!< SYS_T::RSTSTS: SYSRF Position */ +#define SYS_RSTSTS_SYSRF_Msk (0x1ul << SYS_RSTSTS_SYSRF_Pos) /*!< SYS_T::RSTSTS: SYSRF Mask */ + +#define SYS_RSTSTS_CPURF_Pos (7) /*!< SYS_T::RSTSTS: CPURF Position */ +#define SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos) /*!< SYS_T::RSTSTS: CPURF Mask */ + +#define SYS_RSTSTS_CPULKRF_Pos (8) /*!< SYS_T::RSTSTS: CPULKRF Position */ +#define SYS_RSTSTS_CPULKRF_Msk (0x1ul << SYS_RSTSTS_CPULKRF_Pos) /*!< SYS_T::RSTSTS: CPULKRF Mask */ + +#define SYS_IPRST0_CHIPRST_Pos (0) /*!< SYS_T::IPRST0: CHIPRST Position */ +#define SYS_IPRST0_CHIPRST_Msk (0x1ul << SYS_IPRST0_CHIPRST_Pos) /*!< SYS_T::IPRST0: CHIPRST Mask */ + +#define SYS_IPRST0_CPURST_Pos (1) /*!< SYS_T::IPRST0: CPURST Position */ +#define SYS_IPRST0_CPURST_Msk (0x1ul << SYS_IPRST0_CPURST_Pos) /*!< SYS_T::IPRST0: CPURST Mask */ + +#define SYS_IPRST0_PDMARST_Pos (2) /*!< SYS_T::IPRST0: PDMARST Position */ +#define SYS_IPRST0_PDMARST_Msk (0x1ul << SYS_IPRST0_PDMARST_Pos) /*!< SYS_T::IPRST0: PDMARST Mask */ + +#define SYS_IPRST0_EBIRST_Pos (3) /*!< SYS_T::IPRST0: EBIRST Position */ +#define SYS_IPRST0_EBIRST_Msk (0x1ul << SYS_IPRST0_EBIRST_Pos) /*!< SYS_T::IPRST0: EBIRST Mask */ + +#define SYS_IPRST0_EMACRST_Pos (5) /*!< SYS_T::IPRST0: EMACRST Position */ +#define SYS_IPRST0_EMACRST_Msk (0x1ul << SYS_IPRST0_EMACRST_Pos) /*!< SYS_T::IPRST0: EMACRST Mask */ + +#define SYS_IPRST0_SDH0RST_Pos (6) /*!< SYS_T::IPRST0: SDH0RST Position */ +#define SYS_IPRST0_SDH0RST_Msk (0x1ul << SYS_IPRST0_SDH0RST_Pos) /*!< SYS_T::IPRST0: SDH0RST Mask */ + +#define SYS_IPRST0_CRCRST_Pos (7) /*!< SYS_T::IPRST0: CRCRST Position */ +#define SYS_IPRST0_CRCRST_Msk (0x1ul << SYS_IPRST0_CRCRST_Pos) /*!< SYS_T::IPRST0: CRCRST Mask */ + +#define SYS_IPRST0_CCAPRST_Pos (8) /*!< SYS_T::IPRST0: CCAPRST Position */ +#define SYS_IPRST0_CCAPRST_Msk (0x1ul << SYS_IPRST0_CCAPRST_Pos) /*!< SYS_T::IPRST0: CCAPRST Mask */ + +#define SYS_IPRST0_HSUSBDRST_Pos (10) /*!< SYS_T::IPRST0: HSUSBDRST Position */ +#define SYS_IPRST0_HSUSBDRST_Msk (0x1ul << SYS_IPRST0_HSUSBDRST_Pos) /*!< SYS_T::IPRST0: HSUSBDRST Mask */ + +#define SYS_IPRST0_CRPTRST_Pos (12) /*!< SYS_T::IPRST0: CRPTRST Position */ +#define SYS_IPRST0_CRPTRST_Msk (0x1ul << SYS_IPRST0_CRPTRST_Pos) /*!< SYS_T::IPRST0: CRPTRST Mask */ + +#define SYS_IPRST0_SPIMRST_Pos (14) /*!< SYS_T::IPRST0: SPIMRST Position */ +#define SYS_IPRST0_SPIMRST_Msk (0x1ul << SYS_IPRST0_SPIMRST_Pos) /*!< SYS_T::IPRST0: SPIMRST Mask */ + +#define SYS_IPRST0_USBHRST_Pos (16) /*!< SYS_T::IPRST0: USBHRST Position */ +#define SYS_IPRST0_USBHRST_Msk (0x1ul << SYS_IPRST0_USBHRST_Pos) /*!< SYS_T::IPRST0: USBHRST Mask */ + +#define SYS_IPRST0_SDH1RST_Pos (17) /*!< SYS_T::IPRST0: SDH1RST Position */ +#define SYS_IPRST0_SDH1RST_Msk (0x1ul << SYS_IPRST0_SDH1RST_Pos) /*!< SYS_T::IPRST0: SDH1RST Mask */ + +#define SYS_IPRST1_GPIORST_Pos (1) /*!< SYS_T::IPRST1: GPIORST Position */ +#define SYS_IPRST1_GPIORST_Msk (0x1ul << SYS_IPRST1_GPIORST_Pos) /*!< SYS_T::IPRST1: GPIORST Mask */ + +#define SYS_IPRST1_TMR0RST_Pos (2) /*!< SYS_T::IPRST1: TMR0RST Position */ +#define SYS_IPRST1_TMR0RST_Msk (0x1ul << SYS_IPRST1_TMR0RST_Pos) /*!< SYS_T::IPRST1: TMR0RST Mask */ + +#define SYS_IPRST1_TMR1RST_Pos (3) /*!< SYS_T::IPRST1: TMR1RST Position */ +#define SYS_IPRST1_TMR1RST_Msk (0x1ul << SYS_IPRST1_TMR1RST_Pos) /*!< SYS_T::IPRST1: TMR1RST Mask */ + +#define SYS_IPRST1_TMR2RST_Pos (4) /*!< SYS_T::IPRST1: TMR2RST Position */ +#define SYS_IPRST1_TMR2RST_Msk (0x1ul << SYS_IPRST1_TMR2RST_Pos) /*!< SYS_T::IPRST1: TMR2RST Mask */ + +#define SYS_IPRST1_TMR3RST_Pos (5) /*!< SYS_T::IPRST1: TMR3RST Position */ +#define SYS_IPRST1_TMR3RST_Msk (0x1ul << SYS_IPRST1_TMR3RST_Pos) /*!< SYS_T::IPRST1: TMR3RST Mask */ + +#define SYS_IPRST1_ACMP01RST_Pos (7) /*!< SYS_T::IPRST1: ACMP01RST Position */ +#define SYS_IPRST1_ACMP01RST_Msk (0x1ul << SYS_IPRST1_ACMP01RST_Pos) /*!< SYS_T::IPRST1: ACMP01RST Mask */ + +#define SYS_IPRST1_I2C0RST_Pos (8) /*!< SYS_T::IPRST1: I2C0RST Position */ +#define SYS_IPRST1_I2C0RST_Msk (0x1ul << SYS_IPRST1_I2C0RST_Pos) /*!< SYS_T::IPRST1: I2C0RST Mask */ + +#define SYS_IPRST1_I2C1RST_Pos (9) /*!< SYS_T::IPRST1: I2C1RST Position */ +#define SYS_IPRST1_I2C1RST_Msk (0x1ul << SYS_IPRST1_I2C1RST_Pos) /*!< SYS_T::IPRST1: I2C1RST Mask */ + +#define SYS_IPRST1_I2C2RST_Pos (10) /*!< SYS_T::IPRST1: I2C2RST Position */ +#define SYS_IPRST1_I2C2RST_Msk (0x1ul << SYS_IPRST1_I2C2RST_Pos) /*!< SYS_T::IPRST1: I2C2RST Mask */ + +#define SYS_IPRST1_QSPI0RST_Pos (12) /*!< SYS_T::IPRST1: QSPI0RST Position */ +#define SYS_IPRST1_QSPI0RST_Msk (0x1ul << SYS_IPRST1_QSPI0RST_Pos) /*!< SYS_T::IPRST1: QSPI0RST Mask */ + +#define SYS_IPRST1_SPI0RST_Pos (13) /*!< SYS_T::IPRST1: SPI0RST Position */ +#define SYS_IPRST1_SPI0RST_Msk (0x1ul << SYS_IPRST1_SPI0RST_Pos) /*!< SYS_T::IPRST1: SPI0RST Mask */ + +#define SYS_IPRST1_SPI1RST_Pos (14) /*!< SYS_T::IPRST1: SPI1RST Position */ +#define SYS_IPRST1_SPI1RST_Msk (0x1ul << SYS_IPRST1_SPI1RST_Pos) /*!< SYS_T::IPRST1: SPI1RST Mask */ + +#define SYS_IPRST1_SPI2RST_Pos (15) /*!< SYS_T::IPRST1: SPI2RST Position */ +#define SYS_IPRST1_SPI2RST_Msk (0x1ul << SYS_IPRST1_SPI2RST_Pos) /*!< SYS_T::IPRST1: SPI2RST Mask */ + +#define SYS_IPRST1_UART0RST_Pos (16) /*!< SYS_T::IPRST1: UART0RST Position */ +#define SYS_IPRST1_UART0RST_Msk (0x1ul << SYS_IPRST1_UART0RST_Pos) /*!< SYS_T::IPRST1: UART0RST Mask */ + +#define SYS_IPRST1_UART1RST_Pos (17) /*!< SYS_T::IPRST1: UART1RST Position */ +#define SYS_IPRST1_UART1RST_Msk (0x1ul << SYS_IPRST1_UART1RST_Pos) /*!< SYS_T::IPRST1: UART1RST Mask */ + +#define SYS_IPRST1_UART2RST_Pos (18) /*!< SYS_T::IPRST1: UART2RST Position */ +#define SYS_IPRST1_UART2RST_Msk (0x1ul << SYS_IPRST1_UART2RST_Pos) /*!< SYS_T::IPRST1: UART2RST Mask */ + +#define SYS_IPRST1_UART3RST_Pos (19) /*!< SYS_T::IPRST1: UART3RST Position */ +#define SYS_IPRST1_UART3RST_Msk (0x1ul << SYS_IPRST1_UART3RST_Pos) /*!< SYS_T::IPRST1: UART3RST Mask */ + +#define SYS_IPRST1_UART4RST_Pos (20) /*!< SYS_T::IPRST1: UART4RST Position */ +#define SYS_IPRST1_UART4RST_Msk (0x1ul << SYS_IPRST1_UART4RST_Pos) /*!< SYS_T::IPRST1: UART4RST Mask */ + +#define SYS_IPRST1_UART5RST_Pos (21) /*!< SYS_T::IPRST1: UART5RST Position */ +#define SYS_IPRST1_UART5RST_Msk (0x1ul << SYS_IPRST1_UART5RST_Pos) /*!< SYS_T::IPRST1: UART5RST Mask */ + +#define SYS_IPRST1_UART6RST_Pos (22) /*!< SYS_T::IPRST1: UART6RST Position */ +#define SYS_IPRST1_UART6RST_Msk (0x1ul << SYS_IPRST1_UART6RST_Pos) /*!< SYS_T::IPRST1: UART6RST Mask */ + +#define SYS_IPRST1_UART7RST_Pos (23) /*!< SYS_T::IPRST1: UART7RST Position */ +#define SYS_IPRST1_UART7RST_Msk (0x1ul << SYS_IPRST1_UART7RST_Pos) /*!< SYS_T::IPRST1: UART7RST Mask */ + +#define SYS_IPRST1_CAN0RST_Pos (24) /*!< SYS_T::IPRST1: CAN0RST Position */ +#define SYS_IPRST1_CAN0RST_Msk (0x1ul << SYS_IPRST1_CAN0RST_Pos) /*!< SYS_T::IPRST1: CAN0RST Mask */ + +#define SYS_IPRST1_CAN1RST_Pos (25) /*!< SYS_T::IPRST1: CAN1RST Position */ +#define SYS_IPRST1_CAN1RST_Msk (0x1ul << SYS_IPRST1_CAN1RST_Pos) /*!< SYS_T::IPRST1: CAN1RST Mask */ + +#define SYS_IPRST1_OTGRST_Pos (26) /*!< SYS_T::IPRST1: OTGRST Position */ +#define SYS_IPRST1_OTGRST_Msk (0x1ul << SYS_IPRST1_OTGRST_Pos) /*!< SYS_T::IPRST1: OTGRST Mask */ + +#define SYS_IPRST1_USBDRST_Pos (27) /*!< SYS_T::IPRST1: USBDRST Position */ +#define SYS_IPRST1_USBDRST_Msk (0x1ul << SYS_IPRST1_USBDRST_Pos) /*!< SYS_T::IPRST1: USBDRST Mask */ + +#define SYS_IPRST1_EADCRST_Pos (28) /*!< SYS_T::IPRST1: EADCRST Position */ +#define SYS_IPRST1_EADCRST_Msk (0x1ul << SYS_IPRST1_EADCRST_Pos) /*!< SYS_T::IPRST1: EADCRST Mask */ + +#define SYS_IPRST1_I2S0RST_Pos (29) /*!< SYS_T::IPRST1: I2S0RST Position */ +#define SYS_IPRST1_I2S0RST_Msk (0x1ul << SYS_IPRST1_I2S0RST_Pos) /*!< SYS_T::IPRST1: I2S0RST Mask */ + +#define SYS_IPRST1_HSOTGRST_Pos (30) /*!< SYS_T::IPRST1: HSOTGRST Position */ +#define SYS_IPRST1_HSOTGRST_Msk (0x1ul << SYS_IPRST1_HSOTGRST_Pos) /*!< SYS_T::IPRST1: HSOTGRST Mask */ + +#define SYS_IPRST1_TRNGRST_Pos (31) /*!< SYS_T::IPRST1: TRNGRST Position */ +#define SYS_IPRST1_TRNGRST_Msk (0x1ul << SYS_IPRST1_TRNGRST_Pos) /*!< SYS_T::IPRST1: TRNGRST Mask */ + +#define SYS_IPRST2_SC0RST_Pos (0) /*!< SYS_T::IPRST2: SC0RST Position */ +#define SYS_IPRST2_SC0RST_Msk (0x1ul << SYS_IPRST2_SC0RST_Pos) /*!< SYS_T::IPRST2: SC0RST Mask */ + +#define SYS_IPRST2_SC1RST_Pos (1) /*!< SYS_T::IPRST2: SC1RST Position */ +#define SYS_IPRST2_SC1RST_Msk (0x1ul << SYS_IPRST2_SC1RST_Pos) /*!< SYS_T::IPRST2: SC1RST Mask */ + +#define SYS_IPRST2_SC2RST_Pos (2) /*!< SYS_T::IPRST2: SC2RST Position */ +#define SYS_IPRST2_SC2RST_Msk (0x1ul << SYS_IPRST2_SC2RST_Pos) /*!< SYS_T::IPRST2: SC2RST Mask */ + +#define SYS_IPRST2_QSPI1RST_Pos (4) /*!< SYS_T::IPRST2: QSPI1RST Position */ +#define SYS_IPRST2_QSPI1RST_Msk (0x1ul << SYS_IPRST2_QSPI1RST_Pos) /*!< SYS_T::IPRST2: QSPI1RST Mask */ + +#define SYS_IPRST2_SPI3RST_Pos (6) /*!< SYS_T::IPRST2: SPI3RST Position */ +#define SYS_IPRST2_SPI3RST_Msk (0x1ul << SYS_IPRST2_SPI3RST_Pos) /*!< SYS_T::IPRST2: SPI3RST Mask */ + +#define SYS_IPRST2_USCI0RST_Pos (8) /*!< SYS_T::IPRST2: USCI0RST Position */ +#define SYS_IPRST2_USCI0RST_Msk (0x1ul << SYS_IPRST2_USCI0RST_Pos) /*!< SYS_T::IPRST2: USCI0RST Mask */ + +#define SYS_IPRST2_USCI1RST_Pos (9) /*!< SYS_T::IPRST2: USCI1RST Position */ +#define SYS_IPRST2_USCI1RST_Msk (0x1ul << SYS_IPRST2_USCI1RST_Pos) /*!< SYS_T::IPRST2: USCI1RST Mask */ + +#define SYS_IPRST2_DACRST_Pos (12) /*!< SYS_T::IPRST2: DACRST Position */ +#define SYS_IPRST2_DACRST_Msk (0x1ul << SYS_IPRST2_DACRST_Pos) /*!< SYS_T::IPRST2: DACRST Mask */ + +#define SYS_IPRST2_EPWM0RST_Pos (16) /*!< SYS_T::IPRST2: EPWM0RST Position */ +#define SYS_IPRST2_EPWM0RST_Msk (0x1ul << SYS_IPRST2_EPWM0RST_Pos) /*!< SYS_T::IPRST2: EPWM0RST Mask */ + +#define SYS_IPRST2_EPWM1RST_Pos (17) /*!< SYS_T::IPRST2: EPWM1RST Position */ +#define SYS_IPRST2_EPWM1RST_Msk (0x1ul << SYS_IPRST2_EPWM1RST_Pos) /*!< SYS_T::IPRST2: EPWM1RST Mask */ + +#define SYS_IPRST2_BPWM0RST_Pos (18) /*!< SYS_T::IPRST2: BPWM0RST Position */ +#define SYS_IPRST2_BPWM0RST_Msk (0x1ul << SYS_IPRST2_BPWM0RST_Pos) /*!< SYS_T::IPRST2: BPWM0RST Mask */ + +#define SYS_IPRST2_BPWM1RST_Pos (19) /*!< SYS_T::IPRST2: BPWM1RST Position */ +#define SYS_IPRST2_BPWM1RST_Msk (0x1ul << SYS_IPRST2_BPWM1RST_Pos) /*!< SYS_T::IPRST2: BPWM1RST Mask */ + +#define SYS_IPRST2_QEI0RST_Pos (22) /*!< SYS_T::IPRST2: QEI0RST Position */ +#define SYS_IPRST2_QEI0RST_Msk (0x1ul << SYS_IPRST2_QEI0RST_Pos) /*!< SYS_T::IPRST2: QEI0RST Mask */ + +#define SYS_IPRST2_QEI1RST_Pos (23) /*!< SYS_T::IPRST2: QEI1RST Position */ +#define SYS_IPRST2_QEI1RST_Msk (0x1ul << SYS_IPRST2_QEI1RST_Pos) /*!< SYS_T::IPRST2: QEI1RST Mask */ + +#define SYS_IPRST2_ECAP0RST_Pos (26) /*!< SYS_T::IPRST2: ECAP0RST Position */ +#define SYS_IPRST2_ECAP0RST_Msk (0x1ul << SYS_IPRST2_ECAP0RST_Pos) /*!< SYS_T::IPRST2: ECAP0RST Mask */ + +#define SYS_IPRST2_ECAP1RST_Pos (27) /*!< SYS_T::IPRST2: ECAP1RST Position */ +#define SYS_IPRST2_ECAP1RST_Msk (0x1ul << SYS_IPRST2_ECAP1RST_Pos) /*!< SYS_T::IPRST2: ECAP1RST Mask */ + +#define SYS_IPRST2_CAN2RST_Pos (28) /*!< SYS_T::IPRST2: CAN2RST Position */ +#define SYS_IPRST2_CAN2RST_Msk (0x1ul << SYS_IPRST2_CAN2RST_Pos) /*!< SYS_T::IPRST2: CAN2RST Mask */ + +#define SYS_IPRST2_OPARST_Pos (30) /*!< SYS_T::IPRST2: OPARST Position */ +#define SYS_IPRST2_OPARST_Msk (0x1ul << SYS_IPRST2_OPARST_Pos) /*!< SYS_T::IPRST2: OPARST Mask */ + +#define SYS_IPRST2_EADC1RST_Pos (31) /*!< SYS_T::IPRST2: EADC1RST Position */ +#define SYS_IPRST2_EADC1RST_Msk (0x1ul << SYS_IPRST2_EADC1RST_Pos) /*!< SYS_T::IPRST2: EADC1RST Mask */ + +#define SYS_BODCTL_BODEN_Pos (0) /*!< SYS_T::BODCTL: BODEN Position */ +#define SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos) /*!< SYS_T::BODCTL: BODEN Mask */ + +#define SYS_BODCTL_BODRSTEN_Pos (3) /*!< SYS_T::BODCTL: BODRSTEN Position */ +#define SYS_BODCTL_BODRSTEN_Msk (0x1ul << SYS_BODCTL_BODRSTEN_Pos) /*!< SYS_T::BODCTL: BODRSTEN Mask */ + +#define SYS_BODCTL_BODIF_Pos (4) /*!< SYS_T::BODCTL: BODIF Position */ +#define SYS_BODCTL_BODIF_Msk (0x1ul << SYS_BODCTL_BODIF_Pos) /*!< SYS_T::BODCTL: BODIF Mask */ + +#define SYS_BODCTL_BODLPM_Pos (5) /*!< SYS_T::BODCTL: BODLPM Position */ +#define SYS_BODCTL_BODLPM_Msk (0x1ul << SYS_BODCTL_BODLPM_Pos) /*!< SYS_T::BODCTL: BODLPM Mask */ + +#define SYS_BODCTL_BODOUT_Pos (6) /*!< SYS_T::BODCTL: BODOUT Position */ +#define SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos) /*!< SYS_T::BODCTL: BODOUT Mask */ + +#define SYS_BODCTL_LVREN_Pos (7) /*!< SYS_T::BODCTL: LVREN Position */ +#define SYS_BODCTL_LVREN_Msk (0x1ul << SYS_BODCTL_LVREN_Pos) /*!< SYS_T::BODCTL: LVREN Mask */ + +#define SYS_BODCTL_BODDGSEL_Pos (8) /*!< SYS_T::BODCTL: BODDGSEL Position */ +#define SYS_BODCTL_BODDGSEL_Msk (0x7ul << SYS_BODCTL_BODDGSEL_Pos) /*!< SYS_T::BODCTL: BODDGSEL Mask */ + +#define SYS_BODCTL_LVRDGSEL_Pos (12) /*!< SYS_T::BODCTL: LVRDGSEL Position */ +#define SYS_BODCTL_LVRDGSEL_Msk (0x7ul << SYS_BODCTL_LVRDGSEL_Pos) /*!< SYS_T::BODCTL: LVRDGSEL Mask */ + +#define SYS_BODCTL_BODVL_Pos (16) /*!< SYS_T::BODCTL: BODVL Position */ +#define SYS_BODCTL_BODVL_Msk (0x7ul << SYS_BODCTL_BODVL_Pos) /*!< SYS_T::BODCTL: BODVL Mask */ + +#define SYS_IVSCTL_VTEMPEN_Pos (0) /*!< SYS_T::IVSCTL: VTEMPEN Position */ +#define SYS_IVSCTL_VTEMPEN_Msk (0x1ul << SYS_IVSCTL_VTEMPEN_Pos) /*!< SYS_T::IVSCTL: VTEMPEN Mask */ + +#define SYS_IVSCTL_VBATUGEN_Pos (1) /*!< SYS_T::IVSCTL: VBATUGEN Position */ +#define SYS_IVSCTL_VBATUGEN_Msk (0x1ul << SYS_IVSCTL_VBATUGEN_Pos) /*!< SYS_T::IVSCTL: VBATUGEN Mask */ + +#define SYS_PORCTL_POROFF_Pos (0) /*!< SYS_T::PORCTL: POROFF Position */ +#define SYS_PORCTL_POROFF_Msk (0xfffful << SYS_PORCTL_POROFF_Pos) /*!< SYS_T::PORCTL: POROFF Mask */ + +#define SYS_VREFCTL_VREFCTL_Pos (0) /*!< SYS_T::VREFCTL: VREFCTL Position */ +#define SYS_VREFCTL_VREFCTL_Msk (0x1ful << SYS_VREFCTL_VREFCTL_Pos) /*!< SYS_T::VREFCTL: VREFCTL Mask */ + +#define SYS_VREFCTL_PRELOAD_SEL_Pos (6) /*!< SYS_T::VREFCTL: PRELOAD_SEL Position */ +#define SYS_VREFCTL_PRELOAD_SEL_Msk (0x3ul << SYS_VREFCTL_PRELOAD_SEL_Pos) /*!< SYS_T::VREFCTL: PRELOAD_SEL Mask */ + +#define SYS_USBPHY_USBROLE_Pos (0) /*!< SYS_T::USBPHY: USBROLE Position */ +#define SYS_USBPHY_USBROLE_Msk (0x3ul << SYS_USBPHY_USBROLE_Pos) /*!< SYS_T::USBPHY: USBROLE Mask */ + +#define SYS_USBPHY_SBO_Pos (2) /*!< SYS_T::USBPHY: SBO Position */ +#define SYS_USBPHY_SBO_Msk (0x1ul << SYS_USBPHY_SBO_Pos) /*!< SYS_T::USBPHY: SBO Mask */ + +#define SYS_USBPHY_USBEN_Pos (8) /*!< SYS_T::USBPHY: USBEN Position */ +#define SYS_USBPHY_USBEN_Msk (0x1ul << SYS_USBPHY_USBEN_Pos) /*!< SYS_T::USBPHY: USBEN Mask */ + +#define SYS_USBPHY_HSUSBROLE_Pos (16) /*!< SYS_T::USBPHY: HSUSBROLE Position */ +#define SYS_USBPHY_HSUSBROLE_Msk (0x3ul << SYS_USBPHY_HSUSBROLE_Pos) /*!< SYS_T::USBPHY: HSUSBROLE Mask */ + +#define SYS_USBPHY_HSUSBEN_Pos (24) /*!< SYS_T::USBPHY: HSUSBEN Position */ +#define SYS_USBPHY_HSUSBEN_Msk (0x1ul << SYS_USBPHY_HSUSBEN_Pos) /*!< SYS_T::USBPHY: HSUSBEN Mask */ + +#define SYS_USBPHY_HSUSBACT_Pos (25) /*!< SYS_T::USBPHY: HSUSBACT Position */ +#define SYS_USBPHY_HSUSBACT_Msk (0x1ul << SYS_USBPHY_HSUSBACT_Pos) /*!< SYS_T::USBPHY: HSUSBACT Mask */ + +#define SYS_GPA_MFPL_PA0MFP_Pos (0) /*!< SYS_T::GPA_MFPL: PA0MFP Position */ +#define SYS_GPA_MFPL_PA0MFP_Msk (0xful << SYS_GPA_MFPL_PA0MFP_Pos) /*!< SYS_T::GPA_MFPL: PA0MFP Mask */ + +#define SYS_GPA_MFPL_PA1MFP_Pos (4) /*!< SYS_T::GPA_MFPL: PA1MFP Position */ +#define SYS_GPA_MFPL_PA1MFP_Msk (0xful << SYS_GPA_MFPL_PA1MFP_Pos) /*!< SYS_T::GPA_MFPL: PA1MFP Mask */ + +#define SYS_GPA_MFPL_PA2MFP_Pos (8) /*!< SYS_T::GPA_MFPL: PA2MFP Position */ +#define SYS_GPA_MFPL_PA2MFP_Msk (0xful << SYS_GPA_MFPL_PA2MFP_Pos) /*!< SYS_T::GPA_MFPL: PA2MFP Mask */ + +#define SYS_GPA_MFPL_PA3MFP_Pos (12) /*!< SYS_T::GPA_MFPL: PA3MFP Position */ +#define SYS_GPA_MFPL_PA3MFP_Msk (0xful << SYS_GPA_MFPL_PA3MFP_Pos) /*!< SYS_T::GPA_MFPL: PA3MFP Mask */ + +#define SYS_GPA_MFPL_PA4MFP_Pos (16) /*!< SYS_T::GPA_MFPL: PA4MFP Position */ +#define SYS_GPA_MFPL_PA4MFP_Msk (0xful << SYS_GPA_MFPL_PA4MFP_Pos) /*!< SYS_T::GPA_MFPL: PA4MFP Mask */ + +#define SYS_GPA_MFPL_PA5MFP_Pos (20) /*!< SYS_T::GPA_MFPL: PA5MFP Position */ +#define SYS_GPA_MFPL_PA5MFP_Msk (0xful << SYS_GPA_MFPL_PA5MFP_Pos) /*!< SYS_T::GPA_MFPL: PA5MFP Mask */ + +#define SYS_GPA_MFPL_PA6MFP_Pos (24) /*!< SYS_T::GPA_MFPL: PA6MFP Position */ +#define SYS_GPA_MFPL_PA6MFP_Msk (0xful << SYS_GPA_MFPL_PA6MFP_Pos) /*!< SYS_T::GPA_MFPL: PA6MFP Mask */ + +#define SYS_GPA_MFPL_PA7MFP_Pos (28) /*!< SYS_T::GPA_MFPL: PA7MFP Position */ +#define SYS_GPA_MFPL_PA7MFP_Msk (0xful << SYS_GPA_MFPL_PA7MFP_Pos) /*!< SYS_T::GPA_MFPL: PA7MFP Mask */ + +#define SYS_GPA_MFPH_PA8MFP_Pos (0) /*!< SYS_T::GPA_MFPH: PA8MFP Position */ +#define SYS_GPA_MFPH_PA8MFP_Msk (0xful << SYS_GPA_MFPH_PA8MFP_Pos) /*!< SYS_T::GPA_MFPH: PA8MFP Mask */ + +#define SYS_GPA_MFPH_PA9MFP_Pos (4) /*!< SYS_T::GPA_MFPH: PA9MFP Position */ +#define SYS_GPA_MFPH_PA9MFP_Msk (0xful << SYS_GPA_MFPH_PA9MFP_Pos) /*!< SYS_T::GPA_MFPH: PA9MFP Mask */ + +#define SYS_GPA_MFPH_PA10MFP_Pos (8) /*!< SYS_T::GPA_MFPH: PA10MFP Position */ +#define SYS_GPA_MFPH_PA10MFP_Msk (0xful << SYS_GPA_MFPH_PA10MFP_Pos) /*!< SYS_T::GPA_MFPH: PA10MFP Mask */ + +#define SYS_GPA_MFPH_PA11MFP_Pos (12) /*!< SYS_T::GPA_MFPH: PA11MFP Position */ +#define SYS_GPA_MFPH_PA11MFP_Msk (0xful << SYS_GPA_MFPH_PA11MFP_Pos) /*!< SYS_T::GPA_MFPH: PA11MFP Mask */ + +#define SYS_GPA_MFPH_PA12MFP_Pos (16) /*!< SYS_T::GPA_MFPH: PA12MFP Position */ +#define SYS_GPA_MFPH_PA12MFP_Msk (0xful << SYS_GPA_MFPH_PA12MFP_Pos) /*!< SYS_T::GPA_MFPH: PA12MFP Mask */ + +#define SYS_GPA_MFPH_PA13MFP_Pos (20) /*!< SYS_T::GPA_MFPH: PA13MFP Position */ +#define SYS_GPA_MFPH_PA13MFP_Msk (0xful << SYS_GPA_MFPH_PA13MFP_Pos) /*!< SYS_T::GPA_MFPH: PA13MFP Mask */ + +#define SYS_GPA_MFPH_PA14MFP_Pos (24) /*!< SYS_T::GPA_MFPH: PA14MFP Position */ +#define SYS_GPA_MFPH_PA14MFP_Msk (0xful << SYS_GPA_MFPH_PA14MFP_Pos) /*!< SYS_T::GPA_MFPH: PA14MFP Mask */ + +#define SYS_GPA_MFPH_PA15MFP_Pos (28) /*!< SYS_T::GPA_MFPH: PA15MFP Position */ +#define SYS_GPA_MFPH_PA15MFP_Msk (0xful << SYS_GPA_MFPH_PA15MFP_Pos) /*!< SYS_T::GPA_MFPH: PA15MFP Mask */ + +#define SYS_GPB_MFPL_PB0MFP_Pos (0) /*!< SYS_T::GPB_MFPL: PB0MFP Position */ +#define SYS_GPB_MFPL_PB0MFP_Msk (0xful << SYS_GPB_MFPL_PB0MFP_Pos) /*!< SYS_T::GPB_MFPL: PB0MFP Mask */ + +#define SYS_GPB_MFPL_PB1MFP_Pos (4) /*!< SYS_T::GPB_MFPL: PB1MFP Position */ +#define SYS_GPB_MFPL_PB1MFP_Msk (0xful << SYS_GPB_MFPL_PB1MFP_Pos) /*!< SYS_T::GPB_MFPL: PB1MFP Mask */ + +#define SYS_GPB_MFPL_PB2MFP_Pos (8) /*!< SYS_T::GPB_MFPL: PB2MFP Position */ +#define SYS_GPB_MFPL_PB2MFP_Msk (0xful << SYS_GPB_MFPL_PB2MFP_Pos) /*!< SYS_T::GPB_MFPL: PB2MFP Mask */ + +#define SYS_GPB_MFPL_PB3MFP_Pos (12) /*!< SYS_T::GPB_MFPL: PB3MFP Position */ +#define SYS_GPB_MFPL_PB3MFP_Msk (0xful << SYS_GPB_MFPL_PB3MFP_Pos) /*!< SYS_T::GPB_MFPL: PB3MFP Mask */ + +#define SYS_GPB_MFPL_PB4MFP_Pos (16) /*!< SYS_T::GPB_MFPL: PB4MFP Position */ +#define SYS_GPB_MFPL_PB4MFP_Msk (0xful << SYS_GPB_MFPL_PB4MFP_Pos) /*!< SYS_T::GPB_MFPL: PB4MFP Mask */ + +#define SYS_GPB_MFPL_PB5MFP_Pos (20) /*!< SYS_T::GPB_MFPL: PB5MFP Position */ +#define SYS_GPB_MFPL_PB5MFP_Msk (0xful << SYS_GPB_MFPL_PB5MFP_Pos) /*!< SYS_T::GPB_MFPL: PB5MFP Mask */ + +#define SYS_GPB_MFPL_PB6MFP_Pos (24) /*!< SYS_T::GPB_MFPL: PB6MFP Position */ +#define SYS_GPB_MFPL_PB6MFP_Msk (0xful << SYS_GPB_MFPL_PB6MFP_Pos) /*!< SYS_T::GPB_MFPL: PB6MFP Mask */ + +#define SYS_GPB_MFPL_PB7MFP_Pos (28) /*!< SYS_T::GPB_MFPL: PB7MFP Position */ +#define SYS_GPB_MFPL_PB7MFP_Msk (0xful << SYS_GPB_MFPL_PB7MFP_Pos) /*!< SYS_T::GPB_MFPL: PB7MFP Mask */ + +#define SYS_GPB_MFPH_PB8MFP_Pos (0) /*!< SYS_T::GPB_MFPH: PB8MFP Position */ +#define SYS_GPB_MFPH_PB8MFP_Msk (0xful << SYS_GPB_MFPH_PB8MFP_Pos) /*!< SYS_T::GPB_MFPH: PB8MFP Mask */ + +#define SYS_GPB_MFPH_PB9MFP_Pos (4) /*!< SYS_T::GPB_MFPH: PB9MFP Position */ +#define SYS_GPB_MFPH_PB9MFP_Msk (0xful << SYS_GPB_MFPH_PB9MFP_Pos) /*!< SYS_T::GPB_MFPH: PB9MFP Mask */ + +#define SYS_GPB_MFPH_PB10MFP_Pos (8) /*!< SYS_T::GPB_MFPH: PB10MFP Position */ +#define SYS_GPB_MFPH_PB10MFP_Msk (0xful << SYS_GPB_MFPH_PB10MFP_Pos) /*!< SYS_T::GPB_MFPH: PB10MFP Mask */ + +#define SYS_GPB_MFPH_PB11MFP_Pos (12) /*!< SYS_T::GPB_MFPH: PB11MFP Position */ +#define SYS_GPB_MFPH_PB11MFP_Msk (0xful << SYS_GPB_MFPH_PB11MFP_Pos) /*!< SYS_T::GPB_MFPH: PB11MFP Mask */ + +#define SYS_GPB_MFPH_PB12MFP_Pos (16) /*!< SYS_T::GPB_MFPH: PB12MFP Position */ +#define SYS_GPB_MFPH_PB12MFP_Msk (0xful << SYS_GPB_MFPH_PB12MFP_Pos) /*!< SYS_T::GPB_MFPH: PB12MFP Mask */ + +#define SYS_GPB_MFPH_PB13MFP_Pos (20) /*!< SYS_T::GPB_MFPH: PB13MFP Position */ +#define SYS_GPB_MFPH_PB13MFP_Msk (0xful << SYS_GPB_MFPH_PB13MFP_Pos) /*!< SYS_T::GPB_MFPH: PB13MFP Mask */ + +#define SYS_GPB_MFPH_PB14MFP_Pos (24) /*!< SYS_T::GPB_MFPH: PB14MFP Position */ +#define SYS_GPB_MFPH_PB14MFP_Msk (0xful << SYS_GPB_MFPH_PB14MFP_Pos) /*!< SYS_T::GPB_MFPH: PB14MFP Mask */ + +#define SYS_GPB_MFPH_PB15MFP_Pos (28) /*!< SYS_T::GPB_MFPH: PB15MFP Position */ +#define SYS_GPB_MFPH_PB15MFP_Msk (0xful << SYS_GPB_MFPH_PB15MFP_Pos) /*!< SYS_T::GPB_MFPH: PB15MFP Mask */ + +#define SYS_GPC_MFPL_PC0MFP_Pos (0) /*!< SYS_T::GPC_MFPL: PC0MFP Position */ +#define SYS_GPC_MFPL_PC0MFP_Msk (0xful << SYS_GPC_MFPL_PC0MFP_Pos) /*!< SYS_T::GPC_MFPL: PC0MFP Mask */ + +#define SYS_GPC_MFPL_PC1MFP_Pos (4) /*!< SYS_T::GPC_MFPL: PC1MFP Position */ +#define SYS_GPC_MFPL_PC1MFP_Msk (0xful << SYS_GPC_MFPL_PC1MFP_Pos) /*!< SYS_T::GPC_MFPL: PC1MFP Mask */ + +#define SYS_GPC_MFPL_PC2MFP_Pos (8) /*!< SYS_T::GPC_MFPL: PC2MFP Position */ +#define SYS_GPC_MFPL_PC2MFP_Msk (0xful << SYS_GPC_MFPL_PC2MFP_Pos) /*!< SYS_T::GPC_MFPL: PC2MFP Mask */ + +#define SYS_GPC_MFPL_PC3MFP_Pos (12) /*!< SYS_T::GPC_MFPL: PC3MFP Position */ +#define SYS_GPC_MFPL_PC3MFP_Msk (0xful << SYS_GPC_MFPL_PC3MFP_Pos) /*!< SYS_T::GPC_MFPL: PC3MFP Mask */ + +#define SYS_GPC_MFPL_PC4MFP_Pos (16) /*!< SYS_T::GPC_MFPL: PC4MFP Position */ +#define SYS_GPC_MFPL_PC4MFP_Msk (0xful << SYS_GPC_MFPL_PC4MFP_Pos) /*!< SYS_T::GPC_MFPL: PC4MFP Mask */ + +#define SYS_GPC_MFPL_PC5MFP_Pos (20) /*!< SYS_T::GPC_MFPL: PC5MFP Position */ +#define SYS_GPC_MFPL_PC5MFP_Msk (0xful << SYS_GPC_MFPL_PC5MFP_Pos) /*!< SYS_T::GPC_MFPL: PC5MFP Mask */ + +#define SYS_GPC_MFPL_PC6MFP_Pos (24) /*!< SYS_T::GPC_MFPL: PC6MFP Position */ +#define SYS_GPC_MFPL_PC6MFP_Msk (0xful << SYS_GPC_MFPL_PC6MFP_Pos) /*!< SYS_T::GPC_MFPL: PC6MFP Mask */ + +#define SYS_GPC_MFPL_PC7MFP_Pos (28) /*!< SYS_T::GPC_MFPL: PC7MFP Position */ +#define SYS_GPC_MFPL_PC7MFP_Msk (0xful << SYS_GPC_MFPL_PC7MFP_Pos) /*!< SYS_T::GPC_MFPL: PC7MFP Mask */ + +#define SYS_GPC_MFPH_PC8MFP_Pos (0) /*!< SYS_T::GPC_MFPH: PC8MFP Position */ +#define SYS_GPC_MFPH_PC8MFP_Msk (0xful << SYS_GPC_MFPH_PC8MFP_Pos) /*!< SYS_T::GPC_MFPH: PC8MFP Mask */ + +#define SYS_GPC_MFPH_PC9MFP_Pos (4) /*!< SYS_T::GPC_MFPH: PC9MFP Position */ +#define SYS_GPC_MFPH_PC9MFP_Msk (0xful << SYS_GPC_MFPH_PC9MFP_Pos) /*!< SYS_T::GPC_MFPH: PC9MFP Mask */ + +#define SYS_GPC_MFPH_PC10MFP_Pos (8) /*!< SYS_T::GPC_MFPH: PC10MFP Position */ +#define SYS_GPC_MFPH_PC10MFP_Msk (0xful << SYS_GPC_MFPH_PC10MFP_Pos) /*!< SYS_T::GPC_MFPH: PC10MFP Mask */ + +#define SYS_GPC_MFPH_PC11MFP_Pos (12) /*!< SYS_T::GPC_MFPH: PC11MFP Position */ +#define SYS_GPC_MFPH_PC11MFP_Msk (0xful << SYS_GPC_MFPH_PC11MFP_Pos) /*!< SYS_T::GPC_MFPH: PC11MFP Mask */ + +#define SYS_GPC_MFPH_PC12MFP_Pos (16) /*!< SYS_T::GPC_MFPH: PC12MFP Position */ +#define SYS_GPC_MFPH_PC12MFP_Msk (0xful << SYS_GPC_MFPH_PC12MFP_Pos) /*!< SYS_T::GPC_MFPH: PC12MFP Mask */ + +#define SYS_GPC_MFPH_PC13MFP_Pos (20) /*!< SYS_T::GPC_MFPH: PC13MFP Position */ +#define SYS_GPC_MFPH_PC13MFP_Msk (0xful << SYS_GPC_MFPH_PC13MFP_Pos) /*!< SYS_T::GPC_MFPH: PC13MFP Mask */ + +#define SYS_GPC_MFPH_PC14MFP_Pos (24) /*!< SYS_T::GPC_MFPH: PC14MFP Position */ +#define SYS_GPC_MFPH_PC14MFP_Msk (0xful << SYS_GPC_MFPH_PC14MFP_Pos) /*!< SYS_T::GPC_MFPH: PC14MFP Mask */ + +#define SYS_GPC_MFPH_PC15MFP_Pos (28) /*!< SYS_T::GPC_MFPH: PC15MFP Position */ +#define SYS_GPC_MFPH_PC15MFP_Msk (0xful << SYS_GPC_MFPH_PC15MFP_Pos) /*!< SYS_T::GPC_MFPH: PC15MFP Mask */ + +#define SYS_GPD_MFPL_PD0MFP_Pos (0) /*!< SYS_T::GPD_MFPL: PD0MFP Position */ +#define SYS_GPD_MFPL_PD0MFP_Msk (0xful << SYS_GPD_MFPL_PD0MFP_Pos) /*!< SYS_T::GPD_MFPL: PD0MFP Mask */ + +#define SYS_GPD_MFPL_PD1MFP_Pos (4) /*!< SYS_T::GPD_MFPL: PD1MFP Position */ +#define SYS_GPD_MFPL_PD1MFP_Msk (0xful << SYS_GPD_MFPL_PD1MFP_Pos) /*!< SYS_T::GPD_MFPL: PD1MFP Mask */ + +#define SYS_GPD_MFPL_PD2MFP_Pos (8) /*!< SYS_T::GPD_MFPL: PD2MFP Position */ +#define SYS_GPD_MFPL_PD2MFP_Msk (0xful << SYS_GPD_MFPL_PD2MFP_Pos) /*!< SYS_T::GPD_MFPL: PD2MFP Mask */ + +#define SYS_GPD_MFPL_PD3MFP_Pos (12) /*!< SYS_T::GPD_MFPL: PD3MFP Position */ +#define SYS_GPD_MFPL_PD3MFP_Msk (0xful << SYS_GPD_MFPL_PD3MFP_Pos) /*!< SYS_T::GPD_MFPL: PD3MFP Mask */ + +#define SYS_GPD_MFPL_PD4MFP_Pos (16) /*!< SYS_T::GPD_MFPL: PD4MFP Position */ +#define SYS_GPD_MFPL_PD4MFP_Msk (0xful << SYS_GPD_MFPL_PD4MFP_Pos) /*!< SYS_T::GPD_MFPL: PD4MFP Mask */ + +#define SYS_GPD_MFPL_PD5MFP_Pos (20) /*!< SYS_T::GPD_MFPL: PD5MFP Position */ +#define SYS_GPD_MFPL_PD5MFP_Msk (0xful << SYS_GPD_MFPL_PD5MFP_Pos) /*!< SYS_T::GPD_MFPL: PD5MFP Mask */ + +#define SYS_GPD_MFPL_PD6MFP_Pos (24) /*!< SYS_T::GPD_MFPL: PD6MFP Position */ +#define SYS_GPD_MFPL_PD6MFP_Msk (0xful << SYS_GPD_MFPL_PD6MFP_Pos) /*!< SYS_T::GPD_MFPL: PD6MFP Mask */ + +#define SYS_GPD_MFPL_PD7MFP_Pos (28) /*!< SYS_T::GPD_MFPL: PD7MFP Position */ +#define SYS_GPD_MFPL_PD7MFP_Msk (0xful << SYS_GPD_MFPL_PD7MFP_Pos) /*!< SYS_T::GPD_MFPL: PD7MFP Mask */ + +#define SYS_GPD_MFPH_PD8MFP_Pos (0) /*!< SYS_T::GPD_MFPH: PD8MFP Position */ +#define SYS_GPD_MFPH_PD8MFP_Msk (0xful << SYS_GPD_MFPH_PD8MFP_Pos) /*!< SYS_T::GPD_MFPH: PD8MFP Mask */ + +#define SYS_GPD_MFPH_PD9MFP_Pos (4) /*!< SYS_T::GPD_MFPH: PD9MFP Position */ +#define SYS_GPD_MFPH_PD9MFP_Msk (0xful << SYS_GPD_MFPH_PD9MFP_Pos) /*!< SYS_T::GPD_MFPH: PD9MFP Mask */ + +#define SYS_GPD_MFPH_PD10MFP_Pos (8) /*!< SYS_T::GPD_MFPH: PD10MFP Position */ +#define SYS_GPD_MFPH_PD10MFP_Msk (0xful << SYS_GPD_MFPH_PD10MFP_Pos) /*!< SYS_T::GPD_MFPH: PD10MFP Mask */ + +#define SYS_GPD_MFPH_PD11MFP_Pos (12) /*!< SYS_T::GPD_MFPH: PD11MFP Position */ +#define SYS_GPD_MFPH_PD11MFP_Msk (0xful << SYS_GPD_MFPH_PD11MFP_Pos) /*!< SYS_T::GPD_MFPH: PD11MFP Mask */ + +#define SYS_GPD_MFPH_PD12MFP_Pos (16) /*!< SYS_T::GPD_MFPH: PD12MFP Position */ +#define SYS_GPD_MFPH_PD12MFP_Msk (0xful << SYS_GPD_MFPH_PD12MFP_Pos) /*!< SYS_T::GPD_MFPH: PD12MFP Mask */ + +#define SYS_GPD_MFPH_PD13MFP_Pos (20) /*!< SYS_T::GPD_MFPH: PD13MFP Position */ +#define SYS_GPD_MFPH_PD13MFP_Msk (0xful << SYS_GPD_MFPH_PD13MFP_Pos) /*!< SYS_T::GPD_MFPH: PD13MFP Mask */ + +#define SYS_GPD_MFPH_PD14MFP_Pos (24) /*!< SYS_T::GPD_MFPH: PD14MFP Position */ +#define SYS_GPD_MFPH_PD14MFP_Msk (0xful << SYS_GPD_MFPH_PD14MFP_Pos) /*!< SYS_T::GPD_MFPH: PD14MFP Mask */ + +#define SYS_GPD_MFPH_PD15MFP_Pos (28) /*!< SYS_T::GPD_MFPH: PD15MFP Position */ +#define SYS_GPD_MFPH_PD15MFP_Msk (0xful << SYS_GPD_MFPH_PD15MFP_Pos) /*!< SYS_T::GPD_MFPH: PD15MFP Mask */ + +#define SYS_GPE_MFPL_PE0MFP_Pos (0) /*!< SYS_T::GPE_MFPL: PE0MFP Position */ +#define SYS_GPE_MFPL_PE0MFP_Msk (0xful << SYS_GPE_MFPL_PE0MFP_Pos) /*!< SYS_T::GPE_MFPL: PE0MFP Mask */ + +#define SYS_GPE_MFPL_PE1MFP_Pos (4) /*!< SYS_T::GPE_MFPL: PE1MFP Position */ +#define SYS_GPE_MFPL_PE1MFP_Msk (0xful << SYS_GPE_MFPL_PE1MFP_Pos) /*!< SYS_T::GPE_MFPL: PE1MFP Mask */ + +#define SYS_GPE_MFPL_PE2MFP_Pos (8) /*!< SYS_T::GPE_MFPL: PE2MFP Position */ +#define SYS_GPE_MFPL_PE2MFP_Msk (0xful << SYS_GPE_MFPL_PE2MFP_Pos) /*!< SYS_T::GPE_MFPL: PE2MFP Mask */ + +#define SYS_GPE_MFPL_PE3MFP_Pos (12) /*!< SYS_T::GPE_MFPL: PE3MFP Position */ +#define SYS_GPE_MFPL_PE3MFP_Msk (0xful << SYS_GPE_MFPL_PE3MFP_Pos) /*!< SYS_T::GPE_MFPL: PE3MFP Mask */ + +#define SYS_GPE_MFPL_PE4MFP_Pos (16) /*!< SYS_T::GPE_MFPL: PE4MFP Position */ +#define SYS_GPE_MFPL_PE4MFP_Msk (0xful << SYS_GPE_MFPL_PE4MFP_Pos) /*!< SYS_T::GPE_MFPL: PE4MFP Mask */ + +#define SYS_GPE_MFPL_PE5MFP_Pos (20) /*!< SYS_T::GPE_MFPL: PE5MFP Position */ +#define SYS_GPE_MFPL_PE5MFP_Msk (0xful << SYS_GPE_MFPL_PE5MFP_Pos) /*!< SYS_T::GPE_MFPL: PE5MFP Mask */ + +#define SYS_GPE_MFPL_PE6MFP_Pos (24) /*!< SYS_T::GPE_MFPL: PE6MFP Position */ +#define SYS_GPE_MFPL_PE6MFP_Msk (0xful << SYS_GPE_MFPL_PE6MFP_Pos) /*!< SYS_T::GPE_MFPL: PE6MFP Mask */ + +#define SYS_GPE_MFPL_PE7MFP_Pos (28) /*!< SYS_T::GPE_MFPL: PE7MFP Position */ +#define SYS_GPE_MFPL_PE7MFP_Msk (0xful << SYS_GPE_MFPL_PE7MFP_Pos) /*!< SYS_T::GPE_MFPL: PE7MFP Mask */ + +#define SYS_GPE_MFPH_PE8MFP_Pos (0) /*!< SYS_T::GPE_MFPH: PE8MFP Position */ +#define SYS_GPE_MFPH_PE8MFP_Msk (0xful << SYS_GPE_MFPH_PE8MFP_Pos) /*!< SYS_T::GPE_MFPH: PE8MFP Mask */ + +#define SYS_GPE_MFPH_PE9MFP_Pos (4) /*!< SYS_T::GPE_MFPH: PE9MFP Position */ +#define SYS_GPE_MFPH_PE9MFP_Msk (0xful << SYS_GPE_MFPH_PE9MFP_Pos) /*!< SYS_T::GPE_MFPH: PE9MFP Mask */ + +#define SYS_GPE_MFPH_PE10MFP_Pos (8) /*!< SYS_T::GPE_MFPH: PE10MFP Position */ +#define SYS_GPE_MFPH_PE10MFP_Msk (0xful << SYS_GPE_MFPH_PE10MFP_Pos) /*!< SYS_T::GPE_MFPH: PE10MFP Mask */ + +#define SYS_GPE_MFPH_PE11MFP_Pos (12) /*!< SYS_T::GPE_MFPH: PE11MFP Position */ +#define SYS_GPE_MFPH_PE11MFP_Msk (0xful << SYS_GPE_MFPH_PE11MFP_Pos) /*!< SYS_T::GPE_MFPH: PE11MFP Mask */ + +#define SYS_GPE_MFPH_PE12MFP_Pos (16) /*!< SYS_T::GPE_MFPH: PE12MFP Position */ +#define SYS_GPE_MFPH_PE12MFP_Msk (0xful << SYS_GPE_MFPH_PE12MFP_Pos) /*!< SYS_T::GPE_MFPH: PE12MFP Mask */ + +#define SYS_GPE_MFPH_PE13MFP_Pos (20) /*!< SYS_T::GPE_MFPH: PE13MFP Position */ +#define SYS_GPE_MFPH_PE13MFP_Msk (0xful << SYS_GPE_MFPH_PE13MFP_Pos) /*!< SYS_T::GPE_MFPH: PE13MFP Mask */ + +#define SYS_GPE_MFPH_PE14MFP_Pos (24) /*!< SYS_T::GPE_MFPH: PE14MFP Position */ +#define SYS_GPE_MFPH_PE14MFP_Msk (0xful << SYS_GPE_MFPH_PE14MFP_Pos) /*!< SYS_T::GPE_MFPH: PE14MFP Mask */ + +#define SYS_GPE_MFPH_PE15MFP_Pos (28) /*!< SYS_T::GPE_MFPH: PE15MFP Position */ +#define SYS_GPE_MFPH_PE15MFP_Msk (0xful << SYS_GPE_MFPH_PE15MFP_Pos) /*!< SYS_T::GPE_MFPH: PE15MFP Mask */ + +#define SYS_GPF_MFPL_PF0MFP_Pos (0) /*!< SYS_T::GPF_MFPL: PF0MFP Position */ +#define SYS_GPF_MFPL_PF0MFP_Msk (0xful << SYS_GPF_MFPL_PF0MFP_Pos) /*!< SYS_T::GPF_MFPL: PF0MFP Mask */ + +#define SYS_GPF_MFPL_PF1MFP_Pos (4) /*!< SYS_T::GPF_MFPL: PF1MFP Position */ +#define SYS_GPF_MFPL_PF1MFP_Msk (0xful << SYS_GPF_MFPL_PF1MFP_Pos) /*!< SYS_T::GPF_MFPL: PF1MFP Mask */ + +#define SYS_GPF_MFPL_PF2MFP_Pos (8) /*!< SYS_T::GPF_MFPL: PF2MFP Position */ +#define SYS_GPF_MFPL_PF2MFP_Msk (0xful << SYS_GPF_MFPL_PF2MFP_Pos) /*!< SYS_T::GPF_MFPL: PF2MFP Mask */ + +#define SYS_GPF_MFPL_PF3MFP_Pos (12) /*!< SYS_T::GPF_MFPL: PF3MFP Position */ +#define SYS_GPF_MFPL_PF3MFP_Msk (0xful << SYS_GPF_MFPL_PF3MFP_Pos) /*!< SYS_T::GPF_MFPL: PF3MFP Mask */ + +#define SYS_GPF_MFPL_PF4MFP_Pos (16) /*!< SYS_T::GPF_MFPL: PF4MFP Position */ +#define SYS_GPF_MFPL_PF4MFP_Msk (0xful << SYS_GPF_MFPL_PF4MFP_Pos) /*!< SYS_T::GPF_MFPL: PF4MFP Mask */ + +#define SYS_GPF_MFPL_PF5MFP_Pos (20) /*!< SYS_T::GPF_MFPL: PF5MFP Position */ +#define SYS_GPF_MFPL_PF5MFP_Msk (0xful << SYS_GPF_MFPL_PF5MFP_Pos) /*!< SYS_T::GPF_MFPL: PF5MFP Mask */ + +#define SYS_GPF_MFPL_PF6MFP_Pos (24) /*!< SYS_T::GPF_MFPL: PF6MFP Position */ +#define SYS_GPF_MFPL_PF6MFP_Msk (0xful << SYS_GPF_MFPL_PF6MFP_Pos) /*!< SYS_T::GPF_MFPL: PF6MFP Mask */ + +#define SYS_GPF_MFPL_PF7MFP_Pos (28) /*!< SYS_T::GPF_MFPL: PF7MFP Position */ +#define SYS_GPF_MFPL_PF7MFP_Msk (0xful << SYS_GPF_MFPL_PF7MFP_Pos) /*!< SYS_T::GPF_MFPL: PF7MFP Mask */ + +#define SYS_GPF_MFPH_PF8MFP_Pos (0) /*!< SYS_T::GPF_MFPH: PF8MFP Position */ +#define SYS_GPF_MFPH_PF8MFP_Msk (0xful << SYS_GPF_MFPH_PF8MFP_Pos) /*!< SYS_T::GPF_MFPH: PF8MFP Mask */ + +#define SYS_GPF_MFPH_PF9MFP_Pos (4) /*!< SYS_T::GPF_MFPH: PF9MFP Position */ +#define SYS_GPF_MFPH_PF9MFP_Msk (0xful << SYS_GPF_MFPH_PF9MFP_Pos) /*!< SYS_T::GPF_MFPH: PF9MFP Mask */ + +#define SYS_GPF_MFPH_PF10MFP_Pos (8) /*!< SYS_T::GPF_MFPH: PF10MFP Position */ +#define SYS_GPF_MFPH_PF10MFP_Msk (0xful << SYS_GPF_MFPH_PF10MFP_Pos) /*!< SYS_T::GPF_MFPH: PF10MFP Mask */ + +#define SYS_GPF_MFPH_PF11MFP_Pos (12) /*!< SYS_T::GPF_MFPH: PF11MFP Position */ +#define SYS_GPF_MFPH_PF11MFP_Msk (0xful << SYS_GPF_MFPH_PF11MFP_Pos) /*!< SYS_T::GPF_MFPH: PF11MFP Mask */ + +#define SYS_GPF_MFPH_PF12MFP_Pos (16) /*!< SYS_T::GPF_MFPH: PF12MFP Position */ +#define SYS_GPF_MFPH_PF12MFP_Msk (0xful << SYS_GPF_MFPH_PF12MFP_Pos) /*!< SYS_T::GPF_MFPH: PF12MFP Mask */ + +#define SYS_GPF_MFPH_PF13MFP_Pos (20) /*!< SYS_T::GPF_MFPH: PF13MFP Position */ +#define SYS_GPF_MFPH_PF13MFP_Msk (0xful << SYS_GPF_MFPH_PF13MFP_Pos) /*!< SYS_T::GPF_MFPH: PF13MFP Mask */ + +#define SYS_GPF_MFPH_PF14MFP_Pos (24) /*!< SYS_T::GPF_MFPH: PF14MFP Position */ +#define SYS_GPF_MFPH_PF14MFP_Msk (0xful << SYS_GPF_MFPH_PF14MFP_Pos) /*!< SYS_T::GPF_MFPH: PF14MFP Mask */ + +#define SYS_GPF_MFPH_PF15MFP_Pos (28) /*!< SYS_T::GPF_MFPH: PF15MFP Position */ +#define SYS_GPF_MFPH_PF15MFP_Msk (0xful << SYS_GPF_MFPH_PF15MFP_Pos) /*!< SYS_T::GPF_MFPH: PF15MFP Mask */ + +#define SYS_GPG_MFPL_PG0MFP_Pos (0) /*!< SYS_T::GPG_MFPL: PG0MFP Position */ +#define SYS_GPG_MFPL_PG0MFP_Msk (0xful << SYS_GPG_MFPL_PG0MFP_Pos) /*!< SYS_T::GPG_MFPL: PG0MFP Mask */ + +#define SYS_GPG_MFPL_PG1MFP_Pos (4) /*!< SYS_T::GPG_MFPL: PG1MFP Position */ +#define SYS_GPG_MFPL_PG1MFP_Msk (0xful << SYS_GPG_MFPL_PG1MFP_Pos) /*!< SYS_T::GPG_MFPL: PG1MFP Mask */ + +#define SYS_GPG_MFPL_PG2MFP_Pos (8) /*!< SYS_T::GPG_MFPL: PG2MFP Position */ +#define SYS_GPG_MFPL_PG2MFP_Msk (0xful << SYS_GPG_MFPL_PG2MFP_Pos) /*!< SYS_T::GPG_MFPL: PG2MFP Mask */ + +#define SYS_GPG_MFPL_PG3MFP_Pos (12) /*!< SYS_T::GPG_MFPL: PG3MFP Position */ +#define SYS_GPG_MFPL_PG3MFP_Msk (0xful << SYS_GPG_MFPL_PG3MFP_Pos) /*!< SYS_T::GPG_MFPL: PG3MFP Mask */ + +#define SYS_GPG_MFPL_PG4MFP_Pos (16) /*!< SYS_T::GPG_MFPL: PG4MFP Position */ +#define SYS_GPG_MFPL_PG4MFP_Msk (0xful << SYS_GPG_MFPL_PG4MFP_Pos) /*!< SYS_T::GPG_MFPL: PG4MFP Mask */ + +#define SYS_GPG_MFPL_PG5MFP_Pos (20) /*!< SYS_T::GPG_MFPL: PG5MFP Position */ +#define SYS_GPG_MFPL_PG5MFP_Msk (0xful << SYS_GPG_MFPL_PG5MFP_Pos) /*!< SYS_T::GPG_MFPL: PG5MFP Mask */ + +#define SYS_GPG_MFPL_PG6MFP_Pos (24) /*!< SYS_T::GPG_MFPL: PG6MFP Position */ +#define SYS_GPG_MFPL_PG6MFP_Msk (0xful << SYS_GPG_MFPL_PG6MFP_Pos) /*!< SYS_T::GPG_MFPL: PG6MFP Mask */ + +#define SYS_GPG_MFPL_PG7MFP_Pos (28) /*!< SYS_T::GPG_MFPL: PG7MFP Position */ +#define SYS_GPG_MFPL_PG7MFP_Msk (0xful << SYS_GPG_MFPL_PG7MFP_Pos) /*!< SYS_T::GPG_MFPL: PG7MFP Mask */ + +#define SYS_GPG_MFPH_PG8MFP_Pos (0) /*!< SYS_T::GPG_MFPH: PG8MFP Position */ +#define SYS_GPG_MFPH_PG8MFP_Msk (0xful << SYS_GPG_MFPH_PG8MFP_Pos) /*!< SYS_T::GPG_MFPH: PG8MFP Mask */ + +#define SYS_GPG_MFPH_PG9MFP_Pos (4) /*!< SYS_T::GPG_MFPH: PG9MFP Position */ +#define SYS_GPG_MFPH_PG9MFP_Msk (0xful << SYS_GPG_MFPH_PG9MFP_Pos) /*!< SYS_T::GPG_MFPH: PG9MFP Mask */ + +#define SYS_GPG_MFPH_PG10MFP_Pos (8) /*!< SYS_T::GPG_MFPH: PG10MFP Position */ +#define SYS_GPG_MFPH_PG10MFP_Msk (0xful << SYS_GPG_MFPH_PG10MFP_Pos) /*!< SYS_T::GPG_MFPH: PG10MFP Mask */ + +#define SYS_GPG_MFPH_PG11MFP_Pos (12) /*!< SYS_T::GPG_MFPH: PG11MFP Position */ +#define SYS_GPG_MFPH_PG11MFP_Msk (0xful << SYS_GPG_MFPH_PG11MFP_Pos) /*!< SYS_T::GPG_MFPH: PG11MFP Mask */ + +#define SYS_GPG_MFPH_PG12MFP_Pos (16) /*!< SYS_T::GPG_MFPH: PG12MFP Position */ +#define SYS_GPG_MFPH_PG12MFP_Msk (0xful << SYS_GPG_MFPH_PG12MFP_Pos) /*!< SYS_T::GPG_MFPH: PG12MFP Mask */ + +#define SYS_GPG_MFPH_PG13MFP_Pos (20) /*!< SYS_T::GPG_MFPH: PG13MFP Position */ +#define SYS_GPG_MFPH_PG13MFP_Msk (0xful << SYS_GPG_MFPH_PG13MFP_Pos) /*!< SYS_T::GPG_MFPH: PG13MFP Mask */ + +#define SYS_GPG_MFPH_PG14MFP_Pos (24) /*!< SYS_T::GPG_MFPH: PG14MFP Position */ +#define SYS_GPG_MFPH_PG14MFP_Msk (0xful << SYS_GPG_MFPH_PG14MFP_Pos) /*!< SYS_T::GPG_MFPH: PG14MFP Mask */ + +#define SYS_GPG_MFPH_PG15MFP_Pos (28) /*!< SYS_T::GPG_MFPH: PG15MFP Position */ +#define SYS_GPG_MFPH_PG15MFP_Msk (0xful << SYS_GPG_MFPH_PG15MFP_Pos) /*!< SYS_T::GPG_MFPH: PG15MFP Mask */ + +#define SYS_GPH_MFPL_PH0MFP_Pos (0) /*!< SYS_T::GPH_MFPL: PH0MFP Position */ +#define SYS_GPH_MFPL_PH0MFP_Msk (0xful << SYS_GPH_MFPL_PH0MFP_Pos) /*!< SYS_T::GPH_MFPL: PH0MFP Mask */ + +#define SYS_GPH_MFPL_PH1MFP_Pos (4) /*!< SYS_T::GPH_MFPL: PH1MFP Position */ +#define SYS_GPH_MFPL_PH1MFP_Msk (0xful << SYS_GPH_MFPL_PH1MFP_Pos) /*!< SYS_T::GPH_MFPL: PH1MFP Mask */ + +#define SYS_GPH_MFPL_PH2MFP_Pos (8) /*!< SYS_T::GPH_MFPL: PH2MFP Position */ +#define SYS_GPH_MFPL_PH2MFP_Msk (0xful << SYS_GPH_MFPL_PH2MFP_Pos) /*!< SYS_T::GPH_MFPL: PH2MFP Mask */ + +#define SYS_GPH_MFPL_PH3MFP_Pos (12) /*!< SYS_T::GPH_MFPL: PH3MFP Position */ +#define SYS_GPH_MFPL_PH3MFP_Msk (0xful << SYS_GPH_MFPL_PH3MFP_Pos) /*!< SYS_T::GPH_MFPL: PH3MFP Mask */ + +#define SYS_GPH_MFPL_PH4MFP_Pos (16) /*!< SYS_T::GPH_MFPL: PH4MFP Position */ +#define SYS_GPH_MFPL_PH4MFP_Msk (0xful << SYS_GPH_MFPL_PH4MFP_Pos) /*!< SYS_T::GPH_MFPL: PH4MFP Mask */ + +#define SYS_GPH_MFPL_PH5MFP_Pos (20) /*!< SYS_T::GPH_MFPL: PH5MFP Position */ +#define SYS_GPH_MFPL_PH5MFP_Msk (0xful << SYS_GPH_MFPL_PH5MFP_Pos) /*!< SYS_T::GPH_MFPL: PH5MFP Mask */ + +#define SYS_GPH_MFPL_PH6MFP_Pos (24) /*!< SYS_T::GPH_MFPL: PH6MFP Position */ +#define SYS_GPH_MFPL_PH6MFP_Msk (0xful << SYS_GPH_MFPL_PH6MFP_Pos) /*!< SYS_T::GPH_MFPL: PH6MFP Mask */ + +#define SYS_GPH_MFPL_PH7MFP_Pos (28) /*!< SYS_T::GPH_MFPL: PH7MFP Position */ +#define SYS_GPH_MFPL_PH7MFP_Msk (0xful << SYS_GPH_MFPL_PH7MFP_Pos) /*!< SYS_T::GPH_MFPL: PH7MFP Mask */ + +#define SYS_GPH_MFPH_PH8MFP_Pos (0) /*!< SYS_T::GPH_MFPH: PH8MFP Position */ +#define SYS_GPH_MFPH_PH8MFP_Msk (0xful << SYS_GPH_MFPH_PH8MFP_Pos) /*!< SYS_T::GPH_MFPH: PH8MFP Mask */ + +#define SYS_GPH_MFPH_PH9MFP_Pos (4) /*!< SYS_T::GPH_MFPH: PH9MFP Position */ +#define SYS_GPH_MFPH_PH9MFP_Msk (0xful << SYS_GPH_MFPH_PH9MFP_Pos) /*!< SYS_T::GPH_MFPH: PH9MFP Mask */ + +#define SYS_GPH_MFPH_PH10MFP_Pos (8) /*!< SYS_T::GPH_MFPH: PH10MFP Position */ +#define SYS_GPH_MFPH_PH10MFP_Msk (0xful << SYS_GPH_MFPH_PH10MFP_Pos) /*!< SYS_T::GPH_MFPH: PH10MFP Mask */ + +#define SYS_GPH_MFPH_PH11MFP_Pos (12) /*!< SYS_T::GPH_MFPH: PH11MFP Position */ +#define SYS_GPH_MFPH_PH11MFP_Msk (0xful << SYS_GPH_MFPH_PH11MFP_Pos) /*!< SYS_T::GPH_MFPH: PH11MFP Mask */ + +#define SYS_GPH_MFPH_PH12MFP_Pos (16) /*!< SYS_T::GPH_MFPH: PH12MFP Position */ +#define SYS_GPH_MFPH_PH12MFP_Msk (0xful << SYS_GPH_MFPH_PH12MFP_Pos) /*!< SYS_T::GPH_MFPH: PH12MFP Mask */ + +#define SYS_GPH_MFPH_PH13MFP_Pos (20) /*!< SYS_T::GPH_MFPH: PH13MFP Position */ +#define SYS_GPH_MFPH_PH13MFP_Msk (0xful << SYS_GPH_MFPH_PH13MFP_Pos) /*!< SYS_T::GPH_MFPH: PH13MFP Mask */ + +#define SYS_GPH_MFPH_PH14MFP_Pos (24) /*!< SYS_T::GPH_MFPH: PH14MFP Position */ +#define SYS_GPH_MFPH_PH14MFP_Msk (0xful << SYS_GPH_MFPH_PH14MFP_Pos) /*!< SYS_T::GPH_MFPH: PH14MFP Mask */ + +#define SYS_GPH_MFPH_PH15MFP_Pos (28) /*!< SYS_T::GPH_MFPH: PH15MFP Position */ +#define SYS_GPH_MFPH_PH15MFP_Msk (0xful << SYS_GPH_MFPH_PH15MFP_Pos) /*!< SYS_T::GPH_MFPH: PH15MFP Mask */ + +#define SYS_GPA_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPA_MFOS: MFOS0 Position */ +#define SYS_GPA_MFOS_MFOS0_Msk (0x1ul << SYS_GPA_MFOS_MFOS0_Pos) /*!< SYS_T::GPA_MFOS: MFOS0 Mask */ + +#define SYS_GPA_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPA_MFOS: MFOS1 Position */ +#define SYS_GPA_MFOS_MFOS1_Msk (0x1ul << SYS_GPA_MFOS_MFOS1_Pos) /*!< SYS_T::GPA_MFOS: MFOS1 Mask */ + +#define SYS_GPA_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPA_MFOS: MFOS2 Position */ +#define SYS_GPA_MFOS_MFOS2_Msk (0x1ul << SYS_GPA_MFOS_MFOS2_Pos) /*!< SYS_T::GPA_MFOS: MFOS2 Mask */ + +#define SYS_GPA_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPA_MFOS: MFOS3 Position */ +#define SYS_GPA_MFOS_MFOS3_Msk (0x1ul << SYS_GPA_MFOS_MFOS3_Pos) /*!< SYS_T::GPA_MFOS: MFOS3 Mask */ + +#define SYS_GPA_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPA_MFOS: MFOS4 Position */ +#define SYS_GPA_MFOS_MFOS4_Msk (0x1ul << SYS_GPA_MFOS_MFOS4_Pos) /*!< SYS_T::GPA_MFOS: MFOS4 Mask */ + +#define SYS_GPA_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPA_MFOS: MFOS5 Position */ +#define SYS_GPA_MFOS_MFOS5_Msk (0x1ul << SYS_GPA_MFOS_MFOS5_Pos) /*!< SYS_T::GPA_MFOS: MFOS5 Mask */ + +#define SYS_GPA_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPA_MFOS: MFOS6 Position */ +#define SYS_GPA_MFOS_MFOS6_Msk (0x1ul << SYS_GPA_MFOS_MFOS6_Pos) /*!< SYS_T::GPA_MFOS: MFOS6 Mask */ + +#define SYS_GPA_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPA_MFOS: MFOS7 Position */ +#define SYS_GPA_MFOS_MFOS7_Msk (0x1ul << SYS_GPA_MFOS_MFOS7_Pos) /*!< SYS_T::GPA_MFOS: MFOS7 Mask */ + +#define SYS_GPA_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPA_MFOS: MFOS8 Position */ +#define SYS_GPA_MFOS_MFOS8_Msk (0x1ul << SYS_GPA_MFOS_MFOS8_Pos) /*!< SYS_T::GPA_MFOS: MFOS8 Mask */ + +#define SYS_GPA_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPA_MFOS: MFOS9 Position */ +#define SYS_GPA_MFOS_MFOS9_Msk (0x1ul << SYS_GPA_MFOS_MFOS9_Pos) /*!< SYS_T::GPA_MFOS: MFOS9 Mask */ + +#define SYS_GPA_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPA_MFOS: MFOS10 Position */ +#define SYS_GPA_MFOS_MFOS10_Msk (0x1ul << SYS_GPA_MFOS_MFOS10_Pos) /*!< SYS_T::GPA_MFOS: MFOS10 Mask */ + +#define SYS_GPA_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPA_MFOS: MFOS11 Position */ +#define SYS_GPA_MFOS_MFOS11_Msk (0x1ul << SYS_GPA_MFOS_MFOS11_Pos) /*!< SYS_T::GPA_MFOS: MFOS11 Mask */ + +#define SYS_GPA_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPA_MFOS: MFOS12 Position */ +#define SYS_GPA_MFOS_MFOS12_Msk (0x1ul << SYS_GPA_MFOS_MFOS12_Pos) /*!< SYS_T::GPA_MFOS: MFOS12 Mask */ + +#define SYS_GPA_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPA_MFOS: MFOS13 Position */ +#define SYS_GPA_MFOS_MFOS13_Msk (0x1ul << SYS_GPA_MFOS_MFOS13_Pos) /*!< SYS_T::GPA_MFOS: MFOS13 Mask */ + +#define SYS_GPA_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPA_MFOS: MFOS14 Position */ +#define SYS_GPA_MFOS_MFOS14_Msk (0x1ul << SYS_GPA_MFOS_MFOS14_Pos) /*!< SYS_T::GPA_MFOS: MFOS14 Mask */ + +#define SYS_GPA_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPA_MFOS: MFOS15 Position */ +#define SYS_GPA_MFOS_MFOS15_Msk (0x1ul << SYS_GPA_MFOS_MFOS15_Pos) /*!< SYS_T::GPA_MFOS: MFOS15 Mask */ + +#define SYS_GPB_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPB_MFOS: MFOS0 Position */ +#define SYS_GPB_MFOS_MFOS0_Msk (0x1ul << SYS_GPB_MFOS_MFOS0_Pos) /*!< SYS_T::GPB_MFOS: MFOS0 Mask */ + +#define SYS_GPB_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPB_MFOS: MFOS1 Position */ +#define SYS_GPB_MFOS_MFOS1_Msk (0x1ul << SYS_GPB_MFOS_MFOS1_Pos) /*!< SYS_T::GPB_MFOS: MFOS1 Mask */ + +#define SYS_GPB_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPB_MFOS: MFOS2 Position */ +#define SYS_GPB_MFOS_MFOS2_Msk (0x1ul << SYS_GPB_MFOS_MFOS2_Pos) /*!< SYS_T::GPB_MFOS: MFOS2 Mask */ + +#define SYS_GPB_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPB_MFOS: MFOS3 Position */ +#define SYS_GPB_MFOS_MFOS3_Msk (0x1ul << SYS_GPB_MFOS_MFOS3_Pos) /*!< SYS_T::GPB_MFOS: MFOS3 Mask */ + +#define SYS_GPB_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPB_MFOS: MFOS4 Position */ +#define SYS_GPB_MFOS_MFOS4_Msk (0x1ul << SYS_GPB_MFOS_MFOS4_Pos) /*!< SYS_T::GPB_MFOS: MFOS4 Mask */ + +#define SYS_GPB_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPB_MFOS: MFOS5 Position */ +#define SYS_GPB_MFOS_MFOS5_Msk (0x1ul << SYS_GPB_MFOS_MFOS5_Pos) /*!< SYS_T::GPB_MFOS: MFOS5 Mask */ + +#define SYS_GPB_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPB_MFOS: MFOS6 Position */ +#define SYS_GPB_MFOS_MFOS6_Msk (0x1ul << SYS_GPB_MFOS_MFOS6_Pos) /*!< SYS_T::GPB_MFOS: MFOS6 Mask */ + +#define SYS_GPB_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPB_MFOS: MFOS7 Position */ +#define SYS_GPB_MFOS_MFOS7_Msk (0x1ul << SYS_GPB_MFOS_MFOS7_Pos) /*!< SYS_T::GPB_MFOS: MFOS7 Mask */ + +#define SYS_GPB_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPB_MFOS: MFOS8 Position */ +#define SYS_GPB_MFOS_MFOS8_Msk (0x1ul << SYS_GPB_MFOS_MFOS8_Pos) /*!< SYS_T::GPB_MFOS: MFOS8 Mask */ + +#define SYS_GPB_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPB_MFOS: MFOS9 Position */ +#define SYS_GPB_MFOS_MFOS9_Msk (0x1ul << SYS_GPB_MFOS_MFOS9_Pos) /*!< SYS_T::GPB_MFOS: MFOS9 Mask */ + +#define SYS_GPB_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPB_MFOS: MFOS10 Position */ +#define SYS_GPB_MFOS_MFOS10_Msk (0x1ul << SYS_GPB_MFOS_MFOS10_Pos) /*!< SYS_T::GPB_MFOS: MFOS10 Mask */ + +#define SYS_GPB_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPB_MFOS: MFOS11 Position */ +#define SYS_GPB_MFOS_MFOS11_Msk (0x1ul << SYS_GPB_MFOS_MFOS11_Pos) /*!< SYS_T::GPB_MFOS: MFOS11 Mask */ + +#define SYS_GPB_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPB_MFOS: MFOS12 Position */ +#define SYS_GPB_MFOS_MFOS12_Msk (0x1ul << SYS_GPB_MFOS_MFOS12_Pos) /*!< SYS_T::GPB_MFOS: MFOS12 Mask */ + +#define SYS_GPB_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPB_MFOS: MFOS13 Position */ +#define SYS_GPB_MFOS_MFOS13_Msk (0x1ul << SYS_GPB_MFOS_MFOS13_Pos) /*!< SYS_T::GPB_MFOS: MFOS13 Mask */ + +#define SYS_GPB_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPB_MFOS: MFOS14 Position */ +#define SYS_GPB_MFOS_MFOS14_Msk (0x1ul << SYS_GPB_MFOS_MFOS14_Pos) /*!< SYS_T::GPB_MFOS: MFOS14 Mask */ + +#define SYS_GPB_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPB_MFOS: MFOS15 Position */ +#define SYS_GPB_MFOS_MFOS15_Msk (0x1ul << SYS_GPB_MFOS_MFOS15_Pos) /*!< SYS_T::GPB_MFOS: MFOS15 Mask */ + +#define SYS_GPC_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPC_MFOS: MFOS0 Position */ +#define SYS_GPC_MFOS_MFOS0_Msk (0x1ul << SYS_GPC_MFOS_MFOS0_Pos) /*!< SYS_T::GPC_MFOS: MFOS0 Mask */ + +#define SYS_GPC_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPC_MFOS: MFOS1 Position */ +#define SYS_GPC_MFOS_MFOS1_Msk (0x1ul << SYS_GPC_MFOS_MFOS1_Pos) /*!< SYS_T::GPC_MFOS: MFOS1 Mask */ + +#define SYS_GPC_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPC_MFOS: MFOS2 Position */ +#define SYS_GPC_MFOS_MFOS2_Msk (0x1ul << SYS_GPC_MFOS_MFOS2_Pos) /*!< SYS_T::GPC_MFOS: MFOS2 Mask */ + +#define SYS_GPC_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPC_MFOS: MFOS3 Position */ +#define SYS_GPC_MFOS_MFOS3_Msk (0x1ul << SYS_GPC_MFOS_MFOS3_Pos) /*!< SYS_T::GPC_MFOS: MFOS3 Mask */ + +#define SYS_GPC_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPC_MFOS: MFOS4 Position */ +#define SYS_GPC_MFOS_MFOS4_Msk (0x1ul << SYS_GPC_MFOS_MFOS4_Pos) /*!< SYS_T::GPC_MFOS: MFOS4 Mask */ + +#define SYS_GPC_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPC_MFOS: MFOS5 Position */ +#define SYS_GPC_MFOS_MFOS5_Msk (0x1ul << SYS_GPC_MFOS_MFOS5_Pos) /*!< SYS_T::GPC_MFOS: MFOS5 Mask */ + +#define SYS_GPC_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPC_MFOS: MFOS6 Position */ +#define SYS_GPC_MFOS_MFOS6_Msk (0x1ul << SYS_GPC_MFOS_MFOS6_Pos) /*!< SYS_T::GPC_MFOS: MFOS6 Mask */ + +#define SYS_GPC_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPC_MFOS: MFOS7 Position */ +#define SYS_GPC_MFOS_MFOS7_Msk (0x1ul << SYS_GPC_MFOS_MFOS7_Pos) /*!< SYS_T::GPC_MFOS: MFOS7 Mask */ + +#define SYS_GPC_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPC_MFOS: MFOS8 Position */ +#define SYS_GPC_MFOS_MFOS8_Msk (0x1ul << SYS_GPC_MFOS_MFOS8_Pos) /*!< SYS_T::GPC_MFOS: MFOS8 Mask */ + +#define SYS_GPC_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPC_MFOS: MFOS9 Position */ +#define SYS_GPC_MFOS_MFOS9_Msk (0x1ul << SYS_GPC_MFOS_MFOS9_Pos) /*!< SYS_T::GPC_MFOS: MFOS9 Mask */ + +#define SYS_GPC_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPC_MFOS: MFOS10 Position */ +#define SYS_GPC_MFOS_MFOS10_Msk (0x1ul << SYS_GPC_MFOS_MFOS10_Pos) /*!< SYS_T::GPC_MFOS: MFOS10 Mask */ + +#define SYS_GPC_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPC_MFOS: MFOS11 Position */ +#define SYS_GPC_MFOS_MFOS11_Msk (0x1ul << SYS_GPC_MFOS_MFOS11_Pos) /*!< SYS_T::GPC_MFOS: MFOS11 Mask */ + +#define SYS_GPC_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPC_MFOS: MFOS12 Position */ +#define SYS_GPC_MFOS_MFOS12_Msk (0x1ul << SYS_GPC_MFOS_MFOS12_Pos) /*!< SYS_T::GPC_MFOS: MFOS12 Mask */ + +#define SYS_GPC_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPC_MFOS: MFOS13 Position */ +#define SYS_GPC_MFOS_MFOS13_Msk (0x1ul << SYS_GPC_MFOS_MFOS13_Pos) /*!< SYS_T::GPC_MFOS: MFOS13 Mask */ + +#define SYS_GPC_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPC_MFOS: MFOS14 Position */ +#define SYS_GPC_MFOS_MFOS14_Msk (0x1ul << SYS_GPC_MFOS_MFOS14_Pos) /*!< SYS_T::GPC_MFOS: MFOS14 Mask */ + +#define SYS_GPC_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPC_MFOS: MFOS15 Position */ +#define SYS_GPC_MFOS_MFOS15_Msk (0x1ul << SYS_GPC_MFOS_MFOS15_Pos) /*!< SYS_T::GPC_MFOS: MFOS15 Mask */ + +#define SYS_GPD_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPD_MFOS: MFOS0 Position */ +#define SYS_GPD_MFOS_MFOS0_Msk (0x1ul << SYS_GPD_MFOS_MFOS0_Pos) /*!< SYS_T::GPD_MFOS: MFOS0 Mask */ + +#define SYS_GPD_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPD_MFOS: MFOS1 Position */ +#define SYS_GPD_MFOS_MFOS1_Msk (0x1ul << SYS_GPD_MFOS_MFOS1_Pos) /*!< SYS_T::GPD_MFOS: MFOS1 Mask */ + +#define SYS_GPD_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPD_MFOS: MFOS2 Position */ +#define SYS_GPD_MFOS_MFOS2_Msk (0x1ul << SYS_GPD_MFOS_MFOS2_Pos) /*!< SYS_T::GPD_MFOS: MFOS2 Mask */ + +#define SYS_GPD_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPD_MFOS: MFOS3 Position */ +#define SYS_GPD_MFOS_MFOS3_Msk (0x1ul << SYS_GPD_MFOS_MFOS3_Pos) /*!< SYS_T::GPD_MFOS: MFOS3 Mask */ + +#define SYS_GPD_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPD_MFOS: MFOS4 Position */ +#define SYS_GPD_MFOS_MFOS4_Msk (0x1ul << SYS_GPD_MFOS_MFOS4_Pos) /*!< SYS_T::GPD_MFOS: MFOS4 Mask */ + +#define SYS_GPD_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPD_MFOS: MFOS5 Position */ +#define SYS_GPD_MFOS_MFOS5_Msk (0x1ul << SYS_GPD_MFOS_MFOS5_Pos) /*!< SYS_T::GPD_MFOS: MFOS5 Mask */ + +#define SYS_GPD_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPD_MFOS: MFOS6 Position */ +#define SYS_GPD_MFOS_MFOS6_Msk (0x1ul << SYS_GPD_MFOS_MFOS6_Pos) /*!< SYS_T::GPD_MFOS: MFOS6 Mask */ + +#define SYS_GPD_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPD_MFOS: MFOS7 Position */ +#define SYS_GPD_MFOS_MFOS7_Msk (0x1ul << SYS_GPD_MFOS_MFOS7_Pos) /*!< SYS_T::GPD_MFOS: MFOS7 Mask */ + +#define SYS_GPD_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPD_MFOS: MFOS8 Position */ +#define SYS_GPD_MFOS_MFOS8_Msk (0x1ul << SYS_GPD_MFOS_MFOS8_Pos) /*!< SYS_T::GPD_MFOS: MFOS8 Mask */ + +#define SYS_GPD_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPD_MFOS: MFOS9 Position */ +#define SYS_GPD_MFOS_MFOS9_Msk (0x1ul << SYS_GPD_MFOS_MFOS9_Pos) /*!< SYS_T::GPD_MFOS: MFOS9 Mask */ + +#define SYS_GPD_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPD_MFOS: MFOS10 Position */ +#define SYS_GPD_MFOS_MFOS10_Msk (0x1ul << SYS_GPD_MFOS_MFOS10_Pos) /*!< SYS_T::GPD_MFOS: MFOS10 Mask */ + +#define SYS_GPD_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPD_MFOS: MFOS11 Position */ +#define SYS_GPD_MFOS_MFOS11_Msk (0x1ul << SYS_GPD_MFOS_MFOS11_Pos) /*!< SYS_T::GPD_MFOS: MFOS11 Mask */ + +#define SYS_GPD_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPD_MFOS: MFOS12 Position */ +#define SYS_GPD_MFOS_MFOS12_Msk (0x1ul << SYS_GPD_MFOS_MFOS12_Pos) /*!< SYS_T::GPD_MFOS: MFOS12 Mask */ + +#define SYS_GPD_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPD_MFOS: MFOS13 Position */ +#define SYS_GPD_MFOS_MFOS13_Msk (0x1ul << SYS_GPD_MFOS_MFOS13_Pos) /*!< SYS_T::GPD_MFOS: MFOS13 Mask */ + +#define SYS_GPD_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPD_MFOS: MFOS14 Position */ +#define SYS_GPD_MFOS_MFOS14_Msk (0x1ul << SYS_GPD_MFOS_MFOS14_Pos) /*!< SYS_T::GPD_MFOS: MFOS14 Mask */ + +#define SYS_GPD_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPD_MFOS: MFOS15 Position */ +#define SYS_GPD_MFOS_MFOS15_Msk (0x1ul << SYS_GPD_MFOS_MFOS15_Pos) /*!< SYS_T::GPD_MFOS: MFOS15 Mask */ + +#define SYS_GPE_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPE_MFOS: MFOS0 Position */ +#define SYS_GPE_MFOS_MFOS0_Msk (0x1ul << SYS_GPE_MFOS_MFOS0_Pos) /*!< SYS_T::GPE_MFOS: MFOS0 Mask */ + +#define SYS_GPE_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPE_MFOS: MFOS1 Position */ +#define SYS_GPE_MFOS_MFOS1_Msk (0x1ul << SYS_GPE_MFOS_MFOS1_Pos) /*!< SYS_T::GPE_MFOS: MFOS1 Mask */ + +#define SYS_GPE_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPE_MFOS: MFOS2 Position */ +#define SYS_GPE_MFOS_MFOS2_Msk (0x1ul << SYS_GPE_MFOS_MFOS2_Pos) /*!< SYS_T::GPE_MFOS: MFOS2 Mask */ + +#define SYS_GPE_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPE_MFOS: MFOS3 Position */ +#define SYS_GPE_MFOS_MFOS3_Msk (0x1ul << SYS_GPE_MFOS_MFOS3_Pos) /*!< SYS_T::GPE_MFOS: MFOS3 Mask */ + +#define SYS_GPE_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPE_MFOS: MFOS4 Position */ +#define SYS_GPE_MFOS_MFOS4_Msk (0x1ul << SYS_GPE_MFOS_MFOS4_Pos) /*!< SYS_T::GPE_MFOS: MFOS4 Mask */ + +#define SYS_GPE_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPE_MFOS: MFOS5 Position */ +#define SYS_GPE_MFOS_MFOS5_Msk (0x1ul << SYS_GPE_MFOS_MFOS5_Pos) /*!< SYS_T::GPE_MFOS: MFOS5 Mask */ + +#define SYS_GPE_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPE_MFOS: MFOS6 Position */ +#define SYS_GPE_MFOS_MFOS6_Msk (0x1ul << SYS_GPE_MFOS_MFOS6_Pos) /*!< SYS_T::GPE_MFOS: MFOS6 Mask */ + +#define SYS_GPE_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPE_MFOS: MFOS7 Position */ +#define SYS_GPE_MFOS_MFOS7_Msk (0x1ul << SYS_GPE_MFOS_MFOS7_Pos) /*!< SYS_T::GPE_MFOS: MFOS7 Mask */ + +#define SYS_GPE_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPE_MFOS: MFOS8 Position */ +#define SYS_GPE_MFOS_MFOS8_Msk (0x1ul << SYS_GPE_MFOS_MFOS8_Pos) /*!< SYS_T::GPE_MFOS: MFOS8 Mask */ + +#define SYS_GPE_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPE_MFOS: MFOS9 Position */ +#define SYS_GPE_MFOS_MFOS9_Msk (0x1ul << SYS_GPE_MFOS_MFOS9_Pos) /*!< SYS_T::GPE_MFOS: MFOS9 Mask */ + +#define SYS_GPE_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPE_MFOS: MFOS10 Position */ +#define SYS_GPE_MFOS_MFOS10_Msk (0x1ul << SYS_GPE_MFOS_MFOS10_Pos) /*!< SYS_T::GPE_MFOS: MFOS10 Mask */ + +#define SYS_GPE_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPE_MFOS: MFOS11 Position */ +#define SYS_GPE_MFOS_MFOS11_Msk (0x1ul << SYS_GPE_MFOS_MFOS11_Pos) /*!< SYS_T::GPE_MFOS: MFOS11 Mask */ + +#define SYS_GPE_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPE_MFOS: MFOS12 Position */ +#define SYS_GPE_MFOS_MFOS12_Msk (0x1ul << SYS_GPE_MFOS_MFOS12_Pos) /*!< SYS_T::GPE_MFOS: MFOS12 Mask */ + +#define SYS_GPE_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPE_MFOS: MFOS13 Position */ +#define SYS_GPE_MFOS_MFOS13_Msk (0x1ul << SYS_GPE_MFOS_MFOS13_Pos) /*!< SYS_T::GPE_MFOS: MFOS13 Mask */ + +#define SYS_GPE_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPE_MFOS: MFOS14 Position */ +#define SYS_GPE_MFOS_MFOS14_Msk (0x1ul << SYS_GPE_MFOS_MFOS14_Pos) /*!< SYS_T::GPE_MFOS: MFOS14 Mask */ + +#define SYS_GPE_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPE_MFOS: MFOS15 Position */ +#define SYS_GPE_MFOS_MFOS15_Msk (0x1ul << SYS_GPE_MFOS_MFOS15_Pos) /*!< SYS_T::GPE_MFOS: MFOS15 Mask */ + +#define SYS_GPF_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPF_MFOS: MFOS0 Position */ +#define SYS_GPF_MFOS_MFOS0_Msk (0x1ul << SYS_GPF_MFOS_MFOS0_Pos) /*!< SYS_T::GPF_MFOS: MFOS0 Mask */ + +#define SYS_GPF_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPF_MFOS: MFOS1 Position */ +#define SYS_GPF_MFOS_MFOS1_Msk (0x1ul << SYS_GPF_MFOS_MFOS1_Pos) /*!< SYS_T::GPF_MFOS: MFOS1 Mask */ + +#define SYS_GPF_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPF_MFOS: MFOS2 Position */ +#define SYS_GPF_MFOS_MFOS2_Msk (0x1ul << SYS_GPF_MFOS_MFOS2_Pos) /*!< SYS_T::GPF_MFOS: MFOS2 Mask */ + +#define SYS_GPF_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPF_MFOS: MFOS3 Position */ +#define SYS_GPF_MFOS_MFOS3_Msk (0x1ul << SYS_GPF_MFOS_MFOS3_Pos) /*!< SYS_T::GPF_MFOS: MFOS3 Mask */ + +#define SYS_GPF_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPF_MFOS: MFOS4 Position */ +#define SYS_GPF_MFOS_MFOS4_Msk (0x1ul << SYS_GPF_MFOS_MFOS4_Pos) /*!< SYS_T::GPF_MFOS: MFOS4 Mask */ + +#define SYS_GPF_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPF_MFOS: MFOS5 Position */ +#define SYS_GPF_MFOS_MFOS5_Msk (0x1ul << SYS_GPF_MFOS_MFOS5_Pos) /*!< SYS_T::GPF_MFOS: MFOS5 Mask */ + +#define SYS_GPF_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPF_MFOS: MFOS6 Position */ +#define SYS_GPF_MFOS_MFOS6_Msk (0x1ul << SYS_GPF_MFOS_MFOS6_Pos) /*!< SYS_T::GPF_MFOS: MFOS6 Mask */ + +#define SYS_GPF_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPF_MFOS: MFOS7 Position */ +#define SYS_GPF_MFOS_MFOS7_Msk (0x1ul << SYS_GPF_MFOS_MFOS7_Pos) /*!< SYS_T::GPF_MFOS: MFOS7 Mask */ + +#define SYS_GPF_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPF_MFOS: MFOS8 Position */ +#define SYS_GPF_MFOS_MFOS8_Msk (0x1ul << SYS_GPF_MFOS_MFOS8_Pos) /*!< SYS_T::GPF_MFOS: MFOS8 Mask */ + +#define SYS_GPF_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPF_MFOS: MFOS9 Position */ +#define SYS_GPF_MFOS_MFOS9_Msk (0x1ul << SYS_GPF_MFOS_MFOS9_Pos) /*!< SYS_T::GPF_MFOS: MFOS9 Mask */ + +#define SYS_GPF_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPF_MFOS: MFOS10 Position */ +#define SYS_GPF_MFOS_MFOS10_Msk (0x1ul << SYS_GPF_MFOS_MFOS10_Pos) /*!< SYS_T::GPF_MFOS: MFOS10 Mask */ + +#define SYS_GPF_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPF_MFOS: MFOS11 Position */ +#define SYS_GPF_MFOS_MFOS11_Msk (0x1ul << SYS_GPF_MFOS_MFOS11_Pos) /*!< SYS_T::GPF_MFOS: MFOS11 Mask */ + +#define SYS_GPF_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPF_MFOS: MFOS12 Position */ +#define SYS_GPF_MFOS_MFOS12_Msk (0x1ul << SYS_GPF_MFOS_MFOS12_Pos) /*!< SYS_T::GPF_MFOS: MFOS12 Mask */ + +#define SYS_GPF_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPF_MFOS: MFOS13 Position */ +#define SYS_GPF_MFOS_MFOS13_Msk (0x1ul << SYS_GPF_MFOS_MFOS13_Pos) /*!< SYS_T::GPF_MFOS: MFOS13 Mask */ + +#define SYS_GPF_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPF_MFOS: MFOS14 Position */ +#define SYS_GPF_MFOS_MFOS14_Msk (0x1ul << SYS_GPF_MFOS_MFOS14_Pos) /*!< SYS_T::GPF_MFOS: MFOS14 Mask */ + +#define SYS_GPF_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPF_MFOS: MFOS15 Position */ +#define SYS_GPF_MFOS_MFOS15_Msk (0x1ul << SYS_GPF_MFOS_MFOS15_Pos) /*!< SYS_T::GPF_MFOS: MFOS15 Mask */ + +#define SYS_GPG_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPG_MFOS: MFOS0 Position */ +#define SYS_GPG_MFOS_MFOS0_Msk (0x1ul << SYS_GPG_MFOS_MFOS0_Pos) /*!< SYS_T::GPG_MFOS: MFOS0 Mask */ + +#define SYS_GPG_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPG_MFOS: MFOS1 Position */ +#define SYS_GPG_MFOS_MFOS1_Msk (0x1ul << SYS_GPG_MFOS_MFOS1_Pos) /*!< SYS_T::GPG_MFOS: MFOS1 Mask */ + +#define SYS_GPG_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPG_MFOS: MFOS2 Position */ +#define SYS_GPG_MFOS_MFOS2_Msk (0x1ul << SYS_GPG_MFOS_MFOS2_Pos) /*!< SYS_T::GPG_MFOS: MFOS2 Mask */ + +#define SYS_GPG_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPG_MFOS: MFOS3 Position */ +#define SYS_GPG_MFOS_MFOS3_Msk (0x1ul << SYS_GPG_MFOS_MFOS3_Pos) /*!< SYS_T::GPG_MFOS: MFOS3 Mask */ + +#define SYS_GPG_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPG_MFOS: MFOS4 Position */ +#define SYS_GPG_MFOS_MFOS4_Msk (0x1ul << SYS_GPG_MFOS_MFOS4_Pos) /*!< SYS_T::GPG_MFOS: MFOS4 Mask */ + +#define SYS_GPG_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPG_MFOS: MFOS5 Position */ +#define SYS_GPG_MFOS_MFOS5_Msk (0x1ul << SYS_GPG_MFOS_MFOS5_Pos) /*!< SYS_T::GPG_MFOS: MFOS5 Mask */ + +#define SYS_GPG_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPG_MFOS: MFOS6 Position */ +#define SYS_GPG_MFOS_MFOS6_Msk (0x1ul << SYS_GPG_MFOS_MFOS6_Pos) /*!< SYS_T::GPG_MFOS: MFOS6 Mask */ + +#define SYS_GPG_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPG_MFOS: MFOS7 Position */ +#define SYS_GPG_MFOS_MFOS7_Msk (0x1ul << SYS_GPG_MFOS_MFOS7_Pos) /*!< SYS_T::GPG_MFOS: MFOS7 Mask */ + +#define SYS_GPG_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPG_MFOS: MFOS8 Position */ +#define SYS_GPG_MFOS_MFOS8_Msk (0x1ul << SYS_GPG_MFOS_MFOS8_Pos) /*!< SYS_T::GPG_MFOS: MFOS8 Mask */ + +#define SYS_GPG_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPG_MFOS: MFOS9 Position */ +#define SYS_GPG_MFOS_MFOS9_Msk (0x1ul << SYS_GPG_MFOS_MFOS9_Pos) /*!< SYS_T::GPG_MFOS: MFOS9 Mask */ + +#define SYS_GPG_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPG_MFOS: MFOS10 Position */ +#define SYS_GPG_MFOS_MFOS10_Msk (0x1ul << SYS_GPG_MFOS_MFOS10_Pos) /*!< SYS_T::GPG_MFOS: MFOS10 Mask */ + +#define SYS_GPG_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPG_MFOS: MFOS11 Position */ +#define SYS_GPG_MFOS_MFOS11_Msk (0x1ul << SYS_GPG_MFOS_MFOS11_Pos) /*!< SYS_T::GPG_MFOS: MFOS11 Mask */ + +#define SYS_GPG_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPG_MFOS: MFOS12 Position */ +#define SYS_GPG_MFOS_MFOS12_Msk (0x1ul << SYS_GPG_MFOS_MFOS12_Pos) /*!< SYS_T::GPG_MFOS: MFOS12 Mask */ + +#define SYS_GPG_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPG_MFOS: MFOS13 Position */ +#define SYS_GPG_MFOS_MFOS13_Msk (0x1ul << SYS_GPG_MFOS_MFOS13_Pos) /*!< SYS_T::GPG_MFOS: MFOS13 Mask */ + +#define SYS_GPG_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPG_MFOS: MFOS14 Position */ +#define SYS_GPG_MFOS_MFOS14_Msk (0x1ul << SYS_GPG_MFOS_MFOS14_Pos) /*!< SYS_T::GPG_MFOS: MFOS14 Mask */ + +#define SYS_GPG_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPG_MFOS: MFOS15 Position */ +#define SYS_GPG_MFOS_MFOS15_Msk (0x1ul << SYS_GPG_MFOS_MFOS15_Pos) /*!< SYS_T::GPG_MFOS: MFOS15 Mask */ + +#define SYS_GPH_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPH_MFOS: MFOS0 Position */ +#define SYS_GPH_MFOS_MFOS0_Msk (0x1ul << SYS_GPH_MFOS_MFOS0_Pos) /*!< SYS_T::GPH_MFOS: MFOS0 Mask */ + +#define SYS_GPH_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPH_MFOS: MFOS1 Position */ +#define SYS_GPH_MFOS_MFOS1_Msk (0x1ul << SYS_GPH_MFOS_MFOS1_Pos) /*!< SYS_T::GPH_MFOS: MFOS1 Mask */ + +#define SYS_GPH_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPH_MFOS: MFOS2 Position */ +#define SYS_GPH_MFOS_MFOS2_Msk (0x1ul << SYS_GPH_MFOS_MFOS2_Pos) /*!< SYS_T::GPH_MFOS: MFOS2 Mask */ + +#define SYS_GPH_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPH_MFOS: MFOS3 Position */ +#define SYS_GPH_MFOS_MFOS3_Msk (0x1ul << SYS_GPH_MFOS_MFOS3_Pos) /*!< SYS_T::GPH_MFOS: MFOS3 Mask */ + +#define SYS_GPH_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPH_MFOS: MFOS4 Position */ +#define SYS_GPH_MFOS_MFOS4_Msk (0x1ul << SYS_GPH_MFOS_MFOS4_Pos) /*!< SYS_T::GPH_MFOS: MFOS4 Mask */ + +#define SYS_GPH_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPH_MFOS: MFOS5 Position */ +#define SYS_GPH_MFOS_MFOS5_Msk (0x1ul << SYS_GPH_MFOS_MFOS5_Pos) /*!< SYS_T::GPH_MFOS: MFOS5 Mask */ + +#define SYS_GPH_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPH_MFOS: MFOS6 Position */ +#define SYS_GPH_MFOS_MFOS6_Msk (0x1ul << SYS_GPH_MFOS_MFOS6_Pos) /*!< SYS_T::GPH_MFOS: MFOS6 Mask */ + +#define SYS_GPH_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPH_MFOS: MFOS7 Position */ +#define SYS_GPH_MFOS_MFOS7_Msk (0x1ul << SYS_GPH_MFOS_MFOS7_Pos) /*!< SYS_T::GPH_MFOS: MFOS7 Mask */ + +#define SYS_GPH_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPH_MFOS: MFOS8 Position */ +#define SYS_GPH_MFOS_MFOS8_Msk (0x1ul << SYS_GPH_MFOS_MFOS8_Pos) /*!< SYS_T::GPH_MFOS: MFOS8 Mask */ + +#define SYS_GPH_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPH_MFOS: MFOS9 Position */ +#define SYS_GPH_MFOS_MFOS9_Msk (0x1ul << SYS_GPH_MFOS_MFOS9_Pos) /*!< SYS_T::GPH_MFOS: MFOS9 Mask */ + +#define SYS_GPH_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPH_MFOS: MFOS10 Position */ +#define SYS_GPH_MFOS_MFOS10_Msk (0x1ul << SYS_GPH_MFOS_MFOS10_Pos) /*!< SYS_T::GPH_MFOS: MFOS10 Mask */ + +#define SYS_GPH_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPH_MFOS: MFOS11 Position */ +#define SYS_GPH_MFOS_MFOS11_Msk (0x1ul << SYS_GPH_MFOS_MFOS11_Pos) /*!< SYS_T::GPH_MFOS: MFOS11 Mask */ + +#define SYS_GPH_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPH_MFOS: MFOS12 Position */ +#define SYS_GPH_MFOS_MFOS12_Msk (0x1ul << SYS_GPH_MFOS_MFOS12_Pos) /*!< SYS_T::GPH_MFOS: MFOS12 Mask */ + +#define SYS_GPH_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPH_MFOS: MFOS13 Position */ +#define SYS_GPH_MFOS_MFOS13_Msk (0x1ul << SYS_GPH_MFOS_MFOS13_Pos) /*!< SYS_T::GPH_MFOS: MFOS13 Mask */ + +#define SYS_GPH_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPH_MFOS: MFOS14 Position */ +#define SYS_GPH_MFOS_MFOS14_Msk (0x1ul << SYS_GPH_MFOS_MFOS14_Pos) /*!< SYS_T::GPH_MFOS: MFOS14 Mask */ + +#define SYS_GPH_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPH_MFOS: MFOS15 Position */ +#define SYS_GPH_MFOS_MFOS15_Msk (0x1ul << SYS_GPH_MFOS_MFOS15_Pos) /*!< SYS_T::GPH_MFOS: MFOS15 Mask */ + +#define SYS_SRAM_INTCTL_PERRIEN_Pos (0) /*!< SYS_T::SRAM_INTCTL: PERRIEN Position */ +#define SYS_SRAM_INTCTL_PERRIEN_Msk (0x1ul << SYS_SRAM_INTCTL_PERRIEN_Pos) /*!< SYS_T::SRAM_INTCTL: PERRIEN Mask */ + +#define SYS_SRAM_STATUS_PERRIF_Pos (0) /*!< SYS_T::SRAM_STATUS: PERRIF Position */ +#define SYS_SRAM_STATUS_PERRIF_Msk (0x1ul << SYS_SRAM_STATUS_PERRIF_Pos) /*!< SYS_T::SRAM_STATUS: PERRIF Mask */ + +#define SYS_SRAM_ERRADDR_ERRADDR_Pos (0) /*!< SYS_T::SRAM_ERRADDR: ERRADDR Position */ +#define SYS_SRAM_ERRADDR_ERRADDR_Msk (0xfffffffful << SYS_SRAM_ERRADDR_ERRADDR_Pos) /*!< SYS_T::SRAM_ERRADDR: ERRADDR Mask */ + +#define SYS_SRAM_BISTCTL_SRBIST0_Pos (0) /*!< SYS_T::SRAM_BISTCTL: SRBIST0 Position */ +#define SYS_SRAM_BISTCTL_SRBIST0_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST0_Pos) /*!< SYS_T::SRAM_BISTCTL: SRBIST0 Mask */ + +#define SYS_SRAM_BISTCTL_SRBIST1_Pos (1) /*!< SYS_T::SRAM_BISTCTL: SRBIST1 Position */ +#define SYS_SRAM_BISTCTL_SRBIST1_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST1_Pos) /*!< SYS_T::SRAM_BISTCTL: SRBIST1 Mask */ + +#define SYS_SRAM_BISTCTL_CRBIST_Pos (2) /*!< SYS_T::SRAM_BISTCTL: CRBIST Position */ +#define SYS_SRAM_BISTCTL_CRBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_CRBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: CRBIST Mask */ + +#define SYS_SRAM_BISTCTL_CANBIST_Pos (3) /*!< SYS_T::SRAM_BISTCTL: CANBIST Position */ +#define SYS_SRAM_BISTCTL_CANBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_CANBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: CANBIST Mask */ + +#define SYS_SRAM_BISTCTL_USBBIST_Pos (4) /*!< SYS_T::SRAM_BISTCTL: USBBIST Position */ +#define SYS_SRAM_BISTCTL_USBBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_USBBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: USBBIST Mask */ + +#define SYS_SRAM_BISTCTL_SPIMBIST_Pos (5) /*!< SYS_T::SRAM_BISTCTL: SPIMBIST Position */ +#define SYS_SRAM_BISTCTL_SPIMBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_SPIMBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: SPIMBIST Mask */ + +#define SYS_SRAM_BISTCTL_EMCBIST_Pos (6) /*!< SYS_T::SRAM_BISTCTL: EMCBIST Position */ +#define SYS_SRAM_BISTCTL_EMCBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_EMCBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: EMCBIST Mask */ + +#define SYS_SRAM_BISTCTL_PDMABIST_Pos (7) /*!< SYS_T::SRAM_BISTCTL: PDMABIST Position */ +#define SYS_SRAM_BISTCTL_PDMABIST_Msk (0x1ul << SYS_SRAM_BISTCTL_PDMABIST_Pos) /*!< SYS_T::SRAM_BISTCTL: PDMABIST Mask */ + +#define SYS_SRAM_BISTCTL_HSUSBDBIST_Pos (8) /*!< SYS_T::SRAM_BISTCTL: HSUSBDBIST Position*/ +#define SYS_SRAM_BISTCTL_HSUSBDBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_HSUSBDBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: HSUSBDBIST Mask */ + +#define SYS_SRAM_BISTCTL_HSUSBHBIST_Pos (9) /*!< SYS_T::SRAM_BISTCTL: HSUSBHBIST Position*/ +#define SYS_SRAM_BISTCTL_HSUSBHBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_HSUSBHBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: HSUSBHBIST Mask */ + +#define SYS_SRAM_BISTCTL_SRB0S0_Pos (16) /*!< SYS_T::SRAM_BISTCTL: SRB0S0 Position */ +#define SYS_SRAM_BISTCTL_SRB0S0_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB0S0_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB0S0 Mask */ + +#define SYS_SRAM_BISTCTL_SRB0S1_Pos (17) /*!< SYS_T::SRAM_BISTCTL: SRB0S1 Position */ +#define SYS_SRAM_BISTCTL_SRB0S1_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB0S1_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB0S1 Mask */ + +#define SYS_SRAM_BISTCTL_SRB1S0_Pos (18) /*!< SYS_T::SRAM_BISTCTL: SRB1S0 Position */ +#define SYS_SRAM_BISTCTL_SRB1S0_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S0_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S0 Mask */ + +#define SYS_SRAM_BISTCTL_SRB1S1_Pos (19) /*!< SYS_T::SRAM_BISTCTL: SRB1S1 Position */ +#define SYS_SRAM_BISTCTL_SRB1S1_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S1_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S1 Mask */ + +#define SYS_SRAM_BISTCTL_SRB1S2_Pos (20) /*!< SYS_T::SRAM_BISTCTL: SRB1S2 Position */ +#define SYS_SRAM_BISTCTL_SRB1S2_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S2_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S2 Mask */ + +#define SYS_SRAM_BISTCTL_SRB1S3_Pos (21) /*!< SYS_T::SRAM_BISTCTL: SRB1S3 Position */ +#define SYS_SRAM_BISTCTL_SRB1S3_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S3_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S3 Mask */ + +#define SYS_SRAM_BISTCTL_SRB1S4_Pos (22) /*!< SYS_T::SRAM_BISTCTL: SRB1S4 Position */ +#define SYS_SRAM_BISTCTL_SRB1S4_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S4_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S4 Mask */ + +#define SYS_SRAM_BISTCTL_SRB1S5_Pos (23) /*!< SYS_T::SRAM_BISTCTL: SRB1S5 Position */ +#define SYS_SRAM_BISTCTL_SRB1S5_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S5_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S5 Mask */ + +#define SYS_SRAM_BISTSTS_SRBISTEF0_Pos (0) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF0 Position*/ +#define SYS_SRAM_BISTSTS_SRBISTEF0_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF0_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF0 Mask */ + +#define SYS_SRAM_BISTSTS_SRBISTEF1_Pos (1) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF1 Position*/ +#define SYS_SRAM_BISTSTS_SRBISTEF1_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF1_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF1 Mask */ + +#define SYS_SRAM_BISTSTS_CRBISTEF_Pos (2) /*!< SYS_T::SRAM_BISTSTS: CRBISTEF Position */ +#define SYS_SRAM_BISTSTS_CRBISTEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CRBISTEF_Pos) /*!< SYS_T::SRAM_BISTSTS: CRBISTEF Mask */ + +#define SYS_SRAM_BISTSTS_CANBEF_Pos (3) /*!< SYS_T::SRAM_BISTSTS: CANBEF Position */ +#define SYS_SRAM_BISTSTS_CANBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CANBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: CANBEF Mask */ + +#define SYS_SRAM_BISTSTS_USBBEF_Pos (4) /*!< SYS_T::SRAM_BISTSTS: USBBEF Position */ +#define SYS_SRAM_BISTSTS_USBBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: USBBEF Mask */ + +#define SYS_SRAM_BISTSTS_SRBEND0_Pos (16) /*!< SYS_T::SRAM_BISTSTS: SRBEND0 Position */ +#define SYS_SRAM_BISTSTS_SRBEND0_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND0_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBEND0 Mask */ + +#define SYS_SRAM_BISTSTS_SRBEND1_Pos (17) /*!< SYS_T::SRAM_BISTSTS: SRBEND1 Position */ +#define SYS_SRAM_BISTSTS_SRBEND1_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND1_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBEND1 Mask */ + +#define SYS_SRAM_BISTSTS_CRBEND_Pos (18) /*!< SYS_T::SRAM_BISTSTS: CRBEND Position */ +#define SYS_SRAM_BISTSTS_CRBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CRBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: CRBEND Mask */ + +#define SYS_SRAM_BISTSTS_CANBEND_Pos (19) /*!< SYS_T::SRAM_BISTSTS: CANBEND Position */ +#define SYS_SRAM_BISTSTS_CANBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CANBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: CANBEND Mask */ + +#define SYS_SRAM_BISTSTS_USBBEND_Pos (20) /*!< SYS_T::SRAM_BISTSTS: USBBEND Position */ +#define SYS_SRAM_BISTSTS_USBBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: USBBEND Mask */ + +#define SYS_HIRCTCTL_FREQSEL_Pos (0) /*!< SYS_T::HIRCTCTL: FREQSEL Position */ +#define SYS_HIRCTCTL_FREQSEL_Msk (0x3ul << SYS_HIRCTCTL_FREQSEL_Pos) /*!< SYS_T::HIRCTCTL: FREQSEL Mask */ + +#define SYS_HIRCTCTL_LOOPSEL_Pos (4) /*!< SYS_T::HIRCTCTL: LOOPSEL Position */ +#define SYS_HIRCTCTL_LOOPSEL_Msk (0x3ul << SYS_HIRCTCTL_LOOPSEL_Pos) /*!< SYS_T::HIRCTCTL: LOOPSEL Mask */ + +#define SYS_HIRCTCTL_RETRYCNT_Pos (6) /*!< SYS_T::HIRCTCTL: RETRYCNT Position */ +#define SYS_HIRCTCTL_RETRYCNT_Msk (0x3ul << SYS_HIRCTCTL_RETRYCNT_Pos) /*!< SYS_T::HIRCTCTL: RETRYCNT Mask */ + +#define SYS_HIRCTCTL_CESTOPEN_Pos (8) /*!< SYS_T::HIRCTCTL: CESTOPEN Position */ +#define SYS_HIRCTCTL_CESTOPEN_Msk (0x1ul << SYS_HIRCTCTL_CESTOPEN_Pos) /*!< SYS_T::HIRCTCTL: CESTOPEN Mask */ + +#define SYS_HIRCTCTL_BOUNDEN_Pos (9) /*!< SYS_T::HIRCTCTL: BOUNDEN Position */ +#define SYS_HIRCTCTL_BOUNDEN_Msk (0x1ul << SYS_HIRCTCTL_BOUNDEN_Pos) /*!< SYS_T::HIRCTCTL: BOUNDEN Mask */ + +#define SYS_HIRCTCTL_REFCKSEL_Pos (10) /*!< SYS_T::HIRCTCTL: REFCKSEL Position */ +#define SYS_HIRCTCTL_REFCKSEL_Msk (0x1ul << SYS_HIRCTCTL_REFCKSEL_Pos) /*!< SYS_T::HIRCTCTL: REFCKSEL Mask */ + +#define SYS_HIRCTCTL_BOUNDARY_Pos (16) /*!< SYS_T::HIRCTCTL: BOUNDARY Position */ +#define SYS_HIRCTCTL_BOUNDARY_Msk (0x1ful << SYS_HIRCTCTL_BOUNDARY_Pos) /*!< SYS_T::HIRCTCTL: BOUNDARY Mask */ + +#define SYS_HIRCTIEN_TFAILIEN_Pos (1) /*!< SYS_T::HIRCTIEN: TFAILIEN Position */ +#define SYS_HIRCTIEN_TFAILIEN_Msk (0x1ul << SYS_HIRCTIEN_TFAILIEN_Pos) /*!< SYS_T::HIRCTIEN: TFAILIEN Mask */ + +#define SYS_HIRCTIEN_CLKEIEN_Pos (2) /*!< SYS_T::HIRCTIEN: CLKEIEN Position */ +#define SYS_HIRCTIEN_CLKEIEN_Msk (0x1ul << SYS_HIRCTIEN_CLKEIEN_Pos) /*!< SYS_T::HIRCTIEN: CLKEIEN Mask */ + +#define SYS_HIRCTISTS_FREQLOCK_Pos (0) /*!< SYS_T::HIRCTISTS: FREQLOCK Position */ +#define SYS_HIRCTISTS_FREQLOCK_Msk (0x1ul << SYS_HIRCTISTS_FREQLOCK_Pos) /*!< SYS_T::HIRCTISTS: FREQLOCK Mask */ + +#define SYS_HIRCTISTS_TFAILIF_Pos (1) /*!< SYS_T::HIRCTISTS: TFAILIF Position */ +#define SYS_HIRCTISTS_TFAILIF_Msk (0x1ul << SYS_HIRCTISTS_TFAILIF_Pos) /*!< SYS_T::HIRCTISTS: TFAILIF Mask */ + +#define SYS_HIRCTISTS_CLKERRIF_Pos (2) /*!< SYS_T::HIRCTISTS: CLKERRIF Position */ +#define SYS_HIRCTISTS_CLKERRIF_Msk (0x1ul << SYS_HIRCTISTS_CLKERRIF_Pos) /*!< SYS_T::HIRCTISTS: CLKERRIF Mask */ + +#define SYS_HIRCTISTS_OVBDIF_Pos (3) /*!< SYS_T::HIRCTISTS: OVBDIF Position */ +#define SYS_HIRCTISTS_OVBDIF_Msk (0x1ul << SYS_HIRCTISTS_OVBDIF_Pos) /*!< SYS_T::HIRCTISTS: OVBDIF Mask */ + +#define SYS_IRCTCTL_FREQSEL_Pos (0) /*!< SYS_T::IRCTCTL: FREQSEL Position */ +#define SYS_IRCTCTL_FREQSEL_Msk (0x3ul << SYS_IRCTCTL_FREQSEL_Pos) /*!< SYS_T::IRCTCTL: FREQSEL Mask */ + +#define SYS_IRCTCTL_LOOPSEL_Pos (4) /*!< SYS_T::IRCTCTL: LOOPSEL Position */ +#define SYS_IRCTCTL_LOOPSEL_Msk (0x3ul << SYS_IRCTCTL_LOOPSEL_Pos) /*!< SYS_T::IRCTCTL: LOOPSEL Mask */ + +#define SYS_IRCTCTL_RETRYCNT_Pos (6) /*!< SYS_T::IRCTCTL: RETRYCNT Position */ +#define SYS_IRCTCTL_RETRYCNT_Msk (0x3ul << SYS_IRCTCTL_RETRYCNT_Pos) /*!< SYS_T::IRCTCTL: RETRYCNT Mask */ + +#define SYS_IRCTCTL_CESTOPEN_Pos (8) /*!< SYS_T::IRCTCTL: CESTOPEN Position */ +#define SYS_IRCTCTL_CESTOPEN_Msk (0x1ul << SYS_IRCTCTL_CESTOPEN_Pos) /*!< SYS_T::IRCTCTL: CESTOPEN Mask */ + +#define SYS_IRCTCTL_REFCKSEL_Pos (10) /*!< SYS_T::IRCTCTL: REFCKSEL Position */ +#define SYS_IRCTCTL_REFCKSEL_Msk (0x1ul << SYS_IRCTCTL_REFCKSEL_Pos) /*!< SYS_T::IRCTCTL: REFCKSEL Mask */ + +#define SYS_IRCTIEN_TFAILIEN_Pos (1) /*!< SYS_T::IRCTIEN: TFAILIEN Position */ +#define SYS_IRCTIEN_TFAILIEN_Msk (0x1ul << SYS_IRCTIEN_TFAILIEN_Pos) /*!< SYS_T::IRCTIEN: TFAILIEN Mask */ + +#define SYS_IRCTIEN_CLKEIEN_Pos (2) /*!< SYS_T::IRCTIEN: CLKEIEN Position */ +#define SYS_IRCTIEN_CLKEIEN_Msk (0x1ul << SYS_IRCTIEN_CLKEIEN_Pos) /*!< SYS_T::IRCTIEN: CLKEIEN Mask */ + +#define SYS_IRCTISTS_FREQLOCK_Pos (0) /*!< SYS_T::IRCTISTS: FREQLOCK Position */ +#define SYS_IRCTISTS_FREQLOCK_Msk (0x1ul << SYS_IRCTISTS_FREQLOCK_Pos) /*!< SYS_T::IRCTISTS: FREQLOCK Mask */ + +#define SYS_IRCTISTS_TFAILIF_Pos (1) /*!< SYS_T::IRCTISTS: TFAILIF Position */ +#define SYS_IRCTISTS_TFAILIF_Msk (0x1ul << SYS_IRCTISTS_TFAILIF_Pos) /*!< SYS_T::IRCTISTS: TFAILIF Mask */ + +#define SYS_IRCTISTS_CLKERRIF_Pos (2) /*!< SYS_T::IRCTISTS: CLKERRIF Position */ +#define SYS_IRCTISTS_CLKERRIF_Msk (0x1ul << SYS_IRCTISTS_CLKERRIF_Pos) /*!< SYS_T::IRCTISTS: CLKERRIF Mask */ + +#define SYS_REGLCTL_REGLCTL_Pos (0) /*!< SYS_T::REGLCTL: REGLCTL Position */ +#define SYS_REGLCTL_REGLCTL_Msk (0x1ul << SYS_REGLCTL_REGLCTL_Pos) /*!< SYS_T::REGLCTL: REGLCTL Mask */ + +#define SYS_PORDISAN_POROFFAN_Pos (0) /*!< SYS_T::PORDISAN: POROFFAN Position */ +#define SYS_PORDISAN_POROFFAN_Msk (0xfffful << SYS_PORDISAN_POROFFAN_Pos) /*!< SYS_T::PORDISAN: POROFFAN Mask */ + +#define SYS_CSERVER_VERSION_Pos (0) /*!< SYS_T::CSERVER: VERSION Position */ +#define SYS_CSERVER_VERSION_Msk (0xfful << SYS_CSERVER_VERSION_Pos) /*!< SYS_T::CSERVER: VERSION Mask */ + +#define SYS_PLCTL_PLSEL_Pos (0) /*!< SYS_T::PLCTL: PLSEL Position */ +#define SYS_PLCTL_PLSEL_Msk (0x3ul << SYS_PLCTL_PLSEL_Pos) /*!< SYS_T::PLCTL: PLSEL Mask */ + +#define SYS_PLCTL_LVSSTEP_Pos (16) /*!< SYS_T::PLCTL: LVSSTEP Position */ +#define SYS_PLCTL_LVSSTEP_Msk (0x3ful << SYS_PLCTL_LVSSTEP_Pos) /*!< SYS_T::PLCTL: LVSSTEP Mask */ + +#define SYS_PLCTL_LVSPRD_Pos (24) /*!< SYS_T::PLCTL: LVSPRD Position */ +#define SYS_PLCTL_LVSPRD_Msk (0xfful << SYS_PLCTL_LVSPRD_Pos) /*!< SYS_T::PLCTL: LVSPRD Mask */ + +#define SYS_PLSTS_PLCBUSY_Pos (0) /*!< SYS_T::PLSTS: PLCBUSY Position */ +#define SYS_PLSTS_PLCBUSY_Msk (0x1ul << SYS_PLSTS_PLCBUSY_Pos) /*!< SYS_T::PLSTS: PLCBUSY Mask */ + +#define SYS_PLSTS_PLSTATUS_Pos (8) /*!< SYS_T::PLSTS: PLSTATUS Position */ +#define SYS_PLSTS_PLSTATUS_Msk (0x3ul << SYS_PLSTS_PLSTATUS_Pos) /*!< SYS_T::PLSTS: PLSTATUS Mask */ + +#define SYS_AHBMCTL_INTACTEN_Pos (0) /*!< SYS_T::AHBMCTL: INTACTEN Position */ +#define SYS_AHBMCTL_INTACTEN_Msk (0x1ul << SYS_AHBMCTL_INTACTEN_Pos) /*!< SYS_T::AHBMCTL: INTACTEN Mask */ + +/**@}*/ /* SYS_CONST */ +/**@}*/ /* end of SYS register group */ + +/** + @addtogroup NMI NMI Controller (NMI) + Memory Mapped Structure for NMI Controller +@{ */ + +typedef struct +{ + + + /** + * @var NMI_T::NMIEN + * Offset: 0x00 NMI Source Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BODOUT |BOD NMI Source Enable (Write Protect) + * | | |0 = BOD NMI source Disabled. + * | | |1 = BOD NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[1] |IRC_INT |IRC TRIM NMI Source Enable (Write Protect) + * | | |0 = IRC TRIM NMI source Disabled. + * | | |1 = IRC TRIM NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[2] |PWRWU_INT |Power-down Mode Wake-up NMI Source Enable (Write Protect) + * | | |0 = Power-down mode wake-up NMI source Disabled. + * | | |1 = Power-down mode wake-up NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |SRAM_PERR |SRAM Parity Check NMI Source Enable (Write Protect) + * | | |0 = SRAM parity check error NMI source Disabled. + * | | |1 = SRAM parity check error NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[4] |CLKFAIL |Clock Fail Detected and IRC Auto Trim Interrupt NMI Source Enable (Write Protect) + * | | |0 = Clock fail detected and IRC Auto Trim interrupt NMI source Disabled. + * | | |1 = Clock fail detected and IRC Auto Trim interrupt NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[6] |RTC_INT |RTC NMI Source Enable (Write Protect) + * | | |0 = RTC NMI source Disabled. + * | | |1 = RTC NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7] |TAMPER_INT|TAMPER_INT NMI Source Enable (Write Protect) + * | | |0 = Backup register tamper detected NMI source Disabled. + * | | |1 = Backup register tamper detected NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[8] |EINT0 |External Interrupt From PA.6 or PB.5 Pin NMI Source Enable (Write Protect) + * | | |0 = External interrupt from PA.6 or PB.5 pin NMI source Disabled. + * | | |1 = External interrupt from PA.6 or PB.5 pin NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[9] |EINT1 |External Interrupt From PA.7, PB.4 or PD.15 Pin NMI Source Enable (Write Protect) + * | | |0 = External interrupt from PA.7, PB.4 or PD.15 pin NMI source Disabled. + * | | |1 = External interrupt from PA.7, PB.4 or PD.15 pin NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[10] |EINT2 |External Interrupt From PB.3 or PC.6 Pin NMI Source Enable (Write Protect) + * | | |0 = External interrupt from PB.3 or PC.6 pin NMI source Disabled. + * | | |1 = External interrupt from PB.3 or PC.6 pin NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[11] |EINT3 |External Interrupt From PB.2 or PC.7 Pin NMI Source Enable (Write Protect) + * | | |0 = External interrupt from PB.2 or PC.7 pin NMI source Disabled. + * | | |1 = External interrupt from PB.2 or PC.7 pin NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[12] |EINT4 |External Interrupt From PA.8, PB.6 or PF.15 Pin NMI Source Enable (Write Protect) + * | | |0 = External interrupt from PA.8, PB.6 or PF.15 pin NMI source Disabled. + * | | |1 = External interrupt from PA.8, PB.6 or PF.15 pin NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[13] |EINT5 |External Interrupt From PB.7 or PF.14 Pin NMI Source Enable (Write Protect) + * | | |0 = External interrupt from PB.7 or PF.14 pin NMI source Disabled. + * | | |1 = External interrupt from PB.7 or PF.14 pin NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[14] |UART0_INT |UART0 NMI Source Enable (Write Protect) + * | | |0 = UART0 NMI source Disabled. + * | | |1 = UART0 NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[15] |UART1_INT |UART1 NMI Source Enable (Write Protect) + * | | |0 = UART1 NMI source Disabled. + * | | |1 = UART1 NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var NMI_T::NMISTS + * Offset: 0x04 NMI Source Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BODOUT |BOD Interrupt Flag (Read Only) + * | | |0 = BOD interrupt is deasserted. + * | | |1 = BOD interrupt is asserted. + * |[1] |IRC_INT |IRC TRIM Interrupt Flag (Read Only) + * | | |0 = HIRC TRIM interrupt is deasserted. + * | | |1 = HIRC TRIM interrupt is asserted. + * |[2] |PWRWU_INT |Power-down Mode Wake-up Interrupt Flag (Read Only) + * | | |0 = Power-down mode wake-up interrupt is deasserted. + * | | |1 = Power-down mode wake-up interrupt is asserted. + * |[3] |SRAM_PERR |SRAM ParityCheck Error Interrupt Flag (Read Only) + * | | |0 = SRAM parity check error interrupt is deasserted. + * | | |1 = SRAM parity check error interrupt is asserted. + * |[4] |CLKFAIL |Clock Fail Detected or IRC Auto Trim Interrupt Flag (Read Only) + * | | |0 = Clock fail detected or IRC Auto Trim interrupt is deasserted. + * | | |1 = Clock fail detected or IRC Auto Trim interrupt is asserted. + * |[6] |RTC_INT |RTC Interrupt Flag (Read Only) + * | | |0 = RTC interrupt is deasserted. + * | | |1 = RTC interrupt is asserted. + * |[7] |TAMPER_INT|TAMPER_INT Interrupt Flag (Read Only) + * | | |0 = Backup register tamper detected interrupt is deasserted. + * | | |1 = Backup register tamper detected interrupt is asserted. + * |[8] |EINT0 |External Interrupt From PA.6 or PB.5 Pin Interrupt Flag (Read Only) + * | | |0 = External Interrupt from PA.6 or PB.5 interrupt is deasserted. + * | | |1 = External Interrupt from PA.6 or PB.5 interrupt is asserted. + * |[9] |EINT1 |External Interrupt From PA.7, PB.4 or PD.15 Pin Interrupt Flag (Read Only) + * | | |0 = External Interrupt from PA.7, PB.4 or PD.15 interrupt is deasserted. + * | | |1 = External Interrupt from PA.7, PB.4 or PD.15 interrupt is asserted. + * |[10] |EINT2 |External Interrupt From PB.3 or PC.6 Pin Interrupt Flag (Read Only) + * | | |0 = External Interrupt from PB.3 or PC.6 interrupt is deasserted. + * | | |1 = External Interrupt from PB.3 or PC.6 interrupt is asserted. + * |[11] |EINT3 |External Interrupt From PB.2 or PC.7 Pin Interrupt Flag (Read Only) + * | | |0 = External Interrupt from PB.2 or PC.7 interrupt is deasserted. + * | | |1 = External Interrupt from PB.2 or PC.7 interrupt is asserted. + * |[12] |EINT4 |External Interrupt From PA.8, PB.6 or PF.15 Pin Interrupt Flag (Read Only) + * | | |0 = External Interrupt from PA.8, PB.6 or PF.15 interrupt is deasserted. + * | | |1 = External Interrupt from PA.8, PB.6 or PF.15 interrupt is asserted. + * |[13] |EINT5 |External Interrupt From PB.7 or PF.14 Pin Interrupt Flag (Read Only) + * | | |0 = External Interrupt from PB.7 or PF.14 interrupt is deasserted. + * | | |1 = External Interrupt from PB.7 or PF.14 interrupt is asserted. + * |[14] |UART0_INT |UART0 Interrupt Flag (Read Only) + * | | |0 = UART1 interrupt is deasserted. + * | | |1 = UART1 interrupt is asserted. + * |[15] |UART1_INT |UART1 Interrupt Flag (Read Only) + * | | |0 = UART1 interrupt is deasserted. + * | | |1 = UART1 interrupt is asserted. + */ + __IO uint32_t NMIEN; /*!< [0x0000] NMI Source Interrupt Enable Register */ + __I uint32_t NMISTS; /*!< [0x0004] NMI Source Interrupt Status Register */ + +} NMI_T; + +/** + @addtogroup NMI_CONST NMI Bit Field Definition + Constant Definitions for NMI Controller +@{ */ + +#define NMI_NMIEN_BODOUT_Pos (0) /*!< NMI_T::NMIEN: BODOUT Position */ +#define NMI_NMIEN_BODOUT_Msk (0x1ul << NMI_NMIEN_BODOUT_Pos) /*!< NMI_T::NMIEN: BODOUT Mask */ + +#define NMI_NMIEN_IRC_INT_Pos (1) /*!< NMI_T::NMIEN: IRC_INT Position */ +#define NMI_NMIEN_IRC_INT_Msk (0x1ul << NMI_NMIEN_IRC_INT_Pos) /*!< NMI_T::NMIEN: IRC_INT Mask */ + +#define NMI_NMIEN_PWRWU_INT_Pos (2) /*!< NMI_T::NMIEN: PWRWU_INT Position */ +#define NMI_NMIEN_PWRWU_INT_Msk (0x1ul << NMI_NMIEN_PWRWU_INT_Pos) /*!< NMI_T::NMIEN: PWRWU_INT Mask */ + +#define NMI_NMIEN_SRAM_PERR_Pos (3) /*!< NMI_T::NMIEN: SRAM_PERR Position */ +#define NMI_NMIEN_SRAM_PERR_Msk (0x1ul << NMI_NMIEN_SRAM_PERR_Pos) /*!< NMI_T::NMIEN: SRAM_PERR Mask */ + +#define NMI_NMIEN_CLKFAIL_Pos (4) /*!< NMI_T::NMIEN: CLKFAIL Position */ +#define NMI_NMIEN_CLKFAIL_Msk (0x1ul << NMI_NMIEN_CLKFAIL_Pos) /*!< NMI_T::NMIEN: CLKFAIL Mask */ + +#define NMI_NMIEN_RTC_INT_Pos (6) /*!< NMI_T::NMIEN: RTC_INT Position */ +#define NMI_NMIEN_RTC_INT_Msk (0x1ul << NMI_NMIEN_RTC_INT_Pos) /*!< NMI_T::NMIEN: RTC_INT Mask */ + +#define NMI_NMIEN_TAMPER_INT_Pos (7) /*!< NMI_T::NMIEN: TAMPER_INT Position */ +#define NMI_NMIEN_TAMPER_INT_Msk (0x1ul << NMI_NMIEN_TAMPER_INT_Pos) /*!< NMI_T::NMIEN: TAMPER_INT Mask */ + +#define NMI_NMIEN_EINT0_Pos (8) /*!< NMI_T::NMIEN: EINT0 Position */ +#define NMI_NMIEN_EINT0_Msk (0x1ul << NMI_NMIEN_EINT0_Pos) /*!< NMI_T::NMIEN: EINT0 Mask */ + +#define NMI_NMIEN_EINT1_Pos (9) /*!< NMI_T::NMIEN: EINT1 Position */ +#define NMI_NMIEN_EINT1_Msk (0x1ul << NMI_NMIEN_EINT1_Pos) /*!< NMI_T::NMIEN: EINT1 Mask */ + +#define NMI_NMIEN_EINT2_Pos (10) /*!< NMI_T::NMIEN: EINT2 Position */ +#define NMI_NMIEN_EINT2_Msk (0x1ul << NMI_NMIEN_EINT2_Pos) /*!< NMI_T::NMIEN: EINT2 Mask */ + +#define NMI_NMIEN_EINT3_Pos (11) /*!< NMI_T::NMIEN: EINT3 Position */ +#define NMI_NMIEN_EINT3_Msk (0x1ul << NMI_NMIEN_EINT3_Pos) /*!< NMI_T::NMIEN: EINT3 Mask */ + +#define NMI_NMIEN_EINT4_Pos (12) /*!< NMI_T::NMIEN: EINT4 Position */ +#define NMI_NMIEN_EINT4_Msk (0x1ul << NMI_NMIEN_EINT4_Pos) /*!< NMI_T::NMIEN: EINT4 Mask */ + +#define NMI_NMIEN_EINT5_Pos (13) /*!< NMI_T::NMIEN: EINT5 Position */ +#define NMI_NMIEN_EINT5_Msk (0x1ul << NMI_NMIEN_EINT5_Pos) /*!< NMI_T::NMIEN: EINT5 Mask */ + +#define NMI_NMIEN_UART0_INT_Pos (14) /*!< NMI_T::NMIEN: UART0_INT Position */ +#define NMI_NMIEN_UART0_INT_Msk (0x1ul << NMI_NMIEN_UART0_INT_Pos) /*!< NMI_T::NMIEN: UART0_INT Mask */ + +#define NMI_NMIEN_UART1_INT_Pos (15) /*!< NMI_T::NMIEN: UART1_INT Position */ +#define NMI_NMIEN_UART1_INT_Msk (0x1ul << NMI_NMIEN_UART1_INT_Pos) /*!< NMI_T::NMIEN: UART1_INT Mask */ + +#define NMI_NMISTS_BODOUT_Pos (0) /*!< NMI_T::NMISTS: BODOUT Position */ +#define NMI_NMISTS_BODOUT_Msk (0x1ul << NMI_NMISTS_BODOUT_Pos) /*!< NMI_T::NMISTS: BODOUT Mask */ + +#define NMI_NMISTS_IRC_INT_Pos (1) /*!< NMI_T::NMISTS: IRC_INT Position */ +#define NMI_NMISTS_IRC_INT_Msk (0x1ul << NMI_NMISTS_IRC_INT_Pos) /*!< NMI_T::NMISTS: IRC_INT Mask */ + +#define NMI_NMISTS_PWRWU_INT_Pos (2) /*!< NMI_T::NMISTS: PWRWU_INT Position */ +#define NMI_NMISTS_PWRWU_INT_Msk (0x1ul << NMI_NMISTS_PWRWU_INT_Pos) /*!< NMI_T::NMISTS: PWRWU_INT Mask */ + +#define NMI_NMISTS_SRAM_PERR_Pos (3) /*!< NMI_T::NMISTS: SRAM_PERR Position */ +#define NMI_NMISTS_SRAM_PERR_Msk (0x1ul << NMI_NMISTS_SRAM_PERR_Pos) /*!< NMI_T::NMISTS: SRAM_PERR Mask */ + +#define NMI_NMISTS_CLKFAIL_Pos (4) /*!< NMI_T::NMISTS: CLKFAIL Position */ +#define NMI_NMISTS_CLKFAIL_Msk (0x1ul << NMI_NMISTS_CLKFAIL_Pos) /*!< NMI_T::NMISTS: CLKFAIL Mask */ + +#define NMI_NMISTS_RTC_INT_Pos (6) /*!< NMI_T::NMISTS: RTC_INT Position */ +#define NMI_NMISTS_RTC_INT_Msk (0x1ul << NMI_NMISTS_RTC_INT_Pos) /*!< NMI_T::NMISTS: RTC_INT Mask */ + +#define NMI_NMISTS_TAMPER_INT_Pos (7) /*!< NMI_T::NMISTS: TAMPER_INT Position */ +#define NMI_NMISTS_TAMPER_INT_Msk (0x1ul << NMI_NMISTS_TAMPER_INT_Pos) /*!< NMI_T::NMISTS: TAMPER_INT Mask */ + +#define NMI_NMISTS_EINT0_Pos (8) /*!< NMI_T::NMISTS: EINT0 Position */ +#define NMI_NMISTS_EINT0_Msk (0x1ul << NMI_NMISTS_EINT0_Pos) /*!< NMI_T::NMISTS: EINT0 Mask */ + +#define NMI_NMISTS_EINT1_Pos (9) /*!< NMI_T::NMISTS: EINT1 Position */ +#define NMI_NMISTS_EINT1_Msk (0x1ul << NMI_NMISTS_EINT1_Pos) /*!< NMI_T::NMISTS: EINT1 Mask */ + +#define NMI_NMISTS_EINT2_Pos (10) /*!< NMI_T::NMISTS: EINT2 Position */ +#define NMI_NMISTS_EINT2_Msk (0x1ul << NMI_NMISTS_EINT2_Pos) /*!< NMI_T::NMISTS: EINT2 Mask */ + +#define NMI_NMISTS_EINT3_Pos (11) /*!< NMI_T::NMISTS: EINT3 Position */ +#define NMI_NMISTS_EINT3_Msk (0x1ul << NMI_NMISTS_EINT3_Pos) /*!< NMI_T::NMISTS: EINT3 Mask */ + +#define NMI_NMISTS_EINT4_Pos (12) /*!< NMI_T::NMISTS: EINT4 Position */ +#define NMI_NMISTS_EINT4_Msk (0x1ul << NMI_NMISTS_EINT4_Pos) /*!< NMI_T::NMISTS: EINT4 Mask */ + +#define NMI_NMISTS_EINT5_Pos (13) /*!< NMI_T::NMISTS: EINT5 Position */ +#define NMI_NMISTS_EINT5_Msk (0x1ul << NMI_NMISTS_EINT5_Pos) /*!< NMI_T::NMISTS: EINT5 Mask */ + +#define NMI_NMISTS_UART0_INT_Pos (14) /*!< NMI_T::NMISTS: UART0_INT Position */ +#define NMI_NMISTS_UART0_INT_Msk (0x1ul << NMI_NMISTS_UART0_INT_Pos) /*!< NMI_T::NMISTS: UART0_INT Mask */ + +#define NMI_NMISTS_UART1_INT_Pos (15) /*!< NMI_T::NMISTS: UART1_INT Position */ +#define NMI_NMISTS_UART1_INT_Msk (0x1ul << NMI_NMISTS_UART1_INT_Pos) /*!< NMI_T::NMISTS: UART1_INT Mask */ + +/**@}*/ /* NMI_CONST */ +/**@}*/ /* end of NMI register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __SYS_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/system_M480.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/system_M480.h new file mode 100644 index 0000000000000000000000000000000000000000..fe12ac2f5fe4237a9751ae8a7996f2878519c7e2 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/system_M480.h @@ -0,0 +1,76 @@ +/**************************************************************************//** + * @file system_M480.h + * @version V1.00 + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for M480 + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#ifndef __SYSTEM_M480_H__ +#define __SYSTEM_M480_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + +#ifndef __HSI +#define __HSI (12000000UL) /*!< PLL default output is 50MHz */ +#endif + +#ifndef __HXT +#define __HXT (12000000UL) /*!< External Crystal Clock Frequency */ +#endif + +#ifndef __LXT +#define __LXT (32768UL) /*!< External Crystal Clock Frequency 32.768KHz */ +#endif + +#define __HIRC (12000000UL) /*!< Internal 12M RC Oscillator Frequency */ +#define __LIRC (10000UL) /*!< Internal 10K RC Oscillator Frequency */ +#define __SYS_OSC_CLK ( ___HSI) /* Main oscillator frequency */ + + +#define __SYSTEM_CLOCK (1UL*__HXT) + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +extern uint32_t CyclesPerUs; /*!< Cycles per micro second */ +extern uint32_t PllClock; /*!< PLL Output Clock Frequency */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the micro controller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_M480_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/timer_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/timer_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..7c3b4acdac602eb72a10c99aa77c3feeec823104 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/timer_reg.h @@ -0,0 +1,1094 @@ +/**************************************************************************//** + * @file timer_reg.h + * @version V1.00 + * @brief TIMER register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __TIMER_REG_H__ +#define __TIMER_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup TIMER Timer Controller(TIMER) + Memory Mapped Structure for TIMER Controller +@{ */ + +typedef struct +{ + + + /** + * @var TIMER_T::CTL + * Offset: 0x00 Timer Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |PSC |Prescale Counter + * | | |Timer input clock or event source is divided by (PSC+1) before it is fed to the timer up counter + * | | |If this field is 0 (PSC = 0), then there is no scaling. + * | | |Note: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value. + * |[19] |INTRGEN |Inter-timer Trigger Mode Enable Control + * | | |Setting this bit will enable the inter-timer trigger capture function. + * | | |The Timer0/2 will be in event counter mode and counting with external clock source or event + * | | |Also, Timer1/3 will be in trigger-counting mode of capture function. + * | | |0 = Inter-Timer Trigger Capture mode Disabled. + * | | |1 = Inter-Timer Trigger Capture mode Enabled. + * | | |Note: For Timer1/3, this bit is ignored and the read back value is always 0. + * |[20] |PERIOSEL |Periodic Mode Behavior Selection Enable Bit + * | | |0 = The behavior selection in periodic mode is Disabled. + * | | |When user updates CMPDAT while timer is running in periodic mode, + * | | |CNT will be reset to default value. + * | | |1 = The behavior selection in periodic mode is Enabled. + * | | |When user update CMPDAT while timer is running in periodic mode, the limitations as bellows list, + * | | |If updated CMPDAT value > CNT, CMPDAT will be updated and CNT keep running continually. + * | | |If updated CMPDAT value = CNT, timer time-out interrupt will be asserted immediately. + * | | |If updated CMPDAT value < CNT, CNT will be reset to default value. + * |[21] |TGLPINSEL |Toggle-output Pin Select + * | | |0 = Toggle mode output to TMx (Timer Event Counter Pin). + * | | |1 = Toggle mode output to TMx_EXT (Timer External Capture Pin). + * |[22] |CAPSRC |Capture Pin Source Selection + * | | |0 = Capture Function source is from TMx_EXT (x= 0~3) pin. + * | | |1 = Capture Function source is from internal ACMP output signal + * | | |User can set ACMPSSEL (TIMERx_EXTCTL[8]) to decide which internal ACMP output signal as timer capture source. + * |[23] |WKEN |Wake-up Function Enable Bit + * | | |If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU. + * | | |0 = Wake-up function Disabled if timer interrupt signal generated. + * | | |1 = Wake-up function Enabled if timer interrupt signal generated. + * |[24] |EXTCNTEN |Event Counter Mode Enable Bit + * | | |This bit is for external counting pin function enabled. + * | | |0 = Event counter mode Disabled. + * | | |1 = Event counter mode Enabled. + * | | |Note: When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source. + * |[25] |ACTSTS |Timer Active Status Bit (Read Only) + * | | |This bit indicates the 24-bit up counter status. + * | | |0 = 24-bit up counter is not active. + * | | |1 = 24-bit up counter is active. + * | | |Note: This bit may active when CNT 0 transition to CNT 1. + * |[28:27] |OPMODE |Timer Counting Mode Select + * | | |00 = The Timer controller is operated in One-shot mode. + * | | |01 = The Timer controller is operated in Periodic mode. + * | | |10 = The Timer controller is operated in Toggle-output mode. + * | | |11 = The Timer controller is operated in Continuous Counting mode. + * |[29] |INTEN |Timer Interrupt Enable Bit + * | | |0 = Timer time-out interrupt Disabled. + * | | |1 = Timer time-out interrupt Enabled. + * | | |Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU. + * |[30] |CNTEN |Timer Counting Enable Bit + * | | |0 = Stops/Suspends counting. + * | | |1 = Starts counting. + * | | |Note1: In stop status, and then set CNTEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value. + * | | |Note2: This bit is auto-cleared by hardware in one-shot mode (TIMER_CTL[28:27] = 00) when the timer time-out interrupt flag TIF (TIMERx_INTSTS[0]) is generated. + * | | |Note3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not. + * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control (Write Protect) + * | | |0 = ICE debug mode acknowledgement effects TIMER counting. + * | | |TIMER counter will be held while CPU is held by ICE. + * | | |1 = ICE debug mode acknowledgement Disabled. + * | | |TIMER counter will keep going no matter CPU is held by ICE or not. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var TIMER_T::CMP + * Offset: 0x04 Timer Comparator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CMPDAT |Timer Comparator Value + * | | |CMPDAT is a 24-bit compared value register + * | | |When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1. + * | | |Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT). + * | | |Note1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state. + * | | |Note2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field + * | | |But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field. + * @var TIMER_T::INTSTS + * Offset: 0x08 Timer Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TIF |Timer Interrupt Flag + * | | |This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value. + * | | |0 = No effect. + * | | |1 = CNT value matches the CMPDAT value. + * | | |Note: This bit is cleared by writing 1 to it. + * |[1] |TWKF |Timer Wake-up Flag + * | | |This bit indicates the interrupt wake-up flag status of timer. + * | | |0 = Timer does not cause CPU wake-up. + * | | |1 = CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated. + * | | |Note: This bit is cleared by writing 1 to it. + * @var TIMER_T::CNT + * Offset: 0x0C Timer Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CNT |Timer Data Register + * | | |Read operation. + * | | |Read this register to get CNT value. For example: + * | | |If EXTCNTEN (TIMERx_CTL[24] ) is 0, user can read CNT value for getting current 24-bit counter value. + * | | |If EXTCNTEN (TIMERx_CTL[24] ) is 1, user can read CNT value for getting current 24-bit event input counter value. + * | | |Write operation. + * | | |Writing any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter. + * |[31] |RSTACT |Timer Data Register Reset Active (Read Only) + * | | |This bit indicates if the counter reset operation active. + * | | |When user writes this CNT register, timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter + * | | |At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress + * | | |Once the counter reset operation done, timer clear this bit to 0 automatically. + * | | |0 = Reset operation is done. + * | | |1 = Reset operation triggered by writing TIMERx_CNT is in progress. + * | | |Note: This bit is read only. + * @var TIMER_T::CAP + * Offset: 0x10 Timer Capture Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CAPDAT |Timer Capture Data Register + * | | |When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field. + * @var TIMER_T::EXTCTL + * Offset: 0x14 Timer External Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTPHASE |Timer External Count Phase + * | | |This bit indicates the detection phase of external counting pin TMx (x= 0~3). + * | | |0 = A falling edge of external counting pin will be counted. + * | | |1 = A rising edge of external counting pin will be counted. + * |[3] |CAPEN |Timer External Capture Pin Enable Bit + * | | |This bit enables the TMx_EXT capture pin input function. + * | | |0 =TMx_EXT (x= 0~3) pin Disabled. + * | | |1 =TMx_EXT (x= 0~3) pin Enabled. + * |[4] |CAPFUNCS |Capture Function Selection + * | | |0 = External Capture Mode Enabled. + * | | |1 = External Reset Mode Enabled. + * | | |Note1: When CAPFUNCS is 0, transition on TMx_EXT (x= 0~3) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field. + * | | |Note2: When CAPFUNCS is 1, transition on TMx_EXT (x= 0~3) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field then CNT value will be reset immediately. + * |[5] |CAPIEN |Timer External Capture Interrupt Enable Bit + * | | |0 = TMx_EXT (x= 0~3) pin detection Interrupt Disabled. + * | | |1 = TMx_EXT (x= 0~3) pin detection Interrupt Enabled. + * | | |Note: CAPIEN is used to enable timer external interrupt + * | | |If CAPIEN enabled, timer will rise an interrupt when CAPIF (TIMERx_EINTSTS[0]) is 1. + * | | |For example, while CAPIEN = 1, CAPEN = 1, and CAPEDGE = 00, a 1 to 0 transition on the TMx_EXT pin will cause the CAPIF to be set then the interrupt signal is generated and sent to NVIC to inform CPU. + * |[6] |CAPDBEN |Timer External Capture Pin De-bounce Enable Bit + * | | |0 = TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Disabled. + * | | |1 = TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Enabled. + * | | |Note: If this bit is enabled, the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit. + * |[7] |CNTDBEN |Timer Counter Pin De-bounce Enable Bit + * | | |0 = TMx (x= 0~3) pin de-bounce Disabled. + * | | |1 = TMx (x= 0~3) pin de-bounce Enabled. + * | | |Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit. + * |[8:10] |ICAPSEL |Internal Capture Source Select + * | | |000 = Capture Function source is from internal ACMP0 output signal. + * | | |001 = Capture Function source is from internal ACMP1 output signal. + * | | |010 = Capture Function source is from HXT. + * | | |011 = Capture Function source is from LXT. + * | | |100 = Capture Function source is from HIRC. + * | | |101 = Capture Function source is from LIRC. + * | | |110 = Reserved. + * | | |111 = Reserved. + * | | |Note: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1. + * |[14:12] |CAPEDGE |Timer External Capture Pin Edge Detect + * | | |When first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0. + * | | |000 = Capture event occurred when detect falling edge transfer on TMx_EXT (x= 0~3) pin. + * | | |001 = Capture event occurred when detect rising edge transfer on TMx_EXT (x= 0~3) pin. + * | | |010 = Capture event occurred when detect both falling and rising edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at falling edge transfer. + * | | |011 = Capture event occurred when detect both rising and falling edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at rising edge transfer.. + * | | |110 = First capture event occurred at falling edge, follows capture events are at rising edge transfer on TMx_EXT (x= 0~3) pin. + * | | |111 = First capture event occurred at rising edge, follows capture events are at falling edge transfer on TMx_EXT (x= 0~3) pin. + * | | |100, 101 = Reserved. + * |[16] |ECNTSSEL |Event Counter Source Selection to Trigger Event Counter Function + * | | |0 = Event Counter input source is from TMx (x= 0~3) pin. + * | | |1 = Event Counter input source is from USB internal SOF output signal. + * |[31:28] |CAPDIVSCL |Timer Capture Source Divider + * | | |This bits indicate the divide scale for capture source divider + * | | |0000 = Capture source/1. + * | | |0001 = Capture source/2. + * | | |0010 = Capture source/4. + * | | |0011 = Capture source/8. + * | | |0100 = Capture source/16. + * | | |0101 = Capture source/32. + * | | |0110 = Capture source/64. + * | | |0111 = Capture source/128. + * | | |1000 = Capture source/256. + * | | |1001~1111 = Reserved. + * | | |Note: Sets INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source. * @var TIMER_T::EINTSTS + * Offset: 0x18 Timer External Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPIF |Timer External Capture Interrupt Flag + * | | |This bit indicates the timer external capture interrupt flag status. + * | | |0 = TMx_EXT (x= 0~3) pin interrupt did not occur. + * | | |1 = TMx_EXT (x= 0~3) pin interrupt occurred. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2: When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT (x= 0~3) pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, this bit will set to 1 by hardware. + * | | |Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status + * | | |If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value. + * @var TIMER_T::TRGCTL + * Offset: 0x1C Timer Trigger Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TRGSSEL |Trigger Source Select Bit + * | | |This bit is used to select internal trigger source is form timer time-out interrupt signal or + * | | |capture interrupt signal. + * | | |0 = Time-out interrupt signal is used to internal trigger EPWM, BPWM, PDMA, DAC, and EADC. + * | | |1 = Capture interrupt signal is used to internal trigger EPWM, BPWM, PDMA, DAC, and EADC. + * |[1] |TRGEPWM |Trigger EPWM and BPWM Enable Bit + * | | |If this bit is set to 1, each timer time-out event or capture event can be as EPWM and BPWM counter clock source. + * | | |0 = Timer interrupt trigger EPWM and BPWM Disabled. + * | | |1 = Timer interrupt trigger EPWM and BPWM Enabled. + * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal as EPWM and BPWM counter clock source. + * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal as EPWM counter clock source. + * |[2] |TRGEADC |Trigger EADC Enable Bit + * | | |If this bit is set to 1, each timer time-out event or capture event can be triggered EADC conversion. + * | | |0 = Timer interrupt trigger EADC Disabled. + * | | |1 = Timer interrupt trigger EADC Enabled. + * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger EADC conversion. + * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger EADC conversion. + * |[3] |TRGDAC |Trigger DAC Enable Bit + * | | |If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered DAC. + * | | |0 = Timer interrupt trigger DAC Disabled. + * | | |1 = Timer interrupt trigger DAC Enabled. + * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger DAC. + * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger DAC. + * |[4] |TRGPDMA |Trigger PDMA Enable Bit + * | | |If this bit is set to 1, each timer time-out event or capture event can be triggered PDMA transfer. + * | | |0 = Timer interrupt trigger PDMA Disabled. + * | | |1 = Timer interrupt trigger PDMA Enabled. + * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger PDMA transfer. + * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger PDMA transfer. + * @var TIMER_T::ALTCTL + * Offset: 0x20 Timer Alternative Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FUNCSEL |Function Selection + * | | |0 = Timer controller is used as timer function. + * | | |1 = Timer controller is used as PWM function. + * | | |Note: When timer is used as PWM, the clock source of time controller will be forced to PCLKx automatically. + * @var TIMER_T::PWMCTL + * Offset: 0x40 Timer PWM Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTEN |PWM Counter Enable Bit + * | | |0 = PWM counter and clock prescale Stop Running. + * | | |1 = PWM counter and clock prescale Start Running. + * |[2:1] |CNTTYPE |PWM Counter Behavior Type + * | | |00 = Up count type. + * | | |01 = Down count type. + * | | |10 = Up-down count type. + * | | |11 = Reserved. + * |[3] |CNTMODE |PWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[8] |CTRLD |Center Re-load + * | | |In up-down count type, PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period. + * |[9] |IMMLDEN |Immediately Load Enable Bit + * | | |0 = PERIOD will load to PBUF when current PWM period is completed no matter CTRLD is enabled/disabled + * | | |If CTRLD is disabled, CMP will load to CMPBUF when current PWM period is completed; if CTRLD is enabled in up-down count type, CMP will load to CMPBUF at the center point of current period. + * | | |1 = PERIOD/CMP will load to PBUF/CMPBUF immediately when user update PERIOD/CMP. + * | | |Note: If IMMLDEN is enabled, CTRLD will be invalid. + * |[16] |OUTMODE |PWM Output Mode + * | | |This bit controls the output mode of corresponding PWM channel. + * | | |0 = PWM independent mode. + * | | |1 = PWM complementary mode. + * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect) + * | | |If debug mode counter halt is enabled, PWM counter will keep current value until exit ICE debug mode. + * | | |0 = ICE debug mode counter halt disable. + * | | |1 = ICE debug mode counter halt enable. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable Bit (Write Protect) + * | | |0 = ICE debug mode acknowledgement effects PWM output. + * | | |PWM output pin will be forced as tri-state while ICE debug mode acknowledged. + * | | |1 = ICE debug mode acknowledgement disabled. + * | | |PWM output pin will keep output no matter ICE debug mode acknowledged or not. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * @var TIMER_T::PWMCLKSRC + * Offset: 0x44 Timer PWM Counter Clock Source Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |CLKSRC |PWM Counter Clock Source Select + * | | |The PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event. + * | | |000 = TMRx_CLK. + * | | |001 = Internal TIMER0 time-out or capture event. + * | | |010 = Internal TIMER1 time-out or capture event. + * | | |011 = Internal TIMER2 time-out or capture event. + * | | |100 = Internal TIMER3 time-out or capture event. + * | | |Others = Reserved. + * | | |Note: If TIMER0 PWM function is enabled, the PWM counter clock source can be selected from TMR0_CLK, TIMER1 interrupt events, TIMER2 interrupt events, or TIMER3 interrupt events. + * @var TIMER_T::PWMCLKPSC + * Offset: 0x48 Timer PWM Counter Clock Pre-scale Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CLKPSC |PWM Counter Clock Pre-scale + * | | |The active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1) + * | | |If CLKPSC is 0, then there is no scaling in PWM counter clock source. + * @var TIMER_T::PWMCNTCLR + * Offset: 0x4C Timer PWM Clear Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTCLR |Clear PWM Counter Control Bit + * | | |It is automatically cleared by hardware. + * | | |0 = No effect. + * | | |1 = Clear 16-bit PWM counter to 0x10000 in up and up-down count type and reset counter value to PERIOD in down count type. + * @var TIMER_T::PWMPERIOD + * Offset: 0x50 Timer PWM Period Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PERIOD |PWM Period Register + * | | |In up count type: PWM counter counts from 0 to PERIOD, and restarts from 0. + * | | |In down count type: PWM counter counts from PERIOD to 0, and restarts from PERIOD. + * | | |In up-down count type: PWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. + * | | |In up and down count type: + * | | |PWM period time = (PERIOD + 1) * (CLKPSC + 1) * TMRx_PWMCLK. + * | | |In up-down count type: + * | | |PWM period time = 2 * PERIOD * (CLKPSC+ 1) * TMRx_PWMCLK. + * | | |Note: User should take care DIRF (TIMERx_PWMCNT[16]) bit in up/down/up-down count type to monitor current counter direction in each count type. + * @var TIMER_T::PWMCMPDAT + * Offset: 0x54 Timer PWM Comparator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMP |PWM Comparator Register + * | | |PWM CMP is used to compare with PWM CNT to generate PWM output waveform, interrupt events and trigger ADC to start convert. + * @var TIMER_T::PWMDTCTL + * Offset: 0x58 Timer PWM Dead-Time Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |DTCNT |Dead-time Counter (Write Protect) + * | | |The dead-time can be calculated from the following two formulas: + * | | |Dead-time = (DTCNT[11:0] + 1) * TMRx_PWMCLK, if DTCKSEL is 0. + * | | |Dead-time = (DTCNT[11:0] + 1) * TMRx_PWMCLK * (CLKPSC + 1), if DTCKSEL is 1. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[16] |DTEN |Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect) + * | | |Dead-time insertion function is only active when PWM complementary mode is enabled + * | | |If dead- time insertion is inactive, the outputs of PWMx_CH0 and PWMx_CH1 are complementary without any delay. + * | | |0 = Dead-time insertion Disabled on the pin pair. + * | | |1 = Dead-time insertion Enabled on the pin pair. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[24] |DTCKSEL |Dead-time Clock Select (Write Protect) + * | | |0 = Dead-time clock source from TMRx_PWMCLK without counter clock prescale. + * | | |1 = Dead-time clock source from TMRx_PWMCLK with counter clock prescale. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * @var TIMER_T::PWMCNT + * Offset: 0x5C Timer PWM Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CNT |PWM Counter Value Register (Read Only) + * | | |User can monitor CNT to know the current counter value in 16-bit period counter. + * |[16] |DIRF |PWM Counter Direction Indicator Flag (Read Only) + * | | |0 = Counter is active in down count. + * | | |1 = Counter is active up count. + * @var TIMER_T::PWMMSKEN + * Offset: 0x60 Timer PWM Output Mask Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKEN0 |PWMx_CH0 Output Mask Enable Bit + * | | |The PWMx_CH0 output signal will be masked when this bit is enabled + * | | |The PWMx_CH0 will output MSKDAT0 (TIMER_PWMMSK[0]) data. + * | | |0 = PWMx_CH0 output signal is non-masked. + * | | |1 = PWMx_CH0 output signal is masked and output MSKDAT0 data. + * |[1] |MSKEN1 |PWMx_CH1 Output Mask Enable Bit + * | | |The PWMx_CH1 output signal will be masked when this bit is enabled + * | | |The PWMx_CH1 will output MSKDAT1 (TIMER_PWMMSK[1]) data. + * | | |0 = PWMx_CH1 output signal is non-masked. + * | | |1 = PWMx_CH1 output signal is masked and output MSKDAT1 data. + * @var TIMER_T::PWMMSK + * Offset: 0x64 Timer PWM Output Mask Data Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKDAT0 |PWMx_CH0 Output Mask Data Control Bit + * | | |This bit is used to control the output state of PWMx_CH0 pin when PWMx_CH0 output mask function is enabled (MSKEN0 = 1). + * | | |0 = Output logic Low to PWMx_CH0. + * | | |1 = Output logic High to PWMx_CH0. + * |[1] |MSKDAT1 |PWMx_CH1 Output Mask Data Control Bit + * | | |This bit is used to control the output state of PWMx_CH1 pin when PWMx_CH1 output mask function is enabled (MSKEN1 = 1). + * | | |0 = Output logic Low to PWMx_CH1. + * | | |1 = Output logic High to PWMx_CH1. + * @var TIMER_T::PWMBNF + * Offset: 0x68 Timer PWM Brake Pin Noise Filter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKNFEN |Brake Pin Noise Filter Enable Bit + * | | |0 = Pin noise filter detect of PWMx_BRAKEy Disabled. + * | | |1 = Pin noise filter detect of PWMx_BRAKEy Enabled. + * |[3:1] |BRKNFSEL |Brake Pin Noise Filter Clock Selection + * | | |000 = Noise filter clock is PCLKx. + * | | |001 = Noise filter clock is PCLKx/2. + * | | |010 = Noise filter clock is PCLKx/4. + * | | |011 = Noise filter clock is PCLKx/8. + * | | |100 = Noise filter clock is PCLKx/16. + * | | |101 = Noise filter clock is PCLKx/32. + * | | |110 = Noise filter clock is PCLKx/64. + * | | |111 = Noise filter clock is PCLKx/128. + * |[6:4] |BRKFCNT |Brake Pin Noise Filter Count + * | | |The fields is used to control the active noise filter sample time. + * | | |Once noise filter sample time = (Period time of BRKDBCS) * BRKFCNT. + * |[7] |BRKPINV |Brake Pin Detection Control Bit + * | | |0 = Brake pin event will be detected if PWMx_BRAKEy pin status transfer from low to high in edge-detect, or pin status is high in level-detect. + * | | |1 = Brake pin event will be detected if PWMx_BRAKEy pin status transfer from high to low in edge-detect, or pin status is low in level-detect . + * |[17:16] |BKPINSRC |Brake Pin Source Select + * | | |00 = Brake pin source comes from PWM0_BRAKE0 pin. + * | | |01 = Brake pin source comes from PWM0_BRAKE1 pin. + * | | |10 = Brake pin source comes from PWM1_BRAKE0 pin. + * | | |11 = Brake pin source comes from PWM1_BRAKE1 pin. + * @var TIMER_T::PWMFAILBRK + * Offset: 0x6C Timer PWM System Fail Brake Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CSSBRKEN |Clock Security System Detection Trigger PWM Brake Function Enable Bit + * | | |0 = Brake Function triggered by clock fail detection Disabled. + * | | |1 = Brake Function triggered by clock fail detection Enabled. + * |[1] |BODBRKEN |Brown-out Detection Trigger PWM Brake Function Enable Bit + * | | |0 = Brake Function triggered by BOD event Disabled. + * | | |1 = Brake Function triggered by BOD event Enabled. + * |[2] |RAMBRKEN |SRAM Parity Error Detection Trigger PWM Brake Function Enable Bit + * | | |0 = Brake Function triggered by SRAM parity error detection Disabled. + * | | |1 = Brake Function triggered by SRAM parity error detection Enabled. + * |[3] |CORBRKEN |Core Lockup Detection Trigger PWM Brake Function Enable Bit + * | | |0 = Brake Function triggered by core lockup event Disabled. + * | | |1 = Brake Function triggered by core lockup event Enabled. + * @var TIMER_T::PWMBRKCTL + * Offset: 0x70 Timer PWM Brake Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CPO0EBEN |Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect) + * | | |0 = Internal ACMP0_O signal as edge-detect brake source Disabled. + * | | |1 = Internal ACMP0_O signal as edge-detect brake source Enabled. + * | | |Note1: Only internal ACMP0_O signal from low to high will be detected as brake event. + * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. + * |[1] |CPO1EBEN |Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect) + * | | |0 = Internal ACMP1_O signal as edge-detect brake source Disabled. + * | | |1 = Internal ACMP1_O signal as edge-detect brake source Enabled. + * | | |Note1: Only internal ACMP1_O signal from low to high will be detected as brake event. + * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. + * |[4] |BRKPEEN |Enable TM_BRAKEx Pin As Edge-detect Brake Source (Write Protect) + * | | |0 = PWMx_BRAKEy pin event as edge-detect brake source Disabled. + * | | |1 = PWMx_BRAKEy pin event as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[7] |SYSEBEN |Enable System Fail As Edge-detect Brake Source (Write Protect) + * | | |0 = System fail condition as edge-detect brake source Disabled. + * | | |1 = System fail condition as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[8] |CPO0LBEN |Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect) + * | | |0 = Internal ACMP0_O signal as level-detect brake source Disabled. + * | | |1 = Internal ACMP0_O signal as level-detect brake source Enabled. + * | | |Note1: Only internal ACMP0_O signal from low to high will be detected as brake event. + * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. + * |[9] |CPO1LBEN |Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect) + * | | |0 = Internal ACMP1_O signal as level-detect brake source Disabled. + * | | |1 = Internal ACMP1_O signal as level-detect brake source Enabled. + * | | |Note1: Only internal ACMP1_O signal from low to high will be detected as brake event. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[12] |BRKPLEN |Enable TM_BRAKEx Pin As Level-detect Brake Source (Write Protect) + * | | |0 = PWMx_BRAKEy pin event as level-detect brake source Disabled. + * | | |1 = PWMx_BRAKEy pin event as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[15] |SYSLBEN |Enable System Fail As Level-detect Brake Source (Write Protect) + * | | |0 = System fail condition as level-detect brake source Disabled. + * | | |1 = System fail condition as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[17:16] |BRKAEVEN |PWM Brake Action Select for PWMx_CH0 (Write Protect) + * | | |00 = PWMx_BRAKEy brake event will not affect PWMx_CH0 output. + * | | |01 = PWMx_CH0 output tri-state when PWMx_BRAKEy brake event happened. + * | | |10 = PWMx_CH0 output low level when PWMx_BRAKEy brake event happened. + * | | |11 = PWMx_CH0 output high level when PWMx_BRAKEy brake event happened. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[19:18] |BRKAODD |PWM Brake Action Select for PWMx_CH1 (Write Protect) + * | | |00 = PWMx_BRAKEy brake event will not affect PWMx_CH1 output. + * | | |01 = PWMx_CH1 output tri-state when PWMx_BRAKEy brake event happened. + * | | |10 = PWMx_CH1 output low level when PWMx_BRAKEy brake event happened. + * | | |11 = PWMx_CH1 output high level when PWMx_BRAKEy brake event happened. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * @var TIMER_T::PWMPOLCTL + * Offset: 0x74 Timer PWM Pin Output Polar Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PINV0 |PWMx_CH0 Output Pin Polar Control Bit + * | | |The bit is used to control polarity state of PWMx_CH0 output pin. + * | | |0 = PWMx_CH0 output pin polar inverse Disabled. + * | | |1 = PWMx_CH0 output pin polar inverse Enabled. + * |[1] |PINV1 |PWMx_CH1 Output Pin Polar Control Bit + * | | |The bit is used to control polarity state of PWMx_CH1 output pin. + * | | |0 = PWMx_CH1 output pin polar inverse Disabled. + * | | |1 = PWMx_CH1 output pin polar inverse Enabled. + * @var TIMER_T::PWMPOEN + * Offset: 0x78 Timer PWM Pin Output Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |POEN0 |PWMx_CH0 Output Pin Enable Bit + * | | |0 = PWMx_CH0 pin at tri-state mode. + * | | |1 = PWMx_CH0 pin in output mode. + * |[1] |POEN1 |PWMx_CH1 Output Pin Enable Bit + * | | |0 = PWMx_CH1 pin at tri-state mode. + * | | |1 = PWMx_CH1 pin in output mode. + * @var TIMER_T::PWMSWBRK + * Offset: 0x7C Timer PWM Software Trigger Brake Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKETRG |Software Trigger Edge-detect Brake Source (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger PWM edge-detect brake source, then BRKEIF0 and BRKEIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[8] |BRKLTRG |Software Trigger Level-detect Brake Source (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger PWM level-detect brake source, then BRKLIF0 and BRKLIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * @var TIMER_T::PWMINTEN0 + * Offset: 0x80 Timer PWM Interrupt Enable Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIEN |PWM Zero Point Interrupt Enable Bit + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * |[1] |PIEN |PWM Period Point Interrupt Enable Bit + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note: When in up-down count type, period point means the center point of current PWM period. + * |[2] |CMPUIEN |PWM Compare Up Count Interrupt Enable Bit + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[3] |CMPDIEN |PWM Compare Down Count Interrupt Enable Bit + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * @var TIMER_T::PWMINTEN1 + * Offset: 0x84 Timer PWM Interrupt Enable Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKEIEN |PWM Edge-detect Brake Interrupt Enable (Write Protect) + * | | |0 = PWM edge-detect brake interrupt Disabled. + * | | |1 = PWM edge-detect brake interrupt Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[8] |BRKLIEN |PWM Level-detect Brake Interrupt Enable (Write Protect) + * | | |0 = PWM level-detect brake interrupt Disabled. + * | | |1 = PWM level-detect brake interrupt Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * @var TIMER_T::PWMINTSTS0 + * Offset: 0x88 Timer PWM Interrupt Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIF |PWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when TIMERx_PWM counter reaches zero. + * | | |Note: This bit is cleared by writing 1 to it. + * |[1] |PIF |PWM Period Point Interrupt Flag + * | | |This bit is set by hardware when TIMERx_PWM counter reaches PERIOD. + * | | |Note1: When in up-down count type, PIF flag means the center point flag of current PWM period. + * | | |Note2: This bit is cleared by writing 1 to it. + * |[2] |CMPUIF |PWM Compare Up Count Interrupt Flag + * | | |This bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP. + * | | |Note1: If CMP equal to PERIOD, there is no CMPUIF flag in up count type and up-down count type. + * | | |Note2: This bit is cleared by writing 1 to it. + * |[3] |CMPDIF |PWM Compare Down Count Interrupt Flag + * | | |This bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP. + * | | |Note1: If CMP equal to PERIOD, there is no CMPDIF flag in down count type. + * | | |Note2: This bit is cleared by writing 1 to it. + * @var TIMER_T::PWMINTSTS1 + * Offset: 0x8C Timer PWM Interrupt Status Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKEIF0 |Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect) + * | | |0 = PWMx_CH0 edge-detect brake event do not happened. + * | | |1 = PWMx_CH0 edge-detect brake event happened. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. + * |[1] |BRKEIF1 |Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect) + * | | |0 = PWMx_CH1 edge-detect brake event do not happened. + * | | |1 = PWMx_CH1 edge-detect brake event happened. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. + * |[8] |BRKLIF0 |Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect) + * | | |0 = PWMx_CH0 level-detect brake event do not happened. + * | | |1 = PWMx_CH0 level-detect brake event happened. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. + * |[9] |BRKLIF1 |Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect) + * | | |0 = PWMx_CH1 level-detect brake event do not happened. + * | | |1 = PWMx_CH1 level-detect brake event happened. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. + * |[16] |BRKESTS0 |Edge -detect Brake Status of PWMx_CH0 (Read Only) + * | | |0 = PWMx_CH0 edge-detect brake state is released. + * | | |1 = PWMx_CH0 at edge-detect brake state. + * | | |Note: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period. + * |[17] |BRKESTS1 |Edge-detect Brake Status of PWMx_CH1 (Read Only) + * | | |0 = PWMx_CH1 edge-detect brake state is released. + * | | |1 = PWMx_CH1 at edge-detect brake state. + * | | |Note: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period. + * |[24] |BRKLSTS0 |Level-detect Brake Status of PWMx_CH0 (Read Only) + * | | |0 = PWMx_CH0 level-detect brake state is released. + * | | |1 = PWMx_CH0 at level-detect brake state. + * | | |Note: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period. + * |[25] |BRKLSTS1 |Level-detect Brake Status of PWMx_CH1 (Read Only) + * | | |0 = PWMx_CH1 level-detect brake state is released. + * | | |1 = PWMx_CH1 at level-detect brake state. + * | | |Note: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period. + * @var TIMER_T::PWMEADCTS + * Offset: 0x90 Timer PWM ADC Trigger Source Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |TRGSEL |PWM Counter Event Source Select to Trigger EADC Conversion + * | | |000 = Trigger EADC conversion at zero point (ZIF). + * | | |001 = Trigger EADC conversion at period point (PIF). + * | | |010 = Trigger EADC conversion at zero or period point (ZIF or PIF). + * | | |011 = Trigger EADC conversion at compare up count point (CMPUIF). + * | | |100 = Trigger EADC conversion at compare down count point (CMPDIF). + * | | |Others = Reserved. + * |[7] |TRGEN |PWM Counter Event Trigger EADC Conversion Enable Bit + * | | |0 = PWM counter event trigger EADC conversion Disabled. + * | | |1 = PWM counter event trigger EADC conversion Enabled. + * @var TIMER_T::PWMSCTL + * Offset: 0x94 Timer PWM Synchronous Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |SYNCMODE |PWM Synchronous Mode Enable Select + * | | |00 = PWM synchronous function Disabled. + * | | |01 = PWM synchronous counter start function Enabled. + * | | |10 = Reserved. + * | | |11 = PWM synchronous counter clear function Enabled. + * |[8] |SYNCSRC |PWM Synchronous Counter Start/Clear Source Select + * | | |0 = Counter synchronous start/clear by trigger TIMER0_PWMSTRG STRGEN. + * | | |1 = Counter synchronous start/clear by trigger TIMER2_PWMSTRG STRGEN. + * | | |Note1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8], TIMER1_PWMSCTL[8], TIMER2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be 0. + * | | |Note2: If TIMER0/1/ PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8] and TIMER1_PWMSCTL[8] should be set 0, and TIMER2/3/ PWM counter synchronous source are from TIMER2, TIME2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be set 1. + * @var TIMER_T::PWMSTRG + * Offset: 0x98 Timer PWM Synchronous Trigger Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |STRGEN |PWM Counter Synchronous Trigger Enable Bit (Write Only) + * | | |PMW counter synchronous function is used to make selected PWM channels (include TIMER0/1/2/3 PWM, TIMER0/1 PWM and TIMER2/3 PWM) start counting or clear counter at the same time according to TIMERx_PWMSCTL setting. + * | | |Note: This bit is only available in TIMER0 and TIMER2. + * @var TIMER_T::PWMSTATUS + * Offset: 0x9C Timer PWM Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTMAXF |PWM Counter Equal to 0xFFFF Flag + * | | |0 = Indicates the PWM counter value never reached its maximum value 0xFFFF. + * | | |1 = Indicates the PWM counter value has reached its maximum value. + * | | |Note: This bit is cleared by writing 1 to it. + * |[16] |EADCTRGF |Trigger EADC Start Conversion Flag + * | | |0 = PWM counter event trigger EADC start conversion is not occurred. + * | | |1 = PWM counter event trigger EADC start conversion has occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * @var TIMER_T::PWMPBUF + * Offset: 0xA0 Timer PWM Period Buffer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PBUF |PWM Period Buffer Register (Read Only) + * | | |Used as PERIOD active register. + * @var TIMER_T::PWMCMPBUF + * Offset: 0xA4 Timer PWM Comparator Buffer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMPBUF |PWM Comparator Buffer Register (Read Only) + * | | |Used as CMP active register. + */ + __IO uint32_t CTL; /*!< [0x0000] Timer Control Register */ + __IO uint32_t CMP; /*!< [0x0004] Timer Comparator Register */ + __IO uint32_t INTSTS; /*!< [0x0008] Timer Interrupt Status Register */ + __IO uint32_t CNT; /*!< [0x000c] Timer Data Register */ + __I uint32_t CAP; /*!< [0x0010] Timer Capture Data Register */ + __IO uint32_t EXTCTL; /*!< [0x0014] Timer External Control Register */ + __IO uint32_t EINTSTS; /*!< [0x0018] Timer External Interrupt Status Register */ + __IO uint32_t TRGCTL; /*!< [0x001c] Timer Trigger Control Register */ + __IO uint32_t ALTCTL; /*!< [0x0020] Timer Alternative Control Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE0[7]; + /** @endcond */ + __IO uint32_t PWMCTL; /*!< [0x0040] Timer PWM Control Register */ + __IO uint32_t PWMCLKSRC; /*!< [0x0044] Timer PWM Counter Clock Source Register */ + __IO uint32_t PWMCLKPSC; /*!< [0x0048] Timer PWM Counter Clock Pre-scale Register */ + __IO uint32_t PWMCNTCLR; /*!< [0x004c] Timer PWM Clear Counter Register */ + __IO uint32_t PWMPERIOD; /*!< [0x0050] Timer PWM Period Register */ + __IO uint32_t PWMCMPDAT; /*!< [0x0054] Timer PWM Comparator Register */ + __IO uint32_t PWMDTCTL; /*!< [0x0058] Timer PWM Dead-Time Control Register */ + __I uint32_t PWMCNT; /*!< [0x005c] Timer PWM Counter Register */ + __IO uint32_t PWMMSKEN; /*!< [0x0060] Timer PWM Output Mask Enable Register */ + __IO uint32_t PWMMSK; /*!< [0x0064] Timer PWM Output Mask Data Control Register */ + __IO uint32_t PWMBNF; /*!< [0x0068] Timer PWM Brake Pin Noise Filter Register */ + __IO uint32_t PWMFAILBRK; /*!< [0x006c] Timer PWM System Fail Brake Control Register */ + __IO uint32_t PWMBRKCTL; /*!< [0x0070] Timer PWM Brake Control Register */ + __IO uint32_t PWMPOLCTL; /*!< [0x0074] Timer PWM Pin Output Polar Control Register */ + __IO uint32_t PWMPOEN; /*!< [0x0078] Timer PWM Pin Output Enable Register */ + __O uint32_t PWMSWBRK; /*!< [0x007c] Timer PWM Software Trigger Brake Control Register */ + __IO uint32_t PWMINTEN0; /*!< [0x0080] Timer PWM Interrupt Enable Register 0 */ + __IO uint32_t PWMINTEN1; /*!< [0x0084] Timer PWM Interrupt Enable Register 1 */ + __IO uint32_t PWMINTSTS0; /*!< [0x0088] Timer PWM Interrupt Status Register 0 */ + __IO uint32_t PWMINTSTS1; /*!< [0x008c] Timer PWM Interrupt Status Register 1 */ + __IO uint32_t PWMEADCTS; /*!< [0x0090] Timer PWM EADC Trigger Source Select Register */ + __IO uint32_t PWMSCTL; /*!< [0x0094] Timer PWM Synchronous Control Register */ + __O uint32_t PWMSTRG; /*!< [0x0098] Timer PWM Synchronous Trigger Register */ + __IO uint32_t PWMSTATUS; /*!< [0x009c] Timer PWM Status Register */ + __I uint32_t PWMPBUF; /*!< [0x00a0] Timer PWM Period Buffer Register */ + __I uint32_t PWMCMPBUF; /*!< [0x00a4] Timer PWM Comparator Buffer Register */ + +} TIMER_T; + +/** + @addtogroup TIMER_CONST TIMER Bit Field Definition + Constant Definitions for TIMER Controller +@{ */ + +#define TIMER_CTL_PSC_Pos (0) /*!< TIMER_T::CTL: PSC Position */ +#define TIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos) /*!< TIMER_T::CTL: PSC Mask */ + +#define TIMER_CTL_INTRGEN_Pos (19) /*!< TIMER_T::CTL: INTRGEN Position */ +#define TIMER_CTL_INTRGEN_Msk (0x1ul << TIMER_CTL_INTRGEN_Pos) /*!< TIMER_T::CTL: INTRGEN Mask */ + +#define TIMER_CTL_PERIOSEL_Pos (20) /*!< TIMER_T::CTL: PERIOSEL Position */ +#define TIMER_CTL_PERIOSEL_Msk (0x1ul << TIMER_CTL_PERIOSEL_Pos) /*!< TIMER_T::CTL: PERIOSEL Mask */ + +#define TIMER_CTL_TGLPINSEL_Pos (21) /*!< TIMER_T::CTL: TGLPINSEL Position */ +#define TIMER_CTL_TGLPINSEL_Msk (0x1ul << TIMER_CTL_TGLPINSEL_Pos) /*!< TIMER_T::CTL: TGLPINSEL Mask */ + +#define TIMER_CTL_CAPSRC_Pos (22) /*!< TIMER_T::CTL: CAPSRC Position */ +#define TIMER_CTL_CAPSRC_Msk (0x1ul << TIMER_CTL_CAPSRC_Pos) /*!< TIMER_T::CTL: CAPSRC Mask */ + +#define TIMER_CTL_WKEN_Pos (23) /*!< TIMER_T::CTL: WKEN Position */ +#define TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos) /*!< TIMER_T::CTL: WKEN Mask */ + +#define TIMER_CTL_EXTCNTEN_Pos (24) /*!< TIMER_T::CTL: EXTCNTEN Position */ +#define TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos) /*!< TIMER_T::CTL: EXTCNTEN Mask */ + +#define TIMER_CTL_ACTSTS_Pos (25) /*!< TIMER_T::CTL: ACTSTS Position */ +#define TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos) /*!< TIMER_T::CTL: ACTSTS Mask */ + +#define TIMER_CTL_OPMODE_Pos (27) /*!< TIMER_T::CTL: OPMODE Position */ +#define TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos) /*!< TIMER_T::CTL: OPMODE Mask */ + +#define TIMER_CTL_INTEN_Pos (29) /*!< TIMER_T::CTL: INTEN Position */ +#define TIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos) /*!< TIMER_T::CTL: INTEN Mask */ + +#define TIMER_CTL_CNTEN_Pos (30) /*!< TIMER_T::CTL: CNTEN Position */ +#define TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos) /*!< TIMER_T::CTL: CNTEN Mask */ + +#define TIMER_CTL_ICEDEBUG_Pos (31) /*!< TIMER_T::CTL: ICEDEBUG Position */ +#define TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos) /*!< TIMER_T::CTL: ICEDEBUG Mask */ + +#define TIMER_CMP_CMPDAT_Pos (0) /*!< TIMER_T::CMP: CMPDAT Position */ +#define TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_Pos) /*!< TIMER_T::CMP: CMPDAT Mask */ + +#define TIMER_INTSTS_TIF_Pos (0) /*!< TIMER_T::INTSTS: TIF Position */ +#define TIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos) /*!< TIMER_T::INTSTS: TIF Mask */ + +#define TIMER_INTSTS_TWKF_Pos (1) /*!< TIMER_T::INTSTS: TWKF Position */ +#define TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos) /*!< TIMER_T::INTSTS: TWKF Mask */ + +#define TIMER_CNT_CNT_Pos (0) /*!< TIMER_T::CNT: CNT Position */ +#define TIMER_CNT_CNT_Msk (0xfffffful << TIMER_CNT_CNT_Pos) /*!< TIMER_T::CNT: CNT Mask */ + +#define TIMER_CNT_RSTACT_Pos (31) /*!< TIMER_T::CNT: RSTACT Position */ +#define TIMER_CNT_RSTACT_Msk (0x1ul << TIMER_CNT_RSTACT_Pos) /*!< TIMER_T::CNT: RSTACT Mask */ + +#define TIMER_CAP_CAPDAT_Pos (0) /*!< TIMER_T::CAP: CAPDAT Position */ +#define TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos) /*!< TIMER_T::CAP: CAPDAT Mask */ + +#define TIMER_EXTCTL_CNTPHASE_Pos (0) /*!< TIMER_T::EXTCTL: CNTPHASE Position */ +#define TIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos) /*!< TIMER_T::EXTCTL: CNTPHASE Mask */ + +#define TIMER_EXTCTL_CAPEN_Pos (3) /*!< TIMER_T::EXTCTL: CAPEN Position */ +#define TIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos) /*!< TIMER_T::EXTCTL: CAPEN Mask */ + +#define TIMER_EXTCTL_CAPFUNCS_Pos (4) /*!< TIMER_T::EXTCTL: CAPFUNCS Position */ +#define TIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< TIMER_T::EXTCTL: CAPFUNCS Mask */ + +#define TIMER_EXTCTL_CAPIEN_Pos (5) /*!< TIMER_T::EXTCTL: CAPIEN Position */ +#define TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos) /*!< TIMER_T::EXTCTL: CAPIEN Mask */ + +#define TIMER_EXTCTL_CAPDBEN_Pos (6) /*!< TIMER_T::EXTCTL: CAPDBEN Position */ +#define TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos) /*!< TIMER_T::EXTCTL: CAPDBEN Mask */ + +#define TIMER_EXTCTL_CNTDBEN_Pos (7) /*!< TIMER_T::EXTCTL: CNTDBEN Position */ +#define TIMER_EXTCTL_CNTDBEN_Msk (0x1ul << TIMER_EXTCTL_CNTDBEN_Pos) /*!< TIMER_T::EXTCTL: CNTDBEN Mask */ + +#define TIMER_EXTCTL_ICAPSEL_Pos (8) /*!< TIMER_T::EXTCTL: ICAPSEL Position */ +#define TIMER_EXTCTL_ICAPSEL_Msk (0x7ul << TIMER_EXTCTL_ICAPSEL_Pos) /*!< TIMER_T::EXTCTL: ICAPSEL Mask */ + +#define TIMER_EXTCTL_CAPEDGE_Pos (12) /*!< TIMER_T::EXTCTL: CAPEDGE Position */ +#define TIMER_EXTCTL_CAPEDGE_Msk (0x7ul << TIMER_EXTCTL_CAPEDGE_Pos) /*!< TIMER_T::EXTCTL: CAPEDGE Mask */ + +#define TIMER_EXTCTL_ECNTSSEL_Pos (16) /*!< TIMER_T::EXTCTL: ECNTSSEL Position */ +#define TIMER_EXTCTL_ECNTSSEL_Msk (0x1ul << TIMER_EXTCTL_ECNTSSEL_Pos) /*!< TIMER_T::EXTCTL: ECNTSSEL Mask */ + +#define TIMER_EXTCTL_CAPDIVSCL_Pos (28) /*!< TIMER_T::EXTCTL: CAPDIVSCL Position */ +#define TIMER_EXTCTL_CAPDIVSCL_Msk (0xful << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< TIMER_T::EXTCTL: CAPDIVSCL Mask */ + +#define TIMER_EINTSTS_CAPIF_Pos (0) /*!< TIMER_T::EINTSTS: CAPIF Position */ +#define TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos) /*!< TIMER_T::EINTSTS: CAPIF Mask */ + +#define TIMER_TRGCTL_TRGSSEL_Pos (0) /*!< TIMER_T::TRGCTL: TRGSSEL Position */ +#define TIMER_TRGCTL_TRGSSEL_Msk (0x1ul << TIMER_TRGCTL_TRGSSEL_Pos) /*!< TIMER_T::TRGCTL: TRGSSEL Mask */ + +#define TIMER_TRGCTL_TRGEPWM_Pos (1) /*!< TIMER_T::TRGCTL: TRGEPWM Position */ +#define TIMER_TRGCTL_TRGEPWM_Msk (0x1ul << TIMER_TRGCTL_TRGEPWM_Pos) /*!< TIMER_T::TRGCTL: TRGEPWM Mask */ + +#define TIMER_TRGCTL_TRGEADC_Pos (2) /*!< TIMER_T::TRGCTL: TRGEADC Position */ +#define TIMER_TRGCTL_TRGEADC_Msk (0x1ul << TIMER_TRGCTL_TRGEADC_Pos) /*!< TIMER_T::TRGCTL: TRGEADC Mask */ + +#define TIMER_TRGCTL_TRGDAC_Pos (3) /*!< TIMER_T::TRGCTL: TRGDAC Position */ +#define TIMER_TRGCTL_TRGDAC_Msk (0x1ul << TIMER_TRGCTL_TRGDAC_Pos) /*!< TIMER_T::TRGCTL: TRGDAC Mask */ + +#define TIMER_TRGCTL_TRGPDMA_Pos (4) /*!< TIMER_T::TRGCTL: TRGPDMA Position */ +#define TIMER_TRGCTL_TRGPDMA_Msk (0x1ul << TIMER_TRGCTL_TRGPDMA_Pos) /*!< TIMER_T::TRGCTL: TRGPDMA Mask */ + +#define TIMER_ALTCTL_FUNCSEL_Pos (0) /*!< TIMER_T::ALTCTL: FUNCSEL Position */ +#define TIMER_ALTCTL_FUNCSEL_Msk (0x1ul << TIMER_ALTCTL_FUNCSEL_Pos) /*!< TIMER_T::ALTCTL: FUNCSEL Mask */ + +#define TIMER_PWMCTL_CNTEN_Pos (0) /*!< TIMER_T::PWMCTL: CNTEN Position */ +#define TIMER_PWMCTL_CNTEN_Msk (0x1ul << TIMER_PWMCTL_CNTEN_Pos) /*!< TIMER_T::PWMCTL: CNTEN Mask */ + +#define TIMER_PWMCTL_CNTTYPE_Pos (1) /*!< TIMER_T::PWMCTL: CNTTYPE Position */ +#define TIMER_PWMCTL_CNTTYPE_Msk (0x3ul << TIMER_PWMCTL_CNTTYPE_Pos) /*!< TIMER_T::PWMCTL: CNTTYPE Mask */ + +#define TIMER_PWMCTL_CNTMODE_Pos (3) /*!< TIMER_T::PWMCTL: CNTMODE Position */ +#define TIMER_PWMCTL_CNTMODE_Msk (0x1ul << TIMER_PWMCTL_CNTMODE_Pos) /*!< TIMER_T::PWMCTL: CNTMODE Mask */ + +#define TIMER_PWMCTL_CTRLD_Pos (8) /*!< TIMER_T::PWMCTL: CTRLD Position */ +#define TIMER_PWMCTL_CTRLD_Msk (0x1ul << TIMER_PWMCTL_CTRLD_Pos) /*!< TIMER_T::PWMCTL: CTRLD Mask */ + +#define TIMER_PWMCTL_IMMLDEN_Pos (9) /*!< TIMER_T::PWMCTL: IMMLDEN Position */ +#define TIMER_PWMCTL_IMMLDEN_Msk (0x1ul << TIMER_PWMCTL_IMMLDEN_Pos) /*!< TIMER_T::PWMCTL: IMMLDEN Mask */ + +#define TIMER_PWMCTL_OUTMODE_Pos (16) /*!< TIMER_T::PWMCTL: OUTMODE Position */ +#define TIMER_PWMCTL_OUTMODE_Msk (0x1ul << TIMER_PWMCTL_OUTMODE_Pos) /*!< TIMER_T::PWMCTL: OUTMODE Mask */ + +#define TIMER_PWMCTL_DBGHALT_Pos (30) /*!< TIMER_T::PWMCTL: DBGHALT Position */ +#define TIMER_PWMCTL_DBGHALT_Msk (0x1ul << TIMER_PWMCTL_DBGHALT_Pos) /*!< TIMER_T::PWMCTL: DBGHALT Mask */ + +#define TIMER_PWMCTL_DBGTRIOFF_Pos (31) /*!< TIMER_T::PWMCTL: DBGTRIOFF Position */ +#define TIMER_PWMCTL_DBGTRIOFF_Msk (0x1ul << TIMER_PWMCTL_DBGTRIOFF_Pos) /*!< TIMER_T::PWMCTL: DBGTRIOFF Mask */ + +#define TIMER_PWMCLKSRC_CLKSRC_Pos (0) /*!< TIMER_T::PWMCLKSRC: CLKSRC Position */ +#define TIMER_PWMCLKSRC_CLKSRC_Msk (0x7ul << TIMER_PWMCLKSRC_CLKSRC_Pos) /*!< TIMER_T::PWMCLKSRC: CLKSRC Mask */ + +#define TIMER_PWMCLKPSC_CLKPSC_Pos (0) /*!< TIMER_T::PWMCLKPSC: CLKPSC Position */ +#define TIMER_PWMCLKPSC_CLKPSC_Msk (0xffful << TIMER_PWMCLKPSC_CLKPSC_Pos) /*!< TIMER_T::PWMCLKPSC: CLKPSC Mask */ + +#define TIMER_PWMCNTCLR_CNTCLR_Pos (0) /*!< TIMER_T::PWMCNTCLR: CNTCLR Position */ +#define TIMER_PWMCNTCLR_CNTCLR_Msk (0x1ul << TIMER_PWMCNTCLR_CNTCLR_Pos) /*!< TIMER_T::PWMCNTCLR: CNTCLR Mask */ + +#define TIMER_PWMPERIOD_PERIOD_Pos (0) /*!< TIMER_T::PWMPERIOD: PERIOD Position */ +#define TIMER_PWMPERIOD_PERIOD_Msk (0xfffful << TIMER_PWMPERIOD_PERIOD_Pos) /*!< TIMER_T::PWMPERIOD: PERIOD Mask */ + +#define TIMER_PWMCMPDAT_CMP_Pos (0) /*!< TIMER_T::PWMCMPDAT: CMP Position */ +#define TIMER_PWMCMPDAT_CMP_Msk (0xfffful << TIMER_PWMCMPDAT_CMP_Pos) /*!< TIMER_T::PWMCMPDAT: CMP Mask */ + +#define TIMER_PWMDTCTL_DTCNT_Pos (0) /*!< TIMER_T::PWMDTCTL: DTCNT Position */ +#define TIMER_PWMDTCTL_DTCNT_Msk (0xffful << TIMER_PWMDTCTL_DTCNT_Pos) /*!< TIMER_T::PWMDTCTL: DTCNT Mask */ + +#define TIMER_PWMDTCTL_DTEN_Pos (16) /*!< TIMER_T::PWMDTCTL: DTEN Position */ +#define TIMER_PWMDTCTL_DTEN_Msk (0x1ul << TIMER_PWMDTCTL_DTEN_Pos) /*!< TIMER_T::PWMDTCTL: DTEN Mask */ + +#define TIMER_PWMDTCTL_DTCKSEL_Pos (24) /*!< TIMER_T::PWMDTCTL: DTCKSEL Position */ +#define TIMER_PWMDTCTL_DTCKSEL_Msk (0x1ul << TIMER_PWMDTCTL_DTCKSEL_Pos) /*!< TIMER_T::PWMDTCTL: DTCKSEL Mask */ + +#define TIMER_PWMCNT_CNT_Pos (0) /*!< TIMER_T::PWMCNT: CNT Position */ +#define TIMER_PWMCNT_CNT_Msk (0xfffful << TIMER_PWMCNT_CNT_Pos) /*!< TIMER_T::PWMCNT: CNT Mask */ + +#define TIMER_PWMCNT_DIRF_Pos (16) /*!< TIMER_T::PWMCNT: DIRF Position */ +#define TIMER_PWMCNT_DIRF_Msk (0x1ul << TIMER_PWMCNT_DIRF_Pos) /*!< TIMER_T::PWMCNT: DIRF Mask */ + +#define TIMER_PWMMSKEN_MSKEN0_Pos (0) /*!< TIMER_T::PWMMSKEN: MSKEN0 Position */ +#define TIMER_PWMMSKEN_MSKEN0_Msk (0x1ul << TIMER_PWMMSKEN_MSKEN0_Pos) /*!< TIMER_T::PWMMSKEN: MSKEN0 Mask */ + +#define TIMER_PWMMSKEN_MSKEN1_Pos (1) /*!< TIMER_T::PWMMSKEN: MSKEN1 Position */ +#define TIMER_PWMMSKEN_MSKEN1_Msk (0x1ul << TIMER_PWMMSKEN_MSKEN1_Pos) /*!< TIMER_T::PWMMSKEN: MSKEN1 Mask */ + +#define TIMER_PWMMSK_MSKDAT0_Pos (0) /*!< TIMER_T::PWMMSK: MSKDAT0 Position */ +#define TIMER_PWMMSK_MSKDAT0_Msk (0x1ul << TIMER_PWMMSK_MSKDAT0_Pos) /*!< TIMER_T::PWMMSK: MSKDAT0 Mask */ + +#define TIMER_PWMMSK_MSKDAT1_Pos (1) /*!< TIMER_T::PWMMSK: MSKDAT1 Position */ +#define TIMER_PWMMSK_MSKDAT1_Msk (0x1ul << TIMER_PWMMSK_MSKDAT1_Pos) /*!< TIMER_T::PWMMSK: MSKDAT1 Mask */ + +#define TIMER_PWMBNF_BRKNFEN_Pos (0) /*!< TIMER_T::PWMBNF: BRKNFEN Position */ +#define TIMER_PWMBNF_BRKNFEN_Msk (0x1ul << TIMER_PWMBNF_BRKNFEN_Pos) /*!< TIMER_T::PWMBNF: BRKNFEN Mask */ + +#define TIMER_PWMBNF_BRKNFSEL_Pos (1) /*!< TIMER_T::PWMBNF: BRKNFSEL Position */ +#define TIMER_PWMBNF_BRKNFSEL_Msk (0x7ul << TIMER_PWMBNF_BRKNFSEL_Pos) /*!< TIMER_T::PWMBNF: BRKNFSEL Mask */ + +#define TIMER_PWMBNF_BRKFCNT_Pos (4) /*!< TIMER_T::PWMBNF: BRKFCNT Position */ +#define TIMER_PWMBNF_BRKFCNT_Msk (0x7ul << TIMER_PWMBNF_BRKFCNT_Pos) /*!< TIMER_T::PWMBNF: BRKFCNT Mask */ + +#define TIMER_PWMBNF_BRKPINV_Pos (7) /*!< TIMER_T::PWMBNF: BRKPINV Position */ +#define TIMER_PWMBNF_BRKPINV_Msk (0x1ul << TIMER_PWMBNF_BRKPINV_Pos) /*!< TIMER_T::PWMBNF: BRKPINV Mask */ + +#define TIMER_PWMBNF_BKPINSRC_Pos (16) /*!< TIMER_T::PWMBNF: BKPINSRC Position */ +#define TIMER_PWMBNF_BKPINSRC_Msk (0x3ul << TIMER_PWMBNF_BKPINSRC_Pos) /*!< TIMER_T::PWMBNF: BKPINSRC Mask */ + +#define TIMER_PWMFAILBRK_CSSBRKEN_Pos (0) /*!< TIMER_T::PWMFAILBRK: CSSBRKEN Position */ +#define TIMER_PWMFAILBRK_CSSBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_CSSBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: CSSBRKEN Mask */ + +#define TIMER_PWMFAILBRK_BODBRKEN_Pos (1) /*!< TIMER_T::PWMFAILBRK: BODBRKEN Position */ +#define TIMER_PWMFAILBRK_BODBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_BODBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: BODBRKEN Mask */ + +#define TIMER_PWMFAILBRK_RAMBRKEN_Pos (2) /*!< TIMER_T::PWMFAILBRK: RAMBRKEN Position */ +#define TIMER_PWMFAILBRK_RAMBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_RAMBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: RAMBRKEN Mask */ + +#define TIMER_PWMFAILBRK_CORBRKEN_Pos (3) /*!< TIMER_T::PWMFAILBRK: CORBRKEN Position */ +#define TIMER_PWMFAILBRK_CORBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_CORBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: CORBRKEN Mask */ + +#define TIMER_PWMBRKCTL_CPO0EBEN_Pos (0) /*!< TIMER_T::PWMBRKCTL: CPO0EBEN Position */ +#define TIMER_PWMBRKCTL_CPO0EBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO0EBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO0EBEN Mask */ + +#define TIMER_PWMBRKCTL_CPO1EBEN_Pos (1) /*!< TIMER_T::PWMBRKCTL: CPO1EBEN Position */ +#define TIMER_PWMBRKCTL_CPO1EBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO1EBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO1EBEN Mask */ + +#define TIMER_PWMBRKCTL_BRKPEEN_Pos (4) /*!< TIMER_T::PWMBRKCTL: BRKPEEN Position */ +#define TIMER_PWMBRKCTL_BRKPEEN_Msk (0x1ul << TIMER_PWMBRKCTL_BRKPEEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKPEEN Mask */ + +#define TIMER_PWMBRKCTL_SYSEBEN_Pos (7) /*!< TIMER_T::PWMBRKCTL: SYSEBEN Position */ +#define TIMER_PWMBRKCTL_SYSEBEN_Msk (0x1ul << TIMER_PWMBRKCTL_SYSEBEN_Pos) /*!< TIMER_T::PWMBRKCTL: SYSEBEN Mask */ + +#define TIMER_PWMBRKCTL_CPO0LBEN_Pos (8) /*!< TIMER_T::PWMBRKCTL: CPO0LBEN Position */ +#define TIMER_PWMBRKCTL_CPO0LBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO0LBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO0LBEN Mask */ + +#define TIMER_PWMBRKCTL_CPO1LBEN_Pos (9) /*!< TIMER_T::PWMBRKCTL: CPO1LBEN Position */ +#define TIMER_PWMBRKCTL_CPO1LBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO1LBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO1LBEN Mask */ + +#define TIMER_PWMBRKCTL_BRKPLEN_Pos (12) /*!< TIMER_T::PWMBRKCTL: BRKPLEN Position */ +#define TIMER_PWMBRKCTL_BRKPLEN_Msk (0x1ul << TIMER_PWMBRKCTL_BRKPLEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKPLEN Mask */ + +#define TIMER_PWMBRKCTL_SYSLBEN_Pos (15) /*!< TIMER_T::PWMBRKCTL: SYSLBEN Position */ +#define TIMER_PWMBRKCTL_SYSLBEN_Msk (0x1ul << TIMER_PWMBRKCTL_SYSLBEN_Pos) /*!< TIMER_T::PWMBRKCTL: SYSLBEN Mask */ + +#define TIMER_PWMBRKCTL_BRKAEVEN_Pos (16) /*!< TIMER_T::PWMBRKCTL: BRKAEVEN Position */ +#define TIMER_PWMBRKCTL_BRKAEVEN_Msk (0x3ul << TIMER_PWMBRKCTL_BRKAEVEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKAEVEN Mask */ + +#define TIMER_PWMBRKCTL_BRKAODD_Pos (18) /*!< TIMER_T::PWMBRKCTL: BRKAODD Position */ +#define TIMER_PWMBRKCTL_BRKAODD_Msk (0x3ul << TIMER_PWMBRKCTL_BRKAODD_Pos) /*!< TIMER_T::PWMBRKCTL: BRKAODD Mask */ + +#define TIMER_PWMPOLCTL_PINV0_Pos (0) /*!< TIMER_T::PWMPOLCTL: PINV0 Position */ +#define TIMER_PWMPOLCTL_PINV0_Msk (0x1ul << TIMER_PWMPOLCTL_PINV0_Pos) /*!< TIMER_T::PWMPOLCTL: PINV0 Mask */ + +#define TIMER_PWMPOLCTL_PINV1_Pos (1) /*!< TIMER_T::PWMPOLCTL: PINV1 Position */ +#define TIMER_PWMPOLCTL_PINV1_Msk (0x1ul << TIMER_PWMPOLCTL_PINV1_Pos) /*!< TIMER_T::PWMPOLCTL: PINV1 Mask */ + +#define TIMER_PWMPOEN_POEN0_Pos (0) /*!< TIMER_T::PWMPOEN: POEN0 Position */ +#define TIMER_PWMPOEN_POEN0_Msk (0x1ul << TIMER_PWMPOEN_POEN0_Pos) /*!< TIMER_T::PWMPOEN: POEN0 Mask */ + +#define TIMER_PWMPOEN_POEN1_Pos (1) /*!< TIMER_T::PWMPOEN: POEN1 Position */ +#define TIMER_PWMPOEN_POEN1_Msk (0x1ul << TIMER_PWMPOEN_POEN1_Pos) /*!< TIMER_T::PWMPOEN: POEN1 Mask */ + +#define TIMER_PWMSWBRK_BRKETRG_Pos (0) /*!< TIMER_T::PWMSWBRK: BRKETRG Position */ +#define TIMER_PWMSWBRK_BRKETRG_Msk (0x1ul << TIMER_PWMSWBRK_BRKETRG_Pos) /*!< TIMER_T::PWMSWBRK: BRKETRG Mask */ + +#define TIMER_PWMSWBRK_BRKLTRG_Pos (8) /*!< TIMER_T::PWMSWBRK: BRKLTRG Position */ +#define TIMER_PWMSWBRK_BRKLTRG_Msk (0x1ul << TIMER_PWMSWBRK_BRKLTRG_Pos) /*!< TIMER_T::PWMSWBRK: BRKLTRG Mask */ + +#define TIMER_PWMINTEN0_ZIEN_Pos (0) /*!< TIMER_T::PWMINTEN0: ZIEN Position */ +#define TIMER_PWMINTEN0_ZIEN_Msk (0x1ul << TIMER_PWMINTEN0_ZIEN_Pos) /*!< TIMER_T::PWMINTEN0: ZIEN Mask */ + +#define TIMER_PWMINTEN0_PIEN_Pos (1) /*!< TIMER_T::PWMINTEN0: PIEN Position */ +#define TIMER_PWMINTEN0_PIEN_Msk (0x1ul << TIMER_PWMINTEN0_PIEN_Pos) /*!< TIMER_T::PWMINTEN0: PIEN Mask */ + +#define TIMER_PWMINTEN0_CMPUIEN_Pos (2) /*!< TIMER_T::PWMINTEN0: CMPUIEN Position */ +#define TIMER_PWMINTEN0_CMPUIEN_Msk (0x1ul << TIMER_PWMINTEN0_CMPUIEN_Pos) /*!< TIMER_T::PWMINTEN0: CMPUIEN Mask */ + +#define TIMER_PWMINTEN0_CMPDIEN_Pos (3) /*!< TIMER_T::PWMINTEN0: CMPDIEN Position */ +#define TIMER_PWMINTEN0_CMPDIEN_Msk (0x1ul << TIMER_PWMINTEN0_CMPDIEN_Pos) /*!< TIMER_T::PWMINTEN0: CMPDIEN Mask */ + +#define TIMER_PWMINTEN1_BRKEIEN_Pos (0) /*!< TIMER_T::PWMINTEN1: BRKEIEN Position */ +#define TIMER_PWMINTEN1_BRKEIEN_Msk (0x1ul << TIMER_PWMINTEN1_BRKEIEN_Pos) /*!< TIMER_T::PWMINTEN1: BRKEIEN Mask */ + +#define TIMER_PWMINTEN1_BRKLIEN_Pos (8) /*!< TIMER_T::PWMINTEN1: BRKLIEN Position */ +#define TIMER_PWMINTEN1_BRKLIEN_Msk (0x1ul << TIMER_PWMINTEN1_BRKLIEN_Pos) /*!< TIMER_T::PWMINTEN1: BRKLIEN Mask */ + +#define TIMER_PWMINTSTS0_ZIF_Pos (0) /*!< TIMER_T::PWMINTSTS0: ZIF Position */ +#define TIMER_PWMINTSTS0_ZIF_Msk (0x1ul << TIMER_PWMINTSTS0_ZIF_Pos) /*!< TIMER_T::PWMINTSTS0: ZIF Mask */ + +#define TIMER_PWMINTSTS0_PIF_Pos (1) /*!< TIMER_T::PWMINTSTS0: PIF Position */ +#define TIMER_PWMINTSTS0_PIF_Msk (0x1ul << TIMER_PWMINTSTS0_PIF_Pos) /*!< TIMER_T::PWMINTSTS0: PIF Mask */ + +#define TIMER_PWMINTSTS0_CMPUIF_Pos (2) /*!< TIMER_T::PWMINTSTS0: CMPUIF Position */ +#define TIMER_PWMINTSTS0_CMPUIF_Msk (0x1ul << TIMER_PWMINTSTS0_CMPUIF_Pos) /*!< TIMER_T::PWMINTSTS0: CMPUIF Mask */ + +#define TIMER_PWMINTSTS0_CMPDIF_Pos (3) /*!< TIMER_T::PWMINTSTS0: CMPDIF Position */ +#define TIMER_PWMINTSTS0_CMPDIF_Msk (0x1ul << TIMER_PWMINTSTS0_CMPDIF_Pos) /*!< TIMER_T::PWMINTSTS0: CMPDIF Mask */ + +#define TIMER_PWMINTSTS1_BRKEIF0_Pos (0) /*!< TIMER_T::PWMINTSTS1: BRKEIF0 Position */ +#define TIMER_PWMINTSTS1_BRKEIF0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKEIF0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKEIF0 Mask */ + +#define TIMER_PWMINTSTS1_BRKEIF1_Pos (1) /*!< TIMER_T::PWMINTSTS1: BRKEIF1 Position */ +#define TIMER_PWMINTSTS1_BRKEIF1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKEIF1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKEIF1 Mask */ + +#define TIMER_PWMINTSTS1_BRKLIF0_Pos (8) /*!< TIMER_T::PWMINTSTS1: BRKLIF0 Position */ +#define TIMER_PWMINTSTS1_BRKLIF0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLIF0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLIF0 Mask */ + +#define TIMER_PWMINTSTS1_BRKLIF1_Pos (9) /*!< TIMER_T::PWMINTSTS1: BRKLIF1 Position */ +#define TIMER_PWMINTSTS1_BRKLIF1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLIF1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLIF1 Mask */ + +#define TIMER_PWMINTSTS1_BRKESTS0_Pos (16) /*!< TIMER_T::PWMINTSTS1: BRKESTS0 Position */ +#define TIMER_PWMINTSTS1_BRKESTS0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKESTS0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKESTS0 Mask */ + +#define TIMER_PWMINTSTS1_BRKESTS1_Pos (17) /*!< TIMER_T::PWMINTSTS1: BRKESTS1 Position */ +#define TIMER_PWMINTSTS1_BRKESTS1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKESTS1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKESTS1 Mask */ + +#define TIMER_PWMINTSTS1_BRKLSTS0_Pos (24) /*!< TIMER_T::PWMINTSTS1: BRKLSTS0 Position */ +#define TIMER_PWMINTSTS1_BRKLSTS0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLSTS0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLSTS0 Mask */ + +#define TIMER_PWMINTSTS1_BRKLSTS1_Pos (25) /*!< TIMER_T::PWMINTSTS1: BRKLSTS1 Position */ +#define TIMER_PWMINTSTS1_BRKLSTS1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLSTS1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLSTS1 Mask */ + +#define TIMER_PWMEADCTS_TRGSEL_Pos (0) /*!< TIMER_T::PWMEADCTS: TRGSEL Position */ +#define TIMER_PWMEADCTS_TRGSEL_Msk (0x7ul << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< TIMER_T::PWMEADCTS: TRGSEL Mask */ + +#define TIMER_PWMEADCTS_TRGEN_Pos (7) /*!< TIMER_T::PWMEADCTS: TRGEN Position */ +#define TIMER_PWMEADCTS_TRGEN_Msk (0x1ul << TIMER_PWMEADCTS_TRGEN_Pos) /*!< TIMER_T::PWMEADCTS: TRGEN Mask */ + +#define TIMER_PWMSCTL_SYNCMODE_Pos (0) /*!< TIMER_T::PWMSCTL: SYNCMODE Position */ +#define TIMER_PWMSCTL_SYNCMODE_Msk (0x3ul << TIMER_PWMSCTL_SYNCMODE_Pos) /*!< TIMER_T::PWMSCTL: SYNCMODE Mask */ + +#define TIMER_PWMSCTL_SYNCSRC_Pos (8) /*!< TIMER_T::PWMSCTL: SYNCSRC Position */ +#define TIMER_PWMSCTL_SYNCSRC_Msk (0x1ul << TIMER_PWMSCTL_SYNCSRC_Pos) /*!< TIMER_T::PWMSCTL: SYNCSRC Mask */ + +#define TIMER_PWMSTRG_STRGEN_Pos (0) /*!< TIMER_T::PWMSTRG: STRGEN Position */ +#define TIMER_PWMSTRG_STRGEN_Msk (0x1ul << TIMER_PWMSTRG_STRGEN_Pos) /*!< TIMER_T::PWMSTRG: STRGEN Mask */ + +#define TIMER_PWMSTATUS_CNTMAXF_Pos (0) /*!< TIMER_T::PWMSTATUS: CNTMAXF Position */ +#define TIMER_PWMSTATUS_CNTMAXF_Msk (0x1ul << TIMER_PWMSTATUS_CNTMAXF_Pos) /*!< TIMER_T::PWMSTATUS: CNTMAXF Mask */ + +#define TIMER_PWMSTATUS_EADCTRGF_Pos (16) /*!< TIMER_T::PWMSTATUS: EADCTRGF Position */ +#define TIMER_PWMSTATUS_EADCTRGF_Msk (0x1ul << TIMER_PWMSTATUS_EADCTRGF_Pos) /*!< TIMER_T::PWMSTATUS: EADCTRGF Mask */ + +#define TIMER_PWMPBUF_PBUF_Pos (0) /*!< TIMER_T::PWMPBUF: PBUF Position */ +#define TIMER_PWMPBUF_PBUF_Msk (0xfffful << TIMER_PWMPBUF_PBUF_Pos) /*!< TIMER_T::PWMPBUF: PBUF Mask */ + +#define TIMER_PWMCMPBUF_CMPBUF_Pos (0) /*!< TIMER_T::PWMCMPBUF: CMPBUF Position */ +#define TIMER_PWMCMPBUF_CMPBUF_Msk (0xfffful << TIMER_PWMCMPBUF_CMPBUF_Pos) /*!< TIMER_T::PWMCMPBUF: CMPBUF Mask */ + +/**@}*/ /* TIMER_CONST */ +/**@}*/ /* end of TIMER register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __TIMER_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/trng_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/trng_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..ede3dfa65ba7a0c69ee3ec96759c16bede68503b --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/trng_reg.h @@ -0,0 +1,138 @@ +/**************************************************************************//** + * @file trng_reg.h + * @version V1.00 + * @brief TRNG register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __TRNG_REG_H__ +#define __TRNG_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- True Random Number Generator -------------------------*/ +/** + @addtogroup TRNG True Random Number Generator(TRNG) + Memory Mapped Structure for TRNG Controller +@{ */ + +typedef struct +{ + + + /** + * @var TRNG_T::CTL + * Offset: 0x00 TRNG Control Register and Status + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TRNGEN |Random Number Generator Enable Bit + * | | |This bit can be set to 1 only after ACT (TRNG_ACT[7]) bit was set to 1 and READY (TRNG_CTL[7]) bit became 1. + * | | |0 = TRNG disabled. + * | | |1 = TRNG enabled. + * | | |Note: TRNGEN is an enable bit of digital part + * | | |When TRNG is not required to generate random number, TRNGEN bit and ACT (TRNG_ACT[7]) bit should be set to 0 to reduce power consumption. + * |[1] |DVIF |Data Valid (Read Only) + * | | |0 = Data is not valid. Reading from RNGD returns 0x00000000. + * | | |1 = Data is valid. A valid random number can be read form RNGD. + * | | |This bit is cleared to u20180u2019 by read TRNG_DATA. + * |[5:2] |CLKP |Clock Prescaler + * | | |The CLKP is the peripheral clock frequency range for the selected value , the CLKP must higher than or equal to the actual peripheral clock frequency (for correct random bit generation) + * | | |To change the CLKP contents, first set TRNGEN bit to 0 and then change CLKP; finally, set TRNGEN bit to 1 to re-enable the TRNG module. + * | | |0000 = 80 ~ 100 MHz. + * | | |0001 = 60 ~ 80 MHz. + * | | |0010 = 50 ~60 MHz. + * | | |0011 = 40 ~50 MHz. + * | | |0100 = 30 ~40 MHz. + * | | |0101 = 25 ~30 MHz. + * | | |0110 = 20 ~25 MHz. + * | | |0111 = 15 ~20 MHz. + * | | |1000 = 12 ~15 MHz. + * | | |1001 = 9 ~12 MHz. + * | | |1010 = 7 ~9 MHz. + * | | |1011 = 6 ~7 MHz. + * | | |1100 = 5 ~6 MHz. + * | | |1101 = 4 ~5 MHz. + * | | |1111 = Reserved. + * |[6] |DVIEN |Data Valid Interrupt Enable Bit + * | | |0 = Interrupt disabled.. + * | | |1 = Interrupt enabled. + * |[7] |READY |Random Number Generator Ready (Read Only) + * | | |After ACT (TRNG_ACT[7]) bit is set, the READY bit become to 1 after a delay of 90us~120us. + * | | |0 = RNG is not ready or was not activated. + * | | |1 = RNG is ready to be enabled.. + * |[31:8] |Reversed |Reversed + * @var TRNG_T::DATA + * Offset: 0x04 TRNG Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DATA |Random Number Generator Data (Read Only) + * | | |The DATA store the random number generated by TRNG and can be read only once. + * @var TRNG_T::ACT + * Offset: 0x0C TRNG Activation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |VER |TRNG Version + * | | |TRNG version number is dependent on TRNG module. + * | | |0x02:(Current Version Number) + * |[7] |ACT |Random Number Generator Activation + * | | |After enable the ACT bit, it will active the TRNG module and wait the READY (TRNG_CTL[7]) bit to become 1. + * | | |0 = TRNG inactive. + * | | |1 = TRNG active. + * | | |Note: ACT is an enable bit of analog part + * | | |When TRNG is not required to generate random number, TRNGEN (TRNG_CTL[0]) bit and ACT bit should be set to 0 to reduce power consumption. + */ + __IO uint32_t CTL; /*!< [0x0000] TRNG Control Register and Status */ + __I uint32_t DATA; /*!< [0x0004] TRNG Data Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t ACT; /*!< [0x000c] TRNG Activation Register */ + +} TRNG_T; + +/** + @addtogroup TRNG_CONST TRNG Bit Field Definition + Constant Definitions for TRNG Controller +@{ */ + +#define TRNG_CTL_TRNGEN_Pos (0) /*!< TRNG_T::CTL: TRNGEN Position */ +#define TRNG_CTL_TRNGEN_Msk (0x1ul << TRNG_CTL_TRNGEN_Pos) /*!< TRNG_T::CTL: TRNGEN Mask */ + +#define TRNG_CTL_DVIF_Pos (1) /*!< TRNG_T::CTL: DVIF Position */ +#define TRNG_CTL_DVIF_Msk (0x1ul << TRNG_CTL_DVIF_Pos) /*!< TRNG_T::CTL: DVIF Mask */ + +#define TRNG_CTL_CLKP_Pos (2) /*!< TRNG_T::CTL: CLKP Position */ +#define TRNG_CTL_CLKP_Msk (0xful << TRNG_CTL_CLKP_Pos) /*!< TRNG_T::CTL: CLKP Mask */ + +#define TRNG_CTL_DVIEN_Pos (6) /*!< TRNG_T::CTL: DVIEN Position */ +#define TRNG_CTL_DVIEN_Msk (0x1ul << TRNG_CTL_DVIEN_Pos) /*!< TRNG_T::CTL: DVIEN Mask */ + +#define TRNG_CTL_READY_Pos (7) /*!< TRNG_T::CTL: READY Position */ +#define TRNG_CTL_READY_Msk (0x1ul << TRNG_CTL_READY_Pos) /*!< TRNG_T::CTL: READY Mask */ + +#define TRNG_CTL_Reversed_Pos (8) /*!< TRNG_T::CTL: Reversed Position */ +#define TRNG_CTL_Reversed_Msk (0xfffffful << TRNG_CTL_Reversed_Pos) /*!< TRNG_T::CTL: Reversed Mask */ + +#define TRNG_DATA_DATA_Pos (0) /*!< TRNG_T::DATA: DATA Position */ +#define TRNG_DATA_DATA_Msk (0xfful << TRNG_DATA_DATA_Pos) /*!< TRNG_T::DATA: DATA Mask */ + +#define TRNG_ACT_VER_Pos (0) /*!< TRNG_T::ACT: VER Position */ +#define TRNG_ACT_VER_Msk (0x7ful << TRNG_ACT_VER_Pos) /*!< TRNG_T::ACT: VER Mask */ + +#define TRNG_ACT_ACT_Pos (7) /*!< TRNG_T::ACT: ACT Position */ +#define TRNG_ACT_ACT_Msk (0x1ul << TRNG_ACT_ACT_Pos) /*!< TRNG_T::ACT: ACT Mask */ + +/**@}*/ /* TRNG_CONST */ +/**@}*/ /* end of TRNG register group */ +/**@}*/ /* end of REGISTER group */ + + +#endif /* __TRNG_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/uart_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/uart_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..3524551a7a147884025f76e52fdef3cce39fe34a --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/uart_reg.h @@ -0,0 +1,1273 @@ +/**************************************************************************//** + * @file uart_reg.h + * @version V1.00 + * @brief UART register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __UART_REG_H__ +#define __UART_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup UART Universal Asynchronous Receiver/Transmitter Controller(UART) + Memory Mapped Structure for UART Controller +@{ */ + +typedef struct +{ + + + /** + * @var UART_T::DAT + * Offset: 0x00 UART Receive/Transmit Buffer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DAT |Data Receive/Transmit Buffer + * | | |Write Operation: + * | | |By writing one byte to this register, the data byte will be stored in transmitter FIFO + * | | |The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD. + * | | |Read Operation: + * | | |By reading this register, the UART controller will return an 8-bit data received from receiver FIFO. + * |[8] |PARITY |Parity Bit Receive/Transmit Buffer + * | | |Write Operation: + * | | |By writing to this bit, the parity bit will be stored in transmitter FIFO + * | | |If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, + * | | |the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD. + * | | |Read Operation: + * | | |If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit. + * | | |Note: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set. + * @var UART_T::INTEN + * Offset: 0x04 UART Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDAIEN |Receive Data Available Interrupt Enable Bit + * | | |0 = Receive data available interrupt Disabled. + * | | |1 = Receive data available interrupt Enabled. + * |[1] |THREIEN |Transmit Holding Register Empty Interrupt Enable Bit + * | | |0 = Transmit holding register empty interrupt Disabled. + * | | |1 = Transmit holding register empty interrupt Enabled. + * |[2] |RLSIEN |Receive Line Status Interrupt Enable Bit + * | | |0 = Receive Line Status interrupt Disabled. + * | | |1 = Receive Line Status interrupt Enabled. + * |[3] |MODEMIEN |Modem Status Interrupt Enable Bit + * | | |0 = Modem status interrupt Disabled. + * | | |1 = Modem status interrupt Enabled. + * |[4] |RXTOIEN |RX Time-out Interrupt Enable Bit + * | | |0 = RX time-out interrupt Disabled. + * | | |1 = RX time-out interrupt Enabled. + * |[5] |BUFERRIEN |Buffer Error Interrupt Enable Bit + * | | |0 = Buffer error interrupt Disabled. + * | | |1 = Buffer error interrupt Enabled. + * |[6] |WKIEN |Wake-up Interrupt Enable Bit + * | | |0 = Wake-up Interrupt Disabled. + * | | |1 = Wake-up Interrupt Enabled. + * |[8] |LINIEN |LIN Bus Interrupt Enable Bit + * | | |0 = LIN bus interrupt Disabled. + * | | |1 = LIN bus interrupt Enabled. + * | | |Note: This bit is used for LIN function mode. + * |[11] |TOCNTEN |Receive Buffer Time-out Counter Enable Bit + * | | |0 = Receive Buffer Time-out counter Disabled. + * | | |1 = Receive Buffer Time-out counter Enabled. + * |[12] |ATORTSEN |nRTS Auto-flow Control Enable Bit + * | | |0 = nRTS auto-flow control Disabled. + * | | |1 = nRTS auto-flow control Enabled. + * | | |Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal. + * |[13] |ATOCTSEN |nCTS Auto-flow Control Enable Bit + * | | |0 = nCTS auto-flow control Disabled. + * | | |1 = nCTS auto-flow control Enabled. + * | | |Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted). + * |[14] |TXPDMAEN |TX PDMA Enable Bit + * | | |This bit can enable or disable TX PDMA service. + * | | |0 = TX PDMA Disabled. + * | | |1 = TX PDMA Enabled. + * | | |Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused + * | | |If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]) , UART PDMA transmit request operation is stop + * | | |Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue. + * |[15] |RXPDMAEN |RX PDMA Enable Bit + * | | |This bit can enable or disable RX PDMA service. + * | | |0 = RX PDMA Disabled. + * | | |1 = RX PDMA Enabled. + * | | |Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused + * | | |If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]) , UART PDMA receive request operation is stop + * | | |Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue. + * |[18] |ABRIEN |Auto-baud Rate Interrupt Enable Bit + * | | |0 = Auto-baud rate interrupt Disabled. + * | | |1 = Auto-baud rate interrupt Enabled. + * |[22] |TXENDIEN |Transmitter Empty Interrupt Enable Bit + * | | |If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted). + * | | |0 = Transmitter empty interrupt Disabled. + * | | |1 = Transmitter empty interrupt Enabled. + * @var UART_T::FIFO + * Offset: 0x08 UART FIFO Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |RXRST |RX Field Software Reset + * | | |When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared. + * | | |0 = No effect. + * | | |1 = Reset the RX internal state machine and pointers. + * | | |Note1: This bit will automatically clear at least 3 UART peripheral clock cycles. + * | | |Note2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set. + * |[2] |TXRST |TX Field Software Reset + * | | |When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared. + * | | |0 = No effect. + * | | |1 = Reset the TX internal state machine and pointers. + * | | |Note1: This bit will automatically clear at least 3 UART peripheral clock cycles. + * | | |Note2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set. + * |[7:4] |RFITL |RX FIFO Interrupt Trigger Level + * | | |When the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated). + * | | |0000 = RX FIFO Interrupt Trigger Level is 1 byte. + * | | |0001 = RX FIFO Interrupt Trigger Level is 4 bytes. + * | | |0010 = RX FIFO Interrupt Trigger Level is 8 bytes. + * | | |0011 = RX FIFO Interrupt Trigger Level is 14 bytes. + * | | |Others = Reserved. + * |[8] |RXOFF |Receiver Disable Bit + * | | |The receiver is disabled or not (set 1 to disable receiver). + * | | |0 = Receiver Enabled. + * | | |1 = Receiver Disabled. + * | | |Note: This bit is used for RS-485 Normal Multi-drop mode + * | | |It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed. + * |[19:16] |RTSTRGLV |nRTS Trigger Level for Auto-flow Control Use + * | | |0000 = nRTS Trigger Level is 1 byte. + * | | |0001 = nRTS Trigger Level is 4 bytes. + * | | |0010 = nRTS Trigger Level is 8 bytes. + * | | |0011 = nRTS Trigger Level is 14 bytes. + * | | |Others = Reserved. + * | | |Note: This field is used for auto nRTS flow control. + * @var UART_T::LINE + * Offset: 0x0C UART Line Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |WLS |Word Length Selection + * | | |This field sets UART word length. + * | | |00 = 5 bits. + * | | |01 = 6 bits. + * | | |10 = 7 bits. + * | | |11 = 8 bits. + * |[2] |NSB |Number of 'STOP Bit' + * | | |0 = One 'STOP bit' is generated in the transmitted data. + * | | |1 = When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data + * | | |When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data. + * |[3] |PBE |Parity Bit Enable Bit + * | | |0 = Parity bit generated Disabled. + * | | |1 = Parity bit generated Enabled. + * | | |Note: Parity bit is generated on each outgoing character and is checked on each incoming data. + * |[4] |EPE |Even Parity Enable Bit + * | | |0 = Odd number of logic '1's is transmitted and checked in each word. + * | | |1 = Even number of logic '1's is transmitted and checked in each word. + * | | |Note: This bit has effect only when PBE (UART_LINE[3]) is set. + * |[5] |SPE |Stick Parity Enable Bit + * | | |0 = Stick parity Disabled. + * | | |1 = Stick parity Enabled. + * | | |Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0 + * | | |If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1. + * |[6] |BCB |Break Control Bit + * | | |0 = Break Control Disabled. + * | | |1 = Break Control Enabled. + * | | |Note: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0) + * | | |This bit acts only on TX line and has no effect on the transmitter logic. + * |[7] |PSS |Parity Bit Source Selection + * | | |The parity bit can be selected to be generated and checked automatically or by software. + * | | |0 = Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically. + * | | |1 = Parity bit generated and checked by software. + * | | |Note1: This bit has effect only when PBE (UART_LINE[3]) is set. + * | | |Note2: If PSS is 0, the parity bit is transmitted and checked automatically + * | | |If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]). + * |[8] |TXDINV |TX Data Inverted + * | | |0 = Transmitted data signal inverted Disabled. + * | | |1 = Transmitted data signal inverted Enabled. + * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function. + * |[9] |RXDINV |RX Data Inverted + * | | |0 = Received data signal inverted Disabled. + * | | |1 = Received data signal inverted Enabled. + * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function. + * @var UART_T::MODEM + * Offset: 0x10 UART Modem Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |RTS |nRTS (Request-to-send) Signal Control + * | | |This bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration. + * | | |0 = nRTS signal is active. + * | | |1 = nRTS signal is inactive. + * | | |Note1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode. + * | | |Note2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. + * |[9] |RTSACTLV |nRTS Pin Active Level + * | | |This bit defines the active level state of nRTS pin output. + * | | |0 = nRTS pin output is high level active. + * | | |1 = nRTS pin output is low level active. (Default) + * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * |[13] |RTSSTS |nRTS Pin Status (Read Only) + * | | |This bit mirror from nRTS pin output of voltage logic status. + * | | |0 = nRTS pin output is low level voltage logic state. + * | | |1 = nRTS pin output is high level voltage logic state. + * @var UART_T::MODEMSTS + * Offset: 0x14 UART Modem Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CTSDETF |Detect nCTS State Change Flag + * | | |This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1. + * | | |0 = nCTS input has not change state. + * | | |1 = nCTS input has change state. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[4] |CTSSTS |nCTS Pin Status (Read Only) + * | | |This bit mirror from nCTS pin input of voltage logic status. + * | | |0 = nCTS pin input is low level voltage logic state. + * | | |1 = nCTS pin input is high level voltage logic state. + * | | |Note: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected. + * |[8] |CTSACTLV |nCTS Pin Active Level + * | | |This bit defines the active level state of nCTS pin input. + * | | |0 = nCTS pin input is high level active. + * | | |1 = nCTS pin input is low level active. (Default) + * | | |Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * @var UART_T::FIFOSTS + * Offset: 0x18 UART FIFO Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXOVIF |RX Overflow Error Interrupt Flag + * | | |This bit is set when RX FIFO overflow. + * | | |If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set. + * | | |0 = RX FIFO is not overflow. + * | | |1 = RX FIFO is overflow. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[1] |ABRDIF |Auto-baud Rate Detect Interrupt Flag + * | | |This bit is set to logic '1' when auto-baud rate detect function is finished. + * | | |0 = Auto-baud rate detect function is not finished. + * | | |1 = Auto-baud rate detect function is finished. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[2] |ABRDTOIF |Auto-baud Rate Detect Time-out Interrupt Flag + * | | |This bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow. + * | | |0 = Auto-baud rate counter is underflow. + * | | |1 = Auto-baud rate counter is overflow. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[3] |ADDRDETF |RS-485 Address Byte Detect Flag + * | | |0 = Receiver detects a data that is not an address bit (bit 9 ='0'). + * | | |1 = Receiver detects a data that is an address bit (bit 9 ='1'). + * | | |Note1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode. + * | | |Note2: This bit can be cleared by writing '1' to it. + * |[4] |PEF |Parity Error Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'. + * | | |0 = No parity error is generated. + * | | |1 = Parity error is generated. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[5] |FEF |Framing Error Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' + * | | |(that is, the stop bit following the last data bit or parity bit is detected as logic 0). + * | | |0 = No framing error is generated. + * | | |1 = Framing error is generated. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[6] |BIF |Break Interrupt Flag + * | | |This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) + * | | |for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). + * | | |0 = No Break interrupt is generated. + * | | |1 = Break interrupt is generated. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[13:8] |RXPTR |RX FIFO Pointer (Read Only) + * | | |This field indicates the RX FIFO Buffer Pointer + * | | |When UART receives one byte from external device, RXPTR increases one + * | | |When one byte of RX FIFO is read by CPU, RXPTR decreases one. + * | | |The Maximum value shown in RXPTR is 15 + * | | |When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0 + * | | |As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15 + * |[14] |RXEMPTY |Receiver FIFO Empty (Read Only) + * | | |This bit initiate RX FIFO empty or not. + * | | |0 = RX FIFO is not empty. + * | | |1 = RX FIFO is empty. + * | | |Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high + * | | |It will be cleared when UART receives any new data. + * |[15] |RXFULL |Receiver FIFO Full (Read Only) + * | | |This bit initiates RX FIFO full or not. + * | | |0 = RX FIFO is not full. + * | | |1 = RX FIFO is full. + * | | |Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. + * |[21:16] |TXPTR |TX FIFO Pointer (Read Only) + * | | |This field indicates the TX FIFO Buffer Pointer + * | | |When CPU writes one byte into UART_DAT, TXPTR increases one + * | | |When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one. + * | | |The Maximum value shown in TXPTR is 15 + * | | |When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0 + * | | |As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15 + * |[22] |TXEMPTY |Transmitter FIFO Empty (Read Only) + * | | |This bit indicates TX FIFO empty or not. + * | | |0 = TX FIFO is not empty. + * | | |1 = TX FIFO is empty. + * | | |Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high + * | | |It will be cleared when writing data into UART_DAT (TX FIFO not empty). + * |[23] |TXFULL |Transmitter FIFO Full (Read Only) + * | | |This bit indicates TX FIFO full or not. + * | | |0 = TX FIFO is not full. + * | | |1 = TX FIFO is full. + * | | |Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. + * |[24] |TXOVIF |TX Overflow Error Interrupt Flag + * | | |If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1. + * | | |0 = TX FIFO is not overflow. + * | | |1 = TX FIFO is overflow. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[28] |TXEMPTYF |Transmitter Empty Flag (Read Only) + * | | |This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted. + * | | |0 = TX FIFO is not empty or the STOP bit of the last byte has been not transmitted. + * | | |1 = TX FIFO is empty and the STOP bit of the last byte has been transmitted. + * | | |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. + * |[29] |RXIDLE |RX Idle Status (Read Only) + * | | |This bit is set by hardware when RX is idle. + * | | |0 = RX is busy. + * | | |1 = RX is idle. (Default) + * |[31] |TXRXACT |TX and RX Active Status (Read Only) + * | | |This bit indicates TX and RX are active or inactive. + * | | |0 = TX and RX are inactive. + * | | |1 = TX and RX are active. (Default) + * | | |Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared + * | | |The UART controller can not transmit or receive data at this moment + * | | |Otherwise this bit is set. + * @var UART_T::INTSTS + * Offset: 0x1C UART Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDAIF |Receive Data Available Interrupt Flag + * | | |When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set + * | | |If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated. + * | | |0 = No RDA interrupt flag is generated. + * | | |1 = RDA interrupt flag is generated. + * | | |Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]). + * |[1] |THREIF |Transmit Holding Register Empty Interrupt Flag + * | | |This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register + * | | |If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated. + * | | |0 = No THRE interrupt flag is generated. + * | | |1 = THRE interrupt flag is generated. + * | | |Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty). + * |[2] |RLSIF |Receive Line Interrupt Flag (Read Only) + * | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set) + * | | |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated. + * | | |0 = No RLS interrupt flag is generated. + * | | |1 = RLS interrupt flag is generated. + * | | |Note1: In RS-485 function mode, this field is set include "receiver detect and received address byte character (bit9 = '1') bit" + * | | |At the same time, the bit of ADDRDETF (UART_FIFOSTS[3]) is also set. + * | | |Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. + * | | |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. + * |[3] |MODEMIF |MODEM Interrupt Flag (Read Only) + * | | |This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS[0]) = 1) + * | | |If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated. + * | | |0 = No Modem interrupt flag is generated. + * | | |1 = Modem interrupt flag is generated. + * | | |Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]). + * |[4] |RXTOIF |RX Time-out Interrupt Flag (Read Only) + * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]) + * | | |If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated. + * | | |0 = No RX time-out interrupt flag is generated. + * | | |1 = RX time-out interrupt flag is generated. + * | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. + * |[5] |BUFERRIF |Buffer Error Interrupt Flag (Read Only) + * | | |This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set) + * | | |When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct + * | | |If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated. + * | | |0 = No buffer error interrupt flag is generated. + * | | |1 = Buffer error interrupt flag is generated. + * | | |Note: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]). + * |[6] |WKIF |UART Wake-up Interrupt Flag (Read Only) + * | | |This bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1. + * | | |0 = No UART wake-up interrupt flag is generated. + * | | |1 = UART wake-up interrupt flag is generated. + * | | |Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag. + * |[7] |LINIF |LIN Bus Interrupt Flag + * | | |This bit is set when LIN slave header detect (SLVHDETF (UART_LINSTS[0] = 1)), LIN break detect (BRKDETF(UART_LINSTS[8]=1)), bit error detect (BITEF(UART_LINSTS[9]=1)), LIN slave ID parity error (SLVIDPEF(UART_LINSTS[2] = 1)) or LIN slave header error detect (SLVHEF (UART_LINSTS[1])) + * | | |If LINIEN (UART_INTEN [8]) is enabled the LIN interrupt will be generated. + * | | |0 = None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated. + * | | |1 = At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated. + * | | |Note: This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7]). + * |[8] |RDAINT |Receive Data Available Interrupt Indicator (Read Only) + * | | |This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1. + * | | |0 = No RDA interrupt is generated. + * | | |1 = RDA interrupt is generated. + * |[9] |THREINT |Transmit Holding Register Empty Interrupt Indicator (Read Only) + * | | |This bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1. + * | | |0 = No THRE interrupt is generated. + * | | |1 = THRE interrupt is generated. + * |[10] |RLSINT |Receive Line Status Interrupt Indicator (Read Only) + * | | |This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1. + * | | |0 = No RLS interrupt is generated. + * | | |1 = RLS interrupt is generated. + * |[11] |MODEMINT |MODEM Status Interrupt Indicator (Read Only) + * | | |This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1 + * | | |0 = No Modem interrupt is generated. + * | | |1 = Modem interrupt is generated. + * |[12] |RXTOINT |RX Time-out Interrupt Indicator (Read Only) + * | | |This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1. + * | | |0 = No RX time-out interrupt is generated. + * | | |1 = RX time-out interrupt is generated. + * |[13] |BUFERRINT |Buffer Error Interrupt Indicator (Read Only) + * | | |This bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1. + * | | |0 = No buffer error interrupt is generated. + * | | |1 = Buffer error interrupt is generated. + * |[14] |WKINT |UART Wake-up Interrupt Indicator (Read Only) + * | | |This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1. + * | | |0 = No UART wake-up interrupt is generated. + * | | |1 = UART wake-up interrupt is generated. + * |[15] |LININT |LIN Bus Interrupt Indicator (Read Only) + * | | |This bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1. + * | | |0 = No LIN Bus interrupt is generated. + * | | |1 = The LIN Bus interrupt is generated. + * |[18] |HWRLSIF |PDMA Mode Receive Line Status Flag (Read Only) + * | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set) + * | | |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated. + * | | |0 = No RLS interrupt flag is generated in PDMA mode. + * | | |1 = RLS interrupt flag is generated in PDMA mode. + * | | |Note1: In RS-485 function mode, this field include "receiver detect any address byte received address byte character (bit9 = '1') bit". + * | | |Note2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. + * | | |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared + * |[19] |HWMODIF |PDMA Mode MODEM Interrupt Flag (Read Only) + * | | |This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS [0] =1)) + * | | |If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated. + * | | |0 = No Modem interrupt flag is generated in PDMA mode. + * | | |1 = Modem interrupt flag is generated in PDMA mode. + * | | |Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]). + * |[20] |HWTOIF |PDMA Mode RX Time-out Interrupt Flag (Read Only) + * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]) + * | | |If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated . + * | | |0 = No RX time-out interrupt flag is generated in PDMA mode. + * | | |1 = RX time-out interrupt flag is generated in PDMA mode. + * | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. + * |[21] |HWBUFEIF |PDMA Mode Buffer Error Interrupt Flag (Read Only) + * | | |This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set) + * | | |When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct + * | | |If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated. + * | | |0 = No buffer error interrupt flag is generated in PDMA mode. + * | | |1 = Buffer error interrupt flag is generated in PDMA mode. + * | | |Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared. + * |[22] |TXENDIF |Transmitter Empty Interrupt Flag + * | | |This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set) + * | | |If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated. + * | | |0 = No transmitter empty interrupt flag is generated. + * | | |1 = Transmitter empty interrupt flag is generated. + * | | |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. + * |[26] |HWRLSINT |PDMA Mode Receive Line Status Interrupt Indicator (Read Only) + * | | |This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1. + * | | |0 = No RLS interrupt is generated in PDMA mode. + * | | |1 = RLS interrupt is generated in PDMA mode. + * |[27] |HWMODINT |PDMA Mode MODEM Status Interrupt Indicator (Read Only) + * | | |This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1. + * | | |0 = No Modem interrupt is generated in PDMA mode. + * | | |1 = Modem interrupt is generated in PDMA mode. + * |[28] |HWTOINT |PDMA Mode RX Time-out Interrupt Indicator (Read Only) + * | | |This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1. + * | | |0 = No RX time-out interrupt is generated in PDMA mode. + * | | |1 = RX time-out interrupt is generated in PDMA mode. + * |[29] |HWBUFEINT |PDMA Mode Buffer Error Interrupt Indicator (Read Only) + * | | |This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1. + * | | |0 = No buffer error interrupt is generated in PDMA mode. + * | | |1 = Buffer error interrupt is generated in PDMA mode. + * |[30] |TXENDINT |Transmitter Empty Interrupt Indicator (Read Only) + * | | |This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1. + * | | |0 = No Transmitter Empty interrupt is generated. + * | | |1 = Transmitter Empty interrupt is generated. + * |[31] |ABRINT |Auto-baud Rate Interrupt Indicator (Read Only) + * | | |This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1. + * | | |0 = No Auto-baud Rate interrupt is generated. + * | | |1 = The Auto-baud Rate interrupt is generated. + * @var UART_T::TOUT + * Offset: 0x20 UART Time-out Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |TOIC |Time-out Interrupt Comparator + * | | |The time-out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word if time out counter is enabled by setting TOCNTEN (UART_INTEN[11]) + * | | |Once the content of time-out counter is equal to that of time-out interrupt comparator (TOIC (UART_TOUT[7:0])), a receiver time-out interrupt (RXTOINT(UART_INTSTS[12])) is generated if RXTOIEN (UART_INTEN [4]) enabled + * | | |A new incoming data word or RX FIFO empty will clear RXTOIF (UART_INTSTS[4]) + * | | |In order to avoid receiver time-out interrupt generation immediately during one character is being received, TOIC value should be set between 40 and 255 + * | | |So, for example, if TOIC is set with 40, the time-out interrupt is generated after four characters are not received when 1 stop bit and no parity check is set for UART transfer. + * |[15:8] |DLY |TX Delay Time Value + * | | |This field is used to programming the transfer delay time between the last stop bit and next start bit + * | | |The unit is bit time. + * @var UART_T::BAUD + * Offset: 0x24 UART Baud Rate Divider Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |BRD |Baud Rate Divider + * | | |The field indicates the baud rate divider + * | | |This filed is used in baud rate calculation + * | | |The detail description is shown in Table 7.15-4. + * |[27:24] |EDIVM1 |Extra Divider for BAUD Rate Mode 1 + * | | |This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2 + * | | |The detail description is shown in Table 7.15-4 + * |[28] |BAUDM0 |BAUD Rate Mode Selection Bit 0 + * | | |This bit is baud rate mode selection bit 0 + * | | |UART provides three baud rate calculation modes + * | | |This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode + * | | |The detail description is shown in Table 7.15-4. + * |[29] |BAUDM1 |BAUD Rate Mode Selection Bit 1 + * | | |This bit is baud rate mode selection bit 1 + * | | |UART provides three baud rate calculation modes + * | | |This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode + * | | |The detail description is shown in Table 7.15-4. + * | | |Note: In IrDA mode must be operated in mode 0. + * @var UART_T::IRDA + * Offset: 0x28 UART IrDA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TXEN |IrDA Receiver/Transmitter Selection Enable Bit + * | | |0 = IrDA Transmitter Disabled and Receiver Enabled. (Default) + * | | |1 = IrDA Transmitter Enabled and Receiver Disabled. + * |[5] |TXINV |IrDA Inverse Transmitting Output Signal + * | | |0 = None inverse transmitting signal. (Default). + * | | |1 = Inverse transmitting output signal. + * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function. + * |[6] |RXINV |IrDA Inverse Receive Input Signal + * | | |0 = None inverse receiving input signal. + * | | |1 = Inverse receiving input signal. (Default) + * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function. + * @var UART_T::ALTCTL + * Offset: 0x2C UART Alternate Control/Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |BRKFL |UART LIN Break Field Length + * | | |This field indicates a 4-bit LIN TX break field count. + * | | |Note1: This break field length is BRKFL + 1. + * | | |Note2: According to LIN spec, the reset value is 0xC (break field length = 13). + * |[6] |LINRXEN |LIN RX Enable Bit + * | | |0 = LIN RX mode Disabled. + * | | |1 = LIN RX mode Enabled. + * |[7] |LINTXEN |LIN TX Break Mode Enable Bit + * | | |0 = LIN TX Break mode Disabled. + * | | |1 = LIN TX Break mode Enabled. + * | | |Note: When TX break field transfer operation finished, this bit will be cleared automatically. + * |[8] |RS485NMM |RS-485 Normal Multi-drop Operation Mode (NMM) + * | | |0 = RS-485 Normal Multi-drop Operation mode (NMM) Disabled. + * | | |1 = RS-485 Normal Multi-drop Operation mode (NMM) Enabled. + * | | |Note: It cannot be active with RS-485_AAD operation mode. + * |[9] |RS485AAD |RS-485 Auto Address Detection Operation Mode (AAD) + * | | |0 = RS-485 Auto Address Detection Operation mode (AAD) Disabled. + * | | |1 = RS-485 Auto Address Detection Operation mode (AAD) Enabled. + * | | |Note: It cannot be active with RS-485_NMM operation mode. + * |[10] |RS485AUD |RS-485 Auto Direction Function (AUD) + * | | |0 = RS-485 Auto Direction Operation function (AUD) Disabled. + * | | |1 = RS-485 Auto Direction Operation function (AUD) Enabled. + * | | |Note: It can be active with RS-485_AAD or RS-485_NMM operation mode. + * |[15] |ADDRDEN |RS-485 Address Detection Enable Bit + * | | |This bit is used to enable RS-485 Address Detection mode. + * | | |0 = Address detection mode Disabled. + * | | |1 = Address detection mode Enabled. + * | | |Note: This bit is used for RS-485 any operation mode. + * |[17] |ABRIF |Auto-baud Rate Interrupt Flag (Read Only) + * | | |This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. + * | | |0 = No auto-baud rate interrupt flag is generated. + * | | |1 = Auto-baud rate interrupt flag is generated. + * | | |Note: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]) + * |[18] |ABRDEN |Auto-baud Rate Detect Enable Bit + * | | |0 = Auto-baud rate detect function Disabled. + * | | |1 = Auto-baud rate detect function Enabled. + * | | |Note : This bit is cleared automatically after auto-baud detection is finished. + * |[20:19] |ABRDBITS |Auto-baud Rate Detect Bit Length + * | | |00 = 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01. + * | | |01 = 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02. + * | | |10 = 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08. + * | | |11 = 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80. + * | | |Note : The calculation of bit number includes the START bit. + * |[31:24] |ADDRMV |Address Match Value + * | | |This field contains the RS-485 address match values. + * | | |Note: This field is used for RS-485 auto address detection mode. + * @var UART_T::FUNCSEL + * Offset: 0x30 UART Function Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |FUNCSEL |Function Select + * | | |00 = UART function. + * | | |01 = LIN function. + * | | |10 = IrDA function. + * | | |11 = RS-485 function. + * |[3] |TXRXDIS |TX and RX Disable Bit + * | | |Setting this bit can disable TX and RX. + * | | |0 = TX and RX Enabled. + * | | |1 = TX and RX Disabled. + * | | |Note: The TX and RX will not disable immediately when this bit is set + * | | |The TX and RX complete current task before disable TX and RX + * | | |When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared. + * @var UART_T::LINCTL + * Offset: 0x34 UART LIN Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SLVEN |LIN Slave Mode Enable Bit + * | | |0 = LIN slave mode Disabled. + * | | |1 = LIN slave mode Enabled. + * |[1] |SLVHDEN |LIN Slave Header Detection Enable Bit + * | | |0 = LIN slave header detection Disabled. + * | | |1 = LIN slave header detection Enabled. + * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1). + * | | |Note2: In LIN function mode, when detect header field (break + sync + frame ID), SLVHDETF (UART_LINSTS [0]) flag will be asserted + * | | |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated. + * |[2] |SLVAREN |LIN Slave Automatic Resynchronization Mode Enable Bit + * | | |0 = LIN automatic resynchronization Disabled. + * | | |1 = LIN automatic resynchronization Enabled. + * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1). + * | | |Note2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1). + * | | |Note3: The control and interactions of this field are explained in 7.15.5.9 (Slave mode with automatic resynchronization). + * |[3] |SLVDUEN |LIN Slave Divider Update Method Enable Bit + * | | |0 = UART_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time). + * | | |1 = UART_BAUD is updated at the next received character + * | | |User must set the bit before checksum reception. + * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1). + * | | |Note2: This bit used for LIN Slave Automatic Resynchronization mode + * | | |(for Non-Automatic Resynchronization mode, this bit should be kept cleared) + * | | |Note3: The control and interactions of this field are explained in 7.15.5.9 (Slave mode with automatic resynchronization). + * |[4] |MUTE |LIN Mute Mode Enable Bit + * | | |0 = LIN mute mode Disabled. + * | | |1 = LIN mute mode Enabled. + * | | |Note: The exit from mute mode condition and each control and interactions of this field are explained in 7.15.5.9 (LIN slave mode). + * |[8] |SENDH |LIN TX Send Header Enable Bit + * | | |The LIN TX header can be break field or 'break and sync field' or 'break, sync and frame ID field', it is depend on setting HSEL (UART_LINCTL[23:22]). + * | | |0 = Send LIN TX header Disabled. + * | | |1 = Send LIN TX header Enabled. + * | | |Note1: This bit is shadow bit of LINTXEN (UART_ALTCTL [7]); user can read/write it by setting LINTXEN (UART_ALTCTL [7]) or SENDH (UART_LINCTL [8]). + * | | |Note2: When transmitter header field (it may be 'break' or 'break + sync' or 'break + sync + frame ID' selected by HSEL (UART_LINCTL[23:22]) field) transfer operation finished, this bit will be cleared automatically. + * |[9] |IDPEN |LIN ID Parity Enable Bit + * | | |0 = LIN frame ID parity Disabled. + * | | |1 = LIN frame ID parity Enabled. + * | | |Note1: This bit can be used for LIN master to sending header field (SENDH (UART_LINCTL[8])) = 1 and HSEL (UART_LINCTL[23:22]) = 10 or be used for enable LIN slave received frame ID parity checked. + * | | |Note2: This bit is only used when the operation header transmitter is in HSEL (UART_LINCTL[23:22]) = 10 + * |[10] |BRKDETEN |LIN Break Detection Enable Bit + * | | |When detect consecutive dominant greater than 11 bits, and are followed by a delimiter character, the BRKDETF (UART_LINSTS[8]) flag is set at the end of break field + * | | |If the LINIEN (UART_INTEN [8])=1, an interrupt will be generated. + * | | |0 = LIN break detection Disabled . + * | | |1 = LIN break detection Enabled. + * |[11] |LINRXOFF |LIN Receiver Disable Bit + * | | |If the receiver is enabled (LINRXOFF (UART_LINCTL[11] ) = 0), all received byte data will be accepted and stored in the RX FIFO, and if the receiver is disabled (LINRXOFF (UART_LINCTL[11] = 1), all received byte data will be ignore. + * | | |0 = LIN receiver Enabled. + * | | |1 = LIN receiver Disabled. + * | | |Note: This bit is only valid when operating in LIN function mode (FUNCSEL (UART_FUNCSEL[1:0]) = 01). + * |[12] |BITERREN |Bit Error Detect Enable Bit + * | | |0 = Bit error detection function Disabled. + * | | |1 = Bit error detection function Enabled. + * | | |Note: In LIN function mode, when occur bit error, the BITEF (UART_LINSTS[9]) flag will be asserted + * | | |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated. + * |[19:16] |BRKFL |LIN Break Field Length + * | | |This field indicates a 4-bit LIN TX break field count. + * | | |Note1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]), User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]). + * | | |Note2: This break field length is BRKFL + 1. + * | | |Note3: According to LIN spec, the reset value is 12 (break field length = 13). + * |[21:20] |BSL |LIN Break/Sync Delimiter Length + * | | |00 = The LIN break/sync delimiter length is 1-bit time. + * | | |01 = The LIN break/sync delimiter length is 2-bit time. + * | | |10 = The LIN break/sync delimiter length is 3-bit time. + * | | |11 = The LIN break/sync delimiter length is 4-bit time. + * | | |Note: This bit used for LIN master to sending header field. + * |[23:22] |HSEL |LIN Header Select + * | | |00 = The LIN header includes 'break field'. + * | | |01 = The LIN header includes 'break field' and 'sync field'. + * | | |10 = The LIN header includes 'break field', 'sync field' and 'frame ID field'. + * | | |11 = Reserved. + * | | |Note: This bit is used to master mode for LIN to send header field (SENDH (UART_LINCTL [8]) = 1) or used to slave to indicates exit from mute mode condition (MUTE (UART_LINCTL[4] = 1). + * |[31:24] |PID |LIN PID Bits + * | | |This field contains the LIN frame ID value when in LIN function mode, the frame ID parity can be generated by software or hardware depends on IDPEN (UART_LINCTL[9]) = 1. + * | | |If the parity generated by hardware, user fill ID0~ID5 (PID [29:24] ), hardware will calculate P0 (PID[30]) and P1 (PID[31]), otherwise user must filled frame ID and parity in this field. + * | | |Note1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first). + * | | |Note2: This field can be used for LIN master mode or slave mode. + * @var UART_T::LINSTS + * Offset: 0x38 UART LIN Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SLVHDETF |LIN Slave Header Detection Flag + * | | |This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it. + * | | |0 = LIN header not detected. + * | | |1 = LIN header detected (break + sync + frame ID). + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enable LIN slave header detection function (SLVHDEN (UART_LINCTL [1])). + * | | |Note3: When enable ID parity check IDPEN (UART_LINCTL [9]), if hardware detect complete header ('break + sync + frame ID'), the SLVHDETF will be set whether the frame ID correct or not. + * |[1] |SLVHEF |LIN Slave Header Error Flag + * | | |This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it + * | | |The header errors include 'break delimiter is too short (less than 0.5 bit time)', 'frame error in sync field or Identifier field', + * | | |'sync field data is not 0x55 in Non-Automatic Resynchronization mode', 'sync field deviation error with Automatic Resynchronization mode', + * | | |'sync field measure time-out with Automatic Resynchronization mode' and 'LIN header reception time-out'. + * | | |0 = LIN header error not detected. + * | | |1 = LIN header error detected. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: This bit is only valid when UART is operated in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and + * | | |enables LIN slave header detection function (SLVHDEN (UART_LINCTL [1])). + * |[2] |SLVIDPEF |LIN Slave ID Parity Error Flag + * | | |This bit is set by hardware when receipted frame ID parity is not correct. + * | | |0 = No active. + * | | |1 = Receipted frame ID parity is not correct. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0])= 1) and enable LIN frame ID parity check function IDPEN (UART_LINCTL [9]). + * |[3] |SLVSYNCF |LIN Slave Sync Field + * | | |This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode + * | | |When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit. + * | | |0 = The current character is not at LIN sync state. + * | | |1 = The current character is at LIN sync state. + * | | |Note1: This bit is only valid when in LIN Slave mode (SLVEN(UART_LINCTL[0]) = 1). + * | | |Note2: This bit can be cleared by writing 1 to it. + * | | |Note3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header. + * |[8] |BRKDETF |LIN Break Detection Flag + * | | |This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software. + * | | |0 = LIN break not detected. + * | | |1 = LIN break detected. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: This bit is only valid when LIN break detection function is enabled (BRKDETEN (UART_LINCTL[10]) =1). + * |[9] |BITEF |Bit Error Detect Status Flag + * | | |At TX transfer state, hardware will monitor the bus state, if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state, BITEF (UART_LINSTS[9]) will be set. + * | | |When occur bit error, if the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated. + * | | |0 = Bit error not detected. + * | | |1 = Bit error detected. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: This bit is only valid when enable bit error detection function (BITERREN (UART_LINCTL [12]) = 1). + * @var UART_T::BRCOMP + * Offset: 0x3C UART Baud Rate Compensation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |BRCOMP |Baud Rate Compensation Patten + * | | |These 9-bits are used to define the relative bit is compensated or not. + * | | |BRCOMP[7:0] is used to define the compensation of UART_DAT[7:0] and BRCOM[8] is used to define the parity bit. + * |[31] |BRCOMPDEC |Baud Rate Compensation Decrease + * | | |0 = Positive (increase one module clock) compensation for each compensated bit. + * | | |1 = Negative (decrease one module clock) compensation for each compensated bit. + * @var UART_T::WKCTL + * Offset: 0x40 UART Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKCTSEN |nCTS Wake-up Enable Bit + * | | |0 = nCTS Wake-up system function Disabled. + * | | |1 = nCTS Wake-up system function Enabled, when the system is in Power-down mode, an external. + * | | |nCTS change will wake-up system from Power-down mode. + * |[1] |WKDATEN |Incoming Data Wake-up Enable Bit + * | | |0 = Incoming data wake-up system function Disabled. + * | | |1 = Incoming data wake-up system function Enabled, when the system is in Power-down mode,. + * | | |incoming data will wake-up system from Power-down mode. + * |[2] |WKRFRTEN |Received Data FIFO Reached Threshold Wake-up Enable Bit + * | | |0 = Received Data FIFO reached threshold wake-up system function Disabled. + * | | |1 = Received Data FIFO reached threshold wake-up system function Enabled, when the system is. + * | | |in Power-down mode, Received Data FIFO reached threshold will wake-up system from + * | | |Power-down mode. + * |[3] |WKRS485EN |RS-485 Address Match (AAD Mode) Wake-up Enable Bit + * | | |0 = RS-485 Address Match (AAD mode) wake-up system function Disabled. + * | | |1 = RS-485 Address Match (AAD mode) wake-up system function Enabled, when the system is in. + * | | |Power-down mode, RS-485 Address Match will wake-up system from Power-down mode. + * | | |Note: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode + * | | |and ADDRDEN (UART_ALTCTL[15]) is set to 1. + * |[4] |WKTOUTEN |Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit + * | | |0 = Received Data FIFO reached threshold time-out wake-up system function Disabled. + * | | |1 = Received Data FIFO reached threshold time-out wake-up system function Enabled, when the. + * | | |system is in Power-down mode, Received Data FIFO reached threshold time-out will wake-up + * | | |system from Power-down mode. + * | | |Note: It is suggest the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1. + * @var UART_T::WKSTS + * Offset: 0x44 UART Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CTSWKF |nCTS Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by nCTS wake-up. + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by nCTS wake-up. + * | | |Note1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'. + * | | |Note2: This bit can be cleared by writing '1' to it. + * |[1] |DATWKF |Incoming Data Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by data wake-up. + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by Incoming Data wake-up. + * | | |Note1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'. + * | | |Note2: This bit can be cleared by writing '1' to it. + * |[2] |RFRTWKF |Received Data FIFO Reached Threshold Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold + * | | |wake-up . + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up. + * | | |Note1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'. + * | | |Note2: This bit can be cleared by writing '1' to it. + * |[3] |RS485WKF |RS-485 Address Match (AAD Mode) Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode). + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up. + * | | |Note1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'. + * | | |Note2: This bit can be cleared by writing '1' to it. + * |[4] |TOUTWKF |Received Data FIFO Threshold Time-out Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out + * | | |wake-up. + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by Received Data FIFO reached threshold time-out. + * | | |wake-up. + * | | |Note1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'. + * | | |Note2: This bit can be cleared by writing '1' to it. + * @var UART_T::DWKCOMP + * Offset: 0x48 UART Incoming Data Wake-up Compensation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |STCOMP |Start Bit Compensation Value + * | | |These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from power-down mode. + * | | |Note: It is valid only when WKDATEN (UART_WKCTL[1]) is set. + */ + __IO uint32_t DAT; /*!< [0x0000] UART Receive/Transmit Buffer Register */ + __IO uint32_t INTEN; /*!< [0x0004] UART Interrupt Enable Register */ + __IO uint32_t FIFO; /*!< [0x0008] UART FIFO Control Register */ + __IO uint32_t LINE; /*!< [0x000c] UART Line Control Register */ + __IO uint32_t MODEM; /*!< [0x0010] UART Modem Control Register */ + __IO uint32_t MODEMSTS; /*!< [0x0014] UART Modem Status Register */ + __IO uint32_t FIFOSTS; /*!< [0x0018] UART FIFO Status Register */ + __IO uint32_t INTSTS; /*!< [0x001c] UART Interrupt Status Register */ + __IO uint32_t TOUT; /*!< [0x0020] UART Time-out Register */ + __IO uint32_t BAUD; /*!< [0x0024] UART Baud Rate Divider Register */ + __IO uint32_t IRDA; /*!< [0x0028] UART IrDA Control Register */ + __IO uint32_t ALTCTL; /*!< [0x002c] UART Alternate Control/Status Register */ + __IO uint32_t FUNCSEL; /*!< [0x0030] UART Function Select Register */ + __IO uint32_t LINCTL; /*!< [0x0034] UART LIN Control Register */ + __IO uint32_t LINSTS; /*!< [0x0038] UART LIN Status Register */ + __IO uint32_t BRCOMP; /*!< [0x003c] UART Baud Rate Compensation Register */ + __IO uint32_t WKCTL; /*!< [0x0040] UART Wake-up Control Register */ + __IO uint32_t WKSTS; /*!< [0x0044] UART Wake-up Status Register */ + __IO uint32_t DWKCOMP; /*!< [0x0048] UART Incoming Data Wake-up Compensation Register */ + +} UART_T; + +/** + @addtogroup UART_CONST UART Bit Field Definition + Constant Definitions for UART Controller +@{ */ + +#define UART_DAT_DAT_Pos (0) /*!< UART_T::DAT: DAT Position */ +#define UART_DAT_DAT_Msk (0xfful << UART_DAT_DAT_Pos) /*!< UART_T::DAT: DAT Mask */ + +#define UART_DAT_PARITY_Pos (8) /*!< UART_T::DAT: PARITY Position */ +#define UART_DAT_PARITY_Msk (0x1ul << UART_DAT_PARITY_Pos) /*!< UART_T::DAT: PARITY Mask */ + +#define UART_INTEN_RDAIEN_Pos (0) /*!< UART_T::INTEN: RDAIEN Position */ +#define UART_INTEN_RDAIEN_Msk (0x1ul << UART_INTEN_RDAIEN_Pos) /*!< UART_T::INTEN: RDAIEN Mask */ + +#define UART_INTEN_THREIEN_Pos (1) /*!< UART_T::INTEN: THREIEN Position */ +#define UART_INTEN_THREIEN_Msk (0x1ul << UART_INTEN_THREIEN_Pos) /*!< UART_T::INTEN: THREIEN Mask */ + +#define UART_INTEN_RLSIEN_Pos (2) /*!< UART_T::INTEN: RLSIEN Position */ +#define UART_INTEN_RLSIEN_Msk (0x1ul << UART_INTEN_RLSIEN_Pos) /*!< UART_T::INTEN: RLSIEN Mask */ + +#define UART_INTEN_MODEMIEN_Pos (3) /*!< UART_T::INTEN: MODEMIEN Position */ +#define UART_INTEN_MODEMIEN_Msk (0x1ul << UART_INTEN_MODEMIEN_Pos) /*!< UART_T::INTEN: MODEMIEN Mask */ + +#define UART_INTEN_RXTOIEN_Pos (4) /*!< UART_T::INTEN: RXTOIEN Position */ +#define UART_INTEN_RXTOIEN_Msk (0x1ul << UART_INTEN_RXTOIEN_Pos) /*!< UART_T::INTEN: RXTOIEN Mask */ + +#define UART_INTEN_BUFERRIEN_Pos (5) /*!< UART_T::INTEN: BUFERRIEN Position */ +#define UART_INTEN_BUFERRIEN_Msk (0x1ul << UART_INTEN_BUFERRIEN_Pos) /*!< UART_T::INTEN: BUFERRIEN Mask */ + +#define UART_INTEN_WKIEN_Pos (6) /*!< UART_T::INTEN: WKIEN Position */ +#define UART_INTEN_WKIEN_Msk (0x1ul << UART_INTEN_WKIEN_Pos) /*!< UART_T::INTEN: WKIEN Mask */ + +#define UART_INTEN_LINIEN_Pos (8) /*!< UART_T::INTEN: LINIEN Position */ +#define UART_INTEN_LINIEN_Msk (0x1ul << UART_INTEN_LINIEN_Pos) /*!< UART_T::INTEN: LINIEN Mask */ + +#define UART_INTEN_TOCNTEN_Pos (11) /*!< UART_T::INTEN: TOCNTEN Position */ +#define UART_INTEN_TOCNTEN_Msk (0x1ul << UART_INTEN_TOCNTEN_Pos) /*!< UART_T::INTEN: TOCNTEN Mask */ + +#define UART_INTEN_ATORTSEN_Pos (12) /*!< UART_T::INTEN: ATORTSEN Position */ +#define UART_INTEN_ATORTSEN_Msk (0x1ul << UART_INTEN_ATORTSEN_Pos) /*!< UART_T::INTEN: ATORTSEN Mask */ + +#define UART_INTEN_ATOCTSEN_Pos (13) /*!< UART_T::INTEN: ATOCTSEN Position */ +#define UART_INTEN_ATOCTSEN_Msk (0x1ul << UART_INTEN_ATOCTSEN_Pos) /*!< UART_T::INTEN: ATOCTSEN Mask */ + +#define UART_INTEN_TXPDMAEN_Pos (14) /*!< UART_T::INTEN: TXPDMAEN Position */ +#define UART_INTEN_TXPDMAEN_Msk (0x1ul << UART_INTEN_TXPDMAEN_Pos) /*!< UART_T::INTEN: TXPDMAEN Mask */ + +#define UART_INTEN_RXPDMAEN_Pos (15) /*!< UART_T::INTEN: RXPDMAEN Position */ +#define UART_INTEN_RXPDMAEN_Msk (0x1ul << UART_INTEN_RXPDMAEN_Pos) /*!< UART_T::INTEN: RXPDMAEN Mask */ + +#define UART_INTEN_ABRIEN_Pos (18) /*!< UART_T::INTEN: ABRIEN Position */ +#define UART_INTEN_ABRIEN_Msk (0x1ul << UART_INTEN_ABRIEN_Pos) /*!< UART_T::INTEN: ABRIEN Mask */ + +#define UART_INTEN_TXENDIEN_Pos (22) /*!< UART_T::INTEN: TXENDIEN Position */ +#define UART_INTEN_TXENDIEN_Msk (0x1ul << UART_INTEN_TXENDIEN_Pos) /*!< UART_T::INTEN: TXENDIEN Mask */ + +#define UART_FIFO_RXRST_Pos (1) /*!< UART_T::FIFO: RXRST Position */ +#define UART_FIFO_RXRST_Msk (0x1ul << UART_FIFO_RXRST_Pos) /*!< UART_T::FIFO: RXRST Mask */ + +#define UART_FIFO_TXRST_Pos (2) /*!< UART_T::FIFO: TXRST Position */ +#define UART_FIFO_TXRST_Msk (0x1ul << UART_FIFO_TXRST_Pos) /*!< UART_T::FIFO: TXRST Mask */ + +#define UART_FIFO_RFITL_Pos (4) /*!< UART_T::FIFO: RFITL Position */ +#define UART_FIFO_RFITL_Msk (0xful << UART_FIFO_RFITL_Pos) /*!< UART_T::FIFO: RFITL Mask */ + +#define UART_FIFO_RXOFF_Pos (8) /*!< UART_T::FIFO: RXOFF Position */ +#define UART_FIFO_RXOFF_Msk (0x1ul << UART_FIFO_RXOFF_Pos) /*!< UART_T::FIFO: RXOFF Mask */ + +#define UART_FIFO_RTSTRGLV_Pos (16) /*!< UART_T::FIFO: RTSTRGLV Position */ +#define UART_FIFO_RTSTRGLV_Msk (0xful << UART_FIFO_RTSTRGLV_Pos) /*!< UART_T::FIFO: RTSTRGLV Mask */ + +#define UART_LINE_WLS_Pos (0) /*!< UART_T::LINE: WLS Position */ +#define UART_LINE_WLS_Msk (0x3ul << UART_LINE_WLS_Pos) /*!< UART_T::LINE: WLS Mask */ + +#define UART_LINE_NSB_Pos (2) /*!< UART_T::LINE: NSB Position */ +#define UART_LINE_NSB_Msk (0x1ul << UART_LINE_NSB_Pos) /*!< UART_T::LINE: NSB Mask */ + +#define UART_LINE_PBE_Pos (3) /*!< UART_T::LINE: PBE Position */ +#define UART_LINE_PBE_Msk (0x1ul << UART_LINE_PBE_Pos) /*!< UART_T::LINE: PBE Mask */ + +#define UART_LINE_EPE_Pos (4) /*!< UART_T::LINE: EPE Position */ +#define UART_LINE_EPE_Msk (0x1ul << UART_LINE_EPE_Pos) /*!< UART_T::LINE: EPE Mask */ + +#define UART_LINE_SPE_Pos (5) /*!< UART_T::LINE: SPE Position */ +#define UART_LINE_SPE_Msk (0x1ul << UART_LINE_SPE_Pos) /*!< UART_T::LINE: SPE Mask */ + +#define UART_LINE_BCB_Pos (6) /*!< UART_T::LINE: BCB Position */ +#define UART_LINE_BCB_Msk (0x1ul << UART_LINE_BCB_Pos) /*!< UART_T::LINE: BCB Mask */ + +#define UART_LINE_PSS_Pos (7) /*!< UART_T::LINE: PSS Position */ +#define UART_LINE_PSS_Msk (0x1ul << UART_LINE_PSS_Pos) /*!< UART_T::LINE: PSS Mask */ + +#define UART_LINE_TXDINV_Pos (8) /*!< UART_T::LINE: TXDINV Position */ +#define UART_LINE_TXDINV_Msk (0x1ul << UART_LINE_TXDINV_Pos) /*!< UART_T::LINE: TXDINV Mask */ + +#define UART_LINE_RXDINV_Pos (9) /*!< UART_T::LINE: RXDINV Position */ +#define UART_LINE_RXDINV_Msk (0x1ul << UART_LINE_RXDINV_Pos) /*!< UART_T::LINE: RXDINV Mask */ + +#define UART_MODEM_RTS_Pos (1) /*!< UART_T::MODEM: RTS Position */ +#define UART_MODEM_RTS_Msk (0x1ul << UART_MODEM_RTS_Pos) /*!< UART_T::MODEM: RTS Mask */ + +#define UART_MODEM_RTSACTLV_Pos (9) /*!< UART_T::MODEM: RTSACTLV Position */ +#define UART_MODEM_RTSACTLV_Msk (0x1ul << UART_MODEM_RTSACTLV_Pos) /*!< UART_T::MODEM: RTSACTLV Mask */ + +#define UART_MODEM_RTSSTS_Pos (13) /*!< UART_T::MODEM: RTSSTS Position */ +#define UART_MODEM_RTSSTS_Msk (0x1ul << UART_MODEM_RTSSTS_Pos) /*!< UART_T::MODEM: RTSSTS Mask */ + +#define UART_MODEMSTS_CTSDETF_Pos (0) /*!< UART_T::MODEMSTS: CTSDETF Position */ +#define UART_MODEMSTS_CTSDETF_Msk (0x1ul << UART_MODEMSTS_CTSDETF_Pos) /*!< UART_T::MODEMSTS: CTSDETF Mask */ + +#define UART_MODEMSTS_CTSSTS_Pos (4) /*!< UART_T::MODEMSTS: CTSSTS Position */ +#define UART_MODEMSTS_CTSSTS_Msk (0x1ul << UART_MODEMSTS_CTSSTS_Pos) /*!< UART_T::MODEMSTS: CTSSTS Mask */ + +#define UART_MODEMSTS_CTSACTLV_Pos (8) /*!< UART_T::MODEMSTS: CTSACTLV Position */ +#define UART_MODEMSTS_CTSACTLV_Msk (0x1ul << UART_MODEMSTS_CTSACTLV_Pos) /*!< UART_T::MODEMSTS: CTSACTLV Mask */ + +#define UART_FIFOSTS_RXOVIF_Pos (0) /*!< UART_T::FIFOSTS: RXOVIF Position */ +#define UART_FIFOSTS_RXOVIF_Msk (0x1ul << UART_FIFOSTS_RXOVIF_Pos) /*!< UART_T::FIFOSTS: RXOVIF Mask */ + +#define UART_FIFOSTS_ABRDIF_Pos (1) /*!< UART_T::FIFOSTS: ABRDIF Position */ +#define UART_FIFOSTS_ABRDIF_Msk (0x1ul << UART_FIFOSTS_ABRDIF_Pos) /*!< UART_T::FIFOSTS: ABRDIF Mask */ + +#define UART_FIFOSTS_ABRDTOIF_Pos (2) /*!< UART_T::FIFOSTS: ABRDTOIF Position */ +#define UART_FIFOSTS_ABRDTOIF_Msk (0x1ul << UART_FIFOSTS_ABRDTOIF_Pos) /*!< UART_T::FIFOSTS: ABRDTOIF Mask */ + +#define UART_FIFOSTS_ADDRDETF_Pos (3) /*!< UART_T::FIFOSTS: ADDRDETF Position */ +#define UART_FIFOSTS_ADDRDETF_Msk (0x1ul << UART_FIFOSTS_ADDRDETF_Pos) /*!< UART_T::FIFOSTS: ADDRDETF Mask */ + +#define UART_FIFOSTS_PEF_Pos (4) /*!< UART_T::FIFOSTS: PEF Position */ +#define UART_FIFOSTS_PEF_Msk (0x1ul << UART_FIFOSTS_PEF_Pos) /*!< UART_T::FIFOSTS: PEF Mask */ + +#define UART_FIFOSTS_FEF_Pos (5) /*!< UART_T::FIFOSTS: FEF Position */ +#define UART_FIFOSTS_FEF_Msk (0x1ul << UART_FIFOSTS_FEF_Pos) /*!< UART_T::FIFOSTS: FEF Mask */ + +#define UART_FIFOSTS_BIF_Pos (6) /*!< UART_T::FIFOSTS: BIF Position */ +#define UART_FIFOSTS_BIF_Msk (0x1ul << UART_FIFOSTS_BIF_Pos) /*!< UART_T::FIFOSTS: BIF Mask */ + +#define UART_FIFOSTS_RXPTR_Pos (8) /*!< UART_T::FIFOSTS: RXPTR Position */ +#define UART_FIFOSTS_RXPTR_Msk (0x3ful << UART_FIFOSTS_RXPTR_Pos) /*!< UART_T::FIFOSTS: RXPTR Mask */ + +#define UART_FIFOSTS_RXEMPTY_Pos (14) /*!< UART_T::FIFOSTS: RXEMPTY Position */ +#define UART_FIFOSTS_RXEMPTY_Msk (0x1ul << UART_FIFOSTS_RXEMPTY_Pos) /*!< UART_T::FIFOSTS: RXEMPTY Mask */ + +#define UART_FIFOSTS_RXFULL_Pos (15) /*!< UART_T::FIFOSTS: RXFULL Position */ +#define UART_FIFOSTS_RXFULL_Msk (0x1ul << UART_FIFOSTS_RXFULL_Pos) /*!< UART_T::FIFOSTS: RXFULL Mask */ + +#define UART_FIFOSTS_TXPTR_Pos (16) /*!< UART_T::FIFOSTS: TXPTR Position */ +#define UART_FIFOSTS_TXPTR_Msk (0x3ful << UART_FIFOSTS_TXPTR_Pos) /*!< UART_T::FIFOSTS: TXPTR Mask */ + +#define UART_FIFOSTS_TXEMPTY_Pos (22) /*!< UART_T::FIFOSTS: TXEMPTY Position */ +#define UART_FIFOSTS_TXEMPTY_Msk (0x1ul << UART_FIFOSTS_TXEMPTY_Pos) /*!< UART_T::FIFOSTS: TXEMPTY Mask */ + +#define UART_FIFOSTS_TXFULL_Pos (23) /*!< UART_T::FIFOSTS: TXFULL Position */ +#define UART_FIFOSTS_TXFULL_Msk (0x1ul << UART_FIFOSTS_TXFULL_Pos) /*!< UART_T::FIFOSTS: TXFULL Mask */ + +#define UART_FIFOSTS_TXOVIF_Pos (24) /*!< UART_T::FIFOSTS: TXOVIF Position */ +#define UART_FIFOSTS_TXOVIF_Msk (0x1ul << UART_FIFOSTS_TXOVIF_Pos) /*!< UART_T::FIFOSTS: TXOVIF Mask */ + +#define UART_FIFOSTS_TXEMPTYF_Pos (28) /*!< UART_T::FIFOSTS: TXEMPTYF Position */ +#define UART_FIFOSTS_TXEMPTYF_Msk (0x1ul << UART_FIFOSTS_TXEMPTYF_Pos) /*!< UART_T::FIFOSTS: TXEMPTYF Mask */ + +#define UART_FIFOSTS_RXIDLE_Pos (29) /*!< UART_T::FIFOSTS: RXIDLE Position */ +#define UART_FIFOSTS_RXIDLE_Msk (0x1ul << UART_FIFOSTS_RXIDLE_Pos) /*!< UART_T::FIFOSTS: RXIDLE Mask */ + +#define UART_FIFOSTS_TXRXACT_Pos (31) /*!< UART_T::FIFOSTS: TXRXACT Position */ +#define UART_FIFOSTS_TXRXACT_Msk (0x1ul << UART_FIFOSTS_TXRXACT_Pos) /*!< UART_T::FIFOSTS: TXRXACT Mask */ + +#define UART_INTSTS_RDAIF_Pos (0) /*!< UART_T::INTSTS: RDAIF Position */ +#define UART_INTSTS_RDAIF_Msk (0x1ul << UART_INTSTS_RDAIF_Pos) /*!< UART_T::INTSTS: RDAIF Mask */ + +#define UART_INTSTS_THREIF_Pos (1) /*!< UART_T::INTSTS: THREIF Position */ +#define UART_INTSTS_THREIF_Msk (0x1ul << UART_INTSTS_THREIF_Pos) /*!< UART_T::INTSTS: THREIF Mask */ + +#define UART_INTSTS_RLSIF_Pos (2) /*!< UART_T::INTSTS: RLSIF Position */ +#define UART_INTSTS_RLSIF_Msk (0x1ul << UART_INTSTS_RLSIF_Pos) /*!< UART_T::INTSTS: RLSIF Mask */ + +#define UART_INTSTS_MODEMIF_Pos (3) /*!< UART_T::INTSTS: MODEMIF Position */ +#define UART_INTSTS_MODEMIF_Msk (0x1ul << UART_INTSTS_MODEMIF_Pos) /*!< UART_T::INTSTS: MODEMIF Mask */ + +#define UART_INTSTS_RXTOIF_Pos (4) /*!< UART_T::INTSTS: RXTOIF Position */ +#define UART_INTSTS_RXTOIF_Msk (0x1ul << UART_INTSTS_RXTOIF_Pos) /*!< UART_T::INTSTS: RXTOIF Mask */ + +#define UART_INTSTS_BUFERRIF_Pos (5) /*!< UART_T::INTSTS: BUFERRIF Position */ +#define UART_INTSTS_BUFERRIF_Msk (0x1ul << UART_INTSTS_BUFERRIF_Pos) /*!< UART_T::INTSTS: BUFERRIF Mask */ + +#define UART_INTSTS_WKIF_Pos (6) /*!< UART_T::INTSTS: WKIF Position */ +#define UART_INTSTS_WKIF_Msk (0x1ul << UART_INTSTS_WKIF_Pos) /*!< UART_T::INTSTS: WKIF Mask */ + +#define UART_INTSTS_LINIF_Pos (7) /*!< UART_T::INTSTS: LINIF Position */ +#define UART_INTSTS_LINIF_Msk (0x1ul << UART_INTSTS_LINIF_Pos) /*!< UART_T::INTSTS: LINIF Mask */ + +#define UART_INTSTS_RDAINT_Pos (8) /*!< UART_T::INTSTS: RDAINT Position */ +#define UART_INTSTS_RDAINT_Msk (0x1ul << UART_INTSTS_RDAINT_Pos) /*!< UART_T::INTSTS: RDAINT Mask */ + +#define UART_INTSTS_THREINT_Pos (9) /*!< UART_T::INTSTS: THREINT Position */ +#define UART_INTSTS_THREINT_Msk (0x1ul << UART_INTSTS_THREINT_Pos) /*!< UART_T::INTSTS: THREINT Mask */ + +#define UART_INTSTS_RLSINT_Pos (10) /*!< UART_T::INTSTS: RLSINT Position */ +#define UART_INTSTS_RLSINT_Msk (0x1ul << UART_INTSTS_RLSINT_Pos) /*!< UART_T::INTSTS: RLSINT Mask */ + +#define UART_INTSTS_MODEMINT_Pos (11) /*!< UART_T::INTSTS: MODEMINT Position */ +#define UART_INTSTS_MODEMINT_Msk (0x1ul << UART_INTSTS_MODEMINT_Pos) /*!< UART_T::INTSTS: MODEMINT Mask */ + +#define UART_INTSTS_RXTOINT_Pos (12) /*!< UART_T::INTSTS: RXTOINT Position */ +#define UART_INTSTS_RXTOINT_Msk (0x1ul << UART_INTSTS_RXTOINT_Pos) /*!< UART_T::INTSTS: RXTOINT Mask */ + +#define UART_INTSTS_BUFERRINT_Pos (13) /*!< UART_T::INTSTS: BUFERRINT Position */ +#define UART_INTSTS_BUFERRINT_Msk (0x1ul << UART_INTSTS_BUFERRINT_Pos) /*!< UART_T::INTSTS: BUFERRINT Mask */ + +#define UART_INTSTS_WKINT_Pos (14) /*!< UART_T::INTSTS: WKINT Position */ +#define UART_INTSTS_WKINT_Msk (0x1ul << UART_INTSTS_WKINT_Pos) /*!< UART_T::INTSTS: WKINT Mask */ + +#define UART_INTSTS_LININT_Pos (15) /*!< UART_T::INTSTS: LININT Position */ +#define UART_INTSTS_LININT_Msk (0x1ul << UART_INTSTS_LININT_Pos) /*!< UART_T::INTSTS: LININT Mask */ + +#define UART_INTSTS_HWRLSIF_Pos (18) /*!< UART_T::INTSTS: HWRLSIF Position */ +#define UART_INTSTS_HWRLSIF_Msk (0x1ul << UART_INTSTS_HWRLSIF_Pos) /*!< UART_T::INTSTS: HWRLSIF Mask */ + +#define UART_INTSTS_HWMODIF_Pos (19) /*!< UART_T::INTSTS: HWMODIF Position */ +#define UART_INTSTS_HWMODIF_Msk (0x1ul << UART_INTSTS_HWMODIF_Pos) /*!< UART_T::INTSTS: HWMODIF Mask */ + +#define UART_INTSTS_HWTOIF_Pos (20) /*!< UART_T::INTSTS: HWTOIF Position */ +#define UART_INTSTS_HWTOIF_Msk (0x1ul << UART_INTSTS_HWTOIF_Pos) /*!< UART_T::INTSTS: HWTOIF Mask */ + +#define UART_INTSTS_HWBUFEIF_Pos (21) /*!< UART_T::INTSTS: HWBUFEIF Position */ +#define UART_INTSTS_HWBUFEIF_Msk (0x1ul << UART_INTSTS_HWBUFEIF_Pos) /*!< UART_T::INTSTS: HWBUFEIF Mask */ + +#define UART_INTSTS_TXENDIF_Pos (22) /*!< UART_T::INTSTS: TXENDIF Position */ +#define UART_INTSTS_TXENDIF_Msk (0x1ul << UART_INTSTS_TXENDIF_Pos) /*!< UART_T::INTSTS: TXENDIF Mask */ + +#define UART_INTSTS_HWRLSINT_Pos (26) /*!< UART_T::INTSTS: HWRLSINT Position */ +#define UART_INTSTS_HWRLSINT_Msk (0x1ul << UART_INTSTS_HWRLSINT_Pos) /*!< UART_T::INTSTS: HWRLSINT Mask */ + +#define UART_INTSTS_HWMODINT_Pos (27) /*!< UART_T::INTSTS: HWMODINT Position */ +#define UART_INTSTS_HWMODINT_Msk (0x1ul << UART_INTSTS_HWMODINT_Pos) /*!< UART_T::INTSTS: HWMODINT Mask */ + +#define UART_INTSTS_HWTOINT_Pos (28) /*!< UART_T::INTSTS: HWTOINT Position */ +#define UART_INTSTS_HWTOINT_Msk (0x1ul << UART_INTSTS_HWTOINT_Pos) /*!< UART_T::INTSTS: HWTOINT Mask */ + +#define UART_INTSTS_HWBUFEINT_Pos (29) /*!< UART_T::INTSTS: HWBUFEINT Position */ +#define UART_INTSTS_HWBUFEINT_Msk (0x1ul << UART_INTSTS_HWBUFEINT_Pos) /*!< UART_T::INTSTS: HWBUFEINT Mask */ + +#define UART_INTSTS_TXENDINT_Pos (30) /*!< UART_T::INTSTS: TXENDINT Position */ +#define UART_INTSTS_TXENDINT_Msk (0x1ul << UART_INTSTS_TXENDINT_Pos) /*!< UART_T::INTSTS: TXENDINT Mask */ + +#define UART_INTSTS_ABRINT_Pos (31) /*!< UART_T::INTSTS: ABRINT Position */ +#define UART_INTSTS_ABRINT_Msk (0x1ul << UART_INTSTS_ABRINT_Pos) /*!< UART_T::INTSTS: ABRINT Mask */ + +#define UART_TOUT_TOIC_Pos (0) /*!< UART_T::TOUT: TOIC Position */ +#define UART_TOUT_TOIC_Msk (0xfful << UART_TOUT_TOIC_Pos) /*!< UART_T::TOUT: TOIC Mask */ + +#define UART_TOUT_DLY_Pos (8) /*!< UART_T::TOUT: DLY Position */ +#define UART_TOUT_DLY_Msk (0xfful << UART_TOUT_DLY_Pos) /*!< UART_T::TOUT: DLY Mask */ + +#define UART_BAUD_BRD_Pos (0) /*!< UART_T::BAUD: BRD Position */ +#define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos) /*!< UART_T::BAUD: BRD Mask */ + +#define UART_BAUD_EDIVM1_Pos (24) /*!< UART_T::BAUD: EDIVM1 Position */ +#define UART_BAUD_EDIVM1_Msk (0xful << UART_BAUD_EDIVM1_Pos) /*!< UART_T::BAUD: EDIVM1 Mask */ + +#define UART_BAUD_BAUDM0_Pos (28) /*!< UART_T::BAUD: BAUDM0 Position */ +#define UART_BAUD_BAUDM0_Msk (0x1ul << UART_BAUD_BAUDM0_Pos) /*!< UART_T::BAUD: BAUDM0 Mask */ + +#define UART_BAUD_BAUDM1_Pos (29) /*!< UART_T::BAUD: BAUDM1 Position */ +#define UART_BAUD_BAUDM1_Msk (0x1ul << UART_BAUD_BAUDM1_Pos) /*!< UART_T::BAUD: BAUDM1 Mask */ + +#define UART_IRDA_TXEN_Pos (1) /*!< UART_T::IRDA: TXEN Position */ +#define UART_IRDA_TXEN_Msk (0x1ul << UART_IRDA_TXEN_Pos) /*!< UART_T::IRDA: TXEN Mask */ + +#define UART_IRDA_TXINV_Pos (5) /*!< UART_T::IRDA: TXINV Position */ +#define UART_IRDA_TXINV_Msk (0x1ul << UART_IRDA_TXINV_Pos) /*!< UART_T::IRDA: TXINV Mask */ + +#define UART_IRDA_RXINV_Pos (6) /*!< UART_T::IRDA: RXINV Position */ +#define UART_IRDA_RXINV_Msk (0x1ul << UART_IRDA_RXINV_Pos) /*!< UART_T::IRDA: RXINV Mask */ + +#define UART_ALTCTL_BRKFL_Pos (0) /*!< UART_T::ALTCTL: BRKFL Position */ +#define UART_ALTCTL_BRKFL_Msk (0xful << UART_ALTCTL_BRKFL_Pos) /*!< UART_T::ALTCTL: BRKFL Mask */ + +#define UART_ALTCTL_LINRXEN_Pos (6) /*!< UART_T::ALTCTL: LINRXEN Position */ +#define UART_ALTCTL_LINRXEN_Msk (0x1ul << UART_ALTCTL_LINRXEN_Pos) /*!< UART_T::ALTCTL: LINRXEN Mask */ + +#define UART_ALTCTL_LINTXEN_Pos (7) /*!< UART_T::ALTCTL: LINTXEN Position */ +#define UART_ALTCTL_LINTXEN_Msk (0x1ul << UART_ALTCTL_LINTXEN_Pos) /*!< UART_T::ALTCTL: LINTXEN Mask */ + +#define UART_ALTCTL_RS485NMM_Pos (8) /*!< UART_T::ALTCTL: RS485NMM Position */ +#define UART_ALTCTL_RS485NMM_Msk (0x1ul << UART_ALTCTL_RS485NMM_Pos) /*!< UART_T::ALTCTL: RS485NMM Mask */ + +#define UART_ALTCTL_RS485AAD_Pos (9) /*!< UART_T::ALTCTL: RS485AAD Position */ +#define UART_ALTCTL_RS485AAD_Msk (0x1ul << UART_ALTCTL_RS485AAD_Pos) /*!< UART_T::ALTCTL: RS485AAD Mask */ + +#define UART_ALTCTL_RS485AUD_Pos (10) /*!< UART_T::ALTCTL: RS485AUD Position */ +#define UART_ALTCTL_RS485AUD_Msk (0x1ul << UART_ALTCTL_RS485AUD_Pos) /*!< UART_T::ALTCTL: RS485AUD Mask */ + +#define UART_ALTCTL_ADDRDEN_Pos (15) /*!< UART_T::ALTCTL: ADDRDEN Position */ +#define UART_ALTCTL_ADDRDEN_Msk (0x1ul << UART_ALTCTL_ADDRDEN_Pos) /*!< UART_T::ALTCTL: ADDRDEN Mask */ + +#define UART_ALTCTL_ABRIF_Pos (17) /*!< UART_T::ALTCTL: ABRIF Position */ +#define UART_ALTCTL_ABRIF_Msk (0x1ul << UART_ALTCTL_ABRIF_Pos) /*!< UART_T::ALTCTL: ABRIF Mask */ + +#define UART_ALTCTL_ABRDEN_Pos (18) /*!< UART_T::ALTCTL: ABRDEN Position */ +#define UART_ALTCTL_ABRDEN_Msk (0x1ul << UART_ALTCTL_ABRDEN_Pos) /*!< UART_T::ALTCTL: ABRDEN Mask */ + +#define UART_ALTCTL_ABRDBITS_Pos (19) /*!< UART_T::ALTCTL: ABRDBITS Position */ +#define UART_ALTCTL_ABRDBITS_Msk (0x3ul << UART_ALTCTL_ABRDBITS_Pos) /*!< UART_T::ALTCTL: ABRDBITS Mask */ + +#define UART_ALTCTL_ADDRMV_Pos (24) /*!< UART_T::ALTCTL: ADDRMV Position */ +#define UART_ALTCTL_ADDRMV_Msk (0xfful << UART_ALTCTL_ADDRMV_Pos) /*!< UART_T::ALTCTL: ADDRMV Mask */ + +#define UART_FUNCSEL_FUNCSEL_Pos (0) /*!< UART_T::FUNCSEL: FUNCSEL Position */ +#define UART_FUNCSEL_FUNCSEL_Msk (0x3ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_T::FUNCSEL: FUNCSEL Mask */ + +#define UART_FUNCSEL_TXRXDIS_Pos (3) /*!< UART_T::FUNCSEL: TXRXDIS Position */ +#define UART_FUNCSEL_TXRXDIS_Msk (0x1ul << UART_FUNCSEL_TXRXDIS_Pos) /*!< UART_T::FUNCSEL: TXRXDIS Mask */ + +#define UART_LINCTL_SLVEN_Pos (0) /*!< UART_T::LINCTL: SLVEN Position */ +#define UART_LINCTL_SLVEN_Msk (0x1ul << UART_LINCTL_SLVEN_Pos) /*!< UART_T::LINCTL: SLVEN Mask */ + +#define UART_LINCTL_SLVHDEN_Pos (1) /*!< UART_T::LINCTL: SLVHDEN Position */ +#define UART_LINCTL_SLVHDEN_Msk (0x1ul << UART_LINCTL_SLVHDEN_Pos) /*!< UART_T::LINCTL: SLVHDEN Mask */ + +#define UART_LINCTL_SLVAREN_Pos (2) /*!< UART_T::LINCTL: SLVAREN Position */ +#define UART_LINCTL_SLVAREN_Msk (0x1ul << UART_LINCTL_SLVAREN_Pos) /*!< UART_T::LINCTL: SLVAREN Mask */ + +#define UART_LINCTL_SLVDUEN_Pos (3) /*!< UART_T::LINCTL: SLVDUEN Position */ +#define UART_LINCTL_SLVDUEN_Msk (0x1ul << UART_LINCTL_SLVDUEN_Pos) /*!< UART_T::LINCTL: SLVDUEN Mask */ + +#define UART_LINCTL_MUTE_Pos (4) /*!< UART_T::LINCTL: MUTE Position */ +#define UART_LINCTL_MUTE_Msk (0x1ul << UART_LINCTL_MUTE_Pos) /*!< UART_T::LINCTL: MUTE Mask */ + +#define UART_LINCTL_SENDH_Pos (8) /*!< UART_T::LINCTL: SENDH Position */ +#define UART_LINCTL_SENDH_Msk (0x1ul << UART_LINCTL_SENDH_Pos) /*!< UART_T::LINCTL: SENDH Mask */ + +#define UART_LINCTL_IDPEN_Pos (9) /*!< UART_T::LINCTL: IDPEN Position */ +#define UART_LINCTL_IDPEN_Msk (0x1ul << UART_LINCTL_IDPEN_Pos) /*!< UART_T::LINCTL: IDPEN Mask */ + +#define UART_LINCTL_BRKDETEN_Pos (10) /*!< UART_T::LINCTL: BRKDETEN Position */ +#define UART_LINCTL_BRKDETEN_Msk (0x1ul << UART_LINCTL_BRKDETEN_Pos) /*!< UART_T::LINCTL: BRKDETEN Mask */ + +#define UART_LINCTL_LINRXOFF_Pos (11) /*!< UART_T::LINCTL: LINRXOFF Position */ +#define UART_LINCTL_LINRXOFF_Msk (0x1ul << UART_LINCTL_LINRXOFF_Pos) /*!< UART_T::LINCTL: LINRXOFF Mask */ + +#define UART_LINCTL_BITERREN_Pos (12) /*!< UART_T::LINCTL: BITERREN Position */ +#define UART_LINCTL_BITERREN_Msk (0x1ul << UART_LINCTL_BITERREN_Pos) /*!< UART_T::LINCTL: BITERREN Mask */ + +#define UART_LINCTL_BRKFL_Pos (16) /*!< UART_T::LINCTL: BRKFL Position */ +#define UART_LINCTL_BRKFL_Msk (0xful << UART_LINCTL_BRKFL_Pos) /*!< UART_T::LINCTL: BRKFL Mask */ + +#define UART_LINCTL_BSL_Pos (20) /*!< UART_T::LINCTL: BSL Position */ +#define UART_LINCTL_BSL_Msk (0x3ul << UART_LINCTL_BSL_Pos) /*!< UART_T::LINCTL: BSL Mask */ + +#define UART_LINCTL_HSEL_Pos (22) /*!< UART_T::LINCTL: HSEL Position */ +#define UART_LINCTL_HSEL_Msk (0x3ul << UART_LINCTL_HSEL_Pos) /*!< UART_T::LINCTL: HSEL Mask */ + +#define UART_LINCTL_PID_Pos (24) /*!< UART_T::LINCTL: PID Position */ +#define UART_LINCTL_PID_Msk (0xfful << UART_LINCTL_PID_Pos) /*!< UART_T::LINCTL: PID Mask */ + +#define UART_LINSTS_SLVHDETF_Pos (0) /*!< UART_T::LINSTS: SLVHDETF Position */ +#define UART_LINSTS_SLVHDETF_Msk (0x1ul << UART_LINSTS_SLVHDETF_Pos) /*!< UART_T::LINSTS: SLVHDETF Mask */ + +#define UART_LINSTS_SLVHEF_Pos (1) /*!< UART_T::LINSTS: SLVHEF Position */ +#define UART_LINSTS_SLVHEF_Msk (0x1ul << UART_LINSTS_SLVHEF_Pos) /*!< UART_T::LINSTS: SLVHEF Mask */ + +#define UART_LINSTS_SLVIDPEF_Pos (2) /*!< UART_T::LINSTS: SLVIDPEF Position */ +#define UART_LINSTS_SLVIDPEF_Msk (0x1ul << UART_LINSTS_SLVIDPEF_Pos) /*!< UART_T::LINSTS: SLVIDPEF Mask */ + +#define UART_LINSTS_SLVSYNCF_Pos (3) /*!< UART_T::LINSTS: SLVSYNCF Position */ +#define UART_LINSTS_SLVSYNCF_Msk (0x1ul << UART_LINSTS_SLVSYNCF_Pos) /*!< UART_T::LINSTS: SLVSYNCF Mask */ + +#define UART_LINSTS_BRKDETF_Pos (8) /*!< UART_T::LINSTS: BRKDETF Position */ +#define UART_LINSTS_BRKDETF_Msk (0x1ul << UART_LINSTS_BRKDETF_Pos) /*!< UART_T::LINSTS: BRKDETF Mask */ + +#define UART_LINSTS_BITEF_Pos (9) /*!< UART_T::LINSTS: BITEF Position */ +#define UART_LINSTS_BITEF_Msk (0x1ul << UART_LINSTS_BITEF_Pos) /*!< UART_T::LINSTS: BITEF Mask */ + +#define UART_BRCOMP_BRCOMP_Pos (0) /*!< UART_T::BRCOMP: BRCOMP Position */ +#define UART_BRCOMP_BRCOMP_Msk (0x1fful << UART_BRCOMP_BRCOMP_Pos) /*!< UART_T::BRCOMP: BRCOMP Mask */ + +#define UART_BRCOMP_BRCOMPDEC_Pos (31) /*!< UART_T::BRCOMP: BRCOMPDEC Position */ +#define UART_BRCOMP_BRCOMPDEC_Msk (0x1ul << UART_BRCOMP_BRCOMPDEC_Pos) /*!< UART_T::BRCOMP: BRCOMPDEC Mask */ + +#define UART_WKCTL_WKCTSEN_Pos (0) /*!< UART_T::WKCTL: WKCTSEN Position */ +#define UART_WKCTL_WKCTSEN_Msk (0x1ul << UART_WKCTL_WKCTSEN_Pos) /*!< UART_T::WKCTL: WKCTSEN Mask */ + +#define UART_WKCTL_WKDATEN_Pos (1) /*!< UART_T::WKCTL: WKDATEN Position */ +#define UART_WKCTL_WKDATEN_Msk (0x1ul << UART_WKCTL_WKDATEN_Pos) /*!< UART_T::WKCTL: WKDATEN Mask */ + +#define UART_WKCTL_WKRFRTEN_Pos (2) /*!< UART_T::WKCTL: WKRFRTEN Position */ +#define UART_WKCTL_WKRFRTEN_Msk (0x1ul << UART_WKCTL_WKRFRTEN_Pos) /*!< UART_T::WKCTL: WKRFRTEN Mask */ + +#define UART_WKCTL_WKRS485EN_Pos (3) /*!< UART_T::WKCTL: WKRS485EN Position */ +#define UART_WKCTL_WKRS485EN_Msk (0x1ul << UART_WKCTL_WKRS485EN_Pos) /*!< UART_T::WKCTL: WKRS485EN Mask */ + +#define UART_WKCTL_WKTOUTEN_Pos (4) /*!< UART_T::WKCTL: WKTOUTEN Position */ +#define UART_WKCTL_WKTOUTEN_Msk (0x1ul << UART_WKCTL_WKTOUTEN_Pos) /*!< UART_T::WKCTL: WKTOUTEN Mask */ + +#define UART_WKSTS_CTSWKF_Pos (0) /*!< UART_T::WKSTS: CTSWKF Position */ +#define UART_WKSTS_CTSWKF_Msk (0x1ul << UART_WKSTS_CTSWKF_Pos) /*!< UART_T::WKSTS: CTSWKF Mask */ + +#define UART_WKSTS_DATWKF_Pos (1) /*!< UART_T::WKSTS: DATWKF Position */ +#define UART_WKSTS_DATWKF_Msk (0x1ul << UART_WKSTS_DATWKF_Pos) /*!< UART_T::WKSTS: DATWKF Mask */ + +#define UART_WKSTS_RFRTWKF_Pos (2) /*!< UART_T::WKSTS: RFRTWKF Position */ +#define UART_WKSTS_RFRTWKF_Msk (0x1ul << UART_WKSTS_RFRTWKF_Pos) /*!< UART_T::WKSTS: RFRTWKF Mask */ + +#define UART_WKSTS_RS485WKF_Pos (3) /*!< UART_T::WKSTS: RS485WKF Position */ +#define UART_WKSTS_RS485WKF_Msk (0x1ul << UART_WKSTS_RS485WKF_Pos) /*!< UART_T::WKSTS: RS485WKF Mask */ + +#define UART_WKSTS_TOUTWKF_Pos (4) /*!< UART_T::WKSTS: TOUTWKF Position */ +#define UART_WKSTS_TOUTWKF_Msk (0x1ul << UART_WKSTS_TOUTWKF_Pos) /*!< UART_T::WKSTS: TOUTWKF Mask */ + +#define UART_DWKCOMP_STCOMP_Pos (0) /*!< UART_T::DWKCOMP: STCOMP Position */ +#define UART_DWKCOMP_STCOMP_Msk (0xfffful << UART_DWKCOMP_STCOMP_Pos) /*!< UART_T::DWKCOMP: STCOMP Mask */ + +/**@}*/ /* UART_CONST */ +/**@}*/ /* end of UART register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __UART_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/ui2c_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/ui2c_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..04222bcf978d3da1b90fe5511aa3642ce66febd6 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/ui2c_reg.h @@ -0,0 +1,583 @@ +/**************************************************************************//** + * @file ui2c_reg.h + * @version V1.00 + * @brief UI2C register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __UI2C_REG_H__ +#define __UI2C_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup UI2C I2C Mode of USCI Controller(UI2C) + Memory Mapped Structure for UI2C Controller +@{ */ + +typedef struct +{ + + + /** + * @var UI2C_T::CTL + * Offset: 0x00 USCI Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |FUNMODE |Function Mode + * | | |This bit field selects the protocol for this USCI controller + * | | |Selecting a protocol that is not available or a reserved combination disables the USCI + * | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol + * | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE. + * | | |000 = The USCI is disabled. All protocol related state machines are set to idle state. + * | | |001 = The SPI protocol is selected. + * | | |010 = The UART protocol is selected. + * | | |100 = The I2C protocol is selected. + * | | |Note: Other bit combinations are reserved. + * @var UI2C_T::BRGEN + * Offset: 0x08 USCI Baud Rate Generator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RCLKSEL |Reference Clock Source Selection + * | | |This bit selects the source signal of reference clock (fREF_CLK). + * | | |0 = Peripheral device clock fPCLK. + * | | |1 = Reserved. + * |[1] |PTCLKSEL |Protocol Clock Source Selection + * | | |This bit selects the source signal of protocol clock (fPROT_CLK). + * | | |0 = Reference clock fREF_CLK. + * | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK). + * |[3:2] |SPCLKSEL |Sample Clock Source Selection + * | | |This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor. + * | | |00 = fSAMP_CLK = fDIV_CLK. + * | | |01 = fSAMP_CLK = fPROT_CLK. + * | | |10 = fSAMP_CLK = fSCLK. + * | | |11 = fSAMP_CLK = fREF_CLK. + * |[4] |TMCNTEN |Time Measurement Counter Enable Bit + * | | |This bit enables the 10-bit timing measurement counter. + * | | |0 = Time measurement counter is Disabled. + * | | |1 = Time measurement counter is Enabled. + * |[5] |TMCNTSRC |Time Measurement Counter Clock Source Selection + * | | |0 = Time measurement counter with fPROT_CLK. + * | | |1 = Time measurement counter with fDIV_CLK. + * |[9:8] |PDSCNT |Pre-divider for Sample Counter + * | | |This bit field defines the divide ratio of the clock division from sample clock fSAMP_CLK + * | | |The divided frequency fPDS_CNT = fSAMP_CLK / (PDSCNT+1). + * |[14:10] |DSCNT |Denominator for Sample Counter + * | | |This bit field defines the divide ratio of the sample clock fSAMP_CLK. + * | | |The divided frequency fDS_CNT = fPDS_CNT / (DSCNT+1). + * | | |Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value + * |[25:16] |CLKDIV |Clock Divider + * | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ). + * | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(USCI_PROTCTL[6])) is enabled + * | | |The revised value is the average bit time between bit 5 and bit 6 + * | | |The user can use revised CLKDIV and new BRDETITV (USCI_PROTCTL[24:16]) to calculate the precise baud rate. + * @var UI2C_T::LINECTL + * Offset: 0x2C USCI Line Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LSB |LSB First Transmission Selection + * | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first. + * | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first. + * |[11:8] |DWIDTH |Word Length of Transmission + * | | |This bit field defines the data word length (amount of bits) for reception and transmission + * | | |The data word is always right-aligned in the data buffer + * | | |USCI support word length from 4 to 16 bits. + * | | |0x0: The data word contains 16 bits located at bit positions [15:0]. + * | | |0x1: Reserved. + * | | |0x2: Reserved. + * | | |0x3: Reserved. + * | | |0x4: The data word contains 4 bits located at bit positions [3:0]. + * | | |0x5: The data word contains 5 bits located at bit positions [4:0]. + * | | |... + * | | |0xF: The data word contains 15 bits located at bit positions [14:0]. + * | | |Note: In UART protocol, the length can be configured as 6~13 bits + * | | |And in I2C protocol, the length fixed as 8 bits. + * @var UI2C_T::TXDAT + * Offset: 0x30 USCI Transmit Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TXDAT |Transmit Data + * | | |Software can use this bit field to write 16-bit transmit data for transmission. + * @var UI2C_T::RXDAT + * Offset: 0x34 USCI Receive Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RXDAT |Received Data + * | | |This bit field monitors the received data which stored in receive data buffer. + * | | |Note 1: In I2C protocol, RXDAT[12:8] indicate the different transmission conditions which defined in I2C. + * | | |Note 2: In UART protocol, RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (USCI_PROTSTS[7:5]). + * @var UI2C_T::DEVADDR0 + * Offset: 0x44 USCI Device Address Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |DEVADDR |Device Address + * | | |In I2C protocol, this bit field contains the programmed slave address + * | | |If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit + * | | |Then the second address byte is also compared to DEVADDR[7:0]. + * | | |Note 1: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode. + * | | |Note 2: When software set 10'h000, the address can not be used. + * @var UI2C_T::DEVADDR1 + * Offset: 0x48 USCI Device Address Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |DEVADDR |Device Address + * | | |In I2C protocol, this bit field contains the programmed slave address + * | | |If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit + * | | |Then the second address byte is also compared to DEVADDR[7:0]. + * | | |Note 1: The DEVADDR [9:7] must be set 3'000 when I2C operating in 7-bit address mode. + * | | |Note 2: When software set 10'h000, the address can not be used. + * @var UI2C_T::ADDRMSK0 + * Offset: 0x4C USCI Device Address Mask Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |ADDRMSK |USCI Device Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |USCI support multiple address recognition with two address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not use address mask. + * @var UI2C_T::ADDRMSK1 + * Offset: 0x50 USCI Device Address Mask Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |ADDRMSK |USCI Device Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |USCI support multiple address recognition with two address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not use address mask. + * @var UI2C_T::WKCTL + * Offset: 0x54 USCI Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Wake-up Enable Bit + * | | |0 = Wake-up function Disabled. + * | | |1 = Wake-up function Enabled. + * |[1] |WKADDREN |Wake-up Address Match Enable Bit + * | | |0 = The chip is woken up according data toggle. + * | | |1 = The chip is woken up according address match. + * @var UI2C_T::WKSTS + * Offset: 0x58 USCI Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKF |Wake-up Flag + * | | |When chip is woken up from Power-down mode, this bit is set to 1 + * | | |Software can write 1 to clear this bit. + * @var UI2C_T::PROTCTL + * Offset: 0x5C USCI Protocol Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GCFUNC |General Call Function + * | | |0 = General Call Function Disabled. + * | | |1 = General Call Function Enabled. + * |[1] |AA |Assert Acknowledge Control + * | | |When AA=1 prior to address or data received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter + * | | |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line. + * |[2] |STO |I2C STOP Control + * | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically + * | | |In a slave mode, setting STO resets I2C hardware to the defined "not addressed" slave mode when bus error (USCI_PROTSTS.ERRIF = 1). + * |[3] |STA |I2C START Control + * | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. + * |[4] |ADDR10EN |Address 10-bit Function Enable Bit + * | | |0 = Address match 10 bit function is disabled. + * | | |1 = Address match 10 bit function is enabled. + * |[5] |PTRG |I2C Protocol Trigger (Write Only) + * | | |When a new state is present in the USCI_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested + * | | |It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled. + * | | |0 = I2C's stretch disabled and the I2C protocol function will go ahead. + * | | |1 = I2C's stretch active. + * |[8] |SCLOUTEN |SCL Output Enable Bit + * | | |This bit enables monitor pulling SCL to low + * | | |This monitor will pull SCL to low until it has had time to respond to an I2C interrupt. + * | | |0 = SCL output will be forced high due to open drain mechanism. + * | | |1 = I2C module may act as a slave peripheral just like in normal operation, the I2C holds the clock line low until it has had time to clear I2C interrupt. + * |[9] |MONEN |Monitor Mode Enable Bit + * | | |This bit enables monitor mode + * | | |In monitor mode the SDA output will be put in high impedance mode + * | | |This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. + * | | |0 = The monitor mode is disabled. + * | | |1 = The monitor mode is enabled. + * | | |Note: Depending on the state of the SCLOUTEN bit, the SCL output may be also forced high, preventing the module from having control over the I2C clock line. + * |[25:16] |TOCNT |Time-out Clock Cycle + * | | |This bit field indicates how many clock cycle selected by TMCNTSRC (USCI_BRGEN [5]) when each interrupt flags are clear + * | | |The time-out is enable when TOCNT bigger than 0. + * | | |Note: The TMCNTSRC (USCI_BRGEN [5]) must be set zero on I2C mode. + * |[31] |PROTEN |I2C Protocol Enable Bit + * | | |0 = I2C Protocol disable. + * | | |1 = I2C Protocol enable. + * @var UI2C_T::PROTIEN + * Offset: 0x60 USCI Protocol Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TOIEN |Time-out Interrupt Enable Control + * | | |In I2C protocol, this bit enables the interrupt generation in case of a time-out event. + * | | |0 = The time-out interrupt is disabled. + * | | |1 = The time-out interrupt is enabled. + * |[1] |STARIEN |Start Condition Received Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if a start condition is detected. + * | | |0 = The start condition interrupt is disabled. + * | | |1 = The start condition interrupt is enabled. + * |[2] |STORIEN |Stop Condition Received Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if a stop condition is detected. + * | | |0 = The stop condition interrupt is disabled. + * | | |1 = The stop condition interrupt is enabled. + * |[3] |NACKIEN |Non - Acknowledge Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if a non - acknowledge is detected by a master. + * | | |0 = The non - acknowledge interrupt is disabled. + * | | |1 = The non - acknowledge interrupt is enabled. + * |[4] |ARBLOIEN |Arbitration Lost Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if an arbitration lost event is detected. + * | | |0 = The arbitration lost interrupt is disabled. + * | | |1 = The arbitration lost interrupt is enabled. + * |[5] |ERRIEN |Error Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (USCI_PROTSTS [16])). + * | | |0 = The error interrupt is disabled. + * | | |1 = The error interrupt is enabled. + * |[6] |ACKIEN |Acknowledge Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if an acknowledge is detected by a master. + * | | |0 = The acknowledge interrupt is disabled. + * | | |1 = The acknowledge interrupt is enabled. + * @var UI2C_T::PROTSTS + * Offset: 0x64 USCI Protocol Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5] |TOIF |Time-out Interrupt Flag + * | | |0 = A time-out interrupt status has not occurred. + * | | |1 = A time-out interrupt status has occurred. + * | | |Note: It is cleared by software writing one into this bit + * |[6] |ONBUSY |On Bus Busy + * | | |Indicates that a communication is in progress on the bus + * | | |It is set by hardware when a START condition is detected + * | | |It is cleared by hardware when a STOP condition is detected + * | | |0 = The bus is IDLE (both SCLK and SDA High). + * | | |1 = The bus is busy. + * |[8] |STARIF |Start Condition Received Interrupt Flag + * | | |This bit indicates that a start condition or repeated start condition has been detected on master mode + * | | |However, this bit also indicates that a repeated start condition has been detected on slave mode. + * | | |A protocol interrupt can be generated if USCI_PROTCTL.STARIEN = 1. + * | | |0 = A start condition has not yet been detected. + * | | |1 = A start condition has been detected. + * | | |It is cleared by software writing one into this bit + * |[9] |STORIF |Stop Condition Received Interrupt Flag + * | | |This bit indicates that a stop condition has been detected on the I2C bus lines + * | | |A protocol interrupt can be generated if USCI_PROTCTL.STORIEN = 1. + * | | |0 = A stop condition has not yet been detected. + * | | |1 = A stop condition has been detected. + * | | |It is cleared by software writing one into this bit + * | | |Note: This bit is set when slave RX mode. + * |[10] |NACKIF |Non - Acknowledge Received Interrupt Flag + * | | |This bit indicates that a non - acknowledge has been received in master mode + * | | |A protocol interrupt can be generated if USCI_PROTCTL.NACKIEN = 1. + * | | |0 = A non - acknowledge has not been received. + * | | |1 = A non - acknowledge has been received. + * | | |It is cleared by software writing one into this bit + * |[11] |ARBLOIF |Arbitration Lost Interrupt Flag + * | | |This bit indicates that an arbitration has been lost + * | | |A protocol interrupt can be generated if USCI_PROTCTL.ARBLOIEN = 1. + * | | |0 = An arbitration has not been lost. + * | | |1 = An arbitration has been lost. + * | | |It is cleared by software writing one into this bit + * |[12] |ERRIF |Error Interrupt Flag + * | | |This bit indicates that a Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame + * | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit + * | | |A protocol interrupt can be generated if USCI_PROTCTL.ERRIEN = 1. + * | | |0 = An I2C error has not been detected. + * | | |1 = An I2C error has been detected. + * | | |It is cleared by software writing one into this bit + * | | |Note: This bit is set when slave mode, user must write one into STO register to the defined "not addressed" slave mode. + * |[13] |ACKIF |Acknowledge Received Interrupt Flag + * | | |This bit indicates that an acknowledge has been received in master mode + * | | |A protocol interrupt can be generated if USCI_PROTCTL.ACKIEN = 1. + * | | |0 = An acknowledge has not been received. + * | | |1 = An acknowledge has been received. + * | | |It is cleared by software writing one into this bit + * |[14] |SLASEL |Slave Select Status + * | | |This bit indicates that this device has been selected as slave. + * | | |0 = The device is not selected as slave. + * | | |1 = The device is selected as slave. + * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware. + * |[15] |SLAREAD |Slave Read Request Status + * | | |This bit indicates that a slave read request has been detected. + * | | |0 = A slave R/W bit is 1 has not been detected. + * | | |1 = A slave R/W bit is 1 has been detected. + * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware. + * |[16] |WKAKDONE |Wakeup Address Frame Acknowledge Bit Done + * | | |0 = The ACK bit cycle of address match frame isn't done. + * | | |1 = The ACK bit cycle of address match frame is done in power-down. + * | | |Note: This bit can't release when WKUPIF is set. + * |[17] |WRSTSWK |Read/Write Status Bit in Address Wakeup Frame + * | | |0 = Write command be record on the address match wakeup frame. + * | | |1 = Read command be record on the address match wakeup frame. + * |[18] |BUSHANG |Bus Hang-up + * | | |This bit indicates bus hang-up status + * | | |There is 4-bit counter count when SCL hold high and refer fSAMP_CLK + * | | |The hang-up counter will count to overflow and set this bit when SDA is low + * | | |The counter will be reset by falling edge of SCL signal. + * | | |0 = The bus is normal status for transmission. + * | | |1 = The bus is hang-up status for transmission. + * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present. + * |[19] |ERRARBLO |Error Arbitration Lost + * | | |This bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor + * | | |The I2C can send start condition when ERRARBLO is set + * | | |Thus this bit doesn't be cared on slave mode. + * | | |0 = The bus is normal status for transmission. + * | | |1 = The bus is error arbitration lost status for transmission. + * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present. + * @var UI2C_T::ADMAT + * Offset: 0x88 I2C Slave Match Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADMAT0 |USCI Address 0 Match Status Register + * | | |When address 0 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * |[1] |ADMAT1 |USCI Address 1 Match Status Register + * | | |When address 1 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * @var UI2C_T::TMCTL + * Offset: 0x8C I2C Timing Configure Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |STCTL |Setup Time Configure Control Register + * | | |This field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode. + * | | |The delay setup time is numbers of peripheral clock = STCTL x fPCLK. + * |[24:16] |HTCTL |Hold Time Configure Control Register + * | | |This field is used to generate the delay timing between SCL falling edge SDA edge in + * | | |transmission mode. + * | | |The delay hold time is numbers of peripheral clock = HTCTL x fPCLK. + */ + __IO uint32_t CTL; /*!< [0x0000] USCI Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[8]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */ + __O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */ + __I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[3]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t DEVADDR0; /*!< [0x0044] USCI Device Address Register 0 */ + __IO uint32_t DEVADDR1; /*!< [0x0048] USCI Device Address Register 1 */ + __IO uint32_t ADDRMSK0; /*!< [0x004c] USCI Device Address Mask Register 0 */ + __IO uint32_t ADDRMSK1; /*!< [0x0050] USCI Device Address Mask Register 1 */ + __IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */ + __IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */ + __IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */ + __IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */ + __IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[8]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t ADMAT; /*!< [0x0088] I2C Slave Match Address Register */ + __IO uint32_t TMCTL; /*!< [0x008c] I2C Timing Configure Control Register */ + +} UI2C_T; + +/** + @addtogroup UI2C_CONST UI2C Bit Field Definition + Constant Definitions for UI2C Controller +@{ */ + +#define UI2C_CTL_FUNMODE_Pos (0) /*!< UI2C_T::CTL: FUNMODE Position */ +#define UI2C_CTL_FUNMODE_Msk (0x7ul << UI2C_CTL_FUNMODE_Pos) /*!< UI2C_T::CTL: FUNMODE Mask */ + +#define UI2C_BRGEN_RCLKSEL_Pos (0) /*!< UI2C_T::BRGEN: RCLKSEL Position */ +#define UI2C_BRGEN_RCLKSEL_Msk (0x1ul << UI2C_BRGEN_RCLKSEL_Pos) /*!< UI2C_T::BRGEN: RCLKSEL Mask */ + +#define UI2C_BRGEN_PTCLKSEL_Pos (1) /*!< UI2C_T::BRGEN: PTCLKSEL Position */ +#define UI2C_BRGEN_PTCLKSEL_Msk (0x1ul << UI2C_BRGEN_PTCLKSEL_Pos) /*!< UI2C_T::BRGEN: PTCLKSEL Mask */ + +#define UI2C_BRGEN_SPCLKSEL_Pos (2) /*!< UI2C_T::BRGEN: SPCLKSEL Position */ +#define UI2C_BRGEN_SPCLKSEL_Msk (0x3ul << UI2C_BRGEN_SPCLKSEL_Pos) /*!< UI2C_T::BRGEN: SPCLKSEL Mask */ + +#define UI2C_BRGEN_TMCNTEN_Pos (4) /*!< UI2C_T::BRGEN: TMCNTEN Position */ +#define UI2C_BRGEN_TMCNTEN_Msk (0x1ul << UI2C_BRGEN_TMCNTEN_Pos) /*!< UI2C_T::BRGEN: TMCNTEN Mask */ + +#define UI2C_BRGEN_TMCNTSRC_Pos (5) /*!< UI2C_T::BRGEN: TMCNTSRC Position */ +#define UI2C_BRGEN_TMCNTSRC_Msk (0x1ul << UI2C_BRGEN_TMCNTSRC_Pos) /*!< UI2C_T::BRGEN: TMCNTSRC Mask */ + +#define UI2C_BRGEN_PDSCNT_Pos (8) /*!< UI2C_T::BRGEN: PDSCNT Position */ +#define UI2C_BRGEN_PDSCNT_Msk (0x3ul << UI2C_BRGEN_PDSCNT_Pos) /*!< UI2C_T::BRGEN: PDSCNT Mask */ + +#define UI2C_BRGEN_DSCNT_Pos (10) /*!< UI2C_T::BRGEN: DSCNT Position */ +#define UI2C_BRGEN_DSCNT_Msk (0x1ful << UI2C_BRGEN_DSCNT_Pos) /*!< UI2C_T::BRGEN: DSCNT Mask */ + +#define UI2C_BRGEN_CLKDIV_Pos (16) /*!< UI2C_T::BRGEN: CLKDIV Position */ +#define UI2C_BRGEN_CLKDIV_Msk (0x3fful << UI2C_BRGEN_CLKDIV_Pos) /*!< UI2C_T::BRGEN: CLKDIV Mask */ + +#define UI2C_LINECTL_LSB_Pos (0) /*!< UI2C_T::LINECTL: LSB Position */ +#define UI2C_LINECTL_LSB_Msk (0x1ul << UI2C_LINECTL_LSB_Pos) /*!< UI2C_T::LINECTL: LSB Mask */ + +#define UI2C_LINECTL_DWIDTH_Pos (8) /*!< UI2C_T::LINECTL: DWIDTH Position */ +#define UI2C_LINECTL_DWIDTH_Msk (0xful << UI2C_LINECTL_DWIDTH_Pos) /*!< UI2C_T::LINECTL: DWIDTH Mask */ + +#define UI2C_TXDAT_TXDAT_Pos (0) /*!< UI2C_T::TXDAT: TXDAT Position */ +#define UI2C_TXDAT_TXDAT_Msk (0xfffful << UI2C_TXDAT_TXDAT_Pos) /*!< UI2C_T::TXDAT: TXDAT Mask */ + +#define UI2C_RXDAT_RXDAT_Pos (0) /*!< UI2C_T::RXDAT: RXDAT Position */ +#define UI2C_RXDAT_RXDAT_Msk (0xfffful << UI2C_RXDAT_RXDAT_Pos) /*!< UI2C_T::RXDAT: RXDAT Mask */ + +#define UI2C_DEVADDR0_DEVADDR_Pos (0) /*!< UI2C_T::DEVADDR0: DEVADDR Position */ +#define UI2C_DEVADDR0_DEVADDR_Msk (0x3fful << UI2C_DEVADDR0_DEVADDR_Pos) /*!< UI2C_T::DEVADDR0: DEVADDR Mask */ + +#define UI2C_DEVADDR1_DEVADDR_Pos (0) /*!< UI2C_T::DEVADDR1: DEVADDR Position */ +#define UI2C_DEVADDR1_DEVADDR_Msk (0x3fful << UI2C_DEVADDR1_DEVADDR_Pos) /*!< UI2C_T::DEVADDR1: DEVADDR Mask */ + +#define UI2C_ADDRMSK0_ADDRMSK_Pos (0) /*!< UI2C_T::ADDRMSK0: ADDRMSK Position */ +#define UI2C_ADDRMSK0_ADDRMSK_Msk (0x3fful << UI2C_ADDRMSK0_ADDRMSK_Pos) /*!< UI2C_T::ADDRMSK0: ADDRMSK Mask */ + +#define UI2C_ADDRMSK1_ADDRMSK_Pos (0) /*!< UI2C_T::ADDRMSK1: ADDRMSK Position */ +#define UI2C_ADDRMSK1_ADDRMSK_Msk (0x3fful << UI2C_ADDRMSK1_ADDRMSK_Pos) /*!< UI2C_T::ADDRMSK1: ADDRMSK Mask */ + +#define UI2C_WKCTL_WKEN_Pos (0) /*!< UI2C_T::WKCTL: WKEN Position */ +#define UI2C_WKCTL_WKEN_Msk (0x1ul << UI2C_WKCTL_WKEN_Pos) /*!< UI2C_T::WKCTL: WKEN Mask */ + +#define UI2C_WKCTL_WKADDREN_Pos (1) /*!< UI2C_T::WKCTL: WKADDREN Position */ +#define UI2C_WKCTL_WKADDREN_Msk (0x1ul << UI2C_WKCTL_WKADDREN_Pos) /*!< UI2C_T::WKCTL: WKADDREN Mask */ + +#define UI2C_WKSTS_WKF_Pos (0) /*!< UI2C_T::WKSTS: WKF Position */ +#define UI2C_WKSTS_WKF_Msk (0x1ul << UI2C_WKSTS_WKF_Pos) /*!< UI2C_T::WKSTS: WKF Mask */ + +#define UI2C_PROTCTL_GCFUNC_Pos (0) /*!< UI2C_T::PROTCTL: GCFUNC Position */ +#define UI2C_PROTCTL_GCFUNC_Msk (0x1ul << UI2C_PROTCTL_GCFUNC_Pos) /*!< UI2C_T::PROTCTL: GCFUNC Mask */ + +#define UI2C_PROTCTL_AA_Pos (1) /*!< UI2C_T::PROTCTL: AA Position */ +#define UI2C_PROTCTL_AA_Msk (0x1ul << UI2C_PROTCTL_AA_Pos) /*!< UI2C_T::PROTCTL: AA Mask */ + +#define UI2C_PROTCTL_STO_Pos (2) /*!< UI2C_T::PROTCTL: STO Position */ +#define UI2C_PROTCTL_STO_Msk (0x1ul << UI2C_PROTCTL_STO_Pos) /*!< UI2C_T::PROTCTL: STO Mask */ + +#define UI2C_PROTCTL_STA_Pos (3) /*!< UI2C_T::PROTCTL: STA Position */ +#define UI2C_PROTCTL_STA_Msk (0x1ul << UI2C_PROTCTL_STA_Pos) /*!< UI2C_T::PROTCTL: STA Mask */ + +#define UI2C_PROTCTL_ADDR10EN_Pos (4) /*!< UI2C_T::PROTCTL: ADDR10EN Position */ +#define UI2C_PROTCTL_ADDR10EN_Msk (0x1ul << UI2C_PROTCTL_ADDR10EN_Pos) /*!< UI2C_T::PROTCTL: ADDR10EN Mask */ + +#define UI2C_PROTCTL_PTRG_Pos (5) /*!< UI2C_T::PROTCTL: PTRG Position */ +#define UI2C_PROTCTL_PTRG_Msk (0x1ul << UI2C_PROTCTL_PTRG_Pos) /*!< UI2C_T::PROTCTL: PTRG Mask */ + +#define UI2C_PROTCTL_SCLOUTEN_Pos (8) /*!< UI2C_T::PROTCTL: SCLOUTEN Position */ +#define UI2C_PROTCTL_SCLOUTEN_Msk (0x1ul << UI2C_PROTCTL_SCLOUTEN_Pos) /*!< UI2C_T::PROTCTL: SCLOUTEN Mask */ + +#define UI2C_PROTCTL_MONEN_Pos (9) /*!< UI2C_T::PROTCTL: MONEN Position */ +#define UI2C_PROTCTL_MONEN_Msk (0x1ul << UI2C_PROTCTL_MONEN_Pos) /*!< UI2C_T::PROTCTL: MONEN Mask */ + +#define UI2C_PROTCTL_TOCNT_Pos (16) /*!< UI2C_T::PROTCTL: TOCNT Position */ +#define UI2C_PROTCTL_TOCNT_Msk (0x3fful << UI2C_PROTCTL_TOCNT_Pos) /*!< UI2C_T::PROTCTL: TOCNT Mask */ + +#define UI2C_PROTCTL_PROTEN_Pos (31) /*!< UI2C_T::PROTCTL: PROTEN Position */ +#define UI2C_PROTCTL_PROTEN_Msk (0x1ul << UI2C_PROTCTL_PROTEN_Pos) /*!< UI2C_T::PROTCTL: PROTEN Mask */ + +#define UI2C_PROTIEN_TOIEN_Pos (0) /*!< UI2C_T::PROTIEN: TOIEN Position */ +#define UI2C_PROTIEN_TOIEN_Msk (0x1ul << UI2C_PROTIEN_TOIEN_Pos) /*!< UI2C_T::PROTIEN: TOIEN Mask */ + +#define UI2C_PROTIEN_STARIEN_Pos (1) /*!< UI2C_T::PROTIEN: STARIEN Position */ +#define UI2C_PROTIEN_STARIEN_Msk (0x1ul << UI2C_PROTIEN_STARIEN_Pos) /*!< UI2C_T::PROTIEN: STARIEN Mask */ + +#define UI2C_PROTIEN_STORIEN_Pos (2) /*!< UI2C_T::PROTIEN: STORIEN Position */ +#define UI2C_PROTIEN_STORIEN_Msk (0x1ul << UI2C_PROTIEN_STORIEN_Pos) /*!< UI2C_T::PROTIEN: STORIEN Mask */ + +#define UI2C_PROTIEN_NACKIEN_Pos (3) /*!< UI2C_T::PROTIEN: NACKIEN Position */ +#define UI2C_PROTIEN_NACKIEN_Msk (0x1ul << UI2C_PROTIEN_NACKIEN_Pos) /*!< UI2C_T::PROTIEN: NACKIEN Mask */ + +#define UI2C_PROTIEN_ARBLOIEN_Pos (4) /*!< UI2C_T::PROTIEN: ARBLOIEN Position */ +#define UI2C_PROTIEN_ARBLOIEN_Msk (0x1ul << UI2C_PROTIEN_ARBLOIEN_Pos) /*!< UI2C_T::PROTIEN: ARBLOIEN Mask */ + +#define UI2C_PROTIEN_ERRIEN_Pos (5) /*!< UI2C_T::PROTIEN: ERRIEN Position */ +#define UI2C_PROTIEN_ERRIEN_Msk (0x1ul << UI2C_PROTIEN_ERRIEN_Pos) /*!< UI2C_T::PROTIEN: ERRIEN Mask */ + +#define UI2C_PROTIEN_ACKIEN_Pos (6) /*!< UI2C_T::PROTIEN: ACKIEN Position */ +#define UI2C_PROTIEN_ACKIEN_Msk (0x1ul << UI2C_PROTIEN_ACKIEN_Pos) /*!< UI2C_T::PROTIEN: ACKIEN Mask */ + +#define UI2C_PROTSTS_TOIF_Pos (5) /*!< UI2C_T::PROTSTS: TOIF Position */ +#define UI2C_PROTSTS_TOIF_Msk (0x1ul << UI2C_PROTSTS_TOIF_Pos) /*!< UI2C_T::PROTSTS: TOIF Mask */ + +#define UI2C_PROTSTS_ONBUSY_Pos (6) /*!< UI2C_T::PROTSTS: ONBUSY Position */ +#define UI2C_PROTSTS_ONBUSY_Msk (0x1ul << UI2C_PROTSTS_ONBUSY_Pos) /*!< UI2C_T::PROTSTS: ONBUSY Mask */ + +#define UI2C_PROTSTS_STARIF_Pos (8) /*!< UI2C_T::PROTSTS: STARIF Position */ +#define UI2C_PROTSTS_STARIF_Msk (0x1ul << UI2C_PROTSTS_STARIF_Pos) /*!< UI2C_T::PROTSTS: STARIF Mask */ + +#define UI2C_PROTSTS_STORIF_Pos (9) /*!< UI2C_T::PROTSTS: STORIF Position */ +#define UI2C_PROTSTS_STORIF_Msk (0x1ul << UI2C_PROTSTS_STORIF_Pos) /*!< UI2C_T::PROTSTS: STORIF Mask */ + +#define UI2C_PROTSTS_NACKIF_Pos (10) /*!< UI2C_T::PROTSTS: NACKIF Position */ +#define UI2C_PROTSTS_NACKIF_Msk (0x1ul << UI2C_PROTSTS_NACKIF_Pos) /*!< UI2C_T::PROTSTS: NACKIF Mask */ + +#define UI2C_PROTSTS_ARBLOIF_Pos (11) /*!< UI2C_T::PROTSTS: ARBLOIF Position */ +#define UI2C_PROTSTS_ARBLOIF_Msk (0x1ul << UI2C_PROTSTS_ARBLOIF_Pos) /*!< UI2C_T::PROTSTS: ARBLOIF Mask */ + +#define UI2C_PROTSTS_ERRIF_Pos (12) /*!< UI2C_T::PROTSTS: ERRIF Position */ +#define UI2C_PROTSTS_ERRIF_Msk (0x1ul << UI2C_PROTSTS_ERRIF_Pos) /*!< UI2C_T::PROTSTS: ERRIF Mask */ + +#define UI2C_PROTSTS_ACKIF_Pos (13) /*!< UI2C_T::PROTSTS: ACKIF Position */ +#define UI2C_PROTSTS_ACKIF_Msk (0x1ul << UI2C_PROTSTS_ACKIF_Pos) /*!< UI2C_T::PROTSTS: ACKIF Mask */ + +#define UI2C_PROTSTS_SLASEL_Pos (14) /*!< UI2C_T::PROTSTS: SLASEL Position */ +#define UI2C_PROTSTS_SLASEL_Msk (0x1ul << UI2C_PROTSTS_SLASEL_Pos) /*!< UI2C_T::PROTSTS: SLASEL Mask */ + +#define UI2C_PROTSTS_SLAREAD_Pos (15) /*!< UI2C_T::PROTSTS: SLAREAD Position */ +#define UI2C_PROTSTS_SLAREAD_Msk (0x1ul << UI2C_PROTSTS_SLAREAD_Pos) /*!< UI2C_T::PROTSTS: SLAREAD Mask */ + +#define UI2C_PROTSTS_WKAKDONE_Pos (16) /*!< UI2C_T::PROTSTS: WKAKDONE Position */ +#define UI2C_PROTSTS_WKAKDONE_Msk (0x1ul << UI2C_PROTSTS_WKAKDONE_Pos) /*!< UI2C_T::PROTSTS: WKAKDONE Mask */ + +#define UI2C_PROTSTS_WRSTSWK_Pos (17) /*!< UI2C_T::PROTSTS: WRSTSWK Position */ +#define UI2C_PROTSTS_WRSTSWK_Msk (0x1ul << UI2C_PROTSTS_WRSTSWK_Pos) /*!< UI2C_T::PROTSTS: WRSTSWK Mask */ + +#define UI2C_PROTSTS_BUSHANG_Pos (18) /*!< UI2C_T::PROTSTS: BUSHANG Position */ +#define UI2C_PROTSTS_BUSHANG_Msk (0x1ul << UI2C_PROTSTS_BUSHANG_Pos) /*!< UI2C_T::PROTSTS: BUSHANG Mask */ + +#define UI2C_PROTSTS_ERRARBLO_Pos (19) /*!< UI2C_T::PROTSTS: ERRARBLO Position */ +#define UI2C_PROTSTS_ERRARBLO_Msk (0x1ul << UI2C_PROTSTS_ERRARBLO_Pos) /*!< UI2C_T::PROTSTS: ERRARBLO Mask */ + +#define UI2C_ADMAT_ADMAT0_Pos (0) /*!< UI2C_T::ADMAT: ADMAT0 Position */ +#define UI2C_ADMAT_ADMAT0_Msk (0x1ul << UI2C_ADMAT_ADMAT0_Pos) /*!< UI2C_T::ADMAT: ADMAT0 Mask */ + +#define UI2C_ADMAT_ADMAT1_Pos (1) /*!< UI2C_T::ADMAT: ADMAT1 Position */ +#define UI2C_ADMAT_ADMAT1_Msk (0x1ul << UI2C_ADMAT_ADMAT1_Pos) /*!< UI2C_T::ADMAT: ADMAT1 Mask */ + +#define UI2C_TMCTL_STCTL_Pos (0) /*!< UI2C_T::TMCTL: STCTL Position */ +#define UI2C_TMCTL_STCTL_Msk (0x1fful << UI2C_TMCTL_STCTL_Pos) /*!< UI2C_T::TMCTL: STCTL Mask */ + +#define UI2C_TMCTL_HTCTL_Pos (16) /*!< UI2C_T::TMCTL: HTCTL Position */ +#define UI2C_TMCTL_HTCTL_Msk (0x1fful << UI2C_TMCTL_HTCTL_Pos) /*!< UI2C_T::TMCTL: HTCTL Mask */ + +/**@}*/ /* UI2C_CONST */ +/**@}*/ /* end of UI2C register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __UI2C_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/usbd_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/usbd_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..5638db70e6e9f9c2cfd095c5505a5027e71e9b43 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/usbd_reg.h @@ -0,0 +1,649 @@ +/**************************************************************************//** + * @file usbd_reg.h + * @version V1.00 + * @brief USBD register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __USBD_REG_H__ +#define __USBD_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup USBD USB Device Controller(USBD) + Memory Mapped Structure for USBD Controller +@{ */ + +typedef struct +{ + + /** + * @var USBD_EP_T::BUFSEG + * Offset: 0x000 Endpoint n Buffer Segmentation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:3] |BUFSEG |Endpoint Buffer Segmentation + * | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is + * | | |USBD_SRAM address + { BUFSEG, 3'b000} + * | | |Where the USBD_SRAM address = USBD_BA+0x100h. + * | | |Refer to the section 7.29.5.7 for the endpoint SRAM structure and its description. + * @var USBD_EP_T::MXPLD + * Offset: 0x004 Endpoint n Maximal Payload Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |MXPLD |Maximal Payload + * | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token) + * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. + * | | |(1) When the register is written by CPU, + * | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready. + * | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host. + * | | |(2) When the register is read by CPU, + * | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host + * | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host. + * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. + * @var USBD_EP_T::CFG + * Offset: 0x008 Endpoint n Configuration Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |EPNUM |Endpoint Number + * | | |These bits are used to define the endpoint number of the current endpoint + * |[4] |ISOCH |Isochronous Endpoint + * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake. + * | | |0 = No Isochronous endpoint. + * | | |1 = Isochronous endpoint. + * |[6:5] |STATE |Endpoint STATE + * | | |00 = Endpoint is Disabled. + * | | |01 = Out endpoint. + * | | |10 = IN endpoint. + * | | |11 = Undefined. + * |[7] |DSQSYNC |Data Sequence Synchronization + * | | |0 = DATA0 PID. + * | | |1 = DATA1 PID. + * | | |Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction + * | | |hardware will toggle automatically in IN token base on the bit. + * |[9] |CSTALL |Clear STALL Response + * | | |0 = Disable the device to clear the STALL handshake in setup stage. + * | | |1 = Clear the device to response STALL handshake in setup stage. + * @var USBD_EP_T::CFGP + * Offset: 0x00C Endpoint n Set Stall and Clear In/Out Ready Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CLRRDY |Clear Ready + * | | |When the USBD_MXPLDx register is set by user, it means that the endpoint is ready to transmit or receive data + * | | |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is auto clear to 0. + * | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB. + * | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB. + * | | |This bit is write 1 only and is always 0 when it is read back. + * |[1] |SSTALL |Set STALL + * | | |0 = Disable the device to response STALL. + * | | |1 = Set the device to respond STALL automatically. + */ + __IO uint32_t BUFSEG; /*!< [0x0000] Endpoint n Buffer Segmentation Register */ + __IO uint32_t MXPLD; /*!< [0x0004] Endpoint n Maximal Payload Register */ + __IO uint32_t CFG; /*!< [0x0008] Endpoint n Configuration Register */ + __IO uint32_t CFGP; /*!< [0x000c] Endpoint n Set Stall and Clear In/Out Ready Control Register */ + +} USBD_EP_T; + +typedef struct +{ + + + /** + * @var USBD_T::INTEN + * Offset: 0x00 USB Device Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSIEN |Bus Event Interrupt Enable Bit + * | | |0 = BUS event interrupt Disabled. + * | | |1 = BUS event interrupt Enabled. + * |[1] |USBIEN |USB Event Interrupt Enable Bit + * | | |0 = USB event interrupt Disabled. + * | | |1 = USB event interrupt Enabled. + * |[2] |VBDETIEN |VBUS Detection Interrupt Enable Bit + * | | |0 = VBUS detection Interrupt Disabled. + * | | |1 = VBUS detection Interrupt Enabled. + * |[3] |NEVWKIEN |USB No-event-wake-up Interrupt Enable Bit + * | | |0 = No-event-wake-up Interrupt Disabled. + * | | |1 = No-event-wake-up Interrupt Enabled. + * |[4] |SOFIEN |Start of Frame Interrupt Enable Bit + * | | |0 = SOF Interrupt Disabled. + * | | |1 = SOF Interrupt Enabled. + * |[8] |WKEN |Wake-up Function Enable Bit + * | | |0 = USB wake-up function Disabled. + * | | |1 = USB wake-up function Enabled. + * |[15] |INNAKEN |Active NAK Function and Its Status in IN Token + * | | |0 = When device responds NAK after receiving IN token, IN NAK status will not be updated to USBD_EPSTS0 and USBD_EPSTS1register, so that the USB interrupt event will not be asserted. + * | | |1 = IN NAK status will be updated to USBD_EPSTS0 and USBD_EPSTS1 register and the USB interrupt event will be asserted, when the device responds NAK after receiving IN token. + * @var USBD_T::INTSTS + * Offset: 0x04 USB Device Interrupt Event Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSIF |BUS Interrupt Status + * | | |The BUS event means that there is one of the suspense or the resume function in the bus. + * | | |0 = No BUS event occurred. + * | | |1 = Bus event occurred; check USBD_ATTR[3:0] to know which kind of bus event was occurred, cleared by write 1 to USBD_INTSTS[0]. + * |[1] |USBIF |USB Event Interrupt Status + * | | |The USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus. + * | | |0 = No USB event occurred. + * | | |1 = USB event occurred, check EPSTS0~5[2:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[1] or EPSTS0~11 and SETUP (USBD_INTSTS[31]). + * |[2] |VBDETIF |VBUS Detection Interrupt Status + * | | |0 = There is not attached/detached event in the USB. + * | | |1 = There is attached/detached event in the USB bus and it is cleared by write 1 to USBD_INTSTS[2]. + * |[3] |NEVWKIF |No-event-wake-up Interrupt Status + * | | |0 = NEVWK event does not occur. + * | | |1 = No-event-wake-up event occurred, cleared by write 1 to USBD_INTSTS[3]. + * |[4] |SOFIF |Start of Frame Interrupt Status + * | | |0 = SOF event does not occur. + * | | |1 = SOF event occurred, cleared by write 1 to USBD_INTSTS[4]. + * |[16] |EPEVT0 |Endpoint 0's USB Event Status + * | | |0 = No event occurred in endpoint 0. + * | | |1 = USB event occurred on Endpoint 0, check USBD_EPSTS0[3:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[16] or USBD_INTSTS[1]. + * |[17] |EPEVT1 |Endpoint 1's USB Event Status + * | | |0 = No event occurred in endpoint 1. + * | | |1 = USB event occurred on Endpoint 1, check USBD_EPSTS0[7:4] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[17] or USBD_INTSTS[1]. + * |[18] |EPEVT2 |Endpoint 2's USB Event Status + * | | |0 = No event occurred in endpoint 2. + * | | |1 = USB event occurred on Endpoint 2, check USBD_EPSTS0[11:8] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[18] or USBD_INTSTS[1]. + * |[19] |EPEVT3 |Endpoint 3's USB Event Status + * | | |0 = No event occurred in endpoint 3. + * | | |1 = USB event occurred on Endpoint 3, check USBD_EPSTS0[15:12] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[19] or USBD_INTSTS[1]. + * |[20] |EPEVT4 |Endpoint 4's USB Event Status + * | | |0 = No event occurred in endpoint 4. + * | | |1 = USB event occurred on Endpoint 4, check USBD_EPSTS0[19:16] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[20] or USBD_INTSTS[1]. + * |[21] |EPEVT5 |Endpoint 5's USB Event Status + * | | |0 = No event occurred in endpoint 5. + * | | |1 = USB event occurred on Endpoint 5, check USBD_EPSTS0[23:20] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[21] or USBD_INTSTS[1]. + * |[22] |EPEVT6 |Endpoint 6's USB Event Status + * | | |0 = No event occurred in endpoint 6. + * | | |1 = USB event occurred on Endpoint 6, check USBD_EPSTS0[27:24] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[22] or USBD_INTSTS[1]. + * |[23] |EPEVT7 |Endpoint 7's USB Event Status + * | | |0 = No event occurred in endpoint 7. + * | | |1 = USB event occurred on Endpoint 7, check USBD_EPSTS0[31:28] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[23] or USBD_INTSTS[1]. + * |[24] |EPEVT8 |Endpoint 8's USB Event Status + * | | |0 = No event occurred in endpoint 8. + * | | |1 = USB event occurred on Endpoint 8, check USBD_EPSTS1[3 :0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[24] or USBD_INTSTS[1]. + * |[25] |EPEVT9 |Endpoint 9's USB Event Status + * | | |0 = No event occurred in endpoint 9. + * | | |1 = USB event occurred on Endpoint 9, check USBD_EPSTS1[7 :4] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[25] or USBD_INTSTS[1]. + * |[26] |EPEVT10 |Endpoint 10's USB Event Status + * | | |0 = No event occurred in endpoint 10. + * | | |1 = USB event occurred on Endpoint 10, check USBD_EPSTS1[11 :8] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[26] or USBD_INTSTS[1]. + * |[27] |EPEVT11 |Endpoint 11's USB Event Status + * | | |0 = No event occurred in endpoint 11. + * | | |1 = USB event occurred on Endpoint 11, check USBD_EPSTS1[ 15:12] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[27] or USBD_INTSTS[1]. + * |[31] |SETUP |Setup Event Status + * | | |0 = No Setup event. + * | | |1 = Setup event occurred, cleared by write 1 to USBD_INTSTS[31]. + * @var USBD_T::FADDR + * Offset: 0x08 USB Device Function Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |FADDR |USB Device Function Address + * @var USBD_T::EPSTS + * Offset: 0x0C USB Device Endpoint Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7] |OV |Overrun + * | | |It indicates that the received data is over the maximum payload number or not. + * | | |0 = No overrun. + * | | |1 = Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 Bytes. + * @var USBD_T::ATTR + * Offset: 0x10 USB Device Bus Status and Attribution Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |USBRST |USB Reset Status + * | | |0 = Bus no reset. + * | | |1 = Bus reset when SE0 (single-ended 0) more than 2.5us. + * | | |Note: This bit is read only. + * |[1] |SUSPEND |Suspend Status + * | | |0 = Bus no suspend. + * | | |1 = Bus idle more than 3ms, either cable is plugged off or host is sleeping. + * | | |Note: This bit is read only. + * |[2] |RESUME |Resume Status + * | | |0 = No bus resume. + * | | |1 = Resume from suspend. + * | | |Note: This bit is read only. + * |[3] |TOUT |Time-out Status + * | | |0 = No time-out. + * | | |1 = No Bus response more than 18 bits time. + * | | |Note: This bit is read only. + * |[4] |PHYEN |PHY Transceiver Function Enable Bit + * | | |0 = PHY transceiver function Disabled. + * | | |1 = PHY transceiver function Enabled. + * |[5] |RWAKEUP |Remote Wake-up + * | | |0 = Release the USB bus from K state. + * | | |1 = Force USB bus to K (USB_D+ low, USB_D-: high) state, used for remote wake-up. + * |[7] |USBEN |USB Controller Enable Bit + * | | |0 = USB Controller Disabled. + * | | |1 = USB Controller Enabled. + * |[8] |DPPUEN |Pull-up Resistor on USB_DP Enable Bit + * | | |0 = Pull-up resistor in USB_D+ bus Disabled. + * | | |1 = Pull-up resistor in USB_D+ bus Active. + * |[10] |BYTEM |CPU Access USB SRAM Size Mode Selection + * | | |0 = Word mode: The size of the transfer from CPU to USB SRAM can be Word only. + * | | |1 = Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only. + * |[11] |LPMACK |LPM Token Acknowledge Enable Bit + * | | |The NYET/ACK will be returned only on a successful LPM transaction if no errors in both the EXT token and the LPM token and a valid bLinkState = 0001 (L1) is received, else ERROR and STALL will be returned automatically, respectively. + * | | |0= the valid LPM Token will be NYET. + * | | |1= the valid LPM Token will be ACK. + * |[12] |L1SUSPEND |LPM L1 Suspend + * | | |0 = Bus no L1 state suspend. + * | | |1 = This bit is set by the hardware when LPM command to enter the L1 state is successfully received and acknowledged. + * | | |Note: This bit is read only. + * |[13] |L1RESUME |LPM L1 Resume + * | | |0 = Bus no LPM L1 state resume. + * | | |1 = LPM L1 state Resume from LPM L1 state suspend. + * | | |Note: This bit is read only. + * @var USBD_T::VBUSDET + * Offset: 0x14 USB Device VBUS Detection Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |VBUSDET |Device VBUS Detection + * | | |0 = Controller is not attached to the USB host. + * | | |1 = Controller is attached to the USB host. + * @var USBD_T::STBUFSEG + * Offset: 0x18 SETUP Token Buffer Segmentation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:3] |STBUFSEG |SETUP Token Buffer Segmentation + * | | |It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is + * | | |USBD_SRAM address + {STBUFSEG, 3'b000} + * | | |Where the USBD_SRAM address = USBD_BA+0x100h. + * | | |Note: It is used for SETUP token only. + * @var USBD_T::EPSTS0 + * Offset: 0x20 USB Device Endpoint Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[03:00] |EPSTS0 |Endpoint 0 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[07:04] |EPSTS1 |Endpoint 1 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[11:08] |EPSTS2 |Endpoint 2 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[15:12] |EPSTS3 |Endpoint 3 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[19:16] |EPSTS4 |Endpoint 4 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[23:20] |EPSTS5 |Endpoint 5 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[27:24] |EPSTS6 |Endpoint 6 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[31:28] |EPSTS7 |Endpoint 7 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * @var USBD_T::EPSTS1 + * Offset: 0x24 USB Device Endpoint Status Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |EPSTS8 |Endpoint 8 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[7:4] |EPSTS9 |Endpoint 9 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[11:8] |EPSTS10 |Endpoint 10 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[15:12] |EPSTS11 |Endpoint 11 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * @var USBD_T::LPMATTR + * Offset: 0x88 USB LPM Attribution Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |LPMLINKSTS|LPM Link State + * | | |These bits contain the bLinkState received with last ACK LPM Token + * |[7:4] |LPMBESL |LPM Best Effort Service Latency + * | | |These bits contain the BESL value received with last ACK LPM Token + * |[8] |LPMRWAKUP |LPM Remote Wakeup + * | | |This bit contains the bRemoteWake value received with last ACK LPM Token + * @var USBD_T::FN + * Offset: 0x8C USB Frame number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |FN |Frame Number + * | | |These bits contain the 11-bits frame number in the last received SOF packet. + * @var USBD_T::SE0 + * Offset: 0x90 USB Device Drive SE0 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SE0 |Drive Single Ended Zero in USB Bus + * | | |The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low. + * | | |0 = Normal operation. + * | | |1 = Force USB PHY transceiver to drive SE0. + */ + + __IO uint32_t INTEN; /*!< [0x0000] USB Device Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x0004] USB Device Interrupt Event Status Register */ + __IO uint32_t FADDR; /*!< [0x0008] USB Device Function Address Register */ + __I uint32_t EPSTS; /*!< [0x000c] USB Device Endpoint Status Register */ + __IO uint32_t ATTR; /*!< [0x0010] USB Device Bus Status and Attribution Register */ + __I uint32_t VBUSDET; /*!< [0x0014] USB Device VBUS Detection Register */ + __IO uint32_t STBUFSEG; /*!< [0x0018] SETUP Token Buffer Segmentation Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t EPSTS0; /*!< [0x0020] USB Device Endpoint Status Register 0 */ + __I uint32_t EPSTS1; /*!< [0x0024] USB Device Endpoint Status Register 1 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[24]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t LPMATTR; /*!< [0x0088] USB LPM Attribution Register */ + __I uint32_t FN; /*!< [0x008c] USB Frame number Register */ + __IO uint32_t SE0; /*!< [0x0090] USB Device Drive SE0 Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[283]; + /// @endcond //HIDDEN_SYMBOLS + USBD_EP_T EP[12]; /*!< [0x500~0x5bc] USB End Point 0 ~ 11 Configuration Register */ + +} USBD_T; + + +/** + @addtogroup USBD_CONST USBD Bit Field Definition + Constant Definitions for USBD Controller +@{ */ + +#define USBD_INTEN_BUSIEN_Pos (0) /*!< USBD_T::INTEN: BUSIEN Position */ +#define USBD_INTEN_BUSIEN_Msk (0x1ul << USBD_INTEN_BUSIEN_Pos) /*!< USBD_T::INTEN: BUSIEN Mask */ + +#define USBD_INTEN_USBIEN_Pos (1) /*!< USBD_T::INTEN: USBIEN Position */ +#define USBD_INTEN_USBIEN_Msk (0x1ul << USBD_INTEN_USBIEN_Pos) /*!< USBD_T::INTEN: USBIEN Mask */ + +#define USBD_INTEN_VBDETIEN_Pos (2) /*!< USBD_T::INTEN: VBDETIEN Position */ +#define USBD_INTEN_VBDETIEN_Msk (0x1ul << USBD_INTEN_VBDETIEN_Pos) /*!< USBD_T::INTEN: VBDETIEN Mask */ + +#define USBD_INTEN_NEVWKIEN_Pos (3) /*!< USBD_T::INTEN: NEVWKIEN Position */ +#define USBD_INTEN_NEVWKIEN_Msk (0x1ul << USBD_INTEN_NEVWKIEN_Pos) /*!< USBD_T::INTEN: NEVWKIEN Mask */ + +#define USBD_INTEN_SOFIEN_Pos (4) /*!< USBD_T::INTEN: SOFIEN Position */ +#define USBD_INTEN_SOFIEN_Msk (0x1ul << USBD_INTEN_SOFIEN_Pos) /*!< USBD_T::INTEN: SOFIEN Mask */ + +#define USBD_INTEN_WKEN_Pos (8) /*!< USBD_T::INTEN: WKEN Position */ +#define USBD_INTEN_WKEN_Msk (0x1ul << USBD_INTEN_WKEN_Pos) /*!< USBD_T::INTEN: WKEN Mask */ + +#define USBD_INTEN_INNAKEN_Pos (15) /*!< USBD_T::INTEN: INNAKEN Position */ +#define USBD_INTEN_INNAKEN_Msk (0x1ul << USBD_INTEN_INNAKEN_Pos) /*!< USBD_T::INTEN: INNAKEN Mask */ + +#define USBD_INTSTS_BUSIF_Pos (0) /*!< USBD_T::INTSTS: BUSIF Position */ +#define USBD_INTSTS_BUSIF_Msk (0x1ul << USBD_INTSTS_BUSIF_Pos) /*!< USBD_T::INTSTS: BUSIF Mask */ + +#define USBD_INTSTS_USBIF_Pos (1) /*!< USBD_T::INTSTS: USBIF Position */ +#define USBD_INTSTS_USBIF_Msk (0x1ul << USBD_INTSTS_USBIF_Pos) /*!< USBD_T::INTSTS: USBIF Mask */ + +#define USBD_INTSTS_VBDETIF_Pos (2) /*!< USBD_T::INTSTS: VBDETIF Position */ +#define USBD_INTSTS_VBDETIF_Msk (0x1ul << USBD_INTSTS_VBDETIF_Pos) /*!< USBD_T::INTSTS: VBDETIF Mask */ + +#define USBD_INTSTS_NEVWKIF_Pos (3) /*!< USBD_T::INTSTS: NEVWKIF Position */ +#define USBD_INTSTS_NEVWKIF_Msk (0x1ul << USBD_INTSTS_NEVWKIF_Pos) /*!< USBD_T::INTSTS: NEVWKIF Mask */ + +#define USBD_INTSTS_SOFIF_Pos (4) /*!< USBD_T::INTSTS: SOFIF Position */ +#define USBD_INTSTS_SOFIF_Msk (0x1ul << USBD_INTSTS_SOFIF_Pos) /*!< USBD_T::INTSTS: SOFIF Mask */ + +#define USBD_INTSTS_EPEVT0_Pos (16) /*!< USBD_T::INTSTS: EPEVT0 Position */ +#define USBD_INTSTS_EPEVT0_Msk (0x1ul << USBD_INTSTS_EPEVT0_Pos) /*!< USBD_T::INTSTS: EPEVT0 Mask */ + +#define USBD_INTSTS_EPEVT1_Pos (17) /*!< USBD_T::INTSTS: EPEVT1 Position */ +#define USBD_INTSTS_EPEVT1_Msk (0x1ul << USBD_INTSTS_EPEVT1_Pos) /*!< USBD_T::INTSTS: EPEVT1 Mask */ + +#define USBD_INTSTS_EPEVT2_Pos (18) /*!< USBD_T::INTSTS: EPEVT2 Position */ +#define USBD_INTSTS_EPEVT2_Msk (0x1ul << USBD_INTSTS_EPEVT2_Pos) /*!< USBD_T::INTSTS: EPEVT2 Mask */ + +#define USBD_INTSTS_EPEVT3_Pos (19) /*!< USBD_T::INTSTS: EPEVT3 Position */ +#define USBD_INTSTS_EPEVT3_Msk (0x1ul << USBD_INTSTS_EPEVT3_Pos) /*!< USBD_T::INTSTS: EPEVT3 Mask */ + +#define USBD_INTSTS_EPEVT4_Pos (20) /*!< USBD_T::INTSTS: EPEVT4 Position */ +#define USBD_INTSTS_EPEVT4_Msk (0x1ul << USBD_INTSTS_EPEVT4_Pos) /*!< USBD_T::INTSTS: EPEVT4 Mask */ + +#define USBD_INTSTS_EPEVT5_Pos (21) /*!< USBD_T::INTSTS: EPEVT5 Position */ +#define USBD_INTSTS_EPEVT5_Msk (0x1ul << USBD_INTSTS_EPEVT5_Pos) /*!< USBD_T::INTSTS: EPEVT5 Mask */ + +#define USBD_INTSTS_EPEVT6_Pos (22) /*!< USBD_T::INTSTS: EPEVT6 Position */ +#define USBD_INTSTS_EPEVT6_Msk (0x1ul << USBD_INTSTS_EPEVT6_Pos) /*!< USBD_T::INTSTS: EPEVT6 Mask */ + +#define USBD_INTSTS_EPEVT7_Pos (23) /*!< USBD_T::INTSTS: EPEVT7 Position */ +#define USBD_INTSTS_EPEVT7_Msk (0x1ul << USBD_INTSTS_EPEVT7_Pos) /*!< USBD_T::INTSTS: EPEVT7 Mask */ + +#define USBD_INTSTS_EPEVT8_Pos (24) /*!< USBD_T::INTSTS: EPEVT8 Position */ +#define USBD_INTSTS_EPEVT8_Msk (0x1ul << USBD_INTSTS_EPEVT8_Pos) /*!< USBD_T::INTSTS: EPEVT8 Mask */ + +#define USBD_INTSTS_EPEVT9_Pos (25) /*!< USBD_T::INTSTS: EPEVT9 Position */ +#define USBD_INTSTS_EPEVT9_Msk (0x1ul << USBD_INTSTS_EPEVT9_Pos) /*!< USBD_T::INTSTS: EPEVT9 Mask */ + +#define USBD_INTSTS_EPEVT10_Pos (26) /*!< USBD_T::INTSTS: EPEVT10 Position */ +#define USBD_INTSTS_EPEVT10_Msk (0x1ul << USBD_INTSTS_EPEVT10_Pos) /*!< USBD_T::INTSTS: EPEVT10 Mask */ + +#define USBD_INTSTS_EPEVT11_Pos (27) /*!< USBD_T::INTSTS: EPEVT11 Position */ +#define USBD_INTSTS_EPEVT11_Msk (0x1ul << USBD_INTSTS_EPEVT11_Pos) /*!< USBD_T::INTSTS: EPEVT11 Mask */ + +#define USBD_INTSTS_SETUP_Pos (31) /*!< USBD_T::INTSTS: SETUP Position */ +#define USBD_INTSTS_SETUP_Msk (0x1ul << USBD_INTSTS_SETUP_Pos) /*!< USBD_T::INTSTS: SETUP Mask */ + +#define USBD_FADDR_FADDR_Pos (0) /*!< USBD_T::FADDR: FADDR Position */ +#define USBD_FADDR_FADDR_Msk (0x7ful << USBD_FADDR_FADDR_Pos) /*!< USBD_T::FADDR: FADDR Mask */ + +#define USBD_EPSTS_OV_Pos (7) /*!< USBD_T::EPSTS: OV Position */ +#define USBD_EPSTS_OV_Msk (0x1ul << USBD_EPSTS_OV_Pos) /*!< USBD_T::EPSTS: OV Mask */ + +#define USBD_ATTR_USBRST_Pos (0) /*!< USBD_T::ATTR: USBRST Position */ +#define USBD_ATTR_USBRST_Msk (0x1ul << USBD_ATTR_USBRST_Pos) /*!< USBD_T::ATTR: USBRST Mask */ + +#define USBD_ATTR_SUSPEND_Pos (1) /*!< USBD_T::ATTR: SUSPEND Position */ +#define USBD_ATTR_SUSPEND_Msk (0x1ul << USBD_ATTR_SUSPEND_Pos) /*!< USBD_T::ATTR: SUSPEND Mask */ + +#define USBD_ATTR_RESUME_Pos (2) /*!< USBD_T::ATTR: RESUME Position */ +#define USBD_ATTR_RESUME_Msk (0x1ul << USBD_ATTR_RESUME_Pos) /*!< USBD_T::ATTR: RESUME Mask */ + +#define USBD_ATTR_TOUT_Pos (3) /*!< USBD_T::ATTR: TOUT Position */ +#define USBD_ATTR_TOUT_Msk (0x1ul << USBD_ATTR_TOUT_Pos) /*!< USBD_T::ATTR: TOUT Mask */ + +#define USBD_ATTR_PHYEN_Pos (4) /*!< USBD_T::ATTR: PHYEN Position */ +#define USBD_ATTR_PHYEN_Msk (0x1ul << USBD_ATTR_PHYEN_Pos) /*!< USBD_T::ATTR: PHYEN Mask */ + +#define USBD_ATTR_RWAKEUP_Pos (5) /*!< USBD_T::ATTR: RWAKEUP Position */ +#define USBD_ATTR_RWAKEUP_Msk (0x1ul << USBD_ATTR_RWAKEUP_Pos) /*!< USBD_T::ATTR: RWAKEUP Mask */ + +#define USBD_ATTR_USBEN_Pos (7) /*!< USBD_T::ATTR: USBEN Position */ +#define USBD_ATTR_USBEN_Msk (0x1ul << USBD_ATTR_USBEN_Pos) /*!< USBD_T::ATTR: USBEN Mask */ + +#define USBD_ATTR_DPPUEN_Pos (8) /*!< USBD_T::ATTR: DPPUEN Position */ +#define USBD_ATTR_DPPUEN_Msk (0x1ul << USBD_ATTR_DPPUEN_Pos) /*!< USBD_T::ATTR: DPPUEN Mask */ + +#define USBD_ATTR_BYTEM_Pos (10) /*!< USBD_T::ATTR: BYTEM Position */ +#define USBD_ATTR_BYTEM_Msk (0x1ul << USBD_ATTR_BYTEM_Pos) /*!< USBD_T::ATTR: BYTEM Mask */ + +#define USBD_ATTR_LPMACK_Pos (11) /*!< USBD_T::ATTR: LPMACK Position */ +#define USBD_ATTR_LPMACK_Msk (0x1ul << USBD_ATTR_LPMACK_Pos) /*!< USBD_T::ATTR: LPMACK Mask */ + +#define USBD_ATTR_L1SUSPEND_Pos (12) /*!< USBD_T::ATTR: L1SUSPEND Position */ +#define USBD_ATTR_L1SUSPEND_Msk (0x1ul << USBD_ATTR_L1SUSPEND_Pos) /*!< USBD_T::ATTR: L1SUSPEND Mask */ + +#define USBD_ATTR_L1RESUME_Pos (13) /*!< USBD_T::ATTR: L1RESUME Position */ +#define USBD_ATTR_L1RESUME_Msk (0x1ul << USBD_ATTR_L1RESUME_Pos) /*!< USBD_T::ATTR: L1RESUME Mask */ + +#define USBD_VBUSDET_VBUSDET_Pos (0) /*!< USBD_T::VBUSDET: VBUSDET Position */ +#define USBD_VBUSDET_VBUSDET_Msk (0x1ul << USBD_VBUSDET_VBUSDET_Pos) /*!< USBD_T::VBUSDET: VBUSDET Mask */ + +#define USBD_STBUFSEG_STBUFSEG_Pos (3) /*!< USBD_T::STBUFSEG: STBUFSEG Position */ +#define USBD_STBUFSEG_STBUFSEG_Msk (0x3ful << USBD_STBUFSEG_STBUFSEG_Pos) /*!< USBD_T::STBUFSEG: STBUFSEG Mask */ + +#define USBD_EPSTS0_EPSTS0_Pos (0) /*!< USBD_T::EPSTS0: EPSTS0 Position */ +#define USBD_EPSTS0_EPSTS0_Msk (0xful << USBD_EPSTS0_EPSTS0_Pos) /*!< USBD_T::EPSTS0: EPSTS0 Mask */ + +#define USBD_EPSTS0_EPSTS1_Pos (4) /*!< USBD_T::EPSTS0: EPSTS1 Position */ +#define USBD_EPSTS0_EPSTS1_Msk (0xful << USBD_EPSTS0_EPSTS1_Pos) /*!< USBD_T::EPSTS0: EPSTS1 Mask */ + +#define USBD_EPSTS0_EPSTS2_Pos (8) /*!< USBD_T::EPSTS0: EPSTS2 Position */ +#define USBD_EPSTS0_EPSTS2_Msk (0xful << USBD_EPSTS0_EPSTS2_Pos) /*!< USBD_T::EPSTS0: EPSTS2 Mask */ + +#define USBD_EPSTS0_EPSTS3_Pos (12) /*!< USBD_T::EPSTS0: EPSTS3 Position */ +#define USBD_EPSTS0_EPSTS3_Msk (0xful << USBD_EPSTS0_EPSTS3_Pos) /*!< USBD_T::EPSTS0: EPSTS3 Mask */ + +#define USBD_EPSTS0_EPSTS4_Pos (16) /*!< USBD_T::EPSTS0: EPSTS4 Position */ +#define USBD_EPSTS0_EPSTS4_Msk (0xful << USBD_EPSTS0_EPSTS4_Pos) /*!< USBD_T::EPSTS0: EPSTS4 Mask */ + +#define USBD_EPSTS0_EPSTS5_Pos (20) /*!< USBD_T::EPSTS0: EPSTS5 Position */ +#define USBD_EPSTS0_EPSTS5_Msk (0xful << USBD_EPSTS0_EPSTS5_Pos) /*!< USBD_T::EPSTS0: EPSTS5 Mask */ + +#define USBD_EPSTS0_EPSTS6_Pos (24) /*!< USBD_T::EPSTS0: EPSTS6 Position */ +#define USBD_EPSTS0_EPSTS6_Msk (0xful << USBD_EPSTS0_EPSTS6_Pos) /*!< USBD_T::EPSTS0: EPSTS6 Mask */ + +#define USBD_EPSTS0_EPSTS7_Pos (28) /*!< USBD_T::EPSTS0: EPSTS7 Position */ +#define USBD_EPSTS0_EPSTS7_Msk (0xful << USBD_EPSTS0_EPSTS7_Pos) /*!< USBD_T::EPSTS0: EPSTS7 Mask */ + +#define USBD_EPSTS1_EPSTS8_Pos (0) /*!< USBD_T::EPSTS1: EPSTS8 Position */ +#define USBD_EPSTS1_EPSTS8_Msk (0xful << USBD_EPSTS1_EPSTS8_Pos) /*!< USBD_T::EPSTS1: EPSTS8 Mask */ + +#define USBD_EPSTS1_EPSTS9_Pos (4) /*!< USBD_T::EPSTS1: EPSTS9 Position */ +#define USBD_EPSTS1_EPSTS9_Msk (0xful << USBD_EPSTS1_EPSTS9_Pos) /*!< USBD_T::EPSTS1: EPSTS9 Mask */ + +#define USBD_EPSTS1_EPSTS10_Pos (8) /*!< USBD_T::EPSTS1: EPSTS10 Position */ +#define USBD_EPSTS1_EPSTS10_Msk (0xful << USBD_EPSTS1_EPSTS10_Pos) /*!< USBD_T::EPSTS1: EPSTS10 Mask */ + +#define USBD_EPSTS1_EPSTS11_Pos (12) /*!< USBD_T::EPSTS1: EPSTS11 Position */ +#define USBD_EPSTS1_EPSTS11_Msk (0xful << USBD_EPSTS1_EPSTS11_Pos) /*!< USBD_T::EPSTS1: EPSTS11 Mask */ + +#define USBD_LPMATTR_LPMLINKSTS_Pos (0) /*!< USBD_T::LPMATTR: LPMLINKSTS Position */ +#define USBD_LPMATTR_LPMLINKSTS_Msk (0xful << USBD_LPMATTR_LPMLINKSTS_Pos) /*!< USBD_T::LPMATTR: LPMLINKSTS Mask */ + +#define USBD_LPMATTR_LPMBESL_Pos (4) /*!< USBD_T::LPMATTR: LPMBESL Position */ +#define USBD_LPMATTR_LPMBESL_Msk (0xful << USBD_LPMATTR_LPMBESL_Pos) /*!< USBD_T::LPMATTR: LPMBESL Mask */ + +#define USBD_LPMATTR_LPMRWAKUP_Pos (8) /*!< USBD_T::LPMATTR: LPMRWAKUP Position */ +#define USBD_LPMATTR_LPMRWAKUP_Msk (0x1ul << USBD_LPMATTR_LPMRWAKUP_Pos) /*!< USBD_T::LPMATTR: LPMRWAKUP Mask */ + +#define USBD_FN_FN_Pos (0) /*!< USBD_T::FN: FN Position */ +#define USBD_FN_FN_Msk (0x7fful << USBD_FN_FN_Pos) /*!< USBD_T::FN: FN Mask */ + +#define USBD_SE0_SE0_Pos (0) /*!< USBD_T::SE0: SE0 Position */ +#define USBD_SE0_SE0_Msk (0x1ul << USBD_SE0_SE0_Pos) /*!< USBD_T::SE0: SE0 Mask */ + +#define USBD_BUFSEG_BUFSEG_Pos (3) /*!< USBD_EP_T::BUFSEG: BUFSEG Position */ +#define USBD_BUFSEG_BUFSEG_Msk (0x3ful << USBD_BUFSEG_BUFSEG_Pos) /*!< USBD_EP_T::BUFSEG: BUFSEG Mask */ + +#define USBD_MXPLD_MXPLD_Pos (0) /*!< USBD_EP_T::MXPLD: MXPLD Position */ +#define USBD_MXPLD_MXPLD_Msk (0x1fful << USBD_MXPLD_MXPLD_Pos) /*!< USBD_EP_T::MXPLD: MXPLD Mask */ + +#define USBD_CFG_EPNUM_Pos (0) /*!< USBD_EP_T::CFG: EPNUM Position */ +#define USBD_CFG_EPNUM_Msk (0xful << USBD_CFG_EPNUM_Pos) /*!< USBD_EP_T::CFG: EPNUM Mask */ + +#define USBD_CFG_ISOCH_Pos (4) /*!< USBD_EP_T::CFG: ISOCH Position */ +#define USBD_CFG_ISOCH_Msk (0x1ul << USBD_CFG_ISOCH_Pos) /*!< USBD_EP_T::CFG: ISOCH Mask */ + +#define USBD_CFG_STATE_Pos (5) /*!< USBD_EP_T::CFG: STATE Position */ +#define USBD_CFG_STATE_Msk (0x3ul << USBD_CFG_STATE_Pos) /*!< USBD_EP_T::CFG: STATE Mask */ + +#define USBD_CFG_DSQSYNC_Pos (7) /*!< USBD_EP_T::CFG: DSQSYNC Position */ +#define USBD_CFG_DSQSYNC_Msk (0x1ul << USBD_CFG_DSQSYNC_Pos) /*!< USBD_EP_T::CFG: DSQSYNC Mask */ + +#define USBD_CFG_CSTALL_Pos (9) /*!< USBD_EP_T::CFG: CSTALL Position */ +#define USBD_CFG_CSTALL_Msk (0x1ul << USBD_CFG_CSTALL_Pos) /*!< USBD_EP_T::CFG: CSTALL Mask */ + +#define USBD_CFGP_CLRRDY_Pos (0) /*!< USBD_EP_T::CFGP: CLRRDY Position */ +#define USBD_CFGP_CLRRDY_Msk (0x1ul << USBD_CFGP_CLRRDY_Pos) /*!< USBD_EP_T::CFGP: CLRRDY Mask */ + +#define USBD_CFGP_SSTALL_Pos (1) /*!< USBD_EP_T::CFGP: SSTALL Position */ +#define USBD_CFGP_SSTALL_Msk (0x1ul << USBD_CFGP_SSTALL_Pos) /*!< USBD_EP_T::CFGP: SSTALL Mask */ + +/**@}*/ /* USBD_CONST */ +/**@}*/ /* end of USBD register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __USBD_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/usbh_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/usbh_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..01dcffeaf70e9d081da13f4558a7c74b6c8e335c --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/usbh_reg.h @@ -0,0 +1,797 @@ +/**************************************************************************//** + * @file usbh_reg.h + * @version V1.00 + * @brief USBH register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __USBH_REG_H__ +#define __USBH_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup USBH USB Host Controller(USBH) + Memory Mapped Structure for USBH Controller +@{ */ + +typedef struct +{ + + /** + * @var USBH_T::HcRevision + * Offset: 0x00 Host Controller Revision Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |REV |Revision Number + * | | |Indicates the Open HCI Specification revision number implemented by the Hardware + * | | |Host Controller supports 1.1 specification. + * | | |(X.Y = XYh). + * @var USBH_T::HcControl + * Offset: 0x04 Host Controller Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CBSR |Control Bulk Service Ratio + * | | |This specifies the service ratio between Control and Bulk EDs + * | | |Before processing any of the non-periodic lists, HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been processed, in determining whether to continue serving another Control ED or switching to Bulk EDs + * | | |The internal count will be retained when crossing the frame boundary + * | | |In case of reset, HCD is responsible for restoring this + * | | |Value. + * | | |00 = Number of Control EDs over Bulk EDs served is 1:1. + * | | |01 = Number of Control EDs over Bulk EDs served is 2:1. + * | | |10 = Number of Control EDs over Bulk EDs served is 3:1. + * | | |11 = Number of Control EDs over Bulk EDs served is 4:1. + * |[2] |PLE |Periodic List Enable Bit + * | | |When set, this bit enables processing of the Periodic (interrupt and isochronous) list + * | | |The Host Controller checks this bit prior to attempting any periodic transfers in a frame. + * | | |0 = Processing of the Periodic (Interrupt and Isochronous) list after next SOF (Start-Of-Frame) Disabled. + * | | |1 = Processing of the Periodic (Interrupt and Isochronous) list in the next frame Enabled. + * | | |Note: To enable the processing of the Isochronous list, user has to set both PLE and IE (HcControl[3]) high. + * |[3] |IE |Isochronous List Enable Bit + * | | |Both ISOEn and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list + * | | |Either ISOEn or PLE (HcControl[2]) is low disables Host Controller to process the Isochronous list. + * | | |0 = Processing of the Isochronous list after next SOF (Start-Of-Frame) Disabled. + * | | |1 = Processing of the Isochronous list in the next frame Enabled, if the PLE (HcControl[2]) is high, too. + * |[4] |CLE |Control List Enable Bit + * | | |0 = Processing of the Control list after next SOF (Start-Of-Frame) Disabled. + * | | |1 = Processing of the Control list in the next frame Enabled. + * |[5] |BLE |Bulk List Enable Bit + * | | |0 = Processing of the Bulk list after next SOF (Start-Of-Frame) Disabled. + * | | |1 = Processing of the Bulk list in the next frame Enabled. + * |[7:6] |HCFS |Host Controller Functional State + * | | |This field sets the Host Controller state + * | | |The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port + * | | |States are: + * | | |00 = USBSUSPEND. + * | | |01 = USBOPERATIONAL. + * | | |10 = USBRESUME. + * | | |11 = USBRESET. + * @var USBH_T::HcCommandStatus + * Offset: 0x08 Host Controller Command Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |HCR |Host Controller Reset + * | | |This bit is set to initiate the software reset of Host Controller + * | | |This bit is cleared by the Host Controller, upon completed of the reset operation. + * | | |This bit, when set, didn't reset the Root Hub and no subsequent reset signaling be asserted to its downstream ports. + * | | |0 = Host Controller is not in software reset state. + * | | |1 = Host Controller is in software reset state. + * |[1] |CLF |Control List Filled + * | | |Set high to indicate there is an active TD on the Control List + * | | |It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List. + * | | |0 = No active TD found or Host Controller begins to process the head of the Control list. + * | | |1 = An active TD added or found on the Control list. + * |[2] |BLF |Bulk List Filled + * | | |Set high to indicate there is an active TD on the Bulk list + * | | |This bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk list. + * | | |0 = No active TD found or Host Controller begins to process the head of the Bulk list. + * | | |1 = An active TD added or found on the Bulk list. + * |[17:16] |SOC |Schedule Overrun Count + * | | |These bits are incremented on each scheduling overrun error + * | | |It is initialized to 00b and wraps around at 11b + * | | |This will be incremented when a scheduling overrun is detected even if SO (HcInterruptStatus[0]) has already been set. + * @var USBH_T::HcInterruptStatus + * Offset: 0x0C Host Controller Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SO |Scheduling Overrun + * | | |Set when the List Processor determines a Schedule Overrun has occurred. + * | | |0 = Schedule Overrun didn't occur. + * | | |1 = Schedule Overrun has occurred. + * |[1] |WDH |Write Back Done Head + * | | |Set after the Host Controller has written HcDoneHead to HccaDoneHead + * | | |Further updates of the HccaDoneHead will not occur until this bit has been cleared. + * | | |0 =.Host Controller didn't update HccaDoneHead. + * | | |1 =.Host Controller has written HcDoneHead to HccaDoneHead. + * |[2] |SF |Start of Frame + * | | |Set when the Frame Management functional block signals a 'Start of Frame' event + * | | |Host Control generates a SOF token at the same time. + * | | |0 =.Not the start of a frame. + * | | |1 =.Indicate the start of a frame and Host Controller generates a SOF token. + * |[3] |RD |Resume Detected + * | | |Set when Host Controller detects resume signaling on a downstream port. + * | | |0 = No resume signaling detected on a downstream port. + * | | |1 = Resume signaling detected on a downstream port. + * |[5] |FNO |Frame Number Overflow + * | | |This bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1. + * | | |0 = The bit 15 of Frame Number didn't change. + * | | |1 = The bit 15 of Frame Number changes from 1 to 0 or from 0 to 1. + * |[6] |RHSC |Root Hub Status Change + * | | |This bit is set when the content of HcRhStatus or the content of HcRhPortStatus register has changed. + * | | |0 = The content of HcRhStatus and the content of HcRhPortStatus register didn't change. + * | | |1 = The content of HcRhStatus or the content of HcRhPortStatus register has changed. + * @var USBH_T::HcInterruptEnable + * Offset: 0x10 Host Controller Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SO |Scheduling Overrun Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled. + * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled. + * |[1] |WDH |Write Back Done Head Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled. + * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled. + * |[2] |SF |Start of Frame Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled. + * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled. + * |[3] |RD |Resume Detected Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled. + * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled. + * |[5] |FNO |Frame Number Overflow Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled. + * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled. + * |[6] |RHSC |Root Hub Status Change Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled. + * |[31] |MIE |Master Interrupt Enable Bit + * | | |This bit is a global interrupt enable + * | | |A write of '1' allows interrupts to be enabled via the specific enable bits listed above. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high. + * @var USBH_T::HcInterruptDisable + * Offset: 0x14 Host Controller Interrupt Disable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SO |Scheduling Overrun Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled. + * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled. + * |[1] |WDH |Write Back Done Head Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled. + * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled. + * |[2] |SF |Start of Frame Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled. + * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled. + * |[3] |RD |Resume Detected Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled. + * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled. + * |[5] |FNO |Frame Number Overflow Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled. + * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled. + * |[6] |RHSC |Root Hub Status Change Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled. + * |[31] |MIE |Master Interrupt Disable Bit + * | | |Global interrupt disable. Writing '1' to disable all interrupts. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled if the corresponding bit in HcInterruptEnable is high. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high. + * @var USBH_T::HcHCCA + * Offset: 0x18 Host Controller Communication Area Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:8] |HCCA |Host Controller Communication Area + * | | |Pointer to indicate base address of the Host Controller Communication Area (HCCA). + * @var USBH_T::HcPeriodCurrentED + * Offset: 0x1C Host Controller Period Current ED Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |PCED |Periodic Current ED + * | | |Pointer to indicate physical address of the current Isochronous or Interrupt Endpoint Descriptor. + * @var USBH_T::HcControlHeadED + * Offset: 0x20 Host Controller Control Head ED Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |CHED |Control Head ED + * | | |Pointer to indicate physical address of the first Endpoint Descriptor of the Control list. + * @var USBH_T::HcControlCurrentED + * Offset: 0x24 Host Controller Control Current ED Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |CCED |Control Current Head ED + * | | |Pointer to indicate the physical address of the current Endpoint Descriptor of the Control list. + * @var USBH_T::HcBulkHeadED + * Offset: 0x28 Host Controller Bulk Head ED Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |BHED |Bulk Head ED + * | | |Pointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list. + * @var USBH_T::HcBulkCurrentED + * Offset: 0x2C Host Controller Bulk Current ED Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |BCED |Bulk Current Head ED + * | | |Pointer to indicate the physical address of the current endpoint of the Bulk list. + * @var USBH_T::HcDoneHead + * Offset: 0x30 Host Controller Done Head Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |DH |Done Head + * | | |Pointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue. + * @var USBH_T::HcFmInterval + * Offset: 0x34 Host Controller Frame Interval Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[13:0] |FI |Frame Interval + * | | |This field specifies the length of a frame as (bit times - 1) + * | | |For 12,000 bit times in a frame, a value of 11,999 is stored here. + * |[30:16] |FSMPS |FS Largest Data Packet + * | | |This field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame. + * |[31] |FIT |Frame Interval Toggle + * | | |This bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmInterval[13:0]). + * | | |0 = Host Controller Driver didn't load new value into FI (HcFmInterval[13:0]). + * | | |1 = Host Controller Driver loads a new value into FI (HcFmInterval[13:0]). + * @var USBH_T::HcFmRemaining + * Offset: 0x38 Host Controller Frame Remaining Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[13:0] |FR |Frame Remaining + * | | |When the Host Controller is in the USBOPERATIONAL state, this 14-bit field decrements each 12 MHz clock period + * | | |When the count reaches 0, (end of frame) the counter reloads with Frame Interval + * | | |In addition, the counter loads when the Host Controller transitions into USBOPERATIONAL. + * |[31] |FRT |Frame Remaining Toggle + * | | |This bit is loaded from the FIT (HcFmInterval[31]) whenever FR (HcFmRemaining[13:0]) reaches 0. + * @var USBH_T::HcFmNumber + * Offset: 0x3C Host Controller Frame Number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FN |Frame Number + * | | |This 16-bit incrementing counter field is incremented coincident with the re-load of FR (HcFmRemaining[13:0]) + * | | |The count rolls over from 'FFFFh' to '0h.' + * @var USBH_T::HcPeriodicStart + * Offset: 0x40 Host Controller Periodic Start Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[13:0] |PS |Periodic Start + * | | |This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin. + * @var USBH_T::HcLSThreshold + * Offset: 0x44 Host Controller Low-speed Threshold Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |LST |Low-speed Threshold + * | | |This field contains a value which is compared to the FR (HcFmRemaining[13:0]) field prior to initiating a Low-speed transaction + * | | |The transaction is started only if FR (HcFmRemaining[13:0]) >= this field + * | | |The value is calculated by Host Controller Driver with the consideration of transmission and setup overhead. + * @var USBH_T::HcRhDescriptorA + * Offset: 0x48 Host Controller Root Hub Descriptor A Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |NDP |Number Downstream Ports + * | | |USB host control supports two downstream ports and only one port is available in this series of chip. + * |[8] |PSM |Power Switching Mode + * | | |This bit is used to specify how the power switching of the Root Hub ports is controlled. + * | | |0 = Global Switching. + * | | |1 = Individual Switching. + * |[11] |OCPM |over Current Protection Mode + * | | |This bit describes how the over current status for the Root Hub ports reported + * | | |This bit is only valid when NOCP (HcRhDescriptorA[12]) is cleared. + * | | |0 = Global Over current. + * | | |1 = Individual Over current. + * |[12] |NOCP |No over Current Protection + * | | |This bit describes how the over current status for the Root Hub ports reported. + * | | |0 = Over current status is reported. + * | | |1 = Over current status is not reported. + * @var USBH_T::HcRhDescriptorB + * Offset: 0x4C Host Controller Root Hub Descriptor B Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:16] |PPCM |Port Power Control Mask + * | | |Global power switching + * | | |This field is only valid if PowerSwitchingMode is set (individual port switching) + * | | |When set, the port only responds to individual port power switching commands (Set/ClearPortPower) + * | | |When cleared, the port only responds to global power switching commands (Set/ClearGlobalPower). + * | | |0 = Port power controlled by global power switching. + * | | |1 = Port power controlled by port power switching. + * | | |Note: PPCM[15:2] and PPCM[0] are reserved. + * @var USBH_T::HcRhStatus + * Offset: 0x50 Host Controller Root Hub Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LPS |Clear Global Power + * | | |In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to clear all ports' power. + * | | |This bit always read as zero. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Clear global power. + * |[1] |OCI |over Current Indicator + * | | |This bit reflects the state of the over current status pin + * | | |This field is only valid if NOCP (HcRhDesA[12]) and OCPM (HcRhDesA[11]) are cleared. + * | | |0 = No over current condition. + * | | |1 = Over current condition. + * |[15] |DRWE |Device Remote Wakeup Enable Bit + * | | |This bit controls if port's Connect Status Change as a remote wake-up event. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Connect Status Change as a remote wake-up event Enabled. + * | | |Read Operation: + * | | |0 = Connect Status Change as a remote wake-up event Disabled. + * | | |1 = Connect Status Change as a remote wake-up event Enabled. + * |[16] |LPSC |Set Global Power + * | | |In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to enable power to all ports. + * | | |This bit always read as zero. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set global power. + * |[17] |OCIC |over Current Indicator Change + * | | |This bit is set by hardware when a change has occurred in OCI (HcRhStatus[1]). + * | | |Write 1 to clear this bit to zero. + * | | |0 = OCI (HcRhStatus[1]) didn't change. + * | | |1 = OCI (HcRhStatus[1]) change. + * |[31] |CRWE |Clear Remote Wake-up Enable Bit + * | | |This bit is use to clear DRWE (HcRhStatus[15]). + * | | |This bit always read as zero. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Clear DRWE (HcRhStatus[15]). + * @var USBH_T::HcRhPortStatus[2] + * Offset: 0x54 Host Controller Root Hub Port Status + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CCS |CurrentConnectStatus (Read) or ClearPortEnable Bit (Write) + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Clear port enable. + * | | |Read Operation: + * | | |0 = No device connected. + * | | |1 = Device connected. + * |[1] |PES |Port Enable Status + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set port enable. + * | | |Read Operation: + * | | |0 = Port Disabled. + * | | |1 = Port Enabled. + * |[2] |PSS |Port Suspend Status + * | | |This bit indicates the port is suspended + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set port suspend. + * | | |Read Operation: + * | | |0 = Port is not suspended. + * | | |1 = Port is selectively suspended. + * |[3] |POCI |Port over Current Indicator (Read) or Clear Port Suspend (Write) + * | | |This bit reflects the state of the over current status pin dedicated to this port + * | | |This field is only valid if NOCP (HcRhDescriptorA[12]) is cleared and OCPM (HcRhDescriptorA[11]) is set. + * | | |This bit is also used to initiate the selective result sequence for the port. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Clear port suspend. + * | | |Read Operation: + * | | |0 = No over current condition. + * | | |1 = Over current condition. + * |[4] |PRS |Port Reset Status + * | | |This bit reflects the reset state of the port. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set port reset. + * | | |Read Operation + * | | |0 = Port reset signal is not active. + * | | |1 = Port reset signal is active. + * |[8] |PPS |Port Power Status + * | | |This bit reflects the power state of the port regardless of the power switching mode. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Port Power Enabled. + * | | |Read Operation: + * | | |0 = Port power is Disabled. + * | | |1 = Port power is Enabled. + * |[9] |LSDA |Low Speed Device Attached (Read) or Clear Port Power (Write) + * | | |This bit defines the speed (and bud idle) of the attached device + * | | |It is only valid when CCS (HcRhPortStatus1[0]) is set. + * | | |This bit is also used to clear port power. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Clear PPS (HcRhPortStatus1[8]). + * | | |Read Operation: + * | | |0 = Full Speed device. + * | | |1 = Low-speed device. + * |[16] |CSC |Connect Status Change + * | | |This bit indicates connect or disconnect event has been detected (CCS (HcRhPortStatus1[0]) changed). + * | | |Write 1 to clear this bit to zero. + * | | |0 = No connect/disconnect event (CCS (HcRhPortStatus1[0]) didn't change). + * | | |1 = Hardware detection of connect/disconnect event (CCS (HcRhPortStatus1[0]) changed). + * |[17] |PESC |Port Enable Status Change + * | | |This bit indicates that the port has been disabled (PES (HcRhPortStatus1[1]) cleared) due to a hardware event. + * | | |Write 1 to clear this bit to zero. + * | | |0 = PES (HcRhPortStatus1[1]) didn't change. + * | | |1 = PES (HcRhPortStatus1[1]) changed. + * |[18] |PSSC |Port Suspend Status Change + * | | |This bit indicates the completion of the selective resume sequence for the port. + * | | |Write 1 to clear this bit to zero. + * | | |0 = Port resume is not completed. + * | | |1 = Port resume completed. + * |[19] |OCIC |Port over Current Indicator Change + * | | |This bit is set when POCI (HcRhPortStatus1[3]) changes. + * | | |Write 1 to clear this bit to zero. + * | | |0 = POCI (HcRhPortStatus1[3]) didn't change. + * | | |1 = POCI (HcRhPortStatus1[3]) changes. + * |[20] |PRSC |Port Reset Status Change + * | | |This bit indicates that the port reset signal has completed. + * | | |Write 1 to clear this bit to zero. + * | | |0 = Port reset is not complete. + * | | |1 = Port reset is complete. + * @var USBH_T::HcPhyControl + * Offset: 0x200 Host Controller PHY Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[27] |STBYEN |USB Transceiver Standby Enable Bit + * | | |This bit controls if USB transceiver could enter the standby mode to reduce power consumption. + * | | |0 = The USB transceiver would never enter the standby mode. + * | | |1 = The USB transceiver will enter standby mode while port is in power off state (port power is inactive). + * @var USBH_T::HcMiscControl + * Offset: 0x204 Host Controller Miscellaneous Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |ABORT |AHB Bus ERROR Response + * | | |This bit indicates there is an ERROR response received in AHB bus. + * | | |0 = No ERROR response received. + * | | |1 = ERROR response received. + * |[3] |OCAL |over Current Active Low + * | | |This bit controls the polarity of over current flag from external power IC. + * | | |0 = Over current flag is high active. + * | | |1 = Over current flag is low active. + * |[16] |DPRT1 |Disable Port 1 + * | | |This bit controls if the connection between USB host controller and transceiver of port 1 is disabled + * | | |If the connection is disabled, the USB host controller will not recognize any event of USB bus. + * | | |Set this bit high, the transceiver of port 1 will also be forced into the standby mode no matter what USB host controller operation is. + * | | |0 = The connection between USB host controller and transceiver of port 1 Enabled. + * | | |1 = The connection between USB host controller and transceiver of port 1 Disabled and the transceiver of port 1 will also be forced into the standby mode. + */ + __I uint32_t HcRevision; /*!< [0x0000] Host Controller Revision Register */ + __IO uint32_t HcControl; /*!< [0x0004] Host Controller Control Register */ + __IO uint32_t HcCommandStatus; /*!< [0x0008] Host Controller Command Status Register */ + __IO uint32_t HcInterruptStatus; /*!< [0x000c] Host Controller Interrupt Status Register */ + __IO uint32_t HcInterruptEnable; /*!< [0x0010] Host Controller Interrupt Enable Register */ + __IO uint32_t HcInterruptDisable; /*!< [0x0014] Host Controller Interrupt Disable Register */ + __IO uint32_t HcHCCA; /*!< [0x0018] Host Controller Communication Area Register */ + __IO uint32_t HcPeriodCurrentED; /*!< [0x001c] Host Controller Period Current ED Register */ + __IO uint32_t HcControlHeadED; /*!< [0x0020] Host Controller Control Head ED Register */ + __IO uint32_t HcControlCurrentED; /*!< [0x0024] Host Controller Control Current ED Register */ + __IO uint32_t HcBulkHeadED; /*!< [0x0028] Host Controller Bulk Head ED Register */ + __IO uint32_t HcBulkCurrentED; /*!< [0x002c] Host Controller Bulk Current ED Register */ + __IO uint32_t HcDoneHead; /*!< [0x0030] Host Controller Done Head Register */ + __IO uint32_t HcFmInterval; /*!< [0x0034] Host Controller Frame Interval Register */ + __I uint32_t HcFmRemaining; /*!< [0x0038] Host Controller Frame Remaining Register */ + __I uint32_t HcFmNumber; /*!< [0x003c] Host Controller Frame Number Register */ + __IO uint32_t HcPeriodicStart; /*!< [0x0040] Host Controller Periodic Start Register */ + __IO uint32_t HcLSThreshold; /*!< [0x0044] Host Controller Low-speed Threshold Register */ + __IO uint32_t HcRhDescriptorA; /*!< [0x0048] Host Controller Root Hub Descriptor A Register */ + __IO uint32_t HcRhDescriptorB; /*!< [0x004c] Host Controller Root Hub Descriptor B Register */ + __IO uint32_t HcRhStatus; /*!< [0x0050] Host Controller Root Hub Status Register */ + __IO uint32_t HcRhPortStatus[2]; /*!< [0x0054] Host Controller Root Hub Port Status [1] */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[105]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t HcPhyControl; /*!< [0x0200] Host Controller PHY Control Register */ + __IO uint32_t HcMiscControl; /*!< [0x0204] Host Controller Miscellaneous Control Register */ + +} USBH_T; + +/** + @addtogroup USBH_CONST USBH Bit Field Definition + Constant Definitions for USBH Controller +@{ */ + +#define USBH_HcRevision_REV_Pos (0) /*!< USBH_T::HcRevision: REV Position */ +#define USBH_HcRevision_REV_Msk (0xfful << USBH_HcRevision_REV_Pos) /*!< USBH_T::HcRevision: REV Mask */ + +#define USBH_HcControl_CBSR_Pos (0) /*!< USBH_T::HcControl: CBSR Position */ +#define USBH_HcControl_CBSR_Msk (0x3ul << USBH_HcControl_CBSR_Pos) /*!< USBH_T::HcControl: CBSR Mask */ + +#define USBH_HcControl_PLE_Pos (2) /*!< USBH_T::HcControl: PLE Position */ +#define USBH_HcControl_PLE_Msk (0x1ul << USBH_HcControl_PLE_Pos) /*!< USBH_T::HcControl: PLE Mask */ + +#define USBH_HcControl_IE_Pos (3) /*!< USBH_T::HcControl: IE Position */ +#define USBH_HcControl_IE_Msk (0x1ul << USBH_HcControl_IE_Pos) /*!< USBH_T::HcControl: IE Mask */ + +#define USBH_HcControl_CLE_Pos (4) /*!< USBH_T::HcControl: CLE Position */ +#define USBH_HcControl_CLE_Msk (0x1ul << USBH_HcControl_CLE_Pos) /*!< USBH_T::HcControl: CLE Mask */ + +#define USBH_HcControl_BLE_Pos (5) /*!< USBH_T::HcControl: BLE Position */ +#define USBH_HcControl_BLE_Msk (0x1ul << USBH_HcControl_BLE_Pos) /*!< USBH_T::HcControl: BLE Mask */ + +#define USBH_HcControl_HCFS_Pos (6) /*!< USBH_T::HcControl: HCFS Position */ +#define USBH_HcControl_HCFS_Msk (0x3ul << USBH_HcControl_HCFS_Pos) /*!< USBH_T::HcControl: HCFS Mask */ + +#define USBH_HcCommandStatus_HCR_Pos (0) /*!< USBH_T::HcCommandStatus: HCR Position */ +#define USBH_HcCommandStatus_HCR_Msk (0x1ul << USBH_HcCommandStatus_HCR_Pos) /*!< USBH_T::HcCommandStatus: HCR Mask */ + +#define USBH_HcCommandStatus_CLF_Pos (1) /*!< USBH_T::HcCommandStatus: CLF Position */ +#define USBH_HcCommandStatus_CLF_Msk (0x1ul << USBH_HcCommandStatus_CLF_Pos) /*!< USBH_T::HcCommandStatus: CLF Mask */ + +#define USBH_HcCommandStatus_BLF_Pos (2) /*!< USBH_T::HcCommandStatus: BLF Position */ +#define USBH_HcCommandStatus_BLF_Msk (0x1ul << USBH_HcCommandStatus_BLF_Pos) /*!< USBH_T::HcCommandStatus: BLF Mask */ + +#define USBH_HcCommandStatus_SOC_Pos (16) /*!< USBH_T::HcCommandStatus: SOC Position */ +#define USBH_HcCommandStatus_SOC_Msk (0x3ul << USBH_HcCommandStatus_SOC_Pos) /*!< USBH_T::HcCommandStatus: SOC Mask */ + +#define USBH_HcInterruptStatus_SO_Pos (0) /*!< USBH_T::HcInterruptStatus: SO Position */ +#define USBH_HcInterruptStatus_SO_Msk (0x1ul << USBH_HcInterruptStatus_SO_Pos) /*!< USBH_T::HcInterruptStatus: SO Mask */ + +#define USBH_HcInterruptStatus_WDH_Pos (1) /*!< USBH_T::HcInterruptStatus: WDH Position*/ +#define USBH_HcInterruptStatus_WDH_Msk (0x1ul << USBH_HcInterruptStatus_WDH_Pos) /*!< USBH_T::HcInterruptStatus: WDH Mask */ + +#define USBH_HcInterruptStatus_SF_Pos (2) /*!< USBH_T::HcInterruptStatus: SF Position */ +#define USBH_HcInterruptStatus_SF_Msk (0x1ul << USBH_HcInterruptStatus_SF_Pos) /*!< USBH_T::HcInterruptStatus: SF Mask */ + +#define USBH_HcInterruptStatus_RD_Pos (3) /*!< USBH_T::HcInterruptStatus: RD Position */ +#define USBH_HcInterruptStatus_RD_Msk (0x1ul << USBH_HcInterruptStatus_RD_Pos) /*!< USBH_T::HcInterruptStatus: RD Mask */ + +#define USBH_HcInterruptStatus_FNO_Pos (5) /*!< USBH_T::HcInterruptStatus: FNO Position*/ +#define USBH_HcInterruptStatus_FNO_Msk (0x1ul << USBH_HcInterruptStatus_FNO_Pos) /*!< USBH_T::HcInterruptStatus: FNO Mask */ + +#define USBH_HcInterruptStatus_RHSC_Pos (6) /*!< USBH_T::HcInterruptStatus: RHSC Position*/ +#define USBH_HcInterruptStatus_RHSC_Msk (0x1ul << USBH_HcInterruptStatus_RHSC_Pos) /*!< USBH_T::HcInterruptStatus: RHSC Mask */ + +#define USBH_HcInterruptEnable_SO_Pos (0) /*!< USBH_T::HcInterruptEnable: SO Position */ +#define USBH_HcInterruptEnable_SO_Msk (0x1ul << USBH_HcInterruptEnable_SO_Pos) /*!< USBH_T::HcInterruptEnable: SO Mask */ + +#define USBH_HcInterruptEnable_WDH_Pos (1) /*!< USBH_T::HcInterruptEnable: WDH Position*/ +#define USBH_HcInterruptEnable_WDH_Msk (0x1ul << USBH_HcInterruptEnable_WDH_Pos) /*!< USBH_T::HcInterruptEnable: WDH Mask */ + +#define USBH_HcInterruptEnable_SF_Pos (2) /*!< USBH_T::HcInterruptEnable: SF Position */ +#define USBH_HcInterruptEnable_SF_Msk (0x1ul << USBH_HcInterruptEnable_SF_Pos) /*!< USBH_T::HcInterruptEnable: SF Mask */ + +#define USBH_HcInterruptEnable_RD_Pos (3) /*!< USBH_T::HcInterruptEnable: RD Position */ +#define USBH_HcInterruptEnable_RD_Msk (0x1ul << USBH_HcInterruptEnable_RD_Pos) /*!< USBH_T::HcInterruptEnable: RD Mask */ + +#define USBH_HcInterruptEnable_FNO_Pos (5) /*!< USBH_T::HcInterruptEnable: FNO Position*/ +#define USBH_HcInterruptEnable_FNO_Msk (0x1ul << USBH_HcInterruptEnable_FNO_Pos) /*!< USBH_T::HcInterruptEnable: FNO Mask */ + +#define USBH_HcInterruptEnable_RHSC_Pos (6) /*!< USBH_T::HcInterruptEnable: RHSC Position*/ +#define USBH_HcInterruptEnable_RHSC_Msk (0x1ul << USBH_HcInterruptEnable_RHSC_Pos) /*!< USBH_T::HcInterruptEnable: RHSC Mask */ + +#define USBH_HcInterruptEnable_MIE_Pos (31) /*!< USBH_T::HcInterruptEnable: MIE Position*/ +#define USBH_HcInterruptEnable_MIE_Msk (0x1ul << USBH_HcInterruptEnable_MIE_Pos) /*!< USBH_T::HcInterruptEnable: MIE Mask */ + +#define USBH_HcInterruptDisable_SO_Pos (0) /*!< USBH_T::HcInterruptDisable: SO Position*/ +#define USBH_HcInterruptDisable_SO_Msk (0x1ul << USBH_HcInterruptDisable_SO_Pos) /*!< USBH_T::HcInterruptDisable: SO Mask */ + +#define USBH_HcInterruptDisable_WDH_Pos (1) /*!< USBH_T::HcInterruptDisable: WDH Position*/ +#define USBH_HcInterruptDisable_WDH_Msk (0x1ul << USBH_HcInterruptDisable_WDH_Pos) /*!< USBH_T::HcInterruptDisable: WDH Mask */ + +#define USBH_HcInterruptDisable_SF_Pos (2) /*!< USBH_T::HcInterruptDisable: SF Position*/ +#define USBH_HcInterruptDisable_SF_Msk (0x1ul << USBH_HcInterruptDisable_SF_Pos) /*!< USBH_T::HcInterruptDisable: SF Mask */ + +#define USBH_HcInterruptDisable_RD_Pos (3) /*!< USBH_T::HcInterruptDisable: RD Position*/ +#define USBH_HcInterruptDisable_RD_Msk (0x1ul << USBH_HcInterruptDisable_RD_Pos) /*!< USBH_T::HcInterruptDisable: RD Mask */ + +#define USBH_HcInterruptDisable_FNO_Pos (5) /*!< USBH_T::HcInterruptDisable: FNO Position*/ +#define USBH_HcInterruptDisable_FNO_Msk (0x1ul << USBH_HcInterruptDisable_FNO_Pos) /*!< USBH_T::HcInterruptDisable: FNO Mask */ + +#define USBH_HcInterruptDisable_RHSC_Pos (6) /*!< USBH_T::HcInterruptDisable: RHSC Position*/ +#define USBH_HcInterruptDisable_RHSC_Msk (0x1ul << USBH_HcInterruptDisable_RHSC_Pos) /*!< USBH_T::HcInterruptDisable: RHSC Mask */ + +#define USBH_HcInterruptDisable_MIE_Pos (31) /*!< USBH_T::HcInterruptDisable: MIE Position*/ +#define USBH_HcInterruptDisable_MIE_Msk (0x1ul << USBH_HcInterruptDisable_MIE_Pos) /*!< USBH_T::HcInterruptDisable: MIE Mask */ + +#define USBH_HcHCCA_HCCA_Pos (8) /*!< USBH_T::HcHCCA: HCCA Position */ +#define USBH_HcHCCA_HCCA_Msk (0xfffffful << USBH_HcHCCA_HCCA_Pos) /*!< USBH_T::HcHCCA: HCCA Mask */ + +#define USBH_HcPeriodCurrentED_PCED_Pos (4) /*!< USBH_T::HcPeriodCurrentED: PCED Position*/ +#define USBH_HcPeriodCurrentED_PCED_Msk (0xffffffful << USBH_HcPeriodCurrentED_PCED_Pos) /*!< USBH_T::HcPeriodCurrentED: PCED Mask */ + +#define USBH_HcControlHeadED_CHED_Pos (4) /*!< USBH_T::HcControlHeadED: CHED Position */ +#define USBH_HcControlHeadED_CHED_Msk (0xffffffful << USBH_HcControlHeadED_CHED_Pos) /*!< USBH_T::HcControlHeadED: CHED Mask */ + +#define USBH_HcControlCurrentED_CCED_Pos (4) /*!< USBH_T::HcControlCurrentED: CCED Position*/ +#define USBH_HcControlCurrentED_CCED_Msk (0xffffffful << USBH_HcControlCurrentED_CCED_Pos) /*!< USBH_T::HcControlCurrentED: CCED Mask */ + +#define USBH_HcBulkHeadED_BHED_Pos (4) /*!< USBH_T::HcBulkHeadED: BHED Position */ +#define USBH_HcBulkHeadED_BHED_Msk (0xffffffful << USBH_HcBulkHeadED_BHED_Pos) /*!< USBH_T::HcBulkHeadED: BHED Mask */ + +#define USBH_HcBulkCurrentED_BCED_Pos (4) /*!< USBH_T::HcBulkCurrentED: BCED Position */ +#define USBH_HcBulkCurrentED_BCED_Msk (0xffffffful << USBH_HcBulkCurrentED_BCED_Pos) /*!< USBH_T::HcBulkCurrentED: BCED Mask */ + +#define USBH_HcDoneHead_DH_Pos (4) /*!< USBH_T::HcDoneHead: DH Position */ +#define USBH_HcDoneHead_DH_Msk (0xffffffful << USBH_HcDoneHead_DH_Pos) /*!< USBH_T::HcDoneHead: DH Mask */ + +#define USBH_HcFmInterval_FI_Pos (0) /*!< USBH_T::HcFmInterval: FI Position */ +#define USBH_HcFmInterval_FI_Msk (0x3ffful << USBH_HcFmInterval_FI_Pos) /*!< USBH_T::HcFmInterval: FI Mask */ + +#define USBH_HcFmInterval_FSMPS_Pos (16) /*!< USBH_T::HcFmInterval: FSMPS Position */ +#define USBH_HcFmInterval_FSMPS_Msk (0x7ffful << USBH_HcFmInterval_FSMPS_Pos) /*!< USBH_T::HcFmInterval: FSMPS Mask */ + +#define USBH_HcFmInterval_FIT_Pos (31) /*!< USBH_T::HcFmInterval: FIT Position */ +#define USBH_HcFmInterval_FIT_Msk (0x1ul << USBH_HcFmInterval_FIT_Pos) /*!< USBH_T::HcFmInterval: FIT Mask */ + +#define USBH_HcFmRemaining_FR_Pos (0) /*!< USBH_T::HcFmRemaining: FR Position */ +#define USBH_HcFmRemaining_FR_Msk (0x3ffful << USBH_HcFmRemaining_FR_Pos) /*!< USBH_T::HcFmRemaining: FR Mask */ + +#define USBH_HcFmRemaining_FRT_Pos (31) /*!< USBH_T::HcFmRemaining: FRT Position */ +#define USBH_HcFmRemaining_FRT_Msk (0x1ul << USBH_HcFmRemaining_FRT_Pos) /*!< USBH_T::HcFmRemaining: FRT Mask */ + +#define USBH_HcFmNumber_FN_Pos (0) /*!< USBH_T::HcFmNumber: FN Position */ +#define USBH_HcFmNumber_FN_Msk (0xfffful << USBH_HcFmNumber_FN_Pos) /*!< USBH_T::HcFmNumber: FN Mask */ + +#define USBH_HcPeriodicStart_PS_Pos (0) /*!< USBH_T::HcPeriodicStart: PS Position */ +#define USBH_HcPeriodicStart_PS_Msk (0x3ffful << USBH_HcPeriodicStart_PS_Pos) /*!< USBH_T::HcPeriodicStart: PS Mask */ + +#define USBH_HcLSThreshold_LST_Pos (0) /*!< USBH_T::HcLSThreshold: LST Position */ +#define USBH_HcLSThreshold_LST_Msk (0xffful << USBH_HcLSThreshold_LST_Pos) /*!< USBH_T::HcLSThreshold: LST Mask */ + +#define USBH_HcRhDescriptorA_NDP_Pos (0) /*!< USBH_T::HcRhDescriptorA: NDP Position */ +#define USBH_HcRhDescriptorA_NDP_Msk (0xfful << USBH_HcRhDescriptorA_NDP_Pos) /*!< USBH_T::HcRhDescriptorA: NDP Mask */ + +#define USBH_HcRhDescriptorA_PSM_Pos (8) /*!< USBH_T::HcRhDescriptorA: PSM Position */ +#define USBH_HcRhDescriptorA_PSM_Msk (0x1ul << USBH_HcRhDescriptorA_PSM_Pos) /*!< USBH_T::HcRhDescriptorA: PSM Mask */ + +#define USBH_HcRhDescriptorA_OCPM_Pos (11) /*!< USBH_T::HcRhDescriptorA: OCPM Position */ +#define USBH_HcRhDescriptorA_OCPM_Msk (0x1ul << USBH_HcRhDescriptorA_OCPM_Pos) /*!< USBH_T::HcRhDescriptorA: OCPM Mask */ + +#define USBH_HcRhDescriptorA_NOCP_Pos (12) /*!< USBH_T::HcRhDescriptorA: NOCP Position */ +#define USBH_HcRhDescriptorA_NOCP_Msk (0x1ul << USBH_HcRhDescriptorA_NOCP_Pos) /*!< USBH_T::HcRhDescriptorA: NOCP Mask */ + +#define USBH_HcRhDescriptorB_PPCM_Pos (16) /*!< USBH_T::HcRhDescriptorB: PPCM Position */ +#define USBH_HcRhDescriptorB_PPCM_Msk (0xfffful << USBH_HcRhDescriptorB_PPCM_Pos) /*!< USBH_T::HcRhDescriptorB: PPCM Mask */ + +#define USBH_HcRhStatus_LPS_Pos (0) /*!< USBH_T::HcRhStatus: LPS Position */ +#define USBH_HcRhStatus_LPS_Msk (0x1ul << USBH_HcRhStatus_LPS_Pos) /*!< USBH_T::HcRhStatus: LPS Mask */ + +#define USBH_HcRhStatus_OCI_Pos (1) /*!< USBH_T::HcRhStatus: OCI Position */ +#define USBH_HcRhStatus_OCI_Msk (0x1ul << USBH_HcRhStatus_OCI_Pos) /*!< USBH_T::HcRhStatus: OCI Mask */ + +#define USBH_HcRhStatus_DRWE_Pos (15) /*!< USBH_T::HcRhStatus: DRWE Position */ +#define USBH_HcRhStatus_DRWE_Msk (0x1ul << USBH_HcRhStatus_DRWE_Pos) /*!< USBH_T::HcRhStatus: DRWE Mask */ + +#define USBH_HcRhStatus_LPSC_Pos (16) /*!< USBH_T::HcRhStatus: LPSC Position */ +#define USBH_HcRhStatus_LPSC_Msk (0x1ul << USBH_HcRhStatus_LPSC_Pos) /*!< USBH_T::HcRhStatus: LPSC Mask */ + +#define USBH_HcRhStatus_OCIC_Pos (17) /*!< USBH_T::HcRhStatus: OCIC Position */ +#define USBH_HcRhStatus_OCIC_Msk (0x1ul << USBH_HcRhStatus_OCIC_Pos) /*!< USBH_T::HcRhStatus: OCIC Mask */ + +#define USBH_HcRhStatus_CRWE_Pos (31) /*!< USBH_T::HcRhStatus: CRWE Position */ +#define USBH_HcRhStatus_CRWE_Msk (0x1ul << USBH_HcRhStatus_CRWE_Pos) /*!< USBH_T::HcRhStatus: CRWE Mask */ + +#define USBH_HcRhPortStatus_CCS_Pos (0) /*!< USBH_T::HcRhPortStatus1: CCS Position */ +#define USBH_HcRhPortStatus_CCS_Msk (0x1ul << USBH_HcRhPortStatus_CCS_Pos) /*!< USBH_T::HcRhPortStatus1: CCS Mask */ + +#define USBH_HcRhPortStatus_PES_Pos (1) /*!< USBH_T::HcRhPortStatus1: PES Position */ +#define USBH_HcRhPortStatus_PES_Msk (0x1ul << USBH_HcRhPortStatus_PES_Pos) /*!< USBH_T::HcRhPortStatus1: PES Mask */ + +#define USBH_HcRhPortStatus_PSS_Pos (2) /*!< USBH_T::HcRhPortStatus1: PSS Position */ +#define USBH_HcRhPortStatus_PSS_Msk (0x1ul << USBH_HcRhPortStatus_PSS_Pos) /*!< USBH_T::HcRhPortStatus1: PSS Mask */ + +#define USBH_HcRhPortStatus_POCI_Pos (3) /*!< USBH_T::HcRhPortStatus1: POCI Position */ +#define USBH_HcRhPortStatus_POCI_Msk (0x1ul << USBH_HcRhPortStatus_POCI_Pos) /*!< USBH_T::HcRhPortStatus1: POCI Mask */ + +#define USBH_HcRhPortStatus_PRS_Pos (4) /*!< USBH_T::HcRhPortStatus1: PRS Position */ +#define USBH_HcRhPortStatus_PRS_Msk (0x1ul << USBH_HcRhPortStatus_PRS_Pos) /*!< USBH_T::HcRhPortStatus1: PRS Mask */ + +#define USBH_HcRhPortStatus_PPS_Pos (8) /*!< USBH_T::HcRhPortStatus1: PPS Position */ +#define USBH_HcRhPortStatus_PPS_Msk (0x1ul << USBH_HcRhPortStatus_PPS_Pos) /*!< USBH_T::HcRhPortStatus1: PPS Mask */ + +#define USBH_HcRhPortStatus_LSDA_Pos (9) /*!< USBH_T::HcRhPortStatus1: LSDA Position */ +#define USBH_HcRhPortStatus_LSDA_Msk (0x1ul << USBH_HcRhPortStatus_LSDA_Pos) /*!< USBH_T::HcRhPortStatus1: LSDA Mask */ + +#define USBH_HcRhPortStatus_CSC_Pos (16) /*!< USBH_T::HcRhPortStatus1: CSC Position */ +#define USBH_HcRhPortStatus_CSC_Msk (0x1ul << USBH_HcRhPortStatus_CSC_Pos) /*!< USBH_T::HcRhPortStatus1: CSC Mask */ + +#define USBH_HcRhPortStatus_PESC_Pos (17) /*!< USBH_T::HcRhPortStatus1: PESC Position */ +#define USBH_HcRhPortStatus_PESC_Msk (0x1ul << USBH_HcRhPortStatus_PESC_Pos) /*!< USBH_T::HcRhPortStatus1: PESC Mask */ + +#define USBH_HcRhPortStatus_PSSC_Pos (18) /*!< USBH_T::HcRhPortStatus1: PSSC Position */ +#define USBH_HcRhPortStatus_PSSC_Msk (0x1ul << USBH_HcRhPortStatus_PSSC_Pos) /*!< USBH_T::HcRhPortStatus1: PSSC Mask */ + +#define USBH_HcRhPortStatus_OCIC_Pos (19) /*!< USBH_T::HcRhPortStatus1: OCIC Position */ +#define USBH_HcRhPortStatus_OCIC_Msk (0x1ul << USBH_HcRhPortStatus_OCIC_Pos) /*!< USBH_T::HcRhPortStatus1: OCIC Mask */ + +#define USBH_HcRhPortStatus_PRSC_Pos (20) /*!< USBH_T::HcRhPortStatus1: PRSC Position */ +#define USBH_HcRhPortStatus_PRSC_Msk (0x1ul << USBH_HcRhPortStatus_PRSC_Pos) /*!< USBH_T::HcRhPortStatus1: PRSC Mask */ + +#define USBH_HcPhyControl_STBYEN_Pos (27) /*!< USBH_T::HcPhyControl: STBYEN Position */ +#define USBH_HcPhyControl_STBYEN_Msk (0x1ul << USBH_HcPhyControl_STBYEN_Pos) /*!< USBH_T::HcPhyControl: STBYEN Mask */ + +#define USBH_HcMiscControl_ABORT_Pos (1) /*!< USBH_T::HcMiscControl: ABORT Position */ +#define USBH_HcMiscControl_ABORT_Msk (0x1ul << USBH_HcMiscControl_ABORT_Pos) /*!< USBH_T::HcMiscControl: ABORT Mask */ + +#define USBH_HcMiscControl_OCAL_Pos (3) /*!< USBH_T::HcMiscControl: OCAL Position */ +#define USBH_HcMiscControl_OCAL_Msk (0x1ul << USBH_HcMiscControl_OCAL_Pos) /*!< USBH_T::HcMiscControl: OCAL Mask */ + +#define USBH_HcMiscControl_DPRT1_Pos (16) /*!< USBH_T::HcMiscControl: DPRT1 Position */ +#define USBH_HcMiscControl_DPRT1_Msk (0x1ul << USBH_HcMiscControl_DPRT1_Pos) /*!< USBH_T::HcMiscControl: DPRT1 Mask */ + +/**@}*/ /* USBH_CONST */ +/**@}*/ /* end of USBH register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __USBH_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/uspi_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/uspi_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..d9a2d3077a37023e25cf36aa7269e8a451e83875 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/uspi_reg.h @@ -0,0 +1,677 @@ +/**************************************************************************//** + * @file uspi_reg.h + * @version V1.00 + * @brief USPI register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __USPI_REG_H__ +#define __USPI_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup USPI SPI Mode of USCI Controller(USPI) + Memory Mapped Structure for USPI Controller +@{ */ + +typedef struct +{ + + + /** + * @var USPI_T::CTL + * Offset: 0x00 USCI Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |FUNMODE |Function Mode + * | | |This bit field selects the protocol for this USCI controller + * | | |Selecting a protocol that is not available or a reserved combination disables the USCI + * | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol + * | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE. + * | | |000 = The USCI is disabled. All protocol related state machines are set to idle state. + * | | |001 = The SPI protocol is selected. + * | | |010 = The UART protocol is selected. + * | | |100 = The I2C protocol is selected. + * | | |Note: Other bit combinations are reserved. + * @var USPI_T::INTEN + * Offset: 0x04 USCI Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TXSTIEN |Transmit Start Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a transmit start event. + * | | |0 = The transmit start interrupt is disabled. + * | | |1 = The transmit start interrupt is enabled. + * |[2] |TXENDIEN |Transmit End Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a transmit finish event. + * | | |0 = The transmit finish interrupt is disabled. + * | | |1 = The transmit finish interrupt is enabled. + * |[3] |RXSTIEN |Receive Start Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a receive start event. + * | | |0 = The receive start interrupt is disabled. + * | | |1 = The receive start interrupt is enabled. + * |[4] |RXENDIEN |Receive End Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a receive finish event. + * | | |0 = The receive end interrupt is disabled. + * | | |1 = The receive end interrupt is enabled. + * @var USPI_T::BRGEN + * Offset: 0x08 USCI Baud Rate Generator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RCLKSEL |Reference Clock Source Selection + * | | |This bit selects the source of reference clock (fREF_CLK). + * | | |0 = Peripheral device clock fPCLK. + * | | |1 = Reserved. + * |[1] |PTCLKSEL |Protocol Clock Source Selection + * | | |This bit selects the source of protocol clock (fPROT_CLK). + * | | |0 = Reference clock fREF_CLK. + * | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK). + * |[3:2] |SPCLKSEL |Sample Clock Source Selection + * | | |This bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor. + * | | |00 = fDIV_CLK. + * | | |01 = fPROT_CLK. + * | | |10 = fSCLK. + * | | |11 = fREF_CLK. + * |[4] |TMCNTEN |Time Measurement Counter Enable Bit + * | | |This bit enables the 10-bit timing measurement counter. + * | | |0 = Time measurement counter is Disabled. + * | | |1 = Time measurement counter is Enabled. + * |[5] |TMCNTSRC |Time Measurement Counter Clock Source Selection + * | | |0 = Time measurement counter with fPROT_CLK. + * | | |1 = Time measurement counter with fDIV_CLK. + * |[25:16] |CLKDIV |Clock Divider + * | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ). + * | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(USPI_PROTCTL[6])) is enabled + * | | |The revised value is the average bit time between bit 5 and bit 6 + * | | |The user can use revised CLKDIV and new BRDETITV (USPI_PROTCTL[24:16]) to calculate the precise baud rate. + * @var USPI_T::DATIN0 + * Offset: 0x10 USCI Input Data Signal Configuration Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Signal Synchronization Selection + * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * | | |Note: In SPI protocol, we suggest this bit should be set as 0. + * |[2] |ININV |Input Signal Inverse Selection + * | | |This bit defines the inverter enable of the input asynchronous signal. + * | | |0 = The un-synchronized input signal will not be inverted. + * | | |1 = The un-synchronized input signal will be inverted. + * | | |Note: In SPI protocol, we suggest this bit should be set as 0. + * @var USPI_T::CTLIN0 + * Offset: 0x20 USCI Input Control Signal Configuration Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Synchronization Signal Selection + * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * | | |Note: In SPI protocol, we suggest this bit should be set as 0. + * |[2] |ININV |Input Signal Inverse Selection + * | | |This bit defines the inverter enable of the input asynchronous signal. + * | | |0 = The un-synchronized input signal will not be inverted. + * | | |1 = The un-synchronized input signal will be inverted. + * @var USPI_T::CLKIN + * Offset: 0x28 USCI Input Clock Signal Configuration Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Synchronization Signal Selection + * | | |This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * | | |Note: In SPI protocol, we suggest this bit should be set as 0. + * @var USPI_T::LINECTL + * Offset: 0x2C USCI Line Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LSB |LSB First Transmission Selection + * | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first. + * | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first. + * |[5] |DATOINV |Data Output Inverse Selection + * | | |This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin. + * | | |0 = Data output level is not inverted. + * | | |1 = Data output level is inverted. + * |[7] |CTLOINV |Control Signal Output Inverse Selection + * | | |This bit defines the relation between the internal control signal and the output control signal. + * | | |0 = No effect. + * | | |1 = The control signal will be inverted before its output. + * | | |Note: The control signal has different definitions in different protocol + * | | |In SPI protocol, the control signal means slave select signal + * |[11:8] |DWIDTH |Word Length of Transmission + * | | |This bit field defines the data word length (amount of bits) for reception and transmission + * | | |The data word is always right-aligned in the data buffer + * | | |USCI support word length from 4 to 16 bits. + * | | |0x0: The data word contains 16 bits located at bit positions [15:0]. + * | | |0x1: Reserved. + * | | |0x2: Reserved. + * | | |0x3: Reserved. + * | | |0x4: The data word contains 4 bits located at bit positions [3:0]. + * | | |0x5: The data word contains 5 bits located at bit positions [4:0]. + * | | |... + * | | |0xF: The data word contains 15 bits located at bit positions [14:0]. + * @var USPI_T::TXDAT + * Offset: 0x30 USCI Transmit Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TXDAT |Transmit Data + * | | |Software can use this bit field to write 16-bit transmit data for transmission + * | | |In order to avoid overwriting the transmit data, user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field. + * |[16] |PORTDIR |Port Direction Control + * | | |This bit field is only available while USCI operates in SPI protocol (FUNMODE = 0x1) with half-duplex transfer + * | | |It is used to define the direction of the data port pin + * | | |When software writes USPI_TXDAT register, the transmit data and its port direction are settled simultaneously. + * | | |0 = The data pin is configured as output mode. + * | | |1 = The data pin is configured as input mode. + * @var USPI_T::RXDAT + * Offset: 0x34 USCI Receive Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RXDAT |Received Data + * | | |This bit field monitors the received data which stored in receive data buffer. + * @var USPI_T::BUFCTL + * Offset: 0x38 USCI Transmit/Receive Buffer Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6] |TXUDRIEN |Slave Transmit Under Run Interrupt Enable Bit + * | | |0 = Transmit under-run interrupt Disabled. + * | | |1 = Transmit under-run interrupt Enabled. + * |[7] |TXCLR |Clear Transmit Buffer + * | | |0 = No effect. + * | | |1 = The transmit buffer is cleared + * | | |Should only be used while the buffer is not taking part in data traffic. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[14] |RXOVIEN |Receive Buffer Overrun Interrupt Enable Bit + * | | |0 = Receive overrun interrupt Disabled. + * | | |1 = Receive overrun interrupt Enabled. + * |[15] |RXCLR |Clear Receive Buffer + * | | |0 = No effect. + * | | |1 = The receive buffer is cleared + * | | |Should only be used while the buffer is not taking part in data traffic. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[16] |TXRST |Transmit Reset + * | | |0 = No effect. + * | | |1 = Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[17] |RXRST |Receive Reset + * | | |0 = No effect. + * | | |1 = Reset the receive-related counters, state machine, and the content of receive shift register and data buffer. + * | | |Note: It is cleared automatically after one PCLK cycle. + * @var USPI_T::BUFSTS + * Offset: 0x3C USCI Transmit/Receive Buffer Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXEMPTY |Receive Buffer Empty Indicator + * | | |0 = Receive buffer is not empty. + * | | |1 = Receive buffer is empty. + * |[1] |RXFULL |Receive Buffer Full Indicator + * | | |0 = Receive buffer is not full. + * | | |1 = Receive buffer is full. + * |[3] |RXOVIF |Receive Buffer Over-run Interrupt Status + * | | |This bit indicates that a receive buffer overrun event has been detected + * | | |If RXOVIEN (USPI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated + * | | |It is cleared by software writes 1 to this bit. + * | | |0 = A receive buffer overrun event has not been detected. + * | | |1 = A receive buffer overrun event has been detected. + * |[8] |TXEMPTY |Transmit Buffer Empty Indicator + * | | |0 = Transmit buffer is not empty. + * | | |1 = Transmit buffer is empty and available for the next transmission datum. + * |[9] |TXFULL |Transmit Buffer Full Indicator + * | | |0 = Transmit buffer is not full. + * | | |1 = Transmit buffer is full. + * |[11] |TXUDRIF |Transmit Buffer Under-run Interrupt Status + * | | |This bit indicates that a transmit buffer under-run event has been detected + * | | |If enabled by TXUDRIEN (USPI_BUFCTL[6]), the corresponding interrupt request is activated + * | | |It is cleared by software writes 1 to this bit + * | | |0 = A transmit buffer under-run event has not been detected. + * | | |1 = A transmit buffer under-run event has been detected. + * @var USPI_T::PDMACTL + * Offset: 0x40 USCI PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PDMARST |PDMA Reset + * | | |0 = No effect. + * | | |1 = Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically. + * |[1] |TXPDMAEN |PDMA Transmit Channel Available + * | | |0 = Transmit PDMA function Disabled. + * | | |1 = Transmit PDMA function Enabled. + * |[2] |RXPDMAEN |PDMA Receive Channel Available + * | | |0 = Receive PDMA function Disabled. + * | | |1 = Receive PDMA function Enabled. + * |[3] |PDMAEN |PDMA Mode Enable Bit + * | | |0 = PDMA function Disabled. + * | | |1 = PDMA function Enabled. + * | | |Notice: The I2C is not supporting PDMA function. + * @var USPI_T::WKCTL + * Offset: 0x54 USCI Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Wake-up Enable Bit + * | | |0 = Wake-up function Disabled. + * | | |1 = Wake-up function Enabled. + * |[1] |WKADDREN |Wake-up Address Match Enable Bit + * | | |0 = The chip is woken up according data toggle. + * | | |1 = The chip is woken up according address match. + * |[2] |PDBOPT |Power Down Blocking Option + * | | |0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately. + * | | |1 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately. + * @var USPI_T::WKSTS + * Offset: 0x58 USCI Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKF |Wake-up Flag + * | | |When chip is woken up from Power-down mode, this bit is set to 1 + * | | |Software can write 1 to clear this bit. + * @var USPI_T::PROTCTL + * Offset: 0x5C USCI Protocol Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SLAVE |Slave Mode Selection + * | | |0 = Master mode. + * | | |1 = Slave mode. + * |[1] |SLV3WIRE |Slave 3-wire Mode Selection (Slave Only) + * | | |The SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode. + * | | |0 = 4-wire bi-direction interface. + * | | |1 = 3-wire bi-direction interface. + * |[2] |SS |Slave Select Control (Master Only) + * | | |If AUTOSS bit is cleared, setting this bit to 1 will set the slave select signal to active state, and setting this bit to 0 will set the slave select signal back to inactive state. + * | | |If the AUTOSS function is enabled (AUTOSS = 1), the setting value of this bit will not affect the current state of slave select signal. + * | | |Note: In SPI protocol, the internal slave select signal is active high. + * |[3] |AUTOSS |Automatic Slave Select Function Enable (Master Only) + * | | |0 = Slave select signal will be controlled by the setting value of SS (USPI_PROTCTL[2]) bit. + * | | |1 = Slave select signal will be generated automatically + * | | |The slave select signal will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished. + * |[7:6] |SCLKMODE |Serial Bus Clock Mode + * | | |This bit field defines the SCLK idle status, data transmit, and data receive edge. + * | | |MODE0 = The idle state of SPI clock is low level + * | | |Data is transmitted with falling edge and received with rising edge. + * | | |MODE1 = The idle state of SPI clock is low level + * | | |Data is transmitted with rising edge and received with falling edge. + * | | |MODE2 = The idle state of SPI clock is high level + * | | |Data is transmitted with rising edge and received with falling edge. + * | | |MODE3 = The idle state of SPI clock is high level + * | | |Data is transmitted with falling edge and received with rising edge. + * |[11:8] |SUSPITV |Suspend Interval (Master Only) + * | | |This bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer + * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word + * | | |The default value is 0x3 + * | | |The period of the suspend interval is obtained according to the following equation. + * | | |(SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle + * | | |Example: + * | | |SUSPITV = 0x0 ... 0.5 SPI_CLK clock cycle. + * | | |SUSPITV = 0x1 ... 1.5 SPI_CLK clock cycle. + * | | |..... + * | | |SUSPITV = 0xE ... 14.5 SPI_CLK clock cycle. + * | | |SUSPITV = 0xF ... 15.5 SPI_CLK clock cycle. + * |[14:12] |TSMSEL |Transmit Data Mode Selection + * | | |This bit field describes how receive and transmit data is shifted in and out. + * | | |TSMSEL = 000b: Full-duplex SPI. + * | | |TSMSEL = 100b: Half-duplex SPI. + * | | |Other values are reserved. + * | | |Note: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically. + * |[25:16] |SLVTOCNT |Slave Mode Time-out Period (Slave Only) + * | | |In Slave mode, this bit field is used for Slave time-out period + * | | |This bit field indicates how many clock periods (selected by TMCNTSRC, USPI_BRGEN[5]) between the two edges of input SCLK will assert the Slave time-out event + * | | |Writing 0x0 into this bit field will disable the Slave time-out function. + * | | |Example: Assume SLVTOCNT is 0x0A and TMCNTSRC (USPI_BRGEN[5]) is 1, it means the time-out event will occur if the state of SPI bus clock pin is not changed more than (10+1) periods of fDIV_CLK. + * |[28] |TXUDRPOL |Transmit Under-run Data Polarity (for Slave) + * | | |This bit defines the transmitting data level when no data is available for transferring. + * | | |0 = The output data level is 0 if TX under run event occurs. + * | | |1 = The output data level is 1 if TX under run event occurs. + * |[31] |PROTEN |SPI Protocol Enable Bit + * | | |0 = SPI Protocol Disabled. + * | | |1 = SPI Protocol Enabled. + * @var USPI_T::PROTIEN + * Offset: 0x60 USCI Protocol Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SSINAIEN |Slave Select Inactive Interrupt Enable Control + * | | |This bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive. + * | | |0 = Slave select inactive interrupt generation Disabled. + * | | |1 = Slave select inactive interrupt generation Enabled. + * |[1] |SSACTIEN |Slave Select Active Interrupt Enable Control + * | | |This bit enables/disables the generation of a slave select interrupt if the slave select changes to active. + * | | |0 = Slave select active interrupt generation Disabled. + * | | |1 = Slave select active interrupt generation Enabled. + * |[2] |SLVTOIEN |Slave Time-out Interrupt Enable Control + * | | |In SPI protocol, this bit enables the interrupt generation in case of a Slave time-out event. + * | | |0 = The Slave time-out interrupt Disabled. + * | | |1 = The Slave time-out interrupt Enabled. + * |[3] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Control + * | | |If data transfer is terminated by slave time-out or slave select inactive event in Slave mode, so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]) + * | | |Bit count error event occurs. + * | | |0 = The Slave mode bit count error interrupt Disabled. + * | | |1 = The Slave mode bit count error interrupt Enabled. + * @var USPI_T::PROTSTS + * Offset: 0x64 USCI Protocol Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TXSTIF |Transmit Start Interrupt Flag + * | | |0 = Transmit start event does not occur. + * | | |1 = Transmit start event occurs. + * | | |Note: It is cleared by software writes 1 to this bit + * |[2] |TXENDIF |Transmit End Interrupt Flag + * | | |0 = Transmit end event does not occur. + * | | |1 = Transmit end event occurs. + * | | |Note: It is cleared by software writes 1 to this bit + * |[3] |RXSTIF |Receive Start Interrupt Flag + * | | |0 = Receive start event does not occur. + * | | |1 = Receive start event occurs. + * | | |Note: It is cleared by software writes 1 to this bit + * |[4] |RXENDIF |Receive End Interrupt Flag + * | | |0 = Receive end event does not occur. + * | | |1 = Receive end event occurs. + * | | |Note: It is cleared by software writes 1 to this bit + * |[5] |SLVTOIF |Slave Time-out Interrupt Flag (for Slave Only) + * | | |0 = Slave time-out event does not occur. + * | | |1 = Slave time-out event occurs. + * | | |Note: It is cleared by software writes 1 to this bit + * |[6] |SLVBEIF |Slave Bit Count Error Interrupt Flag (for Slave Only) + * | | |0 = Slave bit count error event does not occur. + * | | |1 = Slave bit count error event occurs. + * | | |Note: It is cleared by software writes 1 to this bit. + * |[8] |SSINAIF |Slave Select Inactive Interrupt Flag (for Slave Only) + * | | |This bit indicates that the internal slave select signal has changed to inactive + * | | |It is cleared by software writes 1 to this bit + * | | |0 = The slave select signal has not changed to inactive. + * | | |1 = The slave select signal has changed to inactive. + * | | |Note: The internal slave select signal is active high. + * |[9] |SSACTIF |Slave Select Active Interrupt Flag (for Slave Only) + * | | |This bit indicates that the internal slave select signal has changed to active + * | | |It is cleared by software writes one to this bit + * | | |0 = The slave select signal has not changed to active. + * | | |1 = The slave select signal has changed to active. + * | | |Note: The internal slave select signal is active high. + * |[16] |SSLINE |Slave Select Line Bus Status (Read Only) + * | | |This bit is only available in Slave mode + * | | |It used to monitor the current status of the input slave select signal on the bus. + * | | |0 = The slave select line status is 0. + * | | |1 = The slave select line status is 1. + * |[17] |BUSY |Busy Status (Read Only) + * | | |0 = SPI is in idle state. + * | | |1 = SPI is in busy state. + * | | |The following listing are the bus busy conditions: + * | | |a. USPI_PROTCTL[31] = 1 and the TXEMPTY = 0. + * | | |b. For SPI Master mode, the TXEMPTY = 1 but the current transaction is not finished yet. + * | | |c. For SPI Slave mode, the USPI_PROTCTL[31] = 1 and there is serial clock input into the SPI core logic when slave select is active. + * | | |d. For SPI Slave mode, the USPI_PROTCTL[31] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive. + * |[18] |SLVUDR |Slave Mode Transmit Under-run Status (Read Only) + * | | |In Slave mode, if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock, this status flag will be set to 1 + * | | |This bit indicates whether the current shift-out data of word transmission is switched to TXUDRPOL (USPI_PROTCTL[28]) or not. + * | | |0 = Slave transmit under-run event does not occur. + * | | |1 = Slave transmit under-run event occurs. + */ + __IO uint32_t CTL; /*!< [0x0000] USCI Control Register */ + __IO uint32_t INTEN; /*!< [0x0004] USCI Interrupt Enable Register */ + __IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t DATIN0; /*!< [0x0010] USCI Input Data Signal Configuration Register 0 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[3]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CTLIN0; /*!< [0x0020] USCI Input Control Signal Configuration Register 0 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CLKIN; /*!< [0x0028] USCI Input Clock Signal Configuration Register */ + __IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */ + __O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */ + __I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */ + __IO uint32_t BUFCTL; /*!< [0x0038] USCI Transmit/Receive Buffer Control Register */ + __IO uint32_t BUFSTS; /*!< [0x003c] USCI Transmit/Receive Buffer Status Register */ + __IO uint32_t PDMACTL; /*!< [0x0040] USCI PDMA Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[4]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */ + __IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */ + __IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */ + __IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */ + __IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */ + +} USPI_T; + +/** + @addtogroup USPI_CONST USPI Bit Field Definition + Constant Definitions for USPI Controller +@{ */ + +#define USPI_CTL_FUNMODE_Pos (0) /*!< USPI_T::CTL: FUNMODE Position */ +#define USPI_CTL_FUNMODE_Msk (0x7ul << USPI_CTL_FUNMODE_Pos) /*!< USPI_T::CTL: FUNMODE Mask */ + +#define USPI_INTEN_TXSTIEN_Pos (1) /*!< USPI_T::INTEN: TXSTIEN Position */ +#define USPI_INTEN_TXSTIEN_Msk (0x1ul << USPI_INTEN_TXSTIEN_Pos) /*!< USPI_T::INTEN: TXSTIEN Mask */ + +#define USPI_INTEN_TXENDIEN_Pos (2) /*!< USPI_T::INTEN: TXENDIEN Position */ +#define USPI_INTEN_TXENDIEN_Msk (0x1ul << USPI_INTEN_TXENDIEN_Pos) /*!< USPI_T::INTEN: TXENDIEN Mask */ + +#define USPI_INTEN_RXSTIEN_Pos (3) /*!< USPI_T::INTEN: RXSTIEN Position */ +#define USPI_INTEN_RXSTIEN_Msk (0x1ul << USPI_INTEN_RXSTIEN_Pos) /*!< USPI_T::INTEN: RXSTIEN Mask */ + +#define USPI_INTEN_RXENDIEN_Pos (4) /*!< USPI_T::INTEN: RXENDIEN Position */ +#define USPI_INTEN_RXENDIEN_Msk (0x1ul << USPI_INTEN_RXENDIEN_Pos) /*!< USPI_T::INTEN: RXENDIEN Mask */ + +#define USPI_BRGEN_RCLKSEL_Pos (0) /*!< USPI_T::BRGEN: RCLKSEL Position */ +#define USPI_BRGEN_RCLKSEL_Msk (0x1ul << USPI_BRGEN_RCLKSEL_Pos) /*!< USPI_T::BRGEN: RCLKSEL Mask */ + +#define USPI_BRGEN_PTCLKSEL_Pos (1) /*!< USPI_T::BRGEN: PTCLKSEL Position */ +#define USPI_BRGEN_PTCLKSEL_Msk (0x1ul << USPI_BRGEN_PTCLKSEL_Pos) /*!< USPI_T::BRGEN: PTCLKSEL Mask */ + +#define USPI_BRGEN_SPCLKSEL_Pos (2) /*!< USPI_T::BRGEN: SPCLKSEL Position */ +#define USPI_BRGEN_SPCLKSEL_Msk (0x3ul << USPI_BRGEN_SPCLKSEL_Pos) /*!< USPI_T::BRGEN: SPCLKSEL Mask */ + +#define USPI_BRGEN_TMCNTEN_Pos (4) /*!< USPI_T::BRGEN: TMCNTEN Position */ +#define USPI_BRGEN_TMCNTEN_Msk (0x1ul << USPI_BRGEN_TMCNTEN_Pos) /*!< USPI_T::BRGEN: TMCNTEN Mask */ + +#define USPI_BRGEN_TMCNTSRC_Pos (5) /*!< USPI_T::BRGEN: TMCNTSRC Position */ +#define USPI_BRGEN_TMCNTSRC_Msk (0x1ul << USPI_BRGEN_TMCNTSRC_Pos) /*!< USPI_T::BRGEN: TMCNTSRC Mask */ + +#define USPI_BRGEN_CLKDIV_Pos (16) /*!< USPI_T::BRGEN: CLKDIV Position */ +#define USPI_BRGEN_CLKDIV_Msk (0x3fful << USPI_BRGEN_CLKDIV_Pos) /*!< USPI_T::BRGEN: CLKDIV Mask */ + +#define USPI_DATIN0_SYNCSEL_Pos (0) /*!< USPI_T::DATIN0: SYNCSEL Position */ +#define USPI_DATIN0_SYNCSEL_Msk (0x1ul << USPI_DATIN0_SYNCSEL_Pos) /*!< USPI_T::DATIN0: SYNCSEL Mask */ + +#define USPI_DATIN0_ININV_Pos (2) /*!< USPI_T::DATIN0: ININV Position */ +#define USPI_DATIN0_ININV_Msk (0x1ul << USPI_DATIN0_ININV_Pos) /*!< USPI_T::DATIN0: ININV Mask */ + +#define USPI_CTLIN0_SYNCSEL_Pos (0) /*!< USPI_T::CTLIN0: SYNCSEL Position */ +#define USPI_CTLIN0_SYNCSEL_Msk (0x1ul << USPI_CTLIN0_SYNCSEL_Pos) /*!< USPI_T::CTLIN0: SYNCSEL Mask */ + +#define USPI_CTLIN0_ININV_Pos (2) /*!< USPI_T::CTLIN0: ININV Position */ +#define USPI_CTLIN0_ININV_Msk (0x1ul << USPI_CTLIN0_ININV_Pos) /*!< USPI_T::CTLIN0: ININV Mask */ + +#define USPI_CLKIN_SYNCSEL_Pos (0) /*!< USPI_T::CLKIN: SYNCSEL Position */ +#define USPI_CLKIN_SYNCSEL_Msk (0x1ul << USPI_CLKIN_SYNCSEL_Pos) /*!< USPI_T::CLKIN: SYNCSEL Mask */ + +#define USPI_LINECTL_LSB_Pos (0) /*!< USPI_T::LINECTL: LSB Position */ +#define USPI_LINECTL_LSB_Msk (0x1ul << USPI_LINECTL_LSB_Pos) /*!< USPI_T::LINECTL: LSB Mask */ + +#define USPI_LINECTL_DATOINV_Pos (5) /*!< USPI_T::LINECTL: DATOINV Position */ +#define USPI_LINECTL_DATOINV_Msk (0x1ul << USPI_LINECTL_DATOINV_Pos) /*!< USPI_T::LINECTL: DATOINV Mask */ + +#define USPI_LINECTL_CTLOINV_Pos (7) /*!< USPI_T::LINECTL: CTLOINV Position */ +#define USPI_LINECTL_CTLOINV_Msk (0x1ul << USPI_LINECTL_CTLOINV_Pos) /*!< USPI_T::LINECTL: CTLOINV Mask */ + +#define USPI_LINECTL_DWIDTH_Pos (8) /*!< USPI_T::LINECTL: DWIDTH Position */ +#define USPI_LINECTL_DWIDTH_Msk (0xful << USPI_LINECTL_DWIDTH_Pos) /*!< USPI_T::LINECTL: DWIDTH Mask */ + +#define USPI_TXDAT_TXDAT_Pos (0) /*!< USPI_T::TXDAT: TXDAT Position */ +#define USPI_TXDAT_TXDAT_Msk (0xfffful << USPI_TXDAT_TXDAT_Pos) /*!< USPI_T::TXDAT: TXDAT Mask */ + +#define USPI_TXDAT_PORTDIR_Pos (16) /*!< USPI_T::TXDAT: PORTDIR Position */ +#define USPI_TXDAT_PORTDIR_Msk (0x1ul << USPI_TXDAT_PORTDIR_Pos) /*!< USPI_T::TXDAT: PORTDIR Mask */ + +#define USPI_RXDAT_RXDAT_Pos (0) /*!< USPI_T::RXDAT: RXDAT Position */ +#define USPI_RXDAT_RXDAT_Msk (0xfffful << USPI_RXDAT_RXDAT_Pos) /*!< USPI_T::RXDAT: RXDAT Mask */ + +#define USPI_BUFCTL_TXUDRIEN_Pos (6) /*!< USPI_T::BUFCTL: TXUDRIEN Position */ +#define USPI_BUFCTL_TXUDRIEN_Msk (0x1ul << USPI_BUFCTL_TXUDRIEN_Pos) /*!< USPI_T::BUFCTL: TXUDRIEN Mask */ + +#define USPI_BUFCTL_TXCLR_Pos (7) /*!< USPI_T::BUFCTL: TXCLR Position */ +#define USPI_BUFCTL_TXCLR_Msk (0x1ul << USPI_BUFCTL_TXCLR_Pos) /*!< USPI_T::BUFCTL: TXCLR Mask */ + +#define USPI_BUFCTL_RXOVIEN_Pos (14) /*!< USPI_T::BUFCTL: RXOVIEN Position */ +#define USPI_BUFCTL_RXOVIEN_Msk (0x1ul << USPI_BUFCTL_RXOVIEN_Pos) /*!< USPI_T::BUFCTL: RXOVIEN Mask */ + +#define USPI_BUFCTL_RXCLR_Pos (15) /*!< USPI_T::BUFCTL: RXCLR Position */ +#define USPI_BUFCTL_RXCLR_Msk (0x1ul << USPI_BUFCTL_RXCLR_Pos) /*!< USPI_T::BUFCTL: RXCLR Mask */ + +#define USPI_BUFCTL_TXRST_Pos (16) /*!< USPI_T::BUFCTL: TXRST Position */ +#define USPI_BUFCTL_TXRST_Msk (0x1ul << USPI_BUFCTL_TXRST_Pos) /*!< USPI_T::BUFCTL: TXRST Mask */ + +#define USPI_BUFCTL_RXRST_Pos (17) /*!< USPI_T::BUFCTL: RXRST Position */ +#define USPI_BUFCTL_RXRST_Msk (0x1ul << USPI_BUFCTL_RXRST_Pos) /*!< USPI_T::BUFCTL: RXRST Mask */ + +#define USPI_BUFSTS_RXEMPTY_Pos (0) /*!< USPI_T::BUFSTS: RXEMPTY Position */ +#define USPI_BUFSTS_RXEMPTY_Msk (0x1ul << USPI_BUFSTS_RXEMPTY_Pos) /*!< USPI_T::BUFSTS: RXEMPTY Mask */ + +#define USPI_BUFSTS_RXFULL_Pos (1) /*!< USPI_T::BUFSTS: RXFULL Position */ +#define USPI_BUFSTS_RXFULL_Msk (0x1ul << USPI_BUFSTS_RXFULL_Pos) /*!< USPI_T::BUFSTS: RXFULL Mask */ + +#define USPI_BUFSTS_RXOVIF_Pos (3) /*!< USPI_T::BUFSTS: RXOVIF Position */ +#define USPI_BUFSTS_RXOVIF_Msk (0x1ul << USPI_BUFSTS_RXOVIF_Pos) /*!< USPI_T::BUFSTS: RXOVIF Mask */ + +#define USPI_BUFSTS_TXEMPTY_Pos (8) /*!< USPI_T::BUFSTS: TXEMPTY Position */ +#define USPI_BUFSTS_TXEMPTY_Msk (0x1ul << USPI_BUFSTS_TXEMPTY_Pos) /*!< USPI_T::BUFSTS: TXEMPTY Mask */ + +#define USPI_BUFSTS_TXFULL_Pos (9) /*!< USPI_T::BUFSTS: TXFULL Position */ +#define USPI_BUFSTS_TXFULL_Msk (0x1ul << USPI_BUFSTS_TXFULL_Pos) /*!< USPI_T::BUFSTS: TXFULL Mask */ + +#define USPI_BUFSTS_TXUDRIF_Pos (11) /*!< USPI_T::BUFSTS: TXUDRIF Position */ +#define USPI_BUFSTS_TXUDRIF_Msk (0x1ul << USPI_BUFSTS_TXUDRIF_Pos) /*!< USPI_T::BUFSTS: TXUDRIF Mask */ + +#define USPI_PDMACTL_PDMARST_Pos (0) /*!< USPI_T::PDMACTL: PDMARST Position */ +#define USPI_PDMACTL_PDMARST_Msk (0x1ul << USPI_PDMACTL_PDMARST_Pos) /*!< USPI_T::PDMACTL: PDMARST Mask */ + +#define USPI_PDMACTL_TXPDMAEN_Pos (1) /*!< USPI_T::PDMACTL: TXPDMAEN Position */ +#define USPI_PDMACTL_TXPDMAEN_Msk (0x1ul << USPI_PDMACTL_TXPDMAEN_Pos) /*!< USPI_T::PDMACTL: TXPDMAEN Mask */ + +#define USPI_PDMACTL_RXPDMAEN_Pos (2) /*!< USPI_T::PDMACTL: RXPDMAEN Position */ +#define USPI_PDMACTL_RXPDMAEN_Msk (0x1ul << USPI_PDMACTL_RXPDMAEN_Pos) /*!< USPI_T::PDMACTL: RXPDMAEN Mask */ + +#define USPI_PDMACTL_PDMAEN_Pos (3) /*!< USPI_T::PDMACTL: PDMAEN Position */ +#define USPI_PDMACTL_PDMAEN_Msk (0x1ul << USPI_PDMACTL_PDMAEN_Pos) /*!< USPI_T::PDMACTL: PDMAEN Mask */ + +#define USPI_WKCTL_WKEN_Pos (0) /*!< USPI_T::WKCTL: WKEN Position */ +#define USPI_WKCTL_WKEN_Msk (0x1ul << USPI_WKCTL_WKEN_Pos) /*!< USPI_T::WKCTL: WKEN Mask */ + +#define USPI_WKCTL_WKADDREN_Pos (1) /*!< USPI_T::WKCTL: WKADDREN Position */ +#define USPI_WKCTL_WKADDREN_Msk (0x1ul << USPI_WKCTL_WKADDREN_Pos) /*!< USPI_T::WKCTL: WKADDREN Mask */ + +#define USPI_WKCTL_PDBOPT_Pos (2) /*!< USPI_T::WKCTL: PDBOPT Position */ +#define USPI_WKCTL_PDBOPT_Msk (0x1ul << USPI_WKCTL_PDBOPT_Pos) /*!< USPI_T::WKCTL: PDBOPT Mask */ + +#define USPI_WKSTS_WKF_Pos (0) /*!< USPI_T::WKSTS: WKF Position */ +#define USPI_WKSTS_WKF_Msk (0x1ul << USPI_WKSTS_WKF_Pos) /*!< USPI_T::WKSTS: WKF Mask */ + +#define USPI_PROTCTL_SLAVE_Pos (0) /*!< USPI_T::PROTCTL: SLAVE Position */ +#define USPI_PROTCTL_SLAVE_Msk (0x1ul << USPI_PROTCTL_SLAVE_Pos) /*!< USPI_T::PROTCTL: SLAVE Mask */ + +#define USPI_PROTCTL_SLV3WIRE_Pos (1) /*!< USPI_T::PROTCTL: SLV3WIRE Position */ +#define USPI_PROTCTL_SLV3WIRE_Msk (0x1ul << USPI_PROTCTL_SLV3WIRE_Pos) /*!< USPI_T::PROTCTL: SLV3WIRE Mask */ + +#define USPI_PROTCTL_SS_Pos (2) /*!< USPI_T::PROTCTL: SS Position */ +#define USPI_PROTCTL_SS_Msk (0x1ul << USPI_PROTCTL_SS_Pos) /*!< USPI_T::PROTCTL: SS Mask */ + +#define USPI_PROTCTL_AUTOSS_Pos (3) /*!< USPI_T::PROTCTL: AUTOSS Position */ +#define USPI_PROTCTL_AUTOSS_Msk (0x1ul << USPI_PROTCTL_AUTOSS_Pos) /*!< USPI_T::PROTCTL: AUTOSS Mask */ + +#define USPI_PROTCTL_SCLKMODE_Pos (6) /*!< USPI_T::PROTCTL: SCLKMODE Position */ +#define USPI_PROTCTL_SCLKMODE_Msk (0x3ul << USPI_PROTCTL_SCLKMODE_Pos) /*!< USPI_T::PROTCTL: SCLKMODE Mask */ + +#define USPI_PROTCTL_SUSPITV_Pos (8) /*!< USPI_T::PROTCTL: SUSPITV Position */ +#define USPI_PROTCTL_SUSPITV_Msk (0xful << USPI_PROTCTL_SUSPITV_Pos) /*!< USPI_T::PROTCTL: SUSPITV Mask */ + +#define USPI_PROTCTL_TSMSEL_Pos (12) /*!< USPI_T::PROTCTL: TSMSEL Position */ +#define USPI_PROTCTL_TSMSEL_Msk (0x7ul << USPI_PROTCTL_TSMSEL_Pos) /*!< USPI_T::PROTCTL: TSMSEL Mask */ + +#define USPI_PROTCTL_SLVTOCNT_Pos (16) /*!< USPI_T::PROTCTL: SLVTOCNT Position */ +#define USPI_PROTCTL_SLVTOCNT_Msk (0x3fful << USPI_PROTCTL_SLVTOCNT_Pos) /*!< USPI_T::PROTCTL: SLVTOCNT Mask */ + +#define USPI_PROTCTL_TXUDRPOL_Pos (28) /*!< USPI_T::PROTCTL: TXUDRPOL Position */ +#define USPI_PROTCTL_TXUDRPOL_Msk (0x1ul << USPI_PROTCTL_TXUDRPOL_Pos) /*!< USPI_T::PROTCTL: TXUDRPOL Mask */ + +#define USPI_PROTCTL_PROTEN_Pos (31) /*!< USPI_T::PROTCTL: PROTEN Position */ +#define USPI_PROTCTL_PROTEN_Msk (0x1ul << USPI_PROTCTL_PROTEN_Pos) /*!< USPI_T::PROTCTL: PROTEN Mask */ + +#define USPI_PROTIEN_SSINAIEN_Pos (0) /*!< USPI_T::PROTIEN: SSINAIEN Position */ +#define USPI_PROTIEN_SSINAIEN_Msk (0x1ul << USPI_PROTIEN_SSINAIEN_Pos) /*!< USPI_T::PROTIEN: SSINAIEN Mask */ + +#define USPI_PROTIEN_SSACTIEN_Pos (1) /*!< USPI_T::PROTIEN: SSACTIEN Position */ +#define USPI_PROTIEN_SSACTIEN_Msk (0x1ul << USPI_PROTIEN_SSACTIEN_Pos) /*!< USPI_T::PROTIEN: SSACTIEN Mask */ + +#define USPI_PROTIEN_SLVTOIEN_Pos (2) /*!< USPI_T::PROTIEN: SLVTOIEN Position */ +#define USPI_PROTIEN_SLVTOIEN_Msk (0x1ul << USPI_PROTIEN_SLVTOIEN_Pos) /*!< USPI_T::PROTIEN: SLVTOIEN Mask */ + +#define USPI_PROTIEN_SLVBEIEN_Pos (3) /*!< USPI_T::PROTIEN: SLVBEIEN Position */ +#define USPI_PROTIEN_SLVBEIEN_Msk (0x1ul << USPI_PROTIEN_SLVBEIEN_Pos) /*!< USPI_T::PROTIEN: SLVBEIEN Mask */ + +#define USPI_PROTSTS_TXSTIF_Pos (1) /*!< USPI_T::PROTSTS: TXSTIF Position */ +#define USPI_PROTSTS_TXSTIF_Msk (0x1ul << USPI_PROTSTS_TXSTIF_Pos) /*!< USPI_T::PROTSTS: TXSTIF Mask */ + +#define USPI_PROTSTS_TXENDIF_Pos (2) /*!< USPI_T::PROTSTS: TXENDIF Position */ +#define USPI_PROTSTS_TXENDIF_Msk (0x1ul << USPI_PROTSTS_TXENDIF_Pos) /*!< USPI_T::PROTSTS: TXENDIF Mask */ + +#define USPI_PROTSTS_RXSTIF_Pos (3) /*!< USPI_T::PROTSTS: RXSTIF Position */ +#define USPI_PROTSTS_RXSTIF_Msk (0x1ul << USPI_PROTSTS_RXSTIF_Pos) /*!< USPI_T::PROTSTS: RXSTIF Mask */ + +#define USPI_PROTSTS_RXENDIF_Pos (4) /*!< USPI_T::PROTSTS: RXENDIF Position */ +#define USPI_PROTSTS_RXENDIF_Msk (0x1ul << USPI_PROTSTS_RXENDIF_Pos) /*!< USPI_T::PROTSTS: RXENDIF Mask */ + +#define USPI_PROTSTS_SLVTOIF_Pos (5) /*!< USPI_T::PROTSTS: SLVTOIF Position */ +#define USPI_PROTSTS_SLVTOIF_Msk (0x1ul << USPI_PROTSTS_SLVTOIF_Pos) /*!< USPI_T::PROTSTS: SLVTOIF Mask */ + +#define USPI_PROTSTS_SLVBEIF_Pos (6) /*!< USPI_T::PROTSTS: SLVBEIF Position */ +#define USPI_PROTSTS_SLVBEIF_Msk (0x1ul << USPI_PROTSTS_SLVBEIF_Pos) /*!< USPI_T::PROTSTS: SLVBEIF Mask */ + +#define USPI_PROTSTS_SSINAIF_Pos (8) /*!< USPI_T::PROTSTS: SSINAIF Position */ +#define USPI_PROTSTS_SSINAIF_Msk (0x1ul << USPI_PROTSTS_SSINAIF_Pos) /*!< USPI_T::PROTSTS: SSINAIF Mask */ + +#define USPI_PROTSTS_SSACTIF_Pos (9) /*!< USPI_T::PROTSTS: SSACTIF Position */ +#define USPI_PROTSTS_SSACTIF_Msk (0x1ul << USPI_PROTSTS_SSACTIF_Pos) /*!< USPI_T::PROTSTS: SSACTIF Mask */ + +#define USPI_PROTSTS_SSLINE_Pos (16) /*!< USPI_T::PROTSTS: SSLINE Position */ +#define USPI_PROTSTS_SSLINE_Msk (0x1ul << USPI_PROTSTS_SSLINE_Pos) /*!< USPI_T::PROTSTS: SSLINE Mask */ + +#define USPI_PROTSTS_BUSY_Pos (17) /*!< USPI_T::PROTSTS: BUSY Position */ +#define USPI_PROTSTS_BUSY_Msk (0x1ul << USPI_PROTSTS_BUSY_Pos) /*!< USPI_T::PROTSTS: BUSY Mask */ + +#define USPI_PROTSTS_SLVUDR_Pos (18) /*!< USPI_T::PROTSTS: SLVUDR Position */ +#define USPI_PROTSTS_SLVUDR_Msk (0x1ul << USPI_PROTSTS_SLVUDR_Pos) /*!< USPI_T::PROTSTS: SLVUDR Mask */ + +/**@}*/ /* USPI_CONST */ +/**@}*/ /* end of USPI register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __USPI_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/uuart_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/uuart_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..3ebce1d6f31417f114655aacae9fefc665338206 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/uuart_reg.h @@ -0,0 +1,679 @@ +/**************************************************************************//** + * @file uuart_reg.h + * @version V1.00 + * @brief UUART register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __UUART_REG_H__ +#define __UUART_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup UUART UART Mode of USCI Controller(UUART) + Memory Mapped Structure for UUART Controller +@{ */ + +typedef struct +{ + + + /** + * @var UUART_T::CTL + * Offset: 0x00 USCI Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |FUNMODE |Function Mode + * | | |This bit field selects the protocol for this USCI controller + * | | |Selecting a protocol that is not available or a reserved combination disables the USCI + * | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol + * | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE. + * | | |000 = The USCI is disabled. All protocol related state machines are set to idle state. + * | | |001 = The SPI protocol is selected. + * | | |010 = The UART protocol is selected. + * | | |100 = The I2C protocol is selected. + * | | |Note: Other bit combinations are reserved. + * @var UUART_T::INTEN + * Offset: 0x04 USCI Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TXSTIEN |Transmit Start Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a transmit start event. + * | | |0 = The transmit start interrupt is disabled. + * | | |1 = The transmit start interrupt is enabled. + * |[2] |TXENDIEN |Transmit End Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a transmit finish event. + * | | |0 = The transmit finish interrupt is disabled. + * | | |1 = The transmit finish interrupt is enabled. + * |[3] |RXSTIEN |Receive Start Interrupt Enable BIt + * | | |This bit enables the interrupt generation in case of a receive start event. + * | | |0 = The receive start interrupt is disabled. + * | | |1 = The receive start interrupt is enabled. + * |[4] |RXENDIEN |Receive End Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a receive finish event. + * | | |0 = The receive end interrupt is disabled. + * | | |1 = The receive end interrupt is enabled. + * @var UUART_T::BRGEN + * Offset: 0x08 USCI Baud Rate Generator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RCLKSEL |Reference Clock Source Selection + * | | |This bit selects the source signal of reference clock (fREF_CLK). + * | | |0 = Peripheral device clock fPCLK. + * | | |1 = Reserved. + * |[1] |PTCLKSEL |Protocol Clock Source Selection + * | | |This bit selects the source signal of protocol clock (fPROT_CLK). + * | | |0 = Reference clock fREF_CLK. + * | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK). + * |[3:2] |SPCLKSEL |Sample Clock Source Selection + * | | |This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor. + * | | |00 = fSAMP_CLK = fDIV_CLK. + * | | |01 = fSAMP_CLK = fPROT_CLK. + * | | |10 = fSAMP_CLK = fSCLK. + * | | |11 = fSAMP_CLK = fREF_CLK. + * |[4] |TMCNTEN |Timing Measurement Counter Enable Bit + * | | |This bit enables the 10-bit timing measurement counter. + * | | |0 = Timing measurement counter is Disabled. + * | | |1 = Timing measurement counter is Enabled. + * |[5] |TMCNTSRC |Timing Measurement Counter Clock Source Selection + * | | |0 = Timing measurement counter with fPROT_CLK. + * | | |1 = Timing measurement counter with fDIV_CLK. + * |[9:8] |PDSCNT |Pre-divider for Sample Counter + * | | |This bit field defines the divide ratio of the clock division from sample clock fSAMP_CLK + * | | |The divided frequency fPDS_CNT = fSAMP_CLK / (PDSCNT+1). + * |[14:10] |DSCNT |Denominator for Sample Counter + * | | |This bit field defines the divide ratio of the sample clock fSAMP_CLK. + * | | |The divided frequency fDS_CNT = fPDS_CNT / (DSCNT+1). + * | | |Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value + * |[25:16] |CLKDIV |Clock Divider + * | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and + * | | |the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ). + * | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 + * | | |when the auto baud rate function (ABREN(USCI_PROTCTL[6])) is enabled + * | | |The revised value is the average bit time between bit 5 and bit 6 + * | | |The user can use revised CLKDIV and new BRDETITV (USCI_PROTCTL[24:16]) to calculate the precise baud rate. + * @var UUART_T::DATIN0 + * Offset: 0x10 USCI Input Data Signal Configuration Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Signal Synchronization Selection + * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or + * | | |the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * |[2] |ININV |Input Signal Inverse Selection + * | | |This bit defines the inverter enable of the input asynchronous signal. + * | | |0 = The un-synchronized input signal will not be inverted. + * | | |1 = The un-synchronized input signal will be inverted. + * |[4:3] |EDGEDET |Input Signal Edge Detection Mode + * | | |This bit field selects which edge actives the trigger event of input data signal. + * | | |00 = The trigger event activation is disabled. + * | | |01 = A rising edge activates the trigger event of input data signal. + * | | |10 = A falling edge activates the trigger event of input data signal. + * | | |11 = Both edges activate the trigger event of input data signal. + * | | |Note: In UART function mode, it is suggested to set this bit field as 10. + * @var UUART_T::CTLIN0 + * Offset: 0x20 USCI Input Control Signal Configuration Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Synchronization Signal Selection + * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or + * | | |the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * |[2] |ININV |Input Signal Inverse Selection + * | | |This bit defines the inverter enable of the input asynchronous signal. + * | | |0 = The un-synchronized input signal will not be inverted. + * | | |1 = The un-synchronized input signal will be inverted. + * @var UUART_T::CLKIN + * Offset: 0x28 USCI Input Clock Signal Configuration Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Synchronization Signal Selection + * | | |This bit selects if the un-synchronized input signal or + * | | |the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * @var UUART_T::LINECTL + * Offset: 0x2C USCI Line Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LSB |LSB First Transmission Selection + * | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first. + * | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first. + * |[5] |DATOINV |Data Output Inverse Selection + * | | |This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin. + * | | |0 = The value of USCIx_DAT1 is equal to the data shift register. + * | | |1 = The value of USCIx_DAT1 is the inversion of data shift register. + * |[7] |CTLOINV |Control Signal Output Inverse Selection + * | | |This bit defines the relation between the internal control signal and the output control signal. + * | | |0 = No effect. + * | | |1 = The control signal will be inverted before its output. + * | | |Note: In UART protocol, the control signal means nRTS signal. + * |[11:8] |DWIDTH |Word Length of Transmission + * | | |This bit field defines the data word length (amount of bits) for reception and transmission + * | | |The data word is always right-aligned in the data buffer + * | | |USCI support word length from 4 to 16 bits. + * | | |0x0: The data word contains 16 bits located at bit positions [15:0]. + * | | |0x1: Reserved. + * | | |0x2: Reserved. + * | | |0x3: Reserved. + * | | |0x4: The data word contains 4 bits located at bit positions [3:0]. + * | | |0x5: The data word contains 5 bits located at bit positions [4:0]. + * | | |.. + * | | |0xF: The data word contains 15 bits located at bit positions [14:0]. + * | | |Note: In UART protocol, the length can be configured as 6~13 bits. + * @var UUART_T::TXDAT + * Offset: 0x30 USCI Transmit Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TXDAT |Transmit Data + * | | |Software can use this bit field to write 16-bit transmit data for transmission. + * @var UUART_T::RXDAT + * Offset: 0x34 USCI Receive Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RXDAT |Received Data + * | | |This bit field monitors the received data which stored in receive data buffer. + * | | |Note: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (USCI_PROTSTS[7:5]). + * @var UUART_T::BUFCTL + * Offset: 0x38 USCI Transmit/Receive Buffer Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7] |TXCLR |Clear Transmit Buffer + * | | |0 = No effect. + * | | |1 = The transmit buffer is cleared (filling level is cleared and output pointer is set to input pointer value) + * | | |Should only be used while the buffer is not taking part in data traffic. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[14] |RXOVIEN |Receive Buffer Overrun Error Interrupt Enable Control + * | | |0 = Receive overrun interrupt Disabled. + * | | |1 = Receive overrun interrupt Enabled. + * |[15] |RXCLR |Clear Receive Buffer + * | | |0 = No effect. + * | | |1 = The receive buffer is cleared (filling level is cleared and output pointer is set to input pointer value) + * | | |Should only be used while the buffer is not taking part in data traffic. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[16] |TXRST |Transmit Reset + * | | |0 = No effect. + * | | |1 = Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[17] |RXRST |Receive Reset + * | | |0 = No effect. + * | | |1 = Reset the receive-related counters, state machine, and the content of receive shift register and data buffer. + * | | |Note 1: It is cleared automatically after one PCLK cycle. + * | | |Note 2: It is suggest to check the RXBUSY (USCI_PROTSTS[10]) before this bit will be set to 1. + * @var UUART_T::BUFSTS + * Offset: 0x3C USCI Transmit/Receive Buffer Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXEMPTY |Receive Buffer Empty Indicator + * | | |0 = Receive buffer is not empty. + * | | |1 = Receive buffer is empty. + * |[1] |RXFULL |Receive Buffer Full Indicator + * | | |0 = Receive buffer is not full. + * | | |1 = Receive buffer is full. + * |[3] |RXOVIF |Receive Buffer Over-run Error Interrupt Status + * | | |This bit indicates that a receive buffer overrun error event has been detected + * | | |If RXOVIEN (USCI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated + * | | |It is cleared by software writes 1 to this bit. + * | | |0 = A receive buffer overrun error event has not been detected. + * | | |1 = A receive buffer overrun error event has been detected. + * |[8] |TXEMPTY |Transmit Buffer Empty Indicator + * | | |0 = Transmit buffer is not empty. + * | | |1 = Transmit buffer is empty. + * |[9] |TXFULL |Transmit Buffer Full Indicator + * | | |0 = Transmit buffer is not full. + * | | |1 = Transmit buffer is full. + * @var UUART_T::PDMACTL + * Offset: 0x40 USCI PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PDMARST |PDMA Reset + * | | |0 = No effect. + * | | |1 = Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically. + * |[1] |TXPDMAEN |PDMA Transmit Channel Available + * | | |0 = Transmit PDMA function Disabled. + * | | |1 = Transmit PDMA function Enabled. + * |[2] |RXPDMAEN |PDMA Receive Channel Available + * | | |0 = Receive PDMA function Disabled. + * | | |1 = Receive PDMA function Enabled. + * |[3] |PDMAEN |PDMA Mode Enable Bit + * | | |0 = PDMA function Disabled. + * | | |1 = PDMA function Enabled. + * @var UUART_T::WKCTL + * Offset: 0x54 USCI Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Wake-up Enable Bit + * | | |0 = Wake-up function Disabled. + * | | |1 = Wake-up function Enabled. + * |[2] |PDBOPT |Power Down Blocking Option + * | | |0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately. + * | | |1 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately. + * @var UUART_T::WKSTS + * Offset: 0x58 USCI Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKF |Wake-up Flag + * | | |When chip is woken up from Power-down mode, this bit is set to 1 + * | | |Software can write 1 to clear this bit. + * @var UUART_T::PROTCTL + * Offset: 0x5C USCI Protocol Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |STOPB |Stop Bits + * | | |This bit defines the number of stop bits in an UART frame. + * | | |0 = The number of stop bits is 1. + * | | |1 = The number of stop bits is 2. + * |[1] |PARITYEN |Parity Enable Bit + * | | |This bit defines the parity bit is enabled in an UART frame. + * | | |0 = The parity bit Disabled. + * | | |1 = The parity bit Enabled. + * |[2] |EVENPARITY|Even Parity Enable Bit + * | | |0 = Odd number of logic 1's is transmitted and checked in each word. + * | | |1 = Even number of logic 1's is transmitted and checked in each word. + * | | |Note: This bit has effect only when PARITYEN is set. + * |[3] |RTSAUTOEN |nRTS Auto-flow Control Enable Bit + * | | |When nRTS auto-flow is enabled, if the receiver buffer is full (RXFULL (USCI_BUFSTS[1] = 1'b1)), the UART will de-assert nRTS signal. + * | | |0 = nRTS auto-flow control Disabled. + * | | |1 = nRTS auto-flow control Enabled. + * | | |Note: This bit has effect only when the RTSAUDIREN is not set. + * |[4] |CTSAUTOEN |nCTS Auto-flow Control Enable Bit + * | | |When nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted). + * | | |0 = nCTS auto-flow control Disabled. + * | | |1 = nCTS auto-flow control Enabled. + * |[5] |RTSAUDIREN|nRTS Auto Direction Enable Bit + * | | |When nRTS auto direction is enabled, if the transmitted bytes in the TX buffer is empty, the UART asserted nRTS signal automatically. + * | | |0 = nRTS auto direction control Disabled. + * | | |1 = nRTS auto direction control Enabled. + * | | |Note 1: This bit is used for nRTS auto direction control for RS485. + * | | |Note 2: This bit has effect only when the RTSAUTOEN is not set. + * |[6] |ABREN |Auto-baud Rate Detect Enable Bit + * | | |0 = Auto-baud rate detect function Disabled. + * | | |1 = Auto-baud rate detect function Enabled. + * | | |Note: When the auto - baud rate detect operation finishes, hardware will clear this bit + * | | |The associated interrupt ABRDETIF (USCI_PROTST[9]) will be generated (If ARBIEN (USCI_PROTIEN [1]) is enabled). + * |[9] |DATWKEN |Data Wake-up Mode Enable Bit + * | | |0 = Data wake-up mode Disabled. + * | | |1 = Data wake-up mode Enabled. + * |[10] |CTSWKEN |nCTS Wake-up Mode Enable Bit + * | | |0 = nCTS wake-up mode Disabled. + * | | |1 = nCTS wake-up mode Enabled. + * |[14:11] |WAKECNT |Wake-up Counter + * | | |These bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode. + * |[24:16] |BRDETITV |Baud Rate Detection Interval + * | | |This bit fields indicate how many clock cycle selected by TMCNTSRC (USCI_BRGEN [5]) does the slave calculates the baud rate in one bits + * | | |The order of the bus shall be 1 and 0 step by step (e.g. the input data pattern shall be 0x55) + * | | |The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (USCI_PROTCTL[9]) is set. + * | | |Note: This bit can be cleared to 0 by software writing '0' to the BRDETITV. + * |[26] |STICKEN |Stick Parity Enable Bit + * | | |0 = Stick parity Disabled. + * | | |1 = Stick parity Enabled. + * | | |Note: Refer to RS-485 Support section for detail information. + * |[29] |BCEN |Transmit Break Control Enable Bit + * | | |0 = Transmit Break Control Disabled. + * | | |1 = Transmit Break Control Enabled. + * | | |Note: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0) + * | | |This bit acts only on TX line and has no effect on the transmitter logic. + * |[31] |PROTEN |UART Protocol Enable Bit + * | | |0 = UART Protocol Disabled. + * | | |1 = UART Protocol Enabled. + * @var UUART_T::PROTIEN + * Offset: 0x60 USCI Protocol Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |ABRIEN |Auto-baud Rate Interrupt Enable Bit + * | | |0 = Auto-baud rate interrupt Disabled. + * | | |1 = Auto-baud rate interrupt Enabled. + * |[2] |RLSIEN |Receive Line Status Interrupt Enable Bit + * | | |0 = Receive line status interrupt Disabled. + * | | |1 = Receive line status interrupt Enabled. + * | | |Note: USCI_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt. + * @var UUART_T::PROTSTS + * Offset: 0x64 USCI Protocol Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TXSTIF |Transmit Start Interrupt Flag + * | | |0 = A transmit start interrupt status has not occurred. + * | | |1 = A transmit start interrupt status has occurred. + * | | |Note 1: It is cleared by software writing one into this bit. + * | | |Note 2: Used for user to load next transmit data when there is no data in transmit buffer. + * |[2] |TXENDIF |Transmit End Interrupt Flag + * | | |0 = A transmit end interrupt status has not occurred. + * | | |1 = A transmit end interrupt status has occurred. + * | | |Note: It is cleared by software writing one into this bit. + * |[3] |RXSTIF |Receive Start Interrupt Flag + * | | |0 = A receive start interrupt status has not occurred. + * | | |1 = A receive start interrupt status has occurred. + * | | |Note: It is cleared by software writing one into this bit. + * |[4] |RXENDIF |Receive End Interrupt Flag + * | | |0 = A receive finish interrupt status has not occurred. + * | | |1 = A receive finish interrupt status has occurred. + * | | |Note: It is cleared by software writing one into this bit. + * |[5] |PARITYERR |Parity Error Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'. + * | | |0 = No parity error is generated. + * | | |1 = Parity error is generated. + * | | |Note: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits. + * |[6] |FRMERR |Framing Error Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' + * | | |(that is, the stop bit following the last data bit or parity bit is detected as logic 0). + * | | |0 = No framing error is generated. + * | | |1 = Framing error is generated. + * | | |Note: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits. + * |[7] |BREAK |Break Flag + * | | |This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' + * | | |(logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). + * | | |0 = No Break is generated. + * | | |1 = Break is generated in the receiver bus. + * | | |Note: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits. + * |[9] |ABRDETIF |Auto-baud Rate Interrupt Flag + * | | |This bit is set when auto-baud rate detection is done among the falling edge of the input data + * | | |If the ABRIEN (USCI_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated + * | | |This bit can be set 4 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus. + * | | |0 = Auto-baud rate detect function is not done. + * | | |1 = One Bit auto-baud rate detect function is done. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[10] |RXBUSY |RX Bus Status Flag (Read Only) + * | | |This bit indicates the busy status of the receiver. + * | | |0 = The receiver is Idle. + * | | |1 = The receiver is BUSY. + * |[11] |ABERRSTS |Auto-baud Rate Error Status + * | | |This bit is set when auto-baud rate detection counter overrun + * | | |When the auto-baud rate counter overrun, the user shall revise the CLKDIV (USCI_BRGEN[25:16]) value and + * | | |enable ABREN (USCI_PROTCTL[6]) to detect the correct baud rate again. + * | | |0 = Auto-baud rate detect counter is not overrun. + * | | |1 = Auto-baud rate detect counter is overrun. + * | | |Note 1: This bit is set at the same time of ABRDETIF. + * | | |Note 2: This bit can be cleared by writing '1' to ABRDETIF or ABERRSTS. + * |[16] |CTSSYNCLV |nCTS Synchronized Level Status (Read Only) + * | | |This bit used to indicate the current status of the internal synchronized nCTS signal. + * | | |0 = The internal synchronized nCTS is low. + * | | |1 = The internal synchronized nCTS is high. + * |[17] |CTSLV |nCTS Pin Status (Read Only) + * | | |This bit used to monitor the current status of nCTS pin input. + * | | |0 = nCTS pin input is low level voltage logic state. + * | | |1 = nCTS pin input is high level voltage logic state. + */ + __IO uint32_t CTL; /*!< [0x0000] USCI Control Register */ + __IO uint32_t INTEN; /*!< [0x0004] USCI Interrupt Enable Register */ + __IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t DATIN0; /*!< [0x0010] USCI Input Data Signal Configuration Register 0 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[3]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CTLIN0; /*!< [0x0020] USCI Input Control Signal Configuration Register 0 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CLKIN; /*!< [0x0028] USCI Input Clock Signal Configuration Register */ + __IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */ + __IO uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */ + __IO uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */ + __IO uint32_t BUFCTL; /*!< [0x0038] USCI Transmit/Receive Buffer Control Register */ + __IO uint32_t BUFSTS; /*!< [0x003c] USCI Transmit/Receive Buffer Status Register */ + __IO uint32_t PDMACTL; /*!< [0x0040] USCI PDMA Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[4]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */ + __IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */ + __IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */ + __IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */ + __IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */ + +} UUART_T; + +/** + @addtogroup UUART_CONST UUART Bit Field Definition + Constant Definitions for UUART Controller +@{ */ + +#define UUART_CTL_FUNMODE_Pos (0) /*!< UUART_T::CTL: FUNMODE Position */ +#define UUART_CTL_FUNMODE_Msk (0x7ul << UUART_CTL_FUNMODE_Pos) /*!< UUART_T::CTL: FUNMODE Mask */ + +#define UUART_INTEN_TXSTIEN_Pos (1) /*!< UUART_T::INTEN: TXSTIEN Position */ +#define UUART_INTEN_TXSTIEN_Msk (0x1ul << UUART_INTEN_TXSTIEN_Pos) /*!< UUART_T::INTEN: TXSTIEN Mask */ + +#define UUART_INTEN_TXENDIEN_Pos (2) /*!< UUART_T::INTEN: TXENDIEN Position */ +#define UUART_INTEN_TXENDIEN_Msk (0x1ul << UUART_INTEN_TXENDIEN_Pos) /*!< UUART_T::INTEN: TXENDIEN Mask */ + +#define UUART_INTEN_RXSTIEN_Pos (3) /*!< UUART_T::INTEN: RXSTIEN Position */ +#define UUART_INTEN_RXSTIEN_Msk (0x1ul << UUART_INTEN_RXSTIEN_Pos) /*!< UUART_T::INTEN: RXSTIEN Mask */ + +#define UUART_INTEN_RXENDIEN_Pos (4) /*!< UUART_T::INTEN: RXENDIEN Position */ +#define UUART_INTEN_RXENDIEN_Msk (0x1ul << UUART_INTEN_RXENDIEN_Pos) /*!< UUART_T::INTEN: RXENDIEN Mask */ + +#define UUART_BRGEN_RCLKSEL_Pos (0) /*!< UUART_T::BRGEN: RCLKSEL Position */ +#define UUART_BRGEN_RCLKSEL_Msk (0x1ul << UUART_BRGEN_RCLKSEL_Pos) /*!< UUART_T::BRGEN: RCLKSEL Mask */ + +#define UUART_BRGEN_PTCLKSEL_Pos (1) /*!< UUART_T::BRGEN: PTCLKSEL Position */ +#define UUART_BRGEN_PTCLKSEL_Msk (0x1ul << UUART_BRGEN_PTCLKSEL_Pos) /*!< UUART_T::BRGEN: PTCLKSEL Mask */ + +#define UUART_BRGEN_SPCLKSEL_Pos (2) /*!< UUART_T::BRGEN: SPCLKSEL Position */ +#define UUART_BRGEN_SPCLKSEL_Msk (0x3ul << UUART_BRGEN_SPCLKSEL_Pos) /*!< UUART_T::BRGEN: SPCLKSEL Mask */ + +#define UUART_BRGEN_TMCNTEN_Pos (4) /*!< UUART_T::BRGEN: TMCNTEN Position */ +#define UUART_BRGEN_TMCNTEN_Msk (0x1ul << UUART_BRGEN_TMCNTEN_Pos) /*!< UUART_T::BRGEN: TMCNTEN Mask */ + +#define UUART_BRGEN_TMCNTSRC_Pos (5) /*!< UUART_T::BRGEN: TMCNTSRC Position */ +#define UUART_BRGEN_TMCNTSRC_Msk (0x1ul << UUART_BRGEN_TMCNTSRC_Pos) /*!< UUART_T::BRGEN: TMCNTSRC Mask */ + +#define UUART_BRGEN_PDSCNT_Pos (8) /*!< UUART_T::BRGEN: PDSCNT Position */ +#define UUART_BRGEN_PDSCNT_Msk (0x3ul << UUART_BRGEN_PDSCNT_Pos) /*!< UUART_T::BRGEN: PDSCNT Mask */ + +#define UUART_BRGEN_DSCNT_Pos (10) /*!< UUART_T::BRGEN: DSCNT Position */ +#define UUART_BRGEN_DSCNT_Msk (0x1ful << UUART_BRGEN_DSCNT_Pos) /*!< UUART_T::BRGEN: DSCNT Mask */ + +#define UUART_BRGEN_CLKDIV_Pos (16) /*!< UUART_T::BRGEN: CLKDIV Position */ +#define UUART_BRGEN_CLKDIV_Msk (0x3fful << UUART_BRGEN_CLKDIV_Pos) /*!< UUART_T::BRGEN: CLKDIV Mask */ + +#define UUART_DATIN0_SYNCSEL_Pos (0) /*!< UUART_T::DATIN0: SYNCSEL Position */ +#define UUART_DATIN0_SYNCSEL_Msk (0x1ul << UUART_DATIN0_SYNCSEL_Pos) /*!< UUART_T::DATIN0: SYNCSEL Mask */ + +#define UUART_DATIN0_ININV_Pos (2) /*!< UUART_T::DATIN0: ININV Position */ +#define UUART_DATIN0_ININV_Msk (0x1ul << UUART_DATIN0_ININV_Pos) /*!< UUART_T::DATIN0: ININV Mask */ + +#define UUART_DATIN0_EDGEDET_Pos (3) /*!< UUART_T::DATIN0: EDGEDET Position */ +#define UUART_DATIN0_EDGEDET_Msk (0x3ul << UUART_DATIN0_EDGEDET_Pos) /*!< UUART_T::DATIN0: EDGEDET Mask */ + +#define UUART_CTLIN0_SYNCSEL_Pos (0) /*!< UUART_T::CTLIN0: SYNCSEL Position */ +#define UUART_CTLIN0_SYNCSEL_Msk (0x1ul << UUART_CTLIN0_SYNCSEL_Pos) /*!< UUART_T::CTLIN0: SYNCSEL Mask */ + +#define UUART_CTLIN0_ININV_Pos (2) /*!< UUART_T::CTLIN0: ININV Position */ +#define UUART_CTLIN0_ININV_Msk (0x1ul << UUART_CTLIN0_ININV_Pos) /*!< UUART_T::CTLIN0: ININV Mask */ + +#define UUART_CLKIN_SYNCSEL_Pos (0) /*!< UUART_T::CLKIN: SYNCSEL Position */ +#define UUART_CLKIN_SYNCSEL_Msk (0x1ul << UUART_CLKIN_SYNCSEL_Pos) /*!< UUART_T::CLKIN: SYNCSEL Mask */ + +#define UUART_LINECTL_LSB_Pos (0) /*!< UUART_T::LINECTL: LSB Position */ +#define UUART_LINECTL_LSB_Msk (0x1ul << UUART_LINECTL_LSB_Pos) /*!< UUART_T::LINECTL: LSB Mask */ + +#define UUART_LINECTL_DATOINV_Pos (5) /*!< UUART_T::LINECTL: DATOINV Position */ +#define UUART_LINECTL_DATOINV_Msk (0x1ul << UUART_LINECTL_DATOINV_Pos) /*!< UUART_T::LINECTL: DATOINV Mask */ + +#define UUART_LINECTL_CTLOINV_Pos (7) /*!< UUART_T::LINECTL: CTLOINV Position */ +#define UUART_LINECTL_CTLOINV_Msk (0x1ul << UUART_LINECTL_CTLOINV_Pos) /*!< UUART_T::LINECTL: CTLOINV Mask */ + +#define UUART_LINECTL_DWIDTH_Pos (8) /*!< UUART_T::LINECTL: DWIDTH Position */ +#define UUART_LINECTL_DWIDTH_Msk (0xful << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_T::LINECTL: DWIDTH Mask */ + +#define UUART_TXDAT_TXDAT_Pos (0) /*!< UUART_T::TXDAT: TXDAT Position */ +#define UUART_TXDAT_TXDAT_Msk (0xfffful << UUART_TXDAT_TXDAT_Pos) /*!< UUART_T::TXDAT: TXDAT Mask */ + +#define UUART_RXDAT_RXDAT_Pos (0) /*!< UUART_T::RXDAT: RXDAT Position */ +#define UUART_RXDAT_RXDAT_Msk (0xfffful << UUART_RXDAT_RXDAT_Pos) /*!< UUART_T::RXDAT: RXDAT Mask */ + +#define UUART_BUFCTL_TXCLR_Pos (7) /*!< UUART_T::BUFCTL: TXCLR Position */ +#define UUART_BUFCTL_TXCLR_Msk (0x1ul << UUART_BUFCTL_TXCLR_Pos) /*!< UUART_T::BUFCTL: TXCLR Mask */ + +#define UUART_BUFCTL_RXOVIEN_Pos (14) /*!< UUART_T::BUFCTL: RXOVIEN Position */ +#define UUART_BUFCTL_RXOVIEN_Msk (0x1ul << UUART_BUFCTL_RXOVIEN_Pos) /*!< UUART_T::BUFCTL: RXOVIEN Mask */ + +#define UUART_BUFCTL_RXCLR_Pos (15) /*!< UUART_T::BUFCTL: RXCLR Position */ +#define UUART_BUFCTL_RXCLR_Msk (0x1ul << UUART_BUFCTL_RXCLR_Pos) /*!< UUART_T::BUFCTL: RXCLR Mask */ + +#define UUART_BUFCTL_TXRST_Pos (16) /*!< UUART_T::BUFCTL: TXRST Position */ +#define UUART_BUFCTL_TXRST_Msk (0x1ul << UUART_BUFCTL_TXRST_Pos) /*!< UUART_T::BUFCTL: TXRST Mask */ + +#define UUART_BUFCTL_RXRST_Pos (17) /*!< UUART_T::BUFCTL: RXRST Position */ +#define UUART_BUFCTL_RXRST_Msk (0x1ul << UUART_BUFCTL_RXRST_Pos) /*!< UUART_T::BUFCTL: RXRST Mask */ + +#define UUART_BUFSTS_RXEMPTY_Pos (0) /*!< UUART_T::BUFSTS: RXEMPTY Position */ +#define UUART_BUFSTS_RXEMPTY_Msk (0x1ul << UUART_BUFSTS_RXEMPTY_Pos) /*!< UUART_T::BUFSTS: RXEMPTY Mask */ + +#define UUART_BUFSTS_RXFULL_Pos (1) /*!< UUART_T::BUFSTS: RXFULL Position */ +#define UUART_BUFSTS_RXFULL_Msk (0x1ul << UUART_BUFSTS_RXFULL_Pos) /*!< UUART_T::BUFSTS: RXFULL Mask */ + +#define UUART_BUFSTS_RXOVIF_Pos (3) /*!< UUART_T::BUFSTS: RXOVIF Position */ +#define UUART_BUFSTS_RXOVIF_Msk (0x1ul << UUART_BUFSTS_RXOVIF_Pos) /*!< UUART_T::BUFSTS: RXOVIF Mask */ + +#define UUART_BUFSTS_TXEMPTY_Pos (8) /*!< UUART_T::BUFSTS: TXEMPTY Position */ +#define UUART_BUFSTS_TXEMPTY_Msk (0x1ul << UUART_BUFSTS_TXEMPTY_Pos) /*!< UUART_T::BUFSTS: TXEMPTY Mask */ + +#define UUART_BUFSTS_TXFULL_Pos (9) /*!< UUART_T::BUFSTS: TXFULL Position */ +#define UUART_BUFSTS_TXFULL_Msk (0x1ul << UUART_BUFSTS_TXFULL_Pos) /*!< UUART_T::BUFSTS: TXFULL Mask */ + +#define UUART_PDMACTL_PDMARST_Pos (0) /*!< UUART_T::PDMACTL: PDMARST Position */ +#define UUART_PDMACTL_PDMARST_Msk (0x1ul << UUART_PDMACTL_PDMARST_Pos) /*!< UUART_T::PDMACTL: PDMARST Mask */ + +#define UUART_PDMACTL_TXPDMAEN_Pos (1) /*!< UUART_T::PDMACTL: TXPDMAEN Position */ +#define UUART_PDMACTL_TXPDMAEN_Msk (0x1ul << UUART_PDMACTL_TXPDMAEN_Pos) /*!< UUART_T::PDMACTL: TXPDMAEN Mask */ + +#define UUART_PDMACTL_RXPDMAEN_Pos (2) /*!< UUART_T::PDMACTL: RXPDMAEN Position */ +#define UUART_PDMACTL_RXPDMAEN_Msk (0x1ul << UUART_PDMACTL_RXPDMAEN_Pos) /*!< UUART_T::PDMACTL: RXPDMAEN Mask */ + +#define UUART_PDMACTL_PDMAEN_Pos (3) /*!< UUART_T::PDMACTL: PDMAEN Position */ +#define UUART_PDMACTL_PDMAEN_Msk (0x1ul << UUART_PDMACTL_PDMAEN_Pos) /*!< UUART_T::PDMACTL: PDMAEN Mask */ + +#define UUART_WKCTL_WKEN_Pos (0) /*!< UUART_T::WKCTL: WKEN Position */ +#define UUART_WKCTL_WKEN_Msk (0x1ul << UUART_WKCTL_WKEN_Pos) /*!< UUART_T::WKCTL: WKEN Mask */ + +#define UUART_WKCTL_PDBOPT_Pos (2) /*!< UUART_T::WKCTL: PDBOPT Position */ +#define UUART_WKCTL_PDBOPT_Msk (0x1ul << UUART_WKCTL_PDBOPT_Pos) /*!< UUART_T::WKCTL: PDBOPT Mask */ + +#define UUART_WKSTS_WKF_Pos (0) /*!< UUART_T::WKSTS: WKF Position */ +#define UUART_WKSTS_WKF_Msk (0x1ul << UUART_WKSTS_WKF_Pos) /*!< UUART_T::WKSTS: WKF Mask */ + +#define UUART_PROTCTL_STOPB_Pos (0) /*!< UUART_T::PROTCTL: STOPB Position */ +#define UUART_PROTCTL_STOPB_Msk (0x1ul << UUART_PROTCTL_STOPB_Pos) /*!< UUART_T::PROTCTL: STOPB Mask */ + +#define UUART_PROTCTL_PARITYEN_Pos (1) /*!< UUART_T::PROTCTL: PARITYEN Position */ +#define UUART_PROTCTL_PARITYEN_Msk (0x1ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_T::PROTCTL: PARITYEN Mask */ + +#define UUART_PROTCTL_EVENPARITY_Pos (2) /*!< UUART_T::PROTCTL: EVENPARITY Position */ +#define UUART_PROTCTL_EVENPARITY_Msk (0x1ul << UUART_PROTCTL_EVENPARITY_Pos) /*!< UUART_T::PROTCTL: EVENPARITY Mask */ + +#define UUART_PROTCTL_RTSAUTOEN_Pos (3) /*!< UUART_T::PROTCTL: RTSAUTOEN Position */ +#define UUART_PROTCTL_RTSAUTOEN_Msk (0x1ul << UUART_PROTCTL_RTSAUTOEN_Pos) /*!< UUART_T::PROTCTL: RTSAUTOEN Mask */ + +#define UUART_PROTCTL_CTSAUTOEN_Pos (4) /*!< UUART_T::PROTCTL: CTSAUTOEN Position */ +#define UUART_PROTCTL_CTSAUTOEN_Msk (0x1ul << UUART_PROTCTL_CTSAUTOEN_Pos) /*!< UUART_T::PROTCTL: CTSAUTOEN Mask */ + +#define UUART_PROTCTL_RTSAUDIREN_Pos (5) /*!< UUART_T::PROTCTL: RTSAUDIREN Position */ +#define UUART_PROTCTL_RTSAUDIREN_Msk (0x1ul << UUART_PROTCTL_RTSAUDIREN_Pos) /*!< UUART_T::PROTCTL: RTSAUDIREN Mask */ + +#define UUART_PROTCTL_ABREN_Pos (6) /*!< UUART_T::PROTCTL: ABREN Position */ +#define UUART_PROTCTL_ABREN_Msk (0x1ul << UUART_PROTCTL_ABREN_Pos) /*!< UUART_T::PROTCTL: ABREN Mask */ + +#define UUART_PROTCTL_DATWKEN_Pos (9) /*!< UUART_T::PROTCTL: DATWKEN Position */ +#define UUART_PROTCTL_DATWKEN_Msk (0x1ul << UUART_PROTCTL_DATWKEN_Pos) /*!< UUART_T::PROTCTL: DATWKEN Mask */ + +#define UUART_PROTCTL_CTSWKEN_Pos (10) /*!< UUART_T::PROTCTL: CTSWKEN Position */ +#define UUART_PROTCTL_CTSWKEN_Msk (0x1ul << UUART_PROTCTL_CTSWKEN_Pos) /*!< UUART_T::PROTCTL: CTSWKEN Mask */ + +#define UUART_PROTCTL_WAKECNT_Pos (11) /*!< UUART_T::PROTCTL: WAKECNT Position */ +#define UUART_PROTCTL_WAKECNT_Msk (0xful << UUART_PROTCTL_WAKECNT_Pos) /*!< UUART_T::PROTCTL: WAKECNT Mask */ + +#define UUART_PROTCTL_BRDETITV_Pos (16) /*!< UUART_T::PROTCTL: BRDETITV Position */ +#define UUART_PROTCTL_BRDETITV_Msk (0x1fful << UUART_PROTCTL_BRDETITV_Pos) /*!< UUART_T::PROTCTL: BRDETITV Mask */ + +#define UUART_PROTCTL_STICKEN_Pos (26) /*!< UUART_T::PROTCTL: STICKEN Position */ +#define UUART_PROTCTL_STICKEN_Msk (0x1ul << UUART_PROTCTL_STICKEN_Pos) /*!< UUART_T::PROTCTL: STICKEN Mask */ + +#define UUART_PROTCTL_BCEN_Pos (29) /*!< UUART_T::PROTCTL: BCEN Position */ +#define UUART_PROTCTL_BCEN_Msk (0x1ul << UUART_PROTCTL_BCEN_Pos) /*!< UUART_T::PROTCTL: BCEN Mask */ + +#define UUART_PROTCTL_PROTEN_Pos (31) /*!< UUART_T::PROTCTL: PROTEN Position */ +#define UUART_PROTCTL_PROTEN_Msk (0x1ul << UUART_PROTCTL_PROTEN_Pos) /*!< UUART_T::PROTCTL: PROTEN Mask */ + +#define UUART_PROTIEN_ABRIEN_Pos (1) /*!< UUART_T::PROTIEN: ABRIEN Position */ +#define UUART_PROTIEN_ABRIEN_Msk (0x1ul << UUART_PROTIEN_ABRIEN_Pos) /*!< UUART_T::PROTIEN: ABRIEN Mask */ + +#define UUART_PROTIEN_RLSIEN_Pos (2) /*!< UUART_T::PROTIEN: RLSIEN Position */ +#define UUART_PROTIEN_RLSIEN_Msk (0x1ul << UUART_PROTIEN_RLSIEN_Pos) /*!< UUART_T::PROTIEN: RLSIEN Mask */ + +#define UUART_PROTSTS_TXSTIF_Pos (1) /*!< UUART_T::PROTSTS: TXSTIF Position */ +#define UUART_PROTSTS_TXSTIF_Msk (0x1ul << UUART_PROTSTS_TXSTIF_Pos) /*!< UUART_T::PROTSTS: TXSTIF Mask */ + +#define UUART_PROTSTS_TXENDIF_Pos (2) /*!< UUART_T::PROTSTS: TXENDIF Position */ +#define UUART_PROTSTS_TXENDIF_Msk (0x1ul << UUART_PROTSTS_TXENDIF_Pos) /*!< UUART_T::PROTSTS: TXENDIF Mask */ + +#define UUART_PROTSTS_RXSTIF_Pos (3) /*!< UUART_T::PROTSTS: RXSTIF Position */ +#define UUART_PROTSTS_RXSTIF_Msk (0x1ul << UUART_PROTSTS_RXSTIF_Pos) /*!< UUART_T::PROTSTS: RXSTIF Mask */ + +#define UUART_PROTSTS_RXENDIF_Pos (4) /*!< UUART_T::PROTSTS: RXENDIF Position */ +#define UUART_PROTSTS_RXENDIF_Msk (0x1ul << UUART_PROTSTS_RXENDIF_Pos) /*!< UUART_T::PROTSTS: RXENDIF Mask */ + +#define UUART_PROTSTS_PARITYERR_Pos (5) /*!< UUART_T::PROTSTS: PARITYERR Position */ +#define UUART_PROTSTS_PARITYERR_Msk (0x1ul << UUART_PROTSTS_PARITYERR_Pos) /*!< UUART_T::PROTSTS: PARITYERR Mask */ + +#define UUART_PROTSTS_FRMERR_Pos (6) /*!< UUART_T::PROTSTS: FRMERR Position */ +#define UUART_PROTSTS_FRMERR_Msk (0x1ul << UUART_PROTSTS_FRMERR_Pos) /*!< UUART_T::PROTSTS: FRMERR Mask */ + +#define UUART_PROTSTS_BREAK_Pos (7) /*!< UUART_T::PROTSTS: BREAK Position */ +#define UUART_PROTSTS_BREAK_Msk (0x1ul << UUART_PROTSTS_BREAK_Pos) /*!< UUART_T::PROTSTS: BREAK Mask */ + +#define UUART_PROTSTS_ABRDETIF_Pos (9) /*!< UUART_T::PROTSTS: ABRDETIF Position */ +#define UUART_PROTSTS_ABRDETIF_Msk (0x1ul << UUART_PROTSTS_ABRDETIF_Pos) /*!< UUART_T::PROTSTS: ABRDETIF Mask */ + +#define UUART_PROTSTS_RXBUSY_Pos (10) /*!< UUART_T::PROTSTS: RXBUSY Position */ +#define UUART_PROTSTS_RXBUSY_Msk (0x1ul << UUART_PROTSTS_RXBUSY_Pos) /*!< UUART_T::PROTSTS: RXBUSY Mask */ + +#define UUART_PROTSTS_ABERRSTS_Pos (11) /*!< UUART_T::PROTSTS: ABERRSTS Position */ +#define UUART_PROTSTS_ABERRSTS_Msk (0x1ul << UUART_PROTSTS_ABERRSTS_Pos) /*!< UUART_T::PROTSTS: ABERRSTS Mask */ + +#define UUART_PROTSTS_CTSSYNCLV_Pos (16) /*!< UUART_T::PROTSTS: CTSSYNCLV Position */ +#define UUART_PROTSTS_CTSSYNCLV_Msk (0x1ul << UUART_PROTSTS_CTSSYNCLV_Pos) /*!< UUART_T::PROTSTS: CTSSYNCLV Mask */ + +#define UUART_PROTSTS_CTSLV_Pos (17) /*!< UUART_T::PROTSTS: CTSLV Position */ +#define UUART_PROTSTS_CTSLV_Msk (0x1ul << UUART_PROTSTS_CTSLV_Pos) /*!< UUART_T::PROTSTS: CTSLV Mask */ + +/**@}*/ /* UUART_CONST */ +/**@}*/ /* end of UUART register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __UUART_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/wdt_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/wdt_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..2bead168677f5eb7391df802d1839e7af3ce2b14 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/wdt_reg.h @@ -0,0 +1,183 @@ +/**************************************************************************//** + * @file wdt_reg.h + * @version V1.00 + * @brief WDT register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __WDT_REG_H__ +#define __WDT_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup WDT Watch Dog Timer Controller(WDT) + Memory Mapped Structure for WDT Controller +@{ */ + +typedef struct +{ + + + /** + * @var WDT_T::CTL + * Offset: 0x00 WDT Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RSTCNT |Reset WDT Up Counter (Write Protect) + * | | |0 = No effect. + * | | |1 = Reset the internal 18-bit WDT up counter value. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: This bit will be automatically cleared by hardware. + * |[1] |RSTEN |WDT Time-out Reset Enable Control (Write Protect) + * | | |Setting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires. + * | | |0 = WDT time-out reset function Disabled. + * | | |1 = WDT time-out reset function Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[2] |RSTF |WDT Time-out Reset Flag + * | | |This bit indicates the system has been reset by WDT time-out reset or not. + * | | |0 = WDT time-out reset did not occur. + * | | |1 = WDT time-out reset occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * |[3] |IF |WDT Time-out Interrupt Flag + * | | |This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval + * | | |0 = WDT time-out interrupt did not occur. + * | | |1 = WDT time-out interrupt occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * |[4] |WKEN |WDT Time-out Wake-up Function Control (Write Protect) + * | | |If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip. + * | | |0 = Wake-up trigger event Disabled if WDT time-out interrupt signal generated. + * | | |1 = Wake-up trigger event Enabled if WDT time-out interrupt signal generated. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz internal low speed RC oscillator (LIRC) or LXT. + * |[5] |WKF |WDT Time-out Wake-up Flag (Write Protect) + * | | |This bit indicates the interrupt wake-up flag status of WDT + * | | |0 = WDT does not cause chip wake-up. + * | | |1 = Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: This bit is cleared by writing 1 to it. + * |[6] |INTEN |WDT Time-out Interrupt Enable Control (Write Protect) + * | | |If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU. + * | | |0 = WDT time-out interrupt Disabled. + * | | |1 = WDT time-out interrupt Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7] |WDTEN |WDT Enable Control (Write Protect) + * | | |0 = WDT Disabled (This action will reset the internal up counter value). + * | | |1 = WDT Enabled. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configure to 111, this bit is forced as 1 and user cannot change this bit to 0. + * |[10:8] |TOUTSEL |WDT Time-out Interval Selection (Write Protect) + * | | |These three bits select the time-out interval period for the WDT. + * | | |000 = 24 * WDT_CLK. + * | | |001 = 26 * WDT_CLK. + * | | |010 = 28 * WDT_CLK. + * | | |011 = 210 * WDT_CLK. + * | | |100 = 212 * WDT_CLK. + * | | |101 = 214 * WDT_CLK. + * | | |110 = 216 * WDT_CLK. + * | | |111 = 218 * WDT_CLK. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[30] |SYNC |WDT Enable Control SYNC Flag Indicator (Read Only) + * | | |If user execute enable/disable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is completed or not. + * | | |0 = Set WDTEN bit is completed. + * | | |1 = Set WDTEN bit is synchronizing and not become active yet.. + * | | |Note: Perform enable or disable WDTEN bit needs 2 * WDT_CLK period to become active. + * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control (Write Protect) + * | | |0 = ICE debug mode acknowledgement affects WDT counting. + * | | |WDT up counter will be held while CPU is held by ICE. + * | | |1 = ICE debug mode acknowledgement Disabled. + * | | |WDT up counter will keep going no matter CPU is held by ICE or not. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var WDT_T::ALTCTL + * Offset: 0x04 WDT Alternative Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |RSTDSEL |WDT Reset Delay Selection (Write Protect) + * | | |When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by setting RSTCNT (WDT_CTL[0]) to prevent WDT time-out reset happened + * | | |User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period. + * | | |00 = WDT Reset Delay Period is 1026 * WDT_CLK. + * | | |01 = WDT Reset Delay Period is 130 * WDT_CLK. + * | | |10 = WDT Reset Delay Period is 18 * WDT_CLK. + * | | |11 = WDT Reset Delay Period is 3 * WDT_CLK. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: This register will be reset to 0 if WDT time-out reset happened. + * @var WDT_T::RSTCNT + * Offset: 0x08 WDT Reset Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RSTCNT |WDT Reset Counter Register + * | | |Writing 0x00005AA5 to this field will reset the internal 18-bit WDT up counter value to 0. + * | | |Note: Perform RSTCNT to reset counter needs 2 * WDT_CLK period to become active. + * | | |Note: RSTCNT (WDT_CTL[0]) bit is a write protected bit + * | | |RSTCNT (WDT_RSTCNT[31:0]) bits are not write protected. + */ + __IO uint32_t CTL; /*!< [0x0000] WDT Control Register */ + __IO uint32_t ALTCTL; /*!< [0x0004] WDT Alternative Control Register */ + __O uint32_t RSTCNT; /*!< [0x0008] WDT Reset Counter Register */ + +} WDT_T; + +/** + @addtogroup WDT_CONST WDT Bit Field Definition + Constant Definitions for WDT Controller +@{ */ + +#define WDT_CTL_RSTCNT_Pos (0) /*!< WDT_T::CTL: RSTCNT Position */ +#define WDT_CTL_RSTCNT_Msk (0x1ul << WDT_CTL_RSTCNT_Pos) /*!< WDT_T::CTL: RSTCNT Mask */ + +#define WDT_CTL_RSTEN_Pos (1) /*!< WDT_T::CTL: RSTEN Position */ +#define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos) /*!< WDT_T::CTL: RSTEN Mask */ + +#define WDT_CTL_RSTF_Pos (2) /*!< WDT_T::CTL: RSTF Position */ +#define WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos) /*!< WDT_T::CTL: RSTF Mask */ + +#define WDT_CTL_IF_Pos (3) /*!< WDT_T::CTL: IF Position */ +#define WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos) /*!< WDT_T::CTL: IF Mask */ + +#define WDT_CTL_WKEN_Pos (4) /*!< WDT_T::CTL: WKEN Position */ +#define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos) /*!< WDT_T::CTL: WKEN Mask */ + +#define WDT_CTL_WKF_Pos (5) /*!< WDT_T::CTL: WKF Position */ +#define WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos) /*!< WDT_T::CTL: WKF Mask */ + +#define WDT_CTL_INTEN_Pos (6) /*!< WDT_T::CTL: INTEN Position */ +#define WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos) /*!< WDT_T::CTL: INTEN Mask */ + +#define WDT_CTL_WDTEN_Pos (7) /*!< WDT_T::CTL: WDTEN Position */ +#define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos) /*!< WDT_T::CTL: WDTEN Mask */ + +#define WDT_CTL_TOUTSEL_Pos (8) /*!< WDT_T::CTL: TOUTSEL Position */ +#define WDT_CTL_TOUTSEL_Msk (0x7ul << WDT_CTL_TOUTSEL_Pos) /*!< WDT_T::CTL: TOUTSEL Mask */ + +#define WDT_CTL_SYNC_Pos (30) /*!< WDT_T::CTL: SYNC Position */ +#define WDT_CTL_SYNC_Msk (0x1ul << WDT_CTL_SYNC_Pos) /*!< WDT_T::CTL: SYNC Mask */ + +#define WDT_CTL_ICEDEBUG_Pos (31) /*!< WDT_T::CTL: ICEDEBUG Position */ +#define WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos) /*!< WDT_T::CTL: ICEDEBUG Mask */ + +#define WDT_ALTCTL_RSTDSEL_Pos (0) /*!< WDT_T::ALTCTL: RSTDSEL Position */ +#define WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT_T::ALTCTL: RSTDSEL Mask */ + +#define WDT_RSTCNT_RSTCNT_Pos (0) /*!< WDT_T::RSTCNT: RSTCNT Position */ +#define WDT_RSTCNT_RSTCNT_Msk (0xfffffffful << WDT_RSTCNT_RSTCNT_Pos) /*!< WDT_T::RSTCNT: RSTCNT Mask */ + +/**@}*/ /* WDT_CONST */ +/**@}*/ /* end of WDT register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __WDT_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/wwdt_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/wwdt_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..67f5748826a7c2411d6de30bd702cdb16bbaa591 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/wwdt_reg.h @@ -0,0 +1,149 @@ +/**************************************************************************//** + * @file wwdt_reg.h + * @version V1.00 + * @brief WWDT register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __WWDT_REG_H__ +#define __WWDT_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup WWDT Window Watchdog Timer(WWDT) + Memory Mapped Structure for WWDT Controller +@{ */ + +typedef struct +{ + + + /** + * @var WWDT_T::RLDCNT + * Offset: 0x00 WWDT Reload Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RLDCNT |WWDT Reload Counter Register + * | | |Writing 0x00005AA5 to this register will reload the WWDT counter value to 0x3F. + * | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT (WWDT_CTL[21:16]) + * | | |If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT , WWDT reset signal will generate immediately. + * @var WWDT_T::CTL + * Offset: 0x04 WWDT Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WWDTEN |WWDT Enable Control Bit + * | | |Set this bit to enable WWDT counter counting. + * | | |0 = WWDT counter is stopped. + * | | |1 = WWDT counter is starting counting. + * |[1] |INTEN |WWDT Interrupt Enable Control Bit + * | | |If this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU. + * | | |0 = WWDT counter compare match interrupt Disabled. + * | | |1 = WWDT counter compare match interrupt Enabled. + * |[11:8] |PSCSEL |WWDT Counter Prescale Period Selection + * | | |0000 = Pre-scale is 1; Max time-out period is 1 * 64 * WWDT_CLK. + * | | |0001 = Pre-scale is 2; Max time-out period is 2 * 64 * WWDT_CLK. + * | | |0010 = Pre-scale is 4; Max time-out period is 4 * 64 * WWDT_CLK. + * | | |0011 = Pre-scale is 8; Max time-out period is 8 * 64 * WWDT_CLK. + * | | |0100 = Pre-scale is 16; Max time-out period is 16 * 64 * WWDT_CLK. + * | | |0101 = Pre-scale is 32; Max time-out period is 32 * 64 * WWDT_CLK. + * | | |0110 = Pre-scale is 64; Max time-out period is 64 * 64 * WWDT_CLK. + * | | |0111 = Pre-scale is 128; Max time-out period is 128 * 64 * WWDT_CLK. + * | | |1000 = Pre-scale is 192; Max time-out period is 192 * 64 * WWDT_CLK. + * | | |1001 = Pre-scale is 256; Max time-out period is 256 * 64 * WWDT_CLK. + * | | |1010 = Pre-scale is 384; Max time-out period is 384 * 64 * WWDT_CLK. + * | | |1011 = Pre-scale is 512; Max time-out period is 512 * 64 * WWDT_CLK. + * | | |1100 = Pre-scale is 768; Max time-out period is 768 * 64 * WWDT_CLK. + * | | |1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * WWDT_CLK. + * | | |1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * WWDT_CLK. + * | | |1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * WWDT_CLK. + * |[21:16] |CMPDAT |WWDT Window Compare Register + * | | |Set this register to adjust the valid reload window. + * | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT + * | | |If user writes WWDT_RLDCNT register when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately. + * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control + * | | |0 = ICE debug mode acknowledgement effects WWDT counting. + * | | |WWDT down counter will be held while CPU is held by ICE. + * | | |1 = ICE debug mode acknowledgement Disabled. + * | | |WWDT down counter will keep going no matter CPU is held by ICE or not. + * @var WWDT_T::STATUS + * Offset: 0x08 WWDT Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WWDTIF |WWDT Compare Match Interrupt Flag + * | | |This bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]). + * | | |0 = No effect. + * | | |1 = WWDT counter value matches CMPDAT. + * | | |Note: This bit is cleared by writing 1 to it. + * |[1] |WWDTRF |WWDT Timer-out Reset Flag + * | | |This bit indicates the system has been reset by WWDT time-out reset or not. + * | | |0 = WWDT time-out reset did not occur. + * | | |1 = WWDT time-out reset occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * @var WWDT_T::CNT + * Offset: 0x0C WWDT Counter Value Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |CNTDAT |WWDT Counter Value + * | | |CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value. + */ + __O uint32_t RLDCNT; /*!< [0x0000] WWDT Reload Counter Register */ + __IO uint32_t CTL; /*!< [0x0004] WWDT Control Register */ + __IO uint32_t STATUS; /*!< [0x0008] WWDT Status Register */ + __I uint32_t CNT; /*!< [0x000c] WWDT Counter Value Register */ + +} WWDT_T; + +/** + @addtogroup WWDT_CONST WWDT Bit Field Definition + Constant Definitions for WWDT Controller +@{ */ + +#define WWDT_RLDCNT_RLDCNT_Pos (0) /*!< WWDT_T::RLDCNT: RLDCNT Position */ +#define WWDT_RLDCNT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_RLDCNT_Pos) /*!< WWDT_T::RLDCNT: RLDCNT Mask */ + +#define WWDT_CTL_WWDTEN_Pos (0) /*!< WWDT_T::CTL: WWDTEN Position */ +#define WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos) /*!< WWDT_T::CTL: WWDTEN Mask */ + +#define WWDT_CTL_INTEN_Pos (1) /*!< WWDT_T::CTL: INTEN Position */ +#define WWDT_CTL_INTEN_Msk (0x1ul << WWDT_CTL_INTEN_Pos) /*!< WWDT_T::CTL: INTEN Mask */ + +#define WWDT_CTL_PSCSEL_Pos (8) /*!< WWDT_T::CTL: PSCSEL Position */ +#define WWDT_CTL_PSCSEL_Msk (0xful << WWDT_CTL_PSCSEL_Pos) /*!< WWDT_T::CTL: PSCSEL Mask */ + +#define WWDT_CTL_CMPDAT_Pos (16) /*!< WWDT_T::CTL: CMPDAT Position */ +#define WWDT_CTL_CMPDAT_Msk (0x3ful << WWDT_CTL_CMPDAT_Pos) /*!< WWDT_T::CTL: CMPDAT Mask */ + +#define WWDT_CTL_ICEDEBUG_Pos (31) /*!< WWDT_T::CTL: ICEDEBUG Position */ +#define WWDT_CTL_ICEDEBUG_Msk (0x1ul << WWDT_CTL_ICEDEBUG_Pos) /*!< WWDT_T::CTL: ICEDEBUG Mask */ + +#define WWDT_STATUS_WWDTIF_Pos (0) /*!< WWDT_T::STATUS: WWDTIF Position */ +#define WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos) /*!< WWDT_T::STATUS: WWDTIF Mask */ + +#define WWDT_STATUS_WWDTRF_Pos (1) /*!< WWDT_T::STATUS: WWDTRF Position */ +#define WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos) /*!< WWDT_T::STATUS: WWDTRF Mask */ + +#define WWDT_CNT_CNTDAT_Pos (0) /*!< WWDT_T::CNT: CNTDAT Position */ +#define WWDT_CNT_CNTDAT_Msk (0x3ful << WWDT_CNT_CNTDAT_Pos) /*!< WWDT_T::CNT: CNTDAT Mask */ + +/**@}*/ /* WWDT_CONST */ +/**@}*/ /* end of WWDT register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __WWDT_REG_H__ */ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Source/ARM/startup_M480.s b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Source/ARM/startup_M480.s new file mode 100644 index 0000000000000000000000000000000000000000..3e31df75cb587f72ef8b1449fe9a3feb7c1c588c --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Source/ARM/startup_M480.s @@ -0,0 +1,514 @@ +;/****************************************************************************** +; * @file startup_M480.s +; * @version V1.00 +; * @brief CMSIS Cortex-M4 Core Device Startup File for M480 +; * +; * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. +;*****************************************************************************/ +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + + IF :LNOT: :DEF: Stack_Size +Stack_Size EQU 0x00000800 + ENDIF + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + + IF :LNOT: :DEF: Heap_Size +Heap_Size EQU 0x00000100 + ENDIF + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD BOD_IRQHandler ; 0: Brown Out detection + DCD IRC_IRQHandler ; 1: Internal RC + DCD PWRWU_IRQHandler ; 2: Power down wake up + DCD RAMPE_IRQHandler ; 3: RAM parity error + DCD CKFAIL_IRQHandler ; 4: Clock detection fail + DCD Default_Handler ; 5: Reserved + DCD RTC_IRQHandler ; 6: Real Time Clock + DCD TAMPER_IRQHandler ; 7: Tamper detection + DCD WDT_IRQHandler ; 8: Watchdog timer + DCD WWDT_IRQHandler ; 9: Window watchdog timer + DCD EINT0_IRQHandler ; 10: External Input 0 + DCD EINT1_IRQHandler ; 11: External Input 1 + DCD EINT2_IRQHandler ; 12: External Input 2 + DCD EINT3_IRQHandler ; 13: External Input 3 + DCD EINT4_IRQHandler ; 14: External Input 4 + DCD EINT5_IRQHandler ; 15: External Input 5 + DCD GPA_IRQHandler ; 16: GPIO Port A + DCD GPB_IRQHandler ; 17: GPIO Port B + DCD GPC_IRQHandler ; 18: GPIO Port C + DCD GPD_IRQHandler ; 19: GPIO Port D + DCD GPE_IRQHandler ; 20: GPIO Port E + DCD GPF_IRQHandler ; 21: GPIO Port F + DCD QSPI0_IRQHandler ; 22: QSPI0 + DCD SPI0_IRQHandler ; 23: SPI0 + DCD BRAKE0_IRQHandler ; 24: + DCD EPWM0P0_IRQHandler ; 25: + DCD EPWM0P1_IRQHandler ; 26: + DCD EPWM0P2_IRQHandler ; 27: + DCD BRAKE1_IRQHandler ; 28: + DCD EPWM1P0_IRQHandler ; 29: + DCD EPWM1P1_IRQHandler ; 30: + DCD EPWM1P2_IRQHandler ; 31: + DCD TMR0_IRQHandler ; 32: Timer 0 + DCD TMR1_IRQHandler ; 33: Timer 1 + DCD TMR2_IRQHandler ; 34: Timer 2 + DCD TMR3_IRQHandler ; 35: Timer 3 + DCD UART0_IRQHandler ; 36: UART0 + DCD UART1_IRQHandler ; 37: UART1 + DCD I2C0_IRQHandler ; 38: I2C0 + DCD I2C1_IRQHandler ; 39: I2C1 + DCD PDMA_IRQHandler ; 40: Peripheral DMA + DCD DAC_IRQHandler ; 41: DAC + DCD EADC00_IRQHandler ; 42: EADC0 interrupt source 0 + DCD EADC01_IRQHandler ; 43: EADC0 interrupt source 1 + DCD ACMP01_IRQHandler ; 44: ACMP0 and ACMP1 + DCD Default_Handler ; 45: Reserved + DCD EADC02_IRQHandler ; 46: EADC0 interrupt source 2 + DCD EADC03_IRQHandler ; 47: EADC0 interrupt source 3 + DCD UART2_IRQHandler ; 48: UART2 + DCD UART3_IRQHandler ; 49: UART3 + DCD QSPI1_IRQHandler ; 50: QSPI1 + DCD SPI1_IRQHandler ; 51: SPI1 + DCD SPI2_IRQHandler ; 52: SPI2 + DCD USBD_IRQHandler ; 53: USB device + DCD OHCI_IRQHandler ; 54: OHCI + DCD USBOTG_IRQHandler ; 55: USB OTG + DCD CAN0_IRQHandler ; 56: CAN0 + DCD CAN1_IRQHandler ; 57: CAN1 + DCD SC0_IRQHandler ; 58: + DCD SC1_IRQHandler ; 59: + DCD SC2_IRQHandler ; 60: + DCD Default_Handler ; 61: + DCD SPI3_IRQHandler ; 62: SPI3 + DCD Default_Handler ; 63: + DCD SDH0_IRQHandler ; 64: SDH0 + DCD USBD20_IRQHandler ; 65: USBD20 + DCD EMAC_TX_IRQHandler ; 66: EMAC_TX + DCD EMAC_RX_IRQHandler ; 67: EMAX_RX + DCD I2S0_IRQHandler ; 68: I2S0 + DCD Default_Handler ; 69: ToDo: Add description to this Interrupt + DCD OPA0_IRQHandler ; 70: OPA0 + DCD CRYPTO_IRQHandler ; 71: CRYPTO + DCD GPG_IRQHandler ; 72: + DCD EINT6_IRQHandler ; 73: + DCD UART4_IRQHandler ; 74: UART4 + DCD UART5_IRQHandler ; 75: UART5 + DCD USCI0_IRQHandler ; 76: USCI0 + DCD USCI1_IRQHandler ; 77: USCI1 + DCD BPWM0_IRQHandler ; 78: BPWM0 + DCD BPWM1_IRQHandler ; 79: BPWM1 + DCD SPIM_IRQHandler ; 80: SPIM + DCD CCAP_IRQHandler ; 81: CCAP + DCD I2C2_IRQHandler ; 82: I2C2 + DCD Default_Handler ; 83: + DCD QEI0_IRQHandler ; 84: QEI0 + DCD QEI1_IRQHandler ; 85: QEI1 + DCD ECAP0_IRQHandler ; 86: ECAP0 + DCD ECAP1_IRQHandler ; 87: ECAP1 + DCD GPH_IRQHandler ; 88: + DCD EINT7_IRQHandler ; 89: + DCD SDH1_IRQHandler ; 90: SDH1 + DCD Default_Handler ; 91: + DCD EHCI_IRQHandler ; 92: EHCI + DCD USBOTG20_IRQHandler ; 93: + DCD Default_Handler ; 94: + DCD Default_Handler ; 95: + DCD Default_Handler ; 96: + DCD Default_Handler ; 97: + DCD Default_Handler ; 98: + DCD Default_Handler ; 99: + DCD Default_Handler ; 100: + DCD TRNG_IRQHandler ; 101: TRNG + DCD UART6_IRQHandler ; 102: UART6 + DCD UART7_IRQHandler ; 103: UART7 + DCD EADC10_IRQHandler ; 104: EADC1 interrupt source 0 + DCD EADC11_IRQHandler ; 105: EADC1 interrupt source 1 + DCD EADC12_IRQHandler ; 106: EADC1 interrupt source 2 + DCD EADC13_IRQHandler ; 107: EADC1 interrupt source 3 + DCD CAN2_IRQHandler ; 108: CAN2 + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + ; Unlock Register + LDR R0, =0x40000100 + LDR R1, =0x59 + STR R1, [R0] + LDR R1, =0x16 + STR R1, [R0] + LDR R1, =0x88 + STR R1, [R0] + + IF :LNOT: :DEF: ENABLE_SPIM_CACHE + LDR R0, =0x40000200 ; R0 = Clock Controller Register Base Address + LDR R1, [R0,#0x4] ; R1 = 0x40000204 (AHBCLK) + ORR R1, R1, #0x4000 + STR R1, [R0,#0x4] ; CLK->AHBCLK |= CLK_AHBCLK_SPIMCKEN_Msk; + + LDR R0, =0x40007000 ; R0 = SPIM Register Base Address + LDR R1, [R0,#4] ; R1 = SPIM->CTL1 + ORR R1, R1,#2 ; R1 |= SPIM_CTL1_CACHEOFF_Msk + STR R1, [R0,#4] ; _SPIM_DISABLE_CACHE() + LDR R1, [R0,#4] ; R1 = SPIM->CTL1 + ORR R1, R1, #4 ; R1 |= SPIM_CTL1_CCMEN_Msk + STR R1, [R0,#4] ; _SPIM_ENABLE_CCM() + ENDIF + + LDR R0, =SystemInit + BLX R0 + + ; Init POR + ; LDR R2, =0x40000024 + ; LDR R1, =0x00005AA5 + ; STR R1, [R2] + + ; Lock + LDR R0, =0x40000100 + LDR R1, =0 + STR R1, [R0] + + LDR R0, =__main + BX R0 + + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT BOD_IRQHandler [WEAK] + EXPORT IRC_IRQHandler [WEAK] + EXPORT PWRWU_IRQHandler [WEAK] + EXPORT RAMPE_IRQHandler [WEAK] + EXPORT CKFAIL_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + EXPORT WWDT_IRQHandler [WEAK] + EXPORT EINT0_IRQHandler [WEAK] + EXPORT EINT1_IRQHandler [WEAK] + EXPORT EINT2_IRQHandler [WEAK] + EXPORT EINT3_IRQHandler [WEAK] + EXPORT EINT4_IRQHandler [WEAK] + EXPORT EINT5_IRQHandler [WEAK] + EXPORT GPA_IRQHandler [WEAK] + EXPORT GPB_IRQHandler [WEAK] + EXPORT GPC_IRQHandler [WEAK] + EXPORT GPD_IRQHandler [WEAK] + EXPORT GPE_IRQHandler [WEAK] + EXPORT GPF_IRQHandler [WEAK] + EXPORT QSPI0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT BRAKE0_IRQHandler [WEAK] + EXPORT EPWM0P0_IRQHandler [WEAK] + EXPORT EPWM0P1_IRQHandler [WEAK] + EXPORT EPWM0P2_IRQHandler [WEAK] + EXPORT BRAKE1_IRQHandler [WEAK] + EXPORT EPWM1P0_IRQHandler [WEAK] + EXPORT EPWM1P1_IRQHandler [WEAK] + EXPORT EPWM1P2_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT PDMA_IRQHandler [WEAK] + EXPORT DAC_IRQHandler [WEAK] + EXPORT EADC00_IRQHandler [WEAK] + EXPORT EADC01_IRQHandler [WEAK] + EXPORT ACMP01_IRQHandler [WEAK] + EXPORT EADC02_IRQHandler [WEAK] + EXPORT EADC03_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT QSPI1_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USBD_IRQHandler [WEAK] + EXPORT OHCI_IRQHandler [WEAK] + EXPORT USBOTG_IRQHandler [WEAK] + EXPORT CAN0_IRQHandler [WEAK] + EXPORT CAN1_IRQHandler [WEAK] + EXPORT SC0_IRQHandler [WEAK] + EXPORT SC1_IRQHandler [WEAK] + EXPORT SC2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT SDH0_IRQHandler [WEAK] + EXPORT USBD20_IRQHandler [WEAK] + EXPORT EMAC_TX_IRQHandler [WEAK] + EXPORT EMAC_RX_IRQHandler [WEAK] + EXPORT I2S0_IRQHandler [WEAK] + EXPORT OPA0_IRQHandler [WEAK] + EXPORT CRYPTO_IRQHandler [WEAK] + EXPORT GPG_IRQHandler [WEAK] + EXPORT EINT6_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT USCI0_IRQHandler [WEAK] + EXPORT USCI1_IRQHandler [WEAK] + EXPORT BPWM0_IRQHandler [WEAK] + EXPORT BPWM1_IRQHandler [WEAK] + EXPORT SPIM_IRQHandler [WEAK] + EXPORT CCAP_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT QEI0_IRQHandler [WEAK] + EXPORT QEI1_IRQHandler [WEAK] + EXPORT ECAP0_IRQHandler [WEAK] + EXPORT ECAP1_IRQHandler [WEAK] + EXPORT GPH_IRQHandler [WEAK] + EXPORT EINT7_IRQHandler [WEAK] + EXPORT SDH1_IRQHandler [WEAK] + EXPORT EHCI_IRQHandler [WEAK] + EXPORT USBOTG20_IRQHandler [WEAK] + EXPORT TRNG_IRQHandler [WEAK] + EXPORT UART6_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT EADC10_IRQHandler [WEAK] + EXPORT EADC11_IRQHandler [WEAK] + EXPORT EADC12_IRQHandler [WEAK] + EXPORT EADC13_IRQHandler [WEAK] + EXPORT CAN2_IRQHandler [WEAK] + +Default__IRQHandler +BOD_IRQHandler +IRC_IRQHandler +PWRWU_IRQHandler +RAMPE_IRQHandler +CKFAIL_IRQHandler +RTC_IRQHandler +TAMPER_IRQHandler +WDT_IRQHandler +WWDT_IRQHandler +EINT0_IRQHandler +EINT1_IRQHandler +EINT2_IRQHandler +EINT3_IRQHandler +EINT4_IRQHandler +EINT5_IRQHandler +GPA_IRQHandler +GPB_IRQHandler +GPC_IRQHandler +GPD_IRQHandler +GPE_IRQHandler +GPF_IRQHandler +QSPI0_IRQHandler +SPI0_IRQHandler +BRAKE0_IRQHandler +EPWM0P0_IRQHandler +EPWM0P1_IRQHandler +EPWM0P2_IRQHandler +BRAKE1_IRQHandler +EPWM1P0_IRQHandler +EPWM1P1_IRQHandler +EPWM1P2_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +PDMA_IRQHandler +DAC_IRQHandler +EADC00_IRQHandler +EADC01_IRQHandler +ACMP01_IRQHandler +EADC02_IRQHandler +EADC03_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +QSPI1_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USBD_IRQHandler +OHCI_IRQHandler +USBOTG_IRQHandler +CAN0_IRQHandler +CAN1_IRQHandler +SC0_IRQHandler +SC1_IRQHandler +SC2_IRQHandler +SPI3_IRQHandler +SDH0_IRQHandler +USBD20_IRQHandler +EMAC_TX_IRQHandler +EMAC_RX_IRQHandler +I2S0_IRQHandler +OPA0_IRQHandler +CRYPTO_IRQHandler +GPG_IRQHandler +EINT6_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +USCI0_IRQHandler +USCI1_IRQHandler +BPWM0_IRQHandler +BPWM1_IRQHandler +SPIM_IRQHandler +CCAP_IRQHandler +I2C2_IRQHandler +QEI0_IRQHandler +QEI1_IRQHandler +ECAP0_IRQHandler +ECAP1_IRQHandler +GPH_IRQHandler +EINT7_IRQHandler +SDH1_IRQHandler +EHCI_IRQHandler +USBOTG20_IRQHandler +TRNG_IRQHandler +UART6_IRQHandler +UART7_IRQHandler +EADC10_IRQHandler +EADC11_IRQHandler +EADC12_IRQHandler +EADC13_IRQHandler +CAN2_IRQHandler + + + + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END +;/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Source/GCC/startup_M480.S b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Source/GCC/startup_M480.S new file mode 100644 index 0000000000000000000000000000000000000000..a4eb650ee2ccaa5629269fafd1035e7ed512daa1 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Source/GCC/startup_M480.S @@ -0,0 +1,375 @@ +/****************************************************************************//** + * @file startup_M480.S + * @version V1.00 + * @brief CMSIS Cortex-M4 Core Device Startup File for M480 + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + + // Unlock Register + ldr r0, =0x40000100 + ldr r1, =0x59 + str r1, [r0] + ldr r1, =0x16 + str r1, [r0] + ldr r1, =0x88 + str r1, [r0] + +#ifndef ENABLE_SPIM_CACHE + ldr r0, =0x40000200 // R0 = Clock Controller Register Base Address + ldr r1, [r0,#0x4] // R1 = 0x40000204 (AHBCLK) + orr r1, r1, #0x4000 + str r1, [r0,#0x4] // CLK->AHBCLK |= CLK_AHBCLK_SPIMCKEN_Msk// + + ldr r0, =0x40007000 // R0 = SPIM Register Base Address + ldr r1, [r0,#4] // R1 = SPIM->CTL1 + orr r1, r1,#2 // R1 |= SPIM_CTL1_CACHEOFF_Msk + str r1, [r0,#4] // _SPIM_DISABLE_CACHE() + ldr r1, [r0,#4] // R1 = SPIM->CTL1 + orr r1, r1, #4 // R1 |= SPIM_CTL1_CCMEN_Msk + str r1, [r0,#4] // _SPIM_ENABLE_CCM() +#endif + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + + // Lock + ldr r0, =0x40000100 + ldr r1, =0 + str r1, [r0] + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the application's entry point.*/ + bl entry + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack // Top of Stack + .word Reset_Handler // Reset Handler + .word NMI_Handler // NMI Handler + .word HardFault_Handler // Hard Fault Handler + .word MemManage_Handler // MPU Fault Handler + .word BusFault_Handler // Bus Fault Handler + .word UsageFault_Handler // Usage Fault Handler + .word 0 // Reserved + .word 0 // DCDReserved + .word 0 // Reserved + .word 0 // Reserved + .word SVC_Handler // SVCall Handler + .word DebugMon_Handler // Debug Monitor Handler + .word 0 // Reserved + .word PendSV_Handler // PendSV Handler + .word SysTick_Handler // SysTick Handler + + // External Interrupts + .word BOD_IRQHandler /* 0: BOD */ + .word IRC_IRQHandler /* 1: IRC */ + .word PWRWU_IRQHandler /* 2: PWRWU */ + .word RAMPE_IRQHandler /* 3: RAMPE */ + .word CKFAIL_IRQHandler /* 4: CKFAIL */ + .word 0 /* 5: Reserved */ + .word RTC_IRQHandler /* 6: RTC */ + .word TAMPER_IRQHandler /* 7: TAMPER */ + .word WDT_IRQHandler /* 8: WDT */ + .word WWDT_IRQHandler /* 9: WWDT */ + .word EINT0_IRQHandler /* 10: EINT0 */ + .word EINT1_IRQHandler /* 11: EINT1 */ + .word EINT2_IRQHandler /* 12: EINT2 */ + .word EINT3_IRQHandler /* 13: EINT3 */ + .word EINT4_IRQHandler /* 14: EINT4 */ + .word EINT5_IRQHandler /* 15: EINT5 */ + .word GPA_IRQHandler /* 16: GPA */ + .word GPB_IRQHandler /* 17: GPB */ + .word GPC_IRQHandler /* 18: GPC */ + .word GPD_IRQHandler /* 19: GPD */ + .word GPE_IRQHandler /* 20: GPE */ + .word GPF_IRQHandler /* 21: GPF */ + .word QSPI0_IRQHandler /* 22: QSPI0 */ + .word SPI0_IRQHandler /* 23: SPI0 */ + .word BRAKE0_IRQHandler /* 24: BRAKE0 */ + .word EPWM0P0_IRQHandler /* 25: EPWM0P0 */ + .word EPWM0P1_IRQHandler /* 26: EPWM0P1 */ + .word EPWM0P2_IRQHandler /* 27: EPWM0P2 */ + .word BRAKE1_IRQHandler /* 28: BRAKE1 */ + .word EPWM1P0_IRQHandler /* 29: EPWM1P0 */ + .word EPWM1P1_IRQHandler /* 30: EPWM1P1 */ + .word EPWM1P2_IRQHandler /* 31: EPWM1P2 */ + .word TMR0_IRQHandler /* 32: TIMER0 */ + .word TMR1_IRQHandler /* 33: TIMER1 */ + .word TMR2_IRQHandler /* 34: TIMER2 */ + .word TMR3_IRQHandler /* 35: TIMER3 */ + .word UART0_IRQHandler /* 36: UART0 */ + .word UART1_IRQHandler /* 37: UART1 */ + .word I2C0_IRQHandler /* 38: I2C0 */ + .word I2C1_IRQHandler /* 39: I2C1 */ + .word PDMA_IRQHandler /* 40: PDMA */ + .word DAC_IRQHandler /* 41: DAC */ + .word EADC00_IRQHandler /* 42: EADC00 */ + .word EADC01_IRQHandler /* 43: EADC01 */ + .word ACMP01_IRQHandler /* 44: ACMP */ + .word 0 /* 45: Reserved */ + .word EADC02_IRQHandler /* 46: EADC02 */ + .word EADC03_IRQHandler /* 47: EADC03 */ + .word UART2_IRQHandler /* 48: UART2 */ + .word UART3_IRQHandler /* 49: UART3 */ + .word QSPI1_IRQHandler /* 50: QSPI1 */ + .word SPI1_IRQHandler /* 51: SPI1 */ + .word SPI2_IRQHandler /* 52: SPI2 */ + .word USBD_IRQHandler /* 53: USBD */ + .word OHCI_IRQHandler /* 54: OHCI */ + .word USBOTG_IRQHandler /* 55: OTG */ + .word CAN0_IRQHandler /* 56: CAN0 */ + .word CAN1_IRQHandler /* 57: CAN1 */ + .word SC0_IRQHandler /* 58: SC0 */ + .word SC1_IRQHandler /* 59: SC1 */ + .word SC2_IRQHandler /* 60: SC2 */ + .word 0 /* 61: Reserved */ + .word SPI3_IRQHandler /* 62: SPI3 */ + .word 0 /* 63: Reserved */ + .word SDH0_IRQHandler /* 64: SDH0 */ + .word USBD20_IRQHandler /* 65: HSUSBD */ + .word EMAC_TX_IRQHandler /* 66: EMAC_TX */ + .word EMAC_RX_IRQHandler /* 67: EMAC_RX */ + .word I2S0_IRQHandler /* 68: I2S */ + .word 0 /* 69: Reserved */ + .word OPA0_IRQHandler /* 70: OPA */ + .word CRYPTO_IRQHandler /* 71: CRYPTO */ + .word GPG_IRQHandler /* 72: GPG */ + .word EINT6_IRQHandler /* 73: EINT6 */ + .word UART4_IRQHandler /* 74: UART4 */ + .word UART5_IRQHandler /* 75: UART5 */ + .word USCI0_IRQHandler /* 76: USCI0 */ + .word USCI1_IRQHandler /* 77: USCI1 */ + .word BPWM0_IRQHandler /* 78: BPWM0 */ + .word BPWM1_IRQHandler /* 79: BPWM1 */ + .word SPIM_IRQHandler /* 80: SPIM */ + .word CCAP_IRQHandler /* 81: CCAP */ + .word I2C2_IRQHandler /* 82: I2C2 */ + .word 0 /* 83: Reserved */ + .word QEI0_IRQHandler /* 84: QEI0 */ + .word QEI1_IRQHandler /* 85: QEI1 */ + .word ECAP0_IRQHandler /* 86: ECAP0 */ + .word ECAP1_IRQHandler /* 87: ECAP1 */ + .word GPH_IRQHandler /* 88: GPH */ + .word EINT7_IRQHandler /* 89: EINT7 */ + .word SDH1_IRQHandler /* 90: SDH1 */ + .word 0 /* 91: Reserved */ + .word EHCI_IRQHandler /* 92: EHCI */ + .word USBOTG20_IRQHandler /* 93: HSOTG */ + .word 0 /* 94: Reserved */ + .word 0 /* 95: Reserved */ + .word 0 /* 96: Reserved */ + .word 0 /* 97: Reserved */ + .word 0 /* 98: Reserved */ + .word 0 /* 99: Reserved */ + .word 0 /* 100: Reserved */ + .word TRNG_IRQHandler /* 101: TRNG */ + .word UART6_IRQHandler /* 102: UART6 */ + .word UART7_IRQHandler /* 103: UART7 */ + .word EADC10_IRQHandler /* 104: EADC10 */ + .word EADC11_IRQHandler /* 105: EADC11 */ + .word EADC12_IRQHandler /* 106: EADC12 */ + .word EADC13_IRQHandler /* 107: EADC13 */ + .word CAN2_IRQHandler /* 108: CAN2 */ + + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler BOD_IRQHandler + def_irq_handler IRC_IRQHandler + def_irq_handler PWRWU_IRQHandler + def_irq_handler RAMPE_IRQHandler + def_irq_handler CKFAIL_IRQHandler + def_irq_handler RTC_IRQHandler + def_irq_handler TAMPER_IRQHandler + def_irq_handler WDT_IRQHandler + def_irq_handler WWDT_IRQHandler + def_irq_handler EINT0_IRQHandler + def_irq_handler EINT1_IRQHandler + def_irq_handler EINT2_IRQHandler + def_irq_handler EINT3_IRQHandler + def_irq_handler EINT4_IRQHandler + def_irq_handler EINT5_IRQHandler + def_irq_handler GPA_IRQHandler + def_irq_handler GPB_IRQHandler + def_irq_handler GPC_IRQHandler + def_irq_handler GPD_IRQHandler + def_irq_handler GPE_IRQHandler + def_irq_handler GPF_IRQHandler + def_irq_handler QSPI0_IRQHandler + def_irq_handler SPI0_IRQHandler + def_irq_handler BRAKE0_IRQHandler + def_irq_handler EPWM0P0_IRQHandler + def_irq_handler EPWM0P1_IRQHandler + def_irq_handler EPWM0P2_IRQHandler + def_irq_handler BRAKE1_IRQHandler + def_irq_handler EPWM1P0_IRQHandler + def_irq_handler EPWM1P1_IRQHandler + def_irq_handler EPWM1P2_IRQHandler + def_irq_handler TMR0_IRQHandler + def_irq_handler TMR1_IRQHandler + def_irq_handler TMR2_IRQHandler + def_irq_handler TMR3_IRQHandler + def_irq_handler UART0_IRQHandler + def_irq_handler UART1_IRQHandler + def_irq_handler I2C0_IRQHandler + def_irq_handler I2C1_IRQHandler + def_irq_handler PDMA_IRQHandler + def_irq_handler DAC_IRQHandler + def_irq_handler EADC00_IRQHandler + def_irq_handler EADC01_IRQHandler + def_irq_handler ACMP01_IRQHandler + def_irq_handler EADC02_IRQHandler + def_irq_handler EADC03_IRQHandler + def_irq_handler UART2_IRQHandler + def_irq_handler UART3_IRQHandler + def_irq_handler QSPI1_IRQHandler + def_irq_handler SPI1_IRQHandler + def_irq_handler SPI2_IRQHandler + def_irq_handler USBD_IRQHandler + def_irq_handler OHCI_IRQHandler + def_irq_handler USBOTG_IRQHandler + def_irq_handler CAN0_IRQHandler + def_irq_handler CAN1_IRQHandler + def_irq_handler SC0_IRQHandler + def_irq_handler SC1_IRQHandler + def_irq_handler SC2_IRQHandler + def_irq_handler SPI3_IRQHandler + def_irq_handler SDH0_IRQHandler + def_irq_handler USBD20_IRQHandler + def_irq_handler EMAC_TX_IRQHandler + def_irq_handler EMAC_RX_IRQHandler + def_irq_handler I2S0_IRQHandler + def_irq_handler OPA0_IRQHandler + def_irq_handler CRYPTO_IRQHandler + def_irq_handler GPG_IRQHandler + def_irq_handler EINT6_IRQHandler + def_irq_handler UART4_IRQHandler + def_irq_handler UART5_IRQHandler + def_irq_handler USCI0_IRQHandler + def_irq_handler USCI1_IRQHandler + def_irq_handler BPWM0_IRQHandler + def_irq_handler BPWM1_IRQHandler + def_irq_handler SPIM_IRQHandler + def_irq_handler CCAP_IRQHandler + def_irq_handler I2C2_IRQHandler + def_irq_handler QEI0_IRQHandler + def_irq_handler QEI1_IRQHandler + def_irq_handler ECAP0_IRQHandler + def_irq_handler ECAP1_IRQHandler + def_irq_handler GPH_IRQHandler + def_irq_handler EINT7_IRQHandler + def_irq_handler SDH1_IRQHandler + def_irq_handler EHCI_IRQHandler + def_irq_handler USBOTG20_IRQHandler + def_irq_handler TRNG_IRQHandler + def_irq_handler UART6_IRQHandler + def_irq_handler UART7_IRQHandler + def_irq_handler EADC10_IRQHandler + def_irq_handler EADC11_IRQHandler + def_irq_handler EADC12_IRQHandler + def_irq_handler EADC13_IRQHandler + def_irq_handler CAN2_IRQHandler diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Source/IAR/startup_M480.s b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Source/IAR/startup_M480.s new file mode 100644 index 0000000000000000000000000000000000000000..9aa379a758417384148812f88c8ef437acd1d07a --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Source/IAR/startup_M480.s @@ -0,0 +1,451 @@ +;/****************************************************************************** +; * @file startup_M480.s +; * @version V1.00 +; * @brief CMSIS Cortex-M4 Core Device Startup File for M480 +; * +; * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +;*****************************************************************************/ + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN HardFault_Handler + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD BOD_IRQHandler ; 0: Brown Out detection + DCD IRC_IRQHandler ; 1: Internal RC + DCD PWRWU_IRQHandler ; 2: Power down wake up + DCD RAMPE_IRQHandler ; 3: RAM parity error + DCD CKFAIL_IRQHandler ; 4: Clock detection fail + DCD Default_Handler ; 5: Reserved + DCD RTC_IRQHandler ; 6: Real Time Clock + DCD TAMPER_IRQHandler ; 7: Tamper detection + DCD WDT_IRQHandler ; 8: Watchdog timer + DCD WWDT_IRQHandler ; 9: Window watchdog timer + DCD EINT0_IRQHandler ; 10: External Input 0 + DCD EINT1_IRQHandler ; 11: External Input 1 + DCD EINT2_IRQHandler ; 12: External Input 2 + DCD EINT3_IRQHandler ; 13: External Input 3 + DCD EINT4_IRQHandler ; 14: External Input 4 + DCD EINT5_IRQHandler ; 15: External Input 5 + DCD GPA_IRQHandler ; 16: GPIO Port A + DCD GPB_IRQHandler ; 17: GPIO Port B + DCD GPC_IRQHandler ; 18: GPIO Port C + DCD GPD_IRQHandler ; 19: GPIO Port D + DCD GPE_IRQHandler ; 20: GPIO Port E + DCD GPF_IRQHandler ; 21: GPIO Port F + DCD QSPI0_IRQHandler ; 22: QSPI0 + DCD SPI0_IRQHandler ; 23: SPI0 + DCD BRAKE0_IRQHandler ; 24: + DCD PWM0P0_IRQHandler ; 25: + DCD PWM0P1_IRQHandler ; 26: + DCD PWM0P2_IRQHandler ; 27: + DCD BRAKE1_IRQHandler ; 28: + DCD PWM1P0_IRQHandler ; 29: + DCD PWM1P1_IRQHandler ; 30: + DCD PWM1P2_IRQHandler ; 31: + DCD TMR0_IRQHandler ; 32: Timer 0 + DCD TMR1_IRQHandler ; 33: Timer 1 + DCD TMR2_IRQHandler ; 34: Timer 2 + DCD TMR3_IRQHandler ; 35: Timer 3 + DCD UART0_IRQHandler ; 36: UART0 + DCD UART1_IRQHandler ; 37: UART1 + DCD I2C0_IRQHandler ; 38: I2C0 + DCD I2C1_IRQHandler ; 39: I2C1 + DCD PDMA_IRQHandler ; 40: Peripheral DMA + DCD DAC_IRQHandler ; 41: DAC + DCD EADC00_IRQHandler ; 42: EADC0 interrupt source 0 + DCD EADC01_IRQHandler ; 43: EADC0 interrupt source 1 + DCD ACMP01_IRQHandler ; 44: ACMP0 and ACMP1 + DCD Default_Handler ; 45: Reserved + DCD EADC02_IRQHandler ; 46: EADC0 interrupt source 2 + DCD EADC03_IRQHandler ; 47: EADC0 interrupt source 3 + DCD UART2_IRQHandler ; 48: UART2 + DCD UART3_IRQHandler ; 49: UART3 + DCD QSPI1_IRQHandler ; 50: QSPI1 + DCD SPI1_IRQHandler ; 51: SPI1 + DCD SPI2_IRQHandler ; 52: SPI2 + DCD USBD_IRQHandler ; 53: USB device + DCD OHCI_IRQHandler ; 54: OHCI + DCD USBOTG_IRQHandler ; 55: USB OTG + DCD CAN0_IRQHandler ; 56: CAN0 + DCD CAN1_IRQHandler ; 57: CAN1 + DCD SC0_IRQHandler ; 58: + DCD SC1_IRQHandler ; 59: + DCD SC2_IRQHandler ; 60: + DCD Default_Handler ; 61: + DCD SPI3_IRQHandler ; 62: SPI3 + DCD Default_Handler ; 63: + DCD SDH0_IRQHandler ; 64: SDH0 + DCD USBD20_IRQHandler ; 65: USBD20 + DCD EMAC_TX_IRQHandler ; 66: EMAC_TX + DCD EMAC_RX_IRQHandler ; 67: EMAX_RX + DCD I2S0_IRQHandler ; 68: I2S0 + DCD Default_Handler ; 69: ToDo: Add description to this Interrupt + DCD OPA0_IRQHandler ; 70: OPA0 + DCD CRYPTO_IRQHandler ; 71: CRYPTO + DCD GPG_IRQHandler ; 72: + DCD EINT6_IRQHandler ; 73: + DCD UART4_IRQHandler ; 74: UART4 + DCD UART5_IRQHandler ; 75: UART5 + DCD USCI0_IRQHandler ; 76: USCI0 + DCD USCI1_IRQHandler ; 77: USCI1 + DCD BPWM0_IRQHandler ; 78: BPWM0 + DCD BPWM1_IRQHandler ; 79: BPWM1 + DCD SPIM_IRQHandler ; 80: SPIM + DCD CCAP_IRQHandler ; 81: CCAP + DCD I2C2_IRQHandler ; 82: I2C2 + DCD Default_Handler ; 83: + DCD QEI0_IRQHandler ; 84: QEI0 + DCD QEI1_IRQHandler ; 85: QEI1 + DCD ECAP0_IRQHandler ; 86: ECAP0 + DCD ECAP1_IRQHandler ; 87: ECAP1 + DCD GPH_IRQHandler ; 88: + DCD EINT7_IRQHandler ; 89: + DCD SDH1_IRQHandler ; 90: SDH1 + DCD Default_Handler ; 91: + DCD EHCI_IRQHandler ; 92: EHCI + DCD USBOTG20_IRQHandler ; 93: + DCD Default_Handler ; 94: + DCD Default_Handler ; 95: + DCD Default_Handler ; 96: + DCD Default_Handler ; 97: + DCD Default_Handler ; 98: + DCD Default_Handler ; 99: + DCD Default_Handler ; 100: + DCD TRNG_IRQHandler ; 101: TRNG + DCD UART6_IRQHandler ; 102: UART6 + DCD UART7_IRQHandler ; 103: UART7 + DCD EADC10_IRQHandler ; 104: EADC1 interrupt source 0 + DCD EADC11_IRQHandler ; 105: EADC1 interrupt source 1 + DCD EADC12_IRQHandler ; 106: EADC1 interrupt source 2 + DCD EADC13_IRQHandler ; 107: EADC1 interrupt source 3 + DCD CAN2_IRQHandler ; 108: CAN2 +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + ; Unlock Register + LDR R0, =0x40000100 + LDR R1, =0x59 + STR R1, [R0] + LDR R1, =0x16 + STR R1, [R0] + LDR R1, =0x88 + STR R1, [R0] + + #ifndef ENABLE_SPIM_CACHE + LDR R0, =0x40000200 ; R0 = Clock Controller Register Base Address + LDR R1, [R0,#0x4] ; R1 = 0x40000204 (AHBCLK) + ORR R1, R1, #0x4000 + STR R1, [R0,#0x4] ; CLK->AHBCLK |= CLK_AHBCLK_SPIMCKEN_Msk; + + LDR R0, =0x40007000 ; R0 = SPIM Register Base Address + LDR R1, [R0,#4] ; R1 = SPIM->CTL1 + ORR R1, R1,#2 ; R1 |= SPIM_CTL1_CACHEOFF_Msk + STR R1, [R0,#4] ; _SPIM_DISABLE_CACHE() + LDR R1, [R0,#4] ; R1 = SPIM->CTL1 + ORR R1, R1, #4 ; R1 |= SPIM_CTL1_CCMEN_Msk + STR R1, [R0,#4] ; _SPIM_ENABLE_CCM() + #endif + + LDR R0, =SystemInit + BLX R0 + + ; Init POR + ; LDR R2, =0x40000024 + ; LDR R1, =0x00005AA5 + ; STR R1, [R2] + + ; Lock register + LDR R0, =0x40000100 + MOVS R1, #0 + STR R1, [R0] + + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK BOD_IRQHandler + PUBWEAK IRC_IRQHandler + PUBWEAK PWRWU_IRQHandler + PUBWEAK RAMPE_IRQHandler + PUBWEAK CKFAIL_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK TAMPER_IRQHandler + PUBWEAK WDT_IRQHandler + PUBWEAK WWDT_IRQHandler + PUBWEAK EINT0_IRQHandler + PUBWEAK EINT1_IRQHandler + PUBWEAK EINT2_IRQHandler + PUBWEAK EINT3_IRQHandler + PUBWEAK EINT4_IRQHandler + PUBWEAK EINT5_IRQHandler + PUBWEAK GPA_IRQHandler + PUBWEAK GPB_IRQHandler + PUBWEAK GPC_IRQHandler + PUBWEAK GPD_IRQHandler + PUBWEAK GPE_IRQHandler + PUBWEAK GPF_IRQHandler + PUBWEAK QSPI0_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK BRAKE0_IRQHandler + PUBWEAK PWM0P0_IRQHandler + PUBWEAK PWM0P1_IRQHandler + PUBWEAK PWM0P2_IRQHandler + PUBWEAK BRAKE1_IRQHandler + PUBWEAK PWM1P0_IRQHandler + PUBWEAK PWM1P1_IRQHandler + PUBWEAK PWM1P2_IRQHandler + PUBWEAK TMR0_IRQHandler + PUBWEAK TMR1_IRQHandler + PUBWEAK TMR2_IRQHandler + PUBWEAK TMR3_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C1_IRQHandler + PUBWEAK PDMA_IRQHandler + PUBWEAK DAC_IRQHandler + PUBWEAK EADC00_IRQHandler + PUBWEAK EADC01_IRQHandler + PUBWEAK ACMP01_IRQHandler + PUBWEAK EADC02_IRQHandler + PUBWEAK EADC03_IRQHandler + PUBWEAK UART2_IRQHandler + PUBWEAK UART3_IRQHandler + PUBWEAK QSPI1_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK SPI2_IRQHandler + PUBWEAK USBD_IRQHandler + PUBWEAK OHCI_IRQHandler + PUBWEAK USBOTG_IRQHandler + PUBWEAK CAN0_IRQHandler + PUBWEAK CAN1_IRQHandler + PUBWEAK SC0_IRQHandler + PUBWEAK SC1_IRQHandler + PUBWEAK SC2_IRQHandler + PUBWEAK SPI3_IRQHandler + PUBWEAK SDH0_IRQHandler + PUBWEAK USBD20_IRQHandler + PUBWEAK EMAC_TX_IRQHandler + PUBWEAK EMAC_RX_IRQHandler + PUBWEAK I2S0_IRQHandler + PUBWEAK OPA0_IRQHandler + PUBWEAK CRYPTO_IRQHandler + PUBWEAK GPG_IRQHandler + PUBWEAK EINT6_IRQHandler + PUBWEAK UART4_IRQHandler + PUBWEAK UART5_IRQHandler + PUBWEAK USCI0_IRQHandler + PUBWEAK USCI1_IRQHandler + PUBWEAK BPWM0_IRQHandler + PUBWEAK BPWM1_IRQHandler + PUBWEAK SPIM_IRQHandler + PUBWEAK CCAP_IRQHandler + PUBWEAK I2C2_IRQHandler + PUBWEAK QEI0_IRQHandler + PUBWEAK QEI1_IRQHandler + PUBWEAK ECAP0_IRQHandler + PUBWEAK ECAP1_IRQHandler + PUBWEAK GPH_IRQHandler + PUBWEAK EINT7_IRQHandler + PUBWEAK SDH1_IRQHandler + PUBWEAK EHCI_IRQHandler + PUBWEAK USBOTG20_IRQHandler + PUBWEAK TRNG_IRQHandler + PUBWEAK UART6_IRQHandler + PUBWEAK UART7_IRQHandler + PUBWEAK EADC10_IRQHandler + PUBWEAK EADC11_IRQHandler + PUBWEAK EADC12_IRQHandler + PUBWEAK EADC13_IRQHandler + PUBWEAK CAN2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) + +BOD_IRQHandler +IRC_IRQHandler +PWRWU_IRQHandler +RAMPE_IRQHandler +CKFAIL_IRQHandler +RTC_IRQHandler +TAMPER_IRQHandler +WDT_IRQHandler +WWDT_IRQHandler +EINT0_IRQHandler +EINT1_IRQHandler +EINT2_IRQHandler +EINT3_IRQHandler +EINT4_IRQHandler +EINT5_IRQHandler +GPA_IRQHandler +GPB_IRQHandler +GPC_IRQHandler +GPD_IRQHandler +GPE_IRQHandler +GPF_IRQHandler +QSPI0_IRQHandler +SPI0_IRQHandler +BRAKE0_IRQHandler +PWM0P0_IRQHandler +PWM0P1_IRQHandler +PWM0P2_IRQHandler +BRAKE1_IRQHandler +PWM1P0_IRQHandler +PWM1P1_IRQHandler +PWM1P2_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +PDMA_IRQHandler +DAC_IRQHandler +EADC00_IRQHandler +EADC01_IRQHandler +ACMP01_IRQHandler +EADC02_IRQHandler +EADC03_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +QSPI1_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USBD_IRQHandler +OHCI_IRQHandler +USBOTG_IRQHandler +CAN0_IRQHandler +CAN1_IRQHandler +SC0_IRQHandler +SC1_IRQHandler +SC2_IRQHandler +SPI3_IRQHandler +SDH0_IRQHandler +USBD20_IRQHandler +EMAC_TX_IRQHandler +EMAC_RX_IRQHandler +I2S0_IRQHandler +OPA0_IRQHandler +CRYPTO_IRQHandler +GPG_IRQHandler +EINT6_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +USCI0_IRQHandler +USCI1_IRQHandler +BPWM0_IRQHandler +BPWM1_IRQHandler +SPIM_IRQHandler +CCAP_IRQHandler +I2C2_IRQHandler +QEI0_IRQHandler +QEI1_IRQHandler +ECAP0_IRQHandler +ECAP1_IRQHandler +GPH_IRQHandler +EINT7_IRQHandler +SDH1_IRQHandler +EHCI_IRQHandler +USBOTG20_IRQHandler +TRNG_IRQHandler +UART6_IRQHandler +UART7_IRQHandler +EADC10_IRQHandler +EADC11_IRQHandler +EADC12_IRQHandler +EADC13_IRQHandler +CAN2_IRQHandler +Default_Handler + B Default_Handler + + + + + END +;/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Source/system_M480.c b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Source/system_M480.c new file mode 100644 index 0000000000000000000000000000000000000000..76573a4a3e4060b50df2a959aa4bbbce5c5f3549 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Source/system_M480.c @@ -0,0 +1,110 @@ +/**************************************************************************//** + * @file system_M480.c + * @version V1.000 + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Source File for M480 + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#include "NuMicro.h" + + +/*---------------------------------------------------------------------------- + DEFINES + *----------------------------------------------------------------------------*/ + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ +uint32_t CyclesPerUs = (__HSI / 1000000UL); /* Cycles per micro second */ +uint32_t PllClock = __HSI; /*!< PLL Output Clock Frequency */ +uint32_t gau32ClkSrcTbl[] = {__HXT, __LXT, 0UL, __LIRC, 0UL, 0UL, 0UL, __HIRC}; + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + uint32_t u32Freq, u32ClkSrc; + uint32_t u32HclkDiv; + + /* Update PLL Clock */ + PllClock = CLK_GetPLLClockFreq(); + + u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk; + + if(u32ClkSrc == CLK_CLKSEL0_HCLKSEL_PLL) + { + /* Use PLL clock */ + u32Freq = PllClock; + } + else + { + /* Use the clock sources directly */ + u32Freq = gau32ClkSrcTbl[u32ClkSrc]; + } + + u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1UL; + + /* Update System Core Clock */ + SystemCoreClock = u32Freq / u32HclkDiv; + + + //if(SystemCoreClock == 0) + // __BKPT(0); + + CyclesPerUs = (SystemCoreClock + 500000UL) / 1000000UL; +} + +/** + * @brief Set PF.2 and PF.3 to input mode + * @param None + * @return None + * @details GPIO default state could be configured as input or quasi through user config. + * To use HXT, PF.2 and PF.3 must not set as quasi mode. This function changes + * PF.2 and PF.3 to input mode no matter which mode they are working at. + */ +static __INLINE void HXTInit(void) +{ + PF->MODE &= ~(GPIO_MODE_MODE2_Msk | GPIO_MODE_MODE3_Msk); + +} + +/** + * @brief Initialize the System + * + * @param none + * @return none + */ +void SystemInit (void) +{ + /* Add your system initialize code here. + Do not use global variables because this function is called before + reaching pre-main. RW section maybe overwritten afterwards. */ + + + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ +#endif + + /* Set access cycle for CPU @ 192MHz */ + FMC->CYCCTL = (FMC->CYCCTL & ~FMC_CYCCTL_CYCLE_Msk) | (8 << FMC_CYCCTL_CYCLE_Pos); + /* Configure power down bias, must set 1 before entering power down mode. + So set it at the very beginning */ + CLK->LDOCTL |= CLK_LDOCTL_PDBIASEN_Msk; + /* Hand over the control of PF.4~11 I/O function from RTC module to GPIO module */ + CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk; + RTC->GPIOCTL0 &= ~(RTC_GPIOCTL0_CTLSEL0_Msk | RTC_GPIOCTL0_CTLSEL1_Msk | + RTC_GPIOCTL0_CTLSEL2_Msk | RTC_GPIOCTL0_CTLSEL3_Msk); + RTC->GPIOCTL1 &= ~(RTC_GPIOCTL1_CTLSEL4_Msk | RTC_GPIOCTL1_CTLSEL5_Msk | + RTC_GPIOCTL1_CTLSEL6_Msk | RTC_GPIOCTL1_CTLSEL7_Msk); + CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk; + HXTInit(); + +} +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/Device/SConscript b/bsp/nuvoton/libraries/m480/Device/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..26e69fb8240d75be153c78a2e42eeda586c147d2 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/Device/SConscript @@ -0,0 +1,25 @@ +import rtconfig +Import('RTT_ROOT') +from building import * + +# get current directory +cwd = GetCurrentDir() + +# The set of source files associated with this SConscript file. +src = Split(""" +Nuvoton/M480/Source/system_M480.c +""") + +# add for startup script +if rtconfig.CROSS_TOOL == 'gcc': + src = src + ['Nuvoton/M480/Source/GCC/startup_M480.S'] +elif rtconfig.CROSS_TOOL == 'keil': + src = src + ['Nuvoton/M480/Source/ARM/startup_M480.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src = src + ['Nuvoton/M480/Source/IAR/startup_M480.s'] + +path = [cwd + '/Nuvoton/M480/Include',] + +group = DefineGroup('m480_device', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/nuvoton/libraries/m480/README.md b/bsp/nuvoton/libraries/m480/README.md new file mode 100644 index 0000000000000000000000000000000000000000..e64b873321224a316aa6a0e07066f9cc2c72c203 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/README.md @@ -0,0 +1,49 @@ +# M480 Series + +## Supported drivers + +| Peripheral | rt_device_class_type | Device name | +| ------ | ---- | :------: | +| BPWM | RT_Device_Class_Miscellaneous (PWM) | ***bpwm[0-1]*** | +| BPWM (Capture function)| RT_Device_Class_Miscellaneous (Input capture) | ***bpwm[0-1]i[0-5]*** | +| CAN | RT_Device_Class_CAN | ***can[0-1]*** | +| CLK | RT_Device_Class_PM | ***pm*** | +| CRC | RT_Device_Class_Miscellaneous (HW Crypto) | ***hwcryto*** | +| CRYPTO | RT_Device_Class_Miscellaneous (HW Crypto) | ***hwcryto*** | +| EADC | RT_Device_Class_Miscellaneous (ADC) | ***eadc[0-1]*** | +| EBI | N/A | ***N/A*** | +| ECAP | RT_Device_Class_Miscellaneous (Input capture) | ***ecap[0-1]i[0-2]*** | +| EMAC | RT_Device_Class_NetIf | ***e0*** | +| EPWM | RT_Device_Class_Miscellaneous (PWM) | ***epwm[0-1]*** | +| EPWM (Capture function) | RT_Device_Class_Miscellaneous (Input capture) | ***epwm[0-1]i[0-5]*** | +| FMC | FAL | ***N/A*** | +| GPIO | RT_Device_Class_Miscellaneous (Pin) | ***gpio*** | +| GPIO | RT_Device_Class_I2CBUS | ***softi2c0[0-1]*** | +| HSOTG | RT_Device_Class_USBHost/RT_Device_Class_USBDevice | ***N/A*** | +| HSUSBD | RT_Device_Class_USBDevice | ***usbd*** | +| I2C | RT_Device_Class_I2CBUS | ***i2c[0-2]*** | +| I2S | RT_Device_Class_Sound/RT_Device_Class_Pipe | ***sound0*** | +| PDMA | N/A | ***N/A*** | +| QEI | RT_Device_Class_Miscellaneous (Pulse encoder) | ***qei[0-1]*** | +| QSPI | RT_Device_Class_SPIBUS | ***qspi[0-1]*** | +| RTC | RT_Device_Class_RTC | ***rtc*** | +| SC (UART function) | RT_Device_Class_Char | ***scuart[0-2]*** | +| SDH | RT_Device_Class_Block | ***sdh[0-1]*** | +| SPI | RT_Device_Class_SPIBUS | ***spi[0-3]*** | +| SPI (I2S function) | RT_Device_Class_Sound/RT_Device_Class_Pipe | ***spii2s[0-3]*** | +| TIMER | RT_Device_Class_Timer | ***timer[0-3]*** | +| TIMER (Capture function) | RT_Device_Class_Miscellaneous (Input capture) | ***timer[0-3]i0*** | +| TIMER (PWM function) | RT_Device_Class_Miscellaneous (PWM) | ***tpwm[0-3]*** | +| TRNG | RT_Device_Class_Miscellaneous (HW Crypto) | ***hwcryto*** | +| UART | RT_Device_Class_Char | ***uart[0-7]*** | +| USBD | RT_Device_Class_USBDevice | ***usbd*** | +| USBH, HSUSBH | RT_Device_Class_USBHost | ***usbh*** | +| USCI (I2C function) | RT_Device_Class_I2CBUS | ***ui2c[0-1]*** | +| USCI (SPI function) | RT_Device_Class_SPIBUS | ***uspi[0-1]*** | +| USCI (UART function) | RT_Device_Class_Char | ***uuart[0-1]*** | +| WDT | RT_Device_Class_Miscellaneous (Watchdog) | ***wdt*** | + +## Resources +* [Download M480 TRM][1] + + [1]: https://www.nuvoton.com/resource-download.jsp?tp_GUID=DA05-M480 diff --git a/bsp/nuvoton/libraries/m480/SConscript b/bsp/nuvoton/libraries/m480/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..4c815c49b835a3a5ea61f337dc17154dd316d7d1 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/SConscript @@ -0,0 +1,15 @@ +# RT-Thread building script for bridge + +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/nuvoton/libraries/m480/StdDriver/SConscript b/bsp/nuvoton/libraries/m480/StdDriver/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..6a932cff584df59a56960b320c3c60eba34ba2dd --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/SConscript @@ -0,0 +1,28 @@ +# RT-Thread building script for component +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +libs = [] +src = Glob('*src/*.c') + Glob('src/*.cpp') +cpppath = [cwd + '/inc'] +libpath = [cwd + '/lib'] + +if not GetDepend('BSP_USE_STDDRIVER_SOURCE'): + if rtconfig.CROSS_TOOL == 'keil': + if GetOption('target') == 'mdk5' and os.path.isfile('./lib/libstddriver_keil.lib'): + libs += ['libstddriver_keil'] + elif GetOption('target') == 'mdk4' and os.path.isfile('./lib/libstddriver_keil4.lib'): + libs += ['libstddriver_keil4'] + elif rtconfig.CROSS_TOOL == 'gcc' and os.path.isfile('./lib/libstddriver_gcc.a'): + libs += ['libstddriver_gcc'] + elif os.path.isfile('./lib/libstddriver_iar.a'): + libs += ['libstddriver_iar'] + +if not libs: + group = DefineGroup('m480_stddriver', src, depend = [''], CPPPATH = cpppath) +else: + src = [] + group = DefineGroup('m480_stddriver', src, depend = [''], CPPPATH = cpppath, LIBS = libs, LIBPATH = libpath) + +Return('group') diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_acmp.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_acmp.h new file mode 100644 index 0000000000000000000000000000000000000000..23db060037d5978aee0072b0eb426c104862d4a1 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_acmp.h @@ -0,0 +1,415 @@ +/**************************************************************************//** + * @file ACMP.h + * @version V1.00 + * @brief M480 Series ACMP Driver Header File + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __NU_ACMP_H__ +#define __NU_ACMP_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + + +/** @addtogroup ACMP_Driver ACMP Driver + @{ +*/ + + +/** @addtogroup ACMP_EXPORTED_CONSTANTS ACMP Exported Constants + @{ +*/ + + + +/*---------------------------------------------------------------------------------------------------------*/ +/* ACMP_CTL constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define ACMP_CTL_FILTSEL_OFF (0UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for filter function disabled. \hideinitializer */ +#define ACMP_CTL_FILTSEL_1PCLK (1UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 1 PCLK filter count. \hideinitializer */ +#define ACMP_CTL_FILTSEL_2PCLK (2UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 2 PCLK filter count. \hideinitializer */ +#define ACMP_CTL_FILTSEL_4PCLK (3UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 4 PCLK filter count. \hideinitializer */ +#define ACMP_CTL_FILTSEL_8PCLK (4UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 8 PCLK filter count. \hideinitializer */ +#define ACMP_CTL_FILTSEL_16PCLK (5UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 16 PCLK filter count. \hideinitializer */ +#define ACMP_CTL_FILTSEL_32PCLK (6UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 32 PCLK filter count. \hideinitializer */ +#define ACMP_CTL_FILTSEL_64PCLK (7UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 64 PCLK filter count. \hideinitializer */ +#define ACMP_CTL_INTPOL_RF (0UL << ACMP_CTL_INTPOL_Pos) /*!< ACMP_CTL setting for selecting rising edge and falling edge as interrupt condition. \hideinitializer */ +#define ACMP_CTL_INTPOL_R (1UL << ACMP_CTL_INTPOL_Pos) /*!< ACMP_CTL setting for selecting rising edge as interrupt condition. \hideinitializer */ +#define ACMP_CTL_INTPOL_F (2UL << ACMP_CTL_INTPOL_Pos) /*!< ACMP_CTL setting for selecting falling edge as interrupt condition. \hideinitializer */ +#define ACMP_CTL_POSSEL_P0 (0UL << ACMP_CTL_POSSEL_Pos) /*!< ACMP_CTL setting for selecting ACMPx_P0 pin as the source of ACMP V+. \hideinitializer */ +#define ACMP_CTL_POSSEL_P1 (1UL << ACMP_CTL_POSSEL_Pos) /*!< ACMP_CTL setting for selecting ACMPx_P1 pin as the source of ACMP V+. \hideinitializer */ +#define ACMP_CTL_POSSEL_P2 (2UL << ACMP_CTL_POSSEL_Pos) /*!< ACMP_CTL setting for selecting ACMPx_P2 pin as the source of ACMP V+. \hideinitializer */ +#define ACMP_CTL_POSSEL_P3 (3UL << ACMP_CTL_POSSEL_Pos) /*!< ACMP_CTL setting for selecting ACMPx_P3 pin as the source of ACMP V+. \hideinitializer */ +#define ACMP_CTL_NEGSEL_PIN (0UL << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_CTL setting for selecting the voltage of ACMP negative input pin as the source of ACMP V-. \hideinitializer */ +#define ACMP_CTL_NEGSEL_CRV (1UL << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_CTL setting for selecting internal comparator reference voltage as the source of ACMP V-. \hideinitializer */ +#define ACMP_CTL_NEGSEL_VBG (2UL << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_CTL setting for selecting internal Band-gap voltage as the source of ACMP V-. \hideinitializer */ +#define ACMP_CTL_NEGSEL_DAC (3UL << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_CTL setting for selecting DAC output voltage as the source of ACMP V-. \hideinitializer */ +#define ACMP_CTL_HYSTERESIS_30MV (3UL << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_CTL setting for enabling the hysteresis function at 30mV. \hideinitializer */ +#define ACMP_CTL_HYSTERESIS_20MV (2UL << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_CTL setting for enabling the hysteresis function at 20mV. \hideinitializer */ +#define ACMP_CTL_HYSTERESIS_10MV (1UL << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_CTL setting for enabling the hysteresis function at 10mV. \hideinitializer */ +#define ACMP_CTL_HYSTERESIS_DISABLE (0UL << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_CTL setting for disabling the hysteresis function. \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* ACMP_VREF constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define ACMP_VREF_CRVSSEL_VDDA (0UL << ACMP_VREF_CRVSSEL_Pos) /*!< ACMP_VREF setting for selecting analog supply voltage VDDA as the CRV source voltage \hideinitializer */ +#define ACMP_VREF_CRVSSEL_INTVREF (1UL << ACMP_VREF_CRVSSEL_Pos) /*!< ACMP_VREF setting for selecting internal reference voltage as the CRV source voltage \hideinitializer */ + + +/*@}*/ /* end of group ACMP_EXPORTED_CONSTANTS */ + + +/** @addtogroup ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Macros and functions */ +/*---------------------------------------------------------------------------------------------------------*/ + + +/** + * @brief This macro is used to enable output inverse function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set ACMPOINV bit of ACMP_CTL register to enable output inverse function. + * \hideinitializer + */ +#define ACMP_ENABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPOINV_Msk) + +/** + * @brief This macro is used to disable output inverse function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear ACMPOINV bit of ACMP_CTL register to disable output inverse function. + * \hideinitializer + */ +#define ACMP_DISABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPOINV_Msk) + +/** + * @brief This macro is used to select ACMP negative input source + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32Src is comparator negative input selection. Including: + * - \ref ACMP_CTL_NEGSEL_PIN + * - \ref ACMP_CTL_NEGSEL_CRV + * - \ref ACMP_CTL_NEGSEL_VBG + * - \ref ACMP_CTL_NEGSEL_DAC + * @return None + * @details This macro will set NEGSEL (ACMP_CTL[5:4]) to determine the source of negative input. + * \hideinitializer + */ +#define ACMP_SET_NEG_SRC(acmp, u32ChNum, u32Src) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_NEGSEL_Msk) | (u32Src)) + +/** + * @brief This macro is used to enable hysteresis function and set hysteresis to 30mV + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * \hideinitializer + */ +#define ACMP_ENABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_HYSTERESIS_30MV) + +/** + * @brief This macro is used to disable hysteresis function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear HYSEL bits of ACMP_CTL register to disable hysteresis function. + * \hideinitializer + */ +#define ACMP_DISABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_HYSSEL_Msk) + +/** + * @brief This macro is used to select hysteresis level + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32HysSel The hysteresis function option. Including: + * - \ref ACMP_CTL_HYSTERESIS_30MV + * - \ref ACMP_CTL_HYSTERESIS_20MV + * - \ref ACMP_CTL_HYSTERESIS_10MV + * - \ref ACMP_CTL_HYSTERESIS_DISABLE + * \hideinitializer + * @return None + */ +#define ACMP_CONFIG_HYSTERESIS(acmp, u32ChNum, u32HysSel) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_HYSSEL_Msk) | (u32HysSel)) + +/** + * @brief This macro is used to enable interrupt + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set ACMPIE bit of ACMP_CTL register to enable interrupt function. + * If wake-up function is enabled, the wake-up interrupt will be enabled as well. + * \hideinitializer + */ +#define ACMP_ENABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPIE_Msk) + +/** + * @brief This macro is used to disable interrupt + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear ACMPIE bit of ACMP_CTL register to disable interrupt function. + * \hideinitializer + */ +#define ACMP_DISABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPIE_Msk) + +/** + * @brief This macro is used to enable ACMP + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set ACMPEN bit of ACMP_CTL register to enable analog comparator. + * \hideinitializer + */ +#define ACMP_ENABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPEN_Msk) + +/** + * @brief This macro is used to disable ACMP + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear ACMPEN bit of ACMP_CTL register to disable analog comparator. + * \hideinitializer + */ +#define ACMP_DISABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPEN_Msk) + +/** + * @brief This macro is used to get ACMP output value + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return ACMP output value + * @details This macro will return the ACMP output value. + * \hideinitializer + */ +#define ACMP_GET_OUTPUT(acmp, u32ChNum) (((acmp)->STATUS & (ACMP_STATUS_ACMPO0_Msk<<((u32ChNum))))?1:0) + +/** + * @brief This macro is used to get ACMP interrupt flag + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return ACMP interrupt occurred (1) or not (0) + * @details This macro will return the ACMP interrupt flag. + * \hideinitializer + */ +#define ACMP_GET_INT_FLAG(acmp, u32ChNum) (((acmp)->STATUS & (ACMP_STATUS_ACMPIF0_Msk<<((u32ChNum))))?1:0) + +/** + * @brief This macro is used to clear ACMP interrupt flag + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will write 1 to ACMPIFn bit of ACMP_STATUS register to clear interrupt flag. + * \hideinitializer + */ +#define ACMP_CLR_INT_FLAG(acmp, u32ChNum) ((acmp)->STATUS = (ACMP_STATUS_ACMPIF0_Msk<<((u32ChNum)))) + +/** + * @brief This macro is used to clear ACMP wake-up interrupt flag + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will write 1 to WKIFn bit of ACMP_STATUS register to clear interrupt flag. + * \hideinitializer + */ +#define ACMP_CLR_WAKEUP_INT_FLAG(acmp, u32ChNum) ((acmp)->STATUS = (ACMP_STATUS_WKIF0_Msk<<((u32ChNum)))) + +/** + * @brief This macro is used to enable ACMP wake-up function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set WKEN (ACMP_CTL[16]) to enable ACMP wake-up function. + * \hideinitializer + */ +#define ACMP_ENABLE_WAKEUP(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WKEN_Msk) + +/** + * @brief This macro is used to disable ACMP wake-up function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear WKEN (ACMP_CTL[16]) to disable ACMP wake-up function. + * \hideinitializer + */ +#define ACMP_DISABLE_WAKEUP(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WKEN_Msk) + +/** + * @brief This macro is used to select ACMP positive input pin + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32Pin Comparator positive pin selection. Including: + * - \ref ACMP_CTL_POSSEL_P0 + * - \ref ACMP_CTL_POSSEL_P1 + * - \ref ACMP_CTL_POSSEL_P2 + * - \ref ACMP_CTL_POSSEL_P3 + * @return None + * @details This macro will set POSSEL (ACMP_CTL[7:6]) to determine the comparator positive input pin. + * \hideinitializer + */ +#define ACMP_SELECT_P(acmp, u32ChNum, u32Pin) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_POSSEL_Msk) | (u32Pin)) + +/** + * @brief This macro is used to enable ACMP filter function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set OUTSEL (ACMP_CTL[12]) to enable output filter function. + * \hideinitializer + */ +#define ACMP_ENABLE_FILTER(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_OUTSEL_Msk) + +/** + * @brief This macro is used to disable ACMP filter function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear OUTSEL (ACMP_CTL[12]) to disable output filter function. + * \hideinitializer + */ +#define ACMP_DISABLE_FILTER(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_OUTSEL_Msk) + +/** + * @brief This macro is used to set ACMP filter function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32Cnt is comparator filter count setting. + * - \ref ACMP_CTL_FILTSEL_OFF + * - \ref ACMP_CTL_FILTSEL_1PCLK + * - \ref ACMP_CTL_FILTSEL_2PCLK + * - \ref ACMP_CTL_FILTSEL_4PCLK + * - \ref ACMP_CTL_FILTSEL_8PCLK + * - \ref ACMP_CTL_FILTSEL_16PCLK + * - \ref ACMP_CTL_FILTSEL_32PCLK + * - \ref ACMP_CTL_FILTSEL_64PCLK + * @return None + * @details When ACMP output filter function is enabled, the output sampling count is determined by FILTSEL (ACMP_CTL[15:13]). + * \hideinitializer + */ +#define ACMP_SET_FILTER(acmp, u32ChNum, u32Cnt) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_FILTSEL_Msk) | (u32Cnt)) + +/** + * @brief This macro is used to select comparator reference voltage + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32Level The comparator reference voltage setting. + * The formula is: + * comparator reference voltage = CRV source voltage x (1/6 + u32Level/24) + * The range of u32Level is 0 ~ 15. + * @return None + * @details When CRV is selected as ACMP negative input source, the CRV level is determined by CRVCTL (ACMP_VREF[3:0]). + * \hideinitializer + */ +#define ACMP_CRV_SEL(acmp, u32Level) ((acmp)->VREF = ((acmp)->VREF & ~ACMP_VREF_CRVCTL_Msk) | ((u32Level)<VREF = ((acmp)->VREF & ~ACMP_VREF_CRVSSEL_Msk) | (u32Src)) + +/** + * @brief This macro is used to select ACMP interrupt condition + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32Cond Comparator interrupt condition selection. Including: + * - \ref ACMP_CTL_INTPOL_RF + * - \ref ACMP_CTL_INTPOL_R + * - \ref ACMP_CTL_INTPOL_F + * @return None + * @details The ACMP output interrupt condition can be rising edge, falling edge or any edge. + * \hideinitializer + */ +#define ACMP_SELECT_INT_COND(acmp, u32ChNum, u32Cond) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_INTPOL_Msk) | (u32Cond)) + +/** + * @brief This macro is used to enable ACMP window latch mode + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set WLATEN (ACMP_CTL[17]) to enable ACMP window latch mode. + * When ACMP0/1_WLAT pin is at high level, ACMPO0/1 passes through window latch + * block; when ACMP0/1_WLAT pin is at low level, the output of window latch block, + * WLATOUT, is frozen. + * \hideinitializer + */ +#define ACMP_ENABLE_WINDOW_LATCH(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WLATEN_Msk) + +/** + * @brief This macro is used to disable ACMP window latch mode + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear WLATEN (ACMP_CTL[17]) to disable ACMP window latch mode. + * \hideinitializer + */ +#define ACMP_DISABLE_WINDOW_LATCH(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WLATEN_Msk) + +/** + * @brief This macro is used to enable ACMP window compare mode + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set WCMPSEL (ACMP_CTL[18]) to enable ACMP window compare mode. + * When window compare mode is enabled, user can connect the specific analog voltage + * source to either the positive inputs of both comparators or the negative inputs of + * both comparators. The upper bound and lower bound of the designated range are + * determined by the voltages applied to the other inputs of both comparators. If the + * output of a comparator is low and the other comparator outputs high, which means two + * comparators implies the upper and lower bound. User can directly monitor a specific + * analog voltage source via ACMPWO (ACMP_STATUS[16]). + * \hideinitializer + */ +#define ACMP_ENABLE_WINDOW_COMPARE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WCMPSEL_Msk) + +/** + * @brief This macro is used to disable ACMP window compare mode + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear WCMPSEL (ACMP_CTL[18]) to disable ACMP window compare mode. + * \hideinitializer + */ +#define ACMP_DISABLE_WINDOW_COMPARE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WCMPSEL_Msk) + + + + +/* Function prototype declaration */ +void ACMP_Open(ACMP_T *acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysSel); +void ACMP_Close(ACMP_T *acmp, uint32_t u32ChNum); + + + +/*@}*/ /* end of group ACMP_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group ACMP_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __NU_ACMP_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_bpwm.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_bpwm.h new file mode 100644 index 0000000000000000000000000000000000000000..04e65f601a5da2cc0667184ee77c5f46eabcdffd --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_bpwm.h @@ -0,0 +1,361 @@ +/**************************************************************************//** + * @file nu_bpwm.h + * @version V1.00 + * @brief M480 series PWM driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_BPWM_H__ +#define __NU_BPWM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup BPWM_Driver BPWM Driver + @{ +*/ + +/** @addtogroup BPWM_EXPORTED_CONSTANTS BPWM Exported Constants + @{ +*/ +#define BPWM_CHANNEL_NUM (6) /*!< BPWM channel number \hideinitializer */ +#define BPWM_CH_0_MASK (0x1UL) /*!< BPWM channel 0 mask \hideinitializer */ +#define BPWM_CH_1_MASK (0x2UL) /*!< BPWM channel 1 mask \hideinitializer */ +#define BPWM_CH_2_MASK (0x4UL) /*!< BPWM channel 2 mask \hideinitializer */ +#define BPWM_CH_3_MASK (0x8UL) /*!< BPWM channel 3 mask \hideinitializer */ +#define BPWM_CH_4_MASK (0x10UL) /*!< BPWM channel 4 mask \hideinitializer */ +#define BPWM_CH_5_MASK (0x20UL) /*!< BPWM channel 5 mask \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define BPWM_UP_COUNTER (0UL) /*!< Up counter type \hideinitializer */ +#define BPWM_DOWN_COUNTER (1UL) /*!< Down counter type \hideinitializer */ +#define BPWM_UP_DOWN_COUNTER (2UL) /*!< Up-Down counter type \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Aligned Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define BPWM_EDGE_ALIGNED (1UL) /*!< BPWM working in edge aligned type(down count) \hideinitializer */ +#define BPWM_CENTER_ALIGNED (2UL) /*!< BPWM working in center aligned type \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Output Level Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define BPWM_OUTPUT_NOTHING (0UL) /*!< BPWM output nothing \hideinitializer */ +#define BPWM_OUTPUT_LOW (1UL) /*!< BPWM output low \hideinitializer */ +#define BPWM_OUTPUT_HIGH (2UL) /*!< BPWM output high \hideinitializer */ +#define BPWM_OUTPUT_TOGGLE (3UL) /*!< BPWM output toggle \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Synchronous Start Function Control Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define BPWM_SSCTL_SSRC_PWM0 (0UL<SSCTL = ((bpwm)->SSCTL & ~BPWM_SSCTL_SSRC_Msk) | (u32SyncSrc) | BPWM_SSCTL_SSEN0_Msk) + +/** + * @brief Disable timer synchronous start counting function of specified channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @return None + * @details This macro is used to disable timer synchronous start counting function of specified channel(s). + * @note All channels share channel 0's setting. + * \hideinitializer + */ +#define BPWM_DISABLE_TIMER_SYNC(bpwm, u32ChannelMask) ((bpwm)->SSCTL &= ~BPWM_SSCTL_SSEN0_Msk) + +/** + * @brief This macro enable BPWM counter synchronous start counting function. + * @param[in] bpwm The pointer of the specified BPWM module + * @return None + * @details This macro is used to make selected BPWM0 and BPWM1 channel(s) start counting at the same time. + * To configure synchronous start counting channel(s) by BPWM_ENABLE_TIMER_SYNC() and BPWM_DISABLE_TIMER_SYNC(). + * \hideinitializer + */ +#define BPWM_TRIGGER_SYNC_START(bpwm) ((bpwm)->SSTRG = BPWM_SSTRG_CNTSEN_Msk) + +/** + * @brief This macro enable output inverter of specified channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * \hideinitializer + */ +#define BPWM_ENABLE_OUTPUT_INVERTER(bpwm, u32ChannelMask) ((bpwm)->POLCTL = (u32ChannelMask)) + +/** + * @brief This macro get captured rising data + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return None + * \hideinitializer + */ +#define BPWM_GET_CAPTURE_RISING_DATA(bpwm, u32ChannelNum) ((bpwm)->CAPDAT[(u32ChannelNum)].RCAPDAT) + +/** + * @brief This macro get captured falling data + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return None + * \hideinitializer + */ +#define BPWM_GET_CAPTURE_FALLING_DATA(bpwm, u32ChannelNum) ((bpwm)->CAPDAT[(u32ChannelNum)].FCAPDAT) + +/** + * @brief This macro mask output logic to high or low + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32LevelMask Output logic to high or low + * @return None + * @details This macro is used to mask output logic to high or low of specified channel(s). + * @note If u32ChannelMask parameter is 0, then mask function will be disabled. + * \hideinitializer + */ +#define BPWM_MASK_OUTPUT(bpwm, u32ChannelMask, u32LevelMask) \ + { \ + (bpwm)->MSKEN = (u32ChannelMask); \ + (bpwm)->MSK = (u32LevelMask); \ + } + +/** + * @brief This macro set the prescaler of all channels + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFFF + * @return None + * \hideinitializer + */ +#define BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u32Prescaler) ((bpwm)->CLKPSC = (u32Prescaler)) + +/** + * @brief This macro set the duty of the selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32CMR Duty of specified channel. Valid values are between 0~0xFFFF + * @return None + * @note This new setting will take effect on next BPWM period + * \hideinitializer + */ +#define BPWM_SET_CMR(bpwm, u32ChannelNum, u32CMR) ((bpwm)->CMPDAT[(u32ChannelNum)] = (u32CMR)) + +/** + * @brief This macro get the duty of the selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return None + * \hideinitializer + */ +#define BPWM_GET_CMR(bpwm, u32ChannelNum) ((bpwm)->CMPDAT[(u32ChannelNum)]) + +/** + * @brief This macro set the period of all channels + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF + * @return None + * @note This new setting will take effect on next BPWM period + * @note BPWM counter will stop if period length set to 0 + * \hideinitializer + */ +#define BPWM_SET_CNR(bpwm, u32ChannelNum, u32CNR) ((bpwm)->PERIOD = (u32CNR)) + +/** + * @brief This macro get the period of all channels + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * \hideinitializer + */ +#define BPWM_GET_CNR(bpwm, u32ChannelNum) ((bpwm)->PERIOD) + +/** + * @brief This macro set the BPWM aligned type + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @param[in] u32AlignedType BPWM aligned type, valid values are: + * - \ref BPWM_EDGE_ALIGNED + * - \ref BPWM_CENTER_ALIGNED + * @return None + * @note All channels share channel 0's setting. + * \hideinitializer + */ +#define BPWM_SET_ALIGNED_TYPE(bpwm, u32ChannelMask, u32AlignedType) ((bpwm)->CTL1 = (u32AlignedType)) + +/** + * @brief Clear counter of channel 0 + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @return None + * @details This macro is used to clear counter of channel 0 + * \hideinitializer + */ +#define BPWM_CLR_COUNTER(bpwm, u32ChannelMask) ((bpwm)->CNTCLR = (BPWM_CNTCLR_CNTCLR0_Msk)) + +/** + * @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32ZeroLevel output level at zero point, valid values are: + * - \ref BPWM_OUTPUT_NOTHING + * - \ref BPWM_OUTPUT_LOW + * - \ref BPWM_OUTPUT_HIGH + * - \ref BPWM_OUTPUT_TOGGLE + * @param[in] u32CmpUpLevel output level at compare up point, valid values are: + * - \ref BPWM_OUTPUT_NOTHING + * - \ref BPWM_OUTPUT_LOW + * - \ref BPWM_OUTPUT_HIGH + * - \ref BPWM_OUTPUT_TOGGLE + * @param[in] u32PeriodLevel output level at period(center) point, valid values are: + * - \ref BPWM_OUTPUT_NOTHING + * - \ref BPWM_OUTPUT_LOW + * - \ref BPWM_OUTPUT_HIGH + * - \ref BPWM_OUTPUT_TOGGLE + * @param[in] u32CmpDownLevel output level at compare down point, valid values are: + * - \ref BPWM_OUTPUT_NOTHING + * - \ref BPWM_OUTPUT_LOW + * - \ref BPWM_OUTPUT_HIGH + * - \ref BPWM_OUTPUT_TOGGLE + * @return None + * @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s) + * \hideinitializer + */ +#define BPWM_SET_OUTPUT_LEVEL(bpwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \ + do{ \ + int i; \ + for(i = 0; i < 6; i++) { \ + if((u32ChannelMask) & (1 << i)) { \ + (bpwm)->WGCTL0 = (((bpwm)->WGCTL0 & ~(3UL << (2 * i))) | ((u32ZeroLevel) << (2 * i))); \ + (bpwm)->WGCTL0 = (((bpwm)->WGCTL0 & ~(3UL << (BPWM_WGCTL0_PRDPCTLn_Pos + (2 * i)))) | ((u32PeriodLevel) << (BPWM_WGCTL0_PRDPCTLn_Pos + (2 * i)))); \ + (bpwm)->WGCTL1 = (((bpwm)->WGCTL1 & ~(3UL << (2 * i))) | ((u32CmpUpLevel) << (2 * i))); \ + (bpwm)->WGCTL1 = (((bpwm)->WGCTL1 & ~(3UL << (BPWM_WGCTL1_CMPDCTLn_Pos + (2 * i)))) | ((u32CmpDownLevel) << (BPWM_WGCTL1_CMPDCTLn_Pos + (2 * i)))); \ + } \ + } \ + }while(0) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define BPWM functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge); +uint32_t BPWM_ConfigOutputChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle); +void BPWM_Start(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_Stop(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_ForceStop(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_EnableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition); +void BPWM_DisableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition); +uint32_t BPWM_GetADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_DisableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_EnableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_DisableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_EnableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge); +void BPWM_DisableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge); +void BPWM_ClearCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge); +uint32_t BPWM_GetCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType); +void BPWM_DisableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +uint32_t BPWM_GetDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType); +void BPWM_DisablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +uint32_t BPWM_GetPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_DisableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +uint32_t BPWM_GetZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); +void BPWM_DisableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); +void BPWM_SetClockSource(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel); +uint32_t BPWM_GetWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); + + +/*@}*/ /* end of group BPWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group BPWM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_BPWM_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_can.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_can.h new file mode 100644 index 0000000000000000000000000000000000000000..cfc1c1fd1632d15caf6d98af7c2a65513b7a5b79 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_can.h @@ -0,0 +1,192 @@ +/**************************************************************************//** + * @file nu_can.h + * @version V2.00 + * @brief M480 Series CAN Driver Header File + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __NU_CAN_H__ +#define __NU_CAN_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CAN_Driver CAN Driver + @{ +*/ + +/** @addtogroup CAN_EXPORTED_CONSTANTS CAN Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* CAN Test Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CAN_NORMAL_MODE 0ul /*!< CAN select normal mode \hideinitializer */ +#define CAN_BASIC_MODE 1ul /*!< CAN select basic mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Message ID Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CAN_STD_ID 0ul /*!< CAN select standard ID \hideinitializer */ +#define CAN_EXT_ID 1ul /*!< CAN select extended ID \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Message Frame Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CAN_REMOTE_FRAME 0ul /*!< CAN frame select remote frame \hideinitializer */ +#define CAN_DATA_FRAME 1ul /*!< CAN frame select data frame \hideinitializer */ + +/*@}*/ /* end of group CAN_EXPORTED_CONSTANTS */ + + +/** @addtogroup CAN_EXPORTED_STRUCTS CAN Exported Structs + @{ +*/ +/** + * @details CAN message structure + */ +typedef struct +{ + uint32_t IdType; /*!< ID type */ + uint32_t FrameType; /*!< Frame type */ + uint32_t Id; /*!< Message ID */ + uint8_t DLC; /*!< Data length */ + uint8_t Data[8]; /*!< Data */ +} STR_CANMSG_T; + +/** + * @details CAN mask message structure + */ +typedef struct +{ + uint8_t u8Xtd; /*!< Extended ID */ + uint8_t u8Dir; /*!< Direction */ + uint32_t u32Id; /*!< Message ID */ + uint8_t u8IdType; /*!< ID type*/ +} STR_CANMASK_T; + +/*@}*/ /* end of group CAN_EXPORTED_STRUCTS */ + +/** @cond HIDDEN_SYMBOLS */ +#define MSG(id) (id) +/** @endcond HIDDEN_SYMBOLS */ + +/** @addtogroup CAN_EXPORTED_FUNCTIONS CAN Exported Functions + @{ +*/ + +/** + * @brief Get interrupt status. + * + * @param[in] can The base address of can module. + * + * @return CAN module status register value. + * + * @details Status Interrupt is generated by bits BOff (CAN_STATUS[7]), EWarn (CAN_STATUS[6]), + * EPass (CAN_STATUS[5]), RxOk (CAN_STATUS[4]), TxOk (CAN_STATUS[3]), and LEC (CAN_STATUS[2:0]). + * \hideinitializer + */ +#define CAN_GET_INT_STATUS(can) ((can)->STATUS) + +/** + * @brief Get specified interrupt pending status. + * + * @param[in] can The base address of can module. + * + * @return The source of the interrupt. + * + * @details If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt + * with the highest priority, disregarding their chronological order. + * \hideinitializer + */ +#define CAN_GET_INT_PENDING_STATUS(can) ((can)->IIDR) + +/** + * @brief Disable wake-up function. + * + * @param[in] can The base address of can module. + * + * @return None + * + * @details The macro is used to disable wake-up function. + * \hideinitializer + */ +#define CAN_DISABLE_WAKEUP(can) ((can)->WU_EN = 0ul) + +/** + * @brief Enable wake-up function. + * + * @param[in] can The base address of can module. + * + * @return None + * + * @details User can wake-up system when there is a falling edge in the CAN_Rx pin. + * \hideinitializer + */ +#define CAN_ENABLE_WAKEUP(can) ((can)->WU_EN = CAN_WU_EN_WAKUP_EN_Msk) + +/** + * @brief Get specified Message Object new data into bit value. + * + * @param[in] can The base address of can module. + * @param[in] u32MsgNum Specified Message Object number, valid value are from 0 to 31. + * + * @return Specified Message Object new data into bit value. + * + * @details The NewDat bit (CAN_IFn_MCON[15]) of a specific Message Object can be set/reset by the software through the IFn Message Interface Registers + * or by the Message Handler after reception of a Data Frame or after a successful transmission. + * \hideinitializer + */ +#define CAN_GET_NEW_DATA_IN_BIT(can, u32MsgNum) ((u32MsgNum) < 16 ? (can)->NDAT1 & (1 << (u32MsgNum)) : (can)->NDAT2 & (1 << ((u32MsgNum)-16))) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define CAN functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +uint32_t CAN_SetBaudRate(CAN_T *tCAN, uint32_t u32BaudRate); +uint32_t CAN_Open(CAN_T *tCAN, uint32_t u32BaudRate, uint32_t u32Mode); +void CAN_Close(CAN_T *tCAN); +void CAN_CLR_INT_PENDING_BIT(CAN_T *tCAN, uint8_t u32MsgNum); +void CAN_EnableInt(CAN_T *tCAN, uint32_t u32Mask); +void CAN_DisableInt(CAN_T *tCAN, uint32_t u32Mask); +int32_t CAN_Transmit(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg); +int32_t CAN_Receive(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg); +int32_t CAN_SetMultiRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32MsgCount, uint32_t u32IDType, uint32_t u32ID); +int32_t CAN_SetRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID); +int32_t CAN_SetRxMsgAndMsk(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID, uint32_t u32IDMask); +int32_t CAN_SetTxMsg(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg); +int32_t CAN_TriggerTxMsg(CAN_T *tCAN, uint32_t u32MsgNum); +int32_t CAN_BasicSendMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg); +int32_t CAN_BasicReceiveMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg); +void CAN_EnterInitMode(CAN_T *tCAN, uint8_t u8Mask); +void CAN_EnterTestMode(CAN_T *tCAN, uint8_t u8TestMask); +void CAN_LeaveTestMode(CAN_T *tCAN); +uint32_t CAN_GetCANBitRate(CAN_T *tCAN); +uint32_t CAN_IsNewDataReceived(CAN_T *tCAN, uint8_t u8MsgObj); +void CAN_LeaveInitMode(CAN_T *tCAN); +int32_t CAN_SetRxMsgObjAndMsk(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint32_t u32idmask, uint8_t u8singleOrFifoLast); +int32_t CAN_SetRxMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint8_t u8singleOrFifoLast); +void CAN_WaitMsg(CAN_T *tCAN); +int32_t CAN_ReadMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8Release, STR_CANMSG_T* pCanMsg); + +/*@}*/ /* end of group CAN_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CAN_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /*__NU_CAN_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_ccap.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_ccap.h new file mode 100644 index 0000000000000000000000000000000000000000..a7927f36b71aeb48a4434e7b14d2b30a1d3bdd0e --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_ccap.h @@ -0,0 +1,165 @@ +/**************************************************************************//** + * @file nu_ccap.h + * @version V1.00 + * @brief M480 Series CCAP Driver Header File + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __NU_CCAP_H__ +#define __NU_CCAP_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CCAP_Driver CCAP Driver + @{ +*/ + +/** @addtogroup CCAP_EXPORTED_CONSTANTS CCAP Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* CTL constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CCAP_CTL_CCAPEN (1ul<CTL & CCAP_CTL_CCAPEN_Msk)?0:1) + +/** + * @brief Clear CCAP flag + * + * @param[in] u32IntMask interrupt flags settings. It could be + * - \ref CCAP_INT_VINTF_Msk + * - \ref CCAP_INT_MEINTF_Msk + * - \ref CCAP_INT_ADDRMINTF_Msk + * - \ref CCAP_INT_MDINTF_Msk + * + * @return TRUE(Enable) or FALSE(Disable) + * + * @details Clear Image Capture Interface interrupt flag + * \hideinitializer + */ +#define CCAP_CLR_INT_FLAG(u32IntMask) (CCAP->INT |=u32IntMask) + +/** + * @brief Get CCAP Interrupt status + * + * @return TRUE(Enable) or FALSE(Disable) + * + * @details Get Image Capture Interface interrupt status. + * \hideinitializer + */ +#define CCAP_GET_INT_STS() (CCAP->INT) + +void CCAP_Open(uint32_t u32InFormat, uint32_t u32OutFormet); +void CCAP_SetCroppingWindow(uint32_t u32VStart,uint32_t u32HStart, uint32_t u32Height, uint32_t u32Width); +void CCAP_SetPacketBuf(uint32_t u32Address ); +void CCAP_Close(void); +void CCAP_EnableInt(uint32_t u32IntMask); +void CCAP_DisableInt(uint32_t u32IntMask); +void CCAP_Start(void); +void CCAP_Stop(uint32_t u32FrameComplete); +void CCAP_SetPacketScaling(uint32_t u32VNumerator, uint32_t u32VDenominator, uint32_t u32HNumerator, uint32_t u32HDenominator); +void CCAP_SetPacketStride(uint32_t u32Stride ); +void CCAP_EnableMono(uint32_t u32Interface); +void CCAP_DisableMono(void); +void CCAP_EnableLumaYOne(uint32_t u32th); +void CCAP_DisableLumaYOne(void); + +/*@}*/ /* end of group CCAP_EXPORTED_FUNCTIONS */ + + + +/*@}*/ /* end of group CCAP_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif //__NU_CCAP_H__ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_clk.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_clk.h new file mode 100644 index 0000000000000000000000000000000000000000..9dc88b552d809efe9b32130a31a14a5202a6ce3c --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_clk.h @@ -0,0 +1,714 @@ +/**************************************************************************//** + * @file CLK.h + * @version V1.0 + * @brief M480 Series CLK Driver Header File + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __NU_CLK_H__ +#define __NU_CLK_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CLK_Driver CLK Driver + @{ +*/ + +/** @addtogroup CLK_EXPORTED_CONSTANTS CLK Exported Constants + @{ +*/ + + +#define FREQ_25MHZ 25000000UL /*!< 25 MHz \hideinitializer */ +#define FREQ_50MHZ 50000000UL /*!< 50 MHz \hideinitializer */ +#define FREQ_72MHZ 72000000UL /*!< 72 MHz \hideinitializer */ +#define FREQ_80MHZ 80000000UL /*!< 80 MHz \hideinitializer */ +#define FREQ_100MHZ 100000000UL /*!< 100 MHz \hideinitializer */ +#define FREQ_125MHZ 125000000UL /*!< 125 MHz \hideinitializer */ +#define FREQ_160MHZ 160000000UL /*!< 160 MHz \hideinitializer */ +#define FREQ_192MHZ 192000000UL /*!< 192 MHz \hideinitializer */ +#define FREQ_200MHZ 200000000UL /*!< 200 MHz \hideinitializer */ +#define FREQ_250MHZ 250000000UL /*!< 250 MHz \hideinitializer */ +#define FREQ_500MHZ 500000000UL /*!< 500 MHz \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* CLKSEL0 constant definitions. (Write-protection) */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_CLKSEL0_HCLKSEL_HXT (0x0UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL0_HCLKSEL_LXT (0x1UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL0_HCLKSEL_PLL (0x2UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from PLL \hideinitializer */ +#define CLK_CLKSEL0_HCLKSEL_LIRC (0x3UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from low speed oscillator \hideinitializer */ +#define CLK_CLKSEL0_HCLKSEL_HIRC (0x7UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL0_STCLKSEL_HXT (0x0UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL0_STCLKSEL_LXT (0x1UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL0_STCLKSEL_HXT_DIV2 (0x2UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from HXT/2 \hideinitializer */ +#define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 (0x3UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from HCLK/2 \hideinitializer */ +#define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 (0x7UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from HIRC/2 \hideinitializer */ +#define CLK_CLKSEL0_STCLKSEL_HCLK (0x01UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< Select SysTick clock source from HCLK \hideinitializer */ + +#define CLK_CLKSEL0_CCAPSEL_HXT (0x0UL << CLK_CLKSEL0_CCAPSEL_Pos) /*!< Select CCAP clock source from HXT \hideinitializer */ +#define CLK_CLKSEL0_CCAPSEL_PLL (0x1UL << CLK_CLKSEL0_CCAPSEL_Pos) /*!< Select CCAP clock source from PLL \hideinitializer */ +#define CLK_CLKSEL0_CCAPSEL_HCLK (0x2UL << CLK_CLKSEL0_CCAPSEL_Pos) /*!< Select CCAP clock source from HCLK \hideinitializer */ +#define CLK_CLKSEL0_CCAPSEL_HIRC (0x3UL << CLK_CLKSEL0_CCAPSEL_Pos) /*!< Select CCAP clock source from HIRC \hideinitializer */ + + +#if(0) +#define CLK_CLKSEL0_PCLK0DIV1 (0x0UL << CLK_CLKSEL0_PCLK0SEL_Pos) /*!< Select PCLK0 clock source from HCLK \hideinitializer */ +#define CLK_CLKSEL0_PCLK0DIV2 (0x1UL << CLK_CLKSEL0_PCLK0SEL_Pos) /*!< Select PCLK0 clock source from 1/2 HCLK \hideinitializer */ + +#define CLK_CLKSEL0_PCLK1DIV1 (0x0UL << CLK_CLKSEL0_PCLK1SEL_Pos) /*!< Select PCLK1 clock source from HCLK \hideinitializer */ +#define CLK_CLKSEL0_PCLK1DIV2 (0x1UL << CLK_CLKSEL0_PCLK1SEL_Pos) /*!< Select PCLK1 clock source from 1/2 HCLK \hideinitializer */ +#endif + +#define CLK_CLKSEL0_CCAPSEL_HXT (0x0UL << CLK_CLKSEL0_CCAPSEL_Pos) /*!< Select CCAP clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL0_CCAPSEL_PLL (0x1UL << CLK_CLKSEL0_CCAPSEL_Pos) /*!< Select CCAP clock source from PLL \hideinitializer */ +#define CLK_CLKSEL0_CCAPSEL_HIRC (0x3UL << CLK_CLKSEL0_CCAPSEL_Pos) /*!< Select CCAP clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL0_CCAPSEL_HCLK (0x2UL << CLK_CLKSEL0_CCAPSEL_Pos) /*!< Select CCAP clock source from HCLK \hideinitializer */ + +#define CLK_CLKSEL0_SDH0SEL_HXT (0x0UL << CLK_CLKSEL0_SDH0SEL_Pos) /*!< Select SDH0 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL0_SDH0SEL_PLL (0x1UL << CLK_CLKSEL0_SDH0SEL_Pos) /*!< Select SDH0 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL0_SDH0SEL_HIRC (0x3UL << CLK_CLKSEL0_SDH0SEL_Pos) /*!< Select SDH0 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL0_SDH0SEL_HCLK (0x2UL << CLK_CLKSEL0_SDH0SEL_Pos) /*!< Select SDH0 clock source from HCLK \hideinitializer */ + +#define CLK_CLKSEL0_SDH1SEL_HXT (0x0UL << CLK_CLKSEL0_SDH1SEL_Pos) /*!< Select SDH1 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL0_SDH1SEL_PLL (0x1UL << CLK_CLKSEL0_SDH1SEL_Pos) /*!< Select SDH1 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL0_SDH1SEL_HIRC (0x3UL << CLK_CLKSEL0_SDH1SEL_Pos) /*!< Select SDH1 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL0_SDH1SEL_HCLK (0x2UL << CLK_CLKSEL0_SDH1SEL_Pos) /*!< Select SDH1 clock source from HCLK \hideinitializer */ + +#define CLK_CLKSEL0_USBSEL_RC48M (0x0UL << CLK_CLKSEL0_USBSEL_Pos) /*!< Select USB clock source from RC48M \hideinitializer */ +#define CLK_CLKSEL0_USBSEL_PLL (0x1UL << CLK_CLKSEL0_USBSEL_Pos) /*!< Select USB clock source from PLL \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* CLKSEL1 constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_CLKSEL1_WDTSEL_LXT (0x1UL << CLK_CLKSEL1_WDTSEL_Pos) /*!< Select WDT clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL1_WDTSEL_LIRC (0x3UL << CLK_CLKSEL1_WDTSEL_Pos) /*!< Select WDT clock source from low speed oscillator \hideinitializer */ +#define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 (0x2UL << CLK_CLKSEL1_WDTSEL_Pos) /*!< Select WDT clock source from HCLK/2048 \hideinitializer */ + +#define CLK_CLKSEL1_TMR0SEL_HXT (0x0UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL1_TMR0SEL_LXT (0x1UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL1_TMR0SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from low speed oscillator \hideinitializer */ +#define CLK_CLKSEL1_TMR0SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL1_TMR0SEL_PCLK0 (0x2UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from PCLK0 \hideinitializer */ +#define CLK_CLKSEL1_TMR0SEL_EXT (0x3UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from external trigger \hideinitializer */ + +#define CLK_CLKSEL1_TMR1SEL_HXT (0x0UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL1_TMR1SEL_LXT (0x1UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL1_TMR1SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from low speed oscillator \hideinitializer */ +#define CLK_CLKSEL1_TMR1SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL1_TMR1SEL_PCLK0 (0x2UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from PCLK0 \hideinitializer */ +#define CLK_CLKSEL1_TMR1SEL_EXT (0x3UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from external trigger \hideinitializer */ + +#define CLK_CLKSEL1_TMR2SEL_HXT (0x0UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL1_TMR2SEL_LXT (0x1UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL1_TMR2SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from low speed oscillator \hideinitializer */ +#define CLK_CLKSEL1_TMR2SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL1_TMR2SEL_PCLK1 (0x2UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from PCLK1 \hideinitializer */ +#define CLK_CLKSEL1_TMR2SEL_EXT (0x3UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from external trigger \hideinitializer */ + +#define CLK_CLKSEL1_TMR3SEL_HXT (0x0UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL1_TMR3SEL_LXT (0x1UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL1_TMR3SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from low speed oscillator \hideinitializer */ +#define CLK_CLKSEL1_TMR3SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL1_TMR3SEL_PCLK1 (0x2UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from PCLK1 \hideinitializer */ +#define CLK_CLKSEL1_TMR3SEL_EXT (0x3UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from external trigger \hideinitializer */ + +#define CLK_CLKSEL1_UART0SEL_HXT (0x0UL << CLK_CLKSEL1_UART0SEL_Pos) /*!< Select UART0 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL1_UART0SEL_LXT (0x2UL << CLK_CLKSEL1_UART0SEL_Pos) /*!< Select UART0 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL1_UART0SEL_PLL (0x1UL << CLK_CLKSEL1_UART0SEL_Pos) /*!< Select UART0 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL1_UART0SEL_HIRC (0x3UL << CLK_CLKSEL1_UART0SEL_Pos) /*!< Select UART0 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL1_UART1SEL_HXT (0x0UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UART1 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL1_UART1SEL_LXT (0x2UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UART1 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL1_UART1SEL_PLL (0x1UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UART1 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL1_UART1SEL_HIRC (0x3UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UART1 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL1_CLKOSEL_HXT (0x0UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL1_CLKOSEL_LXT (0x1UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL1_CLKOSEL_HIRC (0x3UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL1_CLKOSEL_HCLK (0x2UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from HCLK \hideinitializer */ + +#define CLK_CLKSEL1_WWDTSEL_LIRC (0x3UL << CLK_CLKSEL1_WWDTSEL_Pos) /*!< Select WWDT clock source from low speed oscillator \hideinitializer */ +#define CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 (0x2UL << CLK_CLKSEL1_WWDTSEL_Pos) /*!< Select WWDT clock source from HCLK/2048 \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* CLKSEL2 constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_CLKSEL2_QSPI0SEL_HXT (0x0UL << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Select QSPI0 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL2_QSPI0SEL_PLL (0x1UL << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Select QSPI0 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL2_QSPI0SEL_HIRC (0x3UL << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Select QSPI0 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL2_QSPI0SEL_PCLK0 (0x2UL << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Select QSPI0 clock source from PCLK0 \hideinitializer */ + +#define CLK_CLKSEL2_SPI0SEL_HXT (0x0UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL2_SPI0SEL_PLL (0x1UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL2_SPI0SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL2_SPI0SEL_PCLK1 (0x2UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from PCLK1 \hideinitializer */ + +#define CLK_CLKSEL2_SPI1SEL_HXT (0x0UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL2_SPI1SEL_PLL (0x1UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL2_SPI1SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL2_SPI1SEL_PCLK0 (0x2UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from PCLK0 \hideinitializer */ + +#define CLK_CLKSEL2_EPWM0SEL_PLL (0x0UL << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< Select EPWM0 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL2_EPWM0SEL_PCLK0 (0x1UL << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< Select EPWM0 clock source from PCLK0 \hideinitializer */ + +#define CLK_CLKSEL2_EPWM1SEL_PLL (0x0UL << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< Select EPWM1 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL2_EPWM1SEL_PCLK1 (0x1UL << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< Select EPWM1 clock source from PCLK1 \hideinitializer */ + +#define CLK_CLKSEL2_BPWM0SEL_PLL (0x0UL << CLK_CLKSEL2_BPWM0SEL_Pos) /*!< Select BPWM0 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL2_BPWM0SEL_PCLK0 (0x1UL << CLK_CLKSEL2_BPWM0SEL_Pos) /*!< Select BPWM0 clock source from PCLK0 \hideinitializer */ + +#define CLK_CLKSEL2_BPWM1SEL_PLL (0x0UL << CLK_CLKSEL2_BPWM1SEL_Pos) /*!< Select BPWM1 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL2_BPWM1SEL_PCLK1 (0x1UL << CLK_CLKSEL2_BPWM1SEL_Pos) /*!< Select BPWM1 clock source from PCLK1 \hideinitializer */ + +#define CLK_CLKSEL2_SPI2SEL_HXT (0x0UL << CLK_CLKSEL2_SPI2SEL_Pos) /*!< Select SPI2 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL2_SPI2SEL_PLL (0x1UL << CLK_CLKSEL2_SPI2SEL_Pos) /*!< Select SPI2 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL2_SPI2SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI2SEL_Pos) /*!< Select SPI2 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL2_SPI2SEL_PCLK1 (0x2UL << CLK_CLKSEL2_SPI2SEL_Pos) /*!< Select SPI2 clock source from PCLK1 \hideinitializer */ + +#define CLK_CLKSEL2_SPI3SEL_HXT (0x0UL << CLK_CLKSEL2_SPI3SEL_Pos) /*!< Select SPI3 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL2_SPI3SEL_PLL (0x1UL << CLK_CLKSEL2_SPI3SEL_Pos) /*!< Select SPI3 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL2_SPI3SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI3SEL_Pos) /*!< Select SPI3 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL2_SPI3SEL_PCLK0 (0x2UL << CLK_CLKSEL2_SPI3SEL_Pos) /*!< Select SPI3 clock source from PCLK0 \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* CLKSEL3 constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_CLKSEL3_SC0SEL_HXT (0x0UL << CLK_CLKSEL3_SC0SEL_Pos) /*!< Select SC0 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL3_SC0SEL_PLL (0x1UL << CLK_CLKSEL3_SC0SEL_Pos) /*!< Select SC0 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL3_SC0SEL_HIRC (0x3UL << CLK_CLKSEL3_SC0SEL_Pos) /*!< Select SC0 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL3_SC0SEL_PCLK0 (0x2UL << CLK_CLKSEL3_SC0SEL_Pos) /*!< Select SC0 clock source from PCLK0 \hideinitializer */ + +#define CLK_CLKSEL3_SC1SEL_HXT (0x0UL << CLK_CLKSEL3_SC1SEL_Pos) /*!< Select SC1 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL3_SC1SEL_PLL (0x1UL << CLK_CLKSEL3_SC1SEL_Pos) /*!< Select SC1 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL3_SC1SEL_HIRC (0x3UL << CLK_CLKSEL3_SC1SEL_Pos) /*!< Select SC1 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL3_SC1SEL_PCLK1 (0x2UL << CLK_CLKSEL3_SC1SEL_Pos) /*!< Select SC1 clock source from PCLK1 \hideinitializer */ + +#define CLK_CLKSEL3_SC2SEL_HXT (0x0UL << CLK_CLKSEL3_SC2SEL_Pos) /*!< Select SC2 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL3_SC2SEL_PLL (0x1UL << CLK_CLKSEL3_SC2SEL_Pos) /*!< Select SC2 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL3_SC2SEL_HIRC (0x3UL << CLK_CLKSEL3_SC2SEL_Pos) /*!< Select SC2 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL3_SC2SEL_PCLK0 (0x2UL << CLK_CLKSEL3_SC2SEL_Pos) /*!< Select SC2 clock source from PCLK0 \hideinitializer */ + +#define CLK_CLKSEL3_RTCSEL_LXT (0x0UL << CLK_CLKSEL3_RTCSEL_Pos) /*!< Select RTC clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL3_RTCSEL_LIRC (0x1UL << CLK_CLKSEL3_RTCSEL_Pos) /*!< Select RTC clock source from low speed oscillator \hideinitializer */ + +#define CLK_CLKSEL3_QSPI1SEL_HXT (0x0UL << CLK_CLKSEL3_QSPI1SEL_Pos) /*!< Select QSPI1 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL3_QSPI1SEL_PLL (0x1UL << CLK_CLKSEL3_QSPI1SEL_Pos) /*!< Select QSPI1 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL3_QSPI1SEL_HIRC (0x3UL << CLK_CLKSEL3_QSPI1SEL_Pos) /*!< Select QSPI1 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL3_QSPI1SEL_PCLK1 (0x2UL << CLK_CLKSEL3_QSPI1SEL_Pos) /*!< Select QSPI1 clock source from PCLK1 \hideinitializer */ + +#define CLK_CLKSEL3_I2S0SEL_HXT (0x0UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL3_I2S0SEL_PLL (0x1UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL3_I2S0SEL_HIRC (0x3UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL3_I2S0SEL_PCLK0 (0x2UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from PCLK0 \hideinitializer */ + +#define CLK_CLKSEL3_UART2SEL_HXT (0x0UL << CLK_CLKSEL3_UART2SEL_Pos) /*!< Select UART2 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL3_UART2SEL_LXT (0x2UL << CLK_CLKSEL3_UART2SEL_Pos) /*!< Select UART2 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL3_UART2SEL_PLL (0x1UL << CLK_CLKSEL3_UART2SEL_Pos) /*!< Select UART2 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL3_UART2SEL_HIRC (0x3UL << CLK_CLKSEL3_UART2SEL_Pos) /*!< Select UART2 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL3_UART3SEL_HXT (0x0UL << CLK_CLKSEL3_UART3SEL_Pos) /*!< Select UART3 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL3_UART3SEL_LXT (0x2UL << CLK_CLKSEL3_UART3SEL_Pos) /*!< Select UART3 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL3_UART3SEL_PLL (0x1UL << CLK_CLKSEL3_UART3SEL_Pos) /*!< Select UART3 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL3_UART3SEL_HIRC (0x3UL << CLK_CLKSEL3_UART3SEL_Pos) /*!< Select UART3 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL3_UART4SEL_HXT (0x0UL << CLK_CLKSEL3_UART4SEL_Pos) /*!< Select UART4 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL3_UART4SEL_LXT (0x2UL << CLK_CLKSEL3_UART4SEL_Pos) /*!< Select UART4 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL3_UART4SEL_PLL (0x1UL << CLK_CLKSEL3_UART4SEL_Pos) /*!< Select UART4 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL3_UART4SEL_HIRC (0x3UL << CLK_CLKSEL3_UART4SEL_Pos) /*!< Select UART4 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL3_UART5SEL_HXT (0x0UL << CLK_CLKSEL3_UART5SEL_Pos) /*!< Select UART5 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL3_UART5SEL_LXT (0x2UL << CLK_CLKSEL3_UART5SEL_Pos) /*!< Select UART5 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL3_UART5SEL_PLL (0x1UL << CLK_CLKSEL3_UART5SEL_Pos) /*!< Select UART5 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL3_UART5SEL_HIRC (0x3UL << CLK_CLKSEL3_UART5SEL_Pos) /*!< Select UART5 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL3_UART6SEL_HXT (0x0UL << CLK_CLKSEL3_UART6SEL_Pos) /*!< Select UART6 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL3_UART6SEL_LXT (0x2UL << CLK_CLKSEL3_UART6SEL_Pos) /*!< Select UART6 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL3_UART6SEL_PLL (0x1UL << CLK_CLKSEL3_UART6SEL_Pos) /*!< Select UART6 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL3_UART6SEL_HIRC (0x3UL << CLK_CLKSEL3_UART6SEL_Pos) /*!< Select UART6 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL3_UART7SEL_HXT (0x0UL << CLK_CLKSEL3_UART7SEL_Pos) /*!< Select UART7 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL3_UART7SEL_LXT (0x2UL << CLK_CLKSEL3_UART7SEL_Pos) /*!< Select UART7 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL3_UART7SEL_PLL (0x1UL << CLK_CLKSEL3_UART7SEL_Pos) /*!< Select UART7 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL3_UART7SEL_HIRC (0x3UL << CLK_CLKSEL3_UART7SEL_Pos) /*!< Select UART7 clock source from high speed oscillator \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* CLKDIV0 constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_CLKDIV0_HCLK(x) (((x) - 1UL) << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLKDIV0 Setting for HCLK clock divider. It could be 1~16 \hideinitializer */ +#define CLK_CLKDIV0_USB(x) (((x) - 1UL) << CLK_CLKDIV0_USBDIV_Pos) /*!< CLKDIV0 Setting for USB clock divider. It could be 1~16 \hideinitializer */ +#define CLK_CLKDIV0_SDH0(x) (((x) - 1UL) << CLK_CLKDIV0_SDH0DIV_Pos) /*!< CLKDIV0 Setting for SDH0 clock divider. It could be 1~256 \hideinitializer */ +#define CLK_CLKDIV0_UART0(x) (((x) - 1UL) << CLK_CLKDIV0_UART0DIV_Pos) /*!< CLKDIV0 Setting for UART0 clock divider. It could be 1~16 \hideinitializer */ +#define CLK_CLKDIV0_UART1(x) (((x) - 1UL) << CLK_CLKDIV0_UART1DIV_Pos) /*!< CLKDIV0 Setting for UART1 clock divider. It could be 1~16 \hideinitializer */ +#define CLK_CLKDIV0_EADC(x) (((x) - 1UL) << CLK_CLKDIV0_EADCDIV_Pos) /*!< CLKDIV0 Setting for EADC clock divider. It could be 1~256 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* CLKDIV1 constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_CLKDIV1_SC0(x) (((x) - 1UL) << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLKDIV1 Setting for SC0 clock divider. It could be 1~256 \hideinitializer */ +#define CLK_CLKDIV1_SC1(x) (((x) - 1UL) << CLK_CLKDIV1_SC1DIV_Pos) /*!< CLKDIV1 Setting for SC1 clock divider. It could be 1~256 \hideinitializer */ +#define CLK_CLKDIV1_SC2(x) (((x) - 1UL) << CLK_CLKDIV1_SC2DIV_Pos) /*!< CLKDIV1 Setting for SC2 clock divider. It could be 1~256 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* CLKDIV2 constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_CLKDIV2_I2S0(x) (((x) - 1UL) << CLK_CLKDIV2_I2SDIV_Pos) /*!< CLKDIV2 Setting for I2S0 clock divider. It could be 1~16 */ +#define CLK_CLKDIV2_EADC1(x) (((x) - 1UL) << CLK_CLKDIV2_EADC1DIV_Pos) /*!< CLKDIV2 Setting for EADC1 clock divider. It could be 1~256 */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* CLKDIV3 constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_CLKDIV3_CCAP(x) (((x) - 1UL) << CLK_CLKDIV3_CCAPDIV_Pos) /*!< CLKDIV3 Setting for CCAP clock divider. It could be 1~256 */ +#define CLK_CLKDIV3_VSENSE(x) (((x) - 1UL) << CLK_CLKDIV3_VSENSEDIV_Pos) /*!< CLKDIV3 Setting for VSENSE clock divider. It could be 1~256 */ +#define CLK_CLKDIV3_EMAC(x) (((x) - 1UL) << CLK_CLKDIV3_EMACDIV_Pos) /*!< CLKDIV3 Setting for EMAC clock divider. It could be 1~256 \hideinitializer */ +#define CLK_CLKDIV3_SDH1(x) (((x) - 1UL) << CLK_CLKDIV3_SDH1DIV_Pos) /*!< CLKDIV3 Setting for SDH1 clock divider. It could be 1~256 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* CLKDIV4 constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_CLKDIV4_UART2(x) (((x) - 1UL) << CLK_CLKDIV4_UART2DIV_Pos) /*!< CLKDIV4 Setting for UART2 clock divider. It could be 1~16 \hideinitializer */ +#define CLK_CLKDIV4_UART3(x) (((x) - 1UL) << CLK_CLKDIV4_UART3DIV_Pos) /*!< CLKDIV4 Setting for UART3 clock divider. It could be 1~16 \hideinitializer */ +#define CLK_CLKDIV4_UART4(x) (((x) - 1UL) << CLK_CLKDIV4_UART4DIV_Pos) /*!< CLKDIV4 Setting for UART4 clock divider. It could be 1~16 \hideinitializer */ +#define CLK_CLKDIV4_UART5(x) (((x) - 1UL) << CLK_CLKDIV4_UART5DIV_Pos) /*!< CLKDIV4 Setting for UART5 clock divider. It could be 1~16 \hideinitializer */ +#define CLK_CLKDIV4_UART6(x) (((x) - 1UL) << CLK_CLKDIV4_UART6DIV_Pos) /*!< CLKDIV4 Setting for UART6 clock divider. It could be 1~16 */ +#define CLK_CLKDIV4_UART7(x) (((x) - 1UL) << CLK_CLKDIV4_UART7DIV_Pos) /*!< CLKDIV4 Setting for UART7 clock divider. It could be 1~16 */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* PCLKDIV constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_PCLKDIV_PCLK0DIV1 (0x0UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = HCLK \hideinitializer */ +#define CLK_PCLKDIV_PCLK0DIV2 (0x1UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/2 HCLK \hideinitializer */ +#define CLK_PCLKDIV_PCLK0DIV4 (0x2UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/4 HCLK \hideinitializer */ +#define CLK_PCLKDIV_PCLK0DIV8 (0x3UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/8 HCLK \hideinitializer */ +#define CLK_PCLKDIV_PCLK0DIV16 (0x4UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/16 HCLK \hideinitializer */ +#define CLK_PCLKDIV_PCLK1DIV1 (0x0UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = HCLK \hideinitializer */ +#define CLK_PCLKDIV_PCLK1DIV2 (0x1UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/2 HCLK \hideinitializer */ +#define CLK_PCLKDIV_PCLK1DIV4 (0x2UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/4 HCLK \hideinitializer */ +#define CLK_PCLKDIV_PCLK1DIV8 (0x3UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/8 HCLK \hideinitializer */ +#define CLK_PCLKDIV_PCLK1DIV16 (0x4UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/16 HCLK \hideinitializer */ +// +#define CLK_PCLKDIV_APB0DIV_DIV1 (0x0UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = HCLK \hideinitializer */ +#define CLK_PCLKDIV_APB0DIV_DIV2 (0x1UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/2 HCLK \hideinitializer */ +#define CLK_PCLKDIV_APB0DIV_DIV4 (0x2UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/4 HCLK \hideinitializer */ +#define CLK_PCLKDIV_APB0DIV_DIV8 (0x3UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/8 HCLK \hideinitializer */ +#define CLK_PCLKDIV_APB0DIV_DIV16 (0x4UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/16 HCLK \hideinitializer */ +#define CLK_PCLKDIV_APB1DIV_DIV1 (0x0UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = HCLK \hideinitializer */ +#define CLK_PCLKDIV_APB1DIV_DIV2 (0x1UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/2 HCLK \hideinitializer */ +#define CLK_PCLKDIV_APB1DIV_DIV4 (0x2UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/4 HCLK \hideinitializer */ +#define CLK_PCLKDIV_APB1DIV_DIV8 (0x3UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/8 HCLK \hideinitializer */ +#define CLK_PCLKDIV_APB1DIV_DIV16 (0x4UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/16 HCLK \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* PLLCTL constant definitions. PLL = FIN * 2 * NF / NR / NO */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_PLLCTL_PLLSRC_HXT 0x00000000UL /*!< For PLL clock source is HXT. 4MHz < FIN/NR < 8MHz \hideinitializer */ +#define CLK_PLLCTL_PLLSRC_HIRC 0x00080000UL /*!< For PLL clock source is HIRC. 4MHz < FIN/NR < 8MHz \hideinitializer */ + +#define CLK_PLLCTL_NF(x) (((x)-2UL)) /*!< x must be constant and 2 <= x <= 513. 200MHz < FIN*2*NF/NR < 500MHz. \hideinitializer */ +#define CLK_PLLCTL_NR(x) (((x)-1UL)<<9) /*!< x must be constant and 1 <= x <= 32. 4MHz < FIN/NR < 8MHz \hideinitializer */ + +#define CLK_PLLCTL_NO_1 0x0000UL /*!< For output divider is 1 \hideinitializer */ +#define CLK_PLLCTL_NO_2 0x4000UL /*!< For output divider is 2 \hideinitializer */ +#define CLK_PLLCTL_NO_4 0xC000UL /*!< For output divider is 4 \hideinitializer */ + +#define CLK_PLLCTL_72MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 36UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 72MHz PLL output with HXT(12MHz X'tal) \hideinitializer */ +#define CLK_PLLCTL_80MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 80MHz PLL output with HXT(12MHz X'tal) \hideinitializer */ +#define CLK_PLLCTL_144MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 24UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 144MHz PLL output with HXT(12MHz X'tal) \hideinitializer */ +#define CLK_PLLCTL_160MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 160MHz PLL output with HXT(12MHz X'tal) \hideinitializer */ +#define CLK_PLLCTL_192MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 32UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 192MHz PLL output with HXT(12MHz X'tal) \hideinitializer */ + +#define CLK_PLLCTL_72MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 36UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 72MHz PLL output with HIRC(12MHz IRC) \hideinitializer */ +#define CLK_PLLCTL_80MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 80MHz PLL output with HIRC(12MHz IRC) \hideinitializer */ +#define CLK_PLLCTL_144MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 24UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 144MHz PLL output with HIRC(12MHz IRC) \hideinitializer */ +#define CLK_PLLCTL_160MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 160MHz PLL output with HIRC(12MHz IRC) \hideinitializer */ +#define CLK_PLLCTL_192MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 32UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 192MHz PLL output with HIRC(12MHz IRC) \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* MODULE constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ + +/* APBCLK(31:30)|CLKSEL(29:28)|CLKSEL_Msk(27:25) |CLKSEL_Pos(24:20)|CLKDIV(19:18)|CLKDIV_Msk(17:10)|CLKDIV_Pos(9:5)|IP_EN_Pos(4:0) */ + +#define MODULE_APBCLK(x) (((x) >>30) & 0x3UL) /*!< Calculate AHBCLK/APBCLK offset on MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 \hideinitializer */ +#define MODULE_CLKSEL(x) (((x) >>28) & 0x3UL) /*!< Calculate CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 \hideinitializer */ +#define MODULE_CLKSEL_Msk(x) (((x) >>25) & 0x7UL) /*!< Calculate CLKSEL mask offset on MODULE index \hideinitializer */ +#define MODULE_CLKSEL_Pos(x) (((x) >>20) & 0x1fUL) /*!< Calculate CLKSEL position offset on MODULE index \hideinitializer */ +#define MODULE_CLKDIV(x) (((x) >>18) & 0x3UL) /*!< Calculate APBCLK CLKDIV on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV1, 0x2:CLKDIV3, 0x3:CLKDIV4 \hideinitializer */ +#define MODULE_CLKDIV_Msk(x) (((x) >>10) & 0xffUL) /*!< Calculate CLKDIV mask offset on MODULE index \hideinitializer */ +#define MODULE_CLKDIV_Pos(x) (((x) >>5 ) & 0x1fUL) /*!< Calculate CLKDIV position offset on MODULE index \hideinitializer */ +#define MODULE_IP_EN_Pos(x) (((x) >>0 ) & 0x1fUL) /*!< Calculate APBCLK offset on MODULE index \hideinitializer */ +#define MODULE_NoMsk 0x0UL /*!< Not mask on MODULE index \hideinitializer */ +#define NA MODULE_NoMsk /*!< Not Available \hideinitializer */ + +#define MODULE_APBCLK_ENC(x) (((x) & 0x03UL) << 30) /*!< MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 \hideinitializer */ +#define MODULE_CLKSEL_ENC(x) (((x) & 0x03UL) << 28) /*!< CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 \hideinitializer */ +#define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x07UL) << 25) /*!< CLKSEL mask offset on MODULE index \hideinitializer */ +#define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1fUL) << 20) /*!< CLKSEL position offset on MODULE index \hideinitializer */ +#define MODULE_CLKDIV_ENC(x) (((x) & 0x03UL) << 18) /*!< APBCLK CLKDIV on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV1, 0x2:CLKDIV3, 0x3:CLKDIV4 \hideinitializer */ +#define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xffUL) << 10) /*!< CLKDIV mask offset on MODULE index \hideinitializer */ +#define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1fUL) << 5) /*!< CLKDIV position offset on MODULE index \hideinitializer */ +#define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1fUL) << 0) /*!< AHBCLK/APBCLK offset on MODULE index \hideinitializer */ + +#define PDMA_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(1UL<<0)) /*!< PDMA Module \hideinitializer */ +#define ISP_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(2UL<<0)) /*!< ISP Module \hideinitializer */ +#define EBI_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(3UL<<0)) /*!< EBI Module \hideinitializer */ +#define USBH_MODULE ((0UL<<30)|(0UL<<28) |(0x1UL<<25) |(8UL<<20) |(0UL<<18) |(0xFUL<<10) |(4UL<<5) |(16UL<<0)) /*!< USBH Module \hideinitializer */ +#define EMAC_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(2UL<<18) |(0xFFUL<<10) |(16UL<<5) |(5UL<<0)) /*!< EMAC Module \hideinitializer */ +#define SDH0_MODULE ((0UL<<30)|(0UL<<28) |(0x3UL<<25) |(20UL<<20) |(0UL<<18) |(0xFFUL<<10) |(24UL<<5) |(6UL<<0)) /*!< SDH0 Module \hideinitializer */ +#define CRC_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(7UL<<0)) /*!< CRC Module \hideinitializer */ +#define CCAP_MODULE ((0UL<<30)|(0UL<<28) |(0x3UL<<25) |(16UL<<20) |(2UL<<18) |(0xFFUL<<10) |(0UL<<5) |(8UL<<0)) /*!< CCAP Module \hideinitializer */ +#define SEN_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(9UL<<0)) /*!< SEN Module \hideinitializer */ +#define HSUSBD_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(10UL<<0)) /*!< HSUSBD Module \hideinitializer */ +#define CRPT_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(12UL<<0)) /*!< CRPT Module \hideinitializer */ +#define SPIM_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(14UL<<0)) /*!< SPIM Module \hideinitializer */ +#define FMCIDLE_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(15UL<<0)) /*!< FMCIDLE Module \hideinitializer */ +#define SDH1_MODULE ((0UL<<30)|(0UL<<28) |(0x3UL<<25) |(22UL<<20) |(2UL<<18) |(0xFFUL<<10) |(24UL<<5) |(17UL<<0)) /*!< SDH1 Module \hideinitializer */ +#define WDT_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(0UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(0UL<<0)) /*!< WDT Module \hideinitializer */ +#define RTC_MODULE ((1UL<<30)|(3UL<<28) |(0x1UL<<25) |(8UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(1UL<<0)) /*!< RTC Module \hideinitializer */ +#define TMR0_MODULE ((1UL<<30)|(1UL<<28) |(0x7UL<<25) |(8UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(2UL<<0)) /*!< TMR0 Module \hideinitializer */ +#define TMR1_MODULE ((1UL<<30)|(1UL<<28) |(0x7UL<<25) |(12UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(3UL<<0)) /*!< TMR1 Module \hideinitializer */ +#define TMR2_MODULE ((1UL<<30)|(1UL<<28) |(0x7UL<<25) |(16UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(4UL<<0)) /*!< TMR2 Module \hideinitializer */ +#define TMR3_MODULE ((1UL<<30)|(1UL<<28) |(0x7UL<<25) |(20UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(5UL<<0)) /*!< TMR3 Module \hideinitializer */ +#define CLKO_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(28UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(6UL<<0)) /*!< CLKO Module \hideinitializer */ +#define WWDT_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(30UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(0UL<<0)) /*!< WWDT Module \hideinitializer */ +#define ACMP01_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(7UL<<0)) /*!< ACMP01 Module \hideinitializer */ +#define I2C0_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(8UL<<0)) /*!< I2C0 Module \hideinitializer */ +#define I2C1_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(9UL<<0)) /*!< I2C1 Module \hideinitializer */ +#define I2C2_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(10UL<<0)) /*!< I2C2 Module \hideinitializer */ +#define QSPI0_MODULE ((1UL<<30)|(2UL<<28) |(0x3UL<<25) |(2UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(12UL<<0)) /*!< QSPI0 Module \hideinitializer */ +#define SPI0_MODULE ((1UL<<30)|(2UL<<28) |(0x3UL<<25) |(4UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(13UL<<0)) /*!< SPI0 Module \hideinitializer */ +#define SPI1_MODULE ((1UL<<30)|(2UL<<28) |(0x3UL<<25) |(6UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(14UL<<0)) /*!< SPI1 Module \hideinitializer */ +#define SPI2_MODULE ((1UL<<30)|(2UL<<28) |(0x3UL<<25) |(10UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(15UL<<0)) /*!< SPI2 Module \hideinitializer */ +#define UART0_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(24UL<<20) |(0UL<<18) |(0xFUL<<10) |(8UL<<5) |(16UL<<0)) /*!< UART0 Module \hideinitializer */ +#define UART1_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(26UL<<20) |(0UL<<18) |(0xFUL<<10) |(12UL<<5) |(17UL<<0)) /*!< UART1 Module \hideinitializer */ +#define UART2_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(24UL<<20) |(3UL<<18) |(0xFUL<<10) |(0UL<<5) |(18UL<<0)) /*!< UART2 Module \hideinitializer */ +#define UART3_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(26UL<<20) |(3UL<<18) |(0xFUL<<10) |(4UL<<5) |(19UL<<0)) /*!< UART3 Module \hideinitializer */ +#define UART4_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(28UL<<20) |(3UL<<18) |(0xFUL<<10) |(8UL<<5) |(20UL<<0)) /*!< UART4 Module \hideinitializer */ +#define UART5_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(30UL<<20) |(3UL<<18) |(0xFUL<<10) |(12UL<<5) |(21UL<<0)) /*!< UART5 Module \hideinitializer */ +#define UART6_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(20UL<<20) |(3UL<<18) |(0xFUL<<10) |(16UL<<5) |(22UL<<0)) /*!< UART6 Module \hideinitializer */ +#define UART7_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(22UL<<20) |(3UL<<18) |(0xFUL<<10) |(20UL<<5) |(23UL<<0)) /*!< UART7 Module \hideinitializer */ +#define CAN0_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(24UL<<0)) /*!< CAN0 Module \hideinitializer */ +#define CAN1_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(25UL<<0)) /*!< CAN1 Module \hideinitializer */ +#define OTG_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(26UL<<0)) /*!< OTG Module \hideinitializer */ +#define USBD_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(1UL<<25) |(8UL<<20) |(MODULE_NoMsk<<18)|(0xFUL<<10) |(4UL<<5) |(27UL<<0)) /*!< USBD Module \hideinitializer */ +#define EADC_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(0UL<<18) |(0xFFUL<<10) |(16UL<<5) |(28UL<<0)) /*!< EADC Module \hideinitializer */ +#define I2S0_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(16UL<<20) |(2UL<<18) |(0xFUL<<10) |(0UL<<5) |(29UL<<0)) /*!< I2S0 Module \hideinitializer */ +#define HSOTG_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(30UL<<0)) /*!< HSOTG Module \hideinitializer */ +#define SC0_MODULE ((2UL<<30)|(3UL<<28) |(0x3UL<<25) |(0UL<<20) |(1UL<<18) |(0xFFUL<<10) |(0UL<<5) |(0UL<<0)) /*!< SC0 Module \hideinitializer */ +#define SC1_MODULE ((2UL<<30)|(3UL<<28) |(0x3UL<<25) |(2UL<<20) |(1UL<<18) |(0xFFUL<<10) |(8UL<<5) |(1UL<<0)) /*!< SC1 Module \hideinitializer */ +#define SC2_MODULE ((2UL<<30)|(3UL<<28) |(0x3UL<<25) |(4UL<<20) |(1UL<<18) |(0xFFUL<<10) |(16UL<<5) |(2UL<<0)) /*!< SC2 Module \hideinitializer */ +#define QSPI1_MODULE ((2UL<<30)|(3UL<<28) |(0x3UL<<25) |(12UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(4UL<<0)) /*!< QSPI1 Module \hideinitializer */ +#define SPI3_MODULE ((2UL<<30)|(2UL<<28) |(0x3UL<<25) |(12UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(6UL<<0)) /*!< SPI3 Module \hideinitializer */ +#define USCI0_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(8UL<<0)) /*!< USCI0 Module \hideinitializer */ +#define USCI1_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(9UL<<0)) /*!< USCI1 Module \hideinitializer */ +#define DAC_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(12UL<<0)) /*!< DAC Module \hideinitializer */ +#define CAN2_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(28UL<<0)) /*!< CAN2 Module \hideinitializer */ +#define EPWM0_MODULE ((2UL<<30)|(2UL<<28) |(0x1UL<<25) |(0UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(16UL<<0)) /*!< EPWM0 Module \hideinitializer */ +#define EPWM1_MODULE ((2UL<<30)|(2UL<<28) |(0x1UL<<25) |(1UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(17UL<<0)) /*!< EPWM1 Module \hideinitializer */ +#define BPWM0_MODULE ((2UL<<30)|(2UL<<28) |(0x1UL<<25) |(8UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(18UL<<0)) /*!< BPWM0 Module \hideinitializer */ +#define BPWM1_MODULE ((2UL<<30)|(2UL<<28) |(0x1UL<<25) |(9UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(19UL<<0)) /*!< BPWM1 Module \hideinitializer */ +#define QEI0_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(22UL<<0)) /*!< QEI0 Module \hideinitializer */ +#define QEI1_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(23UL<<0)) /*!< QEI1 Module \hideinitializer */ +#define TRNG_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(25UL<<0)) /*!< TRNG Module \hideinitializer */ +#define ECAP0_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(26UL<<0)) /*!< ECAP0 Module \hideinitializer */ +#define ECAP1_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(27UL<<0)) /*!< ECAP1 Module \hideinitializer */ +#define OPA_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(30UL<<0)) /*!< OPA Module \hideinitializer */ +#define EADC1_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(2UL<<18) |(0xFFUL<<10) |(24UL<<5) |(31UL<<0)) /*!< EADC1 Module \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* PDMSEL constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_PMUCTL_PDMSEL_PD (0x0UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Power-down mode \hideinitializer */ +#define CLK_PMUCTL_PDMSEL_LLPD (0x1UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Low leakage Power-down mode \hideinitializer */ +#define CLK_PMUCTL_PDMSEL_FWPD (0x2UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Fast wake-up Power-down mode \hideinitializer */ +#define CLK_PMUCTL_PDMSEL_SPD0 (0x4UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Standby Power-down mode 0 \hideinitializer */ +#define CLK_PMUCTL_PDMSEL_SPD1 (0x5UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Standby Power-down mode 1 \hideinitializer */ +#define CLK_PMUCTL_PDMSEL_DPD (0x6UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Deep Power-down mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* WKTMRIS constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_PMUCTL_WKTMRIS_128 (0x0UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 128 OSC10K clocks (12.8 ms) \hideinitializer */ +#define CLK_PMUCTL_WKTMRIS_256 (0x1UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 256 OSC10K clocks (25.6 ms) \hideinitializer */ +#define CLK_PMUCTL_WKTMRIS_512 (0x2UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 512 OSC10K clocks (51.2 ms) \hideinitializer */ +#define CLK_PMUCTL_WKTMRIS_1024 (0x3UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 1024 OSC10K clocks (102.4ms) \hideinitializer */ +#define CLK_PMUCTL_WKTMRIS_4096 (0x4UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 4096 OSC10K clocks (409.6ms) \hideinitializer */ +#define CLK_PMUCTL_WKTMRIS_8192 (0x5UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 8192 OSC10K clocks (819.2ms) \hideinitializer */ +#define CLK_PMUCTL_WKTMRIS_16384 (0x6UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 16384 OSC10K clocks (1638.4ms) \hideinitializer */ +#define CLK_PMUCTL_WKTMRIS_65536 (0x7UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 65536 OSC10K clocks (6553.6ms) \hideinitializer */ +#define CLK_PMUCTL_WKTMRIS_131072 (0x8UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 131072 OSC10K clocks (13107.2 ms) \hideinitializer */ +#define CLK_PMUCTL_WKTMRIS_262144 (0x9UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 262144 OSC10K clocks (26214.4 ms) \hideinitializer */ +#define CLK_PMUCTL_WKTMRIS_524288 (0xaUL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 524288 OSC10K clocks (52428.8ms) \hideinitializer */ +#define CLK_PMUCTL_WKTMRIS_1048576 (0xbUL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 1048576 OSC10K clocks (104857.6ms) \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* SWKDBCLKSEL constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_SWKDBCTL_SWKDBCLKSEL_1 (0x0UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 1 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_2 (0x1UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 2 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_4 (0x2UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 4 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_8 (0x3UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 8 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_16 (0x4UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 16 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_32 (0x5UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 32 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_64 (0x6UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 64 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_128 (0x7UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 128 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_256 (0x8UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 256 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_2x256 (0x9UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 2x256 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_4x256 (0xaUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 4x256 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_8x256 (0xbUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 8x256 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_16x256 (0xcUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 16x256 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_32x256 (0xdUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 32x256 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_64x256 (0xeUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 64x256 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_128x256 (0xfUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 128x256 clocks \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* DPD Pin Rising/Falling Edge Wake-up Enable constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_DPDWKPIN_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Disable Wake-up pin at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN_RISING (0x1UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin rising edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN_FALLING (0x2UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin falling edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin both edge at Deep Power-down mode \hideinitializer */ + +#define CLK_DPDWKPIN0_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Disable Wake-up pin0 (GPC.0) at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN0_RISING (0x1UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin0 (GPC.0) rising edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN0_FALLING (0x2UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin0 (GPC.0) falling edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN0_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin0 (GPC.0) both edge at Deep Power-down mode \hideinitializer */ + +#define CLK_DPDWKPIN1_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN1_Pos) /*!< Disable Wake-up pin1 (GPB.0) at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN1_RISING (0x1UL << CLK_PMUCTL_WKPINEN1_Pos) /*!< Enable Wake-up pin1 (GPB.0) rising edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN1_FALLING (0x2UL << CLK_PMUCTL_WKPINEN1_Pos) /*!< Enable Wake-up pin1 (GPB.0) falling edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN1_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN1_Pos) /*!< Enable Wake-up pin1 (GPB.0) both edge at Deep Power-down mode \hideinitializer */ + +#define CLK_DPDWKPIN2_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN2_Pos) /*!< Disable Wake-up pin2 (GPB.2) at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN2_RISING (0x1UL << CLK_PMUCTL_WKPINEN2_Pos) /*!< Enable Wake-up pin2 (GPB.2) rising edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN2_FALLING (0x2UL << CLK_PMUCTL_WKPINEN2_Pos) /*!< Enable Wake-up pin2 (GPB.2) falling edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN2_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN2_Pos) /*!< Enable Wake-up pin2 (GPB.2) both edge at Deep Power-down mode \hideinitializer */ + +#define CLK_DPDWKPIN3_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN3_Pos) /*!< Disable Wake-up pin3 (GPB.12) at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN3_RISING (0x1UL << CLK_PMUCTL_WKPINEN3_Pos) /*!< Enable Wake-up pin3 (GPB.12) rising edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN3_FALLING (0x2UL << CLK_PMUCTL_WKPINEN3_Pos) /*!< Enable Wake-up pin3 (GPB.12) falling edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN3_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN3_Pos) /*!< Enable Wake-up pin3 (GPB.12) both edge at Deep Power-down mode \hideinitializer */ + +#define CLK_DPDWKPIN4_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN4_Pos) /*!< Disable Wake-up pin4 (GPF.6) at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN4_RISING (0x1UL << CLK_PMUCTL_WKPINEN4_Pos) /*!< Enable Wake-up pin4 (GPF.6) rising edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN4_FALLING (0x2UL << CLK_PMUCTL_WKPINEN4_Pos) /*!< Enable Wake-up pin4 (GPF.6) falling edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN4_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN4_Pos) /*!< Enable Wake-up pin4 (GPF.6) both edge at Deep Power-down mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* SPD Pin Rising/Falling Edge Wake-up Enable constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_SPDWKPIN_ENABLE (0x1UL << 0) /*!< Enable Standby Power-down Pin Wake-up \hideinitializer */ +#define CLK_SPDWKPIN_RISING (0x1UL << 1) /*!< Standby Power-down Wake-up on Standby Power-down Pin rising edge \hideinitializer */ +#define CLK_SPDWKPIN_FALLING (0x1UL << 2) /*!< Standby Power-down Wake-up on Standby Power-down Pin falling edge \hideinitializer */ +#define CLK_SPDWKPIN_DEBOUNCEEN (0x1UL << 8) /*!< Enable Standby power-down pin De-bounce function \hideinitializer */ +#define CLK_SPDWKPIN_DEBOUNCEDIS (0x0UL << 8) /*!< Disable Standby power-down pin De-bounce function \hideinitializer */ + +#define CLK_SPDSRETSEL_NO (0x0UL << CLK_PMUCTL_SRETSEL_Pos) /*!< No SRAM retention when chip enter SPD mode \hideinitializer */ +#define CLK_SPDSRETSEL_16K (0x1UL << CLK_PMUCTL_SRETSEL_Pos) /*!< 16K SRAM retention when chip enter SPD mode \hideinitializer */ +#define CLK_SPDSRETSEL_32K (0x2UL << CLK_PMUCTL_SRETSEL_Pos) /*!< 32K SRAM retention when chip enter SPD mode \hideinitializer */ +#define CLK_SPDSRETSEL_64K (0x3UL << CLK_PMUCTL_SRETSEL_Pos) /*!< 64K SRAM retention when chip enter SPD mode \hideinitializer */ +#define CLK_SPDSRETSEL_128K (0x4UL << CLK_PMUCTL_SRETSEL_Pos) /*!< 128K SRAM retention when chip enter SPD mode \hideinitializer */ + +#define CLK_DISABLE_WKTMR(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKTMREN_Msk) /*!< Disable Wake-up timer at Standby or Deep Power-down mode \hideinitializer */ +#define CLK_ENABLE_WKTMR(void) (CLK->PMUCTL |= CLK_PMUCTL_WKTMREN_Msk) /*!< Enable Wake-up timer at Standby or Deep Power-down mode \hideinitializer */ +#define CLK_DISABLE_DPDWKPIN(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN_Msk) /*!< Disable Wake-up pin at Deep Power-down mode \hideinitializer */ +#define CLK_DISABLE_DPDWKPIN0(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN_Msk) /*!< Disable Wake-up pin0 (GPC.0) at Deep Power-down mode \hideinitializer */ +#define CLK_DISABLE_DPDWKPIN1(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN1_Msk) /*!< Disable Wake-up pin1 (GPB.0) at Deep Power-down mode \hideinitializer */ +#define CLK_DISABLE_DPDWKPIN2(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN2_Msk) /*!< Disable Wake-up pin2 (GPB.2) at Deep Power-down mode \hideinitializer */ +#define CLK_DISABLE_DPDWKPIN3(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN3_Msk) /*!< Disable Wake-up pin3 (GPB.12) at Deep Power-down mode \hideinitializer */ +#define CLK_DISABLE_DPDWKPIN4(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN4_Msk) /*!< Disable Wake-up pin4 (GPF.6) at Deep Power-down mode \hideinitializer */ +#define CLK_DISABLE_SPDACMP(void) (CLK->PMUCTL &= ~CLK_PMUCTL_ACMPSPWK_Msk) /*!< Disable ACMP wake-up at Standby Power-down mode \hideinitializer */ +#define CLK_ENABLE_SPDACMP(void) (CLK->PMUCTL |= CLK_PMUCTL_ACMPSPWK_Msk) /*!< Enable ACMP wake-up at Standby Power-down mode \hideinitializer */ +#define CLK_DISABLE_RTCWK(void) (CLK->PMUCTL &= ~CLK_PMUCTL_RTCWKEN_Msk) /*!< Disable RTC Wake-up at Standby or Deep Power-down mode \hideinitializer */ +#define CLK_ENABLE_RTCWK(void) (CLK->PMUCTL |= CLK_PMUCTL_RTCWKEN_Msk) /*!< Enable RTC Wake-up at Standby or Deep Power-down mode \hideinitializer */ + +/*@}*/ /* end of group CLK_EXPORTED_CONSTANTS */ + +/** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions + @{ +*/ + +/** + * @brief Set Wake-up Timer Time-out Interval + * + * @param[in] u32Interval The Wake-up Timer Time-out Interval selection. It could be + * - \ref CLK_PMUCTL_WKTMRIS_128 + * - \ref CLK_PMUCTL_WKTMRIS_256 + * - \ref CLK_PMUCTL_WKTMRIS_512 + * - \ref CLK_PMUCTL_WKTMRIS_1024 + * - \ref CLK_PMUCTL_WKTMRIS_4096 + * - \ref CLK_PMUCTL_WKTMRIS_8192 + * - \ref CLK_PMUCTL_WKTMRIS_16384 + * - \ref CLK_PMUCTL_WKTMRIS_65536 + * - \ref CLK_PMUCTL_WKTMRIS_131072 + * - \ref CLK_PMUCTL_WKTMRIS_262144 + * - \ref CLK_PMUCTL_WKTMRIS_524288 + * - \ref CLK_PMUCTL_WKTMRIS_1048576 + * + * @return None + * + * @details This function set Wake-up Timer Time-out Interval. + * + * \hideinitializer + */ +#define CLK_SET_WKTMR_INTERVAL(u32Interval) (CLK->PMUCTL |= (u32Interval)) + +/** + * @brief Set De-bounce Sampling Cycle Time + * + * @param[in] u32CycleSel The de-bounce sampling cycle selection. It could be + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_1 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_2 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_4 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_8 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_16 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_32 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_64 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_128 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_2x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_4x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_8x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_16x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_32x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_64x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_128x256 + * + * @return None + * + * @details This function set Set De-bounce Sampling Cycle Time. + * + * \hideinitializer + */ +#define CLK_SET_SPDDEBOUNCETIME(u32CycleSel) (CLK->SWKDBCTL = (u32CycleSel)) + +/*---------------------------------------------------------------------------------------------------------*/ +/* static inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void CLK_SysTickDelay(uint32_t us); +__STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us); + +/** + * @brief This function execute delay function. + * @param[in] us Delay time. The Max value is 2^24 / CPU Clock(MHz). Ex: + * 72MHz => 233016us, 50MHz => 335544us, + * 48MHz => 349525us, 28MHz => 699050us ... + * @return None + * @details Use the SysTick to generate the delay time and the unit is in us. + * The SysTick clock source is from HCLK, i.e the same as system core clock. + */ +__STATIC_INLINE void CLK_SysTickDelay(uint32_t us) +{ + SysTick->LOAD = us * CyclesPerUs; + SysTick->VAL = 0x0UL; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; + + /* Waiting for down-count to zero */ + while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL) + { + } + + /* Disable SysTick counter */ + SysTick->CTRL = 0UL; +} + +/** + * @brief This function execute long delay function. + * @param[in] us Delay time. + * @return None + * @details Use the SysTick to generate the long delay time and the UNIT is in us. + * The SysTick clock source is from HCLK, i.e the same as system core clock. + * User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function. + */ +__STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us) +{ + uint32_t delay; + + /* It should <= 349525us for each delay loop */ + delay = 349525UL; + + do + { + if(us > delay) + { + us -= delay; + } + else + { + delay = us; + us = 0UL; + } + + SysTick->LOAD = delay * CyclesPerUs; + SysTick->VAL = (0x0UL); + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; + + /* Waiting for down-count to zero */ + while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL); + + /* Disable SysTick counter */ + SysTick->CTRL = 0UL; + + } + while(us > 0UL); + +} + + +void CLK_DisableCKO(void); +void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En); +void CLK_PowerDown(void); +void CLK_Idle(void); +uint32_t CLK_GetHXTFreq(void); +uint32_t CLK_GetLXTFreq(void); +uint32_t CLK_GetHCLKFreq(void); +uint32_t CLK_GetPCLK0Freq(void); +uint32_t CLK_GetPCLK1Freq(void); +uint32_t CLK_GetCPUFreq(void); +uint32_t CLK_SetCoreClock(uint32_t u32Hclk); +void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv); +void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv); +void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc); +void CLK_EnableXtalRC(uint32_t u32ClkMask); +void CLK_DisableXtalRC(uint32_t u32ClkMask); +void CLK_EnableModuleClock(uint32_t u32ModuleIdx); +void CLK_DisableModuleClock(uint32_t u32ModuleIdx); +uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq); +void CLK_DisablePLL(void); +uint32_t CLK_WaitClockReady(uint32_t u32ClkMask); +void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count); +void CLK_DisableSysTick(void); +void CLK_SetPowerDownMode(uint32_t u32PDMode); +void CLK_EnableDPDWKPin(uint32_t u32TriggerType); +uint32_t CLK_GetPMUWKSrc(void); +void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn); +uint32_t CLK_GetPLLClockFreq(void); +uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx); +uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx); + +/*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CLK_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_CLK_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_crc.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_crc.h new file mode 100644 index 0000000000000000000000000000000000000000..2dc6afca049eea0e02d19984bf08995594e66399 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_crc.h @@ -0,0 +1,113 @@ +/**************************************************************************//** + * @file nu_crc.h + * @version V1.00 + * @brief M480 series CRC driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_CRC_H__ +#define __NU_CRC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CRC_Driver CRC Driver + @{ +*/ + +/** @addtogroup CRC_EXPORTED_CONSTANTS CRC Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* CRC Polynomial Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CRC_CCITT (0UL << CRC_CTL_CRCMODE_Pos) /*!SEED = (u32Seed); CRC->CTL |= CRC_CTL_CHKSINIT_Msk; }while(0) + +/** + * @brief Get CRC Seed Value + * + * @param None + * + * @return CRC seed value + * + * @details This macro gets the current CRC seed value. + * \hideinitializer + */ +#define CRC_GET_SEED() (CRC->SEED) + +/** + * @brief CRC Write Data + * + * @param[in] u32Data Write data + * + * @return None + * + * @details User can write data directly to CRC Write Data Register(CRC_DAT) by this macro to perform CRC operation. + * \hideinitializer + */ +#define CRC_WRITE_DATA(u32Data) (CRC->DAT = (u32Data)) + +void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen); +uint32_t CRC_GetChecksum(void); + +/*@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CRC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_crypto.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_crypto.h new file mode 100644 index 0000000000000000000000000000000000000000..6b0ccb27d0a533a2ec6f9ac1b44e6dc3190e32a9 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_crypto.h @@ -0,0 +1,378 @@ +/**************************************************************************//** + * @file nu_crypto.h + * @version V1.10 + * @brief Cryptographic Accelerator driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __NU_CRYPTO_H__ +#define __NU_CRYPTO_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CRYPTO_Driver CRYPTO Driver + @{ +*/ + + +/** @addtogroup CRYPTO_EXPORTED_CONSTANTS CRYPTO Exported Constants + @{ +*/ + +#define PRNG_KEY_SIZE_64 0UL /*!< Select to generate 64-bit random key \hideinitializer */ +#define PRNG_KEY_SIZE_128 1UL /*!< Select to generate 128-bit random key \hideinitializer */ +#define PRNG_KEY_SIZE_192 2UL /*!< Select to generate 192-bit random key \hideinitializer */ +#define PRNG_KEY_SIZE_256 3UL /*!< Select to generate 256-bit random key \hideinitializer */ + +#define PRNG_SEED_CONT 0UL /*!< PRNG using current seed \hideinitializer */ +#define PRNG_SEED_RELOAD 1UL /*!< PRNG reload new seed \hideinitializer */ + +#define AES_KEY_SIZE_128 0UL /*!< AES select 128-bit key length \hideinitializer */ +#define AES_KEY_SIZE_192 1UL /*!< AES select 192-bit key length \hideinitializer */ +#define AES_KEY_SIZE_256 2UL /*!< AES select 256-bit key length \hideinitializer */ + +#define AES_MODE_ECB 0UL /*!< AES select ECB mode \hideinitializer */ +#define AES_MODE_CBC 1UL /*!< AES select CBC mode \hideinitializer */ +#define AES_MODE_CFB 2UL /*!< AES select CFB mode \hideinitializer */ +#define AES_MODE_OFB 3UL /*!< AES select OFB mode \hideinitializer */ +#define AES_MODE_CTR 4UL /*!< AES select CTR mode \hideinitializer */ +#define AES_MODE_CBC_CS1 0x10UL /*!< AES select CBC CS1 mode \hideinitializer */ +#define AES_MODE_CBC_CS2 0x11UL /*!< AES select CBC CS2 mode \hideinitializer */ +#define AES_MODE_CBC_CS3 0x12UL /*!< AES select CBC CS3 mode \hideinitializer */ + +#define AES_NO_SWAP 0UL /*!< AES do not swap input and output data \hideinitializer */ +#define AES_OUT_SWAP 1UL /*!< AES swap output data \hideinitializer */ +#define AES_IN_SWAP 2UL /*!< AES swap input data \hideinitializer */ +#define AES_IN_OUT_SWAP 3UL /*!< AES swap both input and output data \hideinitializer */ + +#define DES_MODE_ECB 0x000UL /*!< DES select ECB mode \hideinitializer */ +#define DES_MODE_CBC 0x100UL /*!< DES select CBC mode \hideinitializer */ +#define DES_MODE_CFB 0x200UL /*!< DES select CFB mode \hideinitializer */ +#define DES_MODE_OFB 0x300UL /*!< DES select OFB mode \hideinitializer */ +#define DES_MODE_CTR 0x400UL /*!< DES select CTR mode \hideinitializer */ +#define TDES_MODE_ECB 0x004UL /*!< TDES select ECB mode \hideinitializer */ +#define TDES_MODE_CBC 0x104UL /*!< TDES select CBC mode \hideinitializer */ +#define TDES_MODE_CFB 0x204UL /*!< TDES select CFB mode \hideinitializer */ +#define TDES_MODE_OFB 0x304UL /*!< TDES select OFB mode \hideinitializer */ +#define TDES_MODE_CTR 0x404UL /*!< TDES select CTR mode \hideinitializer */ + +#define TDES_NO_SWAP 0UL /*!< TDES do not swap data \hideinitializer */ +#define TDES_WHL_SWAP 1UL /*!< TDES swap high-low word \hideinitializer */ +#define TDES_OUT_SWAP 2UL /*!< TDES swap output data \hideinitializer */ +#define TDES_OUT_WHL_SWAP 3UL /*!< TDES swap output data and high-low word \hideinitializer */ +#define TDES_IN_SWAP 4UL /*!< TDES swap input data \hideinitializer */ +#define TDES_IN_WHL_SWAP 5UL /*!< TDES swap input data and high-low word \hideinitializer */ +#define TDES_IN_OUT_SWAP 6UL /*!< TDES swap both input and output data \hideinitializer */ +#define TDES_IN_OUT_WHL_SWAP 7UL /*!< TDES swap input, output and high-low word \hideinitializer */ + +#define SHA_MODE_SHA1 0UL /*!< SHA select SHA-1 160-bit \hideinitializer */ +#define SHA_MODE_SHA224 5UL /*!< SHA select SHA-224 224-bit \hideinitializer */ +#define SHA_MODE_SHA256 4UL /*!< SHA select SHA-256 256-bit \hideinitializer */ +#define SHA_MODE_SHA384 7UL /*!< SHA select SHA-384 384-bit \hideinitializer */ +#define SHA_MODE_SHA512 6UL /*!< SHA select SHA-512 512-bit \hideinitializer */ + +#define SHA_NO_SWAP 0UL /*!< SHA do not swap input and output data \hideinitializer */ +#define SHA_OUT_SWAP 1UL /*!< SHA swap output data \hideinitializer */ +#define SHA_IN_SWAP 2UL /*!< SHA swap input data \hideinitializer */ +#define SHA_IN_OUT_SWAP 3UL /*!< SHA swap both input and output data \hideinitializer */ + +#define CRYPTO_DMA_FIRST 0x4UL /*!< Do first encrypt/decrypt in DMA cascade \hideinitializer */ +#define CRYPTO_DMA_ONE_SHOT 0x5UL /*!< Do one shot encrypt/decrypt with DMA \hideinitializer */ +#define CRYPTO_DMA_CONTINUE 0x6UL /*!< Do continuous encrypt/decrypt in DMA cascade \hideinitializer */ +#define CRYPTO_DMA_LAST 0x7UL /*!< Do last encrypt/decrypt in DMA cascade \hideinitializer */ + +typedef enum +{ + /*!< ECC curve \hideinitializer */ + CURVE_P_192, /*!< ECC curve P-192 \hideinitializer */ + CURVE_P_224, /*!< ECC curve P-224 \hideinitializer */ + CURVE_P_256, /*!< ECC curve P-256 \hideinitializer */ + CURVE_P_384, /*!< ECC curve P-384 \hideinitializer */ + CURVE_P_521, /*!< ECC curve P-521 \hideinitializer */ + CURVE_K_163, /*!< ECC curve K-163 \hideinitializer */ + CURVE_K_233, /*!< ECC curve K-233 \hideinitializer */ + CURVE_K_283, /*!< ECC curve K-283 \hideinitializer */ + CURVE_K_409, /*!< ECC curve K-409 \hideinitializer */ + CURVE_K_571, /*!< ECC curve K-571 \hideinitializer */ + CURVE_B_163, /*!< ECC curve B-163 \hideinitializer */ + CURVE_B_233, /*!< ECC curve B-233 \hideinitializer */ + CURVE_B_283, /*!< ECC curve B-283 \hideinitializer */ + CURVE_B_409, /*!< ECC curve B-409 \hideinitializer */ + CURVE_B_571, /*!< ECC curve K-571 \hideinitializer */ + CURVE_KO_192, /*!< ECC 192-bits "Koblitz" curve \hideinitializer */ + CURVE_KO_224, /*!< ECC 224-bits "Koblitz" curve \hideinitializer */ + CURVE_KO_256, /*!< ECC 256-bits "Koblitz" curve \hideinitializer */ + CURVE_BP_256, /*!< ECC Brainpool 256-bits curve \hideinitializer */ + CURVE_BP_384, /*!< ECC Brainpool 256-bits curve \hideinitializer */ + CURVE_BP_512, /*!< ECC Brainpool 256-bits curve \hideinitializer */ + CURVE_UNDEF, /*!< Invalid curve \hideinitializer */ +} +E_ECC_CURVE; /*!< ECC curve \hideinitializer */ + + +/*@}*/ /* end of group CRYPTO_EXPORTED_CONSTANTS */ + + +/** @addtogroup M480_CRYPTO_EXPORTED_MACROS CRYPTO Exported Macros + @{ +*/ + +/*----------------------------------------------------------------------------------------------*/ +/* Macros */ +/*----------------------------------------------------------------------------------------------*/ + +/** + * @brief This macro enables PRNG interrupt. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define PRNG_ENABLE_INT(crpt) ((crpt)->INTEN |= CRPT_INTEN_PRNGIEN_Msk) + +/** + * @brief This macro disables PRNG interrupt. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define PRNG_DISABLE_INT(crpt) ((crpt)->INTEN &= ~CRPT_INTEN_PRNGIEN_Msk) + +/** + * @brief This macro gets PRNG interrupt flag. + * @param crpt Specified cripto module + * @return PRNG interrupt flag. + * \hideinitializer + */ +#define PRNG_GET_INT_FLAG(crpt) ((crpt)->INTSTS & CRPT_INTSTS_PRNGIF_Msk) + +/** + * @brief This macro clears PRNG interrupt flag. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define PRNG_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = CRPT_INTSTS_PRNGIF_Msk) + +/** + * @brief This macro enables AES interrupt. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define AES_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_AESIEN_Msk|CRPT_INTEN_AESEIEN_Msk)) + +/** + * @brief This macro disables AES interrupt. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define AES_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_AESIEN_Msk|CRPT_INTEN_AESEIEN_Msk)) + +/** + * @brief This macro gets AES interrupt flag. + * @param crpt Specified cripto module + * @return AES interrupt flag. + * \hideinitializer + */ +#define AES_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_AESIF_Msk|CRPT_INTSTS_AESEIF_Msk)) + +/** + * @brief This macro clears AES interrupt flag. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define AES_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_AESIF_Msk|CRPT_INTSTS_AESEIF_Msk)) + +/** + * @brief This macro enables AES key protection. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define AES_ENABLE_KEY_PROTECT(crpt) ((crpt)->AES_CTL |= CRPT_AES_CTL_KEYPRT_Msk) + +/** + * @brief This macro disables AES key protection. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define AES_DISABLE_KEY_PROTECT(crpt) ((crpt)->AES_CTL = ((crpt)->AES_CTL & ~CRPT_AES_CTL_KEYPRT_Msk) | (0x16UL<AES_CTL &= ~CRPT_AES_CTL_KEYPRT_Msk) + +/** + * @brief This macro enables TDES interrupt. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define TDES_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_TDESIEN_Msk|CRPT_INTEN_TDESEIEN_Msk)) + +/** + * @brief This macro disables TDES interrupt. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define TDES_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_TDESIEN_Msk|CRPT_INTEN_TDESEIEN_Msk)) + +/** + * @brief This macro gets TDES interrupt flag. + * @param crpt Specified cripto module + * @return TDES interrupt flag. + * \hideinitializer + */ +#define TDES_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_TDESIF_Msk|CRPT_INTSTS_TDESEIF_Msk)) + +/** + * @brief This macro clears TDES interrupt flag. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define TDES_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_TDESIF_Msk|CRPT_INTSTS_TDESEIF_Msk)) + +/** + * @brief This macro enables TDES key protection. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define TDES_ENABLE_KEY_PROTECT(crpt) ((crpt)->TDES_CTL |= CRPT_TDES_CTL_KEYPRT_Msk) + +/** + * @brief This macro disables TDES key protection. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define TDES_DISABLE_KEY_PROTECT(crpt) ((crpt)->TDES_CTL = ((crpt)->TDES_CTL & ~CRPT_TDES_CTL_KEYPRT_Msk) | (0x16UL<TDES_CTL &= ~CRPT_TDES_CTL_KEYPRT_Msk) + +/** + * @brief This macro enables SHA interrupt. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define SHA_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_HMACIEN_Msk|CRPT_INTEN_HMACEIEN_Msk)) + +/** + * @brief This macro disables SHA interrupt. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define SHA_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_HMACIEN_Msk|CRPT_INTEN_HMACEIEN_Msk)) + +/** + * @brief This macro gets SHA interrupt flag. + * @param crpt Specified cripto module + * @return SHA interrupt flag. + * \hideinitializer + */ +#define SHA_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_HMACIF_Msk|CRPT_INTSTS_HMACEIF_Msk)) + +/** + * @brief This macro clears SHA interrupt flag. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define SHA_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_HMACIF_Msk|CRPT_INTSTS_HMACEIF_Msk)) + +/** + * @brief This macro enables ECC interrupt. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define ECC_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_ECCIEN_Msk|CRPT_INTEN_ECCEIEN_Msk)) + +/** + * @brief This macro disables ECC interrupt. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define ECC_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_ECCIEN_Msk|CRPT_INTEN_ECCEIEN_Msk)) + +/** + * @brief This macro gets ECC interrupt flag. + * @param crpt Specified cripto module + * @return ECC interrupt flag. + * \hideinitializer + */ +#define ECC_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_ECCIF_Msk|CRPT_INTSTS_ECCEIF_Msk)) + +/** + * @brief This macro clears ECC interrupt flag. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define ECC_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_ECCIF_Msk|CRPT_INTSTS_ECCEIF_Msk)) + + +/*@}*/ /* end of group M480_CRYPTO_EXPORTED_MACROS */ + + +/** @addtogroup CRYPTO_EXPORTED_FUNCTIONS CRYPTO Exported Functions + @{ +*/ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Functions */ +/*---------------------------------------------------------------------------------------------------------*/ + +void PRNG_Open(CRPT_T *crpt, uint32_t u32KeySize, uint32_t u32SeedReload, uint32_t u32Seed); +void PRNG_Start(CRPT_T *crpt); +void PRNG_Read(CRPT_T *crpt, uint32_t u32RandKey[]); +void AES_Open(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32EncDec, uint32_t u32OpMode, uint32_t u32KeySize, uint32_t u32SwapType); +void AES_Start(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32DMAMode); +void AES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize); +void AES_SetInitVect(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32IV[]); +void AES_SetDMATransfer(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt); +void TDES_Open(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32EncDec, int32_t Is3DES, int32_t Is3Key, uint32_t u32OpMode, uint32_t u32SwapType); +void TDES_Start(CRPT_T *crpt, int32_t u32Channel, uint32_t u32DMAMode); +void TDES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[3][2]); +void TDES_SetInitVect(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32IVH, uint32_t u32IVL); +void TDES_SetDMATransfer(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt); +void SHA_Open(CRPT_T *crpt, uint32_t u32OpMode, uint32_t u32SwapType, uint32_t hmac_key_len); +void SHA_Start(CRPT_T *crpt, uint32_t u32DMAMode); +void SHA_SetDMATransfer(CRPT_T *crpt, uint32_t u32SrcAddr, uint32_t u32TransCnt); +void SHA_Read(CRPT_T *crpt, uint32_t u32Digest[]); +void ECC_Complete(CRPT_T *crpt); +int ECC_IsPrivateKeyValid(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char private_k[]); +int32_t ECC_GeneratePublicKey(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[]); +int32_t ECC_Mutiply(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char x1[], char y1[], char *k, char x2[], char y2[]); +int32_t ECC_GenerateSecretZ(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[], char secret_z[]); +int32_t ECC_GenerateSignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, char *d, char *k, char *R, char *S); +int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, char *public_k1, char *public_k2, char *R, char *S); + + +/*@}*/ /* end of group CRYPTO_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CRYPTO_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_CRYPTO_H__ */ + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ + diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_dac.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_dac.h new file mode 100644 index 0000000000000000000000000000000000000000..71c22f4e4a03e78c75b168676f98d5127e441363 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_dac.h @@ -0,0 +1,269 @@ +/**************************************************************************//** + * @file nu_dac.h + * @version V1.00 + * @brief M480 series DAC driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __NU_DAC_H__ +#define __NU_DAC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup DAC_Driver DAC Driver + @{ +*/ + + +/** @addtogroup DAC_EXPORTED_CONSTANTS DAC Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* DAC_CTL Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define DAC_CTL_LALIGN_RIGHT_ALIGN (0UL<SWTRG = DAC_SWTRG_SWTRG_Msk) + +/** + * @brief Enable DAC data left-aligned. + * @param[in] dac Base address of DAC module. + * @return None + * @details User has to load data into DAC_DAT[15:4] bits. DAC_DAT[31:16] and DAC_DAT[3:0] are ignored in DAC conversion. + * \hideinitializer + */ +#define DAC_ENABLE_LEFT_ALIGN(dac) ((dac)->CTL |= DAC_CTL_LALIGN_Msk) + +/** + * @brief Enable DAC data right-aligned. + * @param[in] dac Base address of DAC module. + * @return None + * @details User has to load data into DAC_DAT[11:0] bits, DAC_DAT[31:12] are ignored in DAC conversion. + * \hideinitializer + */ +#define DAC_ENABLE_RIGHT_ALIGN(dac) ((dac)->CTL &= ~DAC_CTL_LALIGN_Msk) + +/** + * @brief Enable output voltage buffer. + * @param[in] dac Base address of DAC module. + * @return None + * @details The DAC integrates a voltage output buffer that can be used to reduce output impedance and + * drive external loads directly without having to add an external operational amplifier. + * \hideinitializer + */ +#define DAC_ENABLE_BYPASS_BUFFER(dac) ((dac)->CTL |= DAC_CTL_BYPASS_Msk) + +/** + * @brief Disable output voltage buffer. + * @param[in] dac Base address of DAC module. + * @return None + * @details This macro is used to disable output voltage buffer. + * \hideinitializer + */ +#define DAC_DISABLE_BYPASS_BUFFER(dac) ((dac)->CTL &= ~DAC_CTL_BYPASS_Msk) + +/** + * @brief Enable the interrupt. + * @param[in] dac Base address of DAC module. + * @param[in] u32Ch Not used in M480 DAC. + * @return None + * @details This macro is used to enable DAC interrupt. + * \hideinitializer + */ +#define DAC_ENABLE_INT(dac, u32Ch) ((dac)->CTL |= DAC_CTL_DACIEN_Msk) + +/** + * @brief Disable the interrupt. + * @param[in] dac Base address of DAC module. + * @param[in] u32Ch Not used in M480 DAC. + * @return None + * @details This macro is used to disable DAC interrupt. + * \hideinitializer + */ +#define DAC_DISABLE_INT(dac, u32Ch) ((dac)->CTL &= ~DAC_CTL_DACIEN_Msk) + +/** + * @brief Enable DMA under-run interrupt. + * @param[in] dac Base address of DAC module. + * @return None + * @details This macro is used to enable DMA under-run interrupt. + * \hideinitializer + */ +#define DAC_ENABLE_DMAUDR_INT(dac) ((dac)->CTL |= DAC_CTL_DMAURIEN_Msk) + +/** + * @brief Disable DMA under-run interrupt. + * @param[in] dac Base address of DAC module. + * @return None + * @details This macro is used to disable DMA under-run interrupt. + * \hideinitializer + */ +#define DAC_DISABLE_DMAUDR_INT(dac) ((dac)->CTL &= ~DAC_CTL_DMAURIEN_Msk) + +/** + * @brief Enable PDMA mode. + * @param[in] dac Base address of DAC module. + * @return None + * @details DAC DMA request is generated when a hardware trigger event occurs while DMAEN (DAC_CTL[2]) is set. + * \hideinitializer + */ +#define DAC_ENABLE_PDMA(dac) ((dac)->CTL |= DAC_CTL_DMAEN_Msk) + +/** + * @brief Disable PDMA mode. + * @param[in] dac Base address of DAC module. + * @return None + * @details This macro is used to disable DMA mode. + * \hideinitializer + */ +#define DAC_DISABLE_PDMA(dac) ((dac)->CTL &= ~DAC_CTL_DMAEN_Msk) + +/** + * @brief Write data for conversion. + * @param[in] dac Base address of DAC module. + * @param[in] u32Ch Not used in M480 DAC. + * @param[in] u32Data Decides the data for conversion, valid range are between 0~0xFFF. + * @return None + * @details 12 bit left alignment: user has to load data into DAC_DAT[15:4] bits. + * 12 bit right alignment: user has to load data into DAC_DAT[11:0] bits. + * \hideinitializer + */ +#define DAC_WRITE_DATA(dac, u32Ch, u32Data) ((dac)->DAT = (u32Data)) + +/** + * @brief Read DAC 12-bit holding data. + * @param[in] dac Base address of DAC module. + * @param[in] u32Ch Not used in M480 DAC. + * @return Return DAC 12-bit holding data. + * @details This macro is used to read DAC_DAT register. + * \hideinitializer + */ +#define DAC_READ_DATA(dac, u32Ch) ((dac)->DAT) + +/** + * @brief Get the busy state of DAC. + * @param[in] dac Base address of DAC module. + * @param[in] u32Ch Not used in M480 DAC. + * @retval 0 Idle state. + * @retval 1 Busy state. + * @details This macro is used to read BUSY bit (DAC_STATUS[8]) to get busy state. + * \hideinitializer + */ +#define DAC_IS_BUSY(dac, u32Ch) (((dac)->STATUS & DAC_STATUS_BUSY_Msk) >> DAC_STATUS_BUSY_Pos) + +/** + * @brief Get the interrupt flag. + * @param[in] dac Base address of DAC module. + * @param[in] u32Ch Not used in M480 DAC. + * @retval 0 DAC is in conversion state. + * @retval 1 DAC conversion finish. + * @details This macro is used to read FINISH bit (DAC_STATUS[0]) to get DAC conversion complete finish flag. + * \hideinitializer + */ +#define DAC_GET_INT_FLAG(dac, u32Ch) ((dac)->STATUS & DAC_STATUS_FINISH_Msk) + +/** + * @brief Get the DMA under-run flag. + * @param[in] dac Base address of DAC module. + * @retval 0 No DMA under-run error condition occurred. + * @retval 1 DMA under-run error condition occurred. + * @details This macro is used to read DMAUDR bit (DAC_STATUS[1]) to get DMA under-run state. + * \hideinitializer + */ +#define DAC_GET_DMAUDR_FLAG(dac) (((dac)->STATUS & DAC_STATUS_DMAUDR_Msk) >> DAC_STATUS_DMAUDR_Pos) + +/** + * @brief This macro clear the interrupt status bit. + * @param[in] dac Base address of DAC module. + * @param[in] u32Ch Not used in M480 DAC. + * @return None + * @details User writes FINISH bit (DAC_STATUS[0]) to clear DAC conversion complete finish flag. + * \hideinitializer + */ +#define DAC_CLR_INT_FLAG(dac, u32Ch) ((dac)->STATUS = DAC_STATUS_FINISH_Msk) + +/** + * @brief This macro clear the DMA under-run flag. + * @param[in] dac Base address of DAC module. + * @return None + * @details User writes DMAUDR bit (DAC_STATUS[1]) to clear DMA under-run flag. + * \hideinitializer + */ +#define DAC_CLR_DMAUDR_FLAG(dac) ((dac)->STATUS = DAC_STATUS_DMAUDR_Msk) + + +/** + * @brief Enable DAC group mode + * @param[in] dac Base address of DAC module. + * @return None + * \hideinitializer + */ +#define DAC_ENABLE_GROUP_MODE(dac) (DAC0->CTL |= DAC_CTL_GRPEN_Msk) + +/** + * @brief Disable DAC group mode + * @param[in] dac Base address of DAC module. + * @return None + * \hideinitializer + */ +#define DAC_DISABLE_GROUP_MODE(dac) (DAC0->CTL &= ~DAC_CTL_GRPEN_Msk) + +void DAC_Open(DAC_T *dac, uint32_t u32Ch, uint32_t u32TrgSrc); +void DAC_Close(DAC_T *dac, uint32_t u32Ch); +uint32_t DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay); + +/*@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group DAC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_DAC_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_eadc.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_eadc.h new file mode 100644 index 0000000000000000000000000000000000000000..c9bd0ef39bcfe92a4c5a05e6b739b3f942dfc5f3 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_eadc.h @@ -0,0 +1,616 @@ +/**************************************************************************//** + * @file nu_eadc.h + * @version V0.10 + * @brief M480 series EADC driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __NU_EADC_H__ +#define __NU_EADC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EADC_Driver EADC Driver + @{ +*/ + +/** @addtogroup EADC_EXPORTED_CONSTANTS EADC Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* EADC_CTL Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EADC_CTL_DIFFEN_SINGLE_END (0UL<CTL |= EADC_CTL_ADCRST_Msk) + +/** + * @brief Enable PDMA transfer. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details When A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, + * user can enable this bit to generate a PDMA data transfer request. + * @note When set PDMAEN bit (EADC_CTL[11]), user must set ADINTENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt. + * \hideinitializer + */ +#define EADC_ENABLE_PDMA(eadc) ((eadc)->CTL |= EADC_CTL_PDMAEN_Msk) + +/** + * @brief Disable PDMA transfer. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable PDMA transfer. + * \hideinitializer + */ +#define EADC_DISABLE_PDMA(eadc) ((eadc)->CTL &= (~EADC_CTL_PDMAEN_Msk)) + +/** + * @brief Enable Sample Module PDMA transfer. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. + * This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF. + * @return None + * @details When A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, + * user can enable this bit to generate a PDMA data transfer request. + * \hideinitializer + */ +#define EADC_ENABLE_SAMPLE_MODULE_PDMA(eadc, u32ModuleMask) ((eadc)->PDMACTL |= u32ModuleMask) + +/** + * @brief Disable Sample Module PDMA transfer. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. + * This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF. + * @return None + * @details This macro is used to disable sample module PDMA transfer. + * \hideinitializer + */ +#define EADC_DISABLE_SAMPLE_MODULE_PDMA(eadc, u32ModuleMask) ((eadc)->PDMACTL &= (~u32ModuleMask)) + +/** + * @brief Enable double buffer mode. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3. + * @return None + * @details The ADC controller supports a double buffer mode in sample module 0~3. + * If user enable DBMEN (EADC_SCTLn[23], n=0~3), the double buffer mode will enable. + * \hideinitializer + */ +#define EADC_ENABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_DBMEN_Msk) + +/** + * @brief Disable double buffer mode. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3. + * @return None + * @details Sample has one sample result register. + * \hideinitializer + */ +#define EADC_DISABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_DBMEN_Msk) + +/** + * @brief Set ADIFn at A/D end of conversion. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @return None + * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the start of conversion. + * \hideinitializer + */ +#define EADC_ENABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_INTPOS_Msk) + +/** + * @brief Set ADIFn at A/D start of conversion. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @return None + * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the end of conversion. + * \hideinitializer + */ +#define EADC_DISABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_INTPOS_Msk) + +/** + * @brief Enable the interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status. + * This parameter decides which interrupts will be enabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3. + * @return None + * @details The A/D converter generates a conversion end ADIFn (EADC_STATUS2[n]) upon the end of specific sample module A/D conversion. + * If ADCIENn bit (EADC_CTL[n+2]) is set then conversion end interrupt request ADINTn is generated (n=0~3). + * \hideinitializer + */ +#define EADC_ENABLE_INT(eadc, u32Mask) ((eadc)->CTL |= ((u32Mask) << EADC_CTL_ADCIEN0_Pos)) + +/** + * @brief Disable the interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status. + * This parameter decides which interrupts will be disabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3. + * @return None + * @details Specific sample module A/D ADINT0 interrupt function Disabled. + * \hideinitializer + */ +#define EADC_DISABLE_INT(eadc, u32Mask) ((eadc)->CTL &= ~((u32Mask) << EADC_CTL_ADCIEN0_Pos)) + +/** + * @brief Enable the sample module interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3. + * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. + * This parameter decides which sample module interrupts will be enabled, valid range are between 1~0x7FFFF. + * @return None + * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address. + * \hideinitializer + */ +#define EADC_ENABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] |= (u32ModuleMask)) + +/** + * @brief Disable the sample module interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3. + * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. + * This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF. + * @return None + * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address. + * \hideinitializer + */ +#define EADC_DISABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] &= ~(u32ModuleMask)) + +/** + * @brief Set the input mode output format. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Format Decides the output format. Valid values are: + * - EADC_CTL_DMOF_STRAIGHT_BINARY :Select the straight binary format as the output format of the conversion result. + * - EADC_CTL_DMOF_TWOS_COMPLEMENT :Select the 2's complement format as the output format of the conversion result. + * @return None + * @details The macro is used to set A/D input mode output format. + * \hideinitializer + */ +#define EADC_SET_DMOF(eadc, u32Format) ((eadc)->CTL = ((eadc)->CTL & ~EADC_CTL_DMOF_Msk) | (u32Format)) + +/** + * @brief Start the A/D conversion. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module. + * This parameter decides which sample module will be conversion, valid range are between 1~0x7FFFF. + * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module 18. + * @return None + * @details After write EADC_SWTRG register to start ADC conversion, the EADC_PENDSTS register will show which SAMPLE will conversion. + * \hideinitializer + */ +#define EADC_START_CONV(eadc, u32ModuleMask) ((eadc)->SWTRG = (u32ModuleMask)) + +/** + * @brief Cancel the conversion for sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module. + * This parameter decides which sample module will stop the conversion, valid range are between 1~0x7FFFF. + * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module18. + * @return None + * @details If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it. + * \hideinitializer + */ +#define EADC_STOP_CONV(eadc, u32ModuleMask) ((eadc)->PENDSTS = (u32ModuleMask)) + +/** + * @brief Get the conversion pending flag. + * @param[in] eadc The pointer of the specified EADC module. + * @return Return the conversion pending sample module. + * @details This STPFn(EADC_PENDSTS[18:0]) bit remains 1 during pending state, when the respective ADC conversion is end, + * the STPFn (n=0~18) bit is automatically cleared to 0. + * \hideinitializer + */ +#define EADC_GET_PENDING_CONV(eadc) ((eadc)->PENDSTS) + +/** + * @brief Get the conversion data of the user-specified sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18. + * @return Return the conversion data of the user-specified sample module. + * @details This macro is used to read RESULT bit (EADC_DATn[15:0], n=0~18) field to get conversion data. + * \hideinitializer + */ +#define EADC_GET_CONV_DATA(eadc, u32ModuleNum) ((eadc)->DAT[(u32ModuleNum)] & EADC_DAT_RESULT_Msk) + +/** + * @brief Get the data overrun flag of the user-specified sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of data overrun status bits. Each bit corresponds to a data overrun status, valid range are between 1~0x7FFFF. + * @return Return the data overrun flag of the user-specified sample module. + * @details This macro is used to read OV bit (EADC_STATUS0[31:16], EADC_STATUS1[18:16]) field to get data overrun status. + * \hideinitializer + */ +#define EADC_GET_DATA_OVERRUN_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 >> EADC_STATUS0_OV_Pos) | ((eadc)->STATUS1 & EADC_STATUS1_OV_Msk)) & (u32ModuleMask)) + +/** + * @brief Get the data valid flag of the user-specified sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of data valid status bits. Each bit corresponds to a data valid status, valid range are between 1~0x7FFFF. + * @return Return the data valid flag of the user-specified sample module. + * @details This macro is used to read VALID bit (EADC_STATUS0[15:0], EADC_STATUS1[2:0]) field to get data valid status. + * \hideinitializer + */ +#define EADC_GET_DATA_VALID_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 & EADC_STATUS0_VALID_Msk) | (((eadc)->STATUS1 & EADC_STATUS1_VALID_Msk) << 16)) & (u32ModuleMask)) + +/** + * @brief Get the double data of the user-specified sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18. + * @return Return the double data of the user-specified sample module. + * @details This macro is used to read RESULT bit (EADC_DDATn[15:0], n=0~3) field to get conversion data. + * \hideinitializer + */ +#define EADC_GET_DOUBLE_DATA(eadc, u32ModuleNum) ((eadc)->DDAT[(u32ModuleNum)] & EADC_DDAT0_RESULT_Msk) + +/** + * @brief Get the user-specified interrupt flags. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Mask The combination of interrupt status bits. Each bit corresponds to a interrupt status. + * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3. + * Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3. + * @return Return the user-specified interrupt flags. + * @details This macro is used to get the user-specified interrupt flags. + * \hideinitializer + */ +#define EADC_GET_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 & (u32Mask)) + +/** + * @brief Get the user-specified sample module overrun flags. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status, valid range are between 1~0x7FFFF. + * @return Return the user-specified sample module overrun flags. + * @details This macro is used to get the user-specified sample module overrun flags. + * \hideinitializer + */ +#define EADC_GET_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS & (u32ModuleMask)) + +/** + * @brief Clear the selected interrupt status bits. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Mask The combination of compare interrupt status bits. Each bit corresponds to a compare interrupt status. + * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3. + * Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3. + * @return None + * @details This macro is used to clear clear the selected interrupt status bits. + * \hideinitializer + */ +#define EADC_CLR_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 = (u32Mask)) + +/** + * @brief Clear the selected sample module overrun status bits. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status. + * Bit 0 is SPOVF0, bit 1 is SPOVF1..., bit 18 is SPOVF18. + * @return None + * @details This macro is used to clear the selected sample module overrun status bits. + * \hideinitializer + */ +#define EADC_CLR_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS = (u32ModuleMask)) + +/** + * @brief Check all sample module A/D result data register overrun flags. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 None of sample module data register overrun flag is set to 1. + * @retval 1 Any one of sample module data register overrun flag is set to 1. + * @details The AOV bit (EADC_STATUS2[27]) will keep 1 when any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1. + * \hideinitializer + */ +#define EADC_IS_DATA_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AOV_Msk) >> EADC_STATUS2_AOV_Pos) + +/** + * @brief Check all sample module A/D result data register valid flags. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 None of sample module data register valid flag is set to 1. + * @retval 1 Any one of sample module data register valid flag is set to 1. + * @details The AVALID bit (EADC_STATUS2[26]) will keep 1 when any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1. + * \hideinitializer + */ +#define EADC_IS_DATA_VALID(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AVALID_Msk) >> EADC_STATUS2_AVALID_Pos) + +/** + * @brief Check all A/D sample module start of conversion overrun flags. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 None of sample module event overrun flag is set to 1. + * @retval 1 Any one of sample module event overrun flag is set to 1. + * @details The STOVF bit (EADC_STATUS2[25]) will keep 1 when any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1. + * \hideinitializer + */ +#define EADC_IS_SAMPLE_MODULE_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_STOVF_Msk) >> EADC_STATUS2_STOVF_Pos) + +/** + * @brief Check all A/D interrupt flag overrun bits. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 None of ADINT interrupt flag is overwritten to 1. + * @retval 1 Any one of ADINT interrupt flag is overwritten to 1. + * @details The ADOVIF bit (EADC_STATUS2[24]) will keep 1 when any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1. + * \hideinitializer + */ +#define EADC_IS_INT_FLAG_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_ADOVIF_Msk) >> EADC_STATUS2_ADOVIF_Pos) + +/** + * @brief Get the busy state of EADC. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 Idle state. + * @retval 1 Busy state. + * @details This macro is used to read BUSY bit (EADC_STATUS2[23]) to get busy state. + * \hideinitializer + */ +#define EADC_IS_BUSY(eadc) (((eadc)->STATUS2 & EADC_STATUS2_BUSY_Msk) >> EADC_STATUS2_BUSY_Pos) + +/** + * @brief Configure the comparator 0 and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. + * @param[in] u32Condition specifies the compare condition. Valid values are: + * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" + * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value + * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. + * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF. + * @return None + * @details For example, ADC_ENABLE_CMP0(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE); + * Means EADC will assert comparator 0 flag if sample module 5 conversion result is greater or + * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. + * \hideinitializer + */ +#define EADC_ENABLE_CMP0(eadc,\ + u32ModuleNum,\ + u32Condition,\ + u16CMPData,\ + u32MatchCount) ((eadc)->CMP[0] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ + (u32Condition) |\ + ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ + (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\ + EADC_CMP_ADCMPEN_Msk)) + +/** + * @brief Configure the comparator 1 and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. + * @param[in] u32Condition specifies the compare condition. Valid values are: + * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" + * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value + * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. + * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF. + * @return None + * @details For example, ADC_ENABLE_CMP1(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE); + * Means EADC will assert comparator 1 flag if sample module 5 conversion result is greater or + * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. + * \hideinitializer + */ +#define EADC_ENABLE_CMP1(eadc,\ + u32ModuleNum,\ + u32Condition,\ + u16CMPData,\ + u32MatchCount) ((eadc)->CMP[1] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ + (u32Condition) |\ + ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ + (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\ + EADC_CMP_ADCMPEN_Msk)) + +/** + * @brief Configure the comparator 2 and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. + * @param[in] u32Condition specifies the compare condition. Valid values are: + * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" + * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value + * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. + * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF. + * @return None + * @details For example, ADC_ENABLE_CMP2(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE); + * Means EADC will assert comparator 2 flag if sample module 5 conversion result is greater or + * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. + * \hideinitializer + */ +#define EADC_ENABLE_CMP2(eadc,\ + u32ModuleNum,\ + u32Condition,\ + u16CMPData,\ + u32MatchCount) ((eadc)->CMP[2] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ + (u32Condition) |\ + ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ + (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\ + EADC_CMP_ADCMPEN_Msk)) + +/** + * @brief Configure the comparator 3 and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. + * @param[in] u32Condition specifies the compare condition. Valid values are: + * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" + * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value + * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. + * @param[in] u32MatchCount specifies the match count setting, valid range are between 1~0xF. + * @return None + * @details For example, ADC_ENABLE_CMP3(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE); + * Means EADC will assert comparator 3 flag if sample module 5 conversion result is greater or + * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. + * \hideinitializer + */ +#define EADC_ENABLE_CMP3(eadc,\ + u32ModuleNum,\ + u32Condition,\ + u16CMPData,\ + u32MatchCount) ((eadc)->CMP[3] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ + (u32Condition) |\ + ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ + (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\ + EADC_CMP_ADCMPEN_Msk)) + +/** + * @brief Enable the compare window mode. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2. + * @return None + * @details ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched. + * \hideinitializer + */ +#define EADC_ENABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_CMPWEN_Msk) + +/** + * @brief Disable the compare window mode. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2. + * @return None + * @details ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched. + * \hideinitializer + */ +#define EADC_DISABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_CMPWEN_Msk) + +/** + * @brief Enable the compare interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3. + * @return None + * @details If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) + * and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, + * if ADCMPIE is set to 1, a compare interrupt request is generated. + * \hideinitializer + */ +#define EADC_ENABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_ADCMPIE_Msk) + +/** + * @brief Disable the compare interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3. + * @return None + * @details This macro is used to disable the compare interrupt. + * \hideinitializer + */ +#define EADC_DISABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_ADCMPIE_Msk) + +/** + * @brief Disable comparator 0. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable comparator 0. + * \hideinitializer + */ +#define EADC_DISABLE_CMP0(eadc) ((eadc)->CMP[0] = 0) + +/** + * @brief Disable comparator 1. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable comparator 1. + * \hideinitializer + */ +#define EADC_DISABLE_CMP1(eadc) ((eadc)->CMP[1] = 0) + +/** + * @brief Disable comparator 2. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable comparator 2. + * \hideinitializer + */ +#define EADC_DISABLE_CMP2(eadc) ((eadc)->CMP[2] = 0) + +/** + * @brief Disable comparator 3. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable comparator 3. + * \hideinitializer + */ +#define EADC_DISABLE_CMP3(eadc) ((eadc)->CMP[3] = 0) + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define EADC functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +void EADC_Open(EADC_T *eadc, uint32_t u32InputMode); +void EADC_Close(EADC_T *eadc); +void EADC_ConfigSampleModule(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerSrc, uint32_t u32Channel); +void EADC_SetTriggerDelayTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerDelayTime, uint32_t u32DelayClockDivider); +void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime); + +/*@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EADC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_EADC_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_ebi.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_ebi.h new file mode 100644 index 0000000000000000000000000000000000000000..cd9c4998122f8b1c5816b1f7b941c1c2f8b2a471 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_ebi.h @@ -0,0 +1,352 @@ +/**************************************************************************//** + * @file nu_ebi.h + * @version V3.00 + * @brief M480 series External Bus Interface(EBI) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_EBI_H__ +#define __NU_EBI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EBI_Driver EBI Driver + @{ +*/ + +/** @addtogroup EBI_EXPORTED_CONSTANTS EBI Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* Miscellaneous Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_BANK0_BASE_ADDR 0x60000000UL /*!< EBI bank0 base address \hideinitializer */ +#define EBI_BANK1_BASE_ADDR 0x60100000UL /*!< EBI bank1 base address \hideinitializer */ +#define EBI_BANK2_BASE_ADDR 0x60200000UL /*!< EBI bank2 base address \hideinitializer */ +#define EBI_MAX_SIZE 0x00100000UL /*!< Maximum EBI size for each bank is 1 MB \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Constants for EBI bank number */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_BANK0 0UL /*!< EBI bank 0 \hideinitializer */ +#define EBI_BANK1 1UL /*!< EBI bank 1 \hideinitializer */ +#define EBI_BANK2 2UL /*!< EBI bank 2 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Constants for EBI data bus width */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_BUSWIDTH_8BIT 8UL /*!< EBI bus width is 8-bit \hideinitializer */ +#define EBI_BUSWIDTH_16BIT 16UL /*!< EBI bus width is 16-bit \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Constants for EBI CS Active Level */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_CS_ACTIVE_LOW 0UL /*!< EBI CS active level is low \hideinitializer */ +#define EBI_CS_ACTIVE_HIGH 1UL /*!< EBI CS active level is high \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Constants for EBI MCLK divider and Timing */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_MCLKDIV_1 0x0UL /*!< EBI output clock(MCLK) is HCLK/1 \hideinitializer */ +#define EBI_MCLKDIV_2 0x1UL /*!< EBI output clock(MCLK) is HCLK/2 \hideinitializer */ +#define EBI_MCLKDIV_4 0x2UL /*!< EBI output clock(MCLK) is HCLK/4 \hideinitializer */ +#define EBI_MCLKDIV_8 0x3UL /*!< EBI output clock(MCLK) is HCLK/8 \hideinitializer */ +#define EBI_MCLKDIV_16 0x4UL /*!< EBI output clock(MCLK) is HCLK/16 \hideinitializer */ +#define EBI_MCLKDIV_32 0x5UL /*!< EBI output clock(MCLK) is HCLK/32 \hideinitializer */ +#define EBI_MCLKDIV_64 0x6UL /*!< EBI output clock(MCLK) is HCLK/64 \hideinitializer */ +#define EBI_MCLKDIV_128 0x7UL /*!< EBI output clock(MCLK) is HCLK/128 \hideinitializer */ + +#define EBI_TIMING_FASTEST 0x0UL /*!< EBI timing is the fastest \hideinitializer */ +#define EBI_TIMING_VERYFAST 0x1UL /*!< EBI timing is very fast \hideinitializer */ +#define EBI_TIMING_FAST 0x2UL /*!< EBI timing is fast \hideinitializer */ +#define EBI_TIMING_NORMAL 0x3UL /*!< EBI timing is normal \hideinitializer */ +#define EBI_TIMING_SLOW 0x4UL /*!< EBI timing is slow \hideinitializer */ +#define EBI_TIMING_VERYSLOW 0x5UL /*!< EBI timing is very slow \hideinitializer */ +#define EBI_TIMING_SLOWEST 0x6UL /*!< EBI timing is the slowest \hideinitializer */ + +#define EBI_OPMODE_NORMAL 0x0UL /*!< EBI bus operate in normal mode \hideinitializer */ +#define EBI_OPMODE_CACCESS (EBI_CTL_CACCESS_Msk) /*!< EBI bus operate in Continuous Data Access mode \hideinitializer */ +#define EBI_OPMODE_ADSEPARATE (EBI_CTL_ADSEPEN_Msk) /*!< EBI bus operate in AD Separate mode \hideinitializer */ + +/*@}*/ /* end of group EBI_EXPORTED_CONSTANTS */ + + +/** @addtogroup EBI_EXPORTED_FUNCTIONS EBI Exported Functions + @{ +*/ + +/** + * @brief Read 8-bit data on EBI bank0 + * + * @param[in] u32Addr The data address on EBI bank0. + * + * @return 8-bit Data + * + * @details This macro is used to read 8-bit data from specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK0_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 8-bit data to EBI bank0 + * + * @param[in] u32Addr The data address on EBI bank0. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 8-bit data to specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 16-bit data on EBI bank0 + * + * @param[in] u32Addr The data address on EBI bank0. + * + * @return 16-bit Data + * + * @details This macro is used to read 16-bit data from specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK0_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 16-bit data to EBI bank0 + * + * @param[in] u32Addr The data address on EBI bank0. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 16-bit data to specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 32-bit data on EBI bank0 + * + * @param[in] u32Addr The data address on EBI bank0. + * + * @return 32-bit Data + * + * @details This macro is used to read 32-bit data from specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK0_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 32-bit data to EBI bank0 + * + * @param[in] u32Addr The data address on EBI bank0. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 32-bit data to specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 8-bit data on EBI bank1 + * + * @param[in] u32Addr The data address on EBI bank1. + * + * @return 8-bit Data + * + * @details This macro is used to read 8-bit data from specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK1_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 8-bit data to EBI bank1 + * + * @param[in] u32Addr The data address on EBI bank1. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 8-bit data to specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 16-bit data on EBI bank1 + * + * @param[in] u32Addr The data address on EBI bank1. + * + * @return 16-bit Data + * + * @details This macro is used to read 16-bit data from specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK1_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 16-bit data to EBI bank1 + * + * @param[in] u32Addr The data address on EBI bank1. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 16-bit data to specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 32-bit data on EBI bank1 + * + * @param[in] u32Addr The data address on EBI bank1. + * + * @return 32-bit Data + * + * @details This macro is used to read 32-bit data from specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK1_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 32-bit data to EBI bank1 + * + * @param[in] u32Addr The data address on EBI bank1. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 32-bit data to specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 8-bit data on EBI bank2 + * + * @param[in] u32Addr The data address on EBI bank2. + * + * @return 8-bit Data + * + * @details This macro is used to read 8-bit data from specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK2_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 8-bit data to EBI bank2 + * + * @param[in] u32Addr The data address on EBI bank2. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 8-bit data to specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK2_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 16-bit data on EBI bank2 + * + * @param[in] u32Addr The data address on EBI bank2. + * + * @return 16-bit Data + * + * @details This macro is used to read 16-bit data from specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK2_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 16-bit data to EBI bank2 + * + * @param[in] u32Addr The data address on EBI bank2. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 16-bit data to specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK2_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 32-bit data on EBI bank2 + * + * @param[in] u32Addr The data address on EBI bank2. + * + * @return 32-bit Data + * + * @details This macro is used to read 32-bit data from specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK2_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 32-bit data to EBI bank2 + * + * @param[in] u32Addr The data address on EBI bank2. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 32-bit data to specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK2_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Enable EBI Write Buffer + * + * @param None + * + * @return None + * + * @details This macro is used to improve EBI write operation for all EBI banks. + * \hideinitializer + */ +#define EBI_ENABLE_WRITE_BUFFER() (EBI->CTL0 |= EBI_CTL_WBUFEN_Msk); + +/** + * @brief Disable EBI Write Buffer + * + * @param None + * + * @return None + * + * @details This macro is used to disable EBI write buffer function. + * \hideinitializer + */ +#define EBI_DISABLE_WRITE_BUFFER() (EBI->CTL0 &= ~EBI_CTL_WBUFEN_Msk); + +void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel); +void EBI_Close(uint32_t u32Bank); +void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv); + +/*@}*/ /* end of group EBI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EBI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_ecap.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_ecap.h new file mode 100644 index 0000000000000000000000000000000000000000..ebcf061ac067ccd2f7d062c15bac67380853312e --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_ecap.h @@ -0,0 +1,458 @@ +/**************************************************************************//** + * @file nu_ecap.h + * @version V3.00 + * @brief EnHanced Input Capture Timer(ECAP) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __NU_ECAP_H__ +#define __NU_ECAP_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup ECAP_Driver ECAP Driver + @{ +*/ + +/** @addtogroup ECAP_EXPORTED_CONSTANTS ECAP Exported Constants + @{ +*/ + +#define ECAP_IC0 (0UL) /*!< ECAP IC0 Unit \hideinitializer */ +#define ECAP_IC1 (1UL) /*!< ECAP IC1 Unit \hideinitializer */ +#define ECAP_IC2 (2UL) /*!< ECAP IC2 Unit \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* ECAP CTL0 constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define ECAP_NOISE_FILTER_CLKDIV_1 (0UL<CTL0 = ((ecap)->CTL0 & ~ECAP_CTL0_NFCLKSEL_Msk)|(u32ClkSel)) + +/** + * @brief This macro is used to disable noise filter + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable the noise filter of input capture. + * \hideinitializer + */ +#define ECAP_NOISE_FILTER_DISABLE(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CAPNFDIS_Msk) + +/** + * @brief This macro is used to enable noise filter + * @param[in] ecap Specify ECAP port + * @param[in] u32ClkSel Select noise filter clock divide number + * - \ref ECAP_NOISE_FILTER_CLKDIV_1 + * - \ref ECAP_NOISE_FILTER_CLKDIV_2 + * - \ref ECAP_NOISE_FILTER_CLKDIV_4 + * - \ref ECAP_NOISE_FILTER_CLKDIV_16 + * - \ref ECAP_NOISE_FILTER_CLKDIV_32 + * - \ref ECAP_NOISE_FILTER_CLKDIV_64 + * @return None + * @details This macro will enable the noise filter of input capture and set noise filter clock divide. + * \hideinitializer + */ +#define ECAP_NOISE_FILTER_ENABLE(ecap, u32ClkSel) ((ecap)->CTL0 = ((ecap)->CTL0 & ~(ECAP_CTL0_CAPNFDIS_Msk|ECAP_CTL0_NFCLKSEL_Msk))|(u32ClkSel)) + +/** + * @brief This macro is used to enable input channel unit + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_CTL0_IC0EN_Msk + * - \ref ECAP_CTL0_IC1EN_Msk + * - \ref ECAP_CTL0_IC2EN_Msk + * @return None + * @details This macro will enable the input channel_n to input capture. + * \hideinitializer + */ +#define ECAP_ENABLE_INPUT_CHANNEL(ecap, u32Mask) ((ecap)->CTL0 |= (u32Mask)) + +/** + * @brief This macro is used to disable input channel unit + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_CTL0_IC0EN_Msk + * - \ref ECAP_CTL0_IC1EN_Msk + * - \ref ECAP_CTL0_IC2EN_Msk + * @return None + * @details This macro will disable the input channel_n to input capture. + * \hideinitializer + */ +#define ECAP_DISABLE_INPUT_CHANNEL(ecap, u32Mask) ((ecap)->CTL0 &= ~(u32Mask)) + +/** + * @brief This macro is used to select input channel source + * @param[in] ecap Specify ECAP port + * @param[in] u32Index The input channel number + * - \ref ECAP_IC0 + * - \ref ECAP_IC1 + * - \ref ECAP_IC2 + * @param[in] u32Src The input source + * - \ref ECAP_CAP_INPUT_SRC_FROM_IC + * - \ref ECAP_CAP_INPUT_SRC_FROM_CH + * @return None + * @details This macro will select the input source from ICx, CHx. + * \hideinitializer + */ +#define ECAP_SEL_INPUT_SRC(ecap, u32Index, u32Src) ((ecap)->CTL0 = ((ecap)->CTL0 & ~(ECAP_CTL0_CAPSEL0_Msk<<((u32Index)<<1)))|(((u32Src)<CTL0 |= (u32Mask)) + +/** + * @brief This macro is used to disable input channel interrupt + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_IC0 + * - \ref ECAP_IC1 + * - \ref ECAP_IC2 + * @return None + * @details This macro will disable the input channel_n interrupt. + * \hideinitializer + */ +#define ECAP_DISABLE_INT(ecap, u32Mask) ((ecap)->CTL0 &= ~(u32Mask)) + +/** + * @brief This macro is used to enable input channel overflow interrupt + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will enable the input channel overflow interrupt. + * \hideinitializer + */ +#define ECAP_ENABLE_OVF_INT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_OVIEN_Msk) + +/** + * @brief This macro is used to disable input channel overflow interrupt + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable the input channel overflow interrupt. + * \hideinitializer + */ +#define ECAP_DISABLE_OVF_INT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_OVIEN_Msk) + +/** + * @brief This macro is used to enable input channel compare-match interrupt + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will enable the input channel compare-match interrupt. + * \hideinitializer + */ +#define ECAP_ENABLE_CMP_MATCH_INT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CMPIEN_Msk) + +/** + * @brief This macro is used to disable input channel compare-match interrupt + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable the input channel compare-match interrupt. + * \hideinitializer + */ +#define ECAP_DISABLE_CMP_MATCH_INT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CMPIEN_Msk) + +/** + * @brief This macro is used to start capture counter + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will start capture counter up-counting. + * \hideinitializer + */ +#define ECAP_CNT_START(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CNTEN_Msk) + +/** + * @brief This macro is used to stop capture counter + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will stop capture counter up-counting. + * \hideinitializer + */ +#define ECAP_CNT_STOP(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CNTEN_Msk) + +/** + * @brief This macro is used to set event to clear capture counter + * @param[in] ecap Specify ECAP port + * @param[in] u32Event The input channel number + * - \ref ECAP_CTL0_CMPCLREN_Msk + * - \ref ECAP_CTL1_CAP0RLDEN_Msk + * - \ref ECAP_CTL1_CAP1RLDEN_Msk + * - \ref ECAP_CTL1_CAP2RLDEN_Msk + * - \ref ECAP_CTL1_OVRLDEN_Msk + + * @return None + * @details This macro will enable and select compare or capture event that can clear capture counter. + * \hideinitializer + */ +#define ECAP_SET_CNT_CLEAR_EVENT(ecap, u32Event) do{ \ + if((u32Event) & ECAP_CTL0_CMPCLREN_Msk) \ + (ecap)->CTL0 |= ECAP_CTL0_CMPCLREN_Msk; \ + else \ + (ecap)->CTL0 &= ~ECAP_CTL0_CMPCLREN_Msk; \ + (ecap)->CTL1 = ((ecap)->CTL1 &~0xF00) | ((u32Event) & 0xF00); \ + }while(0); + +/** + * @brief This macro is used to enable compare function + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will enable the compare function. + * \hideinitializer + */ +#define ECAP_ENABLE_CMP(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CMPEN_Msk) + +/** + * @brief This macro is used to disable compare function + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable the compare function. + * \hideinitializer + */ +#define ECAP_DISABLE_CMP(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CMPEN_Msk) + +/** + * @brief This macro is used to enable input capture function. + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will enable input capture timer/counter. + * \hideinitializer + */ +#define ECAP_ENABLE_CNT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CAPEN_Msk) + +/** + * @brief This macro is used to disable input capture function. + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable input capture timer/counter. + * \hideinitializer + */ +#define ECAP_DISABLE_CNT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CAPEN_Msk) + +/** + * @brief This macro is used to select input channel edge detection + * @param[in] ecap Specify ECAP port + * @param[in] u32Index The input channel number + * - \ref ECAP_IC0 + * - \ref ECAP_IC1 + * - \ref ECAP_IC2 + * @param[in] u32Edge The input source + * - \ref ECAP_RISING_EDGE + * - \ref ECAP_FALLING_EDGE + * - \ref ECAP_RISING_FALLING_EDGE + * @return None + * @details This macro will select input capture can detect falling edge, rising edge or either rising or falling edge change. + * \hideinitializer + */ +#define ECAP_SEL_CAPTURE_EDGE(ecap, u32Index, u32Edge) ((ecap)->CTL1 = ((ecap)->CTL1 & ~(ECAP_CTL1_EDGESEL0_Msk<<((u32Index)<<1)))|((u32Edge)<<((u32Index)<<1))) + +/** + * @brief This macro is used to select ECAP counter reload trigger source + * @param[in] ecap Specify ECAP port + * @param[in] u32TrigSrc The input source + * - \ref ECAP_CTL1_CAP0RLDEN_Msk + * - \ref ECAP_CTL1_CAP1RLDEN_Msk + * - \ref ECAP_CTL1_CAP2RLDEN_Msk + * - \ref ECAP_CTL1_OVRLDEN_Msk + * @return None + * @details This macro will select capture counter reload trigger source. + * \hideinitializer + */ +#define ECAP_SEL_RELOAD_TRIG_SRC(ecap, u32TrigSrc) ((ecap)->CTL1 = ((ecap)->CTL1 & ~0xF00)|(u32TrigSrc)) + +/** + * @brief This macro is used to select capture timer clock divide. + * @param[in] ecap Specify ECAP port + * @param[in] u32Clkdiv The input source + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_1 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_4 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_16 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_32 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_64 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_96 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_112 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_128 + * @return None + * @details This macro will select capture timer clock has a pre-divider with eight divided option. + * \hideinitializer + */ +#define ECAP_SEL_TIMER_CLK_DIV(ecap, u32Clkdiv) ((ecap)->CTL1 = ((ecap)->CTL1 & ~ECAP_CTL1_CLKSEL_Msk)|(u32Clkdiv)) + +/** + * @brief This macro is used to select capture timer/counter clock source + * @param[in] ecap Specify ECAP port + * @param[in] u32ClkSrc The input source + * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP_CLK + * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP0 + * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP1 + * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP2 + * @return None + * @details This macro will select capture timer/clock clock source. + * \hideinitializer + */ +#define ECAP_SEL_TIMER_CLK_SRC(ecap, u32ClkSrc) ((ecap)->CTL1 = ((ecap)->CTL1 & ~ECAP_CTL1_CNTSRCSEL_Msk)|(u32ClkSrc)) + +/** + * @brief This macro is used to read input capture status + * @param[in] ecap Specify ECAP port + * @return Input capture status flags + * @details This macro will get the input capture interrupt status. + * \hideinitializer + */ +#define ECAP_GET_INT_STATUS(ecap) ((ecap)->STATUS) + +/** + * @brief This macro is used to get input channel interrupt flag + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_STATUS_CAPTF0_Msk + * - \ref ECAP_STATUS_CAPTF1_Msk + * - \ref ECAP_STATUS_CAPTF2_Msk + * - \ref ECAP_STATUS_CAPOVF_Msk + * - \ref ECAP_STATUS_CAPCMPF_Msk + * @return None + * @details This macro will write 1 to get the input channel_n interrupt flag. + * \hideinitializer + */ +#define ECAP_GET_CAPTURE_FLAG(ecap, u32Mask) (((ecap)->STATUS & (u32Mask))?1:0) + +/** + * @brief This macro is used to clear input channel interrupt flag + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_STATUS_CAPTF0_Msk + * - \ref ECAP_STATUS_CAPTF1_Msk + * - \ref ECAP_STATUS_CAPTF2_Msk + * - \ref ECAP_STATUS_CAPOVF_Msk + * - \ref ECAP_STATUS_CAPCMPF_Msk + * @return None + * @details This macro will write 1 to clear the input channel_n interrupt flag. + * \hideinitializer + */ +#define ECAP_CLR_CAPTURE_FLAG(ecap, u32Mask) ((ecap)->STATUS = (u32Mask)) + +/** + * @brief This macro is used to set input capture counter value + * @param[in] ecap Specify ECAP port + * @param[in] u32Val Counter value + * @return None + * @details This macro will set a counter value of input capture. + * \hideinitializer + */ +#define ECAP_SET_CNT_VALUE(ecap, u32Val) ((ecap)->CNT = (u32Val)) + +/** + * @brief This macro is used to get input capture counter value + * @param[in] ecap Specify ECAP port + * @return Capture counter value + * @details This macro will get a counter value of input capture. + * \hideinitializer + */ +#define ECAP_GET_CNT_VALUE(ecap) ((ecap)->CNT) + +/** + * @brief This macro is used to get input capture counter hold value + * @param[in] ecap Specify ECAP port + * @param[in] u32Index The input channel number + * - \ref ECAP_IC0 + * - \ref ECAP_IC1 + * - \ref ECAP_IC2 + * @return Capture counter hold value + * @details This macro will get a hold value of input capture channel_n. + * \hideinitializer + */ +#define ECAP_GET_CNT_HOLD_VALUE(ecap, u32Index) (*(__IO uint32_t *) (&((ecap)->HLD0) + (u32Index))) + +/** + * @brief This macro is used to set input capture counter compare value + * @param[in] ecap Specify ECAP port + * @param[in] u32Val Input capture compare value + * @return None + * @details This macro will set a compare value of input capture counter. + * \hideinitializer + */ +#define ECAP_SET_CNT_CMP(ecap, u32Val) ((ecap)->CNTCMP = (u32Val)) + +void ECAP_Open(ECAP_T* ecap, uint32_t u32FuncMask); +void ECAP_Close(ECAP_T* ecap); +void ECAP_EnableINT(ECAP_T* ecap, uint32_t u32Mask); +void ECAP_DisableINT(ECAP_T* ecap, uint32_t u32Mask); +/*@}*/ /* end of group ECAP_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group ECAP_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_ECAP_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_emac.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_emac.h new file mode 100644 index 0000000000000000000000000000000000000000..152873d76ac3018bdbc3c9b035759188bffa643a --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_emac.h @@ -0,0 +1,357 @@ +/**************************************************************************//** + * @file nu_emac.h + * @version V1.00 + * @brief M480 EMAC driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __NU_EMAC_H__ +#define __NU_EMAC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EMAC_Driver EMAC Driver + @{ +*/ + +/** @addtogroup EMAC_EXPORTED_CONSTANTS EMAC Exported Constants + @{ +*/ + +#define EMAC_PHY_ADDR 1UL /*!< PHY address, this address is board dependent \hideinitializer */ +#define EMAC_RX_DESC_SIZE 4UL /*!< Number of Rx Descriptors, should be 2 at least \hideinitializer */ +#define EMAC_TX_DESC_SIZE 4UL /*!< Number of Tx Descriptors, should be 2 at least \hideinitializer */ +#define EMAC_CAMENTRY_NB 16UL /*!< Number of CAM \hideinitializer */ +#define EMAC_MAX_PKT_SIZE 1524UL /*!< Number of HDR + EXTRA + VLAN_TAG + PAYLOAD + CRC \hideinitializer */ + +#define EMAC_LINK_DOWN 0UL /*!< Ethernet link is down \hideinitializer */ +#define EMAC_LINK_100F 1UL /*!< Ethernet link is 100Mbps full duplex \hideinitializer */ +#define EMAC_LINK_100H 2UL /*!< Ethernet link is 100Mbps half duplex \hideinitializer */ +#define EMAC_LINK_10F 3UL /*!< Ethernet link is 10Mbps full duplex \hideinitializer */ +#define EMAC_LINK_10H 4UL /*!< Ethernet link is 10Mbps half duplex \hideinitializer */ + +/*@}*/ /* end of group EMAC_EXPORTED_CONSTANTS */ + + +/** @addtogroup EMAC_EXPORTED_FUNCTIONS EMAC Exported Functions + @{ +*/ + + +/** + * @brief Enable EMAC Tx function + * @param None + * @return None + * \hideinitializer + */ +#define EMAC_ENABLE_TX() (EMAC->CTL |= EMAC_CTL_TXON_Msk) + + +/** + * @brief Enable EMAC Rx function + * @param None + * @return None + * \hideinitializer + */ +#define EMAC_ENABLE_RX() do{EMAC->CTL |= EMAC_CTL_RXON_Msk; EMAC->RXST = 0;}while(0) + +/** + * @brief Disable EMAC Tx function + * @param None + * @return None + * \hideinitializer + */ +#define EMAC_DISABLE_TX() (EMAC->CTL &= ~EMAC_CTL_TXON_Msk) + + +/** + * @brief Disable EMAC Rx function + * @param None + * @return None + * \hideinitializer + */ +#define EMAC_DISABLE_RX() (EMAC->CTL &= ~EMAC_CTL_RXON_Msk) + +/** + * @brief Enable EMAC Magic Packet Wakeup function + * @param None + * @return None + * \hideinitializer + */ +#define EMAC_ENABLE_MAGIC_PKT_WAKEUP() (EMAC->CTL |= EMAC_CTL_WOLEN_Msk) + +/** + * @brief Disable EMAC Magic Packet Wakeup function + * @param None + * @return None + * \hideinitializer + */ +#define EMAC_DISABLE_MAGIC_PKT_WAKEUP() (EMAC->CTL &= ~EMAC_CTL_WOLEN_Msk) + +/** + * @brief Enable EMAC to receive broadcast packets + * @param None + * @return None + * \hideinitializer + */ +#define EMAC_ENABLE_RECV_BCASTPKT() (EMAC->CAMCTL |= EMAC_CAMCTL_ABP_Msk) + +/** + * @brief Disable EMAC to receive broadcast packets + * @param None + * @return None + * \hideinitializer + */ +#define EMAC_DISABLE_RECV_BCASTPKT() (EMAC->CAMCTL &= ~EMAC_CAMCTL_ABP_Msk) + +/** + * @brief Enable EMAC to receive multicast packets + * @param None + * @return None + * \hideinitializer + */ +#define EMAC_ENABLE_RECV_MCASTPKT() (EMAC->CAMCTL |= EMAC_CAMCTL_AMP_Msk) + +/** + * @brief Disable EMAC Magic Packet Wakeup function + * @param None + * @return None + * \hideinitializer + */ +#define EMAC_DISABLE_RECV_MCASTPKT() (EMAC->CAMCTL &= ~EMAC_CAMCTL_AMP_Msk) + +/** + * @brief Check if EMAC time stamp alarm interrupt occurred or not + * @param None + * @return If time stamp alarm interrupt occurred or not + * @retval 0 Alarm interrupt does not occur + * @retval 1 Alarm interrupt occurred + * \hideinitializer + */ +#define EMAC_GET_ALARM_FLAG() (EMAC->INTSTS & EMAC_INTSTS_TSALMIF_Msk ? 1 : 0) + +/** + * @brief Clear EMAC time stamp alarm interrupt flag + * @param None + * @return None + * \hideinitializer + */ +#define EMAC_CLR_ALARM_FLAG() (EMAC->INTSTS = EMAC_INTSTS_TSALMIF_Msk) + +/** + * @brief Trigger EMAC Rx function + * @param None + * @return None + */ +#define EMAC_TRIGGER_RX() do{EMAC->RXST = 0UL;}while(0) + +/** + * @brief Trigger EMAC Tx function + * @param None + * @return None + */ +#define EMAC_TRIGGER_TX() do{EMAC->TXST = 0UL;}while(0) + +/** + * @brief Enable specified EMAC interrupt + * + * @param[in] emac The pointer of the specified EMAC module + * @param[in] u32eIntSel Interrupt type select + * - \ref EMAC_INTEN_RXIEN_Msk : Receive + * - \ref EMAC_INTEN_CRCEIEN_Msk : CRC Error + * - \ref EMAC_INTEN_RXOVIEN_Msk : Receive FIFO Overflow + * - \ref EMAC_INTEN_LPIEN_Msk : Long Packet + * - \ref EMAC_INTEN_RXGDIEN_Msk : Receive Good + * - \ref EMAC_INTEN_ALIEIEN_Msk : Alignment Error + * - \ref EMAC_INTEN_RPIEN_Msk : Runt Packet + * - \ref EMAC_INTEN_MPCOVIEN_Msk : Miss Packet Counter Overrun + * - \ref EMAC_INTEN_MFLEIEN_Msk : Maximum Frame Length Exceed + * - \ref EMAC_INTEN_DENIEN_Msk : DMA Early Notification + * - \ref EMAC_INTEN_RDUIEN_Msk : Receive Descriptor Unavailable + * - \ref EMAC_INTEN_RXBEIEN_Msk : Receive Bus Error + * - \ref EMAC_INTEN_CFRIEN_Msk : Control Frame Receive + * - \ref EMAC_INTEN_WOLIEN_Msk : Wake on LAN Interrupt + * - \ref EMAC_INTEN_TXIEN_Msk : Transmit + * - \ref EMAC_INTEN_TXUDIEN_Msk : Transmit FIFO Underflow + * - \ref EMAC_INTEN_TXCPIEN_Msk : Transmit Completion + * - \ref EMAC_INTEN_EXDEFIEN_Msk : Defer Exceed + * - \ref EMAC_INTEN_NCSIEN_Msk : No Carrier Sense + * - \ref EMAC_INTEN_TXABTIEN_Msk : Transmit Abort + * - \ref EMAC_INTEN_LCIEN_Msk : Late Collision + * - \ref EMAC_INTEN_TDUIEN_Msk : Transmit Descriptor Unavailable + * - \ref EMAC_INTEN_TXBEIEN_Msk : Transmit Bus Error + * - \ref EMAC_INTEN_TSALMIEN_Msk : Time Stamp Alarm + * + * @return None + * + * @details This macro enable specified EMAC interrupt. + * \hideinitializer + */ +#define EMAC_ENABLE_INT(emac, u32eIntSel) ((emac)->INTEN |= (u32eIntSel)) + +/** + * @brief Disable specified EMAC interrupt + * + * @param[in] emac The pointer of the specified EMAC module + * @param[in] u32eIntSel Interrupt type select + * - \ref EMAC_INTEN_RXIEN_Msk : Receive + * - \ref EMAC_INTEN_CRCEIEN_Msk : CRC Error + * - \ref EMAC_INTEN_RXOVIEN_Msk : Receive FIFO Overflow + * - \ref EMAC_INTEN_LPIEN_Msk : Long Packet + * - \ref EMAC_INTEN_RXGDIEN_Msk : Receive Good + * - \ref EMAC_INTEN_ALIEIEN_Msk : Alignment Error + * - \ref EMAC_INTEN_RPIEN_Msk : Runt Packet + * - \ref EMAC_INTEN_MPCOVIEN_Msk : Miss Packet Counter Overrun + * - \ref EMAC_INTEN_MFLEIEN_Msk : Maximum Frame Length Exceed + * - \ref EMAC_INTEN_DENIEN_Msk : DMA Early Notification + * - \ref EMAC_INTEN_RDUIEN_Msk : Receive Descriptor Unavailable + * - \ref EMAC_INTEN_RXBEIEN_Msk : Receive Bus Error + * - \ref EMAC_INTEN_CFRIEN_Msk : Control Frame Receive + * - \ref EMAC_INTEN_WOLIEN_Msk : Wake on LAN Interrupt + * - \ref EMAC_INTEN_TXIEN_Msk : Transmit + * - \ref EMAC_INTEN_TXUDIEN_Msk : Transmit FIFO Underflow + * - \ref EMAC_INTEN_TXCPIEN_Msk : Transmit Completion + * - \ref EMAC_INTEN_EXDEFIEN_Msk : Defer Exceed + * - \ref EMAC_INTEN_NCSIEN_Msk : No Carrier Sense + * - \ref EMAC_INTEN_TXABTIEN_Msk : Transmit Abort + * - \ref EMAC_INTEN_LCIEN_Msk : Late Collision + * - \ref EMAC_INTEN_TDUIEN_Msk : Transmit Descriptor Unavailable + * - \ref EMAC_INTEN_TXBEIEN_Msk : Transmit Bus Error + * - \ref EMAC_INTEN_TSALMIEN_Msk : Time Stamp Alarm + * + * @return None + * + * @details This macro disable specified EMAC interrupt. + * \hideinitializer + */ +#define EMAC_DISABLE_INT(emac, u32eIntSel) ((emac)->INTEN &= ~ (u32eIntSel)) + +/** + * @brief Get specified interrupt flag/status + * + * @param[in] emac The pointer of the specified EMAC module + * @param[in] u32eIntTypeFlag Interrupt Type Flag, should be + * - \ref EMAC_INTSTS_RXIF_Msk : Receive + * - \ref EMAC_INTSTS_CRCEIF_Msk : CRC Error + * - \ref EMAC_INTSTS_RXOVIF_Msk : Receive FIFO Overflow + * - \ref EMAC_INTSTS_LPIF_Msk : Long Packet + * - \ref EMAC_INTSTS_RXGDIF_Msk : Receive Good + * - \ref EMAC_INTSTS_ALIEIF_Msk : Alignment Error + * - \ref EMAC_INTSTS_RPIF_Msk : Runt Packet + * - \ref EMAC_INTSTS_MPCOVIF_Msk : Missed Packet Counter + * - \ref EMAC_INTSTS_MFLEIF_Msk : Maximum Frame Length Exceed + * - \ref EMAC_INTSTS_DENIF_Msk : DMA Early Notification + * - \ref EMAC_INTSTS_RDUIF_Msk : Receive Descriptor Unavailable + * - \ref EMAC_INTSTS_RXBEIF_Msk : Receive Bus Error + * - \ref EMAC_INTSTS_CFRIF_Msk : Control Frame Receive + * - \ref EMAC_INTSTS_WOLIF_Msk : Wake on LAN + * - \ref EMAC_INTSTS_TXIF_Msk : Transmit + * - \ref EMAC_INTSTS_TXUDIF_Msk : Transmit FIFO Underflow + * - \ref EMAC_INTSTS_TXCPIF_Msk : Transmit Completion + * - \ref EMAC_INTSTS_EXDEFIF_Msk : Defer Exceed + * - \ref EMAC_INTSTS_NCSIF_Msk : No Carrier Sense + * - \ref EMAC_INTSTS_TXABTIF_Msk : Transmit Abort + * - \ref EMAC_INTSTS_LCIF_Msk : Late Collision + * - \ref EMAC_INTSTS_TDUIF_Msk : Transmit Descriptor Unavailable + * - \ref EMAC_INTSTS_TXBEIF_Msk : Transmit Bus Error + * - \ref EMAC_INTSTS_TSALMIF_Msk : Time Stamp Alarm + * + * @return None + * + * @details This macro get specified interrupt flag or interrupt indicator status. + * \hideinitializer + */ +#define EMAC_GET_INT_FLAG(emac, u32eIntTypeFlag) (((emac)->INTSTS & (u32eIntTypeFlag))?1:0) + +/** + * @brief Clear specified interrupt flag/status + * + * @param[in] emac The pointer of the specified EMAC module + * @param[in] u32eIntTypeFlag Interrupt Type Flag, should be + * - \ref EMAC_INTSTS_RXIF_Msk : Receive + * - \ref EMAC_INTSTS_CRCEIF_Msk : CRC Error + * - \ref EMAC_INTSTS_RXOVIF_Msk : Receive FIFO Overflow + * - \ref EMAC_INTSTS_LPIF_Msk : Long Packet + * - \ref EMAC_INTSTS_RXGDIF_Msk : Receive Good + * - \ref EMAC_INTSTS_ALIEIF_Msk : Alignment Error + * - \ref EMAC_INTSTS_RPIF_Msk : Runt Packet + * - \ref EMAC_INTSTS_MPCOVIF_Msk : Missed Packet Counter + * - \ref EMAC_INTSTS_MFLEIF_Msk : Maximum Frame Length Exceed + * - \ref EMAC_INTSTS_DENIF_Msk : DMA Early Notification + * - \ref EMAC_INTSTS_RDUIF_Msk : Receive Descriptor Unavailable + * - \ref EMAC_INTSTS_RXBEIF_Msk : Receive Bus Error + * - \ref EMAC_INTSTS_CFRIF_Msk : Control Frame Receive + * - \ref EMAC_INTSTS_WOLIF_Msk : Wake on LAN + * - \ref EMAC_INTSTS_TXIF_Msk : Transmit + * - \ref EMAC_INTSTS_TXUDIF_Msk : Transmit FIFO Underflow + * - \ref EMAC_INTSTS_TXCPIF_Msk : Transmit Completion + * - \ref EMAC_INTSTS_EXDEFIF_Msk : Defer Exceed + * - \ref EMAC_INTSTS_NCSIF_Msk : No Carrier Sense + * - \ref EMAC_INTSTS_TXABTIF_Msk : Transmit Abort + * - \ref EMAC_INTSTS_LCIF_Msk : Late Collision + * - \ref EMAC_INTSTS_TDUIF_Msk : Transmit Descriptor Unavailable + * - \ref EMAC_INTSTS_TXBEIF_Msk : Transmit Bus Error + * - \ref EMAC_INTSTS_TSALMIF_Msk : Time Stamp Alarm + * + * @retval 0 The specified interrupt is not happened. + * 1 The specified interrupt is happened. + * + * @details This macro clear specified interrupt flag or interrupt indicator status. + * \hideinitializer + */ +#define EMAC_CLEAR_INT_FLAG(emac, u32eIntTypeFlag) ((emac)->INTSTS |= (u32eIntTypeFlag)) + +void EMAC_Open(uint8_t *pu8MacAddr); +void EMAC_Close(void); +void EMAC_SetMacAddr(uint8_t *pu8MacAddr); +void EMAC_EnableCamEntry(uint32_t u32Entry, uint8_t pu8MacAddr[]); +void EMAC_DisableCamEntry(uint32_t u32Entry); + +uint32_t EMAC_RecvPkt(uint8_t *pu8Data, uint32_t *pu32Size); +uint32_t EMAC_RecvPktTS(uint8_t *pu8Data, uint32_t *pu32Size, uint32_t *pu32Sec, uint32_t *pu32Nsec); +void EMAC_RecvPktDone(void); + +uint32_t EMAC_SendPkt(uint8_t *pu8Data, uint32_t u32Size); +uint32_t EMAC_SendPktDone(void); +uint32_t EMAC_SendPktDoneTS(uint32_t *pu32Sec, uint32_t *pu32Nsec); + +void EMAC_EnableTS(uint32_t u32Sec, uint32_t u32Nsec); +void EMAC_DisableTS(void); +void EMAC_GetTime(uint32_t *pu32Sec, uint32_t *pu32Nsec); +void EMAC_SetTime(uint32_t u32Sec, uint32_t u32Nsec); +void EMAC_UpdateTime(uint32_t u32Neg, uint32_t u32Sec, uint32_t u32Nsec); +void EMAC_EnableAlarm(uint32_t u32Sec, uint32_t u32Nsec); +void EMAC_DisableAlarm(void); + +uint32_t EMAC_CheckLinkStatus(void); + +void EMAC_PhyInit(void); +int32_t EMAC_FillCamEntry(uint8_t pu8MacAddr[]); +uint8_t *EMAC_ClaimFreeTXBuf(void); +uint32_t EMAC_GetAvailRXBufSize(uint8_t** ppuDataBuf); +uint32_t EMAC_SendPktWoCopy(uint32_t u32Size); +void EMAC_RecvPktDoneWoRxTrigger(void); + +/*@}*/ /* end of group EMAC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EMAC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_EMAC_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_epwm.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_epwm.h new file mode 100644 index 0000000000000000000000000000000000000000..01557f8054e6c4e0fa3d06bb9e320f2fde6a64bc --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_epwm.h @@ -0,0 +1,645 @@ +/**************************************************************************//** + * @file nu_epwm.h + * @version V3.00 + * @brief M480 series EPWM driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_EPWM_H__ +#define __NU_EPWM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EPWM_Driver EPWM Driver + @{ +*/ + +/** @addtogroup EPWM_EXPORTED_CONSTANTS EPWM Exported Constants + @{ +*/ +#define EPWM_CHANNEL_NUM (6U) /*!< EPWM channel number \hideinitializer */ +#define EPWM_CH_0_MASK (0x1U) /*!< EPWM channel 0 mask \hideinitializer */ +#define EPWM_CH_1_MASK (0x2U) /*!< EPWM channel 1 mask \hideinitializer */ +#define EPWM_CH_2_MASK (0x4U) /*!< EPWM channel 2 mask \hideinitializer */ +#define EPWM_CH_3_MASK (0x8U) /*!< EPWM channel 3 mask \hideinitializer */ +#define EPWM_CH_4_MASK (0x10U) /*!< EPWM channel 4 mask \hideinitializer */ +#define EPWM_CH_5_MASK (0x20U) /*!< EPWM channel 5 mask \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EPWM_UP_COUNTER (0U) /*!< Up counter type \hideinitializer */ +#define EPWM_DOWN_COUNTER (1U) /*!< Down counter type \hideinitializer */ +#define EPWM_UP_DOWN_COUNTER (2U) /*!< Up-Down counter type \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Aligned Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EPWM_EDGE_ALIGNED (1U) /*!< EPWM working in edge aligned type(down count) \hideinitializer */ +#define EPWM_CENTER_ALIGNED (2U) /*!< EPWM working in center aligned type \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Output Level Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EPWM_OUTPUT_NOTHING (0U) /*!< EPWM output nothing \hideinitializer */ +#define EPWM_OUTPUT_LOW (1U) /*!< EPWM output low \hideinitializer */ +#define EPWM_OUTPUT_HIGH (2U) /*!< EPWM output high \hideinitializer */ +#define EPWM_OUTPUT_TOGGLE (3U) /*!< EPWM output toggle \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Synchronous Start Function Control Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EPWM_SSCTL_SSRC_EPWM0 (0U<CTL1 = (epwm)->CTL1 | (0x7ul<CTL1 = (epwm)->CTL1 & ~(0x7ul<CTL0 = (epwm)->CTL0 | EPWM_CTL0_GROUPEN_Msk) + +/** + * @brief This macro disable group mode + * @param[in] epwm The pointer of the specified EPWM module + * @return None + * @details This macro is used to disable group mode of EPWM module. + * \hideinitializer + */ +#define EPWM_DISABLE_GROUP_MODE(epwm) ((epwm)->CTL0 = (epwm)->CTL0 & ~EPWM_CTL0_GROUPEN_Msk) + +/** + * @brief Enable timer synchronous start counting function of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32SyncSrc Synchronous start source selection, valid values are: + * - \ref EPWM_SSCTL_SSRC_EPWM0 + * - \ref EPWM_SSCTL_SSRC_EPWM1 + * - \ref EPWM_SSCTL_SSRC_BPWM0 + * - \ref EPWM_SSCTL_SSRC_BPWM1 + * @return None + * @details This macro is used to enable timer synchronous start counting function of specified channel(s). + * \hideinitializer + */ +#define EPWM_ENABLE_TIMER_SYNC(epwm, u32ChannelMask, u32SyncSrc) ((epwm)->SSCTL = ((epwm)->SSCTL & ~EPWM_SSCTL_SSRC_Msk) | (u32SyncSrc) | (u32ChannelMask)) + +/** + * @brief Disable timer synchronous start counting function of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * @details This macro is used to disable timer synchronous start counting function of specified channel(s). + * \hideinitializer + */ +#define EPWM_DISABLE_TIMER_SYNC(epwm, u32ChannelMask) \ + do{ \ + int i;\ + for(i = 0; i < 6; i++) { \ + if((u32ChannelMask) & (1 << i)) \ + (epwm)->SSCTL &= ~(1UL << i); \ + } \ + }while(0) + +/** + * @brief This macro enable EPWM counter synchronous start counting function. + * @param[in] epwm The pointer of the specified EPWM module + * @return None + * @details This macro is used to make selected EPWM0 and EPWM1 channel(s) start counting at the same time. + * To configure synchronous start counting channel(s) by EPWM_ENABLE_TIMER_SYNC() and EPWM_DISABLE_TIMER_SYNC(). + * \hideinitializer + */ +#define EPWM_TRIGGER_SYNC_START(epwm) ((epwm)->SSTRG = EPWM_SSTRG_CNTSEN_Msk) + +/** + * @brief This macro enable output inverter of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * @details This macro is used to enable output inverter of specified channel(s). + * \hideinitializer + */ +#define EPWM_ENABLE_OUTPUT_INVERTER(epwm, u32ChannelMask) ((epwm)->POLCTL = (u32ChannelMask)) + +/** + * @brief This macro get captured rising data + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This macro is used to get captured rising data of specified channel. + * \hideinitializer + */ +#define EPWM_GET_CAPTURE_RISING_DATA(epwm, u32ChannelNum) ((epwm)->CAPDAT[(u32ChannelNum)].RCAPDAT) + +/** + * @brief This macro get captured falling data + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This macro is used to get captured falling data of specified channel. + * \hideinitializer + */ +#define EPWM_GET_CAPTURE_FALLING_DATA(epwm, u32ChannelNum) ((epwm)->CAPDAT[(u32ChannelNum)].FCAPDAT) + +/** + * @brief This macro mask output logic to high or low + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32LevelMask Output logic to high or low + * @return None + * @details This macro is used to mask output logic to high or low of specified channel(s). + * @note If u32ChannelMask parameter is 0, then mask function will be disabled. + * \hideinitializer + */ +#define EPWM_MASK_OUTPUT(epwm, u32ChannelMask, u32LevelMask) \ + { \ + (epwm)->MSKEN = (u32ChannelMask); \ + (epwm)->MSK = (u32LevelMask); \ + } + +/** + * @brief This macro set the prescaler of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF + * @return None + * @details This macro is used to set the prescaler of specified channel. + * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, channel 1 will also be affected. + * The clock of EPWM counter is divided by (u32Prescaler + 1). + * \hideinitializer + */ +#define EPWM_SET_PRESCALER(epwm, u32ChannelNum, u32Prescaler) ((epwm)->CLKPSC[(u32ChannelNum) >> 1] = (u32Prescaler)) + +/** + * @brief This macro get the prescaler of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Return Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF + * @details This macro is used to get the prescaler of specified channel. + * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, channel 1 will also be affected. + * The clock of EPWM counter is divided by (u32Prescaler + 1). + * \hideinitializer + */ +#define EPWM_GET_PRESCALER(epwm, u32ChannelNum) ((epwm)->CLKPSC[(u32ChannelNum) >> 1U]) + +/** + * @brief This macro set the comparator of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32CMR Comparator of specified channel. Valid values are between 0~0xFFFF + * @return None + * @details This macro is used to set the comparator of specified channel. + * @note This new setting will take effect on next EPWM period. + * \hideinitializer + */ +#define EPWM_SET_CMR(epwm, u32ChannelNum, u32CMR) ((epwm)->CMPDAT[(u32ChannelNum)]= (u32CMR)) + +/** + * @brief This macro get the comparator of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Return the comparator of specified channel. Valid values are between 0~0xFFFF + * @details This macro is used to get the comparator of specified channel. + * \hideinitializer + */ +#define EPWM_GET_CMR(epwm, u32ChannelNum) ((epwm)->CMPDAT[(u32ChannelNum)]) + +/** + * @brief This macro set the free trigger comparator of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32FTCMR Free trigger comparator of specified channel. Valid values are between 0~0xFFFF + * @return None + * @details This macro is used to set the free trigger comparator of specified channel. + * @note This new setting will take effect on next EPWM period. + * \hideinitializer + */ +#define EPWM_SET_FTCMR(epwm, u32ChannelNum, u32FTCMR) (((epwm)->FTCMPDAT[((u32ChannelNum) >> 1U)]) = (u32FTCMR)) + +/** + * @brief This macro set the period of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF + * @return None + * @details This macro is used to set the period of specified channel. + * @note This new setting will take effect on next EPWM period. + * @note EPWM counter will stop if period length set to 0. + * \hideinitializer + */ +#define EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR) ((epwm)->PERIOD[(u32ChannelNum)] = (u32CNR)) + +/** + * @brief This macro get the period of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Return the period of specified channel. Valid values are between 0~0xFFFF + * @details This macro is used to get the period of specified channel. + * \hideinitializer + */ +#define EPWM_GET_CNR(epwm, u32ChannelNum) ((epwm)->PERIOD[(u32ChannelNum)]) + +/** + * @brief This macro set the EPWM aligned type + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32AlignedType EPWM aligned type, valid values are: + * - \ref EPWM_EDGE_ALIGNED + * - \ref EPWM_CENTER_ALIGNED + * @return None + * @details This macro is used to set the EPWM aligned type of specified channel(s). + * \hideinitializer + */ +#define EPWM_SET_ALIGNED_TYPE(epwm, u32ChannelMask, u32AlignedType) \ + do{ \ + int i; \ + for(i = 0; i < 6; i++) { \ + if((u32ChannelMask) & (1 << i)) \ + (epwm)->CTL1 = (((epwm)->CTL1 & ~(3UL << (i << 1))) | ((u32AlignedType) << (i << 1))); \ + } \ + }while(0) + +/** + * @brief Set load window of window loading mode for specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * @details This macro is used to set load window of window loading mode for specified channel(s). + * \hideinitializer + */ +#define EPWM_SET_LOAD_WINDOW(epwm, u32ChannelMask) ((epwm)->LOAD |= (u32ChannelMask)) + +/** + * @brief Trigger synchronous event from specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are 0, 2, 4 + * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4 + * @return None + * @details This macro is used to trigger synchronous event from specified channel(s). + * \hideinitializer + */ +#define EPWM_TRIGGER_SYNC(epwm, u32ChannelNum) ((epwm)->SWSYNC |= (1 << ((u32ChannelNum) >> 1))) + +/** + * @brief Clear counter of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * @details This macro is used to clear counter of specified channel(s). + * \hideinitializer + */ +#define EPWM_CLR_COUNTER(epwm, u32ChannelMask) ((epwm)->CNTCLR |= (u32ChannelMask)) + +/** + * @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32ZeroLevel output level at zero point, valid values are: + * - \ref EPWM_OUTPUT_NOTHING + * - \ref EPWM_OUTPUT_LOW + * - \ref EPWM_OUTPUT_HIGH + * - \ref EPWM_OUTPUT_TOGGLE + * @param[in] u32CmpUpLevel output level at compare up point, valid values are: + * - \ref EPWM_OUTPUT_NOTHING + * - \ref EPWM_OUTPUT_LOW + * - \ref EPWM_OUTPUT_HIGH + * - \ref EPWM_OUTPUT_TOGGLE + * @param[in] u32PeriodLevel output level at period(center) point, valid values are: + * - \ref EPWM_OUTPUT_NOTHING + * - \ref EPWM_OUTPUT_LOW + * - \ref EPWM_OUTPUT_HIGH + * - \ref EPWM_OUTPUT_TOGGLE + * @param[in] u32CmpDownLevel output level at compare down point, valid values are: + * - \ref EPWM_OUTPUT_NOTHING + * - \ref EPWM_OUTPUT_LOW + * - \ref EPWM_OUTPUT_HIGH + * - \ref EPWM_OUTPUT_TOGGLE + * @return None + * @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s). + * \hideinitializer + */ +#define EPWM_SET_OUTPUT_LEVEL(epwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \ + do{ \ + int i; \ + for(i = 0; i < 6; i++) { \ + if((u32ChannelMask) & (1 << i)) { \ + (epwm)->WGCTL0 = (((epwm)->WGCTL0 & ~(3UL << (i << 1))) | ((u32ZeroLevel) << (i << 1))); \ + (epwm)->WGCTL0 = (((epwm)->WGCTL0 & ~(3UL << (EPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))) | ((u32PeriodLevel) << (EPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))); \ + (epwm)->WGCTL1 = (((epwm)->WGCTL1 & ~(3UL << (i << 1))) | ((u32CmpUpLevel) << (i << 1))); \ + (epwm)->WGCTL1 = (((epwm)->WGCTL1 & ~(3UL << (EPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))) | ((u32CmpDownLevel) << (EPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))); \ + } \ + } \ + }while(0) + +/** + * @brief Trigger brake event from specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4 + * @param[in] u32BrakeType Type of brake trigger. + * - \ref EPWM_FB_EDGE + * - \ref EPWM_FB_LEVEL + * @return None + * @details This macro is used to trigger brake event from specified channel(s). + * \hideinitializer + */ +#define EPWM_TRIGGER_BRAKE(epwm, u32ChannelMask, u32BrakeType) ((epwm)->SWBRK |= ((u32ChannelMask) << (u32BrakeType))) + +/** + * @brief Set Dead zone clock source + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32AfterPrescaler Dead zone clock source is from prescaler output. Valid values are TRUE (after prescaler) or FALSE (before prescaler). + * @return None + * @details This macro is used to set Dead zone clock source. Every two channels share the same setting. + * @note The write-protection function should be disabled before using this function. + * \hideinitializer + */ +#define EPWM_SET_DEADZONE_CLK_SRC(epwm, u32ChannelNum, u32AfterPrescaler) \ + ((epwm)->DTCTL[(u32ChannelNum) >> 1] = (((epwm)->DTCTL[(u32ChannelNum) >> 1] & ~EPWM_DTCTL0_1_DTCKSEL_Msk) | \ + ((u32AfterPrescaler) << EPWM_DTCTL0_1_DTCKSEL_Pos))) + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define EPWM functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge); +uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle); +void EPWM_Start(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_Stop(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_ForceStop(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_EnableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); +void EPWM_DisableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum); +int32_t EPWM_EnableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Prescale, uint32_t u32PrescaleCnt); +void EPWM_DisableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); +uint32_t EPWM_GetADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); +void EPWM_DisableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); +uint32_t EPWM_GetDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultBrake(EPWM_T *epwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource); +void EPWM_EnableCapture(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_DisableCapture(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_EnableOutput(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_DisableOutput(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_EnablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode); +void EPWM_DisablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Duration); +void EPWM_DisableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge); +void EPWM_DisableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge); +void EPWM_ClearCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge); +uint32_t EPWM_GetCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType); +void EPWM_DisableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource); +void EPWM_DisableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource); +void EPWM_ClearFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource); +uint32_t EPWM_GetFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource); +void EPWM_EnablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType); +void EPWM_DisablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableAcc(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc); +void EPWM_DisableAcc(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); +void EPWM_DisableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); +void EPWM_ConfigSyncPhase(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase); +void EPWM_EnableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_DisableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_EnableSyncNoiseFilter(EPWM_T *epwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel); +void EPWM_DisableSyncNoiseFilter(EPWM_T *epwm); +void EPWM_EnableSyncPinInverse(EPWM_T *epwm); +void EPWM_DisableSyncPinInverse(EPWM_T *epwm); +void EPWM_SetClockSource(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel); +void EPWM_EnableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel); +void EPWM_DisableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum); +void EPWM_EnableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum); +void EPWM_DisableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum); +void EPWM_SetBrakePinSource(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule); +void EPWM_SetLeadingEdgeBlanking(EPWM_T *epwm, uint32_t u32TrigSrcSel, uint32_t u32TrigType, uint32_t u32BlankingCnt, uint32_t u32BlankingEnable); +uint32_t EPWM_GetWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultDetect(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32AfterPrescaler, uint32_t u32ClkSel); +void EPWM_DisableFaultDetect(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultDetectOutput(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableFaultDetectOutput(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultDetectDeglitch(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32DeglitchSmpCycle); +void EPWM_DisableFaultDetectDeglitch(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultDetectMask(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32MaskCnt); +void EPWM_DisableFaultDetectMask(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum); + +/*@}*/ /* end of group EPWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EPWM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_EPWM_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_fmc.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_fmc.h new file mode 100644 index 0000000000000000000000000000000000000000..d2aa0e96bdc106aae671de54714b2338d2ecbf7d --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_fmc.h @@ -0,0 +1,302 @@ +/**************************************************************************//** + * @file nu_fmc.h + * @version V1.00 + * @brief M480 Series Flash Memory Controller Driver Header File + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __NU_FMC_H__ +#define __NU_FMC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup FMC_Driver FMC Driver + @{ +*/ + + +/** @addtogroup FMC_EXPORTED_CONSTANTS FMC Exported Constants + @{ +*/ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Base Address */ +/*---------------------------------------------------------------------------------------------------------*/ +#define FMC_APROM_BASE 0x00000000UL /*!< APROM base address \hideinitializer */ +#define FMC_APROM_END 0x00080000UL /*!< APROM end address \hideinitializer */ +#define FMC_APROM_BANK0_END (FMC_APROM_END/2UL) /*!< APROM bank0 end address \hideinitializer */ +#define FMC_LDROM_BASE 0x00100000UL /*!< LDROM base address \hideinitializer */ +#define FMC_LDROM_END 0x00101000UL /*!< LDROM end address \hideinitializer */ +#define FMC_SPROM_BASE 0x00200000UL /*!< SPROM base address \hideinitializer */ +#define FMC_SPROM_END 0x00201000UL /*!< SPROM end address \hideinitializer */ +#define FMC_XOM_BASE 0x00200000UL /*!< XOM Base Address \hideinitializer */ +#define FMC_XOMR0_BASE 0x00200000UL /*!< XOMR 0 Base Address \hideinitializer */ +#define FMC_XOMR1_BASE 0x00200010UL /*!< XOMR 1 Base Address \hideinitializer */ +#define FMC_XOMR2_BASE 0x00200020UL /*!< XOMR 2 Base Address \hideinitializer */ +#define FMC_XOMR3_BASE 0x00200030UL /*!< XOMR 3 Base Address \hideinitializer */ +#define FMC_CONFIG_BASE 0x00300000UL /*!< User Configuration address \hideinitializer */ +#define FMC_USER_CONFIG_0 0x00300000UL /*!< User Config 0 address \hideinitializer */ +#define FMC_USER_CONFIG_1 0x00300004UL /*!< User Config 1 address \hideinitializer */ +#define FMC_USER_CONFIG_2 0x00300008UL /*!< User Config 2 address \hideinitializer */ +#define FMC_KPROM_BASE 0x00301000UL /*!< Security ROM base address \hideinitializer */ +#define FMC_OTP_BASE 0x00310000UL /*!< OTP flash base address \hideinitializer */ + +#define FMC_FLASH_PAGE_SIZE 0x1000UL /*!< Flash Page Size (4K bytes) \hideinitializer */ +#define FMC_PAGE_ADDR_MASK 0xFFFFF000UL /*!< Flash page address mask \hideinitializer */ +#define FMC_MULTI_WORD_PROG_LEN 512 /*!< The maximum length of a multi-word program. */ + +#define FMC_APROM_SIZE FMC_APROM_END /*!< APROM Size \hideinitializer */ +#define FMC_BANK_SIZE (FMC_APROM_SIZE/2UL) /*!< APROM Bank Size \hideinitializer */ +#define FMC_LDROM_SIZE 0x1000UL /*!< LDROM Size (4 Kbytes) \hideinitializer */ +#define FMC_SPROM_SIZE 0x1000UL /*!< SPROM Size (4 Kbytes) \hideinitializer */ +#define FMC_OTP_ENTRY_CNT 256UL /*!< OTP entry number \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* XOM region number constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define XOMR0 0UL /*!< XOM region 0 */ +#define XOMR1 1UL /*!< XOM region 1 */ +#define XOMR2 2UL /*!< XOM region 2 */ +#define XOMR3 3UL /*!< XOM region 3 */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* ISPCTL constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define IS_BOOT_FROM_LDROM 0x1UL /*!< ISPCTL setting to select to boot from LDROM */ +#define IS_BOOT_FROM_APROM 0x0UL /*!< ISPCTL setting to select to boot from APROM */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* ISPCMD constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define FMC_ISPCMD_READ 0x00UL /*!< ISP Command: Read flash word \hideinitializer */ +#define FMC_ISPCMD_READ_UID 0x04UL /*!< ISP Command: Read Unique ID \hideinitializer */ +#define FMC_ISPCMD_READ_ALL1 0x08UL /*!< ISP Command: Read all-one result \hideinitializer */ +#define FMC_ISPCMD_READ_CID 0x0BUL /*!< ISP Command: Read Company ID \hideinitializer */ +#define FMC_ISPCMD_READ_DID 0x0CUL /*!< ISP Command: Read Device ID \hideinitializer */ +#define FMC_ISPCMD_READ_CKS 0x0DUL /*!< ISP Command: Read checksum \hideinitializer */ +#define FMC_ISPCMD_PROGRAM 0x21UL /*!< ISP Command: Write flash word \hideinitializer */ +#define FMC_ISPCMD_PAGE_ERASE 0x22UL /*!< ISP Command: Page Erase Flash \hideinitializer */ +#define FMC_ISPCMD_BANK_ERASE 0x23UL /*!< ISP Command: Erase Flash bank 0 or 1 \hideinitializer */ +#define FMC_ISPCMD_BLOCK_ERASE 0x25UL /*!< ISP Command: Erase 4 pages alignment of APROM in bank 0 or 1 \hideinitializer */ +#define FMC_ISPCMD_PROGRAM_MUL 0x27UL /*!< ISP Command: Multuple word program \hideinitializer */ +#define FMC_ISPCMD_RUN_ALL1 0x28UL /*!< ISP Command: Run all-one verification \hideinitializer */ +#define FMC_ISPCMD_RUN_CKS 0x2DUL /*!< ISP Command: Run checksum calculation \hideinitializer */ +#define FMC_ISPCMD_VECMAP 0x2EUL /*!< ISP Command: Vector Page Remap \hideinitializer */ +#define FMC_ISPCMD_READ_64 0x40UL /*!< ISP Command: Read double flash word \hideinitializer */ +#define FMC_ISPCMD_PROGRAM_64 0x61UL /*!< ISP Command: Write double flash word \hideinitializer */ + +#define READ_ALLONE_YES 0xA11FFFFFUL /*!< Check-all-one result is all one. \hideinitializer */ +#define READ_ALLONE_NOT 0xA1100000UL /*!< Check-all-one result is not all one. \hideinitializer */ +#define READ_ALLONE_CMD_FAIL 0xFFFFFFFFUL /*!< Check-all-one command failed. \hideinitializer */ + + +/*@}*/ /* end of group FMC_EXPORTED_CONSTANTS */ + + +/** @addtogroup FMC_EXPORTED_MACROS FMC Exported Macros + @{ +*/ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Macros */ +/*---------------------------------------------------------------------------------------------------------*/ + +#define FMC_SET_APROM_BOOT() (FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk) /*!< Select booting from APROM \hideinitializer */ +#define FMC_SET_LDROM_BOOT() (FMC->ISPCTL |= FMC_ISPCTL_BS_Msk) /*!< Select booting from LDROM \hideinitializer */ +#define FMC_ENABLE_AP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_APUEN_Msk) /*!< Enable APROM update \hideinitializer */ +#define FMC_DISABLE_AP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk) /*!< Disable APROM update \hideinitializer */ +#define FMC_ENABLE_CFG_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_CFGUEN_Msk) /*!< Enable User Config update \hideinitializer */ +#define FMC_DISABLE_CFG_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk) /*!< Disable User Config update \hideinitializer */ +#define FMC_ENABLE_LD_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_LDUEN_Msk) /*!< Enable LDROM update \hideinitializer */ +#define FMC_DISABLE_LD_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk) /*!< Disable LDROM update \hideinitializer */ +#define FMC_ENABLE_SP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_SPUEN_Msk) /*!< Enable SPROM update \hideinitializer */ +#define FMC_DISABLE_SP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_SPUEN_Msk) /*!< Disable SPROM update \hideinitializer */ +#define FMC_DISABLE_ISP() (FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk) /*!< Disable ISP function \hideinitializer */ +#define FMC_ENABLE_ISP() (FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk) /*!< Enable ISP function \hideinitializer */ +#define FMC_GET_FAIL_FLAG() ((FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) ? 1UL : 0UL) /*!< Get ISP fail flag \hideinitializer */ +#define FMC_CLR_FAIL_FLAG() (FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk) /*!< Clear ISP fail flag \hideinitializer */ + +/*@}*/ /* end of group FMC_EXPORTED_MACROS */ + + +/** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ + +__STATIC_INLINE uint32_t FMC_ReadCID(void); +__STATIC_INLINE uint32_t FMC_ReadPID(void); +__STATIC_INLINE uint32_t FMC_ReadUID(uint8_t u8Index); +__STATIC_INLINE uint32_t FMC_ReadUCID(uint32_t u32Index); +__STATIC_INLINE void FMC_SetVectorPageAddr(uint32_t u32PageAddr); +__STATIC_INLINE uint32_t FMC_GetVECMAP(void); + +/** + * @brief Get current vector mapping address. + * @param None + * @return The current vector mapping address. + * @details To get VECMAP value which is the page address for remapping to vector page (0x0). + * @note + * VECMAP only valid when new IAP function is enabled. (CBS = 10'b or 00'b) + */ +__STATIC_INLINE uint32_t FMC_GetVECMAP(void) +{ + return (FMC->ISPSTS & FMC_ISPSTS_VECMAP_Msk); +} + +/** + * @brief Read company ID + * @param None + * @return The company ID (32-bit) + * @details The company ID of Nuvoton is fixed to be 0xDA + */ +__STATIC_INLINE uint32_t FMC_ReadCID(void) +{ + FMC->ISPCMD = FMC_ISPCMD_READ_CID; /* Set ISP Command Code */ + FMC->ISPADDR = 0x0u; /* Must keep 0x0 when read CID */ + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */ +#if ISBEN + __ISB(); +#endif /* To make sure ISP/CPU be Synchronized */ + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */ + + return FMC->ISPDAT; +} + +/** + * @brief Read product ID + * @param None + * @return The product ID (32-bit) + * @details This function is used to read product ID. + */ +__STATIC_INLINE uint32_t FMC_ReadPID(void) +{ + FMC->ISPCMD = FMC_ISPCMD_READ_DID; /* Set ISP Command Code */ + FMC->ISPADDR = 0x04u; /* Must keep 0x4 when read PID */ + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */ +#if ISBEN + __ISB(); +#endif /* To make sure ISP/CPU be Synchronized */ + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */ + + return FMC->ISPDAT; +} + +/** + * @brief Read Unique ID + * @param[in] u8Index UID index. 0 = UID[31:0], 1 = UID[63:32], 2 = UID[95:64] + * @return The 32-bit unique ID data of specified UID index. + * @details To read out 96-bit Unique ID. + */ +__STATIC_INLINE uint32_t FMC_ReadUID(uint8_t u8Index) +{ + FMC->ISPCMD = FMC_ISPCMD_READ_UID; + FMC->ISPADDR = ((uint32_t)u8Index << 2u); + FMC->ISPDAT = 0u; + FMC->ISPTRG = 0x1u; +#if ISBEN + __ISB(); +#endif + while(FMC->ISPTRG) {} + + return FMC->ISPDAT; +} + +/** + * @brief To read UCID + * @param[in] u32Index Index of the UCID to read. u32Index must be 0, 1, 2, or 3. + * @return The UCID of specified index + * @details This function is used to read unique chip ID (UCID). + */ +__STATIC_INLINE uint32_t FMC_ReadUCID(uint32_t u32Index) +{ + FMC->ISPCMD = FMC_ISPCMD_READ_UID; /* Set ISP Command Code */ + FMC->ISPADDR = (0x04u * u32Index) + 0x10u; /* The UCID is at offset 0x10 with word alignment. */ + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */ +#if ISBEN + __ISB(); +#endif /* To make sure ISP/CPU be Synchronized */ + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */ + + return FMC->ISPDAT; +} + +/** + * @brief Set vector mapping address + * @param[in] u32PageAddr The page address to remap to address 0x0. The address must be page alignment. + * @return To set VECMAP to remap specified page address to 0x0. + * @details This function is used to set VECMAP to map specified page to vector page (0x0). + * @note + * VECMAP only valid when new IAP function is enabled. (CBS = 10'b or 00'b) + */ +__STATIC_INLINE void FMC_SetVectorPageAddr(uint32_t u32PageAddr) +{ + FMC->ISPCMD = FMC_ISPCMD_VECMAP; /* Set ISP Command Code */ + FMC->ISPADDR = u32PageAddr; /* The address of specified page which will be map to address 0x0. It must be page alignment. */ + FMC->ISPTRG = 0x1u; /* Trigger to start ISP procedure */ +#if ISBEN + __ISB(); +#endif /* To make sure ISP/CPU be Synchronized */ + while(FMC->ISPTRG) {} /* Waiting for ISP Done */ +} + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Functions */ +/*---------------------------------------------------------------------------------------------------------*/ + +extern void FMC_Close(void); +extern int32_t FMC_ConfigXOM(uint32_t xom_num, uint32_t xom_base, uint8_t xom_page); +extern int32_t FMC_Erase(uint32_t u32PageAddr); +extern int32_t FMC_Erase_SPROM(void); +extern int32_t FMC_Erase_Block(uint32_t u32BlockAddr); +extern int32_t FMC_Erase_Bank(uint32_t u32BankAddr); +extern int32_t FMC_EraseXOM(uint32_t xom_num); +extern int32_t FMC_GetXOMState(uint32_t xom_num); +extern int32_t FMC_GetBootSource(void); +extern void FMC_Open(void); +extern uint32_t FMC_Read(uint32_t u32Addr); +extern int32_t FMC_Read_64(uint32_t u32addr, uint32_t * u32data0, uint32_t * u32data1); +extern uint32_t FMC_ReadDataFlashBaseAddr(void); +extern void FMC_SetBootSource(int32_t i32BootSrc); +extern void FMC_Write(uint32_t u32Addr, uint32_t u32Data); +extern int32_t FMC_Write8Bytes(uint32_t u32addr, uint32_t u32data0, uint32_t u32data1); +extern int32_t FMC_WriteMultiple(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len); +extern int32_t FMC_Write_OTP(uint32_t otp_num, uint32_t low_word, uint32_t high_word); +extern int32_t FMC_Read_OTP(uint32_t otp_num, uint32_t *low_word, uint32_t *high_word); +extern int32_t FMC_Lock_OTP(uint32_t otp_num); +extern int32_t FMC_Is_OTP_Locked(uint32_t otp_num); +extern int32_t FMC_ReadConfig(uint32_t u32Config[], uint32_t u32Count); +extern int32_t FMC_WriteConfig(uint32_t u32Config[], uint32_t u32Count); +extern uint32_t FMC_GetChkSum(uint32_t u32addr, uint32_t u32count); +extern uint32_t FMC_CheckAllOne(uint32_t u32addr, uint32_t u32count); +extern int32_t FMC_SetSPKey(uint32_t key[3], uint32_t kpmax, uint32_t kemax, const int32_t lock_CONFIG, const int32_t lock_SPROM); +extern int32_t FMC_CompareSPKey(uint32_t key[3]); + + +/*@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group FMC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_FMC_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_gpio.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..08ce10ce59e444923c01d67e3bff625e078a7e93 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_gpio.h @@ -0,0 +1,497 @@ +/**************************************************************************//** + * @file GPIO.h + * @version V3.00 + * @brief M480 series GPIO driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __NU_GPIO_H__ +#define __NU_GPIO_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup GPIO_Driver GPIO Driver + @{ +*/ + +/** @addtogroup GPIO_EXPORTED_CONSTANTS GPIO Exported Constants + @{ +*/ + + +#define GPIO_PIN_MAX 16UL /*!< Specify Maximum Pins of Each GPIO Port \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO_MODE Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_MODE_INPUT 0x0UL /*!< Input Mode \hideinitializer */ +#define GPIO_MODE_OUTPUT 0x1UL /*!< Output Mode \hideinitializer */ +#define GPIO_MODE_OPEN_DRAIN 0x2UL /*!< Open-Drain Mode \hideinitializer */ +#define GPIO_MODE_QUASI 0x3UL /*!< Quasi-bidirectional Mode \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO Interrupt Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_INT_RISING 0x00010000UL /*!< Interrupt enable by Input Rising Edge \hideinitializer */ +#define GPIO_INT_FALLING 0x00000001UL /*!< Interrupt enable by Input Falling Edge \hideinitializer */ +#define GPIO_INT_BOTH_EDGE 0x00010001UL /*!< Interrupt enable by both Rising Edge and Falling Edge \hideinitializer */ +#define GPIO_INT_HIGH 0x01010000UL /*!< Interrupt enable by Level-High \hideinitializer */ +#define GPIO_INT_LOW 0x01000001UL /*!< Interrupt enable by Level-Level \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO_INTTYPE Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_INTTYPE_EDGE 0UL /*!< GPIO_INTTYPE Setting for Edge Trigger Mode \hideinitializer */ +#define GPIO_INTTYPE_LEVEL 1UL /*!< GPIO_INTTYPE Setting for Edge Level Mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO Slew Rate Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_SLEWCTL_NORMAL 0x0UL /*!< GPIO slew setting for normal Mode \hideinitializer */ +#define GPIO_SLEWCTL_HIGH 0x1UL /*!< GPIO slew setting for high Mode \hideinitializer */ +#define GPIO_SLEWCTL_FAST 0x2UL /*!< GPIO slew setting for fast Mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO Pull-up And Pull-down Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_PUSEL_DISABLE 0x0UL /*!< GPIO PUSEL setting for Disable Mode \hideinitializer */ +#define GPIO_PUSEL_PULL_UP 0x1UL /*!< GPIO PUSEL setting for Pull-up Mode \hideinitializer */ +#define GPIO_PUSEL_PULL_DOWN 0x2UL /*!< GPIO PUSEL setting for Pull-down Mode \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO_DBCTL Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_DBCTL_ICLK_ON 0x00000020UL /*!< GPIO_DBCTL setting for all IO pins edge detection circuit is always active after reset \hideinitializer */ +#define GPIO_DBCTL_ICLK_OFF 0x00000000UL /*!< GPIO_DBCTL setting for edge detection circuit is active only if IO pin corresponding GPIOx_IEN bit is set to 1 \hideinitializer */ + +#define GPIO_DBCTL_DBCLKSRC_LIRC 0x00000010UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the internal 10 kHz \hideinitializer */ +#define GPIO_DBCTL_DBCLKSRC_HCLK 0x00000000UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the HCLK \hideinitializer */ + +#define GPIO_DBCTL_DBCLKSEL_1 0x00000000UL /*!< GPIO_DBCTL setting for sampling cycle = 1 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_2 0x00000001UL /*!< GPIO_DBCTL setting for sampling cycle = 2 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_4 0x00000002UL /*!< GPIO_DBCTL setting for sampling cycle = 4 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_8 0x00000003UL /*!< GPIO_DBCTL setting for sampling cycle = 8 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_16 0x00000004UL /*!< GPIO_DBCTL setting for sampling cycle = 16 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_32 0x00000005UL /*!< GPIO_DBCTL setting for sampling cycle = 32 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_64 0x00000006UL /*!< GPIO_DBCTL setting for sampling cycle = 64 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_128 0x00000007UL /*!< GPIO_DBCTL setting for sampling cycle = 128 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_256 0x00000008UL /*!< GPIO_DBCTL setting for sampling cycle = 256 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_512 0x00000009UL /*!< GPIO_DBCTL setting for sampling cycle = 512 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_1024 0x0000000AUL /*!< GPIO_DBCTL setting for sampling cycle = 1024 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_2048 0x0000000BUL /*!< GPIO_DBCTL setting for sampling cycle = 2048 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_4096 0x0000000CUL /*!< GPIO_DBCTL setting for sampling cycle = 4096 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_8192 0x0000000DUL /*!< GPIO_DBCTL setting for sampling cycle = 8192 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_16384 0x0000000EUL /*!< GPIO_DBCTL setting for sampling cycle = 16384 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_32768 0x0000000FUL /*!< GPIO_DBCTL setting for sampling cycle = 32768 clocks \hideinitializer */ + + +/* Define GPIO Pin Data Input/Output. It could be used to control each I/O pin by pin address mapping. + Example 1: + + PA0 = 1; + + It is used to set GPIO PA.0 to high; + + Example 2: + + if (PA0) + PA0 = 0; + + If GPIO PA.0 pin status is high, then set GPIO PA.0 data output to low. + */ +#define GPIO_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2)))) /*!< Pin Data Input/Output \hideinitializer */ +#define PA0 GPIO_PIN_DATA(0, 0 ) /*!< Specify PA.0 Pin Data Input/Output \hideinitializer */ +#define PA1 GPIO_PIN_DATA(0, 1 ) /*!< Specify PA.1 Pin Data Input/Output \hideinitializer */ +#define PA2 GPIO_PIN_DATA(0, 2 ) /*!< Specify PA.2 Pin Data Input/Output \hideinitializer */ +#define PA3 GPIO_PIN_DATA(0, 3 ) /*!< Specify PA.3 Pin Data Input/Output \hideinitializer */ +#define PA4 GPIO_PIN_DATA(0, 4 ) /*!< Specify PA.4 Pin Data Input/Output \hideinitializer */ +#define PA5 GPIO_PIN_DATA(0, 5 ) /*!< Specify PA.5 Pin Data Input/Output \hideinitializer */ +#define PA6 GPIO_PIN_DATA(0, 6 ) /*!< Specify PA.6 Pin Data Input/Output \hideinitializer */ +#define PA7 GPIO_PIN_DATA(0, 7 ) /*!< Specify PA.7 Pin Data Input/Output \hideinitializer */ +#define PA8 GPIO_PIN_DATA(0, 8 ) /*!< Specify PA.8 Pin Data Input/Output \hideinitializer */ +#define PA9 GPIO_PIN_DATA(0, 9 ) /*!< Specify PA.9 Pin Data Input/Output \hideinitializer */ +#define PA10 GPIO_PIN_DATA(0, 10) /*!< Specify PA.10 Pin Data Input/Output \hideinitializer */ +#define PA11 GPIO_PIN_DATA(0, 11) /*!< Specify PA.11 Pin Data Input/Output \hideinitializer */ +#define PA12 GPIO_PIN_DATA(0, 12) /*!< Specify PA.12 Pin Data Input/Output \hideinitializer */ +#define PA13 GPIO_PIN_DATA(0, 13) /*!< Specify PA.13 Pin Data Input/Output \hideinitializer */ +#define PA14 GPIO_PIN_DATA(0, 14) /*!< Specify PA.14 Pin Data Input/Output \hideinitializer */ +#define PA15 GPIO_PIN_DATA(0, 15) /*!< Specify PA.15 Pin Data Input/Output \hideinitializer */ +#define PB0 GPIO_PIN_DATA(1, 0 ) /*!< Specify PB.0 Pin Data Input/Output \hideinitializer */ +#define PB1 GPIO_PIN_DATA(1, 1 ) /*!< Specify PB.1 Pin Data Input/Output \hideinitializer */ +#define PB2 GPIO_PIN_DATA(1, 2 ) /*!< Specify PB.2 Pin Data Input/Output \hideinitializer */ +#define PB3 GPIO_PIN_DATA(1, 3 ) /*!< Specify PB.3 Pin Data Input/Output \hideinitializer */ +#define PB4 GPIO_PIN_DATA(1, 4 ) /*!< Specify PB.4 Pin Data Input/Output \hideinitializer */ +#define PB5 GPIO_PIN_DATA(1, 5 ) /*!< Specify PB.5 Pin Data Input/Output \hideinitializer */ +#define PB6 GPIO_PIN_DATA(1, 6 ) /*!< Specify PB.6 Pin Data Input/Output \hideinitializer */ +#define PB7 GPIO_PIN_DATA(1, 7 ) /*!< Specify PB.7 Pin Data Input/Output \hideinitializer */ +#define PB8 GPIO_PIN_DATA(1, 8 ) /*!< Specify PB.8 Pin Data Input/Output \hideinitializer */ +#define PB9 GPIO_PIN_DATA(1, 9 ) /*!< Specify PB.9 Pin Data Input/Output \hideinitializer */ +#define PB10 GPIO_PIN_DATA(1, 10) /*!< Specify PB.10 Pin Data Input/Output \hideinitializer */ +#define PB11 GPIO_PIN_DATA(1, 11) /*!< Specify PB.11 Pin Data Input/Output \hideinitializer */ +#define PB12 GPIO_PIN_DATA(1, 12) /*!< Specify PB.12 Pin Data Input/Output \hideinitializer */ +#define PB13 GPIO_PIN_DATA(1, 13) /*!< Specify PB.13 Pin Data Input/Output \hideinitializer */ +#define PB14 GPIO_PIN_DATA(1, 14) /*!< Specify PB.14 Pin Data Input/Output \hideinitializer */ +#define PB15 GPIO_PIN_DATA(1, 15) /*!< Specify PB.15 Pin Data Input/Output \hideinitializer */ +#define PC0 GPIO_PIN_DATA(2, 0 ) /*!< Specify PC.0 Pin Data Input/Output \hideinitializer */ +#define PC1 GPIO_PIN_DATA(2, 1 ) /*!< Specify PC.1 Pin Data Input/Output \hideinitializer */ +#define PC2 GPIO_PIN_DATA(2, 2 ) /*!< Specify PC.2 Pin Data Input/Output \hideinitializer */ +#define PC3 GPIO_PIN_DATA(2, 3 ) /*!< Specify PC.3 Pin Data Input/Output \hideinitializer */ +#define PC4 GPIO_PIN_DATA(2, 4 ) /*!< Specify PC.4 Pin Data Input/Output \hideinitializer */ +#define PC5 GPIO_PIN_DATA(2, 5 ) /*!< Specify PC.5 Pin Data Input/Output \hideinitializer */ +#define PC6 GPIO_PIN_DATA(2, 6 ) /*!< Specify PC.6 Pin Data Input/Output \hideinitializer */ +#define PC7 GPIO_PIN_DATA(2, 7 ) /*!< Specify PC.7 Pin Data Input/Output \hideinitializer */ +#define PC8 GPIO_PIN_DATA(2, 8 ) /*!< Specify PC.8 Pin Data Input/Output \hideinitializer */ +#define PC9 GPIO_PIN_DATA(2, 9 ) /*!< Specify PC.9 Pin Data Input/Output \hideinitializer */ +#define PC10 GPIO_PIN_DATA(2, 10) /*!< Specify PC.10 Pin Data Input/Output \hideinitializer */ +#define PC11 GPIO_PIN_DATA(2, 11) /*!< Specify PC.11 Pin Data Input/Output \hideinitializer */ +#define PC12 GPIO_PIN_DATA(2, 12) /*!< Specify PC.12 Pin Data Input/Output \hideinitializer */ +#define PC13 GPIO_PIN_DATA(2, 13) /*!< Specify PC.13 Pin Data Input/Output \hideinitializer */ +#define PC14 GPIO_PIN_DATA(2, 14) /*!< Specify PC.14 Pin Data Input/Output \hideinitializer */ +#define PD0 GPIO_PIN_DATA(3, 0 ) /*!< Specify PD.0 Pin Data Input/Output \hideinitializer */ +#define PD1 GPIO_PIN_DATA(3, 1 ) /*!< Specify PD.1 Pin Data Input/Output \hideinitializer */ +#define PD2 GPIO_PIN_DATA(3, 2 ) /*!< Specify PD.2 Pin Data Input/Output \hideinitializer */ +#define PD3 GPIO_PIN_DATA(3, 3 ) /*!< Specify PD.3 Pin Data Input/Output \hideinitializer */ +#define PD4 GPIO_PIN_DATA(3, 4 ) /*!< Specify PD.4 Pin Data Input/Output \hideinitializer */ +#define PD5 GPIO_PIN_DATA(3, 5 ) /*!< Specify PD.5 Pin Data Input/Output \hideinitializer */ +#define PD6 GPIO_PIN_DATA(3, 6 ) /*!< Specify PD.6 Pin Data Input/Output \hideinitializer */ +#define PD7 GPIO_PIN_DATA(3, 7 ) /*!< Specify PD.7 Pin Data Input/Output \hideinitializer */ +#define PD8 GPIO_PIN_DATA(3, 8 ) /*!< Specify PD.8 Pin Data Input/Output \hideinitializer */ +#define PD9 GPIO_PIN_DATA(3, 9 ) /*!< Specify PD.9 Pin Data Input/Output \hideinitializer */ +#define PD10 GPIO_PIN_DATA(3, 10) /*!< Specify PD.10 Pin Data Input/Output \hideinitializer */ +#define PD11 GPIO_PIN_DATA(3, 11) /*!< Specify PD.11 Pin Data Input/Output \hideinitializer */ +#define PD12 GPIO_PIN_DATA(3, 12) /*!< Specify PD.12 Pin Data Input/Output \hideinitializer */ +#define PD13 GPIO_PIN_DATA(3, 13) /*!< Specify PD.13 Pin Data Input/Output \hideinitializer */ +#define PD14 GPIO_PIN_DATA(3, 14) /*!< Specify PD.14 Pin Data Input/Output \hideinitializer */ +#define PE0 GPIO_PIN_DATA(4, 0 ) /*!< Specify PE.0 Pin Data Input/Output \hideinitializer */ +#define PE1 GPIO_PIN_DATA(4, 1 ) /*!< Specify PE.1 Pin Data Input/Output \hideinitializer */ +#define PE2 GPIO_PIN_DATA(4, 2 ) /*!< Specify PE.2 Pin Data Input/Output \hideinitializer */ +#define PE3 GPIO_PIN_DATA(4, 3 ) /*!< Specify PE.3 Pin Data Input/Output \hideinitializer */ +#define PE4 GPIO_PIN_DATA(4, 4 ) /*!< Specify PE.4 Pin Data Input/Output \hideinitializer */ +#define PE5 GPIO_PIN_DATA(4, 5 ) /*!< Specify PE.5 Pin Data Input/Output \hideinitializer */ +#define PE6 GPIO_PIN_DATA(4, 6 ) /*!< Specify PE.6 Pin Data Input/Output \hideinitializer */ +#define PE7 GPIO_PIN_DATA(4, 7 ) /*!< Specify PE.7 Pin Data Input/Output \hideinitializer */ +#define PE8 GPIO_PIN_DATA(4, 8 ) /*!< Specify PE.8 Pin Data Input/Output \hideinitializer */ +#define PE9 GPIO_PIN_DATA(4, 9 ) /*!< Specify PE.9 Pin Data Input/Output \hideinitializer */ +#define PE10 GPIO_PIN_DATA(4, 10) /*!< Specify PE.10 Pin Data Input/Output \hideinitializer */ +#define PE11 GPIO_PIN_DATA(4, 11) /*!< Specify PE.11 Pin Data Input/Output \hideinitializer */ +#define PE12 GPIO_PIN_DATA(4, 12) /*!< Specify PE.12 Pin Data Input/Output \hideinitializer */ +#define PE13 GPIO_PIN_DATA(4, 13) /*!< Specify PE.13 Pin Data Input/Output \hideinitializer */ +#define PE14 GPIO_PIN_DATA(4, 14) /*!< Specify PE.14 Pin Data Input/Output \hideinitializer */ +#define PE15 GPIO_PIN_DATA(4, 15) /*!< Specify PE.15 Pin Data Input/Output \hideinitializer */ +#define PF0 GPIO_PIN_DATA(5, 0 ) /*!< Specify PF.0 Pin Data Input/Output \hideinitializer */ +#define PF1 GPIO_PIN_DATA(5, 1 ) /*!< Specify PF.1 Pin Data Input/Output \hideinitializer */ +#define PF2 GPIO_PIN_DATA(5, 2 ) /*!< Specify PF.2 Pin Data Input/Output \hideinitializer */ +#define PF3 GPIO_PIN_DATA(5, 3 ) /*!< Specify PF.3 Pin Data Input/Output \hideinitializer */ +#define PF4 GPIO_PIN_DATA(5, 4 ) /*!< Specify PF.4 Pin Data Input/Output \hideinitializer */ +#define PF5 GPIO_PIN_DATA(5, 5 ) /*!< Specify PF.5 Pin Data Input/Output \hideinitializer */ +#define PF6 GPIO_PIN_DATA(5, 6 ) /*!< Specify PF.6 Pin Data Input/Output \hideinitializer */ +#define PF7 GPIO_PIN_DATA(5, 7 ) /*!< Specify PF.7 Pin Data Input/Output \hideinitializer */ +#define PF8 GPIO_PIN_DATA(5, 8 ) /*!< Specify PF.8 Pin Data Input/Output \hideinitializer */ +#define PF9 GPIO_PIN_DATA(5, 9 ) /*!< Specify PF.9 Pin Data Input/Output \hideinitializer */ +#define PF10 GPIO_PIN_DATA(5, 10) /*!< Specify PF.10 Pin Data Input/Output \hideinitializer */ +#define PF11 GPIO_PIN_DATA(5, 11) /*!< Specify PF.11 Pin Data Input/Output \hideinitializer */ +#define PG0 GPIO_PIN_DATA(6, 0 ) /*!< Specify PG.0 Pin Data Input/Output \hideinitializer */ +#define PG1 GPIO_PIN_DATA(6, 1 ) /*!< Specify PG.1 Pin Data Input/Output \hideinitializer */ +#define PG2 GPIO_PIN_DATA(6, 2 ) /*!< Specify PG.2 Pin Data Input/Output \hideinitializer */ +#define PG3 GPIO_PIN_DATA(6, 3 ) /*!< Specify PG.3 Pin Data Input/Output \hideinitializer */ +#define PG4 GPIO_PIN_DATA(6, 4 ) /*!< Specify PG.4 Pin Data Input/Output \hideinitializer */ +#define PG5 GPIO_PIN_DATA(6, 5 ) /*!< Specify PG.5 Pin Data Input/Output \hideinitializer */ +#define PG6 GPIO_PIN_DATA(6, 6 ) /*!< Specify PG.6 Pin Data Input/Output \hideinitializer */ +#define PG7 GPIO_PIN_DATA(6, 7 ) /*!< Specify PG.7 Pin Data Input/Output \hideinitializer */ +#define PG8 GPIO_PIN_DATA(6, 8 ) /*!< Specify PG.8 Pin Data Input/Output \hideinitializer */ +#define PG9 GPIO_PIN_DATA(6, 9 ) /*!< Specify PG.9 Pin Data Input/Output \hideinitializer */ +#define PG10 GPIO_PIN_DATA(6, 10) /*!< Specify PG.10 Pin Data Input/Output \hideinitializer */ +#define PG11 GPIO_PIN_DATA(6, 11) /*!< Specify PG.11 Pin Data Input/Output \hideinitializer */ +#define PG12 GPIO_PIN_DATA(6, 12) /*!< Specify PG.12 Pin Data Input/Output \hideinitializer */ +#define PG13 GPIO_PIN_DATA(6, 13) /*!< Specify PG.13 Pin Data Input/Output \hideinitializer */ +#define PG14 GPIO_PIN_DATA(6, 14) /*!< Specify PG.14 Pin Data Input/Output \hideinitializer */ +#define PG15 GPIO_PIN_DATA(6, 15) /*!< Specify PG.15 Pin Data Input/Output \hideinitializer */ +#define PH0 GPIO_PIN_DATA(7, 0 ) /*!< Specify PH.0 Pin Data Input/Output \hideinitializer */ +#define PH1 GPIO_PIN_DATA(7, 1 ) /*!< Specify PH.1 Pin Data Input/Output \hideinitializer */ +#define PH2 GPIO_PIN_DATA(7, 2 ) /*!< Specify PH.2 Pin Data Input/Output \hideinitializer */ +#define PH3 GPIO_PIN_DATA(7, 3 ) /*!< Specify PH.3 Pin Data Input/Output \hideinitializer */ +#define PH4 GPIO_PIN_DATA(7, 4 ) /*!< Specify PH.4 Pin Data Input/Output \hideinitializer */ +#define PH5 GPIO_PIN_DATA(7, 5 ) /*!< Specify PH.5 Pin Data Input/Output \hideinitializer */ +#define PH6 GPIO_PIN_DATA(7, 6 ) /*!< Specify PH.6 Pin Data Input/Output \hideinitializer */ +#define PH7 GPIO_PIN_DATA(7, 7 ) /*!< Specify PH.7 Pin Data Input/Output \hideinitializer */ +#define PH8 GPIO_PIN_DATA(7, 8 ) /*!< Specify PH.8 Pin Data Input/Output \hideinitializer */ +#define PH9 GPIO_PIN_DATA(7, 9 ) /*!< Specify PH.9 Pin Data Input/Output \hideinitializer */ +#define PH10 GPIO_PIN_DATA(7, 10) /*!< Specify PH.10 Pin Data Input/Output \hideinitializer */ +#define PH11 GPIO_PIN_DATA(7, 11) /*!< Specify PH.11 Pin Data Input/Output \hideinitializer */ + + +/*@}*/ /* end of group GPIO_EXPORTED_CONSTANTS */ + + +/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions + @{ +*/ + +/** + * @brief Clear GPIO Pin Interrupt Flag + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be BIT0 ~ BIT13 for PE GPIO port. + * It could be BIT0 ~ BIT11 for PG GPIO port. + * + * @return None + * + * @details Clear the interrupt status of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_CLR_INT_FLAG(port, u32PinMask) ((port)->INTSRC = (u32PinMask)) + +/** + * @brief Disable Pin De-bounce Function + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be BIT0 ~ BIT13 for PE GPIO port. + * It could be BIT0 ~ BIT11 for PG GPIO port. + * + * @return None + * + * @details Disable the interrupt de-bounce function of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_DISABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN &= ~(u32PinMask)) + +/** + * @brief Enable Pin De-bounce Function + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be BIT0 ~ BIT13 for PE GPIO port. + * It could be BIT0 ~ BIT11 for PG GPIO port. + * @return None + * + * @details Enable the interrupt de-bounce function of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_ENABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN |= (u32PinMask)) + +/** + * @brief Disable I/O Digital Input Path + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be BIT0 ~ BIT13 for PE GPIO port. + * It could be BIT0 ~ BIT11 for PG GPIO port. + * + * @return None + * + * @details Disable I/O digital input path of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_DISABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF |= ((u32PinMask)<<16)) + +/** + * @brief Enable I/O Digital Input Path + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be BIT0 ~ BIT13 for PE GPIO port. + * It could be BIT0 ~ BIT11 for PG GPIO port. + * + * @return None + * + * @details Enable I/O digital input path of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_ENABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF &= ~((u32PinMask)<<16)) + +/** + * @brief Disable I/O DOUT mask + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be BIT0 ~ BIT13 for PE GPIO port. + * It could be BIT0 ~ BIT11 for PG GPIO port. + * + * @return None + * + * @details Disable I/O DOUT mask of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_DISABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK &= ~(u32PinMask)) + +/** + * @brief Enable I/O DOUT mask + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be BIT0 ~ BIT13 for PE GPIO port. + * It could be BIT0 ~ BIT11 for PG GPIO port. + * + * @return None + * + * @details Enable I/O DOUT mask of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_ENABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK |= (u32PinMask)) + +/** + * @brief Get GPIO Pin Interrupt Flag + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be BIT0 ~ BIT13 for PE GPIO port. + * It could be BIT0 ~ BIT11 for PG GPIO port. + * + * @retval 0 No interrupt at specified GPIO pin + * @retval 1 The specified GPIO pin generate an interrupt + * + * @details Get the interrupt status of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_GET_INT_FLAG(port, u32PinMask) ((port)->INTSRC & (u32PinMask)) + +/** + * @brief Set De-bounce Sampling Cycle Time + * + * @param[in] u32ClkSrc The de-bounce counter clock source. It could be GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC. + * @param[in] u32ClkSel The de-bounce sampling cycle selection. It could be + * - \ref GPIO_DBCTL_DBCLKSEL_1 + * - \ref GPIO_DBCTL_DBCLKSEL_2 + * - \ref GPIO_DBCTL_DBCLKSEL_4 + * - \ref GPIO_DBCTL_DBCLKSEL_8 + * - \ref GPIO_DBCTL_DBCLKSEL_16 + * - \ref GPIO_DBCTL_DBCLKSEL_32 + * - \ref GPIO_DBCTL_DBCLKSEL_64 + * - \ref GPIO_DBCTL_DBCLKSEL_128 + * - \ref GPIO_DBCTL_DBCLKSEL_256 + * - \ref GPIO_DBCTL_DBCLKSEL_512 + * - \ref GPIO_DBCTL_DBCLKSEL_1024 + * - \ref GPIO_DBCTL_DBCLKSEL_2048 + * - \ref GPIO_DBCTL_DBCLKSEL_4096 + * - \ref GPIO_DBCTL_DBCLKSEL_8192 + * - \ref GPIO_DBCTL_DBCLKSEL_16384 + * - \ref GPIO_DBCTL_DBCLKSEL_32768 + * + * @return None + * + * @details Set the interrupt de-bounce sampling cycle time based on the debounce counter clock source. \n + * Example: _GPIO_SET_DEBOUNCE_TIME(GPIO_DBCTL_DBCLKSRC_LIRC, GPIO_DBCTL_DBCLKSEL_4). \n + * It's meaning the De-debounce counter clock source is internal 10 KHz and sampling cycle selection is 4. \n + * Then the target de-bounce sampling cycle time is (4)*(1/(10*1000)) s = 4*0.0001 s = 400 us, + * and system will sampling interrupt input once per 00 us. + * \hideinitializer + */ +#define GPIO_SET_DEBOUNCE_TIME(u32ClkSrc, u32ClkSel) (GPIO->DBCTL = (GPIO_DBCTL_ICLKON_Msk | (u32ClkSrc) | (u32ClkSel))) + +/** + * @brief Get GPIO Port IN Data + * +* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * + * @return The specified port data + * + * @details Get the PIN register of specified GPIO port. + * \hideinitializer + */ +#define GPIO_GET_IN_DATA(port) ((port)->PIN) + +/** + * @brief Set GPIO Port OUT Data + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32Data GPIO port data. + * + * @return None + * + * @details Set the Data into specified GPIO port. + * \hideinitializer + */ +#define GPIO_SET_OUT_DATA(port, u32Data) ((port)->DOUT = (u32Data)) + +/** + * @brief Toggle Specified GPIO pin + * + * @param[in] u32Pin Pxy + * + * @return None + * + * @details Toggle the specified GPIO pint. + * \hideinitializer + */ +#define GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1) + + +/** + * @brief Enable External GPIO interrupt + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32Pin The pin of specified GPIO port. + * It could be 0 ~ 15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be 0 ~ 13 for PE GPIO port. + * It could be 0 ~ 11 for PG GPIO port. + * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n + * GPIO_INT_RISING, GPIO_INT_FALLING, GPIO_INT_BOTH_EDGE, GPIO_INT_HIGH, GPIO_INT_LOW. + * + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + * \hideinitializer + */ +#define GPIO_EnableEINT GPIO_EnableInt + +/** + * @brief Disable External GPIO interrupt + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32Pin The pin of specified GPIO port. + * It could be 0 ~ 15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be 0 ~ 13 for PE GPIO port. + * It could be 0 ~ 11 for PG GPIO port. + * + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + * \hideinitializer + */ +#define GPIO_DisableEINT GPIO_DisableInt + + +void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode); +void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs); +void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin); +void GPIO_SetSlewCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode); +void GPIO_SetPullCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode); + + +/*@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group GPIO_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_GPIO_H__ */ + +/*** (C) COPYRIGHT 2013~2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_hsotg.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_hsotg.h new file mode 100644 index 0000000000000000000000000000000000000000..b561f226748d8b93e6f480e7c3ee4908cf0f79c6 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_hsotg.h @@ -0,0 +1,268 @@ +/**************************************************************************//** + * @file nu_hsotg.h + * @version V0.10 + * @brief M480 Series HSOTG Driver Header File + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __NU_HSOTG_H__ +#define __NU_HSOTG_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup HSOTG_Driver HSOTG Driver + @{ +*/ + + +/** @addtogroup HSOTG_EXPORTED_CONSTANTS HSOTG Exported Constants + @{ +*/ + + + +/*---------------------------------------------------------------------------------------------------------*/ +/* HSOTG constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define HSOTG_VBUS_EN_ACTIVE_HIGH (0UL) /*!< USB VBUS power switch enable signal is active high. \hideinitializer */ +#define HSOTG_VBUS_EN_ACTIVE_LOW (1UL) /*!< USB VBUS power switch enable signal is active low. \hideinitializer */ +#define HSOTG_VBUS_ST_VALID_HIGH (0UL) /*!< USB VBUS power switch valid status is high. \hideinitializer */ +#define HSOTG_VBUS_ST_VALID_LOW (1UL) /*!< USB VBUS power switch valid status is low. \hideinitializer */ + + +/*@}*/ /* end of group HSOTG_EXPORTED_CONSTANTS */ + + +/** @addtogroup HSOTG_EXPORTED_FUNCTIONS HSOTG Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Macros and functions */ +/*---------------------------------------------------------------------------------------------------------*/ + + +/** + * @brief This macro is used to enable HSOTG function + * @param None + * @return None + * @details This macro will set OTGEN bit of HSOTG_CTL register to enable HSOTG function. + * \hideinitializer + */ +#define HSOTG_ENABLE() (HSOTG->CTL |= HSOTG_CTL_OTGEN_Msk) + +/** + * @brief This macro is used to disable HSOTG function + * @param None + * @return None + * @details This macro will clear OTGEN bit of HSOTG_CTL register to disable HSOTG function. + * \hideinitializer + */ +#define HSOTG_DISABLE() (HSOTG->CTL &= ~HSOTG_CTL_OTGEN_Msk) + +/** + * @brief This macro is used to enable USB PHY + * @param None + * @return None + * @details When the USB role is selected as HSOTG device, use this macro to enable USB PHY. + * This macro will set OTGPHYEN bit of HSOTG_PHYCTL register to enable USB PHY. + * \hideinitializer + */ +#define HSOTG_ENABLE_PHY() (HSOTG->PHYCTL |= HSOTG_PHYCTL_OTGPHYEN_Msk) + +/** + * @brief This macro is used to disable USB PHY + * @param None + * @return None + * @details This macro will clear OTGPHYEN bit of HSOTG_PHYCTL register to disable USB PHY. + * \hideinitializer + */ +#define HSOTG_DISABLE_PHY() (HSOTG->PHYCTL &= ~HSOTG_PHYCTL_OTGPHYEN_Msk) + +/** + * @brief This macro is used to enable ID detection function + * @param None + * @return None + * @details This macro will set IDDETEN bit of HSOTG_PHYCTL register to enable ID detection function. + * \hideinitializer + */ +#define HSOTG_ENABLE_ID_DETECT() (HSOTG->PHYCTL |= HSOTG_PHYCTL_IDDETEN_Msk) + +/** + * @brief This macro is used to disable ID detection function + * @param None + * @return None + * @details This macro will clear IDDETEN bit of HSOTG_PHYCTL register to disable ID detection function. + * \hideinitializer + */ +#define HSOTG_DISABLE_ID_DETECT() (HSOTG->PHYCTL &= ~HSOTG_PHYCTL_IDDETEN_Msk) + +/** + * @brief This macro is used to enable HSOTG wake-up function + * @param None + * @return None + * @details This macro will set WKEN bit of HSOTG_CTL register to enable HSOTG wake-up function. + * \hideinitializer + */ +#define HSOTG_ENABLE_WAKEUP() (HSOTG->CTL |= HSOTG_CTL_WKEN_Msk) + +/** + * @brief This macro is used to disable HSOTG wake-up function + * @param None + * @return None + * @details This macro will clear WKEN bit of HSOTG_CTL register to disable HSOTG wake-up function. + * \hideinitializer + */ +#define HSOTG_DISABLE_WAKEUP() (HSOTG->CTL &= ~HSOTG_CTL_WKEN_Msk) + +/** + * @brief This macro is used to set the polarity of USB_VBUS_EN pin + * @param[in] u32Pol The polarity selection. Valid values are listed below. + * - \ref HSOTG_VBUS_EN_ACTIVE_HIGH + * - \ref HSOTG_VBUS_EN_ACTIVE_LOW + * @return None + * @details This macro is used to set the polarity of external USB VBUS power switch enable signal. + * \hideinitializer + */ +#define HSOTG_SET_VBUS_EN_POL(u32Pol) (HSOTG->PHYCTL = (HSOTG->PHYCTL & (~HSOTG_PHYCTL_VBENPOL_Msk)) | ((u32Pol)<PHYCTL = (HSOTG->PHYCTL & (~HSOTG_PHYCTL_VBSTSPOL_Msk)) | ((u32Pol)<INTEN |= (u32Mask)) + +/** + * @brief This macro is used to disable HSOTG related interrupts + * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref HSOTG_INTEN_ROLECHGIEN_Msk + * - \ref HSOTG_INTEN_VBEIEN_Msk + * - \ref HSOTG_INTEN_SRPFIEN_Msk + * - \ref HSOTG_INTEN_HNPFIEN_Msk + * - \ref HSOTG_INTEN_GOIDLEIEN_Msk + * - \ref HSOTG_INTEN_IDCHGIEN_Msk + * - \ref HSOTG_INTEN_PDEVIEN_Msk + * - \ref HSOTG_INTEN_HOSTIEN_Msk + * - \ref HSOTG_INTEN_BVLDCHGIEN_Msk + * - \ref HSOTG_INTEN_AVLDCHGIEN_Msk + * - \ref HSOTG_INTEN_VBCHGIEN_Msk + * - \ref HSOTG_INTEN_SECHGIEN_Msk + * - \ref HSOTG_INTEN_SRPDETIEN_Msk + * @return None + * @details This macro will disable HSOTG related interrupts specified by u32Mask parameter. + * \hideinitializer + */ +#define HSOTG_DISABLE_INT(u32Mask) (HSOTG->INTEN &= ~(u32Mask)) + +/** + * @brief This macro is used to get HSOTG related interrupt flags + * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref HSOTG_INTSTS_ROLECHGIF_Msk + * - \ref HSOTG_INTSTS_VBEIF_Msk + * - \ref HSOTG_INTSTS_SRPFIF_Msk + * - \ref HSOTG_INTSTS_HNPFIF_Msk + * - \ref HSOTG_INTSTS_GOIDLEIF_Msk + * - \ref HSOTG_INTSTS_IDCHGIF_Msk + * - \ref HSOTG_INTSTS_PDEVIF_Msk + * - \ref HSOTG_INTSTS_HOSTIF_Msk + * - \ref HSOTG_INTSTS_BVLDCHGIF_Msk + * - \ref HSOTG_INTSTS_AVLDCHGIF_Msk + * - \ref HSOTG_INTSTS_VBCHGIF_Msk + * - \ref HSOTG_INTSTS_SECHGIF_Msk + * - \ref HSOTG_INTSTS_SRPDETIF_Msk + * @return Interrupt flags of selected sources. + * @details This macro will return HSOTG related interrupt flags specified by u32Mask parameter. + * \hideinitializer + */ +#define HSOTG_GET_INT_FLAG(u32Mask) (HSOTG->INTSTS & (u32Mask)) + +/** + * @brief This macro is used to clear HSOTG related interrupt flags + * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref HSOTG_INTSTS_ROLECHGIF_Msk + * - \ref HSOTG_INTSTS_VBEIF_Msk + * - \ref HSOTG_INTSTS_SRPFIF_Msk + * - \ref HSOTG_INTSTS_HNPFIF_Msk + * - \ref HSOTG_INTSTS_GOIDLEIF_Msk + * - \ref HSOTG_INTSTS_IDCHGIF_Msk + * - \ref HSOTG_INTSTS_PDEVIF_Msk + * - \ref HSOTG_INTSTS_HOSTIF_Msk + * - \ref HSOTG_INTSTS_BVLDCHGIF_Msk + * - \ref HSOTG_INTSTS_AVLDCHGIF_Msk + * - \ref HSOTG_INTSTS_VBCHGIF_Msk + * - \ref HSOTG_INTSTS_SECHGIF_Msk + * - \ref HSOTG_INTSTS_SRPDETIF_Msk + * @return None + * @details This macro will clear HSOTG related interrupt flags specified by u32Mask parameter. + * \hideinitializer + */ +#define HSOTG_CLR_INT_FLAG(u32Mask) (HSOTG->INTSTS = (u32Mask)) + +/** + * @brief This macro is used to get HSOTG related status + * @param[in] u32Mask The combination of user specified source. Valid values are listed below. + * - \ref HSOTG_STATUS_OVERCUR_Msk + * - \ref HSOTG_STATUS_IDSTS_Msk + * - \ref HSOTG_STATUS_SESSEND_Msk + * - \ref HSOTG_STATUS_BVLD_Msk + * - \ref HSOTG_STATUS_AVLD_Msk + * - \ref HSOTG_STATUS_VBUSVLD_Msk + * @return The user specified status. + * @details This macro will return HSOTG related status specified by u32Mask parameter. + * \hideinitializer + */ +#define HSOTG_GET_STATUS(u32Mask) (HSOTG->STATUS & (u32Mask)) + + + +/*@}*/ /* end of group HSOTG_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group HSOTG_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + + +#ifdef __cplusplus +} +#endif + + +#endif /* __NU_HSOTG_H__ */ + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_hsusbd.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_hsusbd.h new file mode 100644 index 0000000000000000000000000000000000000000..3fcebb1b2dacead3a1f40ec4323e5c55bae8c538 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_hsusbd.h @@ -0,0 +1,382 @@ +/**************************************************************************//** + * @file nu_hsusbd.h + * @version V1.00 + * @brief M480 HSUSBD driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_HSUSBD_H__ +#define __NU_HSUSBD_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup HSUSBD_Driver HSUSBD Driver + @{ +*/ + +/** @addtogroup HSUSBD_EXPORTED_CONSTANTS HSUSBD Exported Constants + @{ +*/ +/** @cond HIDDEN_SYMBOLS */ +#define HSUSBD_MAX_EP 12ul + +#define Maximum(a,b) (a)>(b) ? (a) : (b) +#define Minimum(a,b) (((a)<(b)) ? (a) : (b)) + + +#define CEP 0xfful /*!< Control Endpoint \hideinitializer */ +#define EPA 0ul /*!< Endpoint A \hideinitializer */ +#define EPB 1ul /*!< Endpoint B \hideinitializer */ +#define EPC 2ul /*!< Endpoint C \hideinitializer */ +#define EPD 3ul /*!< Endpoint D \hideinitializer */ +#define EPE 4ul /*!< Endpoint E \hideinitializer */ +#define EPF 5ul /*!< Endpoint F \hideinitializer */ +#define EPG 6ul /*!< Endpoint G \hideinitializer */ +#define EPH 7ul /*!< Endpoint H \hideinitializer */ +#define EPI 8ul /*!< Endpoint I \hideinitializer */ +#define EPJ 9ul /*!< Endpoint J \hideinitializer */ +#define EPK 10ul /*!< Endpoint K \hideinitializer */ +#define EPL 11ul /*!< Endpoint L \hideinitializer */ + +/** @endcond HIDDEN_SYMBOLS */ +/********************* Bit definition of CEPCTL register **********************/ +#define HSUSBD_CEPCTL_NAKCLR ((uint32_t)0x00000000ul) /*!PHYCTL |= (HSUSBD_PHYCTL_PHYEN_Msk|HSUSBD_PHYCTL_DPPUEN_Msk))) /*!PHYCTL &= ~HSUSBD_PHYCTL_DPPUEN_Msk)) /*!PHYCTL |= HSUSBD_PHYCTL_PHYEN_Msk)) /*!PHYCTL &= ~HSUSBD_PHYCTL_PHYEN_Msk)) /*!PHYCTL &= ~HSUSBD_PHYCTL_DPPUEN_Msk)) /*!PHYCTL |= HSUSBD_PHYCTL_DPPUEN_Msk)) /*!FADDR = (addr)) /*!FADDR)) /*!GINTEN = (intr)) /*!BUSINTEN = (intr)) /*!BUSINTSTS) /*!BUSINTSTS = (flag)) /*!CEPINTEN = (intr)) /*!CEPINTSTS = (flag)) /*!CEPCTL = (flag)) /*!CEPTXCNT = (size)) /*!EP[(ep)].EPMPS = (size)) /*!EP[(ep)].EPINTEN = (intr)) /*!EP[(ep)].EPINTSTS) /*!EP[(ep)].EPINTSTS = (flag)) /*!DMACNT = (len)) /*!DMAADDR = (addr)) /*!DMACTL = (HSUSBD->DMACTL & ~HSUSBD_DMACTL_EPNUM_Msk) | HSUSBD_DMACTL_DMARD_Msk | (epnum) | 0x100) /*!DMACTL = (HSUSBD->DMACTL & ~(HSUSBD_DMACTL_EPNUM_Msk | HSUSBD_DMACTL_DMARD_Msk | 0x100)) | (epnum)) /*!DMACTL |= HSUSBD_DMACTL_DMAEN_Msk) /*!PHYCTL & HSUSBD_PHYCTL_VBUSDET_Msk)) /*!DMACNT = 0ul; + HSUSBD->DMACTL = 0x80ul; + HSUSBD->DMACTL = 0x00ul; +} +/** + * @brief HSUSBD_SetEpBufAddr, Set Endpoint buffer address + * @param[in] u32Ep Endpoint Number + * @param[in] u32Base Buffer Start Address + * @param[in] u32Len Buffer length + * @retval None. + */ +__STATIC_INLINE void HSUSBD_SetEpBufAddr(uint32_t u32Ep, uint32_t u32Base, uint32_t u32Len) +{ + if (u32Ep == CEP) + { + HSUSBD->CEPBUFST = u32Base; + HSUSBD->CEPBUFEND = u32Base + u32Len - 1ul; + } + else + { + HSUSBD->EP[u32Ep].EPBUFST = u32Base; + HSUSBD->EP[u32Ep].EPBUFEND = u32Base + u32Len - 1ul; + } +} + +/** + * @brief HSUSBD_ConfigEp, Config Endpoint + * @param[in] u32Ep USB endpoint + * @param[in] u32EpNum Endpoint number + * @param[in] u32EpType Endpoint type + * @param[in] u32EpDir Endpoint direction + * @retval None. + */ +__STATIC_INLINE void HSUSBD_ConfigEp(uint32_t u32Ep, uint32_t u32EpNum, uint32_t u32EpType, uint32_t u32EpDir) +{ + if (u32EpType == HSUSBD_EP_CFG_TYPE_BULK) + { + HSUSBD->EP[u32Ep].EPRSPCTL = (HSUSBD_EP_RSPCTL_FLUSH|HSUSBD_EP_RSPCTL_MODE_AUTO); + } + else if (u32EpType == HSUSBD_EP_CFG_TYPE_INT) + { + HSUSBD->EP[u32Ep].EPRSPCTL = (HSUSBD_EP_RSPCTL_FLUSH|HSUSBD_EP_RSPCTL_MODE_MANUAL); + } + else if (u32EpType == HSUSBD_EP_CFG_TYPE_ISO) + { + HSUSBD->EP[u32Ep].EPRSPCTL = (HSUSBD_EP_RSPCTL_FLUSH|HSUSBD_EP_RSPCTL_MODE_FLY); + } + + HSUSBD->EP[u32Ep].EPCFG = (u32EpType|u32EpDir|HSUSBD_EP_CFG_VALID|(u32EpNum << 4)); +} + +/** + * @brief Set USB endpoint stall state + * @param[in] u32Ep The USB endpoint ID. + * @return None + * @details Set USB endpoint stall state for the specified endpoint ID. Endpoint will respond STALL token automatically. + */ +__STATIC_INLINE void HSUSBD_SetEpStall(uint32_t u32Ep) +{ + if (u32Ep == CEP) + { + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALL); + } + else + { + HSUSBD->EP[u32Ep].EPRSPCTL = (HSUSBD->EP[u32Ep].EPRSPCTL & 0xf7ul) | HSUSBD_EP_RSPCTL_HALT; + } +} + +/** + * @brief Set USB endpoint stall state + * + * @param[in] u32EpNum USB endpoint + * @return None + * + * @details Set USB endpoint stall state, endpoint will return STALL token. + */ +__STATIC_INLINE void HSUSBD_SetStall(uint32_t u32EpNum) +{ + uint32_t i; + + if (u32EpNum == 0ul) + { + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALL); + } + else + { + for (i=0ul; iEP[i].EPCFG & 0xf0ul) >> 4) == u32EpNum) + { + HSUSBD->EP[i].EPRSPCTL = (HSUSBD->EP[i].EPRSPCTL & 0xf7ul) | HSUSBD_EP_RSPCTL_HALT; + } + } + } +} + +/** + * @brief Clear USB endpoint stall state + * @param[in] u32Ep The USB endpoint ID. + * @return None + * @details Clear USB endpoint stall state for the specified endpoint ID. Endpoint will respond ACK/NAK token. + */ +__STATIC_INLINE void HSUSBD_ClearEpStall(uint32_t u32Ep) +{ + HSUSBD->EP[u32Ep].EPRSPCTL = HSUSBD_EP_RSPCTL_TOGGLE; +} + +/** + * @brief Clear USB endpoint stall state + * + * @param[in] u32EpNum USB endpoint + * @return None + * + * @details Clear USB endpoint stall state, endpoint will return ACK/NAK token. + */ +__STATIC_INLINE void HSUSBD_ClearStall(uint32_t u32EpNum) +{ + uint32_t i; + + for (i=0ul; iEP[i].EPCFG & 0xf0ul) >> 4) == u32EpNum) + { + HSUSBD->EP[i].EPRSPCTL = HSUSBD_EP_RSPCTL_TOGGLE; + } + } +} + +/** + * @brief Get USB endpoint stall state + * @param[in] u32Ep The USB endpoint ID. + * @retval 0 USB endpoint is not stalled. + * @retval Others USB endpoint is stalled. + * @details Get USB endpoint stall state of the specified endpoint ID. + */ +__STATIC_INLINE uint32_t HSUSBD_GetEpStall(uint32_t u32Ep) +{ + return (HSUSBD->EP[u32Ep].EPRSPCTL & HSUSBD_EP_RSPCTL_HALT); +} + +/** + * @brief Get USB endpoint stall state + * + * @param[in] u32EpNum USB endpoint + * @retval 0: USB endpoint is not stalled. + * @retval non-0: USB endpoint is stalled. + * + * @details Get USB endpoint stall state. + */ +__STATIC_INLINE uint32_t HSUSBD_GetStall(uint32_t u32EpNum) +{ + uint32_t i; + uint32_t val = 0ul; + + for (i=0ul; iEP[i].EPCFG & 0xf0ul) >> 4) == u32EpNum) + { + val = (HSUSBD->EP[i].EPRSPCTL & HSUSBD_EP_RSPCTL_HALT); + break; + } + } + return val; +} + + +/*-------------------------------------------------------------------------------------------*/ +typedef void (*HSUSBD_VENDOR_REQ)(void); /*!CTL0 = ((i2c)->CTL0 & ~0x3c) | (u8Ctrl)) + +/** + * @brief The macro is used to set START condition of I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Set the I2C bus START condition in I2C_CTL register. + * \hideinitializer + */ +#define I2C_START(i2c) ((i2c)->CTL0 = ((i2c)->CTL0 & ~I2C_CTL0_SI_Msk) | I2C_CTL0_STA_Msk) + +/** + * @brief The macro is used to wait I2C bus status get ready + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details When a new status is presented of I2C bus, the SI flag will be set in I2C_CTL register. + * \hideinitializer + */ +#define I2C_WAIT_READY(i2c) while(!((i2c)->CTL0 & I2C_CTL0_SI_Msk)) + +/** + * @brief The macro is used to Read I2C Bus Data Register + * + * @param[in] i2c Specify I2C port + * + * @return A byte of I2C data register + * + * @details I2C controller read data from bus and save it in I2CDAT register. + * \hideinitializer + */ +#define I2C_GET_DATA(i2c) ((i2c)->DAT) + +/** + * @brief Write a Data to I2C Data Register + * + * @param[in] i2c Specify I2C port + * @param[in] u8Data A byte that writes to data register + * + * @return None + * + * @details When write a data to I2C_DAT register, the I2C controller will shift it to I2C bus. + * \hideinitializer + */ +#define I2C_SET_DATA(i2c, u8Data) ((i2c)->DAT = (u8Data)) + +/** + * @brief Get I2C Bus status code + * + * @param[in] i2c Specify I2C port + * + * @return I2C status code + * + * @details To get this status code to monitor I2C bus event. + * \hideinitializer + */ +#define I2C_GET_STATUS(i2c) ((i2c)->STATUS0) + +/** + * @brief Get Time-out flag from I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @retval 0 I2C Bus time-out is not happened + * @retval 1 I2C Bus time-out is happened + * + * @details When I2C bus occurs time-out event, the time-out flag will be set. + * \hideinitializer + */ +#define I2C_GET_TIMEOUT_FLAG(i2c) ( ((i2c)->TOCTL & I2C_TOCTL_TOIF_Msk) == I2C_TOCTL_TOIF_Msk ? 1:0 ) + +/** + * @brief To get wake-up flag from I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @retval 0 Chip is not woken-up from power-down mode + * @retval 1 Chip is woken-up from power-down mode + * + * @details I2C bus occurs wake-up event, wake-up flag will be set. + * \hideinitializer + */ +#define I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WKIF_Msk) == I2C_WKSTS_WKIF_Msk ? 1:0 ) + +/** + * @brief To clear wake-up flag + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details If wake-up flag is set, use this macro to clear it. + * \hideinitializer + */ +#define I2C_CLEAR_WAKEUP_FLAG(i2c) ((i2c)->WKSTS = I2C_WKSTS_WKIF_Msk) + +/** + * @brief To get SMBus Status + * + * @param[in] i2c Specify I2C port + * + * @return SMBus status + * + * @details To get the Bus Management status of I2C_BUSSTS register + * \hideinitializer + * + */ +#define I2C_SMBUS_GET_STATUS(i2c) ((i2c)->BUSSTS) + +/** + * @brief Get SMBus CRC value + * + * @param[in] i2c Specify I2C port + * + * @return Packet error check byte value + * + * @details The CRC check value after a transmission or a reception by count by using CRC8 + * \hideinitializer + */ +#define I2C_SMBUS_GET_PEC_VALUE(i2c) ((i2c)->PKTCRC) + +/** + * @brief Set SMBus Bytes number of Transmission or reception + * + * @param[in] i2c Specify I2C port + * @param[in] u32PktSize Transmit / Receive bytes + * + * @return None + * + * @details The transmission or receive byte number in one transaction when PECEN is set. The maximum is 255 bytes. + * \hideinitializer + */ +#define I2C_SMBUS_SET_PACKET_BYTE_COUNT(i2c, u32PktSize) ((i2c)->PKTSIZE = (u32PktSize)) + +/** + * @brief Enable SMBus Alert function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin will pull lo, and reply ACK when get ARP from host + * Host Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin is supported to receive alert state(Lo trigger) + * \hideinitializer + */ +#define I2C_SMBUS_ENABLE_ALERT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ALERTEN_Msk) + +/** + * @brief Disable SMBus Alert pin function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin will pull hi, and reply NACK when get ARP from host + * Host Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin is not supported to receive alert state(Lo trigger) + * \hideinitializer + */ +#define I2C_SMBUS_DISABLE_ALERT(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ALERTEN_Msk) + +/** + * @brief Set SMBus SUSCON pin is output mode + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output mode. + * + * \hideinitializer + */ +#define I2C_SMBUS_SET_SUSCON_OUT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOEN_Msk) + +/** + * @brief Set SMBus SUSCON pin is input mode + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is input mode. + * + * \hideinitializer + */ +#define I2C_SMBUS_SET_SUSCON_IN(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOEN_Msk) + +/** + * @brief Set SMBus SUSCON pin output high state + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output hi state. + * \hideinitializer + */ +#define I2C_SMBUS_SET_SUSCON_HIGH(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOSTS_Msk) + + +/** + * @brief Set SMBus SUSCON pin output low state + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output lo state. + * \hideinitializer + */ +#define I2C_SMBUS_SET_SUSCON_LOW(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOSTS_Msk) + +/** + * @brief Enable SMBus Acknowledge control by manual + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details The 9th bit can response the ACK or NACK according the received data by user. When the byte is received, SCLK line stretching to low between the 8th and 9th SCLK pulse. + * \hideinitializer + */ +#define I2C_SMBUS_ACK_MANUAL(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ACKMEN_Msk) + +/** + * @brief Disable SMBus Acknowledge control by manual + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Disable acknowledge response control by user. + * \hideinitializer + */ +#define I2C_SMBUS_ACK_AUTO(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKMEN_Msk) + +/** + * @brief Enable SMBus Acknowledge manual interrupt + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function is used to enable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1 + * \hideinitializer + */ +#define I2C_SMBUS_9THBIT_INT_ENABLE(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ACKM9SI_Msk) + +/** + * @brief Disable SMBus Acknowledge manual interrupt + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function is used to disable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1 + * \hideinitializer + */ +#define I2C_SMBUS_9THBIT_INT_DISABLE(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKM9SI_Msk) + +/** + * @brief Enable SMBus PEC clear at REPEAT START + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function is used to enable the condition of REAEAT START can clear the PEC calculation. + * \hideinitializer + */ +#define I2C_SMBUS_RST_PEC_AT_START_ENABLE(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_PECCLR_Msk) + +/** + * @brief Disable SMBus PEC clear at Repeat START + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function is used to disable the condition of Repeat START can clear the PEC calculation. + * \hideinitializer + */ +#define I2C_SMBUS_RST_PEC_AT_START_DISABLE(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_PECCLR_Msk) + +/** + * @brief Enable RX PDMA function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Set RXPDMAEN bit of I2C_CTL1 register to enable RX PDMA transfer function. + * \hideinitializer + */ +#define I2C_ENABLE_RX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_RXPDMAEN_Msk) + +/** + * @brief Enable TX PDMA function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Set TXPDMAEN bit of I2C_CTL1 register to enable TX PDMA transfer function. + * \hideinitializer + */ +#define I2C_ENABLE_TX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_TXPDMAEN_Msk) + +/** + * @brief Disable RX PDMA transfer. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Clear RXPDMAEN bit of I2C_CTL1 register to disable RX PDMA transfer function. + * \hideinitializer + */ +#define I2C_DISABLE_RX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_RXPDMAEN_Msk) + +/** + * @brief Disable TX PDMA transfer. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Clear TXPDMAEN bit of I2C_CTL1 register to disable TX PDMA transfer function. + * \hideinitializer + */ +#define I2C_DISABLE_TX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_TXPDMAEN_Msk) + +/** + * @brief Enable PDMA stretch function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Enable this function is to stretch bus by hardware after PDMA transfer is done if SI is not cleared. + * \hideinitializer + */ +#define I2C_ENABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMASTR_Msk) + +/** + * @brief Disable PDMA stretch function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details I2C will send STOP after PDMA transfers done automatically. + * \hideinitializer + */ +#define I2C_DISABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_PDMASTR_Msk) + +/** + * @brief Reset PDMA function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details I2C PDMA engine will be reset after this function is called. + * \hideinitializer + */ +#define I2C_DISABLE_RST_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMARST_Msk) + +/*---------------------------------------------------------------------------------------------------------*/ +/* inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void I2C_STOP(I2C_T *i2c); + +/** + * @brief The macro is used to set STOP condition of I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Set the I2C bus STOP condition in I2C_CTL register. + */ +__STATIC_INLINE void I2C_STOP(I2C_T *i2c) +{ + + (i2c)->CTL0 |= (I2C_CTL0_SI_Msk | I2C_CTL0_STO_Msk); + while(i2c->CTL0 & I2C_CTL0_STO_Msk) + { + } +} + +void I2C_ClearTimeoutFlag(I2C_T *i2c); +void I2C_Close(I2C_T *i2c); +void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack); +void I2C_DisableInt(I2C_T *i2c); +void I2C_EnableInt(I2C_T *i2c); +uint32_t I2C_GetBusClockFreq(I2C_T *i2c); +uint32_t I2C_GetIntFlag(I2C_T *i2c); +uint32_t I2C_GetStatus(I2C_T *i2c); +uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock); +uint8_t I2C_GetData(I2C_T *i2c); +void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode); +void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask); +uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock); +void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout); +void I2C_DisableTimeout(I2C_T *i2c); +void I2C_EnableWakeup(I2C_T *i2c); +void I2C_DisableWakeup(I2C_T *i2c); +void I2C_SetData(I2C_T *i2c, uint8_t u8Data); +void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8SMBusIntFlag); +uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data); +uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data[], uint32_t u32wLen); +uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data); +uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data[], uint32_t u32wLen); +uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data); +uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data[], uint32_t u32wLen); +uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr); +uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t rdata[], uint32_t u32rLen); +uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr); +uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t rdata[], uint32_t u32rLen); +uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr); +uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t rdata[], uint32_t u32rLen); +uint32_t I2C_SMBusGetStatus(I2C_T *i2c); +void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize); +void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice); +void I2C_SMBusClose(I2C_T *i2c); +void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn); +uint8_t I2C_SMBusGetPECValue(I2C_T *i2c); +void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t us, uint32_t u32Hclk); +void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk); +void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk); + +/*@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group I2C_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_i2s.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_i2s.h new file mode 100644 index 0000000000000000000000000000000000000000..096c6c0d1aee8b01b690083578a4a74f9f68c550 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_i2s.h @@ -0,0 +1,353 @@ +/****************************************************************************//** + * @file nu_i2s.h + * @version V0.10 + * @brief M480 I2S driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __NU_I2S_H__ +#define __NU_I2S_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup I2S_Driver I2S Driver + @{ +*/ + +/** @addtogroup I2S_EXPORTED_CONSTANTS I2S Exported Constants + @{ +*/ +#define I2S_DATABIT_8 (0U << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 8-bit \hideinitializer */ +#define I2S_DATABIT_16 (1U << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 16-bit \hideinitializer */ +#define I2S_DATABIT_24 (2U << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 24-bit \hideinitializer */ +#define I2S_DATABIT_32 (3U << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 32-bit \hideinitializer */ + +/* Audio Format */ +#define I2S_ENABLE_MONO I2S_CTL0_MONO_Msk /*!< Mono channel \hideinitializer */ +#define I2S_DISABLE_MONO (0U) /*!< Stereo channel \hideinitializer */ + +/* I2S Data Format */ +#define I2S_FORMAT_I2S (0U << I2S_CTL0_FORMAT_Pos) /*!< I2S data format \hideinitializer */ +#define I2S_FORMAT_I2S_MSB (1U << I2S_CTL0_FORMAT_Pos) /*!< I2S MSB data format \hideinitializer */ +#define I2S_FORMAT_I2S_LSB (2U << I2S_CTL0_FORMAT_Pos) /*!< I2S LSB data format \hideinitializer */ +#define I2S_FORMAT_PCM (4U << I2S_CTL0_FORMAT_Pos) /*!< PCM data format \hideinitializer */ +#define I2S_FORMAT_PCM_MSB (5U << I2S_CTL0_FORMAT_Pos) /*!< PCM MSB data format \hideinitializer */ +#define I2S_FORMAT_PCM_LSB (6U << I2S_CTL0_FORMAT_Pos) /*!< PCM LSB data format \hideinitializer */ + +/* I2S Data Format */ +#define I2S_ORDER_AT_MSB (0U) /*!< Channel data is at MSB \hideinitializer */ +#define I2S_ORDER_AT_LSB I2S_CTL0_ORDER_Msk /*!< Channel data is at LSB \hideinitializer */ + +/* I2S TDM Channel Number */ +#define I2S_TDM_2CH 0U /*!< Use TDM 2 channel \hideinitializer */ +#define I2S_TDM_4CH 1U /*!< Use TDM 4 channel \hideinitializer */ +#define I2S_TDM_6CH 2U /*!< Use TDM 6 channel \hideinitializer */ +#define I2S_TDM_8CH 3U /*!< Use TDM 8 channel \hideinitializer */ + +/* I2S TDM Channel Width */ +#define I2S_TDM_WIDTH_8BIT 0U /*!< TDM channel witch is 8-bit \hideinitializer */ +#define I2S_TDM_WIDTH_16BIT 1U /*!< TDM channel witch is 16-bit \hideinitializer */ +#define I2S_TDM_WIDTH_24BIT 2U /*!< TDM channel witch is 24-bit \hideinitializer */ +#define I2S_TDM_WIDTH_32BIT 3U /*!< TDM channel witch is 32-bit \hideinitializer */ + +/* I2S TDM Sync Width */ +#define I2S_TDM_SYNC_ONE_BCLK 0U /*!< TDM sync widht is one BLCK period \hideinitializer */ +#define I2S_TDM_SYNC_ONE_CHANNEL 1U /*!< TDM sync widht is one channel period \hideinitializer */ + +/* I2S Operation mode */ +#define I2S_MODE_SLAVE I2S_CTL0_SLAVE_Msk /*!< As slave mode \hideinitializer */ +#define I2S_MODE_MASTER (0u) /*!< As master mode \hideinitializer */ + +/* I2S FIFO Threshold */ +#define I2S_FIFO_TX_LEVEL_WORD_0 (0U) /*!< TX threshold is 0 word \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_1 (1U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 1 word \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_2 (2U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 2 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_3 (3U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 3 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_4 (4U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 4 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_5 (5U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 5 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_6 (6U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 6 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_7 (7U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 7 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_8 (8U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 8 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_9 (9U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 9 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_10 (10U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 10 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_11 (11U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 11 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_12 (12U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 12 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_13 (13U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 13 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_14 (14U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 14 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_15 (15U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 15 words \hideinitializer */ + +#define I2S_FIFO_RX_LEVEL_WORD_1 (0U) /*!< RX threshold is 1 word \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_2 (1U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 2 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_3 (2U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 3 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_4 (3U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 4 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_5 (4U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 5 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_6 (5U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 6 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_7 (6U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 7 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_8 (7U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 8 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_9 (8U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 9 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_10 (9U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 10 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_11 (10U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 11 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_12 (11U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 12 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_13 (12U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 13 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_14 (13U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 14 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_15 (14U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 15 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_16 (15U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 16 words \hideinitializer */ + +/* I2S Record Channel */ +#define I2S_MONO_RIGHT (0U) /*!< Record mono right channel \hideinitializer */ +#define I2S_MONO_LEFT I2S_CTL0_RXLCH_Msk /*!< Record mono left channel \hideinitializer */ + +/* I2S Channel */ +#define I2S_RIGHT (0U) /*!< Select right channel \hideinitializer */ +#define I2S_LEFT (1U) /*!< Select left channel \hideinitializer */ + +/*@}*/ /* end of group I2S_EXPORTED_CONSTANTS */ + +/** @addtogroup I2S_EXPORTED_FUNCTIONS I2S Exported Functions + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/** + * @brief Enable zero cross detect function. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32ChMask is the mask for channel number (valid value is from (1~8). + * @return none + * \hideinitializer + */ +__STATIC_INLINE void I2S_ENABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask) +{ + if((u32ChMask > 0U) && (u32ChMask < 9U)) + { + i2s->CTL1 |= ((uint32_t)1U << (u32ChMask-1U)); + } +} + +/** + * @brief Disable zero cross detect function. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32ChMask is the mask for channel number (valid value is from (1~8). + * @return none + * \hideinitializer + */ +__STATIC_INLINE void I2S_DISABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask) +{ + if((u32ChMask > 0U) && (u32ChMask < 9U)) + { + i2s->CTL1 &= ~((uint32_t)1U << (u32ChMask-1U)); + } +} + +/** + * @brief Enable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_TXDMA(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXPDMAEN_Msk ) + +/** + * @brief Disable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_TXDMA(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_TXPDMAEN_Msk ) + +/** + * @brief Enable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_RXDMA(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXPDMAEN_Msk ) + +/** + * @brief Disable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_RXDMA(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_RXPDMAEN_Msk ) + +/** + * @brief Enable I2S Tx function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_TX(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXEN_Msk ) + +/** + * @brief Disable I2S Tx function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_TX(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_TXEN_Msk ) + +/** + * @brief Enable I2S Rx function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_RX(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXEN_Msk ) + +/** + * @brief Disable I2S Rx function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_RX(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_RXEN_Msk ) + +/** + * @brief Enable Tx Mute function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_TX_MUTE(i2s) ( (i2s)->CTL0 |= I2S_CTL0_MUTE_Msk ) + +/** + * @brief Disable Tx Mute function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_TX_MUTE(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_MUTE_Msk ) + +/** + * @brief Clear Tx FIFO. Internal pointer is reset to FIFO start point. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_CLR_TX_FIFO(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXFBCLR_Msk ) + +/** + * @brief Clear Rx FIFO. Internal pointer is reset to FIFO start point. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_CLR_RX_FIFO(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXFBCLR_Msk ) + +/** + * @brief This function sets the recording source channel when mono mode is used. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Ch left or right channel. Valid values are: + * - \ref I2S_MONO_LEFT + * - \ref I2S_MONO_RIGHT + * @return none + * \hideinitializer + */ +__STATIC_INLINE void I2S_SET_MONO_RX_CHANNEL(I2S_T *i2s, uint32_t u32Ch) +{ + u32Ch == I2S_MONO_LEFT ? + (i2s->CTL0 |= I2S_CTL0_RXLCH_Msk) : + (i2s->CTL0 &= ~I2S_CTL0_RXLCH_Msk); +} + +/** + * @brief Write data to I2S Tx FIFO. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Data: The data written to FIFO. + * @return none + * \hideinitializer + */ +#define I2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TXFIFO = (u32Data) ) + +/** + * @brief Read Rx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return Data in Rx FIFO. + * \hideinitializer + */ +#define I2S_READ_RX_FIFO(i2s) ( (i2s)->RXFIFO ) + +/** + * @brief This function gets the interrupt flag according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the mask for the all interrupt flags. + * @return The masked bit value of interrupt flag. + * \hideinitializer + */ +#define I2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS0 & (u32Mask) ) + +/** + * @brief This function clears the interrupt flag according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the mask for the all interrupt flags. + * @return none + * \hideinitializer + */ +#define I2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS0 |= (u32Mask) ) + +/** + * @brief This function gets the zero crossing interrupt flag according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the mask for the all interrupt flags. + * @return The masked bit value of interrupt flag. + * \hideinitializer + */ +#define I2S_GET_ZC_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS1 & (u32Mask) ) + +/** + * @brief This function clears the zero crossing interrupt flag according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the mask for the all interrupt flags. + * @return none + * \hideinitializer + */ +#define I2S_CLR_ZC_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS1 |= (u32Mask) ) + +/** + * @brief Get transmit FIFO level + * @param[in] i2s is the base address of I2S module. + * @return FIFO level + * \hideinitializer + */ +#define I2S_GET_TX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS1 & I2S_STATUS1_TXCNT_Msk) >> I2S_STATUS1_TXCNT_Pos) & 0xF ) + +/** + * @brief Get receive FIFO level + * @param[in] i2s is the base address of I2S module. + * @return FIFO level + * \hideinitializer + */ +#define I2S_GET_RX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS1 & I2S_STATUS1_RXCNT_Msk) >> I2S_STATUS1_RXCNT_Pos) & 0xF ) + +void I2S_Close(I2S_T *i2s); +void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask); +void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask); +uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock); +void I2S_DisableMCLK(I2S_T *i2s); +void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold); +void I2S_ConfigureTDM(I2S_T *i2s, uint32_t u32ChannelWidth, uint32_t u32ChannelNum, uint32_t u32SyncWidth); +uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32MonoData, uint32_t u32DataFormat); + +/*@}*/ /* end of group I2S_EXPORTED_FUNCTIONS */ + + +/*@}*/ /* end of group I2S_Driver */ + +/*@}*/ /* end of group Standard_Driver */ +#ifdef __cplusplus +} +#endif + +#endif + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ + diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_opa.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_opa.h new file mode 100644 index 0000000000000000000000000000000000000000..8d2baa9d180849f7426476acfcd39cfed7cfb785 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_opa.h @@ -0,0 +1,209 @@ +/**************************************************************************//** + * @file nu_opa.h + * @version V3.00 + * @brief M480 series OPA driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_OPA_H__ +#define __NU_OPA_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup OPA_Driver OPA Driver + @{ +*/ + +/** @addtogroup OPA_EXPORTED_CONSTANTS OPA Exported Constants + @{ +*/ +#define OPA_CALIBRATION_CLK_1K (0UL) /*!< OPA calibration clock select 1 KHz \hideinitializer */ +#define OPA_CALIBRATION_RV_1_2_AVDD (0UL) /*!< OPA calibration reference voltage select 1/2 AVDD \hideinitializer */ +#define OPA_CALIBRATION_RV_H_L_VCM (1UL) /*!< OPA calibration reference voltage select from high vcm to low vcm \hideinitializer */ + +/*@}*/ /* end of group OPA_EXPORTED_CONSTANTS */ + +/** @addtogroup OPA_EXPORTED_FUNCTIONS OPA Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define OPA functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +__STATIC_INLINE int32_t OPA_Calibration(OPA_T *opa, uint32_t u32OpaNum, uint32_t u32ClockSel, uint32_t u32LevelSel); + +/** + * @brief This macro is used to power on the OPA circuit + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2. + * @return None + * @details This macro will set OPx_EN (x=0, 1) bit of OPACR register to power on the OPA circuit. + * @note Remember to enable HIRC clock while power on the OPA circuit. + * \hideinitializer + */ +#define OPA_POWER_ON(opa, u32OpaNum) ((opa)->CTL |= (1UL<<(OPA_CTL_OPEN0_Pos+(u32OpaNum)))) + +/** + * @brief This macro is used to power down the OPA circuit + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2. + * @return None + * @details This macro will clear OPx_EN (x=0, 1) bit of OPACR register to power down the OPA circuit. + * \hideinitializer + */ +#define OPA_POWER_DOWN(opa, u32OpaNum) ((opa)->CTL &= ~(1UL<<(OPA_CTL_OPEN0_Pos+(u32OpaNum)))) + +/** + * @brief This macro is used to enable the OPA Schmitt trigger buffer + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2. + * @return None + * @details This macro will set OPSCHx_EN (x=0, 1) bit of OPACR register to enable the OPA Schmitt trigger buffer. + * \hideinitializer + */ +#define OPA_ENABLE_SCH_TRIGGER(opa, u32OpaNum) ((opa)->CTL |= (1UL<<(OPA_CTL_OPDOEN0_Pos+(u32OpaNum)))) + +/** + * @brief This macro is used to disable the OPA Schmitt trigger buffer + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2. + * @return None + * @details This macro will clear OPSCHx_EN (x=0, 1) bit of OPACR register to disable the OPA Schmitt trigger buffer. + * \hideinitializer + */ +#define OPA_DISABLE_SCH_TRIGGER(opa, u32OpaNum) ((opa)->CTL &= ~(1UL<<(OPA_CTL_OPDOEN0_Pos+(u32OpaNum)))) + +/** + * @brief This macro is used to enable OPA Schmitt trigger digital output interrupt + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2. + * @return None + * @details This macro will set OPDIEx (x=0, 1) bit of OPACR register to enable the OPA Schmitt trigger digital output interrupt. + * \hideinitializer + */ +#define OPA_ENABLE_INT(opa, u32OpaNum) ((opa)->CTL |= (1UL<<(OPA_CTL_OPDOIEN0_Pos+(u32OpaNum)))) + +/** + * @brief This macro is used to disable OPA Schmitt trigger digital output interrupt + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2. + * @return None + * @details This macro will clear OPDIEx (x=0, 1) bit of OPACR register to disable the OPA Schmitt trigger digital output interrupt. + * \hideinitializer + */ +#define OPA_DISABLE_INT(opa, u32OpaNum) ((opa)->CTL &= ~(1UL<<(OPA_CTL_OPDOIEN0_Pos+(u32OpaNum)))) + +/** + * @brief This macro is used to get OPA digital output state + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2. + * @return OPA digital output state + * @details This macro will return the OPA digital output value. + * \hideinitializer + */ +#define OPA_GET_DIGITAL_OUTPUT(opa, u32OpaNum) (((opa)->STATUS & (OPA_STATUS_OPDO0_Msk<<(u32OpaNum)))?1UL:0UL) + +/** + * @brief This macro is used to get OPA interrupt flag + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2. + * @retval 0 OPA interrupt does not occur. + * @retval 1 OPA interrupt occurs. + * @details This macro will return the ACMP interrupt flag. + * \hideinitializer + */ +#define OPA_GET_INT_FLAG(opa, u32OpaNum) (((opa)->STATUS & (OPA_STATUS_OPDOIF0_Msk<<(u32OpaNum)))?1UL:0UL) + +/** + * @brief This macro is used to clear OPA interrupt flag + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2. + * @return None + * @details This macro will write 1 to OPDFx (x=0,1) bit of OPASR register to clear interrupt flag. + * \hideinitializer + */ +#define OPA_CLR_INT_FLAG(opa, u32OpaNum) ((opa)->STATUS = (OPA_STATUS_OPDOIF0_Msk<<(u32OpaNum))) + + +/** + * @brief This function is used to configure and start OPA calibration + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2. + * @param[in] u32ClockSel Select OPA calibration clock + * - \ref OPA_CALIBRATION_CLK_1K + * @param[in] u32RefVol Select OPA reference voltage + * - \ref OPA_CALIBRATION_RV_1_2_AVDD + * - \ref OPA_CALIBRATION_RV_H_L_VCM + * @retval 0 PMOS and NMOS calibration successfully. + * @retval -1 only PMOS calibration failed. + * @retval -2 only NMOS calibration failed. + * @retval -3 PMOS and NMOS calibration failed. + */ +__STATIC_INLINE int32_t OPA_Calibration(OPA_T *opa, + uint32_t u32OpaNum, + uint32_t u32ClockSel, + uint32_t u32RefVol) +{ + uint32_t u32CALResult; + int32_t i32Ret = 0L; + + (opa)->CALCTL = (((opa)->CALCTL) & ~(OPA_CALCTL_CALCLK0_Msk << (u32OpaNum << 1))); + (opa)->CALCTL = (((opa)->CALCTL) & ~(OPA_CALCTL_CALRVS0_Msk << (u32OpaNum))) | (((u32RefVol) << OPA_CALCTL_CALRVS0_Pos) << (u32OpaNum)); + (opa)->CALCTL |= (OPA_CALCTL_CALTRG0_Msk << (u32OpaNum)); + while((opa)->CALCTL & (OPA_CALCTL_CALTRG0_Msk << (u32OpaNum))) {} + + u32CALResult = ((opa)->CALST >> ((u32OpaNum)*4U)) & (OPA_CALST_CALNS0_Msk|OPA_CALST_CALPS0_Msk); + if (u32CALResult == 0U) + { + i32Ret = 0L; + } + else if (u32CALResult == OPA_CALST_CALNS0_Msk) + { + i32Ret = -2L; + } + else if (u32CALResult == OPA_CALST_CALPS0_Msk) + { + i32Ret = -1L; + } + else if (u32CALResult == (OPA_CALST_CALNS0_Msk|OPA_CALST_CALPS0_Msk)) + { + i32Ret = -3L; + } + + return i32Ret; +} + +/** + * @brief This macro is used to generate asynchronous reset signals to OPA controller + * @param None + * @return None + * \hideinitializer + */ +#define OPA_Reset() \ +do { \ + SYS->IPRST2 |= SYS_IPRST2_OPARST_Msk; \ + SYS->IPRST2 &= ~SYS_IPRST2_OPARST_Msk; \ +} while(0) + +/*@}*/ /* end of group OPA_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group OPA_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_OPA_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_otg.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_otg.h new file mode 100644 index 0000000000000000000000000000000000000000..21c4b8be240cc32ba14b43245b8806d35b40d783 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_otg.h @@ -0,0 +1,268 @@ +/**************************************************************************//** + * @file nu_otg.h + * @version V0.10 + * @brief M480 Series OTG Driver Header File + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __NU_OTG_H__ +#define __NU_OTG_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup OTG_Driver OTG Driver + @{ +*/ + + +/** @addtogroup OTG_EXPORTED_CONSTANTS OTG Exported Constants + @{ +*/ + + + +/*---------------------------------------------------------------------------------------------------------*/ +/* OTG constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define OTG_VBUS_EN_ACTIVE_HIGH (0UL) /*!< USB VBUS power switch enable signal is active high. \hideinitializer */ +#define OTG_VBUS_EN_ACTIVE_LOW (1UL) /*!< USB VBUS power switch enable signal is active low. \hideinitializer */ +#define OTG_VBUS_ST_VALID_HIGH (0UL) /*!< USB VBUS power switch valid status is high. \hideinitializer */ +#define OTG_VBUS_ST_VALID_LOW (1UL) /*!< USB VBUS power switch valid status is low. \hideinitializer */ + + +/*@}*/ /* end of group OTG_EXPORTED_CONSTANTS */ + + +/** @addtogroup OTG_EXPORTED_FUNCTIONS OTG Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Macros and functions */ +/*---------------------------------------------------------------------------------------------------------*/ + + +/** + * @brief This macro is used to enable OTG function + * @param None + * @return None + * @details This macro will set OTGEN bit of OTG_CTL register to enable OTG function. + * \hideinitializer + */ +#define OTG_ENABLE() (OTG->CTL |= OTG_CTL_OTGEN_Msk) + +/** + * @brief This macro is used to disable OTG function + * @param None + * @return None + * @details This macro will clear OTGEN bit of OTG_CTL register to disable OTG function. + * \hideinitializer + */ +#define OTG_DISABLE() (OTG->CTL &= ~OTG_CTL_OTGEN_Msk) + +/** + * @brief This macro is used to enable USB PHY + * @param None + * @return None + * @details When the USB role is selected as OTG device, use this macro to enable USB PHY. + * This macro will set OTGPHYEN bit of OTG_PHYCTL register to enable USB PHY. + * \hideinitializer + */ +#define OTG_ENABLE_PHY() (OTG->PHYCTL |= OTG_PHYCTL_OTGPHYEN_Msk) + +/** + * @brief This macro is used to disable USB PHY + * @param None + * @return None + * @details This macro will clear OTGPHYEN bit of OTG_PHYCTL register to disable USB PHY. + * \hideinitializer + */ +#define OTG_DISABLE_PHY() (OTG->PHYCTL &= ~OTG_PHYCTL_OTGPHYEN_Msk) + +/** + * @brief This macro is used to enable ID detection function + * @param None + * @return None + * @details This macro will set IDDETEN bit of OTG_PHYCTL register to enable ID detection function. + * \hideinitializer + */ +#define OTG_ENABLE_ID_DETECT() (OTG->PHYCTL |= OTG_PHYCTL_IDDETEN_Msk) + +/** + * @brief This macro is used to disable ID detection function + * @param None + * @return None + * @details This macro will clear IDDETEN bit of OTG_PHYCTL register to disable ID detection function. + * \hideinitializer + */ +#define OTG_DISABLE_ID_DETECT() (OTG->PHYCTL &= ~OTG_PHYCTL_IDDETEN_Msk) + +/** + * @brief This macro is used to enable OTG wake-up function + * @param None + * @return None + * @details This macro will set WKEN bit of OTG_CTL register to enable OTG wake-up function. + * \hideinitializer + */ +#define OTG_ENABLE_WAKEUP() (OTG->CTL |= OTG_CTL_WKEN_Msk) + +/** + * @brief This macro is used to disable OTG wake-up function + * @param None + * @return None + * @details This macro will clear WKEN bit of OTG_CTL register to disable OTG wake-up function. + * \hideinitializer + */ +#define OTG_DISABLE_WAKEUP() (OTG->CTL &= ~OTG_CTL_WKEN_Msk) + +/** + * @brief This macro is used to set the polarity of USB_VBUS_EN pin + * @param[in] u32Pol The polarity selection. Valid values are listed below. + * - \ref OTG_VBUS_EN_ACTIVE_HIGH + * - \ref OTG_VBUS_EN_ACTIVE_LOW + * @return None + * @details This macro is used to set the polarity of external USB VBUS power switch enable signal. + * \hideinitializer + */ +#define OTG_SET_VBUS_EN_POL(u32Pol) (OTG->PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBENPOL_Msk)) | ((u32Pol)<PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBSTSPOL_Msk)) | ((u32Pol)<INTEN |= (u32Mask)) + +/** + * @brief This macro is used to disable OTG related interrupts + * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref OTG_INTEN_ROLECHGIEN_Msk + * - \ref OTG_INTEN_VBEIEN_Msk + * - \ref OTG_INTEN_SRPFIEN_Msk + * - \ref OTG_INTEN_HNPFIEN_Msk + * - \ref OTG_INTEN_GOIDLEIEN_Msk + * - \ref OTG_INTEN_IDCHGIEN_Msk + * - \ref OTG_INTEN_PDEVIEN_Msk + * - \ref OTG_INTEN_HOSTIEN_Msk + * - \ref OTG_INTEN_BVLDCHGIEN_Msk + * - \ref OTG_INTEN_AVLDCHGIEN_Msk + * - \ref OTG_INTEN_VBCHGIEN_Msk + * - \ref OTG_INTEN_SECHGIEN_Msk + * - \ref OTG_INTEN_SRPDETIEN_Msk + * @return None + * @details This macro will disable OTG related interrupts specified by u32Mask parameter. + * \hideinitializer + */ +#define OTG_DISABLE_INT(u32Mask) (OTG->INTEN &= ~(u32Mask)) + +/** + * @brief This macro is used to get OTG related interrupt flags + * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref OTG_INTSTS_ROLECHGIF_Msk + * - \ref OTG_INTSTS_VBEIF_Msk + * - \ref OTG_INTSTS_SRPFIF_Msk + * - \ref OTG_INTSTS_HNPFIF_Msk + * - \ref OTG_INTSTS_GOIDLEIF_Msk + * - \ref OTG_INTSTS_IDCHGIF_Msk + * - \ref OTG_INTSTS_PDEVIF_Msk + * - \ref OTG_INTSTS_HOSTIF_Msk + * - \ref OTG_INTSTS_BVLDCHGIF_Msk + * - \ref OTG_INTSTS_AVLDCHGIF_Msk + * - \ref OTG_INTSTS_VBCHGIF_Msk + * - \ref OTG_INTSTS_SECHGIF_Msk + * - \ref OTG_INTSTS_SRPDETIF_Msk + * @return Interrupt flags of selected sources. + * @details This macro will return OTG related interrupt flags specified by u32Mask parameter. + * \hideinitializer + */ +#define OTG_GET_INT_FLAG(u32Mask) (OTG->INTSTS & (u32Mask)) + +/** + * @brief This macro is used to clear OTG related interrupt flags + * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref OTG_INTSTS_ROLECHGIF_Msk + * - \ref OTG_INTSTS_VBEIF_Msk + * - \ref OTG_INTSTS_SRPFIF_Msk + * - \ref OTG_INTSTS_HNPFIF_Msk + * - \ref OTG_INTSTS_GOIDLEIF_Msk + * - \ref OTG_INTSTS_IDCHGIF_Msk + * - \ref OTG_INTSTS_PDEVIF_Msk + * - \ref OTG_INTSTS_HOSTIF_Msk + * - \ref OTG_INTSTS_BVLDCHGIF_Msk + * - \ref OTG_INTSTS_AVLDCHGIF_Msk + * - \ref OTG_INTSTS_VBCHGIF_Msk + * - \ref OTG_INTSTS_SECHGIF_Msk + * - \ref OTG_INTSTS_SRPDETIF_Msk + * @return None + * @details This macro will clear OTG related interrupt flags specified by u32Mask parameter. + * \hideinitializer + */ +#define OTG_CLR_INT_FLAG(u32Mask) (OTG->INTSTS = (u32Mask)) + +/** + * @brief This macro is used to get OTG related status + * @param[in] u32Mask The combination of user specified source. Valid values are listed below. + * - \ref OTG_STATUS_OVERCUR_Msk + * - \ref OTG_STATUS_IDSTS_Msk + * - \ref OTG_STATUS_SESSEND_Msk + * - \ref OTG_STATUS_BVLD_Msk + * - \ref OTG_STATUS_AVLD_Msk + * - \ref OTG_STATUS_VBUSVLD_Msk + * @return The user specified status. + * @details This macro will return OTG related status specified by u32Mask parameter. + * \hideinitializer + */ +#define OTG_GET_STATUS(u32Mask) (OTG->STATUS & (u32Mask)) + + + +/*@}*/ /* end of group OTG_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group OTG_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + + +#ifdef __cplusplus +} +#endif + + +#endif /*__NU_OTG_H__ */ + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_pdma.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_pdma.h new file mode 100644 index 0000000000000000000000000000000000000000..8579994db78534d01c2b29ac62536055fcbb52fa --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_pdma.h @@ -0,0 +1,391 @@ +/**************************************************************************//** + * @file nu_pdma.h + * @version V1.00 + * @brief M480 series PDMA driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_PDMA_H__ +#define __NU_PDMA_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup PDMA_Driver PDMA Driver + @{ +*/ + +/** @addtogroup PDMA_EXPORTED_CONSTANTS PDMA Exported Constants + @{ +*/ +#define PDMA_CH_MAX 16UL /*!< Specify Maximum Channels of PDMA \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Operation Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define PDMA_OP_STOP 0x00000000UL /*!INTSTS)) + +/** + * @brief Get Transfer Done Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @return None + * + * @details Get the transfer done Interrupt status. + * \hideinitializer + */ +#define PDMA_GET_TD_STS(pdma) ((uint32_t)(pdma->TDSTS)) + +/** + * @brief Clear Transfer Done Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @param[in] u32Mask The channel mask + * + * @return None + * + * @details Clear the transfer done Interrupt status. + * \hideinitializer + */ +#define PDMA_CLR_TD_FLAG(pdma,u32Mask) ((uint32_t)(pdma->TDSTS = (u32Mask))) + +/** + * @brief Get Target Abort Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @return None + * + * @details Get the target abort Interrupt status. + * \hideinitializer + */ +#define PDMA_GET_ABORT_STS(pdma) ((uint32_t)(pdma->ABTSTS)) + +/** + * @brief Clear Target Abort Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @param[in] u32Mask The channel mask + * + * @return None + * + * @details Clear the target abort Interrupt status. + * \hideinitializer + */ +#define PDMA_CLR_ABORT_FLAG(pdma,u32Mask) ((uint32_t)(pdma->ABTSTS = (u32Mask))) + +/** + * @brief Get Alignment Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @return None + * + * @details Get Alignment Interrupt status. + * \hideinitializer + */ +#define PDMA_GET_ALIGN_STS(pdma) ((uint32_t)(PDMA->ALIGN)) + +/** + * @brief Clear Alignment Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Mask The channel mask + * + * @return None + * + * @details Clear the Alignment Interrupt status. + * \hideinitializer + */ +#define PDMA_CLR_ALIGN_FLAG(pdma,u32Mask) ((uint32_t)(pdma->ALIGN = (u32Mask))) + +/** + * @brief Clear Timeout Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details Clear the selected channel timeout interrupt status. + * \hideinitializer + */ +#define PDMA_CLR_TMOUT_FLAG(pdma,u32Ch) ((uint32_t)(pdma->INTSTS = (1 << ((u32Ch) + 8)))) + +/** + * @brief Check Channel Status + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @retval 0 Idle state + * @retval 1 Busy state + * + * @details Check the selected channel is busy or not. + * \hideinitializer + */ +#define PDMA_IS_CH_BUSY(pdma,u32Ch) ((uint32_t)(pdma->TRGSTS & (1 << (u32Ch)))? 1 : 0) + +/** + * @brief Set Source Address + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Addr The selected address + * + * @return None + * + * @details This macro set the selected channel source address. + * \hideinitializer + */ +#define PDMA_SET_SRC_ADDR(pdma,u32Ch, u32Addr) ((uint32_t)(pdma->DSCT[(u32Ch)].SA = (u32Addr))) + +/** + * @brief Set Destination Address + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Addr The selected address + * + * @return None + * + * @details This macro set the selected channel destination address. + * \hideinitializer + */ +#define PDMA_SET_DST_ADDR(pdma,u32Ch, u32Addr) ((uint32_t)(pdma->DSCT[(u32Ch)].DA = (u32Addr))) + +/** + * @brief Set Transfer Count + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32TransCount Transfer Count + * + * @return None + * + * @details This macro set the selected channel transfer count. + * \hideinitializer + */ +#define PDMA_SET_TRANS_CNT(pdma,u32Ch, u32TransCount) ((uint32_t)(pdma->DSCT[(u32Ch)].CTL=(pdma->DSCT[(u32Ch)].CTL&~PDMA_DSCT_CTL_TXCNT_Msk)|(((u32TransCount)-1) << PDMA_DSCT_CTL_TXCNT_Pos))) + +/** + * @brief Set Scatter-gather descriptor Address + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Addr The descriptor address + * + * @return None + * + * @details This macro set the selected channel scatter-gather descriptor address. + * \hideinitializer + */ +#define PDMA_SET_SCATTER_DESC(pdma,u32Ch, u32Addr) ((uint32_t)(pdma->DSCT[(u32Ch)].NEXT = (u32Addr) - (pdma->SCATBA))) + +/** + * @brief Stop the channel + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details This macro stop the selected channel. + * \hideinitializer + */ +#define PDMA_STOP(pdma,u32Ch) ((uint32_t)(pdma->PAUSE = (1 << (u32Ch)))) + +/** + * @brief Pause the channel + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details This macro pause the selected channel. + * \hideinitializer + */ +#define PDMA_PAUSE(pdma,u32Ch) ((uint32_t)(pdma->PAUSE = (1 << (u32Ch)))) + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define PDMA functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +void PDMA_Open(PDMA_T * pdma,uint32_t u32Mask); +void PDMA_Close(PDMA_T * pdma); +void PDMA_SetTransferCnt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount); +void PDMA_SetTransferAddr(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl); +void PDMA_SetTransferMode(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr); +void PDMA_SetBurstType(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize); +void PDMA_EnableTimeout(PDMA_T * pdma,uint32_t u32Mask); +void PDMA_DisableTimeout(PDMA_T * pdma,uint32_t u32Mask); +void PDMA_SetTimeOut(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt); +void PDMA_Trigger(PDMA_T * pdma,uint32_t u32Ch); +void PDMA_EnableInt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Mask); +void PDMA_DisableInt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Mask); +void PDMA_SetStride(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32DestLen, uint32_t u32SrcLen, uint32_t u32TransCount); +void PDMA_SetRepeat(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32DestInterval, uint32_t u32SrcInterval, uint32_t u32RepeatCount); + + +/*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group PDMA_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_PDMA_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_qei.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_qei.h new file mode 100644 index 0000000000000000000000000000000000000000..217d506fd2a42100a8587aeaea05694ef68c7826 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_qei.h @@ -0,0 +1,390 @@ +/**************************************************************************//** + * @file nu_qei.h + * @version V3.00 + * @brief Quadrature Encoder Interface (QEI) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __NU_QEI_H__ +#define __NU_QEI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup QEI_Driver QEI Driver + @{ +*/ + +/** @addtogroup QEI_EXPORTED_CONSTANTS QEI Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* QEI counting mode selection constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define QEI_CTL_X4_FREE_COUNTING_MODE (0x0<CTL &= (~QEI_CTL_CMPEN_Msk)) + +/** + * @brief Enable QEI compare function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro enable QEI counter compare function. + * \hideinitializer + */ +#define QEI_ENABLE_CNT_CMP(qei) ((qei)->CTL |= QEI_CTL_CMPEN_Msk) + +/** + * @brief Disable QEI index latch function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro disable QEI index trigger counter latch function. + * \hideinitializer + */ +#define QEI_DISABLE_INDEX_LATCH(qei) ((qei)->CTL &= (~QEI_CTL_IDXLATEN_Msk)) + +/** + * @brief Enable QEI index latch function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro enable QEI index trigger counter latch function. + * \hideinitializer + */ +#define QEI_ENABLE_INDEX_LATCH(qei) ((qei)->CTL |= QEI_CTL_IDXLATEN_Msk) + +/** + * @brief Disable QEI index reload function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro disable QEI index trigger counter reload function. + * \hideinitializer + */ +#define QEI_DISABLE_INDEX_RELOAD(qei) ((qei)->CTL &= (~QEI_CTL_IDXRLDEN_Msk)) + +/** + * @brief Enable QEI index reload function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro enable QEI index trigger counter reload function. + * \hideinitializer + */ +#define QEI_ENABLE_INDEX_RELOAD(qei) ((qei)->CTL |= QEI_CTL_IDXRLDEN_Msk) + +/** + * @brief Disable QEI input + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32InputType Input signal type. + * - \ref QEI_CTL_CHAEN_Msk : QEA input + * - \ref QEI_CTL_CHAEN_Msk : QEB input + * - \ref QEI_CTL_IDXEN_Msk : IDX input + * @return None + * @details This macro disable specified QEI signal input. + * \hideinitializer + */ +#define QEI_DISABLE_INPUT(qei, u32InputType) ((qei)->CTL &= ~(u32InputType)) + +/** + * @brief Enable QEI input + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32InputType Input signal type . + * - \ref QEI_CTL_CHAEN_Msk : QEA input + * - \ref QEI_CTL_CHBEN_Msk : QEB input + * - \ref QEI_CTL_IDXEN_Msk : IDX input + * @return None + * @details This macro enable specified QEI signal input. + * \hideinitializer + */ +#define QEI_ENABLE_INPUT(qei, u32InputType) ((qei)->CTL |= (u32InputType)) + +/** + * @brief Disable inverted input polarity + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32InputType Input signal type . + * - \ref QEI_CTL_CHAINV_Msk : QEA Input + * - \ref QEI_CTL_CHBINV_Msk : QEB Input + * - \ref QEI_CTL_IDXINV_Msk : IDX Input + * @return None + * @details This macro disable specified QEI signal inverted input polarity. + * \hideinitializer + */ +#define QEI_DISABLE_INPUT_INV(qei, u32InputType) ((qei)->CTL &= ~(u32InputType)) + +/** + * @brief Enable inverted input polarity + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32InputType Input signal type. + * - \ref QEI_CTL_CHAINV_Msk : QEA Input + * - \ref QEI_CTL_CHBINV_Msk : QEB Input + * - \ref QEI_CTL_IDXINV_Msk : IDX Input + * @return None + * @details This macro inverse specified QEI signal input polarity. + * \hideinitializer + */ +#define QEI_ENABLE_INPUT_INV(qei, u32InputType) ((qei)->CTL |= (u32InputType)) + +/** + * @brief Disable QEI interrupt + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. + * - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt + * - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt + * - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt + * - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt + * @return None + * @details This macro disable specified QEI interrupt. + * \hideinitializer + */ +#define QEI_DISABLE_INT(qei, u32IntSel) ((qei)->CTL &= ~(u32IntSel)) + +/** + * @brief Enable QEI interrupt + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. + * - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt + * - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt + * - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt + * - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt + * @return None + * @details This macro enable specified QEI interrupt. + * \hideinitializer + */ +#define QEI_ENABLE_INT(qei, u32IntSel) ((qei)->CTL |= (u32IntSel)) + +/** + * @brief Disable QEI noise filter + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro disable QEI noise filter function. + * \hideinitializer + */ +#define QEI_DISABLE_NOISE_FILTER(qei) ((qei)->CTL |= QEI_CTL_NFDIS_Msk) + +/** + * @brief Enable QEI noise filter + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32ClkSel The sampling frequency of the noise filter clock. + * - \ref QEI_CTL_NFCLKSEL_DIV1 + * - \ref QEI_CTL_NFCLKSEL_DIV2 + * - \ref QEI_CTL_NFCLKSEL_DIV4 + * - \ref QEI_CTL_NFCLKSEL_DIV16 + * - \ref QEI_CTL_NFCLKSEL_DIV32 + * - \ref QEI_CTL_NFCLKSEL_DIV64 + * @return None + * @details This macro enable QEI noise filter function and select noise filter clock. + * \hideinitializer + */ +#define QEI_ENABLE_NOISE_FILTER(qei, u32ClkSel) ((qei)->CTL = ((qei)->CTL & (~(QEI_CTL_NFDIS_Msk|QEI_CTL_NFCLKSEL_Msk))) | (u32ClkSel)) + +/** + * @brief Get QEI counter value + * @param[in] qei The pointer of the specified QEI module. + * @return QEI pulse counter register value. + * @details This macro get QEI pulse counter value. + * \hideinitializer + */ +#define QEI_GET_CNT_VALUE(qei) ((qei)->CNT) + +/** + * @brief Get QEI counting direction + * @param[in] qei The pointer of the specified QEI module. + * @retval 0 QEI counter is in down-counting. + * @retval 1 QEI counter is in up-counting. + * @details This macro get QEI counting direction. + * \hideinitializer + */ +#define QEI_GET_DIR(qei) (((qei)->STATUS & (QEI_STATUS_DIRF_Msk))?1:0) + +/** + * @brief Get QEI counter hold value + * @param[in] qei The pointer of the specified QEI module. + * @return QEI pulse counter hold register value. + * @details This macro get QEI pulse counter hold value, which is updated with counter value in hold counter value control. + * \hideinitializer + */ +#define QEI_GET_HOLD_VALUE(qei) ((qei)->CNTHOLD) + +/** + * @brief Get QEI counter index latch value + * @param[in] qei The pointer of the specified QEI module. + * @return QEI pulse counter index latch value + * @details This macro get QEI pulse counter index latch value, which is updated with counter value when the index is detected. + * \hideinitializer + */ +#define QEI_GET_INDEX_LATCH_VALUE(qei) ((qei)->CNTLATCH) + +/** + * @brief Set QEI counter index latch value + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Val The latch value. + * @return QEI pulse counter index latch value + * @details This macro set QEI pulse counter index latch value, which is updated with counter value when the index is detected. + * \hideinitializer + */ +#define QEI_SET_INDEX_LATCH_VALUE(qei,u32Val) ((qei)->CNTLATCH = (u32Val)) + +/** + * @brief Get QEI interrupt flag status + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. +* - \ref QEI_STATUS_DIRF_Msk : Counting direction flag + * - \ref QEI_STATUS_DIRCHGF_Msk : Direction change flag + * - \ref QEI_STATUS_OVUNF_Msk : Counter overflow or underflow flag + * - \ref QEI_STATUS_CMPF_Msk : Compare-match flag + * - \ref QEI_STATUS_IDXF_Msk : Index detected flag + * @retval 0 QEI specified interrupt flag is not set. + * @retval 1 QEI specified interrupt flag is set. + * @details This macro get QEI specified interrupt flag status. + * \hideinitializer + */ +#define QEI_GET_INT_FLAG(qei, u32IntSel) (((qei)->STATUS & (u32IntSel))?1:0) + + +/** + * @brief Clear QEI interrupt flag + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. + * - \ref QEI_STATUS_DIRCHGF_Msk : Direction change flag + * - \ref QEI_STATUS_OVUNF_Msk : Counter overflow or underflow flag + * - \ref QEI_STATUS_CMPF_Msk : Compare-match flag + * - \ref QEI_STATUS_IDXF_Msk : Index detected flag + * @return None + * @details This macro clear QEI specified interrupt flag. + * \hideinitializer + */ +#define QEI_CLR_INT_FLAG(qei, u32IntSel) ((qei)->STATUS = (u32IntSel)) + +/** + * @brief Set QEI counter compare value + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Value The counter compare value. + * @return None + * @details This macro set QEI pulse counter compare value. + * \hideinitializer + */ +#define QEI_SET_CNT_CMP(qei, u32Value) ((qei)->CNTCMP = (u32Value)) + +/** + * @brief Set QEI counter value + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Value The counter compare value. + * @return None + * @details This macro set QEI pulse counter value. + * \hideinitializer + */ +#define QEI_SET_CNT_VALUE(qei, u32Value) ((qei)->CNT = (u32Value)) + +/** + * @brief Enable QEI counter hold mode + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Type The triggered type. + * - \ref QEI_CTL_HOLDCNT_Msk : Hold QEI_CNT control + * - \ref QEI_CTL_HOLDTMR0_Msk : Hold QEI_CNT by Timer0 + * - \ref QEI_CTL_HOLDTMR1_Msk : Hold QEI_CNT by Timer1 + * - \ref QEI_CTL_HOLDTMR2_Msk : Hold QEI_CNT by Timer2 + * - \ref QEI_CTL_HOLDTMR3_Msk : Hold QEI_CNT by Timer3 + * @return None + * @details This macro enable QEI counter hold mode. + * \hideinitializer + */ +#define QEI_ENABLE_HOLD_TRG_SRC(qei, u32Type) ((qei)->CTL |= (u32Type)) + +/** + * @brief Disable QEI counter hold mode + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Type The triggered type. + * - \ref QEI_CTL_HOLDCNT_Msk : Hold QEI_CNT control + * - \ref QEI_CTL_HOLDTMR0_Msk : Hold QEI_CNT by Timer0 + * - \ref QEI_CTL_HOLDTMR1_Msk : Hold QEI_CNT by Timer1 + * - \ref QEI_CTL_HOLDTMR2_Msk : Hold QEI_CNT by Timer2 + * - \ref QEI_CTL_HOLDTMR3_Msk : Hold QEI_CNT by Timer3 + * @return None + * @details This macro disable QEI counter hold mode. + * \hideinitializer + */ +#define QEI_DISABLE_HOLD_TRG_SRC(qei, u32Type) ((qei)->CTL &= ~(u32Type)) + +/** + * @brief Set QEI maximum count value + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Value The counter maximum value. + * @return QEI maximum count value + * @details This macro set QEI maximum count value. + * \hideinitializer + */ +#define QEI_SET_CNT_MAX(qei, u32Value) ((qei)->CNTMAX = (u32Value)) + +/** + * @brief Set QEI counting mode + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Mode QEI counting mode. + * - \ref QEI_CTL_X4_FREE_COUNTING_MODE + * - \ref QEI_CTL_X2_FREE_COUNTING_MODE + * - \ref QEI_CTL_X4_COMPARE_COUNTING_MODE + * - \ref QEI_CTL_X2_COMPARE_COUNTING_MODE + * @return None + * @details This macro set QEI counting mode. + * \hideinitializer + */ +#define QEI_SET_CNT_MODE(qei, u32Mode) ((qei)->CTL = ((qei)->CTL & (~QEI_CTL_MODE_Msk)) | (u32Mode)) + + +void QEI_Close(QEI_T* qei); +void QEI_DisableInt(QEI_T* qei, uint32_t u32IntSel); +void QEI_EnableInt(QEI_T* qei, uint32_t u32IntSel); +void QEI_Open(QEI_T* qei, uint32_t u32Mode, uint32_t u32Value); +void QEI_Start(QEI_T* qei); +void QEI_Stop(QEI_T* qei); + + +/*@}*/ /* end of group QEI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group QEI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_QEI_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_qspi.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_qspi.h new file mode 100644 index 0000000000000000000000000000000000000000..64114525e1e151a1798cb89a34120a24cd87ca0d --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_qspi.h @@ -0,0 +1,357 @@ +/**************************************************************************//** + * @file nu_qspi.h + * @version V3.00 + * @brief M480 series QSPI driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __NU_QSPI_H__ +#define __NU_QSPI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup QSPI_Driver QSPI Driver + @{ +*/ + +/** @addtogroup QSPI_EXPORTED_CONSTANTS QSPI Exported Constants + @{ +*/ + +#define QSPI_MODE_0 (QSPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 \hideinitializer */ +#define QSPI_MODE_1 (QSPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 \hideinitializer */ +#define QSPI_MODE_2 (QSPI_CTL_CLKPOL_Msk | QSPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 \hideinitializer */ +#define QSPI_MODE_3 (QSPI_CTL_CLKPOL_Msk | QSPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 \hideinitializer */ + +#define QSPI_SLAVE (QSPI_CTL_SLAVE_Msk) /*!< Set as slave \hideinitializer */ +#define QSPI_MASTER (0x0U) /*!< Set as master \hideinitializer */ + +#define QSPI_SS (QSPI_SSCTL_SS_Msk) /*!< Set SS \hideinitializer */ +#define QSPI_SS_ACTIVE_HIGH (QSPI_SSCTL_SSACTPOL_Msk) /*!< SS active high \hideinitializer */ +#define QSPI_SS_ACTIVE_LOW (0x0U) /*!< SS active low \hideinitializer */ + +/* QSPI Interrupt Mask */ +#define QSPI_UNIT_INT_MASK (0x001U) /*!< Unit transfer interrupt mask \hideinitializer */ +#define QSPI_SSACT_INT_MASK (0x002U) /*!< Slave selection signal active interrupt mask \hideinitializer */ +#define QSPI_SSINACT_INT_MASK (0x004U) /*!< Slave selection signal inactive interrupt mask \hideinitializer */ +#define QSPI_SLVUR_INT_MASK (0x008U) /*!< Slave under run interrupt mask \hideinitializer */ +#define QSPI_SLVBE_INT_MASK (0x010U) /*!< Slave bit count error interrupt mask \hideinitializer */ +#define QSPI_TXUF_INT_MASK (0x040U) /*!< Slave TX underflow interrupt mask \hideinitializer */ +#define QSPI_FIFO_TXTH_INT_MASK (0x080U) /*!< FIFO TX threshold interrupt mask \hideinitializer */ +#define QSPI_FIFO_RXTH_INT_MASK (0x100U) /*!< FIFO RX threshold interrupt mask \hideinitializer */ +#define QSPI_FIFO_RXOV_INT_MASK (0x200U) /*!< FIFO RX overrun interrupt mask \hideinitializer */ +#define QSPI_FIFO_RXTO_INT_MASK (0x400U) /*!< FIFO RX time-out interrupt mask \hideinitializer */ + +/* QSPI Status Mask */ +#define QSPI_BUSY_MASK (0x01U) /*!< Busy status mask \hideinitializer */ +#define QSPI_RX_EMPTY_MASK (0x02U) /*!< RX empty status mask \hideinitializer */ +#define QSPI_RX_FULL_MASK (0x04U) /*!< RX full status mask \hideinitializer */ +#define QSPI_TX_EMPTY_MASK (0x08U) /*!< TX empty status mask \hideinitializer */ +#define QSPI_TX_FULL_MASK (0x10U) /*!< TX full status mask \hideinitializer */ +#define QSPI_TXRX_RESET_MASK (0x20U) /*!< TX or RX reset status mask \hideinitializer */ +#define QSPI_QSPIEN_STS_MASK (0x40U) /*!< QSPIEN status mask \hideinitializer */ +#define QSPI_SSLINE_STS_MASK (0x80U) /*!< QSPIx_SS line status mask \hideinitializer */ + +/*@}*/ /* end of group QSPI_EXPORTED_CONSTANTS */ + + +/** @addtogroup QSPI_EXPORTED_FUNCTIONS QSPI Exported Functions + @{ +*/ + +/** + * @brief Clear the unit transfer interrupt flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Write 1 to UNITIF bit of QSPI_STATUS register to clear the unit transfer interrupt flag. + * \hideinitializer + */ +#define QSPI_CLR_UNIT_TRANS_INT_FLAG(qspi) ((qspi)->STATUS = QSPI_STATUS_UNITIF_Msk) + +/** + * @brief Trigger RX PDMA function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set RXPDMAEN bit of QSPI_PDMACTL register to enable RX PDMA transfer function. + * \hideinitializer + */ +#define QSPI_TRIGGER_RX_PDMA(qspi) ((qspi)->PDMACTL |= QSPI_PDMACTL_RXPDMAEN_Msk) + +/** + * @brief Trigger TX PDMA function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set TXPDMAEN bit of QSPI_PDMACTL register to enable TX PDMA transfer function. + * \hideinitializer + */ +#define QSPI_TRIGGER_TX_PDMA(qspi) ((qspi)->PDMACTL |= QSPI_PDMACTL_TXPDMAEN_Msk) + +/** + * @brief Disable RX PDMA transfer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear RXPDMAEN bit of QSPI_PDMACTL register to disable RX PDMA transfer function. + * \hideinitializer + */ +#define QSPI_DISABLE_RX_PDMA(qspi) ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Disable TX PDMA transfer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear TXPDMAEN bit of QSPI_PDMACTL register to disable TX PDMA transfer function. + * \hideinitializer + */ +#define QSPI_DISABLE_TX_PDMA(qspi) ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Get the count of available data in RX FIFO. + * @param[in] qspi The pointer of the specified QSPI module. + * @return The count of available data in RX FIFO. + * @details Read RXCNT (QSPI_STATUS[27:24]) to get the count of available data in RX FIFO. + * \hideinitializer + */ +#define QSPI_GET_RX_FIFO_COUNT(qspi) (((qspi)->STATUS & QSPI_STATUS_RXCNT_Msk) >> QSPI_STATUS_RXCNT_Pos) + +/** + * @brief Get the RX FIFO empty flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @retval 0 RX FIFO is not empty. + * @retval 1 RX FIFO is empty. + * @details Read RXEMPTY bit of QSPI_STATUS register to get the RX FIFO empty flag. + * \hideinitializer + */ +#define QSPI_GET_RX_FIFO_EMPTY_FLAG(qspi) (((qspi)->STATUS & QSPI_STATUS_RXEMPTY_Msk)>>QSPI_STATUS_RXEMPTY_Pos) + +/** + * @brief Get the TX FIFO empty flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @retval 0 TX FIFO is not empty. + * @retval 1 TX FIFO is empty. + * @details Read TXEMPTY bit of QSPI_STATUS register to get the TX FIFO empty flag. + * \hideinitializer + */ +#define QSPI_GET_TX_FIFO_EMPTY_FLAG(qspi) (((qspi)->STATUS & QSPI_STATUS_TXEMPTY_Msk)>>QSPI_STATUS_TXEMPTY_Pos) + +/** + * @brief Get the TX FIFO full flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @retval 0 TX FIFO is not full. + * @retval 1 TX FIFO is full. + * @details Read TXFULL bit of QSPI_STATUS register to get the TX FIFO full flag. + * \hideinitializer + */ +#define QSPI_GET_TX_FIFO_FULL_FLAG(qspi) (((qspi)->STATUS & QSPI_STATUS_TXFULL_Msk)>>QSPI_STATUS_TXFULL_Pos) + +/** + * @brief Get the datum read from RX register. + * @param[in] qspi The pointer of the specified QSPI module. + * @return Data in RX register. + * @details Read QSPI_RX register to get the received datum. + * \hideinitializer + */ +#define QSPI_READ_RX(qspi) ((qspi)->RX) + +/** + * @brief Write datum to TX register. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32TxData The datum which user attempt to transfer through QSPI bus. + * @return None. + * @details Write u32TxData to QSPI_TX register. + * \hideinitializer + */ +#define QSPI_WRITE_TX(qspi, u32TxData) ((qspi)->TX = (u32TxData)) + +/** + * @brief Set QSPIx_SS pin to high state. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Disable automatic slave selection function and set QSPIx_SS pin to high state. + * \hideinitializer + */ +#define QSPI_SET_SS_HIGH(qspi) ((qspi)->SSCTL = ((qspi)->SSCTL & (~QSPI_SSCTL_AUTOSS_Msk)) | (QSPI_SSCTL_SSACTPOL_Msk | QSPI_SSCTL_SS_Msk)) + +/** + * @brief Set QSPIx_SS pin to low state. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Disable automatic slave selection function and set QSPIx_SS pin to low state. + * \hideinitializer + */ +#define QSPI_SET_SS_LOW(qspi) ((qspi)->SSCTL = ((qspi)->SSCTL & (~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SSACTPOL_Msk))) | QSPI_SSCTL_SS_Msk) + +/** + * @brief Enable Byte Reorder function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (QSPI_CTL[7:4]). + * \hideinitializer + */ +#define QSPI_ENABLE_BYTE_REORDER(qspi) ((qspi)->CTL |= QSPI_CTL_REORDER_Msk) + +/** + * @brief Disable Byte Reorder function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear REORDER bit field of QSPI_CTL register to disable Byte Reorder function. + * \hideinitializer + */ +#define QSPI_DISABLE_BYTE_REORDER(qspi) ((qspi)->CTL &= ~QSPI_CTL_REORDER_Msk) + +/** + * @brief Set the length of suspend interval. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15. + * @return None. + * @details Set the length of suspend interval according to u32SuspCycle. + * The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one QSPI bus clock cycle). + * \hideinitializer + */ +#define QSPI_SET_SUSPEND_CYCLE(qspi, u32SuspCycle) ((qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << QSPI_CTL_SUSPITV_Pos)) + +/** + * @brief Set the QSPI transfer sequence with LSB first. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set LSB bit of QSPI_CTL register to set the QSPI transfer sequence with LSB first. + * \hideinitializer + */ +#define QSPI_SET_LSB_FIRST(qspi) ((qspi)->CTL |= QSPI_CTL_LSB_Msk) + +/** + * @brief Set the QSPI transfer sequence with MSB first. + * @param[in] qspi The pointer of the specified SPI module. + * @return None. + * @details Clear LSB bit of QSPI_CTL register to set the QSPI transfer sequence with MSB first. + * \hideinitializer + */ +#define QSPI_SET_MSB_FIRST(qspi) ((qspi)->CTL &= ~QSPI_CTL_LSB_Msk) + +/** + * @brief Set the data width of a QSPI transaction. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Width The bit width of one transaction. + * @return None. + * @details The data width can be 8 ~ 32 bits. + * \hideinitializer + */ +#define QSPI_SET_DATA_WIDTH(qspi, u32Width) ((qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DWIDTH_Msk) | (((u32Width)&0x1F) << QSPI_CTL_DWIDTH_Pos)) + +/** + * @brief Get the QSPI busy state. + * @param[in] qspi The pointer of the specified QSPI module. + * @retval 0 QSPI controller is not busy. + * @retval 1 QSPI controller is busy. + * @details This macro will return the busy state of QSPI controller. + * \hideinitializer + */ +#define QSPI_IS_BUSY(qspi) ( ((qspi)->STATUS & QSPI_STATUS_BUSY_Msk)>>QSPI_STATUS_BUSY_Pos ) + +/** + * @brief Enable QSPI controller. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set QSPIEN (QSPI_CTL[0]) to enable QSPI controller. + * \hideinitializer + */ +#define QSPI_ENABLE(qspi) ((qspi)->CTL |= QSPI_CTL_QSPIEN_Msk) + +/** + * @brief Disable QSPI controller. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear QSPIEN (QSPI_CTL[0]) to disable QSPI controller. + * \hideinitializer + */ +#define QSPI_DISABLE(qspi) ((qspi)->CTL &= ~QSPI_CTL_QSPIEN_Msk) + +/** + * @brief Disable QSPI Dual IO function. + * @param[in] qspi is the base address of QSPI module. + * @return none + * \hideinitializer + */ +#define QSPI_DISABLE_DUAL_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_DUALIOEN_Msk ) + +/** + * @brief Enable Dual IO function and set QSPI Dual IO direction to input. + * @param[in] qspi is the base address of QSPI module. + * @return none + * \hideinitializer + */ +#define QSPI_ENABLE_DUAL_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DATDIR_Msk) | QSPI_CTL_DUALIOEN_Msk ) + +/** + * @brief Enable Dual IO function and set QSPI Dual IO direction to output. + * @param[in] qspi is the base address of QSPI module. + * @return none + * \hideinitializer + */ +#define QSPI_ENABLE_DUAL_OUTPUT_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_DATDIR_Msk | QSPI_CTL_DUALIOEN_Msk ) + +/** + * @brief Disable QSPI Dual IO function. + * @param[in] qspi is the base address of QSPI module. + * @return none + * \hideinitializer + */ +#define QSPI_DISABLE_QUAD_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_QUADIOEN_Msk ) + +/** + * @brief Set QSPI Quad IO direction to input. + * @param[in] qspi is the base address of QSPI module. + * @return none + * \hideinitializer + */ +#define QSPI_ENABLE_QUAD_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DATDIR_Msk) | QSPI_CTL_QUADIOEN_Msk ) + +/** + * @brief Set QSPI Quad IO direction to output. + * @param[in] qspi is the base address of QSPI module. + * @return none + * \hideinitializer + */ +#define QSPI_ENABLE_QUAD_OUTPUT_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_DATDIR_Msk | QSPI_CTL_QUADIOEN_Msk ) + + + + +/* Function prototype declaration */ +uint32_t QSPI_Open(QSPI_T *qspi, uint32_t u32MasterSlave, uint32_t u32QSPIMode, uint32_t u32DataWidth, uint32_t u32BusClock); +void QSPI_Close(QSPI_T *qspi); +void QSPI_ClearRxFIFO(QSPI_T *qspi); +void QSPI_ClearTxFIFO(QSPI_T *qspi); +void QSPI_DisableAutoSS(QSPI_T *qspi); +void QSPI_EnableAutoSS(QSPI_T *qspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel); +uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock); +void QSPI_SetFIFO(QSPI_T *qspi, uint32_t u32TxThreshold, uint32_t u32RxThreshold); +uint32_t QSPI_GetBusClock(QSPI_T *qspi); +void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask); +void QSPI_DisableInt(QSPI_T *qspi, uint32_t u32Mask); +uint32_t QSPI_GetIntFlag(QSPI_T *qspi, uint32_t u32Mask); +void QSPI_ClearIntFlag(QSPI_T *qspi, uint32_t u32Mask); +uint32_t QSPI_GetStatus(QSPI_T *qspi, uint32_t u32Mask); + + +/*@}*/ /* end of group QSPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group QSPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_rtc.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_rtc.h new file mode 100644 index 0000000000000000000000000000000000000000..f416519b67dc231c18d21c0a6c30a5e095f5d9e3 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_rtc.h @@ -0,0 +1,342 @@ +/**************************************************************************//** + * @file nu_rtc.h + * @version V3.00 + * @brief M480 series RTC driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_RTC_H__ +#define __NU_RTC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup RTC_Driver RTC Driver + @{ +*/ + +/** @addtogroup RTC_EXPORTED_CONSTANTS RTC Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Initial Keyword Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_INIT_KEY 0xA5EB1357UL /*!< RTC Initiation Key to make RTC leaving reset state \hideinitializer */ +#define RTC_WRITE_KEY 0x0000A965UL /*!< RTC Register Access Enable Key to enable RTC read/write accessible and kept 1024 RTC clock \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Time Attribute Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_CLOCK_12 0UL /*!< RTC as 12-hour time scale with AM and PM indication \hideinitializer */ +#define RTC_CLOCK_24 1UL /*!< RTC as 24-hour time scale \hideinitializer */ +#define RTC_AM 1UL /*!< RTC as AM indication \hideinitializer */ +#define RTC_PM 2UL /*!< RTC as PM indication \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Tick Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_TICK_1_SEC 0x0UL /*!< RTC time tick period is 1 second \hideinitializer */ +#define RTC_TICK_1_2_SEC 0x1UL /*!< RTC time tick period is 1/2 second \hideinitializer */ +#define RTC_TICK_1_4_SEC 0x2UL /*!< RTC time tick period is 1/4 second \hideinitializer */ +#define RTC_TICK_1_8_SEC 0x3UL /*!< RTC time tick period is 1/8 second \hideinitializer */ +#define RTC_TICK_1_16_SEC 0x4UL /*!< RTC time tick period is 1/16 second \hideinitializer */ +#define RTC_TICK_1_32_SEC 0x5UL /*!< RTC time tick period is 1/32 second \hideinitializer */ +#define RTC_TICK_1_64_SEC 0x6UL /*!< RTC time tick period is 1/64 second \hideinitializer */ +#define RTC_TICK_1_128_SEC 0x7UL /*!< RTC time tick period is 1/128 second \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Day of Week Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_SUNDAY 0x0UL /*!< Day of the Week is Sunday \hideinitializer */ +#define RTC_MONDAY 0x1UL /*!< Day of the Week is Monday \hideinitializer */ +#define RTC_TUESDAY 0x2UL /*!< Day of the Week is Tuesday \hideinitializer */ +#define RTC_WEDNESDAY 0x3UL /*!< Day of the Week is Wednesday \hideinitializer */ +#define RTC_THURSDAY 0x4UL /*!< Day of the Week is Thursday \hideinitializer */ +#define RTC_FRIDAY 0x5UL /*!< Day of the Week is Friday \hideinitializer */ +#define RTC_SATURDAY 0x6UL /*!< Day of the Week is Saturday \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Miscellaneous Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_WAIT_COUNT 0xFFFFFFFFUL /*!< Initial Time-out Value \hideinitializer */ +#define RTC_YEAR2000 2000UL /*!< RTC Reference for compute year data \hideinitializer */ +#define RTC_FCR_REFERENCE 32761UL /*!< RTC Reference for frequency compensation \hideinitializer */ + + +#define RTC_TAMPER0_SELECT (0x1ul << 0) /*!< Select Tamper 0 \hideinitializer */ +#define RTC_TAMPER1_SELECT (0x1ul << 1) /*!< Select Tamper 1 \hideinitializer */ +#define RTC_TAMPER2_SELECT (0x1ul << 2) /*!< Select Tamper 2 \hideinitializer */ +#define RTC_TAMPER3_SELECT (0x1ul << 3) /*!< Select Tamper 3 \hideinitializer */ +#define RTC_TAMPER4_SELECT (0x1ul << 4) /*!< Select Tamper 4 \hideinitializer */ +#define RTC_TAMPER5_SELECT (0x1ul << 5) /*!< Select Tamper 5 \hideinitializer */ +#define MAX_TAMPER_PIN_NUM 6ul /*!< Tamper Pin number \hideinitializer */ + +#define RTC_TAMPER_HIGH_LEVEL_DETECT 1ul /*!< Tamper pin detect voltage level is high \hideinitializer */ +#define RTC_TAMPER_LOW_LEVEL_DETECT 0ul /*!< Tamper pin detect voltage level is low \hideinitializer */ + +#define RTC_TAMPER_DEBOUNCE_ENABLE 1ul /*!< Enable RTC tamper pin de-bounce function \hideinitializer */ +#define RTC_TAMPER_DEBOUNCE_DISABLE 0ul /*!< Disable RTC tamper pin de-bounce function \hideinitializer */ + +#define RTC_PAIR0_SELECT (0x1ul << 0) /*!< Select Pair 0 \hideinitializer */ +#define RTC_PAIR1_SELECT (0x1ul << 1) /*!< Select Pair 1 \hideinitializer */ +#define RTC_PAIR2_SELECT (0x1ul << 2) /*!< Select Pair 2 \hideinitializer */ +#define MAX_PAIR_NUM 3ul /*!< Pair number \hideinitializer */ + +#define RTC_2POW10_CLK (0x0 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 RTC clock cycles \hideinitializer */ +#define RTC_2POW11_CLK (0x1 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 2 RTC clock cycles \hideinitializer */ +#define RTC_2POW12_CLK (0x2 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 4 RTC clock cycles \hideinitializer */ +#define RTC_2POW13_CLK (0x3 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 6 RTC clock cycles \hideinitializer */ +#define RTC_2POW14_CLK (0x4 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 8 RTC clock cycles \hideinitializer */ +#define RTC_2POW15_CLK (0x5 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 16 RTC clock cycles \hideinitializer */ +#define RTC_2POW16_CLK (0x6 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 32 RTC clock cycles \hideinitializer */ +#define RTC_2POW17_CLK (0x7 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 64 RTC clock cycles \hideinitializer */ + +#define REF_RANDOM_PATTERN 0x0 /*!< The new reference pattern is generated by random number generator when the reference pattern run out \hideinitializer */ +#define REF_PREVIOUS_PATTERN 0x1 /*!< The new reference pattern is repeated previous random value when the reference pattern run out \hideinitializer */ +#define REF_SEED 0x3 /*!< The new reference pattern is repeated from SEED (RTC_TAMPSEED[31:0]) when the reference pattern run out \hideinitializer */ + +/*@}*/ /* end of group RTC_EXPORTED_CONSTANTS */ + + +/** @addtogroup RTC_EXPORTED_STRUCTS RTC Exported Structs + @{ +*/ +/** + * @details RTC define Time Data Struct + */ +typedef struct +{ + uint32_t u32Year; /*!< Year value */ + uint32_t u32Month; /*!< Month value */ + uint32_t u32Day; /*!< Day value */ + uint32_t u32DayOfWeek; /*!< Day of week value */ + uint32_t u32Hour; /*!< Hour value */ + uint32_t u32Minute; /*!< Minute value */ + uint32_t u32Second; /*!< Second value */ + uint32_t u32TimeScale; /*!< 12-Hour, 24-Hour */ + uint32_t u32AmPm; /*!< Only Time Scale select 12-hr used */ +} S_RTC_TIME_DATA_T; + +/*@}*/ /* end of group RTC_EXPORTED_STRUCTS */ + + +/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions + @{ +*/ + +/** + * @brief Indicate is Leap Year or not + * + * @param None + * + * @retval 0 This year is not a leap year + * @retval 1 This year is a leap year + * + * @details According to current date, return this year is leap year or not. + * \hideinitializer + */ +#define RTC_IS_LEAP_YEAR() (RTC->LEAPYEAR & RTC_LEAPYEAR_LEAPYEAR_Msk ? 1:0) + +/** + * @brief Clear RTC Alarm Interrupt Flag + * + * @param None + * + * @return None + * + * @details This macro is used to clear RTC alarm interrupt flag. + * \hideinitializer + */ +#define RTC_CLEAR_ALARM_INT_FLAG() (RTC->INTSTS = RTC_INTSTS_ALMIF_Msk) + +/** + * @brief Clear RTC Tick Interrupt Flag + * + * @param None + * + * @return None + * + * @details This macro is used to clear RTC tick interrupt flag. + * \hideinitializer + */ +#define RTC_CLEAR_TICK_INT_FLAG() (RTC->INTSTS = RTC_INTSTS_TICKIF_Msk) + +/** + * @brief Clear RTC Tamper Interrupt Flag + * + * @param u32TamperFlag Tamper interrupt flag. It consists of: \n + * - \ref RTC_INTSTS_TAMP0IF_Msk \n + * - \ref RTC_INTSTS_TAMP1IF_Msk \n + * - \ref RTC_INTSTS_TAMP2IF_Msk \n + * - \ref RTC_INTSTS_TAMP3IF_Msk \n + * - \ref RTC_INTSTS_TAMP4IF_Msk \n + * - \ref RTC_INTSTS_TAMP5IF_Msk + * + * @return None + * + * @details This macro is used to clear RTC snooper pin interrupt flag. + * \hideinitializer + */ +#define RTC_CLEAR_TAMPER_INT_FLAG(u32TamperFlag) (RTC->INTSTS = (u32TamperFlag)) + +/** + * @brief Get RTC Alarm Interrupt Flag + * + * @param None + * + * @retval 0 RTC alarm interrupt did not occur + * @retval 1 RTC alarm interrupt occurred + * + * @details This macro indicates RTC alarm interrupt occurred or not. + * \hideinitializer + */ +#define RTC_GET_ALARM_INT_FLAG() ((RTC->INTSTS & RTC_INTSTS_ALMIF_Msk)? 1:0) + +/** + * @brief Get RTC Time Tick Interrupt Flag + * + * @param None + * + * @retval 0 RTC time tick interrupt did not occur + * @retval 1 RTC time tick interrupt occurred + * + * @details This macro indicates RTC time tick interrupt occurred or not. + * \hideinitializer + */ +#define RTC_GET_TICK_INT_FLAG() ((RTC->INTSTS & RTC_INTSTS_TICKIF_Msk)? 1:0) + +/** + * @brief Get RTC Tamper Interrupt Flag + * + * @param None + * + * @retval 0 RTC snooper pin interrupt did not occur + * @retval 1 RTC snooper pin interrupt occurred + * + * @details This macro indicates RTC snooper pin interrupt occurred or not. + * \hideinitializer + */ +#define RTC_GET_TAMPER_INT_FLAG() ((RTC->INTSTS & (0x3F00))? 1:0) + +/** + * @brief Get RTC TAMPER Interrupt Status + * + * @param None + * + * @retval RTC_INTSTS_TAMP0IF_Msk Tamper 0 interrupt flag is generated + * @retval RTC_INTSTS_TAMP1IF_Msk Tamper 1 interrupt flag is generated + * @retval RTC_INTSTS_TAMP2IF_Msk Tamper 2 interrupt flag is generated + * @retval RTC_INTSTS_TAMP3IF_Msk Tamper 3 interrupt flag is generated + * @retval RTC_INTSTS_TAMP4IF_Msk Tamper 4 interrupt flag is generated + * @retval RTC_INTSTS_TAMP5IF_Msk Tamper 5 interrupt flag is generated + * + * @details This macro indicates RTC snooper pin interrupt occurred or not. + * \hideinitializer + */ +#define RTC_GET_TAMPER_INT_STATUS() ((RTC->INTSTS & (0x3F00))) + +/** + * @brief Read Spare Register + * + * @param[in] u32RegNum The spare register number, 0~19. + * + * @return Spare register content + * + * @details Read the specify spare register content. + * @note The returned value is valid only when SPRRDY(SPRCTL[7] SPR Register Ready) bit is set. \n + * And its controlled by RTC Access Enable Register. + * \hideinitializer + */ +#define RTC_READ_SPARE_REGISTER(u32RegNum) (RTC->SPR[(u32RegNum)]) + +/** + * @brief Write Spare Register + * + * @param[in] u32RegNum The spare register number, 0~19. + * @param[in] u32RegValue The spare register value. + * + * @return None + * + * @details Write specify data to spare register. + * @note This macro is effect only when SPRRDY(SPRCTL[7] SPR Register Ready) bit is set. \n + * And its controlled by RTC Access Enable Register(RTC_RWEN). + * \hideinitializer + */ +#define RTC_WRITE_SPARE_REGISTER(u32RegNum, u32RegValue) (RTC->SPR[(u32RegNum)] = (u32RegValue)) + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void RTC_WaitAccessEnable(void); + +/** + * @brief Wait RTC Access Enable + * + * @param None + * + * @return None + * + * @details This function is used to enable the maximum RTC read/write accessible time. + */ +__STATIC_INLINE void RTC_WaitAccessEnable(void) +{ + while((RTC->RWEN & RTC_RWEN_RTCBUSY_Msk) == RTC_RWEN_RTCBUSY_Msk) + { + } + + if(!(SYS->CSERVER & 0x1)) + { + /* To wait RWENF bit is cleared and enable RWENF bit (Access Enable bit) again */ + RTC->RWEN = RTC_WRITE_KEY; + } + + /* To wait RWENF bit is set and user can access the protected-register of RTC from now on */ + while((RTC->RWEN & RTC_RWEN_RWENF_Msk) == (uint32_t)0x0) + { + } +} + +void RTC_Open(S_RTC_TIME_DATA_T *sPt); +void RTC_Close(void); +void RTC_32KCalibration(int32_t i32FrequencyX10000); +void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek); +void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm); +void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day); +void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm); +void RTC_SetAlarmDateMask(uint8_t u8IsTenYMsk, uint8_t u8IsYMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenDMsk, uint8_t u8IsDMsk); +void RTC_SetAlarmTimeMask(uint8_t u8IsTenHMsk, uint8_t u8IsHMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenSMsk, uint8_t u8IsSMsk); +uint32_t RTC_GetDayOfWeek(void); +void RTC_SetTickPeriod(uint32_t u32TickSelection); +void RTC_EnableInt(uint32_t u32IntFlagMask); +void RTC_DisableInt(uint32_t u32IntFlagMask); +void RTC_EnableSpareAccess(void); +void RTC_DisableSpareRegister(void); +void RTC_StaticTamperEnable(uint32_t u32TamperSelect, uint32_t u32DetecLevel, uint32_t u32DebounceEn); +void RTC_StaticTamperDisable(uint32_t u32TamperSelect); +void RTC_DynamicTamperEnable(uint32_t u32PairSel, uint32_t u32DebounceEn, uint32_t u32Pair1Source, uint32_t u32Pair2Source); +void RTC_DynamicTamperDisable(uint32_t u32PairSel); +void RTC_DynamicTamperConfig(uint32_t u32ChangeRate, uint32_t u32SeedReload, uint32_t u32RefPattern, uint32_t u32Seed); + +/*@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group RTC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_RTC_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_sc.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_sc.h new file mode 100644 index 0000000000000000000000000000000000000000..ac778b6644237cdd84621cfe6d3c319726806bab --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_sc.h @@ -0,0 +1,268 @@ +/**************************************************************************//** + * @file nu_sc.h + * @version V1.00 + * @brief M480 Smartcard (SC) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_SC_H__ +#define __NU_SC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SC_Driver SC Driver + @{ +*/ + +/** @addtogroup SC_EXPORTED_CONSTANTS SC Exported Constants + @{ +*/ +#define SC_INTERFACE_NUM 3 /*!< Smartcard interface numbers \hideinitializer */ +#define SC_PIN_STATE_HIGH 1 /*!< Smartcard pin status high \hideinitializer */ +#define SC_PIN_STATE_LOW 0 /*!< Smartcard pin status low \hideinitializer */ +#define SC_PIN_STATE_IGNORE 0xFFFFFFFF /*!< Ignore pin status \hideinitializer */ +#define SC_CLK_ON 1 /*!< Smartcard clock on \hideinitializer */ +#define SC_CLK_OFF 0 /*!< Smartcard clock off \hideinitializer */ + +#define SC_TMR_MODE_0 (0ul << SC_TMRCTL0_OPMODE_Pos) /*!INTEN |= (u32Mask)) + +/** + * @brief This macro disable smartcard interrupt + * @param[in] sc Base address of smartcard module + * @param[in] u32Mask Interrupt mask to be disabled. A combination of + * - \ref SC_INTEN_ACERRIEN_Msk + * - \ref SC_INTEN_RXTOIEN_Msk + * - \ref SC_INTEN_INITIEN_Msk + * - \ref SC_INTEN_CDIEN_Msk + * - \ref SC_INTEN_BGTIEN_Msk + * - \ref SC_INTEN_TMR2IEN_Msk + * - \ref SC_INTEN_TMR1IEN_Msk + * - \ref SC_INTEN_TMR0IEN_Msk + * - \ref SC_INTEN_TERRIEN_Msk + * - \ref SC_INTEN_TBEIEN_Msk + * - \ref SC_INTEN_RDAIEN_Msk + * @return None + * \hideinitializer + */ +#define SC_DISABLE_INT(sc, u32Mask) ((sc)->INTEN &= ~(u32Mask)) + +/** + * @brief This macro set VCC pin state of smartcard interface + * @param[in] sc Base address of smartcard module + * @param[in] u32State Pin state of VCC pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW + * @return None + * \hideinitializer + */ +#define SC_SET_VCC_PIN(sc, u32State) \ + do {\ + while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\ + if(u32State)\ + (sc)->PINCTL |= SC_PINCTL_PWREN_Msk;\ + else\ + (sc)->PINCTL &= ~SC_PINCTL_PWREN_Msk;\ + }while(0) + + +/** + * @brief This macro turns CLK output on or off + * @param[in] sc Base address of smartcard module + * @param[in] u32OnOff Clock on or off for selected smartcard module, valid values are \ref SC_CLK_ON and \ref SC_CLK_OFF + * @return None + * \hideinitializer + */ +#define SC_SET_CLK_PIN(sc, u32OnOff)\ + do {\ + while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\ + if(u32OnOff)\ + (sc)->PINCTL |= SC_PINCTL_CLKKEEP_Msk;\ + else\ + (sc)->PINCTL &= ~(SC_PINCTL_CLKKEEP_Msk);\ + }while(0) + +/** + * @brief This macro set I/O pin state of smartcard interface + * @param[in] sc Base address of smartcard module + * @param[in] u32State Pin state of I/O pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW + * @return None + * \hideinitializer + */ +#define SC_SET_IO_PIN(sc, u32State)\ + do {\ + while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\ + if(u32State)\ + (sc)->PINCTL |= SC_PINCTL_SCDATA_Msk;\ + else\ + (sc)->PINCTL &= ~SC_PINCTL_SCDATA_Msk;\ + }while(0) + +/** + * @brief This macro set RST pin state of smartcard interface + * @param[in] sc Base address of smartcard module + * @param[in] u32State Pin state of RST pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW + * @return None + * \hideinitializer + */ +#define SC_SET_RST_PIN(sc, u32State)\ + do {\ + while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\ + if(u32State)\ + (sc)->PINCTL |= SC_PINCTL_RSTEN_Msk;\ + else\ + (sc)->PINCTL &= ~SC_PINCTL_RSTEN_Msk;\ + }while(0) + +/** + * @brief This macro read one byte from smartcard module receive FIFO + * @param[in] sc Base address of smartcard module + * @return One byte read from receive FIFO + * \hideinitializer + */ +#define SC_READ(sc) ((char)((sc)->DAT)) + +/** + * @brief This macro write one byte to smartcard module transmit FIFO + * @param[in] sc Base address of smartcard module + * @param[in] u8Data Data to write to transmit FIFO + * @return None + * \hideinitializer + */ +#define SC_WRITE(sc, u8Data) ((sc)->DAT = (u8Data)) + +/** + * @brief This macro set smartcard stop bit length + * @param[in] sc Base address of smartcard module + * @param[in] u32Len Stop bit length, ether 1 or 2. + * @return None + * @details Stop bit length must be 1 for T = 1 protocol and 2 for T = 0 protocol. + * \hideinitializer + */ +#define SC_SET_STOP_BIT_LEN(sc, u32Len) ((sc)->CTL = ((sc)->CTL & ~SC_CTL_NSB_Msk) | ((u32Len) == 1 ? SC_CTL_NSB_Msk : 0)) + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void SC_SetTxRetry(SC_T *sc, uint32_t u32Count); +__STATIC_INLINE void SC_SetRxRetry(SC_T *sc, uint32_t u32Count); + +/** + * @brief Enable/Disable Tx error retry, and set Tx error retry count + * @param[in] sc Base address of smartcard module + * @param[in] u32Count The number of times of Tx error retry count, between 0~8. 0 means disable Tx error retry + * @return None + */ +__STATIC_INLINE void SC_SetTxRetry(SC_T *sc, uint32_t u32Count) +{ + while((sc)->CTL & SC_CTL_SYNC_Msk) + { + ; + } + /* Retry count must set while enable bit disabled, so disable it first */ + (sc)->CTL &= ~(SC_CTL_TXRTY_Msk | SC_CTL_TXRTYEN_Msk); + + if((u32Count) != 0UL) + { + while((sc)->CTL & SC_CTL_SYNC_Msk) + { + ; + } + (sc)->CTL |= (((u32Count) - 1UL) << SC_CTL_TXRTY_Pos) | SC_CTL_TXRTYEN_Msk; + } +} + +/** + * @brief Enable/Disable Rx error retry, and set Rx error retry count + * @param[in] sc Base address of smartcard module + * @param[in] u32Count The number of times of Rx error retry count, between 0~8. 0 means disable Rx error retry + * @return None + */ +__STATIC_INLINE void SC_SetRxRetry(SC_T *sc, uint32_t u32Count) +{ + while((sc)->CTL & SC_CTL_SYNC_Msk) + { + ; + } + /* Retry count must set while enable bit disabled, so disable it first */ + (sc)->CTL &= ~(SC_CTL_RXRTY_Msk | SC_CTL_RXRTYEN_Msk); + + if((u32Count) != 0UL) + { + while((sc)->CTL & SC_CTL_SYNC_Msk) + { + ; + } + (sc)->CTL |= (((u32Count) - 1UL) << SC_CTL_RXRTY_Pos) | SC_CTL_RXRTYEN_Msk; + } + +} + + +uint32_t SC_IsCardInserted(SC_T *sc); +void SC_ClearFIFO(SC_T *sc); +void SC_Close(SC_T *sc); +void SC_Open(SC_T *sc, uint32_t u32CardDet, uint32_t u32PWR); +void SC_ResetReader(SC_T *sc); +void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT); +void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT); +void SC_StopAllTimer(SC_T *sc); +void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount); +void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum); +uint32_t SC_GetInterfaceClock(SC_T *sc); + + +/*@}*/ /* end of group SC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_SC_H__ */ + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_scuart.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_scuart.h new file mode 100644 index 0000000000000000000000000000000000000000..e5e9e7831ae59bc630512da3ea4d77b8ed35efe7 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_scuart.h @@ -0,0 +1,267 @@ +/**************************************************************************//** + * @file nu_scuart.h + * @version V1.00 + * @brief M480 Smartcard UART mode (SCUART) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_SCUART_H__ +#define __NU_SCUART_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SCUART_Driver SCUART Driver + @{ +*/ + +/** @addtogroup SCUART_EXPORTED_CONSTANTS SCUART Exported Constants + @{ +*/ +#define SCUART_CHAR_LEN_5 (0x3ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 5 bits \hideinitializer */ +#define SCUART_CHAR_LEN_6 (0x2ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 6 bits \hideinitializer */ +#define SCUART_CHAR_LEN_7 (0x1ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 7 bits \hideinitializer */ +#define SCUART_CHAR_LEN_8 (0UL) /*!< Set SCUART word length to 8 bits \hideinitializer */ + +#define SCUART_PARITY_NONE (SC_UARTCTL_PBOFF_Msk) /*!< Set SCUART transfer with no parity \hideinitializer */ +#define SCUART_PARITY_ODD (SC_UARTCTL_OPE_Msk) /*!< Set SCUART transfer with odd parity \hideinitializer */ +#define SCUART_PARITY_EVEN (0UL) /*!< Set SCUART transfer with even parity \hideinitializer */ + +#define SCUART_STOP_BIT_1 (SC_CTL_NSB_Msk) /*!< Set SCUART transfer with one stop bit \hideinitializer */ +#define SCUART_STOP_BIT_2 (0UL) /*!< Set SCUART transfer with two stop bits \hideinitializer */ + + +/*@}*/ /* end of group SCUART_EXPORTED_CONSTANTS */ + + +/** @addtogroup SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions + @{ +*/ + +/* TX Macros */ +/** + * @brief Write Data to Tx data register + * @param[in] sc The base address of smartcard module. + * @param[in] u8Data Data byte to transmit + * @return None + * \hideinitializer + */ +#define SCUART_WRITE(sc, u8Data) ((sc)->DAT = (u8Data)) + +/** + * @brief Get TX FIFO empty flag status from register + * @param[in] sc The base address of smartcard module + * @return Transmit FIFO empty status + * @retval 0 Transmit FIFO is not empty + * @retval SC_STATUS_TXEMPTY_Msk Transmit FIFO is empty + * \hideinitializer + */ +#define SCUART_GET_TX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_TXEMPTY_Msk) + +/** + * @brief Get TX FIFO full flag status from register + * @param[in] sc The base address of smartcard module + * @return Transmit FIFO full status + * @retval 0 Transmit FIFO is not full + * @retval SC_STATUS_TXFULL_Msk Transmit FIFO is full + * \hideinitializer + */ +#define SCUART_GET_TX_FULL(sc) ((sc)->STATUS & SC_STATUS_TXFULL_Msk) + +/** + * @brief Wait specified smartcard port transmission complete + * @param[in] sc The base address of smartcard module + * @return None + * @note This Macro blocks until transmit complete. + * \hideinitializer + */ +#define SCUART_WAIT_TX_EMPTY(sc) while((sc)->STATUS & SC_STATUS_TXACT_Msk) + +/** + * @brief Check specified smartcard port transmit FIFO is full or not + * @param[in] sc The base address of smartcard module + * @return Transmit FIFO full status + * @retval 0 Transmit FIFO is not full + * @retval 1 Transmit FIFO is full + * \hideinitializer + */ +#define SCUART_IS_TX_FULL(sc) ((sc)->STATUS & SC_STATUS_TXFULL_Msk ? 1 : 0) + +/** + * @brief Check specified smartcard port transmission is over + * @param[in] sc The base address of smartcard module + * @return Transmit complete status + * @retval 0 Transmit is not complete + * @retval 1 Transmit complete + * \hideinitializer + */ +#define SCUART_IS_TX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_TXACT_Msk ? 0 : 1) + +/** + * @brief Check specified Smartcard port Transmission Status + * @param[in] sc The pointer of smartcard module. + * @retval 0 Transmit is completed + * @retval 1 Transmit is active + * @details TXACT (SC_STATUS[31]) is set by hardware when Tx transfer is in active and the STOP bit of the last byte has been transmitted. + * \hideinitializer + */ +#define SCUART_IS_TX_ACTIVE(sc) (((sc)->STATUS & SC_STATUS_TXACT_Msk)? 1 : 0) + +/* RX Macros */ + +/** + * @brief Read Rx data register + * @param[in] sc The base address of smartcard module + * @return The oldest data byte in RX FIFO + * \hideinitializer + */ +#define SCUART_READ(sc) ((sc)->DAT) + +/** + * @brief Get RX FIFO empty flag status from register + * @param[in] sc The base address of smartcard module + * @return Receive FIFO empty status + * @retval 0 Receive FIFO is not empty + * @retval SC_STATUS_RXEMPTY_Msk Receive FIFO is empty + * \hideinitializer + */ +#define SCUART_GET_RX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_RXEMPTY_Msk) + + +/** + * @brief Get RX FIFO full flag status from register + * @param[in] sc The base address of smartcard module + * @return Receive FIFO full status + * @retval 0 Receive FIFO is not full + * @retval SC_STATUS_RXFULLF_Msk Receive FIFO is full + * \hideinitializer + */ +#define SCUART_GET_RX_FULL(sc) ((sc)->STATUS & SC_STATUS_RXFULL_Msk) + +/** + * @brief Check if receive data number in FIFO reach FIFO trigger level or not + * @param[in] sc The base address of smartcard module + * @return Receive FIFO data status + * @retval 0 The number of bytes in receive FIFO is less than trigger level + * @retval 1 The number of bytes in receive FIFO equals or larger than trigger level + * @note If receive trigger level is \b not 1 byte, this macro return 0 does not necessary indicates there is \b no data in FIFO + * \hideinitializer + */ +#define SCUART_IS_RX_READY(sc) ((sc)->INTSTS & SC_INTSTS_RDAIF_Msk ? 1 : 0) + +/** + * @brief Check specified smartcard port receive FIFO is full or not + * @param[in] sc The base address of smartcard module + * @return Receive FIFO full status + * @retval 0 Receive FIFO is not full + * @retval 1 Receive FIFO is full + * \hideinitializer + */ +#define SCUART_IS_RX_FULL(sc) ((sc)->STATUS & SC_STATUS_RXFULL_Msk ? 1 : 0) + +/* Interrupt Macros */ + +/** + * @brief Enable specified interrupts + * @param[in] sc The base address of smartcard module + * @param[in] u32Mask Interrupt masks to enable, a combination of following bits + * - \ref SC_INTEN_RXTOIEN_Msk + * - \ref SC_INTEN_TERRIEN_Msk + * - \ref SC_INTEN_TBEIEN_Msk + * - \ref SC_INTEN_RDAIEN_Msk + * @return None + * \hideinitializer + */ +#define SCUART_ENABLE_INT(sc, u32Mask) ((sc)->INTEN |= (u32Mask)) + +/** + * @brief Disable specified interrupts + * @param[in] sc The base address of smartcard module + * @param[in] u32Mask Interrupt masks to disable, a combination of following bits + * - \ref SC_INTEN_RXTOIEN_Msk + * - \ref SC_INTEN_TERRIEN_Msk + * - \ref SC_INTEN_TBEIEN_Msk + * - \ref SC_INTEN_RDAIEN_Msk + * @return None + * \hideinitializer + */ +#define SCUART_DISABLE_INT(sc, u32Mask) ((sc)->INTEN &= ~(u32Mask)) + +/** + * @brief Get specified interrupt flag/status + * @param[in] sc The base address of smartcard module + * @param[in] u32Type Interrupt flag/status to check, could be one of following value + * - \ref SC_INTSTS_RXTOIF_Msk + * - \ref SC_INTSTS_TERRIF_Msk + * - \ref SC_INTSTS_TBEIF_Msk + * - \ref SC_INTSTS_RDAIF_Msk + * @return The status of specified interrupt + * @retval 0 Specified interrupt does not happened + * @retval 1 Specified interrupt happened + * \hideinitializer + */ +#define SCUART_GET_INT_FLAG(sc, u32Type) ((sc)->INTSTS & (u32Type) ? 1 : 0) + +/** + * @brief Clear specified interrupt flag/status + * @param[in] sc The base address of smartcard module + * @param[in] u32Type Interrupt flag/status to clear, could be the combination of following values + * - \ref SC_INTSTS_RXTOIF_Msk + * - \ref SC_INTSTS_TERRIF_Msk + * - \ref SC_INTSTS_TBEIF_Msk + * @return None + * \hideinitializer + */ +#define SCUART_CLR_INT_FLAG(sc, u32Type) ((sc)->INTSTS = (u32Type)) + +/** + * @brief Get receive error flag/status + * @param[in] sc The base address of smartcard module + * @return Current receive error status, could one of following errors: + * @retval SC_STATUS_PEF_Msk Parity error + * @retval SC_STATUS_FEF_Msk Frame error + * @retval SC_STATUS_BEF_Msk Break error + * \hideinitializer + */ +#define SCUART_GET_ERR_FLAG(sc) ((sc)->STATUS & (SC_STATUS_PEF_Msk | SC_STATUS_FEF_Msk | SC_STATUS_BEF_Msk)) + +/** + * @brief Clear specified receive error flag/status + * @param[in] sc The base address of smartcard module + * @param[in] u32Mask Receive error flag/status to clear, combination following values + * - \ref SC_STATUS_PEF_Msk + * - \ref SC_STATUS_FEF_Msk + * - \ref SC_STATUS_BEF_Msk + * @return None + * \hideinitializer + */ +#define SCUART_CLR_ERR_FLAG(sc, u32Mask) ((sc)->STATUS = (u32Mask)) + +void SCUART_Close(SC_T* sc); +uint32_t SCUART_Open(SC_T* sc, uint32_t u32baudrate); +uint32_t SCUART_Read(SC_T* sc, uint8_t pu8RxBuf[], uint32_t u32ReadBytes); +uint32_t SCUART_SetLineConfig(SC_T* sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits); +void SCUART_SetTimeoutCnt(SC_T* sc, uint32_t u32TOC); +void SCUART_Write(SC_T* sc,uint8_t pu8TxBuf[], uint32_t u32WriteBytes); + +/*@}*/ /* end of group SCUART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SCUART_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_SCUART_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_sdh.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_sdh.h new file mode 100644 index 0000000000000000000000000000000000000000..41d1d199f599f92e3a7a9c7af0c09a0f017209d1 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_sdh.h @@ -0,0 +1,203 @@ +/**************************************************************************//** + * @file nu_sdh.h + * @version V1.00 + * @brief M480 SDH driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include + +#ifndef __NU_SDH_H__ +#define __NU_SDH_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SDH_Driver SDH Driver + @{ +*/ + + +/** @addtogroup SDH_EXPORTED_CONSTANTS SDH Exported Constants + @{ +*/ + +#define SDH_ERR_ID 0xFFFF0100ul /*!< SDH error ID \hideinitializer */ + +#define SDH_TIMEOUT (SDH_ERR_ID|0x01ul) /*!< Timeout \hideinitializer */ +#define SDH_NO_MEMORY (SDH_ERR_ID|0x02ul) /*!< OOM \hideinitializer */ + +/*-- function return value */ +#define Successful 0ul /*!< Success \hideinitializer */ +#define Fail 1ul /*!< Failed \hideinitializer */ + +/*--- define type of SD card or MMC */ +#define SDH_TYPE_UNKNOWN 0ul /*!< Unknown card type \hideinitializer */ +#define SDH_TYPE_SD_HIGH 1ul /*!< SDHC card \hideinitializer */ +#define SDH_TYPE_SD_LOW 2ul /*!< SD card \hideinitializer */ +#define SDH_TYPE_MMC 3ul /*!< MMC card \hideinitializer */ +#define SDH_TYPE_EMMC 4ul /*!< eMMC card \hideinitializer */ + +/* SD error */ +#define SDH_NO_SD_CARD (SDH_ERR_ID|0x10ul) /*!< Card removed \hideinitializer */ +#define SDH_ERR_DEVICE (SDH_ERR_ID|0x11ul) /*!< Device error \hideinitializer */ +#define SDH_INIT_TIMEOUT (SDH_ERR_ID|0x12ul) /*!< Card init timeout \hideinitializer */ +#define SDH_SELECT_ERROR (SDH_ERR_ID|0x13ul) /*!< Card select error \hideinitializer */ +#define SDH_WRITE_PROTECT (SDH_ERR_ID|0x14ul) /*!< Card write protect \hideinitializer */ +#define SDH_INIT_ERROR (SDH_ERR_ID|0x15ul) /*!< Card init error \hideinitializer */ +#define SDH_CRC7_ERROR (SDH_ERR_ID|0x16ul) /*!< CRC 7 error \hideinitializer */ +#define SDH_CRC16_ERROR (SDH_ERR_ID|0x17ul) /*!< CRC 16 error \hideinitializer */ +#define SDH_CRC_ERROR (SDH_ERR_ID|0x18ul) /*!< CRC error \hideinitializer */ +#define SDH_CMD8_ERROR (SDH_ERR_ID|0x19ul) /*!< Command 8 error \hideinitializer */ + +#define MMC_FREQ 20000ul /*!< output 20MHz to MMC \hideinitializer */ +#define SD_FREQ 25000ul /*!< output 25MHz to SD \hideinitializer */ +#define SDHC_FREQ 50000ul /*!< output 50MHz to SDH \hideinitializer */ + +#define SD_PORT0 (1 << 0) /*!< Card select SD0 \hideinitializer */ +#define SD_PORT1 (1 << 2) /*!< Card select SD1 \hideinitializer */ +#define CardDetect_From_GPIO (1ul << 8) /*!< Card detection pin is GPIO \hideinitializer */ +#define CardDetect_From_DAT3 (1ul << 9) /*!< Card detection pin is DAT3 \hideinitializer */ + +/*@}*/ /* end of group SDH_EXPORTED_CONSTANTS */ + +/** @addtogroup SDH_EXPORTED_TYPEDEF SDH Exported Type Defines + @{ +*/ +typedef struct SDH_info_t +{ + unsigned char IsCardInsert; /*!< Card insert state */ + unsigned char R3Flag; + unsigned char R7Flag; + unsigned char volatile DataReadyFlag; + unsigned int CardType; /*!< SDHC, SD, or MMC */ + unsigned int RCA; /*!< Relative card address */ + unsigned int totalSectorN; /*!< Total sector number */ + unsigned int diskSize; /*!< Disk size in K bytes */ + int sectorSize; /*!< Sector size in bytes */ + unsigned char *dmabuf; +} SDH_INFO_T; /*!< Structure holds SD card info */ + +/*@}*/ /* end of group SDH_EXPORTED_TYPEDEF */ + +/** @cond HIDDEN_SYMBOLS */ +extern SDH_INFO_T SD0, SD1; +/** @endcond HIDDEN_SYMBOLS */ + +/** @addtogroup SDH_EXPORTED_FUNCTIONS SDH Exported Functions + @{ +*/ + +/** + * @brief Enable specified interrupt. + * + * @param[in] sdh Select SDH0 or SDH1. + * @param[in] u32IntMask Interrupt type mask: + * \ref SDH_INTEN_BLKDIEN_Msk / \ref SDH_INTEN_CRCIEN_Msk / \ref SDH_INTEN_CDIEN_Msk / + * \ref SDH_INTEN_CDSRC_Msk \ref SDH_INTEN_RTOIEN_Msk / \ref SDH_INTEN_DITOIEN_Msk / + * \ref SDH_INTEN_WKIEN_Msk + * + * @return None. + * \hideinitializer + */ +#define SDH_ENABLE_INT(sdh, u32IntMask) ((sdh)->INTEN |= (u32IntMask)) + +/** + * @brief Disable specified interrupt. + * + * @param[in] sdh Select SDH0 or SDH1. + * @param[in] u32IntMask Interrupt type mask: + * \ref SDH_INTEN_BLKDIEN_Msk / \ref SDH_INTEN_CRCIEN_Msk / \ref SDH_INTEN_CDIEN_Msk / + * \ref SDH_INTEN_RTOIEN_Msk / \ref SDH_INTEN_DITOIEN_Msk / \ref SDH_INTEN_WKIEN_Msk / \ref SDH_INTEN_CDSRC_Msk / + * + * @return None. + * \hideinitializer + */ +#define SDH_DISABLE_INT(sdh, u32IntMask) ((sdh)->INTEN &= ~(u32IntMask)) + +/** + * @brief Get specified interrupt flag/status. + * + * @param[in] sdh Select SDH0 or SDH1. + * @param[in] u32IntMask Interrupt type mask: + * \ref SDH_INTSTS_BLKDIF_Msk / \ref SDH_INTSTS_CRCIF_Msk / \ref SDH_INTSTS_CRC7_Msk / + * \ref SDH_INTSTS_CRC16_Msk / \ref SDH_INTSTS_CRCSTS_Msk / \ref SDH_INTSTS_DAT0STS_Msk / + * \ref SDH_INTSTS_CDIF_Msk \ref SDH_INTSTS_RTOIF_Msk / + * \ref SDH_INTSTS_DITOIF_Msk / \ref SDH_INTSTS_CDSTS_Msk / + * \ref SDH_INTSTS_DAT1STS_Msk + * + * + * @return 0 = The specified interrupt is not happened. + * 1 = The specified interrupt is happened. + * \hideinitializer + */ +#define SDH_GET_INT_FLAG(sdh, u32IntMask) (((sdh)->INTSTS & (u32IntMask))?1:0) + + +/** + * @brief Clear specified interrupt flag/status. + * + * @param[in] sdh Select SDH0 or SDH1. + * @param[in] u32IntMask Interrupt type mask: + * \ref SDH_INTSTS_BLKDIF_Msk / \ref SDH_INTSTS_CRCIF_Msk / \ref SDH_INTSTS_CDIF_Msk / + * \ref SDH_INTSTS_RTOIF_Msk / \ref SDH_INTSTS_DITOIF_Msk + * + * + * @return None. + * \hideinitializer + */ +#define SDH_CLR_INT_FLAG(sdh, u32IntMask) ((sdh)->INTSTS = (u32IntMask)) + + +/** + * @brief Check SD Card inserted or removed. + * + * @param[in] sdh Select SDH0 or SDH1. + * + * @return 1: Card inserted. + * 0: Card removed. + * \hideinitializer + */ +#define SDH_IS_CARD_PRESENT(sdh) (((sdh) == SDH0)? SD0.IsCardInsert : SD1.IsCardInsert) + +/** + * @brief Get SD Card capacity. + * + * @param[in] sdh Select SDH0 or SDH1. + * + * @return SD Card capacity. (unit: KByte) + * \hideinitializer + */ +#define SDH_GET_CARD_CAPACITY(sdh) (((sdh) == SDH0)? SD0.diskSize : SD1.diskSize) + + +void SDH_Open(SDH_T *sdh, uint32_t u32CardDetSrc); +uint32_t SDH_Probe(SDH_T *sdh); +uint32_t SDH_Read(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount); +uint32_t SDH_Write(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount); + +uint32_t SDH_CardDetection(SDH_T *sdh); +void SDH_Open_Disk(SDH_T *sdh, uint32_t u32CardDetSrc); +void SDH_Close_Disk(SDH_T *sdh); + + +/*@}*/ /* end of group SDH_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SDH_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_SDH_H__ */ +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_spi.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..77eeda3b96c5fce1de1779d17ad48da0fada8978 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_spi.h @@ -0,0 +1,584 @@ +/**************************************************************************//** + * @file nu_spi.h + * @version V3.00 + * @brief M480 series SPI driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __NU_SPI_H__ +#define __NU_SPI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SPI_Driver SPI Driver + @{ +*/ + +/** @addtogroup SPI_EXPORTED_CONSTANTS SPI Exported Constants + @{ +*/ + +#define SPI_MODE_0 (SPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 \hideinitializer */ +#define SPI_MODE_1 (SPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 \hideinitializer */ +#define SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 \hideinitializer */ +#define SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 \hideinitializer */ + +#define SPI_SLAVE (SPI_CTL_SLAVE_Msk) /*!< Set as slave \hideinitializer */ +#define SPI_MASTER (0x0U) /*!< Set as master \hideinitializer */ + +#define SPI_SS (SPI_SSCTL_SS_Msk) /*!< Set SS \hideinitializer */ +#define SPI_SS_ACTIVE_HIGH (SPI_SSCTL_SSACTPOL_Msk) /*!< SS active high \hideinitializer */ +#define SPI_SS_ACTIVE_LOW (0x0U) /*!< SS active low \hideinitializer */ + +/* SPI Interrupt Mask */ +#define SPI_UNIT_INT_MASK (0x001U) /*!< Unit transfer interrupt mask \hideinitializer */ +#define SPI_SSACT_INT_MASK (0x002U) /*!< Slave selection signal active interrupt mask \hideinitializer */ +#define SPI_SSINACT_INT_MASK (0x004U) /*!< Slave selection signal inactive interrupt mask \hideinitializer */ +#define SPI_SLVUR_INT_MASK (0x008U) /*!< Slave under run interrupt mask \hideinitializer */ +#define SPI_SLVBE_INT_MASK (0x010U) /*!< Slave bit count error interrupt mask \hideinitializer */ +#define SPI_TXUF_INT_MASK (0x040U) /*!< Slave TX underflow interrupt mask \hideinitializer */ +#define SPI_FIFO_TXTH_INT_MASK (0x080U) /*!< FIFO TX threshold interrupt mask \hideinitializer */ +#define SPI_FIFO_RXTH_INT_MASK (0x100U) /*!< FIFO RX threshold interrupt mask \hideinitializer */ +#define SPI_FIFO_RXOV_INT_MASK (0x200U) /*!< FIFO RX overrun interrupt mask \hideinitializer */ +#define SPI_FIFO_RXTO_INT_MASK (0x400U) /*!< FIFO RX time-out interrupt mask \hideinitializer */ + +/* SPI Status Mask */ +#define SPI_BUSY_MASK (0x01U) /*!< Busy status mask \hideinitializer */ +#define SPI_RX_EMPTY_MASK (0x02U) /*!< RX empty status mask \hideinitializer */ +#define SPI_RX_FULL_MASK (0x04U) /*!< RX full status mask \hideinitializer */ +#define SPI_TX_EMPTY_MASK (0x08U) /*!< TX empty status mask \hideinitializer */ +#define SPI_TX_FULL_MASK (0x10U) /*!< TX full status mask \hideinitializer */ +#define SPI_TXRX_RESET_MASK (0x20U) /*!< TX or RX reset status mask \hideinitializer */ +#define SPI_SPIEN_STS_MASK (0x40U) /*!< SPIEN status mask \hideinitializer */ +#define SPI_SSLINE_STS_MASK (0x80U) /*!< SPIx_SS line status mask \hideinitializer */ + + +/* I2S Data Width */ +#define SPII2S_DATABIT_8 (0U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 8-bit \hideinitializer */ +#define SPII2S_DATABIT_16 (1U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 16-bit \hideinitializer */ +#define SPII2S_DATABIT_24 (2U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 24-bit \hideinitializer */ +#define SPII2S_DATABIT_32 (3U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 32-bit \hideinitializer */ + +/* I2S Audio Format */ +#define SPII2S_MONO SPI_I2SCTL_MONO_Msk /*!< Monaural channel \hideinitializer */ +#define SPII2S_STEREO (0U) /*!< Stereo channel \hideinitializer */ + +/* I2S Data Format */ +#define SPII2S_FORMAT_I2S (0U<STATUS = SPI_STATUS_UNITIF_Msk) + +/** + * @brief Trigger RX PDMA function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set RXPDMAEN bit of SPI_PDMACTL register to enable RX PDMA transfer function. + * \hideinitializer + */ +#define SPI_TRIGGER_RX_PDMA(spi) ((spi)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk) + +/** + * @brief Trigger TX PDMA function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set TXPDMAEN bit of SPI_PDMACTL register to enable TX PDMA transfer function. + * \hideinitializer + */ +#define SPI_TRIGGER_TX_PDMA(spi) ((spi)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk) + +/** + * @brief Disable RX PDMA transfer. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear RXPDMAEN bit of SPI_PDMACTL register to disable RX PDMA transfer function. + * \hideinitializer + */ +#define SPI_DISABLE_RX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Disable TX PDMA transfer. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear TXPDMAEN bit of SPI_PDMACTL register to disable TX PDMA transfer function. + * \hideinitializer + */ +#define SPI_DISABLE_TX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Get the count of available data in RX FIFO. + * @param[in] spi The pointer of the specified SPI module. + * @return The count of available data in RX FIFO. + * @details Read RXCNT (SPI_STATUS[27:24]) to get the count of available data in RX FIFO. + * \hideinitializer + */ +#define SPI_GET_RX_FIFO_COUNT(spi) (((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos) + +/** + * @brief Get the RX FIFO empty flag. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 RX FIFO is not empty. + * @retval 1 RX FIFO is empty. + * @details Read RXEMPTY bit of SPI_STATUS register to get the RX FIFO empty flag. + * \hideinitializer + */ +#define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk)>>SPI_STATUS_RXEMPTY_Pos) + +/** + * @brief Get the TX FIFO empty flag. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 TX FIFO is not empty. + * @retval 1 TX FIFO is empty. + * @details Read TXEMPTY bit of SPI_STATUS register to get the TX FIFO empty flag. + * \hideinitializer + */ +#define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk)>>SPI_STATUS_TXEMPTY_Pos) + +/** + * @brief Get the TX FIFO full flag. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 TX FIFO is not full. + * @retval 1 TX FIFO is full. + * @details Read TXFULL bit of SPI_STATUS register to get the TX FIFO full flag. + * \hideinitializer + */ +#define SPI_GET_TX_FIFO_FULL_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TXFULL_Msk)>>SPI_STATUS_TXFULL_Pos) + +/** + * @brief Get the datum read from RX register. + * @param[in] spi The pointer of the specified SPI module. + * @return Data in RX register. + * @details Read SPI_RX register to get the received datum. + * \hideinitializer + */ +#define SPI_READ_RX(spi) ((spi)->RX) + +/** + * @brief Write datum to TX register. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32TxData The datum which user attempt to transfer through SPI bus. + * @return None. + * @details Write u32TxData to SPI_TX register. + * \hideinitializer + */ +#define SPI_WRITE_TX(spi, u32TxData) ((spi)->TX = (u32TxData)) + +/** + * @brief Set SPIx_SS pin to high state. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Disable automatic slave selection function and set SPIx_SS pin to high state. + * \hideinitializer + */ +#define SPI_SET_SS_HIGH(spi) ((spi)->SSCTL = ((spi)->SSCTL & (~SPI_SSCTL_AUTOSS_Msk)) | (SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk)) + +/** + * @brief Set SPIx_SS pin to low state. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Disable automatic slave selection function and set SPIx_SS pin to low state. + * \hideinitializer + */ +#define SPI_SET_SS_LOW(spi) ((spi)->SSCTL = ((spi)->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk))) | SPI_SSCTL_SS_Msk) + +/** + * @brief Enable Byte Reorder function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (SPI_CTL[7:4]). + * \hideinitializer + */ +#define SPI_ENABLE_BYTE_REORDER(spi) ((spi)->CTL |= SPI_CTL_REORDER_Msk) + +/** + * @brief Disable Byte Reorder function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear REORDER bit field of SPI_CTL register to disable Byte Reorder function. + * \hideinitializer + */ +#define SPI_DISABLE_BYTE_REORDER(spi) ((spi)->CTL &= ~SPI_CTL_REORDER_Msk) + +/** + * @brief Set the length of suspend interval. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15. + * @return None. + * @details Set the length of suspend interval according to u32SuspCycle. + * The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one SPI bus clock cycle). + * \hideinitializer + */ +#define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << SPI_CTL_SUSPITV_Pos)) + +/** + * @brief Set the SPI transfer sequence with LSB first. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set LSB bit of SPI_CTL register to set the SPI transfer sequence with LSB first. + * \hideinitializer + */ +#define SPI_SET_LSB_FIRST(spi) ((spi)->CTL |= SPI_CTL_LSB_Msk) + +/** + * @brief Set the SPI transfer sequence with MSB first. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear LSB bit of SPI_CTL register to set the SPI transfer sequence with MSB first. + * \hideinitializer + */ +#define SPI_SET_MSB_FIRST(spi) ((spi)->CTL &= ~SPI_CTL_LSB_Msk) + +/** + * @brief Set the data width of a SPI transaction. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Width The bit width of one transaction. + * @return None. + * @details The data width can be 8 ~ 32 bits. + * \hideinitializer + */ +#define SPI_SET_DATA_WIDTH(spi, u32Width) ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_DWIDTH_Msk) | (((u32Width)&0x1F) << SPI_CTL_DWIDTH_Pos)) + +/** + * @brief Get the SPI busy state. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 SPI controller is not busy. + * @retval 1 SPI controller is busy. + * @details This macro will return the busy state of SPI controller. + * \hideinitializer + */ +#define SPI_IS_BUSY(spi) ( ((spi)->STATUS & SPI_STATUS_BUSY_Msk)>>SPI_STATUS_BUSY_Pos ) + +/** + * @brief Enable SPI controller. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set SPIEN (SPI_CTL[0]) to enable SPI controller. + * \hideinitializer + */ +#define SPI_ENABLE(spi) ((spi)->CTL |= SPI_CTL_SPIEN_Msk) + +/** + * @brief Disable SPI controller. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear SPIEN (SPI_CTL[0]) to disable SPI controller. + * \hideinitializer + */ +#define SPI_DISABLE(spi) ((spi)->CTL &= ~SPI_CTL_SPIEN_Msk) + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask); +__STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask); +__STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch); + +/** + * @brief Enable zero cross detection function. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32ChMask The mask for left or right channel. Valid values are: + * - \ref SPII2S_RIGHT + * - \ref SPII2S_LEFT + * @return None + * @details This function will set RZCEN or LZCEN bit of SPI_I2SCTL register to enable zero cross detection function. + */ +__STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask) +{ + if(u32ChMask == SPII2S_RIGHT) + { + i2s->I2SCTL |= SPI_I2SCTL_RZCEN_Msk; + } + else + { + i2s->I2SCTL |= SPI_I2SCTL_LZCEN_Msk; + } +} + +/** + * @brief Disable zero cross detection function. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32ChMask The mask for left or right channel. Valid values are: + * - \ref SPII2S_RIGHT + * - \ref SPII2S_LEFT + * @return None + * @details This function will clear RZCEN or LZCEN bit of SPI_I2SCTL register to disable zero cross detection function. + */ +__STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask) +{ + if(u32ChMask == SPII2S_RIGHT) + { + i2s->I2SCTL &= ~SPI_I2SCTL_RZCEN_Msk; + } + else + { + i2s->I2SCTL &= ~SPI_I2SCTL_LZCEN_Msk; + } +} + +/** + * @brief Enable I2S TX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set TXPDMAEN bit of SPI_PDMACTL register to transmit data with PDMA. + * \hideinitializer + */ +#define SPII2S_ENABLE_TXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Disable I2S TX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear TXPDMAEN bit of SPI_PDMACTL register to disable TX DMA function. + * \hideinitializer + */ +#define SPII2S_DISABLE_TXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Enable I2S RX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set RXPDMAEN bit of SPI_PDMACTL register to receive data with PDMA. + * \hideinitializer + */ +#define SPII2S_ENABLE_RXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Disable I2S RX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear RXPDMAEN bit of SPI_PDMACTL register to disable RX DMA function. + * \hideinitializer + */ +#define SPII2S_DISABLE_RXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Enable I2S TX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set TXEN bit of SPI_I2SCTL register to enable I2S TX function. + * \hideinitializer + */ +#define SPII2S_ENABLE_TX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_TXEN_Msk ) + +/** + * @brief Disable I2S TX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear TXEN bit of SPI_I2SCTL register to disable I2S TX function. + * \hideinitializer + */ +#define SPII2S_DISABLE_TX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_TXEN_Msk ) + +/** + * @brief Enable I2S RX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set RXEN bit of SPI_I2SCTL register to enable I2S RX function. + * \hideinitializer + */ +#define SPII2S_ENABLE_RX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_RXEN_Msk ) + +/** + * @brief Disable I2S RX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear RXEN bit of SPI_I2SCTL register to disable I2S RX function. + * \hideinitializer + */ +#define SPII2S_DISABLE_RX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_RXEN_Msk ) + +/** + * @brief Enable TX Mute function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set MUTE bit of SPI_I2SCTL register to enable I2S TX mute function. + * \hideinitializer + */ +#define SPII2S_ENABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_MUTE_Msk ) + +/** + * @brief Disable TX Mute function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear MUTE bit of SPI_I2SCTL register to disable I2S TX mute function. + * \hideinitializer + */ +#define SPII2S_DISABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_MUTE_Msk ) + +/** + * @brief Clear TX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear TX FIFO. The internal TX FIFO pointer will be reset to FIFO start point. + * \hideinitializer + */ +#define SPII2S_CLR_TX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk ) + +/** + * @brief Clear RX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear RX FIFO. The internal RX FIFO pointer will be reset to FIFO start point. + * \hideinitializer + */ +#define SPII2S_CLR_RX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk ) + +/** + * @brief This function sets the recording source channel when mono mode is used. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Ch left or right channel. Valid values are: + * - \ref SPII2S_MONO_LEFT + * - \ref SPII2S_MONO_RIGHT + * @return None + * @details This function selects the recording source channel of monaural mode. + * \hideinitializer + */ +__STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch) +{ + u32Ch == SPII2S_MONO_LEFT ? + (i2s->I2SCTL |= SPI_I2SCTL_RXLCH_Msk) : + (i2s->I2SCTL &= ~SPI_I2SCTL_RXLCH_Msk); +} + +/** + * @brief Write data to I2S TX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Data The value written to TX FIFO. + * @return None + * @details This macro will write a value to TX FIFO. + * \hideinitializer + */ +#define SPII2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TX = (u32Data) ) + +/** + * @brief Read RX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @return The value read from RX FIFO. + * @details This function will return a value read from RX FIFO. + * \hideinitializer + */ +#define SPII2S_READ_RX_FIFO(i2s) ( (i2s)->RX ) + +/** + * @brief Get the interrupt flag. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Mask The mask value for all interrupt flags. + * @return The interrupt flags specified by the u32mask parameter. + * @details This macro will return the combination interrupt flags of SPI_I2SSTS register. The flags are specified by the u32mask parameter. + * \hideinitializer + */ +#define SPII2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS & (u32Mask) ) + +/** + * @brief Clear the interrupt flag. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Mask The mask value for all interrupt flags. + * @return None + * @details This macro will clear the interrupt flags specified by the u32mask parameter. + * @note Except TX and RX FIFO threshold interrupt flags, the other interrupt flags can be cleared by writing 1 to itself. + * \hideinitializer + */ +#define SPII2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS = (u32Mask) ) + +/** + * @brief Get transmit FIFO level + * @param[in] i2s The pointer of the specified I2S module. + * @return TX FIFO level + * @details This macro will return the number of available words in TX FIFO. + * \hideinitializer + */ +#define SPII2S_GET_TX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_TXCNT_Msk) >> SPI_I2SSTS_TXCNT_Pos ) + +/** + * @brief Get receive FIFO level + * @param[in] i2s The pointer of the specified I2S module. + * @return RX FIFO level + * @details This macro will return the number of available words in RX FIFO. + * \hideinitializer + */ +#define SPII2S_GET_RX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_RXCNT_Msk) >> SPI_I2SSTS_RXCNT_Pos ) + + + +/* Function prototype declaration */ +uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock); +void SPI_Close(SPI_T *spi); +void SPI_ClearRxFIFO(SPI_T *spi); +void SPI_ClearTxFIFO(SPI_T *spi); +void SPI_DisableAutoSS(SPI_T *spi); +void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel); +uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock); +void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold); +uint32_t SPI_GetBusClock(SPI_T *spi); +void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask); +void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask); +uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask); +void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask); +uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask); + +uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat); +void SPII2S_Close(SPI_T *i2s); +void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask); +void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask); +uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock); +void SPII2S_DisableMCLK(SPI_T *i2s); +void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold); + + +/*@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_spim.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_spim.h new file mode 100644 index 0000000000000000000000000000000000000000..84a0d98ffba6f6436f01169e9e681c59da2df595 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_spim.h @@ -0,0 +1,634 @@ +/**************************************************************************//** + * @file nu_spim.h + * @version V1.00 + * @brief M480 series SPIM driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __NU_SPIM_H__ +#define __NU_SPIM_H__ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Include related headers */ +/*---------------------------------------------------------------------------------------------------------*/ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SPIM_Driver SPIM Driver + @{ +*/ + + +/** @addtogroup SPIM_EXPORTED_CONSTANTS SPIM Exported Constants + @{ +*/ + +#define SPIM_DMM_MAP_ADDR 0x8000000UL /*!< DMM mode memory map base address \hideinitializer */ +#define SPIM_DMM_SIZE 0x2000000UL /*!< DMM mode memory mapping size \hideinitializer */ +#define SPIM_CCM_ADDR 0x20020000UL /*!< CCM mode memory map base address \hideinitializer */ +#define SPIM_CCM_SIZE 0x8000UL /*!< CCM mode memory size \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* SPIM_CTL0 constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define SPIM_CTL0_RW_IN(x) ((x) ? 0UL : (0x1UL << SPIM_CTL0_QDIODIR_Pos)) /*!< SPIM_CTL0: SPI Interface Direction Select \hideinitializer */ +#define SPIM_CTL0_BITMODE_SING (0UL << SPIM_CTL0_BITMODE_Pos) /*!< SPIM_CTL0: One bit mode (SPI Interface including DO, DI, HOLD, WP) \hideinitializer */ +#define SPIM_CTL0_BITMODE_DUAL (1UL << SPIM_CTL0_BITMODE_Pos) /*!< SPIM_CTL0: Two bits mode (SPI Interface including D0, D1, HOLD, WP) \hideinitializer */ +#define SPIM_CTL0_BITMODE_QUAD (2UL << SPIM_CTL0_BITMODE_Pos) /*!< SPIM_CTL0: Four bits mode (SPI Interface including D0, D1, D2, D3) \hideinitializer */ +#define SPIM_CTL0_OPMODE_IO (0UL << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_CTL0: I/O Mode \hideinitializer */ +#define SPIM_CTL0_OPMODE_PAGEWRITE (1UL << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_CTL0: Page Write Mode \hideinitializer */ +#define SPIM_CTL0_OPMODE_PAGEREAD (2UL << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_CTL0: Page Read Mode \hideinitializer */ +#define SPIM_CTL0_OPMODE_DIRECTMAP (3UL << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_CTL0: Direct Map Mode \hideinitializer */ + +#define CMD_NORMAL_PAGE_PROGRAM (0x02UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Page Program (Page Write Mode Use) \hideinitializer */ +#define CMD_NORMAL_PAGE_PROGRAM_4B (0x12UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Page Program (Page Write Mode Use) \hideinitializer */ +#define CMD_QUAD_PAGE_PROGRAM_WINBOND (0x32UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Quad Page program (for Winbond) (Page Write Mode Use) \hideinitializer */ +#define CMD_QUAD_PAGE_PROGRAM_MXIC (0x38UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Quad Page program (for MXIC) (Page Write Mode Use) \hideinitializer */ +#define CMD_QUAD_PAGE_PROGRAM_EON (0x40UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Quad Page Program (for EON) (Page Write Mode Use) \hideinitializer */ + +#define CMD_DMA_NORMAL_READ (0x03UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Read Data (Page Read Mode Use) \hideinitializer */ +#define CMD_DMA_FAST_READ (0x0BUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read (Page Read Mode Use) \hideinitializer */ +#define CMD_DMA_NORMAL_DUAL_READ (0x3BUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */ +#define CMD_DMA_FAST_READ_DUAL_OUTPUT (0x3BUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */ +#define CMD_DMA_FAST_READ_QUAD_OUTPUT (0x6BUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */ +#define CMD_DMA_FAST_DUAL_READ (0xBBUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */ +#define CMD_DMA_NORMAL_QUAD_READ (0xE7UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Quad I/O (Page Read Mode Use) \hideinitializer */ +#define CMD_DMA_FAST_QUAD_READ (0xEBUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Quad I/O (Page Read Mode Use) \hideinitializer */ + +/** @cond HIDDEN_SYMBOLS */ + +typedef enum +{ + MFGID_UNKNOW = 0x00U, + MFGID_SPANSION = 0x01U, + MFGID_EON = 0x1CU, + MFGID_ISSI = 0x7FU, + MFGID_MXIC = 0xC2U, + MFGID_WINBOND = 0xEFU +} +E_MFGID; + +/* Flash opcodes. */ +#define OPCODE_WREN 0x06U /* Write enable */ +#define OPCODE_RDSR 0x05U /* Read status register #1*/ +#define OPCODE_WRSR 0x01U /* Write status register #1 */ +#define OPCODE_RDSR2 0x35U /* Read status register #2*/ +#define OPCODE_WRSR2 0x31U /* Write status register #2 */ +#define OPCODE_RDSR3 0x15U /* Read status register #3*/ +#define OPCODE_WRSR3 0x11U /* Write status register #3 */ +#define OPCODE_PP 0x02U /* Page program (up to 256 bytes) */ +#define OPCODE_SE_4K 0x20U /* Erase 4KB sector */ +#define OPCODE_BE_32K 0x52U /* Erase 32KB block */ +#define OPCODE_CHIP_ERASE 0xc7U /* Erase whole flash chip */ +#define OPCODE_BE_64K 0xd8U /* Erase 64KB block */ +#define OPCODE_READ_ID 0x90U /* Read ID */ +#define OPCODE_RDID 0x9fU /* Read JEDEC ID */ +#define OPCODE_BRRD 0x16U /* SPANSION flash - Bank Register Read command */ +#define OPCODE_BRWR 0x17U /* SPANSION flash - Bank Register write command */ +#define OPCODE_NORM_READ 0x03U /* Read data bytes */ +#define OPCODE_FAST_READ 0x0bU /* Read data bytes */ +#define OPCODE_FAST_DUAL_READ 0x3bU /* Read data bytes */ +#define OPCODE_FAST_QUAD_READ 0x6bU /* Read data bytes */ + +/* Used for SST flashes only. */ +#define OPCODE_BP 0x02U /* Byte program */ +#define OPCODE_WRDI 0x04U /* Write disable */ +#define OPCODE_AAI_WP 0xadU /* Auto u32Address increment word program */ + +/* Used for Macronix flashes only. */ +#define OPCODE_EN4B 0xb7U /* Enter 4-byte mode */ +#define OPCODE_EX4B 0xe9U /* Exit 4-byte mode */ + +#define OPCODE_RDSCUR 0x2bU +#define OPCODE_WRSCUR 0x2fU + +#define OPCODE_RSTEN 0x66U +#define OPCODE_RST 0x99U + +#define OPCODE_ENQPI 0x38U +#define OPCODE_EXQPI 0xFFU + +/* Status Register bits. */ +#define SR_WIP 0x1U /* Write in progress */ +#define SR_WEL 0x2U /* Write enable latch */ +#define SR_QE 0x40U /* Quad Enable for MXIC */ +/* Status Register #2 bits. */ +#define SR2_QE 0x2U /* Quad Enable for Winbond */ +/* meaning of other SR_* bits may differ between vendors */ +#define SR_BP0 0x4U /* Block protect 0 */ +#define SR_BP1 0x8U /* Block protect 1 */ +#define SR_BP2 0x10U /* Block protect 2 */ +#define SR_SRWD 0x80U /* SR write protect */ +#define SR3_ADR 0x01U /* 4-byte u32Address mode */ + +#define SCUR_4BYTE 0x04U /* 4-byte u32Address mode */ + +/** @endcond HIDDEN_SYMBOLS */ + +/*@}*/ /* end of group SPIM_EXPORTED_CONSTANTS */ + + +/** @addtogroup SPIM_EXPORTED_FUNCTIONS SPIM Exported Functions + @{ +*/ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Macros and functions */ +/*---------------------------------------------------------------------------------------------------------*/ + +/** + * @details Enable cipher. + * \hideinitializer + */ +#define SPIM_ENABLE_CIPHER() (SPIM->CTL0 &= ~SPIM_CTL0_CIPHOFF_Msk) + +/** + * @details Disable cipher. + * \hideinitializer + */ +#define SPIM_DISABLE_CIPHER() (SPIM->CTL0 |= SPIM_CTL0_CIPHOFF_Msk) + +/** + * @details Enable cipher balance + * \hideinitializer + */ +#define SPIM_ENABLE_BALEN() (SPIM->CTL0 |= SPIM_CTL0_BALEN_Msk) + +/** + * @details Disable cipher balance + * \hideinitializer + */ +#define SPIM_DISABLE_BALEN() (SPIM->CTL0 &= ~SPIM_CTL0_BALEN_Msk) + +/** + * @details Set 4-byte address to be enabled/disabled. + * \hideinitializer + */ +#define SPIM_SET_4BYTE_ADDR_EN(x) \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_B4ADDREN_Msk)) | (((x) ? 1UL : 0UL) << SPIM_CTL0_B4ADDREN_Pos); \ + } while (0) + +/** + * @details Enable SPIM interrupt + * \hideinitializer + */ +#define SPIM_ENABLE_INT() (SPIM->CTL0 |= SPIM_CTL0_IEN_Msk) + +/** + * @details Disable SPIM interrupt + * \hideinitializer + */ +#define SPIM_DISABLE_INT() (SPIM->CTL0 &= ~SPIM_CTL0_IEN_Msk) + +/** + * @details Is interrupt flag on. + * \hideinitializer + */ +#define SPIM_IS_IF_ON() ((SPIM->CTL0 & SPIM_CTL0_IF_Msk) != 0UL) + +/** + * @details Clear interrupt flag. + * \hideinitializer + */ +#define SPIM_CLR_INT() \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_IF_Msk)) | (1UL << SPIM_CTL0_IF_Pos); \ + } while (0) + +/** + * @details Set transmit/receive bit length + * \hideinitializer + */ +#define SPIM_SET_DATA_WIDTH(x) \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_DWIDTH_Msk)) | (((x) - 1U) << SPIM_CTL0_DWIDTH_Pos); \ + } while (0) + +/** + * @details Get data transmit/receive bit length setting + * \hideinitializer + */ +#define SPIM_GET_DATA_WIDTH() \ + (((SPIM->CTL0 & SPIM_CTL0_DWIDTH_Msk) >> SPIM_CTL0_DWIDTH_Pos)+1U) + +/** + * @details Set data transmit/receive burst number + * \hideinitializer + */ +#define SPIM_SET_DATA_NUM(x) \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_BURSTNUM_Msk)) | (((x) - 1U) << SPIM_CTL0_BURSTNUM_Pos); \ + } while (0) + +/** + * @details Get data transmit/receive burst number + * \hideinitializer + */ +#define SPIM_GET_DATA_NUM() \ + (((SPIM->CTL0 & SPIM_CTL0_BURSTNUM_Msk) >> SPIM_CTL0_BURSTNUM_Pos)+1U) + +/** + * @details Enable Single Input mode. + * \hideinitializer + */ +#define SPIM_ENABLE_SING_INPUT_MODE() \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_SING | SPIM_CTL0_RW_IN(1)); \ + } while (0) + +/** + * @details Enable Single Output mode. + * \hideinitializer + */ +#define SPIM_ENABLE_SING_OUTPUT_MODE() \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_SING | SPIM_CTL0_RW_IN(0)); \ + } while (0) + +/** + * @details Enable Dual Input mode. + * \hideinitializer + */ +#define SPIM_ENABLE_DUAL_INPUT_MODE() \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_DUAL | SPIM_CTL0_RW_IN(1U)); \ + } while (0) + +/** + * @details Enable Dual Output mode. + * \hideinitializer + */ +#define SPIM_ENABLE_DUAL_OUTPUT_MODE() \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_DUAL | SPIM_CTL0_RW_IN(0U)); \ + } while (0) + +/** + * @details Enable Quad Input mode. + * \hideinitializer + */ +#define SPIM_ENABLE_QUAD_INPUT_MODE() \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_QUAD | SPIM_CTL0_RW_IN(1U)); \ + } while (0) + +/** + * @details Enable Quad Output mode. + * \hideinitializer + */ +#define SPIM_ENABLE_QUAD_OUTPUT_MODE() \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_QUAD | SPIM_CTL0_RW_IN(0U)); \ + } while (0) + +/** + * @details Set suspend interval which ranges between 0 and 15. + * \hideinitializer + */ +#define SPIM_SET_SUSP_INTVL(x) \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_SUSPITV_Msk)) | ((x) << SPIM_CTL0_SUSPITV_Pos); \ + } while (0) + +/** + * @details Get suspend interval setting + * \hideinitializer + */ +#define SPIM_GET_SUSP_INTVL() \ + ((SPIM->CTL0 & SPIM_CTL0_SUSPITV_Msk) >> SPIM_CTL0_SUSPITV_Pos) + +/** + * @details Set operation mode. + * \hideinitializer + */ +#define SPIM_SET_OPMODE(x) \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_OPMODE_Msk)) | (x); \ + } while (0) + +/** + * @details Get operation mode. + * \hideinitializer + */ +#define SPIM_GET_OP_MODE() (SPIM->CTL0 & SPIM_CTL0_OPMODE_Msk) + +/** + * @details Set SPIM mode. + * \hideinitializer + */ +#define SPIM_SET_SPIM_MODE(x) \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_CMDCODE_Msk)) | (x); \ + } while (0) + +/** + * @details Get SPIM mode. + * \hideinitializer + */ +#define SPIM_GET_SPIM_MODE() (SPIM->CTL0 & SPIM_CTL0_CMDCODE_Msk) + +/** + * @details Start operation. + * \hideinitializer + */ +#define SPIM_SET_GO() (SPIM->CTL1 |= SPIM_CTL1_SPIMEN_Msk) + +/** + * @details Is engine busy. + * \hideinitializer + */ +#define SPIM_IS_BUSY() (SPIM->CTL1 & SPIM_CTL1_SPIMEN_Msk) + +/** + * @details Wait for free. + * \hideinitializer + */ +#define SPIM_WAIT_FREE() \ + do { \ + while (SPIM->CTL1 & SPIM_CTL1_SPIMEN_Msk) { } \ + } while (0) + +/** + * @details Enable cache. + * \hideinitializer + */ +#define SPIM_ENABLE_CACHE() (SPIM->CTL1 &= ~SPIM_CTL1_CACHEOFF_Msk) + +/** + * @details Disable cache. + * \hideinitializer + */ +#define SPIM_DISABLE_CACHE() (SPIM->CTL1 |= SPIM_CTL1_CACHEOFF_Msk) + +/** + * @details Is cache enabled. + * \hideinitializer + */ +#define SPIM_IS_CACHE_EN() ((SPIM->CTL1 & SPIM_CTL1_CACHEOFF_Msk) ? 0 : 1) + +/** + * @details Enable CCM + * \hideinitializer + */ +#define SPIM_ENABLE_CCM() (SPIM->CTL1 |= SPIM_CTL1_CCMEN_Msk) + +/** + * @details Disable CCM. + * \hideinitializer + */ +#define SPIM_DISABLE_CCM() (SPIM->CTL1 &= ~SPIM_CTL1_CCMEN_Msk) + +/** + * @details Is CCM enabled. + * \hideinitializer + */ +#define SPIM_IS_CCM_EN() ((SPIM->CTL1 & SPIM_CTL1_CCMEN_Msk) >> SPIM_CTL1_CCMEN_Pos) + +/** + * @details Invalidate cache. + * \hideinitializer + */ +#define SPIM_INVALID_CACHE() (SPIM->CTL1 |= SPIM_CTL1_CDINVAL_Msk) + +/** + * @details Set SS(Select Active) to active level. + * \hideinitializer + */ +#define SPIM_SET_SS_EN(x) \ + do { \ + (SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_SS_Msk)) | ((! (x) ? 1UL : 0UL) << SPIM_CTL1_SS_Pos)); \ + } while (0) + +/** + * @details Is SS(Select Active) in active level. + * \hideinitializer + */ +#define SPIM_GET_SS_EN() \ + (!(SPIM->CTL1 & SPIM_CTL1_SS_Msk)) + +/** + * @details Set active level of slave select to be high/low. + * \hideinitializer + */ +#define SPIM_SET_SS_ACTLVL(x) \ + do { \ + (SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_SSACTPOL_Msk)) | ((!! (x) ? 1UL : 0UL) << SPIM_CTL1_SSACTPOL_Pos)); \ + } while (0) + +/** + * @details Set idle time interval + * \hideinitializer + */ +#define SPIM_SET_IDL_INTVL(x) \ + do { \ + SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_IDLETIME_Msk)) | ((x) << SPIM_CTL1_IDLETIME_Pos); \ + } while (0) + +/** + * @details Get idle time interval setting + * \hideinitializer + */ +#define SPIM_GET_IDL_INTVL() \ + ((SPIM->CTL1 & SPIM_CTL1_IDLETIME_Msk) >> SPIM_CTL1_IDLETIME_Pos) + +/** + * @details Set SPIM clock divider + * \hideinitializer + */ +#define SPIM_SET_CLOCK_DIVIDER(x) \ + do { \ + SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_DIVIDER_Msk)) | ((x) << SPIM_CTL1_DIVIDER_Pos); \ + } while (0) + +/** + * @details Get SPIM current clock divider setting + * \hideinitializer + */ +#define SPIM_GET_CLOCK_DIVIDER() \ + ((SPIM->CTL1 & SPIM_CTL1_DIVIDER_Msk) >> SPIM_CTL1_DIVIDER_Pos) + +/** + * @details Set SPI flash deselect time interval of DMA write mode + * \hideinitializer + */ +#define SPIM_SET_RXCLKDLY_DWDELSEL(x) \ + do { \ + (SPIM->RXCLKDLY = (SPIM->RXCLKDLY & (~SPIM_RXCLKDLY_DWDELSEL_Msk)) | ((x) << SPIM_RXCLKDLY_DWDELSEL_Pos)); \ + } while (0) + +/** + * @details Get SPI flash deselect time interval of DMA write mode + * \hideinitializer + */ +#define SPIM_GET_RXCLKDLY_DWDELSEL() \ + ((SPIM->RXCLKDLY & SPIM_RXCLKDLY_DWDELSEL_Msk) >> SPIM_RXCLKDLY_DWDELSEL_Pos) + +/** + * @details Set sampling clock delay selection for received data + * \hideinitializer + */ +#define SPIM_SET_RXCLKDLY_RDDLYSEL(x) \ + do { \ + (SPIM->RXCLKDLY = (SPIM->RXCLKDLY & (~SPIM_RXCLKDLY_RDDLYSEL_Msk)) | ((x) << SPIM_RXCLKDLY_RDDLYSEL_Pos)); \ + } while (0) + +/** + * @details Get sampling clock delay selection for received data + * \hideinitializer + */ +#define SPIM_GET_RXCLKDLY_RDDLYSEL() \ + ((SPIM->RXCLKDLY & SPIM_RXCLKDLY_RDDLYSEL_Msk) >> SPIM_RXCLKDLY_RDDLYSEL_Pos) + +/** + * @details Set sampling clock edge selection for received data + * \hideinitializer + */ +#define SPIM_SET_RXCLKDLY_RDEDGE() \ + (SPIM->RXCLKDLY |= SPIM_RXCLKDLY_RDEDGE_Msk); \ + +/** + * @details Get sampling clock edge selection for received data + * \hideinitializer + */ +#define SPIM_CLR_RXCLKDLY_RDEDGE() \ + (SPIM->RXCLKDLY &= ~SPIM_RXCLKDLY_RDEDGE_Msk) + +/** + * @details Set mode bits data for continuous read mode + * \hideinitializer + */ +#define SPIM_SET_DMMCTL_CRMDAT(x) \ + do { \ + (SPIM->DMMCTL = (SPIM->DMMCTL & (~SPIM_DMMCTL_CRMDAT_Msk)) | ((x) << SPIM_DMMCTL_CRMDAT_Pos)) | SPIM_DMMCTL_CREN_Msk; \ + } while (0) + +/** + * @details Get mode bits data for continuous read mode + * \hideinitializer + */ +#define SPIM_GET_DMMCTL_CRMDAT() \ + ((SPIM->DMMCTL & SPIM_DMMCTL_CRMDAT_Msk) >> SPIM_DMMCTL_CRMDAT_Pos) + +/** + * @details Set DMM mode SPI flash deselect time + * \hideinitializer + */ +#define SPIM_DMM_SET_DESELTIM(x) \ + do { \ + SPIM->DMMCTL = (SPIM->DMMCTL & ~SPIM_DMMCTL_DESELTIM_Msk) | (((x) & 0x1FUL) << SPIM_DMMCTL_DESELTIM_Pos); \ + } while (0) + +/** + * @details Get current DMM mode SPI flash deselect time setting + * \hideinitializer + */ +#define SPIM_DMM_GET_DESELTIM() \ + ((SPIM->DMMCTL & SPIM_DMMCTL_DESELTIM_Msk) >> SPIM_DMMCTL_DESELTIM_Pos) + +/** + * @details Enable DMM mode burst wrap mode + * \hideinitializer + */ +#define SPIM_DMM_ENABLE_BWEN() (SPIM->DMMCTL |= SPIM_DMMCTL_BWEN_Msk) + +/** + * @details Disable DMM mode burst wrap mode + * \hideinitializer + */ +#define SPIM_DMM_DISABLE_BWEN() (SPIM->DMMCTL &= ~SPIM_DMMCTL_BWEN_Msk) + +/** + * @details Enable DMM mode continuous read mode + * \hideinitializer + */ +#define SPIM_DMM_ENABLE_CREN() (SPIM->DMMCTL |= SPIM_DMMCTL_CREN_Msk) + +/** + * @details Disable DMM mode continuous read mode + * \hideinitializer + */ +#define SPIM_DMM_DISABLE_CREN() (SPIM->DMMCTL &= ~SPIM_DMMCTL_CREN_Msk) + +/** + * @details Set DMM mode SPI flash active SCLK time + * \hideinitializer + */ +#define SPIM_DMM_SET_ACTSCLKT(x) \ + do { \ + SPIM->DMMCTL = (SPIM->DMMCTL & ~SPIM_DMMCTL_ACTSCLKT_Msk) | (((x) & 0xFUL) << SPIM_DMMCTL_ACTSCLKT_Pos) | SPIM_DMMCTL_UACTSCLK_Msk; \ + } while (0) + +/** + * @details Set SPI flash active SCLK time as SPIM default + * \hideinitializer + */ +#define SPIM_DMM_SET_DEFAULT_ACTSCLK() (SPIM->DMMCTL &= ~SPIM_DMMCTL_UACTSCLK_Msk) + +/** + * @details Set dummy cycle number (Only for DMM mode and DMA mode) + * \hideinitializer + */ +#define SPIM_SET_DCNUM(x) \ + do { \ + SPIM->CTL2 = (SPIM->CTL2 & ~SPIM_CTL2_DCNUM_Msk) | (((x) & 0x1FUL) << SPIM_CTL2_DCNUM_Pos) | SPIM_CTL2_USETEN_Msk; \ + } while (0) + +/** + * @details Set dummy cycle number (Only for DMM mode and DMA mode) as SPIM default + * \hideinitializer + */ +#define SPIM_SET_DEFAULT_DCNUM(x) (SPIM->CTL2 &= ~SPIM_CTL2_USETEN_Msk) + + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Function Prototypes */ +/*---------------------------------------------------------------------------------------------------------*/ + + +int SPIM_InitFlash(int clrWP); +uint32_t SPIM_GetSClkFreq(void); +void SPIM_ReadJedecId(uint8_t idBuf[], uint32_t u32NRx, uint32_t u32NBit); +int SPIM_Enable_4Bytes_Mode(int isEn, uint32_t u32NBit); +int SPIM_Is4ByteModeEnable(uint32_t u32NBit); + +void SPIM_ChipErase(uint32_t u32NBit, int isSync); +void SPIM_EraseBlock(uint32_t u32Addr, int is4ByteAddr, uint8_t u8ErsCmd, uint32_t u32NBit, int isSync); + +void SPIM_IO_Write(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint8_t wrCmd, uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat); +void SPIM_IO_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[], uint8_t rdCmd, uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat, int u32NDummy); + +void SPIM_DMA_Write(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint32_t wrCmd); +void SPIM_DMA_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[], uint32_t u32RdCmd, int isSync); + +void SPIM_EnterDirectMapMode(int is4ByteAddr, uint32_t u32RdCmd, uint32_t u32IdleIntvl); +void SPIM_ExitDirectMapMode(void); + +void SPIM_SetQuadEnable(int isEn, uint32_t u32NBit); + +void SPIM_WinbondUnlock(uint32_t u32NBit); + +/*@}*/ /* end of group SPIM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SPIM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_SPIM_H__ */ + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_sys.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_sys.h new file mode 100644 index 0000000000000000000000000000000000000000..a476699c2af217c0233369b0484988237f27aeb7 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_sys.h @@ -0,0 +1,1636 @@ +/**************************************************************************//** + * @file SYS.h + * @version V3.0 + * @brief M480 Series SYS Driver Header File + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ + +#ifndef __NU_SYS_H__ +#define __NU_SYS_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SYS_Driver SYS Driver + @{ +*/ + +/** @addtogroup SYS_EXPORTED_CONSTANTS SYS Exported Constants + @{ +*/ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Module Reset Control Resister constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define PDMA_RST ((0UL<<24) | SYS_IPRST0_PDMARST_Pos) /*!< Reset PDMA \hideinitializer*/ +#define EBI_RST ((0UL<<24) | SYS_IPRST0_EBIRST_Pos) /*!< Reset EBI \hideinitializer*/ +#define EMAC_RST ((0UL<<24) | SYS_IPRST0_EMACRST_Pos) /*!< Reset EMAC \hideinitializer */ +#define SDH0_RST ((0UL<<24) | SYS_IPRST0_SDH0RST_Pos) /*!< Reset SDH0 \hideinitializer */ +#define CRC_RST ((0UL<<24) | SYS_IPRST0_CRCRST_Pos) /*!< Reset CRC \hideinitializer */ +#define CCAP_RST ((0UL<<24) | SYS_IPRST0_CCAPRST_Pos) /*!< Reset ICAP \hideinitializer */ +#define HSUSBD_RST ((0UL<<24) | SYS_IPRST0_HSUSBDRST_Pos) /*!< Reset HSUSBD \hideinitializer */ +#define CRPT_RST ((0UL<<24) | SYS_IPRST0_CRPTRST_Pos) /*!< Reset CRPT \hideinitializer */ +#define SPIM_RST ((0UL<<24) | SYS_IPRST0_SPIMRST_Pos) /*!< Reset SPIM \hideinitializer */ +#define USBH_RST ((0UL<<24) | SYS_IPRST0_USBHRST_Pos) /*!< Reset USBH \hideinitializer */ +#define SDH1_RST ((0UL<<24) | SYS_IPRST0_SDH1RST_Pos) /*!< Reset SDH1 \hideinitializer */ + +#define GPIO_RST ((4UL<<24) | SYS_IPRST1_GPIORST_Pos) /*!< Reset GPIO \hideinitializer */ +#define TMR0_RST ((4UL<<24) | SYS_IPRST1_TMR0RST_Pos) /*!< Reset TMR0 \hideinitializer */ +#define TMR1_RST ((4UL<<24) | SYS_IPRST1_TMR1RST_Pos) /*!< Reset TMR1 \hideinitializer */ +#define TMR2_RST ((4UL<<24) | SYS_IPRST1_TMR2RST_Pos) /*!< Reset TMR2 \hideinitializer */ +#define TMR3_RST ((4UL<<24) | SYS_IPRST1_TMR3RST_Pos) /*!< Reset TMR3 \hideinitializer */ +#define ACMP01_RST ((4UL<<24) | SYS_IPRST1_ACMP01RST_Pos) /*!< Reset ACMP01 \hideinitializer */ +#define I2C0_RST ((4UL<<24) | SYS_IPRST1_I2C0RST_Pos) /*!< Reset I2C0 \hideinitializer */ +#define I2C1_RST ((4UL<<24) | SYS_IPRST1_I2C1RST_Pos) /*!< Reset I2C1 \hideinitializer */ +#define I2C2_RST ((4UL<<24) | SYS_IPRST1_I2C2RST_Pos) /*!< Reset I2C2 \hideinitializer */ +#define QSPI0_RST ((4UL<<24) | SYS_IPRST1_QSPI0RST_Pos) /*!< Reset QSPI0 \hideinitializer */ +#define SPI0_RST ((4UL<<24) | SYS_IPRST1_SPI0RST_Pos) /*!< Reset SPI0 \hideinitializer */ +#define SPI1_RST ((4UL<<24) | SYS_IPRST1_SPI1RST_Pos) /*!< Reset SPI1 \hideinitializer */ +#define SPI2_RST ((4UL<<24) | SYS_IPRST1_SPI2RST_Pos) /*!< Reset SPI2 \hideinitializer */ +#define UART0_RST ((4UL<<24) | SYS_IPRST1_UART0RST_Pos) /*!< Reset UART0 \hideinitializer */ +#define UART1_RST ((4UL<<24) | SYS_IPRST1_UART1RST_Pos) /*!< Reset UART1 \hideinitializer */ +#define UART2_RST ((4UL<<24) | SYS_IPRST1_UART2RST_Pos) /*!< Reset UART2 \hideinitializer */ +#define UART3_RST ((4UL<<24) | SYS_IPRST1_UART3RST_Pos) /*!< Reset UART3 \hideinitializer */ +#define UART4_RST ((4UL<<24) | SYS_IPRST1_UART4RST_Pos) /*!< Reset UART4 \hideinitializer */ +#define UART5_RST ((4UL<<24) | SYS_IPRST1_UART5RST_Pos) /*!< Reset UART5 \hideinitializer */ +#define UART6_RST ((4UL<<24) | SYS_IPRST1_UART6RST_Pos) /*!< Reset UART6 \hideinitializer */ +#define UART7_RST ((4UL<<24) | SYS_IPRST1_UART7RST_Pos) /*!< Reset UART7 \hideinitializer */ +#define CAN0_RST ((4UL<<24) | SYS_IPRST1_CAN0RST_Pos) /*!< Reset CAN0 \hideinitializer */ +#define CAN1_RST ((4UL<<24) | SYS_IPRST1_CAN1RST_Pos) /*!< Reset CAN1 \hideinitializer */ +#define OTG_RST ((4UL<<24) | SYS_IPRST1_OTGRST_Pos) /*!< Reset OTG \hideinitializer */ +#define USBD_RST ((4UL<<24) | SYS_IPRST1_USBDRST_Pos) /*!< Reset USBD \hideinitializer */ +#define EADC_RST ((4UL<<24) | SYS_IPRST1_EADCRST_Pos) /*!< Reset EADC \hideinitializer */ +#define I2S0_RST ((4UL<<24) | SYS_IPRST1_I2S0RST_Pos) /*!< Reset I2S0 \hideinitializer */ +#define HSOTG_RST ((4UL<<24) | SYS_IPRST1_HSOTGRST_Pos) /*!< Reset HSOTG \hideinitializer */ +#define TRNG_RST ((4UL<<24) | SYS_IPRST1_TRNGRST_Pos) /*!< Reset TRNG \hideinitializer */ + +#define SC0_RST ((8UL<<24) | SYS_IPRST2_SC0RST_Pos) /*!< Reset SC0 \hideinitializer */ +#define SC1_RST ((8UL<<24) | SYS_IPRST2_SC1RST_Pos) /*!< Reset SC1 \hideinitializer */ +#define SC2_RST ((8UL<<24) | SYS_IPRST2_SC2RST_Pos) /*!< Reset SC2 \hideinitializer */ +#define QSPI1_RST ((8UL<<24) | SYS_IPRST2_QSPI1RST_Pos) /*!< Reset QSPI1 \hideinitializer */ +#define SPI3_RST ((8UL<<24) | SYS_IPRST2_SPI3RST_Pos) /*!< Reset SPI3 \hideinitializer */ +#define USCI0_RST ((8UL<<24) | SYS_IPRST2_USCI0RST_Pos) /*!< Reset USCI0 \hideinitializer */ +#define USCI1_RST ((8UL<<24) | SYS_IPRST2_USCI1RST_Pos) /*!< Reset USCI1 \hideinitializer */ +#define DAC_RST ((8UL<<24) | SYS_IPRST2_DACRST_Pos) /*!< Reset DAC \hideinitializer */ +#define EPWM0_RST ((8UL<<24) | SYS_IPRST2_EPWM0RST_Pos) /*!< Reset EPWM0 \hideinitializer */ +#define EPWM1_RST ((8UL<<24) | SYS_IPRST2_EPWM1RST_Pos) /*!< Reset EPWM1 \hideinitializer */ +#define BPWM0_RST ((8UL<<24) | SYS_IPRST2_BPWM0RST_Pos) /*!< Reset BPWM0 \hideinitializer */ +#define BPWM1_RST ((8UL<<24) | SYS_IPRST2_BPWM1RST_Pos) /*!< Reset BPWM1 \hideinitializer */ +#define QEI0_RST ((8UL<<24) | SYS_IPRST2_QEI0RST_Pos) /*!< Reset QEI0 \hideinitializer */ +#define QEI1_RST ((8UL<<24) | SYS_IPRST2_QEI1RST_Pos) /*!< Reset QEI1 \hideinitializer */ +#define ECAP0_RST ((8UL<<24) | SYS_IPRST2_ECAP0RST_Pos) /*!< Reset ECAP0 \hideinitializer */ +#define ECAP1_RST ((8UL<<24) | SYS_IPRST2_ECAP1RST_Pos) /*!< Reset ECAP1 \hideinitializer */ +#define CAN2_RST ((8UL<<24) | SYS_IPRST2_CAN2RST_Pos) /*!< Reset CAN2 \hideinitializer */ +#define OPA_RST ((8UL<<24) | SYS_IPRST2_OPARST_Pos) /*!< Reset OPA \hideinitializer */ +#define EADC1_RST ((8UL<<24) | SYS_IPRST2_EADC1RST_Pos) /*!< Reset EADC1 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Brown Out Detector Threshold Voltage Selection constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define SYS_BODCTL_BOD_RST_EN (1UL << SYS_BODCTL_BODRSTEN_Pos) /*!< Brown-out Reset Enable \hideinitializer */ +#define SYS_BODCTL_BOD_INTERRUPT_EN (0UL << SYS_BODCTL_BODRSTEN_Pos) /*!< Brown-out Interrupt Enable \hideinitializer */ +#define SYS_BODCTL_BODVL_3_0V (7UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 3.0V \hideinitializer */ +#define SYS_BODCTL_BODVL_2_8V (6UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.8V \hideinitializer */ +#define SYS_BODCTL_BODVL_2_6V (5UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.6V \hideinitializer */ +#define SYS_BODCTL_BODVL_2_4V (4UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.4V \hideinitializer */ +#define SYS_BODCTL_BODVL_2_2V (3UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.2V \hideinitializer */ +#define SYS_BODCTL_BODVL_2_0V (2UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.0V \hideinitializer */ +#define SYS_BODCTL_BODVL_1_8V (1UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 1.8V \hideinitializer */ +#define SYS_BODCTL_BODVL_1_6V (0UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 1.6V \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* VREFCTL constant definitions. (Write-Protection Register) */ +/*---------------------------------------------------------------------------------------------------------*/ +#define SYS_VREFCTL_VREF_PIN (0x0UL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = Vref pin \hideinitializer */ +#define SYS_VREFCTL_VREF_1_6V (0x3UL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 1.6V \hideinitializer */ +#define SYS_VREFCTL_VREF_2_0V (0x7UL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 2.0V \hideinitializer */ +#define SYS_VREFCTL_VREF_2_5V (0xBUL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 2.5V \hideinitializer */ +#define SYS_VREFCTL_VREF_3_0V (0xFUL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 3.0V \hideinitializer */ +#define SYS_VREFCTL_VREF_AVDD (0x10UL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = AVDD \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* USBPHY constant definitions. (Write-Protection Register) */ +/*---------------------------------------------------------------------------------------------------------*/ +#define SYS_USBPHY_USBROLE_STD_USBD (0x0UL << SYS_USBPHY_USBROLE_Pos) /*!< Standard USB device \hideinitializer */ +#define SYS_USBPHY_USBROLE_STD_USBH (0x1UL << SYS_USBPHY_USBROLE_Pos) /*!< Standard USB host \hideinitializer */ +#define SYS_USBPHY_USBROLE_ID_DEPH (0x2UL << SYS_USBPHY_USBROLE_Pos) /*!< ID dependent device \hideinitializer */ +#define SYS_USBPHY_USBROLE_ON_THE_GO (0x3UL << SYS_USBPHY_USBROLE_Pos) /*!< On-The-Go device \hideinitializer */ +#define SYS_USBPHY_HSUSBROLE_STD_USBD (0x0UL << SYS_USBPHY_HSUSBROLE_Pos) /*!< Standard HSUSB device \hideinitializer */ +#define SYS_USBPHY_HSUSBROLE_STD_USBH (0x1UL << SYS_USBPHY_HSUSBROLE_Pos) /*!< Standard HSUSB host \hideinitializer */ +#define SYS_USBPHY_HSUSBROLE_ID_DEPH (0x2UL << SYS_USBPHY_HSUSBROLE_Pos) /*!< ID dependent device \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* PLCTL constant definitions. (Write-Protection Register) */ +/*---------------------------------------------------------------------------------------------------------*/ +#define SYS_PLCTL_PLSEL_PL0 (0x0UL<GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA0MFP_Msk) ) | SYS_GPA_MFPL_PA0_MFP_SC0_CLK ; + +*/ +/********************* Bit definition of GPA_MFPL register **********************/ +#define SYS_GPA_MFPL_PA0MFP_GPIO (0x00UL<BODCTL |= SYS_BODCTL_BODIF_Msk) + +/** + * @brief Set Brown-out detector function to normal mode + * @param None + * @return None + * @details This macro set Brown-out detector to normal mode. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_CLEAR_BOD_LPM() (SYS->BODCTL &= ~SYS_BODCTL_BODLPM_Msk) + +/** + * @brief Disable Brown-out detector function + * @param None + * @return None + * @details This macro disable Brown-out detector function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_DISABLE_BOD() (SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk) + +/** + * @brief Enable Brown-out detector function + * @param None + * @return None + * @details This macro enable Brown-out detector function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_ENABLE_BOD() (SYS->BODCTL |= SYS_BODCTL_BODEN_Msk) + +/** + * @brief Get Brown-out detector interrupt flag + * @param None + * @retval 0 Brown-out detect interrupt flag is not set. + * @retval >=1 Brown-out detect interrupt flag is set. + * @details This macro get Brown-out detector interrupt flag. + * \hideinitializer + */ +#define SYS_GET_BOD_INT_FLAG() (SYS->BODCTL & SYS_BODCTL_BODIF_Msk) + +/** + * @brief Get Brown-out detector status + * @param None + * @retval 0 System voltage is higher than BOD threshold voltage setting or BOD function is disabled. + * @retval >=1 System voltage is lower than BOD threshold voltage setting. + * @details This macro get Brown-out detector output status. + * If the BOD function is disabled, this function always return 0. + * \hideinitializer + */ +#define SYS_GET_BOD_OUTPUT() (SYS->BODCTL & SYS_BODCTL_BODOUT_Msk) + +/** + * @brief Enable Brown-out detector interrupt function + * @param None + * @return None + * @details This macro enable Brown-out detector interrupt function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_DISABLE_BOD_RST() (SYS->BODCTL &= ~SYS_BODCTL_BODRSTEN_Msk) + +/** + * @brief Enable Brown-out detector reset function + * @param None + * @return None + * @details This macro enable Brown-out detect reset function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_ENABLE_BOD_RST() (SYS->BODCTL |= SYS_BODCTL_BODRSTEN_Msk) + +/** + * @brief Set Brown-out detector function low power mode + * @param None + * @return None + * @details This macro set Brown-out detector to low power mode. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_SET_BOD_LPM() (SYS->BODCTL |= SYS_BODCTL_BODLPM_Msk) + +/** + * @brief Set Brown-out detector voltage level + * @param[in] u32Level is Brown-out voltage level. Including : + * - \ref SYS_BODCTL_BODVL_3_0V + * - \ref SYS_BODCTL_BODVL_2_8V + * - \ref SYS_BODCTL_BODVL_2_6V + * - \ref SYS_BODCTL_BODVL_2_4V + * - \ref SYS_BODCTL_BODVL_2_2V + * - \ref SYS_BODCTL_BODVL_2_0V + * - \ref SYS_BODCTL_BODVL_1_8V + * - \ref SYS_BODCTL_BODVL_1_6V + * @return None + * @details This macro set Brown-out detector voltage level. + * The write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_SET_BOD_LEVEL(u32Level) (SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | (u32Level)) + +/** + * @brief Get reset source is from Brown-out detector reset + * @param None + * @retval 0 Previous reset source is not from Brown-out detector reset + * @retval >=1 Previous reset source is from Brown-out detector reset + * @details This macro get previous reset source is from Brown-out detect reset or not. + * \hideinitializer + */ +#define SYS_IS_BOD_RST() (SYS->RSTSTS & SYS_RSTSTS_BODRF_Msk) + +/** + * @brief Get reset source is from CPU reset + * @param None + * @retval 0 Previous reset source is not from CPU reset + * @retval >=1 Previous reset source is from CPU reset + * @details This macro get previous reset source is from CPU reset. + * \hideinitializer + */ +#define SYS_IS_CPU_RST() (SYS->RSTSTS & SYS_RSTSTS_CPURF_Msk) + +/** + * @brief Get reset source is from LVR Reset + * @param None + * @retval 0 Previous reset source is not from Low-Voltage-Reset + * @retval >=1 Previous reset source is from Low-Voltage-Reset + * @details This macro get previous reset source is from Low-Voltage-Reset. + * \hideinitializer + */ +#define SYS_IS_LVR_RST() (SYS->RSTSTS & SYS_RSTSTS_LVRF_Msk) + +/** + * @brief Get reset source is from Power-on Reset + * @param None + * @retval 0 Previous reset source is not from Power-on Reset + * @retval >=1 Previous reset source is from Power-on Reset + * @details This macro get previous reset source is from Power-on Reset. + * \hideinitializer + */ +#define SYS_IS_POR_RST() (SYS->RSTSTS & SYS_RSTSTS_PORF_Msk) + +/** + * @brief Get reset source is from reset pin reset + * @param None + * @retval 0 Previous reset source is not from reset pin reset + * @retval >=1 Previous reset source is from reset pin reset + * @details This macro get previous reset source is from reset pin reset. + * \hideinitializer + */ +#define SYS_IS_RSTPIN_RST() (SYS->RSTSTS & SYS_RSTSTS_PINRF_Msk) + +/** + * @brief Get reset source is from system reset + * @param None + * @retval 0 Previous reset source is not from system reset + * @retval >=1 Previous reset source is from system reset + * @details This macro get previous reset source is from system reset. + * \hideinitializer + */ +#define SYS_IS_SYSTEM_RST() (SYS->RSTSTS & SYS_RSTSTS_SYSRF_Msk) + +/** + * @brief Get reset source is from window watch dog reset + * @param None + * @retval 0 Previous reset source is not from window watch dog reset + * @retval >=1 Previous reset source is from window watch dog reset + * @details This macro get previous reset source is from window watch dog reset. + * \hideinitializer + */ +#define SYS_IS_WDT_RST() (SYS->RSTSTS & SYS_RSTSTS_WDTRF_Msk) + +/** + * @brief Disable Low-Voltage-Reset function + * @param None + * @return None + * @details This macro disable Low-Voltage-Reset function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_DISABLE_LVR() (SYS->BODCTL &= ~SYS_BODCTL_LVREN_Msk) + +/** + * @brief Enable Low-Voltage-Reset function + * @param None + * @return None + * @details This macro enable Low-Voltage-Reset function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_ENABLE_LVR() (SYS->BODCTL |= SYS_BODCTL_LVREN_Msk) + +/** + * @brief Disable Power-on Reset function + * @param None + * @return None + * @details This macro disable Power-on Reset function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_DISABLE_POR() (((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0) ? (SYS->PORCTL = 0x5AA5):(SYS->PORDISAN = 0x5AA5)) + +/** + * @brief Enable Power-on Reset function + * @param None + * @return None + * @details This macro enable Power-on Reset function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_ENABLE_POR() (((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0) ? (SYS->PORCTL = 0):(SYS->PORDISAN = 0)) + +/** + * @brief Clear reset source flag + * @param[in] u32RstSrc is reset source. Including : + * - \ref SYS_RSTSTS_PORF_Msk + * - \ref SYS_RSTSTS_PINRF_Msk + * - \ref SYS_RSTSTS_WDTRF_Msk + * - \ref SYS_RSTSTS_LVRF_Msk + * - \ref SYS_RSTSTS_BODRF_Msk + * - \ref SYS_RSTSTS_SYSRF_Msk + * - \ref SYS_RSTSTS_CPURF_Msk + * - \ref SYS_RSTSTS_CPULKRF_Msk + * @return None + * @details This macro clear reset source flag. + * \hideinitializer + */ +#define SYS_CLEAR_RST_SOURCE(u32RstSrc) ((SYS->RSTSTS) = (u32RstSrc) ) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* static inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void SYS_UnlockReg(void); +__STATIC_INLINE void SYS_LockReg(void); + +/** + * @brief Disable register write-protection function + * @param None + * @return None + * @details This function disable register write-protection function. + * To unlock the protected register to allow write access. + */ +__STATIC_INLINE void SYS_UnlockReg(void) +{ + do + { + SYS->REGLCTL = 0x59UL; + SYS->REGLCTL = 0x16UL; + SYS->REGLCTL = 0x88UL; + } + while(SYS->REGLCTL == 0UL); +} + +/** + * @brief Enable register write-protection function + * @param None + * @return None + * @details This function is used to enable register write-protection function. + * To lock the protected register to forbid write access. + */ +__STATIC_INLINE void SYS_LockReg(void) +{ + SYS->REGLCTL = 0UL; +} + + +void SYS_ClearResetSrc(uint32_t u32Src); +uint32_t SYS_GetBODStatus(void); +uint32_t SYS_GetResetSrc(void); +uint32_t SYS_IsRegLocked(void); +uint32_t SYS_ReadPDID(void); +void SYS_ResetChip(void); +void SYS_ResetCPU(void); +void SYS_ResetModule(uint32_t u32ModuleIndex); +void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel); +void SYS_DisableBOD(void); +void SYS_SetPowerLevel(uint32_t u32PowerLevel); +void SYS_SetVRef(uint32_t u32VRefCTL); + +/*@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SYS_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_SYS_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_timer.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_timer.h new file mode 100644 index 0000000000000000000000000000000000000000..f889abf09f05266e68f9a0dc35a4af2ae6803417 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_timer.h @@ -0,0 +1,523 @@ +/**************************************************************************//** + * @file nu_timer.h + * @version V1.00 + * @brief M480 series Timer Controller(Timer) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_TIMER_H__ +#define __NU_TIMER_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup TIMER_Driver TIMER Driver + @{ +*/ + +/** @addtogroup TIMER_EXPORTED_CONSTANTS TIMER Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* TIMER Operation Mode, External Counter and Capture Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TIMER_ONESHOT_MODE (0UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in one-shot mode \hideinitializer */ +#define TIMER_PERIODIC_MODE (1UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in periodic mode \hideinitializer */ +#define TIMER_TOGGLE_MODE (2UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in toggle-output mode \hideinitializer */ +#define TIMER_CONTINUOUS_MODE (3UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in continuous counting mode \hideinitializer */ +#define TIMER_TOUT_PIN_FROM_TMX (0UL << TIMER_CTL_TGLPINSEL_Pos) /*!< Timer toggle-output pin is from TMx pin \hideinitializer */ +#define TIMER_TOUT_PIN_FROM_TMX_EXT (1UL << TIMER_CTL_TGLPINSEL_Pos) /*!< Timer toggle-output pin is from TMx_EXT pin \hideinitializer */ + +#define TIMER_COUNTER_EVENT_FALLING (0UL << TIMER_EXTCTL_CNTPHASE_Pos) /*!< Counter increase on falling edge detection \hideinitializer */ +#define TIMER_COUNTER_EVENT_RISING (1UL << TIMER_EXTCTL_CNTPHASE_Pos) /*!< Counter increase on rising edge detection \hideinitializer */ +#define TIMER_CAPTURE_FREE_COUNTING_MODE (0UL << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< Timer capture event to get timer counter value \hideinitializer */ +#define TIMER_CAPTURE_COUNTER_RESET_MODE (1UL << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< Timer capture event to reset timer counter \hideinitializer */ + +#define TIMER_CAPTURE_EVENT_FALLING (0UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Falling edge detection to trigger capture event \hideinitializer */ +#define TIMER_CAPTURE_EVENT_RISING (1UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Rising edge detection to trigger capture event \hideinitializer */ +#define TIMER_CAPTURE_EVENT_FALLING_RISING (2UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Both falling and rising edge detection to trigger capture event, and first event at falling edge \hideinitializer */ +#define TIMER_CAPTURE_EVENT_RISING_FALLING (3UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Both rising and falling edge detection to trigger capture event, and first event at rising edge \hideinitializer */ +#define TIMER_CAPTURE_EVENT_GET_LOW_PERIOD (6UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< First capture event is at falling edge, follows are at at rising edge \hideinitializer */ +#define TIMER_CAPTURE_EVENT_GET_HIGH_PERIOD (7UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< First capture event is at rising edge, follows are at at falling edge \hideinitializer */ + +#define TIMER_TRGSRC_TIMEOUT_EVENT (0UL << TIMER_TRGCTL_TRGSSEL_Pos) /*!< Select internal trigger source from timer time-out event \hideinitializer */ +#define TIMER_TRGSRC_CAPTURE_EVENT (1UL << TIMER_TRGCTL_TRGSSEL_Pos) /*!< Select internal trigger source from timer capture event \hideinitializer */ +#define TIMER_TRG_TO_EPWM (TIMER_TRGCTL_TRGEPWM_Msk) /*!< Each timer event as EPWM counter clock source \hideinitializer */ +#define TIMER_TRG_TO_EADC (TIMER_TRGCTL_TRGEADC_Msk) /*!< Each timer event to start ADC conversion \hideinitializer */ +#define TIMER_TRG_TO_DAC (TIMER_TRGCTL_TRGDAC_Msk) /*!< Each timer event to start DAC conversion \hideinitializer */ +#define TIMER_TRG_TO_PDMA (TIMER_TRGCTL_TRGPDMA_Msk) /*!< Each timer event to trigger PDMA transfer \hideinitializer */ + +/*@}*/ /* end of group TIMER_EXPORTED_CONSTANTS */ + + +/** @addtogroup TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions + @{ +*/ + +/** + * @brief Set Timer Compared Value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Value Timer compare value. Valid values are between 2 to 0xFFFFFF. + * + * @return None + * + * @details This macro is used to set timer compared value to adjust timer time-out interval. + * @note 1. Never write 0x0 or 0x1 in this field, or the core will run into unknown state. \n + * 2. If update timer compared value in continuous counting mode, timer counter value will keep counting continuously. \n + * But if timer is operating at other modes, the timer up counter will restart counting and start from 0. + * \hideinitializer + */ +#define TIMER_SET_CMP_VALUE(timer, u32Value) ((timer)->CMP = (u32Value)) + +/** + * @brief Set Timer Prescale Value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Value Timer prescale value. Valid values are between 0 to 0xFF. + * + * @return None + * + * @details This macro is used to set timer prescale value and timer source clock will be divided by (prescale + 1) \n + * before it is fed into timer. + * \hideinitializer + */ +#define TIMER_SET_PRESCALE_VALUE(timer, u32Value) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_PSC_Msk) | (u32Value)) + +/** + * @brief Check specify Timer Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer 24-bit up counter is inactive + * @retval 1 Timer 24-bit up counter is active + * + * @details This macro is used to check if specify Timer counter is inactive or active. + * \hideinitializer + */ +#define TIMER_IS_ACTIVE(timer) (((timer)->CTL & TIMER_CTL_ACTSTS_Msk)? 1 : 0) + +/** + * @brief Select Toggle-output Pin + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32ToutSel Toggle-output pin selection, valid values are: + * - \ref TIMER_TOUT_PIN_FROM_TMX + * - \ref TIMER_TOUT_PIN_FROM_TMX_EXT + * + * @return None + * + * @details This macro is used to select timer toggle-output pin is output on TMx or TMx_EXT pin. + * \hideinitializer + */ +#define TIMER_SELECT_TOUT_PIN(timer, u32ToutSel) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_TGLPINSEL_Msk) | (u32ToutSel)) + +/** + * @brief Select Timer operating mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32OpMode Operation mode. Possible options are + * - \ref TIMER_ONESHOT_MODE + * - \ref TIMER_PERIODIC_MODE + * - \ref TIMER_TOGGLE_MODE + * - \ref TIMER_CONTINUOUS_MODE + * + * @return None + * \hideinitializer + */ +#define TIMER_SET_OPMODE(timer, u32OpMode) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_OPMODE_Msk) | (u32OpMode)) + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void TIMER_Start(TIMER_T *timer); +__STATIC_INLINE void TIMER_Stop(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableWakeup(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableWakeup(TIMER_T *timer); +__STATIC_INLINE void TIMER_StartCapture(TIMER_T *timer); +__STATIC_INLINE void TIMER_StopCapture(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableInt(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableInt(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableCaptureInt(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableCaptureInt(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer); +__STATIC_INLINE void TIMER_ClearIntFlag(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer); +__STATIC_INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer); +__STATIC_INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetCounter(TIMER_T *timer); +__STATIC_INLINE void TIMER_ResetCounter(TIMER_T *timer); + +/** + * @brief Start Timer Counting + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to start Timer counting. + */ +__STATIC_INLINE void TIMER_Start(TIMER_T *timer) +{ + timer->CTL |= TIMER_CTL_CNTEN_Msk; +} + +/** + * @brief Stop Timer Counting + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to stop/suspend Timer counting. + */ +__STATIC_INLINE void TIMER_Stop(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_CNTEN_Msk; +} + +/** + * @brief Enable Timer Interrupt Wake-up Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the timer interrupt wake-up function and interrupt source could be time-out interrupt, \n + * counter event interrupt or capture trigger interrupt. + * @note To wake the system from Power-down mode, timer clock source must be ether LXT or LIRC. + */ +__STATIC_INLINE void TIMER_EnableWakeup(TIMER_T *timer) +{ + timer->CTL |= TIMER_CTL_WKEN_Msk; +} + +/** + * @brief Disable Timer Wake-up Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the timer interrupt wake-up function. + */ +__STATIC_INLINE void TIMER_DisableWakeup(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_WKEN_Msk; +} + +/** + * @brief Start Timer Capture Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to start Timer capture function. + */ +__STATIC_INLINE void TIMER_StartCapture(TIMER_T *timer) +{ + timer->EXTCTL |= TIMER_EXTCTL_CAPEN_Msk; +} + +/** + * @brief Stop Timer Capture Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to stop Timer capture function. + */ +__STATIC_INLINE void TIMER_StopCapture(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CAPEN_Msk; +} + +/** + * @brief Enable Capture Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the detect de-bounce function of capture pin. + */ +__STATIC_INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer) +{ + timer->EXTCTL |= TIMER_EXTCTL_CAPDBEN_Msk; +} + +/** + * @brief Disable Capture Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the detect de-bounce function of capture pin. + */ +__STATIC_INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CAPDBEN_Msk; +} + +/** + * @brief Enable Counter Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the detect de-bounce function of counter pin. + */ +__STATIC_INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer) +{ + timer->EXTCTL |= TIMER_EXTCTL_CNTDBEN_Msk; +} + +/** + * @brief Disable Counter Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the detect de-bounce function of counter pin. + */ +__STATIC_INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CNTDBEN_Msk; +} + +/** + * @brief Enable Timer Time-out Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the timer time-out interrupt function. + */ +__STATIC_INLINE void TIMER_EnableInt(TIMER_T *timer) +{ + timer->CTL |= TIMER_CTL_INTEN_Msk; +} + +/** + * @brief Disable Timer Time-out Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the timer time-out interrupt function. + */ +__STATIC_INLINE void TIMER_DisableInt(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_INTEN_Msk; +} + +/** + * @brief Enable Capture Trigger Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the timer capture trigger interrupt function. + */ +__STATIC_INLINE void TIMER_EnableCaptureInt(TIMER_T *timer) +{ + timer->EXTCTL |= TIMER_EXTCTL_CAPIEN_Msk; +} + +/** + * @brief Disable Capture Trigger Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the timer capture trigger interrupt function. + */ +__STATIC_INLINE void TIMER_DisableCaptureInt(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CAPIEN_Msk; +} + +/** + * @brief Get Timer Time-out Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer time-out interrupt did not occur + * @retval 1 Timer time-out interrupt occurred + * + * @details This function indicates timer time-out interrupt occurred or not. + */ +__STATIC_INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer) +{ + return ((timer->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1UL : 0UL); +} + +/** + * @brief Clear Timer Time-out Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function clears timer time-out interrupt flag to 0. + */ +__STATIC_INLINE void TIMER_ClearIntFlag(TIMER_T *timer) +{ + timer->INTSTS = TIMER_INTSTS_TIF_Msk; +} + +/** + * @brief Get Timer Capture Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer capture interrupt did not occur + * @retval 1 Timer capture interrupt occurred + * + * @details This function indicates timer capture trigger interrupt occurred or not. + */ +__STATIC_INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer) +{ + return timer->EINTSTS; +} + +/** + * @brief Clear Timer Capture Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function clears timer capture trigger interrupt flag to 0. + */ +__STATIC_INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer) +{ + timer->EINTSTS = TIMER_EINTSTS_CAPIF_Msk; +} + +/** + * @brief Get Timer Wake-up Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer does not cause CPU wake-up + * @retval 1 Timer interrupt event cause CPU wake-up + * + * @details This function indicates timer interrupt event has waked up system or not. + */ +__STATIC_INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer) +{ + return (timer->INTSTS & TIMER_INTSTS_TWKF_Msk ? 1UL : 0UL); +} + +/** + * @brief Clear Timer Wake-up Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function clears the timer wake-up system flag to 0. + */ +__STATIC_INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer) +{ + timer->INTSTS = TIMER_INTSTS_TWKF_Msk; +} + +/** + * @brief Get Capture value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return 24-bit Capture Value + * + * @details This function reports the current 24-bit timer capture value. + */ +__STATIC_INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer) +{ + return timer->CAP; +} + +/** + * @brief Get Counter value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return 24-bit Counter Value + * + * @details This function reports the current 24-bit timer counter value. + */ +__STATIC_INLINE uint32_t TIMER_GetCounter(TIMER_T *timer) +{ + return timer->CNT; +} + +/** + * @brief Reset Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to reset current counter value and internal prescale counter value. + */ +__STATIC_INLINE void TIMER_ResetCounter(TIMER_T *timer) +{ + timer->CNT = 0UL; + while((timer->CNT&TIMER_CNT_RSTACT_Msk) == TIMER_CNT_RSTACT_Msk) + { + ; + } +} + + +uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq); +void TIMER_Close(TIMER_T *timer); +void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec); +void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge); +void TIMER_DisableCapture(TIMER_T *timer); +void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge); +void TIMER_DisableEventCounter(TIMER_T *timer); +uint32_t TIMER_GetModuleClock(TIMER_T *timer); +void TIMER_EnableFreqCounter(TIMER_T *timer, + uint32_t u32DropCount, + uint32_t u32Timeout, + uint32_t u32EnableInt); +void TIMER_DisableFreqCounter(TIMER_T *timer); +void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src); +void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask); + +/*@}*/ /* end of group TIMER_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group TIMER_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_TIMER_H__ */ + + diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_timer_pwm.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_timer_pwm.h new file mode 100644 index 0000000000000000000000000000000000000000..c7b122ff9112b1e98b4c1bd02a4c2d1270c38944 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_timer_pwm.h @@ -0,0 +1,746 @@ +/**************************************************************************//** + * @file nu_timer_pwm.h + * @version V1.00 + * @brief M480 series Timer PWM Controller(Timer PWM) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_TIMER_PWM_H__ +#define __NU_TIMER_PWM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ +/** @addtogroup TIMER_PWM_Driver TIMER PWM Driver + @{ +*/ + +/** @addtogroup TIMER_PWM_EXPORTED_CONSTANTS TIMER PWM Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* Output Channel Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_CH0 (BIT0) /*!< Indicate PWMx_CH0 \hideinitializer */ +#define TPWM_CH1 (BIT1) /*!< Indicate PWMx_CH1 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_UP_COUNT (0UL << TIMER_PWMCTL_CNTTYPE_Pos) /*!< Up count type \hideinitializer */ +#define TPWM_DOWN_COUNT (1UL << TIMER_PWMCTL_CNTTYPE_Pos) /*!< Down count type \hideinitializer */ +#define TPWM_UP_DOWN_COUNT (2UL << TIMER_PWMCTL_CNTTYPE_Pos) /*!< Up-Down count type \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_AUTO_RELOAD_MODE (0UL) /*!< Auto-reload mode \hideinitializer */ +#define TPWM_ONE_SHOT_MODE (TIMER_PWMCTL_CNTMODE_Msk) /*!< One-shot mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Output Level Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_OUTPUT_TOGGLE (0UL) /*!< Timer PWM output toggle \hideinitializer */ +#define TPWM_OUTPUT_NOTHING (1UL) /*!< Timer PWM output nothing \hideinitializer */ +#define TPWM_OUTPUT_LOW (2UL) /*!< Timer PWM output low \hideinitializer */ +#define TPWM_OUTPUT_HIGH (3UL) /*!< Timer PWM output high \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Trigger ADC Source Select Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_TRIGGER_ADC_AT_ZERO_POINT (0UL << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< Timer PWM trigger ADC while counter zero point event occurred \hideinitializer */ +#define TPWM_TRIGGER_ADC_AT_PERIOD_POINT (1UL << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< Timer PWM trigger ADC while counter period point event occurred \hideinitializer */ +#define TPWM_TRIGGER_ADC_AT_ZERO_OR_PERIOD_POINT (2UL << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< Timer PWM trigger ADC while counter zero or period point event occurred \hideinitializer */ +#define TPWM_TRIGGER_ADC_AT_COMPARE_UP_COUNT_POINT (3UL << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< Timer PWM trigger ADC while counter up count compare point event occurred \hideinitializer */ +#define TPWM_TRIGGER_ADC_AT_COMPARE_DOWN_COUNT_POINT (4UL << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< Timer PWM trigger ADC while counter down count compare point event occurred \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Brake Control Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_BRAKE_SOURCE_EDGE_ACMP0 (TIMER_PWMBRKCTL_CPO0EBEN_Msk) /*!< Comparator 0 as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_ACMP1 (TIMER_PWMBRKCTL_CPO1EBEN_Msk) /*!< Comparator 1 as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_BKPIN (TIMER_PWMBRKCTL_BRKPEEN_Msk) /*!< Brake pin as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_SYS_CSS (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_CSSBRKEN_Msk << 16)) /*!< System fail condition: clock security system detection as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_SYS_BOD (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_BODBRKEN_Msk << 16)) /*!< System fail condition: brown-out detection as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_SYS_COR (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_CORBRKEN_Msk << 16)) /*!< System fail condition: core lockup detection as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_SYS_RAM (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_RAMBRKEN_Msk << 16)) /*!< System fail condition: SRAM parity error detection as edge-detect fault brake source \hideinitializer */ + + +#define TPWM_BRAKE_SOURCE_LEVEL_ACMP0 (TIMER_PWMBRKCTL_CPO0LBEN_Msk) /*!< Comparator 0 as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_ACMP1 (TIMER_PWMBRKCTL_CPO1LBEN_Msk) /*!< Comparator 1 as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_BKPIN (TIMER_PWMBRKCTL_BRKPLEN_Msk) /*!< Brake pin as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_SYS_CSS (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_CSSBRKEN_Msk << 16)) /*!< System fail condition: clock security system detection as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_SYS_BOD (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_BODBRKEN_Msk << 16)) /*!< System fail condition: brown-out detection as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_SYS_COR (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_CORBRKEN_Msk << 16)) /*!< System fail condition: core lockup detection as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_SYS_RAM (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_RAMBRKEN_Msk << 16)) /*!< System fail condition: SRAM parity error detection as level-detect fault brake source \hideinitializer */ + +#define TPWM_BRAKE_EDGE (TIMER_PWMSWBRK_BRKETRG_Msk) /*!< Edge-detect fault brake \hideinitializer */ +#define TPWM_BRAKE_LEVEL (TIMER_PWMSWBRK_BRKLTRG_Msk) /*!< Level-detect fault brake \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Load Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_LOAD_MODE_PERIOD (0UL) /*!< Timer PWM period load mode \hideinitializer */ +#define TPWM_LOAD_MODE_IMMEDIATE (TIMER_PWMCTL_IMMLDEN_Msk) /*!< Timer PWM immediately load mode \hideinitializer */ +#define TPWM_LOAD_MODE_CENTER (TIMER_PWMCTL_CTRLD_Msk) /*!< Timer PWM center load mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Brake Pin De-bounce Clock Source Select Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_BKP_DBCLK_PCLK_DIV_1 (0UL) /*!< De-bounce clock is PCLK divide by 1 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_2 (1UL) /*!< De-bounce clock is PCLK divide by 2 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_4 (2UL) /*!< De-bounce clock is PCLK divide by 4 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_8 (3UL) /*!< De-bounce clock is PCLK divide by 8 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_16 (4UL) /*!< De-bounce clock is PCLK divide by 16 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_32 (5UL) /*!< De-bounce clock is PCLK divide by 32 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_64 (6UL) /*!< De-bounce clock is PCLK divide by 64 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_128 (7UL) /*!< De-bounce clock is PCLK divide by 128 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Brake Pin Source Select Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_TM_BRAKE0 (0UL) /*!< Brake pin source comes from TM_BRAKE0 \hideinitializer */ +#define TPWM_TM_BRAKE1 (1UL) /*!< Brake pin source comes from TM_BRAKE1 \hideinitializer */ +#define TPWM_TM_BRAKE2 (2UL) /*!< Brake pin source comes from TM_BRAKE2 \hideinitializer */ +#define TPWM_TM_BRAKE3 (3UL) /*!< Brake pin source comes from TM_BRAKE3 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Clock Source Select Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_CNTR_CLKSRC_TMR_CLK (0UL) /*!< Timer PWM Clock source selects to TMR_CLK \hideinitializer */ +#define TPWM_CNTR_CLKSRC_TIMER0_INT (1UL) /*!< Timer PWM Clock source selects to TIMER0 interrupt event \hideinitializer */ +#define TPWM_CNTR_CLKSRC_TIMER1_INT (2UL) /*!< Timer PWM Clock source selects to TIMER1 interrupt event \hideinitializer */ +#define TPWM_CNTR_CLKSRC_TIMER2_INT (3UL) /*!< Timer PWM Clock source selects to TIMER2 interrupt event \hideinitializer */ +#define TPWM_CNTR_CLKSRC_TIMER3_INT (4UL) /*!< Timer PWM Clock source selects to TIMER3 interrupt event \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Synchronous Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_CNTR_SYNC_DISABLE (0UL) /*!< Disable TIMER PWM synchronous function \hideinitializer */ +#define TPWM_CNTR_SYNC_START_BY_TIMER0 ((0<ALTCTL = (1 << TIMER_ALTCTL_FUNCSEL_Pos)) + +/** + * @brief Disable PWM Counter Mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to disable specified Timer channel as PWM counter mode, then timer counter mode is available. + * @note All registers about PWM counter function will be cleared to 0 after executing this macro. + * \hideinitializer + */ +#define TPWM_DISABLE_PWM_MODE(timer) ((timer)->ALTCTL = (0 << TIMER_ALTCTL_FUNCSEL_Pos)) + +/** + * @brief Enable Independent Mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable independent mode of TIMER PWM module and complementary mode will be disabled. + * \hideinitializer + */ +#define TPWM_ENABLE_INDEPENDENT_MODE(timer) ((timer)->PWMCTL &= ~(1 << TIMER_PWMCTL_OUTMODE_Pos)) + +/** + * @brief Enable Complementary Mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable complementary mode of Timer PWM module and independent mode will be disabled. + * \hideinitializer + */ +#define TPWM_ENABLE_COMPLEMENTARY_MODE(timer) ((timer)->PWMCTL |= (1 << TIMER_PWMCTL_OUTMODE_Pos)) + +/** + * @brief Set Counter Type + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] type Timer PWM count type, could be one of the following type + * - \ref TPWM_UP_COUNT + * - \ref TPWM_DOWN_COUNT + * - \ref TPWM_UP_DOWN_COUNT + * + * @return None + * + * @details This macro is used to set Timer PWM counter type. + * \hideinitializer + */ +#define TPWM_SET_COUNTER_TYPE(timer, type) ((timer)->PWMCTL = ((timer)->PWMCTL & ~TIMER_PWMCTL_CNTTYPE_Msk) | (type)) + +/** + * @brief Start PWM Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable PWM generator and start counter counting. + * \hideinitializer + */ +#define TPWM_START_COUNTER(timer) ((timer)->PWMCTL |= TIMER_PWMCTL_CNTEN_Msk) + +/** + * @brief Stop PWM Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to stop PWM counter after current period is completed. + * \hideinitializer + */ +#define TPWM_STOP_COUNTER(timer) ((timer)->PWMPERIOD = 0x0) + +/** + * @brief Set Counter Clock Prescaler + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] prescaler Clock prescaler of specified channel. Valid values are between 0x0~0xFFF. + * + * @return None + * + * @details This macro is used to set the prescaler of specified TIMER PWM. + * @note If prescaler is 0, then there is no scaling in counter clock source. + * \hideinitializer + */ +#define TPWM_SET_PRESCALER(timer, prescaler) ((timer)->PWMCLKPSC = (prescaler)) + +/** + * @brief Get Counter Clock Prescaler + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return Target prescaler setting, CLKPSC (TIMERx_PWMCLKPSC[11:0]) + * + * @details Get the prescaler setting, the target counter clock divider is (CLKPSC + 1). + * \hideinitializer + */ +#define TPWM_GET_PRESCALER(timer) ((timer)->PWMCLKPSC) + +/** + * @brief Set Counter Period + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] period Period of specified channel. Valid values are between 0x0~0xFFFF. + * + * @return None + * + * @details This macro is used to set the period of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_SET_PERIOD(timer, period) ((timer)->PWMPERIOD = (period)) + +/** + * @brief Get Counter Period + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return Target period setting, PERIOD (TIMERx_PWMPERIOD[15:0]) + * + * @details This macro is used to get the period of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_GET_PERIOD(timer) ((timer)->PWMPERIOD) + +/** + * @brief Set Comparator Value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] cmp Comparator of specified channel. Valid values are between 0x0~0xFFFF. + * + * @return None + * + * @details This macro is used to set the comparator value of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_SET_CMPDAT(timer, cmp) ((timer)->PWMCMPDAT = (cmp)) + +/** + * @brief Get Comparator Value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return Target comparator setting, CMPDAT (TIMERx_PWMCMPDAT[15:0]) + * + * @details This macro is used to get the comparator value of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_GET_CMPDAT(timer) ((timer)->PWMCMPDAT) + +/** + * @brief Clear Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to clear counter of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_CLEAR_COUNTER(timer) ((timer)->PWMCNTCLR = TIMER_PWMCNTCLR_CNTCLR_Msk) + +/** + * @brief Software Trigger Brake Event + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] type Type of brake trigger. Valid values are: + * - \ref TPWM_BRAKE_EDGE + * - \ref TPWM_BRAKE_LEVEL + * + * @return None + * + * @details This macro is used to trigger brake event by writing PWMSWBRK register. + * \hideinitializer + */ +#define TPWM_SW_TRIGGER_BRAKE(timer, type) ((timer)->PWMSWBRK = (type)) + +/** + * @brief Enable Output Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] ch Enable specified channel output function. Valid values are the combination of: + * - \ref TPWM_CH0 + * - \ref TPWM_CH1 + * + * @return None + * + * @details This macro is used to enable output function of specified output pins. + * @note If the corresponding bit in ch parameter is 0, then output function will be disabled in this channel. + * \hideinitializer + */ +#define TPWM_ENABLE_OUTPUT(timer, ch) ((timer)->PWMPOEN = (ch)) + +/** + * @brief Set Output Inverse + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] ch Set specified channel output is inversed or not. Valid values are the combination of: + * - \ref TPWM_CH0 + * - \ref TPWM_CH1 + * + * @return None + * + * @details This macro is used to enable output inverse of specified output pins. + * @note If ch parameter is 0, then output inverse function will be disabled. + * \hideinitializer + */ +#define TPWM_SET_OUTPUT_INVERSE(timer, ch) ((timer)->PWMPOLCTL = (ch)) + +/** + * @brief Enable Output Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] ch Enable specified channel output mask function. Valid values are the combination of: + * - \ref TPWM_CH0 + * - \ref TPWM_CH1 + * + * @param[in] level Output to high or low on specified mask channel. + * + * @return None + * + * @details This macro is used to enable output function of specified output pins. + * @note If ch parameter is 0, then output mask function will be disabled. + * \hideinitializer + */ +#define TPWM_SET_MASK_OUTPUT(timer, ch, level) do {(timer)->PWMMSKEN = (ch); (timer)->PWMMSK = (level); }while(0) + +/** + * @brief Set Counter Synchronous Mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] mode Synchronous mode. Possible options are: + * - \ref TPWM_CNTR_SYNC_DISABLE + * - \ref TPWM_CNTR_SYNC_START_BY_TIMER0 + * - \ref TPWM_CNTR_SYNC_CLEAR_BY_TIMER0 + * - \ref TPWM_CNTR_SYNC_START_BY_TIMER2 + * - \ref TPWM_CNTR_SYNC_CLEAR_BY_TIMER2 + * + * @return None + * + * @details This macro is used to set counter synchronous mode of specified Timer PWM module. + * @note Only support all PWM counters are synchronous by TIMER0 PWM or TIMER0~1 PWM counter synchronous by TIMER0 PWM and + * TIMER2~3 PWM counter synchronous by TIMER2 PWM. + * \hideinitializer + */ +#define TPWM_SET_COUNTER_SYNC_MODE(timer, mode) ((timer)->PWMSCTL = (mode)) + +/** + * @brief Trigger Counter Synchronous + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to trigger synchronous event by specified TIMER PWM. + * @note 1. This macro is only available for TIMER0 PWM and TIMER2 PWM. \n + * 2. STRGEN (PWMSTRG[0]) is write only and always read as 0. + * \hideinitializer + */ +#define TPWM_TRIGGER_COUNTER_SYNC(timer) ((timer)->PWMSTRG = TIMER_PWMSTRG_STRGEN_Msk) + +/** + * @brief Enable Zero Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable the zero event interrupt function. + * \hideinitializer + */ +#define TPWM_ENABLE_ZERO_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_ZIEN_Msk) + +/** + * @brief Disable Zero Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to disable the zero event interrupt function. + * \hideinitializer + */ +#define TPWM_DISABLE_ZERO_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_ZIEN_Msk) + +/** + * @brief Get Zero Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Zero event interrupt did not occur + * @retval 1 Zero event interrupt occurred + * + * @details This macro indicates zero event occurred or not. + * \hideinitializer + */ +#define TPWM_GET_ZERO_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_ZIF_Msk)? 1 : 0) + +/** + * @brief Clear Zero Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro clears zero event interrupt flag. + * \hideinitializer + */ +#define TPWM_CLEAR_ZERO_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_ZIF_Msk) + +/** + * @brief Enable Period Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable the period event interrupt function. + * \hideinitializer + */ +#define TPWM_ENABLE_PERIOD_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_PIEN_Msk) + +/** + * @brief Disable Period Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to disable the period event interrupt function. + * \hideinitializer + */ +#define TPWM_DISABLE_PERIOD_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_PIEN_Msk) + +/** + * @brief Get Period Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Period event interrupt did not occur + * @retval 1 Period event interrupt occurred + * + * @details This macro indicates period event occurred or not. + * \hideinitializer + */ +#define TPWM_GET_PERIOD_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_PIF_Msk)? 1 : 0) + +/** + * @brief Clear Period Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro clears period event interrupt flag. + * \hideinitializer + */ +#define TPWM_CLEAR_PERIOD_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_PIF_Msk) + +/** + * @brief Enable Compare Up Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable the compare up event interrupt function. + * \hideinitializer + */ +#define TPWM_ENABLE_CMP_UP_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_CMPUIEN_Msk) + +/** + * @brief Disable Compare Up Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to disable the compare up event interrupt function. + * \hideinitializer + */ +#define TPWM_DISABLE_CMP_UP_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_CMPUIEN_Msk) + +/** + * @brief Get Compare Up Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Compare up event interrupt did not occur + * @retval 1 Compare up event interrupt occurred + * + * @details This macro indicates compare up event occurred or not. + * \hideinitializer + */ +#define TPWM_GET_CMP_UP_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_CMPUIF_Msk)? 1 : 0) + +/** + * @brief Clear Compare Up Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro clears compare up event interrupt flag. + * \hideinitializer + */ +#define TPWM_CLEAR_CMP_UP_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_CMPUIF_Msk) + +/** + * @brief Enable Compare Down Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable the compare down event interrupt function. + * \hideinitializer + */ +#define TPWM_ENABLE_CMP_DOWN_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_CMPDIEN_Msk) + +/** + * @brief Disable Compare Down Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to disable the compare down event interrupt function. + * \hideinitializer + */ +#define TPWM_DISABLE_CMP_DOWN_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_CMPDIEN_Msk) + +/** + * @brief Get Compare Down Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Compare down event interrupt did not occur + * @retval 1 Compare down event interrupt occurred + * + * @details This macro indicates compare down event occurred or not. + * \hideinitializer + */ +#define TPWM_GET_CMP_DOWN_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_CMPDIF_Msk)? 1 : 0) + +/** + * @brief Clear Compare Down Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro clears compare down event interrupt flag. + * \hideinitializer + */ +#define TPWM_CLEAR_CMP_DOWN_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_CMPDIF_Msk) + +/** + * @brief Get Counter Reach Maximum Count Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer PWM counter never counts to maximum value + * @retval 1 Timer PWM counter counts to maximum value, 0xFFFF + * + * @details This macro indicates Timer PWM counter has count to 0xFFFF or not. + * \hideinitializer + */ +#define TPWM_GET_REACH_MAX_CNT_STATUS(timer) (((timer)->PWMSTATUS & TIMER_PWMSTATUS_CNTMAXF_Msk)? 1 : 0) + +/** + * @brief Clear Counter Reach Maximum Count Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro clears reach maximum count status. + * \hideinitializer + */ +#define TPWM_CLEAR_REACH_MAX_CNT_STATUS(timer) ((timer)->PWMSTATUS = TIMER_PWMSTATUS_CNTMAXF_Msk) + +/** + * @brief Get Trigger ADC Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Trigger ADC start conversion is not occur + * @retval 1 Specified counter compare event has trigger ADC start conversion + * + * @details This macro is used to indicate PWM counter compare event has triggered ADC start conversion. + * \hideinitializer + */ +#define TPWM_GET_TRG_ADC_STATUS(timer) (((timer)->PWMSTATUS & TIMER_PWMSTATUS_EADCTRGF_Msk)? 1 : 0) + +/** + * @brief Clear Trigger ADC Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to clear PWM counter compare event trigger ADC status. + * \hideinitializer + */ +#define TPWM_CLEAR_TRG_ADC_STATUS(timer) ((timer)->PWMSTATUS = TIMER_PWMSTATUS_EADCTRGF_Msk) + +/** + * @brief Set Brake Event at Brake Pin High or Low-to-High + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to set detect brake event when external brake pin at high level or transfer from low to high. + * @note The default brake pin detection is high level or from low to high. + * \hideinitializer + */ +#define TPWM_SET_BRAKE_PIN_HIGH_DETECT(timer) ((timer)->PWMBNF &= ~TIMER_PWMBNF_BRKPINV_Msk) + +/** + * @brief Set Brake Event at Brake Pin Low or High-to-Low + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to set detect brake event when external brake pin at low level or transfer from high to low. + * \hideinitializer + */ +#define TPWM_SET_BRAKE_PIN_LOW_DETECT(timer) ((timer)->PWMBNF |= TIMER_PWMBNF_BRKPINV_Msk) + +/** + * @brief Set External Brake Pin Source + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] pin The external brake pin source, could be one of following source + * - \ref TPWM_TM_BRAKE0 + * - \ref TPWM_TM_BRAKE1 + * - \ref TPWM_TM_BRAKE2 + * - \ref TPWM_TM_BRAKE3 + * + * @return None + * + * @details This macro is used to set detect brake event when external brake pin at high level or transfer from low to high. + * \hideinitializer + */ +#define TPWM_SET_BRAKE_PIN_SOURCE(timer, pin) ((timer)->PWMBNF = ((timer)->PWMBNF & ~TIMER_PWMBNF_BKPINSRC_Msk) | ((pin)<CTL = (TRNG->CTL&~TRNG_CTL_CLKP_Msk)|((clkpsc & 0xf)<> 4ul)-2ul) + + +/** + * @brief Calculate UART baudrate mode2 divider + * + * @param[in] u32SrcFreq UART clock frequency + * @param[in] u32BaudRate Baudrate of UART module + * + * @return UART baudrate mode2 divider + * + * @details This macro calculate UART baudrate mode2 divider. + * \hideinitializer + */ +#define UART_BAUD_MODE2_DIVIDER(u32SrcFreq, u32BaudRate) ((((u32SrcFreq) + ((u32BaudRate)/2ul)) / (u32BaudRate))-2ul) + + +/** + * @brief Write UART data + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u8Data Data byte to transmit. + * + * @return None + * + * @details This macro write Data to Tx data register. + * \hideinitializer + */ +#define UART_WRITE(uart, u8Data) ((uart)->DAT = (u8Data)) + + +/** + * @brief Read UART data + * + * @param[in] uart The pointer of the specified UART module + * + * @return The oldest data byte in RX FIFO. + * + * @details This macro read Rx data register. + * \hideinitializer + */ +#define UART_READ(uart) ((uart)->DAT) + + +/** + * @brief Get Tx empty + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Tx FIFO is not empty + * @retval >=1 Tx FIFO is empty + * + * @details This macro get Transmitter FIFO empty register value. + * \hideinitializer + */ +#define UART_GET_TX_EMPTY(uart) ((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTY_Msk) + + +/** + * @brief Get Rx empty + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Rx FIFO is not empty + * @retval >=1 Rx FIFO is empty + * + * @details This macro get Receiver FIFO empty register value. + * \hideinitializer + */ +#define UART_GET_RX_EMPTY(uart) ((uart)->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) + + +/** + * @brief Check specified UART port transmission is over. + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Tx transmission is not over + * @retval 1 Tx transmission is over + * + * @details This macro return Transmitter Empty Flag register bit value. + * It indicates if specified UART port transmission is over nor not. + * \hideinitializer + */ +#define UART_IS_TX_EMPTY(uart) (((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos) + + +/** + * @brief Wait specified UART port transmission is over + * + * @param[in] uart The pointer of the specified UART module + * + * @return None + * + * @details This macro wait specified UART port transmission is over. + * \hideinitializer + */ +#define UART_WAIT_TX_EMPTY(uart) while(!((((uart)->FIFOSTS) & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos)) + + +/** + * @brief Check RX is ready or not + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 The number of bytes in the RX FIFO is less than the RFITL + * @retval 1 The number of bytes in the RX FIFO equals or larger than RFITL + * + * @details This macro check receive data available interrupt flag is set or not. + * \hideinitializer + */ +#define UART_IS_RX_READY(uart) (((uart)->INTSTS & UART_INTSTS_RDAIF_Msk)>>UART_INTSTS_RDAIF_Pos) + + +/** + * @brief Check TX FIFO is full or not + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 1 TX FIFO is full + * @retval 0 TX FIFO is not full + * + * @details This macro check TX FIFO is full or not. + * \hideinitializer + */ +#define UART_IS_TX_FULL(uart) (((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)>>UART_FIFOSTS_TXFULL_Pos) + + +/** + * @brief Check RX FIFO is full or not + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 1 RX FIFO is full + * @retval 0 RX FIFO is not full + * + * @details This macro check RX FIFO is full or not. + * \hideinitializer + */ +#define UART_IS_RX_FULL(uart) (((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)>>UART_FIFOSTS_RXFULL_Pos) + + +/** + * @brief Get Tx full register value + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Tx FIFO is not full. + * @retval >=1 Tx FIFO is full. + * + * @details This macro get Tx full register value. + * \hideinitializer + */ +#define UART_GET_TX_FULL(uart) ((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) + + +/** + * @brief Get Rx full register value + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Rx FIFO is not full. + * @retval >=1 Rx FIFO is full. + * + * @details This macro get Rx full register value. + * \hideinitializer + */ +#define UART_GET_RX_FULL(uart) ((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk) + + +/** + * @brief Enable specified UART interrupt + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u32eIntSel Interrupt type select + * - \ref UART_INTEN_ABRIEN_Msk : Auto baud rate interrupt + * - \ref UART_INTEN_WKIEN_Msk : Wakeup interrupt + * - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt + * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt + * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt + * - \ref UART_INTEN_MODEMIEN_Msk : Modem interrupt + * - \ref UART_INTEN_RLSIEN_Msk : Rx Line status interrupt + * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt + * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt + * + * @return None + * + * @details This macro enable specified UART interrupt. + * \hideinitializer + */ +#define UART_ENABLE_INT(uart, u32eIntSel) ((uart)->INTEN |= (u32eIntSel)) + + +/** + * @brief Disable specified UART interrupt + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u32eIntSel Interrupt type select + * - \ref UART_INTEN_ABRIEN_Msk : Auto baud rate interrupt + * - \ref UART_INTEN_WKIEN_Msk : Wakeup interrupt + * - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt + * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt + * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt + * - \ref UART_INTEN_MODEMIEN_Msk : Modem status interrupt + * - \ref UART_INTEN_RLSIEN_Msk : Receive Line status interrupt + * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt + * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt + * + * @return None + * + * @details This macro enable specified UART interrupt. + * \hideinitializer + */ +#define UART_DISABLE_INT(uart, u32eIntSel) ((uart)->INTEN &= ~ (u32eIntSel)) + + +/** + * @brief Get specified interrupt flag/status + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u32eIntTypeFlag Interrupt Type Flag, should be + * - \ref UART_INTSTS_HWBUFEINT_Msk : In DMA Mode, Buffer Error Interrupt Indicator + * - \ref UART_INTSTS_HWTOINT_Msk : In DMA Mode, Time-out Interrupt Indicator + * - \ref UART_INTSTS_HWMODINT_Msk : In DMA Mode, MODEM Status Interrupt Indicator + * - \ref UART_INTSTS_HWRLSINT_Msk : In DMA Mode, Receive Line Status Interrupt Indicator + * - \ref UART_INTSTS_HWBUFEIF_Msk : In DMA Mode, Buffer Error Interrupt Flag + * - \ref UART_INTSTS_HWTOIF_Msk : In DMA Mode, Time-out Interrupt Flag + * - \ref UART_INTSTS_HWMODIF_Msk : In DMA Mode, MODEM Interrupt Flag + * - \ref UART_INTSTS_HWRLSIF_Msk : In DMA Mode, Receive Line Status Flag + * - \ref UART_INTSTS_LININT_Msk : LIN Bus Interrupt Indicator + * - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error Interrupt Indicator + * - \ref UART_INTSTS_RXTOINT_Msk : Time-out Interrupt Indicator + * - \ref UART_INTSTS_MODEMINT_Msk : Modem Status Interrupt Indicator + * - \ref UART_INTSTS_RLSINT_Msk : Receive Line Status Interrupt Indicator + * - \ref UART_INTSTS_THREINT_Msk : Transmit Holding Register Empty Interrupt Indicator + * - \ref UART_INTSTS_RDAINT_Msk : Receive Data Available Interrupt Indicator + * - \ref UART_INTSTS_LINIF_Msk : LIN Bus Flag + * - \ref UART_INTSTS_BUFERRIF_Msk : Buffer Error Interrupt Flag + * - \ref UART_INTSTS_RXTOIF_Msk : Rx Time-out Interrupt Flag + * - \ref UART_INTSTS_MODEMIF_Msk : Modem Interrupt Flag + * - \ref UART_INTSTS_RLSIF_Msk : Receive Line Status Interrupt Flag + * - \ref UART_INTSTS_THREIF_Msk : Tx Empty Interrupt Flag + * - \ref UART_INTSTS_RDAIF_Msk : Rx Ready Interrupt Flag + * + * @retval 0 The specified interrupt is not happened. + * 1 The specified interrupt is happened. + * + * @details This macro get specified interrupt flag or interrupt indicator status. + * \hideinitializer + */ +#define UART_GET_INT_FLAG(uart,u32eIntTypeFlag) (((uart)->INTSTS & (u32eIntTypeFlag))?1:0) + + +/** + * @brief Clear RS-485 Address Byte Detection Flag + * + * @param[in] uart The pointer of the specified UART module + * + * @return None + * + * @details This macro clear RS-485 address byte detection flag. + * \hideinitializer + */ +#define UART_RS485_CLEAR_ADDR_FLAG(uart) ((uart)->FIFOSTS = UART_FIFOSTS_ADDRDETF_Msk) + + +/** + * @brief Get RS-485 Address Byte Detection Flag + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Receiver detects a data that is not an address bit. + * @retval 1 Receiver detects a data that is an address bit. + * + * @details This macro get RS-485 address byte detection flag. + * \hideinitializer + */ +#define UART_RS485_GET_ADDR_FLAG(uart) (((uart)->FIFOSTS & UART_FIFOSTS_ADDRDETF_Msk) >> UART_FIFOSTS_ADDRDETF_Pos) + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void UART_CLEAR_RTS(UART_T* uart); +__STATIC_INLINE void UART_SET_RTS(UART_T* uart); + + +/** + * @brief Set RTS pin to low + * + * @param[in] uart The pointer of the specified UART module + * + * @return None + * + * @details This macro set RTS pin to low. + */ +__STATIC_INLINE void UART_CLEAR_RTS(UART_T* uart) +{ + uart->MODEM |= UART_MODEM_RTSACTLV_Msk; + uart->MODEM &= ~UART_MODEM_RTS_Msk; +} + + +/** + * @brief Set RTS pin to high + * + * @param[in] uart The pointer of the specified UART module + * + * @return None + * + * @details This macro set RTS pin to high. + */ +__STATIC_INLINE void UART_SET_RTS(UART_T* uart) +{ + uart->MODEM |= UART_MODEM_RTSACTLV_Msk | UART_MODEM_RTS_Msk; +} + +/** + * @brief Enable specified UART PDMA function + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u32FuncSel Combination of following functions + * - \ref UART_INTEN_TXPDMAEN_Msk + * - \ref UART_INTEN_RXPDMAEN_Msk + * + * @return None + * + * \hideinitializer + */ +#define UART_PDMA_ENABLE(uart, u32FuncSel) ((uart)->INTEN |= (u32FuncSel)) +/** + * @brief Disable specified UART PDMA function + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u32FuncSel Combination of following functions + * - \ref UART_INTEN_TXPDMAEN_Msk + * - \ref UART_INTEN_RXPDMAEN_Msk + * + * @return None + * + * \hideinitializer + */ +#define UART_PDMA_DISABLE(uart, u32FuncSel) ((uart)->INTEN &= ~(u32FuncSel)) + + +void UART_ClearIntFlag(UART_T* uart, uint32_t u32InterruptFlag); +void UART_Close(UART_T* uart); +void UART_DisableFlowCtrl(UART_T* uart); +void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag); +void UART_EnableFlowCtrl(UART_T* uart); +void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag); +void UART_Open(UART_T* uart, uint32_t u32baudrate); +uint32_t UART_Read(UART_T* uart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes); +void UART_SetLineConfig(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits); +void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC); +void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction); +void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr); +void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength); +uint32_t UART_Write(UART_T* uart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes); + + + + +/*@}*/ /* end of group UART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group UART_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /*__NU_UART_H__*/ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_usbd.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_usbd.h new file mode 100644 index 0000000000000000000000000000000000000000..cc03314b85efd26c9158f0df3f5c9bf0df5e9b33 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_usbd.h @@ -0,0 +1,693 @@ +/**************************************************************************//** + * @file nu_usbd.h + * @version V1.00 + * @brief M480 series USB driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __NU_USBD_H__ +#define __NU_USBD_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USBD_Driver USBD Driver + @{ +*/ + +/** @addtogroup USBD_EXPORTED_STRUCT USBD Exported Struct + @{ +*/ +typedef struct s_usbd_info +{ + uint8_t *gu8DevDesc; /*!< Pointer for USB Device Descriptor */ + uint8_t *gu8ConfigDesc; /*!< Pointer for USB Configuration Descriptor */ + uint8_t **gu8StringDesc; /*!< Pointer for USB String Descriptor pointers */ + uint8_t **gu8HidReportDesc; /*!< Pointer for USB HID Report Descriptor */ + uint8_t *gu8BosDesc; /*!< Pointer for USB BOS Descriptor */ + uint32_t *gu32HidReportSize; /*!< Pointer for HID Report descriptor Size */ + uint32_t *gu32ConfigHidDescIdx; /*!< Pointer for HID Descriptor start index */ + +} S_USBD_INFO_T; /*!< Device description structure */ + +extern const S_USBD_INFO_T gsInfo; + +/*@}*/ /* end of group USBD_EXPORTED_STRUCT */ + + + + +/** @addtogroup USBD_EXPORTED_CONSTANTS USBD Exported Constants + @{ +*/ +#define USBD_BUF_BASE (USBD_BASE+0x100ul) /*!< USBD buffer base address \hideinitializer */ +#define USBD_MAX_EP 12ul /*!< Total EP number \hideinitializer */ + +#define EP0 0ul /*!< Endpoint 0 \hideinitializer */ +#define EP1 1ul /*!< Endpoint 1 \hideinitializer */ +#define EP2 2ul /*!< Endpoint 2 \hideinitializer */ +#define EP3 3ul /*!< Endpoint 3 \hideinitializer */ +#define EP4 4ul /*!< Endpoint 4 \hideinitializer */ +#define EP5 5ul /*!< Endpoint 5 \hideinitializer */ +#define EP6 6ul /*!< Endpoint 6 \hideinitializer */ +#define EP7 7ul /*!< Endpoint 7 \hideinitializer */ +#define EP8 8ul /*!< Endpoint 8 \hideinitializer */ +#define EP9 9ul /*!< Endpoint 9 \hideinitializer */ +#define EP10 10ul /*!< Endpoint 10 \hideinitializer */ +#define EP11 11ul /*!< Endpoint 11 \hideinitializer */ + +/** @cond HIDDEN_SYMBOLS */ +/* USB Request Type */ +#define REQ_STANDARD 0x00ul +#define REQ_CLASS 0x20ul +#define REQ_VENDOR 0x40ul + +/* USB Standard Request */ +#define GET_STATUS 0x00ul +#define CLEAR_FEATURE 0x01ul +#define SET_FEATURE 0x03ul +#define SET_ADDRESS 0x05ul +#define GET_DESCRIPTOR 0x06ul +#define SET_DESCRIPTOR 0x07ul +#define GET_CONFIGURATION 0x08ul +#define SET_CONFIGURATION 0x09ul +#define GET_INTERFACE 0x0Aul +#define SET_INTERFACE 0x0Bul +#define SYNC_FRAME 0x0Cul + +/* USB Descriptor Type */ +#define DESC_DEVICE 0x01ul +#define DESC_CONFIG 0x02ul +#define DESC_STRING 0x03ul +#define DESC_INTERFACE 0x04ul +#define DESC_ENDPOINT 0x05ul +#define DESC_QUALIFIER 0x06ul +#define DESC_OTHERSPEED 0x07ul +#define DESC_IFPOWER 0x08ul +#define DESC_OTG 0x09ul +#define DESC_BOS 0x0Ful +#define DESC_CAPABILITY 0x10ul + +/* USB Device Capability Type */ +#define CAP_WIRELESS 0x01ul +#define CAP_USB20_EXT 0x02ul + +/* USB HID Descriptor Type */ +#define DESC_HID 0x21ul +#define DESC_HID_RPT 0x22ul + +/* USB Descriptor Length */ +#define LEN_DEVICE 18ul +#define LEN_QUALIFIER 10ul +#define LEN_CONFIG 9ul +#define LEN_INTERFACE 9ul +#define LEN_ENDPOINT 7ul +#define LEN_OTG 5ul +#define LEN_BOS 5ul +#define LEN_HID 9ul +#define LEN_CCID 0x36ul +#define LEN_BOSCAP 7ul + +/* USB Endpoint Type */ +#define EP_ISO 0x01 +#define EP_BULK 0x02 +#define EP_INT 0x03 + +#define EP_INPUT 0x80 +#define EP_OUTPUT 0x00 + +/* USB Feature Selector */ +#define FEATURE_DEVICE_REMOTE_WAKEUP 0x01ul +#define FEATURE_ENDPOINT_HALT 0x00ul +/** @endcond HIDDEN_SYMBOLS */ + +/******************************************************************************/ +/* USB Specific Macros */ +/******************************************************************************/ + +#define USBD_WAKEUP_EN USBD_INTEN_WKEN_Msk /*!< USB Wake-up Enable \hideinitializer */ +#define USBD_DRVSE0 USBD_SE0_SE0_Msk /*!< Drive SE0 \hideinitializer */ + +#define USBD_DPPU_EN USBD_ATTR_DPPUEN_Msk /*!< USB D+ Pull-up Enable \hideinitializer */ +#define USBD_PWRDN USBD_ATTR_PWRDN_Msk /*!< PHY Turn-On \hideinitializer */ +#define USBD_PHY_EN USBD_ATTR_PHYEN_Msk /*!< PHY Enable \hideinitializer */ +#define USBD_USB_EN USBD_ATTR_USBEN_Msk /*!< USB Enable \hideinitializer */ + +#define USBD_INT_BUS USBD_INTEN_BUSIEN_Msk /*!< USB Bus Event Interrupt \hideinitializer */ +#define USBD_INT_USB USBD_INTEN_USBIEN_Msk /*!< USB Event Interrupt \hideinitializer */ +#define USBD_INT_FLDET USBD_INTEN_VBDETIEN_Msk /*!< USB VBUS Detection Interrupt \hideinitializer */ +#define USBD_INT_WAKEUP (USBD_INTEN_NEVWKIEN_Msk | USBD_INTEN_WKEN_Msk) /*!< USB No-Event-Wake-Up Interrupt \hideinitializer */ + +#define USBD_INTSTS_WAKEUP USBD_INTSTS_NEVWKIF_Msk /*!< USB No-Event-Wake-Up Interrupt Status \hideinitializer */ +#define USBD_INTSTS_FLDET USBD_INTSTS_VBDETIF_Msk /*!< USB Float Detect Interrupt Status \hideinitializer */ +#define USBD_INTSTS_BUS USBD_INTSTS_BUSIF_Msk /*!< USB Bus Event Interrupt Status \hideinitializer */ +#define USBD_INTSTS_USB USBD_INTSTS_USBIF_Msk /*!< USB Event Interrupt Status \hideinitializer */ +#define USBD_INTSTS_SETUP USBD_INTSTS_SETUP_Msk /*!< USB Setup Event \hideinitializer */ +#define USBD_INTSTS_EP0 USBD_INTSTS_EPEVT0_Msk /*!< USB Endpoint 0 Event \hideinitializer */ +#define USBD_INTSTS_EP1 USBD_INTSTS_EPEVT1_Msk /*!< USB Endpoint 1 Event \hideinitializer */ +#define USBD_INTSTS_EP2 USBD_INTSTS_EPEVT2_Msk /*!< USB Endpoint 2 Event \hideinitializer */ +#define USBD_INTSTS_EP3 USBD_INTSTS_EPEVT3_Msk /*!< USB Endpoint 3 Event \hideinitializer */ +#define USBD_INTSTS_EP4 USBD_INTSTS_EPEVT4_Msk /*!< USB Endpoint 4 Event \hideinitializer */ +#define USBD_INTSTS_EP5 USBD_INTSTS_EPEVT5_Msk /*!< USB Endpoint 5 Event \hideinitializer */ +#define USBD_INTSTS_EP6 USBD_INTSTS_EPEVT6_Msk /*!< USB Endpoint 6 Event \hideinitializer */ +#define USBD_INTSTS_EP7 USBD_INTSTS_EPEVT7_Msk /*!< USB Endpoint 7 Event \hideinitializer */ +#define USBD_INTSTS_EP8 USBD_INTSTS_EPEVT8_Msk /*!< USB Endpoint 8 Event \hideinitializer */ +#define USBD_INTSTS_EP9 USBD_INTSTS_EPEVT9_Msk /*!< USB Endpoint 9 Event \hideinitializer */ +#define USBD_INTSTS_EP10 USBD_INTSTS_EPEVT10_Msk /*!< USB Endpoint 10 Event \hideinitializer */ +#define USBD_INTSTS_EP11 USBD_INTSTS_EPEVT11_Msk /*!< USB Endpoint 11 Event \hideinitializer */ + +#define USBD_STATE_USBRST USBD_ATTR_USBRST_Msk /*!< USB Bus Reset \hideinitializer */ +#define USBD_STATE_SUSPEND USBD_ATTR_SUSPEND_Msk /*!< USB Bus Suspend \hideinitializer */ +#define USBD_STATE_RESUME USBD_ATTR_RESUME_Msk /*!< USB Bus Resume \hideinitializer */ +#define USBD_STATE_TIMEOUT USBD_ATTR_TOUT_Msk /*!< USB Bus Timeout \hideinitializer */ + +#define USBD_CFGP_SSTALL USBD_CFGP_SSTALL_Msk /*!< Set Stall \hideinitializer */ +#define USBD_CFG_CSTALL USBD_CFG_CSTALL_Msk /*!< Clear Stall \hideinitializer */ + +#define USBD_CFG_EPMODE_DISABLE (0ul << USBD_CFG_STATE_Pos)/*!< Endpoint Disable \hideinitializer */ +#define USBD_CFG_EPMODE_OUT (1ul << USBD_CFG_STATE_Pos)/*!< Out Endpoint \hideinitializer */ +#define USBD_CFG_EPMODE_IN (2ul << USBD_CFG_STATE_Pos)/*!< In Endpoint \hideinitializer */ +#define USBD_CFG_TYPE_ISO (1ul << USBD_CFG_ISOCH_Pos) /*!< Isochronous \hideinitializer */ + + + +/*@}*/ /* end of group USBD_EXPORTED_CONSTANTS */ + + +/** @addtogroup USBD_EXPORTED_FUNCTIONS USBD Exported Functions + @{ +*/ +/** + * @brief Compare two input numbers and return maximum one. + * + * @param[in] a First number to be compared. + * @param[in] b Second number to be compared. + * + * @return Maximum value between a and b. + * + * @details If a > b, then return a. Otherwise, return b. + * \hideinitializer + */ +#define USBD_Maximum(a,b) ((a)>(b) ? (a) : (b)) + + +/** + * @brief Compare two input numbers and return minimum one + * + * @param[in] a First number to be compared + * @param[in] b Second number to be compared + * + * @return Minimum value between a and b + * + * @details If a < b, then return a. Otherwise, return b. + * \hideinitializer + */ +#define USBD_Minimum(a,b) ((a)<(b) ? (a) : (b)) + + +/** + * @brief Enable USB + * + * @param None + * + * @return None + * + * @details To set USB ATTR control register to enable USB and PHY. + * \hideinitializer + */ +#define USBD_ENABLE_USB() ((uint32_t)(USBD->ATTR |= 0x7D0)) + +/** + * @brief Disable USB + * + * @param None + * + * @return None + * + * @details To set USB ATTR control register to disable USB. + * \hideinitializer + */ +#define USBD_DISABLE_USB() ((uint32_t)(USBD->ATTR &= ~USBD_USB_EN)) + +/** + * @brief Enable USB PHY + * + * @param None + * + * @return None + * + * @details To set USB ATTR control register to enable USB PHY. + * \hideinitializer + */ +#define USBD_ENABLE_PHY() ((uint32_t)(USBD->ATTR |= USBD_PHY_EN)) + +/** + * @brief Disable USB PHY + * + * @param None + * + * @return None + * + * @details To set USB ATTR control register to disable USB PHY. + * \hideinitializer + */ +#define USBD_DISABLE_PHY() ((uint32_t)(USBD->ATTR &= ~USBD_PHY_EN)) + +/** + * @brief Enable SE0. Force USB PHY transceiver to drive SE0. + * + * @param None + * + * @return None + * + * @details Set DRVSE0 bit of USB_DRVSE0 register to enable software-disconnect function. Force USB PHY transceiver to drive SE0 to bus. + * \hideinitializer + */ +#define USBD_SET_SE0() ((uint32_t)(USBD->SE0 |= USBD_DRVSE0)) + +/** + * @brief Disable SE0 + * + * @param None + * + * @return None + * + * @details Clear DRVSE0 bit of USB_DRVSE0 register to disable software-disconnect function. + * \hideinitializer + */ +#define USBD_CLR_SE0() ((uint32_t)(USBD->SE0 &= ~USBD_DRVSE0)) + +/** + * @brief Set USB device address + * + * @param[in] addr The USB device address. + * + * @return None + * + * @details Write USB device address to USB_FADDR register. + * \hideinitializer + */ +#define USBD_SET_ADDR(addr) (USBD->FADDR = (addr)) + +/** + * @brief Get USB device address + * + * @param None + * + * @return USB device address + * + * @details Read USB_FADDR register to get USB device address. + * \hideinitializer + */ +#define USBD_GET_ADDR() ((uint32_t)(USBD->FADDR)) + +/** + * @brief Enable USB interrupt function + * + * @param[in] intr The combination of the specified interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. + * (USBD_INT_WAKEUP, USBD_INT_FLDET, USBD_INT_USB, USBD_INT_BUS) + * + * @return None + * + * @details Enable USB related interrupt functions specified by intr parameter. + * \hideinitializer + */ +#define USBD_ENABLE_INT(intr) (USBD->INTEN |= (intr)) + +/** + * @brief Get interrupt status + * + * @param None + * + * @return The value of USB_INTSTS register + * + * @details Return all interrupt flags of USB_INTSTS register. + * \hideinitializer + */ +#define USBD_GET_INT_FLAG() ((uint32_t)(USBD->INTSTS)) + +/** + * @brief Clear USB interrupt flag + * + * @param[in] flag The combination of the specified interrupt flags. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. + * (USBD_INTSTS_WAKEUP, USBD_INTSTS_FLDET, USBD_INTSTS_BUS, USBD_INTSTS_USB) + * + * @return None + * + * @details Clear USB related interrupt flags specified by flag parameter. + * \hideinitializer + */ +#define USBD_CLR_INT_FLAG(flag) (USBD->INTSTS = (flag)) + +/** + * @brief Get endpoint status + * + * @param None + * + * @return The value of USB_EPSTS register. + * + * @details Return all endpoint status. + * \hideinitializer + */ +#define USBD_GET_EP_FLAG() ((uint32_t)(USBD->EPSTS)) + +/** + * @brief Get USB bus state + * + * @param None + * + * @return The value of USB_ATTR[3:0]. + * Bit 0 indicates USB bus reset status. + * Bit 1 indicates USB bus suspend status. + * Bit 2 indicates USB bus resume status. + * Bit 3 indicates USB bus time-out status. + * + * @details Return USB_ATTR[3:0] for USB bus events. + * \hideinitializer + */ +#define USBD_GET_BUS_STATE() ((uint32_t)(USBD->ATTR & 0xf)) + +/** + * @brief Check cable connection state + * + * @param None + * + * @retval 0 USB cable is not attached. + * @retval 1 USB cable is attached. + * + * @details Check the connection state by FLDET bit of USB_FLDET register. + * \hideinitializer + */ +#define USBD_IS_ATTACHED() ((uint32_t)(USBD->VBUSDET & USBD_VBUSDET_VBUSDET_Msk)) + +/** + * @brief Stop USB transaction of the specified endpoint ID + * + * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Write 1 to CLRRDY bit of USB_CFGPx register to stop USB transaction of the specified endpoint ID. + * \hideinitializer + */ +#define USBD_STOP_TRANSACTION(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_CLRRDY_Msk) + +/** + * @brief Set USB DATA1 PID for the specified endpoint ID + * + * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Set DSQ_SYNC bit of USB_CFGx register to specify the DATA1 PID for the following IN token transaction. + * Base on this setting, hardware will toggle PID between DATA0 and DATA1 automatically for IN token transactions. + * \hideinitializer + */ +#define USBD_SET_DATA1(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DSQSYNC_Msk) + +/** + * @brief Set USB DATA0 PID for the specified endpoint ID + * + * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Clear DSQ_SYNC bit of USB_CFGx register to specify the DATA0 PID for the following IN token transaction. + * Base on this setting, hardware will toggle PID between DATA0 and DATA1 automatically for IN token transactions. + * \hideinitializer + */ +#define USBD_SET_DATA0(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DSQSYNC_Msk)) + +/** + * @brief Set USB payload size (IN data) + * + * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @param[in] size The transfer length. + * + * @return None + * + * @details This macro will write the transfer length to USB_MXPLDx register for IN data transaction. + * \hideinitializer + */ +#define USBD_SET_PAYLOAD_LEN(ep, size) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4))) = (size)) + +/** + * @brief Get USB payload size (OUT data) + * + * @param[in] ep The USB endpoint ID. M480 Series supports 8 endpoint ID. This parameter could be 0 ~ 11. + * + * @return The value of USB_MXPLDx register. + * + * @details Get the data length of OUT data transaction by reading USB_MXPLDx register. + * \hideinitializer + */ +#define USBD_GET_PAYLOAD_LEN(ep) ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4)))) + +/** + * @brief Configure endpoint + * + * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @param[in] config The USB configuration. + * + * @return None + * + * @details This macro will write config parameter to USB_CFGx register of specified endpoint ID. + * \hideinitializer + */ +#define USBD_CONFIG_EP(ep, config) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) = (config)) + +/** + * @brief Set USB endpoint buffer + * + * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @param[in] offset The SRAM offset. + * + * @return None + * + * @details This macro will set the SRAM offset for the specified endpoint ID. + * \hideinitializer + */ +#define USBD_SET_EP_BUF_ADDR(ep, offset) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4))) = (offset)) + +/** + * @brief Get the offset of the specified USB endpoint buffer + * + * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return The offset of the specified endpoint buffer. + * + * @details This macro will return the SRAM offset of the specified endpoint ID. + * \hideinitializer + */ +#define USBD_GET_EP_BUF_ADDR(ep) ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4)))) + +/** + * @brief Set USB endpoint stall state + * + * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Set USB endpoint stall state for the specified endpoint ID. Endpoint will respond STALL token automatically. + * \hideinitializer + */ +#define USBD_SET_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0ul].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_SSTALL_Msk) + +/** + * @brief Clear USB endpoint stall state + * + * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Clear USB endpoint stall state for the specified endpoint ID. Endpoint will respond ACK/NAK token. + * \hideinitializer + */ +#define USBD_CLR_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) &= ~USBD_CFGP_SSTALL_Msk) + +/** + * @brief Get USB endpoint stall state + * + * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @retval 0 USB endpoint is not stalled. + * @retval Others USB endpoint is stalled. + * + * @details Get USB endpoint stall state of the specified endpoint ID. + * \hideinitializer + */ +#define USBD_GET_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) & USBD_CFGP_SSTALL_Msk) + +/** + * @brief To support byte access between USB SRAM and system SRAM + * + * @param[in] dest Destination pointer. + * + * @param[in] src Source pointer. + * + * @param[in] size Byte count. + * + * @return None + * + * @details This function will copy the number of data specified by size and src parameters to the address specified by dest parameter. + * + */ +__STATIC_INLINE void USBD_MemCopy(uint8_t dest[], uint8_t src[], uint32_t size) +{ + uint32_t volatile i=0ul; + + while(size--) + { + dest[i] = src[i]; + i++; + } +} + +/** + * @brief Set USB endpoint stall state + * + * @param[in] epnum USB endpoint number + * + * @return None + * + * @details Set USB endpoint stall state. Endpoint will respond STALL token automatically. + * + */ +__STATIC_INLINE void USBD_SetStall(uint8_t epnum) +{ + uint32_t u32CfgAddr; + uint32_t u32Cfg; + uint32_t i; + + for(i = 0ul; i < USBD_MAX_EP; i++) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + if((u32Cfg & 0xful) == epnum) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + *((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg | USBD_CFGP_SSTALL); + break; + } + } +} + +/** + * @brief Clear USB endpoint stall state + * + * @param[in] epnum USB endpoint number + * + * @return None + * + * @details Clear USB endpoint stall state. Endpoint will respond ACK/NAK token. + */ +__STATIC_INLINE void USBD_ClearStall(uint8_t epnum) +{ + uint32_t u32CfgAddr; + uint32_t u32Cfg; + uint32_t i; + + for(i = 0ul; i < USBD_MAX_EP; i++) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + if((u32Cfg & 0xful) == epnum) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + *((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg & ~USBD_CFGP_SSTALL); + break; + } + } +} + +/** + * @brief Get USB endpoint stall state + * + * @param[in] epnum USB endpoint number + * + * @retval 0 USB endpoint is not stalled. + * @retval Others USB endpoint is stalled. + * + * @details Get USB endpoint stall state. + * + */ +__STATIC_INLINE uint32_t USBD_GetStall(uint8_t epnum) +{ + uint32_t u32CfgAddr; + uint32_t u32Cfg; + uint32_t i; + + for(i = 0ul; i < USBD_MAX_EP; i++) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + if((u32Cfg & 0xful) == epnum) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */ + break; + } + } + + return ((*((__IO uint32_t *)(u32CfgAddr))) & USBD_CFGP_SSTALL); +} + + +extern volatile uint8_t g_usbd_RemoteWakeupEn; + + +typedef void (*VENDOR_REQ)(void); /*!< Functional pointer type definition for Vendor class */ +typedef void (*CLASS_REQ)(void); /*!< Functional pointer type declaration for USB class request callback handler */ +typedef void (*SET_INTERFACE_REQ)(uint32_t u32AltInterface); /*!< Functional pointer type declaration for USB set interface request callback handler */ +typedef void (*SET_CONFIG_CB)(void); /*!< Functional pointer type declaration for USB set configuration request callback handler */ + + +/*--------------------------------------------------------------------*/ +void USBD_Open(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface); +void USBD_Start(void); +void USBD_GetSetupPacket(uint8_t *buf); +void USBD_ProcessSetupPacket(void); +void USBD_StandardRequest(void); +void USBD_PrepareCtrlIn(uint8_t pu8Buf[], uint32_t u32Size); +void USBD_CtrlIn(void); +void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size); +void USBD_CtrlOut(void); +void USBD_SwReset(void); +void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq); +void USBD_SetConfigCallback(SET_CONFIG_CB pfnSetConfigCallback); +void USBD_LockEpStall(uint32_t u32EpBitmap); + +/*@}*/ /* end of group USBD_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USBD_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /*__NU_USBD_H__*/ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_usci_i2c.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_usci_i2c.h new file mode 100644 index 0000000000000000000000000000000000000000..55508d5e77ecabc07246663e63cf00048eb42e93 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_usci_i2c.h @@ -0,0 +1,332 @@ +/**************************************************************************//** + * @file USCI_I2C.h + * @version V3.0 + * @brief M480 series USCI I2C(UI2C) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __NU_USCI_I2C_H__ +#define __NU_USCI_I2C_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_I2C_Driver USCI_I2C Driver + @{ +*/ + +/** @addtogroup USCI_I2C_EXPORTED_CONSTANTS USCI_I2C Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C master event definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +enum UI2C_MASTER_EVENT +{ + MASTER_SEND_ADDRESS = 10, /*!< Master send address to Slave */ + MASTER_SEND_H_WR_ADDRESS, /*!< Master send High address to Slave */ + MASTER_SEND_H_RD_ADDRESS, /*!< Master send address to Slave (Read ADDR) */ + MASTER_SEND_L_ADDRESS, /*!< Master send Low address to Slave */ + MASTER_SEND_DATA, /*!< Master Send Data to Slave */ + MASTER_SEND_REPEAT_START, /*!< Master send repeat start to Slave */ + MASTER_READ_DATA, /*!< Master Get Data from Slave */ + MASTER_STOP, /*!< Master send stop to Slave */ + MASTER_SEND_START /*!< Master send start to Slave */ +}; + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C slave event definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +enum UI2C_SLAVE_EVENT +{ + SLAVE_ADDRESS_ACK = 100, /*!< Slave send address ACK */ + SLAVE_H_WR_ADDRESS_ACK, /*!< Slave send High address ACK */ + SLAVE_L_WR_ADDRESS_ACK, /*!< Slave send Low address ACK */ + SLAVE_GET_DATA, /*!< Slave Get Data from Master (Write CMD) */ + SLAVE_SEND_DATA, /*!< Slave Send Data to Master (Read CMD) */ + SLAVE_H_RD_ADDRESS_ACK, /*!< Slave send High address ACK */ + SLAVE_L_RD_ADDRESS_ACK /*!< Slave send Low address ACK */ +}; + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_CTL constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UI2C_CTL_PTRG 0x20UL /*!< USCI_CTL setting for I2C control bits. It would set PTRG bit \hideinitializer */ +#define UI2C_CTL_STA 0x08UL /*!< USCI_CTL setting for I2C control bits. It would set STA bit \hideinitializer */ +#define UI2C_CTL_STO 0x04UL /*!< USCI_CTL setting for I2C control bits. It would set STO bit \hideinitializer */ +#define UI2C_CTL_AA 0x02UL /*!< USCI_CTL setting for I2C control bits. It would set AA bit \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C GCMode constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UI2C_GCMODE_ENABLE (1U) /*!< Enable USCI_I2C GC Mode \hideinitializer */ +#define UI2C_GCMODE_DISABLE (0U) /*!< Disable USCI_I2C GC Mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C Wakeup Mode constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UI2C_DATA_TOGGLE_WK (0x0U << UI2C_WKCTL_WKADDREN_Pos) /*!< Wakeup according data toggle \hideinitializer */ +#define UI2C_ADDR_MATCH_WK (0x1U << UI2C_WKCTL_WKADDREN_Pos) /*!< Wakeup according address match \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C interrupt mask definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UI2C_TO_INT_MASK (0x001U) /*!< Time-out interrupt mask \hideinitializer */ +#define UI2C_STAR_INT_MASK (0x002U) /*!< Start condition received interrupt mask \hideinitializer */ +#define UI2C_STOR_INT_MASK (0x004U) /*!< Stop condition received interrupt mask \hideinitializer */ +#define UI2C_NACK_INT_MASK (0x008U) /*!< Non-acknowledge interrupt mask \hideinitializer */ +#define UI2C_ARBLO_INT_MASK (0x010U) /*!< Arbitration lost interrupt mask \hideinitializer */ +#define UI2C_ERR_INT_MASK (0x020U) /*!< Error interrupt mask \hideinitializer */ +#define UI2C_ACK_INT_MASK (0x040U) /*!< Acknowledge interrupt mask \hideinitializer */ + +/*@}*/ /* end of group USCI_I2C_EXPORTED_CONSTANTS */ + + +/** @addtogroup USCI_I2C_EXPORTED_FUNCTIONS USCI_I2C Exported Functions + @{ +*/ + +/** + * @brief This macro sets the USCI_I2C protocol control register at one time + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8Ctrl Set the register value of USCI_I2C control register. + * + * @return None + * + * @details Set UI2C_PROTCTL register to control USCI_I2C bus conditions of START, STOP, SI, ACK. + * \hideinitializer + */ +#define UI2C_SET_CONTROL_REG(ui2c, u8Ctrl) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~0x2EU) | (u8Ctrl)) + +/** + * @brief This macro only set START bit to protocol control register of USCI_I2C module. + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details Set the USCI_I2C bus START condition in UI2C_PROTCTL register. + * \hideinitializer + */ +#define UI2C_START(ui2c) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~UI2C_PROTCTL_PTRG_Msk) | UI2C_PROTCTL_STA_Msk) + +/** + * @brief This macro only set STOP bit to the control register of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details Set the USCI_I2C bus STOP condition in UI2C_PROTCTL register. + * \hideinitializer + */ +#define UI2C_STOP(ui2c) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~0x2E) | (UI2C_PROTCTL_PTRG_Msk | UI2C_PROTCTL_STO_Msk)) + +/** + * @brief This macro returns the data stored in data register of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return Data + * + * @details Read a byte data value of UI2C_RXDAT register from USCI_I2C bus + * \hideinitializer + */ +#define UI2C_GET_DATA(ui2c) ((ui2c)->RXDAT) + +/** + * @brief This macro writes the data to data register of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8Data The data which will be written to data register of USCI_I2C module. + * + * @return None + * + * @details Write a byte data value of UI2C_TXDAT register, then sends address or data to USCI I2C bus + * \hideinitializer + */ +#define UI2C_SET_DATA(ui2c, u8Data) ((ui2c)->TXDAT = (u8Data)) + +/** + * @brief This macro returns time-out flag + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @retval 0 USCI_I2C bus time-out is not happened + * @retval 1 USCI_I2C bus time-out is happened + * + * @details USCI_I2C bus occurs time-out event, the time-out flag will be set. If not occurs time-out event, this bit is cleared. + * \hideinitializer + */ +#define UI2C_GET_TIMEOUT_FLAG(ui2c) (((ui2c)->PROTSTS & UI2C_PROTSTS_TOIF_Msk) == UI2C_PROTSTS_TOIF_Msk ? 1:0) + +/** + * @brief This macro returns wake-up flag + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @retval 0 Chip is not woken-up from power-down mode + * @retval 1 Chip is woken-up from power-down mode + * + * @details USCI_I2C controller wake-up flag will be set when USCI_I2C bus occurs wake-up from deep-sleep. + * \hideinitializer + */ +#define UI2C_GET_WAKEUP_FLAG(ui2c) (((ui2c)->WKSTS & UI2C_WKSTS_WKF_Msk) == UI2C_WKSTS_WKF_Msk ? 1:0) + +/** + * @brief This macro is used to clear USCI_I2C wake-up flag + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details If USCI_I2C wake-up flag is set, use this macro to clear it. + * \hideinitializer + */ +#define UI2C_CLR_WAKEUP_FLAG(ui2c) ((ui2c)->WKSTS = UI2C_WKSTS_WKF_Msk) + +/** + * @brief This macro disables the USCI_I2C 10-bit address mode + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details The UI2C_I2C is 7-bit address mode, when disable USCI_I2C 10-bit address match function. + * \hideinitializer + */ +#define UI2C_DISABLE_10BIT_ADDR_MODE(ui2c) ((ui2c)->PROTCTL &= ~(UI2C_PROTCTL_ADDR10EN_Msk)) + +/** + * @brief This macro enables the 10-bit address mode + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details To enable USCI_I2C 10-bit address match function. + * \hideinitializer + */ +#define UI2C_ENABLE_10BIT_ADDR_MODE(ui2c) ((ui2c)->PROTCTL |= UI2C_PROTCTL_ADDR10EN_Msk) + +/** + * @brief This macro gets USCI_I2C protocol interrupt flag or bus status + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return A word data of USCI_I2C_PROTSTS register + * + * @details Read a word data of USCI_I2C PROTSTS register to get USCI_I2C bus Interrupt flags or status. + * \hideinitializer + */ +#define UI2C_GET_PROT_STATUS(ui2c) ((ui2c)->PROTSTS) + +/** + * @brief This macro clears specified protocol interrupt flag + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref UI2C_PROTSTS_ACKIF_Msk + * - \ref UI2C_PROTSTS_ERRIF_Msk + * - \ref UI2C_PROTSTS_ARBLOIF_Msk + * - \ref UI2C_PROTSTS_NACKIF_Msk + * - \ref UI2C_PROTSTS_STORIF_Msk + * - \ref UI2C_PROTSTS_STARIF_Msk + * - \ref UI2C_PROTSTS_TOIF_Msk + * @return None + * + * @details To clear interrupt flag when USCI_I2C occurs interrupt and set interrupt flag. + * \hideinitializer + */ +#define UI2C_CLR_PROT_INT_FLAG(ui2c,u32IntTypeFlag) ((ui2c)->PROTSTS = (u32IntTypeFlag)) + +/** + * @brief This macro enables specified protocol interrupt + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref UI2C_PROTIEN_ACKIEN_Msk + * - \ref UI2C_PROTIEN_ERRIEN_Msk + * - \ref UI2C_PROTIEN_ARBLOIEN_Msk + * - \ref UI2C_PROTIEN_NACKIEN_Msk + * - \ref UI2C_PROTIEN_STORIEN_Msk + * - \ref UI2C_PROTIEN_STARIEN_Msk + * - \ref UI2C_PROTIEN_TOIEN_Msk + * @return None + * + * @details Set specified USCI_I2C protocol interrupt bits to enable interrupt function. + * \hideinitializer + */ +#define UI2C_ENABLE_PROT_INT(ui2c, u32IntSel) ((ui2c)->PROTIEN |= (u32IntSel)) + +/** + * @brief This macro disables specified protocol interrupt + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref UI2C_PROTIEN_ACKIEN_Msk + * - \ref UI2C_PROTIEN_ERRIEN_Msk + * - \ref UI2C_PROTIEN_ARBLOIEN_Msk + * - \ref UI2C_PROTIEN_NACKIEN_Msk + * - \ref UI2C_PROTIEN_STORIEN_Msk + * - \ref UI2C_PROTIEN_STARIEN_Msk + * - \ref UI2C_PROTIEN_TOIEN_Msk + * @return None + * + * @details Clear specified USCI_I2C protocol interrupt bits to disable interrupt function. + * \hideinitializer + */ +#define UI2C_DISABLE_PROT_INT(ui2c, u32IntSel) ((ui2c)->PROTIEN &= ~ (u32IntSel)) + + +uint32_t UI2C_Open(UI2C_T *ui2c, uint32_t u32BusClock); +void UI2C_Close(UI2C_T *ui2c); +void UI2C_ClearTimeoutFlag(UI2C_T *ui2c); +void UI2C_Trigger(UI2C_T *ui2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Ptrg, uint8_t u8Ack); +void UI2C_DisableInt(UI2C_T *ui2c, uint32_t u32Mask); +void UI2C_EnableInt(UI2C_T *ui2c, uint32_t u32Mask); +uint32_t UI2C_GetBusClockFreq(UI2C_T *ui2c); +uint32_t UI2C_SetBusClockFreq(UI2C_T *ui2c, uint32_t u32BusClock); +uint32_t UI2C_GetIntFlag(UI2C_T *ui2c, uint32_t u32Mask); +void UI2C_ClearIntFlag(UI2C_T* ui2c, uint32_t u32Mask); +uint32_t UI2C_GetData(UI2C_T *ui2c); +void UI2C_SetData(UI2C_T *ui2c, uint8_t u8Data); +void UI2C_SetSlaveAddr(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddr, uint8_t u8GCMode); +void UI2C_SetSlaveAddrMask(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddrMask); +void UI2C_EnableTimeout(UI2C_T *ui2c, uint32_t u32TimeoutCnt); +void UI2C_DisableTimeout(UI2C_T *ui2c); +void UI2C_EnableWakeup(UI2C_T *ui2c, uint8_t u8WakeupMode); +void UI2C_DisableWakeup(UI2C_T *ui2c); +uint8_t UI2C_WriteByte(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t data); +uint32_t UI2C_WriteMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t *data, uint32_t u32wLen); +uint8_t UI2C_WriteByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data); +uint32_t UI2C_WriteMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t *data, uint32_t u32wLen); +uint8_t UI2C_WriteByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data); +uint32_t UI2C_WriteMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t *data, uint32_t u32wLen); +uint8_t UI2C_ReadByte(UI2C_T *ui2c, uint8_t u8SlaveAddr); +uint32_t UI2C_ReadMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t *rdata, uint32_t u32rLen); +uint8_t UI2C_ReadByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr); +uint32_t UI2C_ReadMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t *rdata, uint32_t u32rLen); +uint8_t UI2C_ReadByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr); +uint32_t UI2C_ReadMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t *rdata, uint32_t u32rLen); + +/*@}*/ /* end of group USCI_I2C_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USCI_I2C_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_usci_spi.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_usci_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..68d4e02a897b5f66f07a0b80a1c2c42958f79a01 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_usci_spi.h @@ -0,0 +1,411 @@ +/****************************************************************************//** + * @file nu_usci_spi.h + * @version V3.00 + * @brief M480 series USCI_SPI driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __NU_USCI_SPI_H__ +#define __NU_USCI_SPI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_SPI_Driver USCI_SPI Driver + @{ +*/ + +/** @addtogroup USCI_SPI_EXPORTED_CONSTANTS USCI_SPI Exported Constants + @{ +*/ + +#define USPI_MODE_0 (0x0 << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle low; data transmit with falling edge and receive with rising edge \hideinitializer */ +#define USPI_MODE_1 (0x1 << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle low; data transmit with rising edge and receive with falling edge \hideinitializer */ +#define USPI_MODE_2 (0x2 << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle high; data transmit with rising edge and receive with falling edge \hideinitializer */ +#define USPI_MODE_3 (0x3 << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle high; data transmit with falling edge and receive with rising edge \hideinitializer */ + +#define USPI_SLAVE (USPI_PROTCTL_SLAVE_Msk) /*!< Set as slave \hideinitializer */ +#define USPI_MASTER (0x0ul) /*!< Set as master \hideinitializer */ + +#define USPI_SS (USPI_PROTCTL_SS_Msk) /*!< Set SS \hideinitializer */ +#define USPI_SS_ACTIVE_HIGH (0x0ul) /*!< SS active high \hideinitializer */ +#define USPI_SS_ACTIVE_LOW (USPI_LINECTL_CTLOINV_Msk) /*!< SS active low \hideinitializer */ + +/* USCI_SPI Interrupt Mask */ +#define USPI_SSINACT_INT_MASK (0x001ul) /*!< Slave Slave Inactive interrupt mask \hideinitializer */ +#define USPI_SSACT_INT_MASK (0x002ul) /*!< Slave Slave Active interrupt mask \hideinitializer */ +#define USPI_SLVTO_INT_MASK (0x004ul) /*!< Slave Mode Time-out interrupt mask \hideinitializer */ +#define USPI_SLVBE_INT_MASK (0x008ul) /*!< Slave Mode Bit Count Error interrupt mask \hideinitializer */ +#define USPI_TXUDR_INT_MASK (0x010ul) /*!< Slave Transmit Under Run interrupt mask \hideinitializer */ +#define USPI_RXOV_INT_MASK (0x020ul) /*!< Receive Buffer Overrun interrupt mask \hideinitializer */ +#define USPI_TXST_INT_MASK (0x040ul) /*!< Transmit Start interrupt mask \hideinitializer */ +#define USPI_TXEND_INT_MASK (0x080ul) /*!< Transmit End interrupt mask \hideinitializer */ +#define USPI_RXST_INT_MASK (0x100ul) /*!< Receive Start interrupt mask \hideinitializer */ +#define USPI_RXEND_INT_MASK (0x200ul) /*!< Receive End interrupt mask \hideinitializer */ + +/* USCI_SPI Status Mask */ +#define USPI_BUSY_MASK (0x01ul) /*!< Busy status mask \hideinitializer */ +#define USPI_RX_EMPTY_MASK (0x02ul) /*!< RX empty status mask \hideinitializer */ +#define USPI_RX_FULL_MASK (0x04ul) /*!< RX full status mask \hideinitializer */ +#define USPI_TX_EMPTY_MASK (0x08ul) /*!< TX empty status mask \hideinitializer */ +#define USPI_TX_FULL_MASK (0x10ul) /*!< TX full status mask \hideinitializer */ +#define USPI_SSLINE_STS_MASK (0x20ul) /*!< USCI_SPI_SS line status mask \hideinitializer */ + +/*@}*/ /* end of group USCI_SPI_EXPORTED_CONSTANTS */ + + +/** @addtogroup USCI_SPI_EXPORTED_FUNCTIONS USCI_SPI Exported Functions + @{ +*/ + +/** + * @brief Disable slave 3-wire mode. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_DISABLE_3WIRE_MODE(uspi) ( (uspi)->PROTCTL &= ~USPI_PROTCTL_SLV3WIRE_Msk ) + +/** + * @brief Enable slave 3-wire mode. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_ENABLE_3WIRE_MODE(uspi) ( (uspi)->PROTCTL |= USPI_PROTCTL_SLV3WIRE_Msk ) + +/** + * @brief Get the Rx buffer empty flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return Rx buffer flag + * @retval 0: Rx buffer is not empty + * @retval 1: Rx buffer is empty + * \hideinitializer + */ +#define USPI_GET_RX_EMPTY_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_RXEMPTY_Msk) == USPI_BUFSTS_RXEMPTY_Msk ? 1:0 ) + +/** + * @brief Get the Tx buffer empty flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return Tx buffer flag + * @retval 0: Tx buffer is not empty + * @retval 1: Tx buffer is empty + * \hideinitializer + */ +#define USPI_GET_TX_EMPTY_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_TXEMPTY_Msk) == USPI_BUFSTS_TXEMPTY_Msk ? 1:0 ) + +/** + * @brief Get the Tx buffer full flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return Tx buffer flag + * @retval 0: Tx buffer is not full + * @retval 1: Tx buffer is full + * \hideinitializer + */ +#define USPI_GET_TX_FULL_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_TXFULL_Msk) == USPI_BUFSTS_TXFULL_Msk ? 1:0 ) + +/** + * @brief Get the datum read from RX register. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return data in Rx register + * \hideinitializer + */ +#define USPI_READ_RX(uspi) ((uspi)->RXDAT) + +/** + * @brief Write datum to TX register. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32TxData The datum which user attempt to transfer through USCI_SPI bus. + * @return None + * \hideinitializer + */ +#define USPI_WRITE_TX(uspi, u32TxData) ( (uspi)->TXDAT = (u32TxData) ) + +/** + * @brief Set USCI_SPI_SS pin to high state. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Disable automatic slave selection function and set USCI_SPI_SS pin to high state. Only available in Master mode. + * \hideinitializer + */ +#define USPI_SET_SS_HIGH(uspi) \ + do{ \ + (uspi)->LINECTL &= ~(USPI_LINECTL_CTLOINV_Msk); \ + (uspi)->PROTCTL = ((uspi)->PROTCTL & ~(USPI_PROTCTL_AUTOSS_Msk | USPI_PROTCTL_SS_Msk)); \ + }while(0) + +/** + * @brief Set USCI_SPI_SS pin to low state. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Disable automatic slave selection function and set USCI_SPI_SS pin to low state. Only available in Master mode. + * \hideinitializer + */ +#define USPI_SET_SS_LOW(uspi) \ + do{ \ + (uspi)->LINECTL |= (USPI_LINECTL_CTLOINV_Msk); \ + (uspi)->PROTCTL = (((uspi)->PROTCTL & ~USPI_PROTCTL_AUTOSS_Msk) | USPI_PROTCTL_SS_Msk); \ + }while(0) + +/** + * @brief Set the length of suspend interval. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32SuspCycle Decide the length of suspend interval. + * @return None + * \hideinitializer + */ +#define USPI_SET_SUSPEND_CYCLE(uspi, u32SuspCycle) ( (uspi)->PROTCTL = ((uspi)->PROTCTL & ~USPI_PROTCTL_SUSPITV_Msk) | ((u32SuspCycle) << USPI_PROTCTL_SUSPITV_Pos) ) + +/** + * @brief Set the USCI_SPI transfer sequence with LSB first. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_SET_LSB_FIRST(uspi) ( (uspi)->LINECTL |= USPI_LINECTL_LSB_Msk ) + +/** + * @brief Set the USCI_SPI transfer sequence with MSB first. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_SET_MSB_FIRST(uspi) ( (uspi)->LINECTL &= ~USPI_LINECTL_LSB_Msk ) + +/** + * @brief Set the data width of a USCI_SPI transaction. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32Width The data width + * @return None + * \hideinitializer + */ +#define USPI_SET_DATA_WIDTH(uspi,u32Width) \ + do{ \ + if((u32Width) == 16ul){ \ + (uspi)->LINECTL = ((uspi)->LINECTL & ~USPI_LINECTL_DWIDTH_Msk) | (0 << USPI_LINECTL_DWIDTH_Pos); \ + }else { \ + (uspi)->LINECTL = ((uspi)->LINECTL & ~USPI_LINECTL_DWIDTH_Msk) | ((u32Width) << USPI_LINECTL_DWIDTH_Pos); \ + } \ + }while(0) + +/** + * @brief Get the USCI_SPI busy state. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return USCI_SPI busy status + * @retval 0: USCI_SPI module is not busy + * @retval 1: USCI_SPI module is busy + * \hideinitializer + */ +#define USPI_IS_BUSY(uspi) ( ((uspi)->PROTSTS & USPI_PROTSTS_BUSY_Msk) == USPI_PROTSTS_BUSY_Msk ? 1:0 ) + +/** + * @brief Get the USCI_SPI wakeup flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return Wakeup status. + * @retval 0 Flag is not set. + * @retval 1 Flag is set. + * \hideinitializer + */ +#define USPI_GET_WAKEUP_FLAG(uspi) ( ((uspi)->WKSTS & USPI_WKSTS_WKF_Msk) == USPI_WKSTS_WKF_Msk ? 1:0) + +/** + * @brief Clear the USCI_SPI wakeup flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_CLR_WAKEUP_FLAG(uspi) ( (uspi)->WKSTS |= USPI_WKSTS_WKF_Msk) + +/** + * @brief Get protocol interrupt flag/status. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return The interrupt flag/status of protocol status register. + * \hideinitializer + */ +#define USPI_GET_PROT_STATUS(uspi) ( (uspi)->PROTSTS) + +/** + * @brief Clear specified protocol interrupt flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref USPI_PROTSTS_SSACTIF_Msk + * - \ref USPI_PROTSTS_SSINAIF_Msk + * - \ref USPI_PROTSTS_SLVBEIF_Msk + * - \ref USPI_PROTSTS_SLVTOIF_Msk + * - \ref USPI_PROTSTS_RXENDIF_Msk + * - \ref USPI_PROTSTS_RXSTIF_Msk + * - \ref USPI_PROTSTS_TXENDIF_Msk + * - \ref USPI_PROTSTS_TXSTIF_Msk + * @return None + * \hideinitializer + */ +#define USPI_CLR_PROT_INT_FLAG(uspi,u32IntTypeFlag) ( (uspi)->PROTSTS = (u32IntTypeFlag)) + +/** + * @brief Get buffer interrupt flag/status. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return The interrupt flag/status of buffer status register. + * \hideinitializer + */ +#define USPI_GET_BUF_STATUS(uspi) ( (uspi)->BUFSTS) + +/** + * @brief Clear specified buffer interrupt flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref USPI_BUFSTS_TXUDRIF_Msk + * - \ref USPI_BUFSTS_RXOVIF_Msk + * @return None + * \hideinitializer + */ +#define USPI_CLR_BUF_INT_FLAG(uspi,u32IntTypeFlag) ( (uspi)->BUFSTS = (u32IntTypeFlag)) + +/** + * @brief Enable specified protocol interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_PROTIEN_SLVBEIEN_Msk + * - \ref USPI_PROTIEN_SLVTOIEN_Msk + * - \ref USPI_PROTIEN_SSACTIEN_Msk + * - \ref USPI_PROTIEN_SSINAIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_ENABLE_PROT_INT(uspi, u32IntSel) ((uspi)->PROTIEN |= (u32IntSel)) + +/** + * @brief Disable specified protocol interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_PROTIEN_SLVBEIEN_Msk + * - \ref USPI_PROTIEN_SLVTOIEN_Msk + * - \ref USPI_PROTIEN_SSACTIEN_Msk + * - \ref USPI_PROTIEN_SSINAIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_DISABLE_PROT_INT(uspi, u32IntSel) ((uspi)->PROTIEN &= ~ (u32IntSel)) + +/** + * @brief Enable specified buffer interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_BUFCTL_RXOVIEN_Msk + * - \ref USPI_BUFCTL_TXUDRIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_ENABLE_BUF_INT(uspi, u32IntSel) ((uspi)->BUFCTL |= (u32IntSel)) + +/** + * @brief Disable specified buffer interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_BUFCTL_RXOVIEN_Msk + * - \ref USPI_BUFCTL_TXUDRIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_DISABLE_BUF_INT(uspi, u32IntSel) ((uspi)->BUFCTL &= ~ (u32IntSel)) + +/** + * @brief Enable specified transfer interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_INTEN_RXENDIEN_Msk + * - \ref USPI_INTEN_RXSTIEN_Msk + * - \ref USPI_INTEN_TXENDIEN_Msk + * - \ref USPI_INTEN_TXSTIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_ENABLE_TRANS_INT(uspi, u32IntSel) ((uspi)->INTEN |= (u32IntSel)) + +/** + * @brief Disable specified transfer interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_INTEN_RXENDIEN_Msk + * - \ref USPI_INTEN_RXSTIEN_Msk + * - \ref USPI_INTEN_TXENDIEN_Msk + * - \ref USPI_INTEN_TXSTIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_DISABLE_TRANS_INT(uspi, u32IntSel) ((uspi)->INTEN &= ~ (u32IntSel)) + + +/** + * @brief Trigger RX PDMA function. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Set RXPDMAEN bit of USPI_PDMACTL register to enable RX PDMA transfer function. + * \hideinitializer + */ +#define USPI_TRIGGER_RX_PDMA(uspi) ((uspi)->PDMACTL |= USPI_PDMACTL_RXPDMAEN_Msk|USPI_PDMACTL_PDMAEN_Msk) + +/** + * @brief Trigger TX PDMA function. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Set TXPDMAEN bit of USPI_PDMACTL register to enable TX PDMA transfer function. + * \hideinitializer + */ +#define USPI_TRIGGER_TX_PDMA(uspi) ((uspi)->PDMACTL |= USPI_PDMACTL_TXPDMAEN_Msk|USPI_PDMACTL_PDMAEN_Msk) + +/** + * @brief Disable RX PDMA transfer. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Clear RXPDMAEN bit of USPI_PDMACTL register to disable RX PDMA transfer function. + * \hideinitializer + */ +#define USPI_DISABLE_RX_PDMA(uspi) ( (uspi)->PDMACTL &= ~USPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Disable TX PDMA transfer. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Clear TXPDMAEN bit of USPI_PDMACTL register to disable TX PDMA transfer function. + * \hideinitializer + */ +#define USPI_DISABLE_TX_PDMA(uspi) ( (uspi)->PDMACTL &= ~USPI_PDMACTL_TXPDMAEN_Msk ) + +uint32_t USPI_Open(USPI_T *uspi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock); +void USPI_Close(USPI_T *uspi); +void USPI_ClearRxBuf(USPI_T *uspi); +void USPI_ClearTxBuf(USPI_T *uspi); +void USPI_DisableAutoSS(USPI_T *uspi); +void USPI_EnableAutoSS(USPI_T *uspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel); +uint32_t USPI_SetBusClock(USPI_T *uspi, uint32_t u32BusClock); +uint32_t USPI_GetBusClock(USPI_T *uspi); +void USPI_EnableInt(USPI_T *uspi, uint32_t u32Mask); +void USPI_DisableInt(USPI_T *uspi, uint32_t u32Mask); +uint32_t USPI_GetIntFlag(USPI_T *uspi, uint32_t u32Mask); +void USPI_ClearIntFlag(USPI_T *uspi, uint32_t u32Mask); +uint32_t USPI_GetStatus(USPI_T *uspi, uint32_t u32Mask); +void USPI_EnableWakeup(USPI_T *uspi); +void USPI_DisableWakeup(USPI_T *uspi); + + +/*@}*/ /* end of group USCI_SPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USCI_SPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_USCI_SPI_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_usci_uart.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_usci_uart.h new file mode 100644 index 0000000000000000000000000000000000000000..e1402a19115b60bb0166144292609946751a173d --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_usci_uart.h @@ -0,0 +1,520 @@ +/**************************************************************************//** + * @file nu_usci_uart.h + * @version V3.00 + * @brief M480 series USCI UART (UUART) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __NU_USCI_UART_H__ +#define __NU_USCI_UART_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_UART_Driver USCI_UART Driver + @{ +*/ + +/** @addtogroup USCI_UART_EXPORTED_CONSTANTS USCI_UART Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* UUART_LINECTL constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UUART_WORD_LEN_6 (6ul << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 6 bits \hideinitializer */ +#define UUART_WORD_LEN_7 (7ul << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 7 bits \hideinitializer */ +#define UUART_WORD_LEN_8 (8ul << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 8 bits \hideinitializer */ +#define UUART_WORD_LEN_9 (9ul << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 9 bits \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* UUART_PROTCTL constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UUART_PARITY_NONE (0x0ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as no parity \hideinitializer */ +#define UUART_PARITY_ODD (0x1ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as odd parity \hideinitializer */ +#define UUART_PARITY_EVEN (0x3ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as even parity \hideinitializer */ + +#define UUART_STOP_BIT_1 (0x0ul) /*!< UUART_PROTCTL setting for one stop bit \hideinitializer */ +#define UUART_STOP_BIT_2 (0x1ul) /*!< UUART_PROTCTL setting for two stop bit \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI UART interrupt mask definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UUART_ABR_INT_MASK (0x002ul) /*!< Auto-baud rate interrupt mask \hideinitializer */ +#define UUART_RLS_INT_MASK (0x004ul) /*!< Receive line status interrupt mask \hideinitializer */ +#define UUART_BUF_RXOV_INT_MASK (0x008ul) /*!< Buffer RX overrun interrupt mask \hideinitializer */ +#define UUART_TXST_INT_MASK (0x010ul) /*!< TX start interrupt mask \hideinitializer */ +#define UUART_TXEND_INT_MASK (0x020ul) /*!< Tx end interrupt mask \hideinitializer */ +#define UUART_RXST_INT_MASK (0x040ul) /*!< RX start interrupt mask \hideinitializer */ +#define UUART_RXEND_INT_MASK (0x080ul) /*!< RX end interrupt mask \hideinitializer */ + + +/*@}*/ /* end of group USCI_UART_EXPORTED_CONSTANTS */ + + +/** @addtogroup USCI_UART_EXPORTED_FUNCTIONS USCI_UART Exported Functions + @{ +*/ + + +/** + * @brief Write USCI_UART data + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u8Data Data byte to transmit. + * + * @return None + * + * @details This macro write Data to Tx data register. + * \hideinitializer + */ +#define UUART_WRITE(uuart, u8Data) ((uuart)->TXDAT = (u8Data)) + + +/** + * @brief Read USCI_UART data + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @return The oldest data byte in RX buffer. + * + * @details This macro read Rx data register. + * \hideinitializer + */ +#define UUART_READ(uuart) ((uuart)->RXDAT) + + +/** + * @brief Get Tx empty + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Tx buffer is not empty + * @retval >=1 Tx buffer is empty + * + * @details This macro get Transmitter buffer empty register value. + * \hideinitializer + */ +#define UUART_GET_TX_EMPTY(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk) + + +/** + * @brief Get Rx empty + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Rx buffer is not empty + * @retval >=1 Rx buffer is empty + * + * @details This macro get Receiver buffer empty register value. + * \hideinitializer + */ +#define UUART_GET_RX_EMPTY(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk) + + +/** + * @brief Check specified usci_uart port transmission is over. + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Tx transmission is not over + * @retval 1 Tx transmission is over + * + * @details This macro return Transmitter Empty Flag register bit value. \n + * It indicates if specified usci_uart port transmission is over nor not. + * \hideinitializer + */ +#define UUART_IS_TX_EMPTY(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk) >> UUART_BUFSTS_TXEMPTY_Pos) + + +/** + * @brief Check specified usci_uart port receiver is empty. + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Rx receiver is not empty + * @retval 1 Rx receiver is empty + * + * @details This macro return Receive Empty Flag register bit value. \n + * It indicates if specified usci_uart port receiver is empty nor not. + * \hideinitializer + */ +#define UUART_IS_RX_EMPTY(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk) >> UUART_BUFSTS_RXEMPTY_Pos) + + +/** + * @brief Wait specified usci_uart port transmission is over + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @return None + * + * @details This macro wait specified usci_uart port transmission is over. + * \hideinitializer + */ +#define UUART_WAIT_TX_EMPTY(uuart) while(!((((uuart)->BUFSTS) & UUART_BUFSTS_TXEMPTY_Msk) >> UUART_BUFSTS_TXEMPTY_Pos)) + + +/** + * @brief Check TX buffer is full or not + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 1 TX buffer is full + * @retval 0 TX buffer is not full + * + * @details This macro check TX buffer is full or not. + * \hideinitializer + */ +#define UUART_IS_TX_FULL(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_TXFULL_Msk)>>UUART_BUFSTS_TXFULL_Pos) + + +/** + * @brief Check RX buffer is full or not + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 1 RX buffer is full + * @retval 0 RX buffer is not full + * + * @details This macro check RX buffer is full or not. + * \hideinitializer + */ +#define UUART_IS_RX_FULL(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_RXFULL_Msk)>>UUART_BUFSTS_RXFULL_Pos) + + +/** + * @brief Get Tx full register value + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Tx buffer is not full. + * @retval >=1 Tx buffer is full. + * + * @details This macro get Tx full register value. + * \hideinitializer + */ +#define UUART_GET_TX_FULL(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_TXFULL_Msk) + + +/** + * @brief Get Rx full register value + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Rx buffer is not full. + * @retval >=1 Rx buffer is full. + * + * @details This macro get Rx full register value. + * \hideinitializer + */ +#define UUART_GET_RX_FULL(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_RXFULL_Msk) + + +/** + * @brief Enable specified USCI_UART protocol interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_PROTIEN_RLSIEN_Msk : Rx Line status interrupt + * - \ref UUART_PROTIEN_ABRIEN_Msk : Auto-baud rate interrupt + * + * @return None + * + * @details This macro enable specified USCI_UART protocol interrupt. + * \hideinitializer + */ +#define UUART_ENABLE_PROT_INT(uuart, u32IntSel) ((uuart)->PROTIEN |= (u32IntSel)) + + +/** + * @brief Disable specified USCI_UART protocol interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_PROTIEN_RLSIEN_Msk : Rx Line status interrupt + * - \ref UUART_PROTIEN_ABRIEN_Msk : Auto-baud rate interrupt + * + * @return None + * + * @details This macro disable specified USCI_UART protocol interrupt. + * \hideinitializer + */ +#define UUART_DISABLE_PROT_INT(uuart, u32IntSel) ((uuart)->PROTIEN &= ~(u32IntSel)) + + +/** + * @brief Enable specified USCI_UART buffer interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_BUFCTL_RXOVIEN_Msk : Receive buffer overrun error interrupt + * + * @return None + * + * @details This macro enable specified USCI_UART buffer interrupt. + * \hideinitializer + */ +#define UUART_ENABLE_BUF_INT(uuart, u32IntSel) ((uuart)->BUFCTL |= (u32IntSel)) + + +/** + * @brief Disable specified USCI_UART buffer interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_BUFCTL_RXOVIEN_Msk : Receive buffer overrun error interrupt + * + * @return None + * + * @details This macro disable specified USCI_UART buffer interrupt. + * \hideinitializer + */ +#define UUART_DISABLE_BUF_INT(uuart, u32IntSel) ((uuart)->BUFCTL &= ~ (u32IntSel)) + + +/** + * @brief Enable specified USCI_UART transfer interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_INTEN_RXENDIEN_Msk : Receive end interrupt + * - \ref UUART_INTEN_RXSTIEN_Msk : Receive start interrupt + * - \ref UUART_INTEN_TXENDIEN_Msk : Transmit end interrupt + * - \ref UUART_INTEN_TXSTIEN_Msk : Transmit start interrupt + * + * @return None + * + * @details This macro enable specified USCI_UART transfer interrupt. + * \hideinitializer + */ +#define UUART_ENABLE_TRANS_INT(uuart, u32IntSel) ((uuart)->INTEN |= (u32IntSel)) + + +/** + * @brief Disable specified USCI_UART transfer interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_INTEN_RXENDIEN_Msk : Receive end interrupt + * - \ref UUART_INTEN_RXSTIEN_Msk : Receive start interrupt + * - \ref UUART_INTEN_TXENDIEN_Msk : Transmit end interrupt + * - \ref UUART_INTEN_TXSTIEN_Msk : Transmit start interrupt + * + * @return None + * + * @details This macro disable specified USCI_UART transfer interrupt. + * \hideinitializer + */ +#define UUART_DISABLE_TRANS_INT(uuart, u32IntSel) ((uuart)->INTEN &= ~(u32IntSel)) + + +/** + * @brief Get protocol interrupt flag/status + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @return The interrupt flag/status of protocol status register. + * + * @details This macro get protocol status register value. + * \hideinitializer + */ +#define UUART_GET_PROT_STATUS(uuart) ((uuart)->PROTSTS) + + +/** + * @brief Clear specified protocol interrupt flag + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref UUART_PROTSTS_ABERRSTS_Msk : Auto-baud Rate Error Interrupt Indicator + * - \ref UUART_PROTSTS_ABRDETIF_Msk : Auto-baud Rate Detected Interrupt Flag + * - \ref UUART_PROTSTS_BREAK_Msk : Break Flag + * - \ref UUART_PROTSTS_FRMERR_Msk : Framing Error Flag + * - \ref UUART_PROTSTS_PARITYERR_Msk : Parity Error Flag + * - \ref UUART_PROTSTS_RXENDIF_Msk : Receive End Interrupt Flag + * - \ref UUART_PROTSTS_RXSTIF_Msk : Receive Start Interrupt Flag + * - \ref UUART_PROTSTS_TXENDIF_Msk : Transmit End Interrupt Flag + * - \ref UUART_PROTSTS_TXSTIF_Msk : Transmit Start Interrupt Flag + * + * @return None + * + * @details This macro clear specified protocol interrupt flag. + * \hideinitializer + */ +#define UUART_CLR_PROT_INT_FLAG(uuart,u32IntTypeFlag) ((uuart)->PROTSTS = (u32IntTypeFlag)) + + +/** + * @brief Get transmit/receive buffer interrupt flag/status + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @return The interrupt flag/status of buffer status register. + * + * @details This macro get buffer status register value. + * \hideinitializer + */ +#define UUART_GET_BUF_STATUS(uuart) ((uuart)->BUFSTS) + + +/** + * @brief Clear specified buffer interrupt flag + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref UUART_BUFSTS_RXOVIF_Msk : Receive Buffer Over-run Error Interrupt Indicator + * + * @return None + * + * @details This macro clear specified buffer interrupt flag. + * \hideinitializer + */ +#define UUART_CLR_BUF_INT_FLAG(uuart,u32IntTypeFlag) ((uuart)->BUFSTS = (u32IntTypeFlag)) + + +/** + * @brief Get wakeup flag + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Chip did not wake up from power-down mode. + * @retval 1 Chip waked up from power-down mode. + * + * @details This macro get wakeup flag. + * \hideinitializer + */ +#define UUART_GET_WAKEUP_FLAG(uuart) ((uuart)->WKSTS & UUART_WKSTS_WKF_Msk ? 1: 0 ) + + +/** + * @brief Clear wakeup flag + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @return None + * + * @details This macro clear wakeup flag. + * \hideinitializer + */ +#define UUART_CLR_WAKEUP_FLAG(uuart) ((uuart)->WKSTS = UUART_WKSTS_WKF_Msk) + +/** + * @brief Trigger RX PDMA function. + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * + * @return None. + * + * @details Set RXPDMAEN bit of UUART_PDMACTL register to enable RX PDMA transfer function. + * \hideinitializer + */ +#define UUART_TRIGGER_RX_PDMA(uuart) ((uuart)->PDMACTL |= UUART_PDMACTL_RXPDMAEN_Msk|UUART_PDMACTL_PDMAEN_Msk) + +/** + * @brief Trigger TX PDMA function. + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * + * @return None. + * + * @details Set TXPDMAEN bit of UUART_PDMACTL register to enable TX PDMA transfer function. + * \hideinitializer + */ +#define UUART_TRIGGER_TX_PDMA(uuart) ((uuart)->PDMACTL |= UUART_PDMACTL_TXPDMAEN_Msk|UUART_PDMACTL_PDMAEN_Msk) + +/** + * @brief Disable RX PDMA transfer. + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * + * @return None. + * + * @details Clear RXPDMAEN bit of UUART_PDMACTL register to disable RX PDMA transfer function. + * \hideinitializer + */ +#define UUART_DISABLE_RX_PDMA(uuart) ( (uuart)->PDMACTL &= ~UUART_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Disable TX PDMA transfer. + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * + * @return None. + * + * @details Clear TXPDMAEN bit of UUART_PDMACTL register to disable TX PDMA transfer function. + * \hideinitializer + */ +#define UUART_DISABLE_TX_PDMA(uuart) ( (uuart)->PDMACTL &= ~UUART_PDMACTL_TXPDMAEN_Msk ) + + +/** + * @brief Enable specified USCI_UART PDMA function + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32FuncSel Combination of following functions + * - \ref UUART_PDMACTL_TXPDMAEN_Msk + * - \ref UUART_PDMACTL_RXPDMAEN_Msk + * - \ref UUART_PDMACTL_PDMAEN_Msk + * + * @return None + * + * \hideinitializer + */ +#define UUART_PDMA_ENABLE(uuart, u32FuncSel) ((uuart)->PDMACTL |= (u32FuncSel)) + +/** + * @brief Disable specified USCI_UART PDMA function + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32FuncSel Combination of following functions + * - \ref UUART_PDMACTL_TXPDMAEN_Msk + * - \ref UUART_PDMACTL_RXPDMAEN_Msk + * - \ref UUART_PDMACTL_PDMAEN_Msk + * + * @return None + * + * \hideinitializer + */ +#define UUART_PDMA_DISABLE(uuart, u32FuncSel) ((uuart)->PDMACTL &= ~(u32FuncSel)) + + + + +void UUART_ClearIntFlag(UUART_T* uuart, uint32_t u32Mask); +uint32_t UUART_GetIntFlag(UUART_T* uuart, uint32_t u32Mask); +void UUART_Close(UUART_T* uuart); +void UUART_DisableInt(UUART_T* uuart, uint32_t u32Mask); +void UUART_EnableInt(UUART_T* uuart, uint32_t u32Mask); +uint32_t UUART_Open(UUART_T* uuart, uint32_t u32baudrate); +uint32_t UUART_Read(UUART_T* uuart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes); +uint32_t UUART_SetLine_Config(UUART_T* uuart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits); +uint32_t UUART_Write(UUART_T* uuart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes); +void UUART_EnableWakeup(UUART_T* uuart, uint32_t u32WakeupMode); +void UUART_DisableWakeup(UUART_T* uuart); +void UUART_EnableFlowCtrl(UUART_T* uuart); +void UUART_DisableFlowCtrl(UUART_T* uuart); + + +/*@}*/ /* end of group USCI_UART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USCI_UART_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_USCI_UART_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_wdt.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_wdt.h new file mode 100644 index 0000000000000000000000000000000000000000..634d73f80288c30332eabacbc7f4521fcc9e9a36 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_wdt.h @@ -0,0 +1,216 @@ +/**************************************************************************//** + * @file nu_wdt.h + * @version V3.00 + * @brief M480 series WDT driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_WDT_H__ +#define __NU_WDT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WDT_Driver WDT Driver + @{ +*/ + +/** @addtogroup WDT_EXPORTED_CONSTANTS WDT Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* WDT Time-out Interval Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WDT_TIMEOUT_2POW4 (0UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^4 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW6 (1UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^6 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW8 (2UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^8 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW10 (3UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^10 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW12 (4UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^12 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW14 (5UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^14 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW16 (6UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^16 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW18 (7UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^18 * WDT clocks \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* WDT Reset Delay Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WDT_RESET_DELAY_1026CLK (0UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 1026 * WDT clocks \hideinitializer */ +#define WDT_RESET_DELAY_130CLK (1UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 130 * WDT clocks \hideinitializer */ +#define WDT_RESET_DELAY_18CLK (2UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 18 * WDT clocks \hideinitializer */ +#define WDT_RESET_DELAY_3CLK (3UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 3 * WDT clocks \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* WDT Free Reset Counter Keyword Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WDT_RESET_COUNTER_KEYWORD (0x00005AA5UL) /*!< Fill this value to WDT_RSTCNT register to free reset WDT counter \hideinitializer */ + +/*@}*/ /* end of group WDT_EXPORTED_CONSTANTS */ + + +/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions + @{ +*/ + +/** + * @brief Clear WDT Reset System Flag + * + * @param None + * + * @return None + * + * @details This macro clears WDT time-out reset system flag. + * \hideinitializer + */ +#define WDT_CLEAR_RESET_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_RSTF_Msk) + +/** + * @brief Clear WDT Time-out Interrupt Flag + * + * @param None + * + * @return None + * + * @details This macro clears WDT time-out interrupt flag. + * \hideinitializer + */ +#define WDT_CLEAR_TIMEOUT_INT_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_IF_Msk) + +/** + * @brief Clear WDT Wake-up Flag + * + * @param None + * + * @return None + * + * @details This macro clears WDT time-out wake-up system flag. + * \hideinitializer + */ +#define WDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk)) | WDT_CTL_WKF_Msk) + +/** + * @brief Get WDT Time-out Reset Flag + * + * @param None + * + * @retval 0 WDT time-out reset system did not occur + * @retval 1 WDT time-out reset system occurred + * + * @details This macro indicates system has been reset by WDT time-out reset or not. + * \hideinitializer + */ +#define WDT_GET_RESET_FLAG() ((WDT->CTL & WDT_CTL_RSTF_Msk)? 1UL : 0UL) + +/** + * @brief Get WDT Time-out Interrupt Flag + * + * @param None + * + * @retval 0 WDT time-out interrupt did not occur + * @retval 1 WDT time-out interrupt occurred + * + * @details This macro indicates WDT time-out interrupt occurred or not. + * \hideinitializer + */ +#define WDT_GET_TIMEOUT_INT_FLAG() ((WDT->CTL & WDT_CTL_IF_Msk)? 1UL : 0UL) + +/** + * @brief Get WDT Time-out Wake-up Flag + * + * @param None + * + * @retval 0 WDT time-out interrupt does not cause CPU wake-up + * @retval 1 WDT time-out interrupt event cause CPU wake-up + * + * @details This macro indicates WDT time-out interrupt event has waked up system or not. + * \hideinitializer + */ +#define WDT_GET_TIMEOUT_WAKEUP_FLAG() ((WDT->CTL & WDT_CTL_WKF_Msk)? 1UL : 0UL) + +/** + * @brief Reset WDT Counter + * + * @param None + * + * @return None + * + * @details This macro is used to reset the internal 18-bit WDT up counter value. + * @note If WDT is activated and time-out reset system function is enabled also, user should \n + * reset the 18-bit WDT up counter value to avoid generate WDT time-out reset signal to \n + * reset system before the WDT time-out reset delay period expires. + * \hideinitializer + */ +#define WDT_RESET_COUNTER() (WDT->RSTCNT = WDT_RESET_COUNTER_KEYWORD) + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void WDT_Close(void); +__STATIC_INLINE void WDT_EnableInt(void); +__STATIC_INLINE void WDT_DisableInt(void); + +/** + * @brief Stop WDT Counting + * + * @param None + * + * @return None + * + * @details This function will stop WDT counting and disable WDT module. + */ +__STATIC_INLINE void WDT_Close(void) +{ + WDT->CTL = 0UL; + return; +} + +/** + * @brief Enable WDT Time-out Interrupt + * + * @param None + * + * @return None + * + * @details This function will enable the WDT time-out interrupt function. + */ +__STATIC_INLINE void WDT_EnableInt(void) +{ + WDT->CTL |= WDT_CTL_INTEN_Msk; + return; +} + +/** + * @brief Disable WDT Time-out Interrupt + * + * @param None + * + * @return None + * + * @details This function will disable the WDT time-out interrupt function. + */ +__STATIC_INLINE void WDT_DisableInt(void) +{ + /* Do not touch another write 1 clear bits */ + WDT->CTL &= ~(WDT_CTL_INTEN_Msk | WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk); + return; +} + +void WDT_Open(uint32_t u32TimeoutInterval, uint32_t u32ResetDelay, uint32_t u32EnableReset, uint32_t u32EnableWakeup); + +/*@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group WDT_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_WDT_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_wwdt.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_wwdt.h new file mode 100644 index 0000000000000000000000000000000000000000..a15ae1446b2786f09b792caa54b508bfaafbc1c7 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_wwdt.h @@ -0,0 +1,152 @@ +/**************************************************************************//** + * @file nu_wwdt.h + * @version V3.00 + * @brief M480 series WWDT driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_WWDT_H__ +#define __NU_WWDT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WWDT_Driver WWDT Driver + @{ +*/ + +/** @addtogroup WWDT_EXPORTED_CONSTANTS WWDT Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* WWDT Prescale Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WWDT_PRESCALER_1 (0 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_2 (1 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_4 (2 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 4 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_8 (3 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 8 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_16 (4 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 16 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_32 (5 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 32 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_64 (6 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 64 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_128 (7 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 128 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_192 (8 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 192 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_256 (9 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 256 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_384 (10 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 384 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_512 (11 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 512 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_768 (12 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 768 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_1024 (13 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1024 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_1536 (14 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1536 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_2048 (15 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2048 * (64*WWDT_CLK) \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* WWDT Reload Counter Keyword Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WWDT_RELOAD_WORD (0x00005AA5) /*!< Fill this value to WWDT_RLDCNT register to reload WWDT counter \hideinitializer */ + +/*@}*/ /* end of group WWDT_EXPORTED_CONSTANTS */ + + +/** @addtogroup WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions + @{ +*/ + +/** + * @brief Clear WWDT Reset System Flag + * + * @param None + * + * @return None + * + * @details This macro is used to clear WWDT time-out reset system flag. + * \hideinitializer + */ +#define WWDT_CLEAR_RESET_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTRF_Msk) + +/** + * @brief Clear WWDT Compared Match Interrupt Flag + * + * @param None + * + * @return None + * + * @details This macro is used to clear WWDT compared match interrupt flag. + * \hideinitializer + */ +#define WWDT_CLEAR_INT_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTIF_Msk) + +/** + * @brief Get WWDT Reset System Flag + * + * @param None + * + * @retval 0 WWDT time-out reset system did not occur + * @retval 1 WWDT time-out reset system occurred + * + * @details This macro is used to indicate system has been reset by WWDT time-out reset or not. + * \hideinitializer + */ +#define WWDT_GET_RESET_FLAG() ((WWDT->STATUS & WWDT_STATUS_WWDTRF_Msk)? 1 : 0) + +/** + * @brief Get WWDT Compared Match Interrupt Flag + * + * @param None + * + * @retval 0 WWDT compare match interrupt did not occur + * @retval 1 WWDT compare match interrupt occurred + * + * @details This macro is used to indicate WWDT counter value matches CMPDAT value or not. + * \hideinitializer + */ +#define WWDT_GET_INT_FLAG() ((WWDT->STATUS & WWDT_STATUS_WWDTIF_Msk)? 1 : 0) + +/** + * @brief Get WWDT Counter + * + * @param None + * + * @return WWDT Counter Value + * + * @details This macro reflects the current WWDT counter value. + * \hideinitializer + */ +#define WWDT_GET_COUNTER() (WWDT->CNT) + +/** + * @brief Reload WWDT Counter + * + * @param None + * + * @return None + * + * @details This macro is used to reload the WWDT counter value to 0x3F. + * @note User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value \n + * between 0 and CMPDAT value. If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, \n + * WWDT reset signal will generate immediately to reset system. + * \hideinitializer + */ +#define WWDT_RELOAD_COUNTER() (WWDT->RLDCNT = WWDT_RELOAD_WORD) + +void WWDT_Open(uint32_t u32PreScale, uint32_t u32CmpValue, uint32_t u32EnableInt); + +/*@}*/ /* end of group WWDT_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group WWDT_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_WWDT_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/lib/libStdDriver.ewd b/bsp/nuvoton/libraries/m480/StdDriver/lib/libStdDriver.ewd new file mode 100644 index 0000000000000000000000000000000000000000..4990af44b47b5e84eaf3b402cdc9e65011c1444c --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/lib/libStdDriver.ewd @@ -0,0 +1,3285 @@ + + + + 2 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 28 + 1 + 1 + + + + + + + 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$PROJ_DIR$\..\src\nu_spi.c + + + $PROJ_DIR$\..\src\nu_spim.c + + + $PROJ_DIR$\..\src\nu_sys.c + + + $PROJ_DIR$\..\src\nu_timer.c + + + $PROJ_DIR$\..\src\nu_timer_pwm.c + + + $PROJ_DIR$\..\src\nu_trng.c + + + $PROJ_DIR$\..\src\nu_uart.c + + + $PROJ_DIR$\..\src\nu_usbd.c + + + $PROJ_DIR$\..\src\nu_usci_i2c.c + + + $PROJ_DIR$\..\src\nu_usci_spi.c + + + $PROJ_DIR$\..\src\nu_usci_uart.c + + + $PROJ_DIR$\..\src\nu_wdt.c + + + $PROJ_DIR$\..\src\nu_wwdt.c + + + diff --git a/bsp/nuvoton/libraries/m480/StdDriver/lib/libStdDriver.eww b/bsp/nuvoton/libraries/m480/StdDriver/lib/libStdDriver.eww new file mode 100644 index 0000000000000000000000000000000000000000..fcdfcdfe3088731ee61398fc8edc0db6768511b3 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/lib/libStdDriver.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\libStdDriver.ewp + + + + + diff --git a/bsp/nuvoton/libraries/m480/StdDriver/lib/libStdDriver.uvprojx b/bsp/nuvoton/libraries/m480/StdDriver/lib/libStdDriver.uvprojx new file mode 100644 index 0000000000000000000000000000000000000000..c447d034e0a32817e7051b6421ddeb149d4682db --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/lib/libStdDriver.uvprojx @@ -0,0 +1,587 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + libstddriver-m480 + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + M487JIDAE + Nuvoton + Nuvoton.NuMicro_DFP.1.3.9 + http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack + IRAM(0x20000000,0x28000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0M481_AP_512 -FS00 -FL080000 -FP0($$Device:M487JIDAE$Flash\M481_AP_512.FLM)) + 0 + $$Device:M487JIDAE$Device\M480\Include\M480.h + + + + + + + + + + $$Device:M487JIDAE$SVD\Nuvoton\M481_v1.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil5\ + libstddriver_keil + 0 + 1 + 1 + 1 + 1 + .\build\keil5\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + xcopy /y ".\build\keil5\@L.lib" "." + + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x28000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x28000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 5 + 3 + 0 + 0 + 0 + 1 + 0 + + + + + ..\inc;..\lib;..\..\CMSIS\Include;..\..\Device\Nuvoton\M480\Include + + + + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + src + + + nu_acmp.c + 1 + ..\src\nu_acmp.c + + + nu_bpwm.c + 1 + ..\src\nu_bpwm.c + + + nu_can.c + 1 + ..\src\nu_can.c + + + nu_ccap.c + 1 + ..\src\nu_ccap.c + + + nu_clk.c + 1 + ..\src\nu_clk.c + + + nu_crc.c + 1 + ..\src\nu_crc.c + + + nu_crypto.c + 1 + ..\src\nu_crypto.c + + + nu_dac.c + 1 + ..\src\nu_dac.c + + + nu_eadc.c + 1 + ..\src\nu_eadc.c + + + nu_ebi.c + 1 + ..\src\nu_ebi.c + + + nu_ecap.c + 1 + ..\src\nu_ecap.c + + + nu_emac.c + 1 + ..\src\nu_emac.c + + + nu_epwm.c + 1 + ..\src\nu_epwm.c + + + nu_fmc.c + 1 + ..\src\nu_fmc.c + + + nu_gpio.c + 1 + ..\src\nu_gpio.c + + + nu_hsusbd.c + 1 + ..\src\nu_hsusbd.c + + + nu_i2c.c + 1 + ..\src\nu_i2c.c + + + nu_i2s.c + 1 + ..\src\nu_i2s.c + + + nu_pdma.c + 1 + ..\src\nu_pdma.c + + + nu_qei.c + 1 + ..\src\nu_qei.c + + + nu_qspi.c + 1 + ..\src\nu_qspi.c + + + nu_rtc.c + 1 + ..\src\nu_rtc.c + + + nu_sc.c + 1 + ..\src\nu_sc.c + + + nu_scuart.c + 1 + ..\src\nu_scuart.c + + + nu_sdh.c + 1 + ..\src\nu_sdh.c + + + nu_spi.c + 1 + ..\src\nu_spi.c + + + nu_spim.c + 1 + ..\src\nu_spim.c + + + nu_sys.c + 1 + ..\src\nu_sys.c + + + nu_timer.c + 1 + ..\src\nu_timer.c + + + nu_timer_pwm.c + 1 + ..\src\nu_timer_pwm.c + + + nu_trng.c + 1 + ..\src\nu_trng.c + + + nu_uart.c + 1 + ..\src\nu_uart.c + + + nu_usbd.c + 1 + ..\src\nu_usbd.c + + + nu_usci_i2c.c + 1 + ..\src\nu_usci_i2c.c + + + nu_usci_spi.c + 1 + ..\src\nu_usci_spi.c + + + nu_usci_uart.c + 1 + ..\src\nu_usci_uart.c + + + nu_wdt.c + 1 + ..\src\nu_wdt.c + + + nu_wwdt.c + 1 + ..\src\nu_wwdt.c + + + + + + + + + + + + + + diff --git a/bsp/nuvoton/libraries/m480/StdDriver/lib/libStdDriver_4.uvproj b/bsp/nuvoton/libraries/m480/StdDriver/lib/libStdDriver_4.uvproj new file mode 100644 index 0000000000000000000000000000000000000000..3f834f0d1b674720a17ba16beb9523a2227860a2 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/lib/libStdDriver_4.uvproj @@ -0,0 +1,591 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + libStdDriver_4 + 0x4 + ARM-ADS + + + M487JIDAE + Nuvoton + IRAM(0x20000000-0x20027FFF) IROM(0-0x7FFFF) CLOCK(192000000) CPUTYPE("Cortex-M4") FPU2 + + undefined + + 0 + + + + + + + + + + + SFD\Nuvoton\M481_v1.SFR + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil4\ + libstddriver_keil4 + 0 + 1 + 1 + 1 + 1 + .\build\keil4\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + xcopy /y ".\build\keil4\@L.lib" "." + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMCM1.DLL + + SARMCM3.DLL + + TARMCM1.DLL + + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + + 0 + 11 + + + + + + + + + + + + + + NULink\Nu_Link.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4101 + + 0 + NULink\Nu_Link.dll + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x28000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x28000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + --c99 + + + ..\lib;..\inc;..\..\CMSIS\Include;..\..\Device\Nuvoton\M480\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + .\linking_scripts\m480_flash.sct + + + + + + + + + + + src + + + nu_acmp.c + 1 + ..\src\nu_acmp.c + + + nu_bpwm.c + 1 + ..\src\nu_bpwm.c + + + nu_can.c + 1 + ..\src\nu_can.c + + + nu_ccap.c + 1 + ..\src\nu_ccap.c + + + nu_clk.c + 1 + ..\src\nu_clk.c + + + nu_crc.c + 1 + ..\src\nu_crc.c + + + nu_crypto.c + 1 + ..\src\nu_crypto.c + + + nu_dac.c + 1 + ..\src\nu_dac.c + + + nu_eadc.c + 1 + ..\src\nu_eadc.c + + + nu_ebi.c + 1 + ..\src\nu_ebi.c + + + nu_ecap.c + 1 + ..\src\nu_ecap.c + + + nu_emac.c + 1 + ..\src\nu_emac.c + + + nu_epwm.c + 1 + ..\src\nu_epwm.c + + + nu_fmc.c + 1 + ..\src\nu_fmc.c + + + nu_gpio.c + 1 + ..\src\nu_gpio.c + + + nu_hsusbd.c + 1 + ..\src\nu_hsusbd.c + + + nu_i2c.c + 1 + ..\src\nu_i2c.c + + + nu_i2s.c + 1 + ..\src\nu_i2s.c + + + nu_pdma.c + 1 + ..\src\nu_pdma.c + + + nu_qei.c + 1 + ..\src\nu_qei.c + + + nu_qspi.c + 1 + ..\src\nu_qspi.c + + + nu_rtc.c + 1 + ..\src\nu_rtc.c + + + nu_sc.c + 1 + ..\src\nu_sc.c + + + nu_scuart.c + 1 + ..\src\nu_scuart.c + + + nu_sdh.c + 1 + ..\src\nu_sdh.c + + + nu_spi.c + 1 + ..\src\nu_spi.c + + + nu_spim.c + 1 + ..\src\nu_spim.c + + + nu_sys.c + 1 + ..\src\nu_sys.c + + + nu_timer.c + 1 + ..\src\nu_timer.c + + + nu_timer_pwm.c + 1 + ..\src\nu_timer_pwm.c + + + nu_trng.c + 1 + ..\src\nu_trng.c + + + nu_uart.c + 1 + ..\src\nu_uart.c + + + nu_usbd.c + 1 + ..\src\nu_usbd.c + + + nu_usci_i2c.c + 1 + ..\src\nu_usci_i2c.c + + + nu_usci_spi.c + 1 + ..\src\nu_usci_spi.c + + + nu_usci_uart.c + 1 + ..\src\nu_usci_uart.c + + + nu_wdt.c + 1 + ..\src\nu_wdt.c + + + nu_wwdt.c + 1 + ..\src\nu_wwdt.c + + + + + + + + diff --git a/bsp/nuvoton/libraries/m480/StdDriver/lib/nutool_clkcfg.h b/bsp/nuvoton/libraries/m480/StdDriver/lib/nutool_clkcfg.h new file mode 100644 index 0000000000000000000000000000000000000000..950b09946e24237cd387a6e19ff8439707aeb07f --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/lib/nutool_clkcfg.h @@ -0,0 +1,26 @@ +/**************************************************************************** + * @file nutool_clkcfg.h + * @version V1.05 + * @Date 2020/04/15-11:28:38 + * @brief NuMicro generated code file + * + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#ifndef __NUTOOL_CLKCFG_H__ +#define __NUTOOL_CLKCFG_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif +#undef __HXT +#define __HXT (12000000UL) /*!< High Speed External Crystal Clock Frequency */ + +#ifdef __cplusplus +} +#endif +#endif /*__NUTOOL_CLKCFG_H__*/ + +/*** (C) COPYRIGHT 2013-2020 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_acmp.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_acmp.c new file mode 100644 index 0000000000000000000000000000000000000000..6e42fd7a61c2ecd1ec1059d82ce4c86e571cd812 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_acmp.c @@ -0,0 +1,75 @@ +/**************************************************************************//** + * @file acmp.c + * @version V1.00 + * @brief M480 series Analog Comparator(ACMP) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup ACMP_Driver ACMP Driver + @{ +*/ + + +/** @addtogroup ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions + @{ +*/ + + +/** + * @brief Configure the specified ACMP module + * + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum Comparator number. + * @param[in] u32NegSrc Comparator negative input selection. Including: + * - \ref ACMP_CTL_NEGSEL_PIN + * - \ref ACMP_CTL_NEGSEL_CRV + * - \ref ACMP_CTL_NEGSEL_VBG + * - \ref ACMP_CTL_NEGSEL_DAC + * @param[in] u32HysSel The hysteresis function option. Including: + * - \ref ACMP_CTL_HYSTERESIS_30MV + * - \ref ACMP_CTL_HYSTERESIS_20MV + * - \ref ACMP_CTL_HYSTERESIS_10MV + * - \ref ACMP_CTL_HYSTERESIS_DISABLE + * + * @return None + * + * @details Configure hysteresis function, select the source of negative input and enable analog comparator. + */ +void ACMP_Open(ACMP_T *acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysSel) +{ + acmp->CTL[u32ChNum] = (acmp->CTL[u32ChNum] & (~(ACMP_CTL_NEGSEL_Msk | ACMP_CTL_HYSSEL_Msk))) | (u32NegSrc | u32HysSel | ACMP_CTL_ACMPEN_Msk); +} + +/** + * @brief Close analog comparator + * + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum Comparator number. + * + * @return None + * + * @details This function will clear ACMPEN bit of ACMP_CTL register to disable analog comparator. + */ +void ACMP_Close(ACMP_T *acmp, uint32_t u32ChNum) +{ + acmp->CTL[u32ChNum] &= (~ACMP_CTL_ACMPEN_Msk); +} + + + +/*@}*/ /* end of group ACMP_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group ACMP_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ + diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_bpwm.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_bpwm.c new file mode 100644 index 0000000000000000000000000000000000000000..4a6b08fbea65a4fbdb9d0c707457ea61e15eca78 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_bpwm.c @@ -0,0 +1,745 @@ +/**************************************************************************//** + * @file bpwm.c + * @version V1.00 + * @brief M480 series BPWM driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup BPWM_Driver BPWM Driver + @{ +*/ + + +/** @addtogroup BPWM_EXPORTED_FUNCTIONS BPWM Exported Functions + @{ +*/ + +/** + * @brief Configure BPWM capture and get the nearest unit time. + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32UnitTimeNsec The unit time of counter + * @param[in] u32CaptureEdge The condition to latch the counter. This parameter is not used + * @return The nearest unit time in nano second. + * @details This function is used to Configure BPWM capture and get the nearest unit time. + */ +uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge) +{ + uint32_t u32Src; + uint32_t u32PWMClockSrc; + uint32_t u32NearestUnitTimeNsec; + uint16_t u16Prescale = 1U, u16CNR = 0xFFFFU; + + if(bpwm == BPWM0) + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk; + } + else /* (bpwm == BPWM1) */ + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk; + } + + if(u32Src == 0U) + { + /* clock source is from PLL clock */ + u32PWMClockSrc = CLK_GetPLLClockFreq(); + } + else + { + /* clock source is from PCLK */ + SystemCoreClockUpdate(); + if(bpwm == BPWM0) + { + u32PWMClockSrc = CLK_GetPCLK0Freq(); + } + else /* (bpwm == BPWM1) */ + { + u32PWMClockSrc = CLK_GetPCLK1Freq(); + } + } + + u32PWMClockSrc /= 1000UL; + for(u16Prescale = 1U; u16Prescale <= 0x1000U; u16Prescale++) + { + uint32_t u32Exit = 0U; + u32NearestUnitTimeNsec = (1000000UL * u16Prescale) / u32PWMClockSrc; + if(u32NearestUnitTimeNsec < u32UnitTimeNsec) + { + if (u16Prescale == 0x1000U) /* limit to the maximum unit time(nano second) */ + { + u32Exit = 1U; + } + else + { + u32Exit = 0U; + } + if (!(1000000UL * (u16Prescale + 1UL) > (u32NearestUnitTimeNsec * u32PWMClockSrc))) + { + u32Exit = 1U; + } + else + { + u32Exit = 0U; + } + } + else + { + u32Exit = 1U; + } + if (u32Exit == 1U) + { + break; + } + else {} + } + + /* convert to real register value */ + /* all channels share a prescaler */ + u16Prescale -= 1U; + BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u16Prescale); + + /* set BPWM to down count type(edge aligned) */ + (bpwm)->CTL1 = (1UL); + + BPWM_SET_CNR(bpwm, u32ChannelNum, u16CNR); + + return (u32NearestUnitTimeNsec); +} + +/** + * @brief This function Configure BPWM generator and get the nearest frequency in edge aligned auto-reload mode + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Frequency Target generator frequency + * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%... + * @return Nearest frequency clock in nano second + * @note Since all channels shares a prescaler. Call this API to configure BPWM frequency may affect + * existing frequency of other channel. + */ +uint32_t BPWM_ConfigOutputChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle) +{ + uint32_t u32Src; + uint32_t u32PWMClockSrc; + uint32_t i; + uint32_t u32Prescale = 1U, u32CNR = 0xFFFFU; + + if(bpwm == BPWM0) + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk; + } + else /* (bpwm == BPWM1) */ + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk; + } + + if(u32Src == 0U) + { + /* clock source is from PLL clock */ + u32PWMClockSrc = CLK_GetPLLClockFreq(); + } + else + { + /* clock source is from PCLK */ + SystemCoreClockUpdate(); + if(bpwm == BPWM0) + { + u32PWMClockSrc = CLK_GetPCLK0Freq(); + } + else /* (bpwm == BPWM1) */ + { + u32PWMClockSrc = CLK_GetPCLK1Freq(); + } + } + + for(u32Prescale = 1U; u32Prescale < 0xFFFU; u32Prescale++) /* prescale could be 0~0xFFF */ + { + i = (u32PWMClockSrc / u32Frequency) / u32Prescale; + /* If target value is larger than CNR, need to use a larger prescaler */ + if(i < (0x10000U)) + { + u32CNR = i; + break; + } + } + /* Store return value here 'cos we're gonna change u16Prescale & u16CNR to the real value to fill into register */ + i = u32PWMClockSrc / (u32Prescale * u32CNR); + + /* convert to real register value */ + /* all channels share a prescaler */ + u32Prescale -= 1U; + BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u32Prescale); + /* set BPWM to down count type(edge aligned) */ + (bpwm)->CTL1 = (1UL); + + u32CNR -= 1U; + BPWM_SET_CNR(bpwm, u32ChannelNum, u32CNR); + if(u32DutyCycle) + { + BPWM_SET_CMR(bpwm, u32ChannelNum, u32DutyCycle * (u32CNR + 1UL) / 100UL - 1UL); + (bpwm)->WGCTL0 &= ~((BPWM_WGCTL0_PRDPCTL0_Msk | BPWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum * 2U)); + (bpwm)->WGCTL0 |= (BPWM_OUTPUT_LOW << ((u32ChannelNum * (2U)) + (uint32_t)BPWM_WGCTL0_PRDPCTL0_Pos)); + (bpwm)->WGCTL1 &= ~((BPWM_WGCTL1_CMPDCTL0_Msk | BPWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum * 2U)); + (bpwm)->WGCTL1 |= (BPWM_OUTPUT_HIGH << (u32ChannelNum * (2U) + (uint32_t)BPWM_WGCTL1_CMPDCTL0_Pos)); + } + else + { + BPWM_SET_CMR(bpwm, u32ChannelNum, 0U); + (bpwm)->WGCTL0 &= ~((BPWM_WGCTL0_PRDPCTL0_Msk | BPWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum * 2U)); + (bpwm)->WGCTL0 |= (BPWM_OUTPUT_LOW << (u32ChannelNum * 2U + (uint32_t)BPWM_WGCTL0_ZPCTL0_Pos)); + (bpwm)->WGCTL1 &= ~((BPWM_WGCTL1_CMPDCTL0_Msk | BPWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum * 2U)); + (bpwm)->WGCTL1 |= (BPWM_OUTPUT_HIGH << (u32ChannelNum * 2U + (uint32_t)BPWM_WGCTL1_CMPDCTL0_Pos)); + } + + return(i); +} + +/** + * @brief Start BPWM module + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @return None + * @details This function is used to start BPWM module. + * @note All channels share one counter. + */ +void BPWM_Start(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->CNTEN = BPWM_CNTEN_CNTEN0_Msk; +} + +/** + * @brief Stop BPWM module + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @return None + * @details This function is used to stop BPWM module. + * @note All channels share one period. + */ +void BPWM_Stop(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->PERIOD = 0U; +} + +/** + * @brief Stop BPWM generation immediately by clear channel enable bit + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @return None + * @details This function is used to stop BPWM generation immediately by clear channel enable bit. + * @note All channels share one counter. + */ +void BPWM_ForceStop(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->CNTEN &= ~BPWM_CNTEN_CNTEN0_Msk; +} + +/** + * @brief Enable selected channel to trigger ADC + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Condition The condition to trigger ADC. Combination of following conditions: + * - \ref BPWM_TRIGGER_ADC_EVEN_ZERO_POINT + * - \ref BPWM_TRIGGER_ADC_EVEN_PERIOD_POINT + * - \ref BPWM_TRIGGER_ADC_EVEN_ZERO_OR_PERIOD_POINT + * - \ref BPWM_TRIGGER_ADC_EVEN_CMP_UP_COUNT_POINT + * - \ref BPWM_TRIGGER_ADC_EVEN_CMP_DOWN_COUNT_POINT + * - \ref BPWM_TRIGGER_ADC_ODD_CMP_UP_COUNT_POINT + * - \ref BPWM_TRIGGER_ADC_ODD_CMP_DOWN_COUNT_POINT + * @return None + * @details This function is used to enable selected channel to trigger ADC + */ +void BPWM_EnableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + if(u32ChannelNum < 4U) + { + (bpwm)->EADCTS0 &= ~((BPWM_EADCTS0_TRGSEL0_Msk) << (u32ChannelNum * 8U)); + (bpwm)->EADCTS0 |= ((BPWM_EADCTS0_TRGEN0_Msk | u32Condition) << (u32ChannelNum * 8U)); + } + else + { + (bpwm)->EADCTS1 &= ~((BPWM_EADCTS1_TRGSEL4_Msk) << ((u32ChannelNum - 4U) * 8U)); + (bpwm)->EADCTS1 |= ((BPWM_EADCTS1_TRGEN4_Msk | u32Condition) << ((u32ChannelNum - 4U) * 8U)); + } +} + +/** + * @brief Disable selected channel to trigger ADC + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~3 + * @return None + * @details This function is used to disable selected channel to trigger ADC + */ +void BPWM_DisableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + if(u32ChannelNum < 4U) + { + (bpwm)->EADCTS0 &= ~(BPWM_EADCTS0_TRGEN0_Msk << (u32ChannelNum * 8U)); + } + else + { + (bpwm)->EADCTS1 &= ~(BPWM_EADCTS1_TRGEN4_Msk << ((u32ChannelNum - 4U) * 8U)); + } +} + +/** + * @brief Clear selected channel trigger ADC flag + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Condition This parameter is not used + * @return None + * @details This function is used to clear selected channel trigger ADC flag + */ +void BPWM_ClearADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + (bpwm)->STATUS = (BPWM_STATUS_EADCTRG0_Msk << u32ChannelNum); +} + +/** + * @brief Get selected channel trigger ADC flag + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @retval 0 The specified channel trigger ADC to start of conversion flag is not set + * @retval 1 The specified channel trigger ADC to start of conversion flag is set + * @details This function is used to get BPWM trigger ADC to start of conversion flag for specified channel + */ +uint32_t BPWM_GetADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + return (((bpwm)->STATUS & (BPWM_STATUS_EADCTRG0_Msk << u32ChannelNum)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture of selected channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to enable capture of selected channel(s) + */ +void BPWM_EnableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->CAPINEN |= u32ChannelMask; + (bpwm)->CAPCTL |= u32ChannelMask; +} + +/** + * @brief Disable capture of selected channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to disable capture of selected channel(s) + */ +void BPWM_DisableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->CAPINEN &= ~u32ChannelMask; + (bpwm)->CAPCTL &= ~u32ChannelMask; +} + +/** + * @brief Enables BPWM output generation of selected channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output... + * @return None + * @details This function is used to enables BPWM output generation of selected channel(s) + */ +void BPWM_EnableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->POEN |= u32ChannelMask; +} + +/** + * @brief Disables BPWM output generation of selected channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output... + * @return None + * @details This function is used to disables BPWM output generation of selected channel(s) + */ +void BPWM_DisableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->POEN &= ~u32ChannelMask; +} + +/** + * @brief Enable capture interrupt of selected channel. + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref BPWM_CAPTURE_INT_RISING_LATCH + * - \ref BPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to enable capture interrupt of selected channel. + */ +void BPWM_EnableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (bpwm)->CAPIEN |= (u32Edge << u32ChannelNum); +} + +/** + * @brief Disable capture interrupt of selected channel. + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref BPWM_CAPTURE_INT_RISING_LATCH + * - \ref BPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to disable capture interrupt of selected channel. + */ +void BPWM_DisableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (bpwm)->CAPIEN &= ~(u32Edge << u32ChannelNum); +} + +/** + * @brief Clear capture interrupt of selected channel. + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref BPWM_CAPTURE_INT_RISING_LATCH + * - \ref BPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to clear capture interrupt of selected channel. + */ +void BPWM_ClearCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (bpwm)->CAPIF = (u32Edge << u32ChannelNum); +} + +/** + * @brief Get capture interrupt of selected channel. + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @retval 0 No capture interrupt + * @retval 1 Rising edge latch interrupt + * @retval 2 Falling edge latch interrupt + * @retval 3 Rising and falling latch interrupt + * @details This function is used to get capture interrupt of selected channel. + */ +uint32_t BPWM_GetCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + return (((((bpwm)->CAPIF & (BPWM_CAPIF_CAPFIF0_Msk << u32ChannelNum)) ? 1UL : 0UL) << 1) | \ + (((bpwm)->CAPIF & (BPWM_CAPIF_CAPRIF0_Msk << u32ChannelNum)) ? 1UL : 0UL)); +} +/** + * @brief Enable duty interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32IntDutyType Duty interrupt type, could be either + * - \ref BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP + * - \ref BPWM_DUTY_INT_UP_COUNT_MATCH_CMP + * @return None + * @details This function is used to enable duty interrupt of selected channel. + */ +void BPWM_EnableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType) +{ + (bpwm)->INTEN |= (u32IntDutyType << u32ChannelNum); +} + +/** + * @brief Disable duty interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable duty interrupt of selected channel + */ +void BPWM_DisableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + + (bpwm)->INTEN &= ~((uint32_t)(BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP | BPWM_DUTY_INT_UP_COUNT_MATCH_CMP) << u32ChannelNum); +} + +/** + * @brief Clear duty interrupt flag of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear duty interrupt flag of selected channel + */ +void BPWM_ClearDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (bpwm)->INTSTS = (BPWM_INTSTS_CMPUIF0_Msk | BPWM_INTSTS_CMPDIF0_Msk) << u32ChannelNum; +} + +/** + * @brief Get duty interrupt flag of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return Duty interrupt flag of specified channel + * @retval 0 Duty interrupt did not occur + * @retval 1 Duty interrupt occurred + * @details This function is used to get duty interrupt flag of selected channel + */ +uint32_t BPWM_GetDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + return ((((bpwm)->INTSTS & ((BPWM_INTSTS_CMPDIF0_Msk | BPWM_INTSTS_CMPUIF0_Msk) << u32ChannelNum))) ? 1UL : 0UL); +} + +/** + * @brief Enable period interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @param[in] u32IntPeriodType Period interrupt type. This parameter is not used. + * @return None + * @details This function is used to enable period interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_EnablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType) +{ + (bpwm)->INTEN |= BPWM_INTEN_PIEN0_Msk; +} + +/** + * @brief Disable period interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to disable period interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_DisablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (bpwm)->INTEN &= ~BPWM_INTEN_PIEN0_Msk; +} + +/** + * @brief Clear period interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to clear period interrupt of selected channel + * @note All channels share channel 0's setting. + */ +void BPWM_ClearPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (bpwm)->INTSTS = BPWM_INTSTS_PIF0_Msk; +} + +/** + * @brief Get period interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return Period interrupt flag of specified channel + * @retval 0 Period interrupt did not occur + * @retval 1 Period interrupt occurred + * @details This function is used to get period interrupt of selected channel + * @note All channels share channel 0's setting. + */ +uint32_t BPWM_GetPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + return (((bpwm)->INTSTS & BPWM_INTSTS_PIF0_Msk) ? 1UL : 0UL); +} + +/** + * @brief Enable zero interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to enable zero interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_EnableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (bpwm)->INTEN |= BPWM_INTEN_ZIEN0_Msk; +} + +/** + * @brief Disable zero interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to disable zero interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_DisableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (bpwm)->INTEN &= ~BPWM_INTEN_ZIEN0_Msk; +} + +/** + * @brief Clear zero interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to clear zero interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_ClearZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (bpwm)->INTSTS = BPWM_INTSTS_ZIF0_Msk; +} + +/** + * @brief Get zero interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return zero interrupt flag of specified channel + * @retval 0 zero interrupt did not occur + * @retval 1 zero interrupt occurred + * @details This function is used to get zero interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +uint32_t BPWM_GetZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + return (((bpwm)->INTSTS & BPWM_INTSTS_ZIF0_Msk) ? 1UL : 0UL); +} + +/** + * @brief Enable load mode of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32LoadMode BPWM counter loading mode. + * - \ref BPWM_LOAD_MODE_IMMEDIATE + * - \ref BPWM_LOAD_MODE_CENTER + * @return None + * @details This function is used to enable load mode of selected channel. + */ +void BPWM_EnableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode) +{ + (bpwm)->CTL0 |= (u32LoadMode << u32ChannelNum); +} + +/** + * @brief Disable load mode of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32LoadMode PWM counter loading mode. + * - \ref BPWM_LOAD_MODE_IMMEDIATE + * - \ref BPWM_LOAD_MODE_CENTER + * @return None + * @details This function is used to disable load mode of selected channel. + */ +void BPWM_DisableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode) +{ + (bpwm)->CTL0 &= ~(u32LoadMode << u32ChannelNum); +} + +/** + * @brief Set BPWM clock source + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @param[in] u32ClkSrcSel BPWM external clock source. + * - \ref BPWM_CLKSRC_BPWM_CLK + * - \ref BPWM_CLKSRC_TIMER0 + * - \ref BPWM_CLKSRC_TIMER1 + * - \ref BPWM_CLKSRC_TIMER2 + * - \ref BPWM_CLKSRC_TIMER3 + * @return None + * @details This function is used to set BPWM clock source. + * @note All channels share channel 0's setting. + */ +void BPWM_SetClockSource(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel) +{ + (bpwm)->CLKSRC = (u32ClkSrcSel); +} + +/** + * @brief Get the time-base counter reached its maximum value flag of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return Count to max interrupt flag of specified channel + * @retval 0 Count to max interrupt did not occur + * @retval 1 Count to max interrupt occurred + * @details This function is used to get the time-base counter reached its maximum value flag of selected channel. + * @note All channels share channel 0's setting. + */ +uint32_t BPWM_GetWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + return (((bpwm)->STATUS & BPWM_STATUS_CNTMAX0_Msk) ? 1UL : 0UL); +} + +/** + * @brief Clear the time-base counter reached its maximum value flag of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to clear the time-base counter reached its maximum value flag of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_ClearWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (bpwm)->STATUS = BPWM_STATUS_CNTMAX0_Msk; +} + + +/*@}*/ /* end of group BPWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group BPWM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_can.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_can.c new file mode 100644 index 0000000000000000000000000000000000000000..8186886c2f860f271edf96e3c48e1cd211516150 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_can.c @@ -0,0 +1,1292 @@ +/**************************************************************************//** + * @file can.c + * @version V2.00 + * @brief M480 series CAN driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CAN_Driver CAN Driver + @{ +*/ + +/** @addtogroup CAN_EXPORTED_FUNCTIONS CAN Exported Functions + @{ +*/ + +/** @cond HIDDEN_SYMBOLS */ + +#if defined(CAN2) +static uint8_t gu8LockCanIf[3ul][2ul] = {0ul}; /* The chip has three CANs. */ +#elif defined(CAN1) +static uint8_t gu8LockCanIf[2ul][2ul] = {0ul}; /* The chip has two CANs. */ +#elif defined(CAN0) || defined(CAN) +static uint8_t gu8LockCanIf[1ul][2ul] = {0ul}; /* The chip only has one CAN. */ +#endif + +#define RETRY_COUNTS (0x10000000ul) + +#define TSEG1_MIN 2ul +#define TSEG1_MAX 16ul +#define TSEG2_MIN 1ul +#define TSEG2_MAX 8ul +#define BRP_MIN 1ul +#define BRP_MAX 1024ul /* 6-bit BRP field + 4-bit BRPE field*/ +#define SJW_MAX 4ul +#define BRP_INC 1ul + +/* #define DEBUG_PRINTF printf */ +#define DEBUG_PRINTF(...) + +static uint32_t LockIF(CAN_T *tCAN); +static uint32_t LockIF_TL(CAN_T *tCAN); +static void ReleaseIF(CAN_T *tCAN, uint32_t u32IfNo); +static int can_update_spt(int sampl_pt, int tseg, int *tseg1, int *tseg2); + +/** + * @brief Check if any interface is available then lock it for usage. + * @param[in] tCAN The pointer to CAN module base address. + * @retval 0 IF0 is free + * @retval 1 IF1 is free + * @retval 2 No IF is free + * @details Search the first free message interface, starting from 0. If a interface is + * available, set a flag to lock the interface. + */ +static uint32_t LockIF(CAN_T *tCAN) +{ + uint32_t u32CanNo; + uint32_t u32FreeIfNo; + uint32_t u32IntMask; + +#if defined(CAN1) + if(tCAN == CAN0) + u32CanNo = 0ul; + else if(tCAN == CAN1) + u32CanNo = 1ul; + #if defined(CAN2) + else if(tCAN == CAN2) + u32CanNo = 2ul; + #endif +#else /* defined(CAN0) || defined(CAN) */ + u32CanNo = 0ul; +#endif + + u32FreeIfNo = 2ul; + + /* Disable CAN interrupt */ + u32IntMask = tCAN->CON & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk); + tCAN->CON = tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk); + + /* Check interface 1 is available or not */ + if((tCAN->IF[0ul].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0ul) + { + if(gu8LockCanIf[u32CanNo][0ul] == 0ul) + { + gu8LockCanIf[u32CanNo][0ul] = 1u; + u32FreeIfNo = 0ul; + } + else + { + } + } + else + { + } + + /* Or check interface 2 is available or not */ + if(u32FreeIfNo == 2ul) + { + if((tCAN->IF[1ul].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0ul) + { + if(gu8LockCanIf[u32CanNo][1ul] == 0ul) + { + gu8LockCanIf[u32CanNo][1ul] = 1u; + u32FreeIfNo = 1ul; + } + else + { + } + } + else + { + } + } + else + { + } + + /* Enable CAN interrupt */ + tCAN->CON |= u32IntMask; + + return u32FreeIfNo; +} + +/** + * @brief Check if any interface is available in a time limitation then lock it for usage. + * @param[in] tCAN The pointer to CAN module base address. + * @retval 0 IF0 is free + * @retval 1 IF1 is free + * @retval 2 No IF is free + * @details Search the first free message interface, starting from 0. If no interface is + * it will try again until time out. If a interface is available, set a flag to + * lock the interface. + */ +static uint32_t LockIF_TL(CAN_T *tCAN) +{ + uint32_t u32Count; + uint32_t u32FreeIfNo; + + for(u32Count = 0ul; u32Count < RETRY_COUNTS; u32Count++) + { + if((u32FreeIfNo = LockIF(tCAN)) != 2ul) + { + break; + } + else + { + } + } + + return u32FreeIfNo; +} + +/** + * @brief Release locked interface. + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32Info The interface number, 0 or 1. + * @return none + * @details Release the locked interface. + */ +static void ReleaseIF(CAN_T *tCAN, uint32_t u32IfNo) +{ + uint32_t u32IntMask; + uint32_t u32CanNo; + + if(u32IfNo >= 2ul) + { + } + else + { +#if defined(CAN1) + if(tCAN == CAN0) + u32CanNo = 0ul; + else if(tCAN == CAN1) + u32CanNo = 1ul; + #if defined(CAN2) + else if(tCAN == CAN2) + u32CanNo = 2ul; + #endif +#else /* defined(CAN0) || defined(CAN) */ + u32CanNo = 0ul; +#endif + + /* Disable CAN interrupt */ + u32IntMask = tCAN->CON & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk); + tCAN->CON = tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk); + + gu8LockCanIf[u32CanNo][u32IfNo] = 0u; + + /* Enable CAN interrupt */ + tCAN->CON |= u32IntMask; + } +} + +static int can_update_spt(int sampl_pt, int tseg, int *tseg1, int *tseg2) +{ + *tseg2 = tseg + 1 - (sampl_pt * (tseg + 1)) / 1000; + if (*tseg2 < TSEG2_MIN) + { + *tseg2 = TSEG2_MIN; + } + else + { + } + + if (*tseg2 > TSEG2_MAX) + { + *tseg2 = TSEG2_MAX; + } + else + { + } + + *tseg1 = tseg - *tseg2; + if (*tseg1 > TSEG1_MAX) + { + *tseg1 = TSEG1_MAX; + *tseg2 = tseg - *tseg1; + } + else + { + } + + return 1000 * (tseg + 1 - *tseg2) / (tseg + 1); +} + +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief Enter initialization mode + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u8Mask Following values can be used. + * \ref CAN_CON_DAR_Msk Disable automatic retransmission. + * \ref CAN_CON_EIE_Msk Enable error interrupt. + * \ref CAN_CON_SIE_Msk Enable status interrupt. + * \ref CAN_CON_IE_Msk CAN interrupt. + * @return None + * @details This function is used to set CAN to enter initialization mode and enable access bit timing + * register. After bit timing configuration ready, user must call CAN_LeaveInitMode() + * to leave initialization mode and lock bit timing register to let new configuration + * take effect. + */ +void CAN_EnterInitMode(CAN_T *tCAN, uint8_t u8Mask) +{ + tCAN->CON = u8Mask | (CAN_CON_INIT_Msk | CAN_CON_CCE_Msk); +} + + +/** + * @brief Leave initialization mode + * @param[in] tCAN The pointer to CAN module base address. + * @return None + * @details This function is used to set CAN to leave initialization mode to let + * bit timing configuration take effect after configuration ready. + */ +void CAN_LeaveInitMode(CAN_T *tCAN) +{ + tCAN->CON &= (~(CAN_CON_INIT_Msk | CAN_CON_CCE_Msk)); + while(tCAN->CON & CAN_CON_INIT_Msk) + { + /* Check INIT bit is released */ + } +} + +/** + * @brief Wait message into message buffer in basic mode. + * @param[in] tCAN The pointer to CAN module base address. + * @return None + * @details This function is used to wait message into message buffer in basic mode. Please notice the + * function is polling NEWDAT bit of MCON register by while loop and it is used in basic mode. + */ +void CAN_WaitMsg(CAN_T *tCAN) +{ + tCAN->STATUS = 0x0ul; /* clr status */ + + while(1) + { + if(tCAN->IF[1].MCON & CAN_IF_MCON_NEWDAT_Msk) /* check new data */ + { + /* New Data IN */ + break; + } + else + { + } + + if(tCAN->STATUS & CAN_STATUS_RXOK_Msk) + { + /* Rx OK */ + } + else + { + } + + if(tCAN->STATUS & CAN_STATUS_LEC_Msk) + { + /* Error */ + } + else + { + } + } +} + +/** + * @brief Get current bit rate + * @param[in] tCAN The pointer to CAN module base address. + * @return Current Bit-Rate (kilo bit per second) + * @details Return current CAN bit rate according to the user bit-timing parameter settings + */ +uint32_t CAN_GetCANBitRate(CAN_T *tCAN) +{ + uint32_t u32Tseg1, u32Tseg2; + uint32_t u32Bpr; + + u32Tseg1 = (tCAN->BTIME & CAN_BTIME_TSEG1_Msk) >> CAN_BTIME_TSEG1_Pos; + u32Tseg2 = (tCAN->BTIME & CAN_BTIME_TSEG2_Msk) >> CAN_BTIME_TSEG2_Pos; + u32Bpr = (tCAN->BTIME & CAN_BTIME_BRP_Msk) | (tCAN->BRPE << 6ul); + + return (SystemCoreClock / (u32Bpr + 1ul) / (u32Tseg1 + u32Tseg2 + 3ul)); +} + +/** + * @brief Switch the CAN into test mode. + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u8TestMask Specifies the configuration in test modes + * \ref CAN_TEST_BASIC_Msk Enable basic mode of test mode + * \ref CAN_TEST_SILENT_Msk Enable silent mode of test mode + * \ref CAN_TEST_LBACK_Msk Enable Loop Back Mode of test mode + * \ref CAN_TEST_Tx_Msk Control CAN_TX pin bit field + * @return None + * @details Switch the CAN into test mode. There are four test mode (BASIC/SILENT/LOOPBACK/ + * LOOPBACK combined SILENT/CONTROL_TX_PIN)could be selected. After setting test mode,user + * must call CAN_LeaveInitMode() to let the setting take effect. + */ +void CAN_EnterTestMode(CAN_T *tCAN, uint8_t u8TestMask) +{ + tCAN->CON |= CAN_CON_TEST_Msk; + tCAN->TEST = u8TestMask; +} + + +/** + * @brief Leave the test mode + * @param[in] tCAN The pointer to CAN module base address. + * @return None + * @details This function is used to Leave the test mode (switch into normal mode). + */ +void CAN_LeaveTestMode(CAN_T *tCAN) +{ + tCAN->CON |= CAN_CON_TEST_Msk; + tCAN->TEST &= ~(CAN_TEST_LBACK_Msk | CAN_TEST_SILENT_Msk | CAN_TEST_BASIC_Msk); + tCAN->CON &= (~CAN_CON_TEST_Msk); +} + +/** + * @brief Get the waiting status of a received message. + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31. + * @retval non-zero The corresponding message object has a new data bit is set. + * @retval 0 No message object has new data. + * @details This function is used to get the waiting status of a received message. + */ +uint32_t CAN_IsNewDataReceived(CAN_T *tCAN, uint8_t u8MsgObj) +{ + return (u8MsgObj < 16ul ? tCAN->NDAT1 & (1ul << u8MsgObj) : tCAN->NDAT2 & (1ul << (u8MsgObj - 16ul))); +} + + +/** + * @brief Send CAN message in BASIC mode of test mode + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] pCanMsg Pointer to the message structure containing data to transmit. + * @return TRUE: Transmission OK + * FALSE: Check busy flag of interface 0 is timeout + * @details The function is used to send CAN message in BASIC mode of test mode. Before call the API, + * the user should be call CAN_EnterTestMode(CAN_TEST_BASIC) and let CAN controller enter + * basic mode of test mode. Please notice IF1 Registers used as Tx Buffer in basic mode. + */ +int32_t CAN_BasicSendMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg) +{ + uint32_t i = 0ul; + int32_t rev = 1l; + + while(tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk) + { + } + + tCAN->STATUS &= (~CAN_STATUS_TXOK_Msk); + + if(pCanMsg->IdType == CAN_STD_ID) + { + /* standard ID*/ + tCAN->IF[0].ARB1 = 0ul; + tCAN->IF[0].ARB2 = (((pCanMsg->Id) & 0x7FFul) << 2ul) ; + } + else + { + /* extended ID*/ + tCAN->IF[0].ARB1 = (pCanMsg->Id) & 0xFFFFul; + tCAN->IF[0].ARB2 = ((pCanMsg->Id) & 0x1FFF0000ul) >> 16ul | CAN_IF_ARB2_XTD_Msk; + + } + + if(pCanMsg->FrameType) + { + tCAN->IF[0].ARB2 |= CAN_IF_ARB2_DIR_Msk; + } + else + { + tCAN->IF[0].ARB2 &= (~CAN_IF_ARB2_DIR_Msk); + } + + tCAN->IF[0].MCON = (tCAN->IF[0].MCON & (~CAN_IF_MCON_DLC_Msk)) | pCanMsg->DLC; + tCAN->IF[0].DAT_A1 = (uint16_t)((uint16_t)((uint16_t)pCanMsg->Data[1] << 8) | pCanMsg->Data[0]); + tCAN->IF[0].DAT_A2 = (uint16_t)((uint16_t)((uint16_t)pCanMsg->Data[3] << 8) | pCanMsg->Data[2]); + tCAN->IF[0].DAT_B1 = (uint16_t)((uint16_t)((uint16_t)pCanMsg->Data[5] << 8) | pCanMsg->Data[4]); + tCAN->IF[0].DAT_B2 = (uint16_t)((uint16_t)((uint16_t)pCanMsg->Data[7] << 8) | pCanMsg->Data[6]); + + /* request transmission*/ + tCAN->IF[0].CREQ &= (~CAN_IF_CREQ_BUSY_Msk); + if(tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk) + { + /* Cannot clear busy for sending ...*/ + rev = 0l; /* return FALSE */ + } + else + { + tCAN->IF[0].CREQ |= CAN_IF_CREQ_BUSY_Msk; /* sending */ + + for(i = 0ul; i < 0xFFFFFul; i++) + { + if((tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0ul) + { + break; + } + else + { + } + } + + if(i >= 0xFFFFFul) + { + /* Cannot send out... */ + rev = 0l; /* return FALSE */ + } + else + { + } + } + + return rev; +} + +/** + * @brief Get a message information in BASIC mode. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] pCanMsg Pointer to the message structure where received data is copied. + * + * @return FALSE No any message received. + * TRUE Receive a message success. + * + */ +int32_t CAN_BasicReceiveMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg) +{ + int32_t rev = 1l; + + if((tCAN->IF[1].MCON & CAN_IF_MCON_NEWDAT_Msk) == 0ul) + { + /* In basic mode, receive data always save in IF2 */ + rev = 0; /* return FALSE */ + } + else + { + + tCAN->STATUS &= (~CAN_STATUS_RXOK_Msk); + + tCAN->IF[1].CMASK = CAN_IF_CMASK_ARB_Msk + | CAN_IF_CMASK_CONTROL_Msk + | CAN_IF_CMASK_DATAA_Msk + | CAN_IF_CMASK_DATAB_Msk; + + if((tCAN->IF[1].ARB2 & CAN_IF_ARB2_XTD_Msk) == 0ul) + { + /* standard ID*/ + pCanMsg->IdType = CAN_STD_ID; + pCanMsg->Id = (tCAN->IF[1].ARB2 >> 2) & 0x07FFul; + + } + else + { + /* extended ID*/ + pCanMsg->IdType = CAN_EXT_ID; + pCanMsg->Id = (tCAN->IF[1].ARB2 & 0x1FFFul) << 16; + pCanMsg->Id |= (uint32_t)tCAN->IF[1].ARB1; + } + + pCanMsg->FrameType = (((tCAN->IF[1].ARB2 & CAN_IF_ARB2_DIR_Msk) >> CAN_IF_ARB2_DIR_Pos)) ? 0ul : 1ul; + + pCanMsg->DLC = (uint8_t)(tCAN->IF[1].MCON & CAN_IF_MCON_DLC_Msk); + pCanMsg->Data[0] = (uint8_t)(tCAN->IF[1].DAT_A1 & CAN_IF_DAT_A1_DATA0_Msk); + pCanMsg->Data[1] = (uint8_t)((tCAN->IF[1].DAT_A1 & CAN_IF_DAT_A1_DATA1_Msk) >> CAN_IF_DAT_A1_DATA1_Pos); + pCanMsg->Data[2] = (uint8_t)(tCAN->IF[1].DAT_A2 & CAN_IF_DAT_A2_DATA2_Msk); + pCanMsg->Data[3] = (uint8_t)((tCAN->IF[1].DAT_A2 & CAN_IF_DAT_A2_DATA3_Msk) >> CAN_IF_DAT_A2_DATA3_Pos); + pCanMsg->Data[4] = (uint8_t)(tCAN->IF[1].DAT_B1 & CAN_IF_DAT_B1_DATA4_Msk); + pCanMsg->Data[5] = (uint8_t)((tCAN->IF[1].DAT_B1 & CAN_IF_DAT_B1_DATA5_Msk) >> CAN_IF_DAT_B1_DATA5_Pos); + pCanMsg->Data[6] = (uint8_t)(tCAN->IF[1].DAT_B2 & CAN_IF_DAT_B2_DATA6_Msk); + pCanMsg->Data[7] = (uint8_t)((tCAN->IF[1].DAT_B2 & CAN_IF_DAT_B2_DATA7_Msk) >> CAN_IF_DAT_B2_DATA7_Pos); + } + + return rev; +} + +/** + * @brief Set Rx message object, include ID mask. + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31. + * @param[in] u8idType Specifies the identifier type of the frames that will be transmitted + * This parameter can be one of the following values: + * \ref CAN_STD_ID (standard ID, 11-bit) + * \ref CAN_EXT_ID (extended ID, 29-bit) + * @param[in] u32id Specifies the identifier used for acceptance filtering. + * @param[in] u32idmask Specifies the identifier mask used for acceptance filtering. + * @param[in] u8singleOrFifoLast Specifies the end-of-buffer indicator. + * This parameter can be one of the following values: + * TRUE: for a single receive object or a FIFO receive object that is the last one of the FIFO. + * FALSE: for a FIFO receive object that is not the last one. + * @retval TRUE SUCCESS + * @retval FALSE No useful interface + * @details The function is used to configure a receive message object. + */ +int32_t CAN_SetRxMsgObjAndMsk(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint32_t u32idmask, uint8_t u8singleOrFifoLast) +{ + int32_t rev = 1l; + uint32_t u32MsgIfNum; + + /* Get and lock a free interface */ + if((u32MsgIfNum = LockIF_TL(tCAN)) == 2ul) + { + rev = 0; /* return FALSE */ + } + else + { + /* Command Setting */ + tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk | + CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk; + + if(u8idType == CAN_STD_ID) /* According STD/EXT ID format,Configure Mask and Arbitration register */ + { + tCAN->IF[u32MsgIfNum].ARB1 = 0ul; + tCAN->IF[u32MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | (u32id & 0x7FFul) << 2; + } + else + { + tCAN->IF[u32MsgIfNum].ARB1 = u32id & 0xFFFFul; + tCAN->IF[u32MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | CAN_IF_ARB2_XTD_Msk | (u32id & 0x1FFF0000ul) >> 16; + } + + tCAN->IF[u32MsgIfNum].MASK1 = (u32idmask & 0xFFFFul); + tCAN->IF[u32MsgIfNum].MASK2 = (u32idmask >> 16) & 0xFFFFul; + + /* tCAN->IF[u32MsgIfNum].MCON |= CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk; */ + tCAN->IF[u32MsgIfNum].MCON = CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk; + if(u8singleOrFifoLast) + { + tCAN->IF[u32MsgIfNum].MCON |= CAN_IF_MCON_EOB_Msk; + } + else + { + tCAN->IF[u32MsgIfNum].MCON &= (~CAN_IF_MCON_EOB_Msk); + } + + tCAN->IF[u32MsgIfNum].DAT_A1 = 0ul; + tCAN->IF[u32MsgIfNum].DAT_A2 = 0ul; + tCAN->IF[u32MsgIfNum].DAT_B1 = 0ul; + tCAN->IF[u32MsgIfNum].DAT_B2 = 0ul; + + tCAN->IF[u32MsgIfNum].CREQ = 1ul + u8MsgObj; + ReleaseIF(tCAN, u32MsgIfNum); + } + + return rev; +} + +/** + * @brief Set Rx message object + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31. + * @param[in] u8idType Specifies the identifier type of the frames that will be transmitted + * This parameter can be one of the following values: + * \ref CAN_STD_ID (standard ID, 11-bit) + * \ref CAN_EXT_ID (extended ID, 29-bit) + * @param[in] u32id Specifies the identifier used for acceptance filtering. + * @param[in] u8singleOrFifoLast Specifies the end-of-buffer indicator. + * This parameter can be one of the following values: + * TRUE: for a single receive object or a FIFO receive object that is the last one of the FIFO. + * FALSE: for a FIFO receive object that is not the last one. + * @retval TRUE SUCCESS + * @retval FALSE No useful interface + * @details The function is used to configure a receive message object. + */ +int32_t CAN_SetRxMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint8_t u8singleOrFifoLast) +{ + int32_t rev = 1l; + uint32_t u32MsgIfNum; + + /* Get and lock a free interface */ + if((u32MsgIfNum = LockIF_TL(tCAN)) == 2ul) + { + rev = 0; /* return FALSE */ + } + else + { + /* Command Setting */ + tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk | + CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk; + + if(u8idType == CAN_STD_ID) /* According STD/EXT ID format,Configure Mask and Arbitration register */ + { + tCAN->IF[u32MsgIfNum].ARB1 = 0ul; + tCAN->IF[u32MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | (u32id & 0x7FFul) << 2; + } + else + { + tCAN->IF[u32MsgIfNum].ARB1 = u32id & 0xFFFFul; + tCAN->IF[u32MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | CAN_IF_ARB2_XTD_Msk | (u32id & 0x1FFF0000ul) >> 16; + } + + /* tCAN->IF[u8MsgIfNum].MCON |= CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk; */ + tCAN->IF[u32MsgIfNum].MCON = CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk; + if(u8singleOrFifoLast) + { + tCAN->IF[u32MsgIfNum].MCON |= CAN_IF_MCON_EOB_Msk; + } + else + { + tCAN->IF[u32MsgIfNum].MCON &= (~CAN_IF_MCON_EOB_Msk); + } + + tCAN->IF[u32MsgIfNum].DAT_A1 = 0ul; + tCAN->IF[u32MsgIfNum].DAT_A2 = 0ul; + tCAN->IF[u32MsgIfNum].DAT_B1 = 0ul; + tCAN->IF[u32MsgIfNum].DAT_B2 = 0ul; + + tCAN->IF[u32MsgIfNum].CREQ = 1ul + u8MsgObj; + ReleaseIF(tCAN, u32MsgIfNum); + } + + return rev; +} + +/** + * @brief Gets the message + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31. + * @param[in] u8Release Specifies the message release indicator. + * This parameter can be one of the following values: + * TRUE: the message object is released when getting the data. + * FALSE:the message object is not released. + * @param[in] pCanMsg Pointer to the message structure where received data is copied. + * @retval TRUE Success + * @retval FALSE No any message received + * @details Gets the message, if received. + */ +int32_t CAN_ReadMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8Release, STR_CANMSG_T* pCanMsg) +{ + int32_t rev = 1l; + uint32_t u32MsgIfNum; + + if(!CAN_IsNewDataReceived(tCAN, u8MsgObj)) + { + rev = 0; /* return FALSE */ + } + else + { + /* Get and lock a free interface */ + if((u32MsgIfNum = LockIF_TL(tCAN)) == 2ul) + { + rev = 0; /* return FALSE */ + } + else + { + tCAN->STATUS &= (~CAN_STATUS_RXOK_Msk); + + /* read the message contents*/ + tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_MASK_Msk + | CAN_IF_CMASK_ARB_Msk + | CAN_IF_CMASK_CONTROL_Msk + | CAN_IF_CMASK_CLRINTPND_Msk + | (u8Release ? CAN_IF_CMASK_TXRQSTNEWDAT_Msk : 0ul) + | CAN_IF_CMASK_DATAA_Msk + | CAN_IF_CMASK_DATAB_Msk; + + tCAN->IF[u32MsgIfNum].CREQ = 1ul + u8MsgObj; + + while(tCAN->IF[u32MsgIfNum].CREQ & CAN_IF_CREQ_BUSY_Msk) + { + /*Wait*/ + } + + if((tCAN->IF[u32MsgIfNum].ARB2 & CAN_IF_ARB2_XTD_Msk) == 0ul) + { + /* standard ID*/ + pCanMsg->IdType = CAN_STD_ID; + pCanMsg->Id = (tCAN->IF[u32MsgIfNum].ARB2 & CAN_IF_ARB2_ID_Msk) >> 2ul; + } + else + { + /* extended ID*/ + pCanMsg->IdType = CAN_EXT_ID; + pCanMsg->Id = (((tCAN->IF[u32MsgIfNum].ARB2) & 0x1FFFul) << 16) | tCAN->IF[u32MsgIfNum].ARB1; + } + + pCanMsg->DLC = (uint8_t)(tCAN->IF[u32MsgIfNum].MCON & CAN_IF_MCON_DLC_Msk); + pCanMsg->Data[0] = (uint8_t)(tCAN->IF[u32MsgIfNum].DAT_A1 & CAN_IF_DAT_A1_DATA0_Msk); + pCanMsg->Data[1] = (uint8_t)((tCAN->IF[u32MsgIfNum].DAT_A1 & CAN_IF_DAT_A1_DATA1_Msk) >> CAN_IF_DAT_A1_DATA1_Pos); + pCanMsg->Data[2] = (uint8_t)(tCAN->IF[u32MsgIfNum].DAT_A2 & CAN_IF_DAT_A2_DATA2_Msk); + pCanMsg->Data[3] = (uint8_t)((tCAN->IF[u32MsgIfNum].DAT_A2 & CAN_IF_DAT_A2_DATA3_Msk) >> CAN_IF_DAT_A2_DATA3_Pos); + pCanMsg->Data[4] = (uint8_t)(tCAN->IF[u32MsgIfNum].DAT_B1 & CAN_IF_DAT_B1_DATA4_Msk); + pCanMsg->Data[5] = (uint8_t)((tCAN->IF[u32MsgIfNum].DAT_B1 & CAN_IF_DAT_B1_DATA5_Msk) >> CAN_IF_DAT_B1_DATA5_Pos); + pCanMsg->Data[6] = (uint8_t)(tCAN->IF[u32MsgIfNum].DAT_B2 & CAN_IF_DAT_B2_DATA6_Msk); + pCanMsg->Data[7] = (uint8_t)((tCAN->IF[u32MsgIfNum].DAT_B2 & CAN_IF_DAT_B2_DATA7_Msk) >> CAN_IF_DAT_B2_DATA7_Pos); + + ReleaseIF(tCAN, u32MsgIfNum); + } + } + + return rev; +} + + +/** + * @brief Set bus baud-rate. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32BaudRate The target CAN baud-rate. The range of u32BaudRate is 1~1000KHz. + * + * @return u32CurrentBitRate Real baud-rate value. + * + * @details The function is used to set bus timing parameter according current clock and target baud-rate. + */ +uint32_t CAN_SetBaudRate(CAN_T *tCAN, uint32_t u32BaudRate) +{ + long rate; + long best_error = 1000000000, error = 0; + int best_tseg = 0, best_brp = 0, brp = 0; + int tsegall, tseg = 0, tseg1 = 0, tseg2 = 0; + int spt_error = 1000, spt = 0, sampl_pt; + uint64_t clock_freq = (uint64_t)0, u64PCLK_DIV = (uint64_t)1; + uint32_t sjw = (uint32_t)1; + + CAN_EnterInitMode(tCAN, (uint8_t)0); + + SystemCoreClockUpdate(); + if((tCAN == CAN0) || (tCAN == CAN2)) + { + u64PCLK_DIV = (uint64_t)(CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk); + u64PCLK_DIV = (uint64_t)(1 << u64PCLK_DIV); + } + else if(tCAN == CAN1) + { + u64PCLK_DIV = (uint64_t)((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) >> CLK_PCLKDIV_APB1DIV_Pos); + u64PCLK_DIV = (uint64_t)(1 << u64PCLK_DIV); + } + + clock_freq = SystemCoreClock / u64PCLK_DIV; + + if(u32BaudRate >= (uint32_t)1000000) + { + u32BaudRate = (uint32_t)1000000; + } + + /* Use CIA recommended sample points */ + if (u32BaudRate > (uint32_t)800000) + { + sampl_pt = (int)750; + } + else if (u32BaudRate > (uint32_t)500000) + { + sampl_pt = (int)800; + } + else + { + sampl_pt = (int)875; + } + + /* tseg even = round down, odd = round up */ + for (tseg = (TSEG1_MAX + TSEG2_MAX) * 2ul + 1ul; tseg >= (TSEG1_MIN + TSEG2_MIN) * 2ul; tseg--) + { + tsegall = 1ul + tseg / 2ul; + /* Compute all possible tseg choices (tseg=tseg1+tseg2) */ + brp = clock_freq / (tsegall * u32BaudRate) + tseg % 2; + /* chose brp step which is possible in system */ + brp = (brp / BRP_INC) * BRP_INC; + + if ((brp < BRP_MIN) || (brp > BRP_MAX)) + { + continue; + } + rate = clock_freq / (brp * tsegall); + + error = u32BaudRate - rate; + + /* tseg brp biterror */ + if (error < 0) + { + error = -error; + } + if (error > best_error) + { + continue; + } + best_error = error; + if (error == 0) + { + spt = can_update_spt(sampl_pt, tseg / 2, &tseg1, &tseg2); + error = sampl_pt - spt; + if (error < 0) + { + error = -error; + } + if (error > spt_error) + { + continue; + } + spt_error = error; + } + best_tseg = tseg / 2; + best_brp = brp; + + if (error == 0) + { + break; + } + } + + spt = can_update_spt(sampl_pt, best_tseg, &tseg1, &tseg2); + + /* check for sjw user settings */ + /* bt->sjw is at least 1 -> sanitize upper bound to sjw_max */ + if (sjw > SJW_MAX) + { + sjw = SJW_MAX; + } + /* bt->sjw must not be higher than tseg2 */ + if (tseg2 < sjw) + { + sjw = tseg2; + } + + /* real bit-rate */ + u32BaudRate = clock_freq / (best_brp * (tseg1 + tseg2 + 1)); + + tCAN->BTIME = ((uint32_t)(tseg2 - 1ul) << CAN_BTIME_TSEG2_Pos) | ((uint32_t)(tseg1 - 1ul) << CAN_BTIME_TSEG1_Pos) | + ((uint32_t)(best_brp - 1ul) & CAN_BTIME_BRP_Msk) | (sjw << CAN_BTIME_SJW_Pos); + tCAN->BRPE = ((uint32_t)(best_brp - 1ul) >> 6) & 0x0Ful; + + /* printf("\n bitrate = %d \n", CAN_GetCANBitRate(tCAN)); */ + + CAN_LeaveInitMode(tCAN); + + return u32BaudRate; +} + +/** + * @brief The function is used to disable all CAN interrupt. + * + * @param[in] tCAN The pointer to CAN module base address. + * + * @return None + * + * @details No Status Change Interrupt and Error Status Interrupt will be generated. + */ +void CAN_Close(CAN_T *tCAN) +{ + CAN_DisableInt(tCAN, (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk)); +} + +/** + * @brief Set CAN operation mode and target baud-rate. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32BaudRate The target CAN baud-rate. The range of u32BaudRate is 1~1000KHz. + * @param[in] u32Mode The CAN operation mode. Valid values are: + * - \ref CAN_NORMAL_MODE Normal operation. + * - \ref CAN_BASIC_MODE Basic mode. + * @return u32CurrentBitRate Real baud-rate value. + * + * @details Set bus timing parameter according current clock and target baud-rate. + * In Basic mode, IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer. + */ +uint32_t CAN_Open(CAN_T *tCAN, uint32_t u32BaudRate, uint32_t u32Mode) +{ + uint32_t u32CurrentBitRate; + + u32CurrentBitRate = CAN_SetBaudRate(tCAN, u32BaudRate); + + if(u32Mode == CAN_BASIC_MODE) + { + CAN_EnterTestMode(tCAN, (uint8_t)CAN_TEST_BASIC_Msk); + } + else + { + } + + return u32CurrentBitRate; +} + +/** + * @brief The function is used to configure a transmit object. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31. + * @param[in] pCanMsg Pointer to the message structure where received data is copied. + * + * @retval FALSE No useful interface. + * @retval TRUE Config message object success. + * + * @details The two sets of interface registers (IF1 and IF2) control the software access to the Message RAM. + * They buffer the data to be transferred to and from the RAM, avoiding conflicts between software accesses and message reception/transmission. + */ +int32_t CAN_SetTxMsg(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg) +{ + int32_t rev = 1l; + uint32_t u32MsgIfNum; + + if((u32MsgIfNum = LockIF_TL(tCAN)) == 2ul) + { + rev = 0; /* return FALSE */ + } + else + { + /* update the contents needed for transmission*/ + tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk | + CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk; + + if(pCanMsg->IdType == CAN_STD_ID) + { + /* standard ID*/ + tCAN->IF[u32MsgIfNum].ARB1 = 0ul; + tCAN->IF[u32MsgIfNum].ARB2 = (((pCanMsg->Id) & 0x7FFul) << 2) | CAN_IF_ARB2_DIR_Msk | CAN_IF_ARB2_MSGVAL_Msk; + } + else + { + /* extended ID*/ + tCAN->IF[u32MsgIfNum].ARB1 = (pCanMsg->Id) & 0xFFFFul; + tCAN->IF[u32MsgIfNum].ARB2 = ((pCanMsg->Id) & 0x1FFF0000ul) >> 16 | + CAN_IF_ARB2_DIR_Msk | CAN_IF_ARB2_XTD_Msk | CAN_IF_ARB2_MSGVAL_Msk; + } + + if(pCanMsg->FrameType) + { + tCAN->IF[u32MsgIfNum].ARB2 |= CAN_IF_ARB2_DIR_Msk; + } + else + { + tCAN->IF[u32MsgIfNum].ARB2 &= (~CAN_IF_ARB2_DIR_Msk); + } + + tCAN->IF[u32MsgIfNum].DAT_A1 = (uint16_t)((uint16_t)(((uint16_t)pCanMsg->Data[1] << 8)) | pCanMsg->Data[0]); + tCAN->IF[u32MsgIfNum].DAT_A2 = (uint16_t)((uint16_t)(((uint16_t)pCanMsg->Data[3] << 8)) | pCanMsg->Data[2]); + tCAN->IF[u32MsgIfNum].DAT_B1 = (uint16_t)((uint16_t)(((uint16_t)pCanMsg->Data[5] << 8)) | pCanMsg->Data[4]); + tCAN->IF[u32MsgIfNum].DAT_B2 = (uint16_t)((uint16_t)(((uint16_t)pCanMsg->Data[7] << 8)) | pCanMsg->Data[6]); + + tCAN->IF[u32MsgIfNum].MCON = CAN_IF_MCON_NEWDAT_Msk | pCanMsg->DLC | CAN_IF_MCON_TXIE_Msk | CAN_IF_MCON_EOB_Msk; + tCAN->IF[u32MsgIfNum].CREQ = 1ul + u32MsgNum; + + ReleaseIF(tCAN, u32MsgIfNum); + } + + return rev; +} + +/** + * @brief Set transmit request bit. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31. + * + * @return TRUE: Start transmit message. + * + * @details If a transmission is requested by programming bit TxRqst/NewDat (IFn_CMASK[2]), the TxRqst (IFn_MCON[8]) will be ignored. + */ +int32_t CAN_TriggerTxMsg(CAN_T *tCAN, uint32_t u32MsgNum) +{ + int32_t rev = 1l; + uint32_t u32MsgIfNum; + + if((u32MsgIfNum = LockIF_TL(tCAN)) == 2ul) + { + rev = 0; /* return FALSE */ + } + else + { + tCAN->STATUS &= (~CAN_STATUS_TXOK_Msk); + + /* read the message contents*/ + tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_CLRINTPND_Msk + | CAN_IF_CMASK_TXRQSTNEWDAT_Msk; + + tCAN->IF[u32MsgIfNum].CREQ = 1ul + u32MsgNum; + + while(tCAN->IF[u32MsgIfNum].CREQ & CAN_IF_CREQ_BUSY_Msk) + { + /*Wait*/ + } + tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk; + tCAN->IF[u32MsgIfNum].CREQ = 1ul + u32MsgNum; + + ReleaseIF(tCAN, u32MsgIfNum); + } + + return rev; +} + +/** + * @brief Enable CAN interrupt. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32Mask Interrupt Mask. Valid values are: + * - \ref CAN_CON_IE_Msk Module interrupt enable. + * - \ref CAN_CON_SIE_Msk Status change interrupt enable. + * - \ref CAN_CON_EIE_Msk Error interrupt enable. + * + * @return None + * + * @details The application software has two possibilities to follow the source of a message interrupt. + * First, it can follow the IntId in the Interrupt Register and second it can poll the Interrupt Pending Register. + */ +void CAN_EnableInt(CAN_T *tCAN, uint32_t u32Mask) +{ + tCAN->CON = (tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk)) | + (u32Mask & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk)); +} + +/** + * @brief Disable CAN interrupt. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32Mask Interrupt Mask. (CAN_CON_IE_Msk / CAN_CON_SIE_Msk / CAN_CON_EIE_Msk). + * + * @return None + * + * @details The interrupt remains active until the Interrupt Register is back to value zero (the cause of the interrupt is reset) or until IE is reset. + */ +void CAN_DisableInt(CAN_T *tCAN, uint32_t u32Mask) +{ + tCAN->CON = tCAN->CON & ~((u32Mask & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk))); +} + + +/** + * @brief The function is used to configure a receive message object. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31. + * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are: + * - \ref CAN_STD_ID The 11-bit identifier. + * - \ref CAN_EXT_ID The 29-bit identifier. + * @param[in] u32ID Specifies the identifier used for acceptance filtering. + * + * @retval FALSE No useful interface. + * @retval TRUE Configure a receive message object success. + * + * @details If the RxIE bit (CAN_IFn_MCON[10]) is set, the IntPnd bit (CAN_IFn_MCON[13]) + * will be set when a received Data Frame is accepted and stored in the Message Object. + */ +int32_t CAN_SetRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID) +{ + int32_t rev = (int32_t)TRUE; + uint32_t u32TimeOutCount = 0ul; + + while(CAN_SetRxMsgObj(tCAN, (uint8_t)u32MsgNum, (uint8_t)u32IDType, u32ID, (uint8_t)TRUE) == (int32_t)FALSE) + { + if(++u32TimeOutCount >= RETRY_COUNTS) + { + rev = (int32_t)(FALSE); /* return FALSE */ + break; + } + else + { + } + } + + return rev; +} + +/** + * @brief The function is used to configure a receive message object. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31. + * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are: + * - \ref CAN_STD_ID The 11-bit identifier. + * - \ref CAN_EXT_ID The 29-bit identifier. + * @param[in] u32ID Specifies the identifier used for acceptance filtering. + * @param[in] u32IDMask Specifies the identifier mask used for acceptance filtering. + * + * @retval FALSE No useful interface. + * @retval TRUE Configure a receive message object success. + * + * @details If the RxIE bit (CAN_IFn_MCON[10]) is set, the IntPnd bit (CAN_IFn_MCON[13]) + * will be set when a received Data Frame is accepted and stored in the Message Object. + */ +int32_t CAN_SetRxMsgAndMsk(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID, uint32_t u32IDMask) +{ + int32_t rev = (int32_t)TRUE; + uint32_t u32TimeOutCount = 0ul; + + while(CAN_SetRxMsgObjAndMsk(tCAN, (uint8_t)u32MsgNum, (uint8_t)u32IDType, u32ID, u32IDMask, (uint8_t)TRUE) == (int32_t)FALSE) + { + if(++u32TimeOutCount >= RETRY_COUNTS) + { + rev = (int32_t)FALSE; + break; + } + else + { + } + } + + return rev; +} + +/** + * @brief The function is used to configure several receive message objects. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum The starting MSG RAM number(0 ~ 31). + * @param[in] u32MsgCount the number of MSG RAM of the FIFO. + * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are: + * - \ref CAN_STD_ID The 11-bit identifier. + * - \ref CAN_EXT_ID The 29-bit identifier. + * @param[in] u32ID Specifies the identifier used for acceptance filtering. + * + * @retval FALSE No useful interface. + * @retval TRUE Configure receive message objects success. + * + * @details The Interface Registers avoid conflict between the CPU accesses to the Message RAM and CAN message reception + * and transmission by buffering the data to be transferred. + */ +int32_t CAN_SetMultiRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32MsgCount, uint32_t u32IDType, uint32_t u32ID) +{ + int32_t rev = (int32_t)TRUE; + uint32_t i = 0ul; + uint32_t u32TimeOutCount; + uint32_t u32EOB_Flag = 0ul; + + for(i = 1ul; i < u32MsgCount; i++) + { + u32TimeOutCount = 0ul; + + u32MsgNum += (i - 1ul); + + if(i == u32MsgCount) + { + u32EOB_Flag = 1ul; + } + else + { + } + + while(CAN_SetRxMsgObj(tCAN, (uint8_t)u32MsgNum, (uint8_t)u32IDType, u32ID, (uint8_t)u32EOB_Flag) == (int32_t)FALSE) + { + if(++u32TimeOutCount >= RETRY_COUNTS) + { + rev = (int32_t)FALSE; + break; + } + else + { + } + } + } + + return rev; +} + + +/** + * @brief Send CAN message. + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31. + * @param[in] pCanMsg Pointer to the message structure where received data is copied. + * + * @retval FALSE 1. When operation in basic mode: Transmit message time out. \n + * 2. When operation in normal mode: No useful interface. \n + * @retval TRUE Transmit Message success. + * + * @details The receive/transmit priority for the Message Objects is attached to the message number. + * Message Object 1 has the highest priority, while Message Object 32 has the lowest priority. + */ +int32_t CAN_Transmit(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg) +{ + int32_t rev = (int32_t)TRUE; + uint32_t u32Tmp; + + u32Tmp = (tCAN->TEST & CAN_TEST_BASIC_Msk); + + if((tCAN->CON & CAN_CON_TEST_Msk) && u32Tmp) + { + rev = CAN_BasicSendMsg(tCAN, pCanMsg); + } + else + { + if(CAN_SetTxMsg(tCAN, u32MsgNum, pCanMsg) == FALSE) + { + rev = (int32_t)FALSE; + } + else + { + CAN_TriggerTxMsg(tCAN, u32MsgNum); + } + } + + return rev; +} + + +/** + * @brief Gets the message, if received. + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31. + * @param[in] pCanMsg Pointer to the message structure where received data is copied. + * + * @retval FALSE No any message received. + * @retval TRUE Receive Message success. + * + * @details The Interface Registers avoid conflict between the CPU accesses to the Message RAM and CAN message reception + * and transmission by buffering the data to be transferred. + */ +int32_t CAN_Receive(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg) +{ + int32_t rev = (int32_t)TRUE; + uint32_t u32Tmp; + + u32Tmp = (tCAN->TEST & CAN_TEST_BASIC_Msk); + + if((tCAN->CON & CAN_CON_TEST_Msk) && u32Tmp) + { + rev = CAN_BasicReceiveMsg(tCAN, pCanMsg); + } + else + { + rev = CAN_ReadMsgObj(tCAN, (uint8_t)u32MsgNum, (uint8_t)TRUE, pCanMsg); + } + + return rev; +} + +/** + * @brief Clear interrupt pending bit. + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31. + * + * @return None + * + * @details An interrupt remains pending until the application software has cleared it. + */ +void CAN_CLR_INT_PENDING_BIT(CAN_T *tCAN, uint8_t u32MsgNum) +{ + uint32_t u32MsgIfNum; + + if((u32MsgIfNum = LockIF_TL(tCAN)) == 2ul) + { + u32MsgIfNum = 0ul; + } + else + { + } + + tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_CLRINTPND_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk; + tCAN->IF[u32MsgIfNum].CREQ = 1ul + u32MsgNum; + + ReleaseIF(tCAN, u32MsgIfNum); +} + + +/*@}*/ /* end of group CAN_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CAN_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ + diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_ccap.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_ccap.c new file mode 100644 index 0000000000000000000000000000000000000000..5da53eb79b53b9a23ee7e318fe4c950cc0813d61 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_ccap.c @@ -0,0 +1,296 @@ +/**************************************************************************//** + * @file ccap.c + * @version V1.00 + * @brief M480 Series CCAP Driver Source File + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#include "NuMicro.h" +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CCAP_Driver CCAP Driver + @{ +*/ + + +/** @addtogroup CCAP_EXPORTED_FUNCTIONS CCAP Exported Functions + @{ +*/ + +/** + * @brief Open engine clock and sensor clock + * + * @param[in] u32InFormat The bits corresponding VSP, HSP, PCLK, INFMT, SNRTYPE, OUTFMT, PDORD and PNFMT configurations. + * - VSP should be ether \ref CCAP_PAR_VSP_LOW or \ref CCAP_PAR_VSP_HIGH + * - HSP should be ether \ref CCAP_PAR_HSP_LOW or \ref CCAP_PAR_HSP_HIGH + * - PCLK should be ether \ref CCAP_PAR_PCLKP_LOW or \ref CCAP_PAR_PCLKP_HIGH + * - INFMT should be ether \ref CCAP_PAR_INFMT_YUV422 or \ref CCAP_PAR_INFMT_RGB565 + * - SNRTYPE should be ether \ref CCAP_PAR_SENTYPE_CCIR601 or \ref CCAP_PAR_SENTYPE_CCIR656 + * - OUTFMT should be one of the following setting + * - \ref CCAP_PAR_OUTFMT_YUV422 + * - \ref CCAP_PAR_OUTFMT_ONLY_Y + * - \ref CCAP_PAR_OUTFMT_RGB555 + * - \ref CCAP_PAR_OUTFMT_RGB565 + * - PDORD should be one of the following setting + * - \ref CCAP_PAR_INDATORD_YUYV + * - \ref CCAP_PAR_INDATORD_YVYU + * - \ref CCAP_PAR_INDATORD_UYVY + * - \ref CCAP_PAR_INDATORD_VYUY + * - \ref CCAP_PAR_INDATORD_RGGB + * - \ref CCAP_PAR_INDATORD_BGGR + * - \ref CCAP_PAR_INDATORD_GBRG + * - \ref CCAP_PAR_INDATORD_GRBG + * - PNFMT should be one of the following setting + * - \ref CCAP_PAR_PLNFMT_YUV422 + * - \ref CCAP_PAR_PLNFMT_YUV420 + * + * @param[in] u32OutFormet Capture output format, should be one of following setting + * - \ref CCAP_CTL_PKTEN + * + * @return None + * + * @details Initialize the Image Capture Interface. Register a call back for driver internal using + */ +void CCAP_Open(uint32_t u32InFormat, uint32_t u32OutFormet) +{ + CCAP->PAR = (CCAP->PAR & ~(0x000007BFUL)) | u32InFormat; + CCAP->CTL = (CCAP->CTL & ~(0x00000040UL)) | u32OutFormet; +} + +/** + * @brief Set Cropping Window Starting Address and Size + * + * @param[in] u32VStart: Cropping Window Vertical Starting Address. It should be 0 ~ 0x7FF. + * + * @param[in] u32HStart: Cropping Window Horizontal Starting Address. It should be 0 ~ 0x7FF. + * + * @param[in] u32Height: Cropping Window Height . It should be 0 ~ 0x7FF. + * + * @param[in] u32Width: Cropping Window Width. It should be 0 ~ 0x7FF. + * + * @return None + * + * @details Set Cropping Window Starting Address Register + */ +void CCAP_SetCroppingWindow(uint32_t u32VStart,uint32_t u32HStart, uint32_t u32Height, uint32_t u32Width) +{ + CCAP->CWSP = (CCAP->CWSP & ~(CCAP_CWSP_CWSADDRV_Msk | CCAP_CWSP_CWSADDRH_Msk)) + | (((u32VStart << 16) | u32HStart)); + + CCAP->CWS = (CCAP->CWS & ~(CCAP_CWS_CWH_Msk | CCAP_CWS_CWW_Msk)) + | ((u32Height << 16)| u32Width); +} + + +/** + * @brief Set System Memory Packet Base Address0 Register + * + * @param[in] u32Address : set PKTBA0 register, It should be 0x0 ~ 0xFFFFFFFF + * + * @return None + * + * @details Set System Memory Packet Base Address Register + */ +void CCAP_SetPacketBuf(uint32_t u32Address ) +{ + CCAP->PKTBA0 = u32Address; + CCAP->CTL |= CCAP_CTL_UPDATE_Msk; +} + +/** + * @brief Close Camera Capture Interface + * + * @return None + */ +void CCAP_Close(void) +{ + CCAP->CTL &= ~CCAP_CTL_CCAPEN; +} + + +/** + * @brief Set CCAP Interrupt + * + * @param[in] u32IntMask Interrupt settings. It could be + * - \ref CCAP_INT_VIEN_Msk + * - \ref CCAP_INT_MEIEN_Msk + * - \ref CCAP_INT_ADDRMIEN_Msk + * @return None + * + * @details Set Video Frame End Interrupt Enable, + * System Memory Error Interrupt Enable, + * Address Match Interrupt Enable, + * Motion Detection Output Finish Interrupt Enable. + */ +void CCAP_EnableInt(uint32_t u32IntMask) +{ + CCAP->INT = (CCAP->INT & ~(CCAP_INT_VIEN_Msk | CCAP_INT_MEIEN_Msk | CCAP_INT_ADDRMIEN_Msk ) ) + | u32IntMask; +} + +/** + * @brief Disable CCAP Interrupt + * + * @param[in] u32IntMask Interrupt settings. It could be + * - \ref CCAP_INT_VINTF_Msk + * - \ref CCAP_INT_MEINTF_Msk + * - \ref CCAP_INT_ADDRMINTF_Msk + + * @return None + * + * @details Disable Video Frame End Interrupt , + * System Memory Error Interrupt , + * Address Match Interrupt and + * Motion Detection Output Finish Interrupt . + */ +void CCAP_DisableInt(uint32_t u32IntMask) +{ + CCAP->INT = (CCAP->INT & ~(u32IntMask) ) ; +} + + +/** + * @brief Enable Monochrome CMOS Sensor + * + * @param[in] u32Interface I/O interface settings. It could be + * - \ref CCAP_CTL_MY8_MY4 + * - \ref CCAP_CTL_MY8_MY8 + * @return None + * + */ +void CCAP_EnableMono(uint32_t u32Interface) +{ + CCAP->CTL = (CCAP->CTL & ~CCAP_CTL_MY8_MY4) | CCAP_CTL_MONO_Msk |u32Interface; +} + +/** + * @brief Disable Monochrome CMOS Sensor + * + * @return None + * + */ +void CCAP_DisableMono(void) +{ + CCAP->CTL |= CCAP_CTL_MONO_Msk; +} + +/** + * @brief Enable Luminance 8-bit Y to 1-bit Y Conversion + * + * @param[in] u32th Luminance Y8 to Y1 Threshold Value, It should be 0 ~ 255. + * + * @return None + * + */ +void CCAP_EnableLumaYOne(uint32_t u32th) +{ + CCAP->CTL |= CCAP_CTL_Luma_Y_One_Msk; + CCAP->LUMA_Y1_THD = u32th & 0xff; +} + +/** + * @brief Disable Luminance 8-bit Y to 1-bit Y Conversion + * + * @return None + * + */ +void CCAP_DisableLumaYOne(void) +{ + CCAP->CTL &= ~CCAP_CTL_Luma_Y_One_Msk; +} + +/** + * @brief Start Camera Capture Interface + * + * @return None + */ +void CCAP_Start(void) +{ + CCAP->CTL |= CCAP_CTL_CCAPEN; +} + +/** + * @brief Stop Camera Capture Interface + * + * @param[in] u32FrameComplete : + * TRUE: Capture module automatically disable the CCAP module after a frame had been captured + * FALSE: Stop Capture module now + * @return None + * + * @details if u32FrameComplete is set to TRUE then get a new frame and disable CCAP module + */ +void CCAP_Stop(uint32_t u32FrameComplete) +{ + if(u32FrameComplete==FALSE) + CCAP->CTL &= ~CCAP_CTL_CCAPEN; + else + { + CCAP->CTL |= CCAP_CTL_SHUTTER_Msk; + while(CCAP_IS_STOPPED()); + } +} + +/** + * @brief Set Packet Scaling Vertical and Horizontal Factor Register + * + * @param[in] u32VNumerator: Packet Scaling Vertical Factor N. It should be 0 ~ FFFF. + * + * @param[in] u32VDenominator: Packet Scaling Vertical Factor M. It should be 0 ~ FFFF. + * + * @param[in] u32HNumerator: Packet Scaling Vertical Factor N. It should be 0 ~ FFFF. + * + * @param[in] u32HDenominator: Packet Scaling Vertical Factor M. It should be 0 ~ FFFF. + * + * @return None + * + */ +void CCAP_SetPacketScaling(uint32_t u32VNumerator, uint32_t u32VDenominator, uint32_t u32HNumerator, uint32_t u32HDenominator) +{ + uint32_t u32NumeratorL, u32NumeratorH; + uint32_t u32DenominatorL, u32DenominatorH; + + u32NumeratorL = u32VNumerator&0xFF; + u32NumeratorH=u32VNumerator>>8; + u32DenominatorL = u32VDenominator&0xFF; + u32DenominatorH = u32VDenominator>>8; + CCAP->PKTSL = (CCAP->PKTSL & ~(CCAP_PKTSL_PKTSVNL_Msk | CCAP_PKTSL_PKTSVML_Msk)) + | ((u32NumeratorL << 24)| (u32DenominatorL << 16)); + CCAP->PKTSM = (CCAP->PKTSM & ~(CCAP_PKTSM_PKTSVNH_Msk | CCAP_PKTSM_PKTSVMH_Msk)) + | ((u32NumeratorH << 24) | (u32DenominatorH << 16)); + + u32NumeratorL = u32HNumerator&0xFF; + u32NumeratorH=u32HNumerator>>8; + u32DenominatorL = u32HDenominator&0xFF; + u32DenominatorH = u32HDenominator>>8; + CCAP->PKTSL = (CCAP->PKTSL & ~(CCAP_PKTSL_PKTSHNL_Msk | CCAP_PKTSL_PKTSHML_Msk)) + | ((u32NumeratorL << 8)| u32DenominatorL); + CCAP->PKTSM = (CCAP->PKTSM & ~(CCAP_PKTSM_PKTSHNH_Msk | CCAP_PKTSM_PKTSHMH_Msk)) + | ((u32NumeratorH << 8) | u32DenominatorH); +} + +/** + * @brief Set Packet Frame Output Pixel Stride Width. + * + * @param[in] u32Stride : set PKTSTRIDE register, It should be 0x0 ~ 0x3FFF + * + * @return None + * + * @details Set Packet Frame Output Pixel Stride Width + */ +void CCAP_SetPacketStride(uint32_t u32Stride ) +{ + CCAP->STRIDE = (CCAP->STRIDE & ~CCAP_STRIDE_PKTSTRIDE_Msk) | u32Stride; +} + + +/*@}*/ /* end of group CCAP_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CCAP_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_clk.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_clk.c new file mode 100644 index 0000000000000000000000000000000000000000..1a23b44e10ecb220c8aeca4ebfb01533dc578087 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_clk.c @@ -0,0 +1,1353 @@ +/**************************************************************************//** + * @file clk.c + * @version V3.00 + * @brief M480 series CLK driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CLK_Driver CLK Driver + @{ +*/ + +/** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions + @{ +*/ + +/** + * @brief Disable clock divider output function + * @param None + * @return None + * @details This function disable clock divider output function. + */ +void CLK_DisableCKO(void) +{ + /* Disable CKO clock source */ + CLK_DisableModuleClock(CLKO_MODULE); +} + +/** + * @brief This function enable clock divider output module clock, + * enable clock divider output function and set frequency selection. + * @param[in] u32ClkSrc is frequency divider function clock source. Including : + * - \ref CLK_CLKSEL1_CLKOSEL_HXT + * - \ref CLK_CLKSEL1_CLKOSEL_LXT + * - \ref CLK_CLKSEL1_CLKOSEL_HCLK + * - \ref CLK_CLKSEL1_CLKOSEL_HIRC + * @param[in] u32ClkDiv is divider output frequency selection. It could be 0~15. + * @param[in] u32ClkDivBy1En is clock divided by one enabled. + * @return None + * @details Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv. \n + * The formula is: \n + * CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1) \n + * This function is just used to set CKO clock. + * User must enable I/O for CKO clock output pin by themselves. \n + */ +void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En) +{ + /* CKO = clock source / 2^(u32ClkDiv + 1) */ + CLK->CLKOCTL = CLK_CLKOCTL_CLKOEN_Msk | (u32ClkDiv) | (u32ClkDivBy1En << CLK_CLKOCTL_DIV1EN_Pos); + + /* Enable CKO clock source */ + CLK_EnableModuleClock(CLKO_MODULE); + + /* Select CKO clock source */ + CLK_SetModuleClock(CLKO_MODULE, u32ClkSrc, 0UL); +} + +/** + * @brief Enter to Power-down mode + * @param None + * @return None + * @details This function is used to let system enter to Power-down mode. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_PowerDown(void) +{ + uint32_t u32HIRCTRIMCTL; + + /* Set the processor uses deep sleep as its low power mode */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Set system Power-down enabled */ + CLK->PWRCTL |= (CLK_PWRCTL_PDEN_Msk); + + /* Store HIRC control register */ + u32HIRCTRIMCTL = SYS->IRCTCTL; + + /* Disable HIRC auto trim */ + SYS->IRCTCTL &= (~SYS_IRCTCTL_FREQSEL_Msk); + + /* Chip enter Power-down mode after CPU run WFI instruction */ + __WFI(); + + /* Restore HIRC control register */ + SYS->IRCTCTL = u32HIRCTRIMCTL; +} + +/** + * @brief Enter to Idle mode + * @param None + * @return None + * @details This function let system enter to Idle mode. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_Idle(void) +{ + /* Set the processor uses sleep as its low power mode */ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + + /* Set chip in idle mode because of WFI command */ + CLK->PWRCTL &= ~CLK_PWRCTL_PDEN_Msk; + + /* Chip enter idle mode after CPU run WFI instruction */ + __WFI(); +} + +/** + * @brief Get external high speed crystal clock frequency + * @param None + * @return External high frequency crystal frequency + * @details This function get external high frequency crystal frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetHXTFreq(void) +{ + uint32_t u32Freq; + + if((CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk) == CLK_PWRCTL_HXTEN_Msk) + { + u32Freq = __HXT; + } + else + { + u32Freq = 0UL; + } + + return u32Freq; +} + + +/** + * @brief Get external low speed crystal clock frequency + * @param None + * @return External low speed crystal clock frequency + * @details This function get external low frequency crystal frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetLXTFreq(void) +{ + uint32_t u32Freq; + if((CLK->PWRCTL & CLK_PWRCTL_LXTEN_Msk) == CLK_PWRCTL_LXTEN_Msk) + { + u32Freq = __LXT; + } + else + { + u32Freq = 0UL; + } + + return u32Freq; +} + +/** + * @brief Get PCLK0 frequency + * @param None + * @return PCLK0 frequency + * @details This function get PCLK0 frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetPCLK0Freq(void) +{ + uint32_t u32Freq; + SystemCoreClockUpdate(); + + if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_APB0DIV_DIV1) + { + u32Freq = SystemCoreClock; + } + else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_APB0DIV_DIV2) + { + u32Freq = SystemCoreClock / 2UL; + } + else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_APB0DIV_DIV4) + { + u32Freq = SystemCoreClock / 4UL; + } + else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_APB0DIV_DIV8) + { + u32Freq = SystemCoreClock / 8UL; + } + else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_APB0DIV_DIV16) + { + u32Freq = SystemCoreClock / 16UL; + } + else + { + u32Freq = SystemCoreClock; + } + + return u32Freq; +} + + +/** + * @brief Get PCLK1 frequency + * @param None + * @return PCLK1 frequency + * @details This function get PCLK1 frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetPCLK1Freq(void) +{ + uint32_t u32Freq; + SystemCoreClockUpdate(); + + if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_APB1DIV_DIV1) + { + u32Freq = SystemCoreClock; + } + else if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_APB1DIV_DIV2) + { + u32Freq = SystemCoreClock / 2UL; + } + else if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_APB1DIV_DIV4) + { + u32Freq = SystemCoreClock / 4UL; + } + else if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_APB1DIV_DIV8) + { + u32Freq = SystemCoreClock / 8UL; + } + else if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_APB1DIV_DIV16) + { + u32Freq = SystemCoreClock / 16UL; + } + else + { + u32Freq = SystemCoreClock; + } + + return u32Freq; +} + + +/** + * @brief Get HCLK frequency + * @param None + * @return HCLK frequency + * @details This function get HCLK frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetHCLKFreq(void) +{ + SystemCoreClockUpdate(); + return SystemCoreClock; +} + + +/** + * @brief Get CPU frequency + * @param None + * @return CPU frequency + * @details This function get CPU frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetCPUFreq(void) +{ + SystemCoreClockUpdate(); + return SystemCoreClock; +} + + +/** + * @brief Set HCLK frequency + * @param[in] u32Hclk is HCLK frequency. The range of u32Hclk is running up to 192MHz. + * @return HCLK frequency + * @details This function is used to set HCLK frequency. The frequency unit is Hz. \n + * The register write-protection function should be disabled before using this function. + */ +uint32_t CLK_SetCoreClock(uint32_t u32Hclk) +{ + uint32_t u32HIRCSTB; + + /* Read HIRC clock source stable flag */ + u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk; + + /* The range of u32Hclk is running up to 192 MHz */ + if(u32Hclk > FREQ_192MHZ) + { + u32Hclk = FREQ_192MHZ; + } + + /* Switch HCLK clock source to HIRC clock for safe */ + CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk; + CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); + CLK->CLKSEL0 |= CLK_CLKSEL0_HCLKSEL_Msk; + CLK->CLKDIV0 &= (~CLK_CLKDIV0_HCLKDIV_Msk); + + /* Configure PLL setting if HXT clock is enabled */ + if((CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk) == CLK_PWRCTL_HXTEN_Msk) + { + u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HXT, u32Hclk); + } + /* Configure PLL setting if HXT clock is not enabled */ + else + { + u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HIRC, u32Hclk); + + /* Read HIRC clock source stable flag */ + u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk; + } + + /* Select HCLK clock source to PLL, + and update system core clock + */ + CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL, CLK_CLKDIV0_HCLK(1UL)); + + /* Disable HIRC if HIRC is disabled before setting core clock */ + if(u32HIRCSTB == 0UL) + { + CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk; + } + + /* Return actually HCLK frequency is PLL frequency divide 1 */ + return u32Hclk; +} + +/** + * @brief This function set HCLK clock source and HCLK clock divider + * @param[in] u32ClkSrc is HCLK clock source. Including : + * - \ref CLK_CLKSEL0_HCLKSEL_HXT + * - \ref CLK_CLKSEL0_HCLKSEL_LXT + * - \ref CLK_CLKSEL0_HCLKSEL_PLL + * - \ref CLK_CLKSEL0_HCLKSEL_LIRC + * - \ref CLK_CLKSEL0_HCLKSEL_HIRC + * @param[in] u32ClkDiv is HCLK clock divider. Including : + * - \ref CLK_CLKDIV0_HCLK(x) + * @return None + * @details This function set HCLK clock source and HCLK clock divider. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv) +{ + uint32_t u32HIRCSTB; + + /* Read HIRC clock source stable flag */ + u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk; + + /* Switch to HIRC for Safe. Avoid HCLK too high when applying new divider. */ + CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk; + CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); + CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | CLK_CLKSEL0_HCLKSEL_HIRC; + + /* Apply new Divider */ + CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_HCLKDIV_Msk)) | u32ClkDiv; + + /* Switch HCLK to new HCLK source */ + CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | u32ClkSrc; + + /* Update System Core Clock */ + SystemCoreClockUpdate(); + + /* Disable HIRC if HIRC is disabled before switching HCLK source */ + if(u32HIRCSTB == 0UL) + { + CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk; + } +} + +/** + * @brief This function set selected module clock source and module clock divider + * @param[in] u32ModuleIdx is module index. + * @param[in] u32ClkSrc is module clock source. + * @param[in] u32ClkDiv is module clock divider. + * @return None + * @details Valid parameter combinations listed in following table: + * + * |Module index |Clock source |Divider | + * | :---------------- | :----------------------------------- | :-------------------------- | + * |\ref CCAP_MODULE |\ref CLK_CLKSEL0_CCAPSEL_HXT |\ref CLK_CLKDIV3_CCAP(x) | + * |\ref CCAP_MODULE |\ref CLK_CLKSEL0_CCAPSEL_PLL |\ref CLK_CLKDIV3_CCAP(x) | + * |\ref CCAP_MODULE |\ref CLK_CLKSEL0_CCAPSEL_HIRC |\ref CLK_CLKDIV3_CCAP(x) | + * |\ref CCAP_MODULE |\ref CLK_CLKSEL0_CCAPSEL_HCLK |\ref CLK_CLKDIV3_CCAP(x) | + * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_HXT |\ref CLK_CLKDIV0_SDH0(x) | + * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_PLL |\ref CLK_CLKDIV0_SDH0(x) | + * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_HIRC |\ref CLK_CLKDIV0_SDH0(x) | + * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_HCLK |\ref CLK_CLKDIV0_SDH0(x) | + * |\ref SDH1_MODULE |\ref CLK_CLKSEL0_SDH1SEL_HXT |\ref CLK_CLKDIV3_SDH1(x) | + * |\ref SDH1_MODULE |\ref CLK_CLKSEL0_SDH1SEL_PLL |\ref CLK_CLKDIV3_SDH1(x) | + * |\ref SDH1_MODULE |\ref CLK_CLKSEL0_SDH1SEL_HIRC |\ref CLK_CLKDIV3_SDH1(x) | + * |\ref SDH1_MODULE |\ref CLK_CLKSEL0_SDH1SEL_HCLK |\ref CLK_CLKDIV3_SDH1(x) | + * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LXT | x | + * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LIRC | x | + * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HXT | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LXT | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LIRC | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HIRC | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_PCLK0 | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_EXT | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HXT | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LXT | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LIRC | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HIRC | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_PCLK0 | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_EXT | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HXT | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LXT | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LIRC | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HIRC | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_PCLK1 | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_EXT | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HXT | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LXT | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LIRC | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HIRC | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_PCLK1 | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_EXT | x | + * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_HXT |\ref CLK_CLKDIV0_UART0(x) | + * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_LXT |\ref CLK_CLKDIV0_UART0(x) | + * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_PLL |\ref CLK_CLKDIV0_UART0(x) | + * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_HIRC |\ref CLK_CLKDIV0_UART0(x) | + * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_HXT |\ref CLK_CLKDIV0_UART1(x) | + * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_LXT |\ref CLK_CLKDIV0_UART1(x) | + * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_PLL |\ref CLK_CLKDIV0_UART1(x) | + * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_HIRC |\ref CLK_CLKDIV0_UART1(x) | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HXT | x | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_LXT | x | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HIRC | x | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HCLK | x | + * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_LIRC | x | + * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 | x | + * |\ref EPWM0_MODULE |\ref CLK_CLKSEL2_EPWM0SEL_PLL | x | + * |\ref EPWM0_MODULE |\ref CLK_CLKSEL2_EPWM0SEL_PCLK0 | x | + * |\ref EPWM1_MODULE |\ref CLK_CLKSEL2_EPWM1SEL_PLL | x | + * |\ref EPWM1_MODULE |\ref CLK_CLKSEL2_EPWM1SEL_PCLK1 | x | + * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_HXT | x | + * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_PLL | x | + * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_HIRC | x | + * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_PCLK0 | x | + * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_HXT | x | + * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_PLL | x | + * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_HIRC | x | + * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_PCLK1 | x | + * |\ref BPWM0_MODULE |\ref CLK_CLKSEL2_BPWM0SEL_PLL | x | + * |\ref BPWM0_MODULE |\ref CLK_CLKSEL2_BPWM0SEL_PCLK0 | x | + * |\ref BPWM1_MODULE |\ref CLK_CLKSEL2_BPWM1SEL_PLL | x | + * |\ref BPWM1_MODULE |\ref CLK_CLKSEL2_BPWM1SEL_PCLK1 | x | + * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_HXT | x | + * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_PLL | x | + * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_HIRC | x | + * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_PCLK0 | x | + * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_HXT | x | + * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_PLL | x | + * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_HIRC | x | + * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_PCLK1 | x | + * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_HXT | x | + * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_PLL | x | + * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_HIRC | x | + * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_PCLK0 | x | + * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HXT |\ref CLK_CLKDIV1_SC0(x) | + * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PLL |\ref CLK_CLKDIV1_SC0(x) | + * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HIRC |\ref CLK_CLKDIV1_SC0(x) | + * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PCLK0 |\ref CLK_CLKDIV1_SC0(x) | + * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_HXT |\ref CLK_CLKDIV1_SC1(x) | + * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_PLL |\ref CLK_CLKDIV1_SC1(x) | + * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_HIRC |\ref CLK_CLKDIV1_SC1(x) | + * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_PCLK1 |\ref CLK_CLKDIV1_SC1(x) | + * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_HXT |\ref CLK_CLKDIV1_SC2(x) | + * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_PLL |\ref CLK_CLKDIV1_SC2(x) | + * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_HIRC |\ref CLK_CLKDIV1_SC2(x) | + * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_PCLK0 |\ref CLK_CLKDIV1_SC2(x) | + * |\ref RTC_MODULE |\ref CLK_CLKSEL3_RTCSEL_LXT | x | + * |\ref RTC_MODULE |\ref CLK_CLKSEL3_RTCSEL_LIRC | x | + * |\ref QSPI1_MODULE |\ref CLK_CLKSEL3_QSPI1SEL_HXT | x | + * |\ref QSPI1_MODULE |\ref CLK_CLKSEL3_QSPI1SEL_PLL | x | + * |\ref QSPI1_MODULE |\ref CLK_CLKSEL3_QSPI1SEL_HIRC | x | + * |\ref QSPI1_MODULE |\ref CLK_CLKSEL3_QSPI1SEL_PCLK1 | x | + * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_HXT |\ref CLK_CLKDIV2_I2S0(x) | + * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_PLL |\ref CLK_CLKDIV2_I2S0(x) | + * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_HIRC |\ref CLK_CLKDIV2_I2S0(x) | + * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_PCLK0 |\ref CLK_CLKDIV2_I2S0(x) | + * |\ref UART6_MODULE |\ref CLK_CLKSEL3_UART6SEL_HXT |\ref CLK_CLKDIV4_UART6(x) | + * |\ref UART6_MODULE |\ref CLK_CLKSEL3_UART6SEL_LXT |\ref CLK_CLKDIV4_UART6(x) | + * |\ref UART6_MODULE |\ref CLK_CLKSEL3_UART6SEL_PLL |\ref CLK_CLKDIV4_UART6(x) | + * |\ref UART6_MODULE |\ref CLK_CLKSEL3_UART6SEL_HIRC |\ref CLK_CLKDIV4_UART6(x) | + * |\ref UART7_MODULE |\ref CLK_CLKSEL3_UART7SEL_HXT |\ref CLK_CLKDIV4_UART7(x) | + * |\ref UART7_MODULE |\ref CLK_CLKSEL3_UART7SEL_LXT |\ref CLK_CLKDIV4_UART7(x) | + * |\ref UART7_MODULE |\ref CLK_CLKSEL3_UART7SEL_PLL |\ref CLK_CLKDIV4_UART7(x) | + * |\ref UART7_MODULE |\ref CLK_CLKSEL3_UART7SEL_HIRC |\ref CLK_CLKDIV4_UART7(x) | + * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_HXT |\ref CLK_CLKDIV4_UART2(x) | + * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_LXT |\ref CLK_CLKDIV4_UART2(x) | + * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_PLL |\ref CLK_CLKDIV4_UART2(x) | + * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_HIRC |\ref CLK_CLKDIV4_UART2(x) | + * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_HXT |\ref CLK_CLKDIV4_UART3(x) | + * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_LXT |\ref CLK_CLKDIV4_UART3(x) | + * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_PLL |\ref CLK_CLKDIV4_UART3(x) | + * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_HIRC |\ref CLK_CLKDIV4_UART3(x) | + * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_HXT |\ref CLK_CLKDIV4_UART4(x) | + * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_LXT |\ref CLK_CLKDIV4_UART4(x) | + * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_PLL |\ref CLK_CLKDIV4_UART4(x) | + * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_HIRC |\ref CLK_CLKDIV4_UART4(x) | + * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_HXT |\ref CLK_CLKDIV4_UART5(x) | + * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_LXT |\ref CLK_CLKDIV4_UART5(x) | + * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_PLL |\ref CLK_CLKDIV4_UART5(x) | + * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_HIRC |\ref CLK_CLKDIV4_UART5(x) | + * |\ref EADC_MODULE | x |\ref CLK_CLKDIV0_EADC(x) | + * |\ref EADC1_MODULE | x |\ref CLK_CLKDIV2_EADC1(x) | + * |\ref EMAC_MODULE | x |\ref CLK_CLKDIV3_EMAC(x) | + * + */ +void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv) +{ + uint32_t u32sel = 0U, u32div = 0U; + + if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk) + { + /* Get clock divider control register address */ + if ((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x1) // M480LD + { + if(MODULE_CLKDIV(u32ModuleIdx) == 2U && MODULE_IP_EN_Pos_ENC(u32ModuleIdx) == 31U) //EADC1 + { + u32div = (uint32_t)&CLK->CLKDIV2; + } + else if(MODULE_CLKDIV(u32ModuleIdx) == 2U && MODULE_IP_EN_Pos_ENC(u32ModuleIdx) == 29U) //I2S0 + { + u32div = (uint32_t)&CLK->CLKDIV2; + } + else if (MODULE_CLKDIV(u32ModuleIdx) == 2U) + { + u32div = (uint32_t)&CLK->CLKDIV3; + } + else if (MODULE_CLKDIV(u32ModuleIdx) == 3U) + { + u32div = (uint32_t)&CLK->CLKDIV4; + } + else + { + u32div = (uint32_t)&CLK->CLKDIV0 + ((MODULE_CLKDIV(u32ModuleIdx)) * 4U); + } + } + else + { + /* Get clock divider control register address */ + if(MODULE_CLKDIV(u32ModuleIdx) == 2U) + { + u32div = (uint32_t)&CLK->CLKDIV3; + } + else if (MODULE_CLKDIV(u32ModuleIdx) == 3U) + { + u32div = (uint32_t)&CLK->CLKDIV4; + } + else + { + u32div = (uint32_t)&CLK->CLKDIV0 + ((MODULE_CLKDIV(u32ModuleIdx)) * 4U); + } + } + + /* Apply new divider */ + M32(u32div) = (M32(u32div) & (~(MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx)))) | u32ClkDiv; + } + + if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk) + { + /* Get clock select control register address */ + u32sel = (uint32_t)&CLK->CLKSEL0 + ((MODULE_CLKSEL(u32ModuleIdx)) * 4U); + /* Set new clock selection setting */ + M32(u32sel) = (M32(u32sel) & (~(MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx)))) | u32ClkSrc; + } +} + +/** + * @brief Set SysTick clock source + * @param[in] u32ClkSrc is module clock source. Including: + * - \ref CLK_CLKSEL0_STCLKSEL_HXT + * - \ref CLK_CLKSEL0_STCLKSEL_LXT + * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2 + * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 + * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 + * @return None + * @details This function set SysTick clock source. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc) +{ + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc; + +} + +/** + * @brief Enable clock source + * @param[in] u32ClkMask is clock source mask. Including : + * - \ref CLK_PWRCTL_HXTEN_Msk + * - \ref CLK_PWRCTL_LXTEN_Msk + * - \ref CLK_PWRCTL_HIRCEN_Msk + * - \ref CLK_PWRCTL_LIRCEN_Msk + * @return None + * @details This function enable clock source. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_EnableXtalRC(uint32_t u32ClkMask) +{ + CLK->PWRCTL |= u32ClkMask; +} + +/** + * @brief Disable clock source + * @param[in] u32ClkMask is clock source mask. Including : + * - \ref CLK_PWRCTL_HXTEN_Msk + * - \ref CLK_PWRCTL_LXTEN_Msk + * - \ref CLK_PWRCTL_HIRCEN_Msk + * - \ref CLK_PWRCTL_LIRCEN_Msk + * @return None + * @details This function disable clock source. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_DisableXtalRC(uint32_t u32ClkMask) +{ + CLK->PWRCTL &= ~u32ClkMask; +} + +/** + * @brief Enable module clock + * @param[in] u32ModuleIdx is module index. Including : + * - \ref PDMA_MODULE + * - \ref ISP_MODULE + * - \ref EBI_MODULE + * - \ref EMAC_MODULE + * - \ref SDH0_MODULE + * - \ref CRC_MODULE + * - \ref CCAP_MODULE + * - \ref SEN_MODULE + * - \ref HSUSBD_MODULE + * - \ref CRPT_MODULE + * - \ref SPIM_MODULE + * - \ref FMCIDLE_MODULE + * - \ref USBH_MODULE + * - \ref SDH1_MODULE + * - \ref WDT_MODULE + * - \ref RTC_MODULE + * - \ref TMR0_MODULE + * - \ref TMR1_MODULE + * - \ref TMR2_MODULE + * - \ref TMR3_MODULE + * - \ref CLKO_MODULE + * - \ref WWDT_MODULE + * - \ref ACMP01_MODULE + * - \ref I2C0_MODULE + * - \ref I2C1_MODULE + * - \ref I2C2_MODULE + * - \ref QSPI0_MODULE + * - \ref SPI0_MODULE + * - \ref SPI1_MODULE + * - \ref SPI2_MODULE + * - \ref UART0_MODULE + * - \ref UART1_MODULE + * - \ref UART2_MODULE + * - \ref UART3_MODULE + * - \ref UART4_MODULE + * - \ref UART5_MODULE + * - \ref UART6_MODULE + * - \ref UART7_MODULE + * - \ref CAN0_MODULE + * - \ref CAN1_MODULE + * - \ref OTG_MODULE + * - \ref USBD_MODULE + * - \ref EADC_MODULE + * - \ref I2S0_MODULE + * - \ref HSOTG_MODULE + * - \ref SC0_MODULE + * - \ref SC1_MODULE + * - \ref SC2_MODULE + * - \ref QSPI1_MODULE + * - \ref SPI3_MODULE + * - \ref USCI0_MODULE + * - \ref USCI1_MODULE + * - \ref DAC_MODULE + * - \ref CAN2_MODULE + * - \ref EPWM0_MODULE + * - \ref EPWM1_MODULE + * - \ref BPWM0_MODULE + * - \ref BPWM1_MODULE + * - \ref QEI0_MODULE + * - \ref QEI1_MODULE + * - \ref TRNG_MODULE + * - \ref ECAP0_MODULE + * - \ref ECAP1_MODULE + * - \ref CAN2_MODULE + * - \ref OPA_MODULE + * - \ref EADC1_MODULE + * @return None + * @details This function is used to enable module clock. + */ +void CLK_EnableModuleClock(uint32_t u32ModuleIdx) +{ + uint32_t u32tmpVal = 0UL, u32tmpAddr = 0UL; + + u32tmpVal = (1UL << MODULE_IP_EN_Pos(u32ModuleIdx)); + u32tmpAddr = (uint32_t)&CLK->AHBCLK; + u32tmpAddr += ((MODULE_APBCLK(u32ModuleIdx) * 4UL)); + + *(volatile uint32_t *)u32tmpAddr |= u32tmpVal; +} + +/** + * @brief Disable module clock + * @param[in] u32ModuleIdx is module index. Including : + * - \ref PDMA_MODULE + * - \ref ISP_MODULE + * - \ref EBI_MODULE + * - \ref EMAC_MODULE + * - \ref SDH0_MODULE + * - \ref CRC_MODULE + * - \ref CCAP_MODULE + * - \ref SEN_MODULE + * - \ref HSUSBD_MODULE + * - \ref CRPT_MODULE + * - \ref SPIM_MODULE + * - \ref FMCIDLE_MODULE + * - \ref USBH_MODULE + * - \ref SDH1_MODULE + * - \ref WDT_MODULE + * - \ref RTC_MODULE + * - \ref TMR0_MODULE + * - \ref TMR1_MODULE + * - \ref TMR2_MODULE + * - \ref TMR3_MODULE + * - \ref CLKO_MODULE + * - \ref WWDT_MODULE + * - \ref ACMP01_MODULE + * - \ref I2C0_MODULE + * - \ref I2C1_MODULE + * - \ref I2C2_MODULE + * - \ref QSPI0_MODULE + * - \ref SPI0_MODULE + * - \ref SPI1_MODULE + * - \ref SPI2_MODULE + * - \ref UART0_MODULE + * - \ref UART1_MODULE + * - \ref UART2_MODULE + * - \ref UART3_MODULE + * - \ref UART4_MODULE + * - \ref UART5_MODULE + * - \ref UART6_MODULE + * - \ref UART7_MODULE + * - \ref CAN0_MODULE + * - \ref CAN1_MODULE + * - \ref OTG_MODULE + * - \ref USBD_MODULE + * - \ref EADC_MODULE + * - \ref I2S0_MODULE + * - \ref HSOTG_MODULE + * - \ref SC0_MODULE + * - \ref SC1_MODULE + * - \ref SC2_MODULE + * - \ref QSPI1_MODULE + * - \ref SPI3_MODULE + * - \ref USCI0_MODULE + * - \ref USCI1_MODULE + * - \ref DAC_MODULE + * - \ref CAN2_MODULE + * - \ref EPWM0_MODULE + * - \ref EPWM1_MODULE + * - \ref BPWM0_MODULE + * - \ref BPWM1_MODULE + * - \ref QEI0_MODULE + * - \ref QEI1_MODULE + * - \ref TRNG_MODULE + * - \ref ECAP0_MODULE + * - \ref ECAP1_MODULE + * - \ref CAN2_MODULE + * - \ref OPA_MODULE + * - \ref EADC1_MODULE + * @return None + * @details This function is used to disable module clock. + */ +void CLK_DisableModuleClock(uint32_t u32ModuleIdx) +{ + uint32_t u32tmpVal = 0UL, u32tmpAddr = 0UL; + + u32tmpVal = ~(1UL << MODULE_IP_EN_Pos(u32ModuleIdx)); + u32tmpAddr = (uint32_t)&CLK->AHBCLK; + u32tmpAddr += ((MODULE_APBCLK(u32ModuleIdx) * 4UL)); + + *(uint32_t *)u32tmpAddr &= u32tmpVal; +} + + +/** + * @brief Set PLL frequency + * @param[in] u32PllClkSrc is PLL clock source. Including : + * - \ref CLK_PLLCTL_PLLSRC_HXT + * - \ref CLK_PLLCTL_PLLSRC_HIRC + * @param[in] u32PllFreq is PLL frequency. + * @return PLL frequency + * @details This function is used to configure PLLCTL register to set specified PLL frequency. \n + * The register write-protection function should be disabled before using this function. + */ +uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq) +{ + uint32_t u32PllSrcClk, u32NR, u32NF, u32NO, u32CLK_SRC, u32PllClk; + uint32_t u32Tmp, u32Tmp2, u32Tmp3, u32Min, u32MinNF, u32MinNR, u32MinNO, u32basFreq; + + /* Disable PLL first to avoid unstable when setting PLL */ + CLK_DisablePLL(); + + /* PLL source clock is from HXT */ + if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT) + { + /* Enable HXT clock */ + CLK->PWRCTL |= CLK_PWRCTL_HXTEN_Msk; + + /* Wait for HXT clock ready */ + CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk); + + /* Select PLL source clock from HXT */ + u32CLK_SRC = CLK_PLLCTL_PLLSRC_HXT; + u32PllSrcClk = __HXT; + + /* u32NR start from 2 */ + u32NR = 2UL; + } + + /* PLL source clock is from HIRC */ + else + { + /* Enable HIRC clock */ + CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk; + + /* Wait for HIRC clock ready */ + CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); + + /* Select PLL source clock from HIRC */ + u32CLK_SRC = CLK_PLLCTL_PLLSRC_HIRC; + u32PllSrcClk = __HIRC; + + /* u32NR start from 4 when FIN = 22.1184MHz to avoid calculation overflow */ + u32NR = 4UL; + } + + if((u32PllFreq <= FREQ_500MHZ) && (u32PllFreq >= FREQ_50MHZ)) + { + + /* Find best solution */ + u32Min = (uint32_t) - 1; + u32MinNR = 0UL; + u32MinNF = 0UL; + u32MinNO = 0UL; + u32basFreq = u32PllFreq; + + for(u32NO = 1UL; u32NO <= 4UL; u32NO++) + { + /* Break when get good results */ + if (u32Min == 0UL) + { + break; + } + + if (u32NO != 3UL) + { + + if(u32NO == 4UL) + { + u32PllFreq = u32basFreq << 2; + } + else if(u32NO == 2UL) + { + u32PllFreq = u32basFreq << 1; + } + else + { + } + + for(u32NR = 2UL; u32NR <= 32UL; u32NR++) + { + /* Break when get good results */ + if (u32Min == 0UL) + { + break; + } + + u32Tmp = u32PllSrcClk / u32NR; + if((u32Tmp >= 4000000UL) && (u32Tmp <= 8000000UL)) + { + for(u32NF = 2UL; u32NF <= 513UL; u32NF++) + { + /* u32Tmp2 is shifted 2 bits to avoid overflow */ + u32Tmp2 = (((u32Tmp * 2UL) >> 2) * u32NF); + + if((u32Tmp2 >= FREQ_50MHZ) && (u32Tmp2 <= FREQ_125MHZ)) + { + u32Tmp3 = (u32Tmp2 > (u32PllFreq>>2)) ? u32Tmp2 - (u32PllFreq>>2) : (u32PllFreq>>2) - u32Tmp2; + if(u32Tmp3 < u32Min) + { + u32Min = u32Tmp3; + u32MinNR = u32NR; + u32MinNF = u32NF; + u32MinNO = u32NO; + + /* Break when get good results */ + if(u32Min == 0UL) + { + break; + } + } + } + } + } + } + } + } + + /* Enable and apply new PLL setting. */ + CLK->PLLCTL = u32CLK_SRC | ((u32MinNO - 1UL) << 14) | ((u32MinNR - 1UL) << 9) | (u32MinNF - 2UL); + + /* Wait for PLL clock stable */ + CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk); + + /* Actual PLL output clock frequency */ + u32PllClk = u32PllSrcClk / (u32MinNO * (u32MinNR)) * (u32MinNF) * 2UL; + } + else + { + /* Wrong frequency request. Just return default setting. */ + /* Apply default PLL setting and return */ + if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT) + { + CLK->PLLCTL = CLK_PLLCTL_192MHz_HXT; + } + else + { + CLK->PLLCTL = CLK_PLLCTL_192MHz_HIRC; + } + + /* Wait for PLL clock stable */ + CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk); + + /* Actual PLL output clock frequency */ + u32PllClk = CLK_GetPLLClockFreq(); + } + + return u32PllClk; +} + +/** + * @brief Disable PLL + * @param None + * @return None + * @details This function set PLL in Power-down mode. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_DisablePLL(void) +{ + CLK->PLLCTL |= CLK_PLLCTL_PD_Msk; +} + + +/** + * @brief This function check selected clock source status + * @param[in] u32ClkMask is selected clock source. Including : + * - \ref CLK_STATUS_HXTSTB_Msk + * - \ref CLK_STATUS_LXTSTB_Msk + * - \ref CLK_STATUS_HIRCSTB_Msk + * - \ref CLK_STATUS_LIRCSTB_Msk + * - \ref CLK_STATUS_PLLSTB_Msk + * @retval 0 clock is not stable + * @retval 1 clock is stable + * @details To wait for clock ready by specified clock source stable flag or timeout (~300ms) + */ +uint32_t CLK_WaitClockReady(uint32_t u32ClkMask) +{ + int32_t i32TimeOutCnt = 2160000; + uint32_t u32Ret = 1U; + + while((CLK->STATUS & u32ClkMask) != u32ClkMask) + { + if(i32TimeOutCnt-- <= 0) + { + u32Ret = 0U; + break; + } + } + return u32Ret; +} + +/** + * @brief Enable System Tick counter + * @param[in] u32ClkSrc is System Tick clock source. Including: + * - \ref CLK_CLKSEL0_STCLKSEL_HXT + * - \ref CLK_CLKSEL0_STCLKSEL_LXT + * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2 + * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 + * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 + * - \ref CLK_CLKSEL0_STCLKSEL_HCLK + * @param[in] u32Count is System Tick reload value. It could be 0~0xFFFFFF. + * @return None + * @details This function set System Tick clock source, reload value, enable System Tick counter and interrupt. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count) +{ + /* Set System Tick counter disabled */ + SysTick->CTRL = 0UL; + + /* Set System Tick clock source */ + if( u32ClkSrc == CLK_CLKSEL0_STCLKSEL_HCLK ) + { + SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk; + } + else + { + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc; + } + + /* Set System Tick reload value */ + SysTick->LOAD = u32Count; + + /* Clear System Tick current value and counter flag */ + SysTick->VAL = 0UL; + + /* Set System Tick interrupt enabled and counter enabled */ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; +} + +/** + * @brief Disable System Tick counter + * @param None + * @return None + * @details This function disable System Tick counter. + */ +void CLK_DisableSysTick(void) +{ + /* Set System Tick counter disabled */ + SysTick->CTRL = 0UL; +} + + +/** + * @brief Power-down mode selected + * @param[in] u32PDMode is power down mode index. Including : + * - \ref CLK_PMUCTL_PDMSEL_PD + * - \ref CLK_PMUCTL_PDMSEL_LLPD + * - \ref CLK_PMUCTL_PDMSEL_FWPD + * - \ref CLK_PMUCTL_PDMSEL_SPD0 + * - \ref CLK_PMUCTL_PDMSEL_SPD1 + * - \ref CLK_PMUCTL_PDMSEL_DPD + * @return None + * @details This function is used to set power-down mode. + * @note Must enable LIRC clock before entering to Standby Power-down Mode + */ + +void CLK_SetPowerDownMode(uint32_t u32PDMode) +{ + if ((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x1) // M480LD + { + if(u32PDMode == CLK_PMUCTL_PDMSEL_SPD0) + { + u32PDMode = CLK_PMUCTL_PDMSEL_SPD0; + CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_SRETSEL_Msk)) | CLK_SPDSRETSEL_16K; + } + else if(u32PDMode == CLK_PMUCTL_PDMSEL_SPD1) + { + u32PDMode = CLK_PMUCTL_PDMSEL_SPD0; + CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_SRETSEL_Msk)) | CLK_SPDSRETSEL_NO; + } + } + else + { + /* Enable LIRC clock before entering to Standby Power-down Mode */ + if((u32PDMode == CLK_PMUCTL_PDMSEL_SPD0) || (u32PDMode == CLK_PMUCTL_PDMSEL_SPD1)) + { + /* Enable LIRC clock */ + CLK->PWRCTL |= CLK_PWRCTL_LIRCEN_Msk; + + /* Wait for LIRC clock stable */ + CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk); + } + } + + CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_PDMSEL_Msk)) | u32PDMode; +} + + +/** + * @brief Set Wake-up pin trigger type at Deep Power down mode + * + * @param[in] u32TriggerType + * - \ref CLK_DPDWKPIN_RISING + * - \ref CLK_DPDWKPIN_FALLING + * - \ref CLK_DPDWKPIN_BOTHEDGE + * - \ref CLK_DPDWKPIN1_RISING + * - \ref CLK_DPDWKPIN1_FALLING + * - \ref CLK_DPDWKPIN1_BOTHEDGE + * - \ref CLK_DPDWKPIN2_RISING + * - \ref CLK_DPDWKPIN2_FALLING + * - \ref CLK_DPDWKPIN2_BOTHEDGE + * - \ref CLK_DPDWKPIN3_RISING + * - \ref CLK_DPDWKPIN3_FALLING + * - \ref CLK_DPDWKPIN3_BOTHEDGE + * - \ref CLK_DPDWKPIN4_RISING + * - \ref CLK_DPDWKPIN4_FALLING + * - \ref CLK_DPDWKPIN4_BOTHEDGE + * @return None + * + * @details This function is used to enable Wake-up pin trigger type. + */ + +void CLK_EnableDPDWKPin(uint32_t u32TriggerType) +{ + uint32_t u32Pin1, u32Pin2, u32Pin3, u32Pin4; + + if ((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x1) // M480LD + { + u32Pin1 = (((u32TriggerType) & 0x03UL) >> CLK_PMUCTL_WKPINEN1_Pos); + u32Pin2 = (((u32TriggerType) & 0x03UL) >> CLK_PMUCTL_WKPINEN2_Pos); + u32Pin3 = (((u32TriggerType) & 0x03UL) >> CLK_PMUCTL_WKPINEN3_Pos); + u32Pin4 = (((u32TriggerType) & 0x03UL) >> CLK_PMUCTL_WKPINEN4_Pos); + + if(u32Pin1) + { + CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN1_Msk)) | u32TriggerType; + } + else if(u32Pin2) + { + CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN2_Msk)) | u32TriggerType; + } + else if(u32Pin3) + { + CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN3_Msk)) | u32TriggerType; + } + else if(u32Pin4) + { + CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN4_Msk)) | u32TriggerType; + } + else + { + CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN_Msk)) | u32TriggerType; + } + } + else + { + CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN_Msk)) | u32TriggerType; + } +} + +/** + * @brief Get power manager wake up source + * + * @param[in] None + * @return None + * + * @details This function get power manager wake up source. + */ + +uint32_t CLK_GetPMUWKSrc(void) +{ + return (CLK->PMUSTS); +} + +/** + * @brief Set specified GPIO as wake up source at Stand-by Power down mode + * + * @param[in] u32Port GPIO port. It could be 0~3. + * @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 15. + * @param[in] u32TriggerType + * - \ref CLK_SPDWKPIN_RISING + * - \ref CLK_SPDWKPIN_FALLING + * @param[in] u32DebounceEn + * - \ref CLK_SPDWKPIN_DEBOUNCEEN + * - \ref CLK_SPDWKPIN_DEBOUNCEDIS + * @return None + * + * @details This function is used to set specified GPIO as wake up source + * at Stand-by Power down mode. + */ +void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn) +{ + uint32_t u32tmpAddr = 0UL; + uint32_t u32tmpVal = 0UL; + + /* GPx Stand-by Power-down Wake-up Pin Select */ + u32tmpAddr = (uint32_t)&CLK->PASWKCTL; + u32tmpAddr += (0x4UL * u32Port); + + u32tmpVal = inpw((uint32_t *)u32tmpAddr); + u32tmpVal = (u32tmpVal & ~(CLK_PASWKCTL_WKPSEL_Msk | CLK_PASWKCTL_PRWKEN_Msk | CLK_PASWKCTL_PFWKEN_Msk | CLK_PASWKCTL_DBEN_Msk | CLK_PASWKCTL_WKEN_Msk)) | + (u32Pin << CLK_PASWKCTL_WKPSEL_Pos) | u32TriggerType | u32DebounceEn | CLK_SPDWKPIN_ENABLE; + outpw((uint32_t *)u32tmpAddr, u32tmpVal); +} + +/** + * @brief Get PLL clock frequency + * @param None + * @return PLL frequency + * @details This function get PLL frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetPLLClockFreq(void) +{ + uint32_t u32PllFreq = 0UL, u32PllReg; + uint32_t u32FIN, u32NF, u32NR, u32NO; + uint8_t au8NoTbl[4] = {1U, 2U, 2U, 4U}; + + u32PllReg = CLK->PLLCTL; + + if(u32PllReg & (CLK_PLLCTL_PD_Msk | CLK_PLLCTL_OE_Msk)) + { + u32PllFreq = 0UL; /* PLL is in power down mode or fix low */ + } + else if((u32PllReg & CLK_PLLCTL_BP_Msk) == CLK_PLLCTL_BP_Msk) + { + if((u32PllReg & CLK_PLLCTL_PLLSRC_HIRC) == CLK_PLLCTL_PLLSRC_HIRC) + { + u32FIN = __HIRC; /* PLL source clock from HIRC */ + } + else + { + u32FIN = __HXT; /* PLL source clock from HXT */ + } + + u32PllFreq = u32FIN; + } + else + { + if((u32PllReg & CLK_PLLCTL_PLLSRC_HIRC) == CLK_PLLCTL_PLLSRC_HIRC) + { + u32FIN = __HIRC; /* PLL source clock from HIRC */ + } + else + { + u32FIN = __HXT; /* PLL source clock from HXT */ + } + /* PLL is output enabled in normal work mode */ + u32NO = au8NoTbl[((u32PllReg & CLK_PLLCTL_OUTDIV_Msk) >> CLK_PLLCTL_OUTDIV_Pos)]; + u32NF = ((u32PllReg & CLK_PLLCTL_FBDIV_Msk) >> CLK_PLLCTL_FBDIV_Pos) + 2UL; + u32NR = ((u32PllReg & CLK_PLLCTL_INDIV_Msk) >> CLK_PLLCTL_INDIV_Pos) + 1UL; + + /* u32FIN is shifted 2 bits to avoid overflow */ + u32PllFreq = (((u32FIN >> 2) * u32NF) / (u32NR * u32NO) << 2) * 2UL; + } + + return u32PllFreq; +} + +/** + * @brief Get selected module clock source + * @param[in] u32ModuleIdx is module index. + * - \ref CCAP_MODULE + * - \ref SDH0_MODULE + * - \ref SDH1_MODULE + * - \ref WDT_MODULE + * - \ref UART0_MODULE + * - \ref UART1_MODULE + * - \ref CLKO_MODULE + * - \ref WWDT_MODULE + * - \ref TMR0_MODULE + * - \ref TMR1_MODULE + * - \ref TMR2_MODULE + * - \ref TMR3_MODULE + * - \ref EPWM0_MODULE + * - \ref EPWM1_MODULE + * - \ref BPWM0_MODULE + * - \ref BPWM1_MODULE + * - \ref QSPI0_MODULE + * - \ref QSPI1_MODULE + * - \ref SPI0_MODULE + * - \ref SPI1_MODULE + * - \ref SPI2_MODULE + * - \ref SPI3_MODULE + * - \ref SC0_MODULE + * - \ref SC1_MODULE + * - \ref SC2_MODULE + * - \ref RTC_MODULE + * - \ref I2S0_MODULE + * - \ref UART2_MODULE + * - \ref UART3_MODULE + * - \ref UART4_MODULE + * - \ref UART5_MODULE + * - \ref UART6_MODULE + * - \ref UART7_MODULE + * @return Selected module clock source setting + * @details This function get selected module clock source. + */ +uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx) +{ + uint32_t u32sel = 0; + uint32_t u32SelTbl[4] = {0x0, 0x4, 0x8, 0xC}; + + /* Get clock source selection setting */ + if(u32ModuleIdx == EPWM0_MODULE) + return ((CLK->CLKSEL2 & CLK_CLKSEL2_EPWM0SEL_Msk) >> CLK_CLKSEL2_EPWM0SEL_Pos); + else if(u32ModuleIdx == EPWM1_MODULE) + return ((CLK->CLKSEL2 & CLK_CLKSEL2_EPWM1SEL_Msk) >> CLK_CLKSEL2_EPWM1SEL_Pos); + else if(u32ModuleIdx == BPWM0_MODULE) + return ((CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk) >> CLK_CLKSEL2_BPWM0SEL_Pos); + else if(u32ModuleIdx == BPWM1_MODULE) + return ((CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk) >> CLK_CLKSEL2_BPWM1SEL_Pos); + else if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk) + { + /* Get clock select control register address */ + u32sel = (uint32_t)&CLK->CLKSEL0 + (u32SelTbl[MODULE_CLKSEL(u32ModuleIdx)]); + /* Get clock source selection setting */ + return ((M32(u32sel) & (MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx))) >> MODULE_CLKSEL_Pos(u32ModuleIdx)); + } + else + return 0; +} + +/** + * @brief Get selected module clock divider number + * @param[in] u32ModuleIdx is module index. + * - \ref CCAP_MODULE + * - \ref SDH0_MODULE + * - \ref SDH1_MODULE + * - \ref UART0_MODULE + * - \ref UART1_MODULE + * - \ref UART2_MODULE + * - \ref UART3_MODULE + * - \ref UART4_MODULE + * - \ref UART5_MODULE + * - \ref UART6_MODULE + * - \ref UART7_MODULE + * - \ref SC0_MODULE + * - \ref SC1_MODULE + * - \ref SC2_MODULE + * - \ref I2S0_MODULE + * - \ref EADC_MODULE + * - \ref EADC1_MODULE + * - \ref EMAC_MODULE + * @return Selected module clock divider number setting + * @details This function get selected module clock divider number. + */ +uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx) +{ + uint32_t u32div = 0; + uint32_t u32DivTbl[4] = {0x0, 0x4, 0xc, 0x10}; + + if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk) + { + /* Get clock divider control register address */ + u32div = (uint32_t)&CLK->CLKDIV0 + (u32DivTbl[MODULE_CLKDIV(u32ModuleIdx)]); + if ((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x1) // M480LD + { + if(MODULE_IP_EN_Pos_ENC(u32ModuleIdx) == 31U) //EADC1 + u32div = (uint32_t)&CLK->CLKDIV2; + else if(MODULE_IP_EN_Pos_ENC(u32ModuleIdx) == 29U) //I2S0 + u32div = (uint32_t)&CLK->CLKDIV2; + } + /* Get clock divider number setting */ + return ((M32(u32div) & (MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx))) >> MODULE_CLKDIV_Pos(u32ModuleIdx)); + } + else + return 0; +} + + +/*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CLK_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_crc.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_crc.c new file mode 100644 index 0000000000000000000000000000000000000000..0de1d36577000c2c0639a02621ed2bf12236c2ee --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_crc.c @@ -0,0 +1,95 @@ +/**************************************************************************//** + * @file crc.c + * @version V1.00 + * @brief M480 CRC driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CRC_Driver CRC Driver + @{ +*/ + +/** @addtogroup CRC_EXPORTED_FUNCTIONS CRC Exported Functions + @{ +*/ + +/** + * @brief CRC Open + * + * @param[in] u32Mode CRC operation polynomial mode. Valid values are: + * - \ref CRC_CCITT + * - \ref CRC_8 + * - \ref CRC_16 + * - \ref CRC_32 + * @param[in] u32Attribute CRC operation data attribute. Valid values are combined with: + * - \ref CRC_CHECKSUM_COM + * - \ref CRC_CHECKSUM_RVS + * - \ref CRC_WDATA_COM + * - \ref CRC_WDATA_RVS + * @param[in] u32Seed Seed value. + * @param[in] u32DataLen CPU Write Data Length. Valid values are: + * - \ref CRC_CPU_WDATA_8 + * - \ref CRC_CPU_WDATA_16 + * - \ref CRC_CPU_WDATA_32 + * + * @return None + * + * @details This function will enable the CRC controller by specify CRC operation mode, attribute, initial seed and write data length. \n + * After that, user can start to perform CRC calculate by calling CRC_WRITE_DATA macro or CRC_DAT register directly. + */ +void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen) +{ + CRC->SEED = u32Seed; + CRC->CTL = u32Mode | u32Attribute | u32DataLen | CRC_CTL_CRCEN_Msk; + + /* Setting CHKSINIT bit will reload the initial seed value(CRC_SEED register) to CRC controller */ + CRC->CTL |= CRC_CTL_CHKSINIT_Msk; +} + +/** + * @brief Get CRC Checksum + * + * @param[in] None + * + * @return Checksum Result + * + * @details This macro gets the CRC checksum result by current CRC polynomial mode. + */ +uint32_t CRC_GetChecksum(void) +{ + uint32_t ret; + + switch(CRC->CTL & CRC_CTL_CRCMODE_Msk) + { + case CRC_CCITT: + case CRC_16: + ret = (CRC->CHECKSUM & 0xFFFFU); + break; + case CRC_32: + ret = (CRC->CHECKSUM); + break; + case CRC_8: + ret = (CRC->CHECKSUM & 0xFFU); + break; + default: + ret = 0U; + break; + } + + return ret; +} + +/*@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CRC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_crypto.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_crypto.c new file mode 100644 index 0000000000000000000000000000000000000000..fd4bfe884a9909ecd68632a0b7e7243009d6a1bb --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_crypto.c @@ -0,0 +1,1995 @@ +/**************************************************************************//** + * @file crypto.c + * @version V1.10 + * @brief Cryptographic Accelerator driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include +#include "NuMicro.h" + +/** @cond HIDDEN_SYMBOLS */ + +#define ENABLE_DEBUG 0 + +#if ENABLE_DEBUG +#define CRPT_DBGMSG printf +#else +#define CRPT_DBGMSG(...) do { } while (0) /* disable debug */ +#endif + +/** @endcond HIDDEN_SYMBOLS */ + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CRYPTO_Driver CRYPTO Driver + @{ +*/ + + +/** @addtogroup CRYPTO_EXPORTED_FUNCTIONS CRYPTO Exported Functions + @{ +*/ + +/** @cond HIDDEN_SYMBOLS */ + +static uint32_t g_AES_CTL[4]; +static uint32_t g_TDES_CTL[4]; + +static char hex_char_tbl[] = "0123456789abcdef"; + +static void dump_ecc_reg(char *str, uint32_t volatile regs[], int32_t count); +static char get_Nth_nibble_char(uint32_t val32, uint32_t idx); +static void Hex2Reg(char input[], uint32_t volatile reg[]); +static void Reg2Hex(int32_t count, uint32_t volatile reg[], char output[]); +static void Hex2RegEx(char input[], uint32_t volatile reg[], int shift); +static char ch2hex(char ch); +static int get_nibble_value(char c); + + +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief Open PRNG function + * @param[in] crpt Reference to Crypto module. + * @param[in] u32KeySize is PRNG key size, including: + * - \ref PRNG_KEY_SIZE_64 + * - \ref PRNG_KEY_SIZE_128 + * - \ref PRNG_KEY_SIZE_192 + * - \ref PRNG_KEY_SIZE_256 + * @param[in] u32SeedReload is PRNG seed reload or not, including: + * - \ref PRNG_SEED_CONT + * - \ref PRNG_SEED_RELOAD + * @param[in] u32Seed The new seed. Only valid when u32SeedReload is PRNG_SEED_RELOAD. + * @return None + */ +void PRNG_Open(CRPT_T *crpt, uint32_t u32KeySize, uint32_t u32SeedReload, uint32_t u32Seed) +{ + if (u32SeedReload) + { + crpt->PRNG_SEED = u32Seed; + } + + crpt->PRNG_CTL = (u32KeySize << CRPT_PRNG_CTL_KEYSZ_Pos) | + (u32SeedReload << CRPT_PRNG_CTL_SEEDRLD_Pos); +} + +/** + * @brief Start to generate one PRNG key. + * @param[in] crpt Reference to Crypto module. + * @return None + */ +void PRNG_Start(CRPT_T *crpt) +{ + crpt->PRNG_CTL |= CRPT_PRNG_CTL_START_Msk; +} + +/** + * @brief Read the PRNG key. + * @param[in] crpt Reference to Crypto module. + * @param[out] u32RandKey The key buffer to store newly generated PRNG key. + * @return None + */ +void PRNG_Read(CRPT_T *crpt, uint32_t u32RandKey[]) +{ + uint32_t i, wcnt; + + wcnt = (((crpt->PRNG_CTL & CRPT_PRNG_CTL_KEYSZ_Msk) >> CRPT_PRNG_CTL_KEYSZ_Pos) + 1U) * 2U; + + for (i = 0U; i < wcnt; i++) + { + u32RandKey[i] = crpt->PRNG_KEY[i]; + } + + crpt->PRNG_CTL &= ~CRPT_PRNG_CTL_SEEDRLD_Msk; +} + + +/** + * @brief Open AES encrypt/decrypt function. + * @param[in] crpt Reference to Crypto module. + * @param[in] u32Channel AES channel. Must be 0~3. + * @param[in] u32EncDec 1: AES encode; 0: AES decode + * @param[in] u32OpMode AES operation mode, including: + * - \ref AES_MODE_ECB + * - \ref AES_MODE_CBC + * - \ref AES_MODE_CFB + * - \ref AES_MODE_OFB + * - \ref AES_MODE_CTR + * - \ref AES_MODE_CBC_CS1 + * - \ref AES_MODE_CBC_CS2 + * - \ref AES_MODE_CBC_CS3 + * @param[in] u32KeySize is AES key size, including: + * - \ref AES_KEY_SIZE_128 + * - \ref AES_KEY_SIZE_192 + * - \ref AES_KEY_SIZE_256 + * @param[in] u32SwapType is AES input/output data swap control, including: + * - \ref AES_NO_SWAP + * - \ref AES_OUT_SWAP + * - \ref AES_IN_SWAP + * - \ref AES_IN_OUT_SWAP + * @return None + */ +void AES_Open(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32EncDec, + uint32_t u32OpMode, uint32_t u32KeySize, uint32_t u32SwapType) +{ + crpt->AES_CTL = (u32Channel << CRPT_AES_CTL_CHANNEL_Pos) | + (u32EncDec << CRPT_AES_CTL_ENCRPT_Pos) | + (u32OpMode << CRPT_AES_CTL_OPMODE_Pos) | + (u32KeySize << CRPT_AES_CTL_KEYSZ_Pos) | + (u32SwapType << CRPT_AES_CTL_OUTSWAP_Pos); + g_AES_CTL[u32Channel] = crpt->AES_CTL; +} + +/** + * @brief Start AES encrypt/decrypt + * @param[in] crpt Reference to Crypto module. + * @param[in] u32Channel AES channel. Must be 0~3. + * @param[in] u32DMAMode AES DMA control, including: + * - \ref CRYPTO_DMA_ONE_SHOT One shop AES encrypt/decrypt. + * - \ref CRYPTO_DMA_CONTINUE Continuous AES encrypt/decrypt. + * - \ref CRYPTO_DMA_LAST Last AES encrypt/decrypt of a series of AES_Start. + * @return None + */ +void AES_Start(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32DMAMode) +{ + crpt->AES_CTL = g_AES_CTL[u32Channel]; + crpt->AES_CTL |= CRPT_AES_CTL_START_Msk | (u32DMAMode << CRPT_AES_CTL_DMALAST_Pos); +} + +/** + * @brief Set AES keys + * @param[in] crpt Reference to Crypto module. + * @param[in] u32Channel AES channel. Must be 0~3. + * @param[in] au32Keys An word array contains AES keys. + * @param[in] u32KeySize is AES key size, including: + * - \ref AES_KEY_SIZE_128 + * - \ref AES_KEY_SIZE_192 + * - \ref AES_KEY_SIZE_256 + * @return None + */ +void AES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize) +{ + uint32_t i, wcnt, key_reg_addr; + + key_reg_addr = (uint32_t)&crpt->AES0_KEY[0] + (u32Channel * 0x3CUL); + wcnt = 4UL + u32KeySize*2UL; + + for (i = 0U; i < wcnt; i++) + { + outpw(key_reg_addr, au32Keys[i]); + key_reg_addr += 4UL; + } +} + +/** + * @brief Set AES initial vectors + * @param[in] crpt Reference to Crypto module. + * @param[in] u32Channel AES channel. Must be 0~3. + * @param[in] au32IV A four entry word array contains AES initial vectors. + * @return None + */ +void AES_SetInitVect(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32IV[]) +{ + uint32_t i, key_reg_addr; + + key_reg_addr = (uint32_t)&crpt->AES0_IV[0] + (u32Channel * 0x3CUL); + + for (i = 0U; i < 4U; i++) + { + outpw(key_reg_addr, au32IV[i]); + key_reg_addr += 4UL; + } +} + +/** + * @brief Set AES DMA transfer configuration. + * @param[in] crpt Reference to Crypto module. + * @param[in] u32Channel AES channel. Must be 0~3. + * @param[in] u32SrcAddr AES DMA source address + * @param[in] u32DstAddr AES DMA destination address + * @param[in] u32TransCnt AES DMA transfer byte count + * @return None + */ +void AES_SetDMATransfer(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32SrcAddr, + uint32_t u32DstAddr, uint32_t u32TransCnt) +{ + uint32_t reg_addr; + + reg_addr = (uint32_t)&crpt->AES0_SADDR + (u32Channel * 0x3CUL); + outpw(reg_addr, u32SrcAddr); + + reg_addr = (uint32_t)&crpt->AES0_DADDR + (u32Channel * 0x3CUL); + outpw(reg_addr, u32DstAddr); + + reg_addr = (uint32_t)&crpt->AES0_CNT + (u32Channel * 0x3CUL); + outpw(reg_addr, u32TransCnt); +} + +/** + * @brief Open TDES encrypt/decrypt function. + * @param[in] crpt Reference to Crypto module. + * @param[in] u32Channel TDES channel. Must be 0~3. + * @param[in] u32EncDec 1: TDES encode; 0: TDES decode + * @param[in] Is3DES 1: TDES; 0: DES + * @param[in] Is3Key 1: TDES 3 key mode; 0: TDES 2 key mode + * @param[in] u32OpMode TDES operation mode, including: + * - \ref TDES_MODE_ECB + * - \ref TDES_MODE_CBC + * - \ref TDES_MODE_CFB + * - \ref TDES_MODE_OFB + * - \ref TDES_MODE_CTR + * @param[in] u32SwapType is TDES input/output data swap control and word swap control, including: + * - \ref TDES_NO_SWAP + * - \ref TDES_WHL_SWAP + * - \ref TDES_OUT_SWAP + * - \ref TDES_OUT_WHL_SWAP + * - \ref TDES_IN_SWAP + * - \ref TDES_IN_WHL_SWAP + * - \ref TDES_IN_OUT_SWAP + * - \ref TDES_IN_OUT_WHL_SWAP + * @return None + */ +void TDES_Open(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32EncDec, int32_t Is3DES, int32_t Is3Key, + uint32_t u32OpMode, uint32_t u32SwapType) +{ + g_TDES_CTL[u32Channel] = (u32Channel << CRPT_TDES_CTL_CHANNEL_Pos) | + (u32EncDec << CRPT_TDES_CTL_ENCRPT_Pos) | + u32OpMode | (u32SwapType << CRPT_TDES_CTL_BLKSWAP_Pos); + if (Is3DES) + { + g_TDES_CTL[u32Channel] |= CRPT_TDES_CTL_TMODE_Msk; + } + if (Is3Key) + { + g_TDES_CTL[u32Channel] |= CRPT_TDES_CTL_3KEYS_Msk; + } +} + +/** + * @brief Start TDES encrypt/decrypt + * @param[in] crpt Reference to Crypto module. + * @param[in] u32Channel TDES channel. Must be 0~3. + * @param[in] u32DMAMode TDES DMA control, including: + * - \ref CRYPTO_DMA_ONE_SHOT One shop TDES encrypt/decrypt. + * - \ref CRYPTO_DMA_CONTINUE Continuous TDES encrypt/decrypt. + * - \ref CRYPTO_DMA_LAST Last TDES encrypt/decrypt of a series of TDES_Start. + * @return None + */ +void TDES_Start(CRPT_T *crpt, int32_t u32Channel, uint32_t u32DMAMode) +{ + g_TDES_CTL[u32Channel] |= CRPT_TDES_CTL_START_Msk | (u32DMAMode << CRPT_TDES_CTL_DMALAST_Pos); + crpt->TDES_CTL = g_TDES_CTL[u32Channel]; +} + +/** + * @brief Set TDES keys + * @param[in] crpt Reference to Crypto module. + * @param[in] u32Channel TDES channel. Must be 0~3. + * @param[in] au32Keys The TDES keys. au32Keys[0][0] is Key0 high word and au32Keys[0][1] is key0 low word. + * @return None + */ +void TDES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[3][2]) +{ + uint32_t i, reg_addr; + + reg_addr = (uint32_t)&crpt->TDES0_KEY1H + (0x40UL * u32Channel); + + for (i = 0U; i < 3U; i++) + { + outpw(reg_addr, au32Keys[i][0]); /* TDESn_KEYxH */ + reg_addr += 4UL; + outpw(reg_addr, au32Keys[i][1]); /* TDESn_KEYxL */ + reg_addr += 4UL; + } +} + +/** + * @brief Set TDES initial vectors + * @param[in] crpt Reference to Crypto module. + * @param[in] u32Channel TDES channel. Must be 0~3. + * @param[in] u32IVH TDES initial vector high word. + * @param[in] u32IVL TDES initial vector low word. + * @return None + */ +void TDES_SetInitVect(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32IVH, uint32_t u32IVL) +{ + uint32_t reg_addr; + + reg_addr = (uint32_t)&crpt->TDES0_IVH + (u32Channel * 0x40UL); + outpw(reg_addr, u32IVH); + + reg_addr = (uint32_t)&crpt->TDES0_IVL + (u32Channel * 0x40UL); + outpw(reg_addr, u32IVL); +} + +/** + * @brief Set TDES DMA transfer configuration. + * @param[in] crpt Reference to Crypto module. + * @param[in] u32Channel TDES channel. Must be 0~3. + * @param[in] u32SrcAddr TDES DMA source address + * @param[in] u32DstAddr TDES DMA destination address + * @param[in] u32TransCnt TDES DMA transfer byte count + * @return None + */ +void TDES_SetDMATransfer(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32SrcAddr, + uint32_t u32DstAddr, uint32_t u32TransCnt) +{ + uint32_t reg_addr; + + reg_addr = (uint32_t)&crpt->TDES0_SA + (u32Channel * 0x40UL); + outpw(reg_addr, u32SrcAddr); + + reg_addr = (uint32_t)&crpt->TDES0_DA + (u32Channel * 0x40UL); + outpw(reg_addr, u32DstAddr); + + reg_addr = (uint32_t)&crpt->TDES0_CNT + (u32Channel * 0x40UL); + outpw(reg_addr, u32TransCnt); +} + +/** + * @brief Open SHA encrypt function. + * @param[in] crpt Reference to Crypto module. + * @param[in] u32OpMode SHA operation mode, including: + * - \ref SHA_MODE_SHA1 + * - \ref SHA_MODE_SHA224 + * - \ref SHA_MODE_SHA256 + * - \ref SHA_MODE_SHA384 + * - \ref SHA_MODE_SHA512 + * @param[in] u32SwapType is SHA input/output data swap control, including: + * - \ref SHA_NO_SWAP + * - \ref SHA_OUT_SWAP + * - \ref SHA_IN_SWAP + * - \ref SHA_IN_OUT_SWAP + * @param[in] hmac_key_len HMAC key byte count + * @return None + */ +void SHA_Open(CRPT_T *crpt, uint32_t u32OpMode, uint32_t u32SwapType, uint32_t hmac_key_len) +{ + crpt->HMAC_CTL = (u32OpMode << CRPT_HMAC_CTL_OPMODE_Pos) | + (u32SwapType << CRPT_HMAC_CTL_OUTSWAP_Pos); + + if (hmac_key_len != 0UL) + { + crpt->HMAC_KEYCNT = hmac_key_len; + + if ((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x0) + crpt->HMAC_CTL |= (1<<4); /* M480MD HMACEN is CRYPTO_HMAC_CTL[4] */ + else + crpt->HMAC_CTL |= (1<<11); /* M480LD HMACEN is CRYPTO_HMAC_CTL[11] */ + } +} + +/** + * @brief Start SHA encrypt + * @param[in] crpt Reference to Crypto module. + * @param[in] u32DMAMode TDES DMA control, including: + * - \ref CRYPTO_DMA_ONE_SHOT One shop SHA encrypt. + * - \ref CRYPTO_DMA_CONTINUE Continuous SHA encrypt. + * - \ref CRYPTO_DMA_LAST Last SHA encrypt of a series of SHA_Start. + * @return None + */ +void SHA_Start(CRPT_T *crpt, uint32_t u32DMAMode) +{ + crpt->HMAC_CTL &= ~(0x7UL << CRPT_HMAC_CTL_DMALAST_Pos); + crpt->HMAC_CTL |= CRPT_HMAC_CTL_START_Msk | (u32DMAMode << CRPT_HMAC_CTL_DMALAST_Pos); +} + +/** + * @brief Set SHA DMA transfer + * @param[in] crpt Reference to Crypto module. + * @param[in] u32SrcAddr SHA DMA source address + * @param[in] u32TransCnt SHA DMA transfer byte count + * @return None + */ +void SHA_SetDMATransfer(CRPT_T *crpt, uint32_t u32SrcAddr, uint32_t u32TransCnt) +{ + crpt->HMAC_SADDR = u32SrcAddr; + crpt->HMAC_DMACNT = u32TransCnt; +} + +/** + * @brief Read the SHA digest. + * @param[in] crpt Reference to Crypto module. + * @param[out] u32Digest The SHA encrypt output digest. + * @return None + */ +void SHA_Read(CRPT_T *crpt, uint32_t u32Digest[]) +{ + uint32_t i, wcnt, reg_addr; + + i = (crpt->HMAC_CTL & CRPT_HMAC_CTL_OPMODE_Msk) >> CRPT_HMAC_CTL_OPMODE_Pos; + + if (i == SHA_MODE_SHA1) + { + wcnt = 5UL; + } + else if (i == SHA_MODE_SHA224) + { + wcnt = 7UL; + } + else if (i == SHA_MODE_SHA256) + { + wcnt = 8UL; + } + else if (i == SHA_MODE_SHA384) + { + wcnt = 12UL; + } + else + { + /* SHA_MODE_SHA512 */ + wcnt = 16UL; + } + + reg_addr = (uint32_t)&(crpt->HMAC_DGST[0]); + for (i = 0UL; i < wcnt; i++) + { + u32Digest[i] = inpw(reg_addr); + reg_addr += 4UL; + } +} + +/** @cond HIDDEN_SYMBOLS */ + +/*-----------------------------------------------------------------------------------------------*/ +/* */ +/* ECC */ +/* */ +/*-----------------------------------------------------------------------------------------------*/ + +#define ECCOP_POINT_MUL (0x0UL << CRPT_ECC_CTL_ECCOP_Pos) +#define ECCOP_MODULE (0x1UL << CRPT_ECC_CTL_ECCOP_Pos) +#define ECCOP_POINT_ADD (0x2UL << CRPT_ECC_CTL_ECCOP_Pos) +#define ECCOP_POINT_DOUBLE (0x0UL << CRPT_ECC_CTL_ECCOP_Pos) + +#define MODOP_DIV (0x0UL << CRPT_ECC_CTL_MODOP_Pos) +#define MODOP_MUL (0x1UL << CRPT_ECC_CTL_MODOP_Pos) +#define MODOP_ADD (0x2UL << CRPT_ECC_CTL_MODOP_Pos) +#define MODOP_SUB (0x3UL << CRPT_ECC_CTL_MODOP_Pos) + +enum +{ + CURVE_GF_P, + CURVE_GF_2M, +}; + +/*-----------------------------------------------------*/ +/* Define elliptic curve (EC): */ +/*-----------------------------------------------------*/ + +typedef struct e_curve_t +{ + E_ECC_CURVE curve_id; + int32_t Echar; + char Ea[144]; + char Eb[144]; + char Px[144]; + char Py[144]; + int32_t Epl; + char Pp[176]; + int32_t Eol; + char Eorder[176]; + int32_t key_len; + int32_t irreducible_k1; + int32_t irreducible_k2; + int32_t irreducible_k3; + int32_t GF; +} ECC_CURVE; + +const ECC_CURVE _Curve[] = +{ + { + /* NIST: Curve P-192 : y^2=x^3-ax+b (mod p) */ + CURVE_P_192, + 48, /* Echar */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFC", /* "000000000000000000000000000000000000000000000003" */ + "64210519e59c80e70fa7e9ab72243049feb8deecc146b9b1", + "188da80eb03090f67cbf20eb43a18800f4ff0afd82ff1012", + "07192b95ffc8da78631011ed6b24cdd573f977a11e794811", + 58, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFF", /* "6277101735386680763835789423207666416083908700390324961279" */ + 58, /* Eol */ + "FFFFFFFFFFFFFFFFFFFFFFFF99DEF836146BC9B1B4D22831", /* "6277101735386680763835789423176059013767194773182842284081" */ + 192, /* key_len */ + 7, + 2, + 1, + CURVE_GF_P + }, + { + /* NIST: Curve P-224 : y^2=x^3-ax+b (mod p) */ + CURVE_P_224, + 56, /* Echar */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFE", /* "00000000000000000000000000000000000000000000000000000003" */ + "b4050a850c04b3abf54132565044b0b7d7bfd8ba270b39432355ffb4", + "b70e0cbd6bb4bf7f321390b94a03c1d356c21122343280d6115c1d21", + "bd376388b5f723fb4c22dfe6cd4375a05a07476444d5819985007e34", + 70, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "0026959946667150639794667015087019630673557916260026308143510066298881" */ + 70, /* Eol */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFF16A2E0B8F03E13DD29455C5C2A3D", /* "0026959946667150639794667015087019625940457807714424391721682722368061" */ + 224, /* key_len */ + 9, + 8, + 3, + CURVE_GF_P + }, + { + /* NIST: Curve P-256 : y^2=x^3-ax+b (mod p) */ + CURVE_P_256, + 64, /* Echar */ + "FFFFFFFF00000001000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFC", /* "0000000000000000000000000000000000000000000000000000000000000003" */ + "5ac635d8aa3a93e7b3ebbd55769886bc651d06b0cc53b0f63bce3c3e27d2604b", + "6b17d1f2e12c4247f8bce6e563a440f277037d812deb33a0f4a13945d898c296", + "4fe342e2fe1a7f9b8ee7eb4a7c0f9e162bce33576b315ececbb6406837bf51f5", + 78, /* Epl */ + "FFFFFFFF00000001000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFF", /* "115792089210356248762697446949407573530086143415290314195533631308867097853951" */ + 78, /* Eol */ + "FFFFFFFF00000000FFFFFFFFFFFFFFFFBCE6FAADA7179E84F3B9CAC2FC632551", /* "115792089210356248762697446949407573529996955224135760342422259061068512044369" */ + 256, /* key_len */ + 10, + 5, + 2, + CURVE_GF_P + }, + { + /* NIST: Curve P-384 : y^2=x^3-ax+b (mod p) */ + CURVE_P_384, + 96, /* Echar */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFF0000000000000000FFFFFFFC", /* "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003" */ + "b3312fa7e23ee7e4988e056be3f82d19181d9c6efe8141120314088f5013875ac656398d8a2ed19d2a85c8edd3ec2aef", + "aa87ca22be8b05378eb1c71ef320ad746e1d3b628ba79b9859f741e082542a385502f25dbf55296c3a545e3872760ab7", + "3617de4a96262c6f5d9e98bf9292dc29f8f41dbd289a147ce9da3113b5f0b8c00a60b1ce1d7e819d7a431d7c90ea0e5f", + 116, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFF0000000000000000FFFFFFFF", /* "39402006196394479212279040100143613805079739270465446667948293404245721771496870329047266088258938001861606973112319" */ + 116, /* Eol */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC7634D81F4372DDF581A0DB248B0A77AECEC196ACCC52973", /* "39402006196394479212279040100143613805079739270465446667946905279627659399113263569398956308152294913554433653942643" */ + 384, /* key_len */ + 12, + 3, + 2, + CURVE_GF_P + }, + { + /* NIST: Curve P-521 : y^2=x^3-ax+b (mod p)*/ + CURVE_P_521, + 131, /* Echar */ + "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC", /* "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003" */ + "051953eb9618e1c9a1f929a21a0b68540eea2da725b99b315f3b8b489918ef109e156193951ec7e937b1652c0bd3bb1bf073573df883d2c34f1ef451fd46b503f00", + "0c6858e06b70404e9cd9e3ecb662395b4429c648139053fb521f828af606b4d3dbaa14b5e77efe75928fe1dc127a2ffa8de3348b3c1856a429bf97e7e31c2e5bd66", + "11839296a789a3bc0045c8a5fb42c7d1bd998f54449579b446817afbd17273e662c97ee72995ef42640c550b9013fad0761353c7086a272c24088be94769fd16650", + 157, /* Epl */ + "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", /* "6864797660130609714981900799081393217269435300143305409394463459185543183397656052122559640661454554977296311391480858037121987999716643812574028291115057151" */ + 157, /* Eol */ + "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA51868783BF2F966B7FCC0148F709A5D03BB5C9B8899C47AEBB6FB71E91386409", /* "6864797660130609714981900799081393217269435300143305409394463459185543183397655394245057746333217197532963996371363321113864768612440380340372808892707005449" */ + 521, /* key_len */ + 32, + 32, + 32, + CURVE_GF_P + }, + { + /* NIST: Curve B-163 : y^2+xy=x^3+ax^2+b */ + CURVE_B_163, + 41, /* Echar */ + "00000000000000000000000000000000000000001", + "20a601907b8c953ca1481eb10512f78744a3205fd", + "3f0eba16286a2d57ea0991168d4994637e8343e36", + "0d51fbc6c71a0094fa2cdd545b11c5c0c797324f1", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 49, /* Eol */ + "40000000000000000000292FE77E70C12A4234C33", /* "5846006549323611672814742442876390689256843201587" */ + 163, /* key_len */ + 7, + 6, + 3, + CURVE_GF_2M + }, + { + /* NIST: Curve B-233 : y^2+xy=x^3+ax^2+b */ + CURVE_B_233, + 59, /* Echar 59 */ + "00000000000000000000000000000000000000000000000000000000001", + "066647ede6c332c7f8c0923bb58213b333b20e9ce4281fe115f7d8f90ad", + "0fac9dfcbac8313bb2139f1bb755fef65bc391f8b36f8f8eb7371fd558b", + "1006a08a41903350678e58528bebf8a0beff867a7ca36716f7e01f81052", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 70, /* Eol */ + "1000000000000000000000000000013E974E72F8A6922031D2603CFE0D7", /* "6901746346790563787434755862277025555839812737345013555379383634485463" */ + 233, /* key_len */ + 74, + 74, + 74, + CURVE_GF_2M + }, + { + /* NIST: Curve B-283 : y^2+xy=x^3+ax^2+b */ + CURVE_B_283, + 71, /* Echar */ + "00000000000000000000000000000000000000000000000000000000000000000000001", + "27b680ac8b8596da5a4af8a19a0303fca97fd7645309fa2a581485af6263e313b79a2f5", + "5f939258db7dd90e1934f8c70b0dfec2eed25b8557eac9c80e2e198f8cdbecd86b12053", + "3676854fe24141cb98fe6d4b20d02b4516ff702350eddb0826779c813f0df45be8112f4", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 85, /* Eol */ + "3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEF90399660FC938A90165B042A7CEFADB307", /* "7770675568902916283677847627294075626569625924376904889109196526770044277787378692871" */ + 283, /* key_len */ + 12, + 7, + 5, + CURVE_GF_2M + }, + { + /* NIST: Curve B-409 : y^2+xy=x^3+ax^2+b */ + CURVE_B_409, + 103, /* Echar */ + "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001", + "021a5c2c8ee9feb5c4b9a753b7b476b7fd6422ef1f3dd674761fa99d6ac27c8a9a197b272822f6cd57a55aa4f50ae317b13545f", + "15d4860d088ddb3496b0c6064756260441cde4af1771d4db01ffe5b34e59703dc255a868a1180515603aeab60794e54bb7996a7", + "061b1cfab6be5f32bbfa78324ed106a7636b9c5a7bd198d0158aa4f5488d08f38514f1fdf4b4f40d2181b3681c364ba0273c706", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 123, /* Eol */ + "10000000000000000000000000000000000000000000000000001E2AAD6A612F33307BE5FA47C3C9E052F838164CD37D9A21173", /* "661055968790248598951915308032771039828404682964281219284648798304157774827374805208143723762179110965979867288366567526771" */ + 409, /* key_len */ + 87, + 87, + 87, + CURVE_GF_2M + }, + { + /* NIST: Curve B-571 : y^2+xy=x^3+ax^2+b */ + CURVE_B_571, + 143, /* Echar */ + "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001", + "2f40e7e2221f295de297117b7f3d62f5c6a97ffcb8ceff1cd6ba8ce4a9a18ad84ffabbd8efa59332be7ad6756a66e294afd185a78ff12aa520e4de739baca0c7ffeff7f2955727a", + "303001d34b856296c16c0d40d3cd7750a93d1d2955fa80aa5f40fc8db7b2abdbde53950f4c0d293cdd711a35b67fb1499ae60038614f1394abfa3b4c850d927e1e7769c8eec2d19", + "37bf27342da639b6dccfffeb73d69d78c6c27a6009cbbca1980f8533921e8a684423e43bab08a576291af8f461bb2a8b3531d2f0485c19b16e2f1516e23dd3c1a4827af1b8ac15b", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 172, /* Eol */ + "3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE661CE18FF55987308059B186823851EC7DD9CA1161DE93D5174D66E8382E9BB2FE84E47", /* "3864537523017258344695351890931987344298927329706434998657235251451519142289560424536143999389415773083133881121926944486246872462816813070234528288303332411393191105285703" */ + 571, /* key_len */ + 10, + 5, + 2, + CURVE_GF_2M + }, + { + /* NIST: Curve K-163 : y^2+xy=x^3+ax^2+b */ + CURVE_K_163, + 41, /* Echar */ + "00000000000000000000000000000000000000001", + "00000000000000000000000000000000000000001", + "2fe13c0537bbc11acaa07d793de4e6d5e5c94eee8", + "289070fb05d38ff58321f2e800536d538ccdaa3d9", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 49, /* Eol */ + "4000000000000000000020108A2E0CC0D99F8A5EF", /* "5846006549323611672814741753598448348329118574063" */ + 163, /* key_len */ + 7, + 6, + 3, + CURVE_GF_2M + }, + { + /* NIST: Curve K-233 : y^2+xy=x^3+ax^2+b */ + CURVE_K_233, + 59, /* Echar 59 */ + "00000000000000000000000000000000000000000000000000000000000", + "00000000000000000000000000000000000000000000000000000000001", + "17232ba853a7e731af129f22ff4149563a419c26bf50a4c9d6eefad6126", + "1db537dece819b7f70f555a67c427a8cd9bf18aeb9b56e0c11056fae6a3", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 70, /* Eol */ + "8000000000000000000000000000069D5BB915BCD46EFB1AD5F173ABDF", /* "3450873173395281893717377931138512760570940988862252126328087024741343" */ + 233, /* key_len */ + 74, + 74, + 74, + CURVE_GF_2M + }, + { + /* NIST: Curve K-283 : y^2+xy=x^3+ax^2+b */ + CURVE_K_283, + 71, /* Echar */ + "00000000000000000000000000000000000000000000000000000000000000000000000", + "00000000000000000000000000000000000000000000000000000000000000000000001", + "503213f78ca44883f1a3b8162f188e553cd265f23c1567a16876913b0c2ac2458492836", + "1ccda380f1c9e318d90f95d07e5426fe87e45c0e8184698e45962364e34116177dd2259", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 85, /* Eol */ + "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE9AE2ED07577265DFF7F94451E061E163C61", /* "3885337784451458141838923813647037813284811733793061324295874997529815829704422603873" */ + 283, /* key_len */ + 12, + 7, + 5, + CURVE_GF_2M + }, + { + /* NIST: Curve K-409 : y^2+xy=x^3+ax^2+b */ + CURVE_K_409, + 103, /* Echar */ + "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001", + "060f05f658f49c1ad3ab1890f7184210efd0987e307c84c27accfb8f9f67cc2c460189eb5aaaa62ee222eb1b35540cfe9023746", + "1e369050b7c4e42acba1dacbf04299c3460782f918ea427e6325165e9ea10e3da5f6c42e9c55215aa9ca27a5863ec48d8e0286b", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 123, /* Eol */ + "7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE5F83B2D4EA20400EC4557D5ED3E3E7CA5B4B5C83B8E01E5FCF", /* "330527984395124299475957654016385519914202341482140609642324395022880711289249191050673258457777458014096366590617731358671" */ + 409, /* key_len */ + 87, + 87, + 87, + CURVE_GF_2M + }, + { + /* NIST: Curve K-571 : y^2+xy=x^3+ax^2+b */ + CURVE_K_571, + 143, /* Echar */ + "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001", + "26eb7a859923fbc82189631f8103fe4ac9ca2970012d5d46024804801841ca44370958493b205e647da304db4ceb08cbbd1ba39494776fb988b47174dca88c7e2945283a01c8972", + "349dc807f4fbf374f4aeade3bca95314dd58cec9f307a54ffc61efc006d8a2c9d4979c0ac44aea74fbebbb9f772aedcb620b01a7ba7af1b320430c8591984f601cd4c143ef1c7a3", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 172, /* Eol */ + "20000000000000000000000000000000000000000000000000000000000000000000000131850E1F19A63E4B391A8DB917F4138B630D84BE5D639381E91DEB45CFE778F637C1001", /* "1932268761508629172347675945465993672149463664853217499328617625725759571144780212268133978522706711834706712800825351461273674974066617311929682421617092503555733685276673" */ + 571, /* key_len */ + 10, + 5, + 2, + CURVE_GF_2M + }, + { + /* Koblitz: Curve secp192k1 : y2 = x3+ax+b over Fp */ + CURVE_KO_192, + 48, /* Echar */ + "00000000000000000000000000000000000000000", + "00000000000000000000000000000000000000003", + "DB4FF10EC057E9AE26B07D0280B7F4341DA5D1B1EAE06C7D", + "9B2F2F6D9C5628A7844163D015BE86344082AA88D95E2F9D", + 58, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFEE37", /* p */ + 58, /* Eol */ + "FFFFFFFFFFFFFFFFFFFFFFFE26F2FC170F69466A74DEFD8D", /* n */ + 192, /* key_len */ + 7, + 2, + 1, + CURVE_GF_P + }, + { + /* Koblitz: Curve secp224k1 : y2 = x3+ax+b over Fp */ + CURVE_KO_224, + 56, /* Echar */ + "00000000000000000000000000000000000000000000000000000000", + "00000000000000000000000000000000000000000000000000000005", + "A1455B334DF099DF30FC28A169A467E9E47075A90F7E650EB6B7A45C", + "7E089FED7FBA344282CAFBD6F7E319F7C0B0BD59E2CA4BDB556D61A5", + 70, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFE56D", /* p */ + 70, /* Eol */ + "0000000000000000000000000001DCE8D2EC6184CAF0A971769FB1F7", /* n */ + 224, /* key_len */ + 7, + 2, + 1, + CURVE_GF_P + }, + { + /* Koblitz: Curve secp256k1 : y2 = x3+ax+b over Fp */ + CURVE_KO_256, + 64, /* Echar */ + "0000000000000000000000000000000000000000000000000000000000000000", + "0000000000000000000000000000000000000000000000000000000000000007", + "79BE667EF9DCBBAC55A06295CE870B07029BFCDB2DCE28D959F2815B16F81798", + "483ADA7726A3C4655DA4FBFC0E1108A8FD17B448A68554199C47D08FFB10D4B8", + 78, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFC2F", /* p */ + 78, /* Eol */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEBAAEDCE6AF48A03BBFD25E8CD0364141", /* n */ + 256, /* key_len */ + 7, + 2, + 1, + CURVE_GF_P + }, + { + /* Brainpool: Curve brainpoolP256r1 */ + CURVE_BP_256, + 64, /* Echar */ + "7D5A0975FC2C3057EEF67530417AFFE7FB8055C126DC5C6CE94A4B44F330B5D9", /* A */ + "26DC5C6CE94A4B44F330B5D9BBD77CBF958416295CF7E1CE6BCCDC18FF8C07B6", /* B */ + "8BD2AEB9CB7E57CB2C4B482FFC81B7AFB9DE27E1E3BD23C23A4453BD9ACE3262", /* x */ + "547EF835C3DAC4FD97F8461A14611DC9C27745132DED8E545C1D54C72F046997", /* y */ + 78, /* Epl */ + "A9FB57DBA1EEA9BC3E660A909D838D726E3BF623D52620282013481D1F6E5377", /* p */ + 78, /* Eol */ + "A9FB57DBA1EEA9BC3E660A909D838D718C397AA3B561A6F7901E0E82974856A7", /* q */ + 256, /* key_len */ + 7, + 2, + 1, + CURVE_GF_P + }, + { + /* Brainpool: Curve brainpoolP384r1 */ + CURVE_BP_384, + 96, /* Echar */ + "7BC382C63D8C150C3C72080ACE05AFA0C2BEA28E4FB22787139165EFBA91F90F8AA5814A503AD4EB04A8C7DD22CE2826", /* A */ + "04A8C7DD22CE28268B39B55416F0447C2FB77DE107DCD2A62E880EA53EEB62D57CB4390295DBC9943AB78696FA504C11", /* B */ + "1D1C64F068CF45FFA2A63A81B7C13F6B8847A3E77EF14FE3DB7FCAFE0CBD10E8E826E03436D646AAEF87B2E247D4AF1E", /* x */ + "8ABE1D7520F9C2A45CB1EB8E95CFD55262B70B29FEEC5864E19C054FF99129280E4646217791811142820341263C5315", /* y */ + 116, /* Epl */ + "8CB91E82A3386D280F5D6F7E50E641DF152F7109ED5456B412B1DA197FB71123ACD3A729901D1A71874700133107EC53", /* p */ + 116, /* Eol */ + "8CB91E82A3386D280F5D6F7E50E641DF152F7109ED5456B31F166E6CAC0425A7CF3AB6AF6B7FC3103B883202E9046565", /* q */ + 384, /* key_len */ + 7, + 2, + 1, + CURVE_GF_P + }, + { + /* Brainpool: Curve brainpoolP512r1 */ + CURVE_BP_512, + 128, /* Echar */ + "7830A3318B603B89E2327145AC234CC594CBDD8D3DF91610A83441CAEA9863BC2DED5D5AA8253AA10A2EF1C98B9AC8B57F1117A72BF2C7B9E7C1AC4D77FC94CA", /* A */ + "3DF91610A83441CAEA9863BC2DED5D5AA8253AA10A2EF1C98B9AC8B57F1117A72BF2C7B9E7C1AC4D77FC94CADC083E67984050B75EBAE5DD2809BD638016F723", /* B */ + "81AEE4BDD82ED9645A21322E9C4C6A9385ED9F70B5D916C1B43B62EEF4D0098EFF3B1F78E2D0D48D50D1687B93B97D5F7C6D5047406A5E688B352209BCB9F822", /* x */ + "7DDE385D566332ECC0EABFA9CF7822FDF209F70024A57B1AA000C55B881F8111B2DCDE494A5F485E5BCA4BD88A2763AED1CA2B2FA8F0540678CD1E0F3AD80892", /* y */ + 156, /* Epl */ + "AADD9DB8DBE9C48B3FD4E6AE33C9FC07CB308DB3B3C9D20ED6639CCA703308717D4D9B009BC66842AECDA12AE6A380E62881FF2F2D82C68528AA6056583A48F3", /* p */ + 156, /* Eol */ + "AADD9DB8DBE9C48B3FD4E6AE33C9FC07CB308DB3B3C9D20ED6639CCA70330870553E5C414CA92619418661197FAC10471DB1D381085DDADDB58796829CA90069", /* q */ + 512, /* key_len */ + 7, + 2, + 1, + CURVE_GF_P + }, +}; + +static ECC_CURVE *pCurve; +static ECC_CURVE Curve_Copy; + +static ECC_CURVE * get_curve(E_ECC_CURVE ecc_curve); +static int32_t ecc_init_curve(CRPT_T *crpt, E_ECC_CURVE ecc_curve); +static void run_ecc_codec(CRPT_T *crpt, uint32_t mode); + +static char temp_hex_str[160]; + + +#if ENABLE_DEBUG +static void dump_ecc_reg(char *str, uint32_t volatile regs[], int32_t count) +{ + int32_t i; + + printf("%s => ", str); + for (i = 0; i < count; i++) + { + printf("0x%08x ", regs[i]); + } + printf("\n"); +} +#else +static void dump_ecc_reg(char *str, uint32_t volatile regs[], int32_t count) +{ +} +#endif + +static char ch2hex(char ch) +{ + if (ch <= '9') + { + ch = ch - '0'; + } + else if ((ch <= 'z') && (ch >= 'a')) + { + ch = ch - 'a' + 10U; + } + else + { + ch = ch - 'A' + 10U; + } + return ch; +} + +static void Hex2Reg(char input[], uint32_t volatile reg[]) +{ + char hex; + int si, ri; + uint32_t i, val32; + + si = (int)strlen(input) - 1; + ri = 0; + + while (si >= 0) + { + val32 = 0UL; + for (i = 0UL; (i < 8UL) && (si >= 0); i++) + { + hex = ch2hex(input[si]); + val32 |= (uint32_t)hex << (i * 4UL); + si--; + } + reg[ri++] = val32; + } +} + +static void Hex2RegEx(char input[], uint32_t volatile reg[], int shift) +{ + uint32_t hex, carry; + int si, ri; + uint32_t i, val32; + + si = (int)strlen(input) - 1; + ri = 0L; + carry = 0UL; + while (si >= 0) + { + val32 = 0UL; + for (i = 0UL; (i < 8UL) && (si >= 0L); i++) + { + hex = (uint32_t)ch2hex(input[si]); + hex <<= shift; + + val32 |= (uint32_t)((hex & 0xFUL) | carry) << (i * 4UL); + carry = (hex >> 4UL) & 0xFUL; + si--; + } + reg[ri++] = val32; + } + if (carry != 0UL) + { + reg[ri] = carry; + } +} + +/** + * @brief Extract specified nibble from an unsigned word in character format. + * For example: + * Suppose val32 is 0x786543210, get_Nth_nibble_char(val32, 3) will return a '3'. + * @param[in] val32 The input unsigned word + * @param[in] idx The Nth nibble to be extracted. + * @return The nibble in character format. + */ +static char get_Nth_nibble_char(uint32_t val32, uint32_t idx) +{ + return hex_char_tbl[ (val32 >> (idx * 4U)) & 0xfU ]; +} + + +static void Reg2Hex(int32_t count, uint32_t volatile reg[], char output[]) +{ + int32_t idx, ri; + uint32_t i; + + output[count] = 0U; + idx = count - 1; + + for (ri = 0; idx >= 0; ri++) + { + for (i = 0UL; (i < 8UL) && (idx >= 0); i++) + { + output[idx] = get_Nth_nibble_char(reg[ri], i); + idx--; + } + } +} + +static ECC_CURVE * get_curve(E_ECC_CURVE ecc_curve) +{ + uint32_t i; + ECC_CURVE *ret = NULL; + + for (i = 0UL; i < sizeof(_Curve) / sizeof(ECC_CURVE); i++) + { + if (ecc_curve == _Curve[i].curve_id) + { + memcpy((char *)&Curve_Copy, &_Curve[i], sizeof(ECC_CURVE)); + ret = &Curve_Copy; /* (ECC_CURVE *)&_Curve[i]; */ + } + if (ret != NULL) + { + break; + } + } + return ret; +} + +static int32_t ecc_init_curve(CRPT_T *crpt, E_ECC_CURVE ecc_curve) +{ + int32_t i, ret = 0; + + pCurve = get_curve(ecc_curve); + if (pCurve == NULL) + { + CRPT_DBGMSG("Cannot find curve %d!!\n", ecc_curve); + ret = -1; + } + + if (ret == 0) + { + for (i = 0; i < 18; i++) + { + crpt->ECC_A[i] = 0UL; + crpt->ECC_B[i] = 0UL; + crpt->ECC_X1[i] = 0UL; + crpt->ECC_Y1[i] = 0UL; + crpt->ECC_N[i] = 0UL; + } + + Hex2Reg(pCurve->Ea, crpt->ECC_A); + Hex2Reg(pCurve->Eb, crpt->ECC_B); + Hex2Reg(pCurve->Px, crpt->ECC_X1); + Hex2Reg(pCurve->Py, crpt->ECC_Y1); + + CRPT_DBGMSG("Key length = %d\n", pCurve->key_len); + dump_ecc_reg("CRPT_ECC_CURVE_A", crpt->ECC_A, 10); + dump_ecc_reg("CRPT_ECC_CURVE_B", crpt->ECC_B, 10); + dump_ecc_reg("CRPT_ECC_POINT_X1", crpt->ECC_X1, 10); + dump_ecc_reg("CRPT_ECC_POINT_Y1", crpt->ECC_Y1, 10); + + if (pCurve->GF == (int)CURVE_GF_2M) + { + crpt->ECC_N[0] = 0x1UL; + crpt->ECC_N[(pCurve->key_len) / 32] |= (1UL << ((pCurve->key_len) % 32)); + crpt->ECC_N[(pCurve->irreducible_k1) / 32] |= (1UL << ((pCurve->irreducible_k1) % 32)); + crpt->ECC_N[(pCurve->irreducible_k2) / 32] |= (1UL << ((pCurve->irreducible_k2) % 32)); + crpt->ECC_N[(pCurve->irreducible_k3) / 32] |= (1UL << ((pCurve->irreducible_k3) % 32)); + } + else + { + Hex2Reg(pCurve->Pp, crpt->ECC_N); + } + } + dump_ecc_reg("CRPT_ECC_CURVE_N", crpt->ECC_N, 10); + return ret; +} + +static int get_nibble_value(char c) +{ + if ((c >= '0') && (c <= '9')) + { + c = c - '0'; + } + + if ((c >= 'a') && (c <= 'f')) + { + c = c - 'a' + (char)10; + } + + if ((c >= 'A') && (c <= 'F')) + { + c = c - 'A' + (char)10; + } + return (int)c; +} + +static int ecc_strcmp(char *s1, char *s2) +{ + char c1, c2; + + while (*s1 == '0') s1++; + while (*s2 == '0') s2++; + + for ( ; *s1 || *s2; s1++, s2++) + { + if ((*s1 >= 'A') && (*s1 <= 'Z')) + c1 = *s1 + 32; + else + c1 = *s1; + + if ((*s2 >= 'A') && (*s2 <= 'Z')) + c2 = *s2 + 32; + else + c2 = *s2; + + if (c1 != c2) + return 1; + } + return 0; +} + +volatile uint32_t g_ECC_done, g_ECCERR_done; + +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief ECC interrupt service routine. User application must invoke this function in + * his CRYPTO_IRQHandler() to let Crypto driver know ECC processing was done. + * @param[in] crpt Reference to Crypto module. + * @return none + */ +void ECC_Complete(CRPT_T *crpt) +{ + if (crpt->INTSTS & CRPT_INTSTS_ECCIF_Msk) + { + g_ECC_done = 1UL; + crpt->INTSTS = CRPT_INTSTS_ECCIF_Msk; + /* printf("ECC done IRQ.\n"); */ + } + + if (crpt->INTSTS & CRPT_INTSTS_ECCEIF_Msk) + { + g_ECCERR_done = 1UL; + crpt->INTSTS = CRPT_INTSTS_ECCEIF_Msk; + /* printf("ECCERRIF is set!!\n"); */ + } +} + +/** + * @brief Check if the private key is located in valid range of curve. + * @param[in] crpt Reference to Crypto module. + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[in] private_k The input private key. + * @return 1 Is valid. + * @return 0 Is not valid. + * @return -1 Invalid curve. + */ +int ECC_IsPrivateKeyValid(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char private_k[]) +{ + uint32_t i; + int ret = -1; + + pCurve = get_curve(ecc_curve); + if (pCurve == NULL) + { + ret = -1; + } + + if (strlen(private_k) < strlen(pCurve->Eorder)) + { + ret = 1; + } + + if (strlen(private_k) > strlen(pCurve->Eorder)) + { + ret = 0; + } + + for (i = 0UL; i < strlen(private_k); i++) + { + if (get_nibble_value(private_k[i]) < get_nibble_value(pCurve->Eorder[i])) + { + ret = 1; + break; + } + if (get_nibble_value(private_k[i]) > get_nibble_value(pCurve->Eorder[i])) + { + ret = 0; + break; + } + } + return ret; +} + +/** + * @brief Given a private key and curve to generate the public key pair. + * @param[in] crpt Reference to Crypto module. + * @param[in] private_k The input private key. + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[out] public_k1 The output public key 1. + * @param[out] public_k2 The output public key 2. + * @return 0 Success. + * @return -1 "ecc_curve" value is invalid. + */ +int32_t ECC_GeneratePublicKey(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[]) +{ + int32_t i, ret = 0; + + if (ecc_init_curve(crpt, ecc_curve) != 0) + { + ret = -1; + } + + if (ret == 0) + { + for (i = 0; i < 18; i++) + { + crpt->ECC_K[i] = 0UL; + } + Hex2Reg(private_k, crpt->ECC_K); + + /* set FSEL (Field selection) */ + if (pCurve->GF == (int)CURVE_GF_2M) + { + crpt->ECC_CTL = 0UL; + } + else + { + /* CURVE_GF_P */ + crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk; + } + + g_ECC_done = g_ECCERR_done = 0UL; + crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) | + ECCOP_POINT_MUL | CRPT_ECC_CTL_START_Msk; + + while ((g_ECC_done | g_ECCERR_done) == 0UL) + { + } + + Reg2Hex(pCurve->Echar, crpt->ECC_X1, public_k1); + Reg2Hex(pCurve->Echar, crpt->ECC_Y1, public_k2); + } + + return ret; +} + +/** + * @brief Given a private key and curve to generate the public key pair. + * @param[in] crpt Reference to Crypto module. + * @param[out] x1 The x-coordinate of input point. + * @param[out] y1 The y-coordinate of input point. + * @param[in] k The private key + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[out] x2 The x-coordinate of output point. + * @param[out] y2 The y-coordinate of output point. + * @return 0 Success. + * @return -1 "ecc_curve" value is invalid. + */ +int32_t ECC_Mutiply(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char x1[], char y1[], char *k, char x2[], char y2[]) +{ + int32_t i, ret = 0; + + if (ecc_init_curve(crpt, ecc_curve) != 0) + { + ret = -1; + } + + if (ret == 0) + { + for (i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = 0UL; + crpt->ECC_Y1[i] = 0UL; + crpt->ECC_K[i] = 0UL; + } + Hex2Reg(x1, crpt->ECC_X1); + Hex2Reg(y1, crpt->ECC_Y1); + Hex2Reg(k, crpt->ECC_K); + + /* set FSEL (Field selection) */ + if (pCurve->GF == (int)CURVE_GF_2M) + { + crpt->ECC_CTL = 0UL; + } + else + { + /* CURVE_GF_P */ + crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk; + } + + g_ECC_done = g_ECCERR_done = 0UL; + crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) | + ECCOP_POINT_MUL | CRPT_ECC_CTL_START_Msk; + + while ((g_ECC_done | g_ECCERR_done) == 0UL) + { + } + + Reg2Hex(pCurve->Echar, crpt->ECC_X1, x2); + Reg2Hex(pCurve->Echar, crpt->ECC_Y1, y2); + } + + return ret; +} + +/** + * @brief Given a curve parameter, the other party's public key, and one's own private key to generate the secret Z. + * @param[in] crpt Reference to Crypto module. + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[in] private_k One's own private key. + * @param[in] public_k1 The other party's publick key 1. + * @param[in] public_k2 The other party's publick key 2. + * @param[out] secret_z The ECC CDH secret Z. + * @return 0 Success. + * @return -1 "ecc_curve" value is invalid. + */ +int32_t ECC_GenerateSecretZ(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[], char secret_z[]) +{ + int32_t i, ret = 0; + + if (ecc_init_curve(crpt, ecc_curve) != 0) + { + ret = -1; + } + + if (ret == 0) + { + for (i = 0; i < 18; i++) + { + crpt->ECC_K[i] = 0UL; + crpt->ECC_X1[i] = 0UL; + crpt->ECC_Y1[i] = 0UL; + } + + if ((ecc_curve == CURVE_B_163) || (ecc_curve == CURVE_B_233) || (ecc_curve == CURVE_B_283) || + (ecc_curve == CURVE_B_409) || (ecc_curve == CURVE_B_571) || (ecc_curve == CURVE_K_163)) + { + Hex2RegEx(private_k, crpt->ECC_K, 1); + } + else if ((ecc_curve == CURVE_K_233) || (ecc_curve == CURVE_K_283) || + (ecc_curve == CURVE_K_409) || (ecc_curve == CURVE_K_571)) + { + Hex2RegEx(private_k, crpt->ECC_K, 2); + } + else + { + Hex2Reg(private_k, crpt->ECC_K); + } + + Hex2Reg(public_k1, crpt->ECC_X1); + Hex2Reg(public_k2, crpt->ECC_Y1); + + /* set FSEL (Field selection) */ + if (pCurve->GF == (int)CURVE_GF_2M) + { + crpt->ECC_CTL = 0UL; + } + else + { + /* CURVE_GF_P */ + crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk; + } + g_ECC_done = g_ECCERR_done = 0UL; + crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) | + ECCOP_POINT_MUL | CRPT_ECC_CTL_START_Msk; + + while ((g_ECC_done | g_ECCERR_done) == 0UL) + { + } + + Reg2Hex(pCurve->Echar, crpt->ECC_X1, secret_z); + } + + return ret; +} + +/** @cond HIDDEN_SYMBOLS */ + +static void run_ecc_codec(CRPT_T *crpt, uint32_t mode) +{ + if ((mode & CRPT_ECC_CTL_ECCOP_Msk) == ECCOP_MODULE) + { + crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk; + } + else + { + if (pCurve->GF == (int)CURVE_GF_2M) + { + /* point */ + crpt->ECC_CTL = 0UL; + } + else + { + /* CURVE_GF_P */ + crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk; + } + } + + g_ECC_done = g_ECCERR_done = 0UL; + crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) | mode | CRPT_ECC_CTL_START_Msk; + while ((g_ECC_done | g_ECCERR_done) == 0UL) + { + } + + while (crpt->ECC_STS & CRPT_ECC_STS_BUSY_Msk) + { + } +} +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief ECDSA digital signature generation. + * @param[in] crpt Reference to Crypto module. + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[in] message The hash value of source context. + * @param[in] d The private key. + * @param[in] k The selected random integer. + * @param[out] R R of the (R,S) pair digital signature + * @param[out] S S of the (R,S) pair digital signature + * @return 0 Success. + * @return -1 "ecc_curve" value is invalid. + */ +int32_t ECC_GenerateSignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, + char *d, char *k, char *R, char *S) +{ + uint32_t volatile temp_result1[18], temp_result2[18]; + int32_t i, ret = 0; + + if (ecc_init_curve(crpt, ecc_curve) != 0) + { + ret = -1; + } + + if (ret == 0) + { + /* + * 1. Calculate e = HASH(m), where HASH is a cryptographic hashing algorithm, (i.e. SHA-1) + * (1) Use SHA to calculate e + */ + + /* 2. Select a random integer k form [1, n-1] + * (1) Notice that n is order, not prime modulus or irreducible polynomial function + */ + + /* + * 3. Compute r = x1 (mod n), where (x1, y1) = k * G. If r = 0, go to step 2 + * (1) Write the curve parameter A, B, and curve length M to corresponding registers + * (2) Write the prime modulus or irreducible polynomial function to N registers according + * (3) Write the point G(x, y) to X1, Y1 registers + * (4) Write the random integer k to K register + * (5) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00 + * (6) Set FSEL(CRPT_ECC_CTL[8]) according to used curve of prime field or binary field + * (7) Set START(CRPT_ECC_CTL[0]) to 1 + * (8) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (9) Write the curve order and curve length to N ,M registers according + * (10) Write 0x0 to Y1 registers + * (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (12) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10 + * (13) Set START(CRPT_ECC_CTL[0]) to 1 * + * (14) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (15) Read X1 registers to get r + */ + + /* 3-(4) Write the random integer k to K register */ + for (i = 0; i < 18; i++) + { + crpt->ECC_K[i] = 0UL; + } + Hex2Reg(k, crpt->ECC_K); + + run_ecc_codec(crpt, ECCOP_POINT_MUL); + + /* 3-(9) Write the curve order to N registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 3-(10) Write 0x0 to Y1 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = 0UL; + } + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_ADD); + + /* 3-(15) Read X1 registers to get r */ + for (i = 0; i < 18; i++) + { + temp_result1[i] = crpt->ECC_X1[i]; + } + + Reg2Hex(pCurve->Echar, temp_result1, R); + + /* + * 4. Compute s = k ? 1 (e + d r)(mod n). If s = 0, go to step 2 + * (1) Write the curve order to N registers according + * (2) Write 0x1 to Y1 registers + * (3) Write the random integer k to X1 registers according + * (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (5) Set MOPOP(CRPT_ECC_CTL[12:11]) to 00 + * (6) Set START(CRPT_ECC_CTL[0]) to 1 + * (7) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (8) Read X1 registers to get k^-1 + * (9) Write the curve order and curve length to N ,M registers + * (10) Write r, d to X1, Y1 registers + * (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (12) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01 + * (13) Set START(CRPT_ECC_CTL[0]) to 1 + * (14) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (15) Write the curve order to N registers + * (16) Write e to Y1 registers + * (17) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (18) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10 + * (19) Set START(CRPT_ECC_CTL[0]) to 1 + * (20) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (21) Write the curve order and curve length to N ,M registers + * (22) Write k^-1 to Y1 registers + * (23) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (24) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01 + * (25) Set START(CRPT_ECC_CTL[0]) to 1 + * (26) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (27) Read X1 registers to get s + */ + + /* S/W: GFp_add_mod_order(pCurve->key_len+2, 0, x1, a, R); */ + + /* 4-(1) Write the curve order to N registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(2) Write 0x1 to Y1 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = 0UL; + } + crpt->ECC_Y1[0] = 0x1UL; + + /* 4-(3) Write the random integer k to X1 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = 0UL; + } + Hex2Reg(k, crpt->ECC_X1); + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_DIV); + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str); + CRPT_DBGMSG("(7) output = %s\n", temp_hex_str); +#endif + + /* 4-(8) Read X1 registers to get k^-1 */ + + for (i = 0; i < 18; i++) + { + temp_result2[i] = crpt->ECC_X1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str); + CRPT_DBGMSG("k^-1 = %s\n", temp_hex_str); +#endif + + /* 4-(9) Write the curve order and curve length to N ,M registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(10) Write r, d to X1, Y1 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = temp_result1[i]; + } + + for (i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = 0UL; + } + Hex2Reg(d, crpt->ECC_Y1); + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL); + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str); + CRPT_DBGMSG("(14) output = %s\n", temp_hex_str); +#endif + + /* 4-(15) Write the curve order to N registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(16) Write e to Y1 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = 0UL; + } + Hex2Reg(message, crpt->ECC_Y1); + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_ADD); + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str); + CRPT_DBGMSG("(20) output = %s\n", temp_hex_str); +#endif + + /* 4-(21) Write the curve order and curve length to N ,M registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(22) Write k^-1 to Y1 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = temp_result2[i]; + } + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL); + + /* 4-(27) Read X1 registers to get s */ + for (i = 0; i < 18; i++) + { + temp_result2[i] = crpt->ECC_X1[i]; + } + + Reg2Hex(pCurve->Echar, temp_result2, S); + + } /* ret == 0 */ + + return ret; +} + +/** + * @brief ECDSA dogotal signature verification. + * @param[in] crpt Reference to Crypto module. + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[in] message The hash value of source context. + * @param[in] public_k1 The public key 1. + * @param[in] public_k2 The public key 2. + * @param[in] R R of the (R,S) pair digital signature + * @param[in] S S of the (R,S) pair digital signature + * @return 0 Success. + * @return -1 "ecc_curve" value is invalid. + * @return -2 Verification failed. + */ +int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, + char *public_k1, char *public_k2, char *R, char *S) +{ + uint32_t temp_result1[18], temp_result2[18]; + uint32_t temp_x[18], temp_y[18]; + int32_t i, ret = 0; + + /* + * 1. Verify that r and s are integers in the interval [1, n-1]. If not, the signature is invalid + * 2. Compute e = HASH (m), where HASH is the hashing algorithm in signature generation + * (1) Use SHA to calculate e + */ + + /* + * 3. Compute w = s^-1 (mod n) + * (1) Write the curve order to N registers + * (2) Write 0x1 to Y1 registers + * (3) Write s to X1 registers + * (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (5) Set MOPOP(CRPT_ECC_CTL[12:11]) to 00 + * (6) Set FSEL(CRPT_ECC_CTL[8]) according to used curve of prime field or binary field + * (7) Set START(CRPT_ECC_CTL[0]) to 1 + * (8) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (9) Read X1 registers to get w + */ + + if (ecc_init_curve(crpt, ecc_curve) != 0) + { + ret = -1; + } + + if (ret == 0) + { + /* 3-(1) Write the curve order to N registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 3-(2) Write 0x1 to Y1 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = 0UL; + } + crpt->ECC_Y1[0] = 0x1UL; + + /* 3-(3) Write s to X1 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = 0UL; + } + Hex2Reg(S, crpt->ECC_X1); + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_DIV); + + /* 3-(9) Read X1 registers to get w */ + for (i = 0; i < 18; i++) + { + temp_result2[i] = crpt->ECC_X1[i]; + } + +#if ENABLE_DEBUG + CRPT_DBGMSG("e = %s\n", message); + Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str); + CRPT_DBGMSG("w = %s\n", temp_hex_str); + CRPT_DBGMSG("o = %s (order)\n", pCurve->Eorder); +#endif + + /* + * 4. Compute u1 = e w (mod n) and u2 = r w (mod n) + * (1) Write the curve order and curve length to N ,M registers + * (2) Write e, w to X1, Y1 registers + * (3) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (4) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01 + * (5) Set START(CRPT_ECC_CTL[0]) to 1 + * (6) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (7) Read X1 registers to get u1 + * (8) Write the curve order and curve length to N ,M registers + * (9) Write r, w to X1, Y1 registers + * (10) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (11) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01 + * (12) Set START(CRPT_ECC_CTL[0]) to 1 + * (13) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (14) Read X1 registers to get u2 + */ + + /* 4-(1) Write the curve order and curve length to N ,M registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(2) Write e, w to X1, Y1 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = 0UL; + } + Hex2Reg(message, crpt->ECC_X1); + + for (i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = temp_result2[i]; + } + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL); + + /* 4-(7) Read X1 registers to get u1 */ + for (i = 0; i < 18; i++) + { + temp_result1[i] = crpt->ECC_X1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_result1, temp_hex_str); + CRPT_DBGMSG("u1 = %s\n", temp_hex_str); +#endif + + /* 4-(8) Write the curve order and curve length to N ,M registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(9) Write r, w to X1, Y1 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = 0UL; + } + Hex2Reg(R, crpt->ECC_X1); + + for (i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = temp_result2[i]; + } + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL); + + /* 4-(14) Read X1 registers to get u2 */ + for (i = 0; i < 18; i++) + { + temp_result2[i] = crpt->ECC_X1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str); + CRPT_DBGMSG("u2 = %s\n", temp_hex_str); +#endif + + /* + * 5. Compute X (x1, y1) = u1 * G + u2 * Q + * (1) Write the curve parameter A, B, N, and curve length M to corresponding registers + * (2) Write the point G(x, y) to X1, Y1 registers + * (3) Write u1 to K registers + * (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00 + * (5) Set START(CRPT_ECC_CTL[0]) to 1 + * (6) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (7) Read X1, Y1 registers to get u1*G + * (8) Write the curve parameter A, B, N, and curve length M to corresponding registers + * (9) Write the public key Q(x,y) to X1, Y1 registers + * (10) Write u2 to K registers + * (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00 + * (12) Set START(CRPT_ECC_CTL[0]) to 1 + * (13) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (14) Write the curve parameter A, B, N, and curve length M to corresponding registers + * (15) Write the result data u1*G to X2, Y2 registers + * (16) Set ECCOP(CRPT_ECC_CTL[10:9]) to 10 + * (17) Set START(CRPT_ECC_CTL[0]) to 1 + * (18) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (19) Read X1, Y1 registers to get X(x1, y1) + * (20) Write the curve order and curve length to N ,M registers + * (21) Write x1 to X1 registers + * (22) Write 0x0 to Y1 registers + * (23) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (24) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10 + * (25) Set START(CRPT_ECC_CTL[0]) to 1 + * (26) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (27) Read X1 registers to get x1 (mod n) + * + * 6. The signature is valid if x1 = r, otherwise it is invalid + */ + + /* + * (1) Write the curve parameter A, B, N, and curve length M to corresponding registers + * (2) Write the point G(x, y) to X1, Y1 registers + */ + ecc_init_curve(crpt, ecc_curve); + + /* (3) Write u1 to K registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_K[i] = temp_result1[i]; + } + + run_ecc_codec(crpt, ECCOP_POINT_MUL); + + /* (7) Read X1, Y1 registers to get u1*G */ + for (i = 0; i < 18; i++) + { + temp_x[i] = crpt->ECC_X1[i]; + temp_y[i] = crpt->ECC_Y1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_x, temp_hex_str); + CRPT_DBGMSG("5-(7) u1*G, x = %s\n", temp_hex_str); + Reg2Hex(pCurve->Echar, temp_y, temp_hex_str); + CRPT_DBGMSG("5-(7) u1*G, y = %s\n", temp_hex_str); +#endif + + /* (8) Write the curve parameter A, B, N, and curve length M to corresponding registers */ + ecc_init_curve(crpt, ecc_curve); + + /* (9) Write the public key Q(x,y) to X1, Y1 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = 0UL; + crpt->ECC_Y1[i] = 0UL; + } + + Hex2Reg(public_k1, crpt->ECC_X1); + Hex2Reg(public_k2, crpt->ECC_Y1); + + /* (10) Write u2 to K registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_K[i] = temp_result2[i]; + } + + run_ecc_codec(crpt, ECCOP_POINT_MUL); + + for (i = 0; i < 18; i++) + { + temp_result1[i] = crpt->ECC_X1[i]; + temp_result2[i] = crpt->ECC_Y1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_result1, temp_hex_str); + CRPT_DBGMSG("5-(13) u2*Q, x = %s\n", temp_hex_str); + Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str); + CRPT_DBGMSG("5-(13) u2*Q, y = %s\n", temp_hex_str); +#endif + + /* (14) Write the curve parameter A, B, N, and curve length M to corresponding registers */ + ecc_init_curve(crpt, ecc_curve); + + /* Write the result data u2*Q to X1, Y1 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = temp_result1[i]; + crpt->ECC_Y1[i] = temp_result2[i]; + } + + /* (15) Write the result data u1*G to X2, Y2 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_X2[i] = temp_x[i]; + crpt->ECC_Y2[i] = temp_y[i]; + } + + run_ecc_codec(crpt, ECCOP_POINT_ADD); + + /* (19) Read X1, Y1 registers to get X(x1, y1) */ + for (i = 0; i < 18; i++) + { + temp_x[i] = crpt->ECC_X1[i]; + temp_y[i] = crpt->ECC_Y1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_x, temp_hex_str); + CRPT_DBGMSG("5-(19) x' = %s\n", temp_hex_str); + Reg2Hex(pCurve->Echar, temp_y, temp_hex_str); + CRPT_DBGMSG("5-(19) y' = %s\n", temp_hex_str); +#endif + + /* (20) Write the curve order and curve length to N ,M registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* + * (21) Write x1 to X1 registers + * (22) Write 0x0 to Y1 registers + */ + for (i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = temp_x[i]; + crpt->ECC_Y1[i] = 0UL; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str); + CRPT_DBGMSG("5-(21) x' = %s\n", temp_hex_str); + Reg2Hex(pCurve->Echar, crpt->ECC_Y1, temp_hex_str); + CRPT_DBGMSG("5-(22) y' = %s\n", temp_hex_str); +#endif + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_ADD); + + /* (27) Read X1 registers to get x1 (mod n) */ + Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str); + CRPT_DBGMSG("5-(27) x1' (mod n) = %s\n", temp_hex_str); + + /* 6. The signature is valid if x1 = r, otherwise it is invalid */ + + /* Compare with test pattern to check if r is correct or not */ + if (ecc_strcmp(temp_hex_str, R) != 0) + { + CRPT_DBGMSG("x1' (mod n) != R Test filed!!\n"); + CRPT_DBGMSG("Signature R [%s] is not matched with expected R [%s]!\n", temp_hex_str, R); + ret = -2; + } + } /* ret == 0 */ + + return ret; +} + +/*@}*/ /* end of group CRYPTO_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CRYPTO_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ + diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_dac.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_dac.c new file mode 100644 index 0000000000000000000000000000000000000000..1ed45773952a8aef8e043bf828456c898fa10d43 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_dac.c @@ -0,0 +1,90 @@ +/**************************************************************************//** + * @file dac.c + * @version V1.00 + * @brief M480 series DAC driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup DAC_Driver DAC Driver + @{ +*/ + +/** @addtogroup DAC_EXPORTED_FUNCTIONS DAC Exported Functions + @{ +*/ + +/** + * @brief This function make DAC module be ready to convert. + * @param[in] dac Base address of DAC module. + * @param[in] u32Ch Not used in M480 DAC. + * @param[in] u32TrgSrc Decides the trigger source. Valid values are: + * - \ref DAC_WRITE_DAT_TRIGGER :Write DAC_DAT trigger + * - \ref DAC_SOFTWARE_TRIGGER :Software trigger + * - \ref DAC_LOW_LEVEL_TRIGGER :STDAC pin low level trigger + * - \ref DAC_HIGH_LEVEL_TRIGGER :STDAC pin high level trigger + * - \ref DAC_FALLING_EDGE_TRIGGER :STDAC pin falling edge trigger + * - \ref DAC_RISING_EDGE_TRIGGER :STDAC pin rising edge trigger + * - \ref DAC_TIMER0_TRIGGER :Timer 0 trigger + * - \ref DAC_TIMER1_TRIGGER :Timer 1 trigger + * - \ref DAC_TIMER2_TRIGGER :Timer 2 trigger + * - \ref DAC_TIMER3_TRIGGER :Timer 3 trigger + * - \ref DAC_EPWM0_TRIGGER :EPWM0 trigger + * - \ref DAC_EPWM1_TRIGGER :EPWM1 trigger + * @return None + * @details The DAC conversion can be started by writing DAC_DAT, software trigger or hardware trigger. + * When TRGEN (DAC_CTL[4]) is 0, the data conversion is started by writing DAC_DAT register. + * When TRGEN (DAC_CTL[4]) is 1, the data conversion is started by SWTRG (DAC_SWTRG[0]) is set to 1, + * external STDAC pin, timer event, or EPWM event. + */ +void DAC_Open(DAC_T *dac, + uint32_t u32Ch, + uint32_t u32TrgSrc) +{ + dac->CTL &= ~(DAC_CTL_ETRGSEL_Msk | DAC_CTL_TRGSEL_Msk | DAC_CTL_TRGEN_Msk); + dac->CTL |= (u32TrgSrc | DAC_CTL_DACEN_Msk); +} + +/** + * @brief Disable DAC analog power. + * @param[in] dac Base address of DAC module. + * @param[in] u32Ch Not used in M480 DAC. + * @return None + * @details Disable DAC analog power for saving power consumption. + */ +void DAC_Close(DAC_T *dac, uint32_t u32Ch) +{ + dac->CTL &= (~DAC_CTL_DACEN_Msk); +} + +/** + * @brief Set delay time for DAC to become stable. + * @param[in] dac Base address of DAC module. + * @param[in] u32Delay Decides the DAC conversion settling time, the range is from 0~(1023/PCLK1*1000000) micro seconds. + * @return Real DAC conversion settling time (micro second). + * @details For example, DAC controller clock speed is 160MHz and DAC conversion setting time is 1 us, SETTLET (DAC_TCTL[9:0]) value must be greater than 0xA0. + * @note User needs to write appropriate value to meet DAC conversion settling time base on PCLK (APB clock) speed. + */ +uint32_t DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay) +{ + + dac->TCTL = ((CLK_GetPCLK1Freq() * u32Delay / 1000000UL) & 0x3FFUL); + + return ((dac->TCTL) * 1000000UL / CLK_GetPCLK1Freq()); +} + + + +/*@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group DAC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_eadc.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_eadc.c new file mode 100644 index 0000000000000000000000000000000000000000..f7ef09d97ba9a9632450984df05e860261a40334 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_eadc.c @@ -0,0 +1,143 @@ +/**************************************************************************//** + * @file eadc.c + * @version V2.00 + * @brief M480 series EADC driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EADC_Driver EADC Driver + @{ +*/ + +/** @addtogroup EADC_EXPORTED_FUNCTIONS EADC Exported Functions + @{ +*/ + +/** + * @brief This function make EADC_module be ready to convert. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32InputMode Decides the input mode. + * - \ref EADC_CTL_DIFFEN_SINGLE_END :Single end input mode. + * - \ref EADC_CTL_DIFFEN_DIFFERENTIAL :Differential input type. + * @return None + * @details This function is used to set analog input mode and enable A/D Converter. + * Before starting A/D conversion function, ADCEN bit (EADC_CTL[0]) should be set to 1. + * @note + */ +void EADC_Open(EADC_T *eadc, uint32_t u32InputMode) +{ + eadc->CTL &= (~EADC_CTL_DIFFEN_Msk); + + eadc->CTL |= (u32InputMode | EADC_CTL_ADCEN_Msk); + while (!(eadc->PWRM & EADC_PWRM_PWUPRDY_Msk)) {} +} + +/** + * @brief Disable EADC_module. + * @param[in] eadc The pointer of the specified EADC module.. + * @return None + * @details Clear ADCEN bit (EADC_CTL[0]) to disable A/D converter analog circuit power consumption. + */ +void EADC_Close(EADC_T *eadc) +{ + eadc->CTL &= ~EADC_CTL_ADCEN_Msk; +} + +/** + * @brief Configure the sample control logic module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @param[in] u32TriggerSrc Decides the trigger source. Valid values are: + * - \ref EADC_SOFTWARE_TRIGGER : Disable trigger + * - \ref EADC_FALLING_EDGE_TRIGGER : STADC pin falling edge trigger + * - \ref EADC_RISING_EDGE_TRIGGER : STADC pin rising edge trigger + * - \ref EADC_FALLING_RISING_EDGE_TRIGGER : STADC pin both falling and rising edge trigger + * - \ref EADC_ADINT0_TRIGGER : EADC ADINT0 interrupt EOC pulse trigger + * - \ref EADC_ADINT1_TRIGGER : EADC ADINT1 interrupt EOC pulse trigger + * - \ref EADC_TIMER0_TRIGGER : Timer0 overflow pulse trigger + * - \ref EADC_TIMER1_TRIGGER : Timer1 overflow pulse trigger + * - \ref EADC_TIMER2_TRIGGER : Timer2 overflow pulse trigger + * - \ref EADC_TIMER3_TRIGGER : Timer3 overflow pulse trigger + * - \ref EADC_EPWM0TG0_TRIGGER : EPWM0TG0 trigger + * - \ref EADC_EPWM0TG1_TRIGGER : EPWM0TG1 trigger + * - \ref EADC_EPWM0TG2_TRIGGER : EPWM0TG2 trigger + * - \ref EADC_EPWM0TG3_TRIGGER : EPWM0TG3 trigger + * - \ref EADC_EPWM0TG4_TRIGGER : EPWM0TG4 trigger + * - \ref EADC_EPWM0TG5_TRIGGER : EPWM0TG5 trigger + * - \ref EADC_EPWM1TG0_TRIGGER : EPWM1TG0 trigger + * - \ref EADC_EPWM1TG1_TRIGGER : EPWM1TG1 trigger + * - \ref EADC_EPWM1TG2_TRIGGER : EPWM1TG2 trigger + * - \ref EADC_EPWM1TG3_TRIGGER : EPWM1TG3 trigger + * - \ref EADC_EPWM1TG4_TRIGGER : EPWM1TG4 trigger + * - \ref EADC_EPWM1TG5_TRIGGER : EPWM1TG5 trigger + * - \ref EADC_BPWM0TG_TRIGGER : BPWM0TG trigger + * - \ref EADC_BPWM1TG_TRIGGER : BPWM1TG trigger + * @param[in] u32Channel Specifies the sample module channel, valid value are from 0 to 15. + * @return None + * @details Each of ADC control logic modules 0~15 which is configurable for ADC converter channel EADC_CH0~15 and trigger source. + * sample module 16~18 is fixed for ADC channel 16, 17, 18 input sources as band-gap voltage, temperature sensor, and battery power (VBAT). + */ +void EADC_ConfigSampleModule(EADC_T *eadc, \ + uint32_t u32ModuleNum, \ + uint32_t u32TriggerSrc, \ + uint32_t u32Channel) +{ + eadc->SCTL[u32ModuleNum] &= ~(EADC_SCTL_EXTFEN_Msk | EADC_SCTL_EXTREN_Msk | EADC_SCTL_TRGSEL_Msk | EADC_SCTL_CHSEL_Msk); + eadc->SCTL[u32ModuleNum] |= (u32TriggerSrc | u32Channel); +} + + +/** + * @brief Set trigger delay time. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @param[in] u32TriggerDelayTime Decides the trigger delay time, valid range are between 0~0xFF. + * @param[in] u32DelayClockDivider Decides the trigger delay clock divider. Valid values are: + * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_1 : Trigger delay clock frequency is ADC_CLK/1 + * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_2 : Trigger delay clock frequency is ADC_CLK/2 + * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_4 : Trigger delay clock frequency is ADC_CLK/4 + * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_16 : Trigger delay clock frequency is ADC_CLK/16 + * @return None + * @details User can configure the trigger delay time by setting TRGDLYCNT (EADC_SCTLn[15:8], n=0~15) and TRGDLYDIV (EADC_SCTLn[7:6], n=0~15). + * Trigger delay time = (u32TriggerDelayTime) x Trigger delay clock period. + */ +void EADC_SetTriggerDelayTime(EADC_T *eadc, \ + uint32_t u32ModuleNum, \ + uint32_t u32TriggerDelayTime, \ + uint32_t u32DelayClockDivider) +{ + eadc->SCTL[u32ModuleNum] &= ~(EADC_SCTL_TRGDLYDIV_Msk | EADC_SCTL_TRGDLYCNT_Msk); + eadc->SCTL[u32ModuleNum] |= ((u32TriggerDelayTime << EADC_SCTL_TRGDLYCNT_Pos) | u32DelayClockDivider); +} + +/** + * @brief Set ADC extend sample time. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18. + * @param[in] u32ExtendSampleTime Decides the extend sampling time, the range is from 0~255 ADC clock. Valid value are from 0 to 0xFF. + * @return None + * @details When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, + * user can extend A/D sampling time after trigger source is coming to get enough sampling time. + */ +void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime) +{ + eadc->SCTL[u32ModuleNum] &= ~EADC_SCTL_EXTSMPT_Msk; + + eadc->SCTL[u32ModuleNum] |= (u32ExtendSampleTime << EADC_SCTL_EXTSMPT_Pos); + +} + +/*@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EADC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_ebi.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_ebi.c new file mode 100644 index 0000000000000000000000000000000000000000..2a2bd28de6e2734531f39afb3df03d815958a632 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_ebi.c @@ -0,0 +1,195 @@ +/**************************************************************************//** + * @file ebi.c + * @version V3.00 + * @brief M480 series External Bus Interface(EBI) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EBI_Driver EBI Driver + @{ +*/ + + +/** @addtogroup EBI_EXPORTED_FUNCTIONS EBI Exported Functions + @{ +*/ + +/** + * @brief Initialize EBI for specify Bank + * + * @param[in] u32Bank Bank number for EBI. Valid values are: + * - \ref EBI_BANK0 + * - \ref EBI_BANK1 + * - \ref EBI_BANK2 + * @param[in] u32DataWidth Data bus width. Valid values are: + * - \ref EBI_BUSWIDTH_8BIT + * - \ref EBI_BUSWIDTH_16BIT + * @param[in] u32TimingClass Default timing configuration. Valid values are: + * - \ref EBI_TIMING_FASTEST + * - \ref EBI_TIMING_VERYFAST + * - \ref EBI_TIMING_FAST + * - \ref EBI_TIMING_NORMAL + * - \ref EBI_TIMING_SLOW + * - \ref EBI_TIMING_VERYSLOW + * - \ref EBI_TIMING_SLOWEST + * @param[in] u32BusMode Set EBI bus operate mode. Valid values are: + * - \ref EBI_OPMODE_NORMAL + * - \ref EBI_OPMODE_CACCESS + * - \ref EBI_OPMODE_ADSEPARATE + * @param[in] u32CSActiveLevel CS is active High/Low. Valid values are: + * - \ref EBI_CS_ACTIVE_HIGH + * - \ref EBI_CS_ACTIVE_LOW + * + * @return None + * + * @details This function is used to open specify EBI bank with different bus width, timing setting and \n + * active level of CS pin to access EBI device. + * @note Write Buffer Enable(WBUFEN) and Extend Time Of ALE(TALE) are only available in EBI bank0 control register. + */ +void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel) +{ + uint32_t u32Index0 = (uint32_t)&EBI->CTL0 + (uint32_t)u32Bank * 0x10U; + uint32_t u32Index1 = (uint32_t)&EBI->TCTL0 + (uint32_t)u32Bank * 0x10U; + volatile uint32_t *pu32EBICTL = (uint32_t *)( u32Index0 ); + volatile uint32_t *pu32EBITCTL = (uint32_t *)( u32Index1 ); + + if(u32DataWidth == EBI_BUSWIDTH_8BIT) + { + *pu32EBICTL &= ~EBI_CTL_DW16_Msk; + } + else + { + *pu32EBICTL |= EBI_CTL_DW16_Msk; + } + + *pu32EBICTL |= u32BusMode; + + switch(u32TimingClass) + { + case EBI_TIMING_FASTEST: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_1 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk; + *pu32EBITCTL = 0x0U; + break; + + case EBI_TIMING_VERYFAST: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_1 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x3U << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x03003318U; + break; + + case EBI_TIMING_FAST: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk; + *pu32EBITCTL = 0x0U; + break; + + case EBI_TIMING_NORMAL: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x3U << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x03003318U; + break; + + case EBI_TIMING_SLOW: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x7U << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x07007738U; + break; + + case EBI_TIMING_VERYSLOW: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_4 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x7U << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x07007738U; + break; + + case EBI_TIMING_SLOWEST: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_8 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x7U << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x07007738U; + break; + + default: + *pu32EBICTL &= ~EBI_CTL_EN_Msk; + break; + } +} + +/** + * @brief Disable EBI on specify Bank + * + * @param[in] u32Bank Bank number for EBI. Valid values are: + * - \ref EBI_BANK0 + * - \ref EBI_BANK1 + * - \ref EBI_BANK2 + * + * @return None + * + * @details This function is used to close specify EBI function. + */ +void EBI_Close(uint32_t u32Bank) +{ + uint32_t u32Index = (uint32_t)&EBI->CTL0 + u32Bank * 0x10U; + volatile uint32_t *pu32EBICTL = (uint32_t *)( u32Index ); + + *pu32EBICTL &= ~EBI_CTL_EN_Msk; +} + +/** + * @brief Set EBI Bus Timing for specify Bank + * + * @param[in] u32Bank Bank number for EBI. Valid values are: + * - \ref EBI_BANK0 + * - \ref EBI_BANK1 + * - \ref EBI_BANK2 + * @param[in] u32TimingConfig Configure EBI timing settings, includes TACC, TAHD, W2X and R2R setting. + * @param[in] u32MclkDiv Divider for MCLK. Valid values are: + * - \ref EBI_MCLKDIV_1 + * - \ref EBI_MCLKDIV_2 + * - \ref EBI_MCLKDIV_4 + * - \ref EBI_MCLKDIV_8 + * - \ref EBI_MCLKDIV_16 + * - \ref EBI_MCLKDIV_32 + * - \ref EBI_MCLKDIV_64 + * - \ref EBI_MCLKDIV_128 + * + * @return None + * + * @details This function is used to configure specify EBI bus timing for access EBI device. + */ +void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv) +{ + uint32_t u32Index0 = (uint32_t)&EBI->CTL0 + (uint32_t)u32Bank * 0x10U; + uint32_t u32Index1 = (uint32_t)&EBI->TCTL0 + (uint32_t)u32Bank * 0x10U; + volatile uint32_t *pu32EBICTL = (uint32_t *)( u32Index0 ); + volatile uint32_t *pu32EBITCTL = (uint32_t *)( u32Index1 ); + + *pu32EBICTL = (*pu32EBICTL & ~EBI_CTL_MCLKDIV_Msk) | (u32MclkDiv << EBI_CTL_MCLKDIV_Pos); + *pu32EBITCTL = u32TimingConfig; +} + +/*@}*/ /* end of group EBI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EBI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_ecap.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_ecap.c new file mode 100644 index 0000000000000000000000000000000000000000..f0a9e7728099149ee85ef773bd6aae729185970f --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_ecap.c @@ -0,0 +1,118 @@ +/**************************************************************************//** + * @file ecap.c + * @version V3.00 + * @brief Enhanced Input Capture Timer (ECAP) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup ECAP_Driver ECAP Driver + @{ +*/ + +/** @addtogroup ECAP_EXPORTED_FUNCTIONS ECAP Exported Functions + @{ +*/ + +/** + * @brief Enable ECAP function + * @param[in] ecap The pointer of the specified ECAP module. + * @param[in] u32FuncMask Input capture function select + * - \ref ECAP_DISABLE_COMPARE + * - \ref ECAP_COMPARE_FUNCTION + * @return None + * @details This macro enable input capture function and select compare and reload function. + */ +void ECAP_Open(ECAP_T* ecap, uint32_t u32FuncMask) +{ + /* Clear Input capture mode*/ + ecap->CTL0 = ecap->CTL0 & ~(ECAP_CTL0_CMPEN_Msk); + + /* Enable Input Capture and set mode */ + ecap->CTL0 |= ECAP_CTL0_CAPEN_Msk | (u32FuncMask); +} + + + +/** + * @brief Disable ECAP function + * @param[in] ecap The pointer of the specified ECAP module. + * @return None + * @details This macro disable input capture function. + */ +void ECAP_Close(ECAP_T* ecap) +{ + /* Disable Input Capture*/ + ecap->CTL0 &= ~ECAP_CTL0_CAPEN_Msk; +} + +/** + * @brief This macro is used to enable input channel interrupt + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel Mask + * - \ref ECAP_CTL0_CAPIEN0_Msk + * - \ref ECAP_CTL0_CAPIEN1_Msk + * - \ref ECAP_CTL0_CAPIEN2_Msk + * - \ref ECAP_CTL0_OVIEN_Msk + * - \ref ECAP_CTL0_CMPIEN_Msk + * @return None + * @details This macro will enable the input channel_n interrupt. + */ +void ECAP_EnableINT(ECAP_T* ecap, uint32_t u32Mask) +{ + /* Enable input channel interrupt */ + ecap->CTL0 |= (u32Mask); + + /* Enable NVIC ECAP IRQ */ + if(ecap == (ECAP_T*)ECAP0) + { + NVIC_EnableIRQ((IRQn_Type)ECAP0_IRQn); + } + else + { + NVIC_EnableIRQ((IRQn_Type)ECAP1_IRQn); + } +} + +/** + * @brief This macro is used to disable input channel interrupt + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel number + * - \ref ECAP_CTL0_CAPIEN0_Msk + * - \ref ECAP_CTL0_CAPIEN1_Msk + * - \ref ECAP_CTL0_CAPIEN2_Msk + * - \ref ECAP_CTL0_OVIEN_Msk + * - \ref ECAP_CTL0_CMPIEN_Msk + * @return None + * @details This macro will disable the input channel_n interrupt. + */ +void ECAP_DisableINT(ECAP_T* ecap, uint32_t u32Mask) +{ + /* Disable input channel interrupt */ + ecap->CTL0 &= ~(u32Mask); + + /* Disable NVIC ECAP IRQ */ + if(ecap == (ECAP_T*)ECAP0) + { + NVIC_DisableIRQ((IRQn_Type)ECAP0_IRQn); + } + else + { + NVIC_DisableIRQ((IRQn_Type)ECAP1_IRQn); + } +} + +/*@}*/ /* end of group ECAP_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group ECAP_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_emac.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_emac.c new file mode 100644 index 0000000000000000000000000000000000000000..2b93f1ddd9c599701b72bd16c861a0903b0dbc41 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_emac.c @@ -0,0 +1,1178 @@ +/**************************************************************************//** + * @file emac.c + * @version V1.00 + * @brief M480 EMAC driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include +#include +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EMAC_Driver EMAC Driver + @{ +*/ + + +/* Below are structure, definitions, static variables used locally by EMAC driver and does not want to parse by doxygen unless HIDDEN_SYMBOLS is defined */ +/** @cond HIDDEN_SYMBOLS */ + +/** @addtogroup EMAC_EXPORTED_CONSTANTS EMAC Exported Constants + @{ +*/ + +/* PHY Register Description */ +#define PHY_CNTL_REG 0x00UL /*!< PHY control register address */ +#define PHY_STATUS_REG 0x01UL /*!< PHY status register address */ +#define PHY_ID1_REG 0x02UL /*!< PHY ID1 register */ +#define PHY_ID2_REG 0x03UL /*!< PHY ID2 register */ +#define PHY_ANA_REG 0x04UL /*!< PHY auto-negotiation advertisement register */ +#define PHY_ANLPA_REG 0x05UL /*!< PHY auto-negotiation link partner availability register */ +#define PHY_ANE_REG 0x06UL /*!< PHY auto-negotiation expansion register */ + +/* PHY Control Register */ +#define PHY_CNTL_RESET_PHY (1UL << 15UL) +#define PHY_CNTL_DR_100MB (1UL << 13UL) +#define PHY_CNTL_ENABLE_AN (1UL << 12UL) +#define PHY_CNTL_POWER_DOWN (1UL << 11UL) +#define PHY_CNTL_RESTART_AN (1UL << 9UL) +#define PHY_CNTL_FULLDUPLEX (1UL << 8UL) + +/* PHY Status Register */ +#define PHY_STATUS_AN_COMPLETE (1UL << 5UL) +#define PHY_STATUS_LINK_VALID (1UL << 2UL) + +/* PHY Auto-negotiation Advertisement Register */ +#define PHY_ANA_DR100_TX_FULL (1UL << 8UL) +#define PHY_ANA_DR100_TX_HALF (1UL << 7UL) +#define PHY_ANA_DR10_TX_FULL (1UL << 6UL) +#define PHY_ANA_DR10_TX_HALF (1UL << 5UL) +#define PHY_ANA_IEEE_802_3_CSMA_CD (1UL << 0UL) + +/* PHY Auto-negotiation Link Partner Advertisement Register */ +#define PHY_ANLPA_DR100_TX_FULL (1UL << 8UL) +#define PHY_ANLPA_DR100_TX_HALF (1UL << 7UL) +#define PHY_ANLPA_DR10_TX_FULL (1UL << 6UL) +#define PHY_ANLPA_DR10_TX_HALF (1UL << 5UL) + +/* EMAC Tx/Rx descriptor's owner bit */ +#define EMAC_DESC_OWN_EMAC 0x80000000UL /*!< Set owner to EMAC */ +#define EMAC_DESC_OWN_CPU 0x00000000UL /*!< Set owner to CPU */ + +/* Rx Frame Descriptor Status */ +#define EMAC_RXFD_RTSAS 0x0080UL /*!< Time Stamp Available */ +#define EMAC_RXFD_RP 0x0040UL /*!< Runt Packet */ +#define EMAC_RXFD_ALIE 0x0020UL /*!< Alignment Error */ +#define EMAC_RXFD_RXGD 0x0010UL /*!< Receiving Good packet received */ +#define EMAC_RXFD_PTLE 0x0008UL /*!< Packet Too Long Error */ +#define EMAC_RXFD_CRCE 0x0002UL /*!< CRC Error */ +#define EMAC_RXFD_RXINTR 0x0001UL /*!< Interrupt on receive */ + +/* Tx Frame Descriptor's Control bits */ +#define EMAC_TXFD_TTSEN 0x08UL /*!< Tx time stamp enable */ +#define EMAC_TXFD_INTEN 0x04UL /*!< Tx interrupt enable */ +#define EMAC_TXFD_CRCAPP 0x02UL /*!< Append CRC */ +#define EMAC_TXFD_PADEN 0x01UL /*!< Padding mode enable */ + +/* Tx Frame Descriptor Status */ +#define EMAC_TXFD_TXINTR 0x0001UL /*!< Interrupt on Transmit */ +#define EMAC_TXFD_DEF 0x0002UL /*!< Transmit deferred */ +#define EMAC_TXFD_TXCP 0x0008UL /*!< Transmission Completion */ +#define EMAC_TXFD_EXDEF 0x0010UL /*!< Exceed Deferral */ +#define EMAC_TXFD_NCS 0x0020UL /*!< No Carrier Sense Error */ +#define EMAC_TXFD_TXABT 0x0040UL /*!< Transmission Abort */ +#define EMAC_TXFD_LC 0x0080UL /*!< Late Collision */ +#define EMAC_TXFD_TXHA 0x0100UL /*!< Transmission halted */ +#define EMAC_TXFD_PAU 0x0200UL /*!< Paused */ +#define EMAC_TXFD_SQE 0x0400UL /*!< SQE error */ +#define EMAC_TXFD_TTSAS 0x0800UL /*!< Time Stamp available */ + +/*@}*/ /* end of group EMAC_EXPORTED_CONSTANTS */ + +/** @addtogroup EMAC_EXPORTED_TYPEDEF EMAC Exported Type Defines + @{ +*/ + +/** Tx/Rx buffer descriptor structure */ +typedef struct +{ + uint32_t u32Status1; /*!< Status word 1 */ + uint32_t u32Data; /*!< Pointer to data buffer */ + uint32_t u32Status2; /*!< Status word 2 */ + uint32_t u32Next; /*!< Pointer to next descriptor */ + uint32_t u32Backup1; /*!< For backup descriptor fields over written by time stamp */ + uint32_t u32Backup2; /*!< For backup descriptor fields over written by time stamp */ +} EMAC_DESCRIPTOR_T; + +/** Tx/Rx buffer structure */ +typedef struct +{ + uint8_t au8Buf[EMAC_MAX_PKT_SIZE]; +} EMAC_FRAME_T; + +/*@}*/ /* end of group EMAC_EXPORTED_TYPEDEF */ + +/* local variables */ +static volatile EMAC_DESCRIPTOR_T rx_desc[EMAC_RX_DESC_SIZE]; +static volatile EMAC_FRAME_T rx_buf[EMAC_RX_DESC_SIZE]; +static volatile EMAC_DESCRIPTOR_T tx_desc[EMAC_TX_DESC_SIZE]; +static volatile EMAC_FRAME_T tx_buf[EMAC_TX_DESC_SIZE]; + + +static uint32_t u32CurrentTxDesc, u32NextTxDesc, u32CurrentRxDesc; +static uint32_t s_u32EnableTs = 0UL; + +static void EMAC_MdioWrite(uint32_t u32Reg, uint32_t u32Addr, uint32_t u32Data); +static uint32_t EMAC_MdioRead(uint32_t u32Reg, uint32_t u32Addr); +static void EMAC_TxDescInit(void); +static void EMAC_RxDescInit(void); +static uint32_t EMAC_Subsec2Nsec(uint32_t subsec); +static uint32_t EMAC_Nsec2Subsec(uint32_t nsec); + +/** @addtogroup EMAC_EXPORTED_FUNCTIONS EMAC Exported Functions + @{ +*/ + + +/** + * @brief Write PHY register + * @param[in] u32Reg PHY register number + * @param[in] u32Addr PHY address, this address is board dependent + * @param[in] u32Data data to write to PHY register + * @return None + */ +static void EMAC_MdioWrite(uint32_t u32Reg, uint32_t u32Addr, uint32_t u32Data) +{ + /* Set data register */ + EMAC->MIIMDAT = u32Data ; + /* Set PHY address, PHY register address, busy bit and write bit */ + EMAC->MIIMCTL = u32Reg | (u32Addr << 8) | EMAC_MIIMCTL_BUSY_Msk | EMAC_MIIMCTL_WRITE_Msk | EMAC_MIIMCTL_MDCON_Msk; + + /* Wait write complete by polling busy bit. */ + while (EMAC->MIIMCTL & EMAC_MIIMCTL_BUSY_Msk) + { + ; + } + +} + +/** + * @brief Read PHY register + * @param[in] u32Reg PHY register number + * @param[in] u32Addr PHY address, this address is board dependent + * @return Value read from PHY register + */ +static uint32_t EMAC_MdioRead(uint32_t u32Reg, uint32_t u32Addr) +{ + /* Set PHY address, PHY register address, busy bit */ + EMAC->MIIMCTL = u32Reg | (u32Addr << EMAC_MIIMCTL_PHYADDR_Pos) | EMAC_MIIMCTL_BUSY_Msk | EMAC_MIIMCTL_MDCON_Msk; + + /* Wait read complete by polling busy bit */ + while (EMAC->MIIMCTL & EMAC_MIIMCTL_BUSY_Msk) + { + ; + } + + /* Get return data */ + return EMAC->MIIMDAT; +} + +/** + * @brief Initialize PHY chip, check for the auto-negotiation result. + * @param None + * @return None + */ +void EMAC_PhyInit(void) +{ + uint32_t reg; + uint32_t i = 0UL; + + /* Reset Phy Chip */ + EMAC_MdioWrite(PHY_CNTL_REG, EMAC_PHY_ADDR, PHY_CNTL_RESET_PHY); + + /* Wait until reset complete */ + while (1) + { + reg = EMAC_MdioRead(PHY_CNTL_REG, EMAC_PHY_ADDR) ; + + if ((reg & PHY_CNTL_RESET_PHY) == 0UL) + { + break; + } + } + + while (!(EMAC_MdioRead(PHY_STATUS_REG, EMAC_PHY_ADDR) & PHY_STATUS_LINK_VALID)) + { + if (i++ > 80000UL) /* Cable not connected */ + { + EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk; + EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk; + break; + } + } + + if (i <= 80000UL) + { + /* Configure auto negotiation capability */ + EMAC_MdioWrite(PHY_ANA_REG, EMAC_PHY_ADDR, PHY_ANA_DR100_TX_FULL | + PHY_ANA_DR100_TX_HALF | + PHY_ANA_DR10_TX_FULL | + PHY_ANA_DR10_TX_HALF | + PHY_ANA_IEEE_802_3_CSMA_CD); + /* Restart auto negotiation */ + EMAC_MdioWrite(PHY_CNTL_REG, EMAC_PHY_ADDR, EMAC_MdioRead(PHY_CNTL_REG, EMAC_PHY_ADDR) | PHY_CNTL_RESTART_AN); + + /* Wait for auto-negotiation complete */ + while (!(EMAC_MdioRead(PHY_STATUS_REG, EMAC_PHY_ADDR) & PHY_STATUS_AN_COMPLETE)) + { + ; + } + + /* Check link valid again. Some PHYs needs to check result after link valid bit set */ + while (!(EMAC_MdioRead(PHY_STATUS_REG, EMAC_PHY_ADDR) & PHY_STATUS_LINK_VALID)) + { + ; + } + + /* Check link partner capability */ + reg = EMAC_MdioRead(PHY_ANLPA_REG, EMAC_PHY_ADDR) ; + + if (reg & PHY_ANLPA_DR100_TX_FULL) + { + EMAC->CTL |= EMAC_CTL_OPMODE_Msk; + EMAC->CTL |= EMAC_CTL_FUDUP_Msk; + } + else if (reg & PHY_ANLPA_DR100_TX_HALF) + { + EMAC->CTL |= EMAC_CTL_OPMODE_Msk; + EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk; + } + else if (reg & PHY_ANLPA_DR10_TX_FULL) + { + EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk; + EMAC->CTL |= EMAC_CTL_FUDUP_Msk; + } + else + { + EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk; + EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk; + } + } +} + +/** + * @brief Initial EMAC Tx descriptors and get Tx descriptor base address + * @param None + * @return None + */ +static void EMAC_TxDescInit(void) +{ + uint32_t i; + + /* Get Frame descriptor's base address. */ + EMAC->TXDSA = (uint32_t)&tx_desc[0]; + u32NextTxDesc = u32CurrentTxDesc = (uint32_t)&tx_desc[0]; + + for (i = 0UL; i < EMAC_TX_DESC_SIZE; i++) + { + + if (s_u32EnableTs) + { + tx_desc[i].u32Status1 = EMAC_TXFD_PADEN | EMAC_TXFD_CRCAPP | EMAC_TXFD_INTEN; + } + else + { + tx_desc[i].u32Status1 = EMAC_TXFD_PADEN | EMAC_TXFD_CRCAPP | EMAC_TXFD_INTEN | EMAC_TXFD_TTSEN; + } + + tx_desc[i].u32Data = (uint32_t)((uint32_t)&tx_buf[i]); + tx_desc[i].u32Backup1 = tx_desc[i].u32Data; + tx_desc[i].u32Status2 = 0UL; + tx_desc[i].u32Next = (uint32_t)&tx_desc[(i + 1UL) % EMAC_TX_DESC_SIZE]; + tx_desc[i].u32Backup2 = tx_desc[i].u32Next; + + } + +} + + +/** + * @brief Initial EMAC Rx descriptors and get Rx descriptor base address + * @param None + * @return None + */ +static void EMAC_RxDescInit(void) +{ + + uint32_t i; + + /* Get Frame descriptor's base address. */ + EMAC->RXDSA = (uint32_t)&rx_desc[0]; + u32CurrentRxDesc = (uint32_t)&rx_desc[0]; + + for (i = 0UL; i < EMAC_RX_DESC_SIZE; i++) + { + rx_desc[i].u32Status1 = EMAC_DESC_OWN_EMAC; + rx_desc[i].u32Data = (uint32_t)((uint32_t)&rx_buf[i]); + rx_desc[i].u32Backup1 = rx_desc[i].u32Data; + rx_desc[i].u32Status2 = 0UL; + rx_desc[i].u32Next = (uint32_t)&rx_desc[(i + 1UL) % EMAC_RX_DESC_SIZE]; + rx_desc[i].u32Backup2 = rx_desc[i].u32Next; + } + +} + +/** + * @brief Convert subsecond value to nano second + * @param[in] subsec Subsecond value to be convert + * @return Nano second + */ +static uint32_t EMAC_Subsec2Nsec(uint32_t subsec) +{ + /* 2^31 subsec == 10^9 ns */ + uint64_t i; + i = 1000000000ull * (uint64_t)subsec; + i >>= 31; + return ((uint32_t)i); +} + +/** + * @brief Convert nano second to subsecond value + * @param[in] nsec Nano second to be convert + * @return Subsecond + */ +static uint32_t EMAC_Nsec2Subsec(uint32_t nsec) +{ + /* 10^9 ns = 2^31 subsec */ + uint64_t i; + i = (1ull << 31) * nsec; + i /= 1000000000ull; + return ((uint32_t)i); +} + + +/*@}*/ /* end of group EMAC_EXPORTED_FUNCTIONS */ + + + +/** @endcond HIDDEN_SYMBOLS */ + + +/** @addtogroup EMAC_EXPORTED_FUNCTIONS EMAC Exported Functions + @{ +*/ + + +/** + * @brief Initialize EMAC interface, including descriptors, MAC address, and PHY. + * @param[in] pu8MacAddr Pointer to uint8_t array holds MAC address + * @return None + * @note This API configures EMAC to receive all broadcast and multicast packets, but could configure to other settings with + * \ref EMAC_ENABLE_RECV_BCASTPKT, \ref EMAC_DISABLE_RECV_BCASTPKT, \ref EMAC_ENABLE_RECV_MCASTPKT, and \ref EMAC_DISABLE_RECV_MCASTPKT + * @note Receive(RX) and transmit(TX) are not enabled yet, application must call \ref EMAC_ENABLE_RX and \ref EMAC_ENABLE_TX to + * enable receive and transmit function. + */ +void EMAC_Open(uint8_t *pu8MacAddr) +{ + /* Enable transmit and receive descriptor */ + EMAC_TxDescInit(); + EMAC_RxDescInit(); + + /* Set the CAM Control register and the MAC address value */ + EMAC_SetMacAddr(pu8MacAddr); + + /* Configure the MAC interrupt enable register. */ + EMAC->INTEN = EMAC_INTEN_RXIEN_Msk | + EMAC_INTEN_TXIEN_Msk | + EMAC_INTEN_RXGDIEN_Msk | + EMAC_INTEN_TXCPIEN_Msk | + EMAC_INTEN_RXBEIEN_Msk | + EMAC_INTEN_TXBEIEN_Msk | + EMAC_INTEN_RDUIEN_Msk | + EMAC_INTEN_TSALMIEN_Msk | + EMAC_INTEN_WOLIEN_Msk; + + /* Configure the MAC control register. */ + EMAC->CTL = EMAC_CTL_STRIPCRC_Msk | + EMAC_CTL_RMIIEN_Msk; + + /* Accept packets for us and all broadcast and multicast packets */ + EMAC->CAMCTL = EMAC_CAMCTL_CMPEN_Msk | + EMAC_CAMCTL_AMP_Msk | + EMAC_CAMCTL_ABP_Msk; + + /* Limit the max receive frame length to 1514 + 4 */ + EMAC->MRFL = EMAC_MAX_PKT_SIZE; +} + +/** + * @brief This function stop all receive and transmit activity and disable MAC interface + * @param None + * @return None + */ + +void EMAC_Close(void) +{ + EMAC->CTL |= EMAC_CTL_RST_Msk; + + while (EMAC->CTL & EMAC_CTL_RST_Msk) {} +} + +/** + * @brief Set the device MAC address + * @param[in] pu8MacAddr Pointer to uint8_t array holds MAC address + * @return None + */ +void EMAC_SetMacAddr(uint8_t *pu8MacAddr) +{ + EMAC_EnableCamEntry(0UL, pu8MacAddr); + +} + +/** + * @brief Fill a CAM entry for MAC address comparison. + * @param[in] u32Entry MAC entry to fill. Entry 0 is used to store device MAC address, do not overwrite the setting in it. + * @param[in] pu8MacAddr Pointer to uint8_t array holds MAC address + * @return None + */ +void EMAC_EnableCamEntry(uint32_t u32Entry, uint8_t pu8MacAddr[]) +{ + uint32_t u32Lsw, u32Msw; + uint32_t reg; + u32Lsw = (uint32_t)(((uint32_t)pu8MacAddr[4] << 24) | + ((uint32_t)pu8MacAddr[5] << 16)); + u32Msw = (uint32_t)(((uint32_t)pu8MacAddr[0] << 24) | + ((uint32_t)pu8MacAddr[1] << 16) | + ((uint32_t)pu8MacAddr[2] << 8) | + (uint32_t)pu8MacAddr[3]); + + reg = (uint32_t)&EMAC->CAM0M + u32Entry * 2UL * 4UL; + *(uint32_t volatile *)reg = u32Msw; + reg = (uint32_t)&EMAC->CAM0L + u32Entry * 2UL * 4UL; + *(uint32_t volatile *)reg = u32Lsw; + + EMAC->CAMEN |= (1UL << u32Entry); +} + +/** + * @brief Disable a specified CAM entry + * @param[in] u32Entry CAM entry to be disabled + * @return None + */ +void EMAC_DisableCamEntry(uint32_t u32Entry) +{ + EMAC->CAMEN &= ~(1UL << u32Entry); +} + + +/** + * @brief Receive an Ethernet packet + * @param[in] pu8Data Pointer to a buffer to store received packet (4 byte CRC removed) + * @param[in] pu32Size Received packet size (without 4 byte CRC). + * @return Packet receive success or not + * @retval 0 No packet available for receive + * @retval 1 A packet is received + * @note Return 0 doesn't guarantee the packet will be sent and received successfully. + */ +uint32_t EMAC_RecvPkt(uint8_t *pu8Data, uint32_t *pu32Size) +{ + EMAC_DESCRIPTOR_T *desc; + uint32_t status, reg; + uint32_t u32Count = 0UL; + + /* Clear Rx interrupt flags */ + reg = EMAC->INTSTS; + EMAC->INTSTS = reg & 0xFFFFUL; /* Clear all RX related interrupt status */ + + if (reg & EMAC_INTSTS_RXBEIF_Msk) + { + /* Bus error occurred, this is usually a bad sign about software bug and will occur again... */ + while (1) {} + } + else + { + + /* Get Rx Frame Descriptor */ + desc = (EMAC_DESCRIPTOR_T *)u32CurrentRxDesc; + + /* If we reach last recv Rx descriptor, leave the loop */ + if ((desc->u32Status1 & EMAC_DESC_OWN_EMAC) != EMAC_DESC_OWN_EMAC) /* ownership=CPU */ + { + + status = desc->u32Status1 >> 16; + + /* If Rx frame is good, process received frame */ + if (status & EMAC_RXFD_RXGD) + { + /* lower 16 bit in descriptor status1 stores the Rx packet length */ + *pu32Size = desc->u32Status1 & 0xFFFFUL; + memcpy(pu8Data, (uint8_t *)desc->u32Backup1, *pu32Size); + u32Count = 1UL; + } + else + { + /* Save Error status if necessary */ + if (status & EMAC_RXFD_RP) {} + + if (status & EMAC_RXFD_ALIE) {} + + if (status & EMAC_RXFD_PTLE) {} + + if (status & EMAC_RXFD_CRCE) {} + } + } + } + + return (u32Count); +} + +/** + * @brief Receive an Ethernet packet and the time stamp while it's received + * @param[out] pu8Data Pointer to a buffer to store received packet (4 byte CRC removed) + * @param[out] pu32Size Received packet size (without 4 byte CRC). + * @param[out] pu32Sec Second value while packet received + * @param[out] pu32Nsec Nano second value while packet received + * @return Packet receive success or not + * @retval 0 No packet available for receive + * @retval 1 A packet is received + * @note Return 0 doesn't guarantee the packet will be sent and received successfully. + * @note Largest Ethernet packet is 1514 bytes after stripped CRC, application must give + * a buffer large enough to store such packet + */ +uint32_t EMAC_RecvPktTS(uint8_t *pu8Data, uint32_t *pu32Size, uint32_t *pu32Sec, uint32_t *pu32Nsec) +{ + EMAC_DESCRIPTOR_T *desc; + uint32_t status, reg; + uint32_t u32Count = 0UL; + + /* Clear Rx interrupt flags */ + reg = EMAC->INTSTS; + EMAC->INTSTS = reg & 0xFFFFUL; /* Clear all Rx related interrupt status */ + + if (reg & EMAC_INTSTS_RXBEIF_Msk) + { + /* Bus error occurred, this is usually a bad sign about software bug and will occur again... */ + while (1) {} + } + else + { + + /* Get Rx Frame Descriptor */ + desc = (EMAC_DESCRIPTOR_T *)u32CurrentRxDesc; + + /* If we reach last recv Rx descriptor, leave the loop */ + if (EMAC->CRXDSA != (uint32_t)desc) + { + if ((desc->u32Status1 | EMAC_DESC_OWN_EMAC) != EMAC_DESC_OWN_EMAC) /* ownership=CPU */ + { + + status = desc->u32Status1 >> 16; + + /* If Rx frame is good, process received frame */ + if (status & EMAC_RXFD_RXGD) + { + /* lower 16 bit in descriptor status1 stores the Rx packet length */ + *pu32Size = desc->u32Status1 & 0xFFFFUL; + memcpy(pu8Data, (uint8_t *)desc->u32Backup1, *pu32Size); + + *pu32Sec = desc->u32Next; /* second stores in descriptor's NEXT field */ + *pu32Nsec = EMAC_Subsec2Nsec(desc->u32Data); /* Sub nano second store in DATA field */ + + u32Count = 1UL; + } + else + { + /* Save Error status if necessary */ + if (status & EMAC_RXFD_RP) {} + + if (status & EMAC_RXFD_ALIE) {} + + if (status & EMAC_RXFD_PTLE) {} + + if (status & EMAC_RXFD_CRCE) {} + } + } + } + } + + return (u32Count); +} + +/** + * @brief Clean up process after a packet is received + * @param None + * @return None + * @details EMAC Rx interrupt service routine \b must call this API to release the resource use by receive process + * @note Application can only call this function once every time \ref EMAC_RecvPkt or \ref EMAC_RecvPktTS returns 1 + */ +void EMAC_RecvPktDone(void) +{ + EMAC_DESCRIPTOR_T *desc; + /* Get Rx Frame Descriptor */ + desc = (EMAC_DESCRIPTOR_T *)u32CurrentRxDesc; + + /* Restore descriptor link list and data pointer they will be overwrite if time stamp enabled */ + desc->u32Data = desc->u32Backup1; + desc->u32Next = desc->u32Backup2; + + /* Change ownership to DMA for next use */ + desc->u32Status1 |= EMAC_DESC_OWN_EMAC; + + /* Get Next Frame Descriptor pointer to process */ + desc = (EMAC_DESCRIPTOR_T *)desc->u32Next; + + /* Save last processed Rx descriptor */ + u32CurrentRxDesc = (uint32_t)desc; + + EMAC_TRIGGER_RX(); +} + + +/** + * @brief Send an Ethernet packet + * @param[in] pu8Data Pointer to a buffer holds the packet to transmit + * @param[in] u32Size Packet size (without 4 byte CRC). + * @return Packet transmit success or not + * @retval 0 Transmit failed due to descriptor unavailable. + * @retval 1 Packet is copied to descriptor and triggered to transmit. + * @note Return 1 doesn't guarantee the packet will be sent and received successfully. + */ +uint32_t EMAC_SendPkt(uint8_t *pu8Data, uint32_t u32Size) +{ + EMAC_DESCRIPTOR_T *desc; + uint32_t status; + uint32_t ret = 0UL; + /* Get Tx frame descriptor & data pointer */ + desc = (EMAC_DESCRIPTOR_T *)u32NextTxDesc; + + status = desc->u32Status1; + + /* Check descriptor ownership */ + if ((status & EMAC_DESC_OWN_EMAC) != EMAC_DESC_OWN_EMAC) + { + memcpy((uint8_t *)desc->u32Data, pu8Data, u32Size); + + /* Set Tx descriptor transmit byte count */ + desc->u32Status2 = u32Size; + + /* Change descriptor ownership to EMAC */ + desc->u32Status1 |= EMAC_DESC_OWN_EMAC; + + /* Get next Tx descriptor */ + u32NextTxDesc = (uint32_t)(desc->u32Next); + + /* Trigger EMAC to send the packet */ + EMAC_TRIGGER_TX(); + ret = 1UL; + } + + return (ret); +} + + +/** + * @brief Clean up process after packet(s) are sent + * @param None + * @return Number of packet sent between two function calls + * @details EMAC Tx interrupt service routine \b must call this API or \ref EMAC_SendPktDoneTS to + * release the resource use by transmit process + */ +uint32_t EMAC_SendPktDone(void) +{ + EMAC_DESCRIPTOR_T *desc; + uint32_t status, reg; + uint32_t last_tx_desc; + uint32_t u32Count = 0UL; + + reg = EMAC->INTSTS; + /* Clear Tx interrupt flags */ + EMAC->INTSTS = reg & (0xFFFF0000UL & ~EMAC_INTSTS_TSALMIF_Msk); + + + if (reg & EMAC_INTSTS_TXBEIF_Msk) + { + /* Bus error occurred, this is usually a bad sign about software bug and will occur again... */ + while (1) {} + } + else + { + /* Process the descriptor(s). */ + last_tx_desc = EMAC->CTXDSA ; + /* Get our first descriptor to process */ + desc = (EMAC_DESCRIPTOR_T *) u32CurrentTxDesc; + + do + { + /* Descriptor ownership is still EMAC, so this packet haven't been send. */ + if (desc->u32Status1 & EMAC_DESC_OWN_EMAC) + { + break; + } + + /* Get Tx status stored in descriptor */ + status = desc->u32Status2 >> 16UL; + + if (status & EMAC_TXFD_TXCP) + { + u32Count++; + } + else + { + /* Do nothing here on error. */ + if (status & EMAC_TXFD_TXABT) {} + + if (status & EMAC_TXFD_DEF) {} + + if (status & EMAC_TXFD_PAU) {} + + if (status & EMAC_TXFD_EXDEF) {} + + if (status & EMAC_TXFD_NCS) {} + + if (status & EMAC_TXFD_SQE) {} + + if (status & EMAC_TXFD_LC) {} + + if (status & EMAC_TXFD_TXHA) {} + } + + /* restore descriptor link list and data pointer they will be overwrite if time stamp enabled */ + desc->u32Data = desc->u32Backup1; + desc->u32Next = desc->u32Backup2; + /* go to next descriptor in link */ + desc = (EMAC_DESCRIPTOR_T *)desc->u32Next; + } while (last_tx_desc != (uint32_t)desc); /* If we reach last sent Tx descriptor, leave the loop */ + + /* Save last processed Tx descriptor */ + u32CurrentTxDesc = (uint32_t)desc; + } + + return (u32Count); +} + +/** + * @brief Clean up process after a packet is sent, and get the time stamp while packet is sent + * @param[in] pu32Sec Second value while packet sent + * @param[in] pu32Nsec Nano second value while packet sent + * @return If a packet sent successfully + * @retval 0 No packet sent successfully, and the value in *pu32Sec and *pu32Nsec are meaningless + * @retval 1 A packet sent successfully, and the value in *pu32Sec and *pu32Nsec is the time stamp while packet sent + * @details EMAC Tx interrupt service routine \b must call this API or \ref EMAC_SendPktDone to + * release the resource use by transmit process + */ +uint32_t EMAC_SendPktDoneTS(uint32_t *pu32Sec, uint32_t *pu32Nsec) +{ + + EMAC_DESCRIPTOR_T *desc; + uint32_t status, reg; + uint32_t u32Count = 0UL; + + reg = EMAC->INTSTS; + /* Clear Tx interrupt flags */ + EMAC->INTSTS = reg & (0xFFFF0000UL & ~EMAC_INTSTS_TSALMIF_Msk); + + + if (reg & EMAC_INTSTS_TXBEIF_Msk) + { + /* Bus error occurred, this is usually a bad sign about software bug and will occur again... */ + while (1) {} + } + else + { + /* Process the descriptor. + Get our first descriptor to process */ + desc = (EMAC_DESCRIPTOR_T *) u32CurrentTxDesc; + + /* Descriptor ownership is still EMAC, so this packet haven't been send. */ + if ((desc->u32Status1 & EMAC_DESC_OWN_EMAC) != EMAC_DESC_OWN_EMAC) + { + /* Get Tx status stored in descriptor */ + status = desc->u32Status2 >> 16UL; + + if (status & EMAC_TXFD_TXCP) + { + u32Count = 1UL; + *pu32Sec = desc->u32Next; /* second stores in descriptor's NEXT field */ + *pu32Nsec = EMAC_Subsec2Nsec(desc->u32Data); /* Sub nano second store in DATA field */ + } + else + { + /* Do nothing here on error. */ + if (status & EMAC_TXFD_TXABT) {} + + if (status & EMAC_TXFD_DEF) {} + + if (status & EMAC_TXFD_PAU) {} + + if (status & EMAC_TXFD_EXDEF) {} + + if (status & EMAC_TXFD_NCS) {} + + if (status & EMAC_TXFD_SQE) {} + + if (status & EMAC_TXFD_LC) {} + + if (status & EMAC_TXFD_TXHA) {} + } + + /* restore descriptor link list and data pointer they will be overwrite if time stamp enabled */ + desc->u32Data = desc->u32Backup1; + desc->u32Next = desc->u32Backup2; + /* go to next descriptor in link */ + desc = (EMAC_DESCRIPTOR_T *)desc->u32Next; + + /* Save last processed Tx descriptor */ + u32CurrentTxDesc = (uint32_t)desc; + } + } + + return (u32Count); +} + +/** + * @brief Enable IEEE1588 time stamp function and set current time + * @param[in] u32Sec Second value + * @param[in] u32Nsec Nano second value + * @return None + */ +void EMAC_EnableTS(uint32_t u32Sec, uint32_t u32Nsec) +{ + double f; + uint32_t reg; + EMAC->TSCTL = EMAC_TSCTL_TSEN_Msk; + EMAC->UPDSEC = u32Sec; /* Assume current time is 0 sec + 0 nano sec */ + EMAC->UPDSUBSEC = EMAC_Nsec2Subsec(u32Nsec); + + /* PTP source clock is 160MHz (Real chip using PLL). Each tick is 6.25ns + Assume we want to set each tick to 100ns. + Increase register = (100 * 2^31) / (10^9) = 214.71 =~ 215 = 0xD7 + Addend register = 2^32 * tick_freq / (160MHz), where tick_freq = (2^31 / 215) MHz + From above equation, addend register = 2^63 / (160M * 215) ~= 268121280 = 0xFFB34C0 + So: + EMAC->TSIR = 0xD7; + EMAC->TSAR = 0x1E70C600; */ + f = (100.0 * 2147483648.0) / (1000000000.0) + 0.5; + EMAC->TSINC = (reg = (uint32_t)f); + f = (double)9223372036854775808.0 / ((double)(CLK_GetHCLKFreq()) * (double)reg); + EMAC->TSADDEND = (uint32_t)f; + EMAC->TSCTL |= (EMAC_TSCTL_TSUPDATE_Msk | EMAC_TSCTL_TSIEN_Msk | EMAC_TSCTL_TSMODE_Msk); /* Fine update */ +} + +/** + * @brief Disable IEEE1588 time stamp function + * @param None + * @return None + */ +void EMAC_DisableTS(void) +{ + EMAC->TSCTL = 0UL; +} + +/** + * @brief Get current time stamp + * @param[out] pu32Sec Current second value + * @param[out] pu32Nsec Current nano second value + * @return None + */ +void EMAC_GetTime(uint32_t *pu32Sec, uint32_t *pu32Nsec) +{ + /* Must read TSLSR firstly. Hardware will preserve TSMSR value at the time TSLSR read. */ + *pu32Nsec = EMAC_Subsec2Nsec(EMAC->TSSUBSEC); + *pu32Sec = EMAC->TSSEC; +} + +/** + * @brief Set current time stamp + * @param[in] u32Sec Second value + * @param[in] u32Nsec Nano second value + * @return None + */ +void EMAC_SetTime(uint32_t u32Sec, uint32_t u32Nsec) +{ + /* Disable time stamp counter before update time value (clear EMAC_TSCTL_TSIEN_Msk) */ + EMAC->TSCTL = EMAC_TSCTL_TSEN_Msk; + EMAC->UPDSEC = u32Sec; + EMAC->UPDSUBSEC = EMAC_Nsec2Subsec(u32Nsec); + EMAC->TSCTL |= (EMAC_TSCTL_TSIEN_Msk | EMAC_TSCTL_TSMODE_Msk); + +} + +/** + * @brief Enable alarm function and set alarm time + * @param[in] u32Sec Second value to trigger alarm + * @param[in] u32Nsec Nano second value to trigger alarm + * @return None + */ +void EMAC_EnableAlarm(uint32_t u32Sec, uint32_t u32Nsec) +{ + + EMAC->ALMSEC = u32Sec; + EMAC->ALMSUBSEC = EMAC_Nsec2Subsec(u32Nsec); + EMAC->TSCTL |= EMAC_TSCTL_TSALMEN_Msk; + +} + +/** + * @brief Disable alarm function + * @param None + * @return None + */ +void EMAC_DisableAlarm(void) +{ + + EMAC->TSCTL &= ~EMAC_TSCTL_TSALMEN_Msk; + +} + +/** + * @brief Add a offset to current time + * @param[in] u32Neg Offset is negative value (u32Neg == 1) or positive value (u32Neg == 0). + * @param[in] u32Sec Second value to add to current time + * @param[in] u32Nsec Nano second value to add to current time + * @return None + */ +void EMAC_UpdateTime(uint32_t u32Neg, uint32_t u32Sec, uint32_t u32Nsec) +{ + EMAC->UPDSEC = u32Sec; + EMAC->UPDSUBSEC = EMAC_Nsec2Subsec(u32Nsec); + + if (u32Neg) + { + EMAC->UPDSUBSEC |= BIT31; /* Set bit 31 indicates this is a negative value */ + } + + EMAC->TSCTL |= EMAC_TSCTL_TSUPDATE_Msk; + +} + +/** + * @brief Check Ethernet link status + * @param None + * @return Current link status, could be one of following value. + * - \ref EMAC_LINK_DOWN + * - \ref EMAC_LINK_100F + * - \ref EMAC_LINK_100H + * - \ref EMAC_LINK_10F + * - \ref EMAC_LINK_10H + * @note This API should be called regularly to sync EMAC setting with real connection status + */ +uint32_t EMAC_CheckLinkStatus(void) +{ + uint32_t reg, ret = EMAC_LINK_DOWN; + + /* Check link valid again */ + if (EMAC_MdioRead(PHY_STATUS_REG, EMAC_PHY_ADDR) & PHY_STATUS_LINK_VALID) + { + /* Check link partner capability */ + reg = EMAC_MdioRead(PHY_ANLPA_REG, EMAC_PHY_ADDR) ; + + if (reg & PHY_ANLPA_DR100_TX_FULL) + { + EMAC->CTL |= EMAC_CTL_OPMODE_Msk; + EMAC->CTL |= EMAC_CTL_FUDUP_Msk; + ret = EMAC_LINK_100F; + } + else if (reg & PHY_ANLPA_DR100_TX_HALF) + { + EMAC->CTL |= EMAC_CTL_OPMODE_Msk; + EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk; + ret = EMAC_LINK_100H; + } + else if (reg & PHY_ANLPA_DR10_TX_FULL) + { + EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk; + EMAC->CTL |= EMAC_CTL_FUDUP_Msk; + ret = EMAC_LINK_10F; + } + else + { + EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk; + EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk; + ret = EMAC_LINK_10H; + } + } + + return ret; +} + +/** + * @brief Fill a MAC address to list and enable. + * @param A MAC address + * @return The CAM index + * @retval -1 Failed to fill the MAC address. + * @retval 0~(EMAC_CAMENTRY_NB-1) The index number of entry location. + */ +int32_t EMAC_FillCamEntry(uint8_t pu8MacAddr[]) +{ + uint32_t *EMAC_CAMxM; + uint32_t *EMAC_CAMxL; + int32_t index; + uint8_t mac[6]; + + for (index = 0; index < EMAC_CAMENTRY_NB; index ++) + { + EMAC_CAMxM = (uint32_t *)((uint32_t)&EMAC->CAM0M + (index * 8)); + EMAC_CAMxL = (uint32_t *)((uint32_t)&EMAC->CAM0L + (index * 8)); + + mac[0] = (*EMAC_CAMxM >> 24) & 0xff; + mac[1] = (*EMAC_CAMxM >> 16) & 0xff; + mac[2] = (*EMAC_CAMxM >> 8) & 0xff; + mac[3] = (*EMAC_CAMxM) & 0xff; + mac[4] = (*EMAC_CAMxL >> 24) & 0xff; + mac[5] = (*EMAC_CAMxL >> 16) & 0xff; + + if (memcmp(mac, pu8MacAddr, sizeof(mac)) == 0) + { + goto exit_emac_fillcamentry; + } + + if (*EMAC_CAMxM == 0 && *EMAC_CAMxL == 0) + { + break; + } + } + + if (index < EMAC_CAMENTRY_NB) + { + EMAC_EnableCamEntry(index, pu8MacAddr); + goto exit_emac_fillcamentry; + } + + return -1; + +exit_emac_fillcamentry: + + return index; +} + +/** + * @brief Send an Ethernet packet + * @param[in] u32Size Packet size (without 4 byte CRC). + * @return Packet transmit success or not + * @retval 0 Transmit failed due to descriptor unavailable. + * @retval 1 Triggered to transmit. + * @note Return 1 doesn't guarantee the packet will be sent and received successfully. + */ +uint32_t EMAC_SendPktWoCopy(uint32_t u32Size) +{ + EMAC_DESCRIPTOR_T *desc; + uint32_t status; + uint32_t ret = 0UL; + /* Get Tx frame descriptor & data pointer */ + desc = (EMAC_DESCRIPTOR_T *)u32NextTxDesc; + + status = desc->u32Status1; + + /* Check descriptor ownership */ + if ((status & EMAC_DESC_OWN_EMAC) != EMAC_DESC_OWN_EMAC) + { + /* Set Tx descriptor transmit byte count */ + desc->u32Status2 = u32Size; + + /* Change descriptor ownership to EMAC */ + desc->u32Status1 |= EMAC_DESC_OWN_EMAC; + + /* Get next Tx descriptor */ + u32NextTxDesc = (uint32_t)(desc->u32Next); + + /* Trigger EMAC to send the packet */ + EMAC_TRIGGER_TX(); + ret = 1UL; + } + + return (ret); +} + +/** + * @brief Get avaiable TX buffer address + * @param None + * @return An avaiable TX buffer. + * @note This API should be called before EMAC_SendPkt_WoCopy calling. Caller will do data-copy. + */ +uint8_t *EMAC_ClaimFreeTXBuf(void) +{ + EMAC_DESCRIPTOR_T *desc = (EMAC_DESCRIPTOR_T *)u32NextTxDesc; + + if (desc->u32Status1 & EMAC_DESC_OWN_EMAC) + { + return (NULL); + } + else + { + return (uint8_t *)desc->u32Data; + } +} + +/** + * @brief Get data length of avaiable RX buffer. + * @param None + * @return An data length of avaiable RX buffer. + * @note This API should be called before EMAC_RecvPktDone_WoTrigger calling. Caller will do data-copy. + */ +uint32_t EMAC_GetAvailRXBufSize(uint8_t** ppuDataBuf) +{ + EMAC_DESCRIPTOR_T *desc = (EMAC_DESCRIPTOR_T *)u32CurrentRxDesc; + + if ((desc->u32Status1 & EMAC_DESC_OWN_EMAC) != EMAC_DESC_OWN_EMAC) /* ownership=CPU */ + { + uint32_t status = desc->u32Status1 >> 16; + + /* It is good and no CRC error. */ + if ((status & EMAC_RXFD_RXGD) && !(status & EMAC_RXFD_CRCE)) + { + *ppuDataBuf = (uint8_t*)desc->u32Backup1; + return desc->u32Status1 & 0xFFFFUL; + } + else + { + // Drop it + EMAC_RecvPktDone(); + } + } + + return 0; +} + + +/** + * @brief Clean up process after a packet is received. + * @param None + * @return None + * @details Caller must call the function to release the resource. + * @note Application can only call this function once every time \ref EMAC_RecvPkt or \ref EMAC_RecvPktTS returns 1 + * @note This function is without doing EMAC_TRIGGER_RX. + */ +void EMAC_RecvPktDoneWoRxTrigger(void) +{ + EMAC_DESCRIPTOR_T *desc; + /* Get Rx Frame Descriptor */ + desc = (EMAC_DESCRIPTOR_T *)u32CurrentRxDesc; + + /* Restore descriptor link list and data pointer they will be overwrite if time stamp enabled */ + desc->u32Data = desc->u32Backup1; + desc->u32Next = desc->u32Backup2; + + /* Change ownership to DMA for next use */ + desc->u32Status1 |= EMAC_DESC_OWN_EMAC; + + /* Get Next Frame Descriptor pointer to process */ + desc = (EMAC_DESCRIPTOR_T *)desc->u32Next; + + /* Save last processed Rx descriptor */ + u32CurrentRxDesc = (uint32_t)desc; +} + + +/*@}*/ /* end of group EMAC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EMAC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_epwm.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_epwm.c new file mode 100644 index 0000000000000000000000000000000000000000..e082fa5dba86d7f9d97b2d8fe8c3dca0f953c9aa --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_epwm.c @@ -0,0 +1,1699 @@ +/**************************************************************************//** + * @file epwm.c + * @version V3.00 + * $Revision: 3 $ + * @brief M480 series EPWM driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EPWM_Driver EPWM Driver + @{ +*/ + + +/** @addtogroup EPWM_EXPORTED_FUNCTIONS EPWM Exported Functions + @{ +*/ + +/** + * @brief Configure EPWM capture and get the nearest unit time. + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32UnitTimeNsec The unit time of counter + * @param[in] u32CaptureEdge The condition to latch the counter. This parameter is not used + * @return The nearest unit time in nano second. + * @details This function is used to Configure EPWM capture and get the nearest unit time. + */ +uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge) +{ + uint32_t u32Src; + uint32_t u32EPWMClockSrc; + uint32_t u32NearestUnitTimeNsec; + uint32_t u16Prescale = 1U, u16CNR = 0xFFFFU; + + if(epwm == EPWM0) + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM0SEL_Msk; + } + else /* (epwm == EPWM1) */ + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM1SEL_Msk; + } + + if(u32Src == 0U) + { + /* clock source is from PLL clock */ + u32EPWMClockSrc = CLK_GetPLLClockFreq(); + } + else + { + /* clock source is from PCLK */ + SystemCoreClockUpdate(); + if(epwm == EPWM0) + { + u32EPWMClockSrc = CLK_GetPCLK0Freq(); + } + else /* (epwm == EPWM1) */ + { + u32EPWMClockSrc = CLK_GetPCLK1Freq(); + } + } + + u32EPWMClockSrc /= 1000U; + for(u16Prescale = 1U; u16Prescale <= 0x1000U; u16Prescale++) + { + uint32_t u32Exit = 0U; + u32NearestUnitTimeNsec = (1000000U * u16Prescale) / u32EPWMClockSrc; + if(u32NearestUnitTimeNsec < u32UnitTimeNsec) + { + if(u16Prescale == 0x1000U) /* limit to the maximum unit time(nano second) */ + { + u32Exit = 1U; + } + else + { + u32Exit = 0U; + } + if(!((1000000U * (u16Prescale + 1U) > (u32NearestUnitTimeNsec * u32EPWMClockSrc)))) + { + u32Exit = 1U; + } + else + { + u32Exit = 0U; + } + } + else + { + u32Exit = 1U; + } + if (u32Exit == 1U) + { + break; + } + else {} + } + + /* convert to real register value */ + /* every two channels share a prescaler */ + u16Prescale -= 1U; + EPWM_SET_PRESCALER(epwm, u32ChannelNum, u16Prescale); + + /* set EPWM to down count type(edge aligned) */ + (epwm)->CTL1 = ((epwm)->CTL1 & ~(EPWM_CTL1_CNTTYPE0_Msk << (u32ChannelNum << 1U))) | (1UL << (u32ChannelNum << 1U)); + /* set EPWM to auto-reload mode */ + (epwm)->CTL1 &= ~(EPWM_CTL1_CNTMODE0_Msk << u32ChannelNum); + EPWM_SET_CNR(epwm, u32ChannelNum, u16CNR); + + return (u32NearestUnitTimeNsec); +} + +/** + * @brief This function Configure EPWM generator and get the nearest frequency in edge aligned(up counter type) auto-reload mode + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Frequency Target generator frequency + * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%... + * @return Nearest frequency clock in nano second + * @note Since every two channels, (0 & 1), (2 & 3), shares a prescaler. Call this API to configure EPWM frequency may affect + * existing frequency of other channel. + * @note This function is used for initial stage. + * To change duty cycle later, it should get the configured period value and calculate the new comparator value. + */ +uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle) +{ + uint32_t u32Src; + uint32_t u32EPWMClockSrc; + uint32_t i; + uint32_t u32Prescale = 1U, u32CNR = 0xFFFFU; + + if(epwm == EPWM0) + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM0SEL_Msk; + } + else /* (epwm == EPWM1) */ + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM1SEL_Msk; + } + + if(u32Src == 0U) + { + /* clock source is from PLL clock */ + u32EPWMClockSrc = CLK_GetPLLClockFreq(); + } + else + { + /* clock source is from PCLK */ + SystemCoreClockUpdate(); + if(epwm == EPWM0) + { + u32EPWMClockSrc = CLK_GetPCLK0Freq(); + } + else /* (epwm == EPWM1) */ + { + u32EPWMClockSrc = CLK_GetPCLK1Freq(); + } + } + + for(u32Prescale = 1U; u32Prescale < 0xFFFU; u32Prescale++) /* prescale could be 0~0xFFF */ + { + i = (u32EPWMClockSrc / u32Frequency) / u32Prescale; + /* If target value is larger than CNR, need to use a larger prescaler */ + if(i < (0x10000U)) + { + u32CNR = i; + break; + } + } + /* Store return value here 'cos we're gonna change u16Prescale & u16CNR to the real value to fill into register */ + i = u32EPWMClockSrc / (u32Prescale * u32CNR); + + /* convert to real register value */ + /* every two channels share a prescaler */ + u32Prescale -= 1U; + EPWM_SET_PRESCALER(epwm, u32ChannelNum, u32Prescale); + /* set EPWM to up counter type(edge aligned) and auto-reload mode */ + (epwm)->CTL1 = ((epwm)->CTL1 & ~((EPWM_CTL1_CNTTYPE0_Msk << (u32ChannelNum << 1U))|((1UL << EPWM_CTL1_CNTMODE0_Pos) << u32ChannelNum))); + + u32CNR -= 1U; + EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR); + EPWM_SET_CMR(epwm, u32ChannelNum, u32DutyCycle * (u32CNR + 1U) / 100U); + + (epwm)->WGCTL0 = ((epwm)->WGCTL0 & ~((EPWM_WGCTL0_PRDPCTL0_Msk | EPWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum << 1U))) | \ + ((uint32_t)EPWM_OUTPUT_HIGH << ((u32ChannelNum << 1U) + (uint32_t)EPWM_WGCTL0_ZPCTL0_Pos)); + (epwm)->WGCTL1 = ((epwm)->WGCTL1 & ~((EPWM_WGCTL1_CMPDCTL0_Msk | EPWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum << 1U))) | \ + ((uint32_t)EPWM_OUTPUT_LOW << ((u32ChannelNum << 1U) + (uint32_t)EPWM_WGCTL1_CMPUCTL0_Pos)); + + return(i); +} + +/** + * @brief Start EPWM module + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to start EPWM module. + */ +void EPWM_Start(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->CNTEN |= u32ChannelMask; +} + +/** + * @brief Stop EPWM module + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to stop EPWM module. + */ +void EPWM_Stop(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + uint32_t i; + for(i = 0U; i < EPWM_CHANNEL_NUM; i ++) + { + if(u32ChannelMask & (1UL << i)) + { + (epwm)->PERIOD[i] = 0U; + } + } +} + +/** + * @brief Stop EPWM generation immediately by clear channel enable bit + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to stop EPWM generation immediately by clear channel enable bit. + */ +void EPWM_ForceStop(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->CNTEN &= ~u32ChannelMask; +} + +/** + * @brief Enable selected channel to trigger ADC + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Condition The condition to trigger ADC. Combination of following conditions: + * - \ref EPWM_TRG_ADC_EVEN_ZERO + * - \ref EPWM_TRG_ADC_EVEN_PERIOD + * - \ref EPWM_TRG_ADC_EVEN_ZERO_PERIOD + * - \ref EPWM_TRG_ADC_EVEN_COMPARE_UP + * - \ref EPWM_TRG_ADC_EVEN_COMPARE_DOWN + * - \ref EPWM_TRG_ADC_ODD_ZERO + * - \ref EPWM_TRG_ADC_ODD_PERIOD + * - \ref EPWM_TRG_ADC_ODD_ZERO_PERIOD + * - \ref EPWM_TRG_ADC_ODD_COMPARE_UP + * - \ref EPWM_TRG_ADC_ODD_COMPARE_DOWN + * - \ref EPWM_TRG_ADC_CH_0_FREE_CMP_UP + * - \ref EPWM_TRG_ADC_CH_0_FREE_CMP_DOWN + * - \ref EPWM_TRG_ADC_CH_2_FREE_CMP_UP + * - \ref EPWM_TRG_ADC_CH_2_FREE_CMP_DOWN + * - \ref EPWM_TRG_ADC_CH_4_FREE_CMP_UP + * - \ref EPWM_TRG_ADC_CH_4_FREE_CMP_DOWN + * @return None + * @details This function is used to enable selected channel to trigger ADC. + */ +void EPWM_EnableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + if(u32ChannelNum < 4U) + { + (epwm)->EADCTS0 &= ~((EPWM_EADCTS0_TRGSEL0_Msk) << (u32ChannelNum << 3U)); + (epwm)->EADCTS0 |= ((EPWM_EADCTS0_TRGEN0_Msk | u32Condition) << (u32ChannelNum << 3)); + } + else + { + (epwm)->EADCTS1 &= ~((EPWM_EADCTS1_TRGSEL4_Msk) << ((u32ChannelNum - 4U) << 3U)); + (epwm)->EADCTS1 |= ((EPWM_EADCTS1_TRGEN4_Msk | u32Condition) << ((u32ChannelNum - 4U) << 3U)); + } +} + +/** + * @brief Disable selected channel to trigger ADC + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable selected channel to trigger ADC. + */ +void EPWM_DisableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + if(u32ChannelNum < 4U) + { + (epwm)->EADCTS0 &= ~(EPWM_EADCTS0_TRGEN0_Msk << (u32ChannelNum << 3U)); + } + else + { + (epwm)->EADCTS1 &= ~(EPWM_EADCTS1_TRGEN4_Msk << ((u32ChannelNum - 4U) << 3U)); + } +} + +/** + * @brief Enable and configure trigger ADC prescale + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @param[in] u32Prescale ADC prescale. Valid values are between 0 to 0xF. + * @param[in] u32PrescaleCnt ADC prescale counter. Valid values are between 0 to 0xF. + * @retval 0 Success. + * @retval -1 Failed. + * @details This function is used to enable and configure trigger ADC prescale. + * @note User can configure only when ADC trigger prescale is disabled. + * @note ADC prescale counter must less than ADC prescale. + */ +int32_t EPWM_EnableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Prescale, uint32_t u32PrescaleCnt) +{ + /* User can write only when PSCENn(n = 0 ~ 5) is 0 */ + if ((epwm)->EADCPSCCTL & (1UL << u32ChannelNum)) + return (-1); + + if(u32ChannelNum < 4UL) + { + (epwm)->EADCPSC0 = ((epwm)->EADCPSC0 & ~((EPWM_EADCPSC0_EADCPSC0_Msk) << (u32ChannelNum << 3))) | \ + (u32Prescale << (u32ChannelNum << 3)); + (epwm)->EADCPSCNT0 = ((epwm)->EADCPSCNT0 & ~((EPWM_EADCPSCNT0_PSCNT0_Msk) << (u32ChannelNum << 3))) | \ + (u32PrescaleCnt << (u32ChannelNum << 3)); + } + else + { + (epwm)->EADCPSC1 = ((epwm)->EADCPSC1 & ~((EPWM_EADCPSC1_EADCPSC4_Msk) << ((u32ChannelNum - 4UL) << 3))) | \ + (u32Prescale << ((u32ChannelNum - 4UL) << 3)); + (epwm)->EADCPSCNT1 = ((epwm)->EADCPSCNT1 & ~((EPWM_EADCPSCNT1_PSCNT4_Msk) << ((u32ChannelNum - 4UL) << 3))) | \ + (u32PrescaleCnt << ((u32ChannelNum - 4UL) << 3)); + } + + (epwm)->EADCPSCCTL |= EPWM_EADCPSCCTL_PSCEN0_Msk << u32ChannelNum; + + return 0; +} + +/** + * @brief Disable Trigger ADC prescale function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable trigger ADC prescale. + */ +void EPWM_DisableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->EADCPSCCTL &= ~(EPWM_EADCPSCCTL_PSCEN0_Msk << u32ChannelNum); +} + +/** + * @brief Clear selected channel trigger ADC flag + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Condition This parameter is not used + * @return None + * @details This function is used to clear selected channel trigger ADC flag. + */ +void EPWM_ClearADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + (epwm)->STATUS = (EPWM_STATUS_EADCTRGF0_Msk << u32ChannelNum); +} + +/** + * @brief Get selected channel trigger ADC flag + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @retval 0 The specified channel trigger ADC to start of conversion flag is not set + * @retval 1 The specified channel trigger ADC to start of conversion flag is set + * @details This function is used to get EPWM trigger ADC to start of conversion flag for specified channel. + */ +uint32_t EPWM_GetADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((epwm)->STATUS & (EPWM_STATUS_EADCTRGF0_Msk << u32ChannelNum))?1UL:0UL); +} + +/** + * @brief Enable selected channel to trigger DAC + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Condition The condition to trigger DAC. Combination of following conditions: + * - \ref EPWM_TRIGGER_DAC_ZERO + * - \ref EPWM_TRIGGER_DAC_PERIOD + * - \ref EPWM_TRIGGER_DAC_COMPARE_UP + * - \ref EPWM_TRIGGER_DAC_COMPARE_DOWN + * @return None + * @details This function is used to enable selected channel to trigger DAC. + */ +void EPWM_EnableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + (epwm)->DACTRGEN |= (u32Condition << u32ChannelNum); +} + +/** + * @brief Disable selected channel to trigger DAC + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable selected channel to trigger DAC. + */ +void EPWM_DisableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->DACTRGEN &= ~((EPWM_TRIGGER_DAC_ZERO | EPWM_TRIGGER_DAC_PERIOD | EPWM_TRIGGER_DAC_COMPARE_UP | \ + EPWM_TRIGGER_DAC_COMPARE_DOWN) << u32ChannelNum); +} + +/** + * @brief Clear selected channel trigger DAC flag + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. This parameter is not used + * @param[in] u32Condition The condition to trigger DAC. This parameter is not used + * @return None + * @details This function is used to clear selected channel trigger DAC flag. + */ +void EPWM_ClearDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + (epwm)->STATUS = EPWM_STATUS_DACTRGF_Msk; +} + +/** + * @brief Get selected channel trigger DAC flag + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. This parameter is not used + * @retval 0 The specified channel trigger DAC to start of conversion flag is not set + * @retval 1 The specified channel trigger DAC to start of conversion flag is set + * @details This function is used to get selected channel trigger DAC flag. + */ +uint32_t EPWM_GetDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((epwm)->STATUS & EPWM_STATUS_DACTRGF_Msk)?1UL:0UL); +} + +/** + * @brief This function enable fault brake of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * @param[in] u32LevelMask Output high or low while fault brake occurs, each bit represent the level of a channel + * while fault brake occurs. Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32BrakeSource Fault brake source, could be one of following source + * - \ref EPWM_FB_EDGE_ADCRM + * - \ref EPWM_FB_EDGE_ACMP0 + * - \ref EPWM_FB_EDGE_ACMP1 + * - \ref EPWM_FB_EDGE_BKP0 + * - \ref EPWM_FB_EDGE_BKP1 + * - \ref EPWM_FB_EDGE_SYS_CSS + * - \ref EPWM_FB_EDGE_SYS_BOD + * - \ref EPWM_FB_EDGE_SYS_RAM + * - \ref EPWM_FB_EDGE_SYS_COR + * - \ref EPWM_FB_LEVEL_ADCRM + * - \ref EPWM_FB_LEVEL_ACMP0 + * - \ref EPWM_FB_LEVEL_ACMP1 + * - \ref EPWM_FB_LEVEL_BKP0 + * - \ref EPWM_FB_LEVEL_BKP1 + * - \ref EPWM_FB_LEVEL_SYS_CSS + * - \ref EPWM_FB_LEVEL_SYS_BOD + * - \ref EPWM_FB_LEVEL_SYS_RAM + * - \ref EPWM_FB_LEVEL_SYS_COR + * @return None + * @details This function is used to enable fault brake of selected channel(s). + * The write-protection function should be disabled before using this function. + */ +void EPWM_EnableFaultBrake(EPWM_T *epwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource) +{ + uint32_t i; + + for(i = 0U; i < EPWM_CHANNEL_NUM; i ++) + { + if(u32ChannelMask & (1UL << i)) + { + if((u32BrakeSource == EPWM_FB_EDGE_SYS_CSS) || (u32BrakeSource == EPWM_FB_EDGE_SYS_BOD) || \ + (u32BrakeSource == EPWM_FB_EDGE_SYS_RAM) || (u32BrakeSource == EPWM_FB_EDGE_SYS_COR) || \ + (u32BrakeSource == EPWM_FB_LEVEL_SYS_CSS) || (u32BrakeSource == EPWM_FB_LEVEL_SYS_BOD) || \ + (u32BrakeSource == EPWM_FB_LEVEL_SYS_RAM) || (u32BrakeSource == EPWM_FB_LEVEL_SYS_COR)) + { + (epwm)->BRKCTL[i >> 1U] |= (u32BrakeSource & (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_BRKCTL0_1_SYSLBEN_Msk)); + (epwm)->FAILBRK |= (u32BrakeSource & 0xFU); + } + else + { + (epwm)->BRKCTL[i >> 1U] |= u32BrakeSource; + } + } + + if(u32LevelMask & (1UL << i)) + { + if((i & 0x1U) == 0U) + { + /* set brake action as high level for even channel */ + (epwm)->BRKCTL[i >> 1] &= ~EPWM_BRKCTL0_1_BRKAEVEN_Msk; + (epwm)->BRKCTL[i >> 1] |= ((3U) << EPWM_BRKCTL0_1_BRKAEVEN_Pos); + } + else + { + /* set brake action as high level for odd channel */ + (epwm)->BRKCTL[i >> 1] &= ~EPWM_BRKCTL0_1_BRKAODD_Msk; + (epwm)->BRKCTL[i >> 1] |= ((3U) << EPWM_BRKCTL0_1_BRKAODD_Pos); + } + } + else + { + if((i & 0x1U) == 0U) + { + /* set brake action as low level for even channel */ + (epwm)->BRKCTL[i >> 1U] &= ~EPWM_BRKCTL0_1_BRKAEVEN_Msk; + (epwm)->BRKCTL[i >> 1U] |= ((2U) << EPWM_BRKCTL0_1_BRKAEVEN_Pos); + } + else + { + /* set brake action as low level for odd channel */ + (epwm)->BRKCTL[i >> 1U] &= ~EPWM_BRKCTL0_1_BRKAODD_Msk; + (epwm)->BRKCTL[i >> 1U] |= ((2U) << EPWM_BRKCTL0_1_BRKAODD_Pos); + } + } + } +} + +/** + * @brief Enable capture of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to enable capture of selected channel(s). + */ +void EPWM_EnableCapture(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->CAPINEN |= u32ChannelMask; + (epwm)->CAPCTL |= u32ChannelMask; +} + +/** + * @brief Disable capture of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to disable capture of selected channel(s). + */ +void EPWM_DisableCapture(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->CAPINEN &= ~u32ChannelMask; + (epwm)->CAPCTL &= ~u32ChannelMask; +} + +/** + * @brief Enables EPWM output generation of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output... + * @return None + * @details This function is used to enable EPWM output generation of selected channel(s). + */ +void EPWM_EnableOutput(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->POEN |= u32ChannelMask; +} + +/** + * @brief Disables EPWM output generation of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output... + * @return None + * @details This function is used to disable EPWM output generation of selected channel(s). + */ +void EPWM_DisableOutput(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->POEN &= ~u32ChannelMask; +} + +/** + * @brief Enables PDMA transfer of selected channel for EPWM capture + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. + * @param[in] u32RisingFirst The capture order is rising, falling first. Every two channels share the same setting. Valid values are TRUE and FALSE. + * @param[in] u32Mode Captured data transferred by PDMA interrupt type. It could be either + * - \ref EPWM_CAPTURE_PDMA_RISING_LATCH + * - \ref EPWM_CAPTURE_PDMA_FALLING_LATCH + * - \ref EPWM_CAPTURE_PDMA_RISING_FALLING_LATCH + * @return None + * @details This function is used to enable PDMA transfer of selected channel(s) for EPWM capture. + * @note This function can only selects even or odd channel of pairs to do PDMA transfer. + */ +void EPWM_EnablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode) +{ + uint32_t u32IsOddCh; + u32IsOddCh = u32ChannelNum & 0x1U; + (epwm)->PDMACTL = ((epwm)->PDMACTL & ~((EPWM_PDMACTL_CHSEL0_1_Msk | EPWM_PDMACTL_CAPORD0_1_Msk | EPWM_PDMACTL_CAPMOD0_1_Msk) << ((u32ChannelNum >> 1U) << 3U))) | \ + (((u32IsOddCh << EPWM_PDMACTL_CHSEL0_1_Pos) | (u32RisingFirst << EPWM_PDMACTL_CAPORD0_1_Pos) | \ + u32Mode | EPWM_PDMACTL_CHEN0_1_Msk) << ((u32ChannelNum >> 1U) << 3U)); +} + +/** + * @brief Disables PDMA transfer of selected channel for EPWM capture + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. + * @return None + * @details This function is used to enable PDMA transfer of selected channel(s) for EPWM capture. + */ +void EPWM_DisablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->PDMACTL &= ~(EPWM_PDMACTL_CHEN0_1_Msk << ((u32ChannelNum >> 1U) << 3U)); +} + +/** + * @brief Enable Dead zone of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Duration Dead zone length in EPWM clock count, valid values are between 0~0xFFF, but 0 means there is no Dead zone. + * @return None + * @details This function is used to enable Dead zone of selected channel. + * The write-protection function should be disabled before using this function. + * @note Every two channels share the same setting. + */ +void EPWM_EnableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Duration) +{ + /* every two channels share the same setting */ + (epwm)->DTCTL[(u32ChannelNum) >> 1U] &= ~EPWM_DTCTL0_1_DTCNT_Msk; + (epwm)->DTCTL[(u32ChannelNum) >> 1U] |= EPWM_DTCTL0_1_DTEN_Msk | u32Duration; +} + +/** + * @brief Disable Dead zone of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable Dead zone of selected channel. + * The write-protection function should be disabled before using this function. + */ +void EPWM_DisableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + /* every two channels shares the same setting */ + (epwm)->DTCTL[(u32ChannelNum) >> 1U] &= ~EPWM_DTCTL0_1_DTEN_Msk; +} + +/** + * @brief Enable capture interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref EPWM_CAPTURE_INT_RISING_LATCH + * - \ref EPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to enable capture interrupt of selected channel. + */ +void EPWM_EnableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (epwm)->CAPIEN |= (u32Edge << u32ChannelNum); +} + +/** + * @brief Disable capture interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref EPWM_CAPTURE_INT_RISING_LATCH + * - \ref EPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to disable capture interrupt of selected channel. + */ +void EPWM_DisableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (epwm)->CAPIEN &= ~(u32Edge << u32ChannelNum); +} + +/** + * @brief Clear capture interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref EPWM_CAPTURE_INT_RISING_LATCH + * - \ref EPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to clear capture interrupt of selected channel. + */ +void EPWM_ClearCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (epwm)->CAPIF = (u32Edge << u32ChannelNum); +} + +/** + * @brief Get capture interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @retval 0 No capture interrupt + * @retval 1 Rising edge latch interrupt + * @retval 2 Falling edge latch interrupt + * @retval 3 Rising and falling latch interrupt + * @details This function is used to get capture interrupt of selected channel. + */ +uint32_t EPWM_GetCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((((epwm)->CAPIF & (EPWM_CAPIF_CFLIF0_Msk << u32ChannelNum)) ? 1UL : 0UL) << 1) | \ + (((epwm)->CAPIF & (EPWM_CAPIF_CRLIF0_Msk << u32ChannelNum)) ? 1UL : 0UL)); +} +/** + * @brief Enable duty interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32IntDutyType Duty interrupt type, could be either + * - \ref EPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP + * - \ref EPWM_DUTY_INT_UP_COUNT_MATCH_CMP + * @return None + * @details This function is used to enable duty interrupt of selected channel. + */ +void EPWM_EnableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType) +{ + (epwm)->INTEN0 |= (u32IntDutyType << u32ChannelNum); +} + +/** + * @brief Disable duty interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable duty interrupt of selected channel. + */ +void EPWM_DisableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTEN0 &= ~((uint32_t)(EPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP | EPWM_DUTY_INT_UP_COUNT_MATCH_CMP) << u32ChannelNum); +} + +/** + * @brief Clear duty interrupt flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear duty interrupt flag of selected channel. + */ +void EPWM_ClearDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTSTS0 = (EPWM_INTSTS0_CMPUIF0_Msk | EPWM_INTSTS0_CMPDIF0_Msk) << u32ChannelNum; +} + +/** + * @brief Get duty interrupt flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Duty interrupt flag of specified channel + * @retval 0 Duty interrupt did not occur + * @retval 1 Duty interrupt occurred + * @details This function is used to get duty interrupt flag of selected channel. + */ +uint32_t EPWM_GetDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return ((((epwm)->INTSTS0 & ((EPWM_INTSTS0_CMPDIF0_Msk | EPWM_INTSTS0_CMPUIF0_Msk) << u32ChannelNum))) ? 1UL : 0UL); +} + +/** + * @brief This function enable fault brake interrupt + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32BrakeSource Fault brake source. + * - \ref EPWM_FB_EDGE + * - \ref EPWM_FB_LEVEL + * @return None + * @details This function is used to enable fault brake interrupt. + * The write-protection function should be disabled before using this function. + * @note Every two channels share the same setting. + */ +void EPWM_EnableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource) +{ + (epwm)->INTEN1 |= (0x7UL << u32BrakeSource); +} + +/** + * @brief This function disable fault brake interrupt + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32BrakeSource Fault brake source. + * - \ref EPWM_FB_EDGE + * - \ref EPWM_FB_LEVEL + * @return None + * @details This function is used to disable fault brake interrupt. + * The write-protection function should be disabled before using this function. + * @note Every two channels share the same setting. + */ +void EPWM_DisableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource) +{ + (epwm)->INTEN1 &= ~(0x7UL << u32BrakeSource); +} + +/** + * @brief This function clear fault brake interrupt of selected source + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32BrakeSource Fault brake source. + * - \ref EPWM_FB_EDGE + * - \ref EPWM_FB_LEVEL + * @return None + * @details This function is used to clear fault brake interrupt of selected source. + * The write-protection function should be disabled before using this function. + */ +void EPWM_ClearFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource) +{ + (epwm)->INTSTS1 = (0x3fUL << u32BrakeSource); +} + +/** + * @brief This function get fault brake interrupt flag of selected source + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32BrakeSource Fault brake source, could be either + * - \ref EPWM_FB_EDGE + * - \ref EPWM_FB_LEVEL + * @return Fault brake interrupt flag of specified source + * @retval 0 Fault brake interrupt did not occurred + * @retval 1 Fault brake interrupt occurred + * @details This function is used to get fault brake interrupt flag of selected source. + */ +uint32_t EPWM_GetFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource) +{ + return (((epwm)->INTSTS1 & (0x3fUL << u32BrakeSource)) ? 1UL : 0UL); +} + +/** + * @brief Enable period interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32IntPeriodType Period interrupt type. This parameter is not used. + * @return None + * @details This function is used to enable period interrupt of selected channel. + */ +void EPWM_EnablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType) +{ + (epwm)->INTEN0 |= ((1UL << EPWM_INTEN0_PIEN0_Pos) << u32ChannelNum); +} + +/** + * @brief Disable period interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable period interrupt of selected channel. + */ +void EPWM_DisablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTEN0 &= ~((1UL << EPWM_INTEN0_PIEN0_Pos) << u32ChannelNum); +} + +/** + * @brief Clear period interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear period interrupt of selected channel. + */ +void EPWM_ClearPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTSTS0 = ((1UL << EPWM_INTSTS0_PIF0_Pos) << u32ChannelNum); +} + +/** + * @brief Get period interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Period interrupt flag of specified channel + * @retval 0 Period interrupt did not occur + * @retval 1 Period interrupt occurred + * @details This function is used to get period interrupt of selected channel. + */ +uint32_t EPWM_GetPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return ((((epwm)->INTSTS0 & ((1UL << EPWM_INTSTS0_PIF0_Pos) << u32ChannelNum))) ? 1UL : 0UL); +} + +/** + * @brief Enable zero interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to enable zero interrupt of selected channel. + */ +void EPWM_EnableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTEN0 |= ((1UL << EPWM_INTEN0_ZIEN0_Pos) << u32ChannelNum); +} + +/** + * @brief Disable zero interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable zero interrupt of selected channel. + */ +void EPWM_DisableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTEN0 &= ~((1UL << EPWM_INTEN0_ZIEN0_Pos) << u32ChannelNum); +} + +/** + * @brief Clear zero interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear zero interrupt of selected channel. + */ +void EPWM_ClearZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTSTS0 = ((1UL << EPWM_INTEN0_ZIEN0_Pos) << u32ChannelNum); +} + +/** + * @brief Get zero interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Zero interrupt flag of specified channel + * @retval 0 Zero interrupt did not occur + * @retval 1 Zero interrupt occurred + * @details This function is used to get zero interrupt of selected channel. + */ +uint32_t EPWM_GetZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return ((((epwm)->INTSTS0 & ((1UL << EPWM_INTEN0_ZIEN0_Pos) << u32ChannelNum))) ? 1UL : 0UL); +} + +/** + * @brief Enable interrupt flag accumulator of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32IntFlagCnt Interrupt flag counter. Valid values are between 0~65535. + * @param[in] u32IntAccSrc Interrupt flag accumulator source selection. + * - \ref EPWM_IFA_ZERO_POINT + * - \ref EPWM_IFA_PERIOD_POINT + * - \ref EPWM_IFA_COMPARE_UP_COUNT_POINT + * - \ref EPWM_IFA_COMPARE_DOWN_COUNT_POINT + * @return None + * @details This function is used to enable interrupt flag accumulator of selected channel. + */ +void EPWM_EnableAcc(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc) +{ + (epwm)->IFA[u32ChannelNum] = (((epwm)->IFA[u32ChannelNum] & ~((EPWM_IFA0_IFACNT_Msk | EPWM_IFA0_IFASEL_Msk))) | \ + (EPWM_IFA0_IFAEN_Msk | (u32IntAccSrc << EPWM_IFA0_IFASEL_Pos) | u32IntFlagCnt) ); +} + +/** + * @brief Disable interrupt flag accumulator of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to Disable interrupt flag accumulator of selected channel. + */ +void EPWM_DisableAcc(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->IFA[u32ChannelNum] = ((epwm)->IFA[u32ChannelNum] & ~(EPWM_IFA0_IFAEN_Msk)); +} + +/** + * @brief Enable interrupt flag accumulator interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to enable interrupt flag accumulator interrupt of selected channel. + */ +void EPWM_EnableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->AINTEN |= (1UL << (u32ChannelNum)); +} + +/** + * @brief Disable interrupt flag accumulator interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable interrupt flag accumulator interrupt of selected channel. + */ +void EPWM_DisableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->AINTEN &= ~(1UL << (u32ChannelNum)); +} + +/** + * @brief Clear interrupt flag accumulator interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear interrupt flag accumulator interrupt of selected channel. + */ +void EPWM_ClearAccInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->AINTSTS = (1UL << (u32ChannelNum)); +} + +/** + * @brief Get interrupt flag accumulator interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @retval 0 Accumulator interrupt did not occur + * @retval 1 Accumulator interrupt occurred + * @details This function is used to Get interrupt flag accumulator interrupt of selected channel. + */ +uint32_t EPWM_GetAccInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((epwm)->AINTSTS & (1UL << (u32ChannelNum))) ? 1UL : 0UL); +} + +/** + * @brief Enable accumulator PDMA of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to enable accumulator interrupt trigger PDMA of selected channel. + */ +void EPWM_EnableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->APDMACTL |= (1UL << (u32ChannelNum)); +} + +/** + * @brief Disable accumulator PDMA of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable accumulator interrupt trigger PDMA of selected channel. + */ +void EPWM_DisableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->APDMACTL &= ~(1UL << (u32ChannelNum)); +} + +/** + * @brief Enable interrupt flag accumulator stop mode of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to enable interrupt flag accumulator stop mode of selected channel. + */ +void EPWM_EnableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->IFA[u32ChannelNum] |= EPWM_IFA0_STPMOD_Msk; +} + +/** + * @brief Disable interrupt flag accumulator stop mode of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable interrupt flag accumulator stop mode of selected channel. + */ +void EPWM_DisableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->IFA[u32ChannelNum] &= ~EPWM_IFA0_STPMOD_Msk; +} + +/** + * @brief Clear free trigger duty interrupt flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear free trigger duty interrupt flag of selected channel. + */ +void EPWM_ClearFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FTCI = ((EPWM_FTCI_FTCMU0_Msk | EPWM_FTCI_FTCMD0_Msk) << (u32ChannelNum >> 1U)); +} + +/** + * @brief Get free trigger duty interrupt flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Duty interrupt flag of specified channel + * @retval 0 Free trigger duty interrupt did not occur + * @retval 1 Free trigger duty interrupt occurred + * @details This function is used to get free trigger duty interrupt flag of selected channel. + */ +uint32_t EPWM_GetFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((epwm)->FTCI & ((EPWM_FTCI_FTCMU0_Msk | EPWM_FTCI_FTCMD0_Msk) << (u32ChannelNum >> 1U))) ? 1UL : 0UL); +} + +/** + * @brief Enable load mode of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32LoadMode EPWM counter loading mode. + * - \ref EPWM_LOAD_MODE_IMMEDIATE + * - \ref EPWM_LOAD_MODE_WINDOW + * - \ref EPWM_LOAD_MODE_CENTER + * @return None + * @details This function is used to enable load mode of selected channel. + */ +void EPWM_EnableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode) +{ + (epwm)->CTL0 |= (u32LoadMode << u32ChannelNum); +} + +/** + * @brief Disable load mode of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32LoadMode EPWM counter loading mode. + * - \ref EPWM_LOAD_MODE_IMMEDIATE + * - \ref EPWM_LOAD_MODE_WINDOW + * - \ref EPWM_LOAD_MODE_CENTER + * @return None + * @details This function is used to disable load mode of selected channel. + */ +void EPWM_DisableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode) +{ + (epwm)->CTL0 &= ~(u32LoadMode << u32ChannelNum); +} + +/** + * @brief Configure synchronization phase of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32SyncSrc EPWM synchronize source selection. + * - \ref EPWM_SYNC_OUT_FROM_SYNCIN_SWSYNC + * - \ref EPWM_SYNC_OUT_FROM_COUNT_TO_ZERO + * - \ref EPWM_SYNC_OUT_FROM_COUNT_TO_COMPARATOR + * - \ref EPWM_SYNC_OUT_DISABLE + * @param[in] u32Direction Phase direction. Control EPWM counter count decrement or increment after synchronizing. + * - \ref EPWM_PHS_DIR_DECREMENT + * - \ref EPWM_PHS_DIR_INCREMENT + * @param[in] u32StartPhase Synchronous start phase value. Valid values are between 0~65535. + * @return None + * @details This function is used to configure synchronization phase of selected channel. + * @note Every two channels share the same setting. + */ +void EPWM_ConfigSyncPhase(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase) +{ + /* every two channels shares the same setting */ + u32ChannelNum >>= 1U; + (epwm)->SYNC = (((epwm)->SYNC & ~(((3UL << EPWM_SYNC_SINSRC0_Pos) << (u32ChannelNum << 1U)) | ((1UL << EPWM_SYNC_PHSDIR0_Pos) << u32ChannelNum))) | \ + (u32Direction << EPWM_SYNC_PHSDIR0_Pos << u32ChannelNum) | ((u32SyncSrc << EPWM_SYNC_SINSRC0_Pos) << (u32ChannelNum << 1U))); + (epwm)->PHS[(u32ChannelNum)] = u32StartPhase; +} + + +/** + * @brief Enable SYNC phase of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to enable SYNC phase of selected channel(s). + * @note Every two channels share the same setting. + */ +void EPWM_EnableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + uint32_t i; + for(i = 0U; i < EPWM_CHANNEL_NUM; i ++) + { + if(u32ChannelMask & (1UL << i)) + { + (epwm)->SYNC |= ((1UL << EPWM_SYNC_PHSEN0_Pos) << (i >> 1U)); + } + } +} + +/** + * @brief Disable SYNC phase of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to disable SYNC phase of selected channel(s). + * @note Every two channels share the same setting. + */ +void EPWM_DisableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + uint32_t i; + for(i = 0U; i < EPWM_CHANNEL_NUM; i ++) + { + if(u32ChannelMask & (1UL << i)) + { + (epwm)->SYNC &= ~((1UL << EPWM_SYNC_PHSEN0_Pos) << (i >> 1U)); + } + } +} + +/** + * @brief Enable EPWM SYNC_IN noise filter function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ClkCnt SYNC Edge Detector Filter Count. This controls the counter number of edge detector. + * The valid value is 0~7. + * @param[in] u32ClkDivSel SYNC Edge Detector Filter Clock Selection. + * - \ref EPWM_NF_CLK_DIV_1 + * - \ref EPWM_NF_CLK_DIV_2 + * - \ref EPWM_NF_CLK_DIV_4 + * - \ref EPWM_NF_CLK_DIV_8 + * - \ref EPWM_NF_CLK_DIV_16 + * - \ref EPWM_NF_CLK_DIV_32 + * - \ref EPWM_NF_CLK_DIV_64 + * - \ref EPWM_NF_CLK_DIV_128 + * @return None + * @details This function is used to enable EPWM SYNC_IN noise filter function. + */ +void EPWM_EnableSyncNoiseFilter(EPWM_T *epwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel) +{ + (epwm)->SYNC = ((epwm)->SYNC & ~(EPWM_SYNC_SFLTCNT_Msk | EPWM_SYNC_SFLTCSEL_Msk)) | \ + ((u32ClkCnt << EPWM_SYNC_SFLTCNT_Pos) | (u32ClkDivSel << EPWM_SYNC_SFLTCSEL_Pos) | EPWM_SYNC_SNFLTEN_Msk); +} + +/** + * @brief Disable EPWM SYNC_IN noise filter function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @return None + * @details This function is used to Disable EPWM SYNC_IN noise filter function. + */ +void EPWM_DisableSyncNoiseFilter(EPWM_T *epwm) +{ + (epwm)->SYNC &= ~EPWM_SYNC_SNFLTEN_Msk; +} + +/** + * @brief Enable EPWM SYNC input pin inverse function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @return None + * @details This function is used to enable EPWM SYNC input pin inverse function. + */ +void EPWM_EnableSyncPinInverse(EPWM_T *epwm) +{ + (epwm)->SYNC |= EPWM_SYNC_SINPINV_Msk; +} + +/** + * @brief Disable EPWM SYNC input pin inverse function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @return None + * @details This function is used to Disable EPWM SYNC input pin inverse function. + */ +void EPWM_DisableSyncPinInverse(EPWM_T *epwm) +{ + (epwm)->SYNC &= (~EPWM_SYNC_SINPINV_Msk); +} + +/** + * @brief Set EPWM clock source + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32ClkSrcSel EPWM external clock source. + * - \ref EPWM_CLKSRC_EPWM_CLK + * - \ref EPWM_CLKSRC_TIMER0 + * - \ref EPWM_CLKSRC_TIMER1 + * - \ref EPWM_CLKSRC_TIMER2 + * - \ref EPWM_CLKSRC_TIMER3 + * @return None + * @details This function is used to set EPWM clock source. + * @note Every two channels share the same setting. + * @note If the clock source of EPWM counter is selected from TIMERn interrupt events, the TRGEPWM(TIMERn_TRGCTL[1], n=0,1..3) bit must be set as 1. + */ +void EPWM_SetClockSource(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel) +{ + (epwm)->CLKSRC = ((epwm)->CLKSRC & ~(EPWM_CLKSRC_ECLKSRC0_Msk << ((u32ChannelNum >> 1U) << 3U))) | \ + (u32ClkSrcSel << ((u32ChannelNum >> 1U) << 3U)); +} + +/** + * @brief Enable EPWM brake noise filter function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @param[in] u32ClkCnt SYNC Edge Detector Filter Count. This controls the counter number of edge detector + * @param[in] u32ClkDivSel SYNC Edge Detector Filter Clock Selection. + * - \ref EPWM_NF_CLK_DIV_1 + * - \ref EPWM_NF_CLK_DIV_2 + * - \ref EPWM_NF_CLK_DIV_4 + * - \ref EPWM_NF_CLK_DIV_8 + * - \ref EPWM_NF_CLK_DIV_16 + * - \ref EPWM_NF_CLK_DIV_32 + * - \ref EPWM_NF_CLK_DIV_64 + * - \ref EPWM_NF_CLK_DIV_128 + * @return None + * @details This function is used to enable EPWM brake noise filter function. + */ +void EPWM_EnableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel) +{ + (epwm)->BNF = ((epwm)->BNF & ~((EPWM_BNF_BRK0FCNT_Msk | EPWM_BNF_BRK0NFSEL_Msk) << (u32BrakePinNum << 3U))) | \ + (((u32ClkCnt << EPWM_BNF_BRK0FCNT_Pos) | (u32ClkDivSel << EPWM_BNF_BRK0NFSEL_Pos) | EPWM_BNF_BRK0NFEN_Msk) << (u32BrakePinNum << 3U)); +} + +/** + * @brief Disable EPWM brake noise filter function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @return None + * @details This function is used to disable EPWM brake noise filter function. + */ +void EPWM_DisableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum) +{ + (epwm)->BNF &= ~(EPWM_BNF_BRK0NFEN_Msk << (u32BrakePinNum << 3U)); +} + +/** + * @brief Enable EPWM brake pin inverse function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @return None + * @details This function is used to enable EPWM brake pin inverse function. + */ +void EPWM_EnableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum) +{ + (epwm)->BNF |= (EPWM_BNF_BRK0PINV_Msk << (u32BrakePinNum << 3U)); +} + +/** + * @brief Disable EPWM brake pin inverse function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @return None + * @details This function is used to disable EPWM brake pin inverse function. + */ +void EPWM_DisableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum) +{ + (epwm)->BNF &= ~(EPWM_BNF_BRK0PINV_Msk << (u32BrakePinNum * (uint32_t)EPWM_BNF_BRK1NFEN_Pos)); +} + +/** + * @brief Set EPWM brake pin source + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @param[in] u32SelAnotherModule Select to another module. Valid values are TRUE or FALSE. + * @return None + * @details This function is used to set EPWM brake pin source. + */ +void EPWM_SetBrakePinSource(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule) +{ + (epwm)->BNF = ((epwm)->BNF & ~(EPWM_BNF_BK0SRC_Msk << (u32BrakePinNum << 3U))) | (u32SelAnotherModule << ((uint32_t)EPWM_BNF_BK0SRC_Pos + (u32BrakePinNum << 3U))); +} + +/** + * @brief Set EPWM leading edge blanking function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32TrigSrcSel Leading edge blanking source selection. + * - \ref EPWM_LEBCTL_SRCEN0 + * - \ref EPWM_LEBCTL_SRCEN2 + * - \ref EPWM_LEBCTL_SRCEN4 + * - \ref EPWM_LEBCTL_SRCEN0_2 + * - \ref EPWM_LEBCTL_SRCEN0_4 + * - \ref EPWM_LEBCTL_SRCEN2_4 + * - \ref EPWM_LEBCTL_SRCEN0_2_4 + * @param[in] u32TrigType Leading edge blanking trigger type. + * - \ref EPWM_LEBCTL_TRGTYPE_RISING + * - \ref EPWM_LEBCTL_TRGTYPE_FALLING + * - \ref EPWM_LEBCTL_TRGTYPE_RISING_OR_FALLING + * @param[in] u32BlankingCnt Leading Edge Blanking Counter. Valid values are between 1~512. + This counter value decides leading edge blanking window size, and this counter clock base is ECLK. + * @param[in] u32BlankingEnable Enable EPWM leading edge blanking function. Valid values are TRUE (ENABLE) or FALSE (DISABLE). + * - \ref FALSE + * - \ref TRUE + * @return None + * @details This function is used to configure EPWM leading edge blanking function that blank the false trigger from ACMP brake source which may cause by EPWM output transition. + * @note EPWM leading edge blanking function is only used for brake source from ACMP. + */ +void EPWM_SetLeadingEdgeBlanking(EPWM_T *epwm, uint32_t u32TrigSrcSel, uint32_t u32TrigType, uint32_t u32BlankingCnt, uint32_t u32BlankingEnable) +{ + (epwm)->LEBCTL = (u32TrigType) | (u32TrigSrcSel) | (u32BlankingEnable); + /* Blanking window size = LEBCNT + 1, so LEBCNT = u32BlankingCnt - 1 */ + (epwm)->LEBCNT = (u32BlankingCnt) - 1U; +} + +/** + * @brief Get the time-base counter reached its maximum value flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Count to max interrupt flag of specified channel + * @retval 0 Count to max interrupt did not occur + * @retval 1 Count to max interrupt occurred + * @details This function is used to get the time-base counter reached its maximum value flag of selected channel. + */ +uint32_t EPWM_GetWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((epwm)->STATUS & (EPWM_STATUS_CNTMAXF0_Msk << u32ChannelNum)) ? 1UL : 0UL); +} + +/** + * @brief Clear the time-base counter reached its maximum value flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear the time-base counter reached its maximum value flag of selected channel. + */ +void EPWM_ClearWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->STATUS = (EPWM_STATUS_CNTMAXF0_Msk << u32ChannelNum); +} + +/** + * @brief Enable fault detect of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @param[in] u32AfterPrescaler Fault Detect Clock Source is from prescaler output. Valid values are TRUE (after prescaler) or FALSE (before prescaler). + * @param[in] u32ClkSel Fault Detect Clock Select. + * - \ref EPWM_FDCTL_FDCKSEL_CLK_DIV_1 + * - \ref EPWM_FDCTL_FDCKSEL_CLK_DIV_2 + * - \ref EPWM_FDCTL_FDCKSEL_CLK_DIV_4 + * - \ref EPWM_FDCTL_FDCKSEL_CLK_DIV_8 + * @return None + * @details This function is used to enable fault detect of selected channel. + */ +void EPWM_EnableFaultDetect(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32AfterPrescaler, uint32_t u32ClkSel) +{ + (epwm)->FDEN = ((epwm)->FDEN & ~(EPWM_FDEN_FDCKS0_Msk << (u32ChannelNum))) | \ + ((EPWM_FDEN_FDEN0_Msk | ((u32AfterPrescaler) << EPWM_FDEN_FDCKS0_Pos)) << (u32ChannelNum)); + (epwm)->FDCTL[(u32ChannelNum)] = ((epwm)->FDCTL[(u32ChannelNum)] & ~EPWM_FDCTL0_FDCKSEL_Msk) | (u32ClkSel); +} + +/** + * @brief Disable fault detect of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @return None + * @details This function is used to disable fault detect of selected channel. + */ +void EPWM_DisableFaultDetect(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FDEN &= ~(EPWM_FDEN_FDEN0_Msk << (u32ChannelNum)); +} + +/** + * @brief Enable fault detect output of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @return None + * @details This function is used to enable fault detect output of selected channel. + */ +void EPWM_EnableFaultDetectOutput(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FDEN &= ~(EPWM_FDEN_FDODIS0_Msk << (u32ChannelNum)); +} + +/** + * @brief Disable fault detect output of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @return None + * @details This function is used to disable fault detect output of selected channel. + */ +void EPWM_DisableFaultDetectOutput(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FDEN |= (EPWM_FDEN_FDODIS0_Msk << (u32ChannelNum)); +} + +/** + * @brief Enable fault detect deglitch function of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @param[in] u32DeglitchSmpCycle Deglitch Sampling Cycle. Valid values are between 0~7. + * @return None + * @details This function is used to enable fault detect deglitch function of selected channel. + */ +void EPWM_EnableFaultDetectDeglitch(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32DeglitchSmpCycle) +{ + (epwm)->FDCTL[(u32ChannelNum)] = ((epwm)->FDCTL[(u32ChannelNum)] & (~EPWM_FDCTL0_DGSMPCYC_Msk)) | \ + (EPWM_FDCTL0_FDDGEN_Msk | ((u32DeglitchSmpCycle) << EPWM_FDCTL0_DGSMPCYC_Pos)); +} + +/** + * @brief Disable fault detect deglitch function of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @return None + * @details This function is used to disable fault detect deglitch function of selected channel. + */ +void EPWM_DisableFaultDetectDeglitch(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FDCTL[(u32ChannelNum)] &= ~EPWM_FDCTL0_FDDGEN_Msk; +} + +/** + * @brief Enable fault detect mask function of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @param[in] u32MaskCnt Transition mask counter. Valid values are between 0~0x7F. + * @return None + * @details This function is used to enable fault detect mask function of selected channel. + */ +void EPWM_EnableFaultDetectMask(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32MaskCnt) +{ + (epwm)->FDCTL[(u32ChannelNum)] = ((epwm)->FDCTL[(u32ChannelNum)] & (~EPWM_FDCTL0_TRMSKCNT_Msk)) | (EPWM_FDCTL0_FDMSKEN_Msk | (u32MaskCnt)); +} + +/** + * @brief Disable fault detect mask function of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @return None + * @details This function is used to disable fault detect mask function of selected channel. + */ +void EPWM_DisableFaultDetectMask(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FDCTL[(u32ChannelNum)] &= ~EPWM_FDCTL0_FDMSKEN_Msk; +} + +/** + * @brief Enable fault detect interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @return None + * @details This function is used to enable fault detect interrupt of selected channel. + */ +void EPWM_EnableFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FDIEN |= (EPWM_FDIEN_FDIEN0_Msk << (u32ChannelNum)); +} + +/** + * @brief Disable fault detect interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @return None + * @details This function is used to disable fault detect interrupt of selected channel. + */ +void EPWM_DisableFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FDIEN &= ~(EPWM_FDIEN_FDIEN0_Msk << (u32ChannelNum)); +} + +/** + * @brief Clear fault detect interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @return None + * @details This function is used to clear fault detect interrupt of selected channel. + */ +void EPWM_ClearFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FDSTS = (EPWM_FDSTS_FDIF0_Msk << (u32ChannelNum)); +} + +/** + * @brief Get fault detect interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @retval 0 Fault detect interrupt did not occur. + * @retval 1 Fault detect interrupt occurred. + * @details This function is used to Get fault detect interrupt of selected channel. + */ +uint32_t EPWM_GetFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((epwm)->FDSTS & (EPWM_FDSTS_FDIF0_Msk << (u32ChannelNum))) ? 1UL : 0UL); +} + +/*@}*/ /* end of group EPWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EPWM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_fmc.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_fmc.c new file mode 100644 index 0000000000000000000000000000000000000000..d3bbd345dc310d030f0d6459df478eca53daea64 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_fmc.c @@ -0,0 +1,1041 @@ +/**************************************************************************//** + * @file fmc.c + * @version V1.00 + * @brief M480 series FMC driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include + +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup FMC_Driver FMC Driver + @{ +*/ + + +/** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions + @{ +*/ + + +/** + * @brief Disable FMC ISP function. + * @return None + */ +void FMC_Close(void) +{ + FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk; +} + +/** + * @brief Config XOM Region + * @param[in] u32XomNum The XOM number(0~3) + * @param[in] u32XomBase The XOM region base address. + * @param[in] u8XomPage The XOM page number of region size. + * + * @retval 0 Success + * @retval 1 XOM is has already actived. + * @retval -1 Program failed. + * @retval -2 Invalid XOM number. + * + * @details Program XOM base address and XOM size(page) + */ +int32_t FMC_ConfigXOM(uint32_t u32XomNum, uint32_t u32XomBase, uint8_t u8XomPage) +{ + int32_t ret = 0; + + if(u32XomNum >= 4UL) + { + ret = -2; + } + + if(ret == 0) + { + ret = FMC_GetXOMState(u32XomNum); + } + + if(ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC->ISPADDR = FMC_XOM_BASE + (u32XomNum * 0x10u); + FMC->ISPDAT = u32XomBase; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} + + if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + } + + if(ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC->ISPADDR = FMC_XOM_BASE + (u32XomNum * 0x10u + 0x04u); + FMC->ISPDAT = u8XomPage; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} + + if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + } + + if(ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC->ISPADDR = FMC_XOM_BASE + (u32XomNum * 0x10u + 0x08u); + FMC->ISPDAT = 0u; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} + + if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + } + + return ret; +} + +/** + * @brief Execute FMC_ISPCMD_PAGE_ERASE command to erase a flash page. The page size is 4096 bytes. + * @param[in] u32PageAddr Address of the flash page to be erased. + * It must be a 4096 bytes aligned address. + * @return ISP page erase success or not. + * @retval 0 Success + * @retval -1 Erase failed + */ +int32_t FMC_Erase(uint32_t u32PageAddr) +{ + int32_t ret = 0; + + if (u32PageAddr == FMC_SPROM_BASE) + { + ret = FMC_Erase_SPROM(); + } + + if (ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE; + FMC->ISPADDR = u32PageAddr; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) + { + FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk; + ret = -1; + } + } + return ret; +} + + +/** + * @brief Execute FMC_ISPCMD_PAGE_ERASE command to erase SPROM. The page size is 4096 bytes. + * @return SPROM page erase success or not. + * @retval 0 Success + * @retval -1 Erase failed + */ +int32_t FMC_Erase_SPROM(void) +{ + int32_t ret = 0; + + FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE; + FMC->ISPADDR = FMC_SPROM_BASE; + FMC->ISPDAT = 0x0055AA03UL; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) + { + FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk; + ret = -1; + } + return ret; +} + +/** + * @brief Execute FMC_ISPCMD_BLOCK_ERASE command to erase a flash block. The block size is 4 pages. + * @param[in] u32BlockAddr Address of the flash block to be erased. + * It must be a 4 pages aligned address. + * @return ISP page erase success or not. + * @retval 0 Success + * @retval -1 Erase failed + */ +int32_t FMC_Erase_Block(uint32_t u32BlockAddr) +{ + int32_t ret = 0; + + FMC->ISPCMD = FMC_ISPCMD_BLOCK_ERASE; + FMC->ISPADDR = u32BlockAddr; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) + { + FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk; + ret = -1; + } + return ret; +} + +/** + * @brief Execute FMC_ISPCMD_BANK_ERASE command to erase a flash block. + * @param[in] u32BankAddr Base address of the flash bank to be erased. + * @return ISP page erase success or not. + * @retval 0 Success + * @retval -1 Erase failed + */ +int32_t FMC_Erase_Bank(uint32_t u32BankAddr) +{ + int32_t ret = 0; + + FMC->ISPCMD = FMC_ISPCMD_BANK_ERASE; + FMC->ISPADDR = u32BankAddr; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) + { + FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk; + ret = -1; + } + return ret; +} + +/** + * @brief Execute Erase XOM Region + * + * @param[in] u32XomNum The XOMRn(n=0~3) + * + * @return XOM erase success or not. + * @retval 0 Success + * @retval -1 Erase failed + * @retval -2 Invalid XOM number. + * + * @details Execute FMC_ISPCMD_PAGE_ERASE command to erase XOM. + */ +int32_t FMC_EraseXOM(uint32_t u32XomNum) +{ + uint32_t u32Addr; + int32_t i32Active, err = 0; + + if(u32XomNum >= 4UL) + { + err = -2; + } + + if(err == 0) + { + i32Active = FMC_GetXOMState(u32XomNum); + + if(i32Active) + { + switch(u32XomNum) + { + case 0u: + u32Addr = (FMC->XOMR0STS & 0xFFFFFF00u) >> 8u; + break; + case 1u: + u32Addr = (FMC->XOMR1STS & 0xFFFFFF00u) >> 8u; + break; + case 2u: + u32Addr = (FMC->XOMR2STS & 0xFFFFFF00u) >> 8u; + break; + case 3u: + u32Addr = (FMC->XOMR3STS & 0xFFFFFF00u) >> 8u; + break; + default: + break; + } + FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE; + FMC->ISPADDR = u32Addr; + FMC->ISPDAT = 0x55aa03u; + FMC->ISPTRG = 0x1u; +#if ISBEN + __ISB(); +#endif + while(FMC->ISPTRG) {} + + /* Check ISPFF flag to know whether erase OK or fail. */ + if(FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) + { + FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk; + err = -1; + } + } + else + { + err = -1; + } + } + return err; +} + +/** + * @brief Check the XOM is actived or not. + * + * @param[in] u32XomNum The xom number(0~3). + * + * @retval 1 XOM is actived. + * @retval 0 XOM is not actived. + * @retval -2 Invalid XOM number. + * + * @details To get specify XOMRn(n=0~3) active status + */ +int32_t FMC_GetXOMState(uint32_t u32XomNum) +{ + uint32_t u32act; + int32_t ret = 0; + + if(u32XomNum >= 4UL) + { + ret = -2; + } + + if(ret >= 0) + { + u32act = (((FMC->XOMSTS) & 0xful) & (1ul << u32XomNum)) >> u32XomNum; + ret = (int32_t)u32act; + } + return ret; +} + +/** + * @brief Get the current boot source. + * @return The current boot source. + * @retval 0 Is boot from APROM. + * @retval 1 Is boot from LDROM. + * @retval 2 Is boot from Boot Loader. + */ +int32_t FMC_GetBootSource (void) +{ + if (FMC->ISPCTL & FMC_ISPCTL_BL_Msk) + { + return 2; + } + if (FMC->ISPCTL & FMC_ISPCTL_BS_Msk) + { + return 1; + } + return 0; +} + + +/** + * @brief Enable FMC ISP function + * @return None + */ +void FMC_Open(void) +{ + FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk; +} + + +/** + * @brief Execute FMC_ISPCMD_READ command to read a word from flash. + * @param[in] u32Addr Address of the flash location to be read. + * It must be a word aligned address. + * @return The word data read from specified flash address. + */ +uint32_t FMC_Read(uint32_t u32Addr) +{ + FMC->ISPCMD = FMC_ISPCMD_READ; + FMC->ISPADDR = u32Addr; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + return FMC->ISPDAT; +} + + +/** + * @brief Execute FMC_ISPCMD_READ_64 command to read a double-word from flash. + * @param[in] u32addr Address of the flash location to be read. + * It must be a double-word aligned address. + * @param[out] u32data0 Place holder of word 0 read from flash address u32addr. + * @param[out] u32data1 Place holder of word 0 read from flash address u32addr+4. + * @return 0 Success + * @return -1 Failed + */ +int32_t FMC_Read_64(uint32_t u32addr, uint32_t * u32data0, uint32_t * u32data1) +{ + int32_t ret = 0; + + FMC->ISPCMD = FMC_ISPCMD_READ_64; + FMC->ISPADDR = u32addr; + FMC->ISPDAT = 0x0UL; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { } + + if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + else + { + *u32data0 = FMC->MPDAT0; + *u32data1 = FMC->MPDAT1; + } + return ret; +} + + +/** + * @brief Get the base address of Data Flash if enabled. + * @retval The base address of Data Flash + */ +uint32_t FMC_ReadDataFlashBaseAddr(void) +{ + return FMC->DFBA; +} + +/** + * @brief Set boot source from LDROM or APROM after next software reset + * @param[in] i32BootSrc + * 1: Boot from LDROM + * 0: Boot from APROM + * @return None + * @details This function is used to switch APROM boot or LDROM boot. User need to call + * FMC_SetBootSource to select boot source first, then use CPU reset or + * System Reset Request to reset system. + */ +void FMC_SetBootSource(int32_t i32BootSrc) +{ + if(i32BootSrc) + { + FMC->ISPCTL |= FMC_ISPCTL_BS_Msk; /* Boot from LDROM */ + } + else + { + FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk;/* Boot from APROM */ + } +} + +/** + * @brief Execute ISP FMC_ISPCMD_PROGRAM to program a word to flash. + * @param[in] u32Addr Address of the flash location to be programmed. + * It must be a word aligned address. + * @param[in] u32Data The word data to be programmed. + * @return None + */ +void FMC_Write(uint32_t u32Addr, uint32_t u32Data) +{ + FMC->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC->ISPADDR = u32Addr; + FMC->ISPDAT = u32Data; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } +} + +/** + * @brief Execute ISP FMC_ISPCMD_PROGRAM_64 to program a double-word to flash. + * @param[in] u32addr Address of the flash location to be programmed. + * It must be a double-word aligned address. + * @param[in] u32data0 The word data to be programmed to flash address u32addr. + * @param[in] u32data1 The word data to be programmed to flash address u32addr+4. + * @return 0 Success + * @return -1 Failed + */ +int32_t FMC_Write8Bytes(uint32_t u32addr, uint32_t u32data0, uint32_t u32data1) +{ + int32_t ret = 0; + + FMC->ISPCMD = FMC_ISPCMD_PROGRAM_64; + FMC->ISPADDR = u32addr; + FMC->MPDAT0 = u32data0; + FMC->MPDAT1 = u32data1; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { } + + if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + return ret; +} + + +/** + * @brief Program Multi-Word data into specified address of flash. + * @param[in] u32Addr Start flash address in APROM where the data chunk to be programmed into. + * This address must be 8-bytes aligned to flash address. + * @param[in] pu32Buf Buffer that carry the data chunk. + * @param[in] u32Len Length of the data chunk in bytes. + * @retval >=0 Number of data bytes were programmed. + * @return -1 Invalid address. + */ +int32_t FMC_WriteMultiple(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len) +{ + int i, idx, retval = 0; + + if ((u32Addr >= FMC_APROM_END) || ((u32Addr % 8) != 0)) + { + return -1; + } + + u32Len = u32Len - (u32Len % 8); /* u32Len must be multiple of 8. */ + + idx = 0; + + while (u32Len >= 8) + { + FMC->ISPADDR = u32Addr; + FMC->MPDAT0 = pu32Buf[idx++]; + FMC->MPDAT1 = pu32Buf[idx++]; + FMC->MPDAT2 = pu32Buf[idx++]; + FMC->MPDAT3 = pu32Buf[idx++]; + FMC->ISPCMD = FMC_ISPCMD_PROGRAM_MUL; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + for (i = 16; i < FMC_MULTI_WORD_PROG_LEN; ) + { + while (FMC->MPSTS & (FMC_MPSTS_D0_Msk | FMC_MPSTS_D1_Msk)) + ; + retval += 8; + u32Len -= 8; + if (u32Len < 8) + { + return retval; + } + + if (!(FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk)) + { + /* printf(" [WARNING] busy cleared after D0D1 cleared!\n"); */ + i += 8; + break; + } + + FMC->MPDAT0 = pu32Buf[idx++]; + FMC->MPDAT1 = pu32Buf[idx++]; + + if (i == FMC_MULTI_WORD_PROG_LEN/4) + break; // done + + while (FMC->MPSTS & (FMC_MPSTS_D2_Msk | FMC_MPSTS_D3_Msk)) + ; + retval += 8; + u32Len -= 8; + if (u32Len < 8) + { + return retval; + } + + if (!(FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk)) + { + /* printf(" [WARNING] busy cleared after D2D3 cleared!\n"); */ + i += 8; + break; + } + + FMC->MPDAT2 = pu32Buf[idx++]; + FMC->MPDAT3 = pu32Buf[idx++]; + } + + if (i != FMC_MULTI_WORD_PROG_LEN) + { + /* printf(" [WARNING] Multi-word program interrupted at 0x%x !!\n", i); */ + return retval; + } + + while (FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk) ; + + u32Addr += FMC_MULTI_WORD_PROG_LEN; + } + return retval; +} + + +/** + * @brief Program a 64-bits data to the specified OTP. + * @param[in] otp_num The OTP number. + * @param[in] low_word Low word of the 64-bits data. + * @param[in] high_word Low word of the 64-bits data. + * @retval 0 Success + * @retval -1 Program failed. + * @retval -2 Invalid OTP number. + */ +int32_t FMC_Write_OTP(uint32_t otp_num, uint32_t low_word, uint32_t high_word) +{ + int32_t ret = 0; + + if (otp_num > 255UL) + { + ret = -2; + } + + if (ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC->ISPADDR = FMC_OTP_BASE + otp_num * 8UL; + FMC->ISPDAT = low_word; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + } + + if (ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC->ISPADDR = FMC_OTP_BASE + otp_num * 8UL + 4UL; + FMC->ISPDAT = high_word; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + } + + return ret; +} + +/** + * @brief Read the 64-bits data from the specified OTP. + * @param[in] otp_num The OTP number. + * @param[in] low_word Low word of the 64-bits data. + * @param[in] high_word Low word of the 64-bits data. + * @retval 0 Success + * @retval -1 Read failed. + * @retval -2 Invalid OTP number. + */ +int32_t FMC_Read_OTP(uint32_t otp_num, uint32_t *low_word, uint32_t *high_word) +{ + int32_t ret = 0; + + if (otp_num > 255UL) + { + ret = -2; + } + + if (ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_READ_64; + FMC->ISPADDR = FMC_OTP_BASE + otp_num * 8UL ; + FMC->ISPDAT = 0x0UL; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { } + + if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + else + { + *low_word = FMC->MPDAT0; + *high_word = FMC->MPDAT1; + } + } + return ret; +} + +/** + * @brief Lock the specified OTP. + * @param[in] otp_num The OTP number. + * @retval 0 Success + * @retval -1 Failed to write OTP lock bits. + * @retval -2 Invalid OTP number. + */ +int32_t FMC_Lock_OTP(uint32_t otp_num) +{ + int32_t ret = 0; + + if (otp_num > 255UL) + { + ret = -2; + } + + if (ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC->ISPADDR = FMC_OTP_BASE + 0x800UL + otp_num * 4UL; + FMC->ISPDAT = 0UL; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + } + return ret; +} + +/** + * @brief Check the OTP is locked or not. + * @param[in] otp_num The OTP number. + * @retval 1 OTP is locked. + * @retval 0 OTP is not locked. + * @retval -1 Failed to read OTP lock bits. + * @retval -2 Invalid OTP number. + */ +int32_t FMC_Is_OTP_Locked(uint32_t otp_num) +{ + int32_t ret = 0; + + if (otp_num > 255UL) + { + ret = -2; + } + + if (ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_READ; + FMC->ISPADDR = FMC_OTP_BASE + 0x800UL + otp_num * 4UL; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + else + { + if (FMC->ISPDAT != 0xFFFFFFFFUL) + { + ret = 1; /* Lock work was progrmmed. OTP was locked. */ + } + } + } + return ret; +} + +/** + * @brief Execute FMC_ISPCMD_READ command to read User Configuration. + * @param[out] u32Config A two-word array. + * u32Config[0] holds CONFIG0, while u32Config[1] holds CONFIG1. + * @param[in] u32Count Available word count in u32Config. + * @return Success or not. + * @retval 0 Success. + * @retval -1 Invalid parameter. + */ +int32_t FMC_ReadConfig(uint32_t u32Config[], uint32_t u32Count) +{ + int32_t ret = 0; + + u32Config[0] = FMC_Read(FMC_CONFIG_BASE); + + if (u32Count < 2UL) + { + ret = -1; + } + else + { + u32Config[1] = FMC_Read(FMC_CONFIG_BASE+4UL); + } + return ret; +} + + +/** + * @brief Execute ISP commands to erase then write User Configuration. + * @param[in] u32Config A two-word array. + * u32Config[0] holds CONFIG0, while u32Config[1] holds CONFIG1. + * @param[in] u32Count The number of User Configuration words to be written. + * @return Success or not. + * @retval 0 Success + * @retval -1 Failed + */ +int32_t FMC_WriteConfig(uint32_t u32Config[], uint32_t u32Count) +{ + int i; + + FMC_ENABLE_CFG_UPDATE(); + FMC_Erase(FMC_CONFIG_BASE); + + if ((FMC_Read(FMC_CONFIG_BASE) != 0xFFFFFFFF) || (FMC_Read(FMC_CONFIG_BASE+4) != 0xFFFFFFFF) || + (FMC_Read(FMC_CONFIG_BASE+8) != 0xFFFF5A5A)) + { + FMC_DISABLE_CFG_UPDATE(); + return -1; + } + + for (i = 0; i < u32Count; i++) + { + FMC_Write(FMC_CONFIG_BASE+i*4UL, u32Config[i]); + + if (FMC_Read(FMC_CONFIG_BASE+i*4UL) != u32Config[i]) + { + FMC_DISABLE_CFG_UPDATE(); + return -1; + } + } + + FMC_DISABLE_CFG_UPDATE(); + return 0; +} + + +/** + * @brief Run CRC32 checksum calculation and get result. + * @param[in] u32addr Starting flash address. It must be a page aligned address. + * @param[in] u32count Byte count of flash to be calculated. It must be multiple of 512 bytes. + * @return Success or not. + * @retval 0 Success. + * @retval 0xFFFFFFFF Invalid parameter. + */ +uint32_t FMC_GetChkSum(uint32_t u32addr, uint32_t u32count) +{ + uint32_t ret; + + if ((u32addr % 512UL) || (u32count % 512UL)) + { + ret = 0xFFFFFFFF; + } + else + { + FMC->ISPCMD = FMC_ISPCMD_RUN_CKS; + FMC->ISPADDR = u32addr; + FMC->ISPDAT = u32count; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { } + + FMC->ISPCMD = FMC_ISPCMD_READ_CKS; + FMC->ISPADDR = u32addr; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { } + + ret = FMC->ISPDAT; + } + + return ret; +} + + +/** + * @brief Run flash all one verification and get result. + * @param[in] u32addr Starting flash address. It must be a page aligned address. + * @param[in] u32count Byte count of flash to be calculated. It must be multiple of 512 bytes. + * @retval READ_ALLONE_YES The contents of verified flash area are 0xFFFFFFFF. + * @retval READ_ALLONE_NOT Some contents of verified flash area are not 0xFFFFFFFF. + * @retval READ_ALLONE_CMD_FAIL Unexpected error occurred. + */ +uint32_t FMC_CheckAllOne(uint32_t u32addr, uint32_t u32count) +{ + uint32_t ret = READ_ALLONE_CMD_FAIL; + + FMC->ISPSTS = 0x80UL; /* clear check all one bit */ + + FMC->ISPCMD = FMC_ISPCMD_RUN_ALL1; + FMC->ISPADDR = u32addr; + FMC->ISPDAT = u32count; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { } + + do + { + FMC->ISPCMD = FMC_ISPCMD_READ_ALL1; + FMC->ISPADDR = u32addr; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { } + } + while (FMC->ISPDAT == 0UL); + + if (FMC->ISPDAT == READ_ALLONE_YES) + { + ret = FMC->ISPDAT; + } + + if (FMC->ISPDAT == READ_ALLONE_NOT) + { + ret = FMC->ISPDAT; + } + + return ret; +} + + +/** + * @brief Setup security key. + * @param[in] key Key 0~2 to be setup. + * @param[in] kpmax Maximum unmatched power-on counting number. + * @param[in] kemax Maximum unmatched counting number. + * @param[in] lock_CONFIG 1: Security key lock CONFIG to write-protect. 0: Don't lock CONFIG. + * @param[in] lock_SPROM 1: Security key lock SPROM to write-protect. 0: Don't lock SPROM. + * @retval 0 Success. + * @retval -1 Key is locked. Cannot overwrite the current key. + * @retval -2 Failed to erase flash. + * @retval -3 Failed to program key. + * @retval -4 Key lock function failed. + * @retval -5 CONFIG lock function failed. + * @retval -6 SPROM lock function failed. + * @retval -7 KPMAX function failed. + * @retval -8 KEMAX function failed. + */ +int32_t FMC_SetSPKey(uint32_t key[3], uint32_t kpmax, uint32_t kemax, + const int32_t lock_CONFIG, const int32_t lock_SPROM) +{ + uint32_t lock_ctrl = 0UL; + uint32_t u32KeySts; + int32_t ret = 0; + + if (FMC->KPKEYSTS != 0x200UL) + { + ret = -1; + } + + if (FMC_Erase(FMC_KPROM_BASE)) + { + ret = -2; + } + + if (FMC_Erase(FMC_KPROM_BASE+0x200UL)) + { + ret = -3; + } + + if (!lock_CONFIG) + { + lock_ctrl |= 0x1UL; + } + + if (!lock_SPROM) + { + lock_ctrl |= 0x2UL; + } + + if (ret == 0) + { + FMC_Write(FMC_KPROM_BASE, key[0]); + FMC_Write(FMC_KPROM_BASE+0x4UL, key[1]); + FMC_Write(FMC_KPROM_BASE+0x8UL, key[2]); + FMC_Write(FMC_KPROM_BASE+0xCUL, kpmax); + FMC_Write(FMC_KPROM_BASE+0x10UL, kemax); + FMC_Write(FMC_KPROM_BASE+0x14UL, lock_ctrl); + + while (FMC->KPKEYSTS & FMC_KPKEYSTS_KEYBUSY_Msk) { } + + u32KeySts = FMC->KPKEYSTS; + + if (!(u32KeySts & FMC_KPKEYSTS_KEYLOCK_Msk)) + { + /* Security key lock failed! */ + ret = -4; + } + else if ((lock_CONFIG && (!(u32KeySts & FMC_KPKEYSTS_CFGFLAG_Msk))) || + ((!lock_CONFIG) && (u32KeySts & FMC_KPKEYSTS_CFGFLAG_Msk))) + { + /* CONFIG lock failed! */ + ret = -5; + } + else if ((lock_SPROM && (!(u32KeySts & FMC_KPKEYSTS_SPFLAG_Msk))) || + ((!lock_SPROM) && (u32KeySts & FMC_KPKEYSTS_SPFLAG_Msk))) + { + /* CONFIG lock failed! */ + ret = -6; + } + else if (((FMC->KPCNT & FMC_KPCNT_KPMAX_Msk) >> FMC_KPCNT_KPMAX_Pos) != kpmax) + { + /* KPMAX failed! */ + ret = -7; + } + else if (((FMC->KPKEYCNT & FMC_KPKEYCNT_KPKEMAX_Msk) >> FMC_KPKEYCNT_KPKEMAX_Pos) != kemax) + { + /* KEMAX failed! */ + ret = -8; + } + } + return ret; +} + + +/** + * @brief Execute security key comparison. + * @param[in] key Key 0~2 to be compared. + * @retval 0 Key matched. + * @retval -1 Forbidden. Times of key comparison mismatch reach the maximum count. + * @retval -2 Key mismatched. + * @retval -3 No security key lock. Key comparison is not required. + */ +int32_t FMC_CompareSPKey(uint32_t key[3]) +{ + uint32_t u32KeySts; + int32_t ret = 0; + + if (FMC->KPKEYSTS & FMC_KPKEYSTS_FORBID_Msk) + { + /* FMC_CompareSPKey - FORBID! */ + ret = -1; + } + + if (!(FMC->KPKEYSTS & FMC_KPKEYSTS_KEYLOCK_Msk)) + { + /* FMC_CompareSPKey - key is not locked! */ + ret = -3; + } + + if (ret == 0) + { + FMC->KPKEY0 = key[0]; + FMC->KPKEY1 = key[1]; + FMC->KPKEY2 = key[2]; + FMC->KPKEYTRG = FMC_KPKEYTRG_KPKEYGO_Msk | FMC_KPKEYTRG_TCEN_Msk; + + while (FMC->KPKEYSTS & FMC_KPKEYSTS_KEYBUSY_Msk) { } + + u32KeySts = FMC->KPKEYSTS; + + if (!(u32KeySts & FMC_KPKEYSTS_KEYMATCH_Msk)) + { + /* Key mismatched! */ + ret = -2; + } + else if (u32KeySts & FMC_KPKEYSTS_KEYLOCK_Msk) + { + /* Key matched, but still be locked! */ + ret = -2; + } + } + return ret; +} + + +/*@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group FMC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ + + diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_gpio.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_gpio.c new file mode 100644 index 0000000000000000000000000000000000000000..c40a68aae3b586e10377a449c25b0f2157804cf1 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_gpio.c @@ -0,0 +1,153 @@ +/**************************************************************************//** + * @file gpio.c + * @version V3.00 + * @brief M480 series GPIO driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup GPIO_Driver GPIO Driver + @{ +*/ + +/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions + @{ +*/ + +/** + * @brief Set GPIO operation mode + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be BIT0 ~ BIT13 for PE GPIO port. + * It could be BIT0 ~ BIT11 for PG GPIO port. + * @param[in] u32Mode Operation mode. It could be \n + * GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_OPEN_DRAIN, GPIO_MODE_QUASI. + * + * @return None + * + * @details This function is used to set specified GPIO operation mode. + */ +void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode) +{ + uint32_t i; + + for(i = 0ul; i < GPIO_PIN_MAX; i++) + { + if((u32PinMask & (1ul << i))==(1ul << i)) + { + port->MODE = (port->MODE & ~(0x3ul << (i << 1))) | (u32Mode << (i << 1)); + } + } +} + +/** + * @brief Enable GPIO interrupt + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32Pin The pin of specified GPIO port. + * It could be 0 ~ 15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be 0 ~ 13 for PE GPIO port. + * It could be 0 ~ 11 for PG GPIO port. + * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n + * GPIO_INT_RISING, GPIO_INT_FALLING, GPIO_INT_BOTH_EDGE, GPIO_INT_HIGH, GPIO_INT_LOW. + * + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + */ +void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs) +{ + port->INTTYPE = (port->INTTYPE&~(1ul<> 24) & 0xFFUL) << u32Pin); + port->INTEN = (port->INTEN&~(0x00010001ul<INTTYPE &= ~(1UL << u32Pin); + port->INTEN &= ~((0x00010001UL) << u32Pin); +} + +/** + * @brief Set GPIO slew rate control + * + * @param[in] port GPIO port. It could be \ref PA, \ref PB, ... or \ref GPH + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * @param[in] u32Mode Slew rate mode. \ref GPIO_SLEWCTL_NORMAL (maximum 40 MHz at 2.7V) + * \ref GPIO_SLEWCTL_HIGH (maximum 80 MHz at 2.7V) + * \ref GPIO_SLEWCTL_FAST (maximum 100 MHz at 2.7V) + * + * @return None + * + * @details This function is used to set specified GPIO operation mode. + */ +void GPIO_SetSlewCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode) +{ + uint32_t i; + + for(i = 0ul; i < GPIO_PIN_MAX; i++) + { + if(u32PinMask & (1ul << i)) + { + port->SLEWCTL = (port->SLEWCTL & ~(0x3ul << (i << 1))) | (u32Mode << (i << 1)); + } + } +} + +/** + * @brief Set GPIO Pull-up and Pull-down control + * + * @param[in] port GPIO port. It could be \ref PA, \ref PB, ... or \ref GPH + * @param[in] u32PinMask The pin of specified GPIO port. It could be 0 ~ 15. + * @param[in] u32Mode The pin mode of specified GPIO pin. It could be + * \ref GPIO_PUSEL_DISABLE + * \ref GPIO_PUSEL_PULL_UP + * \ref GPIO_PUSEL_PULL_DOWN + * + * @return None + * + * @details Set the pin mode of specified GPIO pin. + */ +void GPIO_SetPullCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode) +{ + uint32_t i; + + for(i = 0ul; i < GPIO_PIN_MAX; i++) + { + if(u32PinMask & (1ul << i)) + { + port->PUSEL = (port->PUSEL & ~(0x3ul << (i << 1))) | (u32Mode << (i << 1)); + } + } +} + + +/*@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group GPIO_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2011~2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_hsusbd.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_hsusbd.c new file mode 100644 index 0000000000000000000000000000000000000000..48474fa875f71b4787803cb3b2a0b1fd4304f622 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_hsusbd.c @@ -0,0 +1,725 @@ +/**************************************************************************//** + * @file hsusbd.c + * @version V1.00 + * @brief M480 HSUSBD driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup HSUSBD_Driver HSUSBD Driver + @{ +*/ + + +/** @addtogroup HSUSBD_EXPORTED_FUNCTIONS HSUSBD Exported Functions + @{ +*/ +/*--------------------------------------------------------------------------*/ +/** @cond HIDDEN_SYMBOLS */ +/* Global variables for Control Pipe */ +S_HSUSBD_CMD_T gUsbCmd; +S_HSUSBD_INFO_T *g_hsusbd_sInfo; + +HSUSBD_VENDOR_REQ g_hsusbd_pfnVendorRequest = NULL; +HSUSBD_CLASS_REQ g_hsusbd_pfnClassRequest = NULL; +HSUSBD_SET_INTERFACE_REQ g_hsusbd_pfnSetInterface = NULL; +uint32_t g_u32HsEpStallLock = 0ul; /* Bit map flag to lock specified EP when SET_FEATURE */ + +static uint8_t *g_hsusbd_CtrlInPointer = 0; +static uint32_t g_hsusbd_CtrlMaxPktSize = 64ul; +static uint8_t g_hsusbd_UsbConfig = 0ul; +static uint8_t g_hsusbd_UsbAltInterface = 0ul; +static uint8_t g_hsusbd_EnableTestMode = 0ul; +static uint8_t g_hsusbd_TestSelector = 0ul; + +#ifdef __ICCARM__ +#pragma data_alignment=4 +static uint8_t g_hsusbd_buf[12]; +#else +static uint8_t g_hsusbd_buf[12] __attribute__((aligned(4))); +#endif + +uint8_t volatile g_hsusbd_Configured = 0ul; +uint8_t g_hsusbd_CtrlZero = 0ul; +uint8_t g_hsusbd_UsbAddr = 0ul; +uint8_t g_hsusbd_ShortPacket = 0ul; +uint32_t volatile g_hsusbd_DmaDone = 0ul; +uint32_t g_hsusbd_CtrlInSize = 0ul; +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief HSUSBD Initial + * + * @param[in] param Descriptor + * @param[in] pfnClassReq Class Request Callback Function + * @param[in] pfnSetInterface SetInterface Request Callback Function + * + * @return None + * + * @details This function is used to initial HSUSBD. + */ +void HSUSBD_Open(S_HSUSBD_INFO_T *param, HSUSBD_CLASS_REQ pfnClassReq, HSUSBD_SET_INTERFACE_REQ pfnSetInterface) +{ + g_hsusbd_sInfo = param; + g_hsusbd_pfnClassRequest = pfnClassReq; + g_hsusbd_pfnSetInterface = pfnSetInterface; + + /* get EP0 maximum packet size */ + g_hsusbd_CtrlMaxPktSize = g_hsusbd_sInfo->gu8DevDesc[7]; + + /* Initial USB engine */ + //HSUSBD->PHYCTL |= (HSUSBD_PHYCTL_PHYEN_Msk | HSUSBD_PHYCTL_DPPUEN_Msk); + HSUSBD_ENABLE_PHY(); + while((HSUSBD->BUSINTSTS & HSUSBD_BUSINTEN_PHYCLKVLDIEN_Msk) != HSUSBD_BUSINTEN_PHYCLKVLDIEN_Msk ){} + HSUSBD_CLR_SE0(); + + /* wait PHY clock ready */ + while (1) + { + HSUSBD->EP[EPA].EPMPS = 0x20ul; + if (HSUSBD->EP[EPA].EPMPS == 0x20ul) + { + HSUSBD->EP[EPA].EPMPS = 0x0ul; + break; + } + } + /* Force SE0, and then clear it to connect*/ + HSUSBD_SET_SE0(); +} + +/** + * @brief HSUSBD Start + * + * @param[in] None + * + * @return None + * + * @details This function is used to start transfer + */ +void HSUSBD_Start(void) +{ + HSUSBD_CLR_SE0(); +} + +/** + * @brief Process Setup Packet + * + * @param[in] None + * + * @return None + * + * @details This function is used to process Setup packet. + */ +void HSUSBD_ProcessSetupPacket(void) +{ + /* Setup packet process */ + gUsbCmd.bmRequestType = (uint8_t)(HSUSBD->SETUP1_0 & 0xfful); + gUsbCmd.bRequest = (uint8_t)((HSUSBD->SETUP1_0 >> 8) & 0xfful); + gUsbCmd.wValue = (uint16_t)HSUSBD->SETUP3_2; + gUsbCmd.wIndex = (uint16_t)HSUSBD->SETUP5_4; + gUsbCmd.wLength = (uint16_t)HSUSBD->SETUP7_6; + + /* USB device request in setup packet: offset 0, D[6..5]: 0=Standard, 1=Class, 2=Vendor, 3=Reserved */ + switch (gUsbCmd.bmRequestType & 0x60ul) + { + case REQ_STANDARD: + { + HSUSBD_StandardRequest(); + break; + } + case REQ_CLASS: + { + if (g_hsusbd_pfnClassRequest != NULL) + { + g_hsusbd_pfnClassRequest(); + } + break; + } + case REQ_VENDOR: + { + if (g_hsusbd_pfnVendorRequest != NULL) + { + g_hsusbd_pfnVendorRequest(); + } + break; + } + default: + { + /* Setup error, stall the device */ + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALLEN_Msk); + break; + } + } +} + +/** + * @brief Get Descriptor request + * + * @param[in] None + * + * @return None + * + * @details This function is used to process GetDescriptor request. + */ +int HSUSBD_GetDescriptor(void) +{ + uint32_t u32Len; + int val = 0; + + u32Len = gUsbCmd.wLength; + g_hsusbd_CtrlZero = (uint8_t)0ul; + + switch ((gUsbCmd.wValue & 0xff00ul) >> 8) + { + /* Get Device Descriptor */ + case DESC_DEVICE: + { + u32Len = Minimum(u32Len, LEN_DEVICE); + HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8DevDesc, u32Len); + break; + } + /* Get Configuration Descriptor */ + case DESC_CONFIG: + { + uint32_t u32TotalLen; + if ((HSUSBD->OPER & 0x04ul) == 0x04ul) + { + u32TotalLen = g_hsusbd_sInfo->gu8ConfigDesc[3]; + u32TotalLen = g_hsusbd_sInfo->gu8ConfigDesc[2] + (u32TotalLen << 8); + + if (u32Len > u32TotalLen) + { + u32Len = u32TotalLen; + if ((u32Len % g_hsusbd_CtrlMaxPktSize) == 0ul) + { + g_hsusbd_CtrlZero = (uint8_t)1ul; + } + } + HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8ConfigDesc, u32Len); + } + else + { + u32TotalLen = g_hsusbd_sInfo->gu8FullConfigDesc[3]; + u32TotalLen = g_hsusbd_sInfo->gu8FullConfigDesc[2] + (u32TotalLen << 8); + + if (u32Len > u32TotalLen) + { + u32Len = u32TotalLen; + if ((u32Len % g_hsusbd_CtrlMaxPktSize) == 0ul) + { + g_hsusbd_CtrlZero = (uint8_t)1ul; + } + } + HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8FullConfigDesc, u32Len); + } + + break; + } + /* Get Qualifier Descriptor */ + case DESC_QUALIFIER: + { + u32Len = Minimum(u32Len, LEN_QUALIFIER); + HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8QualDesc, u32Len); + break; + } + /* Get Other Speed Descriptor - Full speed */ + case DESC_OTHERSPEED: + { + uint32_t u32TotalLen; + if ((HSUSBD->OPER & 0x04ul) == 0x04ul) + { + u32TotalLen = g_hsusbd_sInfo->gu8HSOtherConfigDesc[3]; + u32TotalLen = g_hsusbd_sInfo->gu8HSOtherConfigDesc[2] + (u32TotalLen << 8); + + if (u32Len > u32TotalLen) + { + u32Len = u32TotalLen; + if ((u32Len % g_hsusbd_CtrlMaxPktSize) == 0ul) + { + g_hsusbd_CtrlZero = (uint8_t)1ul; + } + } + HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8HSOtherConfigDesc, u32Len); + } + else + { + u32TotalLen = g_hsusbd_sInfo->gu8FSOtherConfigDesc[3]; + u32TotalLen = g_hsusbd_sInfo->gu8FSOtherConfigDesc[2] + (u32TotalLen << 8); + + if (u32Len > u32TotalLen) + { + u32Len = u32TotalLen; + if ((u32Len % g_hsusbd_CtrlMaxPktSize) == 0ul) + { + g_hsusbd_CtrlZero = (uint8_t)1ul; + } + } + HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8FSOtherConfigDesc, u32Len); + } + + break; + } + /* Get HID Descriptor */ + case DESC_HID: + { + uint32_t u32ConfigDescOffset; /* u32ConfigDescOffset is configuration descriptor offset (HID descriptor start index) */ + u32Len = Minimum(u32Len, LEN_HID); + u32ConfigDescOffset = g_hsusbd_sInfo->gu32ConfigHidDescIdx[gUsbCmd.wIndex & 0xfful]; + HSUSBD_PrepareCtrlIn((uint8_t *)&g_hsusbd_sInfo->gu8ConfigDesc[u32ConfigDescOffset], u32Len); + break; + } + /* Get Report Descriptor */ + case DESC_HID_RPT: + { + if (u32Len > g_hsusbd_sInfo->gu32HidReportSize[gUsbCmd.wIndex & 0xfful]) + { + u32Len = g_hsusbd_sInfo->gu32HidReportSize[gUsbCmd.wIndex & 0xfful]; + if ((u32Len % g_hsusbd_CtrlMaxPktSize) == 0ul) + { + g_hsusbd_CtrlZero = (uint8_t)1ul; + } + } + HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8HidReportDesc[gUsbCmd.wIndex & 0xfful], u32Len); + break; + } + /* Get String Descriptor */ + case DESC_STRING: + { + if((gUsbCmd.wValue & 0xfful) < 8ul) + { + if (u32Len > g_hsusbd_sInfo->gu8StringDesc[gUsbCmd.wValue & 0xfful][0]) + { + u32Len = g_hsusbd_sInfo->gu8StringDesc[gUsbCmd.wValue & 0xfful][0]; + if ((u32Len % g_hsusbd_CtrlMaxPktSize) == 0ul) + { + g_hsusbd_CtrlZero = (uint8_t)1ul; + } + } + HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8StringDesc[gUsbCmd.wValue & 0xfful], u32Len); + } + else + { + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALLEN_Msk); + val = 1; + } + break; + } + default: + /* Not support. Reply STALL. */ + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALLEN_Msk); + val = 1; + break; + } + return val; +} + + +/** + * @brief Process USB standard request + * + * @param[in] None + * + * @return None + * + * @details This function is used to process USB Standard Request. + */ +void HSUSBD_StandardRequest(void) +{ + /* clear global variables for new request */ + g_hsusbd_CtrlInPointer = 0; + g_hsusbd_CtrlInSize = 0ul; + + if ((gUsbCmd.bmRequestType & 0x80ul) == 0x80ul) /* request data transfer direction */ + { + /* Device to host */ + switch (gUsbCmd.bRequest) + { + case GET_CONFIGURATION: + { + /* Return current configuration setting */ + HSUSBD_PrepareCtrlIn((uint8_t *)&g_hsusbd_UsbConfig, 1ul); + + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_INTKIF_Msk); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_INTKIEN_Msk); + break; + } + case GET_DESCRIPTOR: + { + if (!HSUSBD_GetDescriptor()) + { + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_INTKIF_Msk); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_INTKIEN_Msk); + } + break; + } + case GET_INTERFACE: + { + /* Return current interface setting */ + HSUSBD_PrepareCtrlIn((uint8_t *)&g_hsusbd_UsbAltInterface, 1ul); + + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_INTKIF_Msk); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_INTKIEN_Msk); + break; + } + case GET_STATUS: + { + /* Device */ + if (gUsbCmd.bmRequestType == 0x80ul) + { + if ((g_hsusbd_sInfo->gu8ConfigDesc[7] & 0x40ul) == 0x40ul) + { + g_hsusbd_buf[0] = (uint8_t)1ul; /* Self-Powered */ + } + else + { + g_hsusbd_buf[0] = (uint8_t)0ul; /* bus-Powered */ + } + } + /* Interface */ + else if (gUsbCmd.bmRequestType == 0x81ul) + { + g_hsusbd_buf[0] = (uint8_t)0ul; + } + /* Endpoint */ + else if (gUsbCmd.bmRequestType == 0x82ul) + { + uint8_t ep = (uint8_t)(gUsbCmd.wIndex & 0xFul); + g_hsusbd_buf[0] = (uint8_t)HSUSBD_GetStall((uint32_t)ep)? (uint8_t)1 : (uint8_t)0; + } + g_hsusbd_buf[1] = (uint8_t)0ul; + HSUSBD_PrepareCtrlIn(g_hsusbd_buf, 2ul); + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_INTKIF_Msk); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_INTKIEN_Msk); + break; + } + default: + { + /* Setup error, stall the device */ + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALLEN_Msk); + break; + } + } + } + else + { + /* Host to device */ + switch (gUsbCmd.bRequest) + { + case CLEAR_FEATURE: + { + if((gUsbCmd.wValue & 0xfful) == FEATURE_ENDPOINT_HALT) + { + + uint32_t epNum, i; + + /* EP number stall is not allow to be clear in MSC class "Error Recovery Test". + a flag: g_u32HsEpStallLock is added to support it */ + epNum = (uint32_t)(gUsbCmd.wIndex & 0xFul); + for (i=0ul; iEP[i].EPCFG & 0xf0ul) >> 4) == epNum) && ((g_u32HsEpStallLock & (1ul << i)) == 0ul)) + { + HSUSBD->EP[i].EPRSPCTL = (HSUSBD->EP[i].EPRSPCTL & 0xeful) | HSUSBD_EP_RSPCTL_TOGGLE; + } + } + } + /* Status stage */ + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk); + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_STSDONEIEN_Msk); + break; + } + case SET_ADDRESS: + { + g_hsusbd_UsbAddr = (uint8_t)gUsbCmd.wValue; + /* Status Stage */ + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk); + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_STSDONEIEN_Msk); + break; + } + case SET_CONFIGURATION: + { + g_hsusbd_UsbConfig = (uint8_t)gUsbCmd.wValue; + g_hsusbd_Configured = (uint8_t)1ul; + /* Status stage */ + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk); + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_STSDONEIEN_Msk); + break; + } + case SET_FEATURE: + { + if ((gUsbCmd.wValue & 0x3ul) == 2ul) /* TEST_MODE */ + { + g_hsusbd_EnableTestMode = (uint8_t)1ul; + g_hsusbd_TestSelector = (uint8_t)(gUsbCmd.wIndex >> 8); + } + if ((gUsbCmd.wValue & 0x3ul) == 3ul) /* HNP ebable */ + { + HSOTG->CTL |= (HSOTG_CTL_HNPREQEN_Msk | HSOTG_CTL_BUSREQ_Msk); + } + + /* Status stage */ + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk); + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_STSDONEIEN_Msk); + break; + } + case SET_INTERFACE: + { + g_hsusbd_UsbAltInterface = (uint8_t)gUsbCmd.wValue; + if (g_hsusbd_pfnSetInterface != NULL) + { + g_hsusbd_pfnSetInterface((uint32_t)g_hsusbd_UsbAltInterface); + } + /* Status stage */ + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk); + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_STSDONEIEN_Msk); + break; + } + default: + { + /* Setup error, stall the device */ + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALLEN_Msk); + break; + } + } + } +} + +/** + * @brief Update Device State + * + * @param[in] None + * + * @return None + * + * @details This function is used to update Device state when Setup packet complete + */ +/** @cond HIDDEN_SYMBOLS */ +#define TEST_J 0x01ul +#define TEST_K 0x02ul +#define TEST_SE0_NAK 0x03ul +#define TEST_PACKET 0x04ul +#define TEST_FORCE_ENABLE 0x05ul +/** @endcond HIDDEN_SYMBOLS */ + +void HSUSBD_UpdateDeviceState(void) +{ + switch (gUsbCmd.bRequest) + { + case SET_ADDRESS: + { + HSUSBD_SET_ADDR(g_hsusbd_UsbAddr); + break; + } + case SET_CONFIGURATION: + { + if (g_hsusbd_UsbConfig == 0ul) + { + uint32_t volatile i; + /* Reset PID DATA0 */ + for (i=0ul; iEP[i].EPCFG & 0x1ul) == 0x1ul) + { + HSUSBD->EP[i].EPRSPCTL = HSUSBD_EP_RSPCTL_TOGGLE; + } + } + } + break; + } + case SET_FEATURE: + { + if(gUsbCmd.wValue == FEATURE_ENDPOINT_HALT) + { + uint32_t idx; + idx = (uint32_t)(gUsbCmd.wIndex & 0xFul); + HSUSBD_SetStall(idx); + } + else if (g_hsusbd_EnableTestMode) + { + g_hsusbd_EnableTestMode = (uint8_t)0ul; + if (g_hsusbd_TestSelector == TEST_J) + { + HSUSBD->TEST = TEST_J; + } + else if (g_hsusbd_TestSelector == TEST_K) + { + HSUSBD->TEST = TEST_K; + } + else if (g_hsusbd_TestSelector == TEST_SE0_NAK) + { + HSUSBD->TEST = TEST_SE0_NAK; + } + else if (g_hsusbd_TestSelector == TEST_PACKET) + { + HSUSBD->TEST = TEST_PACKET; + } + else if (g_hsusbd_TestSelector == TEST_FORCE_ENABLE) + { + HSUSBD->TEST = TEST_FORCE_ENABLE; + } + } + break; + } + case CLEAR_FEATURE: + { + if(gUsbCmd.wValue == FEATURE_ENDPOINT_HALT) + { + uint32_t idx; + idx = (uint32_t)(gUsbCmd.wIndex & 0xFul); + HSUSBD_ClearStall(idx); + } + break; + } + default: + break; + } +} + + +/** + * @brief Prepare Control IN transaction + * + * @param[in] pu8Buf Control IN data pointer + * @param[in] u32Size IN transfer size + * + * @return None + * + * @details This function is used to prepare Control IN transfer + */ +void HSUSBD_PrepareCtrlIn(uint8_t pu8Buf[], uint32_t u32Size) +{ + g_hsusbd_CtrlInPointer = pu8Buf; + g_hsusbd_CtrlInSize = u32Size; +} + + + +/** + * @brief Start Control IN transfer + * + * @param[in] None + * + * @return None + * + * @details This function is used to start Control IN + */ +void HSUSBD_CtrlIn(void) +{ + uint32_t volatile i, cnt; + uint8_t u8Value; + if(g_hsusbd_CtrlInSize >= g_hsusbd_CtrlMaxPktSize) + { + /* Data size > MXPLD */ + cnt = g_hsusbd_CtrlMaxPktSize >> 2; + for (i=0ul; iCEPDAT = *(uint32_t *)g_hsusbd_CtrlInPointer; + g_hsusbd_CtrlInPointer = (uint8_t *)(g_hsusbd_CtrlInPointer + 4ul); + } + HSUSBD_START_CEP_IN(g_hsusbd_CtrlMaxPktSize); + g_hsusbd_CtrlInSize -= g_hsusbd_CtrlMaxPktSize; + } + else + { + /* Data size <= MXPLD */ + cnt = g_hsusbd_CtrlInSize >> 2; + for (i=0ul; iCEPDAT = *(uint32_t *)g_hsusbd_CtrlInPointer; + g_hsusbd_CtrlInPointer += 4ul; + } + + for (i=0ul; i<(g_hsusbd_CtrlInSize % 4ul); i++) + { + u8Value = *(uint8_t *)(g_hsusbd_CtrlInPointer+i); + outpb(&HSUSBD->CEPDAT, u8Value); + } + + HSUSBD_START_CEP_IN(g_hsusbd_CtrlInSize); + g_hsusbd_CtrlInPointer = 0; + g_hsusbd_CtrlInSize = 0ul; + } +} + +/** + * @brief Start Control OUT transaction + * + * @param[in] pu8Buf Control OUT data pointer + * @param[in] u32Size OUT transfer size + * + * @return None + * + * @details This function is used to start Control OUT transfer + */ +void HSUSBD_CtrlOut(uint8_t pu8Buf[], uint32_t u32Size) +{ + uint32_t volatile i; + while(1) + { + if ((HSUSBD->CEPINTSTS & HSUSBD_CEPINTSTS_RXPKIF_Msk) == HSUSBD_CEPINTSTS_RXPKIF_Msk) + { + for (i=0ul; iCEPDAT); + } + HSUSBD->CEPINTSTS = HSUSBD_CEPINTSTS_RXPKIF_Msk; + break; + } + } +} + +/** + * @brief Clear all software flags + * + * @param[in] None + * + * @return None + * + * @details This function is used to clear all software control flag + */ +void HSUSBD_SwReset(void) +{ + /* Reset all variables for protocol */ + g_hsusbd_UsbAddr = (uint8_t)0ul; + g_hsusbd_DmaDone = 0ul; + g_hsusbd_ShortPacket = (uint8_t)0ul; + g_hsusbd_Configured = (uint8_t)0ul; + + /* Reset USB device address */ + HSUSBD_SET_ADDR(0ul); +} + +/** + * @brief HSUSBD Set Vendor Request + * + * @param[in] pfnVendorReq Vendor Request Callback Function + * + * @return None + * + * @details This function is used to set HSUSBD vendor request callback function + */ +void HSUSBD_SetVendorRequest(HSUSBD_VENDOR_REQ pfnVendorReq) +{ + g_hsusbd_pfnVendorRequest = pfnVendorReq; +} + + +/*@}*/ /* end of group HSUSBD_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group HSUSBD_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_i2c.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_i2c.c new file mode 100644 index 0000000000000000000000000000000000000000..436b7e586b6cf53d46266ac0d0fddd0d9e918872 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_i2c.c @@ -0,0 +1,1486 @@ +/**************************************************************************//** + * @file i2c.c + * @version V3.00 + * @brief M480 series I2C driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup I2C_Driver I2C Driver + @{ +*/ + + +/** @addtogroup I2C_EXPORTED_FUNCTIONS I2C Exported Functions + @{ +*/ + +/** + * @brief Enable specify I2C Controller and set Clock Divider + * + * @param[in] i2c Specify I2C port + * @param[in] u32BusClock The target I2C bus clock in Hz + * + * @return Actual I2C bus clock frequency + * + * @details The function enable the specify I2C Controller and set proper Clock Divider + * in I2C CLOCK DIVIDED REGISTER (I2CLK) according to the target I2C Bus clock. + * I2C Bus clock = PCLK / (4*(divider+1). + * + */ +uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock) +{ + uint32_t u32Div; + uint32_t u32Pclk; + + if(i2c == I2C1) + { + u32Pclk = CLK_GetPCLK1Freq(); + } + else + { + u32Pclk = CLK_GetPCLK0Freq(); + } + + u32Div = (uint32_t)(((u32Pclk * 10U) / (u32BusClock * 4U) + 5U) / 10U - 1U); /* Compute proper divider for I2C clock */ + i2c->CLKDIV = u32Div; + + /* Enable I2C */ + i2c->CTL0 |= I2C_CTL0_I2CEN_Msk; + + return (u32Pclk / ((u32Div + 1U) << 2U)); +} + +/** + * @brief Disable specify I2C Controller + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Reset I2C Controller and disable specify I2C port. + * + */ + +void I2C_Close(I2C_T *i2c) +{ + /* Reset I2C Controller */ + if((uint32_t)i2c == I2C0_BASE) + { + SYS->IPRST1 |= SYS_IPRST1_I2C0RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_I2C0RST_Msk; + } + else if((uint32_t)i2c == I2C1_BASE) + { + SYS->IPRST1 |= SYS_IPRST1_I2C1RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_I2C1RST_Msk; + } + else if((uint32_t)i2c == I2C2_BASE) + { + SYS->IPRST1 |= SYS_IPRST1_I2C2RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_I2C2RST_Msk; + } + + /* Disable I2C */ + i2c->CTL0 &= ~I2C_CTL0_I2CEN_Msk; +} + +/** + * @brief Clear Time-out Counter flag + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details When Time-out flag will be set, use this function to clear I2C Bus Time-out counter flag . + * + */ +void I2C_ClearTimeoutFlag(I2C_T *i2c) +{ + i2c->TOCTL |= I2C_TOCTL_TOIF_Msk; +} + +/** + * @brief Set Control bit of I2C Controller + * + * @param[in] i2c Specify I2C port + * @param[in] u8Start Set I2C START condition + * @param[in] u8Stop Set I2C STOP condition + * @param[in] u8Si Clear SI flag + * @param[in] u8Ack Set I2C ACK bit + * + * @return None + * + * @details The function set I2C Control bit of I2C Bus protocol. + * + */ +void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack) +{ + uint32_t u32Reg = 0U; + + if(u8Start) + { + u32Reg |= I2C_CTL_STA; + } + + if(u8Stop) + { + u32Reg |= I2C_CTL_STO; + } + + if(u8Si) + { + u32Reg |= I2C_CTL_SI; + } + + if(u8Ack) + { + u32Reg |= I2C_CTL_AA; + } + + i2c->CTL0 = (i2c->CTL0 & ~0x3CU) | u32Reg; +} + +/** + * @brief Disable Interrupt of I2C Controller + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details The function is used for disable I2C interrupt + * + */ +void I2C_DisableInt(I2C_T *i2c) +{ + i2c->CTL0 &= ~I2C_CTL0_INTEN_Msk; +} + +/** + * @brief Enable Interrupt of I2C Controller + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details The function is used for enable I2C interrupt + * + */ +void I2C_EnableInt(I2C_T *i2c) +{ + i2c->CTL0 |= I2C_CTL0_INTEN_Msk; +} + +/** + * @brief Get I2C Bus Clock + * + * @param[in] i2c Specify I2C port + * + * @return The actual I2C Bus clock in Hz + * + * @details To get the actual I2C Bus Clock frequency. + */ +uint32_t I2C_GetBusClockFreq(I2C_T *i2c) +{ + uint32_t u32Divider = i2c->CLKDIV; + uint32_t u32Pclk; + + if(i2c == I2C1) + { + u32Pclk = CLK_GetPCLK1Freq(); + } + else + { + u32Pclk = CLK_GetPCLK0Freq(); + } + + return (u32Pclk / ((u32Divider + 1U) << 2U)); +} + +/** + * @brief Set I2C Bus Clock + * + * @param[in] i2c Specify I2C port + * @param[in] u32BusClock The target I2C Bus Clock in Hz + * + * @return The actual I2C Bus Clock in Hz + * + * @details To set the actual I2C Bus Clock frequency. + */ +uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock) +{ + uint32_t u32Div; + uint32_t u32Pclk; + + if(i2c == I2C1) + { + u32Pclk = CLK_GetPCLK1Freq(); + } + else + { + u32Pclk = CLK_GetPCLK0Freq(); + } + + u32Div = (uint32_t)(((u32Pclk * 10U) / (u32BusClock * 4U) + 5U) / 10U - 1U); /* Compute proper divider for I2C clock */ + i2c->CLKDIV = u32Div; + + return (u32Pclk / ((u32Div + 1U) << 2U)); +} + +/** + * @brief Get Interrupt Flag + * + * @param[in] i2c Specify I2C port + * + * @return I2C interrupt flag status + * + * @details To get I2C Bus interrupt flag. + */ +uint32_t I2C_GetIntFlag(I2C_T *i2c) +{ + uint32_t u32Value; + + if((i2c->CTL0 & I2C_CTL0_SI_Msk) == I2C_CTL0_SI_Msk) + { + u32Value = 1U; + } + else + { + u32Value = 0U; + } + + return u32Value; +} + +/** + * @brief Get I2C Bus Status Code + * + * @param[in] i2c Specify I2C port + * + * @return I2C Status Code + * + * @details To get I2C Bus Status Code. + */ +uint32_t I2C_GetStatus(I2C_T *i2c) +{ + return (i2c->STATUS0); +} + +/** + * @brief Read a Byte from I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @return I2C Data + * + * @details To read a bytes data from specify I2C port. + */ +uint8_t I2C_GetData(I2C_T *i2c) +{ + return (uint8_t)(i2c->DAT); +} + +/** + * @brief Send a byte to I2C Bus + * + * @param[in] i2c Specify I2C port + * @param[in] u8Data The data to send to I2C bus + * + * @return None + * + * @details This function is used to write a byte to specified I2C port + */ +void I2C_SetData(I2C_T *i2c, uint8_t u8Data) +{ + i2c->DAT = u8Data; +} + +/** + * @brief Set 7-bit Slave Address and GC Mode + * + * @param[in] i2c Specify I2C port + * @param[in] u8SlaveNo Set the number of I2C address register (0~3) + * @param[in] u8SlaveAddr 7-bit slave address + * @param[in] u8GCMode Enable/Disable GC mode (I2C_GCMODE_ENABLE / I2C_GCMODE_DISABLE) + * + * @return None + * + * @details This function is used to set 7-bit slave addresses in I2C SLAVE ADDRESS REGISTER (I2CADDR0~3) + * and enable GC Mode. + * + */ +void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode) +{ + switch(u8SlaveNo) + { + case 1: + i2c->ADDR1 = ((uint32_t)u8SlaveAddr << 1U) | u8GCMode; + break; + case 2: + i2c->ADDR2 = ((uint32_t)u8SlaveAddr << 1U) | u8GCMode; + break; + case 3: + i2c->ADDR3 = ((uint32_t)u8SlaveAddr << 1U) | u8GCMode; + break; + case 0: + default: + i2c->ADDR0 = ((uint32_t)u8SlaveAddr << 1U) | u8GCMode; + break; + } +} + +/** + * @brief Configure the mask bits of 7-bit Slave Address + * + * @param[in] i2c Specify I2C port + * @param[in] u8SlaveNo Set the number of I2C address mask register (0~3) + * @param[in] u8SlaveAddrMask A byte for slave address mask + * + * @return None + * + * @details This function is used to set 7-bit slave addresses. + * + */ +void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask) +{ + switch(u8SlaveNo) + { + case 1: + i2c->ADDRMSK1 = (uint32_t)u8SlaveAddrMask << 1U; + break; + case 2: + i2c->ADDRMSK2 = (uint32_t)u8SlaveAddrMask << 1U; + break; + case 3: + i2c->ADDRMSK3 = (uint32_t)u8SlaveAddrMask << 1U; + break; + case 0: + default: + i2c->ADDRMSK0 = (uint32_t)u8SlaveAddrMask << 1U; + break; + } +} + +/** + * @brief Enable Time-out Counter Function and support Long Time-out + * + * @param[in] i2c Specify I2C port + * @param[in] u8LongTimeout Configure DIV4 to enable Long Time-out (0/1) + * + * @return None + * + * @details This function enable Time-out Counter function and configure DIV4 to support Long + * Time-out. + * + */ +void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout) +{ + if(u8LongTimeout) + { + i2c->TOCTL |= I2C_TOCTL_TOCDIV4_Msk; + } + else + { + i2c->TOCTL &= ~I2C_TOCTL_TOCDIV4_Msk; + } + + i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk; +} + +/** + * @brief Disable Time-out Counter Function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details To disable Time-out Counter function in I2CTOC register. + * + */ +void I2C_DisableTimeout(I2C_T *i2c) +{ + i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk; +} + +/** + * @brief Enable I2C Wake-up Function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details To enable Wake-up function of I2C Wake-up control register. + * + */ +void I2C_EnableWakeup(I2C_T *i2c) +{ + i2c->WKCTL |= I2C_WKCTL_WKEN_Msk; +} + +/** + * @brief Disable I2C Wake-up Function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details To disable Wake-up function of I2C Wake-up control register. + * + */ +void I2C_DisableWakeup(I2C_T *i2c) +{ + i2c->WKCTL &= ~I2C_WKCTL_WKEN_Msk; +} + +/** + * @brief To get SMBus Status + * + * @param[in] i2c Specify I2C port + * + * @return SMBus status + * + * @details To get the Bus Management status of I2C_BUSSTS register + * + */ +uint32_t I2C_SMBusGetStatus(I2C_T *i2c) +{ + return (i2c->BUSSTS); +} + +/** + * @brief Clear SMBus Interrupt Flag + * + * @param[in] i2c Specify I2C port + * @param[in] u8SMBusIntFlag Specify SMBus interrupt flag + * + * @return None + * + * @details To clear flags of I2C_BUSSTS status register if interrupt set. + * + */ +void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8SMBusIntFlag) +{ + i2c->BUSSTS = u8SMBusIntFlag; +} + +/** + * @brief Set SMBus Bytes Counts of Transmission or Reception + * + * @param[in] i2c Specify I2C port + * @param[in] u32PktSize Transmit / Receive bytes + * + * @return None + * + * @details The transmission or receive byte number in one transaction when PECEN is set. The maximum is 255 bytes. + * + */ +void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize) +{ + i2c->PKTSIZE = u32PktSize; +} + +/** + * @brief Init SMBus Host/Device Mode + * + * @param[in] i2c Specify I2C port + * @param[in] u8HostDevice Init SMBus port mode(I2C_SMBH_ENABLE(1)/I2C_SMBD_ENABLE(0)) + * + * @return None + * + * @details Using SMBus communication must specify the port is a Host or a Device. + * + */ +void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice) +{ + /* Clear BMHEN, BMDEN of BUSCTL Register */ + i2c->BUSCTL &= ~(I2C_BUSCTL_BMHEN_Msk | I2C_BUSCTL_BMDEN_Msk); + + /* Set SMBus Host/Device Mode, and enable Bus Management*/ + if(u8HostDevice == (uint8_t)I2C_SMBH_ENABLE) + { + i2c->BUSCTL |= (I2C_BUSCTL_BMHEN_Msk | I2C_BUSCTL_BUSEN_Msk); + } + else + { + i2c->BUSCTL |= (I2C_BUSCTL_BMDEN_Msk | I2C_BUSCTL_BUSEN_Msk); + } +} + +/** + * @brief Disable SMBus function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Disable all SMBus function include Bus disable, CRC check, Acknowledge by manual, Host/Device Mode. + * + */ +void I2C_SMBusClose(I2C_T *i2c) +{ + + i2c->BUSCTL = 0x00U; +} + +/** + * @brief Enable SMBus PEC Transmit Function + * + * @param[in] i2c Specify I2C port + * @param[in] u8PECTxEn CRC transmit enable(PECTX_ENABLE) or disable(PECTX_DISABLE) + * + * @return None + * + * @details When enable CRC check function, the Host or Device needs to transmit CRC byte. + * + */ +void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn) +{ + i2c->BUSCTL &= ~I2C_BUSCTL_PECTXEN_Msk; + + if(u8PECTxEn) + { + i2c->BUSCTL |= (I2C_BUSCTL_PECEN_Msk | I2C_BUSCTL_PECTXEN_Msk); + } + else + { + i2c->BUSCTL |= I2C_BUSCTL_PECEN_Msk; + } +} + +/** + * @brief Get SMBus CRC value + * + * @param[in] i2c Specify I2C port + * + * @return A byte is packet error check value + * + * @details The CRC check value after a transmission or a reception by count by using CRC8 + * + */ +uint8_t I2C_SMBusGetPECValue(I2C_T *i2c) +{ + return (uint8_t)i2c->PKTCRC; +} + +/** + * @brief Calculate Time-out of SMBus idle period + * + * @param[in] i2c Specify I2C port + * @param[in] us Time-out length(us) + * @param[in] u32Hclk I2C peripheral clock frequency + * + * @return None + * + * @details This function is used to set SMBus Time-out length when bus is in Idle state. + * + */ + +void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t us, uint32_t u32Hclk) +{ + uint32_t u32Div, u32Hclk_kHz; + + i2c->BUSCTL |= I2C_BUSCTL_TIDLE_Msk; + u32Hclk_kHz = u32Hclk / 1000U; + u32Div = (((us * u32Hclk_kHz) / 1000U) >> 2U) - 1U; + if(u32Div > 255U) + { + i2c->BUSTOUT = 0xFFU; + } + else + { + i2c->BUSTOUT = u32Div; + } + +} + +/** + * @brief Calculate Time-out of SMBus active period + * + * @param[in] i2c Specify I2C port + * @param[in] ms Time-out length(ms) + * @param[in] u32Pclk peripheral clock frequency + * + * @return None + * + * @details This function is used to set SMBus Time-out length when bus is in active state. + * Time-out length is calculate the SCL line "one clock" pull low timing. + * + */ + +void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk) +{ + uint32_t u32Div, u32Pclk_kHz; + + i2c->BUSCTL &= ~I2C_BUSCTL_TIDLE_Msk; + + /* DIV4 disabled */ + i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk; + u32Pclk_kHz = u32Pclk / 1000U; + u32Div = ((ms * u32Pclk_kHz) / (16U * 1024U)) - 1U; + if(u32Div <= 0xFFU) + { + i2c->BUSTOUT = u32Div; + } + else + { + /* DIV4 enabled */ + i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk; + i2c->BUSTOUT = (((ms * u32Pclk_kHz) / (16U * 1024U * 4U)) - 1U) & 0xFFU; /* The max value is 255 */ + } +} + +/** + * @brief Calculate Cumulative Clock low Time-out of SMBus active period + * + * @param[in] i2c Specify I2C port + * @param[in] ms Time-out length(ms) + * @param[in] u32Pclk peripheral clock frequency + * + * @return None + * + * @details This function is used to set SMBus Time-out length when bus is in Active state. + * Time-out length is calculate the SCL line "clocks" low cumulative timing. + * + */ + +void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk) +{ + uint32_t u32Div, u32Pclk_kHz; + + i2c->BUSCTL &= ~I2C_BUSCTL_TIDLE_Msk; + + /* DIV4 disabled */ + i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk; + u32Pclk_kHz = u32Pclk / 1000U; + u32Div = ((ms * u32Pclk_kHz) / (16U * 1024U)) - 1U; + if(u32Div <= 0xFFU) + { + i2c->CLKTOUT = u32Div; + } + else + { + /* DIV4 enabled */ + i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk; + i2c->CLKTOUT = (((ms * u32Pclk_kHz) / (16U * 1024U * 4U)) - 1U) & 0xFFU; /* The max value is 255 */ + } +} + + +/** + * @brief Write a byte to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] data Write a byte data to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for I2C Master write a byte data to Slave. + * + */ + +uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + + I2C_START(i2c); + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, data); /* Write data to I2CDAT */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return (u8Err | u8Xfering); /* return (Success)/(Fail) status */ +} + +/** + * @brief Write multi bytes to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] *data Pointer to array to write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for I2C Master write multi bytes data to Slave. + * + */ + +uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data[], uint32_t u32wLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + uint32_t u32txLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + case 0x28u: + if(u32txLen < u32wLen) + { + I2C_SET_DATA(i2c, data[u32txLen++]); /* Write Data to I2CDAT */ + } + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + } + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Specify a byte register address and write a byte to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 byte) of data write to + * @param[in] data A byte data to write it to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for I2C Master specify a address that data write to in Slave. + * + */ + +uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + uint32_t u32txLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Send Slave address with write bit */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if(u32txLen < 1u) + { + I2C_SET_DATA(i2c, data); + u32txLen++; + } + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + } + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return (u8Err | u8Xfering); /* return (Success)/(Fail) status */ +} + + +/** + * @brief Specify a byte register address and write multi bytes to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 byte) of data write to + * @param[in] *data Pointer to array to write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for I2C Master specify a byte address that multi data bytes write to in Slave. + * + */ + +uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data[], uint32_t u32wLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + uint32_t u32txLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if(u32txLen < u32wLen) + { + I2C_SET_DATA(i2c, data[u32txLen++]); + } + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + } + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Specify two bytes register address and Write a byte to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 byte) of data write to + * @param[in] data Write a byte data to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for I2C Master specify two bytes address that data write to in Slave. + * + */ + +uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u; + uint32_t u32txLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if(u8Addr) + { + I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */ + u8Addr = 0u; + } + else if((u32txLen < 1u) && (u8Addr == 0u)) + { + I2C_SET_DATA(i2c, data); + u32txLen++; + } + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + } + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return (u8Err | u8Xfering); /* return (Success)/(Fail) status */ +} + + +/** + * @brief Specify two bytes register address and write multi bytes to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 bytes) of data write to + * @param[in] data[] A data array for write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for I2C Master specify a byte address that multi data write to in Slave. + * + */ + +uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data[], uint32_t u32wLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u; + uint32_t u32txLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if(u8Addr) + { + I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */ + u8Addr = 0u; + } + else if((u32txLen < u32wLen) && (u8Addr == 0u)) + { + I2C_SET_DATA(i2c, data[u32txLen++]); /* Write data to Register I2CDAT*/ + } + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + } + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Read a byte from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * + * @return Read a byte data from Slave + * + * @details The function is used for I2C Master to read a byte data from Slave. + * + */ +uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, rdata = 0u, u8Ctrl = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x58u: + rdata = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + if(u8Err) + { + rdata = 0u; /* If occurs error, return 0 */ + } + return rdata; /* Return read data */ +} + + +/** + * @brief Read multi bytes from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[out] rdata[] A data array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for I2C Master to read multi data bytes from Slave. + * + * + */ +uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t rdata[], uint32_t u32rLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + uint32_t u32rxLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x50u: + rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + if(u32rxLen < (u32rLen - 1u)) + { + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + } + else + { + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + } + break; + case 0x58u: + rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return u32rxLen; /* Return bytes length that have been received */ +} + + +/** + * @brief Specify a byte register address and read a byte from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address(1 byte) of data read from + * + * @return Read a byte data from Slave + * + * @details The function is used for I2C Master specify a byte address that a data byte read from Slave. + * + * + */ +uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, rdata = 0u, u8Ctrl = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + u8Ctrl = I2C_CTL_STA_SI; /* Send repeat START */ + break; + case 0x10u: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x58u: + rdata = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + if(u8Err) + { + rdata = 0u; /* If occurs error, return 0 */ + } + return rdata; /* Return read data */ +} + +/** + * @brief Specify a byte register address and read multi bytes from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 bytes) of data read from + * @param[out] rdata[] A data array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for I2C Master specify a byte address that multi data bytes read from Slave. + * + * + */ +uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t rdata[], uint32_t u32rLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + uint32_t u32rxLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + u8Ctrl = I2C_CTL_STA_SI; /* Send repeat START */ + break; + case 0x10u: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x50u: + rdata[u32rxLen++] = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */ + if(u32rxLen < (u32rLen - 1u)) + { + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + } + else + { + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + } + break; + case 0x58u: + rdata[u32rxLen++] = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return u32rxLen; /* Return bytes length that have been received */ +} + +/** + * @brief Specify two bytes register address and read a byte from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify an address(2 bytes) of data read from + * + * @return Read a byte data from Slave + * + * @details The function is used for I2C Master specify two bytes address that a data byte read from Slave. + * + * + */ +uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, rdata = 0u, u8Addr = 1u, u8Ctrl = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if(u8Addr) + { + I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */ + u8Addr = 0u; + } + else + { + u8Ctrl = I2C_CTL_STA_SI; /* Clear SI and send repeat START */ + } + break; + case 0x10u: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x58u: + rdata = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + if(u8Err) + { + rdata = 0u; /* If occurs error, return 0 */ + } + return rdata; /* Return read data */ +} + +/** + * @brief Specify two bytes register address and read multi bytes from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 bytes) of data read from + * @param[out] rdata[] A data array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for I2C Master specify two bytes address that multi data bytes read from Slave. + * + * + */ +uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t rdata[], uint32_t u32rLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u; + uint32_t u32rxLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if(u8Addr) + { + I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */ + u8Addr = 0u; + } + else + { + u8Ctrl = I2C_CTL_STA_SI; /* Clear SI and send repeat START */ + } + break; + case 0x10u: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x50u: + rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + if(u32rxLen < (u32rLen - 1u)) + { + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + } + else + { + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + } + break; + case 0x58u: + rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return u32rxLen; /* Return bytes length that have been received */ +} + + +/*@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group I2C_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_i2s.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_i2s.c new file mode 100644 index 0000000000000000000000000000000000000000..6e0e5bb6f2b7437d03efefae64c95a6c5f562487 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_i2s.c @@ -0,0 +1,250 @@ +/**************************************************************************//** + * @file i2s.c + * @version V0.10 + * @brief M480 I2S driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup I2S_Driver I2S Driver + @{ +*/ + +/** @addtogroup I2S_EXPORTED_FUNCTIONS I2S Exported Functions + @{ +*/ + +static uint32_t I2S_GetSourceClockFreq(I2S_T *i2s); + +/** + * @brief This function is used to get I2S source clock frequency. + * @param[in] i2s is the base address of I2S module. + * @return I2S source clock frequency (Hz). + */ +static uint32_t I2S_GetSourceClockFreq(I2S_T *i2s) +{ + uint32_t u32Freq, u32ClkSrcSel; + + /* get I2S selection clock source */ + u32ClkSrcSel = CLK->CLKSEL3 & CLK_CLKSEL3_I2S0SEL_Msk; + + switch (u32ClkSrcSel) + { + case CLK_CLKSEL3_I2S0SEL_HXT: + u32Freq = __HXT; + break; + + case CLK_CLKSEL3_I2S0SEL_PLL: + u32Freq = CLK_GetPLLClockFreq(); + break; + + case CLK_CLKSEL3_I2S0SEL_HIRC: + u32Freq = __HIRC; + break; + + case CLK_CLKSEL3_I2S0SEL_PCLK0: + u32Freq = (uint32_t)CLK_GetPCLK0Freq(); + break; + + default: + u32Freq = __HIRC; + break; + } + + return u32Freq; +} + +/** + * @brief This function configures some parameters of I2S interface for general purpose use. + * The sample rate may not be used from the parameter, it depends on system's clock settings, + * but real sample rate used by system will be returned for reference. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32MasterSlave I2S operation mode. Valid values are: + * - \ref I2S_MODE_MASTER + * - \ref I2S_MODE_SLAVE + * @param[in] u32SampleRate Sample rate + * @param[in] u32WordWidth Data length. Valid values are: + * - \ref I2S_DATABIT_8 + * - \ref I2S_DATABIT_16 + * - \ref I2S_DATABIT_24 + * - \ref I2S_DATABIT_32 + * @param[in] u32MonoData: Set audio data to mono or not. Valid values are: + * - \ref I2S_ENABLE_MONO + * - \ref I2S_DISABLE_MONO + * @param[in] u32DataFormat: Data format. This is also used to select I2S or PCM(TDM) function. Valid values are: + * - \ref I2S_FORMAT_I2S + * - \ref I2S_FORMAT_I2S_MSB + * - \ref I2S_FORMAT_I2S_LSB + * - \ref I2S_FORMAT_PCM + * - \ref I2S_FORMAT_PCM_MSB + * - \ref I2S_FORMAT_PCM_LSB + * @return Real sample rate. + */ +uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32MonoData, uint32_t u32DataFormat) +{ + uint16_t u16Divider; + uint32_t u32BitRate, u32SrcClk; + + SYS->IPRST1 |= SYS_IPRST1_I2S0RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_I2S0RST_Msk; + + i2s->CTL0 = u32MasterSlave | u32WordWidth | u32MonoData | u32DataFormat; + i2s->CTL1 = I2S_FIFO_TX_LEVEL_WORD_8 | I2S_FIFO_RX_LEVEL_WORD_8; + + u32SrcClk = I2S_GetSourceClockFreq(i2s); + + u32BitRate = u32SampleRate * (((u32WordWidth>>4U) & 0x3U) + 1U) * 16U; + //u16Divider = (uint16_t)((u32SrcClk/u32BitRate) >> 1U) - 1U; + u16Divider = (uint16_t)((((u32SrcClk * 10UL / u32BitRate) >> 1U) + 5UL) / 10UL) - 1U; + i2s->CLKDIV = (i2s->CLKDIV & ~I2S_CLKDIV_BCLKDIV_Msk) | ((uint32_t)u16Divider << 8U); + + /* calculate real sample rate */ + u32BitRate = u32SrcClk / (2U*((uint32_t)u16Divider+1U)); + u32SampleRate = u32BitRate / ((((u32WordWidth>>4U) & 0x3U) + 1U) * 16U); + + i2s->CTL0 |= I2S_CTL0_I2SEN_Msk; + + return u32SampleRate; +} + +/** + * @brief Disable I2S function and I2S clock. + * @param[in] i2s is the base address of I2S module. + * @return none + */ +void I2S_Close(I2S_T *i2s) +{ + i2s->CTL0 &= ~I2S_CTL0_I2SEN_Msk; +} + +/** + * @brief This function enables the interrupt according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * @return none + */ +void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask) +{ + i2s->IEN |= u32Mask; +} + +/** + * @brief This function disables the interrupt according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * @return none + */ +void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask) +{ + i2s->IEN &= ~u32Mask; +} + +/** + * @brief Enable MCLK . + * @param[in] i2s is the base address of I2S module. + * @param[in] u32BusClock is the target MCLK clock + * @return Actual MCLK clock + */ +uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock) +{ + uint8_t u8Divider; + uint32_t u32SrcClk, u32Reg, u32Clock; + + u32SrcClk = I2S_GetSourceClockFreq(i2s); + if (u32BusClock == u32SrcClk) + { + u8Divider = 0U; + } + else + { + u8Divider = (uint8_t)(u32SrcClk/u32BusClock) >> 1U; + } + + i2s->CLKDIV = (i2s->CLKDIV & ~I2S_CLKDIV_MCLKDIV_Msk) | u8Divider; + + i2s->CTL0 |= I2S_CTL0_MCLKEN_Msk; + + u32Reg = i2s->CLKDIV & I2S_CLKDIV_MCLKDIV_Msk; + + if (u32Reg == 0U) + { + u32Clock = u32SrcClk; + } + else + { + u32Clock = ((u32SrcClk >> 1U) / u32Reg); + } + + return u32Clock; +} + +/** + * @brief Disable MCLK . + * @param[in] i2s is the base address of I2S module. + * @return none + */ +void I2S_DisableMCLK(I2S_T *i2s) +{ + i2s->CTL0 &= ~I2S_CTL0_MCLKEN_Msk; +} + +/** + * @brief Configure FIFO threshold setting. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 7. + * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 7. + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold) +{ + i2s->CTL1 = ((i2s->CTL1 & ~(I2S_CTL1_TXTH_Msk | I2S_CTL1_RXTH_Msk)) | + (u32TxThreshold << I2S_CTL1_TXTH_Pos) | + (u32RxThreshold << I2S_CTL1_RXTH_Pos)); +} + + +/** + * @brief Configure PCM(TDM) function parameters, such as channel width, channel number and sync pulse width + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32ChannelWidth Channel width. Valid values are: + * - \ref I2S_TDM_WIDTH_8BIT + * - \ref I2S_TDM_WIDTH_16BIT + * - \ref I2S_TDM_WIDTH_24BIT + * - \ref I2S_TDM_WIDTH_32BIT + * @param[in] u32ChannelNum Channel number. Valid values are: + * - \ref I2S_TDM_2CH + * - \ref I2S_TDM_4CH + * - \ref I2S_TDM_6CH + * - \ref I2S_TDM_8CH + * @param[in] u32SyncWidth Width for sync pulse. Valid values are: + * - \ref I2S_TDM_SYNC_ONE_BCLK + * - \ref I2S_TDM_SYNC_ONE_CHANNEL + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void I2S_ConfigureTDM(I2S_T *i2s, uint32_t u32ChannelWidth, uint32_t u32ChannelNum, uint32_t u32SyncWidth) +{ + i2s->CTL0 = ((i2s->CTL0 & ~(I2S_CTL0_TDMCHNUM_Msk | I2S_CTL0_CHWIDTH_Msk | I2S_CTL0_PCMSYNC_Msk)) | + (u32ChannelWidth << I2S_CTL0_CHWIDTH_Pos) | + (u32ChannelNum << I2S_CTL0_TDMCHNUM_Pos) | + (u32SyncWidth << I2S_CTL0_PCMSYNC_Pos)); +} + +/*@}*/ /* end of group I2S_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group I2S_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_pdma.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_pdma.c new file mode 100644 index 0000000000000000000000000000000000000000..a4abf2f5e925e5ab89200720de41159f570607ac --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_pdma.c @@ -0,0 +1,487 @@ +/**************************************************************************//** + * @file pdma.c + * @version V1.00 + * @brief M480 series PDMA driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +static uint8_t u32ChSelect[PDMA_CH_MAX]; + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup PDMA_Driver PDMA Driver + @{ +*/ + + +/** @addtogroup PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions + @{ +*/ + +/** + * @brief PDMA Open + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @param[in] u32Mask Channel enable bits. + * + * @return None + * + * @details This function enable the PDMA channels. + */ +void PDMA_Open(PDMA_T * pdma,uint32_t u32Mask) +{ + uint32_t i; + + for (i=0UL; iDSCT[i].CTL = 0UL; + u32ChSelect[i] = PDMA_MEM; + } + } + + pdma->CHCTL |= u32Mask; +} + +/** + * @brief PDMA Close + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @return None + * + * @details This function disable all PDMA channels. + */ +void PDMA_Close(PDMA_T * pdma) +{ + pdma->CHCTL = 0UL; +} + +/** + * @brief Set PDMA Transfer Count + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Width Data width. Valid values are + * - \ref PDMA_WIDTH_8 + * - \ref PDMA_WIDTH_16 + * - \ref PDMA_WIDTH_32 + * @param[in] u32TransCount Transfer count + * + * @return None + * + * @details This function set the selected channel data width and transfer count. + */ +void PDMA_SetTransferCnt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount) +{ + pdma->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXCNT_Msk | PDMA_DSCT_CTL_TXWIDTH_Msk); + pdma->DSCT[u32Ch].CTL |= (u32Width | ((u32TransCount - 1UL) << PDMA_DSCT_CTL_TXCNT_Pos)); +} + +/** + * @brief Set PDMA Stride Mode + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32DestLen Destination stride count + * @param[in] u32SrcLen Source stride count + * @param[in] u32TransCount Transfer count + * + * @return None + * + * @details This function set the selected stride mode. + */ +void PDMA_SetStride(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32DestLen, uint32_t u32SrcLen, uint32_t u32TransCount) +{ + pdma->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_STRIDEEN_Msk; + pdma->STRIDE[u32Ch].ASOCR =((u32DestLen-1)<<16) | (u32SrcLen-1); + pdma->STRIDE[u32Ch].STCR = u32TransCount-1; +} + +/** + * @brief Set PDMA Repeat + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32DestInterval Destination address interval count + * @param[in] u32SrcInterval Source address interval count + * @param[in] u32RepeatCount Repeat count + * + * @return None + * + * @details This function set the selected repeat. + */ +void PDMA_SetRepeat(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32DestInterval, uint32_t u32SrcInterval, uint32_t u32RepeatCount) +{ + pdma->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_STRIDEEN_Msk; + pdma->REPEAT[u32Ch].AICTL =((u32DestInterval)<<16) | (u32SrcInterval); + pdma->REPEAT[u32Ch].RCNT = u32RepeatCount; +} + +/** + * @brief Set PDMA Transfer Address + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32SrcAddr Source address + * @param[in] u32SrcCtrl Source control attribute. Valid values are + * - \ref PDMA_SAR_INC + * - \ref PDMA_SAR_FIX + * @param[in] u32DstAddr destination address + * @param[in] u32DstCtrl destination control attribute. Valid values are + * - \ref PDMA_DAR_INC + * - \ref PDMA_DAR_FIX + * + * @return None + * + * @details This function set the selected channel source/destination address and attribute. + */ +void PDMA_SetTransferAddr(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl) +{ + pdma->DSCT[u32Ch].SA = u32SrcAddr; + pdma->DSCT[u32Ch].DA = u32DstAddr; + pdma->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_SAINC_Msk | PDMA_DSCT_CTL_DAINC_Msk); + pdma->DSCT[u32Ch].CTL |= (u32SrcCtrl | u32DstCtrl); +} + +/** + * @brief Set PDMA Transfer Mode + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Peripheral The selected peripheral. Valid values are + * - \ref PDMA_MEM + * - \ref PDMA_USB_TX + * - \ref PDMA_USB_RX + * - \ref PDMA_UART0_TX + * - \ref PDMA_UART0_RX + * - \ref PDMA_UART1_TX + * - \ref PDMA_UART1_RX + * - \ref PDMA_UART2_TX + * - \ref PDMA_UART2_RX + * - \ref PDMA_UART3_TX + * - \ref PDMA_UART3_RX + * - \ref PDMA_UART4_TX + * - \ref PDMA_UART4_RX + * - \ref PDMA_UART5_TX + * - \ref PDMA_UART5_RX + * - \ref PDMA_USCI0_TX + * - \ref PDMA_USCI0_RX + * - \ref PDMA_USCI1_TX + * - \ref PDMA_USCI1_RX + * - \ref PDMA_QSPI0_TX + * - \ref PDMA_QSPI0_RX + * - \ref PDMA_SPI0_TX + * - \ref PDMA_SPI0_RX + * - \ref PDMA_SPI1_TX + * - \ref PDMA_SPI1_RX + * - \ref PDMA_SPI2_TX + * - \ref PDMA_SPI2_RX + * - \ref PDMA_SPI3_TX + * - \ref PDMA_SPI3_RX + * - \ref PDMA_EPWM0_P1_RX + * - \ref PDMA_EPWM0_P2_RX + * - \ref PDMA_EPWM0_P3_RX + * - \ref PDMA_EPWM1_P1_RX + * - \ref PDMA_EPWM1_P2_RX + * - \ref PDMA_EPWM1_P3_RX + * - \ref PDMA_I2C0_TX + * - \ref PDMA_I2C0_RX + * - \ref PDMA_I2C1_TX + * - \ref PDMA_I2C1_RX + * - \ref PDMA_I2C2_TX + * - \ref PDMA_I2C2_RX + * - \ref PDMA_I2S0_TX + * - \ref PDMA_I2S0_RX + * - \ref PDMA_TMR0 + * - \ref PDMA_TMR1 + * - \ref PDMA_TMR2 + * - \ref PDMA_TMR3 + * - \ref PDMA_EADC0_RX + * - \ref PDMA_DAC0_TX + * - \ref PDMA_DAC1_TX + * - \ref PDMA_EPWM0_CH0_TX + * - \ref PDMA_EPWM0_CH1_TX + * - \ref PDMA_EPWM0_CH2_TX + * - \ref PDMA_EPWM0_CH3_TX + * - \ref PDMA_EPWM0_CH4_TX + * - \ref PDMA_EPWM0_CH5_TX + * - \ref PDMA_EPWM1_CH0_TX + * - \ref PDMA_EPWM1_CH1_TX + * - \ref PDMA_EPWM1_CH2_TX + * - \ref PDMA_EPWM1_CH3_TX + * - \ref PDMA_EPWM1_CH4_TX + * - \ref PDMA_EPWM1_CH5_TX + * - \ref PDMA_UART6_TX + * - \ref PDMA_UART6_RX + * - \ref PDMA_UART7_TX + * - \ref PDMA_UART7_RX + * - \ref PDMA_EADC1_RX + * @param[in] u32ScatterEn Scatter-gather mode enable + * @param[in] u32DescAddr Scatter-gather descriptor address + * + * @return None + * + * @details This function set the selected channel transfer mode. Include peripheral setting. + */ +void PDMA_SetTransferMode(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr) +{ + u32ChSelect[u32Ch] = u32Peripheral; + switch(u32Ch) + { + case 0ul: + pdma->REQSEL0_3 = (pdma->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC0_Msk) | u32Peripheral; + break; + case 1ul: + pdma->REQSEL0_3 = (pdma->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC1_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC1_Pos); + break; + case 2ul: + pdma->REQSEL0_3 = (pdma->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC2_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC2_Pos); + break; + case 3ul: + pdma->REQSEL0_3 = (pdma->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC3_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC3_Pos); + break; + case 4ul: + pdma->REQSEL4_7 = (pdma->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC4_Msk) | u32Peripheral; + break; + case 5ul: + pdma->REQSEL4_7 = (pdma->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC5_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC5_Pos); + break; + case 6ul: + pdma->REQSEL4_7 = (pdma->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC6_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC6_Pos); + break; + case 7ul: + pdma->REQSEL4_7 = (pdma->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC7_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC7_Pos); + break; + case 8ul: + pdma->REQSEL8_11 = (pdma->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC8_Msk) | u32Peripheral; + break; + case 9ul: + pdma->REQSEL8_11 = (pdma->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC9_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC9_Pos); + break; + case 10ul: + pdma->REQSEL8_11 = (pdma->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC10_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC10_Pos); + break; + case 11ul: + pdma->REQSEL8_11 = (pdma->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC11_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC11_Pos); + break; + case 12ul: + pdma->REQSEL12_15 = (pdma->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC12_Msk) | u32Peripheral; + break; + case 13ul: + pdma->REQSEL12_15 = (pdma->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC13_Msk) | (u32Peripheral << PDMA_REQSEL12_15_REQSRC13_Pos); + break; + case 14ul: + pdma->REQSEL12_15 = (pdma->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC14_Msk) | (u32Peripheral << PDMA_REQSEL12_15_REQSRC14_Pos); + break; + case 15ul: + pdma->REQSEL12_15 = (pdma->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC15_Msk) | (u32Peripheral << PDMA_REQSEL12_15_REQSRC15_Pos); + break; + default: + break; + } + + if(u32ScatterEn) + { + pdma->DSCT[u32Ch].CTL = (pdma->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_SCATTER; + pdma->DSCT[u32Ch].NEXT = u32DescAddr - (PDMA->SCATBA); + } + else + { + pdma->DSCT[u32Ch].CTL = (pdma->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_BASIC; + } +} + +/** + * @brief Set PDMA Burst Type and Size + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32BurstType Burst mode or single mode. Valid values are + * - \ref PDMA_REQ_SINGLE + * - \ref PDMA_REQ_BURST + * @param[in] u32BurstSize Set the size of burst mode. Valid values are + * - \ref PDMA_BURST_128 + * - \ref PDMA_BURST_64 + * - \ref PDMA_BURST_32 + * - \ref PDMA_BURST_16 + * - \ref PDMA_BURST_8 + * - \ref PDMA_BURST_4 + * - \ref PDMA_BURST_2 + * - \ref PDMA_BURST_1 + * + * @return None + * + * @details This function set the selected channel burst type and size. + */ +void PDMA_SetBurstType(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize) +{ + pdma->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXTYPE_Msk | PDMA_DSCT_CTL_BURSIZE_Msk); + pdma->DSCT[u32Ch].CTL |= (u32BurstType | u32BurstSize); +} + +/** + * @brief Enable timeout function + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @param[in] u32Mask Channel enable bits. + * + * @return None + * + * @details This function enable timeout function of the selected channel(s). + */ +void PDMA_EnableTimeout(PDMA_T * pdma,uint32_t u32Mask) +{ + pdma->TOUTEN |= u32Mask; +} + +/** + * @brief Disable timeout function + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @param[in] u32Mask Channel enable bits. + * + * @return None + * + * @details This function disable timeout function of the selected channel(s). + */ +void PDMA_DisableTimeout(PDMA_T * pdma,uint32_t u32Mask) +{ + pdma->TOUTEN &= ~u32Mask; +} + +/** + * @brief Set PDMA Timeout Count + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel, + * @param[in] u32OnOff Enable/disable time out function + * @param[in] u32TimeOutCnt Timeout count + * + * @return None + * + * @details This function set the timeout count. + * @note M480 only supported channel 0/1. + */ +void PDMA_SetTimeOut(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt) +{ + switch(u32Ch) + { + case 0ul: + pdma->TOC0_1 = (pdma->TOC0_1 & ~PDMA_TOC0_1_TOC0_Msk) | u32TimeOutCnt; + break; + case 1ul: + pdma->TOC0_1 = (pdma->TOC0_1 & ~PDMA_TOC0_1_TOC1_Msk) | (u32TimeOutCnt << PDMA_TOC0_1_TOC1_Pos); + break; + default: + break; + } + + if (u32OnOff) + pdma->TOUTEN |= (1 << u32Ch); + else + pdma->TOUTEN &= ~(1 << u32Ch); +} + +/** + * @brief Trigger PDMA + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details This function trigger the selected channel. + */ +void PDMA_Trigger(PDMA_T * pdma,uint32_t u32Ch) +{ + if(u32ChSelect[u32Ch] == PDMA_MEM) + { + pdma->SWREQ = (1ul << u32Ch); + } + else {} +} + +/** + * @brief Enable Interrupt + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Mask The Interrupt Type. Valid values are + * - \ref PDMA_INT_TRANS_DONE + * - \ref PDMA_INT_TEMPTY + * - \ref PDMA_INT_TIMEOUT + * + * @return None + * + * @details This function enable the selected channel interrupt. + */ +void PDMA_EnableInt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Mask) +{ + switch(u32Mask) + { + case PDMA_INT_TRANS_DONE: + pdma->INTEN |= (1ul << u32Ch); + break; + case PDMA_INT_TEMPTY: + pdma->DSCT[u32Ch].CTL &= ~PDMA_DSCT_CTL_TBINTDIS_Msk; + break; + case PDMA_INT_TIMEOUT: + pdma->TOUTIEN |= (1ul << u32Ch); + break; + + default: + break; + } +} + +/** + * @brief Disable Interrupt + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Mask The Interrupt Type. Valid values are + * - \ref PDMA_INT_TRANS_DONE + * - \ref PDMA_INT_TEMPTY + * - \ref PDMA_INT_TIMEOUT + * + * @return None + * + * @details This function disable the selected channel interrupt. + */ +void PDMA_DisableInt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Mask) +{ + switch(u32Mask) + { + case PDMA_INT_TRANS_DONE: + pdma->INTEN &= ~(1ul << u32Ch); + break; + case PDMA_INT_TEMPTY: + pdma->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_TBINTDIS_Msk; + break; + case PDMA_INT_TIMEOUT: + pdma->TOUTIEN &= ~(1ul << u32Ch); + break; + + default: + break; + } +} + +/*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group PDMA_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2014~2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_qei.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_qei.c new file mode 100644 index 0000000000000000000000000000000000000000..225b7e16737a6e96206c47ab82c3c1d8e43028de --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_qei.c @@ -0,0 +1,144 @@ +/**************************************************************************//** + * @file qei.c + * @version V3.00 + * @brief Quadrature Encoder Interface (QEI) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup QEI_Driver QEI Driver + @{ +*/ + +/** @addtogroup QEI_EXPORTED_FUNCTIONS QEI Exported Functions + @{ +*/ + +/** + * @brief Close QEI function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This function reset QEI configuration and stop QEI counting. + */ +void QEI_Close(QEI_T* qei) +{ + /* Reset QEI configuration */ + qei->CTL = (uint32_t)0; +} + +/** + * @brief Disable QEI interrupt + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. + * - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt + * - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt + * - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt + * - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt + * @return None + * @details This function disable QEI specified interrupt. + */ +void QEI_DisableInt(QEI_T* qei, uint32_t u32IntSel) +{ + /* Disable QEI specified interrupt */ + QEI_DISABLE_INT(qei, u32IntSel); + + /* Disable NVIC QEI IRQ */ + if(qei ==(QEI_T*)QEI0) + { + NVIC_DisableIRQ((IRQn_Type)QEI0_IRQn); + } + else + { + NVIC_DisableIRQ((IRQn_Type)QEI1_IRQn); + } +} + +/** + * @brief Enable QEI interrupt + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. + * - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt + * - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt + * - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt + * - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt + * @return None + * @details This function enable QEI specified interrupt. + */ +void QEI_EnableInt(QEI_T* qei, uint32_t u32IntSel) +{ + /* Enable QEI specified interrupt */ + QEI_ENABLE_INT(qei, u32IntSel); + + /* Enable NVIC QEI IRQ */ + if(qei == (QEI_T*)QEI0) + { + NVIC_EnableIRQ(QEI0_IRQn); + } + else + { + NVIC_EnableIRQ(QEI1_IRQn); + } +} + +/** + * @brief Open QEI in specified mode and enable input + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Mode QEI counting mode. + * - \ref QEI_CTL_X4_FREE_COUNTING_MODE + * - \ref QEI_CTL_X2_FREE_COUNTING_MODE + * - \ref QEI_CTL_X4_COMPARE_COUNTING_MODE + * - \ref QEI_CTL_X2_COMPARE_COUNTING_MODE + * @param[in] u32Value The counter maximum value in compare-counting mode. + * @return None + * @details This function set QEI in specified mode and enable input. + */ +void QEI_Open(QEI_T* qei, uint32_t u32Mode, uint32_t u32Value) +{ + /* Set QEI function configuration */ + /* Set QEI counting mode */ + /* Enable IDX, QEA and QEB input to QEI controller */ + qei->CTL = (qei->CTL & (~QEI_CTL_MODE_Msk)) | ((u32Mode) | QEI_CTL_CHAEN_Msk | QEI_CTL_CHBEN_Msk | QEI_CTL_IDXEN_Msk); + + /* Set QEI maximum count value in in compare-counting mode */ + qei->CNTMAX = u32Value; +} + +/** + * @brief Start QEI function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This function enable QEI function and start QEI counting. + */ +void QEI_Start(QEI_T* qei) +{ + /* Enable QEI controller function */ + qei->CTL |= QEI_CTL_QEIEN_Msk; +} + +/** + * @brief Stop QEI function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This function disable QEI function and stop QEI counting. + */ +void QEI_Stop(QEI_T* qei) +{ + /* Disable QEI controller function */ + qei->CTL &= (~QEI_CTL_QEIEN_Msk); +} + + +/*@}*/ /* end of group QEI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group QEI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_qspi.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_qspi.c new file mode 100644 index 0000000000000000000000000000000000000000..b0f3ff2b5a3cc606b35ae5b84aeb90b96da8585f --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_qspi.c @@ -0,0 +1,856 @@ +/**************************************************************************//** + * @file qspi.c + * @version V3.00 + * @brief M480 series QSPI driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup QSPI_Driver QSPI Driver + @{ +*/ + + +/** @addtogroup QSPI_EXPORTED_FUNCTIONS QSPI Exported Functions + @{ +*/ + +/** + * @brief This function make QSPI module be ready to transfer. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32MasterSlave Decides the QSPI module is operating in master mode or in slave mode. (QSPI_SLAVE, QSPI_MASTER) + * @param[in] u32QSPIMode Decides the transfer timing. (QSPI_MODE_0, QSPI_MODE_1, QSPI_MODE_2, QSPI_MODE_3) + * @param[in] u32DataWidth Decides the data width of a QSPI transaction. + * @param[in] u32BusClock The expected frequency of QSPI bus clock in Hz. + * @return Actual frequency of QSPI peripheral clock. + * @details By default, the QSPI transfer sequence is MSB first, the slave selection signal is active low and the automatic + * slave selection function is disabled. + * In Slave mode, the u32BusClock shall be NULL and the QSPI clock divider setting will be 0. + * The actual clock rate may be different from the target QSPI clock rate. + * For example, if the QSPI source clock rate is 12 MHz and the target QSPI bus clock rate is 7 MHz, the + * actual QSPI clock rate will be 6MHz. + * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value. + * @note If u32BusClock >= system clock frequency, QSPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0. + * @note If u32BusClock >= QSPI peripheral clock source, DIVIDER will be set to 0. + * @note In slave mode, the QSPI peripheral clock rate will be equal to APB clock rate. + */ +uint32_t QSPI_Open(QSPI_T *qspi, + uint32_t u32MasterSlave, + uint32_t u32QSPIMode, + uint32_t u32DataWidth, + uint32_t u32BusClock) +{ + uint32_t u32ClkSrc = 0U, u32Div, u32HCLKFreq, u32RetValue=0U; + + if(u32DataWidth == 32U) + { + u32DataWidth = 0U; + } + + /* Get system clock frequency */ + u32HCLKFreq = CLK_GetHCLKFreq(); + + if(u32MasterSlave == QSPI_MASTER) + { + /* Default setting: slave selection signal is active low; disable automatic slave selection function. */ + qspi->SSCTL = QSPI_SS_ACTIVE_LOW; + + /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */ + qspi->CTL = u32MasterSlave | (u32DataWidth << QSPI_CTL_DWIDTH_Pos) | (u32QSPIMode) | QSPI_CTL_QSPIEN_Msk; + + if(u32BusClock >= u32HCLKFreq) + { + /* Select PCLK as the clock source of QSPI */ + if (qspi == QSPI0) + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0; + else if (qspi == QSPI1) + CLK->CLKSEL3 = (CLK->CLKSEL3 & (~CLK_CLKSEL3_QSPI1SEL_Msk)) | CLK_CLKSEL3_QSPI1SEL_PCLK1; + } + + /* Check clock source of QSPI */ + if (qspi == QSPI0) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0) + { + /* Clock source is PCLK0 */ + u32ClkSrc = CLK_GetPCLK0Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if (qspi == QSPI1) + { + if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_PCLK1) + { + /* Clock source is PCLK1 */ + u32ClkSrc = CLK_GetPCLK1Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + + if(u32BusClock >= u32HCLKFreq) + { + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock >= u32ClkSrc) + { + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock == 0U) + { + /* Set DIVIDER to the maximum value 0xFF. f_qspi = f_qspi_clk_src / (DIVIDER + 1) */ + qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0xFFU + 1U)); + } + else + { + u32Div = (((u32ClkSrc * 10U) / u32BusClock + 5U) / 10U) - 1U; /* Round to the nearest integer */ + if(u32Div > 0xFFU) + { + u32Div = 0xFFU; + qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0xFFU + 1U)); + } + else + { + qspi->CLKDIV = (qspi->CLKDIV & (~QSPI_CLKDIV_DIVIDER_Msk)) | (u32Div << QSPI_CLKDIV_DIVIDER_Pos); + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (u32Div + 1U)); + } + } + } + else /* For slave mode, force the QSPI peripheral clock rate to equal APB clock rate. */ + { + /* Default setting: slave selection signal is low level active. */ + qspi->SSCTL = QSPI_SS_ACTIVE_LOW; + + /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */ + qspi->CTL = u32MasterSlave | (u32DataWidth << QSPI_CTL_DWIDTH_Pos) | (u32QSPIMode) | QSPI_CTL_QSPIEN_Msk; + + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0U; + + /* Select PCLK as the clock source of QSPI */ + if (qspi == QSPI0) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0; + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK0Freq(); + } + else if (qspi == QSPI1) + { + CLK->CLKSEL3 = (CLK->CLKSEL3 & (~CLK_CLKSEL3_QSPI1SEL_Msk)) | CLK_CLKSEL3_QSPI1SEL_PCLK1; + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK1Freq(); + } + } + + return u32RetValue; +} + +/** + * @brief Disable QSPI controller. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None + * @details This function will reset QSPI controller. + */ +void QSPI_Close(QSPI_T *qspi) +{ + /* Reset QSPI */ + if (qspi == QSPI0) + { + SYS->IPRST1 |= SYS_IPRST1_QSPI0RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_QSPI0RST_Msk; + } + else if (qspi == QSPI1) + { + SYS->IPRST2 |= SYS_IPRST2_QSPI1RST_Msk; + SYS->IPRST2 &= ~SYS_IPRST2_QSPI1RST_Msk; + } +} + +/** + * @brief Clear RX FIFO buffer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None + * @details This function will clear QSPI RX FIFO buffer. The RXEMPTY (QSPI_STATUS[8]) will be set to 1. + */ +void QSPI_ClearRxFIFO(QSPI_T *qspi) +{ + qspi->FIFOCTL |= QSPI_FIFOCTL_RXFBCLR_Msk; +} + +/** + * @brief Clear TX FIFO buffer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None + * @details This function will clear QSPI TX FIFO buffer. The TXEMPTY (QSPI_STATUS[16]) will be set to 1. + * @note The TX shift register will not be cleared. + */ +void QSPI_ClearTxFIFO(QSPI_T *qspi) +{ + qspi->FIFOCTL |= QSPI_FIFOCTL_TXFBCLR_Msk; +} + +/** + * @brief Disable the automatic slave selection function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None + * @details This function will disable the automatic slave selection function and set slave selection signal to inactive state. + */ +void QSPI_DisableAutoSS(QSPI_T *qspi) +{ + qspi->SSCTL &= ~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SS_Msk); +} + +/** + * @brief Enable the automatic slave selection function. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32SSPinMask Specifies slave selection pins. (QSPI_SS) + * @param[in] u32ActiveLevel Specifies the active level of slave selection signal. (QSPI_SS_ACTIVE_HIGH, QSPI_SS_ACTIVE_LOW) + * @return None + * @details This function will enable the automatic slave selection function. Only available in Master mode. + * The slave selection pin and the active level will be set in this function. + */ +void QSPI_EnableAutoSS(QSPI_T *qspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel) +{ + qspi->SSCTL = (qspi->SSCTL & (~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SSACTPOL_Msk | QSPI_SSCTL_SS_Msk))) | (u32SSPinMask | u32ActiveLevel | QSPI_SSCTL_AUTOSS_Msk); +} + +/** + * @brief Set the QSPI bus clock. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32BusClock The expected frequency of QSPI bus clock in Hz. + * @return Actual frequency of QSPI bus clock. + * @details This function is only available in Master mode. The actual clock rate may be different from the target QSPI bus clock rate. + * For example, if the QSPI source clock rate is 12 MHz and the target QSPI bus clock rate is 7 MHz, the actual QSPI bus clock + * rate will be 6 MHz. + * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value. + * @note If u32BusClock >= system clock frequency, QSPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0. + * @note If u32BusClock >= QSPI peripheral clock source, DIVIDER will be set to 0. + */ +uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock) +{ + uint32_t u32ClkSrc, u32HCLKFreq; + uint32_t u32Div, u32RetValue; + + /* Get system clock frequency */ + u32HCLKFreq = CLK_GetHCLKFreq(); + + if(u32BusClock >= u32HCLKFreq) + { + /* Select PCLK as the clock source of QSPI */ + if (qspi == QSPI0) + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0; + else if (qspi == QSPI1) + CLK->CLKSEL3 = (CLK->CLKSEL3 & (~CLK_CLKSEL3_QSPI1SEL_Msk)) | CLK_CLKSEL3_QSPI1SEL_PCLK1; + } + + /* Check clock source of QSPI */ + if (qspi == QSPI0) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0) + { + /* Clock source is PCLK0 */ + u32ClkSrc = CLK_GetPCLK0Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if (qspi == QSPI1) + { + if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_PCLK1) + { + /* Clock source is PCLK1 */ + u32ClkSrc = CLK_GetPCLK1Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + + if(u32BusClock >= u32HCLKFreq) + { + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock >= u32ClkSrc) + { + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock == 0U) + { + /* Set DIVIDER to the maximum value 0xFF. f_qspi = f_qspi_clk_src / (DIVIDER + 1) */ + qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0xFFU + 1U)); + } + else + { + u32Div = (((u32ClkSrc * 10U) / u32BusClock + 5U) / 10U) - 1U; /* Round to the nearest integer */ + if(u32Div > 0x1FFU) + { + u32Div = 0x1FFU; + qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0xFFU + 1U)); + } + else + { + qspi->CLKDIV = (qspi->CLKDIV & (~QSPI_CLKDIV_DIVIDER_Msk)) | (u32Div << QSPI_CLKDIV_DIVIDER_Pos); + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (u32Div + 1U)); + } + } + + return u32RetValue; +} + +/** + * @brief Configure FIFO threshold setting. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 7. + * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 7. + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void QSPI_SetFIFO(QSPI_T *qspi, uint32_t u32TxThreshold, uint32_t u32RxThreshold) +{ + qspi->FIFOCTL = (qspi->FIFOCTL & ~(QSPI_FIFOCTL_TXTH_Msk | QSPI_FIFOCTL_RXTH_Msk)) | + (u32TxThreshold << QSPI_FIFOCTL_TXTH_Pos) | + (u32RxThreshold << QSPI_FIFOCTL_RXTH_Pos); +} + +/** + * @brief Get the actual frequency of QSPI bus clock. Only available in Master mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return Actual QSPI bus clock frequency in Hz. + * @details This function will calculate the actual QSPI bus clock rate according to the QSPInSEL and DIVIDER settings. Only available in Master mode. + */ +uint32_t QSPI_GetBusClock(QSPI_T *qspi) +{ + uint32_t u32Div; + uint32_t u32ClkSrc; + + /* Get DIVIDER setting */ + u32Div = (qspi->CLKDIV & QSPI_CLKDIV_DIVIDER_Msk) >> QSPI_CLKDIV_DIVIDER_Pos; + + /* Check clock source of QSPI */ + if (qspi == QSPI0) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0) + { + /* Clock source is PCLK0 */ + u32ClkSrc = CLK_GetPCLK0Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if (qspi == QSPI1) + { + if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_PCLK1) + { + /* Clock source is PCLK1 */ + u32ClkSrc = CLK_GetPCLK1Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + + /* Return QSPI bus clock rate */ + return (u32ClkSrc / (u32Div + 1U)); +} + +/** + * @brief Enable interrupt function. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. It is combination of: + * - \ref QSPI_UNIT_INT_MASK + * - \ref QSPI_SSACT_INT_MASK + * - \ref QSPI_SSINACT_INT_MASK + * - \ref QSPI_SLVUR_INT_MASK + * - \ref QSPI_SLVBE_INT_MASK + * - \ref QSPI_TXUF_INT_MASK + * - \ref QSPI_FIFO_TXTH_INT_MASK + * - \ref QSPI_FIFO_RXTH_INT_MASK + * - \ref QSPI_FIFO_RXOV_INT_MASK + * - \ref QSPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Enable QSPI related interrupts specified by u32Mask parameter. + */ +void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask) +{ + /* Enable unit transfer interrupt flag */ + if((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK) + { + qspi->CTL |= QSPI_CTL_UNITIEN_Msk; + } + + /* Enable slave selection signal active interrupt flag */ + if((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK) + { + qspi->SSCTL |= QSPI_SSCTL_SSACTIEN_Msk; + } + + /* Enable slave selection signal inactive interrupt flag */ + if((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK) + { + qspi->SSCTL |= QSPI_SSCTL_SSINAIEN_Msk; + } + + /* Enable slave TX under run interrupt flag */ + if((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK) + { + qspi->SSCTL |= QSPI_SSCTL_SLVURIEN_Msk; + } + + /* Enable slave bit count error interrupt flag */ + if((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK) + { + qspi->SSCTL |= QSPI_SSCTL_SLVBEIEN_Msk; + } + + /* Enable slave TX underflow interrupt flag */ + if((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Enable TX threshold interrupt flag */ + if((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Enable RX threshold interrupt flag */ + if((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Enable RX overrun interrupt flag */ + if((u32Mask & QSPI_FIFO_RXOV_INT_MASK) == QSPI_FIFO_RXOV_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Enable RX time-out interrupt flag */ + if((u32Mask & QSPI_FIFO_RXTO_INT_MASK) == QSPI_FIFO_RXTO_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_RXTOIEN_Msk; + } +} + +/** + * @brief Disable interrupt function. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * This parameter decides which interrupts will be disabled. It is combination of: + * - \ref QSPI_UNIT_INT_MASK + * - \ref QSPI_SSACT_INT_MASK + * - \ref QSPI_SSINACT_INT_MASK + * - \ref QSPI_SLVUR_INT_MASK + * - \ref QSPI_SLVBE_INT_MASK + * - \ref QSPI_TXUF_INT_MASK + * - \ref QSPI_FIFO_TXTH_INT_MASK + * - \ref QSPI_FIFO_RXTH_INT_MASK + * - \ref QSPI_FIFO_RXOV_INT_MASK + * - \ref QSPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Disable QSPI related interrupts specified by u32Mask parameter. + */ +void QSPI_DisableInt(QSPI_T *qspi, uint32_t u32Mask) +{ + /* Disable unit transfer interrupt flag */ + if((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK) + { + qspi->CTL &= ~QSPI_CTL_UNITIEN_Msk; + } + + /* Disable slave selection signal active interrupt flag */ + if((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK) + { + qspi->SSCTL &= ~QSPI_SSCTL_SSACTIEN_Msk; + } + + /* Disable slave selection signal inactive interrupt flag */ + if((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK) + { + qspi->SSCTL &= ~QSPI_SSCTL_SSINAIEN_Msk; + } + + /* Disable slave TX under run interrupt flag */ + if((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK) + { + qspi->SSCTL &= ~QSPI_SSCTL_SLVURIEN_Msk; + } + + /* Disable slave bit count error interrupt flag */ + if((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK) + { + qspi->SSCTL &= ~QSPI_SSCTL_SLVBEIEN_Msk; + } + + /* Disable slave TX underflow interrupt flag */ + if((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Disable TX threshold interrupt flag */ + if((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Disable RX threshold interrupt flag */ + if((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Disable RX overrun interrupt flag */ + if((u32Mask & QSPI_FIFO_RXOV_INT_MASK) == QSPI_FIFO_RXOV_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Disable RX time-out interrupt flag */ + if((u32Mask & QSPI_FIFO_RXTO_INT_MASK) == QSPI_FIFO_RXTO_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXTOIEN_Msk; + } +} + +/** + * @brief Get interrupt flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. It is combination of: + * - \ref QSPI_UNIT_INT_MASK + * - \ref QSPI_SSACT_INT_MASK + * - \ref QSPI_SSINACT_INT_MASK + * - \ref QSPI_SLVUR_INT_MASK + * - \ref QSPI_SLVBE_INT_MASK + * - \ref QSPI_TXUF_INT_MASK + * - \ref QSPI_FIFO_TXTH_INT_MASK + * - \ref QSPI_FIFO_RXTH_INT_MASK + * - \ref QSPI_FIFO_RXOV_INT_MASK + * - \ref QSPI_FIFO_RXTO_INT_MASK + * + * @return Interrupt flags of selected sources. + * @details Get QSPI related interrupt flags specified by u32Mask parameter. + */ +uint32_t QSPI_GetIntFlag(QSPI_T *qspi, uint32_t u32Mask) +{ + uint32_t u32IntFlag = 0U, u32TmpVal; + + u32TmpVal = qspi->STATUS & QSPI_STATUS_UNITIF_Msk; + /* Check unit transfer interrupt flag */ + if((u32Mask & QSPI_UNIT_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_UNIT_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_SSACTIF_Msk; + /* Check slave selection signal active interrupt flag */ + if((u32Mask & QSPI_SSACT_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_SSACT_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_SSINAIF_Msk; + /* Check slave selection signal inactive interrupt flag */ + if((u32Mask & QSPI_SSINACT_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_SSINACT_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_SLVURIF_Msk; + /* Check slave TX under run interrupt flag */ + if((u32Mask & QSPI_SLVUR_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_SLVUR_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_SLVBEIF_Msk; + /* Check slave bit count error interrupt flag */ + if((u32Mask & QSPI_SLVBE_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_SLVBE_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_TXUFIF_Msk; + /* Check slave TX underflow interrupt flag */ + if((u32Mask & QSPI_TXUF_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_TXUF_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_TXTHIF_Msk; + /* Check TX threshold interrupt flag */ + if((u32Mask & QSPI_FIFO_TXTH_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_FIFO_TXTH_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_RXTHIF_Msk; + /* Check RX threshold interrupt flag */ + if((u32Mask & QSPI_FIFO_RXTH_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_FIFO_RXTH_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_RXOVIF_Msk; + /* Check RX overrun interrupt flag */ + if((u32Mask & QSPI_FIFO_RXOV_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_FIFO_RXOV_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_RXTOIF_Msk; + /* Check RX time-out interrupt flag */ + if((u32Mask & QSPI_FIFO_RXTO_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_FIFO_RXTO_INT_MASK; + } + + return u32IntFlag; +} + +/** + * @brief Clear interrupt flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. It could be the combination of: + * - \ref QSPI_UNIT_INT_MASK + * - \ref QSPI_SSACT_INT_MASK + * - \ref QSPI_SSINACT_INT_MASK + * - \ref QSPI_SLVUR_INT_MASK + * - \ref QSPI_SLVBE_INT_MASK + * - \ref QSPI_TXUF_INT_MASK + * - \ref QSPI_FIFO_RXOV_INT_MASK + * - \ref QSPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Clear QSPI related interrupt flags specified by u32Mask parameter. + */ +void QSPI_ClearIntFlag(QSPI_T *qspi, uint32_t u32Mask) +{ + if(u32Mask & QSPI_UNIT_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_UNITIF_Msk; /* Clear unit transfer interrupt flag */ + } + + if(u32Mask & QSPI_SSACT_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_SSACTIF_Msk; /* Clear slave selection signal active interrupt flag */ + } + + if(u32Mask & QSPI_SSINACT_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_SSINAIF_Msk; /* Clear slave selection signal inactive interrupt flag */ + } + + if(u32Mask & QSPI_SLVUR_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_SLVURIF_Msk; /* Clear slave TX under run interrupt flag */ + } + + if(u32Mask & QSPI_SLVBE_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_SLVBEIF_Msk; /* Clear slave bit count error interrupt flag */ + } + + if(u32Mask & QSPI_TXUF_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_TXUFIF_Msk; /* Clear slave TX underflow interrupt flag */ + } + + if(u32Mask & QSPI_FIFO_RXOV_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_RXOVIF_Msk; /* Clear RX overrun interrupt flag */ + } + + if(u32Mask & QSPI_FIFO_RXTO_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_RXTOIF_Msk; /* Clear RX time-out interrupt flag */ + } +} + +/** + * @brief Get QSPI status. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related sources. + * Each bit corresponds to a source. + * This parameter decides which flags will be read. It is combination of: + * - \ref QSPI_BUSY_MASK + * - \ref QSPI_RX_EMPTY_MASK + * - \ref QSPI_RX_FULL_MASK + * - \ref QSPI_TX_EMPTY_MASK + * - \ref QSPI_TX_FULL_MASK + * - \ref QSPI_TXRX_RESET_MASK + * - \ref QSPI_QSPIEN_STS_MASK + * - \ref QSPI_SSLINE_STS_MASK + * + * @return Flags of selected sources. + * @details Get QSPI related status specified by u32Mask parameter. + */ +uint32_t QSPI_GetStatus(QSPI_T *qspi, uint32_t u32Mask) +{ + uint32_t u32Flag = 0U, u32TmpValue; + + u32TmpValue = qspi->STATUS & QSPI_STATUS_BUSY_Msk; + /* Check busy status */ + if((u32Mask & QSPI_BUSY_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_BUSY_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_RXEMPTY_Msk; + /* Check RX empty flag */ + if((u32Mask & QSPI_RX_EMPTY_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_RX_EMPTY_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_RXFULL_Msk; + /* Check RX full flag */ + if((u32Mask & QSPI_RX_FULL_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_RX_FULL_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_TXEMPTY_Msk; + /* Check TX empty flag */ + if((u32Mask & QSPI_TX_EMPTY_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_TX_EMPTY_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_TXFULL_Msk; + /* Check TX full flag */ + if((u32Mask & QSPI_TX_FULL_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_TX_FULL_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_TXRXRST_Msk; + /* Check TX/RX reset flag */ + if((u32Mask & QSPI_TXRX_RESET_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_TXRX_RESET_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_QSPIENSTS_Msk; + /* Check QSPIEN flag */ + if((u32Mask & QSPI_QSPIEN_STS_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_QSPIEN_STS_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_SSLINE_Msk; + /* Check QSPIx_SS line status */ + if((u32Mask & QSPI_SSLINE_STS_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_SSLINE_STS_MASK; + } + + return u32Flag; +} + + + +/*@}*/ /* end of group QSPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group QSPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_rtc.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_rtc.c new file mode 100644 index 0000000000000000000000000000000000000000..0df0ccb44328725cf003a8cf83612efb39f66c12 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_rtc.c @@ -0,0 +1,1095 @@ +/**************************************************************************//** + * @file rtc.c + * @version V3.00 + * @brief M480 series RTC driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @cond HIDDEN_SYMBOLS */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Macro, type and constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_GLOBALS + +/*---------------------------------------------------------------------------------------------------------*/ +/* Global file scope (static) variables */ +/*---------------------------------------------------------------------------------------------------------*/ +static volatile uint32_t g_u32hiYear, g_u32loYear, g_u32hiMonth, g_u32loMonth, g_u32hiDay, g_u32loDay; +static volatile uint32_t g_u32hiHour, g_u32loHour, g_u32hiMin, g_u32loMin, g_u32hiSec, g_u32loSec; + +/** @endcond HIDDEN_SYMBOLS */ + + + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup RTC_Driver RTC Driver + @{ +*/ + +/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions + @{ +*/ + +/** + * @brief Initialize RTC module and start counting + * + * @param[in] sPt Specify the time property and current date and time. It includes: \n + * u32Year: Year value, range between 2000 ~ 2099. \n + * u32Month: Month value, range between 1 ~ 12. \n + * u32Day: Day value, range between 1 ~ 31. \n + * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY / + * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY / + * RTC_SATURDAY] \n + * u32Hour: Hour value, range between 0 ~ 23. \n + * u32Minute: Minute value, range between 0 ~ 59. \n + * u32Second: Second value, range between 0 ~ 59. \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This function is used to: \n + * 1. Write initial key to let RTC start count. \n + * 2. Input parameter indicates start date/time. \n + * 3. User has to make sure that parameters of RTC date/time are reasonable. \n + * @note Null pointer for using default starting date/time. + */ +void RTC_Open(S_RTC_TIME_DATA_T *sPt) +{ + RTC->INIT = RTC_INIT_KEY; + + if(RTC->INIT != RTC_INIT_ACTIVE_Msk) + { + RTC->INIT = RTC_INIT_KEY; + while(RTC->INIT != RTC_INIT_ACTIVE_Msk) + { + } + } + + if(sPt == 0) + { + } + else + { + /* Set RTC date and time */ + RTC_SetDateAndTime(sPt); + } +} + +/** + * @brief Disable RTC Clock + * + * @param None + * + * @return None + * + * @details This API will disable RTC peripheral clock and stops RTC counting. + */ +void RTC_Close(void) +{ + CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk; +} + +/** + * @brief Set Frequency Compensation Data + * + * @param[in] i32FrequencyX10000 Specify the RTC clock X10000, ex: 327736512 means 32773.6512. + * + * @return None + * + */ +void RTC_32KCalibration(int32_t i32FrequencyX10000) +{ + uint64_t u64Compensate; + int32_t i32RegInt,i32RegFra ; + + if(!(SYS->CSERVER & 0x1)) + { + u64Compensate = (uint64_t)(0x2710000000000); + u64Compensate = (uint64_t)(u64Compensate / (uint64_t)i32FrequencyX10000); + + if(u64Compensate >= (uint64_t)0x400000) + { + u64Compensate = (uint64_t)0x3FFFFF; + } + + RTC_WaitAccessEnable(); + RTC->FREQADJ = (uint32_t)u64Compensate; + } + else + { + /* Compute Integer and Fraction for RTC register*/ + i32RegInt = (i32FrequencyX10000/10000) - 32752; + i32RegFra = ((((i32FrequencyX10000%10000)) * 64) + 5000) / 10000; + + if(i32RegFra >= 0x40) + { + i32RegFra = 0x0; + i32RegInt++; + } + + /* Judge Integer part is reasonable */ + if ( (i32RegInt < 0) | (i32RegInt > 31) ) + { + return; + } + + RTC_WaitAccessEnable(); + RTC->FREQADJ = (uint32_t)((i32RegInt<<8) | i32RegFra); + } + +} + +/** + * @brief Get Current RTC Date and Time + * + * @param[out] sPt The returned pointer is specified the current RTC value. It includes: \n + * u32Year: Year value \n + * u32Month: Month value \n + * u32Day: Day value \n + * u32DayOfWeek: Day of week \n + * u32Hour: Hour value \n + * u32Minute: Minute value \n + * u32Second: Second value \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This API is used to get the current RTC date and time value. + */ +void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt) +{ + uint32_t u32Tmp; + + sPt->u32TimeScale = RTC->CLKFMT & RTC_CLKFMT_24HEN_Msk; /* 12/24-hour */ + sPt->u32DayOfWeek = RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk; /* Day of the week */ + + /* Get [Date digit] data */ + g_u32hiYear = (RTC->CAL & RTC_CAL_TENYEAR_Msk) >> RTC_CAL_TENYEAR_Pos; + g_u32loYear = (RTC->CAL & RTC_CAL_YEAR_Msk) >> RTC_CAL_YEAR_Pos; + g_u32hiMonth = (RTC->CAL & RTC_CAL_TENMON_Msk) >> RTC_CAL_TENMON_Pos; + g_u32loMonth = (RTC->CAL & RTC_CAL_MON_Msk) >> RTC_CAL_MON_Pos; + g_u32hiDay = (RTC->CAL & RTC_CAL_TENDAY_Msk) >> RTC_CAL_TENDAY_Pos; + g_u32loDay = (RTC->CAL & RTC_CAL_DAY_Msk) >> RTC_CAL_DAY_Pos; + + /* Get [Time digit] data */ + g_u32hiHour = (RTC->TIME & RTC_TIME_TENHR_Msk) >> RTC_TIME_TENHR_Pos; + g_u32loHour = (RTC->TIME & RTC_TIME_HR_Msk) >> RTC_TIME_HR_Pos; + g_u32hiMin = (RTC->TIME & RTC_TIME_TENMIN_Msk) >> RTC_TIME_TENMIN_Pos; + g_u32loMin = (RTC->TIME & RTC_TIME_MIN_Msk) >> RTC_TIME_MIN_Pos; + g_u32hiSec = (RTC->TIME & RTC_TIME_TENSEC_Msk) >> RTC_TIME_TENSEC_Pos; + g_u32loSec = (RTC->TIME & RTC_TIME_SEC_Msk) >> RTC_TIME_SEC_Pos; + + /* Compute to 20XX year */ + u32Tmp = (g_u32hiYear * 10ul); + u32Tmp += g_u32loYear; + sPt->u32Year = u32Tmp + RTC_YEAR2000; + + /* Compute 0~12 month */ + u32Tmp = (g_u32hiMonth * 10ul); + sPt->u32Month = u32Tmp + g_u32loMonth; + + /* Compute 0~31 day */ + u32Tmp = (g_u32hiDay * 10ul); + sPt->u32Day = u32Tmp + g_u32loDay; + + /* Compute 12/24 hour */ + if(sPt->u32TimeScale == RTC_CLOCK_12) + { + u32Tmp = (g_u32hiHour * 10ul); + u32Tmp += g_u32loHour; + sPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */ + + if(sPt->u32Hour >= 21ul) + { + sPt->u32AmPm = RTC_PM; + sPt->u32Hour -= 20ul; + } + else + { + sPt->u32AmPm = RTC_AM; + } + + u32Tmp = (g_u32hiMin * 10ul); + u32Tmp += g_u32loMin; + sPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32hiSec * 10ul); + u32Tmp += g_u32loSec; + sPt->u32Second = u32Tmp; + } + else + { + u32Tmp = (g_u32hiHour * 10ul); + u32Tmp += g_u32loHour; + sPt->u32Hour = u32Tmp; + + u32Tmp = (g_u32hiMin * 10ul); + u32Tmp += g_u32loMin; + sPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32hiSec * 10ul); + u32Tmp += g_u32loSec; + sPt->u32Second = u32Tmp; + } +} + +/** + * @brief Get RTC Alarm Date and Time + * + * @param[out] sPt The returned pointer is specified the RTC alarm value. It includes: \n + * u32Year: Year value \n + * u32Month: Month value \n + * u32Day: Day value \n + * u32DayOfWeek: Day of week \n + * u32Hour: Hour value \n + * u32Minute: Minute value \n + * u32Second: Second value \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This API is used to get the RTC alarm date and time setting. + */ +void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt) +{ + uint32_t u32Tmp; + + sPt->u32TimeScale = RTC->CLKFMT & RTC_CLKFMT_24HEN_Msk; /* 12/24-hour */ + sPt->u32DayOfWeek = RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk; /* Day of the week */ + + /* Get alarm [Date digit] data */ + RTC_WaitAccessEnable(); + g_u32hiYear = (RTC->CALM & RTC_CALM_TENYEAR_Msk) >> RTC_CALM_TENYEAR_Pos; + g_u32loYear = (RTC->CALM & RTC_CALM_YEAR_Msk) >> RTC_CALM_YEAR_Pos; + g_u32hiMonth = (RTC->CALM & RTC_CALM_TENMON_Msk) >> RTC_CALM_TENMON_Pos; + g_u32loMonth = (RTC->CALM & RTC_CALM_MON_Msk) >> RTC_CALM_MON_Pos; + g_u32hiDay = (RTC->CALM & RTC_CALM_TENDAY_Msk) >> RTC_CALM_TENDAY_Pos; + g_u32loDay = (RTC->CALM & RTC_CALM_DAY_Msk) >> RTC_CALM_DAY_Pos; + + /* Get alarm [Time digit] data */ + RTC_WaitAccessEnable(); + g_u32hiHour = (RTC->TALM & RTC_TALM_TENHR_Msk) >> RTC_TALM_TENHR_Pos; + g_u32loHour = (RTC->TALM & RTC_TALM_HR_Msk) >> RTC_TALM_HR_Pos; + g_u32hiMin = (RTC->TALM & RTC_TALM_TENMIN_Msk) >> RTC_TALM_TENMIN_Pos; + g_u32loMin = (RTC->TALM & RTC_TALM_MIN_Msk) >> RTC_TALM_MIN_Pos; + g_u32hiSec = (RTC->TALM & RTC_TALM_TENSEC_Msk) >> RTC_TALM_TENSEC_Pos; + g_u32loSec = (RTC->TALM & RTC_TALM_SEC_Msk) >> RTC_TALM_SEC_Pos; + + /* Compute to 20XX year */ + u32Tmp = (g_u32hiYear * 10ul); + u32Tmp += g_u32loYear; + sPt->u32Year = u32Tmp + RTC_YEAR2000; + + /* Compute 0~12 month */ + u32Tmp = (g_u32hiMonth * 10ul); + sPt->u32Month = u32Tmp + g_u32loMonth; + + /* Compute 0~31 day */ + u32Tmp = (g_u32hiDay * 10ul); + sPt->u32Day = u32Tmp + g_u32loDay; + + /* Compute 12/24 hour */ + if(sPt->u32TimeScale == RTC_CLOCK_12) + { + u32Tmp = (g_u32hiHour * 10ul); + u32Tmp += g_u32loHour; + sPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */ + + if(sPt->u32Hour >= 21ul) + { + sPt->u32AmPm = RTC_PM; + sPt->u32Hour -= 20ul; + } + else + { + sPt->u32AmPm = RTC_AM; + } + + u32Tmp = (g_u32hiMin * 10ul); + u32Tmp += g_u32loMin; + sPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32hiSec * 10ul); + u32Tmp += g_u32loSec; + sPt->u32Second = u32Tmp; + + } + else + { + u32Tmp = (g_u32hiHour * 10ul); + u32Tmp += g_u32loHour; + sPt->u32Hour = u32Tmp; + + u32Tmp = (g_u32hiMin * 10ul); + u32Tmp += g_u32loMin; + sPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32hiSec * 10ul); + u32Tmp += g_u32loSec; + sPt->u32Second = u32Tmp; + } +} + +/** + * @brief Update Current RTC Date and Time + * + * @param[in] sPt Specify the time property and current date and time. It includes: \n + * u32Year: Year value, range between 2000 ~ 2099. \n + * u32Month: Month value, range between 1 ~ 12. \n + * u32Day: Day value, range between 1 ~ 31. \n + * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY / + * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY / + * RTC_SATURDAY] \n + * u32Hour: Hour value, range between 0 ~ 23. \n + * u32Minute: Minute value, range between 0 ~ 59. \n + * u32Second: Second value, range between 0 ~ 59. \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This API is used to update current date and time to RTC. + */ +void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt) +{ + uint32_t u32RegCAL, u32RegTIME; + + if(sPt == 0ul) + { + } + else + { + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC 24/12 hour setting and Day of the Week */ + /*-----------------------------------------------------------------------------------------------------*/ + RTC_WaitAccessEnable(); + if(sPt->u32TimeScale == RTC_CLOCK_12) + { + RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk; + + /*-------------------------------------------------------------------------------------------------*/ + /* Important, range of 12-hour PM mode is 21 up to 32 */ + /*-------------------------------------------------------------------------------------------------*/ + if(sPt->u32AmPm == RTC_PM) + { + sPt->u32Hour += 20ul; + } + } + else + { + RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk; + } + + /* Set Day of the Week */ + RTC_WaitAccessEnable(); + RTC->WEEKDAY = sPt->u32DayOfWeek; + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC Current Date and Time */ + /*-----------------------------------------------------------------------------------------------------*/ + u32RegCAL = ((sPt->u32Year - RTC_YEAR2000) / 10ul) << 20; + u32RegCAL |= (((sPt->u32Year - RTC_YEAR2000) % 10ul) << 16); + u32RegCAL |= ((sPt->u32Month / 10ul) << 12); + u32RegCAL |= ((sPt->u32Month % 10ul) << 8); + u32RegCAL |= ((sPt->u32Day / 10ul) << 4); + u32RegCAL |= (sPt->u32Day % 10ul); + + u32RegTIME = ((sPt->u32Hour / 10ul) << 20); + u32RegTIME |= ((sPt->u32Hour % 10ul) << 16); + u32RegTIME |= ((sPt->u32Minute / 10ul) << 12); + u32RegTIME |= ((sPt->u32Minute % 10ul) << 8); + u32RegTIME |= ((sPt->u32Second / 10ul) << 4); + u32RegTIME |= (sPt->u32Second % 10ul); + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC Calender and Time Loading */ + /*-----------------------------------------------------------------------------------------------------*/ + RTC_WaitAccessEnable(); + RTC->CAL = (uint32_t)u32RegCAL; + RTC_WaitAccessEnable(); + RTC->TIME = (uint32_t)u32RegTIME; + } +} + +/** + * @brief Update RTC Alarm Date and Time + * + * @param[in] sPt Specify the time property and alarm date and time. It includes: \n + * u32Year: Year value, range between 2000 ~ 2099. \n + * u32Month: Month value, range between 1 ~ 12. \n + * u32Day: Day value, range between 1 ~ 31. \n + * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY / + * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY / + * RTC_SATURDAY] \n + * u32Hour: Hour value, range between 0 ~ 23. \n + * u32Minute: Minute value, range between 0 ~ 59. \n + * u32Second: Second value, range between 0 ~ 59. \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This API is used to update alarm date and time setting to RTC. + */ +void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt) +{ + uint32_t u32RegCALM, u32RegTALM; + + if(sPt == 0) + { + } + else + { + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC 24/12 hour setting and Day of the Week */ + /*-----------------------------------------------------------------------------------------------------*/ + RTC_WaitAccessEnable(); + if(sPt->u32TimeScale == RTC_CLOCK_12) + { + RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk; + + /*-------------------------------------------------------------------------------------------------*/ + /* Important, range of 12-hour PM mode is 21 up to 32 */ + /*-------------------------------------------------------------------------------------------------*/ + if(sPt->u32AmPm == RTC_PM) + { + sPt->u32Hour += 20ul; + } + } + else + { + RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk; + } + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC Alarm Date and Time */ + /*-----------------------------------------------------------------------------------------------------*/ + u32RegCALM = ((sPt->u32Year - RTC_YEAR2000) / 10ul) << 20; + u32RegCALM |= (((sPt->u32Year - RTC_YEAR2000) % 10ul) << 16); + u32RegCALM |= ((sPt->u32Month / 10ul) << 12); + u32RegCALM |= ((sPt->u32Month % 10ul) << 8); + u32RegCALM |= ((sPt->u32Day / 10ul) << 4); + u32RegCALM |= (sPt->u32Day % 10ul); + + u32RegTALM = ((sPt->u32Hour / 10ul) << 20); + u32RegTALM |= ((sPt->u32Hour % 10ul) << 16); + u32RegTALM |= ((sPt->u32Minute / 10ul) << 12); + u32RegTALM |= ((sPt->u32Minute % 10ul) << 8); + u32RegTALM |= ((sPt->u32Second / 10ul) << 4); + u32RegTALM |= (sPt->u32Second % 10ul); + + RTC_WaitAccessEnable(); + RTC->CALM = (uint32_t)u32RegCALM; + RTC_WaitAccessEnable(); + RTC->TALM = (uint32_t)u32RegTALM; + } +} + +/** + * @brief Update RTC Current Date + * + * @param[in] u32Year The year calendar digit of current RTC setting. + * @param[in] u32Month The month calendar digit of current RTC setting. + * @param[in] u32Day The day calendar digit of current RTC setting. + * @param[in] u32DayOfWeek The Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY / + * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY / + * RTC_SATURDAY] + * + * @return None + * + * @details This API is used to update current date to RTC. + */ +void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek) +{ + uint32_t u32RegCAL; + + u32RegCAL = ((u32Year - RTC_YEAR2000) / 10ul) << 20; + u32RegCAL |= (((u32Year - RTC_YEAR2000) % 10ul) << 16); + u32RegCAL |= ((u32Month / 10ul) << 12); + u32RegCAL |= ((u32Month % 10ul) << 8); + u32RegCAL |= ((u32Day / 10ul) << 4); + u32RegCAL |= (u32Day % 10ul); + + /* Set Day of the Week */ + RTC_WaitAccessEnable(); + RTC->WEEKDAY = u32DayOfWeek & RTC_WEEKDAY_WEEKDAY_Msk; + + /* Set RTC Calender Loading */ + RTC_WaitAccessEnable(); + RTC->CAL = (uint32_t)u32RegCAL; +} + +/** + * @brief Update RTC Current Time + * + * @param[in] u32Hour The hour time digit of current RTC setting. + * @param[in] u32Minute The minute time digit of current RTC setting. + * @param[in] u32Second The second time digit of current RTC setting. + * @param[in] u32TimeMode The 24-Hour / 12-Hour Time Scale Selection. [RTC_CLOCK_12 / RTC_CLOCK_24] + * @param[in] u32AmPm 12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [RTC_AM / RTC_PM] + * + * @return None + * + * @details This API is used to update current time to RTC. + */ +void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm) +{ + uint32_t u32RegTIME; + + /* Important, range of 12-hour PM mode is 21 up to 32 */ + if((u32TimeMode == RTC_CLOCK_12) && (u32AmPm == RTC_PM)) + { + u32Hour += 20ul; + } + + u32RegTIME = ((u32Hour / 10ul) << 20); + u32RegTIME |= ((u32Hour % 10ul) << 16); + u32RegTIME |= ((u32Minute / 10ul) << 12); + u32RegTIME |= ((u32Minute % 10ul) << 8); + u32RegTIME |= ((u32Second / 10ul) << 4); + u32RegTIME |= (u32Second % 10ul); + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC 24/12 hour setting and Day of the Week */ + /*-----------------------------------------------------------------------------------------------------*/ + RTC_WaitAccessEnable(); + if(u32TimeMode == RTC_CLOCK_12) + { + RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk; + } + else + { + RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk; + } + + RTC_WaitAccessEnable(); + RTC->TIME = (uint32_t)u32RegTIME; +} + +/** + * @brief Update RTC Alarm Date + * + * @param[in] u32Year The year calendar digit of RTC alarm setting. + * @param[in] u32Month The month calendar digit of RTC alarm setting. + * @param[in] u32Day The day calendar digit of RTC alarm setting. + * + * @return None + * + * @details This API is used to update alarm date setting to RTC. + */ +void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day) +{ + uint32_t u32RegCALM; + + u32RegCALM = ((u32Year - RTC_YEAR2000) / 10ul) << 20; + u32RegCALM |= (((u32Year - RTC_YEAR2000) % 10ul) << 16); + u32RegCALM |= ((u32Month / 10ul) << 12); + u32RegCALM |= ((u32Month % 10ul) << 8); + u32RegCALM |= ((u32Day / 10ul) << 4); + u32RegCALM |= (u32Day % 10ul); + + RTC_WaitAccessEnable(); + + /* Set RTC Alarm Date */ + RTC->CALM = (uint32_t)u32RegCALM; +} + +/** + * @brief Update RTC Alarm Time + * + * @param[in] u32Hour The hour time digit of RTC alarm setting. + * @param[in] u32Minute The minute time digit of RTC alarm setting. + * @param[in] u32Second The second time digit of RTC alarm setting. + * @param[in] u32TimeMode The 24-Hour / 12-Hour Time Scale Selection. [RTC_CLOCK_12 / RTC_CLOCK_24] + * @param[in] u32AmPm 12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [RTC_AM / RTC_PM] + * + * @return None + * + * @details This API is used to update alarm time setting to RTC. + */ +void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm) +{ + uint32_t u32RegTALM; + + /* Important, range of 12-hour PM mode is 21 up to 32 */ + if((u32TimeMode == RTC_CLOCK_12) && (u32AmPm == RTC_PM)) + { + u32Hour += 20ul; + } + + u32RegTALM = ((u32Hour / 10ul) << 20); + u32RegTALM |= ((u32Hour % 10ul) << 16); + u32RegTALM |= ((u32Minute / 10ul) << 12); + u32RegTALM |= ((u32Minute % 10ul) << 8); + u32RegTALM |= ((u32Second / 10ul) << 4); + u32RegTALM |= (u32Second % 10ul); + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC 24/12 hour setting and Day of the Week */ + /*-----------------------------------------------------------------------------------------------------*/ + RTC_WaitAccessEnable(); + if(u32TimeMode == RTC_CLOCK_12) + { + RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk; + } + else + { + RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk; + } + + /* Set RTC Alarm Time */ + RTC_WaitAccessEnable(); + RTC->TALM = (uint32_t)u32RegTALM; +} + +/** + * @brief Set RTC Alarm Date Mask Function + * + * @param[in] u8IsTenYMsk 1: enable 10-Year digit alarm mask; 0: disabled. + * @param[in] u8IsYMsk 1: enable 1-Year digit alarm mask; 0: disabled. + * @param[in] u8IsTenMMsk 1: enable 10-Mon digit alarm mask; 0: disabled. + * @param[in] u8IsMMsk 1: enable 1-Mon digit alarm mask; 0: disabled. + * @param[in] u8IsTenDMsk 1: enable 10-Day digit alarm mask; 0: disabled. + * @param[in] u8IsDMsk 1: enable 1-Day digit alarm mask; 0: disabled. + * + * @return None + * + * @details This API is used to enable or disable RTC alarm date mask function. + */ +void RTC_SetAlarmDateMask(uint8_t u8IsTenYMsk, uint8_t u8IsYMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenDMsk, uint8_t u8IsDMsk) +{ + RTC_WaitAccessEnable(); + RTC->CAMSK = ((uint32_t)u8IsTenYMsk << RTC_CAMSK_MTENYEAR_Pos) | + ((uint32_t)u8IsYMsk << RTC_CAMSK_MYEAR_Pos) | + ((uint32_t)u8IsTenMMsk << RTC_CAMSK_MTENMON_Pos) | + ((uint32_t)u8IsMMsk << RTC_CAMSK_MMON_Pos) | + ((uint32_t)u8IsTenDMsk << RTC_CAMSK_MTENDAY_Pos) | + ((uint32_t)u8IsDMsk << RTC_CAMSK_MDAY_Pos); +} + +/** + * @brief Set RTC Alarm Time Mask Function + * + * @param[in] u8IsTenHMsk 1: enable 10-Hour digit alarm mask; 0: disabled. + * @param[in] u8IsHMsk 1: enable 1-Hour digit alarm mask; 0: disabled. + * @param[in] u8IsTenMMsk 1: enable 10-Min digit alarm mask; 0: disabled. + * @param[in] u8IsMMsk 1: enable 1-Min digit alarm mask; 0: disabled. + * @param[in] u8IsTenSMsk 1: enable 10-Sec digit alarm mask; 0: disabled. + * @param[in] u8IsSMsk 1: enable 1-Sec digit alarm mask; 0: disabled. + * + * @return None + * + * @details This API is used to enable or disable RTC alarm time mask function. + */ +void RTC_SetAlarmTimeMask(uint8_t u8IsTenHMsk, uint8_t u8IsHMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenSMsk, uint8_t u8IsSMsk) +{ + RTC_WaitAccessEnable(); + RTC->TAMSK = ((uint32_t)u8IsTenHMsk << RTC_TAMSK_MTENHR_Pos) | + ((uint32_t)u8IsHMsk << RTC_TAMSK_MHR_Pos) | + ((uint32_t)u8IsTenMMsk << RTC_TAMSK_MTENMIN_Pos) | + ((uint32_t)u8IsMMsk << RTC_TAMSK_MMIN_Pos) | + ((uint32_t)u8IsTenSMsk << RTC_TAMSK_MTENSEC_Pos) | + ((uint32_t)u8IsSMsk << RTC_TAMSK_MSEC_Pos); +} + +/** + * @brief Get Day of the Week + * + * @param None + * + * @retval 0 Sunday + * @retval 1 Monday + * @retval 2 Tuesday + * @retval 3 Wednesday + * @retval 4 Thursday + * @retval 5 Friday + * @retval 6 Saturday + * + * @details This API is used to get day of the week of current RTC date. + */ +uint32_t RTC_GetDayOfWeek(void) +{ + return (RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk); +} + +/** + * @brief Set RTC Tick Period Time + * + * @param[in] u32TickSelection It is used to set the RTC tick period time for Periodic Time Tick request. \n + * It consists of: + * - \ref RTC_TICK_1_SEC : Time tick is 1 second + * - \ref RTC_TICK_1_2_SEC : Time tick is 1/2 second + * - \ref RTC_TICK_1_4_SEC : Time tick is 1/4 second + * - \ref RTC_TICK_1_8_SEC : Time tick is 1/8 second + * - \ref RTC_TICK_1_16_SEC : Time tick is 1/16 second + * - \ref RTC_TICK_1_32_SEC : Time tick is 1/32 second + * - \ref RTC_TICK_1_64_SEC : Time tick is 1/64 second + * - \ref RTC_TICK_1_128_SEC : Time tick is 1/128 second + * + * @return None + * + * @details This API is used to set RTC tick period time for each tick interrupt. + */ +void RTC_SetTickPeriod(uint32_t u32TickSelection) +{ + RTC_WaitAccessEnable(); + + RTC->TICK = (RTC->TICK & ~RTC_TICK_TICK_Msk) | u32TickSelection; +} + +/** + * @brief Enable RTC Interrupt + * + * @param[in] u32IntFlagMask Specify the interrupt source. It consists of: + * - \ref RTC_INTEN_ALMIEN_Msk : Alarm interrupt + * - \ref RTC_INTEN_TICKIEN_Msk : Tick interrupt + * - \ref RTC_INTEN_TAMP0IEN_Msk : Tamper 0 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP1IEN_Msk : Tamper 1 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP2IEN_Msk : Tamper 2 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP3IEN_Msk : Tamper 3 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP4IEN_Msk : Tamper 4 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP5IEN_Msk : Tamper 5 Pin Event Detection interrupt + * + * @return None + * + * @details This API is used to enable the specify RTC interrupt function. + */ +void RTC_EnableInt(uint32_t u32IntFlagMask) +{ + RTC_WaitAccessEnable(); + RTC->INTEN |= u32IntFlagMask; +} + +/** + * @brief Disable RTC Interrupt + * + * @param[in] u32IntFlagMask Specify the interrupt source. It consists of: + * - \ref RTC_INTEN_ALMIEN_Msk : Alarm interrupt + * - \ref RTC_INTEN_TICKIEN_Msk : Tick interrupt + * - \ref RTC_INTEN_TAMP0IEN_Msk : Tamper 0 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP1IEN_Msk : Tamper 1 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP2IEN_Msk : Tamper 2 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP3IEN_Msk : Tamper 3 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP4IEN_Msk : Tamper 4 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP5IEN_Msk : Tamper 5 Pin Event Detection interrupt + * + * @return None + * + * @details This API is used to disable the specify RTC interrupt function. + */ +void RTC_DisableInt(uint32_t u32IntFlagMask) +{ + RTC_WaitAccessEnable(); + RTC->INTEN &= ~u32IntFlagMask; + RTC_WaitAccessEnable(); + RTC->INTSTS = u32IntFlagMask; +} + +/** + * @brief Enable Spare Registers Access + * + * @param None + * + * @return None + * + * @details This API is used to enable the spare registers 0~19 can be accessed. + */ +void RTC_EnableSpareAccess(void) +{ + RTC_WaitAccessEnable(); + + RTC->SPRCTL |= RTC_SPRCTL_SPRRWEN_Msk; +} + +/** + * @brief Disable Spare Register + * + * @param None + * + * @return None + * + * @details This API is used to disable the spare register 0~19 cannot be accessed. + */ +void RTC_DisableSpareRegister(void) +{ + RTC_WaitAccessEnable(); + + RTC->SPRCTL &= ~RTC_SPRCTL_SPRRWEN_Msk; +} + +/** + * @brief Static Tamper Detect + * + * @param[in] u32TamperSelect Tamper pin select. Possible options are + * - \ref RTC_TAMPER5_SELECT + * - \ref RTC_TAMPER4_SELECT + * - \ref RTC_TAMPER3_SELECT + * - \ref RTC_TAMPER2_SELECT + * - \ref RTC_TAMPER1_SELECT + * - \ref RTC_TAMPER0_SELECT + * + * @param[in] u32DetecLevel Tamper pin detection level select. Possible options are + * - \ref RTC_TAMPER_HIGH_LEVEL_DETECT + * - \ref RTC_TAMPER_LOW_LEVEL_DETECT + * + * @param[in] u32DebounceEn Tamper pin de-bounce enable + * - \ref RTC_TAMPER_DEBOUNCE_ENABLE + * - \ref RTC_TAMPER_DEBOUNCE_DISABLE + * + * @return None + * + * @details This API is used to enable the tamper pin detect function with specify trigger condition. + */ +void RTC_StaticTamperEnable(uint32_t u32TamperSelect, uint32_t u32DetecLevel, uint32_t u32DebounceEn) +{ + uint32_t i; + uint32_t u32Reg; + uint32_t u32TmpReg; + + RTC_WaitAccessEnable(); + u32Reg = RTC->TAMPCTL; + + u32TmpReg = ( RTC_TAMPCTL_TAMP0EN_Msk | (u32DetecLevel << RTC_TAMPCTL_TAMP0LV_Pos) | + (u32DebounceEn << RTC_TAMPCTL_TAMP0DBEN_Pos) ); + + for(i = 0ul; i < MAX_TAMPER_PIN_NUM; i++) + { + if(u32TamperSelect & (0x1ul << i)) + { + u32Reg &= ~((RTC_TAMPCTL_TAMP0EN_Msk|RTC_TAMPCTL_TAMP0LV_Msk|RTC_TAMPCTL_TAMP0DBEN_Msk) << (i*4ul)); + u32Reg |= (u32TmpReg << (i*4ul)); + } + } + + RTC_WaitAccessEnable(); + RTC->TAMPCTL = u32Reg; + +} + +/** + * @brief Static Tamper Disable + * + * @param[in] u32TamperSelect Tamper pin select. Possible options are + * - \ref RTC_TAMPER5_SELECT + * - \ref RTC_TAMPER4_SELECT + * - \ref RTC_TAMPER3_SELECT + * - \ref RTC_TAMPER2_SELECT + * - \ref RTC_TAMPER1_SELECT + * - \ref RTC_TAMPER0_SELECT + * + * @return None + * + * @details This API is used to disable the static tamper pin detect. + */ +void RTC_StaticTamperDisable(uint32_t u32TamperSelect) +{ + uint32_t i; + uint32_t u32Reg; + uint32_t u32TmpReg; + + RTC_WaitAccessEnable(); + u32Reg = RTC->TAMPCTL; + + u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk); + + for(i = 0ul; i < MAX_TAMPER_PIN_NUM; i++) + { + if(u32TamperSelect & (0x1ul << i)) + { + u32Reg &= ~(u32TmpReg << (i*4ul)); + } + } + + RTC_WaitAccessEnable(); + RTC->TAMPCTL = u32Reg; +} + +/** + * @brief Dynamic Tamper Detect + * + * @param[in] u32PairSel Tamper pin detection enable. Possible options are + * - \ref RTC_PAIR0_SELECT + * - \ref RTC_PAIR1_SELECT + * - \ref RTC_PAIR2_SELECT + * + * @param[in] u32DebounceEn Tamper pin de-bounce enable + * - \ref RTC_TAMPER_DEBOUNCE_ENABLE + * - \ref RTC_TAMPER_DEBOUNCE_DISABLE + * + * @param[in] u32Pair1Source Dynamic Pair 1 Input Source Select + * 0: Pair 1 source select tamper 2 + * 1: Pair 1 source select tamper 0 + * + * @param[in] u32Pair2Source Dynamic Pair 2 Input Source Select + * 0: Pair 2 source select tamper 4 + * 1: Pair 2 source select tamper 0 + * + * @return None + * + * @details This API is used to enable the dynamic tamper. + */ +void RTC_DynamicTamperEnable(uint32_t u32PairSel, uint32_t u32DebounceEn, uint32_t u32Pair1Source, uint32_t u32Pair2Source) +{ + uint32_t i; + uint32_t u32Reg; + uint32_t u32TmpReg; + uint32_t u32Tamper2Debounce, u32Tamper4Debounce; + + RTC_WaitAccessEnable(); + u32Reg = RTC->TAMPCTL; + + u32Tamper2Debounce = u32Reg & RTC_TAMPCTL_TAMP2DBEN_Msk; + u32Tamper4Debounce = u32Reg & RTC_TAMPCTL_TAMP4DBEN_Msk; + + u32Reg &= ~(RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_TAMP2EN_Msk | + RTC_TAMPCTL_TAMP3EN_Msk | RTC_TAMPCTL_TAMP4EN_Msk | RTC_TAMPCTL_TAMP5EN_Msk); + u32Reg &= ~(RTC_TAMPCTL_DYN1ISS_Msk | RTC_TAMPCTL_DYN2ISS_Msk); + u32Reg |= ((u32Pair1Source & 0x1ul) << RTC_TAMPCTL_DYN1ISS_Pos) | ((u32Pair2Source & 0x1ul) << RTC_TAMPCTL_DYN2ISS_Pos); + + if(u32DebounceEn) + { + u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | + RTC_TAMPCTL_TAMP0DBEN_Msk | RTC_TAMPCTL_TAMP1DBEN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk); + } + else + { + u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk); + } + + for(i = 0ul; i < MAX_PAIR_NUM; i++) + { + if(u32PairSel & (0x1ul << i)) + { + u32Reg &= ~((RTC_TAMPCTL_TAMP0DBEN_Msk | RTC_TAMPCTL_TAMP1DBEN_Msk) << (i*8ul)); + u32Reg |= (u32TmpReg << (i*8ul)); + } + } + + if((u32Pair1Source) && (u32PairSel & RTC_PAIR1_SELECT)) + { + u32Reg &= ~RTC_TAMPCTL_TAMP2EN_Msk; + u32Reg |= u32Tamper2Debounce; + } + + if((u32Pair2Source) && (u32PairSel & RTC_PAIR2_SELECT)) + { + u32Reg &= ~RTC_TAMPCTL_TAMP4EN_Msk; + u32Reg |= u32Tamper4Debounce; + } + + RTC_WaitAccessEnable(); + RTC->TAMPCTL = u32Reg; +} + +/** + * @brief Dynamic Tamper Disable + * + * @param[in] u32PairSel Tamper pin detection enable. Possible options are + * - \ref RTC_PAIR0_SELECT + * - \ref RTC_PAIR1_SELECT + * - \ref RTC_PAIR2_SELECT + * + * @return None + * + * @details This API is used to disable the dynamic tamper. + */ +void RTC_DynamicTamperDisable(uint32_t u32PairSel) +{ + uint32_t i; + uint32_t u32Reg; + uint32_t u32TmpReg; + uint32_t u32Tamper2En = 0ul, u32Tamper4En = 0ul; + + RTC_WaitAccessEnable(); + u32Reg = RTC->TAMPCTL; + + if((u32Reg & RTC_TAMPCTL_DYN1ISS_Msk) && (u32PairSel & RTC_PAIR1_SELECT)) + { + u32Tamper2En = u32Reg & RTC_TAMPCTL_TAMP2EN_Msk; + } + + if((u32Reg & RTC_TAMPCTL_DYN2ISS_Msk) && (u32PairSel & RTC_PAIR2_SELECT)) + { + u32Tamper4En = u32Reg & RTC_TAMPCTL_TAMP4EN_Msk; + } + + u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk); + + for(i = 0ul; i < MAX_PAIR_NUM; i++) + { + if(u32PairSel & (0x1ul << i)) + { + u32Reg &= ~(u32TmpReg << ((i*8ul))); + } + } + + u32Reg |= (u32Tamper2En | u32Tamper4En); + + RTC_WaitAccessEnable(); + RTC->TAMPCTL = u32Reg; +} + +/** + * @brief Config dynamic tamper + * + * @param[in] u32ChangeRate The dynamic tamper output change rate + * - \ref RTC_2POW10_CLK + * - \ref RTC_2POW11_CLK + * - \ref RTC_2POW12_CLK + * - \ref RTC_2POW13_CLK + * - \ref RTC_2POW14_CLK + * - \ref RTC_2POW15_CLK + * - \ref RTC_2POW16_CLK + * - \ref RTC_2POW17_CLK + * + * @param[in] u32SeedReload Reload new seed or not + * 0: not reload new seed + * 1: reload new seed + * + * @param[in] u32RefPattern Reference pattern + * - \ref REF_RANDOM_PATTERN + * - \ref REF_PREVIOUS_PATTERN + * - \ref REF_SEED + * + * @param[in] u32Seed Seed Value (0x0 ~ 0xFFFFFFFF) + * + * @return None + * + * @details This API is used to config dynamic tamper setting. + */ +void RTC_DynamicTamperConfig(uint32_t u32ChangeRate, uint32_t u32SeedReload, uint32_t u32RefPattern, uint32_t u32Seed) +{ + uint32_t u32Reg; + RTC_WaitAccessEnable(); + u32Reg = RTC->TAMPCTL; + + u32Reg &= ~(RTC_TAMPCTL_DYNSRC_Msk | RTC_TAMPCTL_SEEDRLD_Msk | RTC_TAMPCTL_DYNRATE_Msk); + + u32Reg |= (u32ChangeRate) | ((u32SeedReload & 0x1ul) << RTC_TAMPCTL_SEEDRLD_Pos) | + ((u32RefPattern & 0x3ul) << RTC_TAMPCTL_DYNSRC_Pos); + + RTC_WaitAccessEnable(); + RTC->TAMPSEED = u32Seed; /* need set seed value before re-load seed */ + RTC_WaitAccessEnable(); + RTC->TAMPCTL = u32Reg; +} + +/*@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group RTC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_sc.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_sc.c new file mode 100644 index 0000000000000000000000000000000000000000..785b86cd4b28edfdfccd921434037196f5e4f685 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_sc.c @@ -0,0 +1,400 @@ +/**************************************************************************//** + * @file sc.c + * @version V3.00 + * @brief M480 Smartcard(SC) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NuMicro.h" + +/* Below are variables used locally by SC driver and does not want to parse by doxygen unless HIDDEN_SYMBOLS is defined */ +/** @cond HIDDEN_SYMBOLS */ +static uint32_t u32CardStateIgnore[SC_INTERFACE_NUM] = {0UL, 0UL, 0UL}; + +/** @endcond HIDDEN_SYMBOLS */ + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SC_Driver SC Driver + @{ +*/ + +/** @addtogroup SC_EXPORTED_FUNCTIONS SC Exported Functions + @{ +*/ + +/** + * @brief This function indicates specified smartcard slot status + * @param[in] sc Base address of smartcard module + * @return Card insert status + * @retval TRUE Card insert + * @retval FALSE Card remove + */ +uint32_t SC_IsCardInserted(SC_T *sc) +{ + uint32_t ret; + /* put conditions into two variable to remove IAR compilation warning */ + uint32_t cond1 = ((sc->STATUS & SC_STATUS_CDPINSTS_Msk) >> SC_STATUS_CDPINSTS_Pos); + uint32_t cond2 = ((sc->CTL & SC_CTL_CDLV_Msk) >> SC_CTL_CDLV_Pos); + + if((sc == SC0) && (u32CardStateIgnore[0] == 1UL)) + { + ret = (uint32_t)TRUE; + } + else if((sc == SC1) && (u32CardStateIgnore[1] == 1UL)) + { + ret = (uint32_t)TRUE; + } + else if((sc == SC2) && (u32CardStateIgnore[2] == 1UL)) + { + ret = (uint32_t)TRUE; + } + else if(cond1 != cond2) + { + ret = (uint32_t)FALSE; + } + else + { + ret = (uint32_t)TRUE; + } + return ret; +} + +/** + * @brief This function reset both transmit and receive FIFO of specified smartcard module + * @param[in] sc Base address of smartcard module + * @return None + */ +void SC_ClearFIFO(SC_T *sc) +{ + while(sc->ALTCTL & SC_ALTCTL_SYNC_Msk) + { + ; + } + sc->ALTCTL |= (SC_ALTCTL_TXRST_Msk | SC_ALTCTL_RXRST_Msk); +} + +/** + * @brief This function disable specified smartcard module + * @param[in] sc Base address of smartcard module + * @return None + */ +void SC_Close(SC_T *sc) +{ + sc->INTEN = 0UL; + while(sc->PINCTL & SC_PINCTL_SYNC_Msk) + { + ; + } + sc->PINCTL = 0UL; + sc->ALTCTL = 0UL; + while(sc->CTL & SC_CTL_SYNC_Msk) + { + ; + } + sc->CTL = 0UL; +} + +/** + * @brief This function initialized smartcard module + * @param[in] sc Base address of smartcard module + * @param[in] u32CardDet Card detect polarity, select the CD pin state which indicates card absent. Could be + * -\ref SC_PIN_STATE_HIGH + * -\ref SC_PIN_STATE_LOW + * -\ref SC_PIN_STATE_IGNORE, no card detect pin, always assumes card present + * @param[in] u32PWR Power on polarity, select the PWR pin state which could set smartcard VCC to high level. Could be + * -\ref SC_PIN_STATE_HIGH + * -\ref SC_PIN_STATE_LOW + * @return None + */ +void SC_Open(SC_T *sc, uint32_t u32CardDet, uint32_t u32PWR) +{ + uint32_t u32Reg = 0UL, u32Intf; + + if(sc == SC0) + { + u32Intf = 0UL; + } + else if(sc == SC1) + { + u32Intf = 1UL; + } + else + { + u32Intf = 2UL; + } + + if(u32CardDet != SC_PIN_STATE_IGNORE) + { + u32Reg = u32CardDet ? 0UL: SC_CTL_CDLV_Msk; + u32CardStateIgnore[u32Intf] = 0UL; + } + else + { + u32CardStateIgnore[u32Intf] = 1UL; + } + sc->PINCTL = u32PWR ? 0UL : SC_PINCTL_PWRINV_Msk; + while(sc->CTL & SC_CTL_SYNC_Msk) + { + ; + } + sc->CTL = SC_CTL_SCEN_Msk | SC_CTL_TMRSEL_Msk | u32Reg; +} + +/** + * @brief This function reset specified smartcard module to its default state for activate smartcard + * @param[in] sc Base address of smartcard module + * @return None + */ +void SC_ResetReader(SC_T *sc) +{ + uint32_t u32Intf; + + if(sc == SC0) + { + u32Intf = 0UL; + } + else if(sc == SC1) + { + u32Intf = 1UL; + } + else + { + u32Intf = 2UL; + } + + /* Reset FIFO, enable auto de-activation while card removal */ + sc->ALTCTL |= (SC_ALTCTL_TXRST_Msk | SC_ALTCTL_RXRST_Msk | SC_ALTCTL_ADACEN_Msk); + /* Set Rx trigger level to 1 character, longest card detect debounce period, disable error retry (EMV ATR does not use error retry) */ + while(sc->CTL & SC_CTL_SYNC_Msk) + { + ; + } + sc->CTL &= ~(SC_CTL_RXTRGLV_Msk | + SC_CTL_CDDBSEL_Msk | + SC_CTL_TXRTY_Msk | + SC_CTL_TXRTYEN_Msk | + SC_CTL_RXRTY_Msk | + SC_CTL_RXRTYEN_Msk); + while(sc->CTL & SC_CTL_SYNC_Msk) + { + ; + } + /* Enable auto convention, and all three smartcard internal timers */ + sc->CTL |= SC_CTL_AUTOCEN_Msk | SC_CTL_TMRSEL_Msk; + /* Disable Rx timeout */ + sc->RXTOUT = 0UL; + /* 372 clocks per ETU by default */ + sc->ETUCTL= 371UL; + + + /* Enable necessary interrupt for smartcard operation */ + if(u32CardStateIgnore[u32Intf]) /* Do not enable card detect interrupt if card present state ignore */ + { + sc->INTEN = (SC_INTEN_RDAIEN_Msk | + SC_INTEN_TERRIEN_Msk | + SC_INTEN_TMR0IEN_Msk | + SC_INTEN_TMR1IEN_Msk | + SC_INTEN_TMR2IEN_Msk | + SC_INTEN_BGTIEN_Msk | + SC_INTEN_ACERRIEN_Msk); + } + else + { + sc->INTEN = (SC_INTEN_RDAIEN_Msk | + SC_INTEN_TERRIEN_Msk | + SC_INTEN_TMR0IEN_Msk | + SC_INTEN_TMR1IEN_Msk | + SC_INTEN_TMR2IEN_Msk | + SC_INTEN_BGTIEN_Msk | + SC_INTEN_CDIEN_Msk | + SC_INTEN_ACERRIEN_Msk); + } + return; +} + +/** + * @brief This function block guard time (BGT) of specified smartcard module + * @param[in] sc Base address of smartcard module + * @param[in] u32BGT Block guard time using ETU as unit, valid range are between 1 ~ 32 + * @return None + */ +void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT) +{ + sc->CTL = (sc->CTL & ~SC_CTL_BGT_Msk) | ((u32BGT - 1UL) << SC_CTL_BGT_Pos); +} + +/** + * @brief This function character guard time (CGT) of specified smartcard module + * @param[in] sc Base address of smartcard module + * @param[in] u32CGT Character guard time using ETU as unit, valid range are between 11 ~ 267 + * @return None + */ +void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT) +{ + u32CGT -= sc->CTL & SC_CTL_NSB_Msk ? 11UL: 12UL; + sc->EGT = u32CGT; +} + +/** + * @brief This function stop all smartcard timer of specified smartcard module + * @param[in] sc Base address of smartcard module + * @return None + * @note This function stop the timers within smartcard module, \b not timer module + */ +void SC_StopAllTimer(SC_T *sc) +{ + while(sc->ALTCTL & SC_ALTCTL_SYNC_Msk) + { + ; + } + sc->ALTCTL &= ~(SC_ALTCTL_CNTEN0_Msk | SC_ALTCTL_CNTEN1_Msk | SC_ALTCTL_CNTEN2_Msk); +} + +/** + * @brief This function configure and start a smartcard timer of specified smartcard module + * @param[in] sc Base address of smartcard module + * @param[in] u32TimerNum Timer to start. Valid values are 0, 1, 2. + * @param[in] u32Mode Timer operating mode, valid values are: + * - \ref SC_TMR_MODE_0 + * - \ref SC_TMR_MODE_1 + * - \ref SC_TMR_MODE_2 + * - \ref SC_TMR_MODE_3 + * - \ref SC_TMR_MODE_4 + * - \ref SC_TMR_MODE_5 + * - \ref SC_TMR_MODE_6 + * - \ref SC_TMR_MODE_7 + * - \ref SC_TMR_MODE_8 + * - \ref SC_TMR_MODE_F + * @param[in] u32ETUCount Timer timeout duration, ETU based. For timer 0, valid range are between 1~0x1000000ETUs. + * For timer 1 and timer 2, valid range are between 1 ~ 0x100 ETUs + * @return None + * @note This function start the timer within smartcard module, \b not timer module + * @note Depend on the timer operating mode, timer may not start counting immediately + */ +void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount) +{ + uint32_t reg = u32Mode | (SC_TMRCTL0_CNT_Msk & (u32ETUCount - 1UL)); + while(sc->ALTCTL & SC_ALTCTL_SYNC_Msk) + { + ; + } + if(u32TimerNum == 0UL) + { + while(sc->TMRCTL0 & SC_TMRCTL0_SYNC_Msk) + { + ; + } + sc->TMRCTL0 = reg; + sc->ALTCTL |= SC_ALTCTL_CNTEN0_Msk; + } + else if(u32TimerNum == 1UL) + { + while(sc->TMRCTL1 & SC_TMRCTL1_SYNC_Msk) + { + ; + } + sc->TMRCTL1 = reg; + sc->ALTCTL |= SC_ALTCTL_CNTEN1_Msk; + } + else /* timer 2 */ + { + while(sc->TMRCTL2 & SC_TMRCTL2_SYNC_Msk) + { + ; + } + sc->TMRCTL2 = reg; + sc->ALTCTL |= SC_ALTCTL_CNTEN2_Msk; + } +} + +/** + * @brief This function stop a smartcard timer of specified smartcard module + * @param[in] sc Base address of smartcard module + * @param[in] u32TimerNum Timer to stop. Valid values are 0, 1, 2. + * @return None + * @note This function stop the timer within smartcard module, \b not timer module + */ +void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum) +{ + while(sc->ALTCTL & SC_ALTCTL_SYNC_Msk) + { + ; + } + if(u32TimerNum == 0UL) + { + sc->ALTCTL &= ~SC_ALTCTL_CNTEN0_Msk; + } + else if(u32TimerNum == 1UL) + { + sc->ALTCTL &= ~SC_ALTCTL_CNTEN1_Msk; + } + else /* timer 2 */ + { + sc->ALTCTL &= ~SC_ALTCTL_CNTEN2_Msk; + } +} + +/** + * @brief This function gets smartcard clock frequency. + * @param[in] sc Base address of smartcard module + * @return Smartcard frequency in kHz + */ +uint32_t SC_GetInterfaceClock(SC_T *sc) +{ + uint32_t u32ClkSrc, u32Num, u32Clk; + + if(sc == SC0) + { + u32Num = 0UL; + } + else if(sc == SC1) + { + u32Num = 1UL; + } + else + { + u32Num = 2UL; + } + + u32ClkSrc = (CLK->CLKSEL3 >> (2UL * u32Num)) & CLK_CLKSEL3_SC0SEL_Msk; + + /* Get smartcard module clock */ + if(u32ClkSrc == 0UL) + { + u32Clk = __HXT; + } + else if(u32ClkSrc == 1UL) + { + u32Clk = CLK_GetPLLClockFreq(); + } + else if(u32ClkSrc == 2UL) + { + if(u32Num == 1UL) + { + u32Clk = CLK_GetPCLK1Freq(); + } + else + { + u32Clk = CLK_GetPCLK0Freq(); + } + } + else + { + u32Clk = __HIRC; + } + + u32Clk /= (((CLK->CLKDIV1 >> (8UL * u32Num)) & CLK_CLKDIV1_SC0DIV_Msk) + 1UL) * 1000UL; + return u32Clk; +} + +/*@}*/ /* end of group SC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_scuart.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_scuart.c new file mode 100644 index 0000000000000000000000000000000000000000..7fa2f5a38e58dec494ed3f082ce0899a042827bb --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_scuart.c @@ -0,0 +1,242 @@ +/**************************************************************************//** + * @file scuart.c + * @version V3.00 + * @brief M480 Smartcard UART mode (SCUART) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +static uint32_t SCUART_GetClock(SC_T *sc); + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SCUART_Driver SCUART Driver + @{ +*/ + + +/** @addtogroup SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions + @{ +*/ + +/** + * @brief The function is used to disable smartcard interface UART mode. + * @param sc The base address of smartcard module. + * @return None + */ +void SCUART_Close(SC_T* sc) +{ + sc->INTEN = 0UL; + sc->UARTCTL = 0UL; + sc->CTL = 0UL; + +} +/** @cond HIDDEN_SYMBOLS */ +/** + * @brief This function returns module clock of specified SC interface + * @param[in] sc The base address of smartcard module. + * @return Module clock of specified SC interface + */ +static uint32_t SCUART_GetClock(SC_T *sc) +{ + uint32_t u32ClkSrc, u32Num, u32Clk; + + if(sc == SC0) + { + u32Num = 0UL; + } + else if(sc == SC1) + { + u32Num = 1UL; + } + else + { + u32Num = 2UL; + } + + u32ClkSrc = (CLK->CLKSEL3 >> (2UL * u32Num)) & CLK_CLKSEL3_SC0SEL_Msk; + + /* Get smartcard module clock */ + if(u32ClkSrc == 0UL) + { + u32Clk = __HXT; + } + else if(u32ClkSrc == 1UL) + { + u32Clk = CLK_GetPLLClockFreq(); + } + else if(u32ClkSrc == 2UL) + { + if(u32Num == 1UL) + { + u32Clk = CLK_GetPCLK1Freq(); + } + else + { + u32Clk = CLK_GetPCLK0Freq(); + } + } + else + { + u32Clk = __HIRC; + } + + u32Clk /= (((CLK->CLKDIV1 >> (8UL * u32Num)) & CLK_CLKDIV1_SC0DIV_Msk) + 1UL); + + + return u32Clk; +} + +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief This function use to enable smartcard module UART mode and set baudrate. + * @param[in] sc The base address of smartcard module. + * @param[in] u32baudrate Target baudrate of smartcard module. + * @return Actual baudrate of smartcard mode + * @details This function configures character width to 8 bits, 1 stop bit, and no parity. + * And can use \ref SCUART_SetLineConfig function to update these settings + * The baudrate clock source comes from SC_CLK/SC_DIV, where SC_CLK is controlled + * by SCxSEL in CLKSEL3 register, SC_DIV is controlled by SCxDIV in CLKDIV1 + * register. Since the baudrate divider is 12-bit wide and must be larger than 4, + * (clock source / baudrate) must be larger or equal to 5 and smaller or equal to + * 4096. Otherwise this function cannot configure SCUART to work with target baudrate. + */ +uint32_t SCUART_Open(SC_T* sc, uint32_t u32baudrate) +{ + uint32_t u32Clk = SCUART_GetClock(sc), u32Div; + + /* Calculate divider for target baudrate */ + u32Div = (u32Clk + (u32baudrate >> 1) - 1UL) / u32baudrate - 1UL; + + /* Enable smartcard interface and stop bit = 1 */ + sc->CTL = SC_CTL_SCEN_Msk | SC_CTL_NSB_Msk; + /* Enable UART mode, disable parity and 8 bit per character */ + sc->UARTCTL = SCUART_CHAR_LEN_8 | SCUART_PARITY_NONE | SC_UARTCTL_UARTEN_Msk; + sc->ETUCTL = u32Div; + + return(u32Clk / (u32Div + 1UL)); +} + +/** + * @brief The function is used to read Rx data from RX FIFO. + * @param[in] sc The base address of smartcard module. + * @param[in] pu8RxBuf The buffer to store receive the data + * @param[in] u32ReadBytes Target number of characters to receive + * @return Actual character number reads to buffer + * @note This function does not block and return immediately if there's no data available + */ +uint32_t SCUART_Read(SC_T* sc, uint8_t pu8RxBuf[], uint32_t u32ReadBytes) +{ + uint32_t u32Count; + + for(u32Count = 0UL; u32Count < u32ReadBytes; u32Count++) + { + if(SCUART_GET_RX_EMPTY(sc)) /* no data available */ + { + break; + } + pu8RxBuf[u32Count] = (uint8_t)SCUART_READ(sc); /* get data from FIFO */ + } + + return u32Count; +} + +/** + * @brief This function use to configure smartcard UART mode line setting. + * @param[in] sc The base address of smartcard module. + * @param[in] u32Baudrate Target baudrate of smartcard module. If this value is 0, UART baudrate will not change. + * @param[in] u32DataWidth The data length, could be + * - \ref SCUART_CHAR_LEN_5 + * - \ref SCUART_CHAR_LEN_6 + * - \ref SCUART_CHAR_LEN_7 + * - \ref SCUART_CHAR_LEN_8 + * @param[in] u32Parity The parity setting, could be + * - \ref SCUART_PARITY_NONE + * - \ref SCUART_PARITY_ODD + * - \ref SCUART_PARITY_EVEN + * @param[in] u32StopBits The stop bit length, could be + * - \ref SCUART_STOP_BIT_1 + * - \ref SCUART_STOP_BIT_2 + * @return Actual baudrate of smartcard + * @details The baudrate clock source comes from SC_CLK/SC_DIV, where SC_CLK is controlled + * by SCxSEL in CLKSEL3 register, SC_DIV is controlled by SCxDIV in CLKDIV1 + * register. Since the baudrate divider is 12-bit wide and must be larger than 4, + * (clock source / baudrate) must be larger or equal to 5 and smaller or equal to + * 4096. Otherwise this function cannot configure SCUART to work with target baudrate. + */ +uint32_t SCUART_SetLineConfig(SC_T* sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits) +{ + + uint32_t u32Clk = SCUART_GetClock(sc), u32Div; + + if(u32Baudrate == 0UL) /* keep original baudrate setting */ + { + u32Div = sc->ETUCTL & SC_ETUCTL_ETURDIV_Msk; + } + else + { + /* Calculate divider for target baudrate */ + u32Div = (u32Clk + (u32Baudrate >> 1) - 1UL)/ u32Baudrate - 1UL; + sc->ETUCTL = u32Div; + } + /* Set stop bit */ + sc->CTL = u32StopBits | SC_CTL_SCEN_Msk; + /* Set character width and parity */ + sc->UARTCTL = u32Parity | u32DataWidth | SC_UARTCTL_UARTEN_Msk; + + return(u32Clk / (u32Div + 1UL)); +} + +/** + * @brief This function use to set receive timeout count. + * @param[in] sc The base address of smartcard module. + * @param[in] u32TOC Rx timeout counter, using baudrate as counter unit. Valid range are 0~0x1FF, + * set this value to 0 will disable timeout counter + * @return None + * @details The time-out counter resets and starts counting whenever the RX buffer received a + * new data word. Once the counter decrease to 1 and no new data is received or CPU + * does not read any data from FIFO, a receiver time-out interrupt will be generated. + */ +void SCUART_SetTimeoutCnt(SC_T* sc, uint32_t u32TOC) +{ + sc->RXTOUT= u32TOC; +} + + +/** + * @brief This function is to write data into transmit FIFO to send data out. + * @param[in] sc The base address of smartcard module. + * @param[in] pu8TxBuf The buffer containing data to send to transmit FIFO. + * @param[in] u32WriteBytes Number of data to send. + * @return None + * @note This function blocks until all data write into FIFO + */ +void SCUART_Write(SC_T* sc,uint8_t pu8TxBuf[], uint32_t u32WriteBytes) +{ + uint32_t u32Count; + + for(u32Count = 0UL; u32Count != u32WriteBytes; u32Count++) + { + /* Wait 'til FIFO not full */ + while(SCUART_GET_TX_FULL(sc)) + { + ; + } + /* Write 1 byte to FIFO */ + sc->DAT = pu8TxBuf[u32Count]; + } +} + + +/*@}*/ /* end of group SCUART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SCUART_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_sdh.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_sdh.c new file mode 100644 index 0000000000000000000000000000000000000000..dbb323b3890d04c05497b08ed305bca2d56a0845 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_sdh.c @@ -0,0 +1,1275 @@ +/**************************************************************************//** + * @file SDH.c + * @version V1.00 + * @brief M480 SDH driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include +#include +#include +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SDH_Driver SDH Driver + @{ +*/ + + +/** @addtogroup SDH_EXPORTED_FUNCTIONS SDH Exported Functions + @{ +*/ +#define SDH_BLOCK_SIZE 512ul + +/** @cond HIDDEN_SYMBOLS */ + +/* global variables */ +/* For response R3 (such as ACMD41, CRC-7 is invalid; but SD controller will still */ +/* calculate CRC-7 and get an error result, software should ignore this error and clear SDISR [CRC_IF] flag */ +/* _sd_uR3_CMD is the flag for it. 1 means software should ignore CRC-7 error */ + +static uint32_t _SDH0_ReferenceClock, _SDH1_ReferenceClock; + +#ifdef __ICCARM__ +#pragma data_alignment = 4 +static uint8_t _SDH0_ucSDHCBuffer[512]; +static uint8_t _SDH1_ucSDHCBuffer[512]; +#else +static uint8_t _SDH0_ucSDHCBuffer[512] __attribute__((aligned(4))); +static uint8_t _SDH1_ucSDHCBuffer[512] __attribute__((aligned(4))); +#endif + +SDH_INFO_T SD0, SD1; + +void SDH_CheckRB(SDH_T *sdh) +{ + while(1) + { + sdh->CTL |= SDH_CTL_CLK8OEN_Msk; + while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk) + { + } + if ((sdh->INTSTS & SDH_INTSTS_DAT0STS_Msk) == SDH_INTSTS_DAT0STS_Msk) + { + break; + } + } +} + + +uint32_t SDH_SDCommand(SDH_T *sdh, uint32_t ucCmd, uint32_t uArg) +{ + volatile uint32_t buf, val = 0ul; + SDH_INFO_T *pSD; + + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + sdh->CMDARG = uArg; + buf = (sdh->CTL&(~SDH_CTL_CMDCODE_Msk))|(ucCmd << 8ul)|(SDH_CTL_COEN_Msk); + sdh->CTL = buf; + + while ((sdh->CTL & SDH_CTL_COEN_Msk) == SDH_CTL_COEN_Msk) + { + if (pSD->IsCardInsert == 0ul) + { + val = SDH_NO_SD_CARD; + } + } + return val; +} + + +uint32_t SDH_SDCmdAndRsp(SDH_T *sdh, uint32_t ucCmd, uint32_t uArg, uint32_t ntickCount) +{ + volatile uint32_t buf; + SDH_INFO_T *pSD; + + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + sdh->CMDARG = uArg; + buf = (sdh->CTL & (~SDH_CTL_CMDCODE_Msk)) | (ucCmd << 8ul) | (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk); + sdh->CTL = buf; + + if (ntickCount > 0ul) + { + while ((sdh->CTL & SDH_CTL_RIEN_Msk) == SDH_CTL_RIEN_Msk) + { + if(ntickCount-- == 0ul) + { + sdh->CTL |= SDH_CTL_CTLRST_Msk; /* reset SD engine */ + return 2ul; + } + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + } + } + else + { + while ((sdh->CTL & SDH_CTL_RIEN_Msk) == SDH_CTL_RIEN_Msk) + { + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + } + } + + if (pSD->R7Flag) + { + uint32_t tmp0 = 0ul, tmp1= 0ul; + tmp1 = sdh->RESP1 & 0xfful; + tmp0 = sdh->RESP0 & 0xful; + if ((tmp1 != 0x55ul) && (tmp0 != 0x01ul)) + { + pSD->R7Flag = 0ul; + return SDH_CMD8_ERROR; + } + } + + if (!pSD->R3Flag) + { + if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) == SDH_INTSTS_CRC7_Msk) /* check CRC7 */ + { + return Successful; + } + else + { + return SDH_CRC7_ERROR; + } + } + else + { + /* ignore CRC error for R3 case */ + pSD->R3Flag = 0ul; + sdh->INTSTS = SDH_INTSTS_CRCIF_Msk; + return Successful; + } +} + + +uint32_t SDH_Swap32(uint32_t val) +{ + uint32_t buf; + + buf = val; + val <<= 24; + val |= (buf<<8) & 0xff0000ul; + val |= (buf>>8) & 0xff00ul; + val |= (buf>>24)& 0xfful; + return val; +} + +/* Get 16 bytes CID or CSD */ +uint32_t SDH_SDCmdAndRsp2(SDH_T *sdh, uint32_t ucCmd, uint32_t uArg, uint32_t puR2ptr[]) +{ + uint32_t i, buf; + uint32_t tmpBuf[5]; + SDH_INFO_T *pSD; + + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + sdh->CMDARG = uArg; + buf = (sdh->CTL&(~SDH_CTL_CMDCODE_Msk))|(ucCmd << 8)|(SDH_CTL_COEN_Msk | SDH_CTL_R2EN_Msk); + sdh->CTL = buf; + + while ((sdh->CTL & SDH_CTL_R2EN_Msk) == SDH_CTL_R2EN_Msk) + { + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + } + + if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) == SDH_INTSTS_CRC7_Msk) + { + for (i=0ul; i<5ul; i++) + { + tmpBuf[i] = SDH_Swap32(sdh->FB[i]); + } + for (i=0ul; i<4ul; i++) + { + puR2ptr[i] = ((tmpBuf[i] & 0x00fffffful)<<8) | ((tmpBuf[i+1ul] & 0xff000000ul)>>24); + } + } + else + { + return SDH_CRC7_ERROR; + } + return Successful; +} + + +uint32_t SDH_SDCmdAndRspDataIn(SDH_T *sdh, uint32_t ucCmd, uint32_t uArg) +{ + volatile uint32_t buf; + SDH_INFO_T *pSD; + + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + sdh->CMDARG = uArg; + buf = (sdh->CTL & (~SDH_CTL_CMDCODE_Msk))|(ucCmd << 8ul)| + (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk); + + sdh->CTL = buf; + + while ((sdh->CTL & SDH_CTL_RIEN_Msk) == SDH_CTL_RIEN_Msk) + { + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + } + + while ((sdh->CTL & SDH_CTL_DIEN_Msk) == SDH_CTL_DIEN_Msk) + { + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + } + + if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) != SDH_INTSTS_CRC7_Msk) + { + /* check CRC7 */ + return SDH_CRC7_ERROR; + } + + if ((sdh->INTSTS & SDH_INTSTS_CRC16_Msk) != SDH_INTSTS_CRC16_Msk) + { + /* check CRC16 */ + return SDH_CRC16_ERROR; + } + return 0ul; +} + +/* there are 8 bits for divider0, maximum is 256 */ +#define SDH_CLK_DIV0_MAX 256ul + +void SDH_Set_clock(SDH_T *sdh, uint32_t sd_clock_khz) +{ + uint32_t rate, div1; + static uint32_t u32SD_ClkSrc = 0ul, u32SD_PwrCtl = 0ul; + + SYS_UnlockReg(); + + /* initial state, clock source use HIRC */ + if (sd_clock_khz <= 400ul) + { + u32SD_PwrCtl = CLK->PWRCTL; + if ((u32SD_PwrCtl & CLK_PWRCTL_HIRCEN_Msk) != 0x4ul) + { + CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk; + } + + if (sdh == SDH0) + { + u32SD_ClkSrc = (CLK->CLKSEL0 & CLK_CLKSEL0_SDH0SEL_Msk); + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_SDH0SEL_Msk) | CLK_CLKSEL0_SDH0SEL_HIRC; + _SDH0_ReferenceClock = (__HIRC / 1000ul); + } + else + { + u32SD_ClkSrc = (CLK->CLKSEL0 & CLK_CLKSEL0_SDH1SEL_Msk); + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_SDH1SEL_Msk) | CLK_CLKSEL0_SDH1SEL_HIRC; + _SDH1_ReferenceClock = (__HIRC / 1000ul); + } + } + /* transfer state, clock source use sys_init() */ + else + { + CLK->PWRCTL = u32SD_PwrCtl; + if (sdh == SDH0) + { + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_SDH0SEL_Msk) | u32SD_ClkSrc; + if(u32SD_ClkSrc == CLK_CLKSEL0_SDH0SEL_HXT) + { + _SDH0_ReferenceClock = (CLK_GetHXTFreq() / 1000ul); + } + else if(u32SD_ClkSrc == CLK_CLKSEL0_SDH0SEL_HIRC) + { + _SDH0_ReferenceClock = (__HIRC / 1000ul); + } + else if(u32SD_ClkSrc == CLK_CLKSEL0_SDH0SEL_PLL) + { + _SDH0_ReferenceClock = (CLK_GetPLLClockFreq() / 1000ul); + } + else if(u32SD_ClkSrc == CLK_CLKSEL0_SDH0SEL_HCLK) + { + _SDH0_ReferenceClock = (CLK_GetHCLKFreq() / 1000ul); + } + } + else + { + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_SDH1SEL_Msk) | u32SD_ClkSrc; + if(u32SD_ClkSrc == CLK_CLKSEL0_SDH1SEL_HXT) + { + _SDH1_ReferenceClock = (CLK_GetHXTFreq() / 1000ul); + } + else if(u32SD_ClkSrc == CLK_CLKSEL0_SDH1SEL_HIRC) + { + _SDH1_ReferenceClock = (__HIRC / 1000ul); + } + else if(u32SD_ClkSrc == CLK_CLKSEL0_SDH1SEL_PLL) + { + _SDH1_ReferenceClock = (CLK_GetPLLClockFreq() / 1000ul); + } + else if(u32SD_ClkSrc == CLK_CLKSEL0_SDH1SEL_HCLK) + { + _SDH1_ReferenceClock = (CLK_GetHCLKFreq() / 1000ul); + } + } + + if(sd_clock_khz >= 50000ul) + { + sd_clock_khz = 50000ul; + } + } + if (sdh == SDH0) + { + rate = _SDH0_ReferenceClock / sd_clock_khz; + + /* choose slower clock if system clock cannot divisible by wanted clock */ + if ((_SDH0_ReferenceClock % sd_clock_khz) != 0ul) + { + rate++; + } + } + else + { + rate = _SDH1_ReferenceClock / sd_clock_khz; + + /* choose slower clock if system clock cannot divisible by wanted clock */ + if ((_SDH1_ReferenceClock % sd_clock_khz) != 0ul) + { + rate++; + } + } + + if(rate >= SDH_CLK_DIV0_MAX) + { + rate = SDH_CLK_DIV0_MAX; + } + + /*--- calculate the second divider CLKDIV0[SDHOST_N]*/ + div1 = (rate - 1ul) & 0xFFul; + + /*--- setup register */ + if (sdh == SDH0) + { + CLK->CLKDIV0 &= ~CLK_CLKDIV0_SDH0DIV_Msk; + CLK->CLKDIV0 |= (div1 << CLK_CLKDIV0_SDH0DIV_Pos); + } + else + { + CLK->CLKDIV3 &= ~CLK_CLKDIV3_SDH1DIV_Msk; + CLK->CLKDIV3 |= (div1 << CLK_CLKDIV3_SDH1DIV_Pos); + } + return; +} + +uint32_t SDH_CardDetection(SDH_T *sdh) +{ + uint32_t i, val = TRUE; + SDH_INFO_T *pSD; + + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + + if ((sdh->INTEN & SDH_INTEN_CDSRC_Msk) == SDH_INTEN_CDSRC_Msk) /* Card detect pin from GPIO */ + { + if ((sdh->INTSTS & SDH_INTSTS_CDSTS_Msk) == SDH_INTSTS_CDSTS_Msk) /* Card remove */ + { + pSD->IsCardInsert = (uint8_t)FALSE; + val = FALSE; + } + else + { + pSD->IsCardInsert = (uint8_t)TRUE; + } + } + else if ((sdh->INTEN & SDH_INTEN_CDSRC_Msk) != SDH_INTEN_CDSRC_Msk) + { + sdh->CTL |= SDH_CTL_CLKKEEP_Msk; + for(i= 0ul; i < 5000ul; i++) + { + } + + if ((sdh->INTSTS & SDH_INTSTS_CDSTS_Msk) == SDH_INTSTS_CDSTS_Msk) /* Card insert */ + { + pSD->IsCardInsert = (uint8_t)TRUE; + } + else + { + pSD->IsCardInsert = (uint8_t)FALSE; + val = FALSE; + } + + sdh->CTL &= ~SDH_CTL_CLKKEEP_Msk; + } + + return val; +} + +uint32_t SDH_Init(SDH_T *sdh) +{ + uint32_t volatile i, status; + uint32_t resp; + uint32_t CIDBuffer[4]; + uint32_t volatile u32CmdTimeOut; + SDH_INFO_T *pSD; + + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + /* set the clock to 300KHz */ + SDH_Set_clock(sdh, 300ul); + + /* power ON 74 clock */ + sdh->CTL |= SDH_CTL_CLK74OEN_Msk; + + while ((sdh->CTL & SDH_CTL_CLK74OEN_Msk) == SDH_CTL_CLK74OEN_Msk) + { + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + } + + SDH_SDCommand(sdh, 0ul, 0ul); /* reset all cards */ + for (i=0x1000ul; i>0ul; i--) + { + } + + /* initial SDHC */ + pSD->R7Flag = 1ul; + u32CmdTimeOut = 0xFFFFFul; + + i = SDH_SDCmdAndRsp(sdh, 8ul, 0x00000155ul, u32CmdTimeOut); + if (i == Successful) + { + /* SD 2.0 */ + SDH_SDCmdAndRsp(sdh, 55ul, 0x00ul, u32CmdTimeOut); + pSD->R3Flag = 1ul; + SDH_SDCmdAndRsp(sdh, 41ul, 0x40ff8000ul, u32CmdTimeOut); /* 2.7v-3.6v */ + resp = sdh->RESP0; + + while ((resp & 0x00800000ul) != 0x00800000ul) /* check if card is ready */ + { + SDH_SDCmdAndRsp(sdh, 55ul, 0x00ul, u32CmdTimeOut); + pSD->R3Flag = 1ul; + SDH_SDCmdAndRsp(sdh, 41ul, 0x40ff8000ul, u32CmdTimeOut); /* 3.0v-3.4v */ + resp = sdh->RESP0; + } + if ((resp & 0x00400000ul) == 0x00400000ul) + { + pSD->CardType = SDH_TYPE_SD_HIGH; + } + else + { + pSD->CardType = SDH_TYPE_SD_LOW; + } + } + else + { + /* SD 1.1 */ + SDH_SDCommand(sdh, 0ul, 0ul); /* reset all cards */ + for (i=0x100ul; i>0ul; i--) + { + } + + i = SDH_SDCmdAndRsp(sdh, 55ul, 0x00ul, u32CmdTimeOut); + if (i == 2ul) /* MMC memory */ + { + + SDH_SDCommand(sdh, 0ul, 0ul); /* reset */ + for (i=0x100ul; i>0ul; i--) + { + } + + pSD->R3Flag = 1ul; + + if (SDH_SDCmdAndRsp(sdh, 1ul, 0x40ff8000ul, u32CmdTimeOut) != 2ul) /* eMMC memory */ + { + resp = sdh->RESP0; + while ((resp & 0x00800000ul) != 0x00800000ul) + { + /* check if card is ready */ + pSD->R3Flag = 1ul; + + SDH_SDCmdAndRsp(sdh, 1ul, 0x40ff8000ul, u32CmdTimeOut); /* high voltage */ + resp = sdh->RESP0; + } + + if ((resp & 0x00400000ul) == 0x00400000ul) + { + pSD->CardType = SDH_TYPE_EMMC; + } + else + { + pSD->CardType = SDH_TYPE_MMC; + } + } + else + { + pSD->CardType = SDH_TYPE_UNKNOWN; + return SDH_ERR_DEVICE; + } + } + else if (i == 0ul) /* SD Memory */ + { + pSD->R3Flag = 1ul; + SDH_SDCmdAndRsp(sdh, 41ul, 0x00ff8000ul, u32CmdTimeOut); /* 3.0v-3.4v */ + resp = sdh->RESP0; + while ((resp & 0x00800000ul) != 0x00800000ul) /* check if card is ready */ + { + SDH_SDCmdAndRsp(sdh, 55ul, 0x00ul, u32CmdTimeOut); + pSD->R3Flag = 1ul; + SDH_SDCmdAndRsp(sdh, 41ul, 0x00ff8000ul, u32CmdTimeOut); /* 3.0v-3.4v */ + resp = sdh->RESP0; + } + pSD->CardType = SDH_TYPE_SD_LOW; + } + else + { + pSD->CardType = SDH_TYPE_UNKNOWN; + return SDH_INIT_ERROR; + } + } + + if (pSD->CardType != SDH_TYPE_UNKNOWN) + { + SDH_SDCmdAndRsp2(sdh, 2ul, 0x00ul, CIDBuffer); + if ((pSD->CardType == SDH_TYPE_MMC) || (pSD->CardType == SDH_TYPE_EMMC)) + { + if ((status = SDH_SDCmdAndRsp(sdh, 3ul, 0x10000ul, 0ul)) != Successful) /* set RCA */ + { + return status; + } + pSD->RCA = 0x10000ul; + } + else + { + if ((status = SDH_SDCmdAndRsp(sdh, 3ul, 0x00ul, 0ul)) != Successful) /* get RCA */ + { + return status; + } + else + { + pSD->RCA = (sdh->RESP0 << 8) & 0xffff0000; + } + } + } + return Successful; +} + + +uint32_t SDH_SwitchToHighSpeed(SDH_T *sdh, SDH_INFO_T *pSD) +{ + uint32_t volatile status=0ul; + uint16_t current_comsumption, busy_status0; + + sdh->DMASA = (uint32_t)pSD->dmabuf; + sdh->BLEN = 63ul; + + if ((status = SDH_SDCmdAndRspDataIn(sdh, 6ul, 0x00ffff01ul)) != Successful) + { + return Fail; + } + + current_comsumption = (uint16_t)(*pSD->dmabuf) << 8; + current_comsumption |= (uint16_t)(*(pSD->dmabuf + 1)); + if (!current_comsumption) + { + return Fail; + } + + busy_status0 = (uint16_t)(*(pSD->dmabuf + 28)) << 8; + busy_status0 |= (uint16_t)(*(pSD->dmabuf + 29)); + + if (!busy_status0) /* function ready */ + { + sdh->DMASA = (uint32_t)pSD->dmabuf; + sdh->BLEN = 63ul; /* 512 bit */ + + if ((status = SDH_SDCmdAndRspDataIn(sdh, 6ul, 0x80ffff01ul)) != Successful) + { + return Fail; + } + + /* function change timing: 8 clocks */ + sdh->CTL |= SDH_CTL_CLK8OEN_Msk; + while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk) + { + } + + current_comsumption = (uint16_t)(*pSD->dmabuf) << 8; + current_comsumption |= (uint16_t)(*(pSD->dmabuf + 1)); + if (!current_comsumption) + { + return Fail; + } + + return Successful; + } + else + { + return Fail; + } +} + + +uint32_t SDH_SelectCardType(SDH_T *sdh) +{ + uint32_t volatile status=0ul; + uint32_t param; + SDH_INFO_T *pSD; + + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + if ((status = SDH_SDCmdAndRsp(sdh, 7ul, pSD->RCA, 0ul)) != Successful) + { + return status; + } + + SDH_CheckRB(sdh); + + /* if SD card set 4bit */ + if (pSD->CardType == SDH_TYPE_SD_HIGH) + { + sdh->DMASA = (uint32_t)pSD->dmabuf; + sdh->BLEN = 0x07ul; /* 64 bit */ + sdh->DMACTL |= SDH_DMACTL_DMARST_Msk; + while ((sdh->DMACTL & SDH_DMACTL_DMARST_Msk) == 0x2); + + if ((status = SDH_SDCmdAndRsp(sdh, 55ul, pSD->RCA, 0ul)) != Successful) + { + return status; + } + if ((status = SDH_SDCmdAndRspDataIn(sdh, 51ul, 0x00ul)) != Successful) + { + return status; + } + + if ((*pSD->dmabuf & 0xful) == 0x2ul) + { + status = SDH_SwitchToHighSpeed(sdh, pSD); + if (status == Successful) + { + /* divider */ + SDH_Set_clock(sdh, SDHC_FREQ); + } + } + + if ((status = SDH_SDCmdAndRsp(sdh, 55ul, pSD->RCA, 0ul)) != Successful) + { + return status; + } + if ((status = SDH_SDCmdAndRsp(sdh, 6ul, 0x02ul, 0ul)) != Successful) /* set bus width */ + { + return status; + } + + sdh->CTL |= SDH_CTL_DBW_Msk; + } + else if (pSD->CardType == SDH_TYPE_SD_LOW) + { + sdh->DMASA = (uint32_t)pSD->dmabuf;; + sdh->BLEN = 0x07ul; + + if ((status = SDH_SDCmdAndRsp(sdh, 55ul, pSD->RCA, 0ul)) != Successful) + { + return status; + } + if ((status = SDH_SDCmdAndRspDataIn(sdh, 51ul, 0x00ul)) != Successful) + { + return status; + } + + /* set data bus width. ACMD6 for SD card, SDCR_DBW for host. */ + if ((status = SDH_SDCmdAndRsp(sdh, 55ul, pSD->RCA, 0ul)) != Successful) + { + return status; + } + + if ((status = SDH_SDCmdAndRsp(sdh, 6ul, 0x02ul, 0ul)) != Successful) + { + return status; + } + + sdh->CTL |= SDH_CTL_DBW_Msk; + } + else if ((pSD->CardType == SDH_TYPE_MMC) ||(pSD->CardType == SDH_TYPE_EMMC)) + { + + if(pSD->CardType == SDH_TYPE_MMC) + { + sdh->CTL &= ~SDH_CTL_DBW_Msk; + } + + /*--- sent CMD6 to MMC card to set bus width to 4 bits mode */ + /* set CMD6 argument Access field to 3, Index to 183, Value to 1 (4-bit mode) */ + param = (3ul << 24) | (183ul << 16) | (1ul << 8); + if ((status = SDH_SDCmdAndRsp(sdh, 6ul, param, 0ul)) != Successful) + { + return status; + } + SDH_CheckRB(sdh); + + sdh->CTL |= SDH_CTL_DBW_Msk; /* set bus width to 4-bit mode for SD host controller */ + + } + + if ((status = SDH_SDCmdAndRsp(sdh, 16ul, SDH_BLOCK_SIZE, 0ul)) != Successful) + { + return status; + } + sdh->BLEN = SDH_BLOCK_SIZE - 1ul; + + SDH_SDCommand(sdh, 7ul, 0ul); + sdh->CTL |= SDH_CTL_CLK8OEN_Msk; + while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk) + { + } + + sdh->INTEN |= SDH_INTEN_BLKDIEN_Msk; + + return Successful; +} + +void SDH_Get_SD_info(SDH_T *sdh) +{ + unsigned int R_LEN, C_Size, MULT, size; + uint32_t Buffer[4]; + //unsigned char *ptr; + SDH_INFO_T *pSD; + + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + SDH_SDCmdAndRsp2(sdh, 9ul, pSD->RCA, Buffer); + + if ((pSD->CardType == SDH_TYPE_MMC) || (pSD->CardType == SDH_TYPE_EMMC)) + { + /* for MMC/eMMC card */ + if ((Buffer[0] & 0xc0000000) == 0xc0000000) + { + /* CSD_STRUCTURE [127:126] is 3 */ + /* CSD version depend on EXT_CSD register in eMMC v4.4 for card size > 2GB */ + SDH_SDCmdAndRsp(sdh, 7ul, pSD->RCA, 0ul); + + //ptr = (uint8_t *)((uint32_t)_SDH_ucSDHCBuffer ); + sdh->DMASA = (uint32_t)pSD->dmabuf;; + sdh->BLEN = 511ul; /* read 512 bytes for EXT_CSD */ + + if (SDH_SDCmdAndRspDataIn(sdh, 8ul, 0x00ul) == Successful) + { + SDH_SDCommand(sdh, 7ul, 0ul); + sdh->CTL |= SDH_CTL_CLK8OEN_Msk; + while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk) + { + } + + pSD->totalSectorN = (uint32_t)(*(pSD->dmabuf+215))<<24; + pSD->totalSectorN |= (uint32_t)(*(pSD->dmabuf+214))<<16; + pSD->totalSectorN |= (uint32_t)(*(pSD->dmabuf+213))<<8; + pSD->totalSectorN |= (uint32_t)(*(pSD->dmabuf+212)); + pSD->diskSize = pSD->totalSectorN / 2ul; + } + } + else + { + /* CSD version v1.0/1.1/1.2 in eMMC v4.4 spec for card size <= 2GB */ + R_LEN = (Buffer[1] & 0x000f0000ul) >> 16; + C_Size = ((Buffer[1] & 0x000003fful) << 2) | ((Buffer[2] & 0xc0000000ul) >> 30); + MULT = (Buffer[2] & 0x00038000ul) >> 15; + size = (C_Size+1ul) * (1ul<<(MULT+2ul)) * (1ul<diskSize = size / 1024ul; + pSD->totalSectorN = size / 512ul; + } + } + else + { + if ((Buffer[0] & 0xc0000000) != 0x0ul) + { + C_Size = ((Buffer[1] & 0x0000003ful) << 16) | ((Buffer[2] & 0xffff0000ul) >> 16); + size = (C_Size+1ul) * 512ul; /* Kbytes */ + + pSD->diskSize = size; + pSD->totalSectorN = size << 1; + } + else + { + R_LEN = (Buffer[1] & 0x000f0000ul) >> 16; + C_Size = ((Buffer[1] & 0x000003fful) << 2) | ((Buffer[2] & 0xc0000000ul) >> 30); + MULT = (Buffer[2] & 0x00038000ul) >> 15; + size = (C_Size+1ul) * (1ul<<(MULT+2ul)) * (1ul<diskSize = size / 1024ul; + pSD->totalSectorN = size / 512ul; + } + } + pSD->sectorSize = (int)512; +} + +/** @endcond HIDDEN_SYMBOLS */ + + +/** + * @brief This function use to reset SD function and select card detection source and pin. + * + * @param[in] sdh Select SDH0 or SDH1. + * @param[in] u32CardDetSrc Select card detection pin from GPIO or DAT3 pin. ( \ref CardDetect_From_GPIO / \ref CardDetect_From_DAT3) + * + * @return None + */ +void SDH_Open(SDH_T *sdh, uint32_t u32CardDetSrc) +{ + sdh->DMACTL = SDH_DMACTL_DMARST_Msk; + while ((sdh->DMACTL & SDH_DMACTL_DMARST_Msk) == SDH_DMACTL_DMARST_Msk) + { + } + + sdh->DMACTL = SDH_DMACTL_DMAEN_Msk; + + sdh->GCTL = SDH_GCTL_GCTLRST_Msk | SDH_GCTL_SDEN_Msk; + while ((sdh->GCTL & SDH_GCTL_GCTLRST_Msk) == SDH_GCTL_GCTLRST_Msk) + { + } + + if (sdh == SDH0) + { + NVIC_EnableIRQ(SDH0_IRQn); + memset(&SD0, 0, sizeof(SDH_INFO_T)); + SD0.dmabuf = _SDH0_ucSDHCBuffer; + } + else if (sdh == SDH1) + { + NVIC_EnableIRQ(SDH1_IRQn); + memset(&SD1, 0, sizeof(SDH_INFO_T)); + SD1.dmabuf = _SDH1_ucSDHCBuffer; + } + else + { + } + + sdh->GCTL = SDH_GCTL_SDEN_Msk; + + if ((u32CardDetSrc & CardDetect_From_DAT3) == CardDetect_From_DAT3) + { + sdh->INTEN &= ~SDH_INTEN_CDSRC_Msk; + } + else + { + sdh->INTEN |= SDH_INTEN_CDSRC_Msk; + } + sdh->INTEN |= SDH_INTEN_CDIEN_Msk; + + sdh->CTL |= SDH_CTL_CTLRST_Msk; + while ((sdh->CTL & SDH_CTL_CTLRST_Msk) == SDH_CTL_CTLRST_Msk) + { + } +} + +/** + * @brief This function use to initial SD card. + * + * @param[in] sdh Select SDH0 or SDH1. + * + * @return None + * + * @details This function is used to initial SD card. + * SD initial state needs 400KHz clock output, driver will use HIRC for SD initial clock source. + * And then switch back to the user's setting. + */ +uint32_t SDH_Probe(SDH_T *sdh) +{ + uint32_t val; + + sdh->GINTEN = 0ul; + sdh->CTL &= ~SDH_CTL_SDNWR_Msk; + sdh->CTL |= 0x09ul << SDH_CTL_SDNWR_Pos; /* set SDNWR = 9 */ + sdh->CTL &= ~SDH_CTL_BLKCNT_Msk; + sdh->CTL |= 0x01ul << SDH_CTL_BLKCNT_Pos; /* set BLKCNT = 1 */ + sdh->CTL &= ~SDH_CTL_DBW_Msk; /* SD 1-bit data bus */ + + if(!(SDH_CardDetection(sdh))) + { + return SDH_NO_SD_CARD; + } + + if ((val = SDH_Init(sdh)) != 0ul) + { + return val; + } + + /* divider */ + if ((SD0.CardType == SDH_TYPE_MMC) || (SD1.CardType == SDH_TYPE_MMC)) + { + SDH_Set_clock(sdh, MMC_FREQ); + } + else + { + SDH_Set_clock(sdh, SD_FREQ); + } + SDH_Get_SD_info(sdh); + + if ((val = SDH_SelectCardType(sdh)) != 0ul) + { + return val; + } + + return 0ul; +} + +/** + * @brief This function use to read data from SD card. + * + * @param[in] sdh Select SDH0 or SDH1. + * @param[out] pu8BufAddr The buffer to receive the data from SD card. + * @param[in] u32StartSec The start read sector address. + * @param[in] u32SecCount The the read sector number of data + * + * @return None + */ +uint32_t SDH_Read(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount) +{ + uint32_t volatile bIsSendCmd = FALSE, buf; + uint32_t volatile reg; + uint32_t volatile i, loop, status; + uint32_t blksize = SDH_BLOCK_SIZE; + + SDH_INFO_T *pSD; + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + if (u32SecCount == 0ul) + { + return SDH_SELECT_ERROR; + } + + if ((status = SDH_SDCmdAndRsp(sdh, 7ul, pSD->RCA, 0ul)) != Successful) + { + return status; + } + SDH_CheckRB(sdh); + + sdh->BLEN = blksize - 1ul; /* the actual byte count is equal to (SDBLEN+1) */ + + if ( (pSD->CardType == SDH_TYPE_SD_HIGH) || (pSD->CardType == SDH_TYPE_EMMC) ) + { + sdh->CMDARG = u32StartSec; + } + else + { + sdh->CMDARG = u32StartSec * blksize; + } + + sdh->DMASA = (uint32_t)pu8BufAddr; + + loop = u32SecCount / 255ul; + for (i=0ul; iDataReadyFlag = (uint8_t)FALSE; + reg = sdh->CTL & ~SDH_CTL_CMDCODE_Msk; + reg = reg | 0xff0000ul; /* set BLK_CNT to 255 */ + if (bIsSendCmd == FALSE) + { + sdh->CTL = reg|(18ul << 8)|(SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk); + bIsSendCmd = TRUE; + } + else + { + sdh->CTL = reg | SDH_CTL_DIEN_Msk; + } + + while(!pSD->DataReadyFlag) + { + if(pSD->DataReadyFlag) + { + break; + } + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + } + + if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) != SDH_INTSTS_CRC7_Msk) /* check CRC7 */ + { + return SDH_CRC7_ERROR; + } + + if ((sdh->INTSTS & SDH_INTSTS_CRC16_Msk) != SDH_INTSTS_CRC16_Msk) /* check CRC16 */ + { + return SDH_CRC16_ERROR; + } + } + + loop = u32SecCount % 255ul; + if (loop != 0ul) + { + pSD->DataReadyFlag = (uint8_t)FALSE; + reg = sdh->CTL & (~SDH_CTL_CMDCODE_Msk); + reg = reg & (~SDH_CTL_BLKCNT_Msk); + reg |= (loop << 16); /* setup SDCR_BLKCNT */ + + if (bIsSendCmd == FALSE) + { + sdh->CTL = reg|(18ul << 8)|(SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk); + bIsSendCmd = TRUE; + } + else + { + sdh->CTL = reg | SDH_CTL_DIEN_Msk; + } + + while(!pSD->DataReadyFlag) + { + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + } + + if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) != SDH_INTSTS_CRC7_Msk) /* check CRC7 */ + { + return SDH_CRC7_ERROR; + } + + if ((sdh->INTSTS & SDH_INTSTS_CRC16_Msk) != SDH_INTSTS_CRC16_Msk) /* check CRC16 */ + { + return SDH_CRC16_ERROR; + } + } + + if (SDH_SDCmdAndRsp(sdh, 12ul, 0ul, 0ul)) /* stop command */ + { + return SDH_CRC7_ERROR; + } + SDH_CheckRB(sdh); + + SDH_SDCommand(sdh, 7ul, 0ul); + sdh->CTL |= SDH_CTL_CLK8OEN_Msk; + while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk) + { + } + + return Successful; +} + + +/** + * @brief This function use to write data to SD card. + * + * @param[in] sdh Select SDH0 or SDH1. + * @param[in] pu8BufAddr The buffer to send the data to SD card. + * @param[in] u32StartSec The start write sector address. + * @param[in] u32SecCount The the write sector number of data. + * + * @return \ref SDH_SELECT_ERROR : u32SecCount is zero. \n + * \ref SDH_NO_SD_CARD : SD card be removed. \n + * \ref SDH_CRC_ERROR : CRC error happen. \n + * \ref SDH_CRC7_ERROR : CRC7 error happen. \n + * \ref Successful : Write data to SD card success. + */ +uint32_t SDH_Write(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount) +{ + uint32_t volatile bIsSendCmd = FALSE; + uint32_t volatile reg; + uint32_t volatile i, loop, status; + + SDH_INFO_T *pSD; + + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + if (u32SecCount == 0ul) + { + return SDH_SELECT_ERROR; + } + + if ((status = SDH_SDCmdAndRsp(sdh, 7ul, pSD->RCA, 0ul)) != Successful) + { + return status; + } + + SDH_CheckRB(sdh); + + /* According to SD Spec v2.0, the write CMD block size MUST be 512, and the start address MUST be 512*n. */ + sdh->BLEN = SDH_BLOCK_SIZE - 1ul; + + if ((pSD->CardType == SDH_TYPE_SD_HIGH) || (pSD->CardType == SDH_TYPE_EMMC)) + { + sdh->CMDARG = u32StartSec; + } + else + { + sdh->CMDARG = u32StartSec * SDH_BLOCK_SIZE; /* set start address for SD CMD */ + } + + sdh->DMASA = (uint32_t)pu8BufAddr; + loop = u32SecCount / 255ul; /* the maximum block count is 0xFF=255 for register SDCR[BLK_CNT] */ + for (i=0ul; iDataReadyFlag = (uint8_t)FALSE; + reg = sdh->CTL & 0xff00c080; + reg = reg | 0xff0000ul; /* set BLK_CNT to 0xFF=255 */ + if (!bIsSendCmd) + { + sdh->CTL = reg|(25ul << 8)|(SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DOEN_Msk); + bIsSendCmd = TRUE; + } + else + { + sdh->CTL = reg | SDH_CTL_DOEN_Msk; + } + + while(!pSD->DataReadyFlag) + { + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + } + + if ((sdh->INTSTS & SDH_INTSTS_CRCIF_Msk) != 0ul) + { + sdh->INTSTS = SDH_INTSTS_CRCIF_Msk; + return SDH_CRC_ERROR; + } + } + + loop = u32SecCount % 255ul; + if (loop != 0ul) + { + pSD->DataReadyFlag = (uint8_t)FALSE; + reg = (sdh->CTL & 0xff00c080) | (loop << 16); + if (!bIsSendCmd) + { + sdh->CTL = reg|(25ul << 8)|(SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DOEN_Msk); + bIsSendCmd = TRUE; + } + else + { + sdh->CTL = reg | SDH_CTL_DOEN_Msk; + } + + while(!pSD->DataReadyFlag) + { + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + } + + if ((sdh->INTSTS & SDH_INTSTS_CRCIF_Msk) != 0ul) + { + sdh->INTSTS = SDH_INTSTS_CRCIF_Msk; + return SDH_CRC_ERROR; + } + } + sdh->INTSTS = SDH_INTSTS_CRCIF_Msk; + + if (SDH_SDCmdAndRsp(sdh, 12ul, 0ul, 0ul)) /* stop command */ + { + return SDH_CRC7_ERROR; + } + SDH_CheckRB(sdh); + + SDH_SDCommand(sdh, 7ul, 0ul); + sdh->CTL |= SDH_CTL_CLK8OEN_Msk; + while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk) + { + } + + return Successful; +} + +/*@}*/ /* end of group SDH_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SDH_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ + + + + + + + + diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_spi.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..0b4c5c789efdb1c1ca5d92fa6d31281db376f8b9 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_spi.c @@ -0,0 +1,1443 @@ +/**************************************************************************//** + * @file spi.c + * @version V3.00 + * @brief M480 series SPI driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SPI_Driver SPI Driver + @{ +*/ + + +/** @addtogroup SPI_EXPORTED_FUNCTIONS SPI Exported Functions + @{ +*/ +static uint32_t SPII2S_GetSourceClockFreq(SPI_T *i2s); + +/** + * @brief This function make SPI module be ready to transfer. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32MasterSlave Decides the SPI module is operating in master mode or in slave mode. (SPI_SLAVE, SPI_MASTER) + * @param[in] u32SPIMode Decides the transfer timing. (SPI_MODE_0, SPI_MODE_1, SPI_MODE_2, SPI_MODE_3) + * @param[in] u32DataWidth Decides the data width of a SPI transaction. + * @param[in] u32BusClock The expected frequency of SPI bus clock in Hz. + * @return Actual frequency of SPI peripheral clock. + * @details By default, the SPI transfer sequence is MSB first, the slave selection signal is active low and the automatic + * slave selection function is disabled. + * In Slave mode, the u32BusClock shall be NULL and the SPI clock divider setting will be 0. + * The actual clock rate may be different from the target SPI clock rate. + * For example, if the SPI source clock rate is 12 MHz and the target SPI bus clock rate is 7 MHz, the + * actual SPI clock rate will be 6MHz. + * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value. + * @note If u32BusClock >= system clock frequency, SPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0. + * @note If u32BusClock >= SPI peripheral clock source, DIVIDER will be set to 0. + * @note In slave mode, the SPI peripheral clock rate will be equal to APB clock rate. + */ +uint32_t SPI_Open(SPI_T *spi, + uint32_t u32MasterSlave, + uint32_t u32SPIMode, + uint32_t u32DataWidth, + uint32_t u32BusClock) +{ + uint32_t u32ClkSrc = 0U, u32Div, u32HCLKFreq, u32RetValue=0U; + + /* Disable I2S mode */ + spi->I2SCTL &= ~SPI_I2SCTL_I2SEN_Msk; + + if(u32DataWidth == 32U) + { + u32DataWidth = 0U; + } + + /* Get system clock frequency */ + u32HCLKFreq = CLK_GetHCLKFreq(); + + if(u32MasterSlave == SPI_MASTER) + { + /* Default setting: slave selection signal is active low; disable automatic slave selection function. */ + spi->SSCTL = SPI_SS_ACTIVE_LOW; + + /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */ + spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode) | SPI_CTL_SPIEN_Msk; + + if(u32BusClock >= u32HCLKFreq) + { + /* Select PCLK as the clock source of SPI */ + if(spi == SPI0) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1; + } + else if(spi == SPI1) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0; + } + else if(spi == SPI2) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK1; + } + else + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI3SEL_Msk)) | CLK_CLKSEL2_SPI3SEL_PCLK0; + } + } + + /* Check clock source of SPI */ + if(spi == SPI0) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK1) + { + /* Clock source is PCLK1 */ + u32ClkSrc = CLK_GetPCLK1Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if(spi == SPI1) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK0) + { + /* Clock source is PCLK0 */ + u32ClkSrc = CLK_GetPCLK0Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if(spi == SPI2) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PCLK1) + { + u32ClkSrc = CLK_GetPCLK1Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PCLK0) + { + /* Clock source is PCLK0 */ + u32ClkSrc = CLK_GetPCLK0Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + + if(u32BusClock >= u32HCLKFreq) + { + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock >= u32ClkSrc) + { + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock == 0U) + { + /* Set DIVIDER to the maximum value 0xFF. f_spi = f_spi_clk_src / (DIVIDER + 1) */ + spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0xFFU + 1U)); + } + else + { + u32Div = (((u32ClkSrc * 10U) / u32BusClock + 5U) / 10U) - 1U; /* Round to the nearest integer */ + if(u32Div > 0xFFU) + { + u32Div = 0xFFU; + spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0xFFU + 1U)); + } + else + { + spi->CLKDIV = (spi->CLKDIV & (~SPI_CLKDIV_DIVIDER_Msk)) | (u32Div << SPI_CLKDIV_DIVIDER_Pos); + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (u32Div + 1U)); + } + } + } + else /* For slave mode, force the SPI peripheral clock rate to equal APB clock rate. */ + { + /* Default setting: slave selection signal is low level active. */ + spi->SSCTL = SPI_SS_ACTIVE_LOW; + + /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */ + spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode) | SPI_CTL_SPIEN_Msk; + + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0U; + + /* Select PCLK as the clock source of SPI */ + if(spi == SPI0) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1; + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK1Freq(); + } + else if(spi == SPI1) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0; + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK0Freq(); + } + else if(spi == SPI2) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK1; + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK1Freq(); + } + else + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI3SEL_Msk)) | CLK_CLKSEL2_SPI3SEL_PCLK0; + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK0Freq(); + } + } + + return u32RetValue; +} + +/** + * @brief Disable SPI controller. + * @param[in] spi The pointer of the specified SPI module. + * @return None + * @details This function will reset SPI controller. + */ +void SPI_Close(SPI_T *spi) +{ + if(spi == SPI0) + { + /* Reset SPI */ + SYS->IPRST1 |= SYS_IPRST1_SPI0RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_SPI0RST_Msk; + } + else if(spi == SPI1) + { + /* Reset SPI */ + SYS->IPRST1 |= SYS_IPRST1_SPI1RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_SPI1RST_Msk; + } + else if(spi == SPI2) + { + /* Reset SPI */ + SYS->IPRST1 |= SYS_IPRST1_SPI2RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_SPI2RST_Msk; + } + else + { + /* Reset SPI */ + SYS->IPRST2 |= SYS_IPRST2_SPI3RST_Msk; + SYS->IPRST2 &= ~SYS_IPRST2_SPI3RST_Msk; + } +} + +/** + * @brief Clear RX FIFO buffer. + * @param[in] spi The pointer of the specified SPI module. + * @return None + * @details This function will clear SPI RX FIFO buffer. The RXEMPTY (SPI_STATUS[8]) will be set to 1. + */ +void SPI_ClearRxFIFO(SPI_T *spi) +{ + spi->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk; +} + +/** + * @brief Clear TX FIFO buffer. + * @param[in] spi The pointer of the specified SPI module. + * @return None + * @details This function will clear SPI TX FIFO buffer. The TXEMPTY (SPI_STATUS[16]) will be set to 1. + * @note The TX shift register will not be cleared. + */ +void SPI_ClearTxFIFO(SPI_T *spi) +{ + spi->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk; +} + +/** + * @brief Disable the automatic slave selection function. + * @param[in] spi The pointer of the specified SPI module. + * @return None + * @details This function will disable the automatic slave selection function and set slave selection signal to inactive state. + */ +void SPI_DisableAutoSS(SPI_T *spi) +{ + spi->SSCTL &= ~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SS_Msk); +} + +/** + * @brief Enable the automatic slave selection function. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32SSPinMask Specifies slave selection pins. (SPI_SS) + * @param[in] u32ActiveLevel Specifies the active level of slave selection signal. (SPI_SS_ACTIVE_HIGH, SPI_SS_ACTIVE_LOW) + * @return None + * @details This function will enable the automatic slave selection function. Only available in Master mode. + * The slave selection pin and the active level will be set in this function. + */ +void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel) +{ + spi->SSCTL = (spi->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk))) | (u32SSPinMask | u32ActiveLevel | SPI_SSCTL_AUTOSS_Msk); +} + +/** + * @brief Set the SPI bus clock. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32BusClock The expected frequency of SPI bus clock in Hz. + * @return Actual frequency of SPI bus clock. + * @details This function is only available in Master mode. The actual clock rate may be different from the target SPI bus clock rate. + * For example, if the SPI source clock rate is 12 MHz and the target SPI bus clock rate is 7 MHz, the actual SPI bus clock + * rate will be 6 MHz. + * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value. + * @note If u32BusClock >= system clock frequency, SPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0. + * @note If u32BusClock >= SPI peripheral clock source, DIVIDER will be set to 0. + */ +uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock) +{ + uint32_t u32ClkSrc, u32HCLKFreq; + uint32_t u32Div, u32RetValue; + + /* Get system clock frequency */ + u32HCLKFreq = CLK_GetHCLKFreq(); + + if(u32BusClock >= u32HCLKFreq) + { + /* Select PCLK as the clock source of SPI */ + if(spi == SPI0) + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1; + else if(spi == SPI1) + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0; + else if(spi == SPI2) + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK1; + else + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI3SEL_Msk)) | CLK_CLKSEL2_SPI3SEL_PCLK0; + } + + /* Check clock source of SPI */ + if(spi == SPI0) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK1) + { + /* Clock source is PCLK1 */ + u32ClkSrc = CLK_GetPCLK1Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if(spi == SPI1) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK0) + { + /* Clock source is PCLK0 */ + u32ClkSrc = CLK_GetPCLK0Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if(spi == SPI2) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PCLK1) + { + /* Clock source is PCLK1 */ + u32ClkSrc = CLK_GetPCLK1Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PCLK0) + { + /* Clock source is PCLK0 */ + u32ClkSrc = CLK_GetPCLK0Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + + if(u32BusClock >= u32HCLKFreq) + { + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock >= u32ClkSrc) + { + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock == 0U) + { + /* Set DIVIDER to the maximum value 0xFF. f_spi = f_spi_clk_src / (DIVIDER + 1) */ + spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0xFFU + 1U)); + } + else + { + u32Div = (((u32ClkSrc * 10U) / u32BusClock + 5U) / 10U) - 1U; /* Round to the nearest integer */ + if(u32Div > 0x1FFU) + { + u32Div = 0x1FFU; + spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0xFFU + 1U)); + } + else + { + spi->CLKDIV = (spi->CLKDIV & (~SPI_CLKDIV_DIVIDER_Msk)) | (u32Div << SPI_CLKDIV_DIVIDER_Pos); + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (u32Div + 1U)); + } + } + + return u32RetValue; +} + +/** + * @brief Configure FIFO threshold setting. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 3. If data width is 8~16 bits, it could be 0 ~ 7. + * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 3. If data width is 8~16 bits, it could be 0 ~ 7. + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold) +{ + spi->FIFOCTL = (spi->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk)) | + (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) | + (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos); +} + +/** + * @brief Get the actual frequency of SPI bus clock. Only available in Master mode. + * @param[in] spi The pointer of the specified SPI module. + * @return Actual SPI bus clock frequency in Hz. + * @details This function will calculate the actual SPI bus clock rate according to the SPInSEL and DIVIDER settings. Only available in Master mode. + */ +uint32_t SPI_GetBusClock(SPI_T *spi) +{ + uint32_t u32Div; + uint32_t u32ClkSrc; + + /* Get DIVIDER setting */ + u32Div = (spi->CLKDIV & SPI_CLKDIV_DIVIDER_Msk) >> SPI_CLKDIV_DIVIDER_Pos; + + /* Check clock source of SPI */ + if(spi == SPI0) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK1) + { + /* Clock source is PCLK1 */ + u32ClkSrc = CLK_GetPCLK1Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if(spi == SPI1) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK0) + { + /* Clock source is PCLK0 */ + u32ClkSrc = CLK_GetPCLK0Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if(spi == SPI2) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PCLK1) + { + /* Clock source is PCLK1 */ + u32ClkSrc = CLK_GetPCLK1Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PCLK0) + { + /* Clock source is PCLK0 */ + u32ClkSrc = CLK_GetPCLK0Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + + /* Return SPI bus clock rate */ + return (u32ClkSrc / (u32Div + 1U)); +} + +/** + * @brief Enable interrupt function. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. It is combination of: + * - \ref SPI_UNIT_INT_MASK + * - \ref SPI_SSACT_INT_MASK + * - \ref SPI_SSINACT_INT_MASK + * - \ref SPI_SLVUR_INT_MASK + * - \ref SPI_SLVBE_INT_MASK + * - \ref SPI_TXUF_INT_MASK + * - \ref SPI_FIFO_TXTH_INT_MASK + * - \ref SPI_FIFO_RXTH_INT_MASK + * - \ref SPI_FIFO_RXOV_INT_MASK + * - \ref SPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Enable SPI related interrupts specified by u32Mask parameter. + */ +void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask) +{ + /* Enable unit transfer interrupt flag */ + if((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK) + { + spi->CTL |= SPI_CTL_UNITIEN_Msk; + } + + /* Enable slave selection signal active interrupt flag */ + if((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK) + { + spi->SSCTL |= SPI_SSCTL_SSACTIEN_Msk; + } + + /* Enable slave selection signal inactive interrupt flag */ + if((u32Mask & SPI_SSINACT_INT_MASK) == SPI_SSINACT_INT_MASK) + { + spi->SSCTL |= SPI_SSCTL_SSINAIEN_Msk; + } + + /* Enable slave TX under run interrupt flag */ + if((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK) + { + spi->SSCTL |= SPI_SSCTL_SLVURIEN_Msk; + } + + /* Enable slave bit count error interrupt flag */ + if((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK) + { + spi->SSCTL |= SPI_SSCTL_SLVBEIEN_Msk; + } + + /* Enable slave TX underflow interrupt flag */ + if((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Enable TX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_TXTH_INT_MASK) == SPI_FIFO_TXTH_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Enable RX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_RXTH_INT_MASK) == SPI_FIFO_RXTH_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Enable RX overrun interrupt flag */ + if((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Enable RX time-out interrupt flag */ + if((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk; + } +} + +/** + * @brief Disable interrupt function. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * This parameter decides which interrupts will be disabled. It is combination of: + * - \ref SPI_UNIT_INT_MASK + * - \ref SPI_SSACT_INT_MASK + * - \ref SPI_SSINACT_INT_MASK + * - \ref SPI_SLVUR_INT_MASK + * - \ref SPI_SLVBE_INT_MASK + * - \ref SPI_TXUF_INT_MASK + * - \ref SPI_FIFO_TXTH_INT_MASK + * - \ref SPI_FIFO_RXTH_INT_MASK + * - \ref SPI_FIFO_RXOV_INT_MASK + * - \ref SPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Disable SPI related interrupts specified by u32Mask parameter. + */ +void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask) +{ + /* Disable unit transfer interrupt flag */ + if((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK) + { + spi->CTL &= ~SPI_CTL_UNITIEN_Msk; + } + + /* Disable slave selection signal active interrupt flag */ + if((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK) + { + spi->SSCTL &= ~SPI_SSCTL_SSACTIEN_Msk; + } + + /* Disable slave selection signal inactive interrupt flag */ + if((u32Mask & SPI_SSINACT_INT_MASK) == SPI_SSINACT_INT_MASK) + { + spi->SSCTL &= ~SPI_SSCTL_SSINAIEN_Msk; + } + + /* Disable slave TX under run interrupt flag */ + if((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK) + { + spi->SSCTL &= ~SPI_SSCTL_SLVURIEN_Msk; + } + + /* Disable slave bit count error interrupt flag */ + if((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK) + { + spi->SSCTL &= ~SPI_SSCTL_SLVBEIEN_Msk; + } + + /* Disable slave TX underflow interrupt flag */ + if((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Disable TX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_TXTH_INT_MASK) == SPI_FIFO_TXTH_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Disable RX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_RXTH_INT_MASK) == SPI_FIFO_RXTH_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Disable RX overrun interrupt flag */ + if((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Disable RX time-out interrupt flag */ + if((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk; + } +} + +/** + * @brief Get interrupt flag. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. It is combination of: + * - \ref SPI_UNIT_INT_MASK + * - \ref SPI_SSACT_INT_MASK + * - \ref SPI_SSINACT_INT_MASK + * - \ref SPI_SLVUR_INT_MASK + * - \ref SPI_SLVBE_INT_MASK + * - \ref SPI_TXUF_INT_MASK + * - \ref SPI_FIFO_TXTH_INT_MASK + * - \ref SPI_FIFO_RXTH_INT_MASK + * - \ref SPI_FIFO_RXOV_INT_MASK + * - \ref SPI_FIFO_RXTO_INT_MASK + * + * @return Interrupt flags of selected sources. + * @details Get SPI related interrupt flags specified by u32Mask parameter. + */ +uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask) +{ + uint32_t u32IntFlag = 0U, u32TmpVal; + + u32TmpVal = spi->STATUS & SPI_STATUS_UNITIF_Msk; + /* Check unit transfer interrupt flag */ + if((u32Mask & SPI_UNIT_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_UNIT_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_SSACTIF_Msk; + /* Check slave selection signal active interrupt flag */ + if((u32Mask & SPI_SSACT_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_SSACT_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_SSINAIF_Msk; + /* Check slave selection signal inactive interrupt flag */ + if((u32Mask & SPI_SSINACT_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_SSINACT_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_SLVURIF_Msk; + /* Check slave TX under run interrupt flag */ + if((u32Mask & SPI_SLVUR_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_SLVUR_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_SLVBEIF_Msk; + /* Check slave bit count error interrupt flag */ + if((u32Mask & SPI_SLVBE_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_SLVBE_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_TXUFIF_Msk; + /* Check slave TX underflow interrupt flag */ + if((u32Mask & SPI_TXUF_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_TXUF_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_TXTHIF_Msk; + /* Check TX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_TXTH_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_FIFO_TXTH_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_RXTHIF_Msk; + /* Check RX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_RXTH_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_FIFO_RXTH_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_RXOVIF_Msk; + /* Check RX overrun interrupt flag */ + if((u32Mask & SPI_FIFO_RXOV_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_FIFO_RXOV_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_RXTOIF_Msk; + /* Check RX time-out interrupt flag */ + if((u32Mask & SPI_FIFO_RXTO_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_FIFO_RXTO_INT_MASK; + } + + return u32IntFlag; +} + +/** + * @brief Clear interrupt flag. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. It could be the combination of: + * - \ref SPI_UNIT_INT_MASK + * - \ref SPI_SSACT_INT_MASK + * - \ref SPI_SSINACT_INT_MASK + * - \ref SPI_SLVUR_INT_MASK + * - \ref SPI_SLVBE_INT_MASK + * - \ref SPI_TXUF_INT_MASK + * - \ref SPI_FIFO_RXOV_INT_MASK + * - \ref SPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Clear SPI related interrupt flags specified by u32Mask parameter. + */ +void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask) +{ + if(u32Mask & SPI_UNIT_INT_MASK) + { + spi->STATUS = SPI_STATUS_UNITIF_Msk; /* Clear unit transfer interrupt flag */ + } + + if(u32Mask & SPI_SSACT_INT_MASK) + { + spi->STATUS = SPI_STATUS_SSACTIF_Msk; /* Clear slave selection signal active interrupt flag */ + } + + if(u32Mask & SPI_SSINACT_INT_MASK) + { + spi->STATUS = SPI_STATUS_SSINAIF_Msk; /* Clear slave selection signal inactive interrupt flag */ + } + + if(u32Mask & SPI_SLVUR_INT_MASK) + { + spi->STATUS = SPI_STATUS_SLVURIF_Msk; /* Clear slave TX under run interrupt flag */ + } + + if(u32Mask & SPI_SLVBE_INT_MASK) + { + spi->STATUS = SPI_STATUS_SLVBEIF_Msk; /* Clear slave bit count error interrupt flag */ + } + + if(u32Mask & SPI_TXUF_INT_MASK) + { + spi->STATUS = SPI_STATUS_TXUFIF_Msk; /* Clear slave TX underflow interrupt flag */ + } + + if(u32Mask & SPI_FIFO_RXOV_INT_MASK) + { + spi->STATUS = SPI_STATUS_RXOVIF_Msk; /* Clear RX overrun interrupt flag */ + } + + if(u32Mask & SPI_FIFO_RXTO_INT_MASK) + { + spi->STATUS = SPI_STATUS_RXTOIF_Msk; /* Clear RX time-out interrupt flag */ + } +} + +/** + * @brief Get SPI status. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related sources. + * Each bit corresponds to a source. + * This parameter decides which flags will be read. It is combination of: + * - \ref SPI_BUSY_MASK + * - \ref SPI_RX_EMPTY_MASK + * - \ref SPI_RX_FULL_MASK + * - \ref SPI_TX_EMPTY_MASK + * - \ref SPI_TX_FULL_MASK + * - \ref SPI_TXRX_RESET_MASK + * - \ref SPI_SPIEN_STS_MASK + * - \ref SPI_SSLINE_STS_MASK + * + * @return Flags of selected sources. + * @details Get SPI related status specified by u32Mask parameter. + */ +uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask) +{ + uint32_t u32Flag = 0U, u32TmpValue; + + u32TmpValue = spi->STATUS & SPI_STATUS_BUSY_Msk; + /* Check busy status */ + if((u32Mask & SPI_BUSY_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_BUSY_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_RXEMPTY_Msk; + /* Check RX empty flag */ + if((u32Mask & SPI_RX_EMPTY_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_RX_EMPTY_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_RXFULL_Msk; + /* Check RX full flag */ + if((u32Mask & SPI_RX_FULL_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_RX_FULL_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_TXEMPTY_Msk; + /* Check TX empty flag */ + if((u32Mask & SPI_TX_EMPTY_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_TX_EMPTY_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_TXFULL_Msk; + /* Check TX full flag */ + if((u32Mask & SPI_TX_FULL_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_TX_FULL_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_TXRXRST_Msk; + /* Check TX/RX reset flag */ + if((u32Mask & SPI_TXRX_RESET_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_TXRX_RESET_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_SPIENSTS_Msk; + /* Check SPIEN flag */ + if((u32Mask & SPI_SPIEN_STS_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_SPIEN_STS_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_SSLINE_Msk; + /* Check SPIx_SS line status */ + if((u32Mask & SPI_SSLINE_STS_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_SSLINE_STS_MASK; + } + + return u32Flag; +} + + +/** + * @brief This function is used to get I2S source clock frequency. + * @param[in] i2s The pointer of the specified I2S module. + * @return I2S source clock frequency (Hz). + * @details Return the source clock frequency according to the setting of SPI0SEL (CLKSEL2[27:26]). + */ +static uint32_t SPII2S_GetSourceClockFreq(SPI_T *i2s) +{ + uint32_t u32Freq; + + if(i2s == SPI0) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT) + { + u32Freq = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL) + { + u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK1) + { + /* Clock source is PCLK1 */ + u32Freq = CLK_GetPCLK1Freq(); + } + else + { + u32Freq = __HIRC; /* Clock source is HIRC */ + } + } + else if(i2s == SPI1) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT) + { + u32Freq = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL) + { + u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK0) + { + /* Clock source is PCLK0 */ + u32Freq = CLK_GetPCLK0Freq(); + } + else + { + u32Freq = __HIRC; /* Clock source is HIRC */ + } + } + else if(i2s == SPI2) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_HXT) + { + u32Freq = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PLL) + { + u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PCLK1) + { + /* Clock source is PCLK1 */ + u32Freq = CLK_GetPCLK1Freq(); + } + else + { + u32Freq = __HIRC; /* Clock source is HIRC */ + } + } + else + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_HXT) + { + u32Freq = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PLL) + { + u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PCLK0) + { + /* Clock source is PCLK0 */ + u32Freq = CLK_GetPCLK0Freq(); + } + else + { + u32Freq = __HIRC; /* Clock source is HIRC */ + } + } + + return u32Freq; +} + +/** + * @brief This function configures some parameters of I2S interface for general purpose use. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32MasterSlave I2S operation mode. Valid values are listed below. + * - \ref SPII2S_MODE_MASTER + * - \ref SPII2S_MODE_SLAVE + * @param[in] u32SampleRate Sample rate + * @param[in] u32WordWidth Data length. Valid values are listed below. + * - \ref SPII2S_DATABIT_8 + * - \ref SPII2S_DATABIT_16 + * - \ref SPII2S_DATABIT_24 + * - \ref SPII2S_DATABIT_32 + * @param[in] u32Channels Audio format. Valid values are listed below. + * - \ref SPII2S_MONO + * - \ref SPII2S_STEREO + * @param[in] u32DataFormat Data format. Valid values are listed below. + * - \ref SPII2S_FORMAT_I2S + * - \ref SPII2S_FORMAT_MSB + * - \ref SPII2S_FORMAT_PCMA + * - \ref SPII2S_FORMAT_PCMB + * @return Real sample rate of master mode or peripheral clock rate of slave mode. + * @details This function will reset SPI/I2S controller and configure I2S controller according to the input parameters. + * Set TX FIFO threshold to 2 and RX FIFO threshold to 1. Both the TX and RX functions will be enabled. + * The actual sample rate may be different from the target sample rate. The real sample rate will be returned for reference. + * @note In slave mode, the SPI peripheral clock rate will be equal to APB clock rate. + */ +uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat) +{ + uint32_t u32Divider; + uint32_t u32BitRate, u32SrcClk, u32RetValue; + + /* Reset SPI/I2S */ + if(i2s == SPI0) + { + SYS->IPRST1 |= SYS_IPRST1_SPI0RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_SPI0RST_Msk; + } + else if(i2s == SPI1) + { + SYS->IPRST1 |= SYS_IPRST1_SPI1RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_SPI1RST_Msk; + } + else if(i2s == SPI2) + { + SYS->IPRST1 |= SYS_IPRST1_SPI2RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_SPI2RST_Msk; + } + else + { + SYS->IPRST2 |= SYS_IPRST2_SPI3RST_Msk; + SYS->IPRST2 &= ~SYS_IPRST2_SPI3RST_Msk; + } + + /* Configure I2S controller */ + i2s->I2SCTL = u32MasterSlave | u32WordWidth | u32Channels | u32DataFormat; + /* Set TX FIFO threshold to 2 and RX FIFO threshold to 1 */ + SPI_SetFIFO(i2s, 2, 1); + + if(u32MasterSlave == SPI_MASTER) + { + /* Get the source clock rate */ + u32SrcClk = SPII2S_GetSourceClockFreq(i2s); + + /* Calculate the bit clock rate */ + u32BitRate = u32SampleRate * ((u32WordWidth >> SPI_I2SCTL_WDWIDTH_Pos) + 1U) * 16U; + u32Divider = ((u32SrcClk / u32BitRate) >> 1U) - 1U; + //u32Divider = ((((u32SrcClk * 10UL / u32BitRate) >> 1U) + 5UL) / 10UL) - 1U; + /* Set BCLKDIV setting */ + i2s->I2SCLK = (i2s->I2SCLK & ~SPI_I2SCLK_BCLKDIV_Msk) | (u32Divider << SPI_I2SCLK_BCLKDIV_Pos); + + /* Calculate bit clock rate */ + u32BitRate = u32SrcClk / ((u32Divider + 1U) * 2U); + /* Calculate real sample rate */ + u32SampleRate = u32BitRate / (((u32WordWidth >> SPI_I2SCTL_WDWIDTH_Pos) + 1U) * 16U); + + /* Enable TX function, RX function and I2S mode. */ + i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); + + /* Return the real sample rate */ + u32RetValue = u32SampleRate; + } + else + { + /* Set BCLKDIV = 0 */ + i2s->I2SCLK &= ~SPI_I2SCLK_BCLKDIV_Msk; + + if(i2s == SPI0) + { + /* Set the peripheral clock rate to equal APB clock rate */ + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1; + /* Enable TX function, RX function and I2S mode. */ + i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK1Freq(); + } + else if(i2s == SPI1) + { + /* Set the peripheral clock rate to equal APB clock rate */ + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0; + /* Enable TX function, RX function and I2S mode. */ + i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK0Freq(); + } + else if(i2s == SPI2) + { + /* Set the peripheral clock rate to equal APB clock rate */ + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK1; + /* Enable TX function, RX function and I2S mode. */ + i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK1Freq(); + } + else + { + /* Set the peripheral clock rate to equal APB clock rate */ + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI3SEL_Msk)) | CLK_CLKSEL2_SPI3SEL_PCLK0; + /* Enable TX function, RX function and I2S mode. */ + i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK0Freq(); + } + } + + return u32RetValue; +} + +/** + * @brief Disable I2S function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details Disable I2S function. + */ +void SPII2S_Close(SPI_T *i2s) +{ + i2s->I2SCTL &= ~SPI_I2SCTL_I2SEN_Msk; +} + +/** + * @brief Enable interrupt function. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref SPII2S_FIFO_TXTH_INT_MASK + * - \ref SPII2S_FIFO_RXTH_INT_MASK + * - \ref SPII2S_FIFO_RXOV_INT_MASK + * - \ref SPII2S_FIFO_RXTO_INT_MASK + * - \ref SPII2S_TXUF_INT_MASK + * - \ref SPII2S_RIGHT_ZC_INT_MASK + * - \ref SPII2S_LEFT_ZC_INT_MASK + * @return None + * @details This function enables the interrupt according to the u32Mask parameter. + */ +void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask) +{ + /* Enable TX threshold interrupt flag */ + if((u32Mask & SPII2S_FIFO_TXTH_INT_MASK) == SPII2S_FIFO_TXTH_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Enable RX threshold interrupt flag */ + if((u32Mask & SPII2S_FIFO_RXTH_INT_MASK) == SPII2S_FIFO_RXTH_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Enable RX overrun interrupt flag */ + if((u32Mask & SPII2S_FIFO_RXOV_INT_MASK) == SPII2S_FIFO_RXOV_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Enable RX time-out interrupt flag */ + if((u32Mask & SPII2S_FIFO_RXTO_INT_MASK) == SPII2S_FIFO_RXTO_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk; + } + + /* Enable TX underflow interrupt flag */ + if((u32Mask & SPII2S_TXUF_INT_MASK) == SPII2S_TXUF_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Enable right channel zero cross interrupt flag */ + if((u32Mask & SPII2S_RIGHT_ZC_INT_MASK) == SPII2S_RIGHT_ZC_INT_MASK) + { + i2s->I2SCTL |= SPI_I2SCTL_RZCIEN_Msk; + } + + /* Enable left channel zero cross interrupt flag */ + if((u32Mask & SPII2S_LEFT_ZC_INT_MASK) == SPII2S_LEFT_ZC_INT_MASK) + { + i2s->I2SCTL |= SPI_I2SCTL_LZCIEN_Msk; + } +} + +/** + * @brief Disable interrupt function. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref SPII2S_FIFO_TXTH_INT_MASK + * - \ref SPII2S_FIFO_RXTH_INT_MASK + * - \ref SPII2S_FIFO_RXOV_INT_MASK + * - \ref SPII2S_FIFO_RXTO_INT_MASK + * - \ref SPII2S_TXUF_INT_MASK + * - \ref SPII2S_RIGHT_ZC_INT_MASK + * - \ref SPII2S_LEFT_ZC_INT_MASK + * @return None + * @details This function disables the interrupt according to the u32Mask parameter. + */ +void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask) +{ + /* Disable TX threshold interrupt flag */ + if((u32Mask & SPII2S_FIFO_TXTH_INT_MASK) == SPII2S_FIFO_TXTH_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Disable RX threshold interrupt flag */ + if((u32Mask & SPII2S_FIFO_RXTH_INT_MASK) == SPII2S_FIFO_RXTH_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Disable RX overrun interrupt flag */ + if((u32Mask & SPII2S_FIFO_RXOV_INT_MASK) == SPII2S_FIFO_RXOV_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Disable RX time-out interrupt flag */ + if((u32Mask & SPII2S_FIFO_RXTO_INT_MASK) == SPII2S_FIFO_RXTO_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk; + } + + /* Disable TX underflow interrupt flag */ + if((u32Mask & SPII2S_TXUF_INT_MASK) == SPII2S_TXUF_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Disable right channel zero cross interrupt flag */ + if((u32Mask & SPII2S_RIGHT_ZC_INT_MASK) == SPII2S_RIGHT_ZC_INT_MASK) + { + i2s->I2SCTL &= ~SPI_I2SCTL_RZCIEN_Msk; + } + + /* Disable left channel zero cross interrupt flag */ + if((u32Mask & SPII2S_LEFT_ZC_INT_MASK) == SPII2S_LEFT_ZC_INT_MASK) + { + i2s->I2SCTL &= ~SPI_I2SCTL_LZCIEN_Msk; + } +} + +/** + * @brief Enable master clock (MCLK). + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32BusClock The target MCLK clock rate. + * @return Actual MCLK clock rate + * @details Set the master clock rate according to u32BusClock parameter and enable master clock output. + * The actual master clock rate may be different from the target master clock rate. The real master clock rate will be returned for reference. + */ +uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock) +{ + uint32_t u32Divider; + uint32_t u32SrcClk, u32RetValue; + + u32SrcClk = SPII2S_GetSourceClockFreq(i2s); + if(u32BusClock == u32SrcClk) + { + u32Divider = 0U; + } + else + { + u32Divider = (u32SrcClk / u32BusClock) >> 1U; + /* MCLKDIV is a 6-bit width configuration. The maximum value is 0x3F. */ + if(u32Divider > 0x3FU) + { + u32Divider = 0x3FU; + } + } + + /* Write u32Divider to MCLKDIV (SPI_I2SCLK[5:0]) */ + i2s->I2SCLK = (i2s->I2SCLK & ~SPI_I2SCLK_MCLKDIV_Msk) | (u32Divider << SPI_I2SCLK_MCLKDIV_Pos); + + /* Enable MCLK output */ + i2s->I2SCTL |= SPI_I2SCTL_MCLKEN_Msk; + + if(u32Divider == 0U) + { + u32RetValue = u32SrcClk; /* If MCLKDIV=0, master clock rate is equal to the source clock rate. */ + } + else + { + u32RetValue = ((u32SrcClk >> 1U) / u32Divider); /* If MCLKDIV>0, master clock rate = source clock rate / (MCLKDIV * 2) */ + } + + return u32RetValue; +} + +/** + * @brief Disable master clock (MCLK). + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details Clear MCLKEN bit of SPI_I2SCTL register to disable master clock output. + */ +void SPII2S_DisableMCLK(SPI_T *i2s) +{ + i2s->I2SCTL &= ~SPI_I2SCTL_MCLKEN_Msk; +} + +/** + * @brief Configure FIFO threshold setting. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 3. + * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 3. + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold) +{ + i2s->FIFOCTL = (i2s->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk)) | + (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) | + (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos); +} + +/*@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_spim.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_spim.c new file mode 100644 index 0000000000000000000000000000000000000000..6715f4469716933179fa1e3fb90f3a6dd59eb00b --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_spim.c @@ -0,0 +1,1308 @@ +/**************************************************************************//** + * @file spim.c + * @version V1.00 + * @brief M480 series SPIM driver + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SPIM_Driver SPIM Driver + @{ +*/ + +/** @addtogroup SPIM_EXPORTED_FUNCTIONS SPIM Exported Functions + @{ +*/ + + +/** @cond HIDDEN_SYMBOLS */ + + +#define ENABLE_DEBUG 0 + +#if ENABLE_DEBUG +#define SPIM_DBGMSG printf +#else +#define SPIM_DBGMSG(...) do { } while (0) /* disable debug */ +#endif + +static volatile uint8_t g_Supported_List[] = +{ + MFGID_WINBOND, + MFGID_MXIC, + MFGID_EON, + MFGID_ISSI, + MFGID_SPANSION +}; + +static void N_delay(int n); +static void SwitchNBitOutput(uint32_t u32NBit); +static void SwitchNBitInput(uint32_t u32NBit); +static void spim_write(uint8_t pu8TxBuf[], uint32_t u32NTx); +static void spim_read(uint8_t pu8RxBuf[], uint32_t u32NRx); +static void SPIM_WriteStatusRegister(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit); +static void SPIM_ReadStatusRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit); +static void SPIM_ReadStatusRegister2(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit); +static void SPIM_WriteStatusRegister2(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit); +static void SPIM_ReadStatusRegister3(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit); +static void SPIM_ReadSecurityRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit); +static int spim_is_write_done(uint32_t u32NBit); +static int spim_wait_write_done(uint32_t u32NBit); +static void spim_set_write_enable(int isEn, uint32_t u32NBit); +static void spim_enable_spansion_quad_mode(int isEn); +static void spim_eon_set_qpi_mode(int isEn); +static void SPIM_SPANSION_4Bytes_Enable(int isEn, uint32_t u32NBit); +static void SPIM_WriteInPageDataByIo(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint8_t wrCmd, + uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat, int isSync); +static void SPIM_WriteInPageDataByPageWrite(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, + uint8_t pu8TxBuf[], uint32_t wrCmd, int isSync); + + +static void N_delay(int n) +{ + while (n-- > 0) + { + __NOP(); + } +} + +static void SwitchNBitOutput(uint32_t u32NBit) +{ + switch (u32NBit) + { + case 1UL: + SPIM_ENABLE_SING_OUTPUT_MODE(); /* 1-bit, Output. */ + break; + + case 2UL: + SPIM_ENABLE_DUAL_OUTPUT_MODE(); /* 2-bit, Output. */ + break; + + case 4UL: + SPIM_ENABLE_QUAD_OUTPUT_MODE(); /* 4-bit, Output. */ + break; + + default: + break; + } +} + +static void SwitchNBitInput(uint32_t u32NBit) +{ + switch (u32NBit) + { + case 1UL: + SPIM_ENABLE_SING_INPUT_MODE(); /* 1-bit, Input. */ + break; + + case 2UL: + SPIM_ENABLE_DUAL_INPUT_MODE(); /* 2-bit, Input. */ + break; + + case 4UL: + SPIM_ENABLE_QUAD_INPUT_MODE(); /* 4-bit, Input. */ + break; + + default: + break; + } +} + + +/** + * @brief Write data to SPI slave. + * @param pu8TxBuf Transmit buffer. + * @param u32NTx Number of bytes to transmit. + * @return None. + */ +static void spim_write(uint8_t pu8TxBuf[], uint32_t u32NTx) +{ + uint32_t buf_idx = 0UL; + + while (u32NTx) + { + uint32_t dataNum = 0UL, dataNum2; + + if (u32NTx >= 16UL) + { + dataNum = 4UL; + } + else if (u32NTx >= 12UL) + { + dataNum = 3UL; + } + else if (u32NTx >= 8UL) + { + dataNum = 2UL; + } + else if (u32NTx >= 4UL) + { + dataNum = 1UL; + } + + dataNum2 = dataNum; + while (dataNum2) + { + uint32_t tmp; + + memcpy(&tmp, &pu8TxBuf[buf_idx], 4U); + buf_idx += 4UL; + u32NTx -= 4UL; + + dataNum2 --; + /* *((__O uint32_t *) &SPIM->TX0 + dataNum2) = tmp; */ + SPIM->TX[dataNum2] = tmp; + } + + if (dataNum) + { + SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO); /* Switch to Normal mode. */ + SPIM_SET_DATA_WIDTH(32UL); + SPIM_SET_DATA_NUM(dataNum); + SPIM_SET_GO(); + SPIM_WAIT_FREE(); + } + + if (u32NTx && (u32NTx < 4UL)) + { + uint32_t rnm, tmp; + + rnm = u32NTx; + memcpy(&tmp, &pu8TxBuf[buf_idx], u32NTx); + buf_idx += u32NTx; + u32NTx = 0UL; + SPIM->TX[0] = tmp; + + SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO); /* Switch to Normal mode. */ + SPIM_SET_DATA_WIDTH(rnm * 8UL); + SPIM_SET_DATA_NUM(1UL); + SPIM_SET_GO(); + SPIM_WAIT_FREE(); + } + } +} + +/** + * @brief Read data from SPI slave. + * @param pu8TxBuf Receive buffer. + * @param u32NRx Size of receive buffer in bytes. + * @return None. + */ +static void spim_read(uint8_t pu8RxBuf[], uint32_t u32NRx) +{ + uint32_t buf_idx = 0UL; + + while (u32NRx) + { + uint32_t dataNum = 0UL; /* number of words */ + + if (u32NRx >= 16UL) + { + dataNum = 4UL; + } + else if (u32NRx >= 12UL) + { + dataNum = 3UL; + } + else if (u32NRx >= 8UL) + { + dataNum = 2UL; + } + else if (u32NRx >= 4UL) + { + dataNum = 1UL; + } + + if (dataNum) + { + SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO); /* Switch to Normal mode. */ + SPIM_SET_DATA_WIDTH(32UL); + SPIM_SET_DATA_NUM(dataNum); + SPIM_SET_GO(); + SPIM_WAIT_FREE(); + } + + while (dataNum) + { + uint32_t tmp; + + tmp = SPIM->RX[dataNum-1UL]; + memcpy(&pu8RxBuf[buf_idx], &tmp, 4U); + buf_idx += 4UL; + dataNum --; + u32NRx -= 4UL; + } + + if (u32NRx && (u32NRx < 4UL)) + { + uint32_t tmp; + + SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO); /* Switch to Normal mode. */ + SPIM_SET_DATA_WIDTH(u32NRx * 8UL); + SPIM_SET_DATA_NUM(1UL); + SPIM_SET_GO(); + SPIM_WAIT_FREE(); + + tmp = SPIM->RX[0]; + memcpy(&pu8RxBuf[buf_idx], &tmp, u32NRx); + buf_idx += u32NRx; + u32NRx = 0UL; + } + } +} + +/** + * @brief Issue Read Status Register #1 command. + * @param dataBuf Receive buffer. + * @param u32NRx Size of receive buffer. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +static void SPIM_ReadStatusRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit) +{ + uint8_t cmdBuf[] = {OPCODE_RDSR}; /* 1-byte Read Status Register #1 command. */ + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SwitchNBitInput(u32NBit); + spim_read(dataBuf, u32NRx); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +/** + * @brief Issue Write Status Register #1 command. + * @param dataBuf Transmit buffer. + * @param u32NTx Size of transmit buffer. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +static void SPIM_WriteStatusRegister(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit) +{ + uint8_t cmdBuf[] = {OPCODE_WRSR, 0x00U}; /* 1-byte Write Status Register #1 command + 1-byte data. */ + + cmdBuf[1] = dataBuf[0]; + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +/** + * @brief Issue Read Status Register #2 command. + * @param dataBuf Receive buffer. + * @param u32NRx Size of receive buffer. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +static void SPIM_ReadStatusRegister2(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit) +{ + uint8_t cmdBuf[] = {OPCODE_RDSR2}; /* 1-byte Read Status Register #1 command. */ + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SwitchNBitInput(u32NBit); + spim_read(dataBuf, u32NRx); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +/** + * @brief Issue Winbond Write Status Register command. This command write both Status Register-1 + * and Status Register-2. + * @param dataBuf Transmit buffer. + * @param u32NTx Size of transmit buffer. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +static void SPIM_WriteStatusRegister2(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit) +{ + uint8_t cmdBuf[3] = {OPCODE_WRSR, 0U, 0U}; + + cmdBuf[1] = dataBuf[0]; + cmdBuf[2] = dataBuf[1]; + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +#if 0 /* not used */ +/** + * @brief Issue Write Status Register #3 command. + * @param dataBuf Transmit buffer. + * @param u32NTx Size of transmit buffer. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +static void SPIM_WriteStatusRegister3(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit) +{ + uint8_t cmdBuf[] = {OPCODE_WRSR3, 0x00U}; /* 1-byte Write Status Register #2 command + 1-byte data. */ + cmdBuf[1] = dataBuf[0]; + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} +#endif + +/** + * @brief Issue Read Status Register #3 command. + * @param dataBuf Receive buffer. + * @param u32NRx Size of receive buffer. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +static void SPIM_ReadStatusRegister3(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit) +{ + uint8_t cmdBuf[] = {OPCODE_RDSR3}; /* 1-byte Read Status Register #1 command. */ + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SwitchNBitInput(u32NBit); + spim_read(dataBuf, u32NRx); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +#if 0 /* not used */ +/** + * @brief Issue Write Security Register command. + * @param dataBuf Transmit buffer. + * @param u32NTx Size of transmit buffer. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +static void SPIM_WriteSecurityRegister(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit) +{ + uint8_t cmdBuf[] = {OPCODE_WRSCUR, 0x00U}; /* 1-byte Write Status Register #2 command + 1-byte data. */ + cmdBuf[1] = dataBuf[0]; + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} +#endif + +/** + * @brief Issue Read Security Register command. + * @param dataBuf Receive buffer. + * @param u32NRx Size of receive buffer. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +static void SPIM_ReadSecurityRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit) +{ + uint8_t cmdBuf[] = {OPCODE_RDSCUR}; /* 1-byte Read Status Register #1 command. */ + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SwitchNBitInput(u32NBit); + spim_read(dataBuf, u32NRx); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +/** + * @brief Check if Erase/Write is done. + * @return 0: Not done. 1: Done. + */ +static int spim_is_write_done(uint32_t u32NBit) +{ + uint8_t status[1]; + SPIM_ReadStatusRegister(status, sizeof (status), u32NBit); + return ! (status[0] & SR_WIP); +} + +/** + * @brief Wait until Erase/Write done. + * @param u32NBit N-bit transmit/receive. + * @return 0 SPIM write done. + */ +static int spim_wait_write_done(uint32_t u32NBit) +{ + uint32_t count; + int ret = -1; + + for (count = 0UL; count < SystemCoreClock/1000UL; count++) + { + if (spim_is_write_done(u32NBit)) + { + ret = 0; + break; + } + } + if (ret != 0) + { + SPIM_DBGMSG("spim_wait_write_done time-out!!\n"); + } + return ret; +} + +/** + * @brief Issue Write Enable/disable command. + * @param isEn Enable/disable. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +static void spim_set_write_enable(int isEn, uint32_t u32NBit) +{ + uint8_t cmdBuf[] = {0U}; /* 1-byte Write Enable command. */ + cmdBuf[0] = isEn ? OPCODE_WREN : OPCODE_WRDI; + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief Get SPIM serial clock. + * @return SPI serial clock. + * @details This function calculates the serial clock of SPI in Hz. + */ +uint32_t SPIM_GetSClkFreq(void) +{ + uint32_t clkDiv = SPIM_GET_CLOCK_DIVIDER(); + + return clkDiv ? SystemCoreClock / (clkDiv * 2U) : SystemCoreClock; +} + +/** + * @brief Initialize SPIM flash. + * @param clrWP Clear Write Protect or not. + * @return 0 Success. + * @return -1 Unrecognized manufacture ID or failed on reading manufacture ID. + */ +int SPIM_InitFlash(int clrWP) +{ + uint8_t idBuf[3]; + uint8_t cmdBuf[1]; + uint32_t i; + int32_t ret = -1; + + SPIM_SET_SS_ACTLVL(0); + + /* + * Because not sure in SPI or QPI mode, do QPI reset and then SPI reset. + */ + /* QPI Reset Enable */ + cmdBuf[0] = OPCODE_RSTEN; + SPIM_SET_SS_EN(1); /* CS activated. */ + SPIM_ENABLE_QUAD_OUTPUT_MODE(); /* 1-bit, Output. */ + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + + /* QPI Reset */ + cmdBuf[0] = OPCODE_RST; + SPIM_SET_SS_EN(1); /* CS activated. */ + SPIM_ENABLE_QUAD_OUTPUT_MODE(); /* 1-bit, Output. */ + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + + /* SPI ResetEnable */ + cmdBuf[0] = OPCODE_RSTEN; + SPIM_SET_SS_EN(1); /* CS activated. */ + SPIM_ENABLE_SING_OUTPUT_MODE(); /* 1-bit, Output. */ + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + + /* SPI Reset */ + cmdBuf[0] = OPCODE_RST; + SPIM_SET_SS_EN(1); /* CS activated. */ + SPIM_ENABLE_SING_OUTPUT_MODE(); /* 1-bit, Output. */ + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + + if (clrWP) + { + uint8_t dataBuf[] = {0x00U}; + + spim_set_write_enable(1, 1UL); /* Clear Block Protect. */ + SPIM_WriteStatusRegister(dataBuf, sizeof (dataBuf), 1U); + spim_wait_write_done(1UL); + } + + SPIM_ReadJedecId(idBuf, sizeof (idBuf), 1UL); + + /* printf("ID: 0x%x, 0x%x, px%x\n", idBuf[0], idBuf[1], idBuf[2]); */ + + for (i = 0UL; i < sizeof(g_Supported_List)/sizeof(g_Supported_List[0]); i++) + { + if (idBuf[0] == g_Supported_List[i]) + { + ret = 0; + } + } + if (ret != 0) + { + SPIM_DBGMSG("Flash initialize failed!! 0x%x\n", idBuf[0]); + } + return ret; +} + +/** + * @brief Issue JEDEC ID command. + * @param idBuf ID buffer. + * @param u32NRx Size of ID buffer. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +void SPIM_ReadJedecId(uint8_t idBuf[], uint32_t u32NRx, uint32_t u32NBit) +{ + uint8_t cmdBuf[] = { OPCODE_RDID }; /* 1-byte JEDEC ID command. */ + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SwitchNBitInput(u32NBit); + spim_read(idBuf, u32NRx); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +/** @cond HIDDEN_SYMBOLS */ + +static void spim_enable_spansion_quad_mode(int isEn) +{ + uint8_t cmdBuf[3]; + uint8_t dataBuf[1], status1; + + cmdBuf[0] = 0x5U; /* Read Status Register-1 */ + + SPIM_SET_SS_EN(1); + SwitchNBitOutput(1UL); + spim_write(cmdBuf, sizeof (cmdBuf)); + SwitchNBitInput(1UL); + spim_read(dataBuf, sizeof (dataBuf)); + SPIM_SET_SS_EN(0); + /* SPIM_DBGMSG("SR1 = 0x%x\n", dataBuf[0]); */ + + status1 = dataBuf[0]; + + cmdBuf[0] = 0x35U; /* Read Configuration Register-1 */ + + SPIM_SET_SS_EN(1); + SwitchNBitOutput(1UL); + spim_write(cmdBuf, sizeof (cmdBuf)); + SwitchNBitInput(1UL); + spim_read(dataBuf, sizeof (dataBuf)); + SPIM_SET_SS_EN(0); + /* SPIM_DBGMSG("CR1 = 0x%x\n", dataBuf[0]); */ + + spim_set_write_enable(1, 1UL); + + cmdBuf[0] = 0x1U; /* Write register */ + cmdBuf[1] = status1; + + if (isEn) + { + cmdBuf[2] = dataBuf[0] | 0x2U; /* set QUAD */ + } + else + { + cmdBuf[2] = dataBuf[0] & ~0x2U; /* clear QUAD */ + } + + SPIM_SET_SS_EN(1); + SwitchNBitOutput(1UL); + spim_write(cmdBuf, 3UL); + SPIM_SET_SS_EN(0); + + spim_set_write_enable(0, 1UL); + + + cmdBuf[0] = 0x35U; /* Read Configuration Register-1 */ + + SPIM_SET_SS_EN(1); + SwitchNBitOutput(1UL); + spim_write(cmdBuf, sizeof (cmdBuf)); + SwitchNBitInput(1UL); + spim_read(dataBuf, sizeof (dataBuf)); + SPIM_SET_SS_EN(0); + + /* SPIM_DBGMSG("CR1 = 0x%x\n", dataBuf[0]); */ + N_delay(10000); +} + +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief Set Quad Enable/disable. + * @param isEn Enable/disable. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +void SPIM_SetQuadEnable(int isEn, uint32_t u32NBit) +{ + uint8_t idBuf[3]; + uint8_t dataBuf[2]; + + SPIM_ReadJedecId(idBuf, sizeof (idBuf), u32NBit); + + SPIM_DBGMSG("SPIM_SetQuadEnable - Flash ID is 0x%x\n", idBuf[0]); + + switch (idBuf[0]) + { + case MFGID_WINBOND: /* Winbond SPI flash */ + SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit); + SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit); + SPIM_DBGMSG("Status Register: 0x%x - 0x%x\n", dataBuf[0], dataBuf[1]); + if (isEn) + { + dataBuf[1] |= SR2_QE; + } + else + { + dataBuf[1] &= ~SR2_QE; + } + + spim_set_write_enable(1, u32NBit); /* Write Enable. */ + SPIM_WriteStatusRegister2(dataBuf, sizeof (dataBuf), u32NBit); + spim_wait_write_done(u32NBit); + + SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit); + SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit); + SPIM_DBGMSG("Status Register: 0x%x - 0x%x\n", dataBuf[0], dataBuf[1]); + break; + + case MFGID_MXIC: /* MXIC SPI flash. */ + case MFGID_EON: + case MFGID_ISSI: /* ISSI SPI flash. */ + spim_set_write_enable(1, u32NBit); /* Write Enable. */ + dataBuf[0] = isEn ? SR_QE : 0U; + SPIM_WriteStatusRegister(dataBuf, sizeof (dataBuf), u32NBit); + spim_wait_write_done(u32NBit); + break; + + case MFGID_SPANSION: + spim_enable_spansion_quad_mode(isEn); + break; + + default: + break; + } +} + +/** + * @brief Enter/exit QPI mode. + * @param isEn Enable/disable. + * @return None. + */ +static void spim_eon_set_qpi_mode(int isEn) +{ + uint8_t cmdBuf[1]; /* 1-byte command. */ + + uint8_t status[1]; + SPIM_ReadStatusRegister(status, sizeof (status), 1UL); + SPIM_DBGMSG("Status: 0x%x\n", status[0]); + + if (isEn) /* Assume in SPI mode. */ + { + cmdBuf[0] = OPCODE_ENQPI; + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(1UL); + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + } + else /* Assume in QPI mode. */ + { + cmdBuf[0] = OPCODE_EXQPI; + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(4UL); + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + } + + SPIM_ReadStatusRegister(status, sizeof (status), 1UL); + SPIM_DBGMSG("Status: 0x%x\n", status[0]); +} + + +static void SPIM_SPANSION_4Bytes_Enable(int isEn, uint32_t u32NBit) +{ + uint8_t cmdBuf[2]; + uint8_t dataBuf[1]; + + cmdBuf[0] = OPCODE_BRRD; + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, 1UL); + SwitchNBitInput(1UL); + spim_read(dataBuf, 1UL); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + + SPIM_DBGMSG("Bank Address register= 0x%x\n", dataBuf[0]); + + cmdBuf[0] = OPCODE_BRWR; + + if (isEn) + { + cmdBuf[1] = dataBuf[0] | 0x80U; /* set EXTADD */ + } + else + { + cmdBuf[1] = dataBuf[0] & ~0x80U; /* clear EXTADD */ + } + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(1UL); + spim_write(cmdBuf, 2UL); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +/** @cond HIDDEN_SYMBOLS */ + +/** + * @brief Query 4-byte address mode enabled or not. + * @param u32NBit N-bit transmit/receive. + * @return 0: 4-byte address mode disabled. 1: 4-byte address mode enabled. + */ +int SPIM_Is4ByteModeEnable(uint32_t u32NBit) +{ + int isEn = 0; + int isSupt = 0; + uint8_t idBuf[3]; + uint8_t dataBuf[1]; + + SPIM_ReadJedecId(idBuf, sizeof (idBuf), u32NBit); + + /* Based on Flash size, check if 4-byte address mode is supported. */ + switch (idBuf[0]) + { + case MFGID_WINBOND: + case MFGID_MXIC: + case MFGID_EON: + isSupt = (idBuf[2] < 0x19U) ? 0L : 1L; + break; + + case MFGID_ISSI: + isSupt = (idBuf[2] < 0x49U) ? 0L : 1L; + break; + + default: + break; + } + + if (isSupt != 0) + { + if (idBuf[0] == MFGID_WINBOND) + { + /* Winbond SPI flash. */ + SPIM_ReadStatusRegister3(dataBuf, sizeof (dataBuf), u32NBit); + isEn = !! (dataBuf[0] & SR3_ADR); + } + else if ((idBuf[0] == MFGID_MXIC) || (idBuf[0] ==MFGID_EON)) + { + /* MXIC/EON SPI flash. */ + SPIM_ReadSecurityRegister(dataBuf, sizeof (dataBuf), u32NBit); + isEn = !! (dataBuf[0] & SCUR_4BYTE); + } + } + + return isEn; +} + +/** @endcond HIDDEN_SYMBOLS */ + + +/** + * @brief Enter/Exit 4-byte address mode. + * @param isEn Enable/disable. + * @param u32NBit N-bit transmit/receive. + * @return 0 success + * -1 failed + */ +int SPIM_Enable_4Bytes_Mode(int isEn, uint32_t u32NBit) +{ + int isSupt = 0L, ret = -1; + uint8_t idBuf[3]; + uint8_t cmdBuf[1]; /* 1-byte Enter/Exit 4-Byte Mode command. */ + + SPIM_ReadJedecId(idBuf, sizeof (idBuf), u32NBit); + + /* Based on Flash size, check if 4-byte address mode is supported. */ + switch (idBuf[0]) + { + case MFGID_WINBOND: + case MFGID_MXIC: + case MFGID_EON: + isSupt = (idBuf[2] < 0x19U) ? 0L : 1L; + break; + + case MFGID_ISSI: + isSupt = (idBuf[2] < 0x49U) ? 0L : 1L; + break; + + case MFGID_SPANSION: + SPIM_SPANSION_4Bytes_Enable(isEn, u32NBit); + isSupt = 1L; + ret = 0L; + break; + + default: + break; + } + + if ((isSupt) && (idBuf[0] != MFGID_SPANSION)) + { + cmdBuf[0] = isEn ? OPCODE_EN4B : OPCODE_EX4B; + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + + /* + * FIXME: Per test, 4BYTE Indicator bit doesn't set after EN4B, which + * doesn't match spec(MX25L25635E), so skip the check below. + */ + if (idBuf[0] != MFGID_MXIC) + { + if (isEn) + { + while (! SPIM_Is4ByteModeEnable(u32NBit)) { } + } + else + { + while (SPIM_Is4ByteModeEnable(u32NBit)) { } + } + } + ret = 0; + } + return ret; +} + + +void SPIM_WinbondUnlock(uint32_t u32NBit) +{ + uint8_t idBuf[3]; + uint8_t dataBuf[4]; + + SPIM_ReadJedecId(idBuf, sizeof (idBuf), u32NBit); + + if ((idBuf[0] != MFGID_WINBOND) || (idBuf[1] != 0x40) || (idBuf[2] != 0x16)) + { + SPIM_DBGMSG("SPIM_WinbondUnlock - Not W25Q32, do nothing.\n"); + return; + } + + SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit); + SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit); + SPIM_DBGMSG("Status Register: 0x%x - 0x%x\n", dataBuf[0], dataBuf[1]); + dataBuf[1] &= ~0x40; /* clear Status Register-1 SEC bit */ + + spim_set_write_enable(1, u32NBit); /* Write Enable. */ + SPIM_WriteStatusRegister2(dataBuf, sizeof (dataBuf), u32NBit); + spim_wait_write_done(u32NBit); + + SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit); + SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit); + SPIM_DBGMSG("Status Register (after unlock): 0x%x - 0x%x\n", dataBuf[0], dataBuf[1]); +} + +/** + * @brief Erase whole chip. + * @param u32NBit N-bit transmit/receive. + * @param isSync Block or not. + * @return None. + */ +void SPIM_ChipErase(uint32_t u32NBit, int isSync) +{ + uint8_t cmdBuf[] = { OPCODE_CHIP_ERASE }; /* 1-byte Chip Erase command. */ + + spim_set_write_enable(1, u32NBit); /* Write Enable. */ + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + + if (isSync) + { + spim_wait_write_done(u32NBit); + } +} + + +/** + * @brief Erase one block. + * @param u32Addr Block to erase which contains the u32Addr. + * @param is4ByteAddr 4-byte u32Address or not. + * @param u8ErsCmd Erase command. + * @param u32NBit N-bit transmit/receive. + * @param isSync Block or not. + * @return None. + */ +void SPIM_EraseBlock(uint32_t u32Addr, int is4ByteAddr, uint8_t u8ErsCmd, uint32_t u32NBit, int isSync) +{ + uint8_t cmdBuf[16]; + uint32_t buf_idx = 0UL; + + spim_set_write_enable(1, u32NBit); /* Write Enable. */ + + cmdBuf[buf_idx++] = u8ErsCmd; + + if (is4ByteAddr) + { + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 24); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr & 0xFFUL); + } + else + { + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr & 0xFFUL); + } + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, buf_idx); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + + if (isSync) + { + spim_wait_write_done(u32NBit); + } +} + + +/** @cond HIDDEN_SYMBOLS */ + +/** + * @brief Write data in the same page by I/O mode. + * @param u32Addr Start u32Address to write. + * @param is4ByteAddr 4-byte u32Address or not. + * @param u32NTx Number of bytes to write. + * @param pu8TxBuf Transmit buffer. + * @param wrCmd Write command. + * @param u32NBitCmd N-bit transmit command. + * @param u32NBitAddr N-bit transmit u32Address. + * @param u32NBitDat N-bit transmit/receive data. + * @param isSync Block or not. + * @return None. + */ +static void SPIM_WriteInPageDataByIo(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint8_t wrCmd, + uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat, int isSync) +{ + uint8_t cmdBuf[16]; + uint32_t buf_idx; + + spim_set_write_enable(1, u32NBitCmd); /* Write Enable. */ + + SPIM_SET_SS_EN(1); /* CS activated. */ + + SwitchNBitOutput(u32NBitCmd); + cmdBuf[0] = wrCmd; + spim_write(cmdBuf, 1UL); /* Write out command. */ + + buf_idx = 0UL; + if (is4ByteAddr) + { + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 24); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8); + cmdBuf[buf_idx++] = (uint8_t) u32Addr; + } + else + { + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8); + cmdBuf[buf_idx++] = (uint8_t) u32Addr; + } + + SwitchNBitOutput(u32NBitAddr); + spim_write(cmdBuf, buf_idx); /* Write out u32Address. */ + + SwitchNBitOutput(u32NBitDat); + spim_write(pu8TxBuf, u32NTx); /* Write out data. */ + + SPIM_SET_SS_EN(0); /* CS deactivated. */ + + if (isSync) + { + spim_wait_write_done(u32NBitCmd); + } +} + +/** + * @brief Write data in the same page by Page Write mode. + * @param u32Addr Start u32Address to write. + * @param is4ByteAddr 4-byte u32Address or not. + * @param u32NTx Number of bytes to write. + * @param pu8TxBuf Transmit buffer. + * @param wrCmd Write command. + * @param isSync Block or not. + * @return None. + */ +static void SPIM_WriteInPageDataByPageWrite(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, + uint8_t pu8TxBuf[], uint32_t wrCmd, int isSync) +{ + if ((wrCmd == CMD_QUAD_PAGE_PROGRAM_WINBOND) || + (wrCmd == CMD_QUAD_PAGE_PROGRAM_MXIC)) + { + SPIM_SetQuadEnable(1, 1UL); /* Set Quad Enable. */ + } + else if (wrCmd == CMD_QUAD_PAGE_PROGRAM_EON) + { + SPIM_SetQuadEnable(1, 1UL); /* Set Quad Enable. */ + spim_eon_set_qpi_mode(1); /* Enter QPI mode. */ + } + + SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_PAGEWRITE);/* Switch to Page Write mode. */ + SPIM_SET_SPIM_MODE(wrCmd); /* SPIM mode. */ + SPIM_SET_4BYTE_ADDR_EN(is4ByteAddr); /* Enable/disable 4-Byte Address. */ + + SPIM->SRAMADDR = (uint32_t) pu8TxBuf; /* SRAM u32Address. */ + SPIM->DMACNT = u32NTx; /* Transfer length. */ + SPIM->FADDR = u32Addr; /* Flash u32Address.*/ + SPIM_SET_GO(); /* Go. */ + + if (isSync) + { + SPIM_WAIT_FREE(); + } + + if (wrCmd == CMD_QUAD_PAGE_PROGRAM_EON) + { + spim_eon_set_qpi_mode(0); /* Exit QPI mode. */ + } +} + +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief Write data to SPI Flash by sending commands manually (I/O mode). + * @param u32Addr: Start u32Address to write. + * @param is4ByteAddr: 4-byte u32Address or not. + * @param u32NTx: Number of bytes to write. + * @param pu8TxBuf: Transmit buffer. + * @param wrCmd: Write command. + * @param u32NBitCmd: N-bit transmit command. + * @param u32NBitAddr: N-bit transmit u32Address. + * @param u32NBitDat: N-bit transmit/receive data. + * @return None. + */ +void SPIM_IO_Write(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint8_t wrCmd, + uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat) +{ + uint32_t pageOffset, toWr; + uint32_t buf_idx = 0UL; + + pageOffset = u32Addr % 256UL; + + if ((pageOffset + u32NTx) <= 256UL) /* Do all the bytes fit onto one page ? */ + { + SPIM_WriteInPageDataByIo(u32Addr, is4ByteAddr, u32NTx, &pu8TxBuf[buf_idx], + wrCmd, u32NBitCmd, u32NBitAddr, u32NBitDat, 1); + } + else + { + toWr = 256UL - pageOffset; /* Size of data remaining on the first page. */ + + SPIM_WriteInPageDataByIo(u32Addr, is4ByteAddr, toWr, &pu8TxBuf[buf_idx], + wrCmd, u32NBitCmd, u32NBitAddr, u32NBitDat, 1); + u32Addr += toWr; /* Advance indicator. */ + u32NTx -= toWr; + buf_idx += toWr; + + while (u32NTx) + { + toWr = 256UL; + if (toWr > u32NTx) + { + toWr = u32NTx; + } + + SPIM_WriteInPageDataByIo(u32Addr, is4ByteAddr, toWr, &pu8TxBuf[buf_idx], + wrCmd, u32NBitCmd, u32NBitAddr, u32NBitDat, 1); + u32Addr += toWr; /* Advance indicator. */ + u32NTx -= toWr; + buf_idx += toWr; + } + } +} + +/** + * @brief Read data from SPI Flash by sending commands manually (I/O mode). + * @param u32Addr Start u32Address to read. + * @param is4ByteAddr 4-byte u32Address or not. + * @param u32NRx Number of bytes to read. + * @param pu8RxBuf Receive buffer. + * @param rdCmd Read command. + * @param u32NBitCmd N-bit transmit command. + * @param u32NBitAddr N-bit transmit u32Address. + * @param u32NBitDat N-bit transmit/receive data. + * @param u32NDummy Number of dummy bytes following address. + * @return None. + */ +void SPIM_IO_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[], uint8_t rdCmd, + uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat, int u32NDummy) +{ + uint8_t cmdBuf[16]; + uint32_t buf_idx; + + SPIM_SET_SS_EN(1); /* CS activated. */ + + cmdBuf[0] = rdCmd; + SwitchNBitOutput(u32NBitCmd); + spim_write(cmdBuf, 1UL); /* Write out command. */ + + buf_idx = 0UL; + if (is4ByteAddr) + { + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 24); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8); + cmdBuf[buf_idx++] = (uint8_t) u32Addr; + } + else + { + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8); + cmdBuf[buf_idx++] = (uint8_t) u32Addr; + } + SwitchNBitOutput(u32NBitAddr); + spim_write(cmdBuf, buf_idx); /* Write out u32Address. */ + + buf_idx = 0UL; + while (u32NDummy --) + { + cmdBuf[buf_idx++] = 0x00U; + } + + /* Same bit mode as above. */ + spim_write(cmdBuf, buf_idx); /* Write out dummy bytes. */ + + SwitchNBitInput(u32NBitDat); + spim_read(pu8RxBuf, u32NRx); /* Read back data. */ + + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +/** + * @brief Write data to SPI Flash by Page Write mode. + * @param u32Addr Start address to write. + * @param is4ByteAddr 4-byte address or not. + * @param u32NTx Number of bytes to write. + * @param pu8TxBuf Transmit buffer. + * @param wrCmd Write command. + * @return None. + */ +void SPIM_DMA_Write(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint32_t wrCmd) +{ + uint32_t pageOffset, toWr; + uint32_t buf_idx = 0UL; + + pageOffset = u32Addr % 256UL; + + if ((pageOffset + u32NTx) <= 256UL) + { + /* Do all the bytes fit onto one page ? */ + SPIM_WriteInPageDataByPageWrite(u32Addr, is4ByteAddr, u32NTx, pu8TxBuf, wrCmd, 1); + } + else + { + toWr = 256UL - pageOffset; /* Size of data remaining on the first page. */ + + SPIM_WriteInPageDataByPageWrite(u32Addr, is4ByteAddr, toWr, &pu8TxBuf[buf_idx], wrCmd, 1); + + u32Addr += toWr; /* Advance indicator. */ + u32NTx -= toWr; + buf_idx += toWr; + + while (u32NTx) + { + toWr = 256UL; + if (toWr > u32NTx) + { + toWr = u32NTx; + } + + SPIM_WriteInPageDataByPageWrite(u32Addr, is4ByteAddr, toWr, &pu8TxBuf[buf_idx], wrCmd, 1); + + u32Addr += toWr; /* Advance indicator. */ + u32NTx -= toWr; + buf_idx += toWr; + } + } +} + +/** + * @brief Read data from SPI Flash by Page Read mode. + * @param u32Addr Start address to read. + * @param is4ByteAddr 4-byte u32Address or not. + * @param u32NRx Number of bytes to read. + * @param pu8RxBuf Receive buffer. + * @param u32RdCmd Read command. + * @param isSync Block or not. + * @return None. + */ +void SPIM_DMA_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[], + uint32_t u32RdCmd, int isSync) +{ + SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_PAGEREAD); /* Switch to Page Read mode. */ + SPIM_SET_SPIM_MODE(u32RdCmd); /* SPIM mode. */ + SPIM_SET_4BYTE_ADDR_EN(is4ByteAddr); /* Enable/disable 4-Byte Address. */ + + SPIM->SRAMADDR = (uint32_t) pu8RxBuf; /* SRAM u32Address. */ + SPIM->DMACNT = u32NRx; /* Transfer length. */ + SPIM->FADDR = u32Addr; /* Flash u32Address.*/ + SPIM_SET_GO(); /* Go. */ + + if (isSync) + { + SPIM_WAIT_FREE(); /* Wait for DMA done. */ + } +} + +/** + * @brief Enter Direct Map mode. + * @param is4ByteAddr 4-byte u32Address or not. + * @param u32RdCmd Read command. + * @param u32IdleIntvl Idle interval. + * @return None. + */ +void SPIM_EnterDirectMapMode(int is4ByteAddr, uint32_t u32RdCmd, uint32_t u32IdleIntvl) +{ + SPIM_SET_4BYTE_ADDR_EN(is4ByteAddr); /* Enable/disable 4-byte u32Address. */ + SPIM_SET_SPIM_MODE(u32RdCmd); /* SPIM mode. */ + SPIM_SET_IDL_INTVL(u32IdleIntvl); /* Idle interval. */ + SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_DIRECTMAP); /* Switch to Direct Map mode. */ +} + +/** + * @brief Exit Direct Map mode. + * @return None. + */ +void SPIM_ExitDirectMapMode(void) +{ + SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO); /* Switch back to Normal mode. */ +} + + +/*@}*/ /* end of group SPIM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SPIM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_sys.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_sys.c new file mode 100644 index 0000000000000000000000000000000000000000..e5e12896e7c312575fb835a67cf9101f7ed07fd9 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_sys.c @@ -0,0 +1,284 @@ +/**************************************************************************//** + * @file sys.c + * @version V1.00 + * @brief M480 series SYS driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include "NuMicro.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SYS_Driver SYS Driver + @{ +*/ + + +/** @addtogroup SYS_EXPORTED_FUNCTIONS SYS Exported Functions + @{ +*/ + +/** + * @brief Clear reset source + * @param[in] u32Src is system reset source. Including : + * - \ref SYS_RSTSTS_CPULKRF_Msk + * - \ref SYS_RSTSTS_CPURF_Msk + * - \ref SYS_RSTSTS_SYSRF_Msk + * - \ref SYS_RSTSTS_BODRF_Msk + * - \ref SYS_RSTSTS_LVRF_Msk + * - \ref SYS_RSTSTS_WDTRF_Msk + * - \ref SYS_RSTSTS_PINRF_Msk + * - \ref SYS_RSTSTS_PORF_Msk + * @return None + * @details This function clear the selected system reset source. + */ +void SYS_ClearResetSrc(uint32_t u32Src) +{ + SYS->RSTSTS |= u32Src; +} + +/** + * @brief Get Brown-out detector output status + * @param None + * @retval 0 System voltage is higher than BODVL setting or BODEN is 0. + * @retval 1 System voltage is lower than BODVL setting. + * @details This function get Brown-out detector output status. + */ +uint32_t SYS_GetBODStatus(void) +{ + return ((SYS->BODCTL & SYS_BODCTL_BODOUT_Msk) >> SYS_BODCTL_BODOUT_Pos); +} + +/** + * @brief Get reset status register value + * @param None + * @return Reset source + * @details This function get the system reset status register value. + */ +uint32_t SYS_GetResetSrc(void) +{ + return (SYS->RSTSTS); +} + +/** + * @brief Check if register is locked nor not + * @param None + * @retval 0 Write-protection function is disabled. + * 1 Write-protection function is enabled. + * @details This function check register write-protection bit setting. + */ +uint32_t SYS_IsRegLocked(void) +{ + return SYS->REGLCTL & 1UL ? 0UL : 1UL; +} + +/** + * @brief Get product ID + * @param None + * @return Product ID + * @details This function get product ID. + */ +uint32_t SYS_ReadPDID(void) +{ + return SYS->PDID; +} + +/** + * @brief Reset chip with chip reset + * @param None + * @return None + * @details This function reset chip with chip reset. + * The register write-protection function should be disabled before using this function. + */ +void SYS_ResetChip(void) +{ + SYS->IPRST0 |= SYS_IPRST0_CHIPRST_Msk; +} + +/** + * @brief Reset chip with CPU reset + * @param None + * @return None + * @details This function reset CPU with CPU reset. + * The register write-protection function should be disabled before using this function. + */ +void SYS_ResetCPU(void) +{ + SYS->IPRST0 |= SYS_IPRST0_CPURST_Msk; +} + +/** + * @brief Reset selected module + * @param[in] u32ModuleIndex is module index. Including : + * - \ref PDMA_RST + * - \ref EBI_RST + * - \ref EMAC_RST + * - \ref SDH0_RST + * - \ref CRC_RST + * - \ref CCAP_RST + * - \ref HSUSBD_RST + * - \ref CRPT_RST + * - \ref SPIM_RST + * - \ref USBH_RST + * - \ref SDH1_RST + * - \ref GPIO_RST + * - \ref TMR0_RST + * - \ref TMR1_RST + * - \ref TMR2_RST + * - \ref TMR3_RST + * - \ref ACMP01_RST + * - \ref I2C0_RST + * - \ref I2C1_RST + * - \ref I2C2_RST + * - \ref QSPI0_RST + * - \ref SPI0_RST + * - \ref SPI1_RST + * - \ref SPI2_RST + * - \ref UART0_RST + * - \ref UART1_RST + * - \ref UART2_RST + * - \ref UART3_RST + * - \ref UART4_RST + * - \ref UART5_RST + * - \ref UART6_RST + * - \ref UART7_RST + * - \ref CAN0_RST + * - \ref CAN1_RST + * - \ref OTG_RST + * - \ref USBD_RST + * - \ref EADC_RST + * - \ref I2S0_RST + * - \ref HSOTG_RST + * - \ref TRNG_RST + * - \ref SC0_RST + * - \ref SC1_RST + * - \ref SC2_RST + * - \ref QSPI1_RST + * - \ref SPI3_RST + * - \ref USCI0_RST + * - \ref USCI1_RST + * - \ref DAC_RST + * - \ref EPWM0_RST + * - \ref EPWM1_RST + * - \ref BPWM0_RST + * - \ref BPWM1_RST + * - \ref QEI0_RST + * - \ref QEI1_RST + * - \ref ECAP0_RST + * - \ref ECAP1_RST + * - \ref CAN2_RST + * - \ref OPA_RST + * - \ref EADC1_RST + * @return None + * @details This function reset selected module. + */ +void SYS_ResetModule(uint32_t u32ModuleIndex) +{ + uint32_t u32tmpVal = 0UL, u32tmpAddr = 0UL; + + /* Generate reset signal to the corresponding module */ + u32tmpVal = (1UL << (u32ModuleIndex & 0x00ffffffUL)); + u32tmpAddr = (uint32_t)&SYS->IPRST0 + ((u32ModuleIndex >> 24UL)); + *(uint32_t *)u32tmpAddr |= u32tmpVal; + + /* Release corresponding module from reset state */ + u32tmpVal = ~(1UL << (u32ModuleIndex & 0x00ffffffUL)); + *(uint32_t *)u32tmpAddr &= u32tmpVal; +} + +/** + * @brief Enable and configure Brown-out detector function + * @param[in] i32Mode is reset or interrupt mode. Including : + * - \ref SYS_BODCTL_BOD_RST_EN + * - \ref SYS_BODCTL_BOD_INTERRUPT_EN + * @param[in] u32BODLevel is Brown-out voltage level. Including : + * - \ref SYS_BODCTL_BODVL_3_0V + * - \ref SYS_BODCTL_BODVL_2_8V + * - \ref SYS_BODCTL_BODVL_2_6V + * - \ref SYS_BODCTL_BODVL_2_4V + * - \ref SYS_BODCTL_BODVL_2_2V + * - \ref SYS_BODCTL_BODVL_2_0V + * - \ref SYS_BODCTL_BODVL_1_8V + * - \ref SYS_BODCTL_BODVL_1_6V + * @return None + * @details This function configure Brown-out detector reset or interrupt mode, enable Brown-out function and set Brown-out voltage level. + * The register write-protection function should be disabled before using this function. + */ +void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel) +{ + /* Enable Brown-out Detector function */ + SYS->BODCTL |= SYS_BODCTL_BODEN_Msk; + + /* Enable Brown-out interrupt or reset function */ + SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODRSTEN_Msk) | (uint32_t)i32Mode; + + /* Select Brown-out Detector threshold voltage */ + SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | u32BODLevel; +} + +/** + * @brief Disable Brown-out detector function + * @param None + * @return None + * @details This function disable Brown-out detector function. + * The register write-protection function should be disabled before using this function. + */ +void SYS_DisableBOD(void) +{ + SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk; +} + +/** + * @brief Set Power Level + * @param[in] u32PowerLevel is power level setting. Including : + * - \ref SYS_PLCTL_PLSEL_PL0 + * - \ref SYS_PLCTL_PLSEL_PL1 + * @return None + * @details This function select power level. + * The register write-protection function should be disabled before using this function. + */ +void SYS_SetPowerLevel(uint32_t u32PowerLevel) +{ + /* Set power voltage level */ + SYS->PLCTL = (SYS->PLCTL & (~SYS_PLCTL_PLSEL_Msk)) | (u32PowerLevel); +} + +/** + * @brief Set Reference Voltage + * @param[in] u32VRefCTL is reference voltage setting. Including : + * - \ref SYS_VREFCTL_VREF_PIN + * - \ref SYS_VREFCTL_VREF_1_6V + * - \ref SYS_VREFCTL_VREF_2_0V + * - \ref SYS_VREFCTL_VREF_2_5V + * - \ref SYS_VREFCTL_VREF_3_0V + * - \ref SYS_VREFCTL_VREF_AVDD + * @return None + * @details This function select reference voltage. + * The register write-protection function should be disabled before using this function. + */ +void SYS_SetVRef(uint32_t u32VRefCTL) +{ + /* Set reference voltage */ + SYS->VREFCTL = (SYS->VREFCTL & (~SYS_VREFCTL_VREFCTL_Msk)) | (u32VRefCTL); +} + +/*@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SYS_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_timer.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_timer.c new file mode 100644 index 0000000000000000000000000000000000000000..1987445777b30c80c5b209cfd220f4a1b66200de --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_timer.c @@ -0,0 +1,353 @@ +/**************************************************************************//** + * @file timer.c + * @brief M480 Timer Controller(Timer) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup TIMER_Driver TIMER Driver + @{ +*/ + +/** @addtogroup TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions + @{ +*/ + +/** + * @brief Open Timer with Operate Mode and Frequency + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Mode Operation mode. Possible options are + * - \ref TIMER_ONESHOT_MODE + * - \ref TIMER_PERIODIC_MODE + * - \ref TIMER_TOGGLE_MODE + * - \ref TIMER_CONTINUOUS_MODE + * @param[in] u32Freq Target working frequency + * + * @return Real timer working frequency + * + * @details This API is used to configure timer to operate in specified mode and frequency. + * If timer cannot work in target frequency, a closest frequency will be chose and returned. + * @note After calling this API, Timer is \b NOT running yet. But could start timer running be calling + * \ref TIMER_Start macro or program registers directly. + */ +uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq) +{ + uint32_t u32Clk = TIMER_GetModuleClock(timer); + uint32_t u32Cmpr = 0UL, u32Prescale = 0UL; + + /* Fastest possible timer working freq is (u32Clk / 2). While cmpr = 2, prescaler = 0. */ + if(u32Freq > (u32Clk / 2UL)) + { + u32Cmpr = 2UL; + } + else + { + u32Cmpr = u32Clk / u32Freq; + u32Prescale = (u32Cmpr >> 24); /* for 24 bits CMPDAT */ + if (u32Prescale > 0UL) + u32Cmpr = u32Cmpr / (u32Prescale + 1UL); + } + + timer->CTL = u32Mode | u32Prescale; + timer->CMP = u32Cmpr; + + return(u32Clk / (u32Cmpr * (u32Prescale + 1UL))); +} + +/** + * @brief Stop Timer Counting + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This API stops timer counting and disable all timer interrupt function. + */ +void TIMER_Close(TIMER_T *timer) +{ + timer->CTL = 0UL; + timer->EXTCTL = 0UL; +} + +/** + * @brief Create a specify Delay Time + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Usec Delay period in micro seconds. Valid values are between 100~1000000 (100 micro second ~ 1 second). + * + * @return None + * + * @details This API is used to create a delay loop for u32usec micro seconds by using timer one-shot mode. + * @note This API overwrites the register setting of the timer used to count the delay time. + * @note This API use polling mode. So there is no need to enable interrupt for the timer module used to generate delay. + */ +void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec) +{ + uint32_t u32Clk = TIMER_GetModuleClock(timer); + uint32_t u32Prescale = 0UL, delay = (SystemCoreClock / u32Clk) + 1UL; + uint32_t u32Cmpr, u32NsecPerTick; + + /* Clear current timer configuration */ + timer->CTL = 0UL; + timer->EXTCTL = 0UL; + + if(u32Clk <= 1000000UL) /* min delay is 1000 us if timer clock source is <= 1 MHz */ + { + if(u32Usec < 1000UL) + { + u32Usec = 1000UL; + } + if(u32Usec > 1000000UL) + { + u32Usec = 1000000UL; + } + } + else + { + if(u32Usec < 100UL) + { + u32Usec = 100UL; + } + if(u32Usec > 1000000UL) + { + u32Usec = 1000000UL; + } + } + + if(u32Clk <= 1000000UL) + { + u32Prescale = 0UL; + u32NsecPerTick = 1000000000UL / u32Clk; + u32Cmpr = (u32Usec * 1000UL) / u32NsecPerTick; + } + else + { + u32Cmpr = u32Usec * (u32Clk / 1000000UL); + u32Prescale = (u32Cmpr >> 24); /* for 24 bits CMPDAT */ + if (u32Prescale > 0UL) + u32Cmpr = u32Cmpr / (u32Prescale + 1UL); + } + + timer->CMP = u32Cmpr; + timer->CTL = TIMER_CTL_CNTEN_Msk | TIMER_ONESHOT_MODE | u32Prescale; + + /* When system clock is faster than timer clock, it is possible timer active bit cannot set in time while we check it. + And the while loop below return immediately, so put a tiny delay here allowing timer start counting and raise active flag. */ + for(; delay > 0UL; delay--) + { + __NOP(); + } + + while(timer->CTL & TIMER_CTL_ACTSTS_Msk) + { + ; + } +} + +/** + * @brief Enable Timer Capture Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32CapMode Timer capture mode. Could be + * - \ref TIMER_CAPTURE_FREE_COUNTING_MODE + * - \ref TIMER_CAPTURE_COUNTER_RESET_MODE + * @param[in] u32Edge Timer capture trigger edge. Possible values are + * - \ref TIMER_CAPTURE_EVENT_FALLING + * - \ref TIMER_CAPTURE_EVENT_RISING + * - \ref TIMER_CAPTURE_EVENT_FALLING_RISING + * - \ref TIMER_CAPTURE_EVENT_RISING_FALLING + * + * @return None + * + * @details This API is used to enable timer capture function with specify capture trigger edge \n + * to get current counter value or reset counter value to 0. + * @note Timer frequency should be configured separately by using \ref TIMER_Open API, or program registers directly. + */ +void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge) +{ + timer->EXTCTL = (timer->EXTCTL & ~(TIMER_EXTCTL_CAPFUNCS_Msk | TIMER_EXTCTL_CAPEDGE_Msk)) | + u32CapMode | u32Edge | TIMER_EXTCTL_CAPEN_Msk; +} + +/** + * @brief Disable Timer Capture Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This API is used to disable the timer capture function. + */ +void TIMER_DisableCapture(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CAPEN_Msk; +} + +/** + * @brief Enable Timer Counter Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Edge Detection edge of counter pin. Could be ether + * - \ref TIMER_COUNTER_EVENT_FALLING, or + * - \ref TIMER_COUNTER_EVENT_RISING + * + * @return None + * + * @details This function is used to enable the timer counter function with specify detection edge. + * @note Timer compare value should be configured separately by using \ref TIMER_SET_CMP_VALUE macro or program registers directly. + * @note While using event counter function, \ref TIMER_TOGGLE_MODE cannot set as timer operation mode. + */ +void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge) +{ + timer->EXTCTL = (timer->EXTCTL & ~TIMER_EXTCTL_CNTPHASE_Msk) | u32Edge; + timer->CTL |= TIMER_CTL_EXTCNTEN_Msk; +} + +/** + * @brief Disable Timer Counter Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This API is used to disable the timer event counter function. + */ +void TIMER_DisableEventCounter(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_EXTCNTEN_Msk; +} + +/** + * @brief Get Timer Clock Frequency + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return Timer clock frequency + * + * @details This API is used to get the timer clock frequency. + * @note This API cannot return correct clock rate if timer source is from external clock input. + */ +uint32_t TIMER_GetModuleClock(TIMER_T *timer) +{ + uint32_t u32Src, u32Clk; + const uint32_t au32Clk[] = {__HXT, __LXT, 0UL, 0UL, 0UL, __LIRC, 0UL, __HIRC}; + + if(timer == TIMER0) + { + u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR0SEL_Msk) >> CLK_CLKSEL1_TMR0SEL_Pos; + } + else if(timer == TIMER1) + { + u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR1SEL_Msk) >> CLK_CLKSEL1_TMR1SEL_Pos; + } + else if(timer == TIMER2) + { + u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR2SEL_Msk) >> CLK_CLKSEL1_TMR2SEL_Pos; + } + else /* Timer 3 */ + { + u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR3SEL_Msk) >> CLK_CLKSEL1_TMR3SEL_Pos; + } + + if(u32Src == 2UL) + { + if((timer == TIMER0) || (timer == TIMER1)) + { + u32Clk = CLK_GetPCLK0Freq(); + } + else + { + u32Clk = CLK_GetPCLK1Freq(); + } + } + else + { + u32Clk = au32Clk[u32Src]; + } + + return u32Clk; +} + + + +/** + * @brief This function is used to enable the Timer frequency counter function + * @param[in] timer The base address of Timer module. Can be \ref TIMER0 or \ref TIMER2 + * @param[in] u32DropCount This parameter has no effect in M480 series BSP + * @param[in] u32Timeout This parameter has no effect in M480 series BSP + * @param[in] u32EnableInt Enable interrupt assertion after capture complete or not. Valid values are TRUE and FALSE + * @return None + * @details This function is used to calculate input event frequency. After enable + * this function, a pair of timers, TIMER0 and TIMER1, or TIMER2 and TIMER3 + * will be configured for this function. The mode used to calculate input + * event frequency is mentioned as "Inter Timer Trigger Mode" in Technical + * Reference Manual + */ +void TIMER_EnableFreqCounter(TIMER_T *timer, + uint32_t u32DropCount, + uint32_t u32Timeout, + uint32_t u32EnableInt) +{ + TIMER_T *t; /* store the timer base to configure compare value */ + + t = (timer == TIMER0) ? TIMER1 : TIMER3; + + t->CMP = 0xFFFFFFUL; + t->EXTCTL = u32EnableInt ? TIMER_EXTCTL_CAPIEN_Msk : 0UL; + timer->CTL = TIMER_CTL_INTRGEN_Msk | TIMER_CTL_CNTEN_Msk; + + return; +} +/** + * @brief This function is used to disable the Timer frequency counter function. + * @param[in] timer The base address of Timer module + * @return None + */ +void TIMER_DisableFreqCounter(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_INTRGEN_Msk; +} + + +/** + * @brief This function is used to select the interrupt source used to trigger other modules. + * @param[in] timer The base address of Timer module + * @param[in] u32Src Selects the interrupt source to trigger other modules. Could be: + * - \ref TIMER_TRGSRC_TIMEOUT_EVENT + * - \ref TIMER_TRGSRC_CAPTURE_EVENT + * @return None + */ +void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src) +{ + timer->TRGCTL = (timer->TRGCTL & ~TIMER_TRGCTL_TRGSSEL_Msk) | u32Src; +} + +/** + * @brief This function is used to set modules trigger by timer interrupt + * @param[in] timer The base address of Timer module + * @param[in] u32Mask The mask of modules (EPWM, EADC, DAC and PDMA) trigger by timer. Is the combination of + * - \ref TIMER_TRG_TO_EPWM, + * - \ref TIMER_TRG_TO_EADC, + * - \ref TIMER_TRG_TO_DAC, and + * - \ref TIMER_TRG_TO_PDMA + * @return None + */ +void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask) +{ + timer->TRGCTL = (timer->TRGCTL & ~(TIMER_TRGCTL_TRGEPWM_Msk | TIMER_TRGCTL_TRGDAC_Msk | TIMER_TRGCTL_TRGEADC_Msk | TIMER_TRGCTL_TRGPDMA_Msk)) | u32Mask; +} + +/*@}*/ /* end of group TIMER_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group TIMER_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_timer_pwm.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_timer_pwm.c new file mode 100644 index 0000000000000000000000000000000000000000..15d180f2658c66487229db908e7401fdd5cb1436 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_timer_pwm.c @@ -0,0 +1,443 @@ +/**************************************************************************//** + * @file timer_pwm.c + * @brief M480 Timer PWM Controller(Timer PWM) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup TIMER_PWM_Driver TIMER PWM Driver + @{ +*/ + +/** @addtogroup TIMER_PWM_EXPORTED_FUNCTIONS TIMER PWM Exported Functions + @{ +*/ + +/** + * @brief Set PWM Counter Clock Source + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32CntClkSrc PWM counter clock source, could be one of following source + * - \ref TPWM_CNTR_CLKSRC_TMR_CLK + * - \ref TPWM_CNTR_CLKSRC_TIMER0_INT + * - \ref TPWM_CNTR_CLKSRC_TIMER1_INT + * - \ref TPWM_CNTR_CLKSRC_TIMER2_INT + * - \ref TPWM_CNTR_CLKSRC_TIMER3_INT + * + * @return None + * + * @details This function is used to set PWM counter clock source. + */ +void TPWM_SetCounterClockSource(TIMER_T *timer, uint32_t u32CntClkSrc) +{ + (timer)->PWMCLKSRC = ((timer)->PWMCLKSRC & ~TIMER_PWMCLKSRC_CLKSRC_Msk) | u32CntClkSrc; +} + +/** + * @brief Configure PWM Output Frequency and Duty Cycle + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Frequency Target generator frequency. + * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0~100. 10 means 10%, 20 means 20%... + * + * @return Nearest frequency clock in nano second + * + * @details This API is used to configure PWM output frequency and duty cycle in up count type and auto-reload operation mode. + * @note This API is only available if Timer PWM counter clock source is from TMRx_CLK. + */ +uint32_t TPWM_ConfigOutputFreqAndDuty(TIMER_T *timer, uint32_t u32Frequency, uint32_t u32DutyCycle) +{ + uint32_t u32PWMClockFreq, u32TargetFreq; + uint32_t u32Prescaler = 0x1000UL, u32Period, u32CMP; + + if((timer == TIMER0) || (timer == TIMER1)) + { + u32PWMClockFreq = CLK_GetPCLK0Freq(); + } + else + { + u32PWMClockFreq = CLK_GetPCLK1Freq(); + } + + /* Calculate u16PERIOD and u16PSC */ + for(u32Prescaler = 1UL; u32Prescaler <= 0x1000UL; u32Prescaler++) + { + u32Period = (u32PWMClockFreq / u32Prescaler) / u32Frequency; + + /* If target u32Period is larger than 0x10000, need to use a larger prescaler */ + if(u32Period <= 0x10000UL) + { + break; + } + } + /* Store return value here 'cos we're gonna change u32Prescaler & u32Period to the real value to fill into register */ + u32TargetFreq = (u32PWMClockFreq / u32Prescaler) / u32Period; + + /* Set PWM to up count type */ + timer->PWMCTL = (timer->PWMCTL & ~TIMER_PWMCTL_CNTTYPE_Msk) | (TPWM_UP_COUNT << TIMER_PWMCTL_CNTTYPE_Pos); + + /* Set PWM to auto-reload mode */ + timer->PWMCTL = (timer->PWMCTL & ~TIMER_PWMCTL_CNTMODE_Msk) | TPWM_AUTO_RELOAD_MODE; + + /* Convert to real register value */ + TPWM_SET_PRESCALER(timer, (u32Prescaler - 1UL)); + + TPWM_SET_PERIOD(timer, (u32Period - 1UL)); + if(u32DutyCycle) + { + u32CMP = (u32DutyCycle * u32Period) / 100UL; + } + else + { + u32CMP = 0UL; + } + + TPWM_SET_CMPDAT(timer, u32CMP); + + return (u32TargetFreq); +} + +/** + * @brief Enable Dead-Time Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32DTCount Dead-Time duration in PWM clock count, valid values are between 0x0~0xFFF, but 0x0 means there is no Dead-Time insertion. + * + * @return None + * + * @details This function is used to enable Dead-Time function and counter source is the same as Timer PWM clock source. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_EnableDeadTime(TIMER_T *timer, uint32_t u32DTCount) +{ + timer->PWMDTCTL = TIMER_PWMDTCTL_DTEN_Msk | u32DTCount; +} + +/** + * @brief Enable Dead-Time Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32DTCount Dead-Time duration in PWM clock count, valid values are between 0x0~0xFFF, but 0x0 means there is no Dead-Time insertion. + * + * @return None + * + * @details This function is used to enable Dead-Time function and counter source is the Timer PWM clock source with prescale. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_EnableDeadTimeWithPrescale(TIMER_T *timer, uint32_t u32DTCount) +{ + timer->PWMDTCTL = TIMER_PWMDTCTL_DTCKSEL_Msk | TIMER_PWMDTCTL_DTEN_Msk | u32DTCount; +} + +/** + * @brief Disable Dead-Time Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable Dead-time of selected channel. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_DisableDeadTime(TIMER_T *timer) +{ + timer->PWMDTCTL = 0x0UL; +} + +/** + * @brief Enable PWM Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable PWM generator and start counter counting. + */ +void TPWM_EnableCounter(TIMER_T *timer) +{ + timer->PWMCTL |= TIMER_PWMCTL_CNTEN_Msk; +} + +/** + * @brief Disable PWM Generator + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable PWM counter immediately by clear CNTEN (TIMERx_PWMCTL[0]) bit. + */ +void TPWM_DisableCounter(TIMER_T *timer) +{ + timer->PWMCTL &= ~TIMER_PWMCTL_CNTEN_Msk; +} + +/** + * @brief Enable Trigger ADC + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Condition The condition to trigger ADC. It could be one of following conditions: + * - \ref TPWM_TRIGGER_ADC_AT_ZERO_POINT + * - \ref TPWM_TRIGGER_ADC_AT_PERIOD_POINT + * - \ref TPWM_TRIGGER_ADC_AT_ZERO_OR_PERIOD_POINT + * - \ref TPWM_TRIGGER_ADC_AT_COMPARE_UP_COUNT_POINT + * - \ref TPWM_TRIGGER_ADC_AT_COMPARE_DOWN_COUNT_POINT + * + * @return None + * + * @details This function is used to enable specified counter compare event to trigger ADC. + */ +void TPWM_EnableTriggerADC(TIMER_T *timer, uint32_t u32Condition) +{ + timer->PWMEADCTS = TIMER_PWMEADCTS_TRGEN_Msk | u32Condition; +} + +/** + * @brief Disable Trigger ADC + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable counter compare event to trigger ADC. + */ +void TPWM_DisableTriggerADC(TIMER_T *timer) +{ + timer->PWMEADCTS = 0x0UL; +} + +/** + * @brief Enable Fault Brake Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32CH0Level PWMx_CH0 output level while fault brake event occurs. Valid value is one of following setting + * - \ref TPWM_OUTPUT_TOGGLE + * - \ref TPWM_OUTPUT_NOTHING + * - \ref TPWM_OUTPUT_LOW + * - \ref TPWM_OUTPUT_HIGH + * @param[in] u32CH1Level PWMx_CH1 output level while fault brake event occurs. Valid value is one of following setting + * - \ref TPWM_OUTPUT_TOGGLE + * - \ref TPWM_OUTPUT_NOTHING + * - \ref TPWM_OUTPUT_LOW + * - \ref TPWM_OUTPUT_HIGH + * @param[in] u32BrakeSource Fault brake source, combination of following source + * - \ref TPWM_BRAKE_SOURCE_EDGE_ACMP0 + * - \ref TPWM_BRAKE_SOURCE_EDGE_ACMP1 + * - \ref TPWM_BRAKE_SOURCE_EDGE_BKPIN + * - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_CSS + * - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_BOD + * - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_COR + * - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_RAM + * - \ref TPWM_BRAKE_SOURCE_LEVEL_ACMP0 + * - \ref TPWM_BRAKE_SOURCE_LEVEL_ACMP1 + * - \ref TPWM_BRAKE_SOURCE_LEVEL_BKPIN + * - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_CSS + * - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_BOD + * - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_COR + * - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_RAM + * + * @return None + * + * @details This function is used to enable fault brake function. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_EnableFaultBrake(TIMER_T *timer, uint32_t u32CH0Level, uint32_t u32CH1Level, uint32_t u32BrakeSource) +{ + timer->PWMFAILBRK |= ((u32BrakeSource >> 16) & 0xFUL); + timer->PWMBRKCTL = (timer->PWMBRKCTL & ~(TIMER_PWMBRKCTL_BRKAEVEN_Msk | TIMER_PWMBRKCTL_BRKAODD_Msk)) | + (u32BrakeSource & 0xFFFFUL) | (u32CH0Level << TIMER_PWMBRKCTL_BRKAEVEN_Pos) | (u32CH1Level << TIMER_PWMBRKCTL_BRKAODD_Pos); +} + +/** + * @brief Enable Fault Brake Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32IntSource Interrupt source, could be one of following source + * - \ref TPWM_BRAKE_EDGE + * - \ref TPWM_BRAKE_LEVEL + * + * @return None + * + * @details This function is used to enable fault brake interrupt. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_EnableFaultBrakeInt(TIMER_T *timer, uint32_t u32IntSource) +{ + timer->PWMINTEN1 |= u32IntSource; +} + +/** + * @brief Disable Fault Brake Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32IntSource Interrupt source, could be one of following source + * - \ref TPWM_BRAKE_EDGE + * - \ref TPWM_BRAKE_LEVEL + * + * @return None + * + * @details This function is used to disable fault brake interrupt. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_DisableFaultBrakeInt(TIMER_T *timer, uint32_t u32IntSource) +{ + timer->PWMINTEN1 &= ~u32IntSource; +} + +/** + * @brief Indicate Fault Brake Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32IntSource Interrupt source, could be one of following source + * - \ref TPWM_BRAKE_EDGE + * - \ref TPWM_BRAKE_LEVEL + * + * @return Fault brake interrupt flag of specified source + * @retval 0 Fault brake interrupt did not occurred + * @retval 1 Fault brake interrupt occurred + * + * @details This function is used to indicate fault brake interrupt flag occurred or not of selected source. + */ +uint32_t TPWM_GetFaultBrakeIntFlag(TIMER_T *timer, uint32_t u32IntSource) +{ + return ((timer->PWMINTSTS1 & (0x3UL << u32IntSource))? 1UL : 0UL); +} + +/** + * @brief Clear Fault Brake Interrupt Flags + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32IntSource Interrupt source, could be one of following source + * - \ref TPWM_BRAKE_EDGE + * - \ref TPWM_BRAKE_LEVEL + * + * @return None + * + * @details This function is used to clear fault brake interrupt flags of selected source. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_ClearFaultBrakeIntFlag(TIMER_T *timer, uint32_t u32IntSource) +{ + timer->PWMINTSTS1 = (0x3UL << u32IntSource); +} + +/** + * @brief Enable load mode of selected channel + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32LoadMode Timer PWM counter loading mode, could be one of following mode + * - \ref TPWM_LOAD_MODE_PERIOD + * - \ref TPWM_LOAD_MODE_IMMEDIATE + * - \ref TPWM_LOAD_MODE_CENTER + * + * @return None + * + * @details This function is used to enable load mode of selected channel. + * @note The default loading mode is period loading mode. + */ +void TPWM_SetLoadMode(TIMER_T *timer, uint32_t u32LoadMode) +{ + timer->PWMCTL = (timer->PWMCTL & ~(TIMER_PWMCTL_IMMLDEN_Msk | TIMER_PWMCTL_CTRLD_Msk)) | u32LoadMode; +} + +/** + * @brief Enable brake pin noise filter function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32BrakePinSrc The external brake pin source, could be one of following source + * - \ref TPWM_TM_BRAKE0 + * - \ref TPWM_TM_BRAKE1 + * - \ref TPWM_TM_BRAKE2 + * - \ref TPWM_TM_BRAKE3 + * @param[in] u32DebounceCnt This value controls the real debounce sample time. + * The target debounce sample time is (debounce sample clock period) * (u32DebounceCnt). + * @param[in] u32ClkSrcSel Brake pin detector debounce clock source, could be one of following source + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_1 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_2 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_4 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_8 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_16 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_32 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_64 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_128 + * + * @return None + * + * @details This function is used to enable external brake pin detector noise filter function. + */ +void TPWM_EnableBrakePinDebounce(TIMER_T *timer, uint32_t u32BrakePinSrc, uint32_t u32DebounceCnt, uint32_t u32ClkSrcSel) +{ + timer->PWMBNF = (timer->PWMBNF & ~(TIMER_PWMBNF_BKPINSRC_Msk | TIMER_PWMBNF_BRKFCNT_Msk | TIMER_PWMBNF_BRKNFSEL_Msk)) | + (u32BrakePinSrc << TIMER_PWMBNF_BKPINSRC_Pos) | + (u32DebounceCnt << TIMER_PWMBNF_BRKFCNT_Pos) | + (u32ClkSrcSel << TIMER_PWMBNF_BRKNFSEL_Pos) | TIMER_PWMBNF_BRKNFEN_Msk; +} + +/** + * @brief Disable brake pin noise filter function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable external brake pin detector noise filter function. + */ +void TPWM_DisableBrakePinDebounce(TIMER_T *timer) +{ + timer->PWMBNF &= ~TIMER_PWMBNF_BRKNFEN_Msk; +} + + +/** + * @brief Enable brake pin inverse function + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @return None + * @details This function is used to enable PWM brake pin inverse function. + */ +void TPWM_EnableBrakePinInverse(TIMER_T *timer) +{ + timer->PWMBNF |= TIMER_PWMBNF_BRKPINV_Msk; +} + +/** + * @brief Disable brake pin inverse function + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @return None + * @details This function is used to disable PWM brake pin inverse function. + */ +void TPWM_DisableBrakePinInverse(TIMER_T *timer) +{ + timer->PWMBNF &= ~TIMER_PWMBNF_BRKPINV_Msk; +} + +/** + * @brief Set brake pin source + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32BrakePinNum Brake pin selection. One of the following: + * - \ref TPWM_TM_BRAKE0 + * - \ref TPWM_TM_BRAKE1 + * - \ref TPWM_TM_BRAKE2 + * - \ref TPWM_TM_BRAKE3 + * @return None + * @details This function is used to set PWM brake pin source. + */ +void TPWM_SetBrakePinSource(TIMER_T *timer, uint32_t u32BrakePinNum) +{ + timer->PWMBNF = (((timer)->PWMBNF & ~TIMER_PWMBNF_BKPINSRC_Msk) | (u32BrakePinNum << TIMER_PWMBNF_BKPINSRC_Pos)); +} + + +/*@}*/ /* end of group TIMER_PWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group TIMER_PWM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_trng.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_trng.c new file mode 100644 index 0000000000000000000000000000000000000000..98449d1a85d86905396bfc7f35110067afc95c99 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_trng.c @@ -0,0 +1,172 @@ +/**************************************************************************//** + * @file trng.c + * @version V1.00 + * @brief M480 series TRNG driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include + +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup TRNG_Driver TRNG Driver + @{ +*/ + + +/** @addtogroup TRNG_EXPORTED_FUNCTIONS TRNG Exported Functions + @{ +*/ + + +/** + * @brief Initialize TRNG hardware. + * @return None + */ +void TRNG_Open(void) +{ + SYS->IPRST1 |= SYS_IPRST1_TRNGRST_Msk; + SYS->IPRST1 ^= SYS_IPRST1_TRNGRST_Msk; + + TRNG->CTL |= TRNG_CTL_TRNGEN_Msk; + + TRNG->ACT |= TRNG_ACT_ACT_Msk; + + /* Waiting for ready */ + while ((TRNG->CTL & TRNG_CTL_READY_Msk) == 0); +} + + +/** + * @brief Generate a 32-bits random number word. + * @param[out] u32RndNum The output 32-bits word random number. + * + * @return Success or time-out. + * @retval 0 Success + * @retval -1 Time-out. TRNG hardware may not be enabled. + */ +int32_t TRNG_GenWord(uint32_t *u32RndNum) +{ + uint32_t i, u32Reg, timeout; + + *u32RndNum = 0; + u32Reg = TRNG->CTL; + + for (i = 0; i < 4; i++) + { + TRNG->CTL = TRNG_CTL_TRNGEN_Msk | u32Reg; + + /* TRNG should generate one byte per 125*8 us */ + for (timeout = (CLK_GetHCLKFreq() / 100); timeout > 0; timeout--) + { + if (TRNG->CTL & TRNG_CTL_DVIF_Msk) + break; + } + + if (timeout == 0) + return -1; + + *u32RndNum |= ((TRNG->DATA & 0xff) << i*8); + + } + return 0; +} + +/** + * @brief Generate a big number in binary format. + * @param[out] u8BigNum The output big number. + * @param[in] i32Len Request bit length of the output big number. It must be multiple of 8. + * + * @return Success or time-out. + * @retval 0 Success + * @retval -1 Time-out. TRNG hardware may not be enabled. + */ +int32_t TRNG_GenBignum(uint8_t u8BigNum[], int32_t i32Len) +{ + uint32_t i, u32Reg, timeout; + + u32Reg = TRNG->CTL; + + for (i = 0; i < i32Len/8; i++) + { + TRNG->CTL = TRNG_CTL_TRNGEN_Msk | u32Reg; + + /* TRNG should generate one byte per 125*8 us */ + for (timeout = (CLK_GetHCLKFreq() / 100); timeout > 0; timeout--) + { + if (TRNG->CTL & TRNG_CTL_DVIF_Msk) + break; + } + + if (timeout == 0) + return -1; + + u8BigNum[i] = (TRNG->DATA & 0xff); + } + return 0; +} + +/** + * @brief Generate a big number in hex format. + * @param[out] cBigNumHex The output hex format big number. + * @param[in] i32Len Request bit length of the output big number. It must be multiple of 8. + * + * @return Success or time-out. + * @retval 0 Success + * @retval -1 Time-out. TRNG hardware may not be enabled. + */ +int32_t TRNG_GenBignumHex(char cBigNumHex[], int32_t i32Len) +{ + uint32_t i, idx, u32Reg, timeout; + uint32_t data; + + u32Reg = TRNG->CTL; + idx = 0; + for (i = 0; i < i32Len/8; i++) + { + TRNG->CTL = TRNG_CTL_TRNGEN_Msk | u32Reg; + + /* TRNG should generate one byte per 125*8 us */ + for (timeout = (CLK_GetHCLKFreq() / 100); timeout > 0; timeout--) + { + if (TRNG->CTL & TRNG_CTL_DVIF_Msk) + break; + } + + if (timeout == 0) + return -1; + + data = (TRNG->DATA & 0xff); + + if (data >= 0xA0) + cBigNumHex[idx++] = ((data >> 4) & 0xf) - 10 + 'A'; + else + cBigNumHex[idx++] = ((data >> 4) & 0xf) + '0'; + + data &= 0xf; + if (data >= 0xA) + cBigNumHex[idx++] = data - 10 + 'A'; + else + cBigNumHex[idx++] = data + '0'; + } + cBigNumHex[idx] = 0; + return 0; +} + + +/*@}*/ /* end of group TRNG_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group TRNG_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2019 Nuvoton Technology Corp. ***/ + + diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_uart.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_uart.c new file mode 100644 index 0000000000000000000000000000000000000000..9687f89ad6fb6d4d0b98f2c872db19ef70249c8f --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_uart.c @@ -0,0 +1,656 @@ +/**************************************************************************//** + * @file uart.c + * @version V3.00 + * @brief M480 series UART driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup UART_Driver UART Driver + @{ +*/ + +/** @addtogroup UART_EXPORTED_FUNCTIONS UART Exported Functions + @{ +*/ + +/** + * @brief Clear UART specified interrupt flag + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32InterruptFlag The specified interrupt of UART module. + * - \ref UART_INTSTS_LININT_Msk : LIN bus interrupt + * - \ref UART_INTSTS_WKIF_Msk : Wake-up interrupt + * - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error interrupt + * - \ref UART_INTSTS_MODEMINT_Msk : Modem Status interrupt + * - \ref UART_INTSTS_RLSINT_Msk : Receive Line Status interrupt + * + * @return None + * + * @details The function is used to clear UART specified interrupt flag. + */ + +void UART_ClearIntFlag(UART_T* uart, uint32_t u32InterruptFlag) +{ + + if(u32InterruptFlag & UART_INTSTS_RLSINT_Msk) /* Clear Receive Line Status Interrupt */ + { + uart->FIFOSTS = UART_FIFOSTS_BIF_Msk | UART_FIFOSTS_FEF_Msk | UART_FIFOSTS_PEF_Msk; + uart->FIFOSTS = UART_FIFOSTS_ADDRDETF_Msk; + } + + if(u32InterruptFlag & UART_INTSTS_MODEMINT_Msk) /* Clear Modem Status Interrupt */ + { + uart->MODEMSTS |= UART_MODEMSTS_CTSDETF_Msk; + } + else + { + } + + if(u32InterruptFlag & UART_INTSTS_BUFERRINT_Msk) /* Clear Buffer Error Interrupt */ + { + uart->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk | UART_FIFOSTS_TXOVIF_Msk; + } + + if(u32InterruptFlag & UART_INTSTS_WKINT_Msk) /* Clear Wake-up Interrupt */ + { + uart->WKSTS = UART_WKSTS_CTSWKF_Msk | UART_WKSTS_DATWKF_Msk | + UART_WKSTS_RFRTWKF_Msk |UART_WKSTS_RS485WKF_Msk | + UART_WKSTS_TOUTWKF_Msk; + } + + if(u32InterruptFlag & UART_INTSTS_LININT_Msk) /* Clear LIN Bus Interrupt */ + { + uart->INTSTS = UART_INTSTS_LINIF_Msk; + uart->LINSTS = UART_LINSTS_BITEF_Msk | UART_LINSTS_BRKDETF_Msk | + UART_LINSTS_SLVSYNCF_Msk | UART_LINSTS_SLVIDPEF_Msk | + UART_LINSTS_SLVHEF_Msk | UART_LINSTS_SLVHDETF_Msk ; + } +} + + +/** + * @brief Disable UART interrupt + * + * @param[in] uart The pointer of the specified UART module. + * + * @return None + * + * @details The function is used to disable UART interrupt. + */ +void UART_Close(UART_T* uart) +{ + uart->INTEN = 0ul; +} + + +/** + * @brief Disable UART auto flow control function + * + * @param[in] uart The pointer of the specified UART module. + * + * @return None + * + * @details The function is used to disable UART auto flow control. + */ +void UART_DisableFlowCtrl(UART_T* uart) +{ + uart->INTEN &= ~(UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk); +} + + +/** + * @brief Disable UART specified interrupt + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32InterruptFlag The specified interrupt of UART module. + * - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt + * - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt + * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt + * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt + * - \ref UART_INTEN_MODEMIEN_Msk : Modem status interrupt + * - \ref UART_INTEN_RLSIEN_Msk : Receive Line status interrupt + * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt + * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt * + * + * @return None + * + * @details The function is used to disable UART specified interrupt and disable NVIC UART IRQ. + */ +void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag) +{ + /* Disable UART specified interrupt */ + UART_DISABLE_INT(uart, u32InterruptFlag); +} + + +/** + * @brief Enable UART auto flow control function + * + * @param[in] uart The pointer of the specified UART module. + * + * @return None + * + * @details The function is used to Enable UART auto flow control. + */ +void UART_EnableFlowCtrl(UART_T* uart) +{ + /* Set RTS pin output is low level active */ + uart->MODEM |= UART_MODEM_RTSACTLV_Msk; + + /* Set CTS pin input is low level active */ + uart->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk; + + /* Set RTS and CTS auto flow control enable */ + uart->INTEN |= UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk; +} + + +/** + * @brief The function is used to enable UART specified interrupt and enable NVIC UART IRQ. + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32InterruptFlag The specified interrupt of UART module: + * - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt + * - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt + * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt + * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt + * - \ref UART_INTEN_MODEMIEN_Msk : Modem status interrupt + * - \ref UART_INTEN_RLSIEN_Msk : Receive Line status interrupt + * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt + * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt * + * + * @return None + * + * @details The function is used to enable UART specified interrupt and enable NVIC UART IRQ. + */ +void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag) +{ + /* Enable UART specified interrupt */ + UART_ENABLE_INT(uart, u32InterruptFlag); +} + + +/** + * @brief Open and set UART function + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32baudrate The baudrate of UART module. + * + * @return None + * + * @details This function use to enable UART function and set baud-rate. + */ +void UART_Open(UART_T* uart, uint32_t u32baudrate) +{ + uint32_t u32UartClkSrcSel=0ul, u32UartClkDivNum=0ul; + uint32_t u32ClkTbl[4] = {__HXT, 0ul, __LXT, __HIRC}; + uint32_t u32Baud_Div = 0ul; + + + if(uart==(UART_T*)UART0) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = ((uint32_t)(CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk)) >> CLK_CLKSEL1_UART0SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos; + } + else if(uart==(UART_T*)UART1) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos; + } + else if(uart==(UART_T*)UART2) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos; + } + else if(uart==(UART_T*)UART3) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART3SEL_Msk) >> CLK_CLKSEL3_UART3SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART3DIV_Msk) >> CLK_CLKDIV4_UART3DIV_Pos; + } + else if(uart==(UART_T*)UART4) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART4SEL_Msk) >> CLK_CLKSEL3_UART4SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART4DIV_Msk) >> CLK_CLKDIV4_UART4DIV_Pos; + } + else if(uart==(UART_T*)UART5) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART5SEL_Msk) >> CLK_CLKSEL3_UART5SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART5DIV_Msk) >> CLK_CLKDIV4_UART5DIV_Pos; + } + + /* Select UART function */ + uart->FUNCSEL = UART_FUNCSEL_UART; + + /* Set UART line configuration */ + uart->LINE = UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1; + + /* Set UART Rx and RTS trigger level */ + uart->FIFO &= ~(UART_FIFO_RFITL_Msk | UART_FIFO_RTSTRGLV_Msk); + + /* Get PLL clock frequency if UART clock source selection is PLL */ + if(u32UartClkSrcSel == 1ul) + { + u32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq(); + } + + /* Set UART baud rate */ + if(u32baudrate != 0ul) + { + u32Baud_Div = UART_BAUD_MODE2_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate); + + if(u32Baud_Div > 0xFFFFul) + { + uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate)); + } + else + { + uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div); + } + } +} + + +/** + * @brief Read UART data + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] pu8RxBuf The buffer to receive the data of receive FIFO. + * @param[in] u32ReadBytes The the read bytes number of data. + * + * @return u32Count Receive byte count + * + * @details The function is used to read Rx data from RX FIFO and the data will be stored in pu8RxBuf. + */ +uint32_t UART_Read(UART_T* uart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes) +{ + uint32_t u32Count, u32delayno; + uint32_t u32Exit = 0ul; + + for(u32Count = 0ul; u32Count < u32ReadBytes; u32Count++) + { + u32delayno = 0ul; + + while(uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) /* Check RX empty => failed */ + { + u32delayno++; + if(u32delayno >= 0x40000000ul) + { + u32Exit = 1ul; + break; + } + else + { + } + } + + if(u32Exit == 1ul) + { + break; + } + else + { + pu8RxBuf[u32Count] = (uint8_t)uart->DAT; /* Get Data from UART RX */ + } + } + + return u32Count; + +} + + +/** + * @brief Set UART line configuration + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32baudrate The register value of baudrate of UART module. + * If u32baudrate = 0, UART baudrate will not change. + * @param[in] u32data_width The data length of UART module. + * - \ref UART_WORD_LEN_5 + * - \ref UART_WORD_LEN_6 + * - \ref UART_WORD_LEN_7 + * - \ref UART_WORD_LEN_8 + * @param[in] u32parity The parity setting (none/odd/even/mark/space) of UART module. + * - \ref UART_PARITY_NONE + * - \ref UART_PARITY_ODD + * - \ref UART_PARITY_EVEN + * - \ref UART_PARITY_MARK + * - \ref UART_PARITY_SPACE + * @param[in] u32stop_bits The stop bit length (1/1.5/2 bit) of UART module. + * - \ref UART_STOP_BIT_1 + * - \ref UART_STOP_BIT_1_5 + * - \ref UART_STOP_BIT_2 + * + * @return None + * + * @details This function use to config UART line setting. + */ +void UART_SetLineConfig(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits) +{ + uint32_t u32UartClkSrcSel=0ul, u32UartClkDivNum=0ul; + uint32_t u32ClkTbl[4ul] = {__HXT, 0ul, __LXT, __HIRC}; + uint32_t u32Baud_Div = 0ul; + + + if(uart==(UART_T*)UART0) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk) >> CLK_CLKSEL1_UART0SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos; + } + else if(uart==(UART_T*)UART1) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos; + } + else if(uart==(UART_T*)UART2) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos; + } + else if(uart==(UART_T*)UART3) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART3SEL_Msk) >> CLK_CLKSEL3_UART3SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART3DIV_Msk) >> CLK_CLKDIV4_UART3DIV_Pos; + } + else if(uart==(UART_T*)UART4) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART4SEL_Msk) >> CLK_CLKSEL3_UART4SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART4DIV_Msk) >> CLK_CLKDIV4_UART4DIV_Pos; + } + else if(uart==(UART_T*)UART5) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART5SEL_Msk) >> CLK_CLKSEL3_UART5SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART5DIV_Msk) >> CLK_CLKDIV4_UART5DIV_Pos; + } + + /* Get PLL clock frequency if UART clock source selection is PLL */ + if(u32UartClkSrcSel == 1ul) + { + u32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq(); + } + else + { + } + + /* Set UART baud rate */ + if(u32baudrate != 0ul) + { + u32Baud_Div = UART_BAUD_MODE2_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate); + + if(u32Baud_Div > 0xFFFFul) + { + uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate)); + } + else + { + uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div); + } + } + + /* Set UART line configuration */ + uart->LINE = u32data_width | u32parity | u32stop_bits; +} + + +/** + * @brief Set Rx timeout count + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32TOC Rx timeout counter. + * + * @return None + * + * @details This function use to set Rx timeout count. + */ +void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC) +{ + /* Set time-out interrupt comparator */ + uart->TOUT = (uart->TOUT & ~UART_TOUT_TOIC_Msk) | (u32TOC); + + /* Set time-out counter enable */ + uart->INTEN |= UART_INTEN_TOCNTEN_Msk; +} + + +/** + * @brief Select and configure IrDA function + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32Buadrate The baudrate of UART module. + * @param[in] u32Direction The direction of UART module in IrDA mode: + * - \ref UART_IRDA_TXEN + * - \ref UART_IRDA_RXEN + * + * @return None + * + * @details The function is used to configure IrDA relative settings. It consists of TX or RX mode and baudrate. + */ +void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction) +{ + uint32_t u32UartClkSrcSel=0ul, u32UartClkDivNum=0ul; + uint32_t u32ClkTbl[4ul] = {__HXT, 0ul, __LXT, __HIRC}; + uint32_t u32Baud_Div; + + /* Select IrDA function mode */ + uart->FUNCSEL = UART_FUNCSEL_IrDA; + + + if(uart==UART0) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk) >> CLK_CLKSEL1_UART0SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos; + } + else if(uart==UART1) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos; + } + else if(uart==UART2) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos; + } + else if(uart==UART3) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART3SEL_Msk) >> CLK_CLKSEL3_UART3SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART3DIV_Msk) >> CLK_CLKDIV4_UART3DIV_Pos; + } + else if(uart==UART4) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART4SEL_Msk) >> CLK_CLKSEL3_UART4SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART4DIV_Msk) >> CLK_CLKDIV4_UART4DIV_Pos; + } + else if(uart==UART5) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART5SEL_Msk) >> CLK_CLKSEL3_UART5SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART5DIV_Msk) >> CLK_CLKDIV4_UART5DIV_Pos; + } + + + /* Get PLL clock frequency if UART clock source selection is PLL */ + if(u32UartClkSrcSel == 1ul) + { + u32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq(); + } + else + { + } + + /* Set UART IrDA baud rate in mode 0 */ + if(u32Buadrate != 0ul) + { + u32Baud_Div = UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32Buadrate); + + if(u32Baud_Div < 0xFFFFul) + { + uart->BAUD = (UART_BAUD_MODE0 | u32Baud_Div); + } + else + { + } + } + + /* Configure IrDA relative settings */ + if(u32Direction == UART_IRDA_RXEN) + { + uart->IRDA |= UART_IRDA_RXINV_Msk; /*Rx signal is inverse*/ + uart->IRDA &= ~UART_IRDA_TXEN_Msk; + } + else + { + uart->IRDA &= ~UART_IRDA_TXINV_Msk; /*Tx signal is not inverse*/ + uart->IRDA |= UART_IRDA_TXEN_Msk; + } + +} + + +/** + * @brief Select and configure RS485 function + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32Mode The operation mode(NMM/AUD/AAD). + * - \ref UART_ALTCTL_RS485NMM_Msk + * - \ref UART_ALTCTL_RS485AUD_Msk + * - \ref UART_ALTCTL_RS485AAD_Msk + * @param[in] u32Addr The RS485 address. + * + * @return None + * + * @details The function is used to set RS485 relative setting. + */ +void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr) +{ + /* Select UART RS485 function mode */ + uart->FUNCSEL = UART_FUNCSEL_RS485; + + /* Set RS585 configuration */ + uart->ALTCTL &= ~(UART_ALTCTL_RS485NMM_Msk | UART_ALTCTL_RS485AUD_Msk | UART_ALTCTL_RS485AAD_Msk | UART_ALTCTL_ADDRMV_Msk); + uart->ALTCTL |= (u32Mode | (u32Addr << UART_ALTCTL_ADDRMV_Pos)); +} + + +/** + * @brief Select and configure LIN function + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32Mode The LIN direction : + * - \ref UART_ALTCTL_LINTXEN_Msk + * - \ref UART_ALTCTL_LINRXEN_Msk + * @param[in] u32BreakLength The break field length. + * + * @return None + * + * @details The function is used to set LIN relative setting. + */ +void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength) +{ + /* Select LIN function mode */ + uart->FUNCSEL = UART_FUNCSEL_LIN; + + /* Select LIN function setting : Tx enable, Rx enable and break field length */ + uart->ALTCTL &= ~(UART_ALTCTL_LINTXEN_Msk | UART_ALTCTL_LINRXEN_Msk | UART_ALTCTL_BRKFL_Msk); + uart->ALTCTL |= (u32Mode | (u32BreakLength << UART_ALTCTL_BRKFL_Pos)); +} + + +/** + * @brief Write UART data + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] pu8TxBuf The buffer to send the data to UART transmission FIFO. + * @param[out] u32WriteBytes The byte number of data. + * + * @return u32Count transfer byte count + * + * @details The function is to write data into TX buffer to transmit data by UART. + */ +uint32_t UART_Write(UART_T* uart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes) +{ + uint32_t u32Count, u32delayno; + uint32_t u32Exit = 0ul; + + for(u32Count = 0ul; u32Count != u32WriteBytes; u32Count++) + { + u32delayno = 0ul; + while(uart->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) /* Check Tx Full */ + { + u32delayno++; + if(u32delayno >= 0x40000000ul) + { + u32Exit = 1ul; + break; + } + else + { + } + } + + if(u32Exit == 1ul) + { + break; + } + else + { + uart->DAT = pu8TxBuf[u32Count]; /* Send UART Data from buffer */ + } + } + + return u32Count; +} + + +/*@}*/ /* end of group UART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group UART_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ + + + diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_usbd.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_usbd.c new file mode 100644 index 0000000000000000000000000000000000000000..fd783140238ad48cc4f1f6af5d4d803c02baf472 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_usbd.c @@ -0,0 +1,745 @@ +/**************************************************************************//** + * @file usbd.c + * @version V1.00 + * @brief M480 USBD driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include "NuMicro.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USBD_Driver USBD Driver + @{ +*/ + + +/** @addtogroup USBD_EXPORTED_FUNCTIONS USBD Exported Functions + @{ +*/ + +/* Global variables for Control Pipe */ +uint8_t g_usbd_SetupPacket[8] = {0ul}; /*!< Setup packet buffer */ +volatile uint8_t g_usbd_RemoteWakeupEn = 0ul; /*!< Remote wake up function enable flag */ + +/** + * @cond HIDDEN_SYMBOLS + */ +static uint8_t *g_usbd_CtrlInPointer = 0; +static uint8_t *g_usbd_CtrlOutPointer = 0; +static volatile uint32_t g_usbd_CtrlInSize = 0ul; +static volatile uint32_t g_usbd_CtrlOutSize = 0ul; +static volatile uint32_t g_usbd_CtrlOutSizeLimit = 0ul; +static volatile uint32_t g_usbd_UsbAddr = 0ul; +static volatile uint32_t g_usbd_UsbConfig = 0ul; +static volatile uint32_t g_usbd_CtrlMaxPktSize = 8ul; +static volatile uint32_t g_usbd_UsbAltInterface = 0ul; +static volatile uint32_t g_usbd_CtrlOutToggle = 0; +static volatile uint8_t g_usbd_CtrlInZeroFlag = 0ul; +/** + * @endcond + */ + +const S_USBD_INFO_T *g_usbd_sInfo; /*!< A pointer for USB information structure */ + +VENDOR_REQ g_usbd_pfnVendorRequest = NULL; /*!< USB Vendor Request Functional Pointer */ +CLASS_REQ g_usbd_pfnClassRequest = NULL; /*!< USB Class Request Functional Pointer */ +SET_INTERFACE_REQ g_usbd_pfnSetInterface = NULL; /*!< USB Set Interface Functional Pointer */ +SET_CONFIG_CB g_usbd_pfnSetConfigCallback = NULL; /*!< USB Set configuration callback function pointer */ +uint32_t g_u32EpStallLock = 0ul; /*!< Bit map flag to lock specified EP when SET_FEATURE */ + +/** + * @brief This function makes USBD module to be ready to use + * + * @param[in] param The structure of USBD information. + * @param[in] pfnClassReq USB Class request callback function. + * @param[in] pfnSetInterface USB Set Interface request callback function. + * + * @return None + * + * @details This function will enable USB controller, USB PHY transceiver and pull-up resistor of USB_D+ pin. USB PHY will drive SE0 to bus. + */ +void USBD_Open(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface) +{ + g_usbd_sInfo = param; + g_usbd_pfnClassRequest = pfnClassReq; + g_usbd_pfnSetInterface = pfnSetInterface; + + /* get EP0 maximum packet size */ + g_usbd_CtrlMaxPktSize = g_usbd_sInfo->gu8DevDesc[7]; + + /* Initial USB engine */ + USBD->ATTR = 0x6D0ul; + /* Force SE0 */ + USBD_SET_SE0(); +} + +/** + * @brief This function makes USB host to recognize the device + * + * @param None + * + * @return None + * + * @details Enable WAKEUP, FLDET, USB and BUS interrupts. Disable software-disconnect function after 100ms delay with SysTick timer. + */ +void USBD_Start(void) +{ + /* Disable software-disconnect function */ + USBD_CLR_SE0(); + USBD->ATTR = 0x7D0ul; + + /* Clear USB-related interrupts before enable interrupt */ + USBD_CLR_INT_FLAG(USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP); + + /* Enable USB-related interrupts. */ + USBD_ENABLE_INT(USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP); +} + +/** + * @brief Get the received SETUP packet + * + * @param[in] buf A buffer pointer used to store 8-byte SETUP packet. + * + * @return None + * + * @details Store SETUP packet to a user-specified buffer. + * + */ +void USBD_GetSetupPacket(uint8_t *buf) +{ + USBD_MemCopy(buf, g_usbd_SetupPacket, 8ul); +} + +/** + * @brief Process SETUP packet + * + * @param None + * + * @return None + * + * @details Parse SETUP packet and perform the corresponding action. + * + */ +void USBD_ProcessSetupPacket(void) +{ + g_usbd_CtrlOutToggle = 0; + /* Get SETUP packet from USB buffer */ + USBD_MemCopy(g_usbd_SetupPacket, (uint8_t *)USBD_BUF_BASE, 8ul); + + /* Check the request type */ + switch(g_usbd_SetupPacket[0] & 0x60ul) + { + case REQ_STANDARD: + { + USBD_StandardRequest(); + break; + } + case REQ_CLASS: + { + if(g_usbd_pfnClassRequest != NULL) + { + g_usbd_pfnClassRequest(); + } + break; + } + case REQ_VENDOR: + { + if(g_usbd_pfnVendorRequest != NULL) + { + g_usbd_pfnVendorRequest(); + } + break; + } + default: + { + /* Setup error, stall the device */ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + break; + } + } +} + +/** + * @brief Process GetDescriptor request + * + * @param None + * + * @return None + * + * @details Parse GetDescriptor request and perform the corresponding action. + * + */ +void USBD_GetDescriptor(void) +{ + uint32_t u32Len; + + g_usbd_CtrlInZeroFlag = (uint8_t)0ul; + u32Len = 0ul; + u32Len = g_usbd_SetupPacket[7]; + u32Len <<= 8ul; + u32Len += g_usbd_SetupPacket[6]; + + switch(g_usbd_SetupPacket[3]) + { + /* Get Device Descriptor */ + case DESC_DEVICE: + { + u32Len = USBD_Minimum(u32Len, (uint32_t)LEN_DEVICE); + USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8DevDesc, u32Len); + + break; + } + /* Get Configuration Descriptor */ + case DESC_CONFIG: + { + uint32_t u32TotalLen; + + u32TotalLen = g_usbd_sInfo->gu8ConfigDesc[3]; + u32TotalLen = g_usbd_sInfo->gu8ConfigDesc[2] + (u32TotalLen << 8); + + if (u32Len > u32TotalLen) + { + u32Len = u32TotalLen; + if ((u32Len % g_usbd_CtrlMaxPktSize) == 0ul) + { + g_usbd_CtrlInZeroFlag = (uint8_t)1ul; + } + } + USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8ConfigDesc, u32Len); + + break; + } + + /* Get BOS Descriptor */ + case DESC_BOS: + { + if (g_usbd_sInfo->gu8BosDesc == 0) + { + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + } + else + { + u32Len = USBD_Minimum(u32Len, LEN_BOS+LEN_BOSCAP); + USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8BosDesc, u32Len); + } + break; + } + /* Get HID Descriptor */ + case DESC_HID: + { + /* CV3.0 HID Class Descriptor Test, + Need to indicate index of the HID Descriptor within gu8ConfigDescriptor, specifically HID Composite device. */ + uint32_t u32ConfigDescOffset; /* u32ConfigDescOffset is configuration descriptor offset (HID descriptor start index) */ + u32Len = USBD_Minimum(u32Len, LEN_HID); + u32ConfigDescOffset = g_usbd_sInfo->gu32ConfigHidDescIdx[g_usbd_SetupPacket[4]]; + USBD_PrepareCtrlIn((uint8_t *)&g_usbd_sInfo->gu8ConfigDesc[u32ConfigDescOffset], u32Len); + + break; + } + /* Get Report Descriptor */ + case DESC_HID_RPT: + { + if (u32Len > g_usbd_sInfo->gu32HidReportSize[g_usbd_SetupPacket[4]]) + { + u32Len = g_usbd_sInfo->gu32HidReportSize[g_usbd_SetupPacket[4]]; + if ((u32Len % g_usbd_CtrlMaxPktSize) == 0ul) + { + g_usbd_CtrlInZeroFlag = (uint8_t)1ul; + } + } + USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8HidReportDesc[g_usbd_SetupPacket[4]], u32Len); + break; + } + /* Get String Descriptor */ + case DESC_STRING: + { + /* Get String Descriptor */ + if(g_usbd_SetupPacket[2] < 4ul) + { + if (u32Len > g_usbd_sInfo->gu8StringDesc[g_usbd_SetupPacket[2]][0]) + { + u32Len = g_usbd_sInfo->gu8StringDesc[g_usbd_SetupPacket[2]][0]; + if ((u32Len % g_usbd_CtrlMaxPktSize) == 0ul) + { + g_usbd_CtrlInZeroFlag = (uint8_t)1ul; + } + } + USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8StringDesc[g_usbd_SetupPacket[2]], u32Len); + break; + } + else + { + /* Not support. Reply STALL. */ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + break; + } + } + default: + /* Not support. Reply STALL.*/ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + break; + } +} + +/** + * @brief Process standard request + * + * @param None + * + * @return None + * + * @details Parse standard request and perform the corresponding action. + * + */ +void USBD_StandardRequest(void) +{ + uint32_t addr; + /* clear global variables for new request */ + g_usbd_CtrlInPointer = 0; + g_usbd_CtrlInSize = 0ul; + + if((g_usbd_SetupPacket[0] & 0x80ul) == 0x80ul) /* request data transfer direction */ + { + /* Device to host */ + switch(g_usbd_SetupPacket[1]) + { + case GET_CONFIGURATION: + { + /* Return current configuration setting */ + /* Data stage */ + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + M8(addr) = (uint8_t)g_usbd_UsbConfig; + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 1ul); + /* Status stage */ + USBD_PrepareCtrlOut(0, 0ul); + break; + } + case GET_DESCRIPTOR: + { + USBD_GetDescriptor(); + USBD_PrepareCtrlOut(0, 0ul); /* For status stage */ + break; + } + case GET_INTERFACE: + { + /* Return current interface setting */ + /* Data stage */ + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + M8(addr) = (uint8_t)g_usbd_UsbAltInterface; + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 1ul); + /* Status stage */ + USBD_PrepareCtrlOut(0, 0ul); + break; + } + case GET_STATUS: + { + /* Device */ + if(g_usbd_SetupPacket[0] == 0x80ul) + { + uint8_t u8Tmp; + + u8Tmp = (uint8_t)0ul; + if ((g_usbd_sInfo->gu8ConfigDesc[7] & 0x40ul) == 0x40ul) + { + u8Tmp |= (uint8_t)1ul; /* Self-Powered/Bus-Powered.*/ + } + if ((g_usbd_sInfo->gu8ConfigDesc[7] & 0x20ul) == 0x20ul) + { + u8Tmp |= (uint8_t)(g_usbd_RemoteWakeupEn << 1ul); /* Remote wake up */ + } + + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + M8(addr) = u8Tmp; + + } + /* Interface */ + else if(g_usbd_SetupPacket[0] == 0x81ul) + { + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + M8(addr) = (uint8_t)0ul; + } + /* Endpoint */ + else if(g_usbd_SetupPacket[0] == 0x82ul) + { + uint8_t ep = (uint8_t)(g_usbd_SetupPacket[4] & 0xFul); + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + M8(addr) = (uint8_t)(USBD_GetStall(ep) ? 1ul : 0ul); + } + + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0) + 1ul; + M8(addr) = (uint8_t)0ul; + /* Data stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 2ul); + /* Status stage */ + USBD_PrepareCtrlOut(0, 0ul); + break; + } + default: + { + /* Setup error, stall the device */ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + break; + } + } + } + else + { + /* Host to device */ + switch(g_usbd_SetupPacket[1]) + { + case CLEAR_FEATURE: + { + if(g_usbd_SetupPacket[2] == FEATURE_ENDPOINT_HALT) + { + uint32_t epNum, i; + + /* EP number stall is not allow to be clear in MSC class "Error Recovery Test". + a flag: g_u32EpStallLock is added to support it */ + epNum = (uint8_t)(g_usbd_SetupPacket[4] & 0xFul); + for(i = 0ul; i < USBD_MAX_EP; i++) + { + if(((USBD->EP[i].CFG & 0xFul) == epNum) && ((g_u32EpStallLock & (1ul << i)) == 0ul)) + { + USBD->EP[i].CFGP &= ~USBD_CFGP_SSTALL_Msk; + USBD->EP[i].CFG &= ~USBD_CFG_DSQSYNC_Msk; + } + } + } + else if(g_usbd_SetupPacket[2] == FEATURE_DEVICE_REMOTE_WAKEUP) + { + g_usbd_RemoteWakeupEn = (uint8_t)0; + } + + /* Status stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0ul); + break; + } + case SET_ADDRESS: + { + g_usbd_UsbAddr = g_usbd_SetupPacket[2]; + /* Status Stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0ul); + + break; + } + case SET_CONFIGURATION: + { + g_usbd_UsbConfig = g_usbd_SetupPacket[2]; + + if(g_usbd_pfnSetConfigCallback) + { + g_usbd_pfnSetConfigCallback(); + } + + /* Status stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0ul); + break; + } + case SET_FEATURE: + { + if( (g_usbd_SetupPacket[0] & 0xFul) == 0ul ) /* 0: device */ + { + if((g_usbd_SetupPacket[2] == 3ul) && (g_usbd_SetupPacket[3] == 0ul)) /* 3: HNP enable */ + { + OTG->CTL |= (OTG_CTL_HNPREQEN_Msk | OTG_CTL_BUSREQ_Msk); + } + } + if(g_usbd_SetupPacket[2] == FEATURE_ENDPOINT_HALT) + { + USBD_SetStall((uint8_t)(g_usbd_SetupPacket[4] & 0xFul)); + } + else if(g_usbd_SetupPacket[2] == FEATURE_DEVICE_REMOTE_WAKEUP) + { + g_usbd_RemoteWakeupEn = (uint8_t)1ul; + } + + /* Status stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0ul); + + break; + } + case SET_INTERFACE: + { + g_usbd_UsbAltInterface = g_usbd_SetupPacket[2]; + if(g_usbd_pfnSetInterface != NULL) + { + g_usbd_pfnSetInterface(g_usbd_UsbAltInterface); + } + /* Status stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0ul); + break; + } + default: + { + /* Setup error, stall the device */ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + break; + } + } + } +} + +/** + * @brief Prepare the first Control IN pipe + * + * @param[in] pu8Buf The pointer of data sent to USB host. + * @param[in] u32Size The IN transfer size. + * + * @return None + * + * @details Prepare data for Control IN transfer. + * + */ +void USBD_PrepareCtrlIn(uint8_t pu8Buf[], uint32_t u32Size) +{ + uint32_t addr; + if(u32Size > g_usbd_CtrlMaxPktSize) + { + /* Data size > MXPLD */ + g_usbd_CtrlInPointer = pu8Buf + g_usbd_CtrlMaxPktSize; + g_usbd_CtrlInSize = u32Size - g_usbd_CtrlMaxPktSize; + USBD_SET_DATA1(EP0); + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + USBD_MemCopy((uint8_t *)addr, pu8Buf, g_usbd_CtrlMaxPktSize); + USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlMaxPktSize); + } + else + { + /* Data size <= MXPLD */ + g_usbd_CtrlInPointer = 0; + g_usbd_CtrlInSize = 0ul; + USBD_SET_DATA1(EP0); + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + USBD_MemCopy((uint8_t *)addr, pu8Buf, u32Size); + USBD_SET_PAYLOAD_LEN(EP0, u32Size); + } +} + +/** + * @brief Repeat Control IN pipe + * + * @param None + * + * @return None + * + * @details This function processes the remained data of Control IN transfer. + * + */ +void USBD_CtrlIn(void) +{ + uint32_t addr; + + if(g_usbd_CtrlInSize) + { + /* Process remained data */ + if(g_usbd_CtrlInSize > g_usbd_CtrlMaxPktSize) + { + /* Data size > MXPLD */ + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + USBD_MemCopy((uint8_t *)addr, (uint8_t *)g_usbd_CtrlInPointer, g_usbd_CtrlMaxPktSize); + USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlMaxPktSize); + g_usbd_CtrlInPointer += g_usbd_CtrlMaxPktSize; + g_usbd_CtrlInSize -= g_usbd_CtrlMaxPktSize; + } + else + { + /* Data size <= MXPLD */ + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + USBD_MemCopy((uint8_t *)addr, (uint8_t *)g_usbd_CtrlInPointer, g_usbd_CtrlInSize); + USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlInSize); + g_usbd_CtrlInPointer = 0; + g_usbd_CtrlInSize = 0ul; + } + } + else + { + /* In ACK for Set address */ + if((g_usbd_SetupPacket[0] == REQ_STANDARD) && (g_usbd_SetupPacket[1] == SET_ADDRESS)) + { + addr = USBD_GET_ADDR(); + if((addr != g_usbd_UsbAddr) && (addr == 0ul)) + { + USBD_SET_ADDR(g_usbd_UsbAddr); + } + } + + /* For the case of data size is integral times maximum packet size */ + if(g_usbd_CtrlInZeroFlag) + { + USBD_SET_PAYLOAD_LEN(EP0, 0ul); + g_usbd_CtrlInZeroFlag = (uint8_t)0ul; + } + } +} + +/** + * @brief Prepare the first Control OUT pipe + * + * @param[in] pu8Buf The pointer of data received from USB host. + * @param[in] u32Size The OUT transfer size. + * + * @return None + * + * @details This function is used to prepare the first Control OUT transfer. + * + */ +void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size) +{ + g_usbd_CtrlOutPointer = pu8Buf; + g_usbd_CtrlOutSize = 0ul; + g_usbd_CtrlOutSizeLimit = u32Size; + USBD_SET_PAYLOAD_LEN(EP1, g_usbd_CtrlMaxPktSize); +} + +/** + * @brief Repeat Control OUT pipe + * + * @param None + * + * @return None + * + * @details This function processes the successive Control OUT transfer. + * + */ +void USBD_CtrlOut(void) +{ + uint32_t u32Size; + uint32_t addr; + + if (g_usbd_CtrlOutToggle != (USBD->EPSTS0 & USBD_EPSTS0_EPSTS1_Msk)) + { + g_usbd_CtrlOutToggle = USBD->EPSTS0 & USBD_EPSTS0_EPSTS1_Msk; + if (g_usbd_CtrlOutSize < g_usbd_CtrlOutSizeLimit) + { + u32Size = USBD_GET_PAYLOAD_LEN(EP1); + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP1); + USBD_MemCopy((uint8_t *)g_usbd_CtrlOutPointer, (uint8_t *)addr, u32Size); + g_usbd_CtrlOutPointer += u32Size; + g_usbd_CtrlOutSize += u32Size; + + if(g_usbd_CtrlOutSize < g_usbd_CtrlOutSizeLimit) + { + USBD_SET_PAYLOAD_LEN(EP1, g_usbd_CtrlMaxPktSize); + } + } + } + else + { + USBD_SET_PAYLOAD_LEN(EP1, g_usbd_CtrlMaxPktSize); + } +} + +/** + * @brief Reset software flags + * + * @param None + * + * @return None + * + * @details This function resets all variables for protocol and resets USB device address to 0. + * + */ +void USBD_SwReset(void) +{ + uint32_t i; + + /* Reset all variables for protocol */ + g_usbd_CtrlInPointer = 0; + g_usbd_CtrlInSize = 0ul; + g_usbd_CtrlOutPointer = 0; + g_usbd_CtrlOutSize = 0ul; + g_usbd_CtrlOutSizeLimit = 0ul; + g_u32EpStallLock = 0ul; + memset(g_usbd_SetupPacket, 0, 8ul); + + /* Reset PID DATA0 */ + for(i=0ul; iEP[i].CFG &= ~USBD_CFG_DSQSYNC_Msk; + } + + /* Reset USB device address */ + USBD_SET_ADDR(0ul); +} + +/** + * @brief USBD Set Vendor Request + * + * @param[in] pfnVendorReq Vendor Request Callback Function + * + * @return None + * + * @details This function is used to set USBD vendor request callback function + */ +void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq) +{ + g_usbd_pfnVendorRequest = pfnVendorReq; +} + +/** + * @brief The callback function which called when get SET CONFIGURATION request + * + * @param[in] pfnSetConfigCallback Callback function pointer for SET CONFIGURATION request + * + * @return None + * + * @details This function is used to set the callback function which will be called at SET CONFIGURATION request. + */ +void USBD_SetConfigCallback(SET_CONFIG_CB pfnSetConfigCallback) +{ + g_usbd_pfnSetConfigCallback = pfnSetConfigCallback; +} + + +/** + * @brief EP stall lock function to avoid stall clear by USB SET FEATURE request. + * + * @param[in] u32EpBitmap Use bitmap to select which endpoints will be locked + * + * @return None + * + * @details This function is used to lock relative endpoint to avoid stall clear by SET FEATURE request. + * If ep stall locked, user needs to reset USB device or re-configure device to clear it. + */ +void USBD_LockEpStall(uint32_t u32EpBitmap) +{ + g_u32EpStallLock = u32EpBitmap; +} + + +/*@}*/ /* end of group USBD_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USBD_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_usci_i2c.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_usci_i2c.c new file mode 100644 index 0000000000000000000000000000000000000000..ee62fca567b1241b151297fcfb951f2955d460b5 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_usci_i2c.c @@ -0,0 +1,1679 @@ +/****************************************************************************//** + * @file usci_i2c.c + * @version V3.00 + * @brief M480 series USCI I2C(UI2C) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_I2C_Driver USCI_I2C Driver + @{ +*/ + + +/** @addtogroup USCI_I2C_EXPORTED_FUNCTIONS USCI_I2C Exported Functions + @{ +*/ + +/** + * @brief This function makes USCI_I2C module be ready and set the wanted bus clock + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32BusClock The target bus speed of USCI_I2C module. + * + * @return Actual USCI_I2C bus clock frequency. + * + * @details Enable USCI_I2C module and configure USCI_I2C module(bus clock, data format). + */ +uint32_t UI2C_Open(UI2C_T *ui2c, uint32_t u32BusClock) +{ + uint32_t u32ClkDiv; + uint32_t u32Pclk; + + if( ui2c == UI2C0 ) + { + u32Pclk = CLK_GetPCLK0Freq(); + } + else + { + u32Pclk = CLK_GetPCLK1Freq(); + } + + u32ClkDiv = (uint32_t) ((((((u32Pclk/2U)*10U)/(u32BusClock))+5U)/10U)-1U); /* Compute proper divider for USCI_I2C clock */ + + /* Enable USCI_I2C protocol */ + ui2c->CTL &= ~UI2C_CTL_FUNMODE_Msk; + ui2c->CTL = 4U << UI2C_CTL_FUNMODE_Pos; + + /* Data format configuration */ + /* 8 bit data length */ + ui2c->LINECTL &= ~UI2C_LINECTL_DWIDTH_Msk; + ui2c->LINECTL |= 8U << UI2C_LINECTL_DWIDTH_Pos; + + /* MSB data format */ + ui2c->LINECTL &= ~UI2C_LINECTL_LSB_Msk; + + /* Set USCI_I2C bus clock */ + ui2c->BRGEN &= ~UI2C_BRGEN_CLKDIV_Msk; + ui2c->BRGEN |= (u32ClkDiv << UI2C_BRGEN_CLKDIV_Pos); + ui2c->PROTCTL |= UI2C_PROTCTL_PROTEN_Msk; + + return ( u32Pclk / ((u32ClkDiv+1U)<<1U) ); +} + +/** + * @brief This function closes the USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details Close USCI_I2C protocol function. + */ +void UI2C_Close(UI2C_T *ui2c) +{ + /* Disable USCI_I2C function */ + ui2c->CTL &= ~UI2C_CTL_FUNMODE_Msk; +} + +/** + * @brief This function clears the time-out flag + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details Clear time-out flag when time-out flag is set. + */ +void UI2C_ClearTimeoutFlag(UI2C_T *ui2c) +{ + ui2c->PROTSTS = UI2C_PROTSTS_TOIF_Msk; +} + +/** + * @brief This function sets the control bit of the USCI_I2C module. + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8Start Set START bit to USCI_I2C module. + * @param[in] u8Stop Set STOP bit to USCI_I2C module. + * @param[in] u8Ptrg Set PTRG bit to USCI_I2C module. + * @param[in] u8Ack Set ACK bit to USCI_I2C module. + * + * @return None + * + * @details The function set USCI_I2C control bit of USCI_I2C bus protocol. + */ +void UI2C_Trigger(UI2C_T *ui2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Ptrg, uint8_t u8Ack) +{ + uint32_t u32Reg = 0U; + uint32_t u32Val = ui2c->PROTCTL & ~(UI2C_PROTCTL_STA_Msk | UI2C_PROTCTL_STO_Msk | UI2C_PROTCTL_AA_Msk); + + if (u8Start) + { + u32Reg |= UI2C_PROTCTL_STA_Msk; + } + if (u8Stop) + { + u32Reg |= UI2C_PROTCTL_STO_Msk; + } + if (u8Ptrg) + { + u32Reg |= UI2C_PROTCTL_PTRG_Msk; + } + if (u8Ack) + { + u32Reg |= UI2C_PROTCTL_AA_Msk; + } + + ui2c->PROTCTL = u32Val | u32Reg; +} + +/** + * @brief This function disables the interrupt of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to an interrupt enable bit. + * This parameter decides which interrupts will be disabled. It is combination of: + * - \ref UI2C_TO_INT_MASK + * - \ref UI2C_STAR_INT_MASK + * - \ref UI2C_STOR_INT_MASK + * - \ref UI2C_NACK_INT_MASK + * - \ref UI2C_ARBLO_INT_MASK + * - \ref UI2C_ERR_INT_MASK + * - \ref UI2C_ACK_INT_MASK + * + * @return None + * + * @details The function is used to disable USCI_I2C bus interrupt events. + */ +void UI2C_DisableInt(UI2C_T *ui2c, uint32_t u32Mask) +{ + /* Disable time-out interrupt flag */ + if((u32Mask & UI2C_TO_INT_MASK) == UI2C_TO_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_TOIEN_Msk; + } + + /* Disable start condition received interrupt flag */ + if((u32Mask & UI2C_STAR_INT_MASK) == UI2C_STAR_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_STARIEN_Msk; + } + + /* Disable stop condition received interrupt flag */ + if((u32Mask & UI2C_STOR_INT_MASK) == UI2C_STOR_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_STORIEN_Msk; + } + + /* Disable non-acknowledge interrupt flag */ + if((u32Mask & UI2C_NACK_INT_MASK) == UI2C_NACK_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_NACKIEN_Msk; + } + + /* Disable arbitration lost interrupt flag */ + if((u32Mask & UI2C_ARBLO_INT_MASK) == UI2C_ARBLO_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_ARBLOIEN_Msk; + } + + /* Disable error interrupt flag */ + if((u32Mask & UI2C_ERR_INT_MASK) == UI2C_ERR_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_ERRIEN_Msk; + } + + /* Disable acknowledge interrupt flag */ + if((u32Mask & UI2C_ACK_INT_MASK) == UI2C_ACK_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_ACKIEN_Msk; + } +} + +/** + * @brief This function enables the interrupt of USCI_I2C module. + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. It is combination of: + * - \ref UI2C_TO_INT_MASK + * - \ref UI2C_STAR_INT_MASK + * - \ref UI2C_STOR_INT_MASK + * - \ref UI2C_NACK_INT_MASK + * - \ref UI2C_ARBLO_INT_MASK + * - \ref UI2C_ERR_INT_MASK + * - \ref UI2C_ACK_INT_MASK + * @return None + * + * @details The function is used to enable USCI_I2C bus interrupt events. + */ +void UI2C_EnableInt(UI2C_T *ui2c, uint32_t u32Mask) +{ + /* Enable time-out interrupt flag */ + if((u32Mask & UI2C_TO_INT_MASK) == UI2C_TO_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_TOIEN_Msk; + } + + /* Enable start condition received interrupt flag */ + if((u32Mask & UI2C_STAR_INT_MASK) == UI2C_STAR_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_STARIEN_Msk; + } + + /* Enable stop condition received interrupt flag */ + if((u32Mask & UI2C_STOR_INT_MASK) == UI2C_STOR_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_STORIEN_Msk; + } + + /* Enable non-acknowledge interrupt flag */ + if((u32Mask & UI2C_NACK_INT_MASK) == UI2C_NACK_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_NACKIEN_Msk; + } + + /* Enable arbitration lost interrupt flag */ + if((u32Mask & UI2C_ARBLO_INT_MASK) == UI2C_ARBLO_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_ARBLOIEN_Msk; + } + + /* Enable error interrupt flag */ + if((u32Mask & UI2C_ERR_INT_MASK) == UI2C_ERR_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_ERRIEN_Msk; + } + + /* Enable acknowledge interrupt flag */ + if((u32Mask & UI2C_ACK_INT_MASK) == UI2C_ACK_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_ACKIEN_Msk; + } +} + +/** + * @brief This function returns the real bus clock of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return Actual USCI_I2C bus clock frequency. + * + * @details The function returns the actual USCI_I2C module bus clock. + */ +uint32_t UI2C_GetBusClockFreq(UI2C_T *ui2c) +{ + uint32_t u32Divider; + uint32_t u32Pclk; + + if (ui2c == UI2C0) + { + u32Pclk = CLK_GetPCLK0Freq(); + } + else + { + u32Pclk = CLK_GetPCLK1Freq(); + } + + u32Divider = (ui2c->BRGEN & UI2C_BRGEN_CLKDIV_Msk) >> UI2C_BRGEN_CLKDIV_Pos; + + return ( u32Pclk / ((u32Divider+1U)<<1U) ); +} + +/** + * @brief This function sets bus clock frequency of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32BusClock The target bus speed of USCI_I2C module. + * + * @return Actual USCI_I2C bus clock frequency. + * + * @details Use this function set USCI_I2C bus clock frequency and return actual bus clock. + */ +uint32_t UI2C_SetBusClockFreq(UI2C_T *ui2c, uint32_t u32BusClock) +{ + uint32_t u32ClkDiv; + uint32_t u32Pclk; + + if( ui2c == UI2C0 ) + { + u32Pclk = CLK_GetPCLK0Freq(); + } + else + { + u32Pclk = CLK_GetPCLK1Freq(); + } + + u32ClkDiv = (uint32_t) ((((((u32Pclk/2U)*10U)/(u32BusClock))+5U)/10U)-1U); /* Compute proper divider for USCI_I2C clock */ + + /* Set USCI_I2C bus clock */ + ui2c->BRGEN &= ~UI2C_BRGEN_CLKDIV_Msk; + ui2c->BRGEN |= (u32ClkDiv << UI2C_BRGEN_CLKDIV_Pos); + + return ( u32Pclk / ((u32ClkDiv+1U)<<1U) ); +} + +/** + * @brief This function gets the interrupt flag of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. It is combination of: + * - \ref UI2C_TO_INT_MASK + * - \ref UI2C_STAR_INT_MASK + * - \ref UI2C_STOR_INT_MASK + * - \ref UI2C_NACK_INT_MASK + * - \ref UI2C_ARBLO_INT_MASK + * - \ref UI2C_ERR_INT_MASK + * - \ref UI2C_ACK_INT_MASK + * + * @return Interrupt flags of selected sources. + * + * @details Use this function to get USCI_I2C interrupt flag when module occurs interrupt event. + */ +uint32_t UI2C_GetIntFlag(UI2C_T *ui2c, uint32_t u32Mask) +{ + uint32_t u32IntFlag = 0U; + uint32_t u32TmpValue; + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_TOIF_Msk; + /* Check Time-out Interrupt Flag */ + if((u32Mask & UI2C_TO_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_TO_INT_MASK; + } + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_STARIF_Msk; + /* Check Start Condition Received Interrupt Flag */ + if((u32Mask & UI2C_STAR_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_STAR_INT_MASK; + } + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_STORIF_Msk; + /* Check Stop Condition Received Interrupt Flag */ + if((u32Mask & UI2C_STOR_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_STOR_INT_MASK; + } + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_NACKIF_Msk; + /* Check Non-Acknowledge Interrupt Flag */ + if((u32Mask & UI2C_NACK_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_NACK_INT_MASK; + } + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_ARBLOIF_Msk; + /* Check Arbitration Lost Interrupt Flag */ + if((u32Mask & UI2C_ARBLO_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_ARBLO_INT_MASK; + } + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_ERRIF_Msk; + /* Check Error Interrupt Flag */ + if((u32Mask & UI2C_ERR_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_ERR_INT_MASK; + } + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_ACKIF_Msk; + /* Check Acknowledge Interrupt Flag */ + if((u32Mask & UI2C_ACK_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_ACK_INT_MASK; + } + + return u32IntFlag; +} + +/** + * @brief This function clears the interrupt flag of USCI_I2C module. + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. It is combination of: + * - \ref UI2C_TO_INT_MASK + * - \ref UI2C_STAR_INT_MASK + * - \ref UI2C_STOR_INT_MASK + * - \ref UI2C_NACK_INT_MASK + * - \ref UI2C_ARBLO_INT_MASK + * - \ref UI2C_ERR_INT_MASK + * - \ref UI2C_ACK_INT_MASK + * + * @return None + * + * @details Use this function to clear USCI_I2C interrupt flag when module occurs interrupt event and set flag. + */ +void UI2C_ClearIntFlag(UI2C_T *ui2c, uint32_t u32Mask) +{ + /* Clear Time-out Interrupt Flag */ + if(u32Mask & UI2C_TO_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_TOIF_Msk; + } + + /* Clear Start Condition Received Interrupt Flag */ + if(u32Mask & UI2C_STAR_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_STARIF_Msk; + } + + /* Clear Stop Condition Received Interrupt Flag */ + if(u32Mask & UI2C_STOR_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_STORIF_Msk; + } + + /* Clear Non-Acknowledge Interrupt Flag */ + if(u32Mask & UI2C_NACK_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_NACKIF_Msk; + } + + /* Clear Arbitration Lost Interrupt Flag */ + if(u32Mask & UI2C_ARBLO_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_ARBLOIF_Msk; + } + + /* Clear Error Interrupt Flag */ + if(u32Mask & UI2C_ERR_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_ERRIF_Msk; + } + + /* Clear Acknowledge Interrupt Flag */ + if(u32Mask & UI2C_ACK_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_ACKIF_Msk; + } +} + +/** + * @brief This function returns the data stored in data register of USCI_I2C module. + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return USCI_I2C data. + * + * @details To read a byte data from USCI_I2C module receive data register. + */ +uint32_t UI2C_GetData(UI2C_T *ui2c) +{ + return ( ui2c->RXDAT ); +} + +/** + * @brief This function writes a byte data to data register of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8Data The data which will be written to data register of USCI_I2C module. + * + * @return None + * + * @details To write a byte data to transmit data register to transmit data. + */ +void UI2C_SetData(UI2C_T *ui2c, uint8_t u8Data) +{ + ui2c->TXDAT = u8Data; +} + +/** + * @brief Configure slave address and enable GC mode + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveNo Slave channel number [0/1] + * @param[in] u16SlaveAddr The slave address. + * @param[in] u8GCMode GC mode enable or not. Valid values are: + * - \ref UI2C_GCMODE_ENABLE + * - \ref UI2C_GCMODE_DISABLE + * + * @return None + * + * @details To configure USCI_I2C module slave address and GC mode. + */ +void UI2C_SetSlaveAddr(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddr, uint8_t u8GCMode) +{ + if(u8SlaveNo) + { + ui2c->DEVADDR1 = u16SlaveAddr; + } + else + { + ui2c->DEVADDR0 = u16SlaveAddr; + } + + ui2c->PROTCTL = (ui2c->PROTCTL & ~UI2C_PROTCTL_GCFUNC_Msk) |u8GCMode; +} + +/** + * @brief Configure the mask bit of slave address. + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveNo Slave channel number [0/1] + * @param[in] u16SlaveAddrMask The slave address mask. + * + * @return None + * + * @details To configure USCI_I2C module slave address mask bit. + * @note The corresponding address bit is "Don't Care". + */ +void UI2C_SetSlaveAddrMask(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddrMask) +{ + if(u8SlaveNo) + { + ui2c->ADDRMSK1 = u16SlaveAddrMask; + } + else + { + ui2c->ADDRMSK0 = u16SlaveAddrMask; + } +} + +/** + * @brief This function enables time-out function and configures timeout counter + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32TimeoutCnt Timeout counter. Valid values are between 0~0x3FF + * + * @return None + * + * @details To enable USCI_I2C bus time-out function and set time-out counter. + */ +void UI2C_EnableTimeout(UI2C_T *ui2c, uint32_t u32TimeoutCnt) +{ + ui2c->PROTCTL = (ui2c->PROTCTL & ~UI2C_PROTCTL_TOCNT_Msk) | (u32TimeoutCnt << UI2C_PROTCTL_TOCNT_Pos); + ui2c->BRGEN = (ui2c->BRGEN & ~UI2C_BRGEN_TMCNTSRC_Msk) | UI2C_BRGEN_TMCNTEN_Msk; +} + +/** + * @brief This function disables time-out function + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details To disable USCI_I2C bus time-out function. + */ +void UI2C_DisableTimeout(UI2C_T *ui2c) +{ + ui2c->PROTCTL &= ~UI2C_PROTCTL_TOCNT_Msk; + ui2c->BRGEN &= ~UI2C_BRGEN_TMCNTEN_Msk; +} + +/** + * @brief This function enables the wakeup function of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8WakeupMode The wake-up mode selection. Valid values are: + * - \ref UI2C_DATA_TOGGLE_WK + * - \ref UI2C_ADDR_MATCH_WK + * + * @return None + * + * @details To enable USCI_I2C module wake-up function. + */ +void UI2C_EnableWakeup(UI2C_T *ui2c, uint8_t u8WakeupMode) +{ + ui2c->WKCTL = (ui2c->WKCTL & ~UI2C_WKCTL_WKADDREN_Msk) | (u8WakeupMode | UI2C_WKCTL_WKEN_Msk); +} + +/** + * @brief This function disables the wakeup function of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details To disable USCI_I2C module wake-up function. + */ +void UI2C_DisableWakeup(UI2C_T *ui2c) +{ + ui2c->WKCTL &= ~UI2C_WKCTL_WKEN_Msk; +} + +/** + * @brief Write a byte to Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] data Write a byte data to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for USCI_I2C Master write a byte data to Slave. + * + */ + +uint8_t UI2C_WriteByte(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t data) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, u8Ctrl = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, data); /* Write data to UI2C_TXDAT */ + eEvent = MASTER_SEND_DATA; + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + return (u8Err | u8Xfering); /* return (Success)/(Fail) status */ +} + +/** + * @brief Write multi bytes to Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] *data Pointer to array to write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for USCI_I2C Master write multi bytes data to Slave. + * + */ + +uint32_t UI2C_WriteMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t *data, uint32_t u32wLen) +{ + uint8_t u8Xfering = 1U, u8Ctrl = 0U; + uint32_t u32txLen = 0U; + + UI2C_START(ui2c); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (u32txLen < u32wLen) + UI2C_SET_DATA(ui2c, data[u32txLen++]); /* Write data to UI2C_TXDAT */ + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */ + } + + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Specify a byte register address and write a byte to Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 byte) of data write to + * @param[in] data A byte data to write it to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for USCI_I2C Master specify a address that data write to in Slave. + * + */ + +uint8_t UI2C_WriteByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, u8Ctrl = 0U; + uint32_t u32txLen = 0U; + + UI2C_START(ui2c); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (u32txLen == 0U) + { + UI2C_SET_DATA(ui2c, u8DataAddr); /* Write data address to UI2C_TXDAT */ + u32txLen++; + } + else if (u32txLen == 1U) + { + UI2C_SET_DATA(ui2c, data); /* Write data to UI2C_TXDAT */ + u32txLen++; + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */ + } + + return (u8Err | u8Xfering); /* return (Success)/(Fail) status */ +} + + +/** + * @brief Specify a byte register address and write multi bytes to Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 byte) of data write to + * @param[in] *data Pointer to array to write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for USCI_I2C Master specify a byte address that multi data bytes write to in Slave. + * + */ + +uint32_t UI2C_WriteMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t *data, uint32_t u32wLen) +{ + uint8_t u8Xfering = 1U, u8Ctrl = 0U; + uint32_t u32txLen = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, u8DataAddr); /* Write data address to UI2C_TXDAT */ + eEvent = MASTER_SEND_DATA; + } + else + { + if (u32txLen < u32wLen) + UI2C_SET_DATA(ui2c, data[u32txLen++]); /* Write data to UI2C_TXDAT */ + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */ + } + + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Specify two bytes register address and Write a byte to Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 byte) of data write to + * @param[in] data Write a byte data to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for USCI_I2C Master specify two bytes address that data write to in Slave. + * + */ + +uint8_t UI2C_WriteByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, u8Ctrl = 0U; + uint32_t u32txLen = 0U; + + UI2C_START(ui2c); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (u32txLen == 0U) + { + UI2C_SET_DATA(ui2c, (uint8_t)((u16DataAddr & 0xFF00U) >> 8U)); /* Write Hi byte data address to UI2C_TXDAT */ + u32txLen++; + } + else if (u32txLen == 1U) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte data address to UI2C_TXDAT */ + u32txLen++; + } + else if (u32txLen == 2U) + { + UI2C_SET_DATA(ui2c, data); /* Write data to UI2C_TXDAT */ + u32txLen++; + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */ + } + + return (u8Err | u8Xfering); +} + + +/** + * @brief Specify two bytes register address and write multi bytes to Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 bytes) of data write to + * @param[in] *data Pointer to array to write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for USCI_I2C Master specify a byte address that multi data write to in Slave. + * + */ + +uint32_t UI2C_WriteMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t *data, uint32_t u32wLen) +{ + uint8_t u8Xfering = 1U, u8Addr = 1U, u8Ctrl = 0U; + uint32_t u32txLen = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, (uint8_t)((u16DataAddr & 0xFF00U) >> 8U)); /* Write Hi byte data address to UI2C_TXDAT */ + eEvent = MASTER_SEND_DATA; + } + else if (eEvent == MASTER_SEND_DATA) + { + if (u8Addr) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte data address to UI2C_TXDAT */ + u8Addr = 0; + } + else + { + if (u32txLen < u32wLen) + { + UI2C_SET_DATA(ui2c, data[u32txLen++]); /* Write data to UI2C_TXDAT */ + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + } + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */ + } + + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Read a byte from Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * + * @return Read a byte data from Slave + * + * @details The function is used for USCI_I2C Master to read a byte data from Slave. + * + */ +uint8_t UI2C_ReadByte(UI2C_T *ui2c, uint8_t u8SlaveAddr) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, rdata = 0U, u8Ctrl = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + eEvent = MASTER_READ_DATA; + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if (eEvent == MASTER_SEND_H_RD_ADDRESS) + { + u8Err = 1U; + } + else + { + rdata = (unsigned char) UI2C_GET_DATA(ui2c); /* Receive Data */ + } + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + if (u8Err) + rdata = 0U; + + return rdata; /* Return read data */ +} + + +/** + * @brief Read multi bytes from Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[out] *rdata Point to array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for USCI_I2C Master to read multi data bytes from Slave. + * + * + */ +uint32_t UI2C_ReadMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t *rdata, uint32_t u32rLen) +{ + uint8_t u8Xfering = 1U, u8Ctrl = 0U; + uint32_t u32rxLen = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_H_RD_ADDRESS) + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + eEvent = MASTER_READ_DATA; + } + else + { + rdata[u32rxLen++] = (unsigned char) UI2C_GET_DATA(ui2c); /* Receive Data */ + + if (u32rxLen < (u32rLen - 1U)) + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + else + u8Ctrl = UI2C_CTL_PTRG; + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if (eEvent == MASTER_READ_DATA) + rdata[u32rxLen++] = (unsigned char) UI2C_GET_DATA(ui2c); /* Receive Data */ + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + return u32rxLen; /* Return bytes length that have been received */ +} + + +/** + * @brief Specify a byte register address and read a byte from Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address(1 byte) of data read from + * + * @return Read a byte data from Slave + * + * @details The function is used for USCI_I2C Master specify a byte address that a data byte read from Slave. + * + * + */ +uint8_t UI2C_ReadByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, rdata = 0U, u8Ctrl = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + + if (eEvent == MASTER_SEND_START) + { + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + } + else if (eEvent == MASTER_SEND_REPEAT_START) + { + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + } + + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, u8DataAddr); /* Write data address of register */ + u8Ctrl = UI2C_CTL_PTRG; + eEvent = MASTER_SEND_DATA; + } + else if (eEvent == MASTER_SEND_DATA) + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA); /* Send repeat START signal */ + eEvent = MASTER_SEND_REPEAT_START; + } + else + { + /* SLA+R ACK */ + u8Ctrl = UI2C_CTL_PTRG; + eEvent = MASTER_READ_DATA; + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if (eEvent == MASTER_READ_DATA) + { + rdata = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */ + } + else + { + u8Err = 1U; + } + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + if (u8Err) + rdata = 0U; /* If occurs error, return 0 */ + + return rdata; /* Return read data */ +} + +/** + * @brief Specify a byte register address and read multi bytes from Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 bytes) of data read from + * @param[out] *rdata Point to array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for USCI_I2C Master specify a byte address that multi data bytes read from Slave. + * + * + */ +uint32_t UI2C_ReadMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t *rdata, uint32_t u32rLen) +{ + uint8_t u8Xfering = 1U, u8Ctrl = 0U; + uint32_t u32rxLen = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + + if (eEvent == MASTER_SEND_START) + { + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + } + else if (eEvent == MASTER_SEND_REPEAT_START) + { + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + } + + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, u8DataAddr); /* Write data address of register */ + u8Ctrl = UI2C_CTL_PTRG; + eEvent = MASTER_SEND_DATA; + } + else if (eEvent == MASTER_SEND_DATA) + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA); /* Send repeat START signal */ + eEvent = MASTER_SEND_REPEAT_START; + } + else if (eEvent == MASTER_SEND_H_RD_ADDRESS) + { + /* SLA+R ACK */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + eEvent = MASTER_READ_DATA; + } + else + { + rdata[u32rxLen++] = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */ + + if (u32rxLen < u32rLen - 1U) + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + else + u8Ctrl = UI2C_CTL_PTRG; + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if (eEvent == MASTER_READ_DATA) + rdata[u32rxLen++] = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */ + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + return u32rxLen; /* Return bytes length that have been received */ +} + +/** + * @brief Specify two bytes register address and read a byte from Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address(2 byte) of data read from + * + * @return Read a byte data from Slave + * + * @details The function is used for USCI_I2C Master specify two bytes address that a data byte read from Slave. + * + * + */ +uint8_t UI2C_ReadByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, rdata = 0U, u8Addr = 1U, u8Ctrl = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + + if (eEvent == MASTER_SEND_START) + { + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + } + else if (eEvent == MASTER_SEND_REPEAT_START) + { + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + } + + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, (uint8_t)((u16DataAddr & 0xFF00U) >> 8U)); /* Write Hi byte address of register */ + eEvent = MASTER_SEND_DATA; + } + else if (eEvent == MASTER_SEND_DATA) + { + if (u8Addr) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte address of register */ + u8Addr = 0; + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA); /* Send repeat START signal */ + eEvent = MASTER_SEND_REPEAT_START; + } + } + else + { + /* SLA+R ACK */ + u8Ctrl = UI2C_CTL_PTRG; + eEvent = MASTER_READ_DATA; + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if (eEvent == MASTER_READ_DATA) + { + rdata = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */ + } + else + { + u8Err = 1U; + } + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + if (u8Err) + rdata = 0U; /* If occurs error, return 0 */ + + return rdata; /* Return read data */ +} + +/** + * @brief Specify two bytes register address and read multi bytes from Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 bytes) of data read from + * @param[out] *rdata Point to array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for USCI_I2C Master specify two bytes address that multi data bytes read from Slave. + * + * + */ +uint32_t UI2C_ReadMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t *rdata, uint32_t u32rLen) +{ + uint8_t u8Xfering = 1U, u8Addr = 1U, u8Ctrl = 0U; + uint32_t u32rxLen = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + + if (eEvent == MASTER_SEND_START) + { + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + } + else if (eEvent == MASTER_SEND_REPEAT_START) + { + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + } + + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, (uint8_t)((u16DataAddr & 0xFF00U) >> 8U)); /* Write Hi byte address of register */ + eEvent = MASTER_SEND_DATA; + } + else if (eEvent == MASTER_SEND_DATA) + { + if (u8Addr) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte address of register */ + u8Addr = 0; + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA); /* Send repeat START signal */ + eEvent = MASTER_SEND_REPEAT_START; + } + } + else if (eEvent == MASTER_SEND_H_RD_ADDRESS) + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + eEvent = MASTER_READ_DATA; + } + else + { + rdata[u32rxLen++] = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */ + + if (u32rxLen < u32rLen - 1U) + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + else + u8Ctrl = UI2C_CTL_PTRG; + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if (eEvent == MASTER_READ_DATA) + rdata[u32rxLen++] = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */ + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + return u32rxLen; /* Return bytes length that have been received */ +} + +/*@}*/ /* end of group USCI_I2C_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USCI_I2C_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_usci_spi.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_usci_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..69744f4644acdeffaa2d47dd6524a284c1064378 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_usci_spi.c @@ -0,0 +1,664 @@ +/****************************************************************************//** + * @file usci_spi.c + * @version V3.00 + * @brief M480 series USCI_SPI driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_SPI_Driver USCI_SPI Driver + @{ +*/ + + +/** @addtogroup USCI_SPI_EXPORTED_FUNCTIONS USCI_SPI Exported Functions + @{ +*/ + +/** + * @brief This function make USCI_SPI module be ready to transfer. + * By default, the USCI_SPI transfer sequence is MSB first, the slave selection + * signal is active low and the automatic slave select function is disabled. In + * Slave mode, the u32BusClock must be NULL and the USCI_SPI clock + * divider setting will be 0. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32MasterSlave Decide the USCI_SPI module is operating in master mode or in slave mode. Valid values are: + * - \ref USPI_SLAVE + * - \ref USPI_MASTER + * @param[in] u32SPIMode Decide the transfer timing. Valid values are: + * - \ref USPI_MODE_0 + * - \ref USPI_MODE_1 + * - \ref USPI_MODE_2 + * - \ref USPI_MODE_3 + * @param[in] u32DataWidth The data width of a USCI_SPI transaction. + * @param[in] u32BusClock The expected frequency of USCI_SPI bus clock in Hz. + * @return Actual frequency of USCI_SPI peripheral clock. + */ +uint32_t USPI_Open(USPI_T *uspi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock) +{ + uint32_t u32ClkDiv = 0ul; + uint32_t u32Pclk; + uint32_t u32UspiClk = 0ul; + + if(uspi == (USPI_T *)USPI0) + { + u32Pclk = CLK_GetPCLK0Freq(); + } + else + { + u32Pclk = CLK_GetPCLK1Freq(); + } + + if(u32BusClock != 0ul) + { + u32ClkDiv = (uint32_t) ((((((u32Pclk/2ul)*10ul)/(u32BusClock))+5ul)/10ul)-1ul); /* Compute proper divider for USCI_SPI clock */ + } + else {} + + /* Enable USCI_SPI protocol */ + uspi->CTL &= ~USPI_CTL_FUNMODE_Msk; + uspi->CTL = 1ul << USPI_CTL_FUNMODE_Pos; + + /* Data format configuration */ + if(u32DataWidth == 16ul) + { + u32DataWidth = 0ul; + } + else {} + uspi->LINECTL &= ~USPI_LINECTL_DWIDTH_Msk; + uspi->LINECTL |= (u32DataWidth << USPI_LINECTL_DWIDTH_Pos); + + /* MSB data format */ + uspi->LINECTL &= ~USPI_LINECTL_LSB_Msk; + + /* Set slave selection signal active low */ + if(u32MasterSlave == USPI_MASTER) + { + uspi->LINECTL |= USPI_LINECTL_CTLOINV_Msk; + } + else + { + uspi->CTLIN0 |= USPI_CTLIN0_ININV_Msk; + } + + /* Set operating mode and transfer timing */ + uspi->PROTCTL &= ~(USPI_PROTCTL_SCLKMODE_Msk | USPI_PROTCTL_AUTOSS_Msk | USPI_PROTCTL_SLAVE_Msk); + uspi->PROTCTL |= (u32MasterSlave | u32SPIMode); + + /* Set USCI_SPI bus clock */ + uspi->BRGEN &= ~USPI_BRGEN_CLKDIV_Msk; + uspi->BRGEN |= (u32ClkDiv << USPI_BRGEN_CLKDIV_Pos); + uspi->PROTCTL |= USPI_PROTCTL_PROTEN_Msk; + + if(u32BusClock != 0ul) + { + u32UspiClk = (uint32_t)( u32Pclk / ((u32ClkDiv+1ul)<<1) ); + } + else {} + + return u32UspiClk; +} + +/** + * @brief Disable USCI_SPI function mode. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_Close(USPI_T *uspi) +{ + uspi->CTL &= ~USPI_CTL_FUNMODE_Msk; +} + +/** + * @brief Clear Rx buffer. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_ClearRxBuf(USPI_T *uspi) +{ + uspi->BUFCTL |= USPI_BUFCTL_RXCLR_Msk; +} + +/** + * @brief Clear Tx buffer. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_ClearTxBuf(USPI_T *uspi) +{ + uspi->BUFCTL |= USPI_BUFCTL_TXCLR_Msk; +} + +/** + * @brief Disable the automatic slave select function. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_DisableAutoSS(USPI_T *uspi) +{ + uspi->PROTCTL &= ~(USPI_PROTCTL_AUTOSS_Msk | USPI_PROTCTL_SS_Msk); +} + +/** + * @brief Enable the automatic slave select function. Only available in Master mode. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32SSPinMask This parameter is not used. + * @param[in] u32ActiveLevel The active level of slave select signal. Valid values are: + * - \ref USPI_SS_ACTIVE_HIGH + * - \ref USPI_SS_ACTIVE_LOW + * @return None + */ +void USPI_EnableAutoSS(USPI_T *uspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel) +{ + uspi->LINECTL = (uspi->LINECTL & ~USPI_LINECTL_CTLOINV_Msk) | u32ActiveLevel; + uspi->PROTCTL |= USPI_PROTCTL_AUTOSS_Msk; +} + +/** + * @brief Set the USCI_SPI bus clock. Only available in Master mode. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32BusClock The expected frequency of USCI_SPI bus clock. + * @return Actual frequency of USCI_SPI peripheral clock. + */ +uint32_t USPI_SetBusClock(USPI_T *uspi, uint32_t u32BusClock) +{ + uint32_t u32ClkDiv; + uint32_t u32Pclk; + + if(uspi == USPI0) + { + u32Pclk = CLK_GetPCLK0Freq(); + } + else + { + u32Pclk = CLK_GetPCLK1Freq(); + } + + u32ClkDiv = (uint32_t) ((((((u32Pclk/2ul)*10ul)/(u32BusClock))+5ul)/10ul)-1ul); /* Compute proper divider for USCI_SPI clock */ + + /* Set USCI_SPI bus clock */ + uspi->BRGEN &= ~USPI_BRGEN_CLKDIV_Msk; + uspi->BRGEN |= (u32ClkDiv << USPI_BRGEN_CLKDIV_Pos); + + return ( u32Pclk / ((u32ClkDiv+1ul)<<1) ); +} + +/** + * @brief Get the actual frequency of USCI_SPI bus clock. Only available in Master mode. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return Actual USCI_SPI bus clock frequency. + */ +uint32_t USPI_GetBusClock(USPI_T *uspi) +{ + uint32_t u32BusClk; + uint32_t u32ClkDiv; + + u32ClkDiv = (uspi->BRGEN & USPI_BRGEN_CLKDIV_Msk) >> USPI_BRGEN_CLKDIV_Pos; + + if(uspi == USPI0) + { + u32BusClk = (uint32_t)( CLK_GetPCLK0Freq() / ((u32ClkDiv+1ul)<<1) ); + } + else + { + u32BusClk = (uint32_t)( CLK_GetPCLK1Freq() / ((u32ClkDiv+1ul)<<1) ); + } + + return u32BusClk; +} + +/** + * @brief Enable related interrupts specified by u32Mask parameter. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * This parameter decides which interrupts will be enabled. Valid values are: + * - \ref USPI_SSINACT_INT_MASK + * - \ref USPI_SSACT_INT_MASK + * - \ref USPI_SLVTO_INT_MASK + * - \ref USPI_SLVBE_INT_MASK + * - \ref USPI_TXUDR_INT_MASK + * - \ref USPI_RXOV_INT_MASK + * - \ref USPI_TXST_INT_MASK + * - \ref USPI_TXEND_INT_MASK + * - \ref USPI_RXST_INT_MASK + * - \ref USPI_RXEND_INT_MASK + * @return None + */ +void USPI_EnableInt(USPI_T *uspi, uint32_t u32Mask) +{ + /* Enable slave selection signal inactive interrupt flag */ + if((u32Mask & USPI_SSINACT_INT_MASK) == USPI_SSINACT_INT_MASK) + { + uspi->PROTIEN |= USPI_PROTIEN_SSINAIEN_Msk; + } + else {} + /* Enable slave selection signal active interrupt flag */ + if((u32Mask & USPI_SSACT_INT_MASK) == USPI_SSACT_INT_MASK) + { + uspi->PROTIEN |= USPI_PROTIEN_SSACTIEN_Msk; + } + else {} + /* Enable slave time-out interrupt flag */ + if((u32Mask & USPI_SLVTO_INT_MASK) == USPI_SLVTO_INT_MASK) + { + uspi->PROTIEN |= USPI_PROTIEN_SLVTOIEN_Msk; + } + else {} + + /* Enable slave bit count error interrupt flag */ + if((u32Mask & USPI_SLVBE_INT_MASK) == USPI_SLVBE_INT_MASK) + { + uspi->PROTIEN |= USPI_PROTIEN_SLVBEIEN_Msk; + } + else {} + /* Enable TX under run interrupt flag */ + if((u32Mask & USPI_TXUDR_INT_MASK) == USPI_TXUDR_INT_MASK) + { + uspi->BUFCTL |= USPI_BUFCTL_TXUDRIEN_Msk; + } + else {} + /* Enable RX overrun interrupt flag */ + if((u32Mask & USPI_RXOV_INT_MASK) == USPI_RXOV_INT_MASK) + { + uspi->BUFCTL |= USPI_BUFCTL_RXOVIEN_Msk; + } + else {} + /* Enable TX start interrupt flag */ + if((u32Mask & USPI_TXST_INT_MASK) == USPI_TXST_INT_MASK) + { + uspi->INTEN |= USPI_INTEN_TXSTIEN_Msk; + } + else {} + /* Enable TX end interrupt flag */ + if((u32Mask & USPI_TXEND_INT_MASK) == USPI_TXEND_INT_MASK) + { + uspi->INTEN |= USPI_INTEN_TXENDIEN_Msk; + } + else {} + /* Enable RX start interrupt flag */ + if((u32Mask & USPI_RXST_INT_MASK) == USPI_RXST_INT_MASK) + { + uspi->INTEN |= USPI_INTEN_RXSTIEN_Msk; + } + else {} + /* Enable RX end interrupt flag */ + if((u32Mask & USPI_RXEND_INT_MASK) == USPI_RXEND_INT_MASK) + { + uspi->INTEN |= USPI_INTEN_RXENDIEN_Msk; + } + else {} +} + +/** + * @brief Disable related interrupts specified by u32Mask parameter. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * This parameter decides which interrupts will be disabled. Valid values are: + * - \ref USPI_SSINACT_INT_MASK + * - \ref USPI_SSACT_INT_MASK + * - \ref USPI_SLVTO_INT_MASK + * - \ref USPI_SLVBE_INT_MASK + * - \ref USPI_TXUDR_INT_MASK + * - \ref USPI_RXOV_INT_MASK + * - \ref USPI_TXST_INT_MASK + * - \ref USPI_TXEND_INT_MASK + * - \ref USPI_RXST_INT_MASK + * - \ref USPI_RXEND_INT_MASK + * @return None + */ +void USPI_DisableInt(USPI_T *uspi, uint32_t u32Mask) +{ + /* Disable slave selection signal inactive interrupt flag */ + if((u32Mask & USPI_SSINACT_INT_MASK) == USPI_SSINACT_INT_MASK) + { + uspi->PROTIEN &= ~USPI_PROTIEN_SSINAIEN_Msk; + } + else {} + /* Disable slave selection signal active interrupt flag */ + if((u32Mask & USPI_SSACT_INT_MASK) == USPI_SSACT_INT_MASK) + { + uspi->PROTIEN &= ~USPI_PROTIEN_SSACTIEN_Msk; + } + else {} + /* Disable slave time-out interrupt flag */ + if((u32Mask & USPI_SLVTO_INT_MASK) == USPI_SLVTO_INT_MASK) + { + uspi->PROTIEN &= ~USPI_PROTIEN_SLVTOIEN_Msk; + } + else {} + /* Disable slave bit count error interrupt flag */ + if((u32Mask & USPI_SLVBE_INT_MASK) == USPI_SLVBE_INT_MASK) + { + uspi->PROTIEN &= ~USPI_PROTIEN_SLVBEIEN_Msk; + } + else {} + /* Disable TX under run interrupt flag */ + if((u32Mask & USPI_TXUDR_INT_MASK) == USPI_TXUDR_INT_MASK) + { + uspi->BUFCTL &= ~USPI_BUFCTL_TXUDRIEN_Msk; + } + else {} + /* Disable RX overrun interrupt flag */ + if((u32Mask & USPI_RXOV_INT_MASK) == USPI_RXOV_INT_MASK) + { + uspi->BUFCTL &= ~USPI_BUFCTL_RXOVIEN_Msk; + } + else {} + /* Disable TX start interrupt flag */ + if((u32Mask & USPI_TXST_INT_MASK) == USPI_TXST_INT_MASK) + { + uspi->INTEN &= ~USPI_INTEN_TXSTIEN_Msk; + } + else {} + /* Disable TX end interrupt flag */ + if((u32Mask & USPI_TXEND_INT_MASK) == USPI_TXEND_INT_MASK) + { + uspi->INTEN &= ~USPI_INTEN_TXENDIEN_Msk; + } + else {} + /* Disable RX start interrupt flag */ + if((u32Mask & USPI_RXST_INT_MASK) == USPI_RXST_INT_MASK) + { + uspi->INTEN &= ~USPI_INTEN_RXSTIEN_Msk; + } + else {} + /* Disable RX end interrupt flag */ + if((u32Mask & USPI_RXEND_INT_MASK) == USPI_RXEND_INT_MASK) + { + uspi->INTEN &= ~USPI_INTEN_RXENDIEN_Msk; + } + else {} +} + +/** + * @brief Get interrupt flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. It is combination of: + * - \ref USPI_SSINACT_INT_MASK + * - \ref USPI_SSACT_INT_MASK + * - \ref USPI_SLVTO_INT_MASK + * - \ref USPI_SLVBE_INT_MASK + * - \ref USPI_TXUDR_INT_MASK + * - \ref USPI_RXOV_INT_MASK + * - \ref USPI_TXST_INT_MASK + * - \ref USPI_TXEND_INT_MASK + * - \ref USPI_RXST_INT_MASK + * - \ref USPI_RXEND_INT_MASK + * @return Interrupt flags of selected sources. + */ +uint32_t USPI_GetIntFlag(USPI_T *uspi, uint32_t u32Mask) +{ + uint32_t u32TmpFlag; + uint32_t u32IntFlag = 0ul; + + /* Check slave selection signal inactive interrupt flag */ + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SSINAIF_Msk; + if(((u32Mask & USPI_SSINACT_INT_MASK)==USPI_SSINACT_INT_MASK) && (u32TmpFlag==USPI_PROTSTS_SSINAIF_Msk) ) + { + u32IntFlag |= USPI_SSINACT_INT_MASK; + } + else {} + /* Check slave selection signal active interrupt flag */ + + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SSACTIF_Msk; + if(((u32Mask & USPI_SSACT_INT_MASK)==USPI_SSACT_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_SSACTIF_Msk)) + { + u32IntFlag |= USPI_SSACT_INT_MASK; + } + else {} + + /* Check slave time-out interrupt flag */ + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SLVTOIF_Msk; + if(((u32Mask & USPI_SLVTO_INT_MASK)==USPI_SLVTO_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_SLVTOIF_Msk)) + { + u32IntFlag |= USPI_SLVTO_INT_MASK; + } + else {} + + /* Check slave bit count error interrupt flag */ + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SLVBEIF_Msk; + if(((u32Mask & USPI_SLVBE_INT_MASK)==USPI_SLVBE_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_SLVBEIF_Msk)) + { + u32IntFlag |= USPI_SLVBE_INT_MASK; + } + else {} + + /* Check TX under run interrupt flag */ + u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_TXUDRIF_Msk; + if(((u32Mask & USPI_TXUDR_INT_MASK)==USPI_TXUDR_INT_MASK) && (u32TmpFlag == USPI_BUFSTS_TXUDRIF_Msk)) + { + u32IntFlag |= USPI_TXUDR_INT_MASK; + } + else {} + + /* Check RX overrun interrupt flag */ + u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_RXOVIF_Msk; + if(((u32Mask & USPI_RXOV_INT_MASK)==USPI_RXOV_INT_MASK) && (u32TmpFlag == USPI_BUFSTS_RXOVIF_Msk)) + { + u32IntFlag |= USPI_RXOV_INT_MASK; + } + else {} + + /* Check TX start interrupt flag */ + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_TXSTIF_Msk; + if(((u32Mask & USPI_TXST_INT_MASK)==USPI_TXST_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_TXSTIF_Msk)) + { + u32IntFlag |= USPI_TXST_INT_MASK; + } + else {} + + /* Check TX end interrupt flag */ + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_TXENDIF_Msk; + if(((u32Mask & USPI_TXEND_INT_MASK)==USPI_TXEND_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_TXENDIF_Msk)) + { + u32IntFlag |= USPI_TXEND_INT_MASK; + } + else {} + + /* Check RX start interrupt flag */ + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_RXSTIF_Msk; + if(((u32Mask & USPI_RXST_INT_MASK)==USPI_RXST_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_RXSTIF_Msk)) + { + u32IntFlag |= USPI_RXST_INT_MASK; + } + else {} + + /* Check RX end interrupt flag */ + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_RXENDIF_Msk; + if(((u32Mask & USPI_RXEND_INT_MASK)==USPI_RXEND_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_RXENDIF_Msk)) + { + u32IntFlag |= USPI_RXEND_INT_MASK; + } + else {} + return u32IntFlag; +} + +/** + * @brief Clear interrupt flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. It could be the combination of: + * - \ref USPI_SSINACT_INT_MASK + * - \ref USPI_SSACT_INT_MASK + * - \ref USPI_SLVTO_INT_MASK + * - \ref USPI_SLVBE_INT_MASK + * - \ref USPI_TXUDR_INT_MASK + * - \ref USPI_RXOV_INT_MASK + * - \ref USPI_TXST_INT_MASK + * - \ref USPI_TXEND_INT_MASK + * - \ref USPI_RXST_INT_MASK + * - \ref USPI_RXEND_INT_MASK + * @return None + */ +void USPI_ClearIntFlag(USPI_T *uspi, uint32_t u32Mask) +{ + /* Clear slave selection signal inactive interrupt flag */ + if((u32Mask & USPI_SSINACT_INT_MASK)==USPI_SSINACT_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_SSINAIF_Msk; + } + else {} + /* Clear slave selection signal active interrupt flag */ + if((u32Mask & USPI_SSACT_INT_MASK)==USPI_SSACT_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_SSACTIF_Msk; + } + else {} + /* Clear slave time-out interrupt flag */ + if((u32Mask & USPI_SLVTO_INT_MASK)==USPI_SLVTO_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_SLVTOIF_Msk; + } + else {} + /* Clear slave bit count error interrupt flag */ + if((u32Mask & USPI_SLVBE_INT_MASK)==USPI_SLVBE_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_SLVBEIF_Msk; + } + else {} + /* Clear TX under run interrupt flag */ + if((u32Mask & USPI_TXUDR_INT_MASK)==USPI_TXUDR_INT_MASK) + { + uspi->BUFSTS = USPI_BUFSTS_TXUDRIF_Msk; + } + else {} + /* Clear RX overrun interrupt flag */ + if((u32Mask & USPI_RXOV_INT_MASK)==USPI_RXOV_INT_MASK) + { + uspi->BUFSTS = USPI_BUFSTS_RXOVIF_Msk; + } + else {} + /* Clear TX start interrupt flag */ + if((u32Mask & USPI_TXST_INT_MASK)==USPI_TXST_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_TXSTIF_Msk; + } + else {} + /* Clear TX end interrupt flag */ + if((u32Mask & USPI_TXEND_INT_MASK)==USPI_TXEND_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_TXENDIF_Msk; + } + else {} + /* Clear RX start interrupt flag */ + if((u32Mask & USPI_RXST_INT_MASK)==USPI_RXST_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_RXSTIF_Msk; + } + else {} + + /* Clear RX end interrupt flag */ + if((u32Mask & USPI_RXEND_INT_MASK)==USPI_RXEND_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_RXENDIF_Msk; + } + else {} +} + +/** + * @brief Get USCI_SPI status. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32Mask The combination of all related sources. + * Each bit corresponds to a source. + * This parameter decides which flags will be read. It is combination of: + * - \ref USPI_BUSY_MASK + * - \ref USPI_RX_EMPTY_MASK + * - \ref USPI_RX_FULL_MASK + * - \ref USPI_TX_EMPTY_MASK + * - \ref USPI_TX_FULL_MASK + * - \ref USPI_SSLINE_STS_MASK + * @return Flags of selected sources. + */ +uint32_t USPI_GetStatus(USPI_T *uspi, uint32_t u32Mask) +{ + uint32_t u32Flag = 0ul; + uint32_t u32TmpFlag; + + /* Check busy status */ + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_BUSY_Msk; + if(((u32Mask & USPI_BUSY_MASK)==USPI_BUSY_MASK) && (u32TmpFlag & USPI_PROTSTS_BUSY_Msk)) + { + u32Flag |= USPI_BUSY_MASK; + } + else {} + + /* Check RX empty flag */ + u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_RXEMPTY_Msk; + if(((u32Mask & USPI_RX_EMPTY_MASK)==USPI_RX_EMPTY_MASK) && (u32TmpFlag == USPI_BUFSTS_RXEMPTY_Msk)) + { + u32Flag |= USPI_RX_EMPTY_MASK; + } + else {} + + /* Check RX full flag */ + u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_RXFULL_Msk; + if(((u32Mask & USPI_RX_FULL_MASK)==USPI_RX_FULL_MASK) && (u32TmpFlag == USPI_BUFSTS_RXFULL_Msk)) + { + u32Flag |= USPI_RX_FULL_MASK; + } + else {} + + /* Check TX empty flag */ + u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_TXEMPTY_Msk; + if(((u32Mask & USPI_TX_EMPTY_MASK)==USPI_TX_EMPTY_MASK) && (u32TmpFlag == USPI_BUFSTS_TXEMPTY_Msk)) + { + u32Flag |= USPI_TX_EMPTY_MASK; + } + else {} + + /* Check TX full flag */ + u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_TXFULL_Msk; + if(((u32Mask & USPI_TX_FULL_MASK)==USPI_TX_FULL_MASK) && (u32TmpFlag == USPI_BUFSTS_TXFULL_Msk)) + { + u32Flag |= USPI_TX_FULL_MASK; + } + else {} + + /* Check USCI_SPI_SS line status */ + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SSLINE_Msk; + if(((u32Mask & USPI_SSLINE_STS_MASK)==USPI_SSLINE_STS_MASK) && (u32TmpFlag & USPI_PROTSTS_SSLINE_Msk)) + { + u32Flag |= USPI_SSLINE_STS_MASK; + } + else {} + return u32Flag; +} + +/** + * @brief Enable USCI_SPI Wake-up Function. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_EnableWakeup(USPI_T *uspi) +{ + uspi->WKCTL |= USPI_WKCTL_WKEN_Msk; +} + +/** + * @brief Disable USCI_SPI Wake-up Function. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_DisableWakeup(USPI_T *uspi) +{ + uspi->WKCTL &= ~USPI_WKCTL_WKEN_Msk; +} + +/*@}*/ /* end of group USCI_SPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USCI_SPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_usci_uart.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_usci_uart.c new file mode 100644 index 0000000000000000000000000000000000000000..94c1fc99aec233620d73c9754a774904972d22f5 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_usci_uart.c @@ -0,0 +1,702 @@ +/**************************************************************************//** + * @file usci_uart.c + * @version V3.00 + * @brief M480 series USCI UART (UUART) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_UART_Driver USCI_UART Driver + @{ +*/ + +/** @addtogroup USCI_UART_EXPORTED_FUNCTIONS USCI_UART Exported Functions + @{ +*/ + +/** + * @brief Clear USCI_UART specified interrupt flag + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. It could be the combination of: + * - \ref UUART_ABR_INT_MASK + * - \ref UUART_RLS_INT_MASK + * - \ref UUART_BUF_RXOV_INT_MASK + * - \ref UUART_TXST_INT_MASK + * - \ref UUART_TXEND_INT_MASK + * - \ref UUART_RXST_INT_MASK + * - \ref UUART_RXEND_INT_MASK + * + * @return None + * + * @details The function is used to clear USCI_UART related interrupt flags specified by u32Mask parameter. + */ + +void UUART_ClearIntFlag(UUART_T* uuart, uint32_t u32Mask) +{ + + if(u32Mask & UUART_ABR_INT_MASK) /* Clear Auto-baud Rate Interrupt */ + { + uuart->PROTSTS = UUART_PROTSTS_ABRDETIF_Msk; + } + + if(u32Mask & UUART_RLS_INT_MASK) /* Clear Receive Line Status Interrupt */ + { + uuart->PROTSTS = (UUART_PROTSTS_BREAK_Msk | UUART_PROTSTS_FRMERR_Msk | UUART_PROTSTS_PARITYERR_Msk); + } + + if(u32Mask & UUART_BUF_RXOV_INT_MASK) /* Clear Receive Buffer Over-run Error Interrupt */ + { + uuart->BUFSTS = UUART_BUFSTS_RXOVIF_Msk; + } + + if(u32Mask & UUART_TXST_INT_MASK) /* Clear Transmit Start Interrupt */ + { + uuart->PROTSTS = UUART_PROTSTS_TXSTIF_Msk; + } + + if(u32Mask & UUART_TXEND_INT_MASK) /* Clear Transmit End Interrupt */ + { + uuart->PROTSTS = UUART_PROTSTS_TXENDIF_Msk; + } + + if(u32Mask & UUART_RXST_INT_MASK) /* Clear Receive Start Interrupt */ + { + uuart->PROTSTS = UUART_PROTSTS_RXSTIF_Msk; + } + + if(u32Mask & UUART_RXEND_INT_MASK) /* Clear Receive End Interrupt */ + { + uuart->PROTSTS = UUART_PROTSTS_RXENDIF_Msk; + } + +} + +/** + * @brief Get USCI_UART specified interrupt flag + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. It is combination of: + * - \ref UUART_ABR_INT_MASK + * - \ref UUART_RLS_INT_MASK + * - \ref UUART_BUF_RXOV_INT_MASK + * - \ref UUART_TXST_INT_MASK + * - \ref UUART_TXEND_INT_MASK + * - \ref UUART_RXST_INT_MASK + * - \ref UUART_RXEND_INT_MASK + * + * @return Interrupt flags of selected sources. + * + * @details The function is used to get USCI_UART related interrupt flags specified by u32Mask parameter. + */ + +uint32_t UUART_GetIntFlag(UUART_T* uuart, uint32_t u32Mask) +{ + uint32_t u32IntFlag = 0ul; + uint32_t u32Tmp1, u32Tmp2; + + /* Check Auto-baud Rate Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_ABR_INT_MASK); + u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_ABRDETIF_Msk); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_ABR_INT_MASK; + } + + /* Check Receive Line Status Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_RLS_INT_MASK); + u32Tmp2 = (uuart->PROTSTS & (UUART_PROTSTS_BREAK_Msk | UUART_PROTSTS_FRMERR_Msk | UUART_PROTSTS_PARITYERR_Msk)); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_RLS_INT_MASK; + } + + /* Check Receive Buffer Over-run Error Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_BUF_RXOV_INT_MASK); + u32Tmp2 = (uuart->BUFSTS & UUART_BUFSTS_RXOVIF_Msk); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_BUF_RXOV_INT_MASK; + } + + /* Check Transmit Start Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_TXST_INT_MASK); + u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_TXSTIF_Msk); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_TXST_INT_MASK; + } + + /* Check Transmit End Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_TXEND_INT_MASK); + u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_TXENDIF_Msk); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_TXEND_INT_MASK; + } + + /* Check Receive Start Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_RXST_INT_MASK); + u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_RXSTIF_Msk); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_RXST_INT_MASK; + } + + /* Check Receive End Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_RXEND_INT_MASK); + u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_RXENDIF_Msk); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_RXEND_INT_MASK; + } + + return u32IntFlag; + +} + + +/** + * @brief Disable USCI_UART function mode + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * + * @return None + * + * @details The function is used to disable USCI_UART function mode. + */ +void UUART_Close(UUART_T* uuart) +{ + uuart->CTL = 0ul; +} + + +/** + * @brief Disable interrupt function. + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be disabled. It is combination of: + * - \ref UUART_ABR_INT_MASK + * - \ref UUART_RLS_INT_MASK + * - \ref UUART_BUF_RXOV_INT_MASK + * - \ref UUART_TXST_INT_MASK + * - \ref UUART_TXEND_INT_MASK + * - \ref UUART_RXST_INT_MASK + * - \ref UUART_RXEND_INT_MASK + * + * @return None + * + * @details The function is used to disabled USCI_UART related interrupts specified by u32Mask parameter. + */ +void UUART_DisableInt(UUART_T* uuart, uint32_t u32Mask) +{ + + /* Disable Auto-baud rate interrupt flag */ + if((u32Mask & UUART_ABR_INT_MASK) == UUART_ABR_INT_MASK) + { + uuart->PROTIEN &= ~UUART_PROTIEN_ABRIEN_Msk; + } + + /* Disable receive line status interrupt flag */ + if((u32Mask & UUART_RLS_INT_MASK) == UUART_RLS_INT_MASK) + { + uuart->PROTIEN &= ~UUART_PROTIEN_RLSIEN_Msk; + } + + /* Disable RX overrun interrupt flag */ + if((u32Mask & UUART_BUF_RXOV_INT_MASK) == UUART_BUF_RXOV_INT_MASK) + { + uuart->BUFCTL &= ~UUART_BUFCTL_RXOVIEN_Msk; + } + + /* Disable TX start interrupt flag */ + if((u32Mask & UUART_TXST_INT_MASK) == UUART_TXST_INT_MASK) + { + uuart->INTEN &= ~UUART_INTEN_TXSTIEN_Msk; + } + + /* Disable TX end interrupt flag */ + if((u32Mask & UUART_TXEND_INT_MASK) == UUART_TXEND_INT_MASK) + { + uuart->INTEN &= ~UUART_INTEN_TXENDIEN_Msk; + } + + /* Disable RX start interrupt flag */ + if((u32Mask & UUART_RXST_INT_MASK) == UUART_RXST_INT_MASK) + { + uuart->INTEN &= ~UUART_INTEN_RXSTIEN_Msk; + } + + /* Disable RX end interrupt flag */ + if((u32Mask & UUART_RXEND_INT_MASK) == UUART_RXEND_INT_MASK) + { + uuart->INTEN &= ~UUART_INTEN_RXENDIEN_Msk; + } +} + + +/** + * @brief Enable interrupt function. + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. It is combination of: + * - \ref UUART_ABR_INT_MASK + * - \ref UUART_RLS_INT_MASK + * - \ref UUART_BUF_RXOV_INT_MASK + * - \ref UUART_TXST_INT_MASK + * - \ref UUART_TXEND_INT_MASK + * - \ref UUART_RXST_INT_MASK + * - \ref UUART_RXEND_INT_MASK + * + * @return None + * + * @details The function is used to enable USCI_UART related interrupts specified by u32Mask parameter. + */ +void UUART_EnableInt(UUART_T* uuart, uint32_t u32Mask) +{ + /* Enable Auto-baud rate interrupt flag */ + if((u32Mask & UUART_ABR_INT_MASK) == UUART_ABR_INT_MASK) + { + uuart->PROTIEN |= UUART_PROTIEN_ABRIEN_Msk; + } + + /* Enable receive line status interrupt flag */ + if((u32Mask & UUART_RLS_INT_MASK) == UUART_RLS_INT_MASK) + { + uuart->PROTIEN |= UUART_PROTIEN_RLSIEN_Msk; + } + + /* Enable RX overrun interrupt flag */ + if((u32Mask & UUART_BUF_RXOV_INT_MASK) == UUART_BUF_RXOV_INT_MASK) + { + uuart->BUFCTL |= UUART_BUFCTL_RXOVIEN_Msk; + } + + /* Enable TX start interrupt flag */ + if((u32Mask & UUART_TXST_INT_MASK) == UUART_TXST_INT_MASK) + { + uuart->INTEN |= UUART_INTEN_TXSTIEN_Msk; + } + + /* Enable TX end interrupt flag */ + if((u32Mask & UUART_TXEND_INT_MASK) == UUART_TXEND_INT_MASK) + { + uuart->INTEN |= UUART_INTEN_TXENDIEN_Msk; + } + + /* Enable RX start interrupt flag */ + if((u32Mask & UUART_RXST_INT_MASK) == UUART_RXST_INT_MASK) + { + uuart->INTEN |= UUART_INTEN_RXSTIEN_Msk; + } + + /* Enable RX end interrupt flag */ + if((u32Mask & UUART_RXEND_INT_MASK) == UUART_RXEND_INT_MASK) + { + uuart->INTEN |= UUART_INTEN_RXENDIEN_Msk; + } +} + + +/** + * @brief Open and set USCI_UART function + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32baudrate The baud rate of USCI_UART module. + * + * @return Real baud rate of USCI_UART module. + * + * @details This function use to enable USCI_UART function and set baud-rate. + */ +uint32_t UUART_Open(UUART_T* uuart, uint32_t u32baudrate) +{ + uint32_t u32PCLKFreq, u32PDSCnt, u32DSCnt, u32ClkDiv; + uint32_t u32Tmp, u32Tmp2, u32Min, u32MinClkDiv, u32MinDSCnt; + uint32_t u32Div; + + /* Get PCLK frequency */ + if( uuart == UUART0) + { + u32PCLKFreq = CLK_GetPCLK0Freq(); + } + else + { + u32PCLKFreq = CLK_GetPCLK1Freq(); + } + + u32Div = u32PCLKFreq / u32baudrate; + u32Tmp = (u32PCLKFreq / u32Div) - u32baudrate; + u32Tmp2 = u32baudrate - (u32PCLKFreq / (u32Div+1ul)); + + if(u32Tmp >= u32Tmp2) u32Div = u32Div + 1ul; + + u32Tmp = 0x400ul * 0x10ul; + for(u32PDSCnt = 1ul; u32PDSCnt <= 0x04ul; u32PDSCnt++) + { + if(u32Div <= (u32Tmp * u32PDSCnt)) break; + } + + if(u32PDSCnt > 0x4ul) u32PDSCnt = 0x4ul; + + u32Div = u32Div / u32PDSCnt; + + /* Find best solution */ + u32Min = (uint32_t) - 1; + u32MinDSCnt = 0ul; + u32MinClkDiv = 0ul; + u32Tmp = 0ul; + + for(u32DSCnt = 6ul; u32DSCnt <= 0x10ul; u32DSCnt++) /* DSCNT could be 0x5~0xF */ + { + + u32ClkDiv = u32Div / u32DSCnt; + + if(u32ClkDiv > 0x400ul) + { + u32ClkDiv = 0x400ul; + u32Tmp = u32Div - (u32ClkDiv * u32DSCnt); + u32Tmp2 = u32Tmp + 1ul; + } + else + { + u32Tmp = u32Div - (u32ClkDiv * u32DSCnt); + u32Tmp2 = ((u32ClkDiv+1ul) * u32DSCnt) - u32Div; + } + + if(u32Tmp >= u32Tmp2) + { + u32ClkDiv = u32ClkDiv + 1ul; + } + else u32Tmp2 = u32Tmp; + + if(u32Tmp2 < u32Min) + { + u32Min = u32Tmp2; + u32MinDSCnt = u32DSCnt; + u32MinClkDiv = u32ClkDiv; + + /* Break when get good results */ + if(u32Min == 0ul) + { + break; + } + } + } + + /* Enable USCI_UART protocol */ + uuart->CTL &= ~UUART_CTL_FUNMODE_Msk; + uuart->CTL = 2ul << UUART_CTL_FUNMODE_Pos; + + /* Set USCI_UART line configuration */ + uuart->LINECTL = UUART_WORD_LEN_8 | UUART_LINECTL_LSB_Msk; + uuart->DATIN0 = (2ul << UUART_DATIN0_EDGEDET_Pos); /* Set falling edge detection */ + + /* Set USCI_UART baud rate */ + uuart->BRGEN = ((u32MinClkDiv-1ul) << UUART_BRGEN_CLKDIV_Pos) | + ((u32MinDSCnt-1ul) << UUART_BRGEN_DSCNT_Pos) | + ((u32PDSCnt-1ul) << UUART_BRGEN_PDSCNT_Pos); + + uuart->PROTCTL |= UUART_PROTCTL_PROTEN_Msk; + + return (u32PCLKFreq/u32PDSCnt/u32MinDSCnt/u32MinClkDiv); +} + + +/** + * @brief Read USCI_UART data + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] pu8RxBuf The buffer to receive the data of receive buffer. + * @param[in] u32ReadBytes The read bytes number of data. + * + * @return Receive byte count + * + * @details The function is used to read Rx data from RX buffer and the data will be stored in pu8RxBuf. + */ +uint32_t UUART_Read(UUART_T* uuart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes) +{ + uint32_t u32Count, u32delayno; + + for(u32Count = 0ul; u32Count < u32ReadBytes; u32Count++) + { + u32delayno = 0ul; + + while(uuart->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk) /* Check RX empty => failed */ + { + u32delayno++; + if(u32delayno >= 0x40000000ul) + { + break; + } + } + + if(u32delayno >= 0x40000000ul) + { + break; + } + + pu8RxBuf[u32Count] = (uint8_t)uuart->RXDAT; /* Get Data from USCI RX */ + } + + return u32Count; + +} + + +/** + * @brief Set USCI_UART line configuration + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32baudrate The register value of baud rate of USCI_UART module. + * If u32baudrate = 0, USCI_UART baud rate will not change. + * @param[in] u32data_width The data length of USCI_UART module. + * - \ref UUART_WORD_LEN_6 + * - \ref UUART_WORD_LEN_7 + * - \ref UUART_WORD_LEN_8 + * - \ref UUART_WORD_LEN_9 + * @param[in] u32parity The parity setting (none/odd/even) of USCI_UART module. + * - \ref UUART_PARITY_NONE + * - \ref UUART_PARITY_ODD + * - \ref UUART_PARITY_EVEN + * @param[in] u32stop_bits The stop bit length (1/2 bit) of USCI_UART module. + * - \ref UUART_STOP_BIT_1 + * - \ref UUART_STOP_BIT_2 + * + * @return Real baud rate of USCI_UART module. + * + * @details This function use to config USCI_UART line setting. + */ +uint32_t UUART_SetLine_Config(UUART_T* uuart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits) +{ + uint32_t u32PCLKFreq, u32PDSCnt, u32DSCnt, u32ClkDiv; + uint32_t u32Tmp, u32Tmp2, u32Min, u32MinClkDiv, u32MinDSCnt; + uint32_t u32Div; + + /* Get PCLK frequency */ + if(uuart == UUART0) + { + u32PCLKFreq = CLK_GetPCLK0Freq(); + } + else /* UUART1 */ + { + u32PCLKFreq = CLK_GetPCLK1Freq(); + } + + if(u32baudrate != 0ul) + { + u32Div = u32PCLKFreq / u32baudrate; + u32Tmp = (u32PCLKFreq / u32Div) - u32baudrate; + u32Tmp2 = u32baudrate - (u32PCLKFreq / (u32Div+1ul)); + + if(u32Tmp >= u32Tmp2) u32Div = u32Div + 1ul; + + u32Tmp = 0x400ul * 0x10ul; + for(u32PDSCnt = 1ul; u32PDSCnt <= 0x04ul; u32PDSCnt++) + { + if(u32Div <= (u32Tmp * u32PDSCnt)) break; + } + + if(u32PDSCnt > 0x4ul) u32PDSCnt = 0x4ul; + + u32Div = u32Div / u32PDSCnt; + + /* Find best solution */ + u32Min = (uint32_t) - 1; + u32MinDSCnt = 0ul; + u32MinClkDiv = 0ul; + + for(u32DSCnt = 6ul; u32DSCnt <= 0x10ul; u32DSCnt++) /* DSCNT could be 0x5~0xF */ + { + u32ClkDiv = u32Div / u32DSCnt; + + if(u32ClkDiv > 0x400ul) + { + u32ClkDiv = 0x400ul; + u32Tmp = u32Div - (u32ClkDiv * u32DSCnt); + u32Tmp2 = u32Tmp + 1ul; + } + else + { + u32Tmp = u32Div - (u32ClkDiv * u32DSCnt); + u32Tmp2 = ((u32ClkDiv+1ul) * u32DSCnt) - u32Div; + } + + if(u32Tmp >= u32Tmp2) + { + u32ClkDiv = u32ClkDiv + 1ul; + } + else u32Tmp2 = u32Tmp; + + if(u32Tmp2 < u32Min) + { + u32Min = u32Tmp2; + u32MinDSCnt = u32DSCnt; + u32MinClkDiv = u32ClkDiv; + + /* Break when get good results */ + if(u32Min == 0ul) + { + break; + } + } + } + + /* Set USCI_UART baud rate */ + uuart->BRGEN = ((u32MinClkDiv-1ul) << UUART_BRGEN_CLKDIV_Pos) | + ((u32MinDSCnt-1ul) << UUART_BRGEN_DSCNT_Pos) | + ((u32PDSCnt-1ul) << UUART_BRGEN_PDSCNT_Pos); + } + else + { + u32PDSCnt = ((uuart->BRGEN & UUART_BRGEN_PDSCNT_Msk) >> UUART_BRGEN_PDSCNT_Pos) + 1ul; + u32MinDSCnt = ((uuart->BRGEN & UUART_BRGEN_DSCNT_Msk) >> UUART_BRGEN_DSCNT_Pos) + 1ul; + u32MinClkDiv = ((uuart->BRGEN & UUART_BRGEN_CLKDIV_Msk) >> UUART_BRGEN_CLKDIV_Pos) + 1ul; + } + + /* Set USCI_UART line configuration */ + uuart->LINECTL = (uuart->LINECTL & ~UUART_LINECTL_DWIDTH_Msk) | u32data_width; + uuart->PROTCTL = (uuart->PROTCTL & ~(UUART_PROTCTL_STICKEN_Msk | UUART_PROTCTL_EVENPARITY_Msk | + UUART_PROTCTL_PARITYEN_Msk)) | u32parity; + uuart->PROTCTL = (uuart->PROTCTL & ~UUART_PROTCTL_STOPB_Msk ) | u32stop_bits; + + return (u32PCLKFreq/u32PDSCnt/u32MinDSCnt/u32MinClkDiv); +} + + +/** + * @brief Write USCI_UART data + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] pu8TxBuf The buffer to send the data to USCI transmission buffer. + * @param[out] u32WriteBytes The byte number of data. + * + * @return Transfer byte count + * + * @details The function is to write data into TX buffer to transmit data by USCI_UART. + */ +uint32_t UUART_Write(UUART_T* uuart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes) +{ + uint32_t u32Count, u32delayno; + + for(u32Count = 0ul; u32Count != u32WriteBytes; u32Count++) + { + u32delayno = 0ul; + while((uuart->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk) == 0ul) /* Wait Tx empty */ + { + u32delayno++; + if(u32delayno >= 0x40000000ul) + { + break; + } + } + + if(u32delayno >= 0x40000000ul) + { + break; + } + + uuart->TXDAT = (uint8_t)pu8TxBuf[u32Count]; /* Send USCI_UART Data to buffer */ + } + + return u32Count; + +} + + +/** + * @brief Enable USCI_UART Wake-up Function + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32WakeupMode The wakeup mode of USCI_UART module. + * - \ref UUART_PROTCTL_DATWKEN_Msk : Data wake-up Mode + * - \ref UUART_PROTCTL_CTSWKEN_Msk : nCTS wake-up Mode + * + * @return None + * + * @details The function is used to enable Wake-up function of USCI_UART. + */ +void UUART_EnableWakeup(UUART_T* uuart, uint32_t u32WakeupMode) +{ + uuart->PROTCTL |= u32WakeupMode; + uuart->WKCTL |= UUART_WKCTL_WKEN_Msk; +} + + +/** + * @brief Disable USCI_UART Wake-up Function + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * + * @return None + * + * @details The function is used to disable Wake-up function of USCI_UART. + */ +void UUART_DisableWakeup(UUART_T* uuart) +{ + uuart->PROTCTL &= ~(UUART_PROTCTL_DATWKEN_Msk|UUART_PROTCTL_CTSWKEN_Msk); + uuart->WKCTL &= ~UUART_WKCTL_WKEN_Msk; +} + +/** + * @brief Enable USCI_UART auto flow control + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * + * @return None + * + * @details The function is used to enable USCI_UART auto flow control. + */ +void UUART_EnableFlowCtrl(UUART_T* uuart) +{ + /* Set RTS signal is low level active */ + uuart->LINECTL &= ~UUART_LINECTL_CTLOINV_Msk; + + /* Set CTS signal is low level active */ + uuart->CTLIN0 &= ~UUART_CTLIN0_ININV_Msk; + + /* Enable CTS and RTS auto flow control function */ + uuart->PROTCTL |= UUART_PROTCTL_RTSAUTOEN_Msk|UUART_PROTCTL_CTSAUTOEN_Msk; +} + +/** + * @brief Disable USCI_UART auto flow control + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * + * @return None + * + * @details The function is used to disable USCI_UART auto flow control. + */ +void UUART_DisableFlowCtrl(UUART_T* uuart) +{ + /* Disable CTS and RTS auto flow control function */ + uuart->PROTCTL &= ~(UUART_PROTCTL_RTSAUTOEN_Msk|UUART_PROTCTL_CTSAUTOEN_Msk); +} + + + + +/*@}*/ /* end of group USCI_UART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USCI_UART_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ + diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_wdt.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_wdt.c new file mode 100644 index 0000000000000000000000000000000000000000..fe4d433b86644ba62b53bccfc69767893652e52e --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_wdt.c @@ -0,0 +1,69 @@ +/**************************************************************************//** + * @file wdt.c + * @version V3.00 + * @brief M480 series WDT driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WDT_Driver WDT Driver + @{ +*/ + +/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions + @{ +*/ + +/** + * @brief Initialize WDT and start counting + * + * @param[in] u32TimeoutInterval Time-out interval period of WDT module. Valid values are: + * - \ref WDT_TIMEOUT_2POW4 + * - \ref WDT_TIMEOUT_2POW6 + * - \ref WDT_TIMEOUT_2POW8 + * - \ref WDT_TIMEOUT_2POW10 + * - \ref WDT_TIMEOUT_2POW12 + * - \ref WDT_TIMEOUT_2POW14 + * - \ref WDT_TIMEOUT_2POW16 + * - \ref WDT_TIMEOUT_2POW18 + * @param[in] u32ResetDelay Configure WDT time-out reset delay period. Valid values are: + * - \ref WDT_RESET_DELAY_1026CLK + * - \ref WDT_RESET_DELAY_130CLK + * - \ref WDT_RESET_DELAY_18CLK + * - \ref WDT_RESET_DELAY_3CLK + * @param[in] u32EnableReset Enable WDT time-out reset system function. Valid values are TRUE and FALSE. + * @param[in] u32EnableWakeup Enable WDT time-out wake-up system function. Valid values are TRUE and FALSE. + * + * @return None + * + * @details This function makes WDT module start counting with different time-out interval, reset delay period and choose to \n + * enable or disable WDT time-out reset system or wake-up system. + * @note Please make sure that Register Write-Protection Function has been disabled before using this function. + */ +void WDT_Open(uint32_t u32TimeoutInterval, + uint32_t u32ResetDelay, + uint32_t u32EnableReset, + uint32_t u32EnableWakeup) +{ + WDT->ALTCTL = u32ResetDelay; + + WDT->CTL = u32TimeoutInterval | WDT_CTL_WDTEN_Msk | + (u32EnableReset << WDT_CTL_RSTEN_Pos) | + (u32EnableWakeup << WDT_CTL_WKEN_Pos); + return; +} + +/*@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group WDT_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/StdDriver/src/nu_wwdt.c b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_wwdt.c new file mode 100644 index 0000000000000000000000000000000000000000..3f1d13a151047d86d27701c630c85b1b360e79eb --- /dev/null +++ b/bsp/nuvoton/libraries/m480/StdDriver/src/nu_wwdt.c @@ -0,0 +1,69 @@ +/**************************************************************************//** + * @file wwdt.c + * @version V3.00 + * @brief M480 series WWDT driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WWDT_Driver WWDT Driver + @{ +*/ + +/** @addtogroup WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions + @{ +*/ + +/** + * @brief Open WWDT and start counting + * + * @param[in] u32PreScale Pre-scale setting of WWDT counter. Valid values are: + * - \ref WWDT_PRESCALER_1 + * - \ref WWDT_PRESCALER_2 + * - \ref WWDT_PRESCALER_4 + * - \ref WWDT_PRESCALER_8 + * - \ref WWDT_PRESCALER_16 + * - \ref WWDT_PRESCALER_32 + * - \ref WWDT_PRESCALER_64 + * - \ref WWDT_PRESCALER_128 + * - \ref WWDT_PRESCALER_192 + * - \ref WWDT_PRESCALER_256 + * - \ref WWDT_PRESCALER_384 + * - \ref WWDT_PRESCALER_512 + * - \ref WWDT_PRESCALER_768 + * - \ref WWDT_PRESCALER_1024 + * - \ref WWDT_PRESCALER_1536 + * - \ref WWDT_PRESCALER_2048 + * @param[in] u32CmpValue Setting the window compared value. Valid values are between 0x0 to 0x3F. + * @param[in] u32EnableInt Enable WWDT time-out interrupt function. Valid values are TRUE and FALSE. + * + * @return None + * + * @details This function makes WWDT module start counting with different counter period by pre-scale setting and compared window value. + * @note This WWDT_CTL register can be write only one time after chip is powered on or reset. + */ +void WWDT_Open(uint32_t u32PreScale, + uint32_t u32CmpValue, + uint32_t u32EnableInt) +{ + WWDT->CTL = u32PreScale | + (u32CmpValue << WWDT_CTL_CMPDAT_Pos) | + ((u32EnableInt == TRUE) ? WWDT_CTL_INTEN_Msk : 0U) | + WWDT_CTL_WWDTEN_Msk; + return; +} + +/*@}*/ /* end of group WWDT_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group WWDT_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/USBHostLib/SConscript b/bsp/nuvoton/libraries/m480/USBHostLib/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..bf3b5901e8598b98a74c69f7e2abda685f0444c6 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/USBHostLib/SConscript @@ -0,0 +1,12 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() +group = [] +if GetDepend('BSP_USING_HSUSBH') or GetDepend('BSP_USING_USBH'): + src = Glob('*src/*.c') + Glob('src/*.cpp') + CPPPATH = [cwd + '/inc'] + group = DefineGroup('m480_usbhostlib', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/nuvoton/libraries/m480/USBHostLib/inc/config.h b/bsp/nuvoton/libraries/m480/USBHostLib/inc/config.h new file mode 100644 index 0000000000000000000000000000000000000000..0dab057ac32fee288f71c39796fc69c26b4fe343 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/USBHostLib/inc/config.h @@ -0,0 +1,114 @@ +/**************************************************************************//** + * @file config.h + * @version V1.00 + * @brief This header file defines the configuration of USB Host library. + * + * SPDX-License-Identifier: Apache-2.0 + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#ifndef _USBH_CONFIG_H_ +#define _USBH_CONFIG_H_ + +/// @cond HIDDEN_SYMBOLS + +#include +#include +/*----------------------------------------------------------------------------------------*/ +/* Hardware settings */ +/*----------------------------------------------------------------------------------------*/ +#define HCLK_MHZ 192 /* used for loop-delay. must be larger than + true HCLK clock MHz */ + +#define ENABLE_OHCI_IRQ() NVIC_EnableIRQ(USBH_IRQn) +#define DISABLE_OHCI_IRQ() NVIC_DisableIRQ(USBH_IRQn) +#define ENABLE_EHCI_IRQ() NVIC_EnableIRQ(HSUSBH_IRQn) +#define DISABLE_EHCI_IRQ() NVIC_DisableIRQ(HSUSBH_IRQn) + +#define ENABLE_OHCI /* Enable OHCI host controller */ + +#if defined(BSP_USING_HSUSBH) +#define ENABLE_EHCI /* Enable EHCI host controller */ +#endif + +#define EHCI_PORT_CNT 1 /* Number of EHCI roothub ports */ +#define OHCI_PORT_CNT 2 /* Number of OHCI roothub ports */ +#define OHCI_PER_PORT_POWER /* OHCI root hub per port powered */ + +#define OHCI_ISO_DELAY 4 /* preserved number frames while scheduling + OHCI isochronous transfer */ + +#define EHCI_ISO_DELAY 2 /* preserved number of frames while + scheduling EHCI isochronous transfer */ + +#define EHCI_ISO_RCLM_RANGE 32 /* When inspecting activated iTD/siTD, + unconditionally reclaim iTD/isTD scheduled + in just elapsed EHCI_ISO_RCLM_RANGE ms. */ + +#define MAX_DESC_BUFF_SIZE 512 /* To hold the configuration descriptor, USB + core will allocate a buffer with this size + for each connected device. USB core does + not release it until device disconnected. */ + +/*----------------------------------------------------------------------------------------*/ +/* Memory allocation settings */ +/*----------------------------------------------------------------------------------------*/ + +#define STATIC_MEMORY_ALLOC 0 /* pre-allocate static memory blocks. No dynamic memory aloocation. + But the maximum number of connected devices and transfers are + limited. */ + +#define MAX_UDEV_DRIVER 8 /*!< Maximum number of registered drivers */ +#define MAX_ALT_PER_IFACE 8 /*!< maximum number of alternative interfaces per interface */ +#define MAX_EP_PER_IFACE 6 /*!< maximum number of endpoints per interface */ +#define MAX_HUB_DEVICE 8 /*!< Maximum number of hub devices */ + +/* Host controller hardware transfer descriptors memory pool. ED/TD/ITD of OHCI and QH/QTD of EHCI + are all allocated from this pool. Allocated unit size is determined by MEM_POOL_UNIT_SIZE. + May allocate one or more units depend on hardware descriptor type. */ + +#define MEM_POOL_UNIT_SIZE 64 /*!< A fixed hard coding setting. Do not change it! */ +#define MEM_POOL_UNIT_NUM 256 /*!< Increase this or heap size if memory allocate failed. */ + +/*----------------------------------------------------------------------------------------*/ +/* Re-defined staff for various compiler */ +/*----------------------------------------------------------------------------------------*/ +#ifdef __ICCARM__ +#define __inline inline +#endif + + +/*----------------------------------------------------------------------------------------*/ +/* Debug settings */ +/*----------------------------------------------------------------------------------------*/ +#define ENABLE_ERROR_MSG /* enable debug messages */ +#define ENABLE_DEBUG_MSG /* enable debug messages */ +//#define ENABLE_VERBOSE_DEBUG /* verbos debug messages */ +//#define DUMP_DESCRIPTOR /* dump descriptors */ + +#ifdef ENABLE_ERROR_MSG +#define USB_error rt_kprintf +#else +#define USB_error(...) +#endif + +#ifdef ENABLE_DEBUG_MSG +#define USB_debug rt_kprintf +#ifdef ENABLE_VERBOSE_DEBUG +#define USB_vdebug rt_kprintf +#else +#define USB_vdebug(...) +#endif +#else +#define USB_debug(...) +#define USB_vdebug(...) +#endif + + +/// @endcond HIDDEN_SYMBOLS + +#endif /* _USBH_CONFIG_H_ */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ + diff --git a/bsp/nuvoton/libraries/m480/USBHostLib/inc/ehci.h b/bsp/nuvoton/libraries/m480/USBHostLib/inc/ehci.h new file mode 100644 index 0000000000000000000000000000000000000000..f99a4abde34c6e48bd024e216b184a4b4342f9bd --- /dev/null +++ b/bsp/nuvoton/libraries/m480/USBHostLib/inc/ehci.h @@ -0,0 +1,281 @@ +/**************************************************************************//** + * @file ehci.h + * @version V1.00 + * @brief USB EHCI host controller driver header file. + * + * SPDX-License-Identifier: Apache-2.0 + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#ifndef _USBH_EHCI_H_ +#define _USBH_EHCI_H_ + +/// @cond HIDDEN_SYMBOLS + +struct utr_t; +struct udev_t; +struct qh_t; +struct iso_ep_t; +struct ep_info_t; + +/*----------------------------------------------------------------------------------------*/ +/* Periodic Frame List Size (256, 512, or 1024) */ +/*----------------------------------------------------------------------------------------*/ +#define FL_SIZE 1024 /* frame list size can be 256, 512, or 1024 */ +#define NUM_IQH 11 /* depends on FL_SIZE, 256:9, 512:10, 1024:11 */ + + +/*----------------------------------------------------------------------------------------*/ +/* Interrupt Threshold Control (1, 2, 4, 6, .. 64) */ +/*----------------------------------------------------------------------------------------*/ +#define UCMDR_INT_THR_CTRL (0x1< of QH */ +} qTD_T; + + +#define QTD_LIST_END 0x1 /* Indicate the terminate of qTD list. */ +#define QTD_PTR(x) ((qTD_T *)((uint32_t)(x) & ~0x1F)) + +/* + * Status: qTD Token[7:0] + */ +#define QTD_STS_PS_OUT (0<<0) /* directs the HC to issue an OUT PID */ +#define QTD_STS_PS_PING (1<<0) /* directs the HC to issue an PING PID */ +#define QTD_STS_SPLIT_STRAT (0<<1) /* directs the HC to issue an Start split */ +#define QTD_STS_SPLIT_COMPLETE (1<<1) /* directs the HC to issue an Complete split */ +#define QTD_STS_MISS_MF (1<<2) /* miss a required complete-split transaction */ +#define QTD_STS_XactErr (1<<3) /* Transaction Error occurred */ +#define QTD_STS_BABBLE (1<<4) /* Babble Detected */ +#define QTD_STS_DATA_BUFF_ERR (1<<5) /* Data Buffer Error */ +#define QTD_STS_HALT (1<<6) /* Halted */ +#define QTD_STS_ACTIVE (1<<7) /* Active */ + +/* + * PID: qTD Token[9:8] + */ +#define QTD_PID_Msk (0x3<<8) +#define QTD_PID_OUT (0<<8) /* generates token (E1H) */ +#define QTD_PID_IN (1<<8) /* generates token (69H) */ +#define QTD_PID_SETUP (2<<8) /* generates token (2DH) */ + +#define QTD_ERR_COUNTER (3<<10) /* Token[11:10] */ +#define QTD_IOC (1<<15) /* Token[15] - Interrupt On Complete */ +#define QTD_TODO_LEN_Pos 16 /* Token[31:16] - Total Bytes to Transfer */ +#define QTD_TODO_LEN(x) (((x)>>16) & 0x7FFF) +#define QTD_DT (1UL<<31) /* Token[31] - Data Toggle */ + +/*----------------------------------------------------------------------------------------*/ +/* Queue Head (QH) */ +/*----------------------------------------------------------------------------------------*/ +typedef struct qh_t +{ + /* OHCI spec. Endpoint descriptor */ + uint32_t HLink; /* Queue Head Horizontal Link Pointer */ + uint32_t Chrst; /* Endpoint Characteristics: QH DWord 1 */ + uint32_t Cap; /* Endpoint Capabilities: QH DWord 2 */ + uint32_t Curr_qTD; /* Current qTD Pointer */ + /* + * The followings are qTD Transfer Overlay + */ + uint32_t OL_Next_qTD; /* Next qTD Pointer */ + uint32_t OL_Alt_Next_qTD; /* Alternate Next qTD Pointer */ + uint32_t OL_Token; /* qTD Token */ + uint32_t OL_Bptr[5]; /* qTD Buffer Page Pointer List */ + /* + * The following members are used by USB Host libary. + */ + qTD_T *dummy; /* point to the inactive dummy qTD */ + qTD_T *qtd_list; /* currently linked qTD transfers */ + qTD_T *done_list; /* currently linked qTD transfers */ + struct qh_t *next; /* point to the next QH in remove list */ +} QH_T; + +/* HLink[0] T field of "Queue Head Horizontal Link Pointer" */ +#define QH_HLNK_END 0x1 + +/* + * HLink[2:1] Typ field of "Queue Head Horizontal Link Pointer" + */ +#define QH_HLNK_ITD(x) (((uint32_t)(x) & ~0x1F) | 0x0) +#define QH_HLNK_QH(x) (((uint32_t)(x) & ~0x1F) | 0x2) +#define QH_HLNK_SITD(x) (((uint32_t)(x) & ~0x1F) | 0x4) +#define QH_HLNK_FSTN(x) (((uint32_t)(x) & ~0x1F) | 0x6) +#define QH_PTR(x) ((QH_T *)((uint32_t)(x) & ~0x1F)) + +/* + * Bit fields of "Endpoint Characteristics" + */ +#define QH_NAK_RL (4L<<28) /* Chrst[31:28] - NAK Count Reload */ +#define QH_CTRL_EP_FLAG (1<<27) /* Chrst[27] - Control Endpoint Flag */ +#define QH_RCLM_LIST_HEAD (1<<15) /* Chrst[15] - Head of Reclamation List Flag */ +#define QH_DTC (1<<14) /* Chrst[14] - Data Toggle Control */ +#define QH_EPS_FULL (0<<12) /* Chrst[13:12] - Endpoint Speed (Full) */ +#define QH_EPS_LOW (1<<12) /* Chrst[13:12] - Endpoint Speed (Low) */ +#define QH_EPS_HIGH (2<<12) /* Chrst[13:12] - Endpoint Speed (High) */ +#define QH_I_NEXT (1<<7) /* Chrst[7] - Inactivate on Next Transaction */ + +/* + * Bit fields of "Endpoint Capabilities" + */ +#define QH_MULT_Pos 30 /* Cap[31:30] - High-Bandwidth Pipe Multiplier */ +#define QH_HUB_PORT_Pos 23 /* Cap[29:23] - Hub Port Number */ +#define QH_HUB_ADDR_Pos 16 /* Cap[22:16] - Hub Addr */ +#define QH_C_MASK_Msk 0xFF00 /* Cap[15:8] - uFrame C-mask */ +#define QH_S_MASK_Msk 0x00FF /* Cap[7:0] - uFrame S-mask */ + + +/*----------------------------------------------------------------------------------------*/ +/* Isochronous (High-Speed) Transfer Descriptor (iTD) */ +/*----------------------------------------------------------------------------------------*/ +typedef struct itd_t +{ + uint32_t Next_Link; /* Next Link Pointer */ + uint32_t Transaction[8]; /* Transaction Status and Control */ + uint32_t Bptr[7]; /* Buffer Page Pointer List */ + /* + * The following members are used by USB Host libary. + */ + struct iso_ep_t *iso_ep; /* associated isochronous information block */ + struct utr_t *utr; /* associated UTR */ + uint32_t buff_base; /* buffer base address */ + uint8_t fidx; /* iTD's first index to UTR iso frames */ + uint8_t trans_mask; /* mask of activated transactions in iTD */ + uint32_t sched_frnidx; /* scheduled frame index */ + struct itd_t *next; /* used by software to maintain iTD list */ +} iTD_T; + +/* + * Next_Link[2:1] Typ field of "Next Schedule Element Pointer" Typ field + */ +#define ITD_HLNK_ITD(x) (((uint32_t)(x) & ~0x1F) | 0x0) +#define ITD_HLNK_QH(x) (((uint32_t)(x) & ~0x1F) | 0x2) +#define ITD_HLNK_SITD(x) (((uint32_t)(x) & ~0x1F) | 0x4) +#define ITD_HLNK_FSTN(x) (((uint32_t)(x) & ~0x1F) | 0x6) +#define ITD_PTR(x) ((iTD_T *)((uint32_t)(x) & ~0x1F)) + +/* + * Transaction[8] + */ +#define ITD_STATUS(x) (((x)>>28)&0xF) +#define ITD_STATUS_ACTIVE (0x80000000UL) /* Active */ +#define ITD_STATUS_BUFF_ERR (0x40000000UL) /* Data Buffer Error */ +#define ITD_STATUS_BABBLE (0x20000000UL) /* Babble Detected */ +#define ITD_STATUS_XACT_ERR (0x10000000UL) /* Transcation Error */ + +#define ITD_XLEN_Pos 16 +#define ITD_XFER_LEN(x) (((x)>>16)&0xFFF) +#define ITD_IOC (1<<15) +#define ITD_PG_Pos 12 +#define ITD_XFER_OFF_Msk 0xFFF + +/* + * Bptr[7] + */ +#define ITD_BUFF_PAGE_Pos 12 +/* Bptr[0] */ +#define ITD_EP_NUM_Pos 8 +#define ITD_EP_NUM(itd) (((itd)->Bptr[0]>>8)&0xF) +#define ITD_DEV_ADDR_Pos 0 +#define ITD_DEV_ADDR(itd) ((itd)->Bptr[0]&0x7F) +/* Bptr[1] */ +#define ITD_DIR_IN (1<<11) +#define ITD_DIR_OUT (0<<11) +#define ITD_MAX_PKTSZ_Pos 0 +#define ITD_MAX_PKTSZ(itd) ((itd)->Bptr[1]&0x7FF) + +/*----------------------------------------------------------------------------------------*/ +/* Split Isochronous (Full-Speed) Transfer Descriptor (siTD) */ +/*----------------------------------------------------------------------------------------*/ +typedef struct sitd_t +{ + uint32_t Next_Link; /* Next Link Pointer */ + uint32_t Chrst; /* Endpoint and Transaction Translator Characteristics */ + uint32_t Sched; /* Micro-frame Schedule Control */ + uint32_t StsCtrl; /* siTD Transfer Status and Control */ + uint32_t Bptr[2]; /* Buffer Page Pointer List */ + uint32_t BackLink; /* siTD Back Link Pointer */ + /* + * The following members are used by USB Host libary. + */ + struct iso_ep_t *iso_ep; /* associated isochronous information block */ + struct utr_t *utr; /* associated UTR */ + uint8_t fidx; /* iTD's first index to UTR iso frames */ + uint32_t sched_frnidx; /* scheduled frame index */ + struct sitd_t *next; /* used by software to maintain siTD list */ +} siTD_T; + +#define SITD_LIST_END 0x1 /* Indicate the terminate of siTD list. */ + +#define SITD_XFER_IO_Msk (1UL<<31) +#define SITD_XFER_IN (1UL<<31) +#define SITD_XFER_OUT (0UL<<31) + +#define SITD_PORT_NUM_Pos 24 +#define SITD_HUB_ADDR_Pos 16 +#define SITD_EP_NUM_Pos 8 +#define SITD_DEV_ADDR_Pos 0 + +#define SITD_IOC (1UL<<31) +#define SITD_XFER_CNT_Pos 16 +#define SITD_XFER_CNT_Msk (0x3FF<>28) & 0x0F) +#define TD_CC_SET(td, cc) (td) = ((td) & 0x0FFFFFFF) | (((cc) & 0x0F) << 28) +#define TD_T_DATA0 0x02000000 +#define TD_T_DATA1 0x03000000 +#define TD_R 0x00040000 +#define TD_DP 0x00180000 +#define TD_DP_IN 0x00100000 +#define TD_DP_OUT 0x00080000 +#define MAXPSW 8 +/* steel TD reserved bits to keep driver data */ +#define TD_TYPE_Msk (0x3<<16) +#define TD_TYPE_CTRL (0x0<<16) +#define TD_TYPE_BULK (0x1<<16) +#define TD_TYPE_INT (0x2<<16) +#define TD_TYPE_ISO (0x3<<16) +#define TD_CTRL_Msk (0x7<<15) +#define TD_CTRL_DATA (1<<15) + + +/* + * The HCCA (Host Controller Communications Area) is a 256 byte + * structure defined in the OHCI spec. that the host controller is + * told the base address of. It must be 256-byte aligned. + */ +typedef struct +{ + uint32_t int_table[32]; /* Interrupt ED table */ + uint16_t frame_no; /* current frame number */ + uint16_t pad1; /* set to 0 on each frame_no change */ + uint32_t done_head; /* info returned for an interrupt */ + uint8_t reserved_for_hc[116]; +} HCCA_T; + + +/// @endcond + +#endif /* _USBH_OHCI_H_ */ diff --git a/bsp/nuvoton/libraries/m480/USBHostLib/inc/usb.h b/bsp/nuvoton/libraries/m480/USBHostLib/inc/usb.h new file mode 100644 index 0000000000000000000000000000000000000000..5d6772f27aadb9eae3b1a2b7f395173af8f1ed55 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/USBHostLib/inc/usb.h @@ -0,0 +1,486 @@ +/**************************************************************************//** + * @file usb.h + * @version V1.00 + * @brief USB Host library header file. + * + * SPDX-License-Identifier: Apache-2.0 + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#ifndef _USBH_H_ +#define _USBH_H_ + +#include "config.h" +#include "usbh_lib.h" +#include "ehci.h" +#include "ohci.h" + +/// @cond HIDDEN_SYMBOLS + +struct utr_t; +struct udev_t; +struct hub_dev_t; +struct iface_t; +struct ep_info_t; + +/*----------------------------------------------------------------------------------*/ +/* USB device request setup packet */ +/*----------------------------------------------------------------------------------*/ +#ifdef __ICCARM__ +typedef struct +{ + __packed uint8_t bmRequestType; + __packed uint8_t bRequest; + __packed uint16_t wValue; + __packed uint16_t wIndex; + __packed uint16_t wLength; +} DEV_REQ_T; +#else +typedef struct __attribute__((__packed__)) +{ + uint8_t bmRequestType; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +} +DEV_REQ_T; +#endif + +/* + * bmRequestType[7] - Data transfer direction + */ +#define REQ_TYPE_OUT 0x00 +#define REQ_TYPE_IN 0x80 +/* + * bmRequestType[6:5] - Type + */ +#define REQ_TYPE_STD_DEV 0x00 +#define REQ_TYPE_CLASS_DEV 0x20 +#define REQ_TYPE_VENDOR_DEV 0x40 +/* + * bmRequestType[4:0] - Recipient + */ +#define REQ_TYPE_TO_DEV 0x00 +#define REQ_TYPE_TO_IFACE 0x01 +#define REQ_TYPE_TO_EP 0x02 +#define REQ_TYPE_TO_OTHER 0x03 +/* + * Standard Requests + */ +#define USB_REQ_GET_STATUS 0x00 +#define USB_REQ_CLEAR_FEATURE 0x01 +#define USB_REQ_SET_FEATURE 0x03 +#define USB_REQ_SET_ADDRESS 0x05 +#define USB_REQ_GET_DESCRIPTOR 0x06 +#define USB_REQ_SET_CONFIGURATION 0x09 +#define USB_REQ_SET_INTERFACE 0x0B +/* + * Descriptor Types + */ +#define USB_DT_STANDARD 0x00 +#define USB_DT_CLASS 0x20 +#define USB_DT_VENDOR 0x40 + +#define USB_DT_DEVICE 0x01 +#define USB_DT_CONFIGURATION 0x02 +#define USB_DT_STRING 0x03 +#define USB_DT_INTERFACE 0x04 +#define USB_DT_ENDPOINT 0x05 +#define USB_DT_DEVICE_QUALIFIER 0x06 +#define USB_DT_OTHER_SPEED_CONF 0x07 +#define USB_DT_IFACE_POWER 0x08 + + + +/*----------------------------------------------------------------------------------*/ +/* USB standard descriptors */ +/*----------------------------------------------------------------------------------*/ + +/* Descriptor header */ +#ifdef __ICCARM__ +typedef struct +{ + __packed uint8_t bLength; + __packed uint8_t bDescriptorType; +} DESC_HDR_T; +#else +typedef struct __attribute__((__packed__)) +{ + uint8_t bLength; + uint8_t bDescriptorType; +} +DESC_HDR_T; +#endif + +/*----------------------------------------------------------------------------------*/ +/* USB device descriptor */ +/*----------------------------------------------------------------------------------*/ +#ifdef __ICCARM__ +typedef struct /*!< device descriptor structure */ +{ + __packed uint8_t bLength; /*!< Length of device descriptor */ + __packed uint8_t bDescriptorType; /*!< Device descriptor type */ + __packed uint16_t bcdUSB; /*!< USB version number */ + __packed uint8_t bDeviceClass; /*!< Device class code */ + __packed uint8_t bDeviceSubClass; /*!< Device subclass code */ + __packed uint8_t bDeviceProtocol; /*!< Device protocol code */ + __packed uint8_t bMaxPacketSize0; /*!< Maximum packet size of control endpoint*/ + __packed uint16_t idVendor; /*!< Vendor ID */ + __packed uint16_t idProduct; /*!< Product ID */ + __packed uint16_t bcdDevice; /*!< Device ID */ + __packed uint8_t iManufacturer; /*!< Manufacture description string ID */ + __packed uint8_t iProduct; /*!< Product description string ID */ + __packed uint8_t iSerialNumber; /*!< Serial number description string ID */ + __packed uint8_t bNumConfigurations; /*!< Total number of configurations */ +} DESC_DEV_T; /*!< device descriptor structure */ +#else +/*----------------------------------------------------------------------------------*/ +/* USB device descriptor */ +/*----------------------------------------------------------------------------------*/ +typedef struct __attribute__((__packed__)) /*!< device descriptor structure */ +{ + uint8_t bLength; /*!< Length of device descriptor */ + uint8_t bDescriptorType; /*!< Device descriptor type */ + uint16_t bcdUSB; /*!< USB version number */ + uint8_t bDeviceClass; /*!< Device class code */ + uint8_t bDeviceSubClass; /*!< Device subclass code */ + uint8_t bDeviceProtocol; /*!< Device protocol code */ + uint8_t bMaxPacketSize0; /*!< Maximum packet size of control endpoint*/ + uint16_t idVendor; /*!< Vendor ID */ + uint16_t idProduct; /*!< Product ID */ + uint16_t bcdDevice; /*!< Device ID */ + uint8_t iManufacturer; /*!< Manufacture description string ID */ + uint8_t iProduct; /*!< Product description string ID */ + uint8_t iSerialNumber; /*!< Serial number description string ID */ + uint8_t bNumConfigurations; /*!< Total number of configurations */ +} +DESC_DEV_T; /*!< device descriptor structure */ +#endif + +/* + * Configuration Descriptor + */ +#ifdef __ICCARM__ +typedef struct usb_config_descriptor /*!< Configuration descriptor structure */ +{ + __packed uint8_t bLength; /*!< Length of configuration descriptor */ + __packed uint8_t bDescriptorType; /*!< Descriptor type */ + __packed uint16_t wTotalLength; /*!< Total length of this configuration */ + __packed uint8_t bNumInterfaces; /*!< Total number of interfaces */ + __packed uint8_t bConfigurationValue; /*!< Configuration descriptor number */ + __packed uint8_t iConfiguration; /*!< String descriptor ID */ + __packed uint8_t bmAttributes; /*!< Configuration characteristics */ + __packed uint8_t MaxPower; /*!< Maximum power consumption */ +} DESC_CONF_T; /*!< Configuration descriptor structure */ +#else +typedef struct __attribute__((__packed__)) usb_config_descriptor /*!< Configuration descriptor structure */ +{ + uint8_t bLength; /*!< Length of configuration descriptor */ + uint8_t bDescriptorType; /*!< Descriptor type */ + uint16_t wTotalLength; /*!< Total length of this configuration */ + uint8_t bNumInterfaces; /*!< Total number of interfaces */ + uint8_t bConfigurationValue; /*!< Configuration descriptor number */ + uint8_t iConfiguration; /*!< String descriptor ID */ + uint8_t bmAttributes; /*!< Configuration characteristics */ + uint8_t MaxPower; /*!< Maximum power consumption */ +} DESC_CONF_T; /*!< Configuration descriptor structure */ +#endif + +/* + * Interface Descriptor + */ +#ifdef __ICCARM__ +typedef struct usb_interface_descriptor /*!< Interface descriptor structure */ +{ + __packed uint8_t bLength; /*!< Length of interface descriptor */ + __packed uint8_t bDescriptorType; /*!< Descriptor type */ + __packed uint8_t bInterfaceNumber; /*!< Interface number */ + __packed uint8_t bAlternateSetting;/*!< Alternate setting number */ + __packed uint8_t bNumEndpoints; /*!< Number of endpoints */ + __packed uint8_t bInterfaceClass; /*!< Interface class code */ + __packed uint8_t bInterfaceSubClass; /*!< Interface subclass code */ + __packed uint8_t bInterfaceProtocol; /*!< Interface protocol code */ + __packed uint8_t iInterface; /*!< Interface ID */ +} DESC_IF_T; /*!< Interface descriptor structure */ +#else +typedef struct __attribute__((__packed__)) usb_interface_descriptor /*!< Interface descriptor structure */ +{ + uint8_t bLength; /*!< Length of interface descriptor */ + uint8_t bDescriptorType; /*!< Descriptor type */ + uint8_t bInterfaceNumber; /*!< Interface number */ + uint8_t bAlternateSetting; /*!< Alternate setting number */ + uint8_t bNumEndpoints; /*!< Number of endpoints */ + uint8_t bInterfaceClass; /*!< Interface class code */ + uint8_t bInterfaceSubClass; /*!< Interface subclass code */ + uint8_t bInterfaceProtocol; /*!< Interface protocol code */ + uint8_t iInterface; /*!< Interface ID */ +} DESC_IF_T; /*!< Interface descriptor structure */ +#endif + +/* + * Interface descriptor bInterfaceClass[7:0] + */ +#if 0 +#define USB_CLASS_AUDIO 0x01 +#define USB_CLASS_COMM 0x02 +#define USB_CLASS_HID 0x03 +#define USB_CLASS_PRINTER 0x07 +#define USB_CLASS_MASS_STORAGE 0x08 +#define USB_CLASS_HUB 0x09 +#define USB_CLASS_DATA 0x0A +#define USB_CLASS_VIDEO 0x0E +#endif +/* + * Endpoint Descriptor + */ +#ifdef __ICCARM__ +typedef struct usb_endpoint_descriptor /*!< Endpoint descriptor structure */ +{ + __packed uint8_t bLength; /*!< Length of endpoint descriptor */ + __packed uint8_t bDescriptorType; /*!< Descriptor type */ + __packed uint8_t bEndpointAddress; /*!< Endpoint address */ + __packed uint8_t bmAttributes; /*!< Endpoint attribute */ + __packed uint16_t wMaxPacketSize; /*!< Maximum packet size */ + __packed uint8_t bInterval; /*!< Synchronous transfer interval */ + __packed uint8_t bRefresh; /*!< Refresh */ + __packed uint8_t bSynchAddress; /*!< Sync address */ +} DESC_EP_T; /*!< Endpoint descriptor structure */ +#else +typedef struct __attribute__((__packed__)) usb_endpoint_descriptor /*!< Endpoint descriptor structure */ +{ + uint8_t bLength; /*!< Length of endpoint descriptor */ + uint8_t bDescriptorType; /*!< Descriptor type */ + uint8_t bEndpointAddress; /*!< Endpoint address */ + uint8_t bmAttributes; /*!< Endpoint attribute */ + uint16_t wMaxPacketSize; /*!< Maximum packet size */ + uint8_t bInterval; /*!< Synchronous transfer interval */ + uint8_t bRefresh; /*!< Refresh */ + uint8_t bSynchAddress; /*!< Sync address */ +} DESC_EP_T; /*!< Endpoint descriptor structure */ +#endif + +/* + * Endpoint descriptor bEndpointAddress[7] - direction + */ +#define EP_ADDR_DIR_MASK 0x80 +#define EP_ADDR_DIR_IN 0x80 +#define EP_ADDR_DIR_OUT 0x00 + +/* + * Endpoint descriptor bmAttributes[1:0] - transfer type + */ +#define EP_ATTR_TT_MASK 0x03 +#define EP_ATTR_TT_CTRL 0x00 +#define EP_ATTR_TT_ISO 0x01 +#define EP_ATTR_TT_BULK 0x02 +#define EP_ATTR_TT_INT 0x03 + + +/*----------------------------------------------------------------------------------*/ +/* USB Host controller driver */ +/*----------------------------------------------------------------------------------*/ +typedef struct +{ + int (*init) (void); + void (*shutdown) (void); + void (*suspend) (void); + void (*resume) (void); + int (*ctrl_xfer)(struct utr_t *utr); + int (*bulk_xfer)(struct utr_t *utr); + int (*int_xfer)(struct utr_t *utr); + int (*iso_xfer)(struct utr_t *utr); + int (*quit_xfer)(struct utr_t *utr, struct ep_info_t *ep); + + /* root hub support */ + int (*rthub_port_reset)(int port); + int (*rthub_polling) (void); +} HC_DRV_T; + + +/*----------------------------------------------------------------------------------*/ +/* USB device driver */ +/*----------------------------------------------------------------------------------*/ +typedef struct +{ + int (*probe) (struct iface_t *iface); + void (*disconnect) (struct iface_t *iface); + void (*suspend) (struct iface_t *iface); + void (*resume) (struct iface_t *iface); +} UDEV_DRV_T; + + +/*----------------------------------------------------------------------------------*/ +/* USB device */ +/*----------------------------------------------------------------------------------*/ + +typedef enum +{ + SPEED_LOW, + SPEED_FULL, + SPEED_HIGH +} SPEED_E; + +typedef struct ep_info_t +{ + uint8_t bEndpointAddress; + uint8_t bmAttributes; + uint8_t bInterval; + uint8_t bToggle; + uint16_t wMaxPacketSize; + void *hw_pipe; /*!< point to the HC assocaied endpoint \hideinitializer */ +} EP_INFO_T; + +typedef struct udev_t +{ + DESC_DEV_T descriptor; /*!< Device descriptor. \hideinitializer */ + struct hub_dev_t *parent; /*!< parent hub device \hideinitializer */ + uint8_t port_num; /*!< The hub port this device connected on \hideinitializer */ + uint8_t dev_num; /*!< device number \hideinitializer */ + int8_t cur_conf; /*!< Currentll selected configuration \hideinitializer */ + SPEED_E speed; /*!< device speed (low/full/high) \hideinitializer */ + /* + * The followings are lightweight USB stack internal used . + */ + uint8_t *cfd_buff; /*!< Configuration descriptor buffer. \hideinitializer */ + EP_INFO_T ep0; /*!< Endpoint 0 \hideinitializer */ + HC_DRV_T *hc_driver; /*!< host controller driver \hideinitializer */ + struct iface_t *iface_list; /*!< Working interface list \hideinitializer */ + struct udev_t *next; /*!< link for global usb device list \hideinitializer */ +} UDEV_T; + +typedef struct alt_iface_t +{ + DESC_IF_T *ifd; /*!< point to the location of this alternative interface descriptor in UDEV_T->cfd_buff */ + EP_INFO_T ep[MAX_EP_PER_IFACE]; /*!< endpoints of this alternative interface */ +} ALT_IFACE_T; + +typedef struct iface_t +{ + UDEV_T *udev; /*!< USB device \hideinitializer */ + uint8_t if_num; /*!< Interface number \hideinitializer */ + uint8_t num_alt; /*!< Number of alternative interface \hideinitializer */ + ALT_IFACE_T *aif; /*!< Point to the active alternative interface */ + ALT_IFACE_T alt[MAX_ALT_PER_IFACE]; /*!< List of alternative interface \hideinitializer */ + UDEV_DRV_T *driver; /*!< Interface associated driver \hideinitializer */ + void *context; /*!< Reference to device context \hideinitializer */ + struct iface_t *next; /*!< Point to next interface of the same device. Started from UDEV_T->iface_list \hideinitializer */ +} IFACE_T; + + +/*----------------------------------------------------------------------------------*/ +/* URB (USB Request Block) */ +/*----------------------------------------------------------------------------------*/ + +#define IF_PER_UTR 8 /* number of frames per UTR isochronous transfer (DO NOT modify it!) */ + +typedef void (*FUNC_UTR_T)(struct utr_t *); + +typedef struct utr_t +{ + UDEV_T *udev; /*!< point to associated USB device \hideinitializer */ + DEV_REQ_T setup; /*!< buffer for setup packet \hideinitializer */ + EP_INFO_T *ep; /*!< associated endpoint \hideinitializer */ + uint8_t *buff; /*!< transfer buffer \hideinitializer */ + uint8_t bIsTransferDone; /*!< tansfer done? \hideinitializer */ + uint32_t data_len; /*!< length of data to be transferred \hideinitializer */ + uint32_t xfer_len; /*!< length of transferred data \hideinitializer */ + uint8_t bIsoNewSched; /*!< New schedule isochronous transfer \hideinitializer */ + uint16_t iso_sf; /*!< Isochronous start frame number \hideinitializer */ + uint16_t iso_xlen[IF_PER_UTR]; /*!< transfer length of isochronous frames \hideinitializer */ + uint8_t * iso_buff[IF_PER_UTR]; /*!< transfer buffer address of isochronous frames \hideinitializer */ + int iso_status[IF_PER_UTR]; /*!< transfer status of isochronous frames \hideinitializer */ + int td_cnt; /*!< number of transfer descriptors \hideinitializer */ + int status; /*!< return status \hideinitializer */ + int interval; /*!< interrupt/isochronous interval \hideinitializer */ + void *context; /*!< point to deivce proprietary data area \hideinitializer */ + FUNC_UTR_T func; /*!< tansfer done call-back function \hideinitializer */ + struct utr_t *next; /* point to the next UTR of the same endpoint. \hideinitializer */ +} UTR_T; + + +/*----------------------------------------------------------------------------------*/ +/* Global variables */ +/*----------------------------------------------------------------------------------*/ +extern USBH_T *_ohci; +extern HSUSBH_T *_ehci; + +extern HC_DRV_T ohci_driver; +extern HC_DRV_T ehci_driver; + +extern UDEV_T * g_udev_list; + +/*----------------------------------------------------------------------------------*/ +/* USB stack exported functions */ +/*----------------------------------------------------------------------------------*/ +extern void usbh_delay_ms(int msec); + +extern void dump_ohci_regs(void); +extern void dump_ohci_ports(void); +extern void dump_ohci_int_table(void); +extern void dump_ehci_regs(void); +extern void dump_ehci_qtd(qTD_T *qtd); +extern void dump_ehci_asynclist(void); +extern void dump_ehci_period_frame_list_simple(void); +extern void usbh_dump_buff_bytes(uint8_t *buff, int nSize); +extern void usbh_dump_interface_descriptor(DESC_IF_T *if_desc); +extern void usbh_dump_endpoint_descriptor(DESC_EP_T *ep_desc); +extern void usbh_dump_iface(IFACE_T *iface); +extern void usbh_dump_ep_info(EP_INFO_T *ep); + +/* + * Memory management functions + */ +extern void usbh_memory_init(void); +extern uint32_t usbh_memory_used(void); +extern void * usbh_alloc_mem(int size); +extern void usbh_free_mem(void *p, int size); +extern int alloc_dev_address(void); +extern void free_dev_address(int dev_addr); +extern UDEV_T * alloc_device(void); +extern void free_device(UDEV_T *udev); +extern UTR_T * alloc_utr(UDEV_T *udev); +extern void free_utr(UTR_T *utr); +extern ED_T * alloc_ohci_ED(void); +extern void free_ohci_ED(ED_T *ed); +extern TD_T * alloc_ohci_TD(UTR_T *utr); +extern void free_ohci_TD(TD_T *td); +extern QH_T * alloc_ehci_QH(void); +extern void free_ehci_QH(QH_T *qh); +extern qTD_T * alloc_ehci_qTD(UTR_T *utr); +extern void free_ehci_qTD(qTD_T *qtd); +extern iTD_T * alloc_ehci_iTD(void); +extern void free_ehci_iTD(iTD_T *itd); +extern siTD_T * alloc_ehci_siTD(void); +extern void free_ehci_siTD(siTD_T *sitd); + + +extern void usbh_hub_init(void); +extern int usbh_connect_device(UDEV_T *); +extern void usbh_disconnect_device(UDEV_T *); +extern int usbh_register_driver(UDEV_DRV_T *driver); +extern EP_INFO_T * usbh_iface_find_ep(IFACE_T *iface, uint8_t ep_addr, uint8_t dir_type); +extern int usbh_reset_device(UDEV_T *); +extern int usbh_reset_port(UDEV_T *); + +/* + * USB Standard Request functions + */ +extern int usbh_get_device_descriptor(UDEV_T *udev, DESC_DEV_T *desc_buff); +extern int usbh_get_config_descriptor(UDEV_T *udev, uint8_t *desc_buff, int buff_len); +extern int usbh_set_configuration(UDEV_T *udev, uint8_t conf_val); +extern int usbh_set_interface(IFACE_T *iface, uint16_t alt_setting); +extern int usbh_clear_halt(UDEV_T *udev, uint16_t ep_addr); + +extern int usbh_ctrl_xfer(UDEV_T *udev, uint8_t bmRequestType, uint8_t bRequest, uint16_t wValue, uint16_t wIndex, uint16_t wLength, uint8_t *buff, uint32_t *xfer_len, uint32_t timeout); +extern int usbh_bulk_xfer(UTR_T *utr); +extern int usbh_int_xfer(UTR_T *utr); +extern int usbh_iso_xfer(UTR_T *utr); +extern int usbh_quit_utr(UTR_T *utr); +extern int usbh_quit_xfer(UDEV_T *udev, EP_INFO_T *ep); + + +/// @endcond HIDDEN_SYMBOLS + +#endif /* _USBH_H_ */ diff --git a/bsp/nuvoton/libraries/m480/USBHostLib/inc/usbh_lib.h b/bsp/nuvoton/libraries/m480/USBHostLib/inc/usbh_lib.h new file mode 100644 index 0000000000000000000000000000000000000000..7b8795b72e640878f466d620e4106be0f9b080a1 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/USBHostLib/inc/usbh_lib.h @@ -0,0 +1,186 @@ +/**************************************************************************//** + * @file usbh_lib.h + * @version V1.10 + * @brief USB Host library exported header file. + * + * SPDX-License-Identifier: Apache-2.0 + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef _USBH_LIB_H_ +#define _USBH_LIB_H_ + +#include "NuMicro.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup LIBRARY Library + @{ +*/ + +/** @addtogroup USBH_Library USB Host Library + @{ +*/ + +/** @addtogroup USBH_EXPORTED_CONSTANTS USB Host Exported Constants + @{ +*/ + +#define USBH_OK 0 /*!< No error. */ +#define USBH_ERR_MEMORY_OUT -10 /*!< Out of memory. */ +#define USBH_ERR_IF_ALT_LIMIT -11 /*!< Number of alternative interface > MAX_ALT_PER_IFACE */ +#define USBH_ERR_IF_EP_LIMIT -15 /*!< Number of endpoints > MAX_EP_PER_IFACE */ +#define USBH_ERR_NOT_SUPPORTED -101 /*!< Device/Class/Transfer not supported */ +#define USBH_ERR_NOT_MATCHED -103 /*!< Not macthed */ +#define USBH_ERR_NOT_EXPECTED -104 /*!< Unknown or unexpected */ +#define USBH_ERR_INVALID_PARAM -105 /*!< Invalid parameter */ +#define USBH_ERR_NOT_FOUND -106 /*!< Device or interface not found */ +#define USBH_ERR_EP_NOT_FOUND -107 /*!< Endpoint not found */ +#define USBH_ERR_DESCRIPTOR -137 /*!< Failed to parse USB descriptors */ +#define USBH_ERR_SET_DEV_ADDR -139 /*!< Failed to set device address */ +#define USBH_ERR_SET_CONFIG -151 /*!< Failed to set device configuration */ + +#define USBH_ERR_TRANSFER -201 /*!< USB transfer error */ +#define USBH_ERR_TIMEOUT -203 /*!< USB transfer time-out */ +#define USBH_ERR_ABORT -205 /*!< USB transfer aborted due to disconnect or reset */ +#define USBH_ERR_PORT_RESET -255 /*!< Hub port reset failed */ +#define USBH_ERR_SCH_OVERRUN -257 /*!< USB isochronous schedule overrun */ +#define USBH_ERR_DISCONNECTED -259 /*!< USB device was disconnected */ + +#define USBH_ERR_TRANSACTION -271 /*!< USB transaction timeout, CRC, Bad PID, etc. */ +#define USBH_ERR_BABBLE_DETECTED -272 /*!< A babble is detected during the transaction */ +#define USBH_ERR_DATA_BUFF -274 /*!< Data buffer overrun or underrun */ + +#define USBH_ERR_CC_NO_ERR -280 /*!< OHCI CC code - no error */ +#define USBH_ERR_CRC -281 /*!< USB trasfer CRC error */ +#define USBH_ERR_BIT_STUFF -282 /*!< USB transfer bit stuffing error */ +#define USBH_ERR_DATA_TOGGLE -283 /*!< USB trasfer data toggle error */ +#define USBH_ERR_STALL -284 /*!< USB trasfer STALL error */ +#define USBH_ERR_DEV_NO_RESP -285 /*!< USB trasfer device no response error */ +#define USBH_ERR_PID_CHECK -286 /*!< USB trasfer PID check failure */ +#define USBH_ERR_UNEXPECT_PID -287 /*!< USB trasfer unexpected PID error */ +#define USBH_ERR_DATA_OVERRUN -288 /*!< USB trasfer data overrun error */ +#define USBH_ERR_DATA_UNDERRUN -289 /*!< USB trasfer data underrun error */ +#define USBH_ERR_BUFF_OVERRUN -292 /*!< USB trasfer buffer overrun error */ +#define USBH_ERR_BUFF_UNDERRUN -293 /*!< USB trasfer buffer underrun error */ +#define USBH_ERR_NOT_ACCESS0 -294 /*!< USB trasfer not accessed error */ +#define USBH_ERR_NOT_ACCESS1 -295 /*!< USB trasfer not accessed error */ + +#define USBH_ERR_OHCI_INIT -301 /*!< Failed to initialize OHIC controller. */ +#define USBH_ERR_OHCI_EP_BUSY -303 /*!< The endpoint is under transfer. */ + +#define USBH_ERR_EHCI_INIT -501 /*!< Failed to initialize EHCI controller. */ +#define USBH_ERR_EHCI_QH_BUSY -503 /*!< the Queue Head is busy. */ + +#define UMAS_OK 0 /*!< No error. */ +#define UMAS_ERR_NO_DEVICE -1031 /*!< No Mass Stroage Device found. */ +#define UMAS_ERR_IO -1033 /*!< Device read/write failed. */ +#define UMAS_ERR_INIT_DEVICE -1035 /*!< failed to init MSC device */ +#define UMAS_ERR_CMD_STATUS -1037 /*!< SCSI command status failed */ +#define UMAS_ERR_IVALID_PARM -1038 /*!< Invalid parameter. */ +#define UMAS_ERR_DRIVE_NOT_FOUND -1039 /*!< drive not found */ + +#define HID_RET_OK 0 /*!< Return with no errors. */ +#define HID_RET_DEV_NOT_FOUND -1081 /*!< HID device not found or removed. */ +#define HID_RET_IO_ERR -1082 /*!< USB transfer failed. */ +#define HID_RET_INVALID_PARAMETER -1083 /*!< Invalid parameter. */ +#define HID_RET_OUT_OF_MEMORY -1084 /*!< Out of memory. */ +#define HID_RET_NOT_SUPPORTED -1085 /*!< Function not supported. */ +#define HID_RET_EP_NOT_FOUND -1086 /*!< Endpoint not found. */ +#define HID_RET_PARSING -1087 /*!< Failed to parse HID descriptor */ +#define HID_RET_XFER_IS_RUNNING -1089 /*!< The transfer has been enabled. */ +#define HID_RET_REPORT_NOT_FOUND -1090 /*!< The transfer has been enabled. */ + +#define UAC_RET_OK 0 /*!< Return with no errors. */ +#define UAC_RET_DEV_NOT_FOUND -2001 /*!< Audio Class device not found or removed. */ +#define UAC_RET_FUNC_NOT_FOUND -2002 /*!< Audio device has no this function. */ +#define UAC_RET_IO_ERR -2003 /*!< USB transfer failed. */ +#define UAC_RET_DATA_LEN -2004 /*!< Unexpected transfer length */ +#define UAC_RET_INVALID -2005 /*!< Invalid parameter or usage. */ +#define UAC_RET_OUT_OF_MEMORY -2007 /*!< Out of memory. */ +#define UAC_RET_DRV_NOT_SUPPORTED -2009 /*!< Function not supported by this UAC driver. */ +#define UAC_RET_DEV_NOT_SUPPORTED -2011 /*!< Function not supported by the UAC device. */ +#define UAC_RET_PARSER -2013 /*!< Failed to parse UAC descriptor */ +#define UAC_RET_IS_STREAMING -2015 /*!< Audio pipe is on streaming. */ + + +/*@}*/ /* end of group USBH_EXPORTED_CONSTANTS */ + + +/** @addtogroup USBH_EXPORTED_TYPEDEF USB Host Typedef + @{ +*/ +struct udev_t; +typedef void (CONN_FUNC)(struct udev_t *udev, int param); + +struct line_coding_t; +struct cdc_dev_t; +typedef void (CDC_CB_FUNC)(struct cdc_dev_t *cdev, uint8_t *rdata, int data_len); + +struct usbhid_dev; +typedef void (HID_IR_FUNC)(struct usbhid_dev *hdev, uint16_t ep_addr, int status, uint8_t *rdata, uint32_t data_len); /*!< interrupt in callback function \hideinitializer */ +typedef void (HID_IW_FUNC)(struct usbhid_dev *hdev, uint16_t ep_addr, int status, uint8_t *wbuff, uint32_t *data_len); /*!< interrupt out callback function \hideinitializer */ + +struct uac_dev_t; +typedef int (UAC_CB_FUNC)(struct uac_dev_t *dev, uint8_t *data, int len); /*!< audio in callback function \hideinitializer */ + +/*@}*/ /* end of group USBH_EXPORTED_STRUCT */ + + + +/** @addtogroup USBH_EXPORTED_FUNCTIONS USB Host Exported Functions + @{ +*/ + +/*------------------------------------------------------------------*/ +/* */ +/* USB Core Library APIs */ +/* */ +/*------------------------------------------------------------------*/ +extern void usbh_core_init(void); +extern int usbh_pooling_root_hubs(void); +extern void usbh_install_conn_callback(CONN_FUNC *conn_func, CONN_FUNC *disconn_func); +extern void usbh_suspend(void); +extern void usbh_resume(void); +extern struct udev_t * usbh_find_device(char *hub_id, int port); + +/** + * @brief A function return current tick count. + * @return Current tick. + * @details User application must provide this function to return current tick. + * The tick should increase by 1 for every 10 ms. + */ +extern uint32_t usbh_get_ticks(void); /* This function must be provided by user application. */ +extern uint32_t usbh_tick_from_millisecond(uint32_t msec); /* This function must be provided by user application. */ + + +/// @cond HIDDEN_SYMBOLS + +extern void dump_ohci_regs(void); +extern void dump_ehci_regs(void); +extern void dump_ohci_ports(void); +extern void dump_ehci_ports(void); +extern uint32_t usbh_memory_used(void); + +/// @endcond HIDDEN_SYMBOLS + + +/*@}*/ /* end of group USBH_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USBH_Library */ + +/*@}*/ /* end of group LIBRARY */ + +#ifdef __cplusplus +} +#endif + +#endif /* _USBH_LIB_H_ */ + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ + + + diff --git a/bsp/nuvoton/libraries/m480/USBHostLib/src/ehci.c b/bsp/nuvoton/libraries/m480/USBHostLib/src/ehci.c new file mode 100644 index 0000000000000000000000000000000000000000..9138c237a492e4387799ed8bf853adb56d91b184 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/USBHostLib/src/ehci.c @@ -0,0 +1,1306 @@ +/**************************************************************************//** + * @file ehci.c + * @version V1.10 + * @brief USB Host library EHCI (USB 2.0) host controller driver. + * + * SPDX-License-Identifier: Apache-2.0 + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include +#include + +#include "NuMicro.h" + +#include "usb.h" +#include "hub.h" + + +/// @cond HIDDEN_SYMBOLS + +static QH_T *_H_qh; /* head of reclamation list */ +static qTD_T *_ghost_qtd; /* used as a terminator qTD */ +static QH_T *qh_remove_list; + +extern ISO_EP_T *iso_ep_list; /* list of activated isochronous pipes */ +extern int ehci_iso_xfer(UTR_T *utr); /* EHCI isochronous transfer function */ +extern int ehci_quit_iso_xfer(UTR_T *utr, EP_INFO_T *ep); + +#ifdef __ICCARM__ +#pragma data_alignment=4096 +uint32_t _PFList[FL_SIZE]; /* Periodic frame list (IAR) */ +#else +uint32_t _PFList[FL_SIZE] __attribute__((aligned(4096))); /* Periodic frame list */ +#endif + +QH_T * _Iqh[NUM_IQH]; + + +#ifdef ENABLE_ERROR_MSG +void dump_ehci_regs() +{ + USB_debug("Dump HSUSBH(EHCI) registers:\n"); + USB_debug(" UCMDR = 0x%x\n", _ehci->UCMDR); + USB_debug(" USTSR = 0x%x\n", _ehci->USTSR); + USB_debug(" UIENR = 0x%x\n", _ehci->UIENR); + USB_debug(" UFINDR = 0x%x\n", _ehci->UFINDR); + USB_debug(" UPFLBAR = 0x%x\n", _ehci->UPFLBAR); + USB_debug(" UCALAR = 0x%x\n", _ehci->UCALAR); + USB_debug(" UASSTR = 0x%x\n", _ehci->UASSTR); + USB_debug(" UCFGR = 0x%x\n", _ehci->UCFGR); + USB_debug(" UPSCR = 0x%x\n", _ehci->UPSCR[0]); + USB_debug(" PHYCTL0 = 0x%x\n", _ehci->USBPCR0); + USB_debug(" PHYCTL1 = 0x%x\n", _ehci->USBPCR1); +} + +void dump_ehci_ports() +{ + USB_debug("_ehci port0=0x%x, port1=0x%x\n", _ehci->UPSCR[0], _ehci->UPSCR[1]); +} + +void dump_ehci_qtd(qTD_T *qtd) +{ + USB_debug(" [qTD] - 0x%08x\n", (int)qtd); + USB_debug(" 0x%08x (Next qtd Pointer)\n", qtd->Next_qTD); + USB_debug(" 0x%08x (Alternate Next qtd Pointer)\n", qtd->Alt_Next_qTD); + USB_debug(" 0x%08x (qtd Token) PID: %s, Bytes: %d, IOC: %d\n", qtd->Token, (((qtd->Token>>8)&0x3)==0) ? "OUT" : ((((qtd->Token>>8)&0x3)==1) ? "IN" : "SETUP"), (qtd->Token>>16)&0x7FFF, (qtd->Token>>15)&0x1); + USB_debug(" 0x%08x (Buffer Pointer (page 0))\n", qtd->Bptr[0]); + //USB_debug(" 0x%08x (Buffer Pointer (page 1))\n", qtd->Bptr[1]); + //USB_debug(" 0x%08x (Buffer Pointer (page 2))\n", qtd->Bptr[2]); + //USB_debug(" 0x%08x (Buffer Pointer (page 3))\n", qtd->Bptr[3]); + //USB_debug(" 0x%08x (Buffer Pointer (page 4))\n", qtd->Bptr[4]); + USB_debug("\n"); +} + +void dump_ehci_asynclist(void) +{ + QH_T *qh = _H_qh; + qTD_T *qtd; + + USB_debug(">>> Dump EHCI Asynchronous List <<<\n"); + do + { + USB_debug("[QH] - 0x%08x\n", (int)qh); + USB_debug(" 0x%08x (Queue Head Horizontal Link Pointer, Queue Head DWord 0)\n", qh->HLink); + USB_debug(" 0x%08x (Endpoint Characteristics) DevAddr: %d, EP: 0x%x, PktSz: %d, Speed: %s\n", qh->Chrst, qh->Chrst&0x7F, (qh->Chrst>>8)&0xF, (qh->Chrst>>16)&0x7FF, ((qh->Chrst>>12)&0x3 == 0) ? "Full" : (((qh->Chrst>>12)&0x3 == 1) ? "Low" : "High")); + USB_debug(" 0x%08x (Endpoint Capabilities: Queue Head DWord 2)\n", qh->Cap); + USB_debug(" 0x%08x (Current qtd Pointer)\n", qh->Curr_qTD); + USB_debug(" --- Overlay Area ---\n"); + USB_debug(" 0x%08x (Next qtd Pointer)\n", qh->OL_Next_qTD); + USB_debug(" 0x%08x (Alternate Next qtd Pointer)\n", qh->OL_Alt_Next_qTD); + USB_debug(" 0x%08x (qtd Token)\n", qh->OL_Token); + USB_debug(" 0x%08x (Buffer Pointer (page 0))\n", qh->OL_Bptr[0]); + USB_debug("\n"); + + qtd = QTD_PTR(qh->Curr_qTD); + while (qtd != NULL) + { + dump_ehci_qtd(qtd); + qtd = QTD_PTR(qtd->Next_qTD); + } + qh = QH_PTR(qh->HLink); + } + while (qh != _H_qh); +} + +void dump_ehci_asynclist_simple(void) +{ + QH_T *qh = _H_qh; + + USB_debug(">>> EHCI Asynchronous List <<<\n"); + USB_debug("[QH] => "); + do + { + USB_debug("0x%08x ", (int)qh); + qh = QH_PTR(qh->HLink); + } + while (qh != _H_qh); + USB_debug("\n"); +} + +void dump_ehci_period_frame_list_simple(void) +{ + QH_T *qh = _Iqh[NUM_IQH-1]; + + USB_debug(">>> EHCI period frame list simple <<<\n"); + USB_debug("[FList] => "); + do + { + USB_debug("0x%08x ", (int)qh); + qh = QH_PTR(qh->HLink); + } + while (qh != NULL); + USB_debug("\n"); +} + +void dump_ehci_period_frame_list() +{ + int i; + QH_T *qh; + + for (i = 0; i < FL_SIZE; i++) + { + USB_debug("!%02d: ", i); + qh = QH_PTR(_PFList[i]);; + while (qh != NULL) + { + // USB_debug("0x%x (0x%x) => ", (int)qh, qh->HLink); + USB_debug("0x%x => ", (int)qh); + qh = QH_PTR(qh->HLink); + } + USB_debug("0\n"); + } +} + +#endif /* ENABLE_ERROR_MSG */ + +static void init_periodic_frame_list() +{ + QH_T *qh_p; + int i, idx, interval; + + memset(_PFList, 0, sizeof(_PFList)); + + iso_ep_list = NULL; + + for (i = NUM_IQH-1; i >= 0; i--) /* interval = i^2 */ + { + _Iqh[i] = alloc_ehci_QH(); + + _Iqh[i]->HLink = QH_HLNK_END; + _Iqh[i]->Curr_qTD = (uint32_t)_ghost_qtd; + _Iqh[i]->OL_Next_qTD = QTD_LIST_END; + _Iqh[i]->OL_Alt_Next_qTD = (uint32_t)_ghost_qtd; + _Iqh[i]->OL_Token = QTD_STS_HALT; + + interval = 0x1 << i; + + for (idx = interval - 1; idx < FL_SIZE; idx += interval) + { + if (_PFList[idx] == 0) /* is empty list, insert directly */ + { + _PFList[idx] = QH_HLNK_QH(_Iqh[i]); + } + else + { + qh_p = QH_PTR(_PFList[idx]); + + while (1) + { + if (qh_p == _Iqh[i]) + break; /* already chained by previous visit */ + + if (qh_p->HLink == QH_HLNK_END) /* reach end of list? */ + { + qh_p->HLink = QH_HLNK_QH(_Iqh[i]); + break; + } + qh_p = QH_PTR(qh_p->HLink); + } + } + } + } +} + +static QH_T * get_int_tree_head_node(int interval) +{ + int i; + + interval /= 8; /* each frame list entry for 8 micro-frame */ + + for (i = 0; i < NUM_IQH-1; i++) + { + interval >>= 1; + if (interval == 0) + return _Iqh[i]; + } + return _Iqh[NUM_IQH-1]; +} + +static int make_int_s_mask(int bInterval) +{ + int order, interval; + + interval = 1; + while (bInterval > 1) + { + interval *= 2; + bInterval--; + } + + if (interval < 2) + return 0xFF; /* interval 1 */ + if (interval < 4) + return 0x55; /* interval 2 */ + if (interval < 8) + return 0x22; /* interval 4 */ + for (order = 0; (interval > 1); order++) + { + interval >>= 1; + } + return (0x1 << (order % 8)); +} + +static int ehci_init(void) +{ + int timeout = 250*1000; /* EHCI reset time-out 250 ms */ + + /*------------------------------------------------------------------------------------*/ + /* Reset EHCI host controller */ + /*------------------------------------------------------------------------------------*/ + _ehci->UCMDR = HSUSBH_UCMDR_HCRST_Msk; + while ((_ehci->UCMDR & HSUSBH_UCMDR_HCRST_Msk) && (timeout > 0)) + { + usbh_delay_ms(1); + timeout -= 1000; + } + if (_ehci->UCMDR & HSUSBH_UCMDR_HCRST_Msk) + return USBH_ERR_EHCI_INIT; + + _ehci->UCMDR = UCMDR_INT_THR_CTRL | HSUSBH_UCMDR_RUN_Msk; + + _ghost_qtd = alloc_ehci_qTD(NULL); + _ghost_qtd->Token = 0x11197B3F; //QTD_STS_HALT; visit_qtd() will not remove a qTD with this mark. It represents a qhost qTD. + + /*------------------------------------------------------------------------------------*/ + /* Initialize asynchronous list */ + /*------------------------------------------------------------------------------------*/ + qh_remove_list = NULL; + + /* Create the QH list head with H-bit 1 */ + _H_qh = alloc_ehci_QH(); + _H_qh->HLink = QH_HLNK_QH(_H_qh); /* circular link to itself, the only one QH */ + _H_qh->Chrst = QH_RCLM_LIST_HEAD; /* it's the head of reclamation list */ + _H_qh->Curr_qTD = (uint32_t)_ghost_qtd; + _H_qh->OL_Next_qTD = QTD_LIST_END; + _H_qh->OL_Alt_Next_qTD = (uint32_t)_ghost_qtd; + _H_qh->OL_Token = QTD_STS_HALT; + _ehci->UCALAR = (uint32_t)_H_qh; + + /*------------------------------------------------------------------------------------*/ + /* Initialize periodic list */ + /*------------------------------------------------------------------------------------*/ + if (FL_SIZE == 256) + _ehci->UCMDR |= (0x2<UCMDR |= (0x1<UCMDR |= (0x0<UPFLBAR = (uint32_t)_PFList; + + /*------------------------------------------------------------------------------------*/ + /* start run */ + /*------------------------------------------------------------------------------------*/ + + _ehci->UCFGR = 0x1; /* enable port routing to EHCI */ + _ehci->UIENR = HSUSBH_UIENR_USBIEN_Msk | HSUSBH_UIENR_UERRIEN_Msk | HSUSBH_UIENR_HSERREN_Msk | HSUSBH_UIENR_IAAEN_Msk; + + usbh_delay_ms(1); /* delay 1 ms */ + + _ehci->UPSCR[0] = HSUSBH_UPSCR_PP_Msk; /* enable port 1 port power */ + _ehci->UPSCR[1] = HSUSBH_UPSCR_PP_Msk | HSUSBH_UPSCR_PO_Msk; /* set port 2 owner to OHCI */ + + init_periodic_frame_list(); + + usbh_delay_ms(10); /* delay 10 ms */ + + return 0; +} + +static void ehci_suspend(void) +{ + if (_ehci->UPSCR[0] & 0x1) + _ehci->UPSCR[0] |= HSUSBH_UPSCR_SUSPEND_Msk; +} + +static void ehci_resume(void) +{ + if (_ehci->UPSCR[0] & 0x1) + _ehci->UPSCR[0] = (HSUSBH->UPSCR[0] & ~HSUSBH_UPSCR_SUSPEND_Msk) | HSUSBH_UPSCR_FPR_Msk; +} + +static void ehci_shutdown(void) +{ + ehci_suspend(); +} + +static void move_qh_to_remove_list(QH_T *qh) +{ + QH_T *q; + + // USB_debug("move_qh_to_remove_list - 0x%x (0x%x)\n", (int)qh, qh->Chrst); + + /* check if this ED found in ed_remove_list */ + q = qh_remove_list; + while (q) + { + if (q == qh) /* This QH found in qh_remove_list. */ + { + return; /* Do nothing, return... */ + } + q = q->next; + } + + DISABLE_EHCI_IRQ(); + + /*------------------------------------------------------------------------------------*/ + /* Search asynchronous frame list and remove qh if found in list. */ + /*------------------------------------------------------------------------------------*/ + q = _H_qh; /* find and remove it from asynchronous list */ + while (QH_PTR(q->HLink) != _H_qh) + { + if (QH_PTR(q->HLink) == qh) + { + /* q's next QH is qh, found... */ + q->HLink = qh->HLink; /* remove qh from list */ + + qh->next = qh_remove_list; /* add qh to qh_remove_list */ + qh_remove_list = qh; + _ehci->UCMDR |= HSUSBH_UCMDR_IAAD_Msk; /* trigger IAA interrupt */ + ENABLE_EHCI_IRQ(); + return; /* done */ + } + q = QH_PTR(q->HLink); /* advance to next QH in asynchronous list */ + } + + /*------------------------------------------------------------------------------------*/ + /* Search periodic frame list and remove qh if found in list. */ + /*------------------------------------------------------------------------------------*/ + q = _Iqh[NUM_IQH-1]; + while (q->HLink != QH_HLNK_END) + { + if (QH_PTR(q->HLink) == qh) + { + /* q's next QH is qh, found... */ + q->HLink = qh->HLink; /* remove qh from list */ + + qh->next = qh_remove_list; /* add qh to qh_remove_list */ + qh_remove_list = qh; + _ehci->UCMDR |= HSUSBH_UCMDR_IAAD_Msk; /* trigger IAA interrupt */ + ENABLE_EHCI_IRQ(); + return; /* done */ + } + q = QH_PTR(q->HLink); /* advance to next QH in asynchronous list */ + } + ENABLE_EHCI_IRQ(); +} + +static void append_to_qtd_list_of_QH(QH_T *qh, qTD_T *qtd) +{ + qTD_T *q; + + if (qh->qtd_list == NULL) + { + qh->qtd_list = qtd; + } + else + { + q = qh->qtd_list; + while (q->next != NULL) + { + q = q->next; + } + q->next = qtd; + } +} + +/* + * If ep==NULL, it's a control endpoint QH. + */ +static void write_qh(UDEV_T *udev, EP_INFO_T *ep, QH_T *qh) +{ + uint32_t chrst, cap; + + /*------------------------------------------------------------------------------------*/ + /* Write QH DWord 1 - Endpoint Characteristics */ + /*------------------------------------------------------------------------------------*/ + if (ep == NULL) /* is control endpoint? */ + { + if (udev->descriptor.bMaxPacketSize0 == 0) + { + if (udev->speed == SPEED_LOW) /* give a default maximum packet size */ + udev->descriptor.bMaxPacketSize0 = 8; + else + udev->descriptor.bMaxPacketSize0 = 64; + } + chrst = QH_DTC | QH_NAK_RL | (udev->descriptor.bMaxPacketSize0 << 16); + if (udev->speed != SPEED_HIGH) + chrst |= QH_CTRL_EP_FLAG; /* non-high-speed control endpoint */ + } + else /* not a control endpoint */ + { + chrst = QH_NAK_RL | (ep->wMaxPacketSize << 16); + chrst |= ((ep->bEndpointAddress & 0xf) << 8); /* Endpoint Address */ + } + + if (udev->speed == SPEED_LOW) + chrst |= QH_EPS_LOW; + else if (udev->speed == SPEED_FULL) + chrst |= QH_EPS_FULL; + else + chrst |= QH_EPS_HIGH; + + chrst |= udev->dev_num; + + qh->Chrst = chrst; + + /*------------------------------------------------------------------------------------*/ + /* Write QH DWord 2 - Endpoint Capabilities */ + /*------------------------------------------------------------------------------------*/ + if (udev->speed == SPEED_HIGH) + { + cap = 0; + } + else + { + /* + * Backtrace device tree until the USB 2.0 hub found + */ + HUB_DEV_T *hub; + int port_num; + + port_num = udev->port_num; + hub = udev->parent; + + while ((hub != NULL) && (hub->iface->udev->speed != SPEED_HIGH)) + { + port_num = hub->iface->udev->port_num; + hub = hub->iface->udev->parent; + } + + cap = (port_num << QH_HUB_PORT_Pos) | + (hub->iface->udev->dev_num << QH_HUB_ADDR_Pos); + } + + qh->Cap = cap; +} + +static void write_qtd_bptr(qTD_T *qtd, uint32_t buff_addr, int xfer_len) +{ + int i; + + qtd->xfer_len = xfer_len; + qtd->Bptr[0] = buff_addr; + + buff_addr = (buff_addr + 0x1000) & ~0xFFF; + + for (i = 1; i < 5; i++) + { + qtd->Bptr[i] = buff_addr; + buff_addr += 0x1000; + } +} + +static int ehci_ctrl_xfer(UTR_T *utr) +{ + UDEV_T *udev; + QH_T *qh; + qTD_T *qtd_setup, *qtd_data, *qtd_status; + uint32_t token; + int is_new_qh = 0; + + udev = utr->udev; + + if (utr->data_len > 0) + { + if (((uint32_t)utr->buff + utr->data_len) > (((uint32_t)utr->buff & ~0xFFF)+0x5000)) + return USBH_ERR_BUFF_OVERRUN; + } + + /*------------------------------------------------------------------------------------*/ + /* Allocate and link QH */ + /*------------------------------------------------------------------------------------*/ + if (udev->ep0.hw_pipe != NULL) + { + qh = (QH_T *)udev->ep0.hw_pipe; + if (qh->qtd_list) + return USBH_ERR_EHCI_QH_BUSY; + } + else + { + qh = alloc_ehci_QH(); + if (qh == NULL) + return USBH_ERR_MEMORY_OUT; + + udev->ep0.hw_pipe = (void *)qh; /* driver can find QH from EP */ + is_new_qh = 1; + } + write_qh(udev, NULL, qh); + utr->ep = &udev->ep0; /* driver can find EP from UTR */ + + /*------------------------------------------------------------------------------------*/ + /* Allocate qTDs */ + /*------------------------------------------------------------------------------------*/ + qtd_setup = alloc_ehci_qTD(utr); /* allocate qTD for SETUP */ + + if (utr->data_len > 0) + qtd_data = alloc_ehci_qTD(utr); /* allocate qTD for DATA */ + else + qtd_data = NULL; + + qtd_status = alloc_ehci_qTD(utr); /* allocate qTD for USTSR */ + + if (qtd_status == NULL) /* out of memory? */ + { + if (qtd_setup) + free_ehci_qTD(qtd_setup); /* free memory */ + if (qtd_data) + free_ehci_qTD(qtd_data); /* free memory */ + return USBH_ERR_MEMORY_OUT; /* out of memory */ + } + + // USB_debug("qh=0x%x, qtd_setup=0x%x, qtd_data=0x%x, qtd_status=0x%x\n", (int)qh, (int)qtd_setup, (int)qtd_data, (int)qtd_status); + + /*------------------------------------------------------------------------------------*/ + /* prepare SETUP stage qTD */ + /*------------------------------------------------------------------------------------*/ + qtd_setup->qh = qh; + //qtd_setup->utr = utr; + write_qtd_bptr(qtd_setup, (uint32_t)&utr->setup, 8); + append_to_qtd_list_of_QH(qh, qtd_setup); + qtd_setup->Token = (8 << 16) | QTD_ERR_COUNTER | QTD_PID_SETUP | QTD_STS_ACTIVE; + + /*------------------------------------------------------------------------------------*/ + /* prepare DATA stage qTD */ + /*------------------------------------------------------------------------------------*/ + if (utr->data_len > 0) + { + qtd_setup->Next_qTD = (uint32_t)qtd_data; + qtd_data->Next_qTD = (uint32_t)qtd_status; + + if ((utr->setup.bmRequestType & 0x80) == REQ_TYPE_OUT) + token = QTD_ERR_COUNTER | QTD_PID_OUT | QTD_STS_ACTIVE; + else + token = QTD_ERR_COUNTER | QTD_PID_IN | QTD_STS_ACTIVE; + + qtd_data->qh = qh; + //qtd_data->utr = utr; + write_qtd_bptr(qtd_data, (uint32_t)utr->buff, utr->data_len); + append_to_qtd_list_of_QH(qh, qtd_data); + qtd_data->Token = QTD_DT | (utr->data_len << 16) | token; + } + else + { + qtd_setup->Next_qTD = (uint32_t)qtd_status; + } + + /*------------------------------------------------------------------------------------*/ + /* prepare USTSR stage qTD */ + /*------------------------------------------------------------------------------------*/ + qtd_status->Next_qTD = (uint32_t)_ghost_qtd; + qtd_status->Alt_Next_qTD = QTD_LIST_END; + + if ((utr->setup.bmRequestType & 0x80) == REQ_TYPE_OUT) + token = QTD_ERR_COUNTER | QTD_PID_IN | QTD_STS_ACTIVE; + else + token = QTD_ERR_COUNTER | QTD_PID_OUT | QTD_STS_ACTIVE; + + qtd_status->qh = qh; + //qtd_status->utr = utr; + append_to_qtd_list_of_QH(qh, qtd_status); + qtd_status->Token = QTD_DT | QTD_IOC | token; + + /*------------------------------------------------------------------------------------*/ + /* Update QH overlay */ + /*------------------------------------------------------------------------------------*/ + qh->Curr_qTD = 0; + qh->OL_Next_qTD = (uint32_t)qtd_setup; + qh->OL_Alt_Next_qTD = QTD_LIST_END; + qh->OL_Token = 0; + + /*------------------------------------------------------------------------------------*/ + /* Link QH and start asynchronous transfer */ + /*------------------------------------------------------------------------------------*/ + if (is_new_qh) + { + qh->HLink = _H_qh->HLink; + _H_qh->HLink = QH_HLNK_QH(qh); + } + + /* Start transfer */ + _ehci->UCMDR |= HSUSBH_UCMDR_ASEN_Msk; /* start asynchronous transfer */ + return 0; +} + +static int ehci_bulk_xfer(UTR_T *utr) +{ + UDEV_T *udev; + EP_INFO_T *ep = utr->ep; + QH_T *qh; + qTD_T *qtd, *qtd_pre; + uint32_t data_len, xfer_len; + uint8_t *buff; + uint32_t token; + int is_new_qh = 0; + + //USB_debug("Bulk XFER =>\n"); + // dump_ehci_asynclist_simple(); + + udev = utr->udev; + + if (ep->hw_pipe != NULL) + { + qh = (QH_T *)ep->hw_pipe ; + if (qh->qtd_list) + { + return USBH_ERR_EHCI_QH_BUSY; + } + } + else + { + qh = alloc_ehci_QH(); + if (qh == NULL) + return USBH_ERR_MEMORY_OUT; + is_new_qh = 1; + write_qh(udev, ep, qh); + ep->hw_pipe = (void *)qh; /* associate QH with endpoint */ + } + + /*------------------------------------------------------------------------------------*/ + /* Prepare qTDs */ + /*------------------------------------------------------------------------------------*/ + data_len = utr->data_len; + buff = utr->buff; + qtd_pre = NULL; + + while (data_len > 0) + { + qtd = alloc_ehci_qTD(utr); + if (qtd == NULL) /* failed to allocate a qTD */ + { + qtd = qh->qtd_list; + while (qtd != NULL) + { + qtd_pre = qtd; + qtd = qtd->next; + free_ehci_qTD(qtd_pre); + } + if (is_new_qh) + { + free_ehci_QH(qh); + ep->hw_pipe = NULL; + } + return USBH_ERR_MEMORY_OUT; + } + + if ((ep->bEndpointAddress & EP_ADDR_DIR_MASK) == EP_ADDR_DIR_OUT) + token = QTD_ERR_COUNTER | QTD_PID_OUT | QTD_STS_ACTIVE; + else + token = QTD_ERR_COUNTER | QTD_PID_IN | QTD_STS_ACTIVE; + + if (data_len > 0x4000) /* force maximum x'fer length 16K per qTD */ + xfer_len = 0x4000; + else + xfer_len = data_len; /* remaining data length < 4K */ + + qtd->qh = qh; + qtd->Next_qTD = (uint32_t)_ghost_qtd; + qtd->Alt_Next_qTD = QTD_LIST_END; //(uint32_t)_ghost_qtd; + write_qtd_bptr(qtd, (uint32_t)buff, xfer_len); + append_to_qtd_list_of_QH(qh, qtd); + qtd->Token = (xfer_len << 16) | token; + + buff += xfer_len; /* advanced buffer pointer */ + data_len -= xfer_len; + + if (data_len == 0) /* is this the latest qTD? */ + { + qtd->Token |= QTD_IOC; /* ask to raise an interrupt on the last qTD */ + qtd->Next_qTD = (uint32_t)_ghost_qtd; /* qTD list end */ + } + + if (qtd_pre != NULL) + qtd_pre->Next_qTD = (uint32_t)qtd; + qtd_pre = qtd; + } + + //USB_debug("utr=0x%x, qh=0x%x, qtd=0x%x\n", (int)utr, (int)qh, (int)qh->qtd_list); + + qtd = qh->qtd_list; + +// qh->Curr_qTD = 0; //(uint32_t)qtd; + qh->OL_Next_qTD = (uint32_t)qtd; +// qh->OL_Alt_Next_qTD = QTD_LIST_END; + + /*------------------------------------------------------------------------------------*/ + /* Link QH and start asynchronous transfer */ + /*------------------------------------------------------------------------------------*/ + if (is_new_qh) + { + memcpy(&(qh->OL_Bptr[0]), &(qtd->Bptr[0]), 20); + qh->Curr_qTD = (uint32_t)qtd; + + qh->OL_Token = 0; //qtd->Token; + + if (utr->ep->bToggle) + qh->OL_Token |= QTD_DT; + + qh->HLink = _H_qh->HLink; + _H_qh->HLink = QH_HLNK_QH(qh); + } + + /* Start transfer */ + _ehci->UCMDR |= HSUSBH_UCMDR_ASEN_Msk; /* start asynchronous transfer */ + + return 0; +} + +static int ehci_int_xfer(UTR_T *utr) +{ + UDEV_T *udev = utr->udev; + EP_INFO_T *ep = utr->ep; + QH_T *qh, *iqh; + qTD_T *qtd, *dummy_qtd; + uint32_t token; + + dummy_qtd = alloc_ehci_qTD(NULL); /* allocate a new dummy qTD */ + if (dummy_qtd == NULL) + return USBH_ERR_MEMORY_OUT; + dummy_qtd->Token &= ~(QTD_STS_ACTIVE | QTD_STS_HALT); + + if (ep->hw_pipe != NULL) + { + qh = (QH_T *)ep->hw_pipe ; + } + else + { + qh = alloc_ehci_QH(); + if (qh == NULL) + { + free_ehci_qTD(dummy_qtd); + return USBH_ERR_MEMORY_OUT; + } + write_qh(udev, ep, qh); + qh->Chrst &= ~0xF0000000; + + if (udev->speed == SPEED_HIGH) + { + qh->Cap = (0x1 << QH_MULT_Pos) | (qh->Cap & 0xff) | make_int_s_mask(ep->bInterval); + } + else + { + qh->Cap = (0x1 << QH_MULT_Pos) | (qh->Cap & ~(QH_C_MASK_Msk | QH_S_MASK_Msk)) | 0x7802; + } + ep->hw_pipe = (void *)qh; /* associate QH with endpoint */ + + /* + * Allocate another dummy qTD + */ + qtd = alloc_ehci_qTD(NULL); /* allocate a new dummy qTD */ + if (qtd == NULL) + { + free_ehci_qTD(dummy_qtd); + free_ehci_QH(qh); + return USBH_ERR_MEMORY_OUT; + } + qtd->Token &= ~(QTD_STS_ACTIVE | QTD_STS_HALT); + + qh->dummy = dummy_qtd; + qh->OL_Next_qTD = (uint32_t)dummy_qtd; + qh->OL_Token = 0; /* !Active & !Halted */ + + /* + * link QH + */ + if (udev->speed == SPEED_HIGH) /* get head node of this interval */ + iqh = get_int_tree_head_node(ep->bInterval); + else + iqh = get_int_tree_head_node(ep->bInterval * 8); + qh->HLink = iqh->HLink; /* Add to list of the same interval */ + iqh->HLink = QH_HLNK_QH(qh); + + dummy_qtd = qtd; + } + + qtd = qh->dummy; /* use the current dummy qTD */ + qtd->Next_qTD = (uint32_t)dummy_qtd; + qtd->utr = utr; + qh->dummy = dummy_qtd; /* give the new dummy qTD */ + + /*------------------------------------------------------------------------------------*/ + /* Prepare qTD */ + /*------------------------------------------------------------------------------------*/ + + if ((ep->bEndpointAddress & EP_ADDR_DIR_MASK) == EP_ADDR_DIR_OUT) + token = QTD_ERR_COUNTER | QTD_PID_OUT; + else + token = QTD_ERR_COUNTER | QTD_PID_IN; + + qtd->qh = qh; + qtd->Alt_Next_qTD = QTD_LIST_END; + write_qtd_bptr(qtd, (uint32_t)utr->buff, utr->data_len); + append_to_qtd_list_of_QH(qh, qtd); + qtd->Token = QTD_IOC | (utr->data_len << 16) | token | QTD_STS_ACTIVE; + + // printf("ehci_int_xfer - qh: 0x%x, 0x%x, 0x%x\n", (int)qh, (int)qh->Chrst, (int)qh->Cap); + + _ehci->UCMDR |= HSUSBH_UCMDR_PSEN_Msk; /* periodic list enable */ + return 0; +} + +/* + * Quit current trasnfer via UTR or hardware EP. + */ +static int ehci_quit_xfer(UTR_T *utr, EP_INFO_T *ep) +{ + QH_T *qh; + + // USB_debug("ehci_quit_xfer - utr: 0x%x, ep: 0x%x\n", (int)utr, (int)ep); + + DISABLE_EHCI_IRQ(); + if (ehci_quit_iso_xfer(utr, ep) == 0) + { + ENABLE_EHCI_IRQ(); + return 0; + } + ENABLE_EHCI_IRQ(); + + if (utr != NULL) + { + if (utr->ep == NULL) + return USBH_ERR_NOT_FOUND; + + qh = (QH_T *)(utr->ep->hw_pipe); + + if (!qh) + return USBH_ERR_NOT_FOUND; + + /* add the QH to remove list, it will be removed on the next IAAD interrupt */ + move_qh_to_remove_list(qh); + utr->ep->hw_pipe = NULL; + } + + if ((ep != NULL) && (ep->hw_pipe != NULL)) + { + qh = (QH_T *)(ep->hw_pipe); + /* add the QH to remove list, it will be removed on the next IAAD interrupt */ + move_qh_to_remove_list(qh); + ep->hw_pipe = NULL; + } + usbh_delay_ms(2); + + return 0; +} + +static int visit_qtd(qTD_T *qtd) +{ + if ((qtd->Token == 0x11197B3F) || (qtd->Token == 0x1197B3F)) + return 0; /* A Dummy qTD or qTD on writing, don't touch it. */ + + // USB_debug("Visit qtd 0x%x - 0x%x\n", (int)qtd, qtd->Token); + + if ((qtd->Token & QTD_STS_ACTIVE) == 0) + { + if (qtd->Token & (QTD_STS_HALT | QTD_STS_DATA_BUFF_ERR | QTD_STS_BABBLE | QTD_STS_XactErr | QTD_STS_MISS_MF)) + { + USB_error("qTD error token=0x%x! 0x%x\n", qtd->Token, qtd->Bptr[0]); + if (qtd->utr->status == 0) + qtd->utr->status = USBH_ERR_TRANSACTION; + } + else + { + if ((qtd->Token & QTD_PID_Msk) != QTD_PID_SETUP) + { + qtd->utr->xfer_len += qtd->xfer_len - QTD_TODO_LEN(qtd->Token); + // USB_debug("0x%x utr->xfer_len += %d\n", qtd->Token, qtd->xfer_len - QTD_TODO_LEN(qtd->Token)); + } + } + return 1; + } + return 0; +} + +static void scan_asynchronous_list() +{ + QH_T *qh, *qh_tmp; + qTD_T *q_pre=NULL, *qtd, *qtd_tmp; + UTR_T *utr; + + qh = QH_PTR(_H_qh->HLink); + while (qh != _H_qh) + { + // USB_debug("Scan qh=0x%x, 0x%x\n", (int)qh, qh->OL_Token); + + utr = NULL; + qtd = qh->qtd_list; + while (qtd != NULL) + { + if (visit_qtd(qtd)) /* if TRUE, reclaim this qtd */ + { + /* qTD is completed, will remove it */ + utr = qtd->utr; + if (qtd == qh->qtd_list) + qh->qtd_list = qtd->next; /* unlink the qTD from qtd_list */ + else + q_pre->next = qtd->next; /* unlink the qTD from qtd_list */ + + qtd_tmp = qtd; /* remember this qTD for freeing later */ + qtd = qtd->next; /* advance to the next qTD */ + + qtd_tmp->next = qh->done_list; /* push this qTD to QH's done list */ + qh->done_list = qtd_tmp; + } + else + { + q_pre = qtd; /* remember this qTD as a preceder */ + qtd = qtd->next; /* advance to next qTD */ + } + } + + qh_tmp = qh; + qh = QH_PTR(qh->HLink); /* advance to the next QH */ + + /* If all TDs are done, call-back to requester and then remove this QH. */ + if ((qh_tmp->qtd_list == NULL) && utr) + { + // printf("T %d [%d]\n", (qh_tmp->Chrst>>8)&0xf, (qh_tmp->OL_Token&QTD_DT) ? 1 : 0); + if (qh_tmp->OL_Token & QTD_DT) + utr->ep->bToggle = 1; + else + utr->ep->bToggle = 0; + + utr->bIsTransferDone = 1; + if (utr->func) + utr->func(utr); + + _ehci->UCMDR |= HSUSBH_UCMDR_IAAD_Msk; /* trigger IAA to reclaim done_list */ + } + } +} + +static void scan_periodic_frame_list() +{ + QH_T *qh; + qTD_T *qtd, *qNext; + UTR_T *utr; + + /*------------------------------------------------------------------------------------*/ + /* Scan interrupt frame list */ + /*------------------------------------------------------------------------------------*/ + qh = _Iqh[NUM_IQH-1]; + while (qh != NULL) + { + qtd = qh->qtd_list; + + if (qtd == NULL) + { + /* empty QH */ + qh = QH_PTR(qh->HLink); /* advance to the next QH */ + continue; + } + + while (qtd != NULL) + { + qNext = qtd->next; + + if (visit_qtd(qtd)) /* if TRUE, reclaim this qtd */ + { + qh->qtd_list = qtd->next; /* proceed to next qTD or NULL */ + qtd->next = qh->done_list; /* push qTD into the done list */ + qh->done_list = qtd; /* move qTD to done list */ + } + qtd = qNext; + } + + qtd = qh->done_list; + + while (qtd != NULL) + { + utr = qtd->utr; + + if (qh->OL_Token & QTD_DT) + utr->ep->bToggle = 1; + else + utr->ep->bToggle = 0; + + utr->bIsTransferDone = 1; + if (utr->func) + utr->func(utr); + + _ehci->UCMDR |= HSUSBH_UCMDR_IAAD_Msk; /* trigger IAA to reclaim done_list */ + + qtd = qtd->next; + } + + qh = QH_PTR(qh->HLink); /* advance to the next QH */ + } + + /*------------------------------------------------------------------------------------*/ + /* Scan isochronous frame list */ + /*------------------------------------------------------------------------------------*/ + + scan_isochronous_list(); +} + +void iaad_remove_qh() +{ + QH_T *qh; + qTD_T *qtd; + UTR_T *utr; + + /*------------------------------------------------------------------------------------*/ + /* Remove all QHs in qh_remove_list... */ + /*------------------------------------------------------------------------------------*/ + while (qh_remove_list != NULL) + { + qh = qh_remove_list; + qh_remove_list = qh->next; + + // USB_debug("iaad_remove_qh - remove QH 0x%x\n", (int)qh); + + while (qh->done_list) /* we can free the qTDs now */ + { + qtd = qh->done_list; + qh->done_list = qtd->next; + free_ehci_qTD(qtd); + } + + if (qh->qtd_list != NULL) /* still have incomplete qTDs? */ + { + utr = qh->qtd_list->utr; + while (qh->qtd_list) + { + qtd = qh->qtd_list; + qh->qtd_list = qtd->next; + free_ehci_qTD(qtd); + } + utr->status = USBH_ERR_ABORT; + utr->bIsTransferDone = 1; + if (utr->func) + utr->func(utr); /* call back */ + } + free_ehci_QH(qh); /* free the QH */ + } + + /*------------------------------------------------------------------------------------*/ + /* Free all qTD in done_list of each asynchronous QH */ + /*------------------------------------------------------------------------------------*/ + qh = QH_PTR(_H_qh->HLink); + while (qh != _H_qh) + { + while (qh->done_list) /* we can free the qTDs now */ + { + qtd = qh->done_list; + qh->done_list = qtd->next; + free_ehci_qTD(qtd); + } + qh = QH_PTR(qh->HLink); /* advance to the next QH */ + } + + /*------------------------------------------------------------------------------------*/ + /* Free all qTD in done_list of each QH of periodic frame list */ + /*------------------------------------------------------------------------------------*/ + qh = _Iqh[NUM_IQH-1]; + while (qh != NULL) + { + while (qh->done_list) /* we can free the qTDs now */ + { + qtd = qh->done_list; + qh->done_list = qtd->next; + free_ehci_qTD(qtd); + } + qh = QH_PTR(qh->HLink); /* advance to the next QH */ + } +} + +//static irqreturn_t ehci_irq (struct usb_hcd *hcd) +void EHCI_IRQHandler(void) +{ + uint32_t intsts; + + intsts = _ehci->USTSR; + _ehci->USTSR = intsts; /* clear interrupt status */ + + // USB_debug("Eirq USTSR=0x%x\n", intsts); + + if (intsts & HSUSBH_USTSR_UERRINT_Msk) + { + // USB_error("Transfer error!\n"); + } + + if (intsts & HSUSBH_USTSR_USBINT_Msk) + { + /* some transfers completed, travel asynchronous */ + /* and periodic lists to find and reclaim them. */ + scan_asynchronous_list(); + + scan_periodic_frame_list(); + } + + if (intsts & HSUSBH_USTSR_IAA_Msk) + { + iaad_remove_qh(); + } +} + +static UDEV_T * ehci_find_device_by_port(int port) +{ + UDEV_T *udev; + + udev = g_udev_list; + while (udev != NULL) + { + if ((udev->parent == NULL) && (udev->port_num == port) && (udev->speed == SPEED_HIGH)) + return udev; + udev = udev->next; + } + return NULL; +} + +static int ehci_rh_port_reset(int port) +{ + int retry; + int reset_time; + uint32_t t0; + + reset_time = usbh_tick_from_millisecond(PORT_RESET_TIME_MS); + + for (retry = 0; retry < PORT_RESET_RETRY; retry++) + { + _ehci->UPSCR[port] = (_ehci->UPSCR[port] | HSUSBH_UPSCR_PRST_Msk) & ~HSUSBH_UPSCR_PE_Msk; + + t0 = usbh_get_ticks(); + while (usbh_get_ticks() - t0 < (reset_time)+1) ; /* wait at least 50 ms */ + + _ehci->UPSCR[port] &= ~HSUSBH_UPSCR_PRST_Msk; + + t0 = usbh_get_ticks(); + while (usbh_get_ticks() - t0 < (reset_time)+1) + { + if (!(_ehci->UPSCR[port] & HSUSBH_UPSCR_CCS_Msk) || + ((_ehci->UPSCR[port] & (HSUSBH_UPSCR_CCS_Msk | HSUSBH_UPSCR_PE_Msk)) == (HSUSBH_UPSCR_CCS_Msk | HSUSBH_UPSCR_PE_Msk))) + goto port_reset_done; + } + reset_time += PORT_RESET_RETRY_INC_MS; + } + + USB_debug("EHCI port %d - port reset failed!\n", port+1); + return USBH_ERR_PORT_RESET; + +port_reset_done: + if ((_ehci->UPSCR[port] & HSUSBH_UPSCR_CCS_Msk) == 0) /* check again if device disconnected */ + { + _ehci->UPSCR[port] |= HSUSBH_UPSCR_CSC_Msk; /* clear CSC */ + return USBH_ERR_DISCONNECTED; + } + _ehci->UPSCR[port] |= HSUSBH_UPSCR_PEC_Msk; /* clear port enable change status */ + return USBH_OK; /* port reset success */ +} + +static int ehci_rh_polling(void) +{ + UDEV_T *udev; + int ret; + int connect_status, t0, debounce_tick; + + if (!(_ehci->UPSCR[0] & HSUSBH_UPSCR_CSC_Msk)) + return 0; + + /*------------------------------------------------------------------------------------*/ + /* connect status change */ + /*------------------------------------------------------------------------------------*/ + + USB_debug("EHCI port1 status change: 0x%x\n", _ehci->UPSCR[0]); + + /*--------------------------------------------------------------------------------*/ + /* Disconnect the devices attached to this port. */ + /*--------------------------------------------------------------------------------*/ + while (1) + { + udev = ehci_find_device_by_port(1); + if (udev == NULL) + break; + usbh_disconnect_device(udev); + } + + /*--------------------------------------------------------------------------------*/ + /* Port de-bounce */ + /*--------------------------------------------------------------------------------*/ + t0 = usbh_get_ticks(); + debounce_tick = usbh_tick_from_millisecond(HUB_DEBOUNCE_TIME); + connect_status = _ehci->UPSCR[0] & HSUSBH_UPSCR_CCS_Msk; + while (usbh_get_ticks() - t0 < debounce_tick) + { + if (connect_status != (_ehci->UPSCR[0] & HSUSBH_UPSCR_CCS_Msk)) + { + /* reset stable time counting */ + t0 = usbh_get_ticks(); + connect_status = _ehci->UPSCR[0] & HSUSBH_UPSCR_CCS_Msk; + } + } + + _ehci->UPSCR[0] |= HSUSBH_UPSCR_CSC_Msk; /* clear connect status change bit */ + + if (connect_status == HSUSBH_UPSCR_CCS_Msk) + { + /*--------------------------------------------------------------------------------*/ + /* A new device connected. */ + /*--------------------------------------------------------------------------------*/ + if (ehci_rh_port_reset(0) != USBH_OK) + { + /* port reset failed, maybe an USB 1.1 device */ + _ehci->UPSCR[0] |= HSUSBH_UPSCR_PO_Msk; /* change port owner to OHCI */ + _ehci->UPSCR[0] |= HSUSBH_UPSCR_CSC_Msk; /* clear all status change bits */ + return 0; + } + + /* + * Port reset success. Start to enumerate this new device. + */ + udev = alloc_device(); + if (udev == NULL) + return 0; /* out-of-memory, do nothing... */ + + udev->parent = NULL; + udev->port_num = 1; + udev->speed = SPEED_HIGH; + udev->hc_driver = &ehci_driver; + + ret = usbh_connect_device(udev); + if (ret < 0) + { + USB_error("connect_device error! [%d]\n", ret); + free_device(udev); + } + } + else + { + /* + * Device disconnected + */ + while (1) + { + udev = ehci_find_device_by_port(1); + if (udev == NULL) + break; + usbh_disconnect_device(udev); + } + } + return 1; +} + + +HC_DRV_T ehci_driver = +{ + ehci_init, /* init */ + ehci_shutdown, /* shutdown */ + ehci_suspend, /* suspend */ + ehci_resume, /* resume */ + ehci_ctrl_xfer, /* ctrl_xfer */ + ehci_bulk_xfer, /* bulk_xfer */ + ehci_int_xfer, /* int_xfer */ + ehci_iso_xfer, /* iso_xfer */ + ehci_quit_xfer, /* quit_xfer */ + ehci_rh_port_reset, /* rthub_port_reset */ + ehci_rh_polling /* rthub_polling */ +}; + + +/// @endcond HIDDEN_SYMBOLS + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/USBHostLib/src/ehci_iso.c b/bsp/nuvoton/libraries/m480/USBHostLib/src/ehci_iso.c new file mode 100644 index 0000000000000000000000000000000000000000..58cbc6fb03c129691337202c0e9bc55c5ceac028 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/USBHostLib/src/ehci_iso.c @@ -0,0 +1,916 @@ +/**************************************************************************//** + * @file ehci_iso.c + * @version V1.10 + * @brief USB EHCI isochronous transfer driver. + * + * SPDX-License-Identifier: Apache-2.0 + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include +#include + +#include "NuMicro.h" + +#include "usb.h" +#include "hub.h" + + +/// @cond HIDDEN_SYMBOLS + +uint32_t g_flr_cnt; /* frame list rollover counter */ + +ISO_EP_T *iso_ep_list; /* list of activated isochronous pipes */ + +extern uint32_t _PFList[FL_SIZE]; /* Periodic frame list */ + +static const uint16_t sitd_OUT_Smask [] = { 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f }; + +static int ehci_iso_split_xfer(UTR_T *utr, ISO_EP_T *iso_ep); + +/* + * Inspect the iTD can be reclaimed or not. If yes, collect the transaction results. + * Return: 1 - reclaimed + * 0 - not completed + */ +static int review_itd(iTD_T *itd) +{ + UTR_T *utr; + uint32_t frnidx = itd->sched_frnidx; + uint32_t now_frame = (_ehci->UFINDR >> 3) & 0x3FF; + int i, fidx; + + // printf("R - %d %d, 0x%x\n", now_frame, frnidx, itd->Transaction[0]); + + if (now_frame == frnidx) + { + for (i = 0; i < 8; i++) + { + if (itd->Transaction[i] & ITD_STATUS_ACTIVE) + return 0; /* have any not completed frames */ + } + } + else if (now_frame > frnidx) + { + if ((now_frame - frnidx) > EHCI_ISO_RCLM_RANGE) + return 0; /* don't touch it */ + } + else + { + if (now_frame + FL_SIZE - frnidx > EHCI_ISO_RCLM_RANGE) + return 0; /* don't touch it */ + } + + /* + * Reclaim this iTD + */ + utr = itd->utr; + fidx = itd->fidx; + for (i = 0; i < 8; i++) + { + if (!(itd->trans_mask & (0x1<Transaction[i])) + { + if (itd->Transaction[i] & ITD_STATUS_ACTIVE) + { + utr->iso_status[fidx] = USBH_ERR_NOT_ACCESS0; + utr->status = USBH_ERR_NOT_ACCESS0; + } + else if (itd->Transaction[i] & ITD_STATUS_BABBLE) + { + utr->iso_status[fidx] = USBH_ERR_BABBLE_DETECTED; + utr->status = USBH_ERR_TRANSFER; + } + else if (itd->Transaction[i] & ITD_STATUS_BUFF_ERR) + { + utr->iso_status[fidx] = USBH_ERR_DATA_BUFF; + utr->status = USBH_ERR_TRANSFER; + } + else + { + utr->iso_status[fidx] = USBH_ERR_TRANSACTION; + utr->status = USBH_ERR_TRANSFER; + } + } + else + { + utr->iso_status[fidx] = 0; + utr->iso_xlen[fidx] = ITD_XFER_LEN(itd->Transaction[i]); + } + fidx++; + } + utr->td_cnt--; + + if (utr->td_cnt == 0) /* All iTD of this UTR done */ + { + utr->bIsTransferDone = 1; + if (utr->func) + utr->func(utr); + } + + return 1; /* to be reclaimed */ +} + +/* + * Inspect the siTD can be reclaimed or not. If yes, collect the transaction results. + * Return: 1 - reclaimed + * 0 - not completed + */ +static int review_sitd(siTD_T *sitd) +{ + UTR_T *utr; + uint32_t frnidx = sitd->sched_frnidx; + uint32_t now_frame = (_ehci->UFINDR >> 3) & 0x3FF; + int fidx; + uint32_t TotalBytesToTransfer; + + if (now_frame == frnidx) + { + if (SITD_STATUS(sitd->StsCtrl) == SITD_STATUS_ACTIVE) + return 0; + } + else if (now_frame > frnidx) + { + if ((now_frame - frnidx) > EHCI_ISO_RCLM_RANGE) + return 0; /* don't touch it */ + } + else + { + if (now_frame + FL_SIZE - frnidx > EHCI_ISO_RCLM_RANGE) + return 0; /* don't touch it */ + } + + /* + * Reclaim this siTD + */ + utr = sitd->utr; + fidx = sitd->fidx; + + if (SITD_STATUS(sitd->StsCtrl)) + { + if (sitd->StsCtrl & SITD_STATUS_ACTIVE) + { + utr->iso_status[fidx] = USBH_ERR_NOT_ACCESS0; + } + else if (sitd->StsCtrl & SITD_BABBLE_DETECTED) + { + utr->iso_status[fidx] = USBH_ERR_BABBLE_DETECTED; + utr->status = USBH_ERR_TRANSFER; + } + else if (sitd->StsCtrl & SITD_STATUS_BUFF_ERR) + { + utr->iso_status[fidx] = USBH_ERR_DATA_BUFF; + utr->status = USBH_ERR_TRANSFER; + } + else + { + utr->iso_status[fidx] = USBH_ERR_TRANSACTION; + utr->status = USBH_ERR_TRANSFER; + } + } + else + { + TotalBytesToTransfer = (sitd->StsCtrl & SITD_XFER_CNT_Msk) >> SITD_XFER_CNT_Pos; + utr->iso_xlen[fidx] = utr->iso_xlen[fidx] - TotalBytesToTransfer; + utr->iso_status[fidx] = 0; + } + utr->td_cnt--; + + if (utr->td_cnt == 0) /* All iTD of this UTR done */ + { + utr->bIsTransferDone = 1; + if (utr->func) + utr->func(utr); + } + return 1; /* to be reclaimed */ +} + +/* + * Some iTD/siTD may be scheduled but not serviced due to time missed. + * This function scan several earlier frames and drop unserviced iTD/siTD if found. + */ +void scan_isochronous_list(void) +{ + ISO_EP_T *iso_ep = iso_ep_list; + iTD_T *itd, *itd_pre, *p; + siTD_T *sitd, *sitd_pre, *sp; + uint32_t frnidx; + + DISABLE_EHCI_IRQ(); + + while (iso_ep != NULL) /* Search all activated iso endpoints */ + { + /*--------------------------------------------------------------------------------*/ + /* Scan all iTDs */ + /*--------------------------------------------------------------------------------*/ + itd = iso_ep->itd_list; /* get the first iTD from iso_ep's iTD list */ + itd_pre = NULL; + while (itd != NULL) /* traverse all iTDs of itd list */ + { + if (review_itd(itd)) /* inspect and reclaim iTD */ + { + /*------------------------------------------------------------------------*/ + /* Remove this iTD from period frame list */ + /*------------------------------------------------------------------------*/ + frnidx = itd->sched_frnidx; + if (_PFList[frnidx] == ITD_HLNK_ITD(itd)) + { + /* is the first entry, just change to next */ + _PFList[frnidx] = itd->Next_Link; + } + else + { + p = ITD_PTR(_PFList[frnidx]); /* find the preceding iTD */ + while ((ITD_PTR(p->Next_Link) != itd) && (p != NULL)) + { + p = ITD_PTR(p->Next_Link); + } + + if (p == NULL) /* link list out of control! */ + { + USB_error("An iTD lost refernece to periodic frame list! 0x%x -> %d\n", (int)itd, frnidx); + } + else /* remove iTD from list */ + { + p->Next_Link = itd->Next_Link; + } + } + + /*------------------------------------------------------------------------*/ + /* Remove this iTD from iso_ep's iTD list */ + /*------------------------------------------------------------------------*/ + if (itd_pre == NULL) + { + iso_ep->itd_list = itd->next; + } + else + { + itd_pre->next = itd->next; + } + p = itd->next; + free_ehci_iTD(itd); + itd = p; + } + else + { + itd_pre = itd; + itd = itd->next; /* traverse to the next iTD of iTD list */ + } + } + + /*--------------------------------------------------------------------------------*/ + /* Scan all siTDs */ + /*--------------------------------------------------------------------------------*/ + sitd = iso_ep->sitd_list; /* get the first siTD from iso_ep's siTD list */ + sitd_pre = NULL; + while (sitd != NULL) /* traverse all siTDs of sitd list */ + { + if (review_sitd(sitd)) /* inspect and reclaim siTD */ + { + /*------------------------------------------------------------------------*/ + /* Remove this siTD from period frame list */ + /*------------------------------------------------------------------------*/ + frnidx = sitd->sched_frnidx; + if (_PFList[frnidx] == SITD_HLNK_SITD(sitd)) + { + /* is the first entry, just change to next */ + _PFList[frnidx] = sitd->Next_Link; + } + else + { + sp = SITD_PTR(_PFList[frnidx]); /* find the preceding siTD */ + while ((SITD_PTR(sp->Next_Link) != sitd) && (sp != NULL)) + { + sp = SITD_PTR(sp->Next_Link); + } + + if (sp == NULL) /* link list out of control! */ + { + USB_error("An siTD lost reference to periodic frame list! 0x%x -> %d\n", (int)sitd, frnidx); + } + else /* remove iTD from list */ + { + sp->Next_Link = sitd->Next_Link; + } + } + + /*------------------------------------------------------------------------*/ + /* Remove this siTD from iso_ep's siTD list */ + /*------------------------------------------------------------------------*/ + if (sitd_pre == NULL) + { + iso_ep->sitd_list = sitd->next; + } + else + { + sitd_pre->next = sitd->next; + } + sp = sitd->next; + free_ehci_siTD(sitd); + sitd = sp; + } + else + { + sitd_pre = sitd; + sitd = sitd->next; /* traverse to the next siTD of siTD list */ + } + } + + iso_ep = iso_ep->next; + } + + ENABLE_EHCI_IRQ(); +} + + +static void write_itd_info(UTR_T *utr, iTD_T *itd) +{ + UDEV_T *udev = utr->udev; + EP_INFO_T *ep = utr->ep; /* reference to isochronous endpoint */ + uint32_t buff_page_addr; + int i; + + buff_page_addr = itd->buff_base & 0xFFFFF000; /* 4K page */ + + for (i = 0; i < 7; i++) + { + itd->Bptr[i] = buff_page_addr + (0x1000 * i); + } + /* EndPtr R Device Address */ + itd->Bptr[0] |= (udev->dev_num) | ((ep->bEndpointAddress & 0xF) << ITD_EP_NUM_Pos); + itd->Bptr[1] |= ep->wMaxPacketSize; /* Maximum Packet Size */ + + if ((ep->bEndpointAddress & EP_ADDR_DIR_MASK) == EP_ADDR_DIR_IN) /* I/O */ + itd->Bptr[1] |= ITD_DIR_IN; + else + itd->Bptr[1] |= ITD_DIR_OUT; + + itd->Bptr[2] |= (ep->wMaxPacketSize + 1023)/1024; /* Mult */ +} + +static void write_itd_micro_frame(UTR_T *utr, int fidx, iTD_T *itd, int mf) +{ + uint32_t buff_addr; + + buff_addr = (uint32_t)(utr->iso_buff[fidx]); /* xfer buffer start address of this frame */ + + itd->Transaction[mf] = ITD_STATUS_ACTIVE | /* Status */ + ((utr->iso_xlen[fidx] & 0xFFF) << ITD_XLEN_Pos) | /* Transaction Length */ + ((buff_addr & 0xFFFFF000) - (itd->buff_base & 0xFFFFF000)) | /* PG */ + (buff_addr & 0xFFF); /* Transaction offset */ +} + + +static void remove_iso_ep_from_list(ISO_EP_T *iso_ep) +{ + ISO_EP_T *p; + + if (iso_ep_list == iso_ep) + { + iso_ep_list = iso_ep->next; /* it's the first entry, remove it */ + return; + } + + p = iso_ep_list; /* find the previous entry of iso_ep */ + while (p->next != NULL) + { + if (p->next == iso_ep) + { + break; + } + p = p->next; + } + + if (p->next == NULL) + { + return; /* not found */ + } + p->next = iso_ep->next; /* remove iso_ep from list */ +} + + +static __inline void add_itd_to_iso_ep(ISO_EP_T *iso_ep, iTD_T *itd) +{ + iTD_T *p; + + itd->next = NULL; + + if (iso_ep->itd_list == NULL) + { + iso_ep->itd_list = itd; + return; + } + + /* + * Find the tail entry of iso_ep->itd_list + */ + p = iso_ep->itd_list; + while (p->next != NULL) + { + p = p->next; + } + p->next = itd; +} + +int ehci_iso_xfer(UTR_T *utr) +{ + EP_INFO_T *ep = utr->ep; /* reference to isochronous endpoint */ + ISO_EP_T *iso_ep; /* software iso endpoint descriptor */ + iTD_T *itd, *itd_next, *itd_list = NULL; + int i, itd_cnt; + int trans_mask; /* bit mask of used xfer in an iTD */ + int fidx; /* index to the 8 iso frames of UTR */ + int interval; /* frame interval of iTD */ + + if (ep->hw_pipe != NULL) + { + iso_ep = (ISO_EP_T *)ep->hw_pipe; /* get reference of the isochronous endpoint */ + + if (utr->bIsoNewSched) + iso_ep->next_frame = (((_ehci->UFINDR + (EHCI_ISO_DELAY * 8)) & HSUSBH_UFINDR_FI_Msk) >> 3) & 0x3FF; + } + else + { + /* first time transfer of this iso endpoint */ + iso_ep = usbh_alloc_mem(sizeof(*iso_ep)); + if (iso_ep == NULL) + return USBH_ERR_MEMORY_OUT; + + memset(iso_ep, 0, sizeof(*iso_ep)); + iso_ep->ep = ep; + iso_ep->next_frame = (((_ehci->UFINDR + (EHCI_ISO_DELAY * 8)) & HSUSBH_UFINDR_FI_Msk) >> 3) & 0x3FF; + + ep->hw_pipe = iso_ep; + + /* + * Add this iso_ep into iso_ep_list + */ + DISABLE_EHCI_IRQ(); + iso_ep->next = iso_ep_list; + iso_ep_list = iso_ep; + ENABLE_EHCI_IRQ(); + } + + if (utr->udev->speed == SPEED_FULL) + return ehci_iso_split_xfer(utr, iso_ep); + + /*------------------------------------------------------------------------------------*/ + /* Allocate iTDs */ + /*------------------------------------------------------------------------------------*/ + + if (ep->bInterval < 2) /* transfer interval is 1 micro-frame */ + { + trans_mask = 0xFF; + itd_cnt = 1; /* required 1 iTD for one UTR */ + interval = 1; /* iTD frame interval of this endpoint */ + } + else if (ep->bInterval < 4) /* transfer interval is 2 micro-frames */ + { + trans_mask = 0x55; + itd_cnt = 2; /* required 2 iTDs for one UTR */ + interval = 1; /* iTD frame interval of this endpoint */ + } + else if (ep->bInterval < 8) /* transfer interval is 4 micro-frames */ + { + trans_mask = 0x44; + itd_cnt = 4; /* required 4 iTDs for one UTR */ + interval = 1; /* iTD frame interval of this endpoint */ + } + else if (ep->bInterval < 16) /* transfer interval is 8 micro-frames */ + { + trans_mask = 0x08; /* there's 1 transfer in one iTD */ + itd_cnt = 8; /* required 8 iTDs for one UTR */ + interval = 1; /* iTD frame interval of this endpoint */ + } + else if (ep->bInterval < 32) /* transfer interval is 16 micro-frames */ + { + trans_mask = 0x10; /* there's 1 transfer in one iTD */ + itd_cnt = 8; /* required 8 iTDs for one UTR */ + interval = 2; /* iTD frame interval of this endpoint */ + } + else if (ep->bInterval < 64) /* transfer interval is 32 micro-frames */ + { + trans_mask = 0x02; /* there's 1 transfer in one iTD */ + itd_cnt = 8; /* required 8 iTDs for one UTR */ + interval = 4; /* iTD frame interval of this endpoint */ + } + else /* transfer interval is 64 micro-frames */ + { + trans_mask = 0x04; /* there's 1 transfer in one iTD */ + itd_cnt = 8; /* required 8 iTDs for one UTR */ + interval = 8; /* iTD frame interval of this endpoint */ + } + + for (i = 0; i < itd_cnt; i++) /* allocate all iTDs required by UTR */ + { + itd = alloc_ehci_iTD(); + if (itd == NULL) + goto malloc_failed; + + if (itd_list == NULL) /* link all iTDs */ + { + itd_list = itd; + } + else + { + itd->next = itd_list; + itd_list = itd; + } + } + + utr->td_cnt = itd_cnt; + + /*------------------------------------------------------------------------------------*/ + /* Fill and link all iTDs */ + /*------------------------------------------------------------------------------------*/ + + utr->iso_sf = iso_ep->next_frame; + fidx = 0; /* index to UTR iso frmes (total IF_PER_UTR) */ + + for (itd = itd_list; (itd != NULL); ) + { + if (fidx >= IF_PER_UTR) /* unlikely */ + { + USB_error("EHCI driver ITD bug!?\n"); + goto malloc_failed; + } + + itd->utr = utr; + itd->fidx = fidx; /* index to UTR's n'th IF_PER_UTR frame */ + itd->buff_base = (uint32_t)(utr->iso_buff[fidx]); /* iTD buffer base is buffer of the first UTR iso frame serviced by this iTD */ + itd->trans_mask = trans_mask; + + write_itd_info(utr, itd); + + for (i = 0; i < 8; i++) /* settle xfer into micro-frames */ + { + if (!(trans_mask & (0x1<Transaction[i] = 0; /* not accesed */ + continue; /* not scheduled micro-frame */ + } + + write_itd_micro_frame(utr, fidx, itd, i); + + fidx++; /* preceed to next UTR iso frame */ + + if (fidx == IF_PER_UTR) /* is the last scheduled micro-frame? */ + { + /* raise interrupt on completed */ + itd->Transaction[i] |= ITD_IOC; + break; + } + } + + itd_next = itd->next; /* remember the next itd */ + + // USB_debug("Link iTD 0x%x, %d\n", (int)itd, iso_ep->next_frame); + /* + * Link iTD to period frame list + */ + DISABLE_EHCI_IRQ(); + itd->sched_frnidx = iso_ep->next_frame; /* remember it for reclamation scan */ + add_itd_to_iso_ep(iso_ep, itd); /* add to software itd list */ + itd->Next_Link = _PFList[itd->sched_frnidx]; /* keep the next link */ + _PFList[itd->sched_frnidx] = ITD_HLNK_ITD(itd); + iso_ep->next_frame = (iso_ep->next_frame + interval) % FL_SIZE; + ENABLE_EHCI_IRQ(); + + itd = itd_next; + } + + _ehci->UCMDR |= HSUSBH_UCMDR_PSEN_Msk; /* periodic list enable */ + return 0; + +malloc_failed: + + while (itd_list != NULL) + { + itd = itd_list; + itd_list = itd->next; + free_ehci_iTD(itd); + } + return USBH_ERR_MEMORY_OUT; +} + +static __inline void add_sitd_to_iso_ep(ISO_EP_T *iso_ep, siTD_T *sitd) +{ + siTD_T *p; + + sitd->next = NULL; + + if (iso_ep->sitd_list == NULL) + { + iso_ep->sitd_list = sitd; + return; + } + + /* + * Find the tail entry of iso_ep->itd_list + */ + p = iso_ep->sitd_list; + while (p->next != NULL) + { + p = p->next; + } + p->next = sitd; +} + +static void write_sitd_info(UTR_T *utr, siTD_T *sitd) +{ + UDEV_T *udev = utr->udev; + EP_INFO_T *ep = utr->ep; /* reference to isochronous endpoint */ + uint32_t buff_page_addr; + int xlen = utr->iso_xlen[sitd->fidx]; + int scnt; + + sitd->Chrst = (udev->port_num << SITD_PORT_NUM_Pos) | + (udev->parent->iface->udev->dev_num << SITD_HUB_ADDR_Pos) | + ((ep->bEndpointAddress & 0xF) << SITD_EP_NUM_Pos) | + (udev->dev_num << SITD_DEV_ADDR_Pos); + + buff_page_addr = ((uint32_t)utr->iso_buff[sitd->fidx]) & 0xFFFFF000; + sitd->Bptr[0] = (uint32_t)(utr->iso_buff[sitd->fidx]); + sitd->Bptr[1] = buff_page_addr + 0x1000; + + scnt = (xlen + 187) / 188; + + if ((ep->bEndpointAddress & EP_ADDR_DIR_MASK) == EP_ADDR_DIR_IN) /* I/O */ + { + sitd->Chrst |= SITD_XFER_IN; + sitd->Sched = (1 << (scnt + 2)) - 1; + sitd->Sched = (sitd->Sched << 10) | 0x1; + //sitd->Sched <<= 1; + } + else + { + sitd->Chrst |= SITD_XFER_OUT; + sitd->Sched = sitd_OUT_Smask[scnt-1]; + if (scnt > 1) + { + sitd->Bptr[1] |= (0x1 << 3); /* Transaction position (TP) 01b: Begin */ + } + sitd->Bptr[1] |= scnt; /* Transaction count (T-Count) */ + } + + if (sitd->fidx == IF_PER_UTR) + { + sitd->Sched |= SITD_IOC; + } + + sitd->StsCtrl = (xlen << SITD_XFER_CNT_Pos) | SITD_STATUS_ACTIVE; + + sitd->BackLink = SITD_LIST_END; +} + + +static void ehci_sitd_adjust_schedule(siTD_T *sitd) +{ + siTD_T *hlink = (siTD_T *)_PFList[sitd->sched_frnidx]; + uint32_t uframe_mask = 0x00; + + while (hlink && !HLINK_IS_TERMINATED(hlink) && HLINK_IS_SITD(hlink)) + { + hlink = SITD_PTR(hlink); + if (hlink != sitd) + { + if ((hlink->Chrst & SITD_XFER_IO_Msk) == SITD_XFER_IN) + { + uframe_mask |= (hlink->Sched & 0xFF); /* mark micro-frames used by IN S-mask */ + uframe_mask |= ((hlink->Sched >> 8) & 0xFF); /* mark micro-frames used by IN C-mask */ + } + else + { + uframe_mask |= (hlink->Sched & 0xFF); /* mark micro-frames used by OUT S-mask */ + } + } + hlink = SITD_PTR(hlink->Next_Link); + } + + uframe_mask = uframe_mask | (uframe_mask << 8); /* mark both S-mask and C-mask */ + + if (uframe_mask) + { + /* + * Shift afterward one micro-frame until no conflicts. + */ + while (1) + { + if (sitd->Sched & uframe_mask) + { + sitd->Sched = (sitd->Sched & 0xFFFF0000) | ((sitd->Sched << 1) & 0xFFFF); + } + else + { + break; /* no conflit, done. */ + } + } + } +} + + +static int ehci_iso_split_xfer(UTR_T *utr, ISO_EP_T *iso_ep) +{ + EP_INFO_T *ep = utr->ep; /* reference to isochronous endpoint */ + siTD_T *sitd, *sitd_next, *sitd_list = NULL; + int i; + int fidx; /* index to the 8 iso frames of UTR */ + + if (utr->udev->parent == NULL) + { + USB_error("siso xfer - parent lost!\n"); + return USBH_ERR_INVALID_PARAM; + } + + /*------------------------------------------------------------------------------------*/ + /* Allocate siTDs */ + /*------------------------------------------------------------------------------------*/ + for (i = 0; i < IF_PER_UTR; i++) /* allocate all siTDs required by UTR */ + { + sitd = alloc_ehci_siTD(); + if (sitd == NULL) + goto malloc_failed; + + if (sitd_list == NULL) /* link all siTDs */ + { + sitd_list = sitd; + } + else + { + sitd->next = sitd_list; + sitd_list = sitd; + } + } + + utr->td_cnt = IF_PER_UTR; + + /*------------------------------------------------------------------------------------*/ + /* Fill and link all siTDs */ + /*------------------------------------------------------------------------------------*/ + + utr->iso_sf = iso_ep->next_frame; + fidx = 0; /* index to UTR iso frmes (total IF_PER_UTR) */ + + for (sitd = sitd_list; (sitd != NULL); fidx++) + { + if (fidx >= IF_PER_UTR) /* unlikely */ + { + USB_error("EHCI driver siTD bug!?\n"); + goto malloc_failed; + } + + sitd->utr = utr; + sitd->fidx = fidx; /* index to UTR's n'th IF_PER_UTR frame */ + + write_sitd_info(utr, sitd); + + sitd_next = sitd->next; /* remember the next itd */ + + // USB_debug("Link iTD 0x%x, %d\n", (int)itd, iso_ep->next_frame); + /* + * Link iTD to period frame list + */ + sitd->sched_frnidx = iso_ep->next_frame; /* remember it for reclamation scan */ + DISABLE_EHCI_IRQ(); + ehci_sitd_adjust_schedule(sitd); + add_sitd_to_iso_ep(iso_ep, sitd); /* add to software itd list */ + sitd->Next_Link = _PFList[sitd->sched_frnidx];/* keep the next link */ + _PFList[sitd->sched_frnidx] = SITD_HLNK_SITD(sitd); + iso_ep->next_frame = (iso_ep->next_frame + ep->bInterval) % FL_SIZE; + ENABLE_EHCI_IRQ(); + + sitd = sitd_next; + } + + _ehci->UCMDR |= HSUSBH_UCMDR_PSEN_Msk; /* periodic list enable */ + return 0; + +malloc_failed: + + while (sitd_list != NULL) + { + sitd = sitd_list; + sitd_list = sitd->next; + free_ehci_siTD(sitd); + } + return USBH_ERR_MEMORY_OUT; +} + +/* + * If it's an isochronous endpoint, quit current transfer via UTR or hardware EP. + */ +int ehci_quit_iso_xfer(UTR_T *utr, EP_INFO_T *ep) +{ + ISO_EP_T *iso_ep; + iTD_T *itd, *itd_next, *p; + uint32_t frnidx; + uint32_t now_frame; + + if (ep == NULL) + { + if (utr == NULL) + return USBH_ERR_NOT_FOUND; + + if (utr->ep == NULL) + return USBH_ERR_NOT_FOUND; + + ep = utr->ep; + } + + if ((ep->bmAttributes & EP_ATTR_TT_MASK) != EP_ATTR_TT_ISO) + return USBH_ERR_NOT_FOUND; /* not isochronous endpoint */ + + /*------------------------------------------------------------------------------------*/ + /* It's an iso endpoint. Remove it as required. */ + /*------------------------------------------------------------------------------------*/ + iso_ep = iso_ep_list; + while (iso_ep != NULL) /* Search all activated iso endpoints */ + { + if (iso_ep->ep == ep) + break; + iso_ep = iso_ep->next; + } + if (iso_ep == NULL) + return 0; /* should have been removed */ + + itd = iso_ep->itd_list; /* get the first iTD from iso_ep's iTD list */ + + while (itd != NULL) /* traverse all iTDs of itd list */ + { + itd_next = itd->next; /* remember the next iTD */ + utr = itd->utr; + + /*--------------------------------------------------------------------------------*/ + /* Remove this iTD from period frame list */ + /*--------------------------------------------------------------------------------*/ + frnidx = itd->sched_frnidx; + + /* + * Prevent to race with Host Controller. If the iTD to be removed is located in + * current or next frame, wait until HC passed through it. + */ + while (1) + { + now_frame = (_ehci->UFINDR >> 3) & 0x3FF; + if ((now_frame == frnidx) || (((now_frame+1)%1024) == frnidx)) + continue; + break; + } + + if (_PFList[frnidx] == ITD_HLNK_ITD(itd)) + { + /* is the first entry, just change to next */ + _PFList[frnidx] = itd->Next_Link; + } + else + { + p = ITD_PTR(_PFList[frnidx]); /* find the preceding iTD */ + while ((ITD_PTR(p->Next_Link) != itd) && (p != NULL)) + { + p = ITD_PTR(p->Next_Link); + } + + if (p == NULL) /* link list out of control! */ + { + USB_error("ehci_quit_iso_xfer - An iTD lost reference to periodic frame list! 0x%x on %d\n", (int)itd, frnidx); + } + else /* remove iTD from list */ + { + p->Next_Link = itd->Next_Link; + } + } + + utr->td_cnt--; + + if (utr->td_cnt == 0) /* All iTD of this UTR done */ + { + utr->bIsTransferDone = 1; + if (utr->func) + utr->func(utr); + utr->status = USBH_ERR_ABORT; + } + free_ehci_iTD(itd); + itd = itd_next; + } + + /* + * Remove iso_ep from iso_ep_list + */ + remove_iso_ep_from_list(iso_ep); + usbh_free_mem(iso_ep, sizeof(*iso_ep)); /* free this iso_ep */ + ep->hw_pipe = NULL; + + if (iso_ep_list == NULL) + _ehci->UCMDR &= ~HSUSBH_UCMDR_PSEN_Msk; + + return 0; +} + + +/// @endcond HIDDEN_SYMBOLS + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/USBHostLib/src/mem_alloc.c b/bsp/nuvoton/libraries/m480/USBHostLib/src/mem_alloc.c new file mode 100644 index 0000000000000000000000000000000000000000..d0eab23770058c2be0fc8e973bc6dcd9373c8f69 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/USBHostLib/src/mem_alloc.c @@ -0,0 +1,503 @@ +/**************************************************************************//** + * @file mem_alloc.c + * @version V1.10 + * @brief USB host library memory allocation functions. + * + * SPDX-License-Identifier: Apache-2.0 + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include +#include + +#include "NuMicro.h" + +#include "usb.h" + + +/// @cond HIDDEN_SYMBOLS + +//#define MEM_DEBUG + +#ifdef MEM_DEBUG +#define mem_debug rt_kprintf +#else +#define mem_debug(...) +#endif + +#ifdef __ICCARM__ +#pragma data_alignment=32 +static uint8_t _mem_pool[MEM_POOL_UNIT_NUM][MEM_POOL_UNIT_SIZE]; +#else +static uint8_t _mem_pool[MEM_POOL_UNIT_NUM][MEM_POOL_UNIT_SIZE] __attribute__((aligned(32))); +#endif +static uint8_t _unit_used[MEM_POOL_UNIT_NUM]; + +static volatile int _usbh_mem_used; +static volatile int _usbh_max_mem_used; +static volatile int _mem_pool_used; + + +UDEV_T * g_udev_list; + +uint8_t _dev_addr_pool[128]; +static volatile int _device_addr; + +static int _sidx = 0;; + +/*--------------------------------------------------------------------------*/ +/* Memory alloc/free recording */ +/*--------------------------------------------------------------------------*/ + +void usbh_memory_init(void) +{ + if (sizeof(TD_T) > MEM_POOL_UNIT_SIZE) + { + USB_error("TD_T - MEM_POOL_UNIT_SIZE too small!\n"); + while (1); + } + + if (sizeof(ED_T) > MEM_POOL_UNIT_SIZE) + { + USB_error("ED_T - MEM_POOL_UNIT_SIZE too small!\n"); + while (1); + } + + _usbh_mem_used = 0L; + _usbh_max_mem_used = 0L; + + memset(_unit_used, 0, sizeof(_unit_used)); + _mem_pool_used = 0; + _sidx = 0; + + g_udev_list = NULL; + + memset(_dev_addr_pool, 0, sizeof(_dev_addr_pool)); + _device_addr = 1; +} + +uint32_t usbh_memory_used(void) +{ + rt_kprintf("USB static memory: %d/%d, heap used: %d\n", _mem_pool_used, MEM_POOL_UNIT_NUM, _usbh_mem_used); + return _usbh_mem_used; +} + +static void memory_counter(int size) +{ + _usbh_mem_used += size; + if (_usbh_mem_used > _usbh_max_mem_used) + _usbh_max_mem_used = _usbh_mem_used; +} + +void * usbh_alloc_mem(int size) +{ + void *p; + + p = malloc(size); + if (p == NULL) + { + USB_error("usbh_alloc_mem failed! %d\n", size); + return NULL; + } + + memset(p, 0, size); + memory_counter(size); + return p; +} + +void usbh_free_mem(void *p, int size) +{ + free(p); + memory_counter(0-size); +} + + +/*--------------------------------------------------------------------------*/ +/* USB device allocate/free */ +/*--------------------------------------------------------------------------*/ + +UDEV_T * alloc_device(void) +{ + UDEV_T *udev; + + udev = malloc(sizeof(*udev)); + if (udev == NULL) + { + USB_error("alloc_device failed!\n"); + return NULL; + } + memset(udev, 0, sizeof(*udev)); + memory_counter(sizeof(*udev)); + udev->cur_conf = -1; /* must! used to identify the first SET CONFIGURATION */ + udev->next = g_udev_list; /* chain to global device list */ + g_udev_list = udev; + return udev; +} + +void free_device(UDEV_T *udev) +{ + UDEV_T *d; + + if (udev == NULL) + return; + + if (udev->cfd_buff != NULL) + usbh_free_mem(udev->cfd_buff, MAX_DESC_BUFF_SIZE); + + /* + * Remove it from the global device list + */ + if (g_udev_list == udev) + { + g_udev_list = g_udev_list->next; + } + else + { + d = g_udev_list; + while (d != NULL) + { + if (d->next == udev) + { + d->next = udev->next; + break; + } + d = d->next; + } + } + + free(udev); + memory_counter(-sizeof(*udev)); +} + +int alloc_dev_address(void) +{ + _device_addr++; + + if (_device_addr >= 128) + _device_addr = 1; + + while (1) + { + if (_dev_addr_pool[_device_addr] == 0) + { + _dev_addr_pool[_device_addr] = 1; + return _device_addr; + } + _device_addr++; + if (_device_addr >= 128) + _device_addr = 1; + } +} + +void free_dev_address(int dev_addr) +{ + if (dev_addr < 128) + _dev_addr_pool[dev_addr] = 0; +} + +/*--------------------------------------------------------------------------*/ +/* UTR (USB Transfer Request) allocate/free */ +/*--------------------------------------------------------------------------*/ + +UTR_T * alloc_utr(UDEV_T *udev) +{ + UTR_T *utr; + + utr = malloc(sizeof(*utr)); + if (utr == NULL) + { + USB_error("alloc_utr failed!\n"); + return NULL; + } + memory_counter(sizeof(*utr)); + memset(utr, 0, sizeof(*utr)); + utr->udev = udev; + mem_debug("[ALLOC] [UTR] - 0x%x\n", (int)utr); + return utr; +} + +void free_utr(UTR_T *utr) +{ + if (utr == NULL) + return; + + mem_debug("[FREE] [UTR] - 0x%x\n", (int)utr); + free(utr); + memory_counter(0-(int)sizeof(*utr)); +} + +/*--------------------------------------------------------------------------*/ +/* OHCI ED allocate/free */ +/*--------------------------------------------------------------------------*/ + +ED_T * alloc_ohci_ED(void) +{ + int i; + ED_T *ed; + + for (i = 0; i < MEM_POOL_UNIT_NUM; i++) + { + if (_unit_used[i] == 0) + { + _unit_used[i] = 1; + _mem_pool_used++; + ed = (ED_T *)&_mem_pool[i]; + memset(ed, 0, sizeof(*ed)); + mem_debug("[ALLOC] [ED] - 0x%x\n", (int)ed); + return ed; + } + } + USB_error("alloc_ohci_ED failed!\n"); + return NULL; +} + +void free_ohci_ED(ED_T *ed) +{ + int i; + + for (i = 0; i < MEM_POOL_UNIT_NUM; i++) + { + if ((uint32_t)&_mem_pool[i] == (uint32_t)ed) + { + mem_debug("[FREE] [ED] - 0x%x\n", (int)ed); + _unit_used[i] = 0; + _mem_pool_used--; + return; + } + } + USB_debug("free_ohci_ED - not found! (ignored in case of multiple UTR)\n"); +} + +/*--------------------------------------------------------------------------*/ +/* OHCI TD allocate/free */ +/*--------------------------------------------------------------------------*/ +TD_T * alloc_ohci_TD(UTR_T *utr) +{ + int i; + TD_T *td; + + for (i = 0; i < MEM_POOL_UNIT_NUM; i++) + { + if (_unit_used[i] == 0) + { + _unit_used[i] = 1; + _mem_pool_used++; + td = (TD_T *)&_mem_pool[i]; + + memset(td, 0, sizeof(*td)); + td->utr = utr; + mem_debug("[ALLOC] [TD] - 0x%x\n", (int)td); + return td; + } + } + USB_error("alloc_ohci_TD failed!\n"); + return NULL; +} + +void free_ohci_TD(TD_T *td) +{ + int i; + + for (i = 0; i < MEM_POOL_UNIT_NUM; i++) + { + if ((uint32_t)&_mem_pool[i] == (uint32_t)td) + { + mem_debug("[FREE] [TD] - 0x%x\n", (int)td); + _unit_used[i] = 0; + _mem_pool_used--; + return; + } + } + USB_error("free_ohci_TD - not found!\n"); +} + +/*--------------------------------------------------------------------------*/ +/* EHCI QH allocate/free */ +/*--------------------------------------------------------------------------*/ +QH_T * alloc_ehci_QH(void) +{ + int i; + QH_T *qh = NULL; + + for (i = (_sidx+1) % MEM_POOL_UNIT_NUM; i != _sidx; i = (i+1) % MEM_POOL_UNIT_NUM) + { + if (_unit_used[i] == 0) + { + _unit_used[i] = 1; + _sidx = i; + _mem_pool_used++; + qh = (QH_T *)&_mem_pool[i]; + memset(qh, 0, sizeof(*qh)); + mem_debug("[ALLOC] [QH] - 0x%x\n", (int)qh); + break; + } + } + if (qh == NULL) + { + USB_error("alloc_ehci_QH failed!\n"); + return NULL; + } + qh->Curr_qTD = QTD_LIST_END; + qh->OL_Next_qTD = QTD_LIST_END; + qh->OL_Alt_Next_qTD = QTD_LIST_END; + qh->OL_Token = QTD_STS_HALT; + return qh; +} + +void free_ehci_QH(QH_T *qh) +{ + int i; + + for (i = 0; i < MEM_POOL_UNIT_NUM; i++) + { + if ((uint32_t)&_mem_pool[i] == (uint32_t)qh) + { + mem_debug("[FREE] [QH] - 0x%x\n", (int)qh); + _unit_used[i] = 0; + _mem_pool_used--; + return; + } + } + USB_debug("free_ehci_QH - not found! (ignored in case of multiple UTR)\n"); +} + +/*--------------------------------------------------------------------------*/ +/* EHCI qTD allocate/free */ +/*--------------------------------------------------------------------------*/ +qTD_T * alloc_ehci_qTD(UTR_T *utr) +{ + int i; + qTD_T *qtd; + + for (i = (_sidx+1) % MEM_POOL_UNIT_NUM; i != _sidx; i = (i+1) % MEM_POOL_UNIT_NUM) + { + if (_unit_used[i] == 0) + { + _unit_used[i] = 1; + _sidx = i; + _mem_pool_used++; + qtd = (qTD_T *)&_mem_pool[i]; + + memset(qtd, 0, sizeof(*qtd)); + qtd->Next_qTD = QTD_LIST_END; + qtd->Alt_Next_qTD = QTD_LIST_END; + qtd->Token = 0x1197B3F; // QTD_STS_HALT; visit_qtd() will not remove a qTD with this mark. It means the qTD still not ready for transfer. + qtd->utr = utr; + mem_debug("[ALLOC] [qTD] - 0x%x\n", (int)qtd); + return qtd; + } + } + USB_error("alloc_ehci_qTD failed!\n"); + return NULL; +} + +void free_ehci_qTD(qTD_T *qtd) +{ + int i; + + for (i = 0; i < MEM_POOL_UNIT_NUM; i++) + { + if ((uint32_t)&_mem_pool[i] == (uint32_t)qtd) + { + mem_debug("[FREE] [qTD] - 0x%x\n", (int)qtd); + _unit_used[i] = 0; + _mem_pool_used--; + return; + } + } + USB_error("free_ehci_qTD 0x%x - not found!\n", (int)qtd); +} + +/*--------------------------------------------------------------------------*/ +/* EHCI iTD allocate/free */ +/*--------------------------------------------------------------------------*/ +iTD_T * alloc_ehci_iTD(void) +{ + int i; + iTD_T *itd; + + for (i = (_sidx+1) % MEM_POOL_UNIT_NUM; i != _sidx; i = (i+1) % MEM_POOL_UNIT_NUM) + { + if (i+2 >= MEM_POOL_UNIT_NUM) + continue; + + if ((_unit_used[i] == 0) && (_unit_used[i+1] == 0)) + { + _unit_used[i] = _unit_used[i+1] = 1; + _sidx = i+1; + _mem_pool_used += 2; + itd = (iTD_T *)&_mem_pool[i]; + memset(itd, 0, sizeof(*itd)); + mem_debug("[ALLOC] [iTD] - 0x%x\n", (int)itd); + return itd; + } + } + USB_error("alloc_ehci_iTD failed!\n"); + return NULL; +} + +void free_ehci_iTD(iTD_T *itd) +{ + int i; + + for (i = 0; i+1 < MEM_POOL_UNIT_NUM; i++) + { + if ((uint32_t)&_mem_pool[i] == (uint32_t)itd) + { + mem_debug("[FREE] [iTD] - 0x%x\n", (int)itd); + _unit_used[i] = _unit_used[i+1] = 0; + _mem_pool_used -= 2; + return; + } + } + USB_error("free_ehci_iTD 0x%x - not found!\n", (int)itd); +} + +/*--------------------------------------------------------------------------*/ +/* EHCI iTD allocate/free */ +/*--------------------------------------------------------------------------*/ +siTD_T * alloc_ehci_siTD(void) +{ + int i; + siTD_T *sitd; + + for (i = (_sidx+1) % MEM_POOL_UNIT_NUM; i != _sidx; i = (i+1) % MEM_POOL_UNIT_NUM) + { + if (_unit_used[i] == 0) + { + _unit_used[i] = 1; + _sidx = i; + _mem_pool_used ++; + sitd = (siTD_T *)&_mem_pool[i]; + memset(sitd, 0, sizeof(*sitd)); + mem_debug("[ALLOC] [siTD] - 0x%x\n", (int)sitd); + return sitd; + } + } + USB_error("alloc_ehci_siTD failed!\n"); + return NULL; +} + +void free_ehci_siTD(siTD_T *sitd) +{ + int i; + + for (i = 0; i < MEM_POOL_UNIT_NUM; i++) + { + if ((uint32_t)&_mem_pool[i] == (uint32_t)sitd) + { + mem_debug("[FREE] [siTD] - 0x%x\n", (int)sitd); + _unit_used[i] = 0; + _mem_pool_used--; + return; + } + } + USB_error("free_ehci_siTD 0x%x - not found!\n", (int)sitd); +} + +/// @endcond HIDDEN_SYMBOLS + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ + diff --git a/bsp/nuvoton/libraries/m480/USBHostLib/src/ohci.c b/bsp/nuvoton/libraries/m480/USBHostLib/src/ohci.c new file mode 100644 index 0000000000000000000000000000000000000000..fd5a87fb9fb47f2110583046e3c17297afbdee1b --- /dev/null +++ b/bsp/nuvoton/libraries/m480/USBHostLib/src/ohci.c @@ -0,0 +1,1292 @@ +/**************************************************************************//** + * @file ohci.c + * @version V1.10 + * @brief USB Host library OHCI (USB 1.1) host controller driver. + * + * SPDX-License-Identifier: Apache-2.0 + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include +#include + +#include "NuMicro.h" + +#include "usb.h" +#include "hub.h" +#include "ohci.h" + +/// @cond HIDDEN_SYMBOLS + +//#define TD_debug printf +#define TD_debug(...) + +//#define ED_debug printf +#define ED_debug(...) + +#ifdef __ICCARM__ +#pragma data_alignment=256 +HCCA_T _hcca; +#else +HCCA_T _hcca __attribute__((aligned(256))); +#endif + +ED_T * _Ied[6]; + + +static ED_T *ed_remove_list; + +static void add_to_ED_remove_list(ED_T *ed) +{ + ED_T *p; + + ED_debug("add_to_ED_remove_list - 0x%x (0x%x)\n", (int)ed, ed->Info); + DISABLE_OHCI_IRQ(); + + /* check if this ED found in ed_remove_list */ + p = ed_remove_list; + while (p) + { + if (p == ed) + { + ENABLE_OHCI_IRQ(); /* This ED found in ed_remove_list */ + return; /* do nothing */ + } + p = p->next; + } + + ed->Info |= ED_SKIP; /* ask OHCI controller skip this ED */ + ed->next = ed_remove_list; + ed_remove_list = ed; /* insert to the head of ed_remove_list */ + ENABLE_OHCI_IRQ(); + _ohci->HcInterruptStatus = USBH_HcInterruptStatus_SF_Msk; + _ohci->HcInterruptEnable |= USBH_HcInterruptEnable_SF_Msk; + usbh_delay_ms(2); /* Full speed wait 2 ms is enough */ +} + +static int ohci_reset(void) +{ + volatile int t0; + + /* Disable HC interrupts */ + _ohci->HcInterruptDisable = USBH_HcInterruptDisable_MIE_Msk; + + /* HC Reset requires max 10 ms delay */ + _ohci->HcControl = 0; + _ohci->HcCommandStatus = USBH_HcCommandStatus_HCR_Msk; + + usbh_delay_ms(10); + + /* Check if OHCI reset completed? */ + if ((USBH->HcCommandStatus & USBH_HcCommandStatus_HCR_Msk) != 0) + { + USB_error("Error! - USB OHCI reset timed out!\n"); + return -1; + } + + USBH->HcRhStatus = USBH_HcRhStatus_OCI_Msk | USBH_HcRhStatus_LPS_Msk; + + USBH->HcControl = HCFS_RESET; + + usbh_delay_ms(10); + + /* Check if OHCI reset completed? */ + if ((USBH->HcCommandStatus & USBH_HcCommandStatus_HCR_Msk) != 0) + { + USB_error("Error! - USB HC reset timed out!\n"); + return -1; + } + return 0; +} + +static void init_hcca_int_table() +{ + ED_T *ed_p; + int i, idx, interval; + + memset(_hcca.int_table, 0, sizeof(_hcca.int_table)); + + for (i = 5; i >= 0; i--) /* interval = i^2 */ + { + _Ied[i] = alloc_ohci_ED(); + _Ied[i]->Info = ED_SKIP; + + interval = 0x1 << i; + + for (idx = interval - 1; idx < 32; idx += interval) + { + if (_hcca.int_table[idx] == 0) /* is empty list, insert directly */ + { + _hcca.int_table[idx] = (uint32_t)_Ied[i]; + } + else + { + ed_p = (ED_T *)_hcca.int_table[idx]; + + while (1) + { + if (ed_p == _Ied[i]) + break; /* already chained by previous visit */ + + if (ed_p->NextED == 0) /* reach end of list? */ + { + ed_p->NextED = (uint32_t)_Ied[i]; + break; + } + ed_p = (ED_T *)ed_p->NextED; + } + } + } + } +} + +static ED_T * get_int_tree_head_node(int interval) +{ + int i; + + for (i = 0; i < 5; i++) + { + interval >>= 1; + if (interval == 0) + return _Ied[i]; + } + return _Ied[5]; /* for interval >= 32 */ +} + +static int get_ohci_interval(int interval) +{ + int i, bInterval = 1; + + for (i = 0; i < 5; i++) + { + interval >>= 1; + if (interval == 0) + return bInterval; + bInterval *= 2; + } + return 32; /* for interval >= 32 */ +} + + +static int ohci_init(void) +{ + uint32_t fminterval; + volatile int i; + + if (ohci_reset() < 0) + return -1; + + ed_remove_list = NULL; + + init_hcca_int_table(); + + /* Tell the controller where the control and bulk lists are + * The lists are empty now. */ + _ohci->HcControlHeadED = 0; /* control ED list head */ + _ohci->HcBulkHeadED = 0; /* bulk ED list head */ + + _ohci->HcHCCA = (uint32_t)&_hcca; /* HCCA area */ + + /* periodic start 90% of frame interval */ + fminterval = 0x2edf; /* 11,999 */ + _ohci->HcPeriodicStart = (fminterval*9)/10; + + /* set FSLargestDataPacket, 10,104 for 0x2edf frame interval */ + fminterval |= ((((fminterval - 210) * 6) / 7) << 16); + _ohci->HcFmInterval = fminterval; + + _ohci->HcLSThreshold = 0x628; + + /* start controller operations */ + _ohci->HcControl = HCFS_OPER | (0x3 << USBH_HcControl_CBSR_Pos); + +#ifdef OHCI_PER_PORT_POWER + _ohci->HcRhDescriptorB = 0x60000; + _ohci->HcRhPortStatus[0] = USBH_HcRhPortStatus_PPS_Msk; + _ohci->HcRhPortStatus[1] = USBH_HcRhPortStatus_PPS_Msk; +#else + _ohci->HcRhDescriptorA = (USBH->HcRhDescriptorA | (1<<9)) & ~USBH_HcRhDescriptorA_PSM_Msk; + _ohci->HcRhStatus = USBH_HcRhStatus_LPSC_Msk; +#endif + + _ohci->HcInterruptEnable = USBH_HcInterruptEnable_MIE_Msk | USBH_HcInterruptEnable_WDH_Msk | USBH_HcInterruptEnable_SF_Msk; + + /* POTPGT delay is bits 24-31, in 20 ms units. */ + usbh_delay_ms(20); + return 0; +} + +static void ohci_suspend(void) +{ + /* set port suspend if connected */ + if (_ohci->HcRhPortStatus[0] & 0x1) + _ohci->HcRhPortStatus[0] = 0x4; + + if (_ohci->HcRhPortStatus[1] & 0x1) + _ohci->HcRhPortStatus[1] = 0x4; + + /* enable Device Remote Wakeup */ + _ohci->HcRhStatus |= USBH_HcRhStatus_DRWE_Msk; + + /* enable USBH RHSC interrupt for system wakeup */ + _ohci->HcInterruptEnable |= USBH_HcInterruptEnable_RHSC_Msk | USBH_HcInterruptEnable_RD_Msk; + + /* set Host Controller enter suspend state */ + _ohci->HcControl = (USBH->HcControl & ~USBH_HcControl_HCFS_Msk) | (3 << USBH_HcControl_HCFS_Pos); +} + +static void ohci_resume(void) +{ + _ohci->HcControl = (USBH->HcControl & ~USBH_HcControl_HCFS_Msk) | (1 << USBH_HcControl_HCFS_Pos); + _ohci->HcControl = (USBH->HcControl & ~USBH_HcControl_HCFS_Msk) | (2 << USBH_HcControl_HCFS_Pos); + + if (_ohci->HcRhPortStatus[0] & 0x4) + _ohci->HcRhPortStatus[0] = 0x8; + if (_ohci->HcRhPortStatus[1] & 0x4) + _ohci->HcRhPortStatus[1] = 0x8; +} + +static void ohci_shutdown(void) +{ + ohci_suspend(); + NVIC_DisableIRQ(USBH_IRQn); +#ifndef OHCI_PER_PORT_POWER + _ohci->HcRhStatus = USBH_HcRhStatus_LPS_Msk; +#endif +} + + +/* + * Quit current trasnfer via UTR or hardware EP. + */ +static int ohci_quit_xfer(UTR_T *utr, EP_INFO_T *ep) +{ + ED_T *ed; + + if (utr != NULL) + { + if (utr->ep == NULL) + return USBH_ERR_NOT_FOUND; + + ed = (ED_T *)(utr->ep->hw_pipe); + + if (!ed) + return USBH_ERR_NOT_FOUND; + + /* add the endpoint to remove list, it will be removed on the next start of frame */ + add_to_ED_remove_list(ed); + utr->ep->hw_pipe = NULL; + } + + if ((ep != NULL) && (ep->hw_pipe != NULL)) + { + ed = (ED_T *)(ep->hw_pipe); + /* add the endpoint to remove list, it will be removed on the next start of frame */ + add_to_ED_remove_list(ed); + ep->hw_pipe = NULL; + } + + return 0; +} + +uint32_t ed_make_info(UDEV_T *udev, EP_INFO_T *ep) +{ + uint32_t info; + + if (ep == NULL) /* is a control endpoint */ + { + /* control endpoint direction is from TD */ + if (udev->descriptor.bMaxPacketSize0 == 0) /* is 0 if device descriptor still not obtained. */ + { + if (udev->speed == SPEED_LOW) /* give a default maximum packet size */ + udev->descriptor.bMaxPacketSize0 = 8; + else + udev->descriptor.bMaxPacketSize0 = 64; + } + info = (udev->descriptor.bMaxPacketSize0 << 16) /* Control endpoint Maximum Packet Size from device descriptor */ + | ED_DIR_BY_TD /* Direction (Get direction From TD) */ + | ED_FORMAT_GENERAL /* General format */ + | (0 << ED_CTRL_EN_Pos); /* Endpoint address 0 */ + } + else /* Other endpoint direction is from endpoint descriptor */ + { + info = (ep->wMaxPacketSize << 16); /* Maximum Packet Size from endpoint */ + + info |= ((ep->bEndpointAddress & 0xf) << ED_CTRL_EN_Pos); /* Endpoint Number */ + + if ((ep->bEndpointAddress & EP_ADDR_DIR_MASK) == EP_ADDR_DIR_IN) + info |= ED_DIR_IN; + else + info |= ED_DIR_OUT; + + if ((ep->bmAttributes & EP_ATTR_TT_MASK) == EP_ATTR_TT_ISO) + info |= ED_FORMAT_ISO; + else + info |= ED_FORMAT_GENERAL; + } + + info |= ((udev->speed == SPEED_LOW) ? ED_SPEED_LOW : ED_SPEED_FULL); /* Speed */ + info |= (udev->dev_num); /* Function Address */ + + return info; +} + +static void write_td(TD_T *td, uint32_t info, uint8_t *buff, uint32_t data_len) +{ + td->Info = info; + td->CBP = (uint32_t)((!buff || !data_len) ? 0 : buff); + td->BE = (uint32_t)((!buff || !data_len ) ? 0 : (uint32_t)buff + data_len - 1); + td->buff_start = td->CBP; + // TD_debug("TD [0x%x]: 0x%x, 0x%x, 0x%x\n", (int)td, td->Info, td->CBP, td->BE); +} + +static int ohci_ctrl_xfer(UTR_T *utr) +{ + UDEV_T *udev; + ED_T *ed; + TD_T *td_setup, *td_data, *td_status; + uint32_t info; + + udev = utr->udev; + + /*------------------------------------------------------------------------------------*/ + /* Allocate ED and TDs */ + /*------------------------------------------------------------------------------------*/ + td_setup = alloc_ohci_TD(utr); + + if (utr->data_len > 0) + td_data = alloc_ohci_TD(utr); + else + td_data = NULL; + + td_status = alloc_ohci_TD(utr); + + if (td_status == NULL) + { + free_ohci_TD(td_setup); + if (utr->data_len > 0) + free_ohci_TD(td_data); + return USBH_ERR_MEMORY_OUT; + } + + /* Check if there's any transfer pending on this endpoint... */ + if (udev->ep0.hw_pipe == NULL) + { + ed = alloc_ohci_ED(); + if (ed == NULL) + { + free_ohci_TD(td_setup); + free_ohci_TD(td_status); + if (utr->data_len > 0) + free_ohci_TD(td_data); + return USBH_ERR_MEMORY_OUT; + } + } + else + ed = (ED_T *)udev->ep0.hw_pipe; + + /*------------------------------------------------------------------------------------*/ + /* prepare SETUP stage TD */ + /*------------------------------------------------------------------------------------*/ + info = TD_CC | TD_T_DATA0 | TD_TYPE_CTRL; + write_td(td_setup, info, (uint8_t *)&utr->setup, 8); + td_setup->ed = ed; + + /*------------------------------------------------------------------------------------*/ + /* prepare DATA stage TD */ + /*------------------------------------------------------------------------------------*/ + if (utr->data_len > 0) + { + if ((utr->setup.bmRequestType & 0x80) == REQ_TYPE_OUT) + info = (TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 | TD_TYPE_CTRL | TD_CTRL_DATA); + else + info = (TD_CC | TD_R | TD_DP_IN | TD_T_DATA1 | TD_TYPE_CTRL | TD_CTRL_DATA); + + write_td(td_data, info, utr->buff, utr->data_len); + td_data->ed = ed; + td_setup->NextTD = (uint32_t)td_data; + td_setup->next = td_data; + td_data->NextTD = (uint32_t)td_status; + td_data->next = td_status; + } + else + { + td_setup->NextTD = (uint32_t)td_status; + td_setup->next = td_status; + } + + /*------------------------------------------------------------------------------------*/ + /* prepare STATUS stage TD */ + /*------------------------------------------------------------------------------------*/ + ed->Info = ed_make_info(udev, NULL); + if ((utr->setup.bmRequestType & 0x80) == REQ_TYPE_OUT) + info = (TD_CC | TD_DP_IN | TD_T_DATA1 | TD_TYPE_CTRL); + else + info = (TD_CC | TD_DP_OUT | TD_T_DATA1 | TD_TYPE_CTRL); + + write_td(td_status, info, NULL, 0); + td_status->ed = ed; + td_status->NextTD = 0; + td_status->next = 0; + + /*------------------------------------------------------------------------------------*/ + /* prepare ED */ + /*------------------------------------------------------------------------------------*/ + ed->TailP = 0; + ed->HeadP = (uint32_t)td_setup; + ed->Info = ed_make_info(udev, NULL); + ed->NextED = 0; + + //TD_debug("TD SETUP [0x%x]: 0x%x, 0x%x, 0x%x, 0x%x\n", (int)td_setup, td_setup->Info, td_setup->CBP, td_setup->BE, td_setup->NextTD); + //if (td_data) + // TD_debug("TD DATA [0x%x]: 0x%x, 0x%x, 0x%x, 0x%x\n", (int)td_data, td_data->Info, td_data->CBP, td_data->BE, td_data->NextTD); + //TD_debug("TD STATUS [0x%x]: 0x%x, 0x%x, 0x%x, 0x%x\n", (int)td_status, td_status->Info, td_status->CBP, td_status->BE, td_status->NextTD); + ED_debug("Xfer ED 0x%x: 0x%x 0x%x 0x%x 0x%x\n", (int)ed, ed->Info, ed->TailP, ed->HeadP, ed->NextED); + + if (utr->data_len > 0) + utr->td_cnt = 3; + else + utr->td_cnt = 2; + + utr->ep = &udev->ep0; /* driver can find EP from UTR */ + udev->ep0.hw_pipe = (void *)ed; /* driver can find ED from EP */ + + /*------------------------------------------------------------------------------------*/ + /* Start transfer */ + /*------------------------------------------------------------------------------------*/ + DISABLE_OHCI_IRQ(); + _ohci->HcControlHeadED = (uint32_t)ed; /* Link ED to OHCI */ + _ohci->HcControl |= USBH_HcControl_CLE_Msk; /* enable control list */ + ENABLE_OHCI_IRQ(); + _ohci->HcCommandStatus = USBH_HcCommandStatus_CLF_Msk; /* start Control list */ + + return 0; +} + +static int ohci_bulk_xfer(UTR_T *utr) +{ + UDEV_T *udev = utr->udev; + EP_INFO_T *ep = utr->ep; + ED_T *ed; + TD_T *td, *td_p, *td_list = NULL; + uint32_t info; + uint32_t data_len, xfer_len; + int8_t bIsNewED = 0; + uint8_t *buff; + + /*------------------------------------------------------------------------------------*/ + /* Check if there's uncompleted transfer on this endpoint... */ + /* Prepare ED */ + /*------------------------------------------------------------------------------------*/ + info = ed_make_info(udev, ep); + + /* Check if there's any transfer pending on this endpoint... */ + ed = (ED_T *)_ohci->HcBulkHeadED; /* get the head of bulk endpoint list */ + while (ed != NULL) + { + if (ed->Info == info) /* have transfer of this EP not completed? */ + { + if ((ed->HeadP & 0xFFFFFFF0) != (ed->TailP & 0xFFFFFFF0)) + return USBH_ERR_OHCI_EP_BUSY; /* endpoint is busy */ + else + break; /* ED already there... */ + } + ed = (ED_T *)ed->NextED; + } + + if (ed == NULL) + { + bIsNewED = 1; + ed = alloc_ohci_ED(); /* allocate an Endpoint Descriptor */ + if (ed == NULL) + return USBH_ERR_MEMORY_OUT; + ed->Info = info; + ed->HeadP = 0; + ED_debug("Link BULK ED 0x%x: 0x%x 0x%x 0x%x 0x%x\n", (int)ed, ed->Info, ed->TailP, ed->HeadP, ed->NextED); + } + + ep->hw_pipe = (void *)ed; + + /*------------------------------------------------------------------------------------*/ + /* Prepare TDs */ + /*------------------------------------------------------------------------------------*/ + utr->td_cnt = 0; + data_len = utr->data_len; + buff = utr->buff; + + do + { + if ((ep->bEndpointAddress & EP_ADDR_DIR_MASK) == EP_ADDR_DIR_OUT) + info = (TD_CC | TD_R | TD_DP_OUT | TD_TYPE_BULK); + else + info = (TD_CC | TD_R | TD_DP_IN | TD_TYPE_BULK); + + info &= ~(1 << 25); /* Data toggle from ED toggleCarry bit */ + + if (data_len > 4096) /* maximum transfer length is 4K for each TD */ + xfer_len = 4096; + else + xfer_len = data_len; /* remaining data length < 4K */ + + td = alloc_ohci_TD(utr); /* allocate a TD */ + if (td == NULL) + goto mem_out; + /* fill this TD */ + write_td(td, info, buff, xfer_len); + td->ed = ed; + + utr->td_cnt++; /* increase TD count, for recalim counter */ + + buff += xfer_len; /* advanced buffer pointer */ + data_len -= xfer_len; + + /* chain to end of TD list */ + if (td_list == NULL) + { + td_list = td; + } + else + { + td_p = td_list; + while (td_p->NextTD != 0) + td_p = (TD_T *)td_p->NextTD; + td_p->NextTD = (uint32_t)td; + } + + } + while (data_len > 0); + + /*------------------------------------------------------------------------------------*/ + /* Start transfer */ + /*------------------------------------------------------------------------------------*/ + utr->status = 0; + DISABLE_OHCI_IRQ(); + ed->HeadP = (ed->HeadP & 0x2) | (uint32_t)td_list; /* keep toggleCarry bit */ + if (bIsNewED) + { + ed->HeadP = (uint32_t)td_list; + /* Link ED to OHCI Bulk List */ + ed->NextED = _ohci->HcBulkHeadED; + _ohci->HcBulkHeadED = (uint32_t)ed; + } + ENABLE_OHCI_IRQ(); + _ohci->HcControl |= USBH_HcControl_BLE_Msk; /* enable bulk list */ + _ohci->HcCommandStatus = USBH_HcCommandStatus_BLF_Msk; /* start bulk list */ + + return 0; + +mem_out: + while (td_list != NULL) + { + td = td_list; + td_list = (TD_T *)td_list->NextTD; + free_ohci_TD(td); + } + free_ohci_ED(ed); + return USBH_ERR_MEMORY_OUT; +} + +static int ohci_int_xfer(UTR_T *utr) +{ + UDEV_T *udev = utr->udev; + EP_INFO_T *ep = utr->ep; + ED_T *ed, *ied; + TD_T *td, *td_new; + uint32_t info; + int8_t bIsNewED = 0; + + if (utr->data_len > 64) /* USB 1.1 interrupt transfer maximum packet size is 64 */ + return USBH_ERR_INVALID_PARAM; + + td_new = alloc_ohci_TD(utr); /* allocate a TD for dummy TD */ + if (td_new == NULL) + return USBH_ERR_MEMORY_OUT; + + ied = get_int_tree_head_node(ep->bInterval); /* get head node of this interval */ + + /*------------------------------------------------------------------------------------*/ + /* Find if this ED was already in the list */ + /*------------------------------------------------------------------------------------*/ + info = ed_make_info(udev, ep); + ed = ied; + while (ed != NULL) + { + if (ed->Info == info) + break; /* Endpoint found */ + ed = (ED_T *)ed->NextED; + } + + if (ed == NULL) /* ED not found, create it */ + { + bIsNewED = 1; + ed = alloc_ohci_ED(); /* allocate an Endpoint Descriptor */ + if (ed == NULL) + return USBH_ERR_MEMORY_OUT; + ed->Info = info; + ed->HeadP = 0; + ed->bInterval = ep->bInterval; + + td = alloc_ohci_TD(NULL); /* allocate the initial dummy TD for ED */ + if (td == NULL) + { + free_ohci_ED(ed); + free_ohci_TD(td_new); + return USBH_ERR_MEMORY_OUT; + } + ed->HeadP = (uint32_t)td; /* Let both HeadP and TailP point to dummy TD */ + ed->TailP = ed->HeadP; + } + else + { + td = (TD_T *)(ed->TailP & ~0xf); /* TailP always point to the dummy TD */ + } + ep->hw_pipe = (void *)ed; + + /*------------------------------------------------------------------------------------*/ + /* Prepare TD */ + /*------------------------------------------------------------------------------------*/ + if ((ep->bEndpointAddress & EP_ADDR_DIR_MASK) == EP_ADDR_DIR_OUT) + info = (TD_CC | TD_R | TD_DP_OUT | TD_TYPE_INT); + else + info = (TD_CC | TD_R | TD_DP_IN | TD_TYPE_INT); + + /* Keep data toggle */ + info = (info & ~(1<<25)) | (td->Info & (1<<25)); + + /* fill this TD */ + write_td(td, info, utr->buff, utr->data_len); + td->ed = ed; + td->NextTD = (uint32_t)td_new; + td->utr = utr; + utr->td_cnt = 1; /* increase TD count, for recalim counter */ + utr->status = 0; + + /*------------------------------------------------------------------------------------*/ + /* Hook ED and TD list to HCCA interrupt table */ + /*------------------------------------------------------------------------------------*/ + DISABLE_OHCI_IRQ(); + + ed->TailP = (uint32_t)td_new; + if (bIsNewED) + { + /* Add to list of the same interval */ + ed->NextED = ied->NextED; + ied->NextED = (uint32_t)ed; + } + + ENABLE_OHCI_IRQ(); + + //printf("Link INT ED 0x%x: 0x%x 0x%x 0x%x 0x%x\n", (int)ed, ed->Info, ed->TailP, ed->HeadP, ed->NextED); + + _ohci->HcControl |= USBH_HcControl_PLE_Msk; /* periodic list enable */ + return 0; +} + +static int ohci_iso_xfer(UTR_T *utr) +{ + UDEV_T *udev = utr->udev; + EP_INFO_T *ep = utr->ep; + ED_T *ed, *ied; + TD_T *td, *td_list, *last_td; + int i; + uint32_t info; + uint32_t buff_addr; + int8_t bIsNewED = 0; + + ied = get_int_tree_head_node(ep->bInterval); /* get head node of this interval */ + + /*------------------------------------------------------------------------------------*/ + /* Find if this ED was already in the list */ + /*------------------------------------------------------------------------------------*/ + info = ed_make_info(udev, ep); + ed = ied; + while (ed != NULL) + { + if (ed->Info == info) + break; /* Endpoint found */ + ed = (ED_T *)ed->NextED; + } + + if (ed == NULL) /* ED not found, create it */ + { + bIsNewED = 1; + ed = alloc_ohci_ED(); /* allocate an Endpoint Descriptor */ + if (ed == NULL) + return USBH_ERR_MEMORY_OUT; + ed->Info = info; + ed->HeadP = 0; + ed->bInterval = ep->bInterval; + } + else + + ep->hw_pipe = (void *)ed; + + /*------------------------------------------------------------------------------------*/ + /* Prepare TDs */ + /*------------------------------------------------------------------------------------*/ + if (utr->bIsoNewSched) /* Is the starting of isochronous streaming? */ + ed->next_sf = _hcca.frame_no + OHCI_ISO_DELAY; + + utr->td_cnt = 0; + utr->iso_sf = ed->next_sf; + + last_td = NULL; + td_list = NULL; + + for (i = 0; i < IF_PER_UTR; i++) + { + utr->iso_status[i] = USBH_ERR_NOT_ACCESS1; + + td = alloc_ohci_TD(utr); /* allocate a TD */ + if (td == NULL) + goto mem_out; + /* fill this TD */ + buff_addr = (uint32_t)(utr->iso_buff[i]); + td->Info = (TD_CC | TD_TYPE_ISO) | ed->next_sf; + ed->next_sf += get_ohci_interval(ed->bInterval); + td->CBP = buff_addr & ~0xFFF; + td->BE = buff_addr + utr->iso_xlen[i] - 1; + td->PSW[0] = 0xE000 | (buff_addr & 0xFFF); + + td->ed = ed; + utr->td_cnt++; /* increase TD count, for reclaim counter */ + + /* chain to end of TD list */ + if (td_list == NULL) + td_list = td; + else + last_td->NextTD = (uint32_t)td; + + last_td = td; + }; + + /*------------------------------------------------------------------------------------*/ + /* Hook ED and TD list to HCCA interrupt table */ + /*------------------------------------------------------------------------------------*/ + utr->status = 0; + DISABLE_OHCI_IRQ(); + + if ((ed->HeadP & ~0x3) == 0) + ed->HeadP = (ed->HeadP & 0x2) | (uint32_t)td_list; /* keep toggleCarry bit */ + else + { + /* find the tail of TDs under this ED */ + td = (TD_T *)(ed->HeadP & ~0x3); + while (td->NextTD != 0) + { + td = (TD_T *)td->NextTD; + } + td->NextTD = (uint32_t)td_list; + } + + if (bIsNewED) + { + /* Add to list of the same interval */ + ed->NextED = ied->NextED; + ied->NextED = (uint32_t)ed; + } + + ENABLE_OHCI_IRQ(); + ED_debug("Link ISO ED 0x%x: 0x%x 0x%x 0x%x 0x%x\n", (int)ed, ed->Info, ed->TailP, ed->HeadP, ed->NextED); + _ohci->HcControl |= USBH_HcControl_PLE_Msk | USBH_HcControl_IE_Msk; /* enable periodic list and isochronous transfer */ + + return 0; + +mem_out: + while (td_list != NULL) + { + td = td_list; + td_list = (TD_T *)td_list->NextTD; + free_ohci_TD(td); + } + free_ohci_ED(ed); + return USBH_ERR_MEMORY_OUT; +} + +static UDEV_T * ohci_find_device_by_port(int port) +{ + UDEV_T *udev; + + udev = g_udev_list; + while (udev != NULL) + { + if ((udev->parent == NULL) && (udev->port_num == port) && + ((udev->speed == SPEED_LOW) || (udev->speed == SPEED_FULL))) + return udev; + udev = udev->next; + } + return NULL; +} + +static int ohci_rh_port_reset(int port) +{ + int retry; + int reset_time; + uint32_t t0; + + reset_time = usbh_tick_from_millisecond(PORT_RESET_TIME_MS); + + for (retry = 0; retry < PORT_RESET_RETRY; retry++) + { + _ohci->HcRhPortStatus[port] = USBH_HcRhPortStatus_PRS_Msk; + + t0 = usbh_get_ticks(); + while (usbh_get_ticks() - t0 < (reset_time)+1) + { + /* + * If device is disconnected or port enabled, we can stop port reset. + */ + if (((_ohci->HcRhPortStatus[port] & USBH_HcRhPortStatus_CCS_Msk) == 0) || + ((_ohci->HcRhPortStatus[port] & (USBH_HcRhPortStatus_PES_Msk | USBH_HcRhPortStatus_CCS_Msk)) == (USBH_HcRhPortStatus_PES_Msk | USBH_HcRhPortStatus_CCS_Msk))) + goto port_reset_done; + } + reset_time += PORT_RESET_RETRY_INC_MS; + } + + USB_debug("OHCI port %d - port reset failed!\n", port+1); + return USBH_ERR_PORT_RESET; + +port_reset_done: + if ((_ohci->HcRhPortStatus[port] & USBH_HcRhPortStatus_CCS_Msk) == 0) /* check again if device disconnected */ + { + _ohci->HcRhPortStatus[port] = USBH_HcRhPortStatus_CSC_Msk; /* clear CSC */ + return USBH_ERR_DISCONNECTED; + } + return USBH_OK; /* port reset success */ +} + +static int ohci_rh_polling(void) +{ + int i, change = 0; + UDEV_T *udev; + int ret; + + for (i = 0; i < 2; i++) + { + if (((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x1) && (i == 0)) + continue; /* M480LD OHCI has no root hub port 0 */ + + /* clear unwanted port change status */ + _ohci->HcRhPortStatus[i] = USBH_HcRhPortStatus_OCIC_Msk | USBH_HcRhPortStatus_PRSC_Msk | + USBH_HcRhPortStatus_PSSC_Msk | USBH_HcRhPortStatus_PESC_Msk; + + if ((_ohci->HcRhPortStatus[i] & USBH_HcRhPortStatus_CSC_Msk) == 0) + continue; + + /*--------------------------------------------------------------------------------*/ + /* connect status change */ + /*--------------------------------------------------------------------------------*/ + + _ohci->HcRhPortStatus[i] = USBH_HcRhPortStatus_CSC_Msk; /* clear CSC */ + + if (_ohci->HcRhPortStatus[i] & USBH_HcRhPortStatus_CCS_Msk) + { + /*----------------------------------------------------------------------------*/ + /* First of all, check if there's any previously connected device. */ + /*----------------------------------------------------------------------------*/ + while (1) + { + udev = ohci_find_device_by_port(i+1); + if (udev == NULL) + break; + usbh_disconnect_device(udev); + } + + if (ohci_rh_port_reset(i) != USBH_OK) + continue; + + /* + * Port reset success... + */ + udev = alloc_device(); + if (udev == NULL) + continue; + + udev->parent = NULL; + udev->port_num = i+1; + if (_ohci->HcRhPortStatus[i] & USBH_HcRhPortStatus_LSDA_Msk) + udev->speed = SPEED_LOW; + else + udev->speed = SPEED_FULL; + udev->hc_driver = &ohci_driver; + + ret = usbh_connect_device(udev); + if (ret < 0) + { + USB_error("connect_device error! [%d]\n", ret); + free_device(udev); + } + + change = 1; + } + else + { + /* + * Device disconnected + */ + while (1) + { + udev = ohci_find_device_by_port(i+1); + if (udev == NULL) + break; + usbh_disconnect_device(udev); + } + change = 1; + } + } + return change; +} + +void td_done(TD_T *td) +{ + UTR_T *utr = td->utr; + uint32_t info; + int cc; + + info = td->Info; + + TD_debug("td_done: 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", (int)td, td->Info, td->CBP, td->NextTD, td->BE); + + /* ISO ... drivers see per-TD length/status */ + if ((info & TD_TYPE_Msk) == TD_TYPE_ISO) + { + uint16_t sf; + int idx; + + sf = info & 0xFFFF; + idx = ((sf + 0x10000 - utr->iso_sf) & 0xFFFF) / get_ohci_interval(td->ed->bInterval); + if (idx >= IF_PER_UTR) + { + USB_error("ISO invalid index!! %d, %d\n", sf, utr->iso_sf); + goto td_out; + } + + cc = (td->PSW[0] >> 12) & 0xF; + if (cc == 0xF) /* this frame was not transferred */ + { + USB_debug("ISO F %d N/A!\n", sf); + utr->iso_status[idx] = USBH_ERR_SCH_OVERRUN; + goto td_out; + } + if ((cc != 0) && (cc != CC_DATA_UNDERRUN)) + { + utr->iso_status[idx] = USBH_ERR_CC_NO_ERR - cc; + goto td_out; + } + utr->iso_status[idx] = 0; + utr->iso_xlen[idx] = td->PSW[0] & 0x7FF; + } + else + { + cc = TD_CC_GET(info); + + /* short packet is fine */ + if ((cc != CC_NOERROR) && (cc != CC_DATA_UNDERRUN)) + { + USB_error("TD error, CC = 0x%x\n", cc); + if (cc == CC_STALL) + utr->status = USBH_ERR_STALL; + else + utr->status = USBH_ERR_TRANSFER; + } + + switch (info & TD_TYPE_Msk) + { + case TD_TYPE_CTRL: + if (info & TD_CTRL_DATA) + { + if (td->CBP == 0) + utr->xfer_len += td->BE - td->buff_start + 1; + else + utr->xfer_len += td->CBP - td->buff_start; + } + break; + + case TD_TYPE_BULK: + case TD_TYPE_INT: + if (td->CBP == 0) + utr->xfer_len += td->BE - td->buff_start + 1; + else + utr->xfer_len += td->CBP - td->buff_start; + break; + } + } + +td_out: + + utr->td_cnt--; + + /* If all TDs are done, call-back to requester. */ + if (utr->td_cnt == 0) + { + utr->bIsTransferDone = 1; + if (utr->func) + utr->func(utr); + } +} + +/* in IRQ context */ +static void remove_ed() +{ + ED_T *ed, *ed_p, *ied; + TD_T *td, *td_next; + UTR_T *utr; + int found; + + while (ed_remove_list != NULL) + { + ED_debug("Remove ED: 0x%x, %d\n", (int)ed_remove_list, ed_remove_list->bInterval); + ed_p = ed_remove_list; + found = 0; + + /*--------------------------------------------------------------------------------*/ + /* Remove endpoint from Control List if found */ + /*--------------------------------------------------------------------------------*/ + if ((ed_p->Info & ED_EP_ADDR_Msk) == 0) + { + if (_ohci->HcControlHeadED == (uint32_t)ed_p) + { + _ohci->HcControlHeadED = (uint32_t)ed_p->NextED; + found = 1; + } + else + { + ed = (ED_T *)_ohci->HcControlHeadED; + while (ed != NULL) + { + if (ed->NextED == (uint32_t)ed_p) + { + ed->NextED = ed_p->NextED; + found = 1; + } + ed = (ED_T *)ed->NextED; + } + } + } + + /*--------------------------------------------------------------------------------*/ + /* Remove INT or ISO endpoint from HCCA interrupt table */ + /*--------------------------------------------------------------------------------*/ + else if (ed_p->bInterval > 0) + { + ied = get_int_tree_head_node(ed_p->bInterval); + + ed = ied; + while (ed != NULL) + { + if (ed->NextED == (uint32_t)ed_p) + { + ed->NextED = ed_p->NextED; + found = 1; + break; + } + ed = (ED_T *)ed->NextED; + } + } + + /*--------------------------------------------------------------------------------*/ + /* Remove endpoint from Bulk List if found */ + /*--------------------------------------------------------------------------------*/ + else + { + if (_ohci->HcBulkHeadED == (uint32_t)ed_p) + { + ed = (ED_T *)ed_p; + _ohci->HcBulkHeadED = ed_p->NextED; + found = 1; + } + else + { + ed = (ED_T *)_ohci->HcBulkHeadED; + while (ed != NULL) + { + if (ed->NextED == (uint32_t)ed_p) + { + ed->NextED = ed_p->NextED; + found = 1; + } + ed = (ED_T *)ed->NextED; + } + } + } + + /*--------------------------------------------------------------------------------*/ + /* Remove and free all TDs under this endpoint */ + /*--------------------------------------------------------------------------------*/ + if (found) + { + td = (TD_T *)(ed_p->HeadP & ~0x3); + if (td != NULL) + { + while (td != NULL) + { + utr = td->utr; + td_next = (TD_T *)td->NextTD; + free_ohci_TD(td); + td = td_next; + + utr->td_cnt--; + if (utr->td_cnt == 0) + { + utr->status = USBH_ERR_ABORT; + utr->bIsTransferDone = 1; + if (utr->func) + utr->func(utr); + } + } + } + } + + /* + * Done. Remove this ED from [ed_remove_list] and free it. + */ + ed_remove_list = ed_p->next; + free_ohci_ED(ed_p); + } +} + + +//static irqreturn_t ohci_irq (struct usb_hcd *hcd) +void OHCI_IRQHandler(void) +{ + TD_T *td, *td_prev, *td_next; + uint32_t int_sts; + + int_sts = _ohci->HcInterruptStatus; + + //USB_debug("ohci int_sts = 0x%x\n", int_sts); + + if ((_ohci->HcInterruptEnable & USBH_HcInterruptEnable_SF_Msk) && + (int_sts & USBH_HcInterruptStatus_SF_Msk)) + { + int_sts &= ~USBH_HcInterruptStatus_SF_Msk; + + _ohci->HcInterruptDisable = USBH_HcInterruptDisable_SF_Msk; + remove_ed(); + _ohci->HcInterruptStatus = USBH_HcInterruptStatus_SF_Msk; + } + + if (int_sts & USBH_HcInterruptStatus_WDH_Msk) + { + //printf("!%02x\n", _ohci->HcFmNumber & 0xff); + int_sts &= ~USBH_HcInterruptStatus_WDH_Msk; + /* + * reverse done list + */ + td = (TD_T *)(_hcca.done_head & TD_ADDR_MASK); + _hcca.done_head = 0; + td_prev = NULL; + _ohci->HcInterruptStatus = USBH_HcInterruptStatus_WDH_Msk; + + while (td != NULL) + { + //TD_debug("Done list TD 0x%x => 0x%x\n", (int)td, (int)td->NextTD); + td_next = (TD_T *)(td->NextTD & TD_ADDR_MASK); + td->NextTD = (uint32_t)td_prev; + td_prev = td; + td = td_next; + } + td = td_prev; /* first TD of the reversed done list */ + + /* + * reclaim TDs + */ + while (td != NULL) + { + TD_debug("Reclaim TD 0x%x, next 0x%x\n", (int)td, td->NextTD); + td_next = (TD_T *)td->NextTD; + td_done(td); + free_ohci_TD(td); + td = td_next; + } + } + + if (int_sts & USBH_HcInterruptStatus_RHSC_Msk) + { + _ohci->HcInterruptDisable = USBH_HcInterruptDisable_RHSC_Msk; + } + + _ohci->HcInterruptStatus = int_sts; +} + +#ifdef ENABLE_DEBUG_MSG + +void dump_ohci_int_table() +{ + int i; + ED_T *ed; + + for (i = 0; i < 32; i++) +// for (i = 0; i < 1; i++) + + { + USB_debug("%02d: ", i); + + ed = (ED_T *)_hcca.int_table[i]; + + while (ed != NULL) + { + USB_debug("0x%x (0x%x) => ", (int)ed, ed->HeadP); + ed = (ED_T *)ed->NextED; + } + rt_kprintf("0\n"); + } +} + +void dump_ohci_regs() +{ + USB_debug("Dump OCHI registers:\n"); + USB_debug(" HcRevision = 0x%x\n", _ohci->HcRevision); + USB_debug(" HcControl = 0x%x\n", _ohci->HcControl); + USB_debug(" HcCommandStatus = 0x%x\n", _ohci->HcCommandStatus); + USB_debug(" HcInterruptStatus = 0x%x\n", _ohci->HcInterruptStatus); + USB_debug(" HcInterruptEnable = 0x%x\n", _ohci->HcInterruptEnable); + USB_debug(" HcInterruptDisable = 0x%x\n", _ohci->HcInterruptDisable); + USB_debug(" HcHCCA = 0x%x\n", _ohci->HcHCCA); + USB_debug(" HcPeriodCurrentED = 0x%x\n", _ohci->HcPeriodCurrentED); + USB_debug(" HcControlHeadED = 0x%x\n", _ohci->HcControlHeadED); + USB_debug(" HcControlCurrentED = 0x%x\n", _ohci->HcControlCurrentED); + USB_debug(" HcBulkHeadED = 0x%x\n", _ohci->HcBulkHeadED); + USB_debug(" HcBulkCurrentED = 0x%x\n", _ohci->HcBulkCurrentED); + USB_debug(" HcDoneHead = 0x%x\n", _ohci->HcDoneHead); + USB_debug(" HcFmInterval = 0x%x\n", _ohci->HcFmInterval); + USB_debug(" HcFmRemaining = 0x%x\n", _ohci->HcFmRemaining); + USB_debug(" HcFmNumber = 0x%x\n", _ohci->HcFmNumber); + USB_debug(" HcPeriodicStart = 0x%x\n", _ohci->HcPeriodicStart); + USB_debug(" HcLSThreshold = 0x%x\n", _ohci->HcLSThreshold); + USB_debug(" HcRhDescriptorA = 0x%x\n", _ohci->HcRhDescriptorA); + USB_debug(" HcRhDescriptorB = 0x%x\n", _ohci->HcRhDescriptorB); + USB_debug(" HcRhStatus = 0x%x\n", _ohci->HcRhStatus); + USB_debug(" HcRhPortStatus0 = 0x%x\n", _ohci->HcRhPortStatus[0]); + USB_debug(" HcRhPortStatus1 = 0x%x\n", _ohci->HcRhPortStatus[1]); + USB_debug(" HcPhyControl = 0x%x\n", _ohci->HcPhyControl); + USB_debug(" HcMiscControl = 0x%x\n", _ohci->HcMiscControl); +} + +void dump_ohci_ports() +{ + USB_debug("_ohci port0=0x%x, port1=0x%x\n", _ohci->HcRhPortStatus[0], _ohci->HcRhPortStatus[1]); +} + +#endif // ENABLE_DEBUG_MSG + +HC_DRV_T ohci_driver = +{ + ohci_init, /* init */ + ohci_shutdown, /* shutdown */ + ohci_suspend, /* suspend */ + ohci_resume, /* resume */ + ohci_ctrl_xfer, /* ctrl_xfer */ + ohci_bulk_xfer, /* bulk_xfer */ + ohci_int_xfer, /* int_xfer */ + ohci_iso_xfer, /* iso_xfer */ + ohci_quit_xfer, /* quit_xfer */ + ohci_rh_port_reset, /* rthub_port_reset */ + ohci_rh_polling /* rthub_polling */ +}; + +/// @endcond HIDDEN_SYMBOLS + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/m480/USBHostLib/src/usb_core.c b/bsp/nuvoton/libraries/m480/USBHostLib/src/usb_core.c new file mode 100644 index 0000000000000000000000000000000000000000..abfb4891c28c40de984c81b4a57bc396afb00006 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/USBHostLib/src/usb_core.c @@ -0,0 +1,299 @@ +/**************************************************************************//** + * @file usb_core.c + * @version V1.10 + * @brief USB Host library core. + * + * SPDX-License-Identifier: Apache-2.0 + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include +#include + +#include "NuMicro.h" + +#include "usb.h" +#include "hub.h" + +/// @cond HIDDEN_SYMBOLS + +USBH_T *_ohci; +HSUSBH_T *_ehci; + +static UDEV_DRV_T * _drivers[MAX_UDEV_DRIVER]; +static CONN_FUNC *g_conn_func, *g_disconn_func; + +/** + * @brief Initialize M480 USB Host controller and USB stack. + * + * @return None. + */ +void usbh_core_init() +{ + NVIC_DisableIRQ(HSUSBH_IRQn); + NVIC_DisableIRQ(USBH_IRQn); + + _ohci = USBH; + _ehci = HSUSBH; + + memset(_drivers, 0, sizeof(_drivers)); + + g_conn_func = NULL; + g_disconn_func = NULL; + +// usbh_hub_init(); + + if ((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x0) /* Only M480MD has EHCI. */ + { + _ehci->USBPCR0 = 0x160; /* enable PHY 0 */ + _ehci->USBPCR1 = 0x520; /* enable PHY 1 */ + } + + usbh_memory_init(); + + _ohci->HcMiscControl |= USBH_HcMiscControl_OCAL_Msk; /* Over-current active low */ + //_ohci->HcMiscControl &= ~USBH_HcMiscControl_OCAL_Msk; /* Over-current active high */ + +#ifdef ENABLE_OHCI + ohci_driver.init(); + ENABLE_OHCI_IRQ(); +#endif + +#ifdef ENABLE_EHCI + if ((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x0) /* Only M480MD has EHCI. */ + { + ehci_driver.init(); + ENABLE_EHCI_IRQ(); + } +#endif +} + +/** + * @brief Let USB stack polls all root hubs. If there's any hub port + * change found, USB stack will manage the hub events in this function call. + * In this function, USB stack enumerates newly connected devices and remove staff + * of disconnected devices. User's application should periodically invoke this + * function. + * @return There's hub port change or not. + * @retval 0 No any hub port status changes found. + * @retval 1 There's hub port status changes. + */ +int usbh_pooling_root_hubs(void) +{ + int ret, change = 0; + +#ifdef ENABLE_EHCI + if ((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x0) /* Only M480MD has EHCI. */ + { + _ehci->UPSCR[1] = HSUSBH_UPSCR_PP_Msk | HSUSBH_UPSCR_PO_Msk; /* set port 2 owner to OHCI */ + do + { + ret = ehci_driver.rthub_polling(); + if (ret) + change = 1; + } + while (ret == 1); + } +#endif + +#ifdef ENABLE_OHCI + do + { + ret = ohci_driver.rthub_polling(); + if (ret) + change = 1; + } + while (ret == 1); +#endif + + return change; +} + +/** + * @brief Force to quit an endpoint transfer. + * @param[in] udev The USB device. + * @param[in] ep The endpoint to be quit. + * @retval 0 Transfer success + * @retval < 0 Failed. Refer to error code definitions. + */ +int usbh_quit_xfer(UDEV_T *udev, EP_INFO_T *ep) +{ + return udev->hc_driver->quit_xfer(NULL, ep); +} + + +int usbh_connect_device(UDEV_T *udev) +{ + usbh_delay_ms(100); /* initially, give 100 ms delay */ + + if (g_conn_func) + g_conn_func(udev, 0); + + return 0; +} + + +void usbh_disconnect_device(UDEV_T *udev) +{ + USB_debug("disconnect device...\n"); + + if (g_disconn_func) + g_disconn_func(udev, 0); + + +#if 1 //CHECK: Maybe create a new API to quit_xfer and free udev for application + usbh_quit_xfer(udev, &(udev->ep0)); /* Quit control transfer if hw_pipe is not NULL. */ + + /* remove device from global device list */ +// free_dev_address(udev->dev_num); + free_device(udev); + +// usbh_memory_used(); +#endif +} + +/** + * @brief Install device connect and disconnect callback function. + * + * @param[in] conn_func Device connect callback function. + * @param[in] disconn_func Device disconnect callback function. + * @return None. + */ +void usbh_install_conn_callback(CONN_FUNC *conn_func, CONN_FUNC *disconn_func) +{ + g_conn_func = conn_func; + g_disconn_func = disconn_func; +} + +int usbh_reset_port(UDEV_T *udev) +{ + if (udev->parent == NULL) + { + if (udev->hc_driver) + return udev->hc_driver->rthub_port_reset(udev->port_num-1); + else + return USBH_ERR_NOT_FOUND; + } + else + { + return udev->parent->port_reset(udev->parent, udev->port_num); + } +} + + +/** + * @brief Force to quit an UTR transfer. + * @param[in] utr The UTR transfer to be quit. + * @retval 0 Transfer success + * @retval < 0 Failed. Refer to error code definitions. + */ +int usbh_quit_utr(UTR_T *utr) +{ + if (!utr || !utr->udev) + return USBH_ERR_NOT_FOUND; + + return utr->udev->hc_driver->quit_xfer(utr, NULL); +} + + +/** + * @brief Execute an USB request in control transfer. This function returns after the request + * was done or aborted. + * @param[in] udev The target USB device. + * @param[in] bmRequestType Characteristics of request + * @param[in] bRequest Specific request + * @param[in] wValue Word-sized field that varies according to request + * @param[in] wIndex Word-sized field that varies according to request + * @param[in] wLength Number of bytes to transfer if there is a Data stage + * @param[in] buff Data buffer used in data stage + * @param[out] xfer_len Transmitted/received length of data + * @param[in] timeout Time-out limit (in 10ms - timer tick) of this transfer + * @retval 0 Transfer success + * @retval < 0 Transfer failed. Refer to error code definitions. + */ +int usbh_ctrl_xfer(UDEV_T *udev, uint8_t bmRequestType, uint8_t bRequest, uint16_t wValue, uint16_t wIndex, + uint16_t wLength, uint8_t *buff, uint32_t *xfer_len, uint32_t timeout) +{ + UTR_T *utr; + uint32_t t0, timeout_tick; + int status; + + *xfer_len = 0; + + //if (check_device(udev)) + // return USBH_ERR_INVALID_PARAM; + + utr = alloc_utr(udev); + if (utr == NULL) + return USBH_ERR_MEMORY_OUT; + + utr->setup.bmRequestType = bmRequestType; + utr->setup.bRequest = bRequest; + utr->setup.wValue = wValue; + utr->setup.wIndex = wIndex; + utr->setup.wLength = wLength; + + utr->buff = buff; + utr->data_len = wLength; + utr->bIsTransferDone = 0; + status = udev->hc_driver->ctrl_xfer(utr); + if (status < 0) + { + udev->ep0.hw_pipe = NULL; + free_utr(utr); + return status; + } + + timeout_tick = usbh_tick_from_millisecond(timeout); + t0 = usbh_get_ticks(); + while (utr->bIsTransferDone == 0) + { + if (usbh_get_ticks() - t0 > timeout_tick) + { + usbh_quit_utr(utr); + free_utr(utr); + udev->ep0.hw_pipe = NULL; + return USBH_ERR_TIMEOUT; + } + } + + status = utr->status; + + if (status == 0) + { + *xfer_len = utr->xfer_len; + } + free_utr(utr); + + return status; +} + +/** + * @brief Execute a bulk transfer request. This function will return immediately after + * issued the bulk transfer. USB stack will later call back utr->func() once the bulk + * transfer was done or aborted. + * @param[in] utr The bulk transfer request. + * @retval 0 Transfer success + * @retval < 0 Failed. Refer to error code definitions. + */ +int usbh_bulk_xfer(UTR_T *utr) +{ + return utr->udev->hc_driver->bulk_xfer(utr); +} + +/** + * @brief Execute an interrupt transfer request. This function will return immediately after + * issued the interrupt transfer. USB stack will later call back utr->func() once the + * interrupt transfer was done or aborted. + * @param[in] utr The interrupt transfer request. + * @retval 0 Transfer success + * @retval < 0 Failed. Refer to error code definitions. + */ +int usbh_int_xfer(UTR_T *utr) +{ + return utr->udev->hc_driver->int_xfer(utr); +} + + diff --git a/bsp/nuvoton/libraries/m480/rtt_port/Kconfig b/bsp/nuvoton/libraries/m480/rtt_port/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..262776534d3d6a067fecd09704fd56b451fe7726 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/Kconfig @@ -0,0 +1,937 @@ +config SOC_SERIES_M480 + bool + select ARCH_ARM_CORTEX_M4 + select SOC_FAMILY_NUMICRO + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + + config BSP_USE_STDDRIVER_SOURCE + bool "Build StdDriver source" + default n + + menuconfig BSP_USING_PDMA + bool "Enable Peripheral Direct Memory Access Controller(PDMA)" + default y + + if BSP_USING_PDMA + config NU_PDMA_MEMFUN_ACTOR_MAX + int "Specify maximum mem actor for memfun" + range 1 4 + default 4 + + config NU_PDMA_SGTBL_POOL_SIZE + int "Specify maximum scatter-gather pool size" + range 1 32 + default 16 + endif + + config BSP_USING_FMC + bool "Enable Flash Memory Controller(FMC)" + select PKG_USING_FAL + default n + + config BSP_USING_GPIO + bool "Enable General Purpose I/O(GPIO)" + select RT_USING_PIN + default y + + menuconfig BSP_USING_CLK + bool "Enable Clock Controller(CLK)" + select RT_USING_PM + select BSP_USING_TMR + default y + help + Choose this option if you need CLK/PM function. + Notice: Enable the option will hold timer3 resource + + if BSP_USING_CLK + config NU_CLK_INVOKE_WKTMR + bool "Enable SPD1 and DPD mode wakeup timer. (About 6.6 Secs)" + default y + endif + + menuconfig BSP_USING_EMAC + bool "Enable Ethernet MAC Controller(EMAC)" + select RT_USING_LWIP + select RT_USING_NETDEV + + config NU_EMAC_PDMA_MEMCOPY + bool "Use PDMA for data tranferring" + select BSP_USING_PDMA + depends on BSP_USING_EMAC + default y + + config NU_EMAC_PDMA_MEMCOPY_THRESHOLD + int "Min threshold to do PDMA memcpy" + range 32 1500 + default 128 + depends on NU_EMAC_PDMA_MEMCOPY + + menuconfig BSP_USING_RTC + bool "Enable Real Time Clock(RTC)" + select RT_USING_RTC + + config NU_RTC_SUPPORT_IO_RW + bool "Support device RW entry" + depends on BSP_USING_RTC && RT_USING_RTC + + config NU_RTC_SUPPORT_MSH_CMD + bool "Support module shell command" + depends on BSP_USING_RTC && RT_USING_RTC + + menuconfig BSP_USING_EADC + bool "Enable Enhanced Analog-to-Digital Converter(EADC)" + + config BSP_USING_EADC0 + bool "Enable EADC0" + depends on BSP_USING_EADC && RT_USING_ADC + + config BSP_USING_EADC1 + bool "Enable EADC1" + depends on BSP_USING_EADC && RT_USING_ADC + + menuconfig BSP_USING_TMR + bool "Enable Timer Controller(TIMER)" + + config BSP_USING_TIMER + bool + + config BSP_USING_TPWM + bool + + config BSP_USING_TIMER_CAPTURE + bool + + config BSP_USING_TMR0 + bool "Enable TIMER0" + depends on BSP_USING_TMR + + if BSP_USING_TMR0 + choice + prompt "Select TIMER0 function mode" + + config BSP_USING_TIMER0 + select BSP_USING_TIMER + select RT_USING_HWTIMER + bool "TIMER" + help + Choose this option if you need TIMER function mode. + + config BSP_USING_TPWM0 + select BSP_USING_TPWM + select RT_USING_PWM + bool "TIMER PWM" + help + Choose this option if you need PWM function mode. + + config BSP_USING_TIMER0_CAPTURE + select BSP_USING_TIMER_CAPTURE + select RT_USING_INPUT_CAPTURE + bool "TIMER CAPTURE" + help + Choose this option if you need CAPTURE function mode. + + endchoice + endif + + config BSP_USING_TMR1 + bool "Enable TIMER1" + depends on BSP_USING_TMR + + if BSP_USING_TMR1 + choice + prompt "Select TIMER1 function mode" + + config BSP_USING_TIMER1 + select BSP_USING_TIMER + select RT_USING_HWTIMER + bool "TIMER" + help + Choose this option if you need TIMER function mode. + + config BSP_USING_TPWM1 + select BSP_USING_TPWM + select RT_USING_PWM + bool "TIMER PWM" + help + Choose this option if you need PWM function mode. + + config BSP_USING_TIMER1_CAPTURE + select BSP_USING_TIMER_CAPTURE + select RT_USING_INPUT_CAPTURE + bool "TIMER CAPTURE" + help + Choose this option if you need CAPTURE function mode. + endchoice + endif + + config BSP_USING_TMR2 + bool "Enable TIMER2" + depends on BSP_USING_TMR + + if BSP_USING_TMR2 + choice + prompt "Select TIMER2 function mode" + + config BSP_USING_TIMER2 + select BSP_USING_TIMER + select RT_USING_HWTIMER + bool "TIMER" + help + Choose this option if you need TIMER function mode. + + config BSP_USING_TPWM2 + select BSP_USING_TPWM + select RT_USING_PWM + bool "TIMER PWM" + help + Choose this option if you need PWM function mode. + + config BSP_USING_TIMER2_CAPTURE + select BSP_USING_TIMER_CAPTURE + select RT_USING_INPUT_CAPTURE + bool "TIMER CAPTURE" + help + Choose this option if you need CAPTURE function mode. + endchoice + endif + + config BSP_USING_TMR3 + bool "Enable TIMER3" + depends on BSP_USING_TMR && !BSP_USING_CLK + + if BSP_USING_TMR3 + choice + prompt "Select TIMER3 function mode" + + config BSP_USING_TIMER3 + select BSP_USING_TIMER + select RT_USING_HWTIMER + bool "TIMER" + help + Choose this option if you need TIMER function mode. + + config BSP_USING_TPWM3 + select BSP_USING_TPWM + select RT_USING_PWM + bool "TIMER PWM" + help + Choose this option if you need PWM function mode. + + config BSP_USING_TIMER3_CAPTURE + select BSP_USING_TIMER_CAPTURE + select RT_USING_INPUT_CAPTURE + bool "TIMER CAPTURE" + help + Choose this option if you need CAPTURE function mode. + endchoice + endif + + menuconfig BSP_USING_UART + bool "Enable Universal Asynchronous Receiver/Transmitters(UART)" + select RT_USING_SERIAL + + if BSP_USING_UART + config BSP_USING_UART0 + bool "Enable UART0" + + config BSP_USING_UART0_TX_DMA + bool "Enable UART0 TX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + + config BSP_USING_UART0_RX_DMA + bool "Enable UART0 RX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + + config BSP_USING_UART1 + bool "Enable UART1" + + config BSP_USING_UART1_TX_DMA + bool "Enable UART1 TX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + + config BSP_USING_UART1_RX_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + + config BSP_USING_UART2 + bool "Enable UART2" + + config BSP_USING_UART2_TX_DMA + bool "Enable UART2 TX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + + config BSP_USING_UART2_RX_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + + config BSP_USING_UART3 + bool "Enable UART3" + + config BSP_USING_UART3_TX_DMA + bool "Enable UART3 TX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + + config BSP_USING_UART3_RX_DMA + bool "Enable UART3 RX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + + config BSP_USING_UART4 + bool "Enable UART4" + + config BSP_USING_UART4_TX_DMA + bool "Enable UART4 TX DMA" + depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + + config BSP_USING_UART4_RX_DMA + bool "Enable UART4 RX DMA" + depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + + config BSP_USING_UART5 + bool "Enable UART5" + + config BSP_USING_UART5_TX_DMA + bool "Enable UART5 TX DMA" + depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA + + config BSP_USING_UART5_RX_DMA + bool "Enable UART5 RX DMA" + depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA + + config BSP_USING_UART6 + bool "Enable UART6" + + config BSP_USING_UART6_TX_DMA + bool "Enable UART6 TX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + + config BSP_USING_UART6_RX_DMA + bool "Enable UART6 RX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + + config BSP_USING_UART7 + bool "Enable UART7" + + config BSP_USING_UART7_TX_DMA + bool "Enable UART7 TX DMA" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + + config BSP_USING_UART7_RX_DMA + bool "Enable UART7 RX DMA" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + endif + + menuconfig BSP_USING_I2C + bool "Enable I2C Serial Interface Controller(I2C)" + select RT_USING_I2C + + if BSP_USING_I2C + config BSP_USING_I2C0 + bool "Enable I2C0" + + config BSP_USING_I2C1 + bool "Enable I2C1" + + config BSP_USING_I2C2 + bool "Enable I2C2" + endif + + menuconfig BSP_USING_USCI + bool "Enable Universal Serial Control Interface Controller(USCI)" + + if BSP_USING_USCI + + config BSP_USING_UUART + bool + + config BSP_USING_USPI + bool + + config BSP_USING_USPI_PDMA + bool + default n + + config BSP_USING_UI2C + bool + + config BSP_USING_USCI0 + bool "Enable USCI0" + + if BSP_USING_USCI0 + choice + prompt "Select USCI0 function mode" + + config BSP_USING_UUART0 + select RT_USING_SERIAL + select BSP_USING_UUART + bool "UUART0" + help + Choose this option if you need UART function mode. + + config BSP_USING_UI2C0 + select RT_USING_I2C + bool "UI2C0" + help + Choose this option if you need I2C function mode. + + config BSP_USING_USPI0 + select RT_USING_SPI + bool "USPI0" + help + Choose this option if you need SPI function mode. + endchoice + + config BSP_USING_UUART0_TX_DMA + bool "Enable UUART0 TX DMA" + depends on BSP_USING_UUART0 && RT_SERIAL_USING_DMA + + config BSP_USING_UUART0_RX_DMA + bool "Enable UUART0 RX DMA" + depends on BSP_USING_UUART0 && RT_SERIAL_USING_DMA + + config BSP_USING_USPI0_PDMA + bool "Use PDMA for data tranferring" + select BSP_USING_USPI_PDMA + depends on BSP_USING_USPI0 + endif + + config BSP_USING_USCI1 + bool "Enable USCI1" + + if BSP_USING_USCI1 + choice + prompt "Select USCI1 function mode" + + config BSP_USING_UUART1 + select RT_USING_SERIAL + select BSP_USING_UUART + bool "UUART1" + help + Choose this option if you need UART function mode. + + config BSP_USING_UI2C1 + select RT_USING_I2C + select BSP_USING_UI2C + bool "UI2C1" + help + Choose this option if you need I2C function mode. + + config BSP_USING_USPI1 + select RT_USING_SPI + select BSP_USING_USPI + bool "USPI1" + help + Choose this option if you need SPI function mode. + endchoice + + config BSP_USING_UUART1_TX_DMA + bool "Enable UUART1 TX DMA" + depends on BSP_USING_UUART1 && RT_SERIAL_USING_DMA + + config BSP_USING_UUART1_RX_DMA + bool "Enable UUART1 RX DMA" + depends on BSP_USING_UUART1 && RT_SERIAL_USING_DMA + + config BSP_USING_USPI1_PDMA + bool "Use PDMA for data tranferring" + select BSP_USING_USPI_PDMA + depends on BSP_USING_USPI1 + endif + + endif + + menuconfig BSP_USING_SDH + bool "Enable Secure Digital Host Controller(SDH)" + select RT_USING_DFS + + if BSP_USING_SDH + config BSP_USING_SDH0 + bool "Enable SDH0" + + config BSP_USING_SDH1 + bool "Enable SDH1" + + config NU_SDH_USING_PDMA + bool "Using PDMA" + select BSP_USING_PDMA + + config NU_SDH_HOTPLUG + bool "Using HOTPLUG" + default y + endif + + menuconfig BSP_USING_CAN + bool "Enable Controller Area Network(CAN)" + select RT_USING_CAN + + if BSP_USING_CAN + config BSP_USING_CAN0 + bool "Enable CAN0" + + config BSP_USING_CAN1 + bool "Enable CAN1" + endif + + menuconfig BSP_USING_BPWM + bool "Enable Basic PWM Generator and Capture Timer(BPWM)" + select RT_USING_PWM + + if BSP_USING_BPWM + + config BSP_USING_BPWM_CAPTURE + bool + + choice + prompt "Select BPWM0 function mode" + config BSP_USING_BPWM0 + select RT_USING_PWM + bool "Enable BPWM0" + help + Choose this option if you need PWM function mode. + + config BSP_USING_BPWM0_CAPTURE + select RT_USING_INPUT_CAPTURE + select BSP_USING_BPWM_CAPTURE + bool "Enable BPWM0_CAPTURE" + help + Choose this option if you need PWM capture function mode. + endchoice + + if BSP_USING_BPWM0_CAPTURE + config BSP_USING_BPWM0_CAPTURE_CHMSK + hex "Specify channel mask for BPWM0_CAP channel." + range 0 0x3F + default 0 + endif + + choice + prompt "Select BPWM1 function mode" + config BSP_USING_BPWM1 + select RT_USING_PWM + bool "Enable BPWM1" + help + Choose this option if you need PWM function mode. + + config BSP_USING_BPWM1_CAPTURE + select RT_USING_INPUT_CAPTURE + select BSP_USING_BPWM_CAPTURE + bool "Enable BPWM1_CAPTURE" + help + Choose this option if you need PWM capture function mode. + endchoice + + if BSP_USING_BPWM1_CAPTURE + config BSP_USING_BPWM1_CAPTURE_CHMSK + hex "Specify channel mask for BPWM1_CAP channel." + range 0 0x3F + default 0 + endif + + endif + + menuconfig BSP_USING_EPWM + bool "Enable EPWM Generator and Capture Timer(EPWM)" + + if BSP_USING_EPWM + + config BSP_USING_EPWM_CAPTURE + bool + + choice + prompt "Select EPWM0 function mode" + config BSP_USING_EPWM0 + select RT_USING_PWM + bool "Enable EPWM0" + help + Choose this option if you need PWM function mode. + + config BSP_USING_EPWM0_CAPTURE + select RT_USING_INPUT_CAPTURE + select BSP_USING_EPWM_CAPTURE + bool "Enable EPWM0_CAPTURE" + help + Choose this option if you need PWM capture function mode. + endchoice + + if BSP_USING_EPWM0_CAPTURE + config BSP_USING_EPWM0_CAPTURE_CHMSK + hex "Specify channel mask for EPWM0_CAP channel." + range 0 0x3F + default 0 + endif + + choice + prompt "Select EPWM1 function mode" + config BSP_USING_EPWM1 + select RT_USING_PWM + bool "Enable EPWM1" + help + Choose this option if you need PWM function mode. + + config BSP_USING_EPWM1_CAPTURE + select RT_USING_INPUT_CAPTURE + select BSP_USING_EPWM_CAPTURE + bool "Enable EPWM1_CAPTURE" + help + Choose this option if you need PWM capture function mode. + endchoice + + if BSP_USING_EPWM1_CAPTURE + config BSP_USING_EPWM1_CAPTURE_CHMSK + hex "Specify channel mask for EPWM1_CAP channel." + range 0 0x3F + default 0 + endif + + endif + + menuconfig BSP_USING_SPI + bool "Enable Serial Peripheral Interface(SPI)" + select RT_USING_SPI + + if BSP_USING_SPI + config BSP_USING_SPI_PDMA + bool + default n + + config BSP_USING_SPII2S + bool + default n + + choice + prompt "Select SPI0 function mode" + config BSP_USING_SPI0_NONE + bool "NONE" + help + Choose this option if you need not SPI0. + + config BSP_USING_SPI0 + bool "Enable SPI0" + help + Choose this option if you need SPI function mode. + + config BSP_USING_SPII2S0 + select RT_USING_AUDIO + select BSP_USING_SPII2S + bool "Enable SPII2S0" + help + Choose this option if you need SPII2S function mode. + endchoice + + if BSP_USING_SPI0 + config BSP_USING_SPI0_PDMA + bool "Enable PDMA for SPI0" + select BSP_USING_SPI_PDMA + depends on BSP_USING_SPI0 + endif + + choice + prompt "Select SPI1 function mode" + config BSP_USING_SPI1_NONE + bool "NONE" + help + Choose this option if you need not SPI1. + + config BSP_USING_SPI1 + bool "Enable SPI1" + help + Choose this option if you need SPI function mode. + + config BSP_USING_SPII2S1 + select RT_USING_AUDIO + select BSP_USING_SPII2S + bool "Enable SPII2S1" + help + Choose this option if you need SPII2S function mode. + endchoice + + if BSP_USING_SPI1 + config BSP_USING_SPI1_PDMA + bool "Enable PDMA for SPI1" + select BSP_USING_SPI_PDMA + depends on BSP_USING_SPI1 + endif + + choice + prompt "Select SPI2 function mode" + config BSP_USING_SPI2_NONE + bool "NONE" + help + Choose this option if you need not SPI2. + + config BSP_USING_SPI2 + bool "Enable SPI2" + help + Choose this option if you need SPI function mode. + + config BSP_USING_SPII2S2 + select RT_USING_AUDIO + select BSP_USING_SPII2S + bool "Enable SPII2S2" + help + Choose this option if you need SPII2S function mode. + endchoice + + if BSP_USING_SPI2 + config BSP_USING_SPI2_PDMA + bool "Enable PDMA for SPI2" + select BSP_USING_SPI_PDMA + depends on BSP_USING_SPI2 + endif + + choice + prompt "Select SPI3 function mode" + config BSP_USING_SPI3_NONE + bool "NONE" + help + Choose this option if you need not SPI3. + + config BSP_USING_SPI3 + bool "Enable SPI3" + help + Choose this option if you need SPI function mode. + + config BSP_USING_SPII2S3 + select RT_USING_AUDIO + select BSP_USING_SPII2S + bool "Enable SPII2S3" + help + Choose this option if you need SPII2S function mode. + endchoice + + if BSP_USING_SPI3 + config BSP_USING_SPI3_PDMA + bool "Enable PDMA for SPI3" + select BSP_USING_SPI_PDMA + depends on BSP_USING_SPI3 + endif + + endif + + config BSP_USING_I2S + bool "Enable I2S Controller(I2S)" + select RT_USING_AUDIO + + if BSP_USING_I2S || BSP_USING_SPII2S + config NU_I2S_DMA_FIFO_SIZE + int "DMA Buffer size of capture and playback" + range 2048 4096 + default 2048 + endif + + menuconfig BSP_USING_QSPI + bool "Enable Quad Serial Peripheral Interface(QSPI)" + select RT_USING_SPI + select RT_USING_QSPI + + if BSP_USING_QSPI + config BSP_USING_QSPI0 + bool "Enable QSPI0" + + config BSP_USING_QSPI0_PDMA + bool "Enable PDMA for QSPI0" + depends on BSP_USING_QSPI0 + + config BSP_USING_QSPI1 + bool "Enable QSPI1" + + config BSP_USING_QSPI1_PDMA + bool "Enable PDMA for QSPI1" + depends on BSP_USING_QSPI1 + endif + + menuconfig BSP_USING_SCUART + bool "Enable Smart Card Host Interface - UART(SCUART)" + + if BSP_USING_SCUART + config BSP_USING_SCUART0 + bool "Enable SCUART0" + + config BSP_USING_SCUART1 + bool "Enable SCUART1" + + config BSP_USING_SCUART2 + bool "Enable SCUART2" + endif + + menuconfig BSP_USING_ECAP + bool "Enable Enhanced Input Capture Timer(ECAP)" + + if BSP_USING_ECAP + + config BSP_USING_ECAP0 + select RT_USING_INPUT_CAPTURE + bool "Enable ECAP0" + help + Choose this option if you need ECAP0. + + if BSP_USING_ECAP0 + config BSP_USING_ECAP0_CHMSK + hex "Specify channel mask for ECAP0 channel." + range 0 0x7 + default 0 + endif + + config BSP_USING_ECAP1 + select RT_USING_INPUT_CAPTURE + bool "Enable ECAP1" + help + Choose this option if you need ECAP1. + + if BSP_USING_ECAP1 + config BSP_USING_ECAP1_CHMSK + hex "Specify channel mask for ECAP1 channel." + range 0 0x7 + default 0 + endif + + endif + + menuconfig BSP_USING_QEI + bool "Enable Quadrature Encoder Interface(QEI)" + + if BSP_USING_QEI + config BSP_USING_QEI0 + bool "Enable QEI0" + select RT_USING_PULSE_ENCODER + + config BSP_USING_QEI1 + bool "Enable QEI1" + select RT_USING_PULSE_ENCODER + endif + + menuconfig BSP_USING_CRYPTO + bool "Enable Cryptographic Accelerator(CRYPTO)" + select RT_USING_HWCRYPTO + select RT_HWCRYPTO_USING_AES + select RT_HWCRYPTO_USING_AES_ECB + select RT_HWCRYPTO_USING_AES_CBC + select RT_HWCRYPTO_USING_AES_CFB + select RT_HWCRYPTO_USING_AES_CTR + select RT_HWCRYPTO_USING_AES_CFB + select RT_HWCRYPTO_USING_AES_OFB + select RT_HWCRYPTO_USING_DES + select RT_HWCRYPTO_USING_DES_ECB + select RT_HWCRYPTO_USING_DES_CBC + select RT_HWCRYPTO_USING_3DES + select RT_HWCRYPTO_USING_3DES_ECB + select RT_HWCRYPTO_USING_3DES_CBC + select RT_HWCRYPTO_USING_SHA1 + select RT_HWCRYPTO_USING_SHA2 + select RT_HWCRYPTO_USING_SHA2_224 + select RT_HWCRYPTO_USING_SHA2_256 + select RT_HWCRYPTO_USING_SHA2_384 + select RT_HWCRYPTO_USING_SHA2_512 + select RT_HWCRYPTO_USING_RNG + + if BSP_USING_CRYPTO + config NU_PRNG_USE_SEED + bool "Use specified seed value." + help + Specify the seed value to PRNG. + + if NU_PRNG_USE_SEED + config NU_PRNG_SEED_VALUE + hex "Enter seed value" + range 0 0xFFFFFFFF + default 0 + endif + endif + + config BSP_USING_TRNG + bool "Enable True Random Number Generator(TRNG)" + select BSP_USING_CRYPTO + select RT_USING_HWCRYPTO + select RT_HWCRYPTO_USING_RNG + + menuconfig BSP_USING_CRC + bool "Enable Cyclic Redundancy Check Generator(CRC)" + select BSP_USING_CRYPTO + select RT_USING_HWCRYPTO + select RT_HWCRYPTO_USING_CRC + select RT_HWCRYPTO_USING_CRC_07 + select RT_HWCRYPTO_USING_CRC_8005 + select RT_HWCRYPTO_USING_CRC_1021 + select RT_HWCRYPTO_USING_CRC_04C11DB7 + + if BSP_USING_CRC + config NU_CRC_USE_PDMA + bool "Use PDMA for data tranferring." + select BSP_USING_PDMA + default y + endif + + + menuconfig BSP_USING_SOFT_I2C + bool "Enable SOFT I2C" + + if BSP_USING_SOFT_I2C + config BSP_USING_SOFT_I2C0 + bool "Enable SOFT I2C0" + select RT_USING_I2C + select RT_USING_I2C_BITOPS + default n + + if BSP_USING_SOFT_I2C0 + config BSP_SOFT_I2C0_SCL_PIN + hex "Specify the pin index of SCL of SOFT I2C0" + range 0 0x7F + default 0x18 + + config BSP_SOFT_I2C0_SDA_PIN + hex "Specify the pin index of SDA of SOFT I2C0" + range 0 0x7F + default 0x17 + endif + + config BSP_USING_SOFT_I2C1 + bool "Enable SOFT I2C1" + select RT_USING_I2C + select RT_USING_I2C_BITOPS + default n + + if BSP_USING_SOFT_I2C1 + config BSP_SOFT_I2C1_SCL_PIN + hex "Specify the pin index of SCL of SOFT I2C1" + range 0 0x7F + default 0x0B + + config BSP_SOFT_I2C1_SDA_PIN + hex "Specify the pin index of SDA of SOFT I2C1" + range 0 0x7F + default 0x0A + endif + endif + + config BSP_USING_WDT + bool "Enable Watchdog Timer(WDT)" + select RT_USING_WDT + default y + + config BSP_USING_EBI + bool "Enable External Bus Interface(EBI)" + default n + + config BSP_USING_USBD + bool "Enable Full-Speed USB Device Controller(USBD)" + select RT_USING_USB_DEVICE + + config BSP_USING_HSUSBD + bool "Enable High-Speed USB Device Controller(HSUSBD)" + select RT_USING_USB_DEVICE + + config BSP_USING_USBH + bool "Enable Full-Speed USB Host Controller(USBH)" + select RT_USING_USB_HOST + select RT_USBH_MSTORAGE + + config BSP_USING_HSUSBH + bool "Enable High-Speed USB Host Controller(HSUSBH)" + select RT_USING_USB_HOST + select RT_USBH_MSTORAGE + + config BSP_USING_HSOTG + bool "Enable High-Speed USB On-The-Go(HSOTG)" + select BSP_USING_HSUSBH + select BSP_USING_HSUSBD diff --git a/bsp/nuvoton/libraries/m480/rtt_port/SConscript b/bsp/nuvoton/libraries/m480/rtt_port/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..a155044a30487ee8290ca112b588dfec32f668ca --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/SConscript @@ -0,0 +1,35 @@ +# RT-Thread building script for component + +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] +group = [] + +# USB driver constrain +if GetDepend('BOARD_USING_HSUSBD') and ( GetDepend('BSP_USING_USBD') or GetDepend('BSP_USING_HSUSBH') or GetDepend('BSP_USING_HSOTG') ): + print 'Sorry, wrong selection.' + print '[Hint] You already select BOARD_USING_HSUSBD. Please de-select BSP_USING_USBD, BSP_USING_HSUSBH and BSP_USING_HSOTG options.' + sys.exit(1) +elif GetDepend('BOARD_USING_HSUSBD_USBH') and ( GetDepend('BSP_USING_USBD') or GetDepend('BSP_USING_HSUSBH') or GetDepend('BSP_USING_HSOTG') ): + print 'Sorry, wrong selection.' + print '[Hint] You already select BOARD_USING_HSUSBD_USBH. Please de-select BSP_USING_USBD, BSP_USING_HSUSBH and BSP_USING_HSOTG options.' + sys.exit(1) +elif GetDepend('BOARD_USING_HSUSBH') and ( GetDepend('BSP_USING_USBH') or GetDepend('BSP_USING_HSUSBD') or GetDepend('BSP_USING_HSOTG') ): + print 'Sorry, wrong selection.' + print '[Hint] You already select BOARD_USING_HSUSBH. Please de-select BSP_USING_USBH, BSP_USING_HSUSBD and BSP_USING_HSOTG options.' + sys.exit(1) +elif GetDepend('BOARD_USING_HSUSBH_USBD') and ( GetDepend('BSP_USING_USBH') or GetDepend('BSP_USING_HSUSBD') or GetDepend('BSP_USING_HSOTG') ): + print 'Sorry, wrong selection.' + print '[Hint] You already select BOARD_USING_HSUSBH_USBD. Please de-select BSP_USING_USBH, BSP_USING_HSUSBD and BSP_USING_HSOTG options.' + sys.exit(1) +elif GetDepend('BOARD_USING_HSOTG') and ( GetDepend('BSP_USING_USBD') or GetDepend('BSP_USING_USBH') ): + print 'Sorry, wrong selection.' + print '[Hint] You already select BOARD_USING_HSOTG. Please de-select BSP_USING_USBD and BSP_USING_USBH options.' + sys.exit(1) +else: + group = DefineGroup('m480_rttport', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_bpwm.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_bpwm.c new file mode 100644 index 0000000000000000000000000000000000000000..14c0b89479f45b5dff8c84dba771367903629818 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_bpwm.c @@ -0,0 +1,228 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-5-22 YHKuo First version +* +******************************************************************************/ + +#include + +#if defined(BSP_USING_BPWM) + +#define LOG_TAG "drv.bpwm" +#define DBG_ENABLE +#define DBG_SECTION_NAME LOG_TAG +#define DBG_LEVEL DBG_INFO +#define DBG_COLOR +#include + +#include +#include +#include +#include "NuMicro.h" + +#define DEFAULT_DUTY 50 +#define DEFAULT_FREQ 1000 + +enum +{ + BPWM_START = -1, +#if defined(BSP_USING_BPWM0) + BPWM0_IDX, +#endif +#if defined(BSP_USING_BPWM1) + BPWM1_IDX, +#endif + BPWM_CNT +}; + +struct nu_bpwm +{ + struct rt_device_pwm dev; + char *name; + BPWM_T *bpwm_base; + rt_int32_t pwm_period_time; +}; + +typedef struct nu_bpwm *nu_bpwm_t; + +static struct nu_bpwm nu_bpwm_arr [] = +{ +#if defined(BSP_USING_BPWM0) + { + .name = "bpwm0", + .bpwm_base = BPWM0, + }, +#endif + +#if defined(BSP_USING_BPWM1) + { + .name = "bpwm1", + .bpwm_base = BPWM1, + }, +#endif + {0} +}; /* bpwm nu_epwm */ + +static rt_err_t nu_bpwm_control(struct rt_device_pwm *device, int cmd, void *arg); + +static struct rt_pwm_ops nu_bpwm_ops = +{ + .control = nu_bpwm_control +}; + +static rt_err_t nu_bpwm_enable(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration, rt_bool_t enable) +{ + rt_err_t result = RT_EOK; + + BPWM_T *pwm_base = ((nu_bpwm_t)device)->bpwm_base; + rt_uint32_t pwm_channel = configuration->channel; + + if (enable == RT_TRUE) + { + BPWM_EnableOutput(pwm_base, 1 << pwm_channel); + BPWM_Start(pwm_base, 1 << pwm_channel); + } + else if (enable == RT_FALSE) + { + BPWM_DisableOutput(pwm_base, 1 << pwm_channel); + BPWM_ForceStop(pwm_base, 1 << pwm_channel); + } + + return result; +} + +static rt_err_t nu_bpwm_set(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration) +{ + if ((configuration->period) <= 0) + return -(RT_ERROR); + rt_uint32_t pwm_freq, pwm_dutycycle; + BPWM_T *pwm_base = ((nu_bpwm_t)device)->bpwm_base; + rt_uint8_t pwm_channel = configuration->channel; + rt_uint32_t pwm_period = configuration->period; + rt_uint32_t pwm_pulse = configuration->pulse; + + pwm_dutycycle = (pwm_pulse * 100) / pwm_period; + + if (BPWM_GET_CNR(pwm_base, pwm_channel) != 0) + { + pwm_period = ((nu_bpwm_t)device)->pwm_period_time; + LOG_I("%s output frequency is determined, user can only change the duty\n", ((nu_bpwm_t)device)->name); + } + else + { + ((nu_bpwm_t)device)->pwm_period_time = pwm_period; + } + + pwm_freq = 1000000000 / pwm_period; + + + BPWM_ConfigOutputChannel(pwm_base, pwm_channel, pwm_freq, pwm_dutycycle) ; + + return RT_EOK; +} + +static rt_uint32_t nu_bpwm_clksr(struct rt_device_pwm *device) +{ + rt_uint32_t u32Src, u32BPWMClockSrc; + BPWM_T *pwm_base = ((nu_bpwm_t)device)->bpwm_base; + if (pwm_base == BPWM0) + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk; + } + else /* (bpwm == BPWM1) */ + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk; + } + + if (u32Src == 0U) + { + /* clock source is from PLL clock */ + u32BPWMClockSrc = CLK_GetPLLClockFreq(); + } + else + { + /* clock source is from PCLK */ + SystemCoreClockUpdate(); + if (pwm_base == BPWM0) + { + u32BPWMClockSrc = CLK_GetPCLK0Freq(); + } + else /* (bpwm == BPWM1) */ + { + u32BPWMClockSrc = CLK_GetPCLK1Freq(); + } + } + return u32BPWMClockSrc; +} + +static rt_err_t nu_bpwm_get(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration) +{ + rt_uint32_t pwm_real_period, pwm_real_duty, time_tick, u32BPWMClockSrc ; + + BPWM_T *pwm_base = ((nu_bpwm_t)device)->bpwm_base; + rt_uint32_t pwm_channel = configuration->channel; + rt_uint32_t pwm_prescale = pwm_base->CLKPSC; + rt_uint32_t pwm_period = BPWM_GET_CNR(pwm_base, pwm_channel); + rt_uint32_t pwm_pulse = BPWM_GET_CMR(pwm_base, pwm_channel); + + u32BPWMClockSrc = nu_bpwm_clksr(device); + time_tick = 1000000000000 / u32BPWMClockSrc; + + pwm_real_period = (((pwm_prescale + 1) * (pwm_period + 1)) * time_tick) / 1000; + pwm_real_duty = (((pwm_prescale + 1) * pwm_pulse * time_tick)) / 1000; + configuration->period = pwm_real_period; + configuration->pulse = pwm_real_duty; + + LOG_I("%s %d %d %d\n", ((nu_bpwm_t)device)->name, configuration->channel, configuration->period, configuration->pulse); + + return RT_EOK; +} + +static rt_err_t nu_bpwm_control(struct rt_device_pwm *device, int cmd, void *arg) +{ + struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(configuration != RT_NULL); + + if (((configuration->channel) + 1) > BPWM_CHANNEL_NUM) + return -(RT_ERROR); + + switch (cmd) + { + case PWM_CMD_ENABLE: + return nu_bpwm_enable(device, configuration, RT_TRUE); + case PWM_CMD_DISABLE: + return nu_bpwm_enable(device, configuration, RT_FALSE); + case PWM_CMD_SET: + return nu_bpwm_set(device, configuration); + case PWM_CMD_GET: + return nu_bpwm_get(device, configuration); + default: + return RT_EINVAL; + } +} + +int rt_hw_bpwm_init(void) +{ + rt_err_t ret; + rt_uint8_t i; + + for (i = (BPWM_START + 1); i < BPWM_CNT; i++) + { + ret = rt_device_pwm_register(&nu_bpwm_arr[i].dev, nu_bpwm_arr[i].name, &nu_bpwm_ops, RT_NULL); + RT_ASSERT(ret == RT_EOK); + } + + return 0; +} + +INIT_DEVICE_EXPORT(rt_hw_bpwm_init); + +#endif diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_bpwm_capture.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_bpwm_capture.c new file mode 100644 index 0000000000000000000000000000000000000000..c7235fe7ae216309bc2d6c837945f07044cf3ae8 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_bpwm_capture.c @@ -0,0 +1,333 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-6-5 Philo First version +* +******************************************************************************/ +#include + +#if defined(BSP_USING_BPWM_CAPTURE) +#include +#include + +/* Private typedef --------------------------------------------------------------*/ +typedef struct _bpwm_dev +{ + BPWM_T *bpwm_base; + IRQn_Type irq; + float fUsPerTick; +} nu_bpwm_dev_t; + +typedef struct _bpwm +{ + struct rt_inputcapture_device parent; + nu_bpwm_dev_t *bpwm_dev; + uint8_t u8Channel; + uint8_t u8DummyData; + uint32_t u32CurrentRisingCnt; + uint32_t u32CurrentFallingCnt; + uint32_t u32LastRisingCnt; + uint32_t u32LastFallingCnt; + rt_bool_t input_data_level; +} nu_capture_t; + +/* Private functions ------------------------------------------------------------*/ +static rt_err_t nu_capture_init(struct rt_inputcapture_device *inputcapture); +static rt_err_t nu_capture_open(struct rt_inputcapture_device *inputcapture); +static rt_err_t nu_capture_close(struct rt_inputcapture_device *inputcapture); +static rt_err_t nu_capture_get_pulsewidth(struct rt_inputcapture_device *inputcapture, rt_uint32_t *pulsewidth_us); + +/* Private define ---------------------------------------------------------------*/ +#define NU_DUMMY_DATA 2 /* First rising and falling edge should be ignore */ + +#define NU_NO_EDGE 0 +#define NU_RISING_EDGE 1 +#define NU_FALLING_EDGE 2 + +/* Public functions -------------------------------------------------------------*/ + + +/* Private variables ------------------------------------------------------------*/ +#if (BSP_USING_BPWM0_CAPTURE_CHMSK!=0) +static const char *nu_bpwm0_device_name[BPWM_CHANNEL_NUM] = { "bpwm0i0", "bpwm0i1", "bpwm0i2", "bpwm0i3", "bpwm0i4", "bpwm0i5"}; +static nu_capture_t *nu_bpwm0_capture[BPWM_CHANNEL_NUM] = {0}; +static nu_bpwm_dev_t nu_bpwm0_dev = {.bpwm_base = BPWM0}; +#endif + +#if (BSP_USING_BPWM1_CAPTURE_CHMSK!=0) +static const char *nu_bpwm1_device_name[BPWM_CHANNEL_NUM] = { "bpwm1i0", "bpwm1i1", "bpwm1i2", "bpwm1i3", "bpwm1i4", "bpwm1i5"}; +static nu_capture_t *nu_bpwm1_capture[BPWM_CHANNEL_NUM] = {0}; +static nu_bpwm_dev_t nu_bpwm1_dev = {.bpwm_base = BPWM1}; +#endif + +static struct rt_inputcapture_ops nu_capture_ops = +{ + .init = nu_capture_init, + .open = nu_capture_open, + .close = nu_capture_close, + .get_pulsewidth = nu_capture_get_pulsewidth, +}; + +/* Functions define ------------------------------------------------------------*/ +void bpwm_interrupt_handler(nu_capture_t *nu_capture[], uint32_t u32ChMsk) +{ + uint32_t u32Status; + + for (uint8_t i = 0; i < BPWM_CHANNEL_NUM ; i++) + { + if ((0x1 << i) & u32ChMsk) + { + if (nu_capture[i]->u8DummyData < NU_DUMMY_DATA) + { + nu_capture[i]->u8DummyData++; + } + else + { + u32Status = BPWM_GetCaptureIntFlag(nu_capture[i]->bpwm_dev->bpwm_base, nu_capture[i]->u8Channel); + + switch (u32Status) + { + case NU_NO_EDGE: + break; + case NU_RISING_EDGE: + BPWM_ClearCaptureIntFlag(nu_capture[i]->bpwm_dev->bpwm_base, nu_capture[i]->u8Channel, BPWM_CAPTURE_INT_RISING_LATCH); + nu_capture[i]->u32CurrentRisingCnt = BPWM_GET_CAPTURE_RISING_DATA(nu_capture[i]->bpwm_dev->bpwm_base, nu_capture[i]->u8Channel); + rt_hw_inputcapture_isr(&nu_capture[i]->parent, nu_capture[i]->input_data_level); + + break; + case NU_FALLING_EDGE: + BPWM_ClearCaptureIntFlag(nu_capture[i]->bpwm_dev->bpwm_base, nu_capture[i]->u8Channel, BPWM_CAPTURE_INT_FALLING_LATCH); + nu_capture[i]->u32CurrentFallingCnt = BPWM_GET_CAPTURE_FALLING_DATA(nu_capture[i]->bpwm_dev->bpwm_base, nu_capture[i]->u8Channel); + rt_hw_inputcapture_isr(&nu_capture[i]->parent, nu_capture[i]->input_data_level); + + break; + default: + BPWM_ClearCaptureIntFlag(nu_capture[i]->bpwm_dev->bpwm_base, nu_capture[i]->u8Channel, BPWM_CAPTURE_INT_RISING_LATCH | BPWM_CAPTURE_INT_FALLING_LATCH); + BPWM_GET_CAPTURE_RISING_DATA(nu_capture[i]->bpwm_dev->bpwm_base, nu_capture[i]->u8Channel); + BPWM_GET_CAPTURE_FALLING_DATA(nu_capture[i]->bpwm_dev->bpwm_base, nu_capture[i]->u8Channel); + + break; + } + } + } + } +} + +#if (BSP_USING_BPWM0_CAPTURE_CHMSK!=0) +void BPWM0_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + bpwm_interrupt_handler(nu_bpwm0_capture, BSP_USING_BPWM0_CAPTURE_CHMSK); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif //(BSP_USING_BPWM0_CAPTURE_CHMSK!=0) + +#if (BSP_USING_BPWM1_CAPTURE_CHMSK!=0) +void BPWM1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + bpwm_interrupt_handler(nu_bpwm1_capture, BSP_USING_BPWM1_CAPTURE_CHMSK); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif //(BSP_USING_BPWM1_CAPTURE_CHMSK!=0) + +static rt_err_t nu_capture_get_pulsewidth(struct rt_inputcapture_device *inputcapture, rt_uint32_t *pulsewidth_us) +{ + rt_err_t ret = RT_EOK; + nu_capture_t *nu_capture; + float fTempCnt; + + nu_capture = (nu_capture_t *)inputcapture; + + if (nu_capture->u32CurrentFallingCnt) + { + if (nu_capture->u32CurrentFallingCnt > nu_capture->u32LastRisingCnt) + fTempCnt = nu_capture->u32CurrentFallingCnt - nu_capture->u32LastRisingCnt; + else /* Overrun case */ + fTempCnt = nu_capture->u32CurrentFallingCnt + (0x10000 - nu_capture->u32LastRisingCnt); + + *pulsewidth_us = fTempCnt * nu_capture->bpwm_dev->fUsPerTick; + nu_capture->input_data_level = RT_FALSE; + nu_capture->u32LastFallingCnt = nu_capture->u32CurrentFallingCnt; + nu_capture->u32CurrentFallingCnt = 0; + } + else if (nu_capture->u32CurrentRisingCnt) + { + if (nu_capture->u32CurrentRisingCnt > nu_capture->u32LastFallingCnt) + fTempCnt = nu_capture->u32CurrentRisingCnt - nu_capture->u32LastFallingCnt; + else /* Overrun case */ + fTempCnt = nu_capture->u32CurrentRisingCnt + (0x10000 - nu_capture->u32LastFallingCnt); + + *pulsewidth_us = fTempCnt * nu_capture->bpwm_dev->fUsPerTick; + nu_capture->input_data_level = RT_TRUE; + nu_capture->u32LastRisingCnt = nu_capture->u32CurrentRisingCnt; + nu_capture->u32CurrentRisingCnt = 0; + } + else + { + ret = RT_ERROR; + } + return -(ret); +} + +static void bpwm_config(nu_capture_t *nu_capture) +{ + /* Set capture time as 500 nano second */ + nu_capture->bpwm_dev->fUsPerTick = (float)BPWM_ConfigCaptureChannel(nu_capture->bpwm_dev->bpwm_base, 0, 500, 0) / 1000; + + /* Enable BPWM NVIC interrupt */ + NVIC_EnableIRQ(nu_capture->bpwm_dev->irq); + + /* Set counter type as up count */ + BPWM_SET_ALIGNED_TYPE(nu_capture->bpwm_dev->bpwm_base, 0, BPWM_UP_COUNTER); + + /* Enable BPWM Timer */ + BPWM_Start(nu_capture->bpwm_dev->bpwm_base, 0); +} + +static rt_err_t nu_bpwm_init(nu_capture_t *nu_capture) +{ + rt_err_t ret = RT_ERROR; + static rt_bool_t bBPWM0Inited = RT_FALSE; + static rt_bool_t bBPWM1Inited = RT_FALSE; + + if (nu_capture->bpwm_dev->bpwm_base == BPWM0) + { + if (bBPWM0Inited == RT_FALSE) + { + /* Enable BPWM0 clock */ + SYS_UnlockReg(); + CLK_EnableModuleClock(BPWM0_MODULE); + CLK_SetModuleClock(BPWM0_MODULE, CLK_CLKSEL2_BPWM0SEL_PLL, (uint32_t)NULL); + SYS_LockReg(); + bpwm_config(nu_capture); + bBPWM0Inited = RT_TRUE; + } + ret = RT_EOK; + } + else if (nu_capture->bpwm_dev->bpwm_base == BPWM1) + { + if (bBPWM1Inited == RT_FALSE) + { + /* Enable BPWM1 clock */ + SYS_UnlockReg(); + CLK_EnableModuleClock(BPWM1_MODULE); + CLK_SetModuleClock(BPWM1_MODULE, CLK_CLKSEL2_BPWM1SEL_PLL, (uint32_t)NULL); + SYS_LockReg(); + bpwm_config(nu_capture); + bBPWM1Inited = RT_TRUE; + } + ret = RT_EOK; + } + + return -(ret); +} + +static rt_err_t nu_capture_init(struct rt_inputcapture_device *inputcapture) +{ + rt_err_t ret = RT_EOK; + nu_capture_t *nu_capture; + + RT_ASSERT(inputcapture != RT_NULL); + + nu_capture = (nu_capture_t *) inputcapture; + + if (nu_bpwm_init(nu_capture) != RT_EOK) + { + rt_kprintf("Failed to initialize BPWM.\n"); + ret = RT_ERROR; + } + + return -(ret); +} + +static rt_err_t nu_capture_open(struct rt_inputcapture_device *inputcapture) +{ + nu_capture_t *nu_capture; + + RT_ASSERT(inputcapture != RT_NULL); + + nu_capture = (nu_capture_t *) inputcapture; + + /* Enable capture rising/falling edge interrupt */ + BPWM_EnableCaptureInt(nu_capture->bpwm_dev->bpwm_base, nu_capture->u8Channel, BPWM_CAPTURE_INT_FALLING_LATCH | BPWM_CAPTURE_INT_RISING_LATCH); + + /* Enable Capture Function for BPWM */ + BPWM_EnableCapture(nu_capture->bpwm_dev->bpwm_base, 0x1 << nu_capture->u8Channel); + + return RT_EOK; +} + +static rt_err_t nu_capture_close(struct rt_inputcapture_device *inputcapture) +{ + nu_capture_t *nu_capture; + + RT_ASSERT(inputcapture != RT_NULL); + + nu_capture = (nu_capture_t *) inputcapture; + + /* Enable Capture Function for BPWM */ + BPWM_DisableCapture(nu_capture->bpwm_dev->bpwm_base, 0x1 << nu_capture->u8Channel); + + /* Disable capture rising/falling edge interrupt */ + BPWM_DisableCaptureInt(nu_capture->bpwm_dev->bpwm_base, nu_capture->u8Channel, BPWM_CAPTURE_INT_FALLING_LATCH | BPWM_CAPTURE_INT_RISING_LATCH); + + return RT_EOK; +} + +static void bpwm_init(nu_capture_t *nu_capture, uint8_t u8Channel, nu_bpwm_dev_t *bpwm_dev, const char *device_name, IRQn_Type irq) +{ + nu_capture->bpwm_dev = bpwm_dev; + nu_capture->bpwm_dev->irq = irq; + nu_capture->u8Channel = u8Channel; + nu_capture->u8DummyData = 0; + nu_capture->u32CurrentFallingCnt = 0; + nu_capture->u32CurrentRisingCnt = 0; + nu_capture->u32LastRisingCnt = 0; + nu_capture->u32LastFallingCnt = 0; + nu_capture->parent.ops = &nu_capture_ops; + + /* register inputcapture device */ + rt_device_inputcapture_register(&nu_capture->parent, device_name, &nu_capture); +} + +/* Init and register bpwm capture */ +static int nu_bpwm_capture_device_init(void) +{ + for (int i = 0; i < BPWM_CHANNEL_NUM; i++) + { +#if (BSP_USING_BPWM0_CAPTURE_CHMSK!=0) + if (BSP_USING_BPWM0_CAPTURE_CHMSK & (0x1 << i)) + { + nu_bpwm0_capture[i] = (nu_capture_t *)rt_malloc(sizeof(nu_capture_t)); + bpwm_init(nu_bpwm0_capture[i], i, &nu_bpwm0_dev, nu_bpwm0_device_name[i], BPWM0_IRQn); + } +#endif //#if (BSP_USING_BPWM0_CAPTURE_CHMSK!=0) + +#if (BSP_USING_BPWM1_CAPTURE_CHMSK!=0) + if (BSP_USING_BPWM1_CAPTURE_CHMSK & (0x1 << i)) + { + nu_bpwm1_capture[i] = (nu_capture_t *)rt_malloc(sizeof(nu_capture_t)); + bpwm_init(nu_bpwm1_capture[i], i, &nu_bpwm1_dev, nu_bpwm1_device_name[i], BPWM1_IRQn); + } +#endif //#if (BSP_USING_BPWM1_CAPTURE_CHMSK!=0) + } + + return 0; +} +INIT_DEVICE_EXPORT(nu_bpwm_capture_device_init); + +#endif //#if defined(BSP_USING_BPWM_CAPTURE) diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_can.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_can.c new file mode 100644 index 0000000000000000000000000000000000000000..f9cc4a973838072bc012772c82c3f06980dd4ffe --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_can.c @@ -0,0 +1,564 @@ +/**************************************************************************//** +* +* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-2-07 ChingI First version +* +******************************************************************************/ + +#include + +#if defined(BSP_USING_CAN) + +#include +#include +#include + +/* Private Define ---------------------------------------------------------------*/ +#define RX_MSG_ID_INDEX 16 +#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU) +#define IS_CAN_DLC(DLC) ((DLC) <= 8U) + +/* Default config for serial_configure structure */ +#define NU_CAN_CONFIG_DEFAULT \ +{ \ + CAN1MBaud, /* 1M bits/s */ \ + RT_CANMSG_BOX_SZ, /* message box max size */ \ + RT_CANSND_BOX_NUM, /* message box number */ \ + RT_CAN_MODE_NORMAL, /* Normal mode */ \ + 0, /* privmode */ \ + 0, /* reserved */ \ + 100, /* Timeout Tick */ \ +} + +enum +{ + CAN_START = -1, +#if defined(BSP_USING_CAN0) + CAN0_IDX, +#endif +#if defined(BSP_USING_CAN1) + CAN1_IDX, +#endif +#if defined(BSP_USING_CAN2) + CAN2_IDX, +#endif + CAN_CNT +}; + +/* Private Typedef --------------------------------------------------------------*/ +struct nu_can +{ + struct rt_can_device dev; + char *name; + CAN_T *can_base; + uint32_t can_rst; + IRQn_Type can_irq_n; +}; +typedef struct nu_can *nu_can_t; + +/* Private functions ------------------------------------------------------------*/ +static rt_err_t nu_can_configure(struct rt_can_device *can, struct can_configure *cfg); +static rt_err_t nu_can_control(struct rt_can_device *can, int cmd, void *arg); +static int nu_can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t boxno); +static int nu_can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxno); +static void nu_can_isr(nu_can_t can); + +static struct nu_can nu_can_arr[] = +{ +#if defined(BSP_USING_CAN0) + { + .name = "can0", + .can_base = CAN0, + .can_rst = CAN0_RST, + .can_irq_n = CAN0_IRQn, + }, +#endif +#if defined(BSP_USING_CAN1) + { + .name = "can1", + .can_base = CAN1, + .can_rst = CAN1_RST, + .can_irq_n = CAN1_IRQn, + }, +#endif + +#if defined(BSP_USING_CAN2) + { + .name = "can2", + .can_base = CAN2, + .can_rst = CAN2_RST, + .can_irq_n = CAN2_IRQn, + }, +#endif + {0} +}; /* usart nu_usart */ + +/* Public functions ------------------------------------------------------------*/ + +/* Private variables ------------------------------------------------------------*/ +static const struct rt_can_ops nu_can_ops = +{ + .configure = nu_can_configure, + .control = nu_can_control, + .sendmsg = nu_can_sendmsg, + .recvmsg = nu_can_recvmsg, +}; + +static const struct can_configure nu_can_default_config = NU_CAN_CONFIG_DEFAULT; + +/* Interrupt Handle Funtion ----------------------------------------------------*/ +#if defined(BSP_USING_CAN0) +/* CAN0 interrupt entry */ +void CAN0_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + nu_can_isr(&nu_can_arr[CAN0_IDX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(BSP_USING_CAN1) +/* CAN1 interrupt entry */ +void CAN1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + nu_can_isr(&nu_can_arr[CAN1_IDX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(BSP_USING_CAN2) +/* CAN2 interrupt entry */ +void CAN2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + nu_can_isr(&nu_can_arr[CAN2_IDX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + + +/* Private Variables ------------------------------------------------------------*/ + + +static void nu_can_isr(nu_can_t can) +{ + uint32_t u32IIDRstatus; + /* Get base address of CAN register */ + CAN_T *can_base = ((nu_can_t)can)->can_base; + + /* Get interrupt event */ + u32IIDRstatus = can_base->IIDR; + + if (u32IIDRstatus == 0x00008000) /* Check Status Interrupt Flag (Error status Int and Status change Int) */ + { + /**************************/ + /* Status Change interrupt*/ + /**************************/ + if (can_base->STATUS & CAN_STATUS_RXOK_Msk) + { + +#ifndef RT_CAN_USING_HDR + /* Using as Lisen,Loopback,Loopback+Lisen mode*/ + rt_hw_can_isr(&can->dev, RT_CAN_EVENT_RX_IND); +#endif + can_base->STATUS &= ~CAN_STATUS_RXOK_Msk; /* Clear Rx Ok status*/ + rt_kprintf("RX OK INT\n") ; + } + + if (can_base->STATUS & CAN_STATUS_TXOK_Msk) + { + +#ifndef RT_CAN_USING_HDR + /* Using as Lisen,Loopback,Loopback+Lisen mode*/ + rt_hw_can_isr(&can->dev, RT_CAN_EVENT_TX_DONE); +#endif + can_base->STATUS &= ~CAN_STATUS_TXOK_Msk; /* Clear Tx Ok status*/ + rt_kprintf("TX OK INT\n") ; + } + + /**************************/ + /* Error Status interrupt */ + /**************************/ + if (can_base->STATUS & CAN_STATUS_EWARN_Msk) + { + rt_kprintf("EWARN INT\n") ; + } + + if (can_base->STATUS & CAN_STATUS_BOFF_Msk) + { + rt_kprintf("BOFF INT\n") ; + + /* Do Init to release busoff pin */ + can_base->CON = (CAN_CON_INIT_Msk | CAN_CON_CCE_Msk); + can_base->CON &= (~(CAN_CON_INIT_Msk | CAN_CON_CCE_Msk)); + while (can_base->CON & CAN_CON_INIT_Msk); + } + } +#ifdef RT_CAN_USING_HDR + /*Number of Message Object which caused the interrupt*/ + else if (u32IIDRstatus != 0 && u32IIDRstatus <= 32) + { + rt_kprintf("=> Interrupt Pointer = %d\n", can_base->IIDR - 1); + /*Message RAM 0~15 for CAN Tx using*/ + if (u32IIDRstatus < 16) + rt_hw_can_isr(&can->dev, RT_CAN_EVENT_TX_DONE); + else /*Message RAM 16~31 for CAN Rx using*/ + { + rt_hw_can_isr(&can->dev, (RT_CAN_EVENT_RX_IND | (((can_base->IIDR) - 1) << 8))); + } + CAN_CLR_INT_PENDING_BIT(can_base, ((can_base->IIDR) - 1)); /* Clear Interrupt Pending */ + } +#endif + +} + + +static rt_err_t nu_can_configure(struct rt_can_device *can, struct can_configure *cfg) +{ + + RT_ASSERT(can != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + /* Get base address of uart register */ + CAN_T *can_base = ((nu_can_t)can)->can_base; + + RT_ASSERT(can_base != RT_NULL); + + /* Reset this module */ + SYS_ResetModule(((nu_can_t)can)->can_rst); + + switch (cfg->mode) + { + /* CAN default Normal mode */ + case RT_CAN_MODE_NORMAL: + can->config.mode = CAN_NORMAL_MODE; + break; + case RT_CAN_MODE_LISEN: + can->config.mode = RT_CAN_MODE_LISEN; + break; + case RT_CAN_MODE_LOOPBACK: + can->config.mode = RT_CAN_MODE_LOOPBACK; + break; + case RT_CAN_MODE_LOOPBACKANLISEN: + can->config.mode = RT_CAN_MODE_LOOPBACKANLISEN; + break; + default: + rt_kprintf("Unsupported Operating mode"); + goto exit_nu_can_configure; + } + + /*Set the CAN Bit Rate and Operating mode*/ + if (CAN_Open(can_base, can->config.baud_rate, can->config.mode) < 1) + return -(RT_ERROR); + + + switch (cfg->mode) + { + /* CAN default Normal mode */ + case RT_CAN_MODE_NORMAL: +#ifdef RT_CAN_USING_HDR + CAN_LeaveTestMode(can_base); +#else + CAN_EnterTestMode(can_base, CAN_TEST_BASIC_Msk); +#endif + break; + case RT_CAN_MODE_LISEN: + CAN_EnterTestMode(can_base, CAN_TEST_BASIC_Msk | CAN_TEST_SILENT_Msk); + break; + case RT_CAN_MODE_LOOPBACK: + CAN_EnterTestMode(can_base, CAN_TEST_BASIC_Msk | CAN_TEST_LBACK_Msk); + break; + case RT_CAN_MODE_LOOPBACKANLISEN: + CAN_EnterTestMode(can_base, CAN_TEST_BASIC_Msk | CAN_TEST_SILENT_Msk | CAN_TEST_LBACK_Msk); + break; + default: + rt_kprintf("Unsupported Operating mode"); + goto exit_nu_can_configure; + } + + + return RT_EOK; + +exit_nu_can_configure: + + CAN_Close(can_base); + + return -(RT_ERROR); +} + +static rt_err_t nu_can_control(struct rt_can_device *can, int cmd, void *arg) +{ + rt_uint32_t argval; + +#ifdef RT_CAN_USING_HDR + struct rt_can_filter_config *filter_cfg; +#endif + /* Get base address of uart register */ + CAN_T *can_base = ((nu_can_t)can)->can_base; + + RT_ASSERT(can_base != RT_NULL); + /* Check baudrate */ + RT_ASSERT(can->config.baud_rate != 0); + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + argval = (rt_uint32_t) arg; + if ((argval == RT_DEVICE_FLAG_INT_RX) || (argval == RT_DEVICE_FLAG_INT_TX)) + { + /* Disable NVIC interrupt. */ + NVIC_DisableIRQ(((nu_can_t)can)->can_irq_n); + /* Disable Status Change Interrupt */ + CAN_DisableInt(can_base, CAN_CON_IE_Msk | CAN_CON_SIE_Msk); + + } + else if (argval == RT_DEVICE_CAN_INT_ERR) + { + /* Disable NVIC interrupt. */ + NVIC_DisableIRQ(((nu_can_t)can)->can_irq_n); + /* Disable Error Interrupt */ + CAN_DisableInt(can_base, CAN_CON_EIE_Msk); + } + break; + + case RT_DEVICE_CTRL_SET_INT: + argval = (rt_uint32_t) arg; + if (argval == RT_DEVICE_FLAG_INT_RX || (argval == RT_DEVICE_FLAG_INT_TX)) + { + /* Enable Status Change Interrupt */ + CAN_EnableInt(can_base, CAN_CON_IE_Msk | CAN_CON_SIE_Msk); + NVIC_SetPriority(((nu_can_t)can)->can_irq_n, (1 << __NVIC_PRIO_BITS) - 2); + /* Enable NVIC interrupt. */ + NVIC_EnableIRQ(((nu_can_t)can)->can_irq_n); + + } + else if (argval == RT_DEVICE_CAN_INT_ERR) + { + /* Enable Error Status and Status Change Interrupt */ + CAN_EnableInt(can_base, CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk); + NVIC_SetPriority(((nu_can_t)can)->can_irq_n, (1 << __NVIC_PRIO_BITS) - 2); + /* Enable NVIC interrupt. */ + NVIC_EnableIRQ(((nu_can_t)can)->can_irq_n); + } + break; + + case RT_CAN_CMD_SET_FILTER: +#ifdef RT_CAN_USING_HDR + filter_cfg = (struct rt_can_filter_config *)arg; + + for (int i = 0; i < filter_cfg->count; i++) + { + + /*set the filter message object*/ + if (filter_cfg->items[i].mode == 1) + { + if (CAN_SetRxMsgObjAndMsk(can_base, MSG(i + RX_MSG_ID_INDEX), filter_cfg->items[i].ide, filter_cfg->items[i].id, filter_cfg->items[i].mask, FALSE) == FALSE) + { + return -(RT_ERROR); + } + } + else + + { + /*set the filter message object*/ + if (CAN_SetRxMsgAndMsk(can_base, MSG(i + RX_MSG_ID_INDEX), filter_cfg->items[i].ide, filter_cfg->items[i].id, filter_cfg->items[i].mask) == FALSE) + { + return -(RT_ERROR); + } + } + } +#endif + break; + case RT_CAN_CMD_SET_MODE: + argval = (rt_uint32_t) arg; + if (argval != RT_CAN_MODE_NORMAL && argval != RT_CAN_MODE_LISEN && + argval != RT_CAN_MODE_LOOPBACK && argval != RT_CAN_MODE_LOOPBACKANLISEN) + { + return -(RT_ERROR); + } + if (argval != can->config.mode) + { + can->config.mode = argval; + return nu_can_configure(can, &can->config); + } + break; + case RT_CAN_CMD_SET_BAUD: + argval = (rt_uint32_t) arg; + if (argval != CAN1MBaud && argval != CAN800kBaud && argval != CAN500kBaud && argval != CAN250kBaud && + argval != CAN125kBaud && argval != CAN100kBaud && argval != CAN50kBaud && argval != CAN20kBaud && argval != CAN10kBaud) + { + return -(RT_ERROR); + } + if (argval != can->config.baud_rate) + { + can->config.baud_rate = argval; + return nu_can_configure(can, &can->config); + } + break; + case RT_CAN_CMD_SET_PRIV: + argval = (rt_uint32_t) arg; + if (argval != RT_CAN_MODE_PRIV && argval != RT_CAN_MODE_NOPRIV) + { + return -(RT_ERROR); + } + if (argval != can->config.privmode) + { + can->config.privmode = argval; + return nu_can_configure(can, &can->config); + } + break; + case RT_CAN_CMD_GET_STATUS: + { + rt_uint32_t errtype; + errtype = can_base->ERR; + /*Receive Error Counter*/ + can->status.rcverrcnt = (errtype >> 8); + /*Transmit Error Counter*/ + can->status.snderrcnt = ((errtype >> 24) & 0xFF); + can->status.lasterrtype = CAN_GET_INT_STATUS(can_base) & 0x8000; + /*status error code*/ + can->status.errcode = CAN_GET_INT_STATUS(can_base) & 0x07; + rt_memcpy(arg, &can->status, sizeof(can->status)); + } + break; + } + + return RT_EOK; +} + +static int nu_can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t boxno) +{ + STR_CANMSG_T tMsg; + struct rt_can_msg *pmsg = (struct rt_can_msg *) buf; + /* Get base address of uart register */ + CAN_T *can_base = ((nu_can_t)can)->can_base; + + RT_ASSERT(can_base != RT_NULL); + RT_ASSERT(buf != RT_NULL); + /* Check the parameters */ + RT_ASSERT(IS_CAN_DLC(pmsg->len)); + /* Standard ID (11 bits)*/ + if (pmsg->ide == RT_CAN_STDID) + { + tMsg.IdType = CAN_STD_ID; + RT_ASSERT(IS_CAN_STDID(pmsg->id)) + tMsg.Id = pmsg->id ; + } + else + { + /* Extended ID (29 bits)*/ + tMsg.IdType = CAN_EXT_ID; + RT_ASSERT(IS_CAN_EXTID(pmsg->id)); + tMsg.Id = pmsg->id ; + } + + if (pmsg->rtr == RT_CAN_DTR) + { + /* Data frame */ + tMsg.FrameType = CAN_DATA_FRAME; + } + else + { + /* Remote frame */ + tMsg.FrameType = CAN_REMOTE_FRAME; + } + tMsg.DLC = pmsg->len; + rt_memcpy(tMsg.Data, pmsg->data, pmsg->len); + + if (CAN_Transmit(can_base, MSG(boxno), &tMsg) == FALSE) // Configure Msg RAM and send the Msg in the RAM + { + return -(RT_ERROR); + } + + return RT_EOK; +} +static int nu_can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxno) +{ + STR_CANMSG_T tMsg; + struct rt_can_msg *pmsg = (struct rt_can_msg *) buf; + /* Get base address of uart register */ + CAN_T *can_base = ((nu_can_t)can)->can_base; + + RT_ASSERT(can_base != RT_NULL); + RT_ASSERT(buf != RT_NULL); + + /* get data */ + CAN_Receive(can_base, boxno, &tMsg); + +#ifdef RT_CAN_USING_HDR + /* Hardware filter messages are valid */ + can->hdr->connected = 1; +#endif + + /* Standard ID (11 bits)*/ + if (tMsg.IdType == CAN_STD_ID) + { + pmsg->ide = RT_CAN_STDID; + pmsg->id = tMsg.Id; + } + else /* Extended ID (29 bits)*/ + { + pmsg->ide = RT_CAN_EXTID; + pmsg->id = tMsg.Id; + } + if (tMsg.FrameType == CAN_DATA_FRAME) + { + /* Data frame */ + pmsg->rtr = RT_CAN_DTR; + } + else + { + /* Remote frame */ + pmsg->rtr = RT_CAN_RTR; + } + pmsg->len = tMsg.DLC ; + rt_memcpy(pmsg->data, tMsg.Data, pmsg->len); + + + return RT_EOK; +} + +/** + * Hardware CAN Initialization + */ +static int rt_hw_can_init(void) +{ + int i; + rt_err_t ret = RT_EOK; + + for (i = (CAN_START + 1); i < CAN_CNT; i++) + { + + nu_can_arr[i].dev.ops = &nu_can_ops; + nu_can_arr[i].dev.config = nu_can_default_config; + +#ifdef RT_CAN_USING_HDR + nu_can_arr[i].dev.config.maxhdr = RT_CANMSG_BOX_SZ; +#endif + ret = rt_hw_can_register(&nu_can_arr[i].dev, nu_can_arr[i].name, &nu_can_ops, NULL); + RT_ASSERT(ret == RT_EOK); + } + + return ret; +} +INIT_DEVICE_EXPORT(rt_hw_can_init); +#endif //#if defined(BSP_USING_CAN) diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_clk.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_clk.c new file mode 100644 index 0000000000000000000000000000000000000000..9ed0233bb2f65fe88917f70a25a8e1e8576f11ec --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_clk.c @@ -0,0 +1,329 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-03-25 klcheng First version +* +******************************************************************************/ + +#include + +#if defined(BSP_USING_CLK) + +#include +#include +#include +#include +#include + + +/* Private define ---------------------------------------------------------------*/ + +/* pm run mode speed mapping */ +#define CONFIG_HIGH_SPEED_FREQ (192000000ul) +#define CONFIG_NORMAL_SPEED_FREQ (192000000ul) +#define CONFIG_MEDIMUM_SPEED_FREQ (144000000ul) +#define CONFIG_LOW_SPEED_FREQ (72000000ul) + +/* pm sleep mode mapping */ +#define CONFIG_MODE_LIGHT (CLK_PMUCTL_PDMSEL_FWPD) +#define CONFIG_MODE_DEEP (CLK_PMUCTL_PDMSEL_PD) +#define CONFIG_MODE_STANDBY (CLK_PMUCTL_PDMSEL_SPD1) +#define CONFIG_MODE_SHUTDOWN (CLK_PMUCTL_PDMSEL_DPD) + + +#if defined (NU_CLK_INVOKE_WKTMR) + /* Wake-up timer clock source is OSC10K */ + #define WKTMR_INTERVAL (CLK_PMUCTL_WKTMRIS_65536) +#endif + + +/* Timer module assigned for pm device usage. */ +/* e.g. If TIMERn is reserved for pm, then define the PM_TIMER_USE_INSTANCE + macro to n value (without parentheses). */ +#define PM_TIMER_USE_INSTANCE 3 + + +/* Concatenate */ +#define _CONCAT2_(x, y) x##y +#define _CONCAT3_(x, y, z) x##y##z +#define CONCAT2(x, y) _CONCAT2_(x, y) +#define CONCAT3(x, y, z) _CONCAT3_(x,y,z) + +/* Concatenate the macros of timer instance for driver usage. */ +#define PM_TIMER CONCAT2(TIMER, PM_TIMER_USE_INSTANCE) +#define PM_TMR CONCAT2(TMR, PM_TIMER_USE_INSTANCE) +#define PM_TIMER_MODULE CONCAT2(PM_TMR, _MODULE) +#define PM_TIMER_IRQn CONCAT2(PM_TMR, _IRQn) +#define PM_TIMER_IRQHandler CONCAT2(PM_TMR, _IRQHandler) +#define PM_TIMER_SEL_LXT CONCAT3(CLK_CLKSEL1_, PM_TMR, SEL_LXT) + +/* Private typedef --------------------------------------------------------------*/ + + +/* Private functions ------------------------------------------------------------*/ +static void pm_sleep(struct rt_pm *pm, rt_uint8_t mode); +static void pm_run(struct rt_pm *pm, rt_uint8_t mode); +static void pm_timer_start(struct rt_pm *pm, rt_uint32_t timeout); +static void pm_timer_stop(struct rt_pm *pm); +static rt_tick_t pm_timer_get_tick(struct rt_pm *pm); +static rt_tick_t pm_tick_from_os_tick(rt_tick_t os_tick); +static rt_tick_t os_tick_from_pm_tick(rt_tick_t pm_tick); + +/* Public functions -------------------------------------------------------------*/ +int rt_hw_pm_init(void); + +/* Private variables ------------------------------------------------------------*/ +static struct rt_pm_ops ops = +{ + .sleep = pm_sleep, + .run = pm_run, + .timer_start = pm_timer_start, + .timer_stop = pm_timer_stop, + .timer_get_tick = pm_timer_get_tick, +}; + +struct rt_device pm; + + + +/* pm sleep() entry */ +static void pm_sleep(struct rt_pm *pm, rt_uint8_t mode) +{ + SYS_UnlockReg(); + + switch (mode) + { + /* wake-up source: */ + /* PM_SLEEP_MODE_LIGHT : TIMERn */ + /* PM_SLEEP_MODE_DEEP : TIMERn */ + /* PM_SLEEP_MODE_STANDBY : wake-up timer (optional) */ + /* PM_SLEEP_MODE_SHUTDOWN : wake-up timer (optional) */ + + case PM_SLEEP_MODE_NONE: + case PM_SLEEP_MODE_IDLE: + break; + + case PM_SLEEP_MODE_LIGHT: + + CLK_SetPowerDownMode(CONFIG_MODE_LIGHT); + CLK_PowerDown(); + break; + + case PM_SLEEP_MODE_DEEP: + + CLK_SetPowerDownMode(CONFIG_MODE_DEEP); + CLK_PowerDown(); + break; + + case PM_SLEEP_MODE_STANDBY: + +#if defined (NU_CLK_INVOKE_WKTMR) + + /* Enable wake-up timer with pre-defined interval if it is invoked */ + CLK_SET_WKTMR_INTERVAL(WKTMR_INTERVAL); + CLK_ENABLE_WKTMR(); +#endif + CLK_SetPowerDownMode(CONFIG_MODE_STANDBY); + CLK_PowerDown(); + break; + + case PM_SLEEP_MODE_SHUTDOWN: + +#if defined (NU_CLK_INVOKE_WKTMR) + /* Enable wake-up timer with pre-defined interval if it is invoked */ + CLK_SET_WKTMR_INTERVAL(WKTMR_INTERVAL); + CLK_ENABLE_WKTMR(); +#endif + CLK_SetPowerDownMode(CONFIG_MODE_SHUTDOWN); + CLK_PowerDown(); + break; + + default: + RT_ASSERT(0); + break; + } + + SYS_LockReg(); +} + + +/* pm run() entry */ +static void pm_run(struct rt_pm *pm, rt_uint8_t mode) +{ + static uint8_t prev_mode = RT_PM_DEFAULT_RUN_MODE; + + /* ignore it if power mode is the same. */ + if (mode == prev_mode) + return; + + prev_mode = mode; + + SYS_UnlockReg(); + + /* Switch run mdoe frequency using PLL + HXT if HXT is enabled. + Otherwise, the systme clock will use PLL + HIRC. */ + switch (mode) + { + case PM_RUN_MODE_HIGH_SPEED: + + CLK_SetCoreClock(CONFIG_HIGH_SPEED_FREQ); + break; + + case PM_RUN_MODE_NORMAL_SPEED: + + CLK_SetCoreClock(CONFIG_NORMAL_SPEED_FREQ); + break; + + case PM_RUN_MODE_MEDIUM_SPEED: + + CLK_SetCoreClock(CONFIG_MEDIMUM_SPEED_FREQ); + break; + + case PM_RUN_MODE_LOW_SPEED: + + CLK_SetCoreClock(CONFIG_LOW_SPEED_FREQ); + break; + + default: + RT_ASSERT(0); + break; + } + + SystemCoreClockUpdate(); + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + + SYS_LockReg(); +} + + +static void hw_timer_init(void) +{ + /* Assign a hardware timer for pm usage. */ + SYS_UnlockReg(); + CLK_SetModuleClock(PM_TIMER_MODULE, PM_TIMER_SEL_LXT, MODULE_NoMsk); + CLK_EnableModuleClock(PM_TIMER_MODULE); + SYS_LockReg(); + + /* Initialise timer and enable wakeup function. */ + TIMER_Open(PM_TIMER, TIMER_CONTINUOUS_MODE, 1); + TIMER_SET_PRESCALE_VALUE(PM_TIMER, 0); + TIMER_EnableInt(PM_TIMER); + TIMER_EnableWakeup(PM_TIMER); + NVIC_EnableIRQ(PM_TIMER_IRQn); +} + + +/* convert os tick to pm timer tick */ +static rt_tick_t pm_tick_from_os_tick(rt_tick_t os_tick) +{ + rt_uint32_t hz = TIMER_GetModuleClock(PM_TIMER); + + return (rt_tick_t)(hz * os_tick / RT_TICK_PER_SECOND); +} + + +/* convert pm timer tick to os tick */ +static rt_tick_t os_tick_from_pm_tick(rt_tick_t pm_tick) +{ + static rt_uint32_t os_tick_remain = 0; + rt_uint32_t ret, hz; + + hz = TIMER_GetModuleClock(PM_TIMER); + ret = (pm_tick * RT_TICK_PER_SECOND + os_tick_remain) / hz; + + os_tick_remain += (pm_tick * RT_TICK_PER_SECOND); + os_tick_remain %= hz; + + return ret; +} + + +/* pm_ops timer_get_tick() entry */ +static rt_tick_t pm_timer_get_tick(struct rt_pm *pm) +{ + rt_tick_t tick; + + tick = TIMER_GetCounter(PM_TIMER); + + return os_tick_from_pm_tick(tick); +} + + +/* pm timer_start() entry */ +static void pm_timer_start(struct rt_pm *pm, rt_uint32_t timeout) +{ + int tick; + + if (timeout == RT_TICK_MAX) + return; + + /* start pm timer to compenstate the os tick in power down mode */ + tick = pm_tick_from_os_tick(timeout); + TIMER_SET_CMP_VALUE(PM_TIMER, tick); + TIMER_Start(PM_TIMER); +} + + +/* pm timer_stop() entry */ +static void pm_timer_stop(struct rt_pm *pm) +{ + TIMER_Stop(PM_TIMER); + TIMER_ResetCounter(PM_TIMER); +} + + +/* pm device driver initialise. */ +int rt_hw_pm_init(void) +{ + rt_uint8_t timer_mask; + + if (CLK_GetPMUWKSrc()) + { + /* Release I/O hold status after wake-up from Standby Power-down Mode (SPD) */ + CLK->IOPDCTL = 1; + + /* Clear Power Manager Status register */ + CLK->PMUSTS = CLK_PMUSTS_CLRWK_Msk; + } + + hw_timer_init(); + + /* initialize timer mask */ + timer_mask = (1UL << PM_SLEEP_MODE_LIGHT) | + (1UL << PM_SLEEP_MODE_DEEP); + + /* initialize system pm module */ + rt_system_pm_init(&ops, timer_mask, RT_NULL); + + return RT_EOK; +} +INIT_BOARD_EXPORT(rt_hw_pm_init); + + +/* pm timer interrupt entry */ +void PM_TIMER_IRQHandler(void) +{ + rt_interrupt_enter(); + + if (TIMER_GetIntFlag(PM_TIMER)) + { + TIMER_ClearIntFlag(PM_TIMER); + } + + if (TIMER_GetWakeupFlag(PM_TIMER)) + { + TIMER_ClearWakeupFlag(PM_TIMER); + } + + rt_interrupt_leave(); +} + +#endif /* BSP_USING_CLK */ + + + diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_crc.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_crc.c new file mode 100644 index 0000000000000000000000000000000000000000..50c056730e5b08b06f1e9cb6221acfd61dfd03ec --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_crc.c @@ -0,0 +1,134 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-3-4 CHChen First version +* +******************************************************************************/ + +#include + +#if (defined(BSP_USING_CRC) && defined(RT_HWCRYPTO_USING_CRC)) + +#include + +#include +#include + +#include "NuMicro.h" +#include "drv_pdma.h" + +/* Private define ---------------------------------------------------------------*/ +#define NU_CRYPTO_CRC_NAME "nu_CRC" + +/* Private variables ------------------------------------------------------------*/ + +static struct rt_mutex s_CRC_mutex; + +static rt_uint32_t nu_crc_run( + uint32_t u32OpMode, + uint32_t u32Seed, + uint32_t u32Attr, + uint8_t *pu8InData, + uint32_t u32DataLen +) +{ + uint32_t u32CalChecksum = 0; + uint32_t i = 0; + + rt_mutex_take(&s_CRC_mutex, RT_WAITING_FOREVER); + + /* Configure CRC controller */ + CRC_Open(u32OpMode, u32Attr, u32Seed, CRC_CPU_WDATA_8); + + uint8_t *pu8InTempData = pu8InData; + + while (i < u32DataLen) + { + if (((((uint32_t)pu8InTempData) % 4) != 0) || (u32DataLen - i < 4)) + { + CRC->CTL &= ~CRC_CTL_DATLEN_Msk; + CRC_WRITE_DATA((*pu8InTempData) & 0xFF); + pu8InTempData ++; + i++; + } + else + { + CRC->CTL &= ~CRC_CTL_DATLEN_Msk; + CRC->CTL |= CRC_CPU_WDATA_32; +#if defined (NU_CRC_USE_PDMA) + int32_t i32PDMATransCnt = (u32DataLen - i) / 4 ; + + i32PDMATransCnt = nu_pdma_mempush((void *)&CRC->DAT, pu8InTempData, 32, i32PDMATransCnt); + + if (i32PDMATransCnt > 0) + { + pu8InTempData += (i32PDMATransCnt * 4); + i += (i32PDMATransCnt * 4); + } +#else + CRC_WRITE_DATA(*(uint32_t *)pu8InTempData); + pu8InTempData += 4; + i += 4; +#endif + } + } + + /* Get checksum value */ + u32CalChecksum = CRC_GetChecksum(); + rt_mutex_release(&s_CRC_mutex); + + return u32CalChecksum; +} + + +rt_err_t nu_crc_init(void) +{ + SYS_ResetModule(CRC_RST); + + rt_mutex_init(&s_CRC_mutex, NU_CRYPTO_CRC_NAME, RT_IPC_FLAG_FIFO); + return RT_EOK; +} + +rt_uint32_t nu_crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, rt_size_t length) +{ + uint32_t u32OpMode; + uint32_t u32CRCAttr = 0; + rt_uint32_t crc_result = 0; + + //select CRC operation mode + switch (ctx->crc_cfg.poly) + { + case 0x04C11DB7: + u32OpMode = CRC_32; + break; + case 0x00001021: + u32OpMode = CRC_CCITT; + break; + case 0x00008005: + u32OpMode = CRC_16; + break; + case 0x00000007: + u32OpMode = CRC_8; + break; + default: + return 0; + } + + + u32CRCAttr |= ctx->crc_cfg.flags & CRC_FLAG_REFOUT ? CRC_CHECKSUM_RVS : 0; //CRC Checksum Reverse + u32CRCAttr |= ctx->crc_cfg.flags & CRC_FLAG_REFIN ? CRC_WDATA_RVS : 0; //CRC Write Data Reverse + + //Calcluate CRC checksum, using config's last value as CRC seed + crc_result = nu_crc_run(u32OpMode, ctx->crc_cfg.last_val, u32CRCAttr, (uint8_t *)in, length); + + //update CRC result to config's last vaule + ctx->crc_cfg.last_val = crc_result; + return crc_result ^ 0x00 ^ ctx->crc_cfg.xorout; +} + +#endif //#if (defined(BSP_USING_CRC) && defined(RT_HWCRYPTO_USING_CRC)) diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_crc.h b/bsp/nuvoton/libraries/m480/rtt_port/drv_crc.h new file mode 100644 index 0000000000000000000000000000000000000000..04c2038c07e6d20b71b7c7f5f47443e2f9ca11a3 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_crc.h @@ -0,0 +1,21 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-3-4 CHChen First version +* +******************************************************************************/ + +#ifndef __DRV_CRC_H__ +#define __DRV_CRC_H__ + +rt_err_t nu_crc_init(void); + +rt_uint32_t nu_crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, rt_size_t length); + + +#endif diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_crypto.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_crypto.c new file mode 100644 index 0000000000000000000000000000000000000000..6cc1f0b30932b4292007ab65306cd8a158ca8af9 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_crypto.c @@ -0,0 +1,842 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-3-3 CHChen First version +* 2020-5-3 YCHuang12 Add TDES and SHA +* +******************************************************************************/ + +#include + +#if ((defined(BSP_USING_CRYPTO) || defined(BSP_USING_TRNG) || defined(BSP_USING_CRC)) && defined(RT_USING_HWCRYPTO)) + +#include + +#include +#include +#include "NuMicro.h" +#include + +#if defined(BSP_USING_TRNG) + #include "drv_trng.h" +#endif + +#if defined(BSP_USING_CRC) + #include "drv_crc.h" +#endif + +/* Private typedef --------------------------------------------------------------*/ + +/* Private functions ------------------------------------------------------------*/ +static rt_err_t nu_hwcrypto_create(struct rt_hwcrypto_ctx *ctx); +static void nu_hwcrypto_destroy(struct rt_hwcrypto_ctx *ctx); +static rt_err_t nu_hwcrypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcrypto_ctx *src); +static void nu_hwcrypto_reset(struct rt_hwcrypto_ctx *ctx); + +/* Private variables ------------------------------------------------------------*/ +static const struct rt_hwcrypto_ops nu_hwcrypto_ops = +{ + .create = nu_hwcrypto_create, + .destroy = nu_hwcrypto_destroy, + .copy = nu_hwcrypto_clone, + .reset = nu_hwcrypto_reset, +}; + +/* Crypto engine operation ------------------------------------------------------------*/ +#if defined(BSP_USING_CRYPTO) + +//define NU_HWCRYPTO_NOT_ALIGN_CHECK to disable plain/cipher buffer address alignment checking +//#define NU_HWCRYPTO_NOT_ALIGN_CHECK + +#define NU_HWCRYPTO_DES_3KEYS 1 +#define NU_HWCRYPTO_DES_NO3KEYS 0 +#define NU_HWCRYPTO_AES_NAME "nu_AES" +#define NU_HWCRYPTO_TDES_NAME "nu_TDES" +#define NU_HWCRYPTO_SHA_NAME "nu_SHA" +#if !defined(BSP_USING_TRNG) + #define NU_HWCRYPTO_PRNG_NAME "nu_PRNG" +#endif + +static struct rt_mutex s_AES_mutex; +static struct rt_mutex s_TDES_mutex; +static struct rt_mutex s_SHA_mutex; + +#if !defined(BSP_USING_TRNG) + static struct rt_mutex s_PRNG_mutex; + static volatile int s_PRNG_done; +#endif + +static volatile int s_AES_done; +static volatile int s_TDES_done; +static volatile int s_SHA_done; + +static rt_err_t nu_crypto_init(void) +{ + /* Enable Crypto engine interrupt */ + NVIC_EnableIRQ(CRPT_IRQn); + + AES_ENABLE_INT(CRPT); + TDES_ENABLE_INT(CRPT); + SHA_ENABLE_INT(CRPT); + + //init cipher mutex + rt_mutex_init(&s_AES_mutex, NU_HWCRYPTO_AES_NAME, RT_IPC_FLAG_FIFO); + rt_mutex_init(&s_TDES_mutex, NU_HWCRYPTO_TDES_NAME, RT_IPC_FLAG_FIFO); + rt_mutex_init(&s_SHA_mutex, NU_HWCRYPTO_SHA_NAME, RT_IPC_FLAG_FIFO); +#if !defined(BSP_USING_TRNG) + PRNG_ENABLE_INT(CRPT); + rt_mutex_init(&s_PRNG_mutex, NU_HWCRYPTO_PRNG_NAME, RT_IPC_FLAG_FIFO); +#endif + + return RT_EOK; +} + +//Crypto engine IRQ handler + +void CRYPTO_IRQHandler() +{ + if (AES_GET_INT_FLAG(CRPT)) + { + s_AES_done = 1; + AES_CLR_INT_FLAG(CRPT); + } + + if (TDES_GET_INT_FLAG(CRPT)) + { + s_TDES_done = 1; + TDES_CLR_INT_FLAG(CRPT); + } + + if (SHA_GET_INT_FLAG(CRPT)) + { + s_SHA_done = 1; + SHA_CLR_INT_FLAG(CRPT); + } + +#if !defined(BSP_USING_TRNG) + if (PRNG_GET_INT_FLAG(CRPT)) + { + s_PRNG_done = 1; + PRNG_CLR_INT_FLAG(CRPT); + } +#endif +} + +static rt_err_t nu_aes_crypt_run( + rt_bool_t bEncrypt, + uint32_t u32OpMode, + uint8_t *pu8Key, + uint32_t u32KeySize, + uint8_t *pu8IV, + uint8_t *pu8InData, + uint8_t *pu8OutData, + uint32_t u32DataLen +) +{ + uint32_t au32SwapKey[8]; + uint32_t au32SwapIV[4]; + + au32SwapKey[0] = nu_get32_be(&pu8Key[0]); + au32SwapKey[1] = nu_get32_be(&pu8Key[4]); + au32SwapKey[2] = nu_get32_be(&pu8Key[8]); + au32SwapKey[3] = nu_get32_be(&pu8Key[12]); + + if ((u32KeySize == AES_KEY_SIZE_192) || (u32KeySize == AES_KEY_SIZE_256)) + { + au32SwapKey[4] = nu_get32_be(&pu8Key[16]); + au32SwapKey[5] = nu_get32_be(&pu8Key[20]); + } + + if (u32KeySize == AES_KEY_SIZE_256) + { + au32SwapKey[6] = nu_get32_be(&pu8Key[24]); + au32SwapKey[7] = nu_get32_be(&pu8Key[28]); + } + + au32SwapIV[0] = nu_get32_be(&pu8IV[0]); + au32SwapIV[1] = nu_get32_be(&pu8IV[4]); + au32SwapIV[2] = nu_get32_be(&pu8IV[8]); + au32SwapIV[3] = nu_get32_be(&pu8IV[12]); + + rt_mutex_take(&s_AES_mutex, RT_WAITING_FOREVER); + + //Using Channel 0 + AES_Open(CRPT, 0, bEncrypt, u32OpMode, u32KeySize, AES_IN_OUT_SWAP); + AES_SetKey(CRPT, 0, (uint32_t *)au32SwapKey, u32KeySize); + AES_SetInitVect(CRPT, 0, (uint32_t *)au32SwapIV); + + //Setup AES DMA + AES_SetDMATransfer(CRPT, 0, (uint32_t)pu8InData, (uint32_t)pu8OutData, u32DataLen); + AES_CLR_INT_FLAG(CRPT); + //Start AES encryption/decryption + s_AES_done = 0; + AES_Start(CRPT, 0, CRYPTO_DMA_ONE_SHOT); + while (!s_AES_done) {}; + + rt_mutex_release(&s_AES_mutex); + + return RT_EOK; +} + +#if !defined(BSP_USING_TRNG) +//Using PRNG instead of TRNG +static void nu_prng_open(uint32_t u32Seed) +{ + rt_mutex_take(&s_PRNG_mutex, RT_WAITING_FOREVER); + + //Open PRNG 64 bits. But always return 32 bits + PRNG_Open(CRPT, PRNG_KEY_SIZE_64, PRNG_SEED_RELOAD, u32Seed); + + rt_mutex_release(&s_PRNG_mutex); +} + +static rt_uint32_t nu_prng_run(void) +{ + uint32_t au32RNGValue[2]; + + rt_mutex_take(&s_PRNG_mutex, RT_WAITING_FOREVER); + + s_PRNG_done = 0; + PRNG_Start(CRPT); + while (!s_PRNG_done) {}; + + PRNG_Read(CRPT, au32RNGValue); + + rt_mutex_release(&s_PRNG_mutex); + return au32RNGValue[0]; +} + +#endif + +static rt_err_t nu_aes_crypt(struct hwcrypto_symmetric *symmetric_ctx, struct hwcrypto_symmetric_info *symmetric_info) +{ + uint32_t u32AESOpMode; + uint32_t u32AESKeySize; + unsigned char *in, *out; + + if ((symmetric_info->length % 16) != 0) + { + return -RT_EINVAL; + } + + //Checking key length + if (symmetric_ctx->key_bitlen == 128) + { + u32AESKeySize = AES_KEY_SIZE_128; + } + else if (symmetric_ctx->key_bitlen == 192) + { + u32AESKeySize = AES_KEY_SIZE_192; + } + else if (symmetric_ctx->key_bitlen == 256) + { + u32AESKeySize = AES_KEY_SIZE_256; + } + else + { + return -RT_EINVAL; + } + + //Select AES operation mode + switch (symmetric_ctx->parent.type & (HWCRYPTO_MAIN_TYPE_MASK | HWCRYPTO_SUB_TYPE_MASK)) + { + case HWCRYPTO_TYPE_AES_ECB: + u32AESOpMode = AES_MODE_ECB; + break; + case HWCRYPTO_TYPE_AES_CBC: + u32AESOpMode = AES_MODE_CBC; + break; + case HWCRYPTO_TYPE_AES_CFB: + u32AESOpMode = AES_MODE_CFB; + break; + case HWCRYPTO_TYPE_AES_OFB: + u32AESOpMode = AES_MODE_OFB; + break; + case HWCRYPTO_TYPE_AES_CTR: + u32AESOpMode = AES_MODE_CTR; + break; + default : + return -RT_ERROR; + } + + in = (unsigned char *)symmetric_info->in; + out = (unsigned char *)symmetric_info->out; + +#if !defined(NU_HWCRYPTO_NOT_ALIGN_CHECK) + unsigned char in_align_flag = 0; + unsigned char out_align_flag = 0; + + //Checking in/out data buffer address alignment or not + if (((rt_uint32_t)in % 4) != 0) + { + in = rt_malloc(symmetric_info->length); + if (in == RT_NULL) + { + LOG_E("fun[%s] memory allocate %d bytes failed!", __FUNCTION__, symmetric_info->length); + return -RT_ENOMEM; + } + + memcpy(in, symmetric_info->in, symmetric_info->length); + in_align_flag = 1; + } + + if (((rt_uint32_t)out % 4) != 0) + { + out = rt_malloc(symmetric_info->length); + if (out == RT_NULL) + { + if (in_align_flag) + rt_free(in); + LOG_E("fun[%s] memory allocate %d bytes failed!", __FUNCTION__, symmetric_info->length); + return -RT_ENOMEM; + } + + out_align_flag = 1; + } +#endif + + nu_aes_crypt_run(symmetric_info->mode == HWCRYPTO_MODE_ENCRYPT ? TRUE : FALSE, u32AESOpMode, symmetric_ctx->key, u32AESKeySize, symmetric_ctx->iv, in, out, symmetric_info->length); + +#if !defined(NU_HWCRYPTO_NOT_ALIGN_CHECK) + if (out_align_flag) + { + memcpy(symmetric_info->out, out, symmetric_info->length); + rt_free(out); + } + + if (in_align_flag) + { + rt_free(in); + } +#endif + + return RT_EOK; +} + +static rt_err_t nu_des_crypt_run( + rt_bool_t bEncrypt, + uint32_t u32OpMode, + uint8_t *pu8Key, + uint32_t u32KeySize, + uint8_t *pu8IV, + uint8_t *pu8InData, + uint8_t *pu8OutData, + uint32_t u32DataLen +) +{ + uint32_t au32SwapKey[3][2]; + uint32_t au32SwapIV[2]; + + au32SwapKey[0][0] = nu_get32_be(&pu8Key[0]); + au32SwapKey[0][1] = nu_get32_be(&pu8Key[4]); + au32SwapKey[1][0] = nu_get32_be(&pu8Key[8]); + au32SwapKey[1][1] = nu_get32_be(&pu8Key[12]); + + if (u32KeySize == NU_HWCRYPTO_DES_3KEYS) + { + au32SwapKey[2][0] = nu_get32_be(&pu8Key[16]); + au32SwapKey[2][1] = nu_get32_be(&pu8Key[20]); + } + + au32SwapIV[0] = nu_get32_be(&pu8IV[0]); + au32SwapIV[1] = nu_get32_be(&pu8IV[4]); + + rt_mutex_take(&s_TDES_mutex, RT_WAITING_FOREVER); + + //Using Channel 0 + TDES_Open(CRPT, 0, bEncrypt, (u32OpMode & CRPT_TDES_CTL_TMODE_Msk), u32KeySize, u32OpMode, TDES_IN_OUT_WHL_SWAP); + TDES_SetKey(CRPT, 0, au32SwapKey); + TDES_SetInitVect(CRPT, 0, au32SwapIV[0], au32SwapIV[1]); + + //Setup TDES DMA + TDES_SetDMATransfer(CRPT, 0, (uint32_t)pu8InData, (uint32_t)pu8OutData, u32DataLen); + TDES_CLR_INT_FLAG(CRPT); + //Start TDES encryption/decryption + s_TDES_done = 0; + TDES_Start(CRPT, 0, CRYPTO_DMA_ONE_SHOT); + while (!s_TDES_done) {}; + + rt_mutex_release(&s_TDES_mutex); + + return RT_EOK; +} + +static rt_err_t nu_des_crypt(struct hwcrypto_symmetric *symmetric_ctx, struct hwcrypto_symmetric_info *symmetric_info) +{ + uint32_t u32DESOpMode; + uint32_t u32DESKeySize; + unsigned char *in, *out; + + if ((symmetric_info->length % 8) != 0) + { + return -RT_EINVAL; + } + + //Checking key length + if (symmetric_ctx->key_bitlen == 128 || symmetric_ctx->key_bitlen == 64) + { + u32DESKeySize = NU_HWCRYPTO_DES_NO3KEYS; + } + else if (symmetric_ctx->key_bitlen == 192) + { + u32DESKeySize = NU_HWCRYPTO_DES_3KEYS; + } + else + { + return -RT_EINVAL; + } + + //Select DES operation mode + switch (symmetric_ctx->parent.type & (HWCRYPTO_MAIN_TYPE_MASK | HWCRYPTO_SUB_TYPE_MASK)) + { + case HWCRYPTO_TYPE_DES_ECB: + u32DESOpMode = DES_MODE_ECB; + break; + case HWCRYPTO_TYPE_DES_CBC: + u32DESOpMode = DES_MODE_CBC; + break; + case HWCRYPTO_TYPE_3DES_ECB: + u32DESOpMode = TDES_MODE_ECB; + break; + case HWCRYPTO_TYPE_3DES_CBC: + u32DESOpMode = TDES_MODE_CBC; + break; + default : + return -RT_ERROR; + } + + in = (unsigned char *)symmetric_info->in; + out = (unsigned char *)symmetric_info->out; + +#if !defined(NU_HWCRYPTO_NOT_ALIGN_CHECK) + unsigned char in_align_flag = 0; + unsigned char out_align_flag = 0; + + //Checking in/out data buffer address alignment or not + if (((rt_uint32_t)in % 4) != 0) + { + in = rt_malloc(symmetric_info->length); + if (in == RT_NULL) + { + LOG_E("fun[%s] memory allocate %d bytes failed!", __FUNCTION__, symmetric_info->length); + return -RT_ENOMEM; + } + + memcpy(in, symmetric_info->in, symmetric_info->length); + in_align_flag = 1; + } + + if (((rt_uint32_t)out % 4) != 0) + { + out = rt_malloc(symmetric_info->length); + if (out == RT_NULL) + { + if (in_align_flag) + rt_free(in); + LOG_E("fun[%s] memory allocate %d bytes failed!", __FUNCTION__, symmetric_info->length); + return -RT_ENOMEM; + } + + out_align_flag = 1; + } +#endif + + nu_des_crypt_run(symmetric_info->mode == HWCRYPTO_MODE_ENCRYPT ? TRUE : FALSE, u32DESOpMode, symmetric_ctx->key, u32DESKeySize, symmetric_ctx->iv, in, out, symmetric_info->length); + +#if !defined(NU_HWCRYPTO_NOT_ALIGN_CHECK) + if (out_align_flag) + { + memcpy(symmetric_info->out, out, symmetric_info->length); + rt_free(out); + } + + if (in_align_flag) + { + rt_free(in); + } +#endif + + return RT_EOK; +} + +static rt_err_t nu_sha_hash_run( + uint32_t u32OpMode, + uint8_t *pu8InData, + uint32_t u32DataLen +) +{ + rt_mutex_take(&s_SHA_mutex, RT_WAITING_FOREVER); + + //Using SHA + SHA_Open(CRPT, u32OpMode, SHA_IN_OUT_SWAP, 0); + + //Setup SHA DMA + SHA_SetDMATransfer(CRPT, (uint32_t)pu8InData, u32DataLen); + SHA_CLR_INT_FLAG(CRPT); + //Start SHA + s_SHA_done = 0; + SHA_Start(CRPT, CRYPTO_DMA_ONE_SHOT); + while (!s_SHA_done) {}; + + rt_mutex_release(&s_SHA_mutex); + + return RT_EOK; +} + +static rt_err_t nu_sha_update(struct hwcrypto_hash *hash_ctx, const rt_uint8_t *in, rt_size_t length) +{ + uint32_t u32SHAOpMode; + unsigned char *nu_in; + + //Select SHA operation mode + switch (hash_ctx->parent.type & (HWCRYPTO_MAIN_TYPE_MASK | HWCRYPTO_SUB_TYPE_MASK)) + { + case HWCRYPTO_TYPE_SHA1: + u32SHAOpMode = SHA_MODE_SHA1; + break; + case HWCRYPTO_TYPE_SHA224: + u32SHAOpMode = SHA_MODE_SHA224; + break; + case HWCRYPTO_TYPE_SHA256: + u32SHAOpMode = SHA_MODE_SHA256; + break; + case HWCRYPTO_TYPE_SHA384: + u32SHAOpMode = SHA_MODE_SHA384; + break; + case HWCRYPTO_TYPE_SHA512: + u32SHAOpMode = SHA_MODE_SHA512; + break; + default : + return -RT_ERROR; + } + + nu_in = (unsigned char *)in; + +#if !defined(NU_HWCRYPTO_NOT_ALIGN_CHECK) + unsigned char in_align_flag = 0; + + //Checking in data buffer address alignment or not + if (((rt_uint32_t)nu_in % 4) != 0) + { + nu_in = rt_malloc(length); + if (nu_in == RT_NULL) + { + LOG_E("fun[%s] memory allocate %d bytes failed!", __FUNCTION__, length); + return -RT_ENOMEM; + } + + memcpy(nu_in, in, length); + in_align_flag = 1; + } +#endif + + nu_sha_hash_run(u32SHAOpMode, nu_in, length); + +#if !defined(NU_HWCRYPTO_NOT_ALIGN_CHECK) + if (in_align_flag) + { + rt_free(nu_in); + } +#endif + + return RT_EOK; +} + +static rt_err_t nu_sha_finish(struct hwcrypto_hash *hash_ctx, rt_uint8_t *out, rt_size_t length) +{ + unsigned char *nu_out; + + //Check SHA Hash value buffer length + switch (hash_ctx->parent.type & (HWCRYPTO_MAIN_TYPE_MASK | HWCRYPTO_SUB_TYPE_MASK)) + { + case HWCRYPTO_TYPE_SHA1: + if (length < 5UL) + { + return -RT_EINVAL; + } + break; + case HWCRYPTO_TYPE_SHA224: + if (length < 7UL) + { + return -RT_EINVAL; + } + break; + case HWCRYPTO_TYPE_SHA256: + if (length < 8UL) + { + return -RT_EINVAL; + } + break; + case HWCRYPTO_TYPE_SHA384: + if (length < 12UL) + { + return -RT_EINVAL; + } + break; + case HWCRYPTO_TYPE_SHA512: + if (length < 16UL) + { + return -RT_EINVAL; + } + break; + default : + return -RT_ERROR; + } + + nu_out = (unsigned char *)out; + +#if !defined(NU_HWCRYPTO_NOT_ALIGN_CHECK) + unsigned char out_align_flag = 0; + + //Checking out data buffer address alignment or not + if (((rt_uint32_t)nu_out % 4) != 0) + { + nu_out = rt_malloc(length); + if (nu_out == RT_NULL) + { + LOG_E("fun[%s] memory allocate %d bytes failed!", __FUNCTION__, length); + return -RT_ENOMEM; + } + + out_align_flag = 1; + } +#endif + + SHA_Read(CRPT, (uint32_t *)nu_out); + +#if !defined(NU_HWCRYPTO_NOT_ALIGN_CHECK) + if (out_align_flag) + { + memcpy(out, out, length); + rt_free(out); + } +#endif + + return RT_EOK; +} + +#if !defined(BSP_USING_TRNG) +static rt_uint32_t nu_prng_rand(struct hwcrypto_rng *ctx) +{ + return nu_prng_run(); +} + +#endif + +static const struct hwcrypto_symmetric_ops nu_aes_ops = +{ + .crypt = nu_aes_crypt, +}; + +static const struct hwcrypto_symmetric_ops nu_des_ops = +{ + .crypt = nu_des_crypt, +}; + +static const struct hwcrypto_hash_ops nu_sha_ops = +{ + .update = nu_sha_update, + .finish = nu_sha_finish, +}; + +#endif + +/* CRC operation ------------------------------------------------------------*/ +#if defined(BSP_USING_CRC) + +static const struct hwcrypto_crc_ops nu_crc_ops = +{ + .update = nu_crc_update, +}; + +#endif + +/* TRNG operation ------------------------------------------------------------*/ +#if defined(BSP_USING_TRNG) + +static const struct hwcrypto_rng_ops nu_rng_ops = +{ + .update = nu_trng_rand, +}; + +#elif defined(BSP_USING_CRYPTO) + +static const struct hwcrypto_rng_ops nu_rng_ops = +{ + .update = nu_prng_rand, +}; + +#endif + +/* Register crypto interface ----------------------------------------------------------*/ +static rt_err_t nu_hwcrypto_create(struct rt_hwcrypto_ctx *ctx) +{ + rt_err_t res = RT_EOK; + + switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK) + { +#if defined(BSP_USING_TRNG) + case HWCRYPTO_TYPE_RNG: + { + ctx->contex = RT_NULL; + //Setup RNG operation + ((struct hwcrypto_rng *)ctx)->ops = &nu_rng_ops; + break; + } +#endif /* BSP_USING_TRNG */ + +#if defined(BSP_USING_CRC) + case HWCRYPTO_TYPE_CRC: + { + ctx->contex = RT_NULL; + //Setup CRC operation + ((struct hwcrypto_crc *)ctx)->ops = &nu_crc_ops; + break; + } +#endif /* BSP_USING_CRC */ + +#if defined(BSP_USING_CRYPTO) + case HWCRYPTO_TYPE_AES: + { + ctx->contex = RT_NULL; + //Setup AES operation + ((struct hwcrypto_symmetric *)ctx)->ops = &nu_aes_ops; + break; + } + + case HWCRYPTO_TYPE_DES: + { + ctx->contex = RT_NULL; + //Setup DES operation + ((struct hwcrypto_symmetric *)ctx)->ops = &nu_des_ops; + break; + } + + case HWCRYPTO_TYPE_3DES: + { + ctx->contex = RT_NULL; + //Setup 3DES operation + ((struct hwcrypto_symmetric *)ctx)->ops = &nu_des_ops; + break; + } + + + case HWCRYPTO_TYPE_SHA1: + { + ctx->contex = RT_NULL; + //Setup SHA1 operation + ((struct hwcrypto_hash *)ctx)->ops = &nu_sha_ops; + break; + } + + case HWCRYPTO_TYPE_SHA2: + { + ctx->contex = RT_NULL; + //Setup SHA2 operation + ((struct hwcrypto_hash *)ctx)->ops = &nu_sha_ops; + break; + } + +#if !defined(BSP_USING_TRNG) + case HWCRYPTO_TYPE_RNG: + { + ctx->contex = RT_NULL; + ((struct hwcrypto_rng *)ctx)->ops = &nu_rng_ops; +#if defined(NU_PRNG_USE_SEED) + nu_prng_open(NU_PRNG_SEED_VALUE); +#else + nu_prng_open(rt_tick_get()); +#endif + break; + } +#endif /* !BSP_USING_TRNG */ + +#endif /* BSP_USING_CRYPTO */ + + + default: + res = -RT_ERROR; + break; + } + + return res; +} + +static void nu_hwcrypto_destroy(struct rt_hwcrypto_ctx *ctx) +{ + if (ctx->contex) + rt_free(ctx->contex); +} + +static rt_err_t nu_hwcrypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcrypto_ctx *src) +{ + rt_err_t res = RT_EOK; + + if (des->contex && src->contex) + { + rt_memcpy(des->contex, src->contex, sizeof(struct rt_hwcrypto_ctx)); + } + else + return -RT_EINVAL; + return res; +} + +static void nu_hwcrypto_reset(struct rt_hwcrypto_ctx *ctx) +{ + switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK) + { +#if !defined(BSP_USING_TRNG) + case HWCRYPTO_TYPE_RNG: + { +#if defined(NU_PRNG_USE_SEED) + nu_prng_open(NU_PRNG_SEED_VALUE); +#else + nu_prng_open(rt_tick_get()); +#endif + break; + } +#endif /* !BSP_USING_TRNG */ + + default: + break; + } +} + +/* Init and register nu_hwcrypto_dev */ + +int nu_hwcrypto_device_init(void) +{ + static struct rt_hwcrypto_device nu_hwcrypto_dev; + + nu_hwcrypto_dev.ops = &nu_hwcrypto_ops; + nu_hwcrypto_dev.id = 0; + nu_hwcrypto_dev.user_data = &nu_hwcrypto_dev; + +#if defined(BSP_USING_CRYPTO) + nu_crypto_init(); +#endif + +#if defined(BSP_USING_CRC) + nu_crc_init(); +#endif + +#if defined(BSP_USING_TRNG) + nu_trng_init(); +#endif + + // register hwcrypto operation + if (rt_hwcrypto_register(&nu_hwcrypto_dev, RT_HWCRYPTO_DEFAULT_NAME) != RT_EOK) + { + return -1; + } + + return 0; +} +INIT_DEVICE_EXPORT(nu_hwcrypto_device_init); + +#endif //#if ((defined(BSP_USING_CRYPTO) || defined(BSP_USING_TRNG) || defined(BSP_USING_CRC)) && defined(RT_USING_HWCRYPTO)) diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_eadc.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_eadc.c new file mode 100644 index 0000000000000000000000000000000000000000..60fb68e44c12e31f450b715d6e7a586b9f0d89f4 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_eadc.c @@ -0,0 +1,162 @@ +/**************************************************************************//** +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-2-11 FYChou First version +* +******************************************************************************/ + +#include +#include +#include + +#ifdef BSP_USING_EADC + +/* Private define ---------------------------------------------------------------*/ + +/* Private Typedef --------------------------------------------------------------*/ +struct nu_eadc +{ + struct rt_adc_device dev; + char *name; + EADC_T *eadc_base; + int eadc_reg_tab; + int eadc_max_ch_num; + +}; +typedef struct nu_eadc *nu_eadc_t; + +/* Private functions ------------------------------------------------------------*/ +static rt_err_t nu_eadc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled); +static rt_err_t nu_get_eadc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value); +static rt_err_t nu_get_eadc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value); + + +/* Public functions ------------------------------------------------------------*/ +int rt_hw_eadc_init(void); + +/* Private variables ------------------------------------------------------------*/ + +static struct nu_eadc nu_eadc_arr [] = +{ +#if defined(BSP_USING_EADC0) + { + .name = "eadc0", + .eadc_base = EADC0, + .eadc_max_ch_num = 19, + }, +#endif + +#if defined(BSP_USING_EADC1) + { + .name = "eadc1", + .eadc_base = EADC1, + .eadc_max_ch_num = 19, + }, +#endif + + {0} +}; + +static const struct rt_adc_ops nu_adc_ops = +{ + nu_eadc_enabled, + nu_get_eadc_value, +}; +typedef struct rt_adc_ops *rt_adc_ops_t; + + +/* nu_adc_enabled - Enable ADC clock and wait for ready */ +static rt_err_t nu_eadc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled) +{ + + EADC_T *eadc_base = ((nu_eadc_t)device)->eadc_base; + int *peadc_reg_tab = &((nu_eadc_t)device)->eadc_reg_tab; + RT_ASSERT(device != RT_NULL); + + if (channel >= ((nu_eadc_t)device)->eadc_max_ch_num) + return -(RT_EINVAL); + + if (enabled) + { + if (*peadc_reg_tab == 0) + { + EADC_Open(eadc_base, EADC_CTL_DIFFEN_SINGLE_END); + } + + *peadc_reg_tab |= (0x1 << channel); + } + else + { + *peadc_reg_tab &= ~(0x1 << channel); + + if (*peadc_reg_tab == 0) + { + EADC_Close(eadc_base); + } + } + + return RT_EOK; +} + +static rt_err_t nu_get_eadc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value) +{ + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(value != RT_NULL); + + EADC_T *eadc_base = ((nu_eadc_t)device)->eadc_base; + int *peadc_reg_tab = &((nu_eadc_t)device)->eadc_reg_tab; + + if (channel >= ((nu_eadc_t)device)->eadc_max_ch_num) + { + *value = 0xFFFFFFFF; + return -(RT_EINVAL); + } + + if ((*peadc_reg_tab & (1 << channel)) == 0) + { + *value = 0xFFFFFFFF; + return -(RT_EBUSY); + } + + EADC_ConfigSampleModule(eadc_base, 0, EADC_SOFTWARE_TRIGGER, channel); + + EADC_CLR_INT_FLAG(eadc_base, EADC_STATUS2_ADIF0_Msk); + + EADC_ENABLE_INT(eadc_base, BIT0); + + EADC_ENABLE_SAMPLE_MODULE_INT(eadc_base, 0, BIT0); + + EADC_START_CONV(eadc_base, BIT0); + + while (EADC_GET_INT_FLAG(eadc_base, BIT0) == 0); + + *value = EADC_GET_CONV_DATA(eadc_base, 0); + + return RT_EOK; +} + +int rt_hw_eadc_init(void) +{ + rt_err_t result = RT_ERROR; + int nu_sel = 0; + + while (nu_eadc_arr[nu_sel].name != 0) + { + nu_eadc_arr[nu_sel].eadc_reg_tab = 0; + + result = rt_hw_adc_register(&nu_eadc_arr[nu_sel].dev, nu_eadc_arr[nu_sel].name, &nu_adc_ops, NULL); + RT_ASSERT(result == RT_EOK); + nu_sel++; + } + + return result; +} +INIT_BOARD_EXPORT(rt_hw_eadc_init); + + +#endif //#if defined(BSP_USING_EADC) diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_ebi.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_ebi.c new file mode 100644 index 0000000000000000000000000000000000000000..aa20ab8e83f7f3787cc845312394d06575e402a6 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_ebi.c @@ -0,0 +1,38 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-3-4 Philo First version +* +******************************************************************************/ +#include + +#ifdef BSP_USING_EBI +#define MAX_BANK EBI_BANK2 + +/* Private variables ------------------------------------------------------------*/ +static uint8_t nu_ebi_bank_mask = 0; + +/* Public functions -------------------------------------------------------------*/ +rt_err_t nu_ebi_init(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel) +{ + if (u32Bank > MAX_BANK) + return -(RT_ERROR); + + /* Check this bank is not used */ + if ((1 << u32Bank) & nu_ebi_bank_mask) + return -(RT_ERROR); + + /* Initialize EBI */ + EBI_Open(u32Bank, u32DataWidth, u32TimingClass, u32BusMode, u32CSActiveLevel); + + nu_ebi_bank_mask |= (1 << u32Bank); + + return RT_EOK; +} + +#endif //BSP_USING_EBI diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_ebi.h b/bsp/nuvoton/libraries/m480/rtt_port/drv_ebi.h new file mode 100644 index 0000000000000000000000000000000000000000..1b5aa5abd402723ad2b824a9f5b84fc12894d98a --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_ebi.h @@ -0,0 +1,48 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-3-5 Philo First version +* +******************************************************************************/ +#ifndef __DRV_EBI_H___ +#define __DRV_EBI_H___ + +#include +#include + +/** + * @brief Initialize EBI for specify Bank + * + * @param[in] u32Bank Bank number for EBI. Valid values are: + * - \ref EBI_BANK0 + * - \ref EBI_BANK1 + * - \ref EBI_BANK2 + * @param[in] u32DataWidth Data bus width. Valid values are: + * - \ref EBI_BUSWIDTH_8BIT + * - \ref EBI_BUSWIDTH_16BIT + * @param[in] u32TimingClass Default timing configuration. Valid values are: + * - \ref EBI_TIMING_FASTEST + * - \ref EBI_TIMING_VERYFAST + * - \ref EBI_TIMING_FAST + * - \ref EBI_TIMING_NORMAL + * - \ref EBI_TIMING_SLOW + * - \ref EBI_TIMING_VERYSLOW + * - \ref EBI_TIMING_SLOWEST + * @param[in] u32BusMode Set EBI bus operate mode. Valid values are: + * - \ref EBI_OPMODE_NORMAL + * - \ref EBI_OPMODE_CACCESS + * - \ref EBI_OPMODE_ADSEPARATE + * @param[in] u32CSActiveLevel CS is active High/Low. Valid values are: + * - \ref EBI_CS_ACTIVE_HIGH + * - \ref EBI_CS_ACTIVE_LOW + * + * @return RT_EOK/RT_ERROR Bank is used or not + */ +rt_err_t nu_ebi_init(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel); + +#endif // __DRV_EBI_H___ diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_ecap.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_ecap.c new file mode 100644 index 0000000000000000000000000000000000000000..c714338d9e21d8b7728ef65e8a30a6ae86029b42 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_ecap.c @@ -0,0 +1,451 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-5-21 Philo First version +* +******************************************************************************/ +#include + +#if defined(BSP_USING_ECAP) +#include +#include + +#define ECAP_CH0_POS (0) +#define ECAP_CH1_POS (1) +#define ECAP_CH2_POS (2) + +#define ECAP_CHANNEL_NUM 0x3 +#define ECAP_CLK_DIV ECAP_CAPTURE_TIMER_CLKDIV_32 + +/* Private typedef --------------------------------------------------------------*/ +typedef struct _ecap_dev +{ + ECAP_T *ecap_base; + float fUsPerTick; +} nu_ecap_dev_t; + +typedef struct _ecap +{ + struct rt_inputcapture_device parent; + nu_ecap_dev_t *ecap_dev; + uint8_t u8Channel; + rt_bool_t bfirstData; + uint32_t u32CurrentCnt; + uint32_t u32LastCnt; + rt_bool_t input_data_level; +} nu_capture_t; + +/* Private functions ------------------------------------------------------------*/ +static rt_err_t nu_capture_init(struct rt_inputcapture_device *inputcapture); +static rt_err_t nu_capture_open(struct rt_inputcapture_device *inputcapture); +static rt_err_t nu_capture_close(struct rt_inputcapture_device *inputcapture); +static rt_err_t nu_capture_get_pulsewidth(struct rt_inputcapture_device *inputcapture, rt_uint32_t *pulsewidth_us); + +/* Private define ---------------------------------------------------------------*/ +#define NU_ECAP_GET_LEVEL(status, channel) ((status&(ECAP_STATUS_CAP0_Msk<CTL1 = ((ecap)->CTL1 & ECAP_CTL1_CLKSEL_Msk)>>ECAP_CTL1_CLKSEL_Pos) + +/* Public functions -------------------------------------------------------------*/ + + +/* Private variables ------------------------------------------------------------*/ +#if (BSP_USING_ECAP0_CHMSK!=0) +static const char *nu_ecap0_device_name[ECAP_CHANNEL_NUM] = { "ecap0i0", "ecap0i1", "ecap0i2" }; +static nu_capture_t *nu_ecap0_capture[ECAP_CHANNEL_NUM] = {0}; +static nu_ecap_dev_t nu_ecap0_dev = {.ecap_base = ECAP0}; +#endif + +#if (BSP_USING_ECAP1_CHMSK!=0) +static const char *nu_ecap1_device_name[ECAP_CHANNEL_NUM] = { "ecap1i0", "ecap1i1", "ecap1i2" }; +static nu_capture_t *nu_ecap1_capture[ECAP_CHANNEL_NUM] = {0}; +static nu_ecap_dev_t nu_ecap1_dev = {.ecap_base = ECAP1}; +#endif + +static struct rt_inputcapture_ops nu_capture_ops = +{ + .init = nu_capture_init, + .open = nu_capture_open, + .close = nu_capture_close, + .get_pulsewidth = nu_capture_get_pulsewidth, +}; + +/* Functions define ------------------------------------------------------------*/ +#if (BSP_USING_ECAP0_CHMSK!=0) +void ECAP0_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uint32_t u32Status; + + /* Get input Capture status */ + u32Status = ECAP_GET_INT_STATUS(ECAP0); + +#if (BSP_USING_ECAP0_CHMSK & (0x1<input_data_level = RT_FALSE; + } + else + { + nu_ecap0_capture[0]->input_data_level = RT_TRUE; + } + + nu_ecap0_capture[0]->u32CurrentCnt = ECAP_GET_CNT_HOLD_VALUE(ECAP0, ECAP_IC0); + + rt_hw_inputcapture_isr(&nu_ecap0_capture[0]->parent, nu_ecap0_capture[0]->input_data_level); + } +#endif + + +#if (BSP_USING_ECAP0_CHMSK & (0x1<input_data_level = RT_FALSE; + } + else + { + nu_ecap0_capture[1]->input_data_level = RT_TRUE; + } + + nu_ecap0_capture[1]->u32CurrentCnt = ECAP_GET_CNT_HOLD_VALUE(ECAP0, ECAP_IC1); + + rt_hw_inputcapture_isr(&nu_ecap0_capture[1]->parent, nu_ecap0_capture[1]->input_data_level); + } +#endif + +#if (BSP_USING_ECAP0_CHMSK & (0x1<input_data_level = RT_FALSE; + } + else + { + nu_ecap0_capture[2]->input_data_level = RT_TRUE; + } + + nu_ecap0_capture[2]->u32CurrentCnt = ECAP_GET_CNT_HOLD_VALUE(ECAP0, ECAP_IC2); + + rt_hw_inputcapture_isr(&nu_ecap0_capture[2]->parent, nu_ecap0_capture[2]->input_data_level); + } +#endif + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif //(BSP_USING_ECAP0_CHMSK!=0) + + +#if (BSP_USING_ECAP1_CHMSK!=0) +void ECAP1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uint32_t u32Status; + + /* Get input Capture status */ + u32Status = ECAP_GET_INT_STATUS(ECAP1); + +#if (BSP_USING_ECAP1_CHMSK & (0x1<input_data_level = RT_FALSE; + } + else + { + nu_ecap1_capture[0]->input_data_level = RT_TRUE; + } + + nu_ecap1_capture[0]->u32CurrentCnt = ECAP_GET_CNT_HOLD_VALUE(ECAP1, ECAP_IC0); + + rt_hw_inputcapture_isr(&nu_ecap1_capture[0]->parent, nu_ecap1_capture[0]->input_data_level); + } +#endif + + +#if (BSP_USING_ECAP1_CHMSK & (0x1<input_data_level = RT_FALSE; + } + else + { + nu_ecap1_capture[1]->input_data_level = RT_TRUE; + } + + nu_ecap1_capture[1]->u32CurrentCnt = ECAP_GET_CNT_HOLD_VALUE(ECAP1, ECAP_IC1); + + rt_hw_inputcapture_isr(&nu_ecap1_capture[1]->parent, nu_ecap1_capture[1]->input_data_level); + } +#endif + +#if (BSP_USING_ECAP1_CHMSK & (0x1<input_data_level = RT_FALSE; + } + else + { + nu_ecap1_capture[2]->input_data_level = RT_TRUE; + } + + nu_ecap1_capture[2]->u32CurrentCnt = ECAP_GET_CNT_HOLD_VALUE(ECAP1, ECAP_IC2); + + rt_hw_inputcapture_isr(&nu_ecap1_capture[2]->parent, nu_ecap1_capture[2]->input_data_level); + } +#endif + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif //(BSP_USING_ECAP1_CHMSK!=0) + +static rt_err_t nu_capture_get_pulsewidth(struct rt_inputcapture_device *inputcapture, rt_uint32_t *pulsewidth_us) +{ + rt_err_t ret = RT_EOK; + nu_capture_t *nu_capture; + float fTempCnt; + + nu_capture = (nu_capture_t *)inputcapture; + + if (nu_capture->bfirstData) + { + nu_capture->bfirstData = RT_FALSE; + ret = RT_ERROR; + + return -(ret); + } + + if (nu_capture->u32CurrentCnt > nu_capture->u32LastCnt) + fTempCnt = nu_capture->u32CurrentCnt - nu_capture->u32LastCnt; + else /* Overrun case */ + fTempCnt = nu_capture->u32CurrentCnt + ((0x1000000 - nu_capture->u32LastCnt) + 1); + + *pulsewidth_us =(int)(fTempCnt * nu_capture->ecap_dev->fUsPerTick); + + nu_capture->u32LastCnt = nu_capture->u32CurrentCnt; + + return -(ret); +} + +static float get_ecap_tick_time_us(nu_capture_t *nu_capture) +{ + uint8_t u8ClockDivider[8] = { 1, 4, 16, 32, 64, 96, 112, 128}; + if (nu_capture->ecap_dev->ecap_base == ECAP0) + return ((float)1000000 / ((float)CLK_GetPCLK0Freq() / u8ClockDivider[(nu_capture->ecap_dev->ecap_base->CTL1 & ECAP_CTL1_CLKSEL_Msk) >> ECAP_CTL1_CLKSEL_Pos])); + else + return ((float)1000000 / ((float)CLK_GetPCLK1Freq() / u8ClockDivider[(nu_capture->ecap_dev->ecap_base->CTL1 & ECAP_CTL1_CLKSEL_Msk) >> ECAP_CTL1_CLKSEL_Pos])); +} + +static rt_err_t nu_ecap_init(nu_capture_t *nu_capture) +{ + rt_err_t ret = RT_ERROR; + static rt_bool_t bECAP0Inited = RT_FALSE; + static rt_bool_t bECAP1Inited = RT_FALSE; + + if (nu_capture->ecap_dev->ecap_base == ECAP0) + { + if (bECAP0Inited == RT_FALSE) + { + /* Enable ECAP0 clock */ + SYS_UnlockReg(); + CLK_EnableModuleClock(ECAP0_MODULE); + SYS_LockReg(); + + NVIC_EnableIRQ(ECAP0_IRQn); + bECAP0Inited = RT_TRUE; + } + else + { + return ret = RT_EOK; + } + } + else if (nu_capture->ecap_dev->ecap_base == ECAP1) + { + if (bECAP1Inited == RT_FALSE) + { + /* Enable ECAP1 clock */ + SYS_UnlockReg(); + CLK_EnableModuleClock(ECAP1_MODULE); + SYS_LockReg(); + + NVIC_EnableIRQ(ECAP1_IRQn); + bECAP1Inited = RT_TRUE; + } + else + { + return ret = RT_EOK; + } + } + else + { + return ret; + } + + /* Enable ECAP */ + ECAP_Open(nu_capture->ecap_dev->ecap_base, ECAP_DISABLE_COMPARE); + + ECAP_SEL_TIMER_CLK_DIV(nu_capture->ecap_dev->ecap_base, ECAP_CLK_DIV); + + /* Select Reload function */ + ECAP_SET_CNT_CLEAR_EVENT(nu_capture->ecap_dev->ecap_base, ECAP_CTL1_OVRLDEN_Msk); + + /* Enable ECAP0 source IC */ + ECAP_SEL_INPUT_SRC(nu_capture->ecap_dev->ecap_base, ECAP_IC0, ECAP_CAP_INPUT_SRC_FROM_IC); + ECAP_SEL_INPUT_SRC(nu_capture->ecap_dev->ecap_base, ECAP_IC1, ECAP_CAP_INPUT_SRC_FROM_IC); + ECAP_SEL_INPUT_SRC(nu_capture->ecap_dev->ecap_base, ECAP_IC2, ECAP_CAP_INPUT_SRC_FROM_IC); + + /* Select IC detect rising edge */ + ECAP_SEL_CAPTURE_EDGE(nu_capture->ecap_dev->ecap_base, ECAP_IC0, ECAP_RISING_FALLING_EDGE); + ECAP_SEL_CAPTURE_EDGE(nu_capture->ecap_dev->ecap_base, ECAP_IC1, ECAP_RISING_FALLING_EDGE); + ECAP_SEL_CAPTURE_EDGE(nu_capture->ecap_dev->ecap_base, ECAP_IC2, ECAP_RISING_FALLING_EDGE); + + ret = RT_EOK; + + return -(ret); +} + +static rt_err_t nu_capture_init(struct rt_inputcapture_device *inputcapture) +{ + rt_err_t ret = RT_EOK; + nu_capture_t *nu_capture; + + RT_ASSERT(inputcapture != RT_NULL); + + nu_capture = (nu_capture_t *) inputcapture; + + if (nu_ecap_init(nu_capture) != RT_EOK) + { + rt_kprintf("Failed to initialize ECAP.\n"); + ret = RT_ERROR; + } + + return -(ret); +} + +static rt_err_t nu_capture_open(struct rt_inputcapture_device *inputcapture) +{ + rt_err_t ret = RT_EOK; + nu_capture_t *nu_capture; + + RT_ASSERT(inputcapture != RT_NULL); + + nu_capture = (nu_capture_t *) inputcapture; + + nu_capture->ecap_dev->fUsPerTick = get_ecap_tick_time_us(nu_capture); + + /* Enable ECAP Input Channel */ + ECAP_ENABLE_INPUT_CHANNEL(nu_capture->ecap_dev->ecap_base, 0x1 << (ECAP_CTL0_IC0EN_Pos + nu_capture->u8Channel)); + + /* Input Channel interrupt enabled */ + ECAP_EnableINT(nu_capture->ecap_dev->ecap_base, 0x1 << (ECAP_CTL0_CAPIEN0_Pos + nu_capture->u8Channel)); + + /* ECAP_CNT starts up-counting */ + ECAP_CNT_START(nu_capture->ecap_dev->ecap_base); + + return ret; +} + +static rt_err_t nu_capture_close(struct rt_inputcapture_device *inputcapture) +{ + rt_err_t ret = RT_EOK; + + nu_capture_t *nu_capture; + + RT_ASSERT(inputcapture != RT_NULL); + + nu_capture = (nu_capture_t *) inputcapture; + + /* Input Channel interrupt disabled */ + ECAP_DisableINT(nu_capture->ecap_dev->ecap_base, 0x1 << (ECAP_CTL0_CAPIEN0_Pos + nu_capture->u8Channel)); + + /* Disable ECAP Input Channel */ + ECAP_DISABLE_INPUT_CHANNEL(nu_capture->ecap_dev->ecap_base, 0x1 << (ECAP_CTL0_IC0EN_Pos + nu_capture->u8Channel)); + + /* Clear input capture channel flag */ + ECAP_CLR_CAPTURE_FLAG(nu_capture->ecap_dev->ecap_base, 0x1 << (ECAP_STATUS_CAPTF0_Pos + nu_capture->u8Channel)); + + return ret; +} + +static void ecap_init(nu_capture_t *nu_capture, uint8_t u8Channel, nu_ecap_dev_t *ecap_dev, const char *device_name) +{ + nu_capture->ecap_dev = ecap_dev; + nu_capture->u8Channel = u8Channel; + nu_capture->bfirstData = RT_TRUE; + nu_capture->u32CurrentCnt = 0; + nu_capture->u32LastCnt = 0; + nu_capture->parent.ops = &nu_capture_ops; + + /* register inputcapture device */ + rt_device_inputcapture_register(&nu_capture->parent, device_name, &nu_capture); +} + +/* Init and register ecap capture */ +static int nu_ecap_capture_device_init(void) +{ + for (int i = 0; i < ECAP_CHANNEL_NUM; i++) + { +#if (BSP_USING_ECAP0_CHMSK!=0) + if (BSP_USING_ECAP0_CHMSK & (0x1 << i)) + { + nu_ecap0_capture[i] = (nu_capture_t*)rt_malloc(sizeof(nu_capture_t)); + ecap_init(nu_ecap0_capture[i], i, &nu_ecap0_dev, nu_ecap0_device_name[i]); + } +#endif //#if (BSP_USING_ECAP0_CHMSK!=0) + +#if (BSP_USING_ECAP1_CHMSK!=0) + if (BSP_USING_ECAP1_CHMSK & (0x1 << i)) + { + nu_ecap1_capture[i] = (nu_capture_t*)rt_malloc(sizeof(nu_capture_t)); + ecap_init(nu_ecap1_capture[i], i, &nu_ecap1_dev, nu_ecap1_device_name[i]); + } +#endif //#if (BSP_USING_ECAP1_CHMSK!=0) + } + + return 0; +} +INIT_DEVICE_EXPORT(nu_ecap_capture_device_init); + +#endif //#if defined(BSP_USING_ECAP) diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_emac.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_emac.c new file mode 100644 index 0000000000000000000000000000000000000000..b612e708d253d281db13c7abfb2560ef5958262f --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_emac.c @@ -0,0 +1,515 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-2-7 Wayne First version +* +******************************************************************************/ + +#include + +#if defined(BSP_USING_EMAC) + +#if defined(RT_USING_LWIP) + +#include +#include +#include +#include +#include +#include "lwipopts.h" + + +#include "drv_pdma.h" + +/* Private define ---------------------------------------------------------------*/ +// RT_DEV_NAME_PREFIX e + +#if !defined(NU_EMAC_PDMA_MEMCOPY) + #define NU_EMAC_PDMA_MEMCOPY +#endif + +#if !defined(NU_EMAC_PDMA_MEMCOPY_THRESHOLD) + #define NU_EMAC_PDMA_MEMCOPY_THRESHOLD 128 +#endif + +#define NU_EMAC_DEBUG +#if defined(NU_EMAC_DEBUG) + // #define NU_EMAC_RX_DUMP + // #define NU_EMAC_TX_DUMP + #define NU_EMAC_TRACE rt_kprintf +#else + #define NU_EMAC_TRACE(...) +#endif + +#define NU_EMAC_TID_STACK_SIZE 256 + +/* Private typedef --------------------------------------------------------------*/ +struct nu_emac +{ + struct eth_device eth; + rt_uint8_t mac_addr[6]; + struct rt_semaphore eth_sem; +}; +typedef struct nu_emac *nu_emac_t; + +/* Private functions ------------------------------------------------------------*/ +#if defined(NU_EMAC_RX_DUMP) || defined(NU_EMAC_TX_DUMP) + static void nu_emac_pkt_dump(const char *msg, const struct pbuf *p); +#endif +#if LWIP_IPV4 && LWIP_IGMP + static err_t nu_igmp_mac_filter(struct netif *netif, const ip4_addr_t *ip4_addr, enum netif_mac_filter_action action); +#endif +static void nu_emac_halt(void); +static void nu_emac_reinit(void); +static void link_monitor(void *param); +static rt_err_t nu_emac_init(rt_device_t dev); + +static rt_err_t nu_emac_open(rt_device_t dev, rt_uint16_t oflag); +static rt_err_t nu_emac_close(rt_device_t dev); +static rt_size_t nu_emac_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size); +static rt_size_t nu_emac_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size); +static rt_err_t nu_emac_control(rt_device_t dev, int cmd, void *args); +static rt_err_t nu_emac_tx(rt_device_t dev, struct pbuf *p); +static struct pbuf *nu_emac_rx(rt_device_t dev); +static rt_err_t rt_hw_nu_emac_register(char *dev_name); +static int rt_hw_nu_emac_init(void); +static void *nu_emac_memcpy(void *dest, void *src, unsigned int count); + +/* Public functions -------------------------------------------------------------*/ + +/* Private variables ------------------------------------------------------------*/ +static struct nu_emac nu_emac_dev = {0}; +static struct rt_thread eth_tid; +static rt_uint8_t eth_stack[NU_EMAC_TID_STACK_SIZE]; + +#if defined(NU_EMAC_RX_DUMP) || defined(NU_EMAC_TX_DUMP) +static void nu_emac_pkt_dump(const char *msg, const struct pbuf *p) +{ + rt_uint32_t i; + rt_uint8_t *ptr = p->payload; + + NU_EMAC_TRACE("%s %d byte\n", msg, p->tot_len); + + for (i = 0; i < p->tot_len; i++) + { + if ((i % 8) == 0) + { + NU_EMAC_TRACE(" "); + } + if ((i % 16) == 0) + { + NU_EMAC_TRACE("\r\n"); + } + NU_EMAC_TRACE("%02x ", *ptr); + ptr++; + } + NU_EMAC_TRACE("\n\n"); +} +#endif /* dump */ + +static void nu_emac_halt(void) +{ + EMAC_DISABLE_RX(); + EMAC_DISABLE_TX(); +} + +static void *nu_emac_memcpy(void *dest, void *src, unsigned int count) +{ +#if defined(NU_EMAC_PDMA_MEMCOPY) + if (count >= NU_EMAC_PDMA_MEMCOPY_THRESHOLD) + return nu_pdma_memcpy(dest, src, count); +#endif + return memcpy(dest, src, count); +} + +static void nu_emac_reinit(void) +{ + rt_uint32_t EMAC_CAMxM[EMAC_CAMENTRY_NB]; + rt_uint32_t EMAC_CAMxL[EMAC_CAMENTRY_NB]; + rt_uint32_t EMAC_CAMEN; + + // Backup MAC address. + EMAC_CAMEN = EMAC->CAMEN; + for (rt_uint8_t index = 0 ; index < EMAC_CAMENTRY_NB; index ++) + { + rt_uint32_t *CAMxM = (rt_uint32_t *)((rt_uint32_t)&EMAC->CAM0M + (index * 8)); + rt_uint32_t *CAMxL = (rt_uint32_t *)((rt_uint32_t)&EMAC->CAM0L + (index * 8)); + + EMAC_CAMxM[index] = *CAMxM; + EMAC_CAMxL[index] = *CAMxL; + } + + nu_emac_halt(); + EMAC_Close(); + EMAC_Open((uint8_t *)&nu_emac_dev.mac_addr[0]); + EMAC_ENABLE_TX(); + EMAC_ENABLE_RX(); + + // Restore MAC address. + for (rt_uint8_t index = 0 ; index < EMAC_CAMENTRY_NB; index ++) + { + rt_uint32_t *CAMxM = (rt_uint32_t *)((rt_uint32_t)&EMAC->CAM0M + (index * 8)); + rt_uint32_t *CAMxL = (rt_uint32_t *)((rt_uint32_t)&EMAC->CAM0L + (index * 8)); + + *CAMxM = EMAC_CAMxM[index]; + *CAMxL = EMAC_CAMxL[index]; + } + EMAC->CAMEN = EMAC_CAMEN; +} + +#if LWIP_IPV4 && LWIP_IGMP +static err_t nu_igmp_mac_filter(struct netif *netif, const ip4_addr_t *ip4_addr, enum netif_mac_filter_action action) +{ + rt_uint8_t mac[6]; + int32_t ret = 0; + const uint8_t *p = (const uint8_t *)ip4_addr; + + mac[0] = 0x01; + mac[1] = 0x00; + mac[2] = 0x5E; + mac[3] = *(p + 1) & 0x7F; + mac[4] = *(p + 2); + mac[5] = *(p + 3); + + ret = EMAC_FillCamEntry((uint8_t *)&mac[0]); + if (ret >= 0) + { + NU_EMAC_TRACE("%s %s %s ", __FUNCTION__, (action == NETIF_ADD_MAC_FILTER) ? "add" : "del", ip4addr_ntoa(ip4_addr)); + NU_EMAC_TRACE("%02X:%02X:%02X:%02X:%02X:%02X\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + } + + return (ret >= 0) ? RT_EOK : -(RT_ERROR); +} +#endif /* LWIP_IPV4 && LWIP_IGMP */ + +static void link_monitor(void *param) +{ + nu_emac_t psNuEMAC = (nu_emac_t)param; + uint32_t LinkStatus_Last = EMAC_LINK_DOWN; + + EMAC_PhyInit(); + + while (1) + { + uint32_t LinkStatus_Current = EMAC_CheckLinkStatus(); + /* linkchange */ + if (LinkStatus_Last != LinkStatus_Current) + { + + switch (LinkStatus_Current) + { + case EMAC_LINK_DOWN: + NU_EMAC_TRACE("Link status: Down\n"); + break; + + case EMAC_LINK_100F: + NU_EMAC_TRACE("Link status: 100F\n"); + break; + + case EMAC_LINK_100H: + NU_EMAC_TRACE("Link status: 100H\n"); + break; + + case EMAC_LINK_10F: + NU_EMAC_TRACE("Link status: 10F\n"); + break; + + case EMAC_LINK_10H: + NU_EMAC_TRACE("Link status: 10H\n"); + break; + } /* switch( LinkStatus_Current ) */ + + /* Send link status to upper layer. */ + if (LinkStatus_Current == EMAC_LINK_DOWN) + eth_device_linkchange(&psNuEMAC->eth, RT_FALSE); + else + eth_device_linkchange(&psNuEMAC->eth, RT_TRUE); + + LinkStatus_Last = LinkStatus_Current; + + } /* if ( LinkStatus_Last != LinkStatus_Current ) */ + + rt_thread_delay(RT_TICK_PER_SECOND); + + } /* while(1) */ + +} + +static rt_err_t nu_emac_init(rt_device_t dev) +{ + nu_emac_t psNuEMAC = (nu_emac_t)dev; + + EMAC_Close(); + EMAC_Open((uint8_t *)&psNuEMAC->mac_addr[0]); + EMAC_ENABLE_RX(); + EMAC_ENABLE_TX(); + + NVIC_SetPriority(EMAC_TX_IRQn, 1); + NVIC_EnableIRQ(EMAC_TX_IRQn); + NVIC_SetPriority(EMAC_RX_IRQn, 1); + NVIC_EnableIRQ(EMAC_RX_IRQn); + + rt_sem_init(&psNuEMAC->eth_sem, "eth_sem", 0, RT_IPC_FLAG_FIFO); + + rt_thread_init(ð_tid, "eth", link_monitor, (void *)psNuEMAC, eth_stack, sizeof(eth_stack), RT_THREAD_PRIORITY_MAX - 2, 10); + rt_thread_startup(ð_tid); + +#if defined(LWIP_IPV4) && defined(LWIP_IGMP) + netif_set_igmp_mac_filter(psNuEMAC->eth.netif, nu_igmp_mac_filter); +#endif /* LWIP_IPV4 && LWIP_IGMP */ + + return RT_EOK; +} + +static rt_err_t nu_emac_open(rt_device_t dev, rt_uint16_t oflag) +{ + return RT_EOK; +} + +static rt_err_t nu_emac_close(rt_device_t dev) +{ + return RT_EOK; +} + +static rt_size_t nu_emac_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + rt_set_errno(-RT_ENOSYS); + return 0; +} + +static rt_size_t nu_emac_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + rt_set_errno(-RT_ENOSYS); + return 0; +} + +static rt_err_t nu_emac_control(rt_device_t dev, int cmd, void *args) +{ + nu_emac_t psNuEMAC = (nu_emac_t)dev; + switch (cmd) + { + case NIOCTL_GADDR: + /* Get MAC address */ + if (args) + rt_memcpy(args, &psNuEMAC->mac_addr[0], 6); + else + return -RT_ERROR; + + break; + default : + break; + } + + return RT_EOK; +} + +static rt_err_t nu_emac_tx(rt_device_t dev, struct pbuf *p) +{ + nu_emac_t psNuEMAC = (nu_emac_t)dev; + struct pbuf *q; + rt_uint32_t offset = 0; + + rt_uint8_t *buf = (rt_uint8_t *)EMAC_ClaimFreeTXBuf(); + + /* Get free TX buffer */ + if (buf == RT_NULL) + { + rt_sem_control(&psNuEMAC->eth_sem, RT_IPC_CMD_RESET, 0); + + EMAC_CLEAR_INT_FLAG(EMAC, EMAC_INTSTS_TXCPIF_Msk); + EMAC_ENABLE_INT(EMAC, EMAC_INTEN_TXCPIEN_Msk); + + do + { + rt_sem_take(&psNuEMAC->eth_sem, 1); + buf = (rt_uint8_t *)EMAC_ClaimFreeTXBuf(); + } + while (buf == RT_NULL); + } + + for (q = p; q != NULL; q = q->next) + { + rt_uint8_t *ptr; + rt_uint32_t len; + + len = q->len; + ptr = q->payload; + + nu_emac_memcpy(&buf[offset], ptr, len); + + offset += len; + } + +#if defined(NU_EMAC_TX_DUMP) + nu_emac_pkt_dump("TX dump", p); +#endif + + /* Return SUCCESS */ + return (EMAC_SendPktWoCopy(offset) == 1) ? RT_EOK : RT_ERROR; +} + +static struct pbuf *nu_emac_rx(rt_device_t dev) +{ + struct pbuf *p = RT_NULL; + uint8_t *pu8DataBuf = NULL; + unsigned int avaialbe_size; + + if ((avaialbe_size = EMAC_GetAvailRXBufSize(&pu8DataBuf)) > 0) + { + /* Allocate RX packet buffer. */ + p = pbuf_alloc(PBUF_RAW, avaialbe_size, PBUF_RAM); + if (p != RT_NULL) + { + RT_ASSERT(p->next == RT_NULL); + nu_emac_memcpy((void *)p->payload, (void *)pu8DataBuf, avaialbe_size); + +#if defined(NU_EMAC_RX_DUMP) + nu_emac_pkt_dump("RX dump", p); +#endif + } + else + { + NU_EMAC_TRACE("Can't allocate memory for RX packet.(%d)\n", avaialbe_size); + } + + /* Update RX descriptor */ + EMAC_RecvPktDoneWoRxTrigger(); + + } // if ( (avaialbe_size= EMAC_GetAvaiableRXBufSize()) > 0 ) + else + { + /* No avaiable RX packet, we enable RXGD/RDUIEN interrupts. */ + if (!(EMAC->INTEN & EMAC_INTEN_RDUIEN_Msk)) + { + EMAC_CLEAR_INT_FLAG(EMAC, (EMAC_INTSTS_RDUIF_Msk | EMAC_INTSTS_RXGDIF_Msk)); + EMAC_ENABLE_INT(EMAC, (EMAC_INTEN_RDUIEN_Msk | EMAC_INTEN_RXGDIEN_Msk)); + } + else + { + EMAC_CLEAR_INT_FLAG(EMAC, EMAC_INTSTS_RXGDIF_Msk); + EMAC_ENABLE_INT(EMAC, EMAC_INTEN_RXGDIEN_Msk); + } + EMAC_TRIGGER_RX(); + } //else + + return p; +} + +void EMAC_RX_IRQHandler(void) +{ + /* Enter interrupt */ + rt_interrupt_enter(); + + /* No RX descriptor avaiable, we need to get data from RX pool */ + if (EMAC_GET_INT_FLAG(EMAC, EMAC_INTSTS_RDUIF_Msk)) + { + EMAC_DISABLE_INT(EMAC, (EMAC_INTEN_RDUIEN_Msk | EMAC_INTEN_RXGDIEN_Msk)); + eth_device_ready(&nu_emac_dev.eth); + } + /* A good packet ready. */ + else if (EMAC_GET_INT_FLAG(EMAC, EMAC_INTSTS_RXGDIF_Msk)) + { + EMAC_DISABLE_INT(EMAC, EMAC_INTEN_RXGDIEN_Msk); + eth_device_ready(&nu_emac_dev.eth); + } + + /* Receive Bus Error Interrupt */ + if (EMAC_GET_INT_FLAG(EMAC, EMAC_INTSTS_RXBEIF_Msk)) + { + NU_EMAC_TRACE("Reinit Rx EMAC\n"); + EMAC_CLEAR_INT_FLAG(EMAC, EMAC_INTSTS_RXBEIF_Msk); + nu_emac_reinit(); + } + + /* Leave interrupt */ + rt_interrupt_leave(); +} + +void EMAC_TX_IRQHandler(void) +{ + /* Enter interrupt */ + rt_interrupt_enter(); + + unsigned int status = EMAC->INTSTS; + + /* Wake-up suspended process to send */ + if (EMAC_GET_INT_FLAG(EMAC, EMAC_INTSTS_TXCPIF_Msk)) + { + EMAC_DISABLE_INT(EMAC, EMAC_INTEN_TXCPIEN_Msk); + rt_sem_release(&nu_emac_dev.eth_sem); + } + + if (EMAC_GET_INT_FLAG(EMAC, EMAC_INTSTS_TXBEIF_Msk)) + { + NU_EMAC_TRACE("Reinit Tx EMAC\n"); + EMAC->INTSTS = EMAC_INTSTS_TXBEIF_Msk; + EMAC_CLEAR_INT_FLAG(EMAC, EMAC_INTSTS_TXBEIF_Msk); + nu_emac_reinit(); + } + else + EMAC_SendPktDone(); + + /* Leave interrupt */ + rt_interrupt_leave(); +} + +static rt_err_t rt_hw_nu_emac_register(char *dev_name) +{ + rt_uint32_t value = 0; + nu_emac_t psNuEMAC = (nu_emac_t)&nu_emac_dev; + + /* Read UID from FMC */ + SYS_UnlockReg(); + FMC_Open(); + for (rt_uint8_t i = 0; i < 3; i++) + { + value += FMC_ReadUID(i); + } + FMC_Close(); + SYS_LockReg(); + + /* Assign MAC address */ + psNuEMAC->mac_addr[0] = 0x82; + psNuEMAC->mac_addr[1] = 0x06; + psNuEMAC->mac_addr[2] = 0x21; + psNuEMAC->mac_addr[3] = (value >> 16) & 0xff; + psNuEMAC->mac_addr[4] = (value >> 8) & 0xff; + psNuEMAC->mac_addr[5] = (value) & 0xff; + NU_EMAC_TRACE("MAC address: %02X:%02X:%02X:%02X:%02X:%02X\n", \ + psNuEMAC->mac_addr[0], \ + psNuEMAC->mac_addr[1], \ + psNuEMAC->mac_addr[2], \ + psNuEMAC->mac_addr[3], \ + psNuEMAC->mac_addr[4], \ + psNuEMAC->mac_addr[5]); + + /* Register member functions */ + psNuEMAC->eth.parent.init = nu_emac_init; + psNuEMAC->eth.parent.open = nu_emac_open; + psNuEMAC->eth.parent.close = nu_emac_close; + psNuEMAC->eth.parent.read = nu_emac_read; + psNuEMAC->eth.parent.write = nu_emac_write; + psNuEMAC->eth.parent.control = nu_emac_control; + psNuEMAC->eth.parent.user_data = RT_NULL; + psNuEMAC->eth.eth_rx = nu_emac_rx; + psNuEMAC->eth.eth_tx = nu_emac_tx; + + /* Register eth device */ + return eth_device_init(&nu_emac_dev.eth, dev_name); +} + +static int rt_hw_nu_emac_init(void) +{ + return rt_hw_nu_emac_register("e0"); +} + +INIT_APP_EXPORT(rt_hw_nu_emac_init); + +#endif /* #if defined( RT_USING_LWIP ) */ + +#endif /* #if defined( BSP_USING_EMAC ) */ diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_epwm.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_epwm.c new file mode 100644 index 0000000000000000000000000000000000000000..ea4d29339e8b2c7edc13d62bd804030e71e0fc8b --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_epwm.c @@ -0,0 +1,268 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-3-16 YH First version +* +******************************************************************************/ + +#include + +#if defined(BSP_USING_EPWM) + +#define LOG_TAG "drv.epwm" +#define DBG_ENABLE +#define DBG_SECTION_NAME "drv.epwm" +#define DBG_LEVEL DBG_INFO +#define DBG_COLOR +#include + +#include +#include +#include +#include "NuMicro.h" + +enum +{ + EPWM_START = -1, +#if defined(BSP_USING_EPWM0) + EPWM0_IDX, +#endif +#if defined(BSP_USING_EPWM1) + EPWM1_IDX, +#endif + EPWM_CNT +}; + +struct nu_epwm +{ + struct rt_device_pwm dev; + char *name; + EPWM_T *epwm_base; +}; + +typedef struct nu_epwm *nu_epwm_t; + +static struct nu_epwm nu_epwm_arr [] = +{ +#if defined(BSP_USING_EPWM0) + { + .name = "epwm0", + .epwm_base = EPWM0, + }, +#endif + +#if defined(BSP_USING_EPWM1) + { + .name = "epwm1", + .epwm_base = EPWM1, + }, +#endif + {0} +}; /* epwm nu_epwm */ + +static rt_err_t nu_epwm_control(struct rt_device_pwm *device, int cmd, void *arg); + +static struct rt_pwm_ops nu_epwm_ops = +{ + .control = nu_epwm_control +}; + +static rt_err_t nu_epwm_enable(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration, rt_bool_t enable) +{ + rt_err_t result = RT_EOK; + + EPWM_T *pwm_base = ((nu_epwm_t)device)->epwm_base; + rt_uint32_t pwm_channel = ((struct rt_pwm_configuration *)configuration)->channel; + + if (enable == RT_TRUE) + { + EPWM_EnableOutput(pwm_base, 1 << pwm_channel); + EPWM_Start(pwm_base, 1 << pwm_channel); + } + else + { + EPWM_DisableOutput(pwm_base, 1 << pwm_channel); + EPWM_ForceStop(pwm_base, 1 << pwm_channel); + } + + return result; +} + +static rt_err_t nu_epwm_set(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration) +{ + if ((((struct rt_pwm_configuration *)configuration)->period) <= 0) + return -(RT_ERROR); + rt_uint8_t pwm_channel_pair; + rt_uint32_t pwm_freq, pwm_dutycycle ; + EPWM_T *pwm_base = ((nu_epwm_t)device)->epwm_base; + rt_uint8_t pwm_channel = ((struct rt_pwm_configuration *)configuration)->channel; + rt_uint32_t pwm_period = ((struct rt_pwm_configuration *)configuration)->period; + rt_uint32_t pwm_pulse = ((struct rt_pwm_configuration *)configuration)->pulse; + rt_uint32_t pre_pwm_prescaler = EPWM_GET_PRESCALER(pwm_base, pwm_channel); + + if ((pwm_channel % 2) == 0) + pwm_channel_pair = pwm_channel + 1; + else + pwm_channel_pair = pwm_channel - 1; + + pwm_freq = 1000000000 / pwm_period; + pwm_dutycycle = (pwm_pulse * 100) / pwm_period; + + EPWM_ConfigOutputChannel(pwm_base, pwm_channel, pwm_freq, pwm_dutycycle) ; + + if ((pre_pwm_prescaler != 0) || (EPWM_GET_CNR(pwm_base, pwm_channel_pair) != 0) || (EPWM_GET_CMR(pwm_base, pwm_channel_pair) != 0)) + { + if (pre_pwm_prescaler < EPWM_GET_PRESCALER(pwm_base, pwm_channel)) + { + EPWM_SET_CNR(pwm_base, pwm_channel_pair, ((EPWM_GET_CNR(pwm_base, pwm_channel_pair) + 1) * (pre_pwm_prescaler + 1)) / (EPWM_GET_PRESCALER(pwm_base, pwm_channel) + 1)); + EPWM_SET_CMR(pwm_base, pwm_channel_pair, (EPWM_GET_CMR(pwm_base, pwm_channel_pair) * (pre_pwm_prescaler + 1)) / (EPWM_GET_PRESCALER(pwm_base, pwm_channel) + 1)); + } + else if (pre_pwm_prescaler > EPWM_GET_PRESCALER(pwm_base, pwm_channel)) + { + EPWM_SET_CNR(pwm_base, pwm_channel, ((EPWM_GET_CNR(pwm_base, pwm_channel) + 1) * (EPWM_GET_PRESCALER(pwm_base, pwm_channel) + 1)) / (pre_pwm_prescaler + 1)); + EPWM_SET_CMR(pwm_base, pwm_channel, (EPWM_GET_CMR(pwm_base, pwm_channel) * (EPWM_GET_PRESCALER(pwm_base, pwm_channel) + 1)) / (pre_pwm_prescaler + 1)); + } + } + return RT_EOK; +} + +static rt_uint32_t nu_epwm_clksr(struct rt_device_pwm *device) +{ + rt_uint32_t u32Src, u32EPWMClockSrc; + EPWM_T *pwm_base = ((nu_epwm_t)device)->epwm_base; + if (pwm_base == EPWM0) + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM0SEL_Msk; + } + else /* (epwm == EPWM1) */ + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM1SEL_Msk; + } + + if (u32Src == 0U) + { + /* clock source is from PLL clock */ + u32EPWMClockSrc = CLK_GetPLLClockFreq(); + } + else + { + /* clock source is from PCLK */ + SystemCoreClockUpdate(); + if (pwm_base == EPWM0) + { + u32EPWMClockSrc = CLK_GetPCLK0Freq(); + } + else /* (epwm == EPWM1) */ + { + u32EPWMClockSrc = CLK_GetPCLK1Freq(); + } + } + return u32EPWMClockSrc; +} + +static rt_err_t nu_epwm_get(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration) +{ + rt_uint32_t pwm_real_period, pwm_real_duty, time_tick, u32EPWMClockSrc ; + + EPWM_T *pwm_base = ((nu_epwm_t)device)->epwm_base; + rt_uint32_t pwm_channel = ((struct rt_pwm_configuration *)configuration)->channel; + rt_uint32_t pwm_prescale = EPWM_GET_PRESCALER(pwm_base, pwm_channel); + rt_uint32_t pwm_period = EPWM_GET_CNR(pwm_base, pwm_channel); + rt_uint32_t pwm_pulse = EPWM_GET_CMR(pwm_base, pwm_channel); + + u32EPWMClockSrc = nu_epwm_clksr(device); + time_tick = 1000000000000 / u32EPWMClockSrc; + + pwm_real_period = (((pwm_prescale + 1) * (pwm_period + 1)) * time_tick) / 1000; + pwm_real_duty = (((pwm_prescale + 1) * pwm_pulse * time_tick)) / 1000; + ((struct rt_pwm_configuration *)configuration)->period = pwm_real_period; + ((struct rt_pwm_configuration *)configuration)->pulse = pwm_real_duty; + + LOG_I("%s %d %d %d\n", ((nu_epwm_t)device)->name, configuration->channel, configuration->period, configuration->pulse); + + return RT_EOK; +} + +static rt_err_t nu_epwm_control(struct rt_device_pwm *device, int cmd, void *arg) +{ + struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(configuration != RT_NULL); + + if (((((struct rt_pwm_configuration *)configuration)->channel) + 1) > EPWM_CHANNEL_NUM) + return -(RT_ERROR); + + switch (cmd) + { + case PWM_CMD_ENABLE: + return nu_epwm_enable(device, configuration, RT_TRUE); + case PWM_CMD_DISABLE: + return nu_epwm_enable(device, configuration, RT_FALSE); + case PWM_CMD_SET: + return nu_epwm_set(device, configuration); + case PWM_CMD_GET: + return nu_epwm_get(device, configuration); + } + return -(RT_EINVAL); +} + +int rt_hw_epwm_init(void) +{ + rt_err_t ret; + int i; + + for (i = (EPWM_START + 1); i < EPWM_CNT; i++) + { + ret = rt_device_pwm_register(&nu_epwm_arr[i].dev, nu_epwm_arr[i].name, &nu_epwm_ops, RT_NULL); + RT_ASSERT(ret == RT_EOK); + } + + return 0; +} + +INIT_DEVICE_EXPORT(rt_hw_epwm_init); + +#ifdef RT_USING_FINSH +#include + +#ifdef FINSH_USING_MSH + +static int pwm_get(int argc, char **argv) +{ + int result = 0; + struct rt_device_pwm *device = RT_NULL; + struct rt_pwm_configuration configuration = {0}; + + if (argc != 3) + { + rt_kprintf("Usage: pwm_get pwm1 1\n"); + result = -RT_ERROR; + goto _exit; + } + + device = (struct rt_device_pwm *)rt_device_find(argv[1]); + if (!device) + { + result = -RT_EIO; + goto _exit; + } + + configuration.channel = atoi(argv[2]); + result = rt_device_control(&device->parent, PWM_CMD_GET, &configuration); + +_exit: + return result; +} + +MSH_CMD_EXPORT(pwm_get, pwm_get epwm1 1); + +#endif /* FINSH_USING_MSH */ +#endif /* RT_USING_FINSH */ + +#endif diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_epwm_capture.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_epwm_capture.c new file mode 100644 index 0000000000000000000000000000000000000000..af21f643ec8b1621a8a6290a9cde9227556314e1 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_epwm_capture.c @@ -0,0 +1,509 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-5-4 Philo First version +* +******************************************************************************/ +#include + +#if defined(BSP_USING_EPWM_CAPTURE) +#include +#include + +#define EPWM_CH0CH1_POS (0) +#define EPWM_CH2CH3_POS (2) +#define EPWM_CH4CH5_POS (4) + +/* Private typedef --------------------------------------------------------------*/ +typedef struct nu_capture +{ + struct rt_inputcapture_device parent; + EPWM_T *epwm; + uint8_t u8Channel; + IRQn_Type irq; + uint32_t u32CurrentRisingCnt; + uint32_t u32CurrentFallingCnt; + rt_bool_t input_data_level; +} nu_capture_t; + +/* Private functions ------------------------------------------------------------*/ +static rt_err_t nu_capture_init(struct rt_inputcapture_device *inputcapture); +static rt_err_t nu_capture_open(struct rt_inputcapture_device *inputcapture); +static rt_err_t nu_capture_close(struct rt_inputcapture_device *inputcapture); +static rt_err_t nu_capture_get_pulsewidth(struct rt_inputcapture_device *inputcapture, rt_uint32_t *pulsewidth_us); + +/* Public functions -------------------------------------------------------------*/ + + +/* Private variables ------------------------------------------------------------*/ +#if (BSP_USING_EPWM0_CAPTURE_CHMSK!=0) +static const char *nu_epwm0_device_name[EPWM_CHANNEL_NUM] = { "epwm0i0", "epwm0i1", "epwm0i2", "epwm0i3", "epwm0i4", "epwm0i5"}; +static const IRQn_Type nu_epwm0_irq[EPWM_CHANNEL_NUM / 2] = { EPWM0P0_IRQn, EPWM0P1_IRQn, EPWM0P2_IRQn}; +static nu_capture_t nu_epwm0_capture[EPWM_CHANNEL_NUM] = {0}; +#endif + +#if (BSP_USING_EPWM1_CAPTURE_CHMSK!=0) +static const char *nu_epwm1_device_name[EPWM_CHANNEL_NUM] = {"epwm1i0", "epwm1i1", "epwm1i2", "epwm1i3", "epwm1i4", "epwm1i5", }; +static const IRQn_Type nu_epwm1_irq[EPWM_CHANNEL_NUM / 2] = {EPWM1P0_IRQn, EPWM1P1_IRQn, EPWM1P2_IRQn }; +static nu_capture_t nu_epwm1_capture[EPWM_CHANNEL_NUM] = {0}; +#endif + +static struct rt_inputcapture_ops nu_capture_ops = +{ + .init = nu_capture_init, + .open = nu_capture_open, + .close = nu_capture_close, + .get_pulsewidth = nu_capture_get_pulsewidth, +}; + +/* Functions define ------------------------------------------------------------*/ +static rt_err_t CalPulseWidth(nu_capture_t *nu_capture) +{ + rt_bool_t bWrapAroundFlag = RT_FALSE; + + /* Check rising/falling capture counter is overflow or not */ + if (EPWM_GetWrapAroundFlag(nu_capture->epwm, nu_capture->u8Channel)) + { + EPWM_ClearWrapAroundFlag(nu_capture->epwm, nu_capture->u8Channel); + bWrapAroundFlag = RT_TRUE; + } + + /* Read the capture counter value if falling/risning edge */ + if (EPWM_GetCaptureIntFlag(nu_capture->epwm, nu_capture->u8Channel) == 1)//Rising edge + { + EPWM_ClearCaptureIntFlag(nu_capture->epwm, nu_capture->u8Channel, EPWM_CAPTURE_INT_RISING_LATCH); + + if (bWrapAroundFlag) + { + nu_capture->u32CurrentRisingCnt = 0x10000; + } + nu_capture->u32CurrentRisingCnt += EPWM_GET_CAPTURE_RISING_DATA(nu_capture->epwm, nu_capture->u8Channel); + } + else if (EPWM_GetCaptureIntFlag(nu_capture->epwm, nu_capture->u8Channel) == 2)//Falling edge + { + EPWM_ClearCaptureIntFlag(nu_capture->epwm, nu_capture->u8Channel, EPWM_CAPTURE_INT_FALLING_LATCH); + + if (bWrapAroundFlag) + { + nu_capture->u32CurrentFallingCnt = 0x10000; + } + nu_capture->u32CurrentFallingCnt += EPWM_GET_CAPTURE_FALLING_DATA(nu_capture->epwm, nu_capture->u8Channel); + } + else + { + EPWM_ClearCaptureIntFlag(nu_capture->epwm, nu_capture->u8Channel, EPWM_CAPTURE_INT_RISING_LATCH); + EPWM_ClearCaptureIntFlag(nu_capture->epwm, nu_capture->u8Channel, EPWM_CAPTURE_INT_FALLING_LATCH); + + return -(RT_ERROR); + } + + return RT_EOK; +} + +#if (BSP_USING_EPWM0_CAPTURE_CHMSK&(0x3<u32CurrentFallingCnt) + { + *pulsewidth_us = nu_capture->u32CurrentFallingCnt; + nu_capture->input_data_level = RT_FALSE; + nu_capture->u32CurrentFallingCnt = 0; + } + else if (nu_capture->u32CurrentRisingCnt) + { + *pulsewidth_us = nu_capture->u32CurrentRisingCnt; + nu_capture->input_data_level = RT_TRUE; + nu_capture->u32CurrentRisingCnt = 0; + } + else + { + ret = RT_ERROR; + } + return -(ret); +} + +static rt_err_t nu_epwm_init(nu_capture_t *nu_capture) +{ + rt_err_t ret = RT_ERROR; + static rt_bool_t bEPWM0Inited = RT_FALSE; + static rt_bool_t bEPWM1Inited = RT_FALSE; + + if (nu_capture->epwm == EPWM0) + { + if (bEPWM0Inited == RT_FALSE) + { + /* Enable EPWM0 clock */ + SYS_UnlockReg(); + CLK_EnableModuleClock(EPWM0_MODULE); + CLK_SetModuleClock(EPWM0_MODULE, CLK_CLKSEL2_EPWM0SEL_PLL, (uint32_t)NULL); + SYS_LockReg(); + bEPWM0Inited = RT_TRUE; + } + ret = RT_EOK; + } + else if (nu_capture->epwm == EPWM1) + { + if (bEPWM1Inited == RT_FALSE) + { + /* Enable EPWM1 clock */ + SYS_UnlockReg(); + CLK_EnableModuleClock(EPWM1_MODULE); + CLK_SetModuleClock(EPWM1_MODULE, CLK_CLKSEL2_EPWM1SEL_PLL, (uint32_t)NULL); + SYS_LockReg(); + bEPWM1Inited = RT_TRUE; + } + ret = RT_EOK; + } + + return -(ret); +} + +static rt_err_t nu_capture_init(struct rt_inputcapture_device *inputcapture) +{ + rt_err_t ret = RT_EOK; + nu_capture_t *nu_capture; + + RT_ASSERT(inputcapture != RT_NULL); + + nu_capture = (nu_capture_t *) inputcapture; + + if (nu_epwm_init(nu_capture) != RT_EOK) + { + rt_kprintf("Failed to initialize EPWM%d.\n", nu_capture->epwm); + ret = RT_ERROR; + } + + return -(ret); +} + +static rt_err_t nu_capture_open(struct rt_inputcapture_device *inputcapture) +{ + rt_err_t ret = RT_EOK; + nu_capture_t *nu_capture; + + RT_ASSERT(inputcapture != RT_NULL); + + nu_capture = (nu_capture_t *) inputcapture; + + /* Set capture time as 1000 nano second */ + EPWM_ConfigCaptureChannel(nu_capture->epwm, nu_capture->u8Channel, 1000, 0); + + /* Enable capture rising/falling edge interrupt */ + EPWM_EnableCaptureInt(nu_capture->epwm, nu_capture->u8Channel, EPWM_CAPTURE_INT_FALLING_LATCH | EPWM_CAPTURE_INT_RISING_LATCH); + + /* Enable EPWM NVIC interrupt */ + NVIC_EnableIRQ(nu_capture->irq); + + /* Enable Capture Function for EPWM */ + EPWM_EnableCapture(nu_capture->epwm, 0x1 << nu_capture->u8Channel); + + /* Enable rising/falling capture reload */ + nu_capture->epwm->CAPCTL |= (0x1 << (EPWM_CAPCTL_RCRLDEN0_Pos + nu_capture->u8Channel)) + | (0x1 << (EPWM_CAPCTL_FCRLDEN0_Pos + nu_capture->u8Channel)); + + /* Set counter type as down count */ + EPWM_SET_ALIGNED_TYPE(nu_capture->epwm, 0x1 << nu_capture->u8Channel, EPWM_UP_COUNTER); + + /* Enable EPWM Timer */ + EPWM_Start(nu_capture->epwm, 0x1 << nu_capture->u8Channel); + + return ret; +} + +static rt_err_t nu_capture_close(struct rt_inputcapture_device *inputcapture) +{ + rt_err_t ret = RT_EOK; + + nu_capture_t *nu_capture; + + RT_ASSERT(inputcapture != RT_NULL); + + nu_capture = (nu_capture_t *) inputcapture; + + /* Disable capture rising/falling edge interrupt */ + EPWM_DisableCaptureInt(nu_capture->epwm, nu_capture->u8Channel, EPWM_CAPTURE_INT_FALLING_LATCH | EPWM_CAPTURE_INT_RISING_LATCH); + + /* Disable EPWM NVIC interrupt */ + NVIC_DisableIRQ(nu_capture->irq); + + /* Enable EPWM Timer */ + EPWM_Stop(nu_capture->epwm, 0x1 << nu_capture->u8Channel); + return ret; +} + +/* Init and register epwm capture */ +int nu_epwm_capture_device_init(void) +{ + /* Init EPWM0 6 channel and EPWM1 6 channel */ +#if (BSP_USING_EPWM0_CAPTURE_CHMSK!=0) + for (int i = 0; i < EPWM_CHANNEL_NUM; i++) + { + if (BSP_USING_EPWM0_CAPTURE_CHMSK & (0x1 << i)) + { + nu_epwm0_capture[i].epwm = EPWM0; + nu_epwm0_capture[i].u8Channel = i; + nu_epwm0_capture[i].irq = nu_epwm0_irq[i / 2]; + nu_epwm0_capture[i].u32CurrentRisingCnt = 0; + nu_epwm0_capture[i].u32CurrentFallingCnt = 0; + nu_epwm0_capture[i].parent.ops = &nu_capture_ops; + + /* register inputcapture device */ + rt_device_inputcapture_register(&nu_epwm0_capture[i].parent, nu_epwm0_device_name[i], &nu_epwm0_capture[i]); + + } + } +#endif //#if (BSP_USING_EPWM0_CAPTURE_CHMSK!=0) +#if (BSP_USING_EPWM1_CAPTURE_CHMSK!=0) + for (int i = 0; i < EPWM_CHANNEL_NUM; i++) + { + if (BSP_USING_EPWM1_CAPTURE_CHMSK & (0x1 << i)) + { + nu_epwm1_capture[i].epwm = EPWM1; + nu_epwm1_capture[i].u8Channel = i; + nu_epwm1_capture[i].irq = nu_epwm1_irq[i / 2]; + nu_epwm1_capture[i].u32CurrentRisingCnt = 0; + nu_epwm1_capture[i].u32CurrentFallingCnt = 0; + nu_epwm1_capture[i].parent.ops = &nu_capture_ops; + + /* register inputcapture device */ + rt_device_inputcapture_register(&nu_epwm1_capture[i].parent, nu_epwm1_device_name[i], &nu_epwm1_capture[i]); + } + } +#endif //#if (BSP_USING_EPWM1_CAPTURE_CHMSK!=0) + return 0; + +} +INIT_DEVICE_EXPORT(nu_epwm_capture_device_init); + +#endif //#if defined(BSP_USING_EPWM_CAPTURE) diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_fmc.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_fmc.c new file mode 100644 index 0000000000000000000000000000000000000000..79e66dbac0d7f7d5f322cf75e411c5f5d2c94342 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_fmc.c @@ -0,0 +1,322 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-3-03 FYChou First version +* +******************************************************************************/ + +#include + +#if defined(BSP_USING_FMC) +#include +#include "NuMicro.h" + +#if defined(PKG_USING_FAL) + #include +#endif + +/* Private define ---------------------------------------------------------------*/ +#define NU_GETBYTE_OFST(addr) ((addr&0x3)*8) +#define NU_GET_WALIGN(addr) (addr&~0x3) +#define NU_GET_LSB2BIT(addr) (addr&0x3) +/* Private typedef --------------------------------------------------------------*/ + +/* Private functions ------------------------------------------------------------*/ +static int nu_fmc_init(void); +#if defined(PKG_USING_FAL) + static int aprom_read(long offset, uint8_t *buf, size_t size); + static int aprom_write(long offset, const uint8_t *buf, size_t size); + static int aprom_erase(long offset, size_t size); + + static int ldrom_read(long offset, uint8_t *buf, size_t size); + static int ldrom_write(long offset, const uint8_t *buf, size_t size); + static int ldrom_erase(long offset, size_t size); +#endif /* PKG_USING_FAL */ + +/* Public functions -------------------------------------------------------------*/ +int nu_fmc_read(long offset, uint8_t *buf, size_t size); +int nu_fmc_write(long offset, const uint8_t *buf, size_t size); +int nu_fmc_erase(long offset, size_t size); + +/* Private variables ------------------------------------------------------------*/ +static rt_mutex_t g_mutex_fmc = RT_NULL; + +/* Public variables -------------------------------------------------------------*/ +#if defined(PKG_USING_FAL) +const struct fal_flash_dev Onchip_aprom_flash = { "OnChip_APROM", FMC_APROM_BASE, FMC_APROM_END, FMC_FLASH_PAGE_SIZE, {NULL, aprom_read, aprom_write, aprom_erase} }; +const struct fal_flash_dev Onchip_ldrom_flash = { "OnChip_LDROM", FMC_LDROM_BASE, FMC_LDROM_END, FMC_FLASH_PAGE_SIZE, {NULL, ldrom_read, ldrom_write, ldrom_erase} }; +#endif /* PKG_USING_FAL */ + +int nu_fmc_read(long addr, uint8_t *buf, size_t size) +{ + size_t read_size = 0; + uint32_t addr_end = addr + size; + uint32_t isp_rdata = 0; + rt_mutex_take(g_mutex_fmc, RT_WAITING_FOREVER); + SYS_UnlockReg(); + + if (NU_GET_LSB2BIT(addr)) + isp_rdata = FMC_Read(NU_GET_WALIGN(addr)); + + + for (; addr < addr_end ;) + { + if (NU_GET_LSB2BIT(addr) == 0) + { + isp_rdata = FMC_Read(addr); + if (addr_end - addr >= 4) + { + *(uint32_t *)buf = isp_rdata; + addr += 4; + buf += 4; + read_size += 4; + continue; + } + } + + *buf = isp_rdata >> NU_GETBYTE_OFST(addr); + addr++; + buf++; + read_size++; + + } + + SYS_LockReg(); + rt_mutex_release(g_mutex_fmc); + + return read_size; +} + +int nu_fmc_write(long addr, const uint8_t *buf, size_t size) +{ + size_t write_size = 0; + uint32_t addr_end = addr + size; + uint32_t isp_rdata = 0; + + rt_mutex_take(g_mutex_fmc, RT_WAITING_FOREVER); + SYS_UnlockReg(); + + if (addr < FMC_APROM_END) + FMC_ENABLE_AP_UPDATE(); + else if ((addr < FMC_LDROM_END) && addr >= FMC_LDROM_BASE) + FMC_ENABLE_LD_UPDATE(); + else + { + goto Exit2; + } + + if (NU_GET_LSB2BIT(addr)) + isp_rdata = FMC_Read(NU_GET_WALIGN(addr)); + + for (; addr < addr_end ;) + { + + if (addr_end - addr >= 4 && NU_GET_LSB2BIT(addr) == 0) + { + FMC_Write(addr, *((uint32_t *)buf)); + addr += 4; + buf += 4; + write_size += 4; + continue; + } + + if ((NU_GET_LSB2BIT(addr)) == 0x0) + isp_rdata = FMC_Read(NU_GET_WALIGN(addr)); + + isp_rdata = (isp_rdata & ~(0xFF << NU_GETBYTE_OFST(addr))) | ((*buf) << NU_GETBYTE_OFST(addr)); + + if ((NU_GET_LSB2BIT(addr)) == 0x3) + FMC_Write(NU_GET_WALIGN(addr), isp_rdata); + + addr++; + buf++; + write_size++; + + } + + if (NU_GET_LSB2BIT(addr)) + FMC_Write(NU_GET_WALIGN(addr), isp_rdata); + + FMC_DISABLE_AP_UPDATE(); + FMC_DISABLE_LD_UPDATE(); +Exit2: + SYS_LockReg(); + rt_mutex_release(g_mutex_fmc); + + return write_size; + +} + +int nu_fmc_erase(long addr, size_t size) +{ + size_t erased_size = 0; + uint32_t addrptr; + uint32_t addr_end = addr + size; + +#if defined(NU_SUPPORT_NONALIGN) + uint8_t *page_sdtemp = RT_NULL, *page_edtemp = RT_NULL; + + + addrptr = addr & (FMC_FLASH_PAGE_SIZE - 1); + if (addrptr) + { + page_sdtemp = rt_malloc(addrptr); + if (page_sdtemp == RT_NULL) + { + erased_size = 0; + + goto Exit3; + } + + if (nu_fmc_read(addr & ~(FMC_FLASH_PAGE_SIZE - 1), page_sdtemp, addrptr) != addrptr) + { + + erased_size = 0; + + goto Exit3; + } + + } + + addrptr = addr_end & (FMC_FLASH_PAGE_SIZE - 1); + if (addrptr) + { + page_edtemp = rt_malloc(FMC_FLASH_PAGE_SIZE - addrptr); + if (page_edtemp == RT_NULL) + { + erased_size = 0; + + goto Exit3; + } + + if (nu_fmc_read(addr_end, page_edtemp, FMC_FLASH_PAGE_SIZE - addrptr) != FMC_FLASH_PAGE_SIZE - addrptr) + { + erased_size = 0; + + goto Exit3; + } + + } +#endif + + rt_mutex_take(g_mutex_fmc, RT_WAITING_FOREVER); + SYS_UnlockReg(); + + if (addr <= FMC_APROM_END) + FMC_ENABLE_AP_UPDATE(); + else if ((addr < FMC_LDROM_END) && addr >= FMC_LDROM_BASE) + FMC_ENABLE_LD_UPDATE(); + else + { + goto Exit2; + } + + addrptr = (addr & ~(FMC_FLASH_PAGE_SIZE - 1)); + while (addrptr < addr_end) + { + if (FMC_Erase(addrptr) != RT_EOK) + { + goto Exit1; + } + erased_size += FMC_FLASH_PAGE_SIZE; + addrptr += FMC_FLASH_PAGE_SIZE; + } + +Exit1: + FMC_DISABLE_AP_UPDATE(); + FMC_DISABLE_LD_UPDATE(); +Exit2: + SYS_LockReg(); + rt_mutex_release(g_mutex_fmc); + +#if defined(NU_SUPPORT_NONALIGN) + + if (erased_size >= size) + { + addrptr = addr & (FMC_FLASH_PAGE_SIZE - 1); + if (addrptr) + { + if (nu_fmc_write(addr & ~(FMC_FLASH_PAGE_SIZE - 1), page_sdtemp, addrptr) != addrptr) + goto Exit3; + + erased_size += addrptr; + } + + addrptr = addr_end & (FMC_FLASH_PAGE_SIZE - 1); + if (addrptr) + { + + if (nu_fmc_write(addr_end, page_edtemp, FMC_FLASH_PAGE_SIZE - addrptr) != FMC_FLASH_PAGE_SIZE - addrptr) + goto Exit3; + + erased_size += FMC_FLASH_PAGE_SIZE - addrptr; + + } + } + else + erased_size = 0; + + +Exit3: + if (page_sdtemp != RT_NULL) + rt_free(page_sdtemp); + + if (page_edtemp != RT_NULL) + rt_free(page_edtemp); +#endif + + return erased_size; +} + +#if defined(PKG_USING_FAL) + +static int aprom_read(long offset, uint8_t *buf, size_t size) +{ + return nu_fmc_read(Onchip_aprom_flash.addr + offset, buf, size); +} + +static int aprom_write(long offset, const uint8_t *buf, size_t size) +{ + return nu_fmc_write(Onchip_aprom_flash.addr + offset, buf, size); +} + +static int aprom_erase(long offset, size_t size) +{ + return nu_fmc_erase(Onchip_aprom_flash.addr + offset, size); +} + +static int ldrom_read(long offset, uint8_t *buf, size_t size) +{ + return nu_fmc_read(Onchip_ldrom_flash.addr + offset, buf, size); +} + +static int ldrom_write(long offset, const uint8_t *buf, size_t size) +{ + return nu_fmc_write(Onchip_ldrom_flash.addr + offset, buf, size); +} + +static int ldrom_erase(long offset, size_t size) +{ + return nu_fmc_erase(Onchip_ldrom_flash.addr + offset, size); +} + +#endif /* PKG_USING_FAL */ + +static int nu_fmc_init(void) +{ + SYS_UnlockReg(); + FMC_ENABLE_ISP(); + SYS_LockReg(); + + g_mutex_fmc = rt_mutex_create("nu_fmc_lock", RT_IPC_FLAG_FIFO); + + return RT_EOK; +} +INIT_APP_EXPORT(nu_fmc_init); + +#endif /* BSP_USING_FMC */ diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_fmc.h b/bsp/nuvoton/libraries/m480/rtt_port/drv_fmc.h new file mode 100644 index 0000000000000000000000000000000000000000..9a9ef373c3acc81c67c00cd831ad4df519b01015 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_fmc.h @@ -0,0 +1,24 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-3-03 FYChou First version +* +******************************************************************************/ + +#ifndef __DRV_FMC_H__ +#define __DRV_FMC_H__ + +#include +#include + +int nu_fmc_read(long offset, uint8_t *buf, size_t size); +int nu_fmc_write(long offset, const uint8_t *buf, size_t size); +int nu_fmc_erase(long offset, size_t size); + + +#endif // __DRV_FMC_H___ diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_gpio.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_gpio.c new file mode 100644 index 0000000000000000000000000000000000000000..4790d6500142bf7b629217dcc146d042352ddc3d --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_gpio.c @@ -0,0 +1,394 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-2-7 YCHuang12 First version +* +******************************************************************************/ + +#include + +#if (defined(BSP_USING_GPIO) && defined(RT_USING_PIN)) + +#include +#include +#include +#include +#include + +/* Private define ---------------------------------------------------------------*/ + +#define PORT_OFFSET 0x40 +#define IRQ_MAX_NUM 16 //Max support 32 +#define MAX_PORTH_PIN_MAX 11 + +/* Private functions ------------------------------------------------------------*/ + +static void nu_gpio_mode(struct rt_device *device, rt_base_t pin, rt_base_t mode); +static void nu_gpio_write(struct rt_device *device, rt_base_t pin, rt_base_t value); +static int nu_gpio_read(struct rt_device *device, rt_base_t pin); +static rt_err_t nu_gpio_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args); +static rt_err_t nu_gpio_detach_irq(struct rt_device *device, rt_int32_t pin); +static rt_err_t nu_gpio_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled); + +/* Private variables ------------------------------------------------------------*/ +static struct rt_pin_irq_hdr pin_irq_hdr_tab[IRQ_MAX_NUM]; +static struct rt_pin_ops nu_gpio_ops = +{ + nu_gpio_mode, + nu_gpio_write, + nu_gpio_read, + nu_gpio_attach_irq, + nu_gpio_detach_irq, + nu_gpio_irq_enable +}; + +static IRQn_Type au32GPIRQ[NU_PORT_CNT] = {GPA_IRQn, GPB_IRQn, GPC_IRQn, GPD_IRQn, GPE_IRQn, GPF_IRQn, GPG_IRQn, GPH_IRQn}; + +static rt_uint32_t g_u32PinIrqMask = 0x0; + +/* Functions define ------------------------------------------------------------*/ + +static rt_err_t nu_port_check(rt_int32_t pin) +{ + if (NU_GET_PORT(pin) >= NU_PORT_CNT) + return -(RT_ERROR); + else if ((NU_GET_PORT(pin) == NU_PH) && (NU_GET_PINS(pin) > MAX_PORTH_PIN_MAX)) + return -(RT_ERROR); + + return RT_EOK; +} + +static rt_int32_t nu_find_irqindex(rt_uint32_t pin_index) +{ + rt_int32_t irqindex; + rt_int32_t u32PinIrqStatus = g_u32PinIrqMask; + + // Find index of pin is attached in pool. + while ((irqindex = nu_ctz(u32PinIrqStatus)) < IRQ_MAX_NUM) // Count Trailing Zeros ==> Find First One + { + if (pin_irq_hdr_tab[irqindex].pin == pin_index) + return irqindex; + + u32PinIrqStatus &= ~(1 << irqindex); + } + + return -(RT_ERROR); +} + +static void pin_irq_hdr(rt_uint32_t irq_status, rt_uint32_t port_index) +{ + rt_int32_t irqindex, i; + rt_int32_t pinindex = port_index * GPIO_PIN_MAX ; + + while ((i = nu_ctz(irq_status)) < GPIO_PIN_MAX)// Count Trailing Zeros ==> Find First One + { + int pin_mask = (1 << i); + irqindex = nu_find_irqindex(pinindex + i); + if (irqindex != -(RT_ERROR)) + { + if (pin_irq_hdr_tab[irqindex].hdr) + { + pin_irq_hdr_tab[irqindex].hdr(pin_irq_hdr_tab[irqindex].args); + } + } + // Clear the served bit. + irq_status &= ~pin_mask; + } +} + +static void nu_gpio_mode(struct rt_device *device, rt_base_t pin, rt_base_t mode) +{ + GPIO_T *PORT; + + if (nu_port_check(pin)) + return; + + PORT = (GPIO_T *)(GPIOA_BASE + (NU_GET_PORT(pin) * PORT_OFFSET)); + + if (mode == PIN_MODE_INPUT_PULLUP) + { + GPIO_SetMode(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_MODE_INPUT); + GPIO_SetPullCtl(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_PUSEL_PULL_UP); + } + else if (mode == PIN_MODE_INPUT_PULLDOWN) + { + GPIO_SetMode(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_MODE_INPUT); + GPIO_SetPullCtl(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_PUSEL_PULL_DOWN); + } + else if (mode == PIN_MODE_OUTPUT) + { + GPIO_SetMode(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_MODE_OUTPUT); + } + else if (mode == PIN_MODE_INPUT) + { + GPIO_SetMode(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_MODE_INPUT); + GPIO_SetPullCtl(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_PUSEL_DISABLE); + } + else if (mode == PIN_MODE_OUTPUT_OD) + { + GPIO_SetMode(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_MODE_OPEN_DRAIN); + GPIO_SetPullCtl(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_PUSEL_DISABLE); + } +} + +static void nu_gpio_write(struct rt_device *device, rt_base_t pin, rt_base_t value) +{ + if (nu_port_check(pin)) + return; + + GPIO_PIN_DATA(NU_GET_PORT(pin), NU_GET_PINS(pin)) = value; +} + +static int nu_gpio_read(struct rt_device *device, rt_base_t pin) +{ + if (nu_port_check(pin)) + return PIN_LOW; + + return GPIO_PIN_DATA(NU_GET_PORT(pin), NU_GET_PINS(pin)); +} + +static rt_err_t nu_gpio_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + rt_base_t level; + rt_int32_t irqindex; + + if (nu_port_check(pin)) + return -(RT_ERROR); + + level = rt_hw_interrupt_disable(); + + // Find index of pin is attached in pool. + if ((irqindex = nu_find_irqindex(pin)) >= 0) + goto exit_nu_gpio_attach_irq; + + // Find avaiable index of pin in pool. + if ((irqindex = nu_cto(g_u32PinIrqMask)) < IRQ_MAX_NUM) // Count Trailing Ones ==> Find First Zero + goto exit_nu_gpio_attach_irq; + + rt_hw_interrupt_enable(level); + + return -(RT_EBUSY); + +exit_nu_gpio_attach_irq: + + pin_irq_hdr_tab[irqindex].pin = pin; + pin_irq_hdr_tab[irqindex].hdr = hdr; + pin_irq_hdr_tab[irqindex].mode = mode; + pin_irq_hdr_tab[irqindex].args = args; + + g_u32PinIrqMask |= (1 << irqindex); + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t nu_gpio_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + rt_base_t level; + rt_int32_t irqindex; + rt_int32_t u32PinIrqStatus; + + if (nu_port_check(pin)) + return -(RT_ERROR); + + level = rt_hw_interrupt_disable(); + + u32PinIrqStatus = g_u32PinIrqMask; + + // Find index of pin is attached in pool. + while ((irqindex = nu_ctz(u32PinIrqStatus)) < IRQ_MAX_NUM)// Count Trailing Zeros ==> Find First One + { + if (pin_irq_hdr_tab[irqindex].pin == pin) + { + pin_irq_hdr_tab[irqindex].pin = PIN_IRQ_PIN_NONE; + pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + pin_irq_hdr_tab[irqindex].mode = PIN_IRQ_MODE_RISING; + pin_irq_hdr_tab[irqindex].args = RT_NULL; + g_u32PinIrqMask &= ~(1 << irqindex); + break; + } + u32PinIrqStatus &= ~(1 << irqindex); + } + + rt_hw_interrupt_enable(level); + return RT_EOK; +} + +static rt_err_t nu_gpio_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) +{ + GPIO_T *PORT; + rt_base_t level; + uint32_t u32IntAttribs; + rt_int32_t irqindex; + rt_err_t ret = RT_EOK; + + if (nu_port_check(pin)) + return -(RT_ERROR); + + level = rt_hw_interrupt_disable(); + + irqindex = nu_find_irqindex(pin); + if (irqindex == -(RT_ERROR)) + { + ret = RT_ERROR; + goto exit_nu_gpio_irq_enable; + } + + PORT = (GPIO_T *)(GPIOA_BASE + (NU_GET_PORT(pin) * PORT_OFFSET)); + + if (enabled == PIN_IRQ_ENABLE) + { + if (pin_irq_hdr_tab[irqindex].mode == PIN_IRQ_MODE_RISING) + u32IntAttribs = GPIO_INT_RISING; + else if (pin_irq_hdr_tab[irqindex].mode == PIN_IRQ_MODE_FALLING) + u32IntAttribs = GPIO_INT_FALLING; + else if (pin_irq_hdr_tab[irqindex].mode == PIN_IRQ_MODE_RISING_FALLING) + u32IntAttribs = GPIO_INT_BOTH_EDGE; + else if (pin_irq_hdr_tab[irqindex].mode == PIN_IRQ_MODE_HIGH_LEVEL) + u32IntAttribs = GPIO_INT_HIGH; + else if (pin_irq_hdr_tab[irqindex].mode == PIN_IRQ_MODE_LOW_LEVEL) + u32IntAttribs = GPIO_INT_LOW; + else + goto exit_nu_gpio_irq_enable; + + GPIO_EnableInt(PORT, NU_GET_PINS(pin), u32IntAttribs); + + NVIC_EnableIRQ(au32GPIRQ[NU_GET_PORT(pin)]); + } + else + { + GPIO_DisableInt(PORT, NU_GET_PINS(pin)); + } + +exit_nu_gpio_irq_enable: + + rt_hw_interrupt_enable(level); + return -(ret); +} + +int rt_hw_gpio_init(void) +{ + rt_int32_t irqindex; + for (irqindex = 0; irqindex < IRQ_MAX_NUM ; irqindex++) + { + pin_irq_hdr_tab[irqindex].pin = PIN_IRQ_PIN_NONE; + pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + pin_irq_hdr_tab[irqindex].mode = PIN_IRQ_MODE_RISING; + pin_irq_hdr_tab[irqindex].args = RT_NULL; + } + + return rt_device_pin_register("gpio", &nu_gpio_ops, RT_NULL); +} + +INIT_BOARD_EXPORT(rt_hw_gpio_init); + +void GPA_IRQHandler(void) +{ + rt_uint32_t int_status; + + rt_interrupt_enter(); + + int_status = PA->INTSRC; + pin_irq_hdr(int_status, NU_PA); + PA->INTSRC = int_status; + + rt_interrupt_leave(); +} + +void GPB_IRQHandler(void) +{ + rt_uint32_t int_status; + + rt_interrupt_enter(); + + int_status = PB->INTSRC; + pin_irq_hdr(int_status, NU_PB); + PB->INTSRC = int_status; + + rt_interrupt_leave(); +} + +void GPC_IRQHandler(void) +{ + rt_uint32_t int_status; + + rt_interrupt_enter(); + + int_status = PC->INTSRC; + pin_irq_hdr(int_status, NU_PC); + PC->INTSRC = int_status; + + rt_interrupt_leave(); +} + +void GPD_IRQHandler(void) +{ + rt_uint32_t int_status; + + rt_interrupt_enter(); + + int_status = PD->INTSRC; + pin_irq_hdr(int_status, NU_PD); + PD->INTSRC = int_status; + + rt_interrupt_leave(); +} + +void GPE_IRQHandler(void) +{ + rt_uint32_t int_status; + + rt_interrupt_enter(); + + int_status = PE->INTSRC; + pin_irq_hdr(int_status, NU_PE); + PE->INTSRC = int_status; + + rt_interrupt_leave(); +} + +void GPF_IRQHandler(void) +{ + rt_uint32_t int_status; + + rt_interrupt_enter(); + + int_status = PF->INTSRC; + pin_irq_hdr(int_status, NU_PF); + PF->INTSRC = int_status; + + rt_interrupt_leave(); +} + +void GPG_IRQHandler(void) +{ + rt_uint32_t int_status; + + rt_interrupt_enter(); + + int_status = PG->INTSRC; + pin_irq_hdr(int_status, NU_PG); + PG->INTSRC = int_status; + + rt_interrupt_leave(); +} + +void GPH_IRQHandler(void) +{ + rt_uint32_t int_status; + + rt_interrupt_enter(); + + int_status = PH->INTSRC; + pin_irq_hdr(int_status, NU_PH); + PH->INTSRC = int_status; + + rt_interrupt_leave(); +} + +#endif //#if (defined(BSP_USING_GPIO) && defined(RT_USING_PIN)) diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_gpio.h b/bsp/nuvoton/libraries/m480/rtt_port/drv_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..c353a1e772551080bf1f0776f3c552bac9c7a773 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_gpio.h @@ -0,0 +1,34 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-2-7 YCHuang12 First version +* +******************************************************************************/ + +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ + +typedef enum +{ + NU_PA, + NU_PB, + NU_PC, + NU_PD, + NU_PE, + NU_PF, + NU_PG, + NU_PH, + NU_PORT_CNT, +} nu_gpio_port; + +#define NU_GET_PININDEX(port, pin) (port*16+pin) +#define NU_GET_PINS(rt_pin_index) ((rt_pin_index) & 0x0000000F) +#define NU_GET_PORT(rt_pin_index) (((rt_pin_index)>>4) & 0x0000000F) +#define NU_GET_PIN_MASK(nu_gpio_pin) (1 << (nu_gpio_pin)) + +#endif //__DRV_GPIO_H__ diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_hsotg.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_hsotg.c new file mode 100644 index 0000000000000000000000000000000000000000..17244d5e0a0a52be7713f21dc1d16db4cf4dd2ce --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_hsotg.c @@ -0,0 +1,125 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-05-22 klcheng First version +* +******************************************************************************/ +#include + +#if defined(BSP_USING_HSOTG) +#include +#include +#include + + +/* This delay must be at least 10 us */ +static void _usb_init_delay(void) +{ + volatile uint32_t i = 0x1000; + + while (i--) + __NOP(); + + return; +} + +/* Check current usb role */ +static void usb_role(void) +{ + uint32_t status; + + status = (HSOTG->STATUS) & (HSOTG_STATUS_ASHOST_Msk | HSOTG_STATUS_ASPERI_Msk | HSOTG_STATUS_IDSTS_Msk); + + if (status == (HSOTG_STATUS_IDSTS_Msk | HSOTG_STATUS_ASPERI_Msk)) + rt_kprintf("usb frame acts as peripheral\n"); + + else if (status == HSOTG_STATUS_ASHOST_Msk) + rt_kprintf("usb frame acts as host\n"); + + else + rt_kprintf("usb frame is unknown state: 0x%x\n", status); + + return; +} +MSH_CMD_EXPORT_ALIAS(usb_role, usb_role, check usb role); + + +static int hsotg_init(void) +{ + SYS_UnlockReg(); + + /* Set HSOTG as ID dependent role */ + SYS->USBPHY = SYS_USBPHY_HSUSBEN_Msk | (0x2 << SYS_USBPHY_HSUSBROLE_Pos); + + /* user should keep HSUSB PHY at reset mode at lease 10 us before changing to active mode */ + _usb_init_delay(); + SYS->USBPHY |= SYS_USBPHY_HSUSBACT_Msk; + + /* Enable OTG and ID detection function */ + HSOTG_ENABLE_PHY(); + HSOTG_ENABLE_ID_DETECT(); + NVIC_EnableIRQ(USBOTG20_IRQn); + + /* clear interrupt and enable relative interrupts */ + HSOTG_ENABLE_INT(HSOTG_INTEN_IDCHGIEN_Msk | HSOTG_INTEN_HOSTIEN_Msk | HSOTG_INTEN_PDEVIEN_Msk | + HSOTG_INTEN_BVLDCHGIEN_Msk | HSOTG_INTEN_AVLDCHGIEN_Msk); + + SYS_LockReg(); + + return (int)RT_EOK; +} +INIT_DEVICE_EXPORT(hsotg_init); + + +/* HSOTG interrupt entry */ +void USBOTG20_IRQHandler(void) +{ + __IO uint32_t reg; + + reg = HSOTG->INTSTS; + + /* usb id pin status change */ + if (reg & HSOTG_INTSTS_IDCHGIF_Msk) + { + HSOTG_CLR_INT_FLAG(HSOTG_INTSTS_IDCHGIF_Msk); + LOG_D("usb id change"); + } + + /* usb acts as host */ + if (reg & HSOTG_INTSTS_HOSTIF_Msk) + { + HSOTG_CLR_INT_FLAG(HSOTG_INTSTS_HOSTIF_Msk); + LOG_D("usb acts as host"); + } + + /* usb acts as peripheral */ + if (reg & HSOTG_INTSTS_PDEVIF_Msk) + { + HSOTG_CLR_INT_FLAG(HSOTG_INTSTS_PDEVIF_Msk); + LOG_D("usb acts as peripheral"); + } + + /* A-device session valid state change */ + if (reg & HSOTG_INTSTS_AVLDCHGIF_Msk) + { + HSOTG_CLR_INT_FLAG(HSOTG_INTSTS_AVLDCHGIF_Msk); + LOG_D("usb a-device session valid state change"); + } + + /* B-device session valid state change */ + if (reg & HSOTG_INTSTS_BVLDCHGIF_Msk) + { + HSOTG_CLR_INT_FLAG(HSOTG_INTSTS_BVLDCHGIF_Msk); + LOG_D("usb b-device session valid state change"); + } +} + +#endif /* defined(BSP_USING_HSOTG) */ + + + diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_hsusbd.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_hsusbd.c new file mode 100644 index 0000000000000000000000000000000000000000..47329cc294bf36a2d0e42f29d6c5f71e3eec7bc1 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_hsusbd.c @@ -0,0 +1,974 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-5-26 Egbert First version +* +******************************************************************************/ + + +#include + +#ifdef BSP_USING_HSUSBD +#include +#include +#include +#include "NuMicro.h" + + +#define LOG_TAG "drv.hsusbd" +#define DBG_ENABLE +#define DBG_SECTION_NAME "drv.hsusbd" +#define DBG_LEVEL DBG_ERROR +#define DBG_COLOR +#include + +/* Private define ---------------------------------------------------------------*/ +#define ENABLE_FULL_SPEED_MODE_ONLY 0 /* 0: default hi-speed mode; 1: full-speed mode only */ + +/* Define EP maximum packet size */ +#define CEP_MAX_PKT_SIZE 64 +#define CEP_OTHER_MAX_PKT_SIZE 64 + +#define EPA_MAX_PKT_SIZE 512 +#define EPA_OTHER_MAX_PKT_SIZE 64 + +#define EPB_MAX_PKT_SIZE 512 +#define EPB_OTHER_MAX_PKT_SIZE 64 + +#define EPC_MAX_PKT_SIZE 64 +#define EPC_OTHER_MAX_PKT_SIZE 64 + +#define EPD_MAX_PKT_SIZE 64 +#define EPD_OTHER_MAX_PKT_SIZE 64 + +#define EPE_MAX_PKT_SIZE 512 +#define EPE_OTHER_MAX_PKT_SIZE 64 + +#define EPF_MAX_PKT_SIZE 512 +#define EPF_OTHER_MAX_PKT_SIZE 64 + +#define EPG_MAX_PKT_SIZE 64 +#define EPG_OTHER_MAX_PKT_SIZE 64 + +#define EPH_MAX_PKT_SIZE 64 +#define EPH_OTHER_MAX_PKT_SIZE 64 + +#define CEP_BUF_BASE 0 +#define CEP_BUF_LEN CEP_MAX_PKT_SIZE +#define EPA_BUF_BASE (CEP_BUF_BASE + CEP_BUF_LEN) +#define EPA_BUF_LEN EPA_MAX_PKT_SIZE +#define EPB_BUF_BASE (EPA_BUF_BASE + EPA_BUF_LEN) +#define EPB_BUF_LEN EPB_MAX_PKT_SIZE +#define EPC_BUF_BASE (EPB_BUF_BASE + EPB_BUF_LEN) +#define EPC_BUF_LEN EPC_MAX_PKT_SIZE +#define EPD_BUF_BASE (EPC_BUF_BASE + EPC_BUF_LEN) +#define EPD_BUF_LEN EPD_MAX_PKT_SIZE +#define EPE_BUF_BASE (EPD_BUF_BASE + EPD_BUF_LEN) +#define EPE_BUF_LEN EPE_MAX_PKT_SIZE +#define EPF_BUF_BASE (EPE_BUF_BASE + EPE_BUF_LEN) +#define EPF_BUF_LEN EPF_MAX_PKT_SIZE +#define EPG_BUF_BASE (EPF_BUF_BASE + EPF_BUF_LEN) +#define EPG_BUF_LEN EPG_MAX_PKT_SIZE +#define EPH_BUF_BASE (EPG_BUF_BASE + EPG_BUF_LEN) +#define EPH_BUF_LEN EPH_MAX_PKT_SIZE + +#define EPADR_SW2HW(address) ((address & USB_EPNO_MASK) - 1) /* for non-control endpoint */ +#define EPADR_HW2SW(address) ((address & USB_EPNO_MASK) + 1) /* for non-control endpoint */ + +/* Private typedef --------------------------------------------------------------*/ +typedef struct _nu_usbd_t +{ + HSUSBD_T *Instance; /* REG base */ + uint8_t address_tmp; /* Keep assigned address for flow control */ +} nu_usbd_t; + + +/* Private variables ------------------------------------------------------------*/ +static nu_usbd_t nu_usbd = +{ + .Instance = HSUSBD, + .address_tmp = 0, +}; + +static struct udcd _rt_obj_udc; + +static struct ep_id _ep_pool[] = +{ + {0x0, USB_EP_ATTR_CONTROL, USB_DIR_INOUT, CEP_MAX_PKT_SIZE, ID_ASSIGNED }, + {EPADR_HW2SW(EPA), USB_EP_ATTR_BULK, USB_DIR_IN, EPA_MAX_PKT_SIZE, ID_UNASSIGNED}, + {EPADR_HW2SW(EPB), USB_EP_ATTR_BULK, USB_DIR_OUT, EPB_MAX_PKT_SIZE, ID_UNASSIGNED}, + {EPADR_HW2SW(EPC), USB_EP_ATTR_INT, USB_DIR_IN, EPC_MAX_PKT_SIZE, ID_UNASSIGNED}, + {EPADR_HW2SW(EPD), USB_EP_ATTR_INT, USB_DIR_OUT, EPD_MAX_PKT_SIZE, ID_UNASSIGNED}, + {EPADR_HW2SW(EPE), USB_EP_ATTR_BULK, USB_DIR_IN, EPE_MAX_PKT_SIZE, ID_UNASSIGNED}, + {EPADR_HW2SW(EPF), USB_EP_ATTR_BULK, USB_DIR_OUT, EPF_MAX_PKT_SIZE, ID_UNASSIGNED}, + {EPADR_HW2SW(EPG), USB_EP_ATTR_INT, USB_DIR_IN, EPG_MAX_PKT_SIZE, ID_UNASSIGNED}, + {EPADR_HW2SW(EPH), USB_EP_ATTR_INT, USB_DIR_OUT, EPH_MAX_PKT_SIZE, ID_UNASSIGNED}, + {0xFF, USB_EP_ATTR_TYPE_MASK, USB_DIR_MASK, 0, ID_ASSIGNED }, +}; + + +static void _nu_ep_partition_fs(void) +{ + /*****************************************************/ + /* EPA ==> Bulk IN endpoint, address 1 */ + HSUSBD_SetEpBufAddr(EPA, EPA_BUF_BASE, EPA_BUF_LEN); + HSUSBD_SET_MAX_PAYLOAD(EPA, EPA_OTHER_MAX_PKT_SIZE); + HSUSBD_ConfigEp(EPA, EPADR_HW2SW(EPA), HSUSBD_EP_CFG_TYPE_BULK, HSUSBD_EP_CFG_DIR_IN); + + + /* EPB ==> Bulk OUT endpoint, address 2 */ + HSUSBD_SetEpBufAddr(EPB, EPB_BUF_BASE, EPB_BUF_LEN); + HSUSBD_SET_MAX_PAYLOAD(EPB, EPB_OTHER_MAX_PKT_SIZE); + HSUSBD_ConfigEp(EPB, EPADR_HW2SW(EPB), HSUSBD_EP_CFG_TYPE_BULK, HSUSBD_EP_CFG_DIR_OUT); + HSUSBD_ENABLE_EP_INT(EPB, HSUSBD_EPINTEN_RXPKIEN_Msk); + + /*****************************************************/ + /* EPC ==> Interrupt IN endpoint, address 3 */ + HSUSBD_SetEpBufAddr(EPC, EPC_BUF_BASE, EPC_BUF_LEN); + HSUSBD_SET_MAX_PAYLOAD(EPC, EPC_OTHER_MAX_PKT_SIZE); + HSUSBD_ConfigEp(EPC, EPADR_HW2SW(EPC), HSUSBD_EP_CFG_TYPE_INT, HSUSBD_EP_CFG_DIR_IN); + + /* EPD ==> Interrupt OUT endpoint, address 4 */ + HSUSBD_SetEpBufAddr(EPD, EPD_BUF_BASE, EPD_BUF_LEN); + HSUSBD_SET_MAX_PAYLOAD(EPD, EPD_OTHER_MAX_PKT_SIZE); + HSUSBD_ConfigEp(EPD, EPADR_HW2SW(EPD), HSUSBD_EP_CFG_TYPE_INT, HSUSBD_EP_CFG_DIR_OUT); + HSUSBD_ENABLE_EP_INT(EPD, HSUSBD_EPINTEN_RXPKIEN_Msk); + + /*****************************************************/ + /* EPE ==> Bulk IN endpoint, address 5 */ + HSUSBD_SetEpBufAddr(EPE, EPE_BUF_BASE, EPE_BUF_LEN); + HSUSBD_SET_MAX_PAYLOAD(EPE, EPE_OTHER_MAX_PKT_SIZE); + HSUSBD_ConfigEp(EPE, EPADR_HW2SW(EPE), HSUSBD_EP_CFG_TYPE_BULK, HSUSBD_EP_CFG_DIR_IN); + + + /* EPF ==> Bulk OUT endpoint, address 6 */ + HSUSBD_SetEpBufAddr(EPF, EPF_BUF_BASE, EPF_BUF_LEN); + HSUSBD_SET_MAX_PAYLOAD(EPF, EPF_OTHER_MAX_PKT_SIZE); + HSUSBD_ConfigEp(EPF, EPADR_HW2SW(EPF), HSUSBD_EP_CFG_TYPE_BULK, HSUSBD_EP_CFG_DIR_OUT); + HSUSBD_ENABLE_EP_INT(EPF, HSUSBD_EPINTEN_RXPKIEN_Msk); + + /*****************************************************/ + /* EPG ==> Interrupt IN endpoint, address 7 */ + HSUSBD_SetEpBufAddr(EPG, EPG_BUF_BASE, EPG_BUF_LEN); + HSUSBD_SET_MAX_PAYLOAD(EPG, EPG_OTHER_MAX_PKT_SIZE); + HSUSBD_ConfigEp(EPG, EPADR_HW2SW(EPG), HSUSBD_EP_CFG_TYPE_INT, HSUSBD_EP_CFG_DIR_IN); + + /* EPH ==> Interrupt OUT endpoint, address 8 */ + HSUSBD_SetEpBufAddr(EPH, EPH_BUF_BASE, EPH_BUF_LEN); + HSUSBD_SET_MAX_PAYLOAD(EPH, EPH_OTHER_MAX_PKT_SIZE); + HSUSBD_ConfigEp(EPH, EPADR_HW2SW(EPH), HSUSBD_EP_CFG_TYPE_INT, HSUSBD_EP_CFG_DIR_OUT); + HSUSBD_ENABLE_EP_INT(EPH, HSUSBD_EPINTEN_RXPKIEN_Msk); +} + +static void _nu_ep_partition_hs(void) +{ + /*****************************************************/ + /* EPA ==> Bulk IN endpoint, address 1 */ + HSUSBD_SetEpBufAddr(EPA, EPA_BUF_BASE, EPA_BUF_LEN); + HSUSBD_SET_MAX_PAYLOAD(EPA, EPA_MAX_PKT_SIZE); + HSUSBD_ConfigEp(EPA, EPADR_HW2SW(EPA), HSUSBD_EP_CFG_TYPE_BULK, HSUSBD_EP_CFG_DIR_IN); + + + /* EPB ==> Bulk OUT endpoint, address 2 */ + HSUSBD_SetEpBufAddr(EPB, EPB_BUF_BASE, EPB_BUF_LEN); + HSUSBD_SET_MAX_PAYLOAD(EPB, EPB_MAX_PKT_SIZE); + HSUSBD_ConfigEp(EPB, EPADR_HW2SW(EPB), HSUSBD_EP_CFG_TYPE_BULK, HSUSBD_EP_CFG_DIR_OUT); + HSUSBD_ENABLE_EP_INT(EPB, HSUSBD_EPINTEN_RXPKIEN_Msk); + + /*****************************************************/ + /* EPC ==> Interrupt IN endpoint, address 3 */ + HSUSBD_SetEpBufAddr(EPC, EPC_BUF_BASE, EPC_BUF_LEN); + HSUSBD_SET_MAX_PAYLOAD(EPC, EPC_MAX_PKT_SIZE); + HSUSBD_ConfigEp(EPC, EPADR_HW2SW(EPC), HSUSBD_EP_CFG_TYPE_INT, HSUSBD_EP_CFG_DIR_IN); + + /* EPD ==> Interrupt OUT endpoint, address 4 */ + HSUSBD_SetEpBufAddr(EPD, EPD_BUF_BASE, EPD_BUF_LEN); + HSUSBD_SET_MAX_PAYLOAD(EPD, EPD_MAX_PKT_SIZE); + HSUSBD_ConfigEp(EPD, EPADR_HW2SW(EPD), HSUSBD_EP_CFG_TYPE_INT, HSUSBD_EP_CFG_DIR_OUT); + HSUSBD_ENABLE_EP_INT(EPD, HSUSBD_EPINTEN_RXPKIEN_Msk); + + /*****************************************************/ + /* EPE ==> Bulk IN endpoint, address 5 */ + HSUSBD_SetEpBufAddr(EPE, EPE_BUF_BASE, EPE_BUF_LEN); + HSUSBD_SET_MAX_PAYLOAD(EPE, EPE_MAX_PKT_SIZE); + HSUSBD_ConfigEp(EPE, EPADR_HW2SW(EPE), HSUSBD_EP_CFG_TYPE_BULK, HSUSBD_EP_CFG_DIR_IN); + + + /* EPF ==> Bulk OUT endpoint, address 6 */ + HSUSBD_SetEpBufAddr(EPF, EPF_BUF_BASE, EPF_BUF_LEN); + HSUSBD_SET_MAX_PAYLOAD(EPF, EPF_MAX_PKT_SIZE); + HSUSBD_ConfigEp(EPF, EPADR_HW2SW(EPF), HSUSBD_EP_CFG_TYPE_BULK, HSUSBD_EP_CFG_DIR_OUT); + HSUSBD_ENABLE_EP_INT(EPF, HSUSBD_EPINTEN_RXPKIEN_Msk); + + /*****************************************************/ + /* EPG ==> Interrupt IN endpoint, address 7 */ + HSUSBD_SetEpBufAddr(EPG, EPG_BUF_BASE, EPG_BUF_LEN); + HSUSBD_SET_MAX_PAYLOAD(EPG, EPG_MAX_PKT_SIZE); + HSUSBD_ConfigEp(EPG, EPADR_HW2SW(EPG), HSUSBD_EP_CFG_TYPE_INT, HSUSBD_EP_CFG_DIR_IN); + + /* EPH ==> Interrupt OUT endpoint, address 8 */ + HSUSBD_SetEpBufAddr(EPH, EPH_BUF_BASE, EPH_BUF_LEN); + HSUSBD_SET_MAX_PAYLOAD(EPH, EPH_MAX_PKT_SIZE); + HSUSBD_ConfigEp(EPH, EPADR_HW2SW(EPH), HSUSBD_EP_CFG_TYPE_INT, HSUSBD_EP_CFG_DIR_OUT); + HSUSBD_ENABLE_EP_INT(EPH, HSUSBD_EPINTEN_RXPKIEN_Msk); +} + +static void _nu_ep_partition(void) +{ + /* Configure USB controller */ + /* Enable USB BUS, CEP and EPA ~ EPH global interrupt */ + HSUSBD_ENABLE_USB_INT(HSUSBD_GINTEN_USBIEN_Msk + | HSUSBD_GINTEN_CEPIEN_Msk + | HSUSBD_GINTEN_EPAIEN_Msk + | HSUSBD_GINTEN_EPBIEN_Msk + | HSUSBD_GINTEN_EPCIEN_Msk + | HSUSBD_GINTEN_EPDIEN_Msk + | HSUSBD_GINTEN_EPEIEN_Msk + | HSUSBD_GINTEN_EPFIEN_Msk + | HSUSBD_GINTEN_EPGIEN_Msk + | HSUSBD_GINTEN_EPHIEN_Msk + ); + + /* Enable BUS interrupt */ + HSUSBD_ENABLE_BUS_INT(HSUSBD_BUSINTEN_DMADONEIEN_Msk + | HSUSBD_BUSINTEN_RESUMEIEN_Msk + | HSUSBD_BUSINTEN_RSTIEN_Msk + | HSUSBD_BUSINTEN_VBUSDETIEN_Msk); + /* Reset Address to 0 */ + HSUSBD_SET_ADDR(0); + + /*****************************************************/ + /* Control endpoint */ + HSUSBD_SetEpBufAddr(CEP, CEP_BUF_BASE, CEP_BUF_LEN); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_SETUPPKIEN_Msk + | HSUSBD_CEPINTEN_STSDONEIEN_Msk + ); + + _nu_ep_partition_hs(); +} + +static void NU_SetupStageCallback(nu_usbd_t *nu_udc) +{ + struct urequest setup_packet; + + /* Setup packet process */ + setup_packet.request_type = (uint8_t)(nu_udc->Instance->SETUP1_0 & 0xfful); + setup_packet.bRequest = (uint8_t)((nu_udc->Instance->SETUP1_0 >> 8) & 0xfful); + setup_packet.wValue = (uint16_t) nu_udc->Instance->SETUP3_2; + setup_packet.wIndex = (uint16_t) nu_udc->Instance->SETUP5_4; + setup_packet.wLength = (uint16_t) nu_udc->Instance->SETUP7_6; + + rt_usbd_ep0_setup_handler(&_rt_obj_udc, (struct urequest *)&setup_packet); +} + +static rt_err_t _ep_set_stall(rt_uint8_t address) +{ + + if (address & USB_EPNO_MASK) + { + HSUSBD_SetEpStall(EPADR_SW2HW(address)); + } + else + { + /* Not support. Reply STALL. */ + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALLEN_Msk); + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_SETUPPKIF_Msk); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_SETUPPKIEN_Msk); + } + return RT_EOK; +} + +static rt_err_t _ep_clear_stall(rt_uint8_t address) +{ + if (address & USB_EPNO_MASK) + { + HSUSBD_ClearEpStall(EPADR_SW2HW(address)); + } + + return RT_EOK; +} + + +static rt_err_t _set_address(rt_uint8_t address) +{ + if (0 != address) + { + nu_usbd.address_tmp = address; + } + + return RT_EOK; +} + +static rt_err_t _set_config(rt_uint8_t address) +{ + return RT_EOK; +} + +static rt_err_t _ep_enable(uep_t ep) +{ + RT_ASSERT(ep != RT_NULL); + RT_ASSERT(ep->ep_desc != RT_NULL); + + HSUSBD->EP[EPADR_SW2HW(ep->ep_desc->bEndpointAddress)].EPRSPCTL = HSUSBD_EP_RSPCTL_TOGGLE; + HSUSBD->EP[EPADR_SW2HW(ep->ep_desc->bEndpointAddress)].EPCFG |= HSUSBD_EP_CFG_VALID; + + return RT_EOK; +} + +static rt_err_t _ep_disable(uep_t ep) +{ + RT_ASSERT(ep != RT_NULL); + RT_ASSERT(ep->ep_desc != RT_NULL); + HSUSBD->EP[EPADR_SW2HW(ep->ep_desc->bEndpointAddress)].EPCFG &= ~HSUSBD_EP_CFG_VALID; + + return RT_EOK; +} + +static rt_err_t _ep0_send_status(void) +{ + /* Status Stage */ + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk + | HSUSBD_CEPINTSTS_SETUPPKIF_Msk + ); + + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_STSDONEIEN_Msk); + + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR); + + return RT_EOK; +} + +__STATIC_INLINE void nu_buffer_cpy(rt_uint8_t address, void *buffer, rt_size_t size) +{ + rt_uint32_t i, cnt; + rt_uint32_t *_buf_word; + rt_uint8_t *_buf_byte; + + _buf_word = (rt_uint32_t *)buffer; + cnt = size >> 2; + _buf_byte = (rt_uint8_t *)((rt_uint8_t *)buffer + (cnt * 4)); + + if ((address & USB_EPNO_MASK)) //EPs + { + if (address & USB_DIR_IN) //IN + { + /* Non-control endpoint IN*/ + for (i = 0; i < cnt; i++) + { + HSUSBD->EP[EPADR_SW2HW(address)].EPDAT = _buf_word[i]; + } + + for (i = 0ul; i < (size % 4ul); i++) + HSUSBD->EP[EPADR_SW2HW(address)].EPDAT_BYTE = _buf_byte[i]; + } + else //OUT + { + for (i = 0; i < cnt; i++) + { + _buf_word[i] = HSUSBD->EP[EPADR_SW2HW(address)].EPDAT; + } + + for (i = 0ul; i < (size % 4ul); i++) + _buf_byte[i] = HSUSBD->EP[EPADR_SW2HW(address)].EPDAT_BYTE; + } + } + else //Control + { + if (address & USB_DIR_IN) //IN + { + for (i = 0; i < cnt; i++) + { + HSUSBD->CEPDAT = _buf_word[i]; + } + + for (i = 0ul; i < (size % 4ul); i++) + HSUSBD->CEPDAT_BYTE = _buf_byte[i]; + + } + else //OUT + { + for (i = 0; i < cnt; i++) + { + _buf_word[i] = HSUSBD->CEPDAT; + } + + for (i = 0ul; i < (size % 4ul); i++) + _buf_byte[i] = HSUSBD->CEPDAT_BYTE; + } + } +} + +static rt_size_t _ep_read(rt_uint8_t address, void *buffer) +{ + rt_size_t size = 0; + + RT_ASSERT(!(address & USB_DIR_IN)); + + if ((address & USB_EPNO_MASK)) + { + RT_ASSERT(buffer != RT_NULL); + size = HSUSBD->EP[EPADR_SW2HW(address)].EPDATCNT & 0xffff; + nu_buffer_cpy(address, buffer, size); + } + else //control transfer + { + + size = HSUSBD->CEPRXCNT & 0xffff; + if (size) + { + RT_ASSERT(_rt_obj_udc.stage == STAGE_DOUT); + nu_buffer_cpy(address, buffer, size); + } + + _ep0_send_status(); + } + + return size; +} + +static rt_size_t _ep_read_prepare(rt_uint8_t address, void *buffer, rt_size_t size) +{ + RT_ASSERT(!(address & USB_DIR_IN)); + + if ((address & USB_EPNO_MASK)) + { + HSUSBD_ENABLE_EP_INT(EPADR_SW2HW(address), + HSUSBD_EPINTEN_RXPKIEN_Msk + ); + } + else //control transfer + { + if (size) + { + RT_ASSERT(_rt_obj_udc.stage == STAGE_DOUT); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_OUTTKIEN_Msk); + } + else + { + + RT_ASSERT(_rt_obj_udc.stage == STAGE_STATUS_OUT); + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_SETUPPKIF_Msk + | HSUSBD_CEPINTSTS_STSDONEIF_Msk + ); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_SETUPPKIEN_Msk + | HSUSBD_CEPINTEN_STSDONEIEN_Msk + ); + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR); + } + + } + + return size; +} + +static rt_size_t _ep_write(rt_uint8_t address, void *buffer, rt_size_t size) +{ + + RT_ASSERT((address & USB_DIR_IN)); + + if (!(address & USB_EPNO_MASK)) //control transfer + { + if (size) + { + nu_buffer_cpy(address, buffer, size); + HSUSBD_START_CEP_IN(size); + } + else//zero length + { + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_ZEROLEN); + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk + | HSUSBD_CEPINTSTS_SETUPPKIF_Msk); + + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_SETUPPKIEN_Msk + | HSUSBD_CEPINTEN_STSDONEIEN_Msk + ); + } + + if (_rt_obj_udc.stage == STAGE_DIN) + { + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_TXPKIF_Msk); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_TXPKIEN_Msk); + } + else if (_rt_obj_udc.stage == STAGE_DOUT) + { + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_RXPKIF_Msk); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_RXPKIEN_Msk); + } + } + else + { + /* Non-control endpoint IN*/ + nu_buffer_cpy(address, buffer, size); + HSUSBD->EP[EPADR_SW2HW(address)].EPRSPCTL = HSUSBD_EP_RSPCTL_SHORTTXEN; // packet end + HSUSBD->EP[EPADR_SW2HW(address)].EPTXCNT = size; + + if ((HSUSBD->EP[EPADR_SW2HW(address)].EPCFG & HSUSBD_EPCFG_EPTYPE_Msk) == HSUSBD_EP_CFG_TYPE_INT) + { + HSUSBD_ENABLE_EP_INT(EPADR_SW2HW(address), HSUSBD_EPINTEN_INTKIEN_Msk); //for interrupt transfer timing + } + else + { + HSUSBD_ENABLE_EP_INT(EPADR_SW2HW(address), HSUSBD_EPINTEN_TXPKIEN_Msk); //for bulk transfer timing + } + } + + return size; +} + + + + +static rt_err_t _suspend(void) +{ + return RT_EOK; +} + +static rt_err_t _wakeup(void) +{ + return RT_EOK; +} + +void _USBD20_IRQHandler(void) +{ + __IO rt_uint32_t IrqStL, IrqSt; + + IrqStL = HSUSBD->GINTSTS & HSUSBD->GINTEN; /* get interrupt status */ + + if (!IrqStL) return; + + /* USB interrupt */ + if (IrqStL & HSUSBD_GINTSTS_USBIF_Msk) + { + IrqSt = HSUSBD->BUSINTSTS & HSUSBD->BUSINTEN; + + if (IrqSt & HSUSBD_BUSINTSTS_SOFIF_Msk) + { + HSUSBD_CLR_BUS_INT_FLAG(HSUSBD_BUSINTSTS_SOFIF_Msk); + rt_usbd_sof_handler(&_rt_obj_udc); + } + if (IrqSt & HSUSBD_BUSINTSTS_RSTIF_Msk) + { + /* Reset USB device address */ + HSUSBD_SET_ADDR(0ul); + + HSUSBD_ResetDMA(); + HSUSBD->EP[EPA].EPRSPCTL = HSUSBD_EPRSPCTL_FLUSH_Msk; + HSUSBD->EP[EPB].EPRSPCTL = HSUSBD_EPRSPCTL_FLUSH_Msk; + HSUSBD->EP[EPC].EPRSPCTL = HSUSBD_EPRSPCTL_FLUSH_Msk; + HSUSBD->EP[EPD].EPRSPCTL = HSUSBD_EPRSPCTL_FLUSH_Msk; + HSUSBD->EP[EPE].EPRSPCTL = HSUSBD_EPRSPCTL_FLUSH_Msk; + HSUSBD->EP[EPF].EPRSPCTL = HSUSBD_EPRSPCTL_FLUSH_Msk; + HSUSBD->EP[EPG].EPRSPCTL = HSUSBD_EPRSPCTL_FLUSH_Msk; + HSUSBD->EP[EPH].EPRSPCTL = HSUSBD_EPRSPCTL_FLUSH_Msk; + + if (HSUSBD->OPER & 0x04) /* high speed */ + { + LOG_I("-High Speed-"); + _nu_ep_partition_hs(); + } + else /* full speed */ + { + LOG_I("-Full Speed-"); + _nu_ep_partition_fs(); + } + + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_SETUPPKIEN_Msk); + HSUSBD_ENABLE_BUS_INT(HSUSBD_BUSINTEN_RSTIEN_Msk + | HSUSBD_BUSINTEN_RESUMEIEN_Msk + | HSUSBD_BUSINTEN_SUSPENDIEN_Msk + | HSUSBD_BUSINTEN_VBUSDETIEN_Msk + ); + HSUSBD_CLR_BUS_INT_FLAG(HSUSBD_BUSINTSTS_RSTIF_Msk); + HSUSBD_CLR_CEP_INT_FLAG(0x1ffc); + + for (rt_uint32_t i = 0ul; i < HSUSBD_MAX_EP; i++) + { + if ((HSUSBD->EP[i].EPCFG & 0x1ul) == 0x1ul) + { + HSUSBD->EP[i].EPRSPCTL = HSUSBD_EP_RSPCTL_TOGGLE; + } + } + rt_usbd_reset_handler(&_rt_obj_udc); + HSUSBD_ENABLE_USB(); + } + + if (IrqSt & HSUSBD_BUSINTSTS_RESUMEIF_Msk) + { + LOG_I("-Resume-"); + HSUSBD_ENABLE_BUS_INT(HSUSBD_BUSINTEN_RSTIEN_Msk | HSUSBD_BUSINTEN_SUSPENDIEN_Msk); + HSUSBD_CLR_BUS_INT_FLAG(HSUSBD_BUSINTSTS_RESUMEIF_Msk); + } + + if (IrqSt & HSUSBD_BUSINTSTS_SUSPENDIF_Msk) + { + LOG_I("-Suspend-"); + HSUSBD_ENABLE_BUS_INT(HSUSBD_BUSINTEN_RSTIEN_Msk | HSUSBD_BUSINTEN_RESUMEIEN_Msk | HSUSBD_BUSINTEN_VBUSDETIEN_Msk); + HSUSBD_CLR_BUS_INT_FLAG(HSUSBD_BUSINTSTS_SUSPENDIF_Msk); + } + + if (IrqSt & HSUSBD_BUSINTSTS_HISPDIF_Msk) + { + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_SETUPPKIEN_Msk); + HSUSBD_CLR_BUS_INT_FLAG(HSUSBD_BUSINTSTS_HISPDIF_Msk); + } + + if (IrqSt & HSUSBD_BUSINTSTS_DMADONEIF_Msk) + { + HSUSBD_CLR_BUS_INT_FLAG(HSUSBD_BUSINTSTS_DMADONEIF_Msk); + + if (!(HSUSBD->DMACTL & HSUSBD_DMACTL_DMARD_Msk)) + { + HSUSBD_ENABLE_EP_INT(EPD, HSUSBD_EPINTEN_RXPKIEN_Msk); + } + } + + if (IrqSt & HSUSBD_BUSINTSTS_PHYCLKVLDIF_Msk) + { + HSUSBD_CLR_BUS_INT_FLAG(HSUSBD_BUSINTSTS_PHYCLKVLDIF_Msk); + } + + if (IrqSt & HSUSBD_BUSINTSTS_VBUSDETIF_Msk) + { + if (HSUSBD_IS_ATTACHED()) + { + LOG_I("PLUG IN"); + /* USB Plug In */ + HSUSBD_ENABLE_USB(); + rt_usbd_connect_handler(&_rt_obj_udc); + + } + else + { + LOG_I("Un-Plug"); + /* USB Un-plug */ + HSUSBD_DISABLE_USB(); + rt_usbd_disconnect_handler(&_rt_obj_udc); + } + HSUSBD_CLR_BUS_INT_FLAG(HSUSBD_BUSINTSTS_VBUSDETIF_Msk); + } + } + + /* Control Transfer */ + if (IrqStL & HSUSBD_GINTSTS_CEPIF_Msk) + { + IrqSt = HSUSBD->CEPINTSTS & HSUSBD->CEPINTEN; + + if (IrqSt & HSUSBD_CEPINTSTS_SETUPTKIF_Msk) + { + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_SETUPTKIF_Msk); + return; + } + + if (IrqSt & HSUSBD_CEPINTSTS_SETUPPKIF_Msk) + { + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_SETUPPKIF_Msk); + NU_SetupStageCallback(&nu_usbd); + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_INTKIF_Msk + | HSUSBD_CEPINTSTS_RXPKIF_Msk + | HSUSBD_CEPINTSTS_STSDONEIF_Msk + ); + return; + } + + if (IrqSt & HSUSBD_CEPINTSTS_OUTTKIF_Msk) + { + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_OUTTKIF_Msk); + rt_usbd_ep0_out_handler(&_rt_obj_udc, 0); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_RXPKIEN_Msk); + return; + } + + if (IrqSt & HSUSBD_CEPINTSTS_INTKIF_Msk) + { + HSUSBD_ENABLE_CEP_INT(0); + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_INTKIF_Msk); + rt_usbd_ep0_in_handler(&_rt_obj_udc); + return; + } + + if (IrqSt & HSUSBD_CEPINTSTS_PINGIF_Msk) + { + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_PINGIF_Msk); + return; + } + + if (IrqSt & HSUSBD_CEPINTSTS_TXPKIF_Msk) + { + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_TXPKIF_Msk + | HSUSBD_CEPINTSTS_SETUPPKIF_Msk + | HSUSBD_CEPINTSTS_STSDONEIF_Msk + ); + + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_INTKIEN_Msk + | HSUSBD_CEPINTEN_SETUPPKIEN_Msk + | HSUSBD_CEPINTEN_STSDONEIEN_Msk + ); + + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR); + return; + } + + if (IrqSt & HSUSBD_CEPINTSTS_RXPKIF_Msk) + { + + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_SETUPPKIF_Msk + | HSUSBD_CEPINTSTS_STSDONEIF_Msk + | HSUSBD_CEPINTSTS_RXPKIF_Msk + ); + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_SETUPPKIEN_Msk + | HSUSBD_CEPINTEN_STSDONEIEN_Msk + | HSUSBD_CEPINTEN_RXPKIEN_Msk + ); + return; + } + + if (IrqSt & HSUSBD_CEPINTSTS_NAKIF_Msk) + { + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_NAKIF_Msk); + return; + } + + if (IrqSt & HSUSBD_CEPINTSTS_STALLIF_Msk) + { + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STALLIF_Msk); + return; + } + + if (IrqSt & HSUSBD_CEPINTSTS_ERRIF_Msk) + { + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_ERRIF_Msk); + return; + } + + if (IrqSt & HSUSBD_CEPINTSTS_STSDONEIF_Msk) + { + + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk | HSUSBD_CEPINTSTS_SETUPPKIF_Msk); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_SETUPPKIEN_Msk); + + if ((HSUSBD_GET_ADDR() == 0) + && ((uint8_t)((nu_usbd.Instance->SETUP1_0 >> 8) & 0xfful) == SET_ADDRESS) + ) + { + HSUSBD_SET_ADDR(nu_usbd.address_tmp); + LOG_I("SET ADDR: 0x%02x", nu_usbd.address_tmp); + nu_usbd.address_tmp = 0; + + } + return; + } + + if (IrqSt & HSUSBD_CEPINTSTS_BUFFULLIF_Msk) + { + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_BUFFULLIF_Msk); + return; + } + + if (IrqSt & HSUSBD_CEPINTSTS_BUFEMPTYIF_Msk) + { + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_BUFEMPTYIF_Msk); + return; + } + } + + /* bulk in */ + if (IrqStL & HSUSBD_GINTSTS_EPAIF_Msk) + { + IrqSt = HSUSBD->EP[EPA].EPINTSTS & HSUSBD->EP[EPA].EPINTEN; + HSUSBD_ENABLE_EP_INT(EPA, 0); + HSUSBD_CLR_EP_INT_FLAG(EPA, IrqSt); + rt_usbd_ep_in_handler(&_rt_obj_udc, USB_DIR_IN | EPADR_HW2SW(EPA), 0); + } + + /* bulk out */ + if (IrqStL & HSUSBD_GINTSTS_EPBIF_Msk) + { + IrqSt = HSUSBD->EP[EPB].EPINTSTS & HSUSBD->EP[EPB].EPINTEN; + HSUSBD_CLR_EP_INT_FLAG(EPB, IrqSt); + rt_usbd_ep_out_handler(&_rt_obj_udc, USB_DIR_OUT | EPADR_HW2SW(EPB), 0); + } + + /* interrupt in */ + if (IrqStL & HSUSBD_GINTSTS_EPCIF_Msk) + { + IrqSt = HSUSBD->EP[EPC].EPINTSTS & HSUSBD->EP[EPC].EPINTEN; + HSUSBD_ENABLE_EP_INT(EPC, 0); + HSUSBD_CLR_EP_INT_FLAG(EPC, IrqSt); + rt_usbd_ep_in_handler(&_rt_obj_udc, USB_DIR_IN | EPADR_HW2SW(EPC), 0); + } + + /* interrupt out */ + if (IrqStL & HSUSBD_GINTSTS_EPDIF_Msk) + { + IrqSt = HSUSBD->EP[EPD].EPINTSTS & HSUSBD->EP[EPD].EPINTEN; + HSUSBD_CLR_EP_INT_FLAG(EPD, IrqSt); + rt_usbd_ep_out_handler(&_rt_obj_udc, USB_DIR_OUT | EPADR_HW2SW(EPD), 0); + } + + /* bulk in */ + if (IrqStL & HSUSBD_GINTSTS_EPEIF_Msk) + { + IrqSt = HSUSBD->EP[EPE].EPINTSTS & HSUSBD->EP[EPE].EPINTEN; + HSUSBD_ENABLE_EP_INT(EPE, 0); + HSUSBD_CLR_EP_INT_FLAG(EPE, IrqSt); + + rt_usbd_ep_in_handler(&_rt_obj_udc, USB_DIR_IN | EPADR_HW2SW(EPE), 0); + } + + /* bulk out */ + if (IrqStL & HSUSBD_GINTSTS_EPFIF_Msk) + { + IrqSt = HSUSBD->EP[EPF].EPINTSTS & HSUSBD->EP[EPF].EPINTEN; + HSUSBD_CLR_EP_INT_FLAG(EPF, IrqSt); + rt_usbd_ep_out_handler(&_rt_obj_udc, USB_DIR_OUT | EPADR_HW2SW(EPF), 0); + } + + /* interrupt in */ + if (IrqStL & HSUSBD_GINTSTS_EPGIF_Msk) + { + IrqSt = HSUSBD->EP[EPG].EPINTSTS & HSUSBD->EP[EPG].EPINTEN; + HSUSBD_ENABLE_EP_INT(EPG, 0); + HSUSBD_CLR_EP_INT_FLAG(EPG, IrqSt); + rt_usbd_ep_in_handler(&_rt_obj_udc, USB_DIR_IN | EPADR_HW2SW(EPG), 0); + } + + /* interrupt out */ + if (IrqStL & HSUSBD_GINTSTS_EPHIF_Msk) + { + IrqSt = HSUSBD->EP[EPH].EPINTSTS & HSUSBD->EP[EPH].EPINTEN; + HSUSBD_CLR_EP_INT_FLAG(EPH, IrqSt); + rt_usbd_ep_out_handler(&_rt_obj_udc, USB_DIR_OUT | EPADR_HW2SW(EPH), 0); + } + +} + +void USBD20_IRQHandler(void) +{ + rt_interrupt_enter(); + + _USBD20_IRQHandler(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static rt_err_t _init(rt_device_t device) +{ +#if !defined(BSP_USING_HSOTG) + uint32_t volatile i; + + /* Initialize USB PHY */ + SYS_UnlockReg(); + SYS->USBPHY &= ~SYS_USBPHY_HSUSBROLE_Msk; /* select HSUSBD */ + + /* Enable USB PHY */ + SYS->USBPHY = (SYS->USBPHY & ~(SYS_USBPHY_HSUSBROLE_Msk | SYS_USBPHY_HSUSBACT_Msk)) | SYS_USBPHY_HSUSBEN_Msk; + + for (i = 0; i < 0x1000; i++) + __NOP(); // delay > 10 us + + SYS->USBPHY |= SYS_USBPHY_HSUSBACT_Msk; + SYS_LockReg(); +#endif + + /* HSUSBD Open */ + HSUSBD->PHYCTL |= (HSUSBD_PHYCTL_PHYEN_Msk | HSUSBD_PHYCTL_DPPUEN_Msk); + while (1) + { + HSUSBD->EP[EPA].EPMPS = 0x20ul; + if (HSUSBD->EP[EPA].EPMPS == 0x20ul) + { + break; + } + } + + /* Force SE0 */ + HSUSBD_SET_SE0(); + + _nu_ep_partition(); + +#if ENABLE_FULL_SPEED_MODE_ONLY + HSUSBD->OPER &= ~HSUSBD_OPER_HISPDEN_Msk; +#else + HSUSBD->OPER |= HSUSBD_OPER_HISPDEN_Msk; +#endif + + /* Enable USBD interrupt */ + NVIC_EnableIRQ(USBD20_IRQn); + + /* Start transaction */ + HSUSBD_Start(); + return RT_EOK; +} + +const static struct udcd_ops _udc_ops = +{ + _set_address, + _set_config, + _ep_set_stall, + _ep_clear_stall, + _ep_enable, + _ep_disable, + _ep_read_prepare, + _ep_read, + _ep_write, + _ep0_send_status, + _suspend, + _wakeup, +}; + +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops _ops = +{ + _init, + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, +}; +#endif + +int nu_hsusbd_register(void) +{ + if (RT_NULL != rt_device_find("usbd")) + { + LOG_E("\nHSUSBD Register failed. Another USBD device is registered\n"); + return -RT_ERROR; + } + + rt_memset((void *)&_rt_obj_udc, 0, sizeof(struct udcd)); + _rt_obj_udc.parent.type = RT_Device_Class_USBDevice; + +#ifdef RT_USING_DEVICE_OPS + _rt_obj_udc.parent.ops = &_ops; +#else + _rt_obj_udc.parent.init = _init; +#endif + + _rt_obj_udc.parent.user_data = &nu_usbd; + _rt_obj_udc.ops = &_udc_ops; + + /* Register endpoint information */ + _rt_obj_udc.ep_pool = _ep_pool; + _rt_obj_udc.ep0.id = &_ep_pool[0]; + +#if ENABLE_FULL_SPEED_MODE_ONLY + _rt_obj_udc.device_is_hs = RT_FALSE; /* Enable Full-speed only */ +#else + _rt_obj_udc.device_is_hs = RT_TRUE; /* Support Hi-Speed */ +#endif + + rt_device_register((rt_device_t)&_rt_obj_udc, "usbd", 0); + + rt_usb_device_init(); + return RT_EOK; +} +INIT_DEVICE_EXPORT(nu_hsusbd_register); +#endif diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_i2c.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_i2c.c new file mode 100644 index 0000000000000000000000000000000000000000..0c96c5336f6f6bd1e05eaee80e30e99da1d23708 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_i2c.c @@ -0,0 +1,393 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-2-05 HPHuang First version +******************************************************************************/ + + +#include + +#ifdef BSP_USING_I2C +#include +#include + +/* Private define ---------------------------------------------------------------*/ +#define LOG_TAG "drv.i2c" +#define DBG_ENABLE +#define DBG_SECTION_NAME "drv.i2c" +#define DBG_LEVEL DBG_ERROR +#define DBG_COLOR +#include + +const rt_uint32_t u32I2C_MASTER_STATUS_START = 0x08UL; +const rt_uint32_t u32I2C_MASTER_STATUS_REPEAT_START = 0x10UL; +const rt_uint32_t u32I2C_MASTER_STATUS_TRANSMIT_ADDRESS_ACK = 0x18UL; +const rt_uint32_t u32I2C_MASTER_STATUS_TRANSMIT_ADDRESS_NACK = 0x20UL; +const rt_uint32_t u32I2C_MASTER_STATUS_TRANSMIT_DATA_ACK = 0x28UL; +const rt_uint32_t u32I2C_MASTER_STATUS_TRANSMIT_DATA_NACK = 0x30UL; +const rt_uint32_t u32I2C_MASTER_STATUS_ARBITRATION_LOST = 0x38UL; +const rt_uint32_t u32I2C_MASTER_STATUS_RECEIVE_ADDRESS_ACK = 0x40UL; +const rt_uint32_t u32I2C_MASTER_STATUS_RECEIVE_ADDRESS_NACK = 0x48UL; +const rt_uint32_t u32I2C_MASTER_STATUS_RECEIVE_DATA_ACK = 0x50UL; +const rt_uint32_t u32I2C_MASTER_STATUS_RECEIVE_DATA_NACK = 0x58UL; +const rt_uint32_t u32I2C_MASTER_STATUS_BUS_ERROR = 0x00UL; +const rt_uint32_t u32I2C_MASTER_STATUS_BUS_RELEASED = 0xF8UL; + +/* Private typedef --------------------------------------------------------------*/ +typedef struct _nu_i2c_bus +{ + struct rt_i2c_bus_device parent; + I2C_T *I2C; + struct rt_i2c_msg *msg; + char *device_name; +} nu_i2c_bus_t; + +/* Private variables ------------------------------------------------------------*/ +#ifdef BSP_USING_I2C0 +#define I2C0BUS_NAME "i2c0" +static nu_i2c_bus_t nu_i2c0 = +{ + .I2C = I2C0, + .device_name = I2C0BUS_NAME, +}; +#endif /* BSP_USING_I2C0 */ + +#ifdef BSP_USING_I2C1 +#define I2C1BUS_NAME "i2c1" +static nu_i2c_bus_t nu_i2c1 = +{ + .I2C = I2C1, + .device_name = I2C1BUS_NAME, +}; +#endif /* BSP_USING_I2C1 */ + +#ifdef BSP_USING_I2C2 +#define I2C2BUS_NAME "i2c2" +static nu_i2c_bus_t nu_i2c2 = +{ + .I2C = I2C2, + .device_name = I2C2BUS_NAME, +}; +#endif /* BSP_USING_I2C2 */ + +/* Private functions ------------------------------------------------------------*/ +#if (defined(BSP_USING_I2C0) || defined(BSP_USING_I2C1) || defined(BSP_USING_I2C2)) + +static rt_size_t nu_i2c_mst_xfer(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], + rt_uint32_t num); + +static const struct rt_i2c_bus_device_ops nu_i2c_ops = +{ + .master_xfer = nu_i2c_mst_xfer, + .slave_xfer = NULL, + .i2c_bus_control = NULL, +}; + +static rt_err_t nu_i2c_configure(nu_i2c_bus_t *bus) +{ + RT_ASSERT(bus != RT_NULL); + + bus->parent.ops = &nu_i2c_ops; + I2C_Open(bus->I2C, 100000); + + return RT_EOK; +} + +static inline rt_err_t nu_i2c_wait_ready_with_timeout(nu_i2c_bus_t *bus) +{ + rt_tick_t start = rt_tick_get(); + while (!(bus->I2C->CTL0 & I2C_CTL0_SI_Msk)) + { + if ((rt_tick_get() - start) > bus->parent.timeout) + { + LOG_E("\ni2c: timeout!\n"); + return -RT_ETIMEOUT; + } + } + + return RT_EOK; +} + +static inline rt_err_t nu_i2c_send_data(nu_i2c_bus_t *nu_i2c, rt_uint8_t data) +{ + I2C_SET_DATA(nu_i2c->I2C, data); + I2C_SET_CONTROL_REG(nu_i2c->I2C, I2C_CTL_SI); + return nu_i2c_wait_ready_with_timeout(nu_i2c); +} + +static rt_err_t nu_i2c_send_address(nu_i2c_bus_t *nu_i2c, + struct rt_i2c_msg *msg) +{ + rt_uint16_t flags = msg->flags; + rt_uint16_t ignore_nack = msg->flags & RT_I2C_IGNORE_NACK; + rt_uint8_t addr1, addr2; + rt_err_t ret; + + + if (flags & RT_I2C_ADDR_10BIT) + { + nu_i2c->I2C->CTL1 |= I2C_CTL1_ADDR10EN_Msk; + addr1 = 0xf0 | ((msg->addr >> 7) & 0x06); + addr2 = msg->addr & 0xff; + + LOG_D("address1: %d, address2: %d\n", addr1, addr2); + + ret = nu_i2c_send_data(nu_i2c, addr1); + if (ret != RT_EOK) /* for timeout condition */ + return -RT_EIO; + + if ((I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_TRANSMIT_ADDRESS_ACK) && !ignore_nack) + { + LOG_E("NACK: sending first address failed\n"); + + return -RT_EIO; + } + + ret = nu_i2c_send_data(nu_i2c, addr2); + if (ret != RT_EOK) /* for timeout condition */ + return -RT_EIO; + + if ((I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_TRANSMIT_ADDRESS_ACK) && !ignore_nack) + { + LOG_E("NACK: sending second address failed\n"); + + return -RT_EIO; + } + + if (flags & RT_I2C_RD) + { + LOG_D("send repeated START signal\n"); + + I2C_SET_CONTROL_REG(nu_i2c->I2C, I2C_CTL_STA_SI); + ret = nu_i2c_wait_ready_with_timeout(nu_i2c); + if (ret != RT_EOK) /* for timeout condition */ + return -RT_EIO; + + if ((I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_REPEAT_START) && !ignore_nack) + { + LOG_E("sending repeated START failed\n"); + + return -RT_EIO; + } + + addr1 |= 0x01; + + ret = nu_i2c_send_data(nu_i2c, addr1); + if (ret != RT_EOK) /* for timeout condition */ + return -RT_EIO; + + if ((I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_RECEIVE_ADDRESS_ACK) && !ignore_nack) + { + LOG_E("NACK: sending read address failed\n"); + + return -RT_EIO; + } + } + } + else + { + /* 7-bit addr */ + addr1 = msg->addr << 1; + if (flags & RT_I2C_RD) + addr1 |= 1; + + /* Send device address */ + ret = nu_i2c_send_data(nu_i2c, addr1); /* Send Address */ + if (ret != RT_EOK) /* for timeout condition */ + return -RT_EIO; + + if ( (I2C_GET_STATUS(nu_i2c->I2C) + != ((flags & RT_I2C_RD) ? u32I2C_MASTER_STATUS_RECEIVE_ADDRESS_ACK : u32I2C_MASTER_STATUS_TRANSMIT_ADDRESS_ACK)) + && !ignore_nack) + { + LOG_E("sending address failed\n"); + return -RT_EIO; + } + } + + return RT_EOK; +} + +static rt_size_t nu_i2c_mst_xfer(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], + rt_uint32_t num) +{ + struct rt_i2c_msg *msg; + nu_i2c_bus_t *nu_i2c; + rt_size_t i; + rt_uint32_t cnt_data; + rt_uint16_t ignore_nack; + rt_err_t ret; + + RT_ASSERT(bus != RT_NULL); + nu_i2c = (nu_i2c_bus_t *) bus; + + nu_i2c->msg = msgs; + + nu_i2c->I2C->CTL0 |= I2C_CTL0_STA_Msk | I2C_CTL0_SI_Msk; + ret = nu_i2c_wait_ready_with_timeout(nu_i2c); + if (ret != RT_EOK) /* for timeout condition */ + { + rt_set_errno(-RT_ETIMEOUT); + return 0; + } + if (I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_START) + { + i = 0; + LOG_E("Send START Failed"); + return i; + } + + for (i = 0; i < num; i++) + { + msg = &msgs[i]; + ignore_nack = msg->flags & RT_I2C_IGNORE_NACK; + + if (!(msg->flags & RT_I2C_NO_START)) + { + if (i) + { + I2C_SET_CONTROL_REG(nu_i2c->I2C, I2C_CTL_STA_SI); + ret = nu_i2c_wait_ready_with_timeout(nu_i2c); + if (ret != RT_EOK) /* for timeout conditrion */ + break; + + if (I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_REPEAT_START) + { + i = 0; + LOG_E("Send repeat START Fail"); + break; + } + } + + if ((RT_EOK != nu_i2c_send_address(nu_i2c, msg)) + && !ignore_nack) + { + i = 0; + LOG_E("Send Address Fail"); + break; + } + } + + + if (nu_i2c->msg[i].flags & RT_I2C_RD) /* Receive Bytes */ + { + rt_uint32_t do_rd_nack = (i == (num - 1)); + for (cnt_data = 0 ; cnt_data < (nu_i2c->msg[i].len) ; cnt_data++) + { + do_rd_nack += (cnt_data == (nu_i2c->msg[i].len - 1)); /* NACK after last byte for hardware setting */ + if (do_rd_nack == 2) + { + I2C_SET_CONTROL_REG(nu_i2c->I2C, I2C_CTL_SI); + } + else + { + I2C_SET_CONTROL_REG(nu_i2c->I2C, I2C_CTL_SI_AA); + } + + ret = nu_i2c_wait_ready_with_timeout(nu_i2c); + if (ret != RT_EOK) /* for timeout condition */ + break; + + if (nu_i2c->I2C->CTL0 & I2C_CTL_AA) + { + if (I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_RECEIVE_DATA_ACK) + { + i = 0; + break; + } + } + else + { + if (I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_RECEIVE_DATA_NACK) + { + i = 0; + break; + } + } + + nu_i2c->msg[i].buf[cnt_data] = nu_i2c->I2C->DAT; + } + } + else /* Send Bytes */ + { + for (cnt_data = 0 ; cnt_data < (nu_i2c->msg[i].len) ; cnt_data++) + { + /* Send register number and MSB of data */ + ret = nu_i2c_send_data(nu_i2c, (uint8_t)(nu_i2c->msg[i].buf[cnt_data])); + if (ret != RT_EOK) /* for timeout condition */ + break; + + if (I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_TRANSMIT_DATA_ACK + && !ignore_nack + ) /* Send aata and get Ack */ + { + i = 0; + break; + } + } + } + } + + I2C_STOP(nu_i2c->I2C); + + RT_ASSERT(I2C_GET_STATUS(nu_i2c->I2C) == u32I2C_MASTER_STATUS_BUS_RELEASED); + if (I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_BUS_RELEASED) + { + i = 0; + } + + nu_i2c->msg = RT_NULL; + nu_i2c->I2C->CTL1 = 0; /*clear all sub modes like 10 bit mode*/ + return i; +} + +#endif + +/* Public functions -------------------------------------------------------------*/ +int rt_hw_i2c_init(void) +{ + rt_err_t ret = RT_ERROR; +#if defined(BSP_USING_I2C0) + SYS_UnlockReg(); + /* Enable I2C0 clock */ + SYS_ResetModule(I2C0_RST); + SYS_LockReg(); + nu_i2c_configure(&nu_i2c0); + ret = rt_i2c_bus_device_register(&nu_i2c0.parent, nu_i2c0.device_name); + RT_ASSERT(RT_EOK == ret); +#endif /* BSP_USING_I2C0 */ + +#if defined(BSP_USING_I2C1) + SYS_UnlockReg(); + /* Enable I2C1 clock */ + SYS_ResetModule(I2C1_RST); + SYS_LockReg(); + nu_i2c_configure(&nu_i2c1); + ret = rt_i2c_bus_device_register(&nu_i2c1.parent, nu_i2c1.device_name); + RT_ASSERT(RT_EOK == ret); +#endif /* BSP_USING_I2C1 */ + +#if defined(BSP_USING_I2C2) + SYS_UnlockReg(); + /* Enable I2C2 clock */ + SYS_ResetModule(I2C2_RST); + SYS_LockReg(); + nu_i2c_configure(&nu_i2c2); + ret = rt_i2c_bus_device_register(&nu_i2c2.parent, nu_i2c2.device_name); + RT_ASSERT(RT_EOK == ret); +#endif /* BSP_USING_I2C2 */ + + return ret; +} + +INIT_DEVICE_EXPORT(rt_hw_i2c_init); + +#endif /* BSP_USING_I2C */ + diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_i2s.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_i2s.c new file mode 100644 index 0000000000000000000000000000000000000000..35b73832103a7dec8953ee75e1ab7048564d15c5 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_i2s.c @@ -0,0 +1,583 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-2-7 Wayne Lin First version +* +******************************************************************************/ + +#include + +#if defined(BSP_USING_I2S) + +#include +#include +#include + +/* Private define ---------------------------------------------------------------*/ +#define DBG_ENABLE +#define DBG_LEVEL DBG_LOG +#define DBG_SECTION_NAME "i2s" +#define DBG_COLOR +#include + +/* Private functions ------------------------------------------------------------*/ +static rt_err_t nu_i2s_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps); +static rt_err_t nu_i2s_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps); +static rt_err_t nu_i2s_init(struct rt_audio_device *audio); +static rt_err_t nu_i2s_start(struct rt_audio_device *audio, int stream); +static rt_err_t nu_i2s_stop(struct rt_audio_device *audio, int stream); +static void nu_i2s_buffer_info(struct rt_audio_device *audio, struct rt_audio_buf_info *info); +/* Public functions -------------------------------------------------------------*/ +rt_err_t nu_i2s_acodec_register(nu_acodec_ops_t); + +/* Private variables ------------------------------------------------------------*/ +static struct nu_i2s g_nu_i2s_dev = +{ + .name = "sound0", + .i2s_base = I2S0, + .i2s_rst = I2S0_RST, + .i2s_dais = { + [NU_I2S_DAI_PLAYBACK] = { + .pdma_perp = PDMA_I2S0_TX, + }, + [NU_I2S_DAI_CAPTURE] = { + .pdma_perp = PDMA_I2S0_RX, + } + } +}; + +static void nu_pdma_i2s_rx_cb(void *pvUserData, uint32_t u32EventFilter) +{ + nu_i2s_t psNuI2s = (nu_i2s_t)pvUserData; + nu_i2s_dai_t psNuI2sDai; + + RT_ASSERT(psNuI2s != RT_NULL); + psNuI2sDai = &psNuI2s->i2s_dais[NU_I2S_DAI_CAPTURE]; + + if (u32EventFilter & NU_PDMA_EVENT_TRANSFER_DONE) + { + // Report a buffer ready. + rt_uint8_t *pbuf_old = &psNuI2sDai->fifo[psNuI2sDai->fifo_block_idx * NU_I2S_DMA_BUF_BLOCK_SIZE] ; + psNuI2sDai->fifo_block_idx = (psNuI2sDai->fifo_block_idx + 1) % NU_I2S_DMA_BUF_BLOCK_NUMBER; + + /* Report upper layer. */ + rt_audio_rx_done(&psNuI2s->audio, pbuf_old, NU_I2S_DMA_BUF_BLOCK_SIZE); + } +} + +static void nu_pdma_i2s_tx_cb(void *pvUserData, uint32_t u32EventFilter) +{ + nu_i2s_t psNuI2s = (nu_i2s_t)pvUserData; + nu_i2s_dai_t psNuI2sDai; + + RT_ASSERT(psNuI2s != RT_NULL); + psNuI2sDai = &psNuI2s->i2s_dais[NU_I2S_DAI_PLAYBACK]; + + if (u32EventFilter & NU_PDMA_EVENT_TRANSFER_DONE) + { + rt_audio_tx_complete(&psNuI2s->audio); + psNuI2sDai->fifo_block_idx = (psNuI2sDai->fifo_block_idx + 1) % NU_I2S_DMA_BUF_BLOCK_NUMBER; + } +} + +static rt_err_t nu_i2s_pdma_sc_config(nu_i2s_t psNuI2s, E_NU_I2S_DAI dai) +{ + rt_err_t result = RT_EOK; + I2S_T *i2s_base; + nu_i2s_dai_t psNuI2sDai; + int i; + uint32_t u32Src, u32Dst; + nu_pdma_cb_handler_t pfm_pdma_cb; + + RT_ASSERT(psNuI2s != RT_NULL); + + /* Get base address of i2s register */ + i2s_base = psNuI2s->i2s_base; + psNuI2sDai = &psNuI2s->i2s_dais[dai]; + + switch ((int)dai) + { + case NU_I2S_DAI_PLAYBACK: + pfm_pdma_cb = nu_pdma_i2s_tx_cb; + u32Src = (uint32_t)&psNuI2sDai->fifo[0]; + u32Dst = (uint32_t)&i2s_base->TXFIFO; + break; + + case NU_I2S_DAI_CAPTURE: + pfm_pdma_cb = nu_pdma_i2s_rx_cb; + u32Src = (uint32_t)&i2s_base->RXFIFO; + u32Dst = (uint32_t)&psNuI2sDai->fifo[0]; + break; + + default: + return -RT_EINVAL; + } + + result = nu_pdma_callback_register(psNuI2sDai->pdma_chanid, + pfm_pdma_cb, + (void *)psNuI2s, + NU_PDMA_EVENT_TRANSFER_DONE); + RT_ASSERT(result == RT_EOK); + + for (i = 0; i < NU_I2S_DMA_BUF_BLOCK_NUMBER; i++) + { + /* Setup dma descriptor entry */ + result = nu_pdma_desc_setup(psNuI2sDai->pdma_chanid, // Channel ID + psNuI2sDai->pdma_descs[i], // this descriptor + 32, // 32-bits + (dai == NU_I2S_DAI_PLAYBACK) ? u32Src + (i * NU_I2S_DMA_BUF_BLOCK_SIZE) : u32Src, //Memory or RXFIFO + (dai == NU_I2S_DAI_PLAYBACK) ? u32Dst : u32Dst + (i * NU_I2S_DMA_BUF_BLOCK_SIZE), //TXFIFO or Memory + (int32_t)NU_I2S_DMA_BUF_BLOCK_SIZE / 4, // Transfer count + psNuI2sDai->pdma_descs[(i + 1) % NU_I2S_DMA_BUF_BLOCK_NUMBER]); // Next descriptor + RT_ASSERT(result == RT_EOK); + } + + /* Assign head descriptor */ + result = nu_pdma_sg_transfer(psNuI2sDai->pdma_chanid, psNuI2sDai->pdma_descs[0], 0); + RT_ASSERT(result == RT_EOK); + + return result; +} + +static rt_bool_t nu_i2s_capacity_check(struct rt_audio_configure *pconfig) +{ + switch (pconfig->samplebits) + { + case 8: + case 16: + /* case 24: PDMA constrain */ + case 32: + break; + default: + goto exit_nu_i2s_capacity_check; + } + + switch (pconfig->channels) + { + case 1: + case 2: + break; + default: + goto exit_nu_i2s_capacity_check; + } + + return RT_TRUE; + +exit_nu_i2s_capacity_check: + + return RT_FALSE; +} + +static rt_err_t nu_i2s_dai_setup(nu_i2s_t psNuI2s, struct rt_audio_configure *pconfig) +{ + rt_err_t result = RT_EOK; + nu_acodec_ops_t pNuACodecOps = RT_NULL; + RT_ASSERT(psNuI2s->AcodecOps != RT_NULL); + pNuACodecOps = psNuI2s->AcodecOps; + rt_uint32_t real_samplerate; + + /* Open I2S */ + if (nu_i2s_capacity_check(pconfig) == RT_TRUE) + { + /* Reset audio codec */ + if (pNuACodecOps->nu_acodec_reset) + result = pNuACodecOps->nu_acodec_reset(); + + if (result != RT_EOK) + goto exit_nu_i2s_dai_setup; + + /* Setup audio codec */ + if (pNuACodecOps->nu_acodec_init) + result = pNuACodecOps->nu_acodec_init(); + + if (!pNuACodecOps->nu_acodec_init || result != RT_EOK) + goto exit_nu_i2s_dai_setup; + + /* Setup acodec samplerate/samplebit/channel */ + if (pNuACodecOps->nu_acodec_dsp_control) + result = pNuACodecOps->nu_acodec_dsp_control(pconfig); + + if (!pNuACodecOps->nu_acodec_dsp_control || result != RT_EOK) + goto exit_nu_i2s_dai_setup; + + real_samplerate = I2S_Open(psNuI2s->i2s_base, + (psNuI2s->AcodecOps->role == NU_ACODEC_ROLE_MASTER) ? I2S_MODE_SLAVE : I2S_MODE_MASTER, + pconfig->samplerate, + (((pconfig->samplebits / 8) - 1) << I2S_CTL0_DATWIDTH_Pos), + (pconfig->channels == 1) ? I2S_ENABLE_MONO : I2S_DISABLE_MONO, + I2S_FORMAT_I2S); + LOG_I("Open I2S."); + + /* Open I2S0 interface and set to slave mode, stereo channel, I2S format */ + if (pconfig->samplerate != real_samplerate) + { + LOG_W("Real sample rate: %d Hz != preferred sample rate: %d Hz\n", real_samplerate, pconfig->samplerate); + } + + /* Set MCLK and enable MCLK */ + I2S_EnableMCLK(psNuI2s->i2s_base, __HXT); + + /* Set unmute */ + if (pNuACodecOps->nu_acodec_mixer_control) + pNuACodecOps->nu_acodec_mixer_control(AUDIO_MIXER_MUTE, RT_FALSE); + } + else + result = -RT_EINVAL; + +exit_nu_i2s_dai_setup: + + return result; +} + +static rt_err_t nu_i2s_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps) +{ + rt_err_t result = RT_EOK; + nu_i2s_t psNuI2s; + nu_acodec_ops_t pNuACodecOps = RT_NULL; + + RT_ASSERT(audio != RT_NULL); + RT_ASSERT(caps != RT_NULL); + + psNuI2s = (nu_i2s_t)audio; + + RT_ASSERT(psNuI2s->AcodecOps != RT_NULL); + + pNuACodecOps = psNuI2s->AcodecOps; + + switch (caps->main_type) + { + case AUDIO_TYPE_QUERY: + switch (caps->sub_type) + { + case AUDIO_TYPE_QUERY: + caps->udata.mask = AUDIO_TYPE_INPUT | AUDIO_TYPE_OUTPUT | AUDIO_TYPE_MIXER; + break; + default: + result = -RT_ERROR; + break; + } // switch (caps->sub_type) + break; + + case AUDIO_TYPE_MIXER: + + if (pNuACodecOps->nu_acodec_mixer_query) + { + switch (caps->sub_type) + { + case AUDIO_MIXER_QUERY: + return pNuACodecOps->nu_acodec_mixer_query(AUDIO_MIXER_QUERY, &caps->udata.mask); + + default: + return pNuACodecOps->nu_acodec_mixer_query(caps->sub_type, (rt_uint32_t *)&caps->udata.value); + } // switch (caps->sub_type) + + } // if (pNuACodecOps->nu_acodec_mixer_query) + + result = -RT_ERROR; + break; + + case AUDIO_TYPE_INPUT: + case AUDIO_TYPE_OUTPUT: + + switch (caps->sub_type) + { + case AUDIO_DSP_PARAM: + caps->udata.config.channels = psNuI2s->config.channels; + caps->udata.config.samplebits = psNuI2s->config.samplebits; + caps->udata.config.samplerate = psNuI2s->config.samplerate; + break; + case AUDIO_DSP_SAMPLERATE: + caps->udata.config.samplerate = psNuI2s->config.samplerate; + break; + case AUDIO_DSP_CHANNELS: + caps->udata.config.channels = psNuI2s->config.channels; + break; + case AUDIO_DSP_SAMPLEBITS: + caps->udata.config.samplebits = psNuI2s->config.samplebits; + break; + default: + result = -RT_ERROR; + break; + } // switch (caps->sub_type) + break; + + } // switch (caps->main_type) + + return result; +} + +static rt_err_t nu_i2s_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps) +{ + rt_err_t result = RT_EOK; + nu_i2s_t psNuI2s; + nu_acodec_ops_t pNuACodecOps = RT_NULL; + int stream = -1; + + RT_ASSERT(audio != RT_NULL); + RT_ASSERT(caps != RT_NULL); + + psNuI2s = (nu_i2s_t)audio; + + RT_ASSERT(psNuI2s->AcodecOps != RT_NULL); + pNuACodecOps = psNuI2s->AcodecOps; + + switch (caps->main_type) + { + case AUDIO_TYPE_MIXER: + if (psNuI2s->AcodecOps->nu_acodec_mixer_control) + psNuI2s->AcodecOps->nu_acodec_mixer_control(caps->sub_type, caps->udata.value); + break; + + + case AUDIO_TYPE_INPUT: + stream = AUDIO_STREAM_RECORD; + case AUDIO_TYPE_OUTPUT: + { + rt_bool_t bNeedReset = RT_FALSE; + + if (stream < 0) + stream = AUDIO_STREAM_REPLAY; + + switch (caps->sub_type) + { + case AUDIO_DSP_PARAM: + if (rt_memcmp(&psNuI2s->config, &caps->udata.config, sizeof(struct rt_audio_configure)) != 0) + { + rt_memcpy(&psNuI2s->config, &caps->udata.config, sizeof(struct rt_audio_configure)); + bNeedReset = RT_TRUE; + } + break; + case AUDIO_DSP_SAMPLEBITS: + if (psNuI2s->config.samplerate != caps->udata.config.samplebits) + { + psNuI2s->config.samplerate = caps->udata.config.samplebits; + bNeedReset = RT_TRUE; + } + break; + case AUDIO_DSP_CHANNELS: + if (psNuI2s->config.channels != caps->udata.config.channels) + { + pNuACodecOps->config.channels = caps->udata.config.channels; + bNeedReset = RT_TRUE; + } + break; + case AUDIO_DSP_SAMPLERATE: + if (psNuI2s->config.samplerate != caps->udata.config.samplerate) + { + psNuI2s->config.samplerate = caps->udata.config.samplerate; + bNeedReset = RT_TRUE; + } + break; + default: + result = -RT_ERROR; + break; + } // switch (caps->sub_type) + + if (bNeedReset) + { + return nu_i2s_start(audio, stream); + } + } + break; + default: + result = -RT_ERROR; + break; + } // switch (caps->main_type) + + return result; +} + +static rt_err_t nu_i2s_init(struct rt_audio_device *audio) +{ + rt_err_t result = RT_EOK; + nu_i2s_t psNuI2s; + + RT_ASSERT(audio != RT_NULL); + + psNuI2s = (nu_i2s_t)audio; + + /* Reset this module */ + SYS_ResetModule(psNuI2s->i2s_rst); + + return -(result); +} + +static rt_err_t nu_i2s_start(struct rt_audio_device *audio, int stream) +{ + nu_i2s_t psNuI2s; + + RT_ASSERT(audio != RT_NULL); + + psNuI2s = (nu_i2s_t)audio; + + /* Restart all: I2S and codec. */ + nu_i2s_stop(audio, stream); + if (nu_i2s_dai_setup(psNuI2s, &psNuI2s->config) != RT_EOK) + return -RT_ERROR; + + switch (stream) + { + case AUDIO_STREAM_REPLAY: + { + nu_i2s_pdma_sc_config(psNuI2s, NU_I2S_DAI_PLAYBACK); + + /* Start TX DMA */ + I2S_ENABLE_TXDMA(psNuI2s->i2s_base); + + /* Enable I2S Tx function */ + I2S_ENABLE_TX(psNuI2s->i2s_base); + + LOG_I("Start replay."); + } + break; + + case AUDIO_STREAM_RECORD: + { + nu_i2s_pdma_sc_config(psNuI2s, NU_I2S_DAI_CAPTURE); + + /* Start RX DMA */ + I2S_ENABLE_RXDMA(psNuI2s->i2s_base); + + /* Enable I2S Rx function */ + I2S_ENABLE_RX(psNuI2s->i2s_base); + + LOG_I("Start record."); + } + break; + } + + return RT_EOK; +} + +static rt_err_t nu_i2s_stop(struct rt_audio_device *audio, int stream) +{ + nu_i2s_t psNuI2s; + nu_i2s_dai_t psNuI2sDai = RT_NULL; + + RT_ASSERT(audio != RT_NULL); + + psNuI2s = (nu_i2s_t)audio; + + switch (stream) + { + case AUDIO_STREAM_REPLAY: + psNuI2sDai = &psNuI2s->i2s_dais[NU_I2S_DAI_PLAYBACK]; + + // Disable TX + I2S_DISABLE_TXDMA(psNuI2s->i2s_base); + I2S_DISABLE_TX(psNuI2s->i2s_base); + + LOG_I("Stop replay."); + break; + + case AUDIO_STREAM_RECORD: + psNuI2sDai = &psNuI2s->i2s_dais[NU_I2S_DAI_CAPTURE]; + + // Disable RX + I2S_DISABLE_RXDMA(psNuI2s->i2s_base); + I2S_DISABLE_RX(psNuI2s->i2s_base); + + LOG_I("Stop record."); + break; + + default: + return -RT_EINVAL; + } + + /* Stop DMA transfer. */ + nu_pdma_channel_terminate(psNuI2sDai->pdma_chanid); + + /* Close I2S */ + if (!(psNuI2s->i2s_base->CTL0 & (I2S_CTL0_TXEN_Msk | I2S_CTL0_RXEN_Msk))) + { + I2S_DisableMCLK(psNuI2s->i2s_base); + I2S_Close(psNuI2s->i2s_base); + LOG_I("Close I2S."); + } + + /* Silence */ + rt_memset((void *)psNuI2sDai->fifo, 0, NU_I2S_DMA_FIFO_SIZE); + psNuI2sDai->fifo_block_idx = 0; + + return RT_EOK; +} + +static void nu_i2s_buffer_info(struct rt_audio_device *audio, struct rt_audio_buf_info *info) +{ + nu_i2s_t psNuI2s; + + RT_ASSERT(audio != RT_NULL); + RT_ASSERT(info != RT_NULL); + + psNuI2s = (nu_i2s_t)audio; + + info->buffer = (rt_uint8_t *)psNuI2s->i2s_dais[NU_I2S_DAI_PLAYBACK].fifo ; + info->total_size = NU_I2S_DMA_FIFO_SIZE; + info->block_size = NU_I2S_DMA_BUF_BLOCK_SIZE; + info->block_count = NU_I2S_DMA_BUF_BLOCK_NUMBER; + + return; +} + +static struct rt_audio_ops nu_i2s_audio_ops = +{ + .getcaps = nu_i2s_getcaps, + .configure = nu_i2s_configure, + + .init = nu_i2s_init, + .start = nu_i2s_start, + .stop = nu_i2s_stop, + .transmit = RT_NULL, + .buffer_info = nu_i2s_buffer_info +}; + +static rt_err_t nu_hw_i2s_pdma_allocate(nu_i2s_dai_t psNuI2sDai) +{ + /* Allocate I2S nu_dma channel */ + if ((psNuI2sDai->pdma_chanid = nu_pdma_channel_allocate(psNuI2sDai->pdma_perp)) < 0) + { + goto nu_hw_i2s_pdma_allocate; + } + + return RT_EOK; + +nu_hw_i2s_pdma_allocate: + + return -(RT_ERROR); +} + +int rt_hw_i2s_init(void) +{ + int i = 0; + nu_i2s_dai_t psNuI2sDai; + + for (i = 0; i < NU_I2S_DAI_CNT; i++) + { + uint8_t *pu8ptr = rt_malloc(NU_I2S_DMA_FIFO_SIZE); + psNuI2sDai = &g_nu_i2s_dev.i2s_dais[i]; + psNuI2sDai->fifo = pu8ptr; + rt_memset(pu8ptr, 0, NU_I2S_DMA_FIFO_SIZE); + RT_ASSERT(psNuI2sDai->fifo != RT_NULL); + + psNuI2sDai->pdma_chanid = -1; + psNuI2sDai->fifo_block_idx = 0; + RT_ASSERT(nu_hw_i2s_pdma_allocate(psNuI2sDai) == RT_EOK); + + RT_ASSERT(nu_pdma_sgtbls_allocate(&psNuI2sDai->pdma_descs[0], NU_I2S_DMA_BUF_BLOCK_NUMBER) == RT_EOK); + } + + /* Register ops of audio device */ + g_nu_i2s_dev.audio.ops = &nu_i2s_audio_ops; + + /* Register device, RW: it is with replay and record functions. */ + rt_audio_register(&g_nu_i2s_dev.audio, g_nu_i2s_dev.name, RT_DEVICE_FLAG_RDWR, &g_nu_i2s_dev); + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_i2s_init); +#endif //#if defined(BSP_USING_I2S) diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_i2s.h b/bsp/nuvoton/libraries/m480/rtt_port/drv_i2s.h new file mode 100644 index 0000000000000000000000000000000000000000..3fe99f3e3b909fb8b33c2db2a22657f7f7e9477e --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_i2s.h @@ -0,0 +1,96 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-2-7 Wayne First version +* +******************************************************************************/ + +#ifndef __DRV_I2S_H__ +#define __DRV_I2S_H__ + +#include +#include +#include + +#if !defined(NU_I2S_DMA_FIFO_SIZE) + #define NU_I2S_DMA_FIFO_SIZE (2048) +#endif + +#if !defined(NU_I2S_DMA_BUF_BLOCK_NUMBER) + #define NU_I2S_DMA_BUF_BLOCK_NUMBER (2) +#endif + +#if ( (NU_I2S_DMA_FIFO_SIZE % NU_I2S_DMA_BUF_BLOCK_NUMBER) != 0 ) + #error "Please give an aligned definition" +#endif +#if ( NU_I2S_DMA_FIFO_SIZE < 2048 ) + #warning "DMA FIFO too small, miss voice?" +#endif + +#define NU_I2S_DMA_BUF_BLOCK_SIZE (NU_I2S_DMA_FIFO_SIZE/NU_I2S_DMA_BUF_BLOCK_NUMBER) + +typedef enum +{ + NU_I2S_DAI_PLAYBACK, + NU_I2S_DAI_CAPTURE, + NU_I2S_DAI_CNT +} E_NU_I2S_DAI; + +typedef enum +{ + NU_ACODEC_ROLE_MASTER, + NU_ACODEC_ROLE_SLAVE, +} E_NU_ACODEC_ROLE; + +typedef struct +{ + char *name; + + E_NU_ACODEC_ROLE role; + + struct rt_audio_configure config; + + rt_err_t (*nu_acodec_init)(void); + + rt_err_t (*nu_acodec_reset)(void); + + rt_err_t (*nu_acodec_dsp_control)(struct rt_audio_configure *config); + + rt_err_t (*nu_acodec_mixer_control)(rt_uint32_t ui32Item, rt_uint32_t ui32Value); + + rt_err_t (*nu_acodec_mixer_query)(rt_uint32_t ui32Item, rt_uint32_t *ui32Value); + +} nu_acodec_ops; + +typedef nu_acodec_ops *nu_acodec_ops_t; + +struct nu_i2s_dai +{ + int16_t pdma_perp; + int8_t pdma_chanid; + rt_uint8_t *fifo; + int16_t fifo_block_idx; + nu_pdma_desc_t pdma_descs[NU_I2S_DMA_BUF_BLOCK_NUMBER]; +}; +typedef struct nu_i2s_dai *nu_i2s_dai_t; + +struct nu_i2s +{ + struct rt_audio_device audio; + struct rt_audio_configure config; + + char *name; + I2S_T *i2s_base; + uint32_t i2s_rst; + + struct nu_i2s_dai i2s_dais[NU_I2S_DAI_CNT]; + nu_acodec_ops_t AcodecOps; +}; +typedef struct nu_i2s *nu_i2s_t; + +#endif // __DRV_I2S_H___ diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_pdma.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_pdma.c new file mode 100644 index 0000000000000000000000000000000000000000..6e3a86ae31365ee7aedb48669d75eafd50cd8063 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_pdma.c @@ -0,0 +1,997 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-2-7 Wayne First version +* +******************************************************************************/ + +#include + +#if defined(BSP_USING_PDMA) + +#include +#include +#include +#include + +/* Private define ---------------------------------------------------------------*/ +// RT_DEV_NAME_PREFIX pdma + +#ifndef NU_PDMA_MEMFUN_ACTOR_MAX + #define NU_PDMA_MEMFUN_ACTOR_MAX (4) +#endif + +#define NU_PDMA_SG_TBL_MAXSIZE (NU_PDMA_SG_LIMITED_DISTANCE/sizeof(DSCT_T)) + +#define NU_PDMA_CH_MAX (PDMA_CH_MAX) /* Specify maximum channels of PDMA */ +#define NU_PDMA_CH_Pos (0) /* Specify first channel number of PDMA */ +#define NU_PDMA_CH_Msk (((1 << NU_PDMA_CH_MAX) - 1) << NU_PDMA_CH_Pos) + +/* Private typedef --------------------------------------------------------------*/ +struct nu_pdma_periph_ctl +{ + uint32_t m_u32Peripheral; + nu_pdma_memctrl_t m_eMemCtl; +}; +typedef struct nu_pdma_periph_ctl nu_pdma_periph_ctl_t; + +struct nu_pdma_chn +{ + nu_pdma_cb_handler_t m_pfnCBHandler; + void *m_pvUserData; + uint32_t m_u32EventFilter; + uint32_t m_u32IdleTimeout_us; + nu_pdma_periph_ctl_t m_spPeripCtl; +}; +typedef struct nu_pdma_chn nu_pdma_chn_t; + +struct nu_pdma_memfun_actor +{ + int m_i32ChannID; + uint32_t m_u32Result; + uint32_t m_u32TrigTransferCnt; + rt_sem_t m_psSemMemFun; +} ; +typedef struct nu_pdma_memfun_actor *nu_pdma_memfun_actor_t; + +/* Private functions ------------------------------------------------------------*/ +static int nu_pdma_peripheral_set(uint32_t u32PeriphType); +static void nu_pdma_init(void); +static void nu_pdma_channel_enable(int i32ChannID); +static void nu_pdma_channel_disable(int i32ChannID); +static void nu_pdma_channel_reset(int i32ChannID); +static rt_err_t nu_pdma_timeout_set(int i32ChannID, int i32Timeout_us); +static void nu_pdma_periph_ctrl_fill(int i32ChannID, int i32CtlPoolIdx); +static rt_size_t nu_pdma_memfun(void *dest, void *src, uint32_t u32DataWidth, unsigned int count, nu_pdma_memctrl_t eMemCtl); +static void nu_pdma_memfun_cb(void *pvUserData, uint32_t u32Events); +static void nu_pdma_memfun_actor_init(void); +static int nu_pdma_memfun_employ(void); +static int nu_pdma_non_transfer_count_get(int32_t i32ChannID); + +/* Public functions -------------------------------------------------------------*/ + + +/* Private variables ------------------------------------------------------------*/ +static volatile int nu_pdma_inited = 0; +static volatile uint32_t nu_pdma_chn_mask = 0; +static nu_pdma_chn_t nu_pdma_chn_arr[NU_PDMA_CH_MAX]; +static rt_mutex_t g_mutex_res = RT_NULL; +static volatile uint32_t nu_pdma_memfun_actor_mask = 0; +static volatile uint32_t nu_pdma_memfun_actor_maxnum = 0; +static rt_sem_t nu_pdma_memfun_actor_pool_sem = RT_NULL; +static rt_mutex_t nu_pdma_memfun_actor_pool_lock = RT_NULL; + +static const nu_pdma_periph_ctl_t g_nu_pdma_peripheral_ctl_pool[ ] = +{ + // M2M + { PDMA_MEM, eMemCtl_SrcInc_DstInc }, + + // M2P + { PDMA_USB_TX, eMemCtl_SrcInc_DstFix }, + + { PDMA_UART0_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_UART1_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_UART2_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_UART3_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_UART4_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_UART5_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_UART6_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_UART7_TX, eMemCtl_SrcInc_DstFix }, + + { PDMA_USCI0_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_USCI1_TX, eMemCtl_SrcInc_DstFix }, + + { PDMA_QSPI0_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_QSPI1_TX, eMemCtl_SrcInc_DstFix }, + + { PDMA_SPI0_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_SPI1_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_SPI2_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_SPI3_TX, eMemCtl_SrcInc_DstFix }, + + { PDMA_I2C0_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_I2C1_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_I2C2_TX, eMemCtl_SrcInc_DstFix }, + + { PDMA_I2S0_TX, eMemCtl_SrcInc_DstFix }, + + { PDMA_DAC0_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_DAC1_TX, eMemCtl_SrcInc_DstFix }, + + { PDMA_EPWM0_CH0_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_EPWM0_CH1_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_EPWM0_CH2_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_EPWM0_CH3_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_EPWM0_CH4_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_EPWM1_CH0_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_EPWM1_CH1_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_EPWM1_CH2_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_EPWM1_CH3_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_EPWM1_CH4_TX, eMemCtl_SrcInc_DstFix }, + + // P2M + { PDMA_USB_RX, eMemCtl_SrcFix_DstInc }, + + { PDMA_UART0_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_UART1_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_UART2_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_UART3_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_UART4_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_UART5_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_UART6_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_UART7_RX, eMemCtl_SrcFix_DstInc }, + + { PDMA_USCI0_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_USCI1_RX, eMemCtl_SrcFix_DstInc }, + + { PDMA_QSPI0_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_QSPI1_RX, eMemCtl_SrcFix_DstInc }, + + { PDMA_SPI0_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_SPI1_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_SPI2_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_SPI3_RX, eMemCtl_SrcFix_DstInc }, + + { PDMA_EPWM0_P1_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_EPWM0_P2_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_EPWM0_P3_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_EPWM1_P1_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_EPWM1_P2_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_EPWM1_P3_RX, eMemCtl_SrcFix_DstInc }, + + { PDMA_I2C0_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_I2C1_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_I2C2_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_I2S0_RX, eMemCtl_SrcFix_DstInc }, + + { PDMA_EADC0_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_EADC1_RX, eMemCtl_SrcFix_DstInc }, +}; +#define NU_PERIPHERAL_SIZE ( sizeof(g_nu_pdma_peripheral_ctl_pool) / sizeof(g_nu_pdma_peripheral_ctl_pool[0]) ) + +static struct nu_pdma_memfun_actor nu_pdma_memfun_actor_arr[NU_PDMA_MEMFUN_ACTOR_MAX]; + +/* SG table pool */ +static DSCT_T nu_pdma_sgtbl_arr[NU_PDMA_SGTBL_POOL_SIZE] = { 0 }; +static uint32_t nu_pdma_sgtbl_token[RT_ALIGN(NU_PDMA_SGTBL_POOL_SIZE, 32) / 32]; +static rt_mutex_t g_mutex_sg = RT_NULL; + +static int nu_pdma_peripheral_set(uint32_t u32PeriphType) +{ + int idx = 0; + + while (idx < NU_PERIPHERAL_SIZE) + { + if (g_nu_pdma_peripheral_ctl_pool[idx].m_u32Peripheral == u32PeriphType) + return idx; + idx++; + } + + // Not such peripheral + return -1; +} + +static void nu_pdma_periph_ctrl_fill(int i32ChannID, int i32CtlPoolIdx) +{ + nu_pdma_chn_t *psPdmaChann = &nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos]; + psPdmaChann->m_spPeripCtl.m_u32Peripheral = g_nu_pdma_peripheral_ctl_pool[i32CtlPoolIdx].m_u32Peripheral; + psPdmaChann->m_spPeripCtl.m_eMemCtl = g_nu_pdma_peripheral_ctl_pool[i32CtlPoolIdx].m_eMemCtl; +} + +static void nu_pdma_init(void) +{ + int latest = 0; + if (nu_pdma_inited) + return; + + g_mutex_res = rt_mutex_create("pdmalock", RT_IPC_FLAG_FIFO); + RT_ASSERT(g_mutex_res != RT_NULL); + + g_mutex_sg = rt_mutex_create("sgtbles", RT_IPC_FLAG_FIFO); + RT_ASSERT(g_mutex_sg != RT_NULL); + + nu_pdma_chn_mask = ~NU_PDMA_CH_Msk; + rt_memset(nu_pdma_chn_arr, 0x00, sizeof(nu_pdma_chn_t)); + + NVIC_EnableIRQ(PDMA_IRQn); + + /* Initialize PDMA setting */ + PDMA_Open(PDMA, NU_PDMA_CH_Msk); + PDMA_Close(PDMA); + + rt_memset(&nu_pdma_sgtbl_arr[0], 0x00, sizeof(nu_pdma_sgtbl_arr)); + + /* Assign first SG table address as PDMA SG table base address */ + PDMA->SCATBA = (uint32_t)&nu_pdma_sgtbl_arr[0]; + + /* Initializa token pool. */ + rt_memset(&nu_pdma_sgtbl_token[0], 0xff, sizeof(nu_pdma_sgtbl_token)); + latest = NU_PDMA_SGTBL_POOL_SIZE / 32; + nu_pdma_sgtbl_token[latest] ^= ~((1 << (NU_PDMA_SGTBL_POOL_SIZE % 32)) - 1) ; + + nu_pdma_inited = 1; +} + +static void nu_pdma_channel_enable(int i32ChannID) +{ + PDMA_Open(PDMA, 1 << i32ChannID); +} + +static inline void nu_pdma_channel_disable(int i32ChannID) +{ + PDMA->CHCTL &= ~(1 << i32ChannID); +} + +static inline void nu_pdma_channel_reset(int i32ChannID) +{ + PDMA->CHRST = (1 << i32ChannID); +} + +void nu_pdma_channel_terminate(int i32ChannID) +{ + int i; + uint32_t u32EnabledChans; + int ch_mask = 0; + + if (!(nu_pdma_chn_mask & (1 << i32ChannID))) + goto exit_pdma_channel_terminate; + + rt_mutex_take(g_mutex_res, RT_WAITING_FOREVER); + + // Suspend all channels. + u32EnabledChans = nu_pdma_chn_mask & NU_PDMA_CH_Msk; + while ((i = nu_ctz(u32EnabledChans)) != 32) + { + ch_mask = (1 << i); + if (i == i32ChannID) + { + u32EnabledChans &= ~ch_mask; + continue; + } + + // Pause the channel + PDMA_PAUSE(PDMA, i); + + // Wait for channel to finish current transfer + while (PDMA->TACTSTS & ch_mask) { } + + u32EnabledChans &= ~ch_mask; + } //while + + // Reset specified channel ID + nu_pdma_channel_reset(i32ChannID); + + // Clean descriptor table control register. + PDMA->DSCT[i32ChannID].CTL = 0UL; + + // Resume all channels. + u32EnabledChans = nu_pdma_chn_mask & NU_PDMA_CH_Msk; + while ((i = nu_ctz(u32EnabledChans)) != 32) + { + ch_mask = (1 << i); + + PDMA->CHCTL |= ch_mask; + PDMA_Trigger(PDMA, i); + u32EnabledChans &= ~ch_mask; + } + + rt_mutex_release(g_mutex_res); + +exit_pdma_channel_terminate: + + return; +} + +static rt_err_t nu_pdma_timeout_set(int i32ChannID, int i32Timeout_us) +{ + rt_err_t ret = RT_EINVAL; + + if (!(nu_pdma_chn_mask & (1 << i32ChannID))) + goto exit_nu_pdma_timeout_set; + + nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_u32IdleTimeout_us = i32Timeout_us; + + if (i32Timeout_us && i32ChannID <= 1) // M480 limit + { + uint32_t u32ToClk_Max = 1000000 / (CLK_GetHCLKFreq() / (1 << 8)); + uint32_t u32Divider = (i32Timeout_us / u32ToClk_Max) / (1 << 16); + uint32_t u32TOutCnt = (i32Timeout_us / u32ToClk_Max) % (1 << 16); + + PDMA_DisableTimeout(PDMA, 1 << i32ChannID); + PDMA_EnableInt(PDMA, i32ChannID, PDMA_INT_TIMEOUT); // Interrupt type + + if (u32Divider > 7) + { + u32Divider = 7; + u32TOutCnt = (1 << 16); + } + PDMA->TOUTPSC |= (u32Divider << (PDMA_TOUTPSC_TOUTPSC1_Pos * i32ChannID)); + PDMA_SetTimeOut(PDMA, i32ChannID, 1, u32TOutCnt); + + ret = RT_EOK; + } + else + { + PDMA_DisableInt(PDMA, i32ChannID, PDMA_INT_TIMEOUT); // Interrupt type + PDMA_DisableTimeout(PDMA, 1 << i32ChannID); + } + +exit_nu_pdma_timeout_set: + + return -(ret); +} + +int nu_pdma_channel_allocate(int32_t i32PeripType) +{ + int i, i32PeripCtlIdx; + + nu_pdma_init(); + + if ((i32PeripCtlIdx = nu_pdma_peripheral_set(i32PeripType)) < 0) + goto exit_nu_pdma_channel_allocate; + + /* Find the position of first '0' in nu_pdma_chn_mask. */ + i = nu_cto(nu_pdma_chn_mask); + if (i != 32) + { + nu_pdma_chn_mask |= (1 << i); + rt_memset(nu_pdma_chn_arr + i - NU_PDMA_CH_Pos, 0x00, sizeof(nu_pdma_chn_t)); + + /* Set idx number of g_nu_pdma_peripheral_ctl_pool */ + nu_pdma_periph_ctrl_fill(i, i32PeripCtlIdx); + + /* Reset channel */ + nu_pdma_channel_reset(i); + + nu_pdma_channel_enable(i); + + return i; + } + +exit_nu_pdma_channel_allocate: + // No channel available + return -(RT_ERROR); +} + +rt_err_t nu_pdma_channel_free(int i32ChannID) +{ + rt_err_t ret = RT_EINVAL; + + if (! nu_pdma_inited) + goto exit_nu_pdma_channel_free; + + if (i32ChannID < NU_PDMA_CH_MAX && i32ChannID >= NU_PDMA_CH_Pos) + { + nu_pdma_chn_mask &= ~(1 << i32ChannID); + nu_pdma_channel_disable(i32ChannID); + ret = RT_EOK; + } +exit_nu_pdma_channel_free: + + return -(ret); +} + +rt_err_t nu_pdma_callback_register(int i32ChannID, nu_pdma_cb_handler_t pfnHandler, void *pvUserData, uint32_t u32EventFilter) +{ + rt_err_t ret = RT_EINVAL; + + if (!(nu_pdma_chn_mask & (1 << i32ChannID))) + goto exit_nu_pdma_callback_register; + + nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_pfnCBHandler = pfnHandler; + nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_pvUserData = pvUserData; + nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_u32EventFilter = u32EventFilter; + + ret = RT_EOK; + +exit_nu_pdma_callback_register: + + return -(ret) ; +} + +nu_pdma_cb_handler_t nu_pdma_callback_hijack(int i32ChannID, nu_pdma_cb_handler_t *ppfnHandler_Hijack, + void **ppvUserData_Hijack, uint32_t *pu32Events_Hijack) +{ + nu_pdma_cb_handler_t pfnHandler_Org = NULL; + void *pvUserData_Org; + uint32_t u32Events_Org; + + RT_ASSERT(ppfnHandler_Hijack != NULL); + RT_ASSERT(ppvUserData_Hijack != NULL); + RT_ASSERT(pu32Events_Hijack != NULL); + + if (!(nu_pdma_chn_mask & (1 << i32ChannID))) + goto exit_nu_pdma_callback_hijack; + + pfnHandler_Org = nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_pfnCBHandler; + pvUserData_Org = nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_pvUserData; + u32Events_Org = nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_u32EventFilter; + + nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_pfnCBHandler = *ppfnHandler_Hijack; + nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_pvUserData = *ppvUserData_Hijack; + nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_u32EventFilter = *pu32Events_Hijack; + + *ppfnHandler_Hijack = pfnHandler_Org; + *ppvUserData_Hijack = pvUserData_Org; + *pu32Events_Hijack = u32Events_Org; + +exit_nu_pdma_callback_hijack: + + return pfnHandler_Org; +} + +static int nu_pdma_non_transfer_count_get(int32_t i32ChannID) +{ + return ((PDMA->DSCT[i32ChannID].CTL & PDMA_DSCT_CTL_TXCNT_Msk) >> PDMA_DSCT_CTL_TXCNT_Pos) + 1; +} + +int nu_pdma_transferred_byte_get(int32_t i32ChannID, int32_t i32TriggerByteLen) +{ + int i32BitWidth = 0; + int cur_txcnt = 0; + + if (!(nu_pdma_chn_mask & (1 << i32ChannID))) + goto exit_nu_pdma_transferred_byte_get; + + i32BitWidth = PDMA->DSCT[i32ChannID].CTL & PDMA_DSCT_CTL_TXWIDTH_Msk; + i32BitWidth = (i32BitWidth == PDMA_WIDTH_8) ? 1 : (i32BitWidth == PDMA_WIDTH_16) ? 2 : (i32BitWidth == PDMA_WIDTH_32) ? 4 : 0; + + cur_txcnt = nu_pdma_non_transfer_count_get(i32ChannID); + + return (i32TriggerByteLen - (cur_txcnt) * i32BitWidth); + +exit_nu_pdma_transferred_byte_get: + + return -1; +} + +nu_pdma_memctrl_t nu_pdma_channel_memctrl_get(int i32ChannID) +{ + nu_pdma_memctrl_t eMemCtrl = eMemCtl_Undefined; + + if (!(nu_pdma_chn_mask & (1 << i32ChannID))) + goto exit_nu_pdma_channel_memctrl_get; + + eMemCtrl = nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_spPeripCtl.m_eMemCtl; + +exit_nu_pdma_channel_memctrl_get: + + return eMemCtrl; +} + +rt_err_t nu_pdma_channel_memctrl_set(int i32ChannID, nu_pdma_memctrl_t eMemCtrl) +{ + rt_err_t ret = RT_EINVAL; + nu_pdma_chn_t *psPdmaChann = &nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos]; + + + if (!(nu_pdma_chn_mask & (1 << i32ChannID))) + goto exit_nu_pdma_channel_memctrl_set; + else if ((eMemCtrl < eMemCtl_SrcFix_DstFix) || (eMemCtrl > eMemCtl_SrcInc_DstInc)) + goto exit_nu_pdma_channel_memctrl_set; + + /* PDMA_MEM/SAR_FIX/BURST mode is not supported. */ + if ((psPdmaChann->m_spPeripCtl.m_u32Peripheral == PDMA_MEM) && + ((eMemCtrl == eMemCtl_SrcFix_DstInc) || (eMemCtrl == eMemCtl_SrcFix_DstFix))) + goto exit_nu_pdma_channel_memctrl_set; + + nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_spPeripCtl.m_eMemCtl = eMemCtrl; + + ret = RT_EOK; + +exit_nu_pdma_channel_memctrl_set: + + return -(ret); +} + +static void nu_pdma_channel_memctrl_fill(nu_pdma_memctrl_t eMemCtl, uint32_t *pu32SrcCtl, uint32_t *pu32DstCtl) +{ + switch ((int)eMemCtl) + { + case eMemCtl_SrcFix_DstFix: + *pu32SrcCtl = PDMA_SAR_FIX; + *pu32DstCtl = PDMA_DAR_FIX; + break; + case eMemCtl_SrcFix_DstInc: + *pu32SrcCtl = PDMA_SAR_FIX; + *pu32DstCtl = PDMA_DAR_INC; + break; + case eMemCtl_SrcInc_DstFix: + *pu32SrcCtl = PDMA_SAR_INC; + *pu32DstCtl = PDMA_DAR_FIX; + break; + case eMemCtl_SrcInc_DstInc: + *pu32SrcCtl = PDMA_SAR_INC; + *pu32DstCtl = PDMA_DAR_INC; + break; + default: + break; + } +} + +/* This is for Scatter-gather DMA. */ +rt_err_t nu_pdma_desc_setup(int i32ChannID, nu_pdma_desc_t dma_desc, uint32_t u32DataWidth, uint32_t u32AddrSrc, + uint32_t u32AddrDst, int32_t i32TransferCnt, nu_pdma_desc_t next) +{ + nu_pdma_periph_ctl_t *psPeriphCtl = NULL; + + uint32_t u32SrcCtl = 0; + uint32_t u32DstCtl = 0; + + rt_err_t ret = RT_EINVAL; + + if (!dma_desc) + goto exit_nu_pdma_desc_setup; + else if (!(nu_pdma_chn_mask & (1 << i32ChannID))) + goto exit_nu_pdma_desc_setup; + else if (!(u32DataWidth == 8 || u32DataWidth == 16 || u32DataWidth == 32)) + goto exit_nu_pdma_desc_setup; + else if ((u32AddrSrc % (u32DataWidth / 8)) || (u32AddrDst % (u32DataWidth / 8))) + goto exit_nu_pdma_desc_setup; + + psPeriphCtl = &nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_spPeripCtl; + + nu_pdma_channel_memctrl_fill(psPeriphCtl->m_eMemCtl, &u32SrcCtl, &u32DstCtl); + + dma_desc->CTL = ((i32TransferCnt - 1) << PDMA_DSCT_CTL_TXCNT_Pos) | + ((u32DataWidth == 8) ? PDMA_WIDTH_8 : (u32DataWidth == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32) | + u32SrcCtl | + u32DstCtl | + PDMA_OP_BASIC; + + dma_desc->SA = u32AddrSrc; + dma_desc->DA = u32AddrDst; + dma_desc->NEXT = 0; /* Terminating node by default. */ + + if (psPeriphCtl->m_u32Peripheral == PDMA_MEM) + { + /* For M2M transfer */ + dma_desc->CTL |= (PDMA_REQ_BURST | PDMA_BURST_32); + } + else + { + /* For P2M and M2P transfer */ + dma_desc->CTL |= (PDMA_REQ_SINGLE); + } + + if (next) + { + /* Link to Next and modify to scatter-gather DMA mode. */ + dma_desc->CTL = (dma_desc->CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_SCATTER; + dma_desc->NEXT = (uint32_t)next - (PDMA->SCATBA); + } + + ret = RT_EOK; + +exit_nu_pdma_desc_setup: + + return -(ret); +} + +static int nu_pdma_sgtbls_token_allocate(void) +{ + int idx, i; + + int pool_size = sizeof(nu_pdma_sgtbl_token) / sizeof(uint32_t); + + for (i = 0; i < pool_size; i++) + { + if ((idx = nu_ctz(nu_pdma_sgtbl_token[i])) != 32) + { + nu_pdma_sgtbl_token[i] &= ~(1 << idx); + idx += i * 32; + return idx; + } + } + + /* No available */ + return -1; +} + +static void nu_pdma_sgtbls_token_free(nu_pdma_desc_t psSgtbls) +{ + int idx = (int)(psSgtbls - &nu_pdma_sgtbl_arr[0]); + RT_ASSERT(idx >= 0); + RT_ASSERT((idx + 1) <= NU_PDMA_SGTBL_POOL_SIZE); + nu_pdma_sgtbl_token[idx / 32] |= (1 << (idx % 32)); +} + +rt_err_t nu_pdma_sgtbls_allocate(nu_pdma_desc_t *ppsSgtbls, int num) +{ + int i, j, idx; + + RT_ASSERT(ppsSgtbls != NULL); + RT_ASSERT(num <= NU_PDMA_SG_TBL_MAXSIZE); + + rt_mutex_take(g_mutex_sg, RT_WAITING_FOREVER); + + for (i = 0; i < num; i++) + { + ppsSgtbls[i] = NULL; + /* Get token. */ + if ((idx = nu_pdma_sgtbls_token_allocate()) < 0) + { + rt_kprintf("No available sgtbl.\n"); + goto fail_nu_pdma_sgtbls_allocate; + } + + ppsSgtbls[i] = (nu_pdma_desc_t)&nu_pdma_sgtbl_arr[idx]; + } + + rt_mutex_release(g_mutex_sg); + + return RT_EOK; + +fail_nu_pdma_sgtbls_allocate: + + /* Release allocated tables. */ + for (j = 0; j < i; j++) + { + if (ppsSgtbls[j] != NULL) + { + nu_pdma_sgtbls_token_free(ppsSgtbls[j]); + } + ppsSgtbls[j] = NULL; + } + + rt_mutex_release(g_mutex_sg); + return -RT_ERROR; +} + +void nu_pdma_sgtbls_free(nu_pdma_desc_t *ppsSgtbls, int num) +{ + int i; + + RT_ASSERT(ppsSgtbls != NULL); + RT_ASSERT(num <= NU_PDMA_SG_TBL_MAXSIZE); + + rt_mutex_take(g_mutex_sg, RT_WAITING_FOREVER); + + for (i = 0; i < num; i++) + { + if (ppsSgtbls[i] != NULL) + { + nu_pdma_sgtbls_token_free(ppsSgtbls[i]); + } + ppsSgtbls[i] = NULL; + } + + rt_mutex_release(g_mutex_sg); +} + +static rt_err_t nu_pdma_sgtbls_valid(nu_pdma_desc_t head) +{ + uint32_t node_addr; + nu_pdma_desc_t node = head; + + do + { + node_addr = (uint32_t)node; + if ((node_addr < PDMA->SCATBA) || (node_addr - PDMA->SCATBA) >= NU_PDMA_SG_LIMITED_DISTANCE) + { + rt_kprintf("The distance is over %d between 0x%08x and 0x%08x. \n", NU_PDMA_SG_LIMITED_DISTANCE, PDMA->SCATBA, node); + rt_kprintf("Please use nu_pdma_sgtbl_allocate to allocate valid sg-table.\n"); + return RT_ERROR; + } + + node = (nu_pdma_desc_t)(node->NEXT + PDMA->SCATBA); + + } while (((uint32_t)node != PDMA->SCATBA) && (node != head)); + + return RT_EOK; +} + +static void _nu_pdma_transfer(int i32ChannID, uint32_t u32Peripheral, nu_pdma_desc_t head, uint32_t u32IdleTimeout_us) +{ + PDMA_DisableTimeout(PDMA, 1 << i32ChannID); + + PDMA_EnableInt(PDMA, i32ChannID, PDMA_INT_TRANS_DONE); + + nu_pdma_timeout_set(i32ChannID, u32IdleTimeout_us); + + /* Set scatter-gather mode and head */ + PDMA_SetTransferMode(PDMA, + i32ChannID, + u32Peripheral, + (head != NULL) ? 1 : 0, + (uint32_t)head); + + /* If peripheral is M2M, trigger it. */ + if (u32Peripheral == PDMA_MEM) + PDMA_Trigger(PDMA, i32ChannID); +} + +rt_err_t nu_pdma_transfer(int i32ChannID, uint32_t u32DataWidth, uint32_t u32AddrSrc, uint32_t u32AddrDst, int32_t i32TransferCnt, uint32_t u32IdleTimeout_us) +{ + rt_err_t ret = RT_EINVAL; + + nu_pdma_periph_ctl_t *psPeriphCtl = NULL; + + if (!(nu_pdma_chn_mask & (1 << i32ChannID))) + goto exit_nu_pdma_transfer; + + psPeriphCtl = &nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_spPeripCtl; + + ret = nu_pdma_desc_setup(i32ChannID, + &PDMA->DSCT[i32ChannID], + u32DataWidth, + u32AddrSrc, + u32AddrDst, + i32TransferCnt, + NULL); + if (ret != RT_EOK) + goto exit_nu_pdma_transfer; + + _nu_pdma_transfer(i32ChannID, psPeriphCtl->m_u32Peripheral, NULL, u32IdleTimeout_us); + + ret = RT_EOK; + +exit_nu_pdma_transfer: + + return -(ret); +} + +rt_err_t nu_pdma_sg_transfer(int i32ChannID, nu_pdma_desc_t head, uint32_t u32IdleTimeout_us) +{ + rt_err_t ret = RT_EINVAL; + nu_pdma_periph_ctl_t *psPeriphCtl = NULL; + + if (!head) + goto exit_nu_pdma_sg_transfer; + else if (!(nu_pdma_chn_mask & (1 << i32ChannID))) + goto exit_nu_pdma_sg_transfer; + else if ( (ret=nu_pdma_sgtbls_valid(head)) != RT_EOK ) /* Check SG-tbls. */ + goto exit_nu_pdma_sg_transfer; + + psPeriphCtl = &nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_spPeripCtl; + + _nu_pdma_transfer(i32ChannID, psPeriphCtl->m_u32Peripheral, head, u32IdleTimeout_us); + + ret = RT_EOK; + +exit_nu_pdma_sg_transfer: + + return -(ret); +} + +void PDMA_IRQHandler(void) +{ + int i; + + /* enter interrupt */ + rt_interrupt_enter(); + + uint32_t intsts = PDMA_GET_INT_STATUS(PDMA); + uint32_t abtsts = PDMA_GET_ABORT_STS(PDMA); + uint32_t tdsts = PDMA_GET_TD_STS(PDMA); + uint32_t reqto = intsts & (PDMA_INTSTS_REQTOF0_Msk | PDMA_INTSTS_REQTOF1_Msk); + uint32_t reqto_ch = ((reqto & PDMA_INTSTS_REQTOF0_Msk) ? (1 << 0) : 0x0) | ((reqto & PDMA_INTSTS_REQTOF1_Msk) ? (1 << 1) : 0x0); + + int allch_sts = (reqto_ch | tdsts | abtsts); + + // Abort + if (intsts & PDMA_INTSTS_ABTIF_Msk) + { + // Clear all Abort flags + PDMA_CLR_ABORT_FLAG(PDMA, abtsts); + } + + // Transfer done + if (intsts & PDMA_INTSTS_TDIF_Msk) + { + // Clear all transfer done flags + PDMA_CLR_TD_FLAG(PDMA, tdsts); + } + + // Timeout + if (reqto) + { + // Clear all Timeout flags + PDMA->INTSTS = reqto; + } + + // Find the position of first '1' in allch_sts. + while ((i = nu_ctz(allch_sts)) != 32) + { + int ch_mask = (1 << i); + + if (nu_pdma_chn_mask & ch_mask) + { + int ch_event = 0; + nu_pdma_chn_t *dma_chn = nu_pdma_chn_arr + i - NU_PDMA_CH_Pos; + + if (dma_chn->m_pfnCBHandler) + { + if (abtsts & ch_mask) + { + ch_event |= NU_PDMA_EVENT_ABORT; + } + + if (tdsts & ch_mask) ch_event |= NU_PDMA_EVENT_TRANSFER_DONE; + + if (reqto_ch & ch_mask) + { + PDMA_DisableTimeout(PDMA, ch_mask); + ch_event |= NU_PDMA_EVENT_TIMEOUT; + } + + if (dma_chn->m_u32EventFilter & ch_event) + dma_chn->m_pfnCBHandler(dma_chn->m_pvUserData, ch_event); + + if (reqto_ch & ch_mask) + nu_pdma_timeout_set(i, nu_pdma_chn_arr[i - NU_PDMA_CH_Pos].m_u32IdleTimeout_us); + + }//if(dma_chn->handler) + } //if (nu_pdma_chn_mask & ch_mask) + + // Clear the served bit. + allch_sts &= ~ch_mask; + + } //while + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void nu_pdma_memfun_actor_init(void) +{ + int i = 0 ; + nu_pdma_init(); + for (i = 0; i < NU_PDMA_MEMFUN_ACTOR_MAX; i++) + { + rt_memset(&nu_pdma_memfun_actor_arr[i], 0, sizeof(struct nu_pdma_memfun_actor)); + if (-(RT_ERROR) != (nu_pdma_memfun_actor_arr[i].m_i32ChannID = nu_pdma_channel_allocate(PDMA_MEM))) + { + nu_pdma_memfun_actor_arr[i].m_psSemMemFun = rt_sem_create("memactor_sem", 0, RT_IPC_FLAG_FIFO); + } + else + break; + } + if (i) + { + nu_pdma_memfun_actor_maxnum = i; + nu_pdma_memfun_actor_mask = ~(((1 << i) - 1)); + nu_pdma_memfun_actor_pool_sem = rt_sem_create("mempool_sem", nu_pdma_memfun_actor_maxnum, RT_IPC_FLAG_FIFO); + nu_pdma_memfun_actor_pool_lock = rt_mutex_create("mempool_lock", RT_IPC_FLAG_FIFO); + } +} + +static void nu_pdma_memfun_cb(void *pvUserData, uint32_t u32Events) +{ + nu_pdma_memfun_actor_t psMemFunActor = (nu_pdma_memfun_actor_t)pvUserData; + psMemFunActor->m_u32Result = u32Events; + rt_sem_release(psMemFunActor->m_psSemMemFun); +} + +static int nu_pdma_memfun_employ(void) +{ + int idx = -1 ; + + /* Headhunter */ + if (nu_pdma_memfun_actor_pool_sem && (rt_sem_take(nu_pdma_memfun_actor_pool_sem, RT_WAITING_FOREVER) == RT_EOK)) + { + rt_mutex_take(nu_pdma_memfun_actor_pool_lock, RT_WAITING_FOREVER); + /* Find the position of first '0' in nu_pdma_memfun_actor_mask. */ + idx = nu_cto(nu_pdma_memfun_actor_mask); + if (idx != 32) + { + nu_pdma_memfun_actor_mask |= (1 << idx); + } + else + { + idx = -1; + } + rt_mutex_release(nu_pdma_memfun_actor_pool_lock); + } + + return idx; +} + +static rt_size_t nu_pdma_memfun(void *dest, void *src, uint32_t u32DataWidth, unsigned int count, nu_pdma_memctrl_t eMemCtl) +{ + nu_pdma_memfun_actor_t psMemFunActor = NULL; + int idx; + rt_size_t ret = 0; + while (1) + { + /* Employ actor */ + if ((idx = nu_pdma_memfun_employ()) < 0) + continue; + + psMemFunActor = &nu_pdma_memfun_actor_arr[idx]; + + psMemFunActor->m_u32TrigTransferCnt = count; + + /* Set PDMA memory control to eMemCtl. */ + nu_pdma_channel_memctrl_set(psMemFunActor->m_i32ChannID, eMemCtl); + + /* Register ISR callback function */ + nu_pdma_callback_register(psMemFunActor->m_i32ChannID, nu_pdma_memfun_cb, (void *)psMemFunActor, NU_PDMA_EVENT_ABORT | NU_PDMA_EVENT_TRANSFER_DONE); + + psMemFunActor->m_u32Result = 0; + + /* Trigger it */ + nu_pdma_transfer(psMemFunActor->m_i32ChannID, u32DataWidth, (uint32_t)src, (uint32_t)dest, count, 0); + + /* Wait it done. */ + rt_sem_take(psMemFunActor->m_psSemMemFun, RT_WAITING_FOREVER); + + /* Give result if get NU_PDMA_EVENT_TRANSFER_DONE.*/ + if (psMemFunActor->m_u32Result & NU_PDMA_EVENT_TRANSFER_DONE) + { + ret = psMemFunActor->m_u32TrigTransferCnt; + } + else + { + ret = psMemFunActor->m_u32TrigTransferCnt - nu_pdma_non_transfer_count_get(psMemFunActor->m_i32ChannID); + } + + /* Terminate it if get ABORT event */ + if (psMemFunActor->m_u32Result & NU_PDMA_EVENT_ABORT) + { + nu_pdma_channel_terminate(psMemFunActor->m_i32ChannID); + } + + rt_mutex_take(nu_pdma_memfun_actor_pool_lock, RT_WAITING_FOREVER); + nu_pdma_memfun_actor_mask &= ~(1 << idx); + rt_mutex_release(nu_pdma_memfun_actor_pool_lock); + + /* Fire actor */ + rt_sem_release(nu_pdma_memfun_actor_pool_sem); + + break; + } + + return ret; +} + +rt_size_t nu_pdma_mempush(void *dest, void *src, uint32_t data_width, unsigned int transfer_count) +{ + if (data_width == 8 || data_width == 16 || data_width == 32) + return nu_pdma_memfun(dest, src, data_width, transfer_count, eMemCtl_SrcInc_DstFix); + return 0; +} + +void *nu_pdma_memcpy(void *dest, void *src, unsigned int count) +{ + if (count == nu_pdma_memfun(dest, src, 8, count, eMemCtl_SrcInc_DstInc)) + return dest; + else + return NULL; +} + +/** + * PDMA memfun actor initialization + */ +int rt_hw_pdma_memfun_init(void) +{ + nu_pdma_memfun_actor_init(); + return 0; +} +INIT_DEVICE_EXPORT(rt_hw_pdma_memfun_init); +#endif // #if defined(BSP_USING_PDMA) diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_pdma.h b/bsp/nuvoton/libraries/m480/rtt_port/drv_pdma.h new file mode 100644 index 0000000000000000000000000000000000000000..e379323633e8eea28eb67a53e983f103115b6eeb --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_pdma.h @@ -0,0 +1,71 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-2-7 Wayne First version +* +******************************************************************************/ + +#ifndef __DRV_PDMA_H__ +#define __DRV_PDMA_H__ + +#include +#include +#include + +#ifndef NU_PDMA_SGTBL_POOL_SIZE + #define NU_PDMA_SGTBL_POOL_SIZE (16) +#endif + +#define NU_PDMA_CAP_NONE (0 << 0) + +#define NU_PDMA_EVENT_ABORT (1 << 0) +#define NU_PDMA_EVENT_TRANSFER_DONE (1 << 1) +#define NU_PDMA_EVENT_TIMEOUT (1 << 2) +#define NU_PDMA_EVENT_ALL (NU_PDMA_EVENT_ABORT | NU_PDMA_EVENT_TRANSFER_DONE | NU_PDMA_EVENT_TIMEOUT) +#define NU_PDMA_EVENT_MASK NU_PDMA_EVENT_ALL +#define NU_PDMA_UNUSED (-1) + +#define NU_PDMA_SG_LIMITED_DISTANCE ((PDMA_DSCT_NEXT_NEXT_Msk>>PDMA_DSCT_NEXT_NEXT_Pos)+1) + +typedef enum +{ + eMemCtl_SrcFix_DstFix, + eMemCtl_SrcFix_DstInc, + eMemCtl_SrcInc_DstFix, + eMemCtl_SrcInc_DstInc, + eMemCtl_Undefined = (-1) +} nu_pdma_memctrl_t; + +typedef DSCT_T *nu_pdma_desc_t; + +typedef void (*nu_pdma_cb_handler_t)(void *, uint32_t); + +int nu_pdma_channel_allocate(int32_t i32PeripType); +rt_err_t nu_pdma_channel_free(int i32ChannID); +rt_err_t nu_pdma_callback_register(int i32ChannID, nu_pdma_cb_handler_t pfnHandler, void *pvUserData, uint32_t u32EventFilter); +rt_err_t nu_pdma_transfer(int i32ChannID, uint32_t u32DataWidth, uint32_t u32AddrSrc, uint32_t u32AddrDst, int32_t i32TransferCnt, uint32_t u32IdleTimeout_us); +int nu_pdma_transferred_byte_get(int32_t i32ChannID, int32_t i32TriggerByteLen); +void nu_pdma_channel_terminate(int i32ChannID); +nu_pdma_memctrl_t nu_pdma_channel_memctrl_get(int i32ChannID); +rt_err_t nu_pdma_channel_memctrl_set(int i32ChannID, nu_pdma_memctrl_t eMemCtrl); + +nu_pdma_cb_handler_t nu_pdma_callback_hijack(int i32ChannID, nu_pdma_cb_handler_t *ppfnHandler_Hijack, + void **ppvUserData_Hijack, uint32_t *pu32EventFilter_Hijack); + +// For scatter-gather DMA +rt_err_t nu_pdma_desc_setup(int i32ChannID, nu_pdma_desc_t dma_desc, uint32_t u32DataWidth, uint32_t u32AddrSrc, uint32_t u32AddrDst, int32_t TransferCnt, nu_pdma_desc_t next); +rt_err_t nu_pdma_sg_transfer(int i32ChannID, nu_pdma_desc_t head, uint32_t u32IdleTimeout_us); +rt_err_t nu_pdma_sgtbls_allocate(nu_pdma_desc_t *ppsSgtbls, int num); +void nu_pdma_sgtbls_free(nu_pdma_desc_t *ppsSgtbls, int num); + + +// For memory actor +void *nu_pdma_memcpy(void *dest, void *src, unsigned int count); +rt_size_t nu_pdma_mempush(void *dest, void *src, uint32_t data_width, unsigned int transfer_count); + +#endif // __DRV_PDMA_H___ diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_qei.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_qei.c new file mode 100644 index 0000000000000000000000000000000000000000..3be7e62b31e7537c28cac10bb5bcc114465e68ad --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_qei.c @@ -0,0 +1,305 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-4-20 FYChou First version +* +******************************************************************************/ + +#include + +#if defined(BSP_USING_QEI) +#include +#include "NuMicro.h" + +/* Private define ---------------------------------------------------------------*/ + +/* Private typedef --------------------------------------------------------------*/ +struct nu_qei +{ + struct rt_pulse_encoder_device dev; + char *name; + QEI_T *qei_base; + rt_uint32_t max_cntval; + rt_uint32_t cmp_val; + IRQn_Type IRQn; + rt_uint8_t qei_type; + rt_uint8_t qei_flag; +}; +typedef struct nu_qei *nu_qei_t; + + +/* Private functions ------------------------------------------------------------*/ +static rt_uint32_t nu_qei_type(struct rt_pulse_encoder_device *pulse_encoder); +static rt_err_t nu_qei_init(struct rt_pulse_encoder_device *pulse_encoder); +static rt_int32_t nu_qei_get_count(struct rt_pulse_encoder_device *pulse_encoder); +static rt_err_t nu_qei_clear_count(struct rt_pulse_encoder_device *pulse_encoder); +static rt_err_t nu_qei_control(struct rt_pulse_encoder_device *pulse_encoder, rt_uint32_t cmd, void *args); + +/* Public functions -------------------------------------------------------------*/ +rt_int32_t nu_qei_get_maxval(rt_device_t *pulse_encoder); +rt_int32_t nu_qei_get_cmpval(rt_device_t *pulse_encoder); +rt_int32_t nu_qei_get_type(rt_device_t *pulse_encoder); +void nu_qei_set_maxval_type(rt_device_t *pulse_encoder, rt_uint32_t u32val, rt_uint8_t u8type); +void nu_qei_set_cmpval(rt_device_t *pulse_encoder, rt_uint32_t u32val); + +/* Private variables ------------------------------------------------------------*/ +static struct nu_qei nu_qei_arr [] = +{ +#if defined(BSP_USING_QEI0) + { + .name = "qei0", + .qei_base = QEI0, + .max_cntval = 1000, + .cmp_val = 100, + .IRQn = QEI0_IRQn, + .qei_type = AB_PHASE_PULSE_ENCODER, + .qei_flag = 0 + }, +#endif + +#if defined(BSP_USING_QEI1) + { + .name = "qei1", + .qei_base = QEI1, + .max_cntval = 1000, + .cmp_val = 100, + .IRQn = QEI1_IRQn, + .qei_type = AB_PHASE_PULSE_ENCODER, + .qei_flag = 0 + }, +#endif + + {0} +}; + +static const struct rt_pulse_encoder_ops nu_qei_ops = +{ + .init = nu_qei_init, + .get_count = nu_qei_get_count, + .clear_count = nu_qei_clear_count, + .control = nu_qei_control, +}; +typedef struct rt_pulse_encoder_ops *nu_qei_ops_t; + +/* Public variables -------------------------------------------------------------*/ + + +static rt_uint32_t nu_qei_type(struct rt_pulse_encoder_device *pulse_encoder) +{ + rt_uint32_t u32type; + switch (pulse_encoder->type) + { + case SINGLE_PHASE_PULSE_ENCODER: + u32type = (((nu_qei_t)pulse_encoder)->cmp_val) ? QEI_CTL_X2_COMPARE_COUNTING_MODE : QEI_CTL_X2_FREE_COUNTING_MODE; + break; + + case UNKNOWN_PULSE_ENCODER_TYPE: + case AB_PHASE_PULSE_ENCODER: + default: + u32type = (((nu_qei_t)pulse_encoder)->cmp_val) ? QEI_CTL_X4_COMPARE_COUNTING_MODE : QEI_CTL_X4_FREE_COUNTING_MODE; + break; + } + + return u32type; +} + +static rt_err_t nu_qei_init(struct rt_pulse_encoder_device *pulse_encoder) +{ + rt_uint32_t u32type; + QEI_T *qui_base; + + RT_ASSERT(pulse_encoder != RT_NULL); + qui_base = ((nu_qei_t)pulse_encoder)->qei_base; + + /* enable noise filter */ + QEI_ENABLE_NOISE_FILTER(qui_base, QEI_CTL_NFCLKSEL_DIV2); + + /* set qei mode */ + u32type = nu_qei_type(pulse_encoder); + + /* set compare value and interrupt */ + if (((nu_qei_t)pulse_encoder)->cmp_val) + { + QEI_SET_CNT_CMP(qui_base, ((nu_qei_t)pulse_encoder)->cmp_val); + QEI_EnableInt(qui_base, QEI_CTL_CMPIEN_Msk); + QEI_ENABLE_CNT_CMP(qui_base); + NVIC_EnableIRQ(((nu_qei_t)pulse_encoder)->IRQn); + } + QEI_Open(qui_base, u32type, ((nu_qei_t)pulse_encoder)->max_cntval); + + + return RT_EOK; +} + +static rt_int32_t nu_qei_get_count(struct rt_pulse_encoder_device *pulse_encoder) +{ + QEI_T *qui_base; + RT_ASSERT(pulse_encoder != RT_NULL); + qui_base = ((nu_qei_t)pulse_encoder)->qei_base; + return (rt_int32_t)QEI_GET_CNT_VALUE(qui_base); +} + + +static rt_err_t nu_qei_clear_count(struct rt_pulse_encoder_device *pulse_encoder) +{ + QEI_T *qui_base; + RT_ASSERT(pulse_encoder != RT_NULL); + qui_base = ((nu_qei_t)pulse_encoder)->qei_base; + QEI_Stop(qui_base); + QEI_SET_CNT_VALUE(qui_base, 0); + QEI_Start(qui_base); + return RT_EOK; +} + +static rt_err_t nu_qei_control(struct rt_pulse_encoder_device *pulse_encoder, rt_uint32_t cmd, void *args) +{ + rt_err_t result; + QEI_T *qui_base; + + RT_ASSERT(pulse_encoder != RT_NULL); + qui_base = ((nu_qei_t)pulse_encoder)->qei_base; + + RT_ASSERT(cmd != RT_NULL); + + result = RT_EOK; + + switch (cmd) + { + case PULSE_ENCODER_CMD_ENABLE: + QEI_Start(qui_base); + if (((nu_qei_t)pulse_encoder)->cmp_val) + { + QEI_EnableInt(qui_base, QEI_CTL_CMPIEN_Msk); + QEI_ENABLE_CNT_CMP(qui_base); + NVIC_EnableIRQ(((nu_qei_t)pulse_encoder)->IRQn); + } + break; + case PULSE_ENCODER_CMD_DISABLE: + if (((nu_qei_t)pulse_encoder)->cmp_val) + { + QEI_DisableInt(qui_base, QEI_CTL_CMPIEN_Msk); + QEI_DISABLE_CNT_CMP(qui_base); + NVIC_DisableIRQ(((nu_qei_t)pulse_encoder)->IRQn); + } + QEI_Stop(qui_base); + break; + default: + result = -RT_ENOSYS; + break; + } + + return result; +} + +#if defined(BSP_USING_QEI0) +/* QEI0 interrupt entry */ +void QEI0_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if (QEI_GET_INT_FLAG(nu_qei_arr[0].qei_base, QEI_STATUS_CMPF_Msk)) + { + nu_qei_arr[0].qei_flag = 1; + QEI_CLR_INT_FLAG(nu_qei_arr[0].qei_base, QEI_STATUS_CMPF_Msk); + rt_kprintf("QEI0 CMP flag rising\n") ; + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(BSP_USING_QEI1) +/* QEI1 interrupt entry */ +void QEI1_IRQHandler(void) +{ + + /* enter interrupt */ + rt_interrupt_enter(); + + if (QEI_GET_INT_FLAG(nu_qei_arr[1].qei_base, QEI_STATUS_CMPF_Msk)) + { + nu_qei_arr[1].qei_flag = 1; + QEI_CLR_INT_FLAG(nu_qei_arr[1].qei_base, QEI_STATUS_CMPF_Msk); + rt_kprintf("QEI1 CMP flag rising\n") ; + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +rt_int32_t nu_qei_get_maxval(rt_device_t *pulse_encoder) +{ + return ((nu_qei_t) * pulse_encoder)->max_cntval; +} + +rt_int32_t nu_qei_get_cmpval(rt_device_t *pulse_encoder) +{ + return ((nu_qei_t) * pulse_encoder)->cmp_val; +} + +rt_int32_t nu_qei_get_type(rt_device_t *pulse_encoder) +{ + return ((nu_qei_t) * pulse_encoder)->qei_type; +} + +void nu_qei_set_maxval_type(rt_device_t *pulse_encoder, rt_uint32_t u32val, rt_uint8_t u8type) +{ + QEI_T *qui_base; + RT_ASSERT(pulse_encoder != RT_NULL); + qui_base = ((nu_qei_t) * pulse_encoder)->qei_base; + + RT_ASSERT(u8type <= AB_PHASE_PULSE_ENCODER); + ((nu_qei_t)*pulse_encoder)->qei_type = u8type; + ((nu_qei_t)*pulse_encoder)->dev.type = (enum rt_pulse_encoder_type)u8type; + ((nu_qei_t)*pulse_encoder)->max_cntval = u32val; + QEI_Open(qui_base, nu_qei_type(&(((nu_qei_t)*pulse_encoder)->dev)), u32val); +} + +void nu_qei_set_cmpval(rt_device_t *pulse_encoder, rt_uint32_t u32val) +{ + QEI_T *qui_base; + RT_ASSERT(pulse_encoder != RT_NULL); + qui_base = ((nu_qei_t) * pulse_encoder)->qei_base; + + ((nu_qei_t)*pulse_encoder)->cmp_val = u32val; + QEI_SET_CNT_CMP(qui_base, ((nu_qei_t)*pulse_encoder)->cmp_val); + + if (((nu_qei_t)*pulse_encoder)->cmp_val) + { + QEI_EnableInt(qui_base, QEI_CTL_CMPIEN_Msk); + QEI_ENABLE_CNT_CMP(qui_base); + NVIC_EnableIRQ(((nu_qei_t)*pulse_encoder)->IRQn); + } + else + { + QEI_DisableInt(qui_base, QEI_CTL_CMPIEN_Msk); + QEI_DISABLE_CNT_CMP(qui_base); + NVIC_DisableIRQ(((nu_qei_t)*pulse_encoder)->IRQn); + } +} + + +int rt_hw_qei_init(void) +{ + int result = RT_ERROR; + int nu_sel = 0; + while (nu_qei_arr[nu_sel].name != 0) + { + nu_qei_arr[nu_sel].dev.type = (enum rt_pulse_encoder_type)nu_qei_arr[nu_sel].qei_type; + nu_qei_arr[nu_sel].dev.ops = &nu_qei_ops; + + result = rt_device_pulse_encoder_register((void *)&nu_qei_arr[nu_sel], nu_qei_arr[nu_sel].name, &(nu_qei_arr[nu_sel].qei_flag)); + RT_ASSERT(result == RT_EOK); + nu_sel++; + } + return result; +} +INIT_APP_EXPORT(rt_hw_qei_init); + +#endif /* BSP_USING_QEI */ diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_qei.h b/bsp/nuvoton/libraries/m480/rtt_port/drv_qei.h new file mode 100644 index 0000000000000000000000000000000000000000..ae8f5a65eb4c14b3803eac6e72e926e3203f1ea8 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_qei.h @@ -0,0 +1,30 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-4-20 FYChou First version +* +* Tips: +* QEI compare interrupt flag *(pulse_encoder->user_data): If compare value is +* not null, after execute device init, compare interrupt will be enabled automatic. +* When the interrupt occur, interrupt flag will be set 1. +* +******************************************************************************/ + +#ifndef __DRV_QEI_H__ +#define __DRV_QEI_H__ + +#include + +rt_int32_t nu_qei_get_maxval(rt_device_t *pulse_encoder); +rt_int32_t nu_qei_get_cmpval(rt_device_t *pulse_encoder); +rt_int32_t nu_qei_get_type(rt_device_t *pulse_encoder); +void nu_qei_set_maxval_type(rt_device_t *pulse_encoder, rt_uint32_t u32val, rt_uint8_t u8type); +void nu_qei_set_cmpval(rt_device_t *pulse_encoder, rt_uint32_t u32val); + + +#endif // __DRV_QEI_H___ diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_qspi.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_qspi.c new file mode 100644 index 0000000000000000000000000000000000000000..a39e0716392a22b1e707bbc06741c4495f28b4df --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_qspi.c @@ -0,0 +1,407 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-5-19 YHKuo First version +* +******************************************************************************/ +#include + +#if defined(BSP_USING_QSPI) +#include +#include + +#include + +/* Private define ---------------------------------------------------------------*/ +enum +{ + QSPI_START = -1, +#if defined(BSP_USING_QSPI0) + QSPI0_IDX, +#endif +#if defined(BSP_USING_QSPI1) + QSPI1_IDX, +#endif + QSPI_CNT +}; + +/* Private typedef --------------------------------------------------------------*/ + +/* Private functions ------------------------------------------------------------*/ +static rt_err_t nu_qspi_bus_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration); +static rt_uint32_t nu_qspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_message *message); +static int nu_qspi_register_bus(struct nu_spi *qspi_bus, const char *name); + +/* Public functions -------------------------------------------------------------*/ + +/* Private variables ------------------------------------------------------------*/ +static struct rt_spi_ops nu_qspi_poll_ops = +{ + .configure = nu_qspi_bus_configure, + .xfer = nu_qspi_bus_xfer, +}; + +static struct nu_spi nu_qspi_arr [] = +{ +#if defined(BSP_USING_QSPI0) + { + .name = "qspi0", + .spi_base = (SPI_T *)QSPI0, + +#if defined(BSP_USING_QSPI_PDMA) +#if defined(BSP_USING_QSPI0_PDMA) + .pdma_perp_tx = PDMA_QSPI0_TX, + .pdma_perp_rx = PDMA_QSPI0_RX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + }, +#endif +#if defined(BSP_USING_QSPI1) + { + .name = "qspi1", + .spi_base = (SPI_T *)QSPI1, + +#if defined(BSP_USING_QSPI_PDMA) +#if defined(BSP_USING_QSPI1_PDMA) + .pdma_perp_tx = PDMA_QSPI1_TX, + .pdma_perp_rx = PDMA_QSPI1_RX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + }, +#endif + {0} +}; /* qspi nu_qspi */ + +static rt_err_t nu_qspi_bus_configure(struct rt_spi_device *device, + struct rt_spi_configuration *configuration) +{ + struct nu_spi *spi_bus; + uint32_t u32SPIMode; + uint32_t u32BusClock; + rt_err_t ret = RT_EOK; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(configuration != RT_NULL); + + spi_bus = (struct nu_spi *) device->bus; + + /* Check mode */ + switch (configuration->mode & RT_SPI_MODE_3) + { + case RT_SPI_MODE_0: + u32SPIMode = SPI_MODE_0; + break; + case RT_SPI_MODE_1: + u32SPIMode = SPI_MODE_1; + break; + case RT_SPI_MODE_2: + u32SPIMode = SPI_MODE_2; + break; + case RT_SPI_MODE_3: + u32SPIMode = SPI_MODE_3; + break; + default: + ret = RT_EIO; + goto exit_nu_qspi_bus_configure; + } + + /* Check data width */ + if (!(configuration->data_width == 8 || + configuration->data_width == 16 || + configuration->data_width == 24 || + configuration->data_width == 32)) + { + ret = RT_EINVAL; + goto exit_nu_qspi_bus_configure; + } + + /* Try to set clock and get actual spi bus clock */ + u32BusClock = QSPI_SetBusClock((QSPI_T *)spi_bus->spi_base, configuration->max_hz); + if (configuration->max_hz > u32BusClock) + { + rt_kprintf("%s clock max frequency is %dHz (!= %dHz)\n", spi_bus->name, u32BusClock, configuration->max_hz); + configuration->max_hz = u32BusClock; + } + + /* Need to initialize new configuration? */ + if (rt_memcmp(configuration, &spi_bus->configuration, sizeof(struct rt_spi_configuration)) != 0) + { + rt_memcpy(&spi_bus->configuration, configuration, sizeof(struct rt_spi_configuration)); + + QSPI_Open((QSPI_T *)spi_bus->spi_base, SPI_MASTER, u32SPIMode, configuration->data_width, u32BusClock); + + if (configuration->mode & RT_SPI_CS_HIGH) + { + /* Set CS pin to LOW */ + SPI_SET_SS_LOW(spi_bus->spi_base); + } + else + { + /* Set CS pin to HIGH */ + SPI_SET_SS_HIGH(spi_bus->spi_base); + } + + if (configuration->mode & RT_SPI_MSB) + { + /* Set sequence to MSB first */ + SPI_SET_MSB_FIRST(spi_bus->spi_base); + } + else + { + /* Set sequence to LSB first */ + SPI_SET_LSB_FIRST(spi_bus->spi_base); + } + } + + /* Clear SPI RX FIFO */ + nu_spi_drain_rxfifo(spi_bus->spi_base); + +exit_nu_qspi_bus_configure: + + return -(ret); +} + +#if defined(RT_SFUD_USING_QSPI) +static int nu_qspi_mode_config(struct nu_spi *qspi_bus, uint8_t *tx, uint8_t *rx, int qspi_lines) +{ + QSPI_T *qspi_base = (QSPI_T *)qspi_bus->spi_base; + if (qspi_lines > 1) + { + if (tx) + { + switch (qspi_lines) + { + case 2: + QSPI_ENABLE_DUAL_OUTPUT_MODE(qspi_base); + break; + case 4: + QSPI_ENABLE_QUAD_OUTPUT_MODE(qspi_base); + break; + } + } + else + { + switch (qspi_lines) + { + case 2: + QSPI_ENABLE_DUAL_INPUT_MODE(qspi_base); + break; + case 4: + QSPI_ENABLE_QUAD_INPUT_MODE(qspi_base); + break; + } + } + } + else + { + QSPI_DISABLE_DUAL_MODE(qspi_base); + QSPI_DISABLE_QUAD_MODE(qspi_base); + } + return qspi_lines; +} +#endif + +static rt_uint32_t nu_qspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ + struct nu_spi *qspi_bus; + struct rt_qspi_configuration *qspi_configuration; +#if defined(RT_SFUD_USING_QSPI) + struct rt_qspi_message *qspi_message; + int last = 1; +#endif + uint8_t bytes_per_word; + QSPI_T *qspi_base; + int len = 0; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(message != RT_NULL); + + qspi_bus = (struct nu_spi *) device->bus; + qspi_base = (QSPI_T *)qspi_bus->spi_base; + qspi_configuration = &qspi_bus->configuration; + + bytes_per_word = qspi_configuration->parent.data_width / 8; + + if (message->cs_take && !(qspi_configuration->parent.mode & RT_SPI_NO_CS)) + { + if (qspi_configuration->parent.mode & RT_SPI_CS_HIGH) + { + QSPI_SET_SS_HIGH(qspi_base); + } + else + { + QSPI_SET_SS_LOW(qspi_base); + } + } + +#if defined(RT_SFUD_USING_QSPI) + qspi_message = (struct rt_qspi_message *)message; + + /* Command + Address + Dummy + Data */ + /* Command stage */ + if (qspi_message->instruction.content != 0) + { + last = nu_qspi_mode_config(qspi_bus, (uint8_t *) &qspi_message->instruction.content, RT_NULL, qspi_message->instruction.qspi_lines); + nu_spi_transfer((struct nu_spi *)qspi_bus, + (uint8_t *) &qspi_message->instruction.content, + RT_NULL, + 1, + 1); + } + + /* Address stage */ + if (qspi_message->address.size != 0) + { + uint32_t u32ReversedAddr = 0; + uint32_t u32AddrNumOfByte = qspi_message->address.size / 8; + switch (u32AddrNumOfByte) + { + case 1: + u32ReversedAddr = (qspi_message->address.content & 0xff); + break; + case 2: + nu_set16_be((uint8_t *)&u32ReversedAddr, qspi_message->address.content); + break; + case 3: + nu_set24_be((uint8_t *)&u32ReversedAddr, qspi_message->address.content); + break; + case 4: + nu_set32_be((uint8_t *)&u32ReversedAddr, qspi_message->address.content); + break; + default: + RT_ASSERT(0); + break; + } + last = nu_qspi_mode_config(qspi_bus, (uint8_t *)&u32ReversedAddr, RT_NULL, qspi_message->address.qspi_lines); + nu_spi_transfer((struct nu_spi *)qspi_bus, + (uint8_t *) &u32ReversedAddr, + RT_NULL, + u32AddrNumOfByte, + 1); + } + + /* Dummy_cycles stage */ + if (qspi_message->dummy_cycles != 0) + { + qspi_bus->dummy = 0xff; + + last = nu_qspi_mode_config(qspi_bus, (uint8_t *) &qspi_bus->dummy, RT_NULL, last); + nu_spi_transfer((struct nu_spi *)qspi_bus, + (uint8_t *) &qspi_bus->dummy, + RT_NULL, + qspi_message->dummy_cycles / (8 / last), + 1); + } + + /* Data stage */ + nu_qspi_mode_config(qspi_bus, (uint8_t *) message->send_buf, (uint8_t *) message->recv_buf, qspi_message->qspi_data_lines); +#endif //#if defined(RT_SFUD_USING_QSPI) + + if (message->length != 0) + { + nu_spi_transfer((struct nu_spi *)qspi_bus, + (uint8_t *) message->send_buf, + (uint8_t *) message->recv_buf, + message->length, + bytes_per_word); + len = message->length; + } + else + { + len = 1; + } + + if (message->cs_release && !(qspi_configuration->parent.mode & RT_SPI_NO_CS)) + { + if (qspi_configuration->parent.mode & RT_SPI_CS_HIGH) + { + QSPI_SET_SS_LOW(qspi_base); + } + else + { + QSPI_SET_SS_HIGH(qspi_base); + } + } + + return len; +} + +static int nu_qspi_register_bus(struct nu_spi *qspi_device, const char *name) +{ + return rt_qspi_bus_register(&qspi_device->dev, name, &nu_qspi_poll_ops); +} + +/** + * Hardware SPI Initial + */ +static int rt_hw_qspi_init(void) +{ + int i; + + for (i = (QSPI_START + 1); i < QSPI_CNT; i++) + { + nu_qspi_register_bus(&nu_qspi_arr[i], nu_qspi_arr[i].name); +#if defined(BSP_USING_QSPI_PDMA) + nu_qspi_arr[i].pdma_chanid_tx = -1; + nu_qspi_arr[i].pdma_chanid_rx = -1; + if ((nu_qspi_arr[i].pdma_perp_tx != NU_PDMA_UNUSED) && (nu_qspi_arr[i].pdma_perp_rx != NU_PDMA_UNUSED)) + { + if (nu_hw_spi_pdma_allocate(&nu_qspi_arr[i]) != RT_EOK) + { + rt_kprintf("Failed to allocate DMA channels for %s. We will use poll-mode for this bus.\n", nu_qspi_arr[i].name); + } + } +#endif + } + + return 0; +} +INIT_DEVICE_EXPORT(rt_hw_qspi_init); + +rt_err_t nu_qspi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint8_t data_line_width, void (*enter_qspi_mode)(), void (*exit_qspi_mode)()) +{ + struct rt_qspi_device *qspi_device = RT_NULL; + rt_err_t result = RT_EOK; + + RT_ASSERT(bus_name != RT_NULL); + RT_ASSERT(device_name != RT_NULL); + RT_ASSERT(data_line_width == 1 || data_line_width == 2 || data_line_width == 4); + + qspi_device = (struct rt_qspi_device *)rt_malloc(sizeof(struct rt_qspi_device)); + if (qspi_device == RT_NULL) + { + rt_kprintf("no memory, qspi bus attach device failed!\n"); + result = -RT_ENOMEM; + goto __exit; + } + + qspi_device->enter_qspi_mode = enter_qspi_mode; + qspi_device->exit_qspi_mode = exit_qspi_mode; + qspi_device->config.qspi_dl_width = data_line_width; + + result = rt_spi_bus_attach_device(&qspi_device->parent, device_name, bus_name, RT_NULL); + +__exit: + if (result != RT_EOK) + { + if (qspi_device) + { + rt_free(qspi_device); + } + } + + return result; +} + +#endif //#if defined(BSP_USING_QSPI) diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_qspi.h b/bsp/nuvoton/libraries/m480/rtt_port/drv_qspi.h new file mode 100644 index 0000000000000000000000000000000000000000..87be3e6e42102d6da5f8d24256a9e404a21b8baf --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_qspi.h @@ -0,0 +1,20 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-2-7 Wayne First version +* +******************************************************************************/ + +#ifndef __DRV_QSPI_H__ +#define __DRV_QSPI_H__ + +#include + +rt_err_t nu_qspi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint8_t data_line_width, void (*enter_qspi_mode)(), void (*exit_qspi_mode)()); + +#endif // __DRV_QSPI_H___ diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_rtc.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_rtc.c new file mode 100644 index 0000000000000000000000000000000000000000..361ee87755fcc0a25e88f3cb1e007337489ea78f --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_rtc.c @@ -0,0 +1,353 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-02-10 klcheng First version +* +******************************************************************************/ +#include + +#if defined (BSP_USING_RTC) + +#include +#include + +/* Private define ---------------------------------------------------------------*/ + +/* convert the real year and month value to the format of struct tm. */ +#define CONV_TO_TM_YEAR(year) ((year) - 1900) +#define CONV_TO_TM_MON(mon) ((mon) - 1) + +/* convert the tm_year and tm_mon from struct tm to the real value. */ +#define CONV_FROM_TM_YEAR(tm_year) ((tm_year) + 1900) +#define CONV_FROM_TM_MON(tm_mon) ((tm_mon) + 1) + +/* rtc date upper bound reaches the year of 2099. */ +#define RTC_TM_UPPER_BOUND \ +{ .tm_year = CONV_TO_TM_YEAR(2099), \ + .tm_mon = CONV_TO_TM_MON(12), \ + .tm_mday = 31, \ + .tm_hour = 23, \ + .tm_min = 59, \ + .tm_sec = 59, \ +} + +/* rtc date lower bound reaches the year of 2000. */ +#define RTC_TM_LOWER_BOUND \ +{ .tm_year = CONV_TO_TM_YEAR(2000), \ + .tm_mon = CONV_TO_TM_MON(1), \ + .tm_mday = 1, \ + .tm_hour = 0, \ + .tm_min = 0, \ + .tm_sec = 0, \ +} + +/* Private typedef --------------------------------------------------------------*/ + +/* Private functions ------------------------------------------------------------*/ +static rt_err_t nu_rtc_control(rt_device_t dev, int cmd, void *args); + +#if defined (NU_RTC_SUPPORT_IO_RW) +static rt_size_t nu_rtc_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size); +static rt_size_t nu_rtc_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size); +#endif + +static rt_err_t nu_rtc_is_date_valid(const time_t *const t); +static void nu_rtc_init(void); + +#if defined(RT_USING_ALARM) +static void nu_rtc_alarm_reset(void); +#endif + +/* Public functions -------------------------------------------------------------*/ +#if defined (NU_RTC_SUPPORT_MSH_CMD) +extern rt_err_t set_date(rt_uint32_t year, rt_uint32_t month, rt_uint32_t day); +extern rt_err_t set_time(rt_uint32_t hour, rt_uint32_t minute, rt_uint32_t second); +#endif + +/* Private variables ------------------------------------------------------------*/ +static struct rt_device device_rtc; + + +static void nu_rtc_init(void) +{ + /* hw rtc initialise */ + RTC_Open(NULL); + RTC_DisableInt(RTC_INTEN_ALMIEN_Msk | RTC_INTEN_TICKIEN_Msk | RTC_INTEN_TAMP0IEN_Msk | + RTC_INTEN_TAMP1IEN_Msk | RTC_INTEN_TAMP2IEN_Msk | RTC_INTEN_TAMP3IEN_Msk | + RTC_INTEN_TAMP4IEN_Msk | RTC_INTEN_TAMP5IEN_Msk); + +#if defined(RT_USING_ALARM) + + nu_rtc_alarm_reset(); + RTC_EnableInt(RTC_INTEN_ALMIEN_Msk); + NVIC_EnableIRQ(RTC_IRQn); +#endif +} + + +#if defined(RT_USING_ALARM) +/* Reset alarm settings to avoid the unwanted values remain in rtc registers. */ +static void nu_rtc_alarm_reset(void) +{ + S_RTC_TIME_DATA_T alarm; + + /* Reset alarm time and calendar. */ + alarm.u32Year = RTC_YEAR2000; + alarm.u32Month = 0; + alarm.u32Day = 0; + alarm.u32Hour = 0; + alarm.u32Minute = 0; + alarm.u32Second = 0; + alarm.u32TimeScale = RTC_CLOCK_24; + + RTC_SetAlarmDateAndTime(&alarm); + + /* Reset alarm time mask and calendar mask. */ + RTC_SetAlarmDateMask(0, 0, 0, 0, 0, 0); + RTC_SetAlarmTimeMask(0, 0, 0, 0, 0, 0); + + /* Clear alarm flag for safe */ + RTC_CLEAR_ALARM_INT_FLAG(); +} +#endif + + +/* rtc device driver initialise. */ +int rt_hw_rtc_init(void) +{ + rt_err_t ret; + + nu_rtc_init(); + + /* register rtc device IO operations */ + device_rtc.type = RT_Device_Class_RTC; + device_rtc.init = NULL; + device_rtc.open = NULL; + device_rtc.close = NULL; + device_rtc.control = nu_rtc_control; + +#if defined (NU_RTC_SUPPORT_IO_RW) + device_rtc.read = nu_rtc_read; + device_rtc.write = nu_rtc_write; +#else + device_rtc.read = NULL; + device_rtc.write = NULL; +#endif + + device_rtc.user_data = RT_NULL; + device_rtc.rx_indicate = RT_NULL; + device_rtc.tx_complete = RT_NULL; + + ret = rt_device_register(&device_rtc, "rtc", RT_DEVICE_FLAG_RDWR); + + return (int)ret; +} +INIT_BOARD_EXPORT(rt_hw_rtc_init); + + +#if defined (NU_RTC_SUPPORT_IO_RW) +/* Register rt-thread device.read() entry. */ +static rt_size_t nu_rtc_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + (void) pos; + nu_rtc_control(dev, RT_DEVICE_CTRL_RTC_GET_TIME, buffer); + + return size; +} +#endif + + +#if defined (NU_RTC_SUPPORT_IO_RW) +/* Register rt-thread device.write() entry. */ +static rt_size_t nu_rtc_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + (void) pos; + nu_rtc_control(dev, RT_DEVICE_CTRL_RTC_SET_TIME, (void *)buffer); + + return size; +} +#endif + + +static rt_err_t nu_rtc_is_date_valid(const time_t *const t) +{ + static struct tm tm_upper = RTC_TM_UPPER_BOUND; + static struct tm tm_lower = RTC_TM_LOWER_BOUND; + static time_t t_upper, t_lower; + static rt_bool_t initialised = RT_FALSE; + + if (!initialised) + { + t_upper = mktime((struct tm *)&tm_upper); + t_lower = mktime((struct tm *)&tm_lower); + initialised = RT_TRUE; + } + + /* check the date is supported by rtc. */ + if ((*t > t_upper) || (*t < t_lower)) + return -(RT_EINVAL); + + return RT_EOK; +} + + +/* Register rt-thread device.control() entry. */ +static rt_err_t nu_rtc_control(rt_device_t dev, int cmd, void *args) +{ + struct tm tm_out, *tm_in; + time_t *time; + S_RTC_TIME_DATA_T hw_time; + +#if defined(RT_USING_ALARM) + + struct rt_rtc_wkalarm *wkalarm; + S_RTC_TIME_DATA_T hw_alarm; +#endif + + if ((dev == NULL) || (args == NULL)) + return -(RT_EINVAL); + + switch (cmd) + { + case RT_DEVICE_CTRL_RTC_GET_TIME: + + time = (time_t *)args; + RTC_GetDateAndTime(&hw_time); + + tm_out.tm_year = CONV_TO_TM_YEAR(hw_time.u32Year); + tm_out.tm_mon = CONV_TO_TM_MON(hw_time.u32Month); + tm_out.tm_mday = hw_time.u32Day; + tm_out.tm_hour = hw_time.u32Hour; + tm_out.tm_min = hw_time.u32Minute; + tm_out.tm_sec = hw_time.u32Second; + *time = mktime(&tm_out); + break; + + case RT_DEVICE_CTRL_RTC_SET_TIME: + + time = (time_t *) args; + tm_in = localtime(time); + + if (nu_rtc_is_date_valid(time) != RT_EOK) + return RT_ERROR; + + hw_time.u32Year = CONV_FROM_TM_YEAR(tm_in->tm_year); + hw_time.u32Month = CONV_FROM_TM_MON(tm_in->tm_mon); + hw_time.u32Day = tm_in->tm_mday; + hw_time.u32Hour = tm_in->tm_hour; + hw_time.u32Minute = tm_in->tm_min; + hw_time.u32Second = tm_in->tm_sec; + hw_time.u32TimeScale = RTC_CLOCK_24; + hw_time.u32AmPm = 0; + + RTC_SetDateAndTime(&hw_time); + break; + +#if defined(RT_USING_ALARM) + case RT_DEVICE_CTRL_RTC_GET_ALARM: + + wkalarm = (struct rt_rtc_wkalarm *) args; + RTC_GetAlarmDateAndTime(&hw_alarm); + + wkalarm->tm_hour = hw_alarm.u32Hour; + wkalarm->tm_min = hw_alarm.u32Minute; + wkalarm->tm_sec = hw_alarm.u32Second; + break; + + case RT_DEVICE_CTRL_RTC_SET_ALARM: + + wkalarm = (struct rt_rtc_wkalarm *) args; + hw_alarm.u32Hour = wkalarm->tm_hour; + hw_alarm.u32Minute = wkalarm->tm_min; + hw_alarm.u32Second = wkalarm->tm_sec; + + RTC_SetAlarmDateMask(1, 1, 1, 1, 1, 1); + RTC_SetAlarmDateAndTime(&hw_alarm); + break; + + default: + return -(RT_EINVAL); +#endif + } + + return RT_EOK; +} + + +#if defined (NU_RTC_SUPPORT_MSH_CMD) + +/* Support "rtc_det_date" command line in msh mode */ +static rt_err_t msh_rtc_set_date(int argc, char **argv) +{ + rt_uint32_t index, len, arg[3]; + + rt_memset(arg, 0, sizeof(arg)); + len = (argc >= 4) ? 4 : argc; + + /* The date information stored in argv is represented by the following order : + argv[0,1,2,3] = [cmd, year, month, day] */ + for (index = 0; index < (len - 1); index ++) + { + arg[index] = atol(argv[index + 1]); + } + + return set_date(arg[0], arg[1], arg[2]); +} +MSH_CMD_EXPORT_ALIAS(msh_rtc_set_date, rtc_set_date, e.g: rtc_set_date 2020 1 20); +#endif + + +#if defined (NU_RTC_SUPPORT_MSH_CMD) + +/* Support "rtc_det_time" command line in msh mode */ +static rt_err_t msh_rtc_set_time(int argc, char **argv) +{ + rt_uint32_t index, len, arg[3]; + + rt_memset(arg, 0, sizeof(arg)); + len = (argc >= 4) ? 4 : argc; + + /* The time information stored in argv is represented by the following order : + argv[0,1,2,3] = [cmd, hour, minute, second] */ + for (index = 0; index < (len - 1); index ++) + { + arg[index] = atol(argv[index + 1]); + } + + return set_time(arg[0], arg[1], arg[2]); +} +MSH_CMD_EXPORT_ALIAS(msh_rtc_set_time, rtc_set_time, e.g: rtc_set_time 18 30 00); +#endif + + +/* rtc interrupt entry */ +void RTC_IRQHandler(void) +{ + rt_interrupt_enter(); + + if (RTC_GET_TICK_INT_FLAG()) + { + RTC_CLEAR_TICK_INT_FLAG(); + } + +#if defined(RT_USING_ALARM) + + if (RTC_GET_ALARM_INT_FLAG()) + { + RTC_CLEAR_ALARM_INT_FLAG(); + + /* Send an alarm event to notify rt-thread alarm service. */ + rt_alarm_update(&device_rtc, NULL); + } +#endif + + rt_interrupt_leave(); +} + +#endif /* BSP_USING_RTC */ + diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_scuart.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_scuart.c new file mode 100644 index 0000000000000000000000000000000000000000..d15750e7768c59e1805b16f1bbdc0891aa0eeda4 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_scuart.c @@ -0,0 +1,381 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-5-31 Egbert First version +* +******************************************************************************/ + +#include + +#if defined(BSP_USING_SCUART) + +#include +#include +#include + +/* Private define ---------------------------------------------------------------*/ +#define LOG_TAG "drv.scuart" +#define DBG_ENABLE +#define DBG_SECTION_NAME "drv.scuart" +#define DBG_LEVEL DBG_ERROR +#define DBG_COLOR +#include + +enum +{ + SCUART_START = -1, +#if defined(BSP_USING_SCUART0) + SCUART0_IDX, +#endif +#if defined(BSP_USING_SCUART1) + SCUART1_IDX, +#endif +#if defined(BSP_USING_SCUART2) + SCUART2_IDX, +#endif + SCUART_CNT +}; + +/* Private typedef --------------------------------------------------------------*/ +struct nu_scuart +{ + rt_serial_t dev; + char *name; + SC_T *scuart_base; + uint32_t scuart_rst; + IRQn_Type scuart_irq_n; + +}; +typedef struct nu_scuart *nu_scuart_t; + +/* Private functions ------------------------------------------------------------*/ +static rt_err_t nu_scuart_configure(struct rt_serial_device *serial, struct serial_configure *cfg); +static rt_err_t nu_scuart_control(struct rt_serial_device *serial, int cmd, void *arg); +static int nu_scuart_send(struct rt_serial_device *serial, char c); +static int nu_scuart_receive(struct rt_serial_device *serial); +static void nu_scuart_isr(nu_scuart_t serial); + +/* Public functions ------------------------------------------------------------*/ + +/* Private variables ------------------------------------------------------------*/ + +static const struct rt_uart_ops nu_scuart_ops = +{ + .configure = nu_scuart_configure, + .control = nu_scuart_control, + .putc = nu_scuart_send, + .getc = nu_scuart_receive, + .dma_transmit = RT_NULL /* not support DMA mode */ +}; + +static const struct serial_configure nu_scuart_default_config = + RT_SERIAL_CONFIG_DEFAULT; + +static struct nu_scuart nu_scuart_arr [] = +{ +#if defined(BSP_USING_SCUART0) + { + .name = "scuart0", + .scuart_base = SC0, + .scuart_rst = SC0_RST, + .scuart_irq_n = SC0_IRQn, + }, +#endif + +#if defined(BSP_USING_SCUART1) + { + .name = "scuart1", + .scuart_base = SC1, + .scuart_rst = SC1_RST, + .scuart_irq_n = SC1_IRQn, + }, +#endif + +#if defined(BSP_USING_SCUART2) + { + .name = "scuart2", + .scuart_base = SC2, + .scuart_rst = SC2_RST, + .scuart_irq_n = SC2_IRQn, + }, +#endif + + {0} +}; /* scuart nu_scuart */ + +/* Interrupt Handle Funtion ----------------------------------------------------*/ +#if defined(BSP_USING_SCUART0) +/* SCUART0 interrupt entry */ +void SC0_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + nu_scuart_isr(&nu_scuart_arr[SCUART0_IDX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(BSP_USING_SCUART1) +/* SCUART1 interrupt entry */ +void SC1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + nu_scuart_isr(&nu_scuart_arr[SCUART1_IDX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(BSP_USING_SCUART2) +/* SCUART2 interrupt entry */ +void SC2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + nu_scuart_isr(&nu_scuart_arr[SCUART2_IDX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + + + +/** + * All SCUART interrupt service routine + */ +static void nu_scuart_isr(nu_scuart_t serial) +{ + /* Get base address of scuart register */ + SC_T *scuart_base = ((nu_scuart_t)serial)->scuart_base; + + /* Get interrupt event */ + uint32_t u32IntSts = scuart_base->INTSTS; + + /* Handle RX event */ + if (u32IntSts & (SC_INTSTS_RDAIF_Msk | SC_INTSTS_RXTOIF_Msk)) + { + rt_hw_serial_isr(&serial->dev, RT_SERIAL_EVENT_RX_IND); + + // RDA is the only interrupt enabled in this driver, this status bit + // automatically cleared after Rx FIFO empty. So no need to clear interrupt + // status here. + scuart_base->INTSTS = SC_INTSTS_RXTOIF_Msk; + } +} + +/** + * Configurae scuart port + */ +static rt_err_t nu_scuart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + rt_err_t ret = RT_EOK; + uint32_t scuart_word_len = 0; + uint32_t scuart_stop_bit = 0; + uint32_t scuart_parity = 0; + + /* Get base address of scuart register */ + SC_T *scuart_base = ((nu_scuart_t)serial)->scuart_base; + + /* Check baudrate */ + RT_ASSERT(cfg->baud_rate != 0); + + /* Check word len */ + switch (cfg->data_bits) + { + case DATA_BITS_5: + scuart_word_len = SCUART_CHAR_LEN_5; + break; + + case DATA_BITS_6: + scuart_word_len = SCUART_CHAR_LEN_6; + break; + + case DATA_BITS_7: + scuart_word_len = SCUART_CHAR_LEN_7; + break; + + case DATA_BITS_8: + scuart_word_len = SCUART_CHAR_LEN_8; + break; + + default: + LOG_E("Unsupported data length"); + ret = RT_EINVAL; + goto exit_nu_scuart_configure; + } + + /* Check stop bit */ + switch (cfg->stop_bits) + { + case STOP_BITS_1: + scuart_stop_bit = SCUART_STOP_BIT_1; + break; + + case STOP_BITS_2: + scuart_stop_bit = SCUART_STOP_BIT_2; + break; + + default: + LOG_E("Unsupported stop bit"); + ret = RT_EINVAL; + goto exit_nu_scuart_configure; + } + + /* Check parity */ + switch (cfg->parity) + { + case PARITY_NONE: + scuart_parity = SCUART_PARITY_NONE; + break; + + case PARITY_ODD: + scuart_parity = SCUART_PARITY_ODD; + break; + + case PARITY_EVEN: + scuart_parity = SCUART_PARITY_EVEN; + break; + + default: + LOG_E("Unsupported parity"); + ret = RT_EINVAL; + goto exit_nu_scuart_configure; + } + + /* Reset this module */ + SYS_ResetModule(((nu_scuart_t)serial)->scuart_rst); + + /* Open SCUART and set SCUART Baudrate */ + SCUART_Open(scuart_base, cfg->baud_rate); + + /* Set line configuration. */ + SCUART_SetLineConfig(scuart_base, 0, scuart_word_len, scuart_parity, scuart_stop_bit); + + /* Enable NVIC interrupt. */ + NVIC_EnableIRQ(((nu_scuart_t)serial)->scuart_irq_n); + +exit_nu_scuart_configure: + + if (ret != RT_EOK) + SCUART_Close(scuart_base); + + return -(ret); +} + +/** + * SCUART interrupt control + */ +static rt_err_t nu_scuart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + rt_err_t result = RT_EOK; + rt_uint32_t flag; + rt_ubase_t ctrl_arg = (rt_ubase_t)arg; + + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(arg != RT_NULL); + + /* Get base address of scuart register */ + SC_T *scuart_base = ((nu_scuart_t)serial)->scuart_base; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) /* Disable INT-RX */ + { + flag = SC_INTEN_RDAIEN_Msk | SC_INTEN_RXTOIEN_Msk; + SCUART_DISABLE_INT(scuart_base, flag); + } + else if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) /* Disable DMA-RX */ + { + LOG_E("SCUART does not support dma transmission"); + } + break; + + case RT_DEVICE_CTRL_SET_INT: + if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) /* Enable INT-RX */ + { + flag = SC_INTEN_RDAIEN_Msk | SC_INTEN_RXTOIEN_Msk; + SCUART_ENABLE_INT(scuart_base, flag); + } + break; + + } + return result; +} + +/** + * SCUART put char + */ +static int nu_scuart_send(struct rt_serial_device *serial, char c) +{ + RT_ASSERT(serial != RT_NULL); + + /* Get base address of scuart register */ + SC_T *scuart_base = ((nu_scuart_t)serial)->scuart_base; + + /* Waiting if TX-FIFO is full. */ + while (SCUART_IS_TX_FULL(scuart_base)); + + /* Put char into TX-FIFO */ + SCUART_WRITE(scuart_base, c); + + return 1; +} + +/** + * SCUART get char + */ +static int nu_scuart_receive(struct rt_serial_device *serial) +{ + RT_ASSERT(serial != RT_NULL); + + /* Get base address of scuart register */ + SC_T *scuart_base = ((nu_scuart_t)serial)->scuart_base; + + /* Return failure if RX-FIFO is empty. */ + if (SCUART_GET_RX_EMPTY(scuart_base)) + { + return -1; + } + + /* Get char from RX-FIFO */ + return SCUART_READ(scuart_base); +} + +/** + * Hardware SCUART Initialization + */ +static int rt_hw_scuart_init(void) +{ + int i; + rt_uint32_t flag; + rt_err_t ret = RT_EOK; + + for (i = (SCUART_START + 1); i < SCUART_CNT; i++) + { + flag = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX; + + nu_scuart_arr[i].dev.ops = &nu_scuart_ops; + nu_scuart_arr[i].dev.config = nu_scuart_default_config; + + ret = rt_hw_serial_register(&nu_scuart_arr[i].dev, nu_scuart_arr[i].name, flag, NULL); + RT_ASSERT(ret == RT_EOK); + } + + return ret; +} +INIT_DEVICE_EXPORT(rt_hw_scuart_init); +#endif //#if defined(BSP_USING_SCUART) diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_sdh.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_sdh.c new file mode 100644 index 0000000000000000000000000000000000000000..6c6dd768b82ac835b84b087fde34e921d4e5d20c --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_sdh.c @@ -0,0 +1,629 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-2-7 Wayne First version +* +******************************************************************************/ + +#include + +#if defined(BSP_USING_SDH) + +#include +#include +#include +#include + +#if defined(RT_USING_DFS) + #include + #include +#endif + +/* Private define ---------------------------------------------------------------*/ +// RT_DEV_NAME_PREFIX sdh + +#ifndef NU_SDH_MOUNTPOINT_ROOT + #define NU_SDH_MOUNTPOINT_ROOT "/mnt" +#endif + +#ifndef NU_SDH_MOUNTPOINT_SDH0 + #define NU_SDH_MOUNTPOINT_SDH0 NU_SDH_MOUNTPOINT_ROOT"/sd0" +#endif + +#ifndef NU_SDH_MOUNTPOINT_SDH1 + #define NU_SDH_MOUNTPOINT_SDH1 NU_SDH_MOUNTPOINT_ROOT"/sd1" +#endif + +#if defined(NU_SDH_USING_PDMA) + #define NU_SDH_MEMCPY nu_pdma_memcpy +#else + #define NU_SDH_MEMCPY memcpy +#endif + +enum +{ + SDH_START = -1, +#if defined(BSP_USING_SDH0) + SDH0_IDX, +#endif +#if defined(BSP_USING_SDH1) + SDH1_IDX, +#endif + SDH_CNT +}; + +#define SDH_BLOCK_SIZE 512ul + +#if defined(NU_SDH_HOTPLUG) + #define NU_SDH_TID_STACK_SIZE 1024 +#endif + +#if defined(NU_SDH_HOTPLUG) +enum +{ + NU_SDH_CARD_INSERTED_SD0 = (1 << 0), + NU_SDH_CARD_REMOVED_SD0 = (1 << 1), + NU_SDH_CARD_INSERTED_SD1 = (1 << 2), + NU_SDH_CARD_REMOVED_SD1 = (1 << 3), + NU_SDH_CARD_EVENT_ALL = (NU_SDH_CARD_INSERTED_SD0 | NU_SDH_CARD_REMOVED_SD0 | NU_SDH_CARD_INSERTED_SD1 | NU_SDH_CARD_REMOVED_SD1) +}; +#endif + +/* Private typedef --------------------------------------------------------------*/ +struct nu_sdh +{ + struct rt_device dev; + char *name; +#if defined(NU_SDH_HOTPLUG) + char *mounted_point; +#endif + SDH_T *base; + uint32_t is_card_inserted; + SDH_INFO_T *info; + struct rt_semaphore lock; + uint8_t *pbuf; +}; +typedef struct nu_sdh *nu_sdh_t; + +#if defined(NU_SDH_HOTPLUG) + static struct rt_thread sdh_tid; + static rt_uint8_t sdh_stack[NU_SDH_TID_STACK_SIZE]; +#endif + +/* Private functions ------------------------------------------------------------*/ +static void nu_sdh_isr(nu_sdh_t sdh); +static rt_err_t nu_sdh_init(rt_device_t dev); +static rt_err_t nu_sdh_open(rt_device_t dev, rt_uint16_t oflag); +static rt_err_t nu_sdh_close(rt_device_t dev); +static rt_size_t nu_sdh_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t blk_nb); +static rt_err_t nu_sdh_control(rt_device_t dev, int cmd, void *args); +static int rt_hw_sdh_init(void); + +#if defined(NU_SDH_HOTPLUG) + static rt_bool_t nu_sdh_hotplug_is_mounted(const char *mounting_path); + static void sdh_hotplugger(void *param); + static rt_err_t nu_sdh_hotplug_mount(nu_sdh_t sdh); + static rt_err_t nu_sdh_hotplug_unmount(nu_sdh_t sdh); +#endif + +/* Public functions -------------------------------------------------------------*/ + + +/* Private variables ------------------------------------------------------------*/ +static struct nu_sdh nu_sdh_arr [] = +{ +#if defined(BSP_USING_SDH0) + { + .name = "sdh0", +#if defined(NU_SDH_HOTPLUG) + .mounted_point = NU_SDH_MOUNTPOINT_SDH0, +#endif + .base = SDH0, + .info = &SD0, + }, +#endif +#if defined(BSP_USING_SDH1) + { + .name = "sdh1", +#if defined(NU_SDH_HOTPLUG) + .mounted_point = NU_SDH_MOUNTPOINT_SDH1, +#endif + .base = SDH1, + .info = &SD1, + }, +#endif + {0} +}; /* struct nu_sdh nu_sdh_arr [] */ +static struct rt_event sdh_event; + +static void nu_sdh_isr(nu_sdh_t sdh) +{ + SDH_T *sdh_base = sdh->base; + unsigned int volatile isr; + unsigned int volatile ier; + SDH_INFO_T *pSD = sdh->info; + + // FMI data abort interrupt + if (sdh_base->GINTSTS & SDH_GINTSTS_DTAIF_Msk) + { + /* ResetAllEngine() */ + sdh_base->GCTL |= SDH_GCTL_GCTLRST_Msk; + } + + //----- SD interrupt status + isr = sdh_base->INTSTS; + if (isr & SDH_INTSTS_BLKDIF_Msk) + { + // block down + pSD->DataReadyFlag = TRUE; + SDH_CLR_INT_FLAG(sdh_base, SDH_INTSTS_BLKDIF_Msk); + } + + if (isr & SDH_INTSTS_CDIF_Msk) // card detect + { + /* SD interrupt status */ + // it is work to delay 50 times for SD_CLK = 200KHz + { + int volatile i; // delay 30 fail, 50 OK + for (i = 0; i < 0x500; i++); // delay to make sure got updated value from REG_SDISR. + isr = sdh_base->INTSTS; + } + + if (isr & SDH_INTSTS_CDSTS_Msk) + { + /* Card removed */ +#if defined(NU_SDH_HOTPLUG) + if (sdh->base == SDH0) + rt_event_send(&sdh_event, NU_SDH_CARD_REMOVED_SD0); + else if (sdh->base == SDH1) + rt_event_send(&sdh_event, NU_SDH_CARD_REMOVED_SD1); +#endif + sdh->info->IsCardInsert = FALSE; // SDISR_CD_Card = 1 means card remove for GPIO mode + rt_memset((void *)sdh->info, 0, sizeof(SDH_INFO_T)); + } + else + { + SDH_Open(sdh_base, CardDetect_From_GPIO); + if (!SDH_Probe(sdh_base)) + { + /* Card inserted */ +#if defined(NU_SDH_HOTPLUG) + if (sdh->base == SDH0) + rt_event_send(&sdh_event, NU_SDH_CARD_INSERTED_SD0); + else if (sdh->base == SDH1) + rt_event_send(&sdh_event, NU_SDH_CARD_INSERTED_SD1); +#endif + } + } + /* Clear CDIF interrupt flag */ + SDH_CLR_INT_FLAG(sdh_base, SDH_INTSTS_CDIF_Msk); + } + + // CRC error interrupt + if (isr & SDH_INTSTS_CRCIF_Msk) + { + if (!(isr & SDH_INTSTS_CRC16_Msk)) + { + /* CRC_16 error */ + // handle CRC 16 error + } + else if (!(isr & SDH_INTSTS_CRC7_Msk)) + { + if (!pSD->R3Flag) + { + /* CRC_7 error */ + // handle CRC 7 error + } + } + /* Clear CRCIF interrupt flag */ + SDH_CLR_INT_FLAG(sdh_base, SDH_INTSTS_CRCIF_Msk); + } + + /* Data-in timeout */ + if (isr & SDH_INTSTS_DITOIF_Msk) + { + sdh_base->INTSTS |= SDH_INTSTS_DITOIF_Msk; + } + + /* Response-in timeout interrupt */ + if (isr & SDH_INTSTS_RTOIF_Msk) + { + sdh_base->INTSTS |= SDH_INTSTS_RTOIF_Msk; + } +} + +#if defined(BSP_USING_SDH0) +void SDH0_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + nu_sdh_isr(&nu_sdh_arr[SDH0_IDX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(BSP_USING_SDH1) +void SDH1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + nu_sdh_isr(&nu_sdh_arr[SDH1_IDX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +/* RT-Thread Device Driver Interface */ +static rt_err_t nu_sdh_init(rt_device_t dev) +{ + return RT_EOK; +} + +static rt_err_t nu_sdh_open(rt_device_t dev, rt_uint16_t oflag) +{ + nu_sdh_t sdh = (nu_sdh_t)dev; + + RT_ASSERT(dev != RT_NULL); + + return (SDH_Probe(sdh->base) == 0) ? RT_EOK : -(RT_ERROR); +} + +static rt_err_t nu_sdh_close(rt_device_t dev) +{ + return RT_EOK; +} + +static rt_size_t nu_sdh_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t blk_nb) +{ + rt_uint32_t ret = 0; + nu_sdh_t sdh = (nu_sdh_t)dev; + + RT_ASSERT(dev != RT_NULL); + RT_ASSERT(buffer != RT_NULL); + + rt_sem_take(&sdh->lock, RT_WAITING_FOREVER); + + /* Check alignment. */ + if (((uint32_t)buffer & 0x03) != 0) + { + /* Non-aligned. */ + uint32_t i; + uint8_t *copy_buffer = (uint8_t *)buffer; + + sdh->pbuf = rt_malloc(SDH_BLOCK_SIZE); + if (sdh->pbuf == RT_NULL) + goto exit_nu_sdh_read; + + for (i = 0; i < blk_nb; i++) + { + /* Read to temp buffer from specified sector. */ + ret = SDH_Read(sdh->base, &sdh->pbuf[0], pos, 1); + if (ret != Successful) + goto exit_nu_sdh_read; + + /* Move to user's buffer */ + NU_SDH_MEMCPY((void *)copy_buffer, (void *)&sdh->pbuf[0], SDH_BLOCK_SIZE); + + pos ++; + copy_buffer += SDH_BLOCK_SIZE; + } + } + else + { + /* Read to user's buffer from specified sector. */ + ret = SDH_Read(sdh->base, (uint8_t *)buffer, pos, blk_nb); + } + +exit_nu_sdh_read: + + if (sdh->pbuf) + { + rt_free(sdh->pbuf); + sdh->pbuf = RT_NULL; + } + + rt_sem_release(&sdh->lock); + + if (ret == Successful) + return blk_nb; + + rt_kprintf("Read failed: %d, buffer 0x%08x\n", ret, buffer); + rt_set_errno(-RT_ENOSYS); + return 0; +} + +static rt_size_t nu_sdh_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t blk_nb) +{ + rt_uint32_t ret = 0; + nu_sdh_t sdh = (nu_sdh_t)dev; + + RT_ASSERT(dev != RT_NULL); + RT_ASSERT(buffer != RT_NULL); + + rt_sem_take(&sdh->lock, RT_WAITING_FOREVER); + + /* Check alignment. */ + if (((uint32_t)buffer & 0x03) != 0) + { + /* Non-aligned. */ + uint32_t i; + uint8_t *copy_buffer = (uint8_t *)buffer; + + sdh->pbuf = rt_malloc(SDH_BLOCK_SIZE); + if (sdh->pbuf == RT_NULL) + goto exit_nu_sdh_write; + + for (i = 0; i < blk_nb; i++) + { + NU_SDH_MEMCPY((void *)&sdh->pbuf[0], copy_buffer, SDH_BLOCK_SIZE); + + ret = SDH_Write(sdh->base, (uint8_t *)&sdh->pbuf[0], pos, 1); + if (ret != Successful) + goto exit_nu_sdh_write; + + pos++; + copy_buffer += SDH_BLOCK_SIZE; + } + } + else + { + /* Write to device directly. */ + ret = SDH_Write(sdh->base, (uint8_t *)buffer, pos, blk_nb); + } + +exit_nu_sdh_write: + + if (sdh->pbuf) + { + rt_free(sdh->pbuf); + sdh->pbuf = RT_NULL; + } + + rt_sem_release(&sdh->lock); + + if (ret == Successful) return blk_nb; + + rt_kprintf("write failed: %d, buffer 0x%08x\n", ret, buffer); + rt_set_errno(-RT_ENOSYS); + return 0; +} + +static rt_err_t nu_sdh_control(rt_device_t dev, int cmd, void *args) +{ + nu_sdh_t sdh = (nu_sdh_t)dev; + + RT_ASSERT(dev != RT_NULL); + + if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME) + { + SDH_INFO_T *sdh_info = sdh->info; + + struct rt_device_blk_geometry *geometry; + + geometry = (struct rt_device_blk_geometry *)args; + if (geometry == RT_NULL) return -RT_ERROR; + + geometry->bytes_per_sector = sdh_info->sectorSize; + geometry->block_size = sdh_info->sectorSize; + geometry->sector_count = sdh_info->totalSectorN; + } + + return RT_EOK; +} + + +static int rt_hw_sdh_init(void) +{ + int i; + rt_err_t ret = RT_EOK; + rt_uint32_t flags = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE; + + rt_event_init(&sdh_event, "sdh_event", RT_IPC_FLAG_FIFO); + + for (i = (SDH_START + 1); i < SDH_CNT; i++) + { + /* Register sdcard device */ + nu_sdh_arr[i].dev.type = RT_Device_Class_Block; + nu_sdh_arr[i].dev.init = nu_sdh_init; + nu_sdh_arr[i].dev.open = nu_sdh_open; + nu_sdh_arr[i].dev.close = nu_sdh_close; + nu_sdh_arr[i].dev.read = nu_sdh_read; + nu_sdh_arr[i].dev.write = nu_sdh_write; + nu_sdh_arr[i].dev.control = nu_sdh_control; + + /* Private */ + nu_sdh_arr[i].dev.user_data = (void *)&nu_sdh_arr[i]; + + rt_sem_init(&nu_sdh_arr[i].lock, "sdhlock", 1, RT_IPC_FLAG_FIFO); + + SDH_Open(nu_sdh_arr[i].base, CardDetect_From_GPIO); + + nu_sdh_arr[i].pbuf = RT_NULL; + ret = rt_device_register(&nu_sdh_arr[i].dev, nu_sdh_arr[i].name, flags); + RT_ASSERT(ret == RT_EOK); + } + + return (int)ret; +} +INIT_BOARD_EXPORT(rt_hw_sdh_init); + +#if defined(NU_SDH_HOTPLUG) +static rt_bool_t nu_sdh_hotplug_is_mounted(const char *mounting_path) +{ + rt_bool_t ret = RT_FALSE; + +#if defined(RT_USING_DFS) + + struct dfs_filesystem *psFS = dfs_filesystem_lookup(mounting_path); + if (psFS == RT_NULL) + { + goto exit_nu_sdh_hotplug_is_mounted; + } + else if (!rt_memcmp(psFS->path, mounting_path, rt_strlen(mounting_path))) + { + ret = RT_TRUE; + } + else + { + ret = RT_FALSE; + } + +#endif + +exit_nu_sdh_hotplug_is_mounted: + + return ret; +} +static rt_err_t nu_sdh_hotplug_mount(nu_sdh_t sdh) +{ + rt_err_t ret = RT_ERROR; + DIR *t; + +#if defined(RT_USING_DFS) + + if (nu_sdh_hotplug_is_mounted(sdh->mounted_point) == RT_TRUE) + { + ret = RT_EOK; + goto exit_nu_sdh_hotplug_mount; + } + + /* Check the SD folder path is valid. */ + if ((t = opendir(sdh->mounted_point)) != RT_NULL) + { + closedir(t); + } + else + { + + /* Check the ROOT path is valid. */ + if ((t = opendir(NU_SDH_MOUNTPOINT_ROOT)) != RT_NULL) + { + closedir(t); + } + else if ((ret = mkdir(NU_SDH_MOUNTPOINT_ROOT, 0)) != RT_EOK) + { + rt_kprintf("Failed to mkdir %s\n", NU_SDH_MOUNTPOINT_ROOT); + goto exit_nu_sdh_hotplug_mount; + } + + if ((ret = mkdir(sdh->mounted_point, 0)) != RT_EOK) + { + rt_kprintf("Failed to mkdir %s\n", sdh->mounted_point); + goto exit_nu_sdh_hotplug_mount; + } + + } //else + + if ((ret = dfs_mount(sdh->name, sdh->mounted_point, "elm", 0, 0)) == 0) + { + rt_kprintf("Mounted %s on %s\n", sdh->name, sdh->mounted_point); + } + else + { + rt_kprintf("Failed to mount %s on %s\n", sdh->name, sdh->mounted_point); + ret = RT_ERROR; + } + +exit_nu_sdh_hotplug_mount: + +#endif + return -(ret); +} + +static rt_err_t nu_sdh_hotplug_unmount(nu_sdh_t sdh) +{ + rt_err_t ret = RT_ERROR; + +#if defined(RT_USING_DFS) + if (nu_sdh_hotplug_is_mounted(sdh->mounted_point) == RT_FALSE) + { + ret = RT_EOK; + goto exit_nu_sdh_hotplug_unmount; + } + + ret = dfs_unmount(sdh->mounted_point); + if (ret != RT_EOK) + { + rt_kprintf("Failed to unmount %s.\n", sdh->mounted_point); + } + else + { + rt_kprintf("Succeed to unmount %s.\n", sdh->mounted_point); + ret = RT_EOK; + } +#endif + +exit_nu_sdh_hotplug_unmount: + + return -(ret); +} +static void sdh_hotplugger(void *param) +{ + rt_uint32_t e; + int i; + + for (i = (SDH_START + 1); i < SDH_CNT; i++) + { + if (SDH_IS_CARD_PRESENT(nu_sdh_arr[i].base)) + { + nu_sdh_hotplug_mount(&nu_sdh_arr[i]); + } + } + + while (1) + { + if (rt_event_recv(&sdh_event, (NU_SDH_CARD_EVENT_ALL), + RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, + RT_WAITING_FOREVER, &e) == RT_EOK) + { + /* Debouce */ + rt_thread_delay(200); + switch (e) + { +#if defined(BSP_USING_SDH0) + case NU_SDH_CARD_INSERTED_SD0: + nu_sdh_hotplug_mount(&nu_sdh_arr[SDH0_IDX]); + break; + case NU_SDH_CARD_REMOVED_SD0: + nu_sdh_hotplug_unmount(&nu_sdh_arr[SDH0_IDX]); + break; +#endif +#if defined(BSP_USING_SDH1) + case NU_SDH_CARD_INSERTED_SD1: + nu_sdh_hotplug_mount(&nu_sdh_arr[SDH1_IDX]); + break; + case NU_SDH_CARD_REMOVED_SD1: + nu_sdh_hotplug_unmount(&nu_sdh_arr[SDH1_IDX]); + break; +#endif + default: + break; + + } //switch(e) + + } //if + + } /* while(1) */ +} + +int mnt_init_sdcard_hotplug(void) +{ + rt_thread_init(&sdh_tid, "hotplug", sdh_hotplugger, NULL, sdh_stack, sizeof(sdh_stack), RT_THREAD_PRIORITY_MAX - 2, 10); + rt_thread_startup(&sdh_tid); + + return 0; +} +INIT_ENV_EXPORT(mnt_init_sdcard_hotplug); +#endif + +#endif //#if defined(BSP_USING_SDH) diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_softi2c.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_softi2c.c new file mode 100644 index 0000000000000000000000000000000000000000..05f9906def180dd59668657d831bb4db656e127d --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_softi2c.c @@ -0,0 +1,254 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-5-28 YCHuang12 First version +* +******************************************************************************/ + +#include + +#if (defined(BSP_USING_SOFT_I2C) && defined(BSP_USING_GPIO) && defined(RT_USING_I2C_BITOPS) && defined(RT_USING_I2C) && defined(RT_USING_PIN)) + +#include +#include +#include +#include + +/* Private define ---------------------------------------------------------------*/ +#define LOG_TAG "drv.softi2c" +#define DBG_ENABLE +#define DBG_SECTION_NAME LOG_TAG +#define DBG_LEVEL DBG_INFO +#define DBG_COLOR +#include + +#ifdef BSP_USING_SOFT_I2C0 +#define NU_SOFT_I2C0_BUS_CONFIG \ + { \ + .scl = BSP_SOFT_I2C0_SCL_PIN, \ + .sda = BSP_SOFT_I2C0_SDA_PIN, \ + .bus_name = "softi2c0", \ + } +#endif + +#ifdef BSP_USING_SOFT_I2C1 +#define NU_SOFT_I2C1_BUS_CONFIG \ + { \ + .scl = BSP_SOFT_I2C1_SCL_PIN, \ + .sda = BSP_SOFT_I2C1_SDA_PIN, \ + .bus_name = "softi2c1", \ + } +#endif + +#if (!defined(BSP_USING_SOFT_I2C0) && !defined(BSP_USING_SOFT_I2C1)) + #error "Please define at least one BSP_USING_SOFT_I2Cx" + /* this driver can be disabled at menuconfig ? RT-Thread Components ? Device Drivers */ +#endif + +/* Private typedef --------------------------------------------------------------*/ +/* soft i2c config class */ +struct nu_soft_i2c_config +{ + rt_uint8_t scl; + rt_uint8_t sda; + const char *bus_name; +}; +/* soft i2c dirver class */ +struct nu_soft_i2c +{ + struct rt_i2c_bit_ops ops; + struct rt_i2c_bus_device soft_i2c_bus; +}; + +/* Private functions ------------------------------------------------------------*/ +static void nu_soft_i2c_udelay(rt_uint32_t us); +static void nu_soft_i2c_set_sda(void *data, rt_int32_t state); +static void nu_soft_i2c_set_scl(void *data, rt_int32_t state); +static rt_int32_t nu_soft_i2c_get_sda(void *data); +static rt_int32_t nu_soft_i2c_get_scl(void *data); + +/* Private variables ------------------------------------------------------------*/ +static const struct nu_soft_i2c_config nu_soft_i2c_cfg[] = +{ +#ifdef BSP_USING_SOFT_I2C0 + NU_SOFT_I2C0_BUS_CONFIG, +#endif +#ifdef BSP_USING_SOFT_I2C1 + NU_SOFT_I2C1_BUS_CONFIG, +#endif +}; + +static struct nu_soft_i2c nu_soft_i2c_obj[sizeof(nu_soft_i2c_cfg) / sizeof(nu_soft_i2c_cfg[0])]; + +static const struct rt_i2c_bit_ops nu_soft_i2c_bit_ops = +{ + .data = RT_NULL, + .set_sda = nu_soft_i2c_set_sda, + .set_scl = nu_soft_i2c_set_scl, + .get_sda = nu_soft_i2c_get_sda, + .get_scl = nu_soft_i2c_get_scl, + .udelay = nu_soft_i2c_udelay, + .delay_us = 1, + .timeout = 100 +}; + +/* Functions define ------------------------------------------------------------*/ + +/** + * The time delay function. + * + * @param microseconds. + */ +static void nu_soft_i2c_udelay(rt_uint32_t us) +{ + rt_uint32_t ticks; + rt_uint32_t told, tnow, tcnt = 0; + rt_uint32_t reload = SysTick->LOAD; + + ticks = us * reload / (1000000 / RT_TICK_PER_SECOND); + told = SysTick->VAL; + while (1) + { + tnow = SysTick->VAL; + if (tnow != told) + { + if (tnow < told) + { + tcnt += told - tnow; + } + else + { + tcnt += reload - tnow + told; + } + told = tnow; + if (tcnt >= ticks) + { + break; + } + } + } +} + +/** + * This function initializes the soft i2c pin. + * + * @param soft i2c config class. + */ +static void nu_soft_i2c_gpio_init(const struct nu_soft_i2c_config *cfg) +{ + rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT_OD); + rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT_OD); + + rt_pin_write(cfg->scl, PIN_HIGH); + rt_pin_write(cfg->sda, PIN_HIGH); +} + +/** + * if i2c is locked, this function will unlock it + * + * @param soft i2c config class + * + * @return RT_EOK indicates successful unlock. + */ +static rt_err_t nu_soft_i2c_bus_unlock(const struct nu_soft_i2c_config *cfg) +{ + rt_int32_t i = 0; + + if (PIN_LOW == rt_pin_read(cfg->sda)) + { + while (i++ < 9) + { + rt_pin_write(cfg->scl, PIN_HIGH); + nu_soft_i2c_udelay(100); + rt_pin_write(cfg->scl, PIN_LOW); + nu_soft_i2c_udelay(100); + } + } + if (PIN_LOW == rt_pin_read(cfg->sda)) + { + return -RT_ERROR; + } + + return RT_EOK; +} + +/** + * This function sets the sda pin. + * + * @param soft i2c config class. + * @param The sda pin state. + */ +static void nu_soft_i2c_set_sda(void *data, rt_int32_t state) +{ + struct nu_soft_i2c_config *cfg = (struct nu_soft_i2c_config *)data; + + rt_pin_write(cfg->sda, state ? PIN_HIGH : PIN_LOW); +} + +/** + * This function sets the scl pin. + * + * @param soft i2c config class. + * @param The scl pin state. + */ +static void nu_soft_i2c_set_scl(void *data, rt_int32_t state) +{ + struct nu_soft_i2c_config *cfg = (struct nu_soft_i2c_config *)data; + + rt_pin_write(cfg->scl, state ? PIN_HIGH : PIN_LOW); +} + +/** + * This function gets the sda pin state. + * + * @param The sda pin state. + */ +static rt_int32_t nu_soft_i2c_get_sda(void *data) +{ + struct nu_soft_i2c_config *cfg = (struct nu_soft_i2c_config *)data; + return rt_pin_read(cfg->sda); +} + +/** + * This function gets the scl pin state. + * + * @param The scl pin state. + */ +static rt_int32_t nu_soft_i2c_get_scl(void *data) +{ + struct nu_soft_i2c_config *cfg = (struct nu_soft_i2c_config *)data; + return rt_pin_read(cfg->scl); +} + +/* Soft I2C initialization function */ +int rt_soft_i2c_init(void) +{ + rt_size_t obj_num = sizeof(nu_soft_i2c_obj) / sizeof(struct nu_soft_i2c); + rt_err_t result; + + for (int i = 0; i < obj_num; i++) + { + nu_soft_i2c_obj[i].ops = nu_soft_i2c_bit_ops; + nu_soft_i2c_obj[i].ops.data = (void *)&nu_soft_i2c_cfg[i]; + nu_soft_i2c_obj[i].soft_i2c_bus.priv = &nu_soft_i2c_obj[i].ops; + nu_soft_i2c_gpio_init(&nu_soft_i2c_cfg[i]); + result = rt_i2c_bit_add_bus(&nu_soft_i2c_obj[i].soft_i2c_bus, nu_soft_i2c_cfg[i].bus_name); + RT_ASSERT(result == RT_EOK); + nu_soft_i2c_bus_unlock(&nu_soft_i2c_cfg[i]); + + LOG_D("software simulation %s init done, pin scl: %d, pin sda %d", + nu_soft_i2c_cfg[i].bus_name, + nu_soft_i2c_cfg[i].scl, + nu_soft_i2c_cfg[i].sda); + } + + return 0; +} +INIT_BOARD_EXPORT(rt_soft_i2c_init); + +#endif //#if (defined(BSP_USING_SOFT_I2C) && defined(BSP_USING_GPIO) && defined(RT_USING_I2C_BITOPS) && defined(RT_USING_I2C) && defined(RT_USING_PIN)) diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_spi.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..8a29a847caaaba9834eafa9d60285be271ddba22 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_spi.c @@ -0,0 +1,667 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-2-27 YHKuo First version +* +******************************************************************************/ +#include + +#if defined(BSP_USING_SPI) || defined(BSP_USING_QSPI) +#include +#include +#include + +#include + + +/* Private define ---------------------------------------------------------------*/ + +#ifndef NU_SPI_USE_PDMA_MIN_THRESHOLD + #define NU_SPI_USE_PDMA_MIN_THRESHOLD 128 +#endif + +enum +{ + SPI_START = -1, +#if defined(BSP_USING_SPI0) + SPI0_IDX, +#endif +#if defined(BSP_USING_SPI1) + SPI1_IDX, +#endif +#if defined(BSP_USING_SPI2) + SPI2_IDX, +#endif +#if defined(BSP_USING_SPI3) + SPI3_IDX, +#endif + SPI_CNT +}; + +/* Private typedef --------------------------------------------------------------*/ + +/* Private functions ------------------------------------------------------------*/ +static void nu_spi_transmission_with_poll(struct nu_spi *spi_bus, + uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word); +static int nu_spi_register_bus(struct nu_spi *spi_bus, const char *name); +static rt_uint32_t nu_spi_bus_xfer(struct rt_spi_device *device, struct rt_spi_message *message); +static rt_err_t nu_spi_bus_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration); + +#if defined(BSP_USING_SPI_PDMA) || defined(BSP_USING_QSPI_PDMA) + static void nu_pdma_spi_rx_cb(void *pvUserData, uint32_t u32EventFilter); + static void nu_pdma_spi_tx_cb(void *pvUserData, uint32_t u32EventFilter); + static rt_err_t nu_pdma_spi_rx_config(struct nu_spi *spi_bus, uint8_t *pu8Buf, int32_t i32RcvLen, uint8_t bytes_per_word); + static rt_err_t nu_pdma_spi_tx_config(struct nu_spi *spi_bus, const uint8_t *pu8Buf, int32_t i32SndLen, uint8_t bytes_per_word); + static rt_size_t nu_spi_pdma_transmit(struct nu_spi *spi_bus, const uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word); +#endif +/* Public functions -------------------------------------------------------------*/ +void nu_spi_transfer(struct nu_spi *spi_bus, uint8_t *tx, uint8_t *rx, int length, uint8_t bytes_per_word); +void nu_spi_drain_rxfifo(SPI_T *spi_base); + +#if defined(BSP_USING_SPI_PDMA) || defined(BSP_USING_QSPI_PDMA) + rt_err_t nu_hw_spi_pdma_allocate(struct nu_spi *spi_bus); +#endif + +/* Private variables ------------------------------------------------------------*/ +static struct rt_spi_ops nu_spi_poll_ops = +{ + .configure = nu_spi_bus_configure, + .xfer = nu_spi_bus_xfer, +}; + +static struct nu_spi nu_spi_arr [] = +{ +#if defined(BSP_USING_SPI0) + { + .name = "spi0", + .spi_base = SPI0, + +#if defined(BSP_USING_SPI_PDMA) +#if defined(BSP_USING_SPI0_PDMA) + .pdma_perp_tx = PDMA_SPI0_TX, + .pdma_perp_rx = PDMA_SPI0_RX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + }, +#endif +#if defined(BSP_USING_SPI1) + { + .name = "spi1", + .spi_base = SPI1, + +#if defined(BSP_USING_SPI_PDMA) +#if defined(BSP_USING_SPI1_PDMA) + .pdma_perp_tx = PDMA_SPI1_TX, + .pdma_perp_rx = PDMA_SPI1_RX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + + }, +#endif +#if defined(BSP_USING_SPI2) + { + .name = "spi2", + .spi_base = SPI2, + +#if defined(BSP_USING_SPI_PDMA) +#if defined(BSP_USING_SPI2_PDMA) + .pdma_perp_tx = PDMA_SPI2_TX, + .pdma_perp_rx = PDMA_SPI2_RX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + + }, +#endif +#if defined(BSP_USING_SPI3) + { + .name = "spi3", + .spi_base = SPI3, + +#if defined(BSP_USING_SPI_PDMA) +#if defined(BSP_USING_SPI3_PDMA) + .pdma_perp_tx = PDMA_SPI3_TX, + .pdma_perp_rx = PDMA_SPI3_RX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + + }, +#endif + {0} +}; /* spi nu_spi */ + +static rt_err_t nu_spi_bus_configure(struct rt_spi_device *device, + struct rt_spi_configuration *configuration) +{ + struct nu_spi *spi_bus; + uint32_t u32SPIMode; + uint32_t u32BusClock; + rt_err_t ret = RT_EOK; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(configuration != RT_NULL); + + spi_bus = (struct nu_spi *) device->bus; + + /* Check mode */ + switch (configuration->mode & RT_SPI_MODE_3) + { + case RT_SPI_MODE_0: + u32SPIMode = SPI_MODE_0; + break; + case RT_SPI_MODE_1: + u32SPIMode = SPI_MODE_1; + break; + case RT_SPI_MODE_2: + u32SPIMode = SPI_MODE_2; + break; + case RT_SPI_MODE_3: + u32SPIMode = SPI_MODE_3; + break; + default: + ret = RT_EIO; + goto exit_nu_spi_bus_configure; + } + + /* Check data width */ + if (!(configuration->data_width == 8 || + configuration->data_width == 16 || + configuration->data_width == 24 || + configuration->data_width == 32)) + { + ret = RT_EINVAL; + goto exit_nu_spi_bus_configure; + } + + /* Try to set clock and get actual spi bus clock */ + u32BusClock = SPI_SetBusClock(spi_bus->spi_base, configuration->max_hz); + if (configuration->max_hz > u32BusClock) + { + rt_kprintf("%s clock max frequency is %dHz (!= %dHz)\n", spi_bus->name, u32BusClock, configuration->max_hz); + configuration->max_hz = u32BusClock; + } + + /* Need to initialize new configuration? */ + if (rt_memcmp(configuration, &spi_bus->configuration, sizeof(*configuration)) != 0) + { + rt_memcpy(&spi_bus->configuration, configuration, sizeof(*configuration)); + + SPI_Open(spi_bus->spi_base, SPI_MASTER, u32SPIMode, configuration->data_width, u32BusClock); + + if (configuration->mode & RT_SPI_CS_HIGH) + { + /* Set CS pin to LOW */ + SPI_SET_SS_LOW(spi_bus->spi_base); + } + else + { + /* Set CS pin to HIGH */ + SPI_SET_SS_HIGH(spi_bus->spi_base); + } + + if (configuration->mode & RT_SPI_MSB) + { + /* Set sequence to MSB first */ + SPI_SET_MSB_FIRST(spi_bus->spi_base); + } + else + { + /* Set sequence to LSB first */ + SPI_SET_LSB_FIRST(spi_bus->spi_base); + } + } + + /* Clear SPI RX FIFO */ + nu_spi_drain_rxfifo(spi_bus->spi_base); + +exit_nu_spi_bus_configure: + + return -(ret); +} + +#if defined(BSP_USING_SPI_PDMA) || defined(BSP_USING_QSPI_PDMA) +static void nu_pdma_spi_rx_cb(void *pvUserData, uint32_t u32EventFilter) +{ + struct nu_spi *spi_bus; + spi_bus = (struct nu_spi *)pvUserData; + + RT_ASSERT(spi_bus != RT_NULL); + + /* Get base address of spi register */ + SPI_T *spi_base = spi_bus->spi_base; + + if (u32EventFilter & NU_PDMA_EVENT_TRANSFER_DONE) + { + SPI_DISABLE_RX_PDMA(spi_base); // Stop DMA TX transfer + } +} +static rt_err_t nu_pdma_spi_rx_config(struct nu_spi *spi_bus, uint8_t *pu8Buf, int32_t i32RcvLen, uint8_t bytes_per_word) +{ + rt_err_t result = RT_EOK; + rt_uint8_t *dst_addr = NULL; + nu_pdma_memctrl_t memctrl = eMemCtl_Undefined; + + /* Get base address of spi register */ + SPI_T *spi_base = spi_bus->spi_base; + + rt_uint8_t spi_pdma_rx_chid = spi_bus->pdma_chanid_rx; + + result = nu_pdma_callback_register(spi_pdma_rx_chid, + nu_pdma_spi_rx_cb, + (void *)spi_bus, + NU_PDMA_EVENT_TRANSFER_DONE); + if (result != RT_EOK) + { + goto exit_nu_pdma_spi_rx_config; + } + + if (pu8Buf == RT_NULL) + { + memctrl = eMemCtl_SrcFix_DstFix; + dst_addr = (rt_uint8_t *) &spi_bus->dummy; + } + else + { + memctrl = eMemCtl_SrcFix_DstInc; + dst_addr = pu8Buf; + } + + result = nu_pdma_channel_memctrl_set(spi_pdma_rx_chid, memctrl); + if (result != RT_EOK) + { + goto exit_nu_pdma_spi_rx_config; + } + + result = nu_pdma_transfer(spi_pdma_rx_chid, + bytes_per_word * 8, + (uint32_t)&spi_base->RX, + (uint32_t)dst_addr, + i32RcvLen / bytes_per_word, + 0); +exit_nu_pdma_spi_rx_config: + + return result; +} + +static void nu_pdma_spi_tx_cb(void *pvUserData, uint32_t u32EventFilter) +{ + struct nu_spi *spi_bus; + spi_bus = (struct nu_spi *)pvUserData; + + RT_ASSERT(spi_bus != RT_NULL); + + /* Get base address of spi register */ + SPI_T *spi_base = spi_bus->spi_base; + + if (u32EventFilter & NU_PDMA_EVENT_TRANSFER_DONE) + { + SPI_DISABLE_TX_PDMA(spi_base); // Stop DMA TX transfer + } + rt_sem_release(spi_bus->m_psSemBus); + +} + +static rt_err_t nu_pdma_spi_tx_config(struct nu_spi *spi_bus, const uint8_t *pu8Buf, int32_t i32SndLen, uint8_t bytes_per_word) +{ + rt_err_t result = RT_EOK; + rt_uint8_t *src_addr = NULL; + nu_pdma_memctrl_t memctrl = eMemCtl_Undefined; + + /* Get base address of spi register */ + SPI_T *spi_base = spi_bus->spi_base; + + rt_uint8_t spi_pdma_tx_chid = spi_bus->pdma_chanid_tx; + + result = nu_pdma_callback_register(spi_pdma_tx_chid, + nu_pdma_spi_tx_cb, + (void *)spi_bus, + NU_PDMA_EVENT_TRANSFER_DONE); + if (result != RT_EOK) + { + goto exit_nu_pdma_spi_tx_config; + } + + if (pu8Buf == RT_NULL) + { + spi_bus->dummy = 0; + memctrl = eMemCtl_SrcFix_DstFix; + src_addr = (rt_uint8_t *)&spi_bus->dummy; + } + else + { + memctrl = eMemCtl_SrcInc_DstFix; + src_addr = (rt_uint8_t *)pu8Buf; + } + + result = nu_pdma_channel_memctrl_set(spi_pdma_tx_chid, memctrl); + if (result != RT_EOK) + { + goto exit_nu_pdma_spi_tx_config; + } + + result = nu_pdma_transfer(spi_pdma_tx_chid, + bytes_per_word * 8, + (uint32_t)src_addr, + (uint32_t)&spi_base->TX, + i32SndLen / bytes_per_word, + 0); +exit_nu_pdma_spi_tx_config: + + return result; +} + + +/** + * SPI PDMA transfer + */ +static rt_size_t nu_spi_pdma_transmit(struct nu_spi *spi_bus, const uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word) +{ + rt_err_t result = RT_EOK; + + /* Get base address of spi register */ + SPI_T *spi_base = spi_bus->spi_base; + + result = nu_pdma_spi_rx_config(spi_bus, recv_addr, length, bytes_per_word); + RT_ASSERT(result == RT_EOK); + result = nu_pdma_spi_tx_config(spi_bus, send_addr, length, bytes_per_word); + RT_ASSERT(result == RT_EOK); + + /* Trigger TX/RX at the same time. */ + SPI_TRIGGER_TX_PDMA(spi_base); + SPI_TRIGGER_RX_PDMA(spi_base); + + /* Wait PDMA transfer done */ + rt_sem_take(spi_bus->m_psSemBus, RT_WAITING_FOREVER); + + while (SPI_IS_BUSY(spi_base)); + + return result; +} + +rt_err_t nu_hw_spi_pdma_allocate(struct nu_spi *spi_bus) +{ + /* Allocate SPI_TX nu_dma channel */ + if ((spi_bus->pdma_chanid_tx = nu_pdma_channel_allocate(spi_bus->pdma_perp_tx)) < 0) + { + goto exit_nu_hw_spi_pdma_allocate; + } + /* Allocate SPI_RX nu_dma channel */ + else if ((spi_bus->pdma_chanid_rx = nu_pdma_channel_allocate(spi_bus->pdma_perp_rx)) < 0) + { + nu_pdma_channel_free(spi_bus->pdma_chanid_tx); + goto exit_nu_hw_spi_pdma_allocate; + } + + spi_bus->m_psSemBus = rt_sem_create("spibus_sem", 0, RT_IPC_FLAG_FIFO); + + return RT_EOK; + +exit_nu_hw_spi_pdma_allocate: + + return -(RT_ERROR); +} +#endif /* #if defined(BSP_USING_SPI_PDMA) || defined(BSP_USING_QSPI_PDMA) */ + +void nu_spi_drain_rxfifo(SPI_T *spi_base) +{ + while (SPI_IS_BUSY(spi_base)); + + // Drain SPI RX FIFO, make sure RX FIFO is empty + while (!SPI_GET_RX_FIFO_EMPTY_FLAG(spi_base)) + { + SPI_ClearRxFIFO(spi_base); + } +} + +static int nu_spi_read(SPI_T *spi_base, uint8_t *recv_addr, uint8_t bytes_per_word) +{ + int size = 0; + uint32_t val; + + // Read RX data + if (!SPI_GET_RX_FIFO_EMPTY_FLAG(spi_base)) + { + // Read data from SPI RX FIFO + switch (bytes_per_word) + { + case 4: + val = SPI_READ_RX(spi_base); + nu_set32_le(recv_addr, val); + break; + case 3: + val = SPI_READ_RX(spi_base); + nu_set24_le(recv_addr, val); + break; + case 2: + val = SPI_READ_RX(spi_base); + nu_set16_le(recv_addr, val); + break; + case 1: + *recv_addr = SPI_READ_RX(spi_base); + break; + } + size = bytes_per_word; + } + return size; +} + +static int nu_spi_write(SPI_T *spi_base, const uint8_t *send_addr, uint8_t bytes_per_word) +{ + // Wait SPI TX send data + while (SPI_GET_TX_FIFO_FULL_FLAG(spi_base)); + + // Input data to SPI TX + switch (bytes_per_word) + { + case 4: + SPI_WRITE_TX(spi_base, nu_get32_le(send_addr)); + break; + case 3: + SPI_WRITE_TX(spi_base, nu_get24_le(send_addr)); + break; + case 2: + SPI_WRITE_TX(spi_base, nu_get16_le(send_addr)); + break; + case 1: + SPI_WRITE_TX(spi_base, *((uint8_t *)send_addr)); + break; + } + + return bytes_per_word; +} + +/** + * @brief SPI bus polling + * @param dev : The pointer of the specified SPI module. + * @param send_addr : Source address + * @param recv_addr : Destination address + * @param length : Data length + */ +static void nu_spi_transmission_with_poll(struct nu_spi *spi_bus, + uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word) +{ + SPI_T *spi_base = spi_bus->spi_base; + + // Write-only + if ((send_addr != RT_NULL) && (recv_addr == RT_NULL)) + { + while (length > 0) + { + send_addr += nu_spi_write(spi_base, send_addr, bytes_per_word); + length -= bytes_per_word; + } + } // if (send_addr != RT_NULL && recv_addr == RT_NULL) + // Read-only + else if ((send_addr == RT_NULL) && (recv_addr != RT_NULL)) + { + spi_bus->dummy = 0; + while (length > 0) + { + /* Input data to SPI TX FIFO */ + length -= nu_spi_write(spi_base, (const uint8_t *)&spi_bus->dummy, bytes_per_word); + + /* Read data from RX FIFO */ + recv_addr += nu_spi_read(spi_base, recv_addr, bytes_per_word); + } + } // else if (send_addr == RT_NULL && recv_addr != RT_NULL) + // Read&Write + else + { + while (length > 0) + { + /* Input data to SPI TX FIFO */ + send_addr += nu_spi_write(spi_base, send_addr, bytes_per_word); + length -= bytes_per_word; + + /* Read data from RX FIFO */ + recv_addr += nu_spi_read(spi_base, recv_addr, bytes_per_word); + } + } // else + + /* Wait RX or drian RX-FIFO */ + if (recv_addr) + { + // Wait SPI transmission done + while (SPI_IS_BUSY(spi_base)) + { + while (!SPI_GET_RX_FIFO_EMPTY_FLAG(spi_base)) + { + recv_addr += nu_spi_read(spi_base, recv_addr, bytes_per_word); + } + } + + while (!SPI_GET_RX_FIFO_EMPTY_FLAG(spi_base)) + { + recv_addr += nu_spi_read(spi_base, recv_addr, bytes_per_word); + } + } + else + { + /* Clear SPI RX FIFO */ + nu_spi_drain_rxfifo(spi_base); + } +} + +void nu_spi_transfer(struct nu_spi *spi_bus, uint8_t *tx, uint8_t *rx, int length, uint8_t bytes_per_word) +{ + RT_ASSERT(spi_bus != RT_NULL); + +#if defined(BSP_USING_SPI_PDMA) + /* DMA transfer constrains */ + if ((spi_bus->pdma_chanid_rx >= 0) && + (!(uint32_t)tx % bytes_per_word) && + (!(uint32_t)rx % bytes_per_word) && + (bytes_per_word != 3) && + (length >= NU_SPI_USE_PDMA_MIN_THRESHOLD)) + nu_spi_pdma_transmit(spi_bus, tx, rx, length, bytes_per_word); + else + nu_spi_transmission_with_poll(spi_bus, tx, rx, length, bytes_per_word); +#else + nu_spi_transmission_with_poll(spi_bus, tx, rx, length, bytes_per_word); +#endif +} + +static rt_uint32_t nu_spi_bus_xfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ + struct nu_spi *spi_bus; + struct rt_spi_configuration *configuration; + uint8_t bytes_per_word; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(device->bus != RT_NULL); + RT_ASSERT(message != RT_NULL); + + spi_bus = (struct nu_spi *) device->bus; + configuration = (struct rt_spi_configuration *)&spi_bus->configuration; + bytes_per_word = configuration->data_width / 8; + + if ((message->length % bytes_per_word) != 0) + { + /* Say bye. */ + rt_kprintf("%s: error payload length(%d%%%d != 0).\n", spi_bus->name, message->length, bytes_per_word); + return 0; + } + + if (message->length > 0) + { + if (message->cs_take && !(configuration->mode & RT_SPI_NO_CS)) + { + if (configuration->mode & RT_SPI_CS_HIGH) + { + SPI_SET_SS_HIGH(spi_bus->spi_base); + } + else + { + SPI_SET_SS_LOW(spi_bus->spi_base); + } + } + + nu_spi_transfer(spi_bus, (uint8_t *)message->send_buf, (uint8_t *)message->recv_buf, message->length, bytes_per_word); + + if (message->cs_release && !(configuration->mode & RT_SPI_NO_CS)) + { + if (configuration->mode & RT_SPI_CS_HIGH) + { + SPI_SET_SS_LOW(spi_bus->spi_base); + } + else + { + SPI_SET_SS_HIGH(spi_bus->spi_base); + } + } + + } + + return message->length; +} + +static int nu_spi_register_bus(struct nu_spi *spi_bus, const char *name) +{ + return rt_spi_bus_register(&spi_bus->dev, name, &nu_spi_poll_ops); +} + +/** + * Hardware SPI Initial + */ +static int rt_hw_spi_init(void) +{ + int i; + + for (i = (SPI_START + 1); i < SPI_CNT; i++) + { + nu_spi_register_bus(&nu_spi_arr[i], nu_spi_arr[i].name); +#if defined(BSP_USING_SPI_PDMA) + nu_spi_arr[i].pdma_chanid_tx = -1; + nu_spi_arr[i].pdma_chanid_rx = -1; + if ((nu_spi_arr[i].pdma_perp_tx != NU_PDMA_UNUSED) && (nu_spi_arr[i].pdma_perp_rx != NU_PDMA_UNUSED)) + { + if (nu_hw_spi_pdma_allocate(&nu_spi_arr[i]) != RT_EOK) + { + rt_kprintf("Failed to allocate DMA channels for %s. We will use poll-mode for this bus.\n", nu_spi_arr[i].name); + } + } +#endif + } + + return 0; +} + +INIT_DEVICE_EXPORT(rt_hw_spi_init); + +#endif //#if defined(BSP_USING_SPI) diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_spi.h b/bsp/nuvoton/libraries/m480/rtt_port/drv_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..c75a126bee85e13b879ffaf0337497ac44275a6c --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_spi.h @@ -0,0 +1,49 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-2-7 Wayne First version +* +******************************************************************************/ + +#ifndef __DRV_SPI_H__ +#define __DRV_SPI_H__ + +#include +#include +#include + +#if defined(BSP_USING_SPI_PDMA) || defined(BSP_USING_QSPI_PDMA) + #include +#endif + +struct nu_spi +{ + struct rt_spi_bus dev; + char *name; + SPI_T *spi_base; + uint32_t dummy; +#if defined(BSP_USING_SPI_PDMA) || defined(BSP_USING_SPI_PDMA) + int16_t pdma_perp_tx; + int8_t pdma_chanid_tx; + int16_t pdma_perp_rx; + int8_t pdma_chanid_rx; + rt_sem_t m_psSemBus; +#endif + struct rt_qspi_configuration configuration; +}; + +typedef struct nu_spi *nu_spi_t; + +void nu_spi_drain_rxfifo(SPI_T *spi_base); +void nu_spi_transfer(struct nu_spi *spi_bus, uint8_t *tx, uint8_t *rx, int length, uint8_t bytes_per_word); + +#if defined(BSP_USING_SPI_PDMA) || defined(BSP_USING_SPI_PDMA) + rt_err_t nu_hw_spi_pdma_allocate(struct nu_spi *spi_bus); +#endif + +#endif // __DRV_SPI_H___ diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_spii2s.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_spii2s.c new file mode 100644 index 0000000000000000000000000000000000000000..bdb8e89fecea5be536c8fc232505118afe372c2d --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_spii2s.c @@ -0,0 +1,651 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-5-29 YHKuo First version +* +******************************************************************************/ + +#include + +#if defined(BSP_USING_SPII2S) + +#include +#include +#include + +/* Private define ---------------------------------------------------------------*/ +#define DBG_ENABLE +#define DBG_LEVEL DBG_LOG +#define DBG_SECTION_NAME "spii2s" +#define DBG_COLOR +#include + +enum +{ + SPII2S_START = -1, +#if defined(BSP_USING_SPII2S0) + SPII2S0_IDX, +#endif +#if defined(BSP_USING_SPII2S1) + SPII2S1_IDX, +#endif +#if defined(BSP_USING_SPII2S2) + SPII2S2_IDX, +#endif +#if defined(BSP_USING_SPII2S3) + SPII2S3_IDX, +#endif + SPII2S_CNT +}; + +/* Private functions ------------------------------------------------------------*/ +static rt_err_t nu_spii2s_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps); +static rt_err_t nu_spii2s_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps); +static rt_err_t nu_spii2s_init(struct rt_audio_device *audio); +static rt_err_t nu_spii2s_start(struct rt_audio_device *audio, int stream); +static rt_err_t nu_spii2s_stop(struct rt_audio_device *audio, int stream); +static void nu_spii2s_buffer_info(struct rt_audio_device *audio, struct rt_audio_buf_info *info); +/* Public functions -------------------------------------------------------------*/ +rt_err_t nu_spii2s_acodec_register(struct rt_audio_device *audio, nu_acodec_ops_t); + +/* Private variables ------------------------------------------------------------*/ +static struct nu_i2s g_nu_spii2s_arr [] = +{ +#if defined(BSP_USING_SPII2S0) + { + .name = "spii2s0", + .i2s_base = (I2S_T *)SPI0, //Avoid warning + .i2s_rst = SPI0_RST, + .i2s_dais = { + [NU_I2S_DAI_PLAYBACK] = { + .pdma_perp = PDMA_SPI0_TX, + }, + [NU_I2S_DAI_CAPTURE] = { + .pdma_perp = PDMA_SPI0_RX, + } + } + }, +#endif +#if defined(BSP_USING_SPII2S1) + { + .name = "spii2s1", + .i2s_base = (I2S_T *)SPI1, //Avoid warning + .i2s_rst = SPI1_RST, + .i2s_dais = { + [NU_I2S_DAI_PLAYBACK] = { + .pdma_perp = PDMA_SPI1_TX, + }, + [NU_I2S_DAI_CAPTURE] = { + .pdma_perp = PDMA_SPI1_RX, + } + } + }, +#endif +#if defined(BSP_USING_SPII2S2) + { + .name = "spii2s2", + .i2s_base = (I2S_T *)SPI2, //Avoid warning + .i2s_rst = SPI2_RST, + .i2s_dais = { + [NU_I2S_DAI_PLAYBACK] = { + .pdma_perp = PDMA_SPI2_TX, + }, + [NU_I2S_DAI_CAPTURE] = { + .pdma_perp = PDMA_SPI2_RX, + } + } + }, +#endif +#if defined(BSP_USING_SPII2S3) + { + .name = "spii2s3", + .i2s_base = (I2S_T *)SPI3, //Avoid warning + .i2s_rst = SPI3_RST, + .i2s_dais = { + [NU_I2S_DAI_PLAYBACK] = { + .pdma_perp = PDMA_SPI3_TX, + }, + [NU_I2S_DAI_CAPTURE] = { + .pdma_perp = PDMA_SPI3_RX, + } + } + }, +#endif +}; + +static void nu_pdma_spii2s_rx_cb(void *pvUserData, uint32_t u32EventFilter) +{ + nu_i2s_t psNuSPII2s = (nu_i2s_t)pvUserData; + nu_i2s_dai_t psNuSPII2sDai; + + RT_ASSERT(psNuSPII2s != RT_NULL); + psNuSPII2sDai = &psNuSPII2s->i2s_dais[NU_I2S_DAI_CAPTURE]; + + if (u32EventFilter & NU_PDMA_EVENT_TRANSFER_DONE) + { + // Report a buffer ready. + rt_uint8_t *pbuf_old = &psNuSPII2sDai->fifo[psNuSPII2sDai->fifo_block_idx * NU_I2S_DMA_BUF_BLOCK_SIZE] ; + psNuSPII2sDai->fifo_block_idx = (psNuSPII2sDai->fifo_block_idx + 1) % NU_I2S_DMA_BUF_BLOCK_NUMBER; + + /* Report upper layer. */ + rt_audio_rx_done(&psNuSPII2s->audio, pbuf_old, NU_I2S_DMA_BUF_BLOCK_SIZE); + } +} + +static void nu_pdma_spii2s_tx_cb(void *pvUserData, uint32_t u32EventFilter) +{ + nu_i2s_t psNuSPII2s = (nu_i2s_t)pvUserData; + nu_i2s_dai_t psNuSPII2sDai; + + RT_ASSERT(psNuSPII2s != RT_NULL); + psNuSPII2sDai = &psNuSPII2s->i2s_dais[NU_I2S_DAI_PLAYBACK]; + + if (u32EventFilter & NU_PDMA_EVENT_TRANSFER_DONE) + { + rt_audio_tx_complete(&psNuSPII2s->audio); + psNuSPII2sDai->fifo_block_idx = (psNuSPII2sDai->fifo_block_idx + 1) % NU_I2S_DMA_BUF_BLOCK_NUMBER; + } +} + +static rt_err_t nu_spii2s_pdma_sc_config(nu_i2s_t psNuSPII2s, E_NU_I2S_DAI dai) +{ + rt_err_t result = RT_EOK; + SPI_T *spii2s_base; + nu_i2s_dai_t psNuSPII2sDai; + int i; + uint32_t u32Src, u32Dst; + nu_pdma_cb_handler_t pfm_pdma_cb; + + RT_ASSERT(psNuSPII2s != RT_NULL); + + /* Get base address of spii2s register */ + spii2s_base = (SPI_T *)psNuSPII2s->i2s_base; + psNuSPII2sDai = &psNuSPII2s->i2s_dais[dai]; + + switch ((int)dai) + { + case NU_I2S_DAI_PLAYBACK: + pfm_pdma_cb = nu_pdma_spii2s_tx_cb; + u32Src = (uint32_t)&psNuSPII2sDai->fifo[0]; + u32Dst = (uint32_t)&spii2s_base->TX; + break; + + case NU_I2S_DAI_CAPTURE: + pfm_pdma_cb = nu_pdma_spii2s_rx_cb; + u32Src = (uint32_t)&spii2s_base->RX; + u32Dst = (uint32_t)&psNuSPII2sDai->fifo[0]; + break; + + default: + return -RT_EINVAL; + } + + result = nu_pdma_callback_register(psNuSPII2sDai->pdma_chanid, + pfm_pdma_cb, + (void *)psNuSPII2s, + NU_PDMA_EVENT_TRANSFER_DONE); + RT_ASSERT(result == RT_EOK); + + for (i = 0; i < NU_I2S_DMA_BUF_BLOCK_NUMBER; i++) + { + /* Setup dma descriptor entry */ + result = nu_pdma_desc_setup(psNuSPII2sDai->pdma_chanid, // Channel ID + psNuSPII2sDai->pdma_descs[i], // this descriptor + 32, // 32-bits + (dai == NU_I2S_DAI_PLAYBACK) ? u32Src + (i * NU_I2S_DMA_BUF_BLOCK_SIZE) : u32Src, //Memory or RXFIFO + (dai == NU_I2S_DAI_PLAYBACK) ? u32Dst : u32Dst + (i * NU_I2S_DMA_BUF_BLOCK_SIZE), //TXFIFO or Memory + (int32_t)NU_I2S_DMA_BUF_BLOCK_SIZE / 4, // Transfer count + psNuSPII2sDai->pdma_descs[(i + 1) % NU_I2S_DMA_BUF_BLOCK_NUMBER]); // Next descriptor + RT_ASSERT(result == RT_EOK); + } + + /* Assign head descriptor */ + result = nu_pdma_sg_transfer(psNuSPII2sDai->pdma_chanid, psNuSPII2sDai->pdma_descs[0], 0); + RT_ASSERT(result == RT_EOK); + + return result; +} + +static rt_bool_t nu_spii2s_capacity_check(struct rt_audio_configure *pconfig) +{ + switch (pconfig->samplebits) + { + case 8: + case 16: + /* case 24: PDMA constrain */ + case 32: + break; + default: + goto exit_nu_spii2s_capacity_check; + } + + switch (pconfig->channels) + { + case 1: + case 2: + break; + default: + goto exit_nu_spii2s_capacity_check; + } + + return RT_TRUE; + +exit_nu_spii2s_capacity_check: + + return RT_FALSE; +} + +static rt_err_t nu_spii2s_dai_setup(nu_i2s_t psNuSPII2s, struct rt_audio_configure *pconfig) +{ + rt_err_t result = RT_EOK; + nu_acodec_ops_t pNuACodecOps = RT_NULL; + RT_ASSERT(psNuSPII2s->AcodecOps != RT_NULL); + pNuACodecOps = psNuSPII2s->AcodecOps; + SPI_T *spii2s_base = (SPI_T *)psNuSPII2s->i2s_base; + + /* Open SPII2S */ + if (nu_spii2s_capacity_check(pconfig) == RT_TRUE) + { + /* Reset audio codec */ + if (pNuACodecOps->nu_acodec_reset) + result = pNuACodecOps->nu_acodec_reset(); + + if (result != RT_EOK) + goto exit_nu_spii2s_dai_setup; + + /* Setup audio codec */ + if (pNuACodecOps->nu_acodec_init) + result = pNuACodecOps->nu_acodec_init(); + + if (!pNuACodecOps->nu_acodec_init || result != RT_EOK) + goto exit_nu_spii2s_dai_setup; + + /* Setup acodec samplerate/samplebit/channel */ + if (pNuACodecOps->nu_acodec_dsp_control) + result = pNuACodecOps->nu_acodec_dsp_control(pconfig); + + if (!pNuACodecOps->nu_acodec_dsp_control || result != RT_EOK) + goto exit_nu_spii2s_dai_setup; + + SPII2S_Open(spii2s_base, + (psNuSPII2s->AcodecOps->role == NU_ACODEC_ROLE_MASTER) ? SPII2S_MODE_SLAVE : SPII2S_MODE_MASTER, + pconfig->samplerate, + (((pconfig->samplebits / 8) - 1) << SPI_I2SCTL_WDWIDTH_Pos), + (pconfig->channels == 1) ? SPII2S_MONO : SPII2S_STEREO, + SPII2S_FORMAT_I2S); + LOG_I("Open SPII2S."); + + /* Set MCLK and enable MCLK */ + SPII2S_EnableMCLK(spii2s_base, __HXT); + + /* Set unmute */ + if (pNuACodecOps->nu_acodec_mixer_control) + pNuACodecOps->nu_acodec_mixer_control(AUDIO_MIXER_MUTE, RT_FALSE); + } + else + result = -RT_EINVAL; + +exit_nu_spii2s_dai_setup: + + return result; +} + +static rt_err_t nu_spii2s_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps) +{ + rt_err_t result = RT_EOK; + nu_i2s_t psNuSPII2s; + nu_acodec_ops_t pNuACodecOps = RT_NULL; + + RT_ASSERT(audio != RT_NULL); + RT_ASSERT(caps != RT_NULL); + + psNuSPII2s = (nu_i2s_t)audio; + + RT_ASSERT(psNuSPII2s->AcodecOps != RT_NULL); + + pNuACodecOps = psNuSPII2s->AcodecOps; + + switch (caps->main_type) + { + case AUDIO_TYPE_QUERY: + switch (caps->sub_type) + { + case AUDIO_TYPE_QUERY: + caps->udata.mask = AUDIO_TYPE_INPUT | AUDIO_TYPE_OUTPUT | AUDIO_TYPE_MIXER; + break; + default: + result = -RT_ERROR; + break; + } // switch (caps->sub_type) + break; + + case AUDIO_TYPE_MIXER: + + if (pNuACodecOps->nu_acodec_mixer_query) + { + switch (caps->sub_type) + { + case AUDIO_MIXER_QUERY: + return pNuACodecOps->nu_acodec_mixer_query(AUDIO_MIXER_QUERY, &caps->udata.mask); + + default: + return pNuACodecOps->nu_acodec_mixer_query(caps->sub_type, (rt_uint32_t *)&caps->udata.value); + } // switch (caps->sub_type) + + } // if (pNuACodecOps->nu_acodec_mixer_query) + + result = -RT_ERROR; + break; + + case AUDIO_TYPE_INPUT: + case AUDIO_TYPE_OUTPUT: + + switch (caps->sub_type) + { + case AUDIO_DSP_PARAM: + caps->udata.config.channels = psNuSPII2s->config.channels; + caps->udata.config.samplebits = psNuSPII2s->config.samplebits; + caps->udata.config.samplerate = psNuSPII2s->config.samplerate; + break; + case AUDIO_DSP_SAMPLERATE: + caps->udata.config.samplerate = psNuSPII2s->config.samplerate; + break; + case AUDIO_DSP_CHANNELS: + caps->udata.config.channels = psNuSPII2s->config.channels; + break; + case AUDIO_DSP_SAMPLEBITS: + caps->udata.config.samplebits = psNuSPII2s->config.samplebits; + break; + default: + result = -RT_ERROR; + break; + } // switch (caps->sub_type) + break; + + } // switch (caps->main_type) + + return result; +} + +static rt_err_t nu_spii2s_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps) +{ + rt_err_t result = RT_EOK; + nu_i2s_t psNuSPII2s; + nu_acodec_ops_t pNuACodecOps = RT_NULL; + int stream = -1; + + RT_ASSERT(audio != RT_NULL); + RT_ASSERT(caps != RT_NULL); + + psNuSPII2s = (nu_i2s_t)audio; + + RT_ASSERT(psNuSPII2s->AcodecOps != RT_NULL); + pNuACodecOps = psNuSPII2s->AcodecOps; + + switch (caps->main_type) + { + case AUDIO_TYPE_MIXER: + if (psNuSPII2s->AcodecOps->nu_acodec_mixer_control) + psNuSPII2s->AcodecOps->nu_acodec_mixer_control(caps->sub_type, caps->udata.value); + break; + + + case AUDIO_TYPE_INPUT: + stream = AUDIO_STREAM_RECORD; + case AUDIO_TYPE_OUTPUT: + { + rt_bool_t bNeedReset = RT_FALSE; + + if (stream < 0) + stream = AUDIO_STREAM_REPLAY; + + switch (caps->sub_type) + { + case AUDIO_DSP_PARAM: + if (rt_memcmp(&psNuSPII2s->config, &caps->udata.config, sizeof(struct rt_audio_configure)) != 0) + { + rt_memcpy(&psNuSPII2s->config, &caps->udata.config, sizeof(struct rt_audio_configure)); + bNeedReset = RT_TRUE; + } + break; + case AUDIO_DSP_SAMPLEBITS: + if (psNuSPII2s->config.samplerate != caps->udata.config.samplebits) + { + psNuSPII2s->config.samplerate = caps->udata.config.samplebits; + bNeedReset = RT_TRUE; + } + break; + case AUDIO_DSP_CHANNELS: + if (psNuSPII2s->config.channels != caps->udata.config.channels) + { + pNuACodecOps->config.channels = caps->udata.config.channels; + bNeedReset = RT_TRUE; + } + break; + case AUDIO_DSP_SAMPLERATE: + if (psNuSPII2s->config.samplerate != caps->udata.config.samplerate) + { + psNuSPII2s->config.samplerate = caps->udata.config.samplerate; + bNeedReset = RT_TRUE; + } + break; + default: + result = -RT_ERROR; + break; + } // switch (caps->sub_type) + + if (bNeedReset) + { + return nu_spii2s_start(audio, stream); + } + } + break; + default: + result = -RT_ERROR; + break; + } // switch (caps->main_type) + + return result; +} + +static rt_err_t nu_spii2s_init(struct rt_audio_device *audio) +{ + rt_err_t result = RT_EOK; + nu_i2s_t psNuSPII2s; + + RT_ASSERT(audio != RT_NULL); + + psNuSPII2s = (nu_i2s_t)audio; + + /* Reset this module */ + SYS_ResetModule(psNuSPII2s->i2s_rst); + + return -(result); +} + +static rt_err_t nu_spii2s_start(struct rt_audio_device *audio, int stream) +{ + nu_i2s_t psNuSPII2s; + + RT_ASSERT(audio != RT_NULL); + + psNuSPII2s = (nu_i2s_t)audio; + + SPI_T *spii2s_base = (SPI_T *)psNuSPII2s->i2s_base; + + /* Restart all: SPII2S and codec. */ + nu_spii2s_stop(audio, stream); + if (nu_spii2s_dai_setup(psNuSPII2s, &psNuSPII2s->config) != RT_EOK) + return -RT_ERROR; + + switch (stream) + { + case AUDIO_STREAM_REPLAY: + { + nu_spii2s_pdma_sc_config(psNuSPII2s, NU_I2S_DAI_PLAYBACK); + + /* Start TX DMA */ + SPII2S_ENABLE_TXDMA(spii2s_base); + + /* Enable I2S Tx function */ + SPII2S_ENABLE_TX(spii2s_base); + + LOG_I("Start replay."); + } + break; + + case AUDIO_STREAM_RECORD: + { + nu_spii2s_pdma_sc_config(psNuSPII2s, NU_I2S_DAI_CAPTURE); + + /* Start RX DMA */ + SPII2S_ENABLE_RXDMA(spii2s_base); + + /* Enable I2S Rx function */ + SPII2S_ENABLE_RX(spii2s_base); + + LOG_I("Start record."); + } + break; + } + + return RT_EOK; +} + +static rt_err_t nu_spii2s_stop(struct rt_audio_device *audio, int stream) +{ + nu_i2s_t psNuSPII2s; + nu_i2s_dai_t psNuSPII2sDai = RT_NULL; + + RT_ASSERT(audio != RT_NULL); + + psNuSPII2s = (nu_i2s_t)audio; + + SPI_T *spii2s_base = (SPI_T *)psNuSPII2s->i2s_base; + + switch (stream) + { + case AUDIO_STREAM_REPLAY: + psNuSPII2sDai = &psNuSPII2s->i2s_dais[NU_I2S_DAI_PLAYBACK]; + + // Disable TX + SPII2S_DISABLE_TXDMA(spii2s_base); + SPII2S_DISABLE_TX(spii2s_base); + + LOG_I("Stop replay."); + break; + + case AUDIO_STREAM_RECORD: + psNuSPII2sDai = &psNuSPII2s->i2s_dais[NU_I2S_DAI_CAPTURE]; + + // Disable RX + SPII2S_DISABLE_RXDMA(spii2s_base); + SPII2S_DISABLE_RX(spii2s_base); + + LOG_I("Stop record."); + break; + + default: + return -RT_EINVAL; + } + + /* Stop DMA transfer. */ + nu_pdma_channel_terminate(psNuSPII2sDai->pdma_chanid); + + /* Close SPII2S */ + if (!(spii2s_base->I2SCTL & (SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_RXEN_Msk))) + { + SPII2S_DisableMCLK(spii2s_base); + SPII2S_Close(spii2s_base); + LOG_I("Close SPII2S."); + } + + /* Silence */ + rt_memset((void *)psNuSPII2sDai->fifo, 0, NU_I2S_DMA_FIFO_SIZE); + psNuSPII2sDai->fifo_block_idx = 0; + + return RT_EOK; +} + +static void nu_spii2s_buffer_info(struct rt_audio_device *audio, struct rt_audio_buf_info *info) +{ + nu_i2s_t psNuSPII2s; + + RT_ASSERT(audio != RT_NULL); + RT_ASSERT(info != RT_NULL); + + psNuSPII2s = (nu_i2s_t)audio; + + info->buffer = (rt_uint8_t *)psNuSPII2s->i2s_dais[NU_I2S_DAI_PLAYBACK].fifo ; + info->total_size = NU_I2S_DMA_FIFO_SIZE; + info->block_size = NU_I2S_DMA_BUF_BLOCK_SIZE; + info->block_count = NU_I2S_DMA_BUF_BLOCK_NUMBER; + + return; +} + +static struct rt_audio_ops nu_spii2s_audio_ops = +{ + .getcaps = nu_spii2s_getcaps, + .configure = nu_spii2s_configure, + + .init = nu_spii2s_init, + .start = nu_spii2s_start, + .stop = nu_spii2s_stop, + .transmit = RT_NULL, + .buffer_info = nu_spii2s_buffer_info +}; + +static rt_err_t nu_hw_spii2s_pdma_allocate(nu_i2s_dai_t psNuSPII2sDai) +{ + /* Allocate I2S nu_dma channel */ + if ((psNuSPII2sDai->pdma_chanid = nu_pdma_channel_allocate(psNuSPII2sDai->pdma_perp)) < 0) + { + goto nu_hw_spii2s_pdma_allocate; + } + + return RT_EOK; + +nu_hw_spii2s_pdma_allocate: + + return -(RT_ERROR); +} + +int rt_hw_spii2s_init(void) +{ + int i = 0, j = 0; + nu_i2s_dai_t psNuSPII2sDai; + + + for (j = (SPII2S_START + 1); j < SPII2S_CNT; j++) + { + for (i = 0; i < NU_I2S_DAI_CNT; i++) + { + uint8_t *pu8ptr = rt_malloc(NU_I2S_DMA_FIFO_SIZE); + psNuSPII2sDai = &g_nu_spii2s_arr[j].i2s_dais[i]; + psNuSPII2sDai->fifo = pu8ptr; + rt_memset(pu8ptr, 0, NU_I2S_DMA_FIFO_SIZE); + RT_ASSERT(psNuSPII2sDai->fifo != RT_NULL); + + psNuSPII2sDai->pdma_chanid = -1; + psNuSPII2sDai->fifo_block_idx = 0; + RT_ASSERT(nu_hw_spii2s_pdma_allocate(psNuSPII2sDai) == RT_EOK); + RT_ASSERT(nu_pdma_sgtbls_allocate(&psNuSPII2sDai->pdma_descs[0], NU_I2S_DMA_BUF_BLOCK_NUMBER) == RT_EOK); + } + + /* Register ops of audio device */ + g_nu_spii2s_arr[j].audio.ops = &nu_spii2s_audio_ops; + + /* Register device, RW: it is with replay and record functions. */ + rt_audio_register(&g_nu_spii2s_arr[j].audio, g_nu_spii2s_arr[j].name, RT_DEVICE_FLAG_RDWR, &g_nu_spii2s_arr[j]); + } + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_spii2s_init); +#endif //#if defined(BSP_USING_SPII2S) diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_timer.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_timer.c new file mode 100644 index 0000000000000000000000000000000000000000..331155e258ec9d3d3e70dda23c6bbcf394f14310 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_timer.c @@ -0,0 +1,325 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-2-7 YCHuang12 First version +* +******************************************************************************/ + +#include + +#if (defined(BSP_USING_TIMER) && defined(RT_USING_HWTIMER)) + +#include +#include + +/* Private define ---------------------------------------------------------------*/ +#define NU_TIMER_DEVICE(timer) (nu_timer_t *)(timer) + +/* Private typedef --------------------------------------------------------------*/ +typedef struct nu_timer +{ + rt_hwtimer_t parent; + TIMER_T *timer_periph; + IRQn_Type IRQn; +} nu_timer_t; + +/* Private functions ------------------------------------------------------------*/ +static void nu_timer_init(rt_hwtimer_t *timer, rt_uint32_t state); +static rt_err_t nu_timer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t opmode); +static void nu_timer_stop(rt_hwtimer_t *timer); +static rt_uint32_t nu_timer_count_get(rt_hwtimer_t *timer); +static rt_err_t nu_timer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args); + +/* Public functions -------------------------------------------------------------*/ + + +/* Private variables ------------------------------------------------------------*/ +#ifdef BSP_USING_TIMER0 + static nu_timer_t nu_timer0; +#endif + +#ifdef BSP_USING_TIMER1 + static nu_timer_t nu_timer1; +#endif + +#ifdef BSP_USING_TIMER2 + static nu_timer_t nu_timer2; +#endif + +#ifdef BSP_USING_TIMER3 + static nu_timer_t nu_timer3; +#endif + +static struct rt_hwtimer_info nu_timer_info = +{ + 12000000, /* maximum count frequency */ + 46875, /* minimum count frequency */ + 0xFFFFFF, /* the maximum counter value */ + HWTIMER_CNTMODE_UP,/* Increment or Decreasing count mode */ +}; + +static struct rt_hwtimer_ops nu_timer_ops = +{ + nu_timer_init, + nu_timer_start, + nu_timer_stop, + nu_timer_count_get, + nu_timer_control +}; + +/* Functions define ------------------------------------------------------------*/ +static void nu_timer_init(rt_hwtimer_t *timer, rt_uint32_t state) +{ + RT_ASSERT(timer != RT_NULL); + + nu_timer_t *nu_timer = NU_TIMER_DEVICE(timer->parent.user_data); + RT_ASSERT(nu_timer != RT_NULL); + RT_ASSERT(nu_timer->timer_periph != RT_NULL); + + if (1 == state) + { + uint32_t timer_clk; + struct rt_hwtimer_info *info = &nu_timer_info; + + timer_clk = TIMER_GetModuleClock(nu_timer->timer_periph); + info->maxfreq = timer_clk; + info->minfreq = timer_clk / 256; + TIMER_Open(nu_timer->timer_periph, TIMER_ONESHOT_MODE, 1); + TIMER_EnableInt(nu_timer->timer_periph); + NVIC_EnableIRQ(nu_timer->IRQn); + } + else + { + NVIC_DisableIRQ(nu_timer->IRQn); + TIMER_DisableInt(nu_timer->timer_periph); + TIMER_Close(nu_timer->timer_periph); + } +} + +static rt_err_t nu_timer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t opmode) +{ + rt_err_t err = RT_EOK; + RT_ASSERT(timer != RT_NULL); + + nu_timer_t *nu_timer = NU_TIMER_DEVICE(timer->parent.user_data); + RT_ASSERT(nu_timer != RT_NULL); + RT_ASSERT(nu_timer->timer_periph != RT_NULL); + + if (cnt > 1 && cnt <= 0xFFFFFF) + { + TIMER_SET_CMP_VALUE(nu_timer->timer_periph, cnt); + } + else + { + rt_kprintf("nu_timer_start set compared value failed\n"); + err = RT_ERROR; + } + + if (HWTIMER_MODE_PERIOD == opmode) + { + TIMER_SET_OPMODE(nu_timer->timer_periph, TIMER_PERIODIC_MODE); + } + else if (HWTIMER_MODE_ONESHOT == opmode) + { + TIMER_SET_OPMODE(nu_timer->timer_periph, TIMER_ONESHOT_MODE); + } + else + { + rt_kprintf("nu_timer_start set operation mode failed\n"); + err = RT_ERROR; + } + + TIMER_Start(nu_timer->timer_periph); + + return err; +} + +static void nu_timer_stop(rt_hwtimer_t *timer) +{ + RT_ASSERT(timer != RT_NULL); + + nu_timer_t *nu_timer = NU_TIMER_DEVICE(timer->parent.user_data); + RT_ASSERT(nu_timer != RT_NULL); + RT_ASSERT(nu_timer->timer_periph != RT_NULL); + + TIMER_Stop(nu_timer->timer_periph); +} + +static rt_uint32_t nu_timer_count_get(rt_hwtimer_t *timer) +{ + RT_ASSERT(timer != RT_NULL); + + nu_timer_t *nu_timer = NU_TIMER_DEVICE(timer->parent.user_data); + RT_ASSERT(nu_timer != RT_NULL); + RT_ASSERT(nu_timer->timer_periph != RT_NULL); + + return TIMER_GetCounter(nu_timer->timer_periph); +} + +static rt_err_t nu_timer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args) +{ + rt_err_t ret = RT_EOK; + + RT_ASSERT(timer != RT_NULL); + + nu_timer_t *nu_timer = NU_TIMER_DEVICE(timer->parent.user_data); + RT_ASSERT(nu_timer != RT_NULL); + RT_ASSERT(nu_timer->timer_periph != RT_NULL); + + switch (cmd) + { + case HWTIMER_CTRL_FREQ_SET: + { + uint32_t clk; + uint32_t pre; + + clk = TIMER_GetModuleClock(nu_timer->timer_periph); + pre = clk / *((uint32_t *)args) - 1; + TIMER_SET_PRESCALE_VALUE(nu_timer->timer_periph, pre); + *((uint32_t *)args) = clk / (pre + 1) ; + } + break; + + case HWTIMER_CTRL_STOP: + TIMER_Stop(nu_timer->timer_periph); + break; + + default: + ret = RT_EINVAL; + break; + } + + return ret; +} + +int rt_hw_timer_init(void) +{ + rt_err_t ret = RT_EOK; + +#ifdef BSP_USING_TIMER0 + nu_timer0.timer_periph = TIMER0; + nu_timer0.parent.info = &nu_timer_info; + nu_timer0.parent.ops = &nu_timer_ops; + nu_timer0.IRQn = TMR0_IRQn; + ret = rt_device_hwtimer_register(&nu_timer0.parent, "timer0", &nu_timer0); + if (ret != RT_EOK) + { + rt_kprintf("timer0 register failed\n"); + } + SYS_ResetModule(TMR0_RST); + CLK_EnableModuleClock(TMR0_MODULE); +#endif + +#ifdef BSP_USING_TIMER1 + nu_timer1.timer_periph = TIMER1; + nu_timer1.parent.info = &nu_timer_info; + nu_timer1.parent.ops = &nu_timer_ops; + nu_timer1.IRQn = TMR1_IRQn; + ret = rt_device_hwtimer_register(&nu_timer1.parent, "timer1", &nu_timer1); + if (ret != RT_EOK) + { + rt_kprintf("timer1 register failed\n"); + } + SYS_ResetModule(TMR1_RST); + CLK_EnableModuleClock(TMR1_MODULE); +#endif + +#ifdef BSP_USING_TIMER2 + nu_timer2.timer_periph = TIMER2; + nu_timer2.parent.info = &nu_timer_info; + nu_timer2.parent.ops = &nu_timer_ops; + nu_timer2.IRQn = TMR2_IRQn; + ret = rt_device_hwtimer_register(&nu_timer2.parent, "timer2", &nu_timer2); + if (ret != RT_EOK) + { + rt_kprintf("timer2 register failed\n"); + } + SYS_ResetModule(TMR2_RST); + CLK_EnableModuleClock(TMR2_MODULE); +#endif + +#ifdef BSP_USING_TIMER3 + nu_timer3.timer_periph = TIMER3; + nu_timer3.parent.info = &nu_timer_info; + nu_timer3.parent.ops = &nu_timer_ops; + nu_timer3.IRQn = TMR3_IRQn; + ret = rt_device_hwtimer_register(&nu_timer3.parent, "timer3", &nu_timer3); + if (ret != RT_EOK) + { + rt_kprintf("timer3 register failed\n"); + } + SYS_ResetModule(TMR3_RST); + CLK_EnableModuleClock(TMR3_MODULE); +#endif + + return ret; +} + +INIT_BOARD_EXPORT(rt_hw_timer_init); + +#ifdef BSP_USING_TIMER0 +void TMR0_IRQHandler(void) +{ + rt_interrupt_enter(); + + if (TIMER_GetIntFlag(TIMER0)) + { + TIMER_ClearIntFlag(TIMER0); + rt_device_hwtimer_isr(&nu_timer0.parent); + } + + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_TIMER1 +void TMR1_IRQHandler(void) +{ + rt_interrupt_enter(); + + if (TIMER_GetIntFlag(TIMER1)) + { + TIMER_ClearIntFlag(TIMER1); + rt_device_hwtimer_isr(&nu_timer1.parent); + } + + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_TIMER2 +void TMR2_IRQHandler(void) +{ + rt_interrupt_enter(); + + if (TIMER_GetIntFlag(TIMER2)) + { + TIMER_ClearIntFlag(TIMER2); + rt_device_hwtimer_isr(&nu_timer2.parent); + } + + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_TIMER3 +void TMR3_IRQHandler(void) +{ + rt_interrupt_enter(); + + if (TIMER_GetIntFlag(TIMER3)) + { + TIMER_ClearIntFlag(TIMER3); + rt_device_hwtimer_isr(&nu_timer3.parent); + } + + rt_interrupt_leave(); +} +#endif + +#endif //#if (defined(BSP_USING_TIMER) && defined(RT_USING_HWTIMER)) diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_timer_capture.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_timer_capture.c new file mode 100644 index 0000000000000000000000000000000000000000..5c32b90aa25f5bf4205c0ac4550c819e5af8ac90 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_timer_capture.c @@ -0,0 +1,322 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-5-21 Philo First version +* +******************************************************************************/ + +#include + +#if defined(BSP_USING_TIMER_CAPTURE) + +#include +#include + +/* Private typedef --------------------------------------------------------------*/ +typedef struct _timer +{ + struct rt_inputcapture_device parent; + TIMER_T *timer; + uint8_t u8Channel; + IRQn_Type irq; + uint32_t u32CurrentCnt; + rt_bool_t input_data_level; + rt_bool_t first_edge; +} nu_capture_t; + +/* Private functions ------------------------------------------------------------*/ +static rt_err_t nu_capture_init(struct rt_inputcapture_device *inputcapture); +static rt_err_t nu_capture_open(struct rt_inputcapture_device *inputcapture); +static rt_err_t nu_capture_close(struct rt_inputcapture_device *inputcapture); +static rt_err_t nu_capture_get_pulsewidth(struct rt_inputcapture_device *inputcapture, rt_uint32_t *pulsewidth_us); + +/* Private define ---------------------------------------------------------------*/ +#define TIMER_CHANNEL_NUM (4) + +#define TIMER0_POS (0) +#define TIMER1_POS (1) +#define TIMER2_POS (2) +#define TIMER3_POS (3) + +/* Timer prescale setting. Since it will affect the pulse width of measure, it is recommended to set to 2. */ +#define PSC_DIV (2) + +/* Public functions -------------------------------------------------------------*/ + + +/* Private variables ------------------------------------------------------------*/ +static const char *nu_timer_device_name[TIMER_CHANNEL_NUM] = { "timer0i0", "timer1i0", "timer2i0", "timer3i0"}; +static const IRQn_Type nu_timer_irq[TIMER_CHANNEL_NUM] = { TMR0_IRQn, TMR1_IRQn, TMR2_IRQn, TMR3_IRQn}; +static TIMER_T *nu_timer_base[TIMER_CHANNEL_NUM] = { TIMER0, TIMER1, TIMER2, TIMER3}; +static nu_capture_t *nu_timer_capture[TIMER_CHANNEL_NUM] = {0}; + +static struct rt_inputcapture_ops nu_capture_ops = +{ + .init = nu_capture_init, + .open = nu_capture_open, + .close = nu_capture_close, + .get_pulsewidth = nu_capture_get_pulsewidth, +}; + +/* Functions define ------------------------------------------------------------*/ +void timer_interrupt_handler(nu_capture_t *nu_timer_capture) +{ + TIMER_ClearCaptureIntFlag(nu_timer_capture->timer); + + /* Frist event is rising edge */ + if (nu_timer_capture->first_edge == RT_TRUE) + { + nu_timer_capture->first_edge = RT_FALSE; + nu_timer_capture->input_data_level = RT_FALSE; + } + else + { + nu_timer_capture->input_data_level = !nu_timer_capture->input_data_level; + nu_timer_capture->u32CurrentCnt = TIMER_GetCaptureData(nu_timer_capture->timer); + + rt_hw_inputcapture_isr(&nu_timer_capture->parent, nu_timer_capture->input_data_level); + } +} + +#if defined(BSP_USING_TIMER0_CAPTURE) +void TMR0_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + timer_interrupt_handler(nu_timer_capture[0]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif //defined(BSP_USING_TIMER0_CAPTURE) + +#if defined(BSP_USING_TIMER1_CAPTURE) +void TMR1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + timer_interrupt_handler(nu_timer_capture[1]); + + /* leave interrupt */ + rt_interrupt_leave(); + +} +#endif //defined(BSP_USING_TIMER1_CAPTURE) + +#if defined(BSP_USING_TIMER2_CAPTURE) +void TMR2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + timer_interrupt_handler(nu_timer_capture[2]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif //defined(BSP_USING_TIMER2_CAPTURE) + +#if defined(BSP_USING_TIMER3_CAPTURE) +void TMR3_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + timer_interrupt_handler(nu_timer_capture[3]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif //defined(BSP_USING_TIMER3_CAPTURE) + +static rt_err_t nu_capture_get_pulsewidth(struct rt_inputcapture_device *inputcapture, rt_uint32_t *pulsewidth_us) +{ + rt_err_t ret = RT_EOK; + nu_capture_t *nu_capture; + + nu_capture = (nu_capture_t *)inputcapture; + + *pulsewidth_us = nu_capture->u32CurrentCnt / PSC_DIV; + + return -(ret); +} + +static rt_err_t nu_timer_init(nu_capture_t *nu_capture) +{ + rt_err_t ret = RT_ERROR; + + SYS_UnlockReg(); + +#if defined(BSP_USING_TIMER0_CAPTURE) + if (nu_capture->timer == TIMER0) + { + /* Enable TIMER0 clock */ + CLK_EnableModuleClock(TMR0_MODULE); + CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_PCLK0, 0); + + ret = RT_EOK; + goto exit_nu_timer_init; + } +#endif +#if defined(BSP_USING_TIMER1_CAPTURE) + if (nu_capture->timer == TIMER1) + { + /* Enable TIMER1 clock */ + CLK_EnableModuleClock(TMR1_MODULE); + CLK_SetModuleClock(TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_PCLK0, 0); + + ret = RT_EOK; + goto exit_nu_timer_init; + } +#endif +#if defined(BSP_USING_TIMER2_CAPTURE) + if (nu_capture->timer == TIMER2) + { + /* Enable TIMER2 clock */ + CLK_EnableModuleClock(TMR2_MODULE); + CLK_SetModuleClock(TMR2_MODULE, CLK_CLKSEL1_TMR2SEL_PCLK1, 0); + + ret = RT_EOK; + goto exit_nu_timer_init; + } +#endif +#if defined(BSP_USING_TIMER3_CAPTURE) + if (nu_capture->timer == TIMER3) + { + /* Enable TIMER3 clock */ + CLK_EnableModuleClock(TMR3_MODULE); + CLK_SetModuleClock(TMR3_MODULE, CLK_CLKSEL1_TMR3SEL_PCLK1, 0); + } +#endif + +exit_nu_timer_init: + SYS_LockReg(); + return -(ret); +} + +static rt_err_t nu_capture_init(struct rt_inputcapture_device *inputcapture) +{ + rt_err_t ret = RT_EOK; + nu_capture_t *nu_capture; + + RT_ASSERT(inputcapture != RT_NULL); + + nu_capture = (nu_capture_t *) inputcapture; + + if (nu_timer_init(nu_capture) != RT_EOK) + { + rt_kprintf("Failed to initialize TIMER.\n"); + ret = RT_ERROR; + } + + return -(ret); +} + +static uint8_t cal_time_prescale(nu_capture_t *nu_capture) +{ + uint32_t u32Clk = TIMER_GetModuleClock(nu_capture->timer); + + /* 1 tick = 1/PSC_DIV us */ + return (u32Clk / 1000000 / PSC_DIV) - 1; +} + +static rt_err_t nu_capture_open(struct rt_inputcapture_device *inputcapture) +{ + rt_err_t ret = RT_EOK; + nu_capture_t *nu_capture; + + RT_ASSERT(inputcapture != RT_NULL); + + nu_capture = (nu_capture_t *) inputcapture; + + nu_capture->first_edge = RT_TRUE; + + /* Enable Timer NVIC */ + NVIC_EnableIRQ(nu_capture->irq); + + TIMER_Open(nu_capture->timer, TIMER_CONTINUOUS_MODE, 1); + TIMER_SET_PRESCALE_VALUE(nu_capture->timer, cal_time_prescale(nu_capture)); + TIMER_SET_CMP_VALUE(nu_capture->timer, 0xFFFFFF); + + TIMER_EnableCapture(nu_capture->timer, TIMER_CAPTURE_COUNTER_RESET_MODE, TIMER_CAPTURE_EVENT_RISING_FALLING); + + TIMER_EnableInt(nu_capture->timer); + + TIMER_EnableCaptureInt(nu_capture->timer); + + TIMER_Start(nu_capture->timer); + + return ret; +} + +static rt_err_t nu_capture_close(struct rt_inputcapture_device *inputcapture) +{ + rt_err_t ret = RT_EOK; + + nu_capture_t *nu_capture; + + RT_ASSERT(inputcapture != RT_NULL); + + nu_capture = (nu_capture_t *) inputcapture; + + TIMER_Stop(nu_capture->timer); + + TIMER_DisableCaptureInt(nu_capture->timer); + + TIMER_DisableInt(nu_capture->timer); + + TIMER_Close(nu_capture->timer); + + NVIC_DisableIRQ(nu_capture->irq); + + return ret; +} + +/* Init and register timer capture */ +static int nu_timer_capture_device_init(void) +{ + uint8_t TIMER_MSK = 0; + +#if defined(BSP_USING_TIMER0_CAPTURE) + TIMER_MSK |= (0x1 << 0); +#endif +#if defined(BSP_USING_TIMER1_CAPTURE) + TIMER_MSK |= (0x1 << 1); +#endif +#if defined(BSP_USING_TIMER2_CAPTURE) + TIMER_MSK |= (0x1 << 2); +#endif +#if defined(BSP_USING_TIMER3_CAPTURE) + TIMER_MSK |= (0x1 << 3); +#endif + + for (int i = 0; i < TIMER_CHANNEL_NUM; i++) + { + if (TIMER_MSK & (0x1 << i)) + { + nu_timer_capture[i] = (nu_capture_t *)rt_malloc(sizeof(nu_capture_t)); + + nu_timer_capture[i]->timer = nu_timer_base[i]; + nu_timer_capture[i]->u8Channel = i; + nu_timer_capture[i]->irq = nu_timer_irq[i]; + nu_timer_capture[i]->u32CurrentCnt = 0; + nu_timer_capture[i]->parent.ops = &nu_capture_ops; + nu_timer_capture[i]->first_edge = RT_TRUE; + + /* register inputcapture device */ + rt_device_inputcapture_register(&nu_timer_capture[i]->parent, nu_timer_device_name[i], &nu_timer_capture[i]); + } + } + + return 0; +} +INIT_DEVICE_EXPORT(nu_timer_capture_device_init); + +#endif //#if defined(BSP_USING_TIMER_CAPTURE) diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_tpwm.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_tpwm.c new file mode 100644 index 0000000000000000000000000000000000000000..0b555fe8e78ff8088c1c297ed0cd7f5dcf820923 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_tpwm.c @@ -0,0 +1,237 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-5-5 YCHuang12 First version +* +* Note: 2 channels of a tpwm have the same output. +******************************************************************************/ + +#include + +#if (defined(BSP_USING_TPWM) && defined(RT_USING_PWM)) + +#define LOG_TAG "drv.tpwm" +#define DBG_ENABLE +#define DBG_SECTION_NAME LOG_TAG +#define DBG_LEVEL DBG_INFO +#define DBG_COLOR +#define TPWM_CHANNEL_NUM 2 +#include + +#include +#include +#include +#include "NuMicro.h" + +/* Private define ---------------------------------------------------------------*/ +#define NU_TPWM_DEVICE(tpwm) (nu_tpwm_t *)(tpwm) + +/* Private typedef --------------------------------------------------------------*/ +typedef struct nu_tpwm +{ + struct rt_device_pwm tpwm_dev; + char *name; + TIMER_T *tpwm_base; + rt_uint32_t channel_mask; //TPWM_CH0 | TPWM_CH1 +} nu_tpwm_t; + +/* Private functions ------------------------------------------------------------*/ +static rt_err_t nu_tpwm_enable(struct rt_device_pwm *tpwm_dev, struct rt_pwm_configuration *tpwm_config, rt_bool_t enable); +static rt_err_t nu_tpwm_set(struct rt_device_pwm *tpwm_dev, struct rt_pwm_configuration *tpwm_config); +static rt_err_t nu_tpwm_get(struct rt_device_pwm *tpwm_dev, struct rt_pwm_configuration *tpwm_config); +static rt_err_t nu_tpwm_control(struct rt_device_pwm *tpwm_dev, int cmd, void *arg); + +/* Private variables ------------------------------------------------------------*/ +#ifdef BSP_USING_TPWM0 + static nu_tpwm_t nu_tpwm0; +#endif + +#ifdef BSP_USING_TPWM1 + static nu_tpwm_t nu_tpwm1; +#endif + +#ifdef BSP_USING_TPWM2 + static nu_tpwm_t nu_tpwm2; +#endif + +#ifdef BSP_USING_TPWM3 + static nu_tpwm_t nu_tpwm3; +#endif + +static struct rt_pwm_ops nu_tpwm_ops = +{ + nu_tpwm_control +}; + +/* Functions define ------------------------------------------------------------*/ +static rt_err_t nu_tpwm_enable(struct rt_device_pwm *tpwm_dev, struct rt_pwm_configuration *tpwm_config, rt_bool_t enable) +{ + rt_err_t result = RT_EOK; + rt_uint32_t tpwm_channel = tpwm_config->channel; + nu_tpwm_t *nu_tpwm = NU_TPWM_DEVICE(tpwm_dev->parent.user_data); + + if (enable == RT_TRUE) + { + if (nu_tpwm->channel_mask == 0) + { + TPWM_START_COUNTER(nu_tpwm->tpwm_base); + } + nu_tpwm->channel_mask |= (1 << tpwm_channel); + TPWM_ENABLE_OUTPUT(nu_tpwm->tpwm_base, nu_tpwm->channel_mask); + } + else + { + nu_tpwm->channel_mask &= ~(1 << tpwm_channel); + TPWM_ENABLE_OUTPUT(nu_tpwm->tpwm_base, nu_tpwm->channel_mask); + if (nu_tpwm->channel_mask == 0) + { + TPWM_STOP_COUNTER(nu_tpwm->tpwm_base); + } + } + + return result; +} + +static rt_err_t nu_tpwm_set(struct rt_device_pwm *tpwm_dev, struct rt_pwm_configuration *tpwm_config) +{ + if (tpwm_config->period <= 0) + return -(RT_ERROR); + + rt_uint32_t tpwm_freq, tpwm_dutycycle ; + rt_uint32_t tpwm_period = tpwm_config->period; + rt_uint32_t tpwm_pulse = tpwm_config->pulse; + nu_tpwm_t *nu_tpwm = NU_TPWM_DEVICE(tpwm_dev->parent.user_data); + + rt_uint32_t pre_tpwm_prescaler = TPWM_GET_PRESCALER(nu_tpwm->tpwm_base); + + tpwm_freq = 1000000000 / tpwm_period; + tpwm_dutycycle = (tpwm_pulse * 100) / tpwm_period; + + TPWM_ConfigOutputFreqAndDuty(nu_tpwm->tpwm_base, tpwm_freq, tpwm_dutycycle) ; + + return RT_EOK; +} + +static rt_err_t nu_tpwm_get(struct rt_device_pwm *tpwm_dev, struct rt_pwm_configuration *tpwm_config) +{ + rt_uint32_t tpwm_real_period, tpwm_real_duty, time_tick, u32TPWMClockFreq ; + + nu_tpwm_t *nu_tpwm = NU_TPWM_DEVICE(tpwm_dev->parent.user_data); + rt_uint32_t tpwm_prescale = TPWM_GET_PRESCALER(nu_tpwm->tpwm_base); + rt_uint32_t tpwm_period = TPWM_GET_PERIOD(nu_tpwm->tpwm_base); + rt_uint32_t tpwm_pulse = TPWM_GET_CMPDAT(nu_tpwm->tpwm_base); + + u32TPWMClockFreq = TIMER_GetModuleClock(nu_tpwm->tpwm_base); + time_tick = 1000000000000 / u32TPWMClockFreq; + + tpwm_real_period = (((tpwm_prescale + 1) * (tpwm_period + 1)) * time_tick) / 1000; + tpwm_real_duty = (((tpwm_prescale + 1) * tpwm_pulse * time_tick)) / 1000; + tpwm_config->period = tpwm_real_period; + tpwm_config->pulse = tpwm_real_duty; + + LOG_I("%s %d %d %d\n", nu_tpwm->name, tpwm_config->channel, tpwm_config->period, tpwm_config->pulse); + + return RT_EOK; +} + +static rt_err_t nu_tpwm_control(struct rt_device_pwm *tpwm_dev, int cmd, void *arg) +{ + struct rt_pwm_configuration *tpwm_config = (struct rt_pwm_configuration *)arg; + + RT_ASSERT(tpwm_dev != RT_NULL); + RT_ASSERT(tpwm_config != RT_NULL); + + nu_tpwm_t *nu_tpwm = NU_TPWM_DEVICE(tpwm_dev->parent.user_data); + RT_ASSERT(nu_tpwm != RT_NULL); + RT_ASSERT(nu_tpwm->tpwm_base != RT_NULL); + + if ((tpwm_config->channel + 1) > TPWM_CHANNEL_NUM) + return -(RT_ERROR); + + switch (cmd) + { + case PWM_CMD_ENABLE: + return nu_tpwm_enable(tpwm_dev, tpwm_config, RT_TRUE); + case PWM_CMD_DISABLE: + return nu_tpwm_enable(tpwm_dev, tpwm_config, RT_FALSE); + case PWM_CMD_SET: + return nu_tpwm_set(tpwm_dev, tpwm_config); + case PWM_CMD_GET: + return nu_tpwm_get(tpwm_dev, tpwm_config); + default: + break; + } + return -(RT_EINVAL); +} + +int rt_hw_tpwm_init(void) +{ + rt_err_t ret = RT_EOK; + +#ifdef BSP_USING_TPWM0 + nu_tpwm0.tpwm_base = TIMER0; + nu_tpwm0.name = "tpwm0"; + nu_tpwm0.channel_mask = 0; + ret = rt_device_pwm_register(&nu_tpwm0.tpwm_dev, nu_tpwm0.name, &nu_tpwm_ops, &nu_tpwm0); + if (ret != RT_EOK) + { + rt_kprintf("tpwm0 register failed\n"); + } + SYS_ResetModule(TMR0_RST); + CLK_EnableModuleClock(TMR0_MODULE); + TPWM_ENABLE_PWM_MODE(TIMER0); +#endif + +#ifdef BSP_USING_TPWM1 + nu_tpwm1.tpwm_base = TIMER1; + nu_tpwm1.name = "tpwm1"; + nu_tpwm1.channel_mask = 0; + ret = rt_device_pwm_register(&nu_tpwm1.tpwm_dev, nu_tpwm1.name, &nu_tpwm_ops, &nu_tpwm1); + if (ret != RT_EOK) + { + rt_kprintf("tpwm1 register failed\n"); + } + SYS_ResetModule(TMR1_RST); + CLK_EnableModuleClock(TMR1_MODULE); + TPWM_ENABLE_PWM_MODE(TIMER1); +#endif + +#ifdef BSP_USING_TPWM2 + nu_tpwm2.tpwm_base = TIMER2; + nu_tpwm2.name = "tpwm2"; + nu_tpwm2.channel_mask = 0; + ret = rt_device_pwm_register(&nu_tpwm2.tpwm_dev, nu_tpwm2.name, &nu_tpwm_ops, &nu_tpwm2); + if (ret != RT_EOK) + { + rt_kprintf("tpwm2 register failed\n"); + } + SYS_ResetModule(TMR2_RST); + CLK_EnableModuleClock(TMR2_MODULE); + TPWM_ENABLE_PWM_MODE(TIMER2); +#endif + +#ifdef BSP_USING_TPWM3 + nu_tpwm3.tpwm_base = TIMER3; + nu_tpwm3.name = "tpwm3"; + nu_tpwm3.channel_mask = 0; + ret = rt_device_pwm_register(&nu_tpwm3.tpwm_dev, nu_tpwm3.name, &nu_tpwm_ops, &nu_tpwm3); + if (ret != RT_EOK) + { + rt_kprintf("tpwm3 register failed\n"); + } + SYS_ResetModule(TMR3_RST); + CLK_EnableModuleClock(TMR3_MODULE); + TPWM_ENABLE_PWM_MODE(TIMER3); +#endif + + return ret; +} + +INIT_DEVICE_EXPORT(rt_hw_tpwm_init); + +#endif //#if (defined(BSP_USING_TPWM) && defined(RT_USING_PWM)) diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_trng.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_trng.c new file mode 100644 index 0000000000000000000000000000000000000000..778a14cb3dd3c1b0df7cf775b4e405eb6bff1c77 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_trng.c @@ -0,0 +1,82 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-3-4 CHChen First version +* +******************************************************************************/ + +#include + +#if (defined(BSP_USING_TRNG) && defined(RT_HWCRYPTO_USING_RNG)) + +#include +#include +#include "NuMicro.h" + +#define NU_CRYPTO_TRNG_NAME "nu_TRNG" + +/* Private variables ------------------------------------------------------------*/ +static struct rt_mutex s_TRNG_mutex; +static int s_i32TRNGEnable = 0; + +static rt_uint32_t nu_trng_run(void) +{ + uint32_t u32RNGValue; + + rt_mutex_take(&s_TRNG_mutex, RT_WAITING_FOREVER); + + TRNG_Open(); + + if (TRNG_GenWord(&u32RNGValue) < 0) + { + //Failed, use software rand + u32RNGValue = rand(); + } + + rt_mutex_release(&s_TRNG_mutex); + return u32RNGValue; +} + +rt_err_t nu_trng_init(void) +{ + rt_mutex_init(&s_TRNG_mutex, NU_CRYPTO_TRNG_NAME, RT_IPC_FLAG_FIFO); + + if ((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x0) + { + rt_kprintf("This chip does not support TRNG!\n"); + return -RT_ERROR; + } + + s_i32TRNGEnable = 1; + SYS_ResetModule(TRNG_RST); + return RT_EOK; +} + +void nu_trng_open(void) +{ +#if defined(NU_PRNG_USE_SEED) + srand(NU_PRNG_SEED_VALUE); +#else + srand(rt_tick_get()); +#endif +} + +rt_uint32_t nu_trng_rand(struct hwcrypto_rng *ctx) +{ + if (!s_i32TRNGEnable) + { + uint32_t u32RNGValue; + //use software rand + u32RNGValue = rand(); + return u32RNGValue; + } + + return nu_trng_run(); +} + +#endif //#if (defined(BSP_USING_TRNG) && defined(RT_HWCRYPTO_USING_RNG)) diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_trng.h b/bsp/nuvoton/libraries/m480/rtt_port/drv_trng.h new file mode 100644 index 0000000000000000000000000000000000000000..7677323a4785c912986971f75691d5dc4498e9ea --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_trng.h @@ -0,0 +1,21 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-3-4 CHChen First version +* +******************************************************************************/ + +#ifndef __DRV_TRNG_H__ +#define __DRV_TRNG_H__ + +rt_err_t nu_trng_init(void); +void nu_trng_open(void); +rt_uint32_t nu_trng_rand(struct hwcrypto_rng *ctx); + +#endif + diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_uart.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_uart.c new file mode 100644 index 0000000000000000000000000000000000000000..b1c5ff45914c7157c35fda21b3b959ee9a513bb2 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_uart.c @@ -0,0 +1,838 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-2-7 Wayne First version +* +******************************************************************************/ + +#include + +#if defined(BSP_USING_UART) + +#include +#include +#include +#include + +#if defined(RT_SERIAL_USING_DMA) + #include +#endif + +/* Private define ---------------------------------------------------------------*/ +enum +{ + UART_START = -1, +#if defined(BSP_USING_UART0) + UART0_IDX, +#endif +#if defined(BSP_USING_UART1) + UART1_IDX, +#endif +#if defined(BSP_USING_UART2) + UART2_IDX, +#endif +#if defined(BSP_USING_UART3) + UART3_IDX, +#endif +#if defined(BSP_USING_UART4) + UART4_IDX, +#endif +#if defined(BSP_USING_UART5) + UART5_IDX, +#endif +#if defined(BSP_USING_UART6) + UART6_IDX, +#endif +#if defined(BSP_USING_UART7) + UART7_IDX, +#endif + UART_CNT +}; + +/* Private typedef --------------------------------------------------------------*/ +struct nu_uart +{ + rt_serial_t dev; + char *name; + UART_T *uart_base; + uint32_t uart_rst; + IRQn_Type uart_irq_n; + +#if defined(RT_SERIAL_USING_DMA) + uint32_t dma_flag; + int16_t pdma_perp_tx; + int8_t pdma_chanid_tx; + + int16_t pdma_perp_rx; + int8_t pdma_chanid_rx; + int32_t rx_write_offset; + int32_t rxdma_trigger_len; +#endif + +}; +typedef struct nu_uart *nu_uart_t; + +/* Private functions ------------------------------------------------------------*/ +static rt_err_t nu_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg); +static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *arg); +static int nu_uart_send(struct rt_serial_device *serial, char c); +static int nu_uart_receive(struct rt_serial_device *serial); +static void nu_uart_isr(nu_uart_t serial); + +#if defined(RT_SERIAL_USING_DMA) + static rt_size_t nu_uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction); + static void nu_pdma_uart_rx_cb(void *pvOwner, uint32_t u32Events); + static void nu_pdma_uart_tx_cb(void *pvOwner, uint32_t u32Events); +#endif + +/* Public functions ------------------------------------------------------------*/ + +/* Private variables ------------------------------------------------------------*/ + +static const struct rt_uart_ops nu_uart_ops = +{ + .configure = nu_uart_configure, + .control = nu_uart_control, + .putc = nu_uart_send, + .getc = nu_uart_receive, +#if defined(RT_SERIAL_USING_DMA) + .dma_transmit = nu_uart_dma_transmit +#else + .dma_transmit = RT_NULL +#endif +}; + +static const struct serial_configure nu_uart_default_config = + RT_SERIAL_CONFIG_DEFAULT; + +static struct nu_uart nu_uart_arr [] = +{ +#if defined(BSP_USING_UART0) + { + .name = "uart0", + .uart_base = UART0, + .uart_rst = UART0_RST, + .uart_irq_n = UART0_IRQn, + +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_USING_UART0_TX_DMA) + .pdma_perp_tx = PDMA_UART0_TX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, +#endif +#if defined(BSP_USING_UART0_RX_DMA) + .pdma_perp_rx = PDMA_UART0_RX, + .rx_write_offset = 0, +#else + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + }, +#endif + +#if defined(BSP_USING_UART1) + { + .name = "uart1", + .uart_base = UART1, + .uart_rst = UART1_RST, + .uart_irq_n = UART1_IRQn, +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_USING_UART1_TX_DMA) + .pdma_perp_tx = PDMA_UART1_TX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, +#endif +#if defined(BSP_USING_UART1_RX_DMA) + .pdma_perp_rx = PDMA_UART1_RX, + .rx_write_offset = 0, +#else + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + }, +#endif + +#if defined(BSP_USING_UART2) + { + .name = "uart2", + .uart_base = UART2, + .uart_rst = UART2_RST, + .uart_irq_n = UART2_IRQn, +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_USING_UART2_TX_DMA) + .pdma_perp_tx = PDMA_UART2_TX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, +#endif +#if defined(BSP_USING_UART2_RX_DMA) + .pdma_perp_rx = PDMA_UART2_RX, + .rx_write_offset = 0, +#else + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + }, +#endif + +#if defined(BSP_USING_UART3) + { + .name = "uart3", + .uart_base = UART3, + .uart_rst = UART3_RST, + .uart_irq_n = UART3_IRQn, +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_USING_UART3_TX_DMA) + .pdma_perp_tx = PDMA_UART3_TX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, +#endif +#if defined(BSP_USING_UART3_RX_DMA) + .pdma_perp_rx = PDMA_UART3_RX, + .rx_write_offset = 0, +#else + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + }, +#endif + +#if defined(BSP_USING_UART4) + { + .name = "uart4", + .uart_base = UART4, + .uart_rst = UART4_RST, + .uart_irq_n = UART4_IRQn, +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_USING_UART4_TX_DMA) + .pdma_perp_tx = PDMA_UART4_TX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, +#endif +#if defined(BSP_USING_UART4_RX_DMA) + .pdma_perp_rx = PDMA_UART4_RX, + .rx_write_offset = 0, +#else + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + }, +#endif + +#if defined(BSP_USING_UART5) + { + .name = "uart5", + .uart_base = UART5, + .uart_rst = UART5_RST, + .uart_irq_n = UART5_IRQn, +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_USING_UART5_TX_DMA) + .pdma_perp_tx = PDMA_UART5_TX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, +#endif +#if defined(BSP_USING_UART5_RX_DMA) + .pdma_perp_rx = PDMA_UART5_RX, + .rx_write_offset = 0, +#else + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + }, +#endif + +#if defined(BSP_USING_UART6) + { + .name = "uart6", + .uart_base = UART6, + .uart_rst = UART6_RST, + .uart_irq_n = UART6_IRQn, +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_USING_UART6_TX_DMA) + .pdma_perp_tx = PDMA_UART6_TX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, +#endif +#if defined(BSP_USING_UART6_RX_DMA) + .pdma_perp_rx = PDMA_UART6_RX, + .rx_write_offset = 0, +#else + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + }, +#endif + +#if defined(BSP_USING_UART7) + { + .name = "uart7", + .uart_base = UART7, + .uart_rst = UART7_RST, + .uart_irq_n = UART7_IRQn, +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_USING_UART7_TX_DMA) + .pdma_perp_tx = PDMA_UART7_TX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, +#endif +#if defined(BSP_USING_UART7_RX_DMA) + .pdma_perp_rx = PDMA_UART7_RX, + .rx_write_offset = 0, +#else + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + }, +#endif + {0} +}; /* uart nu_uart */ + +/* Interrupt Handle Funtion ----------------------------------------------------*/ +#if defined(BSP_USING_UART0) +/* UART0 interrupt entry */ +void UART0_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + nu_uart_isr(&nu_uart_arr[UART0_IDX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(BSP_USING_UART1) +/* UART1 interrupt entry */ +void UART1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + nu_uart_isr(&nu_uart_arr[UART1_IDX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(BSP_USING_UART2) +/* UART2 interrupt entry */ +void UART2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + nu_uart_isr(&nu_uart_arr[UART2_IDX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(BSP_USING_UART3) +/* UART3 interrupt service routine */ +void UART3_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + nu_uart_isr(&nu_uart_arr[UART3_IDX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(BSP_USING_UART4) +/* UART4 interrupt entry */ +void UART4_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + nu_uart_isr(&nu_uart_arr[UART4_IDX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(BSP_USING_UART5) +/* UART5 interrupt entry */ +void UART5_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + nu_uart_isr(&nu_uart_arr[UART5_IDX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(BSP_USING_UART6) +/* UART6 interrupt entry */ +void UART6_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + nu_uart_isr(&nu_uart_arr[UART6_IDX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(BSP_USING_UART7) +/* UART7 interrupt entry */ +void UART7_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + nu_uart_isr(&nu_uart_arr[UART7_IDX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +/** + * All UART interrupt service routine + */ +static void nu_uart_isr(nu_uart_t serial) +{ + /* Get base address of uart register */ + UART_T *uart_base = ((nu_uart_t)serial)->uart_base; + + /* Get interrupt event */ + uint32_t u32IntSts = uart_base->INTSTS; + uint32_t u32FIFOSts = uart_base->FIFOSTS; + +#if defined(RT_SERIAL_USING_DMA) + if (u32IntSts & UART_INTSTS_HWRLSIF_Msk) + { + uart_base->FIFOSTS |= (UART_FIFOSTS_BIF_Msk | UART_FIFOSTS_FEF_Msk | UART_FIFOSTS_PEF_Msk); + return; + } +#endif + + /* Handle RX event */ + if (u32IntSts & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) + { + rt_hw_serial_isr(&serial->dev, RT_SERIAL_EVENT_RX_IND); + } + uart_base->INTSTS = u32IntSts; + uart_base->FIFOSTS = u32FIFOSts; +} + +/** + * Configurae uart port + */ +static rt_err_t nu_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + rt_err_t ret = RT_EOK; + uint32_t uart_word_len = 0; + uint32_t uart_stop_bit = 0; + uint32_t uart_parity = 0; + + /* Get base address of uart register */ + UART_T *uart_base = ((nu_uart_t)serial)->uart_base; + + /* Check baudrate */ + RT_ASSERT(cfg->baud_rate != 0); + + /* Check word len */ + switch (cfg->data_bits) + { + case DATA_BITS_5: + uart_word_len = UART_WORD_LEN_5; + break; + + case DATA_BITS_6: + uart_word_len = UART_WORD_LEN_6; + break; + + case DATA_BITS_7: + uart_word_len = UART_WORD_LEN_7; + break; + + case DATA_BITS_8: + uart_word_len = UART_WORD_LEN_8; + break; + + default: + rt_kprintf("Unsupported data length"); + ret = RT_EINVAL; + goto exit_nu_uart_configure; + } + + /* Check stop bit */ + switch (cfg->stop_bits) + { + case STOP_BITS_1: + uart_stop_bit = UART_STOP_BIT_1; + break; + + case STOP_BITS_2: + uart_stop_bit = UART_STOP_BIT_2; + break; + + default: + rt_kprintf("Unsupported stop bit"); + ret = RT_EINVAL; + goto exit_nu_uart_configure; + } + + /* Check parity */ + switch (cfg->parity) + { + case PARITY_NONE: + uart_parity = UART_PARITY_NONE; + break; + + case PARITY_ODD: + uart_parity = UART_PARITY_ODD; + break; + + case PARITY_EVEN: + uart_parity = UART_PARITY_EVEN; + break; + + default: + rt_kprintf("Unsupported parity"); + ret = RT_EINVAL; + goto exit_nu_uart_configure; + } + + /* Reset this module */ + SYS_ResetModule(((nu_uart_t)serial)->uart_rst); + + /* Open Uart and set UART Baudrate */ + UART_Open(uart_base, cfg->baud_rate); + + /* Set line configuration. */ + UART_SetLineConfig(uart_base, 0, uart_word_len, uart_parity, uart_stop_bit); + + /* Enable NVIC interrupt. */ + NVIC_EnableIRQ(((nu_uart_t)serial)->uart_irq_n); + +exit_nu_uart_configure: + + if (ret != RT_EOK) + UART_Close(uart_base); + + return -(ret); +} + +#if defined(RT_SERIAL_USING_DMA) +static rt_err_t nu_pdma_uart_rx_config(struct rt_serial_device *serial, uint8_t *pu8Buf, int32_t i32TriggerLen) +{ + rt_err_t result = RT_EOK; + + /* Get base address of uart register */ + UART_T *uart_base = ((nu_uart_t)serial)->uart_base; + + result = nu_pdma_callback_register(((nu_uart_t)serial)->pdma_chanid_rx, + nu_pdma_uart_rx_cb, + (void *)serial, + NU_PDMA_EVENT_TRANSFER_DONE | NU_PDMA_EVENT_TIMEOUT); + + result = nu_pdma_transfer(((nu_uart_t)serial)->pdma_chanid_rx, + 8, + (uint32_t)uart_base, + (uint32_t)pu8Buf, + i32TriggerLen, + 1000); //Idle-timeout, 1ms + + /* Enable Receive Line interrupt & Start DMA RX transfer. */ + UART_ENABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk); + UART_PDMA_ENABLE(uart_base, UART_INTEN_RXPDMAEN_Msk); + + return result; +} + +static void nu_pdma_uart_rx_cb(void *pvOwner, uint32_t u32Events) +{ + rt_size_t recv_len=0; + rt_size_t transferred_rxbyte = 0; + struct rt_serial_device *serial = (struct rt_serial_device *)pvOwner; + nu_uart_t puart = (nu_uart_t)serial; + RT_ASSERT(serial != RT_NULL); + + /* Get base address of uart register */ + UART_T *uart_base = puart->uart_base; + + transferred_rxbyte = nu_pdma_transferred_byte_get(puart->pdma_chanid_rx, puart->rxdma_trigger_len); + + if (u32Events & (NU_PDMA_EVENT_TRANSFER_DONE | NU_PDMA_EVENT_TIMEOUT)) + { + if (u32Events & NU_PDMA_EVENT_TRANSFER_DONE) + { + if (serial->config.bufsz != 0) + { + struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; + + nu_pdma_uart_rx_config(serial, &rx_fifo->buffer[0], puart->rxdma_trigger_len); // Config & trigger next + } + else + { + UART_DISABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk); + UART_PDMA_DISABLE(uart_base, UART_INTEN_RXPDMAEN_Msk); + } + transferred_rxbyte = puart->rxdma_trigger_len; + } + else if ((u32Events & NU_PDMA_EVENT_TIMEOUT) && !UART_GET_RX_EMPTY(uart_base)) + { + return; + } + + recv_len = transferred_rxbyte - puart->rx_write_offset; + + puart->rx_write_offset = transferred_rxbyte % puart->rxdma_trigger_len; + + } + + if ((serial->config.bufsz == 0) && (u32Events & NU_PDMA_EVENT_TRANSFER_DONE)) + { + recv_len = puart->rxdma_trigger_len; + } + + if (recv_len) + { + rt_hw_serial_isr(&puart->dev, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); + } +} + +static rt_err_t nu_pdma_uart_tx_config(struct rt_serial_device *serial) +{ + rt_err_t result = RT_EOK; + RT_ASSERT(serial != RT_NULL); + + result = nu_pdma_callback_register(((nu_uart_t)serial)->pdma_chanid_tx, + nu_pdma_uart_tx_cb, + (void *)serial, + NU_PDMA_EVENT_TRANSFER_DONE); + + return result; +} + +static void nu_pdma_uart_tx_cb(void *pvOwner, uint32_t u32Events) +{ + nu_uart_t puart = (nu_uart_t)pvOwner; + + RT_ASSERT(puart != RT_NULL); + + UART_PDMA_DISABLE(puart->uart_base, UART_INTEN_TXPDMAEN_Msk);// Stop DMA TX transfer + + if (u32Events & NU_PDMA_EVENT_TRANSFER_DONE) + { + rt_hw_serial_isr(&puart->dev, RT_SERIAL_EVENT_TX_DMADONE); + } +} + +/** + * Uart DMA transfer + */ +static rt_size_t nu_uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction) +{ + rt_err_t result = RT_EOK; + + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(buf != RT_NULL); + + /* Get base address of uart register */ + UART_T *uart_base = ((nu_uart_t)serial)->uart_base; + if (direction == RT_SERIAL_DMA_TX) + { + result = nu_pdma_transfer(((nu_uart_t)serial)->pdma_chanid_tx, + 8, + (uint32_t)buf, + (uint32_t)uart_base, + size, + 0); // wait-forever + UART_PDMA_ENABLE(uart_base, UART_INTEN_TXPDMAEN_Msk); // Start DMA TX transfer + } + else if (direction == RT_SERIAL_DMA_RX) + { + UART_DISABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk); + UART_PDMA_DISABLE(uart_base, UART_INTEN_RXPDMAEN_Msk); + // If config.bufsz = 0, serial will trigger once. + ((nu_uart_t)serial)->rxdma_trigger_len = size; + ((nu_uart_t)serial)->rx_write_offset = 0; + result = nu_pdma_uart_rx_config(serial, buf, size); + } + else + { + result = RT_ERROR; + } + + return result; +} + +static int nu_hw_uart_dma_allocate(nu_uart_t pusrt) +{ + RT_ASSERT(pusrt != RT_NULL); + + /* Allocate UART_TX nu_dma channel */ + if (pusrt->pdma_perp_tx != NU_PDMA_UNUSED) + { + pusrt->pdma_chanid_tx = nu_pdma_channel_allocate(pusrt->pdma_perp_tx); + if (pusrt->pdma_chanid_tx >= 0) + { + pusrt->dma_flag |= RT_DEVICE_FLAG_DMA_TX; + } + } + + /* Allocate UART_RX nu_dma channel */ + if (pusrt->pdma_perp_rx != NU_PDMA_UNUSED) + { + pusrt->pdma_chanid_rx = nu_pdma_channel_allocate(pusrt->pdma_perp_rx); + if (pusrt->pdma_chanid_rx >= 0) + { + pusrt->dma_flag |= RT_DEVICE_FLAG_DMA_RX; + } + } + + return RT_EOK; +} +#endif + +/** + * Uart interrupt control + */ +static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + rt_err_t result = RT_EOK; + rt_uint32_t flag; + rt_ubase_t ctrl_arg = (rt_ubase_t)arg; + + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(arg != RT_NULL); + + /* Get base address of uart register */ + UART_T *uart_base = ((nu_uart_t)serial)->uart_base; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) /* Disable INT-RX */ + { + flag = UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk; + UART_DISABLE_INT(uart_base, flag); + } + else if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) /* Disable DMA-RX */ + { + /* Disable Receive Line interrupt & Stop DMA RX transfer. */ +#if defined(RT_SERIAL_USING_DMA) + nu_pdma_channel_terminate(((nu_uart_t)serial)->pdma_chanid_rx); + UART_DISABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk); + UART_PDMA_DISABLE(uart_base, UART_INTEN_RXPDMAEN_Msk); +#endif + } + break; + + case RT_DEVICE_CTRL_SET_INT: + if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) /* Enable INT-RX */ + { + flag = UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk; + UART_ENABLE_INT(uart_base, flag); + } + break; + +#if defined(RT_SERIAL_USING_DMA) + case RT_DEVICE_CTRL_CONFIG: + if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) /* Configure and trigger DMA-RX */ + { + struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; + ((nu_uart_t)serial)->rxdma_trigger_len = serial->config.bufsz; + ((nu_uart_t)serial)->rx_write_offset = 0; + result = nu_pdma_uart_rx_config(serial, &rx_fifo->buffer[0], ((nu_uart_t)serial)->rxdma_trigger_len); // Config & trigger + } + else if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX) /* Configure DMA-TX */ + { + result = nu_pdma_uart_tx_config(serial); + } + break; +#endif + + } + return result; +} + +/** + * Uart put char + */ +static int nu_uart_send(struct rt_serial_device *serial, char c) +{ + RT_ASSERT(serial != RT_NULL); + + /* Get base address of uart register */ + UART_T *uart_base = ((nu_uart_t)serial)->uart_base; + + /* Waiting if TX-FIFO is full. */ + while (UART_IS_TX_FULL(uart_base)); + + /* Put char into TX-FIFO */ + UART_WRITE(uart_base, c); + + return 1; +} + +/** + * Uart get char + */ +static int nu_uart_receive(struct rt_serial_device *serial) +{ + RT_ASSERT(serial != RT_NULL); + + /* Get base address of uart register */ + UART_T *uart_base = ((nu_uart_t)serial)->uart_base; + + /* Return failure if RX-FIFO is empty. */ + if (UART_GET_RX_EMPTY(uart_base)) + { + return -1; + } + + /* Get char from RX-FIFO */ + return UART_READ(uart_base); +} + +/** + * Hardware UART Initialization + */ +rt_err_t rt_hw_uart_init(void) +{ + int i; + rt_uint32_t flag; + rt_err_t ret = RT_EOK; + + for (i = (UART_START + 1); i < UART_CNT; i++) + { + flag = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX; + + nu_uart_arr[i].dev.ops = &nu_uart_ops; + nu_uart_arr[i].dev.config = nu_uart_default_config; + +#if defined(RT_SERIAL_USING_DMA) + nu_uart_arr[i].dma_flag = 0; + nu_hw_uart_dma_allocate(&nu_uart_arr[i]); + flag |= nu_uart_arr[i].dma_flag; +#endif + + ret = rt_hw_serial_register(&nu_uart_arr[i].dev, nu_uart_arr[i].name, flag, NULL); + RT_ASSERT(ret == RT_EOK); + } + + return ret; +} + +#endif //#if defined(BSP_USING_UART) diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_uart.h b/bsp/nuvoton/libraries/m480/rtt_port/drv_uart.h new file mode 100644 index 0000000000000000000000000000000000000000..2596c9be0af1d02dc3e74b45840462d2f6a79da3 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_uart.h @@ -0,0 +1,20 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-2-7 Wayne First version +* +******************************************************************************/ + +#ifndef __DRV_UART_H__ +#define __DRV_UART_H__ + +#include + +rt_err_t rt_hw_uart_init(void); + +#endif /* __DRV_UART_H__ */ diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_ui2c.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_ui2c.c new file mode 100644 index 0000000000000000000000000000000000000000..52d7e53e7131abd875d76f204a4327f1fa90e158 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_ui2c.c @@ -0,0 +1,381 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-5-15 YCHuang12 First version +* +******************************************************************************/ + +#include + +#if (defined(BSP_USING_UI2C) && defined(RT_USING_I2C)) + +#include +#include + +/* Private define ---------------------------------------------------------------*/ +#define LOG_TAG "drv.ui2c" +#define DBG_ENABLE +#define DBG_SECTION_NAME LOG_TAG +#define DBG_LEVEL DBG_INFO +#define DBG_COLOR +#include + +#define SLV_10BIT_ADDR (0x1E<<2) //1111+0xx+r/w + +/* Private typedef --------------------------------------------------------------*/ +typedef struct nu_ui2c_bus +{ + struct rt_i2c_bus_device ui2c_dev; + struct rt_i2c_msg *msg; + UI2C_T *ui2c_base; + char *dev_name; +} nu_ui2c_bus_t; + +/* Private functions ------------------------------------------------------------*/ +static rt_size_t nu_ui2c_mst_xfer(struct rt_i2c_bus_device *ui2c_dev, + struct rt_i2c_msg msgs[], + rt_uint32_t num); + +static const struct rt_i2c_bus_device_ops nu_ui2c_ops = +{ + .master_xfer = nu_ui2c_mst_xfer, + .slave_xfer = NULL, + .i2c_bus_control = NULL, +}; + +/* Private variables ------------------------------------------------------------*/ +#ifdef BSP_USING_UI2C0 +#define UI2C0BUS_NAME "ui2c0" +static nu_ui2c_bus_t nu_ui2c0 = +{ + .ui2c_base = UI2C0, + .dev_name = UI2C0BUS_NAME, +}; +#endif /* BSP_USING_UI2C0 */ + +#ifdef BSP_USING_UI2C1 +#define UI2C1BUS_NAME "ui2c1" +static nu_ui2c_bus_t nu_ui2c1 = +{ + .ui2c_base = UI2C1, + .dev_name = UI2C1BUS_NAME, +}; +#endif /* BSP_USING_UI2C1 */ + +/* Functions define ------------------------------------------------------------*/ +#if (defined(BSP_USING_UI2C0) || defined(BSP_USING_UI2C1)) + +static inline rt_err_t nu_ui2c_wait_ready_with_timeout(nu_ui2c_bus_t *nu_ui2c) +{ + rt_tick_t start = rt_tick_get(); + while (!(UI2C_GET_PROT_STATUS(nu_ui2c->ui2c_base) & (UI2C_PROTSTS_STARIF_Msk | UI2C_PROTSTS_ACKIF_Msk | UI2C_PROTSTS_NACKIF_Msk | UI2C_PROTSTS_STORIF_Msk))) + { + if ((rt_tick_get() - start) > nu_ui2c->ui2c_dev.timeout) + { + LOG_E("\nui2c: timeout!\n"); + return -RT_ETIMEOUT; + } + } + + return RT_EOK; +} + +static inline rt_err_t nu_ui2c_send_data(nu_ui2c_bus_t *nu_ui2c, rt_uint8_t data) +{ + UI2C_SET_DATA(nu_ui2c->ui2c_base, data); + UI2C_SET_CONTROL_REG(nu_ui2c->ui2c_base, UI2C_CTL_PTRG); + return nu_ui2c_wait_ready_with_timeout(nu_ui2c); +} + +static rt_err_t nu_ui2c_send_address(nu_ui2c_bus_t *nu_ui2c, + struct rt_i2c_msg *msg) +{ + rt_uint16_t flags = msg->flags; + rt_uint16_t ignore_nack = msg->flags & RT_I2C_IGNORE_NACK; + rt_uint8_t addr1, addr2; + rt_err_t ret; + + if (flags & RT_I2C_ADDR_10BIT) + { + UI2C_ENABLE_10BIT_ADDR_MODE(nu_ui2c->ui2c_base); + /* Init Send 10-bit Addr */ + addr1 = ((msg->addr >> 8) | SLV_10BIT_ADDR) << 1; + addr2 = msg->addr & 0xff; + + LOG_D("addr1: %d, addr2: %d\n", addr1, addr2); + + ret = nu_ui2c_send_data(nu_ui2c, addr1); + if (ret != RT_EOK) //for timeout conditrion + return -RT_EIO; + + if (((UI2C_GET_PROT_STATUS(nu_ui2c->ui2c_base) & UI2C_PROTSTS_ACKIF_Msk) != UI2C_PROTSTS_ACKIF_Msk) && !ignore_nack) + { + LOG_E("NACK: sending first addr\n"); + + return -RT_EIO; + } + UI2C_CLR_PROT_INT_FLAG(nu_ui2c->ui2c_base, UI2C_PROTSTS_ACKIF_Msk); + + ret = nu_ui2c_send_data(nu_ui2c, addr2); + if (ret != RT_EOK) //for timeout conditrion + return -RT_EIO; + + if (((UI2C_GET_PROT_STATUS(nu_ui2c->ui2c_base) & UI2C_PROTSTS_ACKIF_Msk) != UI2C_PROTSTS_ACKIF_Msk) && !ignore_nack) + { + LOG_E("NACK: sending second addr\n"); + + return -RT_EIO; + } + UI2C_CLR_PROT_INT_FLAG(nu_ui2c->ui2c_base, UI2C_PROTSTS_ACKIF_Msk); + + if (flags & RT_I2C_RD) + { + LOG_D("send repeated start condition\n"); + + UI2C_SET_CONTROL_REG(nu_ui2c->ui2c_base, (UI2C_CTL_PTRG | UI2C_CTL_STA)); + ret = nu_ui2c_wait_ready_with_timeout(nu_ui2c); + if (ret != RT_EOK) //for timeout conditrion + return -RT_EIO; + + if (((UI2C_GET_PROT_STATUS(nu_ui2c->ui2c_base) & UI2C_PROTSTS_STARIF_Msk) != UI2C_PROTSTS_STARIF_Msk) && !ignore_nack) + { + LOG_E("sending repeated START fail\n"); + + return -RT_EIO; + } + UI2C_CLR_PROT_INT_FLAG(nu_ui2c->ui2c_base, UI2C_PROTSTS_STARIF_Msk); + + addr1 |= 0x01; + + ret = nu_ui2c_send_data(nu_ui2c, addr1); + if (ret != RT_EOK) //for timeout conditrion + return -RT_EIO; + + if (((UI2C_GET_PROT_STATUS(nu_ui2c->ui2c_base) & UI2C_PROTSTS_ACKIF_Msk) != UI2C_PROTSTS_ACKIF_Msk) && !ignore_nack) + { + LOG_E("NACK: sending repeated addr\n"); + + return -RT_EIO; + } + UI2C_CLR_PROT_INT_FLAG(nu_ui2c->ui2c_base, UI2C_PROTSTS_ACKIF_Msk); + } + } + else + { + /* 7-bit addr */ + addr1 = msg->addr << 1; + if (flags & RT_I2C_RD) + addr1 |= 1; + + /* Send device address */ + ret = nu_ui2c_send_data(nu_ui2c, addr1); /* Send Address */ + if (ret != RT_EOK) //for timeout conditrion + return -RT_EIO; + + if (((UI2C_GET_PROT_STATUS(nu_ui2c->ui2c_base) & UI2C_PROTSTS_ACKIF_Msk) != UI2C_PROTSTS_ACKIF_Msk) + && !ignore_nack) + { + LOG_E("sending addr fail\n"); + return -RT_EIO; + } + UI2C_CLR_PROT_INT_FLAG(nu_ui2c->ui2c_base, UI2C_PROTSTS_ACKIF_Msk); + } + + return RT_EOK; +} + +static rt_size_t nu_ui2c_mst_xfer(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], + rt_uint32_t num) +{ + struct rt_i2c_msg *msg; + nu_ui2c_bus_t *nu_ui2c; + rt_size_t i; + rt_uint32_t cnt_data; + rt_uint16_t ignore_nack; + rt_err_t ret; + + RT_ASSERT(bus != RT_NULL); + nu_ui2c = (nu_ui2c_bus_t *) bus; + + nu_ui2c->msg = msgs; + UI2C_Open(nu_ui2c->ui2c_base, 100000); + (nu_ui2c->ui2c_base)->PROTSTS = (nu_ui2c->ui2c_base)->PROTSTS;//Clear status + + UI2C_SET_CONTROL_REG(nu_ui2c->ui2c_base, UI2C_CTL_STA); + ret = nu_ui2c_wait_ready_with_timeout(nu_ui2c); + + if (ret != RT_EOK) //for timeout conditrion + { + rt_set_errno(-RT_ETIMEOUT); + return 0; + } + + if (((UI2C_GET_PROT_STATUS(nu_ui2c->ui2c_base) & UI2C_PROTSTS_STARIF_Msk) != UI2C_PROTSTS_STARIF_Msk)) /* Check Send START */ + { + i = 0; + LOG_E("Send START Fail"); + return i; + } + UI2C_CLR_PROT_INT_FLAG(nu_ui2c->ui2c_base, UI2C_PROTSTS_STARIF_Msk); + + for (i = 0; i < num; i++) + { + msg = &msgs[i]; + ignore_nack = msg->flags & RT_I2C_IGNORE_NACK; + + if (!(msg->flags & RT_I2C_NO_START)) + { + if (i) + { + UI2C_SET_CONTROL_REG(nu_ui2c->ui2c_base, (UI2C_CTL_PTRG | UI2C_CTL_STA));/* Send repeat START */ + ret = nu_ui2c_wait_ready_with_timeout(nu_ui2c); + if (ret != RT_EOK) //for timeout conditrion + break; + + if (((UI2C_GET_PROT_STATUS(nu_ui2c->ui2c_base) & UI2C_PROTSTS_STARIF_Msk) != UI2C_PROTSTS_STARIF_Msk)) /* Check Send repeat START */ + { + i = 0; + LOG_E("Send repeat START Fail"); + break; + } + UI2C_CLR_PROT_INT_FLAG(nu_ui2c->ui2c_base, UI2C_PROTSTS_STARIF_Msk); + } + + if ((RT_EOK != nu_ui2c_send_address(nu_ui2c, msg)) + && !ignore_nack) + { + i = 0; + LOG_E("Send Address Fail"); + break; + } + } + + if (nu_ui2c->msg[i].flags & RT_I2C_RD) /* Receive Bytes */ + { + rt_uint32_t do_rd_nack = (i == (num - 1)); + for (cnt_data = 0 ; cnt_data < (nu_ui2c->msg[i].len) ; cnt_data++) + { + do_rd_nack += (cnt_data == (nu_ui2c->msg[i].len - 1)); /* NACK after last byte for hardware setting */ + if (do_rd_nack == 2) + { + UI2C_SET_CONTROL_REG(nu_ui2c->ui2c_base, UI2C_CTL_PTRG); + } + else + { + UI2C_SET_CONTROL_REG(nu_ui2c->ui2c_base, (UI2C_CTL_PTRG | UI2C_CTL_AA)); + } + + ret = nu_ui2c_wait_ready_with_timeout(nu_ui2c); + if (ret != RT_EOK) //for timeout conditrion + break; + + if (nu_ui2c->ui2c_base->PROTCTL & UI2C_CTL_AA) + { + if (((UI2C_GET_PROT_STATUS(nu_ui2c->ui2c_base) & UI2C_PROTSTS_ACKIF_Msk) != UI2C_PROTSTS_ACKIF_Msk)) /*Master Receive Data ACK*/ + { + i = 0; + break; + } + UI2C_CLR_PROT_INT_FLAG(nu_ui2c->ui2c_base, UI2C_PROTSTS_ACKIF_Msk); + } + else + { + if (((UI2C_GET_PROT_STATUS(nu_ui2c->ui2c_base) & UI2C_PROTSTS_NACKIF_Msk) != UI2C_PROTSTS_NACKIF_Msk)) /*Master Receive Data NACK*/ + { + i = 0; + break; + } + UI2C_CLR_PROT_INT_FLAG(nu_ui2c->ui2c_base, UI2C_PROTSTS_NACKIF_Msk); + } + + nu_ui2c->msg[i].buf[cnt_data] = nu_ui2c->ui2c_base->RXDAT; + } + } + else /* Send Bytes */ + { + for (cnt_data = 0 ; cnt_data < (nu_ui2c->msg[i].len) ; cnt_data++) + { + /* Send register number and MSB of data */ + ret = nu_ui2c_send_data(nu_ui2c, (uint8_t)(nu_ui2c->msg[i].buf[cnt_data])); + if (ret != RT_EOK) //for timeout conditrion + break; + + if (((UI2C_GET_PROT_STATUS(nu_ui2c->ui2c_base) & UI2C_PROTSTS_ACKIF_Msk) != UI2C_PROTSTS_ACKIF_Msk) + && !ignore_nack + ) /* Send aata and get Ack */ + { + i = 0; + break; + } + UI2C_CLR_PROT_INT_FLAG(nu_ui2c->ui2c_base, UI2C_PROTSTS_ACKIF_Msk); + } + } + } + + UI2C_SET_CONTROL_REG(nu_ui2c->ui2c_base, (UI2C_CTL_PTRG | UI2C_CTL_STO)); /* Send STOP signal */ + ret = nu_ui2c_wait_ready_with_timeout(nu_ui2c); + if (ret != RT_EOK) //for timeout conditrion + { + rt_set_errno(-RT_ETIMEOUT); + return 0; + } + + RT_ASSERT(((UI2C_GET_PROT_STATUS(nu_ui2c->ui2c_base) & UI2C_PROTSTS_STORIF_Msk) == UI2C_PROTSTS_STORIF_Msk)); + if (((UI2C_GET_PROT_STATUS(nu_ui2c->ui2c_base) & UI2C_PROTSTS_STORIF_Msk) != UI2C_PROTSTS_STORIF_Msk)) /* Bus Free*/ + { + i = 0; + LOG_E("Send STOP Fail"); + } + else if (nu_ui2c->msg[0].flags & RT_I2C_ADDR_10BIT) + { + UI2C_DISABLE_10BIT_ADDR_MODE(nu_ui2c->ui2c_base); + } + + UI2C_CLR_PROT_INT_FLAG(nu_ui2c->ui2c_base, UI2C_PROTSTS_STORIF_Msk); + UI2C_SET_CONTROL_REG(nu_ui2c->ui2c_base, UI2C_CTL_PTRG); + + (nu_ui2c->ui2c_base)->PROTSTS = (nu_ui2c->ui2c_base)->PROTSTS; + UI2C_Close(nu_ui2c->ui2c_base); + + nu_ui2c->msg = RT_NULL; + + return i; +} + +#endif //(defined(BSP_USING_UI2C0) || defined(BSP_USING_UI2C1)) + +/* Public functions -------------------------------------------------------------*/ +int rt_hw_ui2c_init(void) +{ + rt_err_t ret = RT_ERROR; + +#if defined(BSP_USING_UI2C0) + /* Enable UI2C0 clock */ + CLK_EnableModuleClock(USCI0_MODULE); + SYS_ResetModule(USCI0_RST); + nu_ui2c0.ui2c_dev.ops = &nu_ui2c_ops; + ret = rt_i2c_bus_device_register(&nu_ui2c0.ui2c_dev, nu_ui2c0.dev_name); + RT_ASSERT(RT_EOK == ret); +#endif /* BSP_USING_UI2C0 */ + +#if defined(BSP_USING_UI2C1) + /* Enable UI2C1 clock */ + CLK_EnableModuleClock(USCI1_MODULE); + SYS_ResetModule(USCI1_RST); + nu_ui2c1.ui2c_dev.ops = &nu_ui2c_ops; + ret = rt_i2c_bus_device_register(&nu_ui2c1.ui2c_dev, nu_ui2c1.dev_name); + RT_ASSERT(RT_EOK == ret); +#endif /* BSP_USING_UI2C1 */ + + return ret; +} + +INIT_DEVICE_EXPORT(rt_hw_ui2c_init); + +#endif //#if (defined(BSP_USING_UI2C) && defined(RT_USING_I2C)) diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_usbd.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_usbd.c new file mode 100644 index 0000000000000000000000000000000000000000..2c815bd4f66c2c04f44f38f536c6c7c1d97db889 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_usbd.c @@ -0,0 +1,537 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-3-25 Egbert First version +* +******************************************************************************/ + +#include + +#ifdef BSP_USING_USBD +#include +#include +#include +#include "NuMicro.h" + +#define LOG_TAG "drv.usbd" +#define DBG_ENABLE +#define DBG_SECTION_NAME "drv.usbd" +#define DBG_LEVEL DBG_ERROR +#define DBG_COLOR +#include + +/* Private define ---------------------------------------------------------------*/ +/* Define EP maximum packet size */ +#define EP0_MAX_PKT_SIZE 64 +#define EP1_MAX_PKT_SIZE EP0_MAX_PKT_SIZE /* EP0 and EP1 are assigned the same size for control endpoint */ +#define EP2_MAX_PKT_SIZE 64 +#define EP3_MAX_PKT_SIZE 64 +#define EP4_MAX_PKT_SIZE 64 +#define EP5_MAX_PKT_SIZE 64 +#define EP6_MAX_PKT_SIZE 64 +#define EP7_MAX_PKT_SIZE 64 +#define EP8_MAX_PKT_SIZE 64 +#define EP9_MAX_PKT_SIZE 64 + +#define SETUP_BUF_BASE 0 +#define SETUP_BUF_LEN 8 +#define EP0_BUF_BASE (SETUP_BUF_BASE + SETUP_BUF_LEN) +#define EP0_BUF_LEN EP0_MAX_PKT_SIZE + +#define EP1_BUF_BASE (SETUP_BUF_BASE + SETUP_BUF_LEN) +#define EP1_BUF_LEN EP1_MAX_PKT_SIZE +#define EP2_BUF_BASE (EP1_BUF_BASE + EP1_BUF_LEN) +#define EP2_BUF_LEN EP2_MAX_PKT_SIZE +#define EP3_BUF_BASE (EP2_BUF_BASE + EP2_BUF_LEN) +#define EP3_BUF_LEN EP3_MAX_PKT_SIZE +#define EP4_BUF_BASE (EP3_BUF_BASE + EP3_BUF_LEN) +#define EP4_BUF_LEN EP4_MAX_PKT_SIZE +#define EP5_BUF_BASE (EP4_BUF_BASE + EP4_BUF_LEN) +#define EP5_BUF_LEN EP5_MAX_PKT_SIZE +#define EP6_BUF_BASE (EP5_BUF_BASE + EP5_BUF_LEN) +#define EP6_BUF_LEN EP6_MAX_PKT_SIZE +#define EP7_BUF_BASE (EP6_BUF_BASE + EP6_BUF_LEN) +#define EP7_BUF_LEN EP7_MAX_PKT_SIZE +#define EP8_BUF_BASE (EP7_BUF_BASE + EP7_BUF_LEN) +#define EP8_BUF_LEN EP8_MAX_PKT_SIZE +#define EP9_BUF_BASE (EP8_BUF_BASE + EP8_BUF_LEN) +#define EP9_BUF_LEN EP9_MAX_PKT_SIZE + +#define EPADR_SW2HW(address) ((((address & USB_EPNO_MASK) * 2) + (!(address & USB_DIR_IN)))) +#define EPADR_HW2SW(address) ((address & USB_EPNO_MASK) / 2) +/* Private typedef --------------------------------------------------------------*/ +typedef struct _nu_usbd_t +{ + USBD_T *Instance; /* REG base */ + uint8_t address_tmp; /* Keep assigned address for flow control */ +} nu_usbd_t; + + +/* Private variables ------------------------------------------------------------*/ +static nu_usbd_t nu_usbd = +{ + .Instance = USBD, + .address_tmp = 0, +}; + +static struct udcd _rt_obj_udc; + +static struct ep_id _ep_pool[] = +{ + {EPADR_HW2SW(EP0), USB_EP_ATTR_CONTROL, USB_DIR_INOUT, EP0_MAX_PKT_SIZE, ID_ASSIGNED }, + {EPADR_HW2SW(EP2), USB_EP_ATTR_BULK, USB_DIR_IN, EP2_MAX_PKT_SIZE, ID_UNASSIGNED}, + {EPADR_HW2SW(EP3), USB_EP_ATTR_BULK, USB_DIR_OUT, EP3_MAX_PKT_SIZE, ID_UNASSIGNED}, + {EPADR_HW2SW(EP4), USB_EP_ATTR_INT, USB_DIR_IN, EP4_MAX_PKT_SIZE, ID_UNASSIGNED}, + {EPADR_HW2SW(EP5), USB_EP_ATTR_INT, USB_DIR_OUT, EP5_MAX_PKT_SIZE, ID_UNASSIGNED}, + {EPADR_HW2SW(EP6), USB_EP_ATTR_BULK, USB_DIR_IN, EP6_MAX_PKT_SIZE, ID_UNASSIGNED}, + {EPADR_HW2SW(EP7), USB_EP_ATTR_BULK, USB_DIR_OUT, EP7_MAX_PKT_SIZE, ID_UNASSIGNED}, + {EPADR_HW2SW(EP8), USB_EP_ATTR_INT, USB_DIR_IN, EP8_MAX_PKT_SIZE, ID_UNASSIGNED}, + {EPADR_HW2SW(EP9), USB_EP_ATTR_INT, USB_DIR_OUT, EP9_MAX_PKT_SIZE, ID_UNASSIGNED}, + {0xFF, USB_EP_ATTR_TYPE_MASK, USB_DIR_MASK, 0, ID_ASSIGNED }, +}; + +static void _nu_ep_partition(void) +{ + /* Init setup packet buffer */ + /* Buffer range for setup packet -> [0 ~ 0x7] */ + USBD->STBUFSEG = SETUP_BUF_BASE; + + /*****************************************************/ + /* EP0 ==> control IN endpoint, address 0 */ + USBD_CONFIG_EP(EP0, USBD_CFG_CSTALL | USBD_CFG_EPMODE_IN | EPADR_HW2SW(EP0)); + /* Buffer range for EP0 */ + USBD_SET_EP_BUF_ADDR(EP0, EP0_BUF_BASE); + + /* EP1 ==> control OUT endpoint, address 0 */ + USBD_CONFIG_EP(EP1, USBD_CFG_CSTALL | USBD_CFG_EPMODE_OUT | EPADR_HW2SW(EP1)); + /* Buffer range for EP1 */ + USBD_SET_EP_BUF_ADDR(EP1, EP1_BUF_BASE); + + /*****************************************************/ + /* EP2 ==> Bulk IN endpoint, address 1 */ + USBD_CONFIG_EP(EP2, USBD_CFG_EPMODE_IN | EPADR_HW2SW(EP2)); + /* Buffer range for EP2 */ + USBD_SET_EP_BUF_ADDR(EP2, EP2_BUF_BASE); + + /* EP3 ==> Bulk OUT endpoint, address 1 */ + USBD_CONFIG_EP(EP3, USBD_CFG_EPMODE_OUT | EPADR_HW2SW(EP3)); + /* Buffer range for EP3 */ + USBD_SET_EP_BUF_ADDR(EP3, EP3_BUF_BASE); + + /*****************************************************/ + /* EP4 ==> Interrupt IN endpoint, address 2 */ + USBD_CONFIG_EP(EP4, USBD_CFG_EPMODE_IN | EPADR_HW2SW(EP4)); + /* Buffer range for EP4 */ + USBD_SET_EP_BUF_ADDR(EP4, EP4_BUF_BASE); + + /* EP5 ==> Interrupt Out endpoint, address 2 */ + USBD_CONFIG_EP(EP5, USBD_CFG_EPMODE_OUT | EPADR_HW2SW(EP5)); + /* Buffer range for EP5 */ + USBD_SET_EP_BUF_ADDR(EP5, EP5_BUF_BASE); + + /*****************************************************/ + /* EP6 ==> Bulk IN endpoint, address 3 */ + USBD_CONFIG_EP(EP6, USBD_CFG_EPMODE_IN | EPADR_HW2SW(EP6)); + /* Buffer range for EP4 */ + USBD_SET_EP_BUF_ADDR(EP6, EP6_BUF_BASE); + + /* EP7 ==> Bulk Out endpoint, address 3 */ + USBD_CONFIG_EP(EP7, USBD_CFG_EPMODE_OUT | EPADR_HW2SW(EP7)); + /* Buffer range for EP5 */ + USBD_SET_EP_BUF_ADDR(EP7, EP7_BUF_BASE); + + /*****************************************************/ + /* EP8 ==> Interrupt IN endpoint, address 4 */ + USBD_CONFIG_EP(EP8, USBD_CFG_EPMODE_IN | EPADR_HW2SW(EP8)); + /* Buffer range for EP4 */ + USBD_SET_EP_BUF_ADDR(EP8, EP8_BUF_BASE); + + /* EP9 ==> Interrupt Out endpoint, address 4 */ + USBD_CONFIG_EP(EP9, USBD_CFG_EPMODE_OUT | EPADR_HW2SW(EP9)); + /* Buffer range for EP9 */ + USBD_SET_EP_BUF_ADDR(EP9, EP9_BUF_BASE); + +} + +static rt_err_t _ep_set_stall(rt_uint8_t address) +{ + USBD_SET_EP_STALL(EPADR_SW2HW(address)); + return RT_EOK; +} + +static rt_err_t _ep_clear_stall(rt_uint8_t address) +{ + USBD_ClearStall(EPADR_SW2HW(address)); + + return RT_EOK; +} + + +static rt_err_t _set_address(rt_uint8_t address) +{ + if (0 != address) + { + nu_usbd.address_tmp = address; + } + + return RT_EOK; +} + +static rt_err_t _set_config(rt_uint8_t address) +{ + return RT_EOK; +} + +static rt_err_t _ep_enable(uep_t ep) +{ + RT_ASSERT(ep != RT_NULL); + RT_ASSERT(ep->ep_desc != RT_NULL); + + USBD_CONFIG_EP(EPADR_SW2HW(EP_ADDRESS(ep)), + USBD_CFG_CSTALL + | ((EP_ADDRESS(ep) & USB_DIR_IN) ? USBD_CFG_EPMODE_IN : USBD_CFG_EPMODE_OUT) + | (EP_ADDRESS(ep) & USB_EPNO_MASK)); + + return RT_EOK; +} + +static rt_err_t _ep_disable(uep_t ep) +{ + RT_ASSERT(ep != RT_NULL); + RT_ASSERT(ep->ep_desc != RT_NULL); + + USBD_CONFIG_EP(EPADR_SW2HW(EP_ADDRESS(ep)), USBD_CFG_EPMODE_DISABLE); + + return RT_EOK; +} + +static rt_size_t _ep_read(rt_uint8_t address, void *buffer) +{ + rt_size_t size = 0; + rt_uint8_t *buf; + rt_uint32_t hw_ep_num = EPADR_SW2HW(address); + + RT_ASSERT(!(address & USB_DIR_IN)); + RT_ASSERT(buffer != RT_NULL); + + size = USBD_GET_PAYLOAD_LEN(hw_ep_num); + buf = (uint8_t *)(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(hw_ep_num)); + USBD_MemCopy(buffer, (uint8_t *)buf, size); + + return size; +} + +static rt_size_t _ep_read_prepare(rt_uint8_t address, void *buffer, rt_size_t size) +{ + RT_ASSERT(!(address & USB_DIR_IN)); + + USBD_SET_PAYLOAD_LEN(EPADR_SW2HW(address), size); + + return size; +} + +static rt_size_t _ep_write(rt_uint8_t address, void *buffer, rt_size_t size) +{ + RT_ASSERT((address & USB_DIR_IN)); + + /* even number is for IN endpoint */ + rt_uint32_t hw_ep_num = EPADR_SW2HW(address); + uint8_t *buf; + buf = (uint8_t *)(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(hw_ep_num)); + + USBD_MemCopy(buf, (uint8_t *)buffer, size); + + USBD_SET_PAYLOAD_LEN(hw_ep_num, size); + + return size; +} + +static rt_err_t _ep0_send_status(void) +{ + /* Status stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0); + return RT_EOK; +} + +static rt_err_t _suspend(void) +{ + return RT_EOK; +} + +static rt_err_t _wakeup(void) +{ + return RT_EOK; +} + +__STATIC_INLINE void _USBD_IRQHandler(void) +{ + rt_uint32_t u32IntSts = USBD_GET_INT_FLAG(); + rt_uint32_t u32State = USBD_GET_BUS_STATE(); + +//------------------------------------------------------------------ + if (u32IntSts & USBD_INTSTS_VBDETIF_Msk) + { + // Floating detect + USBD_CLR_INT_FLAG(USBD_INTSTS_VBDETIF_Msk); + + if (USBD_IS_ATTACHED()) + { + /* USB Plug In */ + USBD_ENABLE_USB(); + rt_usbd_connect_handler(&_rt_obj_udc); + } + else + { + /* USB Un-plug */ + USBD_DISABLE_USB(); + rt_usbd_disconnect_handler(&_rt_obj_udc); + } + } + + if (u32IntSts & USBD_INTSTS_SOFIF_Msk) + { + USBD_CLR_INT_FLAG(USBD_INTSTS_SOFIF_Msk); + rt_usbd_sof_handler(&_rt_obj_udc); + } +//------------------------------------------------------------------ + if (u32IntSts & USBD_INTSTS_BUSIF_Msk) + { + /* Clear event flag */ + USBD_CLR_INT_FLAG(USBD_INTSTS_BUSIF_Msk); + + if (u32State & USBD_ATTR_USBRST_Msk) + { + USBD_ENABLE_USB(); + + /* Reset PID DATA0 */ + for (rt_uint32_t i = 0ul; i < USBD_MAX_EP; i++) + { + nu_usbd.Instance->EP[i].CFG &= ~USBD_CFG_DSQSYNC_Msk; + } + + /* Reset USB device address */ + USBD_SET_ADDR(0ul); + + /* Bus reset */ + rt_usbd_reset_handler(&_rt_obj_udc); + } + if (u32State & USBD_ATTR_SUSPEND_Msk) + { + /* Enable USB but disable PHY */ + USBD_DISABLE_PHY(); + } + if (u32State & USBD_ATTR_RESUME_Msk) + { + /* Enable USB and enable PHY */ + USBD_ENABLE_USB(); + } + } + +//------------------------------------------------------------------ + if (u32IntSts & USBD_INTSTS_WAKEUP) + { + /* Clear event flag */ + USBD_CLR_INT_FLAG(USBD_INTSTS_WAKEUP); + USBD_ENABLE_USB(); + } + + if (u32IntSts & USBD_INTSTS_USBIF_Msk) + { + // USB event + if (u32IntSts & USBD_INTSTS_SETUP_Msk) + { + // Setup packet + /* Clear event flag */ + USBD_CLR_INT_FLAG(USBD_INTSTS_SETUP_Msk); + + /* Clear the data IN/OUT ready flag of control end-points */ + USBD_STOP_TRANSACTION(EP0); + USBD_STOP_TRANSACTION(EP1); + + USBD_SET_DATA1(EP0); + rt_usbd_ep0_setup_handler(&_rt_obj_udc, (struct urequest *)USBD_BUF_BASE); + } + + // EP events + if (u32IntSts & USBD_INTSTS_EP0) + { + /* Clear event flag */ + USBD_CLR_INT_FLAG(USBD_INTSTS_EP0); + + if ( (USBD_GET_ADDR() == 0) + && (nu_usbd.address_tmp) + ) + { + USBD_SET_ADDR(nu_usbd.address_tmp); + LOG_I("SET ADDR: 0x%02x", nu_usbd.address_tmp); + nu_usbd.address_tmp = 0; + } + + rt_usbd_ep0_in_handler(&_rt_obj_udc); + } + + if (u32IntSts & USBD_INTSTS_EP1) + { + /* Clear event flag */ + USBD_CLR_INT_FLAG(USBD_INTSTS_EP1); + rt_usbd_ep0_out_handler(&_rt_obj_udc, 0); + } + + if (u32IntSts & USBD_INTSTS_EP2) + { + /* Clear event flag */ + USBD_CLR_INT_FLAG(USBD_INTSTS_EP2); + rt_usbd_ep_in_handler(&_rt_obj_udc, USB_DIR_IN | EPADR_HW2SW(EP2), 0); + } + + if (u32IntSts & USBD_INTSTS_EP3) + { + /* Clear event flag */ + USBD_CLR_INT_FLAG(USBD_INTSTS_EP3); + rt_usbd_ep_out_handler(&_rt_obj_udc, USB_DIR_OUT | EPADR_HW2SW(EP3), 0); + } + + if (u32IntSts & USBD_INTSTS_EP4) + { + /* Clear event flag */ + USBD_CLR_INT_FLAG(USBD_INTSTS_EP4); + rt_usbd_ep_in_handler(&_rt_obj_udc, USB_DIR_IN | EPADR_HW2SW(EP4), 0); + } + + if (u32IntSts & USBD_INTSTS_EP5) + { + /* Clear event flag */ + USBD_CLR_INT_FLAG(USBD_INTSTS_EP5); + rt_usbd_ep_out_handler(&_rt_obj_udc, USB_DIR_OUT | EPADR_HW2SW(EP5), 0); + } + + if (u32IntSts & USBD_INTSTS_EP6) + { + /* Clear event flag */ + USBD_CLR_INT_FLAG(USBD_INTSTS_EP6); + rt_usbd_ep_in_handler(&_rt_obj_udc, USB_DIR_IN | EPADR_HW2SW(EP6), 0); + } + + if (u32IntSts & USBD_INTSTS_EP7) + { + /* Clear event flag */ + USBD_CLR_INT_FLAG(USBD_INTSTS_EP7); + rt_usbd_ep_out_handler(&_rt_obj_udc, USB_DIR_OUT | EPADR_HW2SW(EP7), 0); + } + + if (u32IntSts & USBD_INTSTS_EP8) + { + /* Clear event flag */ + USBD_CLR_INT_FLAG(USBD_INTSTS_EP8); + rt_usbd_ep_in_handler(&_rt_obj_udc, USB_DIR_IN | EPADR_HW2SW(EP8), 0); + } + + if (u32IntSts & USBD_INTSTS_EP9) + { + /* Clear event flag */ + USBD_CLR_INT_FLAG(USBD_INTSTS_EP9); + rt_usbd_ep_out_handler(&_rt_obj_udc, USB_DIR_OUT | EPADR_HW2SW(EP9), 0); + } + } +} + +void USBD_IRQHandler(void) +{ + rt_interrupt_enter(); + + _USBD_IRQHandler(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static rt_err_t _init(rt_device_t device) +{ + nu_usbd_t *nu_usbd = (nu_usbd_t *)device->user_data; + + /* Initialize USB PHY */ + SYS_UnlockReg(); + /* Select USBD */ + SYS->USBPHY = (SYS->USBPHY & ~SYS_USBPHY_USBROLE_Msk) | SYS_USBPHY_USBEN_Msk | SYS_USBPHY_SBO_Msk; + SYS_ResetModule(USBD_RST); + SYS_LockReg(); + + _nu_ep_partition(); + + /* Initial USB engine */ + nu_usbd->Instance->ATTR = 0x6D0ul; + + /* Force SE0 */ + USBD_SET_SE0(); + + NVIC_EnableIRQ(USBD_IRQn); + + USBD_Start(); + return RT_EOK; +} + +const static struct udcd_ops _udc_ops = +{ + _set_address, + _set_config, + _ep_set_stall, + _ep_clear_stall, + _ep_enable, + _ep_disable, + _ep_read_prepare, + _ep_read, + _ep_write, + _ep0_send_status, + _suspend, + _wakeup, +}; + +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops _ops = +{ + _init, + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, +}; +#endif + +int nu_usbd_register(void) +{ + if (RT_NULL != rt_device_find("usbd")) + { + LOG_E("\nUSBD Register failed. Another USBD device registered\n"); + return -RT_ERROR; + } + + rt_memset((void *)&_rt_obj_udc, 0, sizeof(struct udcd)); + _rt_obj_udc.parent.type = RT_Device_Class_USBDevice; + +#ifdef RT_USING_DEVICE_OPS + _rt_obj_udc.parent.ops = &_ops; +#else + _rt_obj_udc.parent.init = _init; +#endif + + _rt_obj_udc.parent.user_data = &nu_usbd; + _rt_obj_udc.ops = &_udc_ops; + /* Register endpoint infomation */ + _rt_obj_udc.ep_pool = _ep_pool; + _rt_obj_udc.ep0.id = &_ep_pool[0]; + + _rt_obj_udc.device_is_hs = RT_FALSE; /* Support Full-Speed only */ + + rt_device_register((rt_device_t)&_rt_obj_udc, "usbd", 0); + rt_usb_device_init(); + return RT_EOK; +} +INIT_DEVICE_EXPORT(nu_usbd_register); +#endif diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_usbhost.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_usbhost.c new file mode 100644 index 0000000000000000000000000000000000000000..dba7a4e4424db5631e1d01202b2e3a957fe9de00 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_usbhost.c @@ -0,0 +1,814 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-5-4 CHChen First version +* +******************************************************************************/ +#include + + + +#if defined(BSP_USING_USBH) || defined(BSP_USING_HSUSBH) + +#include +#include +#include + +#include "usb.h" +#include "usbh_lib.h" + +#define NU_MAX_USBH_PORT 2 //USB1.1 + USB2.0 port +#define NU_MAX_USBH_PIPE 16 +#define NU_USBH_THREAD_STACK_SIZE 2048 + +#define NU_MAX_USBH_HUB_PORT_DEV USB_HUB_PORT_NUM + +/* Private typedef --------------------------------------------------------------*/ +typedef struct nu_port_dev +{ + rt_bool_t bRHParent; + UDEV_T *pUDev; + EP_INFO_T *apsEPInfo[NU_MAX_USBH_PIPE]; + struct urequest asSetupReq[NU_MAX_USBH_PIPE]; + struct rt_completion utr_completion; + int port_num; + rt_bool_t bEnumDone; +} S_NU_PORT_DEV; + + +typedef struct nu_port_ctrl +{ + S_NU_PORT_DEV sRHPortDev; + S_NU_PORT_DEV asHubPortDev[NU_MAX_USBH_HUB_PORT_DEV]; +} S_NU_RH_PORT_CTRL; + + +struct nu_usbh_dev +{ + uhcd_t uhcd; + S_NU_RH_PORT_CTRL asPortCtrl[NU_MAX_USBH_PORT]; +}; + +/* Private variables ------------------------------------------------------------*/ +static struct nu_usbh_dev s_sUSBHDev = +{ + .uhcd = RT_NULL, +}; + +static S_NU_RH_PORT_CTRL * +GetRHPortControlFromPipe( + upipe_t pipe +) +{ + uinst_t inst; + int port; + if (pipe->inst->parent_hub->is_roothub) + { + //case: device ---> root hub + inst = pipe->inst; + port = inst->port; + } + else + { + //case: device ---> hub ---> root hub + inst = pipe->inst->parent_hub->self; + port = inst->port; + } + + if (port > NU_MAX_USBH_PORT) + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_open_pipe ERROR: port index over NU_MAX_USBH_PORT\n")); + return RT_NULL; + } + + return &s_sUSBHDev.asPortCtrl[port - 1];; +} + +static S_NU_PORT_DEV * +GetPortDevFromPipe( + upipe_t pipe +) +{ + S_NU_RH_PORT_CTRL *psRHPortCtrl = GetRHPortControlFromPipe(pipe); + int i; + + if (psRHPortCtrl == RT_NULL) + return RT_NULL; + + if (pipe->inst->parent_hub->is_roothub) + { + //case: device ---> root hub + return &psRHPortCtrl->sRHPortDev; + } + + //case: device ---> hub ---> root hub + for (i = 0 ; i < NU_MAX_USBH_HUB_PORT_DEV; i ++) + { + if (psRHPortCtrl->asHubPortDev[i].port_num == pipe->inst->port) + break; + } + + if (i >= NU_MAX_USBH_HUB_PORT_DEV) + return RT_NULL; + return &psRHPortCtrl->asHubPortDev[i]; +} + + + +static rt_err_t nu_reset_port(rt_uint8_t port) +{ + S_NU_RH_PORT_CTRL *psPortCtrl; + + if (port > NU_MAX_USBH_PORT) + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_reset_port ERROR: port index over NU_MAX_USBH_PORT\n")); + return RT_EIO; + } + + psPortCtrl = &s_sUSBHDev.asPortCtrl[port - 1]; + if (psPortCtrl->sRHPortDev.pUDev == NULL) + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_reset_port ERROR: udev not found\n")); + return RT_EIO; + } + + usbh_reset_port(psPortCtrl->sRHPortDev.pUDev); + + return RT_EOK; +} + +static EP_INFO_T *GetFreePipe( + S_NU_RH_PORT_CTRL *psPortCtrl, + S_NU_PORT_DEV *psPortDev, + rt_uint8_t *pu8PipeIndex +) +{ + rt_uint8_t i; + if (psPortCtrl == NULL) + return NULL; + + for (i = 1; i < NU_MAX_USBH_PIPE; i ++) + { + if (psPortDev->apsEPInfo[i] == NULL) + break; + } + + if (i >= NU_MAX_USBH_PIPE) + return RT_NULL; + + EP_INFO_T *psEPInfo = rt_malloc(sizeof(EP_INFO_T)); + + psPortDev->apsEPInfo[i] = psEPInfo; + *pu8PipeIndex = i; + return psEPInfo; +} + +static void FreePipe( + S_NU_RH_PORT_CTRL *psPortCtrl, + S_NU_PORT_DEV *psPortDev, + rt_uint8_t u8PipeIndex +) +{ + if (psPortCtrl == NULL) + return; + + if (u8PipeIndex >= NU_MAX_USBH_PIPE) + return; + + if (psPortDev->apsEPInfo[u8PipeIndex]) + { + rt_free(psPortDev->apsEPInfo[u8PipeIndex]); + psPortDev->apsEPInfo[u8PipeIndex] = RT_NULL; + } +} + +static S_NU_PORT_DEV * +AllocateNewUDev( + S_NU_RH_PORT_CTRL *psRHPortCtrl +) +{ + int i; + for (i = 0 ; i < NU_MAX_USBH_HUB_PORT_DEV; i ++) + { + if (psRHPortCtrl->asHubPortDev[i].pUDev == NULL) + break; + } + + if (i >= NU_MAX_USBH_HUB_PORT_DEV) + return RT_NULL; + + psRHPortCtrl->asHubPortDev[i].pUDev = alloc_device(); + + if (psRHPortCtrl->asHubPortDev[i].pUDev == NULL) + return RT_NULL; + + return &psRHPortCtrl->asHubPortDev[i]; +} + + +static rt_err_t nu_open_pipe(upipe_t pipe) +{ + S_NU_RH_PORT_CTRL *psPortCtrl; + S_NU_PORT_DEV *psPortDev; + + psPortCtrl = GetRHPortControlFromPipe(pipe); + if (psPortCtrl == RT_NULL) + { + return RT_EIO; + } + + if (psPortCtrl->sRHPortDev.pUDev == NULL) + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_open_pipe ERROR: udev not found\n")); + return RT_EIO; + } + + psPortDev = GetPortDevFromPipe(pipe); + + if ((psPortDev == NULL) || (psPortDev->pUDev == NULL)) + { + //allocate new dev for hub device + psPortDev = AllocateNewUDev(psPortCtrl); + + if (psPortDev == RT_NULL) + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_open_pipe ERROR: udev allocate failed\n")); + return RT_EIO; + } + + if (pipe->inst->speed) + { + psPortDev->pUDev->speed = SPEED_FULL; + } + else + { + psPortDev->pUDev->speed = SPEED_HIGH; + } + + psPortDev->pUDev->parent = NULL; + psPortDev->pUDev->hc_driver = psPortCtrl->sRHPortDev.pUDev->hc_driver; + psPortDev->port_num = pipe->inst->port; + psPortDev->pUDev->port_num = pipe->inst->port; + psPortDev->bEnumDone = FALSE; + } + + //For ep0 control transfer + if ((pipe->ep.bEndpointAddress & 0x7F) == 0) + { + pipe->pipe_index = 0; + return RT_EOK; + } + + EP_INFO_T *psEPInfo = GetFreePipe(psPortCtrl, psPortDev, &pipe->pipe_index); + + if (psEPInfo == RT_NULL) + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_open_pipe ERROR: get free pipe failed\n")); + return RT_ENOMEM; + } + + int pksz; + + psEPInfo->bEndpointAddress = pipe->ep.bEndpointAddress; + psEPInfo->bmAttributes = pipe->ep.bmAttributes; + + pksz = pipe->ep.wMaxPacketSize; + pksz = (pksz & 0x07ff) * (1 + ((pksz >> 11) & 3)); + psEPInfo->wMaxPacketSize = pksz; + + psEPInfo->bInterval = pipe->ep.bInterval; + psEPInfo->hw_pipe = NULL; + psEPInfo->bToggle = 0; + + return RT_EOK; +} + +static rt_err_t nu_close_pipe(upipe_t pipe) +{ + int i; + S_NU_RH_PORT_CTRL *psPortCtrl; + S_NU_PORT_DEV *psPortDev; + + psPortCtrl = GetRHPortControlFromPipe(pipe); + if (psPortCtrl == RT_NULL) + { + return RT_EIO; + } + + psPortDev = GetPortDevFromPipe(pipe); + + //For ep0 control transfer + if ((pipe->ep.bEndpointAddress & 0x7F) == 0) + { + if ((psPortDev) && (psPortDev->bRHParent == FALSE) && (psPortDev->bEnumDone == TRUE)) + { + if (psPortDev->pUDev) + { + for (i = 0; i < NU_MAX_USBH_PIPE; i++) + { + if (psPortDev->apsEPInfo[i] != NULL) + { + usbh_quit_xfer(psPortDev->pUDev, psPortDev->apsEPInfo[i]); + } + } + + free_device(psPortDev->pUDev); + psPortDev->pUDev = NULL; + } + psPortDev->port_num = 0; + } + } + + if (psPortDev != NULL) + { + FreePipe(psPortCtrl, psPortDev, pipe->pipe_index); + } + return RT_EOK; +} + +static int nu_ctrl_xfer( + S_NU_PORT_DEV *psPortDev, + struct urequest *psSetup, + void *buffer, + int timeouts +) +{ + uint32_t xfer_len; + int ret; + + ret = usbh_ctrl_xfer(psPortDev->pUDev, psSetup->request_type, psSetup->bRequest, psSetup->wValue, psSetup->wIndex, psSetup->wLength, buffer, &xfer_len, timeouts * 10); + + if (ret < 0) + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_ctrl_xfer ERROR: xfer failed %d\n", ret)); + return ret; + } + + if (xfer_len != psSetup->wLength) + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_ctrl_xfer ERROR: xfer length %d %d\n", psSetup->wLength, xfer_len)); + } + + if ((psSetup->bRequest == USB_REQ_SET_ADDRESS) && ((psSetup->request_type & 0x60) == REQ_TYPE_STD_DEV)) + psPortDev->pUDev->dev_num = psSetup->wValue; + + if ((psSetup->bRequest == USB_REQ_SET_CONFIGURATION) && ((psSetup->request_type & 0x60) == REQ_TYPE_STD_DEV)) + { + psPortDev->pUDev->cur_conf = psSetup->wValue; + psPortDev->bEnumDone = TRUE; + } + + return xfer_len; +} + +static int nu_bulk_xfer( + S_NU_PORT_DEV *psPortDev, + UTR_T *psUTR, + int timeouts +) +{ + int ret; + + ret = usbh_bulk_xfer(psUTR); + + if (ret < 0) + return ret; + + //wait transfer done + rt_completion_wait(&(psPortDev->utr_completion), timeouts); + return 0; +} + +static int nu_int_xfer( + upipe_t pipe, + S_NU_PORT_DEV *psPortDev, + UTR_T *psUTR, + int timeouts +) +{ + int ret; + int retry = 3; + + while (retry > 0) + { + ret = usbh_int_xfer(psUTR); + if (ret == 0) + break; + + RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_int_xfer ERROR: failed to submit interrupt request\n")); + rt_thread_delay((pipe->ep.bInterval * RT_TICK_PER_SECOND / 1000) > 0 ? (pipe->ep.bInterval * RT_TICK_PER_SECOND / 1000) : 1); + retry --; + } + + if (ret < 0) + return ret; + + return 0; +} + +static void xfer_done_cb(UTR_T *psUTR) +{ + S_NU_PORT_DEV *psPortDev = (S_NU_PORT_DEV *)psUTR->context; + + //transfer done, signal utr_completion + rt_completion_done(&(psPortDev->utr_completion)); +} + +static void int_xfer_done_cb(UTR_T *psUTR) +{ + upipe_t pipe = (upipe_t)psUTR->context; + + if (psUTR->status != 0) + { + rt_kprintf("Interrupt xfer failed %d\n", psUTR->status); + free_utr(psUTR); + return; + } + + if (pipe->callback != RT_NULL) + { + struct uhost_msg msg; + msg.type = USB_MSG_CALLBACK; + msg.content.cb.function = pipe->callback; + msg.content.cb.context = pipe; + rt_usbh_event_signal(&msg); + } + + free_utr(psUTR); +} + + +static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes, int timeouts) +{ + S_NU_RH_PORT_CTRL *psPortCtrl; + S_NU_PORT_DEV *psPortDev; + + psPortCtrl = GetRHPortControlFromPipe(pipe); + if (psPortCtrl == RT_NULL) + { + return RT_EIO; + } + + psPortDev = GetPortDevFromPipe(pipe); + + if (psPortDev->pUDev == NULL) + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_pipe_xfer ERROR: udev not found\n")); + return -RT_ERROR; + } + + //ctrl xfer + if (pipe->ep.bmAttributes == USB_EP_ATTR_CONTROL) + { + if (token == USBH_PID_SETUP) + { + struct urequest *psSetup; + psSetup = (struct urequest *)buffer; + + if (psSetup->request_type & USB_REQ_TYPE_DIR_IN) + { + //Store setup request + rt_memcpy(&psPortCtrl->asHubPortDev->asSetupReq[pipe->pipe_index], psSetup, sizeof(struct urequest)); + } + else + { + //Trigger USBHostLib Ctril_Xfer + nu_ctrl_xfer(psPortDev, psSetup, NULL, timeouts); + } + return nbytes; + } + else + { + //token == USBH_PID_DATA + if (buffer == RT_NULL) + return nbytes; + + if ((pipe->ep.bEndpointAddress & USB_DIR_MASK) == USB_DIR_IN) + { + //Trigger USBHostLib Ctril_Xfer + nu_ctrl_xfer(psPortDev, &psPortCtrl->asHubPortDev->asSetupReq[pipe->pipe_index], buffer, timeouts); + } + else + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_pipe_xfer ERROR: can not handle ctrl xfer case: buffer!=NULL and USB_DIR_OUT\n")); + } + return nbytes; + } + } + + + //others xfer + rt_completion_init(&(psPortDev->utr_completion)); + + //setup UTR + UTR_T *psUTR; + int i32XferLen; + + psUTR = alloc_utr(psPortDev->pUDev); + if (!psUTR) + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_pipe_xfer ERROR: unable alloc UTR\n")); + return -(RT_ERROR); + } + + psUTR->ep = psPortDev->apsEPInfo[pipe->pipe_index]; + psUTR->buff = buffer; + psUTR->data_len = nbytes; + psUTR->xfer_len = 0; + psUTR->func = xfer_done_cb; + psUTR->context = psPortDev; + psUTR->bIsTransferDone = 0; + psUTR->status = 0; + + if (pipe->ep.bmAttributes == USB_EP_ATTR_BULK) + { + if (nu_bulk_xfer(psPortDev, psUTR, timeouts) < 0) + { + free_utr(psUTR); + RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_pipe_xfer ERROR: bulk transfer failed\n")); + return -(RT_ERROR); + } + } + + if (pipe->ep.bmAttributes == USB_EP_ATTR_INT) + { + psUTR->func = int_xfer_done_cb; + psUTR->context = pipe; + + if (nu_int_xfer(pipe, psPortDev, psUTR, timeouts) < 0) + { + free_utr(psUTR); + RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_pipe_xfer ERROR: int transfer failed\n")); + return -(RT_ERROR); + } + + return nbytes; + } + + //TODO: ISO transfer + if (pipe->ep.bmAttributes == USB_EP_ATTR_ISOC) + { + free_utr(psUTR); + RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_pipe_xfer ERROR: isoc transfer not support\n")); + return -1; + } + + if (psUTR->bIsTransferDone == 0) + { + //Timeout + RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_pipe_xfer ERROR: timeout\n")); + pipe->status = UPIPE_STATUS_ERROR; + usbh_quit_utr(psUTR); + } + else + { + // Transfer Done. Get status + if (psUTR->status == 0) + { + pipe->status = UPIPE_STATUS_OK; + } + else if (psUTR->status == USBH_ERR_STALL) + { + pipe->status = UPIPE_STATUS_STALL; + } + else + { + pipe->status = UPIPE_STATUS_ERROR; + } + } + + i32XferLen = psUTR->xfer_len; + free_utr(psUTR); + + //Call callback + if (pipe->callback != RT_NULL) + { + struct uhost_msg msg; + msg.type = USB_MSG_CALLBACK; + msg.content.cb.function = pipe->callback; + msg.content.cb.context = pipe->user_data; + rt_usbh_event_signal(&msg); + } + + if (pipe->status != UPIPE_STATUS_OK) + return -(RT_ERROR); + + if ((pipe->ep.bEndpointAddress & USB_DIR_MASK) == USB_DIR_IN) + { + return i32XferLen; + } + else if ((pipe->ep.bEndpointAddress & USB_DIR_MASK) == USB_DIR_OUT) + { + return i32XferLen; + } + + return nbytes; +} + +//Pooling USB root hub status task +static void nu_usbh_rh_thread_entry(void *parameter) +{ + while (1) + { + usbh_pooling_root_hubs(); + rt_thread_delay(10); + } +} + +static void nu_hcd_connect_callback( + struct udev_t *udev, + int param +) +{ + int i; + int port_index; + S_NU_RH_PORT_CTRL *psPortCtrl; + + for (i = 0; i < NU_MAX_USBH_PORT; i++) + { + psPortCtrl = &s_sUSBHDev.asPortCtrl[i]; + if (psPortCtrl->sRHPortDev.pUDev == NULL) + break; + } + + if (i >= NU_MAX_USBH_PORT) + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("ERROR: port connect slot is full\n")); + return; + } + + port_index = i + 1; + psPortCtrl->sRHPortDev.pUDev = udev; + psPortCtrl->sRHPortDev.bRHParent = TRUE; + RT_DEBUG_LOG(RT_DEBUG_USB, ("usb connected\n")); + if (udev->speed == SPEED_HIGH) + rt_usbh_root_hub_connect_handler(s_sUSBHDev.uhcd, port_index, RT_TRUE); + else + rt_usbh_root_hub_connect_handler(s_sUSBHDev.uhcd, port_index, RT_FALSE); +} + +static void nu_hcd_disconnect_callback( + struct udev_t *udev, + int param +) +{ + int i; + int port_index; + S_NU_RH_PORT_CTRL *psPortCtrl; + + for (i = 0; i < NU_MAX_USBH_PORT; i++) + { + psPortCtrl = &s_sUSBHDev.asPortCtrl[i]; + if (psPortCtrl->sRHPortDev.pUDev == udev) + break; + } + + if (i >= NU_MAX_USBH_PORT) + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("ERROR: udev not found\n")); + return; + } + + for (i = 0; i < NU_MAX_USBH_PIPE; i++) + { + if (psPortCtrl->sRHPortDev.apsEPInfo[i] != NULL) + { + usbh_quit_xfer(psPortCtrl->sRHPortDev.pUDev, psPortCtrl->sRHPortDev.apsEPInfo[i]); + } + } + + port_index = i + 1; + psPortCtrl->sRHPortDev.pUDev = NULL; + + RT_DEBUG_LOG(RT_DEBUG_USB, ("usb disconnnect\n")); + rt_usbh_root_hub_disconnect_handler(s_sUSBHDev.uhcd, port_index); +} + + +/* USB host operations -----------------------------------------------------------*/ +static struct uhcd_ops nu_uhcd_ops = +{ + nu_reset_port, + nu_pipe_xfer, + nu_open_pipe, + nu_close_pipe, +}; + +static rt_err_t nu_hcd_init(rt_device_t device) +{ + rt_thread_t thread; + + usbh_core_init(); + + //install connect/disconnect callback + usbh_install_conn_callback(nu_hcd_connect_callback, nu_hcd_disconnect_callback); + usbh_pooling_root_hubs(); + + //create thread for polling usbh port status + /* create usb hub thread */ + thread = rt_thread_create("usbh_drv", nu_usbh_rh_thread_entry, RT_NULL, + NU_USBH_THREAD_STACK_SIZE, 8, 20); + if (thread != RT_NULL) + { + /* startup usb host thread */ + rt_thread_startup(thread); + } + else + { + return -(RT_EEMPTY); + } + + return RT_EOK; +} + +/* global function for USB host library -----------------------------*/ +uint32_t usbh_get_ticks(void) +{ + return rt_tick_get(); +} + +void usbh_delay_ms(int msec) +{ + rt_thread_mdelay(msec); +} + +uint32_t usbh_tick_from_millisecond(uint32_t msec) +{ + return rt_tick_from_millisecond(msec); +} + + +int nu_usbh_register(void) +{ + rt_err_t res = -RT_ERROR; + +#if !defined(BSP_USING_HSOTG) + SYS_UnlockReg(); + +#if defined(BSP_USING_HSUSBH) + /* Set USB Host role */ + SYS->USBPHY = (SYS->USBPHY & ~SYS_USBPHY_HSUSBROLE_Msk) | (0x1u << SYS_USBPHY_HSUSBROLE_Pos); + SYS->USBPHY |= SYS_USBPHY_HSUSBEN_Msk | SYS_USBPHY_SBO_Msk; + rt_thread_delay(20); + SYS->USBPHY |= SYS_USBPHY_HSUSBACT_Msk; + +#endif + +#if defined(BSP_USING_USBH) + /* Enable USBD and OTG clock */ + CLK_EnableModuleClock(USBD_MODULE); + CLK_EnableModuleClock(OTG_MODULE); + /* Set USB Host role */ + SYS->USBPHY = (SYS->USBPHY & ~SYS_USBPHY_USBROLE_Msk) | (0x1u << SYS_USBPHY_USBROLE_Pos); + SYS->USBPHY |= SYS_USBPHY_USBEN_Msk | SYS_USBPHY_SBO_Msk ; +#endif + + SYS_LockReg(); +#endif + + + rt_memset(&s_sUSBHDev, 0x0, sizeof(struct nu_usbh_dev)); + + uhcd_t uhcd = (uhcd_t)rt_malloc(sizeof(struct uhcd)); + if (uhcd == RT_NULL) + { + rt_kprintf("uhcd malloc failed\r\n"); + return -RT_ERROR; + } + + rt_memset((void *)uhcd, 0, sizeof(struct uhcd)); + + uhcd->parent.type = RT_Device_Class_USBHost; + uhcd->parent.init = nu_hcd_init; + uhcd->parent.user_data = &s_sUSBHDev; + + uhcd->ops = &nu_uhcd_ops; + uhcd->num_ports = NU_MAX_USBH_PORT; + s_sUSBHDev.uhcd = uhcd; + + res = rt_device_register(&uhcd->parent, "usbh", RT_DEVICE_FLAG_DEACTIVATE); + if (res != RT_EOK) + { + rt_kprintf("register usb host failed res = %d\r\n", res); + return -RT_ERROR; + } + + /*initialize the usb host functin */ + res = rt_usb_host_init(); + + return RT_EOK; +} +INIT_DEVICE_EXPORT(nu_usbh_register); + +#endif + + + + + + diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_uspi.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_uspi.c new file mode 100644 index 0000000000000000000000000000000000000000..96fab9857a277bddd8599802024e0a1d61babd84 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_uspi.c @@ -0,0 +1,622 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-3-31 Philo First version +* +******************************************************************************/ +#include + +#if defined(BSP_USING_USPI) +#include +#include +#include + +#include +#include + +#if defined(BSP_USING_USPI_PDMA) + #include +#endif +/* Private define ---------------------------------------------------------------*/ +enum +{ + USPI_START = -1, +#if defined(BSP_USING_USPI0) + USPI0_IDX, +#endif +#if defined(BSP_USING_USPI1) + USPI1_IDX, +#endif + USPI_CNT +}; + +/* Private typedef --------------------------------------------------------------*/ +struct nu_uspi +{ + struct rt_spi_bus dev; + char *name; + USPI_T *uspi_base; + struct rt_spi_configuration configuration; + uint32_t dummy; +#if defined(BSP_USING_USPI_PDMA) + int16_t pdma_perp_tx; + int8_t pdma_chanid_tx; + int16_t pdma_perp_rx; + int8_t pdma_chanid_rx; + rt_sem_t m_psSemBus; +#endif +}; +typedef struct nu_uspi *uspi_t; + +/* Private functions ------------------------------------------------------------*/ +static rt_err_t nu_uspi_bus_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration); +static rt_uint32_t nu_uspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_message *message); +static void nu_uspi_transmission_with_poll(struct nu_uspi *uspi_bus, + uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word); +static int nu_uspi_register_bus(struct nu_uspi *uspi_bus, const char *name); +static void nu_uspi_drain_rxfifo(USPI_T *uspi_base); + +#if defined(BSP_USING_USPI_PDMA) + static void nu_pdma_uspi_rx_cb(void *pvUserData, uint32_t u32EventFilter); + static void nu_pdma_uspi_tx_cb(void *pvUserData, uint32_t u32EventFilter); + static rt_err_t nu_pdma_uspi_rx_config(struct nu_uspi *uspi_bus, uint8_t *pu8Buf, int32_t i32RcvLen, uint8_t bytes_per_word); + static rt_err_t nu_pdma_uspi_tx_config(struct nu_uspi *uspi_bus, const uint8_t *pu8Buf, int32_t i32SndLen, uint8_t bytes_per_word); + static rt_size_t nu_uspi_pdma_transmit(struct nu_uspi *uspi_bus, const uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word); + static rt_err_t nu_hw_uspi_pdma_allocate(struct nu_uspi *uspi_bus); +#endif +/* Public functions -------------------------------------------------------------*/ + + +/* Private variables ------------------------------------------------------------*/ +static struct rt_spi_ops nu_uspi_poll_ops = +{ + .configure = nu_uspi_bus_configure, + .xfer = nu_uspi_bus_xfer, +}; + +static struct nu_uspi nu_uspi_arr [] = +{ +#if defined(BSP_USING_USPI0) + { + .name = "uspi0", + .uspi_base = USPI0, + +#if defined(BSP_USING_USPI_PDMA) +#if defined(BSP_USING_USPI0_PDMA) + .pdma_perp_tx = PDMA_USCI0_TX, + .pdma_perp_rx = PDMA_USCI0_RX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif //BSP_USING_USPI0_PDMA +#endif //BSP_USING_USPI_PDMA + }, +#endif +#if defined(BSP_USING_USPI1) + { + .name = "uspi1", + .uspi_base = USPI1, + +#if defined(BSP_USING_USPI_PDMA) +#if defined(BSP_USING_USPI1_PDMA) + .pdma_perp_tx = PDMA_USCI1_TX, + .pdma_perp_rx = PDMA_USCI1_RX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif //BSP_USING_USPI1_PDMA +#endif //BSP_USING_USPI_PDMA + + }, +#endif + {0} +}; /* uspi nu_uspi */ + +static rt_err_t nu_uspi_bus_configure(struct rt_spi_device *device, + struct rt_spi_configuration *configuration) +{ + struct nu_uspi *uspi_bus; + uint32_t u32SPIMode; + uint32_t u32BusClock; + rt_err_t ret = RT_EOK; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(configuration != RT_NULL); + + uspi_bus = (struct nu_uspi *) device->bus; + + /* Check mode */ + switch (configuration->mode & RT_SPI_MODE_3) + { + case RT_SPI_MODE_0: + u32SPIMode = USPI_MODE_0; + break; + case RT_SPI_MODE_1: + u32SPIMode = USPI_MODE_1; + break; + case RT_SPI_MODE_2: + u32SPIMode = USPI_MODE_2; + break; + case RT_SPI_MODE_3: + u32SPIMode = USPI_MODE_3; + break; + default: + ret = RT_EIO; + goto exit_nu_uspi_bus_configure; + } + + /* Check data width */ + if (!(configuration->data_width == 8 || + configuration->data_width == 16)) + { + ret = RT_EINVAL; + goto exit_nu_uspi_bus_configure; + } + + /* Try to set clock and get actual uspi bus clock */ + u32BusClock = USPI_SetBusClock(uspi_bus->uspi_base, configuration->max_hz); + if (configuration->max_hz > u32BusClock) + { + rt_kprintf("%s clock max frequency is %dHz (!= %dHz)\n", uspi_bus->name, u32BusClock, configuration->max_hz); + configuration->max_hz = u32BusClock; + } + + /* Need to initialize new configuration? */ + if (rt_memcmp(configuration, &uspi_bus->configuration, sizeof(*configuration)) != 0) + { + rt_memcpy(&uspi_bus->configuration, configuration, sizeof(*configuration)); + + USPI_Open(uspi_bus->uspi_base, USPI_MASTER, u32SPIMode, configuration->data_width, u32BusClock); + + if (configuration->mode & RT_SPI_CS_HIGH) + { + /* Set CS pin to LOW */ + USPI_SET_SS_LOW(uspi_bus->uspi_base); + } + else + { + /* Set CS pin to HIGH */ + USPI_SET_SS_HIGH(uspi_bus->uspi_base); + } + + if (configuration->mode & RT_SPI_MSB) + { + /* Set sequence to MSB first */ + SPI_SET_MSB_FIRST(uspi_bus->uspi_base); + } + else + { + /* Set sequence to LSB first */ + SPI_SET_LSB_FIRST(uspi_bus->uspi_base); + } + } + + /* Clear SPI RX FIFO */ + nu_uspi_drain_rxfifo(uspi_bus->uspi_base); + +exit_nu_uspi_bus_configure: + + return -(ret); +} + +#if defined(BSP_USING_USPI_PDMA) +static void nu_pdma_uspi_rx_cb(void *pvUserData, uint32_t u32EventFilter) +{ + struct nu_uspi *uspi_bus; + uspi_bus = (struct nu_uspi *)pvUserData; + + RT_ASSERT(uspi_bus != RT_NULL); + + /* Get base address of uspi register */ + USPI_T *uspi_base = uspi_bus->uspi_base; + + if (u32EventFilter & NU_PDMA_EVENT_TRANSFER_DONE) + { + USPI_DISABLE_RX_PDMA(uspi_base); // Stop DMA TX transfer + } +} +static rt_err_t nu_pdma_uspi_rx_config(struct nu_uspi *uspi_bus, uint8_t *pu8Buf, int32_t i32RcvLen, uint8_t bytes_per_word) +{ + rt_err_t result = RT_EOK; + rt_uint8_t *dst_addr = NULL; + nu_pdma_memctrl_t memctrl = eMemCtl_Undefined; + + /* Get base address of uspi register */ + USPI_T *uspi_base = uspi_bus->uspi_base; + + rt_uint8_t uspi_pdma_rx_chid = uspi_bus->pdma_chanid_rx; + + result = nu_pdma_callback_register(uspi_pdma_rx_chid, + nu_pdma_uspi_rx_cb, + (void *)uspi_bus, + NU_PDMA_EVENT_TRANSFER_DONE); + if (result != RT_EOK) + { + goto exit_nu_pdma_uspi_rx_config; + } + + if (pu8Buf == RT_NULL) + { + memctrl = eMemCtl_SrcFix_DstFix; + dst_addr = (rt_uint8_t *) &uspi_bus->dummy; + } + else + { + memctrl = eMemCtl_SrcFix_DstInc; + dst_addr = pu8Buf; + } + + result = nu_pdma_channel_memctrl_set(uspi_pdma_rx_chid, memctrl); + if (result != RT_EOK) + { + goto exit_nu_pdma_uspi_rx_config; + } + + result = nu_pdma_transfer(uspi_pdma_rx_chid, + bytes_per_word * 8, + (uint32_t)&uspi_base->RXDAT, + (uint32_t)dst_addr, + i32RcvLen / bytes_per_word, + 0); + +exit_nu_pdma_uspi_rx_config: + + return result; +} + +static void nu_pdma_uspi_tx_cb(void *pvUserData, uint32_t u32EventFilter) +{ + struct nu_uspi *uspi_bus; + uspi_bus = (struct nu_uspi *)pvUserData; + + RT_ASSERT(uspi_bus != RT_NULL); + + /* Get base address of uspi register */ + USPI_T *uspi_base = uspi_bus->uspi_base; + + if (u32EventFilter & NU_PDMA_EVENT_TRANSFER_DONE) + { + USPI_DISABLE_TX_PDMA(uspi_base); // Stop DMA TX transfer + } + rt_sem_release(uspi_bus->m_psSemBus); + +} + +static rt_err_t nu_pdma_uspi_tx_config(struct nu_uspi *uspi_bus, const uint8_t *pu8Buf, int32_t i32SndLen, uint8_t bytes_per_word) +{ + rt_err_t result = RT_EOK; + rt_uint8_t *src_addr = NULL; + nu_pdma_memctrl_t memctrl = eMemCtl_Undefined; + + /* Get base address of uspi register */ + USPI_T *uspi_base = uspi_bus->uspi_base; + + rt_uint8_t uspi_pdma_tx_chid = uspi_bus->pdma_chanid_tx; + + result = nu_pdma_callback_register(uspi_pdma_tx_chid, + nu_pdma_uspi_tx_cb, + (void *)uspi_bus, + NU_PDMA_EVENT_TRANSFER_DONE); + if (result != RT_EOK) + { + goto exit_nu_pdma_uspi_tx_config; + } + + if (pu8Buf == RT_NULL) + { + uspi_bus->dummy = 0; + memctrl = eMemCtl_SrcFix_DstFix; + src_addr = (rt_uint8_t *)&uspi_bus->dummy; + } + else + { + memctrl = eMemCtl_SrcInc_DstFix; + src_addr = (rt_uint8_t *)pu8Buf; + } + + result = nu_pdma_channel_memctrl_set(uspi_pdma_tx_chid, memctrl); + if (result != RT_EOK) + { + goto exit_nu_pdma_uspi_tx_config; + } + + result = nu_pdma_transfer(uspi_pdma_tx_chid, + bytes_per_word * 8, + (uint32_t)src_addr, + (uint32_t)&uspi_base->TXDAT, + i32SndLen / bytes_per_word, + 0); + +exit_nu_pdma_uspi_tx_config: + + return result; +} + + +/** + * SPI PDMA transfer + */ +static rt_size_t nu_uspi_pdma_transmit(struct nu_uspi *uspi_bus, const uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word) +{ + rt_err_t result = RT_EOK; + + /* Get base address of uspi register */ + USPI_T *uspi_base = uspi_bus->uspi_base; + + result = nu_pdma_uspi_rx_config(uspi_bus, recv_addr, length, bytes_per_word); + RT_ASSERT(result == RT_EOK); + result = nu_pdma_uspi_tx_config(uspi_bus, send_addr, length, bytes_per_word); + RT_ASSERT(result == RT_EOK); + + /* Trigger TX/RX at the same time. */ + USPI_TRIGGER_TX_PDMA(uspi_base); + USPI_TRIGGER_RX_PDMA(uspi_base); + + /* Wait PDMA transfer done */ + rt_sem_take(uspi_bus->m_psSemBus, RT_WAITING_FOREVER); + + while (USPI_IS_BUSY(uspi_base)); + + return result; +} + +static rt_err_t nu_hw_uspi_pdma_allocate(struct nu_uspi *uspi_bus) +{ + /* Allocate USPI_TX nu_dma channel */ + if ((uspi_bus->pdma_chanid_tx = nu_pdma_channel_allocate(uspi_bus->pdma_perp_tx)) < 0) + { + goto exit_nu_hw_uspi_pdma_allocate; + } + /* Allocate USPI_RX nu_dma channel */ + else if ((uspi_bus->pdma_chanid_rx = nu_pdma_channel_allocate(uspi_bus->pdma_perp_rx)) < 0) + { + nu_pdma_channel_free(uspi_bus->pdma_chanid_tx); + goto exit_nu_hw_uspi_pdma_allocate; + } + + uspi_bus->m_psSemBus = rt_sem_create("uspibus_sem", 0, RT_IPC_FLAG_FIFO); + + return RT_EOK; + +exit_nu_hw_uspi_pdma_allocate: + + return -(RT_ERROR); +} + +#endif + +static void nu_uspi_drain_rxfifo(USPI_T *uspi_base) +{ + while (USPI_IS_BUSY(uspi_base)); + + // Drain USPI RX FIFO, make sure RX FIFO is empty + while (!USPI_GET_RX_EMPTY_FLAG(uspi_base)) + { + USPI_ClearRxBuf(uspi_base); + } +} + +static int nu_uspi_read(USPI_T *uspi_base, uint8_t *recv_addr, uint8_t bytes_per_word) +{ + int size = 0; + uint32_t val; + + // Read RX data + if (!USPI_GET_RX_EMPTY_FLAG(uspi_base)) + { + // Read data from USPI RX FIFO + switch (bytes_per_word) + { + case 2: + val = USPI_READ_RX(uspi_base); + nu_set16_le(recv_addr, val); + break; + case 1: + *recv_addr = USPI_READ_RX(uspi_base); + break; + } + size = bytes_per_word; + } + return size; +} + +static int nu_uspi_write(USPI_T *uspi_base, const uint8_t *send_addr, uint8_t bytes_per_word) +{ + // Wait USPI TX send data + while (USPI_GET_TX_FULL_FLAG(uspi_base)); + + // Input data to SPI TX + switch (bytes_per_word) + { + case 2: + USPI_WRITE_TX(uspi_base, nu_get16_le(send_addr)); + break; + case 1: + USPI_WRITE_TX(uspi_base, *((uint8_t *)send_addr)); + break; + } + + return bytes_per_word; +} + +/** + * @brief SPI bus polling + * @param dev : The pointer of the specified SPI module. + * @param send_addr : Source address + * @param recv_addr : Destination address + * @param length : Data length + */ +static void nu_uspi_transmission_with_poll(struct nu_uspi *uspi_bus, + uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word) +{ + USPI_T *uspi_base = uspi_bus->uspi_base; + + // Write-only + if ((send_addr != RT_NULL) && (recv_addr == RT_NULL)) + { + while (length > 0) + { + send_addr += nu_uspi_write(uspi_base, send_addr, bytes_per_word); + length -= bytes_per_word; + } + } // if (send_addr != RT_NULL && recv_addr == RT_NULL) + // Read-only + else if ((send_addr == RT_NULL) && (recv_addr != RT_NULL)) + { + uspi_bus->dummy = 0; + while (length > 0) + { + /* Input data to SPI TX FIFO */ + length -= nu_uspi_write(uspi_base, (const uint8_t *)&uspi_bus->dummy, bytes_per_word); + + /* Read data from RX FIFO */ + recv_addr += nu_uspi_read(uspi_base, recv_addr, bytes_per_word); + } + } // else if (send_addr == RT_NULL && recv_addr != RT_NULL) + // Read&Write + else + { + while (length > 0) + { + /* Input data to SPI TX FIFO */ + send_addr += nu_uspi_write(uspi_base, send_addr, bytes_per_word); + length -= bytes_per_word; + + /* Read data from RX FIFO */ + recv_addr += nu_uspi_read(uspi_base, recv_addr, bytes_per_word); + } + } // else + + /* Wait RX or drian RX-FIFO */ + if (recv_addr) + { + // Wait SPI transmission done + while (USPI_IS_BUSY(uspi_base)) + { + while (!USPI_GET_RX_EMPTY_FLAG(uspi_base)) + { + recv_addr += nu_uspi_read(uspi_base, recv_addr, bytes_per_word); + } + } + + while (!USPI_GET_RX_EMPTY_FLAG(uspi_base)) + { + recv_addr += nu_uspi_read(uspi_base, recv_addr, bytes_per_word); + } + } + else + { + /* Clear SPI RX FIFO */ + nu_uspi_drain_rxfifo(uspi_base); + } +} + +static void nu_uspi_transfer(struct nu_uspi *uspi_bus, uint8_t *tx, uint8_t *rx, int length, uint8_t bytes_per_word) +{ +#if defined(BSP_USING_USPI_PDMA) + /* DMA transfer constrains */ + if ((uspi_bus->pdma_chanid_rx >= 0) && + (!(uint32_t)tx % bytes_per_word) && + (!(uint32_t)rx % bytes_per_word) && + (bytes_per_word != 3)) + nu_uspi_pdma_transmit(uspi_bus, tx, rx, length, bytes_per_word); + else + nu_uspi_transmission_with_poll(uspi_bus, tx, rx, length, bytes_per_word); +#else + nu_uspi_transmission_with_poll(uspi_bus, tx, rx, length, bytes_per_word); +#endif +} + +static rt_uint32_t nu_uspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ + struct nu_uspi *uspi_bus; + struct rt_spi_configuration *configuration; + uint8_t bytes_per_word; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(device->bus != RT_NULL); + RT_ASSERT(message != RT_NULL); + + uspi_bus = (struct nu_uspi *) device->bus; + configuration = &uspi_bus->configuration; + bytes_per_word = configuration->data_width / 8; + + if ((message->length % bytes_per_word) != 0) + { + /* Say bye. */ + rt_kprintf("%s: error payload length(%d%%%d != 0).\n", uspi_bus->name, message->length, bytes_per_word); + return 0; + } + + if (message->length > 0) + { + if (message->cs_take && !(configuration->mode & RT_SPI_NO_CS)) + { + if (configuration->mode & RT_SPI_CS_HIGH) + { + USPI_SET_SS_HIGH(uspi_bus->uspi_base); + } + else + { + USPI_SET_SS_LOW(uspi_bus->uspi_base); + } + } + + nu_uspi_transfer(uspi_bus, (uint8_t *)message->send_buf, (uint8_t *)message->recv_buf, message->length, bytes_per_word); + + if (message->cs_release && !(configuration->mode & RT_SPI_NO_CS)) + { + if (configuration->mode & RT_SPI_CS_HIGH) + { + USPI_SET_SS_LOW(uspi_bus->uspi_base); + } + else + { + USPI_SET_SS_HIGH(uspi_bus->uspi_base); + } + } + + } + + return message->length; +} + +static int nu_uspi_register_bus(struct nu_uspi *uspi_bus, const char *name) +{ + return rt_spi_bus_register(&uspi_bus->dev, name, &nu_uspi_poll_ops); +} + +/** + * Hardware USPI Initial + */ +static int rt_hw_uspi_init(void) +{ + int i; + + for (i = (USPI_START + 1); i < USPI_CNT; i++) + { + nu_uspi_register_bus(&nu_uspi_arr[i], nu_uspi_arr[i].name); +#if defined(BSP_USING_USPI_PDMA) + nu_uspi_arr[i].pdma_chanid_tx = -1; + nu_uspi_arr[i].pdma_chanid_rx = -1; + if ((nu_uspi_arr[i].pdma_perp_tx != NU_PDMA_UNUSED) && (nu_uspi_arr[i].pdma_perp_rx != NU_PDMA_UNUSED)) + { + if (nu_hw_uspi_pdma_allocate(&nu_uspi_arr[i]) != RT_EOK) + { + rt_kprintf("Failed to allocate DMA channels for %s. We will use poll-mode for this bus.\n", nu_uspi_arr[i].name); + } + } +#endif + } + + return 0; +} + +INIT_DEVICE_EXPORT(rt_hw_uspi_init); + +#endif //#if defined(BSP_USING_USPI) diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_uuart.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_uuart.c new file mode 100644 index 0000000000000000000000000000000000000000..0ced7ea397cfefa93ac5ed79ef69a85fac90b815 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_uuart.c @@ -0,0 +1,607 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-2-7 ChingI First version +* +******************************************************************************/ + +#include + +#if defined(BSP_USING_UUART) + +#include +#include +#include + +#if defined(RT_SERIAL_USING_DMA) + #include +#endif + +/* Private define ---------------------------------------------------------------*/ +enum +{ + UUART_START = -1, +#if defined(BSP_USING_UUART0) + UUART0_IDX, +#endif +#if defined(BSP_USING_UUART1) + UUART1_IDX, +#endif + UUART_CNT +}; + +/* Private typedef --------------------------------------------------------------*/ +struct nu_uuart +{ + rt_serial_t dev; + char *name; + UUART_T *uuart_base; + uint32_t uuart_rst; + IRQn_Type uuart_irq_n; +#if defined(RT_SERIAL_USING_DMA) + uint32_t dma_flag; + int16_t pdma_perp_tx; + int8_t pdma_chanid_tx; + + int16_t pdma_perp_rx; + int8_t pdma_chanid_rx; + int32_t rx_write_offset; + int32_t rxdma_trigger_len; +#endif +}; +typedef struct nu_uuart *nu_uuart_t; + +/* Private functions ------------------------------------------------------------*/ +static rt_err_t nu_uuart_configure(struct rt_serial_device *serial, struct serial_configure *cfg); +static rt_err_t nu_uuart_control(struct rt_serial_device *serial, int cmd, void *arg); +static int nu_uuart_send(struct rt_serial_device *serial, char c); +static int nu_uuart_receive(struct rt_serial_device *serial); +static void nu_uuart_isr(nu_uuart_t serial); + +#if defined(RT_SERIAL_USING_DMA) + static rt_size_t nu_uuart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction); + static void nu_pdma_uuart_rx_cb(void *pvOwner, uint32_t u32Events); + static void nu_pdma_uuart_tx_cb(void *pvOwner, uint32_t u32Events); +#endif + +/* Public functions ------------------------------------------------------------*/ + +/* Private variables ------------------------------------------------------------*/ + +static const struct rt_uart_ops nu_uuart_ops = +{ + .configure = nu_uuart_configure, + .control = nu_uuart_control, + .putc = nu_uuart_send, + .getc = nu_uuart_receive, +#if defined(RT_SERIAL_USING_DMA) + .dma_transmit = nu_uuart_dma_transmit +#else + .dma_transmit = RT_NULL +#endif +}; + +static const struct serial_configure nu_uuart_default_config = + RT_SERIAL_CONFIG_DEFAULT; + + +static struct nu_uuart nu_uuart_arr [] = +{ +#if defined(BSP_USING_UUART0) + { + .name = "uuart0", + .uuart_base = UUART0, + .uuart_rst = USCI0_RST, + .uuart_irq_n = USCI0_IRQn, +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_USING_UUART0_TX_DMA) + .pdma_perp_tx = PDMA_USCI0_TX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, +#endif +#if defined(BSP_USING_UUART0_RX_DMA) + .pdma_perp_rx = PDMA_USCI0_RX, + .rx_write_offset = 0, +#else + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + }, +#endif + +#if defined(BSP_USING_UUART1) + { + .name = "uuart1", + .uuart_base = UUART1, + .uuart_rst = USCI1_RST, + .uuart_irq_n = USCI1_IRQn, +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_USING_UUART1_TX_DMA) + .pdma_perp_tx = PDMA_USCI1_TX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, +#endif +#if defined(BSP_USING_UUART1_RX_DMA) + .pdma_perp_rx = PDMA_USCI1_RX, + .rx_write_offset = 0, +#else + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + }, +#endif + + {0} +}; /* uuart nu_uuart */ + +/* Interrupt Handle Funtion ----------------------------------------------------*/ +#if defined(BSP_USING_UUART0) +/* USCI0 interrupt entry */ +void USCI0_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + nu_uuart_isr(&nu_uuart_arr[UUART0_IDX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(BSP_USING_UUART1) +/* USCI1 interrupt entry */ +void USCI1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + nu_uuart_isr(&nu_uuart_arr[UUART1_IDX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + + +/** + * All UUART interrupt service routine + */ +static void nu_uuart_isr(nu_uuart_t serial) +{ + /* Get base address of uuart register */ + UUART_T *uuart_base = ((nu_uuart_t)serial)->uuart_base; + + /* Get interrupt event */ + uint32_t u32IntSts = uuart_base->PROTSTS; + uint32_t u32FIFOSts = uuart_base->BUFSTS; + + if (u32IntSts & (UUART_PROTSTS_PARITYERR_Msk | UUART_PROTSTS_FRMERR_Msk | UUART_PROTSTS_BREAK_Msk)) + { + uuart_base->PROTSTS |= (UUART_PROTSTS_PARITYERR_Msk | UUART_PROTSTS_FRMERR_Msk | UUART_PROTSTS_BREAK_Msk); + return; + } + + /* Handle RX event */ + if (u32IntSts & UUART_PROTSTS_RXENDIF_Msk) + { + rt_hw_serial_isr(&serial->dev, RT_SERIAL_EVENT_RX_IND); + } + uuart_base->PROTSTS = u32IntSts; + uuart_base->BUFSTS = u32FIFOSts; +} + +/** + * Configurae uuart port + */ +static rt_err_t nu_uuart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + rt_err_t ret = RT_EOK; + uint32_t uuart_word_len = 0; + uint32_t uuart_stop_bit = 0; + uint32_t uuart_parity = 0; + + /* Get base address of uuart register */ + UUART_T *uuart_base = ((nu_uuart_t)serial)->uuart_base; + + + /* Check baudrate */ + RT_ASSERT(cfg->baud_rate != 0); + + + + /* Check word len */ + switch (cfg->data_bits) + { + case DATA_BITS_5: + rt_kprintf("Unsupported data length"); + goto exit_nu_uuart_configure; + + case DATA_BITS_6: + uuart_word_len = UUART_WORD_LEN_6; + break; + + case DATA_BITS_7: + uuart_word_len = UUART_WORD_LEN_7; + break; + + case DATA_BITS_8: + uuart_word_len = UUART_WORD_LEN_8; + break; + + default: + rt_kprintf("Unsupported data length"); + ret = RT_EINVAL; + goto exit_nu_uuart_configure; + } + + /* Check stop bit */ + switch (cfg->stop_bits) + { + case STOP_BITS_1: + uuart_stop_bit = UUART_STOP_BIT_1; + break; + + case STOP_BITS_2: + uuart_stop_bit = UUART_STOP_BIT_2; + break; + + default: + rt_kprintf("Unsupported stop bit"); + ret = RT_EINVAL; + goto exit_nu_uuart_configure; + } + + /* Check parity */ + switch (cfg->parity) + { + case PARITY_NONE: + uuart_parity = UUART_PARITY_NONE; + break; + + case PARITY_ODD: + uuart_parity = UUART_PARITY_ODD; + break; + + case PARITY_EVEN: + uuart_parity = UUART_PARITY_EVEN; + break; + + default: + rt_kprintf("Unsupported parity"); + ret = RT_EINVAL; + goto exit_nu_uuart_configure; + } + /* Reset this module */ + SYS_ResetModule(((nu_uuart_t)serial)->uuart_rst); + + + /* Open UUart and set UUART Baudrate */ + UUART_Open(uuart_base, cfg->baud_rate); + + /* Set line configuration. */ + UUART_SetLine_Config(uuart_base, 0, uuart_word_len, uuart_parity, uuart_stop_bit); + + /* Enable NVIC interrupt. */ + NVIC_EnableIRQ(((nu_uuart_t)serial)->uuart_irq_n); + +exit_nu_uuart_configure: + + if (ret != RT_EOK) + UUART_Close(uuart_base); + + return -(ret); +} + +#if defined(RT_SERIAL_USING_DMA) +static rt_err_t nu_pdma_uuart_rx_config(struct rt_serial_device *serial, uint8_t *pu8Buf, int32_t i32TriggerLen) +{ + rt_err_t result = RT_EOK; + + /* Get base address of uuart register */ + UUART_T *uuart_base = ((nu_uuart_t)serial)->uuart_base; + + result = nu_pdma_callback_register(((nu_uuart_t)serial)->pdma_chanid_rx, + nu_pdma_uuart_rx_cb, + (void *)serial, + NU_PDMA_EVENT_TRANSFER_DONE | NU_PDMA_EVENT_TIMEOUT); + + result = nu_pdma_transfer(((nu_uuart_t)serial)->pdma_chanid_rx, + 8, + (uint32_t)&uuart_base->RXDAT, + (uint32_t)pu8Buf, + i32TriggerLen, + 1000); //Idle-timeout, 1ms + + + + //UUART PDMA reset + UUART_PDMA_ENABLE(uuart_base, UUART_PDMACTL_PDMARST_Msk); + + /* Enable Receive Line interrupt & Start DMA RX transfer. */ + UUART_EnableInt(uuart_base, UUART_RLS_INT_MASK); + UUART_PDMA_ENABLE(uuart_base, UUART_PDMACTL_RXPDMAEN_Msk | UUART_PDMACTL_PDMAEN_Msk); + + + return result; +} + +static void nu_pdma_uuart_rx_cb(void *pvOwner, uint32_t u32Events) +{ + rt_size_t recv_len = 0; + rt_size_t transferred_rxbyte = 0; + struct rt_serial_device *serial = (struct rt_serial_device *)pvOwner; + nu_uuart_t puuart = (nu_uuart_t)serial; + RT_ASSERT(serial != RT_NULL); + + /* Get base address of uuart register */ + UUART_T *uuart_base = puuart->uuart_base; + + transferred_rxbyte = nu_pdma_transferred_byte_get(puuart->pdma_chanid_rx, puuart->rxdma_trigger_len); + + if (u32Events & (NU_PDMA_EVENT_TRANSFER_DONE | NU_PDMA_EVENT_TIMEOUT)) + { + if (u32Events & NU_PDMA_EVENT_TRANSFER_DONE) + { + if (serial->config.bufsz != 0) + { + struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; + + nu_pdma_uuart_rx_config(serial, &rx_fifo->buffer[0], puuart->rxdma_trigger_len); // Config & trigger next + } + + transferred_rxbyte = puuart->rxdma_trigger_len; + } + else if ((u32Events & NU_PDMA_EVENT_TIMEOUT) && !UUART_GET_RX_EMPTY(uuart_base)) + { + return; + } + + recv_len = transferred_rxbyte - puuart->rx_write_offset; + + puuart->rx_write_offset = transferred_rxbyte % puuart->rxdma_trigger_len; + + } + + if ((serial->config.bufsz == 0) && (u32Events & NU_PDMA_EVENT_TRANSFER_DONE)) + { + recv_len = puuart->rxdma_trigger_len; + } + + if (recv_len) + { + rt_hw_serial_isr(&puuart->dev, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); + } +} + +static rt_err_t nu_pdma_uuart_tx_config(struct rt_serial_device *serial) +{ + rt_err_t result = RT_EOK; + RT_ASSERT(serial != RT_NULL); + + result = nu_pdma_callback_register(((nu_uuart_t)serial)->pdma_chanid_tx, + nu_pdma_uuart_tx_cb, + (void *)serial, + NU_PDMA_EVENT_TRANSFER_DONE); + + return result; +} + +static void nu_pdma_uuart_tx_cb(void *pvOwner, uint32_t u32Events) +{ + nu_uuart_t puuart = (nu_uuart_t)pvOwner; + + RT_ASSERT(puuart != RT_NULL); + + // Stop DMA TX transfer + UUART_PDMA_DISABLE(puuart->uuart_base, UUART_PDMACTL_TXPDMAEN_Msk); + + if (u32Events & NU_PDMA_EVENT_TRANSFER_DONE) + { + rt_hw_serial_isr(&puuart->dev, RT_SERIAL_EVENT_TX_DMADONE); + } +} + +/** + * UUart DMA transfer + */ +static rt_size_t nu_uuart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction) +{ + rt_err_t result = RT_EOK; + + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(buf != RT_NULL); + + /* Get base address of uuart register */ + UUART_T *uuart_base = ((nu_uuart_t)serial)->uuart_base; + if (direction == RT_SERIAL_DMA_TX) + { + result = nu_pdma_transfer(((nu_uuart_t)serial)->pdma_chanid_tx, + 8, + (uint32_t)buf, + (uint32_t)&uuart_base->TXDAT, + size, + 0); // wait-forever + // Start DMA TX transfer + UUART_PDMA_ENABLE(uuart_base, UUART_PDMACTL_TXPDMAEN_Msk | UUART_PDMACTL_PDMAEN_Msk); + } + else if (direction == RT_SERIAL_DMA_RX) + { + // If config.bufsz = 0, serial will trigger once. + ((nu_uuart_t)serial)->rxdma_trigger_len = size; + ((nu_uuart_t)serial)->rx_write_offset = 0; + result = nu_pdma_uuart_rx_config(serial, buf, size); + } + else + { + result = RT_ERROR; + } + + return result; +} + +static int nu_hw_uuart_dma_allocate(nu_uuart_t puuart) +{ + RT_ASSERT(puuart != RT_NULL); + + /* Allocate UUART_TX nu_dma channel */ + if (puuart->pdma_perp_tx != NU_PDMA_UNUSED) + { + puuart->pdma_chanid_tx = nu_pdma_channel_allocate(puuart->pdma_perp_tx); + if (puuart->pdma_chanid_tx >= 0) + { + puuart->dma_flag |= RT_DEVICE_FLAG_DMA_TX; + } + } + + /* Allocate UUART_RX nu_dma channel */ + if (puuart->pdma_perp_rx != NU_PDMA_UNUSED) + { + puuart->pdma_chanid_rx = nu_pdma_channel_allocate(puuart->pdma_perp_rx); + if (puuart->pdma_chanid_rx >= 0) + { + puuart->dma_flag |= RT_DEVICE_FLAG_DMA_RX; + } + } + + return RT_EOK; +} +#endif + +/** + * UUart interrupt control + */ +static rt_err_t nu_uuart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + rt_err_t result = RT_EOK; + rt_uint32_t flag; + rt_ubase_t ctrl_arg = (rt_ubase_t)arg; + + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(arg != RT_NULL); + + /* Get base address of uuart register */ + UUART_T *uuart_base = ((nu_uuart_t)serial)->uuart_base; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) /* Disable INT-RX */ + { + flag = UUART_RXEND_INT_MASK; + UUART_DisableInt(uuart_base, flag); + } + else if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) /* Disable DMA-RX */ + { + /* Disable Receive Line interrupt & Stop DMA RX transfer. */ + flag = UUART_RLS_INT_MASK; + nu_pdma_channel_terminate(((nu_uuart_t)serial)->pdma_chanid_rx); + UUART_PDMA_DISABLE(uuart_base, UUART_PDMACTL_RXPDMAEN_Msk); + UUART_DisableInt(uuart_base, flag); + } + break; + + case RT_DEVICE_CTRL_SET_INT: + if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) /* Enable INT-RX */ + { + flag = UUART_RXEND_INT_MASK; + UUART_EnableInt(uuart_base, flag); + } + break; + +#if defined(RT_SERIAL_USING_DMA) + case RT_DEVICE_CTRL_CONFIG: + if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) /* Configure and trigger DMA-RX */ + { + struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; + ((nu_uuart_t)serial)->rxdma_trigger_len = serial->config.bufsz; + ((nu_uuart_t)serial)->rx_write_offset = 0; + result = nu_pdma_uuart_rx_config(serial, &rx_fifo->buffer[0], ((nu_uuart_t)serial)->rxdma_trigger_len); // Config & trigger + } + else if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX) /* Configure DMA-TX */ + { + result = nu_pdma_uuart_tx_config(serial); + } + break; +#endif + + } + return result; +} + +/** + * UUart put char + */ +static int nu_uuart_send(struct rt_serial_device *serial, char c) +{ + RT_ASSERT(serial != RT_NULL); + + /* Get base address of uuart register */ + UUART_T *uuart_base = ((nu_uuart_t)serial)->uuart_base; + + /* Waiting if TX-FIFO is full. */ + while (UUART_IS_TX_FULL(uuart_base)) {}; + + /* Put char into TX-FIFO */ + UUART_WRITE(uuart_base, c); + + return 1; +} + +/** + * UUart get char + */ +static int nu_uuart_receive(struct rt_serial_device *serial) +{ + RT_ASSERT(serial != RT_NULL); + + /* Get base address of uuart register */ + UUART_T *uuart_base = ((nu_uuart_t)serial)->uuart_base; + + /* Return failure if RX-FIFO is empty. */ + if (UUART_GET_RX_EMPTY(uuart_base) != 0) + { + return -1; + } + + /* Get char from RX-FIFO */ + return UUART_READ(uuart_base); +} + +/** + * Hardware UUART Initialization + */ +static int rt_hw_uuart_init(void) +{ + int i; + rt_uint32_t flag; + rt_err_t ret = RT_EOK; + + for (i = (UUART_START + 1); i < UUART_CNT; i++) + { + flag = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX; + + nu_uuart_arr[i].dev.ops = &nu_uuart_ops; + nu_uuart_arr[i].dev.config = nu_uuart_default_config; + +#if defined(RT_SERIAL_USING_DMA) + nu_uuart_arr[i].dma_flag = 0; + nu_hw_uuart_dma_allocate(&nu_uuart_arr[i]); + flag |= nu_uuart_arr[i].dma_flag; +#endif + + ret = rt_hw_serial_register(&nu_uuart_arr[i].dev, nu_uuart_arr[i].name, flag, NULL); + RT_ASSERT(ret == RT_EOK); + } + + return ret; +} + +INIT_DEVICE_EXPORT(rt_hw_uuart_init); + +#endif //#if defined(BSP_USING_UUART) diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_wdt.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_wdt.c new file mode 100644 index 0000000000000000000000000000000000000000..a4160600e68c65a58d6ba6001e69679ced004e89 --- /dev/null +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_wdt.c @@ -0,0 +1,482 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-3-25 klcheng First version +* +******************************************************************************/ + +#include + +#if defined(BSP_USING_WDT) + +#include +#include +#include +#include + +/*-------------------------------------------------------------------------------*/ +/* watchdog timer timeout look up table */ +/*-------------------------------------------------------------------------------*/ +/* clock = LIRC 10Khz. */ +/* */ +/* working hz toutsel exp cycles timeout (s) */ +/* 10000 0 4 16 0.0016 */ +/* 1 6 64 0.0064 */ +/* 2 8 256 0.0256 */ +/* 3 10 1024 0.1024 */ +/* 4 12 4096 0.4096 */ +/* 5 14 16384 1.6384 */ +/* 6 16 65536 6.5536 */ +/* 7 18 262144 26.2144 */ +/*-------------------------------------------------------------------------------*/ +/* clock = LXT 32.76Khz. */ +/* */ +/* working hz toutsel exp cycles timeout (s) */ +/* 32768 0 4 16 0.0005 */ +/* 1 6 64 0.0020 */ +/* 2 8 256 0.0078 */ +/* 3 10 1024 0.0313 */ +/* 4 12 4096 0.1250 */ +/* 5 14 16384 0.5000 */ +/* 6 16 65536 2.0000 */ +/* 7 18 262144 8.0000 */ +/*-------------------------------------------------------------------------------*/ +/* clock = 192Mhz HCLK divide 2048 = 93750 hz. */ +/* */ +/* working hz toutsel exp cycles timeout (s) */ +/* 93750 0 4 16 0.00017 */ +/* 1 6 64 0.00068 */ +/* 2 8 256 0.00273 */ +/* 3 10 1024 0.01092 */ +/* 4 12 4096 0.04369 */ +/* 5 14 16384 0.17476 */ +/* 6 16 65536 0.69905 */ +/* 7 18 262144 2.79620 */ +/*-------------------------------------------------------------------------------*/ + +/* Private define ---------------------------------------------------------------*/ + +/* Pick a suitable wdt timeout interval, it is a trade-off between the + consideration of timeout accuracy and the system performance. The MIN_CYCLES + parameter is a numerical value of the toutsel setting, and it must be set to + a correct one which matches to the literal meaning of MIN_TOUTSEL. */ +#define MIN_TOUTSEL (WDT_TIMEOUT_2POW10) +#define MIN_CYCLES (1024) + + +/* Macros to convert the value bewtween the timeout interval and the soft time iterations. */ +#define ROUND_TO_INTEGER(value) ((int)(((value) * 10 + 5) / 10)) +#define CONV_SEC_TO_IT(hz, secs) ROUND_TO_INTEGER((float)((secs) * (hz)) / (float)MIN_CYCLES) +#define CONV_IT_TO_SEC(hz, iterations) ROUND_TO_INTEGER((float)(iterations * MIN_CYCLES) / (float)hz) + + +/* Private typedef --------------------------------------------------------------*/ +struct soft_time_handle +{ + int clock_hz; + int wanted_sec; + int report_sec; + int left_iterations; + int full_iterations; + rt_bool_t expired; + rt_bool_t feed_dog; +}; + +typedef volatile struct soft_time_handle soft_time_handle_t; + +/* Private functions ------------------------------------------------------------*/ +static rt_err_t wdt_init(rt_watchdog_t *dev); +static rt_err_t wdt_control(rt_watchdog_t *dev, int cmd, void *args); +static uint32_t wdt_get_working_hz(void); +static void soft_time_init(soft_time_handle_t *const soft_time); +static void soft_time_setup(uint32_t wanted_sec, uint32_t hz, soft_time_handle_t *const soft_time); +static void soft_time_feed_dog(soft_time_handle_t *const soft_time); + +#if defined(RT_USING_PM) + static int wdt_pm_suspend(const struct rt_device *device, rt_uint8_t mode); + static void wdt_pm_resume(const struct rt_device *device, rt_uint8_t mode); + static int wdt_pm_frequency_change(const struct rt_device *device, rt_uint8_t mode); + + static void soft_time_freqeucy_change(uint32_t new_hz, soft_time_handle_t *const soft_time); + +#endif + +/* Public functions -------------------------------------------------------------*/ + +/* Private variables ------------------------------------------------------------*/ +static struct soft_time_handle soft_time; +static struct rt_watchdog_device device_wdt; +static struct rt_watchdog_ops ops_wdt = +{ + .init = wdt_init, + .control = wdt_control, +}; + +#if defined(RT_USING_PM) + +static struct rt_device_pm_ops device_pm_ops = +{ + + .suspend = wdt_pm_suspend, + .resume = wdt_pm_resume, + .frequency_change = wdt_pm_frequency_change +}; +#endif + + + + +#if defined(RT_USING_PM) + +/* device pm suspend() entry. */ +static int wdt_pm_suspend(const struct rt_device *device, rt_uint8_t mode) +{ + switch (mode) + { + case PM_SLEEP_MODE_NONE: + case PM_SLEEP_MODE_IDLE: + case PM_SLEEP_MODE_STANDBY: + case PM_SLEEP_MODE_SHUTDOWN: + break; + + case PM_SLEEP_MODE_LIGHT: + case PM_SLEEP_MODE_DEEP: + + SYS_UnlockReg(); + WDT->CTL &= ~WDT_CTL_WDTEN_Msk; + SYS_LockReg(); + break; + + default: + break; + } + + return (int)RT_EOK; +} + + +/* device pm resume() entry. */ +static void wdt_pm_resume(const struct rt_device *device, rt_uint8_t mode) +{ + switch (mode) + { + case PM_SLEEP_MODE_NONE: + case PM_SLEEP_MODE_IDLE: + case PM_SLEEP_MODE_STANDBY: + case PM_SLEEP_MODE_SHUTDOWN: + break; + + case PM_SLEEP_MODE_LIGHT: + case PM_SLEEP_MODE_DEEP: + + SYS_UnlockReg(); + WDT->CTL |= WDT_CTL_WDTEN_Msk; + SYS_LockReg(); + break; + + default: + break; + } +} + + +static uint32_t wdt_get_module_clock(void) +{ + return (CLK_GetModuleClockSource(WDT_MODULE) << CLK_CLKSEL1_WDTSEL_Pos); +} + + +/* device pm frequency_change() entry. */ +static int wdt_pm_frequency_change(const struct rt_device *device, rt_uint8_t mode) +{ + uint32_t clk, new_hz; + + new_hz = wdt_get_working_hz(); + clk = wdt_get_module_clock(); + + if (clk == CLK_CLKSEL1_WDTSEL_HCLK_DIV2048) + { + if (new_hz == soft_time.clock_hz) + return (int)(RT_EOK); + + /* frequency change occurs in critial section */ + soft_time_freqeucy_change(new_hz, &soft_time); + } + + return (int)(RT_EOK); +} + + +static void soft_time_freqeucy_change(uint32_t new_hz, soft_time_handle_t *const soft_time) +{ + rt_base_t level; + soft_time_handle_t new_time; + rt_bool_t corner_case = RT_FALSE; + + level = rt_hw_interrupt_disable(); + + new_time.clock_hz = new_hz; + new_time.feed_dog = soft_time->feed_dog; + new_time.expired = soft_time->expired; + new_time.wanted_sec = soft_time->wanted_sec; + new_time.full_iterations = CONV_SEC_TO_IT(new_hz, soft_time->wanted_sec); + new_time.report_sec = CONV_IT_TO_SEC(new_hz, new_time.full_iterations); + + new_time.left_iterations = ROUND_TO_INTEGER((float)soft_time->left_iterations * + (float)new_hz / (float)soft_time->clock_hz); + + if ((new_time.left_iterations == 0) && (soft_time->left_iterations > 0)) + { + new_time.left_iterations++;; + corner_case = RT_TRUE; + } + + *soft_time = new_time; + rt_hw_interrupt_enable(level); + + if (corner_case) + { + LOG_W("pm frequency change cause wdt intenal left iterations convert to 0.\n\r \ + wdt driver will add another 1 iteration for this corner case."); + } +} +#endif + + +static void hw_wdt_init(void) +{ + SYS_UnlockReg(); + + if (WDT_GET_RESET_FLAG()) + { + LOG_W("System re-boots from watchdog timer reset.\n"); + WDT_CLEAR_RESET_FLAG(); + } + + SYS_LockReg(); + NVIC_EnableIRQ(WDT_IRQn); +} + + +/* wdt device driver initialise. */ +int rt_hw_wdt_init(void) +{ + rt_err_t ret; + + hw_wdt_init(); + + device_wdt.ops = &ops_wdt; + ret = rt_hw_watchdog_register(&device_wdt, "wdt", RT_DEVICE_FLAG_RDWR, RT_NULL); + +#if defined(RT_USING_PM) + + rt_pm_device_register((struct rt_device *)&device_wdt, &device_pm_ops); +#endif + + + return (int)ret; +} +INIT_BOARD_EXPORT(rt_hw_wdt_init); + + +/* Reigster rt-thread device.init() entry. */ +static rt_err_t wdt_init(rt_watchdog_t *dev) +{ + soft_time_init(&soft_time); + hw_wdt_init(); + + return RT_EOK; +} + + +static uint32_t wdt_get_working_hz(void) +{ + uint32_t clk, hz = 0; + + clk = wdt_get_module_clock(); + + switch (clk) + { + case CLK_CLKSEL1_WDTSEL_LIRC: + hz = __LIRC; + break; + + case CLK_CLKSEL1_WDTSEL_LXT: + hz = __LXT; + break; + + case CLK_CLKSEL1_WDTSEL_HCLK_DIV2048: + hz = CLK_GetHCLKFreq() / 2048; + break; + + default: + break; + } + + return hz; +} + + +static void soft_time_init(soft_time_handle_t *const soft_time) +{ + rt_memset((void *)soft_time, 0, sizeof(struct soft_time_handle)); + +} + + +static void soft_time_setup(uint32_t wanted_sec, uint32_t hz, soft_time_handle_t *const soft_time) +{ + rt_base_t level; + + level = rt_hw_interrupt_disable(); + + soft_time->expired = RT_FALSE; + soft_time->feed_dog = RT_FALSE; + soft_time->wanted_sec = wanted_sec; + soft_time->full_iterations = CONV_SEC_TO_IT(hz, wanted_sec); + soft_time->left_iterations = soft_time->full_iterations; + soft_time->report_sec = CONV_IT_TO_SEC(hz, soft_time->full_iterations); + soft_time->clock_hz = hz; + + rt_hw_interrupt_enable(level); +} + + +static void soft_time_feed_dog(soft_time_handle_t *const soft_time) +{ + soft_time->feed_dog = RT_TRUE; +} + + +/* Register rt-thread device.control() entry. */ +static rt_err_t wdt_control(rt_watchdog_t *dev, int cmd, void *args) +{ + uint32_t wanted_sec, hz; + uint32_t *buf; + rt_err_t ret = RT_EOK; + + if (dev == NULL) + return -(RT_EINVAL); + + SYS_UnlockReg(); + + hz = wdt_get_working_hz(); + + switch (cmd) + { + case RT_DEVICE_CTRL_WDT_GET_TIMEOUT: + + if (args == RT_NULL) + { + ret = RT_EINVAL; + break; + } + + buf = (uint32_t *)args; + *buf = soft_time.report_sec; + break; + + case RT_DEVICE_CTRL_WDT_SET_TIMEOUT: + + wanted_sec = *((uint32_t *)args); + + if (wanted_sec == 0) + { + ret = RT_EINVAL; + break; + } + + soft_time_setup(wanted_sec, hz, &soft_time); + break; + + case RT_DEVICE_CTRL_WDT_GET_TIMELEFT: + + if (args == RT_NULL) + { + ret = RT_EINVAL; + break; + } + + buf = (uint32_t *)args; + *buf = CONV_IT_TO_SEC(hz, soft_time.left_iterations); + break; + + case RT_DEVICE_CTRL_WDT_KEEPALIVE: + + /* Make a mark that the application has fed the watchdog. */ + soft_time_feed_dog(&soft_time); + break; + + case RT_DEVICE_CTRL_WDT_START: + + WDT_Open(MIN_TOUTSEL, WDT_RESET_DELAY_1026CLK, TRUE, TRUE); + WDT_EnableInt(); + break; + + case RT_DEVICE_CTRL_WDT_STOP: + + WDT_Close(); + break; + + default: + ret = RT_ERROR; + } + + SYS_LockReg(); + + return -(ret); +} + + +/* wdt interrupt entry */ +void WDT_IRQHandler(void) +{ + rt_interrupt_enter(); + + /* Clear wdt interrupt flag */ + if (WDT_GET_TIMEOUT_INT_FLAG()) + { + WDT_CLEAR_TIMEOUT_INT_FLAG(); + } + + /* Clear wdt wakeup flag */ + if (WDT_GET_TIMEOUT_WAKEUP_FLAG()) + { + WDT_CLEAR_TIMEOUT_WAKEUP_FLAG(); + } + + /* The soft time has not reached the configured timeout yet. Clear the wdt counter + any way to prevent the system from hardware wdt reset. */ + if (soft_time.left_iterations-- > 0) + { + WDT_RESET_COUNTER(); + } + + /* The soft time reaches the configured timeout boundary. Clear the wdt + counter if he application has fed the dog at least once until now. */ + else + { + if ((soft_time.feed_dog) && (!soft_time.expired)) + { + WDT_RESET_COUNTER(); + soft_time.feed_dog = RT_FALSE; + soft_time.left_iterations = soft_time.full_iterations; + } + else + { + /* Application does not feed the dog in time. */ + soft_time.expired = RT_TRUE; + } + } + + rt_interrupt_leave(); +} + +#endif /* BSP_USING_WDT */ + + diff --git a/bsp/nuvoton/libraries/nu_packages/AudioCodec/SConscript b/bsp/nuvoton/libraries/nu_packages/AudioCodec/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..4c026e13ebcf00a5a9a83ada31f90f1ef71833eb --- /dev/null +++ b/bsp/nuvoton/libraries/nu_packages/AudioCodec/SConscript @@ -0,0 +1,14 @@ +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +group = [] +if GetDepend('NU_PKG_USING_NAU88L25'): + src = Split(""" + acodec_nau88l25.c + audio_test.c + """) + CPPPATH = [cwd] + group = DefineGroup('nu_pkgs_nau88l25', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/nuvoton/libraries/nu_packages/AudioCodec/acodec_nau88l25.c b/bsp/nuvoton/libraries/nu_packages/AudioCodec/acodec_nau88l25.c new file mode 100644 index 0000000000000000000000000000000000000000..65b2f4afba7a0a2f862321e659f9ce396842383b --- /dev/null +++ b/bsp/nuvoton/libraries/nu_packages/AudioCodec/acodec_nau88l25.c @@ -0,0 +1,482 @@ +/**************************************************************************//** +* +* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-1-16 Wayne First version +* +******************************************************************************/ + +#include + +#if defined(NU_PKG_USING_NAU88L25) + +#include +#include + +#include "acodec_nau88l25.h" +#include "drv_i2s.h" + +#define DBG_ENABLE +#define DBG_LEVEL DBG_LOG +#define DBG_SECTION_NAME "acodec.nau88l25" +#define DBG_COLOR +#include + +#define DEF_NAU88L25_ADDR 0x1A + +static struct rt_i2c_bus_device *g_I2cBusDev = NULL; +S_NU_NAU88L25_CONFIG *g_psCodecConfig = NULL; + +static rt_err_t nau88l25_init(void); +static rt_err_t nau88l25_reset(void); +static rt_err_t nau88l25_dsp_control(struct rt_audio_configure *config); +static rt_err_t nau88l25_mixer_control(rt_uint32_t ui32Units, rt_uint32_t ui32Value); +static rt_err_t nau88l25_mixer_query(rt_uint32_t ui32Units, rt_uint32_t *ui32Value); + +nu_acodec_ops nu_acodec_ops_nau88l25 = +{ + .name = "NAU88L25", + .role = NU_ACODEC_ROLE_MASTER, + .config = { // Default settings. + .samplerate = 48000, + .channels = 2, + .samplebits = 16 + }, + .nu_acodec_init = nau88l25_init, + .nu_acodec_reset = nau88l25_reset, + + .nu_acodec_dsp_control = nau88l25_dsp_control, + .nu_acodec_mixer_control = nau88l25_mixer_control, + .nu_acodec_mixer_query = nau88l25_mixer_query +}; + +static void nau88l25_delay_ms(rt_uint32_t nms) +{ + rt_thread_mdelay(nms); +} + +static int I2C_WriteNAU88L25(uint16_t u16addr, uint16_t u16data) +{ + struct rt_i2c_msg msg; + char au8TxData[4]; + + RT_ASSERT(g_I2cBusDev != NULL); + + au8TxData[0] = (uint8_t)((u16addr >> 8) & 0x00FF); //addr [15:8] + au8TxData[1] = (uint8_t)(u16addr & 0x00FF); //addr [ 7:0] + au8TxData[2] = (uint8_t)((u16data >> 8) & 0x00FF); //data [15:8] + au8TxData[3] = (uint8_t)(u16data & 0x00FF); //data [ 7:0] + + msg.addr = DEF_NAU88L25_ADDR; /* Slave address */ + msg.flags = RT_I2C_WR; /* Write flag */ + msg.buf = (rt_uint8_t *)&au8TxData[0]; /* Slave register address */ + msg.len = sizeof(au8TxData); /* Number of bytes sent */ + + if (g_I2cBusDev && rt_i2c_transfer(g_I2cBusDev, &msg, 1) != 1) + { + rt_kprintf("[Failed] addr=%x, data=%d\n", u16addr, u16data); + return -RT_ERROR; + } + + return RT_EOK; +} + +static int I2C_ReadNAU88L25(uint16_t u16addr, uint16_t *pu16data) +{ + struct rt_i2c_msg msgs[2]; + uint16_t u16data = 0; + char au8TxData[2]; + + RT_ASSERT(g_I2cBusDev != NULL); + + au8TxData[0] = (uint8_t)((u16addr >> 8) & 0x00FF); //addr [15:8] + au8TxData[1] = (uint8_t)(u16addr & 0x00FF); //addr [ 7:0] + + msgs[0].addr = DEF_NAU88L25_ADDR; /* Slave address */ + msgs[0].flags = RT_I2C_WR; /* Write flag */ + msgs[0].buf = (rt_uint8_t *)&au8TxData; /* Number of bytes sent */ + msgs[0].len = sizeof(au8TxData); /* Number of bytes read */ + + msgs[1].addr = DEF_NAU88L25_ADDR; /* Slave address */ + msgs[1].flags = RT_I2C_RD; /* Read flag */ + msgs[1].buf = (rt_uint8_t *)&u16data; /* Read data pointer */ + msgs[1].len = sizeof(u16data); /* Number of bytes read */ + + if (rt_i2c_transfer(g_I2cBusDev, &msgs[0], 2) != 2) + { + return -RT_ERROR; + } + + return RT_EOK; +} + +static void nau88l25_phonejack_set(S_NU_NAU88L25_CONFIG *psCodecConfig, int bEnable) +{ + rt_pin_mode(psCodecConfig->pin_phonejack_en, PIN_MODE_OUTPUT); + + if (bEnable) + { + rt_pin_write(psCodecConfig->pin_phonejack_en, PIN_LOW); + } + else + { + rt_pin_write(psCodecConfig->pin_phonejack_en, PIN_HIGH); + } +} + +static rt_err_t nau88l25_probe(void) +{ + return RT_EOK; +} + +static rt_err_t nau88l25_reset(void) +{ + I2C_WriteNAU88L25(0, 0x1); + I2C_WriteNAU88L25(0, 0); // Reset all registers + nau88l25_delay_ms(30); + + LOG_I("Software Reset.\n"); + + return RT_EOK; +} + +static rt_err_t nau88l25_dsp_config(rt_uint32_t ui32SamplRate, rt_uint8_t u8ChNum, rt_uint8_t u8SamplBit) +{ + int clkDivider; + int i2sPcmCtrl2; + int lrClkDiv; + char bClkDiv; + char mClkDiv; + + /* Force to set Channel number to 2 */ + u8ChNum = 2; + + I2C_WriteNAU88L25(REG_I2S_PCM_CTRL1, AIFMT0_STANDI2S | ((u8SamplBit <= 24) ? ((u8SamplBit - 16) >> 2) : WLEN0_32BIT)); + u8SamplBit = (u8SamplBit > 16) ? 32 : 16; + + if (ui32SamplRate % 11025) + { + /* 48000 series 12.288Mhz */ + I2C_WriteNAU88L25(REG_FLL2, 0x3126); + I2C_WriteNAU88L25(REG_FLL3, 0x0008); + + mClkDiv = 49152000 / (ui32SamplRate * 256); + } + else + { + /* 44100 series 11.2896Mhz */ + I2C_WriteNAU88L25(REG_FLL2, 0x86C2); + I2C_WriteNAU88L25(REG_FLL3, 0x0007); + + /* FIXME */ + if (ui32SamplRate > 44100) + ui32SamplRate = 11025; + + mClkDiv = 45158400 / (ui32SamplRate * 256); + } + + lrClkDiv = u8ChNum * u8SamplBit; + bClkDiv = 256 / lrClkDiv; + + switch (mClkDiv) + { + case 1: + mClkDiv = 0; + break; + case 2: + mClkDiv = 2; + break; + case 4: + mClkDiv = 3; + break; + case 8: + mClkDiv = 4; + break; + case 16: + mClkDiv = 5; + break; + case 32: + mClkDiv = 6; + break; + case 3: + mClkDiv = 7; + break; + case 6: + mClkDiv = 10; + break; + case 12: + mClkDiv = 11; + break; + case 24: + mClkDiv = 12; + break; + case 48: + mClkDiv = 13; + break; + case 96: + mClkDiv = 14; + break; + case 5: + mClkDiv = 15; + break; + default: + LOG_E("mclk divider not match!\n"); + mClkDiv = 0; + return -RT_ERROR; + } + + clkDivider = CLK_SYSCLK_SRC_VCO | CLK_ADC_SRC_DIV2 | CLK_DAC_SRC_DIV2 | mClkDiv; + I2C_WriteNAU88L25(REG_CLK_DIVIDER, clkDivider); + + switch (bClkDiv) + { + case 2: + bClkDiv = 0; + break; + case 4: + bClkDiv = 1; + break; + case 8: + bClkDiv = 2; + break; + case 16: + bClkDiv = 3; + break; + case 32: + bClkDiv = 4; + break; + case 64: + bClkDiv = 5; + break; + default: + LOG_E("bclk divider not match!\n"); + bClkDiv = 0; + return -RT_ERROR; + } + + switch (lrClkDiv) + { + case 256: + lrClkDiv = 0; + break; + case 128: + lrClkDiv = 1; + break; + case 64: + lrClkDiv = 2; + break; + case 32: + lrClkDiv = 3; + break; + default: + LOG_E("lrclk divider not match!\n"); + lrClkDiv = 0; + return -RT_ERROR; + } + + i2sPcmCtrl2 = ADCDAT0_OE | MS0_MASTER | (lrClkDiv << 12) | bClkDiv; + + I2C_WriteNAU88L25(REG_I2S_PCM_CTRL2, i2sPcmCtrl2); + + return RT_EOK; +} + +static rt_err_t nau88l25_init(void) +{ + I2C_WriteNAU88L25(REG_CLK_DIVIDER, CLK_SYSCLK_SRC_VCO | CLK_ADC_SRC_DIV2 | CLK_DAC_SRC_DIV2 | MCLK_SRC_DIV4); + I2C_WriteNAU88L25(REG_FLL1, FLL_RATIO_512K); + I2C_WriteNAU88L25(REG_FLL2, 0x3126); + I2C_WriteNAU88L25(REG_FLL3, 0x0008); + I2C_WriteNAU88L25(REG_FLL4, 0x0010); + I2C_WriteNAU88L25(REG_FLL5, PDB_DACICTRL | CHB_FILTER_EN); + I2C_WriteNAU88L25(REG_FLL6, SDM_EN | CUTOFF500); + I2C_WriteNAU88L25(REG_FLL_VCO_RSV, 0xF13C); + I2C_WriteNAU88L25(REG_HSD_CTRL, HSD_AUTO_MODE | MANU_ENGND1_GND); + I2C_WriteNAU88L25(REG_SAR_CTRL, RES_SEL_70K_OHMS | COMP_SPEED_1US | SAMPLE_SPEED_4US); + I2C_WriteNAU88L25(REG_I2S_PCM_CTRL1, AIFMT0_STANDI2S); + + if (nu_acodec_ops_nau88l25.role == NU_ACODEC_ROLE_MASTER) + { + I2C_WriteNAU88L25(REG_I2S_PCM_CTRL2, LRC_DIV_DIV32 | ADCDAT0_OE | MS0_MASTER | BLCKDIV_DIV8); //301A:Master 3012:Slave + } + else + { + I2C_WriteNAU88L25(REG_I2S_PCM_CTRL2, LRC_DIV_DIV32 | ADCDAT0_OE | MS0_SLAVE | BLCKDIV_DIV8); + I2C_WriteNAU88L25(REG_LEFT_TIME_SLOT, DIS_FS_SHORT_DET); + } + + I2C_WriteNAU88L25(REG_ADC_RATE, 0x10 | ADC_RATE_128); + I2C_WriteNAU88L25(REG_DAC_CTRL1, 0x80 | DAC_RATE_128); + + I2C_WriteNAU88L25(REG_MUTE_CTRL, 0x0000); // 0x10000 + I2C_WriteNAU88L25(REG_ADC_DGAIN_CTRL, DGAINL_ADC0(0xEF)); + I2C_WriteNAU88L25(REG_DACL_CTRL, DGAINL_DAC(0xAE)); + I2C_WriteNAU88L25(REG_DACR_CTRL, DGAINR_DAC(0xAE) | DAC_CH_SEL1_RIGHT); + + I2C_WriteNAU88L25(REG_CLASSG_CTRL, CLASSG_TIMER_64MS | CLASSG_CMP_EN_R_DAC | CLASSG_CMP_EN_L_DAC | CLASSG_EN); + I2C_WriteNAU88L25(REG_BIAS_ADJ, VMIDEN | VMIDSEL_125K_OHM); + I2C_WriteNAU88L25(REG_TRIM_SETTINGS, DRV_IBCTRHS | DRV_ICUTHS | INTEG_IBCTRHS | INTEG_ICUTHS); + I2C_WriteNAU88L25(REG_ANALOG_CONTROL_2, AB_ADJ | CAP_1 | CAP_0); + I2C_WriteNAU88L25(REG_ANALOG_ADC_1, CHOPRESETN | CHOPF0_DIV4); + I2C_WriteNAU88L25(REG_ANALOG_ADC_2, VREFSEL_VMIDE_P5DB | PDNOTL | LFSRRESETN); + I2C_WriteNAU88L25(REG_RDAC, DAC_EN_L | DAC_EN_R | CLK_DAC_EN_L | CLK_DAC_EN_R | CLK_DAC_DELAY_2NSEC | DACVREFSEL(0x3)); + I2C_WriteNAU88L25(REG_MIC_BIAS, INT2KB | LOWNOISE | POWERUP | MICBIASLVL1_1P1x); + I2C_WriteNAU88L25(REG_BOOST, PDVMDFST | BIASEN | BOOSTGDIS | EN_SHRT_SHTDWN); + I2C_WriteNAU88L25(REG_POWER_UP_CONTROL, PUFEPGA | FEPGA_GAIN(21) | PUP_INTEG_LEFT_HP | PUP_INTEG_RIGHT_HP | PUP_DRV_INSTG_RIGHT_HP | PUP_DRV_INSTG_LEFT_HP | PUP_MAIN_DRV_RIGHT_HP | PUP_MAIN_DRV_LEFT_HP); + I2C_WriteNAU88L25(REG_CHARGE_PUMP_AND_DOWN_CONTROL, JAMNODCLOW | RNIN); + I2C_WriteNAU88L25(REG_ENA_CTRL, RDAC_EN | LDAC_EN | ADC_EN | DCLK_ADC_EN | DCLK_DAC_EN | CLK_I2S_EN | 0x4); + + nu_acodec_ops_nau88l25.config.samplerate = 48000; + nu_acodec_ops_nau88l25.config.channels = 2; + nu_acodec_ops_nau88l25.config.samplebits = 16; + + LOG_I("Initialized done.\n"); + + return RT_EOK; +} + +static rt_err_t nau88l25_dsp_control(struct rt_audio_configure *config) +{ + rt_err_t result = RT_EOK; + + RT_ASSERT(config != RT_NULL); + + if (rt_memcmp((void *)config, (void *)&nu_acodec_ops_nau88l25.config, sizeof(struct rt_audio_configure)) != 0) + { + if ((result = nau88l25_dsp_config(config->samplerate, config->channels, config->samplebits)) == RT_EOK) + rt_memcpy((void *)&nu_acodec_ops_nau88l25.config, (void *)config, sizeof(struct rt_audio_configure)) ; + } + return result; +} + +static rt_err_t nau88l25_mixer_control(rt_uint32_t ui32Units, rt_uint32_t ui32Value) +{ + switch (ui32Units) + { + case AUDIO_MIXER_MUTE: + if (ui32Value) + { + I2C_WriteNAU88L25(REG_MUTE_CTRL, SMUTE_EN); + nau88l25_phonejack_set(g_psCodecConfig, 0); + } + else + { + I2C_WriteNAU88L25(REG_MUTE_CTRL, 0x0000); + nau88l25_phonejack_set(g_psCodecConfig, 1); + } + break; + + case AUDIO_MIXER_VOLUME: + I2C_WriteNAU88L25(REG_DACL_CTRL, DGAINL_DAC(ui32Value * 2)); + I2C_WriteNAU88L25(REG_DACR_CTRL, DGAINR_DAC(ui32Value * 2) | DAC_CH_SEL1_RIGHT); + break; + + case AUDIO_MIXER_QUERY: + case AUDIO_MIXER_BASS: + case AUDIO_MIXER_MID: + case AUDIO_MIXER_TREBLE: + case AUDIO_MIXER_EQUALIZER: + case AUDIO_MIXER_LINE: + case AUDIO_MIXER_DIGITAL: + case AUDIO_MIXER_MIC: + case AUDIO_MIXER_VITURAL: + case AUDIO_MIXER_EXTEND: + default: + return -RT_ERROR; + } + return RT_EOK; +} + +static rt_err_t nau88l25_mixer_query(rt_uint32_t ui32Units, rt_uint32_t *pui32Value) +{ + RT_ASSERT(pui32Value != RT_NULL); + rt_uint16_t u16RV = 0; + + switch (ui32Units) + { + case AUDIO_MIXER_QUERY: + *pui32Value = AUDIO_MIXER_VOLUME | AUDIO_MIXER_MUTE; + break; + + case AUDIO_MIXER_MUTE: + I2C_ReadNAU88L25(REG_MUTE_CTRL, (uint16_t *)&u16RV); + if (u16RV & SMUTE_EN) + *pui32Value = 1; + else + *pui32Value = 0; + break; + + case AUDIO_MIXER_VOLUME: + I2C_ReadNAU88L25(REG_DACL_CTRL, (uint16_t *)&u16RV); + *pui32Value = u16RV / 2; + break; + + case AUDIO_MIXER_BASS: + case AUDIO_MIXER_MID: + case AUDIO_MIXER_TREBLE: + case AUDIO_MIXER_EQUALIZER: + case AUDIO_MIXER_LINE: + case AUDIO_MIXER_DIGITAL: + case AUDIO_MIXER_MIC: + case AUDIO_MIXER_VITURAL: + case AUDIO_MIXER_EXTEND: + default: + return -RT_ERROR; + } + return RT_EOK; +} + +int nu_hw_nau88l25_init(S_NU_NAU88L25_CONFIG *psCodecConfig) +{ + RT_ASSERT(psCodecConfig != RT_NULL); + struct rt_i2c_bus_device *psI2cBusDev; + struct rt_audio_device *psAudioDev; + nu_i2s_t psNuI2s; + + /* Find I2C bus */ + psI2cBusDev = (struct rt_i2c_bus_device *)rt_device_find(psCodecConfig->i2c_bus_name); + if (psI2cBusDev == RT_NULL) + { + LOG_E("Can't found I2C bus - %s..!\n", psCodecConfig->i2c_bus_name); + goto exit_rt_hw_nau88l25_init; + } + + /* Find I2S bus */ + psAudioDev = (struct rt_audio_device *)rt_device_find(psCodecConfig->i2s_bus_name); + if (psAudioDev == RT_NULL) + { + LOG_E("Can't found I2S bus - %s ..!\n", psCodecConfig->i2s_bus_name); + goto exit_rt_hw_nau88l25_init; + } + + if (nau88l25_probe() != RT_EOK) + { + LOG_E("Can't found audio codec..!\n"); + goto exit_rt_hw_nau88l25_init; + } + + /* Store this board setting. */ + g_psCodecConfig = psCodecConfig; + g_I2cBusDev = psI2cBusDev; + + /* Get NuI2S device instance. */ + psNuI2s = (nu_i2s_t)psAudioDev; + + /* Register Acodec Ops */ + psNuI2s->AcodecOps = &nu_acodec_ops_nau88l25; + + /* Use Acodec default settings. */ + rt_memcpy(&psNuI2s->config, &nu_acodec_ops_nau88l25.config, sizeof(struct rt_audio_configure)); + + return RT_EOK; + +exit_rt_hw_nau88l25_init: + + return -RT_ERROR; +} + +#endif //#if defined(NU_PKG_USING_NAU88L25) diff --git a/bsp/nuvoton/libraries/nu_packages/AudioCodec/acodec_nau88l25.h b/bsp/nuvoton/libraries/nu_packages/AudioCodec/acodec_nau88l25.h new file mode 100644 index 0000000000000000000000000000000000000000..6a429925d423b28112b709d2bef14f90c453ce35 --- /dev/null +++ b/bsp/nuvoton/libraries/nu_packages/AudioCodec/acodec_nau88l25.h @@ -0,0 +1,1096 @@ +/**************************************************************************//** +* +* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-1-16 Wayne First version +* +******************************************************************************/ + +#ifndef __ACODEC_NAU88L25_H__ +#define __ACODEC_NAU88L25_H__ + +#include + +enum +{ + REG_SOFTWARE_RST, + REG_ENA_CTRL, + REG_I2C_ADDR_SET, + REG_CLK_DIVIDER, + REG_FLL1, + REG_FLL2, + REG_FLL3, + REG_FLL4, + REG_FLL5, + REG_FLL6, + REG_FLL_VCO_RSV, + REG_HSD_CTRL = 0xC, //0xC + REG_JACK_DET_CTRL, + REG_INTERRUPT_MASK = 0xF, //0xF + REG_IRQ_STATUS, + REG_INT_LCR_KEY_STATUS, + REG_INTERRUPT_DIS_CTRL, + REG_SAR_CTRL, + REG_KEYDET_CTRL, + REG_VDET_THRESHOLD_1, + REG_VDET_THRESHOLD_2, + REG_VDET_THRESHOLD_3, + REG_VDET_THRESHOLD_4, + REG_GPIO34_CTRL, + REG_GPIO12_CTRL, + REG_TDM_CTRL, + REG_I2S_PCM_CTRL1, + REG_I2S_PCM_CTRL2, + REG_LEFT_TIME_SLOT, + REG_RIGHT_TIME_SLOT, + REG_BIQ_CTRL, + REG_BIQ_COF1, + REG_BIQ_COF2, + REG_BIQ_COF3, + REG_BIQ_COF4, + REG_BIQ_COF5, + REG_BIQ_COF6, + REG_BIQ_COF7, + REG_BIQ_COF8, + REG_BIQ_COF9, //29 + REG_BIQ_COF10, + REG_ADC_RATE, + REG_DAC_CTRL1, + REG_DAC_CTRL2, + REG_DAC_DGAIN_CTRL = 0x2F, + REG_ADC_DGAIN_CTRL, + REG_MUTE_CTRL, + REG_HSVOL_CTRL, + REG_DACL_CTRL, + REG_DACR_CTRL, + REG_ADC_DRC_KNEE_IP12 = 0x38, + REG_ADC_DRC_KNEE_IP34, + REG_ADC_DRC_SLOPES, + REG_ADC_DRC_ATKDCY, + REG_DAC_DRC_KNEE_IP12 = 0x45, //0x45 + REG_DAC_DRC_KNEE_IP34, + REG_DAC_DRC_SLOPES, + REG_DAC_DRC_ATKDCY = 0x48, //0x48 + REG_MODE_CTRL = 0x4C, //0x4C + REG_CLASSG_CTRL = 0x50, //0x50 + REG_OPT_EFUSE_CTRL, + REG_MISC_CTRL = 0x55, //0x55 + + REG_I2C_DEVICE_ID = 0x58, //0x58 + REG_SARDOUT_RAM_STATUS, + + REG_BIAS_ADJ = 0x66, //0x66 + + REG_TRIM_SETTINGS = 0x68, //0x68 + REG_ANALOG_CONTROL_1, + REG_ANALOG_CONTROL_2, + + REG_ANALOG_ADC_1 = 0x71, //0x71 + REG_ANALOG_ADC_2, + REG_RDAC, + REG_MIC_BIAS, //0x74 + REG_BOOST = 0x76, + REG_FEPGA, + REG_POWER_UP_CONTROL = 0x7F, //0x7F + REG_CHARGE_PUMP_AND_DOWN_CONTROL, //0x80 + REG_CHARGE_PUMP_INPUT_READ, + REG_GENERAL_STATUS +}; + + +// R1 REG_ENA_CTRL + +#define CLK_DRC_EN (1) +#define CLK_SAR_EN (1 << 1) +#define CLK_BIST_EN (1 << 3) +#define CLK_I2S_EN (1 << 4) +#define CLK_MODE_EN (1 << 5) +#define DCLK_DAC_EN (1 << 6) +#define DCLK_ADC_EN (1 << 7) +#define ADC_EN (1 << 8) +#define LDAC_EN (1 << 9) +#define RDAC_EN (1 << 10) +#define CLK_DAC_INV (1 << 14) +#define CMLCK_ENB (1 << 15) + + +// R2 REG_I2C_ADDR_SET +#define I2C_ADDDR_SEL +#define I2C_LSB_VAL_IO + + +// R3 REG_CLK_DIVIDER +#define MCLK_SRC_DIV1 (0) +#define MCLK_SRC_INVERTED (1) +#define MCLK_SRC_DIV2 (2) +#define MCLK_SRC_DIV4 (3) +#define MCLK_SRC_DIV8 (4) +#define MCLK_SRC_DIV16 (5) +#define MCLK_SRC_DIV32 (6) +#define MCLK_SRC_DIV3 (7) +#define MCLK_SRC_DIV6 (10) +#define MCLK_SRC_DIV12 (11) +#define MCLK_SRC_DIV24 (12) +#define MCLK_SRC_DIV48 (13) +#define MCLK_SRC_DIV96 (14) +#define MCLK_SRC_DIV5 (15) + +#define CLK_DAC_SRC_DIV1 (0) +#define CLK_DAC_SRC_DIV2 (1 << 4) +#define CLK_DAC_SRC_DIV4 (2 << 4) +#define CLK_DAC_SRC_DIV8 (3 << 4) + +#define CLK_ADC_SRC_DIV1 (0) +#define CLK_ADC_SRC_DIV2 (1 << 6) +#define CLK_ADC_SRC_DIV4 (2 << 6) +#define CLK_ADC_SRC_DIV8 (3 << 6) + +#define CLK_ADC_PL_INVERT (1 << 10) +#define CLK_DAC_PL_INVERT (1 << 11) +#define CLK_CODEC_SRC_IMCLK (0) +#define CLK_CODEC_SRC_PIN (1 << 13) +#define CLK_SYSCLK_SRC_VCO (1 << 15) +#define CLK_SYSCLK_SRC_PIN (0) + +// R4 REG_FLL1 +#define FLL_RATIO_512K (1) +#define FLL_RATIO_256K (1 << 1) +#define FLL_RATIO_128K (1 << 2) +#define FLL_RATIO_64K (1 << 3) +#define FLL_RATIO_32K (1 << 4) +#define FLL_RATIO_8K (1 << 5) +#define FLL_RATIO_4K (1 << 6) +#define FLL_LCOK_BP (1 << 7) +#define ICTRL_V2I_AMP2X (1 << 8) +#define ICTRL_V2I_AMP (1 << 9) +#define ICTRL_V2I_BOTHAMP (3 << 8) +#define ICTRL_LATCH_1X (1 << 10) +#define ICTRL_LATCH_2X (3 << 10) +#define ICTRL_LATCH_3X (7 << 10) +#define FLL1SELDAC_POS (13) +#define FLL1SELDAC_MSK (0x7 << FLL1SELDAC_POS) + +// R5 REG_FLL2 +#define FLLFRAC_POS (0) +#define FLLFRAC_MSK (0xFFFF << FLLFRAC_POS) + +// R6 REG_FLL3 +#define FLL_INTEGER(x) (x << 0) +#define FLL_CLK_REF_SRC_MCLKPIN (0) +#define FLL_CLK_REF_SRC_BCLKPIN (1 << 11) +#define FLL_CLK_REF_SRC_FSPIN (0x3 << 10) +#define GAIN_ERR_x1 (0x0) +#define GAIN_ERR_x2 (0x1 << 12) +#define GAIN_ERR_x4 (0x2 << 12) +#define GAIN_ERR_x8 (0x3 << 12) +#define GAIN_ERR_x16 (0x4 << 12) +#define GAIN_ERR_x32 (0x5 << 12) +#define GAIN_ERR_x64 (0x6 << 12) + + +// R7 REG_FLL4 +#define FLL_N2(x) (x << 0) +#define FLL_CLK_REF_DIV1 (0x0 << 10) +#define FLL_CLK_REF_DIV2 (0x1 << 10) +#define FLL_CLK_REF_DIV4 (0x2 << 10) +#define FLL_CLK_REF_DIV8 (0x3 << 10) +#define FLL_CLK_REF_DIV_4CHK_1 (0x0 << 12) +#define FLL_CLK_REF_DIV_4CHK_1_2 (0x1 << 12) +#define FLL_CLK_REF_DIV_4CHK_1_4 (0x2 << 12) +#define FLL_CLK_REF_DIV_4CHK_1_8 (0x3 << 12) +#define FLL_CLK_REF_DIV_4CHK_1_16 (0x4 << 12) +#define FLL_CLK_REF_DIV_4CHK_1_32 (0x5 << 12) + + +// R8 REG_FLL5 +#define FLL_LOCK_LENGTH(x) (x << 0) +#define FILTER_SW (0x1 << 12) +#define CLK_FILTER_SW (0x1 << 13) +#define CHB_FILTER_EN (0x1 << 14) +#define PDB_DACICTRL (0x1 << 15) + + +// R9 REG_FLL6 +#define FLL_SD_DITHER_SEL_1LSB (0x1 << 4) +#define FLL_SD_DITHER_SEL_2LSBs (0x2 << 4) +#define FLL_SD_DITHER_SEL_3LSBs (0x3 << 4) +#define FLL_FLTR_DITHER_SEL_1LSB (0x1 << 6) +#define FLL_FLTR_DITHER_SEL_2LSBs (0x2 << 6) +#define FLL_FLTR_DITHER_SEL_3LSBs (0x3 << 6) +#define CUTOFF600 (0x1 << 12) +#define CUTOFF500 (0x1 << 13) +#define SDM_EN (0x1 << 14) +#define DCO_EN (0x1 << 15) + + + +// R A REG_FLL_VCO_RSV +#define DOUT2VCO_RSV_POS (0) +#define DOUT2VCO_RSV_Msk (0xFFFF << FLLFRAC_POS) + +// R C REG_HSD_CTRL +#define MANU_SPKR_DWN1L_OPEN (0) +#define MANU_SPKR_DWN1L_GND (1) +#define MANU_SPKR_DWN1R_OPEN (0) +#define MANU_SPKR_DWN1R_GND (1 << 1) +#define MANU_ENGND2_OPEN (0) +#define MANU_ENGND2_GND (1 << 2) +#define MANU_ENGND1_OPEN (0) +#define MANU_ENGND1_GND (1 << 3) +#define MANUAL_START (1 << 4) +#define HSD_AUTO_MODE (1 << 6) +#define RESET_HSD (1 << 15) + + +// R D REG_JACK_DET_CTRL +#define JKDET_LOGIC_AND_GATE (1) +#define JKDET_LOGIC_OR_GATE (0) +#define JKDET_PL_N_INVERT (1) +#define JKDET_PL_INVERT (0) +#define EJECT_DT(x) (x << 2) +#define INSERT_DT(x) (x << 5) +#define DB_BP_MODE_BYBASS_DEBOUNCE (1 << 8) +#define DB_BP_MODE_NORMAL (0) +#define JD_RESTART (1) +#define JK_1_PL_GPIO2JD1 (0) +#define JK_1_PL_GPIO2JD1_INV (1 << 10) +#define JK_1_PL_IGNORE_0 (2 << 10) +#define JK_1_PL_IGNORE_1 (3 << 10) +#define JK_2_PL_JKDETL (0) +#define JK_2_PL_JKDETL_INV (1 << 12) +#define JK_2_PL_IGNORE_0 (2 << 12) +#define JK_2_PL_IGNORE_1 (3 << 12) +#define JK_3_PL_GPIO3JD2 (0) +#define JK_3_PL_GPIO3JD2_INV (1 << 14) +#define JK_3_PL_IGNORE_0 (2 << 14) +#define JK_3_PL_IGNORE_1 (3 << 14) + + +// R F REG_INTERRUPT_MASK +#define JK_DET_INTP_MASK (1) +#define JK_EJECT_INTP_MASK (1 << 2) +#define MIC_DET_INTP_MASK (1 << 4) +#define SHORT_KEY_INTP_MASK (1 << 5) +#define LONG_KEYINTP_MASK (1 << 6) +#define KEY_RELEASE_INTP_MASK (1 << 7) +#define RMS_INTP_MASK (1 << 8) +#define APR_EMRGENCY_SHTDWN1_INTP_MASK (1 << 9) +#define HSD_COMPLETE_INTP_MASK (1 << 10) +#define IRQ_OE (1 << 11) +#define IRQ_DS (1 << 12) +#define IRQ_PE (1 << 13) +#define IRQ_PS (1 << 14) +#define IRQ_PL (1 << 15) + + +// R 10 +#define JACK_DET_IRQ_JACK_INSERT (1) +#define JACK_DET_IRQ_JACK_INSERT_REMOVED (2) +#define JACK_EJCT_IRQ_JACK_INSERT (1 << 2) +#define JACK_EJCT_IRQ_JACK_INSERT_REMOVED (2 << 2) + +#define MIC_DET_INT (1 << 4) +#define SHORT_KEY_INT (1 << 5) +#define LONG_KEY_INT (1 << 6) +#define KEY_RELEASE_INT (1 << 7) +#define RMS_INT (1 << 8) +#define APR_EMRG_SHTDWN (1 << 9) +#define HSD_COMPL_ETE_INT (1 << 10) + + +// R 11 +#define NT_CLR_KEY_STATUS_LK0 (1) +#define NT_CLR_KEY_STATUS_LK1 (1 << 1) +#define NT_CLR_KEY_STATUS_LK2 (1 << 2) +#define NT_CLR_KEY_STATUS_LK3 (1 << 3) +#define NT_CLR_KEY_STATUS_LK4 (1 << 4) +#define NT_CLR_KEY_STATUS_LK5 (1 << 5) +#define NT_CLR_KEY_STATUS_LK6 (1 << 6) +#define NT_CLR_KEY_STATUS_LK7 (1 << 7) + +#define NT_CLR_KEY_STATUS_SK0 (1 << 8) +#define NT_CLR_KEY_STATUS_SK1 (1 << 9) +#define NT_CLR_KEY_STATUS_SK2 (1 << 10) +#define NT_CLR_KEY_STATUS_SK3 (1 << 11) +#define NT_CLR_KEY_STATUS_SK4 (1 << 12) +#define NT_CLR_KEY_STATUS_SK5 (1 << 13) +#define NT_CLR_KEY_STATUS_SK6 (1 << 14) +#define NT_CLR_KEY_STATUS_SK7 (1 << 15) + + +// R 12 +#define JACK_DET_INT_DIS (1) +#define JACK_EJCT_INT_DIS (1 << 2) +#define MIC_DET_INT_DIS (1 << 4) +#define SHORT_KEY_INT_DIS (1 << 5) +#define LONG_KEY_INT_DIS (1 << 6) +#define KEY_RELEASE_INT_DIS (1 << 7) +#define RMS_INT_DIS (1 << 8) +#define SHRT_SHTD_MIN_INT_DIS (1 << 9) +#define HSD_COMPL_ETE_INT_DIS (1 << 10) +#define LONG_KEY0_INT_DIS (1 << 11) +#define KEY0_RELEASE_INT_DIS (1 << 12) +#define KEY_RELEASE_CLR_INTR (1 << 13) + + +// R 13 SAR_CTRL +#define SAMPLE_SPEED_500NS (0) +#define SAMPLE_SPEED_4US (1 << 0) +#define SAMPLE_SPEED_8US (2 << 0) +#define SAMPLE_SPEED_16US (3 << 0) +#define COMP_SPEED_500NS (0 << 2) +#define COMP_SPEED_1US (1 << 2) +#define COMP_SPEED_2US (2 << 2) +#define COMP_SPEED_4US (3 << 2) +#define RES_SEL_35K_OHMS (0) +#define RES_SEL_70K_OHMS (1 << 4) +#define RES_SEL_170K_OHMS (2 << 4) +#define RES_SEL_360K_OHMS (3 << 4) +#define HV_SEL_VDDMIC (1 << 7) +#define HV_SEL_NCIBIAS (0) +#define SAR_TRACKGAIN_POS (8) +#define SAR_TRACKGAIN_MSK (0x7 << SAR_TRACKGAIN_POS) +#define INPUT_SEL_JKSLV (1 << 11) +#define INPUT_JKR2 (0) +#define SAR_ENA (1 << 12) +#define SAR_OUT_INV (1 << 13) + + +// R 14 +#define HY_COEFF(x) (x << 0) +#define SARADC_VDET_COEFF(x) (x << 4) + + +#define ENABLE_LEVEL_KEY0 (0) +#define ENABLE_LEVEL_KEY1 (1 << 8) +#define ENABLE_LEVEL_KEY2 (2 << 8) +#define ENABLE_LEVEL_KEY3 (3 << 8) +#define ENABLE_LEVEL_KEY4 (4 << 8) +#define ENABLE_LEVEL_KEY5 (5 << 8) +#define ENABLE_LEVEL_KEY6 (6 << 8) +#define ENABLE_LEVEL_KEY7 (7 << 8) + +#define SHORTKEY_DT_30MS (0) +#define SHORTKEY_DT_50MS (1 << 12) +#define SHORTKEY_DT_100MS (2 << 13) + +#define LONGKEY_DT_500MS (0) +#define LONGKEY_DT_1S (1 << 14) + + +// R 15/16/17/18 +#define SARADC_VDET_THR_1357_POS (0) +#define SARADC_VDET_THR_1357_MSK (0xFF << SARADC_VDET_THR_1357_POS) + +#define SARADC_VDET_THR_0246_POS (8) +#define SARADC_VDET_THR_0246_MSK (0xFF << SARADC_VDET_THR_0246_POS) + + +// R 19 REG_GPIO34_CTRL +#define GPIO3_OE (1 << 0) +#define GPIO3_DS (1 << 1) +#define GPIO3_PS (1 << 2) +#define GPIO3_PE (1 << 3) +#define GPIO3O (1 << 4) +#define GPIO4_OE (1 << 7) +#define GPIO4_DS (1 << 8) +#define GPIO4_PS (1 << 9) +#define GPIO4_PE (1 << 10) + + +// R 1A REG_GPIO12_CTRL +#define GPIO1_OE (1 << 0) +#define GPIO1_PE (1 << 1) +#define GPIO1_DS (1 << 2) +#define GPIO1_PS (1 << 3) +#define GPIO1SEL(x) (x << 4) +#define GPIO1POL (1 << 7) +#define GPIO2_OE (1 << 8) +#define GPIO2_PE (1 << 9) +#define GPIO2_DS (1 << 10) +#define GPIO2_PS (1 << 11) + + + +// R 1B REG_TDM_CTRL +#define ADC_TX_SEL_SLOT(x) (x << 0) +#define DAC_RIGHT_SEL_SLOT(x) (x << 4) +#define DAC_LEFT_SEL_SLOT(x) (x << 6) +#define PCM_OFFSET_MODE_CTRL (1 << 14) +#define TDM (1 << 15) + + +// R 1C REG_I2S_PCM_CTRL1 +#define AIFMT0_RIGHTJUST (0) +#define AIFMT0_LEFTJUST (1 << 0) +#define AIFMT0_STANDI2S (2 << 0) +#define AIFMT0_PCMA_B (3 << 0) + +#define WLEN0_16BIT (0) +#define WLEN0_20BIT (1 << 2) +#define WLEN0_24BIT (2 << 2) +#define WLEN0_32BIT (3 << 2) + +#define ADCPHS0_LEFT (0) +#define ADCPHS0_RIGHT (1 << 4) + +#define DACPHS0_LEFT (0) +#define DACPHS0_RIGHT (1 << 5) + +#define LRP0 (1 << 6) +#define BCP0 (1 << 7) +#define UA_OFFSET_1S (0) +#define UA_OFFSET_2S (1) +#define CMB8_0_NORMAL (0) +#define CNB8_0_8BIT (1 << 10) +#define ADDAP0 (1 << 11) +#define ADCCM0_ULAW (2 << 12) +#define ADCCM0_ALAW (3 << 12) +#define DACCM0_ULAW (2 << 14) +#define DACCM0_ALAW (3 << 14) + + + +// R 1D REG_2S_PCM_CTRL2 +#define BLCKDIV_DIV2 (0) +#define BLCKDIV_DIV4 (1) +#define BLCKDIV_DIV8 (2) +#define BLCKDIV_DIV16 (3) +#define BLCKDIV_DIV32 (4) +#define BLCKDIV_DIV64 (5) + +#define MS0_SLAVE (0) +#define MS0_MASTER (1 << 3) + +#define ADCDAT0_OE (1 << 4) +#define ADCDAT0_PS_PULLUP (1 << 5) +#define ADCDAT0_PS_PULLDOWN (0) + +#define ADCDAT0_PE (1 << 6) +#define PCM8BIT0 (1 << 8) +#define TRI0 (1 << 9) +#define PCM_TS_EN0 (1 << 10) +#define LRC_DIV_DIV256 (0) +#define LRC_DIV_DIV128 (1 << 12) +#define LRC_DIV_DIV64 (2 << 12) +#define LRC_DIV_DIV32 (3 << 12) +#define I2S_DRV (1 << 14) +#define I2S_TRI (1 << 15) + + +// R 1E REG_LEFT_TIME_SLOT +#define TSLOT_L0_POS (0) +#define TSLOT_L0_MSK (0x3FF << TSLOT_L0_POS) +#define DIS_FS_SHORT_DET (1 << 13) +#define FS_ERR_CMP_SEL_252MCLK (0) +#define FS_ERR_CMP_SEL_253MCLK (1 << 14) +#define FS_ERR_CMP_SEL_254MCLK (2 << 14) +#define FS_ERR_CMP_SEL_255MCLK (3 << 15) + + +// R 1F REG_RIGHT_TIME_SLOT +#define TSLOT_R0_POS (0) +#define TSLOT_R0_MSK (0x3FF << TSLOT_R0_POS) + + +// R 20 REG_BIQ_CTRL +#define BIQ_PATH_SE_ADC (0) +#define BIQ_PATH_SE_DAC (1) +#define BIQ_COF_SE_SYNC_FS (0) +#define BIQ_COF_SE_NO_SYNC (1 << 1) +#define ADC_PATH_EN (1 << 2) +#define DAC_PATH_EN (1 << 3) +#define BIQ_WRT_EN (1 << 4) + + +// R 21 REG_BIQ_COF1 +#define BIQ_A1_L_POS (0) +#define BIQ_A1_L_MSK (0xFFFF << BIQ_A1_L_POS) + +// R 22 REG_BIQ_COF2 +#define BIQ_A1_H_POS (0) +#define BIQ_A1_H_MSK (0x7 << BIQ_A1_H_POS) + +// R 23 REG_BIQ_COF3 +#define BIQ_A2_L_POS (0) +#define BIQ_A2_L_MSK (0xFFFF << BIQ_A2_L_POS) + +// R 24 REG_BIQ_COF4 +#define BIQ_A2_H_POS (0) +#define BIQ_A2_H_MSK (0x7 << BIQ_A2_H_POS) + + +// R 25 REG_BIQ_COF5 +#define BIQ_B0_L_POS (0) +#define BIQ_B0_L_MSK (0xFFFF << BIQ_B0_L_POS) + +// R 26 REG_BIQ_COF6 +#define BIQ_B0_H_POS (0) +#define BIQ_B0_H_MSK (0x7 << BIQ_B0_H_POS) + + +// R 27 REG_BIQ_COF7 +#define BIQ_B1_L_POS (0) +#define BIQ_B1_L_MSK (0xFFFF << BIQ_B1_L_POS) + +// R 28 REG_BIQ_COF8 +#define BIQ_B1_H_POS (0) +#define BIQ_B1_H_MSK (0x7 << BIQ_B1_H_POS) + + +// R 29 REG_BIQ_COF9 +#define BIQ_B2_L_POS (0) +#define BIQ_B2_L_MSK (0xFFFF << BIQ_B2_L_POS) + +// R 2A REG_BIQ_COF10 +#define BIQ_B2_H_POS (0) +#define BIQ_B2_H_MSK (0x7 << BIQ_B2_H_POS) + + +// R 2B REG_ADC_RATE +#define ADC_RATE_32 (0) +#define ADC_RATE_64 (1) +#define ADC_RATE_128 (2) +#define ADC_RATE_256 (3) + +#define SMPL_RATE_48K (0) +#define SMPL_RATE_32K (1 << 5) +#define SMPL_RATE_96K (3 << 5) +#define SMPL_RATE_192K (7 << 5) + + +// R 2C REG_DAC_CTRL1 +#define DAC_RATE_64 (0) +#define DAC_RATE_256 (1) +#define DAC_RATE_128 (2) +#define DAC_RATE_32 (4) +#define CUC_GAIN_ADJ(x) (x << 4) +#define DEM_DLY_N (1 << 14) +#define DISABLE_DEM (1 << 15) + + +// R 2D REG_DAC_CTRL2 +#define DACPR_INVERT (1) +#define DAC_PL_INVERT (1 << 1) +#define DAC_STEP_SEL_DACCLK (4 << 4) +#define DAC_STEP_SEL_DLY1_MCLK (5 << 4) +#define DAC_STEP_SEL_DLY2_MCLK (6 << 4) +#define DAC_STEP_SEL_DLY3_MCLK (7 << 4) +#define DSMOD_DITHER(x) (x << 7) +#define DEM_DITHER(x) (x << 12) + + +// R 2F REG_DAC_DGAIN_CTRL +#define DAC0_TO_DAC1_ST(x) (x << 0) +#define DAC1_TO_DAC0_ST(x) (x << 8) + +// R 30 REG_ADC_DGAIN_CTRL +#define DGAINL_ADC0(x) (x) +#define ADC_TO_DAC_ST1(x) (x << 8) +#define ADC_TO_DAC_ST0(x) (x << 12) + +// R 31 REG_MUTE_CTRL +#define ADC_SMUTE_EN (1 << 1) +#define ADC_ZC_UP_EN (1 << 2) +#define SMUTE_CTRL (1 << 8) +#define SMUTE_EN (1 << 9) +#define AMUTE_CTRL (1 << 10) +#define AMUTE_EN (1 << 11) +#define DAC_ZC_UP_EN (1 << 12) +#define PGA_SMUTE_STEP_128 (0 << 14) +#define PGA_SMUTE_STEP_32 (1 << 14) +#define PGA_SMUTE_STEP_16 (2 << 14) +#define PGA_SMUTE_STEP_1 (3 << 14) + + +// R 32 REG_HSVOL_CTRL +#define HSPGA1_VOL(x) (x << 0) +#define HSPGA0_VOL(x) (x << 6) +#define MUTE_HSPGA1 (1 << 12) +#define MUTE_HSPGA0 (1 << 13) +#define HSPGA_MUTE_AUTO_MODE (1 << 14) +#define HSPGA_MUTE_EN (1 << 15) + + +// R 33 REG_DACL_CTRL +#define DGAINL_DAC(x) (x << 0) +#define DAC_CH_SEL0_LEFT (0) +#define DAC_CH_SEL0_RIGHT (1 << 9) +#define DAC_MIXER_L (1 << 14) +#define DAC_MIXER_R (1 << 15) + + +// R 34 REG_DACR_CTRL +#define DGAINR_DAC(x) (x << 0) +#define DAC_CH_SEL1_LEFT (0) +#define DAC_CH_SEL1_RIGHT (1 << 9) + +// R 38 REG_ADC_DRC_KNEE_IP12 +#define DRC_KNEE1_IP_ADC1(x) (x << 0) +#define DRC_SMTH_ENA_ADC1 (1 << 7) +#define DRC_KNEE2_IP_ADC1(x) (x << 8) +#define DRC_ENA_ADC1 (1 << 15) + + +// R 39 REG_ADC_DRC_KNEE_IP34 +#define DRC_KNEE3_IP_ADC1(x) (x << 0) +#define DRC_KNEE4_IP_ADC1(x) (x << 8) + + +// R 3A REG_ADC_DRC_SLOPES +#define DRC_LMT_SLP_ADC1_0 (0) +#define DRC_LMT_SLP_ADC1_1_2 (1) +#define DRC_LMT_SLP_ADC1_1_4 (2) +#define DRC_LMT_SLP_ADC1_1_8 (3) +#define DRC_LMT_SLP_ADC1_1_16 (4) +#define DRC_LMT_SLP_ADC1_1_32 (5) +#define DRC_LMT_SLP_ADC1_1_64 (6) +#define DRC_LMT_SLP_ADC1_1 (7) + +#define DRC_CMP1_SLP_ADC1_0 (0) +#define DRC_CMP1_SLP_ADC1_1_2 (1 << 3) +#define DRC_CMP1_SLP_ADC1_1_4 (2 << 3) +#define DRC_CMP1_SLP_ADC1_1_8 (3 << 3) +#define DRC_CMP1_SLP_ADC1_1_16 (4 << 3) +#define DRC_CMP1_SLP_ADC1_1 (7 << 3) + +#define DRC_CMP2_SLP_ADC1_0 (0) +#define DRC_CMP2_SLP_ADC1_1_2 (1 << 6) +#define DRC_CMP2_SLP_ADC1_1_4 (2 << 6) +#define DRC_CMP2_SLP_ADC1_1_8 (3 << 6) +#define DRC_CMP2_SLP_ADC1_1_16 (4 << 6) +#define DRC_CMP2_SLP_ADC1_1 (7 << 6) + +#define DRC_EXP_SLP_ADC1_1_1 (0) +#define DRC_EXP_SLP_ADC1_2_1 (1 << 9) +#define DRC_EXP_SLP_ADC1_4_1 (2 << 9) + +#define DRC_NG_SLP_ADC1_1_1 (0) +#define DRC_NG_SLP_ADC1_2_1 (1 << 12) +#define DRC_NG_SLP_ADC1_4_1 (2 << 12) +#define DRC_NG_SLP_ADC1_8_1 (3 << 12) + + + +// R 3B REG_ADC_DRC_ATKDCY +#define DRC_DCY_ADC1_63 (0) +#define DRC_DCY_ADC1_127 (1) +#define DRC_DCY_ADC1_255 (2) +#define DRC_DCY_ADC1_511 (3) +#define DRC_DCY_ADC1_1023 (4) +#define DRC_DCY_ADC1_2047 (5) +#define DRC_DCY_ADC1_4095 (6) +#define DRC_DCY_ADC1_8191 (7) +#define DRC_DCY_ADC1_16383 (8) +#define DRC_DCY_ADC1_32757 (9) +#define DRC_DCY_ADC1_65535 (10) + +#define DRC_ATK_ADC1_x1 (0) +#define DRC_ATK_ADC1_x3 (1 << 4) +#define DRC_ATK_ADC1_x7 (2 << 4) +#define DRC_ATK_ADC1_x15 (3 << 4) +#define DRC_ATK_ADC1_x31 (4 << 4) +#define DRC_ATK_ADC1_x63 (5 << 4) +#define DRC_ATK_ADC1_x127 (6 << 4) +#define DRC_ATK_ADC1_x255 (7 << 4) +#define DRC_ATK_ADC1_x511 (8 << 4) +#define DRC_ATK_ADC1_x1023 (9 << 4) +#define DRC_ATK_ADC1_x2047 (10 << 4) +#define DRC_ATK_ADC1_x4095 (11 << 4) +#define DRC_ATK_ADC1_x8191 (12 << 4) + + +#define DRC_PK_COEF2_ADC1_63 (0) +#define DRC_PK_COEF2_ADC1_127 (1 << 8) +#define DRC_PK_COEF2_ADC1_255 (2 << 8) +#define DRC_PK_COEF2_ADC1_511 (3 << 8) +#define DRC_PK_COEF2_ADC1_1023 (4 << 8) +#define DRC_PK_COEF2_ADC1_2047 (5 << 8) +#define DRC_PK_COEF2_ADC1_4095 (6 << 8) +#define DRC_PK_COEF2_ADC1_8191 (7 << 8) + +#define DRC_PK_COEF1_ADC1_x1 (0) +#define DRC_PK_COEF1_ADC1_x3 (1 << 12) +#define DRC_PK_COEF1_ADC1_x7 (2 << 12) +#define DRC_PK_COEF1_ADC1_x15 (3 << 12) +#define DRC_PK_COEF1_ADC1_x31 (4 << 12) +#define DRC_PK_COEF1_ADC1_x63 (5 << 12) +#define DRC_PK_COEF1_ADC1_x127 (6 << 12) +#define DRC_PK_COEF1_ADC1_x255 (7 << 12) + + +// R 45 REG_DAC_DRC_KNEE_IP12 +#define DRC_KNEE1_IP_DAC(x) (x) +#define DRC_SMTH_ENA_DAC (1 << 7) +#define DRC_KNEE2_IP_DAC(x) (x << 8) +#define DRC_ENA_DAC (1 << 15) + + +// R 46 REG_DAC_DRC_KNEE_IP34 +#define DRC_KNEE3_IP_DAC(x) (x) +#define DRC_KNEE4_IP_DAC(x) (x << 8) + +// R 47 REG_DAC_DRC_SLOPES +#define DRC_LMT_SLP_DAC_0 (0) +#define DRC_LMT_SLP_DAC_1_2 (1) +#define DRC_LMT_SLP_DAC_1_4 (2) +#define DRC_LMT_SLP_DAC_1_8 (3) +#define DRC_LMT_SLP_DAC_1_16 (4) +#define DRC_LMT_SLP_DAC_1_32 (5) +#define DRC_LMT_SLP_DAC_1_64 (6) +#define DRC_LMT_SLP_DAC_1_1 (7) + +#define DRC_CMP1_SLP_DAC_0 (0) +#define DRC_CMP1_SLP_DAC_1_2 (1 << 3) +#define DRC_CMP1_SLP_DAC_1_4 (2 << 3) +#define DRC_CMP1_SLP_DAC_1_8 (3 << 3) +#define DRC_CMP1_SLP_DAC_1_16 (4 << 3) +#define DRC_CMP1_SLP_DAC_1 (7 << 3) + +#define DRC_CMP2_SLP_DAC_0 (0) +#define DRC_CMP2_SLP_DAC_1_2 (1 << 6) +#define DRC_CMP2_SLP_DAC_1_4 (2 << 6) +#define DRC_CMP2_SLP_DAC_1_8 (3 << 6) +#define DRC_CMP2_SLP_DAC_1_16 (4 << 6) +#define DRC_CMP2_SLP_DAC_1 (7 << 6) + +#define DRC_EXP_SLP_DAC_1_1 (0) +#define DRC_EXP_SLP_DAC_2_1 (1 << 9) +#define DRC_EXP_SLP_DAC_4_1 (2 << 9) +#define DRC_EXP_SLP_DAC_8_1 (3 << 9) + +#define DRC_NG_SLP_DAC_1_1 (0) +#define DRC_NG_SLP_DAC_2_1 (1 << 12) +#define DRC_NG_SLP_DAC_4_1 (2 << 12) +#define DRC_NG_SLP_DAC_8_1 (3 << 12) + + +// R 48 REG_DAC_DRC_ATKDCY +#define DRC_DCY_DAC_63 (0) +#define DRC_DCY_DAC_127 (1) +#define DRC_DCY_DAC_255 (2) +#define DRC_DCY_DAC_511 (3) +#define DRC_DCY_DAC_1023 (4) +#define DRC_DCY_DAC_2047 (5) +#define DRC_DCY_DAC_4095 (6) +#define DRC_DCY_DAC_8191 (7) +#define DRC_DCY_DAC_16383 (8) +#define DRC_DCY_DAC_32757 (9) +#define DRC_DCY_DAC_65535 (10) + +#define DRC_ATK_DAC_x1 (0) +#define DRC_ATK_DAC_x3 (1 << 4) +#define DRC_ATK_DAC_x7 (2 << 4) +#define DRC_ATK_DAC_x15 (3 << 4) +#define DRC_ATK_DAC_x31 (4 << 4) +#define DRC_ATK_DAC_x63 (5 << 4) +#define DRC_ATK_DAC_x127 (6 << 4) +#define DRC_ATK_DAC_x255 (7 << 4) +#define DRC_ATK_DAC_x511 (8 << 4) +#define DRC_ATK_DAC_x1023 (9 << 4) +#define DRC_ATK_DAC_x2047 (10 << 4) +#define DRC_ATK_DAC_x4095 (11 << 4) +#define DRC_ATK_DAC_x8191 (12 << 4) + + +#define DRC_PK_COEF2_DAC_63 (0) +#define DRC_PK_COEF2_DAC_127 (1 << 8) +#define DRC_PK_COEF2_DAC_255 (2 << 8) +#define DRC_PK_COEF2_DAC_511 (3 << 8) +#define DRC_PK_COEF2_DAC_1023 (4 << 8) +#define DRC_PK_COEF2_DAC_2047 (5 << 8) +#define DRC_PK_COEF2_DAC_4095 (6 << 8) +#define DRC_PK_COEF2_DAC_8191 (7 << 8) + +#define DRC_PK_COEF1_DAC_x1 (0) +#define DRC_PK_COEF1_DAC_x3 (1 << 12) +#define DRC_PK_COEF1_DAC_x7 (2 << 12) +#define DRC_PK_COEF1_DAC_x15 (3 << 12) +#define DRC_PK_COEF1_DAC_x31 (4 << 12) +#define DRC_PK_COEF1_DAC_x63 (5 << 12) +#define DRC_PK_COEF1_DAC_x127 (6 << 12) +#define DRC_PK_COEF1_DAC_x255 (7 << 12) + + +// R 4C REG_MODE_CTRL +#define DACIN_SRC_DAC_BIQUAD (0) +#define DACIN_SRC_DRC_DAC (1) +#define DACIN_SRC_DAC_MIXER (2) +#define DACIN_SRC_BUILDIN_SINE (3) +#define DACIN_SRC_DRC_LAW_DECODE (4) + + +// R 50 REG_CLASSG_CTRL +#define CLASSG_EN (1) +#define CLASSG_CMP_EN_L_DAC (1 << 1) +#define CLASSG_CMP_EN_R_DAC (1 << 2) +#define CLASSG_THRSLD_1_16 (0) +#define CLASSG_THRSLD_1_8 (1 << 4) +#define CLASSG_THRSLD_3_16 (2 << 4) +#define CLASSG_THRSLD_1_4 (3 << 4) + +#define CLASSG_TIMER_1MS (1 << 8) +#define CLASSG_TIMER_2MS (2 << 8) +#define CLASSG_TIMER_8MS (4 << 8) +#define CLASSG_TIMER_16MS (8 << 8) +#define CLASSG_TIMER_32MS (16 << 8) +#define CLASSG_TIMER_64MS (32 << 8) +#define CLASSG_CLK_SRC_2M (0) +#define CLASSG_CLK_SRC_1_3MCLK (1 << 14) +#define CLASSG_CLK_SRC_MCLK (2 << 14) +#define CLASSG_CLK_SRC_DISABLE_CLK (3 << 14) + +// R 51 REG_OPT_EFU +#define WL_BIN_POS (0) +#define WL_BIN_MSK (0x3F << WL_BIN_POS) + +#define STROBE_IN (1 << 6) +#define PGEN_IN (1 << 7) +#define NR_IN (1 << 8) +#define STANDBY_IN (1 << 15) + +// R 55 REG_MISC_CTRL +#define D2A_LOOP (1 << 1) +#define RAM_TEST_START (1 << 3) +#define SPIEN (1 << 15) +#define I2CEN (0) + +// R 58 REG_I2C_DEVICE_ID +#define Software_ID (0x3) +#define Silicon_Revision_ID (0x7 << 2) +#define JKDETL (0x1 << 5) +#define GPIO3JD2 (0x1 << 6) +#define GPIO2JD1 (0x1 << 7) +#define I2C_DEVICE_ID (0x3F << 9) + +// R 59 REG_SARDOUT_RAM_STATUS +#define SARADC_DOUT (0xff) +#define ANALOG_MUTE (0x1 << 10) +#define RAM_TEST_FAIL (0x3 << 11) +#define RATM_TEST_FINISH (0x1 << 13) + + +// R 66 REG_BIAS_ADJ +#define BIASADJ_NORMAL (0x0) +#define BIASADJ_9 (0x1 << 0) +#define BIASADJ_17 (0x2 << 0) +#define BIASADJ_11 (0x3 << 0) +#define VMIDSEL_OPEN (0x0 << 4) +#define VMIDSEL_25K_OHM (0x1 << 4) +#define VMIDSEL_125K_OHM (0x2 << 4) +#define VMIDSEL_2P5K_OHM (0x3 << 4) +#define VMIDEN (0x1 << 6) +#define MUTEL (0x1 << 13) + +// R 68 REG_TRIM_SETTINGS +#define DIS_OC_RIGHT (0x2) +#define DIS_OC_LEFT (0x4) +#define INTEG_ICUTHS (0x1 << 8) +#define INTEG_IBCTRHS (0x1 << 9) +#define DRV_ICUTHS (0x1 << 14) +#define DRV_IBCTRHS (0x1 << 15) + + +// R 69 REG_ANALOG_CONTROL_1 +#define ENJKDETL (0x1 << 0) +#define JKDETLPOL (0x1 << 1) +#define JD1POL (0x1 << 2) +#define GPIO2THH_P85x (0x0) +#define GPIO2THH_P78x (0x2 << 4) +#define GPIO2THH_P6x (0x3 << 4) +#define GPIO2THL_P22x (0x0) +#define GPIO2THL_P4x (0x2 << 6) +#define GPIO2THL_P5x (0x3 << 6) +#define Pullup_GPIO2_1M (0x0) +#define Pullup_GPIO2_100K (0x1 << 8) +#define GPIO3THH_P85x (0x0) +#define GPIO3THH_P78x (0x2 << 9) +#define GPIO3THH_P6x (0x3 << 9) +#define GPIO3THL_P22x (0x0) +#define GPIO3THL_P4x (0x2 << 11) +#define GPIO3THL_P5x (0x3 << 11) +#define Pullup_GPIO3_1M (0x0) +#define Pullup_GPIO3_100K (0x1 << 13) + + + +// R 6A REG_ANALOG_CONTROL_2 +#define CAP_0 (0x1) +#define CAP_1 (0x1 << 1) +#define MUTEMICN (0x1 << 2) +#define MUTEMICP (0x1 << 3) +#define AB_ADJ (0x1 << 7) + + + +// R 71 REG_ANALOG_ADC_1 +#define CHOPF0_DIV2 (0) +#define CHOPF0_DIV4 (0x1 << 0) +#define CHOPF0_DIV8 (0x2 << 0) +#define CHOPF0_DIV16 (0x3 << 0) +#define CHOPORDER (0x1 << 2) +#define CHOPFIXED (0x1 << 3) +#define CHOPRESETN (0x1 << 4) +#define CHOPPHASE (0x1 << 5) +#define CHOPENABLE (0x1 << 6) +#define RESETL (0x1 << 8) + + +// R 72 REG_ANALOG_ADC_2 +#define MON4TH (0x1 << 0) +#define MON3RD (0x1 << 1) +#define MON2ND (0x1 << 2) +#define MON1ST (0x1 << 3) +#define MONADD (0x1 << 4) +#define LFSRRESETN (0x1 << 5) +#define PDNOTL (0x1 << 6) + +#define VREFSEL_ANALOG (0x0 << 8) +#define VREFSEL_VMIDE (0x1 << 8) +#define VREFSEL_VMIDE_P5DB (0x2 << 8) +#define VREFSEL_ANALOG_1DB (0x3 << 8) + +#define BIAS_NORMAL (0x0 << 10) +#define BIAS_BOUBLE (0x1 << 10) +#define BIAS_HALF (0x2 << 10) +#define BIAS_QUARTER (0x3 << 10) +#define ADC_UPL (0x1 << 13) + + + +// R 73 REG_RDAC +#define DACVREFSEL(x) (x << 2) +#define CLK_DAC_DELAY_0NSEC (0) +#define CLK_DAC_DELAY_1NSEC (0x1 << 4) +#define CLK_DAC_DELAY_2NSEC (0x2 << 4) +#define CLK_DAC_DELAY_3NSEC (0x3 << 4) +#define CLK_DAC_DELAY_4NSEC (0x4 << 4) +#define CLK_DAC_DELAY_N3NSEC (0x5 << 4) +#define CLK_DAC_DELAY_N2NSEC (0x6 << 4) +#define CLK_DAC_DELAY_N1NSEC (0x7 << 4) + +#define FC_CTR (0x1 << 7) +#define CLK_DAC_EN_R (0x1 << 9) +#define CLK_DAC_EN_L (0x1 << 8) +#define DAC_EN_R (0x1 << 13) +#define DAC_EN_L (0x1 << 12) +#define FS_BCLK_ENB (0x1 << 15) + + +// R 74 REG_MIC_BIAS +#define MICBIASLVL1_VDDA (0) +#define MICBIASLVL1_1x (0x1 << 0) +#define MICBIASLVL1_1P1x (0x2 << 0) +#define MICBIASLVL1_1P2x (0x3 << 0) +#define MICBIASLVL1_1P3x (0x4 << 0) +#define MICBIASLVL1_1P4x (0x5 << 0) +#define MICBIASLVL1_1P53x (0x6 << 0) + +#define NOCAP (0x1 << 6) +#define POWERUP (0x1 << 8) +#define LOWNOISE (0x1 << 10) +#define INT2KA (0x1 << 12) +#define INT2KB (0x1 << 14) + + +// R 76 REG_BOOST +#define NAMP_THRSHLD(x) (x << 0) +#define PAMP_THRSHLD(x) (x << 2) +#define HS_SHRT_THRESHLD(x) (x << 4) +#define EN_SHRT_SHTDWN (0x1 << 6) +#define SHRT_SHTDWN_DIG_EN (0x1 << 7) +#define BOOSTGDIS (0x1 << 8) +#define BOOSTDIS (0x1 << 9) +#define BYPS_IBCTR (0x1 << 10) +#define DISCHRG (0x1 << 11) +#define BIASEN (0x1 << 12) +#define PDVMDFST (0x1 << 13) +#define STG2_SEL (0x1 << 14) +#define CLR_APR_EMRGENCY_SHTDWN (0x1 << 15) + + +// R 77 REG_FEPGA +#define FEPGA_MODEL_ANIT_ALIASING (0x1 << 0) +#define FEPGA_MODEL_DISCONNECT_MICPN (0x1 << 1) +#define FEPGA_MODEL_12KOHM_SHORT (0x1 << 3) + +#define IBCTR_CODE(x) (x << 8) +#define IB_LOOP_CTR (0x1 << 11) +#define CMLCK_ADJ(x) (x << 12) +#define ACDC_CTRL_MICP_VREF (0x1 << 14) +#define ACDC_CTRL_MICN_VREF (0x1 << 15) + + +// R 7F REG_POWER_UP_CONTROL +#define PUP_MAIN_DRV_LEFT_HP (0x1 << 0) +#define PUP_MAIN_DRV_RIGHT_HP (0x1 << 1) +#define PUP_DRV_INSTG_LEFT_HP (0x1 << 2) +#define PUP_DRV_INSTG_RIGHT_HP (0x1 << 3) +#define PUP_INTEG_LEFT_HP (0x1 << 4) +#define PUP_INTEG_RIGHT_HP (0x1 << 5) +#define FEPGA_GAIN(x) (x << 8) +#define PUFEPGA (0x1 << 14) + + + +// R 80 REG_CHARGE_PUMP_AND_POWER_DOWN_CONTROL +#define SHCIRSEL1_HIGH (0x1) +#define SHCIRSEL1_LOW (0) +#define SHCIRSEL2_HIGH (0x1 << 1) +#define SHCIRSEL2_LOW (0) +#define DISCHARGEVPOS (0x1 << 2) +#define DISCHARGEVEE (0x1 << 3) +#define PRECHARGE (0x1 << 4) +#define RNIN (0x1 << 5) +#define JAMFORCE1 (0x1 << 6) +#define JAMFORCE2 (0x1 << 7) +#define PD_DAC_ENABLE (0x3 << 8) +#define JAMNODCLOW (0x1 << 10) +#define ADCDAT_DS (0x1 << 12) +#define FS_DS (0x1 << 13) +#define BCLK_DS (0x1 << 14) + + +// R 81 REG_CHARGE_PUMP_INPUT_READ +#define FORCE1BUF (0x1 << 0) +#define VCOMPBUF (0x1 << 1) +#define VPOSOK (0x1 << 2) +#define RN2BUF (0x1 << 3) +#define NODCBUF (0x1 << 4) +#define MODE1BUF (0x1 << 5) +#define APR_EMRGNCY_SHTDWN (0x1 << 15) + + +// R 82 REG_GENERAL_STATUS +#define GPIO1_IN (0x1 << 0) +#define GPIO2_IN (0x1 << 1) +#define GPIO3_IN (0x1 << 2) +#define GPIO4_IN (0x1 << 3) +#define JKDETL1 (0x1 << 4) +#define JKDET_ON (0x1 << 5) +#define JK_INSERT_INTR (0x1 << 6) +#define JK_EJECT_INTR (0x1 << 7) +#define OUT1 (0x1 << 8) +#define OUT2 (0x1 << 9) +#define OUT1_OUT (0x1 << 10) +#define OUT2_OUT (0x1 << 11) + +typedef struct +{ + char *i2c_bus_name; + + char *i2s_bus_name; + + rt_int32_t pin_phonejack_en; + + rt_int32_t pin_phonejack_det; + +} S_NU_NAU88L25_CONFIG; + +int nu_hw_nau88l25_init(S_NU_NAU88L25_CONFIG *psCodecConfig); + +#endif /* __ACODEC_NAU88L25_H__ */ diff --git a/bsp/nuvoton/libraries/nu_packages/AudioCodec/audio_test.c b/bsp/nuvoton/libraries/nu_packages/AudioCodec/audio_test.c new file mode 100644 index 0000000000000000000000000000000000000000..9756f26ffdffb707e862a0f308511c26efa33a20 --- /dev/null +++ b/bsp/nuvoton/libraries/nu_packages/AudioCodec/audio_test.c @@ -0,0 +1,82 @@ +/**************************************************************************//** +* +* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-1-16 Wayne First version +* +******************************************************************************/ + +#include + +#if defined(PKG_USING_WAVPLAYER) + +#include "wavrecorder.h" +#include "wavplayer.h" +#include "dfs_posix.h" + +/* + The routine just for test automatically. + - For record function: Run it w/o parameter. + - For replay function: Run it with parameter. +*/ +static void audio_test(int argc, char **argv) +{ +#define DEF_MAX_ARGV_NUM 8 + int smplrate[] = {8000, 11025, 16000, 22050, 32000, 44100, 48000}; + int smplbit[] = {16}; + int chnum[] = {1, 2}; + struct wavrecord_info info; + char strbuf[128]; + int i, j, k; + int bDoRecording = 1; + struct stat stat_buf; + + if (argc > 1) + bDoRecording = 0; + + for (i = 0; i < sizeof(smplrate) / sizeof(int); i++) + { + for (j = 0; j < sizeof(smplbit) / sizeof(int); j++) + { + for (k = 0; k < sizeof(chnum) / sizeof(int); k++) + { + snprintf(strbuf, sizeof(strbuf), "/mnt/sd0/%d_%d_%d.wav", smplrate[i], smplbit[j], chnum[k]); + + if (bDoRecording) + { + rt_kprintf("Recording file at %s\n", strbuf); + info.uri = strbuf; + info.samplerate = smplrate[i]; + info.samplebits = smplbit[j]; + info.channels = chnum[k]; + wavrecorder_start(&info); + rt_thread_mdelay(10000); + wavrecorder_stop(); + rt_thread_mdelay(1000); + } + else + { + if (stat((const char *)strbuf, &stat_buf) < 0) + { + rt_kprintf("%s non-exist.\n", strbuf); + continue; + } + + rt_kprintf("Replay file at %s\n", strbuf); + wavplayer_play(strbuf); + rt_thread_mdelay(10000); + wavplayer_stop(); + } + } // k + } // j + } // i +} + +#ifdef FINSH_USING_MSH + MSH_CMD_EXPORT(audio_test, Audio record / replay); +#endif +#endif /* PKG_USING_WAVPLAYER */ diff --git a/bsp/nuvoton/libraries/nu_packages/BMX055/SConscript b/bsp/nuvoton/libraries/nu_packages/BMX055/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..385eb0df9097192099583076389eb754fb12ba75 --- /dev/null +++ b/bsp/nuvoton/libraries/nu_packages/BMX055/SConscript @@ -0,0 +1,16 @@ +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +group = [] +if GetDepend('NU_PKG_USING_BMX055'): + src = Split(""" + libraries/BMA2x2_driver/bma2x2.c + libraries/BMG160_driver/bmg160.c + libraries/BMM050_driver/bmm050.c + sensor_bmx055.c + """) + CPPPATH = [cwd, cwd+'/libraries/BMA2x2_driver/', cwd+'/libraries/BMG160_driver/', cwd+'/libraries/BMM050_driver/'] + group = DefineGroup('nu_pkgs_bmx055', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMA2x2_driver/README.md b/bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMA2x2_driver/README.md new file mode 100644 index 0000000000000000000000000000000000000000..4ec36e63ee99c66cb3b1cdce5e70eaff7ced22bf --- /dev/null +++ b/bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMA2x2_driver/README.md @@ -0,0 +1,59 @@ +## Table of Contents +- [Introduction](#intro) +- [Version](#ver) +- [Integration details](#integration) +- [Driver files information](#fileinfo) +- [Supported sensor interface](#interface) +- [Copyright](#copy) + +### Introduction +- This package contains the Bosch Sensortec MEMS accelerometer sensor driver (sensor API) +- The sensor driver package includes bma2x2.h, bma2x2.c and bma2x2_support.c files +- BMA2x2 sensor driver supports the following Bosch MEMS sensors + * BMA280 + * BMA255 + * BMA253 + * BMA250E + * BMA22E + * BMA220 + * BMI055 - Combination of bma2x2 + bmg160 APIs + * BMX055 - Combination of bma2x2 + bmg160 + bmm050 APIs + * BMC150 - Combination of bma2x2 + bmm050 APIs + * BMC056 - Combination of bma2x2 + bmm050 APIs + +### Version +- Version of bma2x2 sensor driver is: + +Driver files | Version +-----------------|--------- +bma2x2.c | 2.0.7 +bma2x2.h | 2.0.7 +bma2x2_support.c | 1.0.4 + +### Integration details +- Integrate bma2x2.h and bma2x2.c file in to your project. +- The bma2x2_support.c file contains only examples for API use cases, so it is not required to integrate into project. + +### Driver files information +- bma2x2.h + - This header file has the register address definition, constant definitions, data type definition and supported sensor driver calls declarations. +- bma2x2.c + - This file contains the implementation for the sensor driver APIs. +- bma2x2_support.c + - This file shall be used as an user guidance, here you can find samples of + - Initialize the sensor with I2C/SPI communication + - Add your code to the SPI and/or I2C bus read and bus write functions. + - Return value can be chosen by yourself + - API just passes that value to your application code + - Add your code to the delay function + - Change I2C address accordingly in bma2x2.h + - Power mode configuration of the sensor + - Get and set functions usage + - Reading the sensor read out data + +### Supported sensor interface +- This accelerometer sensor driver supports SPI and I2C interfaces + +### Copyright +- Copyright (C) 2015 - 2016 Bosch Sensortec GmbH + diff --git a/bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMA2x2_driver/bma2x2.c b/bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMA2x2_driver/bma2x2.c new file mode 100644 index 0000000000000000000000000000000000000000..f7fbee1b1b7f371daccc250be3d653d16ddd68da --- /dev/null +++ b/bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMA2x2_driver/bma2x2.c @@ -0,0 +1,9499 @@ +/*! +**************************************************************************** +* Copyright (C) 2015 - 2016 Bosch Sensortec GmbH +* +* bma2x2.c +* Date: 2016/11/14 +* Revision: 2.0.7 $ +* +* Usage: Sensor Driver for BMA2x2 sensor +* +**************************************************************************** +* Disclaimer +* +* Common: +* Bosch Sensortec products are developed for the consumer goods industry. +* They may only be used within the parameters of the respective valid +* product data sheet. Bosch Sensortec products are provided with the +* express understanding that there is no warranty of fitness for a +* particular purpose.They are not fit for use in life-sustaining, +* safety or security sensitive systems or any system or device +* that may lead to bodily harm or property damage if the system +* or device malfunctions. In addition,Bosch Sensortec products are +* not fit for use in products which interact with motor vehicle systems. +* The resale and or use of products are at the purchasers own risk and +* his own responsibility. The examination of fitness for the intended use +* is the sole responsibility of the Purchaser. +* +* The purchaser shall indemnify Bosch Sensortec from all third party +* claims, including any claims for incidental, or consequential damages, +* arising from any product use not covered by the parameters of +* the respective valid product data sheet or not approved by +* Bosch Sensortec and reimburse Bosch Sensortec for all costs in +* connection with such claims. +* +* The purchaser must monitor the market for the purchased products, +* particularly with regard to product safety and inform Bosch Sensortec +* without delay of all security relevant incidents. +* +* Engineering Samples are marked with an asterisk (*) or (e). +* Samples may vary from the valid technical specifications of the product +* series. They are therefore not intended or fit for resale to third +* parties or for use in end products. Their sole purpose is internal +* client testing. The testing of an engineering sample may in no way +* replace the testing of a product series. Bosch Sensortec assumes +* no liability for the use of engineering samples. +* By accepting the engineering samples, the Purchaser agrees to indemnify +* Bosch Sensortec from all claims arising from the use of engineering +* samples. +* +* Special: +* This software module (hereinafter called "Software") and any information +* on application-sheets (hereinafter called "Information") is provided +* free of charge for the sole purpose to support your application work. +* The Software and Information is subject to the following +* terms and conditions: +* +* The Software is specifically designed for the exclusive use for +* Bosch Sensortec products by personnel who have special experience +* and training. Do not use this Software if you do not have the +* proper experience or training. +* +* This Software package is provided `` as is `` and without any expressed +* or implied warranties,including without limitation, the implied warranties +* of merchantability and fitness for a particular purpose. +* +* Bosch Sensortec and their representatives and agents deny any liability +* for the functional impairment +* of this Software in terms of fitness, performance and safety. +* Bosch Sensortec and their representatives and agents shall not be liable +* for any direct or indirect damages or injury, except as +* otherwise stipulated in mandatory applicable law. +* +* The Information provided is believed to be accurate and reliable. +* Bosch Sensortec assumes no responsibility for the consequences of use +* of such Information nor for any infringement of patents or +* other rights of third parties which may result from its use. +* No license is granted by implication or otherwise under any patent or +* patent rights of Bosch. Specifications mentioned in the Information are +* subject to change without notice. +**************************************************************************/ +/*! file + brief */ +#include "bma2x2.h" +/*! user defined code to be added here ... */ +static struct bma2x2_t *p_bma2x2; +/*! Based on Bit resolution value_u8 should be modified */ +//u8 V_BMA2x2RESOLUTION_U8 = BMA2x2_14_RESOLUTION; +u8 V_BMA2x2RESOLUTION_U8 = BMA2x2_12_RESOLUTION; + +/****************************************************************************/ +/*! Static Function Declarations +*****************************************************************************/ +/*! + * @brief This API computes the number of bytes of accel FIFO data + * which is to be parsed. + * + * @param[out] data_index : The start index for parsing data + * @param[out] data_read_length : No of bytes to be parsed from FIFO buffer + * @param[in] accel_frame_count : Number of accelerometer frames to be read + * @param[in] fifo_data_select : Denoting enabled axes data stored in FIFO + * @param[in] fifo_conf : FIFO configuration structure + * + */ +static void get_accel_len_to_parse(u8 *data_index, u8 *data_read_length, + u8 accel_frame_count, u8 fifo_data_select, + struct fifo_configuration *fifo_conf); + +/*! + * @brief This API is used to parse the accelerometer frame from the + * user defined FIFO data buffer mapped to the structure fifo_conf and store + * it in the union fifo_frame + * + * @note It update the data_index value which is used to store the index of + * the current data byte which is parsed. + * + * @note The parsed accel frames stored in the union fifo_conf contains data + * in accordance with the enabled data axes to be stored in FIFO + * (XYZ axes or individual axis) + * + * @param[in,out] accel_frame : Instance of union fifo_frame + * @param[in,out] data_index : Index value of noumber of bytes parsed + * @param[in,out] accel_index : Index value of accelerometer frame parsed + * @param[in] fifo_data_select : Denoting enabled axes data stored in FIFO + * @param[in] fifo_conf : FIFO configuration structure + * + */ +static void unpack_accel_frame(union fifo_frame *accel_frame, u8 *data_index, + u8 *accel_index, u8 fifo_data_select, + struct fifo_configuration *fifo_conf); + +/*! + * @brief This API is used to parse the accelerometer data and + * store it in the union fifo_frame + * It also updates the data_index value which stores the index of + * the current data byte which is parsed + * + * @param[in,out] accel_frame : Instance of union fifo_frame + * @param[in,out] data_index : Index value of noumber of bytes parsed + * @param[in] fifo_conf : FIFO configuration structure + * + */ +static void unpack_accel_xyz(union fifo_frame *accel_frame, u8 *data_index, + struct fifo_configuration *fifo_conf); +/*! + * @brief + * This API reads the data from + * the given register continuously + * + * + * @param addr_u8 -> Address of the register + * @param data_u8 -> The data from the register + * @param len_u32 -> no of bytes to read + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_burst_read(u8 addr_u8, + u8 *data_u8, u32 len_u32) +{ + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* Read the data from the register*/ + com_rslt = p_bma2x2->BMA2x2_BURST_READ_FUNC + (p_bma2x2->dev_addr, addr_u8, data_u8, len_u32); + } + return com_rslt; +} +/*! + * @brief + * This function is used for initialize + * bus read and bus write functions + * assign the chip id and device address + * chip id is read in the register 0x00 bit from 0 to 7 + * + * @param bma2x2 : structure pointer + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * @note + * While changing the parameter of the bma2x2_t + * consider the following point: + * Changing the reference value of the parameter + * will changes the local copy or local reference + * make sure your changes will not + * affect the reference value of the parameter + * (Better case don't change the reference value of the parameter) + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_init(struct bma2x2_t *bma2x2) +{ + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 data_u8 = BMA2x2_INIT_VALUE; + u8 config_data_u8 = BMA2x2_INIT_VALUE; + /* assign bma2x2 ptr */ + p_bma2x2 = bma2x2; + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + com_rslt = E_BMA2x2_NULL_PTR; + } + else + { + /* read Chip Id */ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_CHIP_ID_REG, &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + p_bma2x2->chip_id = data_u8; /* get bit slice */ + /* read the fifo config register and update + the value to the fifo_config*/ + com_rslt += bma2x2_read_reg(BMA2x2_FIFO_MODE_REG, + &config_data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + p_bma2x2->fifo_config = config_data_u8; + } + return com_rslt; +} +/*! + * @brief + * This API gives data to the given register and + * the data is written in the corresponding register address + * + * + * @param adr_u8 -> Address of the register + * @param data_u8 -> The data to the register + * @param len_u8 -> no of bytes to read + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_write_reg(u8 adr_u8, + u8 *data_u8, u8 len_u8) +{ + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* Write the data to the register*/ + com_rslt = p_bma2x2->BMA2x2_BUS_WRITE_FUNC + (p_bma2x2->dev_addr, adr_u8, data_u8, len_u8); + + if (p_bma2x2->power_mode_u8 != BMA2x2_MODE_NORMAL) + { + /*A minimum interface idle time delay + of atleast 450us is required as per the data sheet.*/ + p_bma2x2->delay_msec(BMA2x2_INTERFACE_IDLE_TIME_DELAY); + } + } + return com_rslt; +} +/*! + * @brief This API reads the data from + * the given register address + * + * + * @param adr_u8 -> Address of the register + * @param data_u8 -> The data from the register + * @param len_u8 -> no of bytes to read + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_reg(u8 adr_u8, + u8 *data_u8, u8 len_u8) +{ + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /*Read the data from the register*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, adr_u8, data_u8, len_u8); + } + return com_rslt; +} +/*! + * @brief + * This API reads acceleration data X values + * from location 02h and 03h + * + * + * @param accel_x_s16 : pointer holding the data of accel X + * value | resolution + * ----------------- | -------------- + * 0 | BMA2x2_12_RESOLUTION + * 1 | BMA2x2_10_RESOLUTION + * 2 | BMA2x2_14_RESOLUTION + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_x(s16 *accel_x_s16) +{ + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + /* Array holding the accel x value + data_u8[0] - x->LSB + data_u8[1] - x->MSB + */ + u8 data_u8[BMA2x2_ACCEL_DATA_SIZE] = + { + BMA2x2_INIT_VALUE, BMA2x2_INIT_VALUE + }; + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + switch (V_BMA2x2RESOLUTION_U8) + { + /* This case used for the resolution bit 12*/ + case BMA2x2_12_RESOLUTION: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ACCEL_X12_LSB_REG, data_u8, + BMA2x2_LSB_MSB_READ_LENGTH); + *accel_x_s16 = (s16)((((s32)((s8) + data_u8[BMA2x2_SENSOR_DATA_ACCEL_MSB])) + << BMA2x2_SHIFT_EIGHT_BITS) | + (data_u8[BMA2x2_SENSOR_DATA_ACCEL_LSB] & + BMA2x2_RESOLUTION_12_MASK)); + *accel_x_s16 = *accel_x_s16 >> + BMA2x2_SHIFT_FOUR_BITS; + break; + /* This case used for the resolution bit 10*/ + case BMA2x2_10_RESOLUTION: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ACCEL_X10_LSB_REG, data_u8, + BMA2x2_LSB_MSB_READ_LENGTH); + *accel_x_s16 = (s16)((((s32)((s8) + data_u8[BMA2x2_SENSOR_DATA_ACCEL_MSB])) + << BMA2x2_SHIFT_EIGHT_BITS) | + (data_u8[BMA2x2_SENSOR_DATA_ACCEL_LSB] & + BMA2x2_RESOLUTION_10_MASK)); + *accel_x_s16 = *accel_x_s16 >> + BMA2x2_SHIFT_SIX_BITS; + break; + /* This case used for the resolution bit 14*/ + case BMA2x2_14_RESOLUTION: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ACCEL_X14_LSB_REG, data_u8, + BMA2x2_LSB_MSB_READ_LENGTH); + *accel_x_s16 = (s16)((((s32)((s8) + data_u8[BMA2x2_SENSOR_DATA_ACCEL_MSB])) + << BMA2x2_SHIFT_EIGHT_BITS) | + (data_u8[BMA2x2_SENSOR_DATA_ACCEL_LSB] & + BMA2x2_RESOLUTION_14_MASK)); + *accel_x_s16 = *accel_x_s16 >> + BMA2x2_SHIFT_TWO_BITS; + break; + default: + break; + } + } + return com_rslt; +} +/*! + * @brief + * This API reads acceleration data X values + * from location 02h and 03h bit resolution support 8bit + * + * + * @param accel_x_s8 : pointer holding the data of accel X + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_eight_resolution_x( + s8 *accel_x_s8) +{ + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 data = BMA2x2_INIT_VALUE; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* Read the sensor X data*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_X_AXIS_MSB_ADDR, &data, + BMA2x2_GEN_READ_WRITE_LENGTH); + *accel_x_s8 = BMA2x2_GET_BITSLICE(data, + BMA2x2_ACCEL_X_MSB); + } + return com_rslt; +} +/*! + * @brief + * This API reads acceleration data Y values + * from location 04h and 05h + * + * @param accel_y_s16 : pointer holding the data of accel Y + * value | resolution + * ----------------- | -------------- + * 0 | BMA2x2_12_RESOLUTION + * 1 | BMA2x2_10_RESOLUTION + * 2 | BMA2x2_14_RESOLUTION + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_y(s16 *accel_y_s16) +{ + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + /* Array holding the accel y value + data_u8[0] - y->LSB + data_u8[1] - y->MSB + */ + u8 data_u8[BMA2x2_ACCEL_DATA_SIZE] = {BMA2x2_INIT_VALUE, + BMA2x2_INIT_VALUE + }; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + switch (V_BMA2x2RESOLUTION_U8) + { + /* This case used for the resolution bit 12*/ + case BMA2x2_12_RESOLUTION: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ACCEL_Y12_LSB_REG, data_u8, + BMA2x2_LSB_MSB_READ_LENGTH); + *accel_y_s16 = (s16)((((s32)((s8) + data_u8[BMA2x2_SENSOR_DATA_ACCEL_MSB])) + << BMA2x2_SHIFT_EIGHT_BITS) | + (data_u8[BMA2x2_SENSOR_DATA_ACCEL_LSB] & + BMA2x2_12_BIT_SHIFT)); + *accel_y_s16 = *accel_y_s16 >> + BMA2x2_SHIFT_FOUR_BITS; + break; + /* This case used for the resolution bit 10*/ + case BMA2x2_10_RESOLUTION: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ACCEL_Y10_LSB_REG, data_u8, + BMA2x2_LSB_MSB_READ_LENGTH); + *accel_y_s16 = (s16)((((s32)((s8) + data_u8[BMA2x2_SENSOR_DATA_ACCEL_MSB])) + << BMA2x2_SHIFT_EIGHT_BITS) | + (data_u8[BMA2x2_SENSOR_DATA_ACCEL_LSB] & + BMA2x2_10_BIT_SHIFT)); + *accel_y_s16 = *accel_y_s16 >> + BMA2x2_SHIFT_SIX_BITS; + break; + /* This case used for the resolution bit 14*/ + case BMA2x2_14_RESOLUTION: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ACCEL_Y14_LSB_REG, data_u8, + BMA2x2_LSB_MSB_READ_LENGTH); + *accel_y_s16 = (s16)((((s32)((s8) + data_u8[BMA2x2_SENSOR_DATA_ACCEL_MSB])) + << BMA2x2_SHIFT_EIGHT_BITS) | + (data_u8[BMA2x2_SENSOR_DATA_ACCEL_LSB] & + BMA2x2_14_BIT_SHIFT)); + *accel_y_s16 = *accel_y_s16 >> + BMA2x2_SHIFT_TWO_BITS; + break; + default: + break; + } + } + return com_rslt; +} +/*! + * @brief This API reads acceleration data Y values of + * 8bit resolution from location 05h + * + * + * + * + * @param accel_y_s8 The data of y + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_eight_resolution_y( + s8 *accel_y_s8) +{ + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 data = BMA2x2_INIT_VALUE; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_Y_AXIS_MSB_ADDR, &data, + BMA2x2_GEN_READ_WRITE_LENGTH); + *accel_y_s8 = BMA2x2_GET_BITSLICE(data, + BMA2x2_ACCEL_Y_MSB); + } + return com_rslt; +} +/*! + * @brief This API reads acceleration data Z values + * from location 06h and 07h + * + * + * @param accel_z_s16 : pointer holding the data of accel Z + * value | resolution + * ----------------- | -------------- + * 0 | BMA2x2_12_RESOLUTION + * 1 | BMA2x2_10_RESOLUTION + * 2 | BMA2x2_14_RESOLUTION + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_z(s16 *accel_z_s16) +{ + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + /* Array holding the accel z value + data_u8[0] - z->LSB + data_u8[1] - z->MSB + */ + u8 data_u8[BMA2x2_ACCEL_DATA_SIZE] = {BMA2x2_INIT_VALUE, + BMA2x2_INIT_VALUE + }; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + switch (V_BMA2x2RESOLUTION_U8) + { + case BMA2x2_12_RESOLUTION: + /* This case used for the resolution bit 12*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ACCEL_Z12_LSB_REG, data_u8, + BMA2x2_LSB_MSB_READ_LENGTH); + *accel_z_s16 = (s16)((((s32)((s8) + data_u8[BMA2x2_SENSOR_DATA_ACCEL_MSB])) + << BMA2x2_SHIFT_EIGHT_BITS) | + (data_u8[BMA2x2_SENSOR_DATA_ACCEL_LSB] + & BMA2x2_12_BIT_SHIFT)); + *accel_z_s16 = *accel_z_s16 >> + BMA2x2_SHIFT_FOUR_BITS; + break; + /* This case used for the resolution bit 10*/ + case BMA2x2_10_RESOLUTION: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ACCEL_Z10_LSB_REG, data_u8, + BMA2x2_LSB_MSB_READ_LENGTH); + *accel_z_s16 = (s16)((((s32)((s8) + data_u8[BMA2x2_SENSOR_DATA_ACCEL_MSB])) + << BMA2x2_SHIFT_EIGHT_BITS) | + (data_u8[BMA2x2_SENSOR_DATA_ACCEL_LSB] + & BMA2x2_10_BIT_SHIFT)); + *accel_z_s16 = *accel_z_s16 >> + BMA2x2_SHIFT_SIX_BITS; + break; + /* This case used for the resolution bit 14*/ + case BMA2x2_14_RESOLUTION: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ACCEL_Z14_LSB_REG, data_u8, + BMA2x2_LSB_MSB_READ_LENGTH); + *accel_z_s16 = (s16)((((s32)((s8) + data_u8[BMA2x2_SENSOR_DATA_ACCEL_MSB])) + << BMA2x2_SHIFT_EIGHT_BITS) | + (data_u8[BMA2x2_SENSOR_DATA_ACCEL_LSB] + & BMA2x2_14_BIT_SHIFT)); + *accel_z_s16 = *accel_z_s16 >> + BMA2x2_SHIFT_TWO_BITS; + break; + default: + break; + } + } + return com_rslt; +} +/*! + * @brief + * This API reads acceleration data Z values of + * 8bit resolution from location 07h + * + * + * + * + * \@aram accel_z_s8 : the data of z + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_eight_resolution_z( + s8 *accel_z_s8) +{ + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 data = BMA2x2_INIT_VALUE; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_Z_AXIS_MSB_ADDR, &data, + BMA2x2_GEN_READ_WRITE_LENGTH); + *accel_z_s8 = BMA2x2_GET_BITSLICE(data, + BMA2x2_ACCEL_Z_MSB); + } + return com_rslt; +} +/*! + * @brief This API reads acceleration data X,Y,Z values + * from location 02h to 07h + * + * @param accel : pointer holding the data of accel + * value | resolution + * ----------------- | -------------- + * 0 | BMA2x2_12_RESOLUTION + * 1 | BMA2x2_10_RESOLUTION + * 2 | BMA2x2_14_RESOLUTION + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_xyz( + struct bma2x2_accel_data *accel) +{ + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + /* Array holding the accel xyz value + data_u8[0] - x->LSB + data_u8[1] - x->MSB + data_u8[2] - y->MSB + data_u8[3] - y->MSB + data_u8[4] - z->MSB + data_u8[5] - z->MSB + */ + u8 data_u8[BMA2x2_ACCEL_XYZ_DATA_SIZE] = + { + BMA2x2_INIT_VALUE, BMA2x2_INIT_VALUE, + BMA2x2_INIT_VALUE, BMA2x2_INIT_VALUE, + BMA2x2_INIT_VALUE, BMA2x2_INIT_VALUE + }; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + switch (V_BMA2x2RESOLUTION_U8) + { + /* This case used for the resolution bit 12*/ + case BMA2x2_12_RESOLUTION: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, BMA2x2_ACCEL_X12_LSB_REG, + data_u8, BMA2x2_SHIFT_SIX_BITS); + /* read the x data_u8*/ + accel->x = (s16)((((s32)((s8) + data_u8[BMA2x2_SENSOR_DATA_XYZ_X_MSB])) + << BMA2x2_SHIFT_EIGHT_BITS) | + (data_u8[BMA2x2_SENSOR_DATA_XYZ_X_LSB] & + BMA2x2_12_BIT_SHIFT)); + accel->x = accel->x >> BMA2x2_SHIFT_FOUR_BITS; + + /* read the y data_u8*/ + accel->y = (s16)((((s32)((s8) + data_u8[BMA2x2_SENSOR_DATA_XYZ_Y_MSB])) + << BMA2x2_SHIFT_EIGHT_BITS) | + (data_u8[BMA2x2_SENSOR_DATA_XYZ_Y_LSB] & + BMA2x2_12_BIT_SHIFT)); + accel->y = accel->y >> BMA2x2_SHIFT_FOUR_BITS; + + /* read the z data_u8*/ + accel->z = (s16)((((s32)((s8) + data_u8[BMA2x2_SENSOR_DATA_XYZ_Z_MSB])) + << BMA2x2_SHIFT_EIGHT_BITS) | + (data_u8[BMA2x2_SENSOR_DATA_XYZ_Z_LSB] & + BMA2x2_12_BIT_SHIFT)); + accel->z = accel->z >> BMA2x2_SHIFT_FOUR_BITS; + + break; + case BMA2x2_10_RESOLUTION: + /* This case used for the resolution bit 10*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, BMA2x2_ACCEL_X10_LSB_REG, + data_u8, BMA2x2_SHIFT_SIX_BITS); + /* read the x data_u8*/ + accel->x = (s16)((((s32)((s8) + data_u8[BMA2x2_SENSOR_DATA_XYZ_X_MSB])) + << BMA2x2_SHIFT_EIGHT_BITS) | + (data_u8[BMA2x2_SENSOR_DATA_XYZ_X_LSB] & + BMA2x2_10_BIT_SHIFT)); + accel->x = accel->x >> BMA2x2_SHIFT_SIX_BITS; + + /* read the y data_u8*/ + accel->y = (s16)((((s32)((s8) + data_u8[BMA2x2_SENSOR_DATA_XYZ_Y_MSB])) + << BMA2x2_SHIFT_EIGHT_BITS) | + (data_u8[BMA2x2_SENSOR_DATA_XYZ_Y_LSB] & + BMA2x2_10_BIT_SHIFT)); + accel->y = accel->y >> BMA2x2_SHIFT_SIX_BITS; + + /* read the z data_u8*/ + accel->z = (s16)((((s32)((s8) + data_u8[BMA2x2_SENSOR_DATA_XYZ_Z_MSB])) + << BMA2x2_SHIFT_EIGHT_BITS) | + (data_u8[BMA2x2_SENSOR_DATA_XYZ_Z_LSB] + & BMA2x2_10_BIT_SHIFT)); + accel->z = accel->z >> BMA2x2_SHIFT_SIX_BITS; + break; + /* This case used for the resolution bit 14*/ + case BMA2x2_14_RESOLUTION: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, BMA2x2_ACCEL_X14_LSB_REG, + data_u8, BMA2x2_SHIFT_SIX_BITS); + + /* read the x data_u8*/ + accel->x = (s16)((((s32)((s8) + data_u8[BMA2x2_SENSOR_DATA_XYZ_X_MSB])) << + BMA2x2_SHIFT_EIGHT_BITS) | + (data_u8[BMA2x2_SENSOR_DATA_XYZ_X_LSB] + & BMA2x2_14_BIT_SHIFT)); + accel->x = accel->x >> BMA2x2_SHIFT_TWO_BITS; + + /* read the y data_u8*/ + accel->y = (s16)((((s32)((s8) + data_u8[BMA2x2_SENSOR_DATA_XYZ_Y_MSB])) << + BMA2x2_SHIFT_EIGHT_BITS) | + (data_u8[BMA2x2_SENSOR_DATA_XYZ_Y_LSB] + & BMA2x2_14_BIT_SHIFT)); + accel->y = accel->y >> BMA2x2_SHIFT_TWO_BITS; + + /* read the z data_u8*/ + accel->z = (s16)((((s32)((s8) + data_u8[BMA2x2_SENSOR_DATA_XYZ_Z_MSB])) << + BMA2x2_SHIFT_EIGHT_BITS) | + (data_u8[BMA2x2_SENSOR_DATA_XYZ_Z_LSB] + & BMA2x2_14_BIT_SHIFT)); + accel->z = accel->z >> BMA2x2_SHIFT_TWO_BITS; + break; + default: + break; + } + } + return com_rslt; +} +/*! + * @brief This API reads acceleration of 8 bit resolution + * data of X,Y,Z values + * from location 03h , 05h and 07h + * + * + * + * + * @param accel : pointer holding the data of accel + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_eight_resolution_xyz( + struct bma2x2_accel_eight_resolution *accel) +{ + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 data_u8 = BMA2x2_INIT_VALUE; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_X_AXIS_MSB_ADDR, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + accel->x = BMA2x2_GET_BITSLICE(data_u8, + BMA2x2_ACCEL_X_MSB); + + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_Y_AXIS_MSB_ADDR, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + accel->y = BMA2x2_GET_BITSLICE(data_u8, + BMA2x2_ACCEL_Y_MSB); + + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_Z_AXIS_MSB_ADDR, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + accel->z = BMA2x2_GET_BITSLICE(data_u8, + BMA2x2_ACCEL_Z_MSB); + } + return com_rslt; +} +/*! + * @brief This API read tap-sign, tap-first-xyz + * slope-sign, slope-first-xyz status register byte + * from location 0Bh + * + * @param stat_tap_u8 : The status of tap and slope + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_tap_stat( + u8 *stat_tap_u8) +{ + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* Read the interrupt status register 0x0B*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, BMA2x2_STAT_TAP_SLOPE_ADDR, + stat_tap_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + } + return com_rslt; +} +/*! + * @brief This API read orient, high-sign and high-first-xyz + * status register byte from location 0Ch + * + * + * @param stat_orient_u8 : The status of orient and high + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_orient_stat( + u8 *stat_orient_u8) +{ + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* Read the interrupt status register 0x0C*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, BMA2x2_STAT_ORIENT_HIGH_ADDR, + stat_orient_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + } + return com_rslt; +} +/*! + * @brief This API reads fifo overrun and fifo frame counter + * status register byte from location 0Eh + * + * @param stat_fifo_u8 : The status of fifo overrun and frame counter + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_fifo_stat( + u8 *stat_fifo_u8) +{ + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* Read the interrupt status register 0x0E*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC( + p_bma2x2->dev_addr, + BMA2x2_STAT_FIFO_ADDR, + stat_fifo_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + } + return com_rslt; +} +/*! + * @brief This API read fifo frame count + * from location 0Eh bit position 0 to 6 + * + * + * @param frame_count_u8 : The status of fifo frame count + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_fifo_frame_count( + u8 *frame_count_u8) +{ + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 data_u8 = BMA2x2_INIT_VALUE; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* Read the FIFO frame count*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC( + p_bma2x2->dev_addr, + BMA2x2_FIFO_FRAME_COUNT_STAT_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *frame_count_u8 = BMA2x2_GET_BITSLICE(data_u8, + BMA2x2_FIFO_FRAME_COUNT_STAT); + } + return com_rslt; +} +/*! + * @brief This API read fifo overrun + * from location 0Eh bit position 7 + * + * + * @param fifo_overrun_u8 : The status of fifo overrun + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_fifo_overrun( + u8 *fifo_overrun_u8) +{ + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 data_u8 = BMA2x2_INIT_VALUE; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* Read the status of fifo over run*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC( + p_bma2x2->dev_addr, + BMA2x2_FIFO_OVERRUN_STAT_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *fifo_overrun_u8 = BMA2x2_GET_BITSLICE(data_u8, + BMA2x2_FIFO_OVERRUN_STAT); + } + return com_rslt; +} +/*! + * @brief This API read interrupt status of flat, orient, single tap, + * double tap, slow no motion, slope, highg and lowg from location 09h + * + * + * + * @param intr_stat_u8 : The value of interrupt status + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_stat( + u8 *intr_stat_u8) +{ + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* Read the interrupt status register 0x09*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC( + p_bma2x2->dev_addr, + BMA2x2_STAT1_ADDR, intr_stat_u8, + BMA2x2_SHIFT_FOUR_BITS); + } + return com_rslt; +} +/*! + * @brief This API is used to get the ranges(g values) of the sensor + * in the register 0x0F bit from 0 to 3 + * + * + * @param range_u8 : The value of range + * range_u8 | result + * ----------------- | -------------- + * 0x03 | BMA2x2_RANGE_2G + * 0x05 | BMA2x2_RANGE_4G + * 0x08 | BMA2x2_RANGE_8G + * 0x0C | BMA2x2_RANGE_16G + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_range(u8 *range_u8) +{ + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 data_u8 = BMA2x2_INIT_VALUE; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* Read the range register 0x0F*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC(p_bma2x2->dev_addr, + BMA2x2_RANGE_SELECT_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_GET_BITSLICE(data_u8, BMA2x2_RANGE_SELECT); + *range_u8 = data_u8; + } + return com_rslt; +} +/*! + * @brief This API is used to set the ranges(g values) of the sensor + * in the register 0x0F bit from 0 to 3 + * + * + * @param range_u8 : The value of range + * range_u8 | result + * ----------------- | -------------- + * 0x03 | BMA2x2_RANGE_2G + * 0x05 | BMA2x2_RANGE_4G + * 0x08 | BMA2x2_RANGE_8G + * 0x0C | BMA2x2_RANGE_16G + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_range(u8 range_u8) +{ + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 data_u8 = BMA2x2_INIT_VALUE; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + if ((range_u8 == BMA2x2_RANGE_2G) || + (range_u8 == BMA2x2_RANGE_4G) || + (range_u8 == BMA2x2_RANGE_8G) || + (range_u8 == BMA2x2_RANGE_16G)) + { + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_RANGE_SELECT_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + switch (range_u8) + { + case BMA2x2_RANGE_2G: + data_u8 = BMA2x2_SET_BITSLICE(data_u8, + BMA2x2_RANGE_SELECT, + BMA2x2_RANGE_2G); + break; + case BMA2x2_RANGE_4G: + data_u8 = BMA2x2_SET_BITSLICE(data_u8, + BMA2x2_RANGE_SELECT, + BMA2x2_RANGE_4G); + break; + case BMA2x2_RANGE_8G: + data_u8 = BMA2x2_SET_BITSLICE(data_u8, + BMA2x2_RANGE_SELECT, + BMA2x2_RANGE_8G); + break; + case BMA2x2_RANGE_16G: + data_u8 = BMA2x2_SET_BITSLICE(data_u8, + BMA2x2_RANGE_SELECT, + BMA2x2_RANGE_16G); + break; + default: + break; + } + /* Write the range register 0x0F*/ + com_rslt += bma2x2_write_reg(BMA2x2_RANGE_SELECT_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + } + else + { + com_rslt = E_OUT_OF_RANGE; + } + } + return com_rslt; +} +/*! + * @brief This API is used to get the bandwidth of the sensor in the register + * 0x10 bit from 0 to 4 + * + * + * @param bw_u8 : The value of bandwidth + * bw_u8 | result + * ----------------- | -------------- + * 0x08 | BMA2x2_BW_7_81HZ + * 0x09 | BMA2x2_BW_15_63HZ + * 0x0A | BMA2x2_BW_31_25HZ + * 0x0B | BMA2x2_BW_62_50HZ + * 0x0C | BMA2x2_BW_125HZ + * 0x0D | BMA2x2_BW_250HZ + * 0x0E | BMA2x2_BW_500HZ + * 0x0F | BMA2x2_BW_1000HZ + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_bw(u8 *bw_u8) +{ + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 data_u8 = BMA2x2_INIT_VALUE; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* Read the bandwidth register 0x10*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_BW_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_GET_BITSLICE(data_u8, BMA2x2_BW); + *bw_u8 = data_u8; + } + return com_rslt; +} +/*! + * @brief This API is used to set the bandwidth of the sensor + * in the register + * 0x10 bit from 0 to 4 + * + * + * @param bw_u8 : The value of bandwidth + * bw_u8 | result + * ----------------- | -------------- + * 0x08 | BMA2x2_BW_7_81HZ + * 0x09 | BMA2x2_BW_15_63HZ + * 0x0A | BMA2x2_BW_31_25HZ + * 0x0B | BMA2x2_BW_62_50HZ + * 0x0C | BMA2x2_BW_125HZ + * 0x0D | BMA2x2_BW_250HZ + * 0x0E | BMA2x2_BW_500HZ + * 0x0F | BMA2x2_BW_1000HZ + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_bw(u8 bw_u8) +{ + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 data_u8 = BMA2x2_INIT_VALUE; + u8 data_bw_u8 = BMA2x2_INIT_VALUE; + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + com_rslt = E_BMA2x2_NULL_PTR; + } + else + { + /* Check the chip id 0xFB, it support upto 500Hz*/ + if (p_bma2x2->chip_id == BANDWIDTH_DEFINE) + { + if (bw_u8 > BMA2x2_ACCEL_BW_MIN_RANGE && + bw_u8 < BMA2x2_ACCEL_BW_1000HZ_RANGE) + { + switch (bw_u8) + { + case BMA2x2_BW_7_81HZ: + data_bw_u8 = BMA2x2_BW_7_81HZ; + + /* 7.81 Hz 64000 uS */ + break; + case BMA2x2_BW_15_63HZ: + data_bw_u8 = BMA2x2_BW_15_63HZ; + + /* 15.63 Hz 32000 uS */ + break; + case BMA2x2_BW_31_25HZ: + data_bw_u8 = BMA2x2_BW_31_25HZ; + + /* 31.25 Hz 16000 uS */ + break; + case BMA2x2_BW_62_50HZ: + data_bw_u8 = BMA2x2_BW_62_50HZ; + + /* 62.50 Hz 8000 uS */ + break; + case BMA2x2_BW_125HZ: + data_bw_u8 = BMA2x2_BW_125HZ; + + /* 125 Hz 4000 uS */ + break; + case BMA2x2_BW_250HZ: + data_bw_u8 = BMA2x2_BW_250HZ; + + /* 250 Hz 2000 uS */ + break; + case BMA2x2_BW_500HZ: + data_bw_u8 = BMA2x2_BW_500HZ; + + /* 500 Hz 1000 uS */ + break; + default: + break; + } + /* Write the bandwidth register */ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_BW_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE(data_u8, + BMA2x2_BW, data_bw_u8); + com_rslt += bma2x2_write_reg + (BMA2x2_BW_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + } + else + { + com_rslt = E_OUT_OF_RANGE; + } + } + else + { + if (bw_u8 > BMA2x2_ACCEL_BW_MIN_RANGE && + bw_u8 < BMA2x2_ACCEL_BW_MAX_RANGE) + { + switch (bw_u8) + { + case BMA2x2_BW_7_81HZ: + data_bw_u8 = BMA2x2_BW_7_81HZ; + + /* 7.81 Hz 64000 uS */ + break; + case BMA2x2_BW_15_63HZ: + data_bw_u8 = BMA2x2_BW_15_63HZ; + + /* 15.63 Hz 32000 uS */ + break; + case BMA2x2_BW_31_25HZ: + data_bw_u8 = BMA2x2_BW_31_25HZ; + + /* 31.25 Hz 16000 uS */ + break; + case BMA2x2_BW_62_50HZ: + data_bw_u8 = BMA2x2_BW_62_50HZ; + + /* 62.50 Hz 8000 uS */ + break; + case BMA2x2_BW_125HZ: + data_bw_u8 = BMA2x2_BW_125HZ; + + /* 125 Hz 4000 uS */ + break; + case BMA2x2_BW_250HZ: + data_bw_u8 = BMA2x2_BW_250HZ; + + /* 250 Hz 2000 uS */ + break; + case BMA2x2_BW_500HZ: + data_bw_u8 = BMA2x2_BW_500HZ; + + /*! 500 Hz 1000 uS */ + break; + case BMA2x2_BW_1000HZ: + data_bw_u8 = BMA2x2_BW_1000HZ; + + /* 1000 Hz 500 uS */ + break; + default: + break; + } + /* Write the bandwidth register */ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_BW_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_BW, data_bw_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_BW_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + } + else + { + com_rslt = E_OUT_OF_RANGE; + } + } + } + return com_rslt; +} +/*! + * @brief This API is used to get the operating + * modes of the sensor in the register 0x11 and 0x12 + * @note Register 0x11 - bit from 5 to 7 + * @note Register 0x12 - bit from 5 and 6 + * + * + * @param power_mode_u8 : The value of power mode + * power_mode_u8 |value | 0x11 | 0x12 + * ------------------------- |-------| --------|-------- + * BMA2x2_MODE_NORMAL | 0 | 0x00 | 0x00 + * BMA2x2_MODE_LOWPOWER1 | 1 | 0x02 | 0x00 + * BMA2x2_MODE_SUSPEND | 2 | 0x06 | 0x00 + * BMA2x2_MODE_DEEP_SUSPEND | 3 | 0x01 | 0x00 + * BMA2x2_MODE_LOWPOWER2 | 4 | 0x02 | 0x01 + * BMA2x2_MODE_STANDBY | 5 | 0x04 | 0x00 + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_power_mode( + u8 *power_mode_u8) +{ + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 data_u8 = BMA2x2_INIT_VALUE; + u8 data2_u8 = BMA2x2_INIT_VALUE; + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + com_rslt = E_BMA2x2_NULL_PTR; + } + else + { + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, BMA2x2_MODE_CTRL_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + com_rslt += p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, BMA2x2_LOW_NOISE_CTRL_ADDR, + &data2_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + + data_u8 = (data_u8 & + BMA2x2_POWER_MODE_HEX_E_ZERO_MASK) >> + BMA2x2_SHIFT_FIVE_BITS; + data2_u8 = (data2_u8 & + BMA2x2_POWER_MODE_HEX_4_ZERO_MASK) >> + BMA2x2_SHIFT_SIX_BITS; + + if ((data_u8 == + BMA2x2_POWER_MODE_HEX_ZERO_ZERO_MASK) && + (data2_u8 == + BMA2x2_POWER_MODE_HEX_ZERO_ZERO_MASK)) + { + *power_mode_u8 = BMA2x2_MODE_NORMAL; + } + else + { + if ((data_u8 == + BMA2x2_POWER_MODE_HEX_ZERO_TWO_MASK) && + (data2_u8 == + BMA2x2_POWER_MODE_HEX_ZERO_ZERO_MASK)) + { + *power_mode_u8 = + BMA2x2_MODE_LOWPOWER1; + } + else + { + if ((data_u8 == + BMA2x2_POWER_MODE_HEX_ZERO_FOUR_MASK + || data_u8 == + BMA2x2_POWER_MODE_HEX_ZERO_SIX_MASK) && + (data2_u8 == + BMA2x2_POWER_MODE_HEX_ZERO_ZERO_MASK)) + { + *power_mode_u8 = + BMA2x2_MODE_SUSPEND; + } + else + { + if (((data_u8 & + BMA2x2_POWER_MODE_HEX_ZERO_ONE_MASK) + == BMA2x2_POWER_MODE_HEX_ZERO_ONE_MASK)) + { + *power_mode_u8 = + BMA2x2_MODE_DEEP_SUSPEND; + } + else + { + if ((data_u8 == + BMA2x2_POWER_MODE_HEX_ZERO_TWO_MASK) + && (data2_u8 == + BMA2x2_POWER_MODE_HEX_ZERO_ONE_MASK)) + { + *power_mode_u8 = + BMA2x2_MODE_LOWPOWER2; + } + else + { + if ((data_u8 == + BMA2x2_POWER_MODE_HEX_ZERO_FOUR_MASK) && + (data2_u8 == + BMA2x2_POWER_MODE_HEX_ZERO_ONE_MASK)) + *power_mode_u8 = + BMA2x2_MODE_STANDBY; + else + *power_mode_u8 = + BMA2x2_MODE_DEEP_SUSPEND; + } + } + } + } + } + } + p_bma2x2->power_mode_u8 = *power_mode_u8; + return com_rslt; +} +/*! + * @brief This API is used to set the operating + * modes of the sensor in the register 0x11 and 0x12 + * @note Register 0x11 - bit from 5 to 7 + * @note Register 0x12 - bit from 5 and 6 + * + * + * @param power_mode_u8 : The value of power mode + * power_mode_u8 |value | 0x11 | 0x12 + * ------------------------- |-------| --------|-------- + * BMA2x2_MODE_NORMAL | 0 | 0x00 | 0x00 + * BMA2x2_MODE_LOWPOWER1 | 1 | 0x02 | 0x00 + * BMA2x2_MODE_SUSPEND | 2 | 0x06 | 0x00 + * BMA2x2_MODE_DEEP_SUSPEND | 3 | 0x01 | 0x00 + * BMA2x2_MODE_LOWPOWER2 | 4 | 0x02 | 0x01 + * BMA2x2_MODE_STANDBY | 5 | 0x04 | 0x00 + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_power_mode(u8 power_mode_u8) +{ + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 mode_ctr_eleven_reg = BMA2x2_INIT_VALUE; + u8 mode_ctr_twel_reg = BMA2x2_INIT_VALUE; + u8 data_u8 = BMA2x2_INIT_VALUE; + u8 data2_u8 = BMA2x2_INIT_VALUE; + u8 pre_fifo_config_data = BMA2x2_INIT_VALUE; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + com_rslt = E_BMA2x2_NULL_PTR; + } + else + { + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC(p_bma2x2->dev_addr, + BMA2x2_MODE_CTRL_REG, &data_u8, 1); + com_rslt += p_bma2x2->BMA2x2_BUS_READ_FUNC(p_bma2x2->dev_addr, + BMA2x2_LOW_POWER_MODE_REG, &data2_u8, 1); + + /* write the previous FIFO mode and data select*/ + pre_fifo_config_data = p_bma2x2->fifo_config; + pre_fifo_config_data |= 0x0C; + + com_rslt += bma2x2_set_mode_value(power_mode_u8); + mode_ctr_eleven_reg = p_bma2x2->ctrl_mode_reg; + mode_ctr_twel_reg = p_bma2x2->low_mode_reg; + + /* write the power mode to the register 0x12*/ + data2_u8 = BMA2x2_SET_BITSLICE(data2_u8, BMA2x2_LOW_POWER_MODE, + mode_ctr_twel_reg); + com_rslt += bma2x2_write_reg(BMA2x2_LOW_POWER_MODE_REG, + &data2_u8, 1); + + /*A minimum delay of atleast 450us is required for + the low power modes, as per the data sheet.*/ + p_bma2x2->delay_msec(BMA2x2_INTERFACE_IDLE_TIME_DELAY); + + if (((p_bma2x2->power_mode_u8 == BMA2x2_MODE_LOWPOWER1) || + (p_bma2x2->power_mode_u8 == BMA2x2_MODE_LOWPOWER2)) && + (power_mode_u8 == BMA2x2_MODE_NORMAL)) + { + /* Enter the power mode to suspend*/ + data_u8 = BMA2x2_SET_BITSLICE(data_u8, + BMA2x2_MODE_CTRL, BMA2x2_SHIFT_FOUR_BITS); + /* write the power mode to suspend*/ + com_rslt += bma2x2_write_reg( + BMA2x2_MODE_CTRL_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + /*re-write FIFO_CONFIG_0 register*/ + com_rslt += bma2x2_write_reg( + BMA2x2_FIFO_MODE_REG, &pre_fifo_config_data, 1); + } + + /* write the power mode to 0x11 register*/ + data_u8 = BMA2x2_SET_BITSLICE(data_u8, BMA2x2_MODE_CTRL, + mode_ctr_eleven_reg); + com_rslt += bma2x2_write_reg(BMA2x2_MODE_CTRL_REG, &data_u8, 1); + /*A minimum delay of atleast 450us is required for + the low power modes, as per the data sheet.*/ + p_bma2x2->delay_msec(BMA2x2_INTERFACE_IDLE_TIME_DELAY); + + com_rslt += bma2x2_write_reg(BMA2x2_FIFO_MODE_REG, + &pre_fifo_config_data, 1); + + /*Assigning the power mode to the global variable*/ + p_bma2x2->power_mode_u8 = power_mode_u8; + } + return com_rslt; +} +/*! + * @brief This API is used to assign the power mode values + * modes of the sensor in the register 0x11 and 0x12 + * @note Register 0x11 - bit from 5 to 7 + * @note Register 0x12 - bit from 5 and 6 + * + * + * @param power_mode_u8 : The value of power mode + * power_mode_u8 |value | 0x11 | 0x12 + * ------------------------- |-------| --------|-------- + * BMA2x2_MODE_NORMAL | 0 | 0x00 | 0x00 + * BMA2x2_MODE_LOWPOWER1 | 1 | 0x02 | 0x00 + * BMA2x2_MODE_SUSPEND | 2 | 0x06 | 0x00 + * BMA2x2_MODE_DEEP_SUSPEND | 3 | 0x01 | 0x00 + * BMA2x2_MODE_LOWPOWER2 | 4 | 0x02 | 0x01 + * BMA2x2_MODE_STANDBY | 5 | 0x04 | 0x00 + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_mode_value(u8 power_mode_u8) +{ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = SUCCESS; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + com_rslt = E_BMA2x2_NULL_PTR; + } + else + { + if (power_mode_u8 < BMA2x2_POWER_MODE_RANGE) + { + switch (power_mode_u8) + { + case BMA2x2_MODE_NORMAL: + p_bma2x2->ctrl_mode_reg = + BMA2x2_POWER_MODE_HEX_ZERO_ZERO_MASK; + p_bma2x2->low_mode_reg = + BMA2x2_POWER_MODE_HEX_ZERO_ZERO_MASK; + break; + case BMA2x2_MODE_LOWPOWER1: + p_bma2x2->ctrl_mode_reg = + BMA2x2_POWER_MODE_HEX_ZERO_TWO_MASK; + p_bma2x2->low_mode_reg = + BMA2x2_POWER_MODE_HEX_ZERO_ZERO_MASK; + break; + case BMA2x2_MODE_LOWPOWER2: + p_bma2x2->ctrl_mode_reg = + BMA2x2_POWER_MODE_HEX_ZERO_TWO_MASK; + p_bma2x2->low_mode_reg = + BMA2x2_POWER_MODE_HEX_ZERO_ONE_MASK; + break; + case BMA2x2_MODE_SUSPEND: + p_bma2x2->ctrl_mode_reg = + BMA2x2_POWER_MODE_HEX_ZERO_FOUR_MASK; + p_bma2x2->low_mode_reg = + BMA2x2_POWER_MODE_HEX_ZERO_ZERO_MASK; + break; + case BMA2x2_MODE_STANDBY: + p_bma2x2->ctrl_mode_reg = + BMA2x2_POWER_MODE_HEX_ZERO_FOUR_MASK; + p_bma2x2->low_mode_reg = + BMA2x2_POWER_MODE_HEX_ZERO_ONE_MASK; + break; + case BMA2x2_MODE_DEEP_SUSPEND: + p_bma2x2->ctrl_mode_reg = + BMA2x2_POWER_MODE_HEX_ZERO_ONE_MASK; + break; + } + } + else + { + com_rslt = E_OUT_OF_RANGE; + } + } + return com_rslt; +} +/*! + * @brief This API is used to get + * the sleep duration of the sensor in the register 0x11 + * Register 0x11 - bit from 0 to 3 + * + * + * @param sleep_durn_u8 : The value of sleep duration time + * sleep_durn_u8 | result + * ----------------- | ---------------------- + * 0x05 | BMA2x2_SLEEP_DURN_0_5MS + * 0x06 | BMA2x2_SLEEP_DURN_1MS + * 0x07 | BMA2x2_SLEEP_DURN_2MS + * 0x08 | BMA2x2_SLEEP_DURN_4MS + * 0x09 | BMA2x2_SLEEP_DURN_6MS + * 0x0A | BMA2x2_SLEEP_DURN_10MS + * 0x0B | BMA2x2_SLEEP_DURN_25MS + * 0x0C | BMA2x2_SLEEP_DURN_50MS + * 0x0D | BMA2x2_SLEEP_DURN_100MS + * 0x0E | BMA2x2_SLEEP_DURN_500MS + * 0x0F | BMA2x2_SLEEP_DURN_1S + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_sleep_durn(u8 *sleep_durn_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* read the sleep duration */ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, BMA2x2_SLEEP_DURN_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *sleep_durn_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_SLEEP_DURN); + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the sleep duration of the sensor in the register 0x11 + * Register 0x11 - bit from 0 to 3 + * + * + * + * + * @param sleep_durn_u8 : The value of sleep duration time + * sleep_durn_u8 | result + * ----------------- | ---------------------- + * 0x05 | BMA2x2_SLEEP_DURN_0_5MS + * 0x06 | BMA2x2_SLEEP_DURN_1MS + * 0x07 | BMA2x2_SLEEP_DURN_2MS + * 0x08 | BMA2x2_SLEEP_DURN_4MS + * 0x09 | BMA2x2_SLEEP_DURN_6MS + * 0x0A | BMA2x2_SLEEP_DURN_10MS + * 0x0B | BMA2x2_SLEEP_DURN_25MS + * 0x0C | BMA2x2_SLEEP_DURN_50MS + * 0x0D | BMA2x2_SLEEP_DURN_100MS + * 0x0E | BMA2x2_SLEEP_DURN_500MS + * 0x0F | BMA2x2_SLEEP_DURN_1S + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_sleep_durn(u8 sleep_durn_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 data_sleep_durn_u8 = BMA2x2_INIT_VALUE; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + if (sleep_durn_u8 > BMA2x2_SLEEP_DURN_MIN_RANGE && + sleep_durn_u8 < BMA2x2_SLEEP_DURN_MAX_RANGE) + { + switch (sleep_durn_u8) + { + case BMA2x2_SLEEP_DURN_0_5MS: + data_sleep_durn_u8 = BMA2x2_SLEEP_DURN_0_5MS; + + /* 0.5 MS */ + break; + case BMA2x2_SLEEP_DURN_1MS: + data_sleep_durn_u8 = BMA2x2_SLEEP_DURN_1MS; + + /* 1 MS */ + break; + case BMA2x2_SLEEP_DURN_2MS: + data_sleep_durn_u8 = BMA2x2_SLEEP_DURN_2MS; + + /* 2 MS */ + break; + case BMA2x2_SLEEP_DURN_4MS: + data_sleep_durn_u8 = BMA2x2_SLEEP_DURN_4MS; + + /* 4 MS */ + break; + case BMA2x2_SLEEP_DURN_6MS: + data_sleep_durn_u8 = BMA2x2_SLEEP_DURN_6MS; + + /* 6 MS */ + break; + case BMA2x2_SLEEP_DURN_10MS: + data_sleep_durn_u8 = BMA2x2_SLEEP_DURN_10MS; + + /* 10 MS */ + break; + case BMA2x2_SLEEP_DURN_25MS: + data_sleep_durn_u8 = BMA2x2_SLEEP_DURN_25MS; + + /* 25 MS */ + break; + case BMA2x2_SLEEP_DURN_50MS: + data_sleep_durn_u8 = BMA2x2_SLEEP_DURN_50MS; + + /* 50 MS */ + break; + case BMA2x2_SLEEP_DURN_100MS: + data_sleep_durn_u8 = BMA2x2_SLEEP_DURN_100MS; + + /* 100 MS */ + break; + case BMA2x2_SLEEP_DURN_500MS: + data_sleep_durn_u8 = BMA2x2_SLEEP_DURN_500MS; + + /* 500 MS */ + break; + case BMA2x2_SLEEP_DURN_1S: + data_sleep_durn_u8 = BMA2x2_SLEEP_DURN_1S; + + /*! 1 SECS */ + break; + default: + break; + } + /* write the sleep duration */ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, BMA2x2_SLEEP_DURN_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_SLEEP_DURN, data_sleep_durn_u8); + com_rslt += bma2x2_write_reg(BMA2x2_SLEEP_DURN_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + } + else + { + com_rslt = E_OUT_OF_RANGE; + } + } + return com_rslt; +} +/*! + * @brief This API is used to get the sleep timer mode + * in the register 0x12 bit 5 + * + * + * + * + * @param sleep_timer_u8 : The value of sleep timer mode + * sleep_timer_u8 | result + * ----------------- | ---------------------- + * 0 | enable EventDrivenSampling(EDT) + * 1 | enable Equidistant sampling mode(EST) + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_sleep_timer_mode( + u8 *sleep_timer_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /*Read the SLEEP TIMER MODE*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, BMA2x2_SLEEP_TIMER_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *sleep_timer_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_SLEEP_TIMER); + } + return com_rslt; +} +/*! + * @brief This API is used to set the sleep timer mode + * in the register 0x12 bit 5 + * + * + * + * + * @param sleep_timer_u8 : The value of sleep timer mode + * sleep_timer_u8 | result + * ----------------- | ---------------------- + * 0 | enable EventDrivenSampling(EDT) + * 1 | enable Equidistant sampling mode(EST) + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_sleep_timer_mode(u8 sleep_timer_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + if (sleep_timer_u8 < BMA2x2_SLEEP_TIMER_MODE_RANGE) + { + /* write the SLEEP TIMER MODE*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, BMA2x2_SLEEP_TIMER_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_SLEEP_TIMER, sleep_timer_u8); + com_rslt += bma2x2_write_reg(BMA2x2_SLEEP_TIMER_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + } + else + { + com_rslt = E_OUT_OF_RANGE; + } + } + return com_rslt; +} +/*! + * @brief This API is used to get high bandwidth + * in the register 0x13 bit 7 + * + * @param high_bw_u8 : The value of high bandwidth + * high_bw_u8 | result + * ----------------- | ---------------------- + * 0 | Unfiltered High Bandwidth + * 1 | Filtered Low Bandwidth + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_high_bw(u8 *high_bw_u8) +{ + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 data_u8 = BMA2x2_INIT_VALUE; + + if (p_bma2x2 == BMA2x2_NULL) + { + return E_BMA2x2_NULL_PTR; + } + else + { + /* Read the high bandwidth*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, BMA2x2_ENABLE_DATA_HIGH_BW_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *high_bw_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_DATA_HIGH_BW); + } + return com_rslt; +} +/*! + * @brief This API is used to write high bandwidth + * in the register 0x13 bit 7 + * + * @param high_bw_u8 : The value of high bandwidth + * high_bw_u8 | result + * ----------------- | ---------------------- + * 0 | Unfiltered High Bandwidth + * 1 | Filtered Low Bandwidth + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_high_bw(u8 high_bw_u8) +{ + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 data_u8 = BMA2x2_INIT_VALUE; + + if (p_bma2x2 == BMA2x2_NULL) + { + return E_BMA2x2_NULL_PTR; + } + else + { + /* Write the high bandwidth*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, BMA2x2_ENABLE_DATA_HIGH_BW_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE(data_u8, + BMA2x2_ENABLE_DATA_HIGH_BW, high_bw_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_ENABLE_DATA_HIGH_BW_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + } + return com_rslt; +} +/*! + * @brief This API is used to get shadow dis + * in the register 0x13 bit 6 + * + * @param shadow_dis_u8 : The value of shadow dis + * shadow_dis_u8 | result + * ----------------- | ------------------ + * 0 | MSB is Locked + * 1 | No MSB Locking + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_shadow_dis(u8 *shadow_dis_u8) +{ + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 data_u8 = BMA2x2_INIT_VALUE; + + if (p_bma2x2 == BMA2x2_NULL) + { + return E_BMA2x2_NULL_PTR; + } + else + { + /*Read the shadow dis*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_DIS_SHADOW_PROC_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *shadow_dis_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_DIS_SHADOW_PROC); + } + return com_rslt; +} +/*! + * @brief This API is used to set shadow dis + * in the register 0x13 bit 6 + * + * @param shadow_dis_u8 : The value of shadow dis + * shadow_dis_u8 | result + * ----------------- | ------------------ + * 0 | MSB is Locked + * 1 | No MSB Locking + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_shadow_dis(u8 shadow_dis_u8) +{ + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 data_u8 = BMA2x2_INIT_VALUE; + + if (p_bma2x2 == BMA2x2_NULL) + { + return E_BMA2x2_NULL_PTR; + } + else + { + /* Write the shadow dis*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, BMA2x2_DIS_SHADOW_PROC_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_DIS_SHADOW_PROC, shadow_dis_u8); + com_rslt += bma2x2_write_reg(BMA2x2_DIS_SHADOW_PROC_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + } + return com_rslt; +} +/*! + * @brief This function is used for the soft reset + * The soft reset register will be written + * with 0xB6 in the register 0x14. + * + * + * + * \param : None + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_soft_rst(void) +{ + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 data_u8 = BMA2x2_ENABLE_SOFT_RESET_VALUE; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /*! To reset the sensor + 0xB6 value_u8 will be written */ + com_rslt = bma2x2_write_reg(BMA2x2_RST_ADDR, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + } + return com_rslt; +} +/*! + * @brief This API is used to update the register values + * + * + * + * + * @param : None + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_update_image(void) +{ + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 data_u8 = BMA2x2_INIT_VALUE; + + if (p_bma2x2 == BMA2x2_NULL) + { + return E_BMA2x2_NULL_PTR; + } + else + { + /* Write the update image*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, BMA2x2_UPDATE_IMAGE_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_UPDATE_IMAGE, + BMA2x2_GEN_READ_WRITE_LENGTH); + com_rslt += bma2x2_write_reg(BMA2x2_UPDATE_IMAGE_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + } + return com_rslt; +} +/*! + * @brief This API is used to get + * interrupt enable bits of the sensor in the registers 0x16 and 0x17 + * @note It reads the flat enable, orient enable, + * @note single tap enable, double tap enable + * @note slope-x enable, slope-y enable, slope-z enable, + * @note fifo watermark enable, + * @note fifo full enable, data enable, low-g enable, + * @note high-z enable, high-y enable + * @note high-z enable + * + * + * + * @param intr_type_u8: The value of interrupts + * intr_type_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_LOW_G_INTR + * 1 | BMA2x2_HIGH_G_X_INTR + * 2 | BMA2x2_HIGH_G_Y_INTR + * 3 | BMA2x2_HIGH_G_Z_INTR + * 4 | BMA2x2_DATA_ENABLE + * 5 | SLOPE_X_INTR + * 6 | SLOPE_Y_INTR + * 7 | SLOPE_Z_INTR + * 8 | SINGLE_TAP_INTR + * 9 | SINGLE_TAP_INTR + * 10 | ORIENT_INT + * 11 | FLAT_INT + * + * @param value_u8 : The value of interrupts enable + * value_u8 | result + * ----------------- | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_enable(u8 intr_type_u8, + u8 *value_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + switch (intr_type_u8) + { + case BMA2x2_LOW_G_INTR: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_LOW_G_INTR_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *value_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_LOW_G_INTR); + break; + case BMA2x2_HIGH_G_X_INTR: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_HIGH_G_X_INTR_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *value_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_HIGH_G_X_INTR); + break; + case BMA2x2_HIGH_G_Y_INTR: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_HIGH_G_Y_INTR_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *value_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_HIGH_G_Y_INTR); + break; + case BMA2x2_HIGH_G_Z_INTR: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_HIGH_G_Z_INTR_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *value_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_HIGH_G_Z_INTR); + break; + case BMA2x2_DATA_ENABLE: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_NEW_DATA_INTR_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *value_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_NEW_DATA_INTR); + break; + case BMA2x2_SLOPE_X_INTR: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_SLOPE_X_INTR_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *value_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_SLOPE_X_INTR); + break; + case BMA2x2_SLOPE_Y_INTR: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_SLOPE_Y_INTR_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *value_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_SLOPE_Y_INTR); + break; + case BMA2x2_SLOPE_Z_INTR: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_SLOPE_Z_INTR_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *value_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_SLOPE_Z_INTR); + break; + case BMA2x2_SINGLE_TAP_INTR: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_SINGLE_TAP_INTR_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *value_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_SINGLE_TAP_INTR); + break; + case BMA2x2_DOUBLE_TAP_INTR: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_DOUBLE_TAP_INTR_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *value_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_DOUBLE_TAP_INTR); + break; + case BMA2x2_ORIENT_INTR: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_ORIENT_INTR_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *value_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_ORIENT_INTR); + break; + case BMA2x2_FLAT_INTR: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_FLAT_INTR_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *value_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_FLAT_INTR); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to set + * interrupt enable bits of the sensor in the registers 0x16 and 0x17 + * @note It reads the flat enable, orient enable, + * @note single tap enable, double tap enable + * @note slope-x enable, slope-y enable, slope-z enable, + * @note fifo watermark enable, + * @note fifo full enable, data enable, low-g enable, + * @note high-z enable, high-y enable + * @note high-z enable + * + * + * + * @param intr_type_u8: The value of interrupts + * intr_type_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_LOW_G_INTR + * 1 | BMA2x2_HIGH_G_X_INTR + * 2 | BMA2x2_HIGH_G_Y_INTR + * 3 | BMA2x2_HIGH_G_Z_INTR + * 4 | BMA2x2_DATA_ENABLE + * 5 | SLOPE_X_INTR + * 6 | SLOPE_Y_INTR + * 7 | SLOPE_Z_INTR + * 8 | SINGLE_TAP_INTR + * 9 | SINGLE_TAP_INTR + * 10 | ORIENT_INT + * 11 | FLAT_INT + * + * @param value_u8 : The value of interrupts enable + * value_u8 | result + * ----------------- | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_enable(u8 intr_type_u8, + u8 value_u8) +{ + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 data_u8 = BMA2x2_INIT_VALUE; + u8 data2_u8 = BMA2x2_INIT_VALUE; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, BMA2x2_INTR_ENABLE1_ADDR, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + com_rslt += p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, BMA2x2_INTR_ENABLE2_ADDR, + &data2_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + value_u8 = value_u8 & BMA2x2_GEN_READ_WRITE_LENGTH; + switch (intr_type_u8) + { + case BMA2x2_LOW_G_INTR: + /* Low G Interrupt */ + data2_u8 = BMA2x2_SET_BITSLICE(data2_u8, + BMA2x2_ENABLE_LOW_G_INTR, value_u8); + break; + case BMA2x2_HIGH_G_X_INTR: + /* High G X Interrupt */ + data2_u8 = BMA2x2_SET_BITSLICE(data2_u8, + BMA2x2_ENABLE_HIGH_G_X_INTR, value_u8); + break; + case BMA2x2_HIGH_G_Y_INTR: + /* High G Y Interrupt */ + data2_u8 = BMA2x2_SET_BITSLICE(data2_u8, + BMA2x2_ENABLE_HIGH_G_Y_INTR, value_u8); + break; + case BMA2x2_HIGH_G_Z_INTR: + /* High G Z Interrupt */ + data2_u8 = BMA2x2_SET_BITSLICE(data2_u8, + BMA2x2_ENABLE_HIGH_G_Z_INTR, value_u8); + break; + case BMA2x2_DATA_ENABLE: + /*Data En Interrupt */ + data2_u8 = BMA2x2_SET_BITSLICE(data2_u8, + BMA2x2_ENABLE_NEW_DATA_INTR, value_u8); + break; + case BMA2x2_SLOPE_X_INTR: + /* Slope X Interrupt */ + data_u8 = BMA2x2_SET_BITSLICE(data_u8, + BMA2x2_ENABLE_SLOPE_X_INTR, value_u8); + break; + case BMA2x2_SLOPE_Y_INTR: + /* Slope Y Interrupt */ + data_u8 = BMA2x2_SET_BITSLICE(data_u8, + BMA2x2_ENABLE_SLOPE_Y_INTR, value_u8); + break; + case BMA2x2_SLOPE_Z_INTR: + /* Slope Z Interrupt */ + data_u8 = BMA2x2_SET_BITSLICE(data_u8, + BMA2x2_ENABLE_SLOPE_Z_INTR, value_u8); + break; + case BMA2x2_SINGLE_TAP_INTR: + /* Single Tap Interrupt */ + data_u8 = BMA2x2_SET_BITSLICE(data_u8, + BMA2x2_ENABLE_SINGLE_TAP_INTR, value_u8); + break; + case BMA2x2_DOUBLE_TAP_INTR: + /* Double Tap Interrupt */ + data_u8 = BMA2x2_SET_BITSLICE(data_u8, + BMA2x2_ENABLE_DOUBLE_TAP_INTR, value_u8); + break; + case BMA2x2_ORIENT_INTR: + /* Orient Interrupt */ + data_u8 = BMA2x2_SET_BITSLICE(data_u8, + BMA2x2_ENABLE_ORIENT_INTR, value_u8); + break; + case BMA2x2_FLAT_INTR: + /* Flat Interrupt */ + data_u8 = BMA2x2_SET_BITSLICE(data_u8, + BMA2x2_ENABLE_FLAT_INTR, value_u8); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + /* write the interrupt*/ + com_rslt += bma2x2_write_reg + (BMA2x2_INTR_ENABLE1_ADDR, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + com_rslt += bma2x2_write_reg + (BMA2x2_INTR_ENABLE2_ADDR, + &data2_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + } + return com_rslt; +} +/*! + * @brief This API is used to get + * the interrupt fifo full enable interrupt status + * in the register 0x17 bit 5 + * + * + * @param fifo_full_u8 The value of fifo full interrupt enable + * fifo_full_u8 | result + * ----------------- | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_fifo_full(u8 *fifo_full_u8) +{ + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 data_u8 = BMA2x2_INIT_VALUE; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* Read fifo full interrupt */ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_INTR_FIFO_FULL_ENABLE_INTR_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *fifo_full_u8 = BMA2x2_GET_BITSLICE(data_u8, + BMA2x2_INTR_FIFO_FULL_ENABLE_INTR); + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the interrupt fifo full enable interrupt status + * in the register 0x17 bit 5 + * + * + * @param fifo_full_u8 The value of fifo full interrupt enable + * fifo_full_u8 | result + * ----------------- | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_fifo_full(u8 fifo_full_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + if (fifo_full_u8 < BMA2x2_FIFO_MODE_STATUS_RANGE) + { + /* Write fifo full interrupt */ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_INTR_FIFO_FULL_ENABLE_INTR_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_INTR_FIFO_FULL_ENABLE_INTR, + fifo_full_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_INTR_FIFO_FULL_ENABLE_INTR_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + } + else + { + com_rslt = E_OUT_OF_RANGE; + } + } + return com_rslt; +} +/*! + * @brief This API is used to get + * the interrupt fifo watermark enable interrupt status + * in the register 0x17 bit 6 + * + * + * + * + * @param fifo_wm_u8 : the value FIFO Water Mark + * fifo_wm_u8 | result + * ----------------- | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_fifo_wm(u8 *fifo_wm_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* Read the fifo water mark*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_INTR_FIFO_WM_ENABLE_INTR_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *fifo_wm_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_INTR_FIFO_WM_ENABLE_INTR); + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the interrupt fifo watermark enable interrupt status + * in the register 0x17 bit 6 + * + * + * + * + * @param fifo_wm_u8 : the value FIFO Water Mark + * fifo_wm_u8 | result + * ----------------- | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_fifo_wm(u8 fifo_wm_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + if (fifo_wm_u8 < BMA2x2_FIFO_MODE_STATUS_RANGE) + { + /* Write the fifo water mark interrupt*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_INTR_FIFO_WM_ENABLE_INTR_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_INTR_FIFO_WM_ENABLE_INTR, + fifo_wm_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_INTR_FIFO_WM_ENABLE_INTR_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + } + else + { + com_rslt = E_OUT_OF_RANGE; + } + } + return com_rslt; +} +/*! + * @brief This API is used to get + * the interrupt status of slow/no motion select and slow no motion + * enable xyz interrupt in the register 0x18 bit from 0 to 3 + * + * + * @param channel_u8 : The value of slow/no motion select + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_ACCEL_SLOW_NO_MOTION_ENABLE_X + * 1 | BMA2x2_ACCEL_SLOW_NO_MOTION_ENABLE_Y + * 2 | BMA2x2_ACCEL_SLOW_NO_MOTION_ENABLE_Z + * 3 | BMA2x2_ACCEL_SLOW_NO_MOTION_ENABLE_SEL + * + * @param slow_no_motion_u8 : The value of slow no motion interrupt enable + * slow_no_motion_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_slow_no_motion(u8 channel_u8, + u8 *slow_no_motion_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* Read the slow no motion interrupt */ + switch (channel_u8) + { + case BMA2x2_SLOW_NO_MOTION_ENABLE_X: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_X_INTR_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *slow_no_motion_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_X_INTR); + break; + case BMA2x2_SLOW_NO_MOTION_ENABLE_Y: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_Y_INTR_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *slow_no_motion_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_Y_INTR); + break; + case BMA2x2_SLOW_NO_MOTION_ENABLE_Z: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_Z_INTR_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *slow_no_motion_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_Z_INTR); + break; + case BMA2x2_SLOW_NO_MOTION_ENABLE_SELECT: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_SELECT_INTR_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *slow_no_motion_u8 = BMA2x2_GET_BITSLICE + (data_u8, + BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_SELECT_INTR); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the interrupt status of slow/no motion select and slow no motion + * enable xyz interrupt in the register 0x18 bit from 0 to 3 + * + * + * @param channel_u8 : The value of slow/no motion select + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_ACCEL_SLOW_NO_MOTION_ENABLE_X + * 1 | BMA2x2_ACCEL_SLOW_NO_MOTION_ENABLE_Y + * 2 | BMA2x2_ACCEL_SLOW_NO_MOTION_ENABLE_Z + * 3 | BMA2x2_ACCEL_SLOW_NO_MOTION_ENABLE_SEL + * + * @param slow_no_motion_u8 : The value of slow no motion + * interrupt enable + * slow_no_motion_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_slow_no_motion(u8 channel_u8, + u8 slow_no_motion_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* Write the slow no motion interrupt*/ + switch (channel_u8) + { + case BMA2x2_SLOW_NO_MOTION_ENABLE_X: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_X_INTR_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, + BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_X_INTR, + slow_no_motion_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_X_INTR_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + case BMA2x2_SLOW_NO_MOTION_ENABLE_Y: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_Y_INTR_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, + BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_Y_INTR, + slow_no_motion_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_Y_INTR_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + case BMA2x2_SLOW_NO_MOTION_ENABLE_Z: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_Z_INTR_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, + BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_Z_INTR, + slow_no_motion_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_Z_INTR_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + case BMA2x2_SLOW_NO_MOTION_ENABLE_SELECT: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_SELECT_INTR_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, + BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_SELECT_INTR, + slow_no_motion_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_SELECT_INTR_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to get + * the interrupt enable of low_g interrupt in the register 0x19 and 0x1B + * @note INTR1_Low_g -> register 0x19 bit 0 + * @note INTR2_Low_g -> register 0x1B bit 0 + * + * + * + * + * @param channel_u8 : The value of low interrupt selection channel + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_ACCEL_INTR1_LOW_G + * 1 | BMA2x2_ACCEL_INTR2_LOW_G + * + * @param intr_low_g_u8 : the value of low_g interrupt + * intr_low_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_low_g(u8 channel_u8, + u8 *intr_low_g_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + switch (channel_u8) + { + /* Read the low_g interrupt*/ + case BMA2x2_INTR1_LOW_G: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR1_PAD_LOW_G_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *intr_low_g_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_INTR1_PAD_LOW_G); + break; + case BMA2x2_INTR2_LOW_G: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR2_PAD_LOW_G_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *intr_low_g_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_INTR2_PAD_LOW_G); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the interrupt enable of low_g interrupt in the register 0x19 and 0x1B + * @note INTR1_Low_g -> register 0x19 bit 0 + * @note INTR2_Low_g -> register 0x1B bit 0 + * + * + * + * + * @param channel_u8 : The value of low interrupt selection channel + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_ACCEL_INTR1_LOW_G + * 1 | BMA2x2_ACCEL_INTR2_LOW_G + * + * @param intr_low_u8 : the value of low_g interrupt + * intr_low_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_low_g(u8 channel_u8, + u8 intr_low_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + switch (channel_u8) + { + case BMA2x2_INTR1_LOW_G: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR1_PAD_LOW_G_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE(data_u8, + BMA2x2_ENABLE_INTR1_PAD_LOW_G, intr_low_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_ENABLE_INTR1_PAD_LOW_G_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + case BMA2x2_INTR2_LOW_G: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR2_PAD_LOW_G_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_ENABLE_INTR2_PAD_LOW_G, + intr_low_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_ENABLE_INTR2_PAD_LOW_G_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to get + * the interrupt enable of high_g interrupt in the register 0x19 and 0x1B + * @note INTR1_high_g -> register 0x19 bit 1 + * @note INTR2_high_g -> register 0x1B bit 1 + * + * + * @param channel_u8: The value of high_g interrupt selection + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_ACCEL_INTR1_HIGH_G + * 1 | BMA2x2_ACCEL_INTR2_HIGH_G + * + * @param intr_high_g_u8 : the value of high_g interrupt + * intr_high_g_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_high_g(u8 channel_u8, + u8 *intr_high_g_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + switch (channel_u8) + { + /* read the high_g interrupt*/ + case BMA2x2_INTR1_HIGH_G: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR1_PAD_HIGH_G_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *intr_high_g_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_INTR1_PAD_HIGH_G); + break; + case BMA2x2_INTR2_HIGH_G: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR2_PAD_HIGH_G_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *intr_high_g_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_INTR2_PAD_HIGH_G); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the interrupt enable of high_g interrupt in the register 0x19 and 0x1B + * @note INTR1_high_g -> register 0x19 bit 1 + * @note INTR2_high_g -> register 0x1B bit 1 + * + * + * @param channel_u8: The value of high_g interrupt selection + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_ACCEL_INTR1_HIGH_G + * 1 | BMA2x2_ACCEL_INTR2_HIGH_G + * + * @param intr_high_g_u8 : the value of high_g interrupt + * intr_high_g_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_high_g(u8 channel_u8, + u8 intr_high_g_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* write the high_g interrupt*/ + switch (channel_u8) + { + case BMA2x2_INTR1_HIGH_G: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR1_PAD_HIGH_G_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_ENABLE_INTR1_PAD_HIGH_G, + intr_high_g_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_ENABLE_INTR1_PAD_HIGH_G_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + case BMA2x2_INTR2_HIGH_G: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR2_PAD_HIGH_G_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_ENABLE_INTR2_PAD_HIGH_G, + intr_high_g_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_ENABLE_INTR2_PAD_HIGH_G_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to get + * the interrupt enable of slope interrupt in the register 0x19 and 0x1B + * @note INTR1_slope -> register 0x19 bit 2 + * @note INTR2_slope -> register 0x1B bit 2 + * + * + * + * @param channel_u8: the value of slope channel select + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_ACCEL_INTR1_SLOPE + * 1 | BMA2x2_ACCEL_INTR2_SLOPE + * + * @param intr_slope_u8 : The slope value enable value + * intr_slope_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_slope(u8 channel_u8, + u8 *intr_slope_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* Read the slope value */ + switch (channel_u8) + { + case BMA2x2_INTR1_SLOPE: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR1_PAD_SLOPE_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *intr_slope_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_INTR1_PAD_SLOPE); + break; + case BMA2x2_INTR2_SLOPE: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR2_PAD_SLOPE_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *intr_slope_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_INTR2_PAD_SLOPE); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the interrupt enable of slope interrupt in the register 0x19 and 0x1B + * @note INTR1_slope -> register 0x19 bit 2 + * @note INTR2_slope -> register 0x1B bit 2 + * + * + * + * @param channel_u8: the value of slope channel select + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_ACCEL_INTR1_SLOPE + * 1 | BMA2x2_ACCEL_INTR2_SLOPE + * + * @param intr_slope_u8 : The slope value enable value + * intr_slope_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_slope(u8 channel_u8, + u8 intr_slope_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + switch (channel_u8) + { + /* Write the slope value */ + case BMA2x2_INTR1_SLOPE: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR1_PAD_SLOPE_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_ENABLE_INTR1_PAD_SLOPE, + intr_slope_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_ENABLE_INTR1_PAD_SLOPE_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + case BMA2x2_INTR2_SLOPE: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR2_PAD_SLOPE_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_ENABLE_INTR2_PAD_SLOPE, + intr_slope_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_ENABLE_INTR2_PAD_SLOPE_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to get + * the interrupt enable of slow/no motion interrupt in + * the register 0x19 and 0x1B + * @note INTR1_slow_no_motion -> register 0x19 bit 3 + * @note INTR2_slow_no_motion -> register 0x1B bit 3 + * + * + * + * + * @param channel_u8 : The value of slow/no motion selection + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_INTR1_SLOW_NO_MOTION + * 1 | BMA2x2_INTR2_SLOW_NO_MOTION + * + * @param intr_slow_no_motion_u8: the slow_no_motion enable value + * intr_slow_no_motion_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_slow_no_motion(u8 channel_u8, + u8 *intr_slow_no_motion_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* Read the slow no motion interrupt */ + switch (channel_u8) + { + case BMA2x2_INTR1_SLOW_NO_MOTION: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR1_PAD_SLOW_NO_MOTION_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *intr_slow_no_motion_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_INTR1_PAD_SLOW_NO_MOTION); + break; + case BMA2x2_INTR2_SLOW_NO_MOTION: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR2_PAD_SLOW_NO_MOTION_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *intr_slow_no_motion_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_INTR2_PAD_SLOW_NO_MOTION); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the interrupt enable of slow/no motion interrupt in + * the register 0x19 and 0x1B + * @note INTR1_slow_no_motion -> register 0x19 bit 3 + * @note INTR2_slow_no_motion -> register 0x1B bit 3 + * + * + * + * + * @param channel_u8 : The value of slow/no motion selection + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_INTR1_SLOW_NO_MOTION + * 1 | BMA2x2_INTR2_SLOW_NO_MOTION + * + * @param intr_slow_no_motion_u8: the slow_no_motion enable value + * intr_slow_no_motion_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_slow_no_motion(u8 channel_u8, + u8 intr_slow_no_motion_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + switch (channel_u8) + { + /* Write the slow no motion interrupt */ + case BMA2x2_INTR1_SLOW_NO_MOTION: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR1_PAD_SLOW_NO_MOTION_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, + BMA2x2_ENABLE_INTR1_PAD_SLOW_NO_MOTION, + intr_slow_no_motion_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_ENABLE_INTR1_PAD_SLOW_NO_MOTION_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + case BMA2x2_INTR2_SLOW_NO_MOTION: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR2_PAD_SLOW_NO_MOTION_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, + BMA2x2_ENABLE_INTR2_PAD_SLOW_NO_MOTION, + intr_slow_no_motion_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_ENABLE_INTR2_PAD_SLOW_NO_MOTION_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to get + * the interrupt enable of double tap interrupt + * in the register 0x19 and 0x1B + * @note INTR1_double -> register 0x19 bit 4 + * @note INTR2_double -> register 0x1B bit 4 + * + * + * + * + * @param channel_u8: The value of double tap selection + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_ACCEL_INTR1_DOUBLE_TAP + * 1 | BMA2x2_ACCEL_INTR2_DOUBLE_TAP + * + * @param intr_double_tap_u8: The double tap interrupt enable value + * intr_double_tap_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_double_tap(u8 channel_u8, + u8 *intr_double_tap_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* read the double tap*/ + switch (channel_u8) + { + case BMA2x2_INTR1_DOUBLE_TAP: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR1_PAD_DOUBLE_TAP_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *intr_double_tap_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_INTR1_PAD_DOUBLE_TAP); + break; + case BMA2x2_INTR2_DOUBLE_TAP: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR2_PAD_DOUBLE_TAP_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *intr_double_tap_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_INTR2_PAD_DOUBLE_TAP); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the interrupt enable of double tap interrupt + * in the register 0x19 and 0x1B + * @note INTR1_double -> register 0x19 bit 4 + * @note INTR2_double -> register 0x1B bit 4 + * + * + * + * + * @param channel_u8: The value of double tap selection + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_ACCEL_INTR1_DOUBLE_TAP + * 1 | BMA2x2_ACCEL_INTR2_DOUBLE_TAP + * + * @param intr_double_tap_u8: The double tap interrupt enable value + * intr_double_tap_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_double_tap(u8 channel_u8, + u8 intr_double_tap_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + switch (channel_u8) + { + /* write the double tap*/ + case BMA2x2_INTR1_DOUBLE_TAP: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR1_PAD_DOUBLE_TAP_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, + BMA2x2_ENABLE_INTR1_PAD_DOUBLE_TAP, + intr_double_tap_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_ENABLE_INTR1_PAD_DOUBLE_TAP_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + case BMA2x2_INTR2_DOUBLE_TAP: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR2_PAD_DOUBLE_TAP_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, + BMA2x2_ENABLE_INTR2_PAD_DOUBLE_TAP, + intr_double_tap_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_ENABLE_INTR2_PAD_DOUBLE_TAP_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to get + * the interrupt enable of single tap + * interrupt in the register 0x19 and 0x1B + * @note INTR1_single_tap -> register 0x19 bit 5 + * @note INTR2_single_tap -> register 0x1B bit 5 + * + * + * @param channel_u8: The value of single tap interrupt select + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_ACCEL_INTR1_SINGLE_TAP + * 1 | BMA2x2_ACCEL_INTR2_SINGLE_TAP + * + * @param intr_single_tap_u8: The single tap interrupt enable value + * intr_single_tap_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_single_tap(u8 channel_u8, + u8 *intr_single_tap_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + switch (channel_u8) + { + /* Read the single tap value*/ + case BMA2x2_INTR1_SINGLE_TAP: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR1_PAD_SINGLE_TAP_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *intr_single_tap_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_INTR1_PAD_SINGLE_TAP); + break; + case BMA2x2_INTR2_SINGLE_TAP: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR2_PAD_SINGLE_TAP_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *intr_single_tap_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_INTR2_PAD_SINGLE_TAP); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the interrupt enable of single tap + * interrupt in the register 0x19 and 0x1B + * @note INTR1_single_tap -> register 0x19 bit 5 + * @note INTR2_single_tap -> register 0x1B bit 5 + * + * + * @param channel_u8: The value of single tap interrupt select + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_ACCEL_INTR1_SINGLE_TAP + * 1 | BMA2x2_ACCEL_INTR2_SINGLE_TAP + * + * @param intr_single_tap_u8: The single tap interrupt enable value + * intr_single_tap_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_single_tap(u8 channel_u8, + u8 intr_single_tap_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + switch (channel_u8) + { + /* write the single tap value*/ + case BMA2x2_INTR1_SINGLE_TAP: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR1_PAD_SINGLE_TAP_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE(data_u8, + BMA2x2_ENABLE_INTR1_PAD_SINGLE_TAP, + intr_single_tap_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_ENABLE_INTR1_PAD_SINGLE_TAP_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + case BMA2x2_INTR2_SINGLE_TAP: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR2_PAD_SINGLE_TAP_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, + BMA2x2_ENABLE_INTR2_PAD_SINGLE_TAP, + intr_single_tap_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_ENABLE_INTR2_PAD_SINGLE_TAP_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to get + * the interrupt status of orient interrupt in the register 0x19 and 0x1B + * @note INTR1_orient -> register 0x19 bit 6 + * @note INTR2_orient -> register 0x1B bit 6 + * + * + * @param channel_u8: The value of orient interrupt select + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_ACCEL_INTR1_ORIENT + * 1 | BMA2x2_ACCEL_INTR2_ORIENT + * + * @param intr_orient_u8: The value of orient interrupt enable + * intr_orient_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_orient(u8 channel_u8, + u8 *intr_orient_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + switch (channel_u8) + { + /* Read orient interrupt*/ + case BMA2x2_INTR1_ORIENT: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR1_PAD_ORIENT_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *intr_orient_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_INTR1_PAD_ORIENT); + break; + case BMA2x2_INTR2_ORIENT: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR2_PAD_ORIENT_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *intr_orient_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_INTR2_PAD_ORIENT); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the interrupt status of orient interrupt in the register 0x19 and 0x1B + * @note INTR1_orient -> register 0x19 bit 6 + * @note INTR2_orient -> register 0x1B bit 6 + * + * + * @param channel_u8: The value of orient interrupt select + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_ACCEL_INTR1_ORIENT + * 1 | BMA2x2_ACCEL_INTR2_ORIENT + * + * @param intr_orient_u8: The value of orient interrupt enable + * intr_orient_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_orient(u8 channel_u8, + u8 intr_orient_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + switch (channel_u8) + { + /* Write orient interrupt */ + case BMA2x2_INTR1_ORIENT: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR1_PAD_ORIENT_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, + BMA2x2_ENABLE_INTR1_PAD_ORIENT, intr_orient_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_ENABLE_INTR1_PAD_ORIENT_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + case BMA2x2_INTR2_ORIENT: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR2_PAD_ORIENT_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, + BMA2x2_ENABLE_INTR2_PAD_ORIENT, intr_orient_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_ENABLE_INTR2_PAD_ORIENT_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to get + * the interrupt enable of flat interrupt in the register 0x19 and 0x1B + * @note INTR1_flat -> register 0x19 bit 7 + * @note INTR2_flat -> register 0x1B bit 7 + * + * + * + * + * @param channel_u8: The value of flat interrupt select + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_ACCEL_INTR1_FLAT + * 1 | BMA2x2_ACCEL_INTR2_FLAT + * + * @param intr_flat_u8: The flat interrupt enable value + * intr_flat_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_flat(u8 channel_u8, + u8 *intr_flat_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + switch (channel_u8) + { + /* Read flat interrupt */ + case BMA2x2_INTR1_FLAT: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR1_PAD_FLAT_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *intr_flat_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_INTR1_PAD_FLAT); + break; + case BMA2x2_INTR2_FLAT: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR2_PAD_FLAT_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *intr_flat_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_INTR2_PAD_FLAT); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the interrupt enable of flat interrupt in the register 0x19 and 0x1B + * @note INTR1_flat -> register 0x19 bit 7 + * @note INTR2_flat -> register 0x1B bit 7 + * + * + * + * + * @param channel_u8: The value of flat interrupt select + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_ACCEL_INTR1_FLAT + * 1 | BMA2x2_ACCEL_INTR2_FLAT + * + * @param intr_flat_u8: The flat interrupt enable value + * intr_flat_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_flat(u8 channel_u8, + u8 intr_flat_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + switch (channel_u8) + { + /* write flat interrupt */ + case BMA2x2_INTR1_FLAT: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR1_PAD_FLAT_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, + BMA2x2_ENABLE_INTR1_PAD_FLAT, intr_flat_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_ENABLE_INTR1_PAD_FLAT_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + case BMA2x2_INTR2_FLAT: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR2_PAD_FLAT_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, + BMA2x2_ENABLE_INTR2_PAD_FLAT, intr_flat_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_ENABLE_INTR2_PAD_FLAT_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to get + * the interrupt status of new data in the register 0x19 + * @note INTR1_data -> register 0x19 bit 0 + * @note INTR2_data -> register 0x19 bit 7 + * + * + * + * @param channel_u8: The value of new data interrupt select + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_ACCEL_INTR1_NEWDATA + * 1 | BMA2x2_ACCEL_INTR2_NEWDATA + * + * @param intr_newdata_u8: The new data interrupt enable value + * intr_newdata_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_new_data(u8 channel_u8, + u8 *intr_newdata_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + switch (channel_u8) + { + /* Read the data interrupt*/ + case BMA2x2_INTR1_NEWDATA: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR1_PAD_NEWDATA_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *intr_newdata_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_INTR1_PAD_NEWDATA); + break; + case BMA2x2_INTR2_NEWDATA: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR2_PAD_NEWDATA_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *intr_newdata_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_INTR2_PAD_NEWDATA); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the interrupt status of new data in the register 0x19 + * @note INTR1_data -> register 0x19 bit 0 + * @note INTR2_data -> register 0x19 bit 7 + * + * + * + * @param channel_u8: The value of new data interrupt select + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_ACCEL_INTR1_NEWDATA + * 1 | BMA2x2_ACCEL_INTR2_NEWDATA + * + * @param intr_newdata_u8: The new data interrupt enable value + * intr_newdata_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_new_data(u8 channel_u8, + u8 intr_newdata_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + switch (channel_u8) + { + /* write the new data interrupt */ + case BMA2x2_INTR1_NEWDATA: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR1_PAD_NEWDATA_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, + BMA2x2_ENABLE_INTR1_PAD_NEWDATA, intr_newdata_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_ENABLE_INTR1_PAD_NEWDATA_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + case BMA2x2_INTR2_NEWDATA: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR2_PAD_NEWDATA_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, + BMA2x2_ENABLE_INTR2_PAD_NEWDATA, intr_newdata_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_ENABLE_INTR2_PAD_NEWDATA_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to get the fifo watermark interrupt1 data + * in the register 0x1A bit 1 + * + * @param intr1_fifo_wm_u8 : The value of interrupt1 FIFO watermark enable + * intr1_fifo_wm_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr1_fifo_wm(u8 *intr1_fifo_wm_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* read the fifo watermark interrupt */ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR1_PAD_FIFO_WM_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *intr1_fifo_wm_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_INTR1_PAD_FIFO_WM); + } + return com_rslt; +} +/*! + * @brief This API is used to set the fifo watermark interrupt1 data + * in the register 0x1A bit 1 + * + * @param intr1_fifo_wm_u8 : The value of interrupt1 FIFO watermark enable + * intr1_fifo_wm_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr1_fifo_wm(u8 intr1_fifo_wm_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + if (intr1_fifo_wm_u8 < + BMA2x2_FIFO_MODE_STATUS_RANGE) + { + /* write the fifo watermark interrupt */ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR1_PAD_FIFO_WM_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, + BMA2x2_ENABLE_INTR1_PAD_FIFO_WM, intr1_fifo_wm_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_ENABLE_INTR1_PAD_FIFO_WM_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + } + else + { + com_rslt = E_OUT_OF_RANGE; + } + } + return com_rslt; +} +/*! + * @brief This API is used to get the fifo watermark interrupt2 data + * in the register 0x1A bit 6 + * + * @param intr2_fifo_wm_u8 : The value of interrupt1 FIFO watermark enable + * intr2_fifo_wm_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr2_fifo_wm(u8 *intr2_fifo_wm_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* read the fifo watermark interrupt2*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR2_PAD_FIFO_WM_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *intr2_fifo_wm_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_INTR2_PAD_FIFO_WM); + } + return com_rslt; +} +/*! + * @brief This API is used to set the fifo watermark interrupt2 data + * in the register 0x1A bit 6 + * + * @param intr2_fifo_wm_u8 : The value of interrupt1 FIFO watermark enable + * intr2_fifo_wm_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr2_fifo_wm(u8 intr2_fifo_wm_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + if (intr2_fifo_wm_u8 < + BMA2x2_FIFO_MODE_STATUS_RANGE) + { + /* write the fifo watermark interrupt2*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR2_PAD_FIFO_WM_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, + BMA2x2_ENABLE_INTR2_PAD_FIFO_WM, intr2_fifo_wm_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_ENABLE_INTR2_PAD_FIFO_WM_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + } + else + { + com_rslt = E_OUT_OF_RANGE; + } + } + return com_rslt; +} +/*! + * @brief This API is used to get + * the fifo full interrupt1 in the register 0x1A bit 2 + * + * + * + * @param intr1_fifo_full_u8 : The value of fifo full interrupt enable + * intr1_fifo_full_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr1_fifo_full(u8 *intr1_fifo_full_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* read the fifo full interrupt1*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR1_PAD_FIFO_FULL_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *intr1_fifo_full_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_INTR1_PAD_FIFO_FULL); + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the fifo full interrupt1 in the register 0x1A bit 2 + * + * + * + * @param intr1_fifo_full_u8 : The value of fifo full interrupt enable + * intr1_fifo_full_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr1_fifo_full(u8 intr1_fifo_full_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + if (intr1_fifo_full_u8 < + BMA2x2_FIFO_MODE_STATUS_RANGE) + { + /* write the fifo full interrupt1*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR1_PAD_FIFO_FULL_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_ENABLE_INTR1_PAD_FIFO_FULL, + intr1_fifo_full_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_ENABLE_INTR1_PAD_FIFO_FULL_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + } + else + { + com_rslt = E_OUT_OF_RANGE; + } + } + return com_rslt; +} +/*! + * @brief This API is used to get + * the fifo full interrupt2 in the register 0x1A bit 5 + * + * + * + * @param intr2_fifo_full_u8 : Thee vale of fifo full enable + * intr2_fifo_full_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr2_fifo_full(u8 *intr2_fifo_full_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* read the fifo full interrupt2*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR2_PAD_FIFO_FULL_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *intr2_fifo_full_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_INTR2_PAD_FIFO_FULL); + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the fifo full interrupt2 in the register 0x1A bit 5 + * + * + * + * @param intr2_fifo_full_u8 : Thee vale of fifo full enable + * intr2_fifo_full_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr2_fifo_full(u8 intr2_fifo_full_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + if (intr2_fifo_full_u8 < + BMA2x2_FIFO_MODE_STATUS_RANGE) + { + /* write the fifo full interrupt2*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_INTR2_PAD_FIFO_FULL_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, + BMA2x2_ENABLE_INTR2_PAD_FIFO_FULL, + intr2_fifo_full_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_ENABLE_INTR2_PAD_FIFO_FULL_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + } + else + { + com_rslt = E_OUT_OF_RANGE; + } + } + return com_rslt; +} +/*! + * @brief This API is used to get + * the source data status of source data, + * source slow no motion, source slope, source high + * and source low in the register 0x1E bit from 0 to 5 + * + * + * + * @param channel_u8 : The value of source select + * channel_u8 | result + * -----------------| ------------------ + * 0 | BMA2x2_ACCEL_SOURCE_LOW_G + * 1 | BMA2x2_ACCEL_SOURCE_HIGH_G + * 2 | BMA2x2_ACCEL_SOURCE_SLOPE + * 3 | BMA2x2_ACCEL_SOURCE_SLOW_NO_MOTION + * 4 | BMA2x2_ACCEL_SOURCE_TAP + * 5 | BMA2x2_ACCEL_SOURCE_DATA + * + * @param intr_source_u8: The source status enable value + * intr_source_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_source(u8 channel_u8, + u8 *intr_source_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + return E_BMA2x2_NULL_PTR; + } + else + { + /* read the source interrupt register */ + switch (channel_u8) + { + case BMA2x2_SOURCE_LOW_G: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_UNFILT_INTR_SOURCE_LOW_G_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *intr_source_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_UNFILT_INTR_SOURCE_LOW_G); + break; + case BMA2x2_SOURCE_HIGH_G: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_UNFILT_INTR_SOURCE_HIGH_G_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *intr_source_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_UNFILT_INTR_SOURCE_HIGH_G); + break; + case BMA2x2_SOURCE_SLOPE: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_UNFILT_INTR_SOURCE_SLOPE_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *intr_source_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_UNFILT_INTR_SOURCE_SLOPE); + break; + case BMA2x2_SOURCE_SLOW_NO_MOTION: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_UNFILT_INTR_SOURCE_SLOW_NO_MOTION_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *intr_source_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_UNFILT_INTR_SOURCE_SLOW_NO_MOTION); + break; + case BMA2x2_SOURCE_TAP: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_UNFILT_INTR_SOURCE_TAP_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *intr_source_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_UNFILT_INTR_SOURCE_TAP); + break; + case BMA2x2_SOURCE_DATA: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_UNFILT_INTR_SOURCE_DATA_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *intr_source_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_UNFILT_INTR_SOURCE_DATA); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the source data status of source data, + * source slow no motion, source slope, source high + * and source low in the register 0x1E bit from 0 to 5 + * + * + * + * @param channel_u8 : The value of source select + * channel_u8 | result + * -----------------| ------------------ + * 0 | BMA2x2_ACCEL_SOURCE_LOW_G + * 1 | BMA2x2_ACCEL_SOURCE_HIGH_G + * 2 | BMA2x2_ACCEL_SOURCE_SLOPE + * 3 | BMA2x2_ACCEL_SOURCE_SLOW_NO_MOTION + * 4 | BMA2x2_ACCEL_SOURCE_TAP + * 5 | BMA2x2_ACCEL_SOURCE_DATA + * + * @param intr_source_u8: The source status enable value + * intr_source_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_source(u8 channel_u8, + u8 intr_source_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + if (p_bma2x2 == BMA2x2_NULL) + { + com_rslt = E_BMA2x2_NULL_PTR; + } + else + { + switch (channel_u8) + { + /* write the source interrupt register*/ + case BMA2x2_SOURCE_LOW_G: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_UNFILT_INTR_SOURCE_LOW_G_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, + BMA2x2_UNFILT_INTR_SOURCE_LOW_G, intr_source_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_UNFILT_INTR_SOURCE_LOW_G_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + case BMA2x2_SOURCE_HIGH_G: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_UNFILT_INTR_SOURCE_HIGH_G_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, + BMA2x2_UNFILT_INTR_SOURCE_HIGH_G, intr_source_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_UNFILT_INTR_SOURCE_HIGH_G_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + case BMA2x2_SOURCE_SLOPE: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_UNFILT_INTR_SOURCE_SLOPE_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, + BMA2x2_UNFILT_INTR_SOURCE_SLOPE, intr_source_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_UNFILT_INTR_SOURCE_SLOPE_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + case BMA2x2_SOURCE_SLOW_NO_MOTION: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_UNFILT_INTR_SOURCE_SLOW_NO_MOTION_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, + BMA2x2_UNFILT_INTR_SOURCE_SLOW_NO_MOTION, + intr_source_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_UNFILT_INTR_SOURCE_SLOW_NO_MOTION_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + case BMA2x2_SOURCE_TAP: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_UNFILT_INTR_SOURCE_TAP_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_UNFILT_INTR_SOURCE_TAP, + intr_source_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_UNFILT_INTR_SOURCE_TAP_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + case BMA2x2_SOURCE_DATA: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_UNFILT_INTR_SOURCE_DATA_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_UNFILT_INTR_SOURCE_DATA, + intr_source_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_UNFILT_INTR_SOURCE_DATA_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to get + * the interrupt output type in the register 0x20. + * @note INTR1 -> bit 1 + * @note INTR2 -> bit 3 + * + * @param channel_u8: The value of output type select + * channel_u8 | result + * -----------------| ------------------ + * 0 | BMA2x2_ACCEL_INTR1_OUTPUT + * 1 | BMA2x2_ACCEL_INTR2_OUTPUT + * + * @param intr_output_type_u8: The value of output type select + * intr_source_u8 | result + * ------------------------ | ------------------ + * 0x01 | OPEN_DRAIN + * 0x00 | PUSS_PULL + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_output_type(u8 channel_u8, + u8 *intr_output_type_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + com_rslt = E_BMA2x2_NULL_PTR; + } + else + { + switch (channel_u8) + { + /* read the output type */ + case BMA2x2_INTR1_OUTPUT: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_INTR1_PAD_OUTPUT_TYPE_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *intr_output_type_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_INTR1_PAD_OUTPUT_TYPE); + break; + case BMA2x2_INTR2_OUTPUT: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_INTR2_PAD_OUTPUT_TYPE_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *intr_output_type_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_INTR2_PAD_OUTPUT_TYPE); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the interrupt output type in the register 0x20. + * @note INTR1 -> bit 1 + * @note INTR2 -> bit 3 + * + * @param channel_u8: The value of output type select + * channel_u8 | result + * -----------------| ------------------ + * 0 | BMA2x2_ACCEL_INTR1_OUTPUT + * 1 | BMA2x2_ACCEL_INTR2_OUTPUT + * + * @param intr_output_type_u8: The value of output type select + * intr_source_u8 | result + * ------------------------ | ------------------ + * 0x01 | OPEN_DRAIN + * 0x00 | PUSS_PULL + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_output_type(u8 channel_u8, + u8 intr_output_type_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + com_rslt = E_BMA2x2_NULL_PTR; + } + else + { + switch (channel_u8) + { + /* write the output type*/ + case BMA2x2_INTR1_OUTPUT: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_INTR1_PAD_OUTPUT_TYPE_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, + BMA2x2_INTR1_PAD_OUTPUT_TYPE, intr_output_type_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_INTR1_PAD_OUTPUT_TYPE_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + case BMA2x2_INTR2_OUTPUT: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_INTR2_PAD_OUTPUT_TYPE_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, + BMA2x2_INTR2_PAD_OUTPUT_TYPE, intr_output_type_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_INTR2_PAD_OUTPUT_TYPE_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to get + * Active Level status in the register 0x20 + * @note INTR1 -> bit 0 + * @note INTR2 -> bit 2 + * + * @param channel_u8: The value of Active Level select + * channel_u8 | result + * -----------------| ------------------ + * 0 | BMA2x2_ACCEL_INTR1_LEVEL + * 1 | BMA2x2_ACCEL_INTR2_LEVEL + * + * @param intr_level_u8: The Active Level status enable value + * intr_level_u8 | result + * ------------------------ | ------------------ + * 0x01 | ACTIVE_HIGH + * 0x00 | ACTIVE_LOW + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_level(u8 channel_u8, + u8 *intr_level_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + com_rslt = E_BMA2x2_NULL_PTR; + } + else + { + switch (channel_u8) + { + /* read the active level*/ + case BMA2x2_INTR1_LEVEL: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_INTR1_PAD_ACTIVE_LEVEL_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *intr_level_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_INTR1_PAD_ACTIVE_LEVEL); + break; + case BMA2x2_INTR2_LEVEL: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_INTR2_PAD_ACTIVE_LEVEL_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *intr_level_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_INTR2_PAD_ACTIVE_LEVEL); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to set + * Active Level status in the register 0x20 + * @note INTR1 -> bit 0 + * @note INTR2 -> bit 2 + * + * @param channel_u8: The value of Active Level select + * channel_u8 | result + * -----------------| ------------------ + * 0 | BMA2x2_ACCEL_INTR1_LEVEL + * 1 | BMA2x2_ACCEL_INTR2_LEVEL + * + * @param intr_level_u8: The Active Level status enable value + * intr_level_u8 | result + * ------------------------ | ------------------ + * 0x01 | ACTIVE_HIGH + * 0x00 | ACTIVE_LOW + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_level(u8 channel_u8, + u8 intr_level_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + com_rslt = E_BMA2x2_NULL_PTR; + } + else + { + switch (channel_u8) + { + /* write the active level */ + case BMA2x2_INTR1_LEVEL: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_INTR1_PAD_ACTIVE_LEVEL_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, + BMA2x2_INTR1_PAD_ACTIVE_LEVEL, intr_level_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_INTR1_PAD_ACTIVE_LEVEL_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + case BMA2x2_INTR2_LEVEL: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_INTR2_PAD_ACTIVE_LEVEL_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, + BMA2x2_INTR2_PAD_ACTIVE_LEVEL, intr_level_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_INTR2_PAD_ACTIVE_LEVEL_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the reset interrupt in the register 0x21 bit 7 + * + * + * + * @param rst_intr_u8: The value of reset interrupt + * rst_intr_u8 | result + * ------------------------ | ------------------ + * 0x01 | clear any latch interrupt + * 0x00 | keep latch interrupt active + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_rst_intr(u8 rst_intr_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, BMA2x2_RESET_INTR_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_RESET_INTR, rst_intr_u8); + com_rslt += bma2x2_write_reg(BMA2x2_RESET_INTR_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + } + return com_rslt; +} +/*! + * @brief This API is used to get + * the latch duration in the register 0x21 bit from 0 to 3 + * + * @param latch_intr_u8: The value of latch duration + * latch_intr_u8 | result + * -----------------| ------------------ + * 0x00 | BMA2x2_LATCH_DURN_NON_LATCH + * 0x01 | BMA2x2_LATCH_DURN_250MS + * 0x02 | BMA2x2_LATCH_DURN_500MS + * 0x03 | BMA2x2_LATCH_DURN_1S + * 0x04 | BMA2x2_LATCH_DURN_2S + * 0x05 | BMA2x2_LATCH_DURN_4S + * 0x06 | BMA2x2_LATCH_DURN_8S + * 0x07 | BMA2x2_LATCH_DURN_LATCH + * 0x08 | BMA2x2_LATCH_DURN_NON_LATCH1 + * 0x09 | BMA2x2_LATCH_DURN_250US + * 0x0A | BMA2x2_LATCH_DURN_500US + * 0x0B | BMA2x2_LATCH_DURN_1MS + * 0x0C | BMA2x2_LATCH_DURN_12_5MS + * 0x0D | BMA2x2_LATCH_DURN_25MS + * 0x0E | BMA2x2_LATCH_DURN_50MS + * 0x0F | BMA2x2_LATCH_DURN_LATCH1 + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_latch_intr(u8 *latch_intr_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* read the latch duration */ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, BMA2x2_LATCH_INTR_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *latch_intr_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_LATCH_INTR); + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the latch duration in the register 0x21 bit from 0 to 3 + * + * @param latch_intr_u8: The value of latch duration + * latch_intr_u8 | result + * -----------------| ------------------ + * 0x00 | BMA2x2_LATCH_DURN_NON_LATCH + * 0x01 | BMA2x2_LATCH_DURN_250MS + * 0x02 | BMA2x2_LATCH_DURN_500MS + * 0x03 | BMA2x2_LATCH_DURN_1S + * 0x04 | BMA2x2_LATCH_DURN_2S + * 0x05 | BMA2x2_LATCH_DURN_4S + * 0x06 | BMA2x2_LATCH_DURN_8S + * 0x07 | BMA2x2_LATCH_DURN_LATCH + * 0x08 | BMA2x2_LATCH_DURN_NON_LATCH1 + * 0x09 | BMA2x2_LATCH_DURN_250US + * 0x0A | BMA2x2_LATCH_DURN_500US + * 0x0B | BMA2x2_LATCH_DURN_1MS + * 0x0C | BMA2x2_LATCH_DURN_12_5MS + * 0x0D | BMA2x2_LATCH_DURN_25MS + * 0x0E | BMA2x2_LATCH_DURN_50MS + * 0x0F | BMA2x2_LATCH_DURN_LATCH1 + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_latch_intr(u8 latch_intr_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 latch_durn_u8 = BMA2x2_INIT_VALUE; + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + if (latch_intr_u8 < BMA2x2_ACCEL_BW_MAX_RANGE) + { + switch (latch_intr_u8) + { + case BMA2x2_LATCH_DURN_NON_LATCH: + latch_durn_u8 = BMA2x2_LATCH_DURN_NON_LATCH; + + /* NON LATCH */ + break; + case BMA2x2_LATCH_DURN_250MS: + latch_durn_u8 = BMA2x2_LATCH_DURN_250MS; + + /* 250 MS */ + break; + case BMA2x2_LATCH_DURN_500MS: + latch_durn_u8 = BMA2x2_LATCH_DURN_500MS; + + /* 500 MS */ + break; + case BMA2x2_LATCH_DURN_1S: + latch_durn_u8 = BMA2x2_LATCH_DURN_1S; + + /* 1 S */ + break; + case BMA2x2_LATCH_DURN_2S: + latch_durn_u8 = BMA2x2_LATCH_DURN_2S; + + /* 2 S */ + break; + case BMA2x2_LATCH_DURN_4S: + latch_durn_u8 = BMA2x2_LATCH_DURN_4S; + + /* 4 S */ + break; + case BMA2x2_LATCH_DURN_8S: + latch_durn_u8 = BMA2x2_LATCH_DURN_8S; + + /* 8 S */ + break; + case BMA2x2_LATCH_DURN_LATCH: + latch_durn_u8 = BMA2x2_LATCH_DURN_LATCH; + + /* LATCH */ + break; + case BMA2x2_LATCH_DURN_NON_LATCH1: + latch_durn_u8 = BMA2x2_LATCH_DURN_NON_LATCH1; + + /* NON LATCH1 */ + break; + case BMA2x2_LATCH_DURN_250US: + latch_durn_u8 = BMA2x2_LATCH_DURN_250US; + + /* 250 US */ + break; + case BMA2x2_LATCH_DURN_500US: + latch_durn_u8 = BMA2x2_LATCH_DURN_500US; + + /* 500 US */ + break; + case BMA2x2_LATCH_DURN_1MS: + latch_durn_u8 = BMA2x2_LATCH_DURN_1MS; + + /* 1 MS */ + break; + case BMA2x2_LATCH_DURN_12_5MS: + latch_durn_u8 = BMA2x2_LATCH_DURN_12_5MS; + + /* 12.5 MS */ + break; + case BMA2x2_LATCH_DURN_25MS: + latch_durn_u8 = BMA2x2_LATCH_DURN_25MS; + + /* 25 MS */ + break; + case BMA2x2_LATCH_DURN_50MS: + latch_durn_u8 = BMA2x2_LATCH_DURN_50MS; + + /* 50 MS */ + break; + case BMA2x2_LATCH_DURN_LATCH1: + latch_durn_u8 = BMA2x2_LATCH_DURN_LATCH1; + + /* LATCH1 */ + break; + default: + break; + } + /* write the latch duration */ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, BMA2x2_LATCH_INTR_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_LATCH_INTR, latch_durn_u8); + com_rslt += bma2x2_write_reg(BMA2x2_LATCH_INTR_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + } + else + { + com_rslt = E_OUT_OF_RANGE; + } + } + return com_rslt; +} +/*! + * @brief This API is used to get the duration of + * Low, High, Slope and slow no motion interrupts in the registers + * @note LOW_DURN -> register 0x22 bit form 0 to 7 + * @note HIGH_DURN -> register 0x25 bit form 0 to 7 + * @note SLOPE_DURN -> register 0x27 bit form 0 to 1 + * @note SLO_NO_MOT_DURN -> register 0x27 bit form 2 to 7 + * + * @param channel_u8: The value of duration select + * channel_u8 | result + * -----------------| ------------------ + * 0 | BMA2x2_ACCEL_LOW_DURN + * 1 | BMA2x2_ACCEL_HIGH_DURN + * 2 | BMA2x2_ACCEL_SLOPE_DURN + * 3 | BMA2x2_ACCEL_SLOW_NO_MOTION_DURN + * + * @param durn_u8: The value of duration + * + * @note : + * Duration | result + * -----------------------| ------------------ + * BMA2x2_ACCEL_LOW_DURN | Low-g interrupt trigger + * - | delay according to([durn_u8 +1]*2)ms + * - | range from 2ms to 512ms. default is 20ms + * BMA2x2_ACCEL_HIGH_DURN | high-g interrupt trigger + * - | delay according to([durn_u8 +1]*2)ms + * - | range from 2ms to 512ms. default is 32ms + * BMA2x2_ACCEL_SLOPE_DURN| slope interrupt trigger + * - | if[durn_u8<1:0>+1] consecutive data points + * - | are above the slope interrupt threshold + * SLO_NO_MOT_DURN | Refer data sheet for clear information + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_durn(u8 channel_u8, + u8 *durn_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* write the duration data */ + switch (channel_u8) + { + case BMA2x2_LOW_DURN: + /*LOW DURATION*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, BMA2x2_LOW_DURN_ADDR, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *durn_u8 = data_u8; + break; + case BMA2x2_HIGH_DURN: + /*HIGH DURATION*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, BMA2x2_HIGH_DURN_ADDR, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *durn_u8 = data_u8; + break; + case BMA2x2_SLOPE_DURN: + /*SLOPE DURATION*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, BMA2x2_SLOPE_DURN_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *durn_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_SLOPE_DURN); + break; + case BMA2x2_SLOW_NO_MOTION_DURN: + /*SLO NO MOT DURATION*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_SLOW_NO_MOTION_DURN_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *durn_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_SLOW_NO_MOTION_DURN); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to set the duration of + * Low, High, Slope and slow no motion interrupts in the registers + * @note LOW_DURN -> register 0x22 bit form 0 to 7 + * @note HIGH_DURN -> register 0x25 bit form 0 to 7 + * @note SLOPE_DURN -> register 0x27 bit form 0 to 1 + * @note SLO_NO_MOT_DURN -> register 0x27 bit form 2 to 7 + * + * @param channel_u8: The value of duration select + * channel_u8 | result + * -----------------| ------------------ + * 0 | BMA2x2_ACCEL_LOW_DURN + * 1 | BMA2x2_ACCEL_HIGH_DURN + * 2 | BMA2x2_ACCEL_SLOPE_DURN + * 3 | BMA2x2_ACCEL_SLOW_NO_MOTION_DURN + * + * @param durn_u8: The value of duration + * + * @note : + * Duration | result + * -----------------------| ------------------ + * BMA2x2_ACCEL_LOW_DURN | Low-g interrupt trigger + * - | delay according to([durn_u8 +1]*2)ms + * - | range from 2ms to 512ms. default is 20ms + * BMA2x2_ACCEL_HIGH_DURN | high-g interrupt trigger + * - | delay according to([durn_u8 +1]*2)ms + * - | range from 2ms to 512ms. default is 32ms + * BMA2x2_ACCEL_SLOPE_DURN| slope interrupt trigger + * - | if[durn_u8<1:0>+1] consecutive data points + * - | are above the slope interrupt threshold + * SLO_NO_MOT_DURN | Refer data sheet for clear information + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_durn(u8 channel_u8, + u8 durn_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* write duration data */ + switch (channel_u8) + { + case BMA2x2_LOW_DURN: + /*LOW DURATION*/ + data_u8 = durn_u8; + com_rslt = bma2x2_write_reg(BMA2x2_LOW_DURN_ADDR, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + case BMA2x2_HIGH_DURN: + /*HIGH DURATION*/ + data_u8 = durn_u8; + com_rslt = bma2x2_write_reg( + BMA2x2_HIGH_DURN_ADDR, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + case BMA2x2_SLOPE_DURN: + /*SLOPE DURATION*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_SLOPE_DURN_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_SLOPE_DURN, durn_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_SLOPE_DURN_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + case BMA2x2_SLOW_NO_MOTION_DURN: + /*SLO NO MOT DURATION*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_SLOW_NO_MOTION_DURN_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_SLOW_NO_MOTION_DURN, durn_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_SLOW_NO_MOTION_DURN_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to get the threshold of + * Low, High, Slope and slow no motion interrupts in the registers + * @note LOW_THRES -> register 0x23 bit form 0 to 7 + * @note HIGH_THRES -> register 0x26 bit form 0 to 7 + * @note SLOPE_THRES -> register 0x28 bit form 0 to 7 + * @note SLO_NO_MOT_THRES -> register 0x29 bit form 0 to 7 + * + * @param channel_u8: The value of threshold selection + * channel_u8 | result + * -----------------| ------------------ + * 0 | BMA2x2_ACCEL_LOW_THRES + * 1 | BMA2x2_ACCEL_HIGH_THRES + * 2 | BMA2x2_ACCEL_SLOPE_THRES + * 3 | BMA2x2_ACCEL_SLOW_NO_MOTION_THRES + * + * @param thres_u8: The threshold value of selected interrupts + * + * @note : LOW-G THRESHOLD + * Threshold | result + * ---------------------------------| ------------------ + * BMA2x2_ACCEL_LOW_THRES | Low-threshold interrupt trigger + * | according to(thres_u8 * 7.81) mg + * | range from 0g to 1.992g + * | default is 375mg + * @note : HIGH-G THRESHOLD + * @note Threshold of high-g interrupt according to accel g range + * g-range | High-g threshold + * --------------------|---------------------------- + * 2g | (thres_u8 * 7.81) mg + * 4g | (thres_u8 * 15.63) mg + * 8g | (thres_u8 * 31.25) mg + * 16g | (thres_u8 * 62.5) mg + * + * @note : SLOPE THRESHOLD + * @note Threshold of slope interrupt according to accel g range + * g-range | Slope threshold + * --------------------|---------------------------- + * 2g | (thres_u8 * 3.19) mg + * 4g | (thres_u8 * 7.81) mg + * 8g | (thres_u8 * 15.63) mg + * 16g | (thres_u8 * 31.25) mg + * + * @note : SLOW NO MOTION THRESHOLD + * @note Threshold of slow no motion interrupt according to accel g range + * g-range | slow no motion threshold + * --------------------|---------------------------- + * 2g | (thres_u8 * 3.19) mg + * 4g | (thres_u8 * 7.81) mg + * 8g | (thres_u8 * 15.63) mg + * 16g | (thres_u8 * 31.25) mg + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_thres(u8 channel_u8, + u8 *thres_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + switch (channel_u8) + { + /* Read the threshold value */ + case BMA2x2_LOW_THRES: + /*LOW THRESHOLD*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, BMA2x2_LOW_THRES_ADDR, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *thres_u8 = data_u8; + break; + case BMA2x2_HIGH_THRES: + /*HIGH THRESHOLD*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_HIGH_THRES_ADDR, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *thres_u8 = data_u8; + break; + case BMA2x2_SLOPE_THRES: + /*SLOPE THRESHOLD*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_SLOPE_THRES_ADDR, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *thres_u8 = data_u8; + break; + case BMA2x2_SLOW_NO_MOTION_THRES: + /*SLO NO MOT THRESHOLD*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_SLOW_NO_MOTION_THRES_ADDR, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *thres_u8 = data_u8; + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to set the threshold of + * Low, High, Slope and slow no motion interrupts in the registers + * @note LOW_THRES -> register 0x23 bit form 0 to 7 + * @note HIGH_THRES -> register 0x26 bit form 0 to 7 + * @note SLOPE_THRES -> register 0x28 bit form 0 to 7 + * @note SLO_NO_MOT_THRES -> register 0x29 bit form 0 to 7 + * + * @param channel_u8: The value of threshold selection + * channel_u8 | result + * -----------------| ------------------ + * 0 | BMA2x2_ACCEL_LOW_THRES + * 1 | BMA2x2_ACCEL_HIGH_THRES + * 2 | BMA2x2_ACCEL_SLOPE_THRES + * 3 | BMA2x2_ACCEL_SLOW_NO_MOTION_THRES + * + * @param thres_u8: The threshold value of selected interrupts + * + * @note : LOW-G THRESHOLD + * Threshold | result + * ---------------------------------| ------------------ + * BMA2x2_ACCEL_LOW_THRES | Low-threshold interrupt trigger + * | according to(thres_u8 * 7.81) mg + * | range from 0g to 1.992g + * | default is 375mg + * @note : HIGH-G THRESHOLD + * @note Threshold of high-g interrupt according to accel g range + * g-range | High-g threshold + * --------------------|---------------------------- + * 2g | (thres_u8 * 7.81) mg + * 4g | (thres_u8 * 15.63) mg + * 8g | (thres_u8 * 31.25) mg + * 16g | (thres_u8 * 62.5) mg + * + * @note : SLOPE THRESHOLD + * @note Threshold of slope interrupt according to accel g range + * g-range | Slope threshold + * --------------------|---------------------------- + * 2g | (thres_u8 * 3.19) mg + * 4g | (thres_u8 * 7.81) mg + * 8g | (thres_u8 * 15.63) mg + * 16g | (thres_u8 * 31.25) mg + * + * @note : SLOW NO MOTION THRESHOLD + * @note Threshold of slow no motion interrupt according to accel g range + * g-range | slow no motion threshold + * --------------------|---------------------------- + * 2g | (thres_u8 * 3.19) mg + * 4g | (thres_u8 * 7.81) mg + * 8g | (thres_u8 * 15.63) mg + * 16g | (thres_u8 * 31.25) mg + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_thres(u8 channel_u8, + u8 thres_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + switch (channel_u8) + { + /* write the threshold value*/ + case BMA2x2_LOW_THRES: + /*LOW THRESHOLD*/ + data_u8 = thres_u8; + com_rslt = bma2x2_write_reg( + BMA2x2_LOW_THRES_ADDR, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + break; + case BMA2x2_HIGH_THRES: + /*HIGH THRESHOLD*/ + data_u8 = thres_u8; + com_rslt = bma2x2_write_reg( + BMA2x2_HIGH_THRES_ADDR, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + break; + case BMA2x2_SLOPE_THRES: + /*SLOPE THRESHOLD*/ + data_u8 = thres_u8; + com_rslt = bma2x2_write_reg( + BMA2x2_SLOPE_THRES_ADDR, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + break; + case BMA2x2_SLOW_NO_MOTION_THRES: + /*SLO NO MOT THRESHOLD*/ + data_u8 = thres_u8; + com_rslt = bma2x2_write_reg( + BMA2x2_SLOW_NO_MOTION_THRES_ADDR, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to get + * the low high hysteresis in the registers 0x24 + * @note LOW_G_HYST -> bit form 0 to 1 + * @note HIGH_G_HYST -> bit from 6 to 7 + * + * @param channel_u8: The value of hysteresis selection + * channel_u8 | result + * -----------------| ------------------ + * 0 | BMA2x2_ACCEL_LOW_G_HYST + * 1 | BMA2x2_ACCEL_HIGH_G_HYST + * + * @param hyst_u8: The hysteresis data + * + * @note LOW HYSTERESIS + * @note Hysteresis of low-g interrupt according to (hyst_u8 * 125)mg + * + * @note HIGH HYSTERESIS + * @note High hysteresis depends on the accel range selection + * g-range | High Hysteresis + * --------------------|---------------------------- + * 2g | (thres_u8 * 125) mg + * 4g | (thres_u8 * 250) mg + * 8g | (thres_u8 * 500) mg + * 16g | (thres_u8 * 1000) mg + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_low_high_g_hyst(u8 channel_u8, + u8 *hyst_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + switch (channel_u8) + { + /* read the hysteresis data */ + case BMA2x2_LOW_G_HYST: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_LOW_G_HYST_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *hyst_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_LOW_G_HYST); + break; + case BMA2x2_HIGH_G_HYST: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_HIGH_G_HYST_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *hyst_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_HIGH_G_HYST); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the low high hysteresis in the registers 0x24 + * @note LOW_G_HYST -> bit form 0 to 1 + * @note HIGH_G_HYST -> bit from 6 to 7 + * + * @param channel_u8: The value of hysteresis selection + * channel_u8 | result + * -----------------| ------------------ + * 0 | BMA2x2_ACCEL_LOW_G_HYST + * 1 | BMA2x2_ACCEL_HIGH_G_HYST + * + * @param hyst_u8: The hysteresis data + * + * @note LOW HYSTERESIS + * @note Hysteresis of low-g interrupt according to (hyst_u8 * 125)mg + * + * @note HIGH HYSTERESIS + * @note High hysteresis depends on the accel range selection + * g-range | High Hysteresis + * --------------------|---------------------------- + * 2g | (thres_u8 * 125) mg + * 4g | (thres_u8 * 250) mg + * 8g | (thres_u8 * 500) mg + * 16g | (thres_u8 * 1000) mg + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_low_high_g_hyst(u8 channel_u8, + u8 hyst_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + switch (channel_u8) + { + /* write the hysteresis data */ + case BMA2x2_LOW_G_HYST: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, BMA2x2_LOW_G_HYST_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_LOW_G_HYST, hyst_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_LOW_G_HYST_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + case BMA2x2_HIGH_G_HYST: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_HIGH_G_HYST_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_HIGH_G_HYST, hyst_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_HIGH_G_HYST_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to get + * low_g mode in the registers 0x24 bit 2 + * + * + * @param low_g_mode_u8: The value of Low_G mode + * low_g_mode_u8 | g-result + * --------------------|---------------------------- + * 0x00 | LOW_G_SINGLE_AXIS_MODE + * 0x01 | LOW_G_SUMMING_MODE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_low_g_mode(u8 *low_g_mode_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* read the low-g mode*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, BMA2x2_LOW_G_INTR_MODE_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *low_g_mode_u8 = BMA2x2_GET_BITSLICE(data_u8, + BMA2x2_LOW_G_INTR_MODE); + } + return com_rslt; +} +/*! + * @brief This API is used to set + * low_g mode in the registers 0x24 bit 2 + * + * + * @param low_g_mode_u8: The value of Low_G mode + * low_g_mode_u8 | result + * --------------------|---------------------------- + * 0x00 | LOW_G_SINGLE_AXIS_MODE + * 0x01 | LOW_G_SUMMING_MODE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_low_g_mode(u8 low_g_mode_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* write the low-g mode*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_LOW_G_INTR_MODE_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_LOW_G_INTR_MODE, low_g_mode_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_LOW_G_INTR_MODE_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + } + return com_rslt; +} +/*! + * @brief This API is used to get + * the tap duration in the register 0x2A bit form 0 to 2 + * + * + * @param tap_durn_u8: The value of tap duration + * tap_durn_u8 | result + * --------------------|---------------------------- + * 0x00 | TAP_DURN_50_MS + * 0x01 | TAP_DURN_100_MS + * 0x02 | TAP_DURN_150_MS + * 0x03 | TAP_DURN_200_MS + * 0x04 | TAP_DURN_250_MS + * 0x05 | TAP_DURN_375_MS + * 0x06 | TAP_DURN_500_MS + * 0x07 | TAP_DURN_700_MS + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_tap_durn(u8 *tap_durn_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* read the tap duration*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_TAP_DURN_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + *tap_durn_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_TAP_DURN); + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the tap duration in the register 0x2A bit form 0 to 2 + * + * + * @param tap_durn_u8: The value of tap duration + * tap_durn_u8 | result + * --------------------|---------------------- + * 0x00 | TAP_DURN_50_MS + * 0x01 | TAP_DURN_100_MS + * 0x02 | TAP_DURN_150_MS + * 0x03 | TAP_DURN_200_MS + * 0x04 | TAP_DURN_250_MS + * 0x05 | TAP_DURN_375_MS + * 0x06 | TAP_DURN_500_MS + * 0x07 | TAP_DURN_700_MS + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_tap_durn(u8 tap_durn_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* write the tap duration */ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC( + p_bma2x2->dev_addr, + BMA2x2_TAP_DURN_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_TAP_DURN, tap_durn_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_TAP_DURN_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + } + return com_rslt; +} +/*! + * @brief This API is used to get + * the tap shock form the register 0x2A bit 6 + * + * + * + * @param tap_shock_u8: The value of tap shock + * tap_shock_u8 | result + * --------------------|---------------------- + * 0x00 | TAP_SHOCK_50_MS + * 0x01 | TAP_SHOCK_75_MS + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_tap_shock(u8 *tap_shock_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* read tap shock value */ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_TAP_SHOCK_DURN_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *tap_shock_u8 = BMA2x2_GET_BITSLICE(data_u8, + BMA2x2_TAP_SHOCK_DURN); + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the tap shock form the register 0x2A bit 6 + * + * + * + * @param tap_shock_u8: The value of tap shock + * tap_shock_u8 | result + * --------------------|---------------------- + * 0x00 | TAP_SHOCK_50_MS + * 0x01 | TAP_SHOCK_75_MS + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_tap_shock(u8 tap_shock_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* write tap shock value*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_TAP_SHOCK_DURN_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE(data_u8, + BMA2x2_TAP_SHOCK_DURN, tap_shock_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_TAP_SHOCK_DURN_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + } + return com_rslt; +} +/*! + * @brief This API is used to get + * the tap quiet in the register 0x2A bit 7 + * + * + * + * @param tap_quiet_u8 : The value of tap quiet + * tap_quiet_u8 | result + * --------------------|---------------------- + * 0x00 | TAP_QUIET_30_MS + * 0x01 | TAP_QUIET_20_MS + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_tap_quiet(u8 *tap_quiet_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* read the tap quiet value*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_TAP_QUIET_DURN_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + *tap_quiet_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_TAP_QUIET_DURN); + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the tap quiet in the register 0x2A bit 7 + * + * + * + * @param tap_quiet_u8 : The value of tap quiet + * tap_quiet_u8 | result + * --------------------|---------------------- + * 0x00 | TAP_QUIET_30_MS + * 0x01 | TAP_QUIET_20_MS + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_tap_quiet(u8 tap_quiet_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* write the tap quiet value*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_TAP_QUIET_DURN_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE(data_u8, + BMA2x2_TAP_QUIET_DURN, tap_quiet_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_TAP_QUIET_DURN_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + } + return com_rslt; +} +/*! + * @brief This API is used to get + * the tap threshold in the register 0x2B bit from 0 to 4 + * + * + * + * @param tap_thres_u8 : The value of tap threshold + * @note Tap threshold of single and double tap corresponding + * to accel range + * range | Tap threshold + * --------------------|---------------------- + * 2g | (tap_thres_u8 * 62.5)mg + * 4g | (tap_thres_u8 * 125)mg + * 8g | (tap_thres_u8 * 250)mg + * 16g | (tap_thres_u8 * 500)mg + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_tap_thres(u8 *tap_thres_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* read the tap threshold*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_TAP_THRES_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *tap_thres_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_TAP_THRES); + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the tap threshold in the register 0x2B bit from 0 to 4 + * + * + * + * @param tap_thres_u8 : The value of tap threshold + * @note Tap threshold of single and double tap corresponding to accel range + * range | Tap threshold + * --------------------|---------------------- + * 2g | (tap_thres_u8 * 62.5)mg + * 4g | (tap_thres_u8 * 125)mg + * 8g | (tap_thres_u8 * 250)mg + * 16g | (tap_thres_u8 * 500)mg + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_tap_thres(u8 tap_thres_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_TAP_THRES_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_TAP_THRES, tap_thres_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_TAP_THRES_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + } + return com_rslt; +} +/*! + * @brief This API is used to get + * the tap sample in the register 0x2B bit 6 and 7 + * + * + * + * @param *tap_sample_u8 : The value of tap sample + * tap_sample_u8 | result + * --------------------|---------------------- + * 0x00 | 2 samples + * 0x01 | 4 samples + * 0x02 | 8 samples + * 0x03 | 16 samples + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_tap_sample(u8 *tap_sample_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* read tap samples */ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_TAP_SAMPLES_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + *tap_sample_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_TAP_SAMPLES); + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the tap sample in the register 0x2B bit 6 and 7 + * + * + * + * @param *tap_sample_u8 : The value of tap sample + * tap_sample_u8 | result + * --------------------|---------------------- + * 0x00 | 2 samples + * 0x01 | 4 samples + * 0x02 | 8 samples + * 0x03 | 16 samples + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_tap_sample(u8 tap_sample_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* write tap samples */ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, BMA2x2_TAP_SAMPLES_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_TAP_SAMPLES, tap_sample_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_TAP_SAMPLES_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + } + return com_rslt; +} +/*! + * @brief This API is used to get + * the orient mode in the register 0x2C bit 0 and 1 + * + * + * + * @param orient_mode_u8 : The value of orient mode + * orient_mode_u8 | result + * --------------------|------------------ + * 0x00 | symmetrical + * 0x01 | high asymmetrical + * 0x02 | low asymmetrical + * 0x03 | symmetrical + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_orient_mode(u8 *orient_mode_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC( + p_bma2x2->dev_addr, + BMA2x2_ORIENT_MODE_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + *orient_mode_u8 = BMA2x2_GET_BITSLICE( + data_u8, BMA2x2_ORIENT_MODE); + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the orient mode in the register 0x2C bit 0 and 1 + * + * + * + * @param orient_mode_u8 : The value of orient mode + * orient_mode_u8 | result + * --------------------|------------------ + * 0x00 | symmetrical + * 0x01 | high asymmetrical + * 0x02 | low asymmetrical + * 0x03 | symmetrical + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_orient_mode(u8 orient_mode_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ORIENT_MODE_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE(data_u8, + BMA2x2_ORIENT_MODE, orient_mode_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_ORIENT_MODE_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + } + return com_rslt; +} +/*! + * @brief This API is used to get + * the orient block in the register 0x2C bit 2 and 3 + * + * + * + * @param orient_block_u8 : The value of orient block + * orient_mode_u8 | result + * --------------------|------------------ + * 0x00 | no blocking + * 0x01 | theta blocking or + * | acceleration slope in any axis > 1.5g + * 0x02 | theta blocking or + * | acceleration slope in any axis > 0.2g + * | acceleration in any axis > 1.5g + * 0x03 | theta blocking or + * | acceleration slope in any axis > 0.4g + * | acceleration in any axis > 1.5g + * | value of orient is not stable for at lease 100ms + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_orient_block( + u8 *orient_block_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* Read the orient block data */ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ORIENT_BLOCK_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + *orient_block_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ORIENT_BLOCK); + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the orient block in the register 0x2C bit 2 and 3 + * + * + * + * @param orient_block_u8 : The value of orient block + * orient_mode_u8 | result + * --------------------|------------------ + * 0x00 | no blocking + * 0x01 | theta blocking or + * | acceleration slope in any axis > 1.5g + * 0x02 | theta blocking or + * | acceleration slope in any axis > 0.2g + * | acceleration in any axis > 1.5g + * 0x03 | theta blocking or + * | acceleration slope in any axis > 0.4g + * | acceleration in any axis > 1.5g + * | value of orient is not stable for at lease 100ms + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_orient_block(u8 orient_block_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* write the orient block data */ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ORIENT_BLOCK_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_ORIENT_BLOCK, orient_block_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_ORIENT_BLOCK_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + } + return com_rslt; +} +/*! + * @brief This API is used to get + * the orient hysteresis in the register 0x2C bit 4 to 6 + * + * + * + * @param orient_hyst_u8 : The value of orient hysteresis + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_orient_hyst(u8 *orient_hyst_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* read the orient hysteresis data*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ORIENT_HYST_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + *orient_hyst_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ORIENT_HYST); + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the orient hysteresis in the register 0x2C bit 4 to 6 + * + * + * + * @param orient_hyst_u8 : The value of orient hysteresis + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_orient_hyst(u8 orient_hyst_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* write the orient hysteresis data */ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ORIENT_HYST_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE(data_u8, + BMA2x2_ORIENT_HYST, orient_hyst_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_ORIENT_HYST_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + } + return com_rslt; +} +/*! + * @brief This API is used to get + * the theta value of orient and flat interrupts + * @note ORIENT_THETA -> register 0x2D bit 0 to 5 + * @note FLAT_THETA -> register 0x2E bit 0 to 5 + * + * @param channel_u8: The value of theta selection + * channel_u8 | result + * --------------------|------------------ + * 0x00 | BMA2x2_ACCEL_ORIENT_THETA + * 0x01 | BMA2x2_ACCEL_FLAT_THETA + * @note + * @note FLAT_THETA : Defines a blocking angle between 0 deg to 44.8 deg + * @note ORIENT_THETA : Defines threshold for detection of flat position + * in range from 0 deg to 44.8 deg + * + * @param theta_u8: The value of theta + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_theta(u8 channel_u8, + u8 *theta_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + switch (channel_u8) + { + /* write theta value*/ + case BMA2x2_ORIENT_THETA: + /*ORIENT THETA*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_THETA_BLOCK_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + *theta_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_THETA_BLOCK); + break; + case BMA2x2_FLAT_THETA: + /*FLAT THETA*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_THETA_FLAT_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *theta_u8 = data_u8; + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the theta value of orient and flat interrupts + * @note ORIENT_THETA -> register 0x2D bit 0 to 5 + * @note FLAT_THETA -> register 0x2E bit 0 to 5 + * + * @param channel_u8: The value of theta selection + * channel_u8 | result + * --------------------|------------------ + * 0x00 | BMA2x2_ACCEL_ORIENT_THETA + * 0x01 | BMA2x2_ACCEL_FLAT_THETA + * @note + * @note FLAT_THETA : Defines a blocking angle between 0 deg to 44.8 deg + * @note ORIENT_THETA : Defines threshold for detection of flat position + * in range from 0 deg to 44.8 deg + * + * @param theta_u8: The value of theta + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_theta(u8 channel_u8, + u8 theta_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + switch (channel_u8) + { + /* write flat value */ + case BMA2x2_ORIENT_THETA: + /*ORIENT THETA*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_THETA_BLOCK_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE(data_u8, + BMA2x2_THETA_BLOCK, theta_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_THETA_BLOCK_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + case BMA2x2_FLAT_THETA: + /*FLAT THETA*/ + data_u8 = theta_u8; + com_rslt = bma2x2_write_reg( + BMA2x2_THETA_FLAT_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to get + * the interrupt enable of orient ud_enable in the register 0x2D bit 6 + * + * + * @param orient_enable_u8 : The value of orient ud_enable + * orient_enable_u8 | result + * ------------------------- |------------------ + * 0x00 | Generates Interrupt + * 0x01 | Do not generate interrupt + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_orient_enable(u8 *orient_enable_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ORIENT_UD_ENABLE_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *orient_enable_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ORIENT_UD_ENABLE); + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the interrupt enable of orient ud_enable in the register 0x2D bit 6 + * + * + * @param orient_enable_u8 : The value of orient ud_enable + * orient_enable_u8 | result + * ------------------------- |------------------ + * 0x00 | Generates Interrupt + * 0x01 | Do not generate interrupt + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_orient_enable(u8 orient_enable_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ORIENT_UD_ENABLE_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE(data_u8, + BMA2x2_ORIENT_UD_ENABLE, orient_enable_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_ORIENT_UD_ENABLE_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + } + return com_rslt; +} +/*! + * @brief This API is used to get + * the interrupt enable of flat hysteresis("flat_hy) + * in the register 0x2F bit 0 to 2 + * + * + * + * + * @param flat_hyst_u8 : The value of flat hysteresis + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_flat_hyst(u8 *flat_hyst_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_FLAT_HYST_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + *flat_hyst_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_FLAT_HYST); + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the interrupt enable of flat hysteresis("flat_hy) + * in the register 0x2F bit 0 to 2 + * + * + * + * + * @param flat_hyst_u8 : The value of flat hysteresis + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_flat_hyst(u8 flat_hyst_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC( + p_bma2x2->dev_addr, + BMA2x2_FLAT_HYST_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_FLAT_HYST, flat_hyst_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_FLAT_HYST_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + } + return com_rslt; +} +/*! + * @brief This API is used to get + * the interrupt enable of flat hold time(flat_hold_time) + * in the register 0x2F bit 4 and 5 + * + * + * @param flat_hold_time_u8 : The value of flat hold time + * flat_hold_time_u8 | result + * ------------------------- |------------------ + * 0x00 | 0ms + * 0x01 | 512ms + * 0x02 | 1024ms + * 0x03 | 2048ms + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_flat_hold_time( + u8 *flat_hold_time_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* read the flat hold time */ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_FLAT_HOLD_TIME_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *flat_hold_time_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_FLAT_HOLD_TIME); + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the interrupt enable of flat hold time(flat_hold_time) + * in the register 0x2F bit 4 and 5 + * + * + * @param flat_hold_time_u8 : The value of flat hold time + * flat_hold_time_u8 | result + * ------------------------- |------------------ + * 0x00 | 0ms + * 0x01 | 512ms + * 0x02 | 1024ms + * 0x03 | 2048ms + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_flat_hold_time( + u8 flat_hold_time_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* write the flat hold time */ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_FLAT_HOLD_TIME_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_FLAT_HOLD_TIME, flat_hold_time_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_FLAT_HOLD_TIME_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + } + return com_rslt; +} +/*! + * @brief This API is used to get + * the fifo water mark level trigger in the register 0x30 bit from 0 to 5 + * + * + * + * + * @param fifo_wml_trig: The value of fifo watermark trigger level + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_fifo_wml_trig( + u8 *fifo_wml_trig) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* read the fifo water mark trigger */ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_FIFO_WML_TRIG_RETAIN_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *fifo_wml_trig = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_FIFO_WML_TRIG_RETAIN); + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the fifo water mark level trigger in the register 0x30 bit from 0 to 5 + * + * + * + * + * @param fifo_wml_trig: The value of fifo watermark trigger level + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_fifo_wml_trig( + u8 fifo_wml_trig) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + u8 power_mode = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + if (fifo_wml_trig < BMA2x2_FIFO_WML_RANGE) + { + /* write the fifo watermark trigger*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_FIFO_WML_TRIG_RETAIN_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_FIFO_WML_TRIG_RETAIN, + fifo_wml_trig); + com_rslt += bma2x2_get_power_mode(&power_mode); + com_rslt += bma2x2_set_power_mode(BMA2x2_MODE_STANDBY); + com_rslt += bma2x2_write_reg( + BMA2x2_FIFO_WML_TRIG_RETAIN_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + com_rslt += bma2x2_set_power_mode(power_mode); + } + else + { + com_rslt = E_OUT_OF_RANGE; + } + } + return com_rslt; +} +/*! + * @brief This API is for to get + * the self test axis(self_test_axis) in the register ox32 bit 0 to 2 + * + * + * + * @param selftest_axis_u8 : The value of selftest axis + * selftest_axis_u8 | result + * ------------------------- |------------------ + * 0x00 | self test disable + * 0x01 | x-axis + * 0x02 | y-axis + * 0x03 | z-axis + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_selftest_axis( + u8 *selftest_axis_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* read the self test axis*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_SELFTEST_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *selftest_axis_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_SELFTEST); + } + return com_rslt; +} +/*! + * @brief This API is for to set + * the self test axis(self_test_axis) in the register ox32 bit 0 to 2 + * + * + * + * @param selftest_axis_u8 : The value of selftest axis + * selftest_axis_u8 | result + * ------------------------- |------------------ + * 0x00 | self test disable + * 0x01 | x-axis + * 0x02 | y-axis + * 0x03 | z-axis + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_selftest_axis( + u8 selftest_axis_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + if (selftest_axis_u8 < BMA2x2_SELF_TEST_AXIS_RANGE) + { + /* write the self test axis*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_SELFTEST_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_ENABLE_SELFTEST, selftest_axis_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_ENABLE_SELFTEST_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + } + else + { + com_rslt = E_OUT_OF_RANGE; + } + } + return com_rslt; +} +/*! + * @brief This API is for to get + * the Self Test sign(selftest_sign) in the register 0x32 bit 2 + * + * + * + * @param selftest_sign_u8 : The value of self test sign + * selftest_sign_u8 | result + * ------------------------- |------------------ + * 0x00 | negative sign + * 0x01 | positive sign + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_selftest_sign( + u8 *selftest_sign_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* read self test sign */ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_NEG_SELFTEST_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *selftest_sign_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_NEG_SELFTEST); + } + return com_rslt; +} +/*! + * @brief This API is for to set + * the Self Test sign(selftest_sign) in the register 0x32 bit 2 + * + * + * + * @param selftest_sign_u8 : The value of self test sign + * selftest_sign_u8 | result + * ------------------------- |------------------ + * 0x00 | negative sign + * 0x01 | positive sign + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_selftest_sign( + u8 selftest_sign_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + if (selftest_sign_u8 < + BMA2x2_SELF_TEST_SIGN_RANGE) + { + /* write self test sign */ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_NEG_SELFTEST_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_NEG_SELFTEST, selftest_sign_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_NEG_SELFTEST_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + } + else + { + com_rslt = E_OUT_OF_RANGE; + } + } + return com_rslt; +} +/*! + * @brief This API is used to get + * the nvm program mode(nvm_prog_mode)in the register 0x33 bit 0 + * + * + * @param nvmprog_mode_u8 : The value of nvm program mode + * nvmprog_mode_u8 | result + * ------------------------- |------------------ + * 0x00 | Disable program mode + * 0x01 | Enable program mode + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_nvmprog_mode( + u8 *nvmprog_mode_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + com_rslt = E_BMA2x2_NULL_PTR; + } + else + { + /* read the nvm program mode*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_UNLOCK_EE_PROG_MODE_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *nvmprog_mode_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_UNLOCK_EE_PROG_MODE); + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the nvm program mode(nvm_prog_mode)in the register 0x33 bit 0 + * + * + * @param nvmprog_mode_u8 : The value of nvm program mode + * nvmprog_mode_u8 | result + * ------------------------- |------------------ + * 0x00 | Disable program mode + * 0x01 | Enable program mode + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_nvmprog_mode(u8 nvmprog_mode_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + com_rslt = E_BMA2x2_NULL_PTR; + } + else + { + /* write the nvm program mode*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_UNLOCK_EE_PROG_MODE_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_UNLOCK_EE_PROG_MODE, nvmprog_mode_u8); + com_rslt += bma2x2_write_reg + (BMA2x2_UNLOCK_EE_PROG_MODE_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the value of nvm program trig in the register 0x33 bit 1 + * + * + * + * + * @param nvprog_trig_u8: The value of nvm program trig + * nvprog_trig_u8 | result + * ------------------------- |------------------ + * 0x00 | Do not trigger nvm program + * 0x01 | Trigger nvm program + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_nvprog_trig(u8 nvprog_trig_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + com_rslt = E_BMA2x2_NULL_PTR; + } + else + { + /* set the nvm program trigger */ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_START_EE_PROG_TRIG_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_START_EE_PROG_TRIG, nvprog_trig_u8); + com_rslt += bma2x2_write_reg + (BMA2x2_START_EE_PROG_TRIG_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + } + return com_rslt; +} +/*! + * @brief This API is used to get + * the nvm program ready in the register bit 2 + * + * + * @param nvprog_ready_u8: The value of nvm program ready + * nvprog_ready_u8 | result + * ------------------------- |------------------ + * 0x00 | nvm write/update operation is in progress + * 0x01 | nvm is ready to accept a new write + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_nvmprog_ready(u8 *nvprog_ready_u8) +{ + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 data_u8 = BMA2x2_INIT_VALUE; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + com_rslt = E_BMA2x2_NULL_PTR; + } + else + { + /* read the nvm program ready*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_EE_PROG_READY_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *nvprog_ready_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_EE_PROG_READY); + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the nvm program ready in the register bit 2 + * + * + * @param nvprog_remain_u8: The value of nvm program ready + * nvprog_remain_u8 | result + * ------------------------- |------------------ + * 0x00 | nvm write/update operation is in progress + * 0x01 | nvm is ready to accept a new write + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_nvmprog_remain(u8 *nvprog_remain_u8) +{ + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Check the struct p_bma2x2 is empty */ + if (BMA2x2_NULL == p_bma2x2) + { + com_rslt = E_BMA2x2_NULL_PTR; + } + else + { + /* write the nvm program ready*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_EE_REMAIN_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + *nvprog_remain_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_EE_REMAIN); + } + return com_rslt; +} +/*! + * @brief This API is used to get the enable status of spi3 + * in the register 0x34 bit 0 + * + * + * + * @param spi3_u8 : The value of SPI 3 or 4 wire enable + * spi3_u8 | result + * ------------------------- |------------------ + * 0x00 | spi4 + * 0x01 | spi3 + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_spi3(u8 *spi3_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* read the spi status*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_SPI_MODE_3_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *spi3_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_SPI_MODE_3); + } + return com_rslt; +} +/*! + * @brief This API is used to set the enable status of spi3 + * in the register 0x34 bit 0 + * + * + * + * @param spi3_u8 : The value of SPI 3 or 4 wire enable + * spi3_u8 | result + * ------------------------- |------------------ + * 0x00 | spi4 + * 0x01 | spi3 + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_spi3(u8 spi3_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /* write the spi status*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_SPI_MODE_3_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_ENABLE_SPI_MODE_3, spi3_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_ENABLE_SPI_MODE_3_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + } + return com_rslt; +} +/*! + * @brief This API is used to get the i2c + * watch dog timer period and I2C interface mode is selected + * in the register 0x34 bit 1 and 2 + * + * + * @param channel_u8: The i2c option selection + * channel_u8 | result + * ------------------------- |------------------ + * 0 | BMA2x2_ACCEL_I2C_SELECT + * 1 | BMA2x2_ACCEL_I2C_ENABLE + * + * @param i2c_wdt_u8: watch dog timer period + * and I2C interface mode is selected + * BMA2x2_ACCEL_I2C_SELECT| result + * ------------------------- |------------------ + * 0x00 | Disable the watchdog at SDI pin + * 0x01 | Enable watchdog + * + * BMA2x2_I2C_ENABLE | result + * ------------------------- |------------------ + * 0x00 | 1ms + * 0x01 | 50ms + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_i2c_wdt(u8 channel_u8, + u8 *i2c_wdt_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + switch (channel_u8) + { + case BMA2x2_I2C_SELECT: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_I2C_WDT_PERIOD_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *i2c_wdt_u8 = BMA2x2_GET_BITSLICE(data_u8, + BMA2x2_I2C_WDT_PERIOD); + break; + case BMA2x2_I2C_ENABLE: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_I2C_WDT_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *i2c_wdt_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_I2C_WDT); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to set the i2c + * watch dog timer period and I2C interface mode is selected + * in the register 0x34 bit 1 and 2 + * + * + * @param channel_u8: The i2c option selection + * channel_u8 | result + * ------------------------- |------------------ + * 0 | BMA2x2_ACCEL_I2C_SELECT + * 1 | BMA2x2_ACCEL_I2C_ENABLE + * + * @param i2c_wdt_u8: watch dog timer period + * and I2C interface mode is selected + * BMA2x2_ACCEL_I2C_SELECT| result + * ------------------------- |------------------ + * 0x00 | Disable the watchdog at SDI pin + * 0x01 | Enable watchdog + * + * BMA2x2_I2C_ENABLE | result + * ------------------------- |------------------ + * 0x00 | 1ms + * 0x01 | 50ms + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_i2c_wdt(u8 channel_u8, + u8 i2c_wdt_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + switch (channel_u8) + { + case BMA2x2_I2C_SELECT: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_I2C_WDT_PERIOD_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, + BMA2x2_I2C_WDT_PERIOD, i2c_wdt_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_I2C_WDT_PERIOD_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + case BMA2x2_I2C_ENABLE: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_I2C_WDT_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, + BMA2x2_ENABLE_I2C_WDT, i2c_wdt_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_ENABLE_I2C_WDT_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to get + * slow compensation(hp_x_enable, hp_y_enable and hp_z_enable) enable + * in the register 0x36 bit 0 to 2 + * @note SLOW_COMP_X -> bit 0 + * @note SLOW_COMP_Y -> bit 1 + * @note SLOW_COMP_Z -> bit 2 + * + * + * @param channel_u8: The value of slow compensation selection + * channel_u8 | result + * ------------------------- |------------------ + * 0 | BMA2x2_ACCEL_SLOW_COMP_X + * 1 | BMA2x2_ACCEL_SLOW_COMP_Y + * 2 | BMA2x2_ACCEL_SLOW_COMP_Z + * + * @param slow_comp_u8: The value of slow compensation enable + * slow_comp_u8 | result + * ------------------------- |------------------ + * 0x00 | Disable + * 0x01 | Enable + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_slow_comp(u8 channel_u8, + u8 *slow_comp_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + switch (channel_u8) + { + case BMA2x2_SLOW_COMP_X: + /*SLOW COMP X*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_SLOW_COMP_X_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *slow_comp_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_SLOW_COMP_X); + break; + case BMA2x2_SLOW_COMP_Y: + /*SLOW COMP Y*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_SLOW_COMP_Y_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *slow_comp_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_SLOW_COMP_Y); + break; + case BMA2x2_SLOW_COMP_Z: + /*SLOW COMP Z*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_SLOW_COMP_Z_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *slow_comp_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_ENABLE_SLOW_COMP_Z); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to set + * slow compensation(hp_x_enable, hp_y_enable and hp_z_enable) enable + * in the register 0x36 bit 0 to 2 + * @note SLOW_COMP_X -> bit 0 + * @note SLOW_COMP_Y -> bit 1 + * @note SLOW_COMP_Z -> bit 2 + * + * + * @param channel_u8: The value of slow compensation selection + * channel_u8 | result + * ------------------------- |------------------ + * 0 | BMA2x2_ACCEL_SLOW_COMP_X + * 1 | BMA2x2_ACCEL_SLOW_COMP_Y + * 2 | BMA2x2_ACCEL_SLOW_COMP_Z + * + * @param slow_comp_u8: The value of slow compensation enable + * slow_comp_u8 | result + * ------------------------- |------------------ + * 0x00 | Disable + * 0x01 | Enable + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_slow_comp(u8 channel_u8, + u8 slow_comp_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + switch (channel_u8) + { + case BMA2x2_SLOW_COMP_X: + /*SLOW COMP X*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_SLOW_COMP_X_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, + BMA2x2_ENABLE_SLOW_COMP_X, slow_comp_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_ENABLE_SLOW_COMP_X_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + case BMA2x2_SLOW_COMP_Y: + /*SLOW COMP Y*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_SLOW_COMP_Y_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, + BMA2x2_ENABLE_SLOW_COMP_Y, slow_comp_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_ENABLE_SLOW_COMP_Y_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + case BMA2x2_SLOW_COMP_Z: + /*SLOW COMP Z*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_ENABLE_SLOW_COMP_Z_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, + BMA2x2_ENABLE_SLOW_COMP_Z, slow_comp_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_ENABLE_SLOW_COMP_Z_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to get + * the status of fast offset compensation(cal_rdy) in the register 0x36 + * bit 4(Read Only Possible) + * + * + * + * @param cal_rdy_u8: The value of cal_ready + * + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_cal_rdy(u8 *cal_rdy_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_FAST_CAL_RDY_STAT_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *cal_rdy_u8 = BMA2x2_GET_BITSLICE(data_u8, + BMA2x2_FAST_CAL_RDY_STAT); + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the status of fast offset compensation(cal_rdy) in the register 0x36 + * bit 4(Read Only Possible) + * + * + * + * @param cal_trigger_u8: The value of cal_ready + * + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_cal_trigger(u8 cal_trigger_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_CAL_TRIGGER_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE(data_u8, + BMA2x2_CAL_TRIGGER, cal_trigger_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_CAL_TRIGGER_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the offset reset(offset_reset) in the register 0x36 + * bit 7(Write only possible) + * + * + * + * @param offset_rst_u8: The offset reset value + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_offset_rst(u8 offset_rst_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_RST_OFFSET_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_RST_OFFSET, + offset_rst_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_RST_OFFSET_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + } + return com_rslt; +} +/*! + * @brief This API is used to get + * the status of offset target axis(offset_target_x, offset_target_y and + * offset_target_z) and cut_off in the register 0x37 + * @note CUT_OFF -> bit 0 + * @note OFFSET_TRIGGER_X -> bit 1 and 2 + * @note OFFSET_TRIGGER_Y -> bit 3 and 4 + * @note OFFSET_TRIGGER_Z -> bit 5 and 6 + * + * + * @param channel_u8: The value of offset axis selection + * channel_u8 | result + * ------------------------- |------------------ + * 0 | BMA2x2_ACCEL_CUT_OFF + * 1 | BMA2x2_ACCEL_OFFSET_TRIGGER_X + * 2 | BMA2x2_ACCEL_OFFSET_TRIGGER_Y + * 2 | BMA2x2_ACCEL_OFFSET_TRIGGER_Z + * + * @param offset_u8: The offset target value + * CUT_OFF | result + * ------------------------- |------------------ + * 0 | 1Hz + * 1 | 10Hz + * + * + * OFFSET_TRIGGER | result + * ------------------------- |------------------ + * 0x00 | 0g + * 0x01 | +1g + * 0x02 | -1g + * 0x03 | 0g + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_offset_target(u8 channel_u8, + u8 *offset_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + switch (channel_u8) + { + case BMA2x2_CUT_OFF: + /*CUT-OFF*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_COMP_CUTOFF_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + *offset_u8 = BMA2x2_GET_BITSLICE(data_u8, + BMA2x2_COMP_CUTOFF); + break; + case BMA2x2_OFFSET_TRIGGER_X: + /*OFFSET TRIGGER X*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_COMP_TARGET_OFFSET_X_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *offset_u8 = BMA2x2_GET_BITSLICE(data_u8, + BMA2x2_COMP_TARGET_OFFSET_X); + break; + case BMA2x2_OFFSET_TRIGGER_Y: + /*OFFSET TRIGGER Y*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_COMP_TARGET_OFFSET_Y_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *offset_u8 = BMA2x2_GET_BITSLICE(data_u8, + BMA2x2_COMP_TARGET_OFFSET_Y); + break; + case BMA2x2_OFFSET_TRIGGER_Z: + /*OFFSET TRIGGER Z*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_COMP_TARGET_OFFSET_Z_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *offset_u8 = BMA2x2_GET_BITSLICE + (data_u8, BMA2x2_COMP_TARGET_OFFSET_Z); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the status of offset target axis(offset_target_x, offset_target_y and + * offset_target_z) and cut_off in the register 0x37 + * @note CUT_OFF -> bit 0 + * @note OFFSET_TRIGGER_X -> bit 1 and 2 + * @note OFFSET_TRIGGER_Y -> bit 3 and 4 + * @note OFFSET_TRIGGER_Z -> bit 5 and 6 + * + * + * @param channel_u8: The value of offset axis selection + * channel_u8 | result + * ------------------------- |------------------ + * 0 | BMA2x2_ACCEL_CUT_OFF + * 1 | BMA2x2_ACCEL_OFFSET_TRIGGER_X + * 2 | BMA2x2_ACCEL_OFFSET_TRIGGER_Y + * 2 | BMA2x2_ACCEL_OFFSET_TRIGGER_Z + * + * @param offset_u8: The offset target value + * CUT_OFF | result + * ------------------------- |------------------ + * 0 | 1Hz + * 1 | 10Hz + * + * + * OFFSET_TRIGGER | result + * ------------------------- |------------------ + * 0x00 | 0g + * 0x01 | +1g + * 0x02 | -1g + * 0x03 | 0g + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_offset_target(u8 channel_u8, + u8 offset_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + switch (channel_u8) + { + case BMA2x2_CUT_OFF: + /*CUT-OFF*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_COMP_CUTOFF_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_COMP_CUTOFF, offset_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_COMP_CUTOFF_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + case BMA2x2_OFFSET_TRIGGER_X: + /*OFFSET TARGET X*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_COMP_TARGET_OFFSET_X_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_COMP_TARGET_OFFSET_X, offset_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_COMP_TARGET_OFFSET_X_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + case BMA2x2_OFFSET_TRIGGER_Y: + /*OFFSET TARGET Y*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_COMP_TARGET_OFFSET_Y_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_COMP_TARGET_OFFSET_Y, offset_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_COMP_TARGET_OFFSET_Y_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + case BMA2x2_OFFSET_TRIGGER_Z: + /*OFFSET TARGET Z*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_COMP_TARGET_OFFSET_Z_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, BMA2x2_COMP_TARGET_OFFSET_Z, offset_u8); + com_rslt += bma2x2_write_reg( + BMA2x2_COMP_TARGET_OFFSET_Z_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to get the status of offset + * (offset_x, offset_y and offset_z) in the registers 0x38,0x39 and 0x3A + * @note offset_x -> register 0x38 bit 0 to 7 + * @note offset_y -> register 0x39 bit 0 to 7 + * @note offset_z -> register 0x3A bit 0 to 7 + * + * + * @param channel_u8: The value of offset selection + * channel_u8 | result + * ------------------------- |------------------ + * 0 | BMA2x2_ACCEL_X_AXIS + * 1 | BMA2x2_ACCEL_Y_AXIS + * 2 | BMA2x2_ACCEL_Z_AXIS + * + * @param offset_u8: The value of offset + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_offset(u8 channel_u8, + s8 *offset_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + switch (channel_u8) + { + case BMA2x2_X_AXIS: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_OFFSET_X_AXIS_ADDR, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + *offset_u8 = (s8)data_u8; + break; + case BMA2x2_Y_AXIS: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_OFFSET_Y_AXIS_ADDR, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + *offset_u8 = (s8)data_u8; + break; + case BMA2x2_Z_AXIS: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_OFFSET_Z_AXIS_ADDR, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + *offset_u8 = (s8)data_u8; + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to set the status of offset + * (offset_x, offset_y and offset_z) in the registers 0x38,0x39 and 0x3A + * @note offset_x -> register 0x38 bit 0 to 7 + * @note offset_y -> register 0x39 bit 0 to 7 + * @note offset_z -> register 0x3A bit 0 to 7 + * + * + * @param channel_u8: The value of offset selection + * channel_u8 | result + * ------------------------- |------------------ + * 0 | BMA2x2_ACCEL_X_AXIS + * 1 | BMA2x2_ACCEL_Y_AXIS + * 2 | BMA2x2_ACCEL_Z_AXIS + * + * @param offset_u8: The value of offset + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_offset(u8 channel_u8, + s8 offset_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + switch (channel_u8) + { + case BMA2x2_X_AXIS: + data_u8 = offset_u8; + com_rslt = bma2x2_write_reg( + BMA2x2_OFFSET_X_AXIS_ADDR, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + break; + case BMA2x2_Y_AXIS: + data_u8 = offset_u8; + com_rslt = bma2x2_write_reg( + BMA2x2_OFFSET_Y_AXIS_ADDR, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + break; + case BMA2x2_Z_AXIS: + data_u8 = offset_u8; + com_rslt = bma2x2_write_reg( + BMA2x2_OFFSET_Z_AXIS_ADDR, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + break; + default: + com_rslt = E_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API is used to get + * the status of fifo (fifo_mode) in the register 0x3E bit 6 and 7 + * + * + * @param fifo_mode_u8 : The value of fifo mode + * fifo_mode_u8 | result + * ------------------------- |------------------ + * 0x00 | BYPASS + * 0x01 | FIFO + * 0x02 | STREAM + * 0x03 | RESERVED + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_fifo_mode(u8 *fifo_mode_u8) +{ + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 data_u8 = BMA2x2_INIT_VALUE; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC( + p_bma2x2->dev_addr, + BMA2x2_FIFO_MODE_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + *fifo_mode_u8 = BMA2x2_GET_BITSLICE(data_u8, + BMA2x2_FIFO_MODE); + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the status of fifo (fifo_mode) in the register 0x3E bit 6 and 7 + * + * + * @param fifo_mode_u8 : The value of fifo mode + * fifo_mode_u8 | result + * ------------------------- |------------------ + * 0x00 | BYPASS + * 0x01 | FIFO + * 0x02 | STREAM + * 0x03 | RESERVED + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * @retval -127 -> Null Pointer Error + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_fifo_mode(u8 fifo_mode_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + u8 power_mode = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + com_rslt = E_BMA2x2_NULL_PTR; + } + else + { + if (fifo_mode_u8 < BMA2x2_FIFO_MODE_RANGE) + { + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_FIFO_MODE_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE(data_u8, + BMA2x2_FIFO_MODE, fifo_mode_u8); + data_u8 |= 0x0C; + /*Power mode is switched to Standby power mode*/ + com_rslt += bma2x2_get_power_mode(&power_mode); + com_rslt += bma2x2_set_power_mode(BMA2x2_MODE_STANDBY); + /*Configure the mode in FIFO_CONFIG registers*/ + com_rslt += bma2x2_write_reg( + BMA2x2_FIFO_MODE_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + if (com_rslt == SUCCESS) + { + /*FIFO config is stored in struct p_bma2x2*/ + p_bma2x2->fifo_config = data_u8; + } + /*Power mode is reverted to previously set mode */ + com_rslt += bma2x2_set_power_mode(power_mode); + + } + else + { + com_rslt = E_OUT_OF_RANGE; + } + } + return com_rslt; +} +/*! + * @brief This API is used to get + * the axis enable of fifo data select in the register 0x3E bit 0 and 1 + * + * + * @param fifo_data_select_u8 : The value of FIFO axis data select + * fifo_data_select_u8 | result + * ------------------------- |------------------ + * 0x00 | XYZ + * 0x01 | Y + * 0x02 | X + * 0x03 | Z + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_fifo_data_select( + u8 *fifo_data_select_u8) +{ + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 data_u8 = BMA2x2_INIT_VALUE; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC( + p_bma2x2->dev_addr, + BMA2x2_FIFO_DATA_SELECT_REG, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *fifo_data_select_u8 = BMA2x2_GET_BITSLICE(data_u8, + BMA2x2_FIFO_DATA_SELECT); + } + return com_rslt; +} +/*! + * @brief This API is used to set + * the axis enable of fifo data select in the register 0x3E bit 0 and 1 + * + * + * @param fifo_data_select_u8 : The value of FIFO axis data select + * fifo_data_select_u8 | result + * ------------------------- |------------------ + * 0x00 | XYZ + * 0x01 | Y + * 0x02 | X + * 0x03 | Z + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * @retval -127 -> Null Pointer Error + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_fifo_data_select( + u8 fifo_data_select_u8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + u8 power_mode = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + com_rslt = E_BMA2x2_NULL_PTR; + } + else + { + if (fifo_data_select_u8 < BMA2x2_FIFO_DATA_SELECT_RANGE) + { + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_FIFO_DATA_SELECT_REG, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + data_u8 = BMA2x2_SET_BITSLICE + (data_u8, + BMA2x2_FIFO_DATA_SELECT, fifo_data_select_u8); + data_u8 |= 0x0C; + /*Power mode is switched to Standby power mode*/ + com_rslt += bma2x2_get_power_mode(&power_mode); + com_rslt += bma2x2_set_power_mode(BMA2x2_MODE_STANDBY); + /* Configure appropriate (X,Y,Z) axes data to be + available in FIFO*/ + com_rslt += bma2x2_write_reg( + BMA2x2_FIFO_DATA_SELECT_REG, &data_u8, 1); + if (com_rslt == SUCCESS) + { + /*FIFO config is stored in struct p_bma2x2*/ + p_bma2x2->fifo_config = data_u8; + } + /*Power mode is reverted to previously set mode */ + com_rslt += bma2x2_set_power_mode(power_mode); + } + else + { + com_rslt = E_OUT_OF_RANGE; + } + } + return com_rslt; +} + +/*! + * @brief This API reads the FIFO data from the register 0x3F + * and store the data in the user defined buffer mapped to the member + * of structure "fifo_configuration" + * + * @note Before calling this API user must map the following FIFO settings + * required to read the FIFO data to the structure "fifo_configuration" + * - Data buffer to store the FIFO data is mapped to + * the structure member "fifo_data" + * - Number of bytes to be read from FIFO is mapped to + * the structure member "fifo_length" + * + * @note The number of bytes to be read from the FIFO is specified in the + * member "fifo_length" of the structure "fifo_configuration" + * + * @param[in,out] fifo_conf : Structure containing the FIFO configurations + * is passed as input and FIFO data of specified length is obtained as output + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * @retval -127 -> Null Pointer Error + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_fifo_data( + struct fifo_configuration *fifo_conf) +{ + u8 fifo_frame_count = 0; + u8 fifo_data_bytes = 0; + u8 fifo_data_select = 0; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL || fifo_conf->fifo_data == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + com_rslt = E_BMA2x2_NULL_PTR; + } + else + { + /*Resetting the FIFO data byte index*/ + fifo_conf->accel_byte_start_index = 0; + /*Frames in FIFO is stored */ + com_rslt = bma2x2_get_fifo_frame_count(&fifo_frame_count); + /*FIFO data select value is stored*/ + com_rslt += bma2x2_get_fifo_data_select(&fifo_data_select); + /*Number of bytes in FIFO is calculated*/ + if (fifo_data_select == BMA2x2_FIFO_XYZ_DATA_ENABLED) + { + /*Number of bytes in FIFO when XYZ data are enabled*/ + fifo_data_bytes = fifo_frame_count * + BMA2x2_FIFO_XYZ_AXES_FRAME_SIZE; + } + else + { + /*No of bytes in FIFO when single axis data enabled*/ + fifo_data_bytes = fifo_frame_count * + BMA2x2_FIFO_SINGLE_AXIS_FRAME_SIZE; + } + /*Handled the case where user requests to read more FIFO + length than available FIFO data*/ + if (fifo_conf->fifo_length > fifo_data_bytes) + { + /*Number of bytes in FIFO is read entirely when user + reads more FIFO data than available*/ + fifo_conf->fifo_length = fifo_data_bytes; + } + /*Read the FIFO data*/ + com_rslt += p_bma2x2->BMA2x2_BUS_READ_FUNC(p_bma2x2->dev_addr, + BMA2x2_FIFO_DATA_OUTPUT_ADDR, fifo_conf->fifo_data, + fifo_conf->fifo_length); + } + return com_rslt; +} + +/*! + * @brief This API extracts the accel data from the FIFO frames + * + * @note The bma2x2_extract_accel() API should be called only after reading + * the FIFO data by calling the bma2x2_read_fifo_data() API + * + * @param[in,out] accel_frame : Instance of the union where accel data + * in FIFO is parsed and stored + * + * @param[in,out] accel_frame_count: Number of Accel frames requested by user + * is got as input and number of + * accel frames parsed and stored is + * returned as output to user + * + * @param[in, out] fifo_conf : FIFO configuration structure. + * It provides the following as input + * - user defined buffer + * - length of FIFO data read + * It returns the accel_byte_start_index + * (index of accel bytes parsed from FIFO) + * + * @return results of API execution status + * @retval 0 -> Success + * @retval -127 -> Error + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_extract_accel(union fifo_frame *accel_frame, + u8 *accel_frame_count, struct fifo_configuration *fifo_conf) +{ + u8 data_index = 0; + u8 accel_index = 0; + u8 data_read_length = 0; + u8 fifo_data_select = 0; + /* Variable used to return value of communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = 0; + + if (p_bma2x2 == BMA2x2_NULL || fifo_conf->fifo_data == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty and FIFO data buffer + not being mapped to fifo_configuration structure */ + com_rslt = E_BMA2x2_NULL_PTR; + } + else + { + /* FIFO data enable value is stored in fifo_data_select*/ + fifo_data_select = p_bma2x2->fifo_config & + BMA2x2_FIFO_DATA_ENABLED_MASK; + /* FIFO bytes available for parsing is obtained in + data_read_length*/ + get_accel_len_to_parse(&data_index, &data_read_length, + *accel_frame_count, fifo_data_select, fifo_conf); + /*Parse the FIFO data from accel byte start index to + data_read_length*/ + for (; data_index < data_read_length;) + { + unpack_accel_frame(accel_frame, &data_index, + &accel_index, fifo_data_select, fifo_conf); + } + /* update number of accel data read*/ + *accel_frame_count = accel_index; + /*update the accel byte index*/ + fifo_conf->accel_byte_start_index = data_index; + } + return com_rslt; +} + +/*! + * @brief This API computes the number of bytes of accel FIFO data + * which is to be parsed. + */ +static void get_accel_len_to_parse(u8 *data_index, u8 *data_read_length, + u8 accel_frame_count, u8 fifo_data_select, + struct fifo_configuration *fifo_conf) +{ + /*Current data index is set to accel_byte_start_index*/ + *data_index = fifo_conf->accel_byte_start_index; + /* FIFO bytes corresponding to the requested FIFO frames is obtained*/ + if (fifo_data_select == BMA2x2_FIFO_XYZ_DATA_ENABLED) + { + /*Number of bytes in FIFO when XYZ data are enabled*/ + *data_read_length = accel_frame_count * + BMA2x2_FIFO_XYZ_AXES_FRAME_SIZE; + } + else + { + /*No of bytes in FIFO when single axis data enabled*/ + *data_read_length = accel_frame_count * + BMA2x2_FIFO_SINGLE_AXIS_FRAME_SIZE; + } + if ((*data_read_length) > fifo_conf->fifo_length) + { + /*Handling the case where more FIFO frame is requested + than available*/ + *data_read_length = fifo_conf->fifo_length; + } +} + +/*! + * @brief This API is used to parse the accelerometer frame from the + * user defined FIFO data buffer mapped to the structure fifo_conf and store + * it in the union fifo_frame + * + * @note It update the data_index value which is used to store the index of + * the current data byte which is parsed. + * + * @note The parsed accel frames stored in the union fifo_conf contains data + * in accordance with the enabled data axes to be stored in FIFO + * (XYZ axes or individual axis) + */ +static void unpack_accel_frame(union fifo_frame *accel_frame, u8 *data_index, + u8 *accel_index, u8 fifo_data_select, + struct fifo_configuration *fifo_conf) +{ + u16 data_lsb = 0; + u16 data_msb = 0; + + switch (fifo_data_select) + { + + case BMA2x2_FIFO_XYZ_DATA_ENABLED: + unpack_accel_xyz(&accel_frame[*accel_index], data_index, + fifo_conf); + /* Accel index is updated*/ + (*accel_index)++; + break; + + case BMA2x2_FIFO_X_DATA_ENABLED: + /* Accel raw x data */ + data_lsb = fifo_conf->fifo_data[(*data_index)++]; + data_msb = fifo_conf->fifo_data[(*data_index)++]; + accel_frame[*accel_index].x = (u16)((data_msb << 8) | data_lsb); + + /* Resolution based data from FIFO is updated */ + if (V_BMA2x2RESOLUTION_U8 == BMA2x2_12_RESOLUTION) + { + accel_frame[*accel_index].x = + (accel_frame[*accel_index].x >> 4); + } + else if (V_BMA2x2RESOLUTION_U8 == BMA2x2_14_RESOLUTION) + { + accel_frame[*accel_index].x = + (accel_frame[*accel_index].x >> 2); + } + else if (V_BMA2x2RESOLUTION_U8 == BMA2x2_10_RESOLUTION) + { + accel_frame[*accel_index].x = + (accel_frame[*accel_index].x >> 6); + } + /* Accel index is updated*/ + (*accel_index)++; + break; + + case BMA2x2_FIFO_Y_DATA_ENABLED: + /* Accel raw y data */ + data_lsb = fifo_conf->fifo_data[(*data_index)++]; + data_msb = fifo_conf->fifo_data[(*data_index)++]; + accel_frame[*accel_index].y = (u16)((data_msb << 8) | data_lsb); + + /* Resolution based data from FIFO is updated */ + if (V_BMA2x2RESOLUTION_U8 == BMA2x2_12_RESOLUTION) + { + accel_frame[*accel_index].y = + (accel_frame[*accel_index].y >> 4); + } + else if (V_BMA2x2RESOLUTION_U8 == BMA2x2_14_RESOLUTION) + { + accel_frame[*accel_index].y = + (accel_frame[*accel_index].y >> 2); + } + else if (V_BMA2x2RESOLUTION_U8 == BMA2x2_10_RESOLUTION) + { + accel_frame[*accel_index].y = + (accel_frame[*accel_index].y >> 6); + } + /* Accel index is updated*/ + (*accel_index)++; + break; + + case BMA2x2_FIFO_Z_DATA_ENABLED: + /* Accel raw z data */ + data_lsb = fifo_conf->fifo_data[(*data_index)++]; + data_msb = fifo_conf->fifo_data[(*data_index)++]; + accel_frame[*accel_index].z = (u16)((data_msb << 8) | data_lsb); + + /* Resolution based data from FIFO is updated */ + if (V_BMA2x2RESOLUTION_U8 == BMA2x2_12_RESOLUTION) + { + accel_frame[*accel_index].z = + (accel_frame[*accel_index].z >> 4); + } + else if (V_BMA2x2RESOLUTION_U8 == BMA2x2_14_RESOLUTION) + { + accel_frame[*accel_index].z = + (accel_frame[*accel_index].z >> 2); + } + else if (V_BMA2x2RESOLUTION_U8 == BMA2x2_10_RESOLUTION) + { + accel_frame[*accel_index].z = + (accel_frame[*accel_index].z >> 6); + } + /* Accel index is updated*/ + (*accel_index)++; + break; + + default: + break; + } +} + +/*! + * @brief This API is used to parse the accelerometer data and + * store it in the union fifo_frame + * It also updates the data_index value which stores the index of + * the current data byte which is parsed + * + */ +static void unpack_accel_xyz(union fifo_frame *accel_frame, u8 *data_index, + struct fifo_configuration *fifo_conf) +{ + u16 data_lsb = 0; + u16 data_msb = 0; + + /* Accel raw x data */ + data_lsb = fifo_conf->fifo_data[(*data_index)++]; + data_msb = fifo_conf->fifo_data[(*data_index)++]; + accel_frame->accel_data.x = (u16)((data_msb << 8) | data_lsb); + + /* Accel raw y data */ + data_lsb = fifo_conf->fifo_data[(*data_index)++]; + data_msb = fifo_conf->fifo_data[(*data_index)++]; + accel_frame->accel_data.y = (u16)((data_msb << 8) | data_lsb); + + /* Accel raw z data */ + data_lsb = fifo_conf->fifo_data[(*data_index)++]; + data_msb = fifo_conf->fifo_data[(*data_index)++]; + accel_frame->accel_data.z = (u16)((data_msb << 8) | data_lsb); + + /* Resolution based data from FIFO is updated */ + if (V_BMA2x2RESOLUTION_U8 == BMA2x2_12_RESOLUTION) + { + accel_frame->accel_data.x = (accel_frame->accel_data.x >> 4); + accel_frame->accel_data.y = (accel_frame->accel_data.y >> 4); + accel_frame->accel_data.z = (accel_frame->accel_data.z >> 4); + } + else if (V_BMA2x2RESOLUTION_U8 == BMA2x2_14_RESOLUTION) + { + accel_frame->accel_data.x = (accel_frame->accel_data.x >> 2); + accel_frame->accel_data.y = (accel_frame->accel_data.y >> 2); + accel_frame->accel_data.z = (accel_frame->accel_data.z >> 2); + } + else if (V_BMA2x2RESOLUTION_U8 == BMA2x2_10_RESOLUTION) + { + accel_frame->accel_data.x = (accel_frame->accel_data.x >> 6); + accel_frame->accel_data.y = (accel_frame->accel_data.y >> 6); + accel_frame->accel_data.z = (accel_frame->accel_data.z >> 6); + } +} + +/*! + * @brief This API is used to read the temp + * from register 0x08 + * + * + * + * @param temp_s8: The value of temperature + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_temp(s8 *temp_s8) +{ + u8 data_u8 = BMA2x2_INIT_VALUE; + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC( + p_bma2x2->dev_addr, + BMA2x2_TEMP_ADDR, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *temp_s8 = (s8)data_u8; + } + return com_rslt; +} +/*! + * @brief This API reads accelerometer data X,Y,Z values and + * temperature data from location 02h to 08h + * + * + * + * + * @param accel : The value of accel xyz and temperature data + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_xyzt( + struct bma2x2_accel_data_temp *accel) +{ + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 data_u8[BMA2x2_ACCEL_XYZ_TEMP_DATA_SIZE] = + { + BMA2x2_INIT_VALUE, BMA2x2_INIT_VALUE, + BMA2x2_INIT_VALUE, BMA2x2_INIT_VALUE, + BMA2x2_INIT_VALUE, BMA2x2_INIT_VALUE, + BMA2x2_INIT_VALUE + }; + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + switch (V_BMA2x2RESOLUTION_U8) + { + case BMA2x2_12_RESOLUTION: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, BMA2x2_ACCEL_X12_LSB_REG, + data_u8, BMA2x2_ACCEL_BW_MIN_RANGE); + + /* read x data_u8*/ + accel->x = (s16)((((s32)((s8) + data_u8[BMA2x2_SENSOR_DATA_XYZ_X_MSB])) + << BMA2x2_SHIFT_EIGHT_BITS) | + (data_u8[BMA2x2_SENSOR_DATA_XYZ_X_LSB] + & BMA2x2_12_BIT_SHIFT)); + accel->x = accel->x >> BMA2x2_SHIFT_FOUR_BITS; + + /* read y data_u8*/ + accel->y = (s16)((((s32)((s8) + data_u8[BMA2x2_SENSOR_DATA_XYZ_Y_MSB])) + << BMA2x2_SHIFT_EIGHT_BITS) | + (data_u8[BMA2x2_SENSOR_DATA_XYZ_Y_LSB] + & BMA2x2_12_BIT_SHIFT)); + accel->y = accel->y >> BMA2x2_SHIFT_FOUR_BITS; + + /* read z data_u8*/ + accel->z = (s16)((((s32)((s8) + data_u8[BMA2x2_SENSOR_DATA_XYZ_Z_MSB])) + << BMA2x2_SHIFT_EIGHT_BITS) | + (data_u8[BMA2x2_SENSOR_DATA_XYZ_Z_LSB] + & BMA2x2_12_BIT_SHIFT)); + accel->z = accel->z >> BMA2x2_SHIFT_FOUR_BITS; + /*Accessing the sixth element of array*/ + accel->temp = (s8)data_u8[BMA2x2_SENSOR_DATA_TEMP]; + break; + case BMA2x2_10_RESOLUTION: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, BMA2x2_ACCEL_X10_LSB_REG, + data_u8, BMA2x2_ACCEL_BW_MIN_RANGE); + + /* read x data_u8*/ + accel->x = (s16)((((s32)((s8) + data_u8[BMA2x2_SENSOR_DATA_XYZ_X_MSB])) << + BMA2x2_SHIFT_EIGHT_BITS) | + (data_u8[BMA2x2_SENSOR_DATA_XYZ_X_LSB] + & BMA2x2_10_BIT_SHIFT)); + accel->x = accel->x >> BMA2x2_SHIFT_SIX_BITS; + + /* read y data_u8*/ + accel->y = (s16)((((s32)((s8) + data_u8[BMA2x2_SENSOR_DATA_XYZ_Y_MSB])) << + BMA2x2_SHIFT_EIGHT_BITS) | + (data_u8[BMA2x2_SENSOR_DATA_XYZ_Y_LSB] + & BMA2x2_10_BIT_SHIFT)); + accel->y = accel->y >> BMA2x2_SHIFT_SIX_BITS; + + /* read z data_u8*/ + accel->z = (s16)((((s32)((s8) + data_u8[BMA2x2_SENSOR_DATA_XYZ_Z_MSB])) << + BMA2x2_SHIFT_EIGHT_BITS) | + (data_u8[BMA2x2_SENSOR_DATA_XYZ_Z_LSB] + & BMA2x2_10_BIT_SHIFT)); + accel->z = accel->z >> BMA2x2_SHIFT_SIX_BITS; + + /* read temp_s8 data_u8*/ + /*Accessing the sixth element of array*/ + accel->temp = (s8)data_u8[BMA2x2_SENSOR_DATA_TEMP]; + break; + case BMA2x2_14_RESOLUTION: + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, BMA2x2_ACCEL_X14_LSB_REG, + data_u8, BMA2x2_ACCEL_BW_MIN_RANGE); + + /* read x data_u8*/ + accel->x = (s16)((((s32)((s8) + data_u8[BMA2x2_SENSOR_DATA_XYZ_X_MSB])) << + BMA2x2_SHIFT_EIGHT_BITS) | + (data_u8[BMA2x2_SENSOR_DATA_XYZ_X_LSB] + & BMA2x2_14_BIT_SHIFT)); + accel->x = accel->x >> BMA2x2_SHIFT_TWO_BITS; + + /* read y data_u8*/ + accel->y = (s16)((((s32)((s8) + data_u8[BMA2x2_SENSOR_DATA_XYZ_Y_MSB])) << + BMA2x2_SHIFT_EIGHT_BITS) | + (data_u8[BMA2x2_SENSOR_DATA_XYZ_Y_LSB] + & BMA2x2_14_BIT_SHIFT)); + accel->y = accel->y >> BMA2x2_SHIFT_TWO_BITS; + + /* read z data_u8*/ + accel->z = (s16)((((s32)((s8) + data_u8[BMA2x2_SENSOR_DATA_XYZ_Z_MSB])) << + BMA2x2_SHIFT_EIGHT_BITS) | + (data_u8[BMA2x2_SENSOR_DATA_XYZ_Z_LSB] + & BMA2x2_14_BIT_SHIFT)); + accel->z = accel->z >> BMA2x2_SHIFT_TWO_BITS; + /* read temp data_u8*/ + /*Accessing the sixth element of array*/ + accel->temp = (s8)data_u8[BMA2x2_SENSOR_DATA_TEMP]; + break; + default: + break; + } + } + return com_rslt; +} +/*! + * @brief This API reads accelerometer data X,Y,Z values and + * temperature data from location 0x02 to 0x08 + * + * + * + * + * @param accel : The value of accel xyz and temperature data + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_eight_resolution_xyzt( + struct bma2x2_accel_eight_resolution_temp *accel) +{ + /* Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 data_u8 = BMA2x2_INIT_VALUE; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_X_AXIS_MSB_ADDR, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + accel->x = BMA2x2_GET_BITSLICE(data_u8, + BMA2x2_ACCEL_X_MSB); + + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_Y_AXIS_MSB_ADDR, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + accel->y = BMA2x2_GET_BITSLICE(data_u8, + BMA2x2_ACCEL_Y_MSB); + + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC + (p_bma2x2->dev_addr, + BMA2x2_Z_AXIS_MSB_ADDR, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + accel->z = BMA2x2_GET_BITSLICE(data_u8, + BMA2x2_ACCEL_Z_MSB); + + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC( + p_bma2x2->dev_addr, BMA2x2_TEMP_ADDR, &data_u8, + BMA2x2_GEN_READ_WRITE_LENGTH); + accel->temp = (s8)data_u8; + } + return com_rslt; +} +#if 0 // avoid compile wranning +/*! + * @brief This API is used to get + * the fifo data in the register 0x3F bit 0 to 7 + * + * + * @param output_reg_u8 : The value of fifo data + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_fifo_data_output_reg( + u8 *output_reg_u8) +{ +#warning This API is deprecated ,Instead use the \ +"bma2x2_read_fifo_data" API for reading FIFO data + + u8 data_u8 = BMA2x2_INIT_VALUE; + /*Variable used to return value of + communication routine*/ + BMA2x2_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + if (p_bma2x2 == BMA2x2_NULL) + { + /* Check the struct p_bma2x2 is empty */ + return E_BMA2x2_NULL_PTR; + } + else + { + /*GET FIFO DATA OUTPUT REGISTER*/ + com_rslt = p_bma2x2->BMA2x2_BUS_READ_FUNC( + p_bma2x2->dev_addr, + BMA2x2_FIFO_DATA_OUTPUT_ADDR, + &data_u8, BMA2x2_GEN_READ_WRITE_LENGTH); + *output_reg_u8 = data_u8; + } + return com_rslt; +} +#endif diff --git a/bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMA2x2_driver/bma2x2.h b/bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMA2x2_driver/bma2x2.h new file mode 100644 index 0000000000000000000000000000000000000000..8ea9bc77d4d85ae7aeca700252cb6ca453678d36 --- /dev/null +++ b/bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMA2x2_driver/bma2x2.h @@ -0,0 +1,5855 @@ +/** \mainpage +* +**************************************************************************** +* Copyright (C) 2015 - 2016 Bosch Sensortec GmbH +* +* File : bma2x2.h +* +* Date : 2016/11/14 +* +* Revision : 2.0.7 $ +* +* Usage: Sensor Driver file for BMA2x2 sensor +* +**************************************************************************** +* \section Disclaimer +* +* Common: +* Bosch Sensortec products are developed for the consumer goods industry. +* They may only be used within the parameters of the respective valid +* product data sheet. Bosch Sensortec products are provided with the +* express understanding that there is no warranty of fitness for a +* particular purpose.They are not fit for use in life-sustaining, +* safety or security sensitive systems or any system or device +* that may lead to bodily harm or property damage if the system +* or device malfunctions. In addition,Bosch Sensortec products are +* not fit for use in products which interact with motor vehicle systems. +* The resale and or use of products are at the purchasers own risk and +* his own responsibility. The examination of fitness for the intended use +* is the sole responsibility of the Purchaser. +* +* The purchaser shall indemnify Bosch Sensortec from all third party +* claims, including any claims for incidental, or consequential damages, +* arising from any product use not covered by the parameters of +* the respective valid product data sheet or not approved by +* Bosch Sensortec and reimburse Bosch Sensortec for all costs in +* connection with such claims. +* +* The purchaser must monitor the market for the purchased products, +* particularly with regard to product safety and inform Bosch Sensortec +* without delay of all security relevant incidents. +* +* Engineering Samples are marked with an asterisk (*) or (e). +* Samples may vary from the valid technical specifications of the product +* series. They are therefore not intended or fit for resale to third +* parties or for use in end products. Their sole purpose is internal +* client testing. The testing of an engineering sample may in no way +* replace the testing of a product series. Bosch Sensortec assumes +* no liability for the use of engineering samples. +* By accepting the engineering samples, the Purchaser agrees to indemnify +* Bosch Sensortec from all claims arising from the use of engineering +* samples. +* +* Special: +* This software module (hereinafter called "Software") and any information +* on application-sheets (hereinafter called "Information") is provided +* free of charge for the sole purpose to support your application work. +* The Software and Information is subject to the following +* terms and conditions: +* +* The Software is specifically designed for the exclusive use for +* Bosch Sensortec products by personnel who have special experience +* and training. Do not use this Software if you do not have the +* proper experience or training. +* +* This Software package is provided `` as is `` and without any expressed +* or implied warranties,including without limitation, the implied warranties +* of merchantability and fitness for a particular purpose. +* +* Bosch Sensortec and their representatives and agents deny any liability +* for the functional impairment +* of this Software in terms of fitness, performance and safety. +* Bosch Sensortec and their representatives and agents shall not be liable +* for any direct or indirect damages or injury, except as +* otherwise stipulated in mandatory applicable law. +* +* The Information provided is believed to be accurate and reliable. +* Bosch Sensortec assumes no responsibility for the consequences of use +* of such Information nor for any infringement of patents or +* other rights of third parties which may result from its use. +* No license is granted by implication or otherwise under any patent or +* patent rights of Bosch. Specifications mentioned in the Information are +* subject to change without notice. +**************************************************************************/ +/*! \file bma2x2.h + \brief BMA2x2 Sensor Driver Support Header File */ +#ifndef __BMA2x2_H__ +#define __BMA2x2_H__ +/****************************************************************/ +/**\name DATA TYPES INCLUDES */ +/************************************************************/ +/*! +* @brief The following definition uses for define the data types +* +* @note While porting the API please consider the following +* @note Please check the version of C standard +* @note Are you using Linux platform +*/ + +/*! +* @brief For the Linux platform support +* Please use the types.h for your data types definitions +*/ +#ifdef __KERNEL__ + + #include + /* singed integer type*/ + typedef int8_t s8;/**< used for signed 8bit */ + typedef int16_t s16;/**< used for signed 16bit */ + typedef int32_t s32;/**< used for signed 32bit */ + typedef int64_t s64;/**< used for signed 64bit */ + + typedef u_int8_t u8;/**< used for unsigned 8bit */ + typedef u_int16_t u16;/**< used for unsigned 16bit */ + typedef u_int32_t u32;/**< used for unsigned 32bit */ + typedef u_int64_t u64;/**< used for unsigned 64bit */ + + + +#else /* ! __KERNEL__ */ + /********************************************************** + * These definition uses for define the C + * standard version data types + ***********************************************************/ + #if !defined(__STDC_VERSION__) + + /************************************************ + * compiler is C11 C standard + ************************************************/ + #if (__STDC_VERSION__ == 201112L) + + /************************************************/ + #include + /************************************************/ + + /*unsigned integer types*/ + typedef uint8_t u8;/**< used for unsigned 8bit */ + typedef uint16_t u16;/**< used for unsigned 16bit */ + typedef uint32_t u32;/**< used for unsigned 32bit */ + typedef uint64_t u64;/**< used for unsigned 64bit */ + + /*signed integer types*/ + typedef int8_t s8;/**< used for signed 8bit */ + typedef int16_t s16;/**< used for signed 16bit */ + typedef int32_t s32;/**< used for signed 32bit */ + typedef int64_t s64;/**< used for signed 64bit */ + /************************************************ + * compiler is C99 C standard + ************************************************/ + + #elif (__STDC_VERSION__ == 199901L) + + /* stdint.h is a C99 supported c library. + which is used to fixed the integer size*/ + /************************************************/ + #include + /************************************************/ + + /*unsigned integer types*/ + typedef uint8_t u8;/**< used for unsigned 8bit */ + typedef uint16_t u16;/**< used for unsigned 16bit */ + typedef uint32_t u32;/**< used for unsigned 32bit */ + typedef uint64_t u64;/**< used for unsigned 64bit */ + + /*signed integer types*/ + typedef int8_t s8;/**< used for signed 8bit */ + typedef int16_t s16;/**< used for signed 16bit */ + typedef int32_t s32;/**< used for signed 32bit */ + typedef int64_t s64;/**< used for signed 64bit */ + /************************************************ + * compiler is C89 or other C standard + ************************************************/ + + #else /* !defined(__STDC_VERSION__) */ + /*! + * @brief By default it is defined as 32 bit machine configuration + * define your data types based on your + * machine/compiler/controller configuration + */ + #define MACHINE_32_BIT + + /*! @brief + * If your machine support 16 bit + * define the MACHINE_16_BIT + */ + #ifdef MACHINE_16_BIT + #include + /*signed integer types*/ + typedef signed char s8;/**< used for signed 8bit */ + typedef signed short int s16;/**< used for signed 16bit */ + typedef signed long int s32;/**< used for signed 32bit */ + + #if defined(LONG_MAX) && LONG_MAX == 0x7fffffffffffffffL + typedef long int s64;/**< used for signed 64bit */ + typedef unsigned long int u64;/**< used for unsigned 64bit */ + #elif defined(LLONG_MAX) && (LLONG_MAX == 0x7fffffffffffffffLL) + typedef long long int s64;/**< used for signed 64bit */ + typedef unsigned long long int u64;/**< used for unsigned 64bit */ + #else + #warning Either the correct data type for signed 64 bit integer \ + could not be found, or 64 bit integers are not supported in your environment. + #warning If 64 bit integers are supported on your platform, \ + please set s64 manually. + #endif + + /*unsigned integer types*/ + typedef unsigned char u8;/**< used for unsigned 8bit */ + typedef unsigned short int u16;/**< used for unsigned 16bit */ + typedef unsigned long int u32;/**< used for unsigned 32bit */ + + /* If your machine support 32 bit + define the MACHINE_32_BIT*/ + #elif defined MACHINE_32_BIT + /*signed integer types*/ + typedef signed char s8;/**< used for signed 8bit */ + typedef signed short int s16;/**< used for signed 16bit */ + typedef signed int s32;/**< used for signed 32bit */ + typedef signed long long int s64;/**< used for signed 64bit */ + + /*unsigned integer types*/ + typedef unsigned char u8;/**< used for unsigned 8bit */ + typedef unsigned short int u16;/**< used for unsigned 16bit */ + typedef unsigned int u32;/**< used for unsigned 32bit */ + typedef unsigned long long int u64;/**< used for unsigned 64bit */ + + /* If your machine support 64 bit + define the MACHINE_64_BIT*/ + #elif defined MACHINE_64_BIT + /*signed integer types*/ + typedef signed char s8;/**< used for signed 8bit */ + typedef signed short int s16;/**< used for signed 16bit */ + typedef signed int s32;/**< used for signed 32bit */ + typedef signed long int s64;/**< used for signed 64bit */ + + /*unsigned integer types*/ + typedef unsigned char u8;/**< used for unsigned 8bit */ + typedef unsigned short int u16;/**< used for unsigned 16bit */ + typedef unsigned int u32;/**< used for unsigned 32bit */ + typedef unsigned long int u64;/**< used for unsigned 64bit */ + + #else + #warning The data types defined above which not supported \ + define the data types manually + #endif + #endif + + /*** This else will execute for the compilers + * which are not supported the C standards + * Like C89/C99/C11***/ + #else + /*! + * @brief By default it is defined as 32 bit machine configuration + * define your data types based on your + * machine/compiler/controller configuration + */ + #define MACHINE_32_BIT + + /* If your machine support 16 bit + define the MACHINE_16_BIT*/ + #ifdef MACHINE_16_BIT + #include + /*signed integer types*/ + typedef signed char s8;/**< used for signed 8bit */ + typedef signed short int s16;/**< used for signed 16bit */ + typedef signed long int s32;/**< used for signed 32bit */ + + #if defined(LONG_MAX) && LONG_MAX == 0x7fffffffffffffffL + typedef long int s64;/**< used for signed 64bit */ + typedef unsigned long int u64;/**< used for unsigned 64bit */ + #elif defined(LLONG_MAX) && (LLONG_MAX == 0x7fffffffffffffffLL) + typedef long long int s64;/**< used for signed 64bit */ + typedef unsigned long long int u64;/**< used for unsigned 64bit */ + #else + #warning Either the correct data type for signed 64 bit integer \ + could not be found, or 64 bit integers are not supported in your environment. + #warning If 64 bit integers are supported on your platform, \ + please set s64 manually. + #endif + + /*unsigned integer types*/ + typedef unsigned char u8;/**< used for unsigned 8bit */ + typedef unsigned short int u16;/**< used for unsigned 16bit */ + typedef unsigned long int u32;/**< used for unsigned 32bit */ + + /*! @brief If your machine support 32 bit + define the MACHINE_32_BIT*/ + #elif defined MACHINE_32_BIT + /*signed integer types*/ + typedef signed char s8;/**< used for signed 8bit */ + typedef signed short int s16;/**< used for signed 16bit */ + typedef signed int s32;/**< used for signed 32bit */ + typedef signed long long int s64;/**< used for signed 64bit */ + + /*unsigned integer types*/ + typedef unsigned char u8;/**< used for unsigned 8bit */ + typedef unsigned short int u16;/**< used for unsigned 16bit */ + typedef unsigned int u32;/**< used for unsigned 32bit */ + typedef unsigned long long int u64;/**< used for unsigned 64bit */ + + /* If your machine support 64 bit + define the MACHINE_64_BIT*/ + #elif defined MACHINE_64_BIT + /*signed integer types*/ + typedef signed char s8;/**< used for signed 8bit */ + typedef signed short int s16;/**< used for signed 16bit */ + typedef signed int s32;/**< used for signed 32bit */ + typedef signed long int s64;/**< used for signed 64bit */ + + /*unsigned integer types*/ + typedef unsigned char u8;/**< used for unsigned 8bit */ + typedef unsigned short int u16;/**< used for unsigned 16bit */ + typedef unsigned int u32;/**< used for unsigned 32bit */ + typedef unsigned long int u64;/**< used for unsigned 64bit */ + + #else + #warning The data types defined above which not supported \ + define the data types manually + #endif + #endif +#endif + +/***************************************************************/ +/**\name BUS READ AND WRITE FUNCTION POINTERS */ +/***************************************************************/ +/*! +* @brief Define the calling convention of YOUR bus communication routine. +* @note This includes types of parameters. +* This example shows the configuration for an SPI bus link. + +* If your communication function looks like this: + +* write_my_bus_xy(u8 device_addr, +* u8 register_addr, u8 * data, u8 length); + +* The BMA2x2_WR_FUNC_PTR would equal: + +* BMA2x2_WR_FUNC_PTR char +* (* bus_write)(u8, u8, u8 *, u8) + +* Parameters can be mixed as needed refer to +* the \ref BMA2x2_BUS_WRITE_FUNC macro. +*/ +#define BMA2x2_WR_FUNC_PTR s8(*bus_write)\ +(u8, u8, u8 *, u8) + +/*! +* @brief link macro between API function calls and bus write function +* @note The bus write function can change since +* this is a system dependant issue. + +* If the bus_write parameter calling order is like: +* reg_addr, reg_data, wr_len it would be as it is here. + +* If the parameters are differently ordered or your communication function +* like I2C need to know the device address, +* you can change this macro accordingly. + + +* define BMA2x2_BUS_WRITE_FUNC(dev_addr, reg_addr, reg_data, wr_len)\ +* bus_write(dev_addr, reg_addr, reg_data, wr_len) + +* This macro lets all API functions call YOUR communication routine in +* a way that equals your definition in the +* ref BMA2x2_WR_FUNC_PTR definition. + +*/ +#define BMA2x2_BUS_WRITE_FUNC(dev_addr, reg_addr, reg_data, wr_len)\ +bus_write(dev_addr, reg_addr, reg_data, wr_len) + + +/*! +* @brief Define the calling convention of YOUR bus communication routine. +* @note This includes types of parameters. This example +*shows the configuration for an SPI bus link. + +*If your communication function looks like this: + +*read_my_bus_xy(u8 device_addr, +*u8 register_addr, u8* data, u8 length); + +*The BMA2x2_RD_FUNC_PTR would equal: + +*BMA2x2_RD_FUNC_PTR s8 +*(* bus_read)(u8, u8, u8*, u8) + +*Parameters can be mixed as needed refer to the + ref BMA2x2_BUS_READ_FUNC macro. +*/ + +#define BMA2x2_SPI_RD_MASK 0x80 +/* for spi read transactions on SPI the MSB has to be set */ +#define BMA2x2_RD_FUNC_PTR s8(*bus_read)\ +(u8, u8, u8 *, u8) +#define BMA2x2_BRD_FUNC_PTR s8(*burst_read)\ +(u8, u8, u8 *, u32) + +/*! +* @brief link macro between API function calls and bus read function +* @note The bus write function can change since +* this is a system dependant issue. + +* If the bus_read parameter calling order is like: +* reg_addr, reg_data, wr_len it would be as it is here. + +* If the parameters are differently ordered or your +* communication function like I2C need to know the device address, +* you can change this macro accordingly. + + +* define BMA2x2_BUS_READ_FUNC(dev_addr, reg_addr, reg_data, wr_len)\ +* bus_read(dev_addr, reg_addr, reg_data, wr_len) + +* This macro lets all API functions call YOUR +* communication routine in a way that equals your definition in the +* ref BMA2x2_WR_FUNC_PTR definition. + +* @note: this macro also includes the "MSB='1'" for reading BMA2x2 addresses. +*/ + + + +#define BMA2x2_BUS_READ_FUNC(dev_addr, reg_addr, reg_data, r_len)\ +bus_read(dev_addr, reg_addr, reg_data, r_len) +#define BMA2x2_BURST_READ_FUNC(device_addr,\ +register_addr, register_data, rd_len)\ +burst_read(device_addr, register_addr, register_data, rd_len) +/**************************************************************/ +/**\name I2C ADDRESS DEFINITIONS */ +/**************************************************************/ +/**< The following definition of I2C address is used for the following sensors +* BMA255 +* BMA253 +* BMA355 +* BMA280 +* BMA282 +* BMA223 +* BMA254 +* BMA284 +* BMA250E +* BMA222E +*/ +#define BMA2x2_I2C_ADDR1 (0x18) +#define BMA2x2_I2C_ADDR2 (0x19) + +/**< The following definition of I2C address is used for the following sensors +* BMC150 +* BMC056 +* BMC156 +*/ +#define BMA2x2_I2C_ADDR3 (0x10) +#define BMA2x2_I2C_ADDR4 (0x11) + +/**************************************************************/ +/**\name CONSTANTS DEFINITION */ +/**************************************************************/ +#define BMA2x2_INIT_VALUE ((u8)0) +#define BMA2x2_GEN_READ_WRITE_LENGTH ((u8)1) +#define BMA2x2_INTERFACE_IDLE_TIME_DELAY ((u8)1) +#define BMA2x2_LSB_MSB_READ_LENGTH ((u8)2) +/** BIT SHIFT DEFINITIONS */ +#define BMA2x2_SHIFT_TWO_BITS ((u8)2) +#define BMA2x2_SHIFT_FOUR_BITS ((u8)4) +#define BMA2x2_SHIFT_FIVE_BITS ((u8)5) +#define BMA2x2_SHIFT_SIX_BITS ((u8)6) +#define BMA2x2_SHIFT_EIGHT_BITS ((u8)8) +/** FIFO DEFINITIONS */ +#define BMA2x2_FIFO_MODE_STATUS_RANGE ((u8)2) +#define BMA2x2_FIFO_DATA_SELECT_RANGE ((u8)4) +#define BMA2x2_FIFO_MODE_RANGE ((u8)4) +#define BMA2x2_FIFO_WML_RANGE ((u8)32) + +#define BMA2x2_FIFO_XYZ_DATA_ENABLED (0x00) +#define BMA2x2_FIFO_X_DATA_ENABLED (0x01) +#define BMA2x2_FIFO_Y_DATA_ENABLED (0x02) +#define BMA2x2_FIFO_Z_DATA_ENABLED (0x03) +#define BMA2x2_FIFO_DATA_ENABLED_MASK (0x03) +#define BMA2x2_FIFO_XYZ_AXES_FRAME_SIZE ((u8)6) +#define BMA2x2_FIFO_SINGLE_AXIS_FRAME_SIZE ((u8)2) +/** MODE RANGES */ +#define BMA2x2_ACCEL_BW_MIN_RANGE ((u8)7) +#define BMA2x2_ACCEL_BW_1000HZ_RANGE ((u8)15) +#define BMA2x2_ACCEL_BW_MAX_RANGE ((u8)16) +#define BMA2x2_SLEEP_DURN_MIN_RANGE ((u8)4) +#define BMA2x2_SLEEP_TIMER_MODE_RANGE ((u8)2) +#define BMA2x2_SLEEP_DURN_MAX_RANGE ((u8)16) +#define BMA2x2_POWER_MODE_RANGE ((u8)6) +#define BMA2x2_SELF_TEST_AXIS_RANGE ((u8)4) +#define BMA2x2_SELF_TEST_SIGN_RANGE ((u8)2) + +/**************************************************************/ +/**\name ERROR CODE DEFINITIONS */ +/**************************************************************/ +#define E_OUT_OF_RANGE ((s8)-2) +#define E_BMA2x2_NULL_PTR ((s8)-127) +#define BMA2x2_NULL ((void *)0) +#define ERROR ((s8)-1) +#define SUCCESS ((u8)0) +/**************************************************************/ +/**\name RETURN TYPE DEFINITION */ +/**************************************************************/ +#define BMA2x2_RETURN_FUNCTION_TYPE s8 +/**< This refers BMA2x2 return type as char */ + +/**************************************************************/ +/**\name REGISTER ADDRESS DEFINITIONS */ +/**************************************************************/ +#define BMA2x2_EEP_OFFSET (0x16) +#define BMA2x2_IMAGE_BASE (0x38) +#define BMA2x2_IMAGE_LEN (22) +#define BMA2x2_CHIP_ID_ADDR (0x00) +/** DATA ADDRESS DEFINITIONS */ +#define BMA2x2_X_AXIS_LSB_ADDR (0x02) +#define BMA2x2_X_AXIS_MSB_ADDR (0x03) +#define BMA2x2_Y_AXIS_LSB_ADDR (0x04) +#define BMA2x2_Y_AXIS_MSB_ADDR (0x05) +#define BMA2x2_Z_AXIS_LSB_ADDR (0x06) +#define BMA2x2_Z_AXIS_MSB_ADDR (0x07) +#define BMA2x2_TEMP_ADDR (0x08) +/**STATUS ADDRESS DEFINITIONS */ +#define BMA2x2_STAT1_ADDR (0x09) +#define BMA2x2_STAT2_ADDR (0x0A) +#define BMA2x2_STAT_TAP_SLOPE_ADDR (0x0B) +#define BMA2x2_STAT_ORIENT_HIGH_ADDR (0x0C) +#define BMA2x2_STAT_FIFO_ADDR (0x0E) +/**STATUS ADDRESS DEFINITIONS */ +#define BMA2x2_RANGE_SELECT_ADDR (0x0F) +#define BMA2x2_BW_SELECT_ADDR (0x10) +#define BMA2x2_MODE_CTRL_ADDR (0x11) +#define BMA2x2_LOW_NOISE_CTRL_ADDR (0x12) +#define BMA2x2_DATA_CTRL_ADDR (0x13) +#define BMA2x2_RST_ADDR (0x14) +/**INTERUPT ADDRESS DEFINITIONS */ +#define BMA2x2_INTR_ENABLE1_ADDR (0x16) +#define BMA2x2_INTR_ENABLE2_ADDR (0x17) +#define BMA2x2_INTR_SLOW_NO_MOTION_ADDR (0x18) +#define BMA2x2_INTR1_PAD_SELECT_ADDR (0x19) +#define BMA2x2_INTR_DATA_SELECT_ADDR (0x1A) +#define BMA2x2_INTR2_PAD_SELECT_ADDR (0x1B) +#define BMA2x2_INTR_SOURCE_ADDR (0x1E) +#define BMA2x2_INTR_SET_ADDR (0x20) +#define BMA2x2_INTR_CTRL_ADDR (0x21) +/** FEATURE ADDRESS DEFINITIONS */ +#define BMA2x2_LOW_DURN_ADDR (0x22) +#define BMA2x2_LOW_THRES_ADDR (0x23) +#define BMA2x2_LOW_HIGH_HYST_ADDR (0x24) +#define BMA2x2_HIGH_DURN_ADDR (0x25) +#define BMA2x2_HIGH_THRES_ADDR (0x26) +#define BMA2x2_SLOPE_DURN_ADDR (0x27) +#define BMA2x2_SLOPE_THRES_ADDR (0x28) +#define BMA2x2_SLOW_NO_MOTION_THRES_ADDR (0x29) +#define BMA2x2_TAP_PARAM_ADDR (0x2A) +#define BMA2x2_TAP_THRES_ADDR (0x2B) +#define BMA2x2_ORIENT_PARAM_ADDR (0x2C) +#define BMA2x2_THETA_BLOCK_ADDR (0x2D) +#define BMA2x2_THETA_FLAT_ADDR (0x2E) +#define BMA2x2_FLAT_HOLD_TIME_ADDR (0x2F) +#define BMA2x2_SELFTEST_ADDR (0x32) +#define BMA2x2_EEPROM_CTRL_ADDR (0x33) +#define BMA2x2_SERIAL_CTRL_ADDR (0x34) +/**OFFSET ADDRESS DEFINITIONS */ +#define BMA2x2_OFFSET_CTRL_ADDR (0x36) +#define BMA2x2_OFFSET_PARAMS_ADDR (0x37) +#define BMA2x2_OFFSET_X_AXIS_ADDR (0x38) +#define BMA2x2_OFFSET_Y_AXIS_ADDR (0x39) +#define BMA2x2_OFFSET_Z_AXIS_ADDR (0x3A) +/**GP ADDRESS DEFINITIONS */ +#define BMA2x2_GP0_ADDR (0x3B) +#define BMA2x2_GP1_ADDR (0x3C) +/**FIFO ADDRESS DEFINITIONS */ +#define BMA2x2_FIFO_MODE_ADDR (0x3E) +#define BMA2x2_FIFO_DATA_OUTPUT_ADDR (0x3F) +#define BMA2x2_FIFO_WML_TRIG (0x30) + +/**************************************************************/ +/**\name ACCEL RESOLUTION DEFINITION */ +/**************************************************************/ +#define BMA2x2_12_RESOLUTION (0) +#define BMA2x2_10_RESOLUTION (1) +#define BMA2x2_14_RESOLUTION (2) + +/**************************************************************/ +/**\name ACCEL DELAY DEFINITION */ +/**************************************************************/ +/* register write and read delays */ +#define BMA2x2_MDELAY_DATA_TYPE u32 +#define BMA2x2_EE_W_DELAY (28) + +/**************************************************************/ +/**\name STRUCTURE DEFINITIONS */ +/**************************************************************/ +/*! +* @brief read accel xyz data for 10,14 and 12 bit resolution +*/ +struct bma2x2_accel_data +{ + s16 x,/**< accel x data 10,14 and 12 resolution*/ + y,/**< accel y data 10,14 and 12 resolution*/ + z;/**< accel z data 10,14 and 12 resolution*/ +}; +/*! +* @brief read accel xyz data for 10,14 and 12 bit resolution +* and temperature output +*/ +struct bma2x2_accel_data_temp +{ + s16 x,/**< accel x data 10,14 and 12 resolution*/ + y,/**< accel y data 10,14 and 12 resolution*/ + z;/**< accel z data 10,14 and 12 resolution*/ + s8 temp;/**< accel temperature data*/ +}; + +/*! +* @brief read accel xyz data for 8 bit resolution +*/ +struct bma2x2_accel_eight_resolution +{ + s8 x,/**< accel x data with eight bit resolution*/ + y,/**< accel y data with eight bit resolution*/ + z;/**< accel z data with eight bit resolution*/ +}; +/*! +* @brief read accel xyz data for 8 bit resolution and temperature +*/ +struct bma2x2_accel_eight_resolution_temp +{ + s8 x,/**< accel x data with eight bit resolution*/ + y,/**< accel y data with eight bit resolution*/ + z;/**< accel z data with eight bit resolution*/ + s8 temp;/**< accel temperature data*/ +}; + +/*! + * @brief FIFO data read is parsed and returned to user using this union. + * + * @note Read the respective data fields in the union for corresponding + * accel data axes enabled in FIFO storage( Axes stored in FIFO can be set + * by the data_select_bits in the register FIFO_CONFIG_1 ) + * + * data enabled for FIFO storage | Data field to be read from the below union + * ------------------------------|------------------------------------------- + * XYZ axes enabled | struct bma2x2_accel_data + * X axis data enabled | x data + * Y axis data enabled | y data + * Z axis data enabled | z data + */ +union fifo_frame +{ + /*! FIFO data stored here when XYZ data enabled in + fifo_data_select bits of register 0x3E*/ + struct bma2x2_accel_data accel_data; + /*! FIFO data stored here when accel X data enabled in + fifo_data_select bits of register 0x3E*/ + s16 x; + /*! FIFO data stored here when accel Y data enabled in + fifo_data_select bits of register 0x3E*/ + s16 y; + /*! FIFO data stored here when accel Z data enabled in + fifo_data_select bits of register 0x3E*/ + s16 z; +}; + +/*! + * @brief bma2x2 initialization struct + * struct bma2x2_t is used for assigning the following parameters. + * + * Bus write function pointer: BMA2x2_WR_FUNC_PTR + * Bus read function pointer: BMA2x2_RD_FUNC_PTR + * Burst read function pointer: BMA2x2_BRD_FUNC_PTR + * Delay function pointer: delay_msec + * I2C address: dev_addr + * Chip id of the sensor: chip_id + */ +struct bma2x2_t +{ + /*! save current bma2x2 operation mode */ + u8 power_mode_u8; + /*! chip_id of bma2x2 */ + u8 chip_id; + /*! the value of power mode register 0x11*/ + u8 ctrl_mode_reg; + /*! the value of power mode register 0x12*/ + u8 low_mode_reg; + /*! initializes bma2x2's I2C device address*/ + u8 dev_addr; + /*! store the fifo configuration register*/ + u8 fifo_config; + /*! function pointer to the SPI/I2C write function */ + BMA2x2_WR_FUNC_PTR; + /*! function pointer to the SPI/I2C read function */ + BMA2x2_RD_FUNC_PTR; + /*! function pointer to the SPI/I2C burst read function */ + BMA2x2_BRD_FUNC_PTR; + /*! delay(in ms) function pointer */ + void (*delay_msec)(BMA2x2_MDELAY_DATA_TYPE); +}; + +/*! + * @brief FIFO configurations are stored in this structure + * + * @note User should map the following before reading the FIFO data + * - buffer for storing the FIFO data should be mapped to the member + * "fifo_data" of this structure + * - Number of bytes to be read from the FIFO should be mapped to the member + * "fifo_length" of this structure + */ +struct fifo_configuration +{ + /*! Data buffer of user defined length is to be mapped here */ + u8 *fifo_data; + /*! Index of accel data stored in FIFO buffer */ + u8 accel_byte_start_index; + /*! No of bytes to be read in FIFO as specified by the user */ + u8 fifo_length; +}; + +/*********************************************************************/ +/**\name REGISTER BIT MASK, BIT LENGTH, BIT POSITION DEFINITIONS */ +/********************************************************************/ +/******************************/ +/**\name CHIP ID */ +/******************************/ +#define BMA2x2_CHIP_ID_POS (0) +#define BMA2x2_CHIP_ID_MSK (0xFF) +#define BMA2x2_CHIP_ID_LEN (8) +#define BMA2x2_CHIP_ID_REG BMA2x2_CHIP_ID_ADDR + +/******************************/ +/**\name DATA REGISTER-X */ +/******************************/ +#define BMA2x2_NEW_DATA_X_POS (0) +#define BMA2x2_NEW_DATA_X_LEN (1) +#define BMA2x2_NEW_DATA_X_MSK (0x01) +#define BMA2x2_NEW_DATA_X_REG BMA2x2_X_AXIS_LSB_ADDR + +#define BMA2x2_ACCEL_X14_LSB_POS (2) +#define BMA2x2_ACCEL_X14_LSB_LEN (6) +#define BMA2x2_ACCEL_X14_LSB_MSK (0xFC) +#define BMA2x2_ACCEL_X14_LSB_REG BMA2x2_X_AXIS_LSB_ADDR + +#define BMA2x2_ACCEL_X12_LSB_POS (4) +#define BMA2x2_ACCEL_X12_LSB_LEN (4) +#define BMA2x2_ACCEL_X12_LSB_MSK (0xF0) +#define BMA2x2_ACCEL_X12_LSB_REG BMA2x2_X_AXIS_LSB_ADDR + +#define BMA2x2_ACCEL_X10_LSB_POS (6) +#define BMA2x2_ACCEL_X10_LSB_LEN (2) +#define BMA2x2_ACCEL_X10_LSB_MSK (0xC0) +#define BMA2x2_ACCEL_X10_LSB_REG BMA2x2_X_AXIS_LSB_ADDR + +#define BMA2x2_ACCEL_X8_LSB_POS (0) +#define BMA2x2_ACCEL_X8_LSB_LEN (0) +#define BMA2x2_ACCEL_X8_LSB_MSK (0x00) +#define BMA2x2_ACCEL_X8_LSB_REG BMA2x2_X_AXIS_LSB_ADDR + +#define BMA2x2_ACCEL_X_MSB_POS (0) +#define BMA2x2_ACCEL_X_MSB_LEN (8) +#define BMA2x2_ACCEL_X_MSB_MSK (0xFF) +#define BMA2x2_ACCEL_X_MSB_REG BMA2x2_X_AXIS_MSB_ADDR +/******************************/ +/**\name DATA REGISTER-Y */ +/******************************/ +#define BMA2x2_NEW_DATA_Y_POS (0) +#define BMA2x2_NEW_DATA_Y_LEN (1) +#define BMA2x2_NEW_DATA_Y_MSK (0x01) +#define BMA2x2_NEW_DATA_Y_REG BMA2x2_Y_AXIS_LSB_ADDR + +#define BMA2x2_ACCEL_Y14_LSB_POS (2) +#define BMA2x2_ACCEL_Y14_LSB_LEN (6) +#define BMA2x2_ACCEL_Y14_LSB_MSK (0xFC) +#define BMA2x2_ACCEL_Y14_LSB_REG BMA2x2_Y_AXIS_LSB_ADDR + +#define BMA2x2_ACCEL_Y12_LSB_POS (4) +#define BMA2x2_ACCEL_Y12_LSB_LEN (4) +#define BMA2x2_ACCEL_Y12_LSB_MSK (0xF0) +#define BMA2x2_ACCEL_Y12_LSB_REG BMA2x2_Y_AXIS_LSB_ADDR + +#define BMA2x2_ACCEL_Y10_LSB_POS (6) +#define BMA2x2_ACCEL_Y10_LSB_LEN (2) +#define BMA2x2_ACCEL_Y10_LSB_MSK (0xC0) +#define BMA2x2_ACCEL_Y10_LSB_REG BMA2x2_Y_AXIS_LSB_ADDR + +#define BMA2x2_ACCEL_Y8_LSB_POS (0) +#define BMA2x2_ACCEL_Y8_LSB_LEN (0) +#define BMA2x2_ACCEL_Y8_LSB_MSK (0x00) +#define BMA2x2_ACCEL_Y8_LSB_REG BMA2x2_Y_AXIS_LSB_ADDR + +#define BMA2x2_ACCEL_Y_MSB_POS (0) +#define BMA2x2_ACCEL_Y_MSB_LEN (8) +#define BMA2x2_ACCEL_Y_MSB_MSK (0xFF) +#define BMA2x2_ACCEL_Y_MSB_REG BMA2x2_Y_AXIS_MSB_ADDR +/******************************/ +/**\name DATA REGISTER-Z */ +/******************************/ +#define BMA2x2_NEW_DATA_Z_POS (0) +#define BMA2x2_NEW_DATA_Z_LEN (1) +#define BMA2x2_NEW_DATA_Z_MSK (0x01) +#define BMA2x2_NEW_DATA_Z_REG BMA2x2_Z_AXIS_LSB_ADDR + +#define BMA2x2_ACCEL_Z14_LSB_POS (2) +#define BMA2x2_ACCEL_Z14_LSB_LEN (6) +#define BMA2x2_ACCEL_Z14_LSB_MSK (0xFC) +#define BMA2x2_ACCEL_Z14_LSB_REG BMA2x2_Z_AXIS_LSB_ADDR + +#define BMA2x2_ACCEL_Z12_LSB_POS (4) +#define BMA2x2_ACCEL_Z12_LSB_LEN (4) +#define BMA2x2_ACCEL_Z12_LSB_MSK (0xF0) +#define BMA2x2_ACCEL_Z12_LSB_REG BMA2x2_Z_AXIS_LSB_ADDR + +#define BMA2x2_ACCEL_Z10_LSB_POS (6) +#define BMA2x2_ACCEL_Z10_LSB_LEN (2) +#define BMA2x2_ACCEL_Z10_LSB_MSK (0xC0) +#define BMA2x2_ACCEL_Z10_LSB_REG BMA2x2_Z_AXIS_LSB_ADDR + +#define BMA2x2_ACCEL_Z8_LSB_POS (0) +#define BMA2x2_ACCEL_Z8_LSB_LEN (0) +#define BMA2x2_ACCEL_Z8_LSB_MSK (0x00) +#define BMA2x2_ACCEL_Z8_LSB_REG BMA2x2_Z_AXIS_LSB_ADDR + +#define BMA2x2_ACCEL_Z_MSB_POS (0) +#define BMA2x2_ACCEL_Z_MSB_LEN (8) +#define BMA2x2_ACCEL_Z_MSB_MSK (0xFF) +#define BMA2x2_ACCEL_Z_MSB_REG BMA2x2_Z_AXIS_MSB_ADDR + +/******************************/ +/**\name TEMPERATURE */ +/******************************/ +#define BMA2x2_ACCEL_TEMP_MSB_POS (0) +#define BMA2x2_ACCEL_TEMP_MSB_LEN (8) +#define BMA2x2_ACCEL_TEMP_MSB_MSK (0xFF) +#define BMA2x2_ACCEL_TEMP_MSB_REG BMA2x2_TEMPERATURE_REG + +/***************************************/ +/**\name INTERRUPT STATUS OF LOW-G */ +/**************************************/ +#define BMA2x2_LOW_G_INTR_STAT_POS (0) +#define BMA2x2_LOW_G_INTR_STAT_LEN (1) +#define BMA2x2_LOW_G_INTR_STAT_MSK (0x01) +#define BMA2x2_LOW_G_INTR_STAT_REG BMA2x2_STAT1_ADDR +/***************************************/ +/**\name INTERRUPT STATUS OF HIGH-G */ +/**************************************/ +#define BMA2x2_HIGH_G_INTR_STAT_POS (1) +#define BMA2x2_HIGH_G_INTR_STAT_LEN (1) +#define BMA2x2_HIGH_G_INTR_STAT_MSK (0x02) +#define BMA2x2_HIGH_G_INTR_STAT_REG BMA2x2_STAT1_ADDR +/***************************************/ +/**\name INTERRUPT STATUS OF SLOPE */ +/**************************************/ +#define BMA2x2_SLOPE_INTR_STAT_POS (2) +#define BMA2x2_SLOPE_INTR_STAT_LEN (1) +#define BMA2x2_SLOPE_INTR_STAT_MSK (0x04) +#define BMA2x2_SLOPE_INTR_STAT_REG BMA2x2_STAT1_ADDR +/*******************************************/ +/**\name INTERRUPT STATUS OF SLOW NO MOTION*/ +/*******************************************/ +#define BMA2x2_SLOW_NO_MOTION_INTR_STAT_POS (3) +#define BMA2x2_SLOW_NO_MOTION_INTR_STAT_LEN (1) +#define BMA2x2_SLOW_NO_MOTION_INTR_STAT_MSK (0x08) +#define BMA2x2_SLOW_NO_MOTION_INTR_STAT_REG BMA2x2_STAT1_ADDR +/***************************************/ +/**\name INTERRUPT STATUS OF DOUBLE TAP */ +/**************************************/ +#define BMA2x2_DOUBLE_TAP_INTR_STAT_POS (4) +#define BMA2x2_DOUBLE_TAP_INTR_STAT_LEN (1) +#define BMA2x2_DOUBLE_TAP_INTR_STAT_MSK (0x10) +#define BMA2x2_DOUBLE_TAP_INTR_STAT_REG BMA2x2_STAT1_ADDR +/***************************************/ +/**\name INTERRUPT STATUS OF SINGLE TAP */ +/**************************************/ +#define BMA2x2_SINGLE_TAP_INTR_STAT_POS (5) +#define BMA2x2_SINGLE_TAP_INTR_STAT_LEN (1) +#define BMA2x2_SINGLE_TAP_INTR_STAT_MSK (0x20) +#define BMA2x2_SINGLE_TAP_INTR_STAT_REG BMA2x2_STAT1_ADDR +/***************************************/ +/**\name INTERRUPT STATUS OF ORIENT*/ +/**************************************/ +#define BMA2x2_ORIENT_INTR_STAT_POS (6) +#define BMA2x2_ORIENT_INTR_STAT_LEN (1) +#define BMA2x2_ORIENT_INTR_STAT_MSK (0x40) +#define BMA2x2_ORIENT_INTR_STAT_REG BMA2x2_STAT1_ADDR +/***************************************/ +/**\name INTERRUPT STATUS OF FLAT */ +/**************************************/ +#define BMA2x2_FLAT_INTR_STAT_POS (7) +#define BMA2x2_FLAT_INTR_STAT_LEN (1) +#define BMA2x2_FLAT_INTR_STAT_MSK (0x80) +#define BMA2x2_FLAT_INTR_STAT_REG BMA2x2_STAT1_ADDR +/***************************************/ +/**\name INTERRUPT STATUS OF FIFO FULL */ +/**************************************/ +#define BMA2x2_FIFO_FULL_INTR_STAT_POS (5) +#define BMA2x2_FIFO_FULL_INTR_STAT_LEN (1) +#define BMA2x2_FIFO_FULL_INTR_STAT_MSK (0x20) +#define BMA2x2_FIFO_FULL_INTR_STAT_REG BMA2x2_STAT2_ADDR +/*******************************************/ +/**\name INTERRUPT STATUS OF FIFO WATERMARK*/ +/******************************************/ +#define BMA2x2_FIFO_WM_INTR_STAT_POS (6) +#define BMA2x2_FIFO_WM_INTR_STAT_LEN (1) +#define BMA2x2_FIFO_WM_INTR_STAT_MSK (0x40) +#define BMA2x2_FIFO_WM_INTR_STAT_REG BMA2x2_STAT2_ADDR +/***************************************/ +/**\name INTERRUPT STATUS OF DATA */ +/**************************************/ +#define BMA2x2_DATA_INTR_STAT_POS (7) +#define BMA2x2_DATA_INTR_STAT_LEN (1) +#define BMA2x2_DATA_INTR_STAT_MSK (0x80) +#define BMA2x2_DATA_INTR_STAT_REG BMA2x2_STAT2_ADDR +/*********************************************/ +/**\name INTERRUPT STATUS SLOPE XYZ AND SIGN */ +/*********************************************/ +#define BMA2x2_SLOPE_FIRST_X_POS (0) +#define BMA2x2_SLOPE_FIRST_X_LEN (1) +#define BMA2x2_SLOPE_FIRST_X_MSK (0x01) +#define BMA2x2_SLOPE_FIRST_X_REG BMA2x2_STAT_TAP_SLOPE_ADDR + +#define BMA2x2_SLOPE_FIRST_Y_POS (1) +#define BMA2x2_SLOPE_FIRST_Y_LEN (1) +#define BMA2x2_SLOPE_FIRST_Y_MSK (0x02) +#define BMA2x2_SLOPE_FIRST_Y_REG BMA2x2_STAT_TAP_SLOPE_ADDR + +#define BMA2x2_SLOPE_FIRST_Z_POS (2) +#define BMA2x2_SLOPE_FIRST_Z_LEN (1) +#define BMA2x2_SLOPE_FIRST_Z_MSK (0x04) +#define BMA2x2_SLOPE_FIRST_Z_REG BMA2x2_STAT_TAP_SLOPE_ADDR + +#define BMA2x2_SLOPE_SIGN_STAT_POS (3) +#define BMA2x2_SLOPE_SIGN_STAT_LEN (1) +#define BMA2x2_SLOPE_SIGN_STAT_MSK (0x08) +#define BMA2x2_SLOPE_SIGN_STAT_REG BMA2x2_STAT_TAP_SLOPE_ADDR +/*********************************************/ +/**\name INTERRUPT STATUS TAP XYZ AND SIGN */ +/*********************************************/ +#define BMA2x2_TAP_FIRST_X_POS (4) +#define BMA2x2_TAP_FIRST_X_LEN (1) +#define BMA2x2_TAP_FIRST_X_MSK (0x10) +#define BMA2x2_TAP_FIRST_X_REG BMA2x2_STAT_TAP_SLOPE_ADDR + +#define BMA2x2_TAP_FIRST_Y_POS (5) +#define BMA2x2_TAP_FIRST_Y_LEN (1) +#define BMA2x2_TAP_FIRST_Y_MSK (0x20) +#define BMA2x2_TAP_FIRST_Y_REG BMA2x2_STAT_TAP_SLOPE_ADDR + +#define BMA2x2_TAP_FIRST_Z_POS (6) +#define BMA2x2_TAP_FIRST_Z_LEN (1) +#define BMA2x2_TAP_FIRST_Z_MSK (0x40) +#define BMA2x2_TAP_FIRST_Z_REG BMA2x2_STAT_TAP_SLOPE_ADDR + +#define BMA2x2_TAP_SIGN_STAT_POS (7) +#define BMA2x2_TAP_SIGN_STAT_LEN (1) +#define BMA2x2_TAP_SIGN_STAT_MSK (0x80) +#define BMA2x2_TAP_SIGN_STAT_REG BMA2x2_STAT_TAP_SLOPE_ADDR +/*********************************************/ +/**\name INTERRUPT STATUS HIGH_G XYZ AND SIGN */ +/*********************************************/ +#define BMA2x2_HIGH_G_FIRST_X_POS (0) +#define BMA2x2_HIGH_G_FIRST_X_LEN (1) +#define BMA2x2_HIGH_G_FIRST_X_MSK (0x01) +#define BMA2x2_HIGH_G_FIRST_X_REG BMA2x2_STAT_ORIENT_HIGH_ADDR + +#define BMA2x2_HIGH_G_FIRST_Y_POS (1) +#define BMA2x2_HIGH_G_FIRST_Y_LEN (1) +#define BMA2x2_HIGH_G_FIRST_Y_MSK (0x02) +#define BMA2x2_HIGH_G_FIRST_Y_REG BMA2x2_STAT_ORIENT_HIGH_ADDR + +#define BMA2x2_HIGH_G_FIRST_Z_POS (2) +#define BMA2x2_HIGH_G_FIRST_Z_LEN (1) +#define BMA2x2_HIGH_G_FIRST_Z_MSK (0x04) +#define BMA2x2_HIGH_G_FIRST_Z_REG BMA2x2_STAT_ORIENT_HIGH_ADDR + +#define BMA2x2_HIGH_G_SIGN_STAT_POS (3) +#define BMA2x2_HIGH_G_SIGN_STAT_LEN (1) +#define BMA2x2_HIGH_G_SIGN_STAT_MSK (0x08) +#define BMA2x2_HIGH_G_SIGN_STAT_REG BMA2x2_STAT_ORIENT_HIGH_ADDR +/*********************************************/ +/**\name INTERRUPT STATUS ORIENT */ +/*********************************************/ +#define BMA2x2_ORIENT_STAT_POS (4) +#define BMA2x2_ORIENT_STAT_LEN (3) +#define BMA2x2_ORIENT_STAT_MSK (0x70) +#define BMA2x2_ORIENT_STAT_REG BMA2x2_STAT_ORIENT_HIGH_ADDR +/*********************************************/ +/**\name INTERRUPT STATUS FLAT */ +/*********************************************/ +#define BMA2x2_FLAT_STAT_POS (7) +#define BMA2x2_FLAT_STAT_LEN (1) +#define BMA2x2_FLAT_STAT_MSK (0x80) +#define BMA2x2_FLAT_STAT_REG BMA2x2_STAT_ORIENT_HIGH_ADDR + +/*********************************************/ +/**\name INTERRUPT STATUS OF FIFO FRAME COUNT */ +/*********************************************/ +#define BMA2x2_FIFO_FRAME_COUNT_STAT_POS (0) +#define BMA2x2_FIFO_FRAME_COUNT_STAT_LEN (7) +#define BMA2x2_FIFO_FRAME_COUNT_STAT_MSK (0x7F) +#define BMA2x2_FIFO_FRAME_COUNT_STAT_REG BMA2x2_STAT_FIFO_ADDR +/*********************************************/ +/**\name INTERRUPT STATUS OF FIFO OVERRUN */ +/*********************************************/ +#define BMA2x2_FIFO_OVERRUN_STAT_POS (7) +#define BMA2x2_FIFO_OVERRUN_STAT_LEN (1) +#define BMA2x2_FIFO_OVERRUN_STAT_MSK (0x80) +#define BMA2x2_FIFO_OVERRUN_STAT_REG BMA2x2_STAT_FIFO_ADDR +/****************************/ +/**\name RANGE */ +/****************************/ +#define BMA2x2_RANGE_SELECT_POS (0) +#define BMA2x2_RANGE_SELECT_LEN (4) +#define BMA2x2_RANGE_SELECT_MSK (0x0F) +#define BMA2x2_RANGE_SELECT_REG BMA2x2_RANGE_SELECT_ADDR +/****************************/ +/**\name BANDWIDTH */ +/****************************/ +#define BMA2x2_BW_POS (0) +#define BMA2x2_BW_LEN (5) +#define BMA2x2_BW_MSK (0x1F) +#define BMA2x2_BW_REG BMA2x2_BW_SELECT_ADDR +/****************************/ +/**\name SLEEP DURATION */ +/****************************/ +#define BMA2x2_SLEEP_DURN_POS (1) +#define BMA2x2_SLEEP_DURN_LEN (4) +#define BMA2x2_SLEEP_DURN_MSK (0x1E) +#define BMA2x2_SLEEP_DURN_REG BMA2x2_MODE_CTRL_ADDR +/****************************/ +/**\name POWER MODEPOWER MODE */ +/****************************/ +#define BMA2x2_MODE_CTRL_POS (5) +#define BMA2x2_MODE_CTRL_LEN (3) +#define BMA2x2_MODE_CTRL_MSK (0xE0) +#define BMA2x2_MODE_CTRL_REG BMA2x2_MODE_CTRL_ADDR +/****************************/ +/**\name SLEEP TIMER */ +/****************************/ +#define BMA2x2_SLEEP_TIMER_POS (5) +#define BMA2x2_SLEEP_TIMER_LEN (1) +#define BMA2x2_SLEEP_TIMER_MSK (0x20) +#define BMA2x2_SLEEP_TIMER_REG BMA2x2_LOW_NOISE_CTRL_ADDR +/****************************/ +/**\name LOWPOWER MODE */ +/****************************/ +#define BMA2x2_LOW_POWER_MODE_POS (6) +#define BMA2x2_LOW_POWER_MODE_LEN (1) +#define BMA2x2_LOW_POWER_MODE_MSK (0x40) +#define BMA2x2_LOW_POWER_MODE_REG BMA2x2_LOW_NOISE_CTRL_ADDR +/*******************************************/ +/**\name DISABLE MSB SHADOWING PROCEDURE */ +/*******************************************/ +#define BMA2x2_DIS_SHADOW_PROC_POS (6) +#define BMA2x2_DIS_SHADOW_PROC_LEN (1) +#define BMA2x2_DIS_SHADOW_PROC_MSK (0x40) +#define BMA2x2_DIS_SHADOW_PROC_REG BMA2x2_DATA_CTRL_ADDR +/***************************************************/ +/**\name FILTERED OR UNFILTERED ACCELERATION DATA */ +/***************************************************/ +#define BMA2x2_ENABLE_DATA_HIGH_BW_POS (7) +#define BMA2x2_ENABLE_DATA_HIGH_BW_LEN (1) +#define BMA2x2_ENABLE_DATA_HIGH_BW_MSK (0x80) +#define BMA2x2_ENABLE_DATA_HIGH_BW_REG BMA2x2_DATA_CTRL_ADDR +/***************************************************/ +/**\name SOFT RESET VALUE */ +/***************************************************/ +#define BMA2x2_ENABLE_SOFT_RESET_VALUE (0xB6) +/**********************************************/ +/**\name INTERRUPT ENABLE OF SLOPE-XYZ */ +/**********************************************/ +#define BMA2x2_ENABLE_SLOPE_X_INTR_POS (0) +#define BMA2x2_ENABLE_SLOPE_X_INTR_LEN (1) +#define BMA2x2_ENABLE_SLOPE_X_INTR_MSK (0x01) +#define BMA2x2_ENABLE_SLOPE_X_INTR_REG BMA2x2_INTR_ENABLE1_ADDR + +#define BMA2x2_ENABLE_SLOPE_Y_INTR_POS (1) +#define BMA2x2_ENABLE_SLOPE_Y_INTR_LEN (1) +#define BMA2x2_ENABLE_SLOPE_Y_INTR_MSK (0x02) +#define BMA2x2_ENABLE_SLOPE_Y_INTR_REG BMA2x2_INTR_ENABLE1_ADDR + +#define BMA2x2_ENABLE_SLOPE_Z_INTR_POS (2) +#define BMA2x2_ENABLE_SLOPE_Z_INTR_LEN (1) +#define BMA2x2_ENABLE_SLOPE_Z_INTR_MSK (0x04) +#define BMA2x2_ENABLE_SLOPE_Z_INTR_REG BMA2x2_INTR_ENABLE1_ADDR +/**********************************************/ +/**\name INTERRUPT ENABLE OF DOUBLE TAP */ +/**********************************************/ +#define BMA2x2_ENABLE_DOUBLE_TAP_INTR_POS (4) +#define BMA2x2_ENABLE_DOUBLE_TAP_INTR_LEN (1) +#define BMA2x2_ENABLE_DOUBLE_TAP_INTR_MSK (0x10) +#define BMA2x2_ENABLE_DOUBLE_TAP_INTR_REG BMA2x2_INTR_ENABLE1_ADDR +/**********************************************/ +/**\name INTERRUPT ENABLE OF SINGLE TAP */ +/**********************************************/ +#define BMA2x2_ENABLE_SINGLE_TAP_INTR_POS (5) +#define BMA2x2_ENABLE_SINGLE_TAP_INTR_LEN (1) +#define BMA2x2_ENABLE_SINGLE_TAP_INTR_MSK (0x20) +#define BMA2x2_ENABLE_SINGLE_TAP_INTR_REG BMA2x2_INTR_ENABLE1_ADDR +/**********************************************/ +/**\name INTERRUPT ENABLE OF ORIENT */ +/**********************************************/ +#define BMA2x2_ENABLE_ORIENT_INTR_POS (6) +#define BMA2x2_ENABLE_ORIENT_INTR_LEN (1) +#define BMA2x2_ENABLE_ORIENT_INTR_MSK (0x40) +#define BMA2x2_ENABLE_ORIENT_INTR_REG BMA2x2_INTR_ENABLE1_ADDR +/**********************************************/ +/**\name INTERRUPT ENABLE OF FLAT */ +/**********************************************/ +#define BMA2x2_ENABLE_FLAT_INTR_POS (7) +#define BMA2x2_ENABLE_FLAT_INTR_LEN (1) +#define BMA2x2_ENABLE_FLAT_INTR_MSK (0x80) +#define BMA2x2_ENABLE_FLAT_INTR_REG BMA2x2_INTR_ENABLE1_ADDR +/**********************************************/ +/**\name INTERRUPT ENABLE OF HIGH_G-XYZ */ +/**********************************************/ +#define BMA2x2_ENABLE_HIGH_G_X_INTR_POS (0) +#define BMA2x2_ENABLE_HIGH_G_X_INTR_LEN (1) +#define BMA2x2_ENABLE_HIGH_G_X_INTR_MSK (0x01) +#define BMA2x2_ENABLE_HIGH_G_X_INTR_REG BMA2x2_INTR_ENABLE2_ADDR + +#define BMA2x2_ENABLE_HIGH_G_Y_INTR_POS (1) +#define BMA2x2_ENABLE_HIGH_G_Y_INTR_LEN (1) +#define BMA2x2_ENABLE_HIGH_G_Y_INTR_MSK (0x02) +#define BMA2x2_ENABLE_HIGH_G_Y_INTR_REG BMA2x2_INTR_ENABLE2_ADDR + +#define BMA2x2_ENABLE_HIGH_G_Z_INTR_POS (2) +#define BMA2x2_ENABLE_HIGH_G_Z_INTR_LEN (1) +#define BMA2x2_ENABLE_HIGH_G_Z_INTR_MSK (0x04) +#define BMA2x2_ENABLE_HIGH_G_Z_INTR_REG BMA2x2_INTR_ENABLE2_ADDR +/**********************************************/ +/**\name INTERRUPT ENABLE OF LOW_G */ +/**********************************************/ +#define BMA2x2_ENABLE_LOW_G_INTR_POS (3) +#define BMA2x2_ENABLE_LOW_G_INTR_LEN (1) +#define BMA2x2_ENABLE_LOW_G_INTR_MSK (0x08) +#define BMA2x2_ENABLE_LOW_G_INTR_REG BMA2x2_INTR_ENABLE2_ADDR +/**********************************************/ +/**\name INTERRUPT ENABLE OF DATA */ +/**********************************************/ +#define BMA2x2_ENABLE_NEW_DATA_INTR_POS (4) +#define BMA2x2_ENABLE_NEW_DATA_INTR_LEN (1) +#define BMA2x2_ENABLE_NEW_DATA_INTR_MSK (0x10) +#define BMA2x2_ENABLE_NEW_DATA_INTR_REG BMA2x2_INTR_ENABLE2_ADDR +/**********************************************/ +/**\name INTERRUPT ENABLE OF FIFO FULL */ +/**********************************************/ +#define BMA2x2_INTR_FIFO_FULL_ENABLE_INTR_POS (5) +#define BMA2x2_INTR_FIFO_FULL_ENABLE_INTR_LEN (1) +#define BMA2x2_INTR_FIFO_FULL_ENABLE_INTR_MSK (0x20) +#define BMA2x2_INTR_FIFO_FULL_ENABLE_INTR_REG BMA2x2_INTR_ENABLE2_ADDR +/**********************************************/ +/**\name INTERRUPT ENABLE OF FIFO WATER MARK */ +/**********************************************/ +#define BMA2x2_INTR_FIFO_WM_ENABLE_INTR_POS (6) +#define BMA2x2_INTR_FIFO_WM_ENABLE_INTR_LEN (1) +#define BMA2x2_INTR_FIFO_WM_ENABLE_INTR_MSK (0x40) +#define BMA2x2_INTR_FIFO_WM_ENABLE_INTR_REG BMA2x2_INTR_ENABLE2_ADDR +/************************************************/ +/**\name INTERRUPT ENABLE OF SLOW NO MOTION-XYZ */ +/*************************************************/ +#define BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_X_INTR_POS (0) +#define BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_X_INTR_LEN (1) +#define BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_X_INTR_MSK (0x01) +#define BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_X_INTR_REG \ +BMA2x2_INTR_SLOW_NO_MOTION_ADDR + +#define BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_Y_INTR_POS (1) +#define BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_Y_INTR_LEN (1) +#define BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_Y_INTR_MSK (0x02) +#define BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_Y_INTR_REG \ +BMA2x2_INTR_SLOW_NO_MOTION_ADDR + +#define BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_Z_INTR_POS (2) +#define BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_Z_INTR_LEN (1) +#define BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_Z_INTR_MSK (0x04) +#define BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_Z_INTR_REG \ +BMA2x2_INTR_SLOW_NO_MOTION_ADDR +/**********************************************/ +/**\name INTERRUPT ENABLE OF SLOW NO MOTION SELECT */ +/**********************************************/ +#define BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_SELECT_INTR_POS (3) +#define BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_SELECT_INTR_LEN (1) +#define BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_SELECT_INTR_MSK (0x08) +#define BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_SELECT_INTR_REG \ +BMA2x2_INTR_SLOW_NO_MOTION_ADDR +/**********************************************/ +/**\name INTERRUPT1 ENABLE OF PAD LOW_G */ +/**********************************************/ +#define BMA2x2_ENABLE_INTR1_PAD_LOW_G_POS (0) +#define BMA2x2_ENABLE_INTR1_PAD_LOW_G_LEN (1) +#define BMA2x2_ENABLE_INTR1_PAD_LOW_G_MSK (0x01) +#define BMA2x2_ENABLE_INTR1_PAD_LOW_G_REG BMA2x2_INTR1_PAD_SELECT_ADDR +/**********************************************/ +/**\name INTERRUPT1 ENABLE OF PAD HIGH_G */ +/**********************************************/ +#define BMA2x2_ENABLE_INTR1_PAD_HIGH_G_POS (1) +#define BMA2x2_ENABLE_INTR1_PAD_HIGH_G_LEN (1) +#define BMA2x2_ENABLE_INTR1_PAD_HIGH_G_MSK (0x02) +#define BMA2x2_ENABLE_INTR1_PAD_HIGH_G_REG BMA2x2_INTR1_PAD_SELECT_ADDR +/**********************************************/ +/**\name INTERRUPT1 ENABLE OF PAD SLOPE */ +/**********************************************/ +#define BMA2x2_ENABLE_INTR1_PAD_SLOPE_POS (2) +#define BMA2x2_ENABLE_INTR1_PAD_SLOPE_LEN (1) +#define BMA2x2_ENABLE_INTR1_PAD_SLOPE_MSK (0x04) +#define BMA2x2_ENABLE_INTR1_PAD_SLOPE_REG BMA2x2_INTR1_PAD_SELECT_ADDR +/**********************************************/ +/**\name INTERRUPT1 ENABLE OF SLOW NO MOTION */ +/**********************************************/ +#define BMA2x2_ENABLE_INTR1_PAD_SLOW_NO_MOTION_POS (3) +#define BMA2x2_ENABLE_INTR1_PAD_SLOW_NO_MOTION_LEN (1) +#define BMA2x2_ENABLE_INTR1_PAD_SLOW_NO_MOTION_MSK (0x08) +#define BMA2x2_ENABLE_INTR1_PAD_SLOW_NO_MOTION_REG \ +BMA2x2_INTR1_PAD_SELECT_ADDR +/**********************************************/ +/**\name INTERRUPT1 ENABLE OF PAD DOUBLE_TAP */ +/**********************************************/ +#define BMA2x2_ENABLE_INTR1_PAD_DOUBLE_TAP_POS (4) +#define BMA2x2_ENABLE_INTR1_PAD_DOUBLE_TAP_LEN (1) +#define BMA2x2_ENABLE_INTR1_PAD_DOUBLE_TAP_MSK (0x10) +#define BMA2x2_ENABLE_INTR1_PAD_DOUBLE_TAP_REG BMA2x2_INTR1_PAD_SELECT_ADDR +/**********************************************/ +/**\name INTERRUPT1 ENABLE OF PAD SINGLE_TAP */ +/**********************************************/ +#define BMA2x2_ENABLE_INTR1_PAD_SINGLE_TAP_POS (5) +#define BMA2x2_ENABLE_INTR1_PAD_SINGLE_TAP_LEN (1) +#define BMA2x2_ENABLE_INTR1_PAD_SINGLE_TAP_MSK (0x20) +#define BMA2x2_ENABLE_INTR1_PAD_SINGLE_TAP_REG BMA2x2_INTR1_PAD_SELECT_ADDR +/**********************************************/ +/**\name INTERRUPT1 ENABLE OF PAD ORIENT*/ +/**********************************************/ +#define BMA2x2_ENABLE_INTR1_PAD_ORIENT_POS (6) +#define BMA2x2_ENABLE_INTR1_PAD_ORIENT_LEN (1) +#define BMA2x2_ENABLE_INTR1_PAD_ORIENT_MSK (0x40) +#define BMA2x2_ENABLE_INTR1_PAD_ORIENT_REG BMA2x2_INTR1_PAD_SELECT_ADDR +/**********************************************/ +/**\name INTERRUPT1 ENABLE OF PAD FLAT */ +/**********************************************/ +#define BMA2x2_ENABLE_INTR1_PAD_FLAT_POS (7) +#define BMA2x2_ENABLE_INTR1_PAD_FLAT_LEN (1) +#define BMA2x2_ENABLE_INTR1_PAD_FLAT_MSK (0x80) +#define BMA2x2_ENABLE_INTR1_PAD_FLAT_REG BMA2x2_INTR1_PAD_SELECT_ADDR +/**********************************************/ +/**\name INTERRUPT2 ENABLE OF PAD LOW_G */ +/**********************************************/ +#define BMA2x2_ENABLE_INTR2_PAD_LOW_G_POS (0) +#define BMA2x2_ENABLE_INTR2_PAD_LOW_G_LEN (1) +#define BMA2x2_ENABLE_INTR2_PAD_LOW_G_MSK (0x01) +#define BMA2x2_ENABLE_INTR2_PAD_LOW_G_REG BMA2x2_INTR2_PAD_SELECT_ADDR +/**********************************************/ +/**\name INTERRUPT2 ENABLE OF PAD HIGH_G */ +/**********************************************/ +#define BMA2x2_ENABLE_INTR2_PAD_HIGH_G_POS (1) +#define BMA2x2_ENABLE_INTR2_PAD_HIGH_G_LEN (1) +#define BMA2x2_ENABLE_INTR2_PAD_HIGH_G_MSK (0x02) +#define BMA2x2_ENABLE_INTR2_PAD_HIGH_G_REG BMA2x2_INTR2_PAD_SELECT_ADDR +/**********************************************/ +/**\name INTERRUPT2 ENABLE OF PAD SLOPE */ +/**********************************************/ +#define BMA2x2_ENABLE_INTR2_PAD_SLOPE_POS (2) +#define BMA2x2_ENABLE_INTR2_PAD_SLOPE_LEN (1) +#define BMA2x2_ENABLE_INTR2_PAD_SLOPE_MSK (0x04) +#define BMA2x2_ENABLE_INTR2_PAD_SLOPE_REG BMA2x2_INTR2_PAD_SELECT_ADDR +/**********************************************/ +/**\name INTERRUPT2 ENABLE OF PAD SLOW NO MOTION */ +/**********************************************/ +#define BMA2x2_ENABLE_INTR2_PAD_SLOW_NO_MOTION_POS (3) +#define BMA2x2_ENABLE_INTR2_PAD_SLOW_NO_MOTION_LEN (1) +#define BMA2x2_ENABLE_INTR2_PAD_SLOW_NO_MOTION_MSK (0x08) +#define BMA2x2_ENABLE_INTR2_PAD_SLOW_NO_MOTION_REG \ +BMA2x2_INTR2_PAD_SELECT_ADDR +/**********************************************/ +/**\name INTERRUPT2 ENABLE OF PAD DOUBLE_TAP */ +/**********************************************/ +#define BMA2x2_ENABLE_INTR2_PAD_DOUBLE_TAP_POS (4) +#define BMA2x2_ENABLE_INTR2_PAD_DOUBLE_TAP_LEN (1) +#define BMA2x2_ENABLE_INTR2_PAD_DOUBLE_TAP_MSK (0x10) +#define BMA2x2_ENABLE_INTR2_PAD_DOUBLE_TAP_REG BMA2x2_INTR2_PAD_SELECT_ADDR +/**********************************************/ +/**\name INTERRUPT2 ENABLE OF PAD SINGLE_TAP */ +/**********************************************/ +#define BMA2x2_ENABLE_INTR2_PAD_SINGLE_TAP_POS (5) +#define BMA2x2_ENABLE_INTR2_PAD_SINGLE_TAP_LEN (1) +#define BMA2x2_ENABLE_INTR2_PAD_SINGLE_TAP_MSK (0x20) +#define BMA2x2_ENABLE_INTR2_PAD_SINGLE_TAP_REG BMA2x2_INTR2_PAD_SELECT_ADDR +/**********************************************/ +/**\name INTERRUPT2 ENABLE OF PAD ORIENT */ +/**********************************************/ +#define BMA2x2_ENABLE_INTR2_PAD_ORIENT_POS (6) +#define BMA2x2_ENABLE_INTR2_PAD_ORIENT_LEN (1) +#define BMA2x2_ENABLE_INTR2_PAD_ORIENT_MSK (0x40) +#define BMA2x2_ENABLE_INTR2_PAD_ORIENT_REG BMA2x2_INTR2_PAD_SELECT_ADDR +/**********************************************/ +/**\name INTERRUPT2 ENABLE OF PAD FLAT */ +/**********************************************/ +#define BMA2x2_ENABLE_INTR2_PAD_FLAT_POS (7) +#define BMA2x2_ENABLE_INTR2_PAD_FLAT_LEN (1) +#define BMA2x2_ENABLE_INTR2_PAD_FLAT_MSK (0x80) +#define BMA2x2_ENABLE_INTR2_PAD_FLAT_REG BMA2x2_INTR2_PAD_SELECT_ADDR +/**********************************************/ +/**\name INTERRUPT2 ENABLE OF PAD DATA */ +/**********************************************/ +#define BMA2x2_ENABLE_INTR1_PAD_NEWDATA_POS (0) +#define BMA2x2_ENABLE_INTR1_PAD_NEWDATA_LEN (1) +#define BMA2x2_ENABLE_INTR1_PAD_NEWDATA_MSK (0x01) +#define BMA2x2_ENABLE_INTR1_PAD_NEWDATA_REG BMA2x2_INTR_DATA_SELECT_ADDR +/**********************************************/ +/**\name INTERRUPT1 ENABLE OF FIFO WATER MARK */ +/**********************************************/ +#define BMA2x2_ENABLE_INTR1_PAD_FIFO_WM_POS (1) +#define BMA2x2_ENABLE_INTR1_PAD_FIFO_WM_LEN (1) +#define BMA2x2_ENABLE_INTR1_PAD_FIFO_WM_MSK (0x02) +#define BMA2x2_ENABLE_INTR1_PAD_FIFO_WM_REG BMA2x2_INTR_DATA_SELECT_ADDR +/**********************************************/ +/**\name INTERRUPT1 ENABLE OF FIFO FULL*/ +/**********************************************/ +#define BMA2x2_ENABLE_INTR1_PAD_FIFO_FULL_POS (2) +#define BMA2x2_ENABLE_INTR1_PAD_FIFO_FULL_LEN (1) +#define BMA2x2_ENABLE_INTR1_PAD_FIFO_FULL_MSK (0x04) +#define BMA2x2_ENABLE_INTR1_PAD_FIFO_FULL_REG BMA2x2_INTR_DATA_SELECT_ADDR +/**********************************************/ +/**\name INTERRUPT2 ENABLE OF PAD FIFO FULL */ +/**********************************************/ +#define BMA2x2_ENABLE_INTR2_PAD_FIFO_FULL_POS (5) +#define BMA2x2_ENABLE_INTR2_PAD_FIFO_FULL_LEN (1) +#define BMA2x2_ENABLE_INTR2_PAD_FIFO_FULL_MSK (0x20) +#define BMA2x2_ENABLE_INTR2_PAD_FIFO_FULL_REG BMA2x2_INTR_DATA_SELECT_ADDR +/**********************************************/ +/**\name INTERRUPT2 ENABLE OF PAD FIFO WATERMARK*/ +/**********************************************/ +#define BMA2x2_ENABLE_INTR2_PAD_FIFO_WM_POS (6) +#define BMA2x2_ENABLE_INTR2_PAD_FIFO_WM_LEN (1) +#define BMA2x2_ENABLE_INTR2_PAD_FIFO_WM_MSK (0x40) +#define BMA2x2_ENABLE_INTR2_PAD_FIFO_WM_REG BMA2x2_INTR_DATA_SELECT_ADDR +/**********************************************/ +/**\name INTERRUPT2 ENABLE OF PAD DATA */ +/**********************************************/ +#define BMA2x2_ENABLE_INTR2_PAD_NEWDATA_POS (7) +#define BMA2x2_ENABLE_INTR2_PAD_NEWDATA_LEN (1) +#define BMA2x2_ENABLE_INTR2_PAD_NEWDATA_MSK (0x80) +#define BMA2x2_ENABLE_INTR2_PAD_NEWDATA_REG BMA2x2_INTR_DATA_SELECT_ADDR +/**********************************************/ +/**\name INTERRUPT SOURCE SELECTION OF LOW_G*/ +/**********************************************/ +#define BMA2x2_UNFILT_INTR_SOURCE_LOW_G_POS (0) +#define BMA2x2_UNFILT_INTR_SOURCE_LOW_G_LEN (1) +#define BMA2x2_UNFILT_INTR_SOURCE_LOW_G_MSK (0x01) +#define BMA2x2_UNFILT_INTR_SOURCE_LOW_G_REG BMA2x2_INTR_SOURCE_ADDR +/**********************************************/ +/**\name INTERRUPT SOURCE SELECTION OF HIGH_G*/ +/**********************************************/ +#define BMA2x2_UNFILT_INTR_SOURCE_HIGH_G_POS (1) +#define BMA2x2_UNFILT_INTR_SOURCE_HIGH_G_LEN (1) +#define BMA2x2_UNFILT_INTR_SOURCE_HIGH_G_MSK (0x02) +#define BMA2x2_UNFILT_INTR_SOURCE_HIGH_G_REG BMA2x2_INTR_SOURCE_ADDR +/**********************************************/ +/**\name INTERRUPT SOURCE SELECTION OF SLOPE*/ +/**********************************************/ +#define BMA2x2_UNFILT_INTR_SOURCE_SLOPE_POS (2) +#define BMA2x2_UNFILT_INTR_SOURCE_SLOPE_LEN (1) +#define BMA2x2_UNFILT_INTR_SOURCE_SLOPE_MSK (0x04) +#define BMA2x2_UNFILT_INTR_SOURCE_SLOPE_REG BMA2x2_INTR_SOURCE_ADDR +/**********************************************/ +/**\name INTERRUPT SOURCE SELECTION OF SLOW NO MOTION*/ +/**********************************************/ +#define BMA2x2_UNFILT_INTR_SOURCE_SLOW_NO_MOTION_POS (3) +#define BMA2x2_UNFILT_INTR_SOURCE_SLOW_NO_MOTION_LEN (1) +#define BMA2x2_UNFILT_INTR_SOURCE_SLOW_NO_MOTION_MSK (0x08) +#define BMA2x2_UNFILT_INTR_SOURCE_SLOW_NO_MOTION_REG \ +BMA2x2_INTR_SOURCE_ADDR +/**********************************************/ +/**\name INTERRUPT SOURCE SELECTION OF TAP*/ +/**********************************************/ +#define BMA2x2_UNFILT_INTR_SOURCE_TAP_POS (4) +#define BMA2x2_UNFILT_INTR_SOURCE_TAP_LEN (1) +#define BMA2x2_UNFILT_INTR_SOURCE_TAP_MSK (0x10) +#define BMA2x2_UNFILT_INTR_SOURCE_TAP_REG BMA2x2_INTR_SOURCE_ADDR +/**********************************************/ +/**\name INTERRUPT SOURCE SELECTION OF DATA*/ +/**********************************************/ +#define BMA2x2_UNFILT_INTR_SOURCE_DATA_POS (5) +#define BMA2x2_UNFILT_INTR_SOURCE_DATA_LEN (1) +#define BMA2x2_UNFILT_INTR_SOURCE_DATA_MSK (0x20) +#define BMA2x2_UNFILT_INTR_SOURCE_DATA_REG BMA2x2_INTR_SOURCE_ADDR +/****************************************************/ +/**\name INTERRUPT PAD ACTIVE LEVEL AND OUTPUT TYPE*/ +/****************************************************/ +#define BMA2x2_INTR1_PAD_ACTIVE_LEVEL_POS (0) +#define BMA2x2_INTR1_PAD_ACTIVE_LEVEL_LEN (1) +#define BMA2x2_INTR1_PAD_ACTIVE_LEVEL_MSK (0x01) +#define BMA2x2_INTR1_PAD_ACTIVE_LEVEL_REG BMA2x2_INTR_SET_ADDR + +#define BMA2x2_INTR2_PAD_ACTIVE_LEVEL_POS (2) +#define BMA2x2_INTR2_PAD_ACTIVE_LEVEL_LEN (1) +#define BMA2x2_INTR2_PAD_ACTIVE_LEVEL_MSK (0x04) +#define BMA2x2_INTR2_PAD_ACTIVE_LEVEL_REG BMA2x2_INTR_SET_ADDR + +#define BMA2x2_INTR1_PAD_OUTPUT_TYPE_POS (1) +#define BMA2x2_INTR1_PAD_OUTPUT_TYPE_LEN (1) +#define BMA2x2_INTR1_PAD_OUTPUT_TYPE_MSK (0x02) +#define BMA2x2_INTR1_PAD_OUTPUT_TYPE_REG BMA2x2_INTR_SET_ADDR + +#define BMA2x2_INTR2_PAD_OUTPUT_TYPE_POS (3) +#define BMA2x2_INTR2_PAD_OUTPUT_TYPE_LEN (1) +#define BMA2x2_INTR2_PAD_OUTPUT_TYPE_MSK (0x08) +#define BMA2x2_INTR2_PAD_OUTPUT_TYPE_REG BMA2x2_INTR_SET_ADDR +/****************************************************/ +/**\name LATCH INTERRUPT */ +/****************************************************/ +#define BMA2x2_LATCH_INTR_POS (0) +#define BMA2x2_LATCH_INTR_LEN (4) +#define BMA2x2_LATCH_INTR_MSK (0x0F) +#define BMA2x2_LATCH_INTR_REG BMA2x2_INTR_CTRL_ADDR +/****************************************************/ +/**\name RESET LATCH INTERRUPT */ +/****************************************************/ +#define BMA2x2_RESET_INTR_POS (7) +#define BMA2x2_RESET_INTR_LEN (1) +#define BMA2x2_RESET_INTR_MSK (0x80) +#define BMA2x2_RESET_INTR_REG BMA2x2_INTR_CTRL_ADDR +/****************************************************/ +/**\name LOW_G HYSTERESIS */ +/****************************************************/ +#define BMA2x2_LOW_G_HYST_POS (0) +#define BMA2x2_LOW_G_HYST_LEN (2) +#define BMA2x2_LOW_G_HYST_MSK (0x03) +#define BMA2x2_LOW_G_HYST_REG BMA2x2_LOW_HIGH_HYST_ADDR +/****************************************************/ +/**\name LOW_G MODE */ +/****************************************************/ +#define BMA2x2_LOW_G_INTR_MODE_POS (2) +#define BMA2x2_LOW_G_INTR_MODE_LEN (1) +#define BMA2x2_LOW_G_INTR_MODE_MSK (0x04) +#define BMA2x2_LOW_G_INTR_MODE_REG BMA2x2_LOW_HIGH_HYST_ADDR + +/****************************************************/ +/**\name HIGH_G HYSTERESIS */ +/****************************************************/ +#define BMA2x2_HIGH_G_HYST_POS (6) +#define BMA2x2_HIGH_G_HYST_LEN (2) +#define BMA2x2_HIGH_G_HYST_MSK (0xC0) +#define BMA2x2_HIGH_G_HYST_REG BMA2x2_LOW_HIGH_HYST_ADDR +/****************************************************/ +/**\name SLOPE DURATION */ +/****************************************************/ +#define BMA2x2_SLOPE_DURN_POS (0) +#define BMA2x2_SLOPE_DURN_LEN (2) +#define BMA2x2_SLOPE_DURN_MSK (0x03) +#define BMA2x2_SLOPE_DURN_REG BMA2x2_SLOPE_DURN_ADDR +/****************************************************/ +/**\name SLOW NO MOTION DURATION */ +/****************************************************/ +#define BMA2x2_SLOW_NO_MOTION_DURN_POS (2) +#define BMA2x2_SLOW_NO_MOTION_DURN_LEN (6) +#define BMA2x2_SLOW_NO_MOTION_DURN_MSK (0xFC) +#define BMA2x2_SLOW_NO_MOTION_DURN_REG BMA2x2_SLOPE_DURN_ADDR + +/****************************************************/ +/**\name TAP DURATION */ +/****************************************************/ +#define BMA2x2_TAP_DURN_POS (0) +#define BMA2x2_TAP_DURN_LEN (3) +#define BMA2x2_TAP_DURN_MSK (0x07) +#define BMA2x2_TAP_DURN_REG BMA2x2_TAP_PARAM_ADDR + +/****************************************************/ +/**\name TAP SHOCK DURATION */ +/****************************************************/ +#define BMA2x2_TAP_SHOCK_DURN_POS (6) +#define BMA2x2_TAP_SHOCK_DURN_LEN (1) +#define BMA2x2_TAP_SHOCK_DURN_MSK (0x40) +#define BMA2x2_TAP_SHOCK_DURN_REG BMA2x2_TAP_PARAM_ADDR + +/* This advance tap interrupt only uses for the chip id 0xFB */ +#define BMA2x2_ADV_TAP_INTR_POS (5) +#define BMA2x2_ADV_TAP_INTR_LEN (1) +#define BMA2x2_ADV_TAP_INTR_MSK (0x20) +#define BMA2x2_ADV_TAP_INTR_REG BMA2x2_TAP_PARAM_ADDR +/****************************************************/ +/**\name TAP QUIET DURATION */ +/****************************************************/ +#define BMA2x2_TAP_QUIET_DURN_POS (7) +#define BMA2x2_TAP_QUIET_DURN_LEN (1) +#define BMA2x2_TAP_QUIET_DURN_MSK (0x80) +#define BMA2x2_TAP_QUIET_DURN_REG BMA2x2_TAP_PARAM_ADDR +/****************************************************/ +/**\name TAP THRESHOLD */ +/****************************************************/ +#define BMA2x2_TAP_THRES_POS (0) +#define BMA2x2_TAP_THRES_LEN (5) +#define BMA2x2_TAP_THRES_MSK (0x1F) +#define BMA2x2_TAP_THRES_REG BMA2x2_TAP_THRES_ADDR +/****************************************************/ +/**\name TAP SAMPLES */ +/****************************************************/ +#define BMA2x2_TAP_SAMPLES_POS (6) +#define BMA2x2_TAP_SAMPLES_LEN (2) +#define BMA2x2_TAP_SAMPLES_MSK (0xC0) +#define BMA2x2_TAP_SAMPLES_REG BMA2x2_TAP_THRES_ADDR +/****************************************************/ +/**\name ORIENT MODE */ +/****************************************************/ +#define BMA2x2_ORIENT_MODE_POS (0) +#define BMA2x2_ORIENT_MODE_LEN (2) +#define BMA2x2_ORIENT_MODE_MSK (0x03) +#define BMA2x2_ORIENT_MODE_REG BMA2x2_ORIENT_PARAM_ADDR +/****************************************************/ +/**\name ORIENT BLOCKING */ +/****************************************************/ +#define BMA2x2_ORIENT_BLOCK_POS (2) +#define BMA2x2_ORIENT_BLOCK_LEN (2) +#define BMA2x2_ORIENT_BLOCK_MSK (0x0C) +#define BMA2x2_ORIENT_BLOCK_REG BMA2x2_ORIENT_PARAM_ADDR +/****************************************************/ +/**\name ORIENT HYSTERESIS */ +/****************************************************/ +#define BMA2x2_ORIENT_HYST_POS (4) +#define BMA2x2_ORIENT_HYST_LEN (3) +#define BMA2x2_ORIENT_HYST_MSK (0x70) +#define BMA2x2_ORIENT_HYST_REG BMA2x2_ORIENT_PARAM_ADDR +/****************************************************/ +/**\name ORIENT AXIS */ +/****************************************************/ +#define BMA2x2_ORIENT_UD_ENABLE_POS (6) +#define BMA2x2_ORIENT_UD_ENABLE_LEN (1) +#define BMA2x2_ORIENT_UD_ENABLE_MSK (0x40) +#define BMA2x2_ORIENT_UD_ENABLE_REG BMA2x2_THETA_BLOCK_ADDR + +/****************************************************/ +/**\name THETA BLOCKING */ +/****************************************************/ +#define BMA2x2_THETA_BLOCK_POS (0) +#define BMA2x2_THETA_BLOCK_LEN (6) +#define BMA2x2_THETA_BLOCK_MSK (0x3F) +#define BMA2x2_THETA_BLOCK_REG BMA2x2_THETA_BLOCK_ADDR +/****************************************************/ +/**\name THETA FLAT */ +/****************************************************/ +#define BMA2x2_THETA_FLAT_POS (0) +#define BMA2x2_THETA_FLAT_LEN (6) +#define BMA2x2_THETA_FLAT_MSK (0x3F) +#define BMA2x2_THETA_FLAT_REG BMA2x2_THETA_FLAT_ADDR +/****************************************************/ +/**\name THETA HOLD TIME */ +/****************************************************/ +#define BMA2x2_FLAT_HOLD_TIME_POS (4) +#define BMA2x2_FLAT_HOLD_TIME_LEN (2) +#define BMA2x2_FLAT_HOLD_TIME_MSK (0x30) +#define BMA2x2_FLAT_HOLD_TIME_REG BMA2x2_FLAT_HOLD_TIME_ADDR +/****************************************************/ +/**\name FLAT HYSTERESIS */ +/****************************************************/ +#define BMA2x2_FLAT_HYST_POS (0) +#define BMA2x2_FLAT_HYST_LEN (3) +#define BMA2x2_FLAT_HYST_MSK (0x07) +#define BMA2x2_FLAT_HYST_REG BMA2x2_FLAT_HOLD_TIME_ADDR +/****************************************************/ +/**\name FIFO WATER MARK LEVEL TRIGGER RETAIN */ +/****************************************************/ +#define BMA2x2_FIFO_WML_TRIG_RETAIN_POS (0) +#define BMA2x2_FIFO_WML_TRIG_RETAIN_LEN (6) +#define BMA2x2_FIFO_WML_TRIG_RETAIN_MSK (0x3F) +#define BMA2x2_FIFO_WML_TRIG_RETAIN_REG BMA2x2_FIFO_WML_TRIG +/****************************************************/ +/**\name ACTIVATE SELF TEST */ +/****************************************************/ +#define BMA2x2_ENABLE_SELFTEST_POS (0) +#define BMA2x2_ENABLE_SELFTEST_LEN (2) +#define BMA2x2_ENABLE_SELFTEST_MSK (0x03) +#define BMA2x2_ENABLE_SELFTEST_REG BMA2x2_SELFTEST_ADDR +/****************************************************/ +/**\name SELF TEST -- NEGATIVE */ +/****************************************************/ +#define BMA2x2_NEG_SELFTEST_POS (2) +#define BMA2x2_NEG_SELFTEST_LEN (1) +#define BMA2x2_NEG_SELFTEST_MSK (0x04) +#define BMA2x2_NEG_SELFTEST_REG BMA2x2_SELFTEST_ADDR +/****************************************************/ +/**\name EEPROM CONTROL */ +/****************************************************/ +#define BMA2x2_UNLOCK_EE_PROG_MODE_POS (0) +#define BMA2x2_UNLOCK_EE_PROG_MODE_LEN (1) +#define BMA2x2_UNLOCK_EE_PROG_MODE_MSK (0x01) +#define BMA2x2_UNLOCK_EE_PROG_MODE_REG BMA2x2_EEPROM_CTRL_ADDR +/**********************************************************************/ +/**\name SETTING THIS BIT STARTS WRITING SETTING REGISTERS TO EEPROM */ +/*********************************************************************/ +#define BMA2x2_START_EE_PROG_TRIG_POS (1) +#define BMA2x2_START_EE_PROG_TRIG_LEN (1) +#define BMA2x2_START_EE_PROG_TRIG_MSK (0x02) +#define BMA2x2_START_EE_PROG_TRIG_REG BMA2x2_EEPROM_CTRL_ADDR +/****************************************************/ +/**\name STATUS OF WRITING TO EEPROM */ +/****************************************************/ +#define BMA2x2_EE_PROG_READY_POS (2) +#define BMA2x2_EE_PROG_READY_LEN (1) +#define BMA2x2_EE_PROG_READY_MSK (0x04) +#define BMA2x2_EE_PROG_READY_REG BMA2x2_EEPROM_CTRL_ADDR +/****************************************************/ +/**\name UPDATE IMAGE REGISTERS WRITING TO EEPROM */ +/****************************************************/ +#define BMA2x2_UPDATE_IMAGE_POS (3) +#define BMA2x2_UPDATE_IMAGE_LEN (1) +#define BMA2x2_UPDATE_IMAGE_MSK (0x08) +#define BMA2x2_UPDATE_IMAGE_REG BMA2x2_EEPROM_CTRL_ADDR + +#define BMA2x2_EE_REMAIN_POS (4) +#define BMA2x2_EE_REMAIN_LEN (4) +#define BMA2x2_EE_REMAIN_MSK (0xF0) +#define BMA2x2_EE_REMAIN_REG BMA2x2_EEPROM_CTRL_ADDR +/****************************************************/ +/**\name SPI INTERFACE MODE SELECTION */ +/***************************************************/ +#define BMA2x2_ENABLE_SPI_MODE_3_POS (0) +#define BMA2x2_ENABLE_SPI_MODE_3_LEN (1) +#define BMA2x2_ENABLE_SPI_MODE_3_MSK (0x01) +#define BMA2x2_ENABLE_SPI_MODE_3_REG BMA2x2_SERIAL_CTRL_ADDR +/****************************************************/ +/**\name I2C WATCHDOG PERIOD SELECTION */ +/***************************************************/ +#define BMA2x2_I2C_WDT_PERIOD_POS (1) +#define BMA2x2_I2C_WDT_PERIOD_LEN (1) +#define BMA2x2_I2C_WDT_PERIOD_MSK (0x02) +#define BMA2x2_I2C_WDT_PERIOD_REG BMA2x2_SERIAL_CTRL_ADDR +/****************************************************/ +/**\name I2C WATCHDOG ENABLE */ +/***************************************************/ +#define BMA2x2_ENABLE_I2C_WDT_POS (2) +#define BMA2x2_ENABLE_I2C_WDT_LEN (1) +#define BMA2x2_ENABLE_I2C_WDT_MSK (0x04) +#define BMA2x2_ENABLE_I2C_WDT_REG BMA2x2_SERIAL_CTRL_ADDR +/****************************************************/ +/**\name SPI INTERFACE MODE SELECTIONE */ +/***************************************************/ +#define BMA2x2_UNLOCK_EE_WRITE_TRIM_POS (4) +#define BMA2x2_UNLOCK_EE_WRITE_TRIM_LEN (4) +#define BMA2x2_UNLOCK_EE_WRITE_TRIM_MSK (0xF0) +#define BMA2x2_UNLOCK_EE_WRITE_TRIM_REG BMA2x2_CTRL_UNLOCK_REG +/******************************************************************/ +/**\name OFFSET COMPENSATION/SLOW COMPENSATION FOR X,Y,Z AXIS */ +/*****************************************************************/ +#define BMA2x2_ENABLE_SLOW_COMP_X_POS (0) +#define BMA2x2_ENABLE_SLOW_COMP_X_LEN (1) +#define BMA2x2_ENABLE_SLOW_COMP_X_MSK (0x01) +#define BMA2x2_ENABLE_SLOW_COMP_X_REG BMA2x2_OFFSET_CTRL_ADDR + +#define BMA2x2_ENABLE_SLOW_COMP_Y_POS (1) +#define BMA2x2_ENABLE_SLOW_COMP_Y_LEN (1) +#define BMA2x2_ENABLE_SLOW_COMP_Y_MSK (0x02) +#define BMA2x2_ENABLE_SLOW_COMP_Y_REG BMA2x2_OFFSET_CTRL_ADDR + +#define BMA2x2_ENABLE_SLOW_COMP_Z_POS (2) +#define BMA2x2_ENABLE_SLOW_COMP_Z_LEN (1) +#define BMA2x2_ENABLE_SLOW_COMP_Z_MSK (0x04) +#define BMA2x2_ENABLE_SLOW_COMP_Z_REG BMA2x2_OFFSET_CTRL_ADDR +/****************************************************/ +/**\name FAST COMPENSATION READY FLAG */ +/***************************************************/ +#define BMA2x2_FAST_CAL_RDY_STAT_POS (4) +#define BMA2x2_FAST_CAL_RDY_STAT_LEN (1) +#define BMA2x2_FAST_CAL_RDY_STAT_MSK (0x10) +#define BMA2x2_FAST_CAL_RDY_STAT_REG BMA2x2_OFFSET_CTRL_ADDR +/****************************************************/ +/**\name FAST COMPENSATION FOR X,Y,Z AXIS */ +/***************************************************/ +#define BMA2x2_CAL_TRIGGER_POS (5) +#define BMA2x2_CAL_TRIGGER_LEN (2) +#define BMA2x2_CAL_TRIGGER_MSK (0x60) +#define BMA2x2_CAL_TRIGGER_REG BMA2x2_OFFSET_CTRL_ADDR +/****************************************************/ +/**\name RESET OFFSET REGISTERS */ +/***************************************************/ +#define BMA2x2_RST_OFFSET_POS (7) +#define BMA2x2_RST_OFFSET_LEN (1) +#define BMA2x2_RST_OFFSET_MSK (0x80) +#define BMA2x2_RST_OFFSET_REG BMA2x2_OFFSET_CTRL_ADDR +/****************************************************/ +/**\name SLOW COMPENSATION CUTOFF */ +/***************************************************/ +#define BMA2x2_COMP_CUTOFF_POS (0) +#define BMA2x2_COMP_CUTOFF_LEN (1) +#define BMA2x2_COMP_CUTOFF_MSK (0x01) +#define BMA2x2_COMP_CUTOFF_REG BMA2x2_OFFSET_PARAMS_ADDR +/****************************************************/ +/**\name COMPENSATION TARGET */ +/***************************************************/ +#define BMA2x2_COMP_TARGET_OFFSET_X_POS (1) +#define BMA2x2_COMP_TARGET_OFFSET_X_LEN (2) +#define BMA2x2_COMP_TARGET_OFFSET_X_MSK (0x06) +#define BMA2x2_COMP_TARGET_OFFSET_X_REG BMA2x2_OFFSET_PARAMS_ADDR + +#define BMA2x2_COMP_TARGET_OFFSET_Y_POS (3) +#define BMA2x2_COMP_TARGET_OFFSET_Y_LEN (2) +#define BMA2x2_COMP_TARGET_OFFSET_Y_MSK (0x18) +#define BMA2x2_COMP_TARGET_OFFSET_Y_REG BMA2x2_OFFSET_PARAMS_ADDR + +#define BMA2x2_COMP_TARGET_OFFSET_Z_POS (5) +#define BMA2x2_COMP_TARGET_OFFSET_Z_LEN (2) +#define BMA2x2_COMP_TARGET_OFFSET_Z_MSK (0x60) +#define BMA2x2_COMP_TARGET_OFFSET_Z_REG BMA2x2_OFFSET_PARAMS_ADDR +/****************************************************/ +/**\name FIFO DATA SELECT */ +/***************************************************/ +#define BMA2x2_FIFO_DATA_SELECT_POS (0) +#define BMA2x2_FIFO_DATA_SELECT_LEN (2) +#define BMA2x2_FIFO_DATA_SELECT_MSK (0x03) +#define BMA2x2_FIFO_DATA_SELECT_REG BMA2x2_FIFO_MODE_ADDR +/****************************************************/ +/**\name FIFO MODE */ +/***************************************************/ +#define BMA2x2_FIFO_MODE_POS (6) +#define BMA2x2_FIFO_MODE_LEN (2) +#define BMA2x2_FIFO_MODE_MSK (0xC0) +#define BMA2x2_FIFO_MODE_REG BMA2x2_FIFO_MODE_ADDR + +/****************************************************/ +/**\name BITSLICE FUNCTIONS */ +/***************************************************/ +#define BMA2x2_GET_BITSLICE(regvar, bitname)\ +((regvar & bitname##_MSK) >> bitname##_POS) + + +#define BMA2x2_SET_BITSLICE(regvar, bitname, val)\ +((regvar & ~bitname##_MSK) | ((val< + * Example: BMA2x2_LOW_TH_IN_G( 0.3, 2.0) generates + * the register value for 0.3G threshold in 2G mode. + * \brief convert g-values to 8-bit value + */ +#define BMA2x2_LOW_THRES_IN_G(gthres, range) ((256 * gthres) / range) + +/** Macro to convert floating point high-g-thresholds + in G to 8-bit register values.
+ * Example: BMA2x2_HIGH_TH_IN_G( 1.4, 2.0) + * generates the register value for 1.4G threshold in 2G mode. + * \brief convert g-values to 8-bit value + */ +#define BMA2x2_HIGH_THRES_IN_G(gthres, range) ((256 * gthres) / range) + +/** Macro to convert floating point low-g-hysteresis +in G to 8-bit register values.
+ * Example: BMA2x2_LOW_HY_IN_G( 0.2, 2.0) + *generates the register value for 0.2G threshold in 2G mode. + * \brief convert g-values to 8-bit value + */ +#define BMA2x2_LOW_HYST_IN_G(ghyst, range) ((32 * ghyst) / range) + +/** Macro to convert floating point high-g-hysteresis + in G to 8-bit register values.
+ * Example: BMA2x2_HIGH_HY_IN_G( 0.2, 2.0) generates + *the register value for 0.2G threshold in 2G mode. + * \brief convert g-values to 8-bit value + */ +#define BMA2x2_HIGH_HYST_IN_G(ghyst, range) ((32 * ghyst) / range) + + +/** Macro to convert floating point G-thresholds + to 8-bit register values
+ * Example: BMA2x2_SLOPE_TH_IN_G( 1.2, 2.0) + * generates the register value for 1.2G threshold in 2G mode. + * \brief convert g-values to 8-bit value + */ + +#define BMA2x2_SLOPE_THRES_IN_G(gthres, range) ((128 * gthres) / range) +/******************************************/ +/**\name FUNCTION DECLARATION */ +/******************************************/ +/******************************************/ +/**\name FUNCTION FOR COMMON READ AND WRITE */ +/******************************************/ +/*! + * @brief + * This API reads the data from + * the given register continuously + * + * + * @param addr_u8 -> Address of the register + * @param data_u8 -> The data from the register + * @param len_u32 -> no of bytes to read + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_burst_read(u8 addr_u8, + u8 *data_u8, u32 len_u32); +/******************************************/ +/**\name FUNCTION FOR INTIALIZE */ +/******************************************/ +/*! + * @brief + * This function is used for initialize + * bus read and bus write functions + * assign the chip id and device address + * chip id is read in the register 0x00 bit from 0 to 7 + * + * @param bma2x2 : structure pointer + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * @note + * While changing the parameter of the bma2x2_t + * consider the following point: + * Changing the reference value of the parameter + * will changes the local copy or local reference + * make sure your changes will not + * affect the reference value of the parameter + * (Better case don't change the reference value of the parameter) + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_init(struct bma2x2_t *bma2x2); +/*! + * @brief + * This API gives data to the given register and + * the data is written in the corresponding register address + * + * + * @param adr_u8 -> Address of the register + * @param data_u8 -> The data to the register + * @param len_u8 -> no of bytes to read + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_write_reg(u8 adr_u8, + u8 *data_u8, u8 len_u8); +/*! + * @brief This API reads the data from + * the given register address + * + * + * @param adr_u8 -> Address of the register + * @param data_u8 -> The data from the register + * @param len_u8 -> no of bytes to read + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_reg(u8 adr_u8, + u8 *data_u8, u8 len_u8); +/******************************************/ +/**\name FUNCTION FOR DATA READ*/ +/******************************************/ +/*! + * @brief + * This API reads acceleration data X values + * from location 02h and 03h + * + * + * @param accel_x_s16 : pointer holding the data of accel X + * value | resolution + * ----------------- | -------------- + * 0 | BMA2x2_12_RESOLUTION + * 1 | BMA2x2_10_RESOLUTION + * 2 | BMA2x2_14_RESOLUTION + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_x(s16 *accel_x_s16); +/*! + * @brief + * This API reads acceleration data X values + * from location 02h and 03h bit resolution support 8bit + * + * + * @param accel_x_s8 : pointer holding the data of accel X + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_eight_resolution_x( + s8 *accel_x_s8); +/*! + * @brief + * This API reads acceleration data Y values + * from location 04h and 05h + * + * @param accel_y_s16 : pointer holding the data of accel Y + * value | resolution + * ----------------- | -------------- + * 0 | BMA2x2_12_RESOLUTION + * 1 | BMA2x2_10_RESOLUTION + * 2 | BMA2x2_14_RESOLUTION + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_y(s16 *accel_y_s16); +/*! + * @brief This API reads acceleration data Y values of + * 8bit resolution from location 05h + * + * + * + * + * @param accel_y_s8 The data of y + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_eight_resolution_y( + s8 *accel_y_s8); +/*! + * @brief This API reads acceleration data Z values + * from location 06h and 07h + * + * + * @param accel_z_s16 : pointer holding the data of accel Z + * value | resolution + * ----------------- | -------------- + * 0 | BMA2x2_12_RESOLUTION + * 1 | BMA2x2_10_RESOLUTION + * 2 | BMA2x2_14_RESOLUTION + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_z(s16 *accel_z_s16); +/*! + * @brief + * This API reads acceleration data Z values of + * 8bit resolution from location 07h + * + * + * + * + * \@aram accel_z_s8 : the data of z + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_eight_resolution_z( + s8 *accel_z_s8); +/*! + * @brief This API reads acceleration data X,Y,Z values + * from location 02h to 07h + * + * @param accel : pointer holding the data of accel + * value | resolution + * ----------------- | -------------- + * 0 | BMA2x2_12_RESOLUTION + * 1 | BMA2x2_10_RESOLUTION + * 2 | BMA2x2_14_RESOLUTION + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_xyz( + struct bma2x2_accel_data *accel); +/*! + * @brief This API reads acceleration of 8 bit resolution + * data of X,Y,Z values + * from location 03h , 05h and 07h + * + * + * + * + * @param accel : pointer holding the data of accel + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_eight_resolution_xyz( + struct bma2x2_accel_eight_resolution *accel); +/******************************************/ +/**\name FUNCTION FOR INTERRUPT STATUS*/ +/******************************************/ +/*! + * @brief This API read tap-sign, tap-first-xyz + * slope-sign, slope-first-xyz status register byte + * from location 0Bh + * + * @param stat_tap_u8 : The status of tap and slope + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_tap_stat( + u8 *stat_tap_u8); +/*! + * @brief This API read orient, high-sign and high-first-xyz + * status register byte from location 0Ch + * + * + * @param stat_orient_u8 : The status of orient and high + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_orient_stat( + u8 *stat_orient_u8); +/*! + * @brief This API reads fifo overrun and fifo frame counter + * status register byte from location 0Eh + * + * @param stat_fifo_u8 : The status of fifo overrun and frame counter + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_fifo_stat( + u8 *stat_fifo_u8); +/*! + * @brief This API read fifo frame count + * from location 0Eh bit position 0 to 6 + * + * + * @param frame_count_u8 : The status of fifo frame count + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_fifo_frame_count( + u8 *frame_count_u8); +/*! + * @brief This API read fifo overrun + * from location 0Eh bit position 7 + * + * + * @param fifo_overrun_u8 : The status of fifo overrun + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_fifo_overrun( + u8 *fifo_overrun_u8); +/******************************************/ +/**\name FUNCTION FOR RANGE */ +/******************************************/ +/*! + * @brief This API read interrupt status of flat, orient, single tap, + * double tap, slow no motion, slope, highg and lowg from location 09h + * + * + * + * @param intr_stat_u8 : The value of interrupt status + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_stat( + u8 *intr_stat_u8); +/*! + * @brief This API is used to get the ranges(g values) of the sensor + * in the register 0x0F bit from 0 to 3 + * + * + * @param range_u8 : The value of range + * range_u8 | result + * ----------------- | -------------- + * 0x03 | BMA2x2_RANGE_2G + * 0x05 | BMA2x2_RANGE_4G + * 0x08 | BMA2x2_RANGE_8G + * 0x0C | BMA2x2_RANGE_16G + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_range(u8 *range_u8); +/*! + * @brief This API is used to set the ranges(g values) of the sensor + * in the register 0x0F bit from 0 to 3 + * + * + * @param range_u8 : The value of range + * range_u8 | result + * ----------------- | -------------- + * 0x03 | BMA2x2_RANGE_2G + * 0x05 | BMA2x2_RANGE_4G + * 0x08 | BMA2x2_RANGE_8G + * 0x0C | BMA2x2_RANGE_16G + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_range(u8 range_u8); +/******************************************/ +/**\name FUNCTION FOR BANDWIDTH*/ +/******************************************/ +/*! + * @brief This API is used to get the bandwidth of the sensor in the register + * 0x10 bit from 0 to 4 + * + * + * @param bw_u8 : The value of bandwidth + * bw_u8 | result + * ----------------- | -------------- + * 0x08 | BMA2x2_BW_7_81HZ + * 0x09 | BMA2x2_BW_15_63HZ + * 0x0A | BMA2x2_BW_31_25HZ + * 0x0B | BMA2x2_BW_62_50HZ + * 0x0C | BMA2x2_BW_125HZ + * 0x0D | BMA2x2_BW_250HZ + * 0x0E | BMA2x2_BW_500HZ + * 0x0F | BMA2x2_BW_1000HZ + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_bw(u8 *bw_u8); +/*! + * @brief This API is used to set the bandwidth of the sensor in the register + * 0x10 bit from 0 to 4 + * + * + * @param bw_u8 : The value of bandwidth + * bw_u8 | result + * ----------------- | -------------- + * 0x08 | BMA2x2_BW_7_81HZ + * 0x09 | BMA2x2_BW_15_63HZ + * 0x0A | BMA2x2_BW_31_25HZ + * 0x0B | BMA2x2_BW_62_50HZ + * 0x0C | BMA2x2_BW_125HZ + * 0x0D | BMA2x2_BW_250HZ + * 0x0E | BMA2x2_BW_500HZ + * 0x0F | BMA2x2_BW_1000HZ + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_bw(u8 bw_u8); +/******************************************/ +/**\name FUNCTION FOR POWER MODE*/ +/******************************************/ +/*! + * @brief This API is used to get the operating + * modes of the sensor in the register 0x11 and 0x12 + * @note Register 0x11 - bit from 5 to 7 + * @note Register 0x12 - bit from 5 and 6 + * + * + * @param power_mode_u8 : The value of power mode + * power_mode_u8 |value | 0x11 | 0x12 + * ------------------------- |-------| --------|-------- + * BMA2x2_MODE_NORMAL | 0 | 0x00 | 0x00 + * BMA2x2_MODE_LOWPOWER1 | 1 | 0x02 | 0x00 + * BMA2x2_MODE_SUSPEND | 2 | 0x06 | 0x00 + * BMA2x2_MODE_DEEP_SUSPEND | 3 | 0x01 | 0x00 + * BMA2x2_MODE_LOWPOWER2 | 4 | 0x02 | 0x01 + * BMA2x2_MODE_STANDBY | 5 | 0x04 | 0x00 + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_power_mode( + u8 *power_mode_u8); +/*! + * @brief This API is used to set the operating + * modes of the sensor in the register 0x11 and 0x12 + * @note Register 0x11 - bit from 5 to 7 + * @note Register 0x12 - bit from 5 and 6 + * + * + * @param power_mode_u8 : The value of power mode + * power_mode_u8 |value | 0x11 | 0x12 + * ------------------------- |-------| --------|-------- + * BMA2x2_MODE_NORMAL | 0 | 0x00 | 0x00 + * BMA2x2_MODE_LOWPOWER1 | 1 | 0x02 | 0x00 + * BMA2x2_MODE_SUSPEND | 2 | 0x06 | 0x00 + * BMA2x2_MODE_DEEP_SUSPEND | 3 | 0x01 | 0x00 + * BMA2x2_MODE_LOWPOWER2 | 4 | 0x02 | 0x01 + * BMA2x2_MODE_STANDBY | 5 | 0x04 | 0x00 + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_power_mode(u8 power_mode_u8); +/*! + * @brief This API is used to assign the power mode values + * modes of the sensor in the register 0x11 and 0x12 + * @note Register 0x11 - bit from 5 to 7 + * @note Register 0x12 - bit from 5 and 6 + * + * + * @param power_mode_u8 : The value of power mode + * power_mode_u8 |value | 0x11 | 0x12 + * ------------------------- |-------| --------|-------- + * BMA2x2_MODE_NORMAL | 0 | 0x00 | 0x00 + * BMA2x2_MODE_LOWPOWER1 | 1 | 0x02 | 0x00 + * BMA2x2_MODE_SUSPEND | 2 | 0x06 | 0x00 + * BMA2x2_MODE_DEEP_SUSPEND | 3 | 0x01 | 0x00 + * BMA2x2_MODE_LOWPOWER2 | 4 | 0x02 | 0x01 + * BMA2x2_MODE_STANDBY | 5 | 0x04 | 0x00 + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_mode_value(u8 power_mode_u8); +/******************************************/ +/**\name FUNCTION FOR SLEEP CONFIGURATION */ +/******************************************/ +/*! + * @brief This API is used to get + * the sleep duration of the sensor in the register 0x11 + * Register 0x11 - bit from 0 to 3 + * + * + * + * + * @param sleep_durn_u8 : The value of sleep duration time + * sleep_durn_u8 | result + * ----------------- | ---------------------- + * 0x05 | BMA2x2_SLEEP_DURN_0_5MS + * 0x06 | BMA2x2_SLEEP_DURN_1MS + * 0x07 | BMA2x2_SLEEP_DURN_2MS + * 0x08 | BMA2x2_SLEEP_DURN_4MS + * 0x09 | BMA2x2_SLEEP_DURN_6MS + * 0x0A | BMA2x2_SLEEP_DURN_10MS + * 0x0B | BMA2x2_SLEEP_DURN_25MS + * 0x0C | BMA2x2_SLEEP_DURN_50MS + * 0x0D | BMA2x2_SLEEP_DURN_100MS + * 0x0E | BMA2x2_SLEEP_DURN_500MS + * 0x0F | BMA2x2_SLEEP_DURN_1S + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_sleep_durn(u8 *sleep_durn_u8); +/*! + * @brief This API is used to set + * the sleep duration of the sensor in the register 0x11 + * Register 0x11 - bit from 0 to 3 + * + * + * + * + * @param sleep_durn_u8 : The value of sleep duration time + * sleep_durn_u8 | result + * ----------------- | ---------------------- + * 0x05 | BMA2x2_SLEEP_DURN_0_5MS + * 0x06 | BMA2x2_SLEEP_DURN_1MS + * 0x07 | BMA2x2_SLEEP_DURN_2MS + * 0x08 | BMA2x2_SLEEP_DURN_4MS + * 0x09 | BMA2x2_SLEEP_DURN_6MS + * 0x0A | BMA2x2_SLEEP_DURN_10MS + * 0x0B | BMA2x2_SLEEP_DURN_25MS + * 0x0C | BMA2x2_SLEEP_DURN_50MS + * 0x0D | BMA2x2_SLEEP_DURN_100MS + * 0x0E | BMA2x2_SLEEP_DURN_500MS + * 0x0F | BMA2x2_SLEEP_DURN_1S + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_sleep_durn(u8 sleep_durn_u8); +/*! + * @brief This API is used to get the sleep timer mode + * in the register 0x12 bit 5 + * + * + * + * + * @param sleep_timer_u8 : The value of sleep timer mode + * sleep_timer_u8 | result + * ----------------- | ---------------------- + * 0 | enable EventDrivenSampling(EDT) + * 1 | enable Equidistant sampling mode(EST) + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_sleep_timer_mode( + u8 *sleep_timer_u8); +/*! + * @brief This API is used to set the sleep timer mode + * in the register 0x12 bit 5 + * + * + * + * + * @param sleep_timer_u8 : The value of sleep timer mode + * sleep_timer_u8 | result + * ----------------- | ---------------------- + * 0 | enable EventDrivenSampling(EDT) + * 1 | enable Equidistant sampling mode(EST) + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_sleep_timer_mode(u8 sleep_timer_u8); +/******************************************/ +/**\name FUNCTION FOR HIGH BANDWIDTH*/ +/******************************************/ +/*! + * @brief This API is used to get high bandwidth + * in the register 0x13 bit 7 + * + * @param high_bw_u8 : The value of high bandwidth + * high_bw_u8 | result + * ----------------- | ---------------------- + * 0 | Unfiltered High Bandwidth + * 1 | Filtered Low Bandwidth + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_high_bw(u8 *high_bw_u8); +/*! + * @brief This API is used to write high bandwidth + * in the register 0x13 bit 7 + * + * @param high_bw_u8 : The value of high bandwidth + * high_bw_u8 | result + * ----------------- | ---------------------- + * 0 | Unfiltered High Bandwidth + * 1 | Filtered Low Bandwidth + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_high_bw(u8 high_bw_u8); +/*! + * @brief This API is used to get shadow dis + * in the register 0x13 bit 6 + * + * @param shadow_dis_u8 : The value of shadow dis + * shadow_dis_u8 | result + * ----------------- | ------------------ + * 0 | MSB is Locked + * 1 | No MSB Locking + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_shadow_dis(u8 *shadow_dis_u8); +/*! + * @brief This API is used to set shadow dis + * in the register 0x13 bit 6 + * + * @param shadow_dis_u8 : The value of shadow dis + * shadow_dis_u8 | result + * ----------------- | ------------------ + * 0 | MSB is Locked + * 1 | No MSB Locking + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_shadow_dis(u8 shadow_dis_u8); +/******************************************/ +/**\name FUNCTION FOR SOFT RESET */ +/******************************************/ +/*! + * @brief This function is used for the soft reset + * The soft reset register will be written + * with 0xB6 in the register 0x14. + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_soft_rst(void); +/*! + * @brief This API is used to update the register values + * + * + * + * + * @param : None + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_update_image(void); +/******************************************/ +/**\name FUNCTION FOR INTERRUPT ENABLE */ +/******************************************/ +/*! + * @brief This API is used to get + * interrupt enable bits of the sensor in the registers 0x16 and 0x17 + * @note It reads the flat enable, orient enable, + * @note single tap enable, double tap enable + * @note slope-x enable, slope-y enable, slope-z enable, + * @note fifo watermark enable, + * @note fifo full enable, data enable, low-g enable, + * @note high-z enable, high-y enable + * @note high-z enable + * + * + * + * @param intr_type_u8: The value of interrupts + * intr_type_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_LOW_G_INTR + * 1 | BMA2x2_HIGH_G_X_INTR + * 2 | BMA2x2_HIGH_G_Y_INTR + * 3 | BMA2x2_HIGH_G_Z_INTR + * 4 | BMA2x2_DATA_ENABLE + * 5 | SLOPE_X_INTR + * 6 | SLOPE_Y_INTR + * 7 | SLOPE_Z_INTR + * 8 | SINGLE_TAP_INTR + * 9 | SINGLE_TAP_INTR + * 10 | ORIENT_INT + * 11 | FLAT_INT + * + * @param value_u8 : The value of interrupts enable + * value_u8 | result + * ----------------- | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_enable(u8 intr_type_u8, + u8 *value_u8); +/*! + * @brief This API is used to set + * interrupt enable bits of the sensor in the registers 0x16 and 0x17 + * @note It reads the flat enable, orient enable, + * @note single tap enable, double tap enable + * @note slope-x enable, slope-y enable, slope-z enable, + * @note fifo watermark enable, + * @note fifo full enable, data enable, low-g enable, + * @note high-z enable, high-y enable + * @note high-z enable + * + * + * + * @param intr_type_u8: The value of interrupts + * intr_type_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_LOW_G_INTR + * 1 | BMA2x2_HIGH_G_X_INTR + * 2 | BMA2x2_HIGH_G_Y_INTR + * 3 | BMA2x2_HIGH_G_Z_INTR + * 4 | BMA2x2_DATA_ENABLE + * 5 | SLOPE_X_INTR + * 6 | SLOPE_Y_INTR + * 7 | SLOPE_Z_INTR + * 8 | SINGLE_TAP_INTR + * 9 | SINGLE_TAP_INTR + * 10 | ORIENT_INT + * 11 | FLAT_INT + * + * @param value_u8 : The value of interrupts enable + * value_u8 | result + * ----------------- | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_enable(u8 intr_type_u8, + u8 value_u8); +/*! + * @brief This API is used to get + * the interrupt fifo full enable interrupt status + * in the register 0x17 bit 5 + * + * + * @param fifo_full_u8 The value of fifo full interrupt enable + * fifo_full_u8 | result + * ----------------- | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_fifo_full(u8 *fifo_full_u8); +/*! + * @brief This API is used to set + * the interrupt fifo full enable interrupt status + * in the register 0x17 bit 5 + * + * + * @param fifo_full_u8 The value of fifo full interrupt enable + * fifo_full_u8 | result + * ----------------- | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_fifo_full(u8 fifo_full_u8); +/*! + * @brief This API is used to get + * the interrupt fifo watermark enable interrupt status + * in the register 0x17 bit 6 + * + * + * + * + * @param fifo_wm_u8 : the value FIFO Water Mark + * fifo_wm_u8 | result + * ----------------- | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_fifo_wm(u8 *fifo_wm_u8); +/*! + * @brief This API is used to set + * the interrupt fifo watermark enable interrupt status + * in the register 0x17 bit 6 + * + * + * + * + * @param fifo_wm_u8 : the value FIFO Water Mark + * fifo_wm_u8 | result + * ----------------- | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_fifo_wm(u8 fifo_wm_u8); +/*! + * @brief This API is used to get + * the interrupt status of slow/no motion select and slow no motion + * enable xyz interrupt in the register 0x18 bit from 0 to 3 + * + * + * @param channel_u8 : The value of slow/no motion select + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_ACCEL_SLOW_NO_MOTION_ENABLE_X + * 1 | BMA2x2_ACCEL_SLOW_NO_MOTION_ENABLE_Y + * 2 | BMA2x2_ACCEL_SLOW_NO_MOTION_ENABLE_Z + * 3 | BMA2x2_ACCEL_SLOW_NO_MOTION_ENABLE_SEL + * + * @param slow_no_motion_u8 : The value of slow no motion interrupt + * enable + * slow_no_motion_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_slow_no_motion(u8 channel_u8, + u8 *slow_no_motion_u8); +/*! + * @brief This API is used to set + * the interrupt status of slow/no motion select and slow no motion + * enable xyz interrupt in the register 0x18 bit from 0 to 3 + * + * + * @param channel_u8 : The value of slow/no motion select + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_ACCEL_SLOW_NO_MOTION_ENABLE_X + * 1 | BMA2x2_ACCEL_SLOW_NO_MOTION_ENABLE_Y + * 2 | BMA2x2_ACCEL_SLOW_NO_MOTION_ENABLE_Z + * 3 | BMA2x2_ACCEL_SLOW_NO_MOTION_ENABLE_SEL + * + * @param slow_no_motion_u8 : The value of slow no motion interrupt enable + * slow_no_motion_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_slow_no_motion(u8 channel_u8, + u8 slow_no_motion_u8); +/*! + * @brief This API is used to get + * the interrupt enable of low_g interrupt in the register 0x19 and 0x1B + * @note INTR1_Low_g -> register 0x19 bit 0 + * @note INTR2_Low_g -> register 0x1B bit 0 + * + * + * + * + * @param channel_u8 : The value of low interrupt selection channel + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_ACCEL_INTR1_LOW_G + * 1 | BMA2x2_ACCEL_INTR2_LOW_G + * + * @param intr_low_g_u8 : the value of low_g interrupt + * intr_low_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_low_g(u8 channel_u8, + u8 *intr_low_g_u8); +/*! + * @brief This API is used to set + * the interrupt enable of low_g interrupt in the register 0x19 and 0x1B + * @note INTR1_Low_g -> register 0x19 bit 0 + * @note INTR2_Low_g -> register 0x1B bit 0 + * + * + * + * + * @param channel_u8 : The value of low interrupt selection channel + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_ACCEL_INTR1_LOW_G + * 1 | BMA2x2_ACCEL_INTR2_LOW_G + * + * @param intr_low_u8 : the value of low_g interrupt + * intr_low_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_low_g(u8 channel_u8, + u8 intr_low_u8); +/*! + * @brief This API is used to get + * the interrupt enable of high_g interrupt in the register 0x19 and 0x1B + * @note INTR1_high_g -> register 0x19 bit 1 + * @note INTR2_high_g -> register 0x1B bit 1 + * + * + * @param channel_u8: The value of high_g interrupt selection + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_ACCEL_INTR1_HIGH_G + * 1 | BMA2x2_ACCEL_INTR2_HIGH_G + * + * @param intr_high_g_u8 : the value of high_g interrupt + * intr_high_g_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_high_g(u8 channel_u8, + u8 *intr_high_g_u8); +/*! + * @brief This API is used to set + * the interrupt enable of high_g interrupt in the register 0x19 and 0x1B + * @note INTR1_high_g -> register 0x19 bit 1 + * @note INTR2_high_g -> register 0x1B bit 1 + * + * + * @param channel_u8: The value of high_g interrupt selection + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_ACCEL_INTR1_HIGH_G + * 1 | BMA2x2_ACCEL_INTR2_HIGH_G + * + * @param intr_high_g_u8 : the value of high_g interrupt + * intr_high_g_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_high_g(u8 channel_u8, + u8 intr_high_g_u8); +/*! + * @brief This API is used to get + * the interrupt enable of slope interrupt in the register 0x19 and 0x1B + * @note INTR1_slope -> register 0x19 bit 2 + * @note INTR2_slope -> register 0x1B bit 2 + * + * + * + * @param channel_u8: the value of slope channel select + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_ACCEL_INTR1_SLOPE + * 1 | BMA2x2_ACCEL_INTR2_SLOPE + * + * @param intr_slope_u8 : The slope value enable value + * intr_slope_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_slope(u8 channel_u8, + u8 *intr_slope_u8); +/*! + * @brief This API is used to set + * the interrupt enable of slope interrupt in the register 0x19 and 0x1B + * @note INTR1_slope -> register 0x19 bit 2 + * @note INTR2_slope -> register 0x1B bit 2 + * + * + * + * @param channel_u8: the value of slope channel select + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_ACCEL_INTR1_SLOPE + * 1 | BMA2x2_ACCEL_INTR2_SLOPE + * + * @param intr_slope_u8 : The slope value enable value + * intr_slope_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_slope(u8 channel_u8, + u8 intr_slope_u8); +/*! + * @brief This API is used to get + * the interrupt enable of slow/no motion interrupt in + * the register 0x19 and 0x1B + * @note INTR1_slow_no_motion -> register 0x19 bit 3 + * @note INTR2_slow_no_motion -> register 0x1B bit 3 + * + * + * + * + * @param channel_u8 : The value of slow/no motion selection + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_INTR1_SLOW_NO_MOTION + * 1 | BMA2x2_INTR2_SLOW_NO_MOTION + * + * @param intr_slow_no_motion_u8: the slow_no_motion enable value + * intr_slow_no_motion_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_slow_no_motion(u8 channel_u8, + u8 *intr_slow_no_motion_u8); +/*! + * @brief This API is used to set + * the interrupt enable of slow/no motion interrupt in + * the register 0x19 and 0x1B + * @note INTR1_slow_no_motion -> register 0x19 bit 3 + * @note INTR2_slow_no_motion -> register 0x1B bit 3 + * + * + * + * + * @param channel_u8 : The value of slow/no motion selection + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_INTR1_SLOW_NO_MOTION + * 1 | BMA2x2_INTR2_SLOW_NO_MOTION + * + * @param intr_slow_no_motion_u8: the slow_no_motion enable value + * intr_slow_no_motion_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_slow_no_motion(u8 channel_u8, + u8 intr_slow_no_motion_u8); +/*! + * @brief This API is used to get + * the interrupt enable of double tap interrupt + * in the register 0x19 and 0x1B + * @note INTR1_double -> register 0x19 bit 4 + * @note INTR2_double -> register 0x1B bit 4 + * + * + * + * + * @param channel_u8: The value of double tap selection + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_ACCEL_INTR1_DOUBLE_TAP + * 1 | BMA2x2_ACCEL_INTR2_DOUBLE_TAP + * + * @param intr_double_tap_u8: The double tap interrupt enable value + * intr_double_tap_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_double_tap(u8 channel_u8, + u8 *intr_double_tap_u8); +/*! + * @brief This API is used to set + * the interrupt enable of double tap interrupt + * in the register 0x19 and 0x1B + * @note INTR1_double -> register 0x19 bit 4 + * @note INTR2_double -> register 0x1B bit 4 + * + * + * + * + * @param channel_u8: The value of double tap selection + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_ACCEL_INTR1_DOUBLE_TAP + * 1 | BMA2x2_ACCEL_INTR2_DOUBLE_TAP + * + * @param intr_double_tap_u8: The double tap interrupt enable value + * intr_double_tap_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_double_tap(u8 channel_u8, + u8 intr_double_tap_u8); +/*! + * @brief This API is used to get + * the interrupt enable of single tap + * interrupt in the register 0x19 and 0x1B + * @note INTR1_single_tap -> register 0x19 bit 5 + * @note INTR2_single_tap -> register 0x1B bit 5 + * + * + * @param channel_u8: The value of single tap interrupt select + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_ACCEL_INTR1_SINGLE_TAP + * 1 | BMA2x2_ACCEL_INTR2_SINGLE_TAP + * + * @param intr_single_tap_u8: The single tap interrupt enable value + * intr_single_tap_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_single_tap(u8 channel_u8, + u8 *intr_single_tap_u8); +/*! + * @brief This API is used to set + * the interrupt enable of single tap + * interrupt in the register 0x19 and 0x1B + * @note INTR1_single_tap -> register 0x19 bit 5 + * @note INTR2_single_tap -> register 0x1B bit 5 + * + * + * @param channel_u8: The value of single tap interrupt select + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_ACCEL_INTR1_SINGLE_TAP + * 1 | BMA2x2_ACCEL_INTR2_SINGLE_TAP + * + * @param intr_single_tap_u8: The single tap interrupt enable value + * intr_single_tap_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_single_tap(u8 channel_u8, + u8 intr_single_tap_u8); +/*! + * @brief This API is used to get + * the interrupt status of orient interrupt in the register 0x19 and 0x1B + * @note INTR1_orient -> register 0x19 bit 6 + * @note INTR2_orient -> register 0x1B bit 6 + * + * + * @param channel_u8: The value of orient interrupt select + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_ACCEL_INTR1_ORIENT + * 1 | BMA2x2_ACCEL_INTR2_ORIENT + * + * @param intr_orient_u8: The value of orient interrupt enable + * intr_orient_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_orient(u8 channel_u8, + u8 *intr_orient_u8); +/*! + * @brief This API is used to set + * the interrupt status of orient interrupt in the register 0x19 and 0x1B + * @note INTR1_orient -> register 0x19 bit 6 + * @note INTR2_orient -> register 0x1B bit 6 + * + * + * @param channel_u8: The value of orient interrupt select + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_ACCEL_INTR1_ORIENT + * 1 | BMA2x2_ACCEL_INTR2_ORIENT + * + * @param intr_orient_u8: The value of orient interrupt enable + * intr_orient_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_orient(u8 channel_u8, + u8 intr_orient_u8); +/*! + * @brief This API is used to get + * the interrupt enable of flat interrupt in the register 0x19 and 0x1B + * @note INTR1_flat -> register 0x19 bit 7 + * @note INTR2_flat -> register 0x1B bit 7 + * + * + * + * + * @param channel_u8: The value of flat interrupt select + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_ACCEL_INTR1_FLAT + * 1 | BMA2x2_ACCEL_INTR2_FLAT + * + * @param intr_flat_u8: The flat interrupt enable value + * intr_flat_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_flat(u8 channel_u8, + u8 *intr_flat_u8); +/*! + * @brief This API is used to set + * the interrupt enable of flat interrupt in the register 0x19 and 0x1B + * @note INTR1_flat -> register 0x19 bit 7 + * @note INTR2_flat -> register 0x1B bit 7 + * + * + * + * + * @param channel_u8: The value of flat interrupt select + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_ACCEL_INTR1_FLAT + * 1 | BMA2x2_ACCEL_INTR2_FLAT + * + * @param intr_flat_u8: The flat interrupt enable value + * intr_flat_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_flat(u8 channel_u8, + u8 intr_flat_u8); +/*! + * @brief This API is used to get + * the interrupt status of new data in the register 0x19 + * @note INTR1_data -> register 0x19 bit 0 + * @note INTR2_data -> register 0x19 bit 7 + * + * + * + * @param channel_u8: The value of new data interrupt select + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_ACCEL_INTR1_NEWDATA + * 1 | BMA2x2_ACCEL_INTR2_NEWDATA + * + * @param intr_newdata_u8: The new data interrupt enable value + * intr_newdata_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_new_data(u8 channel_u8, + u8 *intr_newdata_u8); +/*! + * @brief This API is used to set + * the interrupt status of new data in the register 0x19 + * @note INTR1_data -> register 0x19 bit 0 + * @note INTR2_data -> register 0x19 bit 7 + * + * + * + * @param channel_u8: The value of new data interrupt select + * channel_u8 | result + * ----------------- | ------------------ + * 0 | BMA2x2_ACCEL_INTR1_NEWDATA + * 1 | BMA2x2_ACCEL_INTR2_NEWDATA + * + * @param intr_newdata_u8: The new data interrupt enable value + * intr_newdata_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_new_data(u8 channel_u8, + u8 intr_newdata_u8); +/******************************************/ +/**\name FUNCTION FOR FIFO INTERRUPT ENABLE*/ +/******************************************/ +/*! + * @brief This API is used to get the fifo watermark interrupt1 data + * in the register 0x1A bit 1 + * + * @param intr1_fifo_wm_u8 : The value of interrupt1 FIFO watermark enable + * intr1_fifo_wm_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr1_fifo_wm(u8 *intr1_fifo_wm_u8); +/*! + * @brief This API is used to set the fifo watermark interrupt1 data + * in the register 0x1A bit 1 + * + * @param intr1_fifo_wm_u8 : The value of interrupt1 FIFO watermark enable + * intr1_fifo_wm_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr1_fifo_wm(u8 intr1_fifo_wm_u8); +/*! + * @brief This API is used to get the fifo watermark interrupt2 data + * in the register 0x1A bit 6 + * + * @param intr2_fifo_wm_u8 : The value of interrupt1 FIFO watermark enable + * intr2_fifo_wm_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr2_fifo_wm(u8 *intr2_fifo_wm_u8); +/*! + * @brief This API is used to set the fifo watermark interrupt2 data + * in the register 0x1A bit 6 + * + * @param intr2_fifo_wm_u8 : The value of interrupt1 FIFO watermark enable + * intr2_fifo_wm_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr2_fifo_wm(u8 intr2_fifo_wm_u8); +/*! + * @brief This API is used to get + * the fifo full interrupt1 in the register 0x1A bit 2 + * + * + * + * @param intr1_fifo_full_u8 : The value of fifo full interrupt enable + * intr1_fifo_full_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr1_fifo_full( + u8 *intr1_fifo_full_u8); +/*! + * @brief This API is used to set + * the fifo full interrupt1 in the register 0x1A bit 2 + * + * + * + * @param intr1_fifo_full_u8 : The value of fifo full interrupt enable + * intr1_fifo_full_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr1_fifo_full(u8 intr1_fifo_full_u8); +/*! + * @brief This API is used to get + * the fifo full interrupt2 in the register 0x1A bit 5 + * + * + * + * @param intr2_fifo_full_u8 : Thee vale of fifo full enable + * intr2_fifo_full_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr2_fifo_full( + u8 *intr2_fifo_full_u8); +/*! + * @brief This API is used to set + * the fifo full interrupt2 in the register 0x1A bit 5 + * + * + * + * @param intr2_fifo_full_u8 : Thee vale of fifo full enable + * intr2_fifo_full_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr2_fifo_full(u8 intr2_fifo_full_u8); +/******************************************/ +/**\name FUNCTION FOR SOURCE CONFIGURATION */ +/******************************************/ +/*! + * @brief This API is used to get + * the source data status of source data, + * source slow no motion, source slope, source high + * and source low in the register 0x1E bit from 0 to 5 + * + * + * + * @param channel_u8 : The value of source select + * channel_u8 | result + * -----------------| ------------------ + * 0 | BMA2x2_ACCEL_SOURCE_LOW_G + * 1 | BMA2x2_ACCEL_SOURCE_HIGH_G + * 2 | BMA2x2_ACCEL_SOURCE_SLOPE + * 3 | BMA2x2_ACCEL_SOURCE_SLOW_NO_MOTION + * 4 | BMA2x2_ACCEL_SOURCE_TAP + * 5 | BMA2x2_ACCEL_SOURCE_DATA + * + * @param intr_source_u8: The source status enable value + * intr_source_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_source(u8 channel_u8, + u8 *intr_source_u8); +/*! + * @brief This API is used to set + * the source data status of source data, + * source slow no motion, source slope, source high + * and source low in the register 0x1E bit from 0 to 5 + * + * + * + * @param channel_u8 : The value of source select + * channel_u8 | result + * -----------------| ------------------ + * 0 | BMA2x2_ACCEL_SOURCE_LOW_G + * 1 | BMA2x2_ACCEL_SOURCE_HIGH_G + * 2 | BMA2x2_ACCEL_SOURCE_SLOPE + * 3 | BMA2x2_ACCEL_SOURCE_SLOW_NO_MOTION + * 4 | BMA2x2_ACCEL_SOURCE_TAP + * 5 | BMA2x2_ACCEL_SOURCE_DATA + * + * @param intr_source_u8: The source status enable value + * intr_source_u8 | result + * ------------------------ | ------------------ + * 0x00 | INTR_DISABLE + * 0x01 | INTR_ENABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_source(u8 channel_u8, + u8 intr_source_u8); +/******************************************/ +/**\name FUNCTION FOR OUTPUT TYPE AND LEVEL*/ +/******************************************/ +/*! + * @brief This API is used to get + * the interrupt output type in the register 0x20. + * @note INTR1 -> bit 1 + * @note INTR2 -> bit 3 + * + * @param channel_u8: The value of output type select + * channel_u8 | result + * -----------------| ------------------ + * 0 | BMA2x2_ACCEL_INTR1_OUTPUT + * 1 | BMA2x2_ACCEL_INTR2_OUTPUT + * + * @param intr_output_type_u8: The value of output type select + * intr_source_u8 | result + * ------------------------ | ------------------ + * 0x01 | OPEN_DRAIN + * 0x00 | PUSS_PULL + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_output_type(u8 channel_u8, + u8 *intr_output_type_u8); +/*! + * @brief This API is used to set + * the interrupt output type in the register 0x20. + * @note INTR1 -> bit 1 + * @note INTR2 -> bit 3 + * + * @param channel_u8: The value of output type select + * channel_u8 | result + * -----------------| ------------------ + * 0 | BMA2x2_ACCEL_INTR1_OUTPUT + * 1 | BMA2x2_ACCEL_INTR2_OUTPUT + * + * @param intr_output_type_u8: The value of output type select + * intr_source_u8 | result + * ------------------------ | ------------------ + * 0x01 | OPEN_DRAIN + * 0x00 | PUSS_PULL + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_output_type(u8 channel_u8, + u8 intr_output_type_u8); +/*! + * @brief This API is used to get + * Active Level status in the register 0x20 + * @note INTR1 -> bit 0 + * @note INTR2 -> bit 2 + * + * @param channel_u8: The value of Active Level select + * channel_u8 | result + * -----------------| ------------------ + * 0 | BMA2x2_ACCEL_INTR1_LEVEL + * 1 | BMA2x2_ACCEL_INTR2_LEVEL + * + * @param intr_level_u8: The Active Level status enable value + * intr_level_u8 | result + * ------------------------ | ------------------ + * 0x01 | ACTIVE_HIGH + * 0x00 | ACTIVE_LOW + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_level(u8 channel_u8, + u8 *intr_level_u8); +/*! + * @brief This API is used to set + * Active Level status in the register 0x20 + * @note INTR1 -> bit 0 + * @note INTR2 -> bit 2 + * + * @param channel_u8: The value of Active Level select + * channel_u8 | result + * -----------------| ------------------ + * 0 | BMA2x2_ACCEL_INTR1_LEVEL + * 1 | BMA2x2_ACCEL_INTR2_LEVEL + * + * @param intr_level_u8: The Active Level status enable value + * intr_level_u8 | result + * ------------------------ | ------------------ + * 0x01 | ACTIVE_HIGH + * 0x00 | ACTIVE_LOW + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_level(u8 channel_u8, + u8 intr_level_u8); +/******************************************/ +/**\name FUNCTION FOR RESET INTERRUPT*/ +/******************************************/ +/*! + * @brief This API is used to set + * the reset interrupt in the register 0x21 bit 7 + * + * + * + * @param rst_intr_u8: The value of reset interrupt + * rst_intr_u8 | result + * ------------------------ | ------------------ + * 0x01 | clear any latch interrupt + * 0x00 | keep latch interrupt active + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_rst_intr(u8 rst_intr_u8); +/******************************************/ +/**\name FUNCTION FOR LATCH INTERRUPT INTERRUPT*/ +/******************************************/ +/*! + * @brief This API is used to get + * the latch duration in the register 0x21 bit from 0 to 3 + * + * @param latch_intr_u8: The value of latch duration + * latch_intr_u8 | result + * -----------------| ------------------ + * 0x00 | BMA2x2_LATCH_DURN_NON_LATCH + * 0x01 | BMA2x2_LATCH_DURN_250MS + * 0x02 | BMA2x2_LATCH_DURN_500MS + * 0x03 | BMA2x2_LATCH_DURN_1S + * 0x04 | BMA2x2_LATCH_DURN_2S + * 0x05 | BMA2x2_LATCH_DURN_4S + * 0x06 | BMA2x2_LATCH_DURN_8S + * 0x07 | BMA2x2_LATCH_DURN_LATCH + * 0x08 | BMA2x2_LATCH_DURN_NON_LATCH1 + * 0x09 | BMA2x2_LATCH_DURN_250US + * 0x0A | BMA2x2_LATCH_DURN_500US + * 0x0B | BMA2x2_LATCH_DURN_1MS + * 0x0C | BMA2x2_LATCH_DURN_12_5MS + * 0x0D | BMA2x2_LATCH_DURN_25MS + * 0x0E | BMA2x2_LATCH_DURN_50MS + * 0x0F | BMA2x2_LATCH_DURN_LATCH1 + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_latch_intr(u8 *latch_intr_u8); +/*! + * @brief This API is used to set + * the latch duration in the register 0x21 bit from 0 to 3 + * + * @param latch_intr_u8: The value of latch duration + * latch_intr_u8 | result + * -----------------| ------------------ + * 0x00 | BMA2x2_LATCH_DURN_NON_LATCH + * 0x01 | BMA2x2_LATCH_DURN_250MS + * 0x02 | BMA2x2_LATCH_DURN_500MS + * 0x03 | BMA2x2_LATCH_DURN_1S + * 0x04 | BMA2x2_LATCH_DURN_2S + * 0x05 | BMA2x2_LATCH_DURN_4S + * 0x06 | BMA2x2_LATCH_DURN_8S + * 0x07 | BMA2x2_LATCH_DURN_LATCH + * 0x08 | BMA2x2_LATCH_DURN_NON_LATCH1 + * 0x09 | BMA2x2_LATCH_DURN_250US + * 0x0A | BMA2x2_LATCH_DURN_500US + * 0x0B | BMA2x2_LATCH_DURN_1MS + * 0x0C | BMA2x2_LATCH_DURN_12_5MS + * 0x0D | BMA2x2_LATCH_DURN_25MS + * 0x0E | BMA2x2_LATCH_DURN_50MS + * 0x0F | BMA2x2_LATCH_DURN_LATCH1 + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_latch_intr(u8 latch_intr_u8); +/******************************************/ +/**\name FUNCTION FOR INTERRUPT DURATION CONFIGURATION*/ +/******************************************/ +/*! + * @brief This API is used to get the duration of + * Low, High, Slope and slow no motion interrupts in the registers + * @note LOW_DURN -> register 0x22 bit form 0 to 7 + * @note HIGH_DURN -> register 0x25 bit form 0 to 7 + * @note SLOPE_DURN -> register 0x27 bit form 0 to 1 + * @note SLO_NO_MOT_DURN -> register 0x27 bit form 2 to 7 + * + * @param channel_u8: The value of duration select + * channel_u8 | result + * -----------------| ------------------ + * 0 | BMA2x2_ACCEL_LOW_DURN + * 1 | BMA2x2_ACCEL_HIGH_DURN + * 2 | BMA2x2_ACCEL_SLOPE_DURN + * 3 | BMA2x2_ACCEL_SLOW_NO_MOTION_DURN + * + * @param durn_u8: The value of duration + * + * @note : + * Duration | result + * -----------------------| ------------------ + * BMA2x2_ACCEL_LOW_DURN | Low-g interrupt trigger + * - | delay according to([durn_u8 +1]*2)ms + * - | range from 2ms to 512ms. default is 20ms + * BMA2x2_ACCEL_HIGH_DURN | high-g interrupt trigger + * - | delay according to([durn_u8 +1]*2)ms + * - | range from 2ms to 512ms. default is 32ms + * BMA2x2_ACCEL_SLOPE_DURN| slope interrupt trigger + * - | if[durn_u8<1:0>+1] consecutive data points + * - | are above the slope interrupt threshold + * SLO_NO_MOT_DURN | Refer data sheet for clear information + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_durn(u8 channel_u8, + u8 *durn_u8); +/*! + * @brief This API is used to set the duration of + * Low, High, Slope and slow no motion interrupts in the registers + * @note LOW_DURN -> register 0x22 bit form 0 to 7 + * @note HIGH_DURN -> register 0x25 bit form 0 to 7 + * @note SLOPE_DURN -> register 0x27 bit form 0 to 1 + * @note SLO_NO_MOT_DURN -> register 0x27 bit form 2 to 7 + * + * @param channel_u8: The value of duration select + * channel_u8 | result + * -----------------| ------------------ + * 0 | BMA2x2_ACCEL_LOW_DURN + * 1 | BMA2x2_ACCEL_HIGH_DURN + * 2 | BMA2x2_ACCEL_SLOPE_DURN + * 3 | BMA2x2_ACCEL_SLOW_NO_MOTION_DURN + * + * @param durn_u8: The value of duration + * + * @note : + * Duration | result + * -----------------------| ------------------ + * BMA2x2_ACCEL_LOW_DURN | Low-g interrupt trigger + * - | delay according to([durn_u8 +1]*2)ms + * - | range from 2ms to 512ms. default is 20ms + * BMA2x2_ACCEL_HIGH_DURN | high-g interrupt trigger + * - | delay according to([durn_u8 +1]*2)ms + * - | range from 2ms to 512ms. default is 32ms + * BMA2x2_ACCEL_SLOPE_DURN| slope interrupt trigger + * - | if[durn_u8<1:0>+1] consecutive data points + * - | are above the slope interrupt threshold + * SLO_NO_MOT_DURN | Refer data sheet for clear information + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_durn(u8 channel_u8, + u8 durn_u8); +/******************************************/ +/**\name FUNCTION FOR INTERRUPT THRESHOLD CONFIGURATION */ +/******************************************/ +/*! + * @brief This API is used to get the threshold of + * Low, High, Slope and slow no motion interrupts in the registers + * @note LOW_THRES -> register 0x23 bit form 0 to 7 + * @note HIGH_THRES -> register 0x26 bit form 0 to 7 + * @note SLOPE_THRES -> register 0x28 bit form 0 to 7 + * @note SLO_NO_MOT_THRES -> register 0x29 bit form 0 to 7 + * + * @param channel_u8: The value of threshold selection + * channel_u8 | result + * -----------------| ------------------ + * 0 | BMA2x2_ACCEL_LOW_THRES + * 1 | BMA2x2_ACCEL_HIGH_THRES + * 2 | BMA2x2_ACCEL_SLOPE_THRES + * 3 | BMA2x2_ACCEL_SLOW_NO_MOTION_THRES + * + * @param thres_u8: The threshold value of selected interrupts + * + * @note : LOW-G THRESHOLD + * Threshold | result + * ---------------------------------| ------------------ + * BMA2x2_ACCEL_LOW_THRES | Low-threshold interrupt trigger + * | according to(thres_u8 * 7.81) mg + * | range from 0g to 1.992g + * | default is 375mg + * @note : HIGH-G THRESHOLD + * @note Threshold of high-g interrupt according to accel g range + * g-range | High-g threshold + * --------------------|---------------------------- + * 2g | (thres_u8 * 7.81) mg + * 4g | (thres_u8 * 15.63) mg + * 8g | (thres_u8 * 31.25) mg + * 16g | (thres_u8 * 62.5) mg + * + * @note : SLOPE THRESHOLD + * @note Threshold of slope interrupt according to accel g range + * g-range | Slope threshold + * --------------------|---------------------------- + * 2g | (thres_u8 * 3.19) mg + * 4g | (thres_u8 * 7.81) mg + * 8g | (thres_u8 * 15.63) mg + * 16g | (thres_u8 * 31.25) mg + * + * @note : SLOW NO MOTION THRESHOLD + * @note Threshold of slow no motion interrupt according to accel g range + * g-range | slow no motion threshold + * --------------------|---------------------------- + * 2g | (thres_u8 * 3.19) mg + * 4g | (thres_u8 * 7.81) mg + * 8g | (thres_u8 * 15.63) mg + * 16g | (thres_u8 * 31.25) mg + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_thres(u8 channel_u8, + u8 *thres_u8); +/*! + * @brief This API is used to set the threshold of + * Low, High, Slope and slow no motion interrupts in the registers + * @note LOW_THRES -> register 0x23 bit form 0 to 7 + * @note HIGH_THRES -> register 0x26 bit form 0 to 7 + * @note SLOPE_THRES -> register 0x28 bit form 0 to 7 + * @note SLO_NO_MOT_THRES -> register 0x29 bit form 0 to 7 + * + * @param channel_u8: The value of threshold selection + * channel_u8 | result + * -----------------| ------------------ + * 0 | BMA2x2_ACCEL_LOW_THRES + * 1 | BMA2x2_ACCEL_HIGH_THRES + * 2 | BMA2x2_ACCEL_SLOPE_THRES + * 3 | BMA2x2_ACCEL_SLOW_NO_MOTION_THRES + * + * @param thres_u8: The threshold value of selected interrupts + * + * @note : LOW-G THRESHOLD + * Threshold | result + * ---------------------------------| ------------------ + * BMA2x2_ACCEL_LOW_THRES | Low-threshold interrupt trigger + * | according to(thres_u8 * 7.81) mg + * | range from 0g to 1.992g + * | default is 375mg + * @note : HIGH-G THRESHOLD + * @note Threshold of high-g interrupt according to accel g range + * g-range | High-g threshold + * --------------------|---------------------------- + * 2g | (thres_u8 * 7.81) mg + * 4g | (thres_u8 * 15.63) mg + * 8g | (thres_u8 * 31.25) mg + * 16g | (thres_u8 * 62.5) mg + * + * @note : SLOPE THRESHOLD + * @note Threshold of slope interrupt according to accel g range + * g-range | Slope threshold + * --------------------|---------------------------- + * 2g | (thres_u8 * 3.19) mg + * 4g | (thres_u8 * 7.81) mg + * 8g | (thres_u8 * 15.63) mg + * 16g | (thres_u8 * 31.25) mg + * + * @note : SLOW NO MOTION THRESHOLD + * @note Threshold of slow no motion interrupt according to accel g range + * g-range | slow no motion threshold + * --------------------|---------------------------- + * 2g | (thres_u8 * 3.19) mg + * 4g | (thres_u8 * 7.81) mg + * 8g | (thres_u8 * 15.63) mg + * 16g | (thres_u8 * 31.25) mg + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_thres(u8 channel_u8, + u8 thres_u8); +/******************************************/ +/**\name FUNCTION FOR INTERRUPT HYSTERESIS */ +/******************************************/ +/*! + * @brief This API is used to get + * the low high hysteresis in the registers 0x24 + * @note LOW_G_HYST -> bit form 0 to 1 + * @note HIGH_G_HYST -> bit from 6 to 7 + * + * @param channel_u8: The value of hysteresis selection + * channel_u8 | result + * -----------------| ------------------ + * 0 | BMA2x2_ACCEL_LOW_G_HYST + * 1 | BMA2x2_ACCEL_HIGH_G_HYST + * + * @param hyst_u8: The hysteresis data + * + * @note LOW HYSTERESIS + * @note Hysteresis of low-g interrupt according to (hyst_u8 * 125)mg + * + * @note HIGH HYSTERESIS + * @note High hysteresis depends on the accel range selection + * g-range | High Hysteresis + * --------------------|---------------------------- + * 2g | (thres_u8 * 125) mg + * 4g | (thres_u8 * 250) mg + * 8g | (thres_u8 * 500) mg + * 16g | (thres_u8 * 1000) mg + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_low_high_g_hyst(u8 channel_u8, + u8 *hyst_u8); +/*! + * @brief This API is used to set + * the low high hysteresis in the registers 0x24 + * @note LOW_G_HYST -> bit form 0 to 1 + * @note HIGH_G_HYST -> bit from 6 to 7 + * + * @param channel_u8: The value of hysteresis selection + * channel_u8 | result + * -----------------| ------------------ + * 0 | BMA2x2_ACCEL_LOW_G_HYST + * 1 | BMA2x2_ACCEL_HIGH_G_HYST + * + * @param hyst_u8: The hysteresis data + * + * @note LOW HYSTERESIS + * @note Hysteresis of low-g interrupt according to (hyst_u8 * 125)mg + * + * @note HIGH HYSTERESIS + * @note High hysteresis depends on the accel range selection + * g-range | High Hysteresis + * --------------------|---------------------------- + * 2g | (thres_u8 * 125) mg + * 4g | (thres_u8 * 250) mg + * 8g | (thres_u8 * 500) mg + * 16g | (thres_u8 * 1000) mg + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_low_high_g_hyst(u8 channel_u8, + u8 hyst_u8); +/******************************************/ +/**\name FUNCTION FOR LOW_G MODE */ +/******************************************/ +/*! + * @brief This API is used to get + * low_g mode in the registers 0x24 bit 2 + * + * + * @param low_g_mode_u8: The value of Low_G mode + * low_g_mode_u8 | g-result + * --------------------|---------------------------- + * 0x00 | LOW_G_SINGLE_AXIS_MODE + * 0x01 | LOW_G_SUMMING_MODE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_low_g_mode(u8 *low_g_mode_u8); +/*! + * @brief This API is used to set + * low_g mode in the registers 0x24 bit 2 + * + * + * @param low_g_mode_u8: The value of Low_G mode + * low_g_mode_u8 | result + * --------------------|---------------------------- + * 0x00 | LOW_G_SINGLE_AXIS_MODE + * 0x01 | LOW_G_SUMMING_MODE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_low_g_mode(u8 low_g_mode_u8); +/******************************************/ +/**\name FUNCTION FOR TAP DURATION */ +/******************************************/ +/*! + * @brief This API is used to get + * the tap duration in the register 0x2A bit form 0 to 2 + * + * + * @param tap_durn_u8: The value of tap duration + * tap_durn_u8 | result + * --------------------|---------------------------- + * 0x00 | TAP_DURN_50_MS + * 0x01 | TAP_DURN_100_MS + * 0x02 | TAP_DURN_150_MS + * 0x03 | TAP_DURN_200_MS + * 0x04 | TAP_DURN_250_MS + * 0x05 | TAP_DURN_375_MS + * 0x06 | TAP_DURN_500_MS + * 0x07 | TAP_DURN_700_MS + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_tap_durn(u8 *tap_durn_u8); +/*! + * @brief This API is used to set + * the tap duration in the register 0x2A bit form 0 to 2 + * + * + * @param tap_durn_u8: The value of tap duration + * tap_durn_u8 | result + * --------------------|---------------------------- + * 0x00 | TAP_DURN_50_MS + * 0x01 | TAP_DURN_100_MS + * 0x02 | TAP_DURN_150_MS + * 0x03 | TAP_DURN_200_MS + * 0x04 | TAP_DURN_250_MS + * 0x05 | TAP_DURN_375_MS + * 0x06 | TAP_DURN_500_MS + * 0x07 | TAP_DURN_700_MS + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_tap_durn(u8 tap_durn_u8); +/******************************************/ +/**\name FUNCTION FOR TAP SHOCK */ +/******************************************/ +/*! + * @brief This API is used to get + * the tap shock form the register 0x2A bit 6 + * + * + * + * @param tap_shock_u8: The value of tap shock + * tap_shock_u8 | result + * --------------------|---------------------- + * 0x00 | TAP_SHOCK_50_MS + * 0x01 | TAP_SHOCK_75_MS + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_tap_shock(u8 *tap_shock_u8); +/*! + * @brief This API is used to set + * the tap shock form the register 0x2A bit 6 + * + * + * + * @param tap_shock_u8: The value of tap shock + * tap_shock_u8 | result + * --------------------|---------------------- + * 0x00 | TAP_SHOCK_50_MS + * 0x01 | TAP_SHOCK_75_MS + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_tap_shock(u8 tap_shock_u8); +/******************************************/ +/**\name FUNCTION FOR TAP QUIET */ +/******************************************/ +/*! + * @brief This API is used to get + * the tap quiet in the register 0x2A bit 7 + * + * + * + * @param tap_quiet_u8 : The value of tap quiet + * tap_quiet_u8 | result + * --------------------|---------------------- + * 0x00 | TAP_QUIET_30_MS + * 0x01 | TAP_QUIET_20_MS + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_tap_quiet(u8 *tap_quiet_u8); +/*! + * @brief This API is used to set + * the tap quiet in the register 0x2A bit 7 + * + * + * + * @param tap_quiet_u8 : The value of tap quiet + * tap_quiet_u8 | result + * --------------------|---------------------- + * 0x00 | TAP_QUIET_30_MS + * 0x01 | TAP_QUIET_20_MS + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_tap_quiet(u8 tap_quiet_u8); +/******************************************/ +/**\name FUNCTION FOR TAP THRESHOLD */ +/******************************************/ +/*! + * @brief This API is used to get + * the tap threshold in the register 0x2B bit from 0 to 4 + * + * + * + * @param tap_thres_u8 : The value of tap threshold + * @note Tap threshold of single and double tap corresponding + * to accel range + * range | Tap threshold + * --------------------|---------------------- + * 2g | (tap_thres_u8 * 62.5)mg + * 4g | (tap_thres_u8 * 125)mg + * 8g | (tap_thres_u8 * 250)mg + * 16g | (tap_thres_u8 * 500)mg + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_tap_thres(u8 *tap_thres_u8); +/*! + * @brief This API is used to set + * the tap threshold in the register 0x2B bit from 0 to 4 + * + * + * + * @param tap_thres_u8 : The value of tap threshold + * @note Tap threshold of single and double tap corresponding + * to accel range + * range | Tap threshold + * --------------------|---------------------- + * 2g | (tap_thres_u8 * 62.5)mg + * 4g | (tap_thres_u8 * 125)mg + * 8g | (tap_thres_u8 * 250)mg + * 16g | (tap_thres_u8 * 500)mg + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_tap_thres(u8 tap_thres_u8); +/******************************************/ +/**\name FUNCTION FOR TAP SAMPLES */ +/******************************************/ +/*! + * @brief This API is used to get + * the tap sample in the register 0x2B bit 6 and 7 + * + * + * + * @param *tap_sample_u8 : The value of tap sample + * tap_sample_u8 | result + * --------------------|---------------------- + * 0x00 | 2 samples + * 0x01 | 4 samples + * 0x02 | 8 samples + * 0x03 | 16 samples + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_tap_sample(u8 *tap_sample_u8); +/*! + * @brief This API is used to set + * the tap sample in the register 0x2B bit 6 and 7 + * + * + * + * @param *tap_sample_u8 : The value of tap sample + * tap_sample_u8 | result + * --------------------|---------------------- + * 0x00 | 2 samples + * 0x01 | 4 samples + * 0x02 | 8 samples + * 0x03 | 16 samples + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_tap_sample(u8 tap_sample_u8); +/******************************************/ +/**\name FUNCTION FOR ORIENT MODE */ +/******************************************/ +/*! + * @brief This API is used to get + * the orient mode in the register 0x2C bit 0 and 1 + * + * + * + * @param orient_mode_u8 : The value of orient mode + * orient_mode_u8 | result + * --------------------|------------------ + * 0x00 | symmetrical + * 0x01 | high asymmetrical + * 0x02 | low asymmetrical + * 0x03 | symmetrical + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_orient_mode(u8 *orient_mode_u8); +/*! + * @brief This API is used to set + * the orient mode in the register 0x2C bit 0 and 1 + * + * + * + * @param orient_mode_u8 : The value of orient mode + * orient_mode_u8 | result + * --------------------|------------------ + * 0x00 | symmetrical + * 0x01 | high asymmetrical + * 0x02 | low asymmetrical + * 0x03 | symmetrical + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_orient_mode(u8 orient_mode_u8); +/******************************************/ +/**\name FUNCTION FOR ORIENT BLOCK*/ +/******************************************/ +/*! + * @brief This API is used to get + * the orient block in the register 0x2C bit 2 and 3 + * + * + * + * @param orient_block_u8 : The value of orient block + * orient_mode_u8 | result + * --------------------|------------------ + * 0x00 | no blocking + * 0x01 | theta blocking or + * | acceleration slope in any axis > 1.5g + * 0x02 | theta blocking or + * | acceleration slope in any axis > 0.2g + * | acceleration in any axis > 1.5g + * 0x03 | theta blocking or + * | acceleration slope in any axis > 0.4g + * | acceleration in any axis > 1.5g + * | value of orient is not stable for at lease 100ms + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_orient_block( + u8 *orient_block_u8); +/*! + * @brief This API is used to set + * the orient block in the register 0x2C bit 2 and 3 + * + * + * + * @param orient_block_u8 : The value of orient block + * orient_mode_u8 | result + * --------------------|------------------ + * 0x00 | no blocking + * 0x01 | theta blocking or + * | acceleration slope in any axis > 1.5g + * 0x02 | theta blocking or + * | acceleration slope in any axis > 0.2g + * | acceleration in any axis > 1.5g + * 0x03 | theta blocking or + * | acceleration slope in any axis > 0.4g + * | acceleration in any axis > 1.5g + * | value of orient is not stable for at lease 100ms + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_orient_block(u8 orient_block_u8); +/******************************************/ +/**\name FUNCTION FOR ORIENT HYSTERESIS */ +/******************************************/ +/*! + * @brief This API is used to get + * the orient hysteresis in the register 0x2C bit 4 to 6 + * + * + * + * @param orient_hyst_u8 : The value of orient hysteresis + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_orient_hyst(u8 *orient_hyst_u8); +/*! + * @brief This API is used to set + * the orient hysteresis in the register 0x2C bit 4 to 6 + * + * + * + * @param orient_hyst_u8 : The value of orient hysteresis + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_orient_hyst(u8 orient_hyst_u8); +/******************************************/ +/**\name FUNCTION FOR ORIENT THETA */ +/******************************************/ +/*! + * @brief This API is used to get + * the theta value of orient and flat interrupts + * @note ORIENT_THETA -> register 0x2D bit 0 to 5 + * @note FLAT_THETA -> register 0x2E bit 0 to 5 + * + * @param channel_u8: The value of theta selection + * channel_u8 | result + * --------------------|------------------ + * 0x00 | BMA2x2_ACCEL_ORIENT_THETA + * 0x01 | BMA2x2_ACCEL_FLAT_THETA + * @note + * @note FLAT_THETA : Defines a blocking angle between 0 deg to 44.8 deg + * @note ORIENT_THETA : Defines threshold for detection of flat position + * in range from 0 deg to 44.8 deg + * + * @param theta_u8: The value of theta + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_theta(u8 channel_u8, + u8 *theta_u8); +/*! + * @brief This API is used to set + * the theta value of orient and flat interrupts + * @note ORIENT_THETA -> register 0x2D bit 0 to 5 + * @note FLAT_THETA -> register 0x2E bit 0 to 5 + * + * @param channel_u8: The value of theta selection + * channel_u8 | result + * --------------------|------------------ + * 0x00 | BMA2x2_ACCEL_ORIENT_THETA + * 0x01 | BMA2x2_ACCEL_FLAT_THETA + * @note + * @note FLAT_THETA : Defines a blocking angle between 0 deg to 44.8 deg + * @note ORIENT_THETA : Defines threshold for detection of flat position + * in range from 0 deg to 44.8 deg + * + * @param theta_u8: The value of theta + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_theta(u8 channel_u8, + u8 theta_u8); +/******************************************/ +/**\name FUNCTION FOR ORIENT ENABLE*/ +/******************************************/ +/*! + * @brief This API is used to get + * the interrupt enable of orient ud_enable in the register 0x2D bit 6 + * + * + * @param orient_enable_u8 : The value of orient ud_enable + * orient_enable_u8 | result + * ------------------------- |------------------ + * 0x00 | Generates Interrupt + * 0x01 | Do not generate interrupt + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_orient_enable( + u8 *orient_enable_u8); +/*! + * @brief This API is used to set + * the interrupt enable of orient ud_enable in the register 0x2D bit 6 + * + * + * @param orient_enable_u8 : The value of orient ud_enable + * orient_enable_u8 | result + * ------------------------- |------------------ + * 0x00 | Generates Interrupt + * 0x01 | Do not generate interrupt + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_orient_enable(u8 orient_enable_u8); +/******************************************/ +/**\name FUNCTION FOR FLAT HYSTERESIS */ +/******************************************/ +/*! + * @brief This API is used to get + * the interrupt enable of flat hysteresis("flat_hy) + * in the register 0x2F bit 0 to 2 + * + * + * + * + * @param flat_hyst_u8 : The value of flat hysteresis + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_flat_hyst(u8 *flat_hyst_u8); +/*! + * @brief This API is used to set + * the interrupt enable of flat hysteresis("flat_hy) + * in the register 0x2F bit 0 to 2 + * + * + * + * + * @param flat_hyst_u8 : The value of flat hysteresis + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_flat_hyst(u8 flat_hyst_u8); +/******************************************/ +/**\name FUNCTION FOR FLAT HOLD TIME */ +/******************************************/ +/*! + * @brief This API is used to get + * the interrupt enable of flat hold time(flat_hold_time) + * in the register 0x2F bit 4 and 5 + * + * + * @param flat_hold_time_u8 : The value of flat hold time + * flat_hold_time_u8 | result + * ------------------------- |------------------ + * 0x00 | 0ms + * 0x01 | 512ms + * 0x02 | 1024ms + * 0x03 | 2048ms + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_flat_hold_time( + u8 *flat_hold_time_u8); +/*! + * @brief This API is used to set + * the interrupt enable of flat hold time(flat_hold_time) + * in the register 0x2F bit 4 and 5 + * + * + * @param flat_hold_time_u8 : The value of flat hold time + * flat_hold_time_u8 | result + * ------------------------- |------------------ + * 0x00 | 0ms + * 0x01 | 512ms + * 0x02 | 1024ms + * 0x03 | 2048ms + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_flat_hold_time( + u8 flat_hold_time_u8); +/******************************************/ +/**\name FUNCTION FOR FIFO WATER MARK LEVEL TRIGGER */ +/******************************************/ +/*! + * @brief This API is used to get + * the fifo water mark level trigger in the register 0x30 bit from 0 to 5 + * + * + * + * + * @param fifo_wml_trig: The value of fifo watermark trigger level + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_fifo_wml_trig( + u8 *fifo_wml_trig); +/*! + * @brief This API is used to set + * the fifo water mark level trigger in the register 0x30 bit from 0 to 5 + * + * + * + * + * @param fifo_wml_trig: The value of fifo watermark trigger level + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_fifo_wml_trig( + u8 fifo_wml_trig); +/******************************************/ +/**\name FUNCTION FOR SELFTEST */ +/******************************************/ +/*! + * @brief This API is for to get + * the self test axis(self_test_axis) in the register ox32 bit 0 to 2 + * + * + * + * @param selftest_axis_u8 : The value of selftest axis + * selftest_axis_u8 | result + * ------------------------- |------------------ + * 0x00 | self test disable + * 0x01 | x-axis + * 0x02 | y-axis + * 0x03 | z-axis + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_selftest_axis( + u8 *selftest_axis_u8); +/*! + * @brief This API is for to set + * the self test axis(self_test_axis) in the register ox32 bit 0 to 2 + * + * + * + * @param selftest_axis_u8 : The value of selftest axis + * selftest_axis_u8 | result + * ------------------------- |------------------ + * 0x00 | self test disable + * 0x01 | x-axis + * 0x02 | y-axis + * 0x03 | z-axis + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_selftest_axis( + u8 selftest_axis_u8); +/*! + * @brief This API is for to get + * the Self Test sign(selftest_sign) in the register 0x32 bit 2 + * + * + * + * @param selftest_sign_u8 : The value of self test sign + * selftest_sign_u8 | result + * ------------------------- |------------------ + * 0x00 | negative sign + * 0x01 | positive sign + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_selftest_sign( + u8 *selftest_sign_u8); +/*! + * @brief This API is for to set + * the Self Test sign(selftest_sign) in the register 0x32 bit 2 + * + * + * + * @param selftest_sign_u8 : The value of self test sign + * selftest_sign_u8 | result + * ------------------------- |------------------ + * 0x00 | negative sign + * 0x01 | positive sign + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_selftest_sign( + u8 selftest_sign_u8); +/******************************************/ +/**\name FUNCTION FOR NVM */ +/******************************************/ +/*! + * @brief This API is used to get + * the nvm program mode(nvm_prog_mode)in the register 0x33 bit 0 + * + * + * @param nvmprog_mode_u8 : The value of nvm program mode + * nvmprog_mode_u8 | result + * ------------------------- |------------------ + * 0x00 | Disable program mode + * 0x01 | Enable program mode + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_nvmprog_mode( + u8 *nvmprog_mode_u8); +/*! + * @brief This API is used to set + * the nvm program mode(nvm_prog_mode)in the register 0x33 bit 0 + * + * + * @param nvmprog_mode_u8 : The value of nvm program mode + * nvmprog_mode_u8 | result + * ------------------------- |------------------ + * 0x00 | Disable program mode + * 0x01 | Enable program mode + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_nvmprog_mode(u8 nvmprog_mode_u8); +/*! + * @brief This API is used to set + * the value of nvm program trig in the register 0x33 bit 1 + * + * + * + * + * @param nvprog_trig_u8: The value of nvm program trig + * nvprog_trig_u8 | result + * ------------------------- |------------------ + * 0x00 | Do not trigger nvm program + * 0x01 | Trigger nvm program + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_nvprog_trig(u8 nvprog_trig_u8); +/*! + * @brief This API is used to get + * the nvm program ready in the register bit 2 + * + * + * @param nvprog_ready_u8: The value of nvm program ready + * nvprog_ready_u8 | result + * ------------------------- |------------------ + * 0x00 | nvm write/update operation is in progress + * 0x01 | nvm is ready to accept a new write + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_nvmprog_ready(u8 *nvprog_ready_u8); +/*! + * @brief This API is used to set + * the nvm program ready in the register bit 2 + * + * + * @param nvprog_remain_u8: The value of nvm program ready + * nvprog_remain_u8 | result + * ------------------------- |------------------ + * 0x00 | nvm write/update operation is in progress + * 0x01 | nvm is ready to accept a new write + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_nvmprog_remain(u8 *nvprog_remain_u8); +/******************************************/ +/**\name FUNCTION FOR SPI/I2C CONFIGURATION */ +/******************************************/ +/*! + * @brief This API is used to get the enable status of spi3 + * in the register 0x34 bit 0 + * + * + * + * @param spi3_u8 : The value of SPI 3 or 4 wire enable + * spi3_u8 | result + * ------------------------- |------------------ + * 0x00 | spi4 + * 0x01 | spi3 + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_spi3(u8 *spi3_u8); +/*! + * @brief This API is used to set the enable status of spi3 + * in the register 0x34 bit 0 + * + * + * + * @param spi3_u8 : The value of SPI 3 or 4 wire enable + * spi3_u8 | result + * ------------------------- |------------------ + * 0x00 | spi4 + * 0x01 | spi3 + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_spi3(u8 spi3_u8); +/*! + * @brief This API is used to get the i2c + * watch dog timer period and I2C interface mode is selected + * in the register 0x34 bit 1 and 2 + * + * + * @param channel_u8: The i2c option selection + * channel_u8 | result + * ------------------------- |------------------ + * 0 | BMA2x2_ACCEL_I2C_SELECT + * 1 | BMA2x2_ACCEL_I2C_ENABLE + * + * @param i2c_wdt_u8: watch dog timer period + * and I2C interface mode is selected + * BMA2x2_ACCEL_I2C_SELECT| result + * ------------------------- |------------------ + * 0x00 | Disable the watchdog at SDI pin + * 0x01 | Enable watchdog + * + * BMA2x2_I2C_ENABLE | result + * ------------------------- |------------------ + * 0x00 | 1ms + * 0x01 | 50ms + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_i2c_wdt(u8 channel_u8, + u8 *i2c_wdt_u8); +/*! + * @brief This API is used to set the i2c + * watch dog timer period and I2C interface mode is selected + * in the register 0x34 bit 1 and 2 + * + * + * @param channel_u8: The i2c option selection + * channel_u8 | result + * ------------------------- |------------------ + * 0 | BMA2x2_ACCEL_I2C_SELECT + * 1 | BMA2x2_ACCEL_I2C_ENABLE + * + * @param i2c_wdt_u8: watch dog timer period + * and I2C interface mode is selected + * BMA2x2_ACCEL_I2C_SELECT| result + * ------------------------- |------------------ + * 0x00 | Disable the watchdog at SDI pin + * 0x01 | Enable watchdog + * + * BMA2x2_I2C_ENABLE | result + * ------------------------- |------------------ + * 0x00 | 1ms + * 0x01 | 50ms + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_i2c_wdt(u8 channel_u8, + u8 i2c_wdt_u8); +/******************************************/ +/**\name FUNCTION FOR OFFSET */ +/******************************************/ +/*! + * @brief This API is used to get + * slow compensation(hp_x_enable, hp_y_enable and hp_z_enable) enable + * in the register 0x36 bit 0 to 2 + * @note SLOW_COMP_X -> bit 0 + * @note SLOW_COMP_Y -> bit 1 + * @note SLOW_COMP_Z -> bit 2 + * + * + * @param channel_u8: The value of slow compensation selection + * channel_u8 | result + * ------------------------- |------------------ + * 0 | BMA2x2_ACCEL_SLOW_COMP_X + * 1 | BMA2x2_ACCEL_SLOW_COMP_Y + * 2 | BMA2x2_ACCEL_SLOW_COMP_Z + * + * @param slow_comp_u8: The value of slow compensation enable + * slow_comp_u8 | result + * ------------------------- |------------------ + * 0x00 | Disable + * 0x01 | Enable + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_slow_comp(u8 channel_u8, + u8 *slow_comp_u8); +/*! + * @brief This API is used to set + * slow compensation(hp_x_enable, hp_y_enable and hp_z_enable) enable + * in the register 0x36 bit 0 to 2 + * @note SLOW_COMP_X -> bit 0 + * @note SLOW_COMP_Y -> bit 1 + * @note SLOW_COMP_Z -> bit 2 + * + * + * @param channel_u8: The value of slow compensation selection + * channel_u8 | result + * ------------------------- |------------------ + * 0 | BMA2x2_ACCEL_SLOW_COMP_X + * 1 | BMA2x2_ACCEL_SLOW_COMP_Y + * 2 | BMA2x2_ACCEL_SLOW_COMP_Z + * + * @param slow_comp_u8: The value of slow compensation enable + * slow_comp_u8 | result + * ------------------------- |------------------ + * 0x00 | Disable + * 0x01 | Enable + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_slow_comp(u8 channel_u8, + u8 slow_comp_u8); +/*! + * @brief This API is used to get + * the status of fast offset compensation(cal_rdy) in the register 0x36 + * bit 4(Read Only Possible) + * + * + * + * @param cal_rdy_u8: The value of cal_ready + * + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_cal_rdy(u8 *cal_rdy_u8); +/*! + * @brief This API is used to set + * the status of fast offset compensation(cal_rdy) in the register 0x36 + * bit 4(Read Only Possible) + * + * + * + * @param cal_trigger_u8: The value of cal_ready + * + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_cal_trigger(u8 cal_trigger_u8); +/*! + * @brief This API is used to set + * the offset reset(offset_reset) in the register 0x36 + * bit 7(Write only possible) + * + * + * + * @param offset_rst_u8: The offset reset value + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_offset_rst(u8 offset_rst_u8); +/*! + * @brief This API is used to get + * the status of offset target axis(offset_target_x, offset_target_y and + * offset_target_z) and cut_off in the register 0x37 + * @note CUT_OFF -> bit 0 + * @note OFFSET_TRIGGER_X -> bit 1 and 2 + * @note OFFSET_TRIGGER_Y -> bit 3 and 4 + * @note OFFSET_TRIGGER_Z -> bit 5 and 6 + * + * + * @param channel_u8: The value of offset axis selection + * channel_u8 | result + * ------------------------- |------------------ + * 0 | BMA2x2_ACCEL_CUT_OFF + * 1 | BMA2x2_ACCEL_OFFSET_TRIGGER_X + * 2 | BMA2x2_ACCEL_OFFSET_TRIGGER_Y + * 2 | BMA2x2_ACCEL_OFFSET_TRIGGER_Z + * + * @param offset_u8: The offset target value + * CUT_OFF | result + * ------------------------- |------------------ + * 0 | 1Hz + * 1 | 10Hz + * + * + * OFFSET_TRIGGER | result + * ------------------------- |------------------ + * 0x00 | 0g + * 0x01 | +1g + * 0x02 | -1g + * 0x03 | 0g + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_offset_target(u8 channel_u8, + u8 *offset_u8); +/*! + * @brief This API is used to set + * the status of offset target axis(offset_target_x, offset_target_y and + * offset_target_z) and cut_off in the register 0x37 + * @note CUT_OFF -> bit 0 + * @note OFFSET_TRIGGER_X -> bit 1 and 2 + * @note OFFSET_TRIGGER_Y -> bit 3 and 4 + * @note OFFSET_TRIGGER_Z -> bit 5 and 6 + * + * + * @param channel_u8: The value of offset axis selection + * channel_u8 | result + * ------------------------- |------------------ + * 0 | BMA2x2_ACCEL_CUT_OFF + * 1 | BMA2x2_ACCEL_OFFSET_TRIGGER_X + * 2 | BMA2x2_ACCEL_OFFSET_TRIGGER_Y + * 2 | BMA2x2_ACCEL_OFFSET_TRIGGER_Z + * + * @param offset_u8: The offset target value + * CUT_OFF | result + * ------------------------- |------------------ + * 0 | 1Hz + * 1 | 10Hz + * + * + * OFFSET_TRIGGER | result + * ------------------------- |------------------ + * 0x00 | 0g + * 0x01 | +1g + * 0x02 | -1g + * 0x03 | 0g + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_offset_target(u8 channel_u8, + u8 offset_u8); +/*! + * @brief This API is used to get the status of offset + * (offset_x, offset_y and offset_z) in the registers 0x38,0x39 and 0x3A + * @note offset_x -> register 0x38 bit 0 to 7 + * @note offset_y -> register 0x39 bit 0 to 7 + * @note offset_z -> register 0x3A bit 0 to 7 + * + * + * @param channel_u8: The value of offset selection + * channel_u8 | result + * ------------------------- |------------------ + * 0 | BMA2x2_ACCEL_X_AXIS + * 1 | BMA2x2_ACCEL_Y_AXIS + * 2 | BMA2x2_ACCEL_Z_AXIS + * + * @param offset_u8: The value of offset + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_offset(u8 channel_u8, + s8 *offset_u8); +/*! + * @brief This API is used to set the status of offset + * (offset_x, offset_y and offset_z) in the registers 0x38,0x39 and 0x3A + * @note offset_x -> register 0x38 bit 0 to 7 + * @note offset_y -> register 0x39 bit 0 to 7 + * @note offset_z -> register 0x3A bit 0 to 7 + * + * + * @param channel_u8: The value of offset selection + * channel_u8 | result + * ------------------------- |------------------ + * 0 | BMA2x2_ACCEL_X_AXIS + * 1 | BMA2x2_ACCEL_Y_AXIS + * 2 | BMA2x2_ACCEL_Z_AXIS + * + * @param offset_u8: The value of offset + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_offset(u8 channel_u8, + s8 offset_u8); +/******************************************/ +/**\name FUNCTION FOR FIFO CONFIGURATION */ +/******************************************/ +/*! + * @brief This API is used to get + * the status of fifo (fifo_mode) in the register 0x3E bit 6 and 7 + * + * + * @param fifo_mode_u8 : The value of fifo mode + * fifo_mode_u8 | result + * ------------------------- |------------------ + * 0x00 | BYPASS + * 0x01 | FIFO + * 0x02 | STREAM + * 0x03 | RESERVED + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_fifo_mode(u8 *fifo_mode_u8); +/*! + * @brief This API is used to set + * the status of fifo (fifo_mode) in the register 0x3E bit 6 and 7 + * + * + * @param fifo_mode_u8 : The value of fifo mode + * fifo_mode_u8 | result + * ------------------------- |------------------ + * 0x00 | BYPASS + * 0x01 | FIFO + * 0x02 | STREAM + * 0x03 | RESERVED + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_fifo_mode(u8 fifo_mode_u8); +/*! + * @brief This API is used to get + * the axis enable of fifo data select in the register 0x3E bit 0 and 1 + * + * + * @param fifo_data_select_u8 : The value of FIFO axis data select + * fifo_data_select_u8 | result + * ------------------------- |------------------ + * 0x00 | XYZ + * 0x01 | Y + * 0x02 | X + * 0x03 | Z + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_fifo_data_select( + u8 *fifo_data_select_u8); +/*! + * @brief This API is used to set + * the axis enable of fifo data select in the register 0x3E bit 0 and 1 + * + * + * @param fifo_data_select_u8 : The value of FIFO axis data select + * fifo_data_select_u8 | result + * ------------------------- |------------------ + * 0x00 | XYZ + * 0x01 | Y + * 0x02 | X + * 0x03 | Z + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_fifo_data_select( + u8 fifo_data_select_u8); + +/*! + * @brief This API reads the FIFO data from the register 0x3F + * and store the data in the user defined buffer mapped to the member + * of structure "fifo_configuration" + * + * @note Before calling this API user must map the following FIFO settings + * required to read the FIFO data to the structure "fifo_configuration" + * - Data buffer to store the FIFO data is mapped to + * the structure member "fifo_data" + * - Number of bytes to be read from FIFO is mapped to + * the structure member "fifo_length" + * + * @note The number of bytes to be read from the FIFO is specified in the + * member "fifo_length" of the structure "fifo_configuration" + * + * @param[in,out] fifo_conf : Structure containing the FIFO configurations + * is passed as input and FIFO data of specified length is obtained as output + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_fifo_data( + struct fifo_configuration *fifo_conf); + +/*! + * @brief This API extracts the accel data from the FIFO frames + * + * @note The bma2x2_extract_accel() API should be called only after reading + * the FIFO data by calling the bma2x2_read_fifo_data() API + * + * @param[in,out] accel_frame : Instance of the union where accel data + * in FIFO is parsed and stored + * + * @param[in,out] accel_frame_count: Number of Accel frames requested by user + * is got as input and number of + * accel frames parsed and stored is + * returned as output to user + * + * @param[in, out] fifo_conf : FIFO configuration structure. + * It provides the following as input + * - user defined buffer + * - length of FIFO data read + * It returns the accel_byte_start_index + * (index of accel bytes parsed from FIFO) + * + * @return results of API execution status + * @retval 0 -> Success + * @retval -127 -> Error + * + */ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_extract_accel(union fifo_frame *accel_frame, + u8 *accel_frame_count, struct fifo_configuration *fifo_conf); +/******************************************/ +/**\name FUNCTION FOR TEMPERATURE DATA READ */ +/******************************************/ +/*! + * @brief This API is used to read the temp + * from register 0x08 + * + * + * + * @param temp_s8: The value of temperature + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_temp(s8 *temp_s8); +/******************************************/ +/**\name FUNCTION FOR DATA XYZ WITH TEMPERATURE */ +/******************************************/ +/*! + * @brief This API reads accelerometer data X,Y,Z values and + * temperature data from location 02h to 08h + * + * + * + * + * @param accel : The value of accel xyz and temperature data + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_xyzt( + struct bma2x2_accel_data_temp *accel); +/*! + * @brief This API reads accelerometer data X,Y,Z values and + * temperature data from location 0x02 to 0x08 + * + * + * + * + * @param accel : The value of accel xyz and temperature data + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_eight_resolution_xyzt( + struct bma2x2_accel_eight_resolution_temp *accel); +/*Depreciated Functions*/ +/*! + * @brief This API is used to get + * the fifo data in the register 0x3F bit 0 to 7 + * + * + * @param output_reg_u8 : The value of fifo data + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_fifo_data_output_reg( + u8 *output_reg_u8); +#endif + diff --git a/bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMA2x2_driver/bma2x2_support.c b/bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMA2x2_driver/bma2x2_support.c new file mode 100644 index 0000000000000000000000000000000000000000..221f0da004e15bc5137dd67fb15076c2a951c761 --- /dev/null +++ b/bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMA2x2_driver/bma2x2_support.c @@ -0,0 +1,512 @@ +/* +**************************************************************************** +* Copyright (C) 2015 - 2016 Bosch Sensortec GmbH +* +* bma2x2_support.c +* Date: 2016/03/09 +* Revision: 1.0.4 $ +* +* Usage: Sensor Driver support file for BMA2x2 sensor +* +**************************************************************************** +* Disclaimer +* +* Common: +* Bosch Sensortec products are developed for the consumer goods industry. +* They may only be used within the parameters of the respective valid +* product data sheet. Bosch Sensortec products are provided with the +* express understanding that there is no warranty of fitness for a +* particular purpose.They are not fit for use in life-sustaining, +* safety or security sensitive systems or any system or device +* that may lead to bodily harm or property damage if the system +* or device malfunctions. In addition,Bosch Sensortec products are +* not fit for use in products which interact with motor vehicle systems. +* The resale and or use of products are at the purchasers own risk and +* his own responsibility. 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Do not use this Software if you do not have the +* proper experience or training. +* +* This Software package is provided `` as is `` and without any expressed +* or implied warranties,including without limitation, the implied warranties +* of merchantability and fitness for a particular purpose. +* +* Bosch Sensortec and their representatives and agents deny any liability +* for the functional impairment +* of this Software in terms of fitness, performance and safety. +* Bosch Sensortec and their representatives and agents shall not be liable +* for any direct or indirect damages or injury, except as +* otherwise stipulated in mandatory applicable law. +* +* The Information provided is believed to be accurate and reliable. +* Bosch Sensortec assumes no responsibility for the consequences of use +* of such Information nor for any infringement of patents or +* other rights of third parties which may result from its use. +* No license is granted by implication or otherwise under any patent or +* patent rights of Bosch. Specifications mentioned in the Information are +* subject to change without notice. +**************************************************************************/ +/*---------------------------------------------------------------------------*/ +/* Includes*/ +/*---------------------------------------------------------------------------*/ +#include "bma2x2.h" + +/*----------------------------------------------------------------------------* +* The following functions are used for reading and writing of +* sensor data using I2C or SPI communication +*----------------------------------------------------------------------------*/ +#ifdef BMA2x2_API + /* \Brief: The function is used as I2C bus read + * \Return : Status of the I2C read + * \param dev_addr : The device address of the sensor + * \param reg_addr : Address of the first register, + * will data is going to be read + * \param reg_data : This data read from the sensor, + * which is hold in an array + * \param cnt : The no of byte of data to be read + */ + s8 BMA2x2_I2C_bus_read(u8 dev_addr, u8 reg_addr, u8 *reg_data, u8 cnt); + /* \Brief: The function is used as I2C bus write + * \Return : Status of the I2C write + * \param dev_addr : The device address of the sensor + * \param reg_addr : Address of the first register, + * will data is going to be written + * \param reg_data : It is a value hold in the array, + * will be used for write the value into the register + * \param cnt : The no of byte of data to be write + */ + s8 BMA2x2_I2C_bus_write(u8 dev_addr, u8 reg_addr, u8 *reg_data, u8 cnt); + /* \Brief: The function is used as SPI bus write + * \Return : Status of the SPI write + * \param dev_addr : The device address of the sensor + * \param reg_addr : Address of the first register, + * will data is going to be written + * \param reg_data : It is a value hold in the array, + * will be used for write the value into the register + * \param cnt : The no of byte of data to be write + */ + s8 BMA2x2_SPI_bus_write(u8 dev_addr, u8 reg_addr, u8 *reg_data, u8 cnt); + /* \Brief: The function is used as SPI bus read + * \Return : Status of the SPI read + * \param dev_addr : The device address of the sensor + * \param reg_addr : Address of the first register, + * will data is going to be read + * \param reg_data : This data read from the sensor, which is hold in an array + * \param cnt : The no of byte of data to be read */ + s8 BMA2x2_SPI_bus_read(u8 dev_addr, u8 reg_addr, u8 *reg_data, u8 cnt); + /* + * \Brief: SPI/I2C init routine + */ + s8 I2C_routine(void); + s8 SPI_routine(void); +#endif +/********************End of I2C/SPI function declarations*******************/ +/* Brief : The delay routine + * \param : delay in ms + */ +void BMA2x2_delay_msek(u32 msek); +/*! + * @brief This function is an example for delay + * @param : None + * @return : communication result + */ +s32 bma2x2_data_readout_template(void); +/*----------------------------------------------------------------------------* +* struct bma2x2_t parameters can be accessed by using bma2x2 + * bma2x2_t having the following parameters + * Bus write function pointer: BMA2x2_WR_FUNC_PTR + * Bus read function pointer: BMA2x2_RD_FUNC_PTR + * Burst read function pointer: BMA2x2_BRD_FUNC_PTR + * Delay function pointer: delay_msec + * I2C address: dev_addr + * Chip id of the sensor: chip_id + *---------------------------------------------------------------------------*/ +struct bma2x2_t bma2x2; +/*----------------------------------------------------------------------------* +* V_BMA2x2RESOLUTION_u8R used for selecting the accelerometer resolution + * 12 bit + * 14 bit + * 10 bit +*----------------------------------------------------------------------------*/ +extern u8 V_BMA2x2RESOLUTION_u8R; +/* This function is an example for reading sensor data + * \param: None + * \return: communication result + */ +s32 bma2x2_data_readout_template(void) +{ + /*Local variables for reading accel x, y and z data*/ + s16 accel_x_s16, accel_y_s16, accel_z_s16 = BMA2x2_INIT_VALUE; + + /* bma2x2acc_data structure used to read accel xyz data*/ + struct bma2x2_accel_data sample_xyz; + /* bma2x2acc_data_temp structure used to read + accel xyz and temperature data*/ + struct bma2x2_accel_data_temp sample_xyzt; + /* Local variable used to assign the bandwidth value*/ + u8 bw_value_u8 = BMA2x2_INIT_VALUE; + /* Local variable used to set the bandwidth value*/ + u8 banwid = BMA2x2_INIT_VALUE; + /* status of communication*/ + s32 com_rslt = ERROR; + + + /*********************** START INITIALIZATION ************************ + * Based on the user need configure I2C or SPI interface. + * It is example code to explain how to use the bma2x2 API*/ +#ifdef BMA2x2_API + I2C_routine(); + /*SPI_routine(); */ +#endif + /*--------------------------------------------------------------------------* + * This function used to assign the value/reference of + * the following parameters + * I2C address + * Bus Write + * Bus read + * Chip id + *-------------------------------------------------------------------------*/ + com_rslt = bma2x2_init(&bma2x2); + + /* For initialization it is required to set the mode of + * the sensor as "NORMAL" + * NORMAL mode is set from the register 0x11 and 0x12 + * 0x11 -> bit 5,6,7 -> set value as 0 + * 0x12 -> bit 5,6 -> set value as 0 + * data acquisition/read/write is possible in this mode + * by using the below API able to set the power mode as NORMAL + * For the Normal/standby/Low power 2 mode Idle time + of at least 2us(micro seconds) + * required for read/write operations*/ + /* Set the power mode as NORMAL*/ + com_rslt += bma2x2_set_power_mode(BMA2x2_MODE_NORMAL); + /* Note: + * For the Suspend/Low power1 mode Idle time of + at least 450us(micro seconds) + * required for read/write operations*/ + + /************************* END INITIALIZATION *************************/ + + /*------------------------------------------------------------------------* + ************************* START GET and SET FUNCTIONS DATA **************** + *---------------------------------------------------------------------------*/ + /* This API used to Write the bandwidth of the sensor input + value have to be given + bandwidth is set from the register 0x10 bits from 1 to 4*/ + bw_value_u8 = 0x08;/* set bandwidth of 7.81Hz*/ + com_rslt += bma2x2_set_bw(bw_value_u8); + + /* This API used to read back the written value of bandwidth*/ + com_rslt += bma2x2_get_bw(&banwid); + /*-----------------------------------------------------------------* + ************************* END GET and SET FUNCTIONS **************** + *-------------------------------------------------------------------*/ + /*------------------------------------------------------------------* + ************************* START READ SENSOR DATA(X,Y and Z axis) ******** + *---------------------------------------------------------------------*/ + /* Read the accel X data*/ + com_rslt += bma2x2_read_accel_x(&accel_x_s16); + /* Read the accel Y data*/ + com_rslt += bma2x2_read_accel_y(&accel_y_s16); + /* Read the accel Z data*/ + com_rslt += bma2x2_read_accel_z(&accel_z_s16); + + /* accessing the bma2x2acc_data parameter by using sample_xyz*/ + /* Read the accel XYZ data*/ + com_rslt += bma2x2_read_accel_xyz(&sample_xyz); + + /* accessing the bma2x2acc_data_temp parameter by using sample_xyzt*/ + /* Read the accel XYZT data*/ + com_rslt += bma2x2_read_accel_xyzt(&sample_xyzt); + + /*--------------------------------------------------------------------* + ************************* END READ SENSOR DATA(X,Y and Z axis) ************ + *-------------------------------------------------------------------------*/ + /*-----------------------------------------------------------------------* + ************************* START DE-INITIALIZATION *********************** + *-------------------------------------------------------------------------*/ + /* For de-initialization it is required to set the mode of + * the sensor as "DEEP SUSPEND" + * DEEP SUSPEND mode is set from the register 0x11 + * 0x11 -> bit 5 -> set value as 1 + * the device reaches the lowest power consumption only + * interface selection is kept alive + * No data acquisition is performed + * by using the below API able to set the power mode as DEEPSUSPEND*/ + /* Set the power mode as DEEPSUSPEND*/ + com_rslt += bma2x2_set_power_mode(BMA2x2_MODE_DEEP_SUSPEND); + /*---------------------------------------------------------------------* + ************************* END DE-INITIALIZATION ********************** + *---------------------------------------------------------------------*/ + return com_rslt; +} + +#ifdef BMA2x2_API +/*--------------------------------------------------------------------------* +* The following function is used to map the I2C bus read, write, delay and +* device address with global structure bma2x2_t +*-------------------------------------------------------------------------*/ +s8 I2C_routine(void) +{ + /*--------------------------------------------------------------------------* + * By using bma2x2 the following structure parameter can be accessed + * Bus write function pointer: BMA2x2_WR_FUNC_PTR + * Bus read function pointer: BMA2x2_RD_FUNC_PTR + * Delay function pointer: delay_msec + * I2C address: dev_addr + *--------------------------------------------------------------------------*/ + bma2x2.bus_write = BMA2x2_I2C_bus_write; + bma2x2.bus_read = BMA2x2_I2C_bus_read; + bma2x2.delay_msec = BMA2x2_delay_msek; + bma2x2.dev_addr = BMA2x2_I2C_ADDR2; + + return BMA2x2_INIT_VALUE; +} + +/*---------------------------------------------------------------------------* + * The following function is used to map the SPI bus read, write and delay + * with global structure bma2x2_t + *--------------------------------------------------------------------------*/ +s8 SPI_routine(void) +{ + /*--------------------------------------------------------------------------* + * By using bma2x2 the following structure parameter can be accessed + * Bus write function pointer: BMA2x2_WR_FUNC_PTR + * Bus read function pointer: BMA2x2_RD_FUNC_PTR + * Delay function pointer: delay_msec + *--------------------------------------------------------------------------*/ + + bma2x2.bus_write = BMA2x2_SPI_bus_write; + bma2x2.bus_read = BMA2x2_SPI_bus_read; + bma2x2.delay_msec = BMA2x2_delay_msek; + + return BMA2x2_INIT_VALUE; +} + +/************** I2C/SPI buffer length ******/ +#define I2C_BUFFER_LEN 8 +#define SPI_BUFFER_LEN 5 +#define BMA2x2_BUS_READ_WRITE_ARRAY_INDEX 1 +#define BMA2x2_SPI_BUS_WRITE_CONTROL_BYTE 0x7F +#define BMA2x2_SPI_BUS_READ_CONTROL_BYTE 0x80 + +/*-------------------------------------------------------------------* +* This is a sample code for read and write the data by using I2C/SPI +* Use either I2C or SPI based on your need +* +*-----------------------------------------------------------------------*/ +/* For configuring the I2C it is required to switch ON + * SDI, SDO and CLk and also select the device address + * The following definition of I2C address is used for the following sensors + * BMA255 + * BMA253 + * BMA355 + * BMA280 + * BMA282 + * BMA223 + * BMA254 + * BMA284 + * BMA250E + * BMA222E + + #define BMA2x2_I2C_ADDR1 0x18 + #define BMA2x2_I2C_ADDR2 0x19 + + * The following definition of I2C address is used for the following sensors + * BMC150 + * BMC056 + * BMC156 + + #define BMA2x2_I2C_ADDR3 0x10 + #define BMA2x2_I2C_ADDR4 0x11 + *************************************************************************/ +/* \Brief: The function is used as I2C bus write +* \Return : Status of the I2C write +* \param dev_addr : The device address of the sensor +* \param reg_addr : Address of the first register, +* will data is going to be written +* \param reg_data : It is a value hold in the array, +* will be used for write the value into the register +* \param cnt : The no of byte of data to be write +*/ +s8 BMA2x2_I2C_bus_write(u8 dev_addr, u8 reg_addr, u8 *reg_data, u8 cnt) +{ + s32 iError = BMA2x2_INIT_VALUE; + u8 array[I2C_BUFFER_LEN]; + u8 stringpos = BMA2x2_INIT_VALUE; + + array[BMA2x2_INIT_VALUE] = reg_addr; + for (stringpos = BMA2x2_INIT_VALUE; stringpos < cnt; stringpos++) + { + array[stringpos + BMA2x2_BUS_READ_WRITE_ARRAY_INDEX] = + *(reg_data + stringpos); + } + /* + * Please take the below function as your reference for + * write the data using I2C communication + * "IERROR = I2C_WRITE_STRING(DEV_ADDR, ARRAY, CNT+1)" + * add your I2C write function here + * iError is an return value of I2C read function + * Please select your valid return value + * In the driver SUCCESS defined as 0 + * and FAILURE defined as -1 + * Note : + * This is a full duplex operation, + * The first read data is discarded, for that extra write operation + * have to be initiated. For that cnt+1 operation + * done in the I2C write string function + * For more information please refer data sheet SPI communication: + */ + return (s8)iError; +} + +/* \Brief: The function is used as I2C bus read +* \Return : Status of the I2C read +* \param dev_addr : The device address of the sensor +* \param reg_addr : Address of the first register, +* will data is going to be read +* \param reg_data : This data read from the sensor, +* which is hold in an array +* \param cnt : The no of byte of data to be read +*/ +s8 BMA2x2_I2C_bus_read(u8 dev_addr, u8 reg_addr, u8 *reg_data, u8 cnt) +{ + s32 iError = BMA2x2_INIT_VALUE; + u8 array[I2C_BUFFER_LEN] = {BMA2x2_INIT_VALUE}; + u8 stringpos = BMA2x2_INIT_VALUE; + + array[BMA2x2_INIT_VALUE] = reg_addr; + /* Please take the below function as your reference + * for read the data using I2C communication + * add your I2C rad function here. + * "IERROR = I2C_WRITE_READ_STRING(DEV_ADDR, ARRAY, ARRAY, 1, CNT)" + * iError is an return value of SPI write function + * Please select your valid return value + * In the driver SUCCESS defined as 0 + * and FAILURE defined as -1 + */ + for (stringpos = BMA2x2_INIT_VALUE; stringpos < cnt; stringpos++) + *(reg_data + stringpos) = array[stringpos]; + return (s8)iError; +} + +/* \Brief: The function is used as SPI bus read + * \Return : Status of the SPI read + * \param dev_addr : The device address of the sensor + * \param reg_addr : Address of the first register, + * will data is going to be read + * \param reg_data : This data read from the sensor, + * which is hold in an array + * \param cnt : The no of byte of data to be read */ +s8 BMA2x2_SPI_bus_read(u8 dev_addr, u8 reg_addr, u8 *reg_data, u8 cnt) +{ + s32 iError = BMA2x2_INIT_VALUE; + u8 array[SPI_BUFFER_LEN] = {0xFF}; + u8 stringpos; + /* For the SPI mode only 7 bits of register addresses are used. + The MSB of register address is declared the bit what functionality it is + read/write (read as 1/write as 0)*/ + array[BMA2x2_INIT_VALUE] = reg_addr | BMA2x2_SPI_BUS_READ_CONTROL_BYTE; + /*read routine is initiated register address is mask with 0x80*/ + /* + * Please take the below function as your reference for + * read the data using SPI communication + * " IERROR = SPI_READ_WRITE_STRING(ARRAY, ARRAY, CNT+1)" + * add your SPI read function here + * iError is an return value of SPI read function + * Please select your valid return value + * In the driver SUCCESS defined as 0 + * and FAILURE defined as -1 + * Note : + * This is a full duplex operation, + * The first read data is discarded, for that extra write operation + * have to be initiated. For that cnt+1 operation done in the SPI read + * and write string function + * For more information please refer data sheet SPI communication: + */ + for (stringpos = BMA2x2_INIT_VALUE; stringpos < cnt; stringpos++) + { + *(reg_data + stringpos) = array[stringpos + + BMA2x2_BUS_READ_WRITE_ARRAY_INDEX]; + } + return (s8)iError; +} + +/* \Brief: The function is used as SPI bus write + * \Return : Status of the SPI write + * \param dev_addr : The device address of the sensor + * \param reg_addr : Address of the first register, +* will data is going to be written + * \param reg_data : It is a value hold in the array, + * will be used for write the value into the register + * \param cnt : The no of byte of data to be write + */ +s8 BMA2x2_SPI_bus_write(u8 dev_addr, u8 reg_addr, u8 *reg_data, u8 cnt) +{ + s32 iError = BMA2x2_INIT_VALUE; + u8 array[SPI_BUFFER_LEN * 2]; + u8 stringpos = BMA2x2_INIT_VALUE; + + for (stringpos = BMA2x2_INIT_VALUE; stringpos < cnt; stringpos++) + { + /* the operation of (reg_addr++)&0x7F done: + because it ensure the + 0 and 1 of the given value + It is done only for 8bit operation*/ + array[stringpos * 2] = (reg_addr++) & + BMA2x2_SPI_BUS_WRITE_CONTROL_BYTE; + array[stringpos * 2 + BMA2x2_BUS_READ_WRITE_ARRAY_INDEX] = + *(reg_data + stringpos); + } + /* Please take the below function as your reference + * for write the data using SPI communication + * add your SPI write function here. + * "IERROR = SPI_WRITE_STRING(ARRAY, CNT*2)" + * iError is an return value of SPI write function + * Please select your valid return value + * In the driver SUCCESS defined as 0 + * and FAILURE defined as -1 + */ + return (s8)iError; +} + +/* Brief : The delay routine + * \param : delay in ms +*/ +void BMA2x2_delay_msek(u32 msek) +{ + /*Here you can write your own delay routine*/ +} +#endif diff --git a/bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMG160_driver/README.md b/bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMG160_driver/README.md new file mode 100644 index 0000000000000000000000000000000000000000..c3e900296f18e4cba811d1964c12e0dd761ee6ca --- /dev/null +++ b/bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMG160_driver/README.md @@ -0,0 +1,64 @@ + +CONTENTS OF THIS FILE +======================= + * Introduction + * Version + * Integration details + * Driver files information + * Supported sensor interface + * Copyright + + +INTRODUCTION +=============== + - This package contains the Bosch Sensortec MEMS gyroscope sensor driver (sensor API) + - The sensor driver package includes bmg160.h, bmg160.c and bmg160_support.c files + - BMG160 sensor driver supports the following sensors + * BMG160 + * BMI055 - combination of bma2x2 + bmg160 + * BMX055 - combination of bma2x2 + bmg160 + bmm050 + +VERSION +========= + - Version of bmg160 sensor driver is: + * bmg160.c - V2.0.4 + * bmg160.h - V2.0.4 + * bmg160_support.c - V1.0.5 + +INTEGRATION DETAILS +===================== + - Integrate bmg160.h and bmg160.c file in to your project. + - The bmg160_support.c file contains only examples for API use cases, so it is not required to integrate into project. + +DRIVER FILES INFORMATION +=========================== + bmg160.h + ----------- + * This header file has the register address definition, constant definitions, data type definition and supported sensor driver calls declarations. + + bmg160.c + ------------ + * This file contains the implementation for the sensor driver APIs. + + bmg160_support.c + ---------------------- + * This file shall be used as an user guidance, here you can find samples of + * Initialize the sensor with I2C/SPI communication + - Add your code to the SPI and/or I2C bus read and bus write functions. + - Return value can be chosen by yourself + - API just passes that value to your application code + - Add your code to the delay function + - Change I2C address accordingly in bmg160.h + * Power mode configuration of the sensor + * Get and set functions usage + * Reading the sensor read out data + +SUPPORTED SENSOR INTERFACE +==================================== + - This gyroscope sensor driver supports SPI and I2C interfaces + + +COPYRIGHT +=========== + - Copyright (C) 2010 - 2015 Bosch Sensortec GmbH + diff --git a/bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMG160_driver/bmg160.c b/bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMG160_driver/bmg160.c new file mode 100644 index 0000000000000000000000000000000000000000..5af3c93d3ded8a4b32aee77dfa965d81d3b6060c --- /dev/null +++ b/bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMG160_driver/bmg160.c @@ -0,0 +1,7014 @@ +/* +**************************************************************************** +* Copyright (C) 2010 - 2015 Bosch Sensortec GmbH +* +* bmg160.c +* Date: 2015/04/29 +* Revision: 2.0.4 $ +* +* Usage: Sensor Driver for BMG160 sensor +* +**************************************************************************** +* License: +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* Neither the name of the copyright holder nor the names of the +* contributors may be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDER +* OR CONTRIBUTORS BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, +* OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT NOT LIMITED TO, +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* The information provided is believed to be accurate and reliable. +* The copyright holder assumes no responsibility +* for the consequences of use +* of such information nor for any infringement of patents or +* other rights of third parties which may result from its use. +* No license is granted by implication or otherwise under any patent or +* patent rights of the copyright holder. +**************************************************************************/ +/*! file bmg160.c + brief Driver for BMG160 */ +#include "bmg160.h" +static struct bmg160_t *p_bmg160; + + +/*! + * @brief This function is used for initialize + * the bus read and bus write functions + * and assign the chip id and I2C address of the gyro + * chip id is read in the register 0x00 bit from 0 to 7 + * + * @param bmg160 structure pointer. + * + * @note While changing the parameter of the bmg160_t + * consider the following point: + * @note Changing the reference value of the parameter + * will changes the local copy or local reference + * make sure your changes will not + * affect the reference value of the parameter + * (Better case don't change the reference value of the parameter) + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_init(struct bmg160_t *bmg160) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* Assign the initial function pointers*/ + p_bmg160 = bmg160; + /*Read CHIP_ID */ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_CHIP_ID_ADDR, &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + p_bmg160->chip_id = v_data_u8; + return comres; +} +/*! + * @brief Reads Rate data X in the registers 0x02 to 0x03 + * + * + * + * + * @param v_data_x_s16: The value of gyro x axis data + * + * + * @return results of bus communication function + * @retval 0 -> Success +* @retval -1 -> Error + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_data_X(s16 *v_data_x_s16) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = BMG160_INIT_VALUE; + /*Array holding the gyro data x LSB and MSB data + v_data_u8[0] - X LSB + v_data_u8[1] - X MSB + */ + u8 v_data_u8[BMG160_X_DATA_SIZE] = + { + BMG160_INIT_VALUE, BMG160_INIT_VALUE + }; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read the gyro x data */ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_RATE_X_LSB_BIT__REG, + v_data_u8, BMG160_X_DATA_LENGTH); + v_data_u8[BMG160_X_LSB_DATA] = BMG160_GET_BITSLICE( + v_data_u8[BMG160_X_LSB_DATA], + BMG160_RATE_X_LSB_BIT); + *v_data_x_s16 = (s16) + ((((s32)((s8)v_data_u8[BMG160_X_MSB_DATA])) << + BMG160_SHIFT_BIT_POSITION_BY_08_BITS) + | (v_data_u8[BMG160_X_LSB_DATA])); + } + return comres; +} +/*! + * @brief Reads Rate data Y in the registers 0x04 to 0x05 + * + * + * + * + * @param v_data_y_s16: The value of gyro y axis data + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_data_Y(s16 *v_data_y_s16) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + /*Array holding the gyro data y LSB and MSB data + v_data_u8[0] - Y LSB + v_data_u8[1] - Y MSB + */ + u8 v_data_u8[BMG160_Y_DATA_SIZE] = + { + BMG160_INIT_VALUE, BMG160_INIT_VALUE + }; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read the gyro y data*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC( + p_bmg160->dev_addr, + BMG160_RATE_Y_LSB_BIT__REG, v_data_u8, + BMG160_Y_DATA_LENGTH); + v_data_u8[BMG160_Y_LSB_DATA] = + BMG160_GET_BITSLICE(v_data_u8[BMG160_Y_LSB_DATA], + BMG160_RATE_Y_LSB_BIT); + *v_data_y_s16 = (s16) + ((((s32)((s8)v_data_u8[BMG160_Y_MSB_DATA])) + << BMG160_SHIFT_BIT_POSITION_BY_08_BITS) | + (v_data_u8[BMG160_Y_LSB_DATA])); + } + return comres; +} +/*! + * @brief Reads Rate data Z in the registers 0x06 to 0x07 + * + * + * @param v_data_z_s16: The value of gyro z axis data + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_data_Z(s16 *v_data_z_s16) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + /*Array holding the gyro data z LSB and MSB data + v_data_u8[0] - Z LSB + v_data_u8[1] - Z MSB + */ + u8 v_data_u8[BMG160_Z_DATA_SIZE] = + { + BMG160_INIT_VALUE, BMG160_INIT_VALUE + }; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_RATE_Z_LSB_BIT__REG, + v_data_u8, BMG160_Z_DATA_LENGTH); + v_data_u8[BMG160_Z_LSB_DATA] = + BMG160_GET_BITSLICE(v_data_u8[BMG160_Z_LSB_DATA], + BMG160_RATE_Z_LSB_BIT); + *v_data_z_s16 = (s16) + ((((s32)((s8)v_data_u8[BMG160_Z_MSB_DATA])) + << BMG160_SHIFT_BIT_POSITION_BY_08_BITS) + | (v_data_u8[BMG160_Z_LSB_DATA])); + } + return comres; +} +/*! + * @brief Reads data X,Y and Z from register location 0x02 to 0x07 + * + * + * + * + * @param data: The value of gyro xyz axis data + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_data_XYZ(struct bmg160_data_t *data) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + /*Array holding the gyro data xyz LSB and MSB data + v_data_u8[0] - X LSB + v_data_u8[1] - X MSB + v_data_u8[2] - Y MSB + v_data_u8[3] - Y MSB + v_data_u8[4] - Z MSB + v_data_u8[5] - Z MSB + */ + u8 v_data_u8[BMG160_XYZ_DATA_SIZE] = + { + BMG160_INIT_VALUE, BMG160_INIT_VALUE, + BMG160_INIT_VALUE, BMG160_INIT_VALUE, + BMG160_INIT_VALUE, BMG160_INIT_VALUE + }; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_RATE_X_LSB_BIT__REG, v_data_u8, + BMG160_ALL_DATA_FRAME_LENGTH); + /* Data X */ + v_data_u8[BMG160_DATA_FRAME_X_LSB_BYTE] = + BMG160_GET_BITSLICE(v_data_u8[BMG160_DATA_FRAME_X_LSB_BYTE], + BMG160_RATE_X_LSB_BIT); + data->datax = (s16) + ((((s32)((s8)v_data_u8[BMG160_DATA_FRAME_X_MSB_BYTE])) + << BMG160_SHIFT_BIT_POSITION_BY_08_BITS) | + (v_data_u8[BMG160_DATA_FRAME_X_LSB_BYTE])); + /* Data Y */ + v_data_u8[BMG160_DATA_FRAME_Y_LSB_BYTE] = + BMG160_GET_BITSLICE(v_data_u8[BMG160_DATA_FRAME_Y_LSB_BYTE], + BMG160_RATE_Y_LSB_BIT); + data->datay = (s16) + ((((s32)((s8)v_data_u8[BMG160_DATA_FRAME_Y_MSB_BYTE])) + << BMG160_SHIFT_BIT_POSITION_BY_08_BITS) | + (v_data_u8[BMG160_DATA_FRAME_Y_LSB_BYTE])); + /* Data Z */ + v_data_u8[BMG160_DATA_FRAME_Z_LSB_BYTE] = + BMG160_GET_BITSLICE(v_data_u8[BMG160_DATA_FRAME_Z_LSB_BYTE], + BMG160_RATE_Z_LSB_BIT); + data->dataz = (s16) + ((((s32)((s8)v_data_u8[BMG160_DATA_FRAME_Z_MSB_BYTE])) + << BMG160_SHIFT_BIT_POSITION_BY_08_BITS) | + (v_data_u8[BMG160_DATA_FRAME_Z_LSB_BYTE])); + } + return comres; +} +/*! + * @brief Reads data X,Y,Z and Interrupts + * from register location 0x02 to 0x07 + * + * + * @param data: The value of gyro xyz axis data and interrupt status + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_data_XYZI(struct bmg160_data_t *data) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + /*Array holding the gyro data xyz LSB and MSB data + v_data_u8[0] - X LSB + v_data_u8[1] - X MSB + v_data_u8[2] - Y MSB + v_data_u8[3] - Y MSB + v_data_u8[4] - Z MSB + v_data_u8[5] - Z MSB + v_data_u8[6] - INVALID + v_data_u8[7] - INTR STATUS1 + v_data_u8[8] - INTR STATUS2 + v_data_u8[9] - INTR STATUS3 + v_data_u8[10] - INTR STATUS4 + v_data_u8[11] - INTR STATUS5 + */ + u8 v_data_u8[BMG160_XYZ_INTR_DATA_SIZE] = + { + BMG160_INIT_VALUE, BMG160_INIT_VALUE, + BMG160_INIT_VALUE, BMG160_INIT_VALUE, + BMG160_INIT_VALUE, BMG160_INIT_VALUE, + BMG160_INIT_VALUE, BMG160_INIT_VALUE, + BMG160_INIT_VALUE, BMG160_INIT_VALUE, + BMG160_INIT_VALUE, BMG160_INIT_VALUE + }; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_RATE_X_LSB_BIT__REG, v_data_u8, + BMG160_XYZ_AND_INTR_DATA_LENGTH); + /* Data X */ + v_data_u8[BMG160_DATA_FRAME_X_LSB_BYTE] = + BMG160_GET_BITSLICE(v_data_u8[BMG160_DATA_FRAME_X_LSB_BYTE], + BMG160_RATE_X_LSB_BIT); + data->datax = (s16) + ((((s32)((s8)v_data_u8[BMG160_DATA_FRAME_X_MSB_BYTE])) + << BMG160_SHIFT_BIT_POSITION_BY_08_BITS) | + (v_data_u8[BMG160_DATA_FRAME_X_LSB_BYTE])); + /* Data Y */ + v_data_u8[BMG160_DATA_FRAME_Y_LSB_BYTE] = + BMG160_GET_BITSLICE(v_data_u8[BMG160_DATA_FRAME_Y_LSB_BYTE], + BMG160_RATE_Y_LSB_BIT); + data->datay = (s16) + ((((s32)((s8)v_data_u8[BMG160_DATA_FRAME_Y_MSB_BYTE])) + << BMG160_SHIFT_BIT_POSITION_BY_08_BITS) | + (v_data_u8[BMG160_DATA_FRAME_Y_LSB_BYTE])); + /* Data Z */ + v_data_u8[BMG160_DATA_FRAME_Z_LSB_BYTE] = + BMG160_GET_BITSLICE(v_data_u8[BMG160_DATA_FRAME_Z_LSB_BYTE], + BMG160_RATE_Z_LSB_BIT); + data->dataz = (s16) + ((((s32)((s8)v_data_u8[BMG160_DATA_FRAME_Z_MSB_BYTE])) + << BMG160_SHIFT_BIT_POSITION_BY_08_BITS) | + (v_data_u8[BMG160_DATA_FRAME_Z_LSB_BYTE])); + /* interrupt*/ + data->intstatus[BMG160_INTR0_STAT] = + v_data_u8[BMG160_DATA_FRAME_INTR0_BYTE]; + data->intstatus[BMG160_INTR1_STAT] = + v_data_u8[BMG160_DATA_FRAME_INTR1_BYTE]; + data->intstatus[BMG160_INTR2_STAT] = + v_data_u8[BMG160_DATA_FRAME_INTR2_BYTE]; + data->intstatus[BMG160_INTR3_STAT] = + v_data_u8[BMG160_DATA_FRAME_INTR3_BYTE]; + data->intstatus[BMG160_INTR4_STAT] = + v_data_u8[BMG160_DATA_FRAME_INTR4_BYTE]; + } + return comres; +} +/*! + * @brief Reads Temperature from register location 0x08 + * + * + * + * + * @param v_temp_s8: The value of temperature + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_temp(s8 *v_temp_s8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read temperature data*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_TEMP_ADDR, &v_data_u8, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_temp_s8 = v_data_u8; + } + return comres; +} +/*! + * @brief + * This API reads the data from + * the given register + * + * + * @param v_addr_u8 -> Address of the register + * @param v_data_u8 -> The data from the register + * @param v_len_u8 -> no of bytes to read + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMG160_RETURN_FUNCTION_TYPE bmg160_read_register(u8 v_addr_u8, + u8 *v_data_u8, u8 v_len_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, v_addr_u8, v_data_u8, v_len_u8); + } + return comres; +} +/*! + * @brief + * This API reads the data from + * the given register + * + * + * @param v_addr_u8 -> Address of the register + * @param v_data_u8 -> The data from the register + * @param v_len_u32 -> no of bytes to read + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMG160_RETURN_FUNCTION_TYPE bmg160_burst_read(u8 v_addr_u8, + u8 *v_data_u8, u32 v_len_u32) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + comres = p_bmg160->BMG160_BURST_READ_FUNC(p_bmg160->dev_addr, + v_addr_u8, v_data_u8, v_len_u32); + } + return comres; +} +/*! + * @brief + * This API write the data to + * the given register + * + * + * @param v_addr_u8 -> Address of the register + * @param v_data_u8 -> The data from the register + * @param v_len_u8 -> no of bytes to read + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMG160_RETURN_FUNCTION_TYPE bmg160_write_register(u8 v_addr_u8, + u8 *v_data_u8, u8 v_len_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + comres = p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, v_addr_u8, v_data_u8, v_len_u8); + } + return comres; +} +/*! + * @brief This api used to reads interrupt status of + * any motion and high rate in the register 0x09 + * @note any motion bit -> 2 + * @note high rate bit -> 1 + * + * + * + * @param v_stat0_data_u8 : The interrupt status of + * any motion and high rate + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_intr_stat_reg_zero( + u8 *v_stat0_data_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read the interrupt status any motion and high rate*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_STAT_ZERO__REG, &v_data_u8, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_stat0_data_u8 = + BMG160_GET_BITSLICE(v_data_u8, BMG160_INTR_STAT_ZERO); + } + return comres; +} +/*! + * @brief This api used to reads the interrupt status of + * data, auto_offset, fast_offset and fifo_int in the register 0x0A + * @note data bit -> 7 + * @note auto_offset bit -> 6 + * @note fast_offset bit -> 5 + * @note fifo_int bit -> 4 + * + * + * + * @param + * v_stat1_data_u8 : The interrupt status of + * data, auto_offset, fast_offset and fifo_int + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_intr_stat_reg_one( + u8 *v_stat1_data_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read the interrupt status*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, BMG160_INTR_STAT_ONE__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_stat1_data_u8 = + BMG160_GET_BITSLICE(v_data_u8, BMG160_INTR_STAT_ONE); + } + return comres; +} +/*! + * @brief This api used to reads the interrupt status of + * @note any motion sign, any motion first_z, any motion + * first_x and any motion first_y in the register 0x0B + * @note any motion sign bit -> 3 + * @note any motion first_z bit -> 2 + * @note any motion first_x bit -> 1 + * @note any motion first_y bit -> 0 + * + * + * + * @param + * v_stat2_data_u8 : Pointer holding the the interrupt status of + * any motion sign, any motion first_z, + * any motion first_x and any motion first_y + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_intr_stat_reg_two( + u8 *v_stat2_data_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read the interrupt status */ + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_STAT_TWO__REG, &v_data_u8, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_stat2_data_u8 = + BMG160_GET_BITSLICE(v_data_u8, BMG160_INTR_STAT_TWO); + } + return comres; +} +/*! +* @brief This api used to reads the interrupt status of +* high_rate sign, high_rate first_z, high_rate first_x +* and high_rate first_y in the register 0x0C +* @note high_rate sign bit -> 3 +* @note high_rate first_z bit -> 2 +* @note high_rate first_x bit -> 1 +* @note high_rate first_y bit -> 0 +* @note high_rate first_y bit -> 0 +* +* +* +* @param +* v_stat3_data_u8 : The interrupt status of +* high_rate sign, high_rate first_z, +* high_rate first_x and high_rate first_y +* +* +* @return results of bus communication function +* @retval 0 -> Success +* @retval -1 -> Error +* +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_intr_stat_reg_three( + u8 *v_stat3_data_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read the interrupt status */ + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_STAT_THREE__REG, &v_data_u8, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_stat3_data_u8 = + BMG160_GET_BITSLICE(v_data_u8, BMG160_INTR_STAT_THREE); + } + return comres; +} +/*! + * @brief This API is used to get + * the range in the register 0x0F bits from 0 to 2 + * + * @param v_range_u8 : The value of gyro range + * value | range + * ----------|----------- + * 0x00 | BMG160_RANGE_2000 + * 0x01 | BMG160_RANGE_1000 + * 0x02 | BMG160_RANGE_500 + * 0x03 | BMG160_RANGE_250 + * 0x04 | BMG160_RANGE_125 + * + * + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_range_reg(u8 *v_range_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read the gyro range */ + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_RANGE_ADDR_RANGE__REG, &v_data_u8, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_range_u8 = + BMG160_GET_BITSLICE(v_data_u8, BMG160_RANGE_ADDR_RANGE); + } + return comres; +} +/*! + * @brief This API is used to set + * the range in the register 0x0F bits from 0 to 2 + * + * @param v_range_u8 : The value of gyro range + * value | range + * ----------|----------- + * 0x00 | BMG160_RANGE_2000 + * 0x01 | BMG160_RANGE_1000 + * 0x02 | BMG160_RANGE_500 + * 0x03 | BMG160_RANGE_250 + * 0x04 | BMG160_RANGE_125 + * + * + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_range_reg(u8 v_range_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + if (v_range_u8 < BMG160_BIT_LENGTH_RANGE) + { + /* write the range*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_RANGE_ADDR_RANGE__REG, &v_data_u8, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_RANGE_ADDR_RANGE, + v_range_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_RANGE_ADDR_RANGE__REG, &v_data_u8, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + } + else + { + comres = E_BMG160_OUT_OF_RANGE; + } + } + return comres; +} +/*! + * @brief This API is used to get the gyro bandwidth + * in the register 0x10 bits from 0 to 3 + * + * + * + * + * + * @param v_bw_u8: The value of gyro bandwidth + * value | bandwidth + * ---------|--------------- + * 0x00 | BMG160_BW_500_HZ + * 0x01 | BMG160_BW_230_HZ + * 0x02 | BMG160_BW_116_HZ + * 0x03 | BMG160_BW_47_HZ + * 0x04 | BMG160_BW_23_HZ + * 0x05 | BMG160_BW_12_HZ + * 0x06 | BMG160_BW_64_HZ + * 0x07 | BMG160_BW_32_HZ + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_bw(u8 *v_bw_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read gyro bandwidth*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, BMG160_BW_ADDR__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_bw_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_BW_ADDR); + } + return comres; +} +/*! + * @brief This API is used to set the gyro bandwidth + * in the register 0x10 bits from 0 to 3 + * + * + * + * + * + * @param v_bw_u8: The value of gyro bandwidth + * value | bandwidth + * ---------|--------------- + * 0x00 | BMG160_BW_500_HZ + * 0x01 | BMG160_BW_230_HZ + * 0x02 | BMG160_BW_116_HZ + * 0x03 | BMG160_BW_47_HZ + * 0x04 | BMG160_BW_23_HZ + * 0x05 | BMG160_BW_12_HZ + * 0x06 | BMG160_BW_64_HZ + * 0x07 | BMG160_BW_32_HZ + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_bw(u8 v_bw_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + u8 v_mode_u8r = BMG160_INIT_VALUE; + u8 v_auto_sleep_dur = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + if (v_bw_u8 < BMG160_BIT_LENGTH_BW) + { + comres = bmg160_get_power_mode(&v_mode_u8r); + if (v_mode_u8r == BMG160_MODE_ADVANCEDPOWERSAVING) + { + /* check the advance power save mode */ + comres = bmg160_get_auto_sleep_durn( + &v_auto_sleep_dur); + comres = bmg160_set_auto_sleep_durn( + v_auto_sleep_dur, + v_bw_u8); + } + /* read gyro bandwidth*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_BW_ADDR__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_BW_ADDR, v_bw_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_BW_ADDR__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + } + else + { + comres = E_BMG160_OUT_OF_RANGE; + } + } + return comres; +} +/*! + * @brief This API used to get the status of + * External Trigger selection in the register 0x12h bits from 4 to 5 + * + * + * + * + * @param v_pwu_ext_tri_select_u8 : The value of External Trigger selection + * v_pwu_ext_tri_select_u8 | Trigger source + * --------------------------|------------------------- + * 0x00 | No + * 0x01 | INT1 pin + * 0x02 | INT2 pin + * 0x03 | SDO pin(SPI3 mode) + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_pmu_ext_tri_select( + u8 *v_pwu_ext_tri_select_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* READ PMU TRIGGER*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_MODE_LPM2_ADDR_EXT_TRI_SELECT__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_pwu_ext_tri_select_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_MODE_LPM2_ADDR_EXT_TRI_SELECT); + } + return comres; +} +/*! + * @brief This API used to set the status of + * External Trigger selection in the register 0x12h bits from 4 to 5 + * + * + * + * + * @param v_pwu_ext_tri_select_u8 : The value of External Trigger selection + * v_pwu_ext_tri_select_u8 | Trigger source + * --------------------------|------------------------- + * 0x00 | No + * 0x01 | INT1 pin + * 0x02 | INT2 pin + * 0x03 | SDO pin(SPI3 mode) + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_pmu_ext_tri_select( + u8 v_pwu_ext_tri_select_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* WRITE PMU TRIGGER*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_MODE_LPM2_ADDR_EXT_TRI_SELECT__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_MODE_LPM2_ADDR_EXT_TRI_SELECT, v_pwu_ext_tri_select_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC(p_bmg160->dev_addr, + BMG160_MODE_LPM2_ADDR_EXT_TRI_SELECT__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + } + return comres; +} +/*! + * @brief This API is used to get data high bandwidth + * in the register 0x13 bit 7 + * + * + * + * @param v_high_bw_u8 : The value of high bandwidth + * value | Description + * ---------|-------------- + * 1 | unfiltered + * 0 | filtered + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_high_bw(u8 *v_high_bw_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read high bandwidth*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_HIGH_BW__REG, &v_data_u8, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_high_bw_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_HIGH_BW); + } + return comres; +} +/*! + * @brief This API is used to set data high bandwidth + * in the register 0x13 bit 7 + * + * + * + * @param v_high_bw_u8 : The value of high bandwidth + * value | Description + * ---------|-------------- + * 1 | unfiltered + * 0 | filtered + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_high_bw(u8 v_high_bw_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + if (v_high_bw_u8 < BMG160_BIT_LENGTH_HIGH_BW) + { + /* write high bandwidth*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_HIGH_BW__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_HIGH_BW, v_high_bw_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_HIGH_BW__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + } + else + { + comres = E_BMG160_OUT_OF_RANGE; + } + } + return comres; +} +/*! + * @brief This API is used to get the shadow dis + * in the register 0x13 bit 6 + * + * + * + * @param v_shadow_dis_u8 : The value of shadow dis + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_shadow_dis(u8 *v_shadow_dis_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read shadow dis*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_SHADOW_DIS__REG, &v_data_u8, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_shadow_dis_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_SHADOW_DIS); + } + return comres; +} +/*! + * @brief This API is used to set the shadow dis + * in the register 0x13 bit 6 + * + * + * + * @param v_shadow_dis_u8 : The value of shadow dis + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_shadow_dis(u8 v_shadow_dis_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + if (v_shadow_dis_u8 < BMG160_BIT_LENGTH_SHADOW_DIS) + { + /* write shadow dis*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_SHADOW_DIS__REG, &v_data_u8, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_SHADOW_DIS, v_shadow_dis_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_SHADOW_DIS__REG, &v_data_u8, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + } + else + { + comres = E_BMG160_OUT_OF_RANGE; + } + } + return comres; +} +/*! + * This function is used for the soft reset + * The soft reset register will be written with 0xB6 in the register 0x14. + * + * + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_soft_rst(void) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_soft_rst_u8 = BMG160_INIT_VALUE; + + v_soft_rst_u8 = BMG160_SOFT_RESET; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* write soft reset*/ + comres = p_bmg160->BMG160_BUS_WRITE_FUNC(p_bmg160->dev_addr, + BMG160_BGW_SOFT_RST_ADDR, &v_soft_rst_u8, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + } + return comres; +} +/*! + * @brief This API is used to get the data(data_enable) + * interrupt enable bits of the sensor in the registers 0x15 bit 7 + * + * + * + * + * @param v_data_enable_u8 : The value of data enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_data_enable(u8 *v_data_enable_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read the data enable interrupt */ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_INTR_ENABLE0_DATA__REG, &v_data_u8, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_data_enable_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_INTR_ENABLE0_DATA); + } + return comres; +} +/*! + * @brief This API is used to set the data(data_enable) + * interrupt enable bits of the sensor in the registers 0x15 bit 7 + * + * + * + * + * @param v_data_enable_u8 : The value of data enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_data_enable(u8 v_data_enable_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* write the data enable interrupt*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_ENABLE0_DATA__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_INTR_ENABLE0_DATA, v_data_enable_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_ENABLE0_DATA__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + } + return comres; +} +/*! + * @brief This API is used to get the fifo(fifo_enable) + * interrupt enable bits of the sensor in the registers 0x15 bit 6 + * + * + * + * + * @param v_fifo_enable_u8 : The value of fifo enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_fifo_enable(u8 *v_fifo_enable_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read the fifo enable */ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_INTR_ENABLE0_FIFO__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_fifo_enable_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_INTR_ENABLE0_FIFO); + } + return comres; +} +/*! + * @brief This API is used to set the fifo(fifo_enable) + * interrupt enable bits of the sensor in the registers 0x15 bit 6 + * + * + * + * + * @param v_fifo_enable_u8 : The value of fifo enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_fifo_enable(u8 v_fifo_enable_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + if (v_fifo_enable_u8 < BMG160_BIT_LENGTH_FIFO) + { + /* write the fifo enable */ + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_ENABLE0_FIFO__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_INTR_ENABLE0_FIFO, v_fifo_enable_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_ENABLE0_FIFO__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + } + else + { + comres = E_BMG160_OUT_OF_RANGE; + } + } + return comres; +} +/*! + * @brief This API is used to get + * the auto offset(auto_offset_enable) interrupt enable bits of + * the sensor in the registers 0x15 bit 3 + * + * + * + * @param v_offset_enable_u8 : The value of offset enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_auto_offset_enable( + u8 *v_offset_enable_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read auto offset*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_INTR_ENABLE0_AUTO_OFFSET__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_offset_enable_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_INTR_ENABLE0_AUTO_OFFSET); + } + return comres; +} +/*! + * @brief This API is used to set + * the auto offset(auto_offset_enable) interrupt enable bits of + * the sensor in the registers 0x15 bit 3 + * + * + * + * @param v_offset_enable_u8 : The value of offset enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_auto_offset_enable(u8 v_offset_enable_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* write auto offset */ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_INTR_ENABLE0_AUTO_OFFSET__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_INTR_ENABLE0_AUTO_OFFSET, v_offset_enable_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC(p_bmg160->dev_addr, + BMG160_INTR_ENABLE0_AUTO_OFFSET__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + } + return comres; +} +/*! + * @brief This API is used to get + * the output type status in the register 0x16. + * @note INT1 -> bit 1 + * @note INT2 -> bit 3 + * + * @param v_param_u8: The value of output type selection number + * v_param_u8| output type + * ------------|-------------- + * 0 | BMG160_INTR1 + * 1 | BMG160_INTR2 + * + * @param v_intr_output_type_u8: The value of output type + * value | output + * -----------|------------- + * 1 | open drain + * 0 | push pull + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_intr_output_type(u8 v_param_u8, + u8 *v_intr_output_type_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + switch (v_param_u8) + { + /* read output type*/ + case BMG160_INTR1: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_ENABLE1_IT1_OUTPUT_TYPE__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_intr_output_type_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_INTR_ENABLE1_IT1_OUTPUT_TYPE); + break; + case BMG160_INTR2: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_ENABLE1_IT2_OUTPUT_TYPE__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_intr_output_type_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_INTR_ENABLE1_IT2_OUTPUT_TYPE); + break; + default: + comres = E_BMG160_OUT_OF_RANGE; + break; + } + } + return comres; +} +/*! + * @brief This API is used to set + * the output type status in the register 0x16. + * @note INT1 -> bit 1 + * @note INT2 -> bit 3 + * + * @param v_param_u8: The value of output type selection number + * v_param_u8| output type + * ------------|-------------- + * 0 | BMG160_INTR1 + * 1 | BMG160_INTR2 + * + * @param v_intr_output_type_u8: The value of output type + * value | output + * -----------|------------- + * 1 | open drain + * 0 | push pull + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_intr_output_type(u8 v_param_u8, + u8 v_intr_output_type_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + switch (v_param_u8) + { + /* write output type*/ + case BMG160_INTR1: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_ENABLE1_IT1_OUTPUT_TYPE__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_INTR_ENABLE1_IT1_OUTPUT_TYPE, + v_intr_output_type_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_ENABLE1_IT1_OUTPUT_TYPE__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + case BMG160_INTR2: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_ENABLE1_IT2_OUTPUT_TYPE__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_INTR_ENABLE1_IT2_OUTPUT_TYPE, + v_intr_output_type_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_ENABLE1_IT2_OUTPUT_TYPE__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + default: + comres = E_BMG160_OUT_OF_RANGE; + break; + } + } + return comres; +} +/*! + * @brief This API is used to get + * Active Level status in the register 0x16 + * @note INT1 -> bit 0 + * @note INT2 -> bit 2 + * + * @param v_param_u8: The value of Active Level selection number + * v_param_u8| Active Level + * ------------|-------------- + * 0 | BMG160_INTR1 + * 1 | BMG160_INTR2 + * + * @param v_intr_level_u8: The value of Active Level status value + * value | Active Level + * -----------|------------- + * 1 | Active HIGH + * 0 | Active LOW + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_intr_level(u8 v_param_u8, + u8 *v_intr_level_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + switch (v_param_u8) + { + /* read active level*/ + case BMG160_INTR1: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_ENABLE1_IT1_LEVEL__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_intr_level_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_INTR_ENABLE1_IT1_LEVEL); + break; + case BMG160_INTR2: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_ENABLE1_IT2_LEVEL__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_intr_level_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_INTR_ENABLE1_IT2_LEVEL); + break; + default: + comres = E_BMG160_OUT_OF_RANGE; + break; + } + } + return comres; +} +/*! + * @brief This API is used to set + * Active Level status in the register 0x16 + * @note INT1 -> bit 0 + * @note INT2 -> bit 2 + * + * @param v_param_u8: The value of Active Level selection number + * v_param_u8| Active Level + * ------------|-------------- + * 0 | BMG160_INTR1 + * 1 | BMG160_INTR2 + * + * @param v_intr_level_u8: The value of Active Level status value + * value | Active Level + * -----------|------------- + * 1 | Active HIGH + * 0 | Active LOW + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_intr_level(u8 v_param_u8, + u8 v_intr_level_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + switch (v_param_u8) + { + /* write active level*/ + case BMG160_INTR1: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_ENABLE1_IT1_LEVEL__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_INTR_ENABLE1_IT1_LEVEL, v_intr_level_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_ENABLE1_IT1_LEVEL__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + case BMG160_INTR2: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_ENABLE1_IT2_LEVEL__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_INTR_ENABLE1_IT2_LEVEL, v_intr_level_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_ENABLE1_IT2_LEVEL__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + default: + comres = E_BMG160_OUT_OF_RANGE; + break; + } + } + return comres; +} +/*! + * @brief This API is used to get + * the high rate(int1_high) interrupt1 enable bits of + * the sensor in the registers 0x17 bit 3 + * + * + * + * @param v_intr1_u8 : The value of interrupt1 high_rate enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_intr1_highrate(u8 *v_intr1_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read high_rate enable */ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_INTR_MAP_ZERO_INTR1_HIGHRATE__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_intr1_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_INTR_MAP_ZERO_INTR1_HIGHRATE); + } + return comres; +} +/*! + * @brief This API is used to set + * the high rate(int1_high) interrupt1 enable bits of + * the sensor in the registers 0x17 bit 3 + * + * + * + * @param v_intr1_u8 : The value of interrupt1 high_rate enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_intr1_highrate( + u8 v_intr1_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* write high_rate enable */ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_INTR_MAP_ZERO_INTR1_HIGHRATE__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_INTR_MAP_ZERO_INTR1_HIGHRATE, v_intr1_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC(p_bmg160->dev_addr, + BMG160_INTR_MAP_ZERO_INTR1_HIGHRATE__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + } + return comres; +} +/*! + * @brief This API is used to get + * the any motion(int1_any) interrupt1 enable bits of + * the sensor in the registers 0x17 bit 1 + * + * + * + * @param v_int1r_any_motion_u8 : The value of any motion interrupt1 + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_intr1_any_motion( + u8 *v_int1r_any_motion_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read any motion interrupt*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_INTR_MAP_ZERO_INTR1_ANY_MOTION__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_int1r_any_motion_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_INTR_MAP_ZERO_INTR1_ANY_MOTION); + } + return comres; +} +/*! + * @brief This API is used to set + * the any motion(int1_any) interrupt1 enable bits of + * the sensor in the registers 0x17 bit 1 + * + * + * + * @param v_int1r_any_motion_u8 : The value of any motion interrupt1 + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_intr1_any_motion( + u8 v_int1r_any_motion_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* write any motion interrupt */ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_INTR_MAP_ZERO_INTR1_ANY_MOTION__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_INTR_MAP_ZERO_INTR1_ANY_MOTION, v_int1r_any_motion_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC(p_bmg160->dev_addr, + BMG160_INTR_MAP_ZERO_INTR1_ANY_MOTION__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + } + return comres; +} +/*! + * @brief This API is used to get + * the data interrupt1 and interrupt2(int1_data and int2_data) + * in the register 0x18 + * @note INT1 -> bit 0 + * @note INT2 -> bit 7 + * + * @param v_axis_u8: data interrupt selection + * v_axis_u8 | Data interrupt + * ------------|-------------- + * 0 | BMG160_INTR1_DATA + * 1 | BMG160_INTR2_DATA + * + * @param v_intr_data_u8: The value of data interrupt1 or interrupt2 + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_intr_data(u8 v_axis_u8, + u8 *v_intr_data_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + switch (v_axis_u8) + { + /* read data interrupt */ + case BMG160_INTR1_DATA: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_MAP_ONE_INTR1_DATA__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_intr_data_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_MAP_ONE_INTR1_DATA); + break; + case BMG160_INTR2_DATA: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_MAP_ONE_INTR2_DATA__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_intr_data_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_MAP_ONE_INTR2_DATA); + break; + default: + comres = E_BMG160_OUT_OF_RANGE; + break; + } + } + return comres; +} +/*! + * @brief This API is used to set + * the data interrupt1 and interrupt2(int1_data and int2_data) + * in the register 0x18 + * @note INT1 -> bit 0 + * @note INT2 -> bit 7 + * + * @param v_axis_u8: data interrupt selection + * v_axis_u8 | Data interrupt + * ------------|-------------- + * 0 | BMG160_INTR1_DATA + * 1 | BMG160_INTR2_DATA + * + * @param v_intr_data_u8: The value of data interrupt1 or interrupt2 + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_intr_data(u8 v_axis_u8, + u8 v_intr_data_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + switch (v_axis_u8) + { + /* write data interrupt*/ + case BMG160_INTR1_DATA: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_MAP_ONE_INTR1_DATA__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_MAP_ONE_INTR1_DATA, v_intr_data_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_MAP_ONE_INTR1_DATA__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + case BMG160_INTR2_DATA: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_MAP_ONE_INTR2_DATA__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_MAP_ONE_INTR2_DATA, v_intr_data_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_MAP_ONE_INTR2_DATA__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + default: + comres = E_BMG160_OUT_OF_RANGE; + break; + } + } + return comres; +} +/*! + * @brief This API is used to get + * the fast offset(intr2_fast_offset) and auto offset(intr2_auto_offset) + * of interrupt2 in the register 0x18 + * @note int2_fast_offset -> bit 6 + * @note int2_auto_offset -> bit 4 + * + * @param v_axis_u8: The value of fast/auto offset interrupts selection + * v_axis_u8 | Data interrupt + * ------------|-------------- + * 1 | BMG160_FAST_OFFSET + * 2 | BMG160_AUTO_OFFSET + * + * @param v_intr2_offset_u8: The value of fast/auto offset enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_intr2_offset(u8 v_axis_u8, + u8 *v_intr2_offset_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + switch (v_axis_u8) + { + /* read offset*/ + case BMG160_FAST_OFFSET: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_MAP_ONE_INTR2_FAST_OFFSET__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_intr2_offset_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_MAP_ONE_INTR2_FAST_OFFSET); + break; + case BMG160_AUTO_OFFSET: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_MAP_ONE_INTR2_AUTO_OFFSET__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_intr2_offset_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_MAP_ONE_INTR2_AUTO_OFFSET); + break; + default: + comres = E_BMG160_OUT_OF_RANGE; + break; + } + } + return comres; +} +/*! + * @brief This API is used to set + * the fast offset(intr2_fast_offset) and auto offset(intr2_auto_offset) + * of interrupt2 in the register 0x18 + * @note int2_fast_offset -> bit 6 + * @note int2_auto_offset -> bit 4 + * + * @param v_axis_u8: The value of fast/auto offset interrupts selection + * v_axis_u8 | Data interrupt + * ------------|-------------- + * 1 | BMG160_FAST_OFFSET + * 2 | BMG160_AUTO_OFFSET + * + * @param v_intr2_offset_u8: The value of fast/auto offset enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_intr2_offset(u8 v_axis_u8, + u8 v_intr2_offset_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + switch (v_axis_u8) + { + /* write offset */ + case BMG160_FAST_OFFSET: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_MAP_ONE_INTR2_FAST_OFFSET__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_MAP_ONE_INTR2_FAST_OFFSET, v_intr2_offset_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_MAP_ONE_INTR2_FAST_OFFSET__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + case BMG160_AUTO_OFFSET: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_MAP_ONE_INTR2_AUTO_OFFSET__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_MAP_ONE_INTR2_AUTO_OFFSET, v_intr2_offset_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_MAP_ONE_INTR2_AUTO_OFFSET__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + default: + comres = E_BMG160_OUT_OF_RANGE; + break; + } + } + return comres; +} +/*! + * @brief This API is used to get + * the fast offset(int1_fast_offset) and auto offset(int1_auto_offset) + * of interrupt1 in the register 0x18 + * @note int1_fast_offset -> bit 1 + * @note int1_auto_offset -> bit 3 + * + * @param v_axis_u8: The value of fast/auto offset interrupts selection + * v_axis_u8 | Data interrupt + * ------------|-------------- + * 1 | BMG160_FAST_OFFSET + * 2 | BMG160_AUTO_OFFSET + * + * @param v_intr1_offset_u8: The value of fast/auto offset + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_intr_offset(u8 v_axis_u8, + u8 *v_intr1_offset_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + switch (v_axis_u8) + { + /* read offset*/ + case BMG160_FAST_OFFSET: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_MAP_ONE_INTR1_FAST_OFFSET__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_intr1_offset_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_MAP_ONE_INTR1_FAST_OFFSET); + break; + case BMG160_AUTO_OFFSET: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_MAP_ONE_INTR1_AUTO_OFFSET__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_intr1_offset_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_MAP_ONE_INTR1_AUTO_OFFSET); + break; + default: + comres = E_BMG160_OUT_OF_RANGE; + break; + } + } + return comres; +} +/*! + * @brief This API is used to set + * the fast offset(int1_fast_offset) and auto offset(int1_auto_offset) + * of interrupt1 in the register 0x18 + * @note int1_fast_offset -> bit 1 + * @note int1_auto_offset -> bit 3 + * + * @param v_axis_u8: The value of fast/auto offset interrupts selection + * v_axis_u8 | Data interrupt + * ------------|-------------- + * 1 | BMG160_FAST_OFFSET + * 2 | BMG160_AUTO_OFFSET + * + * @param v_intr1_offset_u8: The value of fast/auto offset + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_intr1_offset(u8 v_axis_u8, + u8 v_intr1_offset_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + switch (v_axis_u8) + { + /* write offset */ + case BMG160_FAST_OFFSET: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_MAP_ONE_INTR1_FAST_OFFSET__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_MAP_ONE_INTR1_FAST_OFFSET, v_intr1_offset_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_MAP_ONE_INTR1_FAST_OFFSET__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + case BMG160_AUTO_OFFSET: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_MAP_ONE_INTR1_AUTO_OFFSET__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_MAP_ONE_INTR1_AUTO_OFFSET, v_intr1_offset_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_MAP_ONE_INTR1_AUTO_OFFSET__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + default: + comres = E_BMG160_OUT_OF_RANGE; + break; + } + } + return comres; +} +/*! + * @brief This API is used to get + * the fifo(int2_fifo) interrupt2 enable bits of + * the sensor in the registers 0x18 bit 5 + * + * + * + * @param v_intr_fifo_u8 : The interrupt2 fifo value + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_intr2_fifo(u8 *v_intr_fifo_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_MAP_ONE_INTR2_FIFO__REG, &v_data_u8, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_intr_fifo_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_MAP_ONE_INTR2_FIFO); + } + return comres; +} +/*! + * @brief This API is used to get + * the fifo(int1_fifo) interrupt1 enable bits of + * the sensor in the registers 0x18 bit 5 + * + * + * + * @param v_intr_fifo_u8 : The interrupt1 fifo value + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_intr1_fifo(u8 *v_intr_fifo_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read fifo interrupt */ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_MAP_ONE_INTR1_FIFO__REG, &v_data_u8, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_intr_fifo_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_MAP_ONE_INTR1_FIFO); + } + return comres; +} +/*! + * @brief This API is used to set the value of + * the fifo interrupt1 and interrupt2(int1_fifo and int2_fifo) + * in the register 0x18 + * @note int1_fifo -> bit 2 + * @note int2_fifo -> bit 5 + * + * @param v_axis_u8: The value of fifo interrupts selection + * v_axis_u8 | fifo interrupt + * ------------|-------------- + * 0 | BMG160_INTR1 + * 1 | BMG160_INTR2 + * + * @param v_intr_fifo_u8: the value of int1_fifo/int2_fifo enable/disable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_intr_fifo(u8 v_axis_u8, + u8 v_intr_fifo_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + switch (v_axis_u8) + { + /* write fifo interrupt */ + case BMG160_INTR1: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_MAP_ONE_INTR1_FIFO__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_MAP_ONE_INTR1_FIFO, v_intr_fifo_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_MAP_ONE_INTR1_FIFO__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + case BMG160_INTR2: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_MAP_ONE_INTR2_FIFO__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_MAP_ONE_INTR2_FIFO, v_intr_fifo_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_MAP_ONE_INTR2_FIFO__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + default: + comres = E_BMG160_OUT_OF_RANGE; + break; + } + } + return comres; +} +/*! + * @brief This API is used to get + * the high rate(int2_high_rate) interrupt2 enable bits of + * the sensor in the registers 0x19 bit 3 + * + * + * + * @param v_intr2_highrate_u8 : The interrupt2 high_rate value + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_intr2_highrate( + u8 *v_intr2_highrate_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read high rate interrupt*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_INTR_MAP_TWO_INTR2_HIGHRATE__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_intr2_highrate_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_INTR_MAP_TWO_INTR2_HIGHRATE); + } + return comres; +} +/*! + * @brief This API is used to set + * the high rate(int2_high_rate) interrupt2 enable bits of + * the sensor in the registers 0x19 bit 3 + * + * + * + * @param v_intr2_highrate_u8 : The interrupt2 high_rate value + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_intr2_highrate( + u8 v_intr2_highrate_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* write high rate interrupt */ + comres = p_bmg160->BMG160_BUS_READ_FUNC( + p_bmg160->dev_addr, + BMG160_INTR_MAP_TWO_INTR2_HIGHRATE__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_INTR_MAP_TWO_INTR2_HIGHRATE, v_intr2_highrate_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC(p_bmg160->dev_addr, + BMG160_INTR_MAP_TWO_INTR2_HIGHRATE__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + } + return comres; +} +/*! + * @brief This API is used to get + * the any motion(int2_any_motion) interrupt2 enable bits of + * the sensor in the registers 0x19 bit 1 + * + * + * + * @param v_intr2_any_motion_u8 : The value of interrupt2 any_motion + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_intr2_any_motion( + u8 *v_intr2_any_motion_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read any motion interrupt */ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_INTR_MAP_TWO_INTR2_ANY_MOTION__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_intr2_any_motion_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_INTR_MAP_TWO_INTR2_ANY_MOTION); + } + return comres; +} +/*! + * @brief This API is used to set + * the any motion(int2_any_motion) interrupt2 enable bits of + * the sensor in the registers 0x19 bit 1 + * + * + * + * @param v_intr2_any_motion_u8 : The value of interrupt2 any_motion + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_intr2_any_motion( + u8 v_intr2_any_motion_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* write any motion interrupt */ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_INTR_MAP_TWO_INTR2_ANY_MOTION__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_INTR_MAP_TWO_INTR2_ANY_MOTION, v_intr2_any_motion_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC(p_bmg160->dev_addr, + BMG160_INTR_MAP_TWO_INTR2_ANY_MOTION__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + } + return comres; +} +/*! + * @brief This API is used to get + * the slow offset and fast offset unfilt data in the register 0x1A and 1B + * @note slow_offset_unfilt -> 0x1A bit 5 + * @note fast_offset_unfilt -> 0x1B bit 7 + * + * @param v_param_u8: The value of fast/slow offset unfilt data selection + * v_param_u8 | offset selection + * ------------|-------------- + * 0 | BMG160_SLOW_OFFSET + * 1 | BMG160_FAST_OFFSET + * + * @param v_offset_unfilt_u8: The value of fast/slow offset unfilt data + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_offset_unfilt(u8 v_param_u8, + u8 *v_offset_unfilt_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + switch (v_param_u8) + { + /* read offset unfilt data */ + case BMG160_SLOW_OFFSET: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_ZERO_ADDR_SLOW_OFFSET_UNFILT__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_offset_unfilt_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_INTR_ZERO_ADDR_SLOW_OFFSET_UNFILT); + break; + case BMG160_FAST_OFFSET: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_ONE_ADDR_FAST_OFFSET_UNFILT__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_offset_unfilt_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_INTR_ONE_ADDR_FAST_OFFSET_UNFILT); + break; + default: + comres = E_BMG160_OUT_OF_RANGE; + break; + } + } + return comres; +} +/*! + * @brief This API is used to set + * the slow offset and fast offset unfilt data in the register 0x1A and 1B + * @note slow_offset_unfilt -> 0x1A bit 5 + * @note fast_offset_unfilt -> 0x1B bit 7 + * + * @param v_param_u8: The value of fast/slow offset unfilt data selection + * v_param_u8 | offset selection + * ------------|-------------- + * 0 | BMG160_SLOW_OFFSET + * 1 | BMG160_FAST_OFFSET + * + * @param v_offset_unfilt_u8: The value of fast/slow offset unfilt data + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_offset_unfilt(u8 v_param_u8, + u8 v_offset_unfilt_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + switch (v_param_u8) + { + /* write offset unfilt data */ + case BMG160_SLOW_OFFSET: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_ZERO_ADDR_SLOW_OFFSET_UNFILT__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_INTR_ZERO_ADDR_SLOW_OFFSET_UNFILT, + v_offset_unfilt_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_ZERO_ADDR_SLOW_OFFSET_UNFILT__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + case BMG160_FAST_OFFSET: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_ONE_ADDR_FAST_OFFSET_UNFILT__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_INTR_ONE_ADDR_FAST_OFFSET_UNFILT, + v_offset_unfilt_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_ONE_ADDR_FAST_OFFSET_UNFILT__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + default: + comres = E_BMG160_OUT_OF_RANGE; + break; + } + } + return comres; +} +/*! + * @brief This API is used to get + * the any motion and high rate unfilt data in the register 0x1A + * @note any_unfilt_data -> bit 1 + * @note high_unfilt_data -> bit 3 + * + * @param v_param_u8: The value of any/high offset unfilt data selection + * v_param_u8 | offset selection + * ------------|-------------- + * 1 | BMG160_HIGHRATE_UNFILT_DATA + * 3 | BMG160_ANY_MOTION_UNFILT_DATA + * + * @param v_unfilt_data_u8: The value of any/high unfilt data + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_unfilt_data(u8 v_param_u8, + u8 *v_unfilt_data_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + switch (v_param_u8) + { + /* read unfilt data */ + case BMG160_HIGHRATE_UNFILT_DATA: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_ZERO_ADDR_HIGHRATE_UNFILT_DATA__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_unfilt_data_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_INTR_ZERO_ADDR_HIGHRATE_UNFILT_DATA); + break; + case BMG160_ANY_MOTION_UNFILT_DATA: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_ZERO_ADDR_ANY_MOTION_UNFILT_DATA__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_unfilt_data_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_INTR_ZERO_ADDR_ANY_MOTION_UNFILT_DATA); + break; + default: + comres = E_BMG160_OUT_OF_RANGE; + break; + } + } + return comres; +} +/*! + * @brief This API is used to set + * the any motion and high rate unfilt data in the register 0x1A + * @note any_unfilt_data -> bit 1 + * @note high_unfilt_data -> bit 3 + * + * @param v_param_u8: The value of any/high offset unfilt data selection + * v_param_u8 | offset selection + * ------------|-------------- + * 1 | BMG160_HIGHRATE_UNFILT_DATA + * 3 | BMG160_ANY_MOTION_UNFILT_DATA + * + * @param v_unfilt_data_u8: The value of any/high unfilt data + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_unfilt_data(u8 v_param_u8, + u8 v_unfilt_data_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + switch (v_param_u8) + { + /* write unfilt data */ + case BMG160_HIGHRATE_UNFILT_DATA: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_ZERO_ADDR_HIGHRATE_UNFILT_DATA__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_INTR_ZERO_ADDR_HIGHRATE_UNFILT_DATA, + v_unfilt_data_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_ZERO_ADDR_HIGHRATE_UNFILT_DATA__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + case BMG160_ANY_MOTION_UNFILT_DATA: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_ZERO_ADDR_ANY_MOTION_UNFILT_DATA__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_INTR_ZERO_ADDR_ANY_MOTION_UNFILT_DATA, + v_unfilt_data_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_ZERO_ADDR_ANY_MOTION_UNFILT_DATA__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + default: + comres = E_BMG160_OUT_OF_RANGE; + break; + } + } + return comres; +} +/*! + * @brief This API is used to get Any motion Threshold + * in the register 0x1B bit from 0 to 6 + * + * + * + * @param v_any_motion_thres_u8 : The value of any_motion Threshold + * + * @note Any motion threshold can be calculate using + * @note ((1+ v_any_motion_thres_u8)*16LSB) + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_any_motion_thres( + u8 *v_any_motion_thres_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read any motion threshold */ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_INTR_ONE_ADDR_ANY_MOTION_THRES__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_any_motion_thres_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_INTR_ONE_ADDR_ANY_MOTION_THRES); + } + return comres; +} +/*! + * @brief This API is used to set Any motion Threshold + * in the register 0x1B bit from 0 to 6 + * + * + * + * @param v_any_motion_thres_u8 : The value of any_motion Threshold + * + * @note Any motion threshold can be calculate using + * @note ((1+ v_any_motion_thres_u8)*16LSB) + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_any_motion_thres( + u8 v_any_motion_thres_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* write any motion threshold*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_INTR_ONE_ADDR_ANY_MOTION_THRES__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_INTR_ONE_ADDR_ANY_MOTION_THRES, v_any_motion_thres_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC(p_bmg160->dev_addr, + BMG160_INTR_ONE_ADDR_ANY_MOTION_THRES__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + } + return comres; +} +/*! + * @brief This API is used to get the awake Duration + * in the register 0x1C bit 6 and 7 + * + * + * + * @param v_awake_durn_u8 : The value of awake Duration + * value | Duration + * ---------|----------- + * 0x00 | 8 samples + * 0x01 | 16 samples + * 0x02 | 32 samples + * 0x03 | 64 samples + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_awake_durn(u8 *v_awake_durn_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read awake duration*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_INTR_TWO_ADDR_AWAKE_DURN__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_awake_durn_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_INTR_TWO_ADDR_AWAKE_DURN); + } + return comres; +} +/*! + * @brief This API is used to set the awake Duration + * in the register 0x1C bit 6 and 7 + * + * + * + * @param v_awake_durn_u8 : The value of awake Duration + * value | Duration + * ---------|----------- + * 0x00 | 8 samples + * 0x01 | 16 samples + * 0x02 | 32 samples + * 0x03 | 64 samples + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_awake_durn(u8 v_awake_durn_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* write awake duration*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_INTR_TWO_ADDR_AWAKE_DURN__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_INTR_TWO_ADDR_AWAKE_DURN, v_awake_durn_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC(p_bmg160->dev_addr, + BMG160_INTR_TWO_ADDR_AWAKE_DURN__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + } + return comres; +} +/*! + * @brief This API is used to get + * the any motion Duration samples in the register 0x1C bit 4 and 5 + * + * + * + * @param v_durn_sample_u8 : The value of any motion duration samples + * value | Samples + * ---------|----------- + * 0x00 | 4 samples + * 0x01 | 8 samples + * 0x02 | 12 samples + * 0x03 | 16 samples + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_any_motion_durn_sample( + u8 *v_durn_sample_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read any motion awake samples*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_INTR_TWO_ADDR_ANY_MOTION_DURN_SAMPLE__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_durn_sample_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_INTR_TWO_ADDR_ANY_MOTION_DURN_SAMPLE); + } + return comres; +} +/*! + * @brief This API is used to set + * the any motion Duration samples in the register 0x1C bit 4 and 5 + * + * + * + * @param v_durn_sample_u8 : The value of any motion duration samples + * value | Samples + * ---------|----------- + * 0x00 | 4 samples + * 0x01 | 8 samples + * 0x02 | 12 samples + * 0x03 | 16 samples + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_any_motion_durn_sample( + u8 v_durn_sample_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* write awake duration samples*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_INTR_TWO_ADDR_ANY_MOTION_DURN_SAMPLE__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_INTR_TWO_ADDR_ANY_MOTION_DURN_SAMPLE, + v_durn_sample_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC( + p_bmg160->dev_addr, + BMG160_INTR_TWO_ADDR_ANY_MOTION_DURN_SAMPLE__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + } + return comres; +} +/*! + * @brief This API is used to get the status of + * Any motion interrupt axis(X,Y,Z) enable channel + * @note BMG160_X_AXIS -> bit 0 + * @note BMG160_Y_AXIS -> bit 1 + * @note BMG160_Z_AXIS -> bit 2 + * + * @param v_channel_u8 : The value of Any Enable channel number + * v_channel_u8 | axis + * --------------|-------------- + * 0 | BMG160_X_AXIS + * 1 | BMG160_Y_AXIS + * 2 | BMG160_Z_AXIS + * + * @param v_data_u8: The value of Any motion axis enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_any_motion_enable_axis(u8 v_channel_u8, + u8 *v_any_motion_axis_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data1_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + switch (v_channel_u8) + { + /* read any motion axis enable*/ + case BMG160_X_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_TWO_ADDR_ANY_MOTION_ENABLE_X__REG, + &v_data1_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_any_motion_axis_u8 = BMG160_GET_BITSLICE(v_data1_u8, + BMG160_INTR_TWO_ADDR_ANY_MOTION_ENABLE_X); + break; + case BMG160_Y_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_TWO_ADDR_ANY_MOTION_ENABLE_Y__REG, + &v_data1_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_any_motion_axis_u8 = BMG160_GET_BITSLICE(v_data1_u8, + BMG160_INTR_TWO_ADDR_ANY_MOTION_ENABLE_Y); + break; + case BMG160_Z_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_TWO_ADDR_ANY_MOTION_ENABLE_Z__REG, + &v_data1_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_any_motion_axis_u8 = BMG160_GET_BITSLICE(v_data1_u8, + BMG160_INTR_TWO_ADDR_ANY_MOTION_ENABLE_Z); + break; + default: + comres = E_BMG160_OUT_OF_RANGE; + break; + } + } + return comres; +} +/*! + * @brief This API is used to set the status of + * Any motion interrupt axis(X,Y,Z) enable channel + * @note BMG160_X_AXIS -> bit 0 + * @note BMG160_Y_AXIS -> bit 1 + * @note BMG160_Z_AXIS -> bit 2 + * + * @param v_channel_u8 : The value of Any Enable channel number + * v_channel_u8 | axis + * --------------|-------------- + * 0 | BMG160_X_AXIS + * 1 | BMG160_Y_AXIS + * 2 | BMG160_Z_AXIS + * + * @param v_any_motion_axis_u8: The value of Any motion axis enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_any_motion_enable_axis(u8 v_channel_u8, + u8 v_any_motion_axis_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + switch (v_channel_u8) + { + /* write any motion axis enable*/ + case BMG160_X_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_TWO_ADDR_ANY_MOTION_ENABLE_X__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_INTR_TWO_ADDR_ANY_MOTION_ENABLE_X, + v_any_motion_axis_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_TWO_ADDR_ANY_MOTION_ENABLE_X__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + case BMG160_Y_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_TWO_ADDR_ANY_MOTION_ENABLE_Y__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_INTR_TWO_ADDR_ANY_MOTION_ENABLE_Y, + v_any_motion_axis_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_TWO_ADDR_ANY_MOTION_ENABLE_Y__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + case BMG160_Z_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_TWO_ADDR_ANY_MOTION_ENABLE_Z__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_INTR_TWO_ADDR_ANY_MOTION_ENABLE_Z, + v_any_motion_axis_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_TWO_ADDR_ANY_MOTION_ENABLE_Z__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + default: + comres = E_BMG160_OUT_OF_RANGE; + break; + } + } + return comres; +} +/*! + * @brief This API is used to get + * the status of fifo water mark in the register 0x1E bit 7 + * + * + * + * @param v_fifo_wm_enable_u8 : The value of fifo water mark enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_fifo_wm_enable( + u8 *v_fifo_wm_enable_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read fifo water mark enable */ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_INTR_4_FIFO_WM_ENABLE__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_fifo_wm_enable_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_INTR_4_FIFO_WM_ENABLE); + } + return comres; +} +/*! + * @brief This API is used to set + * the status of fifo water mark in the register 0x1E bit 7 + * + * + * + * @param v_fifo_wm_enable_u8 : The value of fifo water mark enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_fifo_wm_enable( + u8 v_fifo_wm_enable_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* write fifo water mark enable*/ + if (v_fifo_wm_enable_u8 < BMG160_BIT_LENGTH_FIFO_WM) + { + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_4_FIFO_WM_ENABLE__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_INTR_4_FIFO_WM_ENABLE, v_fifo_wm_enable_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_INTR_4_FIFO_WM_ENABLE__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + } + else + { + comres = E_BMG160_OUT_OF_RANGE; + } + } + return comres; +} +/*! + * @brief This API is used to set the Interrupt Reset + * in the register 0x21 bit 7 + * + * + * + * @param v_rst_int_u8: the value of reset interrupt + * + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_rst_intr(u8 v_rst_int_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* write reset interrupt */ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_RST_LATCH_ADDR_RST_INTR__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_RST_LATCH_ADDR_RST_INTR, v_rst_int_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC(p_bmg160->dev_addr, + BMG160_RST_LATCH_ADDR_RST_INTR__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + } + return comres; +} +/*! + * @brief This API is used to set the offset Reset + * in the register 0x21 bit 6 + * + * + * + * @param v_offset_rst_u8: the value of reset offset + * + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_offset_rst( + u8 v_offset_rst_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* write reset offset */ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_RST_LATCH_ADDR_OFFSET_RST__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_RST_LATCH_ADDR_OFFSET_RST, v_offset_rst_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC(p_bmg160->dev_addr, + BMG160_RST_LATCH_ADDR_OFFSET_RST__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + } + return comres; +} +/*! + * @brief This API is used to get the Latch Status + * in the register 0x21 bit 4 + * + * + * + * @param v_latch_stat_u8 : The value of latch status + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_latch_stat( + u8 *v_latch_stat_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read the latch status*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_RST_LATCH_ADDR_LATCH_STAT__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_latch_stat_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_RST_LATCH_ADDR_LATCH_STAT); + } + return comres; +} +/*! + * @brief This API is used to set the Latch Status + * in the register 0x21 bit 4 + * + * + * + * @param v_latch_stat_u8 : The value of latch status + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_latch_stat( + u8 v_latch_stat_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* write the latch status */ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_RST_LATCH_ADDR_LATCH_STAT__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_RST_LATCH_ADDR_LATCH_STAT, v_latch_stat_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC(p_bmg160->dev_addr, + BMG160_RST_LATCH_ADDR_LATCH_STAT__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + } + return comres; +} +/*! + * @brief This API is used to get the Latch interrupt + * in the register 0x21 bit from 0 to 3 + * + * + * + * @param v_latch_intr_u8 : The value of latch interrupt + * Latch Interrupt | Value + * ----------------------------|----------------- + * BMG160_NON_LATCH | 0x00 + * BMG160_LATCH_250_MS | 0x01 + * BMG160_LATCH_500_MS | 0x02 + * BMG160_LATCH_1_SEC | 0x03 + * BMG160_LATCH_2_SEC | 0x04 + * BMG160_LATCH_4_SEC | 0x05 + * BMG160_LATCH_8_SEC | 0x06 + * BMG160_LATCH_LATCHED | 0x07 + * BMG160_LATCH_NON_LATCHED | 0x08 + * BMG160_LATCH_250_MICRO_SEC | 0x09 + * BMG160_LATCH_500_MICRO_SEC | 0x0A + * BMG160_LATCH_1_MILLI_SEC | 0x0B + * BMG160_LATCH_12.5_MILLI_SEC | 0x0C + * BMG160_LATCH_25_MILLI_SEC | 0x0D + * BMG160_LATCH_50_MILLI_SEC | 0x0E + * BMG160_LATCH_LATCHED | 0x0F + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_latch_intr(u8 *v_latch_intr_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read latch interrupt */ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_RST_LATCH_ADDR_LATCH_INTR__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_latch_intr_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_RST_LATCH_ADDR_LATCH_INTR); + } + return comres; +} +/*! + * @brief This API is used to set the Latch interrupt + * in the register 0x21 bit from 0 to 3 + * + * + * + * @param v_latch_intr_u8 : The value of latch interrupt + * Latch Interrupt | Value + * ----------------------------|----------------- + * BMG160_NON_LATCH | 0x00 + * BMG160_LATCH_250_MS | 0x01 + * BMG160_LATCH_500_MS | 0x02 + * BMG160_LATCH_1_SEC | 0x03 + * BMG160_LATCH_2_SEC | 0x04 + * BMG160_LATCH_4_SEC | 0x05 + * BMG160_LATCH_8_SEC | 0x06 + * BMG160_LATCH_LATCHED | 0x07 + * BMG160_LATCH_NON_LATCHED | 0x08 + * BMG160_LATCH_250_MICRO_SEC | 0x09 + * BMG160_LATCH_500_MICRO_SEC | 0x0A + * BMG160_LATCH_1_MILLI_SEC | 0x0B + * BMG160_LATCH_12.5_MILLI_SEC | 0x0C + * BMG160_LATCH_25_MILLI_SEC | 0x0D + * BMG160_LATCH_50_MILLI_SEC | 0x0E + * BMG160_LATCH_LATCHED | 0x0F + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_latch_intr(u8 v_latch_intr_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* write latch interrupt */ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_RST_LATCH_ADDR_LATCH_INTR__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_RST_LATCH_ADDR_LATCH_INTR, v_latch_intr_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC(p_bmg160->dev_addr, + BMG160_RST_LATCH_ADDR_LATCH_INTR__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + } + return comres; +} +/*! + * @brief This API is used to get the status of High + * Hysteresis of X,Y,Z axis in the registers 0x22,0x24 and 0x26 + * @note X_AXIS - 0x22 bit 6 and 7 + * @note Y_AXIS - 0x24 bit 6 and 7 + * @note Z_AXIS - 0x26 bit 6 and 7 + * + * @param v_channel_u8: The value of high Hysteresis channel number + * v_channel_u8 | value + * --------------|-------------- + * BMG160_X_AXIS | 0 + * BMG160_Y_AXIS | 1 + * BMG160_Z_AXIS | 2 + * + * @param v_highrate_hyst_u8: The value of high Hysteresis + * + * @note High hysteresis can be calculated by + * @note High_hyst = ((255+256 *v_highrate_hyst_u8) * 4LSB) + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_highrate_hyst(u8 v_channel_u8, + u8 *v_highrate_hyst_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + switch (v_channel_u8) + { + /* read high hysteresis*/ + case BMG160_X_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_HIGHRATE_HYST_X__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_highrate_hyst_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_HIGHRATE_HYST_X); + break; + case BMG160_Y_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_HIGHRATE_HYST_Y__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_highrate_hyst_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_HIGHRATE_HYST_Y); + break; + case BMG160_Z_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_HIGHRATE_HYST_Z__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_highrate_hyst_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_HIGHRATE_HYST_Z); + break; + default: + comres = E_BMG160_OUT_OF_RANGE; + break; + } + } + return comres; +} +/*! + * @brief This API is used to set the status of High + * Hysteresis of X,Y,Z axis in the registers 0x22,0x24 and 0x26 + * @note X_AXIS - 0x22 bit 6 and 7 + * @note Y_AXIS - 0x24 bit 6 and 7 + * @note Z_AXIS - 0x26 bit 6 and 7 + * + * @param v_channel_u8: The value of high Hysteresis channel number + * v_channel_u8 | value + * --------------|-------------- + * BMG160_X_AXIS | 0 + * BMG160_Y_AXIS | 1 + * BMG160_Z_AXIS | 2 + * + * @param v_highrate_hyst_u8: The value of high Hysteresis + * + * @note High hysteresis can be calculated by + * @note High_hyst = ((255+256 *v_highrate_hyst_u8) * 4LSB) + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_highrate_hyst(u8 v_channel_u8, + u8 v_highrate_hyst_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + switch (v_channel_u8) + { + /* write high hysteresis*/ + case BMG160_X_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_HIGHRATE_HYST_X__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_HIGHRATE_HYST_X, v_highrate_hyst_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_HIGHRATE_HYST_X__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + case BMG160_Y_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_HIGHRATE_HYST_Y__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_HIGHRATE_HYST_Y, v_highrate_hyst_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_HIGHRATE_HYST_Y__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + case BMG160_Z_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_HIGHRATE_HYST_Z__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_HIGHRATE_HYST_Z, v_highrate_hyst_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_HIGHRATE_HYST_Z__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + default: + comres = E_BMG160_OUT_OF_RANGE; + break; + } + } + return comres; +} +/*! + * @brief This API is used to get the value of High rate + * Threshold of X,Y,Z axis in the registers 0x22, 0x24 and 0x26 + * @note X_AXIS - 0x22 bit from 1 to 5 + * @note Y_AXIS - 0x24 bit from 1 to 5 + * @note Z_AXIS - 0x26 bit from 1 to 5 + * + * @param v_channel_u8 : The value of high threshold channel number + * v_channel_u8 | value + * --------------|-------------- + * BMG160_X_AXIS | 0 + * BMG160_Y_AXIS | 1 + * BMG160_Z_AXIS | 2 + * + * @param v_highrate_thres_u8: the high threshold value + * + * @note High Threshold can be calculated by + * @note High_thres = ((255+256 *v_highrate_thres_u8) * 4LSB) + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_highrate_thres(u8 v_channel_u8, + u8 *v_highrate_thres_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + switch (v_channel_u8) + { + /* read high rate threshold*/ + case BMG160_X_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_HIGHRATE_THRES_X__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_highrate_thres_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_HIGHRATE_THRES_X); + break; + case BMG160_Y_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_HIGHRATE_THRES_Y__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_highrate_thres_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_HIGHRATE_THRES_Y); + break; + case BMG160_Z_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_HIGHRATE_THRES_Z__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_highrate_thres_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_HIGHRATE_THRES_Z); + break; + default: + comres = E_BMG160_OUT_OF_RANGE; + break; + } + } + return comres; +} +/*! + * @brief This API is used to set the value of High rate + * Threshold of X,Y,Z axis in the registers 0x22, 0x24 and 0x26 + * @note X_AXIS - 0x22 bit from 1 to 5 + * @note Y_AXIS - 0x24 bit from 1 to 5 + * @note Z_AXIS - 0x26 bit from 1 to 5 + * + * @param v_channel_u8 : The value of high threshold channel number + * v_channel_u8 | value + * --------------|-------------- + * BMG160_X_AXIS | 0 + * BMG160_Y_AXIS | 1 + * BMG160_Z_AXIS | 2 + * + * @param v_highrate_thres_u8: the high threshold value + * + * @note High Threshold can be calculated by + * @note High_thres = ((255+256 *v_highrate_thres_u8) * 4LSB) + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_highrate_thres(u8 v_channel_u8, + u8 v_highrate_thres_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + switch (v_channel_u8) + { + /* write high rate threshold*/ + case BMG160_X_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_HIGHRATE_THRES_X__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_HIGHRATE_THRES_X, v_highrate_thres_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_HIGHRATE_THRES_X__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + case BMG160_Y_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_HIGHRATE_THRES_Y__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_HIGHRATE_THRES_Y, v_highrate_thres_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_HIGHRATE_THRES_Y__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + case BMG160_Z_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_HIGHRATE_THRES_Z__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_HIGHRATE_THRES_Z, v_highrate_thres_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_HIGHRATE_THRES_Z__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + default: + comres = E_BMG160_OUT_OF_RANGE; + break; + } + } + return comres; +} +/*! + * @brief This API is used to get the status of High Enable + * Channel X,Y,Z in the registers 0x22, 0x24 and 0x26 + * @note X_AXIS - 0x22 bit 0 + * @note Y_AXIS - 0x24 bit 0 + * @note Z_AXIS - 0x26 bit 0 + * + * @param v_channel_u8 : The value of high enable channel number + * v_channel_u8 | value + * --------------|-------------- + * BMG160_X_AXIS | 0 + * BMG160_Y_AXIS | 1 + * BMG160_Z_AXIS | 2 + * + * @param v_enable_u8: The value of high axis enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_highrate_enable_axis(u8 v_channel_u8, + u8 *v_enable_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + switch (v_channel_u8) + { + /* read high rate axis enable */ + case BMG160_X_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_HIGHRATE_ENABLE_X__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_enable_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_HIGHRATE_ENABLE_X); + break; + case BMG160_Y_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_HIGHRATE_ENABLE_Y__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_enable_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_HIGHRATE_ENABLE_Y); + break; + case BMG160_Z_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_HIGHRATE_ENABLE_Z__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_enable_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_HIGHRATE_ENABLE_Z); + break; + default: + comres = E_BMG160_OUT_OF_RANGE; + break; + } + } + return comres; +} +/*! + * @brief This API is used to set the status of High Enable + * Channel X,Y,Z in the registers 0x22, 0x24 and 0x26 + * @note X_AXIS - 0x22 bit 0 + * @note Y_AXIS - 0x24 bit 0 + * @note Z_AXIS - 0x26 bit 0 + * + * @param v_channel_u8 : The value of high enable channel number + * v_channel_u8 | value + * --------------|-------------- + * BMG160_X_AXIS | 0 + * BMG160_Y_AXIS | 1 + * BMG160_Z_AXIS | 2 + * + * @param v_enable_u8: The value of high axis enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_highrate_enable_axis(u8 v_channel_u8, + u8 v_enable_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + switch (v_channel_u8) + { + /* write high rate axis enable */ + case BMG160_X_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_HIGHRATE_ENABLE_X__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_HIGHRATE_ENABLE_X, v_enable_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_HIGHRATE_ENABLE_X__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + case BMG160_Y_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_HIGHRATE_ENABLE_Y__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_HIGHRATE_ENABLE_Y, v_enable_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_HIGHRATE_ENABLE_Y__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + case BMG160_Z_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_HIGHRATE_ENABLE_Z__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_HIGHRATE_ENABLE_Z, v_enable_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_HIGHRATE_ENABLE_Z__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + default: + comres = E_BMG160_OUT_OF_RANGE; + break; + } + } + return comres; +} +/*! + * @brief This API is used to get the status + * of High duration of X,Y,Z axis in + * the registers 0x23, 0x25 and 0x27 + * @note X_AXIS - 0x23 bit form 0 to 7 + * @note Y_AXIS - 0x25 bit form 0 to 7 + * @note Z_AXIS - 0x27 bit form 0 to 7 + * + * + * + * @param v_channel_u8: The value of High Duration channel number + * v_channel_u8 | value + * --------------|-------------- + * BMG160_X_AXIS | 0 + * BMG160_Y_AXIS | 1 + * BMG160_Z_AXIS | 2 + * + * @param v_highrate_durn_axis_u8: The value of high duration + * + * @note High rate duration can be calculated by using the formula + * @note High_durn = ((1+v_highrate_durn_axis_u8)*2.5ms) + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_highrate_durn_axis(u8 v_channel_u8, + u8 *v_highrate_durn_axis_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + switch (v_channel_u8) + { + /* read high rate duration*/ + case BMG160_X_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_HIGHRATE_DURN_X_ADDR, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_highrate_durn_axis_u8 = v_data_u8; + break; + case BMG160_Y_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_HIGHRATE_THRES_Y_ADDR, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_highrate_durn_axis_u8 = v_data_u8; + break; + case BMG160_Z_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_HIGHRATE_THRES_Z_ADDR, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_highrate_durn_axis_u8 = v_data_u8; + break; + default: + comres = E_BMG160_OUT_OF_RANGE; + break; + } + } + return comres; +} +/*! + * @brief This API is used to set the value + * of High duration of X,Y,Z axis in + * the registers 0x23, 0x25 and 0x27 + * @note X_AXIS - 0x23 bit form 0 to 7 + * @note Y_AXIS - 0x25 bit form 0 to 7 + * @note Z_AXIS - 0x27 bit form 0 to 7 + * + * + * + * @param v_channel_u8: The value of High Duration channel number + * v_channel_u8 | value + * --------------|-------------- + * BMG160_X_AXIS | 0 + * BMG160_Y_AXIS | 1 + * BMG160_Z_AXIS | 2 + * + * @param v_highrate_durn_axis_u8: The value of high duration + * + * @note High rate duration can be calculated by using the formula + * @note High_durn = ((1+v_highrate_durn_axis_u8)*2.5ms) + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_highrate_durn_axis(u8 v_channel_u8, + u8 v_highrate_durn_axis_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + switch (v_channel_u8) + { + /* write high rate duration*/ + case BMG160_X_AXIS: + v_data_u8 = v_highrate_durn_axis_u8; + comres = p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_HIGHRATE_THRES_X_ADDR, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + case BMG160_Y_AXIS: + v_data_u8 = v_highrate_durn_axis_u8; + comres = p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_HIGHRATE_THRES_Y_ADDR, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + case BMG160_Z_AXIS: + v_data_u8 = v_highrate_durn_axis_u8; + comres = p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_HIGHRATE_THRES_Z_ADDR, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + default: + comres = E_BMG160_OUT_OF_RANGE; + break; + } + } + return comres; +} +/*! + * @brief This API is used to get Slow Offset Threshold + * status in the register 0x31 bit 6 and 7 + * + * + * + * @param v_offset_thres_u8 : The value of slow offset Threshold + * value | threshold + * ----------|------------- + * 0x00 | 0.1 degree/sec + * 0x01 | 0.2 degree/sec + * 0x02 | 0.5 degree/sec + * 0x03 | 1 degree/sec + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_slow_offset_thres( + u8 *v_offset_thres_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read slow offset threshold*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_SLOW_OFFSET_THRES__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_offset_thres_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_SLOW_OFFSET_THRES); + } + return comres; +} +/*! + * @brief This API is used to set Slow Offset Threshold + * status in the register 0x31 bit 6 and 7 + * + * + * + * @param v_offset_thres_u8 : The value of slow offset Threshold + * value | threshold + * ----------|------------- + * 0x00 | 0.1 degree/sec + * 0x01 | 0.2 degree/sec + * 0x02 | 0.5 degree/sec + * 0x03 | 1 degree/sec + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_slow_offset_thres(u8 v_offset_thres_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* write slow offset threshold*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_SLOW_OFFSET_THRES__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_SLOW_OFFSET_THRES, v_offset_thres_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC(p_bmg160->dev_addr, + BMG160_SLOW_OFFSET_THRES__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + } + return comres; +} +/*! + * @brief This API is used to get Slow Offset duration + * status in the register 0x31 bit 4,5 and 6 + * + * + * + * @param v_offset_durn_u8 : The value of Slow Offset duration + * value | Duration + * -----------|----------- + * 0x00 | 40ms + * 0x01 | 80ms + * 0x02 | 160ms + * 0x03 | 320ms + * 0x04 | 640ms + * 0x05 | 1280ms + * 0x06 | unused + * 0x07 | unused + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_slow_offset_durn( + u8 *v_offset_durn_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read slow offset duration*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_SLOW_OFFSET_DURN__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_offset_durn_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_SLOW_OFFSET_DURN); + } + return comres; +} +/*! + * @brief This API is used to set Slow Offset duration + * status in the register 0x31 bit 4,5 and 6 + * + * + * + * @param v_offset_durn_u8 : The value of Slow Offset duration + * value | Duration + * -----------|----------- + * 0x00 | 40ms + * 0x01 | 80ms + * 0x02 | 160ms + * 0x03 | 320ms + * 0x04 | 640ms + * 0x05 | 1280ms + * 0x06 | unused + * 0x07 | unused + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_slow_offset_durn( + u8 v_offset_durn_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* write slow offset duration*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_SLOW_OFFSET_DURN__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_SLOW_OFFSET_DURN, v_offset_durn_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC(p_bmg160->dev_addr, + BMG160_SLOW_OFFSET_DURN__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + } + return comres; +} +/*! + * @brief This API is used to get Slow Offset Enable channel + * X,Y,Z in the register 0x31 + * @note X_AXIS -> bit 0 + * @note Y_AXIS -> bit 1 + * @note Z_AXIS -> bit 2 + * + * + * @param v_channel_u8: The value of slow offset channel number + * v_channel_u8 | value + * --------------|-------------- + * BMG160_X_AXIS | 0 + * BMG160_Y_AXIS | 1 + * BMG160_Z_AXIS | 2 + * + * @param v_slow_offset_u8: The slow offset value + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_slow_offset_enable_axis( + u8 v_channel_u8, u8 *v_slow_offset_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + switch (v_channel_u8) + { + /* read slow offset axis enable */ + case BMG160_X_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_SLOW_OFFSET_ENABLE_X__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_slow_offset_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_SLOW_OFFSET_ENABLE_X); + break; + case BMG160_Y_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_SLOW_OFFSET_ENABLE_Y__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_slow_offset_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_SLOW_OFFSET_ENABLE_Y); + break; + case BMG160_Z_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_SLOW_OFFSET_ENABLE_Z__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_slow_offset_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_SLOW_OFFSET_ENABLE_Z); + break; + default: + comres = E_BMG160_OUT_OF_RANGE; + break; + } + } + return comres; +} +/*! + * @brief This API is used to set Slow Offset Enable channel + * X,Y,Z in the register 0x31 + * @note X_AXIS -> bit 0 + * @note Y_AXIS -> bit 1 + * @note Z_AXIS -> bit 2 + * + * + * @param v_channel_u8: The value of slow offset channel number + * v_channel_u8 | value + * --------------|-------------- + * BMG160_X_AXIS | 0 + * BMG160_Y_AXIS | 1 + * BMG160_Z_AXIS | 2 + * + * @param v_slow_offset_u8: The slow offset value + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_slow_offset_enable_axis( + u8 v_channel_u8, u8 v_slow_offset_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + switch (v_channel_u8) + { + /* write slow offset axis enable */ + case BMG160_X_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_SLOW_OFFSET_ENABLE_X__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_SLOW_OFFSET_ENABLE_X, v_slow_offset_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_SLOW_OFFSET_ENABLE_X__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + case BMG160_Y_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_SLOW_OFFSET_ENABLE_Y__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_SLOW_OFFSET_ENABLE_Y, v_slow_offset_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_SLOW_OFFSET_ENABLE_Y__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + case BMG160_Z_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_SLOW_OFFSET_ENABLE_Z__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_SLOW_OFFSET_ENABLE_Z, + v_slow_offset_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_SLOW_OFFSET_ENABLE_Z__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + default: + comres = E_BMG160_OUT_OF_RANGE; + break; + } + } + return comres; +} +/*! + * @brief This API is used to get + * Fast Offset WordLength and Auto Offset WordLength in the register 0x32 + * @note fast_offset_wordlength -> bit 4 and 5 + * @note auto_offset_wordlength -> bit 6 and 7 + * + * + * @param v_channel_u8: The value of WordLengthchannel number + * v_channel_u8 | value + * ----------------------|-------------- + * BMG160_AUTO_OFFSET_WL | 0 + * BMG160_FAST_OFFSET_WL | 1 + * + * @param v_offset_word_length_u8: The value of offset word length + * value | word length + * ----------|-------------- + * 0x00 | 32 samples + * 0x01 | 64 samples + * 0x02 | 128 samples + * 0x03 | 256 samples + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_offset_word_length(u8 v_channel_u8, + u8 *v_offset_word_length_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + switch (v_channel_u8) + { + case BMG160_AUTO_OFFSET_WORD_LENGHTH: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_AUTO_OFFSET_WORD_LENGHTH__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_offset_word_length_u8 = + BMG160_GET_BITSLICE(v_data_u8, + BMG160_AUTO_OFFSET_WORD_LENGHTH); + break; + case BMG160_FAST_OFFSET_WORD_LENGHTH: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_FAST_OFFSET_WORD_LENGHTH__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_offset_word_length_u8 = + BMG160_GET_BITSLICE(v_data_u8, + BMG160_FAST_OFFSET_WORD_LENGHTH); + break; + default: + comres = E_BMG160_OUT_OF_RANGE; + break; + } + } + return comres; +} +/*! + * @brief This API is used to set + * Fast Offset WordLength and Auto Offset WordLength in the register 0x32 + * @note fast_offset_wordlength -> bit 4 and 5 + * @note auto_offset_wordlength -> bit 6 and 7 + * + * + * @param v_channel_u8: The value of WordLengthchannel number + * v_channel_u8 | value + * ----------------------|-------------- + * BMG160_AUTO_OFFSET_WL | 0 + * BMG160_FAST_OFFSET_WL | 1 + * + * @param v_offset_word_length_u8: The value of offset word length + * value | word length + * ----------|-------------- + * 0x00 | 32 samples + * 0x01 | 64 samples + * 0x02 | 128 samples + * 0x03 | 256 samples + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_offset_word_length( + u8 v_channel_u8, u8 v_offset_word_length_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + switch (v_channel_u8) + { + case BMG160_AUTO_OFFSET_WORD_LENGHTH: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_AUTO_OFFSET_WORD_LENGHTH__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_AUTO_OFFSET_WORD_LENGHTH, + v_offset_word_length_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_AUTO_OFFSET_WORD_LENGHTH__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + case BMG160_FAST_OFFSET_WORD_LENGHTH: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_FAST_OFFSET_WORD_LENGHTH__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_FAST_OFFSET_WORD_LENGHTH, + v_offset_word_length_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_FAST_OFFSET_WORD_LENGHTH__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + default: + comres = E_BMG160_OUT_OF_RANGE; + break; + } + } + return comres; +} +/*! + * @brief This API is used to enable fast offset + * in the register 0x32 bit 3 it is a write only register + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_enable_fast_offset(void) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_FAST_OFFSET_ENABLE__REG, &v_data_u8, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_FAST_OFFSET_ENABLE, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC(p_bmg160->dev_addr, + BMG160_FAST_OFFSET_ENABLE__REG, &v_data_u8, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + } + return comres; +} +/*! + * @brief This API read the Fast offset enable + * v_axis_u8(X,Y and Z) in the register 0x32 + * @note X_AXIS -> bit 0 + * @note Y_AXIS -> bit 1 + * @note Z_AXIS -> bit 2 + * + * + * + * @param v_fast_offset_u8: The value of fast offset enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_fast_offset_enable_axis( + u8 *v_fast_offset_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read fast offset enable axis*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_FAST_OFFSET_ENABLE_XYZ__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_fast_offset_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_FAST_OFFSET_ENABLE_XYZ); + } + return comres; +} +/*! + * @brief This API set the Fast offset enable + * v_axis_u8(X,Y and Z) in the register 0x32 + * @note X_AXIS -> bit 0 + * @note Y_AXIS -> bit 1 + * @note Z_AXIS -> bit 2 + * + * + * @param v_channel_u8: The value of fast offset channel select + * v_channel_u8 | value + * ----------------|-------------- + * BMG160_X_AXIS | 0 + * BMG160_Y_AXIS | 1 + * BMG160_Z_AXIS | 2 + * + * @param v_fast_offset_u8: The value of fast offset enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_fast_offset_enable_axis( + u8 v_channel_u8, u8 v_fast_offset_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + switch (v_channel_u8) + { + /* write fast offset enable axis*/ + case BMG160_X_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_FAST_OFFSET_ENABLE_X__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_FAST_OFFSET_ENABLE_X, v_fast_offset_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_FAST_OFFSET_ENABLE_X__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + case BMG160_Y_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_FAST_OFFSET_ENABLE_Y__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_FAST_OFFSET_ENABLE_Y, v_fast_offset_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_FAST_OFFSET_ENABLE_Y__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + case BMG160_Z_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_FAST_OFFSET_ENABLE_Z__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_FAST_OFFSET_ENABLE_Z, v_fast_offset_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_FAST_OFFSET_ENABLE_Z__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + default: + comres = E_BMG160_OUT_OF_RANGE; + break; + } + } + return comres; +} +/*! + * @brief This API is used to get the status of nvm program + * remain in the register 0x33 bit from 4 to 7 + * + * + * @param v_nvm_remain_u8: The value of nvm program + * value | Description + * -----------|--------------- + * 1 | Do not trigger + * 0 | Trigger + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_nvm_remain(u8 *v_nvm_remain_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read NVM program*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_TRIM_NVM_CTRL_ADDR_NVM_REMAIN__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_nvm_remain_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_TRIM_NVM_CTRL_ADDR_NVM_REMAIN); + } + return comres; +} +/*! + * @brief This API is used to set the status of nvm program + * remain in the register 0x33 bit from 4 to 7 + * + * + * @param v_nvm_load_u8: The value of nvm program + * value | Description + * -----------|--------------- + * 1 | Do not trigger + * 0 | Trigger + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_nvm_load(u8 v_nvm_load_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* write NVM program*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_TRIM_NVM_CTRL_ADDR_NVM_LOAD__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_TRIM_NVM_CTRL_ADDR_NVM_LOAD, v_nvm_load_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC(p_bmg160->dev_addr, + BMG160_TRIM_NVM_CTRL_ADDR_NVM_LOAD__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + } + return comres; +} +/*! + * @brief This API is used to get the status of nvm + * program in the register 0x33 bit 2 + * + * @param v_nvm_rdy_u8: The value of nvm program + * value | Description + * -----------|--------------- + * 1 | NVM write is in progress + * 0 | NVM is ready to accept a new write + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_nvm_rdy(u8 *v_nvm_rdy_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_TRIM_NVM_CTRL_ADDR_NVM_RDY__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_nvm_rdy_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_TRIM_NVM_CTRL_ADDR_NVM_RDY); + } + return comres; +} +/*! + * @brief This API is used to set the status of nvm + * ready in the register 0x33 bit 1 + * + * @param nvm_prog_trig: The value of nvm program + * value | Description + * -----------|--------------- + * 1 | program seq in progress + * 0 | program seq finished + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_nvm_prog_trig(u8 nvm_prog_trig) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_TRIM_NVM_CTRL_ADDR_NVM_PROG_TRIG__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_TRIM_NVM_CTRL_ADDR_NVM_PROG_TRIG, nvm_prog_trig); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC(p_bmg160->dev_addr, + BMG160_TRIM_NVM_CTRL_ADDR_NVM_PROG_TRIG__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + } + return comres; +} +/*! + * @brief This API is used to get + * the status of nvm program mode in the register 0x33 bit 0 + * + * + * @param nvm_prog_mode: The value of nvm program mode + * value | Description + * -----------|--------------- + * 1 | Unlock + * 0 | Lock nvm write + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_nvm_prog_mode(u8 *nvm_prog_mode) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_TRIM_NVM_CTRL_ADDR_NVM_PROG_MODE__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *nvm_prog_mode = BMG160_GET_BITSLICE(v_data_u8, + BMG160_TRIM_NVM_CTRL_ADDR_NVM_PROG_MODE); + } + return comres; +} +/*! + * @brief This API is used to set + * the status of nvm program mode in the register 0x33 bit 0 + * + * + * @param nvm_prog_mode: The value of nvm program mode + * value | Description + * -----------|--------------- + * 1 | Unlock + * 0 | Lock nvm write + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_nvm_prog_mode(u8 nvm_prog_mode) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_TRIM_NVM_CTRL_ADDR_NVM_PROG_MODE__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_TRIM_NVM_CTRL_ADDR_NVM_PROG_MODE, nvm_prog_mode); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC(p_bmg160->dev_addr, + BMG160_TRIM_NVM_CTRL_ADDR_NVM_PROG_MODE__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + } + return comres; +} +/*! + * @brief This API is used to get + * the status of i2c wdt select and enable in the register 0x34 + * @note i2c_wdt_select -> bit 1 + * @note i2c_wdt_enable -> bit 2 + * + * @param v_channel_u8: The value of i2c wdt channel number + * v_channel_u8 | value + * ------------------------|-------------- + * BMG160_I2C_WDT_ENABLE | 1 + * BMG160_I2C_WDT_SELECT | 0 + * + * @param v_i2c_wdt_u8: The value of I2C enable and WDT select + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_i2c_wdt(u8 v_channel_u8, + u8 *v_i2c_wdt_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + switch (v_channel_u8) + { + /* read i2c wdt*/ + case BMG160_I2C_WDT_ENABLE: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_BGW_SPI3_WDT_ADDR_I2C_WDT_ENABLE__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_i2c_wdt_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_BGW_SPI3_WDT_ADDR_I2C_WDT_ENABLE); + break; + case BMG160_I2C_WDT_SELECT: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_BGW_SPI3_WDT_ADDR_I2C_WDT_SELECT__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_i2c_wdt_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_BGW_SPI3_WDT_ADDR_I2C_WDT_SELECT); + break; + default: + comres = E_BMG160_OUT_OF_RANGE; + break; + } + } + return comres; +} +/*! + * @brief This API is used to set + * the status of i2c wdt select and enable in the register 0x34 + * @note i2c_wdt_select -> bit 1 + * @note i2c_wdt_enable -> bit 2 + * + * @param v_channel_u8: The value of i2c wdt channel number + * v_channel_u8 | value + * ------------------------|-------------- + * BMG160_I2C_WDT_ENABLE | 1 + * BMG160_I2C_WDT_SELECT | 0 + * + * @param v_i2c_wdt_u8: The value of I2C enable and WDT select + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_i2c_wdt(u8 v_channel_u8, + u8 v_i2c_wdt_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + switch (v_channel_u8) + { + /* write i2c wdt*/ + case BMG160_I2C_WDT_ENABLE: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_BGW_SPI3_WDT_ADDR_I2C_WDT_ENABLE__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_BGW_SPI3_WDT_ADDR_I2C_WDT_ENABLE, v_i2c_wdt_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_BGW_SPI3_WDT_ADDR_I2C_WDT_ENABLE__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + case BMG160_I2C_WDT_SELECT: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_BGW_SPI3_WDT_ADDR_I2C_WDT_SELECT__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_BGW_SPI3_WDT_ADDR_I2C_WDT_SELECT, v_i2c_wdt_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_BGW_SPI3_WDT_ADDR_I2C_WDT_SELECT__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + default: + comres = E_BMG160_OUT_OF_RANGE; + break; + } + } + return comres; +} +/*! + * @brief This API is used to get the status of spi3 + * in the register 0x34 bit 0 + * + * + * + * @param v_spi3_u8 : The value of spi3 enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_spi3(u8 *v_spi3_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + comres = p_bmg160->BMG160_BUS_READ_FUNC( + p_bmg160->dev_addr, + BMG160_BGW_SPI3_WDT_ADDR_SPI3__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_spi3_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_BGW_SPI3_WDT_ADDR_SPI3); + } + return comres; +} +/*! + * @brief This API is used to set the status of spi3 + * in the register 0x34 bit 0 + * + * + * + * @param v_spi3_u8 : The value of spi3 enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_spi3(u8 v_spi3_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_BGW_SPI3_WDT_ADDR_SPI3__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_BGW_SPI3_WDT_ADDR_SPI3, v_spi3_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC(p_bmg160->dev_addr, + BMG160_BGW_SPI3_WDT_ADDR_SPI3__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + } + return comres; +} +/*! + * @brief This API is used to get the status of FIFO tag + * in the register 0x3D bit 7 + * + * + * + * @param v_fifo_tag_u8 : The value of fifo tag enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_fifo_tag(u8 *v_fifo_tag_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read fifo tag*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_FIFO_CGF1_ADDR_TAG__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_fifo_tag_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_FIFO_CGF1_ADDR_TAG); + } + return comres; +} +/*! + * @brief This API is used to set the status of FIFO tag + * in the register 0x3D bit 7 + * + * + * + * @param v_fifo_tag_u8 : The value of fifo tag enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_fifo_tag(u8 v_fifo_tag_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + if (v_fifo_tag_u8 < BMG160_BIT_LENGTH_FIFO_TAG) + { + /* write fifo tag */ + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_FIFO_CGF1_ADDR_TAG__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_FIFO_CGF1_ADDR_TAG, v_fifo_tag_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_FIFO_CGF1_ADDR_TAG__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + } + else + { + comres = E_BMG160_OUT_OF_RANGE; + } + } + return comres; +} +/*! + * @brief This API is used to get Water Mark Level + * in the register 0x3D bit from 0 to 6 + * + * + * + * @param v_fifo_wm_level_u8 : The value of fifo water mark level + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_fifo_wm_level( + u8 *v_fifo_wm_level_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_FIFO_CGF1_ADDR_WML__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_fifo_wm_level_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_FIFO_CGF1_ADDR_WML); + } + return comres; +} +/*! + * @brief This API is used to set Water Mark Level + * in the register 0x3D bit from 0 to 6 + * + * + * + * @param v_fifo_wm_level_u8 : The value of fifo water mark level + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_fifo_wm_level( + u8 v_fifo_wm_level_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + if (v_fifo_wm_level_u8 < BMG160_FIFO_WM_LENGTH) + { + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_FIFO_CGF1_ADDR_WML__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_FIFO_CGF1_ADDR_WML, v_fifo_wm_level_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_FIFO_CGF1_ADDR_WML__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + } + else + { + comres = E_BMG160_OUT_OF_RANGE; + } + } + return comres; +} +/*! + * @brief This API is used to get the value of offset + * X, Y and Z in the registers 0x36, 0x37, 0x38, 0x39 and 0x3A + * the offset is a 12bit value + * @note X_AXIS -> + * @note bit 0 and 1 is available in the register 0x3A bit 2 and 3 + * @note bit 2 and 3 is available in the register 0x36 bit 6 and 7 + * @note bit 4 to 11 is available in the register 0x37 bit 0 to 7 + * @note Y_AXIS -> + * @note bit 0 is available in the register 0x3A bit 1 + * @note bit 1,2 and 3 is available in the register 0x36 bit 3,4 and 5 + * @note bit 4 to 11 is available in the register 0x38 bit 0 to 7 + * @note Z_AXIS -> + * @note bit 0 is available in the register 0x3A bit 0 + * @note bit 1,2 and 3 is available in the register 0x36 bit 0,1 and 3 + * @note bit 4 to 11 is available in the register 0x39 bit 0 to 7 + * + * @param v_axis_u8 : The value of offset axis selection + * v_axis_u8 | value + * ----------------|-------------- + * BMG160_X_AXIS | 1 + * BMG160_Y_AXIS | 0 + * BMG160_Z_AXIS | 0 + * + * @param v_offset_s16: The value of offset + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_offset(u8 v_axis_u8, + s16 *v_offset_s16) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data1_u8r = BMG160_INIT_VALUE; + u8 v_data2_u8r = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + switch (v_axis_u8) + { + /* read offset */ + case BMG160_X_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_TRIM_GP0_ADDR_OFFSET_X__REG, + &v_data1_u8r, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data1_u8r = BMG160_GET_BITSLICE(v_data1_u8r, + BMG160_TRIM_GP0_ADDR_OFFSET_X); + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_OFC1_ADDR_OFFSET_X__REG, + &v_data2_u8r, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data2_u8r = BMG160_GET_BITSLICE(v_data2_u8r, + BMG160_OFC1_ADDR_OFFSET_X); + v_data2_u8r = ((v_data2_u8r << + BMG160_SHIFT_BIT_POSITION_BY_02_BITS) + | v_data1_u8r); + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, BMG160_OFC2_ADDR, + &v_data1_u8r, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_offset_s16 = (s16)((((s16) + ((s8)v_data1_u8r)) + << BMG160_SHIFT_BIT_POSITION_BY_04_BITS) + | (v_data2_u8r)); + break; + case BMG160_Y_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_TRIM_GP0_ADDR_OFFSET_Y__REG, + &v_data1_u8r, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data1_u8r = BMG160_GET_BITSLICE(v_data1_u8r, + BMG160_TRIM_GP0_ADDR_OFFSET_Y); + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_OFC1_ADDR_OFFSET_Y__REG, + &v_data2_u8r, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data2_u8r = BMG160_GET_BITSLICE(v_data2_u8r, + BMG160_OFC1_ADDR_OFFSET_Y); + v_data2_u8r = ((v_data2_u8r << + BMG160_SHIFT_BIT_POSITION_BY_01_BIT) + | v_data1_u8r); + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_OFC3_ADDR, &v_data1_u8r, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_offset_s16 = (s16)((((s16) + ((s8)v_data1_u8r)) + << BMG160_SHIFT_BIT_POSITION_BY_04_BITS) + | (v_data2_u8r)); + break; + case BMG160_Z_AXIS: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_TRIM_GP0_ADDR_OFFSET_Z__REG, + &v_data1_u8r, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data1_u8r = BMG160_GET_BITSLICE(v_data1_u8r, + BMG160_TRIM_GP0_ADDR_OFFSET_Z); + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_OFC1_ADDR_OFFSET_Z__REG, + &v_data2_u8r, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data2_u8r = BMG160_GET_BITSLICE(v_data2_u8r, + BMG160_OFC1_ADDR_OFFSET_Z); + v_data2_u8r = ((v_data2_u8r << + BMG160_SHIFT_BIT_POSITION_BY_01_BIT) + | v_data1_u8r); + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_OFC4_ADDR, &v_data1_u8r, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_offset_s16 = (s16)((((s16) + ((s8)v_data1_u8r)) + << BMG160_SHIFT_BIT_POSITION_BY_04_BITS) + | (v_data2_u8r)); + break; + default: + comres = E_BMG160_OUT_OF_RANGE; + break; + } + } + return comres; +} +/*! + * @brief This API is used to set the value of offset + * X, Y and Z in the registers 0x36, 0x37, 0x38, 0x39 and 0x3A + * the offset is a 12bit value + * @note X_AXIS -> + * @note bit 0 and 1 is available in the register 0x3A bit 2 and 3 + * @note bit 2 and 3 is available in the register 0x36 bit 6 and 7 + * @note bit 4 to 11 is available in the register 0x37 bit 0 to 7 + * @note Y_AXIS -> + * @note bit 0 is available in the register 0x3A bit 1 + * @note bit 1,2 and 3 is available in the register 0x36 bit 3,4 and 5 + * @note bit 4 to 11 is available in the register 0x38 bit 0 to 7 + * @note Z_AXIS -> + * @note bit 0 is available in the register 0x3A bit 0 + * @note bit 1,2 and 3 is available in the register 0x36 bit 0,1 and 3 + * @note bit 4 to 11 is available in the register 0x39 bit 0 to 7 + * + * @param v_axis_u8 : The value of offset axis selection + * v_axis_u8 | value + * ----------------|-------------- + * BMG160_X_AXIS | 1 + * BMG160_Y_AXIS | 0 + * BMG160_Z_AXIS | 0 + * + * @param v_offset_s16: The value of offset + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_offset( + u8 v_axis_u8, s16 v_offset_s16) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data1_u8r = BMG160_INIT_VALUE; + u8 v_data2_u8r = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + switch (v_axis_u8) + { + /* write offset */ + case BMG160_X_AXIS: + v_data1_u8r = ((s8)(v_offset_s16 + & BMG160_OFFSET_MASK_BYTE_OF_DATA)) + >> BMG160_SHIFT_BIT_POSITION_BY_04_BITS; + comres = p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_OFC2_ADDR, &v_data1_u8r, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + + v_data1_u8r = (u8)(v_offset_s16 + & BMG160_OFFSET_X_BIT_MASK1); + v_data2_u8r = BMG160_SET_BITSLICE(v_data2_u8r, + BMG160_OFC1_ADDR_OFFSET_X, v_data1_u8r); + comres += p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_OFC1_ADDR_OFFSET_X__REG, + &v_data2_u8r, BMG160_GEN_READ_WRITE_DATA_LENGTH); + + v_data1_u8r = (u8)(v_offset_s16 + & BMG160_OFFSET_X_BIT_MASK2); + v_data2_u8r = BMG160_SET_BITSLICE(v_data2_u8r, + BMG160_TRIM_GP0_ADDR_OFFSET_X, v_data1_u8r); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_TRIM_GP0_ADDR_OFFSET_X__REG, + &v_data2_u8r, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + case BMG160_Y_AXIS: + v_data1_u8r = ((s8)(v_offset_s16 + & BMG160_OFFSET_MASK_BYTE_OF_DATA)) >> + BMG160_SHIFT_BIT_POSITION_BY_04_BITS; + comres = p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_OFC3_ADDR, &v_data1_u8r, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + + v_data1_u8r = (u8)(v_offset_s16 + & BMG160_OFFSET_Y_Z_BIT_MASK2); + v_data2_u8r = BMG160_SET_BITSLICE(v_data2_u8r, + BMG160_OFC1_ADDR_OFFSET_Y, v_data1_u8r); + comres += p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_OFC1_ADDR_OFFSET_Y__REG, + &v_data2_u8r, BMG160_GEN_READ_WRITE_DATA_LENGTH); + + v_data1_u8r = (u8)(v_offset_s16 + & BMG160_OFFSET_Y_Z_BIT_MASK1); + v_data2_u8r = BMG160_SET_BITSLICE(v_data2_u8r, + BMG160_TRIM_GP0_ADDR_OFFSET_Y, v_data1_u8r); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_TRIM_GP0_ADDR_OFFSET_Y__REG, + &v_data2_u8r, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + case BMG160_Z_AXIS: + v_data1_u8r = ((s8)(v_offset_s16 + & BMG160_OFFSET_MASK_BYTE_OF_DATA)) >> + BMG160_SHIFT_BIT_POSITION_BY_04_BITS; + comres = p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_OFC4_ADDR, &v_data1_u8r, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + + v_data1_u8r = (u8)(v_offset_s16 + & BMG160_OFFSET_Y_Z_BIT_MASK2); + v_data2_u8r = BMG160_SET_BITSLICE(v_data2_u8r, + BMG160_OFC1_ADDR_OFFSET_Z, v_data1_u8r); + comres += p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_OFC1_ADDR_OFFSET_Z__REG, + &v_data2_u8r, BMG160_GEN_READ_WRITE_DATA_LENGTH); + + v_data1_u8r = (u8)(v_offset_s16 + & BMG160_OFFSET_Y_Z_BIT_MASK1); + v_data2_u8r = BMG160_SET_BITSLICE(v_data2_u8r, + BMG160_TRIM_GP0_ADDR_OFFSET_Z, v_data1_u8r); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_TRIM_GP0_ADDR_OFFSET_Z__REG, + &v_data2_u8r, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + default: + comres = E_BMG160_OUT_OF_RANGE; + break; + } + } + return comres; +} +/*! + * @brief This API is used to get the status of general + * purpose register in the register 0x3A and 0x3B + * + * + * + * + * @param v_param_u8: The value of general purpose register select + * v_param_u8 | value + * ----------------|-------------- + * BMG160_GP0 | 0 + * BMG160_GP1 | 1 + * + * @param v_gp_u8: The value of general purpose register + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_gp(u8 v_param_u8, + u8 *v_gp_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + switch (v_param_u8) + { + /* read general purpose register*/ + case BMG160_GP0: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_TRIM_GP0_ADDR_GP0__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_gp_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_TRIM_GP0_ADDR_GP0); + break; + case BMG160_GP1: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_TRIM_GP1_ADDR, &v_data_u8, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_gp_u8 = v_data_u8; + break; + default: + comres = E_BMG160_OUT_OF_RANGE; + break; + } + } + return comres; +} +/*! + * @brief This API is used to set the status of general + * purpose register in the register 0x3A and 0x3B + * + * + * + * + * @param v_param_u8: The value of general purpose register select + * v_param_u8 | value + * ----------------|-------------- + * BMG160_GP0 | 0 + * BMG160_GP1 | 1 + * + * @param v_gp_u8: The value of general purpose register + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_gp(u8 v_param_u8, + u8 v_gp_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + switch (v_param_u8) + { + /* write general purpose register*/ + case BMG160_GP0: + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_TRIM_GP0_ADDR_GP0__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_TRIM_GP0_ADDR_GP0, v_gp_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_TRIM_GP0_ADDR_GP0__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + case BMG160_GP1: + v_data_u8 = v_gp_u8; + comres = p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_TRIM_GP1_ADDR, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + default: + comres = E_BMG160_OUT_OF_RANGE; + break; + } + } + return comres; +} +/*! + * @brief Reads FIFO data from location 0x3F + * + * + * + * + * @param v_fifo_data_u8 : The data of fifo + * + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error result of communication routines + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_FIFO_data_reg(u8 *v_fifo_data_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read the fifo data */ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_FIFO_DATA_ADDR, &v_data_u8, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_fifo_data_u8 = v_data_u8; + } + return comres; +} +/*! + * @brief this api is used to read the fifo status + * of frame_counter and overrun in the register 0x0E + * @note frame_counter > bit from 0 to 6 + * @note overrun -> bit 7 + * + * + * + * @param v_fifo_stat_u8 : The value of fifo overrun and fifo counter + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_fifo_stat_reg( + u8 *v_fifo_stat_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read fifo over run and frame counter */ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_FIFO_STAT_ADDR, &v_data_u8, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_fifo_stat_u8 = v_data_u8; + } + return comres; +} +/*! + * @brief this API is used to get the fifo frame counter + * in the register 0x0E bit 0 to 6 + * + * + * + * @param v_fifo_frame_count_u8: The value of fifo frame counter + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_fifo_frame_count( + u8 *v_fifo_frame_count_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read fifo frame counter */ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_FIFO_STAT_FRAME_COUNTER__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_fifo_frame_count_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_FIFO_STAT_FRAME_COUNTER); + } + return comres; +} +/*! + * @brief this API is used to get the fifo over run + * in the register 0x0E bit 7 + * + * + * + * @param v_fifo_overrun_u8: The value of fifo over run + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_fifo_overrun( + u8 *v_fifo_overrun_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read fifo over run*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_FIFO_STAT_OVERRUN__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_fifo_overrun_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_FIFO_STAT_OVERRUN); + } + return comres; +} +/*! + * @brief This API is used to get the status of fifo mode + * in the register 0x3E bit 6 and 7 + * + * + * + * @param v_fifo_mode_u8 : The value of fifo mode + * mode | value + * ----------------|-------------- + * BYPASS | 0 + * FIFO | 1 + * STREAM | 2 + * RESERVED | 3 + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_fifo_mode(u8 *v_fifo_mode_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read fifo mode*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_FIFO_CGF0_ADDR_MODE__REG, &v_data_u8, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_fifo_mode_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_FIFO_CGF0_ADDR_MODE); + } + return comres; +} +/*! + * @brief This API is used to set the status of fifo mode + * in the register 0x3E bit 6 and 7 + * + * + * + * @param v_fifo_mode_u8 : The value of fifo mode + * mode | value + * ----------------|-------------- + * BYPASS | 0 + * FIFO | 1 + * STREAM | 2 + * RESERVED | 3 + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_fifo_mode(u8 v_fifo_mode_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + if (v_fifo_mode_u8 < BMG160_BIT_LENGTH_FIFO_MODE) + { + /* write fifo mode*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_FIFO_CGF0_ADDR_MODE__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_FIFO_CGF0_ADDR_MODE, v_fifo_mode_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_FIFO_CGF0_ADDR_MODE__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + } + else + { + comres = E_BMG160_OUT_OF_RANGE; + } + } + return comres; +} +/*! + * @brief This API is used to get the status of fifo + * data select in the register 0x3E bit 0 and 1 + * + * + * @param v_fifo_data_select_u8 : The value of fifo data selection + * data selection | value + * ---------------------------|-------------- + * X,Y and Z (DEFAULT) | 0 + * X only | 1 + * Y only | 2 + * Z only | 3 + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_fifo_data_select( + u8 *v_fifo_data_select_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read fifo data select*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_FIFO_CGF0_ADDR_DATA_SELECT__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_fifo_data_select_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_FIFO_CGF0_ADDR_DATA_SELECT); + } + return comres; +} +/*! + * @brief This API is used to set the status of fifo + * data select in the register 0x3E bit 0 and 1 + * + * + * @param v_fifo_data_select_u8 : The value of fifo data selection + * data selection | value + * ---------------------------|-------------- + * X,Y and Z (DEFAULT) | 0 + * X only | 1 + * Y only | 2 + * Z only | 3 + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_fifo_data_select( + u8 v_fifo_data_select_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + if (v_fifo_data_select_u8 < + BMG160_BIT_LENGTH_FIFO_DATA_SELECT) + { + /* write fifo data select*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_FIFO_CGF0_ADDR_DATA_SELECT__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_FIFO_CGF0_ADDR_DATA_SELECT, + v_fifo_data_select_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_FIFO_CGF0_ADDR_DATA_SELECT__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + } + else + { + comres = E_BMG160_OUT_OF_RANGE; + } + } + return comres; +} +/*! + * @brief This API is used to get the operating modes of the + * sensor in the registers 0x11 and 0x12 + * + * + * + * @param v_power_mode_u8 :The value of power mode + * value | power mode + * -----------|---------------- + * 0 | BMG160_MODE_NORMAL + * 1 | BMG160_MODE_SUSPEND + * 2 | BMG160_MODE_DEEPSUSPEND + * 3 | BMG160_MODE_FASTPOWERUP + * 4 | BMG160_MODE_ADVANCEDPOWERSAVING + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_power_mode(u8 *v_power_mode_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 data1 = BMG160_INIT_VALUE; + u8 data2 = BMG160_INIT_VALUE; + u8 data3 = BMG160_INIT_VALUE; + + if (p_bmg160 == BMG160_INIT_VALUE) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read the power mode*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_MODE_LPM1_ADDR, &data1, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + comres += p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_MODE_LPM2_ADDR, &data2, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + data1 = (data1 & 0xA0) >> 5; + data3 = (data2 & 0x40) >> 6; + data2 = (data2 & 0x80) >> 7; + if (data3 == 0x01) + { + *v_power_mode_u8 = BMG160_MODE_ADVANCEDPOWERSAVING; + } + else + { + if ((data1 == 0x00) && (data2 == 0x00)) + { + *v_power_mode_u8 = BMG160_MODE_NORMAL; + } + else + { + if ((data1 == 0x01) || (data1 == 0x05)) + { + *v_power_mode_u8 = + BMG160_MODE_DEEPSUSPEND; + } + else + { + if ((data1 == 0x04) && + (data2 == 0x00)) + { + *v_power_mode_u8 = + BMG160_MODE_SUSPEND; + } + else + { + if ((data1 == 0x04) && + (data2 == 0x01)) + *v_power_mode_u8 = + BMG160_MODE_FASTPOWERUP; + } + } + } + } + } + return comres; +} +/*! + * @brief This API is used to set the operating modes of the + * sensor in the registers 0x11 and 0x12 + * + * + * + * @param v_power_mode_u8 :The value of power mode + * value | power mode + * -----------|---------------- + * 0 | BMG160_MODE_NORMAL + * 1 | BMG160_MODE_SUSPEND + * 2 | BMG160_MODE_DEEPSUSPEND + * 3 | BMG160_MODE_FASTPOWERUP + * 4 | BMG160_MODE_ADVANCEDPOWERSAVING + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_power_mode(u8 v_power_mode_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 data1 = BMG160_INIT_VALUE; + u8 data2 = BMG160_INIT_VALUE; + u8 data3 = BMG160_INIT_VALUE; + u8 v_autosleepduration = BMG160_INIT_VALUE; + u8 v_bw_u8r = BMG160_INIT_VALUE; + + if (p_bmg160 == BMG160_INIT_VALUE) + { + return E_BMG160_NULL_PTR; + } + else + { + if (v_power_mode_u8 < BMG160_BIT_LENGTH_POWER_MODE) + { + /* write the power mode*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_MODE_LPM1_ADDR, &data1, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + comres += p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_MODE_LPM2_ADDR, &data2, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + switch (v_power_mode_u8) + { + case BMG160_MODE_NORMAL: + data1 = BMG160_SET_BITSLICE(data1, + BMG160_MODE_LPM1, BMG160_INIT_VALUE); + data2 = BMG160_SET_BITSLICE(data2, + BMG160_MODE_LPM2_ADDR_FAST_POWERUP, + BMG160_INIT_VALUE); + data3 = BMG160_SET_BITSLICE(data2, + BMG160_MODE_LPM2_ADDR_ADV_POWERSAVING, + BMG160_INIT_VALUE); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_MODE_LPM1_ADDR, &data1, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + p_bmg160->delay_msec(BMG160_POWER_MODE_DELAY); + /*A minimum delay of at least + 450us is required for Multiple write.*/ + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_MODE_LPM2_ADDR, &data3, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + case BMG160_MODE_DEEPSUSPEND: + data1 = BMG160_SET_BITSLICE(data1, + BMG160_MODE_LPM1, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + data2 = BMG160_SET_BITSLICE(data2, + BMG160_MODE_LPM2_ADDR_FAST_POWERUP, + BMG160_INIT_VALUE); + data3 = BMG160_SET_BITSLICE(data2, + BMG160_MODE_LPM2_ADDR_ADV_POWERSAVING, + BMG160_INIT_VALUE); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_MODE_LPM1_ADDR, &data1, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + p_bmg160->delay_msec(BMG160_POWER_MODE_DELAY); + /*A minimum delay of at least + 450us is required for Multiple write.*/ + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_MODE_LPM2_ADDR, &data3, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + case BMG160_MODE_SUSPEND: + data1 = BMG160_SET_BITSLICE(data1, + BMG160_MODE_LPM1, BMG160_BIT_MASK_MODE_LPM1); + data2 = BMG160_SET_BITSLICE(data2, + BMG160_MODE_LPM2_ADDR_FAST_POWERUP, + BMG160_INIT_VALUE); + data3 = BMG160_SET_BITSLICE(data2, + BMG160_MODE_LPM2_ADDR_ADV_POWERSAVING, + BMG160_INIT_VALUE); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_MODE_LPM1_ADDR, &data1, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + p_bmg160->delay_msec(BMG160_POWER_MODE_DELAY); + /*A minimum delay of at least + 450us is required for Multiple write.*/ + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_MODE_LPM2_ADDR, &data3, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + case BMG160_MODE_FASTPOWERUP: + data1 = BMG160_SET_BITSLICE(data1, + BMG160_MODE_LPM1, BMG160_BIT_MASK_MODE_LPM1); + data2 = BMG160_SET_BITSLICE(data2, + BMG160_MODE_LPM2_ADDR_FAST_POWERUP, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + data3 = BMG160_SET_BITSLICE(data2, + BMG160_MODE_LPM2_ADDR_ADV_POWERSAVING, + BMG160_INIT_VALUE); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_MODE_LPM1_ADDR, &data1, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + p_bmg160->delay_msec(BMG160_POWER_MODE_DELAY); + /*A minimum delay of at least + 450us is required for Multiple write.*/ + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_MODE_LPM2_ADDR, &data3, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + case BMG160_MODE_ADVANCEDPOWERSAVING: + /* Configuring the proper settings for auto + sleep duration */ + bmg160_get_bw(&v_bw_u8r); + bmg160_get_auto_sleep_durn( + &v_autosleepduration); + bmg160_set_auto_sleep_durn(v_autosleepduration, + v_bw_u8r); + comres += p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_MODE_LPM2_ADDR, &data2, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + /* Configuring the advanced power saving mode*/ + data1 = BMG160_SET_BITSLICE(data1, + BMG160_MODE_LPM1, BMG160_INIT_VALUE); + data2 = BMG160_SET_BITSLICE(data2, + BMG160_MODE_LPM2_ADDR_FAST_POWERUP, + BMG160_INIT_VALUE); + data3 = BMG160_SET_BITSLICE(data2, + BMG160_MODE_LPM2_ADDR_ADV_POWERSAVING, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_MODE_LPM1_ADDR, &data1, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + p_bmg160->delay_msec(BMG160_POWER_MODE_DELAY); + /*A minimum delay of at least + 450us is required for Multiple write.*/ + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_MODE_LPM2_ADDR, &data3, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + break; + } + } + else + { + comres = E_BMG160_OUT_OF_RANGE; + } + } + return comres; +} +/*! + * @brief This API is used to to do selftest to sensor + * sensor in the register 0x3C + * + * + * + * + * @param v_result_u8: The value of self test + * + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_selftest(u8 *v_result_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data1_u8 = BMG160_INIT_VALUE; + u8 v_data2_u8 = BMG160_INIT_VALUE; + + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_SELFTEST_ADDR, &v_data1_u8, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data2_u8 = BMG160_GET_BITSLICE(v_data1_u8, + BMG160_SELFTEST_ADDR_RATEOK); + v_data1_u8 = BMG160_SET_BITSLICE(v_data1_u8, + BMG160_SELFTEST_ADDR_TRIGBIST, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC(p_bmg160->dev_addr, + BMG160_SELFTEST_ADDR_TRIGBIST__REG, &v_data1_u8, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + + /* Waiting time to complete the selftest process */ + p_bmg160->delay_msec(BMG160_SELFTEST_DELAY); + + /* Reading Selftest v_result_u8 bir bist_failure */ + comres += p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_SELFTEST_ADDR_BISTFAIL__REG, &v_data1_u8, + BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data1_u8 = BMG160_GET_BITSLICE(v_data1_u8, + BMG160_SELFTEST_ADDR_BISTFAIL); + if ((v_data1_u8 == BMG160_SELFTEST_BISTFAIL) && + (v_data2_u8 == BMG160_SELFTEST_RATEOK)) + *v_result_u8 = C_BMG160_SUCCESS; + else + *v_result_u8 = C_BMG160_FAILURE; + return comres; +} +/*! + * @brief This API is used to get the auto sleep duration + * in the register 0x12 bit 0 to 2 + * + * + * + * @param v_durn_u8 : The value of gyro auto sleep duration + * sleep duration | value + * ----------------------------|---------- + * not allowed | 0 + * 4ms | 1 + * 5ms | 2 + * 8ms | 3 + * 10ms | 4 + * 15ms | 5 + * 20ms | 6 + * 40ms | 7 + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_auto_sleep_durn(u8 *v_durn_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read auto sleep duration*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_MODE_LPM2_ADDR_AUTO_SLEEP_DURN__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_durn_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_MODE_LPM2_ADDR_AUTO_SLEEP_DURN); + } + return comres; +} +/*! + * @brief This API is used to set the auto sleep duration + * in the register 0x12 bit 0 to 2 + * + * + * + * @param v_durn_u8 : The value of gyro auto sleep duration + * sleep duration | value + * ----------------------------|---------- + * not allowed | 0 + * 4ms | 1 + * 5ms | 2 + * 8ms | 3 + * 10ms | 4 + * 15ms | 5 + * 20ms | 6 + * 40ms | 7 + * + * @param v_bw_u8 : The value of selected bandwidth + * v_bw_u8 | value + * ----------------------------|---------- + * C_BMG160_NO_FILTER_U8X | 0 + * C_BMG160_BW_230HZ_U8X | 1 + * C_BMG160_BW_116HZ_u8X | 2 + * C_BMG160_BW_47HZ_u8X | 3 + * C_BMG160_BW_23HZ_u8X | 4 + * C_BMG160_BW_12HZ_u8X | 5 + * C_BMG160_BW_64HZ_u8X | 6 + * C_BMG160_BW_32HZ_u8X | 7 + * + * @note: sleep duration depends on selected power mode and bandwidth + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_auto_sleep_durn(u8 v_durn_u8, + u8 v_bw_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + u8 v_auto_sleep_durn_u8r = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* write auto sleep duration*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_MODE_LPM2_ADDR_AUTO_SLEEP_DURN__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + if (v_durn_u8 < BMG160_BIT_LENGTH_DURN) + { + switch (v_bw_u8) + { + case C_BMG160_NO_FILTER_U8X: + if (v_durn_u8 > + C_BMG160_4MS_AUTO_SLEEP_DURN_U8X) + v_auto_sleep_durn_u8r = + v_durn_u8; + else + v_auto_sleep_durn_u8r = + C_BMG160_4MS_AUTO_SLEEP_DURN_U8X; + break; + case C_BMG160_BW_230HZ_U8X: + if (v_durn_u8 > + C_BMG160_4MS_AUTO_SLEEP_DURN_U8X) + v_auto_sleep_durn_u8r = + v_durn_u8; + else + v_auto_sleep_durn_u8r = + C_BMG160_4MS_AUTO_SLEEP_DURN_U8X; + break; + case C_BMG160_BW_116HZ_U8X: + if (v_durn_u8 > + C_BMG160_4MS_AUTO_SLEEP_DURN_U8X) + v_auto_sleep_durn_u8r = + v_durn_u8; + else + v_auto_sleep_durn_u8r = + C_BMG160_4MS_AUTO_SLEEP_DURN_U8X; + break; + case C_BMG160_BW_47HZ_U8X: + if (v_durn_u8 > + C_BMG160_5MS_AUTO_SLEEP_DURN_U8X) + v_auto_sleep_durn_u8r = + v_durn_u8; + else + v_auto_sleep_durn_u8r = + C_BMG160_5MS_AUTO_SLEEP_DURN_U8X; + break; + case C_BMG160_BW_23HZ_U8X: + if (v_durn_u8 > + C_BMG160_10MS_AUTO_SLEEP_DURN_U8X) + v_auto_sleep_durn_u8r = + v_durn_u8; + else + v_auto_sleep_durn_u8r = + C_BMG160_10MS_AUTO_SLEEP_DURN_U8X; + break; + case C_BMG160_BW_12HZ_U8X: + if (v_durn_u8 > + C_BMG160_20MS_AUTO_SLEEP_DURN_U8X) + v_auto_sleep_durn_u8r = + v_durn_u8; + else + v_auto_sleep_durn_u8r = + C_BMG160_20MS_AUTO_SLEEP_DURN_U8X; + break; + case C_BMG160_BW_64HZ_U8X: + if (v_durn_u8 > + C_BMG160_10MS_AUTO_SLEEP_DURN_U8X) + v_auto_sleep_durn_u8r = + v_durn_u8; + else + v_auto_sleep_durn_u8r = + C_BMG160_10MS_AUTO_SLEEP_DURN_U8X; + break; + case C_BMG160_BW_32HZ_U8X: + if (v_durn_u8 > + C_BMG160_20MS_AUTO_SLEEP_DURN_U8X) + v_auto_sleep_durn_u8r = + v_durn_u8; + else + v_auto_sleep_durn_u8r = + C_BMG160_20MS_AUTO_SLEEP_DURN_U8X; + break; + default: + if (v_durn_u8 > + C_BMG160_4MS_AUTO_SLEEP_DURN_U8X) + v_auto_sleep_durn_u8r = + v_durn_u8; + else + v_auto_sleep_durn_u8r = + C_BMG160_4MS_AUTO_SLEEP_DURN_U8X; + break; + } + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_MODE_LPM2_ADDR_AUTO_SLEEP_DURN, + v_auto_sleep_durn_u8r); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_MODE_LPM2_ADDR_AUTO_SLEEP_DURN__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + } + else + { + comres = E_BMG160_OUT_OF_RANGE; + } + } + return comres; +} +/*! + * @brief This API is used to get the sleep duration + * in the register 0x11 bit 1 to 3 + * + * + * + * @param v_durn_u8 : The value of sleep duration + * sleep duration | value + * ----------------------------|---------- + * 2ms | 0 + * 4ms | 1 + * 5ms | 2 + * 8ms | 3 + * 10ms | 4 + * 15ms | 5 + * 18ms | 6 + * 20ms | 7 + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_sleep_durn(u8 *v_durn_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + /* read sleep duration */ + comres = p_bmg160->BMG160_BUS_READ_FUNC(p_bmg160->dev_addr, + BMG160_MODELPM1_ADDR_SLEEP_DURN__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + *v_durn_u8 = BMG160_GET_BITSLICE(v_data_u8, + BMG160_MODELPM1_ADDR_SLEEP_DURN); + } + return comres; +} +/*! + * @brief This API is used to set the sleep duration + * in the register 0x11 bit 1 to 3 + * + * + * + * @param v_durn_u8 : The value of sleep duration + * sleep duration | value + * ----------------------------|---------- + * 2ms | 0 + * 4ms | 1 + * 5ms | 2 + * 8ms | 3 + * 10ms | 4 + * 15ms | 5 + * 18ms | 6 + * 20ms | 7 + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_sleep_durn(u8 v_durn_u8) +{ + /* variable used to return the bus communication status*/ + BMG160_RETURN_FUNCTION_TYPE comres = ERROR; + u8 v_data_u8 = BMG160_INIT_VALUE; + /* check the p_bmg160 struct pointer is NULL*/ + if (p_bmg160 == BMG160_NULL) + { + return E_BMG160_NULL_PTR; + } + else + { + if (v_durn_u8 < BMG160_BIT_LENGTH_DURN) + { + /* write sleep duration*/ + comres = p_bmg160->BMG160_BUS_READ_FUNC + (p_bmg160->dev_addr, + BMG160_MODELPM1_ADDR_SLEEP_DURN__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMG160_SET_BITSLICE(v_data_u8, + BMG160_MODELPM1_ADDR_SLEEP_DURN, v_durn_u8); + comres += p_bmg160->BMG160_BUS_WRITE_FUNC + (p_bmg160->dev_addr, + BMG160_MODELPM1_ADDR_SLEEP_DURN__REG, + &v_data_u8, BMG160_GEN_READ_WRITE_DATA_LENGTH); + } + else + { + comres = E_BMG160_OUT_OF_RANGE; + } + } + return comres; +} + diff --git a/bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMG160_driver/bmg160.h b/bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMG160_driver/bmg160.h new file mode 100644 index 0000000000000000000000000000000000000000..d10b39bbb61757e3edcb501ecec0d8ca2f75c39f --- /dev/null +++ b/bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMG160_driver/bmg160.h @@ -0,0 +1,4710 @@ +/** \mainpage +* +**************************************************************************** +* Copyright (C) 2010 - 2015 Bosch Sensortec GmbH +* +* File : bmg160.h +* +* Date : 2015/04/29 +* +* Revision : 2.0.4 $ +* +* Usage: Sensor Driver for BMG160 sensor +* +**************************************************************************** +* +* \section License +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* Neither the name of the copyright holder nor the names of the +* contributors may be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDER +* OR CONTRIBUTORS BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, +* OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT NOT LIMITED TO, +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* The information provided is believed to be accurate and reliable. +* The copyright holder assumes no responsibility +* for the consequences of use +* of such information nor for any infringement of patents or +* other rights of third parties which may result from its use. +* No license is granted by implication or otherwise under any patent or +* patent rights of the copyright holder. +**************************************************************************/ +/*! \file BMG160.h + \brief Header for BMG160 API */ +/* user defined code to be added here ... */ +#ifndef __BMG160_H__ +#define __BMG160_H__ + +/*! +* @brief The following definition uses for define the data types +* +* @note While porting the API please consider the following +* @note Please check the version of C standard +* @note Are you using Linux platform +*/ + +/*! +* @brief For the Linux platform support +* Please use the types.h for your data types definitions +*/ +#ifdef __KERNEL__ + + #include + /* singed integer type*/ + typedef int8_t s8;/**< used for signed 8bit */ + typedef int16_t s16;/**< used for signed 16bit */ + typedef int32_t s32;/**< used for signed 32bit */ + typedef int64_t s64;/**< used for signed 64bit */ + + typedef u_int8_t u8;/**< used for unsigned 8bit */ + typedef u_int16_t u16;/**< used for unsigned 16bit */ + typedef u_int32_t u32;/**< used for unsigned 32bit */ + typedef u_int64_t u64;/**< used for unsigned 64bit */ + + + +#else /* ! __KERNEL__ */ + /********************************************************** + * These definition uses for define the C + * standard version data types + ***********************************************************/ + #if !defined(__STDC_VERSION__) + + /************************************************ + * compiler is C11 C standard + ************************************************/ + #if (__STDC_VERSION__ == 201112L) + + /************************************************/ + #include + /************************************************/ + + /*unsigned integer types*/ + typedef uint8_t u8;/**< used for unsigned 8bit */ + typedef uint16_t u16;/**< used for unsigned 16bit */ + typedef uint32_t u32;/**< used for unsigned 32bit */ + typedef uint64_t u64;/**< used for unsigned 64bit */ + + /*signed integer types*/ + typedef int8_t s8;/**< used for signed 8bit */ + typedef int16_t s16;/**< used for signed 16bit */ + typedef int32_t s32;/**< used for signed 32bit */ + typedef int64_t s64;/**< used for signed 64bit */ + /************************************************ + * compiler is C99 C standard + ************************************************/ + + #elif (__STDC_VERSION__ == 199901L) + + /* stdint.h is a C99 supported c library. + which is used to fixed the integer size*/ + /************************************************/ + #include + /************************************************/ + + /*unsigned integer types*/ + typedef uint8_t u8;/**< used for unsigned 8bit */ + typedef uint16_t u16;/**< used for unsigned 16bit */ + typedef uint32_t u32;/**< used for unsigned 32bit */ + typedef uint64_t u64;/**< used for unsigned 64bit */ + + /*signed integer types*/ + typedef int8_t s8;/**< used for signed 8bit */ + typedef int16_t s16;/**< used for signed 16bit */ + typedef int32_t s32;/**< used for signed 32bit */ + typedef int64_t s64;/**< used for signed 64bit */ + /************************************************ + * compiler is C89 or other C standard + ************************************************/ + + #else /* !defined(__STDC_VERSION__) */ + /*! + * @brief By default it is defined as 32 bit machine configuration + * define your data types based on your + * machine/compiler/controller configuration + */ + #define MACHINE_32_BIT + + /*! @brief + * If your machine support 16 bit + * define the MACHINE_16_BIT + */ + #ifdef MACHINE_16_BIT + #include + /*signed integer types*/ + typedef signed char s8;/**< used for signed 8bit */ + typedef signed short int s16;/**< used for signed 16bit */ + typedef signed long int s32;/**< used for signed 32bit */ + + #if defined(LONG_MAX) && LONG_MAX == 0x7fffffffffffffffL + typedef long int s64;/**< used for signed 64bit */ + typedef unsigned long int u64;/**< used for unsigned 64bit */ + #elif defined(LLONG_MAX) && (LLONG_MAX == 0x7fffffffffffffffLL) + typedef long long int s64;/**< used for signed 64bit */ + typedef unsigned long long int u64;/**< used for unsigned 64bit */ + #else + #warning Either the correct data type for signed 64 bit integer \ + could not be found, or 64 bit integers are not supported in your environment. + #warning If 64 bit integers are supported on your platform, \ + please set s64 manually. + #endif + + /*unsigned integer types*/ + typedef unsigned char u8;/**< used for unsigned 8bit */ + typedef unsigned short int u16;/**< used for unsigned 16bit */ + typedef unsigned long int u32;/**< used for unsigned 32bit */ + + /* If your machine support 32 bit + define the MACHINE_32_BIT*/ + #elif defined MACHINE_32_BIT + /*signed integer types*/ + typedef signed char s8;/**< used for signed 8bit */ + typedef signed short int s16;/**< used for signed 16bit */ + typedef signed int s32;/**< used for signed 32bit */ + typedef signed long long int s64;/**< used for signed 64bit */ + + /*unsigned integer types*/ + typedef unsigned char u8;/**< used for unsigned 8bit */ + typedef unsigned short int u16;/**< used for unsigned 16bit */ + typedef unsigned int u32;/**< used for unsigned 32bit */ + typedef unsigned long long int u64;/**< used for unsigned 64bit */ + + /* If your machine support 64 bit + define the MACHINE_64_BIT*/ + #elif defined MACHINE_64_BIT + /*signed integer types*/ + typedef signed char s8;/**< used for signed 8bit */ + typedef signed short int s16;/**< used for signed 16bit */ + typedef signed int s32;/**< used for signed 32bit */ + typedef signed long int s64;/**< used for signed 64bit */ + + /*unsigned integer types*/ + typedef unsigned char u8;/**< used for unsigned 8bit */ + typedef unsigned short int u16;/**< used for unsigned 16bit */ + typedef unsigned int u32;/**< used for unsigned 32bit */ + typedef unsigned long int u64;/**< used for unsigned 64bit */ + + #else + #warning The data types defined above which not supported \ + define the data types manually + #endif + #endif + + /*** This else will execute for the compilers + * which are not supported the C standards + * Like C89/C99/C11***/ + #else + /*! + * @brief By default it is defined as 32 bit machine configuration + * define your data types based on your + * machine/compiler/controller configuration + */ + #define MACHINE_32_BIT + + /* If your machine support 16 bit + define the MACHINE_16_BIT*/ + #ifdef MACHINE_16_BIT + #include + /*signed integer types*/ + typedef signed char s8;/**< used for signed 8bit */ + typedef signed short int s16;/**< used for signed 16bit */ + typedef signed long int s32;/**< used for signed 32bit */ + + #if defined(LONG_MAX) && LONG_MAX == 0x7fffffffffffffffL + typedef long int s64;/**< used for signed 64bit */ + typedef unsigned long int u64;/**< used for unsigned 64bit */ + #elif defined(LLONG_MAX) && (LLONG_MAX == 0x7fffffffffffffffLL) + typedef long long int s64;/**< used for signed 64bit */ + typedef unsigned long long int u64;/**< used for unsigned 64bit */ + #else + #warning Either the correct data type for signed 64 bit integer \ + could not be found, or 64 bit integers are not supported in your environment. + #warning If 64 bit integers are supported on your platform, \ + please set s64 manually. + #endif + + /*unsigned integer types*/ + typedef unsigned char u8;/**< used for unsigned 8bit */ + typedef unsigned short int u16;/**< used for unsigned 16bit */ + typedef unsigned long int u32;/**< used for unsigned 32bit */ + + /*! @brief If your machine support 32 bit + define the MACHINE_32_BIT*/ + #elif defined MACHINE_32_BIT + /*signed integer types*/ + typedef signed char s8;/**< used for signed 8bit */ + typedef signed short int s16;/**< used for signed 16bit */ + typedef signed int s32;/**< used for signed 32bit */ + typedef signed long long int s64;/**< used for signed 64bit */ + + /*unsigned integer types*/ + typedef unsigned char u8;/**< used for unsigned 8bit */ + typedef unsigned short int u16;/**< used for unsigned 16bit */ + typedef unsigned int u32;/**< used for unsigned 32bit */ + typedef unsigned long long int u64;/**< used for unsigned 64bit */ + + /* If your machine support 64 bit + define the MACHINE_64_BIT*/ + #elif defined MACHINE_64_BIT + /*signed integer types*/ + typedef signed char s8;/**< used for signed 8bit */ + typedef signed short int s16;/**< used for signed 16bit */ + typedef signed int s32;/**< used for signed 32bit */ + typedef signed long int s64;/**< used for signed 64bit */ + + /*unsigned integer types*/ + typedef unsigned char u8;/**< used for unsigned 8bit */ + typedef unsigned short int u16;/**< used for unsigned 16bit */ + typedef unsigned int u32;/**< used for unsigned 32bit */ + typedef unsigned long int u64;/**< used for unsigned 64bit */ + + #else + #warning The data types defined above which not supported \ + define the data types manually + #endif + #endif +#endif +/***************************************************************/ +/**\name BUS READ AND WRITE FUNCTION POINTERS */ +/***************************************************************/ +/*! + @brief Define the calling convention of YOUR bus communication routine. + @note This includes types of parameters. This example shows the + configuration for an SPI bus link. + + If your communication function looks like this: + + write_my_bus_xy(u8 device_addr, u8 register_addr, + u8 * data, u8 length); + + The BMG160_WR_FUNC_PTR would equal: + + BMG160_WR_FUNC_PTR s8 (* bus_write)(u8, + u8, u8 *, u8) + + Parameters can be mixed as needed refer to the + refer BMG160_BUS_WRITE_FUNC macro. + + +*/ +/* defines the calling parameter types of the BMG160_WR_FUNCTION */ +#define BMG160_BUS_WR_RETURN_TYPE s8 + +/* links the order of parameters defined in +BMG160_BUS_WR_PARAM_TYPE to function calls used inside the API*/ +#define BMG160_BUS_WR_PARAM_TYPES u8, u8,\ +u8 *, u8 + +/* links the order of parameters defined in +BMG160_BUS_WR_PARAM_TYPE to function calls used inside the API*/ +#define BMG160_BUS_WR_PARAM_ORDER(device_addr, register_addr,\ +register_data, wr_len) + +/* never change this line */ +#define BMG160_BUS_WRITE_FUNC(device_addr, register_addr,\ +register_data, wr_len) bus_write(device_addr, register_addr,\ +register_data, wr_len) +/**< link macro between API function calls and bus read function + @note The bus write function can change since this is a + system dependant issue. + + If the bus_read parameter calling order is like: reg_addr, + reg_data, wr_len it would be as it is here. + + If the parameters are differently ordered or your communication + function like I2C need to know the device address, + you can change this macro accordingly. + + + BMG160_BUS_READ_FUNC(dev_addr, reg_addr, reg_data, wr_len)\ + bus_read(dev_addr, reg_addr, reg_data, wr_len) + + This macro lets all API functions call YOUR communication routine in a + way that equals your definition in the + refer BMG160_WR_FUNC_PTR definition. + + @note: this macro also includes the "MSB='1' + for reading BMG160 addresses. + +*/ +/*defines the return parameter type of the BMG160_RD_FUNCTION +*/ +#define BMG160_BUS_RD_RETURN_TYPE s8 +/* defines the calling parameter types of the BMG160_RD_FUNCTION +*/ +#define BMG160_BUS_RD_PARAM_TYPES u8, u8,\ +u8 *, u8 +/* links the order of parameters defined in \ +BMG160_BUS_RD_PARAM_TYPE to function calls used inside the API +*/ +#define BMG160_BUS_RD_PARAM_ORDER (device_addr, register_addr,\ +register_data) +/* never change this line */ +#define BMG160_BUS_READ_FUNC(device_addr, register_addr,\ +register_data, rd_len)bus_read(device_addr, register_addr,\ +register_data, rd_len) +/* defines the return parameter type of the BMG160_RD_FUNCTION +*/ +#define BMG160_BURST_RD_RETURN_TYPE s8 +/* defines the calling parameter types of the BMG160_RD_FUNCTION +*/ +#define BMG160_BURST_RD_PARAM_TYPES u8,\ +u8, u8 *, s32 +/* links the order of parameters defined in \ +BMG160_BURST_RD_PARAM_TYPE to function calls used inside the API +*/ +#define BMG160_BURST_RD_PARAM_ORDER (device_addr, register_addr,\ +register_data) +/* never change this line */ +#define BMG160_BURST_READ_FUNC(device_addr, register_addr,\ +register_data, rd_len)burst_read(device_addr, \ +register_addr, register_data, rd_len) +/*! + * @brief defines the return parameter type of the BMG160_DELAY_FUNCTION +*/ +#define BMG160_DELAY_RETURN_TYPE void +/* never change this line */ +#define BMG160_DELAY_FUNC(delay_in_msec)\ + delay_func(delay_in_msec) + +#define BMG160_RETURN_FUNCTION_TYPE s8 +/*This refers BMG160 return type as signed */ +/***************************************************************/ +/**\name DEVICE ADDRESS OF BMG160 */ +/***************************************************************/ +#define BMG160_I2C_ADDR1 (0x68) +#define BMG160_I2C_ADDR2 (0x69) + +/***************************************************************/ +/**\name REGISTER ADDRESS DEFINITION */ +/***************************************************************/ + +/*******************************************/ +/**\name CHIP ID */ +/*******************************************/ +#define BMG160_CHIP_ID_ADDR (0x00) +/**
> bitname##__POS) + +/* Set bit slice */ +#define BMG160_SET_BITSLICE(regvar, bitname, val)\ +((regvar&~bitname##__MSK)|((val< Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_init(struct bmg160_t *bmg160); +/***********************************************/ +/**\name DATA READ XYZ */ +/**********************************************/ +/*! + * @brief Reads Rate data X in the registers 0x02 to 0x03 + * + * + * + * + * @param v_data_x_s16: The value of gyro x axis data + * + * + * @return results of bus communication function + * @retval 0 -> Success +* @retval -1 -> Error + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_data_X(s16 *v_data_x_s16); +/*! + * @brief Reads Rate data Y in the registers 0x04 to 0x05 + * + * + * + * + * @param v_data_y_s16: The value of gyro y axis data + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_data_Y(s16 *v_data_y_s16); +/*! + * @brief Reads Rate data Z in the registers 0x06 to 0x07 + * + * + * @param v_data_z_s16: The value of gyro z axis data + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_data_Z(s16 *v_data_z_s16); +/*! + * @brief Reads data X,Y and Z from register location 0x02 to 0x07 + * + * + * + * + * @param data: The value of gyro xyz axis data + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_data_XYZ(struct bmg160_data_t *data); +/*! + * @brief Reads data X,Y,Z and Interrupts + * from register location 0x02 to 0x07 + * + * + * @param data: The value of gyro xyz axis data and interrupt status + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_data_XYZI(struct bmg160_data_t *data); +/***********************************************/ +/**\name TEMPERATURE DATA READ */ +/**********************************************/ +/*! + * @brief Reads Temperature from register location 0x08 + * + * + * + * + * @param v_temp_s8: The value of temperature + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_temp(s8 *v_temp_s8); +/***********************************************/ +/**\name COMMON READ AND WRITE FUNCTIONS */ +/**********************************************/ +/*! + * @brief + * This API reads the data from + * the given register + * + * + * @param v_addr_u8 -> Address of the register + * @param v_data_u8 -> The data from the register + * @param v_len_u8 -> no of bytes to read + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMG160_RETURN_FUNCTION_TYPE bmg160_read_register(u8 v_addr_u8, + u8 *v_data_u8, u8 v_len_u8); +/*! + * @brief + * This API reads the data from + * the given register + * + * + * @param v_addr_u8 -> Address of the register + * @param v_data_u8 -> The data from the register + * @param v_len_u32 -> no of bytes to read + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMG160_RETURN_FUNCTION_TYPE bmg160_burst_read(u8 v_addr_u8, + u8 *v_data_u8, u32 v_len_u32); +/*! + * @brief + * This API write the data to + * the given register + * + * + * @param v_addr_u8 -> Address of the register + * @param v_data_u8 -> The data from the register + * @param v_len_u8 -> no of bytes to read + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMG160_RETURN_FUNCTION_TYPE bmg160_write_register(u8 v_addr_u8, + u8 *v_data_u8, u8 v_len_u8); +/***********************************************/ +/**\name INTERRUPT STATUS */ +/**********************************************/ +/*! + * @brief This api used to reads interrupt status of + * any motion and high rate in the register 0x09 + * @note any motion bit -> 2 + * @note high rate bit -> 1 + * + * + * + * @param v_stat0_data_u8 : The interrupt status of + * any motion and high rate + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_intr_stat_reg_zero( + u8 *v_stat0_data_u8); +/*! + * @brief This api used to reads the interrupt status of + * data, auto_offset, fast_offset and fifo_int in the register 0x0A + * @note data bit -> 7 + * @note auto_offset bit -> 6 + * @note fast_offset bit -> 5 + * @note fifo_int bit -> 4 + * + * + * + * @param + * v_stat1_data_u8 : The interrupt status of + * data, auto_offset, fast_offset and fifo_int + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_intr_stat_reg_one( + u8 *v_stat1_data_u8); +/*! + * @brief This api used to reads the interrupt status of + * @note any motion sign, any motion first_z, any motion + * first_x and any motion first_y in the register 0x0B + * @note any motion sign bit -> 3 + * @note any motion first_z bit -> 2 + * @note any motion first_x bit -> 1 + * @note any motion first_y bit -> 0 + * + * + * + * @param + * v_stat2_data_u8 : Pointer holding the the interrupt status of + * any motion sign, any motion first_z, + * any motion first_x and any motion first_y + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_intr_stat_reg_two( + u8 *v_stat2_data_u8); +/*! +* @brief This api used to reads the interrupt status of +* high_rate sign, high_rate first_z, high_rate first_x +* and high_rate first_y in the register 0x0C +* @note high_rate sign bit -> 3 +* @note high_rate first_z bit -> 2 +* @note high_rate first_x bit -> 1 +* @note high_rate first_y bit -> 0 +* @note high_rate first_y bit -> 0 +* +* +* +* @param +* v_stat3_data_u8 : The interrupt status of +* high_rate sign, high_rate first_z, +* high_rate first_x and high_rate first_y +* +* +* @return results of bus communication function +* @retval 0 -> Success +* @retval -1 -> Error +* +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_intr_stat_reg_three( + u8 *v_stat3_data_u8); +/***********************************************/ +/**\name RANGE*/ +/**********************************************/ +/*! + * @brief This API is used to get + * the range in the register 0x0F bits from 0 to 2 + * + * @param v_range_u8 : The value of gyro range + * value | range + * ----------|----------- + * 0x00 | BMG160_RANGE_2000 + * 0x01 | BMG160_RANGE_1000 + * 0x02 | BMG160_RANGE_500 + * 0x03 | BMG160_RANGE_250 + * 0x04 | BMG160_RANGE_125 + * + * + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_range_reg(u8 *v_range_u8); +/*! + * @brief This API is used to set + * the range in the register 0x0F bits from 0 to 2 + * + * @param v_range_u8 : The value of gyro range + * value | range + * ----------|----------- + * 0x00 | BMG160_RANGE_2000 + * 0x01 | BMG160_RANGE_1000 + * 0x02 | BMG160_RANGE_500 + * 0x03 | BMG160_RANGE_250 + * 0x04 | BMG160_RANGE_125 + * + * + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_range_reg(u8 v_range_u8); +/***********************************************/ +/**\name BANDWIDTH */ +/**********************************************/ +/*! + * @brief This API is used to get the gyro bandwidth + * in the register 0x10 bits from 0 to 3 + * + * + * + * + * + * @param v_bw_u8: The value of gyro bandwidth + * value | bandwidth + * ---------|--------------- + * 0x00 | BMG160_BW_500_HZ + * 0x01 | BMG160_BW_230_HZ + * 0x02 | BMG160_BW_116_HZ + * 0x03 | BMG160_BW_47_HZ + * 0x04 | BMG160_BW_23_HZ + * 0x05 | BMG160_BW_12_HZ + * 0x06 | BMG160_BW_64_HZ + * 0x07 | BMG160_BW_32_HZ + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_bw(u8 *v_bw_u8); +/*! + * @brief This API is used to set the gyro bandwidth + * in the register 0x10 bits from 0 to 3 + * + * + * + * + * + * @param v_bw_u8: The value of gyro bandwidth + * value | bandwidth + * ---------|--------------- + * 0x00 | BMG160_BW_500_HZ + * 0x01 | BMG160_BW_230_HZ + * 0x02 | BMG160_BW_116_HZ + * 0x03 | BMG160_BW_47_HZ + * 0x04 | BMG160_BW_23_HZ + * 0x05 | BMG160_BW_12_HZ + * 0x06 | BMG160_BW_64_HZ + * 0x07 | BMG160_BW_32_HZ + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_bw(u8 v_bw_u8); +/***********************************************/ +/**\name POWER MODE TRIGGER */ +/**********************************************/ +/*! + * @brief This API used to get the status of + * External Trigger selection in the register 0x12h bits from 4 to 5 + * + * + * + * + * @param v_pwu_ext_tri_select_u8 : The value of External Trigger selection + * v_pwu_ext_tri_select_u8 | Trigger source + * --------------------------|------------------------- + * 0x00 | No + * 0x01 | INT1 pin + * 0x02 | INT2 pin + * 0x03 | SDO pin(SPI3 mode) + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_pmu_ext_tri_select( + u8 *v_pwu_ext_tri_select_u8); +/*! + * @brief This API used to set the status of + * External Trigger selection in the register 0x12h bits from 4 to 5 + * + * + * + * + * @param v_pwu_ext_tri_select_u8 : The value of External Trigger selection + * v_pwu_ext_tri_select_u8 | Trigger source + * --------------------------|------------------------- + * 0x00 | No + * 0x01 | INT1 pin + * 0x02 | INT2 pin + * 0x03 | SDO pin(SPI3 mode) + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_pmu_ext_tri_select( + u8 v_pwu_ext_tri_select_u8); +/***********************************************/ +/**\name HIGH BANDWIDTH*/ +/**********************************************/ +/*! + * @brief This API is used to get data high bandwidth + * in the register 0x13 bit 7 + * + * + * + * @param v_high_bw_u8 : The value of high bandwidth + * value | Description + * ---------|-------------- + * 1 | unfiltered + * 0 | filtered + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_high_bw(u8 *v_high_bw_u8); +/*! + * @brief This API is used to set data high bandwidth + * in the register 0x13 bit 7 + * + * + * + * @param v_high_bw_u8 : The value of high bandwidth + * value | Description + * ---------|-------------- + * 1 | unfiltered + * 0 | filtered + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_high_bw(u8 v_high_bw_u8); +/***********************************************/ +/**\name SHADOW DIS*/ +/**********************************************/ +/*! + * @brief This API is used to get the shadow dis + * in the register 0x13 bit 6 + * + * + * + * @param v_shadow_dis_u8 : The value of shadow dis + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_shadow_dis(u8 *v_shadow_dis_u8); +/*! + * @brief This API is used to set the shadow dis + * in the register 0x13 bit 6 + * + * + * + * @param v_shadow_dis_u8 : The value of shadow dis + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_shadow_dis(u8 v_shadow_dis_u8); +/***********************************************/ +/**\name OFFSET RESET */ +/**********************************************/ +/*! + * This function is used for the soft reset + * The soft reset register will be written with 0xB6 in the register 0x14. + * + * + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_soft_rst(void); +/***********************************************/ +/**\name DATA INTERRUPT */ +/**********************************************/ +/*! + * @brief This API is used to get the data(data_enable) + * interrupt enable bits of the sensor in the registers 0x15 bit 7 + * + * + * + * + * @param v_data_enable_u8 : The value of data enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_data_enable(u8 *v_data_enable_u8); +/*! + * @brief This API is used to set the data(data_enable) + * interrupt enable bits of the sensor in the registers 0x15 bit 7 + * + * + * + * + * @param v_data_enable_u8 : The value of data enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_data_enable(u8 v_data_enable_u8); +/***********************************************/ +/**\name FIFO INTERRUPT */ +/**********************************************/ +/*! + * @brief This API is used to get the fifo(fifo_enable) + * interrupt enable bits of the sensor in the registers 0x15 bit 6 + * + * + * + * + * @param v_fifo_enable_u8 : The value of fifo enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_fifo_enable(u8 *v_fifo_enable_u8); +/*! + * @brief This API is used to set the fifo(fifo_enable) + * interrupt enable bits of the sensor in the registers 0x15 bit 6 + * + * + * + * + * @param v_fifo_enable_u8 : The value of fifo enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_fifo_enable(u8 v_fifo_enable_u8); +/***********************************************/ +/**\name AUTO OFFSET INTERRUPT */ +/**********************************************/ +/*! + * @brief This API is used to get + * the auto offset(auto_offset_enable) interrupt enable bits of + * the sensor in the registers 0x15 bit 3 + * + * + * + * @param v_offset_enable_u8 : The value of offset enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_auto_offset_enable( + u8 *v_offset_enable_u8); +/*! + * @brief This API is used to set + * the auto offset(auto_offset_enable) interrupt enable bits of + * the sensor in the registers 0x15 bit 3 + * + * + * + * @param v_offset_enable_u8 : The value of offset enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_auto_offset_enable( + u8 v_offset_enable_u8); +/***********************************************/ +/**\name OUTPUT TYPE AND LEVEL CONFIGURATION FOR INTERRUPT */ +/**********************************************/ +/*! + * @brief This API is used to get + * the output type status in the register 0x16. + * @note INT1 -> bit 1 + * @note INT2 -> bit 3 + * + * @param v_param_u8: The value of output type selection number + * v_param_u8| output type + * ------------|-------------- + * 0 | BMG160_INTR1 + * 1 | BMG160_INTR2 + * + * @param v_intr_output_type_u8: The value of output type + * value | output + * -----------|------------- + * 1 | open drain + * 0 | push pull + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_intr_output_type(u8 v_param_u8, + u8 *v_intr_output_type_u8); +/*! + * @brief This API is used to set + * the output type status in the register 0x16. + * @note INT1 -> bit 1 + * @note INT2 -> bit 3 + * + * @param v_param_u8: The value of output type selection number + * v_param_u8| output type + * ------------|-------------- + * 0 | BMG160_INTR1 + * 1 | BMG160_INTR2 + * + * @param v_intr_output_type_u8: The value of output type + * value | output + * -----------|------------- + * 1 | open drain + * 0 | push pull + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_intr_output_type(u8 v_param_u8, + u8 v_intr_output_type_u8); +/*! + * @brief This API is used to get + * Active Level status in the register 0x16 + * @note INT1 -> bit 0 + * @note INT2 -> bit 2 + * + * @param v_param_u8: The value of Active Level selection number + * v_param_u8| Active Level + * ------------|-------------- + * 0 | BMG160_INTR1 + * 1 | BMG160_INTR2 + * + * @param v_intr_level_u8: The value of Active Level status value + * value | Active Level + * -----------|------------- + * 1 | Active HIGH + * 0 | Active LOW + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_intr_level(u8 v_param_u8, + u8 *v_intr_level_u8); +/*! + * @brief This API is used to set + * Active Level status in the register 0x16 + * @note INT1 -> bit 0 + * @note INT2 -> bit 2 + * + * @param v_param_u8: The value of Active Level selection number + * v_param_u8| Active Level + * ------------|-------------- + * 0 | BMG160_INTR1 + * 1 | BMG160_INTR2 + * + * @param v_intr_level_u8: The value of Active Level status value + * value | Active Level + * -----------|------------- + * 1 | Active HIGH + * 0 | Active LOW + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_intr_level(u8 v_param_u8, + u8 v_intr_level_u8); +/***********************************************/ +/**\name HIGH RATE INTERRUPT */ +/**********************************************/ +/*! + * @brief This API is used to get + * the high rate(int1_high) interrupt1 enable bits of + * the sensor in the registers 0x17 bit 3 + * + * + * + * @param v_intr1_u8 : The value of interrupt1 high_rate enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_intr1_highrate(u8 *v_intr1_u8); +/*! + * @brief This API is used to set + * the high rate(int1_high) interrupt1 enable bits of + * the sensor in the registers 0x17 bit 3 + * + * + * + * @param v_intr1_u8 : The value of interrupt1 high_rate enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_intr1_highrate( + u8 v_intr1_u8); +/***********************************************/ +/**\name ANY MOTION INTERRUPT */ +/**********************************************/ +/*! + * @brief This API is used to get + * the any motion(int1_any) interrupt1 enable bits of + * the sensor in the registers 0x17 bit 1 + * + * + * + * @param v_int1r_any_motion_u8 : The value of any motion interrupt1 + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_intr1_any_motion( + u8 *v_int1r_any_motion_u8); +/*! + * @brief This API is used to set + * the any motion(int1_any) interrupt1 enable bits of + * the sensor in the registers 0x17 bit 1 + * + * + * + * @param v_int1r_any_motion_u8 : The value of any motion interrupt1 + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_intr1_any_motion( + u8 v_int1r_any_motion_u8); +/***********************************************/ +/**\name DATA INTERRUPT */ +/**********************************************/ +/*! + * @brief This API is used to get + * the data interrupt1 and interrupt2(int1_data and int2_data) + * in the register 0x18 + * @note INT1 -> bit 0 + * @note INT2 -> bit 7 + * + * @param v_axis_u8: data interrupt selection + * v_axis_u8 | Data interrupt + * ------------|-------------- + * 0 | BMG160_INTR1_DATA + * 1 | BMG160_INTR2_DATA + * + * @param v_intr_data_u8: The value of data interrupt1 or interrupt2 + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_intr_data(u8 v_axis_u8, + u8 *v_intr_data_u8); +/*! + * @brief This API is used to set + * the data interrupt1 and interrupt2(int1_data and int2_data) + * in the register 0x18 + * @note INT1 -> bit 0 + * @note INT2 -> bit 7 + * + * @param v_axis_u8: data interrupt selection + * v_axis_u8 | Data interrupt + * ------------|-------------- + * 0 | BMG160_INTR1_DATA + * 1 | BMG160_INTR2_DATA + * + * @param v_intr_data_u8: The value of data interrupt1 or interrupt2 + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_intr_data(u8 v_axis_u8, + u8 v_intr_data_u8); +/***********************************************/ +/**\name OFFSET AND AUTO OFFSET ENABLE */ +/**********************************************/ +/*! + * @brief This API is used to get + * the fast offset(intr2_fast_offset) and auto offset(intr2_auto_offset) + * of interrupt2 in the register 0x18 + * @note int2_fast_offset -> bit 6 + * @note int2_auto_offset -> bit 4 + * + * @param v_axis_u8: The value of fast/auto offset interrupts selection + * v_axis_u8 | Data interrupt + * ------------|-------------- + * 1 | BMG160_FAST_OFFSET + * 2 | BMG160_AUTO_OFFSET + * + * @param v_intr2_offset_u8: The value of fast/auto offset enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_intr2_offset(u8 v_axis_u8, + u8 *v_intr2_offset_u8); +/*! + * @brief This API is used to set + * the fast offset(intr2_fast_offset) and auto offset(intr2_auto_offset) + * of interrupt2 in the register 0x18 + * @note int2_fast_offset -> bit 6 + * @note int2_auto_offset -> bit 4 + * + * @param v_axis_u8: The value of fast/auto offset interrupts selection + * v_axis_u8 | Data interrupt + * ------------|-------------- + * 1 | BMG160_FAST_OFFSET + * 2 | BMG160_AUTO_OFFSET + * + * @param v_intr2_offset_u8: The value of fast/auto offset enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_intr2_offset(u8 v_axis_u8, + u8 v_intr2_offset_u8); +/*! + * @brief This API is used to get + * the fast offset(int1_fast_offset) and auto offset(int1_auto_offset) + * of interrupt1 in the register 0x18 + * @note int1_fast_offset -> bit 1 + * @note int1_auto_offset -> bit 3 + * + * @param v_axis_u8: The value of fast/auto offset interrupts selection + * v_axis_u8 | Data interrupt + * ------------|-------------- + * 1 | BMG160_FAST_OFFSET + * 2 | BMG160_AUTO_OFFSET + * + * @param v_intr1_offset_u8: The value of fast/auto offset + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_intr_offset(u8 v_axis_u8, + u8 *v_intr1_offset_u8); +/*! + * @brief This API is used to set + * the fast offset(int1_fast_offset) and auto offset(int1_auto_offset) + * of interrupt1 in the register 0x18 + * @note int1_fast_offset -> bit 1 + * @note int1_auto_offset -> bit 3 + * + * @param v_axis_u8: The value of fast/auto offset interrupts selection + * v_axis_u8 | Data interrupt + * ------------|-------------- + * 1 | BMG160_FAST_OFFSET + * 2 | BMG160_AUTO_OFFSET + * + * @param v_intr1_offset_u8: The value of fast/auto offset + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_intr1_offset(u8 v_axis_u8, + u8 v_intr1_offset_u8); +/***********************************************/ +/**\name FIFO ENABLE */ +/**********************************************/ +/*! + * @brief This API is used to get + * the fifo(int2_fifo) interrupt2 enable bits of + * the sensor in the registers 0x18 bit 5 + * + * + * + * @param v_intr_fifo_u8 : The interrupt2 fifo value + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_intr2_fifo(u8 *v_intr_fifo_u8); +/*! + * @brief This API is used to get + * the fifo(int1_fifo) interrupt1 enable bits of + * the sensor in the registers 0x18 bit 5 + * + * + * + * @param v_intr_fifo_u8 : The interrupt1 fifo value + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_intr1_fifo(u8 *v_intr_fifo_u8); +/*! + * @brief This API is used to set the value of + * the fifo interrupt1 and interrupt2(int1_fifo and int2_fifo) + * in the register 0x18 + * @note int1_fifo -> bit 2 + * @note int2_fifo -> bit 5 + * + * @param v_axis_u8: The value of fifo interrupts selection + * v_axis_u8 | fifo interrupt + * ------------|-------------- + * 0 | BMG160_INTR1 + * 1 | BMG160_INTR2 + * + * @param v_intr_fifo_u8: the value of int1_fifo/int2_fifo enable/disable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_intr_fifo(u8 v_axis_u8, + u8 v_intr_fifo_u8); +/***********************************************/ +/**\name HIGH RATE ENABLE */ +/**********************************************/ +/*! + * @brief This API is used to get + * the high rate(int2_high_rate) interrupt2 enable bits of + * the sensor in the registers 0x19 bit 3 + * + * + * + * @param v_intr2_highrate_u8 : The interrupt2 high_rate value + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_intr2_highrate( + u8 *v_intr2_highrate_u8); +/*! + * @brief This API is used to set + * the high rate(int2_high_rate) interrupt2 enable bits of + * the sensor in the registers 0x19 bit 3 + * + * + * + * @param v_intr2_highrate_u8 : The interrupt2 high_rate value + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_intr2_highrate( + u8 v_intr2_highrate_u8); +/***********************************************/ +/**\name ANY MOTION ENABLE */ +/**********************************************/ +/*! + * @brief This API is used to get + * the any motion(int2_any_motion) interrupt2 enable bits of + * the sensor in the registers 0x19 bit 1 + * + * + * + * @param v_intr2_any_motion_u8 : The value of interrupt2 any_motion + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_intr2_any_motion( + u8 *v_intr2_any_motion_u8); +/*! + * @brief This API is used to set + * the any motion(int2_any_motion) interrupt2 enable bits of + * the sensor in the registers 0x19 bit 1 + * + * + * + * @param v_intr2_any_motion_u8 : The value of interrupt2 any_motion + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_intr2_any_motion( + u8 v_intr2_any_motion_u8); +/***********************************************/ +/**\name OFFSET UNFILT ENABLE */ +/**********************************************/ +/*! + * @brief This API is used to get + * the slow offset and fast offset unfilt data in the register 0x1A and 1B + * @note slow_offset_unfilt -> 0x1A bit 5 + * @note fast_offset_unfilt -> 0x1B bit 7 + * + * @param v_param_u8: The value of fast/slow offset unfilt data selection + * v_param_u8 | offset selection + * ------------|-------------- + * 0 | BMG160_SLOW_OFFSET + * 1 | BMG160_FAST_OFFSET + * + * @param v_offset_unfilt_u8: The value of fast/slow offset unfilt data + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_offset_unfilt(u8 v_param_u8, + u8 *v_offset_unfilt_u8); +/*! + * @brief This API is used to set + * the slow offset and fast offset unfilt data in the register 0x1A and 1B + * @note slow_offset_unfilt -> 0x1A bit 5 + * @note fast_offset_unfilt -> 0x1B bit 7 + * + * @param v_param_u8: The value of fast/slow offset unfilt data selection + * v_param_u8 | offset selection + * ------------|-------------- + * 0 | BMG160_SLOW_OFFSET + * 1 | BMG160_FAST_OFFSET + * + * @param v_offset_unfilt_u8: The value of fast/slow offset unfilt data + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_offset_unfilt(u8 v_param_u8, + u8 v_offset_unfilt_u8); +/*! + * @brief This API is used to get + * the any motion and high rate unfilt data in the register 0x1A + * @note any_unfilt_data -> bit 1 + * @note high_unfilt_data -> bit 3 + * + * @param v_param_u8: The value of any/high offset unfilt data selection + * v_param_u8 | offset selection + * ------------|-------------- + * 1 | BMG160_HIGHRATE_UNFILT_DATA + * 3 | BMG160_ANY_MOTION_UNFILT_DATA + * + * @param v_unfilt_data_u8: The value of any/high unfilt data + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_unfilt_data(u8 v_param_u8, + u8 *v_unfilt_data_u8); +/*! + * @brief This API is used to set + * the any motion and high rate unfilt data in the register 0x1A + * @note any_unfilt_data -> bit 1 + * @note high_unfilt_data -> bit 3 + * + * @param v_param_u8: The value of any/high offset unfilt data selection + * v_param_u8 | offset selection + * ------------|-------------- + * 1 | BMG160_HIGHRATE_UNFILT_DATA + * 3 | BMG160_ANY_MOTION_UNFILT_DATA + * + * @param v_unfilt_data_u8: The value of any/high unfilt data + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_unfilt_data(u8 v_param_u8, + u8 v_unfilt_data_u8); +/***********************************************/ +/**\name ANY-MOTION CONFIGURATION */ +/**********************************************/ +/*! + * @brief This API is used to get Any motion Threshold + * in the register 0x1B bit from 0 to 6 + * + * + * + * @param v_any_motion_thres_u8 : The value of any_motion Threshold + * + * @note Any motion threshold can be calculate using + * @note ((1+ v_any_motion_thres_u8)*16LSB) + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_any_motion_thres( + u8 *v_any_motion_thres_u8); +/*! + * @brief This API is used to set Any motion Threshold + * in the register 0x1B bit from 0 to 6 + * + * + * + * @param v_any_motion_thres_u8 : The value of any_motion Threshold + * + * @note Any motion threshold can be calculate using + * @note ((1+ v_any_motion_thres_u8)*16LSB) + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_any_motion_thres( + u8 v_any_motion_thres_u8); +/*! + * @brief This API is used to get the awake Duration + * in the register 0x1C bit 6 and 7 + * + * + * + * @param v_awake_durn_u8 : The value of awake Duration + * value | Duration + * ---------|----------- + * 0x00 | 8 samples + * 0x01 | 16 samples + * 0x02 | 32 samples + * 0x03 | 64 samples + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_awake_durn(u8 *v_awake_durn_u8); +/*! + * @brief This API is used to set the awake Duration + * in the register 0x1C bit 6 and 7 + * + * + * + * @param v_awake_durn_u8 : The value of awake Duration + * value | Duration + * ---------|----------- + * 0x00 | 8 samples + * 0x01 | 16 samples + * 0x02 | 32 samples + * 0x03 | 64 samples + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_awake_durn(u8 v_awake_durn_u8); +/*! + * @brief This API is used to get + * the any motion Duration samples in the register 0x1C bit 4 and 5 + * + * + * + * @param v_durn_sample_u8 : The value of any motion duration samples + * value | Samples + * ---------|----------- + * 0x00 | 4 samples + * 0x01 | 8 samples + * 0x02 | 12 samples + * 0x03 | 16 samples + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_any_motion_durn_sample( + u8 *v_durn_sample_u8); +/*! + * @brief This API is used to set + * the any motion Duration samples in the register 0x1C bit 4 and 5 + * + * + * + * @param v_durn_sample_u8 : The value of any motion duration samples + * value | Samples + * ---------|----------- + * 0x00 | 4 samples + * 0x01 | 8 samples + * 0x02 | 12 samples + * 0x03 | 16 samples + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_any_motion_durn_sample( + u8 v_durn_sample_u8); +/*! + * @brief This API is used to get the status of + * Any motion interrupt axis(X,Y,Z) enable channel + * @note BMG160_X_AXIS -> bit 0 + * @note BMG160_Y_AXIS -> bit 1 + * @note BMG160_Z_AXIS -> bit 2 + * + * @param v_channel_u8 : The value of Any Enable channel number + * v_channel_u8 | axis + * --------------|-------------- + * 0 | BMG160_X_AXIS + * 1 | BMG160_Y_AXIS + * 2 | BMG160_Z_AXIS + * + * @param v_any_motion_axis_u8: The value of Any motion axis enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_any_motion_enable_axis(u8 v_channel_u8, + u8 *v_any_motion_axis_u8); +/*! + * @brief This API is used to set the status of + * Any motion interrupt axis(X,Y,Z) enable channel + * @note BMG160_X_AXIS -> bit 0 + * @note BMG160_Y_AXIS -> bit 1 + * @note BMG160_Z_AXIS -> bit 2 + * + * @param v_channel_u8 : The value of Any Enable channel number + * v_channel_u8 | axis + * --------------|-------------- + * 0 | BMG160_X_AXIS + * 1 | BMG160_Y_AXIS + * 2 | BMG160_Z_AXIS + * + * @param v_any_motion_axis_u8: The value of Any motion axis enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_any_motion_enable_axis(u8 v_channel_u8, + u8 v_any_motion_axis_u8); +/***********************************************/ +/**\name FIFO CONFIGURATION */ +/**********************************************/ +/*! + * @brief This API is used to get + * the status of fifo water mark in the register 0x1E bit 7 + * + * + * + * @param v_fifo_wm_enable_u8 : The value of fifo water mark enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_fifo_wm_enable( + u8 *v_fifo_wm_enable_u8); +/*! + * @brief This API is used to set + * the status of fifo water mark in the register 0x1E bit 7 + * + * + * + * @param v_fifo_wm_enable_u8 : The value of fifo water mark enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_fifo_wm_enable( + u8 v_fifo_wm_enable_u8); +/***********************************************/ +/**\name RESET INTERRUPT AND OFFSET CONFIGURATION */ +/**********************************************/ +/*! + * @brief This API is used to set the Interrupt Reset + * in the register 0x21 bit 7 + * + * + * + * @param v_rst_int_u8: the value of reset interrupt + * + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_rst_intr(u8 v_rst_int_u8); +/*! + * @brief This API is used to set the offset Reset + * in the register 0x21 bit 6 + * + * + * + * @param v_offset_rst_u8: the value of reset offset + * + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_offset_rst( + u8 v_offset_rst_u8); +/***********************************************/ +/**\name LATCH CONFIGURATION */ +/**********************************************/ +/*! + * @brief This API is used to get the Latch Status + * in the register 0x21 bit 4 + * + * + * + * @param v_latch_stat_u8 : The value of latch status + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_latch_stat( + u8 *v_latch_stat_u8); +/*! + * @brief This API is used to set the Latch Status + * in the register 0x21 bit 4 + * + * + * + * @param v_latch_stat_u8 : The value of latch status + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_latch_stat( + u8 v_latch_stat_u8); +/*! + * @brief This API is used to get the Latch interrupt + * in the register 0x21 bit from 0 to 3 + * + * + * + * @param v_latch_intr_u8 : The value of latch interrupt + * Latch Interrupt | Value + * ----------------------------|----------------- + * BMG160_NON_LATCH | 0x00 + * BMG160_LATCH_250_MS | 0x01 + * BMG160_LATCH_500_MS | 0x02 + * BMG160_LATCH_1_SEC | 0x03 + * BMG160_LATCH_2_SEC | 0x04 + * BMG160_LATCH_4_SEC | 0x05 + * BMG160_LATCH_8_SEC | 0x06 + * BMG160_LATCH_LATCHED | 0x07 + * BMG160_LATCH_NON_LATCHED | 0x08 + * BMG160_LATCH_250_MICRO_SEC | 0x09 + * BMG160_LATCH_500_MICRO_SEC | 0x0A + * BMG160_LATCH_1_MILLI_SEC | 0x0B + * BMG160_LATCH_12.5_MILLI_SEC | 0x0C + * BMG160_LATCH_25_MILLI_SEC | 0x0D + * BMG160_LATCH_50_MILLI_SEC | 0x0E + * BMG160_LATCH_LATCHED | 0x0F + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_latch_intr(u8 *v_latch_intr_u8); +/*! + * @brief This API is used to set the Latch interrupt + * in the register 0x21 bit from 0 to 3 + * + * + * + * @param v_latch_intr_u8 : The value of latch interrupt + * Latch Interrupt | Value + * ----------------------------|----------------- + * BMG160_NON_LATCH | 0x00 + * BMG160_LATCH_250_MS | 0x01 + * BMG160_LATCH_500_MS | 0x02 + * BMG160_LATCH_1_SEC | 0x03 + * BMG160_LATCH_2_SEC | 0x04 + * BMG160_LATCH_4_SEC | 0x05 + * BMG160_LATCH_8_SEC | 0x06 + * BMG160_LATCH_LATCHED | 0x07 + * BMG160_LATCH_NON_LATCHED | 0x08 + * BMG160_LATCH_250_MICRO_SEC | 0x09 + * BMG160_LATCH_500_MICRO_SEC | 0x0A + * BMG160_LATCH_1_MILLI_SEC | 0x0B + * BMG160_LATCH_12.5_MILLI_SEC | 0x0C + * BMG160_LATCH_25_MILLI_SEC | 0x0D + * BMG160_LATCH_50_MILLI_SEC | 0x0E + * BMG160_LATCH_LATCHED | 0x0F + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_latch_intr(u8 v_latch_intr_u8); +/***********************************************/ +/**\name HIGH RATE CONFIGURATION */ +/**********************************************/ +/*! + * @brief This API is used to get the status of High + * Hysteresis of X,Y,Z axis in the registers 0x22,0x24 and 0x26 + * @note X_AXIS - 0x22 bit 6 and 7 + * @note Y_AXIS - 0x24 bit 6 and 7 + * @note Z_AXIS - 0x26 bit 6 and 7 + * + * @param v_channel_u8: The value of high Hysteresis channel number + * v_channel_u8 | value + * --------------|-------------- + * BMG160_X_AXIS | 0 + * BMG160_Y_AXIS | 1 + * BMG160_Z_AXIS | 2 + * + * @param v_highrate_hyst_u8: The value of high Hysteresis + * + * @note High hysteresis can be calculated by + * @note High_hyst = ((255+256 *v_highrate_hyst_u8) * 4LSB) + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_highrate_hyst(u8 v_channel_u8, + u8 *v_highrate_hyst_u8); +/*! + * @brief This API is used to set the status of High + * Hysteresis of X,Y,Z axis in the registers 0x22,0x24 and 0x26 + * @note X_AXIS - 0x22 bit 6 and 7 + * @note Y_AXIS - 0x24 bit 6 and 7 + * @note Z_AXIS - 0x26 bit 6 and 7 + * + * @param v_channel_u8: The value of high Hysteresis channel number + * v_channel_u8 | value + * --------------|-------------- + * BMG160_X_AXIS | 0 + * BMG160_Y_AXIS | 1 + * BMG160_Z_AXIS | 2 + * + * @param v_highrate_hyst_u8: The value of high Hysteresis + * + * @note High hysteresis can be calculated by + * @note High_hyst = ((255+256 *v_highrate_hyst_u8) * 4LSB) + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_highrate_hyst(u8 v_channel_u8, + u8 v_highrate_hyst_u8); +/*! + * @brief This API is used to get the value of High rate + * Threshold of X,Y,Z axis in the registers 0x22, 0x24 and 0x26 + * @note X_AXIS - 0x22 bit from 1 to 5 + * @note Y_AXIS - 0x24 bit from 1 to 5 + * @note Z_AXIS - 0x26 bit from 1 to 5 + * + * @param v_channel_u8 : The value of high threshold channel number + * v_channel_u8 | value + * --------------|-------------- + * BMG160_X_AXIS | 0 + * BMG160_Y_AXIS | 1 + * BMG160_Z_AXIS | 2 + * + * @param v_highrate_thres_u8: the high threshold value + * + * @note High Threshold can be calculated by + * @note High_thres = ((255+256 *v_highrate_thres_u8) * 4LSB) + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_highrate_thres(u8 v_channel_u8, + u8 *v_highrate_thres_u8); +/*! + * @brief This API is used to set the value of High rate + * Threshold of X,Y,Z axis in the registers 0x22, 0x24 and 0x26 + * @note X_AXIS - 0x22 bit from 1 to 5 + * @note Y_AXIS - 0x24 bit from 1 to 5 + * @note Z_AXIS - 0x26 bit from 1 to 5 + * + * @param v_channel_u8 : The value of high threshold channel number + * v_channel_u8 | value + * --------------|-------------- + * BMG160_X_AXIS | 0 + * BMG160_Y_AXIS | 1 + * BMG160_Z_AXIS | 2 + * + * @param v_highrate_thres_u8: the high threshold value + * + * @note High Threshold can be calculated by + * @note High_thres = ((255+256 *v_highrate_thres_u8) * 4LSB) + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_highrate_thres(u8 v_channel_u8, + u8 v_highrate_thres_u8); +/*! + * @brief This API is used to get the status of High Enable + * Channel X,Y,Z in the registers 0x22, 0x24 and 0x26 + * @note X_AXIS - 0x22 bit 0 + * @note Y_AXIS - 0x24 bit 0 + * @note Z_AXIS - 0x26 bit 0 + * + * @param v_channel_u8 : The value of high enable channel number + * v_channel_u8 | value + * --------------|-------------- + * BMG160_X_AXIS | 0 + * BMG160_Y_AXIS | 1 + * BMG160_Z_AXIS | 2 + * + * @param v_enable_u8: The value of high axis enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_highrate_enable_axis(u8 v_channel_u8, + u8 *v_enable_u8); +/*! + * @brief This API is used to set the status of High Enable + * Channel X,Y,Z in the registers 0x22, 0x24 and 0x26 + * @note X_AXIS - 0x22 bit 0 + * @note Y_AXIS - 0x24 bit 0 + * @note Z_AXIS - 0x26 bit 0 + * + * @param v_channel_u8 : The value of high enable channel number + * v_channel_u8 | value + * --------------|-------------- + * BMG160_X_AXIS | 0 + * BMG160_Y_AXIS | 1 + * BMG160_Z_AXIS | 2 + * + * @param v_enable_u8: The value of high axis enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_highrate_enable_axis(u8 v_channel_u8, + u8 v_enable_u8); +/*! + * @brief This API is used to get the status + * of High duration of X,Y,Z axis in + * the registers 0x23, 0x25 and 0x27 + * @note X_AXIS - 0x23 bit form 0 to 7 + * @note Y_AXIS - 0x25 bit form 0 to 7 + * @note Z_AXIS - 0x27 bit form 0 to 7 + * + * + * + * @param v_channel_u8: The value of High Duration channel number + * v_channel_u8 | value + * --------------|-------------- + * BMG160_X_AXIS | 0 + * BMG160_Y_AXIS | 1 + * BMG160_Z_AXIS | 2 + * + * @param v_highrate_durn_axis_u8: The value of high duration + * + * @note High rate duration can be calculated by using the formula + * @note High_durn = ((1+v_highrate_durn_axis_u8)*2.5ms) + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_highrate_durn_axis(u8 v_channel_u8, + u8 *v_highrate_durn_axis_u8); +/*! + * @brief This API is used to set the value + * of High duration of X,Y,Z axis in + * the registers 0x23, 0x25 and 0x27 + * @note X_AXIS - 0x23 bit form 0 to 7 + * @note Y_AXIS - 0x25 bit form 0 to 7 + * @note Z_AXIS - 0x27 bit form 0 to 7 + * + * + * + * @param v_channel_u8: The value of High Duration channel number + * v_channel_u8 | value + * --------------|-------------- + * BMG160_X_AXIS | 0 + * BMG160_Y_AXIS | 1 + * BMG160_Z_AXIS | 2 + * + * @param v_highrate_durn_axis_u8: The value of high duration + * + * @note High rate duration can be calculated by using the formula + * @note High_durn = ((1+v_highrate_durn_axis_u8)*2.5ms) + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_highrate_durn_axis(u8 v_channel_u8, + u8 v_highrate_durn_axis_u8); +/***********************************************/ +/**\name SLOW OFFSET CONFIGURATION */ +/**********************************************/ +/*! + * @brief This API is used to get Slow Offset Threshold + * status in the register 0x31 bit 6 and 7 + * + * + * + * @param v_offset_thres_u8 : The value of slow offset Threshold + * value | threshold + * ----------|------------- + * 0x00 | 0.1 degree/sec + * 0x01 | 0.2 degree/sec + * 0x02 | 0.5 degree/sec + * 0x03 | 1 degree/sec + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_slow_offset_thres( + u8 *v_offset_thres_u8); +/*! + * @brief This API is used to set Slow Offset Threshold + * status in the register 0x31 bit 6 and 7 + * + * + * + * @param v_offset_thres_u8 : The value of slow offset Threshold + * value | threshold + * ----------|------------- + * 0x00 | 0.1 degree/sec + * 0x01 | 0.2 degree/sec + * 0x02 | 0.5 degree/sec + * 0x03 | 1 degree/sec + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_slow_offset_thres(u8 v_offset_thres_u8); +/*! + * @brief This API is used to get Slow Offset duration + * status in the register 0x31 bit 4,5 and 6 + * + * + * + * @param v_offset_durn_u8 : The value of Slow Offset duration + * value | Duration + * -----------|----------- + * 0x00 | 40ms + * 0x01 | 80ms + * 0x02 | 160ms + * 0x03 | 320ms + * 0x04 | 640ms + * 0x05 | 1280ms + * 0x06 | unused + * 0x07 | unused + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_slow_offset_durn( + u8 *v_offset_durn_u8); +/*! + * @brief This API is used to set Slow Offset duration + * status in the register 0x31 bit 4,5 and 6 + * + * + * + * @param v_offset_durn_u8 : The value of Slow Offset duration + * value | Duration + * -----------|----------- + * 0x00 | 40ms + * 0x01 | 80ms + * 0x02 | 160ms + * 0x03 | 320ms + * 0x04 | 640ms + * 0x05 | 1280ms + * 0x06 | unused + * 0x07 | unused + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_slow_offset_durn( + u8 v_offset_durn_u8); +/*! + * @brief This API is used to get Slow Offset Enable channel + * X,Y,Z in the register 0x31 + * @note X_AXIS -> bit 0 + * @note Y_AXIS -> bit 1 + * @note Z_AXIS -> bit 2 + * + * + * @param v_channel_u8: The value of slow offset channel number + * v_channel_u8 | value + * --------------|-------------- + * BMG160_X_AXIS | 0 + * BMG160_Y_AXIS | 1 + * BMG160_Z_AXIS | 2 + * + * @param v_slow_offset_u8: The slow offset value + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_slow_offset_enable_axis( + u8 v_channel_u8, u8 *v_slow_offset_u8); +/*! + * @brief This API is used to set Slow Offset Enable channel + * X,Y,Z in the register 0x31 + * @note X_AXIS -> bit 0 + * @note Y_AXIS -> bit 1 + * @note Z_AXIS -> bit 2 + * + * + * @param v_channel_u8: The value of slow offset channel number + * v_channel_u8 | value + * --------------|-------------- + * BMG160_X_AXIS | 0 + * BMG160_Y_AXIS | 1 + * BMG160_Z_AXIS | 2 + * + * @param v_slow_offset_u8: The slow offset value + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_slow_offset_enable_axis( + u8 v_channel_u8, u8 v_slow_offset_u8); +/*! + * @brief This API is used to get + * Fast Offset WordLength and Auto Offset WordLength in the register 0x32 + * @note fast_offset_wordlength -> bit 4 and 5 + * @note auto_offset_wordlength -> bit 6 and 7 + * + * + * @param v_channel_u8: The value of WordLengthchannel number + * v_channel_u8 | value + * ----------------------|-------------- + * BMG160_AUTO_OFFSET_WL | 0 + * BMG160_FAST_OFFSET_WL | 1 + * + * @param v_offset_word_length_u8: The value of offset word length + * value | word length + * ----------|-------------- + * 0x00 | 32 samples + * 0x01 | 64 samples + * 0x02 | 128 samples + * 0x03 | 256 samples + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_offset_word_length(u8 v_channel_u8, + u8 *v_offset_word_length_u8); +/*! + * @brief This API is used to set + * Fast Offset WordLength and Auto Offset WordLength in the register 0x32 + * @note fast_offset_wordlength -> bit 4 and 5 + * @note auto_offset_wordlength -> bit 6 and 7 + * + * + * @param v_channel_u8: The value of WordLengthchannel number + * v_channel_u8 | value + * ----------------------|-------------- + * BMG160_AUTO_OFFSET_WL | 0 + * BMG160_FAST_OFFSET_WL | 1 + * + * @param v_offset_word_length_u8: The value of offset word length + * value | word length + * ----------|-------------- + * 0x00 | 32 samples + * 0x01 | 64 samples + * 0x02 | 128 samples + * 0x03 | 256 samples + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_offset_word_length( + u8 v_channel_u8, u8 v_offset_word_length_u8); +/***********************************************/ +/**\name OFFSET CONFIGURATION */ +/**********************************************/ +/*! + * @brief This API is used to enable fast offset + * in the register 0x32 bit 3 it is a write only register + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_enable_fast_offset(void); +/*! + * @brief This API read the Fast offset enable + * v_axis_u8(X,Y and Z) in the register 0x32 + * @note X_AXIS -> bit 0 + * @note Y_AXIS -> bit 1 + * @note Z_AXIS -> bit 2 + * + * + * + * @param v_fast_offset_u8: The value of fast offset enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_fast_offset_enable_axis( + u8 *v_fast_offset_u8); +/*! + * @brief This API set the Fast offset enable + * v_axis_u8(X,Y and Z) in the register 0x32 + * @note X_AXIS -> bit 0 + * @note Y_AXIS -> bit 1 + * @note Z_AXIS -> bit 2 + * + * + * @param v_channel_u8: The value of fast offset channel select + * v_channel_u8 | value + * ----------------|-------------- + * BMG160_X_AXIS | 0 + * BMG160_Y_AXIS | 1 + * BMG160_Z_AXIS | 2 + * + * @param v_fast_offset_u8: The value of fast offset enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_fast_offset_enable_axis( + u8 v_channel_u8, u8 v_fast_offset_u8); +/***********************************************/ +/**\name NVM CONFIGURATION */ +/**********************************************/ +/*! + * @brief This API is used to get the status of nvm program + * remain in the register 0x33 bit from 4 to 7 + * + * + * @param v_nvm_remain_u8: The value of nvm program + * value | Description + * -----------|--------------- + * 1 | Do not trigger + * 0 | Trigger + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_nvm_remain(u8 *v_nvm_remain_u8); +/*! + * @brief This API is used to set the status of nvm program + * remain in the register 0x33 bit from 4 to 7 + * + * + * @param v_nvm_load_u8: The value of nvm program + * value | Description + * -----------|--------------- + * 1 | Do not trigger + * 0 | Trigger + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_nvm_load(u8 v_nvm_load_u8); +/*! + * @brief This API is used to get the status of nvm + * program in the register 0x33 bit 2 + * + * @param v_nvm_rdy_u8: The value of nvm program + * value | Description + * -----------|--------------- + * 1 | NVM write is in progress + * 0 | NVM is ready to accept a new write + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_nvm_rdy(u8 *v_nvm_rdy_u8); +/*! + * @brief This API is used to set the status of nvm + * ready in the register 0x33 bit 1 + * + * @param nvm_prog_trig: The value of nvm program + * value | Description + * -----------|--------------- + * 1 | program seq in progress + * 0 | program seq finished + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_nvm_prog_trig(u8 nvm_prog_trig); +/*! + * @brief This API is used to get + * the status of nvm program mode in the register 0x33 bit 0 + * + * + * @param nvm_prog_mode: The value of nvm program mode + * value | Description + * -----------|--------------- + * 1 | Unlock + * 0 | Lock nvm write + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_nvm_prog_mode(u8 *nvm_prog_mode); +/*! + * @brief This API is used to set + * the status of nvm program mode in the register 0x33 bit 0 + * + * + * @param nvm_prog_mode: The value of nvm program mode + * value | Description + * -----------|--------------- + * 1 | Unlock + * 0 | Lock nvm write + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_nvm_prog_mode(u8 nvm_prog_mode); +/***********************************************/ +/**\name I2C CONFIGURATION */ +/**********************************************/ +/*! + * @brief This API is used to get + * the status of i2c wdt select and enable in the register 0x34 + * @note i2c_wdt_select -> bit 1 + * @note i2c_wdt_enable -> bit 2 + * + * @param v_channel_u8: The value of i2c wdt channel number + * v_channel_u8 | value + * ------------------------|-------------- + * BMG160_I2C_WDT_ENABLE | 1 + * BMG160_I2C_WDT_SELECT | 0 + * + * @param v_i2c_wdt_u8: The value of I2C enable and WDT select + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_i2c_wdt(u8 v_channel_u8, + u8 *v_i2c_wdt_u8); +/*! + * @brief This API is used to set + * the status of i2c wdt select and enable in the register 0x34 + * @note i2c_wdt_select -> bit 1 + * @note i2c_wdt_enable -> bit 2 + * + * @param v_channel_u8: The value of i2c wdt channel number + * v_channel_u8 | value + * ------------------------|-------------- + * BMG160_I2C_WDT_ENABLE | 1 + * BMG160_I2C_WDT_SELECT | 0 + * + * @param v_i2c_wdt_u8: The value of I2C enable and WDT select + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_i2c_wdt(u8 v_channel_u8, + u8 v_i2c_wdt_u8); +/***********************************************/ +/**\name SPI CONFIGURATION */ +/**********************************************/ +/*! + * @brief This API is used to get the status of spi3 + * in the register 0x34 bit 0 + * + * + * + * @param v_spi3_u8 : The value of spi3 enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_spi3(u8 *v_spi3_u8); +/*! + * @brief This API is used to set the status of spi3 + * in the register 0x34 bit 0 + * + * + * + * @param v_spi3_u8 : The value of spi3 enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_spi3(u8 v_spi3_u8); +/***********************************************/ +/**\name FIFO CONFIGURATION */ +/**********************************************/ +/*! + * @brief This API is used to get the status of FIFO tag + * in the register 0x3D bit 7 + * + * + * + * @param v_fifo_tag_u8 : The value of fifo tag enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_fifo_tag(u8 *v_fifo_tag_u8); +/*! + * @brief This API is used to set the status of FIFO tag + * in the register 0x3D bit 7 + * + * + * + * @param v_fifo_tag_u8 : The value of fifo tag enable + * value | Description + * -----------|--------------- + * 1 | BMG160_ENABLE + * 0 | BMG160_DISABLE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_fifo_tag(u8 v_fifo_tag_u8); +/*! + * @brief This API is used to get Water Mark Level + * in the register 0x3D bit from 0 to 6 + * + * + * + * @param v_fifo_wm_level_u8 : The value of fifo water mark level + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_fifo_wm_level( + u8 *v_fifo_wm_level_u8); +/*! + * @brief This API is used to set Water Mark Level + * in the register 0x3D bit from 0 to 6 + * + * + * + * @param v_fifo_wm_level_u8 : The value of fifo water mark level + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_fifo_wm_level( + u8 v_fifo_wm_level_u8); +/***********************************************/ +/**\name OFFSET FUNCTIONS */ +/**********************************************/ +/*! + * @brief This API is used to get the value of offset + * X, Y and Z in the registers 0x36, 0x37, 0x38, 0x39 and 0x3A + * the offset is a 12bit value + * @note X_AXIS -> + * @note bit 0 and 1 is available in the register 0x3A bit 2 and 3 + * @note bit 2 and 3 is available in the register 0x36 bit 6 and 7 + * @note bit 4 to 11 is available in the register 0x37 bit 0 to 7 + * @note Y_AXIS -> + * @note bit 0 is available in the register 0x3A bit 1 + * @note bit 1,2 and 3 is available in the register 0x36 bit 3,4 and 5 + * @note bit 4 to 11 is available in the register 0x38 bit 0 to 7 + * @note Z_AXIS -> + * @note bit 0 is available in the register 0x3A bit 0 + * @note bit 1,2 and 3 is available in the register 0x36 bit 0,1 and 3 + * @note bit 4 to 11 is available in the register 0x39 bit 0 to 7 + * + * @param v_axis_u8 : The value of offset axis selection + * v_axis_u8 | value + * ----------------|-------------- + * BMG160_X_AXIS | 1 + * BMG160_Y_AXIS | 0 + * BMG160_Z_AXIS | 0 + * + * @param v_offset_s16: The value of offset + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_offset(u8 v_axis_u8, + s16 *v_offset_s16); +/*! + * @brief This API is used to set the value of offset + * X, Y and Z in the registers 0x36, 0x37, 0x38, 0x39 and 0x3A + * the offset is a 12bit value + * @note X_AXIS -> + * @note bit 0 and 1 is available in the register 0x3A bit 2 and 3 + * @note bit 2 and 3 is available in the register 0x36 bit 6 and 7 + * @note bit 4 to 11 is available in the register 0x37 bit 0 to 7 + * @note Y_AXIS -> + * @note bit 0 is available in the register 0x3A bit 1 + * @note bit 1,2 and 3 is available in the register 0x36 bit 3,4 and 5 + * @note bit 4 to 11 is available in the register 0x38 bit 0 to 7 + * @note Z_AXIS -> + * @note bit 0 is available in the register 0x3A bit 0 + * @note bit 1,2 and 3 is available in the register 0x36 bit 0,1 and 3 + * @note bit 4 to 11 is available in the register 0x39 bit 0 to 7 + * + * @param v_axis_u8 : The value of offset axis selection + * v_axis_u8 | value + * ----------------|-------------- + * BMG160_X_AXIS | 1 + * BMG160_Y_AXIS | 0 + * BMG160_Z_AXIS | 0 + * + * @param v_offset_s16: The value of offset + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_offset( + u8 v_axis_u8, s16 v_offset_s16); +/*! + * @brief This API is used to get the status of general + * purpose register in the register 0x3A and 0x3B + * + * + * + * + * @param v_param_u8: The value of general purpose register select + * v_param_u8 | value + * ----------------|-------------- + * BMG160_GP0 | 0 + * BMG160_GP1 | 1 + * + * @param v_gp_u8: The value of general purpose register + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_gp(u8 v_param_u8, + u8 *v_gp_u8); +/*! + * @brief This API is used to set the status of general + * purpose register in the register 0x3A and 0x3B + * + * + * + * + * @param v_param_u8: The value of general purpose register select + * v_param_u8 | value + * ----------------|-------------- + * BMG160_GP0 | 0 + * BMG160_GP1 | 1 + * + * @param v_gp_u8: The value of general purpose register + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_gp(u8 v_param_u8, + u8 v_gp_u8); +/***********************************************/ +/**\name FIFO READ AND CONFIGURATION */ +/**********************************************/ +/*! + * @brief Reads FIFO data from location 0x3F + * + * + * + * + * @param v_fifo_data_u8 : The data of fifo + * + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error result of communication routines + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_FIFO_data_reg(u8 *v_fifo_data_u8); +/*! + * @brief this api is used to read the fifo status + * of frame_counter and overrun in the register 0x0E + * @note frame_counter > bit from 0 to 6 + * @note overrun -> bit 7 + * + * + * + * @param v_fifo_stat_u8 : The value of fifo overrun and fifo counter + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_fifo_stat_reg( + u8 *v_fifo_stat_u8); +/*! + * @brief this API is used to get the fifo frame counter + * in the register 0x0E bit 0 to 6 + * + * + * + * @param v_fifo_frame_count_u8: The value of fifo frame counter + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_fifo_frame_count( + u8 *v_fifo_frame_count_u8); +/*! + * @brief this API is used to get the fifo over run + * in the register 0x0E bit 7 + * + * + * + * @param v_fifo_overrun_u8: The value of fifo over run + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_fifo_overrun( + u8 *v_fifo_overrun_u8); +/*! + * @brief This API is used to get the status of fifo mode + * in the register 0x3E bit 6 and 7 + * + * + * + * @param v_fifo_mode_u8 : The value of fifo mode + * mode | value + * ----------------|-------------- + * BYPASS | 0 + * FIFO | 1 + * STREAM | 2 + * RESERVED | 3 + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_fifo_mode(u8 *v_fifo_mode_u8); +/*! + * @brief This API is used to set the status of fifo mode + * in the register 0x3E bit 6 and 7 + * + * + * + * @param v_fifo_mode_u8 : The value of fifo mode + * mode | value + * ----------------|-------------- + * BYPASS | 0 + * FIFO | 1 + * STREAM | 2 + * RESERVED | 3 + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_fifo_mode(u8 v_fifo_mode_u8); +/*! + * @brief This API is used to get the status of fifo + * data select in the register 0x3E bit 0 and 1 + * + * + * @param v_fifo_data_select_u8 : The value of fifo data selection + * data selection | value + * ---------------------------|-------------- + * X,Y and Z (DEFAULT) | 0 + * X only | 1 + * Y only | 2 + * Z only | 3 + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_fifo_data_select( + u8 *v_fifo_data_select_u8); +/*! + * @brief This API is used to set the status of fifo + * data select in the register 0x3E bit 0 and 1 + * + * + * @param v_fifo_data_select_u8 : The value of fifo data selection + * data selection | value + * ---------------------------|-------------- + * X,Y and Z (DEFAULT) | 0 + * X only | 1 + * Y only | 2 + * Z only | 3 + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_fifo_data_select( + u8 v_fifo_data_select_u8); +/***********************************************/ +/**\name POWER MODE CONFIGURATION */ +/**********************************************/ +/*! + * @brief This API is used to get the operating modes of the + * sensor in the registers 0x11 and 0x12 + * + * + * + * @param v_power_mode_u8 :The value of power mode + * value | power mode + * -----------|---------------- + * 0 | BMG160_MODE_NORMAL + * 1 | BMG160_MODE_SUSPEND + * 2 | BMG160_MODE_DEEPSUSPEND + * 3 | BMG160_MODE_FASTPOWERUP + * 4 | BMG160_MODE_ADVANCEDPOWERSAVING + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_power_mode(u8 *v_power_mode_u8); +/*! + * @brief This API is used to set the operating modes of the + * sensor in the registers 0x11 and 0x12 + * + * + * + * @param v_power_mode_u8 :The value of power mode + * value | power mode + * -----------|---------------- + * 0 | BMG160_MODE_NORMAL + * 1 | BMG160_MODE_SUSPEND + * 2 | BMG160_MODE_DEEPSUSPEND + * 3 | BMG160_MODE_FASTPOWERUP + * 4 | BMG160_MODE_ADVANCEDPOWERSAVING + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_power_mode(u8 v_power_mode_u8); +/***********************************************/ +/**\name SELF TEST CONFIGURATION */ +/**********************************************/ +/*! + * @brief This API is used to to do selftest to sensor + * sensor in the register 0x3C + * + * + * + * + * @param v_result_u8: The value of self test + * + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_selftest(u8 *v_result_u8); +/***********************************************/ +/**\name SLEEP AND AUTO SLEEP CONFIGURATION */ +/**********************************************/ +/*! + * @brief This API is used to get the auto sleep duration + * in the register 0x12 bit 0 to 2 + * + * + * + * @param v_durn_u8 : The value of gyro auto sleep duration + * sleep duration | value + * ----------------------------|---------- + * not allowed | 0 + * 4ms | 1 + * 5ms | 2 + * 8ms | 3 + * 10ms | 4 + * 15ms | 5 + * 20ms | 6 + * 40ms | 7 + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_auto_sleep_durn(u8 *v_durn_u8); +/*! + * @brief This API is used to set the auto sleep duration + * in the register 0x12 bit 0 to 2 + * + * + * + * @param v_durn_u8 : The value of gyro auto sleep duration + * sleep duration | value + * ----------------------------|---------- + * not allowed | 0 + * 4ms | 1 + * 5ms | 2 + * 8ms | 3 + * 10ms | 4 + * 15ms | 5 + * 20ms | 6 + * 40ms | 7 + * + * @param v_bw_u8 : The value of selected bandwidth + * v_bw_u8 | value + * ----------------------------|---------- + * C_BMG160_NO_FILTER_U8X | 0 + * C_BMG160_BW_230HZ_U8X | 1 + * C_BMG160_BW_116HZ_u8X | 2 + * C_BMG160_BW_47HZ_u8X | 3 + * C_BMG160_BW_23HZ_u8X | 4 + * C_BMG160_BW_12HZ_u8X | 5 + * C_BMG160_BW_64HZ_u8X | 6 + * C_BMG160_BW_32HZ_u8X | 7 + * + * @note: sleep duration depends on selected power mode and bandwidth + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_auto_sleep_durn(u8 v_durn_u8, + u8 v_bw_u8); +/*! + * @brief This API is used to get the sleep duration + * in the register 0x11 bit 1 to 3 + * + * + * + * @param v_durn_u8 : The value of sleep duration + * sleep duration | value + * ----------------------------|---------- + * 2ms | 0 + * 4ms | 1 + * 5ms | 2 + * 8ms | 3 + * 10ms | 4 + * 15ms | 5 + * 18ms | 6 + * 20ms | 7 + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_get_sleep_durn(u8 *v_durn_u8); +/*! + * @brief This API is used to set the sleep duration + * in the register 0x11 bit 1 to 3 + * + * + * + * @param v_durn_u8 : The value of sleep duration + * sleep duration | value + * ----------------------------|---------- + * 2ms | 0 + * 4ms | 1 + * 5ms | 2 + * 8ms | 3 + * 10ms | 4 + * 15ms | 5 + * 18ms | 6 + * 20ms | 7 + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMG160_RETURN_FUNCTION_TYPE bmg160_set_sleep_durn(u8 v_durn_u8); +#endif diff --git a/bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMG160_driver/bmg160_support.c b/bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMG160_driver/bmg160_support.c new file mode 100644 index 0000000000000000000000000000000000000000..6e34ad18d7c69a18495a98457f96b32f7281edad --- /dev/null +++ b/bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMG160_driver/bmg160_support.c @@ -0,0 +1,435 @@ +/* +**************************************************************************** +* Copyright (C) 2014 - 2015 Bosch Sensortec GmbH +* +* bmg160_support.c +* Date: 2015/04/29 +* Revision: 1.0.5 $ +* +* Usage: Sensor Driver support file for BMG160 sensor +* +**************************************************************************** +* License: +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* Neither the name of the copyright holder nor the names of the +* contributors may be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDER +* OR CONTRIBUTORS BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, +* OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT NOT LIMITED TO, +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* The information provided is believed to be accurate and reliable. +* The copyright holder assumes no responsibility +* for the consequences of use +* of such information nor for any infringement of patents or +* other rights of third parties which may result from its use. +* No license is granted by implication or otherwise under any patent or +* patent rights of the copyright holder. +**************************************************************************/ +/*--------------------------------------------------------------------------*/ +/* Includes*/ +/*--------------------------------------------------------------------------*/ +#include "bmg160.h" + +/*---------------------------------------------------------------------------* +* The following functions are used for reading and writing of +* sensor data using I2C or SPI communication +*---------------------------------------------------------------------------*/ +#ifdef BMG160_API + /* \Brief: The function is used as I2C bus read + * \Return : Status of the I2C read + * \param dev_addr : The device address of the sensor + * \param reg_addr : Address of the first register, will data is going to be read + * \param reg_data : This data read from the sensor, which is hold in an array + * \param cnt : The no of byte of data to be read + */ + s8 BMG160_I2C_bus_read(u8 dev_addr, u8 reg_addr, u8 *reg_data, u8 cnt); + /* \Brief: The function is used as I2C bus write + * \Return : Status of the I2C write + * \param dev_addr : The device address of the sensor + * \param reg_addr : Address of the first register, will data is going to be written + * \param reg_data : It is a value hold in the array, + * will be used for write the value into the register + * \param cnt : The no of byte of data to be write + */ + s8 BMG160_I2C_bus_write(u8 dev_addr, u8 reg_addr, u8 *reg_data, u8 cnt); + /* \Brief: The function is used as SPI bus write + * \Return : Status of the SPI write + * \param dev_addr : The device address of the sensor + * \param reg_addr : Address of the first register, will data is going to be written + * \param reg_data : It is a value hold in the array, + * will be used for write the value into the register + * \param cnt : The no of byte of data to be write + */ + s8 BMG160_SPI_bus_write(u8 dev_addr, u8 reg_addr, u8 *reg_data, u8 cnt); + /* \Brief: The function is used as SPI bus read + * \Return : Status of the SPI read + * \param dev_addr : The device address of the sensor + * \param reg_addr : Address of the first register, will data is going to be read + * \param reg_data : This data read from the sensor, which is hold in an array + * \param cnt : The no of byte of data to be read */ + s8 BMG160_SPI_bus_read(u8 dev_addr, u8 reg_addr, u8 *reg_data, u8 cnt); + /* + * \Brief: SPI/I2C init routine + */ + s8 I2C_routine(void); + s8 SPI_routine(void); +#endif +/********************End of I2C/SPI function declarations***********************/ +/* Brief : The delay routine + * \param : delay in ms +*/ +void BMG160_delay_msek(u32 msek); +/* This function is an example for reading sensor data + * \param: None + * \return: communication result + */ +s32 bmg160_data_readout_template(void); +/*---------------------------------------------------------------------------* +* struct bmg160_t parameters can be accessed by using bmg160 + * bmg160_t having the following parameters + * Bus write function pointer: BMG160_WR_FUNC_PTR + * Bus read function pointer: BMG160_RD_FUNC_PTR + * Burst read function pointer: BMG160_BRD_FUNC_PTR + * Delay function pointer: delay_msec + * I2C address: dev_addr + * Chip id of the sensor: chip_id +*-------------------------------------------------------------------------*/ +struct bmg160_t bmg160; + +/* This function is an example for reading sensor data + * \param: None + * \return: communication result + */ +s32 bmg160_data_readout_template(void) +{ + /* Gyro */ + /* variable used for read the sensor data*/ + s16 v_gyro_datax_s16, v_gyro_datay_s16, v_gyro_dataz_s16 = BMG160_INIT_VALUE; + /* structure used for read the sensor data - xyz*/ + struct bmg160_data_t data_gyro; + /* structure used for read the sensor data - xyz and interrupt status*/ + struct bmg160_data_t gyro_xyzi_data; + /* variable used for read the gyro bandwidth data*/ + u8 v_gyro_value_u8 = BMG160_INIT_VALUE; + /* variable used for set the gyro bandwidth data*/ + u8 v_bw_u8 = BMG160_INIT_VALUE; + /* result of communication results*/ + s32 com_rslt = ERROR; + + /*-------------------------------------------------------------------------* + *********************** START INITIALIZATION *********************** + *-------------------------------------------------------------------------*/ + /* Based on the user need configure I2C or SPI interface. + * It is example code to explain how to use the bmg160 API*/ +#ifdef BMG160_API + I2C_routine(); + /*SPI_routine(); */ +#endif + /*--------------------------------------------------------------------------* + * This function used to assign the value/reference of + * the following parameters + * Gyro I2C address + * Bus Write + * Bus read + * Gyro Chip id + *----------------------------------------------------------------------------*/ + com_rslt = bmg160_init(&bmg160); + /*----------------------------------------------------------------------------*/ + /* For initialization it is required to set the mode of the sensor as "NORMAL" + * data acquisition/read/write is possible in this mode + * by using the below API able to set the power mode as NORMAL + * NORMAL mode set from the register 0x11 and 0x12 + * While sensor in the NORMAL mode idle time of at least 2us(micro seconds) + * is required to write/read operations + * 0x11 -> bit 5,7 -> set value as BMG160_INIT_VALUE + * 0x12 -> bit 6,7 -> set value as BMG160_INIT_VALUE + * Note: + * If the sensor is in the fast power up mode idle time of least + * 450us(micro seconds) required for write/read operations + */ + + /*-------------------------------------------------------------------------*/ + /* Set the gyro power mode as NORMAL*/ + com_rslt += bmg160_set_power_mode(BMG160_MODE_NORMAL); + /*--------------------------------------------------------------------------* + ************************* END INITIALIZATION ****************************** + *--------------------------------------------------------------------------*/ + /*------------------------------------------------------------------------* + ************************* START GET and SET FUNCTIONS DATA *************** + *--------------------------------------------------------------------------*/ + /* This API used to Write the bandwidth of the gyro sensor + input value have to be give 0x10 bit BMG160_INIT_VALUE to 3 + The bandwidth set from the register */ + v_bw_u8 = C_BMG160_BW_230HZ_U8X;/* set gyro bandwidth of 230Hz*/ + com_rslt += bmg160_set_bw(v_bw_u8); + + /* This API used to read back the written value of bandwidth for gyro*/ + com_rslt += bmg160_get_bw(&v_gyro_value_u8); + /*---------------------------------------------------------------------* + ************************* END GET and SET FUNCTIONS ******************** + *----------------------------------------------------------------------*/ + /*---------------------------------------------------------------------* + ************************* START READ SENSOR DATA(X,Y and Z axis) ********* + *-------------------------------------------------------------------------*/ + /******************* Read Gyro data xyz**********************/ + com_rslt += bmg160_get_data_X(&v_gyro_datax_s16);/* Read the gyro X data*/ + + com_rslt += bmg160_get_data_Y(&v_gyro_datay_s16);/* Read the gyro Y data*/ + + com_rslt += bmg160_get_data_Z(&v_gyro_dataz_s16);/* Read the gyro Z data*/ + + /* accessing the bmg160_data_t parameter by using data_gyro*/ + com_rslt += bmg160_get_data_XYZ(&data_gyro);/* Read the gyro XYZ data*/ + + /* accessing the bmg160_data_t parameter by using gyro_xyzi_data*/ + /* Read the gyro XYZ data and interrupt status*/ + com_rslt += bmg160_get_data_XYZI(&gyro_xyzi_data); + /*-------------------------------------------------------------------------- + ************************* END READ SENSOR DATA(X,Y and Z axis) ************* + *----------------------------------------------------------------------------*/ + /*---------------------------------------------------------------------------* + *********************** START DE-INITIALIZATION ***************************** + *--------------------------------------------------------------------------*/ + /* For de-initialization it is required to set the mode of + * the sensor as "DEEPSUSPEND" + * the device reaches the lowest power consumption only + * interface selection is kept alive + * No data acquisition is performed + * The DEEPSUSPEND mode set from the register 0x11 bit 5 + * by using the below API able to set the power mode as DEEPSUSPEND + * For the read/ write operation it is required to provide least 450us + * micro second delay*/ + + com_rslt += bmg160_set_power_mode(BMG160_MODE_DEEPSUSPEND); + + /*--------------------------------------------------------------------------* + *********************** END DE-INITIALIZATION ************************** + *---------------------------------------------------------------------------*/ + return com_rslt; +} + +#ifdef BMG160_API +/*--------------------------------------------------------------------------* +* The following function is used to map the I2C bus read, write, delay and +* device address with global structure bmg160_t +*-------------------------------------------------------------------------*/ +/*-------------------------------------------------------------------------* + * By using bmg160 the following structure parameter can be accessed + * Bus write function pointer: BMG160_WR_FUNC_PTR + * Bus read function pointer: BMG160_RD_FUNC_PTR + * Delay function pointer: delay_msec + * I2C address: dev_addr + *--------------------------------------------------------------------------*/ +s8 I2C_routine(void) +{ + + bmg160.bus_write = BMG160_I2C_bus_write; + bmg160.bus_read = BMG160_I2C_bus_read; + bmg160.delay_msec = BMG160_delay_msek; + bmg160.dev_addr = BMG160_I2C_ADDR1; + + return BMG160_INIT_VALUE; +} + +/*---------------------------------------------------------------------------* + * The following function is used to map the SPI bus read, write and delay + * with global structure bmg160_t + *--------------------------------------------------------------------------*/ +/*--------------------------------------------------------------------------* + * By using bmg160 the following structure parameter can be accessed + * Bus write function pointer: BMG160_WR_FUNC_PTR + * Bus read function pointer: BMG160_RD_FUNC_PTR + * Delay function pointer: delay_msec + *-------------------------------------------------------------------------*/ +s8 SPI_routine(void) +{ + + bmg160.bus_write = BMG160_SPI_bus_write; + bmg160.bus_read = BMG160_SPI_bus_read; + bmg160.delay_msec = BMG160_delay_msek; + + return BMG160_INIT_VALUE; +} + +/************** I2C/SPI buffer length ******/ +#define I2C_BUFFER_LEN 8 +#define SPI_BUFFER_LEN 5 +#define MASK_DATA1 0xFF +#define MASK_DATA2 0x80 +#define MASK_DATA3 0x7F +/*-------------------------------------------------------------------* +* +* This is a sample code for read and write the data by using I2C/SPI +* Use either I2C or SPI based on your need +* The device address defined in the bmg160.h file +* +*-----------------------------------------------------------------------*/ +/* \Brief: The function is used as I2C bus write +* \Return : Status of the I2C write +* \param dev_addr : The device address of the sensor +* \param reg_addr : Address of the first register, will data is going to be written +* \param reg_data : It is a value hold in the array, +* will be used for write the value into the register +* \param cnt : The no of byte of data to be write +*/ +s8 BMG160_I2C_bus_write(u8 dev_addr, u8 reg_addr, u8 *reg_data, u8 cnt) +{ + s32 iError = BMG160_INIT_VALUE; + u8 array[I2C_BUFFER_LEN]; + u8 stringpos = BMG160_INIT_VALUE; + array[BMG160_INIT_VALUE] = reg_addr; + for (stringpos = BMG160_INIT_VALUE; stringpos < cnt; stringpos++) + { + array[stringpos + BMG160_GEN_READ_WRITE_DATA_LENGTH] = *(reg_data + stringpos); + } + /* + * Please take the below function as your reference for + * write the data using I2C communication + * "IERROR = I2C_WRITE_STRING(DEV_ADDR, ARRAY, CNT+1)" + * add your I2C write function here + * iError is an return value of I2C read function + * Please select your valid return value + * In the driver SUCCESS defined as BMG160_INIT_VALUE + * and FAILURE defined as -1 + * Note : + * This is a full duplex operation, + * The first read data is discarded, for that extra write operation + * have to be initiated. For that cnt+1 operation done in the I2C write string function + * For more information please refer data sheet SPI communication: + */ + return (s8)iError; +} + +/* \Brief: The function is used as I2C bus read +* \Return : Status of the I2C read +* \param dev_addr : The device address of the sensor +* \param reg_addr : Address of the first register, will data is going to be read +* \param reg_data : This data read from the sensor, which is hold in an array +* \param cnt : The no of data to be read +*/ +s8 BMG160_I2C_bus_read(u8 dev_addr, u8 reg_addr, u8 *reg_data, u8 cnt) +{ + s32 iError = BMG160_INIT_VALUE; + u8 array[I2C_BUFFER_LEN] = {BMG160_INIT_VALUE}; + u8 stringpos = BMG160_INIT_VALUE; + array[BMG160_INIT_VALUE] = reg_addr; + /* Please take the below function as your reference + * for read the data using I2C communication + * add your I2C rad function here. + * "IERROR = I2C_WRITE_READ_STRING(DEV_ADDR, ARRAY, ARRAY, 1, CNT)" + * iError is an return value of SPI write function + * Please select your valid return value + * In the driver SUCCESS defined as BMG160_INIT_VALUE + * and FAILURE defined as -1 + */ + for (stringpos = BMG160_INIT_VALUE; stringpos < cnt; stringpos++) + { + *(reg_data + stringpos) = array[stringpos]; + } + return (s8)iError; +} + +/* \Brief: The function is used as SPI bus read + * \Return : Status of the SPI read + * \param dev_addr : The device address of the sensor + * \param reg_addr : Address of the first register, will data is going to be read + * \param reg_data : This data read from the sensor, which is hold in an array + * \param cnt : The no of data to be read + */ +s8 BMG160_SPI_bus_read(u8 dev_addr, u8 reg_addr, u8 *reg_data, u8 cnt) +{ + s32 iError = BMG160_INIT_VALUE; + u8 array[SPI_BUFFER_LEN] = {MASK_DATA1}; + u8 stringpos; + /* For the SPI mode only 7 bits of register addresses are used. + The MSB of register address is declared the bit what functionality it is + read/write (read as 1/write as BMG160_INIT_VALUE)*/ + array[BMG160_INIT_VALUE] = reg_addr | MASK_DATA2; /*read routine is initiated register address is mask with 0x80*/ + /* + * Please take the below function as your reference for + * read the data using SPI communication + * " IERROR = SPI_READ_WRITE_STRING(ARRAY, ARRAY, CNT+1)" + * add your SPI read function here + * iError is an return value of SPI read function + * Please select your valid return value + * In the driver SUCCESS defined as BMG160_INIT_VALUE + * and FAILURE defined as -1 + * Note : + * This is a full duplex operation, + * The first read data is discarded, for that extra write operation + * have to be initiated. For that cnt+1 operation done in the SPI read + * and write string function + * For more information please refer data sheet SPI communication: + */ + for (stringpos = BMG160_INIT_VALUE; stringpos < cnt; stringpos++) + { + *(reg_data + stringpos) = array[stringpos + BMG160_GEN_READ_WRITE_DATA_LENGTH]; + } + return (s8)iError; +} + +/* \Brief: The function is used as SPI bus write + * \Return : Status of the SPI write + * \param dev_addr : The device address of the sensor + * \param reg_addr : Address of the first register, will data is going to be written + * \param reg_data : It is a value hold in the array, + * will be used for write the value into the register + * \param cnt : The no of byte of data to be write + */ +s8 BMG160_SPI_bus_write(u8 dev_addr, u8 reg_addr, u8 *reg_data, u8 cnt) +{ + s32 iError = BMG160_INIT_VALUE; + u8 array[SPI_BUFFER_LEN * C_BMG160_TWO_U8X]; + u8 stringpos = BMG160_INIT_VALUE; + for (stringpos = BMG160_INIT_VALUE; stringpos < cnt; stringpos++) + { + /* the operation of (reg_addr++)&0x7F done: because it ensure the + BMG160_INIT_VALUE and 1 of the given value + It is done only for 8bit operation*/ + array[stringpos * C_BMG160_TWO_U8X] = (reg_addr++) & MASK_DATA3; + array[stringpos * C_BMG160_TWO_U8X + BMG160_GEN_READ_WRITE_DATA_LENGTH] = *(reg_data + stringpos); + } + /* Please take the below function as your reference + * for write the data using SPI communication + * add your SPI write function here. + * "IERROR = SPI_WRITE_STRING(ARRAY, CNT*2)" + * iError is an return value of SPI write function + * Please select your valid return value + * In the driver SUCCESS defined as BMG160_INIT_VALUE + * and FAILURE defined as -1 + */ + return (s8)iError; +} + +/* Brief : The delay routine + * \param : delay in ms +*/ +void BMG160_delay_msek(u32 msek) +{ + /*Here you can write your own delay routine*/ +} +#endif diff --git a/bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMM050_driver/README.md b/bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMM050_driver/README.md new file mode 100644 index 0000000000000000000000000000000000000000..1d0c339657ef06b9246f773964c326018fc0e36b --- /dev/null +++ b/bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMM050_driver/README.md @@ -0,0 +1,67 @@ + +CONTENTS OF THIS FILE +======================= + * Introduction + * Version + * Integration details + * Driver files information + * Supported sensor interface + * Copyright + + +INTRODUCTION +=============== + - This package contains the Bosch Sensortec MEMS magnetometer sensor driver (sensor API) + - The sensor driver package includes bmm050.h, bmm050.c and bmm050_support.c files + - BMM050 sensor driver supports the following Bosch MEMS sensors + * BMM050 + * BMM150 + * BMC150 - Combination of bma2x2 + bmm050 APIs + * BMC056 - Combination of bma2x2 + bmm050 APIs + * BMX055 - Combination of bma2x2 + bmg160 + bmm050 APIs + +VERSION +========= + - Version of bmm050 sensor driver is: + * bmm050.c - V2.0.6 + * bmm050.h - V2.0.5 + * bmm050_support.c - V1.0.6 + +INTEGRATION DETAILS +===================== + - Integrate bmm050.h and bmm050.c file in to your project. + - The bmm050_support.c file contains only examples for API use cases, so it is not required to integrate into project. + +DRIVER FILES INFORMATION +=========================== + bmm050.h + ----------- + * This header file has the register address definition, constant definitions, data type definition and supported sensor driver calls declarations. + + bmm050.c + ------------ + * This file contains the implementation for the sensor driver APIs. + + bmm050_support.c + ---------------------- + * This file shall be used as an user guidance, here you can find samples of + * Initialize the sensor with I2C/SPI communication + - Add your code to the SPI and/or I2C bus read and bus write functions. + - Return value can be chosen by yourself + - API just passes that value to your application code + - Add your code to the delay function + - Change I2C address accordingly in bmm050.h + * Power mode configuration of the sensor + * Get and set functions usage + * Reading the sensor read out data + +SUPPORTED SENSOR INTERFACE +==================================== + - This magnetometer sensor driver supports SPI and I2C interfaces + + +COPYRIGHT +=========== + - Copyright (C) 2015 - 2016 Bosch Sensortec GmbH + + diff --git a/bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMM050_driver/bmm050.c b/bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMM050_driver/bmm050.c new file mode 100644 index 0000000000000000000000000000000000000000..a292d90e013b9797c313dae8d3c94945b92c012d --- /dev/null +++ b/bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMM050_driver/bmm050.c @@ -0,0 +1,2745 @@ +/* +**************************************************************************** +* Copyright (C) 2015 - 2016 Bosch Sensortec GmbH +* +* bmm050.c +* Date: 2016/03/17 +* Revision: 2.0.6 $ +* +* Usage: Sensor Driver for BMM050 and BMM150 sensor +* +**************************************************************************** +* License: +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* Neither the name of the copyright holder nor the names of the +* contributors may be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDER +* OR CONTRIBUTORS BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, +* OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT NOT LIMITED TO, +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* The information provided is believed to be accurate and reliable. +* The copyright holder assumes no responsibility +* for the consequences of use +* of such information nor for any infringement of patents or +* other rights of third parties which may result from its use. +* No license is granted by implication or otherwise under any patent or +* patent rights of the copyright holder. +**************************************************************************/ +/****************************************************************************/ + + +#include "bmm050.h" + +static struct bmm050_t *p_bmm050; +/*! + * @brief This function is used for initialize + * bus read and bus write functions + * assign the chip id and device address + * chip id is read in the register 0x40 bit from 0 to 7 + * + * @note While changing the parameter of the bmm050 + * consider the following point: + * @note Changing the reference value of the parameter + * will changes the local copy or local reference + * make sure your changes will not + * affect the reference value of the parameter + * (Better case don't change the reference value of the parameter) + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_init(struct bmm050_t *bmm050) +{ + /* variable used to return the bus communication result*/ + BMM050_RETURN_FUNCTION_TYPE com_rslt = ERROR; + /*Array holding the mag chip id + v_data_u8[0] - chip id + */ + u8 v_data_u8[BMM050_INIT_DATA_SIZE] = + { + BMM050_INIT_VALUE, BMM050_INIT_VALUE + }; + + p_bmm050 = bmm050; + + /* set device from suspend into sleep mode */ + com_rslt = bmm050_set_power_mode(BMM050_ON); + + /* wait two millisecond for bmc to settle */ + p_bmm050->delay_msec(BMM050_DELAY_SETTLING_TIME); + + /*Read CHIP_ID and REv. info */ + com_rslt += p_bmm050->BMM050_BUS_READ_FUNC(p_bmm050->dev_addr, + BMM050_CHIP_ID, v_data_u8, BMM050_GEN_READ_WRITE_DATA_LENGTH); + p_bmm050->company_id = v_data_u8[BMM050_CHIP_ID_DATA]; + + /* Function to initialise trim values */ + com_rslt += bmm050_init_trim_registers(); + /* set the preset mode as regular*/ + com_rslt += bmm050_set_presetmode(BMM050_PRESETMODE_REGULAR); + return com_rslt; +} +/*! + * @brief This API used to get the preset modes + * + * @note The preset mode setting is + * depend on Data Rate, XY and Z repetitions + * + * + * + * @param v_presetmode_u8: The value of selected preset mode + * value | preset_mode + * ----------|----------------- + * 1 | BMM050_PRESETMODE_LOWPOWER + * 2 | BMM050_PRESETMODE_REGULAR + * 3 | BMM050_PRESETMODE_HIGHACCURACY + * 4 | BMM050_PRESETMODE_ENHANCED + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_get_presetmode( + u8 *v_presetmode_u8) +{ + /* variable used to return the bus communication result*/ + BMM050_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 v_data_rate_u8 = BMM050_INIT_VALUE; + u8 rep_xy = BMM050_INIT_VALUE; + u8 rep_z = BMM050_INIT_VALUE; + /* Get the current data rate */ + com_rslt = bmm050_get_data_rate(&v_data_rate_u8); + /* Get the preset number of XY Repetitions */ + com_rslt += bmm050_get_rep_XY(&rep_xy); + /* Get the preset number of Z Repetitions */ + com_rslt += bmm050_get_rep_Z(&rep_z); + if ((v_data_rate_u8 == BMM050_LOWPOWER_DR) && ( + rep_xy == BMM050_LOWPOWER_REPXY) && ( + rep_z == BMM050_LOWPOWER_REPZ)) + { + *v_presetmode_u8 = BMM050_PRESETMODE_LOWPOWER; + } + else + { + if ((v_data_rate_u8 == BMM050_REGULAR_DR) && ( + rep_xy == BMM050_REGULAR_REPXY) && ( + rep_z == BMM050_REGULAR_REPZ)) + { + *v_presetmode_u8 = BMM050_PRESETMODE_REGULAR; + } + else + { + if ((v_data_rate_u8 == BMM050_HIGHACCURACY_DR) && ( + rep_xy == BMM050_HIGHACCURACY_REPXY) && ( + rep_z == BMM050_HIGHACCURACY_REPZ)) + { + *v_presetmode_u8 = + BMM050_PRESETMODE_HIGHACCURACY; + } + else + { + if ((v_data_rate_u8 == BMM050_ENHANCED_DR) && ( + rep_xy == BMM050_ENHANCED_REPXY) && ( + rep_z == BMM050_ENHANCED_REPZ)) + { + *v_presetmode_u8 = + BMM050_PRESETMODE_ENHANCED; + } + else + { + *v_presetmode_u8 = + E_BMM050_UNDEFINED_MODE; + } + } + } + } + return com_rslt; +} +/*! + * @brief This API used to set the preset modes + * + * @note The preset mode setting is + * depend on Data Rate, XY and Z repetitions + * + * + * + * @param v_presetmode_u8: The value of selected preset mode + * value | preset_mode + * ----------|----------------- + * 1 | BMM050_PRESETMODE_LOWPOWER + * 2 | BMM050_PRESETMODE_REGULAR + * 3 | BMM050_PRESETMODE_HIGHACCURACY + * 4 | BMM050_PRESETMODE_ENHANCED + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_set_presetmode(u8 v_presetmode_u8) +{ + /* variable used to return the bus communication result*/ + BMM050_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + switch (v_presetmode_u8) + { + case BMM050_PRESETMODE_LOWPOWER: + /* Set the data rate for Low Power mode */ + com_rslt = bmm050_set_data_rate(BMM050_LOWPOWER_DR); + /* Set the XY-repetitions number for Low Power mode */ + com_rslt += bmm050_set_rep_XY(BMM050_LOWPOWER_REPXY); + /* Set the Z-repetitions number for Low Power mode */ + com_rslt += bmm050_set_rep_Z(BMM050_LOWPOWER_REPZ); + break; + case BMM050_PRESETMODE_REGULAR: + /* Set the data rate for Regular mode */ + com_rslt = bmm050_set_data_rate(BMM050_REGULAR_DR); + /* Set the XY-repetitions number for Regular mode */ + com_rslt += bmm050_set_rep_XY(BMM050_REGULAR_REPXY); + /* Set the Z-repetitions number for Regular mode */ + com_rslt += bmm050_set_rep_Z(BMM050_REGULAR_REPZ); + break; + case BMM050_PRESETMODE_HIGHACCURACY: + /* Set the data rate for High Accuracy mode */ + com_rslt = bmm050_set_data_rate(BMM050_HIGHACCURACY_DR); + /* Set the XY-repetitions number for High Accuracy mode */ + com_rslt += bmm050_set_rep_XY(BMM050_HIGHACCURACY_REPXY); + /* Set the Z-repetitions number for High Accuracy mode */ + com_rslt += bmm050_set_rep_Z(BMM050_HIGHACCURACY_REPZ); + break; + case BMM050_PRESETMODE_ENHANCED: + /* Set the data rate for Enhanced Accuracy mode */ + com_rslt = bmm050_set_data_rate(BMM050_ENHANCED_DR); + /* Set the XY-repetitions number for High Enhanced mode */ + com_rslt += bmm050_set_rep_XY(BMM050_ENHANCED_REPXY); + /* Set the Z-repetitions number for High Enhanced mode */ + com_rslt += bmm050_set_rep_Z(BMM050_ENHANCED_REPZ); + break; + default: + com_rslt = E_BMM050_OUT_OF_RANGE; + break; + } + return com_rslt; +} +/*! + * @brief This API used to set the functional state + * in the register 0x4C and 0x4B + * @note 0x4C bit 1 and 2 + * @note 0x4B bit 0 + * + * + * @param v_functional_state_u8: The value of functional mode + * value | functional state + * -----------|------------------- + * 0x00 | BMM050_NORMAL_MODE + * 0x01 | BMM050_SUSPEND_MODE + * 0x02 | BMM050_FORCED_MODE + * 0x03 | BMM050_SLEEP_MODE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_set_functional_state( + u8 v_functional_state_u8) +{ + /* variable used to return the bus communication result*/ + BMM050_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 v_data_u8 = BMM050_INIT_VALUE; + /* check the p_bmm050 pointer is NULL*/ + if (p_bmm050 == BMM050_NULL) + { + return E_BMM050_NULL_PTR; + } + else + { + /* select the functional state*/ + switch (v_functional_state_u8) + { + /* write the functional state*/ + case BMM050_NORMAL_MODE: + com_rslt = bmm050_get_power_mode(&v_data_u8); + if (v_data_u8 == BMM050_OFF) + { + com_rslt += bmm050_set_power_mode(BMM050_ON); + p_bmm050->delay_msec( + BMM050_DELAY_SUSPEND_SLEEP); + } + com_rslt += p_bmm050->BMM050_BUS_READ_FUNC( + p_bmm050->dev_addr, + BMM050_CONTROL_OPERATION_MODE__REG, + &v_data_u8, BMM050_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMM050_SET_BITSLICE( + v_data_u8, + BMM050_CONTROL_OPERATION_MODE, + BMM050_NORMAL_MODE); + com_rslt += p_bmm050->BMM050_BUS_WRITE_FUNC( + p_bmm050->dev_addr, + BMM050_CONTROL_OPERATION_MODE__REG, + &v_data_u8, BMM050_GEN_READ_WRITE_DATA_LENGTH); + break; + case BMM050_SUSPEND_MODE: + com_rslt = bmm050_set_power_mode(BMM050_OFF); + break; + case BMM050_FORCED_MODE: + com_rslt = bmm050_get_power_mode(&v_data_u8); + if (v_data_u8 == BMM050_OFF) + { + com_rslt += bmm050_set_power_mode(BMM050_ON); + p_bmm050->delay_msec( + BMM050_DELAY_SUSPEND_SLEEP); + } + com_rslt += p_bmm050->BMM050_BUS_READ_FUNC( + p_bmm050->dev_addr, + BMM050_CONTROL_OPERATION_MODE__REG, + &v_data_u8, BMM050_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMM050_SET_BITSLICE( + v_data_u8, + BMM050_CONTROL_OPERATION_MODE, BMM050_ON); + com_rslt += p_bmm050->BMM050_BUS_WRITE_FUNC( + p_bmm050->dev_addr, + BMM050_CONTROL_OPERATION_MODE__REG, + &v_data_u8, BMM050_GEN_READ_WRITE_DATA_LENGTH); + break; + case BMM050_SLEEP_MODE: + com_rslt = bmm050_get_power_mode(&v_data_u8); + if (v_data_u8 == BMM050_OFF) + { + com_rslt += bmm050_set_power_mode(BMM050_ON); + p_bmm050->delay_msec( + BMM050_DELAY_SUSPEND_SLEEP); + } + com_rslt += p_bmm050->BMM050_BUS_READ_FUNC( + p_bmm050->dev_addr, + BMM050_CONTROL_OPERATION_MODE__REG, + &v_data_u8, BMM050_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMM050_SET_BITSLICE( + v_data_u8, + BMM050_CONTROL_OPERATION_MODE, + BMM050_SLEEP_MODE); + com_rslt += p_bmm050->BMM050_BUS_WRITE_FUNC( + p_bmm050->dev_addr, + BMM050_CONTROL_OPERATION_MODE__REG, + &v_data_u8, BMM050_GEN_READ_WRITE_DATA_LENGTH); + break; + default: + com_rslt = E_BMM050_OUT_OF_RANGE; + break; + } + } + return com_rslt; +} +/*! + * @brief This API used to get the functional state + * in the register 0x4C bit 1 and 2 + * + * + * + * + * @param v_functional_state_u8: The value of functional mode + * value | functional state + * -----------|-------------------- + * 0x00 | Normal + * 0x03 | Sleep + * @note If user set the functional state as Force mode(0x01) and read the + * register it returns the value as 0x03 that is sleep mode. + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_get_functional_state( + u8 *v_functional_state_u8) +{ + /* variable used to return the bus communication result*/ + BMM050_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 v_data_u8 = BMM050_INIT_VALUE; + /* check the p_bmm050 pointer is NULL*/ + if (p_bmm050 == BMM050_NULL) + { + return E_BMM050_NULL_PTR; + } + else + { + /* read the functional state*/ + com_rslt = p_bmm050->BMM050_BUS_READ_FUNC( + p_bmm050->dev_addr, + BMM050_CONTROL_OPERATION_MODE__REG, + &v_data_u8, BMM050_GEN_READ_WRITE_DATA_LENGTH); + *v_functional_state_u8 = BMM050_GET_BITSLICE( + v_data_u8, BMM050_CONTROL_OPERATION_MODE); + } + return com_rslt; +} +/*! + * @brief This API reads compensated Magnetometer + * data of X,Y,Z values + * from location 0x42 to 0x49 + * + * + * + * + * @param mag_data : The data of mag compensated XYZ data + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_read_mag_data_XYZ( + struct bmm050_mag_data_s16_t *mag_data) +{ + /* variable used to return the bus communication result*/ + BMM050_RETURN_FUNCTION_TYPE com_rslt = ERROR; + /* Array holding the mag XYZ and R data + v_data_u8[0] - X LSB + v_data_u8[1] - X MSB + v_data_u8[2] - Y LSB + v_data_u8[3] - Y MSB + v_data_u8[4] - Z LSB + v_data_u8[5] - Z MSB + v_data_u8[6] - R LSB + v_data_u8[7] - R MSB + */ + u8 v_data_u8[BMM050_DATA_FRAME_SIZE] = + { + BMM050_INIT_VALUE, BMM050_INIT_VALUE, + BMM050_INIT_VALUE, BMM050_INIT_VALUE, + BMM050_INIT_VALUE, BMM050_INIT_VALUE, + BMM050_INIT_VALUE, BMM050_INIT_VALUE + }; + /* structure used to store the mag raw xyz and r data */ + struct + { + s16 raw_data_x; + s16 raw_data_y; + s16 raw_data_z; + u16 raw_data_r; + } raw_data_xyz_t; + + /* check the p_bmm050 pointer is NULL*/ + if (p_bmm050 == BMM050_NULL) + { + return E_BMM050_NULL_PTR; + } + else + { + /* read the mag xyz and r data*/ + com_rslt = p_bmm050->BMM050_BUS_READ_FUNC(p_bmm050->dev_addr, + BMM050_DATA_X_LSB, v_data_u8, BMM050_ALL_DATA_FRAME_LENGTH); + + if (!com_rslt) + { + /* Reading data for X axis */ + v_data_u8[BMM050_XLSB_DATA] = + BMM050_GET_BITSLICE(v_data_u8[BMM050_XLSB_DATA], + BMM050_DATA_X_LSB_BIT); + raw_data_xyz_t.raw_data_x = (s16)((((s32) + ((s8)v_data_u8[BMM050_XMSB_DATA])) << + BMM050_SHIFT_BIT_POSITION_BY_05_BITS) + | v_data_u8[BMM050_XLSB_DATA]); + + /* Reading data for Y axis */ + v_data_u8[BMM050_YLSB_DATA] = + BMM050_GET_BITSLICE(v_data_u8[BMM050_YLSB_DATA], + BMM050_DATA_Y_LSB_BIT); + raw_data_xyz_t.raw_data_y = (s16)((((s32) + ((s8)v_data_u8[BMM050_YMSB_DATA])) << + BMM050_SHIFT_BIT_POSITION_BY_05_BITS) + | v_data_u8[BMM050_YLSB_DATA]); + + /* Reading data for Z axis */ + v_data_u8[BMM050_ZLSB_DATA] = + BMM050_GET_BITSLICE(v_data_u8[BMM050_ZLSB_DATA], + BMM050_DATA_Z_LSB_BIT); + raw_data_xyz_t.raw_data_z = (s16)((((s32) + ((s8)v_data_u8[BMM050_ZMSB_DATA])) << + BMM050_SHIFT_BIT_POSITION_BY_07_BITS) + | v_data_u8[BMM050_ZLSB_DATA]); + + + /* read the data ready status*/ + mag_data->data_ready = BMM050_GET_BITSLICE( + v_data_u8[BMM050_RLSB_DATA], + BMM050_DATA_RDYSTAT); + + + + /* Reading data for Resistance*/ + v_data_u8[BMM050_RLSB_DATA] = + BMM050_GET_BITSLICE(v_data_u8[BMM050_RLSB_DATA], + BMM050_DATA_R_LSB_BIT); + raw_data_xyz_t.raw_data_r = (u16)((((u32) + v_data_u8[BMM050_RMSB_DATA]) << + BMM050_SHIFT_BIT_POSITION_BY_06_BITS) + | v_data_u8[BMM050_RLSB_DATA]); + + + + /* Compensation for X axis */ + mag_data->datax = bmm050_compensate_X( + raw_data_xyz_t.raw_data_x, + raw_data_xyz_t.raw_data_r); + + /* Compensation for Y axis */ + mag_data->datay = bmm050_compensate_Y( + raw_data_xyz_t.raw_data_y, + raw_data_xyz_t.raw_data_r); + + /* Compensation for Z axis */ + mag_data->dataz = bmm050_compensate_Z( + raw_data_xyz_t.raw_data_z, + raw_data_xyz_t.raw_data_r); + + /* Output raw resistance value */ + mag_data->resistance = raw_data_xyz_t.raw_data_r; + } + } + return com_rslt; +} +/*! + * @brief This API reads remapped compensated Magnetometer + * data of X,Y,Z values + * @note In this function X and Y axis is remapped + * @note X is read from the address 0x44 & 0x45 + * @note Y is read from the address 0x42 & 0x43 + * @note this API is only applicable for BMX055 sensor + * + * + * + * @param mag_data : The data of remapped compensated mag xyz data + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_read_bmx055_remapped_mag_data_XYZ( + struct bmm050_remapped_mag_s16_data_t *mag_data) +{ + /* variable used to return the bus communication result*/ + BMM050_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + /* Array holding the mag XYZ and R data + v_data_u8[0] - X LSB + v_data_u8[1] - X MSB + v_data_u8[2] - Y LSB + v_data_u8[3] - Y MSB + v_data_u8[4] - Z LSB + v_data_u8[5] - Z MSB + v_data_u8[6] - R LSB + v_data_u8[7] - R MSB + */ + u8 v_data_u8[BMM050_DATA_FRAME_SIZE] = + { + BMM050_INIT_VALUE, BMM050_INIT_VALUE, + BMM050_INIT_VALUE, BMM050_INIT_VALUE, + BMM050_INIT_VALUE, BMM050_INIT_VALUE, + BMM050_INIT_VALUE, BMM050_INIT_VALUE + }; + /* structure used to store the mag raw xyz and r data */ + struct + { + s16 raw_data_x; + s16 raw_data_y; + s16 raw_data_z; + u16 raw_data_r; + } raw_data_xyz_t; + + /* check the p_bmm050 pointer is NULL*/ + if (p_bmm050 == BMM050_NULL) + { + return E_BMM050_NULL_PTR; + } + else + { + com_rslt = p_bmm050->BMM050_BUS_READ_FUNC(p_bmm050->dev_addr, + BMM050_REMAPPED_BMX055_DATA_Y_LSB, + v_data_u8, BMM050_ALL_DATA_FRAME_LENGTH); + + if (!com_rslt) + { + /* Reading data for Y axis */ + v_data_u8[BMM050_REMAPPED_YLSB_DATA] = + BMM050_GET_BITSLICE( + v_data_u8[BMM050_REMAPPED_YLSB_DATA], + BMM050_REMAPPED_BMX055_DATA_Y_LSB_BIT); + raw_data_xyz_t.raw_data_y = (s16)((((s32) + ((s8)v_data_u8[BMM050_REMAPPED_YMSB_DATA])) << + BMM050_SHIFT_BIT_POSITION_BY_05_BITS) + | v_data_u8[BMM050_REMAPPED_YLSB_DATA]); + + + /* Reading data for X axis */ + v_data_u8[BMM050_REMAPPED_XLSB_DATA] = + BMM050_GET_BITSLICE( + v_data_u8[BMM050_REMAPPED_XLSB_DATA], + BMM050_REMAPPED_BMX055_DATA_X_LSB_BIT); + raw_data_xyz_t.raw_data_x = (s16)((((s32) + ((s8)v_data_u8[BMM050_REMAPPED_YMSB_DATA])) << + BMM050_SHIFT_BIT_POSITION_BY_05_BITS) + | v_data_u8[BMM050_REMAPPED_XLSB_DATA]); + raw_data_xyz_t.raw_data_x = -raw_data_xyz_t.raw_data_x; + + /* Reading data for Z axis */ + v_data_u8[BMM050_ZLSB_DATA] = + BMM050_GET_BITSLICE(v_data_u8[BMM050_ZLSB_DATA], + BMM050_DATA_Z_LSB_BIT); + raw_data_xyz_t.raw_data_z = (s16)((((s32) + ((s8)v_data_u8[BMM050_ZMSB_DATA])) << + BMM050_SHIFT_BIT_POSITION_BY_07_BITS) + | v_data_u8[BMM050_ZLSB_DATA]); + + + + /* read the data ready status*/ + mag_data->data_ready = BMM050_GET_BITSLICE( + v_data_u8[BMM050_RLSB_DATA], + BMM050_DATA_RDYSTAT); + + /* Reading data for Resistance*/ + v_data_u8[BMM050_RLSB_DATA] = + BMM050_GET_BITSLICE(v_data_u8[BMM050_RLSB_DATA], + BMM050_DATA_R_LSB_BIT); + raw_data_xyz_t.raw_data_r = (u16)((((u32) + v_data_u8[BMM050_RMSB_DATA]) << + BMM050_SHIFT_BIT_POSITION_BY_06_BITS) + | v_data_u8[BMM050_RLSB_DATA]); + + + + /* Compensation for X axis */ + mag_data->datax = bmm050_compensate_X( + raw_data_xyz_t.raw_data_x, + raw_data_xyz_t.raw_data_r); + + /* Compensation for Y axis */ + mag_data->datay = bmm050_compensate_Y( + raw_data_xyz_t.raw_data_y, + raw_data_xyz_t.raw_data_r); + + /* Compensation for Z axis */ + mag_data->dataz = bmm050_compensate_Z( + raw_data_xyz_t.raw_data_z, + raw_data_xyz_t.raw_data_r); + + /* Output raw resistance value */ + mag_data->resistance = raw_data_xyz_t.raw_data_r; + } + } + return com_rslt; +} +/*! + * @brief This API reads compensated magnetometer + * data of X,Y,Z values + * @note The output value of compensated X, Y, Z as s32 + * + * + * @param mag_data : The data of compensated XYZ data + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_read_mag_data_XYZ_s32( + struct bmm050_mag_s32_data_t *mag_data) +{ + /* variable used to return the bus communication result*/ + BMM050_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + /* Array holding the mag XYZ and R data + v_data_u8[0] - X LSB + v_data_u8[1] - X MSB + v_data_u8[2] - Y LSB + v_data_u8[3] - Y MSB + v_data_u8[4] - Z LSB + v_data_u8[5] - Z MSB + v_data_u8[6] - R LSB + v_data_u8[7] - R MSB + */ + u8 v_data_u8[BMM050_DATA_FRAME_SIZE] = + { + BMM050_INIT_VALUE, BMM050_INIT_VALUE, + BMM050_INIT_VALUE, BMM050_INIT_VALUE, + BMM050_INIT_VALUE, BMM050_INIT_VALUE, + BMM050_INIT_VALUE, BMM050_INIT_VALUE + }; + /* structure used to store the mag raw xyz and r data */ + struct + { + s16 raw_data_x; + s16 raw_data_y; + s16 raw_data_z; + u16 raw_data_r; + } raw_data_xyz_t; + + /* check the p_bmm050 pointer is NULL*/ + if (p_bmm050 == BMM050_NULL) + { + return E_BMM050_NULL_PTR; + } + else + { + com_rslt = p_bmm050->BMM050_BUS_READ_FUNC(p_bmm050->dev_addr, + BMM050_DATA_X_LSB, v_data_u8, BMM050_ALL_DATA_FRAME_LENGTH); + + if (!com_rslt) + { + /* Reading data for X axis */ + v_data_u8[BMM050_XLSB_DATA] = + BMM050_GET_BITSLICE(v_data_u8[BMM050_XLSB_DATA], + BMM050_DATA_X_LSB_BIT); + raw_data_xyz_t.raw_data_x = (s16)((((s32) + ((s8)v_data_u8[BMM050_XMSB_DATA])) << + BMM050_SHIFT_BIT_POSITION_BY_05_BITS) + | v_data_u8[BMM050_XLSB_DATA]); + + /* Reading data for Y axis */ + v_data_u8[BMM050_YLSB_DATA] = + BMM050_GET_BITSLICE(v_data_u8[BMM050_YLSB_DATA], + BMM050_DATA_Y_LSB_BIT); + raw_data_xyz_t.raw_data_y = (s16)((((s32) + ((s8)v_data_u8[BMM050_YMSB_DATA])) << + BMM050_SHIFT_BIT_POSITION_BY_05_BITS) + | v_data_u8[BMM050_YLSB_DATA]); + + /* Reading data for Z axis */ + v_data_u8[BMM050_ZLSB_DATA] = + BMM050_GET_BITSLICE(v_data_u8[BMM050_ZLSB_DATA], + BMM050_DATA_Z_LSB_BIT); + raw_data_xyz_t.raw_data_z = (s16)((((s32) + ((s8)v_data_u8[BMM050_ZMSB_DATA])) << + BMM050_SHIFT_BIT_POSITION_BY_07_BITS) + | v_data_u8[BMM050_ZLSB_DATA]); + + + /* read the data ready status*/ + mag_data->data_ready = BMM050_GET_BITSLICE( + v_data_u8[BMM050_RLSB_DATA], + BMM050_DATA_RDYSTAT); + + /* Reading data for Resistance*/ + v_data_u8[BMM050_RLSB_DATA] = + BMM050_GET_BITSLICE(v_data_u8[BMM050_RLSB_DATA], + BMM050_DATA_R_LSB_BIT); + raw_data_xyz_t.raw_data_r = (u16)((((u32) + v_data_u8[BMM050_RMSB_DATA]) << + BMM050_SHIFT_BIT_POSITION_BY_06_BITS) + | v_data_u8[BMM050_RLSB_DATA]); + + + /* Compensation for X axis */ + mag_data->datax = bmm050_compensate_X_s32( + raw_data_xyz_t.raw_data_x, + raw_data_xyz_t.raw_data_r); + + /* Compensation for Y axis */ + mag_data->datay = bmm050_compensate_Y_s32( + raw_data_xyz_t.raw_data_y, + raw_data_xyz_t.raw_data_r); + + /* Compensation for Z axis */ + mag_data->dataz = bmm050_compensate_Z_s32( + raw_data_xyz_t.raw_data_z, + raw_data_xyz_t.raw_data_r); + + /* Output raw resistance value */ + mag_data->resistance = raw_data_xyz_t.raw_data_r; + } + } + return com_rslt; +} +/*! + * @brief This API reads remapped compensated magnetometer + * data of X,Y,Z values + * @note The output value of compensated X, Y, Z as s32 + * @note In this function X and Y axis is remapped + * @note X is read from the address 0x44 & 0x45 + * @note Y is read from the address 0x42 & 0x43 + * @note this API is only applicable for BMX055 sensor + * + * + * @param mag_data : The data of remapped compensated XYZ data + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_read_bmx055_remapped_mag_data_XYZ_s32( + struct bmm050_remapped_mag_s32_data_t *mag_data) +{ + /* variable used to return the bus communication result*/ + BMM050_RETURN_FUNCTION_TYPE com_rslt = ERROR; + /* Array holding the mag XYZ and R data + v_data_u8[0] - X LSB + v_data_u8[1] - X MSB + v_data_u8[2] - Y LSB + v_data_u8[3] - Y MSB + v_data_u8[4] - Z LSB + v_data_u8[5] - Z MSB + v_data_u8[6] - R LSB + v_data_u8[7] - R MSB + */ + u8 v_data_u8[BMM050_DATA_FRAME_SIZE] = + { + BMM050_INIT_VALUE, BMM050_INIT_VALUE, + BMM050_INIT_VALUE, BMM050_INIT_VALUE, + BMM050_INIT_VALUE, BMM050_INIT_VALUE, + BMM050_INIT_VALUE, BMM050_INIT_VALUE + }; + /* structure used to store the mag raw xyz and r data */ + struct + { + s16 raw_data_x; + s16 raw_data_y; + s16 raw_data_z; + u16 raw_data_r; + } raw_data_xyz_t; + /* check the p_bmm050 pointer is NULL*/ + if (p_bmm050 == BMM050_NULL) + { + return E_BMM050_NULL_PTR; + } + else + { + com_rslt = p_bmm050->BMM050_BUS_READ_FUNC(p_bmm050->dev_addr, + BMM050_REMAPPED_BMX055_DATA_Y_LSB, + v_data_u8, BMM050_ALL_DATA_FRAME_LENGTH); + + if (!com_rslt) + { + /* Reading data for Y axis */ + v_data_u8[BMM050_REMAPPED_YLSB_DATA] = + BMM050_GET_BITSLICE( + v_data_u8[BMM050_REMAPPED_YLSB_DATA], + BMM050_REMAPPED_BMX055_DATA_Y_LSB_BIT); + raw_data_xyz_t.raw_data_y = (s16)((((s32) + ((s8)v_data_u8[BMM050_REMAPPED_YMSB_DATA])) << + BMM050_SHIFT_BIT_POSITION_BY_05_BITS) + | v_data_u8[BMM050_REMAPPED_YLSB_DATA]); + + + /* Reading data for X axis */ + v_data_u8[BMM050_REMAPPED_XLSB_DATA] = + BMM050_GET_BITSLICE( + v_data_u8[BMM050_REMAPPED_XLSB_DATA], + BMM050_REMAPPED_BMX055_DATA_X_LSB_BIT); + raw_data_xyz_t.raw_data_x = (s16)((((s32) + ((s8)v_data_u8[BMM050_REMAPPED_XMSB_DATA])) << + BMM050_SHIFT_BIT_POSITION_BY_05_BITS) + | v_data_u8[BMM050_REMAPPED_XLSB_DATA]); + raw_data_xyz_t.raw_data_x = -raw_data_xyz_t.raw_data_x; + + /* Reading data for Z axis */ + v_data_u8[BMM050_ZLSB_DATA] = + BMM050_GET_BITSLICE(v_data_u8[BMM050_ZLSB_DATA], + BMM050_DATA_Z_LSB_BIT); + raw_data_xyz_t.raw_data_z = (s16)((((s32) + ((s8)v_data_u8[BMM050_ZMSB_DATA])) << + BMM050_SHIFT_BIT_POSITION_BY_07_BITS) + | v_data_u8[BMM050_ZLSB_DATA]); + + + /* read the data ready status*/ + mag_data->data_ready = BMM050_GET_BITSLICE( + v_data_u8[BMM050_RLSB_DATA], + BMM050_DATA_RDYSTAT); + + + /* Reading data for Resistance*/ + v_data_u8[BMM050_RLSB_DATA] = + BMM050_GET_BITSLICE(v_data_u8[BMM050_RLSB_DATA], + BMM050_DATA_R_LSB_BIT); + raw_data_xyz_t.raw_data_r = (u16)((((u32) + v_data_u8[BMM050_RMSB_DATA]) << + BMM050_SHIFT_BIT_POSITION_BY_06_BITS) + | v_data_u8[BMM050_RLSB_DATA]); + + + + + /* Compensation for X axis */ + mag_data->datax = bmm050_compensate_X_s32( + raw_data_xyz_t.raw_data_x, + raw_data_xyz_t.raw_data_r); + + /* Compensation for Y axis */ + mag_data->datay = bmm050_compensate_Y_s32( + raw_data_xyz_t.raw_data_y, + raw_data_xyz_t.raw_data_r); + + /* Compensation for Z axis */ + mag_data->dataz = bmm050_compensate_Z_s32( + raw_data_xyz_t.raw_data_z, + raw_data_xyz_t.raw_data_r); + + /* Output raw resistance value */ + mag_data->resistance = raw_data_xyz_t.raw_data_r; + } + } + return com_rslt; +} +#ifdef ENABLE_FLOAT +/*! + * @brief This API reads compensated Magnetometer + * data of X,Y,Z values + * @note The output value of compensated X, Y, Z as float + * + * + * + * @param mag_data : The value of compensated XYZ float data + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_read_mag_data_XYZ_float( + struct bmm050_mag_data_float_t *mag_data) +{ + /* variable used to return the bus communication result*/ + BMM050_RETURN_FUNCTION_TYPE com_rslt = ERROR; + + /* Array holding the mag XYZ and R data + v_data_u8[0] - X LSB + v_data_u8[1] - X MSB + v_data_u8[2] - Y LSB + v_data_u8[3] - Y MSB + v_data_u8[4] - Z LSB + v_data_u8[5] - Z MSB + v_data_u8[6] - R LSB + v_data_u8[7] - R MSB + */ + u8 v_data_u8[BMM050_DATA_FRAME_SIZE] = + { + BMM050_INIT_VALUE, BMM050_INIT_VALUE, + BMM050_INIT_VALUE, BMM050_INIT_VALUE, + BMM050_INIT_VALUE, BMM050_INIT_VALUE, + BMM050_INIT_VALUE, BMM050_INIT_VALUE + }; + /* structure used to store the mag raw xyz and r data */ + struct + { + s16 raw_data_x; + s16 raw_data_y; + s16 raw_data_z; + s16 raw_data_r; + } raw_data_xyz_t; + + /* check the p_bmm050 pointer is NULL*/ + if (p_bmm050 == BMM050_NULL) + { + return E_BMM050_NULL_PTR; + } + else + { + com_rslt = p_bmm050->BMM050_BUS_READ_FUNC(p_bmm050->dev_addr, + BMM050_DATA_X_LSB, v_data_u8, BMM050_ALL_DATA_FRAME_LENGTH); + + if (!com_rslt) + { + /* Reading data for X axis */ + v_data_u8[BMM050_XLSB_DATA] = + BMM050_GET_BITSLICE(v_data_u8[BMM050_XLSB_DATA], + BMM050_DATA_X_LSB_BIT); + raw_data_xyz_t.raw_data_x = (s16)((((s32) + ((s8)v_data_u8[BMM050_XMSB_DATA])) << + BMM050_SHIFT_BIT_POSITION_BY_05_BITS) + | v_data_u8[BMM050_XLSB_DATA]); + + /* Reading data for Y axis */ + v_data_u8[BMM050_YLSB_DATA] = + BMM050_GET_BITSLICE(v_data_u8[BMM050_YLSB_DATA], + BMM050_DATA_Y_LSB_BIT); + raw_data_xyz_t.raw_data_y = (s16)((((s32) + ((s8)v_data_u8[BMM050_YMSB_DATA])) << + BMM050_SHIFT_BIT_POSITION_BY_05_BITS) + | v_data_u8[BMM050_YLSB_DATA]); + + /* Reading data for Z axis */ + v_data_u8[BMM050_ZLSB_DATA] = + BMM050_GET_BITSLICE(v_data_u8[BMM050_ZLSB_DATA], + BMM050_DATA_Z_LSB_BIT); + raw_data_xyz_t.raw_data_z = (s16)((((s32) + ((s8)v_data_u8[BMM050_ZMSB_DATA])) << + BMM050_SHIFT_BIT_POSITION_BY_07_BITS) + | v_data_u8[BMM050_ZLSB_DATA]); + + + + + /* read the data ready status*/ + mag_data->data_ready = BMM050_GET_BITSLICE( + v_data_u8[BMM050_RLSB_DATA], + BMM050_DATA_RDYSTAT); + + /* Reading data for Resistance*/ + v_data_u8[BMM050_RLSB_DATA] = + BMM050_GET_BITSLICE(v_data_u8[BMM050_RLSB_DATA], + BMM050_DATA_R_LSB_BIT); + raw_data_xyz_t.raw_data_r = (u16)((((u32) + v_data_u8[BMM050_RMSB_DATA]) << + BMM050_SHIFT_BIT_POSITION_BY_06_BITS) + | v_data_u8[BMM050_RLSB_DATA]); + + + /* Compensation for X axis */ + mag_data->datax = bmm050_compensate_X_float( + raw_data_xyz_t.raw_data_x, + raw_data_xyz_t.raw_data_r); + + /* Compensation for Y axis */ + mag_data->datay = bmm050_compensate_Y_float( + raw_data_xyz_t.raw_data_y, + raw_data_xyz_t.raw_data_r); + + /* Compensation for Z axis */ + mag_data->dataz = bmm050_compensate_Z_float( + raw_data_xyz_t.raw_data_z, + raw_data_xyz_t.raw_data_r); + + /* Output raw resistance value */ + mag_data->resistance = raw_data_xyz_t.raw_data_r; + } + } + return com_rslt; +} +#endif +#ifdef ENABLE_FLOAT +/*! + * @brief This API reads remapped compensated Magnetometer + * data of X,Y,Z values + * @note The output value of compensated X, Y, Z as float + * + * @note In this function X and Y axis is remapped + * @note X is read from the address 0x44 & 0x45 + * @note Y is read from the address 0x42 & 0x43 + * @note this API is only applicable for BMX055 sensor + * + * @param mag_data : The value of remapped compensated XYZ float data + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_read_bmx055_remapped_mag_data_XYZ_float( + struct bmm050_remapped_mag_data_float_t *mag_data) +{ + /* variable used to return the bus communication result*/ + BMM050_RETURN_FUNCTION_TYPE com_rslt = ERROR; + /* Array holding the mag XYZ and R data + v_data_u8[0] - X LSB + v_data_u8[1] - X MSB + v_data_u8[2] - Y LSB + v_data_u8[3] - Y MSB + v_data_u8[4] - Z LSB + v_data_u8[5] - Z MSB + v_data_u8[6] - R LSB + v_data_u8[7] - R MSB + */ + u8 v_data_u8[BMM050_DATA_FRAME_SIZE] = + { + BMM050_INIT_VALUE, BMM050_INIT_VALUE, + BMM050_INIT_VALUE, BMM050_INIT_VALUE, + BMM050_INIT_VALUE, BMM050_INIT_VALUE, + BMM050_INIT_VALUE, BMM050_INIT_VALUE + }; + /* structure used to store the mag raw xyz and r data */ + struct + { + s16 raw_data_x; + s16 raw_data_y; + s16 raw_data_z; + u16 raw_data_r; + } raw_data_xyz_t; + + /* check the p_bmm050 pointer is NULL*/ + if (p_bmm050 == BMM050_NULL) + { + return E_BMM050_NULL_PTR; + } + else + { + com_rslt = p_bmm050->BMM050_BUS_READ_FUNC(p_bmm050->dev_addr, + BMM050_REMAPPED_BMX055_DATA_Y_LSB, v_data_u8, + BMM050_ALL_DATA_FRAME_LENGTH); + + if (!com_rslt) + { + /* Reading data for Y axis */ + v_data_u8[BMM050_REMAPPED_YLSB_DATA] = + BMM050_GET_BITSLICE( + v_data_u8[BMM050_REMAPPED_YLSB_DATA], + BMM050_REMAPPED_BMX055_DATA_Y_LSB_BIT); + raw_data_xyz_t.raw_data_y = (s16)((((s32) + ((s8)v_data_u8[BMM050_REMAPPED_YMSB_DATA])) << + BMM050_SHIFT_BIT_POSITION_BY_05_BITS) + | v_data_u8[BMM050_REMAPPED_YLSB_DATA]); + + /* Reading data for X axis */ + v_data_u8[BMM050_REMAPPED_XLSB_DATA] = + BMM050_GET_BITSLICE( + v_data_u8[BMM050_REMAPPED_XLSB_DATA], + BMM050_REMAPPED_BMX055_DATA_X_LSB_BIT); + raw_data_xyz_t.raw_data_x = (s16)((((s32) + ((s8)v_data_u8[BMM050_REMAPPED_XMSB_DATA])) << + BMM050_SHIFT_BIT_POSITION_BY_05_BITS) + | v_data_u8[BMM050_REMAPPED_XLSB_DATA]); + raw_data_xyz_t.raw_data_x = -raw_data_xyz_t.raw_data_x; + + /* Reading data for Z axis */ + v_data_u8[BMM050_ZLSB_DATA] = + BMM050_GET_BITSLICE(v_data_u8[BMM050_ZLSB_DATA], + BMM050_DATA_Z_LSB_BIT); + raw_data_xyz_t.raw_data_z = (s16)((((s32) + ((s8)v_data_u8[BMM050_ZMSB_DATA])) << + BMM050_SHIFT_BIT_POSITION_BY_07_BITS) + | v_data_u8[BMM050_ZLSB_DATA]); + + + + /* read the data ready status*/ + mag_data->data_ready = BMM050_GET_BITSLICE( + v_data_u8[BMM050_RLSB_DATA], + BMM050_DATA_RDYSTAT); + + + /* Reading data for Resistance*/ + v_data_u8[BMM050_RLSB_DATA] = + BMM050_GET_BITSLICE(v_data_u8[BMM050_RLSB_DATA], + BMM050_DATA_R_LSB_BIT); + raw_data_xyz_t.raw_data_r = (u16)((((u32) + v_data_u8[BMM050_RMSB_DATA]) << + BMM050_SHIFT_BIT_POSITION_BY_06_BITS) + | v_data_u8[BMM050_RLSB_DATA]); + + + /* Compensation for X axis */ + mag_data->datax = bmm050_compensate_X_float( + raw_data_xyz_t.raw_data_x, + raw_data_xyz_t.raw_data_r); + + /* Compensation for Y axis */ + mag_data->datay = bmm050_compensate_Y_float( + raw_data_xyz_t.raw_data_y, + raw_data_xyz_t.raw_data_r); + + /* Compensation for Z axis */ + mag_data->dataz = bmm050_compensate_Z_float( + raw_data_xyz_t.raw_data_z, + raw_data_xyz_t.raw_data_r); + + /* Output raw resistance value */ + mag_data->resistance = raw_data_xyz_t.raw_data_r; + } + } + return com_rslt; +} +#endif +/*! + * @brief + * This API reads the data from + * the given register + * + * + * @param v_addr_u8 -> Address of the register + * @param v_data_u8 -> The data from the register + * @param v_len_u8 -> no of bytes to read + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMM050_RETURN_FUNCTION_TYPE bmm050_read_register(u8 v_addr_u8, + u8 *v_data_u8, u8 v_len_u8) +{ + /* variable used to return the bus communication result*/ + BMM050_RETURN_FUNCTION_TYPE com_rslt = ERROR; + /* check the p_bmm050 pointer is NULL*/ + if (p_bmm050 == BMM050_NULL) + { + return E_BMM050_NULL_PTR; + } + else + { + com_rslt = p_bmm050->BMM050_BUS_READ_FUNC(p_bmm050->dev_addr, + v_addr_u8, v_data_u8, v_len_u8); + } + return com_rslt; +} +/*! + * @brief + * This API write the data to + * the given register + * + * + * @param v_addr_u8 -> Address of the register + * @param v_data_u8 -> The data from the register + * @param v_len_u8 -> no of bytes to read + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMM050_RETURN_FUNCTION_TYPE bmm050_write_register(u8 v_addr_u8, + u8 *v_data_u8, u8 v_len_u8) +{ + /* variable used to return the bus communication result*/ + BMM050_RETURN_FUNCTION_TYPE com_rslt = ERROR; + /* check the p_bmm050 pointer is NULL*/ + if (p_bmm050 == BMM050_NULL) + { + return E_BMM050_NULL_PTR; + } + else + { + com_rslt = p_bmm050->BMM050_BUS_WRITE_FUNC(p_bmm050->dev_addr, + v_addr_u8, v_data_u8, v_len_u8); + } + return com_rslt; +} +/*! + * @brief This API used to set the self test of the sensor + * in the register 0x4C bit 0 + * + * + * + * @param v_selftest_u8 : The value of selftest + * @note write 0x01 to start self test + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_set_selftest(u8 v_selftest_u8) +{ + /* variable used to return the bus communication result*/ + BMM050_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 v_data_u8 = BMM050_INIT_VALUE; + /* check the p_bmm050 pointer is NULL*/ + if (p_bmm050 == BMM050_NULL) + { + return E_BMM050_NULL_PTR; + } + else + { + com_rslt = p_bmm050->BMM050_BUS_READ_FUNC( + p_bmm050->dev_addr, BMM050_CONTROL_SELFTEST__REG, + &v_data_u8, BMM050_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMM050_SET_BITSLICE( + v_data_u8, BMM050_CONTROL_SELFTEST, v_selftest_u8); + com_rslt += p_bmm050->BMM050_BUS_WRITE_FUNC( + p_bmm050->dev_addr, BMM050_CONTROL_SELFTEST__REG, + &v_data_u8, BMM050_GEN_READ_WRITE_DATA_LENGTH); + } + return com_rslt; +} +/*! + * @brief This API used to read the selftest of the sensor + * + * + * + * + * @param v_selftest_xyz: The self test value of XYZ + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_get_selftest_XYZ( + u8 *v_selftest_xyz) +{ + /* variable used to return the bus communication result*/ + BMM050_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 v_data_u8[BMM050_SELFTEST_DATA_SIZE] = + { + BMM050_INIT_VALUE, BMM050_INIT_VALUE, + BMM050_INIT_VALUE, BMM050_INIT_VALUE, BMM050_INIT_VALUE + }; + u8 v_result_u8 = BMM050_INIT_VALUE; + /* check the p_bmm050 pointer is NULL*/ + if (p_bmm050 == BMM050_NULL) + { + return E_BMM050_NULL_PTR; + } + else + { + /* read self test*/ + com_rslt = p_bmm050->BMM050_BUS_READ_FUNC( + p_bmm050->dev_addr, BMM050_DATA_X_LSB_TESTX__REG, + v_data_u8, BMM050_SELFTEST_DATA_LENGTH); + + if (!com_rslt) + { + v_result_u8 = + BMM050_GET_BITSLICE(v_data_u8[BMM050_ZLSB_DATA], + BMM050_DATA_Z_LSB_TESTZ); + + v_result_u8 = (v_result_u8 + << BMM050_SHIFT_BIT_POSITION_BY_01_BIT); + v_result_u8 = (v_result_u8 | BMM050_GET_BITSLICE( + v_data_u8[BMM050_YLSB_DATA], BMM050_DATA_Y_LSB_TESTY)); + + v_result_u8 = (v_result_u8 + << BMM050_SHIFT_BIT_POSITION_BY_01_BIT); + v_result_u8 = (v_result_u8 | BMM050_GET_BITSLICE( + v_data_u8[BMM050_XLSB_DATA], BMM050_DATA_X_LSB_TESTX)); + + *v_selftest_xyz = v_result_u8; + } + } + return com_rslt; +} +/*! + * @brief This API used to set the spi3 + * in the register 0x4B bit 2 + * + * + * + * @param v_value_u8 : the value of spi3 + * value | Description + * --------|------------ + * 0 | Disable + * 1 | Enable + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_set_spi3(u8 v_value_u8) +{ + /* variable used to return the bus communication result*/ + BMM050_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 v_data_u8 = BMM050_INIT_VALUE; + /* check the p_bmm050 pointer is NULL*/ + if (p_bmm050 == BMM050_NULL) + { + return E_BMM050_NULL_PTR; + } + else + { + /* write spi3 */ + com_rslt = p_bmm050->BMM050_BUS_READ_FUNC(p_bmm050->dev_addr, + BMM050_POWER_CONTROL_SPI3_ENABLE__REG, + &v_data_u8, BMM050_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMM050_SET_BITSLICE(v_data_u8, + BMM050_POWER_CONTROL_SPI3_ENABLE, v_value_u8); + com_rslt += p_bmm050->BMM050_BUS_WRITE_FUNC(p_bmm050->dev_addr, + BMM050_POWER_CONTROL_SPI3_ENABLE__REG, + &v_data_u8, BMM050_GEN_READ_WRITE_DATA_LENGTH); + } + return com_rslt; +} +/*! + * @brief This API used to set the data rate of the sensor + * in the register 0x4C bit 3 to 5 + * + * + * + * @param v_data_rate_u8 : The value of data rate + * value | Description + * -----------|----------------------- + * 0x00 | BMM050_DATA_RATE_10HZ + * 0x01 | BMM050_DATA_RATE_02HZ + * 0x02 | BMM050_DATA_RATE_06HZ + * 0x03 | BMM050_DATA_RATE_08HZ + * 0x04 | BMM050_DATA_RATE_15HZ + * 0x05 | BMM050_DATA_RATE_20HZ + * 0x06 | BMM050_DATA_RATE_25HZ + * 0x07 | BMM050_DATA_RATE_30HZ + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_set_data_rate(u8 v_data_rate_u8) +{ + /* variable used to return the bus communication result*/ + BMM050_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 v_data_u8 = BMM050_INIT_VALUE; + /* check the p_bmm050 pointer is NULL*/ + if (p_bmm050 == BMM050_NULL) + { + return E_BMM050_NULL_PTR; + } + else + { + /* set the data rate */ + com_rslt = p_bmm050->BMM050_BUS_READ_FUNC( + p_bmm050->dev_addr, + BMM050_CONTROL_DATA_RATE__REG, + &v_data_u8, BMM050_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMM050_SET_BITSLICE(v_data_u8, + BMM050_CONTROL_DATA_RATE, v_data_rate_u8); + com_rslt += p_bmm050->BMM050_BUS_WRITE_FUNC( + p_bmm050->dev_addr, + BMM050_CONTROL_DATA_RATE__REG, + &v_data_u8, BMM050_GEN_READ_WRITE_DATA_LENGTH); + } + return com_rslt; +} +/*! + * @brief This API used to get the data rate of the sensor + * in the register 0x4C bit 3 to 5 + * + * + * + * @param v_data_rate_u8 : The value of data rate + * value | Description + * -----------|----------------------- + * 0x00 | BMM050_DATA_RATE_10HZ + * 0x01 | BMM050_DATA_RATE_02HZ + * 0x02 | BMM050_DATA_RATE_06HZ + * 0x03 | BMM050_DATA_RATE_08HZ + * 0x04 | BMM050_DATA_RATE_15HZ + * 0x05 | BMM050_DATA_RATE_20HZ + * 0x06 | BMM050_DATA_RATE_25HZ + * 0x07 | BMM050_DATA_RATE_30HZ + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_get_data_rate(u8 *v_data_rate_u8) +{ + /* variable used to return the bus communication result*/ + BMM050_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 v_data_u8 = BMM050_INIT_VALUE; + /* check the p_bmm050 pointer is NULL*/ + if (p_bmm050 == BMM050_NULL) + { + return E_BMM050_NULL_PTR; + } + else + { + com_rslt = p_bmm050->BMM050_BUS_READ_FUNC( + p_bmm050->dev_addr, + BMM050_CONTROL_DATA_RATE__REG, + &v_data_u8, BMM050_GEN_READ_WRITE_DATA_LENGTH); + *v_data_rate_u8 = BMM050_GET_BITSLICE(v_data_u8, + BMM050_CONTROL_DATA_RATE); + } + return com_rslt; +} +/*! + * @brief This API used to perform the + * advanced self test + * + * + * + * @param v_diff_z_s16 : The output of advance self test + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_perform_advanced_selftest( + s16 *v_diff_z_s16) +{ + /* variable used to return the bus communication result*/ + BMM050_RETURN_FUNCTION_TYPE com_rslt = ERROR; + s16 result_positive = BMM050_INIT_VALUE; + s16 result_negative = BMM050_INIT_VALUE; + struct bmm050_mag_data_s16_t mag_data = {BMM050_INIT_VALUE, + BMM050_INIT_VALUE, BMM050_INIT_VALUE, + BMM050_INIT_VALUE, BMM050_INIT_VALUE + }; + /* check the p_bmm050 pointer is NULL*/ + if (p_bmm050 == BMM050_NULL) + { + return E_BMM050_NULL_PTR; + } + else + { + /* set sleep mode to prepare for forced measurement. + * If sensor is off, this will turn it on + * and respect needed delays. */ + com_rslt = bmm050_set_functional_state(BMM050_SLEEP_MODE); + + /* set normal accuracy mode */ + com_rslt += bmm050_set_rep_Z(BMM050_LOWPOWER_REPZ); + /* 14 repetitions Z in normal accuracy mode */ + + /* disable X, Y channel */ + com_rslt += bmm050_set_control_measurement_x( + BMM050_CHANNEL_DISABLE); + com_rslt += bmm050_set_control_measurement_y( + BMM050_CHANNEL_DISABLE); + + /* enable positive current and force a + * measurement with positive field */ + com_rslt += bmm050_set_advanced_selftest( + BMM050_ADVANCED_SELFTEST_POSITIVE); + com_rslt += bmm050_set_functional_state(BMM050_FORCED_MODE); + /* wait for measurement to complete */ + p_bmm050->delay_msec(BMM050_SELFTEST_DELAY); + + /* read result from positive field measurement */ + com_rslt += bmm050_read_mag_data_XYZ(&mag_data); + result_positive = mag_data.dataz; + + /* enable negative current and force a + * measurement with negative field */ + com_rslt += bmm050_set_advanced_selftest( + BMM050_ADVANCED_SELFTEST_NEGATIVE); + com_rslt += bmm050_set_functional_state(BMM050_FORCED_MODE); + p_bmm050->delay_msec(BMM050_SELFTEST_DELAY); + /* wait for measurement to complete */ + + /* read result from negative field measurement */ + com_rslt += bmm050_read_mag_data_XYZ(&mag_data); + result_negative = mag_data.dataz; + + /* turn off self test current */ + com_rslt += bmm050_set_advanced_selftest( + BMM050_ADVANCED_SELFTEST_OFF); + + /* enable X, Y channel */ + com_rslt += bmm050_set_control_measurement_x( + BMM050_CHANNEL_ENABLE); + com_rslt += bmm050_set_control_measurement_y( + BMM050_CHANNEL_ENABLE); + + /* write out difference in positive and negative field. + * This should be ~ 200 mT = 3200 LSB */ + *v_diff_z_s16 = (result_positive - result_negative); + } + return com_rslt; +} +/*! + * @brief This API used to get the trim values + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_init_trim_registers(void) +{ + /* variable used to return the bus communication result*/ + BMM050_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 v_data_u8[BMM050_TRIM_DATA_SIZE] = + { + BMM050_INIT_VALUE, BMM050_INIT_VALUE + }; + com_rslt = p_bmm050->BMM050_BUS_READ_FUNC(p_bmm050->dev_addr, + BMM050_DIG_X1, (u8 *)&p_bmm050->dig_x1, + BMM050_GEN_READ_WRITE_DATA_LENGTH); + com_rslt += p_bmm050->BMM050_BUS_READ_FUNC(p_bmm050->dev_addr, + BMM050_DIG_Y1, (u8 *)&p_bmm050->dig_y1, + BMM050_GEN_READ_WRITE_DATA_LENGTH); + com_rslt += p_bmm050->BMM050_BUS_READ_FUNC(p_bmm050->dev_addr, + BMM050_DIG_X2, (u8 *)&p_bmm050->dig_x2, + BMM050_GEN_READ_WRITE_DATA_LENGTH); + com_rslt += p_bmm050->BMM050_BUS_READ_FUNC(p_bmm050->dev_addr, + BMM050_DIG_Y2, (u8 *)&p_bmm050->dig_y2, + BMM050_GEN_READ_WRITE_DATA_LENGTH); + com_rslt += p_bmm050->BMM050_BUS_READ_FUNC(p_bmm050->dev_addr, + BMM050_DIG_XY1, (u8 *)&p_bmm050->dig_xy1, + BMM050_GEN_READ_WRITE_DATA_LENGTH); + com_rslt += p_bmm050->BMM050_BUS_READ_FUNC(p_bmm050->dev_addr, + BMM050_DIG_XY2, (u8 *)&p_bmm050->dig_xy2, + BMM050_GEN_READ_WRITE_DATA_LENGTH); + + /* shorts can not be recast into (u8*) + * due to possible mix up between trim data + * arrangement and memory arrangement */ + + com_rslt += p_bmm050->BMM050_BUS_READ_FUNC(p_bmm050->dev_addr, + BMM050_DIG_Z1_LSB, v_data_u8, BMM050_TRIM_DATA_LENGTH); + p_bmm050->dig_z1 = (u16)((((u32)((u8) + v_data_u8[BMM050_TRIM_DIG_Z1_MSB_DATA])) << + BMM050_SHIFT_BIT_POSITION_BY_08_BITS) + | v_data_u8[BMM050_TRIM_DIG_Z1_LSB_DATA]); + + com_rslt += p_bmm050->BMM050_BUS_READ_FUNC(p_bmm050->dev_addr, + BMM050_DIG_Z2_LSB, v_data_u8, BMM050_TRIM_DATA_LENGTH); + p_bmm050->dig_z2 = (s16)((((s32)( + (s8)v_data_u8[BMM050_TRIM_DIG_Z2_MSB_DATA])) << + BMM050_SHIFT_BIT_POSITION_BY_08_BITS) + | v_data_u8[BMM050_TRIM_DIG_Z2_LSB_DATA]); + + com_rslt += p_bmm050->BMM050_BUS_READ_FUNC(p_bmm050->dev_addr, + BMM050_DIG_Z3_LSB, v_data_u8, BMM050_TRIM_DATA_LENGTH); + p_bmm050->dig_z3 = (s16)((((s32)( + (s8)v_data_u8[BMM050_TRIM_DIG_Z3_MSB_DATA])) << + BMM050_SHIFT_BIT_POSITION_BY_08_BITS) + | v_data_u8[BMM050_TRIM_DIG_Z3_LSB_DATA]); + + com_rslt += p_bmm050->BMM050_BUS_READ_FUNC(p_bmm050->dev_addr, + BMM050_DIG_Z4_LSB, v_data_u8, BMM050_TRIM_DATA_LENGTH); + p_bmm050->dig_z4 = (s16)((((s32)( + (s8)v_data_u8[BMM050_TRIM_DIG_Z4_MSB_DATA])) << + BMM050_SHIFT_BIT_POSITION_BY_08_BITS) + | v_data_u8[BMM050_TRIM_DIG_Z4_LSB_DATA]); + + com_rslt += p_bmm050->BMM050_BUS_READ_FUNC(p_bmm050->dev_addr, + BMM050_DIG_XYZ1_LSB, v_data_u8, BMM050_TRIM_DATA_LENGTH); + v_data_u8[BMM050_TRIM_DIG_XYZ1_MSB_DATA] = + BMM050_GET_BITSLICE(v_data_u8[BMM050_TRIM_DIG_XYZ1_MSB_DATA], + BMM050_DIG_XYZ1_MSB); + p_bmm050->dig_xyz1 = (u16)((((u32) + ((u8)v_data_u8[BMM050_TRIM_DIG_XYZ1_MSB_DATA])) << + BMM050_SHIFT_BIT_POSITION_BY_08_BITS) + | v_data_u8[BMM050_TRIM_DIG_XYZ1_LSB_DATA]); + return com_rslt; +} +/*! + * @brief This API used to set the advanced self test + * in the register 0x4C bit 6 and 7 + * + * + * + * @param v_advanced_selftest_u8 : The output value of advanced self test + * value | Status + * -------------|------------------- + * 0 | BMM050_ADVANCED_SELFTEST_OFF + * 2 | BMM050_ADVANCED_SELFTEST_NEGATIVE + * 3 | BMM050_ADVANCED_SELFTEST_POSITIVE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_set_advanced_selftest( + u8 v_advanced_selftest_u8) +{ + /* variable used to return the bus communication result*/ + BMM050_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 v_data_u8 = BMM050_INIT_VALUE; + /* check the p_bmm050 pointer is NULL*/ + if (p_bmm050 == BMM050_NULL) + { + return E_BMM050_NULL_PTR; + } + else + { + switch (v_advanced_selftest_u8) + { + /* perform advanced self test*/ + case BMM050_ADVANCED_SELFTEST_OFF: + com_rslt = p_bmm050->BMM050_BUS_READ_FUNC( + p_bmm050->dev_addr, + BMM050_CONTROL_ADVANCED_SELFTEST__REG, + &v_data_u8, BMM050_GEN_READ_WRITE_DATA_LENGTH); + if (!com_rslt) + { + v_data_u8 = BMM050_SET_BITSLICE( + v_data_u8, + BMM050_CONTROL_ADVANCED_SELFTEST, + BMM050_ADVANCED_SELFTEST_OFF); + + com_rslt += p_bmm050->BMM050_BUS_WRITE_FUNC( + p_bmm050->dev_addr, + BMM050_CONTROL_ADVANCED_SELFTEST__REG, + &v_data_u8, BMM050_GEN_READ_WRITE_DATA_LENGTH); + } + break; + case BMM050_ADVANCED_SELFTEST_POSITIVE: + com_rslt = p_bmm050->BMM050_BUS_READ_FUNC( + p_bmm050->dev_addr, + BMM050_CONTROL_ADVANCED_SELFTEST__REG, + &v_data_u8, BMM050_GEN_READ_WRITE_DATA_LENGTH); + if (!com_rslt) + { + v_data_u8 = BMM050_SET_BITSLICE( + v_data_u8, + BMM050_CONTROL_ADVANCED_SELFTEST, + BMM050_ADVANCED_SELFTEST_POSITIVE); + + com_rslt += p_bmm050->BMM050_BUS_WRITE_FUNC( + p_bmm050->dev_addr, + BMM050_CONTROL_ADVANCED_SELFTEST__REG, + &v_data_u8, BMM050_GEN_READ_WRITE_DATA_LENGTH); + } + break; + case BMM050_ADVANCED_SELFTEST_NEGATIVE: + com_rslt = p_bmm050->BMM050_BUS_READ_FUNC( + p_bmm050->dev_addr, + BMM050_CONTROL_ADVANCED_SELFTEST__REG, + &v_data_u8, BMM050_GEN_READ_WRITE_DATA_LENGTH); + if (!com_rslt) + { + v_data_u8 = BMM050_SET_BITSLICE( + v_data_u8, + BMM050_CONTROL_ADVANCED_SELFTEST, + BMM050_ADVANCED_SELFTEST_NEGATIVE); + com_rslt += p_bmm050->BMM050_BUS_WRITE_FUNC( + p_bmm050->dev_addr, + BMM050_CONTROL_ADVANCED_SELFTEST__REG, + &v_data_u8, BMM050_GEN_READ_WRITE_DATA_LENGTH); + } + break; + default: + break; + } + } + return com_rslt; +} +/*! + * @brief This API used to get the advanced self test + * in the register 0x4C bit 6 and 7 + * + * + * + * @param v_advanced_selftest_u8 : The output value of advanced self test + * value | Status + * -------------|------------------- + * 0 | BMM050_ADVANCED_SELFTEST_OFF + * 2 | BMM050_ADVANCED_SELFTEST_NEGATIVE + * 3 | BMM050_ADVANCED_SELFTEST_POSITIVE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_get_advanced_selftest( + u8 *v_advanced_selftest_u8) +{ + /* variable used to return the bus communication result*/ + BMM050_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 v_data_u8 = BMM050_INIT_VALUE; + /* check the p_bmm050 pointer is NULL*/ + if (p_bmm050 == BMM050_NULL) + { + return E_BMM050_NULL_PTR; + } + else + { + /* read advanced self test */ + com_rslt = p_bmm050->BMM050_BUS_READ_FUNC(p_bmm050->dev_addr, + BMM050_CONTROL_ADVANCED_SELFTEST__REG, + &v_data_u8, BMM050_GEN_READ_WRITE_DATA_LENGTH); + if (!com_rslt) + { + *v_advanced_selftest_u8 = BMM050_GET_BITSLICE(v_data_u8, + BMM050_CONTROL_ADVANCED_SELFTEST); + } + } + return com_rslt; +} +/*! + * @brief This API used to get the power control bit + * in the register 0x4B bit 0 + * + * + * + * @param v_power_mode_u8 : The value of power control bit enable + * value | status + * -----------|------------ + * 0 | Disable the power control bit + * 1 | Enable the power control bit + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_get_power_mode(u8 *v_power_mode_u8) +{ + /* variable used to return the bus communication result*/ + BMM050_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 v_data_u8 = BMM050_INIT_VALUE; + /* check the p_bmm050 pointer is NULL*/ + if (p_bmm050 == BMM050_NULL) + { + return E_BMM050_NULL_PTR; + } + else + { + /* read power control bit */ + com_rslt = p_bmm050->BMM050_BUS_READ_FUNC( + p_bmm050->dev_addr, + BMM050_POWER_CONTROL_POWER_CONTROL_BIT__REG, + &v_data_u8, BMM050_GEN_READ_WRITE_DATA_LENGTH); + if (!com_rslt) + { + *v_power_mode_u8 = BMM050_GET_BITSLICE(v_data_u8, + BMM050_POWER_CONTROL_POWER_CONTROL_BIT); + } + } + return com_rslt; +} +/*! + * @brief This API used to set the power control bit + * in the register 0x4B bit 0 + * + * + * + * @param v_power_mode_u8 : The value of power control bit enable + * value | status + * -----------|------------ + * 0 | Disable the power control bit + * 1 | Enable the power control bit + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_set_power_mode(u8 v_power_mode_u8) +{ + /* variable used to return the bus communication result*/ + BMM050_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 v_data_u8 = BMM050_INIT_VALUE; + /* check the p_bmm050 pointer is NULL*/ + if (p_bmm050 == BMM050_NULL) + { + return E_BMM050_NULL_PTR; + } + else + { + /* write power control bit*/ + com_rslt = p_bmm050->BMM050_BUS_READ_FUNC( + p_bmm050->dev_addr, + BMM050_POWER_CONTROL_POWER_CONTROL_BIT__REG, + &v_data_u8, BMM050_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMM050_SET_BITSLICE(v_data_u8, + BMM050_POWER_CONTROL_POWER_CONTROL_BIT, v_power_mode_u8); + com_rslt += p_bmm050->BMM050_BUS_WRITE_FUNC( + p_bmm050->dev_addr, + BMM050_POWER_CONTROL_POWER_CONTROL_BIT__REG, + &v_data_u8, BMM050_GEN_READ_WRITE_DATA_LENGTH); + } + return com_rslt; +} +/*! + * @brief This API used to get the x and y + * repetition in the register 0x51 bit 0 to 7 + * + * + * + * @param v_rep_xy_u8 : The value of x and y repetitions + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_get_rep_XY( + u8 *v_rep_xy_u8) +{ + /* variable used to return the bus communication result*/ + BMM050_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 v_data_u8 = BMM050_INIT_VALUE; + /* check the p_bmm050 pointer is NULL*/ + if (p_bmm050 == BMM050_NULL) + { + return E_BMM050_NULL_PTR; + } + else + { + /* read XY repetitions*/ + com_rslt = p_bmm050->BMM050_BUS_READ_FUNC( + p_bmm050->dev_addr, + BMM050_REP_XY, + &v_data_u8, BMM050_GEN_READ_WRITE_DATA_LENGTH); + *v_rep_xy_u8 = v_data_u8; + } + return com_rslt; +} +/*! + * @brief This API used to set the x and y + * repetition in the register 0x51 bit 0 to 7 + * + * + * + * @param v_rep_xy_u8 : The value of x and y repetitions + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_set_rep_XY( + u8 v_rep_xy_u8) +{ + /* variable used to return the bus communication result*/ + BMM050_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 v_data_u8 = BMM050_INIT_VALUE; + /* check the p_bmm050 pointer is NULL*/ + if (p_bmm050 == BMM050_NULL) + { + return E_BMM050_NULL_PTR; + } + else + { + /* write XY repetitions*/ + v_data_u8 = v_rep_xy_u8; + com_rslt = p_bmm050->BMM050_BUS_WRITE_FUNC( + p_bmm050->dev_addr, + BMM050_REP_XY, + &v_data_u8, BMM050_GEN_READ_WRITE_DATA_LENGTH); + } + return com_rslt; +} +/*! + * @brief This API used to get the z repetition in the + * register 0x52 bit 0 to 7 + * + * + * + * @param v_rep_z_u8 : The value of z repetitions + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_get_rep_Z( + u8 *v_rep_z_u8) +{ + /* variable used to return the bus communication result*/ + BMM050_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 v_data_u8 = BMM050_INIT_VALUE; + /* check the p_bmm050 pointer is NULL*/ + if (p_bmm050 == BMM050_NULL) + { + return E_BMM050_NULL_PTR; + } + else + { + /* read Z repetitions*/ + com_rslt = p_bmm050->BMM050_BUS_READ_FUNC( + p_bmm050->dev_addr, + BMM050_REP_Z, + &v_data_u8, BMM050_GEN_READ_WRITE_DATA_LENGTH); + *v_rep_z_u8 = v_data_u8; + } + return com_rslt; +} +/*! + * @brief This API used to set the z repetition in the + * register 0x52 bit 0 to 7 + * + * + * + * @param v_rep_z_u8 : The value of z repetitions + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_set_rep_Z( + u8 v_rep_z_u8) +{ + /* variable used to return the bus communication result*/ + BMM050_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 v_data_u8 = BMM050_INIT_VALUE; + /* check the p_bmm050 pointer is NULL*/ + if (p_bmm050 == BMM050_NULL) + { + return E_BMM050_NULL_PTR; + } + else + { + /* write Z repetitions*/ + v_data_u8 = v_rep_z_u8; + com_rslt = p_bmm050->BMM050_BUS_WRITE_FUNC(p_bmm050->dev_addr, + BMM050_REP_Z, &v_data_u8, BMM050_GEN_READ_WRITE_DATA_LENGTH); + } + return com_rslt; +} +/*! + * @brief This API used to get the compensated X data + * the out put of X as s16 + * + * + * + * @param mag_data_x : The value of raw X data + * @param data_r : The value of R data + * + * @return results of compensated X data value output as s16 + * +*/ +s16 bmm050_compensate_X(s16 mag_data_x, u16 data_r) +{ + s16 inter_retval = BMM050_INIT_VALUE; + /* no overflow */ + if (mag_data_x != BMM050_FLIP_OVERFLOW_ADCVAL) + { + if ((data_r != BMM050_INIT_VALUE) + && (p_bmm050->dig_xyz1 != BMM050_INIT_VALUE)) + { + inter_retval = ((s16)(((u16) + ((((s32)p_bmm050->dig_xyz1) + << BMM050_SHIFT_BIT_POSITION_BY_14_BITS) / + (data_r != BMM050_INIT_VALUE ? + data_r : p_bmm050->dig_xyz1))) - + ((u16)0x4000))); + } + else + { + inter_retval = BMM050_OVERFLOW_OUTPUT; + return inter_retval; + } + inter_retval = ((s16)((((s32)mag_data_x) * + ((((((((s32)p_bmm050->dig_xy2) * + ((((s32)inter_retval) * + ((s32)inter_retval)) >> + BMM050_SHIFT_BIT_POSITION_BY_07_BITS)) + + (((s32)inter_retval) * + ((s32)(((s16)p_bmm050->dig_xy1) + << BMM050_SHIFT_BIT_POSITION_BY_07_BITS)))) + >> BMM050_SHIFT_BIT_POSITION_BY_09_BITS) + + ((s32)0x100000)) * + ((s32)(((s16)p_bmm050->dig_x2) + + ((s16)0xA0)))) >> + BMM050_SHIFT_BIT_POSITION_BY_12_BITS)) + >> BMM050_SHIFT_BIT_POSITION_BY_13_BITS)) + + (((s16)p_bmm050->dig_x1) + << BMM050_SHIFT_BIT_POSITION_BY_03_BITS); + } + else + { + /* overflow */ + inter_retval = BMM050_OVERFLOW_OUTPUT; + } + return inter_retval; +} +/*! + * @brief This API used to get the compensated X data + * the out put of X as s32 + * + * + * + * @param mag_data_x : The value of raw X data + * @param data_r : The value of R data + * + * @return results of compensated X data value output as s32 + * +*/ +s32 bmm050_compensate_X_s32(s16 mag_data_x, u16 data_r) +{ + s32 retval = BMM050_INIT_VALUE; + + retval = bmm050_compensate_X(mag_data_x, data_r); + if (retval == (s32)BMM050_OVERFLOW_OUTPUT) + retval = BMM050_OVERFLOW_OUTPUT_S32; + return retval; +} +#ifdef ENABLE_FLOAT +/*! + * @brief This API used to get the compensated X data + * the out put of X as float + * + * + * + * @param mag_data_x : The value of raw X data + * @param data_r : The value of R data + * + * @return results of compensated X data value output as float + * +*/ +float bmm050_compensate_X_float(s16 mag_data_x, u16 data_r) +{ + float inter_retval = BMM050_INIT_VALUE; + + if (mag_data_x != BMM050_FLIP_OVERFLOW_ADCVAL /* no overflow */ + ) + { + if ((data_r != BMM050_INIT_VALUE) + && (p_bmm050->dig_xyz1 != BMM050_INIT_VALUE)) + { + inter_retval = ((((float)p_bmm050->dig_xyz1) + * 16384.0 / data_r) - 16384.0); + } + else + { + inter_retval = BMM050_OVERFLOW_OUTPUT_FLOAT; + return inter_retval; + } + inter_retval = (((mag_data_x * ((((((float)p_bmm050->dig_xy2) * + (inter_retval * inter_retval / + 268435456.0) + + inter_retval * ((float)p_bmm050->dig_xy1) + / 16384.0)) + 256.0) * + (((float)p_bmm050->dig_x2) + 160.0))) + / 8192.0) + + (((float)p_bmm050->dig_x1) * + 8.0)) / 16.0; + } + else + { + inter_retval = BMM050_OVERFLOW_OUTPUT_FLOAT; + } + return inter_retval; +} +#endif +/*! + * @brief This API used to get the compensated Y data + * the out put of Y as s16 + * + * + * + * @param mag_data_y : The value of raw Y data + * @param data_r : The value of R data + * + * @return results of compensated Y data value output as s16 + * +*/ +s16 bmm050_compensate_Y(s16 mag_data_y, u16 data_r) +{ + s16 inter_retval = BMM050_INIT_VALUE; + /* no overflow */ + if (mag_data_y != BMM050_FLIP_OVERFLOW_ADCVAL) + { + if ((data_r != BMM050_INIT_VALUE) + && (p_bmm050->dig_xyz1 != BMM050_INIT_VALUE)) + { + inter_retval = ((s16)(((u16)((( + (s32)p_bmm050->dig_xyz1) + << BMM050_SHIFT_BIT_POSITION_BY_14_BITS) / + (data_r != BMM050_INIT_VALUE ? + data_r : p_bmm050->dig_xyz1))) - + ((u16)0x4000))); + } + else + { + inter_retval = BMM050_OVERFLOW_OUTPUT; + return inter_retval; + } + inter_retval = ((s16)((((s32)mag_data_y) * ((((((((s32) + p_bmm050->dig_xy2) * ((((s32) inter_retval) * + ((s32)inter_retval)) >> + BMM050_SHIFT_BIT_POSITION_BY_07_BITS)) + + (((s32)inter_retval) * + ((s32)(((s16)p_bmm050->dig_xy1) << + BMM050_SHIFT_BIT_POSITION_BY_07_BITS)))) + >> BMM050_SHIFT_BIT_POSITION_BY_09_BITS) + + ((s32)0x100000)) * + ((s32)(((s16)p_bmm050->dig_y2) + + ((s16)0xA0)))) + >> BMM050_SHIFT_BIT_POSITION_BY_12_BITS)) + >> BMM050_SHIFT_BIT_POSITION_BY_13_BITS)) + + (((s16)p_bmm050->dig_y1) + << BMM050_SHIFT_BIT_POSITION_BY_03_BITS); + } + else + { + /* overflow */ + inter_retval = BMM050_OVERFLOW_OUTPUT; + } + return inter_retval; +} +/*! + * @brief This API used to get the compensated Y data + * the out put of Y as s32 + * + * + * + * @param mag_data_y : The value of raw Y data + * @param data_r : The value of R data + * + * @return results of compensated Y data value output as s32 + * +*/ +s32 bmm050_compensate_Y_s32(s16 mag_data_y, u16 data_r) +{ + s32 retval = BMM050_INIT_VALUE; + + retval = bmm050_compensate_Y(mag_data_y, data_r); + if (retval == BMM050_OVERFLOW_OUTPUT) + retval = BMM050_OVERFLOW_OUTPUT_S32; + return retval; +} +#ifdef ENABLE_FLOAT +/*! + * @brief This API used to get the compensated Y data + * the out put of Y as float + * + * + * + * @param mag_data_y : The value of raw Y data + * @param data_r : The value of R data + * + * @return results of compensated Y data value output as float + * +*/ +float bmm050_compensate_Y_float(s16 mag_data_y, u16 data_r) +{ + float inter_retval = BMM050_INIT_VALUE; + + if (mag_data_y != BMM050_FLIP_OVERFLOW_ADCVAL /* no overflow */ + ) + { + if ((data_r != BMM050_INIT_VALUE) + && (p_bmm050->dig_xyz1 != BMM050_INIT_VALUE)) + { + inter_retval = ((((float)p_bmm050->dig_xyz1) + * 16384.0 + / data_r) - 16384.0); + } + else + { + inter_retval = BMM050_OVERFLOW_OUTPUT_FLOAT; + return inter_retval; + } + inter_retval = (((mag_data_y * ((((((float)p_bmm050->dig_xy2) * + (inter_retval * inter_retval + / 268435456.0) + + inter_retval * ((float)p_bmm050->dig_xy1) + / 16384.0)) + + 256.0) * + (((float)p_bmm050->dig_y2) + 160.0))) + / 8192.0) + + (((float)p_bmm050->dig_y1) * 8.0)) + / 16.0; + } + else + { + /* overflow, set output to 0.0f */ + inter_retval = BMM050_OVERFLOW_OUTPUT_FLOAT; + } + return inter_retval; +} +#endif +/*! + * @brief This API used to get the compensated Z data + * the out put of Z as s16 + * + * + * + * @param mag_data_z : The value of raw Z data + * @param data_r : The value of R data + * + * @return results of compensated Z data value output as s16 + * +*/ +s16 bmm050_compensate_Z(s16 mag_data_z, u16 data_r) +{ + s32 retval = BMM050_INIT_VALUE; + + if ((mag_data_z != BMM050_HALL_OVERFLOW_ADCVAL) /* no overflow */ + ) + { + if ((p_bmm050->dig_z2 != BMM050_INIT_VALUE) + && (p_bmm050->dig_z1 != BMM050_INIT_VALUE) + && (data_r != BMM050_INIT_VALUE) + && (p_bmm050->dig_xyz1 != BMM050_INIT_VALUE)) + { + retval = (((((s32)(mag_data_z - p_bmm050->dig_z4)) + << BMM050_SHIFT_BIT_POSITION_BY_15_BITS) - + ((((s32)p_bmm050->dig_z3) * ((s32)(((s16)data_r) - + ((s16) p_bmm050->dig_xyz1)))) + >> BMM050_SHIFT_BIT_POSITION_BY_02_BITS)) / + (p_bmm050->dig_z2 + ((s16)(((((s32) + p_bmm050->dig_z1) * ((((s16)data_r) + << BMM050_SHIFT_BIT_POSITION_BY_01_BIT))) + + (1 << BMM050_SHIFT_BIT_POSITION_BY_15_BITS)) + >> BMM050_SHIFT_BIT_POSITION_BY_16_BITS)))); + } + else + { + retval = BMM050_OVERFLOW_OUTPUT; + return retval; + } + /* saturate result to +/- 2 microTesla */ + if (retval > BMM050_POSITIVE_SATURATION_Z) + { + retval = BMM050_POSITIVE_SATURATION_Z; + } + else + { + if (retval < BMM050_NEGATIVE_SATURATION_Z) + retval = BMM050_NEGATIVE_SATURATION_Z; + } + } + else + { + /* overflow */ + retval = BMM050_OVERFLOW_OUTPUT; + } + return (s16)retval; +} +/*! + * @brief This API used to get the compensated Z data + * the out put of Z as s32 + * + * + * + * @param mag_data_z : The value of raw Z data + * @param data_r : The value of R data + * + * @return results of compensated Z data value output as s32 + * +*/ +s32 bmm050_compensate_Z_s32(s16 mag_data_z, u16 data_r) +{ + s32 retval = BMM050_INIT_VALUE; + + if (mag_data_z != BMM050_HALL_OVERFLOW_ADCVAL) + { + if ((p_bmm050->dig_z2 != BMM050_INIT_VALUE) + && (p_bmm050->dig_z1 != BMM050_INIT_VALUE) + && (data_r != BMM050_INIT_VALUE) + && (p_bmm050->dig_xyz1 != BMM050_INIT_VALUE)) + { + retval = (((((s32)(mag_data_z + - p_bmm050->dig_z4)) + << BMM050_SHIFT_BIT_POSITION_BY_15_BITS) - + ((((s32)p_bmm050->dig_z3) * + ((s32)(((s16)data_r) - + ((s16)p_bmm050->dig_xyz1)))) + >> BMM050_SHIFT_BIT_POSITION_BY_02_BITS)) / + (p_bmm050->dig_z2 + + ((s16)(((((s32)p_bmm050->dig_z1) * + ((((s16)data_r) + << BMM050_SHIFT_BIT_POSITION_BY_01_BIT))) + + (1 << BMM050_SHIFT_BIT_POSITION_BY_15_BITS)) + >> BMM050_SHIFT_BIT_POSITION_BY_16_BITS)))); + } + else + { + retval = BMM050_OVERFLOW_OUTPUT_S32; + return retval; + } + } + else + { + retval = BMM050_OVERFLOW_OUTPUT_S32; + } + return retval; +} +#ifdef ENABLE_FLOAT +/*! + * @brief This API used to get the compensated Z data + * the out put of Z as float + * + * + * + * @param mag_data_z : The value of raw Z data + * @param data_r : The value of R data + * + * @return results of compensated Z data value output as float + * +*/ +float bmm050_compensate_Z_float(s16 mag_data_z, u16 data_r) +{ + float inter_retval = BMM050_INIT_VALUE; + /* no overflow */ + if (mag_data_z != BMM050_HALL_OVERFLOW_ADCVAL) + { + if ((p_bmm050->dig_z2 != BMM050_INIT_VALUE) + && (p_bmm050->dig_z1 != BMM050_INIT_VALUE) + && (p_bmm050->dig_xyz1 != BMM050_INIT_VALUE) + && (data_r != BMM050_INIT_VALUE)) + { + inter_retval = ((((((float)mag_data_z) - + ((float)p_bmm050->dig_z4)) * 131072.0) - + (((float)p_bmm050->dig_z3) * (((float)data_r) + - ((float)p_bmm050->dig_xyz1)))) + / ((((float)p_bmm050->dig_z2) + + ((float)p_bmm050->dig_z1) * ((float)data_r) / + 32768.0) * 4.0)) / 16.0; + } + } + else + { + /* overflow, set output to 0.0f */ + inter_retval = BMM050_OVERFLOW_OUTPUT_FLOAT; + } + return inter_retval; +} +#endif +/*! + * @brief This API used to set the control measurement + * X data in the register 0x4E bit 3 + * + * + * @param v_enable_disable_u8: The value of control measurement-x + * value | Status + * --------|---------- + * 1 | ENABLE + * 0 | DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_set_control_measurement_x( + u8 v_enable_disable_u8) +{ + /* variable used to return the bus communication result*/ + BMM050_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 v_data_u8 = BMM050_INIT_VALUE; + /* check the p_bmm050 pointer is NULL*/ + if (p_bmm050 == BMM050_NULL) + { + return E_BMM050_NULL_PTR; + } + else + { + /* read control measurement */ + com_rslt = p_bmm050->BMM050_BUS_READ_FUNC( + p_bmm050->dev_addr, + BMM050_SENS_CONTROL_CHANNELX__REG, + &v_data_u8, BMM050_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMM050_SET_BITSLICE(v_data_u8, + BMM050_SENS_CONTROL_CHANNELX, + v_enable_disable_u8); + com_rslt += p_bmm050->BMM050_BUS_WRITE_FUNC( + p_bmm050->dev_addr, + BMM050_SENS_CONTROL_CHANNELX__REG, + &v_data_u8, BMM050_GEN_READ_WRITE_DATA_LENGTH); + } + return com_rslt; +} +/*! + * @brief This API used to set the control measurement + * Y data in the register 0x4E bit 4 + * + * + * @param v_enable_disable_u8: The value of control measurement-y + * value | Status + * --------|---------- + * 1 | ENABLE + * 0 | DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_set_control_measurement_y( + u8 v_enable_disable_u8) +{ + /* variable used to return the bus communication result*/ + BMM050_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 v_data_u8 = BMM050_INIT_VALUE; + /* check the p_bmm050 pointer is NULL*/ + if (p_bmm050 == BMM050_NULL) + { + return E_BMM050_NULL_PTR; + } + else + { + /* read control measurement */ + com_rslt = p_bmm050->BMM050_BUS_READ_FUNC( + p_bmm050->dev_addr, + BMM050_SENS_CONTROL_CHANNELY__REG, + &v_data_u8, BMM050_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMM050_SET_BITSLICE( + v_data_u8, + BMM050_SENS_CONTROL_CHANNELY, + v_enable_disable_u8); + com_rslt += p_bmm050->BMM050_BUS_WRITE_FUNC( + p_bmm050->dev_addr, + BMM050_SENS_CONTROL_CHANNELY__REG, + &v_data_u8, BMM050_GEN_READ_WRITE_DATA_LENGTH); + } + return com_rslt; +} +/*! + * @brief This API used reset the register values to default + * in the register 0x4B + * + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_soft_rst(void) +{ + /* variable used to return the bus communication result*/ + BMM050_RETURN_FUNCTION_TYPE com_rslt = ERROR; + u8 v_data_u8 = BMM050_INIT_VALUE; + /* check the p_bmm050 pointer is NULL*/ + if (p_bmm050 == BMM050_NULL) + { + return E_BMM050_NULL_PTR; + } + else + { + v_data_u8 = BMM050_ON; + /* write soft rest */ + com_rslt = p_bmm050->BMM050_BUS_READ_FUNC( + p_bmm050->dev_addr, + BMM050_POWER_CONTROL_SOFT_RST_7__REG, + &v_data_u8, BMM050_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMM050_SET_BITSLICE(v_data_u8, + BMM050_POWER_CONTROL_SOFT_RST_7, + BMM050_SOFT_RESET7_ON); + com_rslt += p_bmm050->BMM050_BUS_WRITE_FUNC( + p_bmm050->dev_addr, + BMM050_POWER_CONTROL_SOFT_RST_7__REG, + &v_data_u8, BMM050_GEN_READ_WRITE_DATA_LENGTH); + + com_rslt += p_bmm050->BMM050_BUS_READ_FUNC( + p_bmm050->dev_addr, + BMM050_POWER_CONTROL_SOFT_RST_1__REG, + &v_data_u8, BMM050_GEN_READ_WRITE_DATA_LENGTH); + v_data_u8 = BMM050_SET_BITSLICE(v_data_u8, + BMM050_POWER_CONTROL_SOFT_RST_1, + BMM050_SOFT_RESET1_ON); + com_rslt += p_bmm050->BMM050_BUS_WRITE_FUNC( + p_bmm050->dev_addr, + BMM050_POWER_CONTROL_SOFT_RST_1__REG, + &v_data_u8, BMM050_GEN_READ_WRITE_DATA_LENGTH); + + p_bmm050->delay_msec(BMM050_DELAY_SOFTRESET); + } + return com_rslt; +} +/*! + * @brief This API reads Magnetometer + * raw data of X,Y,Z values and RHALL values + * from location 0x42 to 0x49 + * + * + * + * + * @param mag_data : The data of raw XYZ data + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_get_raw_xyz( + struct bmm050_mag_data_s16_t *mag_data) +{ + /* variable used to return the bus communication result*/ + BMM050_RETURN_FUNCTION_TYPE com_rslt = ERROR; + /* Array holding the mag XYZ and R data + v_data_u8[0] - X LSB + v_data_u8[1] - X MSB + v_data_u8[2] - Y LSB + v_data_u8[3] - Y MSB + v_data_u8[4] - Z LSB + v_data_u8[5] - Z MSB + v_data_u8[6] - R LSB + v_data_u8[7] - R MSB + */ + u8 v_data_u8[BMM050_DATA_FRAME_SIZE] = + { + BMM050_INIT_VALUE, BMM050_INIT_VALUE, + BMM050_INIT_VALUE, BMM050_INIT_VALUE, + BMM050_INIT_VALUE, BMM050_INIT_VALUE, + BMM050_INIT_VALUE, BMM050_INIT_VALUE + }; + /* check the p_bmm050 pointer is NULL*/ + if (p_bmm050 == BMM050_NULL) + { + return E_BMM050_NULL_PTR; + } + else + { + com_rslt = p_bmm050->BMM050_BUS_READ_FUNC(p_bmm050->dev_addr, + BMM050_DATA_X_LSB, v_data_u8, BMM050_ALL_DATA_FRAME_LENGTH); + if (!com_rslt) + { + /* x data */ + v_data_u8[BMM050_XLSB_DATA] = + BMM050_GET_BITSLICE(v_data_u8[BMM050_XLSB_DATA], + BMM050_DATA_X_LSB_BIT); + mag_data->datax = (s16)((((s32) + ((s8)v_data_u8[BMM050_XMSB_DATA])) + << BMM050_SHIFT_BIT_POSITION_BY_05_BITS) + | v_data_u8[BMM050_XLSB_DATA]); + /* y data */ + v_data_u8[BMM050_YLSB_DATA] = + BMM050_GET_BITSLICE(v_data_u8[BMM050_YLSB_DATA], + BMM050_DATA_Y_LSB_BIT); + mag_data->datay = (s16)((((s32) + ((s8)v_data_u8[BMM050_YMSB_DATA])) + << BMM050_SHIFT_BIT_POSITION_BY_05_BITS) + | v_data_u8[BMM050_YLSB_DATA]); + /* z data */ + v_data_u8[BMM050_ZLSB_DATA] = + BMM050_GET_BITSLICE(v_data_u8[BMM050_ZLSB_DATA], + BMM050_DATA_Z_LSB_BIT); + mag_data->dataz = (s16)((((s32) + ((s8)v_data_u8[BMM050_ZMSB_DATA])) + << BMM050_SHIFT_BIT_POSITION_BY_07_BITS) + | v_data_u8[BMM050_ZLSB_DATA]); + + + /* read the data ready status*/ + mag_data->data_ready = BMM050_GET_BITSLICE( + v_data_u8[BMM050_RLSB_DATA], + BMM050_DATA_RDYSTAT); + + + + + /* r data */ + v_data_u8[BMM050_RLSB_DATA] = + BMM050_GET_BITSLICE(v_data_u8[BMM050_RLSB_DATA], + BMM050_DATA_R_LSB_BIT); + mag_data->resistance = (u16)((((u32) + v_data_u8[BMM050_RMSB_DATA]) << + BMM050_SHIFT_BIT_POSITION_BY_06_BITS) + | v_data_u8[BMM050_RLSB_DATA]); + } + } + return com_rslt; +} +/*! + * @brief This API reads remapped Magnetometer + * raw data of X,Y,Z values and RHALL values + * from location 0x42 to 0x49 + * + * @note In this function X and Y axis is remapped + * @note X is read from the address 0x44 & 0x45 + * @note Y is read from the address 0x42 & 0x43 + * @note this API is only applicable for BMX055 sensor + * + * + * + * @param mag_data : The data of remapped raw XYZ data + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_get_bmx055_remapped_raw_xyz( + struct bmm050_remapped_mag_s16_data_t *mag_data) +{ + /* variable used to return the bus communication result*/ + BMM050_RETURN_FUNCTION_TYPE com_rslt = ERROR; + /* Array holding the mag XYZ and R data + v_data_u8[0] - X LSB + v_data_u8[1] - X MSB + v_data_u8[2] - Y LSB + v_data_u8[3] - Y MSB + v_data_u8[4] - Z LSB + v_data_u8[5] - Z MSB + v_data_u8[6] - R LSB + v_data_u8[7] - R MSB + */ + u8 v_data_u8[BMM050_DATA_FRAME_SIZE] = + { + BMM050_INIT_VALUE, BMM050_INIT_VALUE, + BMM050_INIT_VALUE, BMM050_INIT_VALUE, + BMM050_INIT_VALUE, BMM050_INIT_VALUE, + BMM050_INIT_VALUE, BMM050_INIT_VALUE + }; + /* check the p_bmm050 pointer is NULL*/ + if (p_bmm050 == BMM050_NULL) + { + return E_BMM050_NULL_PTR; + } + else + { + com_rslt = p_bmm050->BMM050_BUS_READ_FUNC(p_bmm050->dev_addr, + BMM050_REMAPPED_BMX055_DATA_Y_LSB, + v_data_u8, BMM050_ALL_DATA_FRAME_LENGTH); + if (!com_rslt) + { + /* x data */ + v_data_u8[BMM050_XLSB_DATA] = + BMM050_GET_BITSLICE(v_data_u8[BMM050_XLSB_DATA], + BMM050_REMAPPED_BMX055_DATA_Y_LSB_BIT); + mag_data->datay = (s16)((((s32) + ((s8)v_data_u8[BMM050_XMSB_DATA])) + << BMM050_SHIFT_BIT_POSITION_BY_05_BITS) + | v_data_u8[BMM050_XLSB_DATA]); + /* y data */ + v_data_u8[BMM050_YLSB_DATA] = + BMM050_GET_BITSLICE(v_data_u8[BMM050_YLSB_DATA], + BMM050_REMAPPED_BMX055_DATA_X_LSB_BIT); + mag_data->datax = (s16)((((s32) + ((s8)v_data_u8[BMM050_YMSB_DATA])) + << BMM050_SHIFT_BIT_POSITION_BY_05_BITS) + | v_data_u8[BMM050_YLSB_DATA]); + mag_data->datax = -mag_data->datax; + /* z data */ + v_data_u8[BMM050_ZLSB_DATA] = + BMM050_GET_BITSLICE(v_data_u8[BMM050_ZLSB_DATA], + BMM050_DATA_Z_LSB_BIT); + mag_data->dataz = (s16)((((s32) + ((s8)v_data_u8[BMM050_ZMSB_DATA])) + << BMM050_SHIFT_BIT_POSITION_BY_07_BITS) + | v_data_u8[BMM050_ZLSB_DATA]); + + + /* read the data ready status*/ + mag_data->data_ready = BMM050_GET_BITSLICE( + v_data_u8[BMM050_RLSB_DATA], + BMM050_DATA_RDYSTAT); + + + /* r data */ + v_data_u8[BMM050_RLSB_DATA] = + BMM050_GET_BITSLICE(v_data_u8[BMM050_RLSB_DATA], + BMM050_DATA_R_LSB_BIT); + mag_data->resistance = (u16)((((u32) + v_data_u8[BMM050_RMSB_DATA]) << + BMM050_SHIFT_BIT_POSITION_BY_06_BITS) + | v_data_u8[BMM050_RLSB_DATA]); + } + } + return com_rslt; +} diff --git a/bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMM050_driver/bmm050.h b/bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMM050_driver/bmm050.h new file mode 100644 index 0000000000000000000000000000000000000000..cf93270e01580d2a7345aff09a9645458d0b2c19 --- /dev/null +++ b/bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMM050_driver/bmm050.h @@ -0,0 +1,1827 @@ +/** \mainpage +* +**************************************************************************** +* Copyright (C) 2015 - 2016 Bosch Sensortec GmbH +* +* File : bmm050.h +* +* Date : 2016/03/17 +* +* Revision : 2.0.5 $ +* +* Usage: Sensor Driver for BMM050 and BMM150 sensor +* +**************************************************************************** +* +* \section License +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* Neither the name of the copyright holder nor the names of the +* contributors may be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDER +* OR CONTRIBUTORS BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, +* OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT NOT LIMITED TO, +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* The information provided is believed to be accurate and reliable. +* The copyright holder assumes no responsibility +* for the consequences of use +* of such information nor for any infringement of patents or +* other rights of third parties which may result from its use. +* No license is granted by implication or otherwise under any patent or +* patent rights of the copyright holder. +**************************************************************************/ +/****************************************************************************/ + +/*! \file bmm050.h + \brief BMM050 Sensor Driver Support Header File */ + +#ifndef __BMM050_H__ +#define __BMM050_H__ + +/*! +* @brief For Enabling and Disabling the floating point API's +* If your platform supports the FLOAT support, please enable this +* macro +*/ +/*#define ENABLE_FLOAT*/ + +/*! +* @brief The following definition uses for define the data types +* +* @note While porting the API please consider the following +* @note Please check the version of C standard +* @note Are you using Linux platform +*/ + +/*! +* @brief For the Linux platform support +* Please use the types.h for your data types definitions +*/ +#ifdef __KERNEL__ + + #include + /* singed integer type*/ + typedef int8_t s8;/**< used for signed 8bit */ + typedef int16_t s16;/**< used for signed 16bit */ + typedef int32_t s32;/**< used for signed 32bit */ + typedef int64_t s64;/**< used for signed 64bit */ + + typedef u_int8_t u8;/**< used for unsigned 8bit */ + typedef u_int16_t u16;/**< used for unsigned 16bit */ + typedef u_int32_t u32;/**< used for unsigned 32bit */ + typedef u_int64_t u64;/**< used for unsigned 64bit */ + + + +#else /* ! __KERNEL__ */ + /********************************************************** + * These definition uses for define the C + * standard version data types + ***********************************************************/ + #if !defined(__STDC_VERSION__) + + /************************************************ + * compiler is C11 C standard + ************************************************/ + #if (__STDC_VERSION__ == 201112L) + + /************************************************/ + #include + /************************************************/ + + /*unsigned integer types*/ + typedef uint8_t u8;/**< used for unsigned 8bit */ + typedef uint16_t u16;/**< used for unsigned 16bit */ + typedef uint32_t u32;/**< used for unsigned 32bit */ + typedef uint64_t u64;/**< used for unsigned 64bit */ + + /*signed integer types*/ + typedef int8_t s8;/**< used for signed 8bit */ + typedef int16_t s16;/**< used for signed 16bit */ + typedef int32_t s32;/**< used for signed 32bit */ + typedef int64_t s64;/**< used for signed 64bit */ + /************************************************ + * compiler is C99 C standard + ************************************************/ + + #elif (__STDC_VERSION__ == 199901L) + + /* stdint.h is a C99 supported c library. + which is used to fixed the integer size*/ + /************************************************/ + #include + /************************************************/ + + /*unsigned integer types*/ + typedef uint8_t u8;/**< used for unsigned 8bit */ + typedef uint16_t u16;/**< used for unsigned 16bit */ + typedef uint32_t u32;/**< used for unsigned 32bit */ + typedef uint64_t u64;/**< used for unsigned 64bit */ + + /*signed integer types*/ + typedef int8_t s8;/**< used for signed 8bit */ + typedef int16_t s16;/**< used for signed 16bit */ + typedef int32_t s32;/**< used for signed 32bit */ + typedef int64_t s64;/**< used for signed 64bit */ + /************************************************ + * compiler is C89 or other C standard + ************************************************/ + + #else /* !defined(__STDC_VERSION__) */ + /*! + * @brief By default it is defined as 32 bit machine configuration + * define your data types based on your + * machine/compiler/controller configuration + */ + #define MACHINE_32_BIT + + /*! @brief + * If your machine support 16 bit + * define the MACHINE_16_BIT + */ + #ifdef MACHINE_16_BIT + #include + /*signed integer types*/ + typedef signed char s8;/**< used for signed 8bit */ + typedef signed short int s16;/**< used for signed 16bit */ + typedef signed long int s32;/**< used for signed 32bit */ + + #if defined(LONG_MAX) && (LONG_MAX == 0x7fffffffffffffffL) + typedef long int s64;/**< used for signed 64bit */ + typedef unsigned long int u64;/**< used for unsigned 64bit */ + #elif defined(LLONG_MAX) && (LLONG_MAX == 0x7fffffffffffffffLL) + typedef long long int s64;/**< used for signed 64bit */ + typedef unsigned long long int u64;/**< used for unsigned 64bit */ + #else + #warning Either the correct data type for signed 64 bit integer \ + could not be found, or 64 bit integers are not supported in your environment. + #warning If 64 bit integers are supported on your platform, \ + please set s64 manually. + #endif + + /*unsigned integer types*/ + typedef unsigned char u8;/**< used for unsigned 8bit */ + typedef unsigned short int u16;/**< used for unsigned 16bit */ + typedef unsigned long int u32;/**< used for unsigned 32bit */ + + /* If your machine support 32 bit + define the MACHINE_32_BIT*/ + #elif defined MACHINE_32_BIT + /*signed integer types*/ + typedef signed char s8;/**< used for signed 8bit */ + typedef signed short int s16;/**< used for signed 16bit */ + typedef signed int s32;/**< used for signed 32bit */ + typedef signed long long int s64;/**< used for signed 64bit */ + + /*unsigned integer types*/ + typedef unsigned char u8;/**< used for unsigned 8bit */ + typedef unsigned short int u16;/**< used for unsigned 16bit */ + typedef unsigned int u32;/**< used for unsigned 32bit */ + typedef unsigned long long int u64;/**< used for unsigned 64bit */ + + /* If your machine support 64 bit + define the MACHINE_64_BIT*/ + #elif defined MACHINE_64_BIT + /*signed integer types*/ + typedef signed char s8;/**< used for signed 8bit */ + typedef signed short int s16;/**< used for signed 16bit */ + typedef signed int s32;/**< used for signed 32bit */ + typedef signed long int s64;/**< used for signed 64bit */ + + /*unsigned integer types*/ + typedef unsigned char u8;/**< used for unsigned 8bit */ + typedef unsigned short int u16;/**< used for unsigned 16bit */ + typedef unsigned int u32;/**< used for unsigned 32bit */ + typedef unsigned long int u64;/**< used for unsigned 64bit */ + + #else + #warning The data types defined above which not supported \ + define the data types manually + #endif + #endif + + /*** This else will execute for the compilers + * which are not supported the C standards + * Like C89/C99/C11***/ + #else + /*! + * @brief By default it is defined as 32 bit machine configuration + * define your data types based on your + * machine/compiler/controller configuration + */ + #define MACHINE_32_BIT + + /* If your machine support 16 bit + define the MACHINE_16_BIT*/ + #ifdef MACHINE_16_BIT + #include + /*signed integer types*/ + typedef signed char s8;/**< used for signed 8bit */ + typedef signed short int s16;/**< used for signed 16bit */ + typedef signed long int s32;/**< used for signed 32bit */ + + #if defined(LONG_MAX) && LONG_MAX == 0x7fffffffffffffffL + typedef long int s64;/**< used for signed 64bit */ + typedef unsigned long int u64;/**< used for unsigned 64bit */ + #elif defined(LLONG_MAX) && (LLONG_MAX == 0x7fffffffffffffffLL) + typedef long long int s64;/**< used for signed 64bit */ + typedef unsigned long long int u64;/**< used for unsigned 64bit */ + #else + #warning Either the correct data type for signed 64 bit integer \ + could not be found, or 64 bit integers are not supported in your environment. + #warning If 64 bit integers are supported on your platform, \ + please set s64 manually. + #endif + + /*unsigned integer types*/ + typedef unsigned char u8;/**< used for unsigned 8bit */ + typedef unsigned short int u16;/**< used for unsigned 16bit */ + typedef unsigned long int u32;/**< used for unsigned 32bit */ + + /*! @brief If your machine support 32 bit + define the MACHINE_32_BIT*/ + #elif defined MACHINE_32_BIT + /*signed integer types*/ + typedef signed char s8;/**< used for signed 8bit */ + typedef signed short int s16;/**< used for signed 16bit */ + typedef signed int s32;/**< used for signed 32bit */ + typedef signed long long int s64;/**< used for signed 64bit */ + + /*unsigned integer types*/ + typedef unsigned char u8;/**< used for unsigned 8bit */ + typedef unsigned short int u16;/**< used for unsigned 16bit */ + typedef unsigned int u32;/**< used for unsigned 32bit */ + typedef unsigned long long int u64;/**< used for unsigned 64bit */ + + /* If your machine support 64 bit + define the MACHINE_64_BIT*/ + #elif defined MACHINE_64_BIT + /*signed integer types*/ + typedef signed char s8;/**< used for signed 8bit */ + typedef signed short int s16;/**< used for signed 16bit */ + typedef signed int s32;/**< used for signed 32bit */ + typedef signed long int s64;/**< used for signed 64bit */ + + /*unsigned integer types*/ + typedef unsigned char u8;/**< used for unsigned 8bit */ + typedef unsigned short int u16;/**< used for unsigned 16bit */ + typedef unsigned int u32;/**< used for unsigned 32bit */ + typedef unsigned long int u64;/**< used for unsigned 64bit */ + + #else + #warning The data types defined above which not supported \ + define the data types manually + #endif + #endif +#endif +/***************************************************************/ +/**\name BUS READ AND WRITE FUNCTION POINTERS */ +/***************************************************************/ +/*! + @brief Define the calling convention of YOUR bus communication routine. + @note This includes types of parameters. This example shows the + configuration for an SPI bus link. + + If your communication function looks like this: + + write_my_bus_xy(u8 device_addr, u8 register_addr, + u8 * data, u8 length); + + The BMM050_WR_FUNC_PTR would equal: + + BMM050_WR_FUNC_PTR s8 (* bus_write)(u8, + u8, u8 *, u8) + + Parameters can be mixed as needed refer to the + refer BMM050_BUS_WRITE_FUNC macro. + + +*/ +#define BMM050_BUS_WR_RETURN_TYPE s8 +#define BMM050_BUS_WR_PARAM_TYPES \ +u8, u8, u8 *, u8 +#define BMM050_BUS_WR_PARAM_ORDER \ +(device_addr, register_addr, register_data, wr_len) +#define BMM050_BUS_WRITE_FUNC( \ +device_addr, register_addr, register_data, wr_len) \ +bus_write(device_addr, register_addr, register_data, wr_len) + +/*! + @brief link macro between API function calls and bus read function + @note The bus write function can change since this is a + system dependant issue. + + @note If the bus_read parameter calling order is like: reg_addr, + reg_data, wr_len it would be as it is here. + + @note If the parameters are differently ordered or your communication + function like I2C need to know the device address, + you can change this macro accordingly. + + + @note BMM050_BUS_READ_FUNC(dev_addr, reg_addr, reg_data, wr_len)\ + bus_read(dev_addr, reg_addr, reg_data, wr_len) + + @note This macro lets all API functions call + YOUR communication routine in a + way that equals your definition in the + refer BMM050_RD_FUNC_PTR definition. + + @note : this macro also includes the "MSB='1' + for reading BMM050 addresses. + +*/ +#define BMM050_BUS_RD_RETURN_TYPE s8 +#define BMM050_BUS_RD_PARAM_TYPES \ +u8, u8, u8 *, u8 +#define BMM050_BUS_RD_PARAM_ORDER (device_addr, register_addr, register_data) +#define BMM050_BUS_READ_FUNC(device_addr, register_addr, register_data, rd_len)\ +bus_read(device_addr, register_addr, register_data, rd_len) +/***************************************************************/ +/**\name RETURN TYPE DEFINITIONS */ +/***************************************************************/ +#define BMM050_DELAY_RETURN_TYPE void +#define BMM050_DELAY_FUNC(delay_in_msec) \ +delay_func(delay_in_msec) +#define BMM050_RETURN_FUNCTION_TYPE s8 +/***************************************************************/ +/**\name I2C ADDRESS DEFINITIONS */ +/***************************************************************/ +#define BMM050_I2C_ADDRESS (0x10) +/***************************************************************/ +/**\name REGISTER ADDRESS DEFINITION */ +/***************************************************************/ +/********************************************/ +/**\name CHIP ID */ +/********************************************/ +/* Fixed Data Registers */ +#define BMM050_CHIP_ID (0x40) +/********************************************/ +/**\name DATA REGISTERS */ +/********************************************/ +/* Data Registers*/ +#define BMM050_DATA_X_LSB (0x42) +#define BMM050_DATA_X_MSB (0x43) +#define BMM050_DATA_Y_LSB (0x44) +#define BMM050_DATA_Y_MSB (0x45) +#define BMM050_DATA_Z_LSB (0x46) +#define BMM050_DATA_Z_MSB (0x47) +#define BMM050_DATA_R_LSB (0x48) +#define BMM050_DATA_R_MSB (0x49) +/********************************************/ +/**\name REMAPPED DATA REGISTERS */ +/********************************************/ +/* Data Registers for remapped axis(XandY) + * this only applicable for BMX055 */ +#define BMM050_REMAPPED_BMX055_DATA_Y_LSB (0x42) +#define BMM050_REMAPPED_BMX055_DATA_Y_MSB (0x43) +#define BMM050_REMAPPED_BMX055_DATA_X_LSB (0x44) +#define BMM050_REMAPPED_BMX055_DATA_X_MSB (0x45) +/********************************************/ +/**\name INTERRUPT STATUS */ +/********************************************/ +/* Status Registers */ +#define BMM050_INT_STAT_REG (0x4A) +/********************************************/ +/**\name POWER MODE DEFINITIONS */ +/********************************************/ +/* Control Registers */ +#define BMM050_POWER_CONTROL (0x4B) +#define BMM050_CONTROL (0x4C) +#define BMM050_INT_CONTROL (0x4D) +#define BMM050_SENS_CONTROL (0x4E) +#define BMM050_LOW_THRES (0x4F) +#define BMM050_HIGH_THRES (0x50) +/********************************************/ +/**\name XY AND Z REPETITIONS DEFINITIONS */ +/********************************************/ +#define BMM050_REP_XY (0x51) +#define BMM050_REP_Z (0x52) +/********************************************/ +/**\name TRIM REGISTERS */ +/********************************************/ +/* Trim Extended Registers */ +#define BMM050_DIG_X1 (0x5D) +#define BMM050_DIG_Y1 (0x5E) +#define BMM050_DIG_Z4_LSB (0x62) +#define BMM050_DIG_Z4_MSB (0x63) +#define BMM050_DIG_X2 (0x64) +#define BMM050_DIG_Y2 (0x65) +#define BMM050_DIG_Z2_LSB (0x68) +#define BMM050_DIG_Z2_MSB (0x69) +#define BMM050_DIG_Z1_LSB (0x6A) +#define BMM050_DIG_Z1_MSB (0x6B) +#define BMM050_DIG_XYZ1_LSB (0x6C) +#define BMM050_DIG_XYZ1_MSB (0x6D) +#define BMM050_DIG_Z3_LSB (0x6E) +#define BMM050_DIG_Z3_MSB (0x6F) +#define BMM050_DIG_XY2 (0x70) +#define BMM050_DIG_XY1 (0x71) + +/********************************************/ +/**\name BIT MASK, LENGTH AND POSITION OF DATA REGISTERS */ +/********************************************/ +/* Data X LSB Register */ +#define BMM050_DATA_X_LSB_BIT__POS (3) +#define BMM050_DATA_X_LSB_BIT__LEN (5) +#define BMM050_DATA_X_LSB_BIT__MSK (0xF8) +#define BMM050_DATA_X_LSB_BIT__REG (BMM050_DATA_X_LSB) + +/* Data X SelfTest Register */ +#define BMM050_DATA_X_LSB_TESTX__POS (0) +#define BMM050_DATA_X_LSB_TESTX__LEN (1) +#define BMM050_DATA_X_LSB_TESTX__MSK (0x01) +#define BMM050_DATA_X_LSB_TESTX__REG (BMM050_DATA_X_LSB) + +/* Data Y LSB Register */ +#define BMM050_DATA_Y_LSB_BIT__POS (3) +#define BMM050_DATA_Y_LSB_BIT__LEN (5) +#define BMM050_DATA_Y_LSB_BIT__MSK (0xF8) +#define BMM050_DATA_Y_LSB_BIT__REG (BMM050_DATA_Y_LSB) + +/* Data Y SelfTest Register */ +#define BMM050_DATA_Y_LSB_TESTY__POS (0) +#define BMM050_DATA_Y_LSB_TESTY__LEN (1) +#define BMM050_DATA_Y_LSB_TESTY__MSK (0x01) +#define BMM050_DATA_Y_LSB_TESTY__REG (BMM050_DATA_Y_LSB) + +/* Data Z LSB Register */ +#define BMM050_DATA_Z_LSB_BIT__POS (1) +#define BMM050_DATA_Z_LSB_BIT__LEN (7) +#define BMM050_DATA_Z_LSB_BIT__MSK (0xFE) +#define BMM050_DATA_Z_LSB_BIT__REG (BMM050_DATA_Z_LSB) + +/* Data Z SelfTest Register */ +#define BMM050_DATA_Z_LSB_TESTZ__POS (0) +#define BMM050_DATA_Z_LSB_TESTZ__LEN (1) +#define BMM050_DATA_Z_LSB_TESTZ__MSK (0x01) +#define BMM050_DATA_Z_LSB_TESTZ__REG (BMM050_DATA_Z_LSB) + +/* Hall Resistance LSB Register */ +#define BMM050_DATA_R_LSB_BIT__POS (2) +#define BMM050_DATA_R_LSB_BIT__LEN (6) +#define BMM050_DATA_R_LSB_BIT__MSK (0xFC) +#define BMM050_DATA_R_LSB_BIT__REG (BMM050_DATA_R_LSB) + +#define BMM050_DATA_RDYSTAT__POS (0) +#define BMM050_DATA_RDYSTAT__LEN (1) +#define BMM050_DATA_RDYSTAT__MSK (0x01) +#define BMM050_DATA_RDYSTAT__REG (BMM050_DATA_R_LSB) +/********************************************/ +/**\name BIT MASK, LENGTH AND POSITION OF REMAPPED DATA REGISTERS */ +/********************************************/ +/* Data X LSB Remapped Register only applicable for BMX055 */ +#define BMM050_REMAPPED_BMX055_DATA_X_LSB_BIT__POS (3) +#define BMM050_REMAPPED_BMX055_DATA_X_LSB_BIT__LEN (5) +#define BMM050_REMAPPED_BMX055_DATA_X_LSB_BIT__MSK (0xF8) +#define BMM050_REMAPPED_BMX055_DATA_X_LSB_BIT__REG\ +(BMM050_REMAPPED_BMX055_DATA_X_LSB) + +/* Data Y LSB Remapped Register only applicable for BMX055 */ +#define BMM050_REMAPPED_BMX055_DATA_Y_LSB_BIT__POS (3) +#define BMM050_REMAPPED_BMX055_DATA_Y_LSB_BIT__LEN (5) +#define BMM050_REMAPPED_BMX055_DATA_Y_LSB_BIT__MSK (0xF8) +#define BMM050_REMAPPED_BMX055_DATA_Y_LSB_BIT__REG\ +(BMM050_REMAPPED_BMX055_DATA_Y_LSB) +/********************************************/ +/**\name BIT MASK, LENGTH AND POSITION OF INTERRUPT STATUS REGISTERS */ +/********************************************/ +/* Interrupt Status Register */ +#define BMM050_INT_STAT_DOR__POS (7) +#define BMM050_INT_STAT_DOR__LEN (1) +#define BMM050_INT_STAT_DOR__MSK (0x80) +#define BMM050_INT_STAT_DOR__REG (BMM050_INT_STAT_REG) + +#define BMM050_INT_STAT_OVRFLOW__POS (6) +#define BMM050_INT_STAT_OVRFLOW__LEN (1) +#define BMM050_INT_STAT_OVRFLOW__MSK (0x40) +#define BMM050_INT_STAT_OVRFLOW__REG (BMM050_INT_STAT_REG) + +#define BMM050_INT_STAT_HIGH_THZ__POS (5) +#define BMM050_INT_STAT_HIGH_THZ__LEN (1) +#define BMM050_INT_STAT_HIGH_THZ__MSK (0x20) +#define BMM050_INT_STAT_HIGH_THZ__REG (BMM050_INT_STAT_REG) + +#define BMM050_INT_STAT_HIGH_THY__POS (4) +#define BMM050_INT_STAT_HIGH_THY__LEN (1) +#define BMM050_INT_STAT_HIGH_THY__MSK (0x10) +#define BMM050_INT_STAT_HIGH_THY__REG (BMM050_INT_STAT_REG) + +#define BMM050_INT_STAT_HIGH_THX__POS (3) +#define BMM050_INT_STAT_HIGH_THX__LEN (1) +#define BMM050_INT_STAT_HIGH_THX__MSK (0x08) +#define BMM050_INT_STAT_HIGH_THX__REG (BMM050_INT_STAT_REG) + +#define BMM050_INT_STAT_LOW_THZ__POS (2) +#define BMM050_INT_STAT_LOW_THZ__LEN (1) +#define BMM050_INT_STAT_LOW_THZ__MSK (0x04) +#define BMM050_INT_STAT_LOW_THZ__REG (BMM050_INT_STAT_REG) + +#define BMM050_INT_STAT_LOW_THY__POS (1) +#define BMM050_INT_STAT_LOW_THY__LEN (1) +#define BMM050_INT_STAT_LOW_THY__MSK (0x02) +#define BMM050_INT_STAT_LOW_THY__REG (BMM050_INT_STAT_REG) + +#define BMM050_INT_STAT_LOW_THX__POS (0) +#define BMM050_INT_STAT_LOW_THX__LEN (1) +#define BMM050_INT_STAT_LOW_THX__MSK (0x01) +#define BMM050_INT_STAT_LOW_THX__REG (BMM050_INT_STAT_REG) +/********************************************/ +/**\name BIT MASK, LENGTH AND POSITION OF SOFT RESET REGISTERS */ +/********************************************/ +/* Power Control Register */ +#define BMM050_POWER_CONTROL_SOFT_RST_7__POS (7) +#define BMM050_POWER_CONTROL_SOFT_RST_7__LEN (1) +#define BMM050_POWER_CONTROL_SOFT_RST_7__MSK (0x80) +#define BMM050_POWER_CONTROL_SOFT_RST_7__REG (BMM050_POWER_CONTROL) + +#define BMM050_POWER_CONTROL_SPI3_ENABLE__POS (2) +#define BMM050_POWER_CONTROL_SPI3_ENABLE__LEN (1) +#define BMM050_POWER_CONTROL_SPI3_ENABLE__MSK (0x04) +#define BMM050_POWER_CONTROL_SPI3_ENABLE__REG (BMM050_POWER_CONTROL) + +#define BMM050_POWER_CONTROL_SOFT_RST_1__POS (1) +#define BMM050_POWER_CONTROL_SOFT_RST_1__LEN (1) +#define BMM050_POWER_CONTROL_SOFT_RST_1__MSK (0x02) +#define BMM050_POWER_CONTROL_SOFT_RST_1__REG (BMM050_POWER_CONTROL) +/********************************************/ +/**\name BIT MASK, LENGTH AND POSITION OF POWER MODE REGISTERS */ +/********************************************/ +#define BMM050_POWER_CONTROL_POWER_CONTROL_BIT__POS (0) +#define BMM050_POWER_CONTROL_POWER_CONTROL_BIT__LEN (1) +#define BMM050_POWER_CONTROL_POWER_CONTROL_BIT__MSK (0x01) +#define BMM050_POWER_CONTROL_POWER_CONTROL_BIT__REG \ +(BMM050_POWER_CONTROL) +/********************************************/ +/**\name BIT MASK, LENGTH AND POSITION OF SELF TEST REGISTERS */ +/********************************************/ +/* Control Register */ +#define BMM050_CONTROL_ADVANCED_SELFTEST__POS (6) +#define BMM050_CONTROL_ADVANCED_SELFTEST__LEN (2) +#define BMM050_CONTROL_ADVANCED_SELFTEST__MSK (0xC0) +#define BMM050_CONTROL_ADVANCED_SELFTEST__REG (BMM050_CONTROL) +/********************************************/ +/**\name BIT MASK, LENGTH AND POSITION OF DATA RATE REGISTERS */ +/********************************************/ +#define BMM050_CONTROL_DATA_RATE__POS (3) +#define BMM050_CONTROL_DATA_RATE__LEN (3) +#define BMM050_CONTROL_DATA_RATE__MSK (0x38) +#define BMM050_CONTROL_DATA_RATE__REG (BMM050_CONTROL) +/********************************************/ +/**\name BIT MASK, LENGTH AND POSITION OF OPERATION MODE REGISTERS */ +/********************************************/ +#define BMM050_CONTROL_OPERATION_MODE__POS (1) +#define BMM050_CONTROL_OPERATION_MODE__LEN (2) +#define BMM050_CONTROL_OPERATION_MODE__MSK (0x06) +#define BMM050_CONTROL_OPERATION_MODE__REG (BMM050_CONTROL) +/********************************************/ +/**\name BIT MASK, LENGTH AND POSITION OF SELF TEST REGISTERS */ +/********************************************/ +#define BMM050_CONTROL_SELFTEST__POS (0) +#define BMM050_CONTROL_SELFTEST__LEN (1) +#define BMM050_CONTROL_SELFTEST__MSK (0x01) +#define BMM050_CONTROL_SELFTEST__REG (BMM050_CONTROL) +/********************************************/ +/**\name BIT MASK, LENGTH AND POSITION OF INTERRUPT CONTROL REGISTERS */ +/********************************************/ +/* Interrupt Control Register */ +#define BMM050_INT_CONTROL_DOR_EN__POS (7) +#define BMM050_INT_CONTROL_DOR_EN__LEN (1) +#define BMM050_INT_CONTROL_DOR_EN__MSK (0x80) +#define BMM050_INT_CONTROL_DOR_EN__REG (BMM050_INT_CONTROL) + +#define BMM050_INT_CONTROL_OVRFLOW_EN__POS (6) +#define BMM050_INT_CONTROL_OVRFLOW_EN__LEN (1) +#define BMM050_INT_CONTROL_OVRFLOW_EN__MSK (0x40) +#define BMM050_INT_CONTROL_OVRFLOW_EN__REG (BMM050_INT_CONTROL) + +#define BMM050_INT_CONTROL_HIGH_THZ_EN__POS (5) +#define BMM050_INT_CONTROL_HIGH_THZ_EN__LEN (1) +#define BMM050_INT_CONTROL_HIGH_THZ_EN__MSK (0x20) +#define BMM050_INT_CONTROL_HIGH_THZ_EN__REG (BMM050_INT_CONTROL) + +#define BMM050_INT_CONTROL_HIGH_THY_EN__POS (4) +#define BMM050_INT_CONTROL_HIGH_THY_EN__LEN (1) +#define BMM050_INT_CONTROL_HIGH_THY_EN__MSK (0x10) +#define BMM050_INT_CONTROL_HIGH_THY_EN__REG (BMM050_INT_CONTROL) + +#define BMM050_INT_CONTROL_HIGH_THX_EN__POS (3) +#define BMM050_INT_CONTROL_HIGH_THX_EN__LEN (1) +#define BMM050_INT_CONTROL_HIGH_THX_EN__MSK (0x08) +#define BMM050_INT_CONTROL_HIGH_THX_EN__REG (BMM050_INT_CONTROL) + +#define BMM050_INT_CONTROL_LOW_THZ_EN__POS (2) +#define BMM050_INT_CONTROL_LOW_THZ_EN__LEN (1) +#define BMM050_INT_CONTROL_LOW_THZ_EN__MSK (0x04) +#define BMM050_INT_CONTROL_LOW_THZ_EN__REG (BMM050_INT_CONTROL) + +#define BMM050_INT_CONTROL_LOW_THY_EN__POS (1) +#define BMM050_INT_CONTROL_LOW_THY_EN__LEN (1) +#define BMM050_INT_CONTROL_LOW_THY_EN__MSK (0x02) +#define BMM050_INT_CONTROL_LOW_THY_EN__REG (BMM050_INT_CONTROL) + +#define BMM050_INT_CONTROL_LOW_THX_EN__POS (0) +#define BMM050_INT_CONTROL_LOW_THX_EN__LEN (1) +#define BMM050_INT_CONTROL_LOW_THX_EN__MSK (0x01) +#define BMM050_INT_CONTROL_LOW_THX_EN__REG (BMM050_INT_CONTROL) + +/* Sensor Control Register */ +#define BMM050_SENS_CONTROL_DRDY_EN__POS (7) +#define BMM050_SENS_CONTROL_DRDY_EN__LEN (1) +#define BMM050_SENS_CONTROL_DRDY_EN__MSK (0x80) +#define BMM050_SENS_CONTROL_DRDY_EN__REG (BMM050_SENS_CONTROL) + +#define BMM050_SENS_CONTROL_IE__POS (6) +#define BMM050_SENS_CONTROL_IE__LEN (1) +#define BMM050_SENS_CONTROL_IE__MSK (0x40) +#define BMM050_SENS_CONTROL_IE__REG BMM050_SENS_CONTROL + +#define BMM050_SENS_CONTROL_CHANNELZ__POS (5) +#define BMM050_SENS_CONTROL_CHANNELZ__LEN (1) +#define BMM050_SENS_CONTROL_CHANNELZ__MSK (0x20) +#define BMM050_SENS_CONTROL_CHANNELZ__REG (BMM050_SENS_CONTROL) + +#define BMM050_SENS_CONTROL_CHANNELY__POS (4) +#define BMM050_SENS_CONTROL_CHANNELY__LEN (1) +#define BMM050_SENS_CONTROL_CHANNELY__MSK (0x10) +#define BMM050_SENS_CONTROL_CHANNELY__REG (BMM050_SENS_CONTROL) + +#define BMM050_SENS_CONTROL_CHANNELX__POS (3) +#define BMM050_SENS_CONTROL_CHANNELX__LEN (1) +#define BMM050_SENS_CONTROL_CHANNELX__MSK (0x08) +#define BMM050_SENS_CONTROL_CHANNELX__REG (BMM050_SENS_CONTROL) + +#define BMM050_SENS_CONTROL_DR_POLARITY__POS (2) +#define BMM050_SENS_CONTROL_DR_POLARITY__LEN (1) +#define BMM050_SENS_CONTROL_DR_POLARITY__MSK (0x04) +#define BMM050_SENS_CONTROL_DR_POLARITY__REG (BMM050_SENS_CONTROL) + +#define BMM050_SENS_CONTROL_INTERRUPT_LATCH__POS (1) +#define BMM050_SENS_CONTROL_INTERRUPT_LATCH__LEN (1) +#define BMM050_SENS_CONTROL_INTERRUPT_LATCH__MSK (0x02) +#define BMM050_SENS_CONTROL_INTERRUPT_LATCH__REG (BMM050_SENS_CONTROL) + +#define BMM050_SENS_CONTROL_INTERRUPT_POLARITY__POS (0) +#define BMM050_SENS_CONTROL_INTERRUPT_POLARITY__LEN (1) +#define BMM050_SENS_CONTROL_INTERRUPT_POLARITY__MSK (0x01) +#define BMM050_SENS_CONTROL_INTERRUPT_POLARITY__REG \ +(BMM050_SENS_CONTROL) +/********************************************/ +/**\name BIT MASK, LENGTH AND POSITION OF TRIM REGISTER */ +/********************************************/ +/* Register 6D */ +#define BMM050_DIG_XYZ1_MSB__POS (0) +#define BMM050_DIG_XYZ1_MSB__LEN (7) +#define BMM050_DIG_XYZ1_MSB__MSK (0x7F) +#define BMM050_DIG_XYZ1_MSB__REG (BMM050_DIG_XYZ1_MSB) +/*****************************************************************/ +/********************************************/ +/**\name CONSTANTS DEFINITIONS */ +/********************************************/ +/********************************************/ +/**\name ERROR CODE */ +/********************************************/ + +/** Error code definitions**/ +#define E_BMM050_NULL_PTR ((s8)-127) +#define ERROR ((s8)-1) +#define E_BMM050_OUT_OF_RANGE ((s8)-2) +#define BMM050_NULL ((u8)0) +#define E_BMM050_UNDEFINED_MODE (0) + +/********************************************/ +/**\name RESET DEFINITIONS */ +/********************************************/ +/*General Info data's*/ +#define BMM050_SOFT_RESET7_ON (1) +#define BMM050_SOFT_RESET1_ON (1) +#define BMM050_SOFT_RESET7_OFF (0) +#define BMM050_SOFT_RESET1_OFF (0) +#define BMM050_DELAY_SOFTRESET (1) + +/********************************************/ +/**\name DELAY DEFINITIONS */ +/********************************************/ +/* Constants */ +#define BMM050_DELAY_POWEROFF_SUSPEND (1) +#define BMM050_DELAY_SUSPEND_SLEEP (3) +#define BMM050_DELAY_SLEEP_ACTIVE (1) +#define BMM050_DELAY_ACTIVE_SLEEP (1) +#define BMM050_DELAY_SLEEP_SUSPEND (1) +#define BMM050_DELAY_ACTIVE_SUSPEND (1) +#define BMM050_DELAY_SLEEP_POWEROFF (1) +#define BMM050_DELAY_ACTIVE_POWEROFF (1) +#define BMM050_DELAY_SETTLING_TIME (3) +#define BMM050_MDELAY_DATA_TYPE u32 +/********************************************/ +/**\name XYZ AXIS DEFINITIONS */ +/********************************************/ +#define BMM050_X_AXIS (0) +#define BMM050_Y_AXIS (1) +#define BMM050_Z_AXIS (2) +#define BMM050_RESISTANCE (3) +#define BMM050_X (1) +#define BMM050_Y (2) +#define BMM050_Z (4) +#define BMM050_XYZ (7) +/********************************************/ +/**\name ENABLE/DISABLE DEFINITIONS */ +/********************************************/ +#define BMM050_CHANNEL_DISABLE (1) +#define BMM050_CHANNEL_ENABLE (0) +#define BMM050_OFF (0) +#define BMM050_ON (1) +/********************************************/ +/**\name POWER MODE DEFINITIONS */ +/********************************************/ +#define BMM050_NORMAL_MODE (0x00) +#define BMM050_FORCED_MODE (0x01) +#define BMM050_SUSPEND_MODE (0x02) +#define BMM050_SLEEP_MODE (0x03) +/********************************************/ +/**\name SELF TEST DEFINITIONS */ +/********************************************/ +#define BMM050_ADVANCED_SELFTEST_OFF (0) +#define BMM050_ADVANCED_SELFTEST_NEGATIVE (2) +#define BMM050_ADVANCED_SELFTEST_POSITIVE (3) + +#define BMM050_NEGATIVE_SATURATION_Z (-32767) +#define BMM050_POSITIVE_SATURATION_Z (32767) +/********************************************/ +/**\name SPI READ/WRITE DEFINITIONS */ +/********************************************/ +#define BMM050_SPI_RD_MASK (0x80) +#define BMM050_READ_SET (0x01) +/********************************************/ +/**\name READ AND WRITE FUNCTION POINTERS */ +/********************************************/ +/* Bus read and bus write */ +#define BMM050_WR_FUNC_PTR \ + s8 (*bus_write)(u8, u8, \ + u8 *, u8) + +#define BMM050_RD_FUNC_PTR \ + s8 (*bus_read)(u8, u8, \ + u8 *, u8) + +/********************************************/ +/**\name NUMERIC DEFINITIONS */ +/********************************************/ +#define BMM050_GEN_READ_WRITE_DATA_LENGTH ((u8)1) +#define BMM050_TRIM_DATA_LENGTH ((u8)2) +#define BMM050_SELFTEST_DELAY ((u8)4) +#define BMM050_SELFTEST_DATA_LENGTH ((u8)5) +#define BMM050_ALL_DATA_FRAME_LENGTH ((u8)8) +/**< Frame length refers the +x,y,z and r values*/ +#define BMM050_INIT_VALUE (0) + +/********************************************/ +/**\name GET AND SET BITSLICE FUNCTIONS */ +/********************************************/ +/* get bit slice */ +#define BMM050_GET_BITSLICE(regvar, bitname)\ + ((regvar & bitname##__MSK) >> bitname##__POS) + +/* Set bit slice */ +#define BMM050_SET_BITSLICE(regvar, bitname, val)\ + ((regvar & ~bitname##__MSK) | ((val< Success + * @retval -1 -> Error + * + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_init(struct bmm050_t *bmm050); +/********************************************/ +/**\name DATA READ FUNCTIONS */ +/********************************************/ +/*! + * @brief This API reads compensated Magnetometer + * data of X,Y,Z values + * from location 0x42 to 0x49 + * + * + * + * + * @param mag_data : The data of mag compensated XYZ data + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_read_mag_data_XYZ( + struct bmm050_mag_data_s16_t *mag_data); +/*! + * @brief This API reads remapped compensated Magnetometer + * data of X,Y,Z values + * @note In this function X and Y axis is remapped + * @note X is read from the address 0x44 & 0x45 + * @note Y is read from the address 0x42 & 0x43 + * @note this API is only applicable for BMX055 sensor + * + * + * + * @param mag_data : The data of remapped compensated mag xyz data + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_read_bmx055_remapped_mag_data_XYZ( + struct bmm050_remapped_mag_s16_data_t *mag_data); +/*! + * @brief This API reads compensated magnetometer + * data of X,Y,Z values + * @note The output value of compensated X, Y, Z as s32 + * + * + * @param mag_data : The data of compensated XYZ data + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_read_mag_data_XYZ_s32( + struct bmm050_mag_s32_data_t *mag_data); +/*! + * @brief This API reads remapped compensated magnetometer + * data of X,Y,Z values + * @note The output value of compensated X, Y, Z as s32 + * @note In this function X and Y axis is remapped + * @note X is read from the address 0x44 & 0x45 + * @note Y is read from the address 0x42 & 0x43 + * @note this API is only applicable for BMX055 sensor + * + * + * @param mag_data : The data of remapped compensated XYZ data + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_read_bmx055_remapped_mag_data_XYZ_s32( + struct bmm050_remapped_mag_s32_data_t *mag_data); +#ifdef ENABLE_FLOAT +/*! + * @brief This API reads compensated Magnetometer + * data of X,Y,Z values + * @note The output value of compensated X, Y, Z as float + * + * + * + * @param mag_data : The value of compensated XYZ float data + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_read_mag_data_XYZ_float( + struct bmm050_mag_data_float_t *mag_data); +#endif +#ifdef ENABLE_FLOAT +/*! + * @brief This API reads remapped compensated Magnetometer + * data of X,Y,Z values + * @note The output value of compensated X, Y, Z as float + * + * @note In this function X and Y axis is remapped + * @note X is read from the address 0x44 & 0x45 + * @note Y is read from the address 0x42 & 0x43 + * @note this API is only applicable for BMX055 sensor + * + * @param mag_data : The value of remapped compensated XYZ float data + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_read_bmx055_remapped_mag_data_XYZ_float( + struct bmm050_remapped_mag_data_float_t *mag_data); +#endif +/********************************************/ +/**\name COMMON READ AND WRITE FUNCTIONS */ +/********************************************/ +/*! + * @brief + * This API reads the data from + * the given register + * + * + * @param v_addr_u8 -> Address of the register + * @param v_data_u8 -> The data from the register + * @param v_len_u8 -> no of bytes to read + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMM050_RETURN_FUNCTION_TYPE bmm050_read_register(u8 v_addr_u8, + u8 *v_data_u8, u8 v_len_u8); +/*! + * @brief + * This API write the data to + * the given register + * + * + * @param v_addr_u8 -> Address of the register + * @param v_data_u8 -> The data from the register + * @param v_len_u8 -> no of bytes to read + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * + * + */ +BMM050_RETURN_FUNCTION_TYPE bmm050_write_register(u8 v_addr_u8, + u8 *v_data_u8, u8 v_len_u8); +/********************************************/ +/**\name SELF TEST FUNCTION */ +/********************************************/ +/*! + * @brief This API used to set the self test of the sensor + * in the register 0x4C bit 0 + * + * + * + * @param v_selftest_u8 : The value of selftest + * @note write 0x01 to start self test + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_set_selftest(u8 v_selftest_u8); +/*! + * @brief This API used to read the selftest of the sensor + * + * + * + * + * @param v_selftest_xyz: The self test value of XYZ + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_get_selftest_XYZ( + u8 *v_selftest_xyz); +/********************************************/ +/**\name SPI ENABLE FUNCTION */ +/********************************************/ +/*! + * @brief This API used to set the spi3 + * in the register 0x4B bit 2 + * + * + * + * @param v_value_u8 : the value of spi3 + * value | Description + * --------|------------ + * 0 | Disable + * 1 | Enable + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_set_spi3(u8 v_value_u8); +/********************************************/ +/**\name DATA RATE FUNCTIONS */ +/********************************************/ +/*! + * @brief This API used to set the data rate of the sensor + * in the register 0x4C bit 3 to 5 + * + * + * + * @param v_data_rate_u8 : The value of data rate + * value | Description + * -----------|----------------------- + * 0x00 | BMM050_DATA_RATE_10HZ + * 0x01 | BMM050_DATA_RATE_02HZ + * 0x02 | BMM050_DATA_RATE_06HZ + * 0x03 | BMM050_DATA_RATE_08HZ + * 0x04 | BMM050_DATA_RATE_15HZ + * 0x05 | BMM050_DATA_RATE_20HZ + * 0x06 | BMM050_DATA_RATE_25HZ + * 0x07 | BMM050_DATA_RATE_30HZ + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_set_data_rate(u8 v_data_rate_u8); +/*! + * @brief This API used to get the data rate of the sensor + * in the register 0x4C bit 3 to 5 + * + * + * + * @param v_data_rate_u8 : The value of data rate + * value | Description + * -----------|----------------------- + * 0x00 | BMM050_DATA_RATE_10HZ + * 0x01 | BMM050_DATA_RATE_02HZ + * 0x02 | BMM050_DATA_RATE_06HZ + * 0x03 | BMM050_DATA_RATE_08HZ + * 0x04 | BMM050_DATA_RATE_15HZ + * 0x05 | BMM050_DATA_RATE_20HZ + * 0x06 | BMM050_DATA_RATE_25HZ + * 0x07 | BMM050_DATA_RATE_30HZ + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_get_data_rate(u8 *v_data_rate_u8); +/********************************************/ +/**\name FUNCTIONAL STATE FUNCTION */ +/********************************************/ +/*! + * @brief This API used to set the functional state + * in the register 0x4C and 0x4B + * @note 0x4C bit 1 and 2 + * @note 0x4B bit 0 + * + * + * @param v_functional_state_u8: The value of functional mode + * value | functional state + * -----------|------------------- + * 0x00 | BMM050_NORMAL_MODE + * 0x01 | BMM050_SUSPEND_MODE + * 0x02 | BMM050_FORCED_MODE + * 0x03 | BMM050_SLEEP_MODE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_set_functional_state( + u8 v_functional_state_u8); +/*! + * @brief This API used to get the functional state + * in the register 0x4C bit 1 and 2 + * + * + * + * + * @param v_functional_state_u8: The value of functional mode + * value | functional state + * -----------|-------------------- + * 0x00 | Normal + * 0x03 | Sleep + * @note If user set the functional state as Force mode(0x01) and read the + * register it returns the value as 0x03 that is sleep mode. + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_get_functional_state( + u8 *v_functional_state_u8); +/********************************************/ +/**\name ADVANCED SELFTEST */ +/********************************************/ +/*! + * @brief This API used to perform the + * advanced self test + * + * + * + * @param v_diff_z_s16 : The output of advance self test + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_perform_advanced_selftest( + s16 *v_diff_z_s16); +/********************************************/ +/**\name TRIM REGISTER */ +/********************************************/ +/*! + * @brief This API used to get the trim values + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + */ +BMM050_RETURN_FUNCTION_TYPE bmm050_init_trim_registers(void); +/********************************************/ +/**\name SET ADVANCED SELFTEST */ +/********************************************/ +/*! + * @brief This API used to set the advanced self test + * in the register 0x4C bit 6 and 7 + * + * + * + * @param v_advanced_selftest_u8 : The output value of advanced self test + * value | Status + * -------------|------------------- + * 0 | BMM050_ADVANCED_SELFTEST_OFF + * 2 | BMM050_ADVANCED_SELFTEST_NEGATIVE + * 3 | BMM050_ADVANCED_SELFTEST_POSITIVE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_set_advanced_selftest( + u8 v_advanced_selftest_u8); +/*! + * @brief This API used to get the advanced self test + * in the register 0x4C bit 6 and 7 + * + * + * + * @param v_advanced_selftest_u8 : The output value of advanced self test + * value | Status + * -------------|------------------- + * 0 | BMM050_ADVANCED_SELFTEST_OFF + * 2 | BMM050_ADVANCED_SELFTEST_NEGATIVE + * 3 | BMM050_ADVANCED_SELFTEST_POSITIVE + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_get_advanced_selftest( + u8 *v_advanced_selftest_u8); +/********************************************/ +/**\name POWER MODE */ +/********************************************/ +/*! + * @brief This API used to get the power control bit + * in the register 0x4B bit 0 + * + * + * + * @param v_power_mode_u8 : The value of power control bit enable + * value | status + * -----------|------------ + * 0 | Disable the power control bit + * 1 | Enable the power control bit + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_get_power_mode(u8 *v_power_mode_u8); +/*! + * @brief This API used to set the power control bit + * in the register 0x4B bit 0 + * + * + * + * @param v_power_mode_u8 : The value of power control bit enable + * value | status + * -----------|------------ + * 0 | Disable the power control bit + * 1 | Enable the power control bit + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_set_power_mode(u8 v_power_mode_u8); +/********************************************/ +/**\name XY AND Z REPETITIONS */ +/********************************************/ +/*! + * @brief This API used to get the x and y + * repetition in the register 0x51 bit 0 to 7 + * + * + * + * @param v_rep_xy_u8 : The value of x and y repetitions + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_get_rep_XY( + u8 *v_rep_xy_u8); +/*! + * @brief This API used to set the x and y + * repetition in the register 0x51 bit 0 to 7 + * + * + * + * @param v_rep_xy_u8 : The value of x and y repetitions + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_set_rep_XY( + u8 v_rep_xy_u8); +/*! + * @brief This API used to get the z repetition in the + * register 0x52 bit 0 to 7 + * + * + * + * @param v_rep_z_u8 : The value of z repetitions + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_get_rep_Z( + u8 *v_rep_z_u8); +/*! + * @brief This API used to set the z repetition in the + * register 0x52 bit 0 to 7 + * + * + * + * @param v_rep_z_u8 : The value of z repetitions + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_set_rep_Z( + u8 v_rep_z_u8); +/********************************************/ +/**\name PRESET MODE */ +/********************************************/ +/*! + * @brief This API used to get the preset modes + * + * @note The preset mode setting is + * depend on Data Rate, XY and Z repetitions + * + * + * + * @param v_presetmode_u8: The value of selected preset mode + * value | preset_mode + * ----------|----------------- + * 1 | BMM050_PRESETMODE_LOWPOWER + * 2 | BMM050_PRESETMODE_REGULAR + * 3 | BMM050_PRESETMODE_HIGHACCURACY + * 4 | BMM050_PRESETMODE_ENHANCED + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_get_presetmode( + u8 *v_presetmode_u8); +/*! + * @brief This API used to set the preset modes + * + * @note The preset mode setting is + * depend on Data Rate, XY and Z repetitions + * + * + * + * @param v_presetmode_u8: The value of selected preset mode + * value | preset_mode + * ----------|----------------- + * 1 | BMM050_PRESETMODE_LOWPOWER + * 2 | BMM050_PRESETMODE_REGULAR + * 3 | BMM050_PRESETMODE_HIGHACCURACY + * 4 | BMM050_PRESETMODE_ENHANCED + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_set_presetmode(u8 v_presetmode_u8); +/********************************************/ +/**\name COMPENSATE X DATA */ +/********************************************/ +/*! + * @brief This API used to get the compensated X data + * the out put of X as s16 + * + * + * + * @param mag_data_x : The value of raw X data + * @param data_r : The value of R data + * + * @return results of compensated X data value output as s16 + * +*/ +s16 bmm050_compensate_X(s16 mag_data_x, u16 data_r); +/*! + * @brief This API used to get the compensated X data + * the out put of X as s32 + * + * + * + * @param mag_data_x : The value of raw X data + * @param data_r : The value of R data + * + * @return results of compensated X data value output as s32 + * +*/ +s32 bmm050_compensate_X_s32(s16 mag_data_x, u16 data_r); +#ifdef ENABLE_FLOAT + /*! + * @brief This API used to get the compensated X data + * the out put of X as float + * + * + * + * @param mag_data_x : The value of raw X data + * @param data_r : The value of R data + * + * @return results of compensated X data value output as float + * + */ + float bmm050_compensate_X_float(s16 mag_data_x, u16 data_r); +#endif +/********************************************/ +/**\name COMPENSATE Y DATA */ +/********************************************/ +/*! + * @brief This API used to get the compensated Y data + * the out put of Y as s16 + * + * + * + * @param mag_data_y : The value of raw Y data + * @param data_r : The value of R data + * + * @return results of compensated Y data value output as s16 + * +*/ +s16 bmm050_compensate_Y(s16 mag_data_y, u16 data_r); +/*! + * @brief This API used to get the compensated Y data + * the out put of Y as s32 + * + * + * + * @param mag_data_y : The value of raw Y data + * @param data_r : The value of R data + * + * @return results of compensated Y data value output as s32 + * +*/ +s32 bmm050_compensate_Y_s32(s16 mag_data_y, u16 data_r); +#ifdef ENABLE_FLOAT + /*! + * @brief This API used to get the compensated Y data + * the out put of Y as float + * + * + * + * @param mag_data_y : The value of raw Y data + * @param data_r : The value of R data + * + * @return results of compensated Y data value output as float + * + */ + float bmm050_compensate_Y_float(s16 mag_data_y, u16 data_r); +#endif +/********************************************/ +/**\name COMPENSATE Z DATA */ +/********************************************/ +/*! + * @brief This API used to get the compensated Z data + * the out put of Z as s16 + * + * + * + * @param mag_data_z : The value of raw Z data + * @param data_r : The value of R data + * + * @return results of compensated Z data value output as s16 + * +*/ +s16 bmm050_compensate_Z(s16 mag_data_z, u16 data_r); +/*! + * @brief This API used to get the compensated Z data + * the out put of Z as s32 + * + * + * + * @param mag_data_z : The value of raw Z data + * @param data_r : The value of R data + * + * @return results of compensated Z data value output as s32 + * +*/ +s32 bmm050_compensate_Z_s32(s16 mag_data_z, u16 data_r); +#ifdef ENABLE_FLOAT + /*! + * @brief This API used to get the compensated Z data + * the out put of Z as float + * + * + * + * @param mag_data_z : The value of raw Z data + * @param data_r : The value of R data + * + * @return results of compensated Z data value output as float + * + */ + float bmm050_compensate_Z_float(s16 mag_data_z, u16 data_r); +#endif +/********************************************/ +/**\name CONTROL MEASUREMENT OF X AND Y */ +/********************************************/ +/*! + * @brief This API used to set the control measurement + * X data in the register 0x4E bit 3 + * + * + * @param v_enable_disable_u8: The value of control measurement-x + * value | Status + * --------|---------- + * 1 | ENABLE + * 0 | DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_set_control_measurement_x( + u8 v_enable_disable_u8); +/*! + * @brief This API used to set the control measurement + * Y data in the register 0x4E bit 4 + * + * + * @param v_enable_disable_u8: The value of control measurement-y + * value | Status + * --------|---------- + * 1 | ENABLE + * 0 | DISABLE + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_set_control_measurement_y( + u8 v_enable_disable_u8); +/********************************************/ +/**\name SOFT RESET */ +/********************************************/ +/*! + * @brief This API used reset the register values to default + * in the register 0x4B + * + * + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_soft_rst(void); +/********************************************/ +/**\name RAW XYZ DATA */ +/********************************************/ +/*! + * @brief This API reads Magnetometer + * raw data of X,Y,Z values and RHALL values + * from location 0x42 to 0x49 + * + * + * + * + * @param mag_data : The data of raw XYZ data + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_get_raw_xyz( + struct bmm050_mag_data_s16_t *mag_data); +/********************************************/ +/**\name REMAPPED RAW XYZ DATA */ +/********************************************/ +/*! + * @brief This API reads remapped Magnetometer + * raw data of X,Y,Z values and RHALL values + * from location 0x42 to 0x49 + * + * @note In this function X and Y axis is remapped + * @note X is read from the address 0x44 & 0x45 + * @note Y is read from the address 0x42 & 0x43 + * @note this API is only applicable for BMX055 sensor + * + * + * + * @param mag_data : The data of remapped raw XYZ data + * + * + * @return results of bus communication function + * @retval 0 -> Success + * @retval -1 -> Error + * +*/ +BMM050_RETURN_FUNCTION_TYPE bmm050_get_bmx055_remapped_raw_xyz( + struct bmm050_remapped_mag_s16_data_t *mag_data); + +#endif diff --git a/bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMM050_driver/bmm050_support.c b/bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMM050_driver/bmm050_support.c new file mode 100644 index 0000000000000000000000000000000000000000..53d701df8db74b4d39adeb99c2244a0048ce49f2 --- /dev/null +++ b/bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMM050_driver/bmm050_support.c @@ -0,0 +1,443 @@ +/* +**************************************************************************** +* Copyright (C) 2015 - 2016 Bosch Sensortec GmbH +* +* bmm050_support.c +* Date: 2016/03/17 +* Revision: 1.0.6 $ +* +* Usage: Sensor Driver support file for BMM050 and BMM150 sensor +* +**************************************************************************** +* License: +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* Neither the name of the copyright holder nor the names of the +* contributors may be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDER +* OR CONTRIBUTORS BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, +* OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT NOT LIMITED TO, +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* The information provided is believed to be accurate and reliable. +* The copyright holder assumes no responsibility +* for the consequences of use +* of such information nor for any infringement of patents or +* other rights of third parties which may result from its use. +* No license is granted by implication or otherwise under any patent or +* patent rights of the copyright holder. +**************************************************************************/ + +/*---------------------------------------------------------------------------*/ +/* Includes*/ +/*---------------------------------------------------------------------------*/ +#include "bmm050.h" + +/*----------------------------------------------------------------------------*/ +/* The following functions are used for reading and writing of + * sensor data using I2C or SPI communication + *----------------------------------------------------------------------------*/ +#ifdef BMM050_API + /* \Brief: The function is used as I2C bus read + * \Return : Status of the I2C read + * \param dev_addr : The device address of the sensor + * \param reg_addr : Address of the first register, + * will data is going to be read + * \param reg_data : This data read from the sensor, + * which is hold in an array + * \param cnt : The no of byte of data to be read + */ + s8 BMM050_I2C_bus_read(u8 dev_addr, u8 reg_addr, u8 *reg_data, u8 cnt); + /* \Brief: The function is used as I2C bus write + * \Return : Status of the I2C write + * \param dev_addr : The device address of the sensor + * \param reg_addr : Address of the first register, + * will data is going to be written + * \param reg_data : It is a value hold in the array, + * will be used for write the value into the register + * \param cnt : The no of byte of data to be write + */ + s8 BMM050_I2C_bus_write(u8 dev_addr, u8 reg_addr, u8 *reg_data, u8 cnt); + /* \Brief: The function is used as SPI bus write + * \Return : Status of the SPI write + * \param dev_addr : The device address of the sensor + * \param reg_addr : Address of the first register, + * will data is going to be written + * \param reg_data : It is a value hold in the array, + * will be used for write the value into the register + * \param cnt : The no of byte of data to be write + */ + s8 BMM050_SPI_bus_write(u8 dev_addr, u8 reg_addr, u8 *reg_data, u8 cnt); + /* \Brief: The function is used as SPI bus read + * \Return : Status of the SPI read + * \param dev_addr : The device address of the sensor + * \param reg_addr : Address of the first register, + * will data is going to be read + * \param reg_data : This data read from the sensor, + * which is hold in an array + * \param cnt : The no of byte of data to be read + */ + s8 BMM050_SPI_bus_read(u8 dev_addr, u8 reg_addr, u8 *reg_data, u8 cnt); + /* + * \Brief: SPI/I2C init routine + */ + s8 I2C_routine(void); + s8 SPI_routine(void); +#endif +/********************End of I2C/SPI function declarations*********************/ +/* Brief : The delay routine + * \param : delay in ms +*/ +void BMM050_delay_msek(u32 msek); +/* This function is an example for reading sensor data + * \param: None + * \return: communication result + */ +s32 bmm050_data_readout_template(void); +/*----------------------------------------------------------------------------* + * struct bmm050_t parameters can be accessed by using bmm050 + * bmm050_t having the following parameters + * Bus write function pointer: BMM050_WR_FUNC_PTR + * Bus read function pointer: BMM050_RD_FUNC_PTR + * Burst read function pointer: BMM050_BRD_FUNC_PTR + * Delay function pointer: delay_msec + * I2C address: dev_addr + * Chip id of the sensor: chip_id + *---------------------------------------------------------------------------*/ +struct bmm050_t bmm050; +/*---------------------------------------------------------------------------*/ +/* This function is an example for reading sensor data + * \param: None + * \return: communication result + */ +s32 bmm050_data_readout_template(void) +{ + /* Structure used for read the mag xyz data*/ + struct bmm050_mag_data_s16_t data; + /* Structure used for read the mag xyz data with 32 bit output*/ + struct bmm050_mag_s32_data_t data_s32; + /* Structure used for read the mag xyz data with float output*/ + struct bmm050_mag_data_float_t data_float; + /* Variable used to get the data rate*/ + u8 v_data_rate_u8 = BMM050_INIT_VALUE; + /* Variable used to set the data rate*/ + u8 v_data_rate_value_u8 = BMM050_INIT_VALUE; + /* result of communication results*/ + s32 com_rslt = ERROR; + + /*---------------------------------------------------------------------------* + *********************** START INITIALIZATION ************************ + *--------------------------------------------------------------------------*/ + /* Based on the user need configure I2C or SPI interface. + * It is sample code to explain how to use the bmm050 API*/ +#ifdef BMM050_API + I2C_routine(); + /*SPI_routine(); */ +#endif + /*--------------------------------------------------------------------------* + * This function used to assign the value/reference of + * the following parameters + * I2C address + * Bus Write + * Bus read + * company_id + *-------------------------------------------------------------------------*/ + com_rslt = bmm050_init(&bmm050); + + /* For initialization it is required to set the mode of + * the sensor as "NORMAL" + * but before set the mode needs to configure the power control bit + * in the register 0x4B bit BMM050_INIT_VALUE should be enabled + * This bit is enabled by calling bmm050_init function + * For the Normal data acquisition/read/write is possible in this mode + * by using the below API able to set the power mode as NORMAL*/ + /* Set the power mode as NORMAL*/ + com_rslt += bmm050_set_functional_state(BMM050_NORMAL_MODE); + /*--------------------------------------------------------------------------* + ************************* END INITIALIZATION ************************* + *---------------------------------------------------------------------------*/ + + /*------------------------------------------------------------------------* + ************************* START GET and SET FUNCTIONS DATA **************** + *---------------------------------------------------------------------------*/ + /* This API used to Write the data rate of the sensor, input + value have to be given + data rate value set from the register 0x4C bit 3 to 5*/ + v_data_rate_value_u8 = BMM050_DATA_RATE_30HZ;/* set data rate of 30Hz*/ + com_rslt += bmm050_set_data_rate(v_data_rate_value_u8); + + /* This API used to read back the written value of data rate*/ + com_rslt += bmm050_get_data_rate(&v_data_rate_u8); + /*-----------------------------------------------------------------* + ************************* END GET and SET FUNCTIONS **************** + *-------------------------------------------------------------------*/ + /*------------------------------------------------------------------* + ************************* START READ SENSOR DATA(X,Y and Z axis) ******** + *------------------------------------------------------------------*/ + /* accessing the bmm050_mdata parameter by using data*/ + /* Reads the mag x y z data*/ + com_rslt += bmm050_read_mag_data_XYZ(&data); + + + /* accessing the bmm050_mdata_float parameter by using data_float*/ + /* Reads mag xyz data output as 32bit value*/ + com_rslt += bmm050_read_mag_data_XYZ_float(&data_float); + + /* accessing the bmm050_mdata_s32 parameter by using data_s32*/ + /* Reads mag xyz data output as float value*/ + com_rslt += bmm050_read_mag_data_XYZ_s32(&data_s32); + + /*--------------------------------------------------------------------* + ************************* END READ SENSOR DATA(X,Y and Z axis) ************ + *-------------------------------------------------------------------------*/ + /*-----------------------------------------------------------------------* + ************************* START DE-INITIALIZATION *********************** + *-------------------------------------------------------------------------*/ + /* For de-initialization it is required to set the mode of + * the sensor as "SUSPEND" + * the SUSPEND mode set from the register 0x4B bit BMM050_INIT_VALUE + * should be disabled + * by using the below API able to set the power mode as SUSPEND*/ + /* Set the power mode as SUSPEND*/ + com_rslt += bmm050_set_functional_state(BMM050_SUSPEND_MODE); + /*---------------------------------------------------------------------* + ************************* END DE-INITIALIZATION ********************** + *---------------------------------------------------------------------*/ + return com_rslt; +} + +#ifdef BMM050_API +/*--------------------------------------------------------------------------*/ +/* The following function is used to map the I2C bus read, write, delay and + * device address with global structure bmm050 + *-------------------------------------------------------------------------*/ +s8 I2C_routine(void) +{ + /*--------------------------------------------------------------------------*/ + /* By using bmm050 the following structure parameter can be accessed + * Bus write function pointer: BMM050_WR_FUNC_PTR + * Bus read function pointer: BMM050_RD_FUNC_PTR + * Delay function pointer: delay_msec + * I2C address: dev_addr + *--------------------------------------------------------------------------*/ + bmm050.bus_write = BMM050_I2C_bus_write; + bmm050.bus_read = BMM050_I2C_bus_read; + bmm050.delay_msec = BMM050_delay_msek; + bmm050.dev_addr = BMM050_I2C_ADDRESS; + + return BMM050_INIT_VALUE; +} + +/*---------------------------------------------------------------------------*/ +/* The following function is used to map the SPI bus read, write and delay + * with global structure bmm050 + *--------------------------------------------------------------------------*/ +s8 SPI_routine(void) +{ + /*--------------------------------------------------------------------------* + * By using bmm050 the following structure parameter can be accessed + * Bus write function pointer: BMM050_WR_FUNC_PTR + * Bus read function pointer: BMM050_RD_FUNC_PTR + * Delay function pointer: delay_msec + *--------------------------------------------------------------------------*/ + + bmm050.bus_write = BMM050_SPI_bus_write; + bmm050.bus_read = BMM050_SPI_bus_read; + bmm050.delay_msec = BMM050_delay_msek; + + return BMM050_INIT_VALUE; +} + +/************** SPI/I2C buffer length ******/ +#define I2C_BUFFER_LEN 8 +#define SPI_BUFFER_LEN 5 +#define MASK_DATA1 0xFF +#define MASK_DATA2 0x80 +#define MASK_DATA3 0x7F +#define C_BMM050_ONE_U8X (1) +#define C_BMM050_TWO_U8X (2) + +/*-------------------------------------------------------------------* +* +* This is a sample code for read and write the data by using I2C/SPI +* Use either I2C or SPI based on your need +* The device address defined in the bmm050.h file +* +*-----------------------------------------------------------------------*/ +/* \Brief: The function is used as I2C bus write +* \Return : Status of the I2C write +* \param dev_addr : The device address of the sensor +* \param reg_addr : Address of the first register, +* will data is going to be written +* \param reg_data : It is a value hold in the array, +* will be used for write the value into the register +* \param cnt : The no of byte of data to be write +*/ +s8 BMM050_I2C_bus_write(u8 dev_addr, u8 reg_addr, u8 *reg_data, u8 cnt) +{ + s32 iError = BMM050_INIT_VALUE; + u8 array[I2C_BUFFER_LEN]; + u8 stringpos = BMM050_INIT_VALUE; + + array[BMM050_INIT_VALUE] = reg_addr; + for (stringpos = BMM050_INIT_VALUE; stringpos < cnt; stringpos++) + array[stringpos + C_BMM050_ONE_U8X] = *(reg_data + stringpos); + /* + * Please take the below function as your reference for + * write the data using I2C communication + * "IERROR = I2C_WRITE_STRING(DEV_ADDR, ARRAY, CNT+C_BMM050_ONE_U8X)" + * add your I2C write function here + * iError is an return value of I2C read function + * Please select your valid return value + * In the driver SUCCESS defined as BMM050_INIT_VALUE + * and FAILURE defined as -C_BMM050_ONE_U8X + * Note : + * This is a full duplex operation, + * The first read data is discarded, for that extra write operation + * have to be initiated. For that cnt+C_BMM050_ONE_U8X operation done + * in the I2C write string function + * For more information please refer data sheet SPI communication: + */ + return (s8)iError; +} + +/* \Brief: The function is used as I2C bus read +* \Return : Status of the I2C read +* \param dev_addr : The device address of the sensor +* \param reg_addr : Address of the first register, +* will data is going to be read +* \param reg_data : This data read from the sensor, +* which is hold in an array +* \param cnt : The no of byte of data to be read +*/ +s8 BMM050_I2C_bus_read(u8 dev_addr, u8 reg_addr, u8 *reg_data, u8 cnt) +{ + s32 iError = BMM050_INIT_VALUE; + u8 array[I2C_BUFFER_LEN] = {BMM050_INIT_VALUE}; + u8 stringpos = BMM050_INIT_VALUE; + + array[BMM050_INIT_VALUE] = reg_addr; + /* Please take the below function as your reference + * for read the data using I2C communication + * add your I2C rad function here. + * "IERROR = I2C_WRITE_READ_STRING( + * DEV_ADDR, ARRAY, ARRAY, C_BMM050_ONE_U8X, CNT)" + * iError is an return value of SPI write function + * Please select your valid return value + * In the driver SUCCESS defined as BMM050_INIT_VALUE + * and FAILURE defined as -C_BMM050_ONE_U8X + */ + for (stringpos = BMM050_INIT_VALUE; stringpos < cnt; stringpos++) + *(reg_data + stringpos) = array[stringpos]; + + return (s8)iError; +} + +/* \Brief: The function is used as SPI bus read + * \Return : Status of the SPI read + * \param dev_addr : The device address of the sensor + * \param reg_addr : Address of the first register, + * will data is going to be read + * \param reg_data : This data read from the sensor, + * which is hold in an array + * \param cnt : The no of byte of data to be read + */ +s8 BMM050_SPI_bus_read(u8 dev_addr, u8 reg_addr, u8 *reg_data, u8 cnt) +{ + s32 iError = BMM050_INIT_VALUE; + u8 array[SPI_BUFFER_LEN] = {MASK_DATA1}; + u8 stringpos; + /* For the SPI mode only 7 bits of register addresses are used. + The MSB of register address is declared the bit what functionality it is + read/write (read as C_BMM050_ONE_U8X/write as BMM050_INIT_VALUE)*/ + /*read routine is initiated register address is mask with 0x80*/ + array[BMM050_INIT_VALUE] = reg_addr | MASK_DATA2; + /* + * Please take the below function as your reference for + * read the data using SPI communication + * " IERROR = SPI_READ_WRITE_STRING(ARRAY, ARRAY, CNT+C_BMM050_ONE_U8X)" + * add your SPI read function here + * iError is an return value of SPI read function + * Please select your valid return value + * In the driver SUCCESS defined as BMM050_INIT_VALUE + * and FAILURE defined as -1 + * Note : + * This is a full duplex operation, + * The first read data is discarded, for that extra write operation + * have to be initiated. For that cnt+C_BMM050_ONE_U8X operation done + * in the SPI read + * and write string function + * For more information please refer data sheet SPI communication: + */ + for (stringpos = BMM050_INIT_VALUE; stringpos < cnt; stringpos++) + *(reg_data + stringpos) = array[stringpos + C_BMM050_ONE_U8X]; + + return (s8)iError; +} + +/* \Brief: The function is used as SPI bus write + * \Return : Status of the SPI write + * \param dev_addr : The device address of the sensor + * \param reg_addr : Address of the first register, + * will data is going to be written + * \param reg_data : It is a value hold in the array, + * will be used for write the value into the register + * \param cnt : The no of byte of data to be write + */ +s8 BMM050_SPI_bus_write(u8 dev_addr, u8 reg_addr, u8 *reg_data, u8 cnt) +{ + s32 iError = BMM050_INIT_VALUE; + u8 array[SPI_BUFFER_LEN * C_BMM050_TWO_U8X]; + u8 stringpos = BMM050_INIT_VALUE; + + for (stringpos = BMM050_INIT_VALUE; stringpos < cnt; stringpos++) + { + /* the operation of (reg_addr++)&0x7F done: because it ensure + the BMM050_INIT_VALUE and C_BMM050_ONE_U8X of the given value + It is done only for 8bit operation*/ + array[stringpos * C_BMM050_TWO_U8X] = (reg_addr++) & MASK_DATA3; + array[stringpos * C_BMM050_TWO_U8X + C_BMM050_ONE_U8X] = + *(reg_data + stringpos); + } + /* Please take the below function as your reference + * for write the data using SPI communication + * add your SPI write function here. + * "IERROR = SPI_WRITE_STRING(ARRAY, CNT*C_BMM050_TWO_U8X)" + * iError is an return value of SPI write function + * Please select your valid return value + * In the driver SUCCESS defined as BMM050_INIT_VALUE + * and FAILURE defined as -1 + */ + return (s8)iError; +} + +/* Brief : The delay routine + * \param : delay in ms +*/ +void BMM050_delay_msek(u32 msek) +{ + /*Here you can write your own delay routine*/ +} +#endif diff --git a/bsp/nuvoton/libraries/nu_packages/BMX055/sensor_bmx055.c b/bsp/nuvoton/libraries/nu_packages/BMX055/sensor_bmx055.c new file mode 100644 index 0000000000000000000000000000000000000000..84b4e0fe76a4245e928955797ae402e2807681bf --- /dev/null +++ b/bsp/nuvoton/libraries/nu_packages/BMX055/sensor_bmx055.c @@ -0,0 +1,656 @@ +/**************************************************************************//** +* +* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-1-16 Wayne First version +* +******************************************************************************/ + +#include + +#if defined(NU_PKG_USING_BMX055) + +#include +#include "sensor_bmx055.h" + +#define DBG_ENABLE +#define DBG_LEVEL DBG_LOG +#define DBG_SECTION_NAME "sensor.bmx055" +#define DBG_COLOR +#include + +struct bmx055 +{ + /* Structure used for Magnetometer */ + struct bmm050_t mag; + + /* Structure used for read the mag xyz data*/ + struct bmm050_mag_data_s16_t mag_data; + + /* Structure used for Accelerometer */ + struct bma2x2_t accel; + + /* Structure used to read accel xyz and temperature data*/ + struct bma2x2_accel_data_temp accel_xyzt; + + /* Structure used for Gyroscope */ + struct bmg160_t gyro; + + /* structure used to read gyro xyz and interrupt status*/ + struct bmg160_data_t gyro_xyzi; + +} ; +typedef struct bmx055 *bmx055_t; + +struct bmx055_param_pair +{ + int val; + int reg; +}; +typedef struct bmx055_param_pair *bmx055_param_pair_t; + +static const struct bmx055_param_pair accel_ranges[] = +{ + {2000, BMA2x2_RANGE_2G}, + {4000, BMA2x2_RANGE_4G}, + {8000, BMA2x2_RANGE_8G}, + {16000, BMA2x2_RANGE_16G}, +}; + +static const struct bmx055_param_pair gyro_ranges[] = +{ + {125, BMG160_RANGE_125}, + {250, BMG160_RANGE_250}, + {500, BMG160_RANGE_500}, + {1000, BMG160_RANGE_1000}, + {2000, BMG160_RANGE_2000}, +}; + +static const struct bmx055_param_pair accel_odr[] = +{ + {8, BMA2x2_BW_7_81HZ}, + {16, BMA2x2_BW_15_63HZ}, + {32, BMA2x2_BW_31_25HZ}, + {63, BMA2x2_BW_62_50HZ}, + {125, BMA2x2_BW_125HZ}, + {250, BMA2x2_BW_250HZ}, + {500, BMA2x2_BW_500HZ}, + {1000, BMA2x2_BW_1000HZ}, +}; + +static const struct bmx055_param_pair gyro_odr[] = +{ + {12, BMG160_BW_12_HZ}, + {23, BMG160_BW_23_HZ}, + {32, BMG160_BW_32_HZ}, + {47, BMG160_BW_47_HZ}, + {64, BMG160_BW_64_HZ}, + {116, BMG160_BW_116_HZ}, + {230, BMG160_BW_230_HZ}, + {500, BMG160_BW_500_HZ}, +}; + +static const struct bmx055_param_pair mag_odr[] = +{ + {2, BMM050_DR_02HZ}, + {6, BMM050_DR_06HZ}, + {8, BMM050_DR_08HZ}, + {15, BMM050_DR_15HZ}, + {20, BMM050_DR_20HZ}, + {25, BMM050_DR_25HZ}, + {30, BMM050_DR_30HZ}, +}; + +static struct bmx055 g_sbmx055; +static struct rt_i2c_bus_device *i2c_bus_dev; +static uint8_t g_u8Range_accel = 0; +static uint8_t g_u8Range_gyro = 0; + +static int8_t bmx055_i2c_write_reg(uint8_t dev_id, uint8_t reg_addr, uint8_t *reg_data, uint8_t len) +{ + struct rt_i2c_msg msgs[2]; + + msgs[0].addr = dev_id; /* Slave address */ + msgs[0].flags = RT_I2C_WR; /* Write flag */ + msgs[0].buf = (rt_uint8_t *)®_addr; /* Slave register address */ + msgs[0].len = 1; /* Number of bytes sent */ + + msgs[1].addr = dev_id; /* Slave address */ + msgs[1].flags = RT_I2C_WR | RT_I2C_NO_START; /* Read flag without NO_START */ + msgs[1].buf = (rt_uint8_t *)reg_data; /* Read data pointer */ + msgs[1].len = len; /* Number of bytes read */ + + if (rt_i2c_transfer(i2c_bus_dev, &msgs[0], 2) != 2) + { + return -RT_ERROR; + } + + return RT_EOK; +} + +static int8_t bmx055_i2c_read_reg(uint8_t dev_id, uint8_t reg_addr, uint8_t *reg_data, uint8_t len) +{ + struct rt_i2c_msg msgs[3]; + + msgs[0].addr = dev_id; /* Slave address */ + msgs[0].flags = RT_I2C_WR; /* Write flag */ + msgs[0].buf = (rt_uint8_t *)®_addr; /* Slave register address */ + msgs[0].len = 1; /* Number of bytes sent */ + + + msgs[1].addr = dev_id; /* Slave address */ + msgs[1].flags = RT_I2C_RD ; /* Read flag */ + msgs[1].buf = (rt_uint8_t *)®_data[0]; /* Read data pointer */ + msgs[1].len = len; + + if (rt_i2c_transfer(i2c_bus_dev, &msgs[0], 2) != 2) + { + return -RT_ERROR; + } + + return RT_EOK; +} + +void bmx055_delay_ms(BMM050_MDELAY_DATA_TYPE ms) +{ + rt_thread_mdelay(ms); +} + +static int8_t bmx055_init_mag(struct bmm050_t *mag) +{ + int8_t com_rslt = 0; + u8 v_data_rate_u8 = BMM050_INIT_VALUE; + + mag->dev_addr = BMM050_I2C_ADDRESS; + mag->bus_write = bmx055_i2c_write_reg; + mag->bus_read = bmx055_i2c_read_reg; + mag->delay_msec = bmx055_delay_ms; + + com_rslt = bmm050_init(mag); + com_rslt += bmm050_set_functional_state(BMM050_NORMAL_MODE); + com_rslt += bmm050_set_data_rate(BMM050_DATA_RATE_30HZ); + com_rslt += bmm050_get_data_rate(&v_data_rate_u8); + + return com_rslt; +} + +static int8_t bmx055_init_accel(struct bma2x2_t *accel) +{ + int8_t com_rslt = 0; + uint8_t bandwidth = 0x08; // bandwidth of 7.81Hz + + accel->dev_addr = BMA2x2_I2C_ADDR1; + accel->bus_write = bmx055_i2c_write_reg; + accel->bus_read = bmx055_i2c_read_reg; + accel->delay_msec = bmx055_delay_ms; + + com_rslt = bma2x2_init(accel); + com_rslt += bma2x2_set_power_mode(BMA2x2_MODE_NORMAL); + com_rslt += bma2x2_set_bw(bandwidth); + com_rslt += bma2x2_get_range(&g_u8Range_accel); + + return com_rslt; +} + +static int8_t bmx055_init_gyro(struct bmg160_t *gyro) +{ + int8_t com_rslt = 0; + + gyro->dev_addr = BMG160_I2C_ADDR1; + gyro->bus_write = bmx055_i2c_write_reg; + gyro->bus_read = bmx055_i2c_read_reg; + gyro->delay_msec = bmx055_delay_ms; + + com_rslt = bmg160_init(gyro); + com_rslt += bmg160_set_power_mode(BMG160_MODE_NORMAL); + com_rslt += bmg160_set_bw(C_BMG160_BW_230HZ_U8X); + com_rslt += bmg160_get_range_reg(&g_u8Range_gyro); + + return com_rslt; +} + +static double get_mg_value(int32_t i32AccelVal) +{ + switch (g_u8Range_accel) + { + case BMA2x2_RANGE_2G: + return (double)i32AccelVal * 0.98; //res: 0.98, + case BMA2x2_RANGE_4G: + return (double)i32AccelVal * 1.95; + case BMA2x2_RANGE_8G: + return (double)i32AccelVal * 3.91; + case BMA2x2_RANGE_16G: + return (double)i32AccelVal * 7.81; + } + return 0.0f; +} + +static double get_mdps_value(int32_t i32AccelVal) +{ + switch (g_u8Range_gyro) + { + case BMG160_RANGE_125: + return (double)i32AccelVal * 3.8; + case BMG160_RANGE_250: + return (double)i32AccelVal * 7.6; + case BMG160_RANGE_500: + return (double)i32AccelVal * 15.3; + case BMG160_RANGE_1000: + return (double)i32AccelVal * 30.5; + case BMG160_RANGE_2000: + return (double)i32AccelVal * 61; + } + return 0.0f; +} + +static rt_size_t bmx055_fetch_data(rt_sensor_t sensor, void *buf, rt_size_t len) +{ + struct rt_sensor_data *data = (struct rt_sensor_data *)buf; + switch (sensor->info.type) + { + case RT_SENSOR_CLASS_ACCE: + bma2x2_read_accel_xyzt(&g_sbmx055.accel_xyzt); + data->type = RT_SENSOR_CLASS_ACCE; + + /* Report mg */ + data->data.acce.x = (int32_t)get_mg_value(g_sbmx055.accel_xyzt.x); + data->data.acce.y = (int32_t)get_mg_value(g_sbmx055.accel_xyzt.y); + data->data.acce.z = (int32_t)get_mg_value(g_sbmx055.accel_xyzt.z); + break; + + case RT_SENSOR_CLASS_GYRO: + bmg160_get_data_XYZI(&g_sbmx055.gyro_xyzi); + data->type = RT_SENSOR_CLASS_GYRO; + + /* Report mdps */ + data->data.gyro.x = (int32_t)get_mdps_value(g_sbmx055.gyro_xyzi.datax); + data->data.gyro.y = (int32_t)get_mdps_value(g_sbmx055.gyro_xyzi.datay); + data->data.gyro.z = (int32_t)get_mdps_value(g_sbmx055.gyro_xyzi.dataz); + break; + + case RT_SENSOR_CLASS_MAG: + bmm050_read_mag_data_XYZ(&g_sbmx055.mag_data); + data->type = RT_SENSOR_CLASS_MAG; + + /* Report mquass */ + data->data.mag.x = g_sbmx055.mag_data.datax; + data->data.mag.y = g_sbmx055.mag_data.datay; + data->data.mag.z = g_sbmx055.mag_data.dataz; + break; + + default: + return 0; + } + data->timestamp = rt_sensor_get_ts(); + return 1; +} + +static int find_param_index(const int eng_val, const struct bmx055_param_pair *pairs, const int size) +{ + int i = 0; + + while (i < size) + { + if (eng_val <= pairs[i].val) + return i; + i++; + } + return i - 1; +} + +static rt_err_t bmx055_getid(rt_sensor_t sensor, rt_uint8_t *pu8) +{ + switch (sensor->info.type) + { + case RT_SENSOR_CLASS_ACCE: + *pu8 = g_sbmx055.accel.chip_id; + break; + + case RT_SENSOR_CLASS_GYRO: + *pu8 = g_sbmx055.gyro.chip_id; + break; + + case RT_SENSOR_CLASS_MAG: + *pu8 = g_sbmx055.mag.company_id; + break; + } + return -RT_EINVAL; +} + + +static rt_err_t bmx055_set_power(rt_sensor_t sensor, rt_uint8_t power_mode) +{ + uint8_t power_ctr; + + switch (sensor->info.type) + { + case RT_SENSOR_CLASS_ACCE: + { + switch (power_mode) + { + case RT_SENSOR_POWER_DOWN: + power_ctr = BMA2x2_MODE_STANDBY; + break; + + case RT_SENSOR_POWER_NORMAL: + power_ctr = BMA2x2_MODE_NORMAL; + break; + + case RT_SENSOR_POWER_LOW: + power_ctr = BMA2x2_MODE_LOWPOWER1; + break; + + default: + return -RT_EINVAL; + } + + if (bma2x2_set_power_mode(power_ctr) != 0) + goto exit_bmx055_set_power; + + } + break; + + case RT_SENSOR_CLASS_GYRO: + { + switch (power_mode) + { + case RT_SENSOR_POWER_DOWN: + power_ctr = BMG160_MODE_DEEPSUSPEND; + break; + + case RT_SENSOR_POWER_NORMAL: + power_ctr = BMG160_MODE_NORMAL; + break; + + default: + return -RT_EINVAL; + } + + if (bmg160_set_power_mode(power_ctr) != 0) + goto exit_bmx055_set_power; + + } + break; + + case RT_SENSOR_CLASS_MAG: + { + switch (power_mode) + { + case RT_SENSOR_POWER_DOWN: + power_ctr = 0; + break; + + case RT_SENSOR_POWER_NORMAL: + power_ctr = 1; + break; + + default: + return -RT_EINVAL; + } + if (bmm050_set_power_mode(power_ctr) != 0) + goto exit_bmx055_set_power; + } + break; + + default: + return -RT_EINVAL; + } + +exit_bmx055_set_power: + + return -RT_ERROR; +} + +static rt_err_t bmx055_set_range(rt_sensor_t sensor, rt_uint16_t range) +{ + int idx; + + switch (sensor->info.type) + { + case RT_SENSOR_CLASS_ACCE: + { + idx = find_param_index(range, accel_ranges, sizeof(accel_ranges)); + if (bma2x2_set_range(accel_ranges[idx].reg) != 0) + goto exit_bmx055_set_range; + else if (bma2x2_get_range(&g_u8Range_accel) != 0) + goto exit_bmx055_set_range; + } + break; + + case RT_SENSOR_CLASS_GYRO: + { + idx = find_param_index(range, gyro_ranges, sizeof(gyro_ranges)); + if (bmg160_set_range_reg(gyro_ranges[idx].reg) != 0) + goto exit_bmx055_set_range; + else if (bmg160_get_range_reg(&g_u8Range_gyro) != 0) + goto exit_bmx055_set_range; + } + break; + + default: + return -RT_EINVAL; + } + +exit_bmx055_set_range: + + return -RT_ERROR; +} + +static rt_err_t bmx055_set_odr(rt_sensor_t sensor, rt_uint16_t odr_hz) +{ + int idx; + switch (sensor->info.type) + { + case RT_SENSOR_CLASS_ACCE: + { + idx = find_param_index(odr_hz, accel_odr, sizeof(accel_odr)); + if (bma2x2_set_bw(accel_odr[idx].reg) != 0) + goto exit_bmx055_set_power; + } + break; + + case RT_SENSOR_CLASS_GYRO: + { + idx = find_param_index(odr_hz, gyro_odr, sizeof(gyro_odr)); + if (bmg160_set_bw(gyro_odr[idx].reg) != 0) + goto exit_bmx055_set_power; + } + break; + + case RT_SENSOR_CLASS_MAG: + { + idx = find_param_index(odr_hz, mag_odr, sizeof(mag_odr)); + if (bmm050_set_data_rate(mag_odr[idx].reg) != 0) + goto exit_bmx055_set_power; + } + break; + + default: + return -RT_EINVAL; + } + + return RT_EOK; + +exit_bmx055_set_power: + + return -RT_ERROR; +} + +static rt_err_t bmx055_control(rt_sensor_t sensor, int cmd, void *args) +{ + RT_ASSERT(sensor != RT_NULL); + RT_ASSERT(args != RT_NULL); + + switch (cmd) + { + case RT_SENSOR_CTRL_GET_ID: + { + rt_uint8_t *pu8id = (rt_uint8_t *)args; + return bmx055_getid(sensor, pu8id); + } + case RT_SENSOR_CTRL_SET_RANGE: + return bmx055_set_range(sensor, (rt_uint32_t)args); + + case RT_SENSOR_CTRL_SET_POWER: + return bmx055_set_power(sensor, ((rt_uint32_t)args & 0xff)); + + case RT_SENSOR_CTRL_SET_ODR: + return bmx055_set_odr(sensor, ((rt_uint32_t)args & 0xff)); + + } + return -RT_EINVAL; +} + +static struct rt_sensor_ops sensor_ops = +{ + bmx055_fetch_data, + bmx055_control +}; + +static int rt_hw_bmx055_accel_init(const char *name, struct rt_sensor_config *cfg) +{ + rt_int8_t result; + rt_sensor_t sensor = RT_NULL; + + sensor = rt_calloc(1, sizeof(struct rt_sensor_device)); + if (sensor == RT_NULL) + return -(RT_ENOMEM); + + sensor->info.type = RT_SENSOR_CLASS_ACCE; + sensor->info.vendor = RT_SENSOR_VENDOR_BOSCH; + sensor->info.model = "bmx055_acce"; + sensor->info.unit = RT_SENSOR_UNIT_MG; + sensor->info.intf_type = RT_SENSOR_INTF_I2C; + sensor->info.range_max = 16000; + sensor->info.range_min = 2000; + sensor->info.period_min = 100; + + rt_memcpy(&sensor->config, cfg, sizeof(struct rt_sensor_config)); + sensor->ops = &sensor_ops; + + result = rt_hw_sensor_register(sensor, name, RT_DEVICE_FLAG_RDWR, RT_NULL); + if (result != RT_EOK) + { + LOG_E("device register: %d", result); + rt_free(sensor); + return -RT_ERROR; + } + return RT_EOK; +} + +static int rt_hw_bmx055_gyro_init(const char *name, struct rt_sensor_config *cfg) +{ + rt_int8_t result; + rt_sensor_t sensor = RT_NULL; + + sensor = rt_calloc(1, sizeof(struct rt_sensor_device)); + if (sensor == RT_NULL) + return -(RT_ENOMEM); + + sensor->info.type = RT_SENSOR_CLASS_GYRO; + sensor->info.vendor = RT_SENSOR_VENDOR_BOSCH; + sensor->info.model = "bmx055_gyro"; + sensor->info.unit = RT_SENSOR_UNIT_MDPS; + sensor->info.intf_type = RT_SENSOR_INTF_I2C; + sensor->info.range_max = 2000; + sensor->info.range_min = 125; + sensor->info.period_min = 100; + + rt_memcpy(&sensor->config, cfg, sizeof(struct rt_sensor_config)); + sensor->ops = &sensor_ops; + + result = rt_hw_sensor_register(sensor, name, RT_DEVICE_FLAG_RDWR, RT_NULL); + if (result != RT_EOK) + { + LOG_E("device register: %d", result); + rt_free(sensor); + return -RT_ERROR; + } + return RT_EOK; +} + +static int rt_hw_bmx055_mag_init(const char *name, struct rt_sensor_config *cfg) +{ + rt_int8_t result; + rt_sensor_t sensor = RT_NULL; + + sensor = rt_calloc(1, sizeof(struct rt_sensor_device)); + if (sensor == RT_NULL) + return -(RT_ENOMEM); + + sensor->info.type = RT_SENSOR_CLASS_MAG; + sensor->info.vendor = RT_SENSOR_VENDOR_BOSCH; + sensor->info.model = "bmx055_mag"; + sensor->info.unit = RT_SENSOR_UNIT_MGAUSS; + sensor->info.intf_type = RT_SENSOR_INTF_I2C; + sensor->info.range_max = 25000; // 1uT = 10*mGauss, X/Y: 1300uT=13000mGauss, Z: 2500uT=25000mG + sensor->info.range_min = 0; + sensor->info.period_min = 100; + + rt_memcpy(&sensor->config, cfg, sizeof(struct rt_sensor_config)); + sensor->ops = &sensor_ops; + + result = rt_hw_sensor_register(sensor, name, RT_DEVICE_FLAG_RDWR, RT_NULL); + if (result != RT_EOK) + { + LOG_E("device register: %d", result); + rt_free(sensor); + return -RT_ERROR; + } + return RT_EOK; +} + +int rt_hw_bmx055_init(const char *name, struct rt_sensor_config *cfg) +{ + struct rt_sensor_intf *intf; + rt_err_t ret = -RT_ERROR; + + RT_ASSERT(name != NULL); + RT_ASSERT(cfg != NULL); + + intf = &cfg->intf; + + /* Find I2C bus */ + i2c_bus_dev = (struct rt_i2c_bus_device *)rt_device_find(intf->dev_name); + if (i2c_bus_dev == RT_NULL) + { + LOG_E("Can't found I2C bus..!\n"); + goto exit_rt_hw_bmx055_init; + } + + if (bmx055_init_mag(&g_sbmx055.mag) != 0) + { + LOG_E("Init mag..!\n"); + } + else if ((ret = rt_hw_bmx055_mag_init(name, cfg)) != RT_EOK) + { + LOG_E("Register mag..!\n"); + } + + if (bmx055_init_accel(&g_sbmx055.accel) != 0) + { + LOG_E("Init accel..!\n"); + } + else if ((ret = rt_hw_bmx055_accel_init(name, cfg)) != RT_EOK) + { + LOG_E("Register accel..!\n"); + } + + if (bmx055_init_gyro(&g_sbmx055.gyro) != 0) + { + LOG_E("Init gyro..!\n"); + } + else if ((ret = rt_hw_bmx055_gyro_init(name, cfg)) != RT_EOK) + { + LOG_E("Register gyro..!\n"); + } + +exit_rt_hw_bmx055_init: + return ret; +} + +#endif //#if defined(NU_PKG_USING_BMX055) diff --git a/bsp/nuvoton/libraries/nu_packages/BMX055/sensor_bmx055.h b/bsp/nuvoton/libraries/nu_packages/BMX055/sensor_bmx055.h new file mode 100644 index 0000000000000000000000000000000000000000..39dbb6a29e3bfd37ba55b5d7f1f2ca6c74a993c9 --- /dev/null +++ b/bsp/nuvoton/libraries/nu_packages/BMX055/sensor_bmx055.h @@ -0,0 +1,23 @@ +/**************************************************************************//** +* +* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-1-16 Wayne First version +* +******************************************************************************/ + +#ifndef __SENSOR_BMX055_H__ +#define __SENSOR_BMX055_H__ + +#include "sensor.h" +#include "bma2x2.h" +#include "bmm050.h" +#include "bmg160.h" + +int rt_hw_bmx055_init(const char *name, struct rt_sensor_config *cfg); + +#endif /* __SENSOR_BMX055_H__ */ diff --git a/bsp/nuvoton/libraries/nu_packages/Demo/SConscript b/bsp/nuvoton/libraries/nu_packages/Demo/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..311e915a5786adc579b9b60ee914b5ebf251e8f8 --- /dev/null +++ b/bsp/nuvoton/libraries/nu_packages/Demo/SConscript @@ -0,0 +1,12 @@ +Import('RTT_ROOT') +from building import * +cwd = GetCurrentDir() +group = [] +if GetDepend('NU_PKG_USING_DEMO'): + src = Split(""" + usbd_hid_dance_mouse.c + """) + CPPPATH = [cwd] + group = DefineGroup('nu_pkgs_demo', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/nuvoton/libraries/nu_packages/Demo/usbd_hid_dance_mouse.c b/bsp/nuvoton/libraries/nu_packages/Demo/usbd_hid_dance_mouse.c new file mode 100644 index 0000000000000000000000000000000000000000..a144c85155bf3bbef23eff1a076c1328565e330a --- /dev/null +++ b/bsp/nuvoton/libraries/nu_packages/Demo/usbd_hid_dance_mouse.c @@ -0,0 +1,114 @@ +/**************************************************************************//** +* +* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-6-16 HPHuang First version +* +******************************************************************************/ + +#include + +#if defined(RT_USB_DEVICE_HID) && (defined(BSP_USING_USBD) || defined(BSP_USING_HSUSBD)) + +#include +#include + +#define DBG_SECTION_NAME "dancemouse" +#define DBG_LEVEL DBG_LOG +#include + +static struct rt_thread usb_thread; +ALIGN(RT_ALIGN_SIZE) +static char usb_thread_stack[512]; +static struct rt_semaphore tx_sem_complete; + +static rt_err_t event_hid_in(rt_device_t dev, void *buffer) +{ + rt_sem_release(&tx_sem_complete); + return RT_EOK; +} + +static void usb_thread_entry(void *parameter) +{ + int8_t i8MouseTable[] = { -16, -16, -16, 0, 16, 16, 16, 0}; + uint8_t u8MouseIdx = 0; + uint8_t u8MoveLen=0, u8MouseMode = 1; + uint8_t pu8Buf[4]; + + rt_device_t device = (rt_device_t)parameter; + + rt_sem_init(&tx_sem_complete, "tx_complete_sem_hid", 1, RT_IPC_FLAG_FIFO); + + rt_device_set_tx_complete(device, event_hid_in); + + LOG_I("Ready.\n"); + + while (1) + { + u8MouseMode ^= 1; + if (u8MouseMode) + { + if (u8MoveLen > 14) + { + /* Update new report data */ + pu8Buf[0] = 0x00; + pu8Buf[1] = i8MouseTable[u8MouseIdx & 0x07]; + pu8Buf[2] = i8MouseTable[(u8MouseIdx + 2) & 0x07]; + pu8Buf[3] = 0x00; + u8MouseIdx++; + u8MoveLen = 0; + } + } + else + { + pu8Buf[0] = pu8Buf[1] = pu8Buf[2] = pu8Buf[3] = 0; + } + + u8MoveLen++; + + if (rt_device_write(device, HID_REPORT_ID_MOUSE, pu8Buf, 4) == 0) + { + /* Sleep 200 Milli-seconds */ + rt_thread_mdelay(200); + } + else + { + /* Wait it done. */ + rt_sem_take(&tx_sem_complete, RT_WAITING_FOREVER); + } + + } // while(1) +} + +static int dance_mouse_init(void) +{ + int err = 0; + rt_device_t device = rt_device_find("hidd"); + + RT_ASSERT(device != RT_NULL); + + err = rt_device_open(device, RT_DEVICE_FLAG_WRONLY); + + if (err != RT_EOK) + { + LOG_E("open dev failed!\n"); + return -1; + } + + rt_thread_init(&usb_thread, + "hidd", + usb_thread_entry, device, + usb_thread_stack, sizeof(usb_thread_stack), + 10, 20); + + rt_thread_startup(&usb_thread); + + return 0; +} +INIT_APP_EXPORT(dance_mouse_init); + +#endif /* #if defined(RT_USB_DEVICE_HID) && (defined(BSP_USING_USBD) || defined(BSP_USING_HSUSBD)) */ diff --git a/bsp/nuvoton/libraries/nu_packages/ILI9341/SConscript b/bsp/nuvoton/libraries/nu_packages/ILI9341/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..cc4a5c38dd3164104d351e16cd3189e2cad2cdbb --- /dev/null +++ b/bsp/nuvoton/libraries/nu_packages/ILI9341/SConscript @@ -0,0 +1,22 @@ +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +group = [] + +src = Split(""" +lcd_ili9341.c +""") +CPPPATH = [cwd] + +if GetDepend('NU_PKG_USING_ILI9341_EBI'): + src += Glob('ili9341_ebi.c') + +if GetDepend('NU_PKG_USING_ILI9341_SPI'): + src += Glob('ili9341_spi.c') + +if GetDepend('NU_PKG_USING_ILI9341'): + group = DefineGroup('nu_pkgs_ili9341', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') + diff --git a/bsp/nuvoton/libraries/nu_packages/ILI9341/ili9341_ebi.c b/bsp/nuvoton/libraries/nu_packages/ILI9341/ili9341_ebi.c new file mode 100644 index 0000000000000000000000000000000000000000..440dd2b9547195eec25fab3475815d2a61cb7878 --- /dev/null +++ b/bsp/nuvoton/libraries/nu_packages/ILI9341/ili9341_ebi.c @@ -0,0 +1,97 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-1-16 Wayne First version +* +******************************************************************************/ + +#include + +#if defined(NU_PKG_USING_ILI9341_EBI) + +#include + +#define ILI9341_ADDR_CMD 0x0 +#define ILI9341_ADDR_DATA 0x0030000 + +#define ili9341_reg_write(u32RegAddr) (*((volatile unsigned short *)(g_uint32_ili9341_base+(ILI9341_ADDR_CMD))) = (u32RegAddr)) +#define ili9341_read_data() (*((volatile unsigned short *)(g_uint32_ili9341_base+(ILI9341_ADDR_DATA)))) +#define ili9341_write_data(u32Data) (*((volatile unsigned short *)(g_uint32_ili9341_base+(ILI9341_ADDR_DATA))) = (u32Data)) + +static rt_uint32_t g_uint32_ili9341_base = 0; + +void ili9341_send_cmd(rt_uint8_t cmd) +{ + CLR_RS; + ili9341_reg_write(cmd); + SET_RS; +} + +void ili9341_send_cmd_parameter(rt_uint8_t data) +{ + ili9341_write_data(data); +} + +void ili9341_send_pixel_data(rt_uint16_t color) +{ + ili9341_write_data(color); +} + +void ili9341_set_column(uint16_t StartCol, uint16_t EndCol) +{ + ili9341_send_cmd(0x2A); + ili9341_write_data((StartCol >> 8) & 0xFF); + ili9341_write_data(StartCol & 0xFF); + ili9341_write_data((EndCol >> 8) & 0xFF); + ili9341_write_data(EndCol & 0xFF); +} + +void ili9341_set_page(uint16_t StartPage, uint16_t EndPage) +{ + ili9341_send_cmd(0x2B); + ili9341_write_data((StartPage >> 8) & 0xFF); + ili9341_write_data(StartPage & 0xFF); + ili9341_write_data((EndPage >> 8) & 0xFF); + ili9341_write_data(EndPage & 0xFF); +} + +void ili9341_lcd_get_pixel(char *color, int x, int y) +{ + rt_uint16_t red = 0; + rt_uint16_t green = 0; + rt_uint16_t blue = 0; + + if (x >= XSIZE_PHYS || y >= YSIZE_PHYS) + { + *(rt_uint16_t *)color = 0; + return; + } + + ili9341_set_column(x, x); + ili9341_set_page(y, y); + ili9341_send_cmd(0x2E); + + ili9341_read_data(); // Dummy + red = ili9341_read_data(); // Red[4:0]@D15~D11 + blue = ili9341_read_data(); // Blue[4:0]@D15~D11 + green = ili9341_read_data(); // Green[5:0]@D15~D10 + + //BGR565: B in High byte, R in low byte + //*(rt_uint16_t *)color = (((blue >> 11) << 11) | ((green >> 10) << 5) | (red >> 11)); + + //RGB565: R in High byte, B in low byte + *(rt_uint16_t *)color = (((red >> 11) << 11) | ((green >> 10) << 5) | (blue >> 11)); +} + +rt_err_t rt_hw_lcd_ili9341_ebi_init(rt_uint32_t ili9341_base) +{ + g_uint32_ili9341_base = ili9341_base; + return RT_EOK; +} + +#endif /* if defined(NU_PKG_USING_ILI9341_EBI) */ diff --git a/bsp/nuvoton/libraries/nu_packages/ILI9341/ili9341_spi.c b/bsp/nuvoton/libraries/nu_packages/ILI9341/ili9341_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..f8bd8536ffbba6f919562c5b7245ccff91c268bf --- /dev/null +++ b/bsp/nuvoton/libraries/nu_packages/ILI9341/ili9341_spi.c @@ -0,0 +1,195 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-1-16 Wayne First version +* +******************************************************************************/ + +#include + +#if defined(NU_PKG_USING_ILI9341_SPI) + +#include +#include + +static struct rt_spi_device ili9341_spi_device; +static struct rt_spi_configuration ili9341_cfg = +{ + .mode = RT_SPI_MODE_0 | RT_SPI_MSB, + .data_width = 8, + .max_hz = 48000000, +}; + +static void ili9341_change_datawidth(int data_width) +{ + if (ili9341_cfg.data_width != data_width) + { + ili9341_cfg.data_width = data_width; + rt_spi_configure(&ili9341_spi_device, &ili9341_cfg); + } +} + +void ili9341_send_cmd(rt_uint8_t cmd) +{ + ili9341_change_datawidth(8); + CLR_RS; + rt_spi_transfer(&ili9341_spi_device, (const void *)&cmd, NULL, 1); + SET_RS; +} + +void ili9341_send_cmd_parameter(uint8_t data) +{ + ili9341_change_datawidth(8); + rt_spi_transfer(&ili9341_spi_device, (const void *)&data, NULL, 1); +} + +static void ili9341_write_data_16bit(uint16_t data) +{ + ili9341_change_datawidth(16); + rt_spi_transfer(&ili9341_spi_device, (const void *)&data, NULL, 2); +} + +void ili9341_send_pixel_data(rt_uint16_t color) +{ + ili9341_write_data_16bit(color); +} + +static rt_err_t ili9341_spi_send_then_recv(struct rt_spi_device *device, + const void *send_buf, + rt_size_t send_length, + void *recv_buf, + rt_size_t recv_length) +{ + rt_err_t result; + struct rt_spi_message message; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(device->bus != RT_NULL); + + ili9341_change_datawidth(8); + result = rt_mutex_take(&(device->bus->lock), RT_WAITING_FOREVER); + if (result == RT_EOK) + { + if (device->bus->owner != device) + { + /* not the same owner as current, re-configure SPI bus */ + result = device->bus->ops->configure(device, &device->config); + if (result == RT_EOK) + { + /* set SPI bus owner */ + device->bus->owner = device; + } + else + { + /* configure SPI bus failed */ + result = -RT_EIO; + goto __exit; + } + } + + /* send data */ + message.send_buf = send_buf; + message.recv_buf = RT_NULL; + message.length = send_length; + message.cs_take = 1; + message.cs_release = 0; + message.next = RT_NULL; + + CLR_RS; + result = device->bus->ops->xfer(device, &message); + SET_RS; + if (result == 0) + { + result = -RT_EIO; + goto __exit; + } + + /* recv data */ + message.send_buf = RT_NULL; + message.recv_buf = recv_buf; + message.length = recv_length; + message.cs_take = 0; + message.cs_release = 1; + message.next = RT_NULL; + + result = device->bus->ops->xfer(device, &message); + if (result == 0) + { + result = -RT_EIO; + goto __exit; + } + + result = RT_EOK; + } + else + { + return -RT_EIO; + } + +__exit: + + rt_mutex_release(&(device->bus->lock)); + return result; +} + +void ili9341_set_column(uint16_t StartCol, uint16_t EndCol) +{ + ili9341_send_cmd(0x2A); + ili9341_write_data_16bit(StartCol); + ili9341_write_data_16bit(EndCol); +} + +void ili9341_set_page(uint16_t StartPage, uint16_t EndPage) +{ + ili9341_send_cmd(0x2B); + ili9341_write_data_16bit(StartPage); + ili9341_write_data_16bit(EndPage); +} + +void ili9341_lcd_get_pixel(char *color, int x, int y) +{ + uint8_t cmd; + typedef union + { + rt_uint32_t rgbx; + struct + { + rt_uint8_t x; + rt_uint8_t r; + rt_uint8_t g; + rt_uint8_t b; + } S; + } ili9341_pixel; + ili9341_pixel bgrx; + + if (x >= XSIZE_PHYS || y >= YSIZE_PHYS) + { + *(rt_uint16_t *)color = 0; + return; + } + + ili9341_set_column(x, x); + ili9341_set_page(y, y); + + cmd = 0x2E; + ili9341_spi_send_then_recv(&ili9341_spi_device, &cmd, 1, &bgrx, 4); + //rt_kprintf("%08x.\n", bgrx); + + // To RGB565 + *(rt_uint16_t *)color = ((bgrx.S.r >> 3) << 11) | ((bgrx.S.g >> 2) << 5) | (bgrx.S.b >> 3); +} + +rt_err_t rt_hw_lcd_ili9341_spi_init(const char *spibusname) +{ + if (rt_spi_bus_attach_device(&ili9341_spi_device, "lcd_ili9341", spibusname, RT_NULL) != RT_EOK) + return -RT_ERROR; + + return rt_spi_configure(&ili9341_spi_device, &ili9341_cfg); +} + +#endif /* #if defined(NU_PKG_USING_ILI9341_SPI) */ diff --git a/bsp/nuvoton/libraries/nu_packages/ILI9341/lcd_ili9341.c b/bsp/nuvoton/libraries/nu_packages/ILI9341/lcd_ili9341.c new file mode 100644 index 0000000000000000000000000000000000000000..c8b24d46be6e80f3fb0b4f8b28480fac4819f54e --- /dev/null +++ b/bsp/nuvoton/libraries/nu_packages/ILI9341/lcd_ili9341.c @@ -0,0 +1,364 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-1-16 Wayne First version +* +******************************************************************************/ + +#include + +#if defined(NU_PKG_USING_ILI9341) + +#include +#include + +static void ili9341_delay_ms(rt_uint32_t nms) +{ + rt_thread_mdelay(nms); +} + +static rt_err_t ili9341_pin_init(void) +{ + rt_pin_mode(BOARD_USING_ILI9341_PIN_DC, PIN_MODE_OUTPUT); + rt_pin_mode(BOARD_USING_ILI9341_PIN_RESET, PIN_MODE_OUTPUT); + rt_pin_mode(BOARD_USING_ILI9341_PIN_BACKLIGHT, PIN_MODE_OUTPUT); + + SET_RS; + SET_RST; + SET_BACKLIGHT_OFF; + + return RT_EOK; +} + +static rt_err_t ili9341_lcd_init(rt_device_t dev) +{ + /* Hardware reset */ + SET_RST; + ili9341_delay_ms(5); // Delay 5ms + + CLR_RST; + ili9341_delay_ms(20); // Delay 20ms + + SET_RST; + ili9341_delay_ms(40); // Delay 40ms + + /* Initial control registers */ + ili9341_send_cmd(0xCB); + ili9341_send_cmd_parameter(0x39); + ili9341_send_cmd_parameter(0x2C); + ili9341_send_cmd_parameter(0x00); + ili9341_send_cmd_parameter(0x34); + ili9341_send_cmd_parameter(0x02); + + ili9341_send_cmd(0xCF); + ili9341_send_cmd_parameter(0x00); + ili9341_send_cmd_parameter(0xC1); + ili9341_send_cmd_parameter(0x30); + + ili9341_send_cmd(0xE8); + ili9341_send_cmd_parameter(0x85); + ili9341_send_cmd_parameter(0x00); + ili9341_send_cmd_parameter(0x78); + + ili9341_send_cmd(0xEA); + ili9341_send_cmd_parameter(0x00); + ili9341_send_cmd_parameter(0x00); + + ili9341_send_cmd(0xED); + ili9341_send_cmd_parameter(0x64); + ili9341_send_cmd_parameter(0x03); + ili9341_send_cmd_parameter(0x12); + ili9341_send_cmd_parameter(0x81); + + ili9341_send_cmd(0xF7); + ili9341_send_cmd_parameter(0x20); + + ili9341_send_cmd(0xC0); + ili9341_send_cmd_parameter(0x23); + + ili9341_send_cmd(0xC1); + ili9341_send_cmd_parameter(0x10); + + ili9341_send_cmd(0xC5); + ili9341_send_cmd_parameter(0x3e); + ili9341_send_cmd_parameter(0x28); + + ili9341_send_cmd(0xC7); + ili9341_send_cmd_parameter(0x86); + + ili9341_send_cmd(0x36); + ili9341_send_cmd_parameter(0x48); // for 240x320 + + ili9341_send_cmd(0x3A); + ili9341_send_cmd_parameter(0x55); + + ili9341_send_cmd(0xB1); + ili9341_send_cmd_parameter(0x00); + ili9341_send_cmd_parameter(0x18); + + ili9341_send_cmd(0xB6); + ili9341_send_cmd_parameter(0x08); + ili9341_send_cmd_parameter(0x82); + ili9341_send_cmd_parameter(0x27); + + ili9341_send_cmd(0xF2); + ili9341_send_cmd_parameter(0x00); + + ili9341_send_cmd(0x26); + ili9341_send_cmd_parameter(0x01); + + ili9341_send_cmd(0xE0); + ili9341_send_cmd_parameter(0x0F); + ili9341_send_cmd_parameter(0x31); + ili9341_send_cmd_parameter(0x2B); + ili9341_send_cmd_parameter(0x0C); + ili9341_send_cmd_parameter(0x0E); + ili9341_send_cmd_parameter(0x08); + ili9341_send_cmd_parameter(0x4E); + ili9341_send_cmd_parameter(0xF1); + ili9341_send_cmd_parameter(0x37); + ili9341_send_cmd_parameter(0x07); + ili9341_send_cmd_parameter(0x10); + ili9341_send_cmd_parameter(0x03); + ili9341_send_cmd_parameter(0x0E); + ili9341_send_cmd_parameter(0x09); + ili9341_send_cmd_parameter(0x00); + + ili9341_send_cmd(0xE1); + ili9341_send_cmd_parameter(0x00); + ili9341_send_cmd_parameter(0x0E); + ili9341_send_cmd_parameter(0x14); + ili9341_send_cmd_parameter(0x03); + ili9341_send_cmd_parameter(0x11); + ili9341_send_cmd_parameter(0x07); + ili9341_send_cmd_parameter(0x31); + ili9341_send_cmd_parameter(0xC1); + ili9341_send_cmd_parameter(0x48); + ili9341_send_cmd_parameter(0x08); + ili9341_send_cmd_parameter(0x0F); + ili9341_send_cmd_parameter(0x0C); + ili9341_send_cmd_parameter(0x31); + ili9341_send_cmd_parameter(0x36); + ili9341_send_cmd_parameter(0x0F); + + ili9341_send_cmd(0x11); + + ili9341_delay_ms(120); // Delay 120ms + + ili9341_send_cmd(0x29); //Display on + + SET_BACKLIGHT_ON; + + return RT_EOK; +} + +static void ili9341_fillscreen(uint16_t color) +{ + ili9341_set_column(0, (XSIZE_PHYS - 1)); + ili9341_set_page(0, (YSIZE_PHYS - 1)); + ili9341_send_cmd(0x2c); + + for (int i = 0; i < (XSIZE_PHYS * YSIZE_PHYS); i++) + ili9341_send_pixel_data(color); +} + +static void ili9341_lcd_set_pixel(const char *color, int x, int y) +{ + ili9341_set_column(x, x); + ili9341_set_page(y, y); + ili9341_send_cmd(0x2c); + ili9341_send_pixel_data(*(uint16_t *)color); +} + +static void ili9341_lcd_draw_hline(const char *pixel, int x1, int x2, int y) +{ + ili9341_set_column(x1, x2); + ili9341_set_page(y, y); + ili9341_send_cmd(0x2c); + + for (; x1 < x2; x1++) + ili9341_send_pixel_data(*(uint16_t *)pixel); +} + +static void ili9341_lcd_draw_vline(const char *pixel, int x, int y1, int y2) +{ + ili9341_set_column(x, x); + ili9341_set_page(y1, y2); + ili9341_send_cmd(0x2c); + + for (; y1 < y2; y1++) + ili9341_send_pixel_data(*(uint16_t *)pixel); +} + +static void ili9341_lcd_blit_line(const char *pixels, int x, int y, rt_size_t size) +{ + rt_uint16_t *ptr = (rt_uint16_t *)pixels; + + ili9341_set_column(x, x + size); + ili9341_set_page(y, y); + ili9341_send_cmd(0x2c); + + while (size--) + ili9341_send_pixel_data(*ptr++); +} + +static rt_err_t ili9341_lcd_open(rt_device_t dev, rt_uint16_t oflag) +{ + return RT_EOK; +} + +static rt_err_t ili9341_lcd_close(rt_device_t dev) +{ + return RT_EOK; +} + +static rt_err_t ili9341_lcd_control(rt_device_t dev, int cmd, void *args) +{ + switch (cmd) + { + case RTGRAPHIC_CTRL_GET_INFO: + { + struct rt_device_graphic_info *info; + + info = (struct rt_device_graphic_info *) args; + RT_ASSERT(info != RT_NULL); + + info->bits_per_pixel = 16; + info->pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565; + info->framebuffer = RT_NULL; + info->width = XSIZE_PHYS; + info->height = YSIZE_PHYS; + } + break; + + case RTGRAPHIC_CTRL_RECT_UPDATE: + /* nothong to be done */ + break; + + default: + break; + } + + return RT_EOK; +} + +static struct rt_device lcd_device; +static struct rt_device_graphic_ops ili9341_ops = +{ + ili9341_lcd_set_pixel, + ili9341_lcd_get_pixel, + ili9341_lcd_draw_hline, + ili9341_lcd_draw_vline, + ili9341_lcd_blit_line +}; + +int rt_hw_lcd_ili9341_init(void) +{ + ili9341_pin_init(); + + /* register lcd device */ + lcd_device.type = RT_Device_Class_Graphic; + lcd_device.init = ili9341_lcd_init; + lcd_device.open = ili9341_lcd_open; + lcd_device.close = ili9341_lcd_close; + lcd_device.control = ili9341_lcd_control; + lcd_device.read = RT_NULL; + lcd_device.write = RT_NULL; + + lcd_device.user_data = &ili9341_ops; + + /* register graphic device driver */ + rt_device_register(&lcd_device, "lcd", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STANDALONE); + + return 0; +} + +#ifdef RT_USING_FINSH +#define LINE_LEN 32 +static void lcd_test(int argc, char *argv[]) +{ + uint16_t pixels[LINE_LEN]; + uint16_t color; + int x, y, i; + x = y = 100; + + ili9341_lcd_init(NULL); + + color = 0x0; //Black, RGB + rt_kprintf("Brush 0x%X on screen.\n", color); + ili9341_fillscreen(color); + ili9341_lcd_get_pixel((char *)&color, x, y); + rt_kprintf("lcd get pixel, pixel: 0x%X, x: %d, y: %d\n", color, x, y); + + color = 0xffff; //White, RGB + rt_kprintf("Brush 0x%X on screen.\n", color); + ili9341_fillscreen(color); + ili9341_lcd_get_pixel((char *)&color, x, y); + rt_kprintf("lcd get pixel, pixel: 0x%X, x: %d, y: %d\n", color, x, y); + + color = 0x1f; //Blue, RGB + rt_kprintf("Brush 0x%X on screen.\n", color); + ili9341_fillscreen(color); + ili9341_lcd_get_pixel((char *)&color, x, y); + rt_kprintf("lcd get pixel, pixel: 0x%X, x: %d, y: %d\n", color, x, y); + + color = 0x07e0; //Green, RGB + rt_kprintf("Brush 0x%X on screen.\n", color); + ili9341_fillscreen(color); + ili9341_lcd_get_pixel((char *)&color, x, y); + rt_kprintf("lcd get pixel, pixel: 0x%X, x: %d, y: %d\n", color, x, y); + + color = 0xf800; //Red, RGB + rt_kprintf("Brush 0x%X on screen.\n", color); + ili9341_fillscreen(color); + ili9341_lcd_get_pixel((char *)&color, x, y); + rt_kprintf("lcd get pixel, pixel: 0x%X, x: %d, y: %d\n", color, x, y); + + color = 0xffff; //White, RGB + rt_kprintf("lcd draw hline, pixel: 0x%X, x1: %d, x2: %d, y: %d\n", color, x, x + 20, y); + ili9341_lcd_draw_hline((const char *)&color, x, x + 20, y); + + color = 0xffff; //White, RGB + rt_kprintf("lcd draw vline, pixel: 0x%X, x: %d, y: %d\n", color, y, y + 20); + ili9341_lcd_draw_vline((const char *)&color, x, y, y + 20); + + for (i = 0; i < LINE_LEN; i++) + pixels[i] = 20 + i * 5; + + x = y = 50; + rt_kprintf("lcd blit line, start: x: %d, y: %d\n", x, y); + ili9341_lcd_blit_line((const char *)&pixels[0], x, y, LINE_LEN); + + x = y = 200; + color = 0x07E0; //Green, RGB + rt_kprintf("lcd set pixel, pixel: 0x%X, x: %d, y: %d\n", color, x, y); + ili9341_lcd_set_pixel((const char *)&color, x, y); + color = 0x0; + ili9341_lcd_get_pixel((char *)&color, x, y); + rt_kprintf("lcd get pixel, pixel: 0x%X, x: %d, y: %d\n", color, x, y); + + x = y = 200; + color = 0x1f; //Blue, RGB + rt_kprintf("lcd set pixel, pixel: 0x%X, x: %d, y: %d\n", color, x, y); + ili9341_lcd_set_pixel((const char *)&color, x, y); + color = 0x0; + ili9341_lcd_get_pixel((char *)&color, x, y); + rt_kprintf("lcd get pixel, pixel: 0x%X, x: %d, y: %d\n", color, x, y); + + x = y = 200; + color = 0xf800; //Red, RGB + rt_kprintf("lcd set pixel, pixel: 0x%X, x: %d, y: %d\n", color, x, y); + ili9341_lcd_set_pixel((const char *)&color, x, y); + color = 0x0; + ili9341_lcd_get_pixel((char *)&color, x, y); + rt_kprintf("lcd get pixel, pixel: 0x%X, x: %d, y: %d\n", color, x, y); +} +MSH_CMD_EXPORT(lcd_test, test lcd display); +#endif + +#endif /* if defined(NU_PKG_USING_ILI9341) */ diff --git a/bsp/nuvoton/libraries/nu_packages/ILI9341/lcd_ili9341.h b/bsp/nuvoton/libraries/nu_packages/ILI9341/lcd_ili9341.h new file mode 100644 index 0000000000000000000000000000000000000000..3cc39cfcf159d53adfa7bf8ce24e324086dfe65c --- /dev/null +++ b/bsp/nuvoton/libraries/nu_packages/ILI9341/lcd_ili9341.h @@ -0,0 +1,48 @@ +/**************************************************************************//** +* +* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-1-16 Wayne First version +* +******************************************************************************/ + +#ifndef __LCD_ILI9341_H__ +#define __LCD_ILI9341_H__ + +#include +#include + +#define SET_RS rt_pin_write(BOARD_USING_ILI9341_PIN_DC, 1) +#define CLR_RS rt_pin_write(BOARD_USING_ILI9341_PIN_DC, 0) + +#define SET_RST rt_pin_write(BOARD_USING_ILI9341_PIN_RESET, 1) +#define CLR_RST rt_pin_write(BOARD_USING_ILI9341_PIN_RESET, 0) + +#define SET_BACKLIGHT_ON rt_pin_write(BOARD_USING_ILI9341_PIN_BACKLIGHT, 1) +#define SET_BACKLIGHT_OFF rt_pin_write(BOARD_USING_ILI9341_PIN_BACKLIGHT, 0) + +// +// Physical display size +// +#define XSIZE_PHYS 240 +#define YSIZE_PHYS 320 + +int rt_hw_lcd_ili9341_init(void); +void ili9341_send_cmd(rt_uint8_t cmd); +void ili9341_send_cmd_parameter(rt_uint8_t data); +void ili9341_set_column(rt_uint16_t StartCol, rt_uint16_t EndCol); +void ili9341_set_page(rt_uint16_t StartPage, rt_uint16_t EndPage); +void ili9341_send_pixel_data(rt_uint16_t color); +void ili9341_lcd_get_pixel(char *color, int x, int y); + +#if defined(NU_PKG_USING_ILI9341_SPI) + rt_err_t rt_hw_lcd_ili9341_spi_init(const char *spibusname); +#elif defined(NU_PKG_USING_ILI9341_EBI) + rt_err_t rt_hw_lcd_ili9341_ebi_init(rt_uint32_t ebi_base); +#endif + +#endif /* __LCD_ILI9341_H__ */ diff --git a/bsp/nuvoton/libraries/nu_packages/Kconfig b/bsp/nuvoton/libraries/nu_packages/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..37c1bf6bddf5f6e9596f2c1f63fda755215b1b43 --- /dev/null +++ b/bsp/nuvoton/libraries/nu_packages/Kconfig @@ -0,0 +1,52 @@ +menu "Nuvoton Packages Config" + config NU_PKG_USING_UTILS + bool + default y + + config NU_PKG_USING_DEMO + bool "Enable demos" + default y + + config NU_PKG_USING_BMX055 + bool "BMX055 9-axis sensor." + select RT_USING_I2C + select RT_USING_SENSOR + default n + + config NU_PKG_USING_MAX31875 + bool "MAX31875 Temperature sensor." + select RT_USING_I2C + select RT_USING_SENSOR + default n + + config NU_PKG_USING_NAU88L25 + bool "NAU88L25 Audio Codec." + select BSP_USING_I2C + default n + + config NU_PKG_USING_ILI9341 + bool "ILI9341 LCD Panel" + select BSP_USING_GPIO + default n + + if NU_PKG_USING_ILI9341 + + choice + prompt "Select ili9341 interface" + + config NU_PKG_USING_ILI9341_SPI + select BSP_USING_SPI + bool "ILI9341_SPI" + help + Choose this option if you the ili9341 device is with SPI interface. + + config NU_PKG_USING_ILI9341_EBI + select BSP_USING_EBI + bool "ILI9341_EBI" + help + Choose this option if you the ili9341 device is with EBI interface. + endchoice + + endif + +endmenu diff --git a/bsp/nuvoton/libraries/nu_packages/MAX31875/SConscript b/bsp/nuvoton/libraries/nu_packages/MAX31875/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..1a4a5158818fc523c216c513dfde652e14d1b353 --- /dev/null +++ b/bsp/nuvoton/libraries/nu_packages/MAX31875/SConscript @@ -0,0 +1,14 @@ +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +group = [] +if GetDepend('NU_PKG_USING_MAX31875'): + src = Split(""" + libraries/max31875_c.c + sensor_max31875.c + """) + CPPPATH = [cwd, cwd + '/libraries'] + group = DefineGroup('nu_pkgs_max31875', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/nuvoton/libraries/nu_packages/MAX31875/libraries/max31875.h b/bsp/nuvoton/libraries/nu_packages/MAX31875/libraries/max31875.h new file mode 100644 index 0000000000000000000000000000000000000000..9446cb7d98f5e66b861ae0265f59d456f08e949b --- /dev/null +++ b/bsp/nuvoton/libraries/nu_packages/MAX31875/libraries/max31875.h @@ -0,0 +1,117 @@ +/******************************************************************************* +* Copyright (C) 2019 Maxim Integrated Products, Inc., All Rights Reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES +* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +* OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of Maxim Integrated +* Products, Inc. shall not be used except as stated in the Maxim Integrated +* Products, Inc. Branding Policy. +* +* The mere transfer of this software does not imply any licenses +* of trade secrets, proprietary technology, copyrights, patents, +* trademarks, maskwork rights, or any other form of intellectual +* property whatsoever. Maxim Integrated Products, Inc. retains all +* ownership rights. +******************************************************************************* +* @file MAX31875.h +******************************************************************************* +*/ +#ifndef MAX31875_H +#define MAX31875_H +#include + +#define MAX31875_NO_ERROR 0 +#define MAX31875_ERROR -1 + +#define MAX31875_REG_TEMPERATURE 0X00 +#define MAX31875_REG_CONFIGURATION 0X01 +#define MAX31875_REG_THYST_LOW_TRIP 0X02 +#define MAX31875_REG_TOS_HIGH_TRIP 0X03 +#define MAX31875_REG_MAX 0X03 + +#define MAX31875_CFG_ONE_SHOT_START (1) /* Start one-shot measurement */ + +#define MAX31875_CFG_CONV_RATE_0_25 (0x00 << 1) /* 0.25 conversions/sec */ +#define MAX31875_CFG_CONV_RATE_1 (0x01 << 1) /* 1.0 conversions/sec */ +#define MAX31875_CFG_CONV_RATE_4 (0x02 << 1) /* 4.0 conversions/sec */ +#define MAX31875_CFG_CONV_RATE_8 (0x03 << 1) /* 8.0 conversions/sec */ +#define MAX31875_WAIT_CONV_RATE_0_25 (4.002) +#define MAX31875_WAIT_CONV_RATE_1 (1.0) +#define MAX31875_WAIT_CONV_RATE_4 (0.25) +#define MAX31875_WAIT_CONV_RATE_8 (0.125) + +#define MAX31875_CFG_RESOLUTION_9BIT (0x00 << 5) +#define MAX31875_CFG_RESOLUTION_10BIT (0x01 << 5) +#define MAX31875_CFG_RESOLUTION_11BIT (0x02 << 5) +#define MAX31875_CFG_RESOLUTION_12BIT (0x03 << 5) + +#define MAX31875_CFG_NORMAL_FORMAT (0X00 << 7) +#define MAX31875_CFG_EXTENDED_FORMAT (0X01 << 7) + +#define MAX31875_CFG_CONTINUOUS (0X00 << 8) +#define MAX31875_CFG_SHUTDOWN (0X01 << 8) + +#define MAX31875_CFG_COMPARATOR_MODE (0X00 << 9) +#define MAX31875_CFG_INTERRUPT_MODE (0X01 << 9) + + +#define MAX31875_CFG_FAULT_FILTER_1 (0x00 << 11) +#define MAX31875_CFG_FAULT_FILTER_2 (0x01 << 11) +#define MAX31875_CFG_FAULT_FILTER_4 (0x02 << 11) +#define MAX31875_CFG_FAULT_FILTER_6 (0x03 << 11) + +#define MAX31875_CFG_OVER_TEMP_MASK (0x80) + + +#define MAX31875_I2C_SLAVE_ADR_R0 (0x90 >> 1) // code uses the 7 bit address +#define MAX31875_I2C_SLAVE_ADR_R1 (0x92 >> 1) +#define MAX31875_I2C_SLAVE_ADR_R2 (0x94 >> 1) +#define MAX31875_I2C_SLAVE_ADR_R3 (0x96 >> 1) +#define MAX31875_I2C_SLAVE_ADR_R4 (0x98 >> 1) +#define MAX31875_I2C_SLAVE_ADR_R5 (0x9A >> 1) +#define MAX31875_I2C_SLAVE_ADR_R6 (0x9C >> 1) +#define MAX31875_I2C_SLAVE_ADR_R7 (0x9E >> 1) + +#define MAX31875_CF_NORMAL_FORMAT (0.00390625F) +#define MAX31875_CF_EXTENDED_FORMAT (0.0078125F) + +/** @union max31875_raw_data + * @brief union data structure for byte word manipulations + */ +typedef union +{ + struct + { + uint8_t lsb; + uint8_t msb; + } s_lm; + struct + { + uint16_t magnitude_bits: 15; + uint16_t sign_bit: 1; + } s_ms; + uint16_t uwrd; + int16_t swrd; +} max31875_raw_data; + +#define MAX31875_U16_MAX ((uint16_t)~0U) +#define MAX31875_S16_MAX ((int16_t)(MAX31875_U16_MAX>>1)) +#define MAX31875_S16_MIN ((int16_t)(-MAX31875_S16_MAX - 1)) + +#endif/* MAX31875_H */ diff --git a/bsp/nuvoton/libraries/nu_packages/MAX31875/libraries/max31875_c.c b/bsp/nuvoton/libraries/nu_packages/MAX31875/libraries/max31875_c.c new file mode 100644 index 0000000000000000000000000000000000000000..178d24373c126e4d0c964f3e0505a605f3e70426 --- /dev/null +++ b/bsp/nuvoton/libraries/nu_packages/MAX31875/libraries/max31875_c.c @@ -0,0 +1,193 @@ +/******************************************************************************* +* Copyright (C) 2019 Maxim Integrated Products, Inc., All Rights Reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES +* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +* OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of Maxim Integrated +* Products, Inc. shall not be used except as stated in the Maxim Integrated +* Products, Inc. Branding Policy. +* +* The mere transfer of this software does not imply any licenses +* of trade secrets, proprietary technology, copyrights, patents, +* trademarks, maskwork rights, or any other form of intellectual +* property whatsoever. Maxim Integrated Products, Inc. retains all +* ownership rights. +******************************************************************************* +*/ +#include "max31875.h" +#include "max31875_c.h" + +/******************************************************************************/ +/* C version for MAX31875 driver */ +/******************************************************************************/ + +/* @var max31875_write_address, max31875_read_address + * @brief I2C address + */ +static uint32_t max31875_extended_format; + +int max31875_init(uint8_t slave_address) +{ + max31875_extended_format = 0; + return MAX31875_NO_ERROR; +} + + +/******************************************************************************/ +int max31875_read_reg(uint16_t *value, char reg, S_MAX31875 *psObj) +{ + int32_t ret; + char data[2] = {0, 0}; + max31875_raw_data tmp; + + if (reg <= MAX31875_REG_MAX) + { + /* write to the Register Select */ + ret = psObj->read(psObj->address, ®, 1, data, 2); + /* read the two bytes of data */ + if (ret == 0) + { + tmp.s_lm.msb = data[0]; + tmp.s_lm.lsb = data[1]; + *value = tmp.uwrd; + return MAX31875_NO_ERROR; + } + else + { + //printf("%s: failed to write to Register Select: ret: %d\r\n", __func__, ret); + } + } + else + { + //printf("%s: register address is not correct: register: %d\r\n", __func__, reg); + } + return MAX31875_ERROR; +} + +float max31875_read_reg_as_temperature(uint8_t reg, S_MAX31875 *psObj) +{ + max31875_raw_data tmp; + float temperature; + if (reg == MAX31875_REG_TEMPERATURE || + reg == MAX31875_REG_THYST_LOW_TRIP || reg == MAX31875_REG_TOS_HIGH_TRIP) + { + max31875_read_reg(&tmp.uwrd, reg, psObj); + temperature = (float)tmp.s_ms.magnitude_bits; + if (max31875_extended_format) + temperature *= MAX31875_CF_EXTENDED_FORMAT; + else + temperature *= MAX31875_CF_NORMAL_FORMAT; + if (tmp.s_ms.sign_bit) + temperature = -temperature; + return temperature; + } + else + { + //printf("%s: register is invalid, %d r\n", __func__, reg); + return 0; + } +} + + +/******************************************************************************/ +int max31875_write_reg(uint16_t value, char reg, S_MAX31875 *psObj) +{ + int32_t ret; + char cmd[3]; + max31875_raw_data tmp; + + if (reg >= MAX31875_REG_CONFIGURATION && reg <= MAX31875_REG_MAX) + { + cmd[0] = reg; + tmp.uwrd = value; + cmd[1] = tmp.s_lm.msb; + cmd[2] = tmp.s_lm.lsb; + ret = psObj->write(psObj->address, cmd, 3); + if (ret == 0) + { + if (MAX31875_REG_CONFIGURATION == reg) + { + max31875_extended_format = 0; + if (tmp.uwrd & MAX31875_CFG_EXTENDED_FORMAT) + max31875_extended_format = 1; + } + return MAX31875_NO_ERROR; + } + else + { + //printf("%s: I2C write error %d\r\n", __func__, ret); + return MAX31875_ERROR; + } + } + else + { + //printf("%s: register value invalid %x\r\n", __func__, reg); + return MAX31875_ERROR; + } +} + + +int max31875_write_cfg(uint16_t cfg, S_MAX31875 *psObj) +{ + return max31875_write_reg(cfg, MAX31875_REG_CONFIGURATION, psObj); +} + + +int max31875_write_trip_low(float temperature, S_MAX31875 *psObj) +{ + max31875_raw_data raw; + raw.uwrd = 0; + if (temperature < 0) + { + raw.s_ms.sign_bit = 1; + temperature = -temperature; + } + if (max31875_extended_format) + temperature /= MAX31875_CF_EXTENDED_FORMAT; + else + temperature /= MAX31875_CF_NORMAL_FORMAT; + raw.s_ms.magnitude_bits = (uint16_t)temperature; + return max31875_write_reg(raw.uwrd, MAX31875_REG_THYST_LOW_TRIP, psObj); +} + + +int max31875_write_trip_high(float temperature, S_MAX31875 *psObj) +{ + max31875_raw_data raw; + raw.uwrd = 0; + if (temperature < 0) + { + raw.s_ms.sign_bit = 1; + temperature = -temperature; + } + if (max31875_extended_format) + temperature /= MAX31875_CF_EXTENDED_FORMAT; + else + temperature /= MAX31875_CF_NORMAL_FORMAT; + raw.s_ms.magnitude_bits = (uint16_t)temperature; + return max31875_write_reg(raw.uwrd, MAX31875_REG_TOS_HIGH_TRIP, psObj); +} + + +float max31875_celsius_to_fahrenheit(float temp_c) +{ + float temp_f; + temp_f = ((temp_c * 9) / 5) + 32; + return temp_f; +} diff --git a/bsp/nuvoton/libraries/nu_packages/MAX31875/libraries/max31875_c.h b/bsp/nuvoton/libraries/nu_packages/MAX31875/libraries/max31875_c.h new file mode 100644 index 0000000000000000000000000000000000000000..6037ec67da927826e38d84d8823c05fd664ce7c9 --- /dev/null +++ b/bsp/nuvoton/libraries/nu_packages/MAX31875/libraries/max31875_c.h @@ -0,0 +1,70 @@ +/******************************************************************************* +* Copyright (C) 2019 Maxim Integrated Products, Inc., All Rights Reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES +* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +* OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of Maxim Integrated +* Products, Inc. shall not be used except as stated in the Maxim Integrated +* Products, Inc. Branding Policy. +* +* The mere transfer of this software does not imply any licenses +* of trade secrets, proprietary technology, copyrights, patents, +* trademarks, maskwork rights, or any other form of intellectual +* property whatsoever. Maxim Integrated Products, Inc. retains all +* ownership rights. +******************************************************************************* +* @file max31875_c.h +******************************************************************************* +*/ +#ifndef MAX31875_C_H +#define MAX31875_C_H + +#include +#include +#include "max31875.h" + +//Define I2C class to instead of mbed API. +typedef struct +{ + uint32_t address; + int (*read)(int address, const char *reg, int reg_length, char *data, int length); + int (*write)(int address, const char *data, int length); +} S_MAX31875; + +/*****************************************************************************/ +/* C header for MAX31875 driver */ +/*****************************************************************************/ + +int max31875_init(uint8_t slaveAddress); + +int max31875_read_reg(uint16_t *value, char reg, S_MAX31875 *psObj); + +float max31875_read_reg_as_temperature(uint8_t reg, S_MAX31875 *psObj); + +int max31875_write_reg(uint16_t value, char reg, S_MAX31875 *psObj); + +int max31875_write_cfg(uint16_t cfg, S_MAX31875 *psObj); + +int max31875_write_trip_low(float temperature, S_MAX31875 *psObj); + +int max31875_write_trip_high(float temperature, S_MAX31875 *psObj); + +float max31875_celsius_to_fahrenheit(float temp_c); + +#endif/* MAX31875_C_H */ diff --git a/bsp/nuvoton/libraries/nu_packages/MAX31875/sensor_max31875.c b/bsp/nuvoton/libraries/nu_packages/MAX31875/sensor_max31875.c new file mode 100644 index 0000000000000000000000000000000000000000..978aa14fc1dd192426fe61b2708e3d5530379fa0 --- /dev/null +++ b/bsp/nuvoton/libraries/nu_packages/MAX31875/sensor_max31875.c @@ -0,0 +1,163 @@ +/**************************************************************************//** +* +* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-1-16 Wayne First version +* +******************************************************************************/ + +#include + +#if defined(NU_PKG_USING_MAX31875) + +#include "sensor.h" +#include "max31875_c.h" + +#define DBG_ENABLE +#define DBG_LEVEL DBG_LOG +#define DBG_SECTION_NAME "sensor.max31875" +#define DBG_COLOR +#include + +static S_MAX31875 g_sMax31875; +static struct rt_i2c_bus_device *i2c_bus_dev; + +static int max31875_i2c_write_reg(int address, const char *data, int length) +{ + struct rt_i2c_msg msg; + + msg.addr = address; /* Slave address */ + msg.flags = RT_I2C_WR; /* Write flag */ + msg.buf = (rt_uint8_t *)data; /* Slave register address */ + msg.len = length; /* Number of bytes sent */ + + if (rt_i2c_transfer(i2c_bus_dev, &msg, 1) != 1) + { + return -RT_ERROR; + } + + return RT_EOK; +} + +static int max31875_i2c_read_reg(int address, const char *reg, int reg_length, char *data, int length) +{ + struct rt_i2c_msg msgs[2]; + + msgs[0].addr = address; /* Slave address */ + msgs[0].flags = RT_I2C_WR; /* Write flag */ + msgs[0].buf = (rt_uint8_t *)reg; /* Slave register address */ + msgs[0].len = reg_length; /* Number of bytes sent */ + msgs[1].addr = address; /* Slave address */ + msgs[1].flags = RT_I2C_RD; /* Read flag without READ_ACK */ + msgs[1].buf = (rt_uint8_t *)data; /* Read data pointer */ + msgs[1].len = length; /* Number of bytes read */ + + if (rt_i2c_transfer(i2c_bus_dev, &msgs[0], 2) != 2) + { + return -RT_ERROR; + } + + return RT_EOK; +} + +static rt_size_t max31875_fetch_data(struct rt_sensor_device *sensor, void *buf, rt_size_t len) +{ + struct rt_sensor_data *data = (struct rt_sensor_data *)buf; + + if (sensor->info.type == RT_SENSOR_CLASS_TEMP) + { + float temp_value; + temp_value = max31875_read_reg_as_temperature(MAX31875_REG_TEMPERATURE, &g_sMax31875); + data->type = RT_SENSOR_CLASS_TEMP; + data->data.temp = (rt_int32_t)(temp_value * 10); + data->timestamp = rt_sensor_get_ts(); + } + + return 1; +} + +static rt_err_t max31875_control(struct rt_sensor_device *sensor, int cmd, void *args) +{ + return -RT_ERROR; +} + +static struct rt_sensor_ops sensor_ops = +{ + max31875_fetch_data, + max31875_control +}; + +int rt_hw_max31875_temp_init(const char *name, struct rt_sensor_config *cfg) +{ + rt_int8_t result; + rt_sensor_t sensor = RT_NULL; + + sensor = rt_calloc(1, sizeof(struct rt_sensor_device)); + if (sensor == RT_NULL) + return -(RT_ENOMEM); + + sensor->info.type = RT_SENSOR_CLASS_TEMP; + sensor->info.vendor = RT_SENSOR_VENDOR_UNKNOWN; + sensor->info.model = "max31875_temp"; + sensor->info.unit = RT_SENSOR_UNIT_DCELSIUS; + sensor->info.intf_type = RT_SENSOR_INTF_I2C; + sensor->info.range_max = 70; + sensor->info.range_min = 0; + sensor->info.period_min = 100; //100ms + + rt_memcpy(&sensor->config, cfg, sizeof(struct rt_sensor_config)); + sensor->ops = &sensor_ops; + + result = rt_hw_sensor_register(sensor, name, RT_DEVICE_FLAG_RDWR, RT_NULL); + if (result != RT_EOK) + { + LOG_E("device register: %d", result); + rt_free(sensor); + return -RT_ERROR; + } + + return RT_EOK; +} + +int rt_hw_max31875_init(const char *name, struct rt_sensor_config *cfg) +{ + struct rt_sensor_intf *intf; + rt_err_t ret = RT_ERROR; + + RT_ASSERT(name != NULL); + RT_ASSERT(cfg != NULL); + + intf = &cfg->intf; + + /* Find I2C bus */ + i2c_bus_dev = (struct rt_i2c_bus_device *)rt_device_find(intf->dev_name); + if (i2c_bus_dev == RT_NULL) + { + goto exit_rt_hw_max31875_init; + } + + g_sMax31875.read = max31875_i2c_read_reg; + g_sMax31875.write = max31875_i2c_write_reg; + g_sMax31875.address = (uint32_t)(intf->user_data) & 0xff; + + if ((ret = max31875_init(g_sMax31875.address)) != RT_EOK) + { + LOG_E("Init..!\n"); + } + else if ((ret = max31875_write_cfg(MAX31875_CFG_CONV_RATE_8 | MAX31875_CFG_RESOLUTION_12BIT, &g_sMax31875)) != RT_EOK) + { + LOG_E("Write_cfg..!\n"); + } + else + return rt_hw_max31875_temp_init(name, cfg); + +exit_rt_hw_max31875_init: + + return -(ret); +} + +#endif //#if defined(NU_PKG_USING_MAX31875) diff --git a/bsp/nuvoton/libraries/nu_packages/MAX31875/sensor_max31875.h b/bsp/nuvoton/libraries/nu_packages/MAX31875/sensor_max31875.h new file mode 100644 index 0000000000000000000000000000000000000000..ac1c976bfafac73bbe51bab73b704a9777b432cb --- /dev/null +++ b/bsp/nuvoton/libraries/nu_packages/MAX31875/sensor_max31875.h @@ -0,0 +1,21 @@ +/**************************************************************************//** +* +* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-1-16 Wayne First version +* +******************************************************************************/ + +#ifndef __SENSOR_MAX31875_H__ +#define __SENSOR_MAX31875_H__ + +#include "sensor.h" +#include "max31875_c.h" + +int rt_hw_max31875_init(const char *name, struct rt_sensor_config *cfg); + +#endif /* __SENSOR_MAX31875_H__ */ diff --git a/bsp/nuvoton/libraries/nu_packages/NuUtils/SConscript b/bsp/nuvoton/libraries/nu_packages/NuUtils/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..3c7feb86d7e32d2f6068235711bf5e6035b944d5 --- /dev/null +++ b/bsp/nuvoton/libraries/nu_packages/NuUtils/SConscript @@ -0,0 +1,9 @@ +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +src = [] +CPPPATH = [cwd + '/inc'] +group = DefineGroup('numicro_common', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/nuvoton/libraries/nu_packages/NuUtils/inc/nu_bitutil.h b/bsp/nuvoton/libraries/nu_packages/NuUtils/inc/nu_bitutil.h new file mode 100644 index 0000000000000000000000000000000000000000..2596ac0985df5f1b8f5bd53bcdef81f2eddc9bf4 --- /dev/null +++ b/bsp/nuvoton/libraries/nu_packages/NuUtils/inc/nu_bitutil.h @@ -0,0 +1,213 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-2-7 Wayne First version +* +******************************************************************************/ +#ifndef __NU_BITUTIL_H__ +#define __NU_BITUTIL_H__ + +#if defined(__ICCARM__) + #include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* ---------------------------------------------- + * Count Leading Zeros Count Trailing Zeros + * (MSB)00000000000000001000000000001000(LSB) + * ################| |!!! + * Find Highest Set Find First Set + * ---------------------------------------------- + * + * ---------------------------------------------- + * Count Leading Ones Count Trailing Ones + * (MSB)11111111111111110111111111110111(LSB) + * ^^^^^^^^^^^^^^^^| |@@@ + * Find Highest Zero Find First Zero + * ---------------------------------------------- +*/ + +/* Count Leading Zeros in word - Find Highest Set + EX: x=(MSB)00000000000000001000000000001000(LSB) + ################| + Find Highest Set + nu_clz will start zero-counting from MSB and return the number. +*/ +__STATIC_INLINE int nu_clz(uint32_t x) +{ + return __CLZ(x); +} + +/* Count Leading Ones in word - Find Highest Zero + EX: x=(MSB)11111111111111110111111111110111(LSB) + ^^^^^^^^^^^^^^^^| + Find Highest Zero + nu_clo will start one-counting from MSB and return the number. +*/ +__STATIC_INLINE int nu_clo(uint32_t x) +{ + return nu_clz(~x); +} + +/* Count Trailing Zero in word - Find First Set + EX: x=(MSB)00000000000000001000000000001000(LSB) + |!!! + Find First Set + nu_ctz will start zero-counting from LSB and return the number. +*/ +__STATIC_INLINE int nu_ctz(uint32_t x) +{ + int c = __CLZ(x & -x); + return x ? 31 - c : c; +} + +/* Count Trailing Ones in word - Find First Zero + EX: x=(MSB)11111111111111110111111111110111(LSB) + |@@@ + Find First Zero + nu_cto will start one-counting from LSB and return the number. +*/ +__STATIC_INLINE int nu_cto(uint32_t x) +{ + return nu_ctz(~x); +} + +/* Get 16-bit from a byte-array in little-endian */ +__STATIC_INLINE uint16_t nu_get16_le(const uint8_t *pos) +{ + uint16_t val; + + val = *pos ++; + val += (*pos << 8); + + return val; +} + +/* Set 16-bit to a byte-array in little-endian */ +__STATIC_INLINE void nu_set16_le(uint8_t *pos, uint16_t val) +{ + *pos ++ = val & 0xFF; + *pos = val >> 8; +} + +/* Get 32-bit from a byte-array in little-endian */ +__STATIC_INLINE uint32_t nu_get32_le(const uint8_t *pos) +{ + uint32_t val; + + val = *pos ++; + val += (*pos ++ << 8); + val += (*pos ++ << 16); + val += (*pos ++ << 24); + + return val; +} + +/* Get 24-bit from a byte-array in little-endian */ +__STATIC_INLINE uint32_t nu_get24_le(const uint8_t *pos) +{ + uint32_t val; + + val = *pos ++; + val += (*pos ++ << 8); + val += (*pos ++ << 16); + + return val; +} + +/* Set 24-bit to a byte-array in little-endian */ +__STATIC_INLINE void nu_set24_le(uint8_t *pos, uint32_t val) +{ + *pos ++ = val & 0xFF; + *pos ++ = (val >> 8) & 0xFF; + *pos ++ = (val >> 16) & 0xFF; +} + +/* Set 32-bit to a byte-array in little-endian */ +__STATIC_INLINE void nu_set32_le(uint8_t *pos, uint32_t val) +{ + *pos ++ = val & 0xFF; + *pos ++ = (val >> 8) & 0xFF; + *pos ++ = (val >> 16) & 0xFF; + *pos = (val >> 24) & 0xFF; +} + +/* Get 16-bit from a byte-array in big-endian */ +__STATIC_INLINE uint16_t nu_get16_be(const uint8_t *pos) +{ + uint16_t val; + + val = *pos ++; + val <<= 8; + val += *pos; + + return val; +} + +/* Set 16-bit to a byte-array in big-endian */ +__STATIC_INLINE void nu_set16_be(uint8_t *pos, uint16_t val) +{ + *pos ++ = val >> 8; + *pos = (val & 0xFF); +} + +/* Get 24-bit from a byte-array in big-endian */ +__STATIC_INLINE uint32_t nu_get24_be(const uint8_t *pos) +{ + uint32_t val; + + val = *pos ++; + val <<= 8; + val += *pos ++; + val <<= 8; + val += *pos ++; + + return val; +} + +/* Set 24-bit to a byte-array in big-endian */ +__STATIC_INLINE void nu_set24_be(uint8_t *pos, uint32_t val) +{ + *pos ++ = val >> 16; + *pos ++ = val >> 8; + *pos ++ = (val & 0xFF); +} + +/* Get 32-bit from a byte-array in big-endian */ +__STATIC_INLINE uint32_t nu_get32_be(const uint8_t *pos) +{ + uint32_t val; + + val = *pos ++; + val <<= 8; + val += *pos ++; + val <<= 8; + val += *pos ++; + val <<= 8; + val += *pos; + + return val; +} + +/* Set 32-bit to a byte-array in big-endian */ +__STATIC_INLINE void nu_set32_be(uint8_t *pos, uint32_t val) +{ + *pos ++ = val >> 24; + *pos ++ = val >> 16; + *pos ++ = val >> 8; + *pos ++ = (val & 0xFF); +} + +#ifdef __cplusplus +} +#endif + +#endif //__NU_BITUTIL_H__ diff --git a/bsp/nuvoton/libraries/nu_packages/NuUtils/inc/nu_miscutil.h b/bsp/nuvoton/libraries/nu_packages/NuUtils/inc/nu_miscutil.h new file mode 100644 index 0000000000000000000000000000000000000000..6f7c72a2c9ce52fc2fdec06302984c7e882c280f --- /dev/null +++ b/bsp/nuvoton/libraries/nu_packages/NuUtils/inc/nu_miscutil.h @@ -0,0 +1,39 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-2-7 Wayne First version +* +******************************************************************************/ + +#ifndef NU_MISC_UTIL_H +#define NU_MISC_UTIL_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define NU_MAX(a,b) ((a)>(b)?(a):(b)) +#define NU_MIN(a,b) ((a)<(b)?(a):(b)) +#define NU_CLAMP(x, min, max) NU_MIN(NU_MAX((x), (min)), (max)) +#define NU_ALIGN_DOWN(X, ALIGN) ((X) & ~((ALIGN) - 1)) +#define NU_ALIGN_UP(X, ALIGN) (((X) + (ALIGN) - 1) & ~((ALIGN) - 1)) +#define NU_ISALIGNED(a, b) (((a) & (b - 1)) == 0) + +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) +#define READ_BIT(REG, BIT) ((REG) & (BIT)) +#define CLEAR_REG(REG) ((REG) = (0x0)) +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) +#define READ_REG(REG) ((REG)) +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/nuvoton/libraries/nu_packages/SConscript b/bsp/nuvoton/libraries/nu_packages/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..4c815c49b835a3a5ea61f337dc17154dd316d7d1 --- /dev/null +++ b/bsp/nuvoton/libraries/nu_packages/SConscript @@ -0,0 +1,15 @@ +# RT-Thread building script for bridge + +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/nuvoton/numaker-iot-m487/.config b/bsp/nuvoton/numaker-iot-m487/.config new file mode 100644 index 0000000000000000000000000000000000000000..4b629558981f2cc58f08699bf07060b8fd8f014c --- /dev/null +++ b/bsp/nuvoton/numaker-iot-m487/.config @@ -0,0 +1,747 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +CONFIG_RT_USING_SIGNALS=y + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=256 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x40002 +CONFIG_ARCH_ARM=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M4=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=2048 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=8 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 +CONFIG_DFS_FD_MAX=32 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=8 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_UFFS is not set +# CONFIG_RT_USING_DFS_JFFS2 is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=64 +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=2048 +CONFIG_RT_USING_CAN=y +# CONFIG_RT_CAN_USING_HDR is not set +CONFIG_RT_USING_HWTIMER=y +# CONFIG_RT_USING_CPUTIME is not set +CONFIG_RT_USING_I2C=y +# CONFIG_RT_I2C_DEBUG is not set +CONFIG_RT_USING_I2C_BITOPS=y +# CONFIG_RT_I2C_BITOPS_DEBUG is not set +CONFIG_RT_USING_PIN=y +CONFIG_RT_USING_ADC=y +CONFIG_RT_USING_PWM=y +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +CONFIG_RT_USING_PM=y +CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_ALARM is not set +# CONFIG_RT_USING_SOFT_RTC is not set +CONFIG_RTC_SYNC_USING_NTP=y +CONFIG_RTC_NTP_FIRST_SYNC_DELAY=30 +CONFIG_RTC_NTP_SYNC_PERIOD=3600 +# CONFIG_RT_USING_SDIO is not set +CONFIG_RT_USING_SPI=y +CONFIG_RT_USING_QSPI=y +# CONFIG_RT_USING_SPI_MSD is not set +CONFIG_RT_USING_SFUD=y +CONFIG_RT_SFUD_USING_SFDP=y +CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y +# CONFIG_RT_SFUD_USING_QSPI is not set +CONFIG_RT_SFUD_SPI_MAX_HZ=50000000 +# CONFIG_RT_DEBUG_SFUD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set +CONFIG_RT_USING_WDT=y +CONFIG_RT_USING_AUDIO=y +CONFIG_RT_AUDIO_REPLAY_MP_BLOCK_SIZE=4096 +CONFIG_RT_AUDIO_REPLAY_MP_BLOCK_COUNT=2 +CONFIG_RT_AUDIO_RECORD_PIPE_SIZE=2048 +CONFIG_RT_USING_SENSOR=y +CONFIG_RT_USING_SENSOR_CMD=y +# CONFIG_RT_USING_TOUCH is not set +CONFIG_RT_USING_HWCRYPTO=y +CONFIG_RT_HWCRYPTO_DEFAULT_NAME="hwcryto" +CONFIG_RT_HWCRYPTO_IV_MAX_SIZE=16 +CONFIG_RT_HWCRYPTO_KEYBIT_MAX_SIZE=256 +# CONFIG_RT_HWCRYPTO_USING_GCM is not set +CONFIG_RT_HWCRYPTO_USING_AES=y +CONFIG_RT_HWCRYPTO_USING_AES_ECB=y +CONFIG_RT_HWCRYPTO_USING_AES_CBC=y +CONFIG_RT_HWCRYPTO_USING_AES_CFB=y +CONFIG_RT_HWCRYPTO_USING_AES_CTR=y +CONFIG_RT_HWCRYPTO_USING_AES_OFB=y +CONFIG_RT_HWCRYPTO_USING_DES=y +CONFIG_RT_HWCRYPTO_USING_DES_ECB=y +CONFIG_RT_HWCRYPTO_USING_DES_CBC=y +CONFIG_RT_HWCRYPTO_USING_3DES=y +CONFIG_RT_HWCRYPTO_USING_3DES_ECB=y +CONFIG_RT_HWCRYPTO_USING_3DES_CBC=y +# CONFIG_RT_HWCRYPTO_USING_RC4 is not set +# CONFIG_RT_HWCRYPTO_USING_MD5 is not set +CONFIG_RT_HWCRYPTO_USING_SHA1=y +CONFIG_RT_HWCRYPTO_USING_SHA2=y +CONFIG_RT_HWCRYPTO_USING_SHA2_224=y +CONFIG_RT_HWCRYPTO_USING_SHA2_256=y +CONFIG_RT_HWCRYPTO_USING_SHA2_384=y +CONFIG_RT_HWCRYPTO_USING_SHA2_512=y +CONFIG_RT_HWCRYPTO_USING_RNG=y +CONFIG_RT_HWCRYPTO_USING_CRC=y +CONFIG_RT_HWCRYPTO_USING_CRC_07=y +CONFIG_RT_HWCRYPTO_USING_CRC_8005=y +CONFIG_RT_HWCRYPTO_USING_CRC_1021=y +# CONFIG_RT_HWCRYPTO_USING_CRC_3D65 is not set +CONFIG_RT_HWCRYPTO_USING_CRC_04C11DB7=y +# CONFIG_RT_HWCRYPTO_USING_BIGNUM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +CONFIG_RT_USING_USB_HOST=y +CONFIG_RT_USBH_MSTORAGE=y +CONFIG_UDISK_MOUNTPOINT="/mnt/udisk/" +CONFIG_RT_USING_USB_DEVICE=y +CONFIG_RT_USBD_THREAD_STACK_SZ=4096 +CONFIG_USB_VENDOR_ID=0x0FFE +CONFIG_USB_PRODUCT_ID=0x0001 +# CONFIG_RT_USB_DEVICE_COMPOSITE is not set +# CONFIG__RT_USB_DEVICE_NONE is not set +# CONFIG__RT_USB_DEVICE_CDC is not set +# CONFIG__RT_USB_DEVICE_MSTORAGE is not set +CONFIG__RT_USB_DEVICE_HID=y +# CONFIG__RT_USB_DEVICE_WINUSB is not set +# CONFIG__RT_USB_DEVICE_AUDIO is not set +CONFIG_RT_USB_DEVICE_HID=y +# CONFIG_RT_USB_DEVICE_HID_KEYBOARD is not set +CONFIG_RT_USB_DEVICE_HID_MOUSE=y +# CONFIG_RT_USB_DEVICE_HID_GENERAL is not set +# CONFIG_RT_USB_DEVICE_HID_MEDIA is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_USING_POSIX=y +# CONFIG_RT_USING_POSIX_MMAP is not set +# CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_AIO is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Network +# + +# +# Socket abstraction layer +# +CONFIG_RT_USING_SAL=y + +# +# protocol stack implement +# +CONFIG_SAL_USING_AT=y +CONFIG_SAL_USING_POSIX=y + +# +# Network interface device +# +CONFIG_RT_USING_NETDEV=y +CONFIG_NETDEV_USING_IFCONFIG=y +CONFIG_NETDEV_USING_PING=y +CONFIG_NETDEV_USING_NETSTAT=y +CONFIG_NETDEV_USING_AUTO_DEFAULT=y +# CONFIG_NETDEV_USING_IPV6 is not set +CONFIG_NETDEV_IPV4=1 +CONFIG_NETDEV_IPV6=0 +# CONFIG_NETDEV_IPV6_SCOPES is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +CONFIG_RT_USING_AT=y +# CONFIG_AT_DEBUG is not set +# CONFIG_AT_USING_SERVER is not set +CONFIG_AT_USING_CLIENT=y +CONFIG_AT_CLIENT_NUM_MAX=1 +CONFIG_AT_USING_SOCKET=y +CONFIG_AT_USING_CLI=y +# CONFIG_AT_PRINT_RAW_CMD is not set +CONFIG_AT_CMD_MAX_LEN=512 +CONFIG_AT_SW_VERSION_NUM=0x10300 + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +CONFIG_RT_USING_UTEST=y +CONFIG_UTEST_THR_STACK_SIZE=4096 +CONFIG_UTEST_THR_PRIORITY=20 +# CONFIG_RT_USING_LWP is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +CONFIG_PKG_USING_NETUTILS=y +CONFIG_PKG_NETUTILS_PATH="/packages/iot/netutils" +# CONFIG_PKG_NETUTILS_TFTP is not set +CONFIG_PKG_NETUTILS_IPERF=y +CONFIG_PKG_NETUTILS_NTP=y +CONFIG_NETUTILS_NTP_TIMEZONE=8 +CONFIG_NETUTILS_NTP_HOSTNAME="cn.ntp.org.cn" +CONFIG_NETUTILS_NTP_HOSTNAME2="ntp.rt-thread.org" +CONFIG_NETUTILS_NTP_HOSTNAME3="edu.ntp.org.cn" +# CONFIG_PKG_NETUTILS_TELNET is not set +# CONFIG_PKG_USING_NETUTILS_V110 is not set +# CONFIG_PKG_USING_NETUTILS_V100 is not set +CONFIG_PKG_USING_NETUTILS_LATEST_VERSION=y +CONFIG_PKG_NETUTILS_VER="latest" +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +CONFIG_PKG_USING_AT_DEVICE=y +CONFIG_PKG_AT_DEVICE_PATH="/packages/iot/at_device" +# CONFIG_AT_DEVICE_USING_M26 is not set +# CONFIG_AT_DEVICE_USING_EC20 is not set +# CONFIG_AT_DEVICE_USING_ESP32 is not set +CONFIG_AT_DEVICE_USING_ESP8266=y +CONFIG_AT_DEVICE_ESP8266_INIT_ASYN=y +# CONFIG_AT_DEVICE_ESP8266_SAMPLE is not set +# CONFIG_AT_DEVICE_USING_RW007 is not set +# CONFIG_AT_DEVICE_USING_SIM800C is not set +# CONFIG_AT_DEVICE_USING_SIM76XX is not set +# CONFIG_AT_DEVICE_USING_MW31 is not set +# CONFIG_AT_DEVICE_USING_W60X is not set +# CONFIG_AT_DEVICE_USING_A9G is not set +# CONFIG_AT_DEVICE_USING_BC26 is not set +# CONFIG_AT_DEVICE_USING_AIR720 is not set +# CONFIG_AT_DEVICE_USING_ME3616 is not set +# CONFIG_AT_DEVICE_USING_M6315 is not set +# CONFIG_AT_DEVICE_USING_BC28 is not set +# CONFIG_AT_DEVICE_USING_EC200X is not set +# CONFIG_AT_DEVICE_USING_N21 is not set +# CONFIG_AT_DEVICE_USING_N58 is not set +# CONFIG_PKG_USING_AT_DEVICE_V203 is not set +# CONFIG_PKG_USING_AT_DEVICE_V202 is not set +# CONFIG_PKG_USING_AT_DEVICE_V201 is not set +# CONFIG_PKG_USING_AT_DEVICE_V200 is not set +CONFIG_PKG_USING_AT_DEVICE_LATEST_VERSION=y +CONFIG_PKG_AT_DEVICE_VER="latest" +CONFIG_PKG_AT_DEVICE_VER_NUM=0x99999 +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +CONFIG_PKG_USING_WAVPLAYER=y +CONFIG_PKG_WAVPLAYER_PATH="/packages/multimedia/wavplayer" +CONFIG_PKG_WP_USING_PLAY=y +CONFIG_PKG_WP_PLAY_DEVICE="sound0" +CONFIG_PKG_WP_USING_RECORD=y +CONFIG_PKG_WP_RECORD_DEVICE="sound0" +# CONFIG_PKG_USING_WAVPLAYER_V020 is not set +CONFIG_PKG_USING_WAVPLAYER_LATEST_VERSION=y +CONFIG_PKG_WAVPLAYER_VER="latest" +# CONFIG_PKG_USING_TJPGD is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_URLENCODE is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +CONFIG_PKG_USING_FAL=y +CONFIG_PKG_FAL_PATH="/packages/system/fal" +CONFIG_FAL_DEBUG_CONFIG=y +CONFIG_FAL_DEBUG=1 +CONFIG_FAL_PART_HAS_TABLE_CFG=y +# CONFIG_FAL_USING_SFUD_PORT is not set +# CONFIG_PKG_USING_FAL_V00500 is not set +# CONFIG_PKG_USING_FAL_V00400 is not set +# CONFIG_PKG_USING_FAL_V00300 is not set +# CONFIG_PKG_USING_FAL_V00200 is not set +# CONFIG_PKG_USING_FAL_V00100 is not set +CONFIG_PKG_USING_FAL_LATEST_VERSION=y +CONFIG_PKG_FAL_VER="latest" +CONFIG_PKG_FAL_VER_NUM=0x99999 +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +CONFIG_PKG_USING_OPTPARSE=y +CONFIG_PKG_OPTPARSE_PATH="/packages/misc/optparse" +CONFIG_PKG_USING_OPTPARSE_V100=y +# CONFIG_PKG_USING_OPTPARSE_LATEST_VERSION is not set +CONFIG_PKG_OPTPARSE_VER="v1.0.0" +# CONFIG_OPTPARSE_USING_DEMO is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set + +# +# Nuvoton Packages Config +# +CONFIG_NU_PKG_USING_UTILS=y +CONFIG_NU_PKG_USING_DEMO=y +CONFIG_NU_PKG_USING_BMX055=y +# CONFIG_NU_PKG_USING_MAX31875 is not set +CONFIG_NU_PKG_USING_NAU88L25=y +# CONFIG_NU_PKG_USING_ILI9341 is not set + +# +# Hardware Drivers Config +# + +# +# On-chip Peripheral Drivers +# +CONFIG_SOC_SERIES_M480=y +# CONFIG_BSP_USE_STDDRIVER_SOURCE is not set +CONFIG_BSP_USING_PDMA=y +CONFIG_NU_PDMA_MEMFUN_ACTOR_MAX=2 +CONFIG_BSP_USING_FMC=y +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_CLK=y +CONFIG_NU_CLK_INVOKE_WKTMR=y +# CONFIG_BSP_USING_EMAC is not set +CONFIG_BSP_USING_RTC=y +# CONFIG_NU_RTC_SUPPORT_IO_RW is not set +CONFIG_NU_RTC_SUPPORT_MSH_CMD=y +# CONFIG_BSP_USING_EADC is not set +CONFIG_BSP_USING_TMR=y +# CONFIG_BSP_USING_TMR0 is not set +# CONFIG_BSP_USING_TMR1 is not set +# CONFIG_BSP_USING_TMR2 is not set +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +# CONFIG_BSP_USING_UART0_TX_DMA is not set +# CONFIG_BSP_USING_UART0_RX_DMA is not set +CONFIG_BSP_USING_UART1=y +CONFIG_BSP_USING_UART1_TX_DMA=y +CONFIG_BSP_USING_UART1_RX_DMA=y +CONFIG_BSP_USING_UART2=y +CONFIG_BSP_USING_UART2_TX_DMA=y +CONFIG_BSP_USING_UART2_RX_DMA=y +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set +# CONFIG_BSP_USING_UART5 is not set +# CONFIG_BSP_USING_UART6 is not set +# CONFIG_BSP_USING_UART7 is not set +CONFIG_BSP_USING_I2C=y +CONFIG_BSP_USING_I2C0=y +CONFIG_BSP_USING_I2C1=y +CONFIG_BSP_USING_I2C2=y +CONFIG_BSP_USING_USCI=y +CONFIG_BSP_USING_UUART=y +# CONFIG_BSP_USING_USPI_PDMA is not set +CONFIG_BSP_USING_USCI0=y +CONFIG_BSP_USING_UUART0=y +# CONFIG_BSP_USING_UI2C0 is not set +# CONFIG_BSP_USING_USPI0 is not set +CONFIG_BSP_USING_UUART0_TX_DMA=y +CONFIG_BSP_USING_UUART0_RX_DMA=y +# CONFIG_BSP_USING_USCI1 is not set +CONFIG_BSP_USING_SDH=y +CONFIG_BSP_USING_SDH0=y +# CONFIG_BSP_USING_SDH1 is not set +CONFIG_NU_SDH_USING_PDMA=y +CONFIG_NU_SDH_HOTPLUG=y +# CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_BPWM is not set +# CONFIG_BSP_USING_EPWM is not set +CONFIG_BSP_USING_SPI=y +CONFIG_BSP_USING_SPI_PDMA=y +# CONFIG_BSP_USING_SPII2S is not set +CONFIG_BSP_USING_SPI0_NONE=y +# CONFIG_BSP_USING_SPI0 is not set +# CONFIG_BSP_USING_SPII2S0 is not set +# CONFIG_BSP_USING_SPI1_NONE is not set +CONFIG_BSP_USING_SPI1=y +# CONFIG_BSP_USING_SPII2S1 is not set +CONFIG_BSP_USING_SPI1_PDMA=y +# CONFIG_BSP_USING_SPI2_NONE is not set +CONFIG_BSP_USING_SPI2=y +# CONFIG_BSP_USING_SPII2S2 is not set +# CONFIG_BSP_USING_SPI2_PDMA is not set +CONFIG_BSP_USING_SPI3_NONE=y +# CONFIG_BSP_USING_SPI3 is not set +# CONFIG_BSP_USING_SPII2S3 is not set +CONFIG_BSP_USING_I2S=y +CONFIG_NU_I2S_DMA_FIFO_SIZE=2048 +CONFIG_BSP_USING_QSPI=y +CONFIG_BSP_USING_QSPI0=y +# CONFIG_BSP_USING_QSPI0_PDMA is not set +# CONFIG_BSP_USING_QSPI1 is not set +# CONFIG_BSP_USING_SCUART is not set +# CONFIG_BSP_USING_ECAP is not set +# CONFIG_BSP_USING_QEI is not set +CONFIG_BSP_USING_CRYPTO=y +# CONFIG_NU_PRNG_USE_SEED is not set +CONFIG_BSP_USING_TRNG=y +CONFIG_BSP_USING_CRC=y +CONFIG_NU_CRC_USE_PDMA=y +# CONFIG_BSP_USING_SOFT_I2C is not set +CONFIG_BSP_USING_WDT=y +# CONFIG_BSP_USING_EBI is not set +CONFIG_BSP_USING_USBD=y +# CONFIG_BSP_USING_HSUSBD is not set +# CONFIG_BSP_USING_USBH is not set +CONFIG_BSP_USING_HSUSBH=y +# CONFIG_BSP_USING_HSOTG is not set + +# +# On-board Peripheral Drivers +# +CONFIG_BSP_USING_NULINKME=y +# CONFIG_BOARD_USING_IP101GR is not set +CONFIG_BOARD_USING_ESP8266=y +CONFIG_BOARD_USING_BMX055=y +CONFIG_BOARD_USING_NAU88L25=y +CONFIG_BOARD_USING_STORAGE_SDCARD=y +CONFIG_BOARD_USING_STORAGE_SPIFLASH=y +# CONFIG_BOARD_USING_HSUSBD is not set +# CONFIG_BOARD_USING_HSUSBD_USBH is not set +# CONFIG_BOARD_USING_HSUSBH is not set +CONFIG_BOARD_USING_HSUSBH_USBD=y +# CONFIG_BOARD_USING_HSOTG is not set + +# +# Board extended module drivers +# +# CONFIG_BOARD_USING_MAX31875 is not set +# CONFIG_BOARD_USING_LCD_ILI9341 is not set +CONFIG_BOARD_USE_UTEST=y +CONFIG_UTEST_CMD_PREFIX="bsp.nuvoton.numaker-iot-m487.test.utest." diff --git a/bsp/nuvoton/numaker-iot-m487/Kconfig b/bsp/nuvoton/numaker-iot-m487/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..5c55e87c61126df91e5422b5dedf381c30f03570 --- /dev/null +++ b/bsp/nuvoton/numaker-iot-m487/Kconfig @@ -0,0 +1,29 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +# you can change the RTT_ROOT default "../../.." to your rtthread_root, +# example : default "F:/git_repositories/rt-thread" + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +config NU_PKGS_DIR + string + option env="NU_PKGS_ROOT" + default "../libraries/nu_packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "$NU_PKGS_DIR/Kconfig" +source "$BSP_DIR/board/Kconfig" diff --git a/bsp/nuvoton/numaker-iot-m487/Nu_Link_Driver.ini b/bsp/nuvoton/numaker-iot-m487/Nu_Link_Driver.ini new file mode 100644 index 0000000000000000000000000000000000000000..a05c0574117e48227821e809e1477bdce8be7026 --- /dev/null +++ b/bsp/nuvoton/numaker-iot-m487/Nu_Link_Driver.ini @@ -0,0 +1,1019 @@ +[Version] +Nu_LinkVersion=V5.13 +[Process] +ProcessID=0x00003a80 +ProcessCreationTime_L=0xac7abbce +ProcessCreationTime_H=0x01d642ca +NuLinkID=0x77885acd +NuLinkIDs_Count=0x00000001 +NuLinkID0=0x77885acd +[ChipSelect] +;ChipName= +ChipName=M481 +[NUC505] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=NUC505_SPIFLASH.FLM +[NUC4xx] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=NUC400_AP_512.FLM +TraceConf0=0x00000002 +TraceConf1=0x014fb180 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +[NUC2xx] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NUC200_AP_128.FLM +[NUC1311] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NUC1311_AP_64.FLM +[NUC126] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x2000 +ProgramAlgorithm=NUC126_AP_256.FLM +[NUC121] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NUC121_AP_32.FLM +[NUC1xx] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NUC100_AP_128.FLM +[NUC029] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=NUC029_AP_16.FLM +[NM1820] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=NM1820_AP_17_5.FLM +[NM1810] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=NM1810_AP_29_5.FLM +[NM1500] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NM1500_AP_128.FLM +[NM1330] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NM1330_AP_64.FLM +[NM1320] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NM1320_AP_32.FLM +[NM1230] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NM1230_AP_64.FLM +[NM1200] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=NM1200_AP_8.FLM +[NM1120] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=NM1120_AP_29_5.FLM +[TF5100] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=TF5100_AP_64.FLM +[NDA102] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=NDA102_AP_29_5.FLM +[Nano103] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=Nano103_AP_64.FLM +[Nano100] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=Nano100_AP_64.FLM +[N576] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=N576_AP_145.FLM +[N575] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=N575_AP_145.FLM +[N572] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x2000 +ProgramAlgorithm=N572Fxxx.FLM +[N571] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x2000 +ProgramAlgorithm=N571E000.FLM +[N570] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=N570_AP_64.FLM +[N569] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=N569_AP_64.FLM +[N512] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=N512_AP_64.FLM +[Mini57] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=Mini57_AP_29_5.FLM +[Mini51] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=Mini51_AP_16.FLM +[M481] +Connect=2 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x00004000 +ProgramAlgorithm=M481_AP_512.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +[M480LD] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=M480LD_AP_256.FLM +[M451] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=M451_AP_256.FLM +[M251] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x2000 +ProgramAlgorithm=M251_AP_192.FLM +[M2351] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=M2351_AP_512.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +[M261] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=M261_AP_512.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +[MR63] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=MR63_AP_512.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +[M0564] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x2000 +ProgramAlgorithm=M0564_AP_256.FLM +[M0519] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=M0519_AP_128.FLM +[M0518] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=M0518_AP_64.FLM +[M05x] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=M0516_AP_64.FLM +[M031] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=M031_AP_128.FLM +Bank=0 +[NPCX] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=NPCX_AP_512.FLM +[I94000] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=I94000_AP_512.FLM +[ISD9300] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=ISD9300_AP_145.FLM +[I9200] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=I9200_AP_128.FLM +[ISD9xxx] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=ISD9100_AP_145.FLM +[ISD9000] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=ISD9000_AP_64.FLM +[AU9xxx] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=AU9100_AP_145.FLM +[General] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm= +[Autodetect] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm= +[I96000] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +Erase=2 +Program=0 +Verify=0 +ResetAndRun=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x8000 +ProgramAlgorithm= +[M030G] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +DisableTimeoutDetect=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=M030G_AP_64.FLM +[M0A21] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=M0A21_AP_32.FLM +[M2354] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Bank=0 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +CheckDPM=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=M2354_AP_1M.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +[M471] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Bank=0 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=M471_AP_512.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +[M479] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=M479_AP_256.FLM +[NM1240] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NM1240_AP_64.FLM diff --git a/bsp/nuvoton/numaker-iot-m487/README.md b/bsp/nuvoton/numaker-iot-m487/README.md new file mode 100644 index 0000000000000000000000000000000000000000..185d77cbdfdb8b6b8447acc90f6a0c24ffda4109 --- /dev/null +++ b/bsp/nuvoton/numaker-iot-m487/README.md @@ -0,0 +1,79 @@ +# NuMaker-IoT-M487 +## 1. Introduction +NuMaker-IoT-M487 provides multiple networking, interfaces, audio recording, playback functions, and flexible extended data storage. Whether you need a sensor node or a light-weight gateway, the NuMaker-IoT-M487 is an ideal choice for IoT applications. + +[![NuMaker-IoT-M487](https://i.imgur.com/VmbMjys.png "NuMaker-IoT-M487")](https://i.imgur.com/VmbMjys.png "NuMaker-IoT-M487") + +### 1.1 MCU specification + +| | Features | +| -- | -- | +| MCU | M487JIDAE | +| Operation frequency | 192MHz | +| embedded Flash size | 512kB, Dual Bank | +| SRAM size | 160kB | +| Crypto engine | DES, AES, ECC, 3DES, HMAC and SHA crypto accelerator | +| RMII interface | Support 10/100 Mbps Ethernet | + +### 1.2 Interface + +| Interface | +| -- | +| Arduino UNO | +| mikroBUS | +| NuMaker-Brick I2C | +| RJ45 Ethernet | +| USB 1.1/2.0 OTG ports | +| A microSD slot | +| A 3.5mm Audio connector | + +### 1.3 On-board devices + +| Device | Descirption | Driver supporting status | +| -- | -- | -- | +|SPI flash | W25Q32 | Supported | +|Ethernet PHY| IP101GR | Supported | +|Sensor| BMX055 | Supported | +|Wi-Fi module| ESP8266-ESP12, AT firmware v1.7 | Supported | +|Audio Codec| NAU88L25, Supports MIC and earphone | Coming soon | + +## 2. Supported compiler +Support GCC, MDK4, MDK5, IAR IDE/compilers. More information of these compiler version as following: + +| IDE/Compiler | Tested version | +| ---------- | ---------------------------- | +| MDK4 | 4.76 | +| MDK5 | 5.26.2 | +| IAR | 8.2 | +| GCC | GCC 5.4.1 20160919 (release) | + +Notice: Please install Nu-Link_Keil_Driver or Nu-Link_IAR_Driver for development. + +## 3. Program firmware +### Step 1: +At first, you need to configure ISW1 switch on the NuMaker-IOT-M487 board. Set the four switches to ‘ON’ position. After the configuration is done, connect the NuMaker-IOT-M487 board and your computer using the USB Micro cable. After that, window manager will show a ‘NuMicro MCU’ virtual disk. Finally, you will use this virtual disk to burn firmware. + +[![NuLinkMe](https://i.imgur.com/us0Fhhu.png "NuLinkMe")](https://i.imgur.com/us0Fhhu.png "NuLinkMe") + +[![NuMicro MCU](https://i.imgur.com/lWnNtpM.png "NuMicro MCU")](https://i.imgur.com/lWnNtpM.png "NuMicro MCU") + +### Step 2: +A simple firmware burning method is that you can drag and drop the binary image file to NuMicro MCU virtual disk or copy the binary file to NuMicro MCU disk to burn firmware. + +[![CopyTo](https://i.imgur.com/6NfGS7m.png "CopyTo")](https://i.imgur.com/6NfGS7m.png "CopyTo") + +## 4. Test +You can use Tera Term terminate emulator (or other software) to type commands of RTT. All parameters of serial communication are shown in below image. Here, you can find out the corresponding port number of Nuvoton Virtual Com Port in window device manager. + +[![Serial settings](https://i.imgur.com/5NYuSNM.png "Serial settings")](https://i.imgur.com/5NYuSNM.png "Serial settings") + +## 5. Purchase +* [Nuvoton Direct][1] + +## 6. Resources +* [Download board schematics][2] +* [Download MCU TRM][3] + + [1]: https://direct.nuvoton.com/en/numaker-iot-m487 + [2]: https://www.nuvoton.com/resource-download.jsp?tp_GUID=HL0320180905131830 + [3]: https://www.nuvoton.com/resource-download.jsp?tp_GUID=DA05-M480 diff --git a/bsp/nuvoton/numaker-iot-m487/SConscript b/bsp/nuvoton/numaker-iot-m487/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..fe0ae941ae9a759ae478de901caec1c961e56af8 --- /dev/null +++ b/bsp/nuvoton/numaker-iot-m487/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +Import('RTT_ROOT') + +cwd = str(Dir('#')) +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/nuvoton/numaker-iot-m487/SConstruct b/bsp/nuvoton/numaker-iot-m487/SConstruct new file mode 100644 index 0000000000000000000000000000000000000000..23d4cf0308d05ca6cf4a596f655487acb7aa8e82 --- /dev/null +++ b/bsp/nuvoton/numaker-iot-m487/SConstruct @@ -0,0 +1,59 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +nuvoton_library = 'm480' +rtconfig.BSP_LIBRARY_TYPE = nuvoton_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, nuvoton_library, 'SConscript'))) + +# include nu_pkgs +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'nu_packages', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/nuvoton/numaker-iot-m487/applications/SConscript b/bsp/nuvoton/numaker-iot-m487/applications/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..9ffdbcd0f9f63b6274eef8adca91f951a1e0fe5f --- /dev/null +++ b/bsp/nuvoton/numaker-iot-m487/applications/SConscript @@ -0,0 +1,11 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/nuvoton/numaker-iot-m487/applications/main.c b/bsp/nuvoton/numaker-iot-m487/applications/main.c new file mode 100644 index 0000000000000000000000000000000000000000..bffd9956a01eef3b7692e6b160ed35d9df98e0ba --- /dev/null +++ b/bsp/nuvoton/numaker-iot-m487/applications/main.c @@ -0,0 +1,36 @@ +/**************************************************************************//** +* +* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-1-16 Wayne First version +* +******************************************************************************/ + +#include +#include +#include + +/* defined the LEDR pin: PH0 */ +#define LEDR NU_GET_PININDEX(NU_PH, 0) + +int main(int argc, char **argv) +{ + int counter = 0; + + /* set LEDR1 pin mode to output */ + rt_pin_mode(LEDR, PIN_MODE_OUTPUT); + + while (counter++ < 10) + { + rt_pin_write(LEDR, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LEDR, PIN_LOW); + rt_thread_mdelay(500); + } + + return 0; +} diff --git a/bsp/nuvoton/numaker-iot-m487/applications/mnt.c b/bsp/nuvoton/numaker-iot-m487/applications/mnt.c new file mode 100644 index 0000000000000000000000000000000000000000..64a219379b80f984d7a587fc53bd6966eb20d48d --- /dev/null +++ b/bsp/nuvoton/numaker-iot-m487/applications/mnt.c @@ -0,0 +1,143 @@ +/**************************************************************************//** +* +* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-1-16 Wayne First version +* +******************************************************************************/ + +#include + +#if defined(RT_USING_DFS) + #include + #include +#endif + +#if defined(PKG_USING_FAL) + #include +#endif + +#if defined(BOARD_USING_STORAGE_SPIFLASH) + #define MOUNT_POINT_SPIFLASH0 "/" +#endif + +#if defined(BOARD_USING_STORAGE_SPIFLASH) + +#if defined(RT_USB_DEVICE_MSTORAGE) +int mnt_init_spiflash0(void) +{ + rt_kprintf("Sorry, you enabled RT_USB_DEVICE_MSTORAGE option in menu, so we won't mount flash0 on /.\n"); + return 0; +} +#else + +/* Recursive mkdir */ +#if defined(RT_USBH_MSTORAGE) && defined(UDISK_MOUNTPOINT) +static int mkdir_p(const char *dir, const mode_t mode) +{ + int ret = -1; + char *tmp = NULL; + char *p = NULL; + struct stat sb; + rt_size_t len; + + if (!dir) + goto exit_mkdir_p; + + /* Copy path */ + /* Get the string length */ + len = strlen(dir); + tmp = rt_strdup(dir); + + /* Remove trailing slash */ + if (tmp[len - 1] == '/') + { + tmp[len - 1] = '\0'; + len--; + } + + /* check if path exists and is a directory */ + if (stat(tmp, &sb) == 0) + { + if (S_ISDIR(sb.st_mode)) + { + ret = 0; + goto exit_mkdir_p; + } + } + + /* Recursive mkdir */ + for (p = tmp + 1; p - tmp <= len; p++) + { + if ((*p == '/') || (p - tmp == len)) + { + *p = 0; + + /* Test path */ + if (stat(tmp, &sb) != 0) + { + /* Path does not exist - create directory */ + if (mkdir(tmp, mode) < 0) + { + goto exit_mkdir_p; + } + } + else if (!S_ISDIR(sb.st_mode)) + { + /* Not a directory */ + goto exit_mkdir_p; + } + if (p - tmp != len) + *p = '/'; + } + } + + ret = 0; + +exit_mkdir_p: + + if (tmp) + rt_free(tmp); + + return ret; +} +#endif + +int mnt_init_spiflash0(void) +{ + if (dfs_mount("flash0", MOUNT_POINT_SPIFLASH0, "elm", 0, 0) != 0) + { + rt_kprintf("Failed to mount elm on %s.\n", MOUNT_POINT_SPIFLASH0); + rt_kprintf("Try to execute 'mkfs -t elm flash0' first, then reboot.\n"); + goto exit_mnt_init_spiflash0; + } + rt_kprintf("mount flash0 with elmfat type: ok\n"); + +#if defined(RT_USBH_MSTORAGE) && defined(UDISK_MOUNTPOINT) + if (mkdir_p(UDISK_MOUNTPOINT, 0) < 0) + { + rt_kprintf("Failed to create directory on %s for RT_USBH_MSTORAGE.\n", UDISK_MOUNTPOINT); + } +#endif + +exit_mnt_init_spiflash0: + + return 0; +} +#endif +INIT_ENV_EXPORT(mnt_init_spiflash0); +#endif + +#if defined(PKG_USING_FAL) +int mnt_init_fal(void) +{ + fal_init(); + return 0; +} +INIT_ENV_EXPORT(mnt_init_fal); +#endif + diff --git a/bsp/nuvoton/numaker-iot-m487/board/Kconfig b/bsp/nuvoton/numaker-iot-m487/board/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..7b2fb2683a03f0ee1347108170f80151d099ce2d --- /dev/null +++ b/bsp/nuvoton/numaker-iot-m487/board/Kconfig @@ -0,0 +1,133 @@ +menu "Hardware Drivers Config" + + menu "On-chip Peripheral Drivers" + source "$BSP_DIR/../libraries/m480/rtt_port/Kconfig" + endmenu + + menu "On-board Peripheral Drivers" + + config BSP_USING_NULINKME + bool "Enable UART0 for RTT Console(uart0)" + select BSP_USING_UART + select BSP_USING_UART0 + default y + + config BOARD_USING_IP101GR + bool "Enable ethernet phy supporting(over emac/mdio)" + select BSP_USING_EMAC + default n + + config BOARD_USING_ESP8266 + bool "ESP8266 Wi-Fi module supporting(over uart1)" + select BSP_USING_UART + select BSP_USING_UART1 + select BSP_USING_UART1_RX_DMA + select BSP_USING_UART1_TX_DMA + select PKG_USING_AT_DEVICE + select AT_DEVICE_USING_ESP8266 + select AT_DEVICE_ESP8266_INIT_ASYN + default n + + config BOARD_USING_BMX055 + bool "BMX055 9-axis sensor(over i2c2)" + select NU_PKG_USING_BMX055 + select BSP_USING_I2C2 + default n + + config BOARD_USING_NAU88L25 + bool "NAU88L25 Audio Codec supporting(over i2s, i2c2)" + select NU_PKG_USING_NAU88L25 + select BSP_USING_I2C2 + select BSP_USING_I2S + select BSP_USING_I2S0 + default n + + config BOARD_USING_STORAGE_SDCARD + bool "SDCARD supporting(over sdh0)" + select BSP_USING_SDH + select BSP_USING_SDH0 + default n + + config BOARD_USING_STORAGE_SPIFLASH + bool "SPIFLASH supporting(over qspi0)" + select BSP_USING_QSPI + select BSP_USING_QSPI0 + default y + + choice + prompt "Select FS/HS USB Ports" + + config BOARD_USING_HSUSBD + select BSP_USING_HSUSBD + bool "Enable HSUSBD(over USB2.0)" + help + Choose this option if you need HSUSBD function mode. + + config BOARD_USING_HSUSBD_USBH + select BSP_USING_USBH + select BSP_USING_HSUSBD + bool "Enable HSUSBD(over USB2.0) and USBH(over USB1.1)" + help + Choose this option if you need HSUSBD and USBH function mode at the same time. + + config BOARD_USING_HSUSBH + select BSP_USING_HSUSBH + bool "Enable HSUSBH(over USB2.0)" + help + Choose this option if you need HSUSBH function mode. + + config BOARD_USING_HSUSBH_USBD + select BSP_USING_HSUSBH + select BSP_USING_USBD + bool "Enable HSUSBH(over USB2.0) and USBD(over USB1.1)" + help + Choose this option if you need HSUSBH and USBD function mode at the same time. + + config BOARD_USING_HSOTG + select BSP_USING_HSOTG + bool "Enable HSOTG(over USB2.0)" + help + Choose this option if you need HSOTG function mode. + + endchoice + + endmenu + + menu "Board extended module drivers" + + config BOARD_USING_MAX31875 + bool "MAX31875 Temperature sensor(over i2c1)" + select NU_PKG_USING_MAX31875 + select BSP_USING_I2C1 + default n + + config BOARD_USING_LCD_ILI9341 + bool "LCD ILI9341 (over spi2)" + select NU_PKG_USING_ILI9341 + select NU_PKG_USING_ILI9341_SPI + select BSP_USING_SPI2 + default n + + if BOARD_USING_LCD_ILI9341 + + config BOARD_USING_ILI9341_PIN_BACKLIGHT + int "Specify the pin index of backlight pin index" + range 0 127 + default 69 + + config BOARD_USING_ILI9341_PIN_RESET + int "Specify the pin index of reset pin index" + range 0 127 + default 19 + + config BOARD_USING_ILI9341_PIN_DC + int "Specify the pin index of data&command switching" + range 0 127 + default 18 + + endif + + endmenu + + +endmenu diff --git a/bsp/nuvoton/numaker-iot-m487/board/NuClockConfig/nutool_clkcfg.h b/bsp/nuvoton/numaker-iot-m487/board/NuClockConfig/nutool_clkcfg.h new file mode 100644 index 0000000000000000000000000000000000000000..950b09946e24237cd387a6e19ff8439707aeb07f --- /dev/null +++ b/bsp/nuvoton/numaker-iot-m487/board/NuClockConfig/nutool_clkcfg.h @@ -0,0 +1,26 @@ +/**************************************************************************** + * @file nutool_clkcfg.h + * @version V1.05 + * @Date 2020/04/15-11:28:38 + * @brief NuMicro generated code file + * + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#ifndef __NUTOOL_CLKCFG_H__ +#define __NUTOOL_CLKCFG_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif +#undef __HXT +#define __HXT (12000000UL) /*!< High Speed External Crystal Clock Frequency */ + +#ifdef __cplusplus +} +#endif +#endif /*__NUTOOL_CLKCFG_H__*/ + +/*** (C) COPYRIGHT 2013-2020 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/numaker-iot-m487/board/NuClockConfig/nutool_modclkcfg.c b/bsp/nuvoton/numaker-iot-m487/board/NuClockConfig/nutool_modclkcfg.c new file mode 100644 index 0000000000000000000000000000000000000000..59af4901f984104a810d91666c33bb421932efd2 --- /dev/null +++ b/bsp/nuvoton/numaker-iot-m487/board/NuClockConfig/nutool_modclkcfg.c @@ -0,0 +1,1153 @@ +/**************************************************************************** + * @file nutool_modclkcfg.c + * @version V1.05 + * @Date 2020/04/15-11:28:38 + * @brief NuMicro generated code file + * + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +/******************** +MCU:M487JIDAE(LQFP144) +Base Clocks: +HIRC:12MHz +LXT:32.7680kHz +HXT:12MHz +PLL:192MHz +HSUSB_OTG_PHY:30MHz +HCLK:192MHz +PCLK0:96MHz +PCLK1:96MHz +Enabled-Module Frequencies: +ACMP01=Bus Clock(PCLK1):96MHz +BPWM0=Bus Clock(PCLK0):96MHz/Engine Clock:96MHz +BPWM1=Bus Clock(PCLK1):96MHz/Engine Clock:96MHz +CAN0=Bus Clock(PCLK0):96MHz +CAN1=Bus Clock(PCLK1):96MHz +CRC=Bus Clock(HCLK):192MHz +CRPT=Bus Clock(HCLK):192MHz +DAC=Bus Clock(PCLK1):96MHz +EADC=Bus Clock(PCLK1):96MHz/Engine Clock:12MHz +EBI=Bus Clock(HCLK):192MHz +ECAP0=Bus Clock(PCLK0):96MHz +ECAP1=Bus Clock(PCLK1):96MHz +EMAC=Bus Clock(HCLK):192MHz/Engine Clock:1.5118MHz +EPWM0=Bus Clock(PCLK0):96MHz/Engine Clock:96MHz +EPWM1=Bus Clock(PCLK1):96MHz/Engine Clock:96MHz +FMCIDLE=Bus Clock(HCLK):192MHz/Engine Clock:12MHz +HSOTG=Bus Clock(PCLK1):96MHz/Engine Clock:30MHz +HSUSBD=Bus Clock(HCLK):192MHz/Engine Clock:30MHz +HSUSBH=Bus Clock(HCLK):192MHz/Engine Clock:30MHz +I2C0=Bus Clock(PCLK0):96MHz +I2C1=Bus Clock(PCLK1):96MHz +I2C2=Bus Clock(PCLK0):96MHz +I2S0=Bus Clock(PCLK0):96MHz/Engine Clock:12MHz +ISP=Bus Clock(HCLK):192MHz/Engine Clock:12MHz +OPA=Bus Clock(PCLK0):96MHz +OTG=Bus Clock(PCLK1):96MHz/Engine Clock:192MHz +PDMA=Bus Clock(HCLK):192MHz +QEI0=Bus Clock(PCLK0):96MHz +QEI1=Bus Clock(PCLK1):96MHz +QSPI0=Bus Clock(PCLK0):96MHz/Engine Clock:96MHz +RTC=Bus Clock(PCLK1):96MHz/Engine Clock:32.7680kHz +SC0=Bus Clock(PCLK0):96MHz/Engine Clock:12MHz +SC1=Bus Clock(PCLK1):96MHz/Engine Clock:12MHz +SC2=Bus Clock(PCLK0):96MHz/Engine Clock:12MHz +SDH0=Bus Clock(HCLK):192MHz/Engine Clock:192MHz +SDH1=Bus Clock(HCLK):192MHz/Engine Clock:192MHz +SPI0=Bus Clock(PCLK1):96MHz/Engine Clock:96MHz +SPI1=Bus Clock(PCLK0):96MHz/Engine Clock:96MHz +SPI2=Bus Clock(PCLK1):96MHz/Engine Clock:96MHz +SPI3=Bus Clock(PCLK0):96MHz/Engine Clock:96MHz +SPIM=Bus Clock(HCLK):192MHz +SYSTICK=Bus Clock(HCLK):192MHz/Engine Clock:192MHz +TMR0=Bus Clock(PCLK0):96MHz/Engine Clock:12MHz +TMR1=Bus Clock(PCLK0):96MHz/Engine Clock:12MHz +TMR2=Bus Clock(PCLK1):96MHz/Engine Clock:12MHz +TMR3=Bus Clock(PCLK1):96MHz/Engine Clock:12MHz +UART0=Bus Clock(PCLK0):96MHz/Engine Clock:12MHz +UART1=Bus Clock(PCLK1):96MHz/Engine Clock:12MHz +UART2=Bus Clock(PCLK0):96MHz/Engine Clock:12MHz +UART3=Bus Clock(PCLK1):96MHz/Engine Clock:12MHz +UART4=Bus Clock(PCLK0):96MHz/Engine Clock:12MHz +UART5=Bus Clock(PCLK1):96MHz/Engine Clock:12MHz +USBD=Bus Clock(PCLK0):96MHz/Engine Clock:48MHz +USBH=Bus Clock(HCLK):192MHz/Engine Clock:48MHz +USCI0=Bus Clock(PCLK0):96MHz +USCI1=Bus Clock(PCLK1):96MHz +WDT=Bus Clock(PCLK0):96MHz/Engine Clock:32.7680kHz +WWDT=Bus Clock(PCLK0):96MHz/Engine Clock:93.7500kHz +********************/ + +#include "M480.h" +#include "rtconfig.h" + +void nutool_modclkcfg_init_acmp01(void) +{ + CLK_EnableModuleClock(ACMP01_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_acmp01(void) +{ + CLK_DisableModuleClock(ACMP01_MODULE); + + return; +} + +void nutool_modclkcfg_init_bpwm0(void) +{ + CLK_EnableModuleClock(BPWM0_MODULE); + CLK_SetModuleClock(BPWM0_MODULE, CLK_CLKSEL2_BPWM0SEL_PCLK0, MODULE_NoMsk); + + return; +} + +void nutool_modclkcfg_deinit_bpwm0(void) +{ + CLK_DisableModuleClock(BPWM0_MODULE); + + return; +} + +void nutool_modclkcfg_init_bpwm1(void) +{ + CLK_EnableModuleClock(BPWM1_MODULE); + CLK_SetModuleClock(BPWM1_MODULE, CLK_CLKSEL2_BPWM1SEL_PCLK1, MODULE_NoMsk); + + return; +} + +void nutool_modclkcfg_deinit_bpwm1(void) +{ + CLK_DisableModuleClock(BPWM1_MODULE); + + return; +} + +void nutool_modclkcfg_init_can0(void) +{ + CLK_EnableModuleClock(CAN0_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_can0(void) +{ + CLK_DisableModuleClock(CAN0_MODULE); + + return; +} + +void nutool_modclkcfg_init_can1(void) +{ + CLK_EnableModuleClock(CAN1_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_can1(void) +{ + CLK_DisableModuleClock(CAN1_MODULE); + + return; +} + +void nutool_modclkcfg_init_crc(void) +{ + CLK_EnableModuleClock(CRC_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_crc(void) +{ + CLK_DisableModuleClock(CRC_MODULE); + + return; +} + +void nutool_modclkcfg_init_crpt(void) +{ + CLK_EnableModuleClock(CRPT_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_crpt(void) +{ + CLK_DisableModuleClock(CRPT_MODULE); + + return; +} + +void nutool_modclkcfg_init_dac(void) +{ + CLK_EnableModuleClock(DAC_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_dac(void) +{ + CLK_DisableModuleClock(DAC_MODULE); + + return; +} + +void nutool_modclkcfg_init_eadc(void) +{ + CLK_EnableModuleClock(EADC_MODULE); + CLK_SetModuleClock(EADC_MODULE, MODULE_NoMsk, CLK_CLKDIV0_EADC(8)); + + return; +} + +void nutool_modclkcfg_deinit_eadc(void) +{ + CLK_DisableModuleClock(EADC_MODULE); + + return; +} + +void nutool_modclkcfg_init_ebi(void) +{ + CLK_EnableModuleClock(EBI_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_ebi(void) +{ + CLK_DisableModuleClock(EBI_MODULE); + + return; +} + +void nutool_modclkcfg_init_ecap0(void) +{ + CLK_EnableModuleClock(ECAP0_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_ecap0(void) +{ + CLK_DisableModuleClock(ECAP0_MODULE); + + return; +} + +void nutool_modclkcfg_init_ecap1(void) +{ + CLK_EnableModuleClock(ECAP1_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_ecap1(void) +{ + CLK_DisableModuleClock(ECAP1_MODULE); + + return; +} + +void nutool_modclkcfg_init_emac(void) +{ + CLK_EnableModuleClock(EMAC_MODULE); + CLK_SetModuleClock(EMAC_MODULE, MODULE_NoMsk, CLK_CLKDIV3_EMAC(127)); + + return; +} + +void nutool_modclkcfg_deinit_emac(void) +{ + CLK_DisableModuleClock(EMAC_MODULE); + + return; +} + +void nutool_modclkcfg_init_epwm0(void) +{ + CLK_EnableModuleClock(EPWM0_MODULE); + CLK_SetModuleClock(EPWM0_MODULE, CLK_CLKSEL2_EPWM0SEL_PCLK0, MODULE_NoMsk); + + return; +} + +void nutool_modclkcfg_deinit_epwm0(void) +{ + CLK_DisableModuleClock(EPWM0_MODULE); + + return; +} + +void nutool_modclkcfg_init_epwm1(void) +{ + CLK_EnableModuleClock(EPWM1_MODULE); + CLK_SetModuleClock(EPWM1_MODULE, CLK_CLKSEL2_EPWM1SEL_PCLK1, MODULE_NoMsk); + + return; +} + +void nutool_modclkcfg_deinit_epwm1(void) +{ + CLK_DisableModuleClock(EPWM1_MODULE); + + return; +} + +void nutool_modclkcfg_init_fmcidle(void) +{ + CLK_EnableModuleClock(FMCIDLE_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_fmcidle(void) +{ + CLK_DisableModuleClock(FMCIDLE_MODULE); + + return; +} + +void nutool_modclkcfg_init_hsotg(void) +{ + CLK_EnableModuleClock(HSOTG_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_hsotg(void) +{ + CLK_DisableModuleClock(HSOTG_MODULE); + + return; +} + +void nutool_modclkcfg_init_hsusbd(void) +{ + CLK_EnableModuleClock(HSUSBD_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_hsusbd(void) +{ + CLK_DisableModuleClock(HSUSBD_MODULE); + + return; +} + +void nutool_modclkcfg_init_i2c0(void) +{ + CLK_EnableModuleClock(I2C0_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_i2c0(void) +{ + CLK_DisableModuleClock(I2C0_MODULE); + + return; +} + +void nutool_modclkcfg_init_i2c1(void) +{ + CLK_EnableModuleClock(I2C1_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_i2c1(void) +{ + CLK_DisableModuleClock(I2C1_MODULE); + + return; +} + +void nutool_modclkcfg_init_i2c2(void) +{ + CLK_EnableModuleClock(I2C2_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_i2c2(void) +{ + CLK_DisableModuleClock(I2C2_MODULE); + + return; +} + +void nutool_modclkcfg_init_i2s0(void) +{ + CLK_EnableModuleClock(I2S0_MODULE); + CLK_SetModuleClock(I2S0_MODULE, CLK_CLKSEL3_I2S0SEL_HXT, MODULE_NoMsk); + + return; +} + +void nutool_modclkcfg_deinit_i2s0(void) +{ + CLK_DisableModuleClock(I2S0_MODULE); + + return; +} + +void nutool_modclkcfg_init_isp(void) +{ + CLK_EnableModuleClock(ISP_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_isp(void) +{ + CLK_DisableModuleClock(ISP_MODULE); + + return; +} + +void nutool_modclkcfg_init_opa(void) +{ + CLK_EnableModuleClock(OPA_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_opa(void) +{ + CLK_DisableModuleClock(OPA_MODULE); + + return; +} + +void nutool_modclkcfg_init_otg(void) +{ + CLK_EnableModuleClock(OTG_MODULE); + CLK_SetModuleClock(OTG_MODULE, MODULE_NoMsk, CLK_CLKDIV0_USB(1)); + + return; +} + +void nutool_modclkcfg_deinit_otg(void) +{ + CLK_DisableModuleClock(OTG_MODULE); + + return; +} + +void nutool_modclkcfg_init_pdma(void) +{ + CLK_EnableModuleClock(PDMA_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_pdma(void) +{ + CLK_DisableModuleClock(PDMA_MODULE); + + return; +} + +void nutool_modclkcfg_init_qei0(void) +{ + CLK_EnableModuleClock(QEI0_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_qei0(void) +{ + CLK_DisableModuleClock(QEI0_MODULE); + + return; +} + +void nutool_modclkcfg_init_qei1(void) +{ + CLK_EnableModuleClock(QEI1_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_qei1(void) +{ + CLK_DisableModuleClock(QEI1_MODULE); + + return; +} + +void nutool_modclkcfg_init_qspi0(void) +{ + CLK_EnableModuleClock(QSPI0_MODULE); + CLK_SetModuleClock(QSPI0_MODULE, CLK_CLKSEL2_QSPI0SEL_PCLK0, MODULE_NoMsk); + + return; +} + +void nutool_modclkcfg_deinit_qspi0(void) +{ + CLK_DisableModuleClock(QSPI0_MODULE); + + return; +} + +void nutool_modclkcfg_init_rtc(void) +{ + CLK_EnableModuleClock(RTC_MODULE); + CLK_SetModuleClock(RTC_MODULE, CLK_CLKSEL3_RTCSEL_LXT, MODULE_NoMsk); + + return; +} + +void nutool_modclkcfg_deinit_rtc(void) +{ + CLK_DisableModuleClock(RTC_MODULE); + + return; +} + +void nutool_modclkcfg_init_sc0(void) +{ + CLK_EnableModuleClock(SC0_MODULE); + CLK_SetModuleClock(SC0_MODULE, CLK_CLKSEL3_SC0SEL_HXT, CLK_CLKDIV1_SC0(1)); + + return; +} + +void nutool_modclkcfg_deinit_sc0(void) +{ + CLK_DisableModuleClock(SC0_MODULE); + + return; +} + +void nutool_modclkcfg_init_sc1(void) +{ + CLK_EnableModuleClock(SC1_MODULE); + CLK_SetModuleClock(SC1_MODULE, CLK_CLKSEL3_SC1SEL_HXT, CLK_CLKDIV1_SC1(1)); + + return; +} + +void nutool_modclkcfg_deinit_sc1(void) +{ + CLK_DisableModuleClock(SC1_MODULE); + + return; +} + +void nutool_modclkcfg_init_sc2(void) +{ + CLK_EnableModuleClock(SC2_MODULE); + CLK_SetModuleClock(SC2_MODULE, CLK_CLKSEL3_SC2SEL_HXT, CLK_CLKDIV1_SC2(1)); + + return; +} + +void nutool_modclkcfg_deinit_sc2(void) +{ + CLK_DisableModuleClock(SC2_MODULE); + + return; +} + +void nutool_modclkcfg_init_sdh0(void) +{ + CLK_EnableModuleClock(SDH0_MODULE); + CLK_SetModuleClock(SDH0_MODULE, CLK_CLKSEL0_SDH0SEL_HCLK, CLK_CLKDIV0_SDH0(1)); + + return; +} + +void nutool_modclkcfg_deinit_sdh0(void) +{ + CLK_DisableModuleClock(SDH0_MODULE); + + return; +} + +void nutool_modclkcfg_init_sdh1(void) +{ + CLK_EnableModuleClock(SDH1_MODULE); + CLK_SetModuleClock(SDH1_MODULE, CLK_CLKSEL0_SDH1SEL_HCLK, CLK_CLKDIV3_SDH1(1)); + + return; +} + +void nutool_modclkcfg_deinit_sdh1(void) +{ + CLK_DisableModuleClock(SDH1_MODULE); + + return; +} + +void nutool_modclkcfg_init_spi0(void) +{ + CLK_EnableModuleClock(SPI0_MODULE); + CLK_SetModuleClock(SPI0_MODULE, CLK_CLKSEL2_SPI0SEL_PCLK1, MODULE_NoMsk); + + return; +} + +void nutool_modclkcfg_deinit_spi0(void) +{ + CLK_DisableModuleClock(SPI0_MODULE); + + return; +} + +void nutool_modclkcfg_init_spi1(void) +{ + CLK_EnableModuleClock(SPI1_MODULE); + CLK_SetModuleClock(SPI1_MODULE, CLK_CLKSEL2_SPI1SEL_PCLK0, MODULE_NoMsk); + + return; +} + +void nutool_modclkcfg_deinit_spi1(void) +{ + CLK_DisableModuleClock(SPI1_MODULE); + + return; +} + +void nutool_modclkcfg_init_spi2(void) +{ + CLK_EnableModuleClock(SPI2_MODULE); + CLK_SetModuleClock(SPI2_MODULE, CLK_CLKSEL2_SPI2SEL_PCLK1, MODULE_NoMsk); + + return; +} + +void nutool_modclkcfg_deinit_spi2(void) +{ + CLK_DisableModuleClock(SPI2_MODULE); + + return; +} + +void nutool_modclkcfg_init_spi3(void) +{ + CLK_EnableModuleClock(SPI3_MODULE); + CLK_SetModuleClock(SPI3_MODULE, CLK_CLKSEL2_SPI3SEL_PCLK0, MODULE_NoMsk); + + return; +} + +void nutool_modclkcfg_deinit_spi3(void) +{ + CLK_DisableModuleClock(SPI3_MODULE); + + return; +} + +void nutool_modclkcfg_init_spim(void) +{ + CLK_EnableModuleClock(SPIM_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_spim(void) +{ + CLK_DisableModuleClock(SPIM_MODULE); + + return; +} + +void nutool_modclkcfg_init_systick(void) +{ + CLK_EnableSysTick(CLK_CLKSEL0_STCLKSEL_HCLK, 0); + + return; +} + +void nutool_modclkcfg_deinit_systick(void) +{ + CLK_DisableSysTick(); + + return; +} + +void nutool_modclkcfg_init_tmr0(void) +{ + CLK_EnableModuleClock(TMR0_MODULE); + CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_HXT, MODULE_NoMsk); + + return; +} + +void nutool_modclkcfg_deinit_tmr0(void) +{ + CLK_DisableModuleClock(TMR0_MODULE); + + return; +} + +void nutool_modclkcfg_init_tmr1(void) +{ + CLK_EnableModuleClock(TMR1_MODULE); + CLK_SetModuleClock(TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_HXT, MODULE_NoMsk); + + return; +} + +void nutool_modclkcfg_deinit_tmr1(void) +{ + CLK_DisableModuleClock(TMR1_MODULE); + + return; +} + +void nutool_modclkcfg_init_tmr2(void) +{ + CLK_EnableModuleClock(TMR2_MODULE); + CLK_SetModuleClock(TMR2_MODULE, CLK_CLKSEL1_TMR2SEL_HXT, MODULE_NoMsk); + + return; +} + +void nutool_modclkcfg_deinit_tmr2(void) +{ + CLK_DisableModuleClock(TMR2_MODULE); + + return; +} + +void nutool_modclkcfg_init_tmr3(void) +{ + CLK_EnableModuleClock(TMR3_MODULE); + CLK_SetModuleClock(TMR3_MODULE, CLK_CLKSEL1_TMR3SEL_HXT, MODULE_NoMsk); + + return; +} + +void nutool_modclkcfg_deinit_tmr3(void) +{ + CLK_DisableModuleClock(TMR3_MODULE); + + return; +} + +void nutool_modclkcfg_init_uart0(void) +{ + CLK_EnableModuleClock(UART0_MODULE); + CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART0SEL_HXT, CLK_CLKDIV0_UART0(1)); + + return; +} + +void nutool_modclkcfg_deinit_uart0(void) +{ + CLK_DisableModuleClock(UART0_MODULE); + + return; +} + +void nutool_modclkcfg_init_uart1(void) +{ + CLK_EnableModuleClock(UART1_MODULE); + CLK_SetModuleClock(UART1_MODULE, CLK_CLKSEL1_UART1SEL_HXT, CLK_CLKDIV0_UART1(1)); + + return; +} + +void nutool_modclkcfg_deinit_uart1(void) +{ + CLK_DisableModuleClock(UART1_MODULE); + + return; +} + +void nutool_modclkcfg_init_uart2(void) +{ + CLK_EnableModuleClock(UART2_MODULE); + CLK_SetModuleClock(UART2_MODULE, CLK_CLKSEL3_UART2SEL_HXT, CLK_CLKDIV4_UART2(1)); + + return; +} + +void nutool_modclkcfg_deinit_uart2(void) +{ + CLK_DisableModuleClock(UART2_MODULE); + + return; +} + +void nutool_modclkcfg_init_uart3(void) +{ + CLK_EnableModuleClock(UART3_MODULE); + CLK_SetModuleClock(UART3_MODULE, CLK_CLKSEL3_UART3SEL_HXT, CLK_CLKDIV4_UART3(1)); + + return; +} + +void nutool_modclkcfg_deinit_uart3(void) +{ + CLK_DisableModuleClock(UART3_MODULE); + + return; +} + +void nutool_modclkcfg_init_uart4(void) +{ + CLK_EnableModuleClock(UART4_MODULE); + CLK_SetModuleClock(UART4_MODULE, CLK_CLKSEL3_UART4SEL_HXT, CLK_CLKDIV4_UART4(1)); + + return; +} + +void nutool_modclkcfg_deinit_uart4(void) +{ + CLK_DisableModuleClock(UART4_MODULE); + + return; +} + +void nutool_modclkcfg_init_uart5(void) +{ + CLK_EnableModuleClock(UART5_MODULE); + CLK_SetModuleClock(UART5_MODULE, CLK_CLKSEL3_UART5SEL_HXT, CLK_CLKDIV4_UART5(1)); + + return; +} + +void nutool_modclkcfg_deinit_uart5(void) +{ + CLK_DisableModuleClock(UART5_MODULE); + + return; +} + +void nutool_modclkcfg_init_usbd(void) +{ + CLK_EnableModuleClock(USBD_MODULE); + CLK_SetModuleClock(USBD_MODULE, CLK_CLKSEL0_USBSEL_PLL, CLK_CLKDIV0_USB(4)); + + return; +} + +void nutool_modclkcfg_deinit_usbd(void) +{ + CLK_DisableModuleClock(USBD_MODULE); + + return; +} + +void nutool_modclkcfg_init_usbh(void) +{ + CLK_EnableModuleClock(USBH_MODULE); + CLK_SetModuleClock(USBH_MODULE, CLK_CLKSEL0_USBSEL_PLL, CLK_CLKDIV0_USB(4)); + + return; +} + +void nutool_modclkcfg_deinit_usbh(void) +{ + CLK_DisableModuleClock(USBH_MODULE); + + return; +} + +void nutool_modclkcfg_init_usci0(void) +{ + CLK_EnableModuleClock(USCI0_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_usci0(void) +{ + CLK_DisableModuleClock(USCI0_MODULE); + + return; +} + +void nutool_modclkcfg_init_usci1(void) +{ + CLK_EnableModuleClock(USCI1_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_usci1(void) +{ + CLK_DisableModuleClock(USCI1_MODULE); + + return; +} + +void nutool_modclkcfg_init_wdt(void) +{ + CLK_EnableModuleClock(WDT_MODULE); + CLK_SetModuleClock(WDT_MODULE, CLK_CLKSEL1_WDTSEL_LXT, MODULE_NoMsk); + + return; +} + +void nutool_modclkcfg_deinit_wdt(void) +{ + CLK_DisableModuleClock(WDT_MODULE); + + return; +} + +void nutool_modclkcfg_init_wwdt(void) +{ + CLK_EnableModuleClock(WWDT_MODULE); + CLK_SetModuleClock(WWDT_MODULE, CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048, MODULE_NoMsk); + + return; +} + +void nutool_modclkcfg_deinit_wwdt(void) +{ + CLK_DisableModuleClock(WWDT_MODULE); + + return; +} + +void nutool_modclkcfg_init_base(void) +{ + /* Set XT1_OUT(PF.2) and XT1_IN(PF.3) to input mode */ + PF->MODE &= ~(GPIO_MODE_MODE2_Msk | GPIO_MODE_MODE3_Msk); + + /* Enable clock source */ + CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk | CLK_PWRCTL_LXTEN_Msk | CLK_PWRCTL_HXTEN_Msk); + + /* Waiting for clock source ready */ + CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk | CLK_STATUS_LXTSTB_Msk | CLK_STATUS_HXTSTB_Msk); + + /* Disable PLL first to avoid unstable when setting PLL */ + CLK_DisablePLL(); + + /* Set PLL frequency */ + CLK->PLLCTL = (CLK->PLLCTL & ~(0x000FFFFFul)) | 0x0000421Eul; + + /* Waiting for PLL ready */ + CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk); + + /* If the defines do not exist in your project, please refer to the related clk.h in the Header folder appended to the tool package. */ + /* Set HCLK clock */ + CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL, CLK_CLKDIV0_HCLK(1)); + + /* Set PCLK-related clock */ + CLK->PCLKDIV = (CLK_PCLKDIV_PCLK0DIV2 | CLK_PCLKDIV_PCLK1DIV2); + + return; +} + +void nutool_modclkcfg_init(void) +{ + /*---------------------------------------------------------------------------------------------------------*/ + /* Init System Clock */ + /*---------------------------------------------------------------------------------------------------------*/ + //CLK->PWRCTL = (CLK->PWRCTL & ~(0x0000000Ful)) | 0x00000017ul; + //CLK->PLLCTL = (CLK->PLLCTL & ~(0x000FFFFFul)) | 0x0000421Eul; + //CLK->CLKDIV0 = (CLK->CLKDIV0 & ~(0xFFFFFFFFul)) | 0x00070000ul; + //CLK->CLKDIV1 = (CLK->CLKDIV1 & ~(0x00FFFFFFul)) | 0x00000000ul; + //CLK->CLKDIV3 = (CLK->CLKDIV3 & ~(0xFFFF0000ul)) | 0x007E0000ul; + //CLK->CLKDIV4 = (CLK->CLKDIV4 & ~(0x0000FFFFul)) | 0x00000000ul; + //CLK->PCLKDIV = (CLK->PCLKDIV & ~(0x00000077ul)) | 0x00000011ul; + //CLK->CLKSEL0 = (CLK->CLKSEL0 & ~(0x00F0003Ful)) | 0x00A30102ul; + //CLK->CLKSEL1 = (CLK->CLKSEL1 & ~(0xFF777703ul)) | 0xB0000001ul; + //CLK->CLKSEL2 = (CLK->CLKSEL2 & ~(0x00003FFFul)) | 0x00002BABul; + //CLK->CLKSEL3 = (CLK->CLKSEL3 & ~(0xFF03023Ful)) | 0x00000000ul; + //CLK->AHBCLK = (CLK->AHBCLK & ~(0x0003D4EEul)) | 0x0003D4EEul; + //CLK->APBCLK0 = (CLK->APBCLK0 & ~(0x7F3FF7FFul)) | 0x7F3FF7BFul; + //CLK->APBCLK1 = (CLK->APBCLK1 & ~(0x4CCF1347ul)) | 0x4CCF1347ul; + //CLK->CLKOCTL = (CLK->CLKOCTL & ~(0x0000007Ful)) | 0x00000000ul; + //SysTick->CTRL = (SysTick->CTRL & ~(0x00000005ul)) | 0x00000005ul; + + /* Unlock protected registers */ + SYS_UnlockReg(); + + /* Enable base clock */ + nutool_modclkcfg_init_base(); + + /* Enable module clock and set clock source */ +#if defined(BSP_USING_ACMP01) + nutool_modclkcfg_init_acmp01(); +#endif +#if defined(BSP_USING_BPWM0) + nutool_modclkcfg_init_bpwm0(); +#endif +#if defined(BSP_USING_BPWM1) + nutool_modclkcfg_init_bpwm1(); +#endif +#if defined(BSP_USING_CAN0) + nutool_modclkcfg_init_can0(); +#endif +#if defined(BSP_USING_CAN1) + nutool_modclkcfg_init_can1(); +#endif +#if defined(BSP_USING_CRC) + nutool_modclkcfg_init_crc(); +#endif +#if defined(BSP_USING_CRYPTO) + nutool_modclkcfg_init_crpt(); +#endif +#if defined(BSP_USING_DAC) + nutool_modclkcfg_init_dac(); +#endif +#if defined(BSP_USING_EADC) + nutool_modclkcfg_init_eadc(); +#endif +#if defined(BSP_USING_EBI) + nutool_modclkcfg_init_ebi(); +#endif +#if defined(BSP_USING_ECAP0) + nutool_modclkcfg_init_ecap0(); +#endif +#if defined(BSP_USING_ECAP1) + nutool_modclkcfg_init_ecap1(); +#endif +#if defined(BSP_USING_EMAC) + nutool_modclkcfg_init_emac(); +#endif +#if defined(BSP_USING_EPWM0) + nutool_modclkcfg_init_epwm0(); +#endif +#if defined(BSP_USING_EPWM1) + nutool_modclkcfg_init_epwm1(); +#endif +#if defined(BSP_USING_FMC) + nutool_modclkcfg_init_fmcidle(); +#endif +#if defined(BSP_USING_HSOTG) + nutool_modclkcfg_init_hsotg(); +#endif +#if defined(BSP_USING_HSUSBD) + nutool_modclkcfg_init_hsusbd(); +#endif +#if defined(BSP_USING_I2C0) + nutool_modclkcfg_init_i2c0(); +#endif +#if defined(BSP_USING_I2C1) + nutool_modclkcfg_init_i2c1(); +#endif +#if defined(BSP_USING_I2C2) + nutool_modclkcfg_init_i2c2(); +#endif +#if defined(BSP_USING_I2S) + nutool_modclkcfg_init_i2s0(); +#endif +#if defined(BSP_USING_FMC) + nutool_modclkcfg_init_isp(); +#endif +#if defined(BSP_USING_OPA) + nutool_modclkcfg_init_opa(); +#endif +#if defined(BSP_USING_OTG) || defined(BSP_USING_USBH) + nutool_modclkcfg_init_otg(); +#endif +#if defined(BSP_USING_PDMA) + nutool_modclkcfg_init_pdma(); +#endif +#if defined(BSP_USING_QEI0) + nutool_modclkcfg_init_qei0(); +#endif +#if defined(BSP_USING_QEI1) + nutool_modclkcfg_init_qei1(); +#endif +#if defined(BSP_USING_QSPI0) + nutool_modclkcfg_init_qspi0(); +#endif +#if defined(BSP_USING_RTC) + nutool_modclkcfg_init_rtc(); +#endif +#if defined(BSP_USING_SCUART0) + nutool_modclkcfg_init_sc0(); +#endif +#if defined(BSP_USING_SCUART1) + nutool_modclkcfg_init_sc1(); +#endif +#if defined(BSP_USING_SCUART2) + nutool_modclkcfg_init_sc2(); +#endif +#if defined(BSP_USING_SDH0) + nutool_modclkcfg_init_sdh0(); +#endif +#if defined(BSP_USING_SDH1) + nutool_modclkcfg_init_sdh1(); +#endif +#if defined(BSP_USING_SPI0) || defined(BSP_USING_SPII2S0) + nutool_modclkcfg_init_spi0(); +#endif +#if defined(BSP_USING_SPI1) || defined(BSP_USING_SPII2S1) + nutool_modclkcfg_init_spi1(); +#endif +#if defined(BSP_USING_SPI2) || defined(BSP_USING_SPII2S2) + nutool_modclkcfg_init_spi2(); +#endif +#if defined(BSP_USING_SPI3) || defined(BSP_USING_SPII2S3) + nutool_modclkcfg_init_spi3(); +#endif + nutool_modclkcfg_init_systick(); +#if defined(BSP_USING_TMR0) + nutool_modclkcfg_init_tmr0(); +#endif +#if defined(BSP_USING_TMR1) + nutool_modclkcfg_init_tmr1(); +#endif +#if defined(BSP_USING_TMR2) + nutool_modclkcfg_init_tmr2(); +#endif +#if defined(BSP_USING_TMR3) + nutool_modclkcfg_init_tmr3(); +#endif +#if defined(BSP_USING_UART0) + nutool_modclkcfg_init_uart0(); +#endif +#if defined(BSP_USING_UART1) + nutool_modclkcfg_init_uart1(); +#endif +#if defined(BSP_USING_UART2) + nutool_modclkcfg_init_uart2(); +#endif +#if defined(BSP_USING_UART3) + nutool_modclkcfg_init_uart3(); +#endif +#if defined(BSP_USING_UART4) + nutool_modclkcfg_init_uart4(); +#endif +#if defined(BSP_USING_UART5) + nutool_modclkcfg_init_uart5(); +#endif +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) + nutool_modclkcfg_init_usbd(); +#endif +#if defined(BSP_USING_USBH) || defined(BSP_USING_HSUSBH) + nutool_modclkcfg_init_usbh(); +#endif +#if defined(BSP_USING_USCI0) + nutool_modclkcfg_init_usci0(); +#endif +#if defined(BSP_USING_USCI1) + nutool_modclkcfg_init_usci1(); +#endif +#if defined(BSP_USING_WDT) + nutool_modclkcfg_init_wdt(); +#endif +#if defined(BSP_USING_WWDT) + nutool_modclkcfg_init_wwdt(); +#endif + + /* Update System Core Clock */ + /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */ + SystemCoreClockUpdate(); + + /* Lock protected registers */ + SYS_LockReg(); + + return; +} + +/*** (C) COPYRIGHT 2013-2020 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/numaker-iot-m487/board/NuClockConfig/nutool_modclkcfg.cfg b/bsp/nuvoton/numaker-iot-m487/board/NuClockConfig/nutool_modclkcfg.cfg new file mode 100644 index 0000000000000000000000000000000000000000..3805c0a7eb156b0e6d4f69c14bbfa32d9acb3d32 --- /dev/null +++ b/bsp/nuvoton/numaker-iot-m487/board/NuClockConfig/nutool_modclkcfg.cfg @@ -0,0 +1,33 @@ +/**************************************************************************** + * @file nutool_modclkcfg.cfg + * @version V1.05 + * @Date 2020/04/15-11:28:42 + * @brief NuMicro clock config file + * + * @note Please do not modify this file. + * Otherwise, it may not be loaded successfully. + * Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +MCU:M487JIDAE(LQFP144) +Reg:CLKDIV0 = 0x00070000 +Reg:CLKDIV1 = 0x00000000 +Reg:CLKDIV3 = 0x007E0000 +Reg:CLKDIV4 = 0x00000000 +Reg:PCLKDIV = 0x00000011 +Reg:CLKSEL0 = 0x00A30102 +Reg:CLKSEL1 = 0xB0000001 +Reg:CLKSEL2 = 0x00002BAB +Reg:CLKSEL3 = 0x00000000 +Reg:PWRCTL = 0x00000017 +Reg:AHBCLK = 0x0003D4EE +Reg:APBCLK0 = 0x7F3FF7BF +Reg:APBCLK1 = 0x4CCF1347 +Reg:PLLCTL = 0x0000421E +Reg:CLKOCTL = 0x00000000 +Reg:SYST_CTRL = 0x00000005 +LXT:32768 +HXT:12000000 +PLL:192000000 +HSUSB_OTG_PHY:30000000 +Step:4 +/*** (C) COPYRIGHT 2013-2020 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/numaker-iot-m487/board/NuClockConfig/nutool_modclkcfg.h b/bsp/nuvoton/numaker-iot-m487/board/NuClockConfig/nutool_modclkcfg.h new file mode 100644 index 0000000000000000000000000000000000000000..9dde7925bbef2a53dfacc81e78bfc1703b3df903 --- /dev/null +++ b/bsp/nuvoton/numaker-iot-m487/board/NuClockConfig/nutool_modclkcfg.h @@ -0,0 +1,139 @@ +/**************************************************************************** + * @file nutool_modclkcfg.h + * @version V1.05 + * @Date 2020/04/15-11:28:38 + * @brief NuMicro generated code file + * + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#ifndef __NUTOOL_MODCLKCFG_H__ +#define __NUTOOL_MODCLKCFG_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif +void nutool_modclkcfg_init_acmp01(void); +void nutool_modclkcfg_deinit_acmp01(void); +void nutool_modclkcfg_init_bpwm0(void); +void nutool_modclkcfg_deinit_bpwm0(void); +void nutool_modclkcfg_init_bpwm1(void); +void nutool_modclkcfg_deinit_bpwm1(void); +void nutool_modclkcfg_init_can0(void); +void nutool_modclkcfg_deinit_can0(void); +void nutool_modclkcfg_init_can1(void); +void nutool_modclkcfg_deinit_can1(void); +void nutool_modclkcfg_init_crc(void); +void nutool_modclkcfg_deinit_crc(void); +void nutool_modclkcfg_init_crpt(void); +void nutool_modclkcfg_deinit_crpt(void); +void nutool_modclkcfg_init_dac(void); +void nutool_modclkcfg_deinit_dac(void); +void nutool_modclkcfg_init_eadc(void); +void nutool_modclkcfg_deinit_eadc(void); +void nutool_modclkcfg_init_ebi(void); +void nutool_modclkcfg_deinit_ebi(void); +void nutool_modclkcfg_init_ecap0(void); +void nutool_modclkcfg_deinit_ecap0(void); +void nutool_modclkcfg_init_ecap1(void); +void nutool_modclkcfg_deinit_ecap1(void); +void nutool_modclkcfg_init_emac(void); +void nutool_modclkcfg_deinit_emac(void); +void nutool_modclkcfg_init_epwm0(void); +void nutool_modclkcfg_deinit_epwm0(void); +void nutool_modclkcfg_init_epwm1(void); +void nutool_modclkcfg_deinit_epwm1(void); +void nutool_modclkcfg_init_fmcidle(void); +void nutool_modclkcfg_deinit_fmcidle(void); +void nutool_modclkcfg_init_hsotg(void); +void nutool_modclkcfg_deinit_hsotg(void); +void nutool_modclkcfg_init_hsusbd(void); +void nutool_modclkcfg_deinit_hsusbd(void); +void nutool_modclkcfg_init_i2c0(void); +void nutool_modclkcfg_deinit_i2c0(void); +void nutool_modclkcfg_init_i2c1(void); +void nutool_modclkcfg_deinit_i2c1(void); +void nutool_modclkcfg_init_i2c2(void); +void nutool_modclkcfg_deinit_i2c2(void); +void nutool_modclkcfg_init_i2s0(void); +void nutool_modclkcfg_deinit_i2s0(void); +void nutool_modclkcfg_init_isp(void); +void nutool_modclkcfg_deinit_isp(void); +void nutool_modclkcfg_init_opa(void); +void nutool_modclkcfg_deinit_opa(void); +void nutool_modclkcfg_init_otg(void); +void nutool_modclkcfg_deinit_otg(void); +void nutool_modclkcfg_init_pdma(void); +void nutool_modclkcfg_deinit_pdma(void); +void nutool_modclkcfg_init_qei0(void); +void nutool_modclkcfg_deinit_qei0(void); +void nutool_modclkcfg_init_qei1(void); +void nutool_modclkcfg_deinit_qei1(void); +void nutool_modclkcfg_init_qspi0(void); +void nutool_modclkcfg_deinit_qspi0(void); +void nutool_modclkcfg_init_rtc(void); +void nutool_modclkcfg_deinit_rtc(void); +void nutool_modclkcfg_init_sc0(void); +void nutool_modclkcfg_deinit_sc0(void); +void nutool_modclkcfg_init_sc1(void); +void nutool_modclkcfg_deinit_sc1(void); +void nutool_modclkcfg_init_sc2(void); +void nutool_modclkcfg_deinit_sc2(void); +void nutool_modclkcfg_init_sdh0(void); +void nutool_modclkcfg_deinit_sdh0(void); +void nutool_modclkcfg_init_sdh1(void); +void nutool_modclkcfg_deinit_sdh1(void); +void nutool_modclkcfg_init_spi0(void); +void nutool_modclkcfg_deinit_spi0(void); +void nutool_modclkcfg_init_spi1(void); +void nutool_modclkcfg_deinit_spi1(void); +void nutool_modclkcfg_init_spi2(void); +void nutool_modclkcfg_deinit_spi2(void); +void nutool_modclkcfg_init_spi3(void); +void nutool_modclkcfg_deinit_spi3(void); +void nutool_modclkcfg_init_spim(void); +void nutool_modclkcfg_deinit_spim(void); +void nutool_modclkcfg_init_systick(void); +void nutool_modclkcfg_deinit_systick(void); +void nutool_modclkcfg_init_tmr0(void); +void nutool_modclkcfg_deinit_tmr0(void); +void nutool_modclkcfg_init_tmr1(void); +void nutool_modclkcfg_deinit_tmr1(void); +void nutool_modclkcfg_init_tmr2(void); +void nutool_modclkcfg_deinit_tmr2(void); +void nutool_modclkcfg_init_tmr3(void); +void nutool_modclkcfg_deinit_tmr3(void); +void nutool_modclkcfg_init_uart0(void); +void nutool_modclkcfg_deinit_uart0(void); +void nutool_modclkcfg_init_uart1(void); +void nutool_modclkcfg_deinit_uart1(void); +void nutool_modclkcfg_init_uart2(void); +void nutool_modclkcfg_deinit_uart2(void); +void nutool_modclkcfg_init_uart3(void); +void nutool_modclkcfg_deinit_uart3(void); +void nutool_modclkcfg_init_uart4(void); +void nutool_modclkcfg_deinit_uart4(void); +void nutool_modclkcfg_init_uart5(void); +void nutool_modclkcfg_deinit_uart5(void); +void nutool_modclkcfg_init_usbd(void); +void nutool_modclkcfg_deinit_usbd(void); +void nutool_modclkcfg_init_usbh(void); +void nutool_modclkcfg_deinit_usbh(void); +void nutool_modclkcfg_init_usci0(void); +void nutool_modclkcfg_deinit_usci0(void); +void nutool_modclkcfg_init_usci1(void); +void nutool_modclkcfg_deinit_usci1(void); +void nutool_modclkcfg_init_wdt(void); +void nutool_modclkcfg_deinit_wdt(void); +void nutool_modclkcfg_init_wwdt(void); +void nutool_modclkcfg_deinit_wwdt(void); +void nutool_modclkcfg_init_base(void); +void nutool_modclkcfg_init(void); +#ifdef __cplusplus +} +#endif +#endif /*__NUTOOL_MODCLKCFG_H__*/ + +/*** (C) COPYRIGHT 2013-2020 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/numaker-iot-m487/board/NuPinConfig/nutool_pincfg.c b/bsp/nuvoton/numaker-iot-m487/board/NuPinConfig/nutool_pincfg.c new file mode 100644 index 0000000000000000000000000000000000000000..3ea22966d4958c29ff6a339a17d9c7be1edca906 --- /dev/null +++ b/bsp/nuvoton/numaker-iot-m487/board/NuPinConfig/nutool_pincfg.c @@ -0,0 +1,521 @@ +/**************************************************************************** + * @file nutool_pincfg.c + * @version V1.20 + * @Date 2020/04/08-17:46:57 + * @brief NuMicro generated code file + * + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +/******************** +MCU:M487JIDAE(LQFP144) +********************/ + +#include "M480.h" + +void nutool_pincfg_init_clko(void) +{ + SYS->GPD_MFPH &= ~(SYS_GPD_MFPH_PD12MFP_Msk); + SYS->GPD_MFPH |= (SYS_GPD_MFPH_PD12MFP_CLKO); + + return; +} + +void nutool_pincfg_deinit_clko(void) +{ + SYS->GPD_MFPH &= ~(SYS_GPD_MFPH_PD12MFP_Msk); + + return; +} + +void nutool_pincfg_init_eadc0(void) +{ + SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB14MFP_Msk | SYS_GPB_MFPH_PB9MFP_Msk | SYS_GPB_MFPH_PB8MFP_Msk); + SYS->GPB_MFPH |= (SYS_GPB_MFPH_PB14MFP_EADC0_CH14 | SYS_GPB_MFPH_PB9MFP_EADC0_CH9 | SYS_GPB_MFPH_PB8MFP_EADC0_CH8); + SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB7MFP_Msk | SYS_GPB_MFPL_PB6MFP_Msk | SYS_GPB_MFPL_PB1MFP_Msk | SYS_GPB_MFPL_PB0MFP_Msk); + SYS->GPB_MFPL |= (SYS_GPB_MFPL_PB7MFP_EADC0_CH7 | SYS_GPB_MFPL_PB6MFP_EADC0_CH6 | SYS_GPB_MFPL_PB1MFP_EADC0_CH1 | SYS_GPB_MFPL_PB0MFP_EADC0_CH0); + + /* Disable digital path on these EADC pins */ + GPIO_DISABLE_DIGITAL_PATH(PB, BIT0 | BIT1 | BIT6 | BIT7 | BIT8 | BIT9 | BIT14); + + return; +} + +void nutool_pincfg_deinit_eadc0(void) +{ + SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB14MFP_Msk | SYS_GPB_MFPH_PB9MFP_Msk | SYS_GPB_MFPH_PB8MFP_Msk); + SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB7MFP_Msk | SYS_GPB_MFPL_PB6MFP_Msk | SYS_GPB_MFPL_PB1MFP_Msk | SYS_GPB_MFPL_PB0MFP_Msk); + + return; +} + +void nutool_pincfg_init_emac(void) +{ + SYS->GPA_MFPL &= ~(SYS_GPA_MFPL_PA7MFP_Msk | SYS_GPA_MFPL_PA6MFP_Msk); + SYS->GPA_MFPL |= (SYS_GPA_MFPL_PA7MFP_EMAC_RMII_CRSDV | SYS_GPA_MFPL_PA6MFP_EMAC_RMII_RXERR); + SYS->GPC_MFPH &= ~(SYS_GPC_MFPH_PC8MFP_Msk); + SYS->GPC_MFPH |= (SYS_GPC_MFPH_PC8MFP_EMAC_RMII_REFCLK); + SYS->GPC_MFPL &= ~(SYS_GPC_MFPL_PC7MFP_Msk | SYS_GPC_MFPL_PC6MFP_Msk); + SYS->GPC_MFPL |= (SYS_GPC_MFPL_PC7MFP_EMAC_RMII_RXD0 | SYS_GPC_MFPL_PC6MFP_EMAC_RMII_RXD1); + SYS->GPE_MFPH &= ~(SYS_GPE_MFPH_PE12MFP_Msk | SYS_GPE_MFPH_PE11MFP_Msk | SYS_GPE_MFPH_PE10MFP_Msk | SYS_GPE_MFPH_PE9MFP_Msk | SYS_GPE_MFPH_PE8MFP_Msk); + SYS->GPE_MFPH |= (SYS_GPE_MFPH_PE12MFP_EMAC_RMII_TXEN | SYS_GPE_MFPH_PE11MFP_EMAC_RMII_TXD1 | SYS_GPE_MFPH_PE10MFP_EMAC_RMII_TXD0 | SYS_GPE_MFPH_PE9MFP_EMAC_RMII_MDIO | SYS_GPE_MFPH_PE8MFP_EMAC_RMII_MDC); + + /* Enable high slew rate on all RMII TX output pins */ + GPIO_SetSlewCtl(PE, BIT10 | BIT11 | BIT12, GPIO_SLEWCTL_HIGH); + + return; +} + +void nutool_pincfg_deinit_emac(void) +{ + SYS->GPA_MFPL &= ~(SYS_GPA_MFPL_PA7MFP_Msk | SYS_GPA_MFPL_PA6MFP_Msk); + SYS->GPC_MFPH &= ~(SYS_GPC_MFPH_PC8MFP_Msk); + SYS->GPC_MFPL &= ~(SYS_GPC_MFPL_PC7MFP_Msk | SYS_GPC_MFPL_PC6MFP_Msk); + SYS->GPE_MFPH &= ~(SYS_GPE_MFPH_PE12MFP_Msk | SYS_GPE_MFPH_PE11MFP_Msk | SYS_GPE_MFPH_PE10MFP_Msk | SYS_GPE_MFPH_PE9MFP_Msk | SYS_GPE_MFPH_PE8MFP_Msk); + + return; +} + +void nutool_pincfg_init_epwm0(void) +{ + SYS->GPD_MFPH &= ~(SYS_GPD_MFPH_PD14MFP_Msk); + SYS->GPD_MFPH |= (SYS_GPD_MFPH_PD14MFP_EPWM0_CH4); + + return; +} + +void nutool_pincfg_deinit_epwm0(void) +{ + SYS->GPD_MFPH &= ~(SYS_GPD_MFPH_PD14MFP_Msk); + + return; +} + +void nutool_pincfg_init_hsusb(void) +{ + SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB11MFP_Msk | SYS_GPB_MFPH_PB10MFP_Msk); + SYS->GPB_MFPH |= (SYS_GPB_MFPH_PB11MFP_HSUSB_VBUS_ST | SYS_GPB_MFPH_PB10MFP_HSUSB_VBUS_EN); + + return; +} + +void nutool_pincfg_deinit_hsusb(void) +{ + SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB11MFP_Msk | SYS_GPB_MFPH_PB10MFP_Msk); + + return; +} + +void nutool_pincfg_init_i2c0(void) +{ + SYS->GPG_MFPL &= ~(SYS_GPG_MFPL_PG1MFP_Msk | SYS_GPG_MFPL_PG0MFP_Msk); + SYS->GPG_MFPL |= (SYS_GPG_MFPL_PG1MFP_I2C0_SDA | SYS_GPG_MFPL_PG0MFP_I2C0_SCL); + + GPIO_SetPullCtl(PG, BIT0 | BIT1, GPIO_PUSEL_PULL_UP); + + return; +} + +void nutool_pincfg_deinit_i2c0(void) +{ + SYS->GPG_MFPL &= ~(SYS_GPG_MFPL_PG1MFP_Msk | SYS_GPG_MFPL_PG0MFP_Msk); + + return; +} + +void nutool_pincfg_init_i2c1(void) +{ + SYS->GPG_MFPL &= ~(SYS_GPG_MFPL_PG3MFP_Msk | SYS_GPG_MFPL_PG2MFP_Msk); + SYS->GPG_MFPL |= (SYS_GPG_MFPL_PG3MFP_I2C1_SDA | SYS_GPG_MFPL_PG2MFP_I2C1_SCL); + + GPIO_SetPullCtl(PG, BIT2 | BIT3, GPIO_PUSEL_PULL_UP); + + return; +} + +void nutool_pincfg_deinit_i2c1(void) +{ + SYS->GPG_MFPL &= ~(SYS_GPG_MFPL_PG3MFP_Msk | SYS_GPG_MFPL_PG2MFP_Msk); + + return; +} + +void nutool_pincfg_init_i2c2(void) +{ + SYS->GPD_MFPL &= ~(SYS_GPD_MFPL_PD1MFP_Msk | SYS_GPD_MFPL_PD0MFP_Msk); + SYS->GPD_MFPL |= (SYS_GPD_MFPL_PD1MFP_I2C2_SCL | SYS_GPD_MFPL_PD0MFP_I2C2_SDA); + + GPIO_SetPullCtl(PD, BIT0 | BIT1, GPIO_PUSEL_PULL_UP); + + return; +} + +void nutool_pincfg_deinit_i2c2(void) +{ + SYS->GPD_MFPL &= ~(SYS_GPD_MFPL_PD1MFP_Msk | SYS_GPD_MFPL_PD0MFP_Msk); + + return; +} + +void nutool_pincfg_init_i2s0(void) +{ + SYS->GPF_MFPH &= ~(SYS_GPF_MFPH_PF10MFP_Msk | SYS_GPF_MFPH_PF9MFP_Msk | SYS_GPF_MFPH_PF8MFP_Msk); + SYS->GPF_MFPH |= (SYS_GPF_MFPH_PF10MFP_I2S0_BCLK | SYS_GPF_MFPH_PF9MFP_I2S0_MCLK | SYS_GPF_MFPH_PF8MFP_I2S0_DI); + SYS->GPF_MFPL &= ~(SYS_GPF_MFPL_PF7MFP_Msk | SYS_GPF_MFPL_PF6MFP_Msk); + SYS->GPF_MFPL |= (SYS_GPF_MFPL_PF7MFP_I2S0_DO | SYS_GPF_MFPL_PF6MFP_I2S0_LRCK); + + return; +} + +void nutool_pincfg_deinit_i2s0(void) +{ + SYS->GPF_MFPH &= ~(SYS_GPF_MFPH_PF10MFP_Msk | SYS_GPF_MFPH_PF9MFP_Msk | SYS_GPF_MFPH_PF8MFP_Msk); + SYS->GPF_MFPL &= ~(SYS_GPF_MFPL_PF7MFP_Msk | SYS_GPF_MFPL_PF6MFP_Msk); + + return; +} + +void nutool_pincfg_init_ice(void) +{ + SYS->GPF_MFPL &= ~(SYS_GPF_MFPL_PF1MFP_Msk | SYS_GPF_MFPL_PF0MFP_Msk); + SYS->GPF_MFPL |= (SYS_GPF_MFPL_PF1MFP_ICE_CLK | SYS_GPF_MFPL_PF0MFP_ICE_DAT); + + return; +} + +void nutool_pincfg_deinit_ice(void) +{ + SYS->GPF_MFPL &= ~(SYS_GPF_MFPL_PF1MFP_Msk | SYS_GPF_MFPL_PF0MFP_Msk); + + return; +} + +void nutool_pincfg_init_pa(void) +{ + SYS->GPA_MFPL &= ~(SYS_GPA_MFPL_PA5MFP_Msk | SYS_GPA_MFPL_PA4MFP_Msk | SYS_GPA_MFPL_PA3MFP_Msk | SYS_GPA_MFPL_PA2MFP_Msk | SYS_GPA_MFPL_PA1MFP_Msk | SYS_GPA_MFPL_PA0MFP_Msk); + SYS->GPA_MFPL |= (SYS_GPA_MFPL_PA5MFP_GPIO | SYS_GPA_MFPL_PA4MFP_GPIO | SYS_GPA_MFPL_PA3MFP_GPIO | SYS_GPA_MFPL_PA2MFP_GPIO | SYS_GPA_MFPL_PA1MFP_GPIO | SYS_GPA_MFPL_PA0MFP_GPIO); + + return; +} + +void nutool_pincfg_deinit_pa(void) +{ + SYS->GPA_MFPL &= ~(SYS_GPA_MFPL_PA5MFP_Msk | SYS_GPA_MFPL_PA4MFP_Msk | SYS_GPA_MFPL_PA3MFP_Msk | SYS_GPA_MFPL_PA2MFP_Msk | SYS_GPA_MFPL_PA1MFP_Msk | SYS_GPA_MFPL_PA0MFP_Msk); + + return; +} + +void nutool_pincfg_init_pb(void) +{ + SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB3MFP_Msk | SYS_GPB_MFPL_PB2MFP_Msk); + SYS->GPB_MFPL |= (SYS_GPB_MFPL_PB3MFP_GPIO | SYS_GPB_MFPL_PB2MFP_GPIO); + + return; +} + +void nutool_pincfg_deinit_pb(void) +{ + SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB3MFP_Msk | SYS_GPB_MFPL_PB2MFP_Msk); + + return; +} + +void nutool_pincfg_init_pc(void) +{ + SYS->GPC_MFPH &= ~(SYS_GPC_MFPH_PC13MFP_Msk | SYS_GPC_MFPH_PC12MFP_Msk | SYS_GPC_MFPH_PC11MFP_Msk | SYS_GPC_MFPH_PC10MFP_Msk | SYS_GPC_MFPH_PC9MFP_Msk); + SYS->GPC_MFPH |= (SYS_GPC_MFPH_PC13MFP_GPIO | SYS_GPC_MFPH_PC12MFP_GPIO | SYS_GPC_MFPH_PC11MFP_GPIO | SYS_GPC_MFPH_PC10MFP_GPIO | SYS_GPC_MFPH_PC9MFP_GPIO); + + return; +} + +void nutool_pincfg_deinit_pc(void) +{ + SYS->GPC_MFPH &= ~(SYS_GPC_MFPH_PC13MFP_Msk | SYS_GPC_MFPH_PC12MFP_Msk | SYS_GPC_MFPH_PC11MFP_Msk | SYS_GPC_MFPH_PC10MFP_Msk | SYS_GPC_MFPH_PC9MFP_Msk); + + return; +} + +void nutool_pincfg_init_pd(void) +{ + SYS->GPD_MFPH &= ~(SYS_GPD_MFPH_PD11MFP_Msk | SYS_GPD_MFPH_PD10MFP_Msk | SYS_GPD_MFPH_PD9MFP_Msk | SYS_GPD_MFPH_PD8MFP_Msk); + SYS->GPD_MFPH |= (SYS_GPD_MFPH_PD11MFP_GPIO | SYS_GPD_MFPH_PD10MFP_GPIO | SYS_GPD_MFPH_PD9MFP_GPIO | SYS_GPD_MFPH_PD8MFP_GPIO); + SYS->GPD_MFPL &= ~(SYS_GPD_MFPL_PD3MFP_Msk | SYS_GPD_MFPL_PD2MFP_Msk); + SYS->GPD_MFPL |= (SYS_GPD_MFPL_PD3MFP_GPIO | SYS_GPD_MFPL_PD2MFP_GPIO); + + return; +} + +void nutool_pincfg_deinit_pd(void) +{ + SYS->GPD_MFPH &= ~(SYS_GPD_MFPH_PD11MFP_Msk | SYS_GPD_MFPH_PD10MFP_Msk | SYS_GPD_MFPH_PD9MFP_Msk | SYS_GPD_MFPH_PD8MFP_Msk); + SYS->GPD_MFPL &= ~(SYS_GPD_MFPL_PD3MFP_Msk | SYS_GPD_MFPL_PD2MFP_Msk); + + return; +} + +void nutool_pincfg_init_pe(void) +{ + SYS->GPE_MFPH &= ~(SYS_GPE_MFPH_PE13MFP_Msk); + SYS->GPE_MFPH |= (SYS_GPE_MFPH_PE13MFP_GPIO); + SYS->GPE_MFPL &= ~(SYS_GPE_MFPL_PE5MFP_Msk | SYS_GPE_MFPL_PE4MFP_Msk | SYS_GPE_MFPL_PE1MFP_Msk | SYS_GPE_MFPL_PE0MFP_Msk); + SYS->GPE_MFPL |= (SYS_GPE_MFPL_PE5MFP_GPIO | SYS_GPE_MFPL_PE4MFP_GPIO | SYS_GPE_MFPL_PE1MFP_GPIO | SYS_GPE_MFPL_PE0MFP_GPIO); + + return; +} + +void nutool_pincfg_deinit_pe(void) +{ + SYS->GPE_MFPH &= ~(SYS_GPE_MFPH_PE13MFP_Msk); + SYS->GPE_MFPL &= ~(SYS_GPE_MFPL_PE5MFP_Msk | SYS_GPE_MFPL_PE4MFP_Msk | SYS_GPE_MFPL_PE1MFP_Msk | SYS_GPE_MFPL_PE0MFP_Msk); + + return; +} + +void nutool_pincfg_init_pg(void) +{ + SYS->GPG_MFPH &= ~(SYS_GPG_MFPH_PG15MFP_Msk | SYS_GPG_MFPH_PG14MFP_Msk | SYS_GPG_MFPH_PG13MFP_Msk | SYS_GPG_MFPH_PG12MFP_Msk | SYS_GPG_MFPH_PG11MFP_Msk | SYS_GPG_MFPH_PG10MFP_Msk | SYS_GPG_MFPH_PG9MFP_Msk | SYS_GPG_MFPH_PG8MFP_Msk); + SYS->GPG_MFPH |= (SYS_GPG_MFPH_PG15MFP_GPIO | SYS_GPG_MFPH_PG14MFP_GPIO | SYS_GPG_MFPH_PG13MFP_GPIO | SYS_GPG_MFPH_PG12MFP_GPIO | SYS_GPG_MFPH_PG11MFP_GPIO | SYS_GPG_MFPH_PG10MFP_GPIO | SYS_GPG_MFPH_PG9MFP_GPIO | SYS_GPG_MFPH_PG8MFP_GPIO); + SYS->GPG_MFPL &= ~(SYS_GPG_MFPL_PG7MFP_Msk | SYS_GPG_MFPL_PG6MFP_Msk | SYS_GPG_MFPL_PG5MFP_Msk | SYS_GPG_MFPL_PG4MFP_Msk); + SYS->GPG_MFPL |= (SYS_GPG_MFPL_PG7MFP_GPIO | SYS_GPG_MFPL_PG6MFP_GPIO | SYS_GPG_MFPL_PG5MFP_GPIO | SYS_GPG_MFPL_PG4MFP_GPIO); + + return; +} + +void nutool_pincfg_deinit_pg(void) +{ + SYS->GPG_MFPH &= ~(SYS_GPG_MFPH_PG15MFP_Msk | SYS_GPG_MFPH_PG14MFP_Msk | SYS_GPG_MFPH_PG13MFP_Msk | SYS_GPG_MFPH_PG12MFP_Msk | SYS_GPG_MFPH_PG11MFP_Msk | SYS_GPG_MFPH_PG10MFP_Msk | SYS_GPG_MFPH_PG9MFP_Msk | SYS_GPG_MFPH_PG8MFP_Msk); + SYS->GPG_MFPL &= ~(SYS_GPG_MFPL_PG7MFP_Msk | SYS_GPG_MFPL_PG6MFP_Msk | SYS_GPG_MFPL_PG5MFP_Msk | SYS_GPG_MFPL_PG4MFP_Msk); + + return; +} + +void nutool_pincfg_init_ph(void) +{ + SYS->GPH_MFPH &= ~(SYS_GPH_MFPH_PH11MFP_Msk | SYS_GPH_MFPH_PH10MFP_Msk); + SYS->GPH_MFPH |= (SYS_GPH_MFPH_PH11MFP_GPIO | SYS_GPH_MFPH_PH10MFP_GPIO); + SYS->GPH_MFPL &= ~(SYS_GPH_MFPL_PH3MFP_Msk | SYS_GPH_MFPL_PH2MFP_Msk | SYS_GPH_MFPL_PH1MFP_Msk | SYS_GPH_MFPL_PH0MFP_Msk); + SYS->GPH_MFPL |= (SYS_GPH_MFPL_PH3MFP_GPIO | SYS_GPH_MFPL_PH2MFP_GPIO | SYS_GPH_MFPL_PH1MFP_GPIO | SYS_GPH_MFPL_PH0MFP_GPIO); + + return; +} + +void nutool_pincfg_deinit_ph(void) +{ + SYS->GPH_MFPH &= ~(SYS_GPH_MFPH_PH11MFP_Msk | SYS_GPH_MFPH_PH10MFP_Msk); + SYS->GPH_MFPL &= ~(SYS_GPH_MFPL_PH3MFP_Msk | SYS_GPH_MFPL_PH2MFP_Msk | SYS_GPH_MFPL_PH1MFP_Msk | SYS_GPH_MFPL_PH0MFP_Msk); + + return; +} + +void nutool_pincfg_init_qspi0(void) +{ + SYS->GPC_MFPL &= ~(SYS_GPC_MFPL_PC5MFP_Msk | SYS_GPC_MFPL_PC4MFP_Msk | SYS_GPC_MFPL_PC3MFP_Msk | SYS_GPC_MFPL_PC2MFP_Msk | SYS_GPC_MFPL_PC1MFP_Msk | SYS_GPC_MFPL_PC0MFP_Msk); + SYS->GPC_MFPL |= (SYS_GPC_MFPL_PC5MFP_QSPI0_MISO1 | SYS_GPC_MFPL_PC4MFP_QSPI0_MOSI1 | SYS_GPC_MFPL_PC3MFP_QSPI0_SS | SYS_GPC_MFPL_PC2MFP_QSPI0_CLK | SYS_GPC_MFPL_PC1MFP_QSPI0_MISO0 | SYS_GPC_MFPL_PC0MFP_QSPI0_MOSI0); + + return; +} + +void nutool_pincfg_deinit_qspi0(void) +{ + SYS->GPC_MFPL &= ~(SYS_GPC_MFPL_PC5MFP_Msk | SYS_GPC_MFPL_PC4MFP_Msk | SYS_GPC_MFPL_PC3MFP_Msk | SYS_GPC_MFPL_PC2MFP_Msk | SYS_GPC_MFPL_PC1MFP_Msk | SYS_GPC_MFPL_PC0MFP_Msk); + + return; +} + +void nutool_pincfg_init_sd0(void) +{ + SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB5MFP_Msk | SYS_GPB_MFPL_PB4MFP_Msk); + SYS->GPB_MFPL |= (SYS_GPB_MFPL_PB5MFP_SD0_DAT3 | SYS_GPB_MFPL_PB4MFP_SD0_DAT2); + SYS->GPD_MFPH &= ~(SYS_GPD_MFPH_PD13MFP_Msk); + SYS->GPD_MFPH |= (SYS_GPD_MFPH_PD13MFP_SD0_nCD); + SYS->GPE_MFPL &= ~(SYS_GPE_MFPL_PE7MFP_Msk | SYS_GPE_MFPL_PE6MFP_Msk | SYS_GPE_MFPL_PE3MFP_Msk | SYS_GPE_MFPL_PE2MFP_Msk); + SYS->GPE_MFPL |= (SYS_GPE_MFPL_PE7MFP_SD0_CMD | SYS_GPE_MFPL_PE6MFP_SD0_CLK | SYS_GPE_MFPL_PE3MFP_SD0_DAT1 | SYS_GPE_MFPL_PE2MFP_SD0_DAT0); + + return; +} + +void nutool_pincfg_deinit_sd0(void) +{ + SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB5MFP_Msk | SYS_GPB_MFPL_PB4MFP_Msk); + SYS->GPD_MFPH &= ~(SYS_GPD_MFPH_PD13MFP_Msk); + SYS->GPE_MFPL &= ~(SYS_GPE_MFPL_PE7MFP_Msk | SYS_GPE_MFPL_PE6MFP_Msk | SYS_GPE_MFPL_PE3MFP_Msk | SYS_GPE_MFPL_PE2MFP_Msk); + + return; +} + +void nutool_pincfg_init_spi1(void) +{ + SYS->GPH_MFPL &= ~(SYS_GPH_MFPL_PH7MFP_Msk | SYS_GPH_MFPL_PH6MFP_Msk | SYS_GPH_MFPL_PH5MFP_Msk | SYS_GPH_MFPL_PH4MFP_Msk); + SYS->GPH_MFPL |= (SYS_GPH_MFPL_PH7MFP_SPI1_SS | SYS_GPH_MFPL_PH6MFP_SPI1_CLK | SYS_GPH_MFPL_PH5MFP_SPI1_MOSI | SYS_GPH_MFPL_PH4MFP_SPI1_MISO); + + return; +} + +void nutool_pincfg_deinit_spi1(void) +{ + SYS->GPH_MFPL &= ~(SYS_GPH_MFPL_PH7MFP_Msk | SYS_GPH_MFPL_PH6MFP_Msk | SYS_GPH_MFPL_PH5MFP_Msk | SYS_GPH_MFPL_PH4MFP_Msk); + + return; +} + +void nutool_pincfg_init_spi2(void) +{ + SYS->GPA_MFPH &= ~(SYS_GPA_MFPH_PA11MFP_Msk | SYS_GPA_MFPH_PA10MFP_Msk | SYS_GPA_MFPH_PA9MFP_Msk | SYS_GPA_MFPH_PA8MFP_Msk); + SYS->GPA_MFPH |= (SYS_GPA_MFPH_PA11MFP_SPI2_SS | SYS_GPA_MFPH_PA10MFP_SPI2_CLK | SYS_GPA_MFPH_PA9MFP_SPI2_MISO | SYS_GPA_MFPH_PA8MFP_SPI2_MOSI); + + return; +} + +void nutool_pincfg_deinit_spi2(void) +{ + SYS->GPA_MFPH &= ~(SYS_GPA_MFPH_PA11MFP_Msk | SYS_GPA_MFPH_PA10MFP_Msk | SYS_GPA_MFPH_PA9MFP_Msk | SYS_GPA_MFPH_PA8MFP_Msk); + + return; +} + +void nutool_pincfg_init_uart0(void) +{ + SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB13MFP_Msk | SYS_GPB_MFPH_PB12MFP_Msk); + SYS->GPB_MFPH |= (SYS_GPB_MFPH_PB13MFP_UART0_TXD | SYS_GPB_MFPH_PB12MFP_UART0_RXD); + + return; +} + +void nutool_pincfg_deinit_uart0(void) +{ + SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB13MFP_Msk | SYS_GPB_MFPH_PB12MFP_Msk); + + return; +} + +void nutool_pincfg_init_uart1(void) +{ + SYS->GPH_MFPH &= ~(SYS_GPH_MFPH_PH9MFP_Msk | SYS_GPH_MFPH_PH8MFP_Msk); + SYS->GPH_MFPH |= (SYS_GPH_MFPH_PH9MFP_UART1_RXD | SYS_GPH_MFPH_PH8MFP_UART1_TXD); + + return; +} + +void nutool_pincfg_deinit_uart1(void) +{ + SYS->GPH_MFPH &= ~(SYS_GPH_MFPH_PH9MFP_Msk | SYS_GPH_MFPH_PH8MFP_Msk); + + return; +} + +void nutool_pincfg_init_uart2(void) +{ + SYS->GPE_MFPH &= ~(SYS_GPE_MFPH_PE15MFP_Msk | SYS_GPE_MFPH_PE14MFP_Msk); + SYS->GPE_MFPH |= (SYS_GPE_MFPH_PE15MFP_UART2_RXD | SYS_GPE_MFPH_PE14MFP_UART2_TXD); + + return; +} + +void nutool_pincfg_deinit_uart2(void) +{ + SYS->GPE_MFPH &= ~(SYS_GPE_MFPH_PE15MFP_Msk | SYS_GPE_MFPH_PE14MFP_Msk); + + return; +} + +void nutool_pincfg_init_usb(void) +{ + SYS->GPA_MFPH &= ~(SYS_GPA_MFPH_PA15MFP_Msk | SYS_GPA_MFPH_PA14MFP_Msk | SYS_GPA_MFPH_PA13MFP_Msk | SYS_GPA_MFPH_PA12MFP_Msk); + SYS->GPA_MFPH |= (SYS_GPA_MFPH_PA15MFP_USB_OTG_ID | SYS_GPA_MFPH_PA14MFP_USB_D_P | SYS_GPA_MFPH_PA13MFP_USB_D_N | SYS_GPA_MFPH_PA12MFP_USB_VBUS); + SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB15MFP_Msk | SYS_GPB_MFPH_PB11MFP_Msk | SYS_GPB_MFPH_PB10MFP_Msk); + SYS->GPB_MFPH |= (SYS_GPB_MFPH_PB15MFP_USB_VBUS_EN | SYS_GPB_MFPH_PB11MFP_HSUSB_VBUS_ST | SYS_GPB_MFPH_PB10MFP_HSUSB_VBUS_EN); + SYS->GPC_MFPH &= ~(SYS_GPC_MFPH_PC14MFP_Msk); + SYS->GPC_MFPH |= (SYS_GPC_MFPH_PC14MFP_USB_VBUS_ST); + + return; +} + +void nutool_pincfg_deinit_usb(void) +{ + SYS->GPA_MFPH &= ~(SYS_GPA_MFPH_PA15MFP_Msk | SYS_GPA_MFPH_PA14MFP_Msk | SYS_GPA_MFPH_PA13MFP_Msk | SYS_GPA_MFPH_PA12MFP_Msk); + SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB15MFP_Msk | SYS_GPB_MFPH_PB11MFP_Msk | SYS_GPB_MFPH_PB10MFP_Msk); + SYS->GPC_MFPH &= ~(SYS_GPC_MFPH_PC14MFP_Msk); + + return; +} + +void nutool_pincfg_init(void) +{ + //SYS->GPA_MFPH = 0xEEEE4444; + //SYS->GPA_MFPL = 0x33000000; + //SYS->GPB_MFPH = 0xE166EE11; + //SYS->GPB_MFPL = 0x11330011; + //SYS->GPC_MFPH = 0x0E000003; + //SYS->GPC_MFPL = 0x33444444; + //SYS->GPD_MFPH = 0x0B3D0000; + //SYS->GPD_MFPL = 0x00000066; + //SYS->GPE_MFPH = 0x33033333; + //SYS->GPE_MFPL = 0x33003300; + //SYS->GPF_MFPH = 0x00000000; + //SYS->GPF_MFPL = 0x000000EE; + //SYS->GPG_MFPH = 0x00000000; + //SYS->GPG_MFPL = 0x00005544; + //SYS->GPH_MFPH = 0x000000AA; + //SYS->GPH_MFPL = 0x33330000; + + nutool_pincfg_init_clko(); + nutool_pincfg_init_eadc0(); + nutool_pincfg_init_emac(); + nutool_pincfg_init_epwm0(); + nutool_pincfg_init_hsusb(); + nutool_pincfg_init_i2c0(); + nutool_pincfg_init_i2c1(); + nutool_pincfg_init_i2c2(); + nutool_pincfg_init_i2s0(); + nutool_pincfg_init_ice(); + nutool_pincfg_init_pa(); + nutool_pincfg_init_pb(); + nutool_pincfg_init_pc(); + nutool_pincfg_init_pd(); + nutool_pincfg_init_pe(); + nutool_pincfg_init_pg(); + nutool_pincfg_init_ph(); + nutool_pincfg_init_qspi0(); + nutool_pincfg_init_sd0(); + nutool_pincfg_init_spi1(); + nutool_pincfg_init_spi2(); + nutool_pincfg_init_uart0(); + nutool_pincfg_init_uart1(); + nutool_pincfg_init_uart2(); + nutool_pincfg_init_usb(); + + return; +} + +void nutool_pincfg_deinit(void) +{ + nutool_pincfg_deinit_clko(); + nutool_pincfg_deinit_eadc0(); + nutool_pincfg_deinit_emac(); + nutool_pincfg_deinit_epwm0(); + nutool_pincfg_deinit_hsusb(); + nutool_pincfg_deinit_i2c0(); + nutool_pincfg_deinit_i2c1(); + nutool_pincfg_deinit_i2c2(); + nutool_pincfg_deinit_i2s0(); + nutool_pincfg_deinit_ice(); + nutool_pincfg_deinit_pa(); + nutool_pincfg_deinit_pb(); + nutool_pincfg_deinit_pc(); + nutool_pincfg_deinit_pd(); + nutool_pincfg_deinit_pe(); + nutool_pincfg_deinit_pg(); + nutool_pincfg_deinit_ph(); + nutool_pincfg_deinit_qspi0(); + nutool_pincfg_deinit_sd0(); + nutool_pincfg_deinit_spi1(); + nutool_pincfg_deinit_spi2(); + nutool_pincfg_deinit_uart0(); + nutool_pincfg_deinit_uart1(); + nutool_pincfg_deinit_uart2(); + nutool_pincfg_deinit_usb(); + + return; +} +/*** (C) COPYRIGHT 2013-2020 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/numaker-iot-m487/board/NuPinConfig/nutool_pincfg.cfg b/bsp/nuvoton/numaker-iot-m487/board/NuPinConfig/nutool_pincfg.cfg new file mode 100644 index 0000000000000000000000000000000000000000..e04db406752b4758c80621246a8b19cdff72757f --- /dev/null +++ b/bsp/nuvoton/numaker-iot-m487/board/NuPinConfig/nutool_pincfg.cfg @@ -0,0 +1,214 @@ +/**************************************************************************** + * @file nutool_pincfg.cfg + * @version V1.20 + * @Date 2020/05/05-11:01:04 + * @brief NuMicro config file + * + * @note Please do not modify this file. + * Otherwise, it may not be loaded successfully. + * Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +MCU:M487JIDAE(LQFP144) +Pin1:SD0_DAT3 +Pin2:SD0_DAT2 +Pin3:PB.3 +Pin4:PB.2 +Pin5:PC.12 +Pin6:PC.11 +Pin7:PC.10 +Pin8:PC.9 +Pin9:EADC0_CH1 +Pin10:EADC0_CH0 +Pin11:VSS +Pin12:VDD +Pin13:SPI2_SS +Pin14:SPI2_CLK +Pin15:SPI2_MISO +Pin16:SPI2_MOSI +Pin17:PC.13 +Pin18:CLKO +Pin19:PD.11 +Pin20:PD.10 +Pin21:VSS +Pin22:VDD +Pin23:I2C0_SCL +Pin24:I2C0_SDA +Pin25:I2C1_SCL +Pin26:I2C1_SDA +Pin27:PG.4 +Pin28:PF.11 +Pin29:I2S0_BCLK +Pin30:I2S0_MCLK +Pin31:I2S0_DI +Pin32:I2S0_DO +Pin33:I2S0_LRCK +Pin34:VDD +Pin35:PF.5 +Pin36:PF.4 +Pin37:PH.0 +Pin38:PH.1 +Pin39:PH.2 +Pin40:PH.3 +Pin41:SPI1_MISO +Pin42:SPI1_MOSI +Pin43:SPI1_CLK +Pin44:SPI1_SS +Pin45:PF.3 +Pin46:PF.2 +Pin47:VSS +Pin48:VDD +Pin49:EMAC_RMII_MDC +Pin50:EMAC_RMII_MDIO +Pin51:EMAC_RMII_TXD0 +Pin52:EMAC_RMII_TXD1 +Pin53:EMAC_RMII_TXEN +Pin54:PE.13 +Pin55:EMAC_RMII_REFCLK +Pin56:EMAC_RMII_RXD0 +Pin57:EMAC_RMII_RXD1 +Pin58:EMAC_RMII_CRSDV +Pin59:EMAC_RMII_RXERR +Pin60:VSS +Pin61:VDD +Pin62:LDO_CAP +Pin63:PA.5 +Pin64:PA.4 +Pin65:PA.3 +Pin66:PA.2 +Pin67:PA.1 +Pin68:PA.0 +Pin69:VDDIO +Pin70:UART2_TXD +Pin71:UART2_RXD +Pin72:nRESET +Pin73:ICE_DAT +Pin74:ICE_CLK +Pin75:PD.9 +Pin76:PD.8 +Pin77:QSPI0_MISO1 +Pin78:QSPI0_MOSI1 +Pin79:QSPI0_SS +Pin80:QSPI0_CLK +Pin81:QSPI0_MISO0 +Pin82:QSPI0_MOSI0 +Pin83:VSS +Pin84:VDD +Pin85:PG.9 +Pin86:PG.10 +Pin87:PG.11 +Pin88:PG.12 +Pin89:PG.13 +Pin90:PG.14 +Pin91:PG.15 +Pin92:PD.3 +Pin93:PD.2 +Pin94:I2C2_SCL +Pin95:I2C2_SDA +Pin96:SD0_nCD +Pin97:USB_VBUS +Pin98:USB_D- +Pin99:USB_D+ +Pin100:USB_OTG_ID +Pin101:HSUSB_VRES +Pin102:HSUSB_VDD33 +Pin103:HSUSB_VBUS +Pin104:HSUSB_D- +Pin105:HSUSB_VSS +Pin106:HSUSB_D+ +Pin107:HSUSB_VDD12_CAP +Pin108:HSUSB_ID +Pin109:SD0_CMD +Pin110:SD0_CLK +Pin111:PE.5 +Pin112:PE.4 +Pin113:SD0_DAT1 +Pin114:SD0_DAT0 +Pin115:VSS +Pin116:VDD +Pin117:PE.1 +Pin118:PE.0 +Pin119:UART1_TXD +Pin120:UART1_RXD +Pin121:PH.10 +Pin122:PH.11 +Pin123:EPWM0_CH4 +Pin124:PG.5 +Pin125:PG.6 +Pin126:PG.7 +Pin127:PG.8 +Pin128:VSS +Pin129:LDO_CAP +Pin130:VDD +Pin131:USB_VBUS_ST +Pin132:USB_VBUS_EN +Pin133:EADC0_CH14 +Pin134:UART0_TXD +Pin135:UART0_RXD +Pin136:AVDD +Pin137:VREF +Pin138:AVSS +Pin139:HSUSB_VBUS_ST +Pin140:HSUSB_VBUS_EN +Pin141:EADC0_CH9 +Pin142:EADC0_CH8 +Pin143:EADC0_CH7 +Pin144:EADC0_CH6 +GPIOpin:26 +GPIOpin:74 +GPIOpin:121 +GPIOpin:120 +GPIOpin:125 +GPIOpin:124 +GPIOpin:91 +GPIOpin:92 +GPIOpin:38 +GPIOpin:37 +GPIOpin:36 +GPIOpin:123 +GPIOpin:86 +GPIOpin:39 +GPIOpin:3 +GPIOpin:2 +GPIOpin:4 +GPIOpin:5 +GPIOpin:6 +GPIOpin:7 +GPIOpin:110 +GPIOpin:111 +GPIOpin:67 +GPIOpin:66 +GPIOpin:65 +GPIOpin:64 +GPIOpin:63 +GPIOpin:62 +GPIOpin:90 +GPIOpin:89 +GPIOpin:88 +GPIOpin:87 +GPIOpin:85 +GPIOpin:84 +GPIOpin:126 +GPIOpin:19 +GPIOpin:18 +GPIOpin:117 +GPIOpin:116 +GPIOpin:75 +GPIOpin:53 +GPIOpin:16 +SYS->GPA_MFPH = 0xEEEE4444 +SYS->GPA_MFPL = 0x33000000 +SYS->GPB_MFPH = 0xE166EE11 +SYS->GPB_MFPL = 0x11330011 +SYS->GPC_MFPH = 0x0E000003 +SYS->GPC_MFPL = 0x33444444 +SYS->GPD_MFPH = 0x0B3D0000 +SYS->GPD_MFPL = 0x00000066 +SYS->GPE_MFPH = 0x33033333 +SYS->GPE_MFPL = 0x33003300 +SYS->GPF_MFPH = 0x00000444 +SYS->GPF_MFPL = 0x440000EE +SYS->GPG_MFPH = 0x00000000 +SYS->GPG_MFPL = 0x00005544 +SYS->GPH_MFPH = 0x000000AA +SYS->GPH_MFPL = 0x33330000 +/*** (C) COPYRIGHT 2013-2020 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/numaker-iot-m487/board/NuPinConfig/nutool_pincfg.h b/bsp/nuvoton/numaker-iot-m487/board/NuPinConfig/nutool_pincfg.h new file mode 100644 index 0000000000000000000000000000000000000000..bb1118a95e69ddd32064d7f9802f2e6c5cc4897e --- /dev/null +++ b/bsp/nuvoton/numaker-iot-m487/board/NuPinConfig/nutool_pincfg.h @@ -0,0 +1,73 @@ +/**************************************************************************** + * @file nutool_pincfg.h + * @version V1.20 + * @Date 2020/04/08-16:32:20 + * @brief NuMicro generated code file + * + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#ifndef __NUTOOL_PINCFG_H__ +#define __NUTOOL_PINCFG_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif +void nutool_pincfg_init_clko(void); +void nutool_pincfg_deinit_clko(void); +void nutool_pincfg_init_eadc0(void); +void nutool_pincfg_deinit_eadc0(void); +void nutool_pincfg_init_emac(void); +void nutool_pincfg_deinit_emac(void); +void nutool_pincfg_init_epwm0(void); +void nutool_pincfg_deinit_epwm0(void); +void nutool_pincfg_init_hsusb(void); +void nutool_pincfg_deinit_hsusb(void); +void nutool_pincfg_init_i2c0(void); +void nutool_pincfg_deinit_i2c0(void); +void nutool_pincfg_init_i2c1(void); +void nutool_pincfg_deinit_i2c1(void); +void nutool_pincfg_init_i2c2(void); +void nutool_pincfg_deinit_i2c2(void); +void nutool_pincfg_init_ice(void); +void nutool_pincfg_deinit_ice(void); +void nutool_pincfg_init_pa(void); +void nutool_pincfg_deinit_pa(void); +void nutool_pincfg_init_pb(void); +void nutool_pincfg_deinit_pb(void); +void nutool_pincfg_init_pc(void); +void nutool_pincfg_deinit_pc(void); +void nutool_pincfg_init_pd(void); +void nutool_pincfg_deinit_pd(void); +void nutool_pincfg_init_pe(void); +void nutool_pincfg_deinit_pe(void); +void nutool_pincfg_init_pg(void); +void nutool_pincfg_deinit_pg(void); +void nutool_pincfg_init_ph(void); +void nutool_pincfg_deinit_ph(void); +void nutool_pincfg_init_qspi0(void); +void nutool_pincfg_deinit_qspi0(void); +void nutool_pincfg_init_sd0(void); +void nutool_pincfg_deinit_sd0(void); +void nutool_pincfg_init_spi1(void); +void nutool_pincfg_deinit_spi1(void); +void nutool_pincfg_init_spi2(void); +void nutool_pincfg_deinit_spi2(void); +void nutool_pincfg_init_uart0(void); +void nutool_pincfg_deinit_uart0(void); +void nutool_pincfg_init_uart1(void); +void nutool_pincfg_deinit_uart1(void); +void nutool_pincfg_init_uart2(void); +void nutool_pincfg_deinit_uart2(void); +void nutool_pincfg_init_usb(void); +void nutool_pincfg_deinit_usb(void); +void nutool_pincfg_init(void); +void nutool_pincfg_deinit(void); +#ifdef __cplusplus +} +#endif +#endif /*__NUTOOL_PINCFG_H__*/ + +/*** (C) COPYRIGHT 2013-2020 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/numaker-iot-m487/board/SConscript b/bsp/nuvoton/numaker-iot-m487/board/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..6ed8f178ba2e4339cc909ed0fc56c6efcc184180 --- /dev/null +++ b/bsp/nuvoton/numaker-iot-m487/board/SConscript @@ -0,0 +1,20 @@ +# RT-Thread building script for component + +from building import * + + +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +src = Split(""" +NuClockConfig/nutool_modclkcfg.c +NuPinConfig/nutool_pincfg.c +""") + +src += Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd, cwd + '/NuClockConfig', cwd + '/NuPinConfig'] + +group = DefineGroup('board', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/nuvoton/numaker-iot-m487/board/board.c b/bsp/nuvoton/numaker-iot-m487/board/board.c new file mode 100644 index 0000000000000000000000000000000000000000..318fe6a0fc2cfcb7bb04f605e3d192ce1526daa8 --- /dev/null +++ b/bsp/nuvoton/numaker-iot-m487/board/board.c @@ -0,0 +1,112 @@ +/**************************************************************************//** +* +* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-1-16 Wayne First version +* +******************************************************************************/ + +#include +#include +#include "drv_uart.h" +#include "board.h" +#include "nutool_pincfg.h" +#include "nutool_modclkcfg.h" + +#ifdef __CC_ARM + extern int Image$$RW_IRAM1$$ZI$$Limit; +#elif __ICCARM__ + #pragma section="HEAP" +#else + extern int __bss_end; + extern int __ram_top; +#endif + +/** + * This function will initial M487 board. + */ +void rt_hw_board_init(void) +{ + /* Init System/modules clock */ + nutool_modclkcfg_init(); + + /* Unlock protected registers */ + SYS_UnlockReg(); + + /* Init all pin function setting */ + nutool_pincfg_init(); + + /* Configure SysTick */ + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + + /* Update System Core Clock */ + /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */ + SystemCoreClockUpdate(); + +#if defined(BSP_USING_EADC) + /* Vref connect to internal */ + SYS->VREFCTL = (SYS->VREFCTL & ~SYS_VREFCTL_VREFCTL_Msk) | SYS_VREFCTL_VREF_3_0V; +#endif + + /* Lock protected registers */ + SYS_LockReg(); + + +#ifdef RT_USING_HEAP +#ifdef __CC_ARM + rt_system_heap_init((void *)&Image$$RW_IRAM1$$ZI$$Limit, (void *)SRAM_END); +#elif __ICCARM__ + rt_system_heap_init(__segment_end("HEAP"), (void *)SRAM_END); +#else + /* init memory system */ + rt_system_heap_init((void *)&__bss_end, (void *)&__ram_top); +#endif +#endif /* RT_USING_HEAP */ + +#if defined(BSP_USING_UART) + rt_hw_uart_init(); +#endif + +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + + NVIC_SetPriorityGrouping(7); + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +} + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void rt_hw_cpu_reset(void) +{ + SYS_UnlockReg(); + + SYS->IPRST0 |= SYS_IPRST0_CHIPRST_Msk; +} + +int reboot(int argc, char** argv) +{ + rt_hw_cpu_reset(); + return 0; +} +MSH_CMD_EXPORT(reboot, Reboot System); diff --git a/bsp/nuvoton/numaker-iot-m487/board/board.h b/bsp/nuvoton/numaker-iot-m487/board/board.h new file mode 100644 index 0000000000000000000000000000000000000000..273621293b3b1ac7e89b8045194da7e691c2d72e --- /dev/null +++ b/bsp/nuvoton/numaker-iot-m487/board/board.h @@ -0,0 +1,23 @@ +/**************************************************************************//** +* +* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-1-16 Wayne First version +* +******************************************************************************/ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +// Internal SRAM memory size[Kbytes] <8-64> +#define SRAM_SIZE (160) +#define SRAM_END (0x20000000 + SRAM_SIZE * 1024) + +void rt_hw_board_init(void); +void rt_hw_cpu_reset(void); + +#endif /* BOARD_H_ */ diff --git a/bsp/nuvoton/numaker-iot-m487/board/board_dev.c b/bsp/nuvoton/numaker-iot-m487/board/board_dev.c new file mode 100644 index 0000000000000000000000000000000000000000..7f3aafb45eec1fcb633447fced3cdf31495718fa --- /dev/null +++ b/bsp/nuvoton/numaker-iot-m487/board/board_dev.c @@ -0,0 +1,251 @@ +/**************************************************************************//** +* +* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-1-16 Wayne First version +* +******************************************************************************/ + +#include +#include + +#if defined(BOARD_USING_STORAGE_SPIFLASH) +#if defined(RT_USING_SFUD) + #include "spi_flash.h" + #include "spi_flash_sfud.h" +#endif + +#include "drv_qspi.h" + +#define W25X_REG_READSTATUS (0x05) +#define W25X_REG_READSTATUS2 (0x35) +#define W25X_REG_WRITEENABLE (0x06) +#define W25X_REG_WRITESTATUS (0x01) +#define W25X_REG_QUADENABLE (0x02) + +static rt_uint8_t SpiFlash_ReadStatusReg(struct rt_qspi_device *qspi_device) +{ + rt_uint8_t u8Val; + rt_uint8_t w25x_txCMD1 = W25X_REG_READSTATUS; + rt_qspi_send_then_recv(qspi_device, &w25x_txCMD1, 1, &u8Val, 1); + + return u8Val; +} + +static rt_uint8_t SpiFlash_ReadStatusReg2(struct rt_qspi_device *qspi_device) +{ + rt_uint8_t u8Val; + rt_uint8_t w25x_txCMD1 = W25X_REG_READSTATUS2; + rt_qspi_send_then_recv(qspi_device, &w25x_txCMD1, 1, &u8Val, 1); + + return u8Val; +} + +static void SpiFlash_WriteStatusReg(struct rt_qspi_device *qspi_device, uint8_t u8Value1, uint8_t u8Value2) +{ + rt_uint8_t w25x_txCMD1; + rt_uint8_t u8Val[3]; + + w25x_txCMD1 = W25X_REG_WRITEENABLE; + rt_qspi_send(qspi_device, &w25x_txCMD1, 1); + + u8Val[0] = W25X_REG_WRITESTATUS; + u8Val[1] = u8Value1; + u8Val[2] = u8Value2; + rt_qspi_send(qspi_device, &u8Val, 3); +} + +static void SpiFlash_WaitReady(struct rt_qspi_device *qspi_device) +{ + volatile uint8_t u8ReturnValue; + + do + { + u8ReturnValue = SpiFlash_ReadStatusReg(qspi_device); + u8ReturnValue = u8ReturnValue & 1; + } + while (u8ReturnValue != 0); // check the BUSY bit +} + +static void SpiFlash_EnterQspiMode(struct rt_qspi_device *qspi_device) +{ + uint8_t u8Status1 = SpiFlash_ReadStatusReg(qspi_device); + uint8_t u8Status2 = SpiFlash_ReadStatusReg2(qspi_device); + + u8Status2 |= W25X_REG_QUADENABLE; + SpiFlash_WriteStatusReg(qspi_device, u8Status1, u8Status2); + SpiFlash_WaitReady(qspi_device); +} + +static void SpiFlash_ExitQspiMode(struct rt_qspi_device *qspi_device) +{ + uint8_t u8Status1 = SpiFlash_ReadStatusReg(qspi_device); + uint8_t u8Status2 = SpiFlash_ReadStatusReg2(qspi_device); + + u8Status2 &= ~W25X_REG_QUADENABLE; + SpiFlash_WriteStatusReg(qspi_device, u8Status1, u8Status2); + SpiFlash_WaitReady(qspi_device); +} + +static int rt_hw_spiflash_init(void) +{ + /* Here, we use Dual I/O to drive the SPI flash by default. */ + /* If you want to use Quad I/O, you can modify to 4 from 2 and crossover D2/D3 pin of SPI flash. */ + if (nu_qspi_bus_attach_device("qspi0", "qspi01", 2, SpiFlash_EnterQspiMode, SpiFlash_ExitQspiMode) != RT_EOK) + return -1; + +#if defined(RT_USING_SFUD) + if (rt_sfud_flash_probe("flash0", "qspi01") == RT_NULL) + { + return -(RT_ERROR); + } +#endif + return 0; +} +INIT_COMPONENT_EXPORT(rt_hw_spiflash_init); +#endif /* BOARD_USING_STORAGE_SPIFLASH */ + + +#if defined(BOARD_USING_MAX31875) +#include +int rt_hw_max31875_port(void) +{ + struct rt_sensor_config cfg; + + cfg.intf.dev_name = "i2c1"; + cfg.intf.user_data = (void *)MAX31875_I2C_SLAVE_ADR_R0; + cfg.irq_pin.pin = RT_PIN_NONE; + + rt_hw_max31875_init("max31875", &cfg); + return 0; +} +INIT_APP_EXPORT(rt_hw_max31875_port); +#endif /* BOARD_USING_MAX31875 */ + + +#if defined(BOARD_USING_BMX055) +#include +int rt_hw_bmx055_port(void) +{ + struct rt_sensor_config cfg; + cfg.intf.dev_name = "i2c2"; + cfg.intf.user_data = (void *)0; + cfg.irq_pin.pin = RT_PIN_NONE; + + rt_hw_bmx055_init("bmx055", &cfg); + return 0; +} +INIT_APP_EXPORT(rt_hw_bmx055_port); +#endif /* BOARD_USING_BMX055 */ + +#if defined(BOARD_USING_ESP8266) +#include + +#define LOG_TAG "at.sample.esp" +#include + +static struct at_device_esp8266 esp0 = +{ + "esp0", /* esp8266 device name */ + "uart1", /* esp8266 serial device name, EX: uart1, uuart1 */ + + "NT_ZY_BUFFALO", /* Wi-Fi SSID */ + "12345678", /* Wi-Fi PASSWORD */ + 1024 /* Receive buffer length */ +}; + +static int rt_hw_esp8266_port(void) +{ + struct at_device_esp8266 *esp8266 = &esp0; + rt_base_t esp_rst_pin = NU_GET_PININDEX(NU_PH, 3); + /* ESP8266 reset pin PH.3 */ + rt_pin_mode(esp_rst_pin, PIN_MODE_OUTPUT); + rt_pin_write(esp_rst_pin, 1); + + return at_device_register(&(esp8266->device), + esp8266->device_name, + esp8266->client_name, + AT_DEVICE_CLASS_ESP8266, + (void *) esp8266); +} +INIT_APP_EXPORT(rt_hw_esp8266_port); + +static void at_wifi_set(int argc, char **argv) +{ + struct at_device_ssid_pwd sATDConf; + struct at_device *at_dev = RT_NULL; + + /* If the number of arguments less than 2 */ + if (argc != 3) + { + rt_kprintf("\n"); + rt_kprintf("at_wifi_set \n"); + return ; + } + + sATDConf.ssid = argv[1]; //ssid + sATDConf.password = argv[2]; //password + + if ((at_dev = at_device_get_first_initialized()) != RT_NULL) + at_device_control(at_dev, AT_DEVICE_CTRL_SET_WIFI_INFO, &sATDConf); + else + { + rt_kprintf("Can't find any initialized AT device.\n"); + } +} +#ifdef FINSH_USING_MSH + MSH_CMD_EXPORT(at_wifi_set, AT device wifi set ssid / password function); +#endif +#endif /* BOARD_USING_ESP8266 */ + +#if defined(BOARD_USING_LCD_ILI9341) && defined(NU_PKG_USING_ILI9341_SPI) +#include +#if defined(PKG_USING_GUIENGINE) + #include +#endif +int rt_hw_ili9341_port(void) +{ + if (rt_hw_lcd_ili9341_spi_init("spi2") != RT_EOK) + return -1; + + rt_hw_lcd_ili9341_init(); + +#if defined(PKG_USING_GUIENGINE) + rt_device_t lcd_ili9341; + lcd_ili9341 = rt_device_find("lcd"); + if (lcd_ili9341) + { + rtgui_graphic_set_device(lcd_ili9341); + } +#endif + return 0; +} +INIT_COMPONENT_EXPORT(rt_hw_ili9341_port); +#endif /* BOARD_USING_LCD_ILI9341 */ + +#if defined(BOARD_USING_NAU88L25) && defined(NU_PKG_USING_NAU88L25) +#include +S_NU_NAU88L25_CONFIG sCodecConfig = +{ + .i2c_bus_name = "i2c2", + + .i2s_bus_name = "sound0", + + .pin_phonejack_en = NU_GET_PININDEX(NU_PE, 13), + + .pin_phonejack_det = 0, +}; + +int rt_hw_nau88l25_port(void) +{ + if (nu_hw_nau88l25_init(&sCodecConfig) != RT_EOK) + return -1; + + return 0; +} +INIT_COMPONENT_EXPORT(rt_hw_nau88l25_port); +#endif /* BOARD_USING_NAU88L25 */ diff --git a/bsp/nuvoton/numaker-iot-m487/board/fal_cfg.h b/bsp/nuvoton/numaker-iot-m487/board/fal_cfg.h new file mode 100644 index 0000000000000000000000000000000000000000..d63249b836b4d0e541881d0d43d9d8de38278255 --- /dev/null +++ b/bsp/nuvoton/numaker-iot-m487/board/fal_cfg.h @@ -0,0 +1,42 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-3-03 FYChou First version +* +******************************************************************************/ + +#ifndef _FAL_CFG_H_ +#define _FAL_CFG_H_ + +#include +#include + + +/* ===================== Flash device Configuration ========================= */ +extern const struct fal_flash_dev Onchip_aprom_flash; +extern const struct fal_flash_dev Onchip_ldrom_flash; + +/* -flash device table------------------------------------------------------- */ +#define FAL_FLASH_DEV_TABLE \ +{ \ + &Onchip_aprom_flash, \ + &Onchip_ldrom_flash, \ +} + +/* ====================== Partition Configuration ============================ */ +#ifdef FAL_PART_HAS_TABLE_CFG + +/* -partition table----------------------------------------------------------- */ +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WORD, "ldrom", "OnChip_LDROM", 0, 0x1000, 0}, \ + {FAL_PART_MAGIC_WORD, "aprom", "OnChip_APROM", 0x60000, 0x20000, 0}, \ +} +#endif /* FAL_PART_HAS_TABLE_CFG */ + +#endif /* _FAL_CFG_H_ */ diff --git a/bsp/nuvoton/numaker-iot-m487/linking_scripts/m480_flash.icf b/bsp/nuvoton/numaker-iot-m487/linking_scripts/m480_flash.icf new file mode 100644 index 0000000000000000000000000000000000000000..cd694e9ade688cd0c89901e45796de567b57bd8d --- /dev/null +++ b/bsp/nuvoton/numaker-iot-m487/linking_scripts/m480_flash.icf @@ -0,0 +1,28 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x00080000; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x00028000; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x0400; +define symbol __ICFEDIT_size_heap__ = 0x0000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/nuvoton/numaker-iot-m487/linking_scripts/m480_flash.sct b/bsp/nuvoton/numaker-iot-m487/linking_scripts/m480_flash.sct new file mode 100644 index 0000000000000000000000000000000000000000..ac1da892d0a711b6ba6370ed28616d132b18962e --- /dev/null +++ b/bsp/nuvoton/numaker-iot-m487/linking_scripts/m480_flash.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x80000 { ; load region size_region + ER_IROM1 0x00000000 0x80000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00028000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/nuvoton/numaker-iot-m487/linking_scripts/m480_link.ld b/bsp/nuvoton/numaker-iot-m487/linking_scripts/m480_link.ld new file mode 100644 index 0000000000000000000000000000000000000000..d33fc91ce8e30633646a0ed3f41490d8799b1863 --- /dev/null +++ b/bsp/nuvoton/numaker-iot-m487/linking_scripts/m480_link.ld @@ -0,0 +1,161 @@ +/**************************************************************************//** +* +* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-1-16 Wayne First version +* +******************************************************************************/ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + CODE (rx) : ORIGIN = 0x00000000, LENGTH = 512k /* 512K flash */ + DATA (rw) : ORIGIN = 0x20000000, LENGTH = 160k /* 160K sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x1000; + +SECTIONS +{ + .vector : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + } > CODE = 0 + + .text : + { + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for utest */ + . = ALIGN(4); + __rt_utest_tc_tab_start = .; + KEEP(*(UtestTcTab)) + __rt_utest_tc_tab_end = .; + + . = ALIGN(4); + _etext = .; + } > CODE = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > CODE + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .stack : + { + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >DATA + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >DATA + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > DATA + __bss_end = .; + _end = .; + + __ram_top = ORIGIN(DATA) + LENGTH(DATA); + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/nuvoton/numaker-iot-m487/rtconfig.py b/bsp/nuvoton/numaker-iot-m487/rtconfig.py new file mode 100644 index 0000000000000000000000000000000000000000..902a2bdce94eb440af0deb11ea21c9cf90c36a06 --- /dev/null +++ b/bsp/nuvoton/numaker-iot-m487/rtconfig.py @@ -0,0 +1,132 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='keil' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR + +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Program Files (x86)\GNU Tools ARM Embedded\6 2017-q1-update\bin' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:\Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.2' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = '' +# BUILD = 'debug' + + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'g++' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections -Wuninitialized' + + if BUILD == 'debug': + DEVICE = DEVICE + ' -DDEBUG' + + CFLAGS = DEVICE + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' + LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map -T ./linking_scripts/m480_link.ld ' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2 -gdwarf-2' + AFLAGS += ' -gdwarf-2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu=cortex-m4.fp' + CFLAGS = DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter ./linking_scripts/m480_flash.sct' + + CFLAGS += ' --c99' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/arm/bin40/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = ' ' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --debug' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' -Ol' + CFLAGS += ' --use_c++_inline' + + AFLAGS = '' + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu None' + + LFLAGS = ' --config ./linking_scripts/m480_flash.icf' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + LFLAGS += ' --redirect _Scanf=_ScanfSmall' + LFLAGS += ' --entry __iar_program_start' + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = '' diff --git a/bsp/nuvoton/numaker-iot-m487/template.ewd b/bsp/nuvoton/numaker-iot-m487/template.ewd new file mode 100644 index 0000000000000000000000000000000000000000..adeebbdc4e17efb87a9c5f3a838bdcddc3ec492b --- /dev/null +++ b/bsp/nuvoton/numaker-iot-m487/template.ewd @@ -0,0 +1,1485 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 30 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 0 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 0 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/bsp/nuvoton/numaker-iot-m487/template.ewp b/bsp/nuvoton/numaker-iot-m487/template.ewp new file mode 100644 index 0000000000000000000000000000000000000000..bd5bdfb9902b292ab2afd0e6de3ea7824e751445 --- /dev/null +++ b/bsp/nuvoton/numaker-iot-m487/template.ewp @@ -0,0 +1,1039 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 35 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + diff --git a/bsp/nuvoton/numaker-iot-m487/template.eww b/bsp/nuvoton/numaker-iot-m487/template.eww new file mode 100644 index 0000000000000000000000000000000000000000..e09d1b57a4f75315b8ce94f7ba22d546b8ce27a3 --- /dev/null +++ b/bsp/nuvoton/numaker-iot-m487/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\Template.ewp + + + + + diff --git a/bsp/nuvoton/numaker-iot-m487/template.uvproj b/bsp/nuvoton/numaker-iot-m487/template.uvproj new file mode 100644 index 0000000000000000000000000000000000000000..c27707d0ea6a1d56f0f2146f18d81629e42fbe78 --- /dev/null +++ b/bsp/nuvoton/numaker-iot-m487/template.uvproj @@ -0,0 +1,400 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread-m480 + 0x4 + ARM-ADS + + + M487JIDAE + Nuvoton + IRAM(0x20000000-0x20027FFF) IROM(0-0x7FFFF) CLOCK(192000000) CPUTYPE("Cortex-M4") FPU2 + + undefined + + 0 + + + + + + + + + + + SFD\Nuvoton\M481_v1.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil4\ + rtthread + 1 + 0 + 1 + 1 + 1 + .\build\keil4\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + fromelf.exe --bin --output "$L@L.bin" "$L@L.axf" + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + + SARMCM3.DLL + + TARMCM1.DLL + + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + + 0 + 10 + + + + + + + + + + + + + + NULink\Nu_Link.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4101 + + 0 + NULink\Nu_Link.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x28000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x28000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + --c99 + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + .\linking_scripts\m480_flash.sct + + + + + + + + + + + + diff --git a/bsp/nuvoton/numaker-iot-m487/template.uvprojx b/bsp/nuvoton/numaker-iot-m487/template.uvprojx new file mode 100644 index 0000000000000000000000000000000000000000..dc049f407505940e1d026c7db3ac9b3ab3dcfbed --- /dev/null +++ b/bsp/nuvoton/numaker-iot-m487/template.uvprojx @@ -0,0 +1,401 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread-m480 + 0x4 + ARM-ADS + 0 + + + M487JIDAE + Nuvoton + Nuvoton.NuMicro_DFP.1.3.5 + http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack + IRAM(0x20000000,0x28000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0M481_AP_512 -FS00 -FL080000 -FP0($$Device:M487JIDAE$Flash\M481_AP_512.FLM)) + 0 + $$Device:M487JIDAE$Device\M480\Include\M480.h + + + + + + + + + + $$Device:M487JIDAE$SVD\Nuvoton\M481_v1.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil5\ + rtthread + 1 + 0 + 1 + 1 + 1 + .\build\keil5\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf.exe --bin --output "$L@L.bin" "$L@L.axf" + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + + SARMCM3.DLL + + TARMCM1.DLL + + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4103 + + 1 + NULink\Nu_Link.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x28000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x28000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --c99 + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\linking_scripts\m480_flash.sct + + + + + + + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/bsp/nuvoton/numaker-pfm-m487/.config b/bsp/nuvoton/numaker-pfm-m487/.config new file mode 100644 index 0000000000000000000000000000000000000000..bdb0764da64f5014a0726b27937331c78a94a840 --- /dev/null +++ b/bsp/nuvoton/numaker-pfm-m487/.config @@ -0,0 +1,737 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +CONFIG_RT_USING_SIGNALS=y + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=256 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x40002 +CONFIG_ARCH_ARM=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M4=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=2048 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=8 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 +CONFIG_DFS_FD_MAX=32 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=8 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_UFFS is not set +# CONFIG_RT_USING_DFS_JFFS2 is not set +# CONFIG_RT_USING_DFS_NFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=64 +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=128 +CONFIG_RT_USING_CAN=y +# CONFIG_RT_CAN_USING_HDR is not set +CONFIG_RT_USING_HWTIMER=y +# CONFIG_RT_USING_CPUTIME is not set +CONFIG_RT_USING_I2C=y +# CONFIG_RT_I2C_DEBUG is not set +CONFIG_RT_USING_I2C_BITOPS=y +# CONFIG_RT_I2C_BITOPS_DEBUG is not set +CONFIG_RT_USING_PIN=y +CONFIG_RT_USING_ADC=y +CONFIG_RT_USING_PWM=y +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +CONFIG_RT_USING_PM=y +CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_ALARM is not set +# CONFIG_RT_USING_SOFT_RTC is not set +# CONFIG_RT_USING_SDIO is not set +CONFIG_RT_USING_SPI=y +CONFIG_RT_USING_QSPI=y +# CONFIG_RT_USING_SPI_MSD is not set +CONFIG_RT_USING_SFUD=y +CONFIG_RT_SFUD_USING_SFDP=y +CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y +# CONFIG_RT_SFUD_USING_QSPI is not set +CONFIG_RT_SFUD_SPI_MAX_HZ=50000000 +# CONFIG_RT_DEBUG_SFUD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set +CONFIG_RT_USING_WDT=y +CONFIG_RT_USING_AUDIO=y +CONFIG_RT_AUDIO_REPLAY_MP_BLOCK_SIZE=4096 +CONFIG_RT_AUDIO_REPLAY_MP_BLOCK_COUNT=2 +CONFIG_RT_AUDIO_RECORD_PIPE_SIZE=2048 +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +CONFIG_RT_USING_HWCRYPTO=y +CONFIG_RT_HWCRYPTO_DEFAULT_NAME="hwcryto" +CONFIG_RT_HWCRYPTO_IV_MAX_SIZE=16 +CONFIG_RT_HWCRYPTO_KEYBIT_MAX_SIZE=256 +# CONFIG_RT_HWCRYPTO_USING_GCM is not set +CONFIG_RT_HWCRYPTO_USING_AES=y +CONFIG_RT_HWCRYPTO_USING_AES_ECB=y +CONFIG_RT_HWCRYPTO_USING_AES_CBC=y +CONFIG_RT_HWCRYPTO_USING_AES_CFB=y +CONFIG_RT_HWCRYPTO_USING_AES_CTR=y +CONFIG_RT_HWCRYPTO_USING_AES_OFB=y +CONFIG_RT_HWCRYPTO_USING_DES=y +CONFIG_RT_HWCRYPTO_USING_DES_ECB=y +CONFIG_RT_HWCRYPTO_USING_DES_CBC=y +CONFIG_RT_HWCRYPTO_USING_3DES=y +CONFIG_RT_HWCRYPTO_USING_3DES_ECB=y +CONFIG_RT_HWCRYPTO_USING_3DES_CBC=y +# CONFIG_RT_HWCRYPTO_USING_RC4 is not set +# CONFIG_RT_HWCRYPTO_USING_MD5 is not set +CONFIG_RT_HWCRYPTO_USING_SHA1=y +CONFIG_RT_HWCRYPTO_USING_SHA2=y +CONFIG_RT_HWCRYPTO_USING_SHA2_224=y +CONFIG_RT_HWCRYPTO_USING_SHA2_256=y +CONFIG_RT_HWCRYPTO_USING_SHA2_384=y +CONFIG_RT_HWCRYPTO_USING_SHA2_512=y +CONFIG_RT_HWCRYPTO_USING_RNG=y +CONFIG_RT_HWCRYPTO_USING_CRC=y +CONFIG_RT_HWCRYPTO_USING_CRC_07=y +CONFIG_RT_HWCRYPTO_USING_CRC_8005=y +CONFIG_RT_HWCRYPTO_USING_CRC_1021=y +# CONFIG_RT_HWCRYPTO_USING_CRC_3D65 is not set +CONFIG_RT_HWCRYPTO_USING_CRC_04C11DB7=y +# CONFIG_RT_HWCRYPTO_USING_BIGNUM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +CONFIG_RT_USING_USB_HOST=y +CONFIG_RT_USBH_MSTORAGE=y +CONFIG_UDISK_MOUNTPOINT="/mnt/udisk/" +CONFIG_RT_USING_USB_DEVICE=y +CONFIG_RT_USBD_THREAD_STACK_SZ=4096 +CONFIG_USB_VENDOR_ID=0x0FFE +CONFIG_USB_PRODUCT_ID=0x0001 +# CONFIG_RT_USB_DEVICE_COMPOSITE is not set +# CONFIG__RT_USB_DEVICE_NONE is not set +# CONFIG__RT_USB_DEVICE_CDC is not set +# CONFIG__RT_USB_DEVICE_MSTORAGE is not set +CONFIG__RT_USB_DEVICE_HID=y +# CONFIG__RT_USB_DEVICE_RNDIS is not set +# CONFIG__RT_USB_DEVICE_ECM is not set +# CONFIG__RT_USB_DEVICE_WINUSB is not set +# CONFIG__RT_USB_DEVICE_AUDIO is not set +CONFIG_RT_USB_DEVICE_HID=y +# CONFIG_RT_USB_DEVICE_HID_KEYBOARD is not set +CONFIG_RT_USB_DEVICE_HID_MOUSE=y +# CONFIG_RT_USB_DEVICE_HID_GENERAL is not set +# CONFIG_RT_USB_DEVICE_HID_MEDIA is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_USING_POSIX=y +# CONFIG_RT_USING_POSIX_MMAP is not set +# CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_AIO is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Network +# + +# +# Socket abstraction layer +# +CONFIG_RT_USING_SAL=y + +# +# protocol stack implement +# +CONFIG_SAL_USING_LWIP=y +# CONFIG_SAL_USING_POSIX is not set +CONFIG_SAL_SOCKETS_NUM=16 + +# +# Network interface device +# +CONFIG_RT_USING_NETDEV=y +CONFIG_NETDEV_USING_IFCONFIG=y +CONFIG_NETDEV_USING_PING=y +CONFIG_NETDEV_USING_NETSTAT=y +CONFIG_NETDEV_USING_AUTO_DEFAULT=y +# CONFIG_NETDEV_USING_IPV6 is not set +CONFIG_NETDEV_IPV4=1 +CONFIG_NETDEV_IPV6=0 +# CONFIG_NETDEV_IPV6_SCOPES is not set + +# +# light weight TCP/IP stack +# +CONFIG_RT_USING_LWIP=y +# CONFIG_RT_USING_LWIP141 is not set +CONFIG_RT_USING_LWIP202=y +# CONFIG_RT_USING_LWIP210 is not set +# CONFIG_RT_USING_LWIP_IPV6 is not set +CONFIG_RT_LWIP_IGMP=y +CONFIG_RT_LWIP_ICMP=y +# CONFIG_RT_LWIP_SNMP is not set +CONFIG_RT_LWIP_DNS=y +CONFIG_RT_LWIP_DHCP=y +CONFIG_IP_SOF_BROADCAST=1 +CONFIG_IP_SOF_BROADCAST_RECV=1 + +# +# Static IPv4 Address +# +CONFIG_RT_LWIP_IPADDR="192.168.1.30" +CONFIG_RT_LWIP_GWADDR="192.168.1.1" +CONFIG_RT_LWIP_MSKADDR="255.255.255.0" +CONFIG_RT_LWIP_UDP=y +CONFIG_RT_LWIP_TCP=y +CONFIG_RT_LWIP_RAW=y +# CONFIG_RT_LWIP_PPP is not set +CONFIG_RT_MEMP_NUM_NETCONN=8 +CONFIG_RT_LWIP_PBUF_NUM=16 +CONFIG_RT_LWIP_RAW_PCB_NUM=4 +CONFIG_RT_LWIP_UDP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_SEG_NUM=40 +CONFIG_RT_LWIP_TCP_SND_BUF=8196 +CONFIG_RT_LWIP_TCP_WND=8196 +CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10 +CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 +CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024 +# CONFIG_LWIP_NO_RX_THREAD is not set +# CONFIG_LWIP_NO_TX_THREAD is not set +CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024 +CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 +# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set +CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 +CONFIG_LWIP_NETIF_LINK_CALLBACK=1 +CONFIG_SO_REUSE=1 +CONFIG_LWIP_SO_RCVTIMEO=1 +CONFIG_LWIP_SO_SNDTIMEO=1 +CONFIG_LWIP_SO_RCVBUF=1 +# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=0 +# CONFIG_RT_LWIP_STATS is not set +# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set +CONFIG_RT_LWIP_USING_PING=y +# CONFIG_RT_LWIP_DEBUG is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set +# CONFIG_LWIP_USING_DHCPD is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +CONFIG_RT_USING_UTEST=y +CONFIG_UTEST_THR_STACK_SIZE=4096 +CONFIG_UTEST_THR_PRIORITY=20 +# CONFIG_RT_USING_LWP is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +CONFIG_PKG_USING_WAVPLAYER=y +CONFIG_PKG_WAVPLAYER_PATH="/packages/multimedia/wavplayer" +CONFIG_PKG_WP_USING_PLAY=y +CONFIG_PKG_WP_PLAY_DEVICE="sound0" +CONFIG_PKG_WP_USING_RECORD=y +CONFIG_PKG_WP_RECORD_DEVICE="sound0" +# CONFIG_PKG_USING_WAVPLAYER_V020 is not set +CONFIG_PKG_USING_WAVPLAYER_LATEST_VERSION=y +CONFIG_PKG_WAVPLAYER_VER="latest" +# CONFIG_PKG_USING_TJPGD is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_URLENCODE is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +CONFIG_PKG_USING_FAL=y +CONFIG_PKG_FAL_PATH="/packages/system/fal" +CONFIG_FAL_DEBUG_CONFIG=y +CONFIG_FAL_DEBUG=1 +CONFIG_FAL_PART_HAS_TABLE_CFG=y +# CONFIG_FAL_USING_SFUD_PORT is not set +# CONFIG_PKG_USING_FAL_V00500 is not set +CONFIG_PKG_USING_FAL_V00400=y +# CONFIG_PKG_USING_FAL_V00300 is not set +# CONFIG_PKG_USING_FAL_V00200 is not set +# CONFIG_PKG_USING_FAL_V00100 is not set +# CONFIG_PKG_USING_FAL_LATEST_VERSION is not set +CONFIG_PKG_FAL_VER="v0.4.0" +CONFIG_PKG_FAL_VER_NUM=0x00400 +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +CONFIG_PKG_USING_OPTPARSE=y +CONFIG_PKG_OPTPARSE_PATH="/packages/misc/optparse" +CONFIG_PKG_USING_OPTPARSE_V100=y +# CONFIG_PKG_USING_OPTPARSE_LATEST_VERSION is not set +CONFIG_PKG_OPTPARSE_VER="v1.0.0" +# CONFIG_OPTPARSE_USING_DEMO is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set + +# +# Nuvoton Packages Config +# +CONFIG_NU_PKG_USING_UTILS=y +CONFIG_NU_PKG_USING_DEMO=y +# CONFIG_NU_PKG_USING_BMX055 is not set +# CONFIG_NU_PKG_USING_MAX31875 is not set +CONFIG_NU_PKG_USING_NAU88L25=y +# CONFIG_NU_PKG_USING_ILI9341 is not set + +# +# Hardware Drivers Config +# + +# +# On-chip Peripheral Drivers +# +CONFIG_SOC_SERIES_M480=y +# CONFIG_BSP_USE_STDDRIVER_SOURCE is not set +CONFIG_BSP_USING_PDMA=y +CONFIG_NU_PDMA_MEMFUN_ACTOR_MAX=2 +CONFIG_BSP_USING_FMC=y +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_CLK=y +CONFIG_NU_CLK_INVOKE_WKTMR=y +CONFIG_BSP_USING_EMAC=y +CONFIG_NU_EMAC_PDMA_MEMCOPY=y +CONFIG_NU_EMAC_PDMA_MEMCOPY_THRESHOLD=128 +CONFIG_BSP_USING_RTC=y +# CONFIG_NU_RTC_SUPPORT_IO_RW is not set +CONFIG_NU_RTC_SUPPORT_MSH_CMD=y +# CONFIG_BSP_USING_EADC is not set +CONFIG_BSP_USING_TMR=y +# CONFIG_BSP_USING_TMR0 is not set +# CONFIG_BSP_USING_TMR1 is not set +# CONFIG_BSP_USING_TMR2 is not set +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +# CONFIG_BSP_USING_UART0_TX_DMA is not set +# CONFIG_BSP_USING_UART0_RX_DMA is not set +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set +# CONFIG_BSP_USING_UART5 is not set +# CONFIG_BSP_USING_UART6 is not set +# CONFIG_BSP_USING_UART7 is not set +CONFIG_BSP_USING_I2C=y +# CONFIG_BSP_USING_I2C0 is not set +CONFIG_BSP_USING_I2C1=y +CONFIG_BSP_USING_I2C2=y +# CONFIG_BSP_USING_USCI is not set +# CONFIG_BSP_USING_UUART0 is not set +# CONFIG_BSP_USING_UI2C0 is not set +# CONFIG_BSP_USING_USPI0 is not set +CONFIG_BSP_USING_SDH=y +CONFIG_BSP_USING_SDH0=y +# CONFIG_BSP_USING_SDH1 is not set +CONFIG_NU_SDH_USING_PDMA=y +CONFIG_NU_SDH_HOTPLUG=y +# CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_BPWM is not set +# CONFIG_BSP_USING_EPWM is not set +CONFIG_BSP_USING_SPI=y +# CONFIG_BSP_USING_SPI_PDMA is not set +# CONFIG_BSP_USING_SPII2S is not set +CONFIG_BSP_USING_SPI0_NONE=y +# CONFIG_BSP_USING_SPI0 is not set +# CONFIG_BSP_USING_SPII2S0 is not set +CONFIG_BSP_USING_SPI1_NONE=y +# CONFIG_BSP_USING_SPI1 is not set +# CONFIG_BSP_USING_SPII2S1 is not set +CONFIG_BSP_USING_SPI2_NONE=y +# CONFIG_BSP_USING_SPI2 is not set +# CONFIG_BSP_USING_SPII2S2 is not set +# CONFIG_BSP_USING_SPI3_NONE is not set +CONFIG_BSP_USING_SPI3=y +# CONFIG_BSP_USING_SPII2S3 is not set +# CONFIG_BSP_USING_SPI3_PDMA is not set +CONFIG_BSP_USING_I2S=y +CONFIG_NU_I2S_DMA_FIFO_SIZE=2048 +CONFIG_BSP_USING_QSPI=y +CONFIG_BSP_USING_QSPI0=y +CONFIG_BSP_USING_QSPI0_PDMA=y +# CONFIG_BSP_USING_QSPI1 is not set +# CONFIG_BSP_USING_SCUART is not set +# CONFIG_BSP_USING_ECAP is not set +# CONFIG_BSP_USING_QEI is not set +CONFIG_BSP_USING_CRYPTO=y +# CONFIG_NU_PRNG_USE_SEED is not set +CONFIG_BSP_USING_TRNG=y +CONFIG_BSP_USING_CRC=y +CONFIG_NU_CRC_USE_PDMA=y +# CONFIG_BSP_USING_SOFT_I2C is not set +CONFIG_BSP_USING_WDT=y +# CONFIG_BSP_USING_EBI is not set +CONFIG_BSP_USING_USBD=y +# CONFIG_BSP_USING_HSUSBD is not set +# CONFIG_BSP_USING_USBH is not set +CONFIG_BSP_USING_HSUSBH=y +# CONFIG_BSP_USING_HSOTG is not set + +# +# On-board Peripheral Drivers +# +CONFIG_BSP_USING_NULINKME=y +CONFIG_BOARD_USING_IP101GR=y +CONFIG_BOARD_USING_NAU88L25=y +CONFIG_BOARD_USING_STORAGE_SDCARD=y +CONFIG_BOARD_USING_STORAGE_SPIFLASH=y +# CONFIG_BOARD_USING_HSUSBD is not set +# CONFIG_BOARD_USING_HSUSBD_USBH is not set +# CONFIG_BOARD_USING_HSUSBH is not set +CONFIG_BOARD_USING_HSUSBH_USBD=y +# CONFIG_BOARD_USING_HSOTG is not set + +# +# Board extended module drivers +# +# CONFIG_BOARD_USING_ADVANCE_V4 is not set +CONFIG_BOARD_USE_UTEST=y +CONFIG_UTEST_CMD_PREFIX="bsp.nuvoton.numaker-pfm-m487.test.utest." diff --git a/bsp/nuvoton/numaker-pfm-m487/Kconfig b/bsp/nuvoton/numaker-pfm-m487/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..5c55e87c61126df91e5422b5dedf381c30f03570 --- /dev/null +++ b/bsp/nuvoton/numaker-pfm-m487/Kconfig @@ -0,0 +1,29 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +# you can change the RTT_ROOT default "../../.." to your rtthread_root, +# example : default "F:/git_repositories/rt-thread" + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +config NU_PKGS_DIR + string + option env="NU_PKGS_ROOT" + default "../libraries/nu_packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "$NU_PKGS_DIR/Kconfig" +source "$BSP_DIR/board/Kconfig" diff --git a/bsp/nuvoton/numaker-pfm-m487/Nu_Link_Driver.ini b/bsp/nuvoton/numaker-pfm-m487/Nu_Link_Driver.ini new file mode 100644 index 0000000000000000000000000000000000000000..13faf632912edf6bbe0c7191d75a6765dd414bd5 --- /dev/null +++ b/bsp/nuvoton/numaker-pfm-m487/Nu_Link_Driver.ini @@ -0,0 +1,870 @@ +[Version] +Nu_LinkVersion=V5.8 +[Process] +ProcessID=0x0000961c +ProcessCreationTime_L=0x338f3649 +ProcessCreationTime_H=0x01d61201 +NuLinkID=0x18004d67 +NuLinkIDs_Count=0x00000001 +NuLinkID0=0x18004d67 +[ChipSelect] +;ChipName= +ChipName=M481 +[NUC505] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=NUC505_SPIFLASH.FLM +[NUC4xx] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=NUC400_AP_512.FLM +TraceConf0=0x00000002 +TraceConf1=0x014fb180 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +[NUC2xx] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NUC200_AP_128.FLM +[NUC1311] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NUC1311_AP_64.FLM +[NUC126] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x2000 +ProgramAlgorithm=NUC126_AP_256.FLM +[NUC121] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NUC121_AP_32.FLM +[NUC1xx] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NUC100_AP_128.FLM +[NUC029] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=NUC029_AP_16.FLM +[NM1820] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=NM1820_AP_17_5.FLM +[NM1810] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=NM1810_AP_29_5.FLM +[NM1500] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NM1500_AP_128.FLM +[NM1330] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NM1330_AP_64.FLM +[NM1320] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NM1320_AP_32.FLM +[NM1230] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NM1230_AP_64.FLM +[NM1200] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=NM1200_AP_8.FLM +[NM1120] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=NM1120_AP_29_5.FLM +[TF5100] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=TF5100_AP_64.FLM +[NDA102] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=NDA102_AP_29_5.FLM +[Nano103] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=Nano103_AP_64.FLM +[Nano100] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=Nano100_AP_64.FLM +[N576] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=N576_AP_145.FLM +[N575] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=N575_AP_145.FLM +[N572] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x2000 +ProgramAlgorithm=N572Fxxx.FLM +[N571] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x2000 +ProgramAlgorithm=N571E000.FLM +[N570] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=N570_AP_64.FLM +[N569] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=N569_AP_64.FLM +[N512] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=N512_AP_64.FLM +[Mini57] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=Mini57_AP_29_5.FLM +[Mini51] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=Mini51_AP_16.FLM +[M481] +Connect=2 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x00004000 +ProgramAlgorithm=M481_AP_512.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +[M480LD] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=M480LD_AP_256.FLM +[M451] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=M451_AP_256.FLM +[M251] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x2000 +ProgramAlgorithm=M251_AP_192.FLM +[M2351] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=M2351_AP_512.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +[M261] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=M261_AP_512.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +[MR63] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=MR63_AP_512.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +[M0564] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x2000 +ProgramAlgorithm=M0564_AP_256.FLM +[M0519] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=M0519_AP_128.FLM +[M0518] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=M0518_AP_64.FLM +[M05x] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=M0516_AP_64.FLM +[M031] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=M031_AP_128.FLM +[NPCX] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=NPCX_AP_512.FLM +[I94000] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=I94000_AP_512.FLM +[ISD9300] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=ISD9300_AP_145.FLM +[I9200] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=I9200_AP_128.FLM +[ISD9xxx] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=ISD9100_AP_145.FLM +[ISD9000] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=ISD9000_AP_64.FLM +[AU9xxx] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=AU9100_AP_145.FLM +[General] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm= diff --git a/bsp/nuvoton/numaker-pfm-m487/README.md b/bsp/nuvoton/numaker-pfm-m487/README.md new file mode 100644 index 0000000000000000000000000000000000000000..3575f3b9c2ca471a1a9605cbe62b7b77b8d98c89 --- /dev/null +++ b/bsp/nuvoton/numaker-pfm-m487/README.md @@ -0,0 +1,76 @@ +# NuMaker-PFM-M487 + +## 1. Introduction +NuMaker-PFM-M487 provides multiple networking, interfaces, audio recording, playback functions, and flexible extended data storage. + +[![NuMaker-PFM-M487](https://i.imgur.com/k8krqTW.png "NuMaker-PFM-M487")](https://i.imgur.com/k8krqTW.png "NuMaker-PFM-M487") + +### 1.1 MCU specification + +| | Features | +| -- | -- | +| MCU | M487JIDAE | +| Operation frequency | 192MHz | +| embedded Flash size | 512kB, Dual Bank | +| SRAM size | 160kB | +| Crypto engine | DES, AES, ECC, 3DES, HMAC and SHA crypto accelerator | +| RMII interface | Support 10/100 Mbps Ethernet | + +### 1.2 Interface + +| Interface | +| -- | +| Arduino UNO | +| RJ45 Ethernet | +| USB 1.1/2.0 OTG ports | +| A microSD slot | +| A 3.5mm Audio connector | + +### 1.3 On-board devices + +| Device | Descirption | Driver supporting status | +| -- | -- | -- | +|SPI flash | W25Q32 | Supported | +|Ethernet PHY| IP101GR | Supported | +|Audio Codec| NAU88L25, Supports MIC and earphone | Coming soon | + +## 2. Supported compiler +Support GCC, MDK4, MDK5, IAR IDE/compilers. More information of these compiler version as following: + +| IDE/Compiler | Tested version | +| ---------- | ---------------------------- | +| MDK4 | 4.76 | +| MDK5 | 5.26.2 | +| IAR | 8.2 | +| GCC | GCC 5.4.1 20160919 (release) | + +Notice: Please install Nu-Link_Keil_Driver or Nu-Link_IAR_Driver for development. + +## 3. Program firmware +### Step 1: +At first, you need to configure ISW1 switch on the NuMaker-PFM-M487 board. Set the four switches to ‘ON’ position. After the configuration is done, connect the NuMaker-PFM-M487 board and your computer using the USB Micro cable. After that, window manager will show a ‘NuMicro MCU’ virtual disk. Finally, you will use this virtual disk to burn firmware. + +[![NuLinkMe](https://i.imgur.com/daoohon.png "NuLinkMe")](https://i.imgur.com/daoohon.png "NuLinkMe") + +[![NuMicro MCU](https://i.imgur.com/lWnNtpM.png "NuMicro MCU")](https://i.imgur.com/lWnNtpM.png "NuMicro MCU") + +### Step 2: +A simple firmware burning method is that you can drag and drop the binary image file to NuMicro MCU virtual disk or copy the binary file to NuMicro MCU disk to burn firmware. + +[![CopyTo](https://i.imgur.com/6NfGS7m.png "CopyTo")](https://i.imgur.com/6NfGS7m.png "CopyTo") + +## 4. Test +You can use Tera Term terminate emulator (or other software) to type commands of RTT. All parameters of serial communication are shown in below image. Here, you can find out the corresponding port number of Nuvoton Virtual Com Port in window device manager. + +[![Serial settings](https://i.imgur.com/5NYuSNM.png "Serial settings")](https://i.imgur.com/5NYuSNM.png "Serial settings") + +## 5. Purchase +* [Nuvoton Direct][1] + +## 6. Resources +* [Download board schematics][2] +* [Download MCU TRM][3] + + [1]: https://direct.nuvoton.com/en/numaker-pfm-m487 + [2]: https://www.nuvoton.com/resource-download.jsp?tp_GUID=HL0120180420145943 + [3]: https://www.nuvoton.com/resource-download.jsp?tp_GUID=DA05-M480 diff --git a/bsp/nuvoton/numaker-pfm-m487/SConscript b/bsp/nuvoton/numaker-pfm-m487/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..fe0ae941ae9a759ae478de901caec1c961e56af8 --- /dev/null +++ b/bsp/nuvoton/numaker-pfm-m487/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +Import('RTT_ROOT') + +cwd = str(Dir('#')) +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/nuvoton/numaker-pfm-m487/SConstruct b/bsp/nuvoton/numaker-pfm-m487/SConstruct new file mode 100644 index 0000000000000000000000000000000000000000..23d4cf0308d05ca6cf4a596f655487acb7aa8e82 --- /dev/null +++ b/bsp/nuvoton/numaker-pfm-m487/SConstruct @@ -0,0 +1,59 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +nuvoton_library = 'm480' +rtconfig.BSP_LIBRARY_TYPE = nuvoton_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, nuvoton_library, 'SConscript'))) + +# include nu_pkgs +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'nu_packages', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/nuvoton/numaker-pfm-m487/applications/SConscript b/bsp/nuvoton/numaker-pfm-m487/applications/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..9ffdbcd0f9f63b6274eef8adca91f951a1e0fe5f --- /dev/null +++ b/bsp/nuvoton/numaker-pfm-m487/applications/SConscript @@ -0,0 +1,11 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/nuvoton/numaker-pfm-m487/applications/main.c b/bsp/nuvoton/numaker-pfm-m487/applications/main.c new file mode 100644 index 0000000000000000000000000000000000000000..51dd121e74e2fac8cccfe074739c87f02345527a --- /dev/null +++ b/bsp/nuvoton/numaker-pfm-m487/applications/main.c @@ -0,0 +1,19 @@ +/**************************************************************************//** +* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-1-16 Wayne First version +* +******************************************************************************/ + +#include +#include +#include + +int main(int argc, char **argv) +{ + return 0; +} diff --git a/bsp/nuvoton/numaker-pfm-m487/applications/mnt.c b/bsp/nuvoton/numaker-pfm-m487/applications/mnt.c new file mode 100644 index 0000000000000000000000000000000000000000..64a219379b80f984d7a587fc53bd6966eb20d48d --- /dev/null +++ b/bsp/nuvoton/numaker-pfm-m487/applications/mnt.c @@ -0,0 +1,143 @@ +/**************************************************************************//** +* +* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-1-16 Wayne First version +* +******************************************************************************/ + +#include + +#if defined(RT_USING_DFS) + #include + #include +#endif + +#if defined(PKG_USING_FAL) + #include +#endif + +#if defined(BOARD_USING_STORAGE_SPIFLASH) + #define MOUNT_POINT_SPIFLASH0 "/" +#endif + +#if defined(BOARD_USING_STORAGE_SPIFLASH) + +#if defined(RT_USB_DEVICE_MSTORAGE) +int mnt_init_spiflash0(void) +{ + rt_kprintf("Sorry, you enabled RT_USB_DEVICE_MSTORAGE option in menu, so we won't mount flash0 on /.\n"); + return 0; +} +#else + +/* Recursive mkdir */ +#if defined(RT_USBH_MSTORAGE) && defined(UDISK_MOUNTPOINT) +static int mkdir_p(const char *dir, const mode_t mode) +{ + int ret = -1; + char *tmp = NULL; + char *p = NULL; + struct stat sb; + rt_size_t len; + + if (!dir) + goto exit_mkdir_p; + + /* Copy path */ + /* Get the string length */ + len = strlen(dir); + tmp = rt_strdup(dir); + + /* Remove trailing slash */ + if (tmp[len - 1] == '/') + { + tmp[len - 1] = '\0'; + len--; + } + + /* check if path exists and is a directory */ + if (stat(tmp, &sb) == 0) + { + if (S_ISDIR(sb.st_mode)) + { + ret = 0; + goto exit_mkdir_p; + } + } + + /* Recursive mkdir */ + for (p = tmp + 1; p - tmp <= len; p++) + { + if ((*p == '/') || (p - tmp == len)) + { + *p = 0; + + /* Test path */ + if (stat(tmp, &sb) != 0) + { + /* Path does not exist - create directory */ + if (mkdir(tmp, mode) < 0) + { + goto exit_mkdir_p; + } + } + else if (!S_ISDIR(sb.st_mode)) + { + /* Not a directory */ + goto exit_mkdir_p; + } + if (p - tmp != len) + *p = '/'; + } + } + + ret = 0; + +exit_mkdir_p: + + if (tmp) + rt_free(tmp); + + return ret; +} +#endif + +int mnt_init_spiflash0(void) +{ + if (dfs_mount("flash0", MOUNT_POINT_SPIFLASH0, "elm", 0, 0) != 0) + { + rt_kprintf("Failed to mount elm on %s.\n", MOUNT_POINT_SPIFLASH0); + rt_kprintf("Try to execute 'mkfs -t elm flash0' first, then reboot.\n"); + goto exit_mnt_init_spiflash0; + } + rt_kprintf("mount flash0 with elmfat type: ok\n"); + +#if defined(RT_USBH_MSTORAGE) && defined(UDISK_MOUNTPOINT) + if (mkdir_p(UDISK_MOUNTPOINT, 0) < 0) + { + rt_kprintf("Failed to create directory on %s for RT_USBH_MSTORAGE.\n", UDISK_MOUNTPOINT); + } +#endif + +exit_mnt_init_spiflash0: + + return 0; +} +#endif +INIT_ENV_EXPORT(mnt_init_spiflash0); +#endif + +#if defined(PKG_USING_FAL) +int mnt_init_fal(void) +{ + fal_init(); + return 0; +} +INIT_ENV_EXPORT(mnt_init_fal); +#endif + diff --git a/bsp/nuvoton/numaker-pfm-m487/board/Kconfig b/bsp/nuvoton/numaker-pfm-m487/board/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..fc56305c9ded49df88164c18bf4a45135a215681 --- /dev/null +++ b/bsp/nuvoton/numaker-pfm-m487/board/Kconfig @@ -0,0 +1,165 @@ +menu "Hardware Drivers Config" + + menu "On-chip Peripheral Drivers" + source "$BSP_DIR/../libraries/m480/rtt_port/Kconfig" + endmenu + + menu "On-board Peripheral Drivers" + + config BSP_USING_NULINKME + bool "Enable UART0 for RTT Console(uart0)" + select BSP_USING_UART + select BSP_USING_UART0 + default y + + config BOARD_USING_IP101GR + bool "Enable ethernet phy supporting(over emac/mdio)" + select BSP_USING_EMAC + default n + + config BOARD_USING_NAU88L25 + bool "NAU88L25 Audio Codec supporting(over i2s, i2c2)" + select NU_PKG_USING_NAU88L25 + select BSP_USING_I2C2 + select BSP_USING_I2S + select BSP_USING_I2S0 + default n + + config BOARD_USING_STORAGE_SDCARD + bool "SDCARD supporting(over sdh0)" + select BSP_USING_SDH + select BSP_USING_SDH0 + default n + + config BOARD_USING_STORAGE_SPIFLASH + bool "SPIFLASH supporting(over qspi0)" + select BSP_USING_QSPI + select BSP_USING_QSPI0 + default y + + choice + prompt "Select FS/HS USB Ports" + + config BOARD_USING_HSUSBD + select BSP_USING_HSUSBD + bool "Enable HSUSBD(over USB2.0)" + help + Choose this option if you need HSUSBD function mode. + + config BOARD_USING_HSUSBD_USBH + select BSP_USING_USBH + select BSP_USING_HSUSBD + bool "Enable HSUSBD(over USB2.0) and USBH(over USB1.1)" + help + Choose this option if you need HSUSBD and USBH function mode at the same time. + + config BOARD_USING_HSUSBH + select BSP_USING_HSUSBH + bool "Enable HSUSBH(over USB2.0)" + help + Choose this option if you need HSUSBH function mode. + + config BOARD_USING_HSUSBH_USBD + select BSP_USING_HSUSBH + select BSP_USING_USBD + bool "Enable HSUSBH(over USB2.0) and USBD(over USB1.1)" + help + Choose this option if you need HSUSBH and USBD function mode at the same time. + + config BOARD_USING_HSOTG + select BSP_USING_HSOTG + bool "Enable HSOTG(over USB2.0)" + help + Choose this option if you need HSOTG function mode. + + endchoice + + endmenu + + menu "Board extended module drivers" + + config BOARD_USING_ADVANCE_V4 + bool "Use BOARD_USING_ADVANCE_V4 board" + default n + + if BOARD_USING_ADVANCE_V4 + + config BOARD_USING_MAX31875 + bool "MAX31875 Temperature sensor(over i2c1)" + select NU_PKG_USING_MAX31875 + select BSP_USING_I2C1 + default n + + config BOARD_USING_MPU6500 + bool "MPU6500 6-axis sensor(over i2c2)" + select PKG_USING_SENSORS_DRIVERS + select PKG_USING_MPU6XXX + select PKG_USING_MPU6XXX_LATEST_VERSION + select PKG_USING_MPU6XXX_ACCE + select PKG_USING_MPU6XXX_GYRO + select BSP_USING_I2C2 + default n + + config BOARD_USING_LCD_ILI9341 + bool "LCD ILI9341(over ebi0)" + select NU_PKG_USING_ILI9341 + select NU_PKG_USING_ILI9341_EBI + default n + + if BOARD_USING_LCD_ILI9341 + + config BOARD_USING_ILI9341_EBI_PORT + int "Specify EBI port index" + range 0 2 + default 0 + + config BOARD_USING_ILI9341_PIN_BACKLIGHT + int "Specify the pin index of backlight pin index" + range 0 127 + default 23 + + config BOARD_USING_ILI9341_PIN_RESET + int "Specify the pin index of reset pin index" + range 0 127 + default 22 + + config BOARD_USING_ILI9341_PIN_DC + int "Specify the pin index of data&command switching" + range 0 127 + default 115 + + endif + + config BOARD_USING_AT24LC64 + bool "AT24LC64 EEPROM(over i2c2)" + select BSP_USING_I2C + select BSP_USING_I2C2 + select PKG_USING_AT24CXX + default n + + config BOARD_USING_SRAM0_AS_MEMHEAP + bool "EBI SRAM supporting(over ebi1)" + select BSP_USING_EBI + select RT_USING_MEMHEAP + select RT_USING_MEMHEAP_AS_HEAP + default n + + if BOARD_USING_SRAM0_AS_MEMHEAP + config NU_EBI_SRAM0_SIZE + hex "SRAM capacity(In byte)" + range 0x200 0x100000 + default 0x80000 + depends on BSP_USING_EBI_BANK0 + endif + + config BOARD_USING_BUZZER + bool "BUZZER.(over bpwm0_ch5)" + select BSP_USING_BPWM + select BSP_USING_BPWM0 + default n + + endif + + endmenu + +endmenu diff --git a/bsp/nuvoton/numaker-pfm-m487/board/NuClockConfig/nutool_clkcfg.h b/bsp/nuvoton/numaker-pfm-m487/board/NuClockConfig/nutool_clkcfg.h new file mode 100644 index 0000000000000000000000000000000000000000..950b09946e24237cd387a6e19ff8439707aeb07f --- /dev/null +++ b/bsp/nuvoton/numaker-pfm-m487/board/NuClockConfig/nutool_clkcfg.h @@ -0,0 +1,26 @@ +/**************************************************************************** + * @file nutool_clkcfg.h + * @version V1.05 + * @Date 2020/04/15-11:28:38 + * @brief NuMicro generated code file + * + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#ifndef __NUTOOL_CLKCFG_H__ +#define __NUTOOL_CLKCFG_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif +#undef __HXT +#define __HXT (12000000UL) /*!< High Speed External Crystal Clock Frequency */ + +#ifdef __cplusplus +} +#endif +#endif /*__NUTOOL_CLKCFG_H__*/ + +/*** (C) COPYRIGHT 2013-2020 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/numaker-pfm-m487/board/NuClockConfig/nutool_modclkcfg.c b/bsp/nuvoton/numaker-pfm-m487/board/NuClockConfig/nutool_modclkcfg.c new file mode 100644 index 0000000000000000000000000000000000000000..59af4901f984104a810d91666c33bb421932efd2 --- /dev/null +++ b/bsp/nuvoton/numaker-pfm-m487/board/NuClockConfig/nutool_modclkcfg.c @@ -0,0 +1,1153 @@ +/**************************************************************************** + * @file nutool_modclkcfg.c + * @version V1.05 + * @Date 2020/04/15-11:28:38 + * @brief NuMicro generated code file + * + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +/******************** +MCU:M487JIDAE(LQFP144) +Base Clocks: +HIRC:12MHz +LXT:32.7680kHz +HXT:12MHz +PLL:192MHz +HSUSB_OTG_PHY:30MHz +HCLK:192MHz +PCLK0:96MHz +PCLK1:96MHz +Enabled-Module Frequencies: +ACMP01=Bus Clock(PCLK1):96MHz +BPWM0=Bus Clock(PCLK0):96MHz/Engine Clock:96MHz +BPWM1=Bus Clock(PCLK1):96MHz/Engine Clock:96MHz +CAN0=Bus Clock(PCLK0):96MHz +CAN1=Bus Clock(PCLK1):96MHz +CRC=Bus Clock(HCLK):192MHz +CRPT=Bus Clock(HCLK):192MHz +DAC=Bus Clock(PCLK1):96MHz +EADC=Bus Clock(PCLK1):96MHz/Engine Clock:12MHz +EBI=Bus Clock(HCLK):192MHz +ECAP0=Bus Clock(PCLK0):96MHz +ECAP1=Bus Clock(PCLK1):96MHz +EMAC=Bus Clock(HCLK):192MHz/Engine Clock:1.5118MHz +EPWM0=Bus Clock(PCLK0):96MHz/Engine Clock:96MHz +EPWM1=Bus Clock(PCLK1):96MHz/Engine Clock:96MHz +FMCIDLE=Bus Clock(HCLK):192MHz/Engine Clock:12MHz +HSOTG=Bus Clock(PCLK1):96MHz/Engine Clock:30MHz +HSUSBD=Bus Clock(HCLK):192MHz/Engine Clock:30MHz +HSUSBH=Bus Clock(HCLK):192MHz/Engine Clock:30MHz +I2C0=Bus Clock(PCLK0):96MHz +I2C1=Bus Clock(PCLK1):96MHz +I2C2=Bus Clock(PCLK0):96MHz +I2S0=Bus Clock(PCLK0):96MHz/Engine Clock:12MHz +ISP=Bus Clock(HCLK):192MHz/Engine Clock:12MHz +OPA=Bus Clock(PCLK0):96MHz +OTG=Bus Clock(PCLK1):96MHz/Engine Clock:192MHz +PDMA=Bus Clock(HCLK):192MHz +QEI0=Bus Clock(PCLK0):96MHz +QEI1=Bus Clock(PCLK1):96MHz +QSPI0=Bus Clock(PCLK0):96MHz/Engine Clock:96MHz +RTC=Bus Clock(PCLK1):96MHz/Engine Clock:32.7680kHz +SC0=Bus Clock(PCLK0):96MHz/Engine Clock:12MHz +SC1=Bus Clock(PCLK1):96MHz/Engine Clock:12MHz +SC2=Bus Clock(PCLK0):96MHz/Engine Clock:12MHz +SDH0=Bus Clock(HCLK):192MHz/Engine Clock:192MHz +SDH1=Bus Clock(HCLK):192MHz/Engine Clock:192MHz +SPI0=Bus Clock(PCLK1):96MHz/Engine Clock:96MHz +SPI1=Bus Clock(PCLK0):96MHz/Engine Clock:96MHz +SPI2=Bus Clock(PCLK1):96MHz/Engine Clock:96MHz +SPI3=Bus Clock(PCLK0):96MHz/Engine Clock:96MHz +SPIM=Bus Clock(HCLK):192MHz +SYSTICK=Bus Clock(HCLK):192MHz/Engine Clock:192MHz +TMR0=Bus Clock(PCLK0):96MHz/Engine Clock:12MHz +TMR1=Bus Clock(PCLK0):96MHz/Engine Clock:12MHz +TMR2=Bus Clock(PCLK1):96MHz/Engine Clock:12MHz +TMR3=Bus Clock(PCLK1):96MHz/Engine Clock:12MHz +UART0=Bus Clock(PCLK0):96MHz/Engine Clock:12MHz +UART1=Bus Clock(PCLK1):96MHz/Engine Clock:12MHz +UART2=Bus Clock(PCLK0):96MHz/Engine Clock:12MHz +UART3=Bus Clock(PCLK1):96MHz/Engine Clock:12MHz +UART4=Bus Clock(PCLK0):96MHz/Engine Clock:12MHz +UART5=Bus Clock(PCLK1):96MHz/Engine Clock:12MHz +USBD=Bus Clock(PCLK0):96MHz/Engine Clock:48MHz +USBH=Bus Clock(HCLK):192MHz/Engine Clock:48MHz +USCI0=Bus Clock(PCLK0):96MHz +USCI1=Bus Clock(PCLK1):96MHz +WDT=Bus Clock(PCLK0):96MHz/Engine Clock:32.7680kHz +WWDT=Bus Clock(PCLK0):96MHz/Engine Clock:93.7500kHz +********************/ + +#include "M480.h" +#include "rtconfig.h" + +void nutool_modclkcfg_init_acmp01(void) +{ + CLK_EnableModuleClock(ACMP01_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_acmp01(void) +{ + CLK_DisableModuleClock(ACMP01_MODULE); + + return; +} + +void nutool_modclkcfg_init_bpwm0(void) +{ + CLK_EnableModuleClock(BPWM0_MODULE); + CLK_SetModuleClock(BPWM0_MODULE, CLK_CLKSEL2_BPWM0SEL_PCLK0, MODULE_NoMsk); + + return; +} + +void nutool_modclkcfg_deinit_bpwm0(void) +{ + CLK_DisableModuleClock(BPWM0_MODULE); + + return; +} + +void nutool_modclkcfg_init_bpwm1(void) +{ + CLK_EnableModuleClock(BPWM1_MODULE); + CLK_SetModuleClock(BPWM1_MODULE, CLK_CLKSEL2_BPWM1SEL_PCLK1, MODULE_NoMsk); + + return; +} + +void nutool_modclkcfg_deinit_bpwm1(void) +{ + CLK_DisableModuleClock(BPWM1_MODULE); + + return; +} + +void nutool_modclkcfg_init_can0(void) +{ + CLK_EnableModuleClock(CAN0_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_can0(void) +{ + CLK_DisableModuleClock(CAN0_MODULE); + + return; +} + +void nutool_modclkcfg_init_can1(void) +{ + CLK_EnableModuleClock(CAN1_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_can1(void) +{ + CLK_DisableModuleClock(CAN1_MODULE); + + return; +} + +void nutool_modclkcfg_init_crc(void) +{ + CLK_EnableModuleClock(CRC_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_crc(void) +{ + CLK_DisableModuleClock(CRC_MODULE); + + return; +} + +void nutool_modclkcfg_init_crpt(void) +{ + CLK_EnableModuleClock(CRPT_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_crpt(void) +{ + CLK_DisableModuleClock(CRPT_MODULE); + + return; +} + +void nutool_modclkcfg_init_dac(void) +{ + CLK_EnableModuleClock(DAC_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_dac(void) +{ + CLK_DisableModuleClock(DAC_MODULE); + + return; +} + +void nutool_modclkcfg_init_eadc(void) +{ + CLK_EnableModuleClock(EADC_MODULE); + CLK_SetModuleClock(EADC_MODULE, MODULE_NoMsk, CLK_CLKDIV0_EADC(8)); + + return; +} + +void nutool_modclkcfg_deinit_eadc(void) +{ + CLK_DisableModuleClock(EADC_MODULE); + + return; +} + +void nutool_modclkcfg_init_ebi(void) +{ + CLK_EnableModuleClock(EBI_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_ebi(void) +{ + CLK_DisableModuleClock(EBI_MODULE); + + return; +} + +void nutool_modclkcfg_init_ecap0(void) +{ + CLK_EnableModuleClock(ECAP0_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_ecap0(void) +{ + CLK_DisableModuleClock(ECAP0_MODULE); + + return; +} + +void nutool_modclkcfg_init_ecap1(void) +{ + CLK_EnableModuleClock(ECAP1_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_ecap1(void) +{ + CLK_DisableModuleClock(ECAP1_MODULE); + + return; +} + +void nutool_modclkcfg_init_emac(void) +{ + CLK_EnableModuleClock(EMAC_MODULE); + CLK_SetModuleClock(EMAC_MODULE, MODULE_NoMsk, CLK_CLKDIV3_EMAC(127)); + + return; +} + +void nutool_modclkcfg_deinit_emac(void) +{ + CLK_DisableModuleClock(EMAC_MODULE); + + return; +} + +void nutool_modclkcfg_init_epwm0(void) +{ + CLK_EnableModuleClock(EPWM0_MODULE); + CLK_SetModuleClock(EPWM0_MODULE, CLK_CLKSEL2_EPWM0SEL_PCLK0, MODULE_NoMsk); + + return; +} + +void nutool_modclkcfg_deinit_epwm0(void) +{ + CLK_DisableModuleClock(EPWM0_MODULE); + + return; +} + +void nutool_modclkcfg_init_epwm1(void) +{ + CLK_EnableModuleClock(EPWM1_MODULE); + CLK_SetModuleClock(EPWM1_MODULE, CLK_CLKSEL2_EPWM1SEL_PCLK1, MODULE_NoMsk); + + return; +} + +void nutool_modclkcfg_deinit_epwm1(void) +{ + CLK_DisableModuleClock(EPWM1_MODULE); + + return; +} + +void nutool_modclkcfg_init_fmcidle(void) +{ + CLK_EnableModuleClock(FMCIDLE_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_fmcidle(void) +{ + CLK_DisableModuleClock(FMCIDLE_MODULE); + + return; +} + +void nutool_modclkcfg_init_hsotg(void) +{ + CLK_EnableModuleClock(HSOTG_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_hsotg(void) +{ + CLK_DisableModuleClock(HSOTG_MODULE); + + return; +} + +void nutool_modclkcfg_init_hsusbd(void) +{ + CLK_EnableModuleClock(HSUSBD_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_hsusbd(void) +{ + CLK_DisableModuleClock(HSUSBD_MODULE); + + return; +} + +void nutool_modclkcfg_init_i2c0(void) +{ + CLK_EnableModuleClock(I2C0_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_i2c0(void) +{ + CLK_DisableModuleClock(I2C0_MODULE); + + return; +} + +void nutool_modclkcfg_init_i2c1(void) +{ + CLK_EnableModuleClock(I2C1_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_i2c1(void) +{ + CLK_DisableModuleClock(I2C1_MODULE); + + return; +} + +void nutool_modclkcfg_init_i2c2(void) +{ + CLK_EnableModuleClock(I2C2_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_i2c2(void) +{ + CLK_DisableModuleClock(I2C2_MODULE); + + return; +} + +void nutool_modclkcfg_init_i2s0(void) +{ + CLK_EnableModuleClock(I2S0_MODULE); + CLK_SetModuleClock(I2S0_MODULE, CLK_CLKSEL3_I2S0SEL_HXT, MODULE_NoMsk); + + return; +} + +void nutool_modclkcfg_deinit_i2s0(void) +{ + CLK_DisableModuleClock(I2S0_MODULE); + + return; +} + +void nutool_modclkcfg_init_isp(void) +{ + CLK_EnableModuleClock(ISP_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_isp(void) +{ + CLK_DisableModuleClock(ISP_MODULE); + + return; +} + +void nutool_modclkcfg_init_opa(void) +{ + CLK_EnableModuleClock(OPA_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_opa(void) +{ + CLK_DisableModuleClock(OPA_MODULE); + + return; +} + +void nutool_modclkcfg_init_otg(void) +{ + CLK_EnableModuleClock(OTG_MODULE); + CLK_SetModuleClock(OTG_MODULE, MODULE_NoMsk, CLK_CLKDIV0_USB(1)); + + return; +} + +void nutool_modclkcfg_deinit_otg(void) +{ + CLK_DisableModuleClock(OTG_MODULE); + + return; +} + +void nutool_modclkcfg_init_pdma(void) +{ + CLK_EnableModuleClock(PDMA_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_pdma(void) +{ + CLK_DisableModuleClock(PDMA_MODULE); + + return; +} + +void nutool_modclkcfg_init_qei0(void) +{ + CLK_EnableModuleClock(QEI0_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_qei0(void) +{ + CLK_DisableModuleClock(QEI0_MODULE); + + return; +} + +void nutool_modclkcfg_init_qei1(void) +{ + CLK_EnableModuleClock(QEI1_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_qei1(void) +{ + CLK_DisableModuleClock(QEI1_MODULE); + + return; +} + +void nutool_modclkcfg_init_qspi0(void) +{ + CLK_EnableModuleClock(QSPI0_MODULE); + CLK_SetModuleClock(QSPI0_MODULE, CLK_CLKSEL2_QSPI0SEL_PCLK0, MODULE_NoMsk); + + return; +} + +void nutool_modclkcfg_deinit_qspi0(void) +{ + CLK_DisableModuleClock(QSPI0_MODULE); + + return; +} + +void nutool_modclkcfg_init_rtc(void) +{ + CLK_EnableModuleClock(RTC_MODULE); + CLK_SetModuleClock(RTC_MODULE, CLK_CLKSEL3_RTCSEL_LXT, MODULE_NoMsk); + + return; +} + +void nutool_modclkcfg_deinit_rtc(void) +{ + CLK_DisableModuleClock(RTC_MODULE); + + return; +} + +void nutool_modclkcfg_init_sc0(void) +{ + CLK_EnableModuleClock(SC0_MODULE); + CLK_SetModuleClock(SC0_MODULE, CLK_CLKSEL3_SC0SEL_HXT, CLK_CLKDIV1_SC0(1)); + + return; +} + +void nutool_modclkcfg_deinit_sc0(void) +{ + CLK_DisableModuleClock(SC0_MODULE); + + return; +} + +void nutool_modclkcfg_init_sc1(void) +{ + CLK_EnableModuleClock(SC1_MODULE); + CLK_SetModuleClock(SC1_MODULE, CLK_CLKSEL3_SC1SEL_HXT, CLK_CLKDIV1_SC1(1)); + + return; +} + +void nutool_modclkcfg_deinit_sc1(void) +{ + CLK_DisableModuleClock(SC1_MODULE); + + return; +} + +void nutool_modclkcfg_init_sc2(void) +{ + CLK_EnableModuleClock(SC2_MODULE); + CLK_SetModuleClock(SC2_MODULE, CLK_CLKSEL3_SC2SEL_HXT, CLK_CLKDIV1_SC2(1)); + + return; +} + +void nutool_modclkcfg_deinit_sc2(void) +{ + CLK_DisableModuleClock(SC2_MODULE); + + return; +} + +void nutool_modclkcfg_init_sdh0(void) +{ + CLK_EnableModuleClock(SDH0_MODULE); + CLK_SetModuleClock(SDH0_MODULE, CLK_CLKSEL0_SDH0SEL_HCLK, CLK_CLKDIV0_SDH0(1)); + + return; +} + +void nutool_modclkcfg_deinit_sdh0(void) +{ + CLK_DisableModuleClock(SDH0_MODULE); + + return; +} + +void nutool_modclkcfg_init_sdh1(void) +{ + CLK_EnableModuleClock(SDH1_MODULE); + CLK_SetModuleClock(SDH1_MODULE, CLK_CLKSEL0_SDH1SEL_HCLK, CLK_CLKDIV3_SDH1(1)); + + return; +} + +void nutool_modclkcfg_deinit_sdh1(void) +{ + CLK_DisableModuleClock(SDH1_MODULE); + + return; +} + +void nutool_modclkcfg_init_spi0(void) +{ + CLK_EnableModuleClock(SPI0_MODULE); + CLK_SetModuleClock(SPI0_MODULE, CLK_CLKSEL2_SPI0SEL_PCLK1, MODULE_NoMsk); + + return; +} + +void nutool_modclkcfg_deinit_spi0(void) +{ + CLK_DisableModuleClock(SPI0_MODULE); + + return; +} + +void nutool_modclkcfg_init_spi1(void) +{ + CLK_EnableModuleClock(SPI1_MODULE); + CLK_SetModuleClock(SPI1_MODULE, CLK_CLKSEL2_SPI1SEL_PCLK0, MODULE_NoMsk); + + return; +} + +void nutool_modclkcfg_deinit_spi1(void) +{ + CLK_DisableModuleClock(SPI1_MODULE); + + return; +} + +void nutool_modclkcfg_init_spi2(void) +{ + CLK_EnableModuleClock(SPI2_MODULE); + CLK_SetModuleClock(SPI2_MODULE, CLK_CLKSEL2_SPI2SEL_PCLK1, MODULE_NoMsk); + + return; +} + +void nutool_modclkcfg_deinit_spi2(void) +{ + CLK_DisableModuleClock(SPI2_MODULE); + + return; +} + +void nutool_modclkcfg_init_spi3(void) +{ + CLK_EnableModuleClock(SPI3_MODULE); + CLK_SetModuleClock(SPI3_MODULE, CLK_CLKSEL2_SPI3SEL_PCLK0, MODULE_NoMsk); + + return; +} + +void nutool_modclkcfg_deinit_spi3(void) +{ + CLK_DisableModuleClock(SPI3_MODULE); + + return; +} + +void nutool_modclkcfg_init_spim(void) +{ + CLK_EnableModuleClock(SPIM_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_spim(void) +{ + CLK_DisableModuleClock(SPIM_MODULE); + + return; +} + +void nutool_modclkcfg_init_systick(void) +{ + CLK_EnableSysTick(CLK_CLKSEL0_STCLKSEL_HCLK, 0); + + return; +} + +void nutool_modclkcfg_deinit_systick(void) +{ + CLK_DisableSysTick(); + + return; +} + +void nutool_modclkcfg_init_tmr0(void) +{ + CLK_EnableModuleClock(TMR0_MODULE); + CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_HXT, MODULE_NoMsk); + + return; +} + +void nutool_modclkcfg_deinit_tmr0(void) +{ + CLK_DisableModuleClock(TMR0_MODULE); + + return; +} + +void nutool_modclkcfg_init_tmr1(void) +{ + CLK_EnableModuleClock(TMR1_MODULE); + CLK_SetModuleClock(TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_HXT, MODULE_NoMsk); + + return; +} + +void nutool_modclkcfg_deinit_tmr1(void) +{ + CLK_DisableModuleClock(TMR1_MODULE); + + return; +} + +void nutool_modclkcfg_init_tmr2(void) +{ + CLK_EnableModuleClock(TMR2_MODULE); + CLK_SetModuleClock(TMR2_MODULE, CLK_CLKSEL1_TMR2SEL_HXT, MODULE_NoMsk); + + return; +} + +void nutool_modclkcfg_deinit_tmr2(void) +{ + CLK_DisableModuleClock(TMR2_MODULE); + + return; +} + +void nutool_modclkcfg_init_tmr3(void) +{ + CLK_EnableModuleClock(TMR3_MODULE); + CLK_SetModuleClock(TMR3_MODULE, CLK_CLKSEL1_TMR3SEL_HXT, MODULE_NoMsk); + + return; +} + +void nutool_modclkcfg_deinit_tmr3(void) +{ + CLK_DisableModuleClock(TMR3_MODULE); + + return; +} + +void nutool_modclkcfg_init_uart0(void) +{ + CLK_EnableModuleClock(UART0_MODULE); + CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART0SEL_HXT, CLK_CLKDIV0_UART0(1)); + + return; +} + +void nutool_modclkcfg_deinit_uart0(void) +{ + CLK_DisableModuleClock(UART0_MODULE); + + return; +} + +void nutool_modclkcfg_init_uart1(void) +{ + CLK_EnableModuleClock(UART1_MODULE); + CLK_SetModuleClock(UART1_MODULE, CLK_CLKSEL1_UART1SEL_HXT, CLK_CLKDIV0_UART1(1)); + + return; +} + +void nutool_modclkcfg_deinit_uart1(void) +{ + CLK_DisableModuleClock(UART1_MODULE); + + return; +} + +void nutool_modclkcfg_init_uart2(void) +{ + CLK_EnableModuleClock(UART2_MODULE); + CLK_SetModuleClock(UART2_MODULE, CLK_CLKSEL3_UART2SEL_HXT, CLK_CLKDIV4_UART2(1)); + + return; +} + +void nutool_modclkcfg_deinit_uart2(void) +{ + CLK_DisableModuleClock(UART2_MODULE); + + return; +} + +void nutool_modclkcfg_init_uart3(void) +{ + CLK_EnableModuleClock(UART3_MODULE); + CLK_SetModuleClock(UART3_MODULE, CLK_CLKSEL3_UART3SEL_HXT, CLK_CLKDIV4_UART3(1)); + + return; +} + +void nutool_modclkcfg_deinit_uart3(void) +{ + CLK_DisableModuleClock(UART3_MODULE); + + return; +} + +void nutool_modclkcfg_init_uart4(void) +{ + CLK_EnableModuleClock(UART4_MODULE); + CLK_SetModuleClock(UART4_MODULE, CLK_CLKSEL3_UART4SEL_HXT, CLK_CLKDIV4_UART4(1)); + + return; +} + +void nutool_modclkcfg_deinit_uart4(void) +{ + CLK_DisableModuleClock(UART4_MODULE); + + return; +} + +void nutool_modclkcfg_init_uart5(void) +{ + CLK_EnableModuleClock(UART5_MODULE); + CLK_SetModuleClock(UART5_MODULE, CLK_CLKSEL3_UART5SEL_HXT, CLK_CLKDIV4_UART5(1)); + + return; +} + +void nutool_modclkcfg_deinit_uart5(void) +{ + CLK_DisableModuleClock(UART5_MODULE); + + return; +} + +void nutool_modclkcfg_init_usbd(void) +{ + CLK_EnableModuleClock(USBD_MODULE); + CLK_SetModuleClock(USBD_MODULE, CLK_CLKSEL0_USBSEL_PLL, CLK_CLKDIV0_USB(4)); + + return; +} + +void nutool_modclkcfg_deinit_usbd(void) +{ + CLK_DisableModuleClock(USBD_MODULE); + + return; +} + +void nutool_modclkcfg_init_usbh(void) +{ + CLK_EnableModuleClock(USBH_MODULE); + CLK_SetModuleClock(USBH_MODULE, CLK_CLKSEL0_USBSEL_PLL, CLK_CLKDIV0_USB(4)); + + return; +} + +void nutool_modclkcfg_deinit_usbh(void) +{ + CLK_DisableModuleClock(USBH_MODULE); + + return; +} + +void nutool_modclkcfg_init_usci0(void) +{ + CLK_EnableModuleClock(USCI0_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_usci0(void) +{ + CLK_DisableModuleClock(USCI0_MODULE); + + return; +} + +void nutool_modclkcfg_init_usci1(void) +{ + CLK_EnableModuleClock(USCI1_MODULE); + + return; +} + +void nutool_modclkcfg_deinit_usci1(void) +{ + CLK_DisableModuleClock(USCI1_MODULE); + + return; +} + +void nutool_modclkcfg_init_wdt(void) +{ + CLK_EnableModuleClock(WDT_MODULE); + CLK_SetModuleClock(WDT_MODULE, CLK_CLKSEL1_WDTSEL_LXT, MODULE_NoMsk); + + return; +} + +void nutool_modclkcfg_deinit_wdt(void) +{ + CLK_DisableModuleClock(WDT_MODULE); + + return; +} + +void nutool_modclkcfg_init_wwdt(void) +{ + CLK_EnableModuleClock(WWDT_MODULE); + CLK_SetModuleClock(WWDT_MODULE, CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048, MODULE_NoMsk); + + return; +} + +void nutool_modclkcfg_deinit_wwdt(void) +{ + CLK_DisableModuleClock(WWDT_MODULE); + + return; +} + +void nutool_modclkcfg_init_base(void) +{ + /* Set XT1_OUT(PF.2) and XT1_IN(PF.3) to input mode */ + PF->MODE &= ~(GPIO_MODE_MODE2_Msk | GPIO_MODE_MODE3_Msk); + + /* Enable clock source */ + CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk | CLK_PWRCTL_LXTEN_Msk | CLK_PWRCTL_HXTEN_Msk); + + /* Waiting for clock source ready */ + CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk | CLK_STATUS_LXTSTB_Msk | CLK_STATUS_HXTSTB_Msk); + + /* Disable PLL first to avoid unstable when setting PLL */ + CLK_DisablePLL(); + + /* Set PLL frequency */ + CLK->PLLCTL = (CLK->PLLCTL & ~(0x000FFFFFul)) | 0x0000421Eul; + + /* Waiting for PLL ready */ + CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk); + + /* If the defines do not exist in your project, please refer to the related clk.h in the Header folder appended to the tool package. */ + /* Set HCLK clock */ + CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL, CLK_CLKDIV0_HCLK(1)); + + /* Set PCLK-related clock */ + CLK->PCLKDIV = (CLK_PCLKDIV_PCLK0DIV2 | CLK_PCLKDIV_PCLK1DIV2); + + return; +} + +void nutool_modclkcfg_init(void) +{ + /*---------------------------------------------------------------------------------------------------------*/ + /* Init System Clock */ + /*---------------------------------------------------------------------------------------------------------*/ + //CLK->PWRCTL = (CLK->PWRCTL & ~(0x0000000Ful)) | 0x00000017ul; + //CLK->PLLCTL = (CLK->PLLCTL & ~(0x000FFFFFul)) | 0x0000421Eul; + //CLK->CLKDIV0 = (CLK->CLKDIV0 & ~(0xFFFFFFFFul)) | 0x00070000ul; + //CLK->CLKDIV1 = (CLK->CLKDIV1 & ~(0x00FFFFFFul)) | 0x00000000ul; + //CLK->CLKDIV3 = (CLK->CLKDIV3 & ~(0xFFFF0000ul)) | 0x007E0000ul; + //CLK->CLKDIV4 = (CLK->CLKDIV4 & ~(0x0000FFFFul)) | 0x00000000ul; + //CLK->PCLKDIV = (CLK->PCLKDIV & ~(0x00000077ul)) | 0x00000011ul; + //CLK->CLKSEL0 = (CLK->CLKSEL0 & ~(0x00F0003Ful)) | 0x00A30102ul; + //CLK->CLKSEL1 = (CLK->CLKSEL1 & ~(0xFF777703ul)) | 0xB0000001ul; + //CLK->CLKSEL2 = (CLK->CLKSEL2 & ~(0x00003FFFul)) | 0x00002BABul; + //CLK->CLKSEL3 = (CLK->CLKSEL3 & ~(0xFF03023Ful)) | 0x00000000ul; + //CLK->AHBCLK = (CLK->AHBCLK & ~(0x0003D4EEul)) | 0x0003D4EEul; + //CLK->APBCLK0 = (CLK->APBCLK0 & ~(0x7F3FF7FFul)) | 0x7F3FF7BFul; + //CLK->APBCLK1 = (CLK->APBCLK1 & ~(0x4CCF1347ul)) | 0x4CCF1347ul; + //CLK->CLKOCTL = (CLK->CLKOCTL & ~(0x0000007Ful)) | 0x00000000ul; + //SysTick->CTRL = (SysTick->CTRL & ~(0x00000005ul)) | 0x00000005ul; + + /* Unlock protected registers */ + SYS_UnlockReg(); + + /* Enable base clock */ + nutool_modclkcfg_init_base(); + + /* Enable module clock and set clock source */ +#if defined(BSP_USING_ACMP01) + nutool_modclkcfg_init_acmp01(); +#endif +#if defined(BSP_USING_BPWM0) + nutool_modclkcfg_init_bpwm0(); +#endif +#if defined(BSP_USING_BPWM1) + nutool_modclkcfg_init_bpwm1(); +#endif +#if defined(BSP_USING_CAN0) + nutool_modclkcfg_init_can0(); +#endif +#if defined(BSP_USING_CAN1) + nutool_modclkcfg_init_can1(); +#endif +#if defined(BSP_USING_CRC) + nutool_modclkcfg_init_crc(); +#endif +#if defined(BSP_USING_CRYPTO) + nutool_modclkcfg_init_crpt(); +#endif +#if defined(BSP_USING_DAC) + nutool_modclkcfg_init_dac(); +#endif +#if defined(BSP_USING_EADC) + nutool_modclkcfg_init_eadc(); +#endif +#if defined(BSP_USING_EBI) + nutool_modclkcfg_init_ebi(); +#endif +#if defined(BSP_USING_ECAP0) + nutool_modclkcfg_init_ecap0(); +#endif +#if defined(BSP_USING_ECAP1) + nutool_modclkcfg_init_ecap1(); +#endif +#if defined(BSP_USING_EMAC) + nutool_modclkcfg_init_emac(); +#endif +#if defined(BSP_USING_EPWM0) + nutool_modclkcfg_init_epwm0(); +#endif +#if defined(BSP_USING_EPWM1) + nutool_modclkcfg_init_epwm1(); +#endif +#if defined(BSP_USING_FMC) + nutool_modclkcfg_init_fmcidle(); +#endif +#if defined(BSP_USING_HSOTG) + nutool_modclkcfg_init_hsotg(); +#endif +#if defined(BSP_USING_HSUSBD) + nutool_modclkcfg_init_hsusbd(); +#endif +#if defined(BSP_USING_I2C0) + nutool_modclkcfg_init_i2c0(); +#endif +#if defined(BSP_USING_I2C1) + nutool_modclkcfg_init_i2c1(); +#endif +#if defined(BSP_USING_I2C2) + nutool_modclkcfg_init_i2c2(); +#endif +#if defined(BSP_USING_I2S) + nutool_modclkcfg_init_i2s0(); +#endif +#if defined(BSP_USING_FMC) + nutool_modclkcfg_init_isp(); +#endif +#if defined(BSP_USING_OPA) + nutool_modclkcfg_init_opa(); +#endif +#if defined(BSP_USING_OTG) || defined(BSP_USING_USBH) + nutool_modclkcfg_init_otg(); +#endif +#if defined(BSP_USING_PDMA) + nutool_modclkcfg_init_pdma(); +#endif +#if defined(BSP_USING_QEI0) + nutool_modclkcfg_init_qei0(); +#endif +#if defined(BSP_USING_QEI1) + nutool_modclkcfg_init_qei1(); +#endif +#if defined(BSP_USING_QSPI0) + nutool_modclkcfg_init_qspi0(); +#endif +#if defined(BSP_USING_RTC) + nutool_modclkcfg_init_rtc(); +#endif +#if defined(BSP_USING_SCUART0) + nutool_modclkcfg_init_sc0(); +#endif +#if defined(BSP_USING_SCUART1) + nutool_modclkcfg_init_sc1(); +#endif +#if defined(BSP_USING_SCUART2) + nutool_modclkcfg_init_sc2(); +#endif +#if defined(BSP_USING_SDH0) + nutool_modclkcfg_init_sdh0(); +#endif +#if defined(BSP_USING_SDH1) + nutool_modclkcfg_init_sdh1(); +#endif +#if defined(BSP_USING_SPI0) || defined(BSP_USING_SPII2S0) + nutool_modclkcfg_init_spi0(); +#endif +#if defined(BSP_USING_SPI1) || defined(BSP_USING_SPII2S1) + nutool_modclkcfg_init_spi1(); +#endif +#if defined(BSP_USING_SPI2) || defined(BSP_USING_SPII2S2) + nutool_modclkcfg_init_spi2(); +#endif +#if defined(BSP_USING_SPI3) || defined(BSP_USING_SPII2S3) + nutool_modclkcfg_init_spi3(); +#endif + nutool_modclkcfg_init_systick(); +#if defined(BSP_USING_TMR0) + nutool_modclkcfg_init_tmr0(); +#endif +#if defined(BSP_USING_TMR1) + nutool_modclkcfg_init_tmr1(); +#endif +#if defined(BSP_USING_TMR2) + nutool_modclkcfg_init_tmr2(); +#endif +#if defined(BSP_USING_TMR3) + nutool_modclkcfg_init_tmr3(); +#endif +#if defined(BSP_USING_UART0) + nutool_modclkcfg_init_uart0(); +#endif +#if defined(BSP_USING_UART1) + nutool_modclkcfg_init_uart1(); +#endif +#if defined(BSP_USING_UART2) + nutool_modclkcfg_init_uart2(); +#endif +#if defined(BSP_USING_UART3) + nutool_modclkcfg_init_uart3(); +#endif +#if defined(BSP_USING_UART4) + nutool_modclkcfg_init_uart4(); +#endif +#if defined(BSP_USING_UART5) + nutool_modclkcfg_init_uart5(); +#endif +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) + nutool_modclkcfg_init_usbd(); +#endif +#if defined(BSP_USING_USBH) || defined(BSP_USING_HSUSBH) + nutool_modclkcfg_init_usbh(); +#endif +#if defined(BSP_USING_USCI0) + nutool_modclkcfg_init_usci0(); +#endif +#if defined(BSP_USING_USCI1) + nutool_modclkcfg_init_usci1(); +#endif +#if defined(BSP_USING_WDT) + nutool_modclkcfg_init_wdt(); +#endif +#if defined(BSP_USING_WWDT) + nutool_modclkcfg_init_wwdt(); +#endif + + /* Update System Core Clock */ + /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */ + SystemCoreClockUpdate(); + + /* Lock protected registers */ + SYS_LockReg(); + + return; +} + +/*** (C) COPYRIGHT 2013-2020 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/numaker-pfm-m487/board/NuClockConfig/nutool_modclkcfg.cfg b/bsp/nuvoton/numaker-pfm-m487/board/NuClockConfig/nutool_modclkcfg.cfg new file mode 100644 index 0000000000000000000000000000000000000000..3805c0a7eb156b0e6d4f69c14bbfa32d9acb3d32 --- /dev/null +++ b/bsp/nuvoton/numaker-pfm-m487/board/NuClockConfig/nutool_modclkcfg.cfg @@ -0,0 +1,33 @@ +/**************************************************************************** + * @file nutool_modclkcfg.cfg + * @version V1.05 + * @Date 2020/04/15-11:28:42 + * @brief NuMicro clock config file + * + * @note Please do not modify this file. + * Otherwise, it may not be loaded successfully. + * Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +MCU:M487JIDAE(LQFP144) +Reg:CLKDIV0 = 0x00070000 +Reg:CLKDIV1 = 0x00000000 +Reg:CLKDIV3 = 0x007E0000 +Reg:CLKDIV4 = 0x00000000 +Reg:PCLKDIV = 0x00000011 +Reg:CLKSEL0 = 0x00A30102 +Reg:CLKSEL1 = 0xB0000001 +Reg:CLKSEL2 = 0x00002BAB +Reg:CLKSEL3 = 0x00000000 +Reg:PWRCTL = 0x00000017 +Reg:AHBCLK = 0x0003D4EE +Reg:APBCLK0 = 0x7F3FF7BF +Reg:APBCLK1 = 0x4CCF1347 +Reg:PLLCTL = 0x0000421E +Reg:CLKOCTL = 0x00000000 +Reg:SYST_CTRL = 0x00000005 +LXT:32768 +HXT:12000000 +PLL:192000000 +HSUSB_OTG_PHY:30000000 +Step:4 +/*** (C) COPYRIGHT 2013-2020 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/numaker-pfm-m487/board/NuClockConfig/nutool_modclkcfg.h b/bsp/nuvoton/numaker-pfm-m487/board/NuClockConfig/nutool_modclkcfg.h new file mode 100644 index 0000000000000000000000000000000000000000..9dde7925bbef2a53dfacc81e78bfc1703b3df903 --- /dev/null +++ b/bsp/nuvoton/numaker-pfm-m487/board/NuClockConfig/nutool_modclkcfg.h @@ -0,0 +1,139 @@ +/**************************************************************************** + * @file nutool_modclkcfg.h + * @version V1.05 + * @Date 2020/04/15-11:28:38 + * @brief NuMicro generated code file + * + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#ifndef __NUTOOL_MODCLKCFG_H__ +#define __NUTOOL_MODCLKCFG_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif +void nutool_modclkcfg_init_acmp01(void); +void nutool_modclkcfg_deinit_acmp01(void); +void nutool_modclkcfg_init_bpwm0(void); +void nutool_modclkcfg_deinit_bpwm0(void); +void nutool_modclkcfg_init_bpwm1(void); +void nutool_modclkcfg_deinit_bpwm1(void); +void nutool_modclkcfg_init_can0(void); +void nutool_modclkcfg_deinit_can0(void); +void nutool_modclkcfg_init_can1(void); +void nutool_modclkcfg_deinit_can1(void); +void nutool_modclkcfg_init_crc(void); +void nutool_modclkcfg_deinit_crc(void); +void nutool_modclkcfg_init_crpt(void); +void nutool_modclkcfg_deinit_crpt(void); +void nutool_modclkcfg_init_dac(void); +void nutool_modclkcfg_deinit_dac(void); +void nutool_modclkcfg_init_eadc(void); +void nutool_modclkcfg_deinit_eadc(void); +void nutool_modclkcfg_init_ebi(void); +void nutool_modclkcfg_deinit_ebi(void); +void nutool_modclkcfg_init_ecap0(void); +void nutool_modclkcfg_deinit_ecap0(void); +void nutool_modclkcfg_init_ecap1(void); +void nutool_modclkcfg_deinit_ecap1(void); +void nutool_modclkcfg_init_emac(void); +void nutool_modclkcfg_deinit_emac(void); +void nutool_modclkcfg_init_epwm0(void); +void nutool_modclkcfg_deinit_epwm0(void); +void nutool_modclkcfg_init_epwm1(void); +void nutool_modclkcfg_deinit_epwm1(void); +void nutool_modclkcfg_init_fmcidle(void); +void nutool_modclkcfg_deinit_fmcidle(void); +void nutool_modclkcfg_init_hsotg(void); +void nutool_modclkcfg_deinit_hsotg(void); +void nutool_modclkcfg_init_hsusbd(void); +void nutool_modclkcfg_deinit_hsusbd(void); +void nutool_modclkcfg_init_i2c0(void); +void nutool_modclkcfg_deinit_i2c0(void); +void nutool_modclkcfg_init_i2c1(void); +void nutool_modclkcfg_deinit_i2c1(void); +void nutool_modclkcfg_init_i2c2(void); +void nutool_modclkcfg_deinit_i2c2(void); +void nutool_modclkcfg_init_i2s0(void); +void nutool_modclkcfg_deinit_i2s0(void); +void nutool_modclkcfg_init_isp(void); +void nutool_modclkcfg_deinit_isp(void); +void nutool_modclkcfg_init_opa(void); +void nutool_modclkcfg_deinit_opa(void); +void nutool_modclkcfg_init_otg(void); +void nutool_modclkcfg_deinit_otg(void); +void nutool_modclkcfg_init_pdma(void); +void nutool_modclkcfg_deinit_pdma(void); +void nutool_modclkcfg_init_qei0(void); +void nutool_modclkcfg_deinit_qei0(void); +void nutool_modclkcfg_init_qei1(void); +void nutool_modclkcfg_deinit_qei1(void); +void nutool_modclkcfg_init_qspi0(void); +void nutool_modclkcfg_deinit_qspi0(void); +void nutool_modclkcfg_init_rtc(void); +void nutool_modclkcfg_deinit_rtc(void); +void nutool_modclkcfg_init_sc0(void); +void nutool_modclkcfg_deinit_sc0(void); +void nutool_modclkcfg_init_sc1(void); +void nutool_modclkcfg_deinit_sc1(void); +void nutool_modclkcfg_init_sc2(void); +void nutool_modclkcfg_deinit_sc2(void); +void nutool_modclkcfg_init_sdh0(void); +void nutool_modclkcfg_deinit_sdh0(void); +void nutool_modclkcfg_init_sdh1(void); +void nutool_modclkcfg_deinit_sdh1(void); +void nutool_modclkcfg_init_spi0(void); +void nutool_modclkcfg_deinit_spi0(void); +void nutool_modclkcfg_init_spi1(void); +void nutool_modclkcfg_deinit_spi1(void); +void nutool_modclkcfg_init_spi2(void); +void nutool_modclkcfg_deinit_spi2(void); +void nutool_modclkcfg_init_spi3(void); +void nutool_modclkcfg_deinit_spi3(void); +void nutool_modclkcfg_init_spim(void); +void nutool_modclkcfg_deinit_spim(void); +void nutool_modclkcfg_init_systick(void); +void nutool_modclkcfg_deinit_systick(void); +void nutool_modclkcfg_init_tmr0(void); +void nutool_modclkcfg_deinit_tmr0(void); +void nutool_modclkcfg_init_tmr1(void); +void nutool_modclkcfg_deinit_tmr1(void); +void nutool_modclkcfg_init_tmr2(void); +void nutool_modclkcfg_deinit_tmr2(void); +void nutool_modclkcfg_init_tmr3(void); +void nutool_modclkcfg_deinit_tmr3(void); +void nutool_modclkcfg_init_uart0(void); +void nutool_modclkcfg_deinit_uart0(void); +void nutool_modclkcfg_init_uart1(void); +void nutool_modclkcfg_deinit_uart1(void); +void nutool_modclkcfg_init_uart2(void); +void nutool_modclkcfg_deinit_uart2(void); +void nutool_modclkcfg_init_uart3(void); +void nutool_modclkcfg_deinit_uart3(void); +void nutool_modclkcfg_init_uart4(void); +void nutool_modclkcfg_deinit_uart4(void); +void nutool_modclkcfg_init_uart5(void); +void nutool_modclkcfg_deinit_uart5(void); +void nutool_modclkcfg_init_usbd(void); +void nutool_modclkcfg_deinit_usbd(void); +void nutool_modclkcfg_init_usbh(void); +void nutool_modclkcfg_deinit_usbh(void); +void nutool_modclkcfg_init_usci0(void); +void nutool_modclkcfg_deinit_usci0(void); +void nutool_modclkcfg_init_usci1(void); +void nutool_modclkcfg_deinit_usci1(void); +void nutool_modclkcfg_init_wdt(void); +void nutool_modclkcfg_deinit_wdt(void); +void nutool_modclkcfg_init_wwdt(void); +void nutool_modclkcfg_deinit_wwdt(void); +void nutool_modclkcfg_init_base(void); +void nutool_modclkcfg_init(void); +#ifdef __cplusplus +} +#endif +#endif /*__NUTOOL_MODCLKCFG_H__*/ + +/*** (C) COPYRIGHT 2013-2020 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/numaker-pfm-m487/board/NuPinConfig/nutool_pincfg.c b/bsp/nuvoton/numaker-pfm-m487/board/NuPinConfig/nutool_pincfg.c new file mode 100644 index 0000000000000000000000000000000000000000..5f9cd205b8437074a47700bd64e37f0957b40bc7 --- /dev/null +++ b/bsp/nuvoton/numaker-pfm-m487/board/NuPinConfig/nutool_pincfg.c @@ -0,0 +1,510 @@ +/**************************************************************************** + * @file nutool_pincfg.c + * @version V1.20 + * @Date 2020/05/27-17:17:14 + * @brief NuMicro generated code file + * + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +/******************** +MCU:M487JIDAE(LQFP144) +********************/ + +#include "M480.h" + +void nutool_pincfg_init_bpwm0(void) +{ + SYS->GPD_MFPH &= ~(SYS_GPD_MFPH_PD12MFP_Msk); + SYS->GPD_MFPH |= (SYS_GPD_MFPH_PD12MFP_BPWM0_CH5); + + return; +} + +void nutool_pincfg_deinit_bpwm0(void) +{ + SYS->GPD_MFPH &= ~(SYS_GPD_MFPH_PD12MFP_Msk); + + return; +} + +void nutool_pincfg_init_can0(void) +{ + SYS->GPA_MFPL &= ~(SYS_GPA_MFPL_PA5MFP_Msk | SYS_GPA_MFPL_PA4MFP_Msk); + SYS->GPA_MFPL |= (SYS_GPA_MFPL_PA5MFP_CAN0_TXD | SYS_GPA_MFPL_PA4MFP_CAN0_RXD); + + return; +} + +void nutool_pincfg_deinit_can0(void) +{ + SYS->GPA_MFPL &= ~(SYS_GPA_MFPL_PA5MFP_Msk | SYS_GPA_MFPL_PA4MFP_Msk); + + return; +} + +void nutool_pincfg_init_eadc0(void) +{ + SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB14MFP_Msk | SYS_GPB_MFPH_PB9MFP_Msk | SYS_GPB_MFPH_PB8MFP_Msk); + SYS->GPB_MFPH |= (SYS_GPB_MFPH_PB14MFP_EADC0_CH14 | SYS_GPB_MFPH_PB9MFP_EADC0_CH9 | SYS_GPB_MFPH_PB8MFP_EADC0_CH8); + SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB2MFP_Msk); + SYS->GPB_MFPL |= (SYS_GPB_MFPL_PB2MFP_EADC0_CH2); + + return; +} + +void nutool_pincfg_deinit_eadc0(void) +{ + SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB14MFP_Msk | SYS_GPB_MFPH_PB9MFP_Msk | SYS_GPB_MFPH_PB8MFP_Msk); + SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB2MFP_Msk); + + return; +} + +void nutool_pincfg_init_ebi(void) +{ + SYS->GPA_MFPH &= ~(SYS_GPA_MFPH_PA8MFP_Msk); + SYS->GPA_MFPH |= (SYS_GPA_MFPH_PA8MFP_EBI_ALE); + SYS->GPD_MFPH &= ~(SYS_GPD_MFPH_PD14MFP_Msk | SYS_GPD_MFPH_PD11MFP_Msk | SYS_GPD_MFPH_PD9MFP_Msk | SYS_GPD_MFPH_PD8MFP_Msk); + SYS->GPD_MFPH |= (SYS_GPD_MFPH_PD14MFP_EBI_nCS0 | SYS_GPD_MFPH_PD11MFP_EBI_nCS1 | SYS_GPD_MFPH_PD9MFP_EBI_AD7 | SYS_GPD_MFPH_PD8MFP_EBI_AD6); + SYS->GPE_MFPH &= ~(SYS_GPE_MFPH_PE15MFP_Msk | SYS_GPE_MFPH_PE14MFP_Msk); + SYS->GPE_MFPH |= (SYS_GPE_MFPH_PE15MFP_EBI_AD9 | SYS_GPE_MFPH_PE14MFP_EBI_AD8); + SYS->GPE_MFPL &= ~(SYS_GPE_MFPL_PE5MFP_Msk | SYS_GPE_MFPL_PE4MFP_Msk | SYS_GPE_MFPL_PE1MFP_Msk | SYS_GPE_MFPL_PE0MFP_Msk); + SYS->GPE_MFPL |= (SYS_GPE_MFPL_PE5MFP_EBI_nRD | SYS_GPE_MFPL_PE4MFP_EBI_nWR | SYS_GPE_MFPL_PE1MFP_EBI_AD10 | SYS_GPE_MFPL_PE0MFP_EBI_AD11); + SYS->GPG_MFPH &= ~(SYS_GPG_MFPH_PG14MFP_Msk | SYS_GPG_MFPH_PG13MFP_Msk | SYS_GPG_MFPH_PG12MFP_Msk | SYS_GPG_MFPH_PG11MFP_Msk | SYS_GPG_MFPH_PG10MFP_Msk | SYS_GPG_MFPH_PG9MFP_Msk | SYS_GPG_MFPH_PG8MFP_Msk); + SYS->GPG_MFPH |= (SYS_GPG_MFPH_PG14MFP_EBI_AD5 | SYS_GPG_MFPH_PG13MFP_EBI_AD4 | SYS_GPG_MFPH_PG12MFP_EBI_AD3 | SYS_GPG_MFPH_PG11MFP_EBI_AD2 | SYS_GPG_MFPH_PG10MFP_EBI_AD1 | SYS_GPG_MFPH_PG9MFP_EBI_AD0 | SYS_GPG_MFPH_PG8MFP_EBI_nWRH); + SYS->GPG_MFPL &= ~(SYS_GPG_MFPL_PG7MFP_Msk); + SYS->GPG_MFPL |= (SYS_GPG_MFPL_PG7MFP_EBI_nWRL); + SYS->GPH_MFPH &= ~(SYS_GPH_MFPH_PH11MFP_Msk | SYS_GPH_MFPH_PH10MFP_Msk | SYS_GPH_MFPH_PH9MFP_Msk | SYS_GPH_MFPH_PH8MFP_Msk); + SYS->GPH_MFPH |= (SYS_GPH_MFPH_PH11MFP_EBI_AD15 | SYS_GPH_MFPH_PH10MFP_EBI_AD14 | SYS_GPH_MFPH_PH9MFP_EBI_AD13 | SYS_GPH_MFPH_PH8MFP_EBI_AD12); + + return; +} + +void nutool_pincfg_deinit_ebi(void) +{ + SYS->GPA_MFPH &= ~(SYS_GPA_MFPH_PA8MFP_Msk); + SYS->GPD_MFPH &= ~(SYS_GPD_MFPH_PD14MFP_Msk | SYS_GPD_MFPH_PD11MFP_Msk | SYS_GPD_MFPH_PD9MFP_Msk | SYS_GPD_MFPH_PD8MFP_Msk); + SYS->GPE_MFPH &= ~(SYS_GPE_MFPH_PE15MFP_Msk | SYS_GPE_MFPH_PE14MFP_Msk); + SYS->GPE_MFPL &= ~(SYS_GPE_MFPL_PE5MFP_Msk | SYS_GPE_MFPL_PE4MFP_Msk | SYS_GPE_MFPL_PE1MFP_Msk | SYS_GPE_MFPL_PE0MFP_Msk); + SYS->GPG_MFPH &= ~(SYS_GPG_MFPH_PG14MFP_Msk | SYS_GPG_MFPH_PG13MFP_Msk | SYS_GPG_MFPH_PG12MFP_Msk | SYS_GPG_MFPH_PG11MFP_Msk | SYS_GPG_MFPH_PG10MFP_Msk | SYS_GPG_MFPH_PG9MFP_Msk | SYS_GPG_MFPH_PG8MFP_Msk); + SYS->GPG_MFPL &= ~(SYS_GPG_MFPL_PG7MFP_Msk); + SYS->GPH_MFPH &= ~(SYS_GPH_MFPH_PH11MFP_Msk | SYS_GPH_MFPH_PH10MFP_Msk | SYS_GPH_MFPH_PH9MFP_Msk | SYS_GPH_MFPH_PH8MFP_Msk); + + return; +} + +void nutool_pincfg_init_emac(void) +{ + SYS->GPA_MFPL &= ~(SYS_GPA_MFPL_PA7MFP_Msk | SYS_GPA_MFPL_PA6MFP_Msk); + SYS->GPA_MFPL |= (SYS_GPA_MFPL_PA7MFP_EMAC_RMII_CRSDV | SYS_GPA_MFPL_PA6MFP_EMAC_RMII_RXERR); + SYS->GPC_MFPH &= ~(SYS_GPC_MFPH_PC8MFP_Msk); + SYS->GPC_MFPH |= (SYS_GPC_MFPH_PC8MFP_EMAC_RMII_REFCLK); + SYS->GPC_MFPL &= ~(SYS_GPC_MFPL_PC7MFP_Msk | SYS_GPC_MFPL_PC6MFP_Msk); + SYS->GPC_MFPL |= (SYS_GPC_MFPL_PC7MFP_EMAC_RMII_RXD0 | SYS_GPC_MFPL_PC6MFP_EMAC_RMII_RXD1); + SYS->GPE_MFPH &= ~(SYS_GPE_MFPH_PE12MFP_Msk | SYS_GPE_MFPH_PE11MFP_Msk | SYS_GPE_MFPH_PE10MFP_Msk | SYS_GPE_MFPH_PE9MFP_Msk | SYS_GPE_MFPH_PE8MFP_Msk); + SYS->GPE_MFPH |= (SYS_GPE_MFPH_PE12MFP_EMAC_RMII_TXEN | SYS_GPE_MFPH_PE11MFP_EMAC_RMII_TXD1 | SYS_GPE_MFPH_PE10MFP_EMAC_RMII_TXD0 | SYS_GPE_MFPH_PE9MFP_EMAC_RMII_MDIO | SYS_GPE_MFPH_PE8MFP_EMAC_RMII_MDC); + + return; +} + +void nutool_pincfg_deinit_emac(void) +{ + SYS->GPA_MFPL &= ~(SYS_GPA_MFPL_PA7MFP_Msk | SYS_GPA_MFPL_PA6MFP_Msk); + SYS->GPC_MFPH &= ~(SYS_GPC_MFPH_PC8MFP_Msk); + SYS->GPC_MFPL &= ~(SYS_GPC_MFPL_PC7MFP_Msk | SYS_GPC_MFPL_PC6MFP_Msk); + SYS->GPE_MFPH &= ~(SYS_GPE_MFPH_PE12MFP_Msk | SYS_GPE_MFPH_PE11MFP_Msk | SYS_GPE_MFPH_PE10MFP_Msk | SYS_GPE_MFPH_PE9MFP_Msk | SYS_GPE_MFPH_PE8MFP_Msk); + + return; +} + +void nutool_pincfg_init_hsusb(void) +{ + SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB11MFP_Msk | SYS_GPB_MFPH_PB10MFP_Msk); + SYS->GPB_MFPH |= (SYS_GPB_MFPH_PB11MFP_HSUSB_VBUS_ST | SYS_GPB_MFPH_PB10MFP_HSUSB_VBUS_EN); + + return; +} + +void nutool_pincfg_deinit_hsusb(void) +{ + SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB11MFP_Msk | SYS_GPB_MFPH_PB10MFP_Msk); + + return; +} + +void nutool_pincfg_init_i2c1(void) +{ + SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB1MFP_Msk | SYS_GPB_MFPL_PB0MFP_Msk); + SYS->GPB_MFPL |= (SYS_GPB_MFPL_PB1MFP_I2C1_SCL | SYS_GPB_MFPL_PB0MFP_I2C1_SDA); + + return; +} + +void nutool_pincfg_deinit_i2c1(void) +{ + SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB1MFP_Msk | SYS_GPB_MFPL_PB0MFP_Msk); + + return; +} + +void nutool_pincfg_init_i2c2(void) +{ + SYS->GPD_MFPL &= ~(SYS_GPD_MFPL_PD1MFP_Msk | SYS_GPD_MFPL_PD0MFP_Msk); + SYS->GPD_MFPL |= (SYS_GPD_MFPL_PD1MFP_I2C2_SCL | SYS_GPD_MFPL_PD0MFP_I2C2_SDA); + + return; +} + +void nutool_pincfg_deinit_i2c2(void) +{ + SYS->GPD_MFPL &= ~(SYS_GPD_MFPL_PD1MFP_Msk | SYS_GPD_MFPL_PD0MFP_Msk); + + return; +} + +void nutool_pincfg_init_i2s0(void) +{ + SYS->GPF_MFPH &= ~(SYS_GPF_MFPH_PF10MFP_Msk | SYS_GPF_MFPH_PF9MFP_Msk | SYS_GPF_MFPH_PF8MFP_Msk); + SYS->GPF_MFPH |= (SYS_GPF_MFPH_PF10MFP_I2S0_BCLK | SYS_GPF_MFPH_PF9MFP_I2S0_MCLK | SYS_GPF_MFPH_PF8MFP_I2S0_DI); + SYS->GPF_MFPL &= ~(SYS_GPF_MFPL_PF7MFP_Msk | SYS_GPF_MFPL_PF6MFP_Msk); + SYS->GPF_MFPL |= (SYS_GPF_MFPL_PF7MFP_I2S0_DO | SYS_GPF_MFPL_PF6MFP_I2S0_LRCK); + + return; +} + +void nutool_pincfg_deinit_i2s0(void) +{ + SYS->GPF_MFPH &= ~(SYS_GPF_MFPH_PF10MFP_Msk | SYS_GPF_MFPH_PF9MFP_Msk | SYS_GPF_MFPH_PF8MFP_Msk); + SYS->GPF_MFPL &= ~(SYS_GPF_MFPL_PF7MFP_Msk | SYS_GPF_MFPL_PF6MFP_Msk); + + return; +} + +void nutool_pincfg_init_ice(void) +{ + SYS->GPF_MFPL &= ~(SYS_GPF_MFPL_PF1MFP_Msk | SYS_GPF_MFPL_PF0MFP_Msk); + SYS->GPF_MFPL |= (SYS_GPF_MFPL_PF1MFP_ICE_CLK | SYS_GPF_MFPL_PF0MFP_ICE_DAT); + + return; +} + +void nutool_pincfg_deinit_ice(void) +{ + SYS->GPF_MFPL &= ~(SYS_GPF_MFPL_PF1MFP_Msk | SYS_GPF_MFPL_PF0MFP_Msk); + + return; +} + +void nutool_pincfg_init_pa(void) +{ + SYS->GPA_MFPH &= ~(SYS_GPA_MFPH_PA11MFP_Msk | SYS_GPA_MFPH_PA10MFP_Msk | SYS_GPA_MFPH_PA9MFP_Msk); + SYS->GPA_MFPH |= (SYS_GPA_MFPH_PA11MFP_GPIO | SYS_GPA_MFPH_PA10MFP_GPIO | SYS_GPA_MFPH_PA9MFP_GPIO); + SYS->GPA_MFPL &= ~(SYS_GPA_MFPL_PA3MFP_Msk | SYS_GPA_MFPL_PA2MFP_Msk | SYS_GPA_MFPL_PA1MFP_Msk | SYS_GPA_MFPL_PA0MFP_Msk); + SYS->GPA_MFPL |= (SYS_GPA_MFPL_PA3MFP_GPIO | SYS_GPA_MFPL_PA2MFP_GPIO | SYS_GPA_MFPL_PA1MFP_GPIO | SYS_GPA_MFPL_PA0MFP_GPIO); + + return; +} + +void nutool_pincfg_deinit_pa(void) +{ + SYS->GPA_MFPH &= ~(SYS_GPA_MFPH_PA11MFP_Msk | SYS_GPA_MFPH_PA10MFP_Msk | SYS_GPA_MFPH_PA9MFP_Msk); + SYS->GPA_MFPL &= ~(SYS_GPA_MFPL_PA3MFP_Msk | SYS_GPA_MFPL_PA2MFP_Msk | SYS_GPA_MFPL_PA1MFP_Msk | SYS_GPA_MFPL_PA0MFP_Msk); + + return; +} + +void nutool_pincfg_init_pb(void) +{ + SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB7MFP_Msk | SYS_GPB_MFPL_PB6MFP_Msk | SYS_GPB_MFPL_PB3MFP_Msk); + SYS->GPB_MFPL |= (SYS_GPB_MFPL_PB7MFP_GPIO | SYS_GPB_MFPL_PB6MFP_GPIO | SYS_GPB_MFPL_PB3MFP_GPIO); + + return; +} + +void nutool_pincfg_deinit_pb(void) +{ + SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB7MFP_Msk | SYS_GPB_MFPL_PB6MFP_Msk | SYS_GPB_MFPL_PB3MFP_Msk); + + return; +} + +void nutool_pincfg_init_pc(void) +{ + SYS->GPC_MFPH &= ~(SYS_GPC_MFPH_PC13MFP_Msk | SYS_GPC_MFPH_PC10MFP_Msk | SYS_GPC_MFPH_PC9MFP_Msk); + SYS->GPC_MFPH |= (SYS_GPC_MFPH_PC13MFP_GPIO | SYS_GPC_MFPH_PC10MFP_GPIO | SYS_GPC_MFPH_PC9MFP_GPIO); + + return; +} + +void nutool_pincfg_deinit_pc(void) +{ + SYS->GPC_MFPH &= ~(SYS_GPC_MFPH_PC13MFP_Msk | SYS_GPC_MFPH_PC10MFP_Msk | SYS_GPC_MFPH_PC9MFP_Msk); + + return; +} + +void nutool_pincfg_init_pd(void) +{ + SYS->GPD_MFPH &= ~(SYS_GPD_MFPH_PD10MFP_Msk); + SYS->GPD_MFPH |= (SYS_GPD_MFPH_PD10MFP_GPIO); + SYS->GPD_MFPL &= ~(SYS_GPD_MFPL_PD3MFP_Msk | SYS_GPD_MFPL_PD2MFP_Msk); + SYS->GPD_MFPL |= (SYS_GPD_MFPL_PD3MFP_GPIO | SYS_GPD_MFPL_PD2MFP_GPIO); + + return; +} + +void nutool_pincfg_deinit_pd(void) +{ + SYS->GPD_MFPH &= ~(SYS_GPD_MFPH_PD10MFP_Msk); + SYS->GPD_MFPL &= ~(SYS_GPD_MFPL_PD3MFP_Msk | SYS_GPD_MFPL_PD2MFP_Msk); + + return; +} + +void nutool_pincfg_init_pe(void) +{ + SYS->GPE_MFPH &= ~(SYS_GPE_MFPH_PE13MFP_Msk); + SYS->GPE_MFPH |= (SYS_GPE_MFPH_PE13MFP_GPIO); + + return; +} + +void nutool_pincfg_deinit_pe(void) +{ + SYS->GPE_MFPH &= ~(SYS_GPE_MFPH_PE13MFP_Msk); + + return; +} + +void nutool_pincfg_init_pg(void) +{ + SYS->GPG_MFPH &= ~(SYS_GPG_MFPH_PG15MFP_Msk); + SYS->GPG_MFPH |= (SYS_GPG_MFPH_PG15MFP_GPIO); + SYS->GPG_MFPL &= ~(SYS_GPG_MFPL_PG4MFP_Msk | SYS_GPG_MFPL_PG3MFP_Msk | SYS_GPG_MFPL_PG2MFP_Msk); + SYS->GPG_MFPL |= (SYS_GPG_MFPL_PG4MFP_GPIO | SYS_GPG_MFPL_PG3MFP_GPIO | SYS_GPG_MFPL_PG2MFP_GPIO); + + return; +} + +void nutool_pincfg_deinit_pg(void) +{ + SYS->GPG_MFPH &= ~(SYS_GPG_MFPH_PG15MFP_Msk); + SYS->GPG_MFPL &= ~(SYS_GPG_MFPL_PG4MFP_Msk | SYS_GPG_MFPL_PG3MFP_Msk | SYS_GPG_MFPL_PG2MFP_Msk); + + return; +} + +void nutool_pincfg_init_ph(void) +{ + SYS->GPH_MFPL &= ~(SYS_GPH_MFPL_PH7MFP_Msk | SYS_GPH_MFPL_PH6MFP_Msk | SYS_GPH_MFPL_PH5MFP_Msk | SYS_GPH_MFPL_PH4MFP_Msk | SYS_GPH_MFPL_PH3MFP_Msk); + SYS->GPH_MFPL |= (SYS_GPH_MFPL_PH7MFP_GPIO | SYS_GPH_MFPL_PH6MFP_GPIO | SYS_GPH_MFPL_PH5MFP_GPIO | SYS_GPH_MFPL_PH4MFP_GPIO | SYS_GPH_MFPL_PH3MFP_GPIO); + + return; +} + +void nutool_pincfg_deinit_ph(void) +{ + SYS->GPH_MFPL &= ~(SYS_GPH_MFPL_PH7MFP_Msk | SYS_GPH_MFPL_PH6MFP_Msk | SYS_GPH_MFPL_PH5MFP_Msk | SYS_GPH_MFPL_PH4MFP_Msk | SYS_GPH_MFPL_PH3MFP_Msk); + + return; +} + +void nutool_pincfg_init_qspi0(void) +{ + SYS->GPC_MFPL &= ~(SYS_GPC_MFPL_PC5MFP_Msk | SYS_GPC_MFPL_PC4MFP_Msk | SYS_GPC_MFPL_PC3MFP_Msk | SYS_GPC_MFPL_PC2MFP_Msk | SYS_GPC_MFPL_PC1MFP_Msk | SYS_GPC_MFPL_PC0MFP_Msk); + SYS->GPC_MFPL |= (SYS_GPC_MFPL_PC5MFP_QSPI0_MISO1 | SYS_GPC_MFPL_PC4MFP_QSPI0_MOSI1 | SYS_GPC_MFPL_PC3MFP_QSPI0_SS | SYS_GPC_MFPL_PC2MFP_QSPI0_CLK | SYS_GPC_MFPL_PC1MFP_QSPI0_MISO0 | SYS_GPC_MFPL_PC0MFP_QSPI0_MOSI0); + + return; +} + +void nutool_pincfg_deinit_qspi0(void) +{ + SYS->GPC_MFPL &= ~(SYS_GPC_MFPL_PC5MFP_Msk | SYS_GPC_MFPL_PC4MFP_Msk | SYS_GPC_MFPL_PC3MFP_Msk | SYS_GPC_MFPL_PC2MFP_Msk | SYS_GPC_MFPL_PC1MFP_Msk | SYS_GPC_MFPL_PC0MFP_Msk); + + return; +} + +void nutool_pincfg_init_sd0(void) +{ + SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB5MFP_Msk | SYS_GPB_MFPL_PB4MFP_Msk); + SYS->GPB_MFPL |= (SYS_GPB_MFPL_PB5MFP_SD0_DAT3 | SYS_GPB_MFPL_PB4MFP_SD0_DAT2); + SYS->GPD_MFPH &= ~(SYS_GPD_MFPH_PD13MFP_Msk); + SYS->GPD_MFPH |= (SYS_GPD_MFPH_PD13MFP_SD0_nCD); + SYS->GPE_MFPL &= ~(SYS_GPE_MFPL_PE7MFP_Msk | SYS_GPE_MFPL_PE6MFP_Msk | SYS_GPE_MFPL_PE3MFP_Msk | SYS_GPE_MFPL_PE2MFP_Msk); + SYS->GPE_MFPL |= (SYS_GPE_MFPL_PE7MFP_SD0_CMD | SYS_GPE_MFPL_PE6MFP_SD0_CLK | SYS_GPE_MFPL_PE3MFP_SD0_DAT1 | SYS_GPE_MFPL_PE2MFP_SD0_DAT0); + + return; +} + +void nutool_pincfg_deinit_sd0(void) +{ + SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB5MFP_Msk | SYS_GPB_MFPL_PB4MFP_Msk); + SYS->GPD_MFPH &= ~(SYS_GPD_MFPH_PD13MFP_Msk); + SYS->GPE_MFPL &= ~(SYS_GPE_MFPL_PE7MFP_Msk | SYS_GPE_MFPL_PE6MFP_Msk | SYS_GPE_MFPL_PE3MFP_Msk | SYS_GPE_MFPL_PE2MFP_Msk); + + return; +} + +void nutool_pincfg_init_spi3(void) +{ + SYS->GPC_MFPH &= ~(SYS_GPC_MFPH_PC12MFP_Msk | SYS_GPC_MFPH_PC11MFP_Msk); + SYS->GPC_MFPH |= (SYS_GPC_MFPH_PC12MFP_SPI3_MISO | SYS_GPC_MFPH_PC11MFP_SPI3_MOSI); + SYS->GPG_MFPL &= ~(SYS_GPG_MFPL_PG6MFP_Msk | SYS_GPG_MFPL_PG5MFP_Msk); + SYS->GPG_MFPL |= (SYS_GPG_MFPL_PG6MFP_SPI3_CLK | SYS_GPG_MFPL_PG5MFP_SPI3_SS); + + return; +} + +void nutool_pincfg_deinit_spi3(void) +{ + SYS->GPC_MFPH &= ~(SYS_GPC_MFPH_PC12MFP_Msk | SYS_GPC_MFPH_PC11MFP_Msk); + SYS->GPG_MFPL &= ~(SYS_GPG_MFPL_PG6MFP_Msk | SYS_GPG_MFPL_PG5MFP_Msk); + + return; +} + +void nutool_pincfg_init_uart0(void) +{ + SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB13MFP_Msk | SYS_GPB_MFPH_PB12MFP_Msk); + SYS->GPB_MFPH |= (SYS_GPB_MFPH_PB13MFP_UART0_TXD | SYS_GPB_MFPH_PB12MFP_UART0_RXD); + + return; +} + +void nutool_pincfg_deinit_uart0(void) +{ + SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB13MFP_Msk | SYS_GPB_MFPH_PB12MFP_Msk); + + return; +} + +void nutool_pincfg_init_uart1(void) +{ + SYS->GPG_MFPL &= ~(SYS_GPG_MFPL_PG1MFP_Msk | SYS_GPG_MFPL_PG0MFP_Msk); + SYS->GPG_MFPL |= (SYS_GPG_MFPL_PG1MFP_UART1_RXD | SYS_GPG_MFPL_PG0MFP_UART1_TXD); + + return; +} + +void nutool_pincfg_deinit_uart1(void) +{ + SYS->GPG_MFPL &= ~(SYS_GPG_MFPL_PG1MFP_Msk | SYS_GPG_MFPL_PG0MFP_Msk); + + return; +} + +void nutool_pincfg_init_uart5(void) +{ + SYS->GPH_MFPL &= ~(SYS_GPH_MFPL_PH2MFP_Msk | SYS_GPH_MFPL_PH1MFP_Msk | SYS_GPH_MFPL_PH0MFP_Msk); + SYS->GPH_MFPL |= (SYS_GPH_MFPL_PH2MFP_UART5_nRTS | SYS_GPH_MFPL_PH1MFP_UART5_RXD | SYS_GPH_MFPL_PH0MFP_UART5_TXD); + + return; +} + +void nutool_pincfg_deinit_uart5(void) +{ + SYS->GPH_MFPL &= ~(SYS_GPH_MFPL_PH2MFP_Msk | SYS_GPH_MFPL_PH1MFP_Msk | SYS_GPH_MFPL_PH0MFP_Msk); + + return; +} + +void nutool_pincfg_init_usb(void) +{ + SYS->GPA_MFPH &= ~(SYS_GPA_MFPH_PA15MFP_Msk | SYS_GPA_MFPH_PA14MFP_Msk | SYS_GPA_MFPH_PA13MFP_Msk | SYS_GPA_MFPH_PA12MFP_Msk); + SYS->GPA_MFPH |= (SYS_GPA_MFPH_PA15MFP_USB_OTG_ID | SYS_GPA_MFPH_PA14MFP_USB_D_P | SYS_GPA_MFPH_PA13MFP_USB_D_N | SYS_GPA_MFPH_PA12MFP_USB_VBUS); + SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB15MFP_Msk | SYS_GPB_MFPH_PB11MFP_Msk | SYS_GPB_MFPH_PB10MFP_Msk); + SYS->GPB_MFPH |= (SYS_GPB_MFPH_PB15MFP_USB_VBUS_EN | SYS_GPB_MFPH_PB11MFP_HSUSB_VBUS_ST | SYS_GPB_MFPH_PB10MFP_HSUSB_VBUS_EN); + SYS->GPC_MFPH &= ~(SYS_GPC_MFPH_PC14MFP_Msk); + SYS->GPC_MFPH |= (SYS_GPC_MFPH_PC14MFP_USB_VBUS_ST); + + return; +} + +void nutool_pincfg_deinit_usb(void) +{ + SYS->GPA_MFPH &= ~(SYS_GPA_MFPH_PA15MFP_Msk | SYS_GPA_MFPH_PA14MFP_Msk | SYS_GPA_MFPH_PA13MFP_Msk | SYS_GPA_MFPH_PA12MFP_Msk); + SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB15MFP_Msk | SYS_GPB_MFPH_PB11MFP_Msk | SYS_GPB_MFPH_PB10MFP_Msk); + SYS->GPC_MFPH &= ~(SYS_GPC_MFPH_PC14MFP_Msk); + + return; +} + +void nutool_pincfg_init(void) +{ + //SYS->GPA_MFPH = 0xEEEE0002; + //SYS->GPA_MFPL = 0x33AA0000; + //SYS->GPB_MFPH = 0xE166EE11; + //SYS->GPB_MFPL = 0x00330199; + //SYS->GPC_MFPH = 0x0E066003; + //SYS->GPC_MFPL = 0x33444444; + //SYS->GPD_MFPH = 0x02392022; + //SYS->GPD_MFPL = 0x00000066; + //SYS->GPE_MFPH = 0x22033333; + //SYS->GPE_MFPL = 0x33223322; + //SYS->GPF_MFPH = 0x00000444; + //SYS->GPF_MFPL = 0x440000EE; + //SYS->GPG_MFPH = 0x02222222; + //SYS->GPG_MFPL = 0x23300088; + //SYS->GPH_MFPH = 0x00002222; + //SYS->GPH_MFPL = 0x00000444; + + nutool_pincfg_init_bpwm0(); + nutool_pincfg_init_can0(); + nutool_pincfg_init_eadc0(); + nutool_pincfg_init_ebi(); + nutool_pincfg_init_emac(); + nutool_pincfg_init_hsusb(); + nutool_pincfg_init_i2c1(); + nutool_pincfg_init_i2c2(); + nutool_pincfg_init_i2s0(); + nutool_pincfg_init_ice(); + nutool_pincfg_init_pa(); + nutool_pincfg_init_pb(); + nutool_pincfg_init_pc(); + nutool_pincfg_init_pd(); + nutool_pincfg_init_pe(); + nutool_pincfg_init_pg(); + nutool_pincfg_init_ph(); + nutool_pincfg_init_qspi0(); + nutool_pincfg_init_sd0(); + nutool_pincfg_init_spi3(); + nutool_pincfg_init_uart0(); + nutool_pincfg_init_uart1(); + nutool_pincfg_init_uart5(); + nutool_pincfg_init_usb(); + + return; +} + +void nutool_pincfg_deinit(void) +{ + nutool_pincfg_deinit_bpwm0(); + nutool_pincfg_deinit_can0(); + nutool_pincfg_deinit_eadc0(); + nutool_pincfg_deinit_ebi(); + nutool_pincfg_deinit_emac(); + nutool_pincfg_deinit_hsusb(); + nutool_pincfg_deinit_i2c1(); + nutool_pincfg_deinit_i2c2(); + nutool_pincfg_deinit_i2s0(); + nutool_pincfg_deinit_ice(); + nutool_pincfg_deinit_pa(); + nutool_pincfg_deinit_pb(); + nutool_pincfg_deinit_pc(); + nutool_pincfg_deinit_pd(); + nutool_pincfg_deinit_pe(); + nutool_pincfg_deinit_pg(); + nutool_pincfg_deinit_ph(); + nutool_pincfg_deinit_qspi0(); + nutool_pincfg_deinit_sd0(); + nutool_pincfg_deinit_spi3(); + nutool_pincfg_deinit_uart0(); + nutool_pincfg_deinit_uart1(); + nutool_pincfg_deinit_uart5(); + nutool_pincfg_deinit_usb(); + + return; +} +/*** (C) COPYRIGHT 2013-2020 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/numaker-pfm-m487/board/NuPinConfig/nutool_pincfg.cfg b/bsp/nuvoton/numaker-pfm-m487/board/NuPinConfig/nutool_pincfg.cfg new file mode 100644 index 0000000000000000000000000000000000000000..5f024d2a66bb69160af25e11e759d344459834b3 --- /dev/null +++ b/bsp/nuvoton/numaker-pfm-m487/board/NuPinConfig/nutool_pincfg.cfg @@ -0,0 +1,198 @@ +/**************************************************************************** + * @file nutool_pincfg.cfg + * @version V1.20 + * @Date 2020/05/27-17:17:16 + * @brief NuMicro config file + * + * @note Please do not modify this file. + * Otherwise, it may not be loaded successfully. + * Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +MCU:M487JIDAE(LQFP144) +Pin1:SD0_DAT3 +Pin2:SD0_DAT2 +Pin3:PB.3 +Pin4:EADC0_CH2 +Pin5:SPI3_MISO +Pin6:SPI3_MOSI +Pin7:PC.10 +Pin8:PC.9 +Pin9:I2C1_SCL +Pin10:I2C1_SDA +Pin11:VSS +Pin12:VDD +Pin13:PA.11 +Pin14:PA.10 +Pin15:PA.9 +Pin16:EBI_ALE +Pin17:PC.13 +Pin18:BPWM0_CH5 +Pin19:EBI_nCS1 +Pin20:PD.10 +Pin21:VSS +Pin22:VDD +Pin23:UART1_TXD +Pin24:UART1_RXD +Pin25:PG.2 +Pin26:PG.3 +Pin27:PG.4 +Pin28:PF.11 +Pin29:I2S0_BCLK +Pin30:I2S0_MCLK +Pin31:I2S0_DI +Pin32:I2S0_DO +Pin33:I2S0_LRCK +Pin34:VDD +Pin35:PF.5 +Pin36:PF.4 +Pin37:UART5_TXD +Pin38:UART5_RXD +Pin39:UART5_nRTS +Pin40:PH.3 +Pin41:PH.4 +Pin42:PH.5 +Pin43:PH.6 +Pin44:PH.7 +Pin45:PF.3 +Pin46:PF.2 +Pin47:VSS +Pin48:VDD +Pin49:EMAC_RMII_MDC +Pin50:EMAC_RMII_MDIO +Pin51:EMAC_RMII_TXD0 +Pin52:EMAC_RMII_TXD1 +Pin53:EMAC_RMII_TXEN +Pin54:PE.13 +Pin55:EMAC_RMII_REFCLK +Pin56:EMAC_RMII_RXD0 +Pin57:EMAC_RMII_RXD1 +Pin58:EMAC_RMII_CRSDV +Pin59:EMAC_RMII_RXERR +Pin60:VSS +Pin61:VDD +Pin62:LDO_CAP +Pin63:CAN0_TXD +Pin64:CAN0_RXD +Pin65:PA.3 +Pin66:PA.2 +Pin67:PA.1 +Pin68:PA.0 +Pin69:VDDIO +Pin70:EBI_AD8 +Pin71:EBI_AD9 +Pin72:nRESET +Pin73:ICE_DAT +Pin74:ICE_CLK +Pin75:EBI_AD7 +Pin76:EBI_AD6 +Pin77:QSPI0_MISO1 +Pin78:QSPI0_MOSI1 +Pin79:QSPI0_SS +Pin80:QSPI0_CLK +Pin81:QSPI0_MISO0 +Pin82:QSPI0_MOSI0 +Pin83:VSS +Pin84:VDD +Pin85:EBI_AD0 +Pin86:EBI_AD1 +Pin87:EBI_AD2 +Pin88:EBI_AD3 +Pin89:EBI_AD4 +Pin90:EBI_AD5 +Pin91:PG.15 +Pin92:PD.3 +Pin93:PD.2 +Pin94:I2C2_SCL +Pin95:I2C2_SDA +Pin96:SD0_nCD +Pin97:USB_VBUS +Pin98:USB_D- +Pin99:USB_D+ +Pin100:USB_OTG_ID +Pin101:HSUSB_VRES +Pin102:HSUSB_VDD33 +Pin103:HSUSB_VBUS +Pin104:HSUSB_D- +Pin105:HSUSB_VSS +Pin106:HSUSB_D+ +Pin107:HSUSB_VDD12_CAP +Pin108:HSUSB_ID +Pin109:SD0_CMD +Pin110:SD0_CLK +Pin111:EBI_nRD +Pin112:EBI_nWR +Pin113:SD0_DAT1 +Pin114:SD0_DAT0 +Pin115:VSS +Pin116:VDD +Pin117:EBI_AD10 +Pin118:EBI_AD11 +Pin119:EBI_AD12 +Pin120:EBI_AD13 +Pin121:EBI_AD14 +Pin122:EBI_AD15 +Pin123:EBI_nCS0 +Pin124:SPI3_SS +Pin125:SPI3_CLK +Pin126:EBI_nWRL +Pin127:EBI_nWRH +Pin128:VSS +Pin129:LDO_CAP +Pin130:VDD +Pin131:USB_VBUS_ST +Pin132:USB_VBUS_EN +Pin133:EADC0_CH14 +Pin134:UART0_TXD +Pin135:UART0_RXD +Pin136:AVDD +Pin137:VREF +Pin138:AVSS +Pin139:HSUSB_VBUS_ST +Pin140:HSUSB_VBUS_EN +Pin141:EADC0_CH9 +Pin142:EADC0_CH8 +Pin143:PB.7 +Pin144:PB.6 +GPIOpin:53 +GPIOpin:12 +GPIOpin:13 +GPIOpin:14 +GPIOpin:39 +GPIOpin:41 +GPIOpin:40 +GPIOpin:143 +GPIOpin:142 +GPIOpin:67 +GPIOpin:66 +GPIOpin:2 +GPIOpin:43 +GPIOpin:42 +GPIOpin:16 +GPIOpin:7 +GPIOpin:6 +GPIOpin:90 +GPIOpin:24 +GPIOpin:25 +GPIOpin:26 +GPIOpin:65 +GPIOpin:64 +GPIOpin:92 +GPIOpin:91 +GPIOpin:19 +SYS->GPA_MFPH = 0xEEEE0002 +SYS->GPA_MFPL = 0x33AA0000 +SYS->GPB_MFPH = 0xE166EE11 +SYS->GPB_MFPL = 0x00330199 +SYS->GPC_MFPH = 0x0E066003 +SYS->GPC_MFPL = 0x33444444 +SYS->GPD_MFPH = 0x02392022 +SYS->GPD_MFPL = 0x00000066 +SYS->GPE_MFPH = 0x22033333 +SYS->GPE_MFPL = 0x33223322 +SYS->GPF_MFPH = 0x00000444 +SYS->GPF_MFPL = 0x440000EE +SYS->GPG_MFPH = 0x02222222 +SYS->GPG_MFPL = 0x23300088 +SYS->GPH_MFPH = 0x00002222 +SYS->GPH_MFPL = 0x00000444 +/*** (C) COPYRIGHT 2013-2020 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/numaker-pfm-m487/board/NuPinConfig/nutool_pincfg.h b/bsp/nuvoton/numaker-pfm-m487/board/NuPinConfig/nutool_pincfg.h new file mode 100644 index 0000000000000000000000000000000000000000..3f24e8cd4866a01fbce023c166374433593eac6c --- /dev/null +++ b/bsp/nuvoton/numaker-pfm-m487/board/NuPinConfig/nutool_pincfg.h @@ -0,0 +1,73 @@ +/**************************************************************************** + * @file nutool_pincfg.h + * @version V1.20 + * @Date 2020/05/27-17:17:14 + * @brief NuMicro generated code file + * + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#ifndef __NUTOOL_PINCFG_H__ +#define __NUTOOL_PINCFG_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif +void nutool_pincfg_init_bpwm0(void); +void nutool_pincfg_deinit_bpwm0(void); +void nutool_pincfg_init_can0(void); +void nutool_pincfg_deinit_can0(void); +void nutool_pincfg_init_eadc0(void); +void nutool_pincfg_deinit_eadc0(void); +void nutool_pincfg_init_ebi(void); +void nutool_pincfg_deinit_ebi(void); +void nutool_pincfg_init_emac(void); +void nutool_pincfg_deinit_emac(void); +void nutool_pincfg_init_hsusb(void); +void nutool_pincfg_deinit_hsusb(void); +void nutool_pincfg_init_i2c1(void); +void nutool_pincfg_deinit_i2c1(void); +void nutool_pincfg_init_i2c2(void); +void nutool_pincfg_deinit_i2c2(void); +void nutool_pincfg_init_i2s0(void); +void nutool_pincfg_deinit_i2s0(void); +void nutool_pincfg_init_ice(void); +void nutool_pincfg_deinit_ice(void); +void nutool_pincfg_init_pa(void); +void nutool_pincfg_deinit_pa(void); +void nutool_pincfg_init_pb(void); +void nutool_pincfg_deinit_pb(void); +void nutool_pincfg_init_pc(void); +void nutool_pincfg_deinit_pc(void); +void nutool_pincfg_init_pd(void); +void nutool_pincfg_deinit_pd(void); +void nutool_pincfg_init_pe(void); +void nutool_pincfg_deinit_pe(void); +void nutool_pincfg_init_pg(void); +void nutool_pincfg_deinit_pg(void); +void nutool_pincfg_init_ph(void); +void nutool_pincfg_deinit_ph(void); +void nutool_pincfg_init_qspi0(void); +void nutool_pincfg_deinit_qspi0(void); +void nutool_pincfg_init_sd0(void); +void nutool_pincfg_deinit_sd0(void); +void nutool_pincfg_init_spi3(void); +void nutool_pincfg_deinit_spi3(void); +void nutool_pincfg_init_uart0(void); +void nutool_pincfg_deinit_uart0(void); +void nutool_pincfg_init_uart1(void); +void nutool_pincfg_deinit_uart1(void); +void nutool_pincfg_init_uart5(void); +void nutool_pincfg_deinit_uart5(void); +void nutool_pincfg_init_usb(void); +void nutool_pincfg_deinit_usb(void); +void nutool_pincfg_init(void); +void nutool_pincfg_deinit(void); +#ifdef __cplusplus +} +#endif +#endif /*__NUTOOL_PINCFG_H__*/ + +/*** (C) COPYRIGHT 2013-2020 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/numaker-pfm-m487/board/SConscript b/bsp/nuvoton/numaker-pfm-m487/board/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..6ed8f178ba2e4339cc909ed0fc56c6efcc184180 --- /dev/null +++ b/bsp/nuvoton/numaker-pfm-m487/board/SConscript @@ -0,0 +1,20 @@ +# RT-Thread building script for component + +from building import * + + +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +src = Split(""" +NuClockConfig/nutool_modclkcfg.c +NuPinConfig/nutool_pincfg.c +""") + +src += Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd, cwd + '/NuClockConfig', cwd + '/NuPinConfig'] + +group = DefineGroup('board', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/nuvoton/numaker-pfm-m487/board/board.c b/bsp/nuvoton/numaker-pfm-m487/board/board.c new file mode 100644 index 0000000000000000000000000000000000000000..318fe6a0fc2cfcb7bb04f605e3d192ce1526daa8 --- /dev/null +++ b/bsp/nuvoton/numaker-pfm-m487/board/board.c @@ -0,0 +1,112 @@ +/**************************************************************************//** +* +* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-1-16 Wayne First version +* +******************************************************************************/ + +#include +#include +#include "drv_uart.h" +#include "board.h" +#include "nutool_pincfg.h" +#include "nutool_modclkcfg.h" + +#ifdef __CC_ARM + extern int Image$$RW_IRAM1$$ZI$$Limit; +#elif __ICCARM__ + #pragma section="HEAP" +#else + extern int __bss_end; + extern int __ram_top; +#endif + +/** + * This function will initial M487 board. + */ +void rt_hw_board_init(void) +{ + /* Init System/modules clock */ + nutool_modclkcfg_init(); + + /* Unlock protected registers */ + SYS_UnlockReg(); + + /* Init all pin function setting */ + nutool_pincfg_init(); + + /* Configure SysTick */ + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + + /* Update System Core Clock */ + /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */ + SystemCoreClockUpdate(); + +#if defined(BSP_USING_EADC) + /* Vref connect to internal */ + SYS->VREFCTL = (SYS->VREFCTL & ~SYS_VREFCTL_VREFCTL_Msk) | SYS_VREFCTL_VREF_3_0V; +#endif + + /* Lock protected registers */ + SYS_LockReg(); + + +#ifdef RT_USING_HEAP +#ifdef __CC_ARM + rt_system_heap_init((void *)&Image$$RW_IRAM1$$ZI$$Limit, (void *)SRAM_END); +#elif __ICCARM__ + rt_system_heap_init(__segment_end("HEAP"), (void *)SRAM_END); +#else + /* init memory system */ + rt_system_heap_init((void *)&__bss_end, (void *)&__ram_top); +#endif +#endif /* RT_USING_HEAP */ + +#if defined(BSP_USING_UART) + rt_hw_uart_init(); +#endif + +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + + NVIC_SetPriorityGrouping(7); + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +} + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void rt_hw_cpu_reset(void) +{ + SYS_UnlockReg(); + + SYS->IPRST0 |= SYS_IPRST0_CHIPRST_Msk; +} + +int reboot(int argc, char** argv) +{ + rt_hw_cpu_reset(); + return 0; +} +MSH_CMD_EXPORT(reboot, Reboot System); diff --git a/bsp/nuvoton/numaker-pfm-m487/board/board.h b/bsp/nuvoton/numaker-pfm-m487/board/board.h new file mode 100644 index 0000000000000000000000000000000000000000..4f2339210b8c25e3e2d307f85f650d18112db515 --- /dev/null +++ b/bsp/nuvoton/numaker-pfm-m487/board/board.h @@ -0,0 +1,25 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-1-16 Wayne First version +* +******************************************************************************/ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +// Internal SRAM memory size[Kbytes] <8-64> +#define SRAM_SIZE (160) +#define SRAM_END (0x20000000 + SRAM_SIZE * 1024) + +#define EE_TYPE AT24C64 + +void rt_hw_board_init(void); +void rt_hw_cpu_reset(void); + +#endif /* __BOARD_H__ */ diff --git a/bsp/nuvoton/numaker-pfm-m487/board/board_dev.c b/bsp/nuvoton/numaker-pfm-m487/board/board_dev.c new file mode 100644 index 0000000000000000000000000000000000000000..5a039f6b3072ed2db6eba3b3fe2973a8d1ae67a2 --- /dev/null +++ b/bsp/nuvoton/numaker-pfm-m487/board/board_dev.c @@ -0,0 +1,292 @@ +/**************************************************************************//** +* +* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-1-16 Wayne First version +* +******************************************************************************/ + +#include +#include + +#if defined(BOARD_USING_STORAGE_SPIFLASH) +#if defined(RT_USING_SFUD) + #include "spi_flash.h" + #include "spi_flash_sfud.h" +#endif + +#include "drv_qspi.h" + +#define W25X_REG_READSTATUS (0x05) +#define W25X_REG_READSTATUS2 (0x35) +#define W25X_REG_WRITEENABLE (0x06) +#define W25X_REG_WRITESTATUS (0x01) +#define W25X_REG_QUADENABLE (0x02) + +static rt_uint8_t SpiFlash_ReadStatusReg(struct rt_qspi_device *qspi_device) +{ + rt_uint8_t u8Val; + rt_uint8_t w25x_txCMD1 = W25X_REG_READSTATUS; + rt_qspi_send_then_recv(qspi_device, &w25x_txCMD1, 1, &u8Val, 1); + + return u8Val; +} + +static rt_uint8_t SpiFlash_ReadStatusReg2(struct rt_qspi_device *qspi_device) +{ + rt_uint8_t u8Val; + rt_uint8_t w25x_txCMD1 = W25X_REG_READSTATUS2; + rt_qspi_send_then_recv(qspi_device, &w25x_txCMD1, 1, &u8Val, 1); + + return u8Val; +} + +static void SpiFlash_WriteStatusReg(struct rt_qspi_device *qspi_device, uint8_t u8Value1, uint8_t u8Value2) +{ + rt_uint8_t w25x_txCMD1; + rt_uint8_t u8Val[3]; + + w25x_txCMD1 = W25X_REG_WRITEENABLE; + rt_qspi_send(qspi_device, &w25x_txCMD1, 1); + + u8Val[0] = W25X_REG_WRITESTATUS; + u8Val[1] = u8Value1; + u8Val[2] = u8Value2; + rt_qspi_send(qspi_device, &u8Val, 3); +} + +static void SpiFlash_WaitReady(struct rt_qspi_device *qspi_device) +{ + volatile uint8_t u8ReturnValue; + + do + { + u8ReturnValue = SpiFlash_ReadStatusReg(qspi_device); + u8ReturnValue = u8ReturnValue & 1; + } + while (u8ReturnValue != 0); // check the BUSY bit +} + +static void SpiFlash_EnterQspiMode(struct rt_qspi_device *qspi_device) +{ + uint8_t u8Status1 = SpiFlash_ReadStatusReg(qspi_device); + uint8_t u8Status2 = SpiFlash_ReadStatusReg2(qspi_device); + + u8Status2 |= W25X_REG_QUADENABLE; + SpiFlash_WriteStatusReg(qspi_device, u8Status1, u8Status2); + SpiFlash_WaitReady(qspi_device); +} + +static void SpiFlash_ExitQspiMode(struct rt_qspi_device *qspi_device) +{ + uint8_t u8Status1 = SpiFlash_ReadStatusReg(qspi_device); + uint8_t u8Status2 = SpiFlash_ReadStatusReg2(qspi_device); + + u8Status2 &= ~W25X_REG_QUADENABLE; + SpiFlash_WriteStatusReg(qspi_device, u8Status1, u8Status2); + SpiFlash_WaitReady(qspi_device); +} + +static int rt_hw_spiflash_init(void) +{ + /* Here, we use Dual I/O to drive the SPI flash by default. */ + /* If you want to use Quad I/O, you can modify to 4 from 2 and crossover D2/D3 pin of SPI flash. */ + if (nu_qspi_bus_attach_device("qspi0", "qspi01", 2, SpiFlash_EnterQspiMode, SpiFlash_ExitQspiMode) != RT_EOK) + return -1; + +#if defined(RT_USING_SFUD) + if (rt_sfud_flash_probe("flash0", "qspi01") == RT_NULL) + { + return -(RT_ERROR); + } +#endif + return 0; +} +INIT_COMPONENT_EXPORT(rt_hw_spiflash_init); +#endif /* BOARD_USING_STORAGE_SPIFLASH */ + +#if defined(BOARD_USING_SRAM0_AS_MEMHEAP) +/* +In Advance board design, SRAM address bus A16/A17/A18 are GPIO-controlled by SW, not EBI. +So we just remap 128KB only to RTT memory heap, due to it is out of controll. +AD0~AD15: 2^16*16bit = 128KB +*/ +#include +#include "NuMicro.h" +static struct rt_memheap system_heap; +int nu_use_exsram_as_heap(void) +{ + rt_err_t ret; + + /* Open ebi bank1 */ + ret = nu_ebi_init(EBI_BANK1, EBI_BUSWIDTH_16BIT, EBI_TIMING_SLOWEST, EBI_OPMODE_NORMAL, EBI_CS_ACTIVE_LOW); + if (ret != RT_EOK) + return ret; + + /* Initial sram as heap */ + return rt_memheap_init(&system_heap, "nu_sram_heap", (void *)EBI_BANK1_BASE_ADDR, 128 * 1024); +} +INIT_BOARD_EXPORT(nu_use_exsram_as_heap); +#endif /* BOARD_USING_SRAM0_AS_MEMHEAP */ + + +#if defined(BOARD_USING_MAX31875) +#include +int rt_hw_max31875_port(void) +{ + struct rt_sensor_config cfg; + + cfg.intf.dev_name = "i2c1"; + cfg.intf.user_data = (void *)MAX31875_I2C_SLAVE_ADR_R0; + cfg.irq_pin.pin = RT_PIN_NONE; + + rt_hw_max31875_init("max31875", &cfg); + return 0; +} +INIT_APP_EXPORT(rt_hw_max31875_port); +#endif /* BOARD_USING_MAX31875 */ + +#if defined(BOARD_USING_MPU6500) +#include +int rt_hw_mpu6500_port(void) +{ + struct rt_sensor_config cfg; + + cfg.intf.dev_name = "i2c2"; + cfg.intf.user_data = (void *)MPU6XXX_ADDR_DEFAULT; + cfg.irq_pin.pin = RT_PIN_NONE; + + rt_hw_mpu6xxx_init("mpu", &cfg); + return 0; +} +INIT_APP_EXPORT(rt_hw_mpu6500_port); +#endif /* BOARD_USING_MPU6500 */ + +#if defined(BOARD_USING_LCD_ILI9341) && defined(NU_PKG_USING_ILI9341_EBI) +#include +#if defined(PKG_USING_GUIENGINE) + #include +#endif +int rt_hw_ili9341_port(void) +{ + rt_err_t ret = RT_EOK; + + /* Open ebi BOARD_USING_ILI9341_EBI_PORT */ + ret = nu_ebi_init(BOARD_USING_ILI9341_EBI_PORT, EBI_BUSWIDTH_16BIT, EBI_TIMING_NORMAL, EBI_OPMODE_NORMAL, EBI_CS_ACTIVE_LOW); + if (ret != RT_EOK) + return ret; + + switch (BOARD_USING_ILI9341_EBI_PORT) + { + case 0: + EBI->CTL0 |= EBI_CTL0_CACCESS_Msk; + EBI->TCTL0 |= (EBI_TCTL0_WAHDOFF_Msk | EBI_TCTL0_RAHDOFF_Msk); + break; + case 1: + EBI->CTL1 |= EBI_CTL1_CACCESS_Msk; + EBI->TCTL1 |= (EBI_TCTL1_WAHDOFF_Msk | EBI_TCTL1_RAHDOFF_Msk); + break; + case 2: + EBI->CTL2 |= EBI_CTL2_CACCESS_Msk; + EBI->TCTL2 |= (EBI_TCTL2_WAHDOFF_Msk | EBI_TCTL2_RAHDOFF_Msk); + break; + default: + return -1; + } + + if (rt_hw_lcd_ili9341_ebi_init(EBI_BANK0_BASE_ADDR + BOARD_USING_ILI9341_EBI_PORT * EBI_MAX_SIZE) != RT_EOK) + return -1; + + rt_hw_lcd_ili9341_init(); + +#if defined(PKG_USING_GUIENGINE) + rt_device_t lcd_ili9341; + lcd_ili9341 = rt_device_find("lcd"); + if (lcd_ili9341) + { + rtgui_graphic_set_device(lcd_ili9341); + } +#endif + + return 0; +} +INIT_COMPONENT_EXPORT(rt_hw_ili9341_port); +#endif /* BOARD_USING_LCD_ILI9341 */ + +#if defined(BOARD_USING_NAU88L25) && defined(NU_PKG_USING_NAU88L25) +#include +S_NU_NAU88L25_CONFIG sCodecConfig = +{ + .i2c_bus_name = "i2c2", + + .i2s_bus_name = "sound0", + + .pin_phonejack_en = NU_GET_PININDEX(NU_PE, 13), + + .pin_phonejack_det = 0, +}; + +int rt_hw_nau88l25_port(void) +{ + if (nu_hw_nau88l25_init(&sCodecConfig) != RT_EOK) + return -1; + + return 0; +} +INIT_COMPONENT_EXPORT(rt_hw_nau88l25_port); +#endif /* BOARD_USING_NAU88L25 */ + +#if defined(BOARD_USING_BUZZER) + +#define BPWM_DEV_NAME "bpwm0" +#define BPWM_DEV_CHANNEL (5) + +static void PlayRingTone(void) +{ + struct rt_device_pwm *bpwm_dev; + rt_uint32_t period; + int i, j; + + period = 1000; + + if ((bpwm_dev = (struct rt_device_pwm *)rt_device_find(BPWM_DEV_NAME)) != RT_NULL) + { + rt_pwm_set(bpwm_dev, BPWM_DEV_CHANNEL, period, period); + rt_pwm_enable(bpwm_dev, BPWM_DEV_CHANNEL); + + for (j = 0; j < 5; j++) + { + for (i = 0; i < 10; i++) + { + rt_pwm_set(bpwm_dev, BPWM_DEV_CHANNEL, period, period); + rt_thread_mdelay(50); + + rt_pwm_set(bpwm_dev, BPWM_DEV_CHANNEL, period, period/2); + rt_thread_mdelay(50); + } + + /* Mute 2 seconds */ + rt_pwm_set(bpwm_dev, BPWM_DEV_CHANNEL, period, period); + rt_thread_mdelay(2000); + } + rt_pwm_disable(bpwm_dev, BPWM_DEV_CHANNEL); + } + else + { + rt_kprintf("Can't find %s\n", BPWM_DEV_NAME); + } +} + +int buzzer_test(void) +{ + PlayRingTone(); + return 0; +} +#ifdef FINSH_USING_MSH + MSH_CMD_EXPORT(buzzer_test, Buzzer - Play ring tone); +#endif +#endif /* BOARD_USING_BUZZER */ diff --git a/bsp/nuvoton/numaker-pfm-m487/board/fal_cfg.h b/bsp/nuvoton/numaker-pfm-m487/board/fal_cfg.h new file mode 100644 index 0000000000000000000000000000000000000000..d63249b836b4d0e541881d0d43d9d8de38278255 --- /dev/null +++ b/bsp/nuvoton/numaker-pfm-m487/board/fal_cfg.h @@ -0,0 +1,42 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-3-03 FYChou First version +* +******************************************************************************/ + +#ifndef _FAL_CFG_H_ +#define _FAL_CFG_H_ + +#include +#include + + +/* ===================== Flash device Configuration ========================= */ +extern const struct fal_flash_dev Onchip_aprom_flash; +extern const struct fal_flash_dev Onchip_ldrom_flash; + +/* -flash device table------------------------------------------------------- */ +#define FAL_FLASH_DEV_TABLE \ +{ \ + &Onchip_aprom_flash, \ + &Onchip_ldrom_flash, \ +} + +/* ====================== Partition Configuration ============================ */ +#ifdef FAL_PART_HAS_TABLE_CFG + +/* -partition table----------------------------------------------------------- */ +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WORD, "ldrom", "OnChip_LDROM", 0, 0x1000, 0}, \ + {FAL_PART_MAGIC_WORD, "aprom", "OnChip_APROM", 0x60000, 0x20000, 0}, \ +} +#endif /* FAL_PART_HAS_TABLE_CFG */ + +#endif /* _FAL_CFG_H_ */ diff --git a/bsp/nuvoton/numaker-pfm-m487/linking_scripts/m480_flash.icf b/bsp/nuvoton/numaker-pfm-m487/linking_scripts/m480_flash.icf new file mode 100644 index 0000000000000000000000000000000000000000..cd694e9ade688cd0c89901e45796de567b57bd8d --- /dev/null +++ b/bsp/nuvoton/numaker-pfm-m487/linking_scripts/m480_flash.icf @@ -0,0 +1,28 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x00080000; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x00028000; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x0400; +define symbol __ICFEDIT_size_heap__ = 0x0000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/nuvoton/numaker-pfm-m487/linking_scripts/m480_flash.sct b/bsp/nuvoton/numaker-pfm-m487/linking_scripts/m480_flash.sct new file mode 100644 index 0000000000000000000000000000000000000000..ac1da892d0a711b6ba6370ed28616d132b18962e --- /dev/null +++ b/bsp/nuvoton/numaker-pfm-m487/linking_scripts/m480_flash.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x80000 { ; load region size_region + ER_IROM1 0x00000000 0x80000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00028000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/nuvoton/numaker-pfm-m487/linking_scripts/m480_link.ld b/bsp/nuvoton/numaker-pfm-m487/linking_scripts/m480_link.ld new file mode 100644 index 0000000000000000000000000000000000000000..d33fc91ce8e30633646a0ed3f41490d8799b1863 --- /dev/null +++ b/bsp/nuvoton/numaker-pfm-m487/linking_scripts/m480_link.ld @@ -0,0 +1,161 @@ +/**************************************************************************//** +* +* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-1-16 Wayne First version +* +******************************************************************************/ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + CODE (rx) : ORIGIN = 0x00000000, LENGTH = 512k /* 512K flash */ + DATA (rw) : ORIGIN = 0x20000000, LENGTH = 160k /* 160K sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x1000; + +SECTIONS +{ + .vector : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + } > CODE = 0 + + .text : + { + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for utest */ + . = ALIGN(4); + __rt_utest_tc_tab_start = .; + KEEP(*(UtestTcTab)) + __rt_utest_tc_tab_end = .; + + . = ALIGN(4); + _etext = .; + } > CODE = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > CODE + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .stack : + { + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >DATA + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >DATA + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > DATA + __bss_end = .; + _end = .; + + __ram_top = ORIGIN(DATA) + LENGTH(DATA); + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/nuvoton/numaker-pfm-m487/rtconfig.py b/bsp/nuvoton/numaker-pfm-m487/rtconfig.py new file mode 100644 index 0000000000000000000000000000000000000000..902a2bdce94eb440af0deb11ea21c9cf90c36a06 --- /dev/null +++ b/bsp/nuvoton/numaker-pfm-m487/rtconfig.py @@ -0,0 +1,132 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='keil' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR + +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Program Files (x86)\GNU Tools ARM Embedded\6 2017-q1-update\bin' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:\Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.2' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = '' +# BUILD = 'debug' + + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'g++' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections -Wuninitialized' + + if BUILD == 'debug': + DEVICE = DEVICE + ' -DDEBUG' + + CFLAGS = DEVICE + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' + LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map -T ./linking_scripts/m480_link.ld ' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2 -gdwarf-2' + AFLAGS += ' -gdwarf-2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu=cortex-m4.fp' + CFLAGS = DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter ./linking_scripts/m480_flash.sct' + + CFLAGS += ' --c99' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/arm/bin40/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = ' ' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --debug' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' -Ol' + CFLAGS += ' --use_c++_inline' + + AFLAGS = '' + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu None' + + LFLAGS = ' --config ./linking_scripts/m480_flash.icf' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + LFLAGS += ' --redirect _Scanf=_ScanfSmall' + LFLAGS += ' --entry __iar_program_start' + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = '' diff --git a/bsp/nuvoton/numaker-pfm-m487/template.ewd b/bsp/nuvoton/numaker-pfm-m487/template.ewd new file mode 100644 index 0000000000000000000000000000000000000000..adeebbdc4e17efb87a9c5f3a838bdcddc3ec492b --- /dev/null +++ b/bsp/nuvoton/numaker-pfm-m487/template.ewd @@ -0,0 +1,1485 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 30 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 0 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 0 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/bsp/nuvoton/numaker-pfm-m487/template.ewp b/bsp/nuvoton/numaker-pfm-m487/template.ewp new file mode 100644 index 0000000000000000000000000000000000000000..bd5bdfb9902b292ab2afd0e6de3ea7824e751445 --- /dev/null +++ b/bsp/nuvoton/numaker-pfm-m487/template.ewp @@ -0,0 +1,1039 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 35 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + diff --git a/bsp/nuvoton/numaker-pfm-m487/template.eww b/bsp/nuvoton/numaker-pfm-m487/template.eww new file mode 100644 index 0000000000000000000000000000000000000000..e09d1b57a4f75315b8ce94f7ba22d546b8ce27a3 --- /dev/null +++ b/bsp/nuvoton/numaker-pfm-m487/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\Template.ewp + + + + + diff --git a/bsp/nuvoton/numaker-pfm-m487/template.uvproj b/bsp/nuvoton/numaker-pfm-m487/template.uvproj new file mode 100644 index 0000000000000000000000000000000000000000..c27707d0ea6a1d56f0f2146f18d81629e42fbe78 --- /dev/null +++ b/bsp/nuvoton/numaker-pfm-m487/template.uvproj @@ -0,0 +1,400 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread-m480 + 0x4 + ARM-ADS + + + M487JIDAE + Nuvoton + IRAM(0x20000000-0x20027FFF) IROM(0-0x7FFFF) CLOCK(192000000) CPUTYPE("Cortex-M4") FPU2 + + undefined + + 0 + + + + + + + + + + + SFD\Nuvoton\M481_v1.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil4\ + rtthread + 1 + 0 + 1 + 1 + 1 + .\build\keil4\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + fromelf.exe --bin --output "$L@L.bin" "$L@L.axf" + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + + SARMCM3.DLL + + TARMCM1.DLL + + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + + 0 + 10 + + + + + + + + + + + + + + NULink\Nu_Link.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4101 + + 0 + NULink\Nu_Link.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x28000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x28000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + --c99 + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + .\linking_scripts\m480_flash.sct + + + + + + + + + + + + diff --git a/bsp/nuvoton/numaker-pfm-m487/template.uvprojx b/bsp/nuvoton/numaker-pfm-m487/template.uvprojx new file mode 100644 index 0000000000000000000000000000000000000000..dc049f407505940e1d026c7db3ac9b3ab3dcfbed --- /dev/null +++ b/bsp/nuvoton/numaker-pfm-m487/template.uvprojx @@ -0,0 +1,401 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread-m480 + 0x4 + ARM-ADS + 0 + + + M487JIDAE + Nuvoton + Nuvoton.NuMicro_DFP.1.3.5 + http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack + IRAM(0x20000000,0x28000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0M481_AP_512 -FS00 -FL080000 -FP0($$Device:M487JIDAE$Flash\M481_AP_512.FLM)) + 0 + $$Device:M487JIDAE$Device\M480\Include\M480.h + + + + + + + + + + $$Device:M487JIDAE$SVD\Nuvoton\M481_v1.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil5\ + rtthread + 1 + 0 + 1 + 1 + 1 + .\build\keil5\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf.exe --bin --output "$L@L.bin" "$L@L.axf" + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + + SARMCM3.DLL + + TARMCM1.DLL + + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4103 + + 1 + NULink\Nu_Link.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x28000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x28000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --c99 + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\linking_scripts\m480_flash.sct + + + + + + + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/bsp/raspberry-pi/raspi4-32/.config b/bsp/raspberry-pi/raspi4-32/.config index 6f7fc20100b800a6784eef0f110d442395001f7d..e0db6a3e95fe90fa47d0d4182521c81b22b3215d 100644 --- a/bsp/raspberry-pi/raspi4-32/.config +++ b/bsp/raspberry-pi/raspi4-32/.config @@ -134,13 +134,19 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_I2C is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set -# CONFIG_RT_USING_SPI is not set +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_QSPI is not set +# CONFIG_RT_USING_SPI_MSD is not set +# CONFIG_RT_USING_SFUD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set @@ -475,6 +481,10 @@ CONFIG_BSP_USING_GIC=y CONFIG_BSP_USING_GIC400=y # CONFIG_BSP_USING_GIC500 is not set CONFIG_BSP_USING_PIN=y +CONFIG_BSP_USING_SPI=y +CONFIG_BSP_USING_SPI0_BUS=y +CONFIG_BSP_USING_SPI0_DEVICE0=y +# CONFIG_BSP_USING_SPI0_DEVICE1 is not set CONFIG_BSP_USING_CORETIMER=y # CONFIG_BSP_USING_SYSTIMER is not set # CONFIG_BSP_USING_WDT is not set diff --git a/bsp/raspberry-pi/raspi4-32/driver/Kconfig b/bsp/raspberry-pi/raspi4-32/driver/Kconfig index fb750ff60e3d6ba2d8744fd7c721fdabd642e2dc..5dca313513f414da4293c9de58990412cee43bb9 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/Kconfig +++ b/bsp/raspberry-pi/raspi4-32/driver/Kconfig @@ -50,6 +50,25 @@ menu "Hardware Drivers Config" select RT_USING_PIN default y + menuconfig BSP_USING_SPI + bool "Enable SPI" + select RT_USING_SPI + default n + + if BSP_USING_SPI + config BSP_USING_SPI0_BUS + bool "Enable SPI0 BUS" + default n + config BSP_USING_SPI0_DEVICE0 + bool "Enable SPI0 DEVICE0" + select BSP_USING_SPI0_BUS + default n + config BSP_USING_SPI0_DEVICE1 + bool "Enable SPI0 DEVICE1" + select BSP_USING_SPI0_BUS + default n + endif + config BSP_USING_CORETIMER bool "Using core timer" select RT_USING_CORETIMER diff --git a/bsp/raspberry-pi/raspi4-32/driver/SConscript b/bsp/raspberry-pi/raspi4-32/driver/SConscript index 533df8ac31d12aaf4a835cde3a1554d8d65d955a..64c764c1b3b3fdde2a31dfa5e8622069b4bcbd85 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/SConscript +++ b/bsp/raspberry-pi/raspi4-32/driver/SConscript @@ -4,6 +4,16 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') CPPPATH = [cwd, str(Dir('#'))] -group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('driver', src, depend = [''], CPPPATH = CPPPATH) + +# build for sub-directory +list = os.listdir(cwd) +objs = [] + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) +group = group + objs Return('group') diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c b/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c index e342032d55bf7d6131ad929d6be23a20ccf19adf..b45fb8574f5b7df79f696bdf47006ef1234c56ed 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c @@ -120,6 +120,34 @@ void prev_raspi_pin_mode(GPIO_PIN pin, GPIO_FUNC mode) raspi_set_pin_state(fselnum, gpfsel); } +void prev_raspi_pin_write(GPIO_PIN pin, int pin_value) +{ + uint32_t num = pin / 32; + + if(num == 0) + { + if(pin_value == 1) + { + GPIO_REG_GPSET0(GPIO_BASE) = 1 << (pin % 32); + } + else + { + GPIO_REG_GPCLR0(GPIO_BASE) = 1 << (pin % 32); + } + } + else + { + if(pin_value == 1) + { + GPIO_REG_GPSET1(GPIO_BASE) = 1 << (pin % 32); + } + else + { + GPIO_REG_GPCLR1(GPIO_BASE) = 1 << (pin % 32); + } + } +} + static void raspi_pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode) { GPIO_FUNC raspi_mode = OUTPUT; @@ -149,30 +177,7 @@ static void raspi_pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode) static void raspi_pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t value) { - uint32_t num = pin / 32; - - if(num == 0) - { - if(value == 0) - { - GPIO_REG_GPSET0(GPIO_BASE) = 1 << (pin % 32); - } - else - { - GPIO_REG_GPCLR0(GPIO_BASE) = 1 << (pin % 32); - } - } - else - { - if(value == 0) - { - GPIO_REG_GPSET1(GPIO_BASE) = 1 << (pin % 32); - } - else - { - GPIO_REG_GPCLR1(GPIO_BASE) = 1 << (pin % 32); - } - } + prev_raspi_pin_write(pin, value); } static int raspi_pin_read(struct rt_device *device, rt_base_t pin) diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.h b/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.h index 44fa0464fd3c8d9e77c2d3c4f44c2138aa7a1f90..7594759f97687aff3953b2d1e8ddffa06b5d356a 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.h +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.h @@ -134,6 +134,7 @@ typedef enum { } GPIO_PUPD_FUNC; void prev_raspi_pin_mode(GPIO_PIN pin, GPIO_FUNC mode); +void prev_raspi_pin_write(GPIO_PIN pin, int pin_value); int rt_hw_gpio_init(void); #endif /* __DRV_GPIO_H__ */ diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_spi.c b/bsp/raspberry-pi/raspi4-32/driver/drv_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..90ea26f7ab6715cb589a1337f5955612b0548c78 --- /dev/null +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_spi.c @@ -0,0 +1,296 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-22 bigmagic first version + */ +#include +#include +#include + +#include "raspi4.h" +#include "drv_spi.h" + +#ifdef RT_USING_SPI + +#define RPI_CORE_CLK_HZ (250000000) +#define BSP_SPI_MAX_HZ (30* 1000 *1000) +#define SPITIMEOUT 0x0FFF + +static rt_uint8_t raspi_byte_reverse_table[] = +{ + 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0, + 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0, + 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8, + 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8, + 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4, + 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4, + 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec, + 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc, + 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2, + 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2, + 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea, + 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa, + 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6, + 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6, + 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee, + 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe, + 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1, + 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1, + 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9, + 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9, + 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5, + 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5, + 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed, + 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd, + 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3, + 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3, + 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb, + 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb, + 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7, + 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7, + 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef, + 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff +}; + +#if defined (BSP_USING_SPI0_BUS) +#define SPI0_BUS_NAME "spi0" +#define SPI0_DEVICE0_NAME "spi0.0" +#define SPI0_DEVICE1_NAME "spi0.1" + +struct rt_spi_bus spi0_bus; + +#if defined (BSP_USING_SPI0_DEVICE0) +static struct rt_spi_device spi0_device0; +#endif + +#if defined (BSP_USING_SPI0_DEVICE1) +static struct rt_spi_device spi0_device1; +#endif +#endif + +static rt_err_t raspi_spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg) +{ + RT_ASSERT(cfg != RT_NULL); + RT_ASSERT(device != RT_NULL); + rt_uint16_t divider; + struct raspi_spi_device* hw_config = (struct raspi_spi_device *)(device->parent.user_data); + struct raspi_spi_hw_config *hwcfg = (struct raspi_spi_hw_config *)hw_config->spi_hw_config; + // spi clear fifo + SPI_REG_CS(hwcfg->hw_base) = (SPI_CS_CLEAR_TX | SPI_CS_CLEAR_RX); + if(cfg->mode & RT_SPI_CPOL) + { + SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CPOL; + } + + if(cfg->mode & RT_SPI_CPHA) + { + SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CPHA; + } + + if(cfg->mode & RT_SPI_CS_HIGH) + { + SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CSPOL_HIGH; + } + + //set clk + if (cfg->max_hz > BSP_SPI_MAX_HZ) + cfg->max_hz = BSP_SPI_MAX_HZ; + + divider = (rt_uint16_t) ((rt_uint32_t) RPI_CORE_CLK_HZ / cfg->max_hz); + divider &= 0xFFFE; + + SPI_REG_CLK(hwcfg->hw_base) = divider; + + return RT_EOK; +} + +rt_uint8_t correct_order(rt_uint8_t b, rt_uint8_t flag) +{ + if (flag) + return raspi_byte_reverse_table[b];//reverse + else + return b; +} + +static rt_err_t spi_transfernb(struct raspi_spi_hw_config *hwcfg, rt_uint8_t* tbuf, rt_uint8_t* rbuf, rt_uint32_t len, rt_uint8_t flag) +{ + rt_uint32_t TXCnt=0; + rt_uint32_t RXCnt=0; + + /* Clear TX and RX fifos */ + SPI_REG_CS(hwcfg->hw_base) |= (SPI_CS_CLEAR_TX | SPI_CS_CLEAR_RX); + + /* Set TA = 1 */ + SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_TA; + + /* Use the FIFO's to reduce the interbyte times */ + while ((TXCnt < len) || (RXCnt < len)) + { + /* TX fifo not full, so add some more bytes */ + while (((SPI_REG_CS(hwcfg->hw_base) & SPI_CS_TX_DATA)) && (TXCnt < len)) + { + SPI_REG_FIFO(hwcfg->hw_base) = correct_order(tbuf[TXCnt],flag); + TXCnt++; + } + /* Rx fifo not empty, so get the next received bytes */ + while (((SPI_REG_CS(hwcfg->hw_base) & SPI_CS_RX_DATA)) && (RXCnt < len)) + { + rbuf[RXCnt] = correct_order(SPI_REG_FIFO(hwcfg->hw_base), flag); + RXCnt++; + } + } + /* Wait for DONE to be set */ + while (!(SPI_REG_CS(hwcfg->hw_base) & SPI_CS_DONE)); + /* Set TA = 0, and also set the barrier */ + SPI_REG_CS(hwcfg->hw_base) |= (0 & SPI_CS_TA); + + return RT_EOK; +} + +static rt_uint32_t raspi_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ + rt_err_t res; + rt_uint8_t flag; + RT_ASSERT(device != RT_NULL); + RT_ASSERT(device->bus != RT_NULL); + RT_ASSERT(device->parent.user_data != RT_NULL); + RT_ASSERT(message->send_buf != RT_NULL || message->recv_buf != RT_NULL); + + struct rt_spi_configuration config = device->config; + struct raspi_spi_device * hw_config = (struct raspi_spi_device *)device->parent.user_data; + GPIO_PIN cs_pin = (GPIO_PIN)hw_config->cs_pin; + struct raspi_spi_hw_config *hwcfg = (struct raspi_spi_hw_config *)hw_config->spi_hw_config; + + if (config.mode & RT_SPI_MSB) + { + flag = 0; + } + else + { + flag = 1; + } + + if (message->cs_take) + { + (config.mode & RT_SPI_CS_HIGH)?prev_raspi_pin_write(cs_pin, 1):prev_raspi_pin_write(cs_pin, 0); + } + + res = spi_transfernb(hwcfg, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, flag); + if (message->cs_release) + { + (config.mode & RT_SPI_CS_HIGH)?prev_raspi_pin_write(cs_pin, 0):prev_raspi_pin_write(cs_pin, 1); + } + if (res != RT_EOK) + return RT_ERROR; + + return message->length; +} + +rt_err_t raspi_spi_bus_attach_device(const char *bus_name, struct raspi_spi_device *device) +{ + rt_err_t ret; + RT_ASSERT(device != RT_NULL); + ret = rt_spi_bus_attach_device(device->spi_device, device->device_name, bus_name, (void *)(device)); + return ret; +} + +rt_err_t raspi_spi_hw_init(struct raspi_spi_hw_config *hwcfg) +{ + prev_raspi_pin_mode(hwcfg->sclk_pin, hwcfg->sclk_mode); + prev_raspi_pin_mode(hwcfg->miso_pin, hwcfg->miso_mode); + prev_raspi_pin_mode(hwcfg->mosi_pin, hwcfg->mosi_mode); +#if defined (BSP_USING_SPI0_DEVICE0) + prev_raspi_pin_mode(hwcfg->ce0_pin, hwcfg->ce0_mode); +#endif + +#if defined (BSP_USING_SPI0_DEVICE1) + prev_raspi_pin_mode(hwcfg->ce1_pin, hwcfg->ce1_mode); +#endif + //clear rx and tx + SPI_REG_CS(hwcfg->hw_base) = (SPI_CS_CLEAR_TX | SPI_CS_CLEAR_RX); + //enable chip select +#if defined (BSP_USING_SPI0_DEVICE0) + SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CHIP_SELECT_0; +#endif + +#if defined (BSP_USING_SPI0_DEVICE1) + SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CHIP_SELECT_1; +#endif + +#if defined (BSP_USING_SPI0_DEVICE0) && defined (BSP_USING_SPI0_DEVICE1) + HWREG32(SPI_REG_CS(hwcfg->hw_base)) |= (SPI_CS_CHIP_SELECT_0 | SPI_CS_CHIP_SELECT_1); +#endif + return RT_EOK; +} + +static struct rt_spi_ops raspi_spi_ops = +{ + .configure = raspi_spi_configure, + .xfer = raspi_spi_xfer +}; + +struct raspi_spi_hw_config raspi_spi0_hw = +{ + .spi_num = 0, + .sclk_pin = GPIO_PIN_11, + .sclk_mode = ALT0, + .mosi_pin = GPIO_PIN_10, + .mosi_mode = ALT0, + .miso_pin = GPIO_PIN_9, + .miso_mode = ALT0, + +#if defined (BSP_USING_SPI0_DEVICE0) + .ce0_pin = GPIO_PIN_8, + .ce0_mode = ALT0, +#endif + +#if defined (BSP_USING_SPI0_DEVICE1) + .ce1_pin = GPIO_PIN_7, + .ce1_mode = ALT0, +#endif + .hw_base = SPI_0_BASE, +}; +#endif + +#if defined (BSP_USING_SPI0_DEVICE0) +struct raspi_spi_device raspi_spi0_device0 = +{ + .device_name = SPI0_DEVICE0_NAME, + .spi_bus = &spi0_bus, + .spi_device = &spi0_device0, + .spi_hw_config = &raspi_spi0_hw, + .cs_pin = GPIO_PIN_8, +}; +#endif + +#if defined (BSP_USING_SPI0_DEVICE1) +struct raspi_spi_device raspi_spi0_device1 = +{ + .device_name = SPI0_DEVICE1_NAME, + .spi_bus = &spi0_bus, + .spi_device = &spi0_device1, + .cs_pin = GPIO_PIN_7, +}; +#endif + +int rt_hw_spi_init(void) +{ +#if defined (BSP_USING_SPI0_BUS) + raspi_spi_hw_init(&raspi_spi0_hw); + rt_spi_bus_register(&spi0_bus, SPI0_BUS_NAME, &raspi_spi_ops); + +#if defined (BSP_USING_SPI0_DEVICE0) + raspi_spi_bus_attach_device(SPI0_BUS_NAME, &raspi_spi0_device0); +#endif + +#if defined (BSP_USING_SPI0_DEVICE1) + raspi_spi_bus_attach_device(SPI0_BUS_NAME, &raspi_spi0_device1); +#endif +#endif + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_spi_init); diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_spi.h b/bsp/raspberry-pi/raspi4-32/driver/drv_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..9cd8e031e4edd4e8f7e141ffdc2c9d83f12d8ecb --- /dev/null +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_spi.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-16 bigmagic first version + */ +#ifndef __DRV_SPI_H__ +#define __DRV_SPI_H__ + +#include "drv_gpio.h" + +#define SPI_REG_CS(BASE) HWREG32(BASE + 0x00) +#define SPI_REG_FIFO(BASE) HWREG32(BASE + 0x04) +#define SPI_REG_CLK(BASE) HWREG32(BASE + 0x08) +#define SPI_REG_DLEN(BASE) HWREG32(BASE + 0x0C) +#define SPI_REG_LTOH(BASE) HWREG32(BASE + 0x10) +#define SPI_REG_DC(BASE) HWREG32(BASE + 0x14) + +/* CS Register */ +#define SPI_CS_LOSSI_LONG_32BIT (1 << 25) +#define SPI_CS_LOSSI_DMA_MODE (1 << 24) +#define SPI_CS_CSPOL2 (1 << 23) +#define SPI_CS_CSPOL1 (1 << 22) +#define SPI_CS_CSPOL0 (1 << 21) +#define SPI_CS_RX_FIFO_FULL (1 << 20) +#define SPI_CS_RX_FIFO_3_QUARTER (1 << 19) +#define SPI_CS_TX_DATA (1 << 18) +#define SPI_CS_RX_DATA (1 << 17) +#define SPI_CS_DONE (1 << 16) +#define SPI_CS_LOSSI_EN (1 << 13) +#define SPI_CS_READ_EN (1 << 12) +#define SPI_CS_AUTO_CS (1 << 11) +#define SPI_CS_INTR_RXR (1 << 10) +#define SPI_CS_INTR_DONE (1 << 9) +#define SPI_CS_DMA_EN (1 << 8) +#define SPI_CS_TA (1 << 7) +#define SPI_CS_CSPOL_HIGH (1 << 6) +#define SPI_CS_CLEAR_RX (2 << 4) +#define SPI_CS_CLEAR_TX (1 << 4) +#define SPI_CS_CPOL (1 << 3) +#define SPI_CS_CPHA (1 << 2) +#define SPI_CS_CHIP_SELECT_2 (2 << 0) +#define SPI_CS_CHIP_SELECT_1 (1 << 0) +#define SPI_CS_CHIP_SELECT_0 (0 << 0) + +struct raspi_spi_hw_config +{ + rt_uint8_t spi_num; + GPIO_PIN sclk_pin; + GPIO_FUNC sclk_mode; + GPIO_PIN mosi_pin; + GPIO_FUNC mosi_mode; + GPIO_PIN miso_pin; + GPIO_FUNC miso_mode; +#if defined (BSP_USING_SPI0_DEVICE0) || defined (BSP_USING_SPI1_DEVICE0) + GPIO_PIN ce0_pin; + GPIO_FUNC ce0_mode; +#endif + +#if defined (BSP_USING_SPI0_DEVICE1) || defined (BSP_USING_SPI1_DEVICE1) + GPIO_PIN ce1_pin; + GPIO_FUNC ce1_mode; +#endif + +#if defined (BSP_USING_SPI1_DEVICE2) + GPIO_PIN ce2_pin; + GPIO_FUNC ce2_mode; +#endif + rt_ubase_t hw_base; + +}; + +struct raspi_spi_device +{ + char *device_name; + struct rt_spi_bus *spi_bus; + struct rt_spi_device *spi_device; + struct raspi_spi_hw_config *spi_hw_config; + GPIO_PIN cs_pin; +}; + +int rt_hw_spi_init(void); + +#endif diff --git a/bsp/raspberry-pi/raspi4-32/driver/raspi4.h b/bsp/raspberry-pi/raspi4-32/driver/raspi4.h index bfdf7bfecc2d0c31cf137317bb644cd132176ed7..f87469670567739c593491c56e88662d6d4a452c 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/raspi4.h +++ b/bsp/raspberry-pi/raspi4-32/driver/raspi4.h @@ -61,6 +61,18 @@ #define AUX_BASE (PER_BASE + AUX_BASE_OFFSET) #define IRQ_PL011 (96 + 57) +/* SPI */ +#define SPI_0_BASE_OFFSET (0x00204000) +#define SPI_3_BASE_OFFSET (0x00204600) +#define SPI_4_BASE_OFFSET (0x00204800) +#define SPI_5_BASE_OFFSET (0x00204A00) +#define SPI_6_BASE_OFFSET (0x00204C00) + +#define SPI_0_BASE (PER_BASE + SPI_0_BASE_OFFSET) +#define SPI_3_BASE (PER_BASE + SPI_3_BASE_OFFSET) +#define SPI_4_BASE (PER_BASE + SPI_4_BASE_OFFSET) +#define SPI_5_BASE (PER_BASE + SPI_5_BASE_OFFSET) +#define SPI_6_BASE (PER_BASE + SPI_6_BASE_OFFSET) /* Peripheral IRQ OR-ing */ #define PACTL_CS HWREG32((PER_BASE + PACTL_CS_OFFSET)) typedef enum { diff --git a/bsp/raspberry-pi/raspi4-32/rtconfig.h b/bsp/raspberry-pi/raspi4-32/rtconfig.h index c073fa500379a26c441bb71d1cf860acd55926af..c5ad40fc0b99e3d3513a338c8f0aea98266232d0 100644 --- a/bsp/raspberry-pi/raspi4-32/rtconfig.h +++ b/bsp/raspberry-pi/raspi4-32/rtconfig.h @@ -86,6 +86,7 @@ #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_PIN +#define RT_USING_SPI /* Using USB */ @@ -173,6 +174,9 @@ #define BSP_USING_GIC #define BSP_USING_GIC400 #define BSP_USING_PIN +#define BSP_USING_SPI +#define BSP_USING_SPI0_BUS +#define BSP_USING_SPI0_DEVICE0 #define BSP_USING_CORETIMER /* Board Peripheral Drivers */ diff --git a/bsp/stm32/libraries/HAL_Drivers/SConscript b/bsp/stm32/libraries/HAL_Drivers/SConscript index fddbc1fa932be27a801769010afe282d194109e8..2aaaf1d9186d4e12a2e18a4838fc33eb5a8a6da3 100644 --- a/bsp/stm32/libraries/HAL_Drivers/SConscript +++ b/bsp/stm32/libraries/HAL_Drivers/SConscript @@ -10,7 +10,7 @@ src = Split(""" if GetDepend(['RT_USING_PIN']): src += ['drv_gpio.c'] - + if GetDepend(['RT_USING_SERIAL']): src += ['drv_usart.c'] @@ -35,7 +35,7 @@ if GetDepend(['BSP_USING_ETH', 'RT_USING_LWIP']): if GetDepend(['RT_USING_ADC']): src += Glob('drv_adc.c') - + if GetDepend(['RT_USING_DAC']): src += Glob('drv_dac.c') @@ -58,6 +58,9 @@ if GetDepend('BSP_USING_LCD_MIPI'): if GetDepend('BSP_USING_ONCHIP_RTC'): src += ['drv_rtc.c'] +if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32G0']): + src += ['drv_flash/drv_flash_g0.c'] + if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F0']): src += ['drv_flash/drv_flash_f0.c'] diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f4.c b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f4.c index f36d5cdc697995b56bf11603eb1a0def3629552c..a9ed886c328a80440c31489f143166628aa11080 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f4.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f4.c @@ -211,6 +211,8 @@ int stm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size) { rt_err_t result = RT_EOK; rt_uint32_t end_addr = addr + size; + rt_uint32_t written_size = 0; + rt_uint32_t write_size = 0; if ((end_addr) > STM32_FLASH_END_ADDRESS) { @@ -227,22 +229,61 @@ int stm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size) __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR); - for (size_t i = 0; i < size; i++, addr++, buf++) + while (written_size < size) { - /* write data to flash */ - if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_BYTE, addr, (rt_uint64_t)(*buf)) == HAL_OK) + if (((addr + written_size) % 4 == 0) && (size - written_size >= 4)) { - if (*(rt_uint8_t *)addr != *buf) + if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, addr + written_size, *((rt_uint32_t *)(buf + written_size))) == HAL_OK) + { + if (*(rt_uint32_t *)(addr + written_size) != *(rt_uint32_t *)(buf + written_size)) + { + result = -RT_ERROR; + break; + } + } + else { result = -RT_ERROR; break; } + write_size = 4; + } + else if (((addr + written_size) % 2 == 0) && (size - written_size >= 2)) + { + if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_HALFWORD, addr + written_size, *((rt_uint16_t *)(buf + written_size))) == HAL_OK) + { + if (*(rt_uint16_t *)(addr + written_size) != *(rt_uint16_t *)(buf + written_size)) + { + result = -RT_ERROR; + break; + } + } + else + { + result = -RT_ERROR; + break; + } + write_size = 2; } else { - result = -RT_ERROR; - break; + if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_BYTE, addr + written_size, *((rt_uint8_t *)(buf + written_size))) == HAL_OK) + { + if (*(rt_uint8_t *)(addr + written_size) != *(rt_uint8_t *)(buf + written_size)) + { + result = -RT_ERROR; + break; + } + } + else + { + result = -RT_ERROR; + break; + } + write_size = 1; } + + written_size += write_size; } HAL_FLASH_Lock(); @@ -277,6 +318,11 @@ int stm32_flash_erase(rt_uint32_t addr, size_t size) return -RT_EINVAL; } + if (size < 1) + { + return -RT_EINVAL; + } + /*Variable used for Erase procedure*/ FLASH_EraseInitTypeDef EraseInitStruct; diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_g0.c b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_g0.c new file mode 100644 index 0000000000000000000000000000000000000000..c5eefb94972bb0214498d1d546d72454e949a420 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_g0.c @@ -0,0 +1,230 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-27 NU-LL first version + */ + +#include "board.h" + +#ifdef BSP_USING_ON_CHIP_FLASH +#include "drv_config.h" +#include "drv_flash.h" + +#if defined(PKG_USING_FAL) +#include "fal.h" +#endif + +// #define DRV_DEBUG +#define LOG_TAG "drv.flash" +#include + +/** + * @brief Gets the page of a given address + * @param Addr: Address of the FLASH Memory + * @retval The page of a given address + */ +static uint32_t GetPage(uint32_t addr) +{ + uint32_t page = 0; + page = RT_ALIGN_DOWN(addr-STM32_FLASH_START_ADRESS, FLASH_PAGE_SIZE)/FLASH_PAGE_SIZE; + return page; +} + +/** + * Read data from flash. + * @note This operation's units is word. + * + * @param addr flash address + * @param buf buffer to store read data + * @param size read bytes size + * + * @return result + */ +int stm32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size) +{ + size_t i; + + if ((addr + size) > STM32_FLASH_END_ADDRESS) + { + LOG_E("read outrange flash size! addr is (0x%p)", (void *)(addr + size)); + return -RT_EINVAL; + } + + for (i = 0; i < size; i++, buf++, addr++) + { + *buf = *(rt_uint8_t *) addr; + } + + return size; +} + +/** + * Write data to flash. + * @note This operation's units is word. + * @note This operation must after erase. @see flash_erase. + * + * @param addr flash address + * @param buf the write data buffer + * @param size write bytes size + * + * @return result + */ +int stm32_flash_write(rt_uint32_t addr, const uint8_t *buf, size_t size) +{ + size_t i, j; + rt_err_t result = 0; + rt_uint64_t write_data = 0, temp_data = 0; + + if ((addr + size) > STM32_FLASH_END_ADDRESS) + { + LOG_E("ERROR: write outrange flash size! addr is (0x%p)\n", (void*)(addr + size)); + return -RT_EINVAL; + } + + if(addr % 8 != 0) + { + LOG_E("write addr must be 8-byte alignment"); + return -RT_EINVAL; + } + + HAL_FLASH_Unlock(); + + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGSERR); + + if (size < 1) + { + return -RT_ERROR; + } + + for (i = 0; i < size;) + { + if ((size - i) < 8) + { + for (j = 0; (size - i) > 0; i++, j++) + { + temp_data = *buf; + write_data = (write_data) | (temp_data << 8 * j); + buf ++; + } + } + else + { + for (j = 0; j < 8; j++, i++) + { + temp_data = *buf; + write_data = (write_data) | (temp_data << 8 * j); + buf ++; + } + } + + /* write data */ + if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, addr, write_data) == HAL_OK) + { + /* Check the written value */ + if (*(uint64_t*)addr != write_data) + { + LOG_E("ERROR: write data != read data\n"); + result = -RT_ERROR; + goto __exit; + } + } + else + { + result = -RT_ERROR; + goto __exit; + } + + temp_data = 0; + write_data = 0; + + addr += 8; + } + +__exit: + HAL_FLASH_Lock(); + if (result != 0) + { + return result; + } + + return size; +} + +/** + * Erase data on flash. + * @note This operation is irreversible. + * @note This operation's units is different which on many chips. + * + * @param addr flash address + * @param size erase bytes size + * + * @return result + */ +int stm32_flash_erase(rt_uint32_t addr, size_t size) +{ + rt_err_t result = RT_EOK; + uint32_t PAGEError = 0; + + /*Variable used for Erase procedure*/ + FLASH_EraseInitTypeDef EraseInitStruct; + + if ((addr + size) > STM32_FLASH_END_ADDRESS) + { + LOG_E("ERROR: erase outrange flash size! addr is (0x%p)\n", (void *)(addr + size)); + return -RT_EINVAL; + } + + HAL_FLASH_Unlock(); + + /* Fill EraseInit structure*/ + EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES; + EraseInitStruct.Page = GetPage(addr); + EraseInitStruct.NbPages = (size + FLASH_PAGE_SIZE - 1) / FLASH_PAGE_SIZE; + + if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK) + { + result = -RT_ERROR; + goto __exit; + } + +__exit: + HAL_FLASH_Lock(); + + if (result != RT_EOK) + { + return result; + } + + LOG_D("erase done: addr (0x%p), size %d", (void *)addr, size); + return size; +} + +#if defined(PKG_USING_FAL) + +static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size); +static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size); +static int fal_flash_erase(long offset, size_t size); + +const struct fal_flash_dev stm32_onchip_flash = { "onchip_flash", STM32_FLASH_START_ADRESS, STM32_FLASH_SIZE, FLASH_PAGE_SIZE, {NULL, fal_flash_read, fal_flash_write, fal_flash_erase} }; + +static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size) +{ + return stm32_flash_read(stm32_onchip_flash.addr + offset, buf, size); +} + +static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size) +{ + return stm32_flash_write(stm32_onchip_flash.addr + offset, buf, size); +} + +static int fal_flash_erase(long offset, size_t size) +{ + return stm32_flash_erase(stm32_onchip_flash.addr + offset, size); +} + +#endif +#endif /* BSP_USING_ON_CHIP_FLASH */ diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/SConscript b/bsp/stm32/libraries/STM32G0xx_HAL/SConscript index 934239833de12d4f05ef7a5e4703f3dae16d1b82..3d712c5d0b67c693f94bb03bd09bdbd713b115aa 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/SConscript +++ b/bsp/stm32/libraries/STM32G0xx_HAL/SConscript @@ -33,7 +33,7 @@ if GetDepend(['RT_USING_I2C']): if GetDepend(['RT_USING_SPI']): src += ['STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_spi.c'] - src += ['STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_spi_ex.c'] + src += ['STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_spi_ex.c'] src += ['STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_spi.c'] if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']): @@ -50,7 +50,12 @@ if GetDepend(['RT_USING_WDT']): src += ['STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_iwdg.c'] src += ['STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_wwdg.c'] -path = [cwd + '/STM32G0xx_HAL_Driver/Inc', +if GetDepend(['RT_USING_RTC']): + src += ['STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rtc.c'] + src += ['STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rtc_ex.c'] + src += ['STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rtc.c'] + +path = [cwd + '/STM32G0xx_HAL_Driver/Inc', cwd + '/CMSIS/Device/ST/STM32G0xx/Include', cwd + '/CMSIS/Include'] diff --git a/bsp/stm32/stm32f407-armfly-v5/.config b/bsp/stm32/stm32f407-armfly-v5/.config new file mode 100644 index 0000000000000000000000000000000000000000..13a4d62a3afbb8c1dfdf24c130d90193d5d2e3ec --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/.config @@ -0,0 +1,351 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x40000 +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M4=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +CONFIG_FINSH_USING_MSH_ONLY=y +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_MTD is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set + +# +# Using WiFi +# +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +# CONFIG_RT_USING_LIBC is not set +# CONFIG_RT_USING_PTHREADS is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# Modbus master and slave stack +# +# CONFIG_RT_USING_MODBUS is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_LOGTRACE is not set +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set + +# +# ARM CMSIS +# +# CONFIG_RT_USING_CMSIS_OS is not set +# CONFIG_RT_USING_RTT_CMSIS is not set +# CONFIG_RT_USING_LWP is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOTKIT is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +CONFIG_SOC_FAMILY_STM32=y +CONFIG_SOC_SERIES_STM32F4=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_STM32F407ZG=y + +# +# Onboard Peripheral Drivers +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_UART1_RX_USING_DMA is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_I2C1 is not set + +# +# Board extended module Drivers +# diff --git a/bsp/stm32/stm32f407-armfly-v5/.gitignore b/bsp/stm32/stm32f407-armfly-v5/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..7221bde019df6157cbf9e42ef5ab8a78420e3b68 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/.gitignore @@ -0,0 +1,42 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h diff --git a/bsp/stm32/stm32f407-armfly-v5/Kconfig b/bsp/stm32/stm32f407-armfly-v5/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..8cbc7b71a8c0cf95b0cefa5f35f19353215eb570 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/Kconfig @@ -0,0 +1,21 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" +source "board/Kconfig" diff --git a/bsp/stm32/stm32f407-armfly-v5/README.md b/bsp/stm32/stm32f407-armfly-v5/README.md new file mode 100644 index 0000000000000000000000000000000000000000..4f2f74f36b74293ec512b30bc343ad93d6f4cbe0 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/README.md @@ -0,0 +1,125 @@ +# STM32F429 armfly-v5 开发板 BSP 说明 + +## 简介 + +本文档为 STM32F429 armfly-v5 开发板的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +armfly-v5 STM32F407 是安富莱推出的一款基于 ARM Cortex-M4 内核的开发板，最高主频为 168Mhz，该开发板具有丰富的板载资源，可以充分发挥 STM32F407 的芯片性能。 + +开发板外观如下图所示： + +![board](figures/board.png) + +该开发板常用 **板载资源** 如下： + +- MCU：STM32F407IGT6，主频 168MHz，1024KB FLASH ，196KB RAM +- 外部 RAM：IS61WV102416BLL-10TL（SRAM，20MB，16bit） +- 外部 FLASH：W25Q64BVSSIG（SPI，8MB）、HY27UF081G2A（NAND，128MB） +- 常用外设 + - LED：4个， LED1 - LED4 + - 按键：4个，k1（PI8），K2（PC13），k3（PI11），五向摇杆 +- 常用接口：USB 转串口、SD 卡接口、以太网接口、LCD 接口 +- 调试接口，SWD + +开发板更多详细信息请参考【安富莱】 [STM32 v5开发板介绍](http://www.armbbs.cn/forum.php?mod=viewthread&tid=1285)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :----------------- | :----------: | :------------------------------------- | +| USB 转串口 | 支持 | UART1/2 | +| SPI Flash | 支持 | W25Q64BVSSIG 8M FLASH SPI3 | +| MPU6050 | 支持 | 软件 I2C2 | +| SD卡 | 支持 | | +| CAN | 暂不支持 | | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | PA0, PA1... PK15 ---> PIN: 0, 1...176 | +| UART | 支持 | UART1 | +| SPI | 支持 | SPI3 | +| I2C | 支持 | 软件 I2C2 | +| ADC | 支持 | | +| RTC | 支持 | 支持外部晶振和内部低速时钟 | +| WDT | 支持 | | +| FLASH | 支持 | 已适配 [FAL](https://github.com/RT-Thread-packages/fal) | +| SDIO | 支持 | | +| PWM | 支持 | | +| USB Device | 暂不支持 | 即将支持 | +| USB Host | 暂不支持 | 即将支持 | +| **扩展模块** | **支持情况** | **备注** | +| ad7606 | 暂不支持 | | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用数据线连接开发板到 PC，打开电源开关。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 STLink 仿真器下载程序，在通过 STLink 连接开发板的基础上，点击下载按钮即可下载程序到开发板 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，【这里写开发板运行起来之后的现象，如：LED 闪烁等】。 + +连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.2 build Jul 13 2020 + 2006 - 2019 Copyright by rt-thread team +msh > +``` +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口1 的功能，如果需使用 SD 卡、Flash 等更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 + +本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 + +## 注意事项 + +- 暂无 + +## 联系人信息 + +维护人: + +- [Dozingfiretruck](https://gitee.com/Dozingfiretruck), 邮箱： \ No newline at end of file diff --git a/bsp/stm32/stm32f407-armfly-v5/SConscript b/bsp/stm32/stm32f407-armfly-v5/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..20f7689c53ca71a676748f79187f9764065466c5 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/stm32/stm32f407-armfly-v5/SConstruct b/bsp/stm32/stm32f407-armfly-v5/SConstruct new file mode 100644 index 0000000000000000000000000000000000000000..945cb55a525ed8ab54c52465c9a6232c2b0c598a --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/SConstruct @@ -0,0 +1,60 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rt-thread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +stm32_library = 'STM32F4xx_HAL' +rtconfig.BSP_LIBRARY_TYPE = stm32_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, stm32_library, 'SConscript'))) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/stm32/stm32f407-armfly-v5/applications/SConscript b/bsp/stm32/stm32f407-armfly-v5/applications/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..6f66f7ab7360b02f3561ec14d3f28841190e7e83 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/applications/SConscript @@ -0,0 +1,12 @@ +import rtconfig +from building import * + +cwd = GetCurrentDir() +CPPPATH = [cwd, str(Dir('#'))] +src = Split(""" +main.c +""") + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/stm32/stm32f407-armfly-v5/applications/main.c b/bsp/stm32/stm32f407-armfly-v5/applications/main.c new file mode 100644 index 0000000000000000000000000000000000000000..297573866c8c809ce27374dd2c6906bc9df29a22 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/applications/main.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-13 Dozingfiretruck first version + */ + +#include +#include +#include + +/* defined the LED4 pin: PC2 */ +#define LED0_PIN GET_PIN(C, 2) + +int main(void) +{ + int count = 1; + /* set LED0 pin mode to output */ + rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); + + while (count++) + { + rt_pin_write(LED0_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED0_PIN, PIN_LOW); + rt_thread_mdelay(500); + } + + return RT_EOK; +} diff --git a/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/.mxproject new file mode 100644 index 0000000000000000000000000000000000000000..4638fb8888753cef2d0e6520c32bf1590ffe2cd4 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/.mxproject @@ -0,0 +1,19 @@ +[PreviousGenFiles] +HeaderPath=C:/Users/qq147/Desktop/rt-thread/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Inc +HeaderFiles=stm32f4xx_it.h;stm32f4xx_hal_conf.h;main.h; +SourcePath=C:/Users/qq147/Desktop/rt-thread/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src +SourceFiles=stm32f4xx_it.c;stm32f4xx_hal_msp.c;main.c; + +[PreviousLibFiles] +LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rng.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rng.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rng.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h; + +[PreviousUsedIarFiles] +SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;..\\Src/system_stm32f4xx.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;..\\Src/system_stm32f4xx.c;..\Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;; +HeaderPath=..\Drivers\STM32F4xx_HAL_Driver\Inc;..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F4xx\Include;..\Drivers\CMSIS\Include;..\Inc; +CDefines=USE_HAL_DRIVER;STM32F407xx;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[PreviousUsedKeilFiles] +SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rng.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;..\\Src/system_stm32f4xx.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rng.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;..\\Src/system_stm32f4xx.c;..\Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;; +HeaderPath=..\Drivers\STM32F4xx_HAL_Driver\Inc;..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F4xx\Include;..\Drivers\CMSIS\Include;..\Inc; +CDefines=USE_HAL_DRIVER;STM32F407xx;USE_HAL_DRIVER;USE_HAL_DRIVER; + diff --git a/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/CubeMX_Config.ioc new file mode 100644 index 0000000000000000000000000000000000000000..07773020232fc505c87b4ffc590f991c37f86eed --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/CubeMX_Config.ioc @@ -0,0 +1,234 @@ +#MicroXplorer Configuration settings - do not modify +ADC1.Channel-3\#ChannelRegularConversion=ADC_CHANNEL_9 +ADC1.IPParameters=Rank-3\#ChannelRegularConversion,master,Channel-3\#ChannelRegularConversion,SamplingTime-3\#ChannelRegularConversion,NbrOfConversionFlag +ADC1.NbrOfConversionFlag=1 +ADC1.Rank-3\#ChannelRegularConversion=1 +ADC1.SamplingTime-3\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES +ADC1.master=1 +File.Version=6 +GPIO.groupedBy=Group By Peripherals +I2S2.ErrorAudioFreq=-0.27 % +I2S2.FullDuplexMode=I2S_FULLDUPLEXMODE_ENABLE +I2S2.IPParameters=Instance,VirtualMode,FullDuplexMode,RealAudioFreq,ErrorAudioFreq +I2S2.Instance=SPI$Index +I2S2.RealAudioFreq=7.978 KHz +I2S2.VirtualMode=I2S_MODE_MASTER +KeepUserPlacement=false +Mcu.Family=STM32F4 +Mcu.IP0=ADC1 +Mcu.IP1=I2S2 +Mcu.IP10=TIM10 +Mcu.IP11=TIM11 +Mcu.IP12=TIM13 +Mcu.IP13=TIM14 +Mcu.IP14=USART1 +Mcu.IP15=USART2 +Mcu.IP2=IWDG +Mcu.IP3=NVIC +Mcu.IP4=RCC +Mcu.IP5=RNG +Mcu.IP6=RTC +Mcu.IP7=SDIO +Mcu.IP8=SPI3 +Mcu.IP9=SYS +Mcu.IPNb=16 +Mcu.Name=STM32F407I(E-G)Tx +Mcu.Package=LQFP176 +Mcu.Pin0=PC14-OSC32_IN +Mcu.Pin1=PC15-OSC32_OUT +Mcu.Pin10=PB15 +Mcu.Pin11=PC6 +Mcu.Pin12=PC8 +Mcu.Pin13=PC9 +Mcu.Pin14=PA9 +Mcu.Pin15=PA10 +Mcu.Pin16=PA13 +Mcu.Pin17=PI2 +Mcu.Pin18=PA14 +Mcu.Pin19=PC10 +Mcu.Pin2=PF6 +Mcu.Pin20=PC11 +Mcu.Pin21=PC12 +Mcu.Pin22=PD2 +Mcu.Pin23=PB3 +Mcu.Pin24=PB4 +Mcu.Pin25=PB5 +Mcu.Pin26=VP_IWDG_VS_IWDG +Mcu.Pin27=VP_RNG_VS_RNG +Mcu.Pin28=VP_RTC_VS_RTC_Activate +Mcu.Pin29=VP_SYS_VS_Systick +Mcu.Pin3=PH0-OSC_IN +Mcu.Pin30=VP_TIM10_VS_ClockSourceINT +Mcu.Pin31=VP_TIM11_VS_ClockSourceINT +Mcu.Pin32=VP_TIM13_VS_ClockSourceINT +Mcu.Pin33=VP_TIM14_VS_ClockSourceINT +Mcu.Pin4=PH1-OSC_OUT +Mcu.Pin5=PA2 +Mcu.Pin6=PA3 +Mcu.Pin7=PB1 +Mcu.Pin8=PB12 +Mcu.Pin9=PB13 +Mcu.PinsNb=34 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32F407IGTx +MxCube.Version=5.6.1 +MxDb.Version=DB.5.0.60 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +PA10.Mode=Asynchronous +PA10.Signal=USART1_RX +PA13.Mode=Serial_Wire +PA13.Signal=SYS_JTMS-SWDIO +PA14.Mode=Serial_Wire +PA14.Signal=SYS_JTCK-SWCLK +PA2.Mode=Asynchronous +PA2.Signal=USART2_TX +PA3.Mode=Asynchronous +PA3.Signal=USART2_RX +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PB1.Signal=ADCx_IN9 +PB12.Mode=Full_Duplex_Master +PB12.Signal=I2S2_WS +PB13.Locked=true +PB13.Mode=Full_Duplex_Master +PB13.Signal=I2S2_CK +PB15.Mode=Full_Duplex_Master +PB15.Signal=I2S2_SD +PB3.Mode=Full_Duplex_Master +PB3.Signal=SPI3_SCK +PB4.Mode=Full_Duplex_Master +PB4.Signal=SPI3_MISO +PB5.Mode=Full_Duplex_Master +PB5.Signal=SPI3_MOSI +PC10.Mode=SD_4_bits_Wide_bus +PC10.Signal=SDIO_D2 +PC11.Mode=SD_4_bits_Wide_bus +PC11.Signal=SDIO_D3 +PC12.Mode=SD_4_bits_Wide_bus +PC12.Signal=SDIO_CK +PC14-OSC32_IN.Mode=LSE-External-Oscillator +PC14-OSC32_IN.Signal=RCC_OSC32_IN +PC15-OSC32_OUT.Mode=LSE-External-Oscillator +PC15-OSC32_OUT.Signal=RCC_OSC32_OUT +PC6.Mode=Master_Clock_Activated +PC6.Signal=I2S2_MCK +PC8.Mode=SD_4_bits_Wide_bus +PC8.Signal=SDIO_D0 +PC9.Mode=SD_4_bits_Wide_bus +PC9.Signal=SDIO_D1 +PD2.Mode=SD_4_bits_Wide_bus +PD2.Signal=SDIO_CMD +PF6.Signal=S_TIM10_CH1 +PH0-OSC_IN.Mode=HSE-External-Oscillator +PH0-OSC_IN.Signal=RCC_OSC_IN +PH1-OSC_OUT.Mode=HSE-External-Oscillator +PH1-OSC_OUT.Signal=RCC_OSC_OUT +PI2.Locked=true +PI2.Mode=Full_Duplex_Master +PI2.Signal=I2S2_ext_SD +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=false +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32F407IGTx +ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.25.0 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=0 +ProjectManager.MainLocation=Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=CubeMX_Config.ioc +ProjectManager.ProjectName=CubeMX_Config +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=MDK-ARM V5.27 +ProjectManager.ToolChainLocation= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_ADC1_Init-ADC1-false-HAL-true,5-MX_I2S2_Init-I2S2-false-HAL-true,6-MX_IWDG_Init-IWDG-false-HAL-true,7-MX_RTC_Init-RTC-false-HAL-true,8-MX_SDIO_SD_Init-SDIO-false-HAL-true,9-MX_SPI3_Init-SPI3-false-HAL-true,10-MX_TIM10_Init-TIM10-false-HAL-true,11-MX_TIM11_Init-TIM11-false-HAL-true,12-MX_TIM13_Init-TIM13-false-HAL-true,13-MX_TIM14_Init-TIM14-false-HAL-true,14-MX_RNG_Init-RNG-false-HAL-true,15-MX_USART2_UART_Init-USART2-false-HAL-true +RCC.48MHZClocksFreq_Value=48000000 +RCC.AHBFreq_Value=168000000 +RCC.APB1CLKDivider=RCC_HCLK_DIV4 +RCC.APB1Freq_Value=42000000 +RCC.APB1TimFreq_Value=84000000 +RCC.APB2CLKDivider=RCC_HCLK_DIV2 +RCC.APB2Freq_Value=84000000 +RCC.APB2TimFreq_Value=168000000 +RCC.CortexFreq_Value=168000000 +RCC.EthernetFreq_Value=168000000 +RCC.FCLKCortexFreq_Value=168000000 +RCC.FamilyName=M +RCC.HCLKFreq_Value=168000000 +RCC.HSE_VALUE=25000000 +RCC.HSI_VALUE=16000000 +RCC.I2SClocksFreq_Value=96000000 +RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLSourceVirtual,RCC_RTC_Clock_Source,RCC_RTC_Clock_SourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VcooutputI2S +RCC.LSI_VALUE=32000 +RCC.MCO2PinFreq_Value=168000000 +RCC.PLLCLKFreq_Value=168000000 +RCC.PLLM=25 +RCC.PLLN=336 +RCC.PLLQ=7 +RCC.PLLQCLKFreq_Value=48000000 +RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE +RCC.RCC_RTC_Clock_Source=RCC_RTCCLKSOURCE_LSE +RCC.RCC_RTC_Clock_SourceVirtual=RCC_RTCCLKSOURCE_LSE +RCC.RTCFreq_Value=32768 +RCC.RTCHSEDivFreq_Value=12500000 +RCC.SYSCLKFreq_VALUE=168000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.VCOI2SOutputFreq_Value=192000000 +RCC.VCOInputFreq_Value=1000000 +RCC.VCOOutputFreq_Value=336000000 +RCC.VcooutputI2S=96000000 +SH.ADCx_IN9.0=ADC1_IN9,IN9 +SH.ADCx_IN9.ConfNb=1 +SH.S_TIM10_CH1.0=TIM10_CH1,PWM Generation1 CH1 +SH.S_TIM10_CH1.ConfNb=1 +SPI3.CalculateBaudRate=21.0 MBits/s +SPI3.Direction=SPI_DIRECTION_2LINES +SPI3.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate +SPI3.Mode=SPI_MODE_MASTER +SPI3.VirtualType=VM_MASTER +TIM10.Channel=TIM_CHANNEL_1 +TIM10.IPParameters=Channel +USART1.IPParameters=VirtualMode +USART1.VirtualMode=VM_ASYNC +USART2.IPParameters=VirtualMode +USART2.VirtualMode=VM_ASYNC +VP_IWDG_VS_IWDG.Mode=IWDG_Activate +VP_IWDG_VS_IWDG.Signal=IWDG_VS_IWDG +VP_RNG_VS_RNG.Mode=RNG_Activate +VP_RNG_VS_RNG.Signal=RNG_VS_RNG +VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled +VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +VP_TIM10_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM10_VS_ClockSourceINT.Signal=TIM10_VS_ClockSourceINT +VP_TIM11_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM11_VS_ClockSourceINT.Signal=TIM11_VS_ClockSourceINT +VP_TIM13_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM13_VS_ClockSourceINT.Signal=TIM13_VS_ClockSourceINT +VP_TIM14_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM14_VS_ClockSourceINT.Signal=TIM14_VS_ClockSourceINT +board=custom diff --git a/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Inc/main.h b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Inc/main.h new file mode 100644 index 0000000000000000000000000000000000000000..71f8e09516fb5ec542ebd1aa79ac1e5404709a6d --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Inc/main.h @@ -0,0 +1,73 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h new file mode 100644 index 0000000000000000000000000000000000000000..9638f92d62094f4c101db85a861a432d8757c55a --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h @@ -0,0 +1,443 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_conf_template.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32f4xx_hal_conf.h. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_CONF_H +#define __STM32F4xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED + + #define HAL_ADC_MODULE_ENABLED +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_CAN_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_DCMI_MODULE_ENABLED */ +/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_ETH_MODULE_ENABLED */ +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_PCCARD_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ +/* #define HAL_I2C_MODULE_ENABLED */ +#define HAL_I2S_MODULE_ENABLED +#define HAL_IWDG_MODULE_ENABLED +/* #define HAL_LTDC_MODULE_ENABLED */ +#define HAL_RNG_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED +/* #define HAL_SAI_MODULE_ENABLED */ +#define HAL_SD_MODULE_ENABLED +/* #define HAL_MMC_MODULE_ENABLED */ +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIM_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +/* #define HAL_PCD_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_FMPI2C_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +/* #define HAL_DFSDM_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the External audio frequency in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U +#define INSTRUCTION_CACHE_ENABLE 1U +#define DATA_CACHE_ENABLE 1U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2U +#define MAC_ADDR1 0U +#define MAC_ADDR2 0U +#define MAC_ADDR3 0U +#define MAC_ADDR4 0U +#define MAC_ADDR5 0U + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848_PHY_ADDRESS Address*/ +#define DP83848_PHY_ADDRESS 0x01U +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) + +#define PHY_READ_TO ((uint32_t)0x0000FFFFU) +#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ +#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ + +#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f4xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32f4xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f4xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f4xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f4xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f4xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f4xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f4xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f4xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED +#include "stm32f4xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f4xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f4xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f4xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f4xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f4xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f4xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f4xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_PCCARD_MODULE_ENABLED + #include "stm32f4xx_hal_pccard.h" +#endif /* HAL_PCCARD_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f4xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f4xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f4xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f4xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f4xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f4xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f4xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f4xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f4xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f4xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f4xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f4xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f4xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f4xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f4xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f4xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f4xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f4xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f4xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f4xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32f4xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f4xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f4xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_FMPI2C_MODULE_ENABLED + #include "stm32f4xx_hal_fmpi2c.h" +#endif /* HAL_FMPI2C_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32f4xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32f4xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f4xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_CONF_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Inc/stm32f4xx_it.h b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Inc/stm32f4xx_it.h new file mode 100644 index 0000000000000000000000000000000000000000..ab2ae38f21a0811ad501114abf56da43f39e6155 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Inc/stm32f4xx_it.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f4xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_IT_H +#define __STM32F4xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/main.c b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/main.c new file mode 100644 index 0000000000000000000000000000000000000000..b2659cd456ba2560e1876af4f0dfd878589b6463 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/main.c @@ -0,0 +1,708 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +ADC_HandleTypeDef hadc1; + +I2S_HandleTypeDef hi2s2; + +IWDG_HandleTypeDef hiwdg; + +RNG_HandleTypeDef hrng; + +RTC_HandleTypeDef hrtc; + +SD_HandleTypeDef hsd; + +SPI_HandleTypeDef hspi3; + +TIM_HandleTypeDef htim10; +TIM_HandleTypeDef htim11; +TIM_HandleTypeDef htim13; +TIM_HandleTypeDef htim14; + +UART_HandleTypeDef huart1; +UART_HandleTypeDef huart2; + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void MX_GPIO_Init(void); +static void MX_USART1_UART_Init(void); +static void MX_ADC1_Init(void); +static void MX_I2S2_Init(void); +static void MX_IWDG_Init(void); +static void MX_RTC_Init(void); +static void MX_SDIO_SD_Init(void); +static void MX_SPI3_Init(void); +static void MX_TIM10_Init(void); +static void MX_TIM11_Init(void); +static void MX_TIM13_Init(void); +static void MX_TIM14_Init(void); +static void MX_RNG_Init(void); +static void MX_USART2_UART_Init(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_USART1_UART_Init(); + MX_ADC1_Init(); + MX_I2S2_Init(); + MX_IWDG_Init(); + MX_RTC_Init(); + MX_SDIO_SD_Init(); + MX_SPI3_Init(); + MX_TIM10_Init(); + MX_TIM11_Init(); + MX_TIM13_Init(); + MX_TIM14_Init(); + MX_RNG_Init(); + MX_USART2_UART_Init(); + /* USER CODE BEGIN 2 */ + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE + |RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 25; + RCC_OscInitStruct.PLL.PLLN = 336; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 7; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) + { + Error_Handler(); + } + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2S|RCC_PERIPHCLK_RTC; + PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; + PeriphClkInitStruct.PLLI2S.PLLI2SR = 2; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } +} + +/** + * @brief ADC1 Initialization Function + * @param None + * @retval None + */ +static void MX_ADC1_Init(void) +{ + + /* USER CODE BEGIN ADC1_Init 0 */ + + /* USER CODE END ADC1_Init 0 */ + + ADC_ChannelConfTypeDef sConfig = {0}; + + /* USER CODE BEGIN ADC1_Init 1 */ + + /* USER CODE END ADC1_Init 1 */ + /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) + */ + hadc1.Instance = ADC1; + hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; + hadc1.Init.Resolution = ADC_RESOLUTION_12B; + hadc1.Init.ScanConvMode = DISABLE; + hadc1.Init.ContinuousConvMode = DISABLE; + hadc1.Init.DiscontinuousConvMode = DISABLE; + hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; + hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; + hadc1.Init.NbrOfConversion = 1; + hadc1.Init.DMAContinuousRequests = DISABLE; + hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; + if (HAL_ADC_Init(&hadc1) != HAL_OK) + { + Error_Handler(); + } + /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. + */ + sConfig.Channel = ADC_CHANNEL_9; + sConfig.Rank = 1; + sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; + if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN ADC1_Init 2 */ + + /* USER CODE END ADC1_Init 2 */ + +} + +/** + * @brief I2S2 Initialization Function + * @param None + * @retval None + */ +static void MX_I2S2_Init(void) +{ + + /* USER CODE BEGIN I2S2_Init 0 */ + + /* USER CODE END I2S2_Init 0 */ + + /* USER CODE BEGIN I2S2_Init 1 */ + + /* USER CODE END I2S2_Init 1 */ + hi2s2.Instance = SPI2; + hi2s2.Init.Mode = I2S_MODE_MASTER_TX; + hi2s2.Init.Standard = I2S_STANDARD_PHILIPS; + hi2s2.Init.DataFormat = I2S_DATAFORMAT_16B; + hi2s2.Init.MCLKOutput = I2S_MCLKOUTPUT_ENABLE; + hi2s2.Init.AudioFreq = I2S_AUDIOFREQ_8K; + hi2s2.Init.CPOL = I2S_CPOL_LOW; + hi2s2.Init.ClockSource = I2S_CLOCK_PLL; + hi2s2.Init.FullDuplexMode = I2S_FULLDUPLEXMODE_ENABLE; + if (HAL_I2S_Init(&hi2s2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN I2S2_Init 2 */ + + /* USER CODE END I2S2_Init 2 */ + +} + +/** + * @brief IWDG Initialization Function + * @param None + * @retval None + */ +static void MX_IWDG_Init(void) +{ + + /* USER CODE BEGIN IWDG_Init 0 */ + + /* USER CODE END IWDG_Init 0 */ + + /* USER CODE BEGIN IWDG_Init 1 */ + + /* USER CODE END IWDG_Init 1 */ + hiwdg.Instance = IWDG; + hiwdg.Init.Prescaler = IWDG_PRESCALER_4; + hiwdg.Init.Reload = 4095; + if (HAL_IWDG_Init(&hiwdg) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN IWDG_Init 2 */ + + /* USER CODE END IWDG_Init 2 */ + +} + +/** + * @brief RNG Initialization Function + * @param None + * @retval None + */ +static void MX_RNG_Init(void) +{ + + /* USER CODE BEGIN RNG_Init 0 */ + + /* USER CODE END RNG_Init 0 */ + + /* USER CODE BEGIN RNG_Init 1 */ + + /* USER CODE END RNG_Init 1 */ + hrng.Instance = RNG; + if (HAL_RNG_Init(&hrng) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN RNG_Init 2 */ + + /* USER CODE END RNG_Init 2 */ + +} + +/** + * @brief RTC Initialization Function + * @param None + * @retval None + */ +static void MX_RTC_Init(void) +{ + + /* USER CODE BEGIN RTC_Init 0 */ + + /* USER CODE END RTC_Init 0 */ + + /* USER CODE BEGIN RTC_Init 1 */ + + /* USER CODE END RTC_Init 1 */ + /** Initialize RTC Only + */ + hrtc.Instance = RTC; + hrtc.Init.HourFormat = RTC_HOURFORMAT_24; + hrtc.Init.AsynchPrediv = 127; + hrtc.Init.SynchPrediv = 255; + hrtc.Init.OutPut = RTC_OUTPUT_DISABLE; + hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; + hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; + if (HAL_RTC_Init(&hrtc) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN RTC_Init 2 */ + + /* USER CODE END RTC_Init 2 */ + +} + +/** + * @brief SDIO Initialization Function + * @param None + * @retval None + */ +static void MX_SDIO_SD_Init(void) +{ + + /* USER CODE BEGIN SDIO_Init 0 */ + + /* USER CODE END SDIO_Init 0 */ + + /* USER CODE BEGIN SDIO_Init 1 */ + + /* USER CODE END SDIO_Init 1 */ + hsd.Instance = SDIO; + hsd.Init.ClockEdge = SDIO_CLOCK_EDGE_RISING; + hsd.Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE; + hsd.Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE; + hsd.Init.BusWide = SDIO_BUS_WIDE_1B; + hsd.Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE; + hsd.Init.ClockDiv = 0; + if (HAL_SD_Init(&hsd) != HAL_OK) + { + Error_Handler(); + } + if (HAL_SD_ConfigWideBusOperation(&hsd, SDIO_BUS_WIDE_4B) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SDIO_Init 2 */ + + /* USER CODE END SDIO_Init 2 */ + +} + +/** + * @brief SPI3 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI3_Init(void) +{ + + /* USER CODE BEGIN SPI3_Init 0 */ + + /* USER CODE END SPI3_Init 0 */ + + /* USER CODE BEGIN SPI3_Init 1 */ + + /* USER CODE END SPI3_Init 1 */ + /* SPI3 parameter configuration*/ + hspi3.Instance = SPI3; + hspi3.Init.Mode = SPI_MODE_MASTER; + hspi3.Init.Direction = SPI_DIRECTION_2LINES; + hspi3.Init.DataSize = SPI_DATASIZE_8BIT; + hspi3.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi3.Init.CLKPhase = SPI_PHASE_1EDGE; + hspi3.Init.NSS = SPI_NSS_SOFT; + hspi3.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + hspi3.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi3.Init.TIMode = SPI_TIMODE_DISABLE; + hspi3.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi3.Init.CRCPolynomial = 10; + if (HAL_SPI_Init(&hspi3) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SPI3_Init 2 */ + + /* USER CODE END SPI3_Init 2 */ + +} + +/** + * @brief TIM10 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM10_Init(void) +{ + + /* USER CODE BEGIN TIM10_Init 0 */ + + /* USER CODE END TIM10_Init 0 */ + + TIM_OC_InitTypeDef sConfigOC = {0}; + + /* USER CODE BEGIN TIM10_Init 1 */ + + /* USER CODE END TIM10_Init 1 */ + htim10.Instance = TIM10; + htim10.Init.Prescaler = 0; + htim10.Init.CounterMode = TIM_COUNTERMODE_UP; + htim10.Init.Period = 0; + htim10.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim10.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim10) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIM_PWM_Init(&htim10) != HAL_OK) + { + Error_Handler(); + } + sConfigOC.OCMode = TIM_OCMODE_PWM1; + sConfigOC.Pulse = 0; + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + if (HAL_TIM_PWM_ConfigChannel(&htim10, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM10_Init 2 */ + + /* USER CODE END TIM10_Init 2 */ + HAL_TIM_MspPostInit(&htim10); + +} + +/** + * @brief TIM11 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM11_Init(void) +{ + + /* USER CODE BEGIN TIM11_Init 0 */ + + /* USER CODE END TIM11_Init 0 */ + + /* USER CODE BEGIN TIM11_Init 1 */ + + /* USER CODE END TIM11_Init 1 */ + htim11.Instance = TIM11; + htim11.Init.Prescaler = 0; + htim11.Init.CounterMode = TIM_COUNTERMODE_UP; + htim11.Init.Period = 0; + htim11.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim11.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim11) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM11_Init 2 */ + + /* USER CODE END TIM11_Init 2 */ + +} + +/** + * @brief TIM13 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM13_Init(void) +{ + + /* USER CODE BEGIN TIM13_Init 0 */ + + /* USER CODE END TIM13_Init 0 */ + + /* USER CODE BEGIN TIM13_Init 1 */ + + /* USER CODE END TIM13_Init 1 */ + htim13.Instance = TIM13; + htim13.Init.Prescaler = 0; + htim13.Init.CounterMode = TIM_COUNTERMODE_UP; + htim13.Init.Period = 0; + htim13.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim13.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim13) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM13_Init 2 */ + + /* USER CODE END TIM13_Init 2 */ + +} + +/** + * @brief TIM14 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM14_Init(void) +{ + + /* USER CODE BEGIN TIM14_Init 0 */ + + /* USER CODE END TIM14_Init 0 */ + + /* USER CODE BEGIN TIM14_Init 1 */ + + /* USER CODE END TIM14_Init 1 */ + htim14.Instance = TIM14; + htim14.Init.Prescaler = 0; + htim14.Init.CounterMode = TIM_COUNTERMODE_UP; + htim14.Init.Period = 0; + htim14.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim14.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim14) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM14_Init 2 */ + + /* USER CODE END TIM14_Init 2 */ + +} + +/** + * @brief USART1 Initialization Function + * @param None + * @retval None + */ +static void MX_USART1_UART_Init(void) +{ + + /* USER CODE BEGIN USART1_Init 0 */ + + /* USER CODE END USART1_Init 0 */ + + /* USER CODE BEGIN USART1_Init 1 */ + + /* USER CODE END USART1_Init 1 */ + huart1.Instance = USART1; + huart1.Init.BaudRate = 115200; + huart1.Init.WordLength = UART_WORDLENGTH_8B; + huart1.Init.StopBits = UART_STOPBITS_1; + huart1.Init.Parity = UART_PARITY_NONE; + huart1.Init.Mode = UART_MODE_TX_RX; + huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart1.Init.OverSampling = UART_OVERSAMPLING_16; + if (HAL_UART_Init(&huart1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART1_Init 2 */ + + /* USER CODE END USART1_Init 2 */ + +} + +/** + * @brief USART2 Initialization Function + * @param None + * @retval None + */ +static void MX_USART2_UART_Init(void) +{ + + /* USER CODE BEGIN USART2_Init 0 */ + + /* USER CODE END USART2_Init 0 */ + + /* USER CODE BEGIN USART2_Init 1 */ + + /* USER CODE END USART2_Init 1 */ + huart2.Instance = USART2; + huart2.Init.BaudRate = 115200; + huart2.Init.WordLength = UART_WORDLENGTH_8B; + huart2.Init.StopBits = UART_STOPBITS_1; + huart2.Init.Parity = UART_PARITY_NONE; + huart2.Init.Mode = UART_MODE_TX_RX; + huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart2.Init.OverSampling = UART_OVERSAMPLING_16; + if (HAL_UART_Init(&huart2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART2_Init 2 */ + + /* USER CODE END USART2_Init 2 */ + +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOI_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c new file mode 100644 index 0000000000000000000000000000000000000000..ab8078f4b0cbfd7d905860b1f97274c034d16bf9 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c @@ -0,0 +1,721 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * File Name : stm32f4xx_hal_msp.c + * Description : This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + /** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/** +* @brief ADC MSP Initialization +* This function configures the hardware resources used in this example +* @param hadc: ADC handle pointer +* @retval None +*/ +void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hadc->Instance==ADC1) + { + /* USER CODE BEGIN ADC1_MspInit 0 */ + + /* USER CODE END ADC1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_ADC1_CLK_ENABLE(); + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**ADC1 GPIO Configuration + PB1 ------> ADC1_IN9 + */ + GPIO_InitStruct.Pin = GPIO_PIN_1; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN ADC1_MspInit 1 */ + + /* USER CODE END ADC1_MspInit 1 */ + } + +} + +/** +* @brief ADC MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hadc: ADC handle pointer +* @retval None +*/ +void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) +{ + if(hadc->Instance==ADC1) + { + /* USER CODE BEGIN ADC1_MspDeInit 0 */ + + /* USER CODE END ADC1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_ADC1_CLK_DISABLE(); + + /**ADC1 GPIO Configuration + PB1 ------> ADC1_IN9 + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_1); + + /* USER CODE BEGIN ADC1_MspDeInit 1 */ + + /* USER CODE END ADC1_MspDeInit 1 */ + } + +} + +/** +* @brief I2S MSP Initialization +* This function configures the hardware resources used in this example +* @param hi2s: I2S handle pointer +* @retval None +*/ +void HAL_I2S_MspInit(I2S_HandleTypeDef* hi2s) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hi2s->Instance==SPI2) + { + /* USER CODE BEGIN SPI2_MspInit 0 */ + + /* USER CODE END SPI2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI2_CLK_ENABLE(); + + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOI_CLK_ENABLE(); + /**I2S2 GPIO Configuration + PB12 ------> I2S2_WS + PB13 ------> I2S2_CK + PB15 ------> I2S2_SD + PC6 ------> I2S2_MCK + PI2 ------> I2S2_ext_SD + */ + GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF6_I2S2ext; + HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI2_MspInit 1 */ + + /* USER CODE END SPI2_MspInit 1 */ + } + +} + +/** +* @brief I2S MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hi2s: I2S handle pointer +* @retval None +*/ +void HAL_I2S_MspDeInit(I2S_HandleTypeDef* hi2s) +{ + if(hi2s->Instance==SPI2) + { + /* USER CODE BEGIN SPI2_MspDeInit 0 */ + + /* USER CODE END SPI2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI2_CLK_DISABLE(); + + /**I2S2 GPIO Configuration + PB12 ------> I2S2_WS + PB13 ------> I2S2_CK + PB15 ------> I2S2_SD + PC6 ------> I2S2_MCK + PI2 ------> I2S2_ext_SD + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_15); + + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_6); + + HAL_GPIO_DeInit(GPIOI, GPIO_PIN_2); + + /* USER CODE BEGIN SPI2_MspDeInit 1 */ + + /* USER CODE END SPI2_MspDeInit 1 */ + } + +} + +/** +* @brief RNG MSP Initialization +* This function configures the hardware resources used in this example +* @param hrng: RNG handle pointer +* @retval None +*/ +void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng) +{ + if(hrng->Instance==RNG) + { + /* USER CODE BEGIN RNG_MspInit 0 */ + + /* USER CODE END RNG_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_RNG_CLK_ENABLE(); + /* USER CODE BEGIN RNG_MspInit 1 */ + + /* USER CODE END RNG_MspInit 1 */ + } + +} + +/** +* @brief RNG MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hrng: RNG handle pointer +* @retval None +*/ +void HAL_RNG_MspDeInit(RNG_HandleTypeDef* hrng) +{ + if(hrng->Instance==RNG) + { + /* USER CODE BEGIN RNG_MspDeInit 0 */ + + /* USER CODE END RNG_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_RNG_CLK_DISABLE(); + /* USER CODE BEGIN RNG_MspDeInit 1 */ + + /* USER CODE END RNG_MspDeInit 1 */ + } + +} + +/** +* @brief RTC MSP Initialization +* This function configures the hardware resources used in this example +* @param hrtc: RTC handle pointer +* @retval None +*/ +void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) +{ + if(hrtc->Instance==RTC) + { + /* USER CODE BEGIN RTC_MspInit 0 */ + + /* USER CODE END RTC_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_RTC_ENABLE(); + /* USER CODE BEGIN RTC_MspInit 1 */ + + /* USER CODE END RTC_MspInit 1 */ + } + +} + +/** +* @brief RTC MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hrtc: RTC handle pointer +* @retval None +*/ +void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) +{ + if(hrtc->Instance==RTC) + { + /* USER CODE BEGIN RTC_MspDeInit 0 */ + + /* USER CODE END RTC_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_RTC_DISABLE(); + /* USER CODE BEGIN RTC_MspDeInit 1 */ + + /* USER CODE END RTC_MspDeInit 1 */ + } + +} + +/** +* @brief SD MSP Initialization +* This function configures the hardware resources used in this example +* @param hsd: SD handle pointer +* @retval None +*/ +void HAL_SD_MspInit(SD_HandleTypeDef* hsd) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hsd->Instance==SDIO) + { + /* USER CODE BEGIN SDIO_MspInit 0 */ + + /* USER CODE END SDIO_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SDIO_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**SDIO GPIO Configuration + PC8 ------> SDIO_D0 + PC9 ------> SDIO_D1 + PC10 ------> SDIO_D2 + PC11 ------> SDIO_D3 + PC12 ------> SDIO_CK + PD2 ------> SDIO_CMD + */ + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + |GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_SDIO; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_SDIO; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* USER CODE BEGIN SDIO_MspInit 1 */ + + /* USER CODE END SDIO_MspInit 1 */ + } + +} + +/** +* @brief SD MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hsd: SD handle pointer +* @retval None +*/ +void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) +{ + if(hsd->Instance==SDIO) + { + /* USER CODE BEGIN SDIO_MspDeInit 0 */ + + /* USER CODE END SDIO_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SDIO_CLK_DISABLE(); + + /**SDIO GPIO Configuration + PC8 ------> SDIO_D0 + PC9 ------> SDIO_D1 + PC10 ------> SDIO_D2 + PC11 ------> SDIO_D3 + PC12 ------> SDIO_CK + PD2 ------> SDIO_CMD + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + |GPIO_PIN_12); + + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); + + /* USER CODE BEGIN SDIO_MspDeInit 1 */ + + /* USER CODE END SDIO_MspDeInit 1 */ + } + +} + +/** +* @brief SPI MSP Initialization +* This function configures the hardware resources used in this example +* @param hspi: SPI handle pointer +* @retval None +*/ +void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hspi->Instance==SPI3) + { + /* USER CODE BEGIN SPI3_MspInit 0 */ + + /* USER CODE END SPI3_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI3_CLK_ENABLE(); + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**SPI3 GPIO Configuration + PB3 ------> SPI3_SCK + PB4 ------> SPI3_MISO + PB5 ------> SPI3_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF6_SPI3; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI3_MspInit 1 */ + + /* USER CODE END SPI3_MspInit 1 */ + } + +} + +/** +* @brief SPI MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hspi: SPI handle pointer +* @retval None +*/ +void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) +{ + if(hspi->Instance==SPI3) + { + /* USER CODE BEGIN SPI3_MspDeInit 0 */ + + /* USER CODE END SPI3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI3_CLK_DISABLE(); + + /**SPI3 GPIO Configuration + PB3 ------> SPI3_SCK + PB4 ------> SPI3_MISO + PB5 ------> SPI3_MOSI + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5); + + /* USER CODE BEGIN SPI3_MspDeInit 1 */ + + /* USER CODE END SPI3_MspDeInit 1 */ + } + +} + +/** +* @brief TIM_Base MSP Initialization +* This function configures the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) +{ + if(htim_base->Instance==TIM10) + { + /* USER CODE BEGIN TIM10_MspInit 0 */ + + /* USER CODE END TIM10_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM10_CLK_ENABLE(); + /* USER CODE BEGIN TIM10_MspInit 1 */ + + /* USER CODE END TIM10_MspInit 1 */ + } + else if(htim_base->Instance==TIM11) + { + /* USER CODE BEGIN TIM11_MspInit 0 */ + + /* USER CODE END TIM11_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM11_CLK_ENABLE(); + /* USER CODE BEGIN TIM11_MspInit 1 */ + + /* USER CODE END TIM11_MspInit 1 */ + } + else if(htim_base->Instance==TIM13) + { + /* USER CODE BEGIN TIM13_MspInit 0 */ + + /* USER CODE END TIM13_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM13_CLK_ENABLE(); + /* USER CODE BEGIN TIM13_MspInit 1 */ + + /* USER CODE END TIM13_MspInit 1 */ + } + else if(htim_base->Instance==TIM14) + { + /* USER CODE BEGIN TIM14_MspInit 0 */ + + /* USER CODE END TIM14_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM14_CLK_ENABLE(); + /* USER CODE BEGIN TIM14_MspInit 1 */ + + /* USER CODE END TIM14_MspInit 1 */ + } + +} + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(htim->Instance==TIM10) + { + /* USER CODE BEGIN TIM10_MspPostInit 0 */ + + /* USER CODE END TIM10_MspPostInit 0 */ + + __HAL_RCC_GPIOF_CLK_ENABLE(); + /**TIM10 GPIO Configuration + PF6 ------> TIM10_CH1 + */ + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF3_TIM10; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM10_MspPostInit 1 */ + + /* USER CODE END TIM10_MspPostInit 1 */ + } + +} +/** +* @brief TIM_Base MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base) +{ + if(htim_base->Instance==TIM10) + { + /* USER CODE BEGIN TIM10_MspDeInit 0 */ + + /* USER CODE END TIM10_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM10_CLK_DISABLE(); + /* USER CODE BEGIN TIM10_MspDeInit 1 */ + + /* USER CODE END TIM10_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM11) + { + /* USER CODE BEGIN TIM11_MspDeInit 0 */ + + /* USER CODE END TIM11_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM11_CLK_DISABLE(); + /* USER CODE BEGIN TIM11_MspDeInit 1 */ + + /* USER CODE END TIM11_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM13) + { + /* USER CODE BEGIN TIM13_MspDeInit 0 */ + + /* USER CODE END TIM13_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM13_CLK_DISABLE(); + /* USER CODE BEGIN TIM13_MspDeInit 1 */ + + /* USER CODE END TIM13_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM14) + { + /* USER CODE BEGIN TIM14_MspDeInit 0 */ + + /* USER CODE END TIM14_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM14_CLK_DISABLE(); + /* USER CODE BEGIN TIM14_MspDeInit 1 */ + + /* USER CODE END TIM14_MspDeInit 1 */ + } + +} + +/** +* @brief UART MSP Initialization +* This function configures the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspInit(UART_HandleTypeDef* huart) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(huart->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspInit 0 */ + + /* USER CODE END USART1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USART1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USART1 GPIO Configuration + PA9 ------> USART1_TX + PA10 ------> USART1_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN USART1_MspInit 1 */ + + /* USER CODE END USART1_MspInit 1 */ + } + else if(huart->Instance==USART2) + { + /* USER CODE BEGIN USART2_MspInit 0 */ + + /* USER CODE END USART2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USART2_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USART2 GPIO Configuration + PA2 ------> USART2_TX + PA3 ------> USART2_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART2; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN USART2_MspInit 1 */ + + /* USER CODE END USART2_MspInit 1 */ + } + +} + +/** +* @brief UART MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) +{ + if(huart->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspDeInit 0 */ + + /* USER CODE END USART1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART1_CLK_DISABLE(); + + /**USART1 GPIO Configuration + PA9 ------> USART1_TX + PA10 ------> USART1_RX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); + + /* USER CODE BEGIN USART1_MspDeInit 1 */ + + /* USER CODE END USART1_MspDeInit 1 */ + } + else if(huart->Instance==USART2) + { + /* USER CODE BEGIN USART2_MspDeInit 0 */ + + /* USER CODE END USART2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART2_CLK_DISABLE(); + + /**USART2 GPIO Configuration + PA2 ------> USART2_TX + PA3 ------> USART2_RX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); + + /* USER CODE BEGIN USART2_MspDeInit 1 */ + + /* USER CODE END USART2_MspDeInit 1 */ + } + +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/stm32f4xx_it.c b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/stm32f4xx_it.c new file mode 100644 index 0000000000000000000000000000000000000000..84413fb5f259a2d7ed1efb49d1481173585c4178 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/stm32f4xx_it.c @@ -0,0 +1,203 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f4xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32f4xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ + +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M4 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn 0 */ + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32F4xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32f4xx.s). */ +/******************************************************************************/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/system_stm32f4xx.c b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/system_stm32f4xx.c new file mode 100644 index 0000000000000000000000000000000000000000..bcb2b9f4a52761260c65cfebc3184691156ee6ce --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/system_stm32f4xx.c @@ -0,0 +1,727 @@ +/** + ****************************************************************************** + * @file system_stm32f4xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx_system + * @{ + */ + +/** @addtogroup STM32F4xx_System_Private_Includes + * @{ + */ + + +#include "stm32f4xx.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ + || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) +/* #define DATA_IN_ExtSRAM */ +#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\ + STM32F412Zx || STM32F412Vx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +/* #define DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ + STM32F479xx */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = 16000000; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes + * @{ + */ + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting, vector table location and External memory + * configuration. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value + * depends on the application requirements), user has to ensure that HSE_VALUE + * is same as the real frequency of the crystal used. Otherwise, this function + * may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmp = 0x00; + + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register __IO uint32_t index; + + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ + RCC->AHB1ENR |= 0x000001F8; + + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; + +/*-- FMC Configuration -------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + FMC_Bank5_6->SDCR[0] = 0x000019E4; + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ + FMC_Bank5_6->SDCMR = 0x00000073; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ + FMC_Bank5_6->SDCMR = 0x00046014; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001091; + FMC_Bank1->BTCR[3] = 0x00110212; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F469xx || STM32F479xx */ + + (void)(tmp); +} +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmp = 0x00; +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#if defined (DATA_IN_ExtSDRAM) + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register __IO uint32_t index; + +#if defined(STM32F446xx) + /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface + clock */ + RCC->AHB1ENR |= 0x0000007D; +#else + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface + clock */ + RCC->AHB1ENR |= 0x000001F8; +#endif /* STM32F446xx */ + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); + +#if defined(STM32F446xx) + /* Connect PAx pins to FMC Alternate function */ + GPIOA->AFR[0] |= 0xC0000000; + GPIOA->AFR[1] |= 0x00000000; + /* Configure PDx pins in Alternate function mode */ + GPIOA->MODER |= 0x00008000; + /* Configure PDx pins speed to 50 MHz */ + GPIOA->OSPEEDR |= 0x00008000; + /* Configure PDx pins Output type to push-pull */ + GPIOA->OTYPER |= 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOA->PUPDR |= 0x00000000; + + /* Connect PCx pins to FMC Alternate function */ + GPIOC->AFR[0] |= 0x00CC0000; + GPIOC->AFR[1] |= 0x00000000; + /* Configure PDx pins in Alternate function mode */ + GPIOC->MODER |= 0x00000A00; + /* Configure PDx pins speed to 50 MHz */ + GPIOC->OSPEEDR |= 0x00000A00; + /* Configure PDx pins Output type to push-pull */ + GPIOC->OTYPER |= 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOC->PUPDR |= 0x00000000; +#endif /* STM32F446xx */ + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x000000CC; + GPIOD->AFR[1] = 0xCC000CCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xA02A000A; + /* Configure PDx pins speed to 50 MHz */ + GPIOD->OSPEEDR = 0xA02A000A; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00000CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA800A; + /* Configure PEx pins speed to 50 MHz */ + GPIOE->OSPEEDR = 0xAAAA800A; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +/*-- FMC Configuration -------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* Configure and enable SDRAM bank1 */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCR[0] = 0x00001954; +#else + FMC_Bank5_6->SDCR[0] = 0x000019E4; +#endif /* STM32F446xx */ + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCMR = 0x000000F3; +#else + FMC_Bank5_6->SDCMR = 0x00000073; +#endif /* STM32F446xx */ + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCMR = 0x00044014; +#else + FMC_Bank5_6->SDCMR = 0x00046014; +#endif /* STM32F446xx */ + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; +#if defined(STM32F446xx) + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1)); +#else + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); +#endif /* STM32F446xx */ + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); +#endif /* DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ + || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) + +#if defined(DATA_IN_ExtSRAM) +/*-- GPIOs Configuration -----------------------------------------------------*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR |= 0x00000078; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCC0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA000AAA; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xFF000FFF; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0x00CCCCCC; + GPIOG->AFR[1] = 0x000000C0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00085AAA; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000CAFFF; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FMC/FSMC Configuration --------------------------------------------------*/ + /* Enable the FMC/FSMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001091; + FMC_Bank1->BTCR[3] = 0x00110212; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F469xx || STM32F479xx */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\ + || defined(STM32F412Zx) || defined(STM32F412Vx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN); + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001011; + FSMC_Bank1->BTCR[3] = 0x00000201; + FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */ + +#endif /* DATA_IN_ExtSRAM */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ + STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */ + (void)(tmp); +} +#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f407-armfly-v5/board/Kconfig b/bsp/stm32/stm32f407-armfly-v5/board/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..7c6b8a97f0e697a2f73b9d2ed962d1da99140631 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/Kconfig @@ -0,0 +1,199 @@ +menu "Hardware Drivers Config" + +config SOC_STM32F407IG + bool + select SOC_SERIES_STM32F4 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "Onboard Peripheral Drivers" + + config BSP_USING_RS232_TO_USART + bool "Enable RS232 TO USART (uart1)" + select BSP_USING_UART + select BSP_USING_UART1 + default y + + config BSP_USING_SPI_FLASH + bool "Enable SPI FLASH (W25Q64 spi3)" + select BSP_USING_SPI + select BSP_USING_SPI3 + select RT_USING_SFUD + select RT_SFUD_USING_SFDP + default n + + config BSP_USING_SDCARD + bool "Enable SDCARD (sdio)" + select BSP_USING_SDIO + select RT_USING_DFS + select RT_USING_DFS_ELMFAT + default n + + config BSP_USING_MPU6050 + bool "Enable MPU6050(i2c2)" + select BSP_USING_I2C2 + select PKG_USING_SENSORS_DRIVERS + select PKG_USING_MPU6XXX + select PKG_USING_MPU6XXX_SAMPLE + select PKG_USING_MPU6XXX_LATEST_VERSION + default n + +endmenu + +menu "On-chip Peripheral Drivers" + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default y + + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART2 + bool "Enable UART2" + default y + + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + endif + + config BSP_USING_ON_CHIP_FLASH + bool "Enable on-chip FLASH" + default n + + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI3 + bool "Enable SPI3 BUS" + default n + + config BSP_SPI3_TX_USING_DMA + bool "Enable SPI3 TX DMA" + depends on BSP_USING_SPI3 + default n + + config BSP_SPI3_RX_USING_DMA + bool "Enable SPI3 RX DMA" + depends on BSP_USING_SPI3 + select BSP_SPI3_TX_USING_DMA + default n + endif + + menuconfig BSP_USING_I2C2 + bool "Enable I2C2 BUS (software simulation)" + default n + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C2 + comment "Notice: PH4 --> 116; PH5 --> 117" + config BSP_I2C2_SCL_PIN + int "i2c2 scl pin number" + range 1 143 + default 116 + config BSP_I2C2_SDA_PIN + int "I2C2 sda pin number" + range 1 143 + default 117 + endif + + menuconfig BSP_USING_TIM + bool "Enable timer" + default n + select RT_USING_HWTIMER + if BSP_USING_TIM + config BSP_USING_TIM11 + bool "Enable TIM11" + default n + + config BSP_USING_TIM13 + bool "Enable TIM13" + default n + + config BSP_USING_TIM14 + bool "Enable TIM14" + default n + endif + + menuconfig BSP_USING_PWM + bool "Enable pwm" + default n + select RT_USING_PWM + if BSP_USING_PWM + menuconfig BSP_USING_PWM10 + bool "Enable timer10 output pwm" + default n + if BSP_USING_PWM10 + config BSP_USING_PWM10_CH1 + bool "Enable PWM10 channel1" + default n + endif + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + endif + + menuconfig BSP_USING_ONCHIP_RTC + bool "Enable RTC" + select RT_USING_RTC + select RT_USING_LIBC + default n + if BSP_USING_ONCHIP_RTC + choice + prompt "Select clock source" + default BSP_RTC_USING_LSE + + config BSP_RTC_USING_LSE + bool "RTC USING LSE" + + config BSP_RTC_USING_LSI + bool "RTC USING LSI" + endchoice + endif + + config BSP_USING_WDT + bool "Enable Watchdog Timer" + select RT_USING_WDT + default n + + config BSP_USING_SDIO + bool "Enable SDIO" + select RT_USING_SDIO + select RT_USING_DFS + default n + + source "../libraries/HAL_Drivers/Kconfig" + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/stm32/stm32f407-armfly-v5/board/SConscript b/bsp/stm32/stm32f407-armfly-v5/board/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..2528db7ceee68ce892732aa5f58bc80bb6aa1091 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/SConscript @@ -0,0 +1,44 @@ +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() + +# add general drivers +src = Split(''' +board.c +CubeMX_Config/Src/stm32f4xx_hal_msp.c +''') + +if GetDepend(['BSP_USING_SPI_FLASH']): + src += Glob('ports/spi_flash_init.c') + +if GetDepend(['BSP_USING_SDCARD']): + src += Glob('ports/sdcard_port.c') + +path = [cwd] +path += [cwd + '/CubeMX_Config/Inc'] +path += [cwd + '/ports'] + +startup_path_prefix = SDK_LIB + +if rtconfig.CROSS_TOOL == 'gcc': + src += [startup_path_prefix + '/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s'] +elif rtconfig.CROSS_TOOL == 'keil': + src += [startup_path_prefix + '/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f407xx.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src += [startup_path_prefix + '/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f407xx.s'] + +# STM32F405xx) || STM32F415xx) || STM32F407xx) || STM32F417xx) +# STM32F427xx) || STM32F437xx) || STM32F429xx) || STM32F439xx) +# STM32F401xC) || STM32F401xE) || STM32F410Tx) || STM32F410Cx) +# STM32F410Rx) || STM32F411xE) || STM32F446xx) || STM32F469xx) +# STM32F479xx) || STM32F412Cx) || STM32F412Rx) || STM32F412Vx) +# STM32F412Zx) || STM32F413xx) || STM32F423xx) +# You can select chips from the list above +CPPDEFINES = ['STM32F407xx'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/stm32/stm32f407-armfly-v5/board/board.c b/bsp/stm32/stm32f407-armfly-v5/board/board.c new file mode 100644 index 0000000000000000000000000000000000000000..e64882e5e165a038c8a73c193392ea307e7f9e9e --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/board.c @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-13 Dozingfiretruck first version + */ + +#include "board.h" + +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE + |RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 25; + RCC_OscInitStruct.PLL.PLLN = 336; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 7; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) + { + Error_Handler(); + } + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2S|RCC_PERIPHCLK_RTC; + PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; + PeriphClkInitStruct.PLLI2S.PLLI2SR = 2; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } +} diff --git a/bsp/stm32/stm32f407-armfly-v5/board/board.h b/bsp/stm32/stm32f407-armfly-v5/board/board.h new file mode 100644 index 0000000000000000000000000000000000000000..68016d18bdaa6bab7bdf82ab14d659d3ee9ab655 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/board.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-13 Dozingfiretruck first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include +#include "drv_common.h" +#include "drv_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000) +#define STM32_FLASH_SIZE (1024 * 1024) +#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE)) + +#define STM32_SRAM_SIZE 128 +#define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) + +#if defined(__CC_ARM) || defined(__CLANG_ARM) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="CSTACK" +#define HEAP_BEGIN (__segment_end("CSTACK")) +#else +extern int __bss_end; +#define HEAP_BEGIN (&__bss_end) +#endif + +#define HEAP_END STM32_SRAM_END + +void SystemClock_Config(void); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/bsp/stm32/stm32f407-armfly-v5/board/linker_scripts/link.icf b/bsp/stm32/stm32f407-armfly-v5/board/linker_scripts/link.icf new file mode 100644 index 0000000000000000000000000000000000000000..067691151fc3f4882a9e276ee7ec08ada97a9e3d --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/linker_scripts/link.icf @@ -0,0 +1,28 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x0400; +define symbol __ICFEDIT_size_heap__ = 0x0000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/stm32/stm32f407-armfly-v5/board/linker_scripts/link.lds b/bsp/stm32/stm32f407-armfly-v5/board/linker_scripts/link.lds new file mode 100644 index 0000000000000000000000000000000000000000..00a1f08cf1e217e24a3a0ea65fb5f275f4bb183c --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/linker_scripts/link.lds @@ -0,0 +1,157 @@ +/* + * linker script for STM32F4xx with GNU ld + * bernard.xiong 2009-10-14 + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + ROM (rx) : ORIGIN = 0x08000000, LENGTH = 1024k /* 1024KB flash */ + RAM (rw) : ORIGIN = 0x20000000, LENGTH = 128k /* 128KB sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x200; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + + _etext = .; + } > ROM = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > ROM + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >RAM + + .stack : + { + . = ALIGN(4); + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >RAM + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > RAM + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/stm32/stm32f407-armfly-v5/board/linker_scripts/link.sct b/bsp/stm32/stm32f407-armfly-v5/board/linker_scripts/link.sct new file mode 100644 index 0000000000000000000000000000000000000000..0d7c47992d534c7779fea3df8bb47bb75c11bbc7 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/linker_scripts/link.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00100000 { ; load region size_region + ER_IROM1 0x08000000 0x00100000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00020000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/stm32/stm32f407-armfly-v5/board/ports/fal_cfg.h b/bsp/stm32/stm32f407-armfly-v5/board/ports/fal_cfg.h new file mode 100644 index 0000000000000000000000000000000000000000..20bcf9e11a3ff27c02b8b80ee398fbae44530898 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/ports/fal_cfg.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-13 Dozingfiretruck first version + */ + +#ifndef _FAL_CFG_H_ +#define _FAL_CFG_H_ + +#include +#include + +#define FLASH_SIZE_GRANULARITY_16K (4 * 16 * 1024) +#define FLASH_SIZE_GRANULARITY_64K (64 * 1024) +#define FLASH_SIZE_GRANULARITY_128K (7 * 128 * 1024) + +#define STM32_FLASH_START_ADRESS_16K STM32_FLASH_START_ADRESS +#define STM32_FLASH_START_ADRESS_64K (STM32_FLASH_START_ADRESS_16K + FLASH_SIZE_GRANULARITY_16K) +#define STM32_FLASH_START_ADRESS_128K (STM32_FLASH_START_ADRESS_64K + FLASH_SIZE_GRANULARITY_64K) + +extern const struct fal_flash_dev stm32_onchip_flash_16k; +extern const struct fal_flash_dev stm32_onchip_flash_64k; +extern const struct fal_flash_dev stm32_onchip_flash_128k; + +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ +{ \ + &stm32_onchip_flash_16k, \ + &stm32_onchip_flash_64k, \ + &stm32_onchip_flash_128k, \ +} +/* ====================== Partition Configuration ========================== */ +#ifdef FAL_PART_HAS_TABLE_CFG + +/* partition table */ +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WROD, "bootloader", "onchip_flash_16k", 0 , FLASH_SIZE_GRANULARITY_16K , 0}, \ + {FAL_PART_MAGIC_WROD, "param", "onchip_flash_64k", 0 , FLASH_SIZE_GRANULARITY_64K , 0}, \ + {FAL_PART_MAGIC_WROD, "app", "onchip_flash_128k", 0 , FLASH_SIZE_GRANULARITY_128K, 0}, \ +} + +#endif /* FAL_PART_HAS_TABLE_CFG */ +#endif /* _FAL_CFG_H_ */ diff --git a/bsp/stm32/stm32f407-armfly-v5/board/ports/sdcard_port.c b/bsp/stm32/stm32f407-armfly-v5/board/ports/sdcard_port.c new file mode 100644 index 0000000000000000000000000000000000000000..5eead223c3ef88f6273d6a020dc50d461c4848d0 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/ports/sdcard_port.c @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-13 Dozingfiretruck first version + */ + +#include + +#ifdef BSP_USING_SDCARD + +#include +#include +#include + +#define DBG_TAG "app.card" +#define DBG_LVL DBG_INFO +#include + +void sd_mount(void *parameter) +{ + while (1) + { + rt_thread_mdelay(500); + if(rt_device_find("sd0") != RT_NULL) + { + if (dfs_mount("sd0", "/", "elm", 0, 0) == RT_EOK) + { + LOG_I("sd card mount to '/'"); + break; + } + else + { + LOG_W("sd card mount to '/' failed!"); + } + } + } +} + +int stm32_sdcard_mount(void) +{ + rt_thread_t tid; + + tid = rt_thread_create("sd_mount", sd_mount, RT_NULL, + 1024, RT_THREAD_PRIORITY_MAX - 2, 20); + if (tid != RT_NULL) + { + rt_thread_startup(tid); + } + else + { + LOG_E("create sd_mount thread err!"); + } + return RT_EOK; +} +INIT_APP_EXPORT(stm32_sdcard_mount); + +#endif /* BSP_USING_SDCARD */ + diff --git a/bsp/stm32/stm32f407-armfly-v5/board/ports/spi_flash_init.c b/bsp/stm32/stm32f407-armfly-v5/board/ports/spi_flash_init.c new file mode 100644 index 0000000000000000000000000000000000000000..9aa8f95c136b833c2729070bb663766c97813fc3 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/ports/spi_flash_init.c @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-13 Dozingfiretruck first version + */ + +#include +#include "spi_flash.h" +#include "spi_flash_sfud.h" +#include "drv_spi.h" + +#if defined(BSP_USING_SPI_FLASH) +static int rt_hw_spi_flash_init(void) +{ + __HAL_RCC_GPIOF_CLK_ENABLE(); + rt_hw_spi_device_attach("spi3", "spi30", GPIOF, GPIO_PIN_8); + + if (RT_NULL == rt_sfud_flash_probe("W25Q64", "spi30")) + { + return -RT_ERROR; + }; + + return RT_EOK; +} +INIT_COMPONENT_EXPORT(rt_hw_spi_flash_init); +#endif + diff --git a/bsp/stm32/stm32f407-armfly-v5/figures/board.png b/bsp/stm32/stm32f407-armfly-v5/figures/board.png new file mode 100644 index 0000000000000000000000000000000000000000..94de91c01206c957bbc2607b86579fb7d1508a41 Binary files /dev/null and b/bsp/stm32/stm32f407-armfly-v5/figures/board.png differ diff --git a/bsp/stm32/stm32f407-armfly-v5/project.ewd b/bsp/stm32/stm32f407-armfly-v5/project.ewd new file mode 100644 index 0000000000000000000000000000000000000000..e94c83ed06b9e53d88b513c0a40c0bc99c7bcb8b --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/project.ewd @@ -0,0 +1,2834 @@ + + + 3 + + rt-thread + + ARM + + 1 + + C-SPY + 2 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
+ + + rt-thread + 0x4 + ARM-ADS + + + STM32F407ZG + STMicroelectronics + IRAM(0x20000000-0x2001FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) CPUTYPE("Cortex-M4") FPU2 + + "Startup\ST\STM32F4xx\startup_stm32f40_41xxx.s" ("STM32F40/41xxx Startup Code") + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000) + 6105 + stm32f4xx.h + + + + + + + -DSTM32F40_41xxx + + + SFD\ST\STM32F4xx\STM32F40x.sfr + 0 + 0 + + + + ST\STM32F4xx\ + ST\STM32F4xx\ + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU -REMAP + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 0 + + 0 + 6 + + + + + + + + + + + + + + Segger\JL2CM3.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 1 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + + + USE_HAL_DRIVER, STM32F407xx + + applications;.;board;board\CubeMX_Config\Inc;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\include;..\..\..\libcpu\arm\cortex-m4;..\..\..\libcpu\arm\common;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Inc;..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Include;..\libraries\STM32F4xx_HAL\CMSIS\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + Drivers + + + board.c + 1 + board\board.c + + + + + stm32f4xx_hal_msp.c + 1 + board\CubeMX_Config\Src\stm32f4xx_hal_msp.c + + + + + startup_stm32f407xx.s + 2 + ..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\arm\startup_stm32f407xx.s + + + + + drv_gpio.c + 1 + ..\libraries\HAL_Drivers\drv_gpio.c + + + + + drv_usart.c + 1 + ..\libraries\HAL_Drivers\drv_usart.c + + + + + drv_common.c + 1 + ..\libraries\HAL_Drivers\drv_common.c + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + + + components.c + 1 + ..\..\..\src\components.c + + + + + device.c + 1 + ..\..\..\src\device.c + + + + + idle.c + 1 + ..\..\..\src\idle.c + + + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + + + irq.c + 1 + ..\..\..\src\irq.c + + + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + + + mem.c + 1 + ..\..\..\src\mem.c + + + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + + + object.c + 1 + ..\..\..\src\object.c + + + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + + + signal.c + 1 + ..\..\..\src\signal.c + + + + + thread.c + 1 + ..\..\..\src\thread.c + + + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + CORTEX-M4 + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m4\cpuport.c + + + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m4\context_rvds.S + + + + + backtrace.c + 1 + ..\..\..\libcpu\arm\common\backtrace.c + + + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + + + DeviceDrivers + + + pin.c + 1 + ..\..\..\components\drivers\misc\pin.c + + + + + serial.c + 1 + ..\..\..\components\drivers\serial\serial.c + + + + + completion.c + 1 + ..\..\..\components\drivers\src\completion.c + + + + + dataqueue.c + 1 + ..\..\..\components\drivers\src\dataqueue.c + + + + + pipe.c + 1 + ..\..\..\components\drivers\src\pipe.c + + + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\src\ringblk_buf.c + + + + + ringbuffer.c + 1 + ..\..\..\components\drivers\src\ringbuffer.c + + + + + waitqueue.c + 1 + ..\..\..\components\drivers\src\waitqueue.c + + + + + workqueue.c + 1 + ..\..\..\components\drivers\src\workqueue.c + + + + + finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + + + symbol.c + 1 + ..\..\..\components\finsh\symbol.c + + + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + + + msh_cmd.c + 1 + ..\..\..\components\finsh\msh_cmd.c + + + + + msh_file.c + 1 + ..\..\..\components\finsh\msh_file.c + + + + + STM32_HAL + + + system_stm32f4xx.c + 1 + ..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c + + + + + stm32f4xx_hal.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c + + + + + stm32f4xx_hal_adc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc.c + + + + + stm32f4xx_hal_adc_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc_ex.c + + + + + stm32f4xx_hal_can.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_can.c + + + + + stm32f4xx_hal_cec.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cec.c + + + + + stm32f4xx_hal_cortex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c + + + + + stm32f4xx_hal_crc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_crc.c + + + + + stm32f4xx_hal_cryp.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp.c + + + + + stm32f4xx_hal_cryp_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp_ex.c + + + + + stm32f4xx_hal_dac.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dac.c + + + + + stm32f4xx_hal_dac_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dac_ex.c + + + + + stm32f4xx_hal_dcmi.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dcmi.c + + + + + stm32f4xx_hal_dcmi_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dcmi_ex.c + + + + + stm32f4xx_hal_dfsdm.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dfsdm.c + + + + + stm32f4xx_hal_dma.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c + + + + + stm32f4xx_hal_dma2d.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma2d.c + + + + + stm32f4xx_hal_dma_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c + + + + + stm32f4xx_hal_dsi.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dsi.c + + + + + stm32f4xx_hal_eth.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_eth.c + + + + + stm32f4xx_hal_flash.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c + + + + + stm32f4xx_hal_flash_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c + + + + + stm32f4xx_hal_flash_ramfunc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c + + + + + stm32f4xx_hal_fmpi2c.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_fmpi2c.c + + + + + stm32f4xx_hal_fmpi2c_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_fmpi2c_ex.c + + + + + stm32f4xx_hal_gpio.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c + + + + + stm32f4xx_hal_hash.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_hash.c + + + + + stm32f4xx_hal_hash_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_hash_ex.c + + + + + stm32f4xx_hal_hcd.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_hcd.c + + + + + stm32f4xx_hal_i2c.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c.c + + + + + stm32f4xx_hal_i2c_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c_ex.c + + + + + stm32f4xx_hal_i2s.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2s.c + + + + + stm32f4xx_hal_i2s_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2s_ex.c + + + + + stm32f4xx_hal_irda.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_irda.c + + + + + stm32f4xx_hal_iwdg.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_iwdg.c + + + + + stm32f4xx_hal_lptim.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_lptim.c + + + + + stm32f4xx_hal_ltdc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_ltdc.c + + + + + stm32f4xx_hal_ltdc_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_ltdc_ex.c + + + + + stm32f4xx_hal_nand.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_nand.c + + + + + stm32f4xx_hal_nor.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_nor.c + + + + + stm32f4xx_hal_pccard.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pccard.c + + + + + stm32f4xx_hal_pcd.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pcd.c + + + + + stm32f4xx_hal_pcd_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pcd_ex.c + + + + + stm32f4xx_hal_pwr.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c + + + + + stm32f4xx_hal_pwr_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c + + + + + stm32f4xx_hal_qspi.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_qspi.c + + + + + stm32f4xx_hal_rcc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c + + + + + stm32f4xx_hal_rcc_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c + + + + + stm32f4xx_hal_rng.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rng.c + + + + + stm32f4xx_hal_rtc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rtc.c + + + + + stm32f4xx_hal_rtc_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rtc_ex.c + + + + + stm32f4xx_hal_sai.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sai.c + + + + + stm32f4xx_hal_sai_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sai_ex.c + + + + + stm32f4xx_hal_sd.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sd.c + + + + + stm32f4xx_hal_sdram.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sdram.c + + + + + stm32f4xx_hal_smartcard.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_smartcard.c + + + + + stm32f4xx_hal_spdifrx.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spdifrx.c + + + + + stm32f4xx_hal_spi.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spi.c + + + + + stm32f4xx_hal_sram.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sram.c + + + + + stm32f4xx_hal_tim.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c + + + + + stm32f4xx_hal_tim_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c + + + + + stm32f4xx_hal_uart.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c + + + + + stm32f4xx_hal_usart.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_usart.c + + + + + stm32f4xx_hal_wwdg.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_wwdg.c + + + + + stm32f4xx_ll_fmc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fmc.c + + + + + stm32f4xx_ll_fsmc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fsmc.c + + + + + stm32f4xx_ll_sdmmc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_sdmmc.c + + + + + stm32f4xx_ll_usb.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_usb.c + + + + + + + diff --git a/bsp/stm32/stm32f407-armfly-v5/project.uvprojx b/bsp/stm32/stm32f407-armfly-v5/project.uvprojx new file mode 100644 index 0000000000000000000000000000000000000000..793a467224697ef98f1413a21879418331b00a43 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/project.uvprojx @@ -0,0 +1,753 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + STM32F407IGTx + STMicroelectronics + Keil.STM32F4xx_DFP.2.14.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IRAM2(0x10000000,0x00010000) IROM(0x08000000,0x00100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407IGTx$CMSIS\Flash\STM32F4xx_1024.FLM)) + 0 + $$Device:STM32F407IGTx$Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h + + + + + + + + + + $$Device:STM32F407IGTx$CMSIS\SVD\STM32F40x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4101 + + 1 + STLink\ST-LINKIII-KEIL_SWO.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + USE_HAL_DRIVER, STM32F407xx + + .;..\..\..\include;applications;.;board;board\CubeMX_Config\Inc;board\ports;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\common;..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Inc;..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Include;..\libraries\STM32F4xx_HAL\CMSIS\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + components.c + 1 + ..\..\..\src\components.c + + + device.c + 1 + ..\..\..\src\device.c + + + idle.c + 1 + ..\..\..\src\idle.c + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + irq.c + 1 + ..\..\..\src\irq.c + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + mem.c + 1 + ..\..\..\src\mem.c + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + object.c + 1 + ..\..\..\src\object.c + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + signal.c + 1 + ..\..\..\src\signal.c + + + thread.c + 1 + ..\..\..\src\thread.c + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + Drivers + + + board.c + 1 + board\board.c + + + stm32f4xx_hal_msp.c + 1 + board\CubeMX_Config\Src\stm32f4xx_hal_msp.c + + + startup_stm32f407xx.s + 2 + ..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\arm\startup_stm32f407xx.s + + + drv_gpio.c + 1 + ..\libraries\HAL_Drivers\drv_gpio.c + + + drv_usart.c + 1 + ..\libraries\HAL_Drivers\drv_usart.c + + + drv_hwtimer.c + 1 + ..\libraries\HAL_Drivers\drv_hwtimer.c + + + drv_common.c + 1 + ..\libraries\HAL_Drivers\drv_common.c + + + + + cpu + + + backtrace.c + 1 + ..\..\..\libcpu\arm\common\backtrace.c + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m4\cpuport.c + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m4\context_rvds.S + + + + + DeviceDrivers + + + hwtimer.c + 1 + ..\..\..\components\drivers\hwtimer\hwtimer.c + + + pin.c + 1 + ..\..\..\components\drivers\misc\pin.c + + + serial.c + 1 + ..\..\..\components\drivers\serial\serial.c + + + completion.c + 1 + ..\..\..\components\drivers\src\completion.c + + + dataqueue.c + 1 + ..\..\..\components\drivers\src\dataqueue.c + + + pipe.c + 1 + ..\..\..\components\drivers\src\pipe.c + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\src\ringblk_buf.c + + + ringbuffer.c + 1 + ..\..\..\components\drivers\src\ringbuffer.c + + + waitqueue.c + 1 + ..\..\..\components\drivers\src\waitqueue.c + + + workqueue.c + 1 + ..\..\..\components\drivers\src\workqueue.c + + + + + finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + + + libc + + + time.c + 1 + ..\..\..\components\libc\compilers\common\time.c + + + + + STM32_HAL + + + system_stm32f4xx.c + 1 + ..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c + + + stm32f4xx_hal.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c + + + stm32f4xx_hal_cec.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cec.c + + + stm32f4xx_hal_cortex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c + + + stm32f4xx_hal_crc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_crc.c + + + stm32f4xx_hal_cryp.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp.c + + + stm32f4xx_hal_cryp_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp_ex.c + + + stm32f4xx_hal_dma.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c + + + stm32f4xx_hal_dma_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c + + + stm32f4xx_hal_pwr.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c + + + stm32f4xx_hal_pwr_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c + + + stm32f4xx_hal_rcc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c + + + stm32f4xx_hal_rcc_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c + + + stm32f4xx_hal_rng.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rng.c + + + stm32f4xx_hal_gpio.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c + + + stm32f4xx_hal_uart.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c + + + stm32f4xx_hal_usart.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_usart.c + + + stm32f4xx_hal_tim.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c + + + stm32f4xx_hal_tim_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c + + + stm32f4xx_hal_lptim.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_lptim.c + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/bsp/stm32/stm32f407-armfly-v5/rtconfig.h b/bsp/stm32/stm32f407-armfly-v5/rtconfig.h new file mode 100644 index 0000000000000000000000000000000000000000..7d83eb4f99373b1c92420a4f79e319fd6bf83ad4 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/rtconfig.h @@ -0,0 +1,173 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_DEBUG +#define RT_DEBUG_COLOR + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x40000 +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M4 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_USING_MSH_ONLY +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA +#define RT_USING_PIN + +/* Using WiFi */ + + +/* Using USB */ + + +/* POSIX layer and C standard library */ + + +/* Network */ + +/* Socket abstraction layer */ + + +/* light weight TCP/IP stack */ + + +/* Modbus master and slave stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* ARM CMSIS */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + +#define SOC_FAMILY_STM32 +#define SOC_SERIES_STM32F4 + +/* Hardware Drivers Config */ + +#define SOC_STM32F407ZG + +/* Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART1 + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/stm32/stm32f407-armfly-v5/rtconfig.py b/bsp/stm32/stm32f407-armfly-v5/rtconfig.py new file mode 100644 index 0000000000000000000000000000000000000000..00d5d737ac1b346b991261caac738aa499b07576 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/rtconfig.py @@ -0,0 +1,150 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/stm32/stm32f407-armfly-v5/template.ewp b/bsp/stm32/stm32f407-armfly-v5/template.ewp new file mode 100644 index 0000000000000000000000000000000000000000..21c66ca0d01a9ff53039e46222e39e65e6fce1e5 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/template.ewp @@ -0,0 +1,2031 @@ + + + 3 + + rt-thread + + ARM + + 1 + + General + 3 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 20 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 20 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + diff --git a/bsp/stm32/stm32f407-armfly-v5/template.eww b/bsp/stm32/stm32f407-armfly-v5/template.eww new file mode 100644 index 0000000000000000000000000000000000000000..bd036bb4c98c1598f04b85f64b0dff37f6ec6028 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/stm32/stm32f407-armfly-v5/template.uvopt b/bsp/stm32/stm32f407-armfly-v5/template.uvopt new file mode 100644 index 0000000000000000000000000000000000000000..5cc5956b4f15734153479bff1fa2d2c672de61e5 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/template.uvopt @@ -0,0 +1,199 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 25000000 + + 1 + 1 + 1 + 0 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 255 + + + 0 + Datasheet + DATASHTS\ST\STM32F4xx\DM00037051.pdf + + + 1 + Reference Manual + DATASHTS\ST\STM32F4xx\DM00031020.pdf + + + 2 + Technical Reference Manual + datashts\arm\cortex_m4\r0p1\DDI0439C_CORTEX_M4_R0P1_TRM.PDF + + + 3 + Generic User Guide + datashts\arm\cortex_m4\r0p1\DUI0553A_CORTEX_M4_DGUG.PDF + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + UL2CM3 + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000) + + + 0 + JL2CM3 + -U30000299 -O207 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + diff --git a/bsp/stm32/stm32f407-armfly-v5/template.uvoptx b/bsp/stm32/stm32f407-armfly-v5/template.uvoptx new file mode 100644 index 0000000000000000000000000000000000000000..904af41f77d0c1ddf6a9485fa5ce17cf0154a9d2 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/template.uvoptx @@ -0,0 +1,187 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 24000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32F4xx_1024 -FL0100000 -FS08000000 -FP0($$Device:STM32F407IGTx$CMSIS\Flash\STM32F4xx_1024.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 10000000 + + + + + + Source Group 1 + 0 + 0 + 0 + 0 + + + diff --git a/bsp/stm32/stm32f407-armfly-v5/template.uvproj b/bsp/stm32/stm32f407-armfly-v5/template.uvproj new file mode 100644 index 0000000000000000000000000000000000000000..73d0b32956b0628c862b7a648741f55cbab8985b --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/template.uvproj @@ -0,0 +1,438 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 0 + + + STM32F407IG + STMicroelectronics + IRAM(0x20000000-0x2001FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) CPUTYPE("Cortex-M4") FPU2 + + "Startup\ST\STM32F4xx\startup_stm32f40_41xxx.s" ("STM32F40/41xxx Startup Code") + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000) + 6104 + stm32f4xx.h + + + + + + + -DSTM32F40_41xxx + + + SFD\ST\STM32F4xx\STM32F40x.sfr + 0 + 0 + + + + ST\STM32F4xx\ + ST\STM32F4xx\ + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU -REMAP + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + + 0 + 6 + + + + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4101 + + 1 + STLink\ST-LINKIII-KEIL_SWO.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/bsp/stm32/stm32f407-armfly-v5/template.uvprojx b/bsp/stm32/stm32f407-armfly-v5/template.uvprojx new file mode 100644 index 0000000000000000000000000000000000000000..4c3ec18c73a4f1a50d3886cd5dcc90990f71c9ae --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/template.uvprojx @@ -0,0 +1,411 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + STM32F407IGTx + STMicroelectronics + Keil.STM32F4xx_DFP.2.14.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IRAM2(0x10000000,0x00010000) IROM(0x08000000,0x00100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407IGTx$CMSIS\Flash\STM32F4xx_1024.FLM)) + 0 + $$Device:STM32F407IGTx$Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h + + + + + + + + + + $$Device:STM32F407IGTx$CMSIS\SVD\STM32F40x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4101 + + 1 + STLink\ST-LINKIII-KEIL_SWO.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Source Group 1 + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/bsp/stm32/stm32f413-st-nucleo/.config b/bsp/stm32/stm32f413-st-nucleo/.config index d8d4619864c5c842c3769c8031bd15d87448653a..ade1a6699f2cbbe5c070b0515cc251b3f21c030c 100644 --- a/bsp/stm32/stm32f413-st-nucleo/.config +++ b/bsp/stm32/stm32f413-st-nucleo/.config @@ -130,7 +130,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set # CONFIG_RT_USING_SPI is not set -# CONFIG_RT_USING_WDT is not set +CONFIG_RT_USING_WDT=y # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set # CONFIG_RT_USING_TOUCH is not set @@ -366,6 +366,13 @@ CONFIG_BSP_USING_UART=y # CONFIG_BSP_USING_UART2 is not set CONFIG_BSP_USING_UART3=y # CONFIG_BSP_UART3_RX_USING_DMA is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_I2C1 is not set +# CONFIG_BSP_USING_TIM is not set +# CONFIG_BSP_USING_PWM is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_ONCHIP_RTC is not set +# CONFIG_BSP_USING_WDT is not set # CONFIG_BSP_USING_ON_CHIP_FLASH is not set # CONFIG_BSP_USING_USBD is not set # CONFIG_BSP_USING_RNG is not set diff --git a/bsp/stm32/stm32f413-st-nucleo/README.md b/bsp/stm32/stm32f413-st-nucleo/README.md index 083970d56b74897b55e46bc541ccb1922812509b..e795064dba95ad5f097897811cb0a52648345c78 100644 --- a/bsp/stm32/stm32f413-st-nucleo/README.md +++ b/bsp/stm32/stm32f413-st-nucleo/README.md @@ -24,7 +24,7 @@ - MCU：STM32F413ZH，主频 100MHz，1536KB FLASH ，320KB RAM - 常用外设 - - LED：8个，user LED (绿色，PC9，LD1；蓝色，PB7，LD2；红色，PB14，LD3), USB communication (LD4), over current (LD5), power LED (黄色，LD6), USB FAULT (LD7), VBUS (LD8)。 + - LED：8个，user LED (JP5跳帽需连接)(黄色，PB0，LD1；蓝色，PB7，LD2；红色，PB14，LD3), USB communication (LD4), over current (LD5), power LED (黄色，LD6), USB FAULT (LD7), VBUS (LD8)。 - 按键：2个，B1（USER，PC13），B2（RESET） - 常用接口：USB 支持 3 种不同接口：虚拟 COM 端口、大容量存储和调试端口等。 - 调试接口，板载 ST-LINK/V2-1 调试器。 @@ -35,12 +35,27 @@ 本 BSP 目前对外设的支持情况如下： +| **板载外设** | **支持情况** | **备注** | +| :------------ | :----------: | :-----------------------------------: | +|STLINK TO USART| 支持 | UART3 | + | **片上外设** | **支持情况** | **备注** | | :------------ | :----------: | :-----------------------------------: | -| GPIO | 支持 | | -| UART | 支持 | UART2,UART3 | -| Onchip Flash | 支持 | | -| USB Device | 支持 | | +| GPIO | 支持 | | +| UART | 支持 | UART2/3 | +| SPI | 支持 | SPI2 | +| I2C | 支持 | I2C1(软件模拟) | +| TIMER | 支持 | TIM11/13/14 | +| PWM | 支持 | PWM2_CH4 | +| ADC | 支持 | ADC1_IN5 | +| RTC | 支持 | 支持外部晶振和内部低速时钟 | +| WDT | 支持 | 独立看门狗 | +| Onchip Flash | 支持 | 片上Flash | +| USB OTG_FS | 支持 | OTGFS as USB device | +| Onchip Flash | 支持 | 片上Flash | +| USB Device | 支持 | OTGFS as USB device | +| RNG | 支持 | Random Number Generator | +| UDID | 支持 | Unique Device Identifier | ## 使用说明 @@ -67,11 +82,11 @@ 双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 -> 工程默认配置使用 xxx 仿真器下载程序，在通过 xxx 连接开发板的基础上，点击下载按钮即可下载程序到开发板 +> 工程默认配置使用 板载ST-LINK 仿真器下载程序，在通过 Micro USB线 连接开发板的基础上，点击下载按钮即可下载程序到开发板 #### 运行结果 -下载程序成功之后，系统会自动运行，观察开发板上 LD2 的运行效果，蓝色 LD2 会周期性闪烁。 +下载程序成功之后，系统会自动运行，在JP5跳帽连接时，观察开发板上LD1的运行效果，黄色LED会周期性闪烁。 连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: @@ -84,7 +99,7 @@ msh > ``` ### 进阶使用 -此 BSP 默认只开启了 GPIO 和 串口 3 的功能，更多高级功能需要利用 ENV 工具对 BSP 进行配置，步骤如下： +此 BSP 默认只开启了 GPIO 和 UART3 的功能，更多高级功能需要利用 ENV 工具对 BSP 进行配置，步骤如下： 1. 在 bsp 下打开 env 工具。 diff --git a/bsp/stm32/stm32f413-st-nucleo/applications/main.c b/bsp/stm32/stm32f413-st-nucleo/applications/main.c index 9f63c9a7ff53d45ecd65ff83ed283ff147129fe7..18b64457a92bae55f86e5388f29d59ea6dd73e96 100644 --- a/bsp/stm32/stm32f413-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32f413-st-nucleo/applications/main.c @@ -12,21 +12,26 @@ #include #include +/* defined the LED1 pin: PB0 */ +#define LED1_PIN GET_PIN(B, 0) /* defined the LED2 pin: PB7 */ #define LED2_PIN GET_PIN(B, 7) +/* defined the LED3 pin: PB14 */ +#define LED3_PIN GET_PIN(B, 14) +/* defined the USER KEY pin: PC13 */ +#define KEY_PIN GET_PIN(C, 13) int main(void) { int count = 1; - /* set LED0 pin mode to output */ - rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT); + /* set LED1 pin mode to output */ + rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT); while (count++) { - rt_pin_write(LED2_PIN, PIN_HIGH); - rt_thread_mdelay(500); - rt_pin_write(LED2_PIN, PIN_LOW); + rt_pin_write(LED1_PIN, PIN_HIGH); rt_thread_mdelay(500); + rt_pin_write(LED1_PIN, PIN_LOW); } return RT_EOK; diff --git a/bsp/stm32/stm32f413-st-nucleo/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32f413-st-nucleo/board/CubeMX_Config/.mxproject index 373c6cc6defe5ce994f41974f14908134c4fb90f..2bc7e1a3d78971310700d1a7d5498281be977577 100644 --- a/bsp/stm32/stm32f413-st-nucleo/board/CubeMX_Config/.mxproject +++ b/bsp/stm32/stm32f413-st-nucleo/board/CubeMX_Config/.mxproject @@ -5,13 +5,14 @@ SourcePath=H:/RT-Thread/rt-thread/bsp/stm32/stm32f413-st-nucleo/board/CubeMX_Con SourceFiles=stm32f4xx_it.c;stm32f4xx_hal_msp.c;main.c; [PreviousLibFiles] -LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f413xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h; +LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f413xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h; [PreviousUsedIarFiles] SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../\Src/system_stm32f4xx.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../\Src/system_stm32f4xx.c;../Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;null; HeaderPath=..\Drivers\STM32F4xx_HAL_Driver\Inc;..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F4xx\Include;..\Drivers\CMSIS\Include;..\Inc; [PreviousUsedKeilFiles] -SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;../\Src/system_stm32f4xx.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;../\Src/system_stm32f4xx.c;../Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;null; +SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c;..\\Src/system_stm32f4xx.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c;..\\Src/system_stm32f4xx.c;..\Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;; HeaderPath=..\Drivers\STM32F4xx_HAL_Driver\Inc;..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F4xx\Include;..\Drivers\CMSIS\Include;..\Inc; +CDefines=USE_HAL_DRIVER;STM32F413xx;USE_HAL_DRIVER;USE_HAL_DRIVER; diff --git a/bsp/stm32/stm32f413-st-nucleo/board/CubeMX_Config/Inc/main.h b/bsp/stm32/stm32f413-st-nucleo/board/CubeMX_Config/Inc/main.h index 04267febcc78ea9eea13581131ad8e9223ea4209..e0bcb43ae2706bdadcc10559871a5e428bd61510 100644 --- a/bsp/stm32/stm32f413-st-nucleo/board/CubeMX_Config/Inc/main.h +++ b/bsp/stm32/stm32f413-st-nucleo/board/CubeMX_Config/Inc/main.h @@ -70,6 +70,8 @@ extern "C" { /* USER CODE END EM */ +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + /* Exported functions prototypes ---------------------------------------------*/ void Error_Handler(void); diff --git a/bsp/stm32/stm32f413-st-nucleo/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h b/bsp/stm32/stm32f413-st-nucleo/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h index 9fabadb8c340a0836f11afa6ed826db49e0c7d5e..9b8a5b56b0a4d523e6aca091cb22350f16ecb732 100644 --- a/bsp/stm32/stm32f413-st-nucleo/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h +++ b/bsp/stm32/stm32f413-st-nucleo/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h @@ -49,7 +49,7 @@ */ #define HAL_MODULE_ENABLED -/* #define HAL_ADC_MODULE_ENABLED */ +#define HAL_ADC_MODULE_ENABLED /* #define HAL_CRYP_MODULE_ENABLED */ /* #define HAL_CAN_MODULE_ENABLED */ /* #define HAL_CRC_MODULE_ENABLED */ @@ -64,17 +64,17 @@ /* #define HAL_SRAM_MODULE_ENABLED */ /* #define HAL_SDRAM_MODULE_ENABLED */ /* #define HAL_HASH_MODULE_ENABLED */ -/* #define HAL_I2C_MODULE_ENABLED */ +#define HAL_I2C_MODULE_ENABLED /* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ +#define HAL_IWDG_MODULE_ENABLED /* #define HAL_LTDC_MODULE_ENABLED */ /* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ +#define HAL_RTC_MODULE_ENABLED /* #define HAL_SAI_MODULE_ENABLED */ /* #define HAL_SD_MODULE_ENABLED */ /* #define HAL_MMC_MODULE_ENABLED */ -/* #define HAL_SPI_MODULE_ENABLED */ -/* #define HAL_TIM_MODULE_ENABLED */ +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIM_MODULE_ENABLED #define HAL_UART_MODULE_ENABLED /* #define HAL_USART_MODULE_ENABLED */ /* #define HAL_IRDA_MODULE_ENABLED */ diff --git a/bsp/stm32/stm32f413-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f413-st-nucleo/board/CubeMX_Config/STM32F413ZH.ioc similarity index 73% rename from bsp/stm32/stm32f413-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc rename to bsp/stm32/stm32f413-st-nucleo/board/CubeMX_Config/STM32F413ZH.ioc index a939b37e7b19b17d70fd31d1d15edbdcd625d2a2..c266589aab6622369a2d78f924ed0ea9d155e416 100644 --- a/bsp/stm32/stm32f413-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32f413-st-nucleo/board/CubeMX_Config/STM32F413ZH.ioc @@ -1,261 +1,326 @@ #MicroXplorer Configuration settings - do not modify -File.Version=6 -KeepUserPlacement=true Mcu.Family=STM32F4 -Mcu.IP0=NVIC -Mcu.IP1=RCC -Mcu.IP2=SYS -Mcu.IP3=USART3 -Mcu.IP4=USB_OTG_FS -Mcu.IPNb=5 -Mcu.Name=STM32F413Z(G-H)Tx -Mcu.Package=LQFP144 +PC3.Mode=Full_Duplex_Master +ProjectManager.MainLocation=Src +RCC.MCOFreq_Value=72000000 +RCC.USART1Freq_Value=72000000 +USART2.IPParameters=VirtualMode +RCC.CortexFreq_Value=96000000 +RCC.TIM17Freq_Value=72000000 +PG6.Signal=GPIO_Output +ProjectManager.KeepUserCode=true +Mcu.UserName=STM32F413ZHTx +PD9.GPIOParameters=GPIO_Label +SPI2.VirtualType=VM_MASTER +PB10.Mode=Full_Duplex_Master +PG6.Locked=true +RCC.PLLCLKFreq_Value=96000000 +PB14.GPIO_Label=LD3 [Red] +VP_IWDG_VS_IWDG.Mode=IWDG_Activate +PG6.GPIO_Label=USB_PowerSwitchOn [STMPS2151STR_EN] +PA14.GPIO_Label=TCK +RCC.PLLQCLKFreq_Value=48000000 +RCC.SYSCLKSourceVirtual=RCC_SYSCLKSOURCE_PLLCLK +PA12.GPIOParameters=GPIO_Label +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART3_UART_Init-USART3-false-HAL-true,4-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true,5-MX_ADC1_Init-ADC1-false-HAL-true,6-MX_I2C1_Init-I2C1-false-HAL-true,7-MX_IWDG_Init-IWDG-false-HAL-true,8-MX_RTC_Init-RTC-false-HAL-true,9-MX_SPI2_Init-SPI2-false-HAL-true,10-MX_TIM2_Init-TIM2-false-HAL-true,11-MX_TIM11_Init-TIM11-false-HAL-true,12-MX_TIM13_Init-TIM13-false-HAL-true,13-MX_TIM14_Init-TIM14-false-HAL-true,14-MX_USART2_UART_Init-USART2-false-HAL-true +PA9.GPIOParameters=GPIO_Label +PD8.Locked=true +PA11.GPIOParameters=GPIO_Label +VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled +PA11.Mode=Device_Only +RCC.RTCFreq_Value=32000 +PC9.Locked=true +RCC.PLLI2SRCLKFreq_Value=48000000 +RCC.USART2Freq_Value=36000000 +PC13.GPIO_Label=USER_Btn [B1] +PD9.Mode=Asynchronous +PinOutPanel.RotationAngle=0 +RCC.MCO1PinFreq_Value=16000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +ProjectManager.StackSize=0x400 +SH.GPXTI13.0=GPIO_EXTI13 +RCC.I2C3Freq_Value=8000000 +Mcu.IP4=RCC +RCC.FCLKCortexFreq_Value=96000000 +Mcu.IP5=RTC +Mcu.IP2=IWDG +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false +Mcu.IP3=NVIC +Mcu.IP0=ADC1 +PA12.Locked=true +Mcu.IP1=I2C1 +PA12.Signal=USB_OTG_FS_DP +Mcu.UserConstants= +PH0\ -\ OSC_IN.Signal=RCC_OSC_IN +SH.GPXTI13.ConfNb=1 +PH0\ -\ OSC_IN.Locked=true +Mcu.ThirdPartyNb=0 +RCC.SDIOFreq_Value=48000000 +RCC.HCLKFreq_Value=96000000 +Mcu.IPNb=15 +RCC.I2SClocksFreq_Value=48000000 +TIM2.IPParameters=Channel-PWM Generation4 CH4 +ProjectManager.PreviousToolchain= +RCC.APB2TimFreq_Value=96000000 +PB6.Signal=I2C1_SCL +RCC.VcooutputI2S=48000000 +RCC.SAI1BFreq_Value=8000000 +RCC.PLLRoutputFreq_Value=192000000 +PD8.GPIOParameters=GPIO_Label +PB6.Mode=I2C +PC3.Signal=SPI2_MOSI +PA8.GPIOParameters=GPIO_Label +Mcu.Pin6=PC3 +Mcu.Pin7=PA2 +PD8.Signal=USART3_TX +VP_TIM2_VS_ClockSourceINT.Signal=TIM2_VS_ClockSourceINT +Mcu.Pin8=PA3 +Mcu.Pin9=PA5 +RCC.AHBFreq_Value=96000000 +RCC.TIM2Freq_Value=72000000 Mcu.Pin0=PC13 Mcu.Pin1=PC14-OSC32_IN -Mcu.Pin10=PC9 -Mcu.Pin11=PA8 -Mcu.Pin12=PA9 -Mcu.Pin13=PA10 -Mcu.Pin14=PA11 -Mcu.Pin15=PA12 -Mcu.Pin16=PA13 -Mcu.Pin17=PA14 -Mcu.Pin18=PB3 -Mcu.Pin19=PB7 Mcu.Pin2=PC15-OSC32_OUT -Mcu.Pin20=VP_SYS_VS_Systick Mcu.Pin3=PH0 - OSC_IN +RCC.USART3Freq_Value=36000000 Mcu.Pin4=PH1 - OSC_OUT -Mcu.Pin5=PB14 -Mcu.Pin6=PD8 -Mcu.Pin7=PD9 -Mcu.Pin8=PG6 -Mcu.Pin9=PG7 -Mcu.PinsNb=21 -Mcu.ThirdPartyNb=0 -Mcu.UserConstants= -Mcu.UserName=STM32F413ZHTx -MxCube.Version=5.1.0 -MxDb.Version=DB.5.0.10 -NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false +Mcu.Pin5=PC2 +ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_5 +ProjectManager.ProjectBuild=false +RCC.HSE_VALUE=8000000 +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:true\:false -NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false -NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:true\:false -NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:true\:false -NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false -NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 -NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false +PA8.Locked=true +Mcu.IP10=TIM13 NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true -NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false -PA10.GPIOParameters=GPIO_Label +Mcu.IP12=USART2 +RCC.PLLMUL=RCC_PLL_MUL9 +Mcu.IP11=TIM14 +ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.24.2 +MxDb.Version=DB.5.0.10 +Mcu.IP14=USB_OTG_FS +Mcu.IP13=USART3 +ProjectManager.BackupPrevious=false +PC14-OSC32_IN.Mode=LSE-External-Oscillator +RCC.VCOInputFreq_Value=1000000 +PA14.Mode=Serial_Wire +File.Version=6 PA10.GPIO_Label=USB_ID -PA10.Locked=true -PA10.Signal=USB_OTG_FS_ID -PA11.GPIOParameters=GPIO_Label -PA11.GPIO_Label=USB_DM -PA11.Locked=true -PA11.Mode=Device_Only -PA11.Signal=USB_OTG_FS_DM -PA12.GPIOParameters=GPIO_Label -PA12.GPIO_Label=USB_DP -PA12.Locked=true -PA12.Mode=Device_Only -PA12.Signal=USB_OTG_FS_DP +SPI2.CalculateBaudRate=24.0 MBits/s +PB3.GPIOParameters=GPIO_Label +PB7.Signal=GPIO_Output +PA8.Signal=USB_OTG_FS_SOF +RCC.PLLRCLKFreq_Value=192000000 +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false +RCC.PLLI2SoutputFreq_Value=48000000 +ProjectManager.HalAssertFull=false +ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES +ProjectManager.ProjectName=STM32F413ZH +RCC.TIM1Freq_Value=72000000 +PH0\ -\ OSC_IN.GPIOParameters=GPIO_Label PA13.GPIOParameters=GPIO_Label -PA13.GPIO_Label=TMS -PA13.Locked=true -PA13.Mode=Serial_Wire -PA13.Signal=SYS_JTMS-SWDIO -PA14.GPIOParameters=GPIO_Label -PA14.GPIO_Label=TCK +RCC.PLLMCOFreq_Value=72000000 +PB7.GPIO_Label=LD2 [Blue] +RCC.MCO2PinFreq_Value=96000000 +Mcu.Package=LQFP144 +PB9.Signal=I2C1_SDA +RCC.TIM15Freq_Value=72000000 +SPI2.Mode=SPI_MODE_MASTER +RCC.I2S2Freq_Value=48000000 +RCC.SAI1AFreq_Value=8000000 +RCC.ADC34outputFreq_Value=72000000 +USART2.VirtualMode=VM_ASYNC PA14.Locked=true -PA14.Mode=Serial_Wire -PA14.Signal=SYS_JTCK-SWCLK -PA8.GPIOParameters=GPIO_Label -PA8.GPIO_Label=USB_SOF [TP1] -PA8.Locked=true -PA8.Mode=Activate_SOF_FS -PA8.Signal=USB_OTG_FS_SOF -PA9.GPIOParameters=GPIO_Label -PA9.GPIO_Label=USB_VBUS -PA9.Locked=true -PA9.Mode=Activate_VBUS -PA9.Signal=USB_OTG_FS_VBUS +ProjectManager.ToolChainLocation= +RCC.LSI_VALUE=32000 +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +USART3.IPParameters=VirtualMode +PA10.Signal=USB_OTG_FS_ID +USB_OTG_FS.VirtualMode=Device_Only +VP_TIM11_VS_ClockSourceINT.Signal=TIM11_VS_ClockSourceINT +VP_TIM13_VS_ClockSourceINT.Signal=TIM13_VS_ClockSourceINT +RCC.DFSDMFreq_Value=96000000 PB14.GPIOParameters=GPIO_Label -PB14.GPIO_Label=LD3 [Red] -PB14.Locked=true -PB14.Signal=GPIO_Output -PB3.GPIOParameters=GPIO_Label -PB3.GPIO_Label=SWO +RCC.TIM16Freq_Value=72000000 +RCC.APB1TimFreq_Value=96000000 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false +SPI2.Direction=SPI_DIRECTION_2LINES +RCC.DFSDM2AudioFreq_Value=48000000 +USB_OTG_FS.IPParameters=VirtualMode +VP_TIM14_VS_ClockSourceINT.Mode=Enable_Timer +RCC.PLLI2SQoutputFreq_Value=48000000 +SH.S_TIM2_CH4.ConfNb=1 +RCC.DFSDMAudioFreq_Value=48000000 +RCC.LPTimerFreq_Value=48000000 +PD6.Signal=USART2_RX +ProjectManager.CustomerFirmwarePackage= +PC14-OSC32_IN.Locked=true PB3.Locked=true -PB3.Signal=SYS_JTDO-SWO -PB7.GPIOParameters=GPIO_Label -PB7.GPIO_Label=LD2 [Blue] -PB7.Locked=true -PB7.Signal=GPIO_Output -PC13.GPIOParameters=GPIO_Label -PC13.GPIO_Label=USER_Btn [B1] +PA3.Signal=S_TIM2_CH4 +PB3.GPIO_Label=SWO +VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate +PC15-OSC32_OUT.Mode=LSE-External-Oscillator +RCC.PLLQoutputFreq_Value=48000000 +ProjectManager.ProjectFileName=STM32F413ZH.ioc +TIM2.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4 +RCC.ADC12outputFreq_Value=72000000 +PG7.Locked=true +ADC1.Rank-0\#ChannelRegularConversion=1 +PG7.Signal=GPIO_Input +PD9.GPIO_Label=STLK_TX [STM32F103CBT6_PA2] +Mcu.PinsNb=36 +VP_TIM14_VS_ClockSourceINT.Signal=TIM14_VS_ClockSourceINT +PC9.GPIO_Label=LD1 [Green] +ProjectManager.NoMain=false +ADC1.IPParameters=Rank-0\#ChannelRegularConversion,master,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag PC13.Locked=true PC13.Signal=GPXTI13 -PC14-OSC32_IN.Locked=true -PC14-OSC32_IN.Mode=LSE-External-Oscillator +PA9.GPIO_Label=USB_VBUS +RCC.FMPI2C1Freq_Value=48000000 +RCC.VCOI2SInputFreq_Value=500000 +PH1\ -\ OSC_OUT.Mode=HSE-External-Clock-Source +PC2.Signal=SPI2_MISO +PA11.GPIO_Label=USB_DM +ProjectManager.DefaultFWLocation=true +PC2.Mode=Full_Duplex_Master +PD9.Signal=USART3_RX +ProjectManager.DeletePrevious=true +PB14.Locked=true +RCC.APB1CLKDivider=RCC_HCLK_DIV2 PC14-OSC32_IN.Signal=RCC_OSC32_IN +boardIOC=true +PD6.Mode=Asynchronous +PA12.GPIO_Label=USB_DP +RCC.FamilyName=M +VP_TIM11_VS_ClockSourceINT.Mode=Enable_Timer +PD8.GPIO_Label=STLK_RX [STM32F103CBT6_PA3] +RCC.WatchDogFreq_Value=32000 +PA13.Signal=SYS_JTMS-SWDIO +PA11.Locked=true +PA9.Mode=Activate_VBUS +PH0\ -\ OSC_IN.Mode=HSE-External-Clock-Source +PA8.GPIO_Label=USB_SOF [TP1] PC15-OSC32_OUT.Locked=true -PC15-OSC32_OUT.Mode=LSE-External-Oscillator +ProjectManager.TargetToolchain=MDK-ARM V5 +PB7.GPIOParameters=GPIO_Label +PB9.Mode=I2C +PA9.Signal=USB_OTG_FS_VBUS +RCC.I2S1Freq_Value=48000000 +SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate +RCC.VCOInputMFreq_Value=500000 +RCC.USBFreq_Value=48000000 PC15-OSC32_OUT.Signal=RCC_OSC32_OUT -PC9.GPIOParameters=GPIO_Label -PC9.GPIO_Label=LD1 [Green] -PC9.Locked=true -PC9.Signal=GPIO_Output -PCC.Checker=false -PCC.Line=STM32F413/423 -PCC.MCU=STM32F413Z(G-H)Tx -PCC.PartNumber=STM32F413ZHTx -PCC.Seq0=0 -PCC.Series=STM32F4 -PCC.Temperature=25 -PCC.Vdd=null -PD8.GPIOParameters=GPIO_Label -PD8.GPIO_Label=STLK_RX [STM32F103CBT6_PA3] -PD8.Locked=true PD8.Mode=Asynchronous -PD8.Signal=USART3_TX -PD9.GPIOParameters=GPIO_Label -PD9.GPIO_Label=STLK_TX [STM32F103CBT6_PA2] -PD9.Locked=true -PD9.Mode=Asynchronous -PD9.Signal=USART3_RX +PB10.Signal=SPI2_SCK +RCC.VCOI2SOutputFreq_Value=96000000 +PB14.Signal=GPIO_Output PG6.GPIOParameters=GPIO_Label -PG6.GPIO_Label=USB_PowerSwitchOn [STMPS2151STR_EN] -PG6.Locked=true -PG6.Signal=GPIO_Output -PG7.GPIOParameters=GPIO_Label -PG7.GPIO_Label=USB_OverCurrent [STMPS2151STR_FAULT] -PG7.Locked=true -PG7.Signal=GPIO_Input -PH0\ -\ OSC_IN.GPIOParameters=GPIO_Label -PH0\ -\ OSC_IN.GPIO_Label=MCO -PH0\ -\ OSC_IN.Locked=true -PH0\ -\ OSC_IN.Mode=HSE-External-Clock-Source -PH0\ -\ OSC_IN.Signal=RCC_OSC_IN -PH1\ -\ OSC_OUT.Mode=HSE-External-Clock-Source +PA5.Signal=ADCx_IN5 PH1\ -\ OSC_OUT.Signal=RCC_OSC_OUT -PinOutPanel.RotationAngle=0 -ProjectManager.AskForMigrate=true -ProjectManager.BackupPrevious=false -ProjectManager.CompilerOptimize=6 -ProjectManager.ComputerToolchain=false -ProjectManager.CoupleFile=false -ProjectManager.CustomerFirmwarePackage= -ProjectManager.DefaultFWLocation=true -ProjectManager.DeletePrevious=true -ProjectManager.DeviceId=STM32F413ZHTx -ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.24.2 -ProjectManager.FreePins=false -ProjectManager.HalAssertFull=false -ProjectManager.HeapSize=0x200 -ProjectManager.KeepUserCode=true +board=NUCLEO-F413ZH +RCC.VCOOutputFreq_Value=384000000 ProjectManager.LastFirmware=true -ProjectManager.LibraryCopy=0 -ProjectManager.MainLocation=Src -ProjectManager.NoMain=false -ProjectManager.PreviousToolchain= -ProjectManager.ProjectBuild=false -ProjectManager.ProjectFileName=CubeMX_Config.ioc -ProjectManager.ProjectName=CubeMX_Config -ProjectManager.StackSize=0x400 -ProjectManager.TargetToolchain=MDK-ARM V5 -ProjectManager.ToolChainLocation= -ProjectManager.UnderRoot=false -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART3_UART_Init-USART3-false-HAL-true,4-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true -RCC.48MHZClocksFreq_Value=24000000 -RCC.ADC12outputFreq_Value=72000000 -RCC.ADC34outputFreq_Value=72000000 -RCC.AHBFreq_Value=96000000 -RCC.APB1CLKDivider=RCC_HCLK_DIV2 -RCC.APB1Freq_Value=48000000 -RCC.APB1TimFreq_Value=96000000 +RCC.VCOOutput2Freq_Value=8000000 +VP_TIM13_VS_ClockSourceINT.Mode=Enable_Timer RCC.APB2Freq_Value=96000000 -RCC.APB2TimFreq_Value=96000000 -RCC.CortexFreq_Value=96000000 -RCC.DFSDM2AudioFreq_Value=48000000 -RCC.DFSDMAudioFreq_Value=48000000 -RCC.DFSDMFreq_Value=96000000 -RCC.EthernetFreq_Value=8000000 -RCC.FCLKCortexFreq_Value=96000000 -RCC.FMPI2C1Freq_Value=48000000 -RCC.FamilyName=M -RCC.HCLKFreq_Value=96000000 -RCC.HSE_VALUE=8000000 -RCC.HSI_VALUE=16000000 +RCC.TIM8Freq_Value=72000000 +RCC.UART4Freq_Value=36000000 +MxCube.Version=5.1.0 +RCC.PRESCALERUSB=RCC_USBCLKSOURCE_PLL_DIV1_5 +VP_TIM2_VS_ClockSourceINT.Mode=Internal +Mcu.Pin35=VP_TIM14_VS_ClockSourceINT RCC.I2C1Freq_Value=8000000 -RCC.I2C2Freq_Value=8000000 -RCC.I2C3Freq_Value=8000000 -RCC.I2S1Freq_Value=48000000 -RCC.I2S2Freq_Value=48000000 -RCC.I2SClocksFreq_Value=48000000 -RCC.IPParameters=48MHZClocksFreq_Value,ADC12outputFreq_Value,ADC34outputFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,DFSDM2AudioFreq_Value,DFSDMAudioFreq_Value,DFSDMFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FMPI2C1Freq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2S1Freq_Value,I2S2Freq_Value,I2SClocksFreq_Value,LPTimerFreq_Value,LSI_VALUE,MCO1PinFreq_Value,MCO2PinFreq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLI2SPCLKFreq_Value,PLLI2SQCLKFreq_Value,PLLI2SQoutputFreq_Value,PLLI2SRCLKFreq_Value,PLLI2SoutputFreq_Value,PLLM,PLLMCOFreq_Value,PLLMUL,PLLN,PLLP,PLLQ,PLLQCLKFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLRoutputFreq_Value,PRESCALERUSB,PWRFreq_Value,RNGFreq_Value,RTCFreq_Value,RTCHSEDivFreq_Value,SAI1AFreq_Value,SAI1BFreq_Value,SDIOFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,SYSCLKSourceVirtual,TIM15Freq_Value,TIM16Freq_Value,TIM17Freq_Value,TIM1Freq_Value,TIM20Freq_Value,TIM2Freq_Value,TIM3Freq_Value,TIM8Freq_Value,UART4Freq_Value,UART5Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOI2SInputFreq_Value,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOInputMFreq_Value,VCOOutput2Freq_Value,VCOOutputFreq_Value,VcooutputI2S,WatchDogFreq_Value -RCC.LPTimerFreq_Value=48000000 -RCC.LSI_VALUE=32000 -RCC.MCO1PinFreq_Value=16000000 -RCC.MCO2PinFreq_Value=96000000 -RCC.MCOFreq_Value=72000000 -RCC.PLLCLKFreq_Value=96000000 RCC.PLLI2SPCLKFreq_Value=48000000 -RCC.PLLI2SQCLKFreq_Value=48000000 -RCC.PLLI2SQoutputFreq_Value=48000000 -RCC.PLLI2SRCLKFreq_Value=48000000 -RCC.PLLI2SoutputFreq_Value=48000000 -RCC.PLLM=8 -RCC.PLLMCOFreq_Value=72000000 -RCC.PLLMUL=RCC_PLL_MUL9 -RCC.PLLN=384 -RCC.PLLP=RCC_PLLP_DIV4 -RCC.PLLQ=8 -RCC.PLLQCLKFreq_Value=48000000 -RCC.PLLQoutputFreq_Value=48000000 -RCC.PLLRCLKFreq_Value=192000000 -RCC.PLLRoutputFreq_Value=192000000 -RCC.PRESCALERUSB=RCC_USBCLKSOURCE_PLL_DIV1_5 -RCC.PWRFreq_Value=96000000 +PC13.GPIOParameters=GPIO_Label +PG7.GPIO_Label=USB_OverCurrent [STMPS2151STR_FAULT] RCC.RNGFreq_Value=48000000 -RCC.RTCFreq_Value=32000 +Mcu.Pin30=VP_RTC_VS_RTC_Activate +PA10.GPIOParameters=GPIO_Label +VP_SYS_VS_Systick.Mode=SysTick +RCC.EthernetFreq_Value=8000000 +Mcu.Pin33=VP_TIM11_VS_ClockSourceINT +Mcu.Pin34=VP_TIM13_VS_ClockSourceINT +Mcu.Pin31=VP_SYS_VS_Systick +Mcu.Pin32=VP_TIM2_VS_ClockSourceINT +PA9.Locked=true +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:true\:false +RCC.UART5Freq_Value=36000000 +PA13.Mode=Serial_Wire +ProjectManager.FreePins=false +RCC.IPParameters=48MHZClocksFreq_Value,ADC12outputFreq_Value,ADC34outputFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,DFSDM2AudioFreq_Value,DFSDMAudioFreq_Value,DFSDMFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FMPI2C1Freq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2S1Freq_Value,I2S2Freq_Value,I2SClocksFreq_Value,LPTimerFreq_Value,LSI_VALUE,MCO1PinFreq_Value,MCO2PinFreq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLI2SPCLKFreq_Value,PLLI2SQCLKFreq_Value,PLLI2SQoutputFreq_Value,PLLI2SRCLKFreq_Value,PLLI2SoutputFreq_Value,PLLM,PLLMCOFreq_Value,PLLMUL,PLLN,PLLP,PLLQ,PLLQCLKFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLRoutputFreq_Value,PRESCALERUSB,PWRFreq_Value,RNGFreq_Value,RTCFreq_Value,RTCHSEDivFreq_Value,SAI1AFreq_Value,SAI1BFreq_Value,SDIOFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,SYSCLKSourceVirtual,TIM15Freq_Value,TIM16Freq_Value,TIM17Freq_Value,TIM1Freq_Value,TIM20Freq_Value,TIM2Freq_Value,TIM3Freq_Value,TIM8Freq_Value,UART4Freq_Value,UART5Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOI2SInputFreq_Value,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOInputMFreq_Value,VCOOutput2Freq_Value,VCOOutputFreq_Value,VcooutputI2S,WatchDogFreq_Value +PC9.GPIOParameters=GPIO_Label +ProjectManager.AskForMigrate=true +Mcu.Name=STM32F413Z(G-H)Tx +RCC.PLLI2SQCLKFreq_Value=48000000 +Mcu.Pin26=PB6 +Mcu.Pin27=PB7 RCC.RTCHSEDivFreq_Value=4000000 -RCC.SAI1AFreq_Value=8000000 -RCC.SAI1BFreq_Value=8000000 -RCC.SDIOFreq_Value=48000000 +PA2.Signal=USART2_TX +PA13.GPIO_Label=TMS +Mcu.Pin24=PD6 +ProjectManager.UnderRoot=false +Mcu.Pin25=PB3 +Mcu.IP8=TIM2 +Mcu.IP9=TIM11 +Mcu.Pin28=PB9 +Mcu.IP6=SPI2 +Mcu.Pin29=VP_IWDG_VS_IWDG +Mcu.IP7=SYS +ProjectManager.CoupleFile=false +RCC.48MHZClocksFreq_Value=24000000 +PB3.Signal=SYS_JTDO-SWO RCC.SYSCLKFreq_VALUE=96000000 -RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK -RCC.SYSCLKSourceVirtual=RCC_SYSCLKSOURCE_PLLCLK -RCC.TIM15Freq_Value=72000000 -RCC.TIM16Freq_Value=72000000 -RCC.TIM17Freq_Value=72000000 -RCC.TIM1Freq_Value=72000000 +Mcu.Pin22=PA13 +Mcu.Pin23=PA14 +Mcu.Pin20=PA11 +ADC1.master=1 +Mcu.Pin21=PA12 +PA12.Mode=Device_Only +PA10.Locked=true +NVIC.ForceEnableDMAVector=true +KeepUserPlacement=true +USART3.VirtualMode=VM_ASYNC +PA14.GPIOParameters=GPIO_Label +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:true\:false +PA13.Locked=true +ProjectManager.CompilerOptimize=6 +PA11.Signal=USB_OTG_FS_DM +VP_IWDG_VS_IWDG.Signal=IWDG_VS_IWDG +PA14.Signal=SYS_JTCK-SWCLK +ProjectManager.HeapSize=0x200 +Mcu.Pin15=PG7 +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false +Mcu.Pin16=PC9 +SH.S_TIM2_CH4.0=TIM2_CH4,PWM Generation4 CH4 +Mcu.Pin13=PD9 +Mcu.Pin14=PG6 +Mcu.Pin19=PA10 RCC.TIM20Freq_Value=72000000 -RCC.TIM2Freq_Value=72000000 +ProjectManager.ComputerToolchain=false +Mcu.Pin17=PA8 +RCC.HSI_VALUE=16000000 +Mcu.Pin18=PA9 RCC.TIM3Freq_Value=72000000 -RCC.TIM8Freq_Value=72000000 -RCC.UART4Freq_Value=36000000 -RCC.UART5Freq_Value=36000000 -RCC.USART1Freq_Value=72000000 -RCC.USART2Freq_Value=36000000 -RCC.USART3Freq_Value=36000000 -RCC.USBFreq_Value=48000000 -RCC.VCOI2SInputFreq_Value=500000 -RCC.VCOI2SOutputFreq_Value=96000000 -RCC.VCOInputFreq_Value=1000000 -RCC.VCOInputMFreq_Value=500000 -RCC.VCOOutput2Freq_Value=8000000 -RCC.VCOOutputFreq_Value=384000000 -RCC.VcooutputI2S=48000000 -RCC.WatchDogFreq_Value=32000 -SH.GPXTI13.0=GPIO_EXTI13 -SH.GPXTI13.ConfNb=1 -USART3.IPParameters=VirtualMode -USART3.VirtualMode=VM_ASYNC -USB_OTG_FS.IPParameters=VirtualMode -USB_OTG_FS.VirtualMode=Device_Only -VP_SYS_VS_Systick.Mode=SysTick -VP_SYS_VS_Systick.Signal=SYS_VS_Systick -board=NUCLEO-F413ZH -boardIOC=true +SH.ADCx_IN5.0=ADC1_IN5,IN5 +RCC.PLLP=RCC_PLLP_DIV4 +RCC.PLLQ=8 +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +ADC1.NbrOfConversionFlag=1 +Mcu.Pin11=PB14 +Mcu.Pin12=PD8 +RCC.PLLM=8 +RCC.PLLN=384 +Mcu.Pin10=PB10 +PB7.Locked=true +PA2.Mode=Asynchronous +RCC.PWRFreq_Value=96000000 +PH0\ -\ OSC_IN.GPIO_Label=MCO +PA8.Mode=Activate_SOF_FS +SH.ADCx_IN5.ConfNb=1 +PC9.Signal=GPIO_Output +RCC.I2C2Freq_Value=8000000 +PD9.Locked=true +RCC.APB1Freq_Value=48000000 +ProjectManager.DeviceId=STM32F413ZHTx +PG7.GPIOParameters=GPIO_Label +ProjectManager.LibraryCopy=0 diff --git a/bsp/stm32/stm32f413-st-nucleo/board/CubeMX_Config/Src/main.c b/bsp/stm32/stm32f413-st-nucleo/board/CubeMX_Config/Src/main.c index 516049000b6824399dc1ef6101ff68df851fa551..944059e7715b54f63314dfb575551ded202eff2b 100644 --- a/bsp/stm32/stm32f413-st-nucleo/board/CubeMX_Config/Src/main.c +++ b/bsp/stm32/stm32f413-st-nucleo/board/CubeMX_Config/Src/main.c @@ -62,6 +62,22 @@ /* USER CODE END PM */ /* Private variables ---------------------------------------------------------*/ +ADC_HandleTypeDef hadc1; + +I2C_HandleTypeDef hi2c1; + +IWDG_HandleTypeDef hiwdg; + +RTC_HandleTypeDef hrtc; + +SPI_HandleTypeDef hspi2; + +TIM_HandleTypeDef htim2; +TIM_HandleTypeDef htim11; +TIM_HandleTypeDef htim13; +TIM_HandleTypeDef htim14; + +UART_HandleTypeDef huart2; UART_HandleTypeDef huart3; PCD_HandleTypeDef hpcd_USB_OTG_FS; @@ -75,6 +91,16 @@ void SystemClock_Config(void); static void MX_GPIO_Init(void); static void MX_USART3_UART_Init(void); static void MX_USB_OTG_FS_PCD_Init(void); +static void MX_ADC1_Init(void); +static void MX_I2C1_Init(void); +static void MX_IWDG_Init(void); +static void MX_RTC_Init(void); +static void MX_SPI2_Init(void); +static void MX_TIM2_Init(void); +static void MX_TIM11_Init(void); +static void MX_TIM13_Init(void); +static void MX_TIM14_Init(void); +static void MX_USART2_UART_Init(void); /* USER CODE BEGIN PFP */ /* USER CODE END PFP */ @@ -114,6 +140,16 @@ int main(void) MX_GPIO_Init(); MX_USART3_UART_Init(); MX_USB_OTG_FS_PCD_Init(); + MX_ADC1_Init(); + MX_I2C1_Init(); + MX_IWDG_Init(); + MX_RTC_Init(); + MX_SPI2_Init(); + MX_TIM2_Init(); + MX_TIM11_Init(); + MX_TIM13_Init(); + MX_TIM14_Init(); + MX_USART2_UART_Init(); /* USER CODE BEGIN 2 */ /* USER CODE END 2 */ @@ -145,8 +181,9 @@ void SystemClock_Config(void) __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); /** Initializes the CPU, AHB and APB busses clocks */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PLLM = 8; @@ -171,7 +208,8 @@ void SystemClock_Config(void) { Error_Handler(); } - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLQ; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { @@ -179,6 +217,375 @@ void SystemClock_Config(void) } } +/** + * @brief ADC1 Initialization Function + * @param None + * @retval None + */ +static void MX_ADC1_Init(void) +{ + + /* USER CODE BEGIN ADC1_Init 0 */ + + /* USER CODE END ADC1_Init 0 */ + + ADC_ChannelConfTypeDef sConfig = {0}; + + /* USER CODE BEGIN ADC1_Init 1 */ + + /* USER CODE END ADC1_Init 1 */ + /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) + */ + hadc1.Instance = ADC1; + hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; + hadc1.Init.Resolution = ADC_RESOLUTION_12B; + hadc1.Init.ScanConvMode = DISABLE; + hadc1.Init.ContinuousConvMode = DISABLE; + hadc1.Init.DiscontinuousConvMode = DISABLE; + hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; + hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; + hadc1.Init.NbrOfConversion = 1; + hadc1.Init.DMAContinuousRequests = DISABLE; + hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; + if (HAL_ADC_Init(&hadc1) != HAL_OK) + { + Error_Handler(); + } + /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. + */ + sConfig.Channel = ADC_CHANNEL_5; + sConfig.Rank = 1; + sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; + if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN ADC1_Init 2 */ + + /* USER CODE END ADC1_Init 2 */ + +} + +/** + * @brief I2C1 Initialization Function + * @param None + * @retval None + */ +static void MX_I2C1_Init(void) +{ + + /* USER CODE BEGIN I2C1_Init 0 */ + + /* USER CODE END I2C1_Init 0 */ + + /* USER CODE BEGIN I2C1_Init 1 */ + + /* USER CODE END I2C1_Init 1 */ + hi2c1.Instance = I2C1; + hi2c1.Init.ClockSpeed = 100000; + hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2; + hi2c1.Init.OwnAddress1 = 0; + hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + hi2c1.Init.OwnAddress2 = 0; + hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + if (HAL_I2C_Init(&hi2c1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN I2C1_Init 2 */ + + /* USER CODE END I2C1_Init 2 */ + +} + +/** + * @brief IWDG Initialization Function + * @param None + * @retval None + */ +static void MX_IWDG_Init(void) +{ + + /* USER CODE BEGIN IWDG_Init 0 */ + + /* USER CODE END IWDG_Init 0 */ + + /* USER CODE BEGIN IWDG_Init 1 */ + + /* USER CODE END IWDG_Init 1 */ + hiwdg.Instance = IWDG; + hiwdg.Init.Prescaler = IWDG_PRESCALER_4; + hiwdg.Init.Reload = 4095; + if (HAL_IWDG_Init(&hiwdg) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN IWDG_Init 2 */ + + /* USER CODE END IWDG_Init 2 */ + +} + +/** + * @brief RTC Initialization Function + * @param None + * @retval None + */ +static void MX_RTC_Init(void) +{ + + /* USER CODE BEGIN RTC_Init 0 */ + + /* USER CODE END RTC_Init 0 */ + + /* USER CODE BEGIN RTC_Init 1 */ + + /* USER CODE END RTC_Init 1 */ + /** Initialize RTC Only + */ + hrtc.Instance = RTC; + hrtc.Init.HourFormat = RTC_HOURFORMAT_24; + hrtc.Init.AsynchPrediv = 127; + hrtc.Init.SynchPrediv = 255; + hrtc.Init.OutPut = RTC_OUTPUT_DISABLE; + hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; + hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; + if (HAL_RTC_Init(&hrtc) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN RTC_Init 2 */ + + /* USER CODE END RTC_Init 2 */ + +} + +/** + * @brief SPI2 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI2_Init(void) +{ + + /* USER CODE BEGIN SPI2_Init 0 */ + + /* USER CODE END SPI2_Init 0 */ + + /* USER CODE BEGIN SPI2_Init 1 */ + + /* USER CODE END SPI2_Init 1 */ + /* SPI2 parameter configuration*/ + hspi2.Instance = SPI2; + hspi2.Init.Mode = SPI_MODE_MASTER; + hspi2.Init.Direction = SPI_DIRECTION_2LINES; + hspi2.Init.DataSize = SPI_DATASIZE_8BIT; + hspi2.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi2.Init.CLKPhase = SPI_PHASE_1EDGE; + hspi2.Init.NSS = SPI_NSS_SOFT; + hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi2.Init.TIMode = SPI_TIMODE_DISABLE; + hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi2.Init.CRCPolynomial = 10; + if (HAL_SPI_Init(&hspi2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SPI2_Init 2 */ + + /* USER CODE END SPI2_Init 2 */ + +} + +/** + * @brief TIM2 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM2_Init(void) +{ + + /* USER CODE BEGIN TIM2_Init 0 */ + + /* USER CODE END TIM2_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + TIM_OC_InitTypeDef sConfigOC = {0}; + + /* USER CODE BEGIN TIM2_Init 1 */ + + /* USER CODE END TIM2_Init 1 */ + htim2.Instance = TIM2; + htim2.Init.Prescaler = 0; + htim2.Init.CounterMode = TIM_COUNTERMODE_UP; + htim2.Init.Period = 0; + htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim2) != HAL_OK) + { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIM_PWM_Init(&htim2) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + sConfigOC.OCMode = TIM_OCMODE_PWM1; + sConfigOC.Pulse = 0; + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM2_Init 2 */ + + /* USER CODE END TIM2_Init 2 */ + HAL_TIM_MspPostInit(&htim2); + +} + +/** + * @brief TIM11 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM11_Init(void) +{ + + /* USER CODE BEGIN TIM11_Init 0 */ + + /* USER CODE END TIM11_Init 0 */ + + /* USER CODE BEGIN TIM11_Init 1 */ + + /* USER CODE END TIM11_Init 1 */ + htim11.Instance = TIM11; + htim11.Init.Prescaler = 0; + htim11.Init.CounterMode = TIM_COUNTERMODE_UP; + htim11.Init.Period = 0; + htim11.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim11.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim11) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM11_Init 2 */ + + /* USER CODE END TIM11_Init 2 */ + +} + +/** + * @brief TIM13 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM13_Init(void) +{ + + /* USER CODE BEGIN TIM13_Init 0 */ + + /* USER CODE END TIM13_Init 0 */ + + /* USER CODE BEGIN TIM13_Init 1 */ + + /* USER CODE END TIM13_Init 1 */ + htim13.Instance = TIM13; + htim13.Init.Prescaler = 0; + htim13.Init.CounterMode = TIM_COUNTERMODE_UP; + htim13.Init.Period = 0; + htim13.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim13.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim13) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM13_Init 2 */ + + /* USER CODE END TIM13_Init 2 */ + +} + +/** + * @brief TIM14 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM14_Init(void) +{ + + /* USER CODE BEGIN TIM14_Init 0 */ + + /* USER CODE END TIM14_Init 0 */ + + /* USER CODE BEGIN TIM14_Init 1 */ + + /* USER CODE END TIM14_Init 1 */ + htim14.Instance = TIM14; + htim14.Init.Prescaler = 0; + htim14.Init.CounterMode = TIM_COUNTERMODE_UP; + htim14.Init.Period = 0; + htim14.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim14.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim14) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM14_Init 2 */ + + /* USER CODE END TIM14_Init 2 */ + +} + +/** + * @brief USART2 Initialization Function + * @param None + * @retval None + */ +static void MX_USART2_UART_Init(void) +{ + + /* USER CODE BEGIN USART2_Init 0 */ + + /* USER CODE END USART2_Init 0 */ + + /* USER CODE BEGIN USART2_Init 1 */ + + /* USER CODE END USART2_Init 1 */ + huart2.Instance = USART2; + huart2.Init.BaudRate = 115200; + huart2.Init.WordLength = UART_WORDLENGTH_8B; + huart2.Init.StopBits = UART_STOPBITS_1; + huart2.Init.Parity = UART_PARITY_NONE; + huart2.Init.Mode = UART_MODE_TX_RX; + huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart2.Init.OverSampling = UART_OVERSAMPLING_16; + if (HAL_UART_Init(&huart2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART2_Init 2 */ + + /* USER CODE END USART2_Init 2 */ + +} + /** * @brief USART3 Initialization Function * @param None @@ -260,10 +667,10 @@ static void MX_GPIO_Init(void) /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); __HAL_RCC_GPIOG_CLK_ENABLE(); - __HAL_RCC_GPIOA_CLK_ENABLE(); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, LD3_Pin|LD2_Pin, GPIO_PIN_RESET); diff --git a/bsp/stm32/stm32f413-st-nucleo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c b/bsp/stm32/stm32f413-st-nucleo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c index d3fdab64dcf1ff6d0d4cb3898db912e7e0c1b3ba..b70b0c1c20f365b091b2def9c85ec5bd58d606ec 100644 --- a/bsp/stm32/stm32f413-st-nucleo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c +++ b/bsp/stm32/stm32f413-st-nucleo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c @@ -78,7 +78,9 @@ /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ -/** + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + /** * Initializes the Global MSP. */ void HAL_MspInit(void) @@ -97,6 +99,389 @@ void HAL_MspInit(void) /* USER CODE END MspInit 1 */ } +/** +* @brief ADC MSP Initialization +* This function configures the hardware resources used in this example +* @param hadc: ADC handle pointer +* @retval None +*/ +void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hadc->Instance==ADC1) + { + /* USER CODE BEGIN ADC1_MspInit 0 */ + + /* USER CODE END ADC1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_ADC1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**ADC1 GPIO Configuration + PA5 ------> ADC1_IN5 + */ + GPIO_InitStruct.Pin = GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN ADC1_MspInit 1 */ + + /* USER CODE END ADC1_MspInit 1 */ + } + +} + +/** +* @brief ADC MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hadc: ADC handle pointer +* @retval None +*/ +void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) +{ + if(hadc->Instance==ADC1) + { + /* USER CODE BEGIN ADC1_MspDeInit 0 */ + + /* USER CODE END ADC1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_ADC1_CLK_DISABLE(); + + /**ADC1 GPIO Configuration + PA5 ------> ADC1_IN5 + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5); + + /* USER CODE BEGIN ADC1_MspDeInit 1 */ + + /* USER CODE END ADC1_MspDeInit 1 */ + } + +} + +/** +* @brief I2C MSP Initialization +* This function configures the hardware resources used in this example +* @param hi2c: I2C handle pointer +* @retval None +*/ +void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hi2c->Instance==I2C1) + { + /* USER CODE BEGIN I2C1_MspInit 0 */ + + /* USER CODE END I2C1_MspInit 0 */ + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**I2C1 GPIO Configuration + PB6 ------> I2C1_SCL + PB9 ------> I2C1_SDA + */ + GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* Peripheral clock enable */ + __HAL_RCC_I2C1_CLK_ENABLE(); + /* USER CODE BEGIN I2C1_MspInit 1 */ + + /* USER CODE END I2C1_MspInit 1 */ + } + +} + +/** +* @brief I2C MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hi2c: I2C handle pointer +* @retval None +*/ +void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c) +{ + if(hi2c->Instance==I2C1) + { + /* USER CODE BEGIN I2C1_MspDeInit 0 */ + + /* USER CODE END I2C1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_I2C1_CLK_DISABLE(); + + /**I2C1 GPIO Configuration + PB6 ------> I2C1_SCL + PB9 ------> I2C1_SDA + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6|GPIO_PIN_9); + + /* USER CODE BEGIN I2C1_MspDeInit 1 */ + + /* USER CODE END I2C1_MspDeInit 1 */ + } + +} + +/** +* @brief RTC MSP Initialization +* This function configures the hardware resources used in this example +* @param hrtc: RTC handle pointer +* @retval None +*/ +void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) +{ + if(hrtc->Instance==RTC) + { + /* USER CODE BEGIN RTC_MspInit 0 */ + + /* USER CODE END RTC_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_RTC_ENABLE(); + /* USER CODE BEGIN RTC_MspInit 1 */ + + /* USER CODE END RTC_MspInit 1 */ + } + +} + +/** +* @brief RTC MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hrtc: RTC handle pointer +* @retval None +*/ +void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) +{ + if(hrtc->Instance==RTC) + { + /* USER CODE BEGIN RTC_MspDeInit 0 */ + + /* USER CODE END RTC_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_RTC_DISABLE(); + /* USER CODE BEGIN RTC_MspDeInit 1 */ + + /* USER CODE END RTC_MspDeInit 1 */ + } + +} + +/** +* @brief SPI MSP Initialization +* This function configures the hardware resources used in this example +* @param hspi: SPI handle pointer +* @retval None +*/ +void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hspi->Instance==SPI2) + { + /* USER CODE BEGIN SPI2_MspInit 0 */ + + /* USER CODE END SPI2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI2_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**SPI2 GPIO Configuration + PC2 ------> SPI2_MISO + PC3 ------> SPI2_MOSI + PB10 ------> SPI2_SCK + */ + GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI2_MspInit 1 */ + + /* USER CODE END SPI2_MspInit 1 */ + } + +} + +/** +* @brief SPI MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hspi: SPI handle pointer +* @retval None +*/ +void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) +{ + if(hspi->Instance==SPI2) + { + /* USER CODE BEGIN SPI2_MspDeInit 0 */ + + /* USER CODE END SPI2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI2_CLK_DISABLE(); + + /**SPI2 GPIO Configuration + PC2 ------> SPI2_MISO + PC3 ------> SPI2_MOSI + PB10 ------> SPI2_SCK + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_2|GPIO_PIN_3); + + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10); + + /* USER CODE BEGIN SPI2_MspDeInit 1 */ + + /* USER CODE END SPI2_MspDeInit 1 */ + } + +} + +/** +* @brief TIM_Base MSP Initialization +* This function configures the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) +{ + if(htim_base->Instance==TIM2) + { + /* USER CODE BEGIN TIM2_MspInit 0 */ + + /* USER CODE END TIM2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM2_CLK_ENABLE(); + /* USER CODE BEGIN TIM2_MspInit 1 */ + + /* USER CODE END TIM2_MspInit 1 */ + } + else if(htim_base->Instance==TIM11) + { + /* USER CODE BEGIN TIM11_MspInit 0 */ + + /* USER CODE END TIM11_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM11_CLK_ENABLE(); + /* USER CODE BEGIN TIM11_MspInit 1 */ + + /* USER CODE END TIM11_MspInit 1 */ + } + else if(htim_base->Instance==TIM13) + { + /* USER CODE BEGIN TIM13_MspInit 0 */ + + /* USER CODE END TIM13_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM13_CLK_ENABLE(); + /* USER CODE BEGIN TIM13_MspInit 1 */ + + /* USER CODE END TIM13_MspInit 1 */ + } + else if(htim_base->Instance==TIM14) + { + /* USER CODE BEGIN TIM14_MspInit 0 */ + + /* USER CODE END TIM14_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM14_CLK_ENABLE(); + /* USER CODE BEGIN TIM14_MspInit 1 */ + + /* USER CODE END TIM14_MspInit 1 */ + } + +} + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(htim->Instance==TIM2) + { + /* USER CODE BEGIN TIM2_MspPostInit 0 */ + + /* USER CODE END TIM2_MspPostInit 0 */ + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**TIM2 GPIO Configuration + PA3 ------> TIM2_CH4 + */ + GPIO_InitStruct.Pin = GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM2_MspPostInit 1 */ + + /* USER CODE END TIM2_MspPostInit 1 */ + } + +} +/** +* @brief TIM_Base MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base) +{ + if(htim_base->Instance==TIM2) + { + /* USER CODE BEGIN TIM2_MspDeInit 0 */ + + /* USER CODE END TIM2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM2_CLK_DISABLE(); + /* USER CODE BEGIN TIM2_MspDeInit 1 */ + + /* USER CODE END TIM2_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM11) + { + /* USER CODE BEGIN TIM11_MspDeInit 0 */ + + /* USER CODE END TIM11_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM11_CLK_DISABLE(); + /* USER CODE BEGIN TIM11_MspDeInit 1 */ + + /* USER CODE END TIM11_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM13) + { + /* USER CODE BEGIN TIM13_MspDeInit 0 */ + + /* USER CODE END TIM13_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM13_CLK_DISABLE(); + /* USER CODE BEGIN TIM13_MspDeInit 1 */ + + /* USER CODE END TIM13_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM14) + { + /* USER CODE BEGIN TIM14_MspDeInit 0 */ + + /* USER CODE END TIM14_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM14_CLK_DISABLE(); + /* USER CODE BEGIN TIM14_MspDeInit 1 */ + + /* USER CODE END TIM14_MspDeInit 1 */ + } + +} + /** * @brief UART MSP Initialization * This function configures the hardware resources used in this example @@ -106,7 +491,39 @@ void HAL_MspInit(void) void HAL_UART_MspInit(UART_HandleTypeDef* huart) { GPIO_InitTypeDef GPIO_InitStruct = {0}; - if(huart->Instance==USART3) + if(huart->Instance==USART2) + { + /* USER CODE BEGIN USART2_MspInit 0 */ + + /* USER CODE END USART2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USART2_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**USART2 GPIO Configuration + PA2 ------> USART2_TX + PD6 ------> USART2_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART2; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART2; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* USER CODE BEGIN USART2_MspInit 1 */ + + /* USER CODE END USART2_MspInit 1 */ + } + else if(huart->Instance==USART3) { /* USER CODE BEGIN USART3_MspInit 0 */ @@ -141,7 +558,27 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) */ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) { - if(huart->Instance==USART3) + if(huart->Instance==USART2) + { + /* USER CODE BEGIN USART2_MspDeInit 0 */ + + /* USER CODE END USART2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART2_CLK_DISABLE(); + + /**USART2 GPIO Configuration + PA2 ------> USART2_TX + PD6 ------> USART2_RX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2); + + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_6); + + /* USER CODE BEGIN USART2_MspDeInit 1 */ + + /* USER CODE END USART2_MspDeInit 1 */ + } + else if(huart->Instance==USART3) { /* USER CODE BEGIN USART3_MspDeInit 0 */ diff --git a/bsp/stm32/stm32f413-st-nucleo/board/Kconfig b/bsp/stm32/stm32f413-st-nucleo/board/Kconfig index ff025ae50e37f352d3e7c90116b0d7774b600a1e..d4c25d61751b451369e0271a8366bc94b0ddbdb3 100644 --- a/bsp/stm32/stm32f413-st-nucleo/board/Kconfig +++ b/bsp/stm32/stm32f413-st-nucleo/board/Kconfig @@ -35,7 +35,7 @@ menu "On-chip Peripheral Drivers" bool "Enable UART2 RX DMA" depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA default n - + config BSP_USING_UART3 bool "Enable UART3" default y @@ -44,7 +44,113 @@ menu "On-chip Peripheral Drivers" depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA default n endif + + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI2 + bool "Enable SPI2 BUS" + default n + + config BSP_SPI2_TX_USING_DMA + bool "Enable SPI2 TX DMA" + depends on BSP_USING_SPI2 + default n + + config BSP_SPI2_RX_USING_DMA + bool "Enable SPI2 RX DMA" + depends on BSP_USING_SPI2 + select BSP_SPI2_TX_USING_DMA + default n + + endif + + menuconfig BSP_USING_I2C1 + bool "Enable I2C1 BUS (software simulation)" + default n + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C1 + comment "Notice: PB6 --> 136; PB9 --> 140" + config BSP_I2C1_SCL_PIN + int "I2C1 scl pin number" + range 1 144 + default 136 + config BSP_I2C1_SDA_PIN + int "I2C1 sda pin number" + range 1 144 + default 140 + endif + + menuconfig BSP_USING_TIM + bool "Enable timer" + default n + select RT_USING_HWTIMER + if BSP_USING_TIM + config BSP_USING_TIM11 + bool "Enable TIM11" + default n + config BSP_USING_TIM13 + bool "Enable TIM13" + default n + + config BSP_USING_TIM14 + bool "Enable TIM14" + default n + endif + + menuconfig BSP_USING_PWM + bool "Enable pwm" + default n + select RT_USING_PWM + if BSP_USING_PWM + menuconfig BSP_USING_PWM2 + bool "Enable timer2 output pwm" + default n + if BSP_USING_PWM2 + config BSP_USING_PWM2_CH4 + bool "Enable PWM2 channel4" + default n + endif + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + endif + + menuconfig BSP_USING_ONCHIP_RTC + bool "Enable RTC" + select RT_USING_RTC + select RT_USING_LIBC + default n + if BSP_USING_ONCHIP_RTC + choice + prompt "Select clock source" + default BSP_RTC_USING_LSE + + config BSP_RTC_USING_LSE + bool "RTC USING LSE" + + config BSP_RTC_USING_LSI + bool "RTC USING LSI" + endchoice + endif + + config BSP_USING_WDT + bool "Enable Watchdog Timer" + select RT_USING_WDT + default n + config BSP_USING_ON_CHIP_FLASH bool "Enable on-chip FLASH" default n diff --git a/bsp/stm32/stm32f413-st-nucleo/board/board.c b/bsp/stm32/stm32f413-st-nucleo/board/board.c index b63870d40cad09ad7d74a3f835bee2cccc527ca7..dffc5bba4013d896d98bc392983193439904749c 100644 --- a/bsp/stm32/stm32f413-st-nucleo/board/board.c +++ b/bsp/stm32/stm32f413-st-nucleo/board/board.c @@ -26,8 +26,9 @@ void SystemClock_Config(void) __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); /** Initializes the CPU, AHB and APB busses clocks */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PLLM = 8; @@ -52,7 +53,8 @@ void SystemClock_Config(void) { Error_Handler(); } - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLQ; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { diff --git a/bsp/stm32/stm32f413-st-nucleo/project.ewp b/bsp/stm32/stm32f413-st-nucleo/project.ewp index 1f62f5577d69d40f4816595adaed21cf5e5a003f..9fc1c540d247dccf977efc487d6549ac00ebcc08 100644 --- a/bsp/stm32/stm32f413-st-nucleo/project.ewp +++ b/bsp/stm32/stm32f413-st-nucleo/project.ewp @@ -2180,6 +2180,9 @@ $PROJ_DIR$\..\..\..\components\drivers\src\workqueue.c + + $PROJ_DIR$\..\..\..\components\drivers\watchdog\watchdog.c + finsh @@ -2252,5 +2255,11 @@ $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_usart.c + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_iwdg.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_wwdg.c + diff --git a/bsp/stm32/stm32f413-st-nucleo/project.uvopt b/bsp/stm32/stm32f413-st-nucleo/project.uvopt index 68d5d3a75c5216aa732668e42df35f4cfc125415..b53d69d5df5ff8a1a7be279244e1c44ee327bfc0 100644 --- a/bsp/stm32/stm32f413-st-nucleo/project.uvopt +++ b/bsp/stm32/stm32f413-st-nucleo/project.uvopt @@ -71,21 +71,11 @@ 0 - 1 + 0 0 1 255 - - SARMCM3.DLL - -MPU -REMAP - DCM.DLL - -pCM4 - SARMCM3.DLL - -MPU - TCM.DLL - -pCM4 - 0 1 @@ -104,9 +94,12 @@ 0 1 0 + 1 + 1 + 0 0 0 - 7 + 6 @@ -132,6 +125,9 @@ + + 0 + 0 0 @@ -158,972 +154,9 @@ 0 0 - - 0 - - - Kernel - 0 - 0 - 0 - 0 - - 1 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\src\clock.c - clock.c - 0 - 0 - - - 1 - 2 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\src\components.c - components.c - 0 - 0 - - - 1 - 3 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\src\device.c - device.c - 0 - 0 - - - 1 - 4 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\src\idle.c - idle.c - 0 - 0 - - - 1 - 5 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\src\ipc.c - ipc.c - 0 - 0 - - - 1 - 6 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\src\irq.c - irq.c - 0 - 0 - - - 1 - 7 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\src\kservice.c - kservice.c - 0 - 0 - - - 1 - 8 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\src\mem.c - mem.c - 0 - 0 - - - 1 - 9 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\src\mempool.c - mempool.c - 0 - 0 - - - 1 - 10 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\src\object.c - object.c - 0 - 0 - - - 1 - 11 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\src\scheduler.c - scheduler.c - 0 - 0 - - - 1 - 12 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\src\signal.c - signal.c - 0 - 0 - - - 1 - 13 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\src\thread.c - thread.c - 0 - 0 - - - 1 - 14 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\src\timer.c - timer.c - 0 - 0 - - - - - Applications - 1 - 0 - 0 - 0 - - 2 - 15 - 1 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - applications\main.c - main.c - 0 - 0 - - - - - Drivers - 0 - 0 - 0 - 0 - - 3 - 16 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - board\board.c - board.c - 0 - 0 - - - 3 - 17 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - board\CubeMX_Config\Src\stm32f4xx_hal_msp.c - stm32f4xx_hal_msp.c - 0 - 0 - - - 3 - 18 - 2 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\arm\startup_stm32f413xx.s - startup_stm32f413xx.s - 0 - 0 - - - 3 - 19 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\libraries\HAL_Drivers\drv_gpio.c - drv_gpio.c - 0 - 0 - - - 3 - 20 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\libraries\HAL_Drivers\drv_usart.c - drv_usart.c - 0 - 0 - - - 3 - 21 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\libraries\HAL_Drivers\drv_common.c - drv_common.c - 0 - 0 - - - - - cpu - 0 - 0 - 0 - 0 - - 4 - 22 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\libcpu\arm\common\backtrace.c - backtrace.c - 0 - 0 - - - 4 - 23 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\libcpu\arm\common\div0.c - div0.c - 0 - 0 - - - 4 - 24 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\libcpu\arm\common\showmem.c - showmem.c - 0 - 0 - - - 4 - 25 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\libcpu\arm\cortex-m4\cpuport.c - cpuport.c - 0 - 0 - - - 4 - 26 - 2 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\libcpu\arm\cortex-m4\context_rvds.S - context_rvds.S - 0 - 0 - - - - - DeviceDrivers - 0 - 0 - 0 - 0 - - 5 - 27 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\components\drivers\misc\pin.c - pin.c - 0 - 0 - - - 5 - 28 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\components\drivers\serial\serial.c - serial.c - 0 - 0 - - - 5 - 29 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\components\drivers\src\completion.c - completion.c - 0 - 0 - - - 5 - 30 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\components\drivers\src\dataqueue.c - dataqueue.c - 0 - 0 - - - 5 - 31 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\components\drivers\src\pipe.c - pipe.c - 0 - 0 - - - 5 - 32 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\components\drivers\src\ringblk_buf.c - ringblk_buf.c - 0 - 0 - - - 5 - 33 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\components\drivers\src\ringbuffer.c - ringbuffer.c - 0 - 0 - - - 5 - 34 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\components\drivers\src\waitqueue.c - waitqueue.c - 0 - 0 - - - 5 - 35 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\components\drivers\src\workqueue.c - workqueue.c - 0 - 0 - - - - - finsh - 0 - 0 - 0 - 0 - - 6 - 36 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\components\finsh\shell.c - shell.c - 0 - 0 - - - 6 - 37 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\components\finsh\cmd.c - cmd.c - 0 - 0 - - - 6 - 38 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\components\finsh\msh.c - msh.c - 0 - 0 - - - - - libc - 0 - 0 - 0 - 0 - - 7 - 39 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\components\libc\compilers\common\time.c - time.c - 0 - 0 - - - - - STM32_HAL - 0 - 0 - 0 - 0 - - 8 - 40 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c - system_stm32f4xx.c - 0 - 0 - - - 8 - 41 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c - stm32f4xx_hal.c - 0 - 0 - - - 8 - 42 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cec.c - stm32f4xx_hal_cec.c - 0 - 0 - - - 8 - 43 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c - stm32f4xx_hal_cortex.c - 0 - 0 - - - 8 - 44 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_crc.c - stm32f4xx_hal_crc.c - 0 - 0 - - - 8 - 45 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp.c - stm32f4xx_hal_cryp.c - 0 - 0 - - - 8 - 46 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp_ex.c - stm32f4xx_hal_cryp_ex.c - 0 - 0 - - - 8 - 47 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c - stm32f4xx_hal_dma.c - 0 - 0 - - - 8 - 48 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c - stm32f4xx_hal_dma_ex.c - 0 - 0 - - - 8 - 49 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c - stm32f4xx_hal_pwr.c - 0 - 0 - - - 8 - 50 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c - stm32f4xx_hal_pwr_ex.c - 0 - 0 - - - 8 - 51 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c - stm32f4xx_hal_rcc.c - 0 - 0 - - - 8 - 52 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c - stm32f4xx_hal_rcc_ex.c - 0 - 0 - - - 8 - 53 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rng.c - stm32f4xx_hal_rng.c - 0 - 0 - - - 8 - 54 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c - stm32f4xx_hal_gpio.c - 0 - 0 - - - 8 - 55 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c - stm32f4xx_hal_uart.c - 0 - 0 - - - 8 - 56 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_usart.c - stm32f4xx_hal_usart.c - 0 - 0 - - - diff --git a/bsp/stm32/stm32f413-st-nucleo/project.uvoptx b/bsp/stm32/stm32f413-st-nucleo/project.uvoptx index 0253b47b87098c7842d5572307aa9f37ae0990d5..0c839365312fbdd4460702ce2eb5638d0104d08e 100644 --- a/bsp/stm32/stm32f413-st-nucleo/project.uvoptx +++ b/bsp/stm32/stm32f413-st-nucleo/project.uvoptx @@ -73,7 +73,7 @@ 0 - 0 + 1 0 1 @@ -140,7 +140,7 @@ 0 ST-LINKIII-KEIL_SWO - -U-O206 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P2 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1536.FLM -FS08000000 -FL0180000 -FP0($$Device:STM32F413ZHTx$CMSIS\Flash\STM32F4xx_1536.FLM) + -U-O206 -O206 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P2 -N00("ARM CoreSight SW-DP (ARM Core") -D00(2BA01477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1536.FLM -FS08000000 -FL0180000 -FP0($$Device:STM32F413ZHTx$CMSIS\Flash\STM32F4xx_1536.FLM) 0 @@ -198,6 +198,7 @@ 1 + 0 0 2 10000000 @@ -663,6 +664,18 @@ 0 0 + + 5 + 36 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\watchdog\watchdog.c + watchdog.c + 0 + 0 + @@ -673,7 +686,7 @@ 0 6 - 36 + 37 1 0 0 @@ -685,7 +698,7 @@ 6 - 37 + 38 1 0 0 @@ -697,7 +710,7 @@ 6 - 38 + 39 1 0 0 @@ -717,7 +730,7 @@ 0 7 - 39 + 40 1 0 0 @@ -737,7 +750,7 @@ 0 8 - 40 + 41 1 0 0 @@ -749,7 +762,7 @@ 8 - 41 + 42 1 0 0 @@ -761,7 +774,7 @@ 8 - 42 + 43 1 0 0 @@ -773,7 +786,7 @@ 8 - 43 + 44 1 0 0 @@ -785,7 +798,7 @@ 8 - 44 + 45 1 0 0 @@ -797,7 +810,7 @@ 8 - 45 + 46 1 0 0 @@ -809,7 +822,7 @@ 8 - 46 + 47 1 0 0 @@ -821,7 +834,7 @@ 8 - 47 + 48 1 0 0 @@ -833,7 +846,7 @@ 8 - 48 + 49 1 0 0 @@ -845,7 +858,7 @@ 8 - 49 + 50 1 0 0 @@ -857,7 +870,7 @@ 8 - 50 + 51 1 0 0 @@ -869,7 +882,7 @@ 8 - 51 + 52 1 0 0 @@ -881,7 +894,7 @@ 8 - 52 + 53 1 0 0 @@ -893,7 +906,7 @@ 8 - 53 + 54 1 0 0 @@ -905,7 +918,7 @@ 8 - 54 + 55 1 0 0 @@ -917,7 +930,7 @@ 8 - 55 + 56 1 0 0 @@ -929,7 +942,7 @@ 8 - 56 + 57 1 0 0 @@ -939,6 +952,30 @@ 0 0 + + 8 + 58 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_iwdg.c + stm32f4xx_hal_iwdg.c + 0 + 0 + + + 8 + 59 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_wwdg.c + stm32f4xx_hal_wwdg.c + 0 + 0 + diff --git a/bsp/stm32/stm32f413-st-nucleo/project.uvproj b/bsp/stm32/stm32f413-st-nucleo/project.uvproj index 5b4ca2796b8d3cdf2c6d56e1e883cae4d8e7b940..f87c223adc043f9ea9559c9294b0941380bbd8f5 100644 --- a/bsp/stm32/stm32f413-st-nucleo/project.uvproj +++ b/bsp/stm32/stm32f413-st-nucleo/project.uvproj @@ -1,10 +1,7 @@ - 1.1 -
### uVision Project, (C) Keil Software
- rt-thread @@ -15,25 +12,26 @@ STM32F407ZG STMicroelectronics IRAM(0x20000000-0x2001FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) CPUTYPE("Cortex-M4") FPU2 - + "Startup\ST\STM32F4xx\startup_stm32f40_41xxx.s" ("STM32F40/41xxx Startup Code") UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000) 6105 stm32f4xx.h - - - - - - + + + + + + -DSTM32F40_41xxx - - + + SFD\ST\STM32F4xx\STM32F40x.sfr + 0 0 - - - + + + ST\STM32F4xx\ ST\STM32F4xx\ @@ -57,8 +55,8 @@ 0 0 - - + + 0 0 0 @@ -67,8 +65,8 @@ 0 0 - - + + 0 0 @@ -76,12 +74,12 @@ 1 0 fromelf --bin !L --output rtthread.bin - + 0 0 0 - + 0 @@ -95,8 +93,9 @@ 0 0 3 - - + + + 1 SARMCM3.DLL @@ -126,6 +125,7 @@ 1 1 0 + 1 1 @@ -137,22 +137,24 @@ 0 1 0 + 1 + 0 0 - 7 + 6 - - - - - + + + + + - - - - - + + + + + Segger\JL2CM3.dll @@ -165,9 +167,14 @@ 1 4096 + 1 BIN\UL2CM3.DLL "" () - + + + + + 0 @@ -199,7 +206,7 @@ 0 0 "Cortex-M4" - + 0 0 0 @@ -330,7 +337,7 @@ 0x10000 - + 1 @@ -346,11 +353,13 @@ 0 0 0 + 1 + 0 - + USE_HAL_DRIVER, STM32F413xx - - .;..\..\..\include;applications;.;board;board\CubeMX_Config\Inc;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\common;..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Inc;..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Include;..\libraries\STM32F4xx_HAL\CMSIS\Include + + .;..\..\..\include;applications;.;board;board\CubeMX_Config\Inc;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\common;..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Inc;..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Include;..\libraries\STM32F4xx_HAL\CMSIS\Include @@ -362,11 +371,12 @@ 0 0 0 + 0 - - - - + + + + @@ -378,12 +388,13 @@ 0 0x08000000 0x20000000 + .\board\linker_scripts\link.sct - - - - - + + + + + @@ -396,66 +407,92 @@ 1 ..\..\..\src\clock.c + + components.c 1 ..\..\..\src\components.c + + device.c 1 ..\..\..\src\device.c + + idle.c 1 ..\..\..\src\idle.c + + ipc.c 1 ..\..\..\src\ipc.c + + irq.c 1 ..\..\..\src\irq.c + + kservice.c 1 ..\..\..\src\kservice.c + + mem.c 1 ..\..\..\src\mem.c + + mempool.c 1 ..\..\..\src\mempool.c + + object.c 1 ..\..\..\src\object.c + + scheduler.c 1 ..\..\..\src\scheduler.c + + signal.c 1 ..\..\..\src\signal.c + + thread.c 1 ..\..\..\src\thread.c + + timer.c 1 @@ -481,26 +518,36 @@ 1 board\board.c + + stm32f4xx_hal_msp.c 1 board\CubeMX_Config\Src\stm32f4xx_hal_msp.c + + startup_stm32f413xx.s 2 ..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\arm\startup_stm32f413xx.s + + drv_gpio.c 1 ..\libraries\HAL_Drivers\drv_gpio.c + + drv_usart.c 1 ..\libraries\HAL_Drivers\drv_usart.c + + drv_common.c 1 @@ -516,21 +563,29 @@ 1 ..\..\..\libcpu\arm\common\backtrace.c + + div0.c 1 ..\..\..\libcpu\arm\common\div0.c + + showmem.c 1 ..\..\..\libcpu\arm\common\showmem.c + + cpuport.c 1 ..\..\..\libcpu\arm\cortex-m4\cpuport.c + + context_rvds.S 2 @@ -546,47 +601,70 @@ 1 ..\..\..\components\drivers\misc\pin.c + + serial.c 1 ..\..\..\components\drivers\serial\serial.c + + completion.c 1 ..\..\..\components\drivers\src\completion.c + + dataqueue.c 1 ..\..\..\components\drivers\src\dataqueue.c + + pipe.c 1 ..\..\..\components\drivers\src\pipe.c + + ringblk_buf.c 1 ..\..\..\components\drivers\src\ringblk_buf.c + + ringbuffer.c 1 ..\..\..\components\drivers\src\ringbuffer.c + + waitqueue.c 1 ..\..\..\components\drivers\src\waitqueue.c + + workqueue.c 1 ..\..\..\components\drivers\src\workqueue.c + + + watchdog.c + 1 + ..\..\..\components\drivers\watchdog\watchdog.c + + finsh @@ -596,11 +674,15 @@ 1 ..\..\..\components\finsh\shell.c + + cmd.c 1 ..\..\..\components\finsh\cmd.c + + msh.c 1 @@ -626,90 +708,135 @@ 1 ..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c + + stm32f4xx_hal.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c + + stm32f4xx_hal_cec.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cec.c + + stm32f4xx_hal_cortex.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c + + stm32f4xx_hal_crc.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_crc.c + + stm32f4xx_hal_cryp.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp.c + + stm32f4xx_hal_cryp_ex.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp_ex.c + + stm32f4xx_hal_dma.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c + + stm32f4xx_hal_dma_ex.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c + + stm32f4xx_hal_pwr.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c + + stm32f4xx_hal_pwr_ex.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c + + stm32f4xx_hal_rcc.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c + + stm32f4xx_hal_rcc_ex.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c + + stm32f4xx_hal_rng.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rng.c + + stm32f4xx_hal_gpio.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c + + stm32f4xx_hal_uart.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c + + stm32f4xx_hal_usart.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_usart.c + + + stm32f4xx_hal_iwdg.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_iwdg.c + + + + + stm32f4xx_hal_wwdg.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_wwdg.c + + - diff --git a/bsp/stm32/stm32f413-st-nucleo/project.uvprojx b/bsp/stm32/stm32f413-st-nucleo/project.uvprojx index 162413e210a2753239b96f81df53d8b688ab8e90..5069e31cf2e115571cc37a58b2634e30c1a9e3e9 100644 --- a/bsp/stm32/stm32f413-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32f413-st-nucleo/project.uvprojx @@ -10,14 +10,14 @@ rt-thread 0x4 ARM-ADS - 5060750::V5.06 update 6 (build 750)::ARMCC + 5060750::V5.06 update 6 (build 750)::.\ARMCC 0 STM32F413ZHTx STMicroelectronics - Keil.STM32F4xx_DFP.2.13.0 - http://www.keil.com/pack + Keil.STM32F4xx_DFP.2.14.0 + http://www.keil.com/pack/ IRAM(0x20000000,0x00050000) IROM(0x08000000,0x00180000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -184,6 +184,8 @@ 0 0 2 + 0 + 0 0 0 8 @@ -337,7 +339,7 @@ USE_HAL_DRIVER, STM32F413xx - .;..\..\..\include;applications;.;board;board\CubeMX_Config\Inc;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\common;..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Inc;..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Include;..\libraries\STM32F4xx_HAL\CMSIS\Include + .;..\..\..\include;applications;.;board;board\CubeMX_Config\Inc;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\common;..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Inc;..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Include;..\libraries\STM32F4xx_HAL\CMSIS\Include @@ -350,7 +352,7 @@ 0 0 0 - 0 + 4 @@ -576,6 +578,11 @@ 1 ..\..\..\components\drivers\src\workqueue.c + + watchdog.c + 1 + ..\..\..\components\drivers\watchdog\watchdog.c + @@ -696,6 +703,16 @@ 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_usart.c + + stm32f4xx_hal_iwdg.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_iwdg.c + + + stm32f4xx_hal_wwdg.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_wwdg.c + @@ -708,4 +725,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/bsp/stm32/stm32f413-st-nucleo/rtconfig.h b/bsp/stm32/stm32f413-st-nucleo/rtconfig.h index 8ddb790c4eccbf4f5b62f13f994f0fcc0be992e2..2f81c11ed6d67e9a3f94c25c6d9a6c25ce5c431e 100644 --- a/bsp/stm32/stm32f413-st-nucleo/rtconfig.h +++ b/bsp/stm32/stm32f413-st-nucleo/rtconfig.h @@ -82,6 +82,7 @@ #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_PIN +#define RT_USING_WDT /* Using USB */ diff --git a/bsp/stm32/stm32f413-st-nucleo/template.uvoptx b/bsp/stm32/stm32f413-st-nucleo/template.uvoptx index f170007195a599326fed7e72e818fcd3f6c66a24..7384c8aaf0a6e32d093bdbdfc99baa3bd34c9afc 100644 --- a/bsp/stm32/stm32f413-st-nucleo/template.uvoptx +++ b/bsp/stm32/stm32f413-st-nucleo/template.uvoptx @@ -73,7 +73,7 @@ 0 - 0 + 1 0 1 @@ -120,7 +120,7 @@ 0 ST-LINKIII-KEIL_SWO - -U-O206 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P2 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1536.FLM -FS08000000 -FL0180000 -FP0($$Device:STM32F413ZHTx$CMSIS\Flash\STM32F4xx_1536.FLM) + -U-O206 -O206 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P2 -N00("") -D00(00000000) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1536.FLM -FS08000000 -FL0180000 -FP0($$Device:STM32F413ZHTx$CMSIS\Flash\STM32F4xx_1536.FLM) 0 @@ -178,6 +178,7 @@ 1 + 0 0 2 10000000 diff --git a/bsp/stm32/stm32f413-st-nucleo/template.uvprojx b/bsp/stm32/stm32f413-st-nucleo/template.uvprojx index 6b03ebbbb96f431fea2baecf8a69c48706d57cf0..76b1b588e9a365000ba85a4ebd225e6ab6274924 100644 --- a/bsp/stm32/stm32f413-st-nucleo/template.uvprojx +++ b/bsp/stm32/stm32f413-st-nucleo/template.uvprojx @@ -16,8 +16,8 @@ STM32F413ZHTx STMicroelectronics - Keil.STM32F4xx_DFP.2.13.0 - http://www.keil.com/pack + Keil.STM32F4xx_DFP.2.14.0 + http://www.keil.com/pack/ IRAM(0x20000000,0x00050000) IROM(0x08000000,0x00180000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -184,6 +184,8 @@ 0 0 2 + 0 + 0 0 0 8 @@ -350,7 +352,7 @@ 0 0 0 - 0 + 4 @@ -391,4 +393,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/bsp/stm32/stm32g070-st-nucleo/.config b/bsp/stm32/stm32g070-st-nucleo/.config new file mode 100644 index 0000000000000000000000000000000000000000..8c3da02cd28c413a61c2f639398766b6151606d7 --- /dev/null +++ b/bsp/stm32/stm32g070-st-nucleo/.config @@ -0,0 +1,453 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart2" +CONFIG_RT_VER_NUM=0x40003 +CONFIG_ARCH_ARM=y +# CONFIG_RT_USING_CPU_FFS is not set +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M0=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +# CONFIG_RT_USING_LIBC is not set +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_LIBC_USING_TIME=y + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_LWP is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_URLENCODE is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +CONFIG_SOC_FAMILY_STM32=y +CONFIG_SOC_SERIES_STM32G0=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_STM32G070RB=y + +# +# Onboard Peripheral Drivers +# +CONFIG_BSP_USING_USB_TO_UART=y + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +# CONFIG_BSP_USING_UART1 is not set +CONFIG_BSP_USING_UART2=y +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_TIM is not set +# CONFIG_BSP_USING_PWM is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_I2C1 is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_ON_CHIP_FLASH is not set +# CONFIG_BSP_USING_ONCHIP_RTC is not set +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_UDID is not set + +# +# Board extended module Drivers +# diff --git a/bsp/stm32/stm32g070-st-nucleo/.gitignore b/bsp/stm32/stm32g070-st-nucleo/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..d45e936a4a4694c1571ea5fc656d99f96127737b --- /dev/null +++ b/bsp/stm32/stm32g070-st-nucleo/.gitignore @@ -0,0 +1,7 @@ +settings +build + +*.uvguix.* +*.uvoptx +settings/* +build/* diff --git a/bsp/stm32/stm32g070-st-nucleo/Kconfig b/bsp/stm32/stm32g070-st-nucleo/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..79b160b856783cfaea4fc056458bc193e16f13d2 --- /dev/null +++ b/bsp/stm32/stm32g070-st-nucleo/Kconfig @@ -0,0 +1,21 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" +source "board/Kconfig" diff --git a/bsp/stm32/stm32g070-st-nucleo/README.md b/bsp/stm32/stm32g070-st-nucleo/README.md new file mode 100644 index 0000000000000000000000000000000000000000..b221d5e6d2462942215e4fb77bd1f82edf600d59 --- /dev/null +++ b/bsp/stm32/stm32g070-st-nucleo/README.md @@ -0,0 +1,116 @@ +# STM32G071 BSP + +## 简介 + +本文档为 STM32G070RB-Nucleo 开发板的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +STM32G070RB-Nucleo 开发板是 ST 官方推出的一款基于 ARM Cortex-M0+ 内核的开发板，最高主频为 64Mhz，该开发板具有丰富的扩展接口，可以方便验证 STM32G070RB 的芯片性能。 + +开发板外观如下图所示： + +![board](figures/board.jpg) + +该开发板常用 **板载资源** 如下： + +- MCU：STM32G070RB，主频 64MHz，128KB FLASH ，36KB RAM +- 外部 RAM：无 +- 外部 FLASH：无 +- 常用外设 + - 按键：1个，user（兼具唤醒功能，PC13） +- 常用接口：USB 转串口、arduino 接口等 +- 调试接口，标准 SWD + +开发板更多详细信息请参考 ST 的 [NUCLEO 开发板介绍](https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-eval-tools/stm32-mcu-eval-tools/stm32-mcu-nucleo/nucleo-g070rb.html)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :----------------- | :----------: | :------------------------------------- | +| ST-LINK 虚拟串口 | 支持 | 使用 USART2 | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | PA0, PA1... PC15 ---> PIN: 0, 1...47 | +| UART | 支持 | USART1/2/3 | +| TIM | 支持 | TIM1/3 | +| PWM | 支持 | | +| SPI | 支持 | SPI1/2 | +| I2C | 支持 | 软件 I2C | +| ADC | 支持 | | +| WDT | 支持 | | +| FLASH | 支持 | 已适配 [FAL](https://github.com/RT-Thread-packages/fal) | +| RTC | 暂不支持 | 详见注意事项 | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + +### 快速上手 + +本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用数据线连接开发板到 PC，打开电源开关。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 将工程使用的仿真器设置为ST-Link并安装仿真器好驱动程序以后，将开发板连接到PC，点击下载按钮即可下载程序到开发板。 + +#### 运行结果 + +下载程序成功之后，系统会自动运行。 + +连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.2 build Jul 1 2020 + 2006 - 2019 Copyright by rt-thread team +msh > +``` + +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 UART 的功能，如果需使用 SPI，I2C 等更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk5/iar` 命令重新生成工程。 + +本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 + +## 注意事项 + +- G0系列RTC驱动有点问题，详见论坛 [该贴](https://www.rt-thread.org/qa/thread-424601-1-2.html) + +## 联系人信息 + +维护人: + +- [NU-LL](https://github.com/NU-LL) diff --git a/bsp/stm32/stm32g070-st-nucleo/SConscript b/bsp/stm32/stm32g070-st-nucleo/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..20f7689c53ca71a676748f79187f9764065466c5 --- /dev/null +++ b/bsp/stm32/stm32g070-st-nucleo/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/stm32/stm32g070-st-nucleo/SConstruct b/bsp/stm32/stm32g070-st-nucleo/SConstruct new file mode 100644 index 0000000000000000000000000000000000000000..96fd191077eeca7036e04d4314ebcd6d0f9e8746 --- /dev/null +++ b/bsp/stm32/stm32g070-st-nucleo/SConstruct @@ -0,0 +1,60 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rt-thread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +stm32_library = 'STM32G0xx_HAL' +rtconfig.BSP_LIBRARY_TYPE = stm32_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, stm32_library, 'SConscript'))) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/stm32/stm32g070-st-nucleo/applications/SConscript b/bsp/stm32/stm32g070-st-nucleo/applications/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..e08e694fafffc60d2923d1bfb217327cb5499b9a --- /dev/null +++ b/bsp/stm32/stm32g070-st-nucleo/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = os.path.join(str(Dir('#')), 'applications') +src = Glob('*.c') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/stm32/stm32g070-st-nucleo/applications/main.c b/bsp/stm32/stm32g070-st-nucleo/applications/main.c new file mode 100644 index 0000000000000000000000000000000000000000..8541bd3b9fc6971e6535a430dfe96ea417e16152 --- /dev/null +++ b/bsp/stm32/stm32g070-st-nucleo/applications/main.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-06 SummerGift change to new framework + */ + +#include +#include +#include + +/* defined the LED pin: PA5 */ +#define LED0_PIN GET_PIN(A, 5) + +int main(void) +{ + int count = 1; + /* set LED0 pin mode to output */ + rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); + + while (count++) + { + rt_pin_write(LED0_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED0_PIN, PIN_LOW); + rt_thread_mdelay(500); + } + + return RT_EOK; +} diff --git a/bsp/stm32/stm32g070-st-nucleo/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32g070-st-nucleo/board/CubeMX_Config/.mxproject new file mode 100644 index 0000000000000000000000000000000000000000..03293ddd2ac6bad34bd378d1deca0726d7f9659b --- /dev/null +++ b/bsp/stm32/stm32g070-st-nucleo/board/CubeMX_Config/.mxproject @@ -0,0 +1,12 @@ +[PreviousGenFiles] +HeaderPath=G:/1 Code/STM32/stm32g070-st-nucleo-doorcontroler/board/CubeMX_Config/Inc +HeaderFiles=stm32g0xx_it.h;stm32g0xx_hal_conf.h;main.h; +SourcePath=G:/1 Code/STM32/stm32g070-st-nucleo-doorcontroler/board/CubeMX_Config/Src +SourceFiles=stm32g0xx_it.c;stm32g0xx_hal_msp.c;main.c; + +[PreviousLibFiles] +LibFiles=Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_adc.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ramfunc.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h;Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_iwdg.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rtc.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rtc_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_spi.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_spi_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_system.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_wwdg.h;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc_ex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_adc.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_iwdg.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rtc.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rtc_ex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_spi.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_spi_ex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart_ex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_wwdg.c;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_adc.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ramfunc.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h;Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_iwdg.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rtc.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rtc_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_spi.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_spi_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_system.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_wwdg.h;Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g070xx.h;Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h;Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h;Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/system_stm32g0xx.c; + +[] +SourceFiles=;; + diff --git a/bsp/stm32/stm32g070-st-nucleo/board/CubeMX_Config/Inc/main.h b/bsp/stm32/stm32g070-st-nucleo/board/CubeMX_Config/Inc/main.h new file mode 100644 index 0000000000000000000000000000000000000000..8e41b0243d6d644cc4a345697e2edfb25438967e --- /dev/null +++ b/bsp/stm32/stm32g070-st-nucleo/board/CubeMX_Config/Inc/main.h @@ -0,0 +1,82 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" +#include "stm32g0xx_ll_system.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +#define MCO_Pin GPIO_PIN_0 +#define MCO_GPIO_Port GPIOF +#define LED_GREEN_Pin GPIO_PIN_5 +#define LED_GREEN_GPIO_Port GPIOA +#define TMS_Pin GPIO_PIN_13 +#define TMS_GPIO_Port GPIOA +#define TCK_Pin GPIO_PIN_14 +#define TCK_GPIO_Port GPIOA +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32g070-st-nucleo/board/CubeMX_Config/Inc/stm32g0xx_hal_conf.h b/bsp/stm32/stm32g070-st-nucleo/board/CubeMX_Config/Inc/stm32g0xx_hal_conf.h new file mode 100644 index 0000000000000000000000000000000000000000..2b8cebd87e138130c56e4f36ac0f330efa9be647 --- /dev/null +++ b/bsp/stm32/stm32g070-st-nucleo/board/CubeMX_Config/Inc/stm32g0xx_hal_conf.h @@ -0,0 +1,310 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_CONF_H +#define STM32G0xx_HAL_CONF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED + + #define HAL_ADC_MODULE_ENABLED +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_COMP_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_EXTI_MODULE_ENABLED */ +/* #define HAL_I2C_MODULE_ENABLED */ +/* #define HAL_I2S_MODULE_ENABLED */ +#define HAL_IWDG_MODULE_ENABLED +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_RNG_MODULE_ENABLED */ +#define HAL_RTC_MODULE_ENABLED +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIM_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +/* #define HAL_USART_MODULE_ENABLED */ +#define HAL_WWDG_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## Register Callbacks selection ############################## */ +/** + * @brief This is the list of modules where register callback can be used + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0u +#define USE_HAL_CEC_REGISTER_CALLBACKS 0u +#define USE_HAL_COMP_REGISTER_CALLBACKS 0u +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0u +#define USE_HAL_DAC_REGISTER_CALLBACKS 0u +#define USE_HAL_I2C_REGISTER_CALLBACKS 0u +#define USE_HAL_I2S_REGISTER_CALLBACKS 0u +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0u +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0u +#define USE_HAL_RNG_REGISTER_CALLBACKS 0u +#define USE_HAL_RTC_REGISTER_CALLBACKS 0u +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0u +#define USE_HAL_SPI_REGISTER_CALLBACKS 0u +#define USE_HAL_TIM_REGISTER_CALLBACKS 0u +#define USE_HAL_UART_REGISTER_CALLBACKS 0u +#define USE_HAL_USART_REGISTER_CALLBACKS 0u +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0u + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) +#define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz +The real value may vary depending on the variations +in voltage and temperature.*/ +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768U /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S1 peripheral + * This value is used by the RCC HAL module to compute the I2S1 clock source + * frequency. + */ +#if !defined (EXTERNAL_I2S1_CLOCK_VALUE) +#define EXTERNAL_I2S1_CLOCK_VALUE 12288000U /*!< Value of the I2S1 External clock source in Hz*/ +#endif /* EXTERNAL_I2S1_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE 3300U /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY 0U /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U +#define INSTRUCTION_CACHE_ENABLE 1U + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* ################## CRYP peripheral configuration ########################## */ + +#define USE_HAL_CRYP_SUSPEND_RESUME 1U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED +#include "stm32g0xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED +#include "stm32g0xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED +#include "stm32g0xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED +#include "stm32g0xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED +#include "stm32g0xx_hal_adc.h" +#include "stm32g0xx_hal_adc_ex.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED +#include "stm32g0xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED +#include "stm32g0xx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED +#include "stm32g0xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED +#include "stm32g0xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED +#include "stm32g0xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED +#include "stm32g0xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED +#include "stm32g0xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED +#include "stm32g0xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED +#include "stm32g0xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED +#include "stm32g0xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED +#include "stm32g0xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED +#include "stm32g0xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED +#include "stm32g0xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED +#include "stm32g0xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED +#include "stm32g0xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED +#include "stm32g0xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED +#include "stm32g0xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED +#include "stm32g0xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED +#include "stm32g0xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED +#include "stm32g0xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED +#include "stm32g0xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED +#include "stm32g0xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for functions parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void assert_failed(uint8_t *file, uint32_t line); +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_HAL_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32g070-st-nucleo/board/CubeMX_Config/Inc/stm32g0xx_it.h b/bsp/stm32/stm32g070-st-nucleo/board/CubeMX_Config/Inc/stm32g0xx_it.h new file mode 100644 index 0000000000000000000000000000000000000000..0149e0fd302449bee1051ae4d1fb63a7b0279a75 --- /dev/null +++ b/bsp/stm32/stm32g070-st-nucleo/board/CubeMX_Config/Inc/stm32g0xx_it.h @@ -0,0 +1,65 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32g0xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32G0xx_IT_H +#define __STM32G0xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32G0xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32g070-st-nucleo/board/CubeMX_Config/Src/main.c b/bsp/stm32/stm32g070-st-nucleo/board/CubeMX_Config/Src/main.c new file mode 100644 index 0000000000000000000000000000000000000000..42a94e2849f613d6331dc663af39f903b9a38142 --- /dev/null +++ b/bsp/stm32/stm32g070-st-nucleo/board/CubeMX_Config/Src/main.c @@ -0,0 +1,797 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +ADC_HandleTypeDef hadc1; + +IWDG_HandleTypeDef hiwdg; + +RTC_HandleTypeDef hrtc; + +SPI_HandleTypeDef hspi1; +SPI_HandleTypeDef hspi2; + +TIM_HandleTypeDef htim1; +TIM_HandleTypeDef htim3; + +UART_HandleTypeDef huart1; +UART_HandleTypeDef huart2; +UART_HandleTypeDef huart3; + +WWDG_HandleTypeDef hwwdg; + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void MX_GPIO_Init(void); +static void MX_USART2_UART_Init(void); +static void MX_ADC1_Init(void); +static void MX_IWDG_Init(void); +static void MX_SPI1_Init(void); +static void MX_SPI2_Init(void); +static void MX_TIM1_Init(void); +static void MX_TIM3_Init(void); +static void MX_USART1_UART_Init(void); +static void MX_USART3_UART_Init(void); +static void MX_RTC_Init(void); +static void MX_WWDG_Init(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_USART2_UART_Init(); + MX_ADC1_Init(); + MX_IWDG_Init(); + MX_SPI1_Init(); + MX_SPI2_Init(); + MX_TIM1_Init(); + MX_TIM3_Init(); + MX_USART1_UART_Init(); + MX_USART3_UART_Init(); + MX_RTC_Init(); + MX_WWDG_Init(); + /* USER CODE BEGIN 2 */ + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + + /** Configure the main internal regulator output voltage + */ + HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); + /** Configure LSE Drive Capability + */ + HAL_PWR_EnableBkUpAccess(); + __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_LSI + |RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1; + RCC_OscInitStruct.PLL.PLLN = 8; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) + { + Error_Handler(); + } + /** Initializes the peripherals clocks + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_USART1 + |RCC_PERIPHCLK_USART2|RCC_PERIPHCLK_ADC; + PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK1; + PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1; + PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_SYSCLK; + PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } +} + +/** + * @brief ADC1 Initialization Function + * @param None + * @retval None + */ +static void MX_ADC1_Init(void) +{ + + /* USER CODE BEGIN ADC1_Init 0 */ + + /* USER CODE END ADC1_Init 0 */ + + ADC_AnalogWDGConfTypeDef AnalogWDGConfig = {0}; + ADC_ChannelConfTypeDef sConfig = {0}; + + /* USER CODE BEGIN ADC1_Init 1 */ + + /* USER CODE END ADC1_Init 1 */ + /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) + */ + hadc1.Instance = ADC1; + hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2; + hadc1.Init.Resolution = ADC_RESOLUTION_12B; + hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; + hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE; + hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; + hadc1.Init.LowPowerAutoWait = DISABLE; + hadc1.Init.LowPowerAutoPowerOff = DISABLE; + hadc1.Init.ContinuousConvMode = DISABLE; + hadc1.Init.NbrOfConversion = 1; + hadc1.Init.DiscontinuousConvMode = DISABLE; + hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; + hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + hadc1.Init.DMAContinuousRequests = DISABLE; + hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED; + hadc1.Init.SamplingTimeCommon1 = ADC_SAMPLETIME_1CYCLE_5; + hadc1.Init.SamplingTimeCommon2 = ADC_SAMPLETIME_1CYCLE_5; + hadc1.Init.OversamplingMode = DISABLE; + hadc1.Init.TriggerFrequencyMode = ADC_TRIGGER_FREQ_HIGH; + if (HAL_ADC_Init(&hadc1) != HAL_OK) + { + Error_Handler(); + } + /** Configure Analog WatchDog 2 + */ + AnalogWDGConfig.WatchdogMode = ADC_ANALOGWATCHDOG_SINGLE_REG; + if (HAL_ADC_AnalogWDGConfig(&hadc1, &AnalogWDGConfig) != HAL_OK) + { + Error_Handler(); + } + /** Configure Regular Channel + */ + sConfig.Channel = ADC_CHANNEL_0; + sConfig.Rank = ADC_REGULAR_RANK_1; + sConfig.SamplingTime = ADC_SAMPLINGTIME_COMMON_1; + if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN ADC1_Init 2 */ + + /* USER CODE END ADC1_Init 2 */ + +} + +/** + * @brief IWDG Initialization Function + * @param None + * @retval None + */ +static void MX_IWDG_Init(void) +{ + + /* USER CODE BEGIN IWDG_Init 0 */ + + /* USER CODE END IWDG_Init 0 */ + + /* USER CODE BEGIN IWDG_Init 1 */ + + /* USER CODE END IWDG_Init 1 */ + hiwdg.Instance = IWDG; + hiwdg.Init.Prescaler = IWDG_PRESCALER_4; + hiwdg.Init.Window = 4095; + hiwdg.Init.Reload = 4095; + if (HAL_IWDG_Init(&hiwdg) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN IWDG_Init 2 */ + + /* USER CODE END IWDG_Init 2 */ + +} + +/** + * @brief RTC Initialization Function + * @param None + * @retval None + */ +static void MX_RTC_Init(void) +{ + + /* USER CODE BEGIN RTC_Init 0 */ + + /* USER CODE END RTC_Init 0 */ + + RTC_TimeTypeDef sTime = {0}; + RTC_DateTypeDef sDate = {0}; + + /* USER CODE BEGIN RTC_Init 1 */ + + /* USER CODE END RTC_Init 1 */ + /** Initialize RTC Only + */ + hrtc.Instance = RTC; + hrtc.Init.HourFormat = RTC_HOURFORMAT_24; + hrtc.Init.AsynchPrediv = 127; + hrtc.Init.SynchPrediv = 255; + hrtc.Init.OutPut = RTC_OUTPUT_DISABLE; + hrtc.Init.OutPutRemap = RTC_OUTPUT_REMAP_NONE; + hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; + hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; + hrtc.Init.OutPutPullUp = RTC_OUTPUT_PULLUP_NONE; + if (HAL_RTC_Init(&hrtc) != HAL_OK) + { + Error_Handler(); + } + + /* USER CODE BEGIN Check_RTC_BKUP */ + + /* USER CODE END Check_RTC_BKUP */ + + /** Initialize RTC and set the Time and Date + */ + sTime.Hours = 0x0; + sTime.Minutes = 0x0; + sTime.Seconds = 0x0; + sTime.SubSeconds = 0x0; + sTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE; + sTime.StoreOperation = RTC_STOREOPERATION_RESET; + if (HAL_RTC_SetTime(&hrtc, &sTime, RTC_FORMAT_BCD) != HAL_OK) + { + Error_Handler(); + } + sDate.WeekDay = RTC_WEEKDAY_MONDAY; + sDate.Month = RTC_MONTH_JANUARY; + sDate.Date = 0x1; + sDate.Year = 0x0; + + if (HAL_RTC_SetDate(&hrtc, &sDate, RTC_FORMAT_BCD) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN RTC_Init 2 */ + + /* USER CODE END RTC_Init 2 */ + +} + +/** + * @brief SPI1 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI1_Init(void) +{ + + /* USER CODE BEGIN SPI1_Init 0 */ + + /* USER CODE END SPI1_Init 0 */ + + /* USER CODE BEGIN SPI1_Init 1 */ + + /* USER CODE END SPI1_Init 1 */ + /* SPI1 parameter configuration*/ + hspi1.Instance = SPI1; + hspi1.Init.Mode = SPI_MODE_MASTER; + hspi1.Init.Direction = SPI_DIRECTION_2LINES; + hspi1.Init.DataSize = SPI_DATASIZE_4BIT; + hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; + hspi1.Init.NSS = SPI_NSS_SOFT; + hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi1.Init.TIMode = SPI_TIMODE_DISABLE; + hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi1.Init.CRCPolynomial = 7; + hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE; + hspi1.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; + if (HAL_SPI_Init(&hspi1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SPI1_Init 2 */ + + /* USER CODE END SPI1_Init 2 */ + +} + +/** + * @brief SPI2 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI2_Init(void) +{ + + /* USER CODE BEGIN SPI2_Init 0 */ + + /* USER CODE END SPI2_Init 0 */ + + /* USER CODE BEGIN SPI2_Init 1 */ + + /* USER CODE END SPI2_Init 1 */ + /* SPI2 parameter configuration*/ + hspi2.Instance = SPI2; + hspi2.Init.Mode = SPI_MODE_MASTER; + hspi2.Init.Direction = SPI_DIRECTION_2LINES; + hspi2.Init.DataSize = SPI_DATASIZE_4BIT; + hspi2.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi2.Init.CLKPhase = SPI_PHASE_1EDGE; + hspi2.Init.NSS = SPI_NSS_SOFT; + hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi2.Init.TIMode = SPI_TIMODE_DISABLE; + hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi2.Init.CRCPolynomial = 7; + hspi2.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE; + hspi2.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; + if (HAL_SPI_Init(&hspi2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SPI2_Init 2 */ + + /* USER CODE END SPI2_Init 2 */ + +} + +/** + * @brief TIM1 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM1_Init(void) +{ + + /* USER CODE BEGIN TIM1_Init 0 */ + + /* USER CODE END TIM1_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; + + /* USER CODE BEGIN TIM1_Init 1 */ + + /* USER CODE END TIM1_Init 1 */ + htim1.Instance = TIM1; + htim1.Init.Prescaler = 0; + htim1.Init.CounterMode = TIM_COUNTERMODE_UP; + htim1.Init.Period = 0; + htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim1.Init.RepetitionCounter = 0; + htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim1) != HAL_OK) + { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + sBreakDeadTimeConfig.BreakAFMode = TIM_BREAK_AFMODE_INPUT; + sBreakDeadTimeConfig.Break2AFMode = TIM_BREAK_AFMODE_INPUT; + if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM1_Init 2 */ + + /* USER CODE END TIM1_Init 2 */ + +} + +/** + * @brief TIM3 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM3_Init(void) +{ + + /* USER CODE BEGIN TIM3_Init 0 */ + + /* USER CODE END TIM3_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + TIM_OC_InitTypeDef sConfigOC = {0}; + + /* USER CODE BEGIN TIM3_Init 1 */ + + /* USER CODE END TIM3_Init 1 */ + htim3.Instance = TIM3; + htim3.Init.Prescaler = 0; + htim3.Init.CounterMode = TIM_COUNTERMODE_UP; + htim3.Init.Period = 0; + htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim3) != HAL_OK) + { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIM_OC_Init(&htim3) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + sConfigOC.OCMode = TIM_OCMODE_PWM1; + sConfigOC.Pulse = 0; + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) + { + Error_Handler(); + } + sConfigOC.OCMode = TIM_OCMODE_TIMING; + if (HAL_TIM_OC_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIM_OC_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIM_OC_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM3_Init 2 */ + + /* USER CODE END TIM3_Init 2 */ + HAL_TIM_MspPostInit(&htim3); + +} + +/** + * @brief USART1 Initialization Function + * @param None + * @retval None + */ +static void MX_USART1_UART_Init(void) +{ + + /* USER CODE BEGIN USART1_Init 0 */ + + /* USER CODE END USART1_Init 0 */ + + /* USER CODE BEGIN USART1_Init 1 */ + + /* USER CODE END USART1_Init 1 */ + huart1.Instance = USART1; + huart1.Init.BaudRate = 115200; + huart1.Init.WordLength = UART_WORDLENGTH_8B; + huart1.Init.StopBits = UART_STOPBITS_1; + huart1.Init.Parity = UART_PARITY_NONE; + huart1.Init.Mode = UART_MODE_TX_RX; + huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart1.Init.OverSampling = UART_OVERSAMPLING_16; + huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; + huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart1) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART1_Init 2 */ + + /* USER CODE END USART1_Init 2 */ + +} + +/** + * @brief USART2 Initialization Function + * @param None + * @retval None + */ +static void MX_USART2_UART_Init(void) +{ + + /* USER CODE BEGIN USART2_Init 0 */ + + /* USER CODE END USART2_Init 0 */ + + /* USER CODE BEGIN USART2_Init 1 */ + + /* USER CODE END USART2_Init 1 */ + huart2.Instance = USART2; + huart2.Init.BaudRate = 115200; + huart2.Init.WordLength = UART_WORDLENGTH_7B; + huart2.Init.StopBits = UART_STOPBITS_1; + huart2.Init.Parity = UART_PARITY_NONE; + huart2.Init.Mode = UART_MODE_TX_RX; + huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart2.Init.OverSampling = UART_OVERSAMPLING_16; + huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart2.Init.ClockPrescaler = UART_PRESCALER_DIV1; + huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart2) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetTxFifoThreshold(&huart2, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetRxFifoThreshold(&huart2, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_DisableFifoMode(&huart2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART2_Init 2 */ + + /* USER CODE END USART2_Init 2 */ + +} + +/** + * @brief USART3 Initialization Function + * @param None + * @retval None + */ +static void MX_USART3_UART_Init(void) +{ + + /* USER CODE BEGIN USART3_Init 0 */ + + /* USER CODE END USART3_Init 0 */ + + /* USER CODE BEGIN USART3_Init 1 */ + + /* USER CODE END USART3_Init 1 */ + huart3.Instance = USART3; + huart3.Init.BaudRate = 115200; + huart3.Init.WordLength = UART_WORDLENGTH_8B; + huart3.Init.StopBits = UART_STOPBITS_1; + huart3.Init.Parity = UART_PARITY_NONE; + huart3.Init.Mode = UART_MODE_TX_RX; + huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart3.Init.OverSampling = UART_OVERSAMPLING_16; + huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart3.Init.ClockPrescaler = UART_PRESCALER_DIV1; + huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart3) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART3_Init 2 */ + + /* USER CODE END USART3_Init 2 */ + +} + +/** + * @brief WWDG Initialization Function + * @param None + * @retval None + */ +static void MX_WWDG_Init(void) +{ + + /* USER CODE BEGIN WWDG_Init 0 */ + + /* USER CODE END WWDG_Init 0 */ + + /* USER CODE BEGIN WWDG_Init 1 */ + + /* USER CODE END WWDG_Init 1 */ + hwwdg.Instance = WWDG; + hwwdg.Init.Prescaler = WWDG_PRESCALER_1; + hwwdg.Init.Window = 64; + hwwdg.Init.Counter = 64; + hwwdg.Init.EWIMode = WWDG_EWI_DISABLE; + if (HAL_WWDG_Init(&hwwdg) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN WWDG_Init 2 */ + + /* USER CODE END WWDG_Init 2 */ + +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(LED_GREEN_GPIO_Port, LED_GREEN_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin : LED_GREEN_Pin */ + GPIO_InitStruct.Pin = LED_GREEN_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(LED_GREEN_GPIO_Port, &GPIO_InitStruct); + +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32g070-st-nucleo/board/CubeMX_Config/Src/stm32g0xx_hal_msp.c b/bsp/stm32/stm32g070-st-nucleo/board/CubeMX_Config/Src/stm32g0xx_hal_msp.c new file mode 100644 index 0000000000000000000000000000000000000000..7c05429633538bb36231def501cb521e843f6561 --- /dev/null +++ b/bsp/stm32/stm32g070-st-nucleo/board/CubeMX_Config/Src/stm32g0xx_hal_msp.c @@ -0,0 +1,598 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * File Name : stm32g0xx_hal_msp.c + * Description : This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + /** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/** +* @brief ADC MSP Initialization +* This function configures the hardware resources used in this example +* @param hadc: ADC handle pointer +* @retval None +*/ +void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hadc->Instance==ADC1) + { + /* USER CODE BEGIN ADC1_MspInit 0 */ + + /* USER CODE END ADC1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_ADC_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**ADC1 GPIO Configuration + PA0 ------> ADC1_IN0 + */ + GPIO_InitStruct.Pin = GPIO_PIN_0; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN ADC1_MspInit 1 */ + + /* USER CODE END ADC1_MspInit 1 */ + } + +} + +/** +* @brief ADC MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hadc: ADC handle pointer +* @retval None +*/ +void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) +{ + if(hadc->Instance==ADC1) + { + /* USER CODE BEGIN ADC1_MspDeInit 0 */ + + /* USER CODE END ADC1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_ADC_CLK_DISABLE(); + + /**ADC1 GPIO Configuration + PA0 ------> ADC1_IN0 + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_0); + + /* USER CODE BEGIN ADC1_MspDeInit 1 */ + + /* USER CODE END ADC1_MspDeInit 1 */ + } + +} + +/** +* @brief RTC MSP Initialization +* This function configures the hardware resources used in this example +* @param hrtc: RTC handle pointer +* @retval None +*/ +void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) +{ + if(hrtc->Instance==RTC) + { + /* USER CODE BEGIN RTC_MspInit 0 */ + + /* USER CODE END RTC_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_RTC_ENABLE(); + __HAL_RCC_RTCAPB_CLK_ENABLE(); + /* USER CODE BEGIN RTC_MspInit 1 */ + + /* USER CODE END RTC_MspInit 1 */ + } + +} + +/** +* @brief RTC MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hrtc: RTC handle pointer +* @retval None +*/ +void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) +{ + if(hrtc->Instance==RTC) + { + /* USER CODE BEGIN RTC_MspDeInit 0 */ + + /* USER CODE END RTC_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_RTC_DISABLE(); + __HAL_RCC_RTCAPB_CLK_DISABLE(); + /* USER CODE BEGIN RTC_MspDeInit 1 */ + + /* USER CODE END RTC_MspDeInit 1 */ + } + +} + +/** +* @brief SPI MSP Initialization +* This function configures the hardware resources used in this example +* @param hspi: SPI handle pointer +* @retval None +*/ +void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hspi->Instance==SPI1) + { + /* USER CODE BEGIN SPI1_MspInit 0 */ + + /* USER CODE END SPI1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**SPI1 GPIO Configuration + PA1 ------> SPI1_SCK + PA11 [PA9] ------> SPI1_MISO + PA12 [PA10] ------> SPI1_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_11|GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF0_SPI1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI1_MspInit 1 */ + + /* USER CODE END SPI1_MspInit 1 */ + } + else if(hspi->Instance==SPI2) + { + /* USER CODE BEGIN SPI2_MspInit 0 */ + + /* USER CODE END SPI2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI2_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**SPI2 GPIO Configuration + PC2 ------> SPI2_MISO + PC3 ------> SPI2_MOSI + PB10 ------> SPI2_SCK + */ + GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF1_SPI2; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI2_MspInit 1 */ + + /* USER CODE END SPI2_MspInit 1 */ + } + +} + +/** +* @brief SPI MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hspi: SPI handle pointer +* @retval None +*/ +void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) +{ + if(hspi->Instance==SPI1) + { + /* USER CODE BEGIN SPI1_MspDeInit 0 */ + + /* USER CODE END SPI1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI1_CLK_DISABLE(); + + /**SPI1 GPIO Configuration + PA1 ------> SPI1_SCK + PA11 [PA9] ------> SPI1_MISO + PA12 [PA10] ------> SPI1_MOSI + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1|GPIO_PIN_11|GPIO_PIN_12); + + /* USER CODE BEGIN SPI1_MspDeInit 1 */ + + /* USER CODE END SPI1_MspDeInit 1 */ + } + else if(hspi->Instance==SPI2) + { + /* USER CODE BEGIN SPI2_MspDeInit 0 */ + + /* USER CODE END SPI2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI2_CLK_DISABLE(); + + /**SPI2 GPIO Configuration + PC2 ------> SPI2_MISO + PC3 ------> SPI2_MOSI + PB10 ------> SPI2_SCK + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_2|GPIO_PIN_3); + + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10); + + /* USER CODE BEGIN SPI2_MspDeInit 1 */ + + /* USER CODE END SPI2_MspDeInit 1 */ + } + +} + +/** +* @brief TIM_Base MSP Initialization +* This function configures the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) +{ + if(htim_base->Instance==TIM1) + { + /* USER CODE BEGIN TIM1_MspInit 0 */ + + /* USER CODE END TIM1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM1_CLK_ENABLE(); + /* USER CODE BEGIN TIM1_MspInit 1 */ + + /* USER CODE END TIM1_MspInit 1 */ + } + else if(htim_base->Instance==TIM3) + { + /* USER CODE BEGIN TIM3_MspInit 0 */ + + /* USER CODE END TIM3_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM3_CLK_ENABLE(); + /* USER CODE BEGIN TIM3_MspInit 1 */ + + /* USER CODE END TIM3_MspInit 1 */ + } + +} + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(htim->Instance==TIM3) + { + /* USER CODE BEGIN TIM3_MspPostInit 0 */ + + /* USER CODE END TIM3_MspPostInit 0 */ + + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**TIM3 GPIO Configuration + PA6 ------> TIM3_CH1 + PA7 ------> TIM3_CH2 + PB0 ------> TIM3_CH3 + PB1 ------> TIM3_CH4 + */ + GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF1_TIM3; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF1_TIM3; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM3_MspPostInit 1 */ + + /* USER CODE END TIM3_MspPostInit 1 */ + } + +} +/** +* @brief TIM_Base MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base) +{ + if(htim_base->Instance==TIM1) + { + /* USER CODE BEGIN TIM1_MspDeInit 0 */ + + /* USER CODE END TIM1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM1_CLK_DISABLE(); + /* USER CODE BEGIN TIM1_MspDeInit 1 */ + + /* USER CODE END TIM1_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM3) + { + /* USER CODE BEGIN TIM3_MspDeInit 0 */ + + /* USER CODE END TIM3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM3_CLK_DISABLE(); + /* USER CODE BEGIN TIM3_MspDeInit 1 */ + + /* USER CODE END TIM3_MspDeInit 1 */ + } + +} + +/** +* @brief UART MSP Initialization +* This function configures the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspInit(UART_HandleTypeDef* huart) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(huart->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspInit 0 */ + + /* USER CODE END USART1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USART1_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + /**USART1 GPIO Configuration + PC4 ------> USART1_TX + PC5 ------> USART1_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF1_USART1; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /* USER CODE BEGIN USART1_MspInit 1 */ + + /* USER CODE END USART1_MspInit 1 */ + } + else if(huart->Instance==USART2) + { + /* USER CODE BEGIN USART2_MspInit 0 */ + + /* USER CODE END USART2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USART2_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USART2 GPIO Configuration + PA2 ------> USART2_TX + PA3 ------> USART2_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF1_USART2; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN USART2_MspInit 1 */ + + /* USER CODE END USART2_MspInit 1 */ + } + else if(huart->Instance==USART3) + { + /* USER CODE BEGIN USART3_MspInit 0 */ + + /* USER CODE END USART3_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USART3_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**USART3 GPIO Configuration + PC11 ------> USART3_RX + PB2 ------> USART3_TX + */ + GPIO_InitStruct.Pin = GPIO_PIN_11; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF0_USART3; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF4_USART3; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN USART3_MspInit 1 */ + + /* USER CODE END USART3_MspInit 1 */ + } + +} + +/** +* @brief UART MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) +{ + if(huart->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspDeInit 0 */ + + /* USER CODE END USART1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART1_CLK_DISABLE(); + + /**USART1 GPIO Configuration + PC4 ------> USART1_TX + PC5 ------> USART1_RX + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_4|GPIO_PIN_5); + + /* USER CODE BEGIN USART1_MspDeInit 1 */ + + /* USER CODE END USART1_MspDeInit 1 */ + } + else if(huart->Instance==USART2) + { + /* USER CODE BEGIN USART2_MspDeInit 0 */ + + /* USER CODE END USART2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART2_CLK_DISABLE(); + + /**USART2 GPIO Configuration + PA2 ------> USART2_TX + PA3 ------> USART2_RX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); + + /* USER CODE BEGIN USART2_MspDeInit 1 */ + + /* USER CODE END USART2_MspDeInit 1 */ + } + else if(huart->Instance==USART3) + { + /* USER CODE BEGIN USART3_MspDeInit 0 */ + + /* USER CODE END USART3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART3_CLK_DISABLE(); + + /**USART3 GPIO Configuration + PC11 ------> USART3_RX + PB2 ------> USART3_TX + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_11); + + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_2); + + /* USER CODE BEGIN USART3_MspDeInit 1 */ + + /* USER CODE END USART3_MspDeInit 1 */ + } + +} + +/** +* @brief WWDG MSP Initialization +* This function configures the hardware resources used in this example +* @param hwwdg: WWDG handle pointer +* @retval None +*/ +void HAL_WWDG_MspInit(WWDG_HandleTypeDef* hwwdg) +{ + if(hwwdg->Instance==WWDG) + { + /* USER CODE BEGIN WWDG_MspInit 0 */ + + /* USER CODE END WWDG_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_WWDG_CLK_ENABLE(); + /* USER CODE BEGIN WWDG_MspInit 1 */ + + /* USER CODE END WWDG_MspInit 1 */ + } + +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32g070-st-nucleo/board/CubeMX_Config/Src/stm32g0xx_it.c b/bsp/stm32/stm32g070-st-nucleo/board/CubeMX_Config/Src/stm32g0xx_it.c new file mode 100644 index 0000000000000000000000000000000000000000..5d2ca523b1d0da590a53fdf48cf01b9a0a8c3ddd --- /dev/null +++ b/bsp/stm32/stm32g070-st-nucleo/board/CubeMX_Config/Src/stm32g0xx_it.c @@ -0,0 +1,145 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32g0xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32g0xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ + +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M0+ Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVC_IRQn 0 */ + + /* USER CODE END SVC_IRQn 0 */ + /* USER CODE BEGIN SVC_IRQn 1 */ + + /* USER CODE END SVC_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32G0xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32g0xx.s). */ +/******************************************************************************/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32g070-st-nucleo/board/CubeMX_Config/stm32g070rbt6.ioc b/bsp/stm32/stm32g070-st-nucleo/board/CubeMX_Config/stm32g070rbt6.ioc new file mode 100644 index 0000000000000000000000000000000000000000..353d97411cb71613772a2785b9b796fbcdc1eb32 --- /dev/null +++ b/bsp/stm32/stm32g070-st-nucleo/board/CubeMX_Config/stm32g070rbt6.ioc @@ -0,0 +1,247 @@ +#MicroXplorer Configuration settings - do not modify +Mcu.Family=STM32G0 +PC3.Mode=Full_Duplex_Master +ProjectManager.MainLocation=Src +PA2.GPIO_PuPd=GPIO_PULLUP +PA11\ [PA9].Mode=Full_Duplex_Master +RCC.USART1Freq_Value=64000000 +USART2.IPParameters=VirtualMode-Asynchronous,WordLength +RCC.CortexFreq_Value=64000000 +ProjectManager.KeepUserCode=true +Mcu.UserName=STM32G070RBTx +SPI1.VirtualType=VM_MASTER +SPI2.VirtualType=VM_MASTER +PB10.Mode=Full_Duplex_Master +TIM3.Channel-Output\ Compare3\ CH3=TIM_CHANNEL_3 +PA12\ [PA10].Mode=Full_Duplex_Master +VP_IWDG_VS_IWDG.Mode=IWDG_Activate +PA3.GPIO_PuPd=GPIO_PULLUP +PA14-BOOT0.Mode=Serial_Wire +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART2_UART_Init-USART2-false-HAL-true,4-MX_ADC1_Init-ADC1-false-HAL-true,5-MX_IWDG_Init-IWDG-false-HAL-true,6-MX_SPI1_Init-SPI1-false-HAL-true,7-MX_SPI2_Init-SPI2-false-HAL-true,8-MX_TIM1_Init-TIM1-false-HAL-true,9-MX_TIM3_Init-TIM3-false-HAL-true,10-MX_USART1_UART_Init-USART1-false-HAL-true,11-MX_USART3_UART_Init-USART3-false-HAL-true +VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled +RCC.RTCFreq_Value=32768 +PA3.GPIOParameters=GPIO_PuPd +RCC.USART2Freq_Value=64000000 +VP_RTC_VS_RTC_Calendar.Signal=RTC_VS_RTC_Calendar +PC15-OSC32_OUT\ (PC15).Mode=LSE-External-Oscillator +NVIC.SVC_IRQn=true\:0\:0\:false\:false\:true\:false\:false +PC5.Mode=Asynchronous +USART1.IPParameters=VirtualMode-Asynchronous +PF0-OSC_IN\ (PF0).GPIO_Label=MCO +PA2.GPIOParameters=GPIO_PuPd +PinOutPanel.RotationAngle=0 +PF0-OSC_IN\ (PF0).Signal=RCC_OSC_IN +RCC.MCO1PinFreq_Value=64000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +ProjectManager.StackSize=0x400 +PC14-OSC32_IN\ (PC14).Mode=LSE-External-Oscillator +USART3.VirtualMode-Asynchronous=VM_ASYNC +RCC.LPTIM1Freq_Value=16000000 +Mcu.IP4=RTC +RCC.FCLKCortexFreq_Value=64000000 +Mcu.IP5=SPI1 +Mcu.IP2=NVIC +Mcu.IP3=RCC +Mcu.IP0=ADC1 +Mcu.IP1=IWDG +Mcu.UserConstants= +SH.S_TIM3_CH2.ConfNb=1 +PA14-BOOT0.GPIOParameters=GPIO_Label +Mcu.ThirdPartyNb=0 +SPI1.Direction=SPI_DIRECTION_2LINES +RCC.HCLKFreq_Value=64000000 +PA12\ [PA10].Signal=SPI1_MOSI +Mcu.IPNb=14 +ProjectManager.PreviousToolchain= +SPI1.CalculateBaudRate=32.0 MBits/s +PC3.Signal=SPI2_MOSI +Mcu.Pin6=PC3 +Mcu.Pin7=PA0 +Mcu.Pin8=PA1 +Mcu.Pin9=PA2 +RCC.AHBFreq_Value=64000000 +PF0-OSC_IN\ (PF0).Locked=true +Mcu.Pin0=PC11 +Mcu.Pin1=PC13 +PA14-BOOT0.Signal=SYS_SWCLK +TIM3.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1 +Mcu.Pin2=PC14-OSC32_IN (PC14) +Mcu.Pin3=PC15-OSC32_OUT (PC15) +Mcu.Pin4=PF0-OSC_IN (PF0) +Mcu.Pin5=PC2 +ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_0 +ProjectManager.ProjectBuild=false +RCC.HSE_VALUE=8000000 +PB2.Signal=USART3_TX +Mcu.IP10=USART1 +USART2.VirtualMode-Asynchronous=VM_ASYNC +NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true +RCC.RTCClockSelection=RCC_RTCCLKSOURCE_LSE +Mcu.IP12=USART3 +Mcu.IP11=USART2 +ProjectManager.FirmwarePackage=STM32Cube FW_G0 V1.3.0 +MxDb.Version=DB.5.0.60 +Mcu.IP13=WWDG +ProjectManager.BackupPrevious=false +RCC.VCOInputFreq_Value=16000000 +File.Version=6 +PA0.Mode=IN0 +SPI2.CalculateBaudRate=32.0 MBits/s +VP_SYS_VS_DBSignals.Mode=DisableDeadBatterySignals +RCC.PLLRCLKFreq_Value=64000000 +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false +SH.S_TIM3_CH1.0=TIM3_CH1,PWM Generation1 CH1 +ProjectManager.HalAssertFull=false +VP_TIM1_VS_ClockSourceINT.Mode=Internal +ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLINGTIME_COMMON_1 +ProjectManager.ProjectName=stm32g070rbt6 +PA0.Signal=ADC1_IN0 +RCC.TIM1Freq_Value=16000000 +PA13.GPIOParameters=GPIO_Label +Mcu.Package=LQFP64 +PB1.Signal=S_TIM3_CH4 +PA6.Signal=S_TIM3_CH1 +RCC.TIM15Freq_Value=16000000 +PA5.Locked=true +SPI2.Mode=SPI_MODE_MASTER +RCC.APBFreq_Value=64000000 +ProjectManager.ToolChainLocation= +RCC.LSI_VALUE=32000 +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +RCC.LSCOPinFreq_Value=32000 +USART3.IPParameters=VirtualMode-Asynchronous +VP_RTC_VS_RTC_Calendar.Mode=RTC_Calendar +PA5.GPIOParameters=GPIO_Speed,GPIO_Label +PC11.Mode=Asynchronous +USART2.WordLength=WORDLENGTH_7B +PC14-OSC32_IN\ (PC14).Locked=true +RCC.PLLPoutputFreq_Value=64000000 +RCC.CECFreq_Value=32786.88524590164 +RCC.LPUART1Freq_Value=16000000 +SPI2.Direction=SPI_DIRECTION_2LINES +PC5.Signal=USART1_RX +TIM3.Channel-Output\ Compare2\ CH2=TIM_CHANNEL_2 +ProjectManager.CustomerFirmwarePackage= +VP_TIM3_VS_ClockSourceINT.Mode=Internal +PC4.Mode=Asynchronous +PA3.Signal=USART2_RX +VP_WWDG_VS_WWDG.Signal=WWDG_VS_WWDG +PA2.Locked=true +VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate +RCC.PLLQoutputFreq_Value=64000000 +ProjectManager.ProjectFileName=stm32g070rbt6.ioc +PA14-BOOT0.GPIO_Label=TCK +ADC1.Rank-0\#ChannelRegularConversion=1 +Mcu.PinsNb=32 +ProjectManager.NoMain=false +SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate +ADC1.IPParameters=Rank-0\#ChannelRegularConversion,master,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag +PC13.Locked=true +PC13.Signal=SYS_WKUP2 +PC11.Signal=USART3_RX +PC2.Signal=SPI2_MISO +PC4.Signal=USART1_TX +RCC.EXTERNAL_CLOCK_VALUE=12288000 +ProjectManager.DefaultFWLocation=true +PC2.Mode=Full_Duplex_Master +PC15-OSC32_OUT\ (PC15).Signal=RCC_OSC32_OUT +ProjectManager.DeletePrevious=true +boardIOC=true +SH.S_TIM3_CH3.0=TIM3_CH3,Output Compare3 CH3 +RCC.FamilyName=M +PF0-OSC_IN\ (PF0).Mode=HSE-External-Clock-Source +USART1.VirtualMode-Asynchronous=VM_ASYNC +PA13.Signal=SYS_SWDIO +PA3.Mode=Asynchronous +ProjectManager.TargetToolchain=Makefile +SH.S_TIM3_CH3.ConfNb=1 +VP_TIM1_VS_ClockSourceINT.Signal=TIM1_VS_ClockSourceINT +RCC.I2S1Freq_Value=64000000 +SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate +PC15-OSC32_OUT\ (PC15).Locked=true +VP_TIM3_VS_ClockSourceINT.Signal=TIM3_VS_ClockSourceINT +PA1.Signal=SPI1_SCK +PB10.Signal=SPI2_SCK +PA5.Signal=GPIO_Output +SH.S_TIM3_CH2.0=TIM3_CH2,Output Compare2 CH2 +board=NUCLEO-G070RB +RCC.VCOOutputFreq_Value=128000000 +ProjectManager.LastFirmware=true +PA1.Mode=Full_Duplex_Master +MxCube.Version=5.6.1 +RCC.I2C1Freq_Value=64000000 +SPI1.Mode=SPI_MODE_MASTER +VP_SYS_VS_DBSignals.Signal=SYS_VS_DBSignals +Mcu.Pin30=VP_TIM3_VS_ClockSourceINT +RCC.ADCFreq_Value=64000000 +VP_SYS_VS_Systick.Mode=SysTick +TIM3.IPParameters=Channel-Output Compare2 CH2,Channel-Output Compare3 CH3,Channel-Output Compare4 CH4,Channel-PWM Generation1 CH1 +Mcu.Pin31=VP_WWDG_VS_WWDG +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false +PC13.Mode=SYS_WakeUp1 +PA13.Mode=Serial_Wire +ProjectManager.FreePins=false +RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APBFreq_Value,APBTimFreq_Value,CECFreq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2S1Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSI_VALUE,MCO1PinFreq_Value,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RTCClockSelection,RTCFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,TIM15Freq_Value,TIM1Freq_Value,USART1Freq_Value,USART2Freq_Value,VCOInputFreq_Value,VCOOutputFreq_Value +ProjectManager.AskForMigrate=true +Mcu.Name=STM32G070RBTx +PA11\ [PA9].Signal=SPI1_MISO +RCC.LPTIM2Freq_Value=16000000 +Mcu.Pin26=VP_RTC_VS_RTC_Calendar +PA14-BOOT0.Locked=true +Mcu.Pin27=VP_SYS_VS_Systick +PA2.Signal=USART2_TX +PA13.GPIO_Label=TMS +Mcu.Pin24=VP_IWDG_VS_IWDG +ProjectManager.UnderRoot=false +Mcu.Pin25=VP_RTC_VS_RTC_Activate +TIM3.Channel-Output\ Compare4\ CH4=TIM_CHANNEL_4 +Mcu.IP8=TIM1 +Mcu.IP9=TIM3 +Mcu.Pin28=VP_SYS_VS_DBSignals +Mcu.IP6=SPI2 +Mcu.Pin29=VP_TIM1_VS_ClockSourceINT +Mcu.IP7=SYS +ProjectManager.CoupleFile=false +RCC.APBTimFreq_Value=64000000 +RCC.SYSCLKFreq_VALUE=64000000 +Mcu.Pin22=PA13 +Mcu.Pin23=PA14-BOOT0 +Mcu.Pin20=PA11 [PA9] +ADC1.master=1 +Mcu.Pin21=PA12 [PA10] +PA3.Locked=true +PA5.GPIO_Label=LED_GREEN +NVIC.ForceEnableDMAVector=true +KeepUserPlacement=false +PC14-OSC32_IN\ (PC14).Signal=RCC_OSC32_IN +PB2.Mode=Asynchronous +PA13.Locked=true +ProjectManager.CompilerOptimize=6 +VP_IWDG_VS_IWDG.Signal=IWDG_VS_IWDG +ProjectManager.HeapSize=0x200 +Mcu.Pin15=PC5 +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +Mcu.Pin16=PB0 +Mcu.Pin13=PA7 +Mcu.Pin14=PC4 +VP_WWDG_VS_WWDG.Mode=WWDG_Activate +Mcu.Pin19=PB10 +SH.S_TIM3_CH1.ConfNb=1 +ProjectManager.ComputerToolchain=false +Mcu.Pin17=PB1 +RCC.HSI_VALUE=16000000 +Mcu.Pin18=PB2 +PA5.GPIO_Speed=GPIO_SPEED_FREQ_HIGH +SH.S_TIM3_CH4.ConfNb=1 +ADC1.NbrOfConversionFlag=1 +Mcu.Pin11=PA5 +Mcu.Pin12=PA6 +Mcu.Pin10=PA3 +PA2.Mode=Asynchronous +RCC.PWRFreq_Value=64000000 +PB0.Signal=S_TIM3_CH3 +PF0-OSC_IN\ (PF0).GPIOParameters=GPIO_Label +ProjectManager.DeviceId=STM32G070RBTx +ProjectManager.LibraryCopy=1 +SH.S_TIM3_CH4.0=TIM3_CH4,Output Compare4 CH4 +PA7.Signal=S_TIM3_CH2 diff --git a/bsp/stm32/stm32g070-st-nucleo/board/Kconfig b/bsp/stm32/stm32g070-st-nucleo/board/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..9f1ce517205adb982bf72ece3d6a2917dcea1bb0 --- /dev/null +++ b/bsp/stm32/stm32g070-st-nucleo/board/Kconfig @@ -0,0 +1,198 @@ +menu "Hardware Drivers Config" + +config SOC_STM32G070RB + bool + select SOC_SERIES_STM32G0 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "Onboard Peripheral Drivers" + + config BSP_USING_USB_TO_UART + bool "Enable USB TO UART (uart2)" + select BSP_USING_UART2 + default y + +endmenu + +menu "On-chip Peripheral Drivers" + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default n + + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART2 + bool "Enable UART2" + default n + + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART3 + bool "Enable UART3" + default n + + config BSP_UART3_RX_USING_DMA + bool "Enable UART3 RX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + endif + + menuconfig BSP_USING_TIM + bool "Enable timer" + default n + select RT_USING_HWTIMER + if BSP_USING_TIM + + config BSP_USING_TIM1 + bool "Enable TIM1" + default n + + config BSP_USING_TIM3 + bool "Enable TIM3" + default n + endif + + menuconfig BSP_USING_PWM + bool "Enable pwm" + default n + select RT_USING_PWM + if BSP_USING_PWM + menuconfig BSP_USING_PWM3 + bool "Enable timer3 output pwm" + default n + if BSP_USING_PWM3 + config BSP_USING_PWM3_CH1 + bool "Enable PWM3 channel1" + default n + + config BSP_USING_PWM3_CH2 + bool "Enable PWM3 channel2" + default n + + config BSP_USING_PWM3_CH3 + bool "Enable PWM3 channel3" + default n + + config BSP_USING_PWM3_CH4 + bool "Enable PWM3 channel4" + default n + endif + endif + + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n + + config BSP_SPI1_TX_USING_DMA + bool "Enable SPI1 TX DMA" + depends on BSP_USING_SPI1 + default n + + config BSP_SPI1_RX_USING_DMA + bool "Enable SPI1 RX DMA" + depends on BSP_USING_SPI1 + select BSP_SPI1_TX_USING_DMA + default n + + config BSP_USING_SPI2 + bool "Enable SPI2 BUS" + default n + + config BSP_SPI2_TX_USING_DMA + bool "Enable SPI2 TX DMA" + depends on BSP_USING_SPI2 + default n + + config BSP_SPI2_RX_USING_DMA + bool "Enable SPI2 RX DMA" + depends on BSP_USING_SPI2 + select BSP_SPI2_TX_USING_DMA + default n + endif + + menuconfig BSP_USING_I2C1 + bool "Enable I2C1 BUS (software simulation)" + default n + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C1 + config BSP_I2C1_SCL_PIN + int "i2c1 scl pin number" + range 0 63 + default 22 + config BSP_I2C1_SDA_PIN + int "I2C1 sda pin number" + range 0 63 + default 23 + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + endif + + config BSP_USING_ON_CHIP_FLASH + bool "Enable on-chip FLASH" + default n + + menuconfig BSP_USING_ONCHIP_RTC + bool "Enable RTC" + select RT_USING_RTC + select RT_USING_LIBC + default n + if BSP_USING_ONCHIP_RTC + choice + prompt "Select clock source" + default BSP_RTC_USING_LSE + + config BSP_RTC_USING_LSE + bool "RTC USING LSE" + + config BSP_RTC_USING_LSI + bool "RTC USING LSI" + endchoice + endif + + config BSP_USING_WDT + bool "Enable Watchdog Timer" + select RT_USING_WDT + default n + source "libraries/HAL_Drivers/Kconfig" + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/stm32/stm32g070-st-nucleo/board/SConscript b/bsp/stm32/stm32g070-st-nucleo/board/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..1ee2dd32b326fea1703b522a5bac4585958230aa --- /dev/null +++ b/bsp/stm32/stm32g070-st-nucleo/board/SConscript @@ -0,0 +1,30 @@ +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() + +# add general drivers +src = Split(''' +board.c +CubeMX_Config/Src/stm32g0xx_hal_msp.c +''') + +path = [cwd] +path += [cwd + '/CubeMX_Config/Inc'] +path += [cwd + '/ports'] + +startup_path_prefix = SDK_LIB + +if rtconfig.CROSS_TOOL == 'gcc': + src += [startup_path_prefix + '/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g070xx.s'] +elif rtconfig.CROSS_TOOL == 'keil': + src += [startup_path_prefix + '/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/arm/startup_stm32g070xx.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src += [startup_path_prefix + '/STM32G0xx_HAL/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/startup_stm32g070xx.s'] + +CPPDEFINES = ['STM32G070xx'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) +Return('group') diff --git a/bsp/stm32/stm32g070-st-nucleo/board/board.c b/bsp/stm32/stm32g070-st-nucleo/board/board.c new file mode 100644 index 0000000000000000000000000000000000000000..0c907528d032bfb0e99ff54d452d9384be07ab2f --- /dev/null +++ b/bsp/stm32/stm32g070-st-nucleo/board/board.c @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-7-1 NU-LL first version + */ + +#include "board.h" + +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + + /** Configure the main internal regulator output voltage + */ + HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_LSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1; + RCC_OscInitStruct.PLL.PLLN = 8; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) + { + Error_Handler(); + } + /** Initializes the peripherals clocks + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1|RCC_PERIPHCLK_USART2 + |RCC_PERIPHCLK_ADC; + PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK1; + PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1; + PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_SYSCLK; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } +} diff --git a/bsp/stm32/stm32g070-st-nucleo/board/board.h b/bsp/stm32/stm32g070-st-nucleo/board/board.h new file mode 100644 index 0000000000000000000000000000000000000000..f0345a1293365b8d83d9d6e031df046b349ef9a9 --- /dev/null +++ b/bsp/stm32/stm32g070-st-nucleo/board/board.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-06 SummerGift first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include +#include "drv_common.h" +#include "drv_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000) +#define STM32_FLASH_SIZE (128 * 1024) +#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE)) + +/* Internal SRAM memory size[Kbytes] <8-64>, Default: 36 */ +#define STM32_SRAM_SIZE 36 +#define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) + +#if defined(__CC_ARM) || defined(__CLANG_ARM) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="CSTACK" +#define HEAP_BEGIN (__segment_end("CSTACK")) +#else +extern int __bss_end; +#define HEAP_BEGIN ((void *)&__bss_end) +#endif + +#define HEAP_END STM32_SRAM_END + +void SystemClock_Config(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __BOARD_H__ */ diff --git a/bsp/stm32/stm32g070-st-nucleo/board/linker_scripts/link.icf b/bsp/stm32/stm32g070-st-nucleo/board/linker_scripts/link.icf new file mode 100644 index 0000000000000000000000000000000000000000..3c754ac8f32c937168571dc61dfd4f6cf6a0e8bd --- /dev/null +++ b/bsp/stm32/stm32g070-st-nucleo/board/linker_scripts/link.icf @@ -0,0 +1,28 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x08020000; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20009000; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x0200; +define symbol __ICFEDIT_size_heap__ = 0x0000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/stm32/stm32g070-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32g070-st-nucleo/board/linker_scripts/link.lds new file mode 100644 index 0000000000000000000000000000000000000000..963ce61634c73344c65937f037a1d3d0fb74b57e --- /dev/null +++ b/bsp/stm32/stm32g070-st-nucleo/board/linker_scripts/link.lds @@ -0,0 +1,156 @@ +/* + * linker script for STM32FG0x with GNU ld + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + ROM (rx) : ORIGIN = 0x08000000, LENGTH = 128k /* 128KB flash */ + RAM (rw) : ORIGIN = 0x20000000, LENGTH = 36k /* 36K sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x200; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + + _etext = .; + } > ROM = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > ROM + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >RAM + + .stack : + { + . = ALIGN(4); + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >RAM + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > RAM + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/stm32/stm32g070-st-nucleo/board/linker_scripts/link.sct b/bsp/stm32/stm32g070-st-nucleo/board/linker_scripts/link.sct new file mode 100644 index 0000000000000000000000000000000000000000..01a848e615b9c0231a57072d0577c92ccb1fe48f --- /dev/null +++ b/bsp/stm32/stm32g070-st-nucleo/board/linker_scripts/link.sct @@ -0,0 +1,16 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00020000 { ; load region size_region + ER_IROM1 0x08000000 0x00020000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + RW_IRAM1 0x20000000 0x00009000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/stm32/stm32g070-st-nucleo/board/ports/fal_cfg.h b/bsp/stm32/stm32g070-st-nucleo/board/ports/fal_cfg.h new file mode 100644 index 0000000000000000000000000000000000000000..ee65e188d922a60e36d346e246c975319f6059a8 --- /dev/null +++ b/bsp/stm32/stm32g070-st-nucleo/board/ports/fal_cfg.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-8 zylx first version + */ + +#ifndef _FAL_CFG_H_ +#define _FAL_CFG_H_ + +#include +#include + +extern const struct fal_flash_dev stm32_onchip_flash; + +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ +{ \ + &stm32_onchip_flash, \ +} +/* ====================== Partition Configuration ========================== */ +#ifdef FAL_PART_HAS_TABLE_CFG + +/* partition table */ +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 112 * 1024, 0}, \ + {FAL_PART_MAGIC_WROD, "param", "onchip_flash", 112 * 1024 , 16 * 1024, 0}, \ +} +#endif /* FAL_PART_HAS_TABLE_CFG */ +#endif /* _FAL_CFG_H_ */ diff --git a/bsp/stm32/stm32g070-st-nucleo/figures/board.jpg b/bsp/stm32/stm32g070-st-nucleo/figures/board.jpg new file mode 100644 index 0000000000000000000000000000000000000000..13471220ca3b8417e45f6b6890434f5591da38c1 Binary files /dev/null and b/bsp/stm32/stm32g070-st-nucleo/figures/board.jpg differ diff --git a/bsp/stm32/stm32g070-st-nucleo/project.ewp b/bsp/stm32/stm32g070-st-nucleo/project.ewp new file mode 100644 index 0000000000000000000000000000000000000000..7ff56f91342fc1377c44a7ec73352d22ed16b2a0 --- /dev/null +++ b/bsp/stm32/stm32g070-st-nucleo/project.ewp @@ -0,0 +1,2326 @@ + + 3 + + rt-thread + + ARM + + 1 + + General + 3 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 35 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 35 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + Kernel + + $PROJ_DIR$\..\..\..\src\clock.c + + + $PROJ_DIR$\..\..\..\src\components.c + + + $PROJ_DIR$\..\..\..\src\device.c + + + $PROJ_DIR$\..\..\..\src\idle.c + + + $PROJ_DIR$\..\..\..\src\ipc.c + + + $PROJ_DIR$\..\..\..\src\irq.c + + + $PROJ_DIR$\..\..\..\src\kservice.c + + + $PROJ_DIR$\..\..\..\src\mem.c + + + $PROJ_DIR$\..\..\..\src\mempool.c + + + $PROJ_DIR$\..\..\..\src\object.c + + + $PROJ_DIR$\..\..\..\src\scheduler.c + + + $PROJ_DIR$\..\..\..\src\signal.c + + + $PROJ_DIR$\..\..\..\src\thread.c + + + $PROJ_DIR$\..\..\..\src\timer.c + + + + Applications + + $PROJ_DIR$\applications\main.c + + + + Drivers + + $PROJ_DIR$\board\board.c + + + $PROJ_DIR$\board\CubeMX_Config\Src\stm32g0xx_hal_msp.c + + + $PROJ_DIR$\..\libraries\STM32G0xx_HAL\CMSIS\Device\ST\STM32G0xx\Source\Templates\iar\startup_stm32g071xx.s + + + $PROJ_DIR$\..\libraries\HAL_Drivers\drv_gpio.c + + + $PROJ_DIR$\..\libraries\HAL_Drivers\drv_usart.c + + + $PROJ_DIR$\..\libraries\HAL_Drivers\drv_common.c + + + + cpu + + $PROJ_DIR$\..\..\..\libcpu\arm\common\backtrace.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m0\cpuport.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m0\context_iar.S + + + + DeviceDrivers + + $PROJ_DIR$\..\..\..\components\drivers\misc\pin.c + + + $PROJ_DIR$\..\..\..\components\drivers\serial\serial.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\completion.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\dataqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\pipe.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\ringblk_buf.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\ringbuffer.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\waitqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\workqueue.c + + + + finsh + + $PROJ_DIR$\..\..\..\components\finsh\shell.c + + + $PROJ_DIR$\..\..\..\components\finsh\cmd.c + + + $PROJ_DIR$\..\..\..\components\finsh\msh.c + + + $PROJ_DIR$\..\..\..\components\finsh\finsh_compiler.c + + + $PROJ_DIR$\..\..\..\components\finsh\finsh_error.c + + + $PROJ_DIR$\..\..\..\components\finsh\finsh_heap.c + + + $PROJ_DIR$\..\..\..\components\finsh\finsh_init.c + + + $PROJ_DIR$\..\..\..\components\finsh\finsh_node.c + + + $PROJ_DIR$\..\..\..\components\finsh\finsh_ops.c + + + $PROJ_DIR$\..\..\..\components\finsh\finsh_parser.c + + + $PROJ_DIR$\..\..\..\components\finsh\finsh_var.c + + + $PROJ_DIR$\..\..\..\components\finsh\finsh_vm.c + + + $PROJ_DIR$\..\..\..\components\finsh\finsh_token.c + + + + libc + + + STM32_HAL + + $PROJ_DIR$\..\libraries\STM32G0xx_HAL\CMSIS\Device\ST\STM32G0xx\Source\Templates\system_stm32g0xx.c + + + $PROJ_DIR$\..\libraries\STM32G0xx_HAL\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_cec.c + + + $PROJ_DIR$\..\libraries\STM32G0xx_HAL\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_rcc.c + + + $PROJ_DIR$\..\libraries\STM32G0xx_HAL\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_rcc_ex.c + + + $PROJ_DIR$\..\libraries\STM32G0xx_HAL\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_flash.c + + + $PROJ_DIR$\..\libraries\STM32G0xx_HAL\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_flash_ex.c + + + $PROJ_DIR$\..\libraries\STM32G0xx_HAL\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_dma.c + + + $PROJ_DIR$\..\libraries\STM32G0xx_HAL\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_dma_ex.c + + + $PROJ_DIR$\..\libraries\STM32G0xx_HAL\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_pwr.c + + + $PROJ_DIR$\..\libraries\STM32G0xx_HAL\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_pwr_ex.c + + + $PROJ_DIR$\..\libraries\STM32G0xx_HAL\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_cortex.c + + + $PROJ_DIR$\..\libraries\STM32G0xx_HAL\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal.c + + + $PROJ_DIR$\..\libraries\STM32G0xx_HAL\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_gpio.c + + + $PROJ_DIR$\..\libraries\STM32G0xx_HAL\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_uart.c + + + $PROJ_DIR$\..\libraries\STM32G0xx_HAL\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_uart_ex.c + + + $PROJ_DIR$\..\libraries\STM32G0xx_HAL\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_usart_ex.c + + + $PROJ_DIR$\..\libraries\STM32G0xx_HAL\STM32G0xx_HAL_Driver\Src\stm32g0xx_ll_usart.c + + + diff --git a/bsp/stm32/stm32g070-st-nucleo/project.eww b/bsp/stm32/stm32g070-st-nucleo/project.eww new file mode 100644 index 0000000000000000000000000000000000000000..c2cb02eb1e89d73e24183274c1c886ddf74f9537 --- /dev/null +++ b/bsp/stm32/stm32g070-st-nucleo/project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\project.ewp + + + + + diff --git a/bsp/stm32/stm32g070-st-nucleo/project.uvprojx b/bsp/stm32/stm32g070-st-nucleo/project.uvprojx new file mode 100644 index 0000000000000000000000000000000000000000..309fc164a9f88fb2496e8754b550cd5f9b0f0cc1 --- /dev/null +++ b/bsp/stm32/stm32g070-st-nucleo/project.uvprojx @@ -0,0 +1,762 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + STM32G070RBTx + STMicroelectronics + Keil.STM32G0xx_DFP.1.2.0 + https://www.keil.com/pack/ + IRAM(0x20000000,0x00009000) IROM(0x08000000,0x00020000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32G0xx_128 -FS08000000 -FL020000 -FP0($$Device:STM32G070RBTx$CMSIS\Flash\STM32G0xx_128.FLM)) + 0 + $$Device:STM32G070RBTx$Drivers\CMSIS\Device\ST\STM32G0xx\Include\stm32g0xx.h + + + + + + + + + + $$Device:STM32G070RBTx$CMSIS\SVD\STM32G070.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + template + 1 + 0 + 0 + 1 + 0 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP-MPU + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + -MPU + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x9000 + + + 1 + 0x8000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x9000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + USE_HAL_DRIVER, STM32G070xx + + applications;.;rt-thread\libcpu\arm\common;rt-thread\libcpu\arm\cortex-m0;rt-thread\components\drivers\include;rt-thread\components\drivers\include;rt-thread\components\drivers\include;board;board\CubeMX_Config\Inc;board\ports;libraries\HAL_Drivers;libraries\HAL_Drivers\config;rt-thread\components\finsh;.;rt-thread\include;rt-thread\components\libc\compilers\common;libraries\STM32G0xx_HAL\STM32G0xx_HAL_Driver\Inc;libraries\STM32G0xx_HAL\CMSIS\Device\ST\STM32G0xx\Include;libraries\STM32G0xx_HAL\CMSIS\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + cpu + + + backtrace.c + 1 + rt-thread\libcpu\arm\common\backtrace.c + + + div0.c + 1 + rt-thread\libcpu\arm\common\div0.c + + + showmem.c + 1 + rt-thread\libcpu\arm\common\showmem.c + + + cpuport.c + 1 + rt-thread\libcpu\arm\cortex-m0\cpuport.c + + + context_rvds.S + 2 + rt-thread\libcpu\arm\cortex-m0\context_rvds.S + + + + + DeviceDrivers + + + pin.c + 1 + rt-thread\components\drivers\misc\pin.c + + + serial.c + 1 + rt-thread\components\drivers\serial\serial.c + + + completion.c + 1 + rt-thread\components\drivers\src\completion.c + + + dataqueue.c + 1 + rt-thread\components\drivers\src\dataqueue.c + + + pipe.c + 1 + rt-thread\components\drivers\src\pipe.c + + + ringblk_buf.c + 1 + rt-thread\components\drivers\src\ringblk_buf.c + + + ringbuffer.c + 1 + rt-thread\components\drivers\src\ringbuffer.c + + + waitqueue.c + 1 + rt-thread\components\drivers\src\waitqueue.c + + + workqueue.c + 1 + rt-thread\components\drivers\src\workqueue.c + + + + + Drivers + + + board.c + 1 + board\board.c + + + stm32g0xx_hal_msp.c + 1 + board\CubeMX_Config\Src\stm32g0xx_hal_msp.c + + + startup_stm32g070xx.s + 2 + libraries\STM32G0xx_HAL\CMSIS\Device\ST\STM32G0xx\Source\Templates\arm\startup_stm32g070xx.s + + + drv_gpio.c + 1 + libraries\HAL_Drivers\drv_gpio.c + + + drv_usart.c + 1 + libraries\HAL_Drivers\drv_usart.c + + + drv_common.c + 1 + libraries\HAL_Drivers\drv_common.c + + + + + finsh + + + shell.c + 1 + rt-thread\components\finsh\shell.c + + + cmd.c + 1 + rt-thread\components\finsh\cmd.c + + + msh.c + 1 + rt-thread\components\finsh\msh.c + + + finsh_compiler.c + 1 + rt-thread\components\finsh\finsh_compiler.c + + + finsh_error.c + 1 + rt-thread\components\finsh\finsh_error.c + + + finsh_heap.c + 1 + rt-thread\components\finsh\finsh_heap.c + + + finsh_init.c + 1 + rt-thread\components\finsh\finsh_init.c + + + finsh_node.c + 1 + rt-thread\components\finsh\finsh_node.c + + + finsh_ops.c + 1 + rt-thread\components\finsh\finsh_ops.c + + + finsh_parser.c + 1 + rt-thread\components\finsh\finsh_parser.c + + + finsh_var.c + 1 + rt-thread\components\finsh\finsh_var.c + + + finsh_vm.c + 1 + rt-thread\components\finsh\finsh_vm.c + + + finsh_token.c + 1 + rt-thread\components\finsh\finsh_token.c + + + + + Kernel + + + clock.c + 1 + rt-thread\src\clock.c + + + components.c + 1 + rt-thread\src\components.c + + + device.c + 1 + rt-thread\src\device.c + + + idle.c + 1 + rt-thread\src\idle.c + + + ipc.c + 1 + rt-thread\src\ipc.c + + + irq.c + 1 + rt-thread\src\irq.c + + + kservice.c + 1 + rt-thread\src\kservice.c + + + mem.c + 1 + rt-thread\src\mem.c + + + mempool.c + 1 + rt-thread\src\mempool.c + + + object.c + 1 + rt-thread\src\object.c + + + scheduler.c + 1 + rt-thread\src\scheduler.c + + + signal.c + 1 + rt-thread\src\signal.c + + + thread.c + 1 + rt-thread\src\thread.c + + + timer.c + 1 + rt-thread\src\timer.c + + + + + libc + + + time.c + 1 + rt-thread\components\libc\compilers\common\time.c + + + + + STM32_HAL + + + system_stm32g0xx.c + 1 + libraries\STM32G0xx_HAL\CMSIS\Device\ST\STM32G0xx\Source\Templates\system_stm32g0xx.c + + + stm32g0xx_hal_cec.c + 1 + libraries\STM32G0xx_HAL\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_cec.c + + + stm32g0xx_hal_rcc.c + 1 + libraries\STM32G0xx_HAL\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_rcc.c + + + stm32g0xx_hal_rcc_ex.c + 1 + libraries\STM32G0xx_HAL\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_rcc_ex.c + + + stm32g0xx_hal_flash.c + 1 + libraries\STM32G0xx_HAL\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_flash.c + + + stm32g0xx_hal_flash_ex.c + 1 + libraries\STM32G0xx_HAL\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_flash_ex.c + + + stm32g0xx_hal_dma.c + 1 + libraries\STM32G0xx_HAL\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_dma.c + + + stm32g0xx_hal_dma_ex.c + 1 + libraries\STM32G0xx_HAL\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_dma_ex.c + + + stm32g0xx_hal_pwr.c + 1 + libraries\STM32G0xx_HAL\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_pwr.c + + + stm32g0xx_hal_pwr_ex.c + 1 + libraries\STM32G0xx_HAL\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_pwr_ex.c + + + stm32g0xx_hal_cortex.c + 1 + libraries\STM32G0xx_HAL\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_cortex.c + + + stm32g0xx_hal.c + 1 + libraries\STM32G0xx_HAL\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal.c + + + stm32g0xx_hal_gpio.c + 1 + libraries\STM32G0xx_HAL\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_gpio.c + + + stm32g0xx_hal_uart.c + 1 + libraries\STM32G0xx_HAL\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_uart.c + + + stm32g0xx_hal_uart_ex.c + 1 + libraries\STM32G0xx_HAL\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_uart_ex.c + + + stm32g0xx_hal_usart_ex.c + 1 + libraries\STM32G0xx_HAL\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_usart_ex.c + + + stm32g0xx_ll_usart.c + 1 + libraries\STM32G0xx_HAL\STM32G0xx_HAL_Driver\Src\stm32g0xx_ll_usart.c + + + + + + + + + + + + + + diff --git a/bsp/stm32/stm32g070-st-nucleo/rtconfig.h b/bsp/stm32/stm32g070-st-nucleo/rtconfig.h new file mode 100644 index 0000000000000000000000000000000000000000..6abecff5f80def00a7419c24e695929fd6896f49 --- /dev/null +++ b/bsp/stm32/stm32g070-st-nucleo/rtconfig.h @@ -0,0 +1,169 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_DEBUG +#define RT_DEBUG_COLOR + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart2" +#define RT_VER_NUM 0x40003 +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M0 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_LIBC_USING_TIME + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + +#define SOC_FAMILY_STM32 +#define SOC_SERIES_STM32G0 + +/* Hardware Drivers Config */ + +#define SOC_STM32G070RB + +/* Onboard Peripheral Drivers */ + +#define BSP_USING_USB_TO_UART + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART2 + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/stm32/stm32g070-st-nucleo/rtconfig.py b/bsp/stm32/stm32g070-st-nucleo/rtconfig.py new file mode 100644 index 0000000000000000000000000000000000000000..d279b236588a5005a420053041dfdc88023b00ac --- /dev/null +++ b/bsp/stm32/stm32g070-st-nucleo/rtconfig.py @@ -0,0 +1,150 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m0' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m0plus -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M0 ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M0' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M0' + AFLAGS += ' --fpu None' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/stm32/stm32g070-st-nucleo/template.ewp b/bsp/stm32/stm32g070-st-nucleo/template.ewp new file mode 100644 index 0000000000000000000000000000000000000000..9c6d9a994e6caed574a1e073e6a62e4492b344ac --- /dev/null +++ b/bsp/stm32/stm32g070-st-nucleo/template.ewp @@ -0,0 +1,2074 @@ + + + 3 + + rt-thread + + ARM + + 1 + + General + 3 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 35 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 35 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + diff --git a/bsp/stm32/stm32g070-st-nucleo/template.eww b/bsp/stm32/stm32g070-st-nucleo/template.eww new file mode 100644 index 0000000000000000000000000000000000000000..bd036bb4c98c1598f04b85f64b0dff37f6ec6028 --- /dev/null +++ b/bsp/stm32/stm32g070-st-nucleo/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/stm32/stm32g070-st-nucleo/template.uvprojx b/bsp/stm32/stm32g070-st-nucleo/template.uvprojx new file mode 100644 index 0000000000000000000000000000000000000000..585b403d784794fd13867b4fd0ed303aa558814b --- /dev/null +++ b/bsp/stm32/stm32g070-st-nucleo/template.uvprojx @@ -0,0 +1,390 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + STM32G070RBTx + STMicroelectronics + Keil.STM32G0xx_DFP.1.2.0 + https://www.keil.com/pack/ + IRAM(0x20000000,0x00009000) IROM(0x08000000,0x00020000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32G0xx_128 -FS08000000 -FL020000 -FP0($$Device:STM32G070RBTx$CMSIS\Flash\STM32G0xx_128.FLM)) + 0 + $$Device:STM32G070RBTx$Drivers\CMSIS\Device\ST\STM32G0xx\Include\stm32g0xx.h + + + + + + + + + + $$Device:STM32G070RBTx$CMSIS\SVD\STM32G070.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + template + 1 + 0 + 0 + 1 + 0 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP-MPU + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + -MPU + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4104 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x9000 + + + 1 + 0x8000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x9000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + + + + + + + + diff --git a/bsp/tm4c123bsp/.config b/bsp/tm4c123bsp/.config new file mode 100644 index 0000000000000000000000000000000000000000..2a5a430b36b5353af4eda79f534364e976eade3d --- /dev/null +++ b/bsp/tm4c123bsp/.config @@ -0,0 +1,478 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_COLOR is not set +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x40003 +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_PIN=y +CONFIG_RT_USING_ADC=y +CONFIG_RT_USING_PWM=y +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_QSPI is not set +# CONFIG_RT_USING_SPI_MSD is not set +# CONFIG_RT_USING_SFUD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_URLENCODE is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_BSP_USING_SPI1 is not set +# CONFIG_BSP_USING_SPI2 is not set +# CONFIG_BSP_USING_SPI3 is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set + +# +# Hardware Drivers Config +# +CONFIG_tm4c123=y + +# +# Onboard Peripheral Drivers +# +CONFIG_BSP_USING_USB_TO_USART=y +# CONFIG_BSP_USING_RS485_OR_RS232 is not set +# CONFIG_BSP_USING_SPI_FLASH is not set +# CONFIG_BSP_USING_RGB is not set +# CONFIG_BSP_USING_POT is not set +# CONFIG_BSP_USING_EEPROM is not set +# CONFIG_BSP_USING_ETH is not set +# CONFIG_BSP_USING_SDCARD is not set + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_UART1_RX_USING_DMA is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_ON_CHIP_FLASH is not set +CONFIG_BSP_USING_SPI=y +CONFIG_BSP_USING_SPI0=y +# CONFIG_BSP_USING_I2C1 is not set +# CONFIG_BSP_USING_TIM is not set +CONFIG_BSP_USING_PWM=y +# CONFIG_BSP_USING_PWM0 is not set +# CONFIG_BSP_USING_PWM1 is not set +# CONFIG_BSP_USING_PWM2 is not set +# CONFIG_BSP_USING_PWM3 is not set +# CONFIG_BSP_USING_PWM4 is not set +# CONFIG_BSP_USING_PWM5 is not set +# CONFIG_BSP_USING_PWM6 is not set +CONFIG_BSP_USING_PWM7=y +CONFIG_BSP_USING_ADC=y +CONFIG_BSP_USING_ADC0=y +# CONFIG_BSP_USING_ADC1 is not set +# CONFIG_BSP_USING_ONCHIP_RTC is not set +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_SDIO is not set +# CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_USBD is not set +# CONFIG_BSP_USING_CRC is not set + +# +# Board extended module Drivers +# diff --git a/bsp/tm4c123bsp/Kconfig b/bsp/tm4c123bsp/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..55a92c308ffe28d5f4e3c7a32f0f3dfc7ce242f0 --- /dev/null +++ b/bsp/tm4c123bsp/Kconfig @@ -0,0 +1,21 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "board/Kconfig" + diff --git a/bsp/tm4c123bsp/README.md b/bsp/tm4c123bsp/README.md new file mode 100644 index 0000000000000000000000000000000000000000..8fbcae5fef0a0333902bec148d831df13221a18e --- /dev/null +++ b/bsp/tm4c123bsp/README.md @@ -0,0 +1,123 @@ +# BSP README 模板 + +## 简介 + +本文档为ek-tm4c123gxl开发板的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +【此处简单介绍一下开发板】 + +开发板外观如下图所示： + +![](E:\00MyWorkSpace\tm4c123_rtos\tm4c123bsp\figures\board.jpg) + +该开发板常用 **板载资源** 如下： + +- MCU：TM4C123Gh6PM，主频 80MHz，256KB FLASH ，32KB RAM +- 外部 RAM：型号，xMB +- 外部 FLASH：型号，xMB +- 常用外设 + - LED：1个三色，（红色，PF1），（蓝色，PF2）,（绿色，PF3） + - 按键：2个，SW1（PF4），SW2（兼具唤醒功能，PF0） +- 常用接口：ICDI（具串口功能）、USB接口 +- 调试接口，ICDI + +开发板更多详细信息请参考【TI】 [TM4C123G开发板介绍](https://www.ti.com/tool/EK-TM4C123GXL?DCMP=stellaris-launchpad&HQS=tm4c123g-launchpad)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :----------------- | :----------: | :------------------------------------- | +| USB 转串口 | 支持 | | +| SPI Flash | 暂不支持 | | +| 以太网 | 暂不支持 | | +| SD卡 | 暂不支持 | | +| CAN | 暂不支持 | | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | PF0, PF1... PF4---> PIN: 0, 1...4 | +| UART | 支持 | UART0/1/2/3 | +| SPI | 支持 | SPI0/1/2 | +| I2C | 支持 | 软件 I2C | +| SDIO | 暂不支持 | 即将支持 | +| RTC | 暂不支持 | 即将支持 | +| PWM | 支持 | PWM0/1/2/3/4/5/6/7 | +| USB Device | 暂不支持 | 即将支持 | +| USB Host | 暂不支持 | 即将支持 | +| IWG | 暂不支持 | 即将支持 | +| **扩展模块** | **支持情况** | **备注** | +| xxx 模块 | 支持 | | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用数据线连接开发板到 PC，打开电源开关。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 ICDI 仿真器下载程序，在通过USB连接开发板的基础上，点击下载按钮即可下载程序到开发板 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，【这里写开发板运行起来之后的现象，如：LED 闪烁等】。 + +连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 3.1.1 build Nov 19 2018 + 2006 - 2018 Copyright by rt-thread team +msh > +``` +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口0 的功能，如果需使用 SD 卡、Flash 等更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 + +本章节更多详细的介绍请结合 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)学习使用。 + +## 注意事项 + +- 本BSP配置片上外设在board/tm4c123gh6pz_config.c/h中进行配置。配置时钟在board.c文件中进行 + +## 联系人信息 + +维护人: + +- [AHTYDHD](https://github.com/LYH-ux), 邮箱：<1780328728@qq.com> \ No newline at end of file diff --git a/bsp/tm4c123bsp/SConscript b/bsp/tm4c123bsp/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..20f7689c53ca71a676748f79187f9764065466c5 --- /dev/null +++ b/bsp/tm4c123bsp/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/tm4c123bsp/SConstruct b/bsp/tm4c123bsp/SConstruct new file mode 100644 index 0000000000000000000000000000000000000000..66c8aefddcebcf201dff71251707245e2c6a13f3 --- /dev/null +++ b/bsp/tm4c123bsp/SConstruct @@ -0,0 +1,64 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +# set RTT_ROOT +#if not os.getenv("RTT_ROOT"): + #RTT_ROOT="rt-thread" + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rt-thread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +tm4c123_library = 'TivaWare_C_series' +rtconfig.BSP_LIBRARY_TYPE = tm4c123_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, tm4c123_library, 'SConscript'))) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'Drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/tm4c123bsp/applications/SConscript b/bsp/tm4c123bsp/applications/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..04f04dd5435cd69acd90735e75caaffc0ba0d9ff --- /dev/null +++ b/bsp/tm4c123bsp/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/tm4c123bsp/applications/main.c b/bsp/tm4c123bsp/applications/main.c new file mode 100644 index 0000000000000000000000000000000000000000..3d5b70bcb9adbd57c6070e8ea339b749a488da62 --- /dev/null +++ b/bsp/tm4c123bsp/applications/main.c @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-27 AHTYDHD the first version + */ + +#include +#include + +int main(void) +{ + int count = 1; + /* set LED0 pin mode to output */ + rt_pin_mode(2, PIN_MODE_OUTPUT); + + while (count++) + { + rt_pin_write(2, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(2, PIN_LOW); + rt_thread_mdelay(500); + } + + return RT_EOK; +} diff --git a/bsp/tm4c123bsp/board/Kconfig b/bsp/tm4c123bsp/board/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..db5b976281d51627fb39c799ff017bff734192a5 --- /dev/null +++ b/bsp/tm4c123bsp/board/Kconfig @@ -0,0 +1,349 @@ +menu "Hardware Drivers Config" + +config tm4c123 + bool + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + + +menu "Onboard Peripheral Drivers" + + config BSP_USING_USB_TO_USART + bool "Enable USB TO USART (uart1)" + select BSP_USING_UART + select BSP_USING_UART1 + default y + + config BSP_USING_RS485_OR_RS232 + bool "Enable RS485/RS232 (uart2 be shared)" + select BSP_USING_UART2 + default n + + config BSP_USING_SPI_FLASH + bool "Enable SPI FLASH (W25Q64 spi1)" + select BSP_USING_SPI + select BSP_USING_SPI1 + select RT_USING_SFUD + select RT_SFUD_USING_SFDP + default n + + config BSP_USING_RGB + bool "Enable RGB LED (timer3 channel2 - 4)" + select RT_USING_PWM + select BSP_USING_PWM + select BSP_USING_PWM3 + select BSP_USING_PWM3_CH2 + select BSP_USING_PWM3_CH3 + select BSP_USING_PWM3_CH4 + default n + + config BSP_USING_POT + bool "Enable potentiometer" + select BSP_USING_ADC + select BSP_USING_ADC1 + default n + + config BSP_USING_EEPROM + bool "Enable I2C EEPROM (i2c1)" + select BSP_USING_I2C1 + default n + + config BSP_USING_ETH + bool "Enable Ethernet Driver (spi2)" + default n + select PKG_USING_WIZNET + select WIZNET_DEVICE_EXTERN_CONFIG + select BSP_USING_SPI2 + if BSP_USING_ETH + if WIZNET_DEVICE_EXTERN_CONFIG + config WIZ_SPI_DEVICE + string + default "spi20" + + config WIZ_RST_PIN + int + default 111 + + config WIZ_IRQ_PIN + int + default 104 + endif + + config EXTERNAL_PHY_ADDRESS + hex + default 0x00 + + endif + + config BSP_USING_SDCARD + bool "Enable SDCARD (sdio)" + select BSP_USING_SDIO + select RT_USING_DFS + select RT_USING_DFS_ELMFAT + default n + +endmenu + +menu "On-chip Peripheral Drivers" + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART0 + bool "Enable UART0" + default y + + config BSP_USING_UART1 + bool "Enable UART1" + default n + + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART2 + bool "Enable UART2" + default n + + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART3 + bool "Enable UART3" + default n + + config BSP_UART3_RX_USING_DMA + bool "Enable UART3 RX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + endif + + config BSP_USING_ON_CHIP_FLASH + bool "Enable on-chip FLASH" + default n + + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI0 + bool "Enable SPI0 BUS" + default n + + config BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n + + config BSP_SPI1_TX_USING_DMA + bool "Enable SPI1 TX DMA" + depends on BSP_USING_SPI1 + default n + + config BSP_SPI1_RX_USING_DMA + bool "Enable SPI1 RX DMA" + depends on BSP_USING_SPI1 + select BSP_SPI1_TX_USING_DMA + default n + + config BSP_USING_SPI2 + bool "Enable SPI2 BUS" + default n + + config BSP_SPI2_TX_USING_DMA + bool "Enable SPI2 TX DMA" + depends on BSP_USING_SPI2 + default n + + config BSP_SPI2_RX_USING_DMA + bool "Enable SPI2 RX DMA" + depends on BSP_USING_SPI2 + select BSP_SPI2_TX_USING_DMA + default n + + config BSP_USING_SPI3 + bool "Enable SPI3 BUS" + default n + + config BSP_SPI3_TX_USING_DMA + bool "Enable SPI3 TX DMA" + depends on BSP_USING_SPI3 + default n + + config BSP_SPI3_RX_USING_DMA + bool "Enable SPI3 RX DMA" + depends on BSP_USING_SPI3 + select BSP_SPI3_TX_USING_DMA + default n + endif + + menuconfig BSP_USING_I2C1 + bool "Enable I2C1 BUS (software simulation)" + default n + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C1 + config BSP_I2C1_SCL_PIN + int "i2c1 scl pin number" + range 0 175 + default 22 + config BSP_I2C1_SDA_PIN + int "I2C1 sda pin number" + range 0 175 + default 23 + endif + + menuconfig BSP_USING_TIM + bool "Enable timer" + default n + select RT_USING_HWTIMER + if BSP_USING_TIM + config BSP_USING_TIM2 + bool "Enable TIM2" + default n + + config BSP_USING_TIM3 + bool "Enable TIM3" + default n + + config BSP_USING_TIM4 + bool "Enable TIM4" + default n + + config BSP_USING_TIM5 + bool "Enable TIM5" + default n + endif + + menuconfig BSP_USING_PWM + bool "Enable pwm" + default n + select RT_USING_PWM + if BSP_USING_PWM + menuconfig BSP_USING_PWM0 + bool "Enable pwm0" + default n + if BSP_USING_PWM0 + config BSP_USING_PWM0_CH1 + bool "Enable PWM0 channel1" + default y + + config BSP_USING_PWM0_CH2 + bool "Enable PWM0 channel2" + default n + endif + config BSP_USING_PWM1 + bool "Enable pwm1" + default n + config BSP_USING_PWM2 + bool "Enable pwm2" + default n + config BSP_USING_PWM3 + bool "Enable pwm3" + default n + config BSP_USING_PWM4 + bool "Enable pwm4" + default n + config BSP_USING_PWM5 + bool "Enable pwm5" + default n + config BSP_USING_PWM6 + bool "Enable pwm6" + default n + config BSP_USING_PWM7 + bool "Enable pwm7" + default n + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + config BSP_USING_ADC0 + bool "Enable ADC0" + default n + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + endif + + menuconfig BSP_USING_ONCHIP_RTC + bool "Enable RTC" + select RT_USING_RTC + select RT_USING_LIBC + default n + if BSP_USING_ONCHIP_RTC + choice + prompt "Select clock source" + default BSP_RTC_USING_LSE + + config BSP_RTC_USING_LSE + bool "RTC USING LSE" + + config BSP_RTC_USING_LSI + bool "RTC USING LSI" + endchoice + endif + + config BSP_USING_WDT + bool "Enable Watchdog Timer" + select RT_USING_WDT + default n + + config BSP_USING_SDIO + bool "Enable SDIO" + select RT_USING_SDIO + select RT_USING_DFS + default n + + menuconfig BSP_USING_CAN + bool "Enable CAN" + default n + select RT_USING_CAN + if BSP_USING_CAN + config BSP_USING_CAN1 + bool "using CAN1" + default n + endif + + config BSP_USING_USBD + bool "Enable USB device" + select RT_USING_USB_DEVICE + default n + if BSP_USING_USBD + config BSP_USB_CONNECT_PIN + int "USB connect pin" + default 67 + + config BSP_USB_PULL_UP_STATUS + int "USB PULL UP STATUS" + default 0 + endif + config BSP_USING_CRC + bool "Enable CRC (CRC-32 0x04C11DB7 Polynomial)" + select RT_USING_HWCRYPTO + select RT_HWCRYPTO_USING_CRC + # "Crypto device frame dose not support above 8-bits granularity" + # "Reserve progress, running well, about 32-bits granularity, such as stm32f1, stm32f4" + default n + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/tm4c123bsp/board/SConscript b/bsp/tm4c123bsp/board/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..87558a20ee8293c70cba10a5fab80ebc7a084cf0 --- /dev/null +++ b/bsp/tm4c123bsp/board/SConscript @@ -0,0 +1,33 @@ +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() + +# add general drivers +src = Split(''' +board.c +tm4c123_config.c +''') + +path = [cwd] +#path += [cwd + '/CubeMX_Config/Inc'] + +startup_path_prefix = SDK_LIB + +if rtconfig.CROSS_TOOL == 'gcc': + src += [startup_path_prefix + '/TivaWare_C_series/tm4c123_driverlib/startup/gcc/startup_gcc.c'] +elif rtconfig.CROSS_TOOL == 'keil': + src += [startup_path_prefix + '/TivaWare_C_series/tm4c123_driverlib/startup/arm/startup_rvmdk.S'] +elif rtconfig.CROSS_TOOL == 'iar': + src += [startup_path_prefix + '/TivaWare_C_series/tm4c123_driverlib/startup/iar/startup_rvmdk.S'] + + +CPPDEFINES = ['PART_TM4C123GH6PM'] +CPPDEFINES += ['TARGET_IS_TM4C123_RB1'] +if rtconfig.CROSS_TOOL == 'keil': + CPPDEFINES += ['rvmdk'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) +Return('group') diff --git a/bsp/tm4c123bsp/board/board.c b/bsp/tm4c123bsp/board/board.c new file mode 100644 index 0000000000000000000000000000000000000000..5e4b8baa58b0081083edb313b7b6ee88e2478823 --- /dev/null +++ b/bsp/tm4c123bsp/board/board.c @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-07-24 Tanek the first version + * 2018-11-12 Ernest Chen modify copyright + * 2020-06-27 AHTYDHD modify to adapt in TM4C123 + */ + +#include +#include +#include "inc/hw_sysctl.h" +#include "inc/hw_memmap.h" +#include "driverlib/fpu.h" +#include "driverlib/sysctl.h" +#include "driverlib/systick.h" +#include "board.h" + +uint32_t SystemCoreClock; + +/* this function set the system clock */ +void SystemCoreClockUpdate(void) +{ + FPULazyStackingEnable(); + /* Set the clocking to run directly from the crystal. 50MHz*/ + SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | + SYSCTL_OSC_MAIN); + SystemCoreClock = SysCtlClockGet(); +} + +/* this funtion set the Systick and enable systick int */ +void SysTickConfig() +{ + SysTickDisable(); + SysTickPeriodSet(SystemCoreClock / RT_TICK_PER_SECOND); + SysTickIntEnable(); + SysTickEnable(); +} + +/** + * This function will initial your board. + */ +void rt_hw_board_init() +{ + /* System Clock Update */ + SystemCoreClockUpdate(); + /* System Tick Configuration */ + SysTickConfig(); + +#ifdef RT_USING_SERIAL + rt_hw_usart_init(); +#endif +#ifdef RT_USING_PIN + rt_hw_pin_init(); +#endif +#ifdef RT_USING_PWM + rt_hw_pwm_init(); +#endif + /* Call components board initial (use INIT_BOARD_EXPORT()) */ +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + /* set the console device */ + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); + +#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP) + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + +} + +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + rt_tick_increase(); + /* leave interrupt */ + rt_interrupt_leave(); +} diff --git a/bsp/tm4c123bsp/board/board.h b/bsp/tm4c123bsp/board/board.h new file mode 100644 index 0000000000000000000000000000000000000000..cd1647ec15c666f35cb1e28f2a3e8b73144d449a --- /dev/null +++ b/bsp/tm4c123bsp/board/board.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-27 AHTYDHD the first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include + +#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP) + #define TM4C123_SRAM1_START (0x20000000) + #define TM4C123_SRAM1_END (TM4C123_SRAM1_START + 32 * 1024) // end address = 0x20000000(base adddress) + 32K(RAM size) + + #if defined(__CC_ARM) || defined(__CLANG_ARM) + extern int Image$$RW_IRAM$$ZI$$Limit; // RW_IRAM + #define HEAP_BEGIN ((void *)&Image$$RW_IRAM$$ZI$$Limit) + #elif __ICCARM__ + #pragma section="HEAP" + #define HEAP_BEGIN (__segment_end("HEAP")) + #else + extern int _ebss; + #define HEAP_BEGIN ((void *)&_ebss) + #endif + #define HEAP_END TM4C123_SRAM1_END +#endif + +#ifdef RT_USING_PIN + #include "drv_gpio.h" +#endif /* RT_USING_PIN */ + +#ifdef RT_USING_SERIAL + #include "drv_uart.h" +#endif /* RT_USING_SERIAL */ + +#ifdef RT_USING_PWM + #include "drv_pwm.h" +#endif /* RT_USING_PWM*/ + +#ifdef RT_USING_SPI + #include "drv_spi.h" +#endif /* RT_USING_SPI*/ + +#endif /*__BOARD_H__*/ + +/************************** end of file ******************/ \ No newline at end of file diff --git a/bsp/tm4c123bsp/board/linker_scripts/link.icf b/bsp/tm4c123bsp/board/linker_scripts/link.icf new file mode 100644 index 0000000000000000000000000000000000000000..953c77e9098454a0d86936573220f04fea2e8f02 --- /dev/null +++ b/bsp/tm4c123bsp/board/linker_scripts/link.icf @@ -0,0 +1,78 @@ +//***************************************************************************** +// +// hello.icf - Linker configuration file for hello. +// +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2.1.4.178 of the EK-TM4C123GXL Firmware Package. +// +//***************************************************************************** + +// +// Define a memory region that covers the entire 4 GB addressible space of the +// processor. +// +define memory mem with size = 4G; + +// +// Define a region for the on-chip flash. +// +define region FLASH = mem:[from 0x00000000 to 0x0003ffff]; + +// +// Define a region for the on-chip SRAM. +// +define region SRAM = mem:[from 0x20000000 to 0x20007fff]; + +// +// Define a block for the heap. The size should be set to something other +// than zero if things in the C library that require the heap are used. +// +define block HEAP with alignment = 8, size = 0x00000000 { }; + +// +// Indicate that the read/write values should be initialized by copying from +// flash. +// +initialize by copy { readwrite }; + +// +// Indicate that the noinit values should be left alone. This includes the +// stack, which if initialized will destroy the return address from the +// initialization code, causing the processor to branch to zero and fault. +// +do not initialize { section .noinit }; + +// +// Place the interrupt vectors at the start of flash. +// +place at start of FLASH { readonly section .intvec }; + +// +// Place the remainder of the read-only items into flash. +// +place in FLASH { readonly }; + +// +// Place the RAM vector table at the start of SRAM. +// +place at start of SRAM { section VTABLE }; + +// +// Place all read/write items into SRAM. +// +place in SRAM { readwrite, block HEAP }; diff --git a/bsp/tm4c123bsp/board/linker_scripts/link.ld b/bsp/tm4c123bsp/board/linker_scripts/link.ld new file mode 100644 index 0000000000000000000000000000000000000000..f207943565840767372e25c1a5326b43196f54e4 --- /dev/null +++ b/bsp/tm4c123bsp/board/linker_scripts/link.ld @@ -0,0 +1,58 @@ +/****************************************************************************** + * + * hello.ld - Linker configuration file for hello. + * + * Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. + * Software License Agreement + * + * Texas Instruments (TI) is supplying this software for use solely and + * exclusively on TI's microcontroller products. The software is owned by + * TI and/or its suppliers, and is protected under applicable copyright + * laws. You may not combine this software with "viral" open-source + * software in order to form a larger program. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. + * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT + * NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY + * CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL + * DAMAGES, FOR ANY REASON WHATSOEVER. + * + * This is part of revision 2.1.4.178 of the EK-TM4C123GXL Firmware Package. + * + *****************************************************************************/ + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 +} + +SECTIONS +{ + .text : + { + _text = .; + KEEP(*(.isr_vector)) + *(.text*) + *(.rodata*) + _etext = .; + } > FLASH + + .data : AT(ADDR(.iplt) ) + { + _data = .; + _ldata = LOADADDR (.data); + *(vtable) + *(.data*) + _edata = .; + } > SRAM + + .bss : + { + _bss = .; + *(.bss*) + *(COMMON) + _ebss = .; + } > SRAM +} diff --git a/bsp/tm4c123bsp/board/linker_scripts/link.sct b/bsp/tm4c123bsp/board/linker_scripts/link.sct new file mode 100644 index 0000000000000000000000000000000000000000..58f2ff6f661b65cd9a17f5400b98b205a942d6d7 --- /dev/null +++ b/bsp/tm4c123bsp/board/linker_scripts/link.sct @@ -0,0 +1,47 @@ +;****************************************************************************** +; +; hello.sct - Linker configuration file for hello. +; +; Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +; Software License Agreement +; +; Texas Instruments (TI) is supplying this software for use solely and +; exclusively on TI's microcontroller products. The software is owned by +; TI and/or its suppliers, and is protected under applicable copyright +; laws. You may not combine this software with "viral" open-source +; software in order to form a larger program. +; +; THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +; NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +; NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +; A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +; CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +; DAMAGES, FOR ANY REASON WHATSOEVER. +; +; This is part of revision 2.1.4.178 of the EK-TM4C123GXL Firmware Package. +; +;****************************************************************************** + +LR_IROM 0x00000000 0x00040000 +{ + ; + ; Specify the Execution Address of the code and the size. + ; + ER_IROM 0x00000000 0x00040000 + { + *.o (RESET, +First) + * (InRoot$$Sections, +RO) + } + + ; + ; Specify the Execution Address of the data area. + ; + RW_IRAM 0x20000000 0x00008000 + { + ; + ; Uncomment the following line in order to use IntRegister(). + ; + ;* (vtable, +First) + * (+RW, +ZI) + } +} diff --git a/bsp/tm4c123bsp/board/tm4c123_config.c b/bsp/tm4c123bsp/board/tm4c123_config.c new file mode 100644 index 0000000000000000000000000000000000000000..781f2a504e19ce31ada65be7edc930c18c14b39a --- /dev/null +++ b/bsp/tm4c123bsp/board/tm4c123_config.c @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-27 AHTYDHD the first version + */ + +#include +#include +#include +#include "inc/hw_memmap.h" +#include "driverlib/pin_map.h" +#include "driverlib/sysctl.h" +#include "driverlib/gpio.h" +#include "tm4c123_config.h" + +#ifdef RT_USING_SERIAL + #include "driverlib/uart.h" +#endif /* RT_USING_SERIAL */ +#ifdef RT_USING_ADC + #include "driverlib/adc.h" +#endif /* RT_USING_ADC */ +#ifdef RT_USING_PWM + #include "driverlib/pwm.h" +#endif /* RT_USING_PWM */ +#ifdef RT_USING_SPI + #include "driverlib/ssi.h" +#endif /* RT_USING_SPI */ + + +#ifdef RT_USING_SERIAL +void uart_hw_config(void) +{ + /* UART0 */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + GPIOPinConfigure(GPIO_PA0_U0RX); + GPIOPinConfigure(GPIO_PA1_U0TX); + GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); + /* UART1 */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART1); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); + GPIOPinConfigure(GPIO_PC4_U1RX); + GPIOPinConfigure(GPIO_PC5_U1TX); + GPIOPinTypeUART(GPIO_PORTC_BASE, GPIO_PIN_4 | GPIO_PIN_5); +} +#endif /* RT_USING_SERIAL */ + +#ifdef RT_USING_ADC +void adc_hw_config(void) +{ + /* ADC0 */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD); + GPIOPinTypeADC(GPIO_PORTD_BASE, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3); +} +#endif /* RT_USING_ADC */ + +#ifdef RT_USING_PWM +void pwm_hw_config(void) +{ + /* PWM7 (PWM1 module,M1PWM6 and M1PWM7) */ + SysCtlPWMClockSet(SYSCTL_PWMDIV_2); + SysCtlPeripheralEnable(SYSCTL_PERIPH_PWM1); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF); + GPIOPinConfigure(GPIO_PF2_M1PWM6); + GPIOPinConfigure(GPIO_PF3_M1PWM7); + GPIOPinTypePWM(GPIO_PORTF_BASE, GPIO_PIN_2 | GPIO_PIN_3); +} +#endif /* RT_USING_PWM */ + +#ifdef RT_USING_SPI +void spi_hw_config(void) +{ + /* SPI0 */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + GPIOPinConfigure(GPIO_PA2_SSI0CLK); + GPIOPinConfigure(GPIO_PA4_SSI0RX); + GPIOPinConfigure(GPIO_PA5_SSI0TX); + GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_5 | GPIO_PIN_4 | GPIO_PIN_2); +} +#endif /* RT_USING_SPI */ + +/************************** end of file ******************/ \ No newline at end of file diff --git a/bsp/tm4c123bsp/board/tm4c123_config.h b/bsp/tm4c123bsp/board/tm4c123_config.h new file mode 100644 index 0000000000000000000000000000000000000000..38128bc60fa8d18b1b18bd92843b5a6d902092ab --- /dev/null +++ b/bsp/tm4c123bsp/board/tm4c123_config.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-27 AHTYDHD the first version + */ + +#ifndef __TM4C123GH6PZ_CONFIG_H__ +#define __TM4C123GH6PZ_CONFIG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef RT_USING_SERIAL +void uart_hw_config(void); +#endif /* RT_USING_SERIAL */ +#ifdef RT_USING_ADC +void adc_hw_config(void); +#endif /* RT_USING_ADC */ +#ifdef RT_USING_PWM +void pwm_hw_config(void); +#endif /* RT_USING_PWM */ +#ifdef RT_USING_SPI +void spi_hw_config(void); +#endif /* RT_USING_SPI */ + +#ifdef __cplusplus +} +#endif + +#endif /*__TM4C123GH6PZ_CONFIG_H__*/ + +/************************** end of file ******************/ + diff --git a/bsp/tm4c123bsp/figures/board.jpg b/bsp/tm4c123bsp/figures/board.jpg new file mode 100644 index 0000000000000000000000000000000000000000..938f0b3c8269b76937118f74501b8567cf997d2a Binary files /dev/null and b/bsp/tm4c123bsp/figures/board.jpg differ diff --git a/bsp/tm4c123bsp/libraries/Drivers/SConscript b/bsp/tm4c123bsp/libraries/Drivers/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..50ef944d57977a11b9d2d9d06e60567fd84ea2df --- /dev/null +++ b/bsp/tm4c123bsp/libraries/Drivers/SConscript @@ -0,0 +1,101 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(""" +""") + +if GetDepend(['RT_USING_PIN']): + src += ['drv_gpio.c'] + +if GetDepend(['RT_USING_SERIAL']): + src += ['drv_uart.c'] + +if GetDepend(['RT_USING_HWTIMER']): + src += ['drv_hwtimer.c'] + +if GetDepend(['RT_USING_PWM']): + src += ['drv_pwm.c'] + +if GetDepend(['RT_USING_SPI']): + src += ['drv_spi.c'] + +if GetDepend(['RT_USING_QSPI']): + src += ['drv_qspi.c'] + +if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']): + if GetDepend('BSP_USING_I2C1') or GetDepend('BSP_USING_I2C2') or GetDepend('BSP_USING_I2C3') or GetDepend('BSP_USING_I2C4'): + src += ['drv_soft_i2c.c'] + +if GetDepend(['BSP_USING_ETH', 'RT_USING_LWIP']): + src += ['drv_eth.c'] + +if GetDepend(['RT_USING_ADC']): + src += Glob('drv_adc.c') + +if GetDepend(['RT_USING_CAN']): + src += ['drv_can.c'] + +if GetDepend(['RT_USING_PM', 'SOC_SERIES_STM32L4']): + src += ['drv_pm.c'] + src += ['drv_lptim.c'] + +if GetDepend('BSP_USING_SDRAM'): + src += ['drv_sdram.c'] + +if GetDepend('BSP_USING_LCD'): + src += ['drv_lcd.c'] + +if GetDepend('BSP_USING_LCD_MIPI'): + src += ['drv_lcd_mipi.c'] + +if GetDepend('BSP_USING_ONCHIP_RTC'): + src += ['drv_rtc.c'] + +if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F0']): + src += ['drv_flash/drv_flash_f0.c'] + +if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F1']): + src += ['drv_flash/drv_flash_f1.c'] + +if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F2']): + src += ['drv_flash/drv_flash_f2.c'] + +if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F4']): + src += ['drv_flash/drv_flash_f4.c'] + +if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F7']): + src += ['drv_flash/drv_flash_f7.c'] + +if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32L4']): + src += ['drv_flash/drv_flash_l4.c'] + +if GetDepend('RT_USING_HWCRYPTO'): + src += ['drv_crypto.c'] + +if GetDepend(['BSP_USING_WDT']): + src += ['drv_wdt.c'] + +if GetDepend(['BSP_USING_SDIO']): + src += ['drv_sdio.c'] + +if GetDepend(['BSP_USING_USBD']): + src += ['drv_usbd.c'] + +if GetDepend(['BSP_USING_PULSE_ENCODER']): + src += ['drv_pulse_encoder.c'] + +#src += ['drv_common.c'] + +path = [cwd] +path += [cwd + '/config'] + +if GetDepend('BSP_USING_ON_CHIP_FLASH'): + path += [cwd + '/drv_flash'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/tm4c123bsp/libraries/Drivers/config/adc_config.h b/bsp/tm4c123bsp/libraries/Drivers/config/adc_config.h new file mode 100644 index 0000000000000000000000000000000000000000..cfeb25602078bf1acd0227a5b5693a754216a7c8 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/Drivers/config/adc_config.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-27 AHTYDHD the first version + */ + +#ifndef __ADC_CONFIG_H__ +#define __ADC_CONFIG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_ADC0 +#ifndef ADC0_CONFIG +#define ADC0_CONFIG \ + { \ + .name ="adc0", \ + .adcbase = ADC0_BASE, \ + .channel = 0 , \ + .sequence = 2 , \ + .trigermode = ADC_TRIGGER_PROCESSOR, \ + .sequencepriority = 0 \ + } +#endif /* ADC0_CONFIG */ +#endif /* BSP_USING_ADC0 */ + +#ifdef BSP_USING_ADC1 +#ifndef ADC1_CONFIG +#define ADC1_CONFIG \ + { \ + .name = "adc1", \ + .adcbase = ADC1_BASE, \ + .channel = 0 , \ + .sequence = 3 , \ + .syncMode = ADC_TRIGGER_PROCESSOR, \ + .sequencepriority = 0 \ + } +#endif /* ADC1_CONFIG */ +#endif /* BSP_USING_ADC1 */ + +#ifdef __cplusplus +} +#endif + +#endif /*__ADC_CONFIG_H__*/ + +/************************** end of file ******************/ \ No newline at end of file diff --git a/bsp/tm4c123bsp/libraries/Drivers/config/pwm_config.h b/bsp/tm4c123bsp/libraries/Drivers/config/pwm_config.h new file mode 100644 index 0000000000000000000000000000000000000000..e44eb372e457efae65554f47b82b60b8f1613d0c --- /dev/null +++ b/bsp/tm4c123bsp/libraries/Drivers/config/pwm_config.h @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-27 AHTYDHD the first version + */ + +#ifndef __PWM_CONFIG_H__ +#define __PWM_CONFIG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_PWM0 +#ifndef PWM0_CONFIG +#define PWM0_CONFIG \ + { \ + .name = "pwm0", \ + .channel = 0 , \ + .counterMode = PWM_GEN_MODE_UP_DOWN , \ + .syncMode = PWM_GEN_MODE_NO_SYNC \ + } +#endif /* PWM0_CONFIG */ +#endif /* BSP_USING_PWM0 */ + +#ifdef BSP_USING_PWM1 +#ifndef PWM1_CONFIG +#define PWM1_CONFIG \ + { \ + .name = "pwm1", \ + .channel = 0 , \ + .counterMode = PWM_GEN_MODE_UP_DOWN , \ + .syncMode = PWM_GEN_MODE_NO_SYNC \ + } +#endif /* PWM1_CONFIG */ +#endif /* BSP_USING_PWM1 */ + +#ifdef BSP_USING_PWM2 +#ifndef PWM2_CONFIG +#define PWM2_CONFIG \ + { \ + .name = "pwm2", \ + .channel = 0 , \ + .counterMode = PWM_GEN_MODE_UP_DOWN , \ + .syncMode = PWM_GEN_MODE_NO_SYNC \ + } +#endif /* PWM2_CONFIG */ +#endif /* BSP_USING_PWM2 */ + +#ifdef BSP_USING_PWM3 +#ifndef PWM3_CONFIG +#define PWM3_CONFIG \ + { \ + .name = "pwm3", \ + .channel = 0 , \ + .counterMode = PWM_GEN_MODE_UP_DOWN , \ + .syncMode = PWM_GEN_MODE_NO_SYNC \ + } +#endif /* PWM3_CONFIG */ +#endif /* BSP_USING_PWM3 */ + +#ifdef BSP_USING_PWM4 +#ifndef PWM4_CONFIG +#define PWM4_CONFIG \ + { \ + .name = "pwm4", \ + .channel = 0 , \ + .counterMode = PWM_GEN_MODE_UP_DOWN , \ + .syncMode = PWM_GEN_MODE_NO_SYNC \ + } +#endif /* PWM4_CONFIG */ +#endif /* BSP_USING_PWM4 */ + +#ifdef BSP_USING_PWM5 +#ifndef PWM5_CONFIG +#define PWM5_CONFIG \ + { \ + .name = "pwm5", \ + .channel = 0 , \ + .counterMode = PWM_GEN_MODE_UP_DOWN , \ + .syncMode = PWM_GEN_MODE_NO_SYNC \ + } +#endif /* PWM5_CONFIG */ +#endif /* BSP_USING_PWM5 */ + +#ifdef BSP_USING_PWM6 +#ifndef PWM6_CONFIG +#define PWM6_CONFIG \ + { \ + .name = "pwm6", \ + .channel = 0 , \ + .counterMode = PWM_GEN_MODE_UP_DOWN , \ + .syncMode = PWM_GEN_MODE_NO_SYNC \ + } +#endif /* PWM6_CONFIG */ +#endif /* BSP_USING_PWM6 */ + +#ifdef BSP_USING_PWM7 +#ifndef PWM7_CONFIG +#define PWM7_CONFIG \ + { \ + .name = "pwm7", \ + .channel = 0 , \ + .counterMode = PWM_GEN_MODE_UP_DOWN , \ + .syncMode = PWM_GEN_MODE_NO_SYNC \ + } +#endif /* PWM7_CONFIG */ +#endif /* BSP_USING_PWM7 */ + +#ifdef __cplusplus +} +#endif + +#endif /*__PWM_CONFIG_H__*/ + +/************************** end of file ******************/ \ No newline at end of file diff --git a/bsp/tm4c123bsp/libraries/Drivers/config/spi_config.h b/bsp/tm4c123bsp/libraries/Drivers/config/spi_config.h new file mode 100644 index 0000000000000000000000000000000000000000..7da0b7852f99a0ca9eb74e7babc3e038ef43c818 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/Drivers/config/spi_config.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-27 AHTYDHD the first version + */ + +#ifndef __SPI_CONFIG_H__ +#define __SPI_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_SPI0 +#ifndef SPI0_BUS_CONFIG +#define SPI0_BUS_CONFIG \ + { \ + .base = SSI0_BASE, \ + .bus_name = "spi0", \ + } +#endif /* SPI0_BUS_CONFIG */ +#endif /* BSP_USING_SPI0 */ + +#ifdef BSP_USING_SPI1 +#ifndef SPI1_BUS_CONFIG +#define SPI1_BUS_CONFIG \ + { \ + .base = SSI1_BASE, \ + .bus_name = "spi1", \ + } +#endif /* SPI1_BUS_CONFIG */ +#endif /* BSP_USING_SPI1 */ + +#ifdef BSP_USING_SPI2 +#ifndef SPI2_BUS_CONFIG +#define SPI2_BUS_CONFIG \ + { \ + .base = SSI2_BASE, \ + .bus_name = "spi2", \ + } +#endif /* SPI2_BUS_CONFIG */ +#endif /* BSP_USING_SPI2 */ + +#ifdef BSP_USING_SPI3 +#ifndef SPI3_BUS_CONFIG +#define SPI3_BUS_CONFIG \ + { \ + .base = SSI3_BASE, \ + .bus_name = "spi3", \ + } +#endif /* SPI3_BUS_CONFIG */ +#endif /* BSP_USING_SPI3 */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SPI_CONFIG_H__ */ + +/************************** end of file ******************/ \ No newline at end of file diff --git a/bsp/tm4c123bsp/libraries/Drivers/config/uart_config.h b/bsp/tm4c123bsp/libraries/Drivers/config/uart_config.h new file mode 100644 index 0000000000000000000000000000000000000000..b8fd375d0730a8f7764504b45cba5844815dceab --- /dev/null +++ b/bsp/tm4c123bsp/libraries/Drivers/config/uart_config.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-27 AHTYDHD the first version + */ + +#ifndef __UART_CONFIG_H__ +#define __UART_CONFIG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(BSP_USING_UART0) +#ifndef UART0_CONFIG +#define UART0_CONFIG \ + { \ + .name = "uart0", \ + .uartbase = UART0_BASE, \ + .baudrate = 115200, \ + .mode = UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | \ + UART_CONFIG_PAR_NONE \ + } +#endif /* UART1_CONFIG */ +#endif /* BSP_USING_UART1*/ + +#if defined(BSP_USING_UART1) +#ifndef UART1_CONFIG +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .uartbase = UART1_BASE, \ + .baudrate = 115200, \ + .mode = UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | \ + UART_CONFIG_PAR_NONE \ + } +#endif /* UART1_CONFIG */ +#endif /* BSP_USING_UART1*/ + +#if defined(BSP_USING_UART2) +#ifndef UART2_CONFIG +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .uartbase = UART2_BASE, \ + .baudrate = 115200, \ + .mode = UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | \ + UART_CONFIG_PAR_NONE \ + } +#endif /* UART2_CONFIG */ +#endif /* BSP_USING_UART2*/ + +#if defined(BSP_USING_UART3) +#ifndef UART3_CONFIG +#define UART3_CONFIG \ + { \ + .name = "uart3", \ + .uartbase = UART3_BASE, \ + .baudrate = 115200, \ + .mode = UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | \ + UART_CONFIG_PAR_NONE \ + } +#endif /* UART3_CONFIG */ +#endif /* BSP_USING_UART3*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __UART_CONFIG_H__ */ + +/************************** end of file ******************/ \ No newline at end of file diff --git a/bsp/tm4c123bsp/libraries/Drivers/drv_adc.c b/bsp/tm4c123bsp/libraries/Drivers/drv_adc.c new file mode 100644 index 0000000000000000000000000000000000000000..daf8e7b8caa10b3e35a9da1d6c1ca4073cc278d5 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/Drivers/drv_adc.c @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-27 AHTYDHD the first version + */ + +#include "drv_adc.h" +#include +#include +#include "inc/hw_memmap.h" +#include "driverlib/adc.h" +#include "driverlib/sysctl.h" + +#ifdef RT_USING_ADC +#include "adc_config.h" +#include "tm4c123_config.h" +#include + +#define LOG_TAG "drv.adc" +#include + +static struct tm4c123_adc_config adc_config[] = +{ +#ifdef BSP_USING_ADC0 + ADC0_CONFIG, +#endif +#ifdef BSP_USING_ADC1 + ADC1_CONFIG, +#endif +}; + +struct tm4c123_adc +{ + struct tm4c123_adc_config *config; + struct rt_adc_device adc_device; +}; + +static struct tm4c123_adc adc_obj[sizeof(adc_config) / sizeof(adc_config[0])] = {0}; + +static rt_err_t tm4c123_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled) +{ + RT_ASSERT(device != RT_NULL); + struct tm4c123_adc_config *config = (struct tm4c123_adc_config *)device->parent.user_data; + + if (enabled) + { + ADCSequenceEnable(config->adcbase, config->sequence); + ADCIntClear(config->adcbase, config->sequence); + } + else + { + ADCSequenceDisable(config->adcbase, config->sequence); + } + return RT_EOK; +} + +static rt_err_t tm4c123_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value) +{ + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(value != RT_NULL); + + uint32_t pui32ADC0Value[4] = {0}; + struct tm4c123_adc_config *config = (struct tm4c123_adc_config *)device->parent.user_data; + + /* Trigger the ADC conversion. */ + ADCProcessorTrigger(config->adcbase, config->sequence); + + while (!ADCIntStatus(config->adcbase, config->sequence, false)) + { + } + + /* Clear the ADC interrupt flag. */ + ADCIntClear(config->adcbase, config->sequence); + + /* Read ADC Value. */ + ADCSequenceDataGet(config->adcbase, config->sequence, pui32ADC0Value); + + /* get ADC value */ + *value = (rt_uint32_t)pui32ADC0Value[channel]; + + return RT_EOK; +} + +static const struct rt_adc_ops tm4c123_adc_ops = +{ + .enabled = tm4c123_adc_enabled, + .convert = tm4c123_get_adc_value, +}; + + +static rt_err_t tm4c123_hw_adc_init(struct tm4c123_adc *device) +{ + + uint32_t adcbase = device->config->adcbase; + uint32_t sequencenum = device->config->sequence; + + ADCSequenceConfigure(adcbase, sequencenum, + device->config->trigermode, 0); + + ADCSequenceStepConfigure(adcbase, sequencenum, 0, ADC_CTL_CH7); + ADCSequenceStepConfigure(adcbase, sequencenum, 1, ADC_CTL_CH6 | ADC_CTL_IE); + ADCSequenceStepConfigure(adcbase, sequencenum, 2, ADC_CTL_CH5); + /*Tell the ADC logic + that this is the last conversion on sequence 3 (ADC_CTL_END). */ + ADCSequenceStepConfigure(adcbase, sequencenum, 3, ADC_CTL_CH4 | ADC_CTL_IE | + ADC_CTL_END); + return RT_EOK; +} + + +static int tm4c123_adc_init(void) +{ + int i = 0; + rt_size_t obj_num = sizeof(adc_obj) / sizeof(struct tm4c123_adc); + rt_err_t result = RT_EOK; + + adc_hw_config(); + + for (i = 0; i < obj_num; i++) + { + /* ADC init */ + adc_obj[i].config = &adc_config[i]; + + + if (tm4c123_hw_adc_init(&adc_obj[i]) != RT_EOK) + { + LOG_E("%s init failed", adc_obj[i].config->name); + result = -RT_ERROR; + return result; + } + else + { + LOG_D("%s init success", adc_obj[i].config->name); + + /* register adc device */ + if (rt_hw_adc_register(&adc_obj[i].adc_device, adc_obj[i].config->name, &tm4c123_adc_ops, &adc_config[i]) == RT_EOK) + { + LOG_D("%s register success", adc_obj[i].config->name); + } + else + { + LOG_E("%s register failed", adc_obj[i].config->name); + result = -RT_ERROR; + } + } + } + + return result; +} +INIT_APP_EXPORT(tm4c123_adc_init); + +#endif /*RT_UING_ADC*/ + +/************************** end of file ******************/ \ No newline at end of file diff --git a/bsp/tm4c123bsp/libraries/Drivers/drv_adc.h b/bsp/tm4c123bsp/libraries/Drivers/drv_adc.h new file mode 100644 index 0000000000000000000000000000000000000000..a552e5f04717675d637b10a0fa208e7e3d76177d --- /dev/null +++ b/bsp/tm4c123bsp/libraries/Drivers/drv_adc.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-27 AHTYDHD the first version + */ + +#ifndef __DRV_ADC_H__ +#define __DRV_ADC_H__ + +#include +#include +#include +#include + +struct tm4c123_adc_config +{ + const char *name; + uint32_t adcbase; + uint32_t channel; + uint32_t sequence; + uint32_t trigermode; + uint32_t sequencepriority; +}; + +#endif /*__DRV_ADC_H__*/ + +/************************** end of file ******************/ \ No newline at end of file diff --git a/bsp/tm4c123bsp/libraries/Drivers/drv_gpio.c b/bsp/tm4c123bsp/libraries/Drivers/drv_gpio.c new file mode 100644 index 0000000000000000000000000000000000000000..7cdfaf91f98897cf85accee85c5202af1efe019e --- /dev/null +++ b/bsp/tm4c123bsp/libraries/Drivers/drv_gpio.c @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-27 AHTYDHD the first version + */ + +#include "drv_gpio.h" +#include +#include +#include "drv_gpio.h" +#include +#include +#include "inc/hw_memmap.h" +#include "driverlib/sysctl.h" +#include "driverlib/gpio.h" +#include "driverlib/pin_map.h" + +#ifdef RT_USING_PIN + +static const struct pin_index pins[] = +{ + _TM4C_PIN(0, F, 0), + _TM4C_PIN(1, F, 1), + _TM4C_PIN(2, F, 2), + _TM4C_PIN(3, F, 3), + _TM4C_PIN(4, F, 4) +}; + +/* this is pin_irq map, reserved for update */ +static struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + {-1, 0, RT_NULL, RT_NULL}, +}; + +static uint32_t pin_irq_enable_mask = 0; + +#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) + +static const struct pin_index *get_pin(uint8_t pin) +{ + const struct pin_index *index; + + if (pin < ITEM_NUM(pins)) + { + index = &pins[pin]; + if (index->index == -1) + index = RT_NULL; + } + else + { + index = RT_NULL; + } + return index; +}; + +static void tm4c123_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + const struct pin_index *index; + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + if (mode == PIN_MODE_INPUT) + { + GPIOPinTypeGPIOInput(index ->gpioBaseAddress, index->pin); + } + else if (mode == PIN_MODE_OUTPUT) + { + GPIOPinTypeGPIOOutput(index->gpioBaseAddress, index->pin); + } + else if (mode == PIN_MODE_INPUT_PULLUP) + { + GPIODirModeSet(index->gpioBaseAddress, index->pin, GPIO_DIR_MODE_IN); + GPIOPadConfigSet(index->gpioBaseAddress, index->pin, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU); + } + else if (mode == PIN_MODE_INPUT_PULLDOWN) + { + GPIODirModeSet(index->gpioBaseAddress, index->pin, GPIO_DIR_MODE_IN); + GPIOPadConfigSet(index->gpioBaseAddress, index->pin, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPD); + } + else if (mode == PIN_MODE_OUTPUT_OD) + { + GPIOPadConfigSet(index->gpioBaseAddress, index->pin, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD); + GPIODirModeSet(index->gpioBaseAddress, index->pin, GPIO_DIR_MODE_OUT); + } + +} + +static void tm4c123_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t ui8Val) +{ + const struct pin_index *index; + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + if (ui8Val) + { + GPIOPinWrite(index ->gpioBaseAddress, index->pin, index->pin); + } + else + { + GPIOPinWrite(index ->gpioBaseAddress, index->pin, 0); + } +} + +static int tm4c123_pin_read(rt_device_t dev, rt_base_t pin) +{ + const struct pin_index *index; + int value = 0; + + index = get_pin(pin); + if (index == RT_NULL) + { + return value; + } + value = GPIOPinRead(index ->gpioBaseAddress, index ->pin); + + return value; +} + +static rt_err_t tm4c123_pin_attach_irq(rt_device_t device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + /* this is interface for pin_irq, reserved for update. */ + return RT_EOK; +} + +static rt_err_t tm4c123_pin_dettach_irq(rt_device_t device, rt_int32_t pin) +{ + /* this is interface for pin_irq, reserved for update. */ + return RT_EOK; +} + +static rt_err_t tm4c123_pin_irq_enable(rt_device_t device, rt_base_t pin, + rt_uint32_t enabled) +{ + /* this is interface for pin_irq_enable, reserved for update. */ + return RT_EOK; +} + + +const static struct rt_pin_ops _tm4c123_pin_ops = +{ + tm4c123_pin_mode, + tm4c123_pin_write, + tm4c123_pin_read, + tm4c123_pin_attach_irq, + tm4c123_pin_dettach_irq, + tm4c123_pin_irq_enable, +}; + +int rt_hw_pin_init(void) +{ + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF); + return rt_device_pin_register("pin", &_tm4c123_pin_ops, RT_NULL); +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +#endif /*RT_USING_PIN*/ + +/************************** end of file ******************/ \ No newline at end of file diff --git a/bsp/tm4c123bsp/libraries/Drivers/drv_gpio.h b/bsp/tm4c123bsp/libraries/Drivers/drv_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..5205367e8b0570b16b8b61f3caf434cf8c722248 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/Drivers/drv_gpio.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-27 AHTYDHD the first version + */ + +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ + +#include +#include + +#define _TM4C_PIN(index, gpioport, gpio_index) \ + { \ + index, GPIO_PORT##gpioport##_BASE, GPIO_PIN_##gpio_index \ + } + +#define _TM4C_PIN_RESERVE \ + { \ + -1, 0, 0 \ + } + +/* TM4C123 GPIO driver*/ +struct pin_index +{ + int index; + uint32_t gpioBaseAddress; + uint32_t pin; +}; + +extern int rt_hw_pin_init(void); + +#endif /*__DRV_GPIO_H__*/ + +/************************** end of file ******************/ \ No newline at end of file diff --git a/bsp/tm4c123bsp/libraries/Drivers/drv_log.h b/bsp/tm4c123bsp/libraries/Drivers/drv_log.h new file mode 100644 index 0000000000000000000000000000000000000000..ea5e64842998a22822c23e0ad06085d77b53019e --- /dev/null +++ b/bsp/tm4c123bsp/libraries/Drivers/drv_log.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-15 SummerGift first version + */ + +/* + * NOTE: DO NOT include this file on the header file. + */ + +#ifndef LOG_TAG + #define DBG_TAG "drv" +#else + #define DBG_TAG LOG_TAG +#endif /* LOG_TAG */ + +#ifdef DRV_DEBUG + #define DBG_LVL DBG_LOG +#else + #define DBG_LVL DBG_INFO +#endif /* DRV_DEBUG */ + +#include diff --git a/bsp/tm4c123bsp/libraries/Drivers/drv_pwm.c b/bsp/tm4c123bsp/libraries/Drivers/drv_pwm.c new file mode 100644 index 0000000000000000000000000000000000000000..dbd69fdb4efe389a78170742fd6c20c4d8bdc4aa --- /dev/null +++ b/bsp/tm4c123bsp/libraries/Drivers/drv_pwm.c @@ -0,0 +1,325 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-27 AHTYDHD the first version + */ + +#include "drv_pwm.h" +#include +#include +#include "inc/hw_memmap.h" +#include "driverlib/pwm.h" +#include "driverlib/sysctl.h" + +#ifdef RT_USING_PWM +#include "pwm_config.h" +#include "tm4c123_config.h" +#include + +#define LOG_TAG "drv.pwm" +#include + +enum +{ +#ifdef BSP_USING_PWM0 + PWM0_INDEX, +#endif +#ifdef BSP_USING_PWM1 + PWM1_INDEX, +#endif +#ifdef BSP_USING_PWM2 + PWM2_INDEX, +#endif +#ifdef BSP_USING_PWM3 + PWM3_INDEX, +#endif +#ifdef BSP_USING_PWM4 + PWM4_INDEX, +#endif +#ifdef BSP_USING_PWM5 + PWM5_INDEX, +#endif +#ifdef BSP_USING_PWM6 + PWM6_INDEX, +#endif +#ifdef BSP_USING_PWM7 + PWM7_INDEX, +#endif +}; + +static struct tm4c123_pwm_config pwm_config[] = +{ +#ifdef BSP_USING_PWM0 + PWM0_CONFIG, +#endif +#ifdef BSP_USING_PWM1 + PWM1_CONFIG, +#endif +#ifdef BSP_USING_PWM2 + PWM2_CONFIG, +#endif +#ifdef BSP_USING_PWM3 + PWM3_CONFIG, +#endif +#ifdef BSP_USING_PWM4 + PWM4_CONFIG, +#endif +#ifdef BSP_USING_PWM5 + PWM5_CONFIG, +#endif +#ifdef BSP_USING_PWM6 + PWM6_CONFIG, +#endif +#ifdef BSP_USING_PWM7 + PWM7_CONFIG, +#endif +}; + +static struct tm4c123_pwm pwm_obj[sizeof(pwm_config) / sizeof(pwm_config[0])] = {0}; + +static rt_err_t tm4c123_pwm_control(struct rt_device_pwm *device, int cmd, void *arg); +static struct rt_pwm_ops drv_ops = +{ + tm4c123_pwm_control +}; + +static rt_err_t drv_pwm_enable(char *name, struct rt_pwm_configuration *configuration, rt_bool_t enable) +{ + + int num = name[3] - 0x30; + + if (!enable) + { + if (num <= 3) + { + /* Converts the channel number to the channel number of Hal library */ + PWMOutputState(PWM0_BASE, PWM_OUT_0_BIT << (num * 2 + (configuration->channel - 1)), false); + } + else + { + PWMOutputState(PWM1_BASE, PWM_OUT_0_BIT << ((num % 4) * 2 + (configuration->channel - 1)), false); + } + } + else + { + if (num <= 3) + { + PWMOutputState(PWM0_BASE, PWM_OUT_0_BIT << (num * 2 + (configuration->channel - 1)), true); + } + else + { + PWMOutputState(PWM1_BASE, PWM_OUT_0_BIT << ((num % 4) * 2 + (configuration->channel - 1)), true); + } + } + + return RT_EOK; +} + +static rt_err_t drv_pwm_get(char *name, struct rt_pwm_configuration *configuration) +{ + + switch (name[3]) + { + case '0': + configuration->period = PWMGenPeriodGet(PWM0_BASE, PWM_GEN_0); + configuration->pulse = PWMPulseWidthGet(PWM0_BASE, PWM_OUT_0 + (uint32_t)(configuration->channel - 1)); + break; + case '1': + configuration->period = PWMGenPeriodGet(PWM0_BASE, PWM_GEN_1); + configuration->pulse = PWMPulseWidthGet(PWM0_BASE, PWM_OUT_2 + (uint32_t)(configuration->channel - 1)); + break; + case '2': + configuration->period = PWMGenPeriodGet(PWM0_BASE, PWM_GEN_2); + configuration->pulse = PWMPulseWidthGet(PWM0_BASE, PWM_OUT_4 + (uint32_t)(configuration->channel - 1)); + break; + case '3': + configuration->period = PWMGenPeriodGet(PWM0_BASE, PWM_GEN_3); + configuration->pulse = PWMPulseWidthGet(PWM0_BASE, PWM_OUT_6 + (uint32_t)(configuration->channel - 1)); + break; + case '4': + configuration->period = PWMGenPeriodGet(PWM1_BASE, PWM_GEN_0); + configuration->pulse = PWMPulseWidthGet(PWM1_BASE, PWM_OUT_0 + (uint32_t)(configuration->channel - 1)); + break; + case '5': + configuration->period = PWMGenPeriodGet(PWM1_BASE, PWM_GEN_1); + configuration->pulse = PWMPulseWidthGet(PWM1_BASE, PWM_OUT_2 + (uint32_t)(configuration->channel - 1)); + break; + case '6': + configuration->period = PWMGenPeriodGet(PWM1_BASE, PWM_GEN_2); + configuration->pulse = PWMPulseWidthGet(PWM1_BASE, PWM_OUT_4 + (uint32_t)(configuration->channel - 1)); + break; + case '7': + configuration->period = PWMGenPeriodGet(PWM1_BASE, PWM_GEN_3); + configuration->pulse = PWMPulseWidthGet(PWM1_BASE, PWM_OUT_6 + (uint32_t)(configuration->channel - 1)); + break; + default: + break; + } + return RT_EOK; +} + +static rt_err_t drv_pwm_set(char *name, struct rt_pwm_configuration *configuration) +{ + + uint32_t sysPwmClock = SysCtlPWMClockGet(); + switch (name[3]) + { + case '0': + PWMGenPeriodSet(PWM0_BASE, PWM_GEN_0, configuration->period / 1000 * (sysPwmClock / 1000000)); // t(s)/(1/f) = ticks ns/1000/1000000 + PWMPulseWidthSet(PWM0_BASE, PWM_OUT_0 + (uint32_t)(configuration->channel - 1), configuration->pulse / 1000 * (sysPwmClock / 1000000)); + PWMGenEnable(PWM0_BASE, PWM_GEN_0); + break; + case '1': + PWMGenPeriodSet(PWM0_BASE, PWM_GEN_1, configuration->period / 1000 * (sysPwmClock / 1000000)); + PWMPulseWidthSet(PWM0_BASE, PWM_OUT_0 + (uint32_t)(configuration->channel - 1), configuration->pulse / 1000 * (sysPwmClock / 1000000)); + PWMGenEnable(PWM0_BASE, PWM_GEN_1); + break; + case '2': + PWMGenPeriodSet(PWM0_BASE, PWM_GEN_2, configuration->period / 1000 * (sysPwmClock / 1000000)); + PWMPulseWidthSet(PWM0_BASE, PWM_OUT_0 + (uint32_t)(configuration->channel - 1), configuration->pulse / 1000 * (sysPwmClock / 1000000)); + PWMGenEnable(PWM0_BASE, PWM_GEN_2); + break; + case '3': + PWMGenPeriodSet(PWM0_BASE, PWM_GEN_3, configuration->period / 1000 * (sysPwmClock / 1000000)); + PWMPulseWidthSet(PWM0_BASE, PWM_OUT_0 + (uint32_t)(configuration->channel - 1), configuration->pulse / 1000 * (sysPwmClock / 1000000)); + PWMGenEnable(PWM0_BASE, PWM_GEN_3); + break; + case '4': + PWMGenPeriodSet(PWM1_BASE, PWM_GEN_0, configuration->period / 1000 * (sysPwmClock / 1000000)); + PWMPulseWidthSet(PWM1_BASE, PWM_OUT_0 + (uint32_t)(configuration->channel - 1), configuration->pulse / 1000 * (sysPwmClock / 1000000)); + PWMGenEnable(PWM1_BASE, PWM_GEN_0); + break; + case '5': + PWMGenPeriodSet(PWM1_BASE, PWM_GEN_1, configuration->period / 1000 * (sysPwmClock / 1000000)); + PWMPulseWidthSet(PWM1_BASE, PWM_OUT_2 + (uint32_t)(configuration->channel - 1), configuration->pulse / 1000 * (sysPwmClock / 1000000)); + PWMGenEnable(PWM1_BASE, PWM_GEN_1); + break; + case '6': + PWMGenPeriodSet(PWM1_BASE, PWM_GEN_2, configuration->period / 1000 * (sysPwmClock / 1000000)); + PWMPulseWidthSet(PWM1_BASE, PWM_OUT_4 + (uint32_t)(configuration->channel - 1), configuration->pulse / 1000 * (sysPwmClock / 1000000)); + PWMGenEnable(PWM1_BASE, PWM_GEN_2); + break; + case '7': + PWMGenPeriodSet(PWM1_BASE, PWM_GEN_3, configuration->period / 1000 * (sysPwmClock / 1000000)); + PWMPulseWidthSet(PWM1_BASE, PWM_OUT_6 + (uint32_t)(configuration->channel - 1), configuration->pulse / 1000 * (sysPwmClock / 1000000)); + PWMGenEnable(PWM1_BASE, PWM_GEN_3); + break; + default: + break; + } + + return RT_EOK; +} + +static rt_err_t tm4c123_pwm_control(struct rt_device_pwm *device, int cmd, void *arg) + +{ + struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg; + + switch (cmd) + { + case PWM_CMD_ENABLE: + return drv_pwm_enable(device->parent.parent.name, configuration, RT_TRUE); + case PWM_CMD_DISABLE: + return drv_pwm_enable(device->parent.parent.name, configuration, RT_FALSE); + case PWM_CMD_SET: + return drv_pwm_set(device->parent.parent.name, configuration); + case PWM_CMD_GET: + return drv_pwm_get(device->parent.parent.name, configuration); + default: + return RT_EINVAL; + } +} + +static rt_err_t tm4c123_hw_pwm_init(struct tm4c123_pwm *device) +{ + rt_err_t result = RT_EOK; + RT_ASSERT(device != RT_NULL); + + pwm_hw_config(); + switch (device->config->name[3]) + { + case '0': + PWMGenConfigure(PWM0_BASE, PWM_GEN_0, device->config->counterMode | + device->config->syncMode); + break; + case '1': + PWMGenConfigure(PWM0_BASE, PWM_GEN_1, device->config->counterMode | + device->config->syncMode); + break; + case '2': + PWMGenConfigure(PWM0_BASE, PWM_GEN_2, device->config->counterMode | + device->config->syncMode); + break; + case '3': + PWMGenConfigure(PWM0_BASE, PWM_GEN_3, device->config->counterMode | + device->config->syncMode); + break; + case '4': + PWMGenConfigure(PWM1_BASE, PWM_GEN_0, device->config->counterMode | + device->config->syncMode); + break; + case '5': + PWMGenConfigure(PWM1_BASE, PWM_GEN_1, device->config->counterMode | + device->config->syncMode); + break; + case '6': + PWMGenConfigure(PWM1_BASE, PWM_GEN_2, device->config->counterMode | + device->config->syncMode); + break; + case '7': + PWMGenConfigure(PWM1_BASE, PWM_GEN_3, device->config->counterMode | + device->config->syncMode); + break; + default: + LOG_E("%s PWMGenConfigure failed", device->config->name); + result = -RT_ERROR; + return result; + } + + return result; +} + +int rt_hw_pwm_init(void) +{ + int i = 0; + rt_size_t obj_num = sizeof(pwm_obj) / sizeof(struct tm4c123_pwm); + rt_err_t result = RT_EOK; + + for (i = 0 ; i < obj_num; i++) + { + pwm_obj[i].config = &pwm_config[i]; + pwm_obj[i].pwm_device.ops = &drv_ops; + /*pwm_init*/ + if (tm4c123_hw_pwm_init(&pwm_obj[i]) != RT_EOK) + { + LOG_E("%s init failed", pwm_obj[i].config->name); + result = -RT_ERROR; + return result; + } + else + { + LOG_D("%s init success", pwm_obj[i].config->name); + + /* register pwm device */ + if (rt_device_pwm_register(&pwm_obj[i].pwm_device, pwm_obj[i].config->name, &drv_ops, RT_NULL) == RT_EOK) + { + LOG_D("%s register success", pwm_obj[i].config->name); + } + else + { + LOG_E("%s register failed", pwm_obj[i].config->name); + result = -RT_ERROR; + } + } + } + return result; +} + +#endif /* RT_USING_PWM */ + +/************************** end of file ******************/ \ No newline at end of file diff --git a/bsp/tm4c123bsp/libraries/Drivers/drv_pwm.h b/bsp/tm4c123bsp/libraries/Drivers/drv_pwm.h new file mode 100644 index 0000000000000000000000000000000000000000..29ce1899bd9cc4a66de6eb2d1e88bbd8a535b7bb --- /dev/null +++ b/bsp/tm4c123bsp/libraries/Drivers/drv_pwm.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-27 AHTYDHD the first version + */ + +#ifndef __DRV_PWM_H__ +#define __DRV_PWM_H__ + +#include +#include + +struct tm4c123_pwm +{ + struct tm4c123_pwm_config *config; + struct rt_device_pwm pwm_device; +}; + +/* tm4c123 config class */ +struct tm4c123_pwm_config +{ + rt_uint8_t channel; + char *name; + uint32_t counterMode; + uint32_t syncMode; +}; + +int rt_hw_pwm_init(void); + +#endif /*__DRV_PWM_H__*/ + +/************************** end of file ******************/ \ No newline at end of file diff --git a/bsp/tm4c123bsp/libraries/Drivers/drv_spi.c b/bsp/tm4c123bsp/libraries/Drivers/drv_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..d604c2199398fcfb7ecdfee459a23f861fbf1a0c --- /dev/null +++ b/bsp/tm4c123bsp/libraries/Drivers/drv_spi.c @@ -0,0 +1,309 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-27 AHTYDHD the first version + */ + +#include "drv_spi.h" +#include +#include +#include "inc/hw_memmap.h" +#include "driverlib/ssi.h" +#include "driverlib/gpio.h" +#include "driverlib/sysctl.h" + +#ifdef RT_USING_SPI + +#if defined(BSP_USING_SPI0) || defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3) +/* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */ +#include "tm4c123_config.h" +#include "spi_config.h" +#include + +//#define DRV_DEBUG +#define LOG_TAG "drv.spi" +#include + +enum +{ +#ifdef BSP_USING_SPI0 + SPI0_INDEX, +#endif +#ifdef BSP_USING_SPI1 + SPI1_INDEX, +#endif +#ifdef BSP_USING_SPI2 + SPI2_INDEX, +#endif +#ifdef BSP_USING_SPI3 + SPI3_INDEX, +#endif +}; + +static struct tm4c123_spi_config spi_config[] = +{ +#ifdef BSP_USING_SPI0 + SPI0_BUS_CONFIG, +#endif + +#ifdef BSP_USING_SPI1 + SPI1_BUS_CONFIG, +#endif + +#ifdef BSP_USING_SPI2 + SPI2_BUS_CONFIG, +#endif + +#ifdef BSP_USING_SPI3 + SPI3_BUS_CONFIG, +#endif + +}; + +static struct tm4c123_spi spi_bus_obj[sizeof(spi_config) / sizeof(spi_config[0])] = {0}; + +static rt_err_t tm4c123_spi_configure(struct tm4c123_spi *spi_drv, struct rt_spi_configuration *cfg) +{ + RT_ASSERT(spi_drv != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + uint32_t ui32Protocol, ui32Mode; + uint32_t ui32BitRate = (uint32_t)cfg->max_hz; + uint32_t ui32DataWidth = (uint32_t)cfg->data_width; + uint32_t pui32DataRx[1]; + rt_uint8_t ui8Protocol = 0; + + if (cfg->mode & RT_SPI_SLAVE) + { + ui32Mode = SSI_MODE_SLAVE; + } + else + { + ui32Mode = SSI_MODE_MASTER; + } + + if (cfg->mode & RT_SPI_CPHA) + { + ui8Protocol += 1; + } + else + { + ui8Protocol += 0; + } + + if (cfg->mode & RT_SPI_CPOL) + { + ui8Protocol += 2; + } + else + { + ui8Protocol += 0; + } + + switch (ui8Protocol) + { + case 0: + ui32Protocol = SSI_FRF_MOTO_MODE_0; + break; + case 1: + ui32Protocol = SSI_FRF_MOTO_MODE_1; + break; + case 2: + ui32Protocol = SSI_FRF_MOTO_MODE_2; + break; + case 3: + ui32Protocol = SSI_FRF_MOTO_MODE_3; + break; + default: + ui32Protocol = SSI_FRF_MOTO_MODE_0; + break; + } + + SSIConfigSetExpClk(spi_drv->config->base, SysCtlClockGet(), ui32Protocol, + ui32Mode, ui32BitRate, ui32DataWidth); + + LOG_D("ssiclk freq: %d, SPI limiting freq: %d", SysCtlClockGet(), cfg->max_hz); + + SSIEnable(spi_drv->config->base); + + while (SSIDataGetNonBlocking(SSI0_BASE, &pui32DataRx[0])) + { + } + + LOG_D("%s init done", spi_drv->config->bus_name); + + return RT_EOK; +} + +static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ + + rt_size_t message_length; + rt_uint8_t *recv_buf; + const rt_uint8_t *send_buf; + uint32_t ReadData = 0; + int i = 0; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(device->bus != RT_NULL); + RT_ASSERT(device->bus->parent.user_data != RT_NULL); + RT_ASSERT(message != RT_NULL); + + struct tm4c123_spi *spi_drv = rt_container_of(device->bus, struct tm4c123_spi, spi_bus); + struct tm4c123_hw_spi_cs *cs = device->parent.user_data; + + if (message->cs_take) + { + GPIOPinWrite(cs->portbase, cs->GPIO_Pin, 0); + } + + LOG_D("%s transfer prepare and start", spi_drv->config->bus_name); + LOG_D("%s sendbuf: %X, recvbuf: %X, length: %d", + spi_drv->config->bus_name, + (uint32_t)message->send_buf, + (uint32_t)message->recv_buf, message->length); + + message_length = message->length; + recv_buf = message->recv_buf; + send_buf = message->send_buf; + + if (message->send_buf && message->recv_buf) + { + for (i = 0; i < message_length; i++) + { + SSIDataPut(spi_drv->config->base, (uint32_t)send_buf[i]); + while (SSIBusy(spi_drv->config->base)) + { + } + SSIDataGet(spi_drv->config->base, &ReadData); + recv_buf[i] = (unsigned char)ReadData; + } + + } + else if (message->send_buf) + { + for (i = 0; i < message_length; i++) + { + SSIDataPut(spi_drv->config->base, (uint32_t)send_buf[i]); + while (SSIBusy(spi_drv->config->base)) + { + } + SSIDataGet(spi_drv->config->base, &ReadData); + } + } + else + { + for (i = 0; i < message_length; i++) + { + SSIDataPut(spi_drv->config->base, (uint32_t)0xff); + while (SSIBusy(spi_drv->config->base)) + { + } + SSIDataGet(spi_drv->config->base, &ReadData); + recv_buf[i] = (unsigned char)ReadData; + } + } + + LOG_D("%s transfer done", spi_drv->config->bus_name); + + if (message->cs_release) + { + GPIOPinWrite(cs->portbase, cs->GPIO_Pin, cs->GPIO_Pin); + } + + return message->length; +} + + +static rt_err_t spi_configure(struct rt_spi_device *device, + struct rt_spi_configuration *configuration) +{ + RT_ASSERT(device != RT_NULL); + RT_ASSERT(configuration != RT_NULL); + + struct tm4c123_spi *spi_drv = rt_container_of(device->bus, struct tm4c123_spi, spi_bus); + spi_drv->cfg = configuration; + + return tm4c123_spi_configure(spi_drv, configuration); +} + +static const struct rt_spi_ops tm4c123_spi_ops = +{ + .configure = spi_configure, + .xfer = spixfer, +}; + + +static int rt_hw_spi_bus_init(void) +{ + rt_err_t result; + for (int i = 0; i < sizeof(spi_config) / sizeof(spi_config[0]); i++) + { + spi_bus_obj[i].config = &spi_config[i]; + spi_bus_obj[i].spi_bus.parent.user_data = &spi_config[i]; + + + result = rt_spi_bus_register(&spi_bus_obj[i].spi_bus, spi_config[i].bus_name, &tm4c123_spi_ops); + RT_ASSERT(result == RT_EOK); + + LOG_D("%s bus init done", spi_config[i].bus_name); + } + + return result; +} + +/** + * Attach the spi device to SPI bus, this function must be used after initialization. + */ +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, uint32_t portindex, uint32_t cs_gpiobase, uint32_t cs_gpio_pin) +{ + RT_ASSERT(bus_name != RT_NULL); + RT_ASSERT(device_name != RT_NULL); + + rt_err_t result; + struct rt_spi_device *spi_device; + struct tm4c123_hw_spi_cs *cs_pin; + + /* initialize the cs pin && select the slave*/ + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA + portindex); + GPIOPinTypeGPIOOutput(cs_gpiobase, cs_gpio_pin); + GPIOPinWrite(cs_gpiobase, cs_gpio_pin, cs_gpio_pin); + + /* attach the device to spi bus*/ + spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); + RT_ASSERT(spi_device != RT_NULL); + cs_pin = (struct tm4c123_hw_spi_cs *)rt_malloc(sizeof(struct tm4c123_hw_spi_cs)); + RT_ASSERT(cs_pin != RT_NULL); + cs_pin->portbase = cs_gpiobase; + cs_pin->GPIO_Pin = cs_gpio_pin; + result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); + + if (result != RT_EOK) + { + LOG_E("%s attach to %s faild, %d\n", device_name, bus_name, result); + } + + RT_ASSERT(result == RT_EOK); + + LOG_D("%s attach to %s done", device_name, bus_name); + + return result; +} + + +int rt_hw_spi_init(void) +{ + spi_hw_config(); + + return rt_hw_spi_bus_init(); +} +INIT_BOARD_EXPORT(rt_hw_spi_init); + +#endif /* defined(BSP_USING_SPI0) || defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3) */ +#endif /*RT_USING_SPI*/ + +/************************** end of file ******************/ \ No newline at end of file diff --git a/bsp/tm4c123bsp/libraries/Drivers/drv_spi.h b/bsp/tm4c123bsp/libraries/Drivers/drv_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..bc4e5a4e240eed51f266982c232345b0ff45e490 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/Drivers/drv_spi.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-27 AHTYDHD the first version + */ + +#ifndef __DRV_SPI_H__ +#define __DRV_SPI_H__ + +#include +#include +#include "drivers/spi.h" + +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, uint32_t portindex, uint32_t cs_gpiobase, uint32_t cs_gpio_pin); + +struct tm4c123_hw_spi_cs +{ + uint32_t portbase; + uint32_t GPIO_Pin; +}; + +struct tm4c123_spi_config +{ + uint32_t base; + char *bus_name; +}; + +/* tm4c123 spi dirver class */ +struct tm4c123_spi +{ + struct tm4c123_spi_config *config; + struct rt_spi_configuration *cfg; + struct rt_spi_bus spi_bus; +}; + +struct tm4c123_spi_device +{ + rt_uint32_t pin; + char *bus_name; + char *device_name; +}; + +#endif /*__DRV_SPI_H__ */ + +/************************** end of file ******************/ \ No newline at end of file diff --git a/bsp/tm4c123bsp/libraries/Drivers/drv_uart.c b/bsp/tm4c123bsp/libraries/Drivers/drv_uart.c new file mode 100644 index 0000000000000000000000000000000000000000..9679baf2936c472cb770b77fe07b99f8b17a994d --- /dev/null +++ b/bsp/tm4c123bsp/libraries/Drivers/drv_uart.c @@ -0,0 +1,238 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-27 AHTYDHD the first version + */ + +#include "drv_uart.h" +#include +#include +#include "inc/hw_memmap.h" +#include "inc/hw_ints.h" +#include "driverlib/sysctl.h" +#include "driverlib/gpio.h" +#include "driverlib/pin_map.h" +#include "driverlib/interrupt.h" +#include "driverlib/uart.h" + +#ifdef RT_USING_SERIAL +#include "uart_config.h" +#include "tm4c123_config.h" + +#define LOG_TAG "drv.uart" +#include + +#if !defined(BSP_USING_UART0)&&!defined(BSP_USING_UART1)&&!defined(BSP_USING_UART2)&&!defined(BSP_USING_UART3) + #error "Please define at least one BSP_USING_UARTx" +#endif + +enum +{ +#ifdef BSP_USING_UART0 + UART0_INDEX, +#endif +#ifdef BSP_USING_UART1 + UART1_INDEX, +#endif +#ifdef BSP_USING_UART2 + UART2_INDEX, +#endif +#ifdef BSP_USING_UART3 + UART3_INDEX, +#endif +}; + +uint32_t uart_intbase[] = +{ +#ifdef BSP_USING_UART0 + INT_UART0, +#endif +#ifdef BSP_USING_UART1 + INT_UART1, +#endif +#ifdef BSP_USING_UART2 + INT_UART2, +#endif +#ifdef BSP_USING_UART3 + INT_UART3 +#endif +}; + +static struct tm4c123_uart_config uart_config[] = +{ +#ifdef BSP_USING_UART0 + UART0_CONFIG, +#endif + +#ifdef BSP_USING_UART1 + UART1_CONFIG, +#endif + +#ifdef BSP_USING_UART2 + UART2_CONFIG, +#endif + +#ifdef BSP_USING_UART3 + UART3_CONFIG, +#endif +}; +static struct tm4c123_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0}; + +static rt_err_t tm4c123_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct tm4c123_uart *uart; + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + uart = rt_container_of(serial, struct tm4c123_uart, serial); + + UARTFIFOLevelSet(uart->config->uartbase, UART_FIFO_TX1_8, UART_FIFO_RX1_8); + UARTConfigSetExpClk(uart->config->uartbase, SysCtlClockGet(), uart->config->baudrate, + uart->config->mode); + return RT_EOK; +} + + +static rt_err_t tm4c123_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct tm4c123_uart *uart; + RT_ASSERT(serial != RT_NULL); + uart = rt_container_of(serial, struct tm4c123_uart, serial); + + switch (cmd) + { + /* disable interrupt */ + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + IntDisable(uart->uartintbase); + UARTIntDisable(uart->config->uartbase, UART_INT_RX); + break; + /* enable interrupt */ + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + IntEnable(uart->uartintbase); + UARTIntEnable(uart->config->uartbase, UART_INT_RX); + break; + } + return RT_EOK; +} + +static int tm4c123_putc(struct rt_serial_device *serial, char c) +{ + struct tm4c123_uart *uart; + RT_ASSERT(serial != RT_NULL); + + uart = rt_container_of(serial, struct tm4c123_uart, serial); + UARTCharPut(uart->config->uartbase, c); + return 1; +} + +static int tm4c123_getc(struct rt_serial_device *serial) +{ + int ch; + struct tm4c123_uart *uart; + RT_ASSERT(serial != RT_NULL); + + uart = rt_container_of(serial, struct tm4c123_uart, serial); + ch = -1; + ch = UARTCharGetNonBlocking(uart->config->uartbase); + return ch; +} + +static rt_size_t tm4c123_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction) +{ + /* this is an interface for uart dma, reserved for uptate. */ + return 0; +} + +static const struct rt_uart_ops tm4c123_uart_ops = +{ + .configure = tm4c123_configure, + .control = tm4c123_control, + .putc = tm4c123_putc, + .getc = tm4c123_getc, + .dma_transmit = tm4c123_dma_transmit +}; + +/** + * Uart common interrupt process. This need add to uart ISR. + * + * @param serial serial device + */ +static void uart_isr(struct rt_serial_device *serial) +{ + struct tm4c123_uart *uart; + uint32_t ui32Ints; + RT_ASSERT(serial != RT_NULL); + uart = rt_container_of(serial, struct tm4c123_uart, serial); + + ui32Ints = UARTIntStatus(uart->config->uartbase, true); + UARTIntClear(uart->config->uartbase, ui32Ints); + + /* UART in mode Receiver -------------------------------------------------*/ + if (ui32Ints & (UART_INT_RX | UART_INT_RT)) + { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + } +} + +#if defined(BSP_USING_UART0) +void UART0IntHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART0_INDEX].serial)); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART0 */ + +#if defined(BSP_USING_UART1) +void UART1IntHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART1_INDEX].serial)); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART1 */ + +static void tm4c123_uart_get_dma_config(void) +{ + /* this is an interface for uart dma, reserved for update */ +} + +int rt_hw_usart_init(void) +{ + rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct tm4c123_uart); + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + rt_err_t result = 0; + + uart_hw_config(); + for (int i = 0; i < obj_num; i++) + { + uart_obj[i].config = &uart_config[i]; + uart_obj[i].uartintbase = uart_intbase[i]; + uart_obj[i].serial.ops = &tm4c123_uart_ops; + uart_obj[i].serial.config = config; + /* register UART device */ + result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name, + RT_DEVICE_FLAG_RDWR + | RT_DEVICE_FLAG_INT_RX + | RT_DEVICE_FLAG_INT_TX + | uart_obj[i].uart_dma_flag + , NULL); + RT_ASSERT(result == RT_EOK); + } + return result; +} + +#endif /* RT_USING_SERIAL */ + +/************************** end of file ******************/ \ No newline at end of file diff --git a/bsp/tm4c123bsp/libraries/Drivers/drv_uart.h b/bsp/tm4c123bsp/libraries/Drivers/drv_uart.h new file mode 100644 index 0000000000000000000000000000000000000000..44f8615008b2ca969fc17138bda7a42ee2a4d6d8 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/Drivers/drv_uart.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-27 AHTYDHD the first version + */ + +#ifndef __DRV_UART_H__ +#define __DRV_UART_H__ + +#include +#include +#include +#include "rtdevice.h" + +/* tm4c123 config class */ +struct tm4c123_uart_config +{ + const char *name; + uint32_t uartbase; + uint32_t baudrate; + uint32_t mode; + +}; + +/* tm4c123 uart dirver class */ +struct tm4c123_uart +{ + struct tm4c123_uart_config *config; + uint32_t uartintbase; + +#ifdef RT_SERIAL_USING_DMA +#endif + + rt_uint16_t uart_dma_flag; + struct rt_serial_device serial; +}; + +extern int rt_hw_usart_init(void); + +#endif /*__DRV_UART_H__*/ + +/************************** end of file ******************/ \ No newline at end of file diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/SConscript b/bsp/tm4c123bsp/libraries/TivaWare_C_series/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..9178aeaa352baa75f59a5d0c0106245bb1308cd2 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/SConscript @@ -0,0 +1,73 @@ +import rtconfig +Import('RTT_ROOT') +from building import * + +# get current directory +cwd = GetCurrentDir() + +# The set of source files associated with this SConscript file. +src = Split(""" +tm4c123_driverlib/src/sysctl.c +tm4c123_driverlib/src/systick.c +tm4c123_driverlib/src/interrupt.c +tm4c123_driverlib/src/fpu.c +tm4c123_driverlib/src/cpu.c +tm4c123_driverlib/src/gpio.c +""") + +#if GetDepend(['RT_USING_PIN']): + +if GetDepend(['RT_USING_SERIAL']): + src += ['tm4c123_driverlib/src/uart.c'] + +#if GetDepend(['RT_USING_I2C']): + + +if GetDepend(['RT_USING_SPI']): + src += ['tm4c123_driverlib/src/ssi.c'] + +#if GetDepend(['RT_USING_USB_HOST']) or GetDepend(['RT_USING_USB_DEVICE']): + + +#if GetDepend(['RT_USING_CAN']): + + +#if GetDepend(['RT_USING_HWTIMER']) + +if GetDepend(['RT_USING_PWM']) or GetDepend(['RT_USING_PULSE_ENCODER']): + src += ['tm4c123_driverlib/src/pwm.c'] + +#if GetDepend(['BSP_USING_ETH']): + + +if GetDepend(['RT_USING_ADC']): + src += ['tm4c123_driverlib/src/adc.c'] + +#if GetDepend(['RT_USING_RTC']): + + +#if GetDepend(['RT_USING_WDT']): + + +#if GetDepend(['RT_USING_SDIO']): + + +#if GetDepend(['RT_USING_AUDIO']): + + +#if GetDepend(['RT_USING_MTD_NOR']): + + +#if GetDepend(['RT_USING_MTD_NAND']): + + +#if GetDepend(['BSP_USING_ON_CHIP_FLASH']): + + +path = [cwd + '/tm4c123_driverlib', + cwd + '/tm4c123_driverlib/driverlib', + cwd + '/tm4c123_driverlib/driverlib/inc'] + +group = DefineGroup('TM4C123_HAL', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/adc.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/adc.h new file mode 100644 index 0000000000000000000000000000000000000000..993b6a3fb5798570edde64667e78aa9a69f67479 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/adc.h @@ -0,0 +1,327 @@ +//***************************************************************************** +// +// adc.h - ADC headers for using the ADC driver functions. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_ADC_H__ +#define __DRIVERLIB_ADC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to ADCSequenceConfigure as the ui32Trigger +// parameter. +// +//***************************************************************************** +#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event +#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event +#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event +#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event +#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event +#define ADC_TRIGGER_TIMER 0x00000005 // Timer event +#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event +#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event +#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event +#define ADC_TRIGGER_PWM3 0x00000009 // PWM3 event +#define ADC_TRIGGER_NEVER 0x0000000E // Never Trigger +#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event +#define ADC_TRIGGER_PWM_MOD0 0x00000000 // PWM triggers from PWM0 +#define ADC_TRIGGER_PWM_MOD1 0x00000010 // PWM triggers from PWM1 + +//***************************************************************************** +// +// Values that can be passed to ADCSequenceStepConfigure as the ui32Config +// parameter. +// +//***************************************************************************** +#define ADC_CTL_TS 0x00000080 // Temperature sensor select +#define ADC_CTL_IE 0x00000040 // Interrupt enable +#define ADC_CTL_END 0x00000020 // Sequence end select +#define ADC_CTL_D 0x00000010 // Differential select +#define ADC_CTL_CH0 0x00000000 // Input channel 0 +#define ADC_CTL_CH1 0x00000001 // Input channel 1 +#define ADC_CTL_CH2 0x00000002 // Input channel 2 +#define ADC_CTL_CH3 0x00000003 // Input channel 3 +#define ADC_CTL_CH4 0x00000004 // Input channel 4 +#define ADC_CTL_CH5 0x00000005 // Input channel 5 +#define ADC_CTL_CH6 0x00000006 // Input channel 6 +#define ADC_CTL_CH7 0x00000007 // Input channel 7 +#define ADC_CTL_CH8 0x00000008 // Input channel 8 +#define ADC_CTL_CH9 0x00000009 // Input channel 9 +#define ADC_CTL_CH10 0x0000000A // Input channel 10 +#define ADC_CTL_CH11 0x0000000B // Input channel 11 +#define ADC_CTL_CH12 0x0000000C // Input channel 12 +#define ADC_CTL_CH13 0x0000000D // Input channel 13 +#define ADC_CTL_CH14 0x0000000E // Input channel 14 +#define ADC_CTL_CH15 0x0000000F // Input channel 15 +#define ADC_CTL_CH16 0x00000100 // Input channel 16 +#define ADC_CTL_CH17 0x00000101 // Input channel 17 +#define ADC_CTL_CH18 0x00000102 // Input channel 18 +#define ADC_CTL_CH19 0x00000103 // Input channel 19 +#define ADC_CTL_CH20 0x00000104 // Input channel 20 +#define ADC_CTL_CH21 0x00000105 // Input channel 21 +#define ADC_CTL_CH22 0x00000106 // Input channel 22 +#define ADC_CTL_CH23 0x00000107 // Input channel 23 +#define ADC_CTL_CMP0 0x00080000 // Select Comparator 0 +#define ADC_CTL_CMP1 0x00090000 // Select Comparator 1 +#define ADC_CTL_CMP2 0x000A0000 // Select Comparator 2 +#define ADC_CTL_CMP3 0x000B0000 // Select Comparator 3 +#define ADC_CTL_CMP4 0x000C0000 // Select Comparator 4 +#define ADC_CTL_CMP5 0x000D0000 // Select Comparator 5 +#define ADC_CTL_CMP6 0x000E0000 // Select Comparator 6 +#define ADC_CTL_CMP7 0x000F0000 // Select Comparator 7 +#define ADC_CTL_SHOLD_4 0x00000000 // Sample and hold 4 ADC clocks +#define ADC_CTL_SHOLD_8 0x00200000 // Sample and hold 8 ADC clocks +#define ADC_CTL_SHOLD_16 0x00400000 // Sample and hold 16 ADC clocks +#define ADC_CTL_SHOLD_32 0x00600000 // Sample and hold 32 ADC clocks +#define ADC_CTL_SHOLD_64 0x00800000 // Sample and hold 64 ADC clocks +#define ADC_CTL_SHOLD_128 0x00A00000 // Sample and hold 128 ADC clocks +#define ADC_CTL_SHOLD_256 0x00C00000 // Sample and hold 256 ADC clocks + +//***************************************************************************** +// +// Values that can be passed to ADCComparatorConfigure as part of the +// ui32Config parameter. +// +//***************************************************************************** +#define ADC_COMP_TRIG_NONE 0x00000000 // Trigger Disabled +#define ADC_COMP_TRIG_LOW_ALWAYS \ + 0x00001000 // Trigger Low Always +#define ADC_COMP_TRIG_LOW_ONCE 0x00001100 // Trigger Low Once +#define ADC_COMP_TRIG_LOW_HALWAYS \ + 0x00001200 // Trigger Low Always (Hysteresis) +#define ADC_COMP_TRIG_LOW_HONCE 0x00001300 // Trigger Low Once (Hysteresis) +#define ADC_COMP_TRIG_MID_ALWAYS \ + 0x00001400 // Trigger Mid Always +#define ADC_COMP_TRIG_MID_ONCE 0x00001500 // Trigger Mid Once +#define ADC_COMP_TRIG_HIGH_ALWAYS \ + 0x00001C00 // Trigger High Always +#define ADC_COMP_TRIG_HIGH_ONCE 0x00001D00 // Trigger High Once +#define ADC_COMP_TRIG_HIGH_HALWAYS \ + 0x00001E00 // Trigger High Always (Hysteresis) +#define ADC_COMP_TRIG_HIGH_HONCE \ + 0x00001F00 // Trigger High Once (Hysteresis) + +#define ADC_COMP_INT_NONE 0x00000000 // Interrupt Disabled +#define ADC_COMP_INT_LOW_ALWAYS \ + 0x00000010 // Interrupt Low Always +#define ADC_COMP_INT_LOW_ONCE 0x00000011 // Interrupt Low Once +#define ADC_COMP_INT_LOW_HALWAYS \ + 0x00000012 // Interrupt Low Always + // (Hysteresis) +#define ADC_COMP_INT_LOW_HONCE 0x00000013 // Interrupt Low Once (Hysteresis) +#define ADC_COMP_INT_MID_ALWAYS \ + 0x00000014 // Interrupt Mid Always +#define ADC_COMP_INT_MID_ONCE 0x00000015 // Interrupt Mid Once +#define ADC_COMP_INT_HIGH_ALWAYS \ + 0x0000001C // Interrupt High Always +#define ADC_COMP_INT_HIGH_ONCE 0x0000001D // Interrupt High Once +#define ADC_COMP_INT_HIGH_HALWAYS \ + 0x0000001E // Interrupt High Always + // (Hysteresis) +#define ADC_COMP_INT_HIGH_HONCE \ + 0x0000001F // Interrupt High Once (Hysteresis) + +//***************************************************************************** +// +// Values that can be used to modify the sequence number passed to +// ADCProcessorTrigger in order to get cross-module synchronous processor +// triggers. +// +//***************************************************************************** +#define ADC_TRIGGER_WAIT 0x08000000 // Wait for the synchronous trigger +#define ADC_TRIGGER_SIGNAL 0x80000000 // Signal the synchronous trigger + +//***************************************************************************** +// +// Values that can be passed to ADCPhaseDelaySet as the ui32Phase parameter and +// returned from ADCPhaseDelayGet. +// +//***************************************************************************** +#define ADC_PHASE_0 0x00000000 // 0 degrees +#define ADC_PHASE_22_5 0x00000001 // 22.5 degrees +#define ADC_PHASE_45 0x00000002 // 45 degrees +#define ADC_PHASE_67_5 0x00000003 // 67.5 degrees +#define ADC_PHASE_90 0x00000004 // 90 degrees +#define ADC_PHASE_112_5 0x00000005 // 112.5 degrees +#define ADC_PHASE_135 0x00000006 // 135 degrees +#define ADC_PHASE_157_5 0x00000007 // 157.5 degrees +#define ADC_PHASE_180 0x00000008 // 180 degrees +#define ADC_PHASE_202_5 0x00000009 // 202.5 degrees +#define ADC_PHASE_225 0x0000000A // 225 degrees +#define ADC_PHASE_247_5 0x0000000B // 247.5 degrees +#define ADC_PHASE_270 0x0000000C // 270 degrees +#define ADC_PHASE_292_5 0x0000000D // 292.5 degrees +#define ADC_PHASE_315 0x0000000E // 315 degrees +#define ADC_PHASE_337_5 0x0000000F // 337.5 degrees + +//***************************************************************************** +// +// Values that can be passed to ADCReferenceSet as the ui32Ref parameter. +// +//***************************************************************************** +#define ADC_REF_INT 0x00000000 // Internal reference +#define ADC_REF_EXT_3V 0x00000001 // External 3V reference + +//***************************************************************************** +// +// Values that can be passed to ADCIntDisableEx(), ADCIntEnableEx(), +// ADCIntClearEx() and ADCIntStatusEx(). +// +//***************************************************************************** +#define ADC_INT_SS0 0x00000001 +#define ADC_INT_SS1 0x00000002 +#define ADC_INT_SS2 0x00000004 +#define ADC_INT_SS3 0x00000008 +#define ADC_INT_DMA_SS0 0x00000100 +#define ADC_INT_DMA_SS1 0x00000200 +#define ADC_INT_DMA_SS2 0x00000400 +#define ADC_INT_DMA_SS3 0x00000800 +#define ADC_INT_DCON_SS0 0x00010000 +#define ADC_INT_DCON_SS1 0x00020000 +#define ADC_INT_DCON_SS2 0x00040000 +#define ADC_INT_DCON_SS3 0x00080000 + +//***************************************************************************** +// +// Values that can be passed to ADCClockConfigSet() and ADCClockConfigGet(). +// +//***************************************************************************** +#define ADC_CLOCK_RATE_FULL 0x00000070 +#define ADC_CLOCK_RATE_HALF 0x00000050 +#define ADC_CLOCK_RATE_FOURTH 0x00000030 +#define ADC_CLOCK_RATE_EIGHTH 0x00000010 +#define ADC_CLOCK_SRC_PLL 0x00000000 +#define ADC_CLOCK_SRC_PIOSC 0x00000001 +#define ADC_CLOCK_SRC_ALTCLK 0x00000001 +#define ADC_CLOCK_SRC_MOSC 0x00000002 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void ADCIntRegister(uint32_t ui32Base, uint32_t ui32SequenceNum, + void (*pfnHandler)(void)); +extern void ADCIntUnregister(uint32_t ui32Base, uint32_t ui32SequenceNum); +extern void ADCIntDisable(uint32_t ui32Base, uint32_t ui32SequenceNum); +extern void ADCIntEnable(uint32_t ui32Base, uint32_t ui32SequenceNum); +extern uint32_t ADCIntStatus(uint32_t ui32Base, uint32_t ui32SequenceNum, + bool bMasked); +extern void ADCIntClear(uint32_t ui32Base, uint32_t ui32SequenceNum); +extern void ADCSequenceEnable(uint32_t ui32Base, uint32_t ui32SequenceNum); +extern void ADCSequenceDisable(uint32_t ui32Base, uint32_t ui32SequenceNum); +extern void ADCSequenceConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum, + uint32_t ui32Trigger, uint32_t ui32Priority); +extern void ADCSequenceStepConfigure(uint32_t ui32Base, + uint32_t ui32SequenceNum, + uint32_t ui32Step, uint32_t ui32Config); +extern int32_t ADCSequenceOverflow(uint32_t ui32Base, + uint32_t ui32SequenceNum); +extern void ADCSequenceOverflowClear(uint32_t ui32Base, + uint32_t ui32SequenceNum); +extern int32_t ADCSequenceUnderflow(uint32_t ui32Base, + uint32_t ui32SequenceNum); +extern void ADCSequenceUnderflowClear(uint32_t ui32Base, + uint32_t ui32SequenceNum); +extern int32_t ADCSequenceDataGet(uint32_t ui32Base, uint32_t ui32SequenceNum, + uint32_t *pui32Buffer); +extern void ADCProcessorTrigger(uint32_t ui32Base, uint32_t ui32SequenceNum); +extern void ADCSoftwareOversampleConfigure(uint32_t ui32Base, + uint32_t ui32SequenceNum, + uint32_t ui32Factor); +extern void ADCSoftwareOversampleStepConfigure(uint32_t ui32Base, + uint32_t ui32SequenceNum, + uint32_t ui32Step, + uint32_t ui32Config); +extern void ADCSoftwareOversampleDataGet(uint32_t ui32Base, + uint32_t ui32SequenceNum, + uint32_t *pui32Buffer, + uint32_t ui32Count); +extern void ADCHardwareOversampleConfigure(uint32_t ui32Base, + uint32_t ui32Factor); +extern void ADCClockConfigSet(uint32_t ui32Base, uint32_t ui32Config, + uint32_t ui32ClockDiv); +extern uint32_t ADCClockConfigGet(uint32_t ui32Base, uint32_t *pui32ClockDiv); + +extern void ADCComparatorConfigure(uint32_t ui32Base, uint32_t ui32Comp, + uint32_t ui32Config); +extern void ADCComparatorRegionSet(uint32_t ui32Base, uint32_t ui32Comp, + uint32_t ui32LowRef, uint32_t ui32HighRef); +extern void ADCComparatorReset(uint32_t ui32Base, uint32_t ui32Comp, + bool bTrigger, bool bInterrupt); +extern void ADCComparatorIntDisable(uint32_t ui32Base, + uint32_t ui32SequenceNum); +extern void ADCComparatorIntEnable(uint32_t ui32Base, + uint32_t ui32SequenceNum); +extern uint32_t ADCComparatorIntStatus(uint32_t ui32Base); +extern void ADCComparatorIntClear(uint32_t ui32Base, uint32_t ui32Status); +extern void ADCIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void ADCIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags); +extern uint32_t ADCIntStatusEx(uint32_t ui32Base, bool bMasked); +extern void ADCIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void ADCSequenceDMAEnable(uint32_t ui32Base, uint32_t ui32SequenceNum); +extern void ADCSequenceDMADisable(uint32_t ui32Base, uint32_t ui32SequenceNum); +extern bool ADCBusy(uint32_t ui32Base); +extern void ADCReferenceSet(uint32_t ui32Base, uint32_t ui32Ref); +extern uint32_t ADCReferenceGet(uint32_t ui32Base); +extern void ADCPhaseDelaySet(uint32_t ui32Base, uint32_t ui32Phase); +extern uint32_t ADCPhaseDelayGet(uint32_t ui32Base); +extern void ADCSampleRateSet(uint32_t ui32Base, uint32_t ui32ADCClock, + uint32_t ui32Rate); +extern uint32_t ADCSampleRateGet(uint32_t ui32Base); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_ADC_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/aes.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/aes.h new file mode 100644 index 0000000000000000000000000000000000000000..6cf44780ddccafbdc1bd63f4e75ab6e8b322f2a7 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/aes.h @@ -0,0 +1,218 @@ +//***************************************************************************** +// +// aes.h - Defines and Macros for the AES module. +// +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_AES_H__ +#define __DRIVERLIB_AES_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following defines are used to specify the operation direction in the +// ui32Config argument in the AESConfig function. Only one is permitted. +// +//***************************************************************************** +#define AES_CFG_DIR_ENCRYPT 0x00000004 +#define AES_CFG_DIR_DECRYPT 0x00000000 + +//***************************************************************************** +// +// The following defines are used to specify the key size in the ui32Config +// argument in the AESConfig function. Only one is permitted. +// +//***************************************************************************** +#define AES_CFG_KEY_SIZE_128BIT 0x00000008 +#define AES_CFG_KEY_SIZE_192BIT 0x00000010 +#define AES_CFG_KEY_SIZE_256BIT 0x00000018 + +//***************************************************************************** +// +// The following defines are used to specify the mode of operation in the +// ui32Config argument in the AESConfig function. Only one is permitted. +// +//***************************************************************************** +#define AES_CFG_MODE_M 0x2007fe60 +#define AES_CFG_MODE_ECB 0x00000000 +#define AES_CFG_MODE_CBC 0x00000020 +#define AES_CFG_MODE_CTR 0x00000040 +#define AES_CFG_MODE_ICM 0x00000200 +#define AES_CFG_MODE_CFB 0x00000400 +#define AES_CFG_MODE_XTS_TWEAKJL \ + 0x00000800 +#define AES_CFG_MODE_XTS_K2IJL \ + 0x00001000 +#define AES_CFG_MODE_XTS_K2ILJ0 \ + 0x00001800 +#define AES_CFG_MODE_F8 0x00002000 +#define AES_CFG_MODE_F9 0x20004000 +#define AES_CFG_MODE_CBCMAC 0x20008000 +#define AES_CFG_MODE_GCM_HLY0ZERO \ + 0x20010000 +#define AES_CFG_MODE_GCM_HLY0CALC \ + 0x20020040 +#define AES_CFG_MODE_GCM_HY0CALC \ + 0x20030040 +#define AES_CFG_MODE_CCM 0x20040040 + +//***************************************************************************** +// +// The following defines are used to specify the counter width in the +// ui32Config argument in the AESConfig function. It is only required to +// be defined when using CTR, CCM, or GCM modes. Only one length is permitted. +// +//***************************************************************************** +#define AES_CFG_CTR_WIDTH_32 0x00000000 +#define AES_CFG_CTR_WIDTH_64 0x00000080 +#define AES_CFG_CTR_WIDTH_96 0x00000100 +#define AES_CFG_CTR_WIDTH_128 0x00000180 + +//***************************************************************************** +// +// The following defines are used to define the width of the length field for +// CCM operation through the ui32Config argument in the AESConfig function. +// This value is also known as L. Only one is permitted. +// +//***************************************************************************** +#define AES_CFG_CCM_L_1 0x00000000 +#define AES_CFG_CCM_L_2 0x00080000 +#define AES_CFG_CCM_L_3 0x00100000 +#define AES_CFG_CCM_L_4 0x00180000 +#define AES_CFG_CCM_L_5 0x00200000 +#define AES_CFG_CCM_L_6 0x00280000 +#define AES_CFG_CCM_L_7 0x00300000 +#define AES_CFG_CCM_L_8 0x00380000 + +//***************************************************************************** +// +// The following defines are used to define the length of the authentication +// field for CCM operations through the ui32Config argument in the AESConfig +// function. This value is also known as M. Only one is permitted. +// +//***************************************************************************** +#define AES_CFG_CCM_M_4 0x00400000 +#define AES_CFG_CCM_M_6 0x00800000 +#define AES_CFG_CCM_M_8 0x00c00000 +#define AES_CFG_CCM_M_10 0x01000000 +#define AES_CFG_CCM_M_12 0x01400000 +#define AES_CFG_CCM_M_14 0x01800000 +#define AES_CFG_CCM_M_16 0x01c00000 + +//***************************************************************************** +// +// Interrupt flags for use with the AESIntEnable, AESIntDisable, and +// AESIntStatus functions. +// +//***************************************************************************** +#define AES_INT_CONTEXT_IN 0x00000001 +#define AES_INT_CONTEXT_OUT 0x00000008 +#define AES_INT_DATA_IN 0x00000002 +#define AES_INT_DATA_OUT 0x00000004 +#define AES_INT_DMA_CONTEXT_IN 0x00010000 +#define AES_INT_DMA_CONTEXT_OUT 0x00080000 +#define AES_INT_DMA_DATA_IN 0x00020000 +#define AES_INT_DMA_DATA_OUT 0x00040000 + +//***************************************************************************** +// +// Defines used when enabling and disabling DMA requests in the +// AESEnableDMA and AESDisableDMA functions. +// +//***************************************************************************** +#define AES_DMA_DATA_IN 0x00000020 +#define AES_DMA_DATA_OUT 0x00000040 +#define AES_DMA_CONTEXT_IN 0x00000080 +#define AES_DMA_CONTEXT_OUT 0x00000100 + +//***************************************************************************** +// +// Function prototypes. +// +//***************************************************************************** +extern void AESAuthLengthSet(uint32_t ui32Base, uint32_t ui32Length); +extern void AESConfigSet(uint32_t ui32Base, uint32_t ui32Config); +extern void AESDataRead(uint32_t ui32Base, uint32_t *pui32Dest); +extern bool AESDataReadNonBlocking(uint32_t ui32Base, uint32_t *pui32Dest); +extern bool AESDataProcess(uint32_t ui32Base, uint32_t *pui32Src, + uint32_t *pui32Dest, uint32_t ui32Length); +extern bool AESDataAuth(uint32_t ui32Base, uint32_t *pui32Src, + uint32_t ui32Length, uint32_t *pui32Tag); +extern bool AESDataProcessAuth(uint32_t ui32Base, uint32_t *pui32Src, + uint32_t *pui32Dest, uint32_t ui32Length, + uint32_t *pui32AuthSrc, + uint32_t ui32AuthLength, uint32_t *pui32Tag); +extern void AESDataWrite(uint32_t ui32Base, uint32_t *pui32Src); +extern bool AESDataWriteNonBlocking(uint32_t ui32Base, uint32_t *pui32Src); +extern void AESDMADisable(uint32_t ui32Base, uint32_t ui32Flags); +extern void AESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags); +extern void AESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void AESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void AESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void AESIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); +extern uint32_t AESIntStatus(uint32_t ui32Base, bool bMasked); +extern void AESIntUnregister(uint32_t ui32Base); +extern void AESIVSet(uint32_t ui32Base, uint32_t *pui32IVdata); +extern void AESIVRead(uint32_t ui32Base, uint32_t *pui32IVdata); +extern void AESKey1Set(uint32_t ui32Base, uint32_t *pui32Key, + uint32_t ui32Keysize); +extern void AESKey2Set(uint32_t ui32Base, uint32_t *pui32Key, + uint32_t ui32Keysize); +extern void AESKey3Set(uint32_t ui32Base, uint32_t *pui32Key); +extern void AESLengthSet(uint32_t ui32Base, uint64_t ui64Length); +extern void AESReset(uint32_t ui32Base); +extern void AESTagRead(uint32_t ui32Base, uint32_t *pui32TagData); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_AES_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/can.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/can.h new file mode 100644 index 0000000000000000000000000000000000000000..199721906b02823c2111652952dc1eda006b3099 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/can.h @@ -0,0 +1,449 @@ +//***************************************************************************** +// +// can.h - Defines and Macros for the CAN controller. +// +// Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_CAN_H__ +#define __DRIVERLIB_CAN_H__ + +//***************************************************************************** +// +//! \addtogroup can_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Miscellaneous defines for Message ID Types +// +//***************************************************************************** + +//***************************************************************************** +// +// These are the flags used by the tCANMsgObject.ui32Flags value when calling +// the CANMessageSet() and CANMessageGet() functions. +// +//***************************************************************************** + +// +//! This indicates that transmit interrupts are enabled. +// +#define MSG_OBJ_TX_INT_ENABLE 0x00000001 + +// +//! This indicates that receive interrupts are enabled. +// +#define MSG_OBJ_RX_INT_ENABLE 0x00000002 + +// +//! This indicates that a message object is using an extended identifier. +// +#define MSG_OBJ_EXTENDED_ID 0x00000004 + +// +//! This indicates that a message object is using filtering based on the +//! object's message identifier. +// +#define MSG_OBJ_USE_ID_FILTER 0x00000008 + +// +//! This indicates that new data was available in the message object. +// +#define MSG_OBJ_NEW_DATA 0x00000080 + +// +//! This indicates that data was lost since this message object was last +//! read. +// +#define MSG_OBJ_DATA_LOST 0x00000100 + +// +//! This indicates that a message object uses or is using filtering +//! based on the direction of the transfer. If the direction filtering is +//! used, then ID filtering must also be enabled. +// +#define MSG_OBJ_USE_DIR_FILTER (0x00000010 | MSG_OBJ_USE_ID_FILTER) + +// +//! This indicates that a message object uses or is using message +//! identifier filtering based on the extended identifier. If the extended +//! identifier filtering is used, then ID filtering must also be enabled. +// +#define MSG_OBJ_USE_EXT_FILTER (0x00000020 | MSG_OBJ_USE_ID_FILTER) + +// +//! This indicates that a message object is a remote frame. +// +#define MSG_OBJ_REMOTE_FRAME 0x00000040 + +// +//! This indicates that this message object is part of a FIFO structure and +//! not the final message object in a FIFO. +// +#define MSG_OBJ_FIFO 0x00000200 + +// +//! This indicates that a message object has no flags set. +// +#define MSG_OBJ_NO_FLAGS 0x00000000 + +//***************************************************************************** +// +//! This define is used with the flag values to allow checking only status +//! flags and not configuration flags. +// +//***************************************************************************** +#define MSG_OBJ_STATUS_MASK (MSG_OBJ_NEW_DATA | MSG_OBJ_DATA_LOST) + +//***************************************************************************** +// +//! The structure used for encapsulating all the items associated with a CAN +//! message object in the CAN controller. +// +//***************************************************************************** +typedef struct +{ + // + //! The CAN message identifier used for 11 or 29 bit identifiers. + // + uint32_t ui32MsgID; + + // + //! The message identifier mask used when identifier filtering is enabled. + // + uint32_t ui32MsgIDMask; + + // + //! This value holds various status flags and settings specified by + //! tCANObjFlags. + // + uint32_t ui32Flags; + + // + //! This value is the number of bytes of data in the message object. + // + uint32_t ui32MsgLen; + + // + //! This is a pointer to the message object's data. + // + uint8_t *pui8MsgData; +} +tCANMsgObject; + +//***************************************************************************** +// +//! This structure is used for encapsulating the values associated with setting +//! up the bit timing for a CAN controller. The structure is used when calling +//! the CANGetBitTiming and CANSetBitTiming functions. +// +//***************************************************************************** +typedef struct +{ + // + //! This value holds the sum of the Synchronization, Propagation, and Phase + //! Buffer 1 segments, measured in time quanta. The valid values for this + //! setting range from 2 to 16. + // + uint32_t ui32SyncPropPhase1Seg; + + // + //! This value holds the Phase Buffer 2 segment in time quanta. The valid + //! values for this setting range from 1 to 8. + // + uint32_t ui32Phase2Seg; + + // + //! This value holds the Resynchronization Jump Width in time quanta. The + //! valid values for this setting range from 1 to 4. + // + uint32_t ui32SJW; + + // + //! This value holds the CAN_CLK divider used to determine time quanta. + //! The valid values for this setting range from 1 to 1023. + // + uint32_t ui32QuantumPrescaler; +} +tCANBitClkParms; + +//***************************************************************************** +// +//! This data type is used to identify the interrupt status register. This is +//! used when calling the CANIntStatus() function. +// +//***************************************************************************** +typedef enum +{ + // + //! Read the CAN interrupt status information. + // + CAN_INT_STS_CAUSE, + + // + //! Read a message object's interrupt status. + // + CAN_INT_STS_OBJECT +} +tCANIntStsReg; + +//***************************************************************************** +// +//! This data type is used to identify which of several status registers to +//! read when calling the CANStatusGet() function. +// +//***************************************************************************** +typedef enum +{ + // + //! Read the full CAN controller status. + // + CAN_STS_CONTROL, + + // + //! Read the full 32-bit mask of message objects with a transmit request + //! set. + // + CAN_STS_TXREQUEST, + + // + //! Read the full 32-bit mask of message objects with new data available. + // + CAN_STS_NEWDAT, + + // + //! Read the full 32-bit mask of message objects that are enabled. + // + CAN_STS_MSGVAL +} +tCANStsReg; + +//***************************************************************************** +// +// These definitions are used to specify interrupt sources to CANIntEnable() +// and CANIntDisable(). +// +//***************************************************************************** +// +//! This flag is used to allow a CAN controller to generate error +//! interrupts. +// +#define CAN_INT_ERROR 0x00000008 + +// +//! This flag is used to allow a CAN controller to generate status +//! interrupts. +// +#define CAN_INT_STATUS 0x00000004 + +// +//! This flag is used to allow a CAN controller to generate any CAN +//! interrupts. If this is not set, then no interrupts are generated +//! by the CAN controller. +// +#define CAN_INT_MASTER 0x00000002 + +//***************************************************************************** +// +//! This definition is used to determine the type of message object that is +//! set up via a call to the CANMessageSet() API. +// +//***************************************************************************** +typedef enum +{ + // + //! Transmit message object. + // + MSG_OBJ_TYPE_TX, + + // + //! Transmit remote request message object + // + MSG_OBJ_TYPE_TX_REMOTE, + + // + //! Receive message object. + // + MSG_OBJ_TYPE_RX, + + // + //! Receive remote request message object. + // + MSG_OBJ_TYPE_RX_REMOTE, + + // + //! Remote frame receive remote, with auto-transmit message object. + // + MSG_OBJ_TYPE_RXTX_REMOTE +} +tMsgObjType; + +//***************************************************************************** +// +// The following enumeration contains all error or status indicators that can +// be returned when calling the CANStatusGet() function. +// +//***************************************************************************** +// +//! CAN controller has entered a Bus Off state. +// +#define CAN_STATUS_BUS_OFF 0x00000080 + +// +//! CAN controller error level has reached warning level. +// +#define CAN_STATUS_EWARN 0x00000040 + +// +//! CAN controller error level has reached error passive level. +// +#define CAN_STATUS_EPASS 0x00000020 + +// +//! A message was received successfully since the last read of this status. +// +#define CAN_STATUS_RXOK 0x00000010 + +// +//! A message was transmitted successfully since the last read of this +//! status. +// +#define CAN_STATUS_TXOK 0x00000008 + +// +//! This is the mask for the last error code field. +// +#define CAN_STATUS_LEC_MSK 0x00000007 + +// +//! There was no error. +// +#define CAN_STATUS_LEC_NONE 0x00000000 + +// +//! A bit stuffing error has occurred. +// +#define CAN_STATUS_LEC_STUFF 0x00000001 + +// +//! A formatting error has occurred. +// +#define CAN_STATUS_LEC_FORM 0x00000002 + +// +//! An acknowledge error has occurred. +// +#define CAN_STATUS_LEC_ACK 0x00000003 + +// +//! The bus remained a bit level of 1 for longer than is allowed. +// +#define CAN_STATUS_LEC_BIT1 0x00000004 + +// +//! The bus remained a bit level of 0 for longer than is allowed. +// +#define CAN_STATUS_LEC_BIT0 0x00000005 + +// +//! A CRC error has occurred. +// +#define CAN_STATUS_LEC_CRC 0x00000006 + +// +//! This is the mask for the CAN Last Error Code (LEC). +// +#define CAN_STATUS_LEC_MASK 0x00000007 + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void CANBitTimingGet(uint32_t ui32Base, tCANBitClkParms *psClkParms); +extern void CANBitTimingSet(uint32_t ui32Base, tCANBitClkParms *psClkParms); +extern uint32_t CANBitRateSet(uint32_t ui32Base, uint32_t ui32SourceClock, + uint32_t ui32BitRate); +extern void CANDisable(uint32_t ui32Base); +extern void CANEnable(uint32_t ui32Base); +extern bool CANErrCntrGet(uint32_t ui32Base, uint32_t *pui32RxCount, + uint32_t *pui32TxCount); +extern void CANInit(uint32_t ui32Base); +extern void CANIntClear(uint32_t ui32Base, uint32_t ui32IntClr); +extern void CANIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void CANIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void CANIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); +extern uint32_t CANIntStatus(uint32_t ui32Base, tCANIntStsReg eIntStsReg); +extern void CANIntUnregister(uint32_t ui32Base); +extern void CANMessageClear(uint32_t ui32Base, uint32_t ui32ObjID); +extern void CANMessageGet(uint32_t ui32Base, uint32_t ui32ObjID, + tCANMsgObject *psMsgObject, bool bClrPendingInt); +extern void CANMessageSet(uint32_t ui32Base, uint32_t ui32ObjID, + tCANMsgObject *psMsgObject, tMsgObjType eMsgType); +extern bool CANRetryGet(uint32_t ui32Base); +extern void CANRetrySet(uint32_t ui32Base, bool bAutoRetry); +extern uint32_t CANStatusGet(uint32_t ui32Base, tCANStsReg eStatusReg); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_CAN_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/comp.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/comp.h new file mode 100644 index 0000000000000000000000000000000000000000..2f95df09c95c553890292737e821e50463ae0aa2 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/comp.h @@ -0,0 +1,141 @@ +//***************************************************************************** +// +// comp.h - Prototypes for the analog comparator driver. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_COMP_H__ +#define __DRIVERLIB_COMP_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to ComparatorConfigure() as the ui32Config +// parameter. For each group (in other words, COMP_TRIG_xxx, COMP_INT_xxx, and +// so on), one of the values may be selected and combined together with values +// from the other groups via a logical OR. +// +//***************************************************************************** +#define COMP_TRIG_NONE 0x00000000 // No ADC trigger +#define COMP_TRIG_HIGH 0x00000880 // Trigger when high +#define COMP_TRIG_LOW 0x00000800 // Trigger when low +#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge +#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge +#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges +#define COMP_INT_HIGH 0x00000010 // Interrupt when high +#define COMP_INT_LOW 0x00000000 // Interrupt when low +#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge +#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge +#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges +#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin +#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin +#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_OUTPUT_NORMAL 0x00000000 // Comparator output normal +#define COMP_OUTPUT_INVERT 0x00000002 // Comparator output inverted + +//***************************************************************************** +// +// Values that can be passed to ComparatorSetRef() as the ui32Ref parameter. +// +//***************************************************************************** +#define COMP_REF_OFF 0x00000000 // Turn off the internal reference +#define COMP_REF_0V 0x00000300 // Internal reference of 0V +#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V +#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V +#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V +#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V +#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V +#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V +#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V +#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V +#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V +#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V +#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V +#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V +#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V +#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V +#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V +#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V +#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V +#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V +#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V +#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V +#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V +#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V +#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V +#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V +#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V +#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V +#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void ComparatorConfigure(uint32_t ui32Base, uint32_t ui32Comp, + uint32_t ui32Config); +extern void ComparatorRefSet(uint32_t ui32Base, uint32_t ui32Ref); +extern bool ComparatorValueGet(uint32_t ui32Base, uint32_t ui32Comp); +extern void ComparatorIntRegister(uint32_t ui32Base, uint32_t ui32Comp, + void (*pfnHandler)(void)); +extern void ComparatorIntUnregister(uint32_t ui32Base, uint32_t ui32Comp); +extern void ComparatorIntEnable(uint32_t ui32Base, uint32_t ui32Comp); +extern void ComparatorIntDisable(uint32_t ui32Base, uint32_t ui32Comp); +extern bool ComparatorIntStatus(uint32_t ui32Base, uint32_t ui32Comp, + bool bMasked); +extern void ComparatorIntClear(uint32_t ui32Base, uint32_t ui32Comp); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_COMP_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/cpu.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/cpu.h new file mode 100644 index 0000000000000000000000000000000000000000..11a07e88d030918eb71449214275f1598a7c19db --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/cpu.h @@ -0,0 +1,75 @@ +//***************************************************************************** +// +// cpu.h - Prototypes for the CPU instruction wrapper functions. +// +// Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_CPU_H__ +#define __DRIVERLIB_CPU_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes. +// +//***************************************************************************** +extern uint32_t CPUcpsid(void); +extern uint32_t CPUcpsie(void); +extern uint32_t CPUprimask(void); +extern void CPUwfi(void); +extern uint32_t CPUbasepriGet(void); +extern void CPUbasepriSet(uint32_t ui32NewBasepri); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_CPU_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/crc.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/crc.h new file mode 100644 index 0000000000000000000000000000000000000000..7d33e84cb627ac88c55c8e5f22938346d19200fb --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/crc.h @@ -0,0 +1,101 @@ +//***************************************************************************** +// +// crc.h - Defines and Macros for CRC module. +// +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_CRC_H__ +#define __DRIVERLIB_CRC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following defines are used in the ui32Config argument of the +// ECConfig function. +// +//***************************************************************************** +#define CRC_CFG_INIT_SEED 0x00000000 // Initialize with seed +#define CRC_CFG_INIT_0 0x00004000 // Initialize to all '0s' +#define CRC_CFG_INIT_1 0x00006000 // Initialize to all '1s' +#define CRC_CFG_SIZE_8BIT 0x00001000 // Input Data Size +#define CRC_CFG_SIZE_32BIT 0x00000000 // Input Data Size +#define CRC_CFG_RESINV 0x00000200 // Result Inverse Enable +#define CRC_CFG_OBR 0x00000100 // Output Reverse Enable +#define CRC_CFG_IBR 0x00000080 // Bit reverse enable +#define CRC_CFG_ENDIAN_SBHW 0x00000020 // Swap byte in half-word +#define CRC_CFG_ENDIAN_SHW 0x00000010 // Swap half-word +#define CRC_CFG_TYPE_P8005 0x00000000 // Polynomial 0x8005 +#define CRC_CFG_TYPE_P1021 0x00000001 // Polynomial 0x1021 +#define CRC_CFG_TYPE_P4C11DB7 0x00000002 // Polynomial 0x4C11DB7 +#define CRC_CFG_TYPE_P1EDC6F41 0x00000003 // Polynomial 0x1EDC6F41 +#define CRC_CFG_TYPE_TCPCHKSUM 0x00000008 // TCP checksum + +//***************************************************************************** +// +// Function prototypes. +// +//***************************************************************************** +#if 0 +extern void ECClockGatingReqest(uint32_t ui32Base, uint32_t ui32ECIP, + bool bGate); +#endif +extern void CRCConfigSet(uint32_t ui32Base, uint32_t ui32CRCConfig); +extern uint32_t CRCDataProcess(uint32_t ui32Base, uint32_t *pui32DataIn, + uint32_t ui32DataLength, bool bPPResult); +extern void CRCDataWrite(uint32_t ui32Base, uint32_t ui32Data); +extern uint32_t CRCResultRead(uint32_t ui32Base, bool bPPResult); +extern void CRCSeedSet(uint32_t ui32Base, uint32_t ui32Seed); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_CRC_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/debug.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/debug.h new file mode 100644 index 0000000000000000000000000000000000000000..fd2e3afba11f1edc743bfda0ef78afa4dff31a4a --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/debug.h @@ -0,0 +1,70 @@ +//***************************************************************************** +// +// debug.h - Macros for assisting debug of the driver library. +// +// Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_DEBUG_H__ +#define __DRIVERLIB_DEBUG_H__ + +//***************************************************************************** +// +// Prototype for the function that is called when an invalid argument is passed +// to an API. This is only used when doing a DEBUG build. +// +//***************************************************************************** +extern void __error__(char *pcFilename, uint32_t ui32Line); + +//***************************************************************************** +// +// The ASSERT macro, which does the actual assertion checking. Typically, this +// will be for procedure arguments. +// +//***************************************************************************** +#ifdef DEBUG +#define ASSERT(expr) do \ + { \ + if(!(expr)) \ + { \ + __error__(__FILE__, __LINE__); \ + } \ + } \ + while(0) +#else +#define ASSERT(expr) +#endif + +#endif // __DRIVERLIB_DEBUG_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/des.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/des.h new file mode 100644 index 0000000000000000000000000000000000000000..9f6c8d1853959681827a5f30bcedbc3b93e3c28a --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/des.h @@ -0,0 +1,140 @@ +//***************************************************************************** +// +// des.h - Defines and Macros for the DES module. +// +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_DES_H__ +#define __DRIVERLIB_DES_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following defines are used to specify the direction with the +// ui32Config argument in the DESConfig() function. Only one is permitted. +// +//***************************************************************************** +#define DES_CFG_DIR_DECRYPT 0x00000000 +#define DES_CFG_DIR_ENCRYPT 0x00000004 + +//***************************************************************************** +// +// The following defines are used to specify the operational with the +// ui32Config argument in the DESConfig() function. Only one is permitted. +// +//***************************************************************************** +#define DES_CFG_MODE_ECB 0x00000000 +#define DES_CFG_MODE_CBC 0x00000010 +#define DES_CFG_MODE_CFB 0x00000020 + +//***************************************************************************** +// +// The following defines are used to select between single DES and triple DES +// with the ui32Config argument in the DESConfig() function. Only one is +// permitted. +// +//***************************************************************************** +#define DES_CFG_SINGLE 0x00000000 +#define DES_CFG_TRIPLE 0x00000008 + +//***************************************************************************** +// +// The following defines are used with the DESIntEnable(), DESIntDisable() and +// DESIntStatus() functions. +// +//***************************************************************************** +#define DES_INT_CONTEXT_IN 0x00000001 +#define DES_INT_DATA_IN 0x00000002 +#define DES_INT_DATA_OUT 0x00000004 +#define DES_INT_DMA_CONTEXT_IN 0x00010000 +#define DES_INT_DMA_DATA_IN 0x00020000 +#define DES_INT_DMA_DATA_OUT 0x00040000 + +//***************************************************************************** +// +// The following defines are used with the DESEnableDMA() and DESDisableDMA() +// functions. +// +//***************************************************************************** +#define DES_DMA_CONTEXT_IN 0x00000080 +#define DES_DMA_DATA_OUT 0x00000040 +#define DES_DMA_DATA_IN 0x00000020 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void DESConfigSet(uint32_t ui32Base, uint32_t ui32Config); +extern void DESDataRead(uint32_t ui32Base, uint32_t *pui32Dest); +extern bool DESDataReadNonBlocking(uint32_t ui32Base, uint32_t *pui32Dest); +extern bool DESDataProcess(uint32_t ui32Base, uint32_t *pui32Src, + uint32_t *pui32Dest, uint32_t ui32Length); +extern void DESDataWrite(uint32_t ui32Base, uint32_t *pui32Src); +extern bool DESDataWriteNonBlocking(uint32_t ui32Base, uint32_t *pui32Src); +extern void DESDMADisable(uint32_t ui32Base, uint32_t ui32Flags); +extern void DESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags); +extern void DESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void DESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void DESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void DESIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); +extern uint32_t DESIntStatus(uint32_t ui32Base, bool bMasked); +extern void DESIntUnregister(uint32_t ui32Base); +extern bool DESIVSet(uint32_t ui32Base, uint32_t *pui32IVdata); +extern void DESKeySet(uint32_t ui32Base, uint32_t *pui32Key); +extern void DESLengthSet(uint32_t ui32Base, uint32_t ui32Length); +extern void DESReset(uint32_t ui32Base); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_DES_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/eeprom.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/eeprom.h new file mode 100644 index 0000000000000000000000000000000000000000..0336010e0694e2258c7ee6a63bdfa1173b1418fd --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/eeprom.h @@ -0,0 +1,284 @@ +//***************************************************************************** +// +// eeprom.h - Prototypes for the EEPROM driver. +// +// Copyright (c) 2010-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_EEPROM_H__ +#define __DRIVERLIB_EEPROM_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup eeprom_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Values returned by EEPROMInit. +// +//***************************************************************************** + +// +//! This value may be returned from a call to EEPROMInit(). It indicates that +//! no previous write operations were interrupted by a reset event and that the +//! EEPROM peripheral is ready for use. +// +#define EEPROM_INIT_OK 0 + +// +//! This value may be returned from a call to EEPROMInit(). It indicates that +//! a previous data or protection write operation was interrupted by a reset +//! event and that the EEPROM peripheral was unable to clean up after the +//! problem. This situation may be resolved with another reset or may be fatal +//! depending upon the cause of the problem. For example, if the voltage to +//! the part is unstable, retrying once the voltage has stabilized may clear +//! the error. +// +#define EEPROM_INIT_ERROR 2 + +//***************************************************************************** +// +// Error indicators returned by various EEPROM API calls. These will be ORed +// together into the final return code. +// +//***************************************************************************** + +// +//! This return code bit indicates that an attempt was made to read from +//! the EEPROM while a write operation was in progress. +// +#define EEPROM_RC_WRBUSY 0x00000020 + +// +//! This return code bit indicates that an attempt was made to write a +//! value but the destination permissions disallow write operations. This +//! may be due to the destination block being locked, access protection set +//! to prohibit writes or an attempt to write a password when one is already +//! written. +// +#define EEPROM_RC_NOPERM 0x00000010 + +// +//! This return code bit indicates that the EEPROM programming state machine +//! is currently copying to or from the internal copy buffer to make room for +//! a newly written value. It is provided as a status indicator and does not +//! indicate an error. +// +#define EEPROM_RC_WKCOPY 0x00000008 + +// +//! This return code bit indicates that the EEPROM programming state machine +//! is currently erasing the internal copy buffer. It is provided as a +//! status indicator and does not indicate an error. +// +#define EEPROM_RC_WKERASE 0x00000004 + +// +//! This return code bit indicates that the EEPROM programming state machine +//! is currently working. No new write operations should be attempted until +//! this bit is clear. +// +#define EEPROM_RC_WORKING 0x00000001 + +//***************************************************************************** +// +// Values that can be passed to EEPROMBlockProtectSet() in the ui32Protect +// parameter, and returned by EEPROMBlockProtectGet(). +// +//***************************************************************************** + +// +//! This bit may be ORed with the protection option passed to +//! EEPROMBlockProtectSet() or returned from EEPROMBlockProtectGet(). It +//! restricts EEPROM access to threads running in supervisor mode and prevents +//! access to an EEPROM block when the CPU is in user mode. +// +#define EEPROM_PROT_SUPERVISOR_ONLY 0x00000008 + +// +//! This value may be passed to EEPROMBlockProtectSet() or returned from +//! EEPROMBlockProtectGet(). It indicates that the block should offer +//! read/write access when no password is set or when a password is set and +//! the block is unlocked, and read-only access when a password is set but +//! the block is locked. +// +#define EEPROM_PROT_RW_LRO_URW 0x00000000 + +// +//! This value may be passed to EEPROMBlockProtectSet() or returned from +//! EEPROMBlockProtectGet(). It indicates that the block should offer neither +//! read nor write access unless it is protected by a password and unlocked. +// +#define EEPROM_PROT_NA_LNA_URW 0x00000001 + +// +//! This value may be passed to EEPROMBlockProtectSet() or returned from +//! EEPROMBlockProtectGet(). It indicates that the block should offer +//! read-only access when no password is set or when a password is set and the +//! block is unlocked. When a password is set and the block is locked, neither +//! read nor write access is permitted. +// +#define EEPROM_PROT_RO_LNA_URO 0x00000002 + +//***************************************************************************** +// +//! This value may be passed to EEPROMIntEnable() and EEPROMIntDisable() and is +//! returned by EEPROMIntStatus() if an EEPROM interrupt is currently being +//! signaled. +// +//***************************************************************************** +#define EEPROM_INT_PROGRAM 0x00000004 + +//***************************************************************************** +// +//! Returns the EEPROM block number containing a given offset address. +//! +//! \param ui32Addr is the linear, byte address of the EEPROM location whose +//! block number is to be returned. This is a zero-based offset from the start +//! of the EEPROM storage. +//! +//! This macro may be used to translate an EEPROM address offset into a +//! block number suitable for use in any of the driver's block protection +//! functions. The address provided is expressed as a byte offset from the +//! base of the EEPROM. +//! +//! \return Returns the zero-based block number which contains the passed +//! address. +// +//***************************************************************************** +#define EEPROMBlockFromAddr(ui32Addr) ((ui32Addr) >> 6) + +//***************************************************************************** +// +//! Returns the offset address of the first word in an EEPROM block. +//! +//! \param ui32Block is the index of the EEPROM block whose first word address +//! is to be returned. +//! +//! This macro may be used to determine the address of the first word in a +//! given EEPROM block. The address returned is expressed as a byte offset +//! from the base of EEPROM storage. +//! +//! \return Returns the address of the first word in the given EEPROM block. +// +//***************************************************************************** +#define EEPROMAddrFromBlock(ui32Block) ((ui32Block) << 6) + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern uint32_t EEPROMInit(void); +extern uint32_t EEPROMSizeGet(void); +extern uint32_t EEPROMBlockCountGet(void); +extern void EEPROMRead(uint32_t *pui32Data, uint32_t ui32Address, + uint32_t ui32Count); +extern uint32_t EEPROMProgram(uint32_t *pui32Data, + uint32_t ui32Address, + uint32_t ui32Count); +extern uint32_t EEPROMProgramNonBlocking(uint32_t ui32Data, + uint32_t ui32Address); +extern uint32_t EEPROMStatusGet(void); +extern uint32_t EEPROMMassErase(void); +extern uint32_t EEPROMBlockProtectGet(uint32_t ui32Block); +extern uint32_t EEPROMBlockProtectSet(uint32_t ui32Block, + uint32_t ui32Protect); +extern uint32_t EEPROMBlockPasswordSet(uint32_t ui32Block, + uint32_t *pui32Password, + uint32_t ui32Count); +extern uint32_t EEPROMBlockLock(uint32_t ui32Block); +extern uint32_t EEPROMBlockUnlock(uint32_t ui32Block, + uint32_t *pui32Password, + uint32_t ui32Count); +extern void EEPROMBlockHide(uint32_t ui32Block); +extern void EEPROMIntEnable(uint32_t ui32IntFlags); +extern void EEPROMIntDisable(uint32_t ui32IntFlags); +extern uint32_t EEPROMIntStatus(bool bMasked); +extern void EEPROMIntClear(uint32_t ui32IntFlags); + +#ifndef DEPRECATED +//***************************************************************************** +// +// The following definitions appeared in previous revisions of this file +// but have been deprecated and should not be used by applications. +// +//***************************************************************************** + +// +// This value used to be one of those which could be returned from a call to +// EEPROMInit(). It transpires that it is was incorrect and has been removed +// after EEPROMInit() was reworked for TivaWare 2.1. +// +#define EEPROM_INIT_RETRY 1 + +// +// This return code is not available from any Tiva part and has been removed. +// +#define EEPROM_RC_INVPL 0x00000100 + +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_EEPROM_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/emac.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/emac.h new file mode 100644 index 0000000000000000000000000000000000000000..f82919c8c0b971ef3abfe82119b74b8a320d7d93 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/emac.h @@ -0,0 +1,1041 @@ +//***************************************************************************** +// +// emac.h - Defines and Macros for the Ethernet module on Snowflake-class +// devices. +// +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_EMAC_H__ +#define __DRIVERLIB_EMAC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup emac_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// The physical address of the internal PHY. This should be in hw_emac.h. +// +//***************************************************************************** +#define EMAC_PHY_ADDR 0 + +//***************************************************************************** +// +// Helper Macros for Ethernet Processing +// +//***************************************************************************** +// +// htonl/ntohl - Big endian/little endian byte swapping macros for 32-bit +// values. +// +//***************************************************************************** +#ifndef htonl + #define htonl(a) \ + ((((a) >> 24) & 0x000000ff) | \ + (((a) >> 8) & 0x0000ff00) | \ + (((a) << 8) & 0x00ff0000) | \ + (((a) << 24) & 0xff000000)) +#endif + +#ifndef ntohl + #define ntohl(a) htonl((a)) +#endif + +//***************************************************************************** +// +// htons/ntohs - Big endian/little endian byte swapping macros for 16-bit +// values. +// +//***************************************************************************** +#ifndef htons + #define htons(a) \ + ((((a) >> 8) & 0x00ff) | \ + (((a) << 8) & 0xff00)) +#endif + +#ifndef ntohs + #define ntohs(a) htons((a)) +#endif + +//***************************************************************************** +// +// Forward reference to the Ethernet DMA descriptor structure. +// +//***************************************************************************** +typedef struct tEMACDMADescriptor tEMACDMADescriptor; + +//***************************************************************************** +// +//! A union used to describe the two overlapping fields forming the third +//! word of the Ethernet DMA descriptor. +// +//***************************************************************************** +typedef union +{ + // + //! When DMA descriptors are used in chained mode, this field is used to + //! provide a link to the next descriptor. + // + tEMACDMADescriptor *pLink; + + // + //! When the DMA descriptors are unchained, this field may be used to point + //! to a second buffer containing data for transmission or providing + //! storage for a received frame. + // + void *pvBuffer2; +} +tEMACDES3; + +//***************************************************************************** +// +//! A structure defining a single Ethernet DMA buffer descriptor. +// +//***************************************************************************** +struct tEMACDMADescriptor +{ + // + //! The first DMA descriptor word contains various control and status bits + //! depending upon whether the descriptor is in the transmit or receive + //! queue. Bit 31 is always the ``OWN'' bit which, when set, indicates + //! that the hardware has control of the descriptor. + // + volatile uint32_t ui32CtrlStatus; + + // + //! The second descriptor word contains information on the size of the + //! buffer or buffers attached to the descriptor and various additional + //! control bits. + // + volatile uint32_t ui32Count; + + // + //! The third descriptor word contains a pointer to the buffer containing + //! data to transmit or into which received data should be written. This + //! pointer must refer to a buffer in internal SRAM. Pointers to flash or + //! EPI-connected memory may not be used and will result in the MAC + //! reporting a bus error. + // + void *pvBuffer1; + + // + //! The fourth descriptor word contains either a pointer to the next + //! descriptor in the ring or a pointer to a second data buffer. The + //! meaning of the word is controlled by the ``CHAINED'' control bit which + //! appears in the first word of the transmit descriptor or the second + //! word of the receive descriptor. + //! + tEMACDES3 DES3; + + // + //! The fifth descriptor word is reserved for transmit descriptors but + //! used to report extended status in a receive descriptor. + // + volatile uint32_t ui32ExtRxStatus; + + // + //! The sixth descriptor word is reserved for both transmit and receive + //! descriptors. + // + uint32_t ui32Reserved; + + // + //! The seventh descriptor word contains the low 32 bits of the 64-bit + //! timestamp captured for transmitted or received data. The value is set + //! only when the transmitted or received data contains the end of a + //! packet. Availability of the timestamp is indicated via a status bit + //! in the first descriptor word. + // + volatile uint32_t ui32IEEE1588TimeLo; + + // + //! The eighth descriptor word contains the high 32 bits of the 64-bit + //! timestamp captured for transmitted or received data. + // + volatile uint32_t ui32IEEE1588TimeHi; +}; + +//***************************************************************************** +// +// Fields found in the DES0 word of the transmit descriptor (ui32CtrlStatus in +// tEMACDMADescriptor) +// +//***************************************************************************** +#define DES0_TX_CTRL_OWN 0x80000000 +#define DES0_TX_CTRL_INTERRUPT 0x40000000 +#define DES0_TX_CTRL_LAST_SEG 0x20000000 +#define DES0_TX_CTRL_FIRST_SEG 0x10000000 + +// +// This value indicates that the MAC should not append a CRC to transmitted +// packets. If used with DES0_TX_CTRL_REPLACE_CRC, the last 4 bytes of the +// packet passed to the transmitter are replaced with a newly calculated CRC. +// If DES0_TX_CTRL_REPLACE_CRC is not specified, it is assumed that packets +// transmitted have valid CRCs precomputed and included in the frame data. +// +// If DES0_TX_CTRL_DISABLE_CRC is not specified, the MAC will calculate the +// CRC for all frames transmitted and append this value as the 4-byte FCS +// after the last data byte in the frame. +// +#define DES0_TX_CTRL_DISABLE_CRC 0x08000000 +#define DES0_TX_CTRL_DISABLE_PADDING 0x04000000 +#define DES0_TX_CTRL_ENABLE_TS 0x02000000 + +// +// This value is only valid if used alongside DES0_TX_CTRL_DISABLE_CRC. When +// specified, the MAC will replace the last 4 bytes of a transmitted frame +// with a newly calculated CRC. +// +#define DES0_TX_CTRL_REPLACE_CRC 0x01000000 +#define DES0_TX_CTRL_CHKSUM_M 0x00C00000 +#define DES0_TX_CTRL_NO_CHKSUM 0x00000000 +#define DES0_TX_CTRL_IP_HDR_CHKSUM 0x00400000 +#define DES0_TX_CTRL_IP_HDR_PAY_CHKSUM 0x00800000 +#define DES0_TX_CTRL_IP_ALL_CKHSUMS 0x00C00000 +#define DES0_TX_CTRL_END_OF_RING 0x00200000 +#define DES0_TX_CTRL_CHAINED 0x00100000 +#define DES0_TX_CTRL_VLAN_M 0x000C0000 +#define DES0_TX_CTRL_VLAN_NONE 0x00000000 +#define DES0_TX_CTRL_VLAN_REMOVE 0x00040000 +#define DES0_TX_CTRL_VLAN_INSERT 0x00080000 +#define DES0_TX_CTRL_VLAN_REPLACE 0x000C0000 +#define DES0_TX_STAT_TS_CAPTURED 0x00020000 +#define DES0_TX_STAT_IPH_ERR 0x00010000 +#define DES0_TX_STAT_ERR 0x00008000 +#define DES0_TX_STAT_JABBER_TO 0x00004000 +#define DES0_TX_STAT_FLUSHED 0x00002000 +#define DES0_TX_STAT_PAYLOAD_ERR 0x00001000 +#define DES0_TX_STAT_CARRIER_LOST 0x00000800 +#define DES0_TX_STAT_NO_CARRIER 0x00000400 +#define DES0_TX_STAT_TX_L_COLLISION 0x00000200 +#define DES0_TX_STAT_E_COLLISION 0x00000100 +#define DES0_TX_STAT_VLAN_FRAME 0x00000080 +#define DES0_TX_STAT_COL_COUNT_M 0x00000078 +#define DES0_TX_STAT_COL_COUNT_S 3 +#define DES0_TX_STAT_E_DEFERRAL 0x00000004 +#define DES0_TX_STAT_UNDERFLOW 0x00000002 +#define DES0_TX_STAT_DEFERRED 0x00000001 + +//***************************************************************************** +// +// Fields found in the DES1 word of the transmit descriptor (ui32Count in +// tEMACDMADescriptor) +// +//***************************************************************************** +#define DES1_TX_CTRL_SADDR_MAC1 0x80000000 +#define DES1_TX_CTRL_SADDR_M 0x60000000 +#define DES1_TX_CTRL_SADDR_NONE 0x00000000 +#define DES1_TX_CTRL_SADDR_INSERT 0x20000000 +#define DES1_TX_CTRL_SADDR_REPLACE 0x40000000 +#define DES1_TX_CTRL_BUFF2_SIZE_M 0x1FFF0000 +#define DES1_TX_CTRL_BUFF1_SIZE_M 0x00001FFF +#define DES1_TX_CTRL_BUFF2_SIZE_S 16 +#define DES1_TX_CTRL_BUFF1_SIZE_S 0 + +//***************************************************************************** +// +// Fields found in the DES0 word of the receive descriptor (ui32CtrlStatus in +// tEMACDMADescriptor) +// +//***************************************************************************** +#define DES0_RX_CTRL_OWN 0x80000000 +#define DES0_RX_STAT_DEST_ADDR_FAIL 0x40000000 +#define DES0_RX_STAT_FRAME_LENGTH_M 0x3FFF0000 +#define DES0_RX_STAT_FRAME_LENGTH_S 16 +#define DES0_RX_STAT_ERR 0x00008000 +#define DES0_RX_STAT_DESCRIPTOR_ERR 0x00004000 +#define DES0_RX_STAT_SRC_ADDR_FAIL 0x00002000 +#define DES0_RX_STAT_LENGTH_ERR 0x00001000 +#define DES0_RX_STAT_OVERFLOW 0x00000800 +#define DES0_RX_STAT_VLAN_TAG 0x00000400 +#define DES0_RX_STAT_FIRST_DESC 0x00000200 +#define DES0_RX_STAT_LAST_DESC 0x00000100 +#define DES0_RX_STAT_TS_AVAILABLE 0x00000080 +#define DES0_RX_STAT_RX_L_COLLISION 0x00000040 +#define DES0_RX_STAT_FRAME_TYPE 0x00000020 +#define DES0_RX_STAT_WDOG_TIMEOUT 0x00000010 +#define DES0_RX_STAT_RX_ERR 0x00000008 +#define DES0_RX_STAT_DRIBBLE_ERR 0x00000004 +#define DES0_RX_STAT_CRC_ERR 0x00000002 +#define DES0_RX_STAT_MAC_ADDR 0x00000001 +#define DES0_RX_STAT_EXT_AVAILABLE 0x00000001 + +//***************************************************************************** +// +// Fields found in the DES1 word of the receive descriptor (ui32Count in +// tEMACDMADescriptor) +// +//***************************************************************************** +#define DES1_RX_CTRL_DISABLE_INT 0x80000000 +#define DES1_RX_CTRL_BUFF2_SIZE_M 0x1FFF0000 +#define DES1_RX_CTRL_BUFF2_SIZE_S 16 +#define DES1_RX_CTRL_END_OF_RING 0x00008000 +#define DES1_RX_CTRL_CHAINED 0x00004000 +#define DES1_RX_CTRL_BUFF1_SIZE_M 0x00001FFF +#define DES1_RX_CTRL_BUFF1_SIZE_S 0 + +//***************************************************************************** +// +// Fields found in the DES4 word of the receive descriptor (ui32ExtRxStatus in +// tEMACDMADescriptor) +// +//***************************************************************************** +#define DES4_RX_STAT_TS_DROPPED 0x00004000 +#define DES4_RX_STAT_PTP_VERSION2 0x00002000 +#define DES4_RX_STAT_PTP_TYPE_ETH 0x00001000 +#define DES4_RX_STAT_PTP_TYPE_UDP 0x00000000 +#define DES4_RX_STAT_PTP_MT_M 0x00000F00 +#define DES4_RX_STAT_PTP_MT_NONE 0x00000000 +#define DES4_RX_STAT_PTP_MT_SYNC 0x00000100 +#define DES4_RX_STAT_PTP_MT_FOLLOW_UP 0x00000200 +#define DES4_RX_STAT_PTP_MT_DELAY_REQ 0x00000300 +#define DES4_RX_STAT_PTP_MT_DELAY_RESP 0x00000400 +#define DES4_RX_STAT_PTP_MT_PDELAY_REQ 0x00000500 +#define DES4_RX_STAT_PTP_MT_PDELAY_RESP 0x00000600 +#define DES4_RX_STAT_PTP_MT_PDELAY_RFU 0x00000700 +#define DES4_RX_STAT_PTP_MT_ANNOUNCE 0x00000800 +#define DES4_RX_STAT_PTP_MT_SIGNALLING 0x00000A00 +#define DES4_RX_STAT_PTP_MT_RESERVED 0x00000F00 +#define DES4_RX_STAT_IPV6 0x00000080 +#define DES4_RX_STAT_IPV4 0x00000040 +#define DES4_RX_STAT_IP_CHK_BYPASSED 0x00000020 +#define DES4_RX_STAT_IP_PAYLOAD_ERR 0x00000010 +#define DES4_RX_STAT_IP_HEADER_ERR 0x00000008 +#define DES4_RX_STAT_PAYLOAD_M 0x00000007 +#define DES4_RX_STAT_PAYLOAD_UNKNOWN 0x00000000 +#define DES4_RX_STAT_PAYLOAD_UDP 0x00000001 +#define DES4_RX_STAT_PAYLOAD_TCP 0x00000002 +#define DES4_RX_STAT_PAYLOAD_ICMP 0x00000003 + +//***************************************************************************** +// +// Values used in the ui32BusConfig parameter to EMACInit(). +// +//*************************************************************************** +#define EMAC_BCONFIG_DMA_PRIO_WEIGHT_M 0x30000000 +#define EMAC_BCONFIG_DMA_PRIO_WEIGHT_1 0x00000000 +#define EMAC_BCONFIG_DMA_PRIO_WEIGHT_2 0x10000000 +#define EMAC_BCONFIG_DMA_PRIO_WEIGHT_3 0x20000000 +#define EMAC_BCONFIG_DMA_PRIO_WEIGHT_4 0x30000000 +#define EMAC_BCONFIG_TX_PRIORITY 0x08000000 +#define EMAC_BCONFIG_ADDR_ALIGNED 0x02000000 +#define EMAC_BCONFIG_PRIORITY_M 0x0000C000 +#define EMAC_BCONFIG_PRIORITY_1_1 (0 << 14) +#define EMAC_BCONFIG_PRIORITY_2_1 (1 << 14) +#define EMAC_BCONFIG_PRIORITY_3_1 (2 << 14) +#define EMAC_BCONFIG_PRIORITY_4_1 (3 << 14) +#define EMAC_BCONFIG_PRIORITY_FIXED 0x00000002 +#define EMAC_BCONFIG_FIXED_BURST 0x00010000 +#define EMAC_BCONFIG_MIXED_BURST 0x04000000 + +//***************************************************************************** +// +// Options used in the ui32Config parameter to EMACPHYConfigSet(). +// +//***************************************************************************** +#define EMAC_PHY_TYPE_INTERNAL 0x00000000 +#define EMAC_PHY_TYPE_EXTERNAL_MII 0x80000000 +#define EMAC_PHY_TYPE_EXTERNAL_RMII 0xC0000000 +#define EMAC_PHY_INT_NIB_TXERR_DET_DIS 0x01000000 +#define EMAC_PHY_INT_RX_ER_DURING_IDLE 0x00800000 +#define EMAC_PHY_INT_ISOLATE_MII_LLOSS 0x00400000 +#define EMAC_PHY_INT_LINK_LOSS_RECOVERY 0x00200000 +#define EMAC_PHY_INT_TDRRUN 0x00100000 +#define EMAC_PHY_INT_LD_ON_RX_ERR_COUNT 0x00040000 +#define EMAC_PHY_INT_LD_ON_MTL3_ERR_COUNT 0x00020000 +#define EMAC_PHY_INT_LD_ON_LOW_SNR 0x00010000 +#define EMAC_PHY_INT_LD_ON_SIGNAL_ENERGY 0x00008000 +#define EMAC_PHY_INT_POLARITY_SWAP 0x00004000 +#define EMAC_PHY_INT_MDI_SWAP 0x00002000 +#define EMAC_PHY_INT_ROBUST_MDIX 0x00001000 +#define EMAC_PHY_INT_FAST_MDIX 0x00000800 +#define EMAC_PHY_INT_MDIX_EN 0x00000400 +#define EMAC_PHY_INT_FAST_RXDV_DETECT 0x00000200 +#define EMAC_PHY_INT_FAST_L_UP_DETECT 0x00000100 +#define EMAC_PHY_INT_EXT_FULL_DUPLEX 0x00000080 +#define EMAC_PHY_INT_FAST_AN_80_50_35 0x00000040 +#define EMAC_PHY_INT_FAST_AN_120_75_50 0x00000050 +#define EMAC_PHY_INT_FAST_AN_140_150_100 0x00000060 +#define EMAC_PHY_FORCE_10B_T_HALF_DUPLEX 0x00000000 +#define EMAC_PHY_FORCE_10B_T_FULL_DUPLEX 0x00000002 +#define EMAC_PHY_FORCE_100B_T_HALF_DUPLEX 0x00000004 +#define EMAC_PHY_FORCE_100B_T_FULL_DUPLEX 0x00000006 +#define EMAC_PHY_AN_10B_T_HALF_DUPLEX 0x00000008 +#define EMAC_PHY_AN_10B_T_FULL_DUPLEX 0x0000000A +#define EMAC_PHY_AN_100B_T_HALF_DUPLEX 0x0000000C +#define EMAC_PHY_AN_100B_T_FULL_DUPLEX 0x0000000E +#define EMAC_PHY_INT_HOLD 0x00000001 + +#define EMAC_PHY_TYPE_MASK 0xC0000000 + +//***************************************************************************** +// +// Options used in the ui32Config parameter to EMACConfigSet(). +// +//***************************************************************************** +#define EMAC_CONFIG_USE_MACADDR1 0x40000000 +#define EMAC_CONFIG_USE_MACADDR0 0x00000000 +#define EMAC_CONFIG_SA_FROM_DESCRIPTOR 0x00000000 +#define EMAC_CONFIG_SA_INSERT 0x20000000 +#define EMAC_CONFIG_SA_REPLACE 0x30000000 +#define EMAC_CONFIG_2K_PACKETS 0x08000000 +#define EMAC_CONFIG_STRIP_CRC 0x02000000 +#define EMAC_CONFIG_JABBER_DISABLE 0x00400000 +#define EMAC_CONFIG_JUMBO_ENABLE 0x00100000 +#define EMAC_CONFIG_IF_GAP_MASK 0x000E0000 +#define EMAC_CONFIG_IF_GAP_96BITS (0x0 << 17) +#define EMAC_CONFIG_IF_GAP_88BITS (0x1 << 17) +#define EMAC_CONFIG_IF_GAP_80BITS (0x2 << 17) +#define EMAC_CONFIG_IF_GAP_72BITS (0x3 << 17) +#define EMAC_CONFIG_IF_GAP_64BITS (0x4 << 17) +#define EMAC_CONFIG_IF_GAP_56BITS (0x5 << 17) +#define EMAC_CONFIG_IF_GAP_48BITS (0x6 << 17) +#define EMAC_CONFIG_IF_GAP_40BITS (0x7 << 17) +#define EMAC_CONFIG_CS_DISABLE 0x00010000 +#define EMAC_CONFIG_100MBPS 0x00004000 +#define EMAC_CONFIG_10MBPS 0x00000000 +#define EMAC_CONFIG_RX_OWN_DISABLE 0x00002000 +#define EMAC_CONFIG_LOOPBACK 0x00001000 +#define EMAC_CONFIG_FULL_DUPLEX 0x00000800 +#define EMAC_CONFIG_HALF_DUPLEX 0x00000000 +#define EMAC_CONFIG_CHECKSUM_OFFLOAD 0x00000400 +#define EMAC_CONFIG_RETRY_DISABLE 0x00000200 +#define EMAC_CONFIG_AUTO_CRC_STRIPPING 0x00000080 +#define EMAC_CONFIG_BO_MASK 0x00000060 +#define EMAC_CONFIG_BO_LIMIT_1024 (0x0 << 5) +#define EMAC_CONFIG_BO_LIMIT_256 (0x1 << 5) +#define EMAC_CONFIG_BO_LIMIT_16 (0x2 << 5) +#define EMAC_CONFIG_BO_LIMIT_2 (0x3 << 5) +#define EMAC_CONFIG_DEFERRAL_CHK_ENABLE 0x00000010 +#define EMAC_CONFIG_PREAMBLE_MASK 0x00000003 +#define EMAC_CONFIG_7BYTE_PREAMBLE 0x00000000 +#define EMAC_CONFIG_5BYTE_PREAMBLE 0x00000001 +#define EMAC_CONFIG_3BYTE_PREAMBLE 0x00000002 + +//***************************************************************************** +// +// Options used in the ui32ModeFlags parameter to EMACConfigSet(). +// +//***************************************************************************** +#define EMAC_MODE_KEEP_BAD_CRC 0x04000000 +#define EMAC_MODE_RX_STORE_FORWARD 0x02000000 +#define EMAC_MODE_RX_FLUSH_DISABLE 0x01000000 +#define EMAC_MODE_TX_STORE_FORWARD 0x00200000 +#define EMAC_MODE_TX_THRESHOLD_16_BYTES (7 << 14) +#define EMAC_MODE_TX_THRESHOLD_24_BYTES (6 << 14) +#define EMAC_MODE_TX_THRESHOLD_32_BYTES (5 << 14) +#define EMAC_MODE_TX_THRESHOLD_40_BYTES (4 << 14) +#define EMAC_MODE_TX_THRESHOLD_64_BYTES (0 << 14) +#define EMAC_MODE_TX_THRESHOLD_128_BYTES (1 << 14) +#define EMAC_MODE_TX_THRESHOLD_192_BYTES (2 << 14) +#define EMAC_MODE_TX_THRESHOLD_256_BYTES (3 << 14) +#define EMAC_MODE_RX_ERROR_FRAMES 0x00000080 +#define EMAC_MODE_RX_UNDERSIZED_FRAMES 0x00000040 +#define EMAC_MODE_RX_THRESHOLD_64_BYTES (0 << 3) +#define EMAC_MODE_RX_THRESHOLD_32_BYTES (1 << 3) +#define EMAC_MODE_RX_THRESHOLD_96_BYTES (2 << 3) +#define EMAC_MODE_RX_THRESHOLD_128_BYTES (3 << 3) +#define EMAC_MODE_OPERATE_2ND_FRAME 0x00000002 + +//***************************************************************************** +// +// These two values may be returned by EMACConfigGet() in the *pui32Config +// parameter. The transmitter and receiver are, however, enabled and disabled +// using independent functions, EMACTxEnable/Disable() and +// EMACRxEnable/Disable(). +// +//***************************************************************************** +#define EMAC_CONFIG_TX_ENABLED 0x00000008 +#define EMAC_CONFIG_RX_ENABLED 0x00000004 + +//***************************************************************************** +// +// These two values may be returned by EMACConfigGet() in the *pui32Mode +// parameter. The transmit and receive DMA channels are, however, enabled and +// disabled using independent functions, EMACTxEnable/Disable() and +// EMACRxEnable/Disable(). +// +//***************************************************************************** +#define EMAC_MODE_TX_DMA_ENABLED 0x00002000 +#define EMAC_MODE_RX_DMA_ENABLED 0x00000002 + +//***************************************************************************** +// +// These values may be passed to EMACFrameFilterSet() in the ui32FilterOpts +// parameter, and are returned by EMACFrameFilterGet(). +// +//***************************************************************************** +#define EMAC_FRMFILTER_RX_ALL 0x80000000 +#define EMAC_FRMFILTER_VLAN 0x00010000 +#define EMAC_FRMFILTER_HASH_AND_PERFECT 0x00000400 +#define EMAC_FRMFILTER_SADDR 0x00000200 +#define EMAC_FRMFILTER_INV_SADDR 0x00000100 +#define EMAC_FRMFILTER_PASS_MASK (0x03 << 6) +#define EMAC_FRMFILTER_PASS_NO_CTRL (0x00 << 6) +#define EMAC_FRMFILTER_PASS_NO_PAUSE (0x01 << 6) +#define EMAC_FRMFILTER_PASS_ALL_CTRL (0x02 << 6) +#define EMAC_FRMFILTER_PASS_ADDR_CTRL (0x03 << 6) +#define EMAC_FRMFILTER_BROADCAST 0x00000020 +#define EMAC_FRMFILTER_PASS_MULTICAST 0x00000010 +#define EMAC_FRMFILTER_INV_DADDR 0x00000008 +#define EMAC_FRMFILTER_HASH_MULTICAST 0x00000004 +#define EMAC_FRMFILTER_HASH_UNICAST 0x00000002 +#define EMAC_FRMFILTER_PROMISCUOUS 0x00000001 + +//***************************************************************************** +// +// Values which may be returned by EMACStatusGet(). +// +//***************************************************************************** +#define EMAC_STATUS_TX_NOT_EMPTY 0x01000000 +#define EMAC_STATUS_TX_WRITING_FIFO 0x00400000 +#define EMAC_STATUS_TRC_STATE_MASK 0x00300000 +#define EMAC_STATUS_TRC_STATE_IDLE (0x00 << 20) +#define EMAC_STATUS_TRC_STATE_READING (0x01 << 20) +#define EMAC_STATUS_TRC_STATE_WAITING (0x02 << 20) +#define EMAC_STATUS_TRC_STATE_STATUS (0x03 << 20) +#define EMAC_STATUS_TX_PAUSED 0x00080000 +#define EMAC_STATUS_TFC_STATE_MASK 0x00060000 +#define EMAC_STATUS_TFC_STATE_IDLE (0x00 << 17) +#define EMAC_STATUS_TFC_STATE_WAITING (0x01 << 17) +#define EMAC_STATUS_TFC_STATE_PAUSING (0x02 << 17) +#define EMAC_STATUS_TFC_STATE_WRITING (0x03 << 17) +#define EMAC_STATUS_MAC_NOT_IDLE 0x00010000 +#define EMAC_STATUS_RX_FIFO_LEVEL_MASK 0x00000300 +#define EMAC_STATUS_RX_FIFO_EMPTY (0x00 << 8) +#define EMAC_STATUS_RX_FIFO_BELOW (0x01 << 8) +#define EMAC_STATUS_RX_FIFO_ABOVE (0x02 << 8) +#define EMAC_STATUS_RX_FIFO_FULL (0x03 << 8) +#define EMAC_STATUS_RX_FIFO_STATE_MASK 0x00000060 +#define EMAC_STATUS_RX_FIFO_IDLE (0x00 << 5) +#define EMAC_STATUS_RX_FIFO_READING (0x01 << 5) +#define EMAC_STATUS_RX_FIFO_STATUS (0x02 << 5) +#define EMAC_STATUS_RX_FIFO_FLUSHING (0x03 << 5) +#define EMAC_STATUS_RWC_ACTIVE 0x00000010 +#define EMAC_STATUS_RPE_ACTIVE 0x00000001 + +//***************************************************************************** +// +// Values which may be returned by EMACDMAStateGet(). +// +//***************************************************************************** +#define EMAC_DMA_TXSTAT_MASK (0x07 << 20) +#define EMAC_DMA_TXSTAT_STOPPED (0x00 << 20) +#define EMAC_DMA_TXSTAT_RUN_FETCH_DESC (0x01 << 20) +#define EMAC_DMA_TXSTAT_RUN_WAIT_STATUS (0x02 << 20) +#define EMAC_DMA_TXSTAT_RUN_READING (0x03 << 20) +#define EMAC_DMA_TXSTAT_RUN_CLOSE_DESC (0x07 << 20) +#define EMAC_DMA_TXSTAT_TS_WRITE (0x04 << 20) +#define EMAC_DMA_TXSTAT_SUSPENDED (0x06 << 20) + +#define EMAC_DMA_RXSTAT_MASK (0x07 << 17) +#define EMAC_DMA_RXSTAT_STOPPED (0x00 << 17) +#define EMAC_DMA_RXSTAT_RUN_FETCH_DESC (0x01 << 17) +#define EMAC_DMA_RXSTAT_RUN_WAIT_PACKET (0x03 << 17) +#define EMAC_DMA_RXSTAT_SUSPENDED (0x04 << 17) +#define EMAC_DMA_RXSTAT_RUN_CLOSE_DESC (0x05 << 17) +#define EMAC_DMA_RXSTAT_TS_WRITE (0x06 << 17) +#define EMAC_DMA_RXSTAT_RUN_RECEIVING (0x07 << 17) + +#define EMAC_TX_DMA_STATE(x) ((x) & EMAC_DMA_TXSTAT_MASK) +#define EMAC_RX_DMA_STATE(x) ((x) & EMAC_DMA_RXSTAT_MASK) + +#define EMAC_DMA_ERROR 0x00002000 +#define EMAC_DMA_ERR_MASK 0x03800000 +#define EMAC_DMA_ERR_RX_DATA_WRITE 0x00000000 +#define EMAC_DMA_ERR_TX_DATA_READ 0x01800000 +#define EMAC_DMA_ERR_RX_DESC_WRITE 0x02000000 +#define EMAC_DMA_ERR_TX_DESC_WRITE 0x02800000 +#define EMAC_DMA_ERR_RX_DESC_READ 0x03000000 +#define EMAC_DMA_ERR_TX_DESC_READ 0x03800000 + +//***************************************************************************** +// +// Values which may be ORed together in the ui32Config parameter passed to +// EMACAddrFilterSet and which may be returned by EMACAddrFilterGet. +// +//***************************************************************************** +#define EMAC_FILTER_ADDR_ENABLE 0x80000000 +#define EMAC_FILTER_SOURCE_ADDR 0x40000000 +#define EMAC_FILTER_MASK_BYTE_6 0x20000000 +#define EMAC_FILTER_MASK_BYTE_5 0x10000000 +#define EMAC_FILTER_MASK_BYTE_4 0x08000000 +#define EMAC_FILTER_MASK_BYTE_3 0x04000000 +#define EMAC_FILTER_MASK_BYTE_2 0x03000000 +#define EMAC_FILTER_MASK_BYTE_1 0x01000000 + +#define EMAC_FILTER_BYTE_MASK_M 0x3F000000 +#define EMAC_FILTER_BYTE_MASK_S 24 + +//***************************************************************************** +// +// Flags passed to EMACTimestampConfigSet or returned from +// EMACTimestampConfigGet. +// +//***************************************************************************** +#define EMAC_TS_MAC_FILTER_ENABLE 0x00040000 +#define EMAC_TS_MAC_FILTER_DISABLE 0x00000000 +#define EMAC_TS_SYNC_FOLLOW_DREQ_DRESP 0x00000000 +#define EMAC_TS_SYNC_ONLY 0x00004000 +#define EMAC_TS_DELAYREQ_ONLY 0x0000C000 +#define EMAC_TS_ALL 0x00010000 +#define EMAC_TS_SYNC_PDREQ_PDRESP 0x00014000 +#define EMAC_TS_DREQ_PDREQ_PDRESP 0x0001C000 +#define EMAC_TS_SYNC_DELAYREQ 0x00020000 +#define EMAC_TS_PDREQ_PDRESP 0x00030000 +#define EMAC_TS_PROCESS_IPV4_UDP 0x00002000 +#define EMAC_TS_PROCESS_IPV6_UDP 0x00001000 +#define EMAC_TS_PROCESS_ETHERNET 0x00000800 +#define EMAC_TS_PTP_VERSION_2 0x00000400 +#define EMAC_TS_PTP_VERSION_1 0x00000000 +#define EMAC_TS_DIGITAL_ROLLOVER 0x00000200 +#define EMAC_TS_BINARY_ROLLOVER 0x00000000 +#define EMAC_TS_ALL_RX_FRAMES 0x00000100 +#define EMAC_TS_UPDATE_FINE 0x00000002 +#define EMAC_TS_UPDATE_COARSE 0x00000000 + +//***************************************************************************** +// +// Some register bit definitions relating to external PHYs. These are not +// relevant (or available) when using the internal Ethernet PHY but having +// the definitions here helps when using an external MII or RMII PHY. +// +//***************************************************************************** +#define EPHY_SCR_INPOL_EXT 0x00000008 +#define EPHY_SCR_TINT_EXT 0x00000004 +#define EPHY_SCR_INTEN_EXT 0x00000002 +#define EPHY_SCR_INTOE_EXT 0x00000001 + +//***************************************************************************** +// +// These interrupt sources may be passed to EMACIntEnable() and +// EMACIntDisable() to enable or disable various Ethernet interrupt sources. +// +//***************************************************************************** +// +// Note that interrupts relating to timestamping and power management must be +// independently enabled via calls to functions EMACTimestampTargetIntEnable +// and EMACPowerManagementControlSet. +// +// EMAC_INT_PHY is deliberately set to a reserved bit in the MAC interrupt +// register. We handle the fact that the PHY interrupt is controlled via an +// independent register within the code. If we didn't do this, the app would +// have to enable the MAC interrupt then enable the PHY interrupt via a +// different API (since they share a vector). To further complicate matters, +// they would have to call EMACIntStatus() and then, if it returned 0, +// read the PHY interrupt status to see that it fired. This would be nasty +// and unfriendly so we hide it inside DriverLib. +// +//***************************************************************************** +#define EMAC_INT_PHY 0x80000000 +#define EMAC_INT_EARLY_RECEIVE 0x00004000 +#define EMAC_INT_BUS_ERROR 0x00002000 +#define EMAC_INT_EARLY_TRANSMIT 0x00000400 +#define EMAC_INT_RX_WATCHDOG 0x00000200 +#define EMAC_INT_RX_STOPPED 0x00000100 +#define EMAC_INT_RX_NO_BUFFER 0x00000080 +#define EMAC_INT_RECEIVE 0x00000040 +#define EMAC_INT_TX_UNDERFLOW 0x00000020 +#define EMAC_INT_RX_OVERFLOW 0x00000010 +#define EMAC_INT_TX_JABBER 0x00000008 +#define EMAC_INT_TX_NO_BUFFER 0x00000004 +#define EMAC_INT_TX_STOPPED 0x00000002 +#define EMAC_INT_TRANSMIT 0x00000001 + +// +// These interrupt sources are summary indicators. They are readable +// using EMACIntStatus() and must be cleared using EMACIntClear(). They +// may be enabled or disabled independently of the group of interrupts that +// they are derived from but offer merely a simple way to be informed of a +// normal or abnormal condition requiring software attention. +// +// EMAC_INT_NORMAL_INT is the logical OR of the masked state of +// EMAC_INT_TRANSMIT | EMAC_INT_RECEIVE | EMAC_INT_TX_NO_BUFFER | +// EMAC_INT_EARLY_RECEIVE. +// +// EMAC_INT_ABNORMAL_INT is the logical OR of the masked state of +// EMAC_INT_TX_STOPPED | EMAC_INT_TX_JABBER | EMAC_INT_RX_OVERFLOW | +// EMAC_INT_TX_UNDERFLOW | EMAC_INT_RX_NO_BUFFER | EMAC_INT_RX_STOPPED | +// EMAC_INT_RX_WATCHDOG | EMAC_INT_EARLY_TRANSMIT | EMAC_INT_BUS_ERROR. +// +#define EMAC_INT_NORMAL_INT 0x00010000 +#define EMAC_INT_ABNORMAL_INT 0x00008000 + +// +// This interrupt source is readable using EMACIntStatus but must +// be cleared by calling the EMACEEEStatus(). +// +#define EMAC_INT_LPI 0x40000000 + +// +// This interrupt source is readable using EMACIntStatus but must +// be cleared by calling the EMACTimestampIntStatus(). +// +#define EMAC_INT_TIMESTAMP 0x20000000 + +// +// Interrupt sources which may be returned from EMACTimestampIntStatus(). +// +#define EMAC_TS_INT_TARGET_REACHED 0x00000002 +#define EMAC_TS_INT_TS_SEC_OVERFLOW 0x00000001 + +// +// This interrupt source is readable using EMACIntStatus but must +// be cleared by calling EMACPowerManagementStatusGet(). +// +#define EMAC_INT_POWER_MGMNT 0x10000000 + +//***************************************************************************** +// +// Configuration flags that may be passed in the ui32FreqConfig parameter to +// EMACTimestampPPSSimpleModeSet(). +// +//***************************************************************************** +#define EMAC_PPS_SINGLE_PULSE 0x00000000 +#define EMAC_PPS_1HZ 0x00000001 +#define EMAC_PPS_2HZ 0x00000002 +#define EMAC_PPS_4HZ 0x00000003 +#define EMAC_PPS_8HZ 0x00000004 +#define EMAC_PPS_16HZ 0x00000005 +#define EMAC_PPS_32HZ 0x00000006 +#define EMAC_PPS_64HZ 0x00000007 +#define EMAC_PPS_128HZ 0x00000008 +#define EMAC_PPS_256HZ 0x00000009 +#define EMAC_PPS_512HZ 0x0000000A +#define EMAC_PPS_1024HZ 0x0000000B +#define EMAC_PPS_2048HZ 0x0000000C +#define EMAC_PPS_4096HZ 0x0000000D +#define EMAC_PPS_8192HZ 0x0000000E +#define EMAC_PPS_16384HZ 0x0000000F +#define EMAC_PPS_32768HZ 0x00000010 + +//***************************************************************************** +// +// Configuration flags that may be passed in the ui32Config parameter to +// EMACTimestampPPSCommandModeSet(). +// +//***************************************************************************** +#define EMAC_PPS_TARGET_INT 0x00000000 +#define EMAC_PPS_TARGET_PPS 0x00000060 +#define EMAC_PPS_TARGET_BOTH 0x00000040 + +//***************************************************************************** +// +// Commands which may be passed to EMACTimestampPPSCmd. +// +//***************************************************************************** +#define EMAC_PPS_COMMAND_NONE 0x00 +#define EMAC_PPS_COMMAND_START_SINGLE 0x01 +#define EMAC_PPS_COMMAND_START_TRAIN 0x02 +#define EMAC_PPS_COMMAND_CANCEL_START 0x03 +#define EMAC_PPS_COMMAND_STOP_AT_TIME 0x04 +#define EMAC_PPS_COMMAND_STOP_NOW 0x05 +#define EMAC_PPS_COMMAND_CANCEL_STOP 0x06 + +//***************************************************************************** +// +// Values which may be passed to EMACVLANRxConfigSet in the ui32Config +// parameter and which may be returned from EMACVLANRxConfigGet. +// +//***************************************************************************** +#define EMAC_VLAN_RX_HASH_ENABLE 0x00080000 +#define EMAC_VLAN_RX_HASH_DISABLE 0x00000000 +#define EMAC_VLAN_RX_SVLAN_ENABLE 0x00040000 +#define EMAC_VLAN_RX_SVLAN_DISABLE 0x00000000 +#define EMAC_VLAN_RX_NORMAL_MATCH 0x00000000 +#define EMAC_VLAN_RX_INVERSE_MATCH 0x00020000 +#define EMAC_VLAN_RX_12BIT_TAG 0x00010000 +#define EMAC_VLAN_RX_16BIT_TAG 0x00000000 + +//***************************************************************************** +// +// Values which may be passed to EMACVLANTxConfigSet in the ui32Config +// parameter and which may be returned from EMACVLANTxConfigGet. +// +//***************************************************************************** +#define EMAC_VLAN_TX_CVLAN 0x00000000 +#define EMAC_VLAN_TX_SVLAN 0x00080000 +#define EMAC_VLAN_TX_USE_VLC 0x00040000 +#define EMAC_VLAN_TX_VLC_NONE 0x00000000 +#define EMAC_VLAN_TX_VLC_DELETE 0x00010000 +#define EMAC_VLAN_TX_VLC_INSERT 0x00020000 +#define EMAC_VLAN_TX_VLC_REPLACE 0x00030000 + +#define EMAC_VLAN_TX_VLC_MASK 0x00030000 + +#define EMAC_RWU_FILTER_ENABLE 1 +#define EMAC_RWU_FILTER_DISABLE 0 +#define EMAC_RWU_FILTER_MULTICAST 8 +#define EMAC_RWU_FILTER_UNICAST 0 + +//***************************************************************************** +// +// The following structure fields must be packed. +// +//***************************************************************************** +#ifdef ewarm +#pragma pack(1) +#endif + +//***************************************************************************** +// +//! This structure defines up to 4 filters that can be used to define specific +//! frames which will cause the MAC to wake up from sleep mode. +// +//***************************************************************************** +typedef struct +{ + // + //! A byte mask for each filter defining which bytes from a sequence of + //! 31 (bit 31 must be clear in each mask) are used to filter incoming + //! packets. A 1 indicates that the relevant byte is used to update the + //! CRC16 for the filter, a 0 indicates that the byte is ignored. + // + uint32_t pui32ByteMask[4]; + + // + //! Defines whether each filter is enabled and, if so, whether it filters + //! multicast or unicast frames. Valid values are one of + //! EMAC_RWU_FILTER_ENABLE or EMAC_RWU_FILTER_DISABLE ORed with one of + //! EMAC_RWU_FILTER_UNICAST or EMAC_RWU_FILTER_MULTICAST. + // + uint8_t pui8Command[4]; + + // + //! Determines the byte offset within the frame at which the filter starts + //! examining bytes. The minimum value for each offset is 12. The first + //! byte of a frame is offset 0. + // + uint8_t pui8Offset[4]; + + // + //! The CRC16 value that is expected for each filter if it passes. The + //! CRC is calculated using all bytes indicated by the filter's mask. + // + uint16_t pui16CRC[4]; +} +#if defined(ccs) || \ + defined(codered) || \ + defined(gcc) || \ + defined(rvmdk) || \ + defined(__ARMCC_VERSION) || \ + defined(sourcerygxx) +__attribute__ ((packed)) tEMACWakeUpFrameFilter; +#else +tEMACWakeUpFrameFilter; +#endif + +//***************************************************************************** +// +// Turn off structure packing again. +// +//***************************************************************************** +#ifdef ewarm +#pragma pack() +#endif + +//***************************************************************************** +// +// Values which may be ORed together and used in the ui32Flags parameter to +// EMACPowerManagementControlSet. These may also returned be from a call to +// EMACPowerManagementControlGet. +// +//***************************************************************************** +#define EMAC_PMT_GLOBAL_UNICAST_ENABLE 0x00000200 +#define EMAC_PMT_WAKEUP_PACKET_ENABLE 0x00000004 +#define EMAC_PMT_MAGIC_PACKET_ENABLE 0x00000002 +#define EMAC_PMT_POWER_DOWN 0x00000001 + +//***************************************************************************** +// +// Values which may be ORed together and returned from a call to +// EMACPowerManagementStatusGet. This call will also return +// EMAC_PMT_POWER_DOWN if the MAC is in power-down mode. +// +//***************************************************************************** +#define EMAC_PMT_WAKEUP_PACKET_RECEIVED 0x00000040 +#define EMAC_PMT_MAGIC_PACKET_RECEIVED 0x00000020 + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Public function prototypes. +// +//***************************************************************************** +extern void EMACInit(uint32_t ui32Base, uint32_t ui32SysClk, + uint32_t ui32BusConfig, uint32_t ui32RxBurst, + uint32_t ui32TxBurst, uint32_t ui32DescSkipSize); +extern void EMACReset(uint32_t ui32Base); +extern void EMACPHYConfigSet(uint32_t ui32Base, uint32_t ui32Config); +extern void EMACConfigSet(uint32_t ui32Base, uint32_t ui32Config, + uint32_t ui32ModeFlags, + uint32_t ui32RxMaxFrameSize); +extern void EMACFrameFilterSet(uint32_t ui32Base, uint32_t ui32FilterOpts); +extern uint32_t EMACFrameFilterGet(uint32_t ui32Base); +extern void EMACHashFilterSet(uint32_t ui32Base, uint32_t ui32HashHi, + uint32_t ui32HashLo); +extern void EMACHashFilterGet(uint32_t ui32Base, uint32_t *pui32HashHi, + uint32_t *pui32HashLo); +extern uint32_t EMACHashFilterBitCalculate(uint8_t *pui8MACAddr); +extern void EMACTxDMAPollDemand(uint32_t ui32Base); +extern void EMACRxDMAPollDemand(uint32_t ui32Base); +extern void EMACRxDMADescriptorListSet(uint32_t ui32Base, + tEMACDMADescriptor *pDescriptor); +extern tEMACDMADescriptor *EMACRxDMADescriptorListGet(uint32_t ui32Base); +extern tEMACDMADescriptor *EMACRxDMACurrentDescriptorGet(uint32_t ui32Base); +extern uint8_t *EMACRxDMACurrentBufferGet(uint32_t ui32Base); +extern void EMACTxDMADescriptorListSet(uint32_t ui32Base, + tEMACDMADescriptor *pDescriptor); +extern tEMACDMADescriptor *EMACTxDMADescriptorListGet(uint32_t ui32Base); +extern tEMACDMADescriptor *EMACTxDMACurrentDescriptorGet(uint32_t ui32Base); +extern uint8_t *EMACTxDMACurrentBufferGet(uint32_t ui32Base); +extern void EMACConfigGet(uint32_t ui32Base, uint32_t *pui32Config, + uint32_t *pui32Mode, uint32_t *pui32RxMaxFrameSize); +extern void EMACAddrSet(uint32_t ui32Base, uint32_t ui32Index, + const uint8_t *pui8MACAddr); +extern void EMACAddrGet(uint32_t ui32Base, uint32_t ui32Index, + uint8_t *pui8MACAddr); +extern uint32_t EMACNumAddrGet(uint32_t ui32Base); +extern void EMACAddrFilterSet(uint32_t ui32Base, uint32_t ui32Index, + uint32_t ui32Config); +extern uint32_t EMACAddrFilterGet(uint32_t ui32Base, uint32_t ui32Index); +extern void EMACRxWatchdogTimerSet(uint32_t ui32Base, uint8_t ui8Timeout); +extern uint32_t EMACStatusGet(uint32_t ui32Base); +extern uint32_t EMACDMAStateGet(uint32_t ui32Base); +extern void EMACTxFlush(uint32_t ui32Base); +extern void EMACTxEnable(uint32_t ui32Base); +extern void EMACTxDisable(uint32_t ui32Base); +extern void EMACRxEnable(uint32_t ui32Base); +extern void EMACRxDisable(uint32_t ui32Base); +extern void EMACIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void EMACIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern uint32_t EMACIntStatus(uint32_t ui32Base, bool bMasked); +extern void EMACIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void EMACIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); +extern void EMACIntUnregister(uint32_t ui32Base); +extern void EMACPHYWrite(uint32_t ui32Base, uint8_t ui8PhyAddr, + uint8_t ui8RegAddr, uint16_t ui16Data); +extern void EMACPHYExtendedWrite(uint32_t ui32Base, uint8_t ui8PhyAddr, + uint16_t ui16RegAddr, uint16_t ui16Data); +extern uint16_t EMACPHYRead(uint32_t ui32Base, uint8_t ui8PhyAddr, + uint8_t ui8RegAddr); +extern uint16_t EMACPHYExtendedRead(uint32_t ui32Base, uint8_t ui8PhyAddr, + uint16_t ui16RegAddr); +extern void EMACPHYPowerOff(uint32_t ui32Base, uint8_t ui8PhyAddr); +extern void EMACPHYPowerOn(uint32_t ui32Base, uint8_t ui8PhyAddr); +extern void EMACTimestampConfigSet(uint32_t ui32Base, uint32_t ui32Config, + uint32_t ui32SubSecondInc); +extern uint32_t EMACTimestampConfigGet(uint32_t ui32Base, + uint32_t *pui32SubSecondInc); +extern void EMACTimestampAddendSet(uint32_t ui32Base, uint32_t ui32Seconds); +extern void EMACTimestampEnable(uint32_t ui32Base); +extern void EMACTimestampDisable(uint32_t ui32Base); +extern void EMACTimestampSysTimeSet(uint32_t ui32Base, uint32_t ui32Seconds, + uint32_t ui32SubSeconds); +extern void EMACTimestampSysTimeGet(uint32_t ui32Base, uint32_t *pui32Seconds, + uint32_t *pui32SubSeconds); +extern void EMACTimestampSysTimeUpdate(uint32_t ui32Base, uint32_t ui32Seconds, + uint32_t ui32SubSeconds, bool bInc); +extern void EMACTimestampTargetSet(uint32_t ui32Base, uint32_t ui32Seconds, + uint32_t ui32Nanoseconds); +extern void EMACTimestampTargetIntEnable(uint32_t ui32Base); +extern void EMACTimestampTargetIntDisable(uint32_t ui32Base); +extern uint32_t EMACTimestampIntStatus(uint32_t ui32Base); +extern void EMACTimestampPPSSimpleModeSet(uint32_t ui32Base, + uint32_t ui32FreqConfig); +extern void EMACTimestampPPSCommandModeSet(uint32_t ui32Base, + uint32_t ui32Config); +extern void EMACTimestampPPSCommand(uint32_t ui32Base, uint8_t ui8Cmd); +extern void EMACTimestampPPSPeriodSet(uint32_t ui32Base, uint32_t ui32Period, + uint32_t ui32Width); +extern void EMACVLANRxConfigSet(uint32_t ui32Base, uint16_t ui16Tag, + uint32_t ui32Config); +extern uint32_t EMACVLANRxConfigGet(uint32_t ui32Base, uint16_t *pui16Tag); +extern void EMACVLANTxConfigSet(uint32_t ui32Base, uint16_t ui16Tag, + uint32_t ui32Config); +extern uint32_t EMACVLANTxConfigGet(uint32_t ui32Base, uint16_t *pui16Tag); +extern uint32_t EMACVLANHashFilterBitCalculate(uint16_t ui16Tag); +extern void EMACVLANHashFilterSet(uint32_t ui32Base, uint32_t ui32Hash); +extern uint32_t EMACVLANHashFilterGet(uint32_t ui32Base); +extern void EMACRemoteWakeUpFrameFilterSet(uint32_t ui32Base, + const tEMACWakeUpFrameFilter *pFilter); +extern void EMACRemoteWakeUpFrameFilterGet(uint32_t ui32Base, + tEMACWakeUpFrameFilter *pFilter); +extern void EMACPowerManagementControlSet(uint32_t ui32Base, + uint32_t ui32Flags); +extern uint32_t EMACPowerManagementControlGet(uint32_t ui32Base); +extern uint32_t EMACPowerManagementStatusGet(uint32_t ui32Base); +extern void EMACWoLEnter(uint32_t ui32Base); +extern void EMACLPIConfig(uint32_t ui32Base, bool bLPIConfig, + uint16_t ui16LPILSTimer, uint16_t ui16LPITWTimer); +extern void EMACLPIEnter(uint32_t ui32Base); +extern uint16_t EMACLPIStatus(uint32_t ui32Base); +extern void EMACLPILinkSet(uint32_t ui32Base); +extern void EMACLPILinkClear(uint32_t ui32Base); +extern void EMACPHYMMDWrite(uint32_t ui32Base, uint8_t ui8PhyAddr, + uint16_t ui16RegAddr, uint16_t ui16Data); +extern uint16_t EMACPHYMMDRead(uint32_t ui32Base, uint8_t ui8PhyAddr, + uint16_t ui16RegAddr); +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_EMAC_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/epi.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/epi.h new file mode 100644 index 0000000000000000000000000000000000000000..fc26a81469d0da841d97a5daab6468f522f94d1f --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/epi.h @@ -0,0 +1,762 @@ +//***************************************************************************** +// +// epi.h - Prototypes and macros for the EPI module. +// +// Copyright (c) 2008-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_EPI_H__ +#define __DRIVERLIB_EPI_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to EPIModeSet() +// +//***************************************************************************** +#define EPI_MODE_GENERAL 0x00000010 +#define EPI_MODE_SDRAM 0x00000011 +#define EPI_MODE_HB8 0x00000012 +#define EPI_MODE_HB16 0x00000013 +#define EPI_MODE_DISABLE 0x00000000 + +//***************************************************************************** +// +// Values that can be passed to EPIConfigSDRAMSet() +// +//***************************************************************************** +#define EPI_SDRAM_CORE_FREQ_0_15 \ + 0x00000000 +#define EPI_SDRAM_CORE_FREQ_15_30 \ + 0x40000000 +#define EPI_SDRAM_CORE_FREQ_30_50 \ + 0x80000000 +#define EPI_SDRAM_CORE_FREQ_50_100 \ + 0xC0000000 +#define EPI_SDRAM_LOW_POWER 0x00000200 +#define EPI_SDRAM_FULL_POWER 0x00000000 +#define EPI_SDRAM_SIZE_64MBIT 0x00000000 +#define EPI_SDRAM_SIZE_128MBIT 0x00000001 +#define EPI_SDRAM_SIZE_256MBIT 0x00000002 +#define EPI_SDRAM_SIZE_512MBIT 0x00000003 + +//***************************************************************************** +// +// Values that can be passed to EPIConfigGPModeSet() +// +//***************************************************************************** +#define EPI_GPMODE_CLKPIN 0x80000000 +#define EPI_GPMODE_CLKGATE 0x40000000 +#define EPI_GPMODE_FRAME50 0x04000000 +#define EPI_GPMODE_WRITE2CYCLE 0x00080000 +#define EPI_GPMODE_ASIZE_NONE 0x00000000 +#define EPI_GPMODE_ASIZE_4 0x00000010 +#define EPI_GPMODE_ASIZE_12 0x00000020 +#define EPI_GPMODE_ASIZE_20 0x00000030 +#define EPI_GPMODE_DSIZE_8 0x00000000 +#define EPI_GPMODE_DSIZE_16 0x00000001 +#define EPI_GPMODE_DSIZE_24 0x00000002 +#define EPI_GPMODE_DSIZE_32 0x00000003 + +//***************************************************************************** +// +// Values that can be passed to EPIConfigHB8ModeSet() +// +//***************************************************************************** +#define EPI_HB8_USE_TXEMPTY 0x00800000 +#define EPI_HB8_USE_RXFULL 0x00400000 +#define EPI_HB8_WRHIGH 0x00200000 +#define EPI_HB8_RDHIGH 0x00100000 +#define EPI_HB8_ALE_HIGH 0x00080000 +#define EPI_HB8_ALE_LOW 0x00000000 +#define EPI_HB8_WRWAIT_0 0x00000000 +#define EPI_HB8_WRWAIT_1 0x00000040 +#define EPI_HB8_WRWAIT_2 0x00000080 +#define EPI_HB8_WRWAIT_3 0x000000C0 +#define EPI_HB8_RDWAIT_0 0x00000000 +#define EPI_HB8_RDWAIT_1 0x00000010 +#define EPI_HB8_RDWAIT_2 0x00000020 +#define EPI_HB8_RDWAIT_3 0x00000030 +#define EPI_HB8_MODE_ADMUX 0x00000000 +#define EPI_HB8_MODE_ADDEMUX 0x00000001 +#define EPI_HB8_MODE_SRAM 0x00000002 +#define EPI_HB8_MODE_FIFO 0x00000003 +#define EPI_HB8_WORD_ACCESS 0x00000100 +#define EPI_HB8_CSCFG_ALE 0x00000000 +#define EPI_HB8_CSCFG_CS 0x00000200 +#define EPI_HB8_CSCFG_DUAL_CS 0x00000400 +#define EPI_HB8_CSCFG_ALE_DUAL_CS \ + 0x00000600 +#define EPI_HB8_CSCFG_ALE_SINGLE_CS \ + 0x00001000 +#define EPI_HB8_CSCFG_QUAD_CS 0x00001200 +#define EPI_HB8_CSCFG_ALE_QUAD_CS \ + 0x00001400 +#define EPI_HB8_CSBAUD 0x00000800 +#define EPI_HB8_CLOCK_GATE 0x80000000 +#define EPI_HB8_CLOCK_GATE_IDLE \ + 0x40000000 +#define EPI_HB8_CLOCK_INVERT 0x20000000 +#define EPI_HB8_IN_READY_EN 0x10000000 +#define EPI_HB8_IN_READY_EN_INVERT \ + 0x18000000 +#define EPI_HB8_CSCFG_MASK 0x00001600 + +//***************************************************************************** +// +// Values that can be passed to EPIConfigHB16ModeSet() +// +//***************************************************************************** +#define EPI_HB16_USE_TXEMPTY 0x00800000 +#define EPI_HB16_USE_RXFULL 0x00400000 +#define EPI_HB16_WRHIGH 0x00200000 +#define EPI_HB16_RDHIGH 0x00100000 +#define EPI_HB16_WRWAIT_0 0x00000000 +#define EPI_HB16_WRWAIT_1 0x00000040 +#define EPI_HB16_WRWAIT_2 0x00000080 +#define EPI_HB16_WRWAIT_3 0x000000C0 +#define EPI_HB16_RDWAIT_0 0x00000000 +#define EPI_HB16_RDWAIT_1 0x00000010 +#define EPI_HB16_RDWAIT_2 0x00000020 +#define EPI_HB16_RDWAIT_3 0x00000030 +#define EPI_HB16_MODE_ADMUX 0x00000000 +#define EPI_HB16_MODE_ADDEMUX 0x00000001 +#define EPI_HB16_MODE_SRAM 0x00000002 +#define EPI_HB16_MODE_FIFO 0x00000003 +#define EPI_HB16_BSEL 0x00000004 +#define EPI_HB16_WORD_ACCESS 0x00000100 +#define EPI_HB16_CSCFG_ALE 0x00000000 +#define EPI_HB16_CSCFG_CS 0x00000200 +#define EPI_HB16_CSCFG_DUAL_CS 0x00000400 +#define EPI_HB16_CSCFG_ALE_DUAL_CS \ + 0x00000600 +#define EPI_HB16_CSCFG_ALE_SINGLE_CS \ + 0x00001000 +#define EPI_HB16_CSCFG_QUAD_CS 0x00001200 +#define EPI_HB16_CSCFG_ALE_QUAD_CS \ + 0x00001400 +#define EPI_HB16_CLOCK_GATE 0x80000000 +#define EPI_HB16_CLOCK_GATE_IDLE \ + 0x40000000 +#define EPI_HB16_CLOCK_INVERT 0x20000000 +#define EPI_HB16_IN_READY_EN 0x10000000 +#define EPI_HB16_IN_READY_EN_INVERTED \ + 0x18000000 +#define EPI_HB16_ALE_HIGH 0x00080000 +#define EPI_HB16_ALE_LOW 0x00000000 +#define EPI_HB16_BURST_TRAFFIC 0x00010000 +#define EPI_HB16_CSBAUD 0x00000800 +#define EPI_HB16_CSCFG_MASK 0x00001600 + +//***************************************************************************** +// +// Values that can be passed to EPIConfigHB8TimingSet(). +// +//***************************************************************************** +#define EPI_HB8_IN_READY_DELAY_1 \ + 0x01000000 +#define EPI_HB8_IN_READY_DELAY_2 \ + 0x02000000 +#define EPI_HB8_IN_READY_DELAY_3 \ + 0x03000000 +#define EPI_HB8_CAP_WIDTH_1 0x00001000 +#define EPI_HB8_CAP_WIDTH_2 0x00002000 +#define EPI_HB8_WRWAIT_MINUS_DISABLE \ + 0x00000000 +#define EPI_HB8_WRWAIT_MINUS_ENABLE \ + 0x00000010 +#define EPI_HB8_RDWAIT_MINUS_DISABLE \ + 0x00000000 +#define EPI_HB8_RDWAIT_MINUS_ENABLE \ + 0x00000001 + +//***************************************************************************** +// +// Values that can be passed to EPIConfigHB16TimingSet(). +// +//***************************************************************************** +#define EPI_HB16_IN_READY_DELAY_1 \ + 0x01000000 +#define EPI_HB16_IN_READY_DELAY_2 \ + 0x02000000 +#define EPI_HB16_IN_READY_DELAY_3 \ + 0x03000000 +#define EPI_HB16_PSRAM_NO_LIMIT 0x00000000 +#define EPI_HB16_PSRAM_128 0x00010000 +#define EPI_HB16_PSRAM_256 0x00020000 +#define EPI_HB16_PSRAM_512 0x00030000 +#define EPI_HB16_PSRAM_1024 0x00040000 +#define EPI_HB16_PSRAM_2048 0x00050000 +#define EPI_HB16_PSRAM_4096 0x00060000 +#define EPI_HB16_PSRAM_8192 0x00070000 +#define EPI_HB16_CAP_WIDTH_1 0x00001000 +#define EPI_HB16_CAP_WIDTH_2 0x00002000 +#define EPI_HB16_WRWAIT_MINUS_DISABLE \ + 0x00000000 +#define EPI_HB16_WRWAIT_MINUS_ENABLE \ + 0x00000008 +#define EPI_HB16_RDWAIT_MINUS_DISABLE \ + 0x00000000 +#define EPI_HB16_RDWAIT_MINUS_ENABLE \ + 0x00000001 + +//***************************************************************************** +// +// Values that can be passed to EPIAddressMapSet(). +// +//***************************************************************************** +#define EPI_ADDR_PER_SIZE_256B 0x00000000 +#define EPI_ADDR_PER_SIZE_64KB 0x00000040 +#define EPI_ADDR_PER_SIZE_16MB 0x00000080 +#define EPI_ADDR_PER_SIZE_256MB 0x000000C0 +#define EPI_ADDR_PER_BASE_NONE 0x00000000 +#define EPI_ADDR_PER_BASE_A 0x00000010 +#define EPI_ADDR_PER_BASE_C 0x00000020 +#define EPI_ADDR_RAM_SIZE_256B 0x00000000 +#define EPI_ADDR_RAM_SIZE_64KB 0x00000004 +#define EPI_ADDR_RAM_SIZE_16MB 0x00000008 +#define EPI_ADDR_RAM_SIZE_256MB 0x0000000C +#define EPI_ADDR_RAM_BASE_NONE 0x00000000 +#define EPI_ADDR_RAM_BASE_6 0x00000001 +#define EPI_ADDR_RAM_BASE_8 0x00000002 +#define EPI_ADDR_QUAD_MODE 0x00000033 +#define EPI_ADDR_CODE_SIZE_256B 0x00000000 +#define EPI_ADDR_CODE_SIZE_64KB 0x00000400 +#define EPI_ADDR_CODE_SIZE_16MB 0x00000800 +#define EPI_ADDR_CODE_SIZE_256MB \ + 0x00000C00 +#define EPI_ADDR_CODE_BASE_NONE 0x00000000 +#define EPI_ADDR_CODE_BASE_1 0x00000100 + +//***************************************************************************** +// +// Values that can be passed to EPINonBlockingReadConfigure() +// +//***************************************************************************** +#define EPI_NBCONFIG_SIZE_8 1 +#define EPI_NBCONFIG_SIZE_16 2 +#define EPI_NBCONFIG_SIZE_32 3 + +//***************************************************************************** +// +// Values that can be passed to EPIFIFOConfig() +// +//***************************************************************************** +#define EPI_FIFO_CONFIG_WTFULLERR \ + 0x00020000 +#define EPI_FIFO_CONFIG_RSTALLERR \ + 0x00010000 +#define EPI_FIFO_CONFIG_TX_EMPTY \ + 0x00000000 +#define EPI_FIFO_CONFIG_TX_1_4 0x00000020 +#define EPI_FIFO_CONFIG_TX_1_2 0x00000030 +#define EPI_FIFO_CONFIG_TX_3_4 0x00000040 +#define EPI_FIFO_CONFIG_RX_1_8 0x00000001 +#define EPI_FIFO_CONFIG_RX_1_4 0x00000002 +#define EPI_FIFO_CONFIG_RX_1_2 0x00000003 +#define EPI_FIFO_CONFIG_RX_3_4 0x00000004 +#define EPI_FIFO_CONFIG_RX_7_8 0x00000005 +#define EPI_FIFO_CONFIG_RX_FULL 0x00000006 + +//***************************************************************************** +// +// Values that can be passed to EPIIntEnable(), EPIIntDisable(), or returned +// as flags from EPIIntStatus() +// +//***************************************************************************** +#define EPI_INT_DMA_TX_DONE 0x00000010 +#define EPI_INT_DMA_RX_DONE 0x00000008 +#define EPI_INT_TXREQ 0x00000004 +#define EPI_INT_RXREQ 0x00000002 +#define EPI_INT_ERR 0x00000001 + +//***************************************************************************** +// +// Values that can be passed to EPIIntErrorClear(), or returned as flags from +// EPIIntErrorStatus() +// +//***************************************************************************** +#define EPI_INT_ERR_DMAWRIC 0x00000010 +#define EPI_INT_ERR_DMARDIC 0x00000008 +#define EPI_INT_ERR_WTFULL 0x00000004 +#define EPI_INT_ERR_RSTALL 0x00000002 +#define EPI_INT_ERR_TIMEOUT 0x00000001 + +#ifdef rvmdk +//***************************************************************************** +// +// Keil case. +// +//***************************************************************************** +inline void +EPIWorkaroundWordWrite(uint32_t *pui32Addr, uint32_t ui32Value) +{ + uint32_t ui32Scratch; + + __asm + { + // + // Add a NOP to ensure we dont have a flash read immediately before + // the EPI read. + // + NOP + + // + // Perform the write we're actually interested in. + // + STR ui32Value, [pui32Addr] + + // + // Read from SRAM to ensure that we don't have an EPI write followed by + // a flash read. + // + LDR ui32Scratch, [__current_sp()] + } +} + +inline uint32_t +EPIWorkaroundWordRead(uint32_t *pui32Addr) +{ + uint32_t ui32Value, ui32Scratch; + + __asm + { + // + // Add a NOP to ensure we dont have a flash read immediately before + // the EPI read. + // + NOP + + // + // Perform the read we're actually interested in. + // + LDR ui32Value, [pui32Addr] + + // + // Read from SRAM to ensure that we don't have an EPI read followed by + // a flash read. + // + LDR ui32Scratch, [__current_sp()] + } + + return(ui32Value); +} + +inline void +EPIWorkaroundHWordWrite(uint16_t *pui16Addr, uint16_t ui16Value) +{ + uint32_t ui32Scratch; + + __asm + { + // + // Add a NOP to ensure we dont have a flash read immediately before + // the EPI read. + // + NOP + + // + // Perform the write we're actually interested in. + // + STRH ui16Value, [pui16Addr] + + // + // Read from SRAM to ensure that we don't have an EPI write followed by + // a flash read. + // + LDR ui32Scratch, [__current_sp()] + } +} + +inline uint16_t +EPIWorkaroundHWordRead(uint16_t *pui16Addr) +{ + uint32_t ui32Scratch; + uint16_t ui16Value; + + __asm + { + // + // Add a NOP to ensure we dont have a flash read immediately before + // the EPI read. + // + NOP + + // + // Perform the read we're actually interested in. + // + LDRH ui16Value, [pui16Addr] + + // + // Read from SRAM to ensure that we don't have an EPI read followed by + // a flash read. + // + LDR ui32Scratch, [__current_sp()] + } + + return(ui16Value); +} + +inline void +EPIWorkaroundByteWrite(uint8_t *pui8Addr, uint8_t ui8Value) +{ + uint32_t ui32Scratch; + + __asm + { + // + // Add a NOP to ensure we dont have a flash read immediately before + // the EPI read. + // + NOP + + // + // Perform the write we're actually interested in. + // + STRB ui8Value, [pui8Addr] + + // + // Read from SRAM to ensure that we don't have an EPI write followed by + // a flash read. + // + LDR ui32Scratch, [__current_sp()] + } +} + +inline uint8_t +EPIWorkaroundByteRead(uint8_t *pui8Addr) +{ + uint32_t ui32Scratch; + uint8_t ui8Value; + + __asm + { + // + // Add a NOP to ensure we dont have a flash read immediately before + // the EPI read. + // + NOP + + // + // Perform the read we're actually interested in. + // + LDRB ui8Value, [pui8Addr] + + // + // Read from SRAM to ensure that we don't have an EPI read followed by + // a flash read. + // + LDR ui32Scratch, [__current_sp()] + } + + return(ui8Value); +} +#endif + +#ifdef ccs +//***************************************************************************** +// +// Code Composer Studio versions of these functions can be found in separate +// source file epi_workaround_ccs.s. +// +//***************************************************************************** +extern void EPIWorkaroundWordWrite(uint32_t *pui32Addr, uint32_t ui32Value); +extern uint32_t EPIWorkaroundWordRead(uint32_t *pui32Addr); +extern void EPIWorkaroundHWordWrite(uint16_t *pui16Addr, uint16_t ui16Value); +extern uint16_t EPIWorkaroundHWordRead(uint16_t *pui16Addr); +extern void EPIWorkaroundByteWrite(uint8_t *pui8Addr, uint8_t ui8Value); +extern uint8_t EPIWorkaroundByteRead(uint8_t *pui8Addr); + +#endif + +#if (defined gcc) || (defined ewarm) || (defined sourcerygxx) || \ + (defined codered) +//***************************************************************************** +// +// GCC-based toolchain and IAR case. +// +//***************************************************************************** +inline void +EPIWorkaroundWordWrite(uint32_t *pui32Addr, uint32_t ui32Value) +{ + volatile register uint32_t ui32Scratch; + + __asm volatile ( + // + // Add a NOP to ensure we dont have a flash read immediately before + // the EPI read. + // + " NOP\n" + " STR %[value],[%[addr]]\n" + " LDR %[scratch],[sp]\n" + : [scratch] "=r" (ui32Scratch) + : [addr] "r" (pui32Addr), [value] "r" (ui32Value) + ); + + // + // Keep the compiler from generating a warning. + // + ui32Scratch = ui32Scratch; +} + +inline uint32_t +EPIWorkaroundWordRead(uint32_t *pui32Addr) +{ + volatile register uint32_t ui32Data, ui32Scratch; + + // + // ui32Scratch is not used other than to add a padding read following the + // "real" read. + // + + __asm volatile( + // + // Add a NOP to ensure we dont have a flash read immediately before + // the EPI read. + // + " NOP\n" + " LDR %[ret],[%[addr]]\n" + " LDR %[scratch],[sp]\n" + : [ret] "=r" (ui32Data), + [scratch] "=r" (ui32Scratch) + : [addr] "r" (pui32Addr) + ); + + + // + // Keep the compiler from generating a warning. + // + ui32Scratch = ui32Scratch; + + return(ui32Data); +} + +inline void +EPIWorkaroundHWordWrite(uint16_t *pui16Addr, uint16_t ui16Value) +{ + volatile register uint32_t ui32Scratch; + + __asm volatile ( + // + // Add a NOP to ensure we dont have a flash read immediately before + // the EPI read. + // + " NOP\n" + " STRH %[value],[%[addr]]\n" + " LDR %[scratch],[sp]\n" + : [scratch] "=r" (ui32Scratch) + : [addr] "r" (pui16Addr), [value] "r" (ui16Value) + ); + + + // + // Keep the compiler from generating a warning. + // + ui32Scratch = ui32Scratch; +} + +inline uint16_t +EPIWorkaroundHWordRead(uint16_t *pui16Addr) +{ + register uint16_t ui16Data; + register uint32_t ui32Scratch; + + // + // ui32Scratch is not used other than to add a padding read following the + // "real" read. + // + + __asm volatile( + // + // Add a NOP to ensure we dont have a flash read immediately before + // the EPI read. + // + " NOP\n" + " LDRH %[ret],[%[addr]]\n" + " LDR %[scratch],[sp]\n" + : [ret] "=r" (ui16Data), + [scratch] "=r" (ui32Scratch) + : [addr] "r" (pui16Addr) + ); + + // + // Keep the compiler from generating a warning. + // + ui32Scratch = ui32Scratch; + + return(ui16Data); +} + +inline void +EPIWorkaroundByteWrite(uint8_t *pui8Addr, uint8_t ui8Value) +{ + volatile register uint32_t ui32Scratch; + + __asm volatile ( + // + // Add a NOP to ensure we dont have a flash read immediately before + // the EPI read. + // + " NOP\n" + " STRB %[value],[%[addr]]\n" + " LDR %[scratch],[sp]\n" + : [scratch] "=r" (ui32Scratch) + : [addr] "r" (pui8Addr), [value] "r" (ui8Value) + ); + + // + // Keep the compiler from generating a warning. + // + ui32Scratch = ui32Scratch; +} + +inline uint8_t +EPIWorkaroundByteRead(uint8_t *pui8Addr) +{ + register uint8_t ui8Data; + register uint32_t ui32Scratch; + + // + // ui32Scratch is not used other than to add a padding read following the + // "real" read. + // + + __asm volatile( + // + // Add a NOP to ensure we dont have a flash read immediately before + // the EPI read. + // + " NOP\n" + " LDRB %[ret],[%[addr]]\n" + " LDR %[scratch],[sp]\n" + : [ret] "=r" (ui8Data), + [scratch] "=r" (ui32Scratch) + : [addr] "r" (pui8Addr) + ); + + // + // Keep the compiler from generating a warning. + // + ui32Scratch = ui32Scratch; + + return(ui8Data); +} +#endif + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void EPIModeSet(uint32_t ui32Base, uint32_t ui32Mode); +extern void EPIDividerSet(uint32_t ui32Base, uint32_t ui32Divider); +extern void EPIDividerCSSet(uint32_t ui32Base, uint32_t ui32CS, + uint32_t ui32Divider); +extern void EPIDMATxCount(uint32_t ui32Base, uint32_t ui32Count); +extern void EPIConfigGPModeSet(uint32_t ui32Base, uint32_t ui32Config, + uint32_t ui32FrameCount, uint32_t ui32MaxWait); +extern void EPIConfigHB8Set(uint32_t ui32Base, uint32_t ui32Config, + uint32_t ui32MaxWait); +extern void EPIConfigHB16Set(uint32_t ui32Base, uint32_t ui32Config, + uint32_t ui32MaxWait); +extern void EPIConfigHB8CSSet(uint32_t ui32Base, uint32_t ui32CS, + uint32_t ui32Config); +extern void EPIConfigHB16CSSet(uint32_t ui32Base, uint32_t ui32CS, + uint32_t ui32Config); +extern void EPIConfigHB8TimingSet(uint32_t ui32Base, uint32_t ui32CS, + uint32_t ui32Config); +extern void EPIConfigHB16TimingSet(uint32_t ui32Base, uint32_t ui32CS, + uint32_t ui32Config); +extern void EPIPSRAMConfigRegSet(uint32_t ui32Base, uint32_t ui32CS, + uint32_t ui32CR); +extern void EPIPSRAMConfigRegRead(uint32_t ui32Base, uint32_t ui32CS); +extern bool EPIPSRAMConfigRegGetNonBlocking(uint32_t ui32Base, + uint32_t ui32CS, + uint32_t *pui32CR); +extern uint32_t EPIPSRAMConfigRegGet(uint32_t ui32Base, uint32_t ui32CS); +extern void EPIConfigSDRAMSet(uint32_t ui32Base, uint32_t ui32Config, + uint32_t ui32Refresh); +extern void EPIAddressMapSet(uint32_t ui32Base, uint32_t ui32Map); +extern void EPINonBlockingReadConfigure(uint32_t ui32Base, + uint32_t ui32Channel, + uint32_t ui32DataSize, + uint32_t ui32Address); +extern void EPINonBlockingReadStart(uint32_t ui32Base, + uint32_t ui32Channel, + uint32_t ui32Count); +extern void EPINonBlockingReadStop(uint32_t ui32Base, + uint32_t ui32Channel); +extern uint32_t EPINonBlockingReadCount(uint32_t ui32Base, + uint32_t ui32Channel); +extern uint32_t EPINonBlockingReadAvail(uint32_t ui32Base); +extern uint32_t EPINonBlockingReadGet32(uint32_t ui32Base, + uint32_t ui32Count, + uint32_t *pui32Buf); +extern uint32_t EPINonBlockingReadGet16(uint32_t ui32Base, + uint32_t ui32Count, + uint16_t *pui16Buf); +extern uint32_t EPINonBlockingReadGet8(uint32_t ui32Base, + uint32_t ui32Count, + uint8_t *pui8Buf); +extern void EPIFIFOConfig(uint32_t ui32Base, uint32_t ui32Config); +extern uint32_t EPIWriteFIFOCountGet(uint32_t ui32Base); +extern void EPIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void EPIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern uint32_t EPIIntStatus(uint32_t ui32Base, bool bMasked); +extern uint32_t EPIIntErrorStatus(uint32_t ui32Base); +extern void EPIIntErrorClear(uint32_t ui32Base, uint32_t ui32ErrFlags); +extern void EPIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); +extern void EPIIntUnregister(uint32_t ui32Base); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_EPI_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/flash.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/flash.h new file mode 100644 index 0000000000000000000000000000000000000000..0d20ab1c4822249475ac65fe54a8aa102651d1db --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/flash.h @@ -0,0 +1,122 @@ +//***************************************************************************** +// +// flash.h - Prototypes for the flash driver. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_FLASH_H__ +#define __DRIVERLIB_FLASH_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to FlashProtectSet(), and returned by +// FlashProtectGet(). +// +//***************************************************************************** +typedef enum +{ + FlashReadWrite, // Flash can be read and written + FlashReadOnly, // Flash can only be read + FlashExecuteOnly // Flash can only be executed +} +tFlashProtection; + +//***************************************************************************** +// +// Values passed to FlashIntEnable(), FlashIntDisable() and FlashIntClear() and +// returned from FlashIntStatus(). +// +//***************************************************************************** +#define FLASH_INT_PROGRAM 0x00000002 // Programming Interrupt Mask +#define FLASH_INT_ACCESS 0x00000001 // Access Interrupt Mask +#define FLASH_INT_EEPROM 0x00000004 // EEPROM Interrupt Mask +#define FLASH_INT_VOLTAGE_ERR 0x00000200 // Voltage Error Interrupt Mask +#define FLASH_INT_DATA_ERR 0x00000400 // Invalid Data Interrupt Mask +#define FLASH_INT_ERASE_ERR 0x00000800 // Erase Error Interrupt Mask +#define FLASH_INT_PROGRAM_ERR 0x00002000 // Program Verify Error Interrupt Mask + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern int32_t FlashErase(uint32_t ui32Address); +extern int32_t FlashProgram(uint32_t *pui32Data, uint32_t ui32Address, + uint32_t ui32Count); +extern tFlashProtection FlashProtectGet(uint32_t ui32Address); +extern int32_t FlashProtectSet(uint32_t ui32Address, + tFlashProtection eProtect); +extern int32_t FlashProtectSave(void); +extern int32_t FlashUserGet(uint32_t *pui32User0, uint32_t *pui32User1); +extern int32_t FlashUserSet(uint32_t ui32User0, uint32_t ui32User1); +extern int32_t FlashAllUserRegisterGet(uint32_t *pui32User0, + uint32_t *pui32User1, + uint32_t *pui32User2, + uint32_t *pui32User3); +extern int32_t FlashAllUserRegisterSet(uint32_t ui32User0, + uint32_t ui32User1, + uint32_t ui32User2, + uint32_t ui32User3); +extern int32_t FlashUserSave(void); +extern int32_t FlashAllUserRegisterSave(void); +extern void FlashIntRegister(void (*pfnHandler)(void)); +extern void FlashIntUnregister(void); +extern void FlashIntEnable(uint32_t ui32IntFlags); +extern void FlashIntDisable(uint32_t ui32IntFlags); +extern uint32_t FlashIntStatus(bool bMasked); +extern void FlashIntClear(uint32_t ui32IntFlags); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_FLASH_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/fpu.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/fpu.h new file mode 100644 index 0000000000000000000000000000000000000000..c96d69a7346c4a42762498f7a40cbdba60313f18 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/fpu.h @@ -0,0 +1,113 @@ +//***************************************************************************** +// +// fpu.h - Prototypes for the floatint point manipulation routines. +// +// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_FPU_H__ +#define __DRIVERLIB_FPU_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to FPUHalfPrecisionSet as the ui32Mode parameter. +// +//***************************************************************************** +#define FPU_HALF_IEEE 0x00000000 +#define FPU_HALF_ALTERNATE 0x04000000 + +//***************************************************************************** +// +// Values that can be passed to FPUNaNModeSet as the ui32Mode parameter. +// +//***************************************************************************** +#define FPU_NAN_PROPAGATE 0x00000000 +#define FPU_NAN_DEFAULT 0x02000000 + +//***************************************************************************** +// +// Values that can be passed to FPUFlushToZeroModeSet as the ui32Mode +// parameter. +// +//***************************************************************************** +#define FPU_FLUSH_TO_ZERO_DIS 0x00000000 +#define FPU_FLUSH_TO_ZERO_EN 0x01000000 + +//***************************************************************************** +// +// Values that can be passed to FPURoundingModeSet as the ui32Mode parameter. +// +//***************************************************************************** +#define FPU_ROUND_NEAREST 0x00000000 +#define FPU_ROUND_POS_INF 0x00400000 +#define FPU_ROUND_NEG_INF 0x00800000 +#define FPU_ROUND_ZERO 0x00c00000 + +//***************************************************************************** +// +// Prototypes. +// +//***************************************************************************** +extern void FPUEnable(void); +extern void FPUDisable(void); +extern void FPUStackingEnable(void); +extern void FPULazyStackingEnable(void); +extern void FPUStackingDisable(void); +extern void FPUHalfPrecisionModeSet(uint32_t ui32Mode); +extern void FPUNaNModeSet(uint32_t ui32Mode); +extern void FPUFlushToZeroModeSet(uint32_t ui32Mode); +extern void FPURoundingModeSet(uint32_t ui32Mode); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_FPU_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/gpio.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..47b0dd71b478835f794379db97eba341d911d68a --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/gpio.h @@ -0,0 +1,204 @@ +//***************************************************************************** +// +// gpio.h - Defines and Macros for GPIO API. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_GPIO_H__ +#define __DRIVERLIB_GPIO_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following values define the bit field for the ui8Pins argument to +// several of the APIs. +// +//***************************************************************************** +#define GPIO_PIN_0 0x00000001 // GPIO pin 0 +#define GPIO_PIN_1 0x00000002 // GPIO pin 1 +#define GPIO_PIN_2 0x00000004 // GPIO pin 2 +#define GPIO_PIN_3 0x00000008 // GPIO pin 3 +#define GPIO_PIN_4 0x00000010 // GPIO pin 4 +#define GPIO_PIN_5 0x00000020 // GPIO pin 5 +#define GPIO_PIN_6 0x00000040 // GPIO pin 6 +#define GPIO_PIN_7 0x00000080 // GPIO pin 7 + +//***************************************************************************** +// +// Values that can be passed to GPIODirModeSet as the ui32PinIO parameter, and +// returned from GPIODirModeGet. +// +//***************************************************************************** +#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input +#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output +#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function + +//***************************************************************************** +// +// Values that can be passed to GPIOIntTypeSet as the ui32IntType parameter, +// and returned from GPIOIntTypeGet. +// +//***************************************************************************** +#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge +#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge +#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges +#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level +#define GPIO_HIGH_LEVEL 0x00000006 // Interrupt on high level +#define GPIO_DISCRETE_INT 0x00010000 // Interrupt for individual pins + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ui32Strength parameter, +// and returned by GPIOPadConfigGet in the *pui32Strength parameter. +// +//***************************************************************************** +#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength +#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength +#define GPIO_STRENGTH_6MA 0x00000065 // 6mA drive strength +#define GPIO_STRENGTH_8MA 0x00000066 // 8mA drive strength +#define GPIO_STRENGTH_8MA_SC 0x0000006E // 8mA drive with slew rate control +#define GPIO_STRENGTH_10MA 0x00000075 // 10mA drive strength +#define GPIO_STRENGTH_12MA 0x00000077 // 12mA drive strength + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ui32PadType parameter, +// and returned by GPIOPadConfigGet in the *pui32PadType parameter. +// +//***************************************************************************** +#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull +#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up +#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down +#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain +#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator +#define GPIO_PIN_TYPE_WAKE_HIGH 0x00000208 // Hibernate wake, high +#define GPIO_PIN_TYPE_WAKE_LOW 0x00000108 // Hibernate wake, low + +//***************************************************************************** +// +// Values that can be passed to GPIOIntEnable() and GPIOIntDisable() functions +// in the ui32IntFlags parameter. +// +//***************************************************************************** +#define GPIO_INT_PIN_0 0x00000001 +#define GPIO_INT_PIN_1 0x00000002 +#define GPIO_INT_PIN_2 0x00000004 +#define GPIO_INT_PIN_3 0x00000008 +#define GPIO_INT_PIN_4 0x00000010 +#define GPIO_INT_PIN_5 0x00000020 +#define GPIO_INT_PIN_6 0x00000040 +#define GPIO_INT_PIN_7 0x00000080 +#define GPIO_INT_DMA 0x00000100 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void GPIODirModeSet(uint32_t ui32Port, uint8_t ui8Pins, + uint32_t ui32PinIO); +extern uint32_t GPIODirModeGet(uint32_t ui32Port, uint8_t ui8Pin); +extern void GPIOIntTypeSet(uint32_t ui32Port, uint8_t ui8Pins, + uint32_t ui32IntType); +extern uint32_t GPIOIntTypeGet(uint32_t ui32Port, uint8_t ui8Pin); +extern void GPIOPadConfigSet(uint32_t ui32Port, uint8_t ui8Pins, + uint32_t ui32Strength, uint32_t ui32PadType); +extern void GPIOPadConfigGet(uint32_t ui32Port, uint8_t ui8Pin, + uint32_t *pui32Strength, uint32_t *pui32PadType); +extern void GPIOIntEnable(uint32_t ui32Port, uint32_t ui32IntFlags); +extern void GPIOIntDisable(uint32_t ui32Port, uint32_t ui32IntFlags); +extern uint32_t GPIOIntStatus(uint32_t ui32Port, bool bMasked); +extern void GPIOIntClear(uint32_t ui32Port, uint32_t ui32IntFlags); +extern void GPIOIntRegister(uint32_t ui32Port, void (*pfnIntHandler)(void)); +extern void GPIOIntUnregister(uint32_t ui32Port); +extern void GPIOIntRegisterPin(uint32_t ui32Port, uint32_t ui32Pin, + void (*pfnIntHandler)(void)); +extern void GPIOIntUnregisterPin(uint32_t ui32Port, uint32_t ui32Pin); +extern int32_t GPIOPinRead(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinWrite(uint32_t ui32Port, uint8_t ui8Pins, uint8_t ui8Val); +extern void GPIOPinConfigure(uint32_t ui32PinConfig); +extern void GPIOPinTypeADC(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeCAN(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeComparator(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeComparatorOutput(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeDIVSCLK(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeEPI(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeEthernetLED(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeEthernetMII(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeGPIOInput(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeGPIOOutput(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeGPIOOutputOD(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeHibernateRTCCLK(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeI2C(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeI2CSCL(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeLCD(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeOneWire(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypePWM(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeQEI(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeSSI(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeTimer(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeTrace(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeUART(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeUSBAnalog(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeUSBDigital(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeWakeHigh(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeWakeLow(uint32_t ui32Port, uint8_t ui8Pins); +extern uint32_t GPIOPinWakeStatus(uint32_t ui32Port); +extern void GPIODMATriggerEnable(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIODMATriggerDisable(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOADCTriggerEnable(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOADCTriggerDisable(uint32_t ui32Port, uint8_t ui8Pins); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_GPIO_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/hibernate.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/hibernate.h new file mode 100644 index 0000000000000000000000000000000000000000..80633b950c143869d10a00c4610720bdf58230f7 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/hibernate.h @@ -0,0 +1,257 @@ +//***************************************************************************** +// +// hibernate.h - API definition for the Hibernation module. +// +// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_HIBERNATE_H__ +#define __DRIVERLIB_HIBERNATE_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Macros need to configure wake events for HibernateWakeSet() +// +//***************************************************************************** +#define HIBERNATE_WAKE_PIN 0x00000010 +#define HIBERNATE_WAKE_RTC 0x00000008 +#define HIBERNATE_WAKE_LOW_BAT 0x00000200 +#define HIBERNATE_WAKE_GPIO 0x00000010 +#define HIBERNATE_WAKE_RESET 0x00100010 +#define HIBERNATE_WAKE_TAMPER 0x08000010 + +//***************************************************************************** +// +// Macros needed to configure low battery detect for HibernateLowBatSet() +// +//***************************************************************************** +#define HIBERNATE_LOW_BAT_DETECT \ + 0x00000020 +#define HIBERNATE_LOW_BAT_ABORT 0x000000A0 +#define HIBERNATE_LOW_BAT_1_9V 0x00000000 +#define HIBERNATE_LOW_BAT_2_1V 0x00002000 +#define HIBERNATE_LOW_BAT_2_3V 0x00004000 +#define HIBERNATE_LOW_BAT_2_5V 0x00006000 + +//***************************************************************************** +// +// Macros defining interrupt source bits for the interrupt functions. +// +//***************************************************************************** +#define HIBERNATE_INT_VDDFAIL 0x00000080 +#define HIBERNATE_INT_RESET_WAKE \ + 0x00000040 +#define HIBERNATE_INT_GPIO_WAKE 0x00000020 +#define HIBERNATE_INT_WR_COMPLETE \ + 0x00000010 +#define HIBERNATE_INT_PIN_WAKE 0x00000008 +#define HIBERNATE_INT_LOW_BAT 0x00000004 +#define HIBERNATE_INT_RTC_MATCH_0 \ + 0x00000001 + +//***************************************************************************** +// +// Macros defining oscillator configuration options for the +// HibernateClockConfig() function. +// +//***************************************************************************** +#define HIBERNATE_OSC_LFIOSC 0x00080000 +#define HIBERNATE_OSC_LOWDRIVE 0x00000000 +#define HIBERNATE_OSC_HIGHDRIVE 0x00020000 +#define HIBERNATE_OSC_DISABLE 0x00010000 +#define HIBERNATE_OUT_WRSTALL 0x20000000 +#define HIBERNATE_OUT_SYSCLK 0x00000001 +#define HIBERNATE_OUT_ALT1CLK 0x00000002 + +//***************************************************************************** +// +// The following defines are used with the HibernateCounterMode() API. +// +//***************************************************************************** +#define HIBERNATE_COUNTER_RTC 0x00000000 +#define HIBERNATE_COUNTER_12HR 0x00000001 +#define HIBERNATE_COUNTER_24HR 0x00000005 + +//***************************************************************************** +// +// Tamper event configuration options used with HibernateTamperEventsConfig(). +// +//***************************************************************************** +#define HIBERNATE_TAMPER_EVENTS_NO_HIB_WAKE \ + 0x00000000 +#define HIBERNATE_TAMPER_EVENTS_HIB_WAKE \ + 0x00000800 +#define HIBERNATE_TAMPER_EVENTS_NO_ERASE_HIB_MEM \ + 0x00000000 +#define HIBERNATE_TAMPER_EVENTS_ERASE_LOW_HIB_MEM \ + 0x00000100 +#define HIBERNATE_TAMPER_EVENTS_ERASE_HIGH_HIB_MEM \ + 0x00000200 +#define HIBERNATE_TAMPER_EVENTS_ERASE_ALL_HIB_MEM \ + 0x00000300 + +//***************************************************************************** +// +// Status flags returned by the HibernateTamperStatus() function. +// +//***************************************************************************** +#define HIBERNATE_TAMPER_STATUS_INACTIVE \ + 0x00000010 +#define HIBERNATE_TAMPER_STATUS_ACTIVE \ + 0x00000020 +#define HIBERNATE_TAMPER_STATUS_EVENT \ + 0x00000040 +#define HIBERNATE_TAMPER_STATUS_EXT_OSC_ACTIVE \ + 0x00000008 +#define HIBERNATE_TAMPER_STATUS_EXT_OSC_INACTIVE \ + 0x00000002 +#define HIBERNATE_TAMPER_STATUS_EXT_OSC_VALID \ + 0x00000004 +#define HIBERNATE_TAMPER_STATUS_EXT_OSC_FAILED \ + 0x00000001 + +//***************************************************************************** +// +// Configuration options used with HibernateTamperIOEnable(). +// +//***************************************************************************** +#define HIBERNATE_TAMPER_IO_TRIGGER_LOW \ + 0x00000000 +#define HIBERNATE_TAMPER_IO_TRIGGER_HIGH \ + 0x00000002 +#define HIBERNATE_TAMPER_IO_WPU_DISABLED \ + 0x00000000 +#define HIBERNATE_TAMPER_IO_WPU_ENABLED \ + 0x00000004 +#define HIBERNATE_TAMPER_IO_MATCH_SHORT \ + 0x00000000 +#define HIBERNATE_TAMPER_IO_MATCH_LONG \ + 0x00000008 + +//***************************************************************************** +// +// Tamper log event flags. +// +//***************************************************************************** +#define HIBERNATE_TAMPER_EVENT_0 \ + 0x00000001 +#define HIBERNATE_TAMPER_EVENT_1 \ + 0x00000002 +#define HIBERNATE_TAMPER_EVENT_2 \ + 0x00000004 +#define HIBERNATE_TAMPER_EVENT_3 \ + 0x00000008 +#define HIBERNATE_TAMPER_EVENT_EXT_OSC \ + 0x00010000 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void HibernateGPIORetentionEnable(void); +extern void HibernateGPIORetentionDisable(void); +extern bool HibernateGPIORetentionGet(void); +extern void HibernateEnableExpClk(uint32_t ui32HibClk); +extern void HibernateDisable(void); +extern void HibernateRTCEnable(void); +extern void HibernateRTCDisable(void); +extern void HibernateWakeSet(uint32_t ui32WakeFlags); +extern uint32_t HibernateWakeGet(void); +extern void HibernateLowBatSet(uint32_t ui32LowBatFlags); +extern uint32_t HibernateLowBatGet(void); +extern void HibernateRTCSet(uint32_t ui32RTCValue); +extern uint32_t HibernateRTCGet(void); +extern void HibernateRTCMatchSet(uint32_t ui32Match, uint32_t ui32Value); +extern uint32_t HibernateRTCMatchGet(uint32_t ui32Match); +extern void HibernateRTCTrimSet(uint32_t ui32Trim); +extern uint32_t HibernateRTCTrimGet(void); +extern void HibernateDataSet(uint32_t *pui32Data, uint32_t ui32Count); +extern void HibernateDataGet(uint32_t *pui32Data, uint32_t ui32Count); +extern void HibernateRequest(void); +extern void HibernateIntEnable(uint32_t ui32IntFlags); +extern void HibernateIntDisable(uint32_t ui32IntFlags); +extern void HibernateIntRegister(void (*pfnHandler)(void)); +extern void HibernateIntUnregister(void); +extern uint32_t HibernateIntStatus(bool bMasked); +extern void HibernateIntClear(uint32_t ui32IntFlags); +extern uint32_t HibernateIsActive(void); +extern void HibernateRTCSSMatchSet(uint32_t ui32Match, uint32_t ui32Value); +extern uint32_t HibernateRTCSSMatchGet(uint32_t ui32Match); +extern uint32_t HibernateRTCSSGet(void); +extern void HibernateClockConfig(uint32_t ui32Config); +extern void HibernateBatCheckStart(void); +extern uint32_t HibernateBatCheckDone(void); +extern void HibernateCounterMode(uint32_t ui32Config); +extern void HibernateCalendarSet(struct tm *psTime); +extern int HibernateCalendarGet(struct tm *psTime); +extern void HibernateCalendarMatchSet(uint32_t ui32Index, struct tm *psTime); +extern void HibernateCalendarMatchGet(uint32_t ui32Index, struct tm *psTime); +extern void HibernateTamperEnable(void); +extern void HibernateTamperEventsConfig(uint32_t ui32Config); +extern bool HibernateTamperEventsGet(uint32_t ui32Index, uint32_t *pui32RTC, + uint32_t *pui32Event); +extern void HibernateTamperEventsClear(void); +extern void HibernateTamperEventsClearNoLock(void); +extern void HibernateTamperUnLock(void); +extern void HibernateTamperLock(void); +extern void HibernateTamperDisable(void); +extern void HibernateTamperIOEnable(uint32_t ui32Input, uint32_t ui32Config); +extern void HibernateTamperIODisable(uint32_t ui32Input); +extern uint32_t HibernateTamperStatusGet(void); +extern void HibernateTamperExtOscRecover(void); +extern bool HibernateTamperExtOscValid(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_HIBERNATE_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/i2c.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/i2c.h new file mode 100644 index 0000000000000000000000000000000000000000..ab7b44e4fe78a686e4b54d8c03dd53759c09fced --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/i2c.h @@ -0,0 +1,362 @@ +//***************************************************************************** +// +// i2c.h - Prototypes for the I2C Driver. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_I2C_H__ +#define __DRIVERLIB_I2C_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** + +//***************************************************************************** +// +// Interrupt defines. +// +//***************************************************************************** +#define I2C_INT_MASTER 0x00000001 +#define I2C_INT_SLAVE 0x00000002 + +//***************************************************************************** +// +// I2C Master commands. +// +//***************************************************************************** +#define I2C_MASTER_CMD_SINGLE_SEND \ + 0x00000007 +#define I2C_MASTER_CMD_SINGLE_RECEIVE \ + 0x00000007 +#define I2C_MASTER_CMD_BURST_SEND_START \ + 0x00000003 +#define I2C_MASTER_CMD_BURST_SEND_CONT \ + 0x00000001 +#define I2C_MASTER_CMD_BURST_SEND_FINISH \ + 0x00000005 +#define I2C_MASTER_CMD_BURST_SEND_STOP \ + 0x00000004 +#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ + 0x00000004 +#define I2C_MASTER_CMD_BURST_RECEIVE_START \ + 0x0000000b +#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ + 0x00000009 +#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ + 0x00000005 +#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ + 0x00000004 +#define I2C_MASTER_CMD_QUICK_COMMAND \ + 0x00000027 +#define I2C_MASTER_CMD_HS_MASTER_CODE_SEND \ + 0x00000013 +#define I2C_MASTER_CMD_FIFO_SINGLE_SEND \ + 0x00000046 +#define I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE \ + 0x00000046 +#define I2C_MASTER_CMD_FIFO_BURST_SEND_START \ + 0x00000042 +#define I2C_MASTER_CMD_FIFO_BURST_SEND_CONT \ + 0x00000040 +#define I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH \ + 0x00000044 +#define I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP \ + 0x00000004 +#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START \ + 0x0000004a +#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT \ + 0x00000048 +#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH \ + 0x00000044 +#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP \ + 0x00000004 + +//***************************************************************************** +// +// I2C Master glitch filter configuration. +// +//***************************************************************************** +#define I2C_MASTER_GLITCH_FILTER_DISABLED \ + 0 +#define I2C_MASTER_GLITCH_FILTER_1 \ + 0x00010000 +#define I2C_MASTER_GLITCH_FILTER_2 \ + 0x00020000 +#define I2C_MASTER_GLITCH_FILTER_3 \ + 0x00030000 +#define I2C_MASTER_GLITCH_FILTER_4 \ + 0x00040000 +#define I2C_MASTER_GLITCH_FILTER_8 \ + 0x00050000 +#define I2C_MASTER_GLITCH_FILTER_16 \ + 0x00060000 +#define I2C_MASTER_GLITCH_FILTER_32 \ + 0x00070000 + +//***************************************************************************** +// +// I2C Master error status. +// +//***************************************************************************** +#define I2C_MASTER_ERR_NONE 0 +#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 +#define I2C_MASTER_ERR_DATA_ACK 0x00000008 +#define I2C_MASTER_ERR_ARB_LOST 0x00000010 +#define I2C_MASTER_ERR_CLK_TOUT 0x00000080 + +//***************************************************************************** +// +// I2C Slave action requests +// +//***************************************************************************** +#define I2C_SLAVE_ACT_NONE 0 +#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data +#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data +#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte +#define I2C_SLAVE_ACT_OWN2SEL 0x00000008 // Master requested secondary slave +#define I2C_SLAVE_ACT_QCMD 0x00000010 // Master has sent a Quick Command +#define I2C_SLAVE_ACT_QCMD_DATA 0x00000020 // Master Quick Command value + +//***************************************************************************** +// +// Miscellaneous I2C driver definitions. +// +//***************************************************************************** +#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries + +//***************************************************************************** +// +// I2C Master interrupts. +// +//***************************************************************************** +#define I2C_MASTER_INT_RX_FIFO_FULL \ + 0x00000800 // RX FIFO Full Interrupt +#define I2C_MASTER_INT_TX_FIFO_EMPTY \ + 0x00000400 // TX FIFO Empty Interrupt +#define I2C_MASTER_INT_RX_FIFO_REQ \ + 0x00000200 // RX FIFO Request Interrupt +#define I2C_MASTER_INT_TX_FIFO_REQ \ + 0x00000100 // TX FIFO Request Interrupt +#define I2C_MASTER_INT_ARB_LOST \ + 0x00000080 // Arb Lost Interrupt +#define I2C_MASTER_INT_STOP 0x00000040 // Stop Condition Interrupt +#define I2C_MASTER_INT_START 0x00000020 // Start Condition Interrupt +#define I2C_MASTER_INT_NACK 0x00000010 // Addr/Data NACK Interrupt +#define I2C_MASTER_INT_TX_DMA_DONE \ + 0x00000008 // TX DMA Complete Interrupt +#define I2C_MASTER_INT_RX_DMA_DONE \ + 0x00000004 // RX DMA Complete Interrupt +#define I2C_MASTER_INT_TIMEOUT 0x00000002 // Clock Timeout Interrupt +#define I2C_MASTER_INT_DATA 0x00000001 // Data Interrupt + +//***************************************************************************** +// +// I2C Slave interrupts. +// +//***************************************************************************** +#define I2C_SLAVE_INT_RX_FIFO_FULL \ + 0x00000100 // RX FIFO Full Interrupt +#define I2C_SLAVE_INT_TX_FIFO_EMPTY \ + 0x00000080 // TX FIFO Empty Interrupt +#define I2C_SLAVE_INT_RX_FIFO_REQ \ + 0x00000040 // RX FIFO Request Interrupt +#define I2C_SLAVE_INT_TX_FIFO_REQ \ + 0x00000020 // TX FIFO Request Interrupt +#define I2C_SLAVE_INT_TX_DMA_DONE \ + 0x00000010 // TX DMA Complete Interrupt +#define I2C_SLAVE_INT_RX_DMA_DONE \ + 0x00000008 // RX DMA Complete Interrupt +#define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt +#define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt +#define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt + +//***************************************************************************** +// +// I2C Slave FIFO configuration macros. +// +//***************************************************************************** +#define I2C_SLAVE_TX_FIFO_ENABLE \ + 0x00000002 +#define I2C_SLAVE_RX_FIFO_ENABLE \ + 0x00000004 + +//***************************************************************************** +// +// I2C FIFO configuration macros. +// +//***************************************************************************** +#define I2C_FIFO_CFG_TX_MASTER 0x00000000 +#define I2C_FIFO_CFG_TX_SLAVE 0x00008000 +#define I2C_FIFO_CFG_RX_MASTER 0x00000000 +#define I2C_FIFO_CFG_RX_SLAVE 0x80000000 +#define I2C_FIFO_CFG_TX_MASTER_DMA \ + 0x00002000 +#define I2C_FIFO_CFG_TX_SLAVE_DMA \ + 0x0000a000 +#define I2C_FIFO_CFG_RX_MASTER_DMA \ + 0x20000000 +#define I2C_FIFO_CFG_RX_SLAVE_DMA \ + 0xa0000000 +#define I2C_FIFO_CFG_TX_NO_TRIG 0x00000000 +#define I2C_FIFO_CFG_TX_TRIG_1 0x00000001 +#define I2C_FIFO_CFG_TX_TRIG_2 0x00000002 +#define I2C_FIFO_CFG_TX_TRIG_3 0x00000003 +#define I2C_FIFO_CFG_TX_TRIG_4 0x00000004 +#define I2C_FIFO_CFG_TX_TRIG_5 0x00000005 +#define I2C_FIFO_CFG_TX_TRIG_6 0x00000006 +#define I2C_FIFO_CFG_TX_TRIG_7 0x00000007 +#define I2C_FIFO_CFG_TX_TRIG_8 0x00000008 +#define I2C_FIFO_CFG_RX_NO_TRIG 0x00000000 +#define I2C_FIFO_CFG_RX_TRIG_1 0x00010000 +#define I2C_FIFO_CFG_RX_TRIG_2 0x00020000 +#define I2C_FIFO_CFG_RX_TRIG_3 0x00030000 +#define I2C_FIFO_CFG_RX_TRIG_4 0x00040000 +#define I2C_FIFO_CFG_RX_TRIG_5 0x00050000 +#define I2C_FIFO_CFG_RX_TRIG_6 0x00060000 +#define I2C_FIFO_CFG_RX_TRIG_7 0x00070000 +#define I2C_FIFO_CFG_RX_TRIG_8 0x00080000 + +//***************************************************************************** +// +// I2C FIFO status. +// +//***************************************************************************** +#define I2C_FIFO_RX_BELOW_TRIG_LEVEL \ + 0x00040000 +#define I2C_FIFO_RX_FULL 0x00020000 +#define I2C_FIFO_RX_EMPTY 0x00010000 +#define I2C_FIFO_TX_BELOW_TRIG_LEVEL \ + 0x00000004 +#define I2C_FIFO_TX_FULL 0x00000002 +#define I2C_FIFO_TX_EMPTY 0x00000001 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void I2CIntRegister(uint32_t ui32Base, void(*pfnHandler)(void)); +extern void I2CIntUnregister(uint32_t ui32Base); +extern void I2CTxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config); +extern void I2CTxFIFOFlush(uint32_t ui32Base); +extern void I2CRxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config); +extern void I2CRxFIFOFlush(uint32_t ui32Base); +extern uint32_t I2CFIFOStatus(uint32_t ui32Base); +extern void I2CFIFODataPut(uint32_t ui32Base, uint8_t ui8Data); +extern uint32_t I2CFIFODataPutNonBlocking(uint32_t ui32Base, + uint8_t ui8Data); +extern uint32_t I2CFIFODataGet(uint32_t ui32Base); +extern uint32_t I2CFIFODataGetNonBlocking(uint32_t ui32Base, + uint8_t *pui8Data); +extern void I2CMasterBurstLengthSet(uint32_t ui32Base, + uint8_t ui8Length); +extern uint32_t I2CMasterBurstCountGet(uint32_t ui32Base); +extern void I2CMasterGlitchFilterConfigSet(uint32_t ui32Base, + uint32_t ui32Config); +extern void I2CSlaveFIFOEnable(uint32_t ui32Base, uint32_t ui32Config); +extern void I2CSlaveFIFODisable(uint32_t ui32Base); +extern bool I2CMasterBusBusy(uint32_t ui32Base); +extern bool I2CMasterBusy(uint32_t ui32Base); +extern void I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd); +extern uint32_t I2CMasterDataGet(uint32_t ui32Base); +extern void I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data); +extern void I2CMasterDisable(uint32_t ui32Base); +extern void I2CMasterEnable(uint32_t ui32Base); +extern uint32_t I2CMasterErr(uint32_t ui32Base); +extern void I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk, + bool bFast); +extern void I2CMasterIntClear(uint32_t ui32Base); +extern void I2CMasterIntDisable(uint32_t ui32Base); +extern void I2CMasterIntEnable(uint32_t ui32Base); +extern bool I2CMasterIntStatus(uint32_t ui32Base, bool bMasked); +extern void I2CMasterIntEnableEx(uint32_t ui32Base, + uint32_t ui32IntFlags); +extern void I2CMasterIntDisableEx(uint32_t ui32Base, + uint32_t ui32IntFlags); +extern uint32_t I2CMasterIntStatusEx(uint32_t ui32Base, + bool bMasked); +extern void I2CMasterIntClearEx(uint32_t ui32Base, + uint32_t ui32IntFlags); +extern void I2CMasterTimeoutSet(uint32_t ui32Base, uint32_t ui32Value); +extern void I2CSlaveACKOverride(uint32_t ui32Base, bool bEnable); +extern void I2CSlaveACKValueSet(uint32_t ui32Base, bool bACK); +extern uint32_t I2CMasterLineStateGet(uint32_t ui32Base); +extern void I2CMasterSlaveAddrSet(uint32_t ui32Base, + uint8_t ui8SlaveAddr, + bool bReceive); +extern uint32_t I2CSlaveDataGet(uint32_t ui32Base); +extern void I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data); +extern void I2CSlaveDisable(uint32_t ui32Base); +extern void I2CSlaveEnable(uint32_t ui32Base); +extern void I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr); +extern void I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8AddrNum, + uint8_t ui8SlaveAddr); +extern void I2CSlaveIntClear(uint32_t ui32Base); +extern void I2CSlaveIntDisable(uint32_t ui32Base); +extern void I2CSlaveIntEnable(uint32_t ui32Base); +extern void I2CSlaveIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void I2CSlaveIntDisableEx(uint32_t ui32Base, + uint32_t ui32IntFlags); +extern void I2CSlaveIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags); +extern bool I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked); +extern uint32_t I2CSlaveIntStatusEx(uint32_t ui32Base, + bool bMasked); +extern uint32_t I2CSlaveStatus(uint32_t ui32Base); +extern void I2CLoopbackEnable(uint32_t ui32Base); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_I2C_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/asmdefs.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/asmdefs.h new file mode 100644 index 0000000000000000000000000000000000000000..b0e4cc217ca36d33d776c12d627c159f73920917 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/asmdefs.h @@ -0,0 +1,227 @@ +//***************************************************************************** +// +// asmdefs.h - Macros to allow assembly code be portable among toolchains. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __ASMDEFS_H__ +#define __ASMDEFS_H__ + +//***************************************************************************** +// +// The defines required for code_red. +// +//***************************************************************************** +#ifdef codered + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + .syntax unified + .thumb + +// +// Section headers. +// +#define __LIBRARY__ @ +#define __TEXT__ .text +#define __DATA__ .data +#define __BSS__ .bss +#define __TEXT_NOROOT__ .text + +// +// Assembler nmenonics. +// +#define __ALIGN__ .balign 4 +#define __END__ .end +#define __EXPORT__ .globl +#define __IMPORT__ .extern +#define __LABEL__ : +#define __STR__ .ascii +#define __THUMB_LABEL__ .thumb_func +#define __WORD__ .word +#define __INLINE_DATA__ + +#endif // codered + +//***************************************************************************** +// +// The defines required for EW-ARM. +// +//***************************************************************************** +#ifdef ewarm + +// +// Section headers. +// +#define __LIBRARY__ module +#define __TEXT__ rseg CODE:CODE(2) +#define __DATA__ rseg DATA:DATA(2) +#define __BSS__ rseg DATA:DATA(2) +#define __TEXT_NOROOT__ rseg CODE:CODE:NOROOT(2) + +// +// Assembler nmenonics. +// +#define __ALIGN__ alignrom 2 +#define __END__ end +#define __EXPORT__ export +#define __IMPORT__ import +#define __LABEL__ +#define __STR__ dcb +#define __THUMB_LABEL__ thumb +#define __WORD__ dcd +#define __INLINE_DATA__ data + +#endif // ewarm + +//***************************************************************************** +// +// The defines required for GCC. +// +//***************************************************************************** +#if defined(gcc) + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + .syntax unified + .thumb + +// +// Section headers. +// +#define __LIBRARY__ @ +#define __TEXT__ .text +#define __DATA__ .data +#define __BSS__ .bss +#define __TEXT_NOROOT__ .text + +// +// Assembler nmenonics. +// +#define __ALIGN__ .balign 4 +#define __END__ .end +#define __EXPORT__ .globl +#define __IMPORT__ .extern +#define __LABEL__ : +#define __STR__ .ascii +#define __THUMB_LABEL__ .thumb_func +#define __WORD__ .word +#define __INLINE_DATA__ + +#endif // gcc + +//***************************************************************************** +// +// The defines required for RV-MDK. +// +//***************************************************************************** +#ifdef rvmdk + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + thumb + require8 + preserve8 + +// +// Section headers. +// +#define __LIBRARY__ ; +#define __TEXT__ area ||.text||, code, readonly, align=2 +#define __DATA__ area ||.data||, data, align=2 +#define __BSS__ area ||.bss||, noinit, align=2 +#define __TEXT_NOROOT__ area ||.text||, code, readonly, align=2 + +// +// Assembler nmenonics. +// +#define __ALIGN__ align 4 +#define __END__ end +#define __EXPORT__ export +#define __IMPORT__ import +#define __LABEL__ +#define __STR__ dcb +#define __THUMB_LABEL__ +#define __WORD__ dcd +#define __INLINE_DATA__ + +#endif // rvmdk + +//***************************************************************************** +// +// The defines required for Sourcery G++. +// +//***************************************************************************** +#if defined(sourcerygxx) + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + .syntax unified + .thumb + +// +// Section headers. +// +#define __LIBRARY__ @ +#define __TEXT__ .text +#define __DATA__ .data +#define __BSS__ .bss +#define __TEXT_NOROOT__ .text + +// +// Assembler nmenonics. +// +#define __ALIGN__ .balign 4 +#define __END__ .end +#define __EXPORT__ .globl +#define __IMPORT__ .extern +#define __LABEL__ : +#define __STR__ .ascii +#define __THUMB_LABEL__ .thumb_func +#define __WORD__ .word +#define __INLINE_DATA__ + +#endif // sourcerygxx + +#endif // __ASMDEF_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_adc.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_adc.h new file mode 100644 index 0000000000000000000000000000000000000000..41f8a33e4df5434f5b442412631fe04723dd74f1 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_adc.h @@ -0,0 +1,1306 @@ +//***************************************************************************** +// +// hw_adc.h - Macros used when accessing the ADC hardware. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_ADC_H__ +#define __HW_ADC_H__ + +//***************************************************************************** +// +// The following are defines for the ADC register offsets. +// +//***************************************************************************** +#define ADC_O_ACTSS 0x00000000 // ADC Active Sample Sequencer +#define ADC_O_RIS 0x00000004 // ADC Raw Interrupt Status +#define ADC_O_IM 0x00000008 // ADC Interrupt Mask +#define ADC_O_ISC 0x0000000C // ADC Interrupt Status and Clear +#define ADC_O_OSTAT 0x00000010 // ADC Overflow Status +#define ADC_O_EMUX 0x00000014 // ADC Event Multiplexer Select +#define ADC_O_USTAT 0x00000018 // ADC Underflow Status +#define ADC_O_TSSEL 0x0000001C // ADC Trigger Source Select +#define ADC_O_SSPRI 0x00000020 // ADC Sample Sequencer Priority +#define ADC_O_SPC 0x00000024 // ADC Sample Phase Control +#define ADC_O_PSSI 0x00000028 // ADC Processor Sample Sequence + // Initiate +#define ADC_O_SAC 0x00000030 // ADC Sample Averaging Control +#define ADC_O_DCISC 0x00000034 // ADC Digital Comparator Interrupt + // Status and Clear +#define ADC_O_CTL 0x00000038 // ADC Control +#define ADC_O_SSMUX0 0x00000040 // ADC Sample Sequence Input + // Multiplexer Select 0 +#define ADC_O_SSCTL0 0x00000044 // ADC Sample Sequence Control 0 +#define ADC_O_SSFIFO0 0x00000048 // ADC Sample Sequence Result FIFO + // 0 +#define ADC_O_SSFSTAT0 0x0000004C // ADC Sample Sequence FIFO 0 + // Status +#define ADC_O_SSOP0 0x00000050 // ADC Sample Sequence 0 Operation +#define ADC_O_SSDC0 0x00000054 // ADC Sample Sequence 0 Digital + // Comparator Select +#define ADC_O_SSEMUX0 0x00000058 // ADC Sample Sequence Extended + // Input Multiplexer Select 0 +#define ADC_O_SSTSH0 0x0000005C // ADC Sample Sequence 0 Sample and + // Hold Time +#define ADC_O_SSMUX1 0x00000060 // ADC Sample Sequence Input + // Multiplexer Select 1 +#define ADC_O_SSCTL1 0x00000064 // ADC Sample Sequence Control 1 +#define ADC_O_SSFIFO1 0x00000068 // ADC Sample Sequence Result FIFO + // 1 +#define ADC_O_SSFSTAT1 0x0000006C // ADC Sample Sequence FIFO 1 + // Status +#define ADC_O_SSOP1 0x00000070 // ADC Sample Sequence 1 Operation +#define ADC_O_SSDC1 0x00000074 // ADC Sample Sequence 1 Digital + // Comparator Select +#define ADC_O_SSEMUX1 0x00000078 // ADC Sample Sequence Extended + // Input Multiplexer Select 1 +#define ADC_O_SSTSH1 0x0000007C // ADC Sample Sequence 1 Sample and + // Hold Time +#define ADC_O_SSMUX2 0x00000080 // ADC Sample Sequence Input + // Multiplexer Select 2 +#define ADC_O_SSCTL2 0x00000084 // ADC Sample Sequence Control 2 +#define ADC_O_SSFIFO2 0x00000088 // ADC Sample Sequence Result FIFO + // 2 +#define ADC_O_SSFSTAT2 0x0000008C // ADC Sample Sequence FIFO 2 + // Status +#define ADC_O_SSOP2 0x00000090 // ADC Sample Sequence 2 Operation +#define ADC_O_SSDC2 0x00000094 // ADC Sample Sequence 2 Digital + // Comparator Select +#define ADC_O_SSEMUX2 0x00000098 // ADC Sample Sequence Extended + // Input Multiplexer Select 2 +#define ADC_O_SSTSH2 0x0000009C // ADC Sample Sequence 2 Sample and + // Hold Time +#define ADC_O_SSMUX3 0x000000A0 // ADC Sample Sequence Input + // Multiplexer Select 3 +#define ADC_O_SSCTL3 0x000000A4 // ADC Sample Sequence Control 3 +#define ADC_O_SSFIFO3 0x000000A8 // ADC Sample Sequence Result FIFO + // 3 +#define ADC_O_SSFSTAT3 0x000000AC // ADC Sample Sequence FIFO 3 + // Status +#define ADC_O_SSOP3 0x000000B0 // ADC Sample Sequence 3 Operation +#define ADC_O_SSDC3 0x000000B4 // ADC Sample Sequence 3 Digital + // Comparator Select +#define ADC_O_SSEMUX3 0x000000B8 // ADC Sample Sequence Extended + // Input Multiplexer Select 3 +#define ADC_O_SSTSH3 0x000000BC // ADC Sample Sequence 3 Sample and + // Hold Time +#define ADC_O_DCRIC 0x00000D00 // ADC Digital Comparator Reset + // Initial Conditions +#define ADC_O_DCCTL0 0x00000E00 // ADC Digital Comparator Control 0 +#define ADC_O_DCCTL1 0x00000E04 // ADC Digital Comparator Control 1 +#define ADC_O_DCCTL2 0x00000E08 // ADC Digital Comparator Control 2 +#define ADC_O_DCCTL3 0x00000E0C // ADC Digital Comparator Control 3 +#define ADC_O_DCCTL4 0x00000E10 // ADC Digital Comparator Control 4 +#define ADC_O_DCCTL5 0x00000E14 // ADC Digital Comparator Control 5 +#define ADC_O_DCCTL6 0x00000E18 // ADC Digital Comparator Control 6 +#define ADC_O_DCCTL7 0x00000E1C // ADC Digital Comparator Control 7 +#define ADC_O_DCCMP0 0x00000E40 // ADC Digital Comparator Range 0 +#define ADC_O_DCCMP1 0x00000E44 // ADC Digital Comparator Range 1 +#define ADC_O_DCCMP2 0x00000E48 // ADC Digital Comparator Range 2 +#define ADC_O_DCCMP3 0x00000E4C // ADC Digital Comparator Range 3 +#define ADC_O_DCCMP4 0x00000E50 // ADC Digital Comparator Range 4 +#define ADC_O_DCCMP5 0x00000E54 // ADC Digital Comparator Range 5 +#define ADC_O_DCCMP6 0x00000E58 // ADC Digital Comparator Range 6 +#define ADC_O_DCCMP7 0x00000E5C // ADC Digital Comparator Range 7 +#define ADC_O_PP 0x00000FC0 // ADC Peripheral Properties +#define ADC_O_PC 0x00000FC4 // ADC Peripheral Configuration +#define ADC_O_CC 0x00000FC8 // ADC Clock Configuration + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_ACTSS register. +// +//***************************************************************************** +#define ADC_ACTSS_BUSY 0x00010000 // ADC Busy +#define ADC_ACTSS_ADEN3 0x00000800 // ADC SS3 DMA Enable +#define ADC_ACTSS_ADEN2 0x00000400 // ADC SS2 DMA Enable +#define ADC_ACTSS_ADEN1 0x00000200 // ADC SS1 DMA Enable +#define ADC_ACTSS_ADEN0 0x00000100 // ADC SS1 DMA Enable +#define ADC_ACTSS_ASEN3 0x00000008 // ADC SS3 Enable +#define ADC_ACTSS_ASEN2 0x00000004 // ADC SS2 Enable +#define ADC_ACTSS_ASEN1 0x00000002 // ADC SS1 Enable +#define ADC_ACTSS_ASEN0 0x00000001 // ADC SS0 Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_RIS register. +// +//***************************************************************************** +#define ADC_RIS_INRDC 0x00010000 // Digital Comparator Raw Interrupt + // Status +#define ADC_RIS_DMAINR3 0x00000800 // SS3 DMA Raw Interrupt Status +#define ADC_RIS_DMAINR2 0x00000400 // SS2 DMA Raw Interrupt Status +#define ADC_RIS_DMAINR1 0x00000200 // SS1 DMA Raw Interrupt Status +#define ADC_RIS_DMAINR0 0x00000100 // SS0 DMA Raw Interrupt Status +#define ADC_RIS_INR3 0x00000008 // SS3 Raw Interrupt Status +#define ADC_RIS_INR2 0x00000004 // SS2 Raw Interrupt Status +#define ADC_RIS_INR1 0x00000002 // SS1 Raw Interrupt Status +#define ADC_RIS_INR0 0x00000001 // SS0 Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_IM register. +// +//***************************************************************************** +#define ADC_IM_DCONSS3 0x00080000 // Digital Comparator Interrupt on + // SS3 +#define ADC_IM_DCONSS2 0x00040000 // Digital Comparator Interrupt on + // SS2 +#define ADC_IM_DCONSS1 0x00020000 // Digital Comparator Interrupt on + // SS1 +#define ADC_IM_DCONSS0 0x00010000 // Digital Comparator Interrupt on + // SS0 +#define ADC_IM_DMAMASK3 0x00000800 // SS3 DMA Interrupt Mask +#define ADC_IM_DMAMASK2 0x00000400 // SS2 DMA Interrupt Mask +#define ADC_IM_DMAMASK1 0x00000200 // SS1 DMA Interrupt Mask +#define ADC_IM_DMAMASK0 0x00000100 // SS0 DMA Interrupt Mask +#define ADC_IM_MASK3 0x00000008 // SS3 Interrupt Mask +#define ADC_IM_MASK2 0x00000004 // SS2 Interrupt Mask +#define ADC_IM_MASK1 0x00000002 // SS1 Interrupt Mask +#define ADC_IM_MASK0 0x00000001 // SS0 Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_ISC register. +// +//***************************************************************************** +#define ADC_ISC_DCINSS3 0x00080000 // Digital Comparator Interrupt + // Status on SS3 +#define ADC_ISC_DCINSS2 0x00040000 // Digital Comparator Interrupt + // Status on SS2 +#define ADC_ISC_DCINSS1 0x00020000 // Digital Comparator Interrupt + // Status on SS1 +#define ADC_ISC_DCINSS0 0x00010000 // Digital Comparator Interrupt + // Status on SS0 +#define ADC_ISC_DMAIN3 0x00000800 // SS3 DMA Interrupt Status and + // Clear +#define ADC_ISC_DMAIN2 0x00000400 // SS2 DMA Interrupt Status and + // Clear +#define ADC_ISC_DMAIN1 0x00000200 // SS1 DMA Interrupt Status and + // Clear +#define ADC_ISC_DMAIN0 0x00000100 // SS0 DMA Interrupt Status and + // Clear +#define ADC_ISC_IN3 0x00000008 // SS3 Interrupt Status and Clear +#define ADC_ISC_IN2 0x00000004 // SS2 Interrupt Status and Clear +#define ADC_ISC_IN1 0x00000002 // SS1 Interrupt Status and Clear +#define ADC_ISC_IN0 0x00000001 // SS0 Interrupt Status and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_OSTAT register. +// +//***************************************************************************** +#define ADC_OSTAT_OV3 0x00000008 // SS3 FIFO Overflow +#define ADC_OSTAT_OV2 0x00000004 // SS2 FIFO Overflow +#define ADC_OSTAT_OV1 0x00000002 // SS1 FIFO Overflow +#define ADC_OSTAT_OV0 0x00000001 // SS0 FIFO Overflow + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_EMUX register. +// +//***************************************************************************** +#define ADC_EMUX_EM3_M 0x0000F000 // SS3 Trigger Select +#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor (default) +#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog Comparator 0 +#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog Comparator 1 +#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog Comparator 2 +#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External (GPIO Pins) +#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer +#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM generator 0 +#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM generator 1 +#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM generator 2 +#define ADC_EMUX_EM3_PWM3 0x00009000 // PWM generator 3 +#define ADC_EMUX_EM3_NEVER 0x0000E000 // Never Trigger +#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always (continuously sample) +#define ADC_EMUX_EM2_M 0x00000F00 // SS2 Trigger Select +#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor (default) +#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog Comparator 0 +#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog Comparator 1 +#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog Comparator 2 +#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External (GPIO Pins) +#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer +#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM generator 0 +#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM generator 1 +#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM generator 2 +#define ADC_EMUX_EM2_PWM3 0x00000900 // PWM generator 3 +#define ADC_EMUX_EM2_NEVER 0x00000E00 // Never Trigger +#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always (continuously sample) +#define ADC_EMUX_EM1_M 0x000000F0 // SS1 Trigger Select +#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor (default) +#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog Comparator 0 +#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog Comparator 1 +#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog Comparator 2 +#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External (GPIO Pins) +#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer +#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM generator 0 +#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM generator 1 +#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM generator 2 +#define ADC_EMUX_EM1_PWM3 0x00000090 // PWM generator 3 +#define ADC_EMUX_EM1_NEVER 0x000000E0 // Never Trigger +#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always (continuously sample) +#define ADC_EMUX_EM0_M 0x0000000F // SS0 Trigger Select +#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor (default) +#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog Comparator 0 +#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog Comparator 1 +#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog Comparator 2 +#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External (GPIO Pins) +#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer +#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM generator 0 +#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM generator 1 +#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM generator 2 +#define ADC_EMUX_EM0_PWM3 0x00000009 // PWM generator 3 +#define ADC_EMUX_EM0_NEVER 0x0000000E // Never Trigger +#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always (continuously sample) + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_USTAT register. +// +//***************************************************************************** +#define ADC_USTAT_UV3 0x00000008 // SS3 FIFO Underflow +#define ADC_USTAT_UV2 0x00000004 // SS2 FIFO Underflow +#define ADC_USTAT_UV1 0x00000002 // SS1 FIFO Underflow +#define ADC_USTAT_UV0 0x00000001 // SS0 FIFO Underflow + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_TSSEL register. +// +//***************************************************************************** +#define ADC_TSSEL_PS3_M 0x30000000 // Generator 3 PWM Module Trigger + // Select +#define ADC_TSSEL_PS3_0 0x00000000 // Use Generator 3 (and its + // trigger) in PWM module 0 +#define ADC_TSSEL_PS3_1 0x10000000 // Use Generator 3 (and its + // trigger) in PWM module 1 +#define ADC_TSSEL_PS2_M 0x00300000 // Generator 2 PWM Module Trigger + // Select +#define ADC_TSSEL_PS2_0 0x00000000 // Use Generator 2 (and its + // trigger) in PWM module 0 +#define ADC_TSSEL_PS2_1 0x00100000 // Use Generator 2 (and its + // trigger) in PWM module 1 +#define ADC_TSSEL_PS1_M 0x00003000 // Generator 1 PWM Module Trigger + // Select +#define ADC_TSSEL_PS1_0 0x00000000 // Use Generator 1 (and its + // trigger) in PWM module 0 +#define ADC_TSSEL_PS1_1 0x00001000 // Use Generator 1 (and its + // trigger) in PWM module 1 +#define ADC_TSSEL_PS0_M 0x00000030 // Generator 0 PWM Module Trigger + // Select +#define ADC_TSSEL_PS0_0 0x00000000 // Use Generator 0 (and its + // trigger) in PWM module 0 +#define ADC_TSSEL_PS0_1 0x00000010 // Use Generator 0 (and its + // trigger) in PWM module 1 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSPRI register. +// +//***************************************************************************** +#define ADC_SSPRI_SS3_M 0x00003000 // SS3 Priority +#define ADC_SSPRI_SS2_M 0x00000300 // SS2 Priority +#define ADC_SSPRI_SS1_M 0x00000030 // SS1 Priority +#define ADC_SSPRI_SS0_M 0x00000003 // SS0 Priority + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SPC register. +// +//***************************************************************************** +#define ADC_SPC_PHASE_M 0x0000000F // Phase Difference +#define ADC_SPC_PHASE_0 0x00000000 // ADC sample lags by 0.0 +#define ADC_SPC_PHASE_22_5 0x00000001 // ADC sample lags by 22.5 +#define ADC_SPC_PHASE_45 0x00000002 // ADC sample lags by 45.0 +#define ADC_SPC_PHASE_67_5 0x00000003 // ADC sample lags by 67.5 +#define ADC_SPC_PHASE_90 0x00000004 // ADC sample lags by 90.0 +#define ADC_SPC_PHASE_112_5 0x00000005 // ADC sample lags by 112.5 +#define ADC_SPC_PHASE_135 0x00000006 // ADC sample lags by 135.0 +#define ADC_SPC_PHASE_157_5 0x00000007 // ADC sample lags by 157.5 +#define ADC_SPC_PHASE_180 0x00000008 // ADC sample lags by 180.0 +#define ADC_SPC_PHASE_202_5 0x00000009 // ADC sample lags by 202.5 +#define ADC_SPC_PHASE_225 0x0000000A // ADC sample lags by 225.0 +#define ADC_SPC_PHASE_247_5 0x0000000B // ADC sample lags by 247.5 +#define ADC_SPC_PHASE_270 0x0000000C // ADC sample lags by 270.0 +#define ADC_SPC_PHASE_292_5 0x0000000D // ADC sample lags by 292.5 +#define ADC_SPC_PHASE_315 0x0000000E // ADC sample lags by 315.0 +#define ADC_SPC_PHASE_337_5 0x0000000F // ADC sample lags by 337.5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_PSSI register. +// +//***************************************************************************** +#define ADC_PSSI_GSYNC 0x80000000 // Global Synchronize +#define ADC_PSSI_SYNCWAIT 0x08000000 // Synchronize Wait +#define ADC_PSSI_SS3 0x00000008 // SS3 Initiate +#define ADC_PSSI_SS2 0x00000004 // SS2 Initiate +#define ADC_PSSI_SS1 0x00000002 // SS1 Initiate +#define ADC_PSSI_SS0 0x00000001 // SS0 Initiate + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SAC register. +// +//***************************************************************************** +#define ADC_SAC_AVG_M 0x00000007 // Hardware Averaging Control +#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling +#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling +#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling +#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling +#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling +#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling +#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCISC register. +// +//***************************************************************************** +#define ADC_DCISC_DCINT7 0x00000080 // Digital Comparator 7 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT6 0x00000040 // Digital Comparator 6 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT5 0x00000020 // Digital Comparator 5 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT4 0x00000010 // Digital Comparator 4 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT3 0x00000008 // Digital Comparator 3 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT2 0x00000004 // Digital Comparator 2 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT1 0x00000002 // Digital Comparator 1 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT0 0x00000001 // Digital Comparator 0 Interrupt + // Status and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_CTL register. +// +//***************************************************************************** +#define ADC_CTL_VREF_M 0x00000003 // Voltage Reference Select +#define ADC_CTL_VREF_INTERNAL 0x00000000 // VDDA and GNDA are the voltage + // references +#define ADC_CTL_VREF_EXT_3V 0x00000001 // The external VREFA+ and VREFA- + // inputs are the voltage + // references + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX0 register. +// +//***************************************************************************** +#define ADC_SSMUX0_MUX7_M 0xF0000000 // 8th Sample Input Select +#define ADC_SSMUX0_MUX6_M 0x0F000000 // 7th Sample Input Select +#define ADC_SSMUX0_MUX5_M 0x00F00000 // 6th Sample Input Select +#define ADC_SSMUX0_MUX4_M 0x000F0000 // 5th Sample Input Select +#define ADC_SSMUX0_MUX3_M 0x0000F000 // 4th Sample Input Select +#define ADC_SSMUX0_MUX2_M 0x00000F00 // 3rd Sample Input Select +#define ADC_SSMUX0_MUX1_M 0x000000F0 // 2nd Sample Input Select +#define ADC_SSMUX0_MUX0_M 0x0000000F // 1st Sample Input Select +#define ADC_SSMUX0_MUX7_S 28 +#define ADC_SSMUX0_MUX6_S 24 +#define ADC_SSMUX0_MUX5_S 20 +#define ADC_SSMUX0_MUX4_S 16 +#define ADC_SSMUX0_MUX3_S 12 +#define ADC_SSMUX0_MUX2_S 8 +#define ADC_SSMUX0_MUX1_S 4 +#define ADC_SSMUX0_MUX0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL0 register. +// +//***************************************************************************** +#define ADC_SSCTL0_TS7 0x80000000 // 8th Sample Temp Sensor Select +#define ADC_SSCTL0_IE7 0x40000000 // 8th Sample Interrupt Enable +#define ADC_SSCTL0_END7 0x20000000 // 8th Sample is End of Sequence +#define ADC_SSCTL0_D7 0x10000000 // 8th Sample Differential Input + // Select +#define ADC_SSCTL0_TS6 0x08000000 // 7th Sample Temp Sensor Select +#define ADC_SSCTL0_IE6 0x04000000 // 7th Sample Interrupt Enable +#define ADC_SSCTL0_END6 0x02000000 // 7th Sample is End of Sequence +#define ADC_SSCTL0_D6 0x01000000 // 7th Sample Differential Input + // Select +#define ADC_SSCTL0_TS5 0x00800000 // 6th Sample Temp Sensor Select +#define ADC_SSCTL0_IE5 0x00400000 // 6th Sample Interrupt Enable +#define ADC_SSCTL0_END5 0x00200000 // 6th Sample is End of Sequence +#define ADC_SSCTL0_D5 0x00100000 // 6th Sample Differential Input + // Select +#define ADC_SSCTL0_TS4 0x00080000 // 5th Sample Temp Sensor Select +#define ADC_SSCTL0_IE4 0x00040000 // 5th Sample Interrupt Enable +#define ADC_SSCTL0_END4 0x00020000 // 5th Sample is End of Sequence +#define ADC_SSCTL0_D4 0x00010000 // 5th Sample Differential Input + // Select +#define ADC_SSCTL0_TS3 0x00008000 // 4th Sample Temp Sensor Select +#define ADC_SSCTL0_IE3 0x00004000 // 4th Sample Interrupt Enable +#define ADC_SSCTL0_END3 0x00002000 // 4th Sample is End of Sequence +#define ADC_SSCTL0_D3 0x00001000 // 4th Sample Differential Input + // Select +#define ADC_SSCTL0_TS2 0x00000800 // 3rd Sample Temp Sensor Select +#define ADC_SSCTL0_IE2 0x00000400 // 3rd Sample Interrupt Enable +#define ADC_SSCTL0_END2 0x00000200 // 3rd Sample is End of Sequence +#define ADC_SSCTL0_D2 0x00000100 // 3rd Sample Differential Input + // Select +#define ADC_SSCTL0_TS1 0x00000080 // 2nd Sample Temp Sensor Select +#define ADC_SSCTL0_IE1 0x00000040 // 2nd Sample Interrupt Enable +#define ADC_SSCTL0_END1 0x00000020 // 2nd Sample is End of Sequence +#define ADC_SSCTL0_D1 0x00000010 // 2nd Sample Differential Input + // Select +#define ADC_SSCTL0_TS0 0x00000008 // 1st Sample Temp Sensor Select +#define ADC_SSCTL0_IE0 0x00000004 // 1st Sample Interrupt Enable +#define ADC_SSCTL0_END0 0x00000002 // 1st Sample is End of Sequence +#define ADC_SSCTL0_D0 0x00000001 // 1st Sample Differential Input + // Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO0 register. +// +//***************************************************************************** +#define ADC_SSFIFO0_DATA_M 0x00000FFF // Conversion Result Data +#define ADC_SSFIFO0_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register. +// +//***************************************************************************** +#define ADC_SSFSTAT0_FULL 0x00001000 // FIFO Full +#define ADC_SSFSTAT0_EMPTY 0x00000100 // FIFO Empty +#define ADC_SSFSTAT0_HPTR_M 0x000000F0 // FIFO Head Pointer +#define ADC_SSFSTAT0_TPTR_M 0x0000000F // FIFO Tail Pointer +#define ADC_SSFSTAT0_HPTR_S 4 +#define ADC_SSFSTAT0_TPTR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSOP0 register. +// +//***************************************************************************** +#define ADC_SSOP0_S7DCOP 0x10000000 // Sample 7 Digital Comparator + // Operation +#define ADC_SSOP0_S6DCOP 0x01000000 // Sample 6 Digital Comparator + // Operation +#define ADC_SSOP0_S5DCOP 0x00100000 // Sample 5 Digital Comparator + // Operation +#define ADC_SSOP0_S4DCOP 0x00010000 // Sample 4 Digital Comparator + // Operation +#define ADC_SSOP0_S3DCOP 0x00001000 // Sample 3 Digital Comparator + // Operation +#define ADC_SSOP0_S2DCOP 0x00000100 // Sample 2 Digital Comparator + // Operation +#define ADC_SSOP0_S1DCOP 0x00000010 // Sample 1 Digital Comparator + // Operation +#define ADC_SSOP0_S0DCOP 0x00000001 // Sample 0 Digital Comparator + // Operation + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSDC0 register. +// +//***************************************************************************** +#define ADC_SSDC0_S7DCSEL_M 0xF0000000 // Sample 7 Digital Comparator + // Select +#define ADC_SSDC0_S6DCSEL_M 0x0F000000 // Sample 6 Digital Comparator + // Select +#define ADC_SSDC0_S5DCSEL_M 0x00F00000 // Sample 5 Digital Comparator + // Select +#define ADC_SSDC0_S4DCSEL_M 0x000F0000 // Sample 4 Digital Comparator + // Select +#define ADC_SSDC0_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator + // Select +#define ADC_SSDC0_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator + // Select +#define ADC_SSDC0_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator + // Select +#define ADC_SSDC0_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator + // Select +#define ADC_SSDC0_S6DCSEL_S 24 +#define ADC_SSDC0_S5DCSEL_S 20 +#define ADC_SSDC0_S4DCSEL_S 16 +#define ADC_SSDC0_S3DCSEL_S 12 +#define ADC_SSDC0_S2DCSEL_S 8 +#define ADC_SSDC0_S1DCSEL_S 4 +#define ADC_SSDC0_S0DCSEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSEMUX0 register. +// +//***************************************************************************** +#define ADC_SSEMUX0_EMUX7 0x10000000 // 8th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX0_EMUX6 0x01000000 // 7th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX0_EMUX5 0x00100000 // 6th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX0_EMUX4 0x00010000 // 5th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX0_EMUX3 0x00001000 // 4th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX0_EMUX2 0x00000100 // 3rd Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX0_EMUX1 0x00000010 // 2th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX0_EMUX0 0x00000001 // 1st Sample Input Select (Upper + // Bit) + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSTSH0 register. +// +//***************************************************************************** +#define ADC_SSTSH0_TSH7_M 0xF0000000 // 8th Sample and Hold Period + // Select +#define ADC_SSTSH0_TSH6_M 0x0F000000 // 7th Sample and Hold Period + // Select +#define ADC_SSTSH0_TSH5_M 0x00F00000 // 6th Sample and Hold Period + // Select +#define ADC_SSTSH0_TSH4_M 0x000F0000 // 5th Sample and Hold Period + // Select +#define ADC_SSTSH0_TSH3_M 0x0000F000 // 4th Sample and Hold Period + // Select +#define ADC_SSTSH0_TSH2_M 0x00000F00 // 3rd Sample and Hold Period + // Select +#define ADC_SSTSH0_TSH1_M 0x000000F0 // 2nd Sample and Hold Period + // Select +#define ADC_SSTSH0_TSH0_M 0x0000000F // 1st Sample and Hold Period + // Select +#define ADC_SSTSH0_TSH7_S 28 +#define ADC_SSTSH0_TSH6_S 24 +#define ADC_SSTSH0_TSH5_S 20 +#define ADC_SSTSH0_TSH4_S 16 +#define ADC_SSTSH0_TSH3_S 12 +#define ADC_SSTSH0_TSH2_S 8 +#define ADC_SSTSH0_TSH1_S 4 +#define ADC_SSTSH0_TSH0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX1 register. +// +//***************************************************************************** +#define ADC_SSMUX1_MUX3_M 0x0000F000 // 4th Sample Input Select +#define ADC_SSMUX1_MUX2_M 0x00000F00 // 3rd Sample Input Select +#define ADC_SSMUX1_MUX1_M 0x000000F0 // 2nd Sample Input Select +#define ADC_SSMUX1_MUX0_M 0x0000000F // 1st Sample Input Select +#define ADC_SSMUX1_MUX3_S 12 +#define ADC_SSMUX1_MUX2_S 8 +#define ADC_SSMUX1_MUX1_S 4 +#define ADC_SSMUX1_MUX0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL1 register. +// +//***************************************************************************** +#define ADC_SSCTL1_TS3 0x00008000 // 4th Sample Temp Sensor Select +#define ADC_SSCTL1_IE3 0x00004000 // 4th Sample Interrupt Enable +#define ADC_SSCTL1_END3 0x00002000 // 4th Sample is End of Sequence +#define ADC_SSCTL1_D3 0x00001000 // 4th Sample Differential Input + // Select +#define ADC_SSCTL1_TS2 0x00000800 // 3rd Sample Temp Sensor Select +#define ADC_SSCTL1_IE2 0x00000400 // 3rd Sample Interrupt Enable +#define ADC_SSCTL1_END2 0x00000200 // 3rd Sample is End of Sequence +#define ADC_SSCTL1_D2 0x00000100 // 3rd Sample Differential Input + // Select +#define ADC_SSCTL1_TS1 0x00000080 // 2nd Sample Temp Sensor Select +#define ADC_SSCTL1_IE1 0x00000040 // 2nd Sample Interrupt Enable +#define ADC_SSCTL1_END1 0x00000020 // 2nd Sample is End of Sequence +#define ADC_SSCTL1_D1 0x00000010 // 2nd Sample Differential Input + // Select +#define ADC_SSCTL1_TS0 0x00000008 // 1st Sample Temp Sensor Select +#define ADC_SSCTL1_IE0 0x00000004 // 1st Sample Interrupt Enable +#define ADC_SSCTL1_END0 0x00000002 // 1st Sample is End of Sequence +#define ADC_SSCTL1_D0 0x00000001 // 1st Sample Differential Input + // Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO1 register. +// +//***************************************************************************** +#define ADC_SSFIFO1_DATA_M 0x00000FFF // Conversion Result Data +#define ADC_SSFIFO1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register. +// +//***************************************************************************** +#define ADC_SSFSTAT1_FULL 0x00001000 // FIFO Full +#define ADC_SSFSTAT1_EMPTY 0x00000100 // FIFO Empty +#define ADC_SSFSTAT1_HPTR_M 0x000000F0 // FIFO Head Pointer +#define ADC_SSFSTAT1_TPTR_M 0x0000000F // FIFO Tail Pointer +#define ADC_SSFSTAT1_HPTR_S 4 +#define ADC_SSFSTAT1_TPTR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSOP1 register. +// +//***************************************************************************** +#define ADC_SSOP1_S3DCOP 0x00001000 // Sample 3 Digital Comparator + // Operation +#define ADC_SSOP1_S2DCOP 0x00000100 // Sample 2 Digital Comparator + // Operation +#define ADC_SSOP1_S1DCOP 0x00000010 // Sample 1 Digital Comparator + // Operation +#define ADC_SSOP1_S0DCOP 0x00000001 // Sample 0 Digital Comparator + // Operation + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSDC1 register. +// +//***************************************************************************** +#define ADC_SSDC1_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator + // Select +#define ADC_SSDC1_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator + // Select +#define ADC_SSDC1_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator + // Select +#define ADC_SSDC1_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator + // Select +#define ADC_SSDC1_S2DCSEL_S 8 +#define ADC_SSDC1_S1DCSEL_S 4 +#define ADC_SSDC1_S0DCSEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSEMUX1 register. +// +//***************************************************************************** +#define ADC_SSEMUX1_EMUX3 0x00001000 // 4th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX1_EMUX2 0x00000100 // 3rd Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX1_EMUX1 0x00000010 // 2th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX1_EMUX0 0x00000001 // 1st Sample Input Select (Upper + // Bit) + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSTSH1 register. +// +//***************************************************************************** +#define ADC_SSTSH1_TSH3_M 0x0000F000 // 4th Sample and Hold Period + // Select +#define ADC_SSTSH1_TSH2_M 0x00000F00 // 3rd Sample and Hold Period + // Select +#define ADC_SSTSH1_TSH1_M 0x000000F0 // 2nd Sample and Hold Period + // Select +#define ADC_SSTSH1_TSH0_M 0x0000000F // 1st Sample and Hold Period + // Select +#define ADC_SSTSH1_TSH3_S 12 +#define ADC_SSTSH1_TSH2_S 8 +#define ADC_SSTSH1_TSH1_S 4 +#define ADC_SSTSH1_TSH0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX2 register. +// +//***************************************************************************** +#define ADC_SSMUX2_MUX3_M 0x0000F000 // 4th Sample Input Select +#define ADC_SSMUX2_MUX2_M 0x00000F00 // 3rd Sample Input Select +#define ADC_SSMUX2_MUX1_M 0x000000F0 // 2nd Sample Input Select +#define ADC_SSMUX2_MUX0_M 0x0000000F // 1st Sample Input Select +#define ADC_SSMUX2_MUX3_S 12 +#define ADC_SSMUX2_MUX2_S 8 +#define ADC_SSMUX2_MUX1_S 4 +#define ADC_SSMUX2_MUX0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL2 register. +// +//***************************************************************************** +#define ADC_SSCTL2_TS3 0x00008000 // 4th Sample Temp Sensor Select +#define ADC_SSCTL2_IE3 0x00004000 // 4th Sample Interrupt Enable +#define ADC_SSCTL2_END3 0x00002000 // 4th Sample is End of Sequence +#define ADC_SSCTL2_D3 0x00001000 // 4th Sample Differential Input + // Select +#define ADC_SSCTL2_TS2 0x00000800 // 3rd Sample Temp Sensor Select +#define ADC_SSCTL2_IE2 0x00000400 // 3rd Sample Interrupt Enable +#define ADC_SSCTL2_END2 0x00000200 // 3rd Sample is End of Sequence +#define ADC_SSCTL2_D2 0x00000100 // 3rd Sample Differential Input + // Select +#define ADC_SSCTL2_TS1 0x00000080 // 2nd Sample Temp Sensor Select +#define ADC_SSCTL2_IE1 0x00000040 // 2nd Sample Interrupt Enable +#define ADC_SSCTL2_END1 0x00000020 // 2nd Sample is End of Sequence +#define ADC_SSCTL2_D1 0x00000010 // 2nd Sample Differential Input + // Select +#define ADC_SSCTL2_TS0 0x00000008 // 1st Sample Temp Sensor Select +#define ADC_SSCTL2_IE0 0x00000004 // 1st Sample Interrupt Enable +#define ADC_SSCTL2_END0 0x00000002 // 1st Sample is End of Sequence +#define ADC_SSCTL2_D0 0x00000001 // 1st Sample Differential Input + // Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO2 register. +// +//***************************************************************************** +#define ADC_SSFIFO2_DATA_M 0x00000FFF // Conversion Result Data +#define ADC_SSFIFO2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register. +// +//***************************************************************************** +#define ADC_SSFSTAT2_FULL 0x00001000 // FIFO Full +#define ADC_SSFSTAT2_EMPTY 0x00000100 // FIFO Empty +#define ADC_SSFSTAT2_HPTR_M 0x000000F0 // FIFO Head Pointer +#define ADC_SSFSTAT2_TPTR_M 0x0000000F // FIFO Tail Pointer +#define ADC_SSFSTAT2_HPTR_S 4 +#define ADC_SSFSTAT2_TPTR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSOP2 register. +// +//***************************************************************************** +#define ADC_SSOP2_S3DCOP 0x00001000 // Sample 3 Digital Comparator + // Operation +#define ADC_SSOP2_S2DCOP 0x00000100 // Sample 2 Digital Comparator + // Operation +#define ADC_SSOP2_S1DCOP 0x00000010 // Sample 1 Digital Comparator + // Operation +#define ADC_SSOP2_S0DCOP 0x00000001 // Sample 0 Digital Comparator + // Operation + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSDC2 register. +// +//***************************************************************************** +#define ADC_SSDC2_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator + // Select +#define ADC_SSDC2_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator + // Select +#define ADC_SSDC2_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator + // Select +#define ADC_SSDC2_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator + // Select +#define ADC_SSDC2_S2DCSEL_S 8 +#define ADC_SSDC2_S1DCSEL_S 4 +#define ADC_SSDC2_S0DCSEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSEMUX2 register. +// +//***************************************************************************** +#define ADC_SSEMUX2_EMUX3 0x00001000 // 4th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX2_EMUX2 0x00000100 // 3rd Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX2_EMUX1 0x00000010 // 2th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX2_EMUX0 0x00000001 // 1st Sample Input Select (Upper + // Bit) + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSTSH2 register. +// +//***************************************************************************** +#define ADC_SSTSH2_TSH3_M 0x0000F000 // 4th Sample and Hold Period + // Select +#define ADC_SSTSH2_TSH2_M 0x00000F00 // 3rd Sample and Hold Period + // Select +#define ADC_SSTSH2_TSH1_M 0x000000F0 // 2nd Sample and Hold Period + // Select +#define ADC_SSTSH2_TSH0_M 0x0000000F // 1st Sample and Hold Period + // Select +#define ADC_SSTSH2_TSH3_S 12 +#define ADC_SSTSH2_TSH2_S 8 +#define ADC_SSTSH2_TSH1_S 4 +#define ADC_SSTSH2_TSH0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX3 register. +// +//***************************************************************************** +#define ADC_SSMUX3_MUX0_M 0x0000000F // 1st Sample Input Select +#define ADC_SSMUX3_MUX0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL3 register. +// +//***************************************************************************** +#define ADC_SSCTL3_TS0 0x00000008 // 1st Sample Temp Sensor Select +#define ADC_SSCTL3_IE0 0x00000004 // Sample Interrupt Enable +#define ADC_SSCTL3_END0 0x00000002 // End of Sequence +#define ADC_SSCTL3_D0 0x00000001 // Sample Differential Input Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO3 register. +// +//***************************************************************************** +#define ADC_SSFIFO3_DATA_M 0x00000FFF // Conversion Result Data +#define ADC_SSFIFO3_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register. +// +//***************************************************************************** +#define ADC_SSFSTAT3_FULL 0x00001000 // FIFO Full +#define ADC_SSFSTAT3_EMPTY 0x00000100 // FIFO Empty +#define ADC_SSFSTAT3_HPTR_M 0x000000F0 // FIFO Head Pointer +#define ADC_SSFSTAT3_TPTR_M 0x0000000F // FIFO Tail Pointer +#define ADC_SSFSTAT3_HPTR_S 4 +#define ADC_SSFSTAT3_TPTR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSOP3 register. +// +//***************************************************************************** +#define ADC_SSOP3_S0DCOP 0x00000001 // Sample 0 Digital Comparator + // Operation + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSDC3 register. +// +//***************************************************************************** +#define ADC_SSDC3_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator + // Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSEMUX3 register. +// +//***************************************************************************** +#define ADC_SSEMUX3_EMUX0 0x00000001 // 1st Sample Input Select (Upper + // Bit) + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSTSH3 register. +// +//***************************************************************************** +#define ADC_SSTSH3_TSH0_M 0x0000000F // 1st Sample and Hold Period + // Select +#define ADC_SSTSH3_TSH0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCRIC register. +// +//***************************************************************************** +#define ADC_DCRIC_DCTRIG7 0x00800000 // Digital Comparator Trigger 7 +#define ADC_DCRIC_DCTRIG6 0x00400000 // Digital Comparator Trigger 6 +#define ADC_DCRIC_DCTRIG5 0x00200000 // Digital Comparator Trigger 5 +#define ADC_DCRIC_DCTRIG4 0x00100000 // Digital Comparator Trigger 4 +#define ADC_DCRIC_DCTRIG3 0x00080000 // Digital Comparator Trigger 3 +#define ADC_DCRIC_DCTRIG2 0x00040000 // Digital Comparator Trigger 2 +#define ADC_DCRIC_DCTRIG1 0x00020000 // Digital Comparator Trigger 1 +#define ADC_DCRIC_DCTRIG0 0x00010000 // Digital Comparator Trigger 0 +#define ADC_DCRIC_DCINT7 0x00000080 // Digital Comparator Interrupt 7 +#define ADC_DCRIC_DCINT6 0x00000040 // Digital Comparator Interrupt 6 +#define ADC_DCRIC_DCINT5 0x00000020 // Digital Comparator Interrupt 5 +#define ADC_DCRIC_DCINT4 0x00000010 // Digital Comparator Interrupt 4 +#define ADC_DCRIC_DCINT3 0x00000008 // Digital Comparator Interrupt 3 +#define ADC_DCRIC_DCINT2 0x00000004 // Digital Comparator Interrupt 2 +#define ADC_DCRIC_DCINT1 0x00000002 // Digital Comparator Interrupt 1 +#define ADC_DCRIC_DCINT0 0x00000001 // Digital Comparator Interrupt 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL0 register. +// +//***************************************************************************** +#define ADC_DCCTL0_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL0_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL0_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL0_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL0_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL0_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL0_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL0_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL0_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL0_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL0_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL0_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL0_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL0_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL0_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL0_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL0_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL0_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL0_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL0_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL1 register. +// +//***************************************************************************** +#define ADC_DCCTL1_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL1_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL1_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL1_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL1_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL1_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL1_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL1_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL1_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL1_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL1_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL1_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL1_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL1_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL1_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL1_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL1_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL1_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL1_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL1_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL2 register. +// +//***************************************************************************** +#define ADC_DCCTL2_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL2_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL2_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL2_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL2_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL2_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL2_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL2_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL2_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL2_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL2_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL2_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL2_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL2_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL2_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL2_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL2_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL2_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL2_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL2_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL3 register. +// +//***************************************************************************** +#define ADC_DCCTL3_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL3_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL3_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL3_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL3_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL3_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL3_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL3_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL3_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL3_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL3_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL3_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL3_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL3_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL3_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL3_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL3_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL3_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL3_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL3_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL4 register. +// +//***************************************************************************** +#define ADC_DCCTL4_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL4_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL4_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL4_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL4_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL4_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL4_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL4_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL4_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL4_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL4_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL4_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL4_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL4_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL4_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL4_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL4_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL4_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL4_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL4_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL5 register. +// +//***************************************************************************** +#define ADC_DCCTL5_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL5_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL5_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL5_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL5_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL5_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL5_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL5_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL5_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL5_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL5_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL5_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL5_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL5_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL5_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL5_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL5_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL5_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL5_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL5_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL6 register. +// +//***************************************************************************** +#define ADC_DCCTL6_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL6_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL6_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL6_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL6_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL6_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL6_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL6_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL6_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL6_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL6_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL6_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL6_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL6_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL6_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL6_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL6_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL6_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL6_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL6_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL7 register. +// +//***************************************************************************** +#define ADC_DCCTL7_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL7_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL7_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL7_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL7_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL7_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL7_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL7_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL7_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL7_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL7_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL7_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL7_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL7_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL7_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL7_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL7_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL7_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL7_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL7_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP0 register. +// +//***************************************************************************** +#define ADC_DCCMP0_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP0_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP0_COMP1_S 16 +#define ADC_DCCMP0_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP1 register. +// +//***************************************************************************** +#define ADC_DCCMP1_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP1_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP1_COMP1_S 16 +#define ADC_DCCMP1_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP2 register. +// +//***************************************************************************** +#define ADC_DCCMP2_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP2_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP2_COMP1_S 16 +#define ADC_DCCMP2_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP3 register. +// +//***************************************************************************** +#define ADC_DCCMP3_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP3_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP3_COMP1_S 16 +#define ADC_DCCMP3_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP4 register. +// +//***************************************************************************** +#define ADC_DCCMP4_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP4_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP4_COMP1_S 16 +#define ADC_DCCMP4_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP5 register. +// +//***************************************************************************** +#define ADC_DCCMP5_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP5_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP5_COMP1_S 16 +#define ADC_DCCMP5_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP6 register. +// +//***************************************************************************** +#define ADC_DCCMP6_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP6_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP6_COMP1_S 16 +#define ADC_DCCMP6_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP7 register. +// +//***************************************************************************** +#define ADC_DCCMP7_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP7_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP7_COMP1_S 16 +#define ADC_DCCMP7_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_PP register. +// +//***************************************************************************** +#define ADC_PP_APSHT 0x01000000 // Application-Programmable + // Sample-and-Hold Time +#define ADC_PP_TS 0x00800000 // Temperature Sensor +#define ADC_PP_RSL_M 0x007C0000 // Resolution +#define ADC_PP_TYPE_M 0x00030000 // ADC Architecture +#define ADC_PP_TYPE_SAR 0x00000000 // SAR +#define ADC_PP_DC_M 0x0000FC00 // Digital Comparator Count +#define ADC_PP_CH_M 0x000003F0 // ADC Channel Count +#define ADC_PP_MCR_M 0x0000000F // Maximum Conversion Rate +#define ADC_PP_MCR_FULL 0x00000007 // Full conversion rate (FCONV) as + // defined by TADC and NSH +#define ADC_PP_MSR_M 0x0000000F // Maximum ADC Sample Rate +#define ADC_PP_MSR_125K 0x00000001 // 125 ksps +#define ADC_PP_MSR_250K 0x00000003 // 250 ksps +#define ADC_PP_MSR_500K 0x00000005 // 500 ksps +#define ADC_PP_MSR_1M 0x00000007 // 1 Msps +#define ADC_PP_RSL_S 18 +#define ADC_PP_DC_S 10 +#define ADC_PP_CH_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_PC register. +// +//***************************************************************************** +#define ADC_PC_SR_M 0x0000000F // ADC Sample Rate +#define ADC_PC_SR_125K 0x00000001 // 125 ksps +#define ADC_PC_SR_250K 0x00000003 // 250 ksps +#define ADC_PC_SR_500K 0x00000005 // 500 ksps +#define ADC_PC_SR_1M 0x00000007 // 1 Msps +#define ADC_PC_MCR_M 0x0000000F // Conversion Rate +#define ADC_PC_MCR_1_8 0x00000001 // Eighth conversion rate. After a + // conversion completes, the logic + // pauses for 112 TADC periods + // before starting the next + // conversion +#define ADC_PC_MCR_1_4 0x00000003 // Quarter conversion rate. After a + // conversion completes, the logic + // pauses for 48 TADC periods + // before starting the next + // conversion +#define ADC_PC_MCR_1_2 0x00000005 // Half conversion rate. After a + // conversion completes, the logic + // pauses for 16 TADC periods + // before starting the next + // conversion +#define ADC_PC_MCR_FULL 0x00000007 // Full conversion rate (FCONV) as + // defined by TADC and NSH + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_CC register. +// +//***************************************************************************** +#define ADC_CC_CLKDIV_M 0x000003F0 // PLL VCO Clock Divisor +#define ADC_CC_CS_M 0x0000000F // ADC Clock Source +#define ADC_CC_CS_SYSPLL 0x00000000 // PLL VCO divided by CLKDIV +#define ADC_CC_CS_PIOSC 0x00000001 // PIOSC +#define ADC_CC_CS_MOSC 0x00000002 // MOSC +#define ADC_CC_CLKDIV_S 4 + +#endif // __HW_ADC_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_aes.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_aes.h new file mode 100644 index 0000000000000000000000000000000000000000..79d56113d65d213d247d0f3b2f7ce159dd788380 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_aes.h @@ -0,0 +1,545 @@ +//***************************************************************************** +// +// hw_aes.h - Macros used when accessing the AES hardware. +// +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_AES_H__ +#define __HW_AES_H__ + +//***************************************************************************** +// +// The following are defines for the AES register offsets. +// +//***************************************************************************** +#define AES_O_KEY2_6 0x00000000 // AES Key 2_6 +#define AES_O_KEY2_7 0x00000004 // AES Key 2_7 +#define AES_O_KEY2_4 0x00000008 // AES Key 2_4 +#define AES_O_KEY2_5 0x0000000C // AES Key 2_5 +#define AES_O_KEY2_2 0x00000010 // AES Key 2_2 +#define AES_O_KEY2_3 0x00000014 // AES Key 2_3 +#define AES_O_KEY2_0 0x00000018 // AES Key 2_0 +#define AES_O_KEY2_1 0x0000001C // AES Key 2_1 +#define AES_O_KEY1_6 0x00000020 // AES Key 1_6 +#define AES_O_KEY1_7 0x00000024 // AES Key 1_7 +#define AES_O_KEY1_4 0x00000028 // AES Key 1_4 +#define AES_O_KEY1_5 0x0000002C // AES Key 1_5 +#define AES_O_KEY1_2 0x00000030 // AES Key 1_2 +#define AES_O_KEY1_3 0x00000034 // AES Key 1_3 +#define AES_O_KEY1_0 0x00000038 // AES Key 1_0 +#define AES_O_KEY1_1 0x0000003C // AES Key 1_1 +#define AES_O_IV_IN_0 0x00000040 // AES Initialization Vector Input + // 0 +#define AES_O_IV_IN_1 0x00000044 // AES Initialization Vector Input + // 1 +#define AES_O_IV_IN_2 0x00000048 // AES Initialization Vector Input + // 2 +#define AES_O_IV_IN_3 0x0000004C // AES Initialization Vector Input + // 3 +#define AES_O_CTRL 0x00000050 // AES Control +#define AES_O_C_LENGTH_0 0x00000054 // AES Crypto Data Length 0 +#define AES_O_C_LENGTH_1 0x00000058 // AES Crypto Data Length 1 +#define AES_O_AUTH_LENGTH 0x0000005C // AES Authentication Data Length +#define AES_O_DATA_IN_0 0x00000060 // AES Data RW Plaintext/Ciphertext + // 0 +#define AES_O_DATA_IN_1 0x00000064 // AES Data RW Plaintext/Ciphertext + // 1 +#define AES_O_DATA_IN_2 0x00000068 // AES Data RW Plaintext/Ciphertext + // 2 +#define AES_O_DATA_IN_3 0x0000006C // AES Data RW Plaintext/Ciphertext + // 3 +#define AES_O_TAG_OUT_0 0x00000070 // AES Hash Tag Out 0 +#define AES_O_TAG_OUT_1 0x00000074 // AES Hash Tag Out 1 +#define AES_O_TAG_OUT_2 0x00000078 // AES Hash Tag Out 2 +#define AES_O_TAG_OUT_3 0x0000007C // AES Hash Tag Out 3 +#define AES_O_REVISION 0x00000080 // AES IP Revision Identifier +#define AES_O_SYSCONFIG 0x00000084 // AES System Configuration +#define AES_O_SYSSTATUS 0x00000088 // AES System Status +#define AES_O_IRQSTATUS 0x0000008C // AES Interrupt Status +#define AES_O_IRQENABLE 0x00000090 // AES Interrupt Enable +#define AES_O_DIRTYBITS 0x00000094 // AES Dirty Bits +#define AES_O_DMAIM 0xFFFFA020 // AES DMA Interrupt Mask +#define AES_O_DMARIS 0xFFFFA024 // AES DMA Raw Interrupt Status +#define AES_O_DMAMIS 0xFFFFA028 // AES DMA Masked Interrupt Status +#define AES_O_DMAIC 0xFFFFA02C // AES DMA Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_6 register. +// +//***************************************************************************** +#define AES_KEY2_6_KEY_M 0xFFFFFFFF // Key Data +#define AES_KEY2_6_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_7 register. +// +//***************************************************************************** +#define AES_KEY2_7_KEY_M 0xFFFFFFFF // Key Data +#define AES_KEY2_7_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_4 register. +// +//***************************************************************************** +#define AES_KEY2_4_KEY_M 0xFFFFFFFF // Key Data +#define AES_KEY2_4_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_5 register. +// +//***************************************************************************** +#define AES_KEY2_5_KEY_M 0xFFFFFFFF // Key Data +#define AES_KEY2_5_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_2 register. +// +//***************************************************************************** +#define AES_KEY2_2_KEY_M 0xFFFFFFFF // Key Data +#define AES_KEY2_2_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_3 register. +// +//***************************************************************************** +#define AES_KEY2_3_KEY_M 0xFFFFFFFF // Key Data +#define AES_KEY2_3_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_0 register. +// +//***************************************************************************** +#define AES_KEY2_0_KEY_M 0xFFFFFFFF // Key Data +#define AES_KEY2_0_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_1 register. +// +//***************************************************************************** +#define AES_KEY2_1_KEY_M 0xFFFFFFFF // Key Data +#define AES_KEY2_1_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_6 register. +// +//***************************************************************************** +#define AES_KEY1_6_KEY_M 0xFFFFFFFF // Key Data +#define AES_KEY1_6_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_7 register. +// +//***************************************************************************** +#define AES_KEY1_7_KEY_M 0xFFFFFFFF // Key Data +#define AES_KEY1_7_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_4 register. +// +//***************************************************************************** +#define AES_KEY1_4_KEY_M 0xFFFFFFFF // Key Data +#define AES_KEY1_4_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_5 register. +// +//***************************************************************************** +#define AES_KEY1_5_KEY_M 0xFFFFFFFF // Key Data +#define AES_KEY1_5_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_2 register. +// +//***************************************************************************** +#define AES_KEY1_2_KEY_M 0xFFFFFFFF // Key Data +#define AES_KEY1_2_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_3 register. +// +//***************************************************************************** +#define AES_KEY1_3_KEY_M 0xFFFFFFFF // Key Data +#define AES_KEY1_3_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_0 register. +// +//***************************************************************************** +#define AES_KEY1_0_KEY_M 0xFFFFFFFF // Key Data +#define AES_KEY1_0_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_1 register. +// +//***************************************************************************** +#define AES_KEY1_1_KEY_M 0xFFFFFFFF // Key Data +#define AES_KEY1_1_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_IV_IN_0 register. +// +//***************************************************************************** +#define AES_IV_IN_0_DATA_M 0xFFFFFFFF // Initialization Vector Input +#define AES_IV_IN_0_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_IV_IN_1 register. +// +//***************************************************************************** +#define AES_IV_IN_1_DATA_M 0xFFFFFFFF // Initialization Vector Input +#define AES_IV_IN_1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_IV_IN_2 register. +// +//***************************************************************************** +#define AES_IV_IN_2_DATA_M 0xFFFFFFFF // Initialization Vector Input +#define AES_IV_IN_2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_IV_IN_3 register. +// +//***************************************************************************** +#define AES_IV_IN_3_DATA_M 0xFFFFFFFF // Initialization Vector Input +#define AES_IV_IN_3_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_CTRL register. +// +//***************************************************************************** +#define AES_CTRL_CTXTRDY 0x80000000 // Context Data Registers Ready +#define AES_CTRL_SVCTXTRDY 0x40000000 // AES TAG/IV Block(s) Ready +#define AES_CTRL_SAVE_CONTEXT 0x20000000 // TAG or Result IV Save +#define AES_CTRL_CCM_M_M 0x01C00000 // Counter with CBC-MAC (CCM) +#define AES_CTRL_CCM_L_M 0x00380000 // L Value +#define AES_CTRL_CCM_L_2 0x00080000 // width = 2 +#define AES_CTRL_CCM_L_4 0x00180000 // width = 4 +#define AES_CTRL_CCM_L_8 0x00380000 // width = 8 +#define AES_CTRL_CCM 0x00040000 // AES-CCM Mode Enable +#define AES_CTRL_GCM_M 0x00030000 // AES-GCM Mode Enable +#define AES_CTRL_GCM_NOP 0x00000000 // No operation +#define AES_CTRL_GCM_HLY0ZERO 0x00010000 // GHASH with H loaded and + // Y0-encrypted forced to zero +#define AES_CTRL_GCM_HLY0CALC 0x00020000 // GHASH with H loaded and + // Y0-encrypted calculated + // internally +#define AES_CTRL_GCM_HY0CALC 0x00030000 // Autonomous GHASH (both H and + // Y0-encrypted calculated + // internally) +#define AES_CTRL_CBCMAC 0x00008000 // AES-CBC MAC Enable +#define AES_CTRL_F9 0x00004000 // AES f9 Mode Enable +#define AES_CTRL_F8 0x00002000 // AES f8 Mode Enable +#define AES_CTRL_XTS_M 0x00001800 // AES-XTS Operation Enabled +#define AES_CTRL_XTS_NOP 0x00000000 // No operation +#define AES_CTRL_XTS_TWEAKJL 0x00000800 // Previous/intermediate tweak + // value and j loaded (value is + // loaded via IV, j is loaded via + // the AAD length register) +#define AES_CTRL_XTS_K2IJL 0x00001000 // Key2, n and j are loaded (n is + // loaded via IV, j is loaded via + // the AAD length register) +#define AES_CTRL_XTS_K2ILJ0 0x00001800 // Key2 and n are loaded; j=0 (n is + // loaded via IV) +#define AES_CTRL_CFB 0x00000400 // Full block AES cipher feedback + // mode (CFB128) Enable +#define AES_CTRL_ICM 0x00000200 // AES Integer Counter Mode (ICM) + // Enable +#define AES_CTRL_CTR_WIDTH_M 0x00000180 // AES-CTR Mode Counter Width +#define AES_CTRL_CTR_WIDTH_32 0x00000000 // Counter is 32 bits +#define AES_CTRL_CTR_WIDTH_64 0x00000080 // Counter is 64 bits +#define AES_CTRL_CTR_WIDTH_96 0x00000100 // Counter is 96 bits +#define AES_CTRL_CTR_WIDTH_128 0x00000180 // Counter is 128 bits +#define AES_CTRL_CTR 0x00000040 // Counter Mode +#define AES_CTRL_MODE 0x00000020 // ECB/CBC Mode +#define AES_CTRL_KEY_SIZE_M 0x00000018 // Key Size +#define AES_CTRL_KEY_SIZE_128 0x00000008 // Key is 128 bits +#define AES_CTRL_KEY_SIZE_192 0x00000010 // Key is 192 bits +#define AES_CTRL_KEY_SIZE_256 0x00000018 // Key is 256 bits +#define AES_CTRL_DIRECTION 0x00000004 // Encryption/Decryption Selection +#define AES_CTRL_INPUT_READY 0x00000002 // Input Ready Status +#define AES_CTRL_OUTPUT_READY 0x00000001 // Output Ready Status +#define AES_CTRL_CCM_M_S 22 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_C_LENGTH_0 +// register. +// +//***************************************************************************** +#define AES_C_LENGTH_0_LENGTH_M 0xFFFFFFFF // Data Length +#define AES_C_LENGTH_0_LENGTH_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_C_LENGTH_1 +// register. +// +//***************************************************************************** +#define AES_C_LENGTH_1_LENGTH_M 0xFFFFFFFF // Data Length +#define AES_C_LENGTH_1_LENGTH_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_AUTH_LENGTH +// register. +// +//***************************************************************************** +#define AES_AUTH_LENGTH_AUTH_M 0xFFFFFFFF // Authentication Data Length +#define AES_AUTH_LENGTH_AUTH_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_DATA_IN_0 +// register. +// +//***************************************************************************** +#define AES_DATA_IN_0_DATA_M 0xFFFFFFFF // Secure Data RW + // Plaintext/Ciphertext +#define AES_DATA_IN_0_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_DATA_IN_1 +// register. +// +//***************************************************************************** +#define AES_DATA_IN_1_DATA_M 0xFFFFFFFF // Secure Data RW + // Plaintext/Ciphertext +#define AES_DATA_IN_1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_DATA_IN_2 +// register. +// +//***************************************************************************** +#define AES_DATA_IN_2_DATA_M 0xFFFFFFFF // Secure Data RW + // Plaintext/Ciphertext +#define AES_DATA_IN_2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_DATA_IN_3 +// register. +// +//***************************************************************************** +#define AES_DATA_IN_3_DATA_M 0xFFFFFFFF // Secure Data RW + // Plaintext/Ciphertext +#define AES_DATA_IN_3_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_TAG_OUT_0 +// register. +// +//***************************************************************************** +#define AES_TAG_OUT_0_HASH_M 0xFFFFFFFF // Hash Result +#define AES_TAG_OUT_0_HASH_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_TAG_OUT_1 +// register. +// +//***************************************************************************** +#define AES_TAG_OUT_1_HASH_M 0xFFFFFFFF // Hash Result +#define AES_TAG_OUT_1_HASH_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_TAG_OUT_2 +// register. +// +//***************************************************************************** +#define AES_TAG_OUT_2_HASH_M 0xFFFFFFFF // Hash Result +#define AES_TAG_OUT_2_HASH_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_TAG_OUT_3 +// register. +// +//***************************************************************************** +#define AES_TAG_OUT_3_HASH_M 0xFFFFFFFF // Hash Result +#define AES_TAG_OUT_3_HASH_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_REVISION register. +// +//***************************************************************************** +#define AES_REVISION_M 0xFFFFFFFF // Revision number +#define AES_REVISION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_SYSCONFIG +// register. +// +//***************************************************************************** +#define AES_SYSCONFIG_K3 0x00001000 // K3 Select +#define AES_SYSCONFIG_KEYENC 0x00000800 // Key Encoding +#define AES_SYSCONFIG_MAP_CONTEXT_OUT_ON_DATA_OUT \ + 0x00000200 // Map Context Out on Data Out + // Enable +#define AES_SYSCONFIG_DMA_REQ_CONTEXT_OUT_EN \ + 0x00000100 // DMA Request Context Out Enable +#define AES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \ + 0x00000080 // DMA Request Context In Enable +#define AES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \ + 0x00000040 // DMA Request Data Out Enable +#define AES_SYSCONFIG_DMA_REQ_DATA_IN_EN \ + 0x00000020 // DMA Request Data In Enable +#define AES_SYSCONFIG_SOFTRESET 0x00000002 // Soft reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_SYSSTATUS +// register. +// +//***************************************************************************** +#define AES_SYSSTATUS_RESETDONE 0x00000001 // Reset Done + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_IRQSTATUS +// register. +// +//***************************************************************************** +#define AES_IRQSTATUS_CONTEXT_OUT \ + 0x00000008 // Context Output Interrupt Status +#define AES_IRQSTATUS_DATA_OUT 0x00000004 // Data Out Interrupt Status +#define AES_IRQSTATUS_DATA_IN 0x00000002 // Data In Interrupt Status +#define AES_IRQSTATUS_CONTEXT_IN \ + 0x00000001 // Context In Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_IRQENABLE +// register. +// +//***************************************************************************** +#define AES_IRQENABLE_CONTEXT_OUT \ + 0x00000008 // Context Out Interrupt Enable +#define AES_IRQENABLE_DATA_OUT 0x00000004 // Data Out Interrupt Enable +#define AES_IRQENABLE_DATA_IN 0x00000002 // Data In Interrupt Enable +#define AES_IRQENABLE_CONTEXT_IN \ + 0x00000001 // Context In Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_DIRTYBITS +// register. +// +//***************************************************************************** +#define AES_DIRTYBITS_S_DIRTY 0x00000002 // AES Dirty Bit +#define AES_DIRTYBITS_S_ACCESS 0x00000001 // AES Access Bit + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_DMAIM register. +// +//***************************************************************************** +#define AES_DMAIM_DOUT 0x00000008 // Data Out DMA Done Interrupt Mask +#define AES_DMAIM_DIN 0x00000004 // Data In DMA Done Interrupt Mask +#define AES_DMAIM_COUT 0x00000002 // Context Out DMA Done Interrupt + // Mask +#define AES_DMAIM_CIN 0x00000001 // Context In DMA Done Interrupt + // Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_DMARIS register. +// +//***************************************************************************** +#define AES_DMARIS_DOUT 0x00000008 // Data Out DMA Done Raw Interrupt + // Status +#define AES_DMARIS_DIN 0x00000004 // Data In DMA Done Raw Interrupt + // Status +#define AES_DMARIS_COUT 0x00000002 // Context Out DMA Done Raw + // Interrupt Status +#define AES_DMARIS_CIN 0x00000001 // Context In DMA Done Raw + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_DMAMIS register. +// +//***************************************************************************** +#define AES_DMAMIS_DOUT 0x00000008 // Data Out DMA Done Masked + // Interrupt Status +#define AES_DMAMIS_DIN 0x00000004 // Data In DMA Done Masked + // Interrupt Status +#define AES_DMAMIS_COUT 0x00000002 // Context Out DMA Done Masked + // Interrupt Status +#define AES_DMAMIS_CIN 0x00000001 // Context In DMA Done Raw + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_DMAIC register. +// +//***************************************************************************** +#define AES_DMAIC_DOUT 0x00000008 // Data Out DMA Done Interrupt + // Clear +#define AES_DMAIC_DIN 0x00000004 // Data In DMA Done Interrupt Clear +#define AES_DMAIC_COUT 0x00000002 // Context Out DMA Done Masked + // Interrupt Status +#define AES_DMAIC_CIN 0x00000001 // Context In DMA Done Raw + // Interrupt Status + +#endif // __HW_AES_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_can.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_can.h new file mode 100644 index 0000000000000000000000000000000000000000..398a83d6cb1b0b550650997faaf7bde9a531caf5 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_can.h @@ -0,0 +1,462 @@ +//***************************************************************************** +// +// hw_can.h - Defines and macros used when accessing the CAN controllers. +// +// Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_CAN_H__ +#define __HW_CAN_H__ + +//***************************************************************************** +// +// The following are defines for the CAN register offsets. +// +//***************************************************************************** +#define CAN_O_CTL 0x00000000 // CAN Control +#define CAN_O_STS 0x00000004 // CAN Status +#define CAN_O_ERR 0x00000008 // CAN Error Counter +#define CAN_O_BIT 0x0000000C // CAN Bit Timing +#define CAN_O_INT 0x00000010 // CAN Interrupt +#define CAN_O_TST 0x00000014 // CAN Test +#define CAN_O_BRPE 0x00000018 // CAN Baud Rate Prescaler + // Extension +#define CAN_O_IF1CRQ 0x00000020 // CAN IF1 Command Request +#define CAN_O_IF1CMSK 0x00000024 // CAN IF1 Command Mask +#define CAN_O_IF1MSK1 0x00000028 // CAN IF1 Mask 1 +#define CAN_O_IF1MSK2 0x0000002C // CAN IF1 Mask 2 +#define CAN_O_IF1ARB1 0x00000030 // CAN IF1 Arbitration 1 +#define CAN_O_IF1ARB2 0x00000034 // CAN IF1 Arbitration 2 +#define CAN_O_IF1MCTL 0x00000038 // CAN IF1 Message Control +#define CAN_O_IF1DA1 0x0000003C // CAN IF1 Data A1 +#define CAN_O_IF1DA2 0x00000040 // CAN IF1 Data A2 +#define CAN_O_IF1DB1 0x00000044 // CAN IF1 Data B1 +#define CAN_O_IF1DB2 0x00000048 // CAN IF1 Data B2 +#define CAN_O_IF2CRQ 0x00000080 // CAN IF2 Command Request +#define CAN_O_IF2CMSK 0x00000084 // CAN IF2 Command Mask +#define CAN_O_IF2MSK1 0x00000088 // CAN IF2 Mask 1 +#define CAN_O_IF2MSK2 0x0000008C // CAN IF2 Mask 2 +#define CAN_O_IF2ARB1 0x00000090 // CAN IF2 Arbitration 1 +#define CAN_O_IF2ARB2 0x00000094 // CAN IF2 Arbitration 2 +#define CAN_O_IF2MCTL 0x00000098 // CAN IF2 Message Control +#define CAN_O_IF2DA1 0x0000009C // CAN IF2 Data A1 +#define CAN_O_IF2DA2 0x000000A0 // CAN IF2 Data A2 +#define CAN_O_IF2DB1 0x000000A4 // CAN IF2 Data B1 +#define CAN_O_IF2DB2 0x000000A8 // CAN IF2 Data B2 +#define CAN_O_TXRQ1 0x00000100 // CAN Transmission Request 1 +#define CAN_O_TXRQ2 0x00000104 // CAN Transmission Request 2 +#define CAN_O_NWDA1 0x00000120 // CAN New Data 1 +#define CAN_O_NWDA2 0x00000124 // CAN New Data 2 +#define CAN_O_MSG1INT 0x00000140 // CAN Message 1 Interrupt Pending +#define CAN_O_MSG2INT 0x00000144 // CAN Message 2 Interrupt Pending +#define CAN_O_MSG1VAL 0x00000160 // CAN Message 1 Valid +#define CAN_O_MSG2VAL 0x00000164 // CAN Message 2 Valid + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_CTL register. +// +//***************************************************************************** +#define CAN_CTL_TEST 0x00000080 // Test Mode Enable +#define CAN_CTL_CCE 0x00000040 // Configuration Change Enable +#define CAN_CTL_DAR 0x00000020 // Disable Automatic-Retransmission +#define CAN_CTL_EIE 0x00000008 // Error Interrupt Enable +#define CAN_CTL_SIE 0x00000004 // Status Interrupt Enable +#define CAN_CTL_IE 0x00000002 // CAN Interrupt Enable +#define CAN_CTL_INIT 0x00000001 // Initialization + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_STS register. +// +//***************************************************************************** +#define CAN_STS_BOFF 0x00000080 // Bus-Off Status +#define CAN_STS_EWARN 0x00000040 // Warning Status +#define CAN_STS_EPASS 0x00000020 // Error Passive +#define CAN_STS_RXOK 0x00000010 // Received a Message Successfully +#define CAN_STS_TXOK 0x00000008 // Transmitted a Message + // Successfully +#define CAN_STS_LEC_M 0x00000007 // Last Error Code +#define CAN_STS_LEC_NONE 0x00000000 // No Error +#define CAN_STS_LEC_STUFF 0x00000001 // Stuff Error +#define CAN_STS_LEC_FORM 0x00000002 // Format Error +#define CAN_STS_LEC_ACK 0x00000003 // ACK Error +#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 Error +#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 Error +#define CAN_STS_LEC_CRC 0x00000006 // CRC Error +#define CAN_STS_LEC_NOEVENT 0x00000007 // No Event + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_ERR register. +// +//***************************************************************************** +#define CAN_ERR_RP 0x00008000 // Received Error Passive +#define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter +#define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter +#define CAN_ERR_REC_S 8 +#define CAN_ERR_TEC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_BIT register. +// +//***************************************************************************** +#define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point +#define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample Point +#define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width +#define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescaler +#define CAN_BIT_TSEG2_S 12 +#define CAN_BIT_TSEG1_S 8 +#define CAN_BIT_SJW_S 6 +#define CAN_BIT_BRP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_INT register. +// +//***************************************************************************** +#define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier +#define CAN_INT_INTID_NONE 0x00000000 // No interrupt pending +#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_TST register. +// +//***************************************************************************** +#define CAN_TST_RX 0x00000080 // Receive Observation +#define CAN_TST_TX_M 0x00000060 // Transmit Control +#define CAN_TST_TX_CANCTL 0x00000000 // CAN Module Control +#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point +#define CAN_TST_TX_DOMINANT 0x00000040 // Driven Low +#define CAN_TST_TX_RECESSIVE 0x00000060 // Driven High +#define CAN_TST_LBACK 0x00000010 // Loopback Mode +#define CAN_TST_SILENT 0x00000008 // Silent Mode +#define CAN_TST_BASIC 0x00000004 // Basic Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_BRPE register. +// +//***************************************************************************** +#define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescaler Extension +#define CAN_BRPE_BRPE_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1CRQ register. +// +//***************************************************************************** +#define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag +#define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number +#define CAN_IF1CRQ_MNUM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1CMSK register. +// +//***************************************************************************** +#define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read +#define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits +#define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits +#define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits +#define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit +#define CAN_IF1CMSK_NEWDAT 0x00000004 // Access New Data +#define CAN_IF1CMSK_TXRQST 0x00000004 // Access Transmission Request +#define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3 +#define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1MSK1 register. +// +//***************************************************************************** +#define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask +#define CAN_IF1MSK1_IDMSK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1MSK2 register. +// +//***************************************************************************** +#define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier +#define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction +#define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask +#define CAN_IF1MSK2_IDMSK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1ARB1 register. +// +//***************************************************************************** +#define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier +#define CAN_IF1ARB1_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1ARB2 register. +// +//***************************************************************************** +#define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid +#define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier +#define CAN_IF1ARB2_DIR 0x00002000 // Message Direction +#define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier +#define CAN_IF1ARB2_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1MCTL register. +// +//***************************************************************************** +#define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data +#define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost +#define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending +#define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask +#define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable +#define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable +#define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable +#define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request +#define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer +#define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code +#define CAN_IF1MCTL_DLC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1DA1 register. +// +//***************************************************************************** +#define CAN_IF1DA1_DATA_M 0x0000FFFF // Data +#define CAN_IF1DA1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1DA2 register. +// +//***************************************************************************** +#define CAN_IF1DA2_DATA_M 0x0000FFFF // Data +#define CAN_IF1DA2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1DB1 register. +// +//***************************************************************************** +#define CAN_IF1DB1_DATA_M 0x0000FFFF // Data +#define CAN_IF1DB1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1DB2 register. +// +//***************************************************************************** +#define CAN_IF1DB2_DATA_M 0x0000FFFF // Data +#define CAN_IF1DB2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2CRQ register. +// +//***************************************************************************** +#define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag +#define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number +#define CAN_IF2CRQ_MNUM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2CMSK register. +// +//***************************************************************************** +#define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read +#define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits +#define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits +#define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits +#define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit +#define CAN_IF2CMSK_NEWDAT 0x00000004 // Access New Data +#define CAN_IF2CMSK_TXRQST 0x00000004 // Access Transmission Request +#define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3 +#define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2MSK1 register. +// +//***************************************************************************** +#define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask +#define CAN_IF2MSK1_IDMSK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2MSK2 register. +// +//***************************************************************************** +#define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier +#define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction +#define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask +#define CAN_IF2MSK2_IDMSK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2ARB1 register. +// +//***************************************************************************** +#define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier +#define CAN_IF2ARB1_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2ARB2 register. +// +//***************************************************************************** +#define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid +#define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier +#define CAN_IF2ARB2_DIR 0x00002000 // Message Direction +#define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier +#define CAN_IF2ARB2_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2MCTL register. +// +//***************************************************************************** +#define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data +#define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost +#define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending +#define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask +#define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable +#define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable +#define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable +#define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request +#define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer +#define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code +#define CAN_IF2MCTL_DLC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2DA1 register. +// +//***************************************************************************** +#define CAN_IF2DA1_DATA_M 0x0000FFFF // Data +#define CAN_IF2DA1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2DA2 register. +// +//***************************************************************************** +#define CAN_IF2DA2_DATA_M 0x0000FFFF // Data +#define CAN_IF2DA2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2DB1 register. +// +//***************************************************************************** +#define CAN_IF2DB1_DATA_M 0x0000FFFF // Data +#define CAN_IF2DB1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2DB2 register. +// +//***************************************************************************** +#define CAN_IF2DB2_DATA_M 0x0000FFFF // Data +#define CAN_IF2DB2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_TXRQ1 register. +// +//***************************************************************************** +#define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits +#define CAN_TXRQ1_TXRQST_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_TXRQ2 register. +// +//***************************************************************************** +#define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits +#define CAN_TXRQ2_TXRQST_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_NWDA1 register. +// +//***************************************************************************** +#define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits +#define CAN_NWDA1_NEWDAT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_NWDA2 register. +// +//***************************************************************************** +#define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits +#define CAN_NWDA2_NEWDAT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_MSG1INT register. +// +//***************************************************************************** +#define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits +#define CAN_MSG1INT_INTPND_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_MSG2INT register. +// +//***************************************************************************** +#define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits +#define CAN_MSG2INT_INTPND_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_MSG1VAL register. +// +//***************************************************************************** +#define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits +#define CAN_MSG1VAL_MSGVAL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_MSG2VAL register. +// +//***************************************************************************** +#define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits +#define CAN_MSG2VAL_MSGVAL_S 0 + +#endif // __HW_CAN_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_ccm.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_ccm.h new file mode 100644 index 0000000000000000000000000000000000000000..9664ceea75a5fd90c35b5755ff6249b61fb01b30 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_ccm.h @@ -0,0 +1,115 @@ +//***************************************************************************** +// +// hw_ccm.h - Macros used when accessing the CCM hardware. +// +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_CCM_H__ +#define __HW_CCM_H__ + +//***************************************************************************** +// +// The following are defines for the EC register offsets. +// +//***************************************************************************** +#define CCM_O_CRCCTRL 0x00000400 // CRC Control +#define CCM_O_CRCSEED 0x00000410 // CRC SEED/Context +#define CCM_O_CRCDIN 0x00000414 // CRC Data Input +#define CCM_O_CRCRSLTPP 0x00000418 // CRC Post Processing Result + +//***************************************************************************** +// +// The following are defines for the bit fields in the CCM_O_CRCCTRL register. +// +//***************************************************************************** +#define CCM_CRCCTRL_INIT_M 0x00006000 // CRC Initialization +#define CCM_CRCCTRL_INIT_SEED 0x00000000 // Use the CRCSEED register context + // as the starting value +#define CCM_CRCCTRL_INIT_0 0x00004000 // Initialize to all '0s' +#define CCM_CRCCTRL_INIT_1 0x00006000 // Initialize to all '1s' +#define CCM_CRCCTRL_SIZE 0x00001000 // Input Data Size +#define CCM_CRCCTRL_RESINV 0x00000200 // Result Inverse Enable +#define CCM_CRCCTRL_OBR 0x00000100 // Output Reverse Enable +#define CCM_CRCCTRL_BR 0x00000080 // Bit reverse enable +#define CCM_CRCCTRL_ENDIAN_M 0x00000030 // Endian Control +#define CCM_CRCCTRL_ENDIAN_SBHW 0x00000000 // Configuration unchanged. (B3, + // B2, B1, B0) +#define CCM_CRCCTRL_ENDIAN_SHW 0x00000010 // Bytes are swapped in half-words + // but half-words are not swapped + // (B2, B3, B0, B1) +#define CCM_CRCCTRL_ENDIAN_SHWNB \ + 0x00000020 // Half-words are swapped but bytes + // are not swapped in half-word. + // (B1, B0, B3, B2) +#define CCM_CRCCTRL_ENDIAN_SBSW 0x00000030 // Bytes are swapped in half-words + // and half-words are swapped. (B0, + // B1, B2, B3) +#define CCM_CRCCTRL_TYPE_M 0x0000000F // Operation Type +#define CCM_CRCCTRL_TYPE_P8055 0x00000000 // Polynomial 0x8005 +#define CCM_CRCCTRL_TYPE_P1021 0x00000001 // Polynomial 0x1021 +#define CCM_CRCCTRL_TYPE_P4C11DB7 \ + 0x00000002 // Polynomial 0x4C11DB7 +#define CCM_CRCCTRL_TYPE_P1EDC6F41 \ + 0x00000003 // Polynomial 0x1EDC6F41 +#define CCM_CRCCTRL_TYPE_TCPCHKSUM \ + 0x00000008 // TCP checksum + +//***************************************************************************** +// +// The following are defines for the bit fields in the CCM_O_CRCSEED register. +// +//***************************************************************************** +#define CCM_CRCSEED_SEED_M 0xFFFFFFFF // SEED/Context Value +#define CCM_CRCSEED_SEED_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CCM_O_CRCDIN register. +// +//***************************************************************************** +#define CCM_CRCDIN_DATAIN_M 0xFFFFFFFF // Data Input +#define CCM_CRCDIN_DATAIN_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CCM_O_CRCRSLTPP +// register. +// +//***************************************************************************** +#define CCM_CRCRSLTPP_RSLTPP_M 0xFFFFFFFF // Post Processing Result +#define CCM_CRCRSLTPP_RSLTPP_S 0 + +#endif // __HW_CCM_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_comp.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_comp.h new file mode 100644 index 0000000000000000000000000000000000000000..24616aa954f64c0f6c1255e6b63013e5864e406b --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_comp.h @@ -0,0 +1,211 @@ +//***************************************************************************** +// +// hw_comp.h - Macros used when accessing the comparator hardware. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_COMP_H__ +#define __HW_COMP_H__ + +//***************************************************************************** +// +// The following are defines for the Comparator register offsets. +// +//***************************************************************************** +#define COMP_O_ACMIS 0x00000000 // Analog Comparator Masked + // Interrupt Status +#define COMP_O_ACRIS 0x00000004 // Analog Comparator Raw Interrupt + // Status +#define COMP_O_ACINTEN 0x00000008 // Analog Comparator Interrupt + // Enable +#define COMP_O_ACREFCTL 0x00000010 // Analog Comparator Reference + // Voltage Control +#define COMP_O_ACSTAT0 0x00000020 // Analog Comparator Status 0 +#define COMP_O_ACCTL0 0x00000024 // Analog Comparator Control 0 +#define COMP_O_ACSTAT1 0x00000040 // Analog Comparator Status 1 +#define COMP_O_ACCTL1 0x00000044 // Analog Comparator Control 1 +#define COMP_O_ACSTAT2 0x00000060 // Analog Comparator Status 2 +#define COMP_O_ACCTL2 0x00000064 // Analog Comparator Control 2 +#define COMP_O_PP 0x00000FC0 // Analog Comparator Peripheral + // Properties + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACMIS register. +// +//***************************************************************************** +#define COMP_ACMIS_IN2 0x00000004 // Comparator 2 Masked Interrupt + // Status +#define COMP_ACMIS_IN1 0x00000002 // Comparator 1 Masked Interrupt + // Status +#define COMP_ACMIS_IN0 0x00000001 // Comparator 0 Masked Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACRIS register. +// +//***************************************************************************** +#define COMP_ACRIS_IN2 0x00000004 // Comparator 2 Interrupt Status +#define COMP_ACRIS_IN1 0x00000002 // Comparator 1 Interrupt Status +#define COMP_ACRIS_IN0 0x00000001 // Comparator 0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACINTEN register. +// +//***************************************************************************** +#define COMP_ACINTEN_IN2 0x00000004 // Comparator 2 Interrupt Enable +#define COMP_ACINTEN_IN1 0x00000002 // Comparator 1 Interrupt Enable +#define COMP_ACINTEN_IN0 0x00000001 // Comparator 0 Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACREFCTL +// register. +// +//***************************************************************************** +#define COMP_ACREFCTL_EN 0x00000200 // Resistor Ladder Enable +#define COMP_ACREFCTL_RNG 0x00000100 // Resistor Ladder Range +#define COMP_ACREFCTL_VREF_M 0x0000000F // Resistor Ladder Voltage Ref +#define COMP_ACREFCTL_VREF_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACSTAT0 register. +// +//***************************************************************************** +#define COMP_ACSTAT0_OVAL 0x00000002 // Comparator Output Value + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACCTL0 register. +// +//***************************************************************************** +#define COMP_ACCTL0_TOEN 0x00000800 // Trigger Output Enable +#define COMP_ACCTL0_ASRCP_M 0x00000600 // Analog Source Positive +#define COMP_ACCTL0_ASRCP_PIN 0x00000000 // Pin value of Cn+ +#define COMP_ACCTL0_ASRCP_PIN0 0x00000200 // Pin value of C0+ +#define COMP_ACCTL0_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_ACCTL0_TSLVAL 0x00000080 // Trigger Sense Level Value +#define COMP_ACCTL0_TSEN_M 0x00000060 // Trigger Sense +#define COMP_ACCTL0_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL +#define COMP_ACCTL0_TSEN_FALL 0x00000020 // Falling edge +#define COMP_ACCTL0_TSEN_RISE 0x00000040 // Rising edge +#define COMP_ACCTL0_TSEN_BOTH 0x00000060 // Either edge +#define COMP_ACCTL0_ISLVAL 0x00000010 // Interrupt Sense Level Value +#define COMP_ACCTL0_ISEN_M 0x0000000C // Interrupt Sense +#define COMP_ACCTL0_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL +#define COMP_ACCTL0_ISEN_FALL 0x00000004 // Falling edge +#define COMP_ACCTL0_ISEN_RISE 0x00000008 // Rising edge +#define COMP_ACCTL0_ISEN_BOTH 0x0000000C // Either edge +#define COMP_ACCTL0_CINV 0x00000002 // Comparator Output Invert + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACSTAT1 register. +// +//***************************************************************************** +#define COMP_ACSTAT1_OVAL 0x00000002 // Comparator Output Value + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACCTL1 register. +// +//***************************************************************************** +#define COMP_ACCTL1_TOEN 0x00000800 // Trigger Output Enable +#define COMP_ACCTL1_ASRCP_M 0x00000600 // Analog Source Positive +#define COMP_ACCTL1_ASRCP_PIN 0x00000000 // Pin value of Cn+ +#define COMP_ACCTL1_ASRCP_PIN0 0x00000200 // Pin value of C0+ +#define COMP_ACCTL1_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_ACCTL1_TSLVAL 0x00000080 // Trigger Sense Level Value +#define COMP_ACCTL1_TSEN_M 0x00000060 // Trigger Sense +#define COMP_ACCTL1_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL +#define COMP_ACCTL1_TSEN_FALL 0x00000020 // Falling edge +#define COMP_ACCTL1_TSEN_RISE 0x00000040 // Rising edge +#define COMP_ACCTL1_TSEN_BOTH 0x00000060 // Either edge +#define COMP_ACCTL1_ISLVAL 0x00000010 // Interrupt Sense Level Value +#define COMP_ACCTL1_ISEN_M 0x0000000C // Interrupt Sense +#define COMP_ACCTL1_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL +#define COMP_ACCTL1_ISEN_FALL 0x00000004 // Falling edge +#define COMP_ACCTL1_ISEN_RISE 0x00000008 // Rising edge +#define COMP_ACCTL1_ISEN_BOTH 0x0000000C // Either edge +#define COMP_ACCTL1_CINV 0x00000002 // Comparator Output Invert + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACSTAT2 register. +// +//***************************************************************************** +#define COMP_ACSTAT2_OVAL 0x00000002 // Comparator Output Value + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACCTL2 register. +// +//***************************************************************************** +#define COMP_ACCTL2_TOEN 0x00000800 // Trigger Output Enable +#define COMP_ACCTL2_ASRCP_M 0x00000600 // Analog Source Positive +#define COMP_ACCTL2_ASRCP_PIN 0x00000000 // Pin value of Cn+ +#define COMP_ACCTL2_ASRCP_PIN0 0x00000200 // Pin value of C0+ +#define COMP_ACCTL2_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_ACCTL2_TSLVAL 0x00000080 // Trigger Sense Level Value +#define COMP_ACCTL2_TSEN_M 0x00000060 // Trigger Sense +#define COMP_ACCTL2_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL +#define COMP_ACCTL2_TSEN_FALL 0x00000020 // Falling edge +#define COMP_ACCTL2_TSEN_RISE 0x00000040 // Rising edge +#define COMP_ACCTL2_TSEN_BOTH 0x00000060 // Either edge +#define COMP_ACCTL2_ISLVAL 0x00000010 // Interrupt Sense Level Value +#define COMP_ACCTL2_ISEN_M 0x0000000C // Interrupt Sense +#define COMP_ACCTL2_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL +#define COMP_ACCTL2_ISEN_FALL 0x00000004 // Falling edge +#define COMP_ACCTL2_ISEN_RISE 0x00000008 // Rising edge +#define COMP_ACCTL2_ISEN_BOTH 0x0000000C // Either edge +#define COMP_ACCTL2_CINV 0x00000002 // Comparator Output Invert + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_PP register. +// +//***************************************************************************** +#define COMP_PP_C2O 0x00040000 // Comparator Output 2 Present +#define COMP_PP_C1O 0x00020000 // Comparator Output 1 Present +#define COMP_PP_C0O 0x00010000 // Comparator Output 0 Present +#define COMP_PP_CMP2 0x00000004 // Comparator 2 Present +#define COMP_PP_CMP1 0x00000002 // Comparator 1 Present +#define COMP_PP_CMP0 0x00000001 // Comparator 0 Present + +#endif // __HW_COMP_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_des.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_des.h new file mode 100644 index 0000000000000000000000000000000000000000..775c3a745c77cd1c7cb051de186d2c1b4426ecaf --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_des.h @@ -0,0 +1,310 @@ +//***************************************************************************** +// +// hw_des.h - Macros used when accessing the DES hardware. +// +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_DES_H__ +#define __HW_DES_H__ + +//***************************************************************************** +// +// The following are defines for the DES register offsets. +// +//***************************************************************************** +#define DES_O_KEY3_L 0x00000000 // DES Key 3 LSW for 192-Bit Key +#define DES_O_KEY3_H 0x00000004 // DES Key 3 MSW for 192-Bit Key +#define DES_O_KEY2_L 0x00000008 // DES Key 2 LSW for 128-Bit Key +#define DES_O_KEY2_H 0x0000000C // DES Key 2 MSW for 128-Bit Key +#define DES_O_KEY1_L 0x00000010 // DES Key 1 LSW for 64-Bit Key +#define DES_O_KEY1_H 0x00000014 // DES Key 1 MSW for 64-Bit Key +#define DES_O_IV_L 0x00000018 // DES Initialization Vector +#define DES_O_IV_H 0x0000001C // DES Initialization Vector +#define DES_O_CTRL 0x00000020 // DES Control +#define DES_O_LENGTH 0x00000024 // DES Cryptographic Data Length +#define DES_O_DATA_L 0x00000028 // DES LSW Data RW +#define DES_O_DATA_H 0x0000002C // DES MSW Data RW +#define DES_O_REVISION 0x00000030 // DES Revision Number +#define DES_O_SYSCONFIG 0x00000034 // DES System Configuration +#define DES_O_SYSSTATUS 0x00000038 // DES System Status +#define DES_O_IRQSTATUS 0x0000003C // DES Interrupt Status +#define DES_O_IRQENABLE 0x00000040 // DES Interrupt Enable +#define DES_O_DIRTYBITS 0x00000044 // DES Dirty Bits +#define DES_O_DMAIM 0xFFFF8030 // DES DMA Interrupt Mask +#define DES_O_DMARIS 0xFFFF8034 // DES DMA Raw Interrupt Status +#define DES_O_DMAMIS 0xFFFF8038 // DES DMA Masked Interrupt Status +#define DES_O_DMAIC 0xFFFF803C // DES DMA Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_KEY3_L register. +// +//***************************************************************************** +#define DES_KEY3_L_KEY_M 0xFFFFFFFF // Key Data +#define DES_KEY3_L_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_KEY3_H register. +// +//***************************************************************************** +#define DES_KEY3_H_KEY_M 0xFFFFFFFF // Key Data +#define DES_KEY3_H_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_KEY2_L register. +// +//***************************************************************************** +#define DES_KEY2_L_KEY_M 0xFFFFFFFF // Key Data +#define DES_KEY2_L_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_KEY2_H register. +// +//***************************************************************************** +#define DES_KEY2_H_KEY_M 0xFFFFFFFF // Key Data +#define DES_KEY2_H_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_KEY1_L register. +// +//***************************************************************************** +#define DES_KEY1_L_KEY_M 0xFFFFFFFF // Key Data +#define DES_KEY1_L_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_KEY1_H register. +// +//***************************************************************************** +#define DES_KEY1_H_KEY_M 0xFFFFFFFF // Key Data +#define DES_KEY1_H_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_IV_L register. +// +//***************************************************************************** +#define DES_IV_L_M 0xFFFFFFFF // Initialization vector for CBC, + // CFB modes (LSW) +#define DES_IV_L_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_IV_H register. +// +//***************************************************************************** +#define DES_IV_H_M 0xFFFFFFFF // Initialization vector for CBC, + // CFB modes (MSW) +#define DES_IV_H_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_CTRL register. +// +//***************************************************************************** +#define DES_CTRL_CONTEXT 0x80000000 // If 1, this read-only status bit + // indicates that the context data + // registers can be overwritten and + // the host is permitted to write + // the next context +#define DES_CTRL_MODE_M 0x00000030 // Select CBC, ECB or CFB mode0x0: + // ECB mode0x1: CBC mode0x2: CFB + // mode0x3: reserved +#define DES_CTRL_TDES 0x00000008 // Select DES or triple DES + // encryption/decryption +#define DES_CTRL_DIRECTION 0x00000004 // Select encryption/decryption + // 0x0: decryption is selected0x1: + // Encryption is selected +#define DES_CTRL_INPUT_READY 0x00000002 // When 1, ready to encrypt/decrypt + // data +#define DES_CTRL_OUTPUT_READY 0x00000001 // When 1, Data decrypted/encrypted + // ready +#define DES_CTRL_MODE_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_LENGTH register. +// +//***************************************************************************** +#define DES_LENGTH_M 0xFFFFFFFF // Cryptographic data length in + // bytes for all modes +#define DES_LENGTH_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_DATA_L register. +// +//***************************************************************************** +#define DES_DATA_L_M 0xFFFFFFFF // Data for encryption/decryption, + // LSW +#define DES_DATA_L_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_DATA_H register. +// +//***************************************************************************** +#define DES_DATA_H_M 0xFFFFFFFF // Data for encryption/decryption, + // MSW +#define DES_DATA_H_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_REVISION register. +// +//***************************************************************************** +#define DES_REVISION_M 0xFFFFFFFF // Revision number +#define DES_REVISION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_SYSCONFIG +// register. +// +//***************************************************************************** +#define DES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \ + 0x00000080 // DMA Request Context In Enable +#define DES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \ + 0x00000040 // DMA Request Data Out Enable +#define DES_SYSCONFIG_DMA_REQ_DATA_IN_EN \ + 0x00000020 // DMA Request Data In Enable +#define DES_SYSCONFIG_SIDLE_M 0x0000000C // Sidle mode +#define DES_SYSCONFIG_SIDLE_FORCE \ + 0x00000000 // Force-idle mode +#define DES_SYSCONFIG_SOFTRESET 0x00000002 // Soft reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_SYSSTATUS +// register. +// +//***************************************************************************** +#define DES_SYSSTATUS_RESETDONE 0x00000001 // Reset Done + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_IRQSTATUS +// register. +// +//***************************************************************************** +#define DES_IRQSTATUS_DATA_OUT 0x00000004 // This bit indicates data output + // interrupt is active and triggers + // the interrupt output +#define DES_IRQSTATUS_DATA_IN 0x00000002 // This bit indicates data input + // interrupt is active and triggers + // the interrupt output +#define DES_IRQSTATUS_CONTEX_IN 0x00000001 // This bit indicates context + // interrupt is active and triggers + // the interrupt output + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_IRQENABLE +// register. +// +//***************************************************************************** +#define DES_IRQENABLE_M_DATA_OUT \ + 0x00000004 // If this bit is set to 1 the data + // output interrupt is enabled +#define DES_IRQENABLE_M_DATA_IN 0x00000002 // If this bit is set to 1 the data + // input interrupt is enabled +#define DES_IRQENABLE_M_CONTEX_IN \ + 0x00000001 // If this bit is set to 1 the + // context interrupt is enabled + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_DIRTYBITS +// register. +// +//***************************************************************************** +#define DES_DIRTYBITS_S_DIRTY 0x00000002 // This bit is set to 1 by the + // module if any of the DES_* + // registers is written +#define DES_DIRTYBITS_S_ACCESS 0x00000001 // This bit is set to 1 by the + // module if any of the DES_* + // registers is read + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_DMAIM register. +// +//***************************************************************************** +#define DES_DMAIM_DOUT 0x00000004 // Data Out DMA Done Interrupt Mask +#define DES_DMAIM_DIN 0x00000002 // Data In DMA Done Interrupt Mask +#define DES_DMAIM_CIN 0x00000001 // Context In DMA Done Interrupt + // Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_DMARIS register. +// +//***************************************************************************** +#define DES_DMARIS_DOUT 0x00000004 // Data Out DMA Done Raw Interrupt + // Status +#define DES_DMARIS_DIN 0x00000002 // Data In DMA Done Raw Interrupt + // Status +#define DES_DMARIS_CIN 0x00000001 // Context In DMA Done Raw + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_DMAMIS register. +// +//***************************************************************************** +#define DES_DMAMIS_DOUT 0x00000004 // Data Out DMA Done Masked + // Interrupt Status +#define DES_DMAMIS_DIN 0x00000002 // Data In DMA Done Masked + // Interrupt Status +#define DES_DMAMIS_CIN 0x00000001 // Context In DMA Done Raw + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_DMAIC register. +// +//***************************************************************************** +#define DES_DMAIC_DOUT 0x00000004 // Data Out DMA Done Interrupt + // Clear +#define DES_DMAIC_DIN 0x00000002 // Data In DMA Done Interrupt Clear +#define DES_DMAIC_CIN 0x00000001 // Context In DMA Done Raw + // Interrupt Status + +#endif // __HW_DES_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_eeprom.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_eeprom.h new file mode 100644 index 0000000000000000000000000000000000000000..2118c958e6823f022b2eb088a990defe73170c94 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_eeprom.h @@ -0,0 +1,251 @@ +//***************************************************************************** +// +// hw_eeprom.h - Macros used when accessing the EEPROM controller. +// +// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_EEPROM_H__ +#define __HW_EEPROM_H__ + +//***************************************************************************** +// +// The following are defines for the EEPROM register offsets. +// +//***************************************************************************** +#define EEPROM_EESIZE 0x400AF000 // EEPROM Size Information +#define EEPROM_EEBLOCK 0x400AF004 // EEPROM Current Block +#define EEPROM_EEOFFSET 0x400AF008 // EEPROM Current Offset +#define EEPROM_EERDWR 0x400AF010 // EEPROM Read-Write +#define EEPROM_EERDWRINC 0x400AF014 // EEPROM Read-Write with Increment +#define EEPROM_EEDONE 0x400AF018 // EEPROM Done Status +#define EEPROM_EESUPP 0x400AF01C // EEPROM Support Control and + // Status +#define EEPROM_EEUNLOCK 0x400AF020 // EEPROM Unlock +#define EEPROM_EEPROT 0x400AF030 // EEPROM Protection +#define EEPROM_EEPASS0 0x400AF034 // EEPROM Password +#define EEPROM_EEPASS1 0x400AF038 // EEPROM Password +#define EEPROM_EEPASS2 0x400AF03C // EEPROM Password +#define EEPROM_EEINT 0x400AF040 // EEPROM Interrupt +#define EEPROM_EEHIDE0 0x400AF050 // EEPROM Block Hide 0 +#define EEPROM_EEHIDE 0x400AF050 // EEPROM Block Hide +#define EEPROM_EEHIDE1 0x400AF054 // EEPROM Block Hide 1 +#define EEPROM_EEHIDE2 0x400AF058 // EEPROM Block Hide 2 +#define EEPROM_EEDBGME 0x400AF080 // EEPROM Debug Mass Erase +#define EEPROM_PP 0x400AFFC0 // EEPROM Peripheral Properties + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EESIZE register. +// +//***************************************************************************** +#define EEPROM_EESIZE_WORDCNT_M 0x0000FFFF // Number of 32-Bit Words +#define EEPROM_EESIZE_BLKCNT_M 0x07FF0000 // Number of 16-Word Blocks +#define EEPROM_EESIZE_WORDCNT_S 0 +#define EEPROM_EESIZE_BLKCNT_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEBLOCK register. +// +//***************************************************************************** +#define EEPROM_EEBLOCK_BLOCK_M 0x0000FFFF // Current Block +#define EEPROM_EEBLOCK_BLOCK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEOFFSET +// register. +// +//***************************************************************************** +#define EEPROM_EEOFFSET_OFFSET_M \ + 0x0000000F // Current Address Offset +#define EEPROM_EEOFFSET_OFFSET_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EERDWR register. +// +//***************************************************************************** +#define EEPROM_EERDWR_VALUE_M 0xFFFFFFFF // EEPROM Read or Write Data +#define EEPROM_EERDWR_VALUE_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EERDWRINC +// register. +// +//***************************************************************************** +#define EEPROM_EERDWRINC_VALUE_M \ + 0xFFFFFFFF // EEPROM Read or Write Data with + // Increment +#define EEPROM_EERDWRINC_VALUE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEDONE register. +// +//***************************************************************************** +#define EEPROM_EEDONE_WORKING 0x00000001 // EEPROM Working +#define EEPROM_EEDONE_WKERASE 0x00000004 // Working on an Erase +#define EEPROM_EEDONE_WKCOPY 0x00000008 // Working on a Copy +#define EEPROM_EEDONE_NOPERM 0x00000010 // Write Without Permission +#define EEPROM_EEDONE_WRBUSY 0x00000020 // Write Busy + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EESUPP register. +// +//***************************************************************************** +#define EEPROM_EESUPP_ERETRY 0x00000004 // Erase Must Be Retried +#define EEPROM_EESUPP_PRETRY 0x00000008 // Programming Must Be Retried + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEUNLOCK +// register. +// +//***************************************************************************** +#define EEPROM_EEUNLOCK_UNLOCK_M \ + 0xFFFFFFFF // EEPROM Unlock + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEPROT register. +// +//***************************************************************************** +#define EEPROM_EEPROT_PROT_M 0x00000007 // Protection Control +#define EEPROM_EEPROT_PROT_RWNPW \ + 0x00000000 // This setting is the default. If + // there is no password, the block + // is not protected and is readable + // and writable +#define EEPROM_EEPROT_PROT_RWPW 0x00000001 // If there is a password, the + // block is readable or writable + // only when unlocked +#define EEPROM_EEPROT_PROT_RONPW \ + 0x00000002 // If there is no password, the + // block is readable, not writable +#define EEPROM_EEPROT_ACC 0x00000008 // Access Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEPASS0 register. +// +//***************************************************************************** +#define EEPROM_EEPASS0_PASS_M 0xFFFFFFFF // Password +#define EEPROM_EEPASS0_PASS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEPASS1 register. +// +//***************************************************************************** +#define EEPROM_EEPASS1_PASS_M 0xFFFFFFFF // Password +#define EEPROM_EEPASS1_PASS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEPASS2 register. +// +//***************************************************************************** +#define EEPROM_EEPASS2_PASS_M 0xFFFFFFFF // Password +#define EEPROM_EEPASS2_PASS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEINT register. +// +//***************************************************************************** +#define EEPROM_EEINT_INT 0x00000001 // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEHIDE0 register. +// +//***************************************************************************** +#define EEPROM_EEHIDE0_HN_M 0xFFFFFFFE // Hide Block + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEHIDE register. +// +//***************************************************************************** +#define EEPROM_EEHIDE_HN_M 0xFFFFFFFE // Hide Block + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEHIDE1 register. +// +//***************************************************************************** +#define EEPROM_EEHIDE1_HN_M 0xFFFFFFFF // Hide Block + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEHIDE2 register. +// +//***************************************************************************** +#define EEPROM_EEHIDE2_HN_M 0xFFFFFFFF // Hide Block + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEDBGME register. +// +//***************************************************************************** +#define EEPROM_EEDBGME_ME 0x00000001 // Mass Erase +#define EEPROM_EEDBGME_KEY_M 0xFFFF0000 // Erase Key +#define EEPROM_EEDBGME_KEY_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_PP register. +// +//***************************************************************************** +#define EEPROM_PP_SIZE_M 0x0000FFFF // EEPROM Size +#define EEPROM_PP_SIZE_64 0x00000000 // 64 bytes of EEPROM +#define EEPROM_PP_SIZE_128 0x00000001 // 128 bytes of EEPROM +#define EEPROM_PP_SIZE_256 0x00000003 // 256 bytes of EEPROM +#define EEPROM_PP_SIZE_512 0x00000007 // 512 bytes of EEPROM +#define EEPROM_PP_SIZE_1K 0x0000000F // 1 KB of EEPROM +#define EEPROM_PP_SIZE_2K 0x0000001F // 2 KB of EEPROM +#define EEPROM_PP_SIZE_3K 0x0000003F // 3 KB of EEPROM +#define EEPROM_PP_SIZE_4K 0x0000007F // 4 KB of EEPROM +#define EEPROM_PP_SIZE_5K 0x000000FF // 5 KB of EEPROM +#define EEPROM_PP_SIZE_6K 0x000001FF // 6 KB of EEPROM +#define EEPROM_PP_SIZE_S 0 + +#endif // __HW_EEPROM_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_emac.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_emac.h new file mode 100644 index 0000000000000000000000000000000000000000..a836da9d2120d6d7e0abab5338608ad72ac7d9a7 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_emac.h @@ -0,0 +1,1874 @@ +//***************************************************************************** +// +// hw_emac.h - Macros used when accessing the EMAC hardware. +// +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_EMAC_H__ +#define __HW_EMAC_H__ + +//***************************************************************************** +// +// The following are defines for the EMAC register offsets. +// +//***************************************************************************** +#define EMAC_O_CFG 0x00000000 // Ethernet MAC Configuration +#define EMAC_O_FRAMEFLTR 0x00000004 // Ethernet MAC Frame Filter +#define EMAC_O_HASHTBLH 0x00000008 // Ethernet MAC Hash Table High +#define EMAC_O_HASHTBLL 0x0000000C // Ethernet MAC Hash Table Low +#define EMAC_O_MIIADDR 0x00000010 // Ethernet MAC MII Address +#define EMAC_O_MIIDATA 0x00000014 // Ethernet MAC MII Data Register +#define EMAC_O_FLOWCTL 0x00000018 // Ethernet MAC Flow Control +#define EMAC_O_VLANTG 0x0000001C // Ethernet MAC VLAN Tag +#define EMAC_O_STATUS 0x00000024 // Ethernet MAC Status +#define EMAC_O_RWUFF 0x00000028 // Ethernet MAC Remote Wake-Up + // Frame Filter +#define EMAC_O_PMTCTLSTAT 0x0000002C // Ethernet MAC PMT Control and + // Status Register +#define EMAC_O_LPICTLSTAT 0x00000030 // Ethernet MAC Low Power Idle + // Control and Status Register +#define EMAC_O_LPITIMERCTL 0x00000034 // Ethernet MAC Low Power Idle + // Timer Control Register +#define EMAC_O_RIS 0x00000038 // Ethernet MAC Raw Interrupt + // Status +#define EMAC_O_IM 0x0000003C // Ethernet MAC Interrupt Mask +#define EMAC_O_ADDR0H 0x00000040 // Ethernet MAC Address 0 High +#define EMAC_O_ADDR0L 0x00000044 // Ethernet MAC Address 0 Low + // Register +#define EMAC_O_ADDR1H 0x00000048 // Ethernet MAC Address 1 High +#define EMAC_O_ADDR1L 0x0000004C // Ethernet MAC Address 1 Low +#define EMAC_O_ADDR2H 0x00000050 // Ethernet MAC Address 2 High +#define EMAC_O_ADDR2L 0x00000054 // Ethernet MAC Address 2 Low +#define EMAC_O_ADDR3H 0x00000058 // Ethernet MAC Address 3 High +#define EMAC_O_ADDR3L 0x0000005C // Ethernet MAC Address 3 Low +#define EMAC_O_WDOGTO 0x000000DC // Ethernet MAC Watchdog Timeout +#define EMAC_O_MMCCTRL 0x00000100 // Ethernet MAC MMC Control +#define EMAC_O_MMCRXRIS 0x00000104 // Ethernet MAC MMC Receive Raw + // Interrupt Status +#define EMAC_O_MMCTXRIS 0x00000108 // Ethernet MAC MMC Transmit Raw + // Interrupt Status +#define EMAC_O_MMCRXIM 0x0000010C // Ethernet MAC MMC Receive + // Interrupt Mask +#define EMAC_O_MMCTXIM 0x00000110 // Ethernet MAC MMC Transmit + // Interrupt Mask +#define EMAC_O_TXCNTGB 0x00000118 // Ethernet MAC Transmit Frame + // Count for Good and Bad Frames +#define EMAC_O_TXCNTSCOL 0x0000014C // Ethernet MAC Transmit Frame + // Count for Frames Transmitted + // after Single Collision +#define EMAC_O_TXCNTMCOL 0x00000150 // Ethernet MAC Transmit Frame + // Count for Frames Transmitted + // after Multiple Collisions +#define EMAC_O_TXOCTCNTG 0x00000164 // Ethernet MAC Transmit Octet + // Count Good +#define EMAC_O_RXCNTGB 0x00000180 // Ethernet MAC Receive Frame Count + // for Good and Bad Frames +#define EMAC_O_RXCNTCRCERR 0x00000194 // Ethernet MAC Receive Frame Count + // for CRC Error Frames +#define EMAC_O_RXCNTALGNERR 0x00000198 // Ethernet MAC Receive Frame Count + // for Alignment Error Frames +#define EMAC_O_RXCNTGUNI 0x000001C4 // Ethernet MAC Receive Frame Count + // for Good Unicast Frames +#define EMAC_O_VLNINCREP 0x00000584 // Ethernet MAC VLAN Tag Inclusion + // or Replacement +#define EMAC_O_VLANHASH 0x00000588 // Ethernet MAC VLAN Hash Table +#define EMAC_O_TIMSTCTRL 0x00000700 // Ethernet MAC Timestamp Control +#define EMAC_O_SUBSECINC 0x00000704 // Ethernet MAC Sub-Second + // Increment +#define EMAC_O_TIMSEC 0x00000708 // Ethernet MAC System Time - + // Seconds +#define EMAC_O_TIMNANO 0x0000070C // Ethernet MAC System Time - + // Nanoseconds +#define EMAC_O_TIMSECU 0x00000710 // Ethernet MAC System Time - + // Seconds Update +#define EMAC_O_TIMNANOU 0x00000714 // Ethernet MAC System Time - + // Nanoseconds Update +#define EMAC_O_TIMADD 0x00000718 // Ethernet MAC Timestamp Addend +#define EMAC_O_TARGSEC 0x0000071C // Ethernet MAC Target Time Seconds +#define EMAC_O_TARGNANO 0x00000720 // Ethernet MAC Target Time + // Nanoseconds +#define EMAC_O_HWORDSEC 0x00000724 // Ethernet MAC System Time-Higher + // Word Seconds +#define EMAC_O_TIMSTAT 0x00000728 // Ethernet MAC Timestamp Status +#define EMAC_O_PPSCTRL 0x0000072C // Ethernet MAC PPS Control +#define EMAC_O_PPS0INTVL 0x00000760 // Ethernet MAC PPS0 Interval +#define EMAC_O_PPS0WIDTH 0x00000764 // Ethernet MAC PPS0 Width +#define EMAC_O_DMABUSMOD 0x00000C00 // Ethernet MAC DMA Bus Mode +#define EMAC_O_TXPOLLD 0x00000C04 // Ethernet MAC Transmit Poll + // Demand +#define EMAC_O_RXPOLLD 0x00000C08 // Ethernet MAC Receive Poll Demand +#define EMAC_O_RXDLADDR 0x00000C0C // Ethernet MAC Receive Descriptor + // List Address +#define EMAC_O_TXDLADDR 0x00000C10 // Ethernet MAC Transmit Descriptor + // List Address +#define EMAC_O_DMARIS 0x00000C14 // Ethernet MAC DMA Interrupt + // Status +#define EMAC_O_DMAOPMODE 0x00000C18 // Ethernet MAC DMA Operation Mode +#define EMAC_O_DMAIM 0x00000C1C // Ethernet MAC DMA Interrupt Mask + // Register +#define EMAC_O_MFBOC 0x00000C20 // Ethernet MAC Missed Frame and + // Buffer Overflow Counter +#define EMAC_O_RXINTWDT 0x00000C24 // Ethernet MAC Receive Interrupt + // Watchdog Timer +#define EMAC_O_HOSTXDESC 0x00000C48 // Ethernet MAC Current Host + // Transmit Descriptor +#define EMAC_O_HOSRXDESC 0x00000C4C // Ethernet MAC Current Host + // Receive Descriptor +#define EMAC_O_HOSTXBA 0x00000C50 // Ethernet MAC Current Host + // Transmit Buffer Address +#define EMAC_O_HOSRXBA 0x00000C54 // Ethernet MAC Current Host + // Receive Buffer Address +#define EMAC_O_PP 0x00000FC0 // Ethernet MAC Peripheral Property + // Register +#define EMAC_O_PC 0x00000FC4 // Ethernet MAC Peripheral + // Configuration Register +#define EMAC_O_CC 0x00000FC8 // Ethernet MAC Clock Configuration + // Register +#define EMAC_O_EPHYRIS 0x00000FD0 // Ethernet PHY Raw Interrupt + // Status +#define EMAC_O_EPHYIM 0x00000FD4 // Ethernet PHY Interrupt Mask +#define EMAC_O_EPHYMISC 0x00000FD8 // Ethernet PHY Masked Interrupt + // Status and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_CFG register. +// +//***************************************************************************** +#define EMAC_CFG_TWOKPEN 0x08000000 // IEEE 802 +#define EMAC_CFG_CST 0x02000000 // CRC Stripping for Type Frames +#define EMAC_CFG_WDDIS 0x00800000 // Watchdog Disable +#define EMAC_CFG_JD 0x00400000 // Jabber Disable +#define EMAC_CFG_JFEN 0x00100000 // Jumbo Frame Enable +#define EMAC_CFG_IFG_M 0x000E0000 // Inter-Frame Gap (IFG) +#define EMAC_CFG_IFG_96 0x00000000 // 96 bit times +#define EMAC_CFG_IFG_88 0x00020000 // 88 bit times +#define EMAC_CFG_IFG_80 0x00040000 // 80 bit times +#define EMAC_CFG_IFG_72 0x00060000 // 72 bit times +#define EMAC_CFG_IFG_64 0x00080000 // 64 bit times +#define EMAC_CFG_IFG_56 0x000A0000 // 56 bit times +#define EMAC_CFG_IFG_48 0x000C0000 // 48 bit times +#define EMAC_CFG_IFG_40 0x000E0000 // 40 bit times +#define EMAC_CFG_DISCRS 0x00010000 // Disable Carrier Sense During + // Transmission +#define EMAC_CFG_PS 0x00008000 // Port Select +#define EMAC_CFG_FES 0x00004000 // Speed +#define EMAC_CFG_DRO 0x00002000 // Disable Receive Own +#define EMAC_CFG_LOOPBM 0x00001000 // Loopback Mode +#define EMAC_CFG_DUPM 0x00000800 // Duplex Mode +#define EMAC_CFG_IPC 0x00000400 // Checksum Offload +#define EMAC_CFG_DR 0x00000200 // Disable Retry +#define EMAC_CFG_ACS 0x00000080 // Automatic Pad or CRC Stripping +#define EMAC_CFG_BL_M 0x00000060 // Back-Off Limit +#define EMAC_CFG_BL_1024 0x00000000 // k = min (n,10) +#define EMAC_CFG_BL_256 0x00000020 // k = min (n,8) +#define EMAC_CFG_BL_8 0x00000040 // k = min (n,4) +#define EMAC_CFG_BL_2 0x00000060 // k = min (n,1) +#define EMAC_CFG_DC 0x00000010 // Deferral Check +#define EMAC_CFG_TE 0x00000008 // Transmitter Enable +#define EMAC_CFG_RE 0x00000004 // Receiver Enable +#define EMAC_CFG_PRELEN_M 0x00000003 // Preamble Length for Transmit + // Frames +#define EMAC_CFG_PRELEN_7 0x00000000 // 7 bytes of preamble +#define EMAC_CFG_PRELEN_5 0x00000001 // 5 bytes of preamble +#define EMAC_CFG_PRELEN_3 0x00000002 // 3 bytes of preamble + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_FRAMEFLTR +// register. +// +//***************************************************************************** +#define EMAC_FRAMEFLTR_RA 0x80000000 // Receive All +#define EMAC_FRAMEFLTR_VTFE 0x00010000 // VLAN Tag Filter Enable +#define EMAC_FRAMEFLTR_HPF 0x00000400 // Hash or Perfect Filter +#define EMAC_FRAMEFLTR_SAF 0x00000200 // Source Address Filter Enable +#define EMAC_FRAMEFLTR_SAIF 0x00000100 // Source Address (SA) Inverse + // Filtering +#define EMAC_FRAMEFLTR_PCF_M 0x000000C0 // Pass Control Frames +#define EMAC_FRAMEFLTR_PCF_ALL 0x00000000 // The MAC filters all control + // frames from reaching application +#define EMAC_FRAMEFLTR_PCF_PAUSE \ + 0x00000040 // MAC forwards all control frames + // except PAUSE control frames to + // application even if they fail + // the address filter +#define EMAC_FRAMEFLTR_PCF_NONE 0x00000080 // MAC forwards all control frames + // to application even if they fail + // the address Filter +#define EMAC_FRAMEFLTR_PCF_ADDR 0x000000C0 // MAC forwards control frames that + // pass the address Filter +#define EMAC_FRAMEFLTR_DBF 0x00000020 // Disable Broadcast Frames +#define EMAC_FRAMEFLTR_PM 0x00000010 // Pass All Multicast +#define EMAC_FRAMEFLTR_DAIF 0x00000008 // Destination Address (DA) Inverse + // Filtering +#define EMAC_FRAMEFLTR_HMC 0x00000004 // Hash Multicast +#define EMAC_FRAMEFLTR_HUC 0x00000002 // Hash Unicast +#define EMAC_FRAMEFLTR_PR 0x00000001 // Promiscuous Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_HASHTBLH +// register. +// +//***************************************************************************** +#define EMAC_HASHTBLH_HTH_M 0xFFFFFFFF // Hash Table High +#define EMAC_HASHTBLH_HTH_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_HASHTBLL +// register. +// +//***************************************************************************** +#define EMAC_HASHTBLL_HTL_M 0xFFFFFFFF // Hash Table Low +#define EMAC_HASHTBLL_HTL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_MIIADDR register. +// +//***************************************************************************** +#define EMAC_MIIADDR_PLA_M 0x0000F800 // Physical Layer Address +#define EMAC_MIIADDR_MII_M 0x000007C0 // MII Register +#define EMAC_MIIADDR_CR_M 0x0000003C // Clock Reference Frequency + // Selection +#define EMAC_MIIADDR_CR_60_100 0x00000000 // The frequency of the System + // Clock is 60 to 100 MHz providing + // a MDIO clock of SYSCLK/42 +#define EMAC_MIIADDR_CR_100_150 0x00000004 // The frequency of the System + // Clock is 100 to 150 MHz + // providing a MDIO clock of + // SYSCLK/62 +#define EMAC_MIIADDR_CR_20_35 0x00000008 // The frequency of the System + // Clock is 20-35 MHz providing a + // MDIO clock of System Clock/16 +#define EMAC_MIIADDR_CR_35_60 0x0000000C // The frequency of the System + // Clock is 35 to 60 MHz providing + // a MDIO clock of System Clock/26 +#define EMAC_MIIADDR_MIIW 0x00000002 // MII Write +#define EMAC_MIIADDR_MIIB 0x00000001 // MII Busy +#define EMAC_MIIADDR_PLA_S 11 +#define EMAC_MIIADDR_MII_S 6 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_MIIDATA register. +// +//***************************************************************************** +#define EMAC_MIIDATA_DATA_M 0x0000FFFF // MII Data +#define EMAC_MIIDATA_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_FLOWCTL register. +// +//***************************************************************************** +#define EMAC_FLOWCTL_PT_M 0xFFFF0000 // Pause Time +#define EMAC_FLOWCTL_DZQP 0x00000080 // Disable Zero-Quanta Pause +#define EMAC_FLOWCTL_UP 0x00000008 // Unicast Pause Frame Detect +#define EMAC_FLOWCTL_RFE 0x00000004 // Receive Flow Control Enable +#define EMAC_FLOWCTL_TFE 0x00000002 // Transmit Flow Control Enable +#define EMAC_FLOWCTL_FCBBPA 0x00000001 // Flow Control Busy or + // Back-pressure Activate +#define EMAC_FLOWCTL_PT_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_VLANTG register. +// +//***************************************************************************** +#define EMAC_VLANTG_VTHM 0x00080000 // VLAN Tag Hash Table Match Enable +#define EMAC_VLANTG_ESVL 0x00040000 // Enable S-VLAN +#define EMAC_VLANTG_VTIM 0x00020000 // VLAN Tag Inverse Match Enable +#define EMAC_VLANTG_ETV 0x00010000 // Enable 12-Bit VLAN Tag + // Comparison +#define EMAC_VLANTG_VL_M 0x0000FFFF // VLAN Tag Identifier for Receive + // Frames +#define EMAC_VLANTG_VL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_STATUS register. +// +//***************************************************************************** +#define EMAC_STATUS_TXFF 0x02000000 // TX/RX Controller TX FIFO Full + // Status +#define EMAC_STATUS_TXFE 0x01000000 // TX/RX Controller TX FIFO Not + // Empty Status +#define EMAC_STATUS_TWC 0x00400000 // TX/RX Controller TX FIFO Write + // Controller Active Status +#define EMAC_STATUS_TRC_M 0x00300000 // TX/RX Controller's TX FIFO Read + // Controller Status +#define EMAC_STATUS_TRC_IDLE 0x00000000 // IDLE state +#define EMAC_STATUS_TRC_READ 0x00100000 // READ state (transferring data to + // MAC transmitter) +#define EMAC_STATUS_TRC_WAIT 0x00200000 // Waiting for TX Status from MAC + // transmitter +#define EMAC_STATUS_TRC_WRFLUSH 0x00300000 // Writing the received TX Status + // or flushing the TX FIFO +#define EMAC_STATUS_TXPAUSED 0x00080000 // MAC Transmitter PAUSE +#define EMAC_STATUS_TFC_M 0x00060000 // MAC Transmit Frame Controller + // Status +#define EMAC_STATUS_TFC_IDLE 0x00000000 // IDLE state +#define EMAC_STATUS_TFC_STATUS 0x00020000 // Waiting for status of previous + // frame or IFG or backoff period + // to be over +#define EMAC_STATUS_TFC_PAUSE 0x00040000 // Generating and transmitting a + // PAUSE control frame (in the + // full-duplex mode) +#define EMAC_STATUS_TFC_INPUT 0x00060000 // Transferring input frame for + // transmission +#define EMAC_STATUS_TPE 0x00010000 // MAC MII Transmit Protocol Engine + // Status +#define EMAC_STATUS_RXF_M 0x00000300 // TX/RX Controller RX FIFO + // Fill-level Status +#define EMAC_STATUS_RXF_EMPTY 0x00000000 // RX FIFO Empty +#define EMAC_STATUS_RXF_BELOW 0x00000100 // RX FIFO fill level is below the + // flow-control deactivate + // threshold +#define EMAC_STATUS_RXF_ABOVE 0x00000200 // RX FIFO fill level is above the + // flow-control activate threshold +#define EMAC_STATUS_RXF_FULL 0x00000300 // RX FIFO Full +#define EMAC_STATUS_RRC_M 0x00000060 // TX/RX Controller Read Controller + // State +#define EMAC_STATUS_RRC_IDLE 0x00000000 // IDLE state +#define EMAC_STATUS_RRC_STATUS 0x00000020 // Reading frame data +#define EMAC_STATUS_RRC_DATA 0x00000040 // Reading frame status (or + // timestamp) +#define EMAC_STATUS_RRC_FLUSH 0x00000060 // Flushing the frame data and + // status +#define EMAC_STATUS_RWC 0x00000010 // TX/RX Controller RX FIFO Write + // Controller Active Status +#define EMAC_STATUS_RFCFC_M 0x00000006 // MAC Receive Frame Controller + // FIFO Status +#define EMAC_STATUS_RPE 0x00000001 // MAC MII Receive Protocol Engine + // Status +#define EMAC_STATUS_RFCFC_S 1 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_RWUFF register. +// +//***************************************************************************** +#define EMAC_RWUFF_WAKEUPFIL_M 0xFFFFFFFF // Remote Wake-Up Frame Filter +#define EMAC_RWUFF_WAKEUPFIL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_PMTCTLSTAT +// register. +// +//***************************************************************************** +#define EMAC_PMTCTLSTAT_WUPFRRST \ + 0x80000000 // Wake-Up Frame Filter Register + // Pointer Reset +#define EMAC_PMTCTLSTAT_RWKPTR_M \ + 0x07000000 // Remote Wake-Up FIFO Pointer +#define EMAC_PMTCTLSTAT_GLBLUCAST \ + 0x00000200 // Global Unicast +#define EMAC_PMTCTLSTAT_WUPRX 0x00000040 // Wake-Up Frame Received +#define EMAC_PMTCTLSTAT_MGKPRX 0x00000020 // Magic Packet Received +#define EMAC_PMTCTLSTAT_WUPFREN 0x00000004 // Wake-Up Frame Enable +#define EMAC_PMTCTLSTAT_MGKPKTEN \ + 0x00000002 // Magic Packet Enable +#define EMAC_PMTCTLSTAT_PWRDWN 0x00000001 // Power Down +#define EMAC_PMTCTLSTAT_RWKPTR_S \ + 24 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_LPICTLSTAT +// register. +// +//***************************************************************************** +#define EMAC_LPICTLSTAT_LPITXA 0x00080000 // LPI TX Automate +#define EMAC_LPICTLSTAT_PLSEN 0x00040000 // PHY Link Status Enable +#define EMAC_LPICTLSTAT_PLS 0x00020000 // PHY Link Status +#define EMAC_LPICTLSTAT_LPIEN 0x00010000 // LPI Enable +#define EMAC_LPICTLSTAT_RLPIST 0x00000200 // Receive LPI State +#define EMAC_LPICTLSTAT_TLPIST 0x00000100 // Transmit LPI State +#define EMAC_LPICTLSTAT_RLPIEX 0x00000008 // Receive LPI Exit +#define EMAC_LPICTLSTAT_RLPIEN 0x00000004 // Receive LPI Entry +#define EMAC_LPICTLSTAT_TLPIEX 0x00000002 // Transmit LPI Exit +#define EMAC_LPICTLSTAT_TLPIEN 0x00000001 // Transmit LPI Entry + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_LPITIMERCTL +// register. +// +//***************************************************************************** +#define EMAC_LPITIMERCTL_LST_M 0x03FF0000 // Low Power Idle LS Timer +#define EMAC_LPITIMERCTL_LST_S 16 +#define EMAC_LPITIMERCTL_TWT_M 0x0000FFFF // Low Power Idle TW Timer +#define EMAC_LPITIMERCTL_TWT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_RIS register. +// +//***************************************************************************** +#define EMAC_RIS_LPI 0x00000400 // LPI Interrupt Status +#define EMAC_RIS_TS 0x00000200 // Timestamp Interrupt Status +#define EMAC_RIS_MMCTX 0x00000040 // MMC Transmit Interrupt Status +#define EMAC_RIS_MMCRX 0x00000020 // MMC Receive Interrupt Status +#define EMAC_RIS_MMC 0x00000010 // MMC Interrupt Status +#define EMAC_RIS_PMT 0x00000008 // PMT Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_IM register. +// +//***************************************************************************** +#define EMAC_IM_LPI 0x00000400 // LPI Interrupt Mask +#define EMAC_IM_TSI 0x00000200 // Timestamp Interrupt Mask +#define EMAC_IM_PMT 0x00000008 // PMT Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_ADDR0H register. +// +//***************************************************************************** +#define EMAC_ADDR0H_AE 0x80000000 // Address Enable +#define EMAC_ADDR0H_ADDRHI_M 0x0000FFFF // MAC Address0 [47:32] +#define EMAC_ADDR0H_ADDRHI_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_ADDR0L register. +// +//***************************************************************************** +#define EMAC_ADDR0L_ADDRLO_M 0xFFFFFFFF // MAC Address0 [31:0] +#define EMAC_ADDR0L_ADDRLO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_ADDR1H register. +// +//***************************************************************************** +#define EMAC_ADDR1H_AE 0x80000000 // Address Enable +#define EMAC_ADDR1H_SA 0x40000000 // Source Address +#define EMAC_ADDR1H_MBC_M 0x3F000000 // Mask Byte Control +#define EMAC_ADDR1H_ADDRHI_M 0x0000FFFF // MAC Address1 [47:32] +#define EMAC_ADDR1H_MBC_S 24 +#define EMAC_ADDR1H_ADDRHI_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_ADDR1L register. +// +//***************************************************************************** +#define EMAC_ADDR1L_ADDRLO_M 0xFFFFFFFF // MAC Address1 [31:0] +#define EMAC_ADDR1L_ADDRLO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_ADDR2H register. +// +//***************************************************************************** +#define EMAC_ADDR2H_AE 0x80000000 // Address Enable +#define EMAC_ADDR2H_SA 0x40000000 // Source Address +#define EMAC_ADDR2H_MBC_M 0x3F000000 // Mask Byte Control +#define EMAC_ADDR2H_ADDRHI_M 0x0000FFFF // MAC Address2 [47:32] +#define EMAC_ADDR2H_MBC_S 24 +#define EMAC_ADDR2H_ADDRHI_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_ADDR2L register. +// +//***************************************************************************** +#define EMAC_ADDR2L_ADDRLO_M 0xFFFFFFFF // MAC Address2 [31:0] +#define EMAC_ADDR2L_ADDRLO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_ADDR3H register. +// +//***************************************************************************** +#define EMAC_ADDR3H_AE 0x80000000 // Address Enable +#define EMAC_ADDR3H_SA 0x40000000 // Source Address +#define EMAC_ADDR3H_MBC_M 0x3F000000 // Mask Byte Control +#define EMAC_ADDR3H_ADDRHI_M 0x0000FFFF // MAC Address3 [47:32] +#define EMAC_ADDR3H_MBC_S 24 +#define EMAC_ADDR3H_ADDRHI_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_ADDR3L register. +// +//***************************************************************************** +#define EMAC_ADDR3L_ADDRLO_M 0xFFFFFFFF // MAC Address3 [31:0] +#define EMAC_ADDR3L_ADDRLO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_WDOGTO register. +// +//***************************************************************************** +#define EMAC_WDOGTO_PWE 0x00010000 // Programmable Watchdog Enable +#define EMAC_WDOGTO_WTO_M 0x00003FFF // Watchdog Timeout +#define EMAC_WDOGTO_WTO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_MMCCTRL register. +// +//***************************************************************************** +#define EMAC_MMCCTRL_UCDBC 0x00000100 // Update MMC Counters for Dropped + // Broadcast Frames +#define EMAC_MMCCTRL_CNTPRSTLVL 0x00000020 // Full/Half Preset Level Value +#define EMAC_MMCCTRL_CNTPRST 0x00000010 // Counters Preset +#define EMAC_MMCCTRL_CNTFREEZ 0x00000008 // MMC Counter Freeze +#define EMAC_MMCCTRL_RSTONRD 0x00000004 // Reset on Read +#define EMAC_MMCCTRL_CNTSTPRO 0x00000002 // Counters Stop Rollover +#define EMAC_MMCCTRL_CNTRST 0x00000001 // Counters Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_MMCRXRIS +// register. +// +//***************************************************************************** +#define EMAC_MMCRXRIS_UCGF 0x00020000 // MMC Receive Unicast Good Frame + // Counter Interrupt Status +#define EMAC_MMCRXRIS_ALGNERR 0x00000040 // MMC Receive Alignment Error + // Frame Counter Interrupt Status +#define EMAC_MMCRXRIS_CRCERR 0x00000020 // MMC Receive CRC Error Frame + // Counter Interrupt Status +#define EMAC_MMCRXRIS_GBF 0x00000001 // MMC Receive Good Bad Frame + // Counter Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_MMCTXRIS +// register. +// +//***************************************************************************** +#define EMAC_MMCTXRIS_OCTCNT 0x00100000 // Octet Counter Interrupt Status +#define EMAC_MMCTXRIS_MCOLLGF 0x00008000 // MMC Transmit Multiple Collision + // Good Frame Counter Interrupt + // Status +#define EMAC_MMCTXRIS_SCOLLGF 0x00004000 // MMC Transmit Single Collision + // Good Frame Counter Interrupt + // Status +#define EMAC_MMCTXRIS_GBF 0x00000002 // MMC Transmit Good Bad Frame + // Counter Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_MMCRXIM register. +// +//***************************************************************************** +#define EMAC_MMCRXIM_UCGF 0x00020000 // MMC Receive Unicast Good Frame + // Counter Interrupt Mask +#define EMAC_MMCRXIM_ALGNERR 0x00000040 // MMC Receive Alignment Error + // Frame Counter Interrupt Mask +#define EMAC_MMCRXIM_CRCERR 0x00000020 // MMC Receive CRC Error Frame + // Counter Interrupt Mask +#define EMAC_MMCRXIM_GBF 0x00000001 // MMC Receive Good Bad Frame + // Counter Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_MMCTXIM register. +// +//***************************************************************************** +#define EMAC_MMCTXIM_OCTCNT 0x00100000 // MMC Transmit Good Octet Counter + // Interrupt Mask +#define EMAC_MMCTXIM_MCOLLGF 0x00008000 // MMC Transmit Multiple Collision + // Good Frame Counter Interrupt + // Mask +#define EMAC_MMCTXIM_SCOLLGF 0x00004000 // MMC Transmit Single Collision + // Good Frame Counter Interrupt + // Mask +#define EMAC_MMCTXIM_GBF 0x00000002 // MMC Transmit Good Bad Frame + // Counter Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_TXCNTGB register. +// +//***************************************************************************** +#define EMAC_TXCNTGB_TXFRMGB_M 0xFFFFFFFF // This field indicates the number + // of good and bad frames + // transmitted, exclusive of + // retried frames +#define EMAC_TXCNTGB_TXFRMGB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_TXCNTSCOL +// register. +// +//***************************************************************************** +#define EMAC_TXCNTSCOL_TXSNGLCOLG_M \ + 0xFFFFFFFF // This field indicates the number + // of successfully transmitted + // frames after a single collision + // in the half-duplex mode +#define EMAC_TXCNTSCOL_TXSNGLCOLG_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_TXCNTMCOL +// register. +// +//***************************************************************************** +#define EMAC_TXCNTMCOL_TXMULTCOLG_M \ + 0xFFFFFFFF // This field indicates the number + // of successfully transmitted + // frames after multiple collisions + // in the half-duplex mode +#define EMAC_TXCNTMCOL_TXMULTCOLG_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_TXOCTCNTG +// register. +// +//***************************************************************************** +#define EMAC_TXOCTCNTG_TXOCTG_M 0xFFFFFFFF // This field indicates the number + // of bytes transmitted, exclusive + // of preamble, in good frames +#define EMAC_TXOCTCNTG_TXOCTG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_RXCNTGB register. +// +//***************************************************************************** +#define EMAC_RXCNTGB_RXFRMGB_M 0xFFFFFFFF // This field indicates the number + // of received good and bad frames +#define EMAC_RXCNTGB_RXFRMGB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_RXCNTCRCERR +// register. +// +//***************************************************************************** +#define EMAC_RXCNTCRCERR_RXCRCERR_M \ + 0xFFFFFFFF // This field indicates the number + // of frames received with CRC + // error +#define EMAC_RXCNTCRCERR_RXCRCERR_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_RXCNTALGNERR +// register. +// +//***************************************************************************** +#define EMAC_RXCNTALGNERR_RXALGNERR_M \ + 0xFFFFFFFF // This field indicates the number + // of frames received with + // alignment (dribble) error +#define EMAC_RXCNTALGNERR_RXALGNERR_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_RXCNTGUNI +// register. +// +//***************************************************************************** +#define EMAC_RXCNTGUNI_RXUCASTG_M \ + 0xFFFFFFFF // This field indicates the number + // of received good unicast frames +#define EMAC_RXCNTGUNI_RXUCASTG_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_VLNINCREP +// register. +// +//***************************************************************************** +#define EMAC_VLNINCREP_CSVL 0x00080000 // C-VLAN or S-VLAN +#define EMAC_VLNINCREP_VLP 0x00040000 // VLAN Priority Control +#define EMAC_VLNINCREP_VLC_M 0x00030000 // VLAN Tag Control in Transmit + // Frames +#define EMAC_VLNINCREP_VLC_NONE 0x00000000 // No VLAN tag deletion, insertion, + // or replacement +#define EMAC_VLNINCREP_VLC_TAGDEL \ + 0x00010000 // VLAN tag deletion +#define EMAC_VLNINCREP_VLC_TAGINS \ + 0x00020000 // VLAN tag insertion +#define EMAC_VLNINCREP_VLC_TAGREP \ + 0x00030000 // VLAN tag replacement +#define EMAC_VLNINCREP_VLT_M 0x0000FFFF // VLAN Tag for Transmit Frames +#define EMAC_VLNINCREP_VLT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_VLANHASH +// register. +// +//***************************************************************************** +#define EMAC_VLANHASH_VLHT_M 0x0000FFFF // VLAN Hash Table +#define EMAC_VLANHASH_VLHT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_TIMSTCTRL +// register. +// +//***************************************************************************** +#define EMAC_TIMSTCTRL_PTPFLTR 0x00040000 // Enable MAC address for PTP Frame + // Filtering +#define EMAC_TIMSTCTRL_SELPTP_M 0x00030000 // Select PTP packets for Taking + // Snapshots +#define EMAC_TIMSTCTRL_TSMAST 0x00008000 // Enable Snapshot for Messages + // Relevant to Master +#define EMAC_TIMSTCTRL_TSEVNT 0x00004000 // Enable Timestamp Snapshot for + // Event Messages +#define EMAC_TIMSTCTRL_PTPIPV4 0x00002000 // Enable Processing of PTP Frames + // Sent over IPv4-UDP +#define EMAC_TIMSTCTRL_PTPIPV6 0x00001000 // Enable Processing of PTP Frames + // Sent Over IPv6-UDP +#define EMAC_TIMSTCTRL_PTPETH 0x00000800 // Enable Processing of PTP Over + // Ethernet Frames +#define EMAC_TIMSTCTRL_PTPVER2 0x00000400 // Enable PTP Packet Processing For + // Version 2 Format +#define EMAC_TIMSTCTRL_DGTLBIN 0x00000200 // Timestamp Digital or Binary + // Rollover Control +#define EMAC_TIMSTCTRL_ALLF 0x00000100 // Enable Timestamp For All Frames +#define EMAC_TIMSTCTRL_ADDREGUP 0x00000020 // Addend Register Update +#define EMAC_TIMSTCTRL_INTTRIG 0x00000010 // Timestamp Interrupt Trigger + // Enable +#define EMAC_TIMSTCTRL_TSUPDT 0x00000008 // Timestamp Update +#define EMAC_TIMSTCTRL_TSINIT 0x00000004 // Timestamp Initialize +#define EMAC_TIMSTCTRL_TSFCUPDT 0x00000002 // Timestamp Fine or Coarse Update +#define EMAC_TIMSTCTRL_TSEN 0x00000001 // Timestamp Enable +#define EMAC_TIMSTCTRL_SELPTP_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_SUBSECINC +// register. +// +//***************************************************************************** +#define EMAC_SUBSECINC_SSINC_M 0x000000FF // Sub-second Increment Value +#define EMAC_SUBSECINC_SSINC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_TIMSEC register. +// +//***************************************************************************** +#define EMAC_TIMSEC_TSS_M 0xFFFFFFFF // Timestamp Second +#define EMAC_TIMSEC_TSS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_TIMNANO register. +// +//***************************************************************************** +#define EMAC_TIMNANO_TSSS_M 0x7FFFFFFF // Timestamp Sub-Seconds +#define EMAC_TIMNANO_TSSS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_TIMSECU register. +// +//***************************************************************************** +#define EMAC_TIMSECU_TSS_M 0xFFFFFFFF // Timestamp Second +#define EMAC_TIMSECU_TSS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_TIMNANOU +// register. +// +//***************************************************************************** +#define EMAC_TIMNANOU_ADDSUB 0x80000000 // Add or subtract time +#define EMAC_TIMNANOU_TSSS_M 0x7FFFFFFF // Timestamp Sub-Second +#define EMAC_TIMNANOU_TSSS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_TIMADD register. +// +//***************************************************************************** +#define EMAC_TIMADD_TSAR_M 0xFFFFFFFF // Timestamp Addend Register +#define EMAC_TIMADD_TSAR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_TARGSEC register. +// +//***************************************************************************** +#define EMAC_TARGSEC_TSTR_M 0xFFFFFFFF // Target Time Seconds Register +#define EMAC_TARGSEC_TSTR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_TARGNANO +// register. +// +//***************************************************************************** +#define EMAC_TARGNANO_TRGTBUSY 0x80000000 // Target Time Register Busy +#define EMAC_TARGNANO_TTSLO_M 0x7FFFFFFF // Target Timestamp Low Register +#define EMAC_TARGNANO_TTSLO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_HWORDSEC +// register. +// +//***************************************************************************** +#define EMAC_HWORDSEC_TSHWR_M 0x0000FFFF // Target Timestamp Higher Word + // Register +#define EMAC_HWORDSEC_TSHWR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_TIMSTAT register. +// +//***************************************************************************** +#define EMAC_TIMSTAT_TSTARGT 0x00000002 // Timestamp Target Time Reached +#define EMAC_TIMSTAT_TSSOVF 0x00000001 // Timestamp Seconds Overflow + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_PPSCTRL register. +// +//***************************************************************************** +#define EMAC_PPSCTRL_TRGMODS0_M 0x00000060 // Target Time Register Mode for + // PPS0 Output +#define EMAC_PPSCTRL_TRGMODS0_INTONLY \ + 0x00000000 // Indicates that the Target Time + // registers are programmed only + // for generating the interrupt + // event +#define EMAC_PPSCTRL_TRGMODS0_INTPPS0 \ + 0x00000040 // Indicates that the Target Time + // registers are programmed for + // generating the interrupt event + // and starting or stopping the + // generation of the EN0PPS output + // signal +#define EMAC_PPSCTRL_TRGMODS0_PPS0ONLY \ + 0x00000060 // Indicates that the Target Time + // registers are programmed only + // for starting or stopping the + // generation of the EN0PPS output + // signal. No interrupt is asserted +#define EMAC_PPSCTRL_PPSEN0 0x00000010 // Flexible PPS Output Mode Enable +#define EMAC_PPSCTRL_PPSCTRL_M 0x0000000F // EN0PPS Output Frequency Control + // (PPSCTRL) or Command Control + // (PPSCMD) + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_PPS0INTVL +// register. +// +//***************************************************************************** +#define EMAC_PPS0INTVL_PPS0INT_M \ + 0xFFFFFFFF // PPS0 Output Signal Interval +#define EMAC_PPS0INTVL_PPS0INT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_PPS0WIDTH +// register. +// +//***************************************************************************** +#define EMAC_PPS0WIDTH_M 0xFFFFFFFF // EN0PPS Output Signal Width +#define EMAC_PPS0WIDTH_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_DMABUSMOD +// register. +// +//***************************************************************************** +#define EMAC_DMABUSMOD_RIB 0x80000000 // Rebuild Burst +#define EMAC_DMABUSMOD_TXPR 0x08000000 // Transmit Priority +#define EMAC_DMABUSMOD_MB 0x04000000 // Mixed Burst +#define EMAC_DMABUSMOD_AAL 0x02000000 // Address Aligned Beats +#define EMAC_DMABUSMOD_8XPBL 0x01000000 // 8 x Programmable Burst Length + // (PBL) Mode +#define EMAC_DMABUSMOD_USP 0x00800000 // Use Separate Programmable Burst + // Length (PBL) +#define EMAC_DMABUSMOD_RPBL_M 0x007E0000 // RX DMA Programmable Burst Length + // (PBL) +#define EMAC_DMABUSMOD_FB 0x00010000 // Fixed Burst +#define EMAC_DMABUSMOD_PR_M 0x0000C000 // Priority Ratio +#define EMAC_DMABUSMOD_PBL_M 0x00003F00 // Programmable Burst Length +#define EMAC_DMABUSMOD_ATDS 0x00000080 // Alternate Descriptor Size +#define EMAC_DMABUSMOD_DSL_M 0x0000007C // Descriptor Skip Length +#define EMAC_DMABUSMOD_DA 0x00000002 // DMA Arbitration Scheme +#define EMAC_DMABUSMOD_SWR 0x00000001 // DMA Software Reset +#define EMAC_DMABUSMOD_RPBL_S 17 +#define EMAC_DMABUSMOD_PR_S 14 +#define EMAC_DMABUSMOD_PBL_S 8 +#define EMAC_DMABUSMOD_DSL_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_TXPOLLD register. +// +//***************************************************************************** +#define EMAC_TXPOLLD_TPD_M 0xFFFFFFFF // Transmit Poll Demand +#define EMAC_TXPOLLD_TPD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_RXPOLLD register. +// +//***************************************************************************** +#define EMAC_RXPOLLD_RPD_M 0xFFFFFFFF // Receive Poll Demand +#define EMAC_RXPOLLD_RPD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_RXDLADDR +// register. +// +//***************************************************************************** +#define EMAC_RXDLADDR_STRXLIST_M \ + 0xFFFFFFFC // Start of Receive List +#define EMAC_RXDLADDR_STRXLIST_S \ + 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_TXDLADDR +// register. +// +//***************************************************************************** +#define EMAC_TXDLADDR_TXDLADDR_M \ + 0xFFFFFFFC // Start of Transmit List Base + // Address +#define EMAC_TXDLADDR_TXDLADDR_S \ + 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_DMARIS register. +// +//***************************************************************************** +#define EMAC_DMARIS_LPI 0x40000000 // LPI Trigger Interrupt Status +#define EMAC_DMARIS_TT 0x20000000 // Timestamp Trigger Interrupt + // Status +#define EMAC_DMARIS_PMT 0x10000000 // MAC PMT Interrupt Status +#define EMAC_DMARIS_MMC 0x08000000 // MAC MMC Interrupt +#define EMAC_DMARIS_AE_M 0x03800000 // Access Error +#define EMAC_DMARIS_AE_RXDMAWD 0x00000000 // Error during RX DMA Write Data + // Transfer +#define EMAC_DMARIS_AE_TXDMARD 0x01800000 // Error during TX DMA Read Data + // Transfer +#define EMAC_DMARIS_AE_RXDMADW 0x02000000 // Error during RX DMA Descriptor + // Write Access +#define EMAC_DMARIS_AE_TXDMADW 0x02800000 // Error during TX DMA Descriptor + // Write Access +#define EMAC_DMARIS_AE_RXDMADR 0x03000000 // Error during RX DMA Descriptor + // Read Access +#define EMAC_DMARIS_AE_TXDMADR 0x03800000 // Error during TX DMA Descriptor + // Read Access +#define EMAC_DMARIS_TS_M 0x00700000 // Transmit Process State +#define EMAC_DMARIS_TS_STOP 0x00000000 // Stopped; Reset or Stop transmit + // command processed +#define EMAC_DMARIS_TS_RUNTXTD 0x00100000 // Running; Fetching transmit + // transfer descriptor +#define EMAC_DMARIS_TS_STATUS 0x00200000 // Running; Waiting for status +#define EMAC_DMARIS_TS_RUNTX 0x00300000 // Running; Reading data from host + // memory buffer and queuing it to + // transmit buffer (TX FIFO) +#define EMAC_DMARIS_TS_TSTAMP 0x00400000 // Writing Timestamp +#define EMAC_DMARIS_TS_SUSPEND 0x00600000 // Suspended; Transmit descriptor + // unavailable or transmit buffer + // underflow +#define EMAC_DMARIS_TS_RUNCTD 0x00700000 // Running; Closing transmit + // descriptor +#define EMAC_DMARIS_RS_M 0x000E0000 // Received Process State +#define EMAC_DMARIS_RS_STOP 0x00000000 // Stopped: Reset or stop receive + // command issued +#define EMAC_DMARIS_RS_RUNRXTD 0x00020000 // Running: Fetching receive + // transfer descriptor +#define EMAC_DMARIS_RS_RUNRXD 0x00060000 // Running: Waiting for receive + // packet +#define EMAC_DMARIS_RS_SUSPEND 0x00080000 // Suspended: Receive descriptor + // unavailable +#define EMAC_DMARIS_RS_RUNCRD 0x000A0000 // Running: Closing receive + // descriptor +#define EMAC_DMARIS_RS_TSWS 0x000C0000 // Writing Timestamp +#define EMAC_DMARIS_RS_RUNTXD 0x000E0000 // Running: Transferring the + // receive packet data from receive + // buffer to host memory +#define EMAC_DMARIS_NIS 0x00010000 // Normal Interrupt Summary +#define EMAC_DMARIS_AIS 0x00008000 // Abnormal Interrupt Summary +#define EMAC_DMARIS_ERI 0x00004000 // Early Receive Interrupt +#define EMAC_DMARIS_FBI 0x00002000 // Fatal Bus Error Interrupt +#define EMAC_DMARIS_ETI 0x00000400 // Early Transmit Interrupt +#define EMAC_DMARIS_RWT 0x00000200 // Receive Watchdog Timeout +#define EMAC_DMARIS_RPS 0x00000100 // Receive Process Stopped +#define EMAC_DMARIS_RU 0x00000080 // Receive Buffer Unavailable +#define EMAC_DMARIS_RI 0x00000040 // Receive Interrupt +#define EMAC_DMARIS_UNF 0x00000020 // Transmit Underflow +#define EMAC_DMARIS_OVF 0x00000010 // Receive Overflow +#define EMAC_DMARIS_TJT 0x00000008 // Transmit Jabber Timeout +#define EMAC_DMARIS_TU 0x00000004 // Transmit Buffer Unavailable +#define EMAC_DMARIS_TPS 0x00000002 // Transmit Process Stopped +#define EMAC_DMARIS_TI 0x00000001 // Transmit Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_DMAOPMODE +// register. +// +//***************************************************************************** +#define EMAC_DMAOPMODE_DT 0x04000000 // Disable Dropping of TCP/IP + // Checksum Error Frames +#define EMAC_DMAOPMODE_RSF 0x02000000 // Receive Store and Forward +#define EMAC_DMAOPMODE_DFF 0x01000000 // Disable Flushing of Received + // Frames +#define EMAC_DMAOPMODE_TSF 0x00200000 // Transmit Store and Forward +#define EMAC_DMAOPMODE_FTF 0x00100000 // Flush Transmit FIFO +#define EMAC_DMAOPMODE_TTC_M 0x0001C000 // Transmit Threshold Control +#define EMAC_DMAOPMODE_TTC_64 0x00000000 // 64 bytes +#define EMAC_DMAOPMODE_TTC_128 0x00004000 // 128 bytes +#define EMAC_DMAOPMODE_TTC_192 0x00008000 // 192 bytes +#define EMAC_DMAOPMODE_TTC_256 0x0000C000 // 256 bytes +#define EMAC_DMAOPMODE_TTC_40 0x00010000 // 40 bytes +#define EMAC_DMAOPMODE_TTC_32 0x00014000 // 32 bytes +#define EMAC_DMAOPMODE_TTC_24 0x00018000 // 24 bytes +#define EMAC_DMAOPMODE_TTC_16 0x0001C000 // 16 bytes +#define EMAC_DMAOPMODE_ST 0x00002000 // Start or Stop Transmission + // Command +#define EMAC_DMAOPMODE_FEF 0x00000080 // Forward Error Frames +#define EMAC_DMAOPMODE_FUF 0x00000040 // Forward Undersized Good Frames +#define EMAC_DMAOPMODE_DGF 0x00000020 // Drop Giant Frame Enable +#define EMAC_DMAOPMODE_RTC_M 0x00000018 // Receive Threshold Control +#define EMAC_DMAOPMODE_RTC_64 0x00000000 // 64 bytes +#define EMAC_DMAOPMODE_RTC_32 0x00000008 // 32 bytes +#define EMAC_DMAOPMODE_RTC_96 0x00000010 // 96 bytes +#define EMAC_DMAOPMODE_RTC_128 0x00000018 // 128 bytes +#define EMAC_DMAOPMODE_OSF 0x00000004 // Operate on Second Frame +#define EMAC_DMAOPMODE_SR 0x00000002 // Start or Stop Receive + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_DMAIM register. +// +//***************************************************************************** +#define EMAC_DMAIM_NIE 0x00010000 // Normal Interrupt Summary Enable +#define EMAC_DMAIM_AIE 0x00008000 // Abnormal Interrupt Summary + // Enable +#define EMAC_DMAIM_ERE 0x00004000 // Early Receive Interrupt Enable +#define EMAC_DMAIM_FBE 0x00002000 // Fatal Bus Error Enable +#define EMAC_DMAIM_ETE 0x00000400 // Early Transmit Interrupt Enable +#define EMAC_DMAIM_RWE 0x00000200 // Receive Watchdog Timeout Enable +#define EMAC_DMAIM_RSE 0x00000100 // Receive Stopped Enable +#define EMAC_DMAIM_RUE 0x00000080 // Receive Buffer Unavailable + // Enable +#define EMAC_DMAIM_RIE 0x00000040 // Receive Interrupt Enable +#define EMAC_DMAIM_UNE 0x00000020 // Underflow Interrupt Enable +#define EMAC_DMAIM_OVE 0x00000010 // Overflow Interrupt Enable +#define EMAC_DMAIM_TJE 0x00000008 // Transmit Jabber Timeout Enable +#define EMAC_DMAIM_TUE 0x00000004 // Transmit Buffer Unvailable + // Enable +#define EMAC_DMAIM_TSE 0x00000002 // Transmit Stopped Enable +#define EMAC_DMAIM_TIE 0x00000001 // Transmit Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_MFBOC register. +// +//***************************************************************************** +#define EMAC_MFBOC_OVFCNTOVF 0x10000000 // Overflow Bit for FIFO Overflow + // Counter +#define EMAC_MFBOC_OVFFRMCNT_M 0x0FFE0000 // Overflow Frame Counter +#define EMAC_MFBOC_MISCNTOVF 0x00010000 // Overflow bit for Missed Frame + // Counter +#define EMAC_MFBOC_MISFRMCNT_M 0x0000FFFF // Missed Frame Counter +#define EMAC_MFBOC_OVFFRMCNT_S 17 +#define EMAC_MFBOC_MISFRMCNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_RXINTWDT +// register. +// +//***************************************************************************** +#define EMAC_RXINTWDT_RIWT_M 0x000000FF // Receive Interrupt Watchdog Timer + // Count +#define EMAC_RXINTWDT_RIWT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_HOSTXDESC +// register. +// +//***************************************************************************** +#define EMAC_HOSTXDESC_CURTXDESC_M \ + 0xFFFFFFFF // Host Transmit Descriptor Address + // Pointer +#define EMAC_HOSTXDESC_CURTXDESC_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_HOSRXDESC +// register. +// +//***************************************************************************** +#define EMAC_HOSRXDESC_CURRXDESC_M \ + 0xFFFFFFFF // Host Receive Descriptor Address + // Pointer +#define EMAC_HOSRXDESC_CURRXDESC_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_HOSTXBA register. +// +//***************************************************************************** +#define EMAC_HOSTXBA_CURTXBUFA_M \ + 0xFFFFFFFF // Host Transmit Buffer Address + // Pointer +#define EMAC_HOSTXBA_CURTXBUFA_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_HOSRXBA register. +// +//***************************************************************************** +#define EMAC_HOSRXBA_CURRXBUFA_M \ + 0xFFFFFFFF // Host Receive Buffer Address + // Pointer +#define EMAC_HOSRXBA_CURRXBUFA_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_PP register. +// +//***************************************************************************** +#define EMAC_PP_MACTYPE_M 0x00000700 // Ethernet MAC Type +#define EMAC_PP_MACTYPE_1 0x00000100 // Tiva TM4E129x-class MAC +#define EMAC_PP_PHYTYPE_M 0x00000007 // Ethernet PHY Type +#define EMAC_PP_PHYTYPE_NONE 0x00000000 // No PHY +#define EMAC_PP_PHYTYPE_1 0x00000003 // Snowflake class PHY + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_PC register. +// +//***************************************************************************** +#define EMAC_PC_PHYEXT 0x80000000 // PHY Select +#define EMAC_PC_PINTFS_M 0x70000000 // Ethernet Interface Select +#define EMAC_PC_PINTFS_IMII 0x00000000 // MII (default) Used for internal + // PHY or external PHY connected + // via MII +#define EMAC_PC_PINTFS_RMII 0x40000000 // RMII: Used for external PHY + // connected via RMII +#define EMAC_PC_DIGRESTART 0x02000000 // PHY Soft Restart +#define EMAC_PC_NIBDETDIS 0x01000000 // Odd Nibble TXER Detection + // Disable +#define EMAC_PC_RXERIDLE 0x00800000 // RXER Detection During Idle +#define EMAC_PC_ISOMIILL 0x00400000 // Isolate MII in Link Loss +#define EMAC_PC_LRR 0x00200000 // Link Loss Recovery +#define EMAC_PC_TDRRUN 0x00100000 // TDR Auto Run +#define EMAC_PC_FASTLDMODE_M 0x000F8000 // Fast Link Down Mode +#define EMAC_PC_POLSWAP 0x00004000 // Polarity Swap +#define EMAC_PC_MDISWAP 0x00002000 // MDI Swap +#define EMAC_PC_RBSTMDIX 0x00001000 // Robust Auto MDI-X +#define EMAC_PC_FASTMDIX 0x00000800 // Fast Auto MDI-X +#define EMAC_PC_MDIXEN 0x00000400 // MDIX Enable +#define EMAC_PC_FASTRXDV 0x00000200 // Fast RXDV Detection +#define EMAC_PC_FASTLUPD 0x00000100 // FAST Link-Up in Parallel Detect +#define EMAC_PC_EXTFD 0x00000080 // Extended Full Duplex Ability +#define EMAC_PC_FASTANEN 0x00000040 // Fast Auto Negotiation Enable +#define EMAC_PC_FASTANSEL_M 0x00000030 // Fast Auto Negotiation Select +#define EMAC_PC_ANEN 0x00000008 // Auto Negotiation Enable +#define EMAC_PC_ANMODE_M 0x00000006 // Auto Negotiation Mode +#define EMAC_PC_ANMODE_10HD 0x00000000 // When ANEN = 0x0, the mode is + // 10Base-T, Half-Duplex +#define EMAC_PC_ANMODE_10FD 0x00000002 // When ANEN = 0x0, the mode is + // 10Base-T, Full-Duplex +#define EMAC_PC_ANMODE_100HD 0x00000004 // When ANEN = 0x0, the mode is + // 100Base-TX, Half-Duplex +#define EMAC_PC_ANMODE_100FD 0x00000006 // When ANEN = 0x0, the mode is + // 100Base-TX, Full-Duplex +#define EMAC_PC_PHYHOLD 0x00000001 // Ethernet PHY Hold +#define EMAC_PC_FASTLDMODE_S 15 +#define EMAC_PC_FASTANSEL_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_CC register. +// +//***************************************************************************** +#define EMAC_CC_PTPCEN 0x00040000 // PTP Clock Reference Enable +#define EMAC_CC_POL 0x00020000 // LED Polarity Control +#define EMAC_CC_CLKEN 0x00010000 // EN0RREF_CLK Signal Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_EPHYRIS register. +// +//***************************************************************************** +#define EMAC_EPHYRIS_INT 0x00000001 // Ethernet PHY Raw Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_EPHYIM register. +// +//***************************************************************************** +#define EMAC_EPHYIM_INT 0x00000001 // Ethernet PHY Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_EPHYMISC +// register. +// +//***************************************************************************** +#define EMAC_EPHYMISC_INT 0x00000001 // Ethernet PHY Status and Clear + // register + +//***************************************************************************** +// +// The following are defines for the EPHY register offsets. +// +//***************************************************************************** +#define EPHY_BMCR 0x00000000 // Ethernet PHY Basic Mode Control +#define EPHY_BMSR 0x00000001 // Ethernet PHY Basic Mode Status +#define EPHY_ID1 0x00000002 // Ethernet PHY Identifier Register + // 1 +#define EPHY_ID2 0x00000003 // Ethernet PHY Identifier Register + // 2 +#define EPHY_ANA 0x00000004 // Ethernet PHY Auto-Negotiation + // Advertisement +#define EPHY_ANLPA 0x00000005 // Ethernet PHY Auto-Negotiation + // Link Partner Ability +#define EPHY_ANER 0x00000006 // Ethernet PHY Auto-Negotiation + // Expansion +#define EPHY_ANNPTR 0x00000007 // Ethernet PHY Auto-Negotiation + // Next Page TX +#define EPHY_ANLNPTR 0x00000008 // Ethernet PHY Auto-Negotiation + // Link Partner Ability Next Page +#define EPHY_CFG1 0x00000009 // Ethernet PHY Configuration 1 +#define EPHY_CFG2 0x0000000A // Ethernet PHY Configuration 2 +#define EPHY_CFG3 0x0000000B // Ethernet PHY Configuration 3 +#define EPHY_REGCTL 0x0000000D // Ethernet PHY Register Control +#define EPHY_ADDAR 0x0000000E // Ethernet PHY Address or Data +#define EPHY_STS 0x00000010 // Ethernet PHY Status +#define EPHY_SCR 0x00000011 // Ethernet PHY Specific Control +#define EPHY_MISR1 0x00000012 // Ethernet PHY MII Interrupt + // Status 1 +#define EPHY_MISR2 0x00000013 // Ethernet PHY MII Interrupt + // Status 2 +#define EPHY_FCSCR 0x00000014 // Ethernet PHY False Carrier Sense + // Counter +#define EPHY_RXERCNT 0x00000015 // Ethernet PHY Receive Error Count +#define EPHY_BISTCR 0x00000016 // Ethernet PHY BIST Control +#define EPHY_LEDCR 0x00000018 // Ethernet PHY LED Control +#define EPHY_CTL 0x00000019 // Ethernet PHY Control +#define EPHY_10BTSC 0x0000001A // Ethernet PHY 10Base-T + // Status/Control - MR26 +#define EPHY_BICSR1 0x0000001B // Ethernet PHY BIST Control and + // Status 1 +#define EPHY_BICSR2 0x0000001C // Ethernet PHY BIST Control and + // Status 2 +#define EPHY_CDCR 0x0000001E // Ethernet PHY Cable Diagnostic + // Control +#define EPHY_RCR 0x0000001F // Ethernet PHY Reset Control +#define EPHY_LEDCFG 0x00000025 // Ethernet PHY LED Configuration + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_BMCR register. +// +//***************************************************************************** +#define EPHY_BMCR_MIIRESET 0x00008000 // MII Register reset +#define EPHY_BMCR_MIILOOPBK 0x00004000 // MII Loopback +#define EPHY_BMCR_SPEED 0x00002000 // Speed Select +#define EPHY_BMCR_ANEN 0x00001000 // Auto-Negotiate Enable +#define EPHY_BMCR_PWRDWN 0x00000800 // Power Down +#define EPHY_BMCR_ISOLATE 0x00000400 // Port Isolate +#define EPHY_BMCR_RESTARTAN 0x00000200 // Restart Auto-Negotiation +#define EPHY_BMCR_DUPLEXM 0x00000100 // Duplex Mode +#define EPHY_BMCR_COLLTST 0x00000080 // Collision Test + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_BMSR register. +// +//***************************************************************************** +#define EPHY_BMSR_100BTXFD 0x00004000 // 100Base-TX Full Duplex Capable +#define EPHY_BMSR_100BTXHD 0x00002000 // 100Base-TX Half Duplex Capable +#define EPHY_BMSR_10BTFD 0x00001000 // 10 Base-T Full Duplex Capable +#define EPHY_BMSR_10BTHD 0x00000800 // 10 Base-T Half Duplex Capable +#define EPHY_BMSR_MFPRESUP 0x00000040 // Preamble Suppression Capable +#define EPHY_BMSR_ANC 0x00000020 // Auto-Negotiation Complete +#define EPHY_BMSR_RFAULT 0x00000010 // Remote Fault +#define EPHY_BMSR_ANEN 0x00000008 // Auto Negotiation Enabled +#define EPHY_BMSR_LINKSTAT 0x00000004 // Link Status +#define EPHY_BMSR_JABBER 0x00000002 // Jabber Detect +#define EPHY_BMSR_EXTEN 0x00000001 // Extended Capability Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_ID1 register. +// +//***************************************************************************** +#define EPHY_ID1_OUIMSB_M 0x0000FFFF // OUI Most Significant Bits +#define EPHY_ID1_OUIMSB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_ID2 register. +// +//***************************************************************************** +#define EPHY_ID2_OUILSB_M 0x0000FC00 // OUI Least Significant Bits +#define EPHY_ID2_VNDRMDL_M 0x000003F0 // Vendor Model Number +#define EPHY_ID2_MDLREV_M 0x0000000F // Model Revision Number +#define EPHY_ID2_OUILSB_S 10 +#define EPHY_ID2_VNDRMDL_S 4 +#define EPHY_ID2_MDLREV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_ANA register. +// +//***************************************************************************** +#define EPHY_ANA_NP 0x00008000 // Next Page Indication +#define EPHY_ANA_RF 0x00002000 // Remote Fault +#define EPHY_ANA_ASMDUP 0x00000800 // Asymmetric PAUSE support for + // Full Duplex Links +#define EPHY_ANA_PAUSE 0x00000400 // PAUSE Support for Full Duplex + // Links +#define EPHY_ANA_100BT4 0x00000200 // 100Base-T4 Support +#define EPHY_ANA_100BTXFD 0x00000100 // 100Base-TX Full Duplex Support +#define EPHY_ANA_100BTX 0x00000080 // 100Base-TX Support +#define EPHY_ANA_10BTFD 0x00000040 // 10Base-T Full Duplex Support +#define EPHY_ANA_10BT 0x00000020 // 10Base-T Support +#define EPHY_ANA_SELECT_M 0x0000001F // Protocol Selection +#define EPHY_ANA_SELECT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_ANLPA register. +// +//***************************************************************************** +#define EPHY_ANLPA_NP 0x00008000 // Next Page Indication +#define EPHY_ANLPA_ACK 0x00004000 // Acknowledge +#define EPHY_ANLPA_RF 0x00002000 // Remote Fault +#define EPHY_ANLPA_ASMDUP 0x00000800 // Asymmetric PAUSE +#define EPHY_ANLPA_PAUSE 0x00000400 // PAUSE +#define EPHY_ANLPA_100BT4 0x00000200 // 100Base-T4 Support +#define EPHY_ANLPA_100BTXFD 0x00000100 // 100Base-TX Full Duplex Support +#define EPHY_ANLPA_100BTX 0x00000080 // 100Base-TX Support +#define EPHY_ANLPA_10BTFD 0x00000040 // 10Base-T Full Duplex Support +#define EPHY_ANLPA_10BT 0x00000020 // 10Base-T Support +#define EPHY_ANLPA_SELECT_M 0x0000001F // Protocol Selection +#define EPHY_ANLPA_SELECT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_ANER register. +// +//***************************************************************************** +#define EPHY_ANER_PDF 0x00000010 // Parallel Detection Fault +#define EPHY_ANER_LPNPABLE 0x00000008 // Link Partner Next Page Able +#define EPHY_ANER_NPABLE 0x00000004 // Next Page Able +#define EPHY_ANER_PAGERX 0x00000002 // Link Code Word Page Received +#define EPHY_ANER_LPANABLE 0x00000001 // Link Partner Auto-Negotiation + // Able + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_ANNPTR register. +// +//***************************************************************************** +#define EPHY_ANNPTR_NP 0x00008000 // Next Page Indication +#define EPHY_ANNPTR_MP 0x00002000 // Message Page +#define EPHY_ANNPTR_ACK2 0x00001000 // Acknowledge 2 +#define EPHY_ANNPTR_TOGTX 0x00000800 // Toggle +#define EPHY_ANNPTR_CODE_M 0x000007FF // Code +#define EPHY_ANNPTR_CODE_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_ANLNPTR register. +// +//***************************************************************************** +#define EPHY_ANLNPTR_NP 0x00008000 // Next Page Indication +#define EPHY_ANLNPTR_ACK 0x00004000 // Acknowledge +#define EPHY_ANLNPTR_MP 0x00002000 // Message Page +#define EPHY_ANLNPTR_ACK2 0x00001000 // Acknowledge 2 +#define EPHY_ANLNPTR_TOG 0x00000800 // Toggle +#define EPHY_ANLNPTR_CODE_M 0x000007FF // Code +#define EPHY_ANLNPTR_CODE_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_CFG1 register. +// +//***************************************************************************** +#define EPHY_CFG1_DONE 0x00008000 // Configuration Done +#define EPHY_CFG1_TDRAR 0x00000100 // TDR Auto-Run at Link Down +#define EPHY_CFG1_LLR 0x00000080 // Link Loss Recovery +#define EPHY_CFG1_FAMDIX 0x00000040 // Fast Auto MDI/MDIX +#define EPHY_CFG1_RAMDIX 0x00000020 // Robust Auto MDI/MDIX +#define EPHY_CFG1_FASTANEN 0x00000010 // Fast Auto Negotiation Enable +#define EPHY_CFG1_FANSEL_M 0x0000000C // Fast Auto-Negotiation Select + // Configuration +#define EPHY_CFG1_FANSEL_BLT80 0x00000000 // Break Link Timer: 80 ms +#define EPHY_CFG1_FANSEL_BLT120 0x00000004 // Break Link Timer: 120 ms +#define EPHY_CFG1_FANSEL_BLT240 0x00000008 // Break Link Timer: 240 ms +#define EPHY_CFG1_FRXDVDET 0x00000002 // FAST RXDV Detection + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_CFG2 register. +// +//***************************************************************************** +#define EPHY_CFG2_FLUPPD 0x00000040 // Fast Link-Up in Parallel Detect + // Mode +#define EPHY_CFG2_EXTFD 0x00000020 // Extended Full-Duplex Ability +#define EPHY_CFG2_ENLEDLINK 0x00000010 // Enhanced LED Functionality +#define EPHY_CFG2_ISOMIILL 0x00000008 // Isolate MII outputs when + // Enhanced Link is not Achievable +#define EPHY_CFG2_RXERRIDLE 0x00000004 // Detection of Receive Symbol + // Error During IDLE State +#define EPHY_CFG2_ODDNDETDIS 0x00000002 // Detection of Transmit Error + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_CFG3 register. +// +//***************************************************************************** +#define EPHY_CFG3_POLSWAP 0x00000080 // Polarity Swap +#define EPHY_CFG3_MDIMDIXS 0x00000040 // MDI/MDIX Swap +#define EPHY_CFG3_FLDWNM_M 0x0000001F // Fast Link Down Modes +#define EPHY_CFG3_FLDWNM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_REGCTL register. +// +//***************************************************************************** +#define EPHY_REGCTL_FUNC_M 0x0000C000 // Function +#define EPHY_REGCTL_FUNC_ADDR 0x00000000 // Address +#define EPHY_REGCTL_FUNC_DATANI 0x00004000 // Data, no post increment +#define EPHY_REGCTL_FUNC_DATAPIRW \ + 0x00008000 // Data, post increment on read and + // write +#define EPHY_REGCTL_FUNC_DATAPIWO \ + 0x0000C000 // Data, post increment on write + // only +#define EPHY_REGCTL_DEVAD_M 0x0000001F // Device Address +#define EPHY_REGCTL_DEVAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_ADDAR register. +// +//***************************************************************************** +#define EPHY_ADDAR_ADDRDATA_M 0x0000FFFF // Address or Data +#define EPHY_ADDAR_ADDRDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_STS register. +// +//***************************************************************************** +#define EPHY_STS_MDIXM 0x00004000 // MDI-X Mode +#define EPHY_STS_RXLERR 0x00002000 // Receive Error Latch +#define EPHY_STS_POLSTAT 0x00001000 // Polarity Status +#define EPHY_STS_FCSL 0x00000800 // False Carrier Sense Latch +#define EPHY_STS_SD 0x00000400 // Signal Detect +#define EPHY_STS_DL 0x00000200 // Descrambler Lock +#define EPHY_STS_PAGERX 0x00000100 // Link Code Page Received +#define EPHY_STS_MIIREQ 0x00000080 // MII Interrupt Pending +#define EPHY_STS_RF 0x00000040 // Remote Fault +#define EPHY_STS_JD 0x00000020 // Jabber Detect +#define EPHY_STS_ANS 0x00000010 // Auto-Negotiation Status +#define EPHY_STS_MIILB 0x00000008 // MII Loopback Status +#define EPHY_STS_DUPLEX 0x00000004 // Duplex Status +#define EPHY_STS_SPEED 0x00000002 // Speed Status +#define EPHY_STS_LINK 0x00000001 // Link Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_SCR register. +// +//***************************************************************************** +#define EPHY_SCR_DISCLK 0x00008000 // Disable CLK +#define EPHY_SCR_PSEN 0x00004000 // Power Saving Modes Enable +#define EPHY_SCR_PSMODE_M 0x00003000 // Power Saving Modes +#define EPHY_SCR_PSMODE_NORMAL 0x00000000 // Normal: Normal operation mode. + // PHY is fully functional +#define EPHY_SCR_PSMODE_LOWPWR 0x00001000 // IEEE Power Down +#define EPHY_SCR_PSMODE_ACTWOL 0x00002000 // Active Sleep +#define EPHY_SCR_PSMODE_PASWOL 0x00003000 // Passive Sleep +#define EPHY_SCR_SBPYASS 0x00000800 // Scrambler Bypass +#define EPHY_SCR_LBFIFO_M 0x00000300 // Loopback FIFO Depth +#define EPHY_SCR_LBFIFO_4 0x00000000 // Four nibble FIFO +#define EPHY_SCR_LBFIFO_5 0x00000100 // Five nibble FIFO +#define EPHY_SCR_LBFIFO_6 0x00000200 // Six nibble FIFO +#define EPHY_SCR_LBFIFO_8 0x00000300 // Eight nibble FIFO +#define EPHY_SCR_COLFDM 0x00000010 // Collision in Full-Duplex Mode +#define EPHY_SCR_TINT 0x00000004 // Test Interrupt +#define EPHY_SCR_INTEN 0x00000002 // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_MISR1 register. +// +//***************************************************************************** +#define EPHY_MISR1_LINKSTAT 0x00002000 // Change of Link Status Interrupt +#define EPHY_MISR1_SPEED 0x00001000 // Change of Speed Status Interrupt +#define EPHY_MISR1_DUPLEXM 0x00000800 // Change of Duplex Status + // Interrupt +#define EPHY_MISR1_ANC 0x00000400 // Auto-Negotiation Complete + // Interrupt +#define EPHY_MISR1_FCHF 0x00000200 // False Carrier Counter Half-Full + // Interrupt +#define EPHY_MISR1_RXHF 0x00000100 // Receive Error Counter Half-Full + // Interrupt +#define EPHY_MISR1_LINKSTATEN 0x00000020 // Link Status Interrupt Enable +#define EPHY_MISR1_SPEEDEN 0x00000010 // Speed Change Interrupt Enable +#define EPHY_MISR1_DUPLEXMEN 0x00000008 // Duplex Status Interrupt Enable +#define EPHY_MISR1_ANCEN 0x00000004 // Auto-Negotiation Complete + // Interrupt Enable +#define EPHY_MISR1_FCHFEN 0x00000002 // False Carrier Counter Register + // half-full Interrupt Enable +#define EPHY_MISR1_RXHFEN 0x00000001 // Receive Error Counter Register + // Half-Full Event Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_MISR2 register. +// +//***************************************************************************** +#define EPHY_MISR2_ANERR 0x00004000 // Auto-Negotiation Error Interrupt +#define EPHY_MISR2_PAGERX 0x00002000 // Page Receive Interrupt +#define EPHY_MISR2_LBFIFO 0x00001000 // Loopback FIFO Overflow/Underflow + // Event Interrupt +#define EPHY_MISR2_MDICO 0x00000800 // MDI/MDIX Crossover Status + // Changed Interrupt +#define EPHY_MISR2_SLEEP 0x00000400 // Sleep Mode Event Interrupt +#define EPHY_MISR2_POLINT 0x00000200 // Polarity Changed Interrupt +#define EPHY_MISR2_JABBER 0x00000100 // Jabber Detect Event Interrupt +#define EPHY_MISR2_ANERREN 0x00000040 // Auto-Negotiation Error Interrupt + // Enable +#define EPHY_MISR2_PAGERXEN 0x00000020 // Page Receive Interrupt Enable +#define EPHY_MISR2_LBFIFOEN 0x00000010 // Loopback FIFO Overflow/Underflow + // Interrupt Enable +#define EPHY_MISR2_MDICOEN 0x00000008 // MDI/MDIX Crossover Status + // Changed Interrupt Enable +#define EPHY_MISR2_SLEEPEN 0x00000004 // Sleep Mode Event Interrupt + // Enable +#define EPHY_MISR2_POLINTEN 0x00000002 // Polarity Changed Interrupt + // Enable +#define EPHY_MISR2_JABBEREN 0x00000001 // Jabber Detect Event Interrupt + // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_FCSCR register. +// +//***************************************************************************** +#define EPHY_FCSCR_FCSCNT_M 0x000000FF // False Carrier Event Counter +#define EPHY_FCSCR_FCSCNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_RXERCNT register. +// +//***************************************************************************** +#define EPHY_RXERCNT_RXERRCNT_M 0x0000FFFF // Receive Error Count +#define EPHY_RXERCNT_RXERRCNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_BISTCR register. +// +//***************************************************************************** +#define EPHY_BISTCR_PRBSM 0x00004000 // PRBS Single/Continuous Mode +#define EPHY_BISTCR_PRBSPKT 0x00002000 // Generated PRBS Packets +#define EPHY_BISTCR_PKTEN 0x00001000 // Packet Generation Enable +#define EPHY_BISTCR_PRBSCHKLK 0x00000800 // PRBS Checker Lock Indication +#define EPHY_BISTCR_PRBSCHKSYNC 0x00000400 // PRBS Checker Lock Sync Loss + // Indication +#define EPHY_BISTCR_PKTGENSTAT 0x00000200 // Packet Generator Status + // Indication +#define EPHY_BISTCR_PWRMODE 0x00000100 // Power Mode Indication +#define EPHY_BISTCR_TXMIILB 0x00000040 // Transmit Data in MII Loopback + // Mode +#define EPHY_BISTCR_LBMODE_M 0x0000001F // Loopback Mode Select +#define EPHY_BISTCR_LBMODE_NPCSIN \ + 0x00000001 // Near-end loopback: PCS Input + // Loopback +#define EPHY_BISTCR_LBMODE_NPCSOUT \ + 0x00000002 // Near-end loopback: PCS Output + // Loopback (In 100Base-TX only) +#define EPHY_BISTCR_LBMODE_NDIG 0x00000004 // Near-end loopback: Digital + // Loopback +#define EPHY_BISTCR_LBMODE_NANA 0x00000008 // Near-end loopback: Analog + // Loopback (requires 100 Ohm + // termination) +#define EPHY_BISTCR_LBMODE_FREV 0x00000010 // Far-end Loopback: Reverse + // Loopback + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_LEDCR register. +// +//***************************************************************************** +#define EPHY_LEDCR_BLINKRATE_M 0x00000600 // LED Blinking Rate (ON/OFF + // duration): +#define EPHY_LEDCR_BLINKRATE_20HZ \ + 0x00000000 // 20 Hz (50 ms) +#define EPHY_LEDCR_BLINKRATE_10HZ \ + 0x00000200 // 10 Hz (100 ms) +#define EPHY_LEDCR_BLINKRATE_5HZ \ + 0x00000400 // 5 Hz (200 ms) +#define EPHY_LEDCR_BLINKRATE_2HZ \ + 0x00000600 // 2 Hz (500 ms) + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_CTL register. +// +//***************************************************************************** +#define EPHY_CTL_AUTOMDI 0x00008000 // Auto-MDIX Enable +#define EPHY_CTL_FORCEMDI 0x00004000 // Force MDIX +#define EPHY_CTL_PAUSERX 0x00002000 // Pause Receive Negotiated Status +#define EPHY_CTL_PAUSETX 0x00001000 // Pause Transmit Negotiated Status +#define EPHY_CTL_MIILNKSTAT 0x00000800 // MII Link Status +#define EPHY_CTL_BYPLEDSTRCH 0x00000080 // Bypass LED Stretching + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_10BTSC register. +// +//***************************************************************************** +#define EPHY_10BTSC_RXTHEN 0x00002000 // Lower Receiver Threshold Enable +#define EPHY_10BTSC_SQUELCH_M 0x00001E00 // Squelch Configuration +#define EPHY_10BTSC_NLPDIS 0x00000080 // Normal Link Pulse (NLP) + // Transmission Control +#define EPHY_10BTSC_POLSTAT 0x00000010 // 10 Mb Polarity Status +#define EPHY_10BTSC_JABBERD 0x00000001 // Jabber Disable +#define EPHY_10BTSC_SQUELCH_S 9 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_BICSR1 register. +// +//***************************************************************************** +#define EPHY_BICSR1_ERRCNT_M 0x0000FF00 // BIST Error Count +#define EPHY_BICSR1_IPGLENGTH_M 0x000000FF // BIST IPG Length +#define EPHY_BICSR1_ERRCNT_S 8 +#define EPHY_BICSR1_IPGLENGTH_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_BICSR2 register. +// +//***************************************************************************** +#define EPHY_BICSR2_PKTLENGTH_M 0x000007FF // BIST Packet Length +#define EPHY_BICSR2_PKTLENGTH_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_CDCR register. +// +//***************************************************************************** +#define EPHY_CDCR_START 0x00008000 // Cable Diagnostic Process Start +#define EPHY_CDCR_LINKQUAL_M 0x00000300 // Link Quality Indication +#define EPHY_CDCR_LINKQUAL_GOOD 0x00000100 // Good Quality Link Indication +#define EPHY_CDCR_LINKQUAL_MILD 0x00000200 // Mid- Quality Link Indication +#define EPHY_CDCR_LINKQUAL_POOR 0x00000300 // Poor Quality Link Indication +#define EPHY_CDCR_DONE 0x00000002 // Cable Diagnostic Process Done +#define EPHY_CDCR_FAIL 0x00000001 // Cable Diagnostic Process Fail + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_RCR register. +// +//***************************************************************************** +#define EPHY_RCR_SWRST 0x00008000 // Software Reset +#define EPHY_RCR_SWRESTART 0x00004000 // Software Restart + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_LEDCFG register. +// +//***************************************************************************** +#define EPHY_LEDCFG_LED2_M 0x00000F00 // LED2 Configuration +#define EPHY_LEDCFG_LED2_LINK 0x00000000 // Link OK +#define EPHY_LEDCFG_LED2_RXTX 0x00000100 // RX/TX Activity +#define EPHY_LEDCFG_LED2_TX 0x00000200 // TX Activity +#define EPHY_LEDCFG_LED2_RX 0x00000300 // RX Activity +#define EPHY_LEDCFG_LED2_COL 0x00000400 // Collision +#define EPHY_LEDCFG_LED2_100BT 0x00000500 // 100-Base TX +#define EPHY_LEDCFG_LED2_10BT 0x00000600 // 10-Base TX +#define EPHY_LEDCFG_LED2_FD 0x00000700 // Full Duplex +#define EPHY_LEDCFG_LED2_LINKTXRX \ + 0x00000800 // Link OK/Blink on TX/RX Activity +#define EPHY_LEDCFG_LED1_M 0x000000F0 // LED1 Configuration +#define EPHY_LEDCFG_LED1_LINK 0x00000000 // Link OK +#define EPHY_LEDCFG_LED1_RXTX 0x00000010 // RX/TX Activity +#define EPHY_LEDCFG_LED1_TX 0x00000020 // TX Activity +#define EPHY_LEDCFG_LED1_RX 0x00000030 // RX Activity +#define EPHY_LEDCFG_LED1_COL 0x00000040 // Collision +#define EPHY_LEDCFG_LED1_100BT 0x00000050 // 100-Base TX +#define EPHY_LEDCFG_LED1_10BT 0x00000060 // 10-Base TX +#define EPHY_LEDCFG_LED1_FD 0x00000070 // Full Duplex +#define EPHY_LEDCFG_LED1_LINKTXRX \ + 0x00000080 // Link OK/Blink on TX/RX Activity +#define EPHY_LEDCFG_LED0_M 0x0000000F // LED0 Configuration +#define EPHY_LEDCFG_LED0_LINK 0x00000000 // Link OK +#define EPHY_LEDCFG_LED0_RXTX 0x00000001 // RX/TX Activity +#define EPHY_LEDCFG_LED0_TX 0x00000002 // TX Activity +#define EPHY_LEDCFG_LED0_RX 0x00000003 // RX Activity +#define EPHY_LEDCFG_LED0_COL 0x00000004 // Collision +#define EPHY_LEDCFG_LED0_100BT 0x00000005 // 100-Base TX +#define EPHY_LEDCFG_LED0_10BT 0x00000006 // 10-Base TX +#define EPHY_LEDCFG_LED0_FD 0x00000007 // Full Duplex +#define EPHY_LEDCFG_LED0_LINKTXRX \ + 0x00000008 // Link OK/Blink on TX/RX Activity + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// EMAC_O_PPSCTRL register. +// +//***************************************************************************** +#define EMAC_PPSCTRL_PPSCTRL_1HZ \ + 0x00000000 // When the PPSEN0 bit = 0x0, the + // EN0PPS signal is 1 pulse of the + // PTP reference clock.(of width + // clk_ptp_i) every second +#define EMAC_PPSCTRL_PPSCTRL_2HZ \ + 0x00000001 // When the PPSEN0 bit = 0x0, the + // binary rollover is 2 Hz, and the + // digital rollover is 1 Hz +#define EMAC_PPSCTRL_PPSCTRL_4HZ \ + 0x00000002 // When the PPSEN0 bit = 0x0, the + // binary rollover is 4 Hz, and the + // digital rollover is 2 Hz +#define EMAC_PPSCTRL_PPSCTRL_8HZ \ + 0x00000003 // When thePPSEN0 bit = 0x0, the + // binary rollover is 8 Hz, and the + // digital rollover is 4 Hz, +#define EMAC_PPSCTRL_PPSCTRL_16HZ \ + 0x00000004 // When thePPSEN0 bit = 0x0, the + // binary rollover is 16 Hz, and + // the digital rollover is 8 Hz +#define EMAC_PPSCTRL_PPSCTRL_32HZ \ + 0x00000005 // When thePPSEN0 bit = 0x0, the + // binary rollover is 32 Hz, and + // the digital rollover is 16 Hz +#define EMAC_PPSCTRL_PPSCTRL_64HZ \ + 0x00000006 // When thePPSEN0 bit = 0x0, the + // binary rollover is 64 Hz, and + // the digital rollover is 32 Hz +#define EMAC_PPSCTRL_PPSCTRL_128HZ \ + 0x00000007 // When thePPSEN0 bit = 0x0, the + // binary rollover is 128 Hz, and + // the digital rollover is 64 Hz +#define EMAC_PPSCTRL_PPSCTRL_256HZ \ + 0x00000008 // When thePPSEN0 bit = 0x0, the + // binary rollover is 256 Hz, and + // the digital rollover is 128 Hz +#define EMAC_PPSCTRL_PPSCTRL_512HZ \ + 0x00000009 // When thePPSEN0 bit = 0x0, the + // binary rollover is 512 Hz, and + // the digital rollover is 256 Hz +#define EMAC_PPSCTRL_PPSCTRL_1024HZ \ + 0x0000000A // When the PPSEN0 bit = 0x0, the + // binary rollover is 1.024 kHz, + // and the digital rollover is 512 + // Hz +#define EMAC_PPSCTRL_PPSCTRL_2048HZ \ + 0x0000000B // When thePPSEN0 bit = 0x0, the + // binary rollover is 2.048 kHz, + // and the digital rollover is + // 1.024 kHz +#define EMAC_PPSCTRL_PPSCTRL_4096HZ \ + 0x0000000C // When thePPSEN0 bit = 0x0, the + // binary rollover is 4.096 kHz, + // and the digital rollover is + // 2.048 kHz +#define EMAC_PPSCTRL_PPSCTRL_8192HZ \ + 0x0000000D // When thePPSEN0 bit = 0x0, the + // binary rollover is 8.192 kHz, + // and the digital rollover is + // 4.096 kHz +#define EMAC_PPSCTRL_PPSCTRL_16384HZ \ + 0x0000000E // When thePPSEN0 bit = 0x0, the + // binary rollover is 16.384 kHz, + // and the digital rollover is + // 8.092 kHz +#define EMAC_PPSCTRL_PPSCTRL_32768HZ \ + 0x0000000F // When thePPSEN0 bit = 0x0, the + // binary rollover is 32.768 KHz, + // and the digital rollover is + // 16.384 KHz + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the EMAC_O_CC +// register. +// +//***************************************************************************** +#define EMAC_CC_CS_PA7 0x00000001 // GPIO + +#endif + +#endif // __HW_EMAC_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_epi.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_epi.h new file mode 100644 index 0000000000000000000000000000000000000000..ea9f0655629e6b73b3cb40157b46113e0429fc3b --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_epi.h @@ -0,0 +1,933 @@ +//***************************************************************************** +// +// hw_epi.h - Macros for use in accessing the EPI registers. +// +// Copyright (c) 2008-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_EPI_H__ +#define __HW_EPI_H__ + +//***************************************************************************** +// +// The following are defines for the External Peripheral Interface register +// offsets. +// +//***************************************************************************** +#define EPI_O_CFG 0x00000000 // EPI Configuration +#define EPI_O_BAUD 0x00000004 // EPI Main Baud Rate +#define EPI_O_BAUD2 0x00000008 // EPI Main Baud Rate +#define EPI_O_HB16CFG 0x00000010 // EPI Host-Bus 16 Configuration +#define EPI_O_GPCFG 0x00000010 // EPI General-Purpose + // Configuration +#define EPI_O_SDRAMCFG 0x00000010 // EPI SDRAM Configuration +#define EPI_O_HB8CFG 0x00000010 // EPI Host-Bus 8 Configuration +#define EPI_O_HB8CFG2 0x00000014 // EPI Host-Bus 8 Configuration 2 +#define EPI_O_HB16CFG2 0x00000014 // EPI Host-Bus 16 Configuration 2 +#define EPI_O_ADDRMAP 0x0000001C // EPI Address Map +#define EPI_O_RSIZE0 0x00000020 // EPI Read Size 0 +#define EPI_O_RADDR0 0x00000024 // EPI Read Address 0 +#define EPI_O_RPSTD0 0x00000028 // EPI Non-Blocking Read Data 0 +#define EPI_O_RSIZE1 0x00000030 // EPI Read Size 1 +#define EPI_O_RADDR1 0x00000034 // EPI Read Address 1 +#define EPI_O_RPSTD1 0x00000038 // EPI Non-Blocking Read Data 1 +#define EPI_O_STAT 0x00000060 // EPI Status +#define EPI_O_RFIFOCNT 0x0000006C // EPI Read FIFO Count +#define EPI_O_READFIFO0 0x00000070 // EPI Read FIFO +#define EPI_O_READFIFO1 0x00000074 // EPI Read FIFO Alias 1 +#define EPI_O_READFIFO2 0x00000078 // EPI Read FIFO Alias 2 +#define EPI_O_READFIFO3 0x0000007C // EPI Read FIFO Alias 3 +#define EPI_O_READFIFO4 0x00000080 // EPI Read FIFO Alias 4 +#define EPI_O_READFIFO5 0x00000084 // EPI Read FIFO Alias 5 +#define EPI_O_READFIFO6 0x00000088 // EPI Read FIFO Alias 6 +#define EPI_O_READFIFO7 0x0000008C // EPI Read FIFO Alias 7 +#define EPI_O_FIFOLVL 0x00000200 // EPI FIFO Level Selects +#define EPI_O_WFIFOCNT 0x00000204 // EPI Write FIFO Count +#define EPI_O_DMATXCNT 0x00000208 // EPI DMA Transmit Count +#define EPI_O_IM 0x00000210 // EPI Interrupt Mask +#define EPI_O_RIS 0x00000214 // EPI Raw Interrupt Status +#define EPI_O_MIS 0x00000218 // EPI Masked Interrupt Status +#define EPI_O_EISC 0x0000021C // EPI Error and Interrupt Status + // and Clear +#define EPI_O_HB8CFG3 0x00000308 // EPI Host-Bus 8 Configuration 3 +#define EPI_O_HB16CFG3 0x00000308 // EPI Host-Bus 16 Configuration 3 +#define EPI_O_HB16CFG4 0x0000030C // EPI Host-Bus 16 Configuration 4 +#define EPI_O_HB8CFG4 0x0000030C // EPI Host-Bus 8 Configuration 4 +#define EPI_O_HB8TIME 0x00000310 // EPI Host-Bus 8 Timing Extension +#define EPI_O_HB16TIME 0x00000310 // EPI Host-Bus 16 Timing Extension +#define EPI_O_HB8TIME2 0x00000314 // EPI Host-Bus 8 Timing Extension +#define EPI_O_HB16TIME2 0x00000314 // EPI Host-Bus 16 Timing Extension +#define EPI_O_HB16TIME3 0x00000318 // EPI Host-Bus 16 Timing Extension +#define EPI_O_HB8TIME3 0x00000318 // EPI Host-Bus 8 Timing Extension +#define EPI_O_HB8TIME4 0x0000031C // EPI Host-Bus 8 Timing Extension +#define EPI_O_HB16TIME4 0x0000031C // EPI Host-Bus 16 Timing Extension +#define EPI_O_HBPSRAM 0x00000360 // EPI Host-Bus PSRAM + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_CFG register. +// +//***************************************************************************** +#define EPI_CFG_INTDIV 0x00000100 // Integer Clock Divider Enable +#define EPI_CFG_BLKEN 0x00000010 // Block Enable +#define EPI_CFG_MODE_M 0x0000000F // Mode Select +#define EPI_CFG_MODE_NONE 0x00000000 // General Purpose +#define EPI_CFG_MODE_SDRAM 0x00000001 // SDRAM +#define EPI_CFG_MODE_HB8 0x00000002 // 8-Bit Host-Bus (HB8) +#define EPI_CFG_MODE_HB16 0x00000003 // 16-Bit Host-Bus (HB16) + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_BAUD register. +// +//***************************************************************************** +#define EPI_BAUD_COUNT1_M 0xFFFF0000 // Baud Rate Counter 1 +#define EPI_BAUD_COUNT0_M 0x0000FFFF // Baud Rate Counter 0 +#define EPI_BAUD_COUNT1_S 16 +#define EPI_BAUD_COUNT0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_BAUD2 register. +// +//***************************************************************************** +#define EPI_BAUD2_COUNT1_M 0xFFFF0000 // CS3n Baud Rate Counter 1 +#define EPI_BAUD2_COUNT0_M 0x0000FFFF // CS2n Baud Rate Counter 0 +#define EPI_BAUD2_COUNT1_S 16 +#define EPI_BAUD2_COUNT0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_HB16CFG register. +// +//***************************************************************************** +#define EPI_HB16CFG_CLKGATE 0x80000000 // Clock Gated +#define EPI_HB16CFG_CLKGATEI 0x40000000 // Clock Gated Idle +#define EPI_HB16CFG_CLKINV 0x20000000 // Invert Output Clock Enable +#define EPI_HB16CFG_RDYEN 0x10000000 // Input Ready Enable +#define EPI_HB16CFG_IRDYINV 0x08000000 // Input Ready Invert +#define EPI_HB16CFG_XFFEN 0x00800000 // External FIFO FULL Enable +#define EPI_HB16CFG_XFEEN 0x00400000 // External FIFO EMPTY Enable +#define EPI_HB16CFG_WRHIGH 0x00200000 // WRITE Strobe Polarity +#define EPI_HB16CFG_RDHIGH 0x00100000 // READ Strobe Polarity +#define EPI_HB16CFG_ALEHIGH 0x00080000 // ALE Strobe Polarity +#define EPI_HB16CFG_WRCRE 0x00040000 // PSRAM Configuration Register + // Write +#define EPI_HB16CFG_RDCRE 0x00020000 // PSRAM Configuration Register + // Read +#define EPI_HB16CFG_BURST 0x00010000 // Burst Mode +#define EPI_HB16CFG_MAXWAIT_M 0x0000FF00 // Maximum Wait +#define EPI_HB16CFG_WRWS_M 0x000000C0 // Write Wait States +#define EPI_HB16CFG_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks +#define EPI_HB16CFG_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks +#define EPI_HB16CFG_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks +#define EPI_HB16CFG_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks +#define EPI_HB16CFG_RDWS_M 0x00000030 // Read Wait States +#define EPI_HB16CFG_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks +#define EPI_HB16CFG_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks +#define EPI_HB16CFG_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks +#define EPI_HB16CFG_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks +#define EPI_HB16CFG_BSEL 0x00000004 // Byte Select Configuration +#define EPI_HB16CFG_MODE_M 0x00000003 // Host Bus Sub-Mode +#define EPI_HB16CFG_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0] +#define EPI_HB16CFG_MODE_ADNMUX 0x00000001 // ADNONMUX - D[15:0] +#define EPI_HB16CFG_MODE_SRAM 0x00000002 // Continuous Read - D[15:0] +#define EPI_HB16CFG_MODE_XFIFO 0x00000003 // XFIFO - D[15:0] +#define EPI_HB16CFG_MAXWAIT_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_GPCFG register. +// +//***************************************************************************** +#define EPI_GPCFG_CLKPIN 0x80000000 // Clock Pin +#define EPI_GPCFG_CLKGATE 0x40000000 // Clock Gated +#define EPI_GPCFG_FRM50 0x04000000 // 50/50 Frame +#define EPI_GPCFG_FRMCNT_M 0x03C00000 // Frame Count +#define EPI_GPCFG_WR2CYC 0x00080000 // 2-Cycle Writes +#define EPI_GPCFG_ASIZE_M 0x00000030 // Address Bus Size +#define EPI_GPCFG_ASIZE_NONE 0x00000000 // No address +#define EPI_GPCFG_ASIZE_4BIT 0x00000010 // Up to 4 bits wide +#define EPI_GPCFG_ASIZE_12BIT 0x00000020 // Up to 12 bits wide. This size + // cannot be used with 24-bit data +#define EPI_GPCFG_ASIZE_20BIT 0x00000030 // Up to 20 bits wide. This size + // cannot be used with data sizes + // other than 8 +#define EPI_GPCFG_DSIZE_M 0x00000003 // Size of Data Bus +#define EPI_GPCFG_DSIZE_4BIT 0x00000000 // 8 Bits Wide (EPI0S0 to EPI0S7) +#define EPI_GPCFG_DSIZE_16BIT 0x00000001 // 16 Bits Wide (EPI0S0 to EPI0S15) +#define EPI_GPCFG_DSIZE_24BIT 0x00000002 // 24 Bits Wide (EPI0S0 to EPI0S23) +#define EPI_GPCFG_DSIZE_32BIT 0x00000003 // 32 Bits Wide (EPI0S0 to EPI0S31) +#define EPI_GPCFG_FRMCNT_S 22 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_SDRAMCFG register. +// +//***************************************************************************** +#define EPI_SDRAMCFG_FREQ_M 0xC0000000 // EPI Frequency Range +#define EPI_SDRAMCFG_FREQ_NONE 0x00000000 // 0 - 15 MHz +#define EPI_SDRAMCFG_FREQ_15MHZ 0x40000000 // 15 - 30 MHz +#define EPI_SDRAMCFG_FREQ_30MHZ 0x80000000 // 30 - 50 MHz +#define EPI_SDRAMCFG_RFSH_M 0x07FF0000 // Refresh Counter +#define EPI_SDRAMCFG_SLEEP 0x00000200 // Sleep Mode +#define EPI_SDRAMCFG_SIZE_M 0x00000003 // Size of SDRAM +#define EPI_SDRAMCFG_SIZE_8MB 0x00000000 // 64 megabits (8MB) +#define EPI_SDRAMCFG_SIZE_16MB 0x00000001 // 128 megabits (16MB) +#define EPI_SDRAMCFG_SIZE_32MB 0x00000002 // 256 megabits (32MB) +#define EPI_SDRAMCFG_SIZE_64MB 0x00000003 // 512 megabits (64MB) +#define EPI_SDRAMCFG_RFSH_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_HB8CFG register. +// +//***************************************************************************** +#define EPI_HB8CFG_CLKGATE 0x80000000 // Clock Gated +#define EPI_HB8CFG_CLKGATEI 0x40000000 // Clock Gated when Idle +#define EPI_HB8CFG_CLKINV 0x20000000 // Invert Output Clock Enable +#define EPI_HB8CFG_RDYEN 0x10000000 // Input Ready Enable +#define EPI_HB8CFG_IRDYINV 0x08000000 // Input Ready Invert +#define EPI_HB8CFG_XFFEN 0x00800000 // External FIFO FULL Enable +#define EPI_HB8CFG_XFEEN 0x00400000 // External FIFO EMPTY Enable +#define EPI_HB8CFG_WRHIGH 0x00200000 // WRITE Strobe Polarity +#define EPI_HB8CFG_RDHIGH 0x00100000 // READ Strobe Polarity +#define EPI_HB8CFG_ALEHIGH 0x00080000 // ALE Strobe Polarity +#define EPI_HB8CFG_MAXWAIT_M 0x0000FF00 // Maximum Wait +#define EPI_HB8CFG_WRWS_M 0x000000C0 // Write Wait States +#define EPI_HB8CFG_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks +#define EPI_HB8CFG_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks +#define EPI_HB8CFG_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks +#define EPI_HB8CFG_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks +#define EPI_HB8CFG_RDWS_M 0x00000030 // Read Wait States +#define EPI_HB8CFG_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks +#define EPI_HB8CFG_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks +#define EPI_HB8CFG_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks +#define EPI_HB8CFG_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks +#define EPI_HB8CFG_MODE_M 0x00000003 // Host Bus Sub-Mode +#define EPI_HB8CFG_MODE_MUX 0x00000000 // ADMUX - AD[7:0] +#define EPI_HB8CFG_MODE_NMUX 0x00000001 // ADNONMUX - D[7:0] +#define EPI_HB8CFG_MODE_SRAM 0x00000002 // Continuous Read - D[7:0] +#define EPI_HB8CFG_MODE_FIFO 0x00000003 // XFIFO - D[7:0] +#define EPI_HB8CFG_MAXWAIT_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_HB8CFG2 register. +// +//***************************************************************************** +#define EPI_HB8CFG2_CSCFGEXT 0x08000000 // Chip Select Extended + // Configuration +#define EPI_HB8CFG2_CSBAUD 0x04000000 // Chip Select Baud Rate and + // Multiple Sub-Mode Configuration + // enable +#define EPI_HB8CFG2_CSCFG_M 0x03000000 // Chip Select Configuration +#define EPI_HB8CFG2_CSCFG_ALE 0x00000000 // ALE Configuration +#define EPI_HB8CFG2_CSCFG_CS 0x01000000 // CSn Configuration +#define EPI_HB8CFG2_CSCFG_DCS 0x02000000 // Dual CSn Configuration +#define EPI_HB8CFG2_CSCFG_ADCS 0x03000000 // ALE with Dual CSn Configuration +#define EPI_HB8CFG2_WRHIGH 0x00200000 // CS1n WRITE Strobe Polarity +#define EPI_HB8CFG2_RDHIGH 0x00100000 // CS1n READ Strobe Polarity +#define EPI_HB8CFG2_ALEHIGH 0x00080000 // CS1n ALE Strobe Polarity +#define EPI_HB8CFG2_WRWS_M 0x000000C0 // CS1n Write Wait States +#define EPI_HB8CFG2_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks +#define EPI_HB8CFG2_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks +#define EPI_HB8CFG2_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks +#define EPI_HB8CFG2_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks +#define EPI_HB8CFG2_RDWS_M 0x00000030 // CS1n Read Wait States +#define EPI_HB8CFG2_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks +#define EPI_HB8CFG2_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks +#define EPI_HB8CFG2_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks +#define EPI_HB8CFG2_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks +#define EPI_HB8CFG2_MODE_M 0x00000003 // CS1n Host Bus Sub-Mode +#define EPI_HB8CFG2_MODE_ADMUX 0x00000000 // ADMUX - AD[7:0] +#define EPI_HB8CFG2_MODE_AD 0x00000001 // ADNONMUX - D[7:0] + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_HB16CFG2 register. +// +//***************************************************************************** +#define EPI_HB16CFG2_CSCFGEXT 0x08000000 // Chip Select Extended + // Configuration +#define EPI_HB16CFG2_CSBAUD 0x04000000 // Chip Select Baud Rate and + // Multiple Sub-Mode Configuration + // enable +#define EPI_HB16CFG2_CSCFG_M 0x03000000 // Chip Select Configuration +#define EPI_HB16CFG2_CSCFG_ALE 0x00000000 // ALE Configuration +#define EPI_HB16CFG2_CSCFG_CS 0x01000000 // CSn Configuration +#define EPI_HB16CFG2_CSCFG_DCS 0x02000000 // Dual CSn Configuration +#define EPI_HB16CFG2_CSCFG_ADCS 0x03000000 // ALE with Dual CSn Configuration +#define EPI_HB16CFG2_WRHIGH 0x00200000 // CS1n WRITE Strobe Polarity +#define EPI_HB16CFG2_RDHIGH 0x00100000 // CS1n READ Strobe Polarity +#define EPI_HB16CFG2_ALEHIGH 0x00080000 // CS1n ALE Strobe Polarity +#define EPI_HB16CFG2_WRCRE 0x00040000 // CS1n PSRAM Configuration + // Register Write +#define EPI_HB16CFG2_RDCRE 0x00020000 // CS1n PSRAM Configuration + // Register Read +#define EPI_HB16CFG2_BURST 0x00010000 // CS1n Burst Mode +#define EPI_HB16CFG2_WRWS_M 0x000000C0 // CS1n Write Wait States +#define EPI_HB16CFG2_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks +#define EPI_HB16CFG2_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks +#define EPI_HB16CFG2_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks +#define EPI_HB16CFG2_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks +#define EPI_HB16CFG2_RDWS_M 0x00000030 // CS1n Read Wait States +#define EPI_HB16CFG2_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks +#define EPI_HB16CFG2_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks +#define EPI_HB16CFG2_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks +#define EPI_HB16CFG2_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks +#define EPI_HB16CFG2_MODE_M 0x00000003 // CS1n Host Bus Sub-Mode +#define EPI_HB16CFG2_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0] +#define EPI_HB16CFG2_MODE_AD 0x00000001 // ADNONMUX - D[15:0] + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_ADDRMAP register. +// +//***************************************************************************** +#define EPI_ADDRMAP_ECSZ_M 0x00000C00 // External Code Size +#define EPI_ADDRMAP_ECSZ_256B 0x00000000 // 256 bytes; lower address range: + // 0x00 to 0xFF +#define EPI_ADDRMAP_ECSZ_64KB 0x00000400 // 64 KB; lower address range: + // 0x0000 to 0xFFFF +#define EPI_ADDRMAP_ECSZ_16MB 0x00000800 // 16 MB; lower address range: + // 0x00.0000 to 0xFF.FFFF +#define EPI_ADDRMAP_ECSZ_256MB 0x00000C00 // 256MB; lower address range: + // 0x000.0000 to 0x0FFF.FFFF +#define EPI_ADDRMAP_ECADR_M 0x00000300 // External Code Address +#define EPI_ADDRMAP_ECADR_NONE 0x00000000 // Not mapped +#define EPI_ADDRMAP_ECADR_1000 0x00000100 // At 0x1000.0000 +#define EPI_ADDRMAP_EPSZ_M 0x000000C0 // External Peripheral Size +#define EPI_ADDRMAP_EPSZ_256B 0x00000000 // 256 bytes; lower address range: + // 0x00 to 0xFF +#define EPI_ADDRMAP_EPSZ_64KB 0x00000040 // 64 KB; lower address range: + // 0x0000 to 0xFFFF +#define EPI_ADDRMAP_EPSZ_16MB 0x00000080 // 16 MB; lower address range: + // 0x00.0000 to 0xFF.FFFF +#define EPI_ADDRMAP_EPSZ_256MB 0x000000C0 // 256 MB; lower address range: + // 0x000.0000 to 0xFFF.FFFF +#define EPI_ADDRMAP_EPADR_M 0x00000030 // External Peripheral Address +#define EPI_ADDRMAP_EPADR_NONE 0x00000000 // Not mapped +#define EPI_ADDRMAP_EPADR_A000 0x00000010 // At 0xA000.0000 +#define EPI_ADDRMAP_EPADR_C000 0x00000020 // At 0xC000.0000 +#define EPI_ADDRMAP_EPADR_HBQS 0x00000030 // Only to be used with Host Bus + // quad chip select. In quad chip + // select mode, CS2n maps to + // 0xA000.0000 and CS3n maps to + // 0xC000.0000 +#define EPI_ADDRMAP_ERSZ_M 0x0000000C // External RAM Size +#define EPI_ADDRMAP_ERSZ_256B 0x00000000 // 256 bytes; lower address range: + // 0x00 to 0xFF +#define EPI_ADDRMAP_ERSZ_64KB 0x00000004 // 64 KB; lower address range: + // 0x0000 to 0xFFFF +#define EPI_ADDRMAP_ERSZ_16MB 0x00000008 // 16 MB; lower address range: + // 0x00.0000 to 0xFF.FFFF +#define EPI_ADDRMAP_ERSZ_256MB 0x0000000C // 256 MB; lower address range: + // 0x000.0000 to 0xFFF.FFFF +#define EPI_ADDRMAP_ERADR_M 0x00000003 // External RAM Address +#define EPI_ADDRMAP_ERADR_NONE 0x00000000 // Not mapped +#define EPI_ADDRMAP_ERADR_6000 0x00000001 // At 0x6000.0000 +#define EPI_ADDRMAP_ERADR_8000 0x00000002 // At 0x8000.0000 +#define EPI_ADDRMAP_ERADR_HBQS 0x00000003 // Only to be used with Host Bus + // quad chip select. In quad chip + // select mode, CS0n maps to + // 0x6000.0000 and CS1n maps to + // 0x8000.0000 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_RSIZE0 register. +// +//***************************************************************************** +#define EPI_RSIZE0_SIZE_M 0x00000003 // Current Size +#define EPI_RSIZE0_SIZE_8BIT 0x00000001 // Byte (8 bits) +#define EPI_RSIZE0_SIZE_16BIT 0x00000002 // Half-word (16 bits) +#define EPI_RSIZE0_SIZE_32BIT 0x00000003 // Word (32 bits) + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_RADDR0 register. +// +//***************************************************************************** +#define EPI_RADDR0_ADDR_M 0xFFFFFFFF // Current Address +#define EPI_RADDR0_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_RPSTD0 register. +// +//***************************************************************************** +#define EPI_RPSTD0_POSTCNT_M 0x00001FFF // Post Count +#define EPI_RPSTD0_POSTCNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_RSIZE1 register. +// +//***************************************************************************** +#define EPI_RSIZE1_SIZE_M 0x00000003 // Current Size +#define EPI_RSIZE1_SIZE_8BIT 0x00000001 // Byte (8 bits) +#define EPI_RSIZE1_SIZE_16BIT 0x00000002 // Half-word (16 bits) +#define EPI_RSIZE1_SIZE_32BIT 0x00000003 // Word (32 bits) + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_RADDR1 register. +// +//***************************************************************************** +#define EPI_RADDR1_ADDR_M 0xFFFFFFFF // Current Address +#define EPI_RADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_RPSTD1 register. +// +//***************************************************************************** +#define EPI_RPSTD1_POSTCNT_M 0x00001FFF // Post Count +#define EPI_RPSTD1_POSTCNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_STAT register. +// +//***************************************************************************** +#define EPI_STAT_XFFULL 0x00000100 // External FIFO Full +#define EPI_STAT_XFEMPTY 0x00000080 // External FIFO Empty +#define EPI_STAT_INITSEQ 0x00000040 // Initialization Sequence +#define EPI_STAT_WBUSY 0x00000020 // Write Busy +#define EPI_STAT_NBRBUSY 0x00000010 // Non-Blocking Read Busy +#define EPI_STAT_ACTIVE 0x00000001 // Register Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_RFIFOCNT register. +// +//***************************************************************************** +#define EPI_RFIFOCNT_COUNT_M 0x0000000F // FIFO Count +#define EPI_RFIFOCNT_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_READFIFO0 +// register. +// +//***************************************************************************** +#define EPI_READFIFO0_DATA_M 0xFFFFFFFF // Reads Data +#define EPI_READFIFO0_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_READFIFO1 +// register. +// +//***************************************************************************** +#define EPI_READFIFO1_DATA_M 0xFFFFFFFF // Reads Data +#define EPI_READFIFO1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_READFIFO2 +// register. +// +//***************************************************************************** +#define EPI_READFIFO2_DATA_M 0xFFFFFFFF // Reads Data +#define EPI_READFIFO2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_READFIFO3 +// register. +// +//***************************************************************************** +#define EPI_READFIFO3_DATA_M 0xFFFFFFFF // Reads Data +#define EPI_READFIFO3_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_READFIFO4 +// register. +// +//***************************************************************************** +#define EPI_READFIFO4_DATA_M 0xFFFFFFFF // Reads Data +#define EPI_READFIFO4_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_READFIFO5 +// register. +// +//***************************************************************************** +#define EPI_READFIFO5_DATA_M 0xFFFFFFFF // Reads Data +#define EPI_READFIFO5_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_READFIFO6 +// register. +// +//***************************************************************************** +#define EPI_READFIFO6_DATA_M 0xFFFFFFFF // Reads Data +#define EPI_READFIFO6_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_READFIFO7 +// register. +// +//***************************************************************************** +#define EPI_READFIFO7_DATA_M 0xFFFFFFFF // Reads Data +#define EPI_READFIFO7_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_FIFOLVL register. +// +//***************************************************************************** +#define EPI_FIFOLVL_WFERR 0x00020000 // Write Full Error +#define EPI_FIFOLVL_RSERR 0x00010000 // Read Stall Error +#define EPI_FIFOLVL_WRFIFO_M 0x00000070 // Write FIFO +#define EPI_FIFOLVL_WRFIFO_EMPT 0x00000000 // Interrupt is triggered while + // WRFIFO is empty. +#define EPI_FIFOLVL_WRFIFO_2 0x00000020 // Interrupt is triggered until + // there are only two slots + // available. Thus, trigger is + // deasserted when there are two + // WRFIFO entries present. This + // configuration is optimized for + // bursts of 2 +#define EPI_FIFOLVL_WRFIFO_1 0x00000030 // Interrupt is triggered until + // there is one WRFIFO entry + // available. This configuration + // expects only single writes +#define EPI_FIFOLVL_WRFIFO_NFULL \ + 0x00000040 // Trigger interrupt when WRFIFO is + // not full, meaning trigger will + // continue to assert until there + // are four entries in the WRFIFO +#define EPI_FIFOLVL_RDFIFO_M 0x00000007 // Read FIFO +#define EPI_FIFOLVL_RDFIFO_EMPT 0x00000000 // Empty +#define EPI_FIFOLVL_RDFIFO_1 0x00000001 // Trigger when there are 1 or more + // entries in the NBRFIFO +#define EPI_FIFOLVL_RDFIFO_2 0x00000002 // Trigger when there are 2 or more + // entries in the NBRFIFO +#define EPI_FIFOLVL_RDFIFO_4 0x00000003 // Trigger when there are 4 or more + // entries in the NBRFIFO +#define EPI_FIFOLVL_RDFIFO_6 0x00000004 // Trigger when there are 6 or more + // entries in the NBRFIFO +#define EPI_FIFOLVL_RDFIFO_7 0x00000005 // Trigger when there are 7 or more + // entries in the NBRFIFO +#define EPI_FIFOLVL_RDFIFO_8 0x00000006 // Trigger when there are 8 entries + // in the NBRFIFO + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_WFIFOCNT register. +// +//***************************************************************************** +#define EPI_WFIFOCNT_WTAV_M 0x00000007 // Available Write Transactions +#define EPI_WFIFOCNT_WTAV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_DMATXCNT register. +// +//***************************************************************************** +#define EPI_DMATXCNT_TXCNT_M 0x0000FFFF // DMA Count +#define EPI_DMATXCNT_TXCNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_IM register. +// +//***************************************************************************** +#define EPI_IM_DMAWRIM 0x00000010 // Write uDMA Interrupt Mask +#define EPI_IM_DMARDIM 0x00000008 // Read uDMA Interrupt Mask +#define EPI_IM_WRIM 0x00000004 // Write FIFO Empty Interrupt Mask +#define EPI_IM_RDIM 0x00000002 // Read FIFO Full Interrupt Mask +#define EPI_IM_ERRIM 0x00000001 // Error Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_RIS register. +// +//***************************************************************************** +#define EPI_RIS_DMAWRRIS 0x00000010 // Write uDMA Raw Interrupt Status +#define EPI_RIS_DMARDRIS 0x00000008 // Read uDMA Raw Interrupt Status +#define EPI_RIS_WRRIS 0x00000004 // Write Raw Interrupt Status +#define EPI_RIS_RDRIS 0x00000002 // Read Raw Interrupt Status +#define EPI_RIS_ERRRIS 0x00000001 // Error Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_MIS register. +// +//***************************************************************************** +#define EPI_MIS_DMAWRMIS 0x00000010 // Write uDMA Masked Interrupt + // Status +#define EPI_MIS_DMARDMIS 0x00000008 // Read uDMA Masked Interrupt + // Status +#define EPI_MIS_WRMIS 0x00000004 // Write Masked Interrupt Status +#define EPI_MIS_RDMIS 0x00000002 // Read Masked Interrupt Status +#define EPI_MIS_ERRMIS 0x00000001 // Error Masked Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_EISC register. +// +//***************************************************************************** +#define EPI_EISC_DMAWRIC 0x00000010 // Write uDMA Interrupt Clear +#define EPI_EISC_DMARDIC 0x00000008 // Read uDMA Interrupt Clear +#define EPI_EISC_WTFULL 0x00000004 // Write FIFO Full Error +#define EPI_EISC_RSTALL 0x00000002 // Read Stalled Error +#define EPI_EISC_TOUT 0x00000001 // Timeout Error + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_HB8CFG3 register. +// +//***************************************************************************** +#define EPI_HB8CFG3_WRHIGH 0x00200000 // CS2n WRITE Strobe Polarity +#define EPI_HB8CFG3_RDHIGH 0x00100000 // CS2n READ Strobe Polarity +#define EPI_HB8CFG3_ALEHIGH 0x00080000 // CS2n ALE Strobe Polarity +#define EPI_HB8CFG3_WRWS_M 0x000000C0 // CS2n Write Wait States +#define EPI_HB8CFG3_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks +#define EPI_HB8CFG3_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks +#define EPI_HB8CFG3_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks +#define EPI_HB8CFG3_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks +#define EPI_HB8CFG3_RDWS_M 0x00000030 // CS2n Read Wait States +#define EPI_HB8CFG3_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks +#define EPI_HB8CFG3_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks +#define EPI_HB8CFG3_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks +#define EPI_HB8CFG3_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks +#define EPI_HB8CFG3_MODE_M 0x00000003 // CS2n Host Bus Sub-Mode +#define EPI_HB8CFG3_MODE_ADMUX 0x00000000 // ADMUX - AD[7:0] +#define EPI_HB8CFG3_MODE_AD 0x00000001 // ADNONMUX - D[7:0] + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_HB16CFG3 register. +// +//***************************************************************************** +#define EPI_HB16CFG3_WRHIGH 0x00200000 // CS2n WRITE Strobe Polarity +#define EPI_HB16CFG3_RDHIGH 0x00100000 // CS2n READ Strobe Polarity +#define EPI_HB16CFG3_ALEHIGH 0x00080000 // CS2n ALE Strobe Polarity +#define EPI_HB16CFG3_WRCRE 0x00040000 // CS2n PSRAM Configuration + // Register Write +#define EPI_HB16CFG3_RDCRE 0x00020000 // CS2n PSRAM Configuration + // Register Read +#define EPI_HB16CFG3_BURST 0x00010000 // CS2n Burst Mode +#define EPI_HB16CFG3_WRWS_M 0x000000C0 // CS2n Write Wait States +#define EPI_HB16CFG3_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks +#define EPI_HB16CFG3_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks +#define EPI_HB16CFG3_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks +#define EPI_HB16CFG3_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks +#define EPI_HB16CFG3_RDWS_M 0x00000030 // CS2n Read Wait States +#define EPI_HB16CFG3_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks +#define EPI_HB16CFG3_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks +#define EPI_HB16CFG3_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks +#define EPI_HB16CFG3_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks +#define EPI_HB16CFG3_MODE_M 0x00000003 // CS2n Host Bus Sub-Mode +#define EPI_HB16CFG3_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0] +#define EPI_HB16CFG3_MODE_AD 0x00000001 // ADNONMUX - D[15:0] + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_HB16CFG4 register. +// +//***************************************************************************** +#define EPI_HB16CFG4_WRHIGH 0x00200000 // CS3n WRITE Strobe Polarity +#define EPI_HB16CFG4_RDHIGH 0x00100000 // CS3n READ Strobe Polarity +#define EPI_HB16CFG4_ALEHIGH 0x00080000 // CS3n ALE Strobe Polarity +#define EPI_HB16CFG4_WRCRE 0x00040000 // CS3n PSRAM Configuration + // Register Write +#define EPI_HB16CFG4_RDCRE 0x00020000 // CS3n PSRAM Configuration + // Register Read +#define EPI_HB16CFG4_BURST 0x00010000 // CS3n Burst Mode +#define EPI_HB16CFG4_WRWS_M 0x000000C0 // CS3n Write Wait States +#define EPI_HB16CFG4_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks +#define EPI_HB16CFG4_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks +#define EPI_HB16CFG4_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks +#define EPI_HB16CFG4_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks +#define EPI_HB16CFG4_RDWS_M 0x00000030 // CS3n Read Wait States +#define EPI_HB16CFG4_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks +#define EPI_HB16CFG4_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks +#define EPI_HB16CFG4_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks +#define EPI_HB16CFG4_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks +#define EPI_HB16CFG4_MODE_M 0x00000003 // CS3n Host Bus Sub-Mode +#define EPI_HB16CFG4_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0] +#define EPI_HB16CFG4_MODE_AD 0x00000001 // ADNONMUX - D[15:0] + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_HB8CFG4 register. +// +//***************************************************************************** +#define EPI_HB8CFG4_WRHIGH 0x00200000 // CS3n WRITE Strobe Polarity +#define EPI_HB8CFG4_RDHIGH 0x00100000 // CS2n READ Strobe Polarity +#define EPI_HB8CFG4_ALEHIGH 0x00080000 // CS3n ALE Strobe Polarity +#define EPI_HB8CFG4_WRWS_M 0x000000C0 // CS3n Write Wait States +#define EPI_HB8CFG4_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks +#define EPI_HB8CFG4_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks +#define EPI_HB8CFG4_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks +#define EPI_HB8CFG4_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks +#define EPI_HB8CFG4_RDWS_M 0x00000030 // CS3n Read Wait States +#define EPI_HB8CFG4_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks +#define EPI_HB8CFG4_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks +#define EPI_HB8CFG4_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks +#define EPI_HB8CFG4_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks +#define EPI_HB8CFG4_MODE_M 0x00000003 // CS3n Host Bus Sub-Mode +#define EPI_HB8CFG4_MODE_ADMUX 0x00000000 // ADMUX - AD[7:0] +#define EPI_HB8CFG4_MODE_AD 0x00000001 // ADNONMUX - D[7:0] + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_HB8TIME register. +// +//***************************************************************************** +#define EPI_HB8TIME_IRDYDLY_M 0x03000000 // CS0n Input Ready Delay +#define EPI_HB8TIME_CAPWIDTH_M 0x00003000 // CS0n Inter-transfer Capture + // Width +#define EPI_HB8TIME_WRWSM 0x00000010 // Write Wait State Minus One +#define EPI_HB8TIME_RDWSM 0x00000001 // Read Wait State Minus One +#define EPI_HB8TIME_IRDYDLY_S 24 +#define EPI_HB8TIME_CAPWIDTH_S 12 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_HB16TIME register. +// +//***************************************************************************** +#define EPI_HB16TIME_IRDYDLY_M 0x03000000 // CS0n Input Ready Delay +#define EPI_HB16TIME_PSRAMSZ_M 0x00070000 // PSRAM Row Size +#define EPI_HB16TIME_PSRAMSZ_0 0x00000000 // No row size limitation +#define EPI_HB16TIME_PSRAMSZ_128B \ + 0x00010000 // 128 B +#define EPI_HB16TIME_PSRAMSZ_256B \ + 0x00020000 // 256 B +#define EPI_HB16TIME_PSRAMSZ_512B \ + 0x00030000 // 512 B +#define EPI_HB16TIME_PSRAMSZ_1KB \ + 0x00040000 // 1024 B +#define EPI_HB16TIME_PSRAMSZ_2KB \ + 0x00050000 // 2048 B +#define EPI_HB16TIME_PSRAMSZ_4KB \ + 0x00060000 // 4096 B +#define EPI_HB16TIME_PSRAMSZ_8KB \ + 0x00070000 // 8192 B +#define EPI_HB16TIME_CAPWIDTH_M 0x00003000 // CS0n Inter-transfer Capture + // Width +#define EPI_HB16TIME_WRWSM 0x00000010 // Write Wait State Minus One +#define EPI_HB16TIME_RDWSM 0x00000001 // Read Wait State Minus One +#define EPI_HB16TIME_IRDYDLY_S 24 +#define EPI_HB16TIME_CAPWIDTH_S 12 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_HB8TIME2 register. +// +//***************************************************************************** +#define EPI_HB8TIME2_IRDYDLY_M 0x03000000 // CS1n Input Ready Delay +#define EPI_HB8TIME2_CAPWIDTH_M 0x00003000 // CS1n Inter-transfer Capture + // Width +#define EPI_HB8TIME2_WRWSM 0x00000010 // CS1n Write Wait State Minus One +#define EPI_HB8TIME2_RDWSM 0x00000001 // CS1n Read Wait State Minus One +#define EPI_HB8TIME2_IRDYDLY_S 24 +#define EPI_HB8TIME2_CAPWIDTH_S 12 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_HB16TIME2 +// register. +// +//***************************************************************************** +#define EPI_HB16TIME2_IRDYDLY_M 0x03000000 // CS1n Input Ready Delay +#define EPI_HB16TIME2_PSRAMSZ_M 0x00070000 // PSRAM Row Size +#define EPI_HB16TIME2_PSRAMSZ_0 0x00000000 // No row size limitation +#define EPI_HB16TIME2_PSRAMSZ_128B \ + 0x00010000 // 128 B +#define EPI_HB16TIME2_PSRAMSZ_256B \ + 0x00020000 // 256 B +#define EPI_HB16TIME2_PSRAMSZ_512B \ + 0x00030000 // 512 B +#define EPI_HB16TIME2_PSRAMSZ_1KB \ + 0x00040000 // 1024 B +#define EPI_HB16TIME2_PSRAMSZ_2KB \ + 0x00050000 // 2048 B +#define EPI_HB16TIME2_PSRAMSZ_4KB \ + 0x00060000 // 4096 B +#define EPI_HB16TIME2_PSRAMSZ_8KB \ + 0x00070000 // 8192 B +#define EPI_HB16TIME2_CAPWIDTH_M \ + 0x00003000 // CS1n Inter-transfer Capture + // Width +#define EPI_HB16TIME2_WRWSM 0x00000010 // CS1n Write Wait State Minus One +#define EPI_HB16TIME2_RDWSM 0x00000001 // CS1n Read Wait State Minus One +#define EPI_HB16TIME2_IRDYDLY_S 24 +#define EPI_HB16TIME2_CAPWIDTH_S \ + 12 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_HB16TIME3 +// register. +// +//***************************************************************************** +#define EPI_HB16TIME3_IRDYDLY_M 0x03000000 // CS2n Input Ready Delay +#define EPI_HB16TIME3_PSRAMSZ_M 0x00070000 // PSRAM Row Size +#define EPI_HB16TIME3_PSRAMSZ_0 0x00000000 // No row size limitation +#define EPI_HB16TIME3_PSRAMSZ_128B \ + 0x00010000 // 128 B +#define EPI_HB16TIME3_PSRAMSZ_256B \ + 0x00020000 // 256 B +#define EPI_HB16TIME3_PSRAMSZ_512B \ + 0x00030000 // 512 B +#define EPI_HB16TIME3_PSRAMSZ_1KB \ + 0x00040000 // 1024 B +#define EPI_HB16TIME3_PSRAMSZ_2KB \ + 0x00050000 // 2048 B +#define EPI_HB16TIME3_PSRAMSZ_4KB \ + 0x00060000 // 4096 B +#define EPI_HB16TIME3_PSRAMSZ_8KB \ + 0x00070000 // 8192 B +#define EPI_HB16TIME3_CAPWIDTH_M \ + 0x00003000 // CS2n Inter-transfer Capture + // Width +#define EPI_HB16TIME3_WRWSM 0x00000010 // CS2n Write Wait State Minus One +#define EPI_HB16TIME3_RDWSM 0x00000001 // CS2n Read Wait State Minus One +#define EPI_HB16TIME3_IRDYDLY_S 24 +#define EPI_HB16TIME3_CAPWIDTH_S \ + 12 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_HB8TIME3 register. +// +//***************************************************************************** +#define EPI_HB8TIME3_IRDYDLY_M 0x03000000 // CS2n Input Ready Delay +#define EPI_HB8TIME3_CAPWIDTH_M 0x00003000 // CS2n Inter-transfer Capture + // Width +#define EPI_HB8TIME3_WRWSM 0x00000010 // CS2n Write Wait State Minus One +#define EPI_HB8TIME3_RDWSM 0x00000001 // CS2n Read Wait State Minus One +#define EPI_HB8TIME3_IRDYDLY_S 24 +#define EPI_HB8TIME3_CAPWIDTH_S 12 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_HB8TIME4 register. +// +//***************************************************************************** +#define EPI_HB8TIME4_IRDYDLY_M 0x03000000 // CS3n Input Ready Delay +#define EPI_HB8TIME4_CAPWIDTH_M 0x00003000 // CS3n Inter-transfer Capture + // Width +#define EPI_HB8TIME4_WRWSM 0x00000010 // CS3n Write Wait State Minus One +#define EPI_HB8TIME4_RDWSM 0x00000001 // CS3n Read Wait State Minus One +#define EPI_HB8TIME4_IRDYDLY_S 24 +#define EPI_HB8TIME4_CAPWIDTH_S 12 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_HB16TIME4 +// register. +// +//***************************************************************************** +#define EPI_HB16TIME4_IRDYDLY_M 0x03000000 // CS3n Input Ready Delay +#define EPI_HB16TIME4_PSRAMSZ_M 0x00070000 // PSRAM Row Size +#define EPI_HB16TIME4_PSRAMSZ_0 0x00000000 // No row size limitation +#define EPI_HB16TIME4_PSRAMSZ_128B \ + 0x00010000 // 128 B +#define EPI_HB16TIME4_PSRAMSZ_256B \ + 0x00020000 // 256 B +#define EPI_HB16TIME4_PSRAMSZ_512B \ + 0x00030000 // 512 B +#define EPI_HB16TIME4_PSRAMSZ_1KB \ + 0x00040000 // 1024 B +#define EPI_HB16TIME4_PSRAMSZ_2KB \ + 0x00050000 // 2048 B +#define EPI_HB16TIME4_PSRAMSZ_4KB \ + 0x00060000 // 4096 B +#define EPI_HB16TIME4_PSRAMSZ_8KB \ + 0x00070000 // 8192 B +#define EPI_HB16TIME4_CAPWIDTH_M \ + 0x00003000 // CS3n Inter-transfer Capture + // Width +#define EPI_HB16TIME4_WRWSM 0x00000010 // CS3n Write Wait State Minus One +#define EPI_HB16TIME4_RDWSM 0x00000001 // CS3n Read Wait State Minus One +#define EPI_HB16TIME4_IRDYDLY_S 24 +#define EPI_HB16TIME4_CAPWIDTH_S \ + 12 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_HBPSRAM register. +// +//***************************************************************************** +#define EPI_HBPSRAM_CR_M 0x001FFFFF // PSRAM Config Register +#define EPI_HBPSRAM_CR_S 0 + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the EPI_O_FIFOLVL +// register. +// +//***************************************************************************** +#define EPI_FIFOLVL_WRFIFO_1_4 0x00000020 // Trigger when there are up to 3 + // spaces available in the WFIFO +#define EPI_FIFOLVL_WRFIFO_1_2 0x00000030 // Trigger when there are up to 2 + // spaces available in the WFIFO +#define EPI_FIFOLVL_WRFIFO_3_4 0x00000040 // Trigger when there is 1 space + // available in the WFIFO +#define EPI_FIFOLVL_RDFIFO_1_8 0x00000001 // Trigger when there are 1 or more + // entries in the NBRFIFO +#define EPI_FIFOLVL_RDFIFO_1_4 0x00000002 // Trigger when there are 2 or more + // entries in the NBRFIFO +#define EPI_FIFOLVL_RDFIFO_1_2 0x00000003 // Trigger when there are 4 or more + // entries in the NBRFIFO +#define EPI_FIFOLVL_RDFIFO_3_4 0x00000004 // Trigger when there are 6 or more + // entries in the NBRFIFO +#define EPI_FIFOLVL_RDFIFO_7_8 0x00000005 // Trigger when there are 7 or more + // entries in the NBRFIFO +#define EPI_FIFOLVL_RDFIFO_FULL 0x00000006 // Trigger when there are 8 entries + // in the NBRFIFO + +#endif + +#endif // __HW_EPI_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_fan.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_fan.h new file mode 100644 index 0000000000000000000000000000000000000000..9c191cf0af6b2a598b5d3cf923e5486fa7680dab --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_fan.h @@ -0,0 +1,49 @@ +//***************************************************************************** +// +// hw_fan.h - Macros used when accessing the fan control hardware. +// +// Copyright (c) 2010-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_FAN_H__ +#define __HW_FAN_H__ + +//***************************************************************************** +// +// The following are defines for the Fan Control register offsets. +// +//***************************************************************************** + +#endif // __HW_FAN_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_flash.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_flash.h new file mode 100644 index 0000000000000000000000000000000000000000..e38e85b59d0bac83af4d473395c4437c3c599ffe --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_flash.h @@ -0,0 +1,625 @@ +//***************************************************************************** +// +// hw_flash.h - Macros used when accessing the flash controller. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_FLASH_H__ +#define __HW_FLASH_H__ + +//***************************************************************************** +// +// The following are defines for the FLASH register offsets. +// +//***************************************************************************** +#define FLASH_FMA 0x400FD000 // Flash Memory Address +#define FLASH_FMD 0x400FD004 // Flash Memory Data +#define FLASH_FMC 0x400FD008 // Flash Memory Control +#define FLASH_FCRIS 0x400FD00C // Flash Controller Raw Interrupt + // Status +#define FLASH_FCIM 0x400FD010 // Flash Controller Interrupt Mask +#define FLASH_FCMISC 0x400FD014 // Flash Controller Masked + // Interrupt Status and Clear +#define FLASH_FMC2 0x400FD020 // Flash Memory Control 2 +#define FLASH_FWBVAL 0x400FD030 // Flash Write Buffer Valid +#define FLASH_FLPEKEY 0x400FD03C // Flash Program/Erase Key +#define FLASH_FWBN 0x400FD100 // Flash Write Buffer n +#define FLASH_PP 0x400FDFC0 // Flash Peripheral Properties +#define FLASH_FSIZE 0x400FDFC0 // Flash Size +#define FLASH_SSIZE 0x400FDFC4 // SRAM Size +#define FLASH_CONF 0x400FDFC8 // Flash Configuration Register +#define FLASH_ROMSWMAP 0x400FDFCC // ROM Software Map +#define FLASH_DMASZ 0x400FDFD0 // Flash DMA Address Size +#define FLASH_DMAST 0x400FDFD4 // Flash DMA Starting Address +#define FLASH_RVP 0x400FE0D4 // Reset Vector Pointer +#define FLASH_RMCTL 0x400FE0F0 // ROM Control +#define FLASH_BOOTCFG 0x400FE1D0 // Boot Configuration +#define FLASH_USERREG0 0x400FE1E0 // User Register 0 +#define FLASH_USERREG1 0x400FE1E4 // User Register 1 +#define FLASH_USERREG2 0x400FE1E8 // User Register 2 +#define FLASH_USERREG3 0x400FE1EC // User Register 3 +#define FLASH_FMPRE0 0x400FE200 // Flash Memory Protection Read + // Enable 0 +#define FLASH_FMPRE1 0x400FE204 // Flash Memory Protection Read + // Enable 1 +#define FLASH_FMPRE2 0x400FE208 // Flash Memory Protection Read + // Enable 2 +#define FLASH_FMPRE3 0x400FE20C // Flash Memory Protection Read + // Enable 3 +#define FLASH_FMPRE4 0x400FE210 // Flash Memory Protection Read + // Enable 4 +#define FLASH_FMPRE5 0x400FE214 // Flash Memory Protection Read + // Enable 5 +#define FLASH_FMPRE6 0x400FE218 // Flash Memory Protection Read + // Enable 6 +#define FLASH_FMPRE7 0x400FE21C // Flash Memory Protection Read + // Enable 7 +#define FLASH_FMPRE8 0x400FE220 // Flash Memory Protection Read + // Enable 8 +#define FLASH_FMPRE9 0x400FE224 // Flash Memory Protection Read + // Enable 9 +#define FLASH_FMPRE10 0x400FE228 // Flash Memory Protection Read + // Enable 10 +#define FLASH_FMPRE11 0x400FE22C // Flash Memory Protection Read + // Enable 11 +#define FLASH_FMPRE12 0x400FE230 // Flash Memory Protection Read + // Enable 12 +#define FLASH_FMPRE13 0x400FE234 // Flash Memory Protection Read + // Enable 13 +#define FLASH_FMPRE14 0x400FE238 // Flash Memory Protection Read + // Enable 14 +#define FLASH_FMPRE15 0x400FE23C // Flash Memory Protection Read + // Enable 15 +#define FLASH_FMPPE0 0x400FE400 // Flash Memory Protection Program + // Enable 0 +#define FLASH_FMPPE1 0x400FE404 // Flash Memory Protection Program + // Enable 1 +#define FLASH_FMPPE2 0x400FE408 // Flash Memory Protection Program + // Enable 2 +#define FLASH_FMPPE3 0x400FE40C // Flash Memory Protection Program + // Enable 3 +#define FLASH_FMPPE4 0x400FE410 // Flash Memory Protection Program + // Enable 4 +#define FLASH_FMPPE5 0x400FE414 // Flash Memory Protection Program + // Enable 5 +#define FLASH_FMPPE6 0x400FE418 // Flash Memory Protection Program + // Enable 6 +#define FLASH_FMPPE7 0x400FE41C // Flash Memory Protection Program + // Enable 7 +#define FLASH_FMPPE8 0x400FE420 // Flash Memory Protection Program + // Enable 8 +#define FLASH_FMPPE9 0x400FE424 // Flash Memory Protection Program + // Enable 9 +#define FLASH_FMPPE10 0x400FE428 // Flash Memory Protection Program + // Enable 10 +#define FLASH_FMPPE11 0x400FE42C // Flash Memory Protection Program + // Enable 11 +#define FLASH_FMPPE12 0x400FE430 // Flash Memory Protection Program + // Enable 12 +#define FLASH_FMPPE13 0x400FE434 // Flash Memory Protection Program + // Enable 13 +#define FLASH_FMPPE14 0x400FE438 // Flash Memory Protection Program + // Enable 14 +#define FLASH_FMPPE15 0x400FE43C // Flash Memory Protection Program + // Enable 15 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMA register. +// +//***************************************************************************** +#define FLASH_FMA_OFFSET_M 0x000FFFFF // Address Offset +#define FLASH_FMA_OFFSET_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMD register. +// +//***************************************************************************** +#define FLASH_FMD_DATA_M 0xFFFFFFFF // Data Value +#define FLASH_FMD_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMC register. +// +//***************************************************************************** +#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key +#define FLASH_FMC_COMT 0x00000008 // Commit Register Value +#define FLASH_FMC_MERASE 0x00000004 // Mass Erase Flash Memory +#define FLASH_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory +#define FLASH_FMC_WRITE 0x00000001 // Write a Word into Flash Memory + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FCRIS register. +// +//***************************************************************************** +#define FLASH_FCRIS_PROGRIS 0x00002000 // Program Verify Error Raw + // Interrupt Status +#define FLASH_FCRIS_ERRIS 0x00000800 // Erase Verify Error Raw Interrupt + // Status +#define FLASH_FCRIS_INVDRIS 0x00000400 // Invalid Data Raw Interrupt + // Status +#define FLASH_FCRIS_VOLTRIS 0x00000200 // Pump Voltage Raw Interrupt + // Status +#define FLASH_FCRIS_ERIS 0x00000004 // EEPROM Raw Interrupt Status +#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt Status +#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FCIM register. +// +//***************************************************************************** +#define FLASH_FCIM_PROGMASK 0x00002000 // PROGVER Interrupt Mask +#define FLASH_FCIM_ERMASK 0x00000800 // ERVER Interrupt Mask +#define FLASH_FCIM_INVDMASK 0x00000400 // Invalid Data Interrupt Mask +#define FLASH_FCIM_VOLTMASK 0x00000200 // VOLT Interrupt Mask +#define FLASH_FCIM_EMASK 0x00000004 // EEPROM Interrupt Mask +#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask +#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FCMISC register. +// +//***************************************************************************** +#define FLASH_FCMISC_PROGMISC 0x00002000 // PROGVER Masked Interrupt Status + // and Clear +#define FLASH_FCMISC_ERMISC 0x00000800 // ERVER Masked Interrupt Status + // and Clear +#define FLASH_FCMISC_INVDMISC 0x00000400 // Invalid Data Masked Interrupt + // Status and Clear +#define FLASH_FCMISC_VOLTMISC 0x00000200 // VOLT Masked Interrupt Status and + // Clear +#define FLASH_FCMISC_EMISC 0x00000004 // EEPROM Masked Interrupt Status + // and Clear +#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt + // Status and Clear +#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status + // and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMC2 register. +// +//***************************************************************************** +#define FLASH_FMC2_WRKEY 0xA4420000 // FLASH write key +#define FLASH_FMC2_WRBUF 0x00000001 // Buffered Flash Memory Write + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FWBVAL register. +// +//***************************************************************************** +#define FLASH_FWBVAL_FWB_M 0xFFFFFFFF // Flash Memory Write Buffer + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FLPEKEY register. +// +//***************************************************************************** +#define FLASH_FLPEKEY_PEKEY_M 0x0000FFFF // Key Value +#define FLASH_FLPEKEY_PEKEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FWBN register. +// +//***************************************************************************** +#define FLASH_FWBN_DATA_M 0xFFFFFFFF // Data + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_PP register. +// +//***************************************************************************** +#define FLASH_PP_PFC 0x40000000 // Prefetch Buffer Mode +#define FLASH_PP_FMM 0x20000000 // Flash Mirror Mode +#define FLASH_PP_DFA 0x10000000 // DMA Flash Access +#define FLASH_PP_EESS_M 0x00780000 // EEPROM Sector Size of the + // physical bank +#define FLASH_PP_EESS_1KB 0x00000000 // 1 KB +#define FLASH_PP_EESS_2KB 0x00080000 // 2 KB +#define FLASH_PP_EESS_4KB 0x00100000 // 4 KB +#define FLASH_PP_EESS_8KB 0x00180000 // 8 KB +#define FLASH_PP_MAINSS_M 0x00070000 // Flash Sector Size of the + // physical bank +#define FLASH_PP_MAINSS_1KB 0x00000000 // 1 KB +#define FLASH_PP_MAINSS_2KB 0x00010000 // 2 KB +#define FLASH_PP_MAINSS_4KB 0x00020000 // 4 KB +#define FLASH_PP_MAINSS_8KB 0x00030000 // 8 KB +#define FLASH_PP_MAINSS_16KB 0x00040000 // 16 KB +#define FLASH_PP_SIZE_M 0x0000FFFF // Flash Size +#define FLASH_PP_SIZE_512KB 0x000000FF // 512 KB of Flash +#define FLASH_PP_SIZE_1MB 0x000001FF // 1024 KB of Flash + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FSIZE register. +// +//***************************************************************************** +#define FLASH_FSIZE_SIZE_M 0x0000FFFF // Flash Size +#define FLASH_FSIZE_SIZE_32KB 0x0000000F // 32 KB of Flash +#define FLASH_FSIZE_SIZE_64KB 0x0000001F // 64 KB of Flash +#define FLASH_FSIZE_SIZE_128KB 0x0000003F // 128 KB of Flash +#define FLASH_FSIZE_SIZE_256KB 0x0000007F // 256 KB of Flash + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_SSIZE register. +// +//***************************************************************************** +#define FLASH_SSIZE_SIZE_M 0x0000FFFF // SRAM Size +#define FLASH_SSIZE_SIZE_12KB 0x0000002F // 12 KB of SRAM +#define FLASH_SSIZE_SIZE_24KB 0x0000005F // 24 KB of SRAM +#define FLASH_SSIZE_SIZE_32KB 0x0000007F // 32 KB of SRAM +#define FLASH_SSIZE_SIZE_256KB 0x000003FF // 256 KB of SRAM + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CONF register. +// +//***************************************************************************** +#define FLASH_CONF_FMME 0x40000000 // Flash Mirror Mode Enable +#define FLASH_CONF_SPFE 0x20000000 // Single Prefetch Mode Enable +#define FLASH_CONF_CLRTV 0x00100000 // Clear Valid Tags +#define FLASH_CONF_FPFON 0x00020000 // Force Prefetch On +#define FLASH_CONF_FPFOFF 0x00010000 // Force Prefetch Off + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_ROMSWMAP register. +// +//***************************************************************************** +#define FLASH_ROMSWMAP_SAFERTOS 0x00000001 // SafeRTOS Present +#define FLASH_ROMSWMAP_SW0EN_M 0x00000003 // ROM SW Region 0 Availability +#define FLASH_ROMSWMAP_SW0EN_NOTVIS \ + 0x00000000 // Software region not available to + // the core +#define FLASH_ROMSWMAP_SW0EN_CORE \ + 0x00000001 // Region available to core +#define FLASH_ROMSWMAP_SW1EN_M 0x0000000C // ROM SW Region 1 Availability +#define FLASH_ROMSWMAP_SW1EN_NOTVIS \ + 0x00000000 // Software region not available to + // the core +#define FLASH_ROMSWMAP_SW1EN_CORE \ + 0x00000004 // Region available to core +#define FLASH_ROMSWMAP_SW2EN_M 0x00000030 // ROM SW Region 2 Availability +#define FLASH_ROMSWMAP_SW2EN_NOTVIS \ + 0x00000000 // Software region not available to + // the core +#define FLASH_ROMSWMAP_SW2EN_CORE \ + 0x00000010 // Region available to core +#define FLASH_ROMSWMAP_SW3EN_M 0x000000C0 // ROM SW Region 3 Availability +#define FLASH_ROMSWMAP_SW3EN_NOTVIS \ + 0x00000000 // Software region not available to + // the core +#define FLASH_ROMSWMAP_SW3EN_CORE \ + 0x00000040 // Region available to core +#define FLASH_ROMSWMAP_SW4EN_M 0x00000300 // ROM SW Region 4 Availability +#define FLASH_ROMSWMAP_SW4EN_NOTVIS \ + 0x00000000 // Software region not available to + // the core +#define FLASH_ROMSWMAP_SW4EN_CORE \ + 0x00000100 // Region available to core +#define FLASH_ROMSWMAP_SW5EN_M 0x00000C00 // ROM SW Region 5 Availability +#define FLASH_ROMSWMAP_SW5EN_NOTVIS \ + 0x00000000 // Software region not available to + // the core +#define FLASH_ROMSWMAP_SW5EN_CORE \ + 0x00000400 // Region available to core +#define FLASH_ROMSWMAP_SW6EN_M 0x00003000 // ROM SW Region 6 Availability +#define FLASH_ROMSWMAP_SW6EN_NOTVIS \ + 0x00000000 // Software region not available to + // the core +#define FLASH_ROMSWMAP_SW6EN_CORE \ + 0x00001000 // Region available to core +#define FLASH_ROMSWMAP_SW7EN_M 0x0000C000 // ROM SW Region 7 Availability +#define FLASH_ROMSWMAP_SW7EN_NOTVIS \ + 0x00000000 // Software region not available to + // the core +#define FLASH_ROMSWMAP_SW7EN_CORE \ + 0x00004000 // Region available to core + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_DMASZ register. +// +//***************************************************************************** +#define FLASH_DMASZ_SIZE_M 0x0003FFFF // uDMA-accessible Memory Size +#define FLASH_DMASZ_SIZE_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_DMAST register. +// +//***************************************************************************** +#define FLASH_DMAST_ADDR_M 0x1FFFF800 // Contains the starting address of + // the flash region accessible by + // uDMA if the FLASHPP register DFA + // bit is set +#define FLASH_DMAST_ADDR_S 11 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_RVP register. +// +//***************************************************************************** +#define FLASH_RVP_RV_M 0xFFFFFFFF // Reset Vector Pointer Address +#define FLASH_RVP_RV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_RMCTL register. +// +//***************************************************************************** +#define FLASH_RMCTL_BA 0x00000001 // Boot Alias + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_BOOTCFG register. +// +//***************************************************************************** +#define FLASH_BOOTCFG_NW 0x80000000 // Not Written +#define FLASH_BOOTCFG_PORT_M 0x0000E000 // Boot GPIO Port +#define FLASH_BOOTCFG_PORT_A 0x00000000 // Port A +#define FLASH_BOOTCFG_PORT_B 0x00002000 // Port B +#define FLASH_BOOTCFG_PORT_C 0x00004000 // Port C +#define FLASH_BOOTCFG_PORT_D 0x00006000 // Port D +#define FLASH_BOOTCFG_PORT_E 0x00008000 // Port E +#define FLASH_BOOTCFG_PORT_F 0x0000A000 // Port F +#define FLASH_BOOTCFG_PORT_G 0x0000C000 // Port G +#define FLASH_BOOTCFG_PORT_H 0x0000E000 // Port H +#define FLASH_BOOTCFG_PIN_M 0x00001C00 // Boot GPIO Pin +#define FLASH_BOOTCFG_PIN_0 0x00000000 // Pin 0 +#define FLASH_BOOTCFG_PIN_1 0x00000400 // Pin 1 +#define FLASH_BOOTCFG_PIN_2 0x00000800 // Pin 2 +#define FLASH_BOOTCFG_PIN_3 0x00000C00 // Pin 3 +#define FLASH_BOOTCFG_PIN_4 0x00001000 // Pin 4 +#define FLASH_BOOTCFG_PIN_5 0x00001400 // Pin 5 +#define FLASH_BOOTCFG_PIN_6 0x00001800 // Pin 6 +#define FLASH_BOOTCFG_PIN_7 0x00001C00 // Pin 7 +#define FLASH_BOOTCFG_POL 0x00000200 // Boot GPIO Polarity +#define FLASH_BOOTCFG_EN 0x00000100 // Boot GPIO Enable +#define FLASH_BOOTCFG_KEY 0x00000010 // KEY Select +#define FLASH_BOOTCFG_DBG1 0x00000002 // Debug Control 1 +#define FLASH_BOOTCFG_DBG0 0x00000001 // Debug Control 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USERREG0 register. +// +//***************************************************************************** +#define FLASH_USERREG0_DATA_M 0xFFFFFFFF // User Data +#define FLASH_USERREG0_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USERREG1 register. +// +//***************************************************************************** +#define FLASH_USERREG1_DATA_M 0xFFFFFFFF // User Data +#define FLASH_USERREG1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USERREG2 register. +// +//***************************************************************************** +#define FLASH_USERREG2_DATA_M 0xFFFFFFFF // User Data +#define FLASH_USERREG2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USERREG3 register. +// +//***************************************************************************** +#define FLASH_USERREG3_DATA_M 0xFFFFFFFF // User Data +#define FLASH_USERREG3_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMPRE8 register. +// +//***************************************************************************** +#define FLASH_FMPRE8_READ_ENABLE_M \ + 0xFFFFFFFF // Flash Read Enable +#define FLASH_FMPRE8_READ_ENABLE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMPRE9 register. +// +//***************************************************************************** +#define FLASH_FMPRE9_READ_ENABLE_M \ + 0xFFFFFFFF // Flash Read Enable +#define FLASH_FMPRE9_READ_ENABLE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMPRE10 register. +// +//***************************************************************************** +#define FLASH_FMPRE10_READ_ENABLE_M \ + 0xFFFFFFFF // Flash Read Enable +#define FLASH_FMPRE10_READ_ENABLE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMPRE11 register. +// +//***************************************************************************** +#define FLASH_FMPRE11_READ_ENABLE_M \ + 0xFFFFFFFF // Flash Read Enable +#define FLASH_FMPRE11_READ_ENABLE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMPRE12 register. +// +//***************************************************************************** +#define FLASH_FMPRE12_READ_ENABLE_M \ + 0xFFFFFFFF // Flash Read Enable +#define FLASH_FMPRE12_READ_ENABLE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMPRE13 register. +// +//***************************************************************************** +#define FLASH_FMPRE13_READ_ENABLE_M \ + 0xFFFFFFFF // Flash Read Enable +#define FLASH_FMPRE13_READ_ENABLE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMPRE14 register. +// +//***************************************************************************** +#define FLASH_FMPRE14_READ_ENABLE_M \ + 0xFFFFFFFF // Flash Read Enable +#define FLASH_FMPRE14_READ_ENABLE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMPRE15 register. +// +//***************************************************************************** +#define FLASH_FMPRE15_READ_ENABLE_M \ + 0xFFFFFFFF // Flash Read Enable +#define FLASH_FMPRE15_READ_ENABLE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMPPE8 register. +// +//***************************************************************************** +#define FLASH_FMPPE8_PROG_ENABLE_M \ + 0xFFFFFFFF // Flash Programming Enable +#define FLASH_FMPPE8_PROG_ENABLE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMPPE9 register. +// +//***************************************************************************** +#define FLASH_FMPPE9_PROG_ENABLE_M \ + 0xFFFFFFFF // Flash Programming Enable +#define FLASH_FMPPE9_PROG_ENABLE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMPPE10 register. +// +//***************************************************************************** +#define FLASH_FMPPE10_PROG_ENABLE_M \ + 0xFFFFFFFF // Flash Programming Enable +#define FLASH_FMPPE10_PROG_ENABLE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMPPE11 register. +// +//***************************************************************************** +#define FLASH_FMPPE11_PROG_ENABLE_M \ + 0xFFFFFFFF // Flash Programming Enable +#define FLASH_FMPPE11_PROG_ENABLE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMPPE12 register. +// +//***************************************************************************** +#define FLASH_FMPPE12_PROG_ENABLE_M \ + 0xFFFFFFFF // Flash Programming Enable +#define FLASH_FMPPE12_PROG_ENABLE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMPPE13 register. +// +//***************************************************************************** +#define FLASH_FMPPE13_PROG_ENABLE_M \ + 0xFFFFFFFF // Flash Programming Enable +#define FLASH_FMPPE13_PROG_ENABLE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMPPE14 register. +// +//***************************************************************************** +#define FLASH_FMPPE14_PROG_ENABLE_M \ + 0xFFFFFFFF // Flash Programming Enable +#define FLASH_FMPPE14_PROG_ENABLE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMPPE15 register. +// +//***************************************************************************** +#define FLASH_FMPPE15_PROG_ENABLE_M \ + 0xFFFFFFFF // Flash Programming Enable +#define FLASH_FMPPE15_PROG_ENABLE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the erase size of the FLASH block that is +// erased by an erase operation, and the protect size is the size of the FLASH +// block that is protected by each protection register. +// +//***************************************************************************** +#define FLASH_PROTECT_SIZE 0x00000800 +#define FLASH_ERASE_SIZE 0x00000400 + +#endif // __HW_FLASH_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_gpio.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..9e95aed4355c92d49aabc2d60f8ed90a8287abb6 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_gpio.h @@ -0,0 +1,213 @@ +//***************************************************************************** +// +// hw_gpio.h - Defines and Macros for GPIO hardware. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_GPIO_H__ +#define __HW_GPIO_H__ + +//***************************************************************************** +// +// The following are defines for the GPIO register offsets. +// +//***************************************************************************** +#define GPIO_O_DATA 0x00000000 // GPIO Data +#define GPIO_O_DIR 0x00000400 // GPIO Direction +#define GPIO_O_IS 0x00000404 // GPIO Interrupt Sense +#define GPIO_O_IBE 0x00000408 // GPIO Interrupt Both Edges +#define GPIO_O_IEV 0x0000040C // GPIO Interrupt Event +#define GPIO_O_IM 0x00000410 // GPIO Interrupt Mask +#define GPIO_O_RIS 0x00000414 // GPIO Raw Interrupt Status +#define GPIO_O_MIS 0x00000418 // GPIO Masked Interrupt Status +#define GPIO_O_ICR 0x0000041C // GPIO Interrupt Clear +#define GPIO_O_AFSEL 0x00000420 // GPIO Alternate Function Select +#define GPIO_O_DR2R 0x00000500 // GPIO 2-mA Drive Select +#define GPIO_O_DR4R 0x00000504 // GPIO 4-mA Drive Select +#define GPIO_O_DR8R 0x00000508 // GPIO 8-mA Drive Select +#define GPIO_O_ODR 0x0000050C // GPIO Open Drain Select +#define GPIO_O_PUR 0x00000510 // GPIO Pull-Up Select +#define GPIO_O_PDR 0x00000514 // GPIO Pull-Down Select +#define GPIO_O_SLR 0x00000518 // GPIO Slew Rate Control Select +#define GPIO_O_DEN 0x0000051C // GPIO Digital Enable +#define GPIO_O_LOCK 0x00000520 // GPIO Lock +#define GPIO_O_CR 0x00000524 // GPIO Commit +#define GPIO_O_AMSEL 0x00000528 // GPIO Analog Mode Select +#define GPIO_O_PCTL 0x0000052C // GPIO Port Control +#define GPIO_O_ADCCTL 0x00000530 // GPIO ADC Control +#define GPIO_O_DMACTL 0x00000534 // GPIO DMA Control +#define GPIO_O_SI 0x00000538 // GPIO Select Interrupt +#define GPIO_O_DR12R 0x0000053C // GPIO 12-mA Drive Select +#define GPIO_O_WAKEPEN 0x00000540 // GPIO Wake Pin Enable +#define GPIO_O_WAKELVL 0x00000544 // GPIO Wake Level +#define GPIO_O_WAKESTAT 0x00000548 // GPIO Wake Status +#define GPIO_O_PP 0x00000FC0 // GPIO Peripheral Property +#define GPIO_O_PC 0x00000FC4 // GPIO Peripheral Configuration + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_IM register. +// +//***************************************************************************** +#define GPIO_IM_DMAIME 0x00000100 // GPIO uDMA Done Interrupt Mask + // Enable +#define GPIO_IM_GPIO_M 0x000000FF // GPIO Interrupt Mask Enable +#define GPIO_IM_GPIO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_RIS register. +// +//***************************************************************************** +#define GPIO_RIS_DMARIS 0x00000100 // GPIO uDMA Done Interrupt Raw + // Status +#define GPIO_RIS_GPIO_M 0x000000FF // GPIO Interrupt Raw Status +#define GPIO_RIS_GPIO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_MIS register. +// +//***************************************************************************** +#define GPIO_MIS_DMAMIS 0x00000100 // GPIO uDMA Done Masked Interrupt + // Status +#define GPIO_MIS_GPIO_M 0x000000FF // GPIO Masked Interrupt Status +#define GPIO_MIS_GPIO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_ICR register. +// +//***************************************************************************** +#define GPIO_ICR_DMAIC 0x00000100 // GPIO uDMA Interrupt Clear +#define GPIO_ICR_GPIO_M 0x000000FF // GPIO Interrupt Clear +#define GPIO_ICR_GPIO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_LOCK register. +// +//***************************************************************************** +#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock +#define GPIO_LOCK_UNLOCKED 0x00000000 // The GPIOCR register is unlocked + // and may be modified +#define GPIO_LOCK_LOCKED 0x00000001 // The GPIOCR register is locked + // and may not be modified +#define GPIO_LOCK_KEY 0x4C4F434B // Unlocks the GPIO_CR register + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_SI register. +// +//***************************************************************************** +#define GPIO_SI_SUM 0x00000001 // Summary Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_DR12R register. +// +//***************************************************************************** +#define GPIO_DR12R_DRV12_M 0x000000FF // Output Pad 12-mA Drive Enable +#define GPIO_DR12R_DRV12_12MA 0x00000001 // The corresponding GPIO pin has + // 12-mA drive. This encoding is + // only valid if the GPIOPP EDE bit + // is set and the appropriate + // GPIOPC EDM bit field is + // programmed to 0x3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_WAKEPEN register. +// +//***************************************************************************** +#define GPIO_WAKEPEN_WAKEP4 0x00000010 // P[4] Wake Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_WAKELVL register. +// +//***************************************************************************** +#define GPIO_WAKELVL_WAKELVL4 0x00000010 // P[4] Wake Level + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_WAKESTAT +// register. +// +//***************************************************************************** +#define GPIO_WAKESTAT_STAT4 0x00000010 // P[4] Wake Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_PP register. +// +//***************************************************************************** +#define GPIO_PP_EDE 0x00000001 // Extended Drive Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_PC register. +// +//***************************************************************************** +#define GPIO_PC_EDM7_M 0x0000C000 // Extended Drive Mode Bit 7 +#define GPIO_PC_EDM6_M 0x00003000 // Extended Drive Mode Bit 6 +#define GPIO_PC_EDM5_M 0x00000C00 // Extended Drive Mode Bit 5 +#define GPIO_PC_EDM4_M 0x00000300 // Extended Drive Mode Bit 4 +#define GPIO_PC_EDM3_M 0x000000C0 // Extended Drive Mode Bit 3 +#define GPIO_PC_EDM2_M 0x00000030 // Extended Drive Mode Bit 2 +#define GPIO_PC_EDM1_M 0x0000000C // Extended Drive Mode Bit 1 +#define GPIO_PC_EDM0_M 0x00000003 // Extended Drive Mode Bit 0 +#define GPIO_PC_EDM0_DISABLE 0x00000000 // Drive values of 2, 4 and 8 mA + // are maintained. GPIO n Drive + // Select (GPIODRnR) registers + // function as normal +#define GPIO_PC_EDM0_6MA 0x00000001 // An additional 6 mA option is + // provided +#define GPIO_PC_EDM0_PLUS2MA 0x00000003 // A 2 mA driver is always enabled; + // setting the corresponding + // GPIODR4R register bit adds 2 mA + // and setting the corresponding + // GPIODR8R of GPIODR12R register + // bit adds an additional 4 mA +#define GPIO_PC_EDM7_S 14 +#define GPIO_PC_EDM6_S 12 +#define GPIO_PC_EDM5_S 10 +#define GPIO_PC_EDM4_S 8 +#define GPIO_PC_EDM3_S 6 +#define GPIO_PC_EDM2_S 4 +#define GPIO_PC_EDM1_S 2 + +#endif // __HW_GPIO_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_hibernate.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_hibernate.h new file mode 100644 index 0000000000000000000000000000000000000000..ce469a20e1e30d4771add0725def7a5c742f9e66 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_hibernate.h @@ -0,0 +1,483 @@ +//***************************************************************************** +// +// hw_hibernate.h - Defines and Macros for the Hibernation module. +// +// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_HIBERNATE_H__ +#define __HW_HIBERNATE_H__ + +//***************************************************************************** +// +// The following are defines for the Hibernation module register addresses. +// +//***************************************************************************** +#define HIB_RTCC 0x400FC000 // Hibernation RTC Counter +#define HIB_RTCM0 0x400FC004 // Hibernation RTC Match 0 +#define HIB_RTCLD 0x400FC00C // Hibernation RTC Load +#define HIB_CTL 0x400FC010 // Hibernation Control +#define HIB_IM 0x400FC014 // Hibernation Interrupt Mask +#define HIB_RIS 0x400FC018 // Hibernation Raw Interrupt Status +#define HIB_MIS 0x400FC01C // Hibernation Masked Interrupt + // Status +#define HIB_IC 0x400FC020 // Hibernation Interrupt Clear +#define HIB_RTCT 0x400FC024 // Hibernation RTC Trim +#define HIB_RTCSS 0x400FC028 // Hibernation RTC Sub Seconds +#define HIB_IO 0x400FC02C // Hibernation IO Configuration +#define HIB_DATA 0x400FC030 // Hibernation Data +#define HIB_CALCTL 0x400FC300 // Hibernation Calendar Control +#define HIB_CAL0 0x400FC310 // Hibernation Calendar 0 +#define HIB_CAL1 0x400FC314 // Hibernation Calendar 1 +#define HIB_CALLD0 0x400FC320 // Hibernation Calendar Load 0 +#define HIB_CALLD1 0x400FC324 // Hibernation Calendar Load +#define HIB_CALM0 0x400FC330 // Hibernation Calendar Match 0 +#define HIB_CALM1 0x400FC334 // Hibernation Calendar Match 1 +#define HIB_LOCK 0x400FC360 // Hibernation Lock +#define HIB_TPCTL 0x400FC400 // HIB Tamper Control +#define HIB_TPSTAT 0x400FC404 // HIB Tamper Status +#define HIB_TPIO 0x400FC410 // HIB Tamper I/O Control +#define HIB_TPLOG0 0x400FC4E0 // HIB Tamper Log 0 +#define HIB_TPLOG1 0x400FC4E4 // HIB Tamper Log 1 +#define HIB_TPLOG2 0x400FC4E8 // HIB Tamper Log 2 +#define HIB_TPLOG3 0x400FC4EC // HIB Tamper Log 3 +#define HIB_TPLOG4 0x400FC4F0 // HIB Tamper Log 4 +#define HIB_TPLOG5 0x400FC4F4 // HIB Tamper Log 5 +#define HIB_TPLOG6 0x400FC4F8 // HIB Tamper Log 6 +#define HIB_TPLOG7 0x400FC4FC // HIB Tamper Log 7 +#define HIB_PP 0x400FCFC0 // Hibernation Peripheral + // Properties +#define HIB_CC 0x400FCFC8 // Hibernation Clock Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCC register. +// +//***************************************************************************** +#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter +#define HIB_RTCC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCM0 register. +// +//***************************************************************************** +#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0 +#define HIB_RTCM0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCLD register. +// +//***************************************************************************** +#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load +#define HIB_RTCLD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_CTL register. +// +//***************************************************************************** +#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable +#define HIB_CTL_RETCLR 0x40000000 // GPIO Retention/Clear +#define HIB_CTL_OSCSEL 0x00080000 // Oscillator Select +#define HIB_CTL_OSCDRV 0x00020000 // Oscillator Drive Capability +#define HIB_CTL_OSCBYP 0x00010000 // Oscillator Bypass +#define HIB_CTL_VBATSEL_M 0x00006000 // Select for Low-Battery + // Comparator +#define HIB_CTL_VBATSEL_1_9V 0x00000000 // 1.9 Volts +#define HIB_CTL_VBATSEL_2_1V 0x00002000 // 2.1 Volts (default) +#define HIB_CTL_VBATSEL_2_3V 0x00004000 // 2.3 Volts +#define HIB_CTL_VBATSEL_2_5V 0x00006000 // 2.5 Volts +#define HIB_CTL_BATCHK 0x00000400 // Check Battery Status +#define HIB_CTL_BATWKEN 0x00000200 // Wake on Low Battery +#define HIB_CTL_VDD3ON 0x00000100 // VDD Powered +#define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable +#define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable +#define HIB_CTL_PINWEN 0x00000010 // External Wake Pin Enable +#define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable +#define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request +#define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_IM register. +// +//***************************************************************************** +#define HIB_IM_VDDFAIL 0x00000080 // VDD Fail Interrupt Mask +#define HIB_IM_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Interrupt + // Mask +#define HIB_IM_PADIOWK 0x00000020 // Pad I/O Wake-Up Interrupt Mask +#define HIB_IM_WC 0x00000010 // External Write Complete/Capable + // Interrupt Mask +#define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask +#define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt + // Mask +#define HIB_IM_RTCALT0 0x00000001 // RTC Alert 0 Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RIS register. +// +//***************************************************************************** +#define HIB_RIS_VDDFAIL 0x00000080 // VDD Fail Raw Interrupt Status +#define HIB_RIS_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Raw + // Interrupt Status +#define HIB_RIS_PADIOWK 0x00000020 // Pad I/O Wake-Up Raw Interrupt + // Status +#define HIB_RIS_WC 0x00000010 // Write Complete/Capable Raw + // Interrupt Status +#define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt + // Status +#define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw + // Interrupt Status +#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert 0 Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_MIS register. +// +//***************************************************************************** +#define HIB_MIS_VDDFAIL 0x00000080 // VDD Fail Interrupt Mask +#define HIB_MIS_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Interrupt + // Mask +#define HIB_MIS_PADIOWK 0x00000020 // Pad I/O Wake-Up Interrupt Mask +#define HIB_MIS_WC 0x00000010 // Write Complete/Capable Masked + // Interrupt Status +#define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked + // Interrupt Status +#define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked + // Interrupt Status +#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert 0 Masked Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_IC register. +// +//***************************************************************************** +#define HIB_IC_VDDFAIL 0x00000080 // VDD Fail Interrupt Clear +#define HIB_IC_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Interrupt + // Clear +#define HIB_IC_PADIOWK 0x00000020 // Pad I/O Wake-Up Interrupt Clear +#define HIB_IC_WC 0x00000010 // Write Complete/Capable Interrupt + // Clear +#define HIB_IC_EXTW 0x00000008 // External Wake-Up Interrupt Clear +#define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Interrupt + // Clear +#define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCT register. +// +//***************************************************************************** +#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value +#define HIB_RTCT_TRIM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCSS register. +// +//***************************************************************************** +#define HIB_RTCSS_RTCSSM_M 0x7FFF0000 // RTC Sub Seconds Match +#define HIB_RTCSS_RTCSSC_M 0x00007FFF // RTC Sub Seconds Count +#define HIB_RTCSS_RTCSSM_S 16 +#define HIB_RTCSS_RTCSSC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_IO register. +// +//***************************************************************************** +#define HIB_IO_IOWRC 0x80000000 // I/O Write Complete +#define HIB_IO_WURSTEN 0x00000010 // Reset Wake Source Enable +#define HIB_IO_WUUNLK 0x00000001 // I/O Wake Pad Configuration + // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_DATA register. +// +//***************************************************************************** +#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV Data +#define HIB_DATA_RTD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_CALCTL register. +// +//***************************************************************************** +#define HIB_CALCTL_CAL24 0x00000004 // Calendar Mode +#define HIB_CALCTL_CALEN 0x00000001 // RTC Calendar/Counter Mode Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_CAL0 register. +// +//***************************************************************************** +#define HIB_CAL0_VALID 0x80000000 // Valid Calendar Load +#define HIB_CAL0_AMPM 0x00400000 // AM/PM Designation +#define HIB_CAL0_HR_M 0x001F0000 // Hours +#define HIB_CAL0_MIN_M 0x00003F00 // Minutes +#define HIB_CAL0_SEC_M 0x0000003F // Seconds +#define HIB_CAL0_HR_S 16 +#define HIB_CAL0_MIN_S 8 +#define HIB_CAL0_SEC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_CAL1 register. +// +//***************************************************************************** +#define HIB_CAL1_VALID 0x80000000 // Valid Calendar Load +#define HIB_CAL1_DOW_M 0x07000000 // Day of Week +#define HIB_CAL1_YEAR_M 0x007F0000 // Year Value +#define HIB_CAL1_MON_M 0x00000F00 // Month +#define HIB_CAL1_DOM_M 0x0000001F // Day of Month +#define HIB_CAL1_DOW_S 24 +#define HIB_CAL1_YEAR_S 16 +#define HIB_CAL1_MON_S 8 +#define HIB_CAL1_DOM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_CALLD0 register. +// +//***************************************************************************** +#define HIB_CALLD0_AMPM 0x00400000 // AM/PM Designation +#define HIB_CALLD0_HR_M 0x001F0000 // Hours +#define HIB_CALLD0_MIN_M 0x00003F00 // Minutes +#define HIB_CALLD0_SEC_M 0x0000003F // Seconds +#define HIB_CALLD0_HR_S 16 +#define HIB_CALLD0_MIN_S 8 +#define HIB_CALLD0_SEC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_CALLD1 register. +// +//***************************************************************************** +#define HIB_CALLD1_DOW_M 0x07000000 // Day of Week +#define HIB_CALLD1_YEAR_M 0x007F0000 // Year Value +#define HIB_CALLD1_MON_M 0x00000F00 // Month +#define HIB_CALLD1_DOM_M 0x0000001F // Day of Month +#define HIB_CALLD1_DOW_S 24 +#define HIB_CALLD1_YEAR_S 16 +#define HIB_CALLD1_MON_S 8 +#define HIB_CALLD1_DOM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_CALM0 register. +// +//***************************************************************************** +#define HIB_CALM0_AMPM 0x00400000 // AM/PM Designation +#define HIB_CALM0_HR_M 0x001F0000 // Hours +#define HIB_CALM0_MIN_M 0x00003F00 // Minutes +#define HIB_CALM0_SEC_M 0x0000003F // Seconds +#define HIB_CALM0_HR_S 16 +#define HIB_CALM0_MIN_S 8 +#define HIB_CALM0_SEC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_CALM1 register. +// +//***************************************************************************** +#define HIB_CALM1_DOM_M 0x0000001F // Day of Month +#define HIB_CALM1_DOM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_LOCK register. +// +//***************************************************************************** +#define HIB_LOCK_HIBLOCK_M 0xFFFFFFFF // HIbernate Lock +#define HIB_LOCK_HIBLOCK_KEY 0xA3359554 // Hibernate Lock Key +#define HIB_LOCK_HIBLOCK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_TPCTL register. +// +//***************************************************************************** +#define HIB_TPCTL_WAKE 0x00000800 // Wake from Hibernate on a Tamper + // Event +#define HIB_TPCTL_MEMCLR_M 0x00000300 // HIB Memory Clear on Tamper Event +#define HIB_TPCTL_MEMCLR_NONE 0x00000000 // Do not Clear HIB memory on + // tamper event +#define HIB_TPCTL_MEMCLR_LOW32 0x00000100 // Clear Lower 32 Bytes of HIB + // memory on tamper event +#define HIB_TPCTL_MEMCLR_HIGH32 0x00000200 // Clear upper 32 Bytes of HIB + // memory on tamper event +#define HIB_TPCTL_MEMCLR_ALL 0x00000300 // Clear all HIB memory on tamper + // event +#define HIB_TPCTL_TPCLR 0x00000010 // Tamper Event Clear +#define HIB_TPCTL_TPEN 0x00000001 // Tamper Module Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_TPSTAT register. +// +//***************************************************************************** +#define HIB_TPSTAT_STATE_M 0x0000000C // Tamper Module Status +#define HIB_TPSTAT_STATE_DISABLED \ + 0x00000000 // Tamper disabled +#define HIB_TPSTAT_STATE_CONFIGED \ + 0x00000004 // Tamper configured +#define HIB_TPSTAT_STATE_ERROR 0x00000008 // Tamper pin event occurred +#define HIB_TPSTAT_XOSCST 0x00000002 // External Oscillator Status +#define HIB_TPSTAT_XOSCFAIL 0x00000001 // External Oscillator Failure + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_TPIO register. +// +//***************************************************************************** +#define HIB_TPIO_GFLTR3 0x08000000 // TMPR3 Glitch Filtering +#define HIB_TPIO_PUEN3 0x04000000 // TMPR3 Internal Weak Pull-up + // Enable +#define HIB_TPIO_LEV3 0x02000000 // TMPR3 Trigger Level +#define HIB_TPIO_EN3 0x01000000 // TMPR3 Enable +#define HIB_TPIO_GFLTR2 0x00080000 // TMPR2 Glitch Filtering +#define HIB_TPIO_PUEN2 0x00040000 // TMPR2 Internal Weak Pull-up + // Enable +#define HIB_TPIO_LEV2 0x00020000 // TMPR2 Trigger Level +#define HIB_TPIO_EN2 0x00010000 // TMPR2 Enable +#define HIB_TPIO_GFLTR1 0x00000800 // TMPR1 Glitch Filtering +#define HIB_TPIO_PUEN1 0x00000400 // TMPR1 Internal Weak Pull-up + // Enable +#define HIB_TPIO_LEV1 0x00000200 // TMPR1 Trigger Level +#define HIB_TPIO_EN1 0x00000100 // TMPR1Enable +#define HIB_TPIO_GFLTR0 0x00000008 // TMPR0 Glitch Filtering +#define HIB_TPIO_PUEN0 0x00000004 // TMPR0 Internal Weak Pull-up + // Enable +#define HIB_TPIO_LEV0 0x00000002 // TMPR0 Trigger Level +#define HIB_TPIO_EN0 0x00000001 // TMPR0 Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_TPLOG0 register. +// +//***************************************************************************** +#define HIB_TPLOG0_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information +#define HIB_TPLOG0_TIME_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_TPLOG1 register. +// +//***************************************************************************** +#define HIB_TPLOG1_XOSC 0x00010000 // Status of external 32 +#define HIB_TPLOG1_TRIG3 0x00000008 // Status of TMPR[3] Trigger +#define HIB_TPLOG1_TRIG2 0x00000004 // Status of TMPR[2] Trigger +#define HIB_TPLOG1_TRIG1 0x00000002 // Status of TMPR[1] Trigger +#define HIB_TPLOG1_TRIG0 0x00000001 // Status of TMPR[0] Trigger + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_TPLOG2 register. +// +//***************************************************************************** +#define HIB_TPLOG2_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information +#define HIB_TPLOG2_TIME_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_TPLOG3 register. +// +//***************************************************************************** +#define HIB_TPLOG3_XOSC 0x00010000 // Status of external 32 +#define HIB_TPLOG3_TRIG3 0x00000008 // Status of TMPR[3] Trigger +#define HIB_TPLOG3_TRIG2 0x00000004 // Status of TMPR[2] Trigger +#define HIB_TPLOG3_TRIG1 0x00000002 // Status of TMPR[1] Trigger +#define HIB_TPLOG3_TRIG0 0x00000001 // Status of TMPR[0] Trigger + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_TPLOG4 register. +// +//***************************************************************************** +#define HIB_TPLOG4_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information +#define HIB_TPLOG4_TIME_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_TPLOG5 register. +// +//***************************************************************************** +#define HIB_TPLOG5_XOSC 0x00010000 // Status of external 32 +#define HIB_TPLOG5_TRIG3 0x00000008 // Status of TMPR[3] Trigger +#define HIB_TPLOG5_TRIG2 0x00000004 // Status of TMPR[2] Trigger +#define HIB_TPLOG5_TRIG1 0x00000002 // Status of TMPR[1] Trigger +#define HIB_TPLOG5_TRIG0 0x00000001 // Status of TMPR[0] Trigger + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_TPLOG6 register. +// +//***************************************************************************** +#define HIB_TPLOG6_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information +#define HIB_TPLOG6_TIME_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_TPLOG7 register. +// +//***************************************************************************** +#define HIB_TPLOG7_XOSC 0x00010000 // Status of external 32 +#define HIB_TPLOG7_TRIG3 0x00000008 // Status of TMPR[3] Trigger +#define HIB_TPLOG7_TRIG2 0x00000004 // Status of TMPR[2] Trigger +#define HIB_TPLOG7_TRIG1 0x00000002 // Status of TMPR[1] Trigger +#define HIB_TPLOG7_TRIG0 0x00000001 // Status of TMPR[0] Trigger + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_PP register. +// +//***************************************************************************** +#define HIB_PP_TAMPER 0x00000002 // Tamper Pin Presence +#define HIB_PP_WAKENC 0x00000001 // Wake Pin Presence + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_CC register. +// +//***************************************************************************** +#define HIB_CC_SYSCLKEN 0x00000001 // RTCOSC to System Clock Enable + +#endif // __HW_HIBERNATE_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_i2c.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_i2c.h new file mode 100644 index 0000000000000000000000000000000000000000..d9d00b5d57075ac2a1360406b2946f5901cbb0e6 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_i2c.h @@ -0,0 +1,470 @@ +//***************************************************************************** +// +// hw_i2c.h - Macros used when accessing the I2C master and slave hardware. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_I2C_H__ +#define __HW_I2C_H__ + +//***************************************************************************** +// +// The following are defines for the I2C register offsets. +// +//***************************************************************************** +#define I2C_O_MSA 0x00000000 // I2C Master Slave Address +#define I2C_O_MCS 0x00000004 // I2C Master Control/Status +#define I2C_O_MDR 0x00000008 // I2C Master Data +#define I2C_O_MTPR 0x0000000C // I2C Master Timer Period +#define I2C_O_MIMR 0x00000010 // I2C Master Interrupt Mask +#define I2C_O_MRIS 0x00000014 // I2C Master Raw Interrupt Status +#define I2C_O_MMIS 0x00000018 // I2C Master Masked Interrupt + // Status +#define I2C_O_MICR 0x0000001C // I2C Master Interrupt Clear +#define I2C_O_MCR 0x00000020 // I2C Master Configuration +#define I2C_O_MCLKOCNT 0x00000024 // I2C Master Clock Low Timeout + // Count +#define I2C_O_MBMON 0x0000002C // I2C Master Bus Monitor +#define I2C_O_MBLEN 0x00000030 // I2C Master Burst Length +#define I2C_O_MBCNT 0x00000034 // I2C Master Burst Count +#define I2C_O_MCR2 0x00000038 // I2C Master Configuration 2 +#define I2C_O_SOAR 0x00000800 // I2C Slave Own Address +#define I2C_O_SCSR 0x00000804 // I2C Slave Control/Status +#define I2C_O_SDR 0x00000808 // I2C Slave Data +#define I2C_O_SIMR 0x0000080C // I2C Slave Interrupt Mask +#define I2C_O_SRIS 0x00000810 // I2C Slave Raw Interrupt Status +#define I2C_O_SMIS 0x00000814 // I2C Slave Masked Interrupt + // Status +#define I2C_O_SICR 0x00000818 // I2C Slave Interrupt Clear +#define I2C_O_SOAR2 0x0000081C // I2C Slave Own Address 2 +#define I2C_O_SACKCTL 0x00000820 // I2C Slave ACK Control +#define I2C_O_FIFODATA 0x00000F00 // I2C FIFO Data +#define I2C_O_FIFOCTL 0x00000F04 // I2C FIFO Control +#define I2C_O_FIFOSTATUS 0x00000F08 // I2C FIFO Status +#define I2C_O_PP 0x00000FC0 // I2C Peripheral Properties +#define I2C_O_PC 0x00000FC4 // I2C Peripheral Configuration + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MSA register. +// +//***************************************************************************** +#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address +#define I2C_MSA_RS 0x00000001 // Receive not send +#define I2C_MSA_SA_S 1 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCS register. +// +//***************************************************************************** +#define I2C_MCS_ACTDMARX 0x80000000 // DMA RX Active Status +#define I2C_MCS_ACTDMATX 0x40000000 // DMA TX Active Status +#define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error +#define I2C_MCS_BURST 0x00000040 // Burst Enable +#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy +#define I2C_MCS_IDLE 0x00000020 // I2C Idle +#define I2C_MCS_QCMD 0x00000020 // Quick Command +#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost +#define I2C_MCS_HS 0x00000010 // High-Speed Enable +#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable +#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data +#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address +#define I2C_MCS_STOP 0x00000004 // Generate STOP +#define I2C_MCS_ERROR 0x00000002 // Error +#define I2C_MCS_START 0x00000002 // Generate START +#define I2C_MCS_RUN 0x00000001 // I2C Master Enable +#define I2C_MCS_BUSY 0x00000001 // I2C Busy + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MDR register. +// +//***************************************************************************** +#define I2C_MDR_DATA_M 0x000000FF // This byte contains the data + // transferred during a transaction +#define I2C_MDR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MTPR register. +// +//***************************************************************************** +#define I2C_MTPR_PULSEL_M 0x00070000 // Glitch Suppression Pulse Width +#define I2C_MTPR_PULSEL_BYPASS 0x00000000 // Bypass +#define I2C_MTPR_PULSEL_1 0x00010000 // 1 clock +#define I2C_MTPR_PULSEL_2 0x00020000 // 2 clocks +#define I2C_MTPR_PULSEL_3 0x00030000 // 3 clocks +#define I2C_MTPR_PULSEL_4 0x00040000 // 4 clocks +#define I2C_MTPR_PULSEL_8 0x00050000 // 8 clocks +#define I2C_MTPR_PULSEL_16 0x00060000 // 16 clocks +#define I2C_MTPR_PULSEL_31 0x00070000 // 31 clocks +#define I2C_MTPR_HS 0x00000080 // High-Speed Enable +#define I2C_MTPR_TPR_M 0x0000007F // Timer Period +#define I2C_MTPR_TPR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MIMR register. +// +//***************************************************************************** +#define I2C_MIMR_RXFFIM 0x00000800 // Receive FIFO Full Interrupt Mask +#define I2C_MIMR_TXFEIM 0x00000400 // Transmit FIFO Empty Interrupt + // Mask +#define I2C_MIMR_RXIM 0x00000200 // Receive FIFO Request Interrupt + // Mask +#define I2C_MIMR_TXIM 0x00000100 // Transmit FIFO Request Interrupt + // Mask +#define I2C_MIMR_ARBLOSTIM 0x00000080 // Arbitration Lost Interrupt Mask +#define I2C_MIMR_STOPIM 0x00000040 // STOP Detection Interrupt Mask +#define I2C_MIMR_STARTIM 0x00000020 // START Detection Interrupt Mask +#define I2C_MIMR_NACKIM 0x00000010 // Address/Data NACK Interrupt Mask +#define I2C_MIMR_DMATXIM 0x00000008 // Transmit DMA Interrupt Mask +#define I2C_MIMR_DMARXIM 0x00000004 // Receive DMA Interrupt Mask +#define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask +#define I2C_MIMR_IM 0x00000001 // Master Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MRIS register. +// +//***************************************************************************** +#define I2C_MRIS_RXFFRIS 0x00000800 // Receive FIFO Full Raw Interrupt + // Status +#define I2C_MRIS_TXFERIS 0x00000400 // Transmit FIFO Empty Raw + // Interrupt Status +#define I2C_MRIS_RXRIS 0x00000200 // Receive FIFO Request Raw + // Interrupt Status +#define I2C_MRIS_TXRIS 0x00000100 // Transmit Request Raw Interrupt + // Status +#define I2C_MRIS_ARBLOSTRIS 0x00000080 // Arbitration Lost Raw Interrupt + // Status +#define I2C_MRIS_STOPRIS 0x00000040 // STOP Detection Raw Interrupt + // Status +#define I2C_MRIS_STARTRIS 0x00000020 // START Detection Raw Interrupt + // Status +#define I2C_MRIS_NACKRIS 0x00000010 // Address/Data NACK Raw Interrupt + // Status +#define I2C_MRIS_DMATXRIS 0x00000008 // Transmit DMA Raw Interrupt + // Status +#define I2C_MRIS_DMARXRIS 0x00000004 // Receive DMA Raw Interrupt Status +#define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt + // Status +#define I2C_MRIS_RIS 0x00000001 // Master Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MMIS register. +// +//***************************************************************************** +#define I2C_MMIS_RXFFMIS 0x00000800 // Receive FIFO Full Interrupt Mask +#define I2C_MMIS_TXFEMIS 0x00000400 // Transmit FIFO Empty Interrupt + // Mask +#define I2C_MMIS_RXMIS 0x00000200 // Receive FIFO Request Interrupt + // Mask +#define I2C_MMIS_TXMIS 0x00000100 // Transmit Request Interrupt Mask +#define I2C_MMIS_ARBLOSTMIS 0x00000080 // Arbitration Lost Interrupt Mask +#define I2C_MMIS_STOPMIS 0x00000040 // STOP Detection Interrupt Mask +#define I2C_MMIS_STARTMIS 0x00000020 // START Detection Interrupt Mask +#define I2C_MMIS_NACKMIS 0x00000010 // Address/Data NACK Interrupt Mask +#define I2C_MMIS_DMATXMIS 0x00000008 // Transmit DMA Interrupt Status +#define I2C_MMIS_DMARXMIS 0x00000004 // Receive DMA Interrupt Status +#define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt + // Status +#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MICR register. +// +//***************************************************************************** +#define I2C_MICR_RXFFIC 0x00000800 // Receive FIFO Full Interrupt + // Clear +#define I2C_MICR_TXFEIC 0x00000400 // Transmit FIFO Empty Interrupt + // Clear +#define I2C_MICR_RXIC 0x00000200 // Receive FIFO Request Interrupt + // Clear +#define I2C_MICR_TXIC 0x00000100 // Transmit FIFO Request Interrupt + // Clear +#define I2C_MICR_ARBLOSTIC 0x00000080 // Arbitration Lost Interrupt Clear +#define I2C_MICR_STOPIC 0x00000040 // STOP Detection Interrupt Clear +#define I2C_MICR_STARTIC 0x00000020 // START Detection Interrupt Clear +#define I2C_MICR_NACKIC 0x00000010 // Address/Data NACK Interrupt + // Clear +#define I2C_MICR_DMATXIC 0x00000008 // Transmit DMA Interrupt Clear +#define I2C_MICR_DMARXIC 0x00000004 // Receive DMA Interrupt Clear +#define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear +#define I2C_MICR_IC 0x00000001 // Master Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCR register. +// +//***************************************************************************** +#define I2C_MCR_GFE 0x00000040 // I2C Glitch Filter Enable +#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable +#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable +#define I2C_MCR_LPBK 0x00000001 // I2C Loopback + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCLKOCNT register. +// +//***************************************************************************** +#define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count +#define I2C_MCLKOCNT_CNTL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MBMON register. +// +//***************************************************************************** +#define I2C_MBMON_SDA 0x00000002 // I2C SDA Status +#define I2C_MBMON_SCL 0x00000001 // I2C SCL Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MBLEN register. +// +//***************************************************************************** +#define I2C_MBLEN_CNTL_M 0x000000FF // I2C Burst Length +#define I2C_MBLEN_CNTL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MBCNT register. +// +//***************************************************************************** +#define I2C_MBCNT_CNTL_M 0x000000FF // I2C Master Burst Count +#define I2C_MBCNT_CNTL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCR2 register. +// +//***************************************************************************** +#define I2C_MCR2_GFPW_M 0x00000070 // I2C Glitch Filter Pulse Width +#define I2C_MCR2_GFPW_BYPASS 0x00000000 // Bypass +#define I2C_MCR2_GFPW_1 0x00000010 // 1 clock +#define I2C_MCR2_GFPW_2 0x00000020 // 2 clocks +#define I2C_MCR2_GFPW_3 0x00000030 // 3 clocks +#define I2C_MCR2_GFPW_4 0x00000040 // 4 clocks +#define I2C_MCR2_GFPW_8 0x00000050 // 8 clocks +#define I2C_MCR2_GFPW_16 0x00000060 // 16 clocks +#define I2C_MCR2_GFPW_31 0x00000070 // 31 clocks + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SOAR register. +// +//***************************************************************************** +#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address +#define I2C_SOAR_OAR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SCSR register. +// +//***************************************************************************** +#define I2C_SCSR_ACTDMARX 0x80000000 // DMA RX Active Status +#define I2C_SCSR_ACTDMATX 0x40000000 // DMA TX Active Status +#define I2C_SCSR_QCMDRW 0x00000020 // Quick Command Read / Write +#define I2C_SCSR_QCMDST 0x00000010 // Quick Command Status +#define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched +#define I2C_SCSR_FBR 0x00000004 // First Byte Received +#define I2C_SCSR_RXFIFO 0x00000004 // RX FIFO Enable +#define I2C_SCSR_TXFIFO 0x00000002 // TX FIFO Enable +#define I2C_SCSR_TREQ 0x00000002 // Transmit Request +#define I2C_SCSR_DA 0x00000001 // Device Active +#define I2C_SCSR_RREQ 0x00000001 // Receive Request + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SDR register. +// +//***************************************************************************** +#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer +#define I2C_SDR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SIMR register. +// +//***************************************************************************** +#define I2C_SIMR_RXFFIM 0x00000100 // Receive FIFO Full Interrupt Mask +#define I2C_SIMR_TXFEIM 0x00000080 // Transmit FIFO Empty Interrupt + // Mask +#define I2C_SIMR_RXIM 0x00000040 // Receive FIFO Request Interrupt + // Mask +#define I2C_SIMR_TXIM 0x00000020 // Transmit FIFO Request Interrupt + // Mask +#define I2C_SIMR_DMATXIM 0x00000010 // Transmit DMA Interrupt Mask +#define I2C_SIMR_DMARXIM 0x00000008 // Receive DMA Interrupt Mask +#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask +#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask +#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SRIS register. +// +//***************************************************************************** +#define I2C_SRIS_RXFFRIS 0x00000100 // Receive FIFO Full Raw Interrupt + // Status +#define I2C_SRIS_TXFERIS 0x00000080 // Transmit FIFO Empty Raw + // Interrupt Status +#define I2C_SRIS_RXRIS 0x00000040 // Receive FIFO Request Raw + // Interrupt Status +#define I2C_SRIS_TXRIS 0x00000020 // Transmit Request Raw Interrupt + // Status +#define I2C_SRIS_DMATXRIS 0x00000010 // Transmit DMA Raw Interrupt + // Status +#define I2C_SRIS_DMARXRIS 0x00000008 // Receive DMA Raw Interrupt Status +#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt + // Status +#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt + // Status +#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SMIS register. +// +//***************************************************************************** +#define I2C_SMIS_RXFFMIS 0x00000100 // Receive FIFO Full Interrupt Mask +#define I2C_SMIS_TXFEMIS 0x00000080 // Transmit FIFO Empty Interrupt + // Mask +#define I2C_SMIS_RXMIS 0x00000040 // Receive FIFO Request Interrupt + // Mask +#define I2C_SMIS_TXMIS 0x00000020 // Transmit FIFO Request Interrupt + // Mask +#define I2C_SMIS_DMATXMIS 0x00000010 // Transmit DMA Masked Interrupt + // Status +#define I2C_SMIS_DMARXMIS 0x00000008 // Receive DMA Masked Interrupt + // Status +#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt + // Status +#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt + // Status +#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SICR register. +// +//***************************************************************************** +#define I2C_SICR_RXFFIC 0x00000100 // Receive FIFO Full Interrupt Mask +#define I2C_SICR_TXFEIC 0x00000080 // Transmit FIFO Empty Interrupt + // Mask +#define I2C_SICR_RXIC 0x00000040 // Receive Request Interrupt Mask +#define I2C_SICR_TXIC 0x00000020 // Transmit Request Interrupt Mask +#define I2C_SICR_DMATXIC 0x00000010 // Transmit DMA Interrupt Clear +#define I2C_SICR_DMARXIC 0x00000008 // Receive DMA Interrupt Clear +#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear +#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear +#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SOAR2 register. +// +//***************************************************************************** +#define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable +#define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2 +#define I2C_SOAR2_OAR2_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SACKCTL register. +// +//***************************************************************************** +#define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value +#define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_FIFODATA register. +// +//***************************************************************************** +#define I2C_FIFODATA_DATA_M 0x000000FF // I2C TX FIFO Write Data Byte +#define I2C_FIFODATA_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_FIFOCTL register. +// +//***************************************************************************** +#define I2C_FIFOCTL_RXASGNMT 0x80000000 // RX Control Assignment +#define I2C_FIFOCTL_RXFLUSH 0x40000000 // RX FIFO Flush +#define I2C_FIFOCTL_DMARXENA 0x20000000 // DMA RX Channel Enable +#define I2C_FIFOCTL_RXTRIG_M 0x00070000 // RX FIFO Trigger +#define I2C_FIFOCTL_TXASGNMT 0x00008000 // TX Control Assignment +#define I2C_FIFOCTL_TXFLUSH 0x00004000 // TX FIFO Flush +#define I2C_FIFOCTL_DMATXENA 0x00002000 // DMA TX Channel Enable +#define I2C_FIFOCTL_TXTRIG_M 0x00000007 // TX FIFO Trigger +#define I2C_FIFOCTL_RXTRIG_S 16 +#define I2C_FIFOCTL_TXTRIG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_FIFOSTATUS +// register. +// +//***************************************************************************** +#define I2C_FIFOSTATUS_RXABVTRIG \ + 0x00040000 // RX FIFO Above Trigger Level +#define I2C_FIFOSTATUS_RXFF 0x00020000 // RX FIFO Full +#define I2C_FIFOSTATUS_RXFE 0x00010000 // RX FIFO Empty +#define I2C_FIFOSTATUS_TXBLWTRIG \ + 0x00000004 // TX FIFO Below Trigger Level +#define I2C_FIFOSTATUS_TXFF 0x00000002 // TX FIFO Full +#define I2C_FIFOSTATUS_TXFE 0x00000001 // TX FIFO Empty + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_PP register. +// +//***************************************************************************** +#define I2C_PP_HS 0x00000001 // High-Speed Capable + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_PC register. +// +//***************************************************************************** +#define I2C_PC_HS 0x00000001 // High-Speed Capable + +#endif // __HW_I2C_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_ints.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_ints.h new file mode 100644 index 0000000000000000000000000000000000000000..c75a84a6bbb45847200bf663f4cc6bc6efda731d --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_ints.h @@ -0,0 +1,491 @@ +//***************************************************************************** +// +// hw_ints.h - Macros that define the interrupt assignment on Tiva C Series +// MCUs. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_INTS_H__ +#define __HW_INTS_H__ + +//***************************************************************************** +// +// The following are defines for the fault assignments. +// +//***************************************************************************** +#define FAULT_NMI 2 // NMI fault +#define FAULT_HARD 3 // Hard fault +#define FAULT_MPU 4 // MPU fault +#define FAULT_BUS 5 // Bus fault +#define FAULT_USAGE 6 // Usage fault +#define FAULT_SVCALL 11 // SVCall +#define FAULT_DEBUG 12 // Debug monitor +#define FAULT_PENDSV 14 // PendSV +#define FAULT_SYSTICK 15 // System Tick + +//***************************************************************************** +// +// TM4C123 Class Interrupts +// +//***************************************************************************** +#define INT_GPIOA_TM4C123 16 // GPIO Port A +#define INT_GPIOB_TM4C123 17 // GPIO Port B +#define INT_GPIOC_TM4C123 18 // GPIO Port C +#define INT_GPIOD_TM4C123 19 // GPIO Port D +#define INT_GPIOE_TM4C123 20 // GPIO Port E +#define INT_UART0_TM4C123 21 // UART0 +#define INT_UART1_TM4C123 22 // UART1 +#define INT_SSI0_TM4C123 23 // SSI0 +#define INT_I2C0_TM4C123 24 // I2C0 +#define INT_PWM0_FAULT_TM4C123 25 // PWM0 Fault +#define INT_PWM0_0_TM4C123 26 // PWM0 Generator 0 +#define INT_PWM0_1_TM4C123 27 // PWM0 Generator 1 +#define INT_PWM0_2_TM4C123 28 // PWM0 Generator 2 +#define INT_QEI0_TM4C123 29 // QEI0 +#define INT_ADC0SS0_TM4C123 30 // ADC0 Sequence 0 +#define INT_ADC0SS1_TM4C123 31 // ADC0 Sequence 1 +#define INT_ADC0SS2_TM4C123 32 // ADC0 Sequence 2 +#define INT_ADC0SS3_TM4C123 33 // ADC0 Sequence 3 +#define INT_WATCHDOG_TM4C123 34 // Watchdog Timers 0 and 1 +#define INT_TIMER0A_TM4C123 35 // 16/32-Bit Timer 0A +#define INT_TIMER0B_TM4C123 36 // 16/32-Bit Timer 0B +#define INT_TIMER1A_TM4C123 37 // 16/32-Bit Timer 1A +#define INT_TIMER1B_TM4C123 38 // 16/32-Bit Timer 1B +#define INT_TIMER2A_TM4C123 39 // 16/32-Bit Timer 2A +#define INT_TIMER2B_TM4C123 40 // 16/32-Bit Timer 2B +#define INT_COMP0_TM4C123 41 // Analog Comparator 0 +#define INT_COMP1_TM4C123 42 // Analog Comparator 1 +#define INT_COMP2_TM4C123 43 // Analog Comparator 2 +#define INT_SYSCTL_TM4C123 44 // System Control +#define INT_FLASH_TM4C123 45 // Flash Memory Control and EEPROM + // Control +#define INT_GPIOF_TM4C123 46 // GPIO Port F +#define INT_GPIOG_TM4C123 47 // GPIO Port G +#define INT_GPIOH_TM4C123 48 // GPIO Port H +#define INT_UART2_TM4C123 49 // UART2 +#define INT_SSI1_TM4C123 50 // SSI1 +#define INT_TIMER3A_TM4C123 51 // 16/32-Bit Timer 3A +#define INT_TIMER3B_TM4C123 52 // Timer 3B +#define INT_I2C1_TM4C123 53 // I2C1 +#define INT_QEI1_TM4C123 54 // QEI1 +#define INT_CAN0_TM4C123 55 // CAN0 +#define INT_CAN1_TM4C123 56 // CAN1 +#define INT_HIBERNATE_TM4C123 59 // Hibernation Module +#define INT_USB0_TM4C123 60 // USB +#define INT_PWM0_3_TM4C123 61 // PWM Generator 3 +#define INT_UDMA_TM4C123 62 // uDMA Software +#define INT_UDMAERR_TM4C123 63 // uDMA Error +#define INT_ADC1SS0_TM4C123 64 // ADC1 Sequence 0 +#define INT_ADC1SS1_TM4C123 65 // ADC1 Sequence 1 +#define INT_ADC1SS2_TM4C123 66 // ADC1 Sequence 2 +#define INT_ADC1SS3_TM4C123 67 // ADC1 Sequence 3 +#define INT_GPIOJ_TM4C123 70 // GPIO Port J +#define INT_GPIOK_TM4C123 71 // GPIO Port K +#define INT_GPIOL_TM4C123 72 // GPIO Port L +#define INT_SSI2_TM4C123 73 // SSI2 +#define INT_SSI3_TM4C123 74 // SSI3 +#define INT_UART3_TM4C123 75 // UART3 +#define INT_UART4_TM4C123 76 // UART4 +#define INT_UART5_TM4C123 77 // UART5 +#define INT_UART6_TM4C123 78 // UART6 +#define INT_UART7_TM4C123 79 // UART7 +#define INT_I2C2_TM4C123 84 // I2C2 +#define INT_I2C3_TM4C123 85 // I2C3 +#define INT_TIMER4A_TM4C123 86 // 16/32-Bit Timer 4A +#define INT_TIMER4B_TM4C123 87 // 16/32-Bit Timer 4B +#define INT_TIMER5A_TM4C123 108 // 16/32-Bit Timer 5A +#define INT_TIMER5B_TM4C123 109 // 16/32-Bit Timer 5B +#define INT_WTIMER0A_TM4C123 110 // 32/64-Bit Timer 0A +#define INT_WTIMER0B_TM4C123 111 // 32/64-Bit Timer 0B +#define INT_WTIMER1A_TM4C123 112 // 32/64-Bit Timer 1A +#define INT_WTIMER1B_TM4C123 113 // 32/64-Bit Timer 1B +#define INT_WTIMER2A_TM4C123 114 // 32/64-Bit Timer 2A +#define INT_WTIMER2B_TM4C123 115 // 32/64-Bit Timer 2B +#define INT_WTIMER3A_TM4C123 116 // 32/64-Bit Timer 3A +#define INT_WTIMER3B_TM4C123 117 // 32/64-Bit Timer 3B +#define INT_WTIMER4A_TM4C123 118 // 32/64-Bit Timer 4A +#define INT_WTIMER4B_TM4C123 119 // 32/64-Bit Timer 4B +#define INT_WTIMER5A_TM4C123 120 // 32/64-Bit Timer 5A +#define INT_WTIMER5B_TM4C123 121 // 32/64-Bit Timer 5B +#define INT_SYSEXC_TM4C123 122 // System Exception (imprecise) +#define INT_I2C4_TM4C123 125 // I2C4 +#define INT_I2C5_TM4C123 126 // I2C5 +#define INT_GPIOM_TM4C123 127 // GPIO Port M +#define INT_GPION_TM4C123 128 // GPIO Port N +#define INT_GPIOP0_TM4C123 132 // GPIO Port P (Summary or P0) +#define INT_GPIOP1_TM4C123 133 // GPIO Port P1 +#define INT_GPIOP2_TM4C123 134 // GPIO Port P2 +#define INT_GPIOP3_TM4C123 135 // GPIO Port P3 +#define INT_GPIOP4_TM4C123 136 // GPIO Port P4 +#define INT_GPIOP5_TM4C123 137 // GPIO Port P5 +#define INT_GPIOP6_TM4C123 138 // GPIO Port P6 +#define INT_GPIOP7_TM4C123 139 // GPIO Port P7 +#define INT_GPIOQ0_TM4C123 140 // GPIO Port Q (Summary or Q0) +#define INT_GPIOQ1_TM4C123 141 // GPIO Port Q1 +#define INT_GPIOQ2_TM4C123 142 // GPIO Port Q2 +#define INT_GPIOQ3_TM4C123 143 // GPIO Port Q3 +#define INT_GPIOQ4_TM4C123 144 // GPIO Port Q4 +#define INT_GPIOQ5_TM4C123 145 // GPIO Port Q5 +#define INT_GPIOQ6_TM4C123 146 // GPIO Port Q6 +#define INT_GPIOQ7_TM4C123 147 // GPIO Port Q7 +#define INT_PWM1_0_TM4C123 150 // PWM1 Generator 0 +#define INT_PWM1_1_TM4C123 151 // PWM1 Generator 1 +#define INT_PWM1_2_TM4C123 152 // PWM1 Generator 2 +#define INT_PWM1_3_TM4C123 153 // PWM1 Generator 3 +#define INT_PWM1_FAULT_TM4C123 154 // PWM1 Fault +#define NUM_INTERRUPTS_TM4C123 155 + +//***************************************************************************** +// +// TM4C129 Class Interrupts +// +//***************************************************************************** +#define INT_GPIOA_TM4C129 16 // GPIO Port A +#define INT_GPIOB_TM4C129 17 // GPIO Port B +#define INT_GPIOC_TM4C129 18 // GPIO Port C +#define INT_GPIOD_TM4C129 19 // GPIO Port D +#define INT_GPIOE_TM4C129 20 // GPIO Port E +#define INT_UART0_TM4C129 21 // UART0 +#define INT_UART1_TM4C129 22 // UART1 +#define INT_SSI0_TM4C129 23 // SSI0 +#define INT_I2C0_TM4C129 24 // I2C0 +#define INT_PWM0_FAULT_TM4C129 25 // PWM Fault +#define INT_PWM0_0_TM4C129 26 // PWM Generator 0 +#define INT_PWM0_1_TM4C129 27 // PWM Generator 1 +#define INT_PWM0_2_TM4C129 28 // PWM Generator 2 +#define INT_QEI0_TM4C129 29 // QEI0 +#define INT_ADC0SS0_TM4C129 30 // ADC0 Sequence 0 +#define INT_ADC0SS1_TM4C129 31 // ADC0 Sequence 1 +#define INT_ADC0SS2_TM4C129 32 // ADC0 Sequence 2 +#define INT_ADC0SS3_TM4C129 33 // ADC0 Sequence 3 +#define INT_WATCHDOG_TM4C129 34 // Watchdog Timers 0 and 1 +#define INT_TIMER0A_TM4C129 35 // 16/32-Bit Timer 0A +#define INT_TIMER0B_TM4C129 36 // 16/32-Bit Timer 0B +#define INT_TIMER1A_TM4C129 37 // 16/32-Bit Timer 1A +#define INT_TIMER1B_TM4C129 38 // 16/32-Bit Timer 1B +#define INT_TIMER2A_TM4C129 39 // 16/32-Bit Timer 2A +#define INT_TIMER2B_TM4C129 40 // 16/32-Bit Timer 2B +#define INT_COMP0_TM4C129 41 // Analog Comparator 0 +#define INT_COMP1_TM4C129 42 // Analog Comparator 1 +#define INT_COMP2_TM4C129 43 // Analog Comparator 2 +#define INT_SYSCTL_TM4C129 44 // System Control +#define INT_FLASH_TM4C129 45 // Flash Memory Control +#define INT_GPIOF_TM4C129 46 // GPIO Port F +#define INT_GPIOG_TM4C129 47 // GPIO Port G +#define INT_GPIOH_TM4C129 48 // GPIO Port H +#define INT_UART2_TM4C129 49 // UART2 +#define INT_SSI1_TM4C129 50 // SSI1 +#define INT_TIMER3A_TM4C129 51 // 16/32-Bit Timer 3A +#define INT_TIMER3B_TM4C129 52 // 16/32-Bit Timer 3B +#define INT_I2C1_TM4C129 53 // I2C1 +#define INT_CAN0_TM4C129 54 // CAN 0 +#define INT_CAN1_TM4C129 55 // CAN1 +#define INT_EMAC0_TM4C129 56 // Ethernet MAC +#define INT_HIBERNATE_TM4C129 57 // HIB +#define INT_USB0_TM4C129 58 // USB MAC +#define INT_PWM0_3_TM4C129 59 // PWM Generator 3 +#define INT_UDMA_TM4C129 60 // uDMA 0 Software +#define INT_UDMAERR_TM4C129 61 // uDMA 0 Error +#define INT_ADC1SS0_TM4C129 62 // ADC1 Sequence 0 +#define INT_ADC1SS1_TM4C129 63 // ADC1 Sequence 1 +#define INT_ADC1SS2_TM4C129 64 // ADC1 Sequence 2 +#define INT_ADC1SS3_TM4C129 65 // ADC1 Sequence 3 +#define INT_EPI0_TM4C129 66 // EPI 0 +#define INT_GPIOJ_TM4C129 67 // GPIO Port J +#define INT_GPIOK_TM4C129 68 // GPIO Port K +#define INT_GPIOL_TM4C129 69 // GPIO Port L +#define INT_SSI2_TM4C129 70 // SSI 2 +#define INT_SSI3_TM4C129 71 // SSI 3 +#define INT_UART3_TM4C129 72 // UART 3 +#define INT_UART4_TM4C129 73 // UART 4 +#define INT_UART5_TM4C129 74 // UART 5 +#define INT_UART6_TM4C129 75 // UART 6 +#define INT_UART7_TM4C129 76 // UART 7 +#define INT_I2C2_TM4C129 77 // I2C 2 +#define INT_I2C3_TM4C129 78 // I2C 3 +#define INT_TIMER4A_TM4C129 79 // Timer 4A +#define INT_TIMER4B_TM4C129 80 // Timer 4B +#define INT_TIMER5A_TM4C129 81 // Timer 5A +#define INT_TIMER5B_TM4C129 82 // Timer 5B +#define INT_SYSEXC_TM4C129 83 // Floating-Point Exception + // (imprecise) +#define INT_I2C4_TM4C129 86 // I2C 4 +#define INT_I2C5_TM4C129 87 // I2C 5 +#define INT_GPIOM_TM4C129 88 // GPIO Port M +#define INT_GPION_TM4C129 89 // GPIO Port N +#define INT_TAMPER0_TM4C129 91 // Tamper +#define INT_GPIOP0_TM4C129 92 // GPIO Port P (Summary or P0) +#define INT_GPIOP1_TM4C129 93 // GPIO Port P1 +#define INT_GPIOP2_TM4C129 94 // GPIO Port P2 +#define INT_GPIOP3_TM4C129 95 // GPIO Port P3 +#define INT_GPIOP4_TM4C129 96 // GPIO Port P4 +#define INT_GPIOP5_TM4C129 97 // GPIO Port P5 +#define INT_GPIOP6_TM4C129 98 // GPIO Port P6 +#define INT_GPIOP7_TM4C129 99 // GPIO Port P7 +#define INT_GPIOQ0_TM4C129 100 // GPIO Port Q (Summary or Q0) +#define INT_GPIOQ1_TM4C129 101 // GPIO Port Q1 +#define INT_GPIOQ2_TM4C129 102 // GPIO Port Q2 +#define INT_GPIOQ3_TM4C129 103 // GPIO Port Q3 +#define INT_GPIOQ4_TM4C129 104 // GPIO Port Q4 +#define INT_GPIOQ5_TM4C129 105 // GPIO Port Q5 +#define INT_GPIOQ6_TM4C129 106 // GPIO Port Q6 +#define INT_GPIOQ7_TM4C129 107 // GPIO Port Q7 +#define INT_GPIOR_TM4C129 108 // GPIO Port R +#define INT_GPIOS_TM4C129 109 // GPIO Port S +#define INT_SHA0_TM4C129 110 // SHA/MD5 +#define INT_AES0_TM4C129 111 // AES +#define INT_DES0_TM4C129 112 // DES +#define INT_LCD0_TM4C129 113 // LCD +#define INT_TIMER6A_TM4C129 114 // 16/32-Bit Timer 6A +#define INT_TIMER6B_TM4C129 115 // 16/32-Bit Timer 6B +#define INT_TIMER7A_TM4C129 116 // 16/32-Bit Timer 7A +#define INT_TIMER7B_TM4C129 117 // 16/32-Bit Timer 7B +#define INT_I2C6_TM4C129 118 // I2C 6 +#define INT_I2C7_TM4C129 119 // I2C 7 +#define INT_ONEWIRE0_TM4C129 121 // 1-Wire +#define INT_I2C8_TM4C129 125 // I2C 8 +#define INT_I2C9_TM4C129 126 // I2C 9 +#define INT_GPIOT_TM4C129 127 // GPIO T +#define NUM_INTERRUPTS_TM4C129 129 + +//***************************************************************************** +// +// TM4C123 Interrupt Class Definition +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || defined(TARGET_IS_TM4C123_RA2) || \ + defined(TARGET_IS_TM4C123_RA3) || defined(TARGET_IS_TM4C123_RB0) || \ + defined(TARGET_IS_TM4C123_RB1) || defined(PART_TM4C1230C3PM) || \ + defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) || \ + defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || \ + defined(PART_TM4C1231D5PM) || defined(PART_TM4C1231D5PZ) || \ + defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) || \ + defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) || \ + defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || \ + defined(PART_TM4C1232E6PM) || defined(PART_TM4C1232H6PM) || \ + defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) || \ + defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || \ + defined(PART_TM4C1233E6PZ) || defined(PART_TM4C1233H6PM) || \ + defined(PART_TM4C1233H6PZ) || defined(PART_TM4C1236D5PM) || \ + defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) || \ + defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || \ + defined(PART_TM4C1237E6PM) || defined(PART_TM4C1237E6PZ) || \ + defined(PART_TM4C1237H6PM) || defined(PART_TM4C1237H6PZ) || \ + defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) || \ + defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || \ + defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || \ + defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || \ + defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GE6PZ) || \ + defined(PART_TM4C123GH6PM) || defined(PART_TM4C123GH6PZ) || \ + defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1233H6PGE) || \ + defined(PART_TM4C1237H6PGE) || defined(PART_TM4C123BH6PGE) || \ + defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123GH6PGE) || \ + defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH6ZXR) +#define INT_RESOLVE(intname, class) intname##TM4C123 + +//***************************************************************************** +// +// TM4C129 Interrupt Class Definition +// +//***************************************************************************** +#elif defined(TARGET_IS_TM4C129_RA0) || defined(PART_TM4C1290NCPDT) || \ + defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT) || \ + defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || \ + defined(PART_TM4C1294NCPDT) || defined(PART_TM4C1294NCZAD) || \ + defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD) || \ + defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || \ + defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT) || \ + defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT) || \ + defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || \ + defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD) || \ + defined(PART_TM4C129XNCZAD) +#define INT_RESOLVE(intname, class) intname##TM4C129 +#else +#define INT_DEVICE_CLASS "UNKNOWN" +#endif + +//***************************************************************************** +// +// Macros to resolve the INT_PERIPH_CLASS name to a common INT_PERIPH name. +// +//***************************************************************************** +#define INT_CONCAT(intname, class) INT_RESOLVE(intname, class) + +//***************************************************************************** +// +// The following are defines for the interrupt assignments. +// +//***************************************************************************** +#define INT_ADC0SS0 INT_CONCAT(INT_ADC0SS0_, INT_DEVICE_CLASS) +#define INT_ADC0SS1 INT_CONCAT(INT_ADC0SS1_, INT_DEVICE_CLASS) +#define INT_ADC0SS2 INT_CONCAT(INT_ADC0SS2_, INT_DEVICE_CLASS) +#define INT_ADC0SS3 INT_CONCAT(INT_ADC0SS3_, INT_DEVICE_CLASS) +#define INT_ADC1SS0 INT_CONCAT(INT_ADC1SS0_, INT_DEVICE_CLASS) +#define INT_ADC1SS1 INT_CONCAT(INT_ADC1SS1_, INT_DEVICE_CLASS) +#define INT_ADC1SS2 INT_CONCAT(INT_ADC1SS2_, INT_DEVICE_CLASS) +#define INT_ADC1SS3 INT_CONCAT(INT_ADC1SS3_, INT_DEVICE_CLASS) +#define INT_AES0 INT_CONCAT(INT_AES0_, INT_DEVICE_CLASS) +#define INT_CAN0 INT_CONCAT(INT_CAN0_, INT_DEVICE_CLASS) +#define INT_CAN1 INT_CONCAT(INT_CAN1_, INT_DEVICE_CLASS) +#define INT_COMP0 INT_CONCAT(INT_COMP0_, INT_DEVICE_CLASS) +#define INT_COMP1 INT_CONCAT(INT_COMP1_, INT_DEVICE_CLASS) +#define INT_COMP2 INT_CONCAT(INT_COMP2_, INT_DEVICE_CLASS) +#define INT_DES0 INT_CONCAT(INT_DES0_, INT_DEVICE_CLASS) +#define INT_EMAC0 INT_CONCAT(INT_EMAC0_, INT_DEVICE_CLASS) +#define INT_EPI0 INT_CONCAT(INT_EPI0_, INT_DEVICE_CLASS) +#define INT_FLASH INT_CONCAT(INT_FLASH_, INT_DEVICE_CLASS) +#define INT_GPIOA INT_CONCAT(INT_GPIOA_, INT_DEVICE_CLASS) +#define INT_GPIOB INT_CONCAT(INT_GPIOB_, INT_DEVICE_CLASS) +#define INT_GPIOC INT_CONCAT(INT_GPIOC_, INT_DEVICE_CLASS) +#define INT_GPIOD INT_CONCAT(INT_GPIOD_, INT_DEVICE_CLASS) +#define INT_GPIOE INT_CONCAT(INT_GPIOE_, INT_DEVICE_CLASS) +#define INT_GPIOF INT_CONCAT(INT_GPIOF_, INT_DEVICE_CLASS) +#define INT_GPIOG INT_CONCAT(INT_GPIOG_, INT_DEVICE_CLASS) +#define INT_GPIOH INT_CONCAT(INT_GPIOH_, INT_DEVICE_CLASS) +#define INT_GPIOJ INT_CONCAT(INT_GPIOJ_, INT_DEVICE_CLASS) +#define INT_GPIOK INT_CONCAT(INT_GPIOK_, INT_DEVICE_CLASS) +#define INT_GPIOL INT_CONCAT(INT_GPIOL_, INT_DEVICE_CLASS) +#define INT_GPIOM INT_CONCAT(INT_GPIOM_, INT_DEVICE_CLASS) +#define INT_GPION INT_CONCAT(INT_GPION_, INT_DEVICE_CLASS) +#define INT_GPIOP0 INT_CONCAT(INT_GPIOP0_, INT_DEVICE_CLASS) +#define INT_GPIOP1 INT_CONCAT(INT_GPIOP1_, INT_DEVICE_CLASS) +#define INT_GPIOP2 INT_CONCAT(INT_GPIOP2_, INT_DEVICE_CLASS) +#define INT_GPIOP3 INT_CONCAT(INT_GPIOP3_, INT_DEVICE_CLASS) +#define INT_GPIOP4 INT_CONCAT(INT_GPIOP4_, INT_DEVICE_CLASS) +#define INT_GPIOP5 INT_CONCAT(INT_GPIOP5_, INT_DEVICE_CLASS) +#define INT_GPIOP6 INT_CONCAT(INT_GPIOP6_, INT_DEVICE_CLASS) +#define INT_GPIOP7 INT_CONCAT(INT_GPIOP7_, INT_DEVICE_CLASS) +#define INT_GPIOQ0 INT_CONCAT(INT_GPIOQ0_, INT_DEVICE_CLASS) +#define INT_GPIOQ1 INT_CONCAT(INT_GPIOQ1_, INT_DEVICE_CLASS) +#define INT_GPIOQ2 INT_CONCAT(INT_GPIOQ2_, INT_DEVICE_CLASS) +#define INT_GPIOQ3 INT_CONCAT(INT_GPIOQ3_, INT_DEVICE_CLASS) +#define INT_GPIOQ4 INT_CONCAT(INT_GPIOQ4_, INT_DEVICE_CLASS) +#define INT_GPIOQ5 INT_CONCAT(INT_GPIOQ5_, INT_DEVICE_CLASS) +#define INT_GPIOQ6 INT_CONCAT(INT_GPIOQ6_, INT_DEVICE_CLASS) +#define INT_GPIOQ7 INT_CONCAT(INT_GPIOQ7_, INT_DEVICE_CLASS) +#define INT_GPIOR INT_CONCAT(INT_GPIOR_, INT_DEVICE_CLASS) +#define INT_GPIOS INT_CONCAT(INT_GPIOS_, INT_DEVICE_CLASS) +#define INT_GPIOT INT_CONCAT(INT_GPIOT_, INT_DEVICE_CLASS) +#define INT_HIBERNATE INT_CONCAT(INT_HIBERNATE_, INT_DEVICE_CLASS) +#define INT_I2C0 INT_CONCAT(INT_I2C0_, INT_DEVICE_CLASS) +#define INT_I2C1 INT_CONCAT(INT_I2C1_, INT_DEVICE_CLASS) +#define INT_I2C2 INT_CONCAT(INT_I2C2_, INT_DEVICE_CLASS) +#define INT_I2C3 INT_CONCAT(INT_I2C3_, INT_DEVICE_CLASS) +#define INT_I2C4 INT_CONCAT(INT_I2C4_, INT_DEVICE_CLASS) +#define INT_I2C5 INT_CONCAT(INT_I2C5_, INT_DEVICE_CLASS) +#define INT_I2C6 INT_CONCAT(INT_I2C6_, INT_DEVICE_CLASS) +#define INT_I2C7 INT_CONCAT(INT_I2C7_, INT_DEVICE_CLASS) +#define INT_I2C8 INT_CONCAT(INT_I2C8_, INT_DEVICE_CLASS) +#define INT_I2C9 INT_CONCAT(INT_I2C9_, INT_DEVICE_CLASS) +#define INT_LCD0 INT_CONCAT(INT_LCD0_, INT_DEVICE_CLASS) +#define INT_ONEWIRE0 INT_CONCAT(INT_ONEWIRE0_, INT_DEVICE_CLASS) +#define INT_PWM0_0 INT_CONCAT(INT_PWM0_0_, INT_DEVICE_CLASS) +#define INT_PWM0_1 INT_CONCAT(INT_PWM0_1_, INT_DEVICE_CLASS) +#define INT_PWM0_2 INT_CONCAT(INT_PWM0_2_, INT_DEVICE_CLASS) +#define INT_PWM0_3 INT_CONCAT(INT_PWM0_3_, INT_DEVICE_CLASS) +#define INT_PWM0_FAULT INT_CONCAT(INT_PWM0_FAULT_, INT_DEVICE_CLASS) +#define INT_PWM1_0 INT_CONCAT(INT_PWM1_0_, INT_DEVICE_CLASS) +#define INT_PWM1_1 INT_CONCAT(INT_PWM1_1_, INT_DEVICE_CLASS) +#define INT_PWM1_2 INT_CONCAT(INT_PWM1_2_, INT_DEVICE_CLASS) +#define INT_PWM1_3 INT_CONCAT(INT_PWM1_3_, INT_DEVICE_CLASS) +#define INT_PWM1_FAULT INT_CONCAT(INT_PWM1_FAULT_, INT_DEVICE_CLASS) +#define INT_QEI0 INT_CONCAT(INT_QEI0_, INT_DEVICE_CLASS) +#define INT_QEI1 INT_CONCAT(INT_QEI1_, INT_DEVICE_CLASS) +#define INT_SHA0 INT_CONCAT(INT_SHA0_, INT_DEVICE_CLASS) +#define INT_SSI0 INT_CONCAT(INT_SSI0_, INT_DEVICE_CLASS) +#define INT_SSI1 INT_CONCAT(INT_SSI1_, INT_DEVICE_CLASS) +#define INT_SSI2 INT_CONCAT(INT_SSI2_, INT_DEVICE_CLASS) +#define INT_SSI3 INT_CONCAT(INT_SSI3_, INT_DEVICE_CLASS) +#define INT_SYSCTL INT_CONCAT(INT_SYSCTL_, INT_DEVICE_CLASS) +#define INT_SYSEXC INT_CONCAT(INT_SYSEXC_, INT_DEVICE_CLASS) +#define INT_TAMPER0 INT_CONCAT(INT_TAMPER0_, INT_DEVICE_CLASS) +#define INT_TIMER0A INT_CONCAT(INT_TIMER0A_, INT_DEVICE_CLASS) +#define INT_TIMER0B INT_CONCAT(INT_TIMER0B_, INT_DEVICE_CLASS) +#define INT_TIMER1A INT_CONCAT(INT_TIMER1A_, INT_DEVICE_CLASS) +#define INT_TIMER1B INT_CONCAT(INT_TIMER1B_, INT_DEVICE_CLASS) +#define INT_TIMER2A INT_CONCAT(INT_TIMER2A_, INT_DEVICE_CLASS) +#define INT_TIMER2B INT_CONCAT(INT_TIMER2B_, INT_DEVICE_CLASS) +#define INT_TIMER3A INT_CONCAT(INT_TIMER3A_, INT_DEVICE_CLASS) +#define INT_TIMER3B INT_CONCAT(INT_TIMER3B_, INT_DEVICE_CLASS) +#define INT_TIMER4A INT_CONCAT(INT_TIMER4A_, INT_DEVICE_CLASS) +#define INT_TIMER4B INT_CONCAT(INT_TIMER4B_, INT_DEVICE_CLASS) +#define INT_TIMER5A INT_CONCAT(INT_TIMER5A_, INT_DEVICE_CLASS) +#define INT_TIMER5B INT_CONCAT(INT_TIMER5B_, INT_DEVICE_CLASS) +#define INT_TIMER6A INT_CONCAT(INT_TIMER6A_, INT_DEVICE_CLASS) +#define INT_TIMER6B INT_CONCAT(INT_TIMER6B_, INT_DEVICE_CLASS) +#define INT_TIMER7A INT_CONCAT(INT_TIMER7A_, INT_DEVICE_CLASS) +#define INT_TIMER7B INT_CONCAT(INT_TIMER7B_, INT_DEVICE_CLASS) +#define INT_UART0 INT_CONCAT(INT_UART0_, INT_DEVICE_CLASS) +#define INT_UART1 INT_CONCAT(INT_UART1_, INT_DEVICE_CLASS) +#define INT_UART2 INT_CONCAT(INT_UART2_, INT_DEVICE_CLASS) +#define INT_UART3 INT_CONCAT(INT_UART3_, INT_DEVICE_CLASS) +#define INT_UART4 INT_CONCAT(INT_UART4_, INT_DEVICE_CLASS) +#define INT_UART5 INT_CONCAT(INT_UART5_, INT_DEVICE_CLASS) +#define INT_UART6 INT_CONCAT(INT_UART6_, INT_DEVICE_CLASS) +#define INT_UART7 INT_CONCAT(INT_UART7_, INT_DEVICE_CLASS) +#define INT_UDMA INT_CONCAT(INT_UDMA_, INT_DEVICE_CLASS) +#define INT_UDMAERR INT_CONCAT(INT_UDMAERR_, INT_DEVICE_CLASS) +#define INT_USB0 INT_CONCAT(INT_USB0_, INT_DEVICE_CLASS) +#define INT_WATCHDOG INT_CONCAT(INT_WATCHDOG_, INT_DEVICE_CLASS) +#define INT_WTIMER0A INT_CONCAT(INT_WTIMER0A_, INT_DEVICE_CLASS) +#define INT_WTIMER0B INT_CONCAT(INT_WTIMER0B_, INT_DEVICE_CLASS) +#define INT_WTIMER1A INT_CONCAT(INT_WTIMER1A_, INT_DEVICE_CLASS) +#define INT_WTIMER1B INT_CONCAT(INT_WTIMER1B_, INT_DEVICE_CLASS) +#define INT_WTIMER2A INT_CONCAT(INT_WTIMER2A_, INT_DEVICE_CLASS) +#define INT_WTIMER2B INT_CONCAT(INT_WTIMER2B_, INT_DEVICE_CLASS) +#define INT_WTIMER3A INT_CONCAT(INT_WTIMER3A_, INT_DEVICE_CLASS) +#define INT_WTIMER3B INT_CONCAT(INT_WTIMER3B_, INT_DEVICE_CLASS) +#define INT_WTIMER4A INT_CONCAT(INT_WTIMER4A_, INT_DEVICE_CLASS) +#define INT_WTIMER4B INT_CONCAT(INT_WTIMER4B_, INT_DEVICE_CLASS) +#define INT_WTIMER5A INT_CONCAT(INT_WTIMER5A_, INT_DEVICE_CLASS) +#define INT_WTIMER5B INT_CONCAT(INT_WTIMER5B_, INT_DEVICE_CLASS) + +//***************************************************************************** +// +// The following are defines for the total number of interrupts. +// +//***************************************************************************** +#define NUM_INTERRUPTS INT_CONCAT(NUM_INTERRUPTS_, INT_DEVICE_CLASS) + +//***************************************************************************** +// +// The following are defines for the total number of priority levels. +// +//***************************************************************************** +#define NUM_PRIORITY 8 +#define NUM_PRIORITY_BITS 3 + +#endif // __HW_INTS_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_lcd.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_lcd.h new file mode 100644 index 0000000000000000000000000000000000000000..bf0be0ae2fe8c6dbc86e4613795103faa6e382ba --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_lcd.h @@ -0,0 +1,575 @@ +//***************************************************************************** +// +// hw_lcd.h - Defines and macros used when accessing the LCD controller. +// +// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_LCD_H__ +#define __HW_LCD_H__ + +//***************************************************************************** +// +// The following are defines for the LCD register offsets. +// +//***************************************************************************** +#define LCD_O_PID 0x00000000 // LCD PID Register Format +#define LCD_O_CTL 0x00000004 // LCD Control +#define LCD_O_LIDDCTL 0x0000000C // LCD LIDD Control +#define LCD_O_LIDDCS0CFG 0x00000010 // LCD LIDD CS0 Configuration +#define LCD_O_LIDDCS0ADDR 0x00000014 // LIDD CS0 Read/Write Address +#define LCD_O_LIDDCS0DATA 0x00000018 // LIDD CS0 Data Read/Write + // Initiation +#define LCD_O_LIDDCS1CFG 0x0000001C // LIDD CS1 Configuration +#define LCD_O_LIDDCS1ADDR 0x00000020 // LIDD CS1 Address Read/Write + // Initiation +#define LCD_O_LIDDCS1DATA 0x00000024 // LIDD CS1 Data Read/Write + // Initiation +#define LCD_O_RASTRCTL 0x00000028 // LCD Raster Control +#define LCD_O_RASTRTIM0 0x0000002C // LCD Raster Timing 0 +#define LCD_O_RASTRTIM1 0x00000030 // LCD Raster Timing 1 +#define LCD_O_RASTRTIM2 0x00000034 // LCD Raster Timing 2 +#define LCD_O_RASTRSUBP1 0x00000038 // LCD Raster Subpanel Display 1 +#define LCD_O_RASTRSUBP2 0x0000003C // LCD Raster Subpanel Display 2 +#define LCD_O_DMACTL 0x00000040 // LCD DMA Control +#define LCD_O_DMABAFB0 0x00000044 // LCD DMA Frame Buffer 0 Base + // Address +#define LCD_O_DMACAFB0 0x00000048 // LCD DMA Frame Buffer 0 Ceiling + // Address +#define LCD_O_DMABAFB1 0x0000004C // LCD DMA Frame Buffer 1 Base + // Address +#define LCD_O_DMACAFB1 0x00000050 // LCD DMA Frame Buffer 1 Ceiling + // Address +#define LCD_O_SYSCFG 0x00000054 // LCD System Configuration + // Register +#define LCD_O_RISSET 0x00000058 // LCD Interrupt Raw Status and Set + // Register +#define LCD_O_MISCLR 0x0000005C // LCD Interrupt Status and Clear +#define LCD_O_IM 0x00000060 // LCD Interrupt Mask +#define LCD_O_IENC 0x00000064 // LCD Interrupt Enable Clear +#define LCD_O_CLKEN 0x0000006C // LCD Clock Enable +#define LCD_O_CLKRESET 0x00000070 // LCD Clock Resets + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_PID register. +// +//***************************************************************************** +#define LCD_PID_MAJOR_M 0x00000700 // Major Release Number +#define LCD_PID_MINOR_M 0x0000003F // Minor Release Number +#define LCD_PID_MAJOR_S 8 +#define LCD_PID_MINOR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_CTL register. +// +//***************************************************************************** +#define LCD_CTL_CLKDIV_M 0x0000FF00 // Clock Divisor +#define LCD_CTL_UFLOWRST 0x00000002 // Underflow Restart +#define LCD_CTL_LCDMODE 0x00000001 // LCD Mode Select +#define LCD_CTL_CLKDIV_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_LIDDCTL register. +// +//***************************************************************************** +#define LCD_LIDDCTL_DMACS 0x00000200 // CS0/CS1 Select for LIDD DMA + // Writes +#define LCD_LIDDCTL_DMAEN 0x00000100 // LIDD DMA Enable +#define LCD_LIDDCTL_CS1E1 0x00000080 // Chip Select 1 (CS1)/Enable 1(E1) + // Polarity Control +#define LCD_LIDDCTL_CS0E0 0x00000040 // Chip Select 0 (CS0)/Enable 0 + // (E0) Polarity Control +#define LCD_LIDDCTL_WRDIRINV 0x00000020 // Write Strobe (WR) /Direction + // (DIR) Polarity Control +#define LCD_LIDDCTL_RDEN 0x00000010 // Read Strobe (RD) /Direct Enable + // (EN) Polarity Control +#define LCD_LIDDCTL_ALE 0x00000008 // Address Latch Enable (ALE) + // Polarity Control +#define LCD_LIDDCTL_MODE_M 0x00000007 // LIDD Mode Select +#define LCD_LIDDCTL_MODE_SYNCM68 \ + 0x00000000 // Synchronous Motorola 6800 Mode +#define LCD_LIDDCTL_MODE_ASYNCM68 \ + 0x00000001 // Asynchronous Motorola 6800 Mode +#define LCD_LIDDCTL_MODE_SYNCM80 \ + 0x00000002 // Synchronous Intel 8080 mode +#define LCD_LIDDCTL_MODE_ASYNCM80 \ + 0x00000003 // Asynchronous Intel 8080 mode +#define LCD_LIDDCTL_MODE_ASYNCHIT \ + 0x00000004 // Asynchronous Hitachi mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_LIDDCS0CFG +// register. +// +//***************************************************************************** +#define LCD_LIDDCS0CFG_WRSU_M 0xF8000000 // Write Strobe (WR) Set-Up Cycles +#define LCD_LIDDCS0CFG_WRDUR_M 0x07E00000 // Write Strobe (WR) Duration + // Cycles +#define LCD_LIDDCS0CFG_WRHOLD_M 0x001E0000 // Write Strobe (WR) Hold cycles +#define LCD_LIDDCS0CFG_RDSU_M 0x0001F000 // Read Strobe (RD) Set-Up cycles +#define LCD_LIDDCS0CFG_RDDUR_M 0x00000FC0 // Read Strobe (RD) Duration cycles +#define LCD_LIDDCS0CFG_RDHOLD_M 0x0000003C // Read Strobe (RD) Hold cycles +#define LCD_LIDDCS0CFG_GAP_M 0x00000003 // Field value defines the number + // of LCDMCLK cycles (GAP +1) + // between the end of one CS0 + // (LCDAC) device access and the + // start of another CS0 (LCDAC) + // device access unless the two + // accesses are both reads +#define LCD_LIDDCS0CFG_WRSU_S 27 +#define LCD_LIDDCS0CFG_WRDUR_S 21 +#define LCD_LIDDCS0CFG_WRHOLD_S 17 +#define LCD_LIDDCS0CFG_RDSU_S 12 +#define LCD_LIDDCS0CFG_RDDUR_S 6 +#define LCD_LIDDCS0CFG_RDHOLD_S 2 +#define LCD_LIDDCS0CFG_GAP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_LIDDCS0ADDR +// register. +// +//***************************************************************************** +#define LCD_LIDDCS0ADDR_CS0ADDR_M \ + 0x0000FFFF // LCD Address +#define LCD_LIDDCS0ADDR_CS0ADDR_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_LIDDCS0DATA +// register. +// +//***************************************************************************** +#define LCD_LIDDCS0DATA_CS0DATA_M \ + 0x0000FFFF // LCD Data Read/Write +#define LCD_LIDDCS0DATA_CS0DATA_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_LIDDCS1CFG +// register. +// +//***************************************************************************** +#define LCD_LIDDCS1CFG_WRSU_M 0xF8000000 // Write Strobe (WR) Set-Up Cycles +#define LCD_LIDDCS1CFG_WRDUR_M 0x07E00000 // Write Strobe (WR) Duration + // Cycles +#define LCD_LIDDCS1CFG_WRHOLD_M 0x001E0000 // Write Strobe (WR) Hold cycles +#define LCD_LIDDCS1CFG_RDSU_M 0x0001F000 // Read Strobe (RD) Set-Up cycles +#define LCD_LIDDCS1CFG_RDDUR_M 0x00000FC0 // Read Strobe (RD) Duration cycles +#define LCD_LIDDCS1CFG_RDHOLD_M 0x0000003C // Read Strobe (RD) Hold cycles +#define LCD_LIDDCS1CFG_GAP_M 0x00000003 // Field value defines the number + // of LCDMCLK cycles (GAP + 1) + // between the end of one CS1 + // (LCDAC) device access and the + // start of another CS0 (LCDAC) + // device access unless the two + // accesses are both reads +#define LCD_LIDDCS1CFG_WRSU_S 27 +#define LCD_LIDDCS1CFG_WRDUR_S 21 +#define LCD_LIDDCS1CFG_WRHOLD_S 17 +#define LCD_LIDDCS1CFG_RDSU_S 12 +#define LCD_LIDDCS1CFG_RDDUR_S 6 +#define LCD_LIDDCS1CFG_RDHOLD_S 2 +#define LCD_LIDDCS1CFG_GAP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_LIDDCS1ADDR +// register. +// +//***************************************************************************** +#define LCD_LIDDCS1ADDR_CS1ADDR_M \ + 0x0000FFFF // LCD Address Bus +#define LCD_LIDDCS1ADDR_CS1ADDR_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_LIDDCS1DATA +// register. +// +//***************************************************************************** +#define LCD_LIDDCS1DATA_CS0DATA_M \ + 0x0000FFFF // LCD Data Read/Write Initiation +#define LCD_LIDDCS1DATA_CS0DATA_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_RASTRCTL register. +// +//***************************************************************************** +#define LCD_RASTRCTL_TFT24UPCK 0x04000000 // 24-bit TFT Mode Packing +#define LCD_RASTRCTL_TFT24 0x02000000 // 24-Bit TFT Mode +#define LCD_RASTRCTL_FRMBUFSZ 0x01000000 // Frame Buffer Select +#define LCD_RASTRCTL_TFTMAP 0x00800000 // TFT Mode Alternate Signal + // Mapping for Palettized + // Framebuffer +#define LCD_RASTRCTL_NIBMODE 0x00400000 // Nibble Mode +#define LCD_RASTRCTL_PALMODE_M 0x00300000 // Pallette Loading Mode +#define LCD_RASTRCTL_PALMODE_PALDAT \ + 0x00000000 // Palette and data loading, reset + // value +#define LCD_RASTRCTL_PALMODE_PAL \ + 0x00100000 // Palette loading only +#define LCD_RASTRCTL_PALMODE_DAT \ + 0x00200000 // Data loading only +#define LCD_RASTRCTL_REQDLY_M 0x000FF000 // Palette Loading Delay +#define LCD_RASTRCTL_MONO8B 0x00000200 // Mono 8-Bit +#define LCD_RASTRCTL_RDORDER 0x00000100 // Raster Data Order Select +#define LCD_RASTRCTL_LCDTFT 0x00000080 // LCD TFT +#define LCD_RASTRCTL_LCDBW 0x00000002 // LCD Monochrome +#define LCD_RASTRCTL_LCDEN 0x00000001 // LCD Controller Enable for Raster + // Operations +#define LCD_RASTRCTL_REQDLY_S 12 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_RASTRTIM0 +// register. +// +//***************************************************************************** +#define LCD_RASTRTIM0_HBP_M 0xFF000000 // Horizontal Back Porch Lowbits +#define LCD_RASTRTIM0_HFP_M 0x00FF0000 // Horizontal Front Porch Lowbits +#define LCD_RASTRTIM0_HSW_M 0x0000FC00 // Horizontal Sync Pulse Width + // Lowbits +#define LCD_RASTRTIM0_PPL_M 0x000003F0 // Pixels-per-line LSB[9:4] +#define LCD_RASTRTIM0_MSBPPL 0x00000008 // Pixels-per-line MSB[10] +#define LCD_RASTRTIM0_HBP_S 24 +#define LCD_RASTRTIM0_HFP_S 16 +#define LCD_RASTRTIM0_HSW_S 10 +#define LCD_RASTRTIM0_PPL_S 4 +#define LCD_RASTRTIM0_MSBPPL_S 3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_RASTRTIM1 +// register. +// +//***************************************************************************** +#define LCD_RASTRTIM1_VBP_M 0xFF000000 // Vertical Back Porch +#define LCD_RASTRTIM1_VFP_M 0x00FF0000 // Vertical Front Porch +#define LCD_RASTRTIM1_VSW_M 0x0000FC00 // Vertical Sync Width Pulse +#define LCD_RASTRTIM1_LPP_M 0x000003FF // Lines Per Panel +#define LCD_RASTRTIM1_VBP_S 24 +#define LCD_RASTRTIM1_VFP_S 16 +#define LCD_RASTRTIM1_VSW_S 10 +#define LCD_RASTRTIM1_LPP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_RASTRTIM2 +// register. +// +//***************************************************************************** +#define LCD_RASTRTIM2_HSW_M 0x78000000 // Bits 9:6 of the horizontal sync + // width field +#define LCD_RASTRTIM2_MSBLPP 0x04000000 // MSB of Lines Per Panel +#define LCD_RASTRTIM2_PXLCLKCTL 0x02000000 // Hsync/Vsync Pixel Clock Control + // On/Off +#define LCD_RASTRTIM2_PSYNCRF 0x01000000 // Program HSYNC/VSYNC Rise or Fall +#define LCD_RASTRTIM2_INVOE 0x00800000 // Invert Output Enable +#define LCD_RASTRTIM2_INVPXLCLK 0x00400000 // Invert Pixel Clock +#define LCD_RASTRTIM2_IHS 0x00200000 // Invert Hysync +#define LCD_RASTRTIM2_IVS 0x00100000 // Invert Vsync +#define LCD_RASTRTIM2_ACBI_M 0x000F0000 // AC Bias Pins Transitions per + // Interrupt +#define LCD_RASTRTIM2_ACBF_M 0x0000FF00 // AC Bias Pin Frequency +#define LCD_RASTRTIM2_MSBHBP_M 0x00000030 // Bits 9:8 of the horizontal back + // porch field +#define LCD_RASTRTIM2_MSBHFP_M 0x00000003 // Bits 9:8 of the horizontal front + // porch field +#define LCD_RASTRTIM2_HSW_S 27 +#define LCD_RASTRTIM2_MSBLPP_S 26 +#define LCD_RASTRTIM2_ACBI_S 16 +#define LCD_RASTRTIM2_ACBF_S 8 +#define LCD_RASTRTIM2_MSBHBP_S 4 +#define LCD_RASTRTIM2_MSBHFP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_RASTRSUBP1 +// register. +// +//***************************************************************************** +#define LCD_RASTRSUBP1_SPEN 0x80000000 // Sub Panel Enable +#define LCD_RASTRSUBP1_HOLS 0x20000000 // High or Low Signal +#define LCD_RASTRSUBP1_LPPT_M 0x03FF0000 // Line Per Panel Threshold +#define LCD_RASTRSUBP1_DPDLSB_M 0x0000FFFF // Default Pixel Data LSB[15:0] +#define LCD_RASTRSUBP1_LPPT_S 16 +#define LCD_RASTRSUBP1_DPDLSB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_RASTRSUBP2 +// register. +// +//***************************************************************************** +#define LCD_RASTRSUBP2_LPPTMSB 0x00000100 // Lines Per Panel Threshold Bit 10 +#define LCD_RASTRSUBP2_DPDMSB_M 0x000000FF // Default Pixel Data MSB [23:16] +#define LCD_RASTRSUBP2_DPDMSB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_DMACTL register. +// +//***************************************************************************** +#define LCD_DMACTL_FIFORDY_M 0x00000700 // DMA FIFO threshold +#define LCD_DMACTL_FIFORDY_8 0x00000000 // 8 words +#define LCD_DMACTL_FIFORDY_16 0x00000100 // 16 words +#define LCD_DMACTL_FIFORDY_32 0x00000200 // 32 words +#define LCD_DMACTL_FIFORDY_64 0x00000300 // 64 words +#define LCD_DMACTL_FIFORDY_128 0x00000400 // 128 words +#define LCD_DMACTL_FIFORDY_256 0x00000500 // 256 words +#define LCD_DMACTL_FIFORDY_512 0x00000600 // 512 words +#define LCD_DMACTL_BURSTSZ_M 0x00000070 // Burst Size setting for DMA + // transfers (all DMA transfers are + // 32 bits wide): +#define LCD_DMACTL_BURSTSZ_4 0x00000020 // burst size of 4 +#define LCD_DMACTL_BURSTSZ_8 0x00000030 // burst size of 8 +#define LCD_DMACTL_BURSTSZ_16 0x00000040 // burst size of 16 +#define LCD_DMACTL_BYTESWAP 0x00000008 // This bit controls the bytelane + // ordering of the data on the + // output of the DMA module +#define LCD_DMACTL_BIGDEND 0x00000002 // Big Endian Enable +#define LCD_DMACTL_FMODE 0x00000001 // Frame Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_DMABAFB0 register. +// +//***************************************************************************** +#define LCD_DMABAFB0_FB0BA_M 0xFFFFFFFC // Frame Buffer 0 Base Address + // pointer +#define LCD_DMABAFB0_FB0BA_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_DMACAFB0 register. +// +//***************************************************************************** +#define LCD_DMACAFB0_FB0CA_M 0xFFFFFFFC // Frame Buffer 0 Ceiling Address + // pointer +#define LCD_DMACAFB0_FB0CA_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_DMABAFB1 register. +// +//***************************************************************************** +#define LCD_DMABAFB1_FB1BA_M 0xFFFFFFFC // Frame Buffer 1 Base Address + // pointer +#define LCD_DMABAFB1_FB1BA_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_DMACAFB1 register. +// +//***************************************************************************** +#define LCD_DMACAFB1_FB1CA_M 0xFFFFFFFC // Frame Buffer 1 Ceiling Address + // pointer +#define LCD_DMACAFB1_FB1CA_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_SYSCFG register. +// +//***************************************************************************** +#define LCD_SYSCFG_STDBY_M 0x00000030 // Standby Mode +#define LCD_SYSCFG_STDBY_FORCE 0x00000000 // Force-standby mode: local + // initiator is unconditionally + // placed in standby state. Backup + // mode, for debug only +#define LCD_SYSCFG_STDBY_NONE 0x00000010 // No-standby mode: local initiator + // is unconditionally placed out of + // standby state. Backup mode, for + // debug only +#define LCD_SYSCFG_STDBY_SMART 0x00000020 // Smart-standby mode: local + // initiator standby status depends + // on local conditions, that is, + // the module's functional + // requirement from the initiator. + // IP module shall not generate + // (initiator-related) wakeup + // events +#define LCD_SYSCFG_IDLEMODE_M 0x0000000C // Idle Mode +#define LCD_SYSCFG_IDLEMODE_FORCE \ + 0x00000000 // Force-idle mode: local target's + // idle state follows + // (acknowledges) the system's idle + // requests unconditionally, that + // is, regardless of the IP + // module's internal requirements. + // Backup mode, for debug only +#define LCD_SYSCFG_IDLEMODE_NONE \ + 0x00000004 // No-idle mode: local target never + // enters idle state. Backup mode, + // for debug only +#define LCD_SYSCFG_IDLEMODE_SMART \ + 0x00000008 // Smart-idle mode: local target's + // idle state eventually follows + // (acknowledges) the system's idle + // requests, depending on the IP + // module's internal requirements. + // IP module shall not generate + // (IRQ- or DMA-requestrelated) + // wakeup events + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_RISSET register. +// +//***************************************************************************** +#define LCD_RISSET_EOF1 0x00000200 // DMA End-of-Frame 1 Raw Interrupt + // Status and Set +#define LCD_RISSET_EOF0 0x00000100 // DMA End-of-Frame 0 Raw Interrupt + // Status and Set +#define LCD_RISSET_PALLOAD 0x00000040 // DMA Palette Loaded Raw Interrupt + // Status and Set +#define LCD_RISSET_FIFOU 0x00000020 // DMA FIFO Underflow Raw Interrupt + // Status and Set +#define LCD_RISSET_ACBS 0x00000008 // AC Bias Count Raw Interrupt + // Status and Set +#define LCD_RISSET_SYNCS 0x00000004 // Frame Synchronization Lost Raw + // Interrupt Status and Set +#define LCD_RISSET_RRASTRDONE 0x00000002 // Raster Mode Frame Done interrupt +#define LCD_RISSET_DONE 0x00000001 // Raster or LIDD Frame Done + // (shared, depends on whether + // Raster or LIDD mode enabled) Raw + // Interrupt Status and Set + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_MISCLR register. +// +//***************************************************************************** +#define LCD_MISCLR_EOF1 0x00000200 // DMA End-of-Frame 1 Enabled + // Interrupt and Clear +#define LCD_MISCLR_EOF0 0x00000100 // DMA End-of-Frame 0 Raw Interrupt + // and Clear +#define LCD_MISCLR_PALLOAD 0x00000040 // DMA Palette Loaded Enabled + // Interrupt and Clear +#define LCD_MISCLR_FIFOU 0x00000020 // DMA FIFO Underflow Enabled + // Interrupt and Clear +#define LCD_MISCLR_ACBS 0x00000008 // AC Bias Count Enabled Interrupt + // and Clear +#define LCD_MISCLR_SYNCS 0x00000004 // Frame Synchronization Lost + // Enabled Interrupt and Clear +#define LCD_MISCLR_RRASTRDONE 0x00000002 // Raster Mode Frame Done interrupt +#define LCD_MISCLR_DONE 0x00000001 // Raster or LIDD Frame Done + // (shared, depends on whether + // Raster or LIDD mode enabled) + // Enabled Interrupt and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_IM register. +// +//***************************************************************************** +#define LCD_IM_EOF1 0x00000200 // DMA End-of-Frame 1 Interrupt + // Enable Set +#define LCD_IM_EOF0 0x00000100 // DMA End-of-Frame 0 Interrupt + // Enable Set +#define LCD_IM_PALLOAD 0x00000040 // DMA Palette Loaded Interrupt + // Enable Set +#define LCD_IM_FIFOU 0x00000020 // DMA FIFO Underflow Interrupt + // Enable Set +#define LCD_IM_ACBS 0x00000008 // AC Bias Count Interrupt Enable + // Set +#define LCD_IM_SYNCS 0x00000004 // Frame Synchronization Lost + // Interrupt Enable Set +#define LCD_IM_RRASTRDONE 0x00000002 // Raster Mode Frame Done Interrupt + // Enable Set +#define LCD_IM_DONE 0x00000001 // Raster or LIDD Frame Done + // (shared, depends on whether + // Raster or LIDD mode enabled) + // Interrupt Enable Set + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_IENC register. +// +//***************************************************************************** +#define LCD_IENC_EOF1 0x00000200 // DMA End-of-Frame 1 Interrupt + // Enable Clear +#define LCD_IENC_EOF0 0x00000100 // DMA End-of-Frame 0 Interrupt + // Enable Clear +#define LCD_IENC_PALLOAD 0x00000040 // DMA Palette Loaded Interrupt + // Enable Clear +#define LCD_IENC_FIFOU 0x00000020 // DMA FIFO Underflow Interrupt + // Enable Clear +#define LCD_IENC_ACBS 0x00000008 // AC Bias Count Interrupt Enable + // Clear +#define LCD_IENC_SYNCS 0x00000004 // Frame Synchronization Lost + // Interrupt Enable Clear +#define LCD_IENC_RRASTRDONE 0x00000002 // Raster Mode Frame Done Interrupt + // Enable Clear +#define LCD_IENC_DONE 0x00000001 // Raster or LIDD Frame Done + // (shared, depends on whether + // Raster or LIDD mode enabled) + // Interrupt Enable Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_CLKEN register. +// +//***************************************************************************** +#define LCD_CLKEN_DMA 0x00000004 // DMA Clock Enable +#define LCD_CLKEN_LIDD 0x00000002 // LIDD Submodule Clock Enable +#define LCD_CLKEN_CORE 0x00000001 // LCD Core Clock Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_CLKRESET register. +// +//***************************************************************************** +#define LCD_CLKRESET_MAIN 0x00000008 // Software Reset for the entire + // LCD module +#define LCD_CLKRESET_DMA 0x00000004 // Software Reset for the DMA + // submodule +#define LCD_CLKRESET_LIDD 0x00000002 // Software Reset for the LIDD + // submodule (character displays) +#define LCD_CLKRESET_CORE 0x00000001 // Software Reset for the Core, + // which encompasses the Raster + // Active Matrix and Passive Matrix + // logic + +#endif // __HW_LCD_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_memmap.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_memmap.h new file mode 100644 index 0000000000000000000000000000000000000000..87033ab8230b4d779b6c69ee741a1eecb680caee --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_memmap.h @@ -0,0 +1,151 @@ +//***************************************************************************** +// +// hw_memmap.h - Macros defining the memory map of the device. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_MEMMAP_H__ +#define __HW_MEMMAP_H__ + +//***************************************************************************** +// +// The following are defines for the base address of the memories and +// peripherals. +// +//***************************************************************************** +#define FLASH_BASE 0x00000000 // FLASH memory +#define SRAM_BASE 0x20000000 // SRAM memory +#define WATCHDOG0_BASE 0x40000000 // Watchdog0 +#define WATCHDOG1_BASE 0x40001000 // Watchdog1 +#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A +#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B +#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C +#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D +#define SSI0_BASE 0x40008000 // SSI0 +#define SSI1_BASE 0x40009000 // SSI1 +#define SSI2_BASE 0x4000A000 // SSI2 +#define SSI3_BASE 0x4000B000 // SSI3 +#define UART0_BASE 0x4000C000 // UART0 +#define UART1_BASE 0x4000D000 // UART1 +#define UART2_BASE 0x4000E000 // UART2 +#define UART3_BASE 0x4000F000 // UART3 +#define UART4_BASE 0x40010000 // UART4 +#define UART5_BASE 0x40011000 // UART5 +#define UART6_BASE 0x40012000 // UART6 +#define UART7_BASE 0x40013000 // UART7 +#define I2C0_BASE 0x40020000 // I2C0 +#define I2C1_BASE 0x40021000 // I2C1 +#define I2C2_BASE 0x40022000 // I2C2 +#define I2C3_BASE 0x40023000 // I2C3 +#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E +#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F +#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G +#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H +#define PWM0_BASE 0x40028000 // Pulse Width Modulator (PWM) +#define PWM1_BASE 0x40029000 // Pulse Width Modulator (PWM) +#define QEI0_BASE 0x4002C000 // QEI0 +#define QEI1_BASE 0x4002D000 // QEI1 +#define TIMER0_BASE 0x40030000 // Timer0 +#define TIMER1_BASE 0x40031000 // Timer1 +#define TIMER2_BASE 0x40032000 // Timer2 +#define TIMER3_BASE 0x40033000 // Timer3 +#define TIMER4_BASE 0x40034000 // Timer4 +#define TIMER5_BASE 0x40035000 // Timer5 +#define WTIMER0_BASE 0x40036000 // Wide Timer0 +#define WTIMER1_BASE 0x40037000 // Wide Timer1 +#define ADC0_BASE 0x40038000 // ADC0 +#define ADC1_BASE 0x40039000 // ADC1 +#define COMP_BASE 0x4003C000 // Analog comparators +#define GPIO_PORTJ_BASE 0x4003D000 // GPIO Port J +#define CAN0_BASE 0x40040000 // CAN0 +#define CAN1_BASE 0x40041000 // CAN1 +#define WTIMER2_BASE 0x4004C000 // Wide Timer2 +#define WTIMER3_BASE 0x4004D000 // Wide Timer3 +#define WTIMER4_BASE 0x4004E000 // Wide Timer4 +#define WTIMER5_BASE 0x4004F000 // Wide Timer5 +#define USB0_BASE 0x40050000 // USB 0 Controller +#define GPIO_PORTA_AHB_BASE 0x40058000 // GPIO Port A (high speed) +#define GPIO_PORTB_AHB_BASE 0x40059000 // GPIO Port B (high speed) +#define GPIO_PORTC_AHB_BASE 0x4005A000 // GPIO Port C (high speed) +#define GPIO_PORTD_AHB_BASE 0x4005B000 // GPIO Port D (high speed) +#define GPIO_PORTE_AHB_BASE 0x4005C000 // GPIO Port E (high speed) +#define GPIO_PORTF_AHB_BASE 0x4005D000 // GPIO Port F (high speed) +#define GPIO_PORTG_AHB_BASE 0x4005E000 // GPIO Port G (high speed) +#define GPIO_PORTH_AHB_BASE 0x4005F000 // GPIO Port H (high speed) +#define GPIO_PORTJ_AHB_BASE 0x40060000 // GPIO Port J (high speed) +#define GPIO_PORTK_BASE 0x40061000 // GPIO Port K +#define GPIO_PORTL_BASE 0x40062000 // GPIO Port L +#define GPIO_PORTM_BASE 0x40063000 // GPIO Port M +#define GPIO_PORTN_BASE 0x40064000 // GPIO Port N +#define GPIO_PORTP_BASE 0x40065000 // GPIO Port P +#define GPIO_PORTQ_BASE 0x40066000 // GPIO Port Q +#define GPIO_PORTR_BASE 0x40067000 // General-Purpose Input/Outputs + // (GPIOs) +#define GPIO_PORTS_BASE 0x40068000 // General-Purpose Input/Outputs + // (GPIOs) +#define GPIO_PORTT_BASE 0x40069000 // General-Purpose Input/Outputs + // (GPIOs) +#define EEPROM_BASE 0x400AF000 // EEPROM memory +#define ONEWIRE0_BASE 0x400B6000 // 1-Wire Master Module +#define I2C8_BASE 0x400B8000 // I2C8 +#define I2C9_BASE 0x400B9000 // I2C9 +#define I2C4_BASE 0x400C0000 // I2C4 +#define I2C5_BASE 0x400C1000 // I2C5 +#define I2C6_BASE 0x400C2000 // I2C6 +#define I2C7_BASE 0x400C3000 // I2C7 +#define EPI0_BASE 0x400D0000 // EPI0 +#define TIMER6_BASE 0x400E0000 // General-Purpose Timers +#define TIMER7_BASE 0x400E1000 // General-Purpose Timers +#define EMAC0_BASE 0x400EC000 // Ethernet Controller +#define SYSEXC_BASE 0x400F9000 // System Exception Module +#define HIB_BASE 0x400FC000 // Hibernation Module +#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller +#define SYSCTL_BASE 0x400FE000 // System Control +#define UDMA_BASE 0x400FF000 // uDMA Controller +#define CCM0_BASE 0x44030000 // Cyclical Redundancy Check (CRC) +#define SHAMD5_BASE 0x44034000 // SHA/MD5 Accelerator +#define AES_BASE 0x44036000 // Advance Encryption + // Hardware-Accelerated Module +#define DES_BASE 0x44038000 // Data Encryption Standard + // Accelerator (DES) +#define LCD0_BASE 0x44050000 // LCD Controller +#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell +#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace +#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint +#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl +#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit + +#endif // __HW_MEMMAP_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_nvic.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_nvic.h new file mode 100644 index 0000000000000000000000000000000000000000..be8becf0fb877eb659a1b73b033bf6081c7e124c --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_nvic.h @@ -0,0 +1,1414 @@ +//***************************************************************************** +// +// hw_nvic.h - Macros used when accessing the NVIC hardware. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_NVIC_H__ +#define __HW_NVIC_H__ + +//***************************************************************************** +// +// The following are defines for the NVIC register addresses. +// +//***************************************************************************** +#define NVIC_ACTLR 0xE000E008 // Auxiliary Control +#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status + // Register +#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register +#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register +#define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable +#define NVIC_EN1 0xE000E104 // Interrupt 32-63 Set Enable +#define NVIC_EN2 0xE000E108 // Interrupt 64-95 Set Enable +#define NVIC_EN3 0xE000E10C // Interrupt 96-127 Set Enable +#define NVIC_EN4 0xE000E110 // Interrupt 128-159 Set Enable +#define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable +#define NVIC_DIS1 0xE000E184 // Interrupt 32-63 Clear Enable +#define NVIC_DIS2 0xE000E188 // Interrupt 64-95 Clear Enable +#define NVIC_DIS3 0xE000E18C // Interrupt 96-127 Clear Enable +#define NVIC_DIS4 0xE000E190 // Interrupt 128-159 Clear Enable +#define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending +#define NVIC_PEND1 0xE000E204 // Interrupt 32-63 Set Pending +#define NVIC_PEND2 0xE000E208 // Interrupt 64-95 Set Pending +#define NVIC_PEND3 0xE000E20C // Interrupt 96-127 Set Pending +#define NVIC_PEND4 0xE000E210 // Interrupt 128-159 Set Pending +#define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending +#define NVIC_UNPEND1 0xE000E284 // Interrupt 32-63 Clear Pending +#define NVIC_UNPEND2 0xE000E288 // Interrupt 64-95 Clear Pending +#define NVIC_UNPEND3 0xE000E28C // Interrupt 96-127 Clear Pending +#define NVIC_UNPEND4 0xE000E290 // Interrupt 128-159 Clear Pending +#define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit +#define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-63 Active Bit +#define NVIC_ACTIVE2 0xE000E308 // Interrupt 64-95 Active Bit +#define NVIC_ACTIVE3 0xE000E30C // Interrupt 96-127 Active Bit +#define NVIC_ACTIVE4 0xE000E310 // Interrupt 128-159 Active Bit +#define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority +#define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority +#define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority +#define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority +#define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority +#define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority +#define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority +#define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority +#define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority +#define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority +#define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority +#define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority +#define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority +#define NVIC_PRI13 0xE000E434 // Interrupt 52-55 Priority +#define NVIC_PRI14 0xE000E438 // Interrupt 56-59 Priority +#define NVIC_PRI15 0xE000E43C // Interrupt 60-63 Priority +#define NVIC_PRI16 0xE000E440 // Interrupt 64-67 Priority +#define NVIC_PRI17 0xE000E444 // Interrupt 68-71 Priority +#define NVIC_PRI18 0xE000E448 // Interrupt 72-75 Priority +#define NVIC_PRI19 0xE000E44C // Interrupt 76-79 Priority +#define NVIC_PRI20 0xE000E450 // Interrupt 80-83 Priority +#define NVIC_PRI21 0xE000E454 // Interrupt 84-87 Priority +#define NVIC_PRI22 0xE000E458 // Interrupt 88-91 Priority +#define NVIC_PRI23 0xE000E45C // Interrupt 92-95 Priority +#define NVIC_PRI24 0xE000E460 // Interrupt 96-99 Priority +#define NVIC_PRI25 0xE000E464 // Interrupt 100-103 Priority +#define NVIC_PRI26 0xE000E468 // Interrupt 104-107 Priority +#define NVIC_PRI27 0xE000E46C // Interrupt 108-111 Priority +#define NVIC_PRI28 0xE000E470 // Interrupt 112-115 Priority +#define NVIC_PRI29 0xE000E474 // Interrupt 116-119 Priority +#define NVIC_PRI30 0xE000E478 // Interrupt 120-123 Priority +#define NVIC_PRI31 0xE000E47C // Interrupt 124-127 Priority +#define NVIC_PRI32 0xE000E480 // Interrupt 128-131 Priority +#define NVIC_PRI33 0xE000E484 // Interrupt 132-135 Priority +#define NVIC_PRI34 0xE000E488 // Interrupt 136-139 Priority +#define NVIC_CPUID 0xE000ED00 // CPU ID Base +#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State +#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset +#define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset + // Control +#define NVIC_SYS_CTRL 0xE000ED10 // System Control +#define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control +#define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1 +#define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2 +#define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3 +#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State +#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status +#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status +#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register +#define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address +#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address +#define NVIC_CPAC 0xE000ED88 // Coprocessor Access Control +#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type +#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control +#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number +#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address +#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size +#define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1 +#define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size + // Alias 1 +#define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2 +#define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size + // Alias 2 +#define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3 +#define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size + // Alias 3 +#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg +#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select +#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data +#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control +#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt +#define NVIC_FPCC 0xE000EF34 // Floating-Point Context Control +#define NVIC_FPCA 0xE000EF38 // Floating-Point Context Address +#define NVIC_FPDSC 0xE000EF3C // Floating-Point Default Status + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTLR register. +// +//***************************************************************************** +#define NVIC_ACTLR_DISOOFP 0x00000200 // Disable Out-Of-Order Floating + // Point +#define NVIC_ACTLR_DISFPCA 0x00000100 // Disable CONTROL +#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding +#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer +#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple + // Cycle Instructions + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CTRL register. +// +//***************************************************************************** +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag +#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_RELOAD register. +// +//***************************************************************************** +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value +#define NVIC_ST_RELOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CURRENT +// register. +// +//***************************************************************************** +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value +#define NVIC_ST_CURRENT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN0 register. +// +//***************************************************************************** +#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN1 register. +// +//***************************************************************************** +#define NVIC_EN1_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN2 register. +// +//***************************************************************************** +#define NVIC_EN2_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN3 register. +// +//***************************************************************************** +#define NVIC_EN3_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN4 register. +// +//***************************************************************************** +#define NVIC_EN4_INT_M 0x000007FF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS0 register. +// +//***************************************************************************** +#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS1 register. +// +//***************************************************************************** +#define NVIC_DIS1_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS2 register. +// +//***************************************************************************** +#define NVIC_DIS2_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS3 register. +// +//***************************************************************************** +#define NVIC_DIS3_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS4 register. +// +//***************************************************************************** +#define NVIC_DIS4_INT_M 0x000007FF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND0 register. +// +//***************************************************************************** +#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND1 register. +// +//***************************************************************************** +#define NVIC_PEND1_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND2 register. +// +//***************************************************************************** +#define NVIC_PEND2_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND3 register. +// +//***************************************************************************** +#define NVIC_PEND3_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND4 register. +// +//***************************************************************************** +#define NVIC_PEND4_INT_M 0x000007FF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND0 register. +// +//***************************************************************************** +#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND1 register. +// +//***************************************************************************** +#define NVIC_UNPEND1_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND2 register. +// +//***************************************************************************** +#define NVIC_UNPEND2_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND3 register. +// +//***************************************************************************** +#define NVIC_UNPEND3_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND4 register. +// +//***************************************************************************** +#define NVIC_UNPEND4_INT_M 0x000007FF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE0 register. +// +//***************************************************************************** +#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE1 register. +// +//***************************************************************************** +#define NVIC_ACTIVE1_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE2 register. +// +//***************************************************************************** +#define NVIC_ACTIVE2_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE3 register. +// +//***************************************************************************** +#define NVIC_ACTIVE3_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE4 register. +// +//***************************************************************************** +#define NVIC_ACTIVE4_INT_M 0x000007FF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI0 register. +// +//***************************************************************************** +#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask +#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask +#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask +#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask +#define NVIC_PRI0_INT3_S 29 +#define NVIC_PRI0_INT2_S 21 +#define NVIC_PRI0_INT1_S 13 +#define NVIC_PRI0_INT0_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI1 register. +// +//***************************************************************************** +#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask +#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask +#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask +#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask +#define NVIC_PRI1_INT7_S 29 +#define NVIC_PRI1_INT6_S 21 +#define NVIC_PRI1_INT5_S 13 +#define NVIC_PRI1_INT4_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI2 register. +// +//***************************************************************************** +#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask +#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask +#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask +#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask +#define NVIC_PRI2_INT11_S 29 +#define NVIC_PRI2_INT10_S 21 +#define NVIC_PRI2_INT9_S 13 +#define NVIC_PRI2_INT8_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI3 register. +// +//***************************************************************************** +#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask +#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask +#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask +#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask +#define NVIC_PRI3_INT15_S 29 +#define NVIC_PRI3_INT14_S 21 +#define NVIC_PRI3_INT13_S 13 +#define NVIC_PRI3_INT12_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI4 register. +// +//***************************************************************************** +#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask +#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask +#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask +#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask +#define NVIC_PRI4_INT19_S 29 +#define NVIC_PRI4_INT18_S 21 +#define NVIC_PRI4_INT17_S 13 +#define NVIC_PRI4_INT16_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI5 register. +// +//***************************************************************************** +#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask +#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask +#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask +#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask +#define NVIC_PRI5_INT23_S 29 +#define NVIC_PRI5_INT22_S 21 +#define NVIC_PRI5_INT21_S 13 +#define NVIC_PRI5_INT20_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI6 register. +// +//***************************************************************************** +#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask +#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask +#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask +#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask +#define NVIC_PRI6_INT27_S 29 +#define NVIC_PRI6_INT26_S 21 +#define NVIC_PRI6_INT25_S 13 +#define NVIC_PRI6_INT24_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI7 register. +// +//***************************************************************************** +#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask +#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask +#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask +#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask +#define NVIC_PRI7_INT31_S 29 +#define NVIC_PRI7_INT30_S 21 +#define NVIC_PRI7_INT29_S 13 +#define NVIC_PRI7_INT28_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI8 register. +// +//***************************************************************************** +#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask +#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask +#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask +#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask +#define NVIC_PRI8_INT35_S 29 +#define NVIC_PRI8_INT34_S 21 +#define NVIC_PRI8_INT33_S 13 +#define NVIC_PRI8_INT32_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI9 register. +// +//***************************************************************************** +#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask +#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask +#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask +#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask +#define NVIC_PRI9_INT39_S 29 +#define NVIC_PRI9_INT38_S 21 +#define NVIC_PRI9_INT37_S 13 +#define NVIC_PRI9_INT36_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI10 register. +// +//***************************************************************************** +#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask +#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask +#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask +#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask +#define NVIC_PRI10_INT43_S 29 +#define NVIC_PRI10_INT42_S 21 +#define NVIC_PRI10_INT41_S 13 +#define NVIC_PRI10_INT40_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI11 register. +// +//***************************************************************************** +#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask +#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask +#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask +#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask +#define NVIC_PRI11_INT47_S 29 +#define NVIC_PRI11_INT46_S 21 +#define NVIC_PRI11_INT45_S 13 +#define NVIC_PRI11_INT44_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI12 register. +// +//***************************************************************************** +#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask +#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask +#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask +#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask +#define NVIC_PRI12_INT51_S 29 +#define NVIC_PRI12_INT50_S 21 +#define NVIC_PRI12_INT49_S 13 +#define NVIC_PRI12_INT48_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI13 register. +// +//***************************************************************************** +#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask +#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask +#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask +#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask +#define NVIC_PRI13_INT55_S 29 +#define NVIC_PRI13_INT54_S 21 +#define NVIC_PRI13_INT53_S 13 +#define NVIC_PRI13_INT52_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI14 register. +// +//***************************************************************************** +#define NVIC_PRI14_INTD_M 0xE0000000 // Interrupt 59 Priority Mask +#define NVIC_PRI14_INTC_M 0x00E00000 // Interrupt 58 Priority Mask +#define NVIC_PRI14_INTB_M 0x0000E000 // Interrupt 57 Priority Mask +#define NVIC_PRI14_INTA_M 0x000000E0 // Interrupt 56 Priority Mask +#define NVIC_PRI14_INTD_S 29 +#define NVIC_PRI14_INTC_S 21 +#define NVIC_PRI14_INTB_S 13 +#define NVIC_PRI14_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI15 register. +// +//***************************************************************************** +#define NVIC_PRI15_INTD_M 0xE0000000 // Interrupt 63 Priority Mask +#define NVIC_PRI15_INTC_M 0x00E00000 // Interrupt 62 Priority Mask +#define NVIC_PRI15_INTB_M 0x0000E000 // Interrupt 61 Priority Mask +#define NVIC_PRI15_INTA_M 0x000000E0 // Interrupt 60 Priority Mask +#define NVIC_PRI15_INTD_S 29 +#define NVIC_PRI15_INTC_S 21 +#define NVIC_PRI15_INTB_S 13 +#define NVIC_PRI15_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI16 register. +// +//***************************************************************************** +#define NVIC_PRI16_INTD_M 0xE0000000 // Interrupt 67 Priority Mask +#define NVIC_PRI16_INTC_M 0x00E00000 // Interrupt 66 Priority Mask +#define NVIC_PRI16_INTB_M 0x0000E000 // Interrupt 65 Priority Mask +#define NVIC_PRI16_INTA_M 0x000000E0 // Interrupt 64 Priority Mask +#define NVIC_PRI16_INTD_S 29 +#define NVIC_PRI16_INTC_S 21 +#define NVIC_PRI16_INTB_S 13 +#define NVIC_PRI16_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI17 register. +// +//***************************************************************************** +#define NVIC_PRI17_INTD_M 0xE0000000 // Interrupt 71 Priority Mask +#define NVIC_PRI17_INTC_M 0x00E00000 // Interrupt 70 Priority Mask +#define NVIC_PRI17_INTB_M 0x0000E000 // Interrupt 69 Priority Mask +#define NVIC_PRI17_INTA_M 0x000000E0 // Interrupt 68 Priority Mask +#define NVIC_PRI17_INTD_S 29 +#define NVIC_PRI17_INTC_S 21 +#define NVIC_PRI17_INTB_S 13 +#define NVIC_PRI17_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI18 register. +// +//***************************************************************************** +#define NVIC_PRI18_INTD_M 0xE0000000 // Interrupt 75 Priority Mask +#define NVIC_PRI18_INTC_M 0x00E00000 // Interrupt 74 Priority Mask +#define NVIC_PRI18_INTB_M 0x0000E000 // Interrupt 73 Priority Mask +#define NVIC_PRI18_INTA_M 0x000000E0 // Interrupt 72 Priority Mask +#define NVIC_PRI18_INTD_S 29 +#define NVIC_PRI18_INTC_S 21 +#define NVIC_PRI18_INTB_S 13 +#define NVIC_PRI18_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI19 register. +// +//***************************************************************************** +#define NVIC_PRI19_INTD_M 0xE0000000 // Interrupt 79 Priority Mask +#define NVIC_PRI19_INTC_M 0x00E00000 // Interrupt 78 Priority Mask +#define NVIC_PRI19_INTB_M 0x0000E000 // Interrupt 77 Priority Mask +#define NVIC_PRI19_INTA_M 0x000000E0 // Interrupt 76 Priority Mask +#define NVIC_PRI19_INTD_S 29 +#define NVIC_PRI19_INTC_S 21 +#define NVIC_PRI19_INTB_S 13 +#define NVIC_PRI19_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI20 register. +// +//***************************************************************************** +#define NVIC_PRI20_INTD_M 0xE0000000 // Interrupt 83 Priority Mask +#define NVIC_PRI20_INTC_M 0x00E00000 // Interrupt 82 Priority Mask +#define NVIC_PRI20_INTB_M 0x0000E000 // Interrupt 81 Priority Mask +#define NVIC_PRI20_INTA_M 0x000000E0 // Interrupt 80 Priority Mask +#define NVIC_PRI20_INTD_S 29 +#define NVIC_PRI20_INTC_S 21 +#define NVIC_PRI20_INTB_S 13 +#define NVIC_PRI20_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI21 register. +// +//***************************************************************************** +#define NVIC_PRI21_INTD_M 0xE0000000 // Interrupt 87 Priority Mask +#define NVIC_PRI21_INTC_M 0x00E00000 // Interrupt 86 Priority Mask +#define NVIC_PRI21_INTB_M 0x0000E000 // Interrupt 85 Priority Mask +#define NVIC_PRI21_INTA_M 0x000000E0 // Interrupt 84 Priority Mask +#define NVIC_PRI21_INTD_S 29 +#define NVIC_PRI21_INTC_S 21 +#define NVIC_PRI21_INTB_S 13 +#define NVIC_PRI21_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI22 register. +// +//***************************************************************************** +#define NVIC_PRI22_INTD_M 0xE0000000 // Interrupt 91 Priority Mask +#define NVIC_PRI22_INTC_M 0x00E00000 // Interrupt 90 Priority Mask +#define NVIC_PRI22_INTB_M 0x0000E000 // Interrupt 89 Priority Mask +#define NVIC_PRI22_INTA_M 0x000000E0 // Interrupt 88 Priority Mask +#define NVIC_PRI22_INTD_S 29 +#define NVIC_PRI22_INTC_S 21 +#define NVIC_PRI22_INTB_S 13 +#define NVIC_PRI22_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI23 register. +// +//***************************************************************************** +#define NVIC_PRI23_INTD_M 0xE0000000 // Interrupt 95 Priority Mask +#define NVIC_PRI23_INTC_M 0x00E00000 // Interrupt 94 Priority Mask +#define NVIC_PRI23_INTB_M 0x0000E000 // Interrupt 93 Priority Mask +#define NVIC_PRI23_INTA_M 0x000000E0 // Interrupt 92 Priority Mask +#define NVIC_PRI23_INTD_S 29 +#define NVIC_PRI23_INTC_S 21 +#define NVIC_PRI23_INTB_S 13 +#define NVIC_PRI23_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI24 register. +// +//***************************************************************************** +#define NVIC_PRI24_INTD_M 0xE0000000 // Interrupt 99 Priority Mask +#define NVIC_PRI24_INTC_M 0x00E00000 // Interrupt 98 Priority Mask +#define NVIC_PRI24_INTB_M 0x0000E000 // Interrupt 97 Priority Mask +#define NVIC_PRI24_INTA_M 0x000000E0 // Interrupt 96 Priority Mask +#define NVIC_PRI24_INTD_S 29 +#define NVIC_PRI24_INTC_S 21 +#define NVIC_PRI24_INTB_S 13 +#define NVIC_PRI24_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI25 register. +// +//***************************************************************************** +#define NVIC_PRI25_INTD_M 0xE0000000 // Interrupt 103 Priority Mask +#define NVIC_PRI25_INTC_M 0x00E00000 // Interrupt 102 Priority Mask +#define NVIC_PRI25_INTB_M 0x0000E000 // Interrupt 101 Priority Mask +#define NVIC_PRI25_INTA_M 0x000000E0 // Interrupt 100 Priority Mask +#define NVIC_PRI25_INTD_S 29 +#define NVIC_PRI25_INTC_S 21 +#define NVIC_PRI25_INTB_S 13 +#define NVIC_PRI25_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI26 register. +// +//***************************************************************************** +#define NVIC_PRI26_INTD_M 0xE0000000 // Interrupt 107 Priority Mask +#define NVIC_PRI26_INTC_M 0x00E00000 // Interrupt 106 Priority Mask +#define NVIC_PRI26_INTB_M 0x0000E000 // Interrupt 105 Priority Mask +#define NVIC_PRI26_INTA_M 0x000000E0 // Interrupt 104 Priority Mask +#define NVIC_PRI26_INTD_S 29 +#define NVIC_PRI26_INTC_S 21 +#define NVIC_PRI26_INTB_S 13 +#define NVIC_PRI26_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI27 register. +// +//***************************************************************************** +#define NVIC_PRI27_INTD_M 0xE0000000 // Interrupt 111 Priority Mask +#define NVIC_PRI27_INTC_M 0x00E00000 // Interrupt 110 Priority Mask +#define NVIC_PRI27_INTB_M 0x0000E000 // Interrupt 109 Priority Mask +#define NVIC_PRI27_INTA_M 0x000000E0 // Interrupt 108 Priority Mask +#define NVIC_PRI27_INTD_S 29 +#define NVIC_PRI27_INTC_S 21 +#define NVIC_PRI27_INTB_S 13 +#define NVIC_PRI27_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI28 register. +// +//***************************************************************************** +#define NVIC_PRI28_INTD_M 0xE0000000 // Interrupt 115 Priority Mask +#define NVIC_PRI28_INTC_M 0x00E00000 // Interrupt 114 Priority Mask +#define NVIC_PRI28_INTB_M 0x0000E000 // Interrupt 113 Priority Mask +#define NVIC_PRI28_INTA_M 0x000000E0 // Interrupt 112 Priority Mask +#define NVIC_PRI28_INTD_S 29 +#define NVIC_PRI28_INTC_S 21 +#define NVIC_PRI28_INTB_S 13 +#define NVIC_PRI28_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI29 register. +// +//***************************************************************************** +#define NVIC_PRI29_INTD_M 0xE0000000 // Interrupt 119 Priority Mask +#define NVIC_PRI29_INTC_M 0x00E00000 // Interrupt 118 Priority Mask +#define NVIC_PRI29_INTB_M 0x0000E000 // Interrupt 117 Priority Mask +#define NVIC_PRI29_INTA_M 0x000000E0 // Interrupt 116 Priority Mask +#define NVIC_PRI29_INTD_S 29 +#define NVIC_PRI29_INTC_S 21 +#define NVIC_PRI29_INTB_S 13 +#define NVIC_PRI29_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI30 register. +// +//***************************************************************************** +#define NVIC_PRI30_INTD_M 0xE0000000 // Interrupt 123 Priority Mask +#define NVIC_PRI30_INTC_M 0x00E00000 // Interrupt 122 Priority Mask +#define NVIC_PRI30_INTB_M 0x0000E000 // Interrupt 121 Priority Mask +#define NVIC_PRI30_INTA_M 0x000000E0 // Interrupt 120 Priority Mask +#define NVIC_PRI30_INTD_S 29 +#define NVIC_PRI30_INTC_S 21 +#define NVIC_PRI30_INTB_S 13 +#define NVIC_PRI30_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI31 register. +// +//***************************************************************************** +#define NVIC_PRI31_INTD_M 0xE0000000 // Interrupt 127 Priority Mask +#define NVIC_PRI31_INTC_M 0x00E00000 // Interrupt 126 Priority Mask +#define NVIC_PRI31_INTB_M 0x0000E000 // Interrupt 125 Priority Mask +#define NVIC_PRI31_INTA_M 0x000000E0 // Interrupt 124 Priority Mask +#define NVIC_PRI31_INTD_S 29 +#define NVIC_PRI31_INTC_S 21 +#define NVIC_PRI31_INTB_S 13 +#define NVIC_PRI31_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI32 register. +// +//***************************************************************************** +#define NVIC_PRI32_INTD_M 0xE0000000 // Interrupt 131 Priority Mask +#define NVIC_PRI32_INTC_M 0x00E00000 // Interrupt 130 Priority Mask +#define NVIC_PRI32_INTB_M 0x0000E000 // Interrupt 129 Priority Mask +#define NVIC_PRI32_INTA_M 0x000000E0 // Interrupt 128 Priority Mask +#define NVIC_PRI32_INTD_S 29 +#define NVIC_PRI32_INTC_S 21 +#define NVIC_PRI32_INTB_S 13 +#define NVIC_PRI32_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI33 register. +// +//***************************************************************************** +#define NVIC_PRI33_INTD_M 0xE0000000 // Interrupt Priority for Interrupt + // [4n+3] +#define NVIC_PRI33_INTC_M 0x00E00000 // Interrupt Priority for Interrupt + // [4n+2] +#define NVIC_PRI33_INTB_M 0x0000E000 // Interrupt Priority for Interrupt + // [4n+1] +#define NVIC_PRI33_INTA_M 0x000000E0 // Interrupt Priority for Interrupt + // [4n] +#define NVIC_PRI33_INTD_S 29 +#define NVIC_PRI33_INTC_S 21 +#define NVIC_PRI33_INTB_S 13 +#define NVIC_PRI33_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI34 register. +// +//***************************************************************************** +#define NVIC_PRI34_INTD_M 0xE0000000 // Interrupt Priority for Interrupt + // [4n+3] +#define NVIC_PRI34_INTC_M 0x00E00000 // Interrupt Priority for Interrupt + // [4n+2] +#define NVIC_PRI34_INTB_M 0x0000E000 // Interrupt Priority for Interrupt + // [4n+1] +#define NVIC_PRI34_INTA_M 0x000000E0 // Interrupt Priority for Interrupt + // [4n] +#define NVIC_PRI34_INTD_S 29 +#define NVIC_PRI34_INTC_S 21 +#define NVIC_PRI34_INTB_S 13 +#define NVIC_PRI34_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CPUID register. +// +//***************************************************************************** +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code +#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number +#define NVIC_CPUID_CON_M 0x000F0000 // Constant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number +#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor +#define NVIC_CPUID_REV_M 0x0000000F // Revision Number + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_INT_CTRL register. +// +//***************************************************************************** +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending +#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending +#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number +#define NVIC_INT_CTRL_VEC_PEN_NMI \ + 0x00002000 // NMI +#define NVIC_INT_CTRL_VEC_PEN_HARD \ + 0x00003000 // Hard fault +#define NVIC_INT_CTRL_VEC_PEN_MEM \ + 0x00004000 // Memory management fault +#define NVIC_INT_CTRL_VEC_PEN_BUS \ + 0x00005000 // Bus fault +#define NVIC_INT_CTRL_VEC_PEN_USG \ + 0x00006000 // Usage fault +#define NVIC_INT_CTRL_VEC_PEN_SVC \ + 0x0000B000 // SVCall +#define NVIC_INT_CTRL_VEC_PEN_PNDSV \ + 0x0000E000 // PendSV +#define NVIC_INT_CTRL_VEC_PEN_TICK \ + 0x0000F000 // SysTick +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base +#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number +#define NVIC_INT_CTRL_VEC_ACT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_VTABLE register. +// +//***************************************************************************** +#define NVIC_VTABLE_OFFSET_M 0xFFFFFC00 // Vector Table Offset +#define NVIC_VTABLE_OFFSET_S 10 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_APINT register. +// +//***************************************************************************** +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key +#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key +#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping +#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split +#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split +#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split +#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split +#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split +#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split +#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split +#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault +#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CFG_CTRL register. +// +//***************************************************************************** +#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception + // Entry +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and + // Fault +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI1 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority +#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority +#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority +#define NVIC_SYS_PRI1_USAGE_S 21 +#define NVIC_SYS_PRI1_BUS_S 13 +#define NVIC_SYS_PRI1_MEM_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI2 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority +#define NVIC_SYS_PRI2_SVC_S 29 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI3 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority +#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority +#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority +#define NVIC_SYS_PRI3_TICK_S 29 +#define NVIC_SYS_PRI3_PENDSV_S 21 +#define NVIC_SYS_PRI3_DEBUG_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL +// register. +// +//***************************************************************************** +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending +#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending +#define NVIC_SYS_HND_CTRL_USAGEP \ + 0x00001000 // Usage Fault Pending +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage + // Fault +#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid +#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy + // State Preservation +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error +#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address + // Register Valid +#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on + // Floating-Point Lazy State + // Preservation +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_HFAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DEBUG_STAT +// register. +// +//***************************************************************************** +#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted +#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch +#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match +#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction +#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MM_ADDR register. +// +//***************************************************************************** +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_MM_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_ADDR +// register. +// +//***************************************************************************** +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_FAULT_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CPAC register. +// +//***************************************************************************** +#define NVIC_CPAC_CP11_M 0x00C00000 // CP11 Coprocessor Access + // Privilege +#define NVIC_CPAC_CP11_DIS 0x00000000 // Access Denied +#define NVIC_CPAC_CP11_PRIV 0x00400000 // Privileged Access Only +#define NVIC_CPAC_CP11_FULL 0x00C00000 // Full Access +#define NVIC_CPAC_CP10_M 0x00300000 // CP10 Coprocessor Access + // Privilege +#define NVIC_CPAC_CP10_DIS 0x00000000 // Access Denied +#define NVIC_CPAC_CP10_PRIV 0x00100000 // Privileged Access Only +#define NVIC_CPAC_CP10_FULL 0x00300000 // Full Access + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_TYPE register. +// +//***************************************************************************** +#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I Regions +#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D Regions +#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or Unified MPU +#define NVIC_MPU_TYPE_IREGION_S 16 +#define NVIC_MPU_TYPE_DREGION_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_CTRL register. +// +//***************************************************************************** +#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU Default Region +#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU Enabled During Faults +#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_NUMBER +// register. +// +//***************************************************************************** +#define NVIC_MPU_NUMBER_M 0x00000007 // MPU Region to Access +#define NVIC_MPU_NUMBER_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE register. +// +//***************************************************************************** +#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE_ADDR_S 5 +#define NVIC_MPU_BASE_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 // prv: no access, usr: no access +#define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 // prv: rw, usr: none +#define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 // prv: rw, usr: read-only +#define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 // prv: rw, usr: rw +#define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 // prv: ro, usr: none +#define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 // prv: ro, usr: ro +#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable +#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable +#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable +#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR_SRD_0 0x00000100 // Sub-region 0 disable +#define NVIC_MPU_ATTR_SRD_1 0x00000200 // Sub-region 1 disable +#define NVIC_MPU_ATTR_SRD_2 0x00000400 // Sub-region 2 disable +#define NVIC_MPU_ATTR_SRD_3 0x00000800 // Sub-region 3 disable +#define NVIC_MPU_ATTR_SRD_4 0x00001000 // Sub-region 4 disable +#define NVIC_MPU_ATTR_SRD_5 0x00002000 // Sub-region 5 disable +#define NVIC_MPU_ATTR_SRD_6 0x00004000 // Sub-region 6 disable +#define NVIC_MPU_ATTR_SRD_7 0x00008000 // Sub-region 7 disable +#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR_SIZE_32B 0x00000008 // Region size 32 bytes +#define NVIC_MPU_ATTR_SIZE_64B 0x0000000A // Region size 64 bytes +#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C // Region size 128 bytes +#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E // Region size 256 bytes +#define NVIC_MPU_ATTR_SIZE_512B 0x00000010 // Region size 512 bytes +#define NVIC_MPU_ATTR_SIZE_1K 0x00000012 // Region size 1 Kbytes +#define NVIC_MPU_ATTR_SIZE_2K 0x00000014 // Region size 2 Kbytes +#define NVIC_MPU_ATTR_SIZE_4K 0x00000016 // Region size 4 Kbytes +#define NVIC_MPU_ATTR_SIZE_8K 0x00000018 // Region size 8 Kbytes +#define NVIC_MPU_ATTR_SIZE_16K 0x0000001A // Region size 16 Kbytes +#define NVIC_MPU_ATTR_SIZE_32K 0x0000001C // Region size 32 Kbytes +#define NVIC_MPU_ATTR_SIZE_64K 0x0000001E // Region size 64 Kbytes +#define NVIC_MPU_ATTR_SIZE_128K 0x00000020 // Region size 128 Kbytes +#define NVIC_MPU_ATTR_SIZE_256K 0x00000022 // Region size 256 Kbytes +#define NVIC_MPU_ATTR_SIZE_512K 0x00000024 // Region size 512 Kbytes +#define NVIC_MPU_ATTR_SIZE_1M 0x00000026 // Region size 1 Mbytes +#define NVIC_MPU_ATTR_SIZE_2M 0x00000028 // Region size 2 Mbytes +#define NVIC_MPU_ATTR_SIZE_4M 0x0000002A // Region size 4 Mbytes +#define NVIC_MPU_ATTR_SIZE_8M 0x0000002C // Region size 8 Mbytes +#define NVIC_MPU_ATTR_SIZE_16M 0x0000002E // Region size 16 Mbytes +#define NVIC_MPU_ATTR_SIZE_32M 0x00000030 // Region size 32 Mbytes +#define NVIC_MPU_ATTR_SIZE_64M 0x00000032 // Region size 64 Mbytes +#define NVIC_MPU_ATTR_SIZE_128M 0x00000034 // Region size 128 Mbytes +#define NVIC_MPU_ATTR_SIZE_256M 0x00000036 // Region size 256 Mbytes +#define NVIC_MPU_ATTR_SIZE_512M 0x00000038 // Region size 512 Mbytes +#define NVIC_MPU_ATTR_SIZE_1G 0x0000003A // Region size 1 Gbytes +#define NVIC_MPU_ATTR_SIZE_2G 0x0000003C // Region size 2 Gbytes +#define NVIC_MPU_ATTR_SIZE_4G 0x0000003E // Region size 4 Gbytes +#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE1 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE1_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE1_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE1_ADDR_S 5 +#define NVIC_MPU_BASE1_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR1_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR1_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR1_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR1_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR1_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR1_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR1_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR1_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR1_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE2 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE2_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE2_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE2_ADDR_S 5 +#define NVIC_MPU_BASE2_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR2_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR2_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR2_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR2_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR2_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR2_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR2_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR2_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR2_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE3 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE3_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE3_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE3_ADDR_S 5 +#define NVIC_MPU_BASE3_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR3_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR3_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR3_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR3_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR3_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR3_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR3_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR3_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR3_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_CTRL register. +// +//***************************************************************************** +#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask +#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key +#define NVIC_DBG_CTRL_S_RESET_ST \ + 0x02000000 // Core has reset since last read +#define NVIC_DBG_CTRL_S_RETIRE_ST \ + 0x01000000 // Core has executed insruction + // since last read +#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up +#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping +#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt +#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available +#define NVIC_DBG_CTRL_C_SNAPSTALL \ + 0x00000020 // Breaks a stalled load/store +#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping +#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core +#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core +#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_XFER register. +// +//***************************************************************************** +#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read +#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register +#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 +#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 +#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 +#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 +#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 +#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 +#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 +#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 +#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 +#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 +#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 +#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 +#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 +#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 +#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 +#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 +#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register +#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP +#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP +#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP +#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_DATA register. +// +//***************************************************************************** +#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache +#define NVIC_DBG_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_INT register. +// +//***************************************************************************** +#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault +#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors +#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error +#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state +#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check +#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error +#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault +#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status +#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset +#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending +#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SW_TRIG register. +// +//***************************************************************************** +#define NVIC_SW_TRIG_INTID_M 0x000000FF // Interrupt ID +#define NVIC_SW_TRIG_INTID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FPCC register. +// +//***************************************************************************** +#define NVIC_FPCC_ASPEN 0x80000000 // Automatic State Preservation + // Enable +#define NVIC_FPCC_LSPEN 0x40000000 // Lazy State Preservation Enable +#define NVIC_FPCC_MONRDY 0x00000100 // Monitor Ready +#define NVIC_FPCC_BFRDY 0x00000040 // Bus Fault Ready +#define NVIC_FPCC_MMRDY 0x00000020 // Memory Management Fault Ready +#define NVIC_FPCC_HFRDY 0x00000010 // Hard Fault Ready +#define NVIC_FPCC_THREAD 0x00000008 // Thread Mode +#define NVIC_FPCC_USER 0x00000002 // User Privilege Level +#define NVIC_FPCC_LSPACT 0x00000001 // Lazy State Preservation Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FPCA register. +// +//***************************************************************************** +#define NVIC_FPCA_ADDRESS_M 0xFFFFFFF8 // Address +#define NVIC_FPCA_ADDRESS_S 3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FPDSC register. +// +//***************************************************************************** +#define NVIC_FPDSC_AHP 0x04000000 // AHP Bit Default +#define NVIC_FPDSC_DN 0x02000000 // DN Bit Default +#define NVIC_FPDSC_FZ 0x01000000 // FZ Bit Default +#define NVIC_FPDSC_RMODE_M 0x00C00000 // RMODE Bit Default +#define NVIC_FPDSC_RMODE_RN 0x00000000 // Round to Nearest (RN) mode +#define NVIC_FPDSC_RMODE_RP 0x00400000 // Round towards Plus Infinity (RP) + // mode +#define NVIC_FPDSC_RMODE_RM 0x00800000 // Round towards Minus Infinity + // (RM) mode +#define NVIC_FPDSC_RMODE_RZ 0x00C00000 // Round towards Zero (RZ) mode + +#endif // __HW_NVIC_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_onewire.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_onewire.h new file mode 100644 index 0000000000000000000000000000000000000000..bf810b7ce93a0fc4c6e005c7ce724ccaf428ad1f --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_onewire.h @@ -0,0 +1,223 @@ +//***************************************************************************** +// +// hw_onewire.h - Macros used when accessing the One wire hardware. +// +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_ONEWIRE_H__ +#define __HW_ONEWIRE_H__ + +//***************************************************************************** +// +// The following are defines for the One wire register offsets. +// +//***************************************************************************** +#define ONEWIRE_O_CS 0x00000000 // 1-Wire Control and Status +#define ONEWIRE_O_TIM 0x00000004 // 1-Wire Timing Override +#define ONEWIRE_O_DATW 0x00000008 // 1-Wire Data Write +#define ONEWIRE_O_DATR 0x0000000C // 1-Wire Data Read +#define ONEWIRE_O_IM 0x00000100 // 1-Wire Interrupt Mask +#define ONEWIRE_O_RIS 0x00000104 // 1-Wire Raw Interrupt Status +#define ONEWIRE_O_MIS 0x00000108 // 1-Wire Masked Interrupt Status +#define ONEWIRE_O_ICR 0x0000010C // 1-Wire Interrupt Clear +#define ONEWIRE_O_DMA 0x00000120 // 1-Wire uDMA Control +#define ONEWIRE_O_PP 0x00000FC0 // 1-Wire Peripheral Properties + +//***************************************************************************** +// +// The following are defines for the bit fields in the ONEWIRE_O_CS register. +// +//***************************************************************************** +#define ONEWIRE_CS_USEALT 0x80000000 // Two Wire Enable +#define ONEWIRE_CS_ALTP 0x40000000 // Alternate Polarity Enable +#define ONEWIRE_CS_BSIZE_M 0x00070000 // Last Byte Size +#define ONEWIRE_CS_BSIZE_8 0x00000000 // 8 bits (1 byte) +#define ONEWIRE_CS_BSIZE_1 0x00010000 // 1 bit +#define ONEWIRE_CS_BSIZE_2 0x00020000 // 2 bits +#define ONEWIRE_CS_BSIZE_3 0x00030000 // 3 bits +#define ONEWIRE_CS_BSIZE_4 0x00040000 // 4 bits +#define ONEWIRE_CS_BSIZE_5 0x00050000 // 5 bits +#define ONEWIRE_CS_BSIZE_6 0x00060000 // 6 bits +#define ONEWIRE_CS_BSIZE_7 0x00070000 // 7 bits +#define ONEWIRE_CS_STUCK 0x00000400 // STUCK Status +#define ONEWIRE_CS_NOATR 0x00000200 // Answer-to-Reset Status +#define ONEWIRE_CS_BUSY 0x00000100 // Busy Status +#define ONEWIRE_CS_SKATR 0x00000080 // Skip Answer-to-Reset Enable +#define ONEWIRE_CS_LSAM 0x00000040 // Late Sample Enable +#define ONEWIRE_CS_ODRV 0x00000020 // Overdrive Enable +#define ONEWIRE_CS_SZ_M 0x00000018 // Data Operation Size +#define ONEWIRE_CS_OP_M 0x00000006 // Operation Request +#define ONEWIRE_CS_OP_NONE 0x00000000 // No operation +#define ONEWIRE_CS_OP_RD 0x00000002 // Read +#define ONEWIRE_CS_OP_WR 0x00000004 // Write +#define ONEWIRE_CS_OP_WRRD 0x00000006 // Write/Read +#define ONEWIRE_CS_RST 0x00000001 // Reset Request +#define ONEWIRE_CS_SZ_S 3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ONEWIRE_O_TIM register. +// +//***************************************************************************** +#define ONEWIRE_TIM_W1TIM_M 0xF0000000 // Value '1' Timing +#define ONEWIRE_TIM_W0TIM_M 0x0F800000 // Value '0' Timing +#define ONEWIRE_TIM_W0REST_M 0x00780000 // Rest Time +#define ONEWIRE_TIM_W1SAM_M 0x00078000 // Sample Time +#define ONEWIRE_TIM_ATRSAM_M 0x00007800 // Answer-to-Reset Sample +#define ONEWIRE_TIM_ATRTIM_M 0x000007C0 // Answer-to-Reset/Rest Period +#define ONEWIRE_TIM_RSTTIM_M 0x0000003F // Reset Low Time +#define ONEWIRE_TIM_W1TIM_S 28 +#define ONEWIRE_TIM_W0TIM_S 23 +#define ONEWIRE_TIM_W0REST_S 19 +#define ONEWIRE_TIM_W1SAM_S 15 +#define ONEWIRE_TIM_ATRSAM_S 11 +#define ONEWIRE_TIM_ATRTIM_S 6 +#define ONEWIRE_TIM_RSTTIM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ONEWIRE_O_DATW register. +// +//***************************************************************************** +#define ONEWIRE_DATW_B3_M 0xFF000000 // Upper Data Byte +#define ONEWIRE_DATW_B2_M 0x00FF0000 // Upper Middle Data Byte +#define ONEWIRE_DATW_B1_M 0x0000FF00 // Lower Middle Data Byte +#define ONEWIRE_DATW_B0_M 0x000000FF // Lowest Data Byte +#define ONEWIRE_DATW_B3_S 24 +#define ONEWIRE_DATW_B2_S 16 +#define ONEWIRE_DATW_B1_S 8 +#define ONEWIRE_DATW_B0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ONEWIRE_O_DATR register. +// +//***************************************************************************** +#define ONEWIRE_DATR_B3_M 0xFF000000 // Upper Data Byte +#define ONEWIRE_DATR_B2_M 0x00FF0000 // Upper Middle Data Byte +#define ONEWIRE_DATR_B1_M 0x0000FF00 // Lower Middle Data Byte +#define ONEWIRE_DATR_B0_M 0x000000FF // Lowest Data Byte +#define ONEWIRE_DATR_B3_S 24 +#define ONEWIRE_DATR_B2_S 16 +#define ONEWIRE_DATR_B1_S 8 +#define ONEWIRE_DATR_B0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ONEWIRE_O_IM register. +// +//***************************************************************************** +#define ONEWIRE_IM_DMA 0x00000010 // DMA Done Interrupt Mask +#define ONEWIRE_IM_STUCK 0x00000008 // Stuck Status Interrupt Mask +#define ONEWIRE_IM_NOATR 0x00000004 // No Answer-to-Reset Interrupt + // Mask +#define ONEWIRE_IM_OPC 0x00000002 // Operation Complete Interrupt + // Mask +#define ONEWIRE_IM_RST 0x00000001 // Reset Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the ONEWIRE_O_RIS register. +// +//***************************************************************************** +#define ONEWIRE_RIS_DMA 0x00000010 // DMA Done Raw Interrupt Status +#define ONEWIRE_RIS_STUCK 0x00000008 // Stuck Status Raw Interrupt + // Status +#define ONEWIRE_RIS_NOATR 0x00000004 // No Answer-to-Reset Raw Interrupt + // Status +#define ONEWIRE_RIS_OPC 0x00000002 // Operation Complete Raw Interrupt + // Status +#define ONEWIRE_RIS_RST 0x00000001 // Reset Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the ONEWIRE_O_MIS register. +// +//***************************************************************************** +#define ONEWIRE_MIS_DMA 0x00000010 // DMA Done Masked Interrupt Status +#define ONEWIRE_MIS_STUCK 0x00000008 // Stuck Status Masked Interrupt + // Status +#define ONEWIRE_MIS_NOATR 0x00000004 // No Answer-to-Reset Masked + // Interrupt Status +#define ONEWIRE_MIS_OPC 0x00000002 // Operation Complete Masked + // Interrupt Status +#define ONEWIRE_MIS_RST 0x00000001 // Reset Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the ONEWIRE_O_ICR register. +// +//***************************************************************************** +#define ONEWIRE_ICR_DMA 0x00000010 // DMA Done Interrupt Clear +#define ONEWIRE_ICR_STUCK 0x00000008 // Stuck Status Interrupt Clear +#define ONEWIRE_ICR_NOATR 0x00000004 // No Answer-to-Reset Interrupt + // Clear +#define ONEWIRE_ICR_OPC 0x00000002 // Operation Complete Interrupt + // Clear +#define ONEWIRE_ICR_RST 0x00000001 // Reset Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the ONEWIRE_O_DMA register. +// +//***************************************************************************** +#define ONEWIRE_DMA_SG 0x00000008 // Scatter-Gather Enable +#define ONEWIRE_DMA_DMAOP_M 0x00000006 // uDMA Operation +#define ONEWIRE_DMA_DMAOP_DIS 0x00000000 // uDMA disabled +#define ONEWIRE_DMA_DMAOP_RDSNG 0x00000002 // uDMA single read: 1-Wire + // requests uDMA to read + // ONEWIREDATR register after each + // read transaction +#define ONEWIRE_DMA_DMAOP_WRMUL 0x00000004 // uDMA multiple write: 1-Wire + // requests uDMA to load whenever + // the ONEWIREDATW register is + // empty +#define ONEWIRE_DMA_DMAOP_RDMUL 0x00000006 // uDMA multiple read: An initial + // read occurs and subsequent reads + // start after uDMA has read the + // ONEWIREDATR register +#define ONEWIRE_DMA_RST 0x00000001 // uDMA Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the ONEWIRE_O_PP register. +// +//***************************************************************************** +#define ONEWIRE_PP_DMAP 0x00000010 // uDMA Present +#define ONEWIRE_PP_CNT_M 0x00000003 // 1-Wire Bus Count +#define ONEWIRE_PP_CNT_S 0 + +#endif // __HW_ONEWIRE_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_pwm.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_pwm.h new file mode 100644 index 0000000000000000000000000000000000000000..2167aad93abe84c3bc765d2a8392275167a93bcd --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_pwm.h @@ -0,0 +1,1885 @@ +//***************************************************************************** +// +// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_PWM_H__ +#define __HW_PWM_H__ + +//***************************************************************************** +// +// The following are defines for the PWM register offsets. +// +//***************************************************************************** +#define PWM_O_CTL 0x00000000 // PWM Master Control +#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync +#define PWM_O_ENABLE 0x00000008 // PWM Output Enable +#define PWM_O_INVERT 0x0000000C // PWM Output Inversion +#define PWM_O_FAULT 0x00000010 // PWM Output Fault +#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable +#define PWM_O_RIS 0x00000018 // PWM Raw Interrupt Status +#define PWM_O_ISC 0x0000001C // PWM Interrupt Status and Clear +#define PWM_O_STATUS 0x00000020 // PWM Status +#define PWM_O_FAULTVAL 0x00000024 // PWM Fault Condition Value +#define PWM_O_ENUPD 0x00000028 // PWM Enable Update +#define PWM_O_0_CTL 0x00000040 // PWM0 Control +#define PWM_O_0_INTEN 0x00000044 // PWM0 Interrupt and Trigger + // Enable +#define PWM_O_0_RIS 0x00000048 // PWM0 Raw Interrupt Status +#define PWM_O_0_ISC 0x0000004C // PWM0 Interrupt Status and Clear +#define PWM_O_0_LOAD 0x00000050 // PWM0 Load +#define PWM_O_0_COUNT 0x00000054 // PWM0 Counter +#define PWM_O_0_CMPA 0x00000058 // PWM0 Compare A +#define PWM_O_0_CMPB 0x0000005C // PWM0 Compare B +#define PWM_O_0_GENA 0x00000060 // PWM0 Generator A Control +#define PWM_O_0_GENB 0x00000064 // PWM0 Generator B Control +#define PWM_O_0_DBCTL 0x00000068 // PWM0 Dead-Band Control +#define PWM_O_0_DBRISE 0x0000006C // PWM0 Dead-Band Rising-Edge Delay +#define PWM_O_0_DBFALL 0x00000070 // PWM0 Dead-Band + // Falling-Edge-Delay +#define PWM_O_0_FLTSRC0 0x00000074 // PWM0 Fault Source 0 +#define PWM_O_0_FLTSRC1 0x00000078 // PWM0 Fault Source 1 +#define PWM_O_0_MINFLTPER 0x0000007C // PWM0 Minimum Fault Period +#define PWM_O_1_CTL 0x00000080 // PWM1 Control +#define PWM_O_1_INTEN 0x00000084 // PWM1 Interrupt and Trigger + // Enable +#define PWM_O_1_RIS 0x00000088 // PWM1 Raw Interrupt Status +#define PWM_O_1_ISC 0x0000008C // PWM1 Interrupt Status and Clear +#define PWM_O_1_LOAD 0x00000090 // PWM1 Load +#define PWM_O_1_COUNT 0x00000094 // PWM1 Counter +#define PWM_O_1_CMPA 0x00000098 // PWM1 Compare A +#define PWM_O_1_CMPB 0x0000009C // PWM1 Compare B +#define PWM_O_1_GENA 0x000000A0 // PWM1 Generator A Control +#define PWM_O_1_GENB 0x000000A4 // PWM1 Generator B Control +#define PWM_O_1_DBCTL 0x000000A8 // PWM1 Dead-Band Control +#define PWM_O_1_DBRISE 0x000000AC // PWM1 Dead-Band Rising-Edge Delay +#define PWM_O_1_DBFALL 0x000000B0 // PWM1 Dead-Band + // Falling-Edge-Delay +#define PWM_O_1_FLTSRC0 0x000000B4 // PWM1 Fault Source 0 +#define PWM_O_1_FLTSRC1 0x000000B8 // PWM1 Fault Source 1 +#define PWM_O_1_MINFLTPER 0x000000BC // PWM1 Minimum Fault Period +#define PWM_O_2_CTL 0x000000C0 // PWM2 Control +#define PWM_O_2_INTEN 0x000000C4 // PWM2 Interrupt and Trigger + // Enable +#define PWM_O_2_RIS 0x000000C8 // PWM2 Raw Interrupt Status +#define PWM_O_2_ISC 0x000000CC // PWM2 Interrupt Status and Clear +#define PWM_O_2_LOAD 0x000000D0 // PWM2 Load +#define PWM_O_2_COUNT 0x000000D4 // PWM2 Counter +#define PWM_O_2_CMPA 0x000000D8 // PWM2 Compare A +#define PWM_O_2_CMPB 0x000000DC // PWM2 Compare B +#define PWM_O_2_GENA 0x000000E0 // PWM2 Generator A Control +#define PWM_O_2_GENB 0x000000E4 // PWM2 Generator B Control +#define PWM_O_2_DBCTL 0x000000E8 // PWM2 Dead-Band Control +#define PWM_O_2_DBRISE 0x000000EC // PWM2 Dead-Band Rising-Edge Delay +#define PWM_O_2_DBFALL 0x000000F0 // PWM2 Dead-Band + // Falling-Edge-Delay +#define PWM_O_2_FLTSRC0 0x000000F4 // PWM2 Fault Source 0 +#define PWM_O_2_FLTSRC1 0x000000F8 // PWM2 Fault Source 1 +#define PWM_O_2_MINFLTPER 0x000000FC // PWM2 Minimum Fault Period +#define PWM_O_3_CTL 0x00000100 // PWM3 Control +#define PWM_O_3_INTEN 0x00000104 // PWM3 Interrupt and Trigger + // Enable +#define PWM_O_3_RIS 0x00000108 // PWM3 Raw Interrupt Status +#define PWM_O_3_ISC 0x0000010C // PWM3 Interrupt Status and Clear +#define PWM_O_3_LOAD 0x00000110 // PWM3 Load +#define PWM_O_3_COUNT 0x00000114 // PWM3 Counter +#define PWM_O_3_CMPA 0x00000118 // PWM3 Compare A +#define PWM_O_3_CMPB 0x0000011C // PWM3 Compare B +#define PWM_O_3_GENA 0x00000120 // PWM3 Generator A Control +#define PWM_O_3_GENB 0x00000124 // PWM3 Generator B Control +#define PWM_O_3_DBCTL 0x00000128 // PWM3 Dead-Band Control +#define PWM_O_3_DBRISE 0x0000012C // PWM3 Dead-Band Rising-Edge Delay +#define PWM_O_3_DBFALL 0x00000130 // PWM3 Dead-Band + // Falling-Edge-Delay +#define PWM_O_3_FLTSRC0 0x00000134 // PWM3 Fault Source 0 +#define PWM_O_3_FLTSRC1 0x00000138 // PWM3 Fault Source 1 +#define PWM_O_3_MINFLTPER 0x0000013C // PWM3 Minimum Fault Period +#define PWM_O_0_FLTSEN 0x00000800 // PWM0 Fault Pin Logic Sense +#define PWM_O_0_FLTSTAT0 0x00000804 // PWM0 Fault Status 0 +#define PWM_O_0_FLTSTAT1 0x00000808 // PWM0 Fault Status 1 +#define PWM_O_1_FLTSEN 0x00000880 // PWM1 Fault Pin Logic Sense +#define PWM_O_1_FLTSTAT0 0x00000884 // PWM1 Fault Status 0 +#define PWM_O_1_FLTSTAT1 0x00000888 // PWM1 Fault Status 1 +#define PWM_O_2_FLTSEN 0x00000900 // PWM2 Fault Pin Logic Sense +#define PWM_O_2_FLTSTAT0 0x00000904 // PWM2 Fault Status 0 +#define PWM_O_2_FLTSTAT1 0x00000908 // PWM2 Fault Status 1 +#define PWM_O_3_FLTSEN 0x00000980 // PWM3 Fault Pin Logic Sense +#define PWM_O_3_FLTSTAT0 0x00000984 // PWM3 Fault Status 0 +#define PWM_O_3_FLTSTAT1 0x00000988 // PWM3 Fault Status 1 +#define PWM_O_PP 0x00000FC0 // PWM Peripheral Properties +#define PWM_O_CC 0x00000FC8 // PWM Clock Configuration + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_CTL register. +// +//***************************************************************************** +#define PWM_CTL_GLOBALSYNC3 0x00000008 // Update PWM Generator 3 +#define PWM_CTL_GLOBALSYNC2 0x00000004 // Update PWM Generator 2 +#define PWM_CTL_GLOBALSYNC1 0x00000002 // Update PWM Generator 1 +#define PWM_CTL_GLOBALSYNC0 0x00000001 // Update PWM Generator 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_SYNC register. +// +//***************************************************************************** +#define PWM_SYNC_SYNC3 0x00000008 // Reset Generator 3 Counter +#define PWM_SYNC_SYNC2 0x00000004 // Reset Generator 2 Counter +#define PWM_SYNC_SYNC1 0x00000002 // Reset Generator 1 Counter +#define PWM_SYNC_SYNC0 0x00000001 // Reset Generator 0 Counter + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_ENABLE register. +// +//***************************************************************************** +#define PWM_ENABLE_PWM7EN 0x00000080 // MnPWM7 Output Enable +#define PWM_ENABLE_PWM6EN 0x00000040 // MnPWM6 Output Enable +#define PWM_ENABLE_PWM5EN 0x00000020 // MnPWM5 Output Enable +#define PWM_ENABLE_PWM4EN 0x00000010 // MnPWM4 Output Enable +#define PWM_ENABLE_PWM3EN 0x00000008 // MnPWM3 Output Enable +#define PWM_ENABLE_PWM2EN 0x00000004 // MnPWM2 Output Enable +#define PWM_ENABLE_PWM1EN 0x00000002 // MnPWM1 Output Enable +#define PWM_ENABLE_PWM0EN 0x00000001 // MnPWM0 Output Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_INVERT register. +// +//***************************************************************************** +#define PWM_INVERT_PWM7INV 0x00000080 // Invert MnPWM7 Signal +#define PWM_INVERT_PWM6INV 0x00000040 // Invert MnPWM6 Signal +#define PWM_INVERT_PWM5INV 0x00000020 // Invert MnPWM5 Signal +#define PWM_INVERT_PWM4INV 0x00000010 // Invert MnPWM4 Signal +#define PWM_INVERT_PWM3INV 0x00000008 // Invert MnPWM3 Signal +#define PWM_INVERT_PWM2INV 0x00000004 // Invert MnPWM2 Signal +#define PWM_INVERT_PWM1INV 0x00000002 // Invert MnPWM1 Signal +#define PWM_INVERT_PWM0INV 0x00000001 // Invert MnPWM0 Signal + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_FAULT register. +// +//***************************************************************************** +#define PWM_FAULT_FAULT7 0x00000080 // MnPWM7 Fault +#define PWM_FAULT_FAULT6 0x00000040 // MnPWM6 Fault +#define PWM_FAULT_FAULT5 0x00000020 // MnPWM5 Fault +#define PWM_FAULT_FAULT4 0x00000010 // MnPWM4 Fault +#define PWM_FAULT_FAULT3 0x00000008 // MnPWM3 Fault +#define PWM_FAULT_FAULT2 0x00000004 // MnPWM2 Fault +#define PWM_FAULT_FAULT1 0x00000002 // MnPWM1 Fault +#define PWM_FAULT_FAULT0 0x00000001 // MnPWM0 Fault + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_INTEN register. +// +//***************************************************************************** +#define PWM_INTEN_INTFAULT3 0x00080000 // Interrupt Fault 3 +#define PWM_INTEN_INTFAULT2 0x00040000 // Interrupt Fault 2 +#define PWM_INTEN_INTFAULT1 0x00020000 // Interrupt Fault 1 +#define PWM_INTEN_INTFAULT0 0x00010000 // Interrupt Fault 0 +#define PWM_INTEN_INTPWM3 0x00000008 // PWM3 Interrupt Enable +#define PWM_INTEN_INTPWM2 0x00000004 // PWM2 Interrupt Enable +#define PWM_INTEN_INTPWM1 0x00000002 // PWM1 Interrupt Enable +#define PWM_INTEN_INTPWM0 0x00000001 // PWM0 Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_RIS register. +// +//***************************************************************************** +#define PWM_RIS_INTFAULT3 0x00080000 // Interrupt Fault PWM 3 +#define PWM_RIS_INTFAULT2 0x00040000 // Interrupt Fault PWM 2 +#define PWM_RIS_INTFAULT1 0x00020000 // Interrupt Fault PWM 1 +#define PWM_RIS_INTFAULT0 0x00010000 // Interrupt Fault PWM 0 +#define PWM_RIS_INTPWM3 0x00000008 // PWM3 Interrupt Asserted +#define PWM_RIS_INTPWM2 0x00000004 // PWM2 Interrupt Asserted +#define PWM_RIS_INTPWM1 0x00000002 // PWM1 Interrupt Asserted +#define PWM_RIS_INTPWM0 0x00000001 // PWM0 Interrupt Asserted + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_ISC register. +// +//***************************************************************************** +#define PWM_ISC_INTFAULT3 0x00080000 // FAULT3 Interrupt Asserted +#define PWM_ISC_INTFAULT2 0x00040000 // FAULT2 Interrupt Asserted +#define PWM_ISC_INTFAULT1 0x00020000 // FAULT1 Interrupt Asserted +#define PWM_ISC_INTFAULT0 0x00010000 // FAULT0 Interrupt Asserted +#define PWM_ISC_INTPWM3 0x00000008 // PWM3 Interrupt Status +#define PWM_ISC_INTPWM2 0x00000004 // PWM2 Interrupt Status +#define PWM_ISC_INTPWM1 0x00000002 // PWM1 Interrupt Status +#define PWM_ISC_INTPWM0 0x00000001 // PWM0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_STATUS register. +// +//***************************************************************************** +#define PWM_STATUS_FAULT3 0x00000008 // Generator 3 Fault Status +#define PWM_STATUS_FAULT2 0x00000004 // Generator 2 Fault Status +#define PWM_STATUS_FAULT1 0x00000002 // Generator 1 Fault Status +#define PWM_STATUS_FAULT0 0x00000001 // Generator 0 Fault Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_FAULTVAL register. +// +//***************************************************************************** +#define PWM_FAULTVAL_PWM7 0x00000080 // MnPWM7 Fault Value +#define PWM_FAULTVAL_PWM6 0x00000040 // MnPWM6 Fault Value +#define PWM_FAULTVAL_PWM5 0x00000020 // MnPWM5 Fault Value +#define PWM_FAULTVAL_PWM4 0x00000010 // MnPWM4 Fault Value +#define PWM_FAULTVAL_PWM3 0x00000008 // MnPWM3 Fault Value +#define PWM_FAULTVAL_PWM2 0x00000004 // MnPWM2 Fault Value +#define PWM_FAULTVAL_PWM1 0x00000002 // MnPWM1 Fault Value +#define PWM_FAULTVAL_PWM0 0x00000001 // MnPWM0 Fault Value + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_ENUPD register. +// +//***************************************************************************** +#define PWM_ENUPD_ENUPD7_M 0x0000C000 // MnPWM7 Enable Update Mode +#define PWM_ENUPD_ENUPD7_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD7_LSYNC 0x00008000 // Locally Synchronized +#define PWM_ENUPD_ENUPD7_GSYNC 0x0000C000 // Globally Synchronized +#define PWM_ENUPD_ENUPD6_M 0x00003000 // MnPWM6 Enable Update Mode +#define PWM_ENUPD_ENUPD6_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD6_LSYNC 0x00002000 // Locally Synchronized +#define PWM_ENUPD_ENUPD6_GSYNC 0x00003000 // Globally Synchronized +#define PWM_ENUPD_ENUPD5_M 0x00000C00 // MnPWM5 Enable Update Mode +#define PWM_ENUPD_ENUPD5_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD5_LSYNC 0x00000800 // Locally Synchronized +#define PWM_ENUPD_ENUPD5_GSYNC 0x00000C00 // Globally Synchronized +#define PWM_ENUPD_ENUPD4_M 0x00000300 // MnPWM4 Enable Update Mode +#define PWM_ENUPD_ENUPD4_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD4_LSYNC 0x00000200 // Locally Synchronized +#define PWM_ENUPD_ENUPD4_GSYNC 0x00000300 // Globally Synchronized +#define PWM_ENUPD_ENUPD3_M 0x000000C0 // MnPWM3 Enable Update Mode +#define PWM_ENUPD_ENUPD3_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD3_LSYNC 0x00000080 // Locally Synchronized +#define PWM_ENUPD_ENUPD3_GSYNC 0x000000C0 // Globally Synchronized +#define PWM_ENUPD_ENUPD2_M 0x00000030 // MnPWM2 Enable Update Mode +#define PWM_ENUPD_ENUPD2_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD2_LSYNC 0x00000020 // Locally Synchronized +#define PWM_ENUPD_ENUPD2_GSYNC 0x00000030 // Globally Synchronized +#define PWM_ENUPD_ENUPD1_M 0x0000000C // MnPWM1 Enable Update Mode +#define PWM_ENUPD_ENUPD1_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD1_LSYNC 0x00000008 // Locally Synchronized +#define PWM_ENUPD_ENUPD1_GSYNC 0x0000000C // Globally Synchronized +#define PWM_ENUPD_ENUPD0_M 0x00000003 // MnPWM0 Enable Update Mode +#define PWM_ENUPD_ENUPD0_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD0_LSYNC 0x00000002 // Locally Synchronized +#define PWM_ENUPD_ENUPD0_GSYNC 0x00000003 // Globally Synchronized + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_CTL register. +// +//***************************************************************************** +#define PWM_0_CTL_LATCH 0x00040000 // Latch Fault Input +#define PWM_0_CTL_MINFLTPER 0x00020000 // Minimum Fault Period +#define PWM_0_CTL_FLTSRC 0x00010000 // Fault Condition Source +#define PWM_0_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode +#define PWM_0_CTL_DBFALLUPD_I 0x00000000 // Immediate +#define PWM_0_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized +#define PWM_0_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized +#define PWM_0_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode +#define PWM_0_CTL_DBRISEUPD_I 0x00000000 // Immediate +#define PWM_0_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized +#define PWM_0_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized +#define PWM_0_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode +#define PWM_0_CTL_DBCTLUPD_I 0x00000000 // Immediate +#define PWM_0_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized +#define PWM_0_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized +#define PWM_0_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode +#define PWM_0_CTL_GENBUPD_I 0x00000000 // Immediate +#define PWM_0_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized +#define PWM_0_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized +#define PWM_0_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode +#define PWM_0_CTL_GENAUPD_I 0x00000000 // Immediate +#define PWM_0_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized +#define PWM_0_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized +#define PWM_0_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode +#define PWM_0_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode +#define PWM_0_CTL_LOADUPD 0x00000008 // Load Register Update Mode +#define PWM_0_CTL_DEBUG 0x00000004 // Debug Mode +#define PWM_0_CTL_MODE 0x00000002 // Counter Mode +#define PWM_0_CTL_ENABLE 0x00000001 // PWM Block Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_INTEN register. +// +//***************************************************************************** +#define PWM_0_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB + // Down +#define PWM_0_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up +#define PWM_0_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA + // Down +#define PWM_0_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up +#define PWM_0_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD +#define PWM_0_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 +#define PWM_0_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB + // Down +#define PWM_0_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB + // Up +#define PWM_0_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA + // Down +#define PWM_0_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA + // Up +#define PWM_0_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD +#define PWM_0_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_RIS register. +// +//***************************************************************************** +#define PWM_0_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt + // Status +#define PWM_0_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status +#define PWM_0_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt + // Status +#define PWM_0_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status +#define PWM_0_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status +#define PWM_0_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_ISC register. +// +//***************************************************************************** +#define PWM_0_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt +#define PWM_0_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt +#define PWM_0_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt +#define PWM_0_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt +#define PWM_0_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt +#define PWM_0_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_LOAD register. +// +//***************************************************************************** +#define PWM_0_LOAD_M 0x0000FFFF // Counter Load Value +#define PWM_0_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_COUNT register. +// +//***************************************************************************** +#define PWM_0_COUNT_M 0x0000FFFF // Counter Value +#define PWM_0_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_CMPA register. +// +//***************************************************************************** +#define PWM_0_CMPA_M 0x0000FFFF // Comparator A Value +#define PWM_0_CMPA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_CMPB register. +// +//***************************************************************************** +#define PWM_0_CMPB_M 0x0000FFFF // Comparator B Value +#define PWM_0_CMPB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_GENA register. +// +//***************************************************************************** +#define PWM_0_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_0_GENA_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA +#define PWM_0_GENA_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmA Low +#define PWM_0_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High +#define PWM_0_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_0_GENA_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA +#define PWM_0_GENA_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmA Low +#define PWM_0_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High +#define PWM_0_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_0_GENA_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA +#define PWM_0_GENA_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmA Low +#define PWM_0_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High +#define PWM_0_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_0_GENA_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA +#define PWM_0_GENA_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmA Low +#define PWM_0_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High +#define PWM_0_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_0_GENA_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_0_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA +#define PWM_0_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low +#define PWM_0_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High +#define PWM_0_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_0_GENA_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_0_GENA_ACTZERO_INV 0x00000001 // Invert pwmA +#define PWM_0_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low +#define PWM_0_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_GENB register. +// +//***************************************************************************** +#define PWM_0_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_0_GENB_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB +#define PWM_0_GENB_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmB Low +#define PWM_0_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High +#define PWM_0_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_0_GENB_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB +#define PWM_0_GENB_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmB Low +#define PWM_0_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High +#define PWM_0_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_0_GENB_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB +#define PWM_0_GENB_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmB Low +#define PWM_0_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High +#define PWM_0_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_0_GENB_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB +#define PWM_0_GENB_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmB Low +#define PWM_0_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High +#define PWM_0_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_0_GENB_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_0_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB +#define PWM_0_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low +#define PWM_0_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High +#define PWM_0_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_0_GENB_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_0_GENB_ACTZERO_INV 0x00000001 // Invert pwmB +#define PWM_0_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low +#define PWM_0_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_DBCTL register. +// +//***************************************************************************** +#define PWM_0_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_DBRISE register. +// +//***************************************************************************** +#define PWM_0_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay +#define PWM_0_DBRISE_DELAY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_DBFALL register. +// +//***************************************************************************** +#define PWM_0_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay +#define PWM_0_DBFALL_DELAY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_FLTSRC0 +// register. +// +//***************************************************************************** +#define PWM_0_FLTSRC0_FAULT3 0x00000008 // Fault3 Input +#define PWM_0_FLTSRC0_FAULT2 0x00000004 // Fault2 Input +#define PWM_0_FLTSRC0_FAULT1 0x00000002 // Fault1 Input +#define PWM_0_FLTSRC0_FAULT0 0x00000001 // Fault0 Input + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_FLTSRC1 +// register. +// +//***************************************************************************** +#define PWM_0_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 +#define PWM_0_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 +#define PWM_0_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 +#define PWM_0_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 +#define PWM_0_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 +#define PWM_0_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 +#define PWM_0_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 +#define PWM_0_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_MINFLTPER +// register. +// +//***************************************************************************** +#define PWM_0_MINFLTPER_M 0x0000FFFF // Minimum Fault Period +#define PWM_0_MINFLTPER_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_CTL register. +// +//***************************************************************************** +#define PWM_1_CTL_LATCH 0x00040000 // Latch Fault Input +#define PWM_1_CTL_MINFLTPER 0x00020000 // Minimum Fault Period +#define PWM_1_CTL_FLTSRC 0x00010000 // Fault Condition Source +#define PWM_1_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode +#define PWM_1_CTL_DBFALLUPD_I 0x00000000 // Immediate +#define PWM_1_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized +#define PWM_1_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized +#define PWM_1_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode +#define PWM_1_CTL_DBRISEUPD_I 0x00000000 // Immediate +#define PWM_1_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized +#define PWM_1_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized +#define PWM_1_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode +#define PWM_1_CTL_DBCTLUPD_I 0x00000000 // Immediate +#define PWM_1_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized +#define PWM_1_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized +#define PWM_1_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode +#define PWM_1_CTL_GENBUPD_I 0x00000000 // Immediate +#define PWM_1_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized +#define PWM_1_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized +#define PWM_1_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode +#define PWM_1_CTL_GENAUPD_I 0x00000000 // Immediate +#define PWM_1_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized +#define PWM_1_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized +#define PWM_1_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode +#define PWM_1_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode +#define PWM_1_CTL_LOADUPD 0x00000008 // Load Register Update Mode +#define PWM_1_CTL_DEBUG 0x00000004 // Debug Mode +#define PWM_1_CTL_MODE 0x00000002 // Counter Mode +#define PWM_1_CTL_ENABLE 0x00000001 // PWM Block Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_INTEN register. +// +//***************************************************************************** +#define PWM_1_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB + // Down +#define PWM_1_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up +#define PWM_1_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA + // Down +#define PWM_1_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up +#define PWM_1_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD +#define PWM_1_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 +#define PWM_1_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB + // Down +#define PWM_1_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB + // Up +#define PWM_1_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA + // Down +#define PWM_1_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA + // Up +#define PWM_1_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD +#define PWM_1_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_RIS register. +// +//***************************************************************************** +#define PWM_1_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt + // Status +#define PWM_1_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status +#define PWM_1_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt + // Status +#define PWM_1_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status +#define PWM_1_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status +#define PWM_1_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_ISC register. +// +//***************************************************************************** +#define PWM_1_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt +#define PWM_1_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt +#define PWM_1_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt +#define PWM_1_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt +#define PWM_1_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt +#define PWM_1_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_LOAD register. +// +//***************************************************************************** +#define PWM_1_LOAD_LOAD_M 0x0000FFFF // Counter Load Value +#define PWM_1_LOAD_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_COUNT register. +// +//***************************************************************************** +#define PWM_1_COUNT_COUNT_M 0x0000FFFF // Counter Value +#define PWM_1_COUNT_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_CMPA register. +// +//***************************************************************************** +#define PWM_1_CMPA_COMPA_M 0x0000FFFF // Comparator A Value +#define PWM_1_CMPA_COMPA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_CMPB register. +// +//***************************************************************************** +#define PWM_1_CMPB_COMPB_M 0x0000FFFF // Comparator B Value +#define PWM_1_CMPB_COMPB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_GENA register. +// +//***************************************************************************** +#define PWM_1_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_1_GENA_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA +#define PWM_1_GENA_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmA Low +#define PWM_1_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High +#define PWM_1_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_1_GENA_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA +#define PWM_1_GENA_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmA Low +#define PWM_1_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High +#define PWM_1_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_1_GENA_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA +#define PWM_1_GENA_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmA Low +#define PWM_1_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High +#define PWM_1_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_1_GENA_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA +#define PWM_1_GENA_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmA Low +#define PWM_1_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High +#define PWM_1_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_1_GENA_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_1_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA +#define PWM_1_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low +#define PWM_1_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High +#define PWM_1_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_1_GENA_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_1_GENA_ACTZERO_INV 0x00000001 // Invert pwmA +#define PWM_1_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low +#define PWM_1_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_GENB register. +// +//***************************************************************************** +#define PWM_1_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_1_GENB_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB +#define PWM_1_GENB_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmB Low +#define PWM_1_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High +#define PWM_1_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_1_GENB_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB +#define PWM_1_GENB_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmB Low +#define PWM_1_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High +#define PWM_1_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_1_GENB_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB +#define PWM_1_GENB_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmB Low +#define PWM_1_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High +#define PWM_1_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_1_GENB_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB +#define PWM_1_GENB_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmB Low +#define PWM_1_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High +#define PWM_1_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_1_GENB_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_1_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB +#define PWM_1_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low +#define PWM_1_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High +#define PWM_1_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_1_GENB_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_1_GENB_ACTZERO_INV 0x00000001 // Invert pwmB +#define PWM_1_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low +#define PWM_1_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_DBCTL register. +// +//***************************************************************************** +#define PWM_1_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_DBRISE register. +// +//***************************************************************************** +#define PWM_1_DBRISE_RISEDELAY_M \ + 0x00000FFF // Dead-Band Rise Delay +#define PWM_1_DBRISE_RISEDELAY_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_DBFALL register. +// +//***************************************************************************** +#define PWM_1_DBFALL_FALLDELAY_M \ + 0x00000FFF // Dead-Band Fall Delay +#define PWM_1_DBFALL_FALLDELAY_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_FLTSRC0 +// register. +// +//***************************************************************************** +#define PWM_1_FLTSRC0_FAULT3 0x00000008 // Fault3 Input +#define PWM_1_FLTSRC0_FAULT2 0x00000004 // Fault2 Input +#define PWM_1_FLTSRC0_FAULT1 0x00000002 // Fault1 Input +#define PWM_1_FLTSRC0_FAULT0 0x00000001 // Fault0 Input + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_FLTSRC1 +// register. +// +//***************************************************************************** +#define PWM_1_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 +#define PWM_1_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 +#define PWM_1_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 +#define PWM_1_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 +#define PWM_1_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 +#define PWM_1_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 +#define PWM_1_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 +#define PWM_1_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_MINFLTPER +// register. +// +//***************************************************************************** +#define PWM_1_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period +#define PWM_1_MINFLTPER_MFP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_CTL register. +// +//***************************************************************************** +#define PWM_2_CTL_LATCH 0x00040000 // Latch Fault Input +#define PWM_2_CTL_MINFLTPER 0x00020000 // Minimum Fault Period +#define PWM_2_CTL_FLTSRC 0x00010000 // Fault Condition Source +#define PWM_2_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode +#define PWM_2_CTL_DBFALLUPD_I 0x00000000 // Immediate +#define PWM_2_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized +#define PWM_2_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized +#define PWM_2_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode +#define PWM_2_CTL_DBRISEUPD_I 0x00000000 // Immediate +#define PWM_2_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized +#define PWM_2_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized +#define PWM_2_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode +#define PWM_2_CTL_DBCTLUPD_I 0x00000000 // Immediate +#define PWM_2_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized +#define PWM_2_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized +#define PWM_2_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode +#define PWM_2_CTL_GENBUPD_I 0x00000000 // Immediate +#define PWM_2_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized +#define PWM_2_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized +#define PWM_2_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode +#define PWM_2_CTL_GENAUPD_I 0x00000000 // Immediate +#define PWM_2_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized +#define PWM_2_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized +#define PWM_2_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode +#define PWM_2_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode +#define PWM_2_CTL_LOADUPD 0x00000008 // Load Register Update Mode +#define PWM_2_CTL_DEBUG 0x00000004 // Debug Mode +#define PWM_2_CTL_MODE 0x00000002 // Counter Mode +#define PWM_2_CTL_ENABLE 0x00000001 // PWM Block Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_INTEN register. +// +//***************************************************************************** +#define PWM_2_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB + // Down +#define PWM_2_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up +#define PWM_2_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA + // Down +#define PWM_2_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up +#define PWM_2_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD +#define PWM_2_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 +#define PWM_2_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB + // Down +#define PWM_2_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB + // Up +#define PWM_2_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA + // Down +#define PWM_2_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA + // Up +#define PWM_2_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD +#define PWM_2_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_RIS register. +// +//***************************************************************************** +#define PWM_2_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt + // Status +#define PWM_2_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status +#define PWM_2_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt + // Status +#define PWM_2_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status +#define PWM_2_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status +#define PWM_2_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_ISC register. +// +//***************************************************************************** +#define PWM_2_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt +#define PWM_2_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt +#define PWM_2_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt +#define PWM_2_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt +#define PWM_2_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt +#define PWM_2_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_LOAD register. +// +//***************************************************************************** +#define PWM_2_LOAD_LOAD_M 0x0000FFFF // Counter Load Value +#define PWM_2_LOAD_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_COUNT register. +// +//***************************************************************************** +#define PWM_2_COUNT_COUNT_M 0x0000FFFF // Counter Value +#define PWM_2_COUNT_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_CMPA register. +// +//***************************************************************************** +#define PWM_2_CMPA_COMPA_M 0x0000FFFF // Comparator A Value +#define PWM_2_CMPA_COMPA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_CMPB register. +// +//***************************************************************************** +#define PWM_2_CMPB_COMPB_M 0x0000FFFF // Comparator B Value +#define PWM_2_CMPB_COMPB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_GENA register. +// +//***************************************************************************** +#define PWM_2_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_2_GENA_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA +#define PWM_2_GENA_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmA Low +#define PWM_2_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High +#define PWM_2_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_2_GENA_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA +#define PWM_2_GENA_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmA Low +#define PWM_2_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High +#define PWM_2_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_2_GENA_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA +#define PWM_2_GENA_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmA Low +#define PWM_2_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High +#define PWM_2_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_2_GENA_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA +#define PWM_2_GENA_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmA Low +#define PWM_2_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High +#define PWM_2_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_2_GENA_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_2_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA +#define PWM_2_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low +#define PWM_2_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High +#define PWM_2_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_2_GENA_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_2_GENA_ACTZERO_INV 0x00000001 // Invert pwmA +#define PWM_2_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low +#define PWM_2_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_GENB register. +// +//***************************************************************************** +#define PWM_2_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_2_GENB_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB +#define PWM_2_GENB_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmB Low +#define PWM_2_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High +#define PWM_2_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_2_GENB_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB +#define PWM_2_GENB_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmB Low +#define PWM_2_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High +#define PWM_2_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_2_GENB_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB +#define PWM_2_GENB_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmB Low +#define PWM_2_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High +#define PWM_2_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_2_GENB_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB +#define PWM_2_GENB_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmB Low +#define PWM_2_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High +#define PWM_2_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_2_GENB_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_2_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB +#define PWM_2_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low +#define PWM_2_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High +#define PWM_2_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_2_GENB_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_2_GENB_ACTZERO_INV 0x00000001 // Invert pwmB +#define PWM_2_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low +#define PWM_2_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_DBCTL register. +// +//***************************************************************************** +#define PWM_2_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_DBRISE register. +// +//***************************************************************************** +#define PWM_2_DBRISE_RISEDELAY_M \ + 0x00000FFF // Dead-Band Rise Delay +#define PWM_2_DBRISE_RISEDELAY_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_DBFALL register. +// +//***************************************************************************** +#define PWM_2_DBFALL_FALLDELAY_M \ + 0x00000FFF // Dead-Band Fall Delay +#define PWM_2_DBFALL_FALLDELAY_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_FLTSRC0 +// register. +// +//***************************************************************************** +#define PWM_2_FLTSRC0_FAULT3 0x00000008 // Fault3 Input +#define PWM_2_FLTSRC0_FAULT2 0x00000004 // Fault2 Input +#define PWM_2_FLTSRC0_FAULT1 0x00000002 // Fault1 Input +#define PWM_2_FLTSRC0_FAULT0 0x00000001 // Fault0 Input + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_FLTSRC1 +// register. +// +//***************************************************************************** +#define PWM_2_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 +#define PWM_2_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 +#define PWM_2_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 +#define PWM_2_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 +#define PWM_2_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 +#define PWM_2_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 +#define PWM_2_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 +#define PWM_2_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_MINFLTPER +// register. +// +//***************************************************************************** +#define PWM_2_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period +#define PWM_2_MINFLTPER_MFP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_CTL register. +// +//***************************************************************************** +#define PWM_3_CTL_LATCH 0x00040000 // Latch Fault Input +#define PWM_3_CTL_MINFLTPER 0x00020000 // Minimum Fault Period +#define PWM_3_CTL_FLTSRC 0x00010000 // Fault Condition Source +#define PWM_3_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode +#define PWM_3_CTL_DBFALLUPD_I 0x00000000 // Immediate +#define PWM_3_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized +#define PWM_3_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized +#define PWM_3_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode +#define PWM_3_CTL_DBRISEUPD_I 0x00000000 // Immediate +#define PWM_3_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized +#define PWM_3_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized +#define PWM_3_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode +#define PWM_3_CTL_DBCTLUPD_I 0x00000000 // Immediate +#define PWM_3_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized +#define PWM_3_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized +#define PWM_3_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode +#define PWM_3_CTL_GENBUPD_I 0x00000000 // Immediate +#define PWM_3_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized +#define PWM_3_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized +#define PWM_3_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode +#define PWM_3_CTL_GENAUPD_I 0x00000000 // Immediate +#define PWM_3_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized +#define PWM_3_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized +#define PWM_3_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode +#define PWM_3_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode +#define PWM_3_CTL_LOADUPD 0x00000008 // Load Register Update Mode +#define PWM_3_CTL_DEBUG 0x00000004 // Debug Mode +#define PWM_3_CTL_MODE 0x00000002 // Counter Mode +#define PWM_3_CTL_ENABLE 0x00000001 // PWM Block Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_INTEN register. +// +//***************************************************************************** +#define PWM_3_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB + // Down +#define PWM_3_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up +#define PWM_3_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA + // Down +#define PWM_3_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up +#define PWM_3_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD +#define PWM_3_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 +#define PWM_3_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB + // Down +#define PWM_3_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB + // Up +#define PWM_3_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA + // Down +#define PWM_3_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA + // Up +#define PWM_3_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD +#define PWM_3_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_RIS register. +// +//***************************************************************************** +#define PWM_3_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt + // Status +#define PWM_3_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status +#define PWM_3_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt + // Status +#define PWM_3_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status +#define PWM_3_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status +#define PWM_3_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_ISC register. +// +//***************************************************************************** +#define PWM_3_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt +#define PWM_3_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt +#define PWM_3_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt +#define PWM_3_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt +#define PWM_3_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt +#define PWM_3_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_LOAD register. +// +//***************************************************************************** +#define PWM_3_LOAD_LOAD_M 0x0000FFFF // Counter Load Value +#define PWM_3_LOAD_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_COUNT register. +// +//***************************************************************************** +#define PWM_3_COUNT_COUNT_M 0x0000FFFF // Counter Value +#define PWM_3_COUNT_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_CMPA register. +// +//***************************************************************************** +#define PWM_3_CMPA_COMPA_M 0x0000FFFF // Comparator A Value +#define PWM_3_CMPA_COMPA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_CMPB register. +// +//***************************************************************************** +#define PWM_3_CMPB_COMPB_M 0x0000FFFF // Comparator B Value +#define PWM_3_CMPB_COMPB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_GENA register. +// +//***************************************************************************** +#define PWM_3_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_3_GENA_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA +#define PWM_3_GENA_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmA Low +#define PWM_3_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High +#define PWM_3_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_3_GENA_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA +#define PWM_3_GENA_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmA Low +#define PWM_3_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High +#define PWM_3_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_3_GENA_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA +#define PWM_3_GENA_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmA Low +#define PWM_3_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High +#define PWM_3_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_3_GENA_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA +#define PWM_3_GENA_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmA Low +#define PWM_3_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High +#define PWM_3_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_3_GENA_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_3_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA +#define PWM_3_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low +#define PWM_3_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High +#define PWM_3_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_3_GENA_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_3_GENA_ACTZERO_INV 0x00000001 // Invert pwmA +#define PWM_3_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low +#define PWM_3_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_GENB register. +// +//***************************************************************************** +#define PWM_3_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_3_GENB_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB +#define PWM_3_GENB_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmB Low +#define PWM_3_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High +#define PWM_3_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_3_GENB_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB +#define PWM_3_GENB_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmB Low +#define PWM_3_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High +#define PWM_3_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_3_GENB_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB +#define PWM_3_GENB_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmB Low +#define PWM_3_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High +#define PWM_3_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_3_GENB_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB +#define PWM_3_GENB_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmB Low +#define PWM_3_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High +#define PWM_3_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_3_GENB_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_3_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB +#define PWM_3_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low +#define PWM_3_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High +#define PWM_3_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_3_GENB_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_3_GENB_ACTZERO_INV 0x00000001 // Invert pwmB +#define PWM_3_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low +#define PWM_3_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_DBCTL register. +// +//***************************************************************************** +#define PWM_3_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_DBRISE register. +// +//***************************************************************************** +#define PWM_3_DBRISE_RISEDELAY_M \ + 0x00000FFF // Dead-Band Rise Delay +#define PWM_3_DBRISE_RISEDELAY_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_DBFALL register. +// +//***************************************************************************** +#define PWM_3_DBFALL_FALLDELAY_M \ + 0x00000FFF // Dead-Band Fall Delay +#define PWM_3_DBFALL_FALLDELAY_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_FLTSRC0 +// register. +// +//***************************************************************************** +#define PWM_3_FLTSRC0_FAULT3 0x00000008 // Fault3 Input +#define PWM_3_FLTSRC0_FAULT2 0x00000004 // Fault2 Input +#define PWM_3_FLTSRC0_FAULT1 0x00000002 // Fault1 Input +#define PWM_3_FLTSRC0_FAULT0 0x00000001 // Fault0 Input + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_FLTSRC1 +// register. +// +//***************************************************************************** +#define PWM_3_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 +#define PWM_3_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 +#define PWM_3_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 +#define PWM_3_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 +#define PWM_3_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 +#define PWM_3_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 +#define PWM_3_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 +#define PWM_3_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_MINFLTPER +// register. +// +//***************************************************************************** +#define PWM_3_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period +#define PWM_3_MINFLTPER_MFP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_FLTSEN register. +// +//***************************************************************************** +#define PWM_0_FLTSEN_FAULT3 0x00000008 // Fault3 Sense +#define PWM_0_FLTSEN_FAULT2 0x00000004 // Fault2 Sense +#define PWM_0_FLTSEN_FAULT1 0x00000002 // Fault1 Sense +#define PWM_0_FLTSEN_FAULT0 0x00000001 // Fault0 Sense + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_FLTSTAT0 +// register. +// +//***************************************************************************** +#define PWM_0_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 +#define PWM_0_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 +#define PWM_0_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 +#define PWM_0_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_FLTSTAT1 +// register. +// +//***************************************************************************** +#define PWM_0_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger +#define PWM_0_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger +#define PWM_0_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger +#define PWM_0_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger +#define PWM_0_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger +#define PWM_0_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger +#define PWM_0_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger +#define PWM_0_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_FLTSEN register. +// +//***************************************************************************** +#define PWM_1_FLTSEN_FAULT3 0x00000008 // Fault3 Sense +#define PWM_1_FLTSEN_FAULT2 0x00000004 // Fault2 Sense +#define PWM_1_FLTSEN_FAULT1 0x00000002 // Fault1 Sense +#define PWM_1_FLTSEN_FAULT0 0x00000001 // Fault0 Sense + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_FLTSTAT0 +// register. +// +//***************************************************************************** +#define PWM_1_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 +#define PWM_1_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 +#define PWM_1_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 +#define PWM_1_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_FLTSTAT1 +// register. +// +//***************************************************************************** +#define PWM_1_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger +#define PWM_1_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger +#define PWM_1_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger +#define PWM_1_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger +#define PWM_1_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger +#define PWM_1_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger +#define PWM_1_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger +#define PWM_1_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_FLTSEN register. +// +//***************************************************************************** +#define PWM_2_FLTSEN_FAULT3 0x00000008 // Fault3 Sense +#define PWM_2_FLTSEN_FAULT2 0x00000004 // Fault2 Sense +#define PWM_2_FLTSEN_FAULT1 0x00000002 // Fault1 Sense +#define PWM_2_FLTSEN_FAULT0 0x00000001 // Fault0 Sense + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_FLTSTAT0 +// register. +// +//***************************************************************************** +#define PWM_2_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 +#define PWM_2_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 +#define PWM_2_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 +#define PWM_2_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_FLTSTAT1 +// register. +// +//***************************************************************************** +#define PWM_2_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger +#define PWM_2_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger +#define PWM_2_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger +#define PWM_2_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger +#define PWM_2_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger +#define PWM_2_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger +#define PWM_2_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger +#define PWM_2_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_FLTSEN register. +// +//***************************************************************************** +#define PWM_3_FLTSEN_FAULT3 0x00000008 // Fault3 Sense +#define PWM_3_FLTSEN_FAULT2 0x00000004 // Fault2 Sense +#define PWM_3_FLTSEN_FAULT1 0x00000002 // Fault1 Sense +#define PWM_3_FLTSEN_FAULT0 0x00000001 // Fault0 Sense + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_FLTSTAT0 +// register. +// +//***************************************************************************** +#define PWM_3_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 +#define PWM_3_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 +#define PWM_3_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 +#define PWM_3_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_FLTSTAT1 +// register. +// +//***************************************************************************** +#define PWM_3_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger +#define PWM_3_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger +#define PWM_3_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger +#define PWM_3_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger +#define PWM_3_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger +#define PWM_3_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger +#define PWM_3_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger +#define PWM_3_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_PP register. +// +//***************************************************************************** +#define PWM_PP_GCNT_M 0x0000000F // Generators +#define PWM_PP_FCNT_M 0x000000F0 // Fault Inputs (per PWM unit) +#define PWM_PP_ESYNC 0x00000100 // Extended Synchronization +#define PWM_PP_EFAULT 0x00000200 // Extended Fault +#define PWM_PP_ONE 0x00000400 // One-Shot Mode +#define PWM_PP_GCNT_S 0 +#define PWM_PP_FCNT_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_CC register. +// +//***************************************************************************** +#define PWM_CC_USEPWM 0x00000100 // Use PWM Clock Divisor +#define PWM_CC_PWMDIV_M 0x00000007 // PWM Clock Divider +#define PWM_CC_PWMDIV_2 0x00000000 // /2 +#define PWM_CC_PWMDIV_4 0x00000001 // /4 +#define PWM_CC_PWMDIV_8 0x00000002 // /8 +#define PWM_CC_PWMDIV_16 0x00000003 // /16 +#define PWM_CC_PWMDIV_32 0x00000004 // /32 +#define PWM_CC_PWMDIV_64 0x00000005 // /64 + +//***************************************************************************** +// +// The following are defines for the PWM Generator standard offsets. +// +//***************************************************************************** +#define PWM_O_X_CTL 0x00000000 // Gen Control Reg +#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg +#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg +#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg +#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg +#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg +#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg +#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg +#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg +#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg +#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg +#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg +#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg +#define PWM_O_X_FLTSRC0 0x00000034 // Fault pin, comparator condition +#define PWM_O_X_FLTSRC1 0x00000038 // Digital comparator condition +#define PWM_O_X_MINFLTPER 0x0000003C // Fault minimum period extension +#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base +#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base +#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base +#define PWM_GEN_3_OFFSET 0x00000100 // PWM3 base + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_CTL register. +// +//***************************************************************************** +#define PWM_X_CTL_LATCH 0x00040000 // Latch Fault Input +#define PWM_X_CTL_MINFLTPER 0x00020000 // Minimum Fault Period +#define PWM_X_CTL_FLTSRC 0x00010000 // Fault Condition Source +#define PWM_X_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode +#define PWM_X_CTL_DBFALLUPD_I 0x00000000 // Immediate +#define PWM_X_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized +#define PWM_X_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized +#define PWM_X_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode +#define PWM_X_CTL_DBRISEUPD_I 0x00000000 // Immediate +#define PWM_X_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized +#define PWM_X_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized +#define PWM_X_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode +#define PWM_X_CTL_DBCTLUPD_I 0x00000000 // Immediate +#define PWM_X_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized +#define PWM_X_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized +#define PWM_X_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode +#define PWM_X_CTL_GENBUPD_I 0x00000000 // Immediate +#define PWM_X_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized +#define PWM_X_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized +#define PWM_X_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode +#define PWM_X_CTL_GENAUPD_I 0x00000000 // Immediate +#define PWM_X_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized +#define PWM_X_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized +#define PWM_X_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode +#define PWM_X_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode +#define PWM_X_CTL_LOADUPD 0x00000008 // Load Register Update Mode +#define PWM_X_CTL_DEBUG 0x00000004 // Debug Mode +#define PWM_X_CTL_MODE 0x00000002 // Counter Mode +#define PWM_X_CTL_ENABLE 0x00000001 // PWM Block Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_INTEN register. +// +//***************************************************************************** +#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB + // Down +#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up +#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA + // Down +#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up +#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD +#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 +#define PWM_X_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB + // Down +#define PWM_X_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB + // Up +#define PWM_X_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA + // Down +#define PWM_X_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA + // Up +#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD +#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_RIS register. +// +//***************************************************************************** +#define PWM_X_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt + // Status +#define PWM_X_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status +#define PWM_X_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt + // Status +#define PWM_X_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status +#define PWM_X_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status +#define PWM_X_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_ISC register. +// +//***************************************************************************** +#define PWM_X_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt +#define PWM_X_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt +#define PWM_X_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt +#define PWM_X_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt +#define PWM_X_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt +#define PWM_X_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_LOAD register. +// +//***************************************************************************** +#define PWM_X_LOAD_M 0x0000FFFF // Counter Load Value +#define PWM_X_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_COUNT register. +// +//***************************************************************************** +#define PWM_X_COUNT_M 0x0000FFFF // Counter Value +#define PWM_X_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_CMPA register. +// +//***************************************************************************** +#define PWM_X_CMPA_M 0x0000FFFF // Comparator A Value +#define PWM_X_CMPA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_CMPB register. +// +//***************************************************************************** +#define PWM_X_CMPB_M 0x0000FFFF // Comparator B Value +#define PWM_X_CMPB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_GENA register. +// +//***************************************************************************** +#define PWM_X_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_X_GENA_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_X_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA +#define PWM_X_GENA_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmA Low +#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High +#define PWM_X_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_X_GENA_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_X_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA +#define PWM_X_GENA_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmA Low +#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High +#define PWM_X_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_X_GENA_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_X_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA +#define PWM_X_GENA_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmA Low +#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High +#define PWM_X_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_X_GENA_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_X_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA +#define PWM_X_GENA_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmA Low +#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High +#define PWM_X_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_X_GENA_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_X_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA +#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low +#define PWM_X_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High +#define PWM_X_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_X_GENA_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_X_GENA_ACTZERO_INV 0x00000001 // Invert pwmA +#define PWM_X_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low +#define PWM_X_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_GENB register. +// +//***************************************************************************** +#define PWM_X_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_X_GENB_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_X_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB +#define PWM_X_GENB_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmB Low +#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High +#define PWM_X_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_X_GENB_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_X_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB +#define PWM_X_GENB_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmB Low +#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High +#define PWM_X_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_X_GENB_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_X_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB +#define PWM_X_GENB_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmB Low +#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High +#define PWM_X_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_X_GENB_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_X_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB +#define PWM_X_GENB_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmB Low +#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High +#define PWM_X_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_X_GENB_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_X_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB +#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low +#define PWM_X_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High +#define PWM_X_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_X_GENB_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_X_GENB_ACTZERO_INV 0x00000001 // Invert pwmB +#define PWM_X_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low +#define PWM_X_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_DBCTL register. +// +//***************************************************************************** +#define PWM_X_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_DBRISE register. +// +//***************************************************************************** +#define PWM_X_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay +#define PWM_X_DBRISE_DELAY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_DBFALL register. +// +//***************************************************************************** +#define PWM_X_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay +#define PWM_X_DBFALL_DELAY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_FLTSRC0 +// register. +// +//***************************************************************************** +#define PWM_X_FLTSRC0_FAULT3 0x00000008 // Fault3 Input +#define PWM_X_FLTSRC0_FAULT2 0x00000004 // Fault2 Input +#define PWM_X_FLTSRC0_FAULT1 0x00000002 // Fault1 Input +#define PWM_X_FLTSRC0_FAULT0 0x00000001 // Fault0 Input + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_FLTSRC1 +// register. +// +//***************************************************************************** +#define PWM_X_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 +#define PWM_X_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 +#define PWM_X_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 +#define PWM_X_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 +#define PWM_X_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 +#define PWM_X_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 +#define PWM_X_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 +#define PWM_X_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_MINFLTPER +// register. +// +//***************************************************************************** +#define PWM_X_MINFLTPER_M 0x0000FFFF // Minimum Fault Period +#define PWM_X_MINFLTPER_S 0 + +//***************************************************************************** +// +// The following are defines for the PWM Generator extended offsets. +// +//***************************************************************************** +#define PWM_O_X_FLTSEN 0x00000000 // Fault logic sense +#define PWM_O_X_FLTSTAT0 0x00000004 // Pin and comparator status +#define PWM_O_X_FLTSTAT1 0x00000008 // Digital comparator status +#define PWM_EXT_0_OFFSET 0x00000800 // PWM0 extended base +#define PWM_EXT_1_OFFSET 0x00000880 // PWM1 extended base +#define PWM_EXT_2_OFFSET 0x00000900 // PWM2 extended base +#define PWM_EXT_3_OFFSET 0x00000980 // PWM3 extended base + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_FLTSEN register. +// +//***************************************************************************** +#define PWM_X_FLTSEN_FAULT3 0x00000008 // Fault3 Sense +#define PWM_X_FLTSEN_FAULT2 0x00000004 // Fault2 Sense +#define PWM_X_FLTSEN_FAULT1 0x00000002 // Fault1 Sense +#define PWM_X_FLTSEN_FAULT0 0x00000001 // Fault0 Sense + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_FLTSTAT0 +// register. +// +//***************************************************************************** +#define PWM_X_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 +#define PWM_X_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 +#define PWM_X_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 +#define PWM_X_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_FLTSTAT1 +// register. +// +//***************************************************************************** +#define PWM_X_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger +#define PWM_X_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger +#define PWM_X_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger +#define PWM_X_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger +#define PWM_X_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger +#define PWM_X_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger +#define PWM_X_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger +#define PWM_X_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger + +#endif // __HW_PWM_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_qei.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_qei.h new file mode 100644 index 0000000000000000000000000000000000000000..a86f5259bddbdeb2a9915b15d01c5041f87fc900 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_qei.h @@ -0,0 +1,178 @@ +//***************************************************************************** +// +// hw_qei.h - Macros used when accessing the QEI hardware. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_QEI_H__ +#define __HW_QEI_H__ + +//***************************************************************************** +// +// The following are defines for the QEI register offsets. +// +//***************************************************************************** +#define QEI_O_CTL 0x00000000 // QEI Control +#define QEI_O_STAT 0x00000004 // QEI Status +#define QEI_O_POS 0x00000008 // QEI Position +#define QEI_O_MAXPOS 0x0000000C // QEI Maximum Position +#define QEI_O_LOAD 0x00000010 // QEI Timer Load +#define QEI_O_TIME 0x00000014 // QEI Timer +#define QEI_O_COUNT 0x00000018 // QEI Velocity Counter +#define QEI_O_SPEED 0x0000001C // QEI Velocity +#define QEI_O_INTEN 0x00000020 // QEI Interrupt Enable +#define QEI_O_RIS 0x00000024 // QEI Raw Interrupt Status +#define QEI_O_ISC 0x00000028 // QEI Interrupt Status and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_CTL register. +// +//***************************************************************************** +#define QEI_CTL_FILTCNT_M 0x000F0000 // Input Filter Prescale Count +#define QEI_CTL_FILTEN 0x00002000 // Enable Input Filter +#define QEI_CTL_STALLEN 0x00001000 // Stall QEI +#define QEI_CTL_INVI 0x00000800 // Invert Index Pulse +#define QEI_CTL_INVB 0x00000400 // Invert PhB +#define QEI_CTL_INVA 0x00000200 // Invert PhA +#define QEI_CTL_VELDIV_M 0x000001C0 // Predivide Velocity +#define QEI_CTL_VELDIV_1 0x00000000 // QEI clock /1 +#define QEI_CTL_VELDIV_2 0x00000040 // QEI clock /2 +#define QEI_CTL_VELDIV_4 0x00000080 // QEI clock /4 +#define QEI_CTL_VELDIV_8 0x000000C0 // QEI clock /8 +#define QEI_CTL_VELDIV_16 0x00000100 // QEI clock /16 +#define QEI_CTL_VELDIV_32 0x00000140 // QEI clock /32 +#define QEI_CTL_VELDIV_64 0x00000180 // QEI clock /64 +#define QEI_CTL_VELDIV_128 0x000001C0 // QEI clock /128 +#define QEI_CTL_VELEN 0x00000020 // Capture Velocity +#define QEI_CTL_RESMODE 0x00000010 // Reset Mode +#define QEI_CTL_CAPMODE 0x00000008 // Capture Mode +#define QEI_CTL_SIGMODE 0x00000004 // Signal Mode +#define QEI_CTL_SWAP 0x00000002 // Swap Signals +#define QEI_CTL_ENABLE 0x00000001 // Enable QEI +#define QEI_CTL_FILTCNT_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_STAT register. +// +//***************************************************************************** +#define QEI_STAT_DIRECTION 0x00000002 // Direction of Rotation +#define QEI_STAT_ERROR 0x00000001 // Error Detected + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_POS register. +// +//***************************************************************************** +#define QEI_POS_M 0xFFFFFFFF // Current Position Integrator + // Value +#define QEI_POS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_MAXPOS register. +// +//***************************************************************************** +#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum Position Integrator + // Value +#define QEI_MAXPOS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_LOAD register. +// +//***************************************************************************** +#define QEI_LOAD_M 0xFFFFFFFF // Velocity Timer Load Value +#define QEI_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_TIME register. +// +//***************************************************************************** +#define QEI_TIME_M 0xFFFFFFFF // Velocity Timer Current Value +#define QEI_TIME_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_COUNT register. +// +//***************************************************************************** +#define QEI_COUNT_M 0xFFFFFFFF // Velocity Pulse Count +#define QEI_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_SPEED register. +// +//***************************************************************************** +#define QEI_SPEED_M 0xFFFFFFFF // Velocity +#define QEI_SPEED_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_INTEN register. +// +//***************************************************************************** +#define QEI_INTEN_ERROR 0x00000008 // Phase Error Interrupt Enable +#define QEI_INTEN_DIR 0x00000004 // Direction Change Interrupt + // Enable +#define QEI_INTEN_TIMER 0x00000002 // Timer Expires Interrupt Enable +#define QEI_INTEN_INDEX 0x00000001 // Index Pulse Detected Interrupt + // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_RIS register. +// +//***************************************************************************** +#define QEI_RIS_ERROR 0x00000008 // Phase Error Detected +#define QEI_RIS_DIR 0x00000004 // Direction Change Detected +#define QEI_RIS_TIMER 0x00000002 // Velocity Timer Expired +#define QEI_RIS_INDEX 0x00000001 // Index Pulse Asserted + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_ISC register. +// +//***************************************************************************** +#define QEI_ISC_ERROR 0x00000008 // Phase Error Interrupt +#define QEI_ISC_DIR 0x00000004 // Direction Change Interrupt +#define QEI_ISC_TIMER 0x00000002 // Velocity Timer Expired Interrupt +#define QEI_ISC_INDEX 0x00000001 // Index Pulse Interrupt + +#endif // __HW_QEI_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_shamd5.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_shamd5.h new file mode 100644 index 0000000000000000000000000000000000000000..d34c76092cf6aeef80dedb29f5930e3744a20460 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_shamd5.h @@ -0,0 +1,548 @@ +//***************************************************************************** +// +// hw_shamd5.h - Macros used when accessing the SHA/MD5 hardware. +// +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_SHAMD5_H__ +#define __HW_SHAMD5_H__ + +//***************************************************************************** +// +// The following are defines for the SHA/MD5 register offsets. +// +//***************************************************************************** +#define SHAMD5_O_ODIGEST_A 0x00000000 // SHA Outer Digest A +#define SHAMD5_O_ODIGEST_B 0x00000004 // SHA Outer Digest B +#define SHAMD5_O_ODIGEST_C 0x00000008 // SHA Outer Digest C +#define SHAMD5_O_ODIGEST_D 0x0000000C // SHA Outer Digest D +#define SHAMD5_O_ODIGEST_E 0x00000010 // SHA Outer Digest E +#define SHAMD5_O_ODIGEST_F 0x00000014 // SHA Outer Digest F +#define SHAMD5_O_ODIGEST_G 0x00000018 // SHA Outer Digest G +#define SHAMD5_O_ODIGEST_H 0x0000001C // SHA Outer Digest H +#define SHAMD5_O_IDIGEST_A 0x00000020 // SHA Inner Digest A +#define SHAMD5_O_IDIGEST_B 0x00000024 // SHA Inner Digest B +#define SHAMD5_O_IDIGEST_C 0x00000028 // SHA Inner Digest C +#define SHAMD5_O_IDIGEST_D 0x0000002C // SHA Inner Digest D +#define SHAMD5_O_IDIGEST_E 0x00000030 // SHA Inner Digest E +#define SHAMD5_O_IDIGEST_F 0x00000034 // SHA Inner Digest F +#define SHAMD5_O_IDIGEST_G 0x00000038 // SHA Inner Digest G +#define SHAMD5_O_IDIGEST_H 0x0000003C // SHA Inner Digest H +#define SHAMD5_O_DIGEST_COUNT 0x00000040 // SHA Digest Count +#define SHAMD5_O_MODE 0x00000044 // SHA Mode +#define SHAMD5_O_LENGTH 0x00000048 // SHA Length +#define SHAMD5_O_DATA_0_IN 0x00000080 // SHA Data 0 Input +#define SHAMD5_O_DATA_1_IN 0x00000084 // SHA Data 1 Input +#define SHAMD5_O_DATA_2_IN 0x00000088 // SHA Data 2 Input +#define SHAMD5_O_DATA_3_IN 0x0000008C // SHA Data 3 Input +#define SHAMD5_O_DATA_4_IN 0x00000090 // SHA Data 4 Input +#define SHAMD5_O_DATA_5_IN 0x00000094 // SHA Data 5 Input +#define SHAMD5_O_DATA_6_IN 0x00000098 // SHA Data 6 Input +#define SHAMD5_O_DATA_7_IN 0x0000009C // SHA Data 7 Input +#define SHAMD5_O_DATA_8_IN 0x000000A0 // SHA Data 8 Input +#define SHAMD5_O_DATA_9_IN 0x000000A4 // SHA Data 9 Input +#define SHAMD5_O_DATA_10_IN 0x000000A8 // SHA Data 10 Input +#define SHAMD5_O_DATA_11_IN 0x000000AC // SHA Data 11 Input +#define SHAMD5_O_DATA_12_IN 0x000000B0 // SHA Data 12 Input +#define SHAMD5_O_DATA_13_IN 0x000000B4 // SHA Data 13 Input +#define SHAMD5_O_DATA_14_IN 0x000000B8 // SHA Data 14 Input +#define SHAMD5_O_DATA_15_IN 0x000000BC // SHA Data 15 Input +#define SHAMD5_O_REVISION 0x00000100 // SHA Revision +#define SHAMD5_O_SYSCONFIG 0x00000110 // SHA System Configuration +#define SHAMD5_O_SYSSTATUS 0x00000114 // SHA System Status +#define SHAMD5_O_IRQSTATUS 0x00000118 // SHA Interrupt Status +#define SHAMD5_O_IRQENABLE 0x0000011C // SHA Interrupt Enable +#define SHAMD5_O_DMAIM 0xFFFFC010 // SHA DMA Interrupt Mask +#define SHAMD5_O_DMARIS 0xFFFFC014 // SHA DMA Raw Interrupt Status +#define SHAMD5_O_DMAMIS 0xFFFFC018 // SHA DMA Masked Interrupt Status +#define SHAMD5_O_DMAIC 0xFFFFC01C // SHA DMA Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_A +// register. +// +//***************************************************************************** +#define SHAMD5_ODIGEST_A_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_ODIGEST_A_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_B +// register. +// +//***************************************************************************** +#define SHAMD5_ODIGEST_B_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_ODIGEST_B_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_C +// register. +// +//***************************************************************************** +#define SHAMD5_ODIGEST_C_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_ODIGEST_C_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_D +// register. +// +//***************************************************************************** +#define SHAMD5_ODIGEST_D_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_ODIGEST_D_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_E +// register. +// +//***************************************************************************** +#define SHAMD5_ODIGEST_E_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_ODIGEST_E_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_F +// register. +// +//***************************************************************************** +#define SHAMD5_ODIGEST_F_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_ODIGEST_F_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_G +// register. +// +//***************************************************************************** +#define SHAMD5_ODIGEST_G_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_ODIGEST_G_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_H +// register. +// +//***************************************************************************** +#define SHAMD5_ODIGEST_H_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_ODIGEST_H_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_A +// register. +// +//***************************************************************************** +#define SHAMD5_IDIGEST_A_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_IDIGEST_A_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_B +// register. +// +//***************************************************************************** +#define SHAMD5_IDIGEST_B_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_IDIGEST_B_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_C +// register. +// +//***************************************************************************** +#define SHAMD5_IDIGEST_C_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_IDIGEST_C_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_D +// register. +// +//***************************************************************************** +#define SHAMD5_IDIGEST_D_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_IDIGEST_D_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_E +// register. +// +//***************************************************************************** +#define SHAMD5_IDIGEST_E_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_IDIGEST_E_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_F +// register. +// +//***************************************************************************** +#define SHAMD5_IDIGEST_F_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_IDIGEST_F_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_G +// register. +// +//***************************************************************************** +#define SHAMD5_IDIGEST_G_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_IDIGEST_G_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_H +// register. +// +//***************************************************************************** +#define SHAMD5_IDIGEST_H_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_IDIGEST_H_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DIGEST_COUNT +// register. +// +//***************************************************************************** +#define SHAMD5_DIGEST_COUNT_M 0xFFFFFFFF // Digest Count +#define SHAMD5_DIGEST_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_MODE register. +// +//***************************************************************************** +#define SHAMD5_MODE_HMAC_OUTER_HASH \ + 0x00000080 // HMAC Outer Hash Processing + // Enable +#define SHAMD5_MODE_HMAC_KEY_PROC \ + 0x00000020 // HMAC Key Processing Enable +#define SHAMD5_MODE_CLOSE_HASH 0x00000010 // Performs the padding, the + // Hash/HMAC will be 'closed' at + // the end of the block, as per + // MD5/SHA-1/SHA-2 specification +#define SHAMD5_MODE_ALGO_CONSTANT \ + 0x00000008 // The initial digest register will + // be overwritten with the + // algorithm constants for the + // selected algorithm when hashing + // and the initial digest count + // register will be reset to 0 +#define SHAMD5_MODE_ALGO_M 0x00000007 // Hash Algorithm +#define SHAMD5_MODE_ALGO_MD5 0x00000000 // MD5 +#define SHAMD5_MODE_ALGO_SHA1 0x00000002 // SHA-1 +#define SHAMD5_MODE_ALGO_SHA224 0x00000004 // SHA-224 +#define SHAMD5_MODE_ALGO_SHA256 0x00000006 // SHA-256 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_LENGTH +// register. +// +//***************************************************************************** +#define SHAMD5_LENGTH_M 0xFFFFFFFF // Block Length/Remaining Byte + // Count +#define SHAMD5_LENGTH_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA_0_IN +// register. +// +//***************************************************************************** +#define SHAMD5_DATA_0_IN_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_DATA_0_IN_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA_1_IN +// register. +// +//***************************************************************************** +#define SHAMD5_DATA_1_IN_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_DATA_1_IN_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA_2_IN +// register. +// +//***************************************************************************** +#define SHAMD5_DATA_2_IN_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_DATA_2_IN_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA_3_IN +// register. +// +//***************************************************************************** +#define SHAMD5_DATA_3_IN_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_DATA_3_IN_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA_4_IN +// register. +// +//***************************************************************************** +#define SHAMD5_DATA_4_IN_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_DATA_4_IN_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA_5_IN +// register. +// +//***************************************************************************** +#define SHAMD5_DATA_5_IN_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_DATA_5_IN_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA_6_IN +// register. +// +//***************************************************************************** +#define SHAMD5_DATA_6_IN_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_DATA_6_IN_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA_7_IN +// register. +// +//***************************************************************************** +#define SHAMD5_DATA_7_IN_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_DATA_7_IN_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA_8_IN +// register. +// +//***************************************************************************** +#define SHAMD5_DATA_8_IN_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_DATA_8_IN_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA_9_IN +// register. +// +//***************************************************************************** +#define SHAMD5_DATA_9_IN_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_DATA_9_IN_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA_10_IN +// register. +// +//***************************************************************************** +#define SHAMD5_DATA_10_IN_DATA_M \ + 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_DATA_10_IN_DATA_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA_11_IN +// register. +// +//***************************************************************************** +#define SHAMD5_DATA_11_IN_DATA_M \ + 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_DATA_11_IN_DATA_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA_12_IN +// register. +// +//***************************************************************************** +#define SHAMD5_DATA_12_IN_DATA_M \ + 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_DATA_12_IN_DATA_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA_13_IN +// register. +// +//***************************************************************************** +#define SHAMD5_DATA_13_IN_DATA_M \ + 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_DATA_13_IN_DATA_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA_14_IN +// register. +// +//***************************************************************************** +#define SHAMD5_DATA_14_IN_DATA_M \ + 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_DATA_14_IN_DATA_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA_15_IN +// register. +// +//***************************************************************************** +#define SHAMD5_DATA_15_IN_DATA_M \ + 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_DATA_15_IN_DATA_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_REVISION +// register. +// +//***************************************************************************** +#define SHAMD5_REVISION_M 0xFFFFFFFF // Revision Number +#define SHAMD5_REVISION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_SYSCONFIG +// register. +// +//***************************************************************************** +#define SHAMD5_SYSCONFIG_SADVANCED \ + 0x00000080 // Advanced Mode Enable +#define SHAMD5_SYSCONFIG_SIDLE_M \ + 0x00000030 // Sidle mode +#define SHAMD5_SYSCONFIG_SIDLE_FORCE \ + 0x00000000 // Force-idle mode +#define SHAMD5_SYSCONFIG_DMA_EN 0x00000008 // uDMA Request Enable +#define SHAMD5_SYSCONFIG_IT_EN 0x00000004 // Interrupt Enable +#define SHAMD5_SYSCONFIG_SOFTRESET \ + 0x00000002 // Soft reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_SYSSTATUS +// register. +// +//***************************************************************************** +#define SHAMD5_SYSSTATUS_RESETDONE \ + 0x00000001 // Reset done status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IRQSTATUS +// register. +// +//***************************************************************************** +#define SHAMD5_IRQSTATUS_CONTEXT_READY \ + 0x00000008 // Context Ready Status +#define SHAMD5_IRQSTATUS_INPUT_READY \ + 0x00000002 // Input Ready Status +#define SHAMD5_IRQSTATUS_OUTPUT_READY \ + 0x00000001 // Output Ready Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IRQENABLE +// register. +// +//***************************************************************************** +#define SHAMD5_IRQENABLE_CONTEXT_READY \ + 0x00000008 // Mask for context ready interrupt +#define SHAMD5_IRQENABLE_INPUT_READY \ + 0x00000002 // Mask for input ready interrupt +#define SHAMD5_IRQENABLE_OUTPUT_READY \ + 0x00000001 // Mask for output ready interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DMAIM register. +// +//***************************************************************************** +#define SHAMD5_DMAIM_COUT 0x00000004 // Context Out DMA Done Interrupt + // Mask +#define SHAMD5_DMAIM_DIN 0x00000002 // Data In DMA Done Interrupt Mask +#define SHAMD5_DMAIM_CIN 0x00000001 // Context In DMA Done Interrupt + // Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DMARIS +// register. +// +//***************************************************************************** +#define SHAMD5_DMARIS_COUT 0x00000004 // Context Out DMA Done Raw + // Interrupt Status +#define SHAMD5_DMARIS_DIN 0x00000002 // Data In DMA Done Raw Interrupt + // Status +#define SHAMD5_DMARIS_CIN 0x00000001 // Context In DMA Done Raw + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DMAMIS +// register. +// +//***************************************************************************** +#define SHAMD5_DMAMIS_COUT 0x00000004 // Context Out DMA Done Masked + // Interrupt Status +#define SHAMD5_DMAMIS_DIN 0x00000002 // Data In DMA Done Masked + // Interrupt Status +#define SHAMD5_DMAMIS_CIN 0x00000001 // Context In DMA Done Raw + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DMAIC register. +// +//***************************************************************************** +#define SHAMD5_DMAIC_COUT 0x00000004 // Context Out DMA Done Masked + // Interrupt Status +#define SHAMD5_DMAIC_DIN 0x00000002 // Data In DMA Done Interrupt Clear +#define SHAMD5_DMAIC_CIN 0x00000001 // Context In DMA Done Raw + // Interrupt Status + +#endif // __HW_SHAMD5_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_ssi.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_ssi.h new file mode 100644 index 0000000000000000000000000000000000000000..36a92cf1e4a16bbcaade40a87a8729839946b8ff --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_ssi.h @@ -0,0 +1,237 @@ +//***************************************************************************** +// +// hw_ssi.h - Macros used when accessing the SSI hardware. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_SSI_H__ +#define __HW_SSI_H__ + +//***************************************************************************** +// +// The following are defines for the SSI register offsets. +// +//***************************************************************************** +#define SSI_O_CR0 0x00000000 // SSI Control 0 +#define SSI_O_CR1 0x00000004 // SSI Control 1 +#define SSI_O_DR 0x00000008 // SSI Data +#define SSI_O_SR 0x0000000C // SSI Status +#define SSI_O_CPSR 0x00000010 // SSI Clock Prescale +#define SSI_O_IM 0x00000014 // SSI Interrupt Mask +#define SSI_O_RIS 0x00000018 // SSI Raw Interrupt Status +#define SSI_O_MIS 0x0000001C // SSI Masked Interrupt Status +#define SSI_O_ICR 0x00000020 // SSI Interrupt Clear +#define SSI_O_DMACTL 0x00000024 // SSI DMA Control +#define SSI_O_PP 0x00000FC0 // SSI Peripheral Properties +#define SSI_O_CC 0x00000FC8 // SSI Clock Configuration + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_CR0 register. +// +//***************************************************************************** +#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate +#define SSI_CR0_SPH 0x00000080 // SSI Serial Clock Phase +#define SSI_CR0_SPO 0x00000040 // SSI Serial Clock Polarity +#define SSI_CR0_FRF_M 0x00000030 // SSI Frame Format Select +#define SSI_CR0_FRF_MOTO 0x00000000 // Freescale SPI Frame Format +#define SSI_CR0_FRF_TI 0x00000010 // Synchronous Serial Frame Format +#define SSI_CR0_FRF_NMW 0x00000020 // MICROWIRE Frame Format +#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select +#define SSI_CR0_DSS_4 0x00000003 // 4-bit data +#define SSI_CR0_DSS_5 0x00000004 // 5-bit data +#define SSI_CR0_DSS_6 0x00000005 // 6-bit data +#define SSI_CR0_DSS_7 0x00000006 // 7-bit data +#define SSI_CR0_DSS_8 0x00000007 // 8-bit data +#define SSI_CR0_DSS_9 0x00000008 // 9-bit data +#define SSI_CR0_DSS_10 0x00000009 // 10-bit data +#define SSI_CR0_DSS_11 0x0000000A // 11-bit data +#define SSI_CR0_DSS_12 0x0000000B // 12-bit data +#define SSI_CR0_DSS_13 0x0000000C // 13-bit data +#define SSI_CR0_DSS_14 0x0000000D // 14-bit data +#define SSI_CR0_DSS_15 0x0000000E // 15-bit data +#define SSI_CR0_DSS_16 0x0000000F // 16-bit data +#define SSI_CR0_SCR_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_CR1 register. +// +//***************************************************************************** +#define SSI_CR1_EOM 0x00000800 // Stop Frame (End of Message) +#define SSI_CR1_FSSHLDFRM 0x00000400 // FSS Hold Frame +#define SSI_CR1_HSCLKEN 0x00000200 // High Speed Clock Enable +#define SSI_CR1_DIR 0x00000100 // SSI Direction of Operation +#define SSI_CR1_MODE_M 0x000000C0 // SSI Mode +#define SSI_CR1_MODE_LEGACY 0x00000000 // Legacy SSI mode +#define SSI_CR1_MODE_BI 0x00000040 // Bi-SSI mode +#define SSI_CR1_MODE_QUAD 0x00000080 // Quad-SSI Mode +#define SSI_CR1_MODE_ADVANCED 0x000000C0 // Advanced SSI Mode with 8-bit + // packet size +#define SSI_CR1_EOT 0x00000010 // End of Transmission +#define SSI_CR1_MS 0x00000004 // SSI Master/Slave Select +#define SSI_CR1_SSE 0x00000002 // SSI Synchronous Serial Port + // Enable +#define SSI_CR1_LBM 0x00000001 // SSI Loopback Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_DR register. +// +//***************************************************************************** +#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data +#define SSI_DR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_SR register. +// +//***************************************************************************** +#define SSI_SR_BSY 0x00000010 // SSI Busy Bit +#define SSI_SR_RFF 0x00000008 // SSI Receive FIFO Full +#define SSI_SR_RNE 0x00000004 // SSI Receive FIFO Not Empty +#define SSI_SR_TNF 0x00000002 // SSI Transmit FIFO Not Full +#define SSI_SR_TFE 0x00000001 // SSI Transmit FIFO Empty + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_CPSR register. +// +//***************************************************************************** +#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor +#define SSI_CPSR_CPSDVSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_IM register. +// +//***************************************************************************** +#define SSI_IM_EOTIM 0x00000040 // End of Transmit Interrupt Mask +#define SSI_IM_DMATXIM 0x00000020 // SSI Transmit DMA Interrupt Mask +#define SSI_IM_DMARXIM 0x00000010 // SSI Receive DMA Interrupt Mask +#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt Mask +#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask +#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt + // Mask +#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt + // Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_RIS register. +// +//***************************************************************************** +#define SSI_RIS_EOTRIS 0x00000040 // End of Transmit Raw Interrupt + // Status +#define SSI_RIS_DMATXRIS 0x00000020 // SSI Transmit DMA Raw Interrupt + // Status +#define SSI_RIS_DMARXRIS 0x00000010 // SSI Receive DMA Raw Interrupt + // Status +#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt + // Status +#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt + // Status +#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw + // Interrupt Status +#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_MIS register. +// +//***************************************************************************** +#define SSI_MIS_EOTMIS 0x00000040 // End of Transmit Masked Interrupt + // Status +#define SSI_MIS_DMATXMIS 0x00000020 // SSI Transmit DMA Masked + // Interrupt Status +#define SSI_MIS_DMARXMIS 0x00000010 // SSI Receive DMA Masked Interrupt + // Status +#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked + // Interrupt Status +#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked + // Interrupt Status +#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked + // Interrupt Status +#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_ICR register. +// +//***************************************************************************** +#define SSI_ICR_EOTIC 0x00000040 // End of Transmit Interrupt Clear +#define SSI_ICR_DMATXIC 0x00000020 // SSI Transmit DMA Interrupt Clear +#define SSI_ICR_DMARXIC 0x00000010 // SSI Receive DMA Interrupt Clear +#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt + // Clear +#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_DMACTL register. +// +//***************************************************************************** +#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable +#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_PP register. +// +//***************************************************************************** +#define SSI_PP_FSSHLDFRM 0x00000008 // FSS Hold Frame Capability +#define SSI_PP_MODE_M 0x00000006 // Mode of Operation +#define SSI_PP_MODE_LEGACY 0x00000000 // Legacy SSI mode +#define SSI_PP_MODE_ADVBI 0x00000002 // Legacy mode, Advanced SSI mode + // and Bi-SSI mode enabled +#define SSI_PP_MODE_ADVBIQUAD 0x00000004 // Legacy mode, Advanced mode, + // Bi-SSI and Quad-SSI mode enabled +#define SSI_PP_HSCLK 0x00000001 // High Speed Capability + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_CC register. +// +//***************************************************************************** +#define SSI_CC_CS_M 0x0000000F // SSI Baud Clock Source +#define SSI_CC_CS_SYSPLL 0x00000000 // System clock (based on clock + // source and divisor factor) +#define SSI_CC_CS_PIOSC 0x00000005 // PIOSC + +#endif // __HW_SSI_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_sysctl.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_sysctl.h new file mode 100644 index 0000000000000000000000000000000000000000..cab5049da58c3d6a1b34f7d959f4f665ef695255 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_sysctl.h @@ -0,0 +1,3749 @@ +//***************************************************************************** +// +// hw_sysctl.h - Macros used when accessing the system control hardware. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_SYSCTL_H__ +#define __HW_SYSCTL_H__ + +//***************************************************************************** +// +// The following are defines for the System Control register addresses. +// +//***************************************************************************** +#define SYSCTL_DID0 0x400FE000 // Device Identification 0 +#define SYSCTL_DID1 0x400FE004 // Device Identification 1 +#define SYSCTL_DC0 0x400FE008 // Device Capabilities 0 +#define SYSCTL_DC1 0x400FE010 // Device Capabilities 1 +#define SYSCTL_DC2 0x400FE014 // Device Capabilities 2 +#define SYSCTL_DC3 0x400FE018 // Device Capabilities 3 +#define SYSCTL_DC4 0x400FE01C // Device Capabilities 4 +#define SYSCTL_DC5 0x400FE020 // Device Capabilities 5 +#define SYSCTL_DC6 0x400FE024 // Device Capabilities 6 +#define SYSCTL_DC7 0x400FE028 // Device Capabilities 7 +#define SYSCTL_DC8 0x400FE02C // Device Capabilities 8 +#define SYSCTL_PBORCTL 0x400FE030 // Brown-Out Reset Control +#define SYSCTL_PTBOCTL 0x400FE038 // Power-Temp Brown Out Control +#define SYSCTL_SRCR0 0x400FE040 // Software Reset Control 0 +#define SYSCTL_SRCR1 0x400FE044 // Software Reset Control 1 +#define SYSCTL_SRCR2 0x400FE048 // Software Reset Control 2 +#define SYSCTL_RIS 0x400FE050 // Raw Interrupt Status +#define SYSCTL_IMC 0x400FE054 // Interrupt Mask Control +#define SYSCTL_MISC 0x400FE058 // Masked Interrupt Status and + // Clear +#define SYSCTL_RESC 0x400FE05C // Reset Cause +#define SYSCTL_PWRTC 0x400FE060 // Power-Temperature Cause +#define SYSCTL_RCC 0x400FE060 // Run-Mode Clock Configuration +#define SYSCTL_NMIC 0x400FE064 // NMI Cause Register +#define SYSCTL_GPIOHBCTL 0x400FE06C // GPIO High-Performance Bus + // Control +#define SYSCTL_RCC2 0x400FE070 // Run-Mode Clock Configuration 2 +#define SYSCTL_MOSCCTL 0x400FE07C // Main Oscillator Control +#define SYSCTL_RSCLKCFG 0x400FE0B0 // Run and Sleep Mode Configuration + // Register +#define SYSCTL_MEMTIM0 0x400FE0C0 // Memory Timing Parameter Register + // 0 for Main Flash and EEPROM +#define SYSCTL_RCGC0 0x400FE100 // Run Mode Clock Gating Control + // Register 0 +#define SYSCTL_RCGC1 0x400FE104 // Run Mode Clock Gating Control + // Register 1 +#define SYSCTL_RCGC2 0x400FE108 // Run Mode Clock Gating Control + // Register 2 +#define SYSCTL_SCGC0 0x400FE110 // Sleep Mode Clock Gating Control + // Register 0 +#define SYSCTL_SCGC1 0x400FE114 // Sleep Mode Clock Gating Control + // Register 1 +#define SYSCTL_SCGC2 0x400FE118 // Sleep Mode Clock Gating Control + // Register 2 +#define SYSCTL_DCGC0 0x400FE120 // Deep Sleep Mode Clock Gating + // Control Register 0 +#define SYSCTL_DCGC1 0x400FE124 // Deep-Sleep Mode Clock Gating + // Control Register 1 +#define SYSCTL_DCGC2 0x400FE128 // Deep Sleep Mode Clock Gating + // Control Register 2 +#define SYSCTL_ALTCLKCFG 0x400FE138 // Alternate Clock Configuration +#define SYSCTL_DSLPCLKCFG 0x400FE144 // Deep Sleep Clock Configuration +#define SYSCTL_DSCLKCFG 0x400FE144 // Deep Sleep Clock Configuration + // Register +#define SYSCTL_DIVSCLK 0x400FE148 // Divisor and Source Clock + // Configuration +#define SYSCTL_SYSPROP 0x400FE14C // System Properties +#define SYSCTL_PIOSCCAL 0x400FE150 // Precision Internal Oscillator + // Calibration +#define SYSCTL_PIOSCSTAT 0x400FE154 // Precision Internal Oscillator + // Statistics +#define SYSCTL_PLLFREQ0 0x400FE160 // PLL Frequency 0 +#define SYSCTL_PLLFREQ1 0x400FE164 // PLL Frequency 1 +#define SYSCTL_PLLSTAT 0x400FE168 // PLL Status +#define SYSCTL_SLPPWRCFG 0x400FE188 // Sleep Power Configuration +#define SYSCTL_DSLPPWRCFG 0x400FE18C // Deep-Sleep Power Configuration +#define SYSCTL_DC9 0x400FE190 // Device Capabilities 9 +#define SYSCTL_NVMSTAT 0x400FE1A0 // Non-Volatile Memory Information +#define SYSCTL_LDOSPCTL 0x400FE1B4 // LDO Sleep Power Control +#define SYSCTL_LDODPCTL 0x400FE1BC // LDO Deep-Sleep Power Control +#define SYSCTL_RESBEHAVCTL 0x400FE1D8 // Reset Behavior Control Register +#define SYSCTL_HSSR 0x400FE1F4 // Hardware System Service Request +#define SYSCTL_USBPDS 0x400FE280 // USB Power Domain Status +#define SYSCTL_USBMPC 0x400FE284 // USB Memory Power Control +#define SYSCTL_EMACPDS 0x400FE288 // Ethernet MAC Power Domain Status +#define SYSCTL_EMACMPC 0x400FE28C // Ethernet MAC Memory Power + // Control +#define SYSCTL_LCDMPC 0x400FE294 // LCD Memory Power Control +#define SYSCTL_PPWD 0x400FE300 // Watchdog Timer Peripheral + // Present +#define SYSCTL_PPTIMER 0x400FE304 // 16/32-Bit General-Purpose Timer + // Peripheral Present +#define SYSCTL_PPGPIO 0x400FE308 // General-Purpose Input/Output + // Peripheral Present +#define SYSCTL_PPDMA 0x400FE30C // Micro Direct Memory Access + // Peripheral Present +#define SYSCTL_PPEPI 0x400FE310 // EPI Peripheral Present +#define SYSCTL_PPHIB 0x400FE314 // Hibernation Peripheral Present +#define SYSCTL_PPUART 0x400FE318 // Universal Asynchronous + // Receiver/Transmitter Peripheral + // Present +#define SYSCTL_PPSSI 0x400FE31C // Synchronous Serial Interface + // Peripheral Present +#define SYSCTL_PPI2C 0x400FE320 // Inter-Integrated Circuit + // Peripheral Present +#define SYSCTL_PPUSB 0x400FE328 // Universal Serial Bus Peripheral + // Present +#define SYSCTL_PPEPHY 0x400FE330 // Ethernet PHY Peripheral Present +#define SYSCTL_PPCAN 0x400FE334 // Controller Area Network + // Peripheral Present +#define SYSCTL_PPADC 0x400FE338 // Analog-to-Digital Converter + // Peripheral Present +#define SYSCTL_PPACMP 0x400FE33C // Analog Comparator Peripheral + // Present +#define SYSCTL_PPPWM 0x400FE340 // Pulse Width Modulator Peripheral + // Present +#define SYSCTL_PPQEI 0x400FE344 // Quadrature Encoder Interface + // Peripheral Present +#define SYSCTL_PPLPC 0x400FE348 // Low Pin Count Interface + // Peripheral Present +#define SYSCTL_PPPECI 0x400FE350 // Platform Environment Control + // Interface Peripheral Present +#define SYSCTL_PPFAN 0x400FE354 // Fan Control Peripheral Present +#define SYSCTL_PPEEPROM 0x400FE358 // EEPROM Peripheral Present +#define SYSCTL_PPWTIMER 0x400FE35C // 32/64-Bit Wide General-Purpose + // Timer Peripheral Present +#define SYSCTL_PPRTS 0x400FE370 // Remote Temperature Sensor + // Peripheral Present +#define SYSCTL_PPCCM 0x400FE374 // CRC and Cryptographic Modules + // Peripheral Present +#define SYSCTL_PPLCD 0x400FE390 // LCD Peripheral Present +#define SYSCTL_PPOWIRE 0x400FE398 // 1-Wire Peripheral Present +#define SYSCTL_PPEMAC 0x400FE39C // Ethernet MAC Peripheral Present +#define SYSCTL_PPHIM 0x400FE3A4 // Human Interface Master + // Peripheral Present +#define SYSCTL_SRWD 0x400FE500 // Watchdog Timer Software Reset +#define SYSCTL_SRTIMER 0x400FE504 // 16/32-Bit General-Purpose Timer + // Software Reset +#define SYSCTL_SRGPIO 0x400FE508 // General-Purpose Input/Output + // Software Reset +#define SYSCTL_SRDMA 0x400FE50C // Micro Direct Memory Access + // Software Reset +#define SYSCTL_SREPI 0x400FE510 // EPI Software Reset +#define SYSCTL_SRHIB 0x400FE514 // Hibernation Software Reset +#define SYSCTL_SRUART 0x400FE518 // Universal Asynchronous + // Receiver/Transmitter Software + // Reset +#define SYSCTL_SRSSI 0x400FE51C // Synchronous Serial Interface + // Software Reset +#define SYSCTL_SRI2C 0x400FE520 // Inter-Integrated Circuit + // Software Reset +#define SYSCTL_SRUSB 0x400FE528 // Universal Serial Bus Software + // Reset +#define SYSCTL_SREPHY 0x400FE530 // Ethernet PHY Software Reset +#define SYSCTL_SRCAN 0x400FE534 // Controller Area Network Software + // Reset +#define SYSCTL_SRADC 0x400FE538 // Analog-to-Digital Converter + // Software Reset +#define SYSCTL_SRACMP 0x400FE53C // Analog Comparator Software Reset +#define SYSCTL_SRPWM 0x400FE540 // Pulse Width Modulator Software + // Reset +#define SYSCTL_SRQEI 0x400FE544 // Quadrature Encoder Interface + // Software Reset +#define SYSCTL_SREEPROM 0x400FE558 // EEPROM Software Reset +#define SYSCTL_SRWTIMER 0x400FE55C // 32/64-Bit Wide General-Purpose + // Timer Software Reset +#define SYSCTL_SRCCM 0x400FE574 // CRC and Cryptographic Modules + // Software Reset +#define SYSCTL_SRLCD 0x400FE590 // LCD Controller Software Reset +#define SYSCTL_SROWIRE 0x400FE598 // 1-Wire Software Reset +#define SYSCTL_SREMAC 0x400FE59C // Ethernet MAC Software Reset +#define SYSCTL_RCGCWD 0x400FE600 // Watchdog Timer Run Mode Clock + // Gating Control +#define SYSCTL_RCGCTIMER 0x400FE604 // 16/32-Bit General-Purpose Timer + // Run Mode Clock Gating Control +#define SYSCTL_RCGCGPIO 0x400FE608 // General-Purpose Input/Output Run + // Mode Clock Gating Control +#define SYSCTL_RCGCDMA 0x400FE60C // Micro Direct Memory Access Run + // Mode Clock Gating Control +#define SYSCTL_RCGCEPI 0x400FE610 // EPI Run Mode Clock Gating + // Control +#define SYSCTL_RCGCHIB 0x400FE614 // Hibernation Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART 0x400FE618 // Universal Asynchronous + // Receiver/Transmitter Run Mode + // Clock Gating Control +#define SYSCTL_RCGCSSI 0x400FE61C // Synchronous Serial Interface Run + // Mode Clock Gating Control +#define SYSCTL_RCGCI2C 0x400FE620 // Inter-Integrated Circuit Run + // Mode Clock Gating Control +#define SYSCTL_RCGCUSB 0x400FE628 // Universal Serial Bus Run Mode + // Clock Gating Control +#define SYSCTL_RCGCEPHY 0x400FE630 // Ethernet PHY Run Mode Clock + // Gating Control +#define SYSCTL_RCGCCAN 0x400FE634 // Controller Area Network Run Mode + // Clock Gating Control +#define SYSCTL_RCGCADC 0x400FE638 // Analog-to-Digital Converter Run + // Mode Clock Gating Control +#define SYSCTL_RCGCACMP 0x400FE63C // Analog Comparator Run Mode Clock + // Gating Control +#define SYSCTL_RCGCPWM 0x400FE640 // Pulse Width Modulator Run Mode + // Clock Gating Control +#define SYSCTL_RCGCQEI 0x400FE644 // Quadrature Encoder Interface Run + // Mode Clock Gating Control +#define SYSCTL_RCGCEEPROM 0x400FE658 // EEPROM Run Mode Clock Gating + // Control +#define SYSCTL_RCGCWTIMER 0x400FE65C // 32/64-Bit Wide General-Purpose + // Timer Run Mode Clock Gating + // Control +#define SYSCTL_RCGCCCM 0x400FE674 // CRC and Cryptographic Modules + // Run Mode Clock Gating Control +#define SYSCTL_RCGCLCD 0x400FE690 // LCD Controller Run Mode Clock + // Gating Control +#define SYSCTL_RCGCOWIRE 0x400FE698 // 1-Wire Run Mode Clock Gating + // Control +#define SYSCTL_RCGCEMAC 0x400FE69C // Ethernet MAC Run Mode Clock + // Gating Control +#define SYSCTL_SCGCWD 0x400FE700 // Watchdog Timer Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCTIMER 0x400FE704 // 16/32-Bit General-Purpose Timer + // Sleep Mode Clock Gating Control +#define SYSCTL_SCGCGPIO 0x400FE708 // General-Purpose Input/Output + // Sleep Mode Clock Gating Control +#define SYSCTL_SCGCDMA 0x400FE70C // Micro Direct Memory Access Sleep + // Mode Clock Gating Control +#define SYSCTL_SCGCEPI 0x400FE710 // EPI Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCHIB 0x400FE714 // Hibernation Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART 0x400FE718 // Universal Asynchronous + // Receiver/Transmitter Sleep Mode + // Clock Gating Control +#define SYSCTL_SCGCSSI 0x400FE71C // Synchronous Serial Interface + // Sleep Mode Clock Gating Control +#define SYSCTL_SCGCI2C 0x400FE720 // Inter-Integrated Circuit Sleep + // Mode Clock Gating Control +#define SYSCTL_SCGCUSB 0x400FE728 // Universal Serial Bus Sleep Mode + // Clock Gating Control +#define SYSCTL_SCGCEPHY 0x400FE730 // Ethernet PHY Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCCAN 0x400FE734 // Controller Area Network Sleep + // Mode Clock Gating Control +#define SYSCTL_SCGCADC 0x400FE738 // Analog-to-Digital Converter + // Sleep Mode Clock Gating Control +#define SYSCTL_SCGCACMP 0x400FE73C // Analog Comparator Sleep Mode + // Clock Gating Control +#define SYSCTL_SCGCPWM 0x400FE740 // Pulse Width Modulator Sleep Mode + // Clock Gating Control +#define SYSCTL_SCGCQEI 0x400FE744 // Quadrature Encoder Interface + // Sleep Mode Clock Gating Control +#define SYSCTL_SCGCEEPROM 0x400FE758 // EEPROM Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCWTIMER 0x400FE75C // 32/64-Bit Wide General-Purpose + // Timer Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCCCM 0x400FE774 // CRC and Cryptographic Modules + // Sleep Mode Clock Gating Control +#define SYSCTL_SCGCLCD 0x400FE790 // LCD Controller Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCOWIRE 0x400FE798 // 1-Wire Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCEMAC 0x400FE79C // Ethernet MAC Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCWD 0x400FE800 // Watchdog Timer Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCTIMER 0x400FE804 // 16/32-Bit General-Purpose Timer + // Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCGPIO 0x400FE808 // General-Purpose Input/Output + // Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCDMA 0x400FE80C // Micro Direct Memory Access + // Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCEPI 0x400FE810 // EPI Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCHIB 0x400FE814 // Hibernation Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART 0x400FE818 // Universal Asynchronous + // Receiver/Transmitter Deep-Sleep + // Mode Clock Gating Control +#define SYSCTL_DCGCSSI 0x400FE81C // Synchronous Serial Interface + // Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCI2C 0x400FE820 // Inter-Integrated Circuit + // Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCUSB 0x400FE828 // Universal Serial Bus Deep-Sleep + // Mode Clock Gating Control +#define SYSCTL_DCGCEPHY 0x400FE830 // Ethernet PHY Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCCAN 0x400FE834 // Controller Area Network + // Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCADC 0x400FE838 // Analog-to-Digital Converter + // Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCACMP 0x400FE83C // Analog Comparator Deep-Sleep + // Mode Clock Gating Control +#define SYSCTL_DCGCPWM 0x400FE840 // Pulse Width Modulator Deep-Sleep + // Mode Clock Gating Control +#define SYSCTL_DCGCQEI 0x400FE844 // Quadrature Encoder Interface + // Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCEEPROM 0x400FE858 // EEPROM Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCWTIMER 0x400FE85C // 32/64-Bit Wide General-Purpose + // Timer Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCCCM 0x400FE874 // CRC and Cryptographic Modules + // Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCLCD 0x400FE890 // LCD Controller Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCOWIRE 0x400FE898 // 1-Wire Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCEMAC 0x400FE89C // Ethernet MAC Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_PCWD 0x400FE900 // Watchdog Timer Power Control +#define SYSCTL_PCTIMER 0x400FE904 // 16/32-Bit General-Purpose Timer + // Power Control +#define SYSCTL_PCGPIO 0x400FE908 // General-Purpose Input/Output + // Power Control +#define SYSCTL_PCDMA 0x400FE90C // Micro Direct Memory Access Power + // Control +#define SYSCTL_PCEPI 0x400FE910 // External Peripheral Interface + // Power Control +#define SYSCTL_PCHIB 0x400FE914 // Hibernation Power Control +#define SYSCTL_PCUART 0x400FE918 // Universal Asynchronous + // Receiver/Transmitter Power + // Control +#define SYSCTL_PCSSI 0x400FE91C // Synchronous Serial Interface + // Power Control +#define SYSCTL_PCI2C 0x400FE920 // Inter-Integrated Circuit Power + // Control +#define SYSCTL_PCUSB 0x400FE928 // Universal Serial Bus Power + // Control +#define SYSCTL_PCEPHY 0x400FE930 // Ethernet PHY Power Control +#define SYSCTL_PCCAN 0x400FE934 // Controller Area Network Power + // Control +#define SYSCTL_PCADC 0x400FE938 // Analog-to-Digital Converter + // Power Control +#define SYSCTL_PCACMP 0x400FE93C // Analog Comparator Power Control +#define SYSCTL_PCPWM 0x400FE940 // Pulse Width Modulator Power + // Control +#define SYSCTL_PCQEI 0x400FE944 // Quadrature Encoder Interface + // Power Control +#define SYSCTL_PCEEPROM 0x400FE958 // EEPROM Power Control +#define SYSCTL_PCCCM 0x400FE974 // CRC and Cryptographic Modules + // Power Control +#define SYSCTL_PCLCD 0x400FE990 // LCD Controller Power Control +#define SYSCTL_PCOWIRE 0x400FE998 // 1-Wire Power Control +#define SYSCTL_PCEMAC 0x400FE99C // Ethernet MAC Power Control +#define SYSCTL_PRWD 0x400FEA00 // Watchdog Timer Peripheral Ready +#define SYSCTL_PRTIMER 0x400FEA04 // 16/32-Bit General-Purpose Timer + // Peripheral Ready +#define SYSCTL_PRGPIO 0x400FEA08 // General-Purpose Input/Output + // Peripheral Ready +#define SYSCTL_PRDMA 0x400FEA0C // Micro Direct Memory Access + // Peripheral Ready +#define SYSCTL_PREPI 0x400FEA10 // EPI Peripheral Ready +#define SYSCTL_PRHIB 0x400FEA14 // Hibernation Peripheral Ready +#define SYSCTL_PRUART 0x400FEA18 // Universal Asynchronous + // Receiver/Transmitter Peripheral + // Ready +#define SYSCTL_PRSSI 0x400FEA1C // Synchronous Serial Interface + // Peripheral Ready +#define SYSCTL_PRI2C 0x400FEA20 // Inter-Integrated Circuit + // Peripheral Ready +#define SYSCTL_PRUSB 0x400FEA28 // Universal Serial Bus Peripheral + // Ready +#define SYSCTL_PREPHY 0x400FEA30 // Ethernet PHY Peripheral Ready +#define SYSCTL_PRCAN 0x400FEA34 // Controller Area Network + // Peripheral Ready +#define SYSCTL_PRADC 0x400FEA38 // Analog-to-Digital Converter + // Peripheral Ready +#define SYSCTL_PRACMP 0x400FEA3C // Analog Comparator Peripheral + // Ready +#define SYSCTL_PRPWM 0x400FEA40 // Pulse Width Modulator Peripheral + // Ready +#define SYSCTL_PRQEI 0x400FEA44 // Quadrature Encoder Interface + // Peripheral Ready +#define SYSCTL_PREEPROM 0x400FEA58 // EEPROM Peripheral Ready +#define SYSCTL_PRWTIMER 0x400FEA5C // 32/64-Bit Wide General-Purpose + // Timer Peripheral Ready +#define SYSCTL_PRCCM 0x400FEA74 // CRC and Cryptographic Modules + // Peripheral Ready +#define SYSCTL_PRLCD 0x400FEA90 // LCD Controller Peripheral Ready +#define SYSCTL_PROWIRE 0x400FEA98 // 1-Wire Peripheral Ready +#define SYSCTL_PREMAC 0x400FEA9C // Ethernet MAC Peripheral Ready +#define SYSCTL_UNIQUEID0 0x400FEF20 // Unique ID 0 +#define SYSCTL_UNIQUEID1 0x400FEF24 // Unique ID 1 +#define SYSCTL_UNIQUEID2 0x400FEF28 // Unique ID 2 +#define SYSCTL_UNIQUEID3 0x400FEF2C // Unique ID 3 +#define SYSCTL_CCMCGREQ 0x44030204 // Cryptographic Modules Clock + // Gating Request + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DID0 register. +// +//***************************************************************************** +#define SYSCTL_DID0_VER_M 0x70000000 // DID0 Version +#define SYSCTL_DID0_VER_1 0x10000000 // Second version of the DID0 + // register format. +#define SYSCTL_DID0_CLASS_M 0x00FF0000 // Device Class +#define SYSCTL_DID0_CLASS_TM4C123 \ + 0x00050000 // Tiva TM4C123x and TM4E123x + // microcontrollers +#define SYSCTL_DID0_CLASS_TM4C129 \ + 0x000A0000 // Tiva(TM) TM4C129-class + // microcontrollers +#define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major Revision +#define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device) +#define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer + // revision) +#define SYSCTL_DID0_MAJ_REVC 0x00000200 // Revision C (second base layer + // revision) +#define SYSCTL_DID0_MIN_M 0x000000FF // Minor Revision +#define SYSCTL_DID0_MIN_0 0x00000000 // Initial device, or a major + // revision update +#define SYSCTL_DID0_MIN_1 0x00000001 // First metal layer change +#define SYSCTL_DID0_MIN_2 0x00000002 // Second metal layer change + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DID1 register. +// +//***************************************************************************** +#define SYSCTL_DID1_VER_M 0xF0000000 // DID1 Version +#define SYSCTL_DID1_VER_1 0x10000000 // fury_ib +#define SYSCTL_DID1_FAM_M 0x0F000000 // Family +#define SYSCTL_DID1_FAM_TIVA 0x00000000 // Tiva family of microcontollers +#define SYSCTL_DID1_PRTNO_M 0x00FF0000 // Part Number +#define SYSCTL_DID1_PRTNO_TM4C1230C3PM \ + 0x00220000 // TM4C1230C3PM +#define SYSCTL_DID1_PRTNO_TM4C1230D5PM \ + 0x00230000 // TM4C1230D5PM +#define SYSCTL_DID1_PRTNO_TM4C1230E6PM \ + 0x00200000 // TM4C1230E6PM +#define SYSCTL_DID1_PRTNO_TM4C1230H6PM \ + 0x00210000 // TM4C1230H6PM +#define SYSCTL_DID1_PRTNO_TM4C1231C3PM \ + 0x00180000 // TM4C1231C3PM +#define SYSCTL_DID1_PRTNO_TM4C1231D5PM \ + 0x00190000 // TM4C1231D5PM +#define SYSCTL_DID1_PRTNO_TM4C1231D5PZ \ + 0x00360000 // TM4C1231D5PZ +#define SYSCTL_DID1_PRTNO_TM4C1231E6PM \ + 0x00100000 // TM4C1231E6PM +#define SYSCTL_DID1_PRTNO_TM4C1231E6PZ \ + 0x00300000 // TM4C1231E6PZ +#define SYSCTL_DID1_PRTNO_TM4C1231H6PGE \ + 0x00350000 // TM4C1231H6PGE +#define SYSCTL_DID1_PRTNO_TM4C1231H6PM \ + 0x00110000 // TM4C1231H6PM +#define SYSCTL_DID1_PRTNO_TM4C1231H6PZ \ + 0x00310000 // TM4C1231H6PZ +#define SYSCTL_DID1_PRTNO_TM4C1232C3PM \ + 0x00080000 // TM4C1232C3PM +#define SYSCTL_DID1_PRTNO_TM4C1232D5PM \ + 0x00090000 // TM4C1232D5PM +#define SYSCTL_DID1_PRTNO_TM4C1232E6PM \ + 0x000A0000 // TM4C1232E6PM +#define SYSCTL_DID1_PRTNO_TM4C1232H6PM \ + 0x000B0000 // TM4C1232H6PM +#define SYSCTL_DID1_PRTNO_TM4C1233C3PM \ + 0x00010000 // TM4C1233C3PM +#define SYSCTL_DID1_PRTNO_TM4C1233D5PM \ + 0x00020000 // TM4C1233D5PM +#define SYSCTL_DID1_PRTNO_TM4C1233D5PZ \ + 0x00D00000 // TM4C1233D5PZ +#define SYSCTL_DID1_PRTNO_TM4C1233E6PM \ + 0x00030000 // TM4C1233E6PM +#define SYSCTL_DID1_PRTNO_TM4C1233E6PZ \ + 0x00D10000 // TM4C1233E6PZ +#define SYSCTL_DID1_PRTNO_TM4C1233H6PGE \ + 0x00D60000 // TM4C1233H6PGE +#define SYSCTL_DID1_PRTNO_TM4C1233H6PM \ + 0x00040000 // TM4C1233H6PM +#define SYSCTL_DID1_PRTNO_TM4C1233H6PZ \ + 0x00D20000 // TM4C1233H6PZ +#define SYSCTL_DID1_PRTNO_TM4C1236D5PM \ + 0x00520000 // TM4C1236D5PM +#define SYSCTL_DID1_PRTNO_TM4C1236E6PM \ + 0x00500000 // TM4C1236E6PM +#define SYSCTL_DID1_PRTNO_TM4C1236H6PM \ + 0x00510000 // TM4C1236H6PM +#define SYSCTL_DID1_PRTNO_TM4C1237D5PM \ + 0x00480000 // TM4C1237D5PM +#define SYSCTL_DID1_PRTNO_TM4C1237D5PZ \ + 0x00660000 // TM4C1237D5PZ +#define SYSCTL_DID1_PRTNO_TM4C1237E6PM \ + 0x00400000 // TM4C1237E6PM +#define SYSCTL_DID1_PRTNO_TM4C1237E6PZ \ + 0x00600000 // TM4C1237E6PZ +#define SYSCTL_DID1_PRTNO_TM4C1237H6PGE \ + 0x00650000 // TM4C1237H6PGE +#define SYSCTL_DID1_PRTNO_TM4C1237H6PM \ + 0x00410000 // TM4C1237H6PM +#define SYSCTL_DID1_PRTNO_TM4C1237H6PZ \ + 0x00610000 // TM4C1237H6PZ +#define SYSCTL_DID1_PRTNO_TM4C123AE6PM \ + 0x00800000 // TM4C123AE6PM +#define SYSCTL_DID1_PRTNO_TM4C123AH6PM \ + 0x00830000 // TM4C123AH6PM +#define SYSCTL_DID1_PRTNO_TM4C123BE6PM \ + 0x00700000 // TM4C123BE6PM +#define SYSCTL_DID1_PRTNO_TM4C123BE6PZ \ + 0x00C30000 // TM4C123BE6PZ +#define SYSCTL_DID1_PRTNO_TM4C123BH6PGE \ + 0x00C60000 // TM4C123BH6PGE +#define SYSCTL_DID1_PRTNO_TM4C123BH6PM \ + 0x00730000 // TM4C123BH6PM +#define SYSCTL_DID1_PRTNO_TM4C123BH6PZ \ + 0x00C40000 // TM4C123BH6PZ +#define SYSCTL_DID1_PRTNO_TM4C123BH6ZRB \ + 0x00E90000 // TM4C123BH6ZRB +#define SYSCTL_DID1_PRTNO_TM4C123FE6PM \ + 0x00B00000 // TM4C123FE6PM +#define SYSCTL_DID1_PRTNO_TM4C123FH6PM \ + 0x00B10000 // TM4C123FH6PM +#define SYSCTL_DID1_PRTNO_TM4C123GE6PM \ + 0x00A00000 // TM4C123GE6PM +#define SYSCTL_DID1_PRTNO_TM4C123GE6PZ \ + 0x00C00000 // TM4C123GE6PZ +#define SYSCTL_DID1_PRTNO_TM4C123GH6PGE \ + 0x00C50000 // TM4C123GH6PGE +#define SYSCTL_DID1_PRTNO_TM4C123GH6PM \ + 0x00A10000 // TM4C123GH6PM +#define SYSCTL_DID1_PRTNO_TM4C123GH6PZ \ + 0x00C10000 // TM4C123GH6PZ +#define SYSCTL_DID1_PRTNO_TM4C123GH6ZRB \ + 0x00E30000 // TM4C123GH6ZRB +#define SYSCTL_DID1_PRTNO_TM4C1290NCPDT \ + 0x00190000 // TM4C1290NCPDT +#define SYSCTL_DID1_PRTNO_TM4C1290NCZAD \ + 0x001B0000 // TM4C1290NCZAD +#define SYSCTL_DID1_PRTNO_TM4C1292NCPDT \ + 0x001C0000 // TM4C1292NCPDT +#define SYSCTL_DID1_PRTNO_TM4C1292NCZAD \ + 0x001E0000 // TM4C1292NCZAD +#define SYSCTL_DID1_PRTNO_TM4C1294KCPDT \ + 0x00340000 // TM4C1294KCPDT +#define SYSCTL_DID1_PRTNO_TM4C1294NCPDT \ + 0x001F0000 // TM4C1294NCPDT +#define SYSCTL_DID1_PRTNO_TM4C1294NCZAD \ + 0x00210000 // TM4C1294NCZAD +#define SYSCTL_DID1_PRTNO_TM4C1297NCZAD \ + 0x00220000 // TM4C1297NCZAD +#define SYSCTL_DID1_PRTNO_TM4C1299KCZAD \ + 0x00360000 // TM4C1299KCZAD +#define SYSCTL_DID1_PRTNO_TM4C1299NCZAD \ + 0x00230000 // TM4C1299NCZAD +#define SYSCTL_DID1_PRTNO_TM4C129CNCPDT \ + 0x00240000 // TM4C129CNCPDT +#define SYSCTL_DID1_PRTNO_TM4C129CNCZAD \ + 0x00260000 // TM4C129CNCZAD +#define SYSCTL_DID1_PRTNO_TM4C129DNCPDT \ + 0x00270000 // TM4C129DNCPDT +#define SYSCTL_DID1_PRTNO_TM4C129DNCZAD \ + 0x00290000 // TM4C129DNCZAD +#define SYSCTL_DID1_PRTNO_TM4C129EKCPDT \ + 0x00350000 // TM4C129EKCPDT +#define SYSCTL_DID1_PRTNO_TM4C129ENCPDT \ + 0x002D0000 // TM4C129ENCPDT +#define SYSCTL_DID1_PRTNO_TM4C129ENCZAD \ + 0x002F0000 // TM4C129ENCZAD +#define SYSCTL_DID1_PRTNO_TM4C129LNCZAD \ + 0x00300000 // TM4C129LNCZAD +#define SYSCTL_DID1_PRTNO_TM4C129XKCZAD \ + 0x00370000 // TM4C129XKCZAD +#define SYSCTL_DID1_PRTNO_TM4C129XNCZAD \ + 0x00320000 // TM4C129XNCZAD +#define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count +#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100-pin LQFP package +#define SYSCTL_DID1_PINCNT_64 0x00006000 // 64-pin LQFP package +#define SYSCTL_DID1_PINCNT_144 0x00008000 // 144-pin LQFP package +#define SYSCTL_DID1_PINCNT_157 0x0000A000 // 157-pin BGA package +#define SYSCTL_DID1_PINCNT_128 0x0000C000 // 128-pin TQFP package +#define SYSCTL_DID1_TEMP_M 0x000000E0 // Temperature Range +#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temperature range +#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temperature range +#define SYSCTL_DID1_TEMP_E 0x00000040 // Extended temperature range +#define SYSCTL_DID1_TEMP_IE 0x00000060 // Available in both industrial + // temperature range (-40C to 85C) + // and extended temperature range + // (-40C to 105C) devices. See +#define SYSCTL_DID1_PKG_M 0x00000018 // Package Type +#define SYSCTL_DID1_PKG_QFP 0x00000008 // QFP package +#define SYSCTL_DID1_PKG_BGA 0x00000010 // BGA package +#define SYSCTL_DID1_ROHS 0x00000004 // RoHS-Compliance +#define SYSCTL_DID1_QUAL_M 0x00000003 // Qualification Status +#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering Sample (unqualified) +#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot Production (unqualified) +#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully Qualified + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC0 register. +// +//***************************************************************************** +#define SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 // SRAM Size +#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_6KB 0x00170000 // 6 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_12KB 0x002F0000 // 12 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_20KB 0x004F0000 // 20 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_24KB 0x005F0000 // 24 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM +#define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF // Flash Size +#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of Flash +#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of Flash +#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of Flash +#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of Flash +#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of Flash +#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of Flash +#define SYSCTL_DC0_FLASHSZ_192K 0x0000005F // 192 KB of Flash +#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of Flash + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC1 register. +// +//***************************************************************************** +#define SYSCTL_DC1_WDT1 0x10000000 // Watchdog Timer1 Present +#define SYSCTL_DC1_CAN1 0x02000000 // CAN Module 1 Present +#define SYSCTL_DC1_CAN0 0x01000000 // CAN Module 0 Present +#define SYSCTL_DC1_PWM1 0x00200000 // PWM Module 1 Present +#define SYSCTL_DC1_PWM0 0x00100000 // PWM Module 0 Present +#define SYSCTL_DC1_ADC1 0x00020000 // ADC Module 1 Present +#define SYSCTL_DC1_ADC0 0x00010000 // ADC Module 0 Present +#define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 // System Clock Divider +#define SYSCTL_DC1_MINSYSDIV_80 0x00002000 // Specifies an 80-MHz CPU clock + // with a PLL divider of 2.5 +#define SYSCTL_DC1_MINSYSDIV_50 0x00003000 // Specifies a 50-MHz CPU clock + // with a PLL divider of 4 +#define SYSCTL_DC1_MINSYSDIV_40 0x00004000 // Specifies a 40-MHz CPU clock + // with a PLL divider of 5 +#define SYSCTL_DC1_MINSYSDIV_25 0x00007000 // Specifies a 25-MHz clock with a + // PLL divider of 8 +#define SYSCTL_DC1_MINSYSDIV_20 0x00009000 // Specifies a 20-MHz clock with a + // PLL divider of 10 +#define SYSCTL_DC1_ADC1SPD_M 0x00000C00 // Max ADC1 Speed +#define SYSCTL_DC1_ADC1SPD_125K 0x00000000 // 125K samples/second +#define SYSCTL_DC1_ADC1SPD_250K 0x00000400 // 250K samples/second +#define SYSCTL_DC1_ADC1SPD_500K 0x00000800 // 500K samples/second +#define SYSCTL_DC1_ADC1SPD_1M 0x00000C00 // 1M samples/second +#define SYSCTL_DC1_ADC0SPD_M 0x00000300 // Max ADC0 Speed +#define SYSCTL_DC1_ADC0SPD_125K 0x00000000 // 125K samples/second +#define SYSCTL_DC1_ADC0SPD_250K 0x00000100 // 250K samples/second +#define SYSCTL_DC1_ADC0SPD_500K 0x00000200 // 500K samples/second +#define SYSCTL_DC1_ADC0SPD_1M 0x00000300 // 1M samples/second +#define SYSCTL_DC1_MPU 0x00000080 // MPU Present +#define SYSCTL_DC1_HIB 0x00000040 // Hibernation Module Present +#define SYSCTL_DC1_TEMP 0x00000020 // Temp Sensor Present +#define SYSCTL_DC1_PLL 0x00000010 // PLL Present +#define SYSCTL_DC1_WDT0 0x00000008 // Watchdog Timer 0 Present +#define SYSCTL_DC1_SWO 0x00000004 // SWO Trace Port Present +#define SYSCTL_DC1_SWD 0x00000002 // SWD Present +#define SYSCTL_DC1_JTAG 0x00000001 // JTAG Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC2 register. +// +//***************************************************************************** +#define SYSCTL_DC2_EPI0 0x40000000 // EPI Module 0 Present +#define SYSCTL_DC2_I2S0 0x10000000 // I2S Module 0 Present +#define SYSCTL_DC2_COMP2 0x04000000 // Analog Comparator 2 Present +#define SYSCTL_DC2_COMP1 0x02000000 // Analog Comparator 1 Present +#define SYSCTL_DC2_COMP0 0x01000000 // Analog Comparator 0 Present +#define SYSCTL_DC2_TIMER3 0x00080000 // Timer Module 3 Present +#define SYSCTL_DC2_TIMER2 0x00040000 // Timer Module 2 Present +#define SYSCTL_DC2_TIMER1 0x00020000 // Timer Module 1 Present +#define SYSCTL_DC2_TIMER0 0x00010000 // Timer Module 0 Present +#define SYSCTL_DC2_I2C1HS 0x00008000 // I2C Module 1 Speed +#define SYSCTL_DC2_I2C1 0x00004000 // I2C Module 1 Present +#define SYSCTL_DC2_I2C0HS 0x00002000 // I2C Module 0 Speed +#define SYSCTL_DC2_I2C0 0x00001000 // I2C Module 0 Present +#define SYSCTL_DC2_QEI1 0x00000200 // QEI Module 1 Present +#define SYSCTL_DC2_QEI0 0x00000100 // QEI Module 0 Present +#define SYSCTL_DC2_SSI1 0x00000020 // SSI Module 1 Present +#define SYSCTL_DC2_SSI0 0x00000010 // SSI Module 0 Present +#define SYSCTL_DC2_UART2 0x00000004 // UART Module 2 Present +#define SYSCTL_DC2_UART1 0x00000002 // UART Module 1 Present +#define SYSCTL_DC2_UART0 0x00000001 // UART Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC3 register. +// +//***************************************************************************** +#define SYSCTL_DC3_32KHZ 0x80000000 // 32KHz Input Clock Available +#define SYSCTL_DC3_CCP5 0x20000000 // T2CCP1 Pin Present +#define SYSCTL_DC3_CCP4 0x10000000 // T2CCP0 Pin Present +#define SYSCTL_DC3_CCP3 0x08000000 // T1CCP1 Pin Present +#define SYSCTL_DC3_CCP2 0x04000000 // T1CCP0 Pin Present +#define SYSCTL_DC3_CCP1 0x02000000 // T0CCP1 Pin Present +#define SYSCTL_DC3_CCP0 0x01000000 // T0CCP0 Pin Present +#define SYSCTL_DC3_ADC0AIN7 0x00800000 // ADC Module 0 AIN7 Pin Present +#define SYSCTL_DC3_ADC0AIN6 0x00400000 // ADC Module 0 AIN6 Pin Present +#define SYSCTL_DC3_ADC0AIN5 0x00200000 // ADC Module 0 AIN5 Pin Present +#define SYSCTL_DC3_ADC0AIN4 0x00100000 // ADC Module 0 AIN4 Pin Present +#define SYSCTL_DC3_ADC0AIN3 0x00080000 // ADC Module 0 AIN3 Pin Present +#define SYSCTL_DC3_ADC0AIN2 0x00040000 // ADC Module 0 AIN2 Pin Present +#define SYSCTL_DC3_ADC0AIN1 0x00020000 // ADC Module 0 AIN1 Pin Present +#define SYSCTL_DC3_ADC0AIN0 0x00010000 // ADC Module 0 AIN0 Pin Present +#define SYSCTL_DC3_PWMFAULT 0x00008000 // PWM Fault Pin Present +#define SYSCTL_DC3_C2O 0x00004000 // C2o Pin Present +#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ Pin Present +#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- Pin Present +#define SYSCTL_DC3_C1O 0x00000800 // C1o Pin Present +#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ Pin Present +#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- Pin Present +#define SYSCTL_DC3_C0O 0x00000100 // C0o Pin Present +#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ Pin Present +#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- Pin Present +#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 Pin Present +#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 Pin Present +#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 Pin Present +#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 Pin Present +#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 Pin Present +#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 Pin Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC4 register. +// +//***************************************************************************** +#define SYSCTL_DC4_EPHY0 0x40000000 // Ethernet PHY Layer 0 Present +#define SYSCTL_DC4_EMAC0 0x10000000 // Ethernet MAC Layer 0 Present +#define SYSCTL_DC4_E1588 0x01000000 // 1588 Capable +#define SYSCTL_DC4_PICAL 0x00040000 // PIOSC Calibrate +#define SYSCTL_DC4_CCP7 0x00008000 // T3CCP1 Pin Present +#define SYSCTL_DC4_CCP6 0x00004000 // T3CCP0 Pin Present +#define SYSCTL_DC4_UDMA 0x00002000 // Micro-DMA Module Present +#define SYSCTL_DC4_ROM 0x00001000 // Internal Code ROM Present +#define SYSCTL_DC4_GPIOJ 0x00000100 // GPIO Port J Present +#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO Port H Present +#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO Port G Present +#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO Port F Present +#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO Port E Present +#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO Port D Present +#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO Port C Present +#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO Port B Present +#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO Port A Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC5 register. +// +//***************************************************************************** +#define SYSCTL_DC5_PWMFAULT3 0x08000000 // PWM Fault 3 Pin Present +#define SYSCTL_DC5_PWMFAULT2 0x04000000 // PWM Fault 2 Pin Present +#define SYSCTL_DC5_PWMFAULT1 0x02000000 // PWM Fault 1 Pin Present +#define SYSCTL_DC5_PWMFAULT0 0x01000000 // PWM Fault 0 Pin Present +#define SYSCTL_DC5_PWMEFLT 0x00200000 // PWM Extended Fault Active +#define SYSCTL_DC5_PWMESYNC 0x00100000 // PWM Extended SYNC Active +#define SYSCTL_DC5_PWM7 0x00000080 // PWM7 Pin Present +#define SYSCTL_DC5_PWM6 0x00000040 // PWM6 Pin Present +#define SYSCTL_DC5_PWM5 0x00000020 // PWM5 Pin Present +#define SYSCTL_DC5_PWM4 0x00000010 // PWM4 Pin Present +#define SYSCTL_DC5_PWM3 0x00000008 // PWM3 Pin Present +#define SYSCTL_DC5_PWM2 0x00000004 // PWM2 Pin Present +#define SYSCTL_DC5_PWM1 0x00000002 // PWM1 Pin Present +#define SYSCTL_DC5_PWM0 0x00000001 // PWM0 Pin Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC6 register. +// +//***************************************************************************** +#define SYSCTL_DC6_USB0PHY 0x00000010 // USB Module 0 PHY Present +#define SYSCTL_DC6_USB0_M 0x00000003 // USB Module 0 Present +#define SYSCTL_DC6_USB0_DEV 0x00000001 // USB0 is Device Only +#define SYSCTL_DC6_USB0_HOSTDEV 0x00000002 // USB is Device or Host +#define SYSCTL_DC6_USB0_OTG 0x00000003 // USB0 is OTG + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC7 register. +// +//***************************************************************************** +#define SYSCTL_DC7_DMACH30 0x40000000 // DMA Channel 30 +#define SYSCTL_DC7_DMACH29 0x20000000 // DMA Channel 29 +#define SYSCTL_DC7_DMACH28 0x10000000 // DMA Channel 28 +#define SYSCTL_DC7_DMACH27 0x08000000 // DMA Channel 27 +#define SYSCTL_DC7_DMACH26 0x04000000 // DMA Channel 26 +#define SYSCTL_DC7_DMACH25 0x02000000 // DMA Channel 25 +#define SYSCTL_DC7_DMACH24 0x01000000 // DMA Channel 24 +#define SYSCTL_DC7_DMACH23 0x00800000 // DMA Channel 23 +#define SYSCTL_DC7_DMACH22 0x00400000 // DMA Channel 22 +#define SYSCTL_DC7_DMACH21 0x00200000 // DMA Channel 21 +#define SYSCTL_DC7_DMACH20 0x00100000 // DMA Channel 20 +#define SYSCTL_DC7_DMACH19 0x00080000 // DMA Channel 19 +#define SYSCTL_DC7_DMACH18 0x00040000 // DMA Channel 18 +#define SYSCTL_DC7_DMACH17 0x00020000 // DMA Channel 17 +#define SYSCTL_DC7_DMACH16 0x00010000 // DMA Channel 16 +#define SYSCTL_DC7_DMACH15 0x00008000 // DMA Channel 15 +#define SYSCTL_DC7_DMACH14 0x00004000 // DMA Channel 14 +#define SYSCTL_DC7_DMACH13 0x00002000 // DMA Channel 13 +#define SYSCTL_DC7_DMACH12 0x00001000 // DMA Channel 12 +#define SYSCTL_DC7_DMACH11 0x00000800 // DMA Channel 11 +#define SYSCTL_DC7_DMACH10 0x00000400 // DMA Channel 10 +#define SYSCTL_DC7_DMACH9 0x00000200 // DMA Channel 9 +#define SYSCTL_DC7_DMACH8 0x00000100 // DMA Channel 8 +#define SYSCTL_DC7_DMACH7 0x00000080 // DMA Channel 7 +#define SYSCTL_DC7_DMACH6 0x00000040 // DMA Channel 6 +#define SYSCTL_DC7_DMACH5 0x00000020 // DMA Channel 5 +#define SYSCTL_DC7_DMACH4 0x00000010 // DMA Channel 4 +#define SYSCTL_DC7_DMACH3 0x00000008 // DMA Channel 3 +#define SYSCTL_DC7_DMACH2 0x00000004 // DMA Channel 2 +#define SYSCTL_DC7_DMACH1 0x00000002 // DMA Channel 1 +#define SYSCTL_DC7_DMACH0 0x00000001 // DMA Channel 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC8 register. +// +//***************************************************************************** +#define SYSCTL_DC8_ADC1AIN15 0x80000000 // ADC Module 1 AIN15 Pin Present +#define SYSCTL_DC8_ADC1AIN14 0x40000000 // ADC Module 1 AIN14 Pin Present +#define SYSCTL_DC8_ADC1AIN13 0x20000000 // ADC Module 1 AIN13 Pin Present +#define SYSCTL_DC8_ADC1AIN12 0x10000000 // ADC Module 1 AIN12 Pin Present +#define SYSCTL_DC8_ADC1AIN11 0x08000000 // ADC Module 1 AIN11 Pin Present +#define SYSCTL_DC8_ADC1AIN10 0x04000000 // ADC Module 1 AIN10 Pin Present +#define SYSCTL_DC8_ADC1AIN9 0x02000000 // ADC Module 1 AIN9 Pin Present +#define SYSCTL_DC8_ADC1AIN8 0x01000000 // ADC Module 1 AIN8 Pin Present +#define SYSCTL_DC8_ADC1AIN7 0x00800000 // ADC Module 1 AIN7 Pin Present +#define SYSCTL_DC8_ADC1AIN6 0x00400000 // ADC Module 1 AIN6 Pin Present +#define SYSCTL_DC8_ADC1AIN5 0x00200000 // ADC Module 1 AIN5 Pin Present +#define SYSCTL_DC8_ADC1AIN4 0x00100000 // ADC Module 1 AIN4 Pin Present +#define SYSCTL_DC8_ADC1AIN3 0x00080000 // ADC Module 1 AIN3 Pin Present +#define SYSCTL_DC8_ADC1AIN2 0x00040000 // ADC Module 1 AIN2 Pin Present +#define SYSCTL_DC8_ADC1AIN1 0x00020000 // ADC Module 1 AIN1 Pin Present +#define SYSCTL_DC8_ADC1AIN0 0x00010000 // ADC Module 1 AIN0 Pin Present +#define SYSCTL_DC8_ADC0AIN15 0x00008000 // ADC Module 0 AIN15 Pin Present +#define SYSCTL_DC8_ADC0AIN14 0x00004000 // ADC Module 0 AIN14 Pin Present +#define SYSCTL_DC8_ADC0AIN13 0x00002000 // ADC Module 0 AIN13 Pin Present +#define SYSCTL_DC8_ADC0AIN12 0x00001000 // ADC Module 0 AIN12 Pin Present +#define SYSCTL_DC8_ADC0AIN11 0x00000800 // ADC Module 0 AIN11 Pin Present +#define SYSCTL_DC8_ADC0AIN10 0x00000400 // ADC Module 0 AIN10 Pin Present +#define SYSCTL_DC8_ADC0AIN9 0x00000200 // ADC Module 0 AIN9 Pin Present +#define SYSCTL_DC8_ADC0AIN8 0x00000100 // ADC Module 0 AIN8 Pin Present +#define SYSCTL_DC8_ADC0AIN7 0x00000080 // ADC Module 0 AIN7 Pin Present +#define SYSCTL_DC8_ADC0AIN6 0x00000040 // ADC Module 0 AIN6 Pin Present +#define SYSCTL_DC8_ADC0AIN5 0x00000020 // ADC Module 0 AIN5 Pin Present +#define SYSCTL_DC8_ADC0AIN4 0x00000010 // ADC Module 0 AIN4 Pin Present +#define SYSCTL_DC8_ADC0AIN3 0x00000008 // ADC Module 0 AIN3 Pin Present +#define SYSCTL_DC8_ADC0AIN2 0x00000004 // ADC Module 0 AIN2 Pin Present +#define SYSCTL_DC8_ADC0AIN1 0x00000002 // ADC Module 0 AIN1 Pin Present +#define SYSCTL_DC8_ADC0AIN0 0x00000001 // ADC Module 0 AIN0 Pin Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PBORCTL register. +// +//***************************************************************************** +#define SYSCTL_PBORCTL_BOR0 0x00000004 // VDD under BOR0 Event Action +#define SYSCTL_PBORCTL_BOR1 0x00000002 // VDD under BOR1 Event Action + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PTBOCTL register. +// +//***************************************************************************** +#define SYSCTL_PTBOCTL_VDDA_UBOR_M \ + 0x00000300 // VDDA under BOR Event Action +#define SYSCTL_PTBOCTL_VDDA_UBOR_NONE \ + 0x00000000 // No Action +#define SYSCTL_PTBOCTL_VDDA_UBOR_SYSINT \ + 0x00000100 // System control interrupt +#define SYSCTL_PTBOCTL_VDDA_UBOR_NMI \ + 0x00000200 // NMI +#define SYSCTL_PTBOCTL_VDDA_UBOR_RST \ + 0x00000300 // Reset +#define SYSCTL_PTBOCTL_VDD_UBOR_M \ + 0x00000003 // VDD (VDDS) under BOR Event + // Action +#define SYSCTL_PTBOCTL_VDD_UBOR_NONE \ + 0x00000000 // No Action +#define SYSCTL_PTBOCTL_VDD_UBOR_SYSINT \ + 0x00000001 // System control interrupt +#define SYSCTL_PTBOCTL_VDD_UBOR_NMI \ + 0x00000002 // NMI +#define SYSCTL_PTBOCTL_VDD_UBOR_RST \ + 0x00000003 // Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCR0 register. +// +//***************************************************************************** +#define SYSCTL_SRCR0_WDT1 0x10000000 // WDT1 Reset Control +#define SYSCTL_SRCR0_CAN1 0x02000000 // CAN1 Reset Control +#define SYSCTL_SRCR0_CAN0 0x01000000 // CAN0 Reset Control +#define SYSCTL_SRCR0_PWM0 0x00100000 // PWM Reset Control +#define SYSCTL_SRCR0_ADC1 0x00020000 // ADC1 Reset Control +#define SYSCTL_SRCR0_ADC0 0x00010000 // ADC0 Reset Control +#define SYSCTL_SRCR0_HIB 0x00000040 // HIB Reset Control +#define SYSCTL_SRCR0_WDT0 0x00000008 // WDT0 Reset Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCR1 register. +// +//***************************************************************************** +#define SYSCTL_SRCR1_COMP2 0x04000000 // Analog Comp 2 Reset Control +#define SYSCTL_SRCR1_COMP1 0x02000000 // Analog Comp 1 Reset Control +#define SYSCTL_SRCR1_COMP0 0x01000000 // Analog Comp 0 Reset Control +#define SYSCTL_SRCR1_TIMER3 0x00080000 // Timer 3 Reset Control +#define SYSCTL_SRCR1_TIMER2 0x00040000 // Timer 2 Reset Control +#define SYSCTL_SRCR1_TIMER1 0x00020000 // Timer 1 Reset Control +#define SYSCTL_SRCR1_TIMER0 0x00010000 // Timer 0 Reset Control +#define SYSCTL_SRCR1_I2C1 0x00004000 // I2C1 Reset Control +#define SYSCTL_SRCR1_I2C0 0x00001000 // I2C0 Reset Control +#define SYSCTL_SRCR1_QEI1 0x00000200 // QEI1 Reset Control +#define SYSCTL_SRCR1_QEI0 0x00000100 // QEI0 Reset Control +#define SYSCTL_SRCR1_SSI1 0x00000020 // SSI1 Reset Control +#define SYSCTL_SRCR1_SSI0 0x00000010 // SSI0 Reset Control +#define SYSCTL_SRCR1_UART2 0x00000004 // UART2 Reset Control +#define SYSCTL_SRCR1_UART1 0x00000002 // UART1 Reset Control +#define SYSCTL_SRCR1_UART0 0x00000001 // UART0 Reset Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCR2 register. +// +//***************************************************************************** +#define SYSCTL_SRCR2_USB0 0x00010000 // USB0 Reset Control +#define SYSCTL_SRCR2_UDMA 0x00002000 // Micro-DMA Reset Control +#define SYSCTL_SRCR2_GPIOJ 0x00000100 // Port J Reset Control +#define SYSCTL_SRCR2_GPIOH 0x00000080 // Port H Reset Control +#define SYSCTL_SRCR2_GPIOG 0x00000040 // Port G Reset Control +#define SYSCTL_SRCR2_GPIOF 0x00000020 // Port F Reset Control +#define SYSCTL_SRCR2_GPIOE 0x00000010 // Port E Reset Control +#define SYSCTL_SRCR2_GPIOD 0x00000008 // Port D Reset Control +#define SYSCTL_SRCR2_GPIOC 0x00000004 // Port C Reset Control +#define SYSCTL_SRCR2_GPIOB 0x00000002 // Port B Reset Control +#define SYSCTL_SRCR2_GPIOA 0x00000001 // Port A Reset Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RIS register. +// +//***************************************************************************** +#define SYSCTL_RIS_BOR0RIS 0x00000800 // VDD under BOR0 Raw Interrupt + // Status +#define SYSCTL_RIS_VDDARIS 0x00000400 // VDDA Power OK Event Raw + // Interrupt Status +#define SYSCTL_RIS_MOSCPUPRIS 0x00000100 // MOSC Power Up Raw Interrupt + // Status +#define SYSCTL_RIS_USBPLLLRIS 0x00000080 // USB PLL Lock Raw Interrupt + // Status +#define SYSCTL_RIS_PLLLRIS 0x00000040 // PLL Lock Raw Interrupt Status +#define SYSCTL_RIS_MOFRIS 0x00000008 // Main Oscillator Failure Raw + // Interrupt Status +#define SYSCTL_RIS_BOR1RIS 0x00000002 // VDD under BOR1 Raw Interrupt + // Status +#define SYSCTL_RIS_BORRIS 0x00000002 // Brown-Out Reset Raw Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_IMC register. +// +//***************************************************************************** +#define SYSCTL_IMC_BOR0IM 0x00000800 // VDD under BOR0 Interrupt Mask +#define SYSCTL_IMC_VDDAIM 0x00000400 // VDDA Power OK Interrupt Mask +#define SYSCTL_IMC_MOSCPUPIM 0x00000100 // MOSC Power Up Interrupt Mask +#define SYSCTL_IMC_USBPLLLIM 0x00000080 // USB PLL Lock Interrupt Mask +#define SYSCTL_IMC_PLLLIM 0x00000040 // PLL Lock Interrupt Mask +#define SYSCTL_IMC_MOFIM 0x00000008 // Main Oscillator Failure + // Interrupt Mask +#define SYSCTL_IMC_BORIM 0x00000002 // Brown-Out Reset Interrupt Mask +#define SYSCTL_IMC_BOR1IM 0x00000002 // VDD under BOR1 Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_MISC register. +// +//***************************************************************************** +#define SYSCTL_MISC_BOR0MIS 0x00000800 // VDD under BOR0 Masked Interrupt + // Status +#define SYSCTL_MISC_VDDAMIS 0x00000400 // VDDA Power OK Masked Interrupt + // Status +#define SYSCTL_MISC_MOSCPUPMIS 0x00000100 // MOSC Power Up Masked Interrupt + // Status +#define SYSCTL_MISC_USBPLLLMIS 0x00000080 // USB PLL Lock Masked Interrupt + // Status +#define SYSCTL_MISC_PLLLMIS 0x00000040 // PLL Lock Masked Interrupt Status +#define SYSCTL_MISC_MOFMIS 0x00000008 // Main Oscillator Failure Masked + // Interrupt Status +#define SYSCTL_MISC_BORMIS 0x00000002 // BOR Masked Interrupt Status +#define SYSCTL_MISC_BOR1MIS 0x00000002 // VDD under BOR1 Masked Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RESC register. +// +//***************************************************************************** +#define SYSCTL_RESC_MOSCFAIL 0x00010000 // MOSC Failure Reset +#define SYSCTL_RESC_HSSR 0x00001000 // HSSR Reset +#define SYSCTL_RESC_WDT1 0x00000020 // Watchdog Timer 1 Reset +#define SYSCTL_RESC_SW 0x00000010 // Software Reset +#define SYSCTL_RESC_WDT0 0x00000008 // Watchdog Timer 0 Reset +#define SYSCTL_RESC_BOR 0x00000004 // Brown-Out Reset +#define SYSCTL_RESC_POR 0x00000002 // Power-On Reset +#define SYSCTL_RESC_EXT 0x00000001 // External Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PWRTC register. +// +//***************************************************************************** +#define SYSCTL_PWRTC_VDDA_UBOR 0x00000010 // VDDA Under BOR Status +#define SYSCTL_PWRTC_VDD_UBOR 0x00000001 // VDD Under BOR Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCC register. +// +//***************************************************************************** +#define SYSCTL_RCC_ACG 0x08000000 // Auto Clock Gating +#define SYSCTL_RCC_SYSDIV_M 0x07800000 // System Clock Divisor +#define SYSCTL_RCC_USESYSDIV 0x00400000 // Enable System Clock Divider +#define SYSCTL_RCC_USEPWMDIV 0x00100000 // Enable PWM Clock Divisor +#define SYSCTL_RCC_PWMDIV_M 0x000E0000 // PWM Unit Clock Divisor +#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2 +#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4 +#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8 +#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16 +#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32 +#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64 +#define SYSCTL_RCC_PWRDN 0x00002000 // PLL Power Down +#define SYSCTL_RCC_BYPASS 0x00000800 // PLL Bypass +#define SYSCTL_RCC_XTAL_M 0x000007C0 // Crystal Value +#define SYSCTL_RCC_XTAL_4MHZ 0x00000180 // 4 MHz +#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // 4.096 MHz +#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // 4.9152 MHz +#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // 5 MHz +#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // 5.12 MHz +#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // 6 MHz +#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // 6.144 MHz +#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // 7.3728 MHz +#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // 8 MHz +#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // 8.192 MHz +#define SYSCTL_RCC_XTAL_10MHZ 0x00000400 // 10 MHz +#define SYSCTL_RCC_XTAL_12MHZ 0x00000440 // 12 MHz +#define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480 // 12.288 MHz +#define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0 // 13.56 MHz +#define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500 // 14.31818 MHz +#define SYSCTL_RCC_XTAL_16MHZ 0x00000540 // 16 MHz +#define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580 // 16.384 MHz +#define SYSCTL_RCC_XTAL_18MHZ 0x000005C0 // 18.0 MHz (USB) +#define SYSCTL_RCC_XTAL_20MHZ 0x00000600 // 20.0 MHz (USB) +#define SYSCTL_RCC_XTAL_24MHZ 0x00000640 // 24.0 MHz (USB) +#define SYSCTL_RCC_XTAL_25MHZ 0x00000680 // 25.0 MHz (USB) +#define SYSCTL_RCC_OSCSRC_M 0x00000030 // Oscillator Source +#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // MOSC +#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // IOSC +#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // IOSC/4 +#define SYSCTL_RCC_OSCSRC_30 0x00000030 // LFIOSC +#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main Oscillator Disable +#define SYSCTL_RCC_SYSDIV_S 23 +#define SYSCTL_RCC_XTAL_S 6 // Shift to the XTAL field + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_NMIC register. +// +//***************************************************************************** +#define SYSCTL_NMIC_MOSCFAIL 0x00010000 // MOSC Failure NMI +#define SYSCTL_NMIC_TAMPER 0x00000200 // Tamper Event NMI +#define SYSCTL_NMIC_WDT1 0x00000020 // Watch Dog Timer (WDT) 1 NMI +#define SYSCTL_NMIC_WDT0 0x00000008 // Watch Dog Timer (WDT) 0 NMI +#define SYSCTL_NMIC_POWER 0x00000004 // Power/Brown Out Event NMI +#define SYSCTL_NMIC_EXTERNAL 0x00000001 // External Pin NMI + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_GPIOHBCTL +// register. +// +//***************************************************************************** +#define SYSCTL_GPIOHBCTL_PORTJ 0x00000100 // Port J Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTH 0x00000080 // Port H Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTG 0x00000040 // Port G Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTF 0x00000020 // Port F Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTE 0x00000010 // Port E Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTD 0x00000008 // Port D Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTC 0x00000004 // Port C Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTB 0x00000002 // Port B Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTA 0x00000001 // Port A Advanced High-Performance + // Bus + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCC2 register. +// +//***************************************************************************** +#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2 +#define SYSCTL_RCC2_DIV400 0x40000000 // Divide PLL as 400 MHz vs. 200 + // MHz +#define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 // System Clock Divisor 2 +#define SYSCTL_RCC2_SYSDIV2LSB 0x00400000 // Additional LSB for SYSDIV2 +#define SYSCTL_RCC2_USBPWRDN 0x00004000 // Power-Down USB PLL +#define SYSCTL_RCC2_PWRDN2 0x00002000 // Power-Down PLL 2 +#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL Bypass 2 +#define SYSCTL_RCC2_OSCSRC2_M 0x00000070 // Oscillator Source 2 +#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // MOSC +#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // PIOSC +#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // PIOSC/4 +#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // LFIOSC +#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // 32.768 kHz +#define SYSCTL_RCC2_SYSDIV2_S 23 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_MOSCCTL register. +// +//***************************************************************************** +#define SYSCTL_MOSCCTL_OSCRNG 0x00000010 // Oscillator Range +#define SYSCTL_MOSCCTL_PWRDN 0x00000008 // Power Down +#define SYSCTL_MOSCCTL_NOXTAL 0x00000004 // No Crystal Connected +#define SYSCTL_MOSCCTL_MOSCIM 0x00000002 // MOSC Failure Action +#define SYSCTL_MOSCCTL_CVAL 0x00000001 // Clock Validation for MOSC + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RSCLKCFG +// register. +// +//***************************************************************************** +#define SYSCTL_RSCLKCFG_MEMTIMU 0x80000000 // Memory Timing Register Update +#define SYSCTL_RSCLKCFG_NEWFREQ 0x40000000 // New PLLFREQ Accept +#define SYSCTL_RSCLKCFG_ACG 0x20000000 // Auto Clock Gating +#define SYSCTL_RSCLKCFG_USEPLL 0x10000000 // Use PLL +#define SYSCTL_RSCLKCFG_PLLSRC_M \ + 0x0F000000 // PLL Source +#define SYSCTL_RSCLKCFG_PLLSRC_PIOSC \ + 0x00000000 // PIOSC is PLL input clock source +#define SYSCTL_RSCLKCFG_PLLSRC_MOSC \ + 0x03000000 // MOSC is the PLL input clock + // source +#define SYSCTL_RSCLKCFG_OSCSRC_M \ + 0x00F00000 // Oscillator Source +#define SYSCTL_RSCLKCFG_OSCSRC_PIOSC \ + 0x00000000 // PIOSC is oscillator source +#define SYSCTL_RSCLKCFG_OSCSRC_LFIOSC \ + 0x00200000 // LFIOSC is oscillator source +#define SYSCTL_RSCLKCFG_OSCSRC_MOSC \ + 0x00300000 // MOSC is oscillator source +#define SYSCTL_RSCLKCFG_OSCSRC_RTC \ + 0x00400000 // Hibernation Module RTC + // Oscillator (RTCOSC) +#define SYSCTL_RSCLKCFG_OSYSDIV_M \ + 0x000FFC00 // Oscillator System Clock Divisor +#define SYSCTL_RSCLKCFG_PSYSDIV_M \ + 0x000003FF // PLL System Clock Divisor +#define SYSCTL_RSCLKCFG_OSYSDIV_S \ + 10 +#define SYSCTL_RSCLKCFG_PSYSDIV_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_MEMTIM0 register. +// +//***************************************************************************** +#define SYSCTL_MEMTIM0_EBCHT_M 0x03C00000 // EEPROM Clock High Time +#define SYSCTL_MEMTIM0_EBCHT_0_5 \ + 0x00000000 // 1/2 system clock period +#define SYSCTL_MEMTIM0_EBCHT_1 0x00400000 // 1 system clock period +#define SYSCTL_MEMTIM0_EBCHT_1_5 \ + 0x00800000 // 1.5 system clock periods +#define SYSCTL_MEMTIM0_EBCHT_2 0x00C00000 // 2 system clock periods +#define SYSCTL_MEMTIM0_EBCHT_2_5 \ + 0x01000000 // 2.5 system clock periods +#define SYSCTL_MEMTIM0_EBCHT_3 0x01400000 // 3 system clock periods +#define SYSCTL_MEMTIM0_EBCHT_3_5 \ + 0x01800000 // 3.5 system clock periods +#define SYSCTL_MEMTIM0_EBCHT_4 0x01C00000 // 4 system clock periods +#define SYSCTL_MEMTIM0_EBCHT_4_5 \ + 0x02000000 // 4.5 system clock periods +#define SYSCTL_MEMTIM0_EBCE 0x00200000 // EEPROM Bank Clock Edge +#define SYSCTL_MEMTIM0_MB1 0x00100010 // Must be one +#define SYSCTL_MEMTIM0_EWS_M 0x000F0000 // EEPROM Wait States +#define SYSCTL_MEMTIM0_FBCHT_M 0x000003C0 // Flash Bank Clock High Time +#define SYSCTL_MEMTIM0_FBCHT_0_5 \ + 0x00000000 // 1/2 system clock period +#define SYSCTL_MEMTIM0_FBCHT_1 0x00000040 // 1 system clock period +#define SYSCTL_MEMTIM0_FBCHT_1_5 \ + 0x00000080 // 1.5 system clock periods +#define SYSCTL_MEMTIM0_FBCHT_2 0x000000C0 // 2 system clock periods +#define SYSCTL_MEMTIM0_FBCHT_2_5 \ + 0x00000100 // 2.5 system clock periods +#define SYSCTL_MEMTIM0_FBCHT_3 0x00000140 // 3 system clock periods +#define SYSCTL_MEMTIM0_FBCHT_3_5 \ + 0x00000180 // 3.5 system clock periods +#define SYSCTL_MEMTIM0_FBCHT_4 0x000001C0 // 4 system clock periods +#define SYSCTL_MEMTIM0_FBCHT_4_5 \ + 0x00000200 // 4.5 system clock periods +#define SYSCTL_MEMTIM0_FBCE 0x00000020 // Flash Bank Clock Edge +#define SYSCTL_MEMTIM0_FWS_M 0x0000000F // Flash Wait State +#define SYSCTL_MEMTIM0_EWS_S 16 +#define SYSCTL_MEMTIM0_FWS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGC0 register. +// +//***************************************************************************** +#define SYSCTL_RCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control +#define SYSCTL_RCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control +#define SYSCTL_RCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control +#define SYSCTL_RCGC0_PWM0 0x00100000 // PWM Clock Gating Control +#define SYSCTL_RCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control +#define SYSCTL_RCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control +#define SYSCTL_RCGC0_ADC1SPD_M 0x00000C00 // ADC1 Sample Speed +#define SYSCTL_RCGC0_ADC1SPD_125K \ + 0x00000000 // 125K samples/second +#define SYSCTL_RCGC0_ADC1SPD_250K \ + 0x00000400 // 250K samples/second +#define SYSCTL_RCGC0_ADC1SPD_500K \ + 0x00000800 // 500K samples/second +#define SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00 // 1M samples/second +#define SYSCTL_RCGC0_ADC0SPD_M 0x00000300 // ADC0 Sample Speed +#define SYSCTL_RCGC0_ADC0SPD_125K \ + 0x00000000 // 125K samples/second +#define SYSCTL_RCGC0_ADC0SPD_250K \ + 0x00000100 // 250K samples/second +#define SYSCTL_RCGC0_ADC0SPD_500K \ + 0x00000200 // 500K samples/second +#define SYSCTL_RCGC0_ADC0SPD_1M 0x00000300 // 1M samples/second +#define SYSCTL_RCGC0_HIB 0x00000040 // HIB Clock Gating Control +#define SYSCTL_RCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGC1 register. +// +//***************************************************************************** +#define SYSCTL_RCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating +#define SYSCTL_RCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating +#define SYSCTL_RCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating +#define SYSCTL_RCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control +#define SYSCTL_RCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control +#define SYSCTL_RCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control +#define SYSCTL_RCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control +#define SYSCTL_RCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control +#define SYSCTL_RCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control +#define SYSCTL_RCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control +#define SYSCTL_RCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control +#define SYSCTL_RCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control +#define SYSCTL_RCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control +#define SYSCTL_RCGC1_UART2 0x00000004 // UART2 Clock Gating Control +#define SYSCTL_RCGC1_UART1 0x00000002 // UART1 Clock Gating Control +#define SYSCTL_RCGC1_UART0 0x00000001 // UART0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGC2 register. +// +//***************************************************************************** +#define SYSCTL_RCGC2_USB0 0x00010000 // USB0 Clock Gating Control +#define SYSCTL_RCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control +#define SYSCTL_RCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control +#define SYSCTL_RCGC2_GPIOH 0x00000080 // Port H Clock Gating Control +#define SYSCTL_RCGC2_GPIOG 0x00000040 // Port G Clock Gating Control +#define SYSCTL_RCGC2_GPIOF 0x00000020 // Port F Clock Gating Control +#define SYSCTL_RCGC2_GPIOE 0x00000010 // Port E Clock Gating Control +#define SYSCTL_RCGC2_GPIOD 0x00000008 // Port D Clock Gating Control +#define SYSCTL_RCGC2_GPIOC 0x00000004 // Port C Clock Gating Control +#define SYSCTL_RCGC2_GPIOB 0x00000002 // Port B Clock Gating Control +#define SYSCTL_RCGC2_GPIOA 0x00000001 // Port A Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGC0 register. +// +//***************************************************************************** +#define SYSCTL_SCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control +#define SYSCTL_SCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control +#define SYSCTL_SCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control +#define SYSCTL_SCGC0_PWM0 0x00100000 // PWM Clock Gating Control +#define SYSCTL_SCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control +#define SYSCTL_SCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control +#define SYSCTL_SCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed +#define SYSCTL_SCGC0_HIB 0x00000040 // HIB Clock Gating Control +#define SYSCTL_SCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGC1 register. +// +//***************************************************************************** +#define SYSCTL_SCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating +#define SYSCTL_SCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating +#define SYSCTL_SCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating +#define SYSCTL_SCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control +#define SYSCTL_SCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control +#define SYSCTL_SCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control +#define SYSCTL_SCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control +#define SYSCTL_SCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control +#define SYSCTL_SCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control +#define SYSCTL_SCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control +#define SYSCTL_SCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control +#define SYSCTL_SCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control +#define SYSCTL_SCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control +#define SYSCTL_SCGC1_UART2 0x00000004 // UART2 Clock Gating Control +#define SYSCTL_SCGC1_UART1 0x00000002 // UART1 Clock Gating Control +#define SYSCTL_SCGC1_UART0 0x00000001 // UART0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGC2 register. +// +//***************************************************************************** +#define SYSCTL_SCGC2_USB0 0x00010000 // USB0 Clock Gating Control +#define SYSCTL_SCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control +#define SYSCTL_SCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control +#define SYSCTL_SCGC2_GPIOH 0x00000080 // Port H Clock Gating Control +#define SYSCTL_SCGC2_GPIOG 0x00000040 // Port G Clock Gating Control +#define SYSCTL_SCGC2_GPIOF 0x00000020 // Port F Clock Gating Control +#define SYSCTL_SCGC2_GPIOE 0x00000010 // Port E Clock Gating Control +#define SYSCTL_SCGC2_GPIOD 0x00000008 // Port D Clock Gating Control +#define SYSCTL_SCGC2_GPIOC 0x00000004 // Port C Clock Gating Control +#define SYSCTL_SCGC2_GPIOB 0x00000002 // Port B Clock Gating Control +#define SYSCTL_SCGC2_GPIOA 0x00000001 // Port A Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGC0 register. +// +//***************************************************************************** +#define SYSCTL_DCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control +#define SYSCTL_DCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control +#define SYSCTL_DCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control +#define SYSCTL_DCGC0_PWM0 0x00100000 // PWM Clock Gating Control +#define SYSCTL_DCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control +#define SYSCTL_DCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control +#define SYSCTL_DCGC0_HIB 0x00000040 // HIB Clock Gating Control +#define SYSCTL_DCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGC1 register. +// +//***************************************************************************** +#define SYSCTL_DCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating +#define SYSCTL_DCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating +#define SYSCTL_DCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating +#define SYSCTL_DCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control +#define SYSCTL_DCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control +#define SYSCTL_DCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control +#define SYSCTL_DCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control +#define SYSCTL_DCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control +#define SYSCTL_DCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control +#define SYSCTL_DCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control +#define SYSCTL_DCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control +#define SYSCTL_DCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control +#define SYSCTL_DCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control +#define SYSCTL_DCGC1_UART2 0x00000004 // UART2 Clock Gating Control +#define SYSCTL_DCGC1_UART1 0x00000002 // UART1 Clock Gating Control +#define SYSCTL_DCGC1_UART0 0x00000001 // UART0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGC2 register. +// +//***************************************************************************** +#define SYSCTL_DCGC2_USB0 0x00010000 // USB0 Clock Gating Control +#define SYSCTL_DCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control +#define SYSCTL_DCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control +#define SYSCTL_DCGC2_GPIOH 0x00000080 // Port H Clock Gating Control +#define SYSCTL_DCGC2_GPIOG 0x00000040 // Port G Clock Gating Control +#define SYSCTL_DCGC2_GPIOF 0x00000020 // Port F Clock Gating Control +#define SYSCTL_DCGC2_GPIOE 0x00000010 // Port E Clock Gating Control +#define SYSCTL_DCGC2_GPIOD 0x00000008 // Port D Clock Gating Control +#define SYSCTL_DCGC2_GPIOC 0x00000004 // Port C Clock Gating Control +#define SYSCTL_DCGC2_GPIOB 0x00000002 // Port B Clock Gating Control +#define SYSCTL_DCGC2_GPIOA 0x00000001 // Port A Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_ALTCLKCFG +// register. +// +//***************************************************************************** +#define SYSCTL_ALTCLKCFG_ALTCLK_M \ + 0x0000000F // Alternate Clock Source +#define SYSCTL_ALTCLKCFG_ALTCLK_PIOSC \ + 0x00000000 // PIOSC +#define SYSCTL_ALTCLKCFG_ALTCLK_RTCOSC \ + 0x00000003 // Hibernation Module Real-time + // clock output (RTCOSC) +#define SYSCTL_ALTCLKCFG_ALTCLK_LFIOSC \ + 0x00000004 // Low-frequency internal + // oscillator (LFIOSC) + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG +// register. +// +//***************************************************************************** +#define SYSCTL_DSLPCLKCFG_D_M 0x1F800000 // Divider Field Override +#define SYSCTL_DSLPCLKCFG_O_M 0x00000070 // Clock Source +#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // MOSC +#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // PIOSC +#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // LFIOSC +#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // 32.768 kHz +#define SYSCTL_DSLPCLKCFG_PIOSCPD \ + 0x00000002 // PIOSC Power Down Request +#define SYSCTL_DSLPCLKCFG_D_S 23 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DSCLKCFG +// register. +// +//***************************************************************************** +#define SYSCTL_DSCLKCFG_PIOSCPD 0x80000000 // PIOSC Power Down +#define SYSCTL_DSCLKCFG_MOSCDPD 0x40000000 // MOSC Disable Power Down +#define SYSCTL_DSCLKCFG_DSOSCSRC_M \ + 0x00F00000 // Deep Sleep Oscillator Source +#define SYSCTL_DSCLKCFG_DSOSCSRC_PIOSC \ + 0x00000000 // PIOSC +#define SYSCTL_DSCLKCFG_DSOSCSRC_LFIOSC \ + 0x00200000 // LFIOSC +#define SYSCTL_DSCLKCFG_DSOSCSRC_MOSC \ + 0x00300000 // MOSC +#define SYSCTL_DSCLKCFG_DSOSCSRC_RTC \ + 0x00400000 // Hibernation Module RTCOSC +#define SYSCTL_DSCLKCFG_DSSYSDIV_M \ + 0x000003FF // Deep Sleep Clock Divisor +#define SYSCTL_DSCLKCFG_DSSYSDIV_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DIVSCLK register. +// +//***************************************************************************** +#define SYSCTL_DIVSCLK_EN 0x80000000 // DIVSCLK Enable +#define SYSCTL_DIVSCLK_SRC_M 0x00030000 // Clock Source +#define SYSCTL_DIVSCLK_SRC_SYSCLK \ + 0x00000000 // System Clock +#define SYSCTL_DIVSCLK_SRC_PIOSC \ + 0x00010000 // PIOSC +#define SYSCTL_DIVSCLK_SRC_MOSC 0x00020000 // MOSC +#define SYSCTL_DIVSCLK_DIV_M 0x000000FF // Divisor Value +#define SYSCTL_DIVSCLK_DIV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SYSPROP register. +// +//***************************************************************************** +#define SYSCTL_SYSPROP_FPU 0x00000001 // FPU Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PIOSCCAL +// register. +// +//***************************************************************************** +#define SYSCTL_PIOSCCAL_UTEN 0x80000000 // Use User Trim Value +#define SYSCTL_PIOSCCAL_CAL 0x00000200 // Start Calibration +#define SYSCTL_PIOSCCAL_UPDATE 0x00000100 // Update Trim +#define SYSCTL_PIOSCCAL_UT_M 0x0000007F // User Trim Value +#define SYSCTL_PIOSCCAL_UT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PIOSCSTAT +// register. +// +//***************************************************************************** +#define SYSCTL_PIOSCSTAT_DT_M 0x007F0000 // Default Trim Value +#define SYSCTL_PIOSCSTAT_CR_M 0x00000300 // Calibration Result +#define SYSCTL_PIOSCSTAT_CRNONE 0x00000000 // Calibration has not been + // attempted +#define SYSCTL_PIOSCSTAT_CRPASS 0x00000100 // The last calibration operation + // completed to meet 1% accuracy +#define SYSCTL_PIOSCSTAT_CRFAIL 0x00000200 // The last calibration operation + // failed to meet 1% accuracy +#define SYSCTL_PIOSCSTAT_CT_M 0x0000007F // Calibration Trim Value +#define SYSCTL_PIOSCSTAT_DT_S 16 +#define SYSCTL_PIOSCSTAT_CT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PLLFREQ0 +// register. +// +//***************************************************************************** +#define SYSCTL_PLLFREQ0_PLLPWR 0x00800000 // PLL Power +#define SYSCTL_PLLFREQ0_MFRAC_M 0x000FFC00 // PLL M Fractional Value +#define SYSCTL_PLLFREQ0_MINT_M 0x000003FF // PLL M Integer Value +#define SYSCTL_PLLFREQ0_MFRAC_S 10 +#define SYSCTL_PLLFREQ0_MINT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PLLFREQ1 +// register. +// +//***************************************************************************** +#define SYSCTL_PLLFREQ1_Q_M 0x00001F00 // PLL Q Value +#define SYSCTL_PLLFREQ1_N_M 0x0000001F // PLL N Value +#define SYSCTL_PLLFREQ1_Q_S 8 +#define SYSCTL_PLLFREQ1_N_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PLLSTAT register. +// +//***************************************************************************** +#define SYSCTL_PLLSTAT_LOCK 0x00000001 // PLL Lock + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SLPPWRCFG +// register. +// +//***************************************************************************** +#define SYSCTL_SLPPWRCFG_FLASHPM_M \ + 0x00000030 // Flash Power Modes +#define SYSCTL_SLPPWRCFG_FLASHPM_NRM \ + 0x00000000 // Active Mode +#define SYSCTL_SLPPWRCFG_FLASHPM_SLP \ + 0x00000020 // Low Power Mode +#define SYSCTL_SLPPWRCFG_SRAMPM_M \ + 0x00000003 // SRAM Power Modes +#define SYSCTL_SLPPWRCFG_SRAMPM_NRM \ + 0x00000000 // Active Mode +#define SYSCTL_SLPPWRCFG_SRAMPM_SBY \ + 0x00000001 // Standby Mode +#define SYSCTL_SLPPWRCFG_SRAMPM_LP \ + 0x00000003 // Low Power Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DSLPPWRCFG +// register. +// +//***************************************************************************** +#define SYSCTL_DSLPPWRCFG_LDOSM 0x00000200 // LDO Sleep Mode +#define SYSCTL_DSLPPWRCFG_TSPD 0x00000100 // Temperature Sense Power Down +#define SYSCTL_DSLPPWRCFG_FLASHPM_M \ + 0x00000030 // Flash Power Modes +#define SYSCTL_DSLPPWRCFG_FLASHPM_NRM \ + 0x00000000 // Active Mode +#define SYSCTL_DSLPPWRCFG_FLASHPM_SLP \ + 0x00000020 // Low Power Mode +#define SYSCTL_DSLPPWRCFG_SRAMPM_M \ + 0x00000003 // SRAM Power Modes +#define SYSCTL_DSLPPWRCFG_SRAMPM_NRM \ + 0x00000000 // Active Mode +#define SYSCTL_DSLPPWRCFG_SRAMPM_SBY \ + 0x00000001 // Standby Mode +#define SYSCTL_DSLPPWRCFG_SRAMPM_LP \ + 0x00000003 // Low Power Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC9 register. +// +//***************************************************************************** +#define SYSCTL_DC9_ADC1DC7 0x00800000 // ADC1 DC7 Present +#define SYSCTL_DC9_ADC1DC6 0x00400000 // ADC1 DC6 Present +#define SYSCTL_DC9_ADC1DC5 0x00200000 // ADC1 DC5 Present +#define SYSCTL_DC9_ADC1DC4 0x00100000 // ADC1 DC4 Present +#define SYSCTL_DC9_ADC1DC3 0x00080000 // ADC1 DC3 Present +#define SYSCTL_DC9_ADC1DC2 0x00040000 // ADC1 DC2 Present +#define SYSCTL_DC9_ADC1DC1 0x00020000 // ADC1 DC1 Present +#define SYSCTL_DC9_ADC1DC0 0x00010000 // ADC1 DC0 Present +#define SYSCTL_DC9_ADC0DC7 0x00000080 // ADC0 DC7 Present +#define SYSCTL_DC9_ADC0DC6 0x00000040 // ADC0 DC6 Present +#define SYSCTL_DC9_ADC0DC5 0x00000020 // ADC0 DC5 Present +#define SYSCTL_DC9_ADC0DC4 0x00000010 // ADC0 DC4 Present +#define SYSCTL_DC9_ADC0DC3 0x00000008 // ADC0 DC3 Present +#define SYSCTL_DC9_ADC0DC2 0x00000004 // ADC0 DC2 Present +#define SYSCTL_DC9_ADC0DC1 0x00000002 // ADC0 DC1 Present +#define SYSCTL_DC9_ADC0DC0 0x00000001 // ADC0 DC0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_NVMSTAT register. +// +//***************************************************************************** +#define SYSCTL_NVMSTAT_FWB 0x00000001 // 32 Word Flash Write Buffer + // Available + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_LDOSPCTL +// register. +// +//***************************************************************************** +#define SYSCTL_LDOSPCTL_VADJEN 0x80000000 // Voltage Adjust Enable +#define SYSCTL_LDOSPCTL_VLDO_M 0x000000FF // LDO Output Voltage +#define SYSCTL_LDOSPCTL_VLDO_0_90V \ + 0x00000012 // 0.90 V +#define SYSCTL_LDOSPCTL_VLDO_0_95V \ + 0x00000013 // 0.95 V +#define SYSCTL_LDOSPCTL_VLDO_1_00V \ + 0x00000014 // 1.00 V +#define SYSCTL_LDOSPCTL_VLDO_1_05V \ + 0x00000015 // 1.05 V +#define SYSCTL_LDOSPCTL_VLDO_1_10V \ + 0x00000016 // 1.10 V +#define SYSCTL_LDOSPCTL_VLDO_1_15V \ + 0x00000017 // 1.15 V +#define SYSCTL_LDOSPCTL_VLDO_1_20V \ + 0x00000018 // 1.20 V + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_LDODPCTL +// register. +// +//***************************************************************************** +#define SYSCTL_LDODPCTL_VADJEN 0x80000000 // Voltage Adjust Enable +#define SYSCTL_LDODPCTL_VLDO_M 0x000000FF // LDO Output Voltage +#define SYSCTL_LDODPCTL_VLDO_0_90V \ + 0x00000012 // 0.90 V +#define SYSCTL_LDODPCTL_VLDO_0_95V \ + 0x00000013 // 0.95 V +#define SYSCTL_LDODPCTL_VLDO_1_00V \ + 0x00000014 // 1.00 V +#define SYSCTL_LDODPCTL_VLDO_1_05V \ + 0x00000015 // 1.05 V +#define SYSCTL_LDODPCTL_VLDO_1_10V \ + 0x00000016 // 1.10 V +#define SYSCTL_LDODPCTL_VLDO_1_15V \ + 0x00000017 // 1.15 V +#define SYSCTL_LDODPCTL_VLDO_1_20V \ + 0x00000018 // 1.20 V +#define SYSCTL_LDODPCTL_VLDO_1_25V \ + 0x00000019 // 1.25 V +#define SYSCTL_LDODPCTL_VLDO_1_30V \ + 0x0000001A // 1.30 V +#define SYSCTL_LDODPCTL_VLDO_1_35V \ + 0x0000001B // 1.35 V + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RESBEHAVCTL +// register. +// +//***************************************************************************** +#define SYSCTL_RESBEHAVCTL_WDOG1_M \ + 0x000000C0 // Watchdog 1 Reset Operation +#define SYSCTL_RESBEHAVCTL_WDOG1_SYSRST \ + 0x00000080 // Watchdog 1 issues a system + // reset. The application starts + // within 10 us +#define SYSCTL_RESBEHAVCTL_WDOG1_POR \ + 0x000000C0 // Watchdog 1 issues a simulated + // POR sequence. Application starts + // less than 500 us after + // deassertion (Default) +#define SYSCTL_RESBEHAVCTL_WDOG0_M \ + 0x00000030 // Watchdog 0 Reset Operation +#define SYSCTL_RESBEHAVCTL_WDOG0_SYSRST \ + 0x00000020 // Watchdog 0 issues a system + // reset. The application starts + // within 10 us +#define SYSCTL_RESBEHAVCTL_WDOG0_POR \ + 0x00000030 // Watchdog 0 issues a simulated + // POR sequence. Application starts + // less than 500 us after + // deassertion (Default) +#define SYSCTL_RESBEHAVCTL_BOR_M \ + 0x0000000C // BOR Reset operation +#define SYSCTL_RESBEHAVCTL_BOR_SYSRST \ + 0x00000008 // Brown Out Reset issues system + // reset. The application starts + // within 10 us +#define SYSCTL_RESBEHAVCTL_BOR_POR \ + 0x0000000C // Brown Out Reset issues a + // simulated POR sequence. The + // application starts less than 500 + // us after deassertion (Default) +#define SYSCTL_RESBEHAVCTL_EXTRES_M \ + 0x00000003 // External RST Pin Operation +#define SYSCTL_RESBEHAVCTL_EXTRES_SYSRST \ + 0x00000002 // External RST assertion issues a + // system reset. The application + // starts within 10 us +#define SYSCTL_RESBEHAVCTL_EXTRES_POR \ + 0x00000003 // External RST assertion issues a + // simulated POR sequence. + // Application starts less than 500 + // us after deassertion (Default) + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_HSSR register. +// +//***************************************************************************** +#define SYSCTL_HSSR_KEY_M 0xFF000000 // Write Key +#define SYSCTL_HSSR_CDOFF_M 0x00FFFFFF // Command Descriptor Pointer +#define SYSCTL_HSSR_KEY_S 24 +#define SYSCTL_HSSR_CDOFF_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_USBPDS register. +// +//***************************************************************************** +#define SYSCTL_USBPDS_MEMSTAT_M 0x0000000C // Memory Array Power Status +#define SYSCTL_USBPDS_MEMSTAT_OFF \ + 0x00000000 // Array OFF +#define SYSCTL_USBPDS_MEMSTAT_RETAIN \ + 0x00000004 // SRAM Retention +#define SYSCTL_USBPDS_MEMSTAT_ON \ + 0x0000000C // Array On +#define SYSCTL_USBPDS_PWRSTAT_M 0x00000003 // Power Domain Status +#define SYSCTL_USBPDS_PWRSTAT_OFF \ + 0x00000000 // OFF +#define SYSCTL_USBPDS_PWRSTAT_ON \ + 0x00000003 // ON + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_USBMPC register. +// +//***************************************************************************** +#define SYSCTL_USBMPC_PWRCTL_M 0x00000003 // Memory Array Power Control +#define SYSCTL_USBMPC_PWRCTL_OFF \ + 0x00000000 // Array OFF +#define SYSCTL_USBMPC_PWRCTL_RETAIN \ + 0x00000001 // SRAM Retention +#define SYSCTL_USBMPC_PWRCTL_ON 0x00000003 // Array On + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_EMACPDS register. +// +//***************************************************************************** +#define SYSCTL_EMACPDS_MEMSTAT_M \ + 0x0000000C // Memory Array Power Status +#define SYSCTL_EMACPDS_MEMSTAT_OFF \ + 0x00000000 // Array OFF +#define SYSCTL_EMACPDS_MEMSTAT_ON \ + 0x0000000C // Array On +#define SYSCTL_EMACPDS_PWRSTAT_M \ + 0x00000003 // Power Domain Status +#define SYSCTL_EMACPDS_PWRSTAT_OFF \ + 0x00000000 // OFF +#define SYSCTL_EMACPDS_PWRSTAT_ON \ + 0x00000003 // ON + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_EMACMPC register. +// +//***************************************************************************** +#define SYSCTL_EMACMPC_PWRCTL_M 0x00000003 // Memory Array Power Control +#define SYSCTL_EMACMPC_PWRCTL_OFF \ + 0x00000000 // Array OFF +#define SYSCTL_EMACMPC_PWRCTL_ON \ + 0x00000003 // Array On + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_LCDMPC register. +// +//***************************************************************************** +#define SYSCTL_LCDMPC_PWRCTL_M 0x00000003 // Memory Array Power Control +#define SYSCTL_LCDMPC_PWRCTL_OFF \ + 0x00000000 // Array OFF +#define SYSCTL_LCDMPC_PWRCTL_ON 0x00000003 // Array On + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPWD register. +// +//***************************************************************************** +#define SYSCTL_PPWD_P1 0x00000002 // Watchdog Timer 1 Present +#define SYSCTL_PPWD_P0 0x00000001 // Watchdog Timer 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPTIMER register. +// +//***************************************************************************** +#define SYSCTL_PPTIMER_P7 0x00000080 // 16/32-Bit General-Purpose Timer + // 7 Present +#define SYSCTL_PPTIMER_P6 0x00000040 // 16/32-Bit General-Purpose Timer + // 6 Present +#define SYSCTL_PPTIMER_P5 0x00000020 // 16/32-Bit General-Purpose Timer + // 5 Present +#define SYSCTL_PPTIMER_P4 0x00000010 // 16/32-Bit General-Purpose Timer + // 4 Present +#define SYSCTL_PPTIMER_P3 0x00000008 // 16/32-Bit General-Purpose Timer + // 3 Present +#define SYSCTL_PPTIMER_P2 0x00000004 // 16/32-Bit General-Purpose Timer + // 2 Present +#define SYSCTL_PPTIMER_P1 0x00000002 // 16/32-Bit General-Purpose Timer + // 1 Present +#define SYSCTL_PPTIMER_P0 0x00000001 // 16/32-Bit General-Purpose Timer + // 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPGPIO register. +// +//***************************************************************************** +#define SYSCTL_PPGPIO_P17 0x00020000 // GPIO Port T Present +#define SYSCTL_PPGPIO_P16 0x00010000 // GPIO Port S Present +#define SYSCTL_PPGPIO_P15 0x00008000 // GPIO Port R Present +#define SYSCTL_PPGPIO_P14 0x00004000 // GPIO Port Q Present +#define SYSCTL_PPGPIO_P13 0x00002000 // GPIO Port P Present +#define SYSCTL_PPGPIO_P12 0x00001000 // GPIO Port N Present +#define SYSCTL_PPGPIO_P11 0x00000800 // GPIO Port M Present +#define SYSCTL_PPGPIO_P10 0x00000400 // GPIO Port L Present +#define SYSCTL_PPGPIO_P9 0x00000200 // GPIO Port K Present +#define SYSCTL_PPGPIO_P8 0x00000100 // GPIO Port J Present +#define SYSCTL_PPGPIO_P7 0x00000080 // GPIO Port H Present +#define SYSCTL_PPGPIO_P6 0x00000040 // GPIO Port G Present +#define SYSCTL_PPGPIO_P5 0x00000020 // GPIO Port F Present +#define SYSCTL_PPGPIO_P4 0x00000010 // GPIO Port E Present +#define SYSCTL_PPGPIO_P3 0x00000008 // GPIO Port D Present +#define SYSCTL_PPGPIO_P2 0x00000004 // GPIO Port C Present +#define SYSCTL_PPGPIO_P1 0x00000002 // GPIO Port B Present +#define SYSCTL_PPGPIO_P0 0x00000001 // GPIO Port A Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPDMA register. +// +//***************************************************************************** +#define SYSCTL_PPDMA_P0 0x00000001 // uDMA Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPEPI register. +// +//***************************************************************************** +#define SYSCTL_PPEPI_P0 0x00000001 // EPI Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPHIB register. +// +//***************************************************************************** +#define SYSCTL_PPHIB_P0 0x00000001 // Hibernation Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPUART register. +// +//***************************************************************************** +#define SYSCTL_PPUART_P7 0x00000080 // UART Module 7 Present +#define SYSCTL_PPUART_P6 0x00000040 // UART Module 6 Present +#define SYSCTL_PPUART_P5 0x00000020 // UART Module 5 Present +#define SYSCTL_PPUART_P4 0x00000010 // UART Module 4 Present +#define SYSCTL_PPUART_P3 0x00000008 // UART Module 3 Present +#define SYSCTL_PPUART_P2 0x00000004 // UART Module 2 Present +#define SYSCTL_PPUART_P1 0x00000002 // UART Module 1 Present +#define SYSCTL_PPUART_P0 0x00000001 // UART Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPSSI register. +// +//***************************************************************************** +#define SYSCTL_PPSSI_P3 0x00000008 // SSI Module 3 Present +#define SYSCTL_PPSSI_P2 0x00000004 // SSI Module 2 Present +#define SYSCTL_PPSSI_P1 0x00000002 // SSI Module 1 Present +#define SYSCTL_PPSSI_P0 0x00000001 // SSI Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPI2C register. +// +//***************************************************************************** +#define SYSCTL_PPI2C_P9 0x00000200 // I2C Module 9 Present +#define SYSCTL_PPI2C_P8 0x00000100 // I2C Module 8 Present +#define SYSCTL_PPI2C_P7 0x00000080 // I2C Module 7 Present +#define SYSCTL_PPI2C_P6 0x00000040 // I2C Module 6 Present +#define SYSCTL_PPI2C_P5 0x00000020 // I2C Module 5 Present +#define SYSCTL_PPI2C_P4 0x00000010 // I2C Module 4 Present +#define SYSCTL_PPI2C_P3 0x00000008 // I2C Module 3 Present +#define SYSCTL_PPI2C_P2 0x00000004 // I2C Module 2 Present +#define SYSCTL_PPI2C_P1 0x00000002 // I2C Module 1 Present +#define SYSCTL_PPI2C_P0 0x00000001 // I2C Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPUSB register. +// +//***************************************************************************** +#define SYSCTL_PPUSB_P0 0x00000001 // USB Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPEPHY register. +// +//***************************************************************************** +#define SYSCTL_PPEPHY_P0 0x00000001 // Ethernet PHY Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPCAN register. +// +//***************************************************************************** +#define SYSCTL_PPCAN_P1 0x00000002 // CAN Module 1 Present +#define SYSCTL_PPCAN_P0 0x00000001 // CAN Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPADC register. +// +//***************************************************************************** +#define SYSCTL_PPADC_P1 0x00000002 // ADC Module 1 Present +#define SYSCTL_PPADC_P0 0x00000001 // ADC Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPACMP register. +// +//***************************************************************************** +#define SYSCTL_PPACMP_P0 0x00000001 // Analog Comparator Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPPWM register. +// +//***************************************************************************** +#define SYSCTL_PPPWM_P1 0x00000002 // PWM Module 1 Present +#define SYSCTL_PPPWM_P0 0x00000001 // PWM Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPQEI register. +// +//***************************************************************************** +#define SYSCTL_PPQEI_P1 0x00000002 // QEI Module 1 Present +#define SYSCTL_PPQEI_P0 0x00000001 // QEI Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPLPC register. +// +//***************************************************************************** +#define SYSCTL_PPLPC_P0 0x00000001 // LPC Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPPECI register. +// +//***************************************************************************** +#define SYSCTL_PPPECI_P0 0x00000001 // PECI Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPFAN register. +// +//***************************************************************************** +#define SYSCTL_PPFAN_P0 0x00000001 // FAN Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPEEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_PPEEPROM_P0 0x00000001 // EEPROM Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_PPWTIMER_P5 0x00000020 // 32/64-Bit Wide General-Purpose + // Timer 5 Present +#define SYSCTL_PPWTIMER_P4 0x00000010 // 32/64-Bit Wide General-Purpose + // Timer 4 Present +#define SYSCTL_PPWTIMER_P3 0x00000008 // 32/64-Bit Wide General-Purpose + // Timer 3 Present +#define SYSCTL_PPWTIMER_P2 0x00000004 // 32/64-Bit Wide General-Purpose + // Timer 2 Present +#define SYSCTL_PPWTIMER_P1 0x00000002 // 32/64-Bit Wide General-Purpose + // Timer 1 Present +#define SYSCTL_PPWTIMER_P0 0x00000001 // 32/64-Bit Wide General-Purpose + // Timer 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPRTS register. +// +//***************************************************************************** +#define SYSCTL_PPRTS_P0 0x00000001 // RTS Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPCCM register. +// +//***************************************************************************** +#define SYSCTL_PPCCM_P0 0x00000001 // CRC and Cryptographic Modules + // Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPLCD register. +// +//***************************************************************************** +#define SYSCTL_PPLCD_P0 0x00000001 // LCD Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPOWIRE register. +// +//***************************************************************************** +#define SYSCTL_PPOWIRE_P0 0x00000001 // 1-Wire Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPEMAC register. +// +//***************************************************************************** +#define SYSCTL_PPEMAC_P0 0x00000001 // Ethernet Controller Module + // Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPHIM register. +// +//***************************************************************************** +#define SYSCTL_PPHIM_P0 0x00000001 // HIM Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRWD register. +// +//***************************************************************************** +#define SYSCTL_SRWD_R1 0x00000002 // Watchdog Timer 1 Software Reset +#define SYSCTL_SRWD_R0 0x00000001 // Watchdog Timer 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRTIMER register. +// +//***************************************************************************** +#define SYSCTL_SRTIMER_R7 0x00000080 // 16/32-Bit General-Purpose Timer + // 7 Software Reset +#define SYSCTL_SRTIMER_R6 0x00000040 // 16/32-Bit General-Purpose Timer + // 6 Software Reset +#define SYSCTL_SRTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer + // 5 Software Reset +#define SYSCTL_SRTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer + // 4 Software Reset +#define SYSCTL_SRTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer + // 3 Software Reset +#define SYSCTL_SRTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer + // 2 Software Reset +#define SYSCTL_SRTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer + // 1 Software Reset +#define SYSCTL_SRTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer + // 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRGPIO register. +// +//***************************************************************************** +#define SYSCTL_SRGPIO_R17 0x00020000 // GPIO Port T Software Reset +#define SYSCTL_SRGPIO_R16 0x00010000 // GPIO Port S Software Reset +#define SYSCTL_SRGPIO_R15 0x00008000 // GPIO Port R Software Reset +#define SYSCTL_SRGPIO_R14 0x00004000 // GPIO Port Q Software Reset +#define SYSCTL_SRGPIO_R13 0x00002000 // GPIO Port P Software Reset +#define SYSCTL_SRGPIO_R12 0x00001000 // GPIO Port N Software Reset +#define SYSCTL_SRGPIO_R11 0x00000800 // GPIO Port M Software Reset +#define SYSCTL_SRGPIO_R10 0x00000400 // GPIO Port L Software Reset +#define SYSCTL_SRGPIO_R9 0x00000200 // GPIO Port K Software Reset +#define SYSCTL_SRGPIO_R8 0x00000100 // GPIO Port J Software Reset +#define SYSCTL_SRGPIO_R7 0x00000080 // GPIO Port H Software Reset +#define SYSCTL_SRGPIO_R6 0x00000040 // GPIO Port G Software Reset +#define SYSCTL_SRGPIO_R5 0x00000020 // GPIO Port F Software Reset +#define SYSCTL_SRGPIO_R4 0x00000010 // GPIO Port E Software Reset +#define SYSCTL_SRGPIO_R3 0x00000008 // GPIO Port D Software Reset +#define SYSCTL_SRGPIO_R2 0x00000004 // GPIO Port C Software Reset +#define SYSCTL_SRGPIO_R1 0x00000002 // GPIO Port B Software Reset +#define SYSCTL_SRGPIO_R0 0x00000001 // GPIO Port A Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRDMA register. +// +//***************************************************************************** +#define SYSCTL_SRDMA_R0 0x00000001 // uDMA Module Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SREPI register. +// +//***************************************************************************** +#define SYSCTL_SREPI_R0 0x00000001 // EPI Module Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRHIB register. +// +//***************************************************************************** +#define SYSCTL_SRHIB_R0 0x00000001 // Hibernation Module Software + // Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRUART register. +// +//***************************************************************************** +#define SYSCTL_SRUART_R7 0x00000080 // UART Module 7 Software Reset +#define SYSCTL_SRUART_R6 0x00000040 // UART Module 6 Software Reset +#define SYSCTL_SRUART_R5 0x00000020 // UART Module 5 Software Reset +#define SYSCTL_SRUART_R4 0x00000010 // UART Module 4 Software Reset +#define SYSCTL_SRUART_R3 0x00000008 // UART Module 3 Software Reset +#define SYSCTL_SRUART_R2 0x00000004 // UART Module 2 Software Reset +#define SYSCTL_SRUART_R1 0x00000002 // UART Module 1 Software Reset +#define SYSCTL_SRUART_R0 0x00000001 // UART Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRSSI register. +// +//***************************************************************************** +#define SYSCTL_SRSSI_R3 0x00000008 // SSI Module 3 Software Reset +#define SYSCTL_SRSSI_R2 0x00000004 // SSI Module 2 Software Reset +#define SYSCTL_SRSSI_R1 0x00000002 // SSI Module 1 Software Reset +#define SYSCTL_SRSSI_R0 0x00000001 // SSI Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRI2C register. +// +//***************************************************************************** +#define SYSCTL_SRI2C_R9 0x00000200 // I2C Module 9 Software Reset +#define SYSCTL_SRI2C_R8 0x00000100 // I2C Module 8 Software Reset +#define SYSCTL_SRI2C_R7 0x00000080 // I2C Module 7 Software Reset +#define SYSCTL_SRI2C_R6 0x00000040 // I2C Module 6 Software Reset +#define SYSCTL_SRI2C_R5 0x00000020 // I2C Module 5 Software Reset +#define SYSCTL_SRI2C_R4 0x00000010 // I2C Module 4 Software Reset +#define SYSCTL_SRI2C_R3 0x00000008 // I2C Module 3 Software Reset +#define SYSCTL_SRI2C_R2 0x00000004 // I2C Module 2 Software Reset +#define SYSCTL_SRI2C_R1 0x00000002 // I2C Module 1 Software Reset +#define SYSCTL_SRI2C_R0 0x00000001 // I2C Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRUSB register. +// +//***************************************************************************** +#define SYSCTL_SRUSB_R0 0x00000001 // USB Module Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SREPHY register. +// +//***************************************************************************** +#define SYSCTL_SREPHY_R0 0x00000001 // Ethernet PHY Module Software + // Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCAN register. +// +//***************************************************************************** +#define SYSCTL_SRCAN_R1 0x00000002 // CAN Module 1 Software Reset +#define SYSCTL_SRCAN_R0 0x00000001 // CAN Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRADC register. +// +//***************************************************************************** +#define SYSCTL_SRADC_R1 0x00000002 // ADC Module 1 Software Reset +#define SYSCTL_SRADC_R0 0x00000001 // ADC Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRACMP register. +// +//***************************************************************************** +#define SYSCTL_SRACMP_R0 0x00000001 // Analog Comparator Module 0 + // Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRPWM register. +// +//***************************************************************************** +#define SYSCTL_SRPWM_R1 0x00000002 // PWM Module 1 Software Reset +#define SYSCTL_SRPWM_R0 0x00000001 // PWM Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRQEI register. +// +//***************************************************************************** +#define SYSCTL_SRQEI_R1 0x00000002 // QEI Module 1 Software Reset +#define SYSCTL_SRQEI_R0 0x00000001 // QEI Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SREEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_SREEPROM_R0 0x00000001 // EEPROM Module Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_SRWTIMER_R5 0x00000020 // 32/64-Bit Wide General-Purpose + // Timer 5 Software Reset +#define SYSCTL_SRWTIMER_R4 0x00000010 // 32/64-Bit Wide General-Purpose + // Timer 4 Software Reset +#define SYSCTL_SRWTIMER_R3 0x00000008 // 32/64-Bit Wide General-Purpose + // Timer 3 Software Reset +#define SYSCTL_SRWTIMER_R2 0x00000004 // 32/64-Bit Wide General-Purpose + // Timer 2 Software Reset +#define SYSCTL_SRWTIMER_R1 0x00000002 // 32/64-Bit Wide General-Purpose + // Timer 1 Software Reset +#define SYSCTL_SRWTIMER_R0 0x00000001 // 32/64-Bit Wide General-Purpose + // Timer 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCCM register. +// +//***************************************************************************** +#define SYSCTL_SRCCM_R0 0x00000001 // CRC and Cryptographic Modules + // Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRLCD register. +// +//***************************************************************************** +#define SYSCTL_SRLCD_R0 0x00000001 // LCD Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SROWIRE register. +// +//***************************************************************************** +#define SYSCTL_SROWIRE_R0 0x00000001 // 1-Wire Module Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SREMAC register. +// +//***************************************************************************** +#define SYSCTL_SREMAC_R0 0x00000001 // Ethernet Controller MAC Module 0 + // Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCWD register. +// +//***************************************************************************** +#define SYSCTL_RCGCWD_R1 0x00000002 // Watchdog Timer 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCWD_R0 0x00000001 // Watchdog Timer 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCTIMER_R7 0x00000080 // 16/32-Bit General-Purpose Timer + // 7 Run Mode Clock Gating Control +#define SYSCTL_RCGCTIMER_R6 0x00000040 // 16/32-Bit General-Purpose Timer + // 6 Run Mode Clock Gating Control +#define SYSCTL_RCGCTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer + // 5 Run Mode Clock Gating Control +#define SYSCTL_RCGCTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer + // 4 Run Mode Clock Gating Control +#define SYSCTL_RCGCTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer + // 3 Run Mode Clock Gating Control +#define SYSCTL_RCGCTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer + // 2 Run Mode Clock Gating Control +#define SYSCTL_RCGCTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer + // 1 Run Mode Clock Gating Control +#define SYSCTL_RCGCTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer + // 0 Run Mode Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCGPIO +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCGPIO_R17 0x00020000 // GPIO Port T Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R16 0x00010000 // GPIO Port S Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R15 0x00008000 // GPIO Port R Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R14 0x00004000 // GPIO Port Q Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R13 0x00002000 // GPIO Port P Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R12 0x00001000 // GPIO Port N Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R11 0x00000800 // GPIO Port M Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R10 0x00000400 // GPIO Port L Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R9 0x00000200 // GPIO Port K Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R8 0x00000100 // GPIO Port J Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R7 0x00000080 // GPIO Port H Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R6 0x00000040 // GPIO Port G Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R5 0x00000020 // GPIO Port F Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R4 0x00000010 // GPIO Port E Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R3 0x00000008 // GPIO Port D Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R2 0x00000004 // GPIO Port C Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R1 0x00000002 // GPIO Port B Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R0 0x00000001 // GPIO Port A Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCDMA register. +// +//***************************************************************************** +#define SYSCTL_RCGCDMA_R0 0x00000001 // uDMA Module Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCEPI register. +// +//***************************************************************************** +#define SYSCTL_RCGCEPI_R0 0x00000001 // EPI Module Run Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCHIB register. +// +//***************************************************************************** +#define SYSCTL_RCGCHIB_R0 0x00000001 // Hibernation Module Run Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCUART +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCUART_R7 0x00000080 // UART Module 7 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R6 0x00000040 // UART Module 6 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R5 0x00000020 // UART Module 5 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R4 0x00000010 // UART Module 4 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R3 0x00000008 // UART Module 3 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R2 0x00000004 // UART Module 2 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R1 0x00000002 // UART Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R0 0x00000001 // UART Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCSSI register. +// +//***************************************************************************** +#define SYSCTL_RCGCSSI_R3 0x00000008 // SSI Module 3 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCSSI_R2 0x00000004 // SSI Module 2 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCSSI_R1 0x00000002 // SSI Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCSSI_R0 0x00000001 // SSI Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCI2C register. +// +//***************************************************************************** +#define SYSCTL_RCGCI2C_R9 0x00000200 // I2C Module 9 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R8 0x00000100 // I2C Module 8 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R7 0x00000080 // I2C Module 7 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R6 0x00000040 // I2C Module 6 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R5 0x00000020 // I2C Module 5 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R4 0x00000010 // I2C Module 4 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R3 0x00000008 // I2C Module 3 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R2 0x00000004 // I2C Module 2 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R1 0x00000002 // I2C Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R0 0x00000001 // I2C Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCUSB register. +// +//***************************************************************************** +#define SYSCTL_RCGCUSB_R0 0x00000001 // USB Module Run Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCEPHY +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCEPHY_R0 0x00000001 // Ethernet PHY Module Run Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCCAN register. +// +//***************************************************************************** +#define SYSCTL_RCGCCAN_R1 0x00000002 // CAN Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCCAN_R0 0x00000001 // CAN Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCADC register. +// +//***************************************************************************** +#define SYSCTL_RCGCADC_R1 0x00000002 // ADC Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCADC_R0 0x00000001 // ADC Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCACMP +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCACMP_R0 0x00000001 // Analog Comparator Module 0 Run + // Mode Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCPWM register. +// +//***************************************************************************** +#define SYSCTL_RCGCPWM_R1 0x00000002 // PWM Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCPWM_R0 0x00000001 // PWM Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCQEI register. +// +//***************************************************************************** +#define SYSCTL_RCGCQEI_R1 0x00000002 // QEI Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCQEI_R0 0x00000001 // QEI Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCEEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCEEPROM_R0 0x00000001 // EEPROM Module Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCWTIMER_R5 0x00000020 // 32/64-Bit Wide General-Purpose + // Timer 5 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCWTIMER_R4 0x00000010 // 32/64-Bit Wide General-Purpose + // Timer 4 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCWTIMER_R3 0x00000008 // 32/64-Bit Wide General-Purpose + // Timer 3 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCWTIMER_R2 0x00000004 // 32/64-Bit Wide General-Purpose + // Timer 2 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCWTIMER_R1 0x00000002 // 32/64-Bit Wide General-Purpose + // Timer 1 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCWTIMER_R0 0x00000001 // 32/64-Bit Wide General-Purpose + // Timer 0 Run Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCCCM register. +// +//***************************************************************************** +#define SYSCTL_RCGCCCM_R0 0x00000001 // CRC and Cryptographic Modules + // Run Mode Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCLCD register. +// +//***************************************************************************** +#define SYSCTL_RCGCLCD_R0 0x00000001 // LCD Controller Module 0 Run Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCOWIRE +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCOWIRE_R0 0x00000001 // 1-Wire Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCEMAC +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCEMAC_R0 0x00000001 // Ethernet MAC Module 0 Run Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCWD register. +// +//***************************************************************************** +#define SYSCTL_SCGCWD_S1 0x00000002 // Watchdog Timer 1 Sleep Mode + // Clock Gating Control +#define SYSCTL_SCGCWD_S0 0x00000001 // Watchdog Timer 0 Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCTIMER_S7 0x00000080 // 16/32-Bit General-Purpose Timer + // 7 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S6 0x00000040 // 16/32-Bit General-Purpose Timer + // 6 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S5 0x00000020 // 16/32-Bit General-Purpose Timer + // 5 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S4 0x00000010 // 16/32-Bit General-Purpose Timer + // 4 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S3 0x00000008 // 16/32-Bit General-Purpose Timer + // 3 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S2 0x00000004 // 16/32-Bit General-Purpose Timer + // 2 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S1 0x00000002 // 16/32-Bit General-Purpose Timer + // 1 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S0 0x00000001 // 16/32-Bit General-Purpose Timer + // 0 Sleep Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCGPIO +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCGPIO_S17 0x00020000 // GPIO Port T Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S16 0x00010000 // GPIO Port S Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S15 0x00008000 // GPIO Port R Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S14 0x00004000 // GPIO Port Q Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S13 0x00002000 // GPIO Port P Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S12 0x00001000 // GPIO Port N Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S11 0x00000800 // GPIO Port M Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S10 0x00000400 // GPIO Port L Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S9 0x00000200 // GPIO Port K Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S8 0x00000100 // GPIO Port J Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S7 0x00000080 // GPIO Port H Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S6 0x00000040 // GPIO Port G Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S5 0x00000020 // GPIO Port F Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S4 0x00000010 // GPIO Port E Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S3 0x00000008 // GPIO Port D Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S2 0x00000004 // GPIO Port C Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S1 0x00000002 // GPIO Port B Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S0 0x00000001 // GPIO Port A Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCDMA register. +// +//***************************************************************************** +#define SYSCTL_SCGCDMA_S0 0x00000001 // uDMA Module Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCEPI register. +// +//***************************************************************************** +#define SYSCTL_SCGCEPI_S0 0x00000001 // EPI Module Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCHIB register. +// +//***************************************************************************** +#define SYSCTL_SCGCHIB_S0 0x00000001 // Hibernation Module Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCUART +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCUART_S7 0x00000080 // UART Module 7 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S6 0x00000040 // UART Module 6 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S5 0x00000020 // UART Module 5 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S4 0x00000010 // UART Module 4 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S3 0x00000008 // UART Module 3 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S2 0x00000004 // UART Module 2 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S1 0x00000002 // UART Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S0 0x00000001 // UART Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCSSI register. +// +//***************************************************************************** +#define SYSCTL_SCGCSSI_S3 0x00000008 // SSI Module 3 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCSSI_S2 0x00000004 // SSI Module 2 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCSSI_S1 0x00000002 // SSI Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCSSI_S0 0x00000001 // SSI Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCI2C register. +// +//***************************************************************************** +#define SYSCTL_SCGCI2C_S9 0x00000200 // I2C Module 9 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S8 0x00000100 // I2C Module 8 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S7 0x00000080 // I2C Module 7 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S6 0x00000040 // I2C Module 6 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S5 0x00000020 // I2C Module 5 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S4 0x00000010 // I2C Module 4 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S3 0x00000008 // I2C Module 3 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S2 0x00000004 // I2C Module 2 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S1 0x00000002 // I2C Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S0 0x00000001 // I2C Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCUSB register. +// +//***************************************************************************** +#define SYSCTL_SCGCUSB_S0 0x00000001 // USB Module Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCEPHY +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCEPHY_S0 0x00000001 // PHY Module Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCCAN register. +// +//***************************************************************************** +#define SYSCTL_SCGCCAN_S1 0x00000002 // CAN Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCCAN_S0 0x00000001 // CAN Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCADC register. +// +//***************************************************************************** +#define SYSCTL_SCGCADC_S1 0x00000002 // ADC Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCADC_S0 0x00000001 // ADC Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCACMP +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCACMP_S0 0x00000001 // Analog Comparator Module 0 Sleep + // Mode Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCPWM register. +// +//***************************************************************************** +#define SYSCTL_SCGCPWM_S1 0x00000002 // PWM Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCPWM_S0 0x00000001 // PWM Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCQEI register. +// +//***************************************************************************** +#define SYSCTL_SCGCQEI_S1 0x00000002 // QEI Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCQEI_S0 0x00000001 // QEI Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCEEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCEEPROM_S0 0x00000001 // EEPROM Module Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCWTIMER_S5 0x00000020 // 32/64-Bit Wide General-Purpose + // Timer 5 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCWTIMER_S4 0x00000010 // 32/64-Bit Wide General-Purpose + // Timer 4 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCWTIMER_S3 0x00000008 // 32/64-Bit Wide General-Purpose + // Timer 3 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCWTIMER_S2 0x00000004 // 32/64-Bit Wide General-Purpose + // Timer 2 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCWTIMER_S1 0x00000002 // 32/64-Bit Wide General-Purpose + // Timer 1 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCWTIMER_S0 0x00000001 // 32/64-Bit Wide General-Purpose + // Timer 0 Sleep Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCCCM register. +// +//***************************************************************************** +#define SYSCTL_SCGCCCM_S0 0x00000001 // CRC and Cryptographic Modules + // Sleep Mode Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCLCD register. +// +//***************************************************************************** +#define SYSCTL_SCGCLCD_S0 0x00000001 // LCD Controller Module 0 Sleep + // Mode Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCOWIRE +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCOWIRE_S0 0x00000001 // 1-Wire Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCEMAC +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCEMAC_S0 0x00000001 // Ethernet MAC Module 0 Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCWD register. +// +//***************************************************************************** +#define SYSCTL_DCGCWD_D1 0x00000002 // Watchdog Timer 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCWD_D0 0x00000001 // Watchdog Timer 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCTIMER_D7 0x00000080 // 16/32-Bit General-Purpose Timer + // 7 Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCTIMER_D6 0x00000040 // 16/32-Bit General-Purpose Timer + // 6 Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCTIMER_D5 0x00000020 // 16/32-Bit General-Purpose Timer + // 5 Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCTIMER_D4 0x00000010 // 16/32-Bit General-Purpose Timer + // 4 Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCTIMER_D3 0x00000008 // 16/32-Bit General-Purpose Timer + // 3 Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCTIMER_D2 0x00000004 // 16/32-Bit General-Purpose Timer + // 2 Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCTIMER_D1 0x00000002 // 16/32-Bit General-Purpose Timer + // 1 Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCTIMER_D0 0x00000001 // 16/32-Bit General-Purpose Timer + // 0 Deep-Sleep Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCGPIO +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCGPIO_D17 0x00020000 // GPIO Port T Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D16 0x00010000 // GPIO Port S Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D15 0x00008000 // GPIO Port R Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D14 0x00004000 // GPIO Port Q Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D13 0x00002000 // GPIO Port P Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D12 0x00001000 // GPIO Port N Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D11 0x00000800 // GPIO Port M Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D10 0x00000400 // GPIO Port L Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D9 0x00000200 // GPIO Port K Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D8 0x00000100 // GPIO Port J Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D7 0x00000080 // GPIO Port H Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D6 0x00000040 // GPIO Port G Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D5 0x00000020 // GPIO Port F Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D4 0x00000010 // GPIO Port E Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D3 0x00000008 // GPIO Port D Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D2 0x00000004 // GPIO Port C Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D1 0x00000002 // GPIO Port B Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D0 0x00000001 // GPIO Port A Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCDMA register. +// +//***************************************************************************** +#define SYSCTL_DCGCDMA_D0 0x00000001 // uDMA Module Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCEPI register. +// +//***************************************************************************** +#define SYSCTL_DCGCEPI_D0 0x00000001 // EPI Module Deep-Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCHIB register. +// +//***************************************************************************** +#define SYSCTL_DCGCHIB_D0 0x00000001 // Hibernation Module Deep-Sleep + // Mode Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCUART +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCUART_D7 0x00000080 // UART Module 7 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D6 0x00000040 // UART Module 6 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D5 0x00000020 // UART Module 5 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D4 0x00000010 // UART Module 4 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D3 0x00000008 // UART Module 3 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D2 0x00000004 // UART Module 2 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D1 0x00000002 // UART Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D0 0x00000001 // UART Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCSSI register. +// +//***************************************************************************** +#define SYSCTL_DCGCSSI_D3 0x00000008 // SSI Module 3 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCSSI_D2 0x00000004 // SSI Module 2 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCSSI_D1 0x00000002 // SSI Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCSSI_D0 0x00000001 // SSI Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCI2C register. +// +//***************************************************************************** +#define SYSCTL_DCGCI2C_D9 0x00000200 // I2C Module 9 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D8 0x00000100 // I2C Module 8 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D7 0x00000080 // I2C Module 7 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D6 0x00000040 // I2C Module 6 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D5 0x00000020 // I2C Module 5 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D4 0x00000010 // I2C Module 4 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D3 0x00000008 // I2C Module 3 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D2 0x00000004 // I2C Module 2 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D1 0x00000002 // I2C Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D0 0x00000001 // I2C Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCUSB register. +// +//***************************************************************************** +#define SYSCTL_DCGCUSB_D0 0x00000001 // USB Module Deep-Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCEPHY +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCEPHY_D0 0x00000001 // PHY Module Deep-Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCCAN register. +// +//***************************************************************************** +#define SYSCTL_DCGCCAN_D1 0x00000002 // CAN Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCCAN_D0 0x00000001 // CAN Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCADC register. +// +//***************************************************************************** +#define SYSCTL_DCGCADC_D1 0x00000002 // ADC Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCADC_D0 0x00000001 // ADC Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCACMP +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCACMP_D0 0x00000001 // Analog Comparator Module 0 + // Deep-Sleep Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCPWM register. +// +//***************************************************************************** +#define SYSCTL_DCGCPWM_D1 0x00000002 // PWM Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCPWM_D0 0x00000001 // PWM Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCQEI register. +// +//***************************************************************************** +#define SYSCTL_DCGCQEI_D1 0x00000002 // QEI Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCQEI_D0 0x00000001 // QEI Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCEEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCEEPROM_D0 0x00000001 // EEPROM Module Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCWTIMER_D5 0x00000020 // 32/64-Bit Wide General-Purpose + // Timer 5 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCWTIMER_D4 0x00000010 // 32/64-Bit Wide General-Purpose + // Timer 4 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCWTIMER_D3 0x00000008 // 32/64-Bit Wide General-Purpose + // Timer 3 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCWTIMER_D2 0x00000004 // 32/64-Bit Wide General-Purpose + // Timer 2 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCWTIMER_D1 0x00000002 // 32/64-Bit Wide General-Purpose + // Timer 1 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCWTIMER_D0 0x00000001 // 32/64-Bit Wide General-Purpose + // Timer 0 Deep-Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCCCM register. +// +//***************************************************************************** +#define SYSCTL_DCGCCCM_D0 0x00000001 // CRC and Cryptographic Modules + // Deep-Sleep Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCLCD register. +// +//***************************************************************************** +#define SYSCTL_DCGCLCD_D0 0x00000001 // LCD Controller Module 0 + // Deep-Sleep Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCOWIRE +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCOWIRE_D0 0x00000001 // 1-Wire Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCEMAC +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCEMAC_D0 0x00000001 // Ethernet MAC Module 0 Deep-Sleep + // Mode Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCWD register. +// +//***************************************************************************** +#define SYSCTL_PCWD_P1 0x00000002 // Watchdog Timer 1 Power Control +#define SYSCTL_PCWD_P0 0x00000001 // Watchdog Timer 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCTIMER register. +// +//***************************************************************************** +#define SYSCTL_PCTIMER_P7 0x00000080 // General-Purpose Timer 7 Power + // Control +#define SYSCTL_PCTIMER_P6 0x00000040 // General-Purpose Timer 6 Power + // Control +#define SYSCTL_PCTIMER_P5 0x00000020 // General-Purpose Timer 5 Power + // Control +#define SYSCTL_PCTIMER_P4 0x00000010 // General-Purpose Timer 4 Power + // Control +#define SYSCTL_PCTIMER_P3 0x00000008 // General-Purpose Timer 3 Power + // Control +#define SYSCTL_PCTIMER_P2 0x00000004 // General-Purpose Timer 2 Power + // Control +#define SYSCTL_PCTIMER_P1 0x00000002 // General-Purpose Timer 1 Power + // Control +#define SYSCTL_PCTIMER_P0 0x00000001 // General-Purpose Timer 0 Power + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCGPIO register. +// +//***************************************************************************** +#define SYSCTL_PCGPIO_P17 0x00020000 // GPIO Port T Power Control +#define SYSCTL_PCGPIO_P16 0x00010000 // GPIO Port S Power Control +#define SYSCTL_PCGPIO_P15 0x00008000 // GPIO Port R Power Control +#define SYSCTL_PCGPIO_P14 0x00004000 // GPIO Port Q Power Control +#define SYSCTL_PCGPIO_P13 0x00002000 // GPIO Port P Power Control +#define SYSCTL_PCGPIO_P12 0x00001000 // GPIO Port N Power Control +#define SYSCTL_PCGPIO_P11 0x00000800 // GPIO Port M Power Control +#define SYSCTL_PCGPIO_P10 0x00000400 // GPIO Port L Power Control +#define SYSCTL_PCGPIO_P9 0x00000200 // GPIO Port K Power Control +#define SYSCTL_PCGPIO_P8 0x00000100 // GPIO Port J Power Control +#define SYSCTL_PCGPIO_P7 0x00000080 // GPIO Port H Power Control +#define SYSCTL_PCGPIO_P6 0x00000040 // GPIO Port G Power Control +#define SYSCTL_PCGPIO_P5 0x00000020 // GPIO Port F Power Control +#define SYSCTL_PCGPIO_P4 0x00000010 // GPIO Port E Power Control +#define SYSCTL_PCGPIO_P3 0x00000008 // GPIO Port D Power Control +#define SYSCTL_PCGPIO_P2 0x00000004 // GPIO Port C Power Control +#define SYSCTL_PCGPIO_P1 0x00000002 // GPIO Port B Power Control +#define SYSCTL_PCGPIO_P0 0x00000001 // GPIO Port A Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCDMA register. +// +//***************************************************************************** +#define SYSCTL_PCDMA_P0 0x00000001 // uDMA Module Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCEPI register. +// +//***************************************************************************** +#define SYSCTL_PCEPI_P0 0x00000001 // EPI Module Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCHIB register. +// +//***************************************************************************** +#define SYSCTL_PCHIB_P0 0x00000001 // Hibernation Module Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCUART register. +// +//***************************************************************************** +#define SYSCTL_PCUART_P7 0x00000080 // UART Module 7 Power Control +#define SYSCTL_PCUART_P6 0x00000040 // UART Module 6 Power Control +#define SYSCTL_PCUART_P5 0x00000020 // UART Module 5 Power Control +#define SYSCTL_PCUART_P4 0x00000010 // UART Module 4 Power Control +#define SYSCTL_PCUART_P3 0x00000008 // UART Module 3 Power Control +#define SYSCTL_PCUART_P2 0x00000004 // UART Module 2 Power Control +#define SYSCTL_PCUART_P1 0x00000002 // UART Module 1 Power Control +#define SYSCTL_PCUART_P0 0x00000001 // UART Module 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCSSI register. +// +//***************************************************************************** +#define SYSCTL_PCSSI_P3 0x00000008 // SSI Module 3 Power Control +#define SYSCTL_PCSSI_P2 0x00000004 // SSI Module 2 Power Control +#define SYSCTL_PCSSI_P1 0x00000002 // SSI Module 1 Power Control +#define SYSCTL_PCSSI_P0 0x00000001 // SSI Module 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCI2C register. +// +//***************************************************************************** +#define SYSCTL_PCI2C_P9 0x00000200 // I2C Module 9 Power Control +#define SYSCTL_PCI2C_P8 0x00000100 // I2C Module 8 Power Control +#define SYSCTL_PCI2C_P7 0x00000080 // I2C Module 7 Power Control +#define SYSCTL_PCI2C_P6 0x00000040 // I2C Module 6 Power Control +#define SYSCTL_PCI2C_P5 0x00000020 // I2C Module 5 Power Control +#define SYSCTL_PCI2C_P4 0x00000010 // I2C Module 4 Power Control +#define SYSCTL_PCI2C_P3 0x00000008 // I2C Module 3 Power Control +#define SYSCTL_PCI2C_P2 0x00000004 // I2C Module 2 Power Control +#define SYSCTL_PCI2C_P1 0x00000002 // I2C Module 1 Power Control +#define SYSCTL_PCI2C_P0 0x00000001 // I2C Module 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCUSB register. +// +//***************************************************************************** +#define SYSCTL_PCUSB_P0 0x00000001 // USB Module Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCEPHY register. +// +//***************************************************************************** +#define SYSCTL_PCEPHY_P0 0x00000001 // Ethernet PHY Module Power + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCCAN register. +// +//***************************************************************************** +#define SYSCTL_PCCAN_P1 0x00000002 // CAN Module 1 Power Control +#define SYSCTL_PCCAN_P0 0x00000001 // CAN Module 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCADC register. +// +//***************************************************************************** +#define SYSCTL_PCADC_P1 0x00000002 // ADC Module 1 Power Control +#define SYSCTL_PCADC_P0 0x00000001 // ADC Module 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCACMP register. +// +//***************************************************************************** +#define SYSCTL_PCACMP_P0 0x00000001 // Analog Comparator Module 0 Power + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCPWM register. +// +//***************************************************************************** +#define SYSCTL_PCPWM_P0 0x00000001 // PWM Module 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCQEI register. +// +//***************************************************************************** +#define SYSCTL_PCQEI_P0 0x00000001 // QEI Module 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCEEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_PCEEPROM_P0 0x00000001 // EEPROM Module 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCCCM register. +// +//***************************************************************************** +#define SYSCTL_PCCCM_P0 0x00000001 // CRC and Cryptographic Modules + // Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCLCD register. +// +//***************************************************************************** +#define SYSCTL_PCLCD_P0 0x00000001 // LCD Controller Module 0 Power + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCOWIRE register. +// +//***************************************************************************** +#define SYSCTL_PCOWIRE_P0 0x00000001 // 1-Wire Module 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCEMAC register. +// +//***************************************************************************** +#define SYSCTL_PCEMAC_P0 0x00000001 // Ethernet MAC Module 0 Power + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRWD register. +// +//***************************************************************************** +#define SYSCTL_PRWD_R1 0x00000002 // Watchdog Timer 1 Peripheral + // Ready +#define SYSCTL_PRWD_R0 0x00000001 // Watchdog Timer 0 Peripheral + // Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRTIMER register. +// +//***************************************************************************** +#define SYSCTL_PRTIMER_R7 0x00000080 // 16/32-Bit General-Purpose Timer + // 7 Peripheral Ready +#define SYSCTL_PRTIMER_R6 0x00000040 // 16/32-Bit General-Purpose Timer + // 6 Peripheral Ready +#define SYSCTL_PRTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer + // 5 Peripheral Ready +#define SYSCTL_PRTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer + // 4 Peripheral Ready +#define SYSCTL_PRTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer + // 3 Peripheral Ready +#define SYSCTL_PRTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer + // 2 Peripheral Ready +#define SYSCTL_PRTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer + // 1 Peripheral Ready +#define SYSCTL_PRTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer + // 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRGPIO register. +// +//***************************************************************************** +#define SYSCTL_PRGPIO_R17 0x00020000 // GPIO Port T Peripheral Ready +#define SYSCTL_PRGPIO_R16 0x00010000 // GPIO Port S Peripheral Ready +#define SYSCTL_PRGPIO_R15 0x00008000 // GPIO Port R Peripheral Ready +#define SYSCTL_PRGPIO_R14 0x00004000 // GPIO Port Q Peripheral Ready +#define SYSCTL_PRGPIO_R13 0x00002000 // GPIO Port P Peripheral Ready +#define SYSCTL_PRGPIO_R12 0x00001000 // GPIO Port N Peripheral Ready +#define SYSCTL_PRGPIO_R11 0x00000800 // GPIO Port M Peripheral Ready +#define SYSCTL_PRGPIO_R10 0x00000400 // GPIO Port L Peripheral Ready +#define SYSCTL_PRGPIO_R9 0x00000200 // GPIO Port K Peripheral Ready +#define SYSCTL_PRGPIO_R8 0x00000100 // GPIO Port J Peripheral Ready +#define SYSCTL_PRGPIO_R7 0x00000080 // GPIO Port H Peripheral Ready +#define SYSCTL_PRGPIO_R6 0x00000040 // GPIO Port G Peripheral Ready +#define SYSCTL_PRGPIO_R5 0x00000020 // GPIO Port F Peripheral Ready +#define SYSCTL_PRGPIO_R4 0x00000010 // GPIO Port E Peripheral Ready +#define SYSCTL_PRGPIO_R3 0x00000008 // GPIO Port D Peripheral Ready +#define SYSCTL_PRGPIO_R2 0x00000004 // GPIO Port C Peripheral Ready +#define SYSCTL_PRGPIO_R1 0x00000002 // GPIO Port B Peripheral Ready +#define SYSCTL_PRGPIO_R0 0x00000001 // GPIO Port A Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRDMA register. +// +//***************************************************************************** +#define SYSCTL_PRDMA_R0 0x00000001 // uDMA Module Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PREPI register. +// +//***************************************************************************** +#define SYSCTL_PREPI_R0 0x00000001 // EPI Module Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRHIB register. +// +//***************************************************************************** +#define SYSCTL_PRHIB_R0 0x00000001 // Hibernation Module Peripheral + // Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRUART register. +// +//***************************************************************************** +#define SYSCTL_PRUART_R7 0x00000080 // UART Module 7 Peripheral Ready +#define SYSCTL_PRUART_R6 0x00000040 // UART Module 6 Peripheral Ready +#define SYSCTL_PRUART_R5 0x00000020 // UART Module 5 Peripheral Ready +#define SYSCTL_PRUART_R4 0x00000010 // UART Module 4 Peripheral Ready +#define SYSCTL_PRUART_R3 0x00000008 // UART Module 3 Peripheral Ready +#define SYSCTL_PRUART_R2 0x00000004 // UART Module 2 Peripheral Ready +#define SYSCTL_PRUART_R1 0x00000002 // UART Module 1 Peripheral Ready +#define SYSCTL_PRUART_R0 0x00000001 // UART Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRSSI register. +// +//***************************************************************************** +#define SYSCTL_PRSSI_R3 0x00000008 // SSI Module 3 Peripheral Ready +#define SYSCTL_PRSSI_R2 0x00000004 // SSI Module 2 Peripheral Ready +#define SYSCTL_PRSSI_R1 0x00000002 // SSI Module 1 Peripheral Ready +#define SYSCTL_PRSSI_R0 0x00000001 // SSI Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRI2C register. +// +//***************************************************************************** +#define SYSCTL_PRI2C_R9 0x00000200 // I2C Module 9 Peripheral Ready +#define SYSCTL_PRI2C_R8 0x00000100 // I2C Module 8 Peripheral Ready +#define SYSCTL_PRI2C_R7 0x00000080 // I2C Module 7 Peripheral Ready +#define SYSCTL_PRI2C_R6 0x00000040 // I2C Module 6 Peripheral Ready +#define SYSCTL_PRI2C_R5 0x00000020 // I2C Module 5 Peripheral Ready +#define SYSCTL_PRI2C_R4 0x00000010 // I2C Module 4 Peripheral Ready +#define SYSCTL_PRI2C_R3 0x00000008 // I2C Module 3 Peripheral Ready +#define SYSCTL_PRI2C_R2 0x00000004 // I2C Module 2 Peripheral Ready +#define SYSCTL_PRI2C_R1 0x00000002 // I2C Module 1 Peripheral Ready +#define SYSCTL_PRI2C_R0 0x00000001 // I2C Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRUSB register. +// +//***************************************************************************** +#define SYSCTL_PRUSB_R0 0x00000001 // USB Module Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PREPHY register. +// +//***************************************************************************** +#define SYSCTL_PREPHY_R0 0x00000001 // Ethernet PHY Module Peripheral + // Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRCAN register. +// +//***************************************************************************** +#define SYSCTL_PRCAN_R1 0x00000002 // CAN Module 1 Peripheral Ready +#define SYSCTL_PRCAN_R0 0x00000001 // CAN Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRADC register. +// +//***************************************************************************** +#define SYSCTL_PRADC_R1 0x00000002 // ADC Module 1 Peripheral Ready +#define SYSCTL_PRADC_R0 0x00000001 // ADC Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRACMP register. +// +//***************************************************************************** +#define SYSCTL_PRACMP_R0 0x00000001 // Analog Comparator Module 0 + // Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRPWM register. +// +//***************************************************************************** +#define SYSCTL_PRPWM_R1 0x00000002 // PWM Module 1 Peripheral Ready +#define SYSCTL_PRPWM_R0 0x00000001 // PWM Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRQEI register. +// +//***************************************************************************** +#define SYSCTL_PRQEI_R1 0x00000002 // QEI Module 1 Peripheral Ready +#define SYSCTL_PRQEI_R0 0x00000001 // QEI Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PREEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_PREEPROM_R0 0x00000001 // EEPROM Module Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_PRWTIMER_R5 0x00000020 // 32/64-Bit Wide General-Purpose + // Timer 5 Peripheral Ready +#define SYSCTL_PRWTIMER_R4 0x00000010 // 32/64-Bit Wide General-Purpose + // Timer 4 Peripheral Ready +#define SYSCTL_PRWTIMER_R3 0x00000008 // 32/64-Bit Wide General-Purpose + // Timer 3 Peripheral Ready +#define SYSCTL_PRWTIMER_R2 0x00000004 // 32/64-Bit Wide General-Purpose + // Timer 2 Peripheral Ready +#define SYSCTL_PRWTIMER_R1 0x00000002 // 32/64-Bit Wide General-Purpose + // Timer 1 Peripheral Ready +#define SYSCTL_PRWTIMER_R0 0x00000001 // 32/64-Bit Wide General-Purpose + // Timer 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRCCM register. +// +//***************************************************************************** +#define SYSCTL_PRCCM_R0 0x00000001 // CRC and Cryptographic Modules + // Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRLCD register. +// +//***************************************************************************** +#define SYSCTL_PRLCD_R0 0x00000001 // LCD Controller Module 0 + // Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PROWIRE register. +// +//***************************************************************************** +#define SYSCTL_PROWIRE_R0 0x00000001 // 1-Wire Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PREMAC register. +// +//***************************************************************************** +#define SYSCTL_PREMAC_R0 0x00000001 // Ethernet MAC Module 0 Peripheral + // Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_UNIQUEID0 +// register. +// +//***************************************************************************** +#define SYSCTL_UNIQUEID0_ID_M 0xFFFFFFFF // Unique ID +#define SYSCTL_UNIQUEID0_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_UNIQUEID1 +// register. +// +//***************************************************************************** +#define SYSCTL_UNIQUEID1_ID_M 0xFFFFFFFF // Unique ID +#define SYSCTL_UNIQUEID1_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_UNIQUEID2 +// register. +// +//***************************************************************************** +#define SYSCTL_UNIQUEID2_ID_M 0xFFFFFFFF // Unique ID +#define SYSCTL_UNIQUEID2_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_UNIQUEID3 +// register. +// +//***************************************************************************** +#define SYSCTL_UNIQUEID3_ID_M 0xFFFFFFFF // Unique ID +#define SYSCTL_UNIQUEID3_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_CCMCGREQ +// register. +// +//***************************************************************************** +#define SYSCTL_CCMCGREQ_DESCFG 0x00000004 // DES Clock Gating Request +#define SYSCTL_CCMCGREQ_AESCFG 0x00000002 // AES Clock Gating Request +#define SYSCTL_CCMCGREQ_SHACFG 0x00000001 // SHA/MD5 Clock Gating Request + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_DID0 +// register. +// +//***************************************************************************** +#define SYSCTL_DID0_CLASS_BLIZZARD \ + 0x00050000 // Tiva(TM) C Series TM4C123-class + // microcontrollers +#define SYSCTL_DID0_CLASS_SNOWFLAKE \ + 0x000A0000 // Tiva(TM) C Series TM4C129-class + // microcontrollers + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_RESC +// register. +// +//***************************************************************************** +#define SYSCTL_RESC_HIB 0x00000040 // HIB Reset + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_PWRTC +// register. +// +//***************************************************************************** +#define SYSCTL_PWRTC_VDDA_UBOR0 0x00000010 // VDDA Under BOR0 Status +#define SYSCTL_PWRTC_VDD_UBOR0 0x00000001 // VDD Under BOR0 Status + +#endif + +#endif // __HW_SYSCTL_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_sysexc.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_sysexc.h new file mode 100644 index 0000000000000000000000000000000000000000..314d17a8a1452e7e607682858e0cbef64b8b2aa1 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_sysexc.h @@ -0,0 +1,132 @@ +//***************************************************************************** +// +// hw_sysexc.h - Macros used when accessing the system exception module. +// +// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_SYSEXC_H__ +#define __HW_SYSEXC_H__ + +//***************************************************************************** +// +// The following are defines for the System Exception Module register +// addresses. +// +//***************************************************************************** +#define SYSEXC_RIS 0x400F9000 // System Exception Raw Interrupt + // Status +#define SYSEXC_IM 0x400F9004 // System Exception Interrupt Mask +#define SYSEXC_MIS 0x400F9008 // System Exception Masked + // Interrupt Status +#define SYSEXC_IC 0x400F900C // System Exception Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSEXC_RIS register. +// +//***************************************************************************** +#define SYSEXC_RIS_FPIXCRIS 0x00000020 // Floating-Point Inexact Exception + // Raw Interrupt Status +#define SYSEXC_RIS_FPOFCRIS 0x00000010 // Floating-Point Overflow + // Exception Raw Interrupt Status +#define SYSEXC_RIS_FPUFCRIS 0x00000008 // Floating-Point Underflow + // Exception Raw Interrupt Status +#define SYSEXC_RIS_FPIOCRIS 0x00000004 // Floating-Point Invalid Operation + // Raw Interrupt Status +#define SYSEXC_RIS_FPDZCRIS 0x00000002 // Floating-Point Divide By 0 + // Exception Raw Interrupt Status +#define SYSEXC_RIS_FPIDCRIS 0x00000001 // Floating-Point Input Denormal + // Exception Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSEXC_IM register. +// +//***************************************************************************** +#define SYSEXC_IM_FPIXCIM 0x00000020 // Floating-Point Inexact Exception + // Interrupt Mask +#define SYSEXC_IM_FPOFCIM 0x00000010 // Floating-Point Overflow + // Exception Interrupt Mask +#define SYSEXC_IM_FPUFCIM 0x00000008 // Floating-Point Underflow + // Exception Interrupt Mask +#define SYSEXC_IM_FPIOCIM 0x00000004 // Floating-Point Invalid Operation + // Interrupt Mask +#define SYSEXC_IM_FPDZCIM 0x00000002 // Floating-Point Divide By 0 + // Exception Interrupt Mask +#define SYSEXC_IM_FPIDCIM 0x00000001 // Floating-Point Input Denormal + // Exception Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSEXC_MIS register. +// +//***************************************************************************** +#define SYSEXC_MIS_FPIXCMIS 0x00000020 // Floating-Point Inexact Exception + // Masked Interrupt Status +#define SYSEXC_MIS_FPOFCMIS 0x00000010 // Floating-Point Overflow + // Exception Masked Interrupt + // Status +#define SYSEXC_MIS_FPUFCMIS 0x00000008 // Floating-Point Underflow + // Exception Masked Interrupt + // Status +#define SYSEXC_MIS_FPIOCMIS 0x00000004 // Floating-Point Invalid Operation + // Masked Interrupt Status +#define SYSEXC_MIS_FPDZCMIS 0x00000002 // Floating-Point Divide By 0 + // Exception Masked Interrupt + // Status +#define SYSEXC_MIS_FPIDCMIS 0x00000001 // Floating-Point Input Denormal + // Exception Masked Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSEXC_IC register. +// +//***************************************************************************** +#define SYSEXC_IC_FPIXCIC 0x00000020 // Floating-Point Inexact Exception + // Interrupt Clear +#define SYSEXC_IC_FPOFCIC 0x00000010 // Floating-Point Overflow + // Exception Interrupt Clear +#define SYSEXC_IC_FPUFCIC 0x00000008 // Floating-Point Underflow + // Exception Interrupt Clear +#define SYSEXC_IC_FPIOCIC 0x00000004 // Floating-Point Invalid Operation + // Interrupt Clear +#define SYSEXC_IC_FPDZCIC 0x00000002 // Floating-Point Divide By 0 + // Exception Interrupt Clear +#define SYSEXC_IC_FPIDCIC 0x00000001 // Floating-Point Input Denormal + // Exception Interrupt Clear + +#endif // __HW_SYSEXC_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_timer.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_timer.h new file mode 100644 index 0000000000000000000000000000000000000000..47a857567a84ab1b7ce64f2bc35e233e1bde13f5 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_timer.h @@ -0,0 +1,700 @@ +//***************************************************************************** +// +// hw_timer.h - Defines and macros used when accessing the timer. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_TIMER_H__ +#define __HW_TIMER_H__ + +//***************************************************************************** +// +// The following are defines for the Timer register offsets. +// +//***************************************************************************** +#define TIMER_O_CFG 0x00000000 // GPTM Configuration +#define TIMER_O_TAMR 0x00000004 // GPTM Timer A Mode +#define TIMER_O_TBMR 0x00000008 // GPTM Timer B Mode +#define TIMER_O_CTL 0x0000000C // GPTM Control +#define TIMER_O_SYNC 0x00000010 // GPTM Synchronize +#define TIMER_O_IMR 0x00000018 // GPTM Interrupt Mask +#define TIMER_O_RIS 0x0000001C // GPTM Raw Interrupt Status +#define TIMER_O_MIS 0x00000020 // GPTM Masked Interrupt Status +#define TIMER_O_ICR 0x00000024 // GPTM Interrupt Clear +#define TIMER_O_TAILR 0x00000028 // GPTM Timer A Interval Load +#define TIMER_O_TBILR 0x0000002C // GPTM Timer B Interval Load +#define TIMER_O_TAMATCHR 0x00000030 // GPTM Timer A Match +#define TIMER_O_TBMATCHR 0x00000034 // GPTM Timer B Match +#define TIMER_O_TAPR 0x00000038 // GPTM Timer A Prescale +#define TIMER_O_TBPR 0x0000003C // GPTM Timer B Prescale +#define TIMER_O_TAPMR 0x00000040 // GPTM TimerA Prescale Match +#define TIMER_O_TBPMR 0x00000044 // GPTM TimerB Prescale Match +#define TIMER_O_TAR 0x00000048 // GPTM Timer A +#define TIMER_O_TBR 0x0000004C // GPTM Timer B +#define TIMER_O_TAV 0x00000050 // GPTM Timer A Value +#define TIMER_O_TBV 0x00000054 // GPTM Timer B Value +#define TIMER_O_RTCPD 0x00000058 // GPTM RTC Predivide +#define TIMER_O_TAPS 0x0000005C // GPTM Timer A Prescale Snapshot +#define TIMER_O_TBPS 0x00000060 // GPTM Timer B Prescale Snapshot +#define TIMER_O_TAPV 0x00000064 // GPTM Timer A Prescale Value +#define TIMER_O_TBPV 0x00000068 // GPTM Timer B Prescale Value +#define TIMER_O_DMAEV 0x0000006C // GPTM DMA Event +#define TIMER_O_ADCEV 0x00000070 // GPTM ADC Event +#define TIMER_O_PP 0x00000FC0 // GPTM Peripheral Properties +#define TIMER_O_CC 0x00000FC8 // GPTM Clock Configuration + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_CFG register. +// +//***************************************************************************** +#define TIMER_CFG_M 0x00000007 // GPTM Configuration +#define TIMER_CFG_32_BIT_TIMER 0x00000000 // For a 16/32-bit timer, this + // value selects the 32-bit timer + // configuration +#define TIMER_CFG_32_BIT_RTC 0x00000001 // For a 16/32-bit timer, this + // value selects the 32-bit + // real-time clock (RTC) counter + // configuration +#define TIMER_CFG_16_BIT 0x00000004 // For a 16/32-bit timer, this + // value selects the 16-bit timer + // configuration + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAMR register. +// +//***************************************************************************** +#define TIMER_TAMR_TCACT_M 0x0000E000 // Timer Compare Action Select +#define TIMER_TAMR_TCACT_NONE 0x00000000 // Disable compare operations +#define TIMER_TAMR_TCACT_TOGGLE 0x00002000 // Toggle State on Time-Out +#define TIMER_TAMR_TCACT_CLRTO 0x00004000 // Clear CCP on Time-Out +#define TIMER_TAMR_TCACT_SETTO 0x00006000 // Set CCP on Time-Out +#define TIMER_TAMR_TCACT_SETTOGTO \ + 0x00008000 // Set CCP immediately and toggle + // on Time-Out +#define TIMER_TAMR_TCACT_CLRTOGTO \ + 0x0000A000 // Clear CCP immediately and toggle + // on Time-Out +#define TIMER_TAMR_TCACT_SETCLRTO \ + 0x0000C000 // Set CCP immediately and clear on + // Time-Out +#define TIMER_TAMR_TCACT_CLRSETTO \ + 0x0000E000 // Clear CCP immediately and set on + // Time-Out +#define TIMER_TAMR_TACINTD 0x00001000 // One-shot/Periodic Interrupt + // Disable +#define TIMER_TAMR_TAPLO 0x00000800 // GPTM Timer A PWM Legacy + // Operation +#define TIMER_TAMR_TAMRSU 0x00000400 // GPTM Timer A Match Register + // Update +#define TIMER_TAMR_TAPWMIE 0x00000200 // GPTM Timer A PWM Interrupt + // Enable +#define TIMER_TAMR_TAILD 0x00000100 // GPTM Timer A Interval Load Write +#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode +#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger +#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt + // Enable +#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction +#define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode + // Select +#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode +#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode +#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode +#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode +#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBMR register. +// +//***************************************************************************** +#define TIMER_TBMR_TCACT_M 0x0000E000 // Timer Compare Action Select +#define TIMER_TBMR_TCACT_NONE 0x00000000 // Disable compare operations +#define TIMER_TBMR_TCACT_TOGGLE 0x00002000 // Toggle State on Time-Out +#define TIMER_TBMR_TCACT_CLRTO 0x00004000 // Clear CCP on Time-Out +#define TIMER_TBMR_TCACT_SETTO 0x00006000 // Set CCP on Time-Out +#define TIMER_TBMR_TCACT_SETTOGTO \ + 0x00008000 // Set CCP immediately and toggle + // on Time-Out +#define TIMER_TBMR_TCACT_CLRTOGTO \ + 0x0000A000 // Clear CCP immediately and toggle + // on Time-Out +#define TIMER_TBMR_TCACT_SETCLRTO \ + 0x0000C000 // Set CCP immediately and clear on + // Time-Out +#define TIMER_TBMR_TCACT_CLRSETTO \ + 0x0000E000 // Clear CCP immediately and set on + // Time-Out +#define TIMER_TBMR_TBCINTD 0x00001000 // One-Shot/Periodic Interrupt + // Disable +#define TIMER_TBMR_TBPLO 0x00000800 // GPTM Timer B PWM Legacy + // Operation +#define TIMER_TBMR_TBMRSU 0x00000400 // GPTM Timer B Match Register + // Update +#define TIMER_TBMR_TBPWMIE 0x00000200 // GPTM Timer B PWM Interrupt + // Enable +#define TIMER_TBMR_TBILD 0x00000100 // GPTM Timer B Interval Load Write +#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode +#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger +#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt + // Enable +#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction +#define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode + // Select +#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode +#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode +#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode +#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode +#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_CTL register. +// +//***************************************************************************** +#define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level +#define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger + // Enable +#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode +#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge +#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge +#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges +#define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable +#define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable +#define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level +#define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger + // Enable +#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Stall Enable +#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode +#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge +#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge +#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges +#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable +#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_SYNC register. +// +//***************************************************************************** +#define TIMER_SYNC_SYNCWT5_M 0x00C00000 // Synchronize GPTM 32/64-Bit Timer + // 5 +#define TIMER_SYNC_SYNCWT5_NONE 0x00000000 // GPTM 32/64-Bit Timer 5 is not + // affected +#define TIMER_SYNC_SYNCWT5_TA 0x00400000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 5 is + // triggered +#define TIMER_SYNC_SYNCWT5_TB 0x00800000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 5 is + // triggered +#define TIMER_SYNC_SYNCWT5_TATB 0x00C00000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 5 is triggered +#define TIMER_SYNC_SYNCWT4_M 0x00300000 // Synchronize GPTM 32/64-Bit Timer + // 4 +#define TIMER_SYNC_SYNCWT4_NONE 0x00000000 // GPTM 32/64-Bit Timer 4 is not + // affected +#define TIMER_SYNC_SYNCWT4_TA 0x00100000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 4 is + // triggered +#define TIMER_SYNC_SYNCWT4_TB 0x00200000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 4 is + // triggered +#define TIMER_SYNC_SYNCWT4_TATB 0x00300000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 4 is triggered +#define TIMER_SYNC_SYNCWT3_M 0x000C0000 // Synchronize GPTM 32/64-Bit Timer + // 3 +#define TIMER_SYNC_SYNCWT3_NONE 0x00000000 // GPTM 32/64-Bit Timer 3 is not + // affected +#define TIMER_SYNC_SYNCWT3_TA 0x00040000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 3 is + // triggered +#define TIMER_SYNC_SYNCWT3_TB 0x00080000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 3 is + // triggered +#define TIMER_SYNC_SYNCWT3_TATB 0x000C0000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 3 is triggered +#define TIMER_SYNC_SYNCWT2_M 0x00030000 // Synchronize GPTM 32/64-Bit Timer + // 2 +#define TIMER_SYNC_SYNCWT2_NONE 0x00000000 // GPTM 32/64-Bit Timer 2 is not + // affected +#define TIMER_SYNC_SYNCWT2_TA 0x00010000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 2 is + // triggered +#define TIMER_SYNC_SYNCWT2_TB 0x00020000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 2 is + // triggered +#define TIMER_SYNC_SYNCWT2_TATB 0x00030000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 2 is triggered +#define TIMER_SYNC_SYNCT7_M 0x0000C000 // Synchronize GPTM Timer 7 +#define TIMER_SYNC_SYNCT7_NONE 0x00000000 // GPT7 is not affected +#define TIMER_SYNC_SYNCT7_TA 0x00004000 // A timeout event for Timer A of + // GPTM7 is triggered +#define TIMER_SYNC_SYNCT7_TB 0x00008000 // A timeout event for Timer B of + // GPTM7 is triggered +#define TIMER_SYNC_SYNCT7_TATB 0x0000C000 // A timeout event for both Timer A + // and Timer B of GPTM7 is + // triggered +#define TIMER_SYNC_SYNCWT1_M 0x0000C000 // Synchronize GPTM 32/64-Bit Timer + // 1 +#define TIMER_SYNC_SYNCWT1_NONE 0x00000000 // GPTM 32/64-Bit Timer 1 is not + // affected +#define TIMER_SYNC_SYNCWT1_TA 0x00004000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 1 is + // triggered +#define TIMER_SYNC_SYNCWT1_TB 0x00008000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 1 is + // triggered +#define TIMER_SYNC_SYNCWT1_TATB 0x0000C000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 1 is triggered +#define TIMER_SYNC_SYNCWT0_M 0x00003000 // Synchronize GPTM 32/64-Bit Timer + // 0 +#define TIMER_SYNC_SYNCWT0_NONE 0x00000000 // GPTM 32/64-Bit Timer 0 is not + // affected +#define TIMER_SYNC_SYNCWT0_TA 0x00001000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 0 is + // triggered +#define TIMER_SYNC_SYNCWT0_TB 0x00002000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 0 is + // triggered +#define TIMER_SYNC_SYNCWT0_TATB 0x00003000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 0 is triggered +#define TIMER_SYNC_SYNCT6_M 0x00003000 // Synchronize GPTM Timer 6 +#define TIMER_SYNC_SYNCT6_NONE 0x00000000 // GPTM6 is not affected +#define TIMER_SYNC_SYNCT6_TA 0x00001000 // A timeout event for Timer A of + // GPTM6 is triggered +#define TIMER_SYNC_SYNCT6_TB 0x00002000 // A timeout event for Timer B of + // GPTM6 is triggered +#define TIMER_SYNC_SYNCT6_TATB 0x00003000 // A timeout event for both Timer A + // and Timer B of GPTM6 is + // triggered +#define TIMER_SYNC_SYNCT5_M 0x00000C00 // Synchronize GPTM Timer 5 +#define TIMER_SYNC_SYNCT5_NONE 0x00000000 // GPTM5 is not affected +#define TIMER_SYNC_SYNCT5_TA 0x00000400 // A timeout event for Timer A of + // GPTM5 is triggered +#define TIMER_SYNC_SYNCT5_TB 0x00000800 // A timeout event for Timer B of + // GPTM5 is triggered +#define TIMER_SYNC_SYNCT5_TATB 0x00000C00 // A timeout event for both Timer A + // and Timer B of GPTM5 is + // triggered +#define TIMER_SYNC_SYNCT4_M 0x00000300 // Synchronize GPTM Timer 4 +#define TIMER_SYNC_SYNCT4_NONE 0x00000000 // GPTM4 is not affected +#define TIMER_SYNC_SYNCT4_TA 0x00000100 // A timeout event for Timer A of + // GPTM4 is triggered +#define TIMER_SYNC_SYNCT4_TB 0x00000200 // A timeout event for Timer B of + // GPTM4 is triggered +#define TIMER_SYNC_SYNCT4_TATB 0x00000300 // A timeout event for both Timer A + // and Timer B of GPTM4 is + // triggered +#define TIMER_SYNC_SYNCT3_M 0x000000C0 // Synchronize GPTM Timer 3 +#define TIMER_SYNC_SYNCT3_NONE 0x00000000 // GPTM3 is not affected +#define TIMER_SYNC_SYNCT3_TA 0x00000040 // A timeout event for Timer A of + // GPTM3 is triggered +#define TIMER_SYNC_SYNCT3_TB 0x00000080 // A timeout event for Timer B of + // GPTM3 is triggered +#define TIMER_SYNC_SYNCT3_TATB 0x000000C0 // A timeout event for both Timer A + // and Timer B of GPTM3 is + // triggered +#define TIMER_SYNC_SYNCT2_M 0x00000030 // Synchronize GPTM Timer 2 +#define TIMER_SYNC_SYNCT2_NONE 0x00000000 // GPTM2 is not affected +#define TIMER_SYNC_SYNCT2_TA 0x00000010 // A timeout event for Timer A of + // GPTM2 is triggered +#define TIMER_SYNC_SYNCT2_TB 0x00000020 // A timeout event for Timer B of + // GPTM2 is triggered +#define TIMER_SYNC_SYNCT2_TATB 0x00000030 // A timeout event for both Timer A + // and Timer B of GPTM2 is + // triggered +#define TIMER_SYNC_SYNCT1_M 0x0000000C // Synchronize GPTM Timer 1 +#define TIMER_SYNC_SYNCT1_NONE 0x00000000 // GPTM1 is not affected +#define TIMER_SYNC_SYNCT1_TA 0x00000004 // A timeout event for Timer A of + // GPTM1 is triggered +#define TIMER_SYNC_SYNCT1_TB 0x00000008 // A timeout event for Timer B of + // GPTM1 is triggered +#define TIMER_SYNC_SYNCT1_TATB 0x0000000C // A timeout event for both Timer A + // and Timer B of GPTM1 is + // triggered +#define TIMER_SYNC_SYNCT0_M 0x00000003 // Synchronize GPTM Timer 0 +#define TIMER_SYNC_SYNCT0_NONE 0x00000000 // GPTM0 is not affected +#define TIMER_SYNC_SYNCT0_TA 0x00000001 // A timeout event for Timer A of + // GPTM0 is triggered +#define TIMER_SYNC_SYNCT0_TB 0x00000002 // A timeout event for Timer B of + // GPTM0 is triggered +#define TIMER_SYNC_SYNCT0_TATB 0x00000003 // A timeout event for both Timer A + // and Timer B of GPTM0 is + // triggered + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_IMR register. +// +//***************************************************************************** +#define TIMER_IMR_WUEIM 0x00010000 // 32/64-Bit Wide GPTM Write Update + // Error Interrupt Mask +#define TIMER_IMR_DMABIM 0x00002000 // GPTM Timer B DMA Done Interrupt + // Mask +#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Match Interrupt + // Mask +#define TIMER_IMR_CBEIM 0x00000400 // GPTM Timer B Capture Mode Event + // Interrupt Mask +#define TIMER_IMR_CBMIM 0x00000200 // GPTM Timer B Capture Mode Match + // Interrupt Mask +#define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt + // Mask +#define TIMER_IMR_DMAAIM 0x00000020 // GPTM Timer A DMA Done Interrupt + // Mask +#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Match Interrupt + // Mask +#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask +#define TIMER_IMR_CAEIM 0x00000004 // GPTM Timer A Capture Mode Event + // Interrupt Mask +#define TIMER_IMR_CAMIM 0x00000002 // GPTM Timer A Capture Mode Match + // Interrupt Mask +#define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt + // Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_RIS register. +// +//***************************************************************************** +#define TIMER_RIS_WUERIS 0x00010000 // 32/64-Bit Wide GPTM Write Update + // Error Raw Interrupt Status +#define TIMER_RIS_DMABRIS 0x00002000 // GPTM Timer B DMA Done Raw + // Interrupt Status +#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Match Raw Interrupt +#define TIMER_RIS_CBERIS 0x00000400 // GPTM Timer B Capture Mode Event + // Raw Interrupt +#define TIMER_RIS_CBMRIS 0x00000200 // GPTM Timer B Capture Mode Match + // Raw Interrupt +#define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw + // Interrupt +#define TIMER_RIS_DMAARIS 0x00000020 // GPTM Timer A DMA Done Raw + // Interrupt Status +#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Match Raw Interrupt +#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt +#define TIMER_RIS_CAERIS 0x00000004 // GPTM Timer A Capture Mode Event + // Raw Interrupt +#define TIMER_RIS_CAMRIS 0x00000002 // GPTM Timer A Capture Mode Match + // Raw Interrupt +#define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw + // Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_MIS register. +// +//***************************************************************************** +#define TIMER_MIS_WUEMIS 0x00010000 // 32/64-Bit Wide GPTM Write Update + // Error Masked Interrupt Status +#define TIMER_MIS_DMABMIS 0x00002000 // GPTM Timer B DMA Done Masked + // Interrupt +#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Match Masked + // Interrupt +#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Timer B Capture Mode Event + // Masked Interrupt +#define TIMER_MIS_CBMMIS 0x00000200 // GPTM Timer B Capture Mode Match + // Masked Interrupt +#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked + // Interrupt +#define TIMER_MIS_DMAAMIS 0x00000020 // GPTM Timer A DMA Done Masked + // Interrupt +#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Match Masked + // Interrupt +#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt +#define TIMER_MIS_CAEMIS 0x00000004 // GPTM Timer A Capture Mode Event + // Masked Interrupt +#define TIMER_MIS_CAMMIS 0x00000002 // GPTM Timer A Capture Mode Match + // Masked Interrupt +#define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked + // Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_ICR register. +// +//***************************************************************************** +#define TIMER_ICR_WUECINT 0x00010000 // 32/64-Bit Wide GPTM Write Update + // Error Interrupt Clear +#define TIMER_ICR_DMABINT 0x00002000 // GPTM Timer B DMA Done Interrupt + // Clear +#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Match Interrupt + // Clear +#define TIMER_ICR_CBECINT 0x00000400 // GPTM Timer B Capture Mode Event + // Interrupt Clear +#define TIMER_ICR_CBMCINT 0x00000200 // GPTM Timer B Capture Mode Match + // Interrupt Clear +#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt + // Clear +#define TIMER_ICR_DMAAINT 0x00000020 // GPTM Timer A DMA Done Interrupt + // Clear +#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Match Interrupt + // Clear +#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear +#define TIMER_ICR_CAECINT 0x00000004 // GPTM Timer A Capture Mode Event + // Interrupt Clear +#define TIMER_ICR_CAMCINT 0x00000002 // GPTM Timer A Capture Mode Match + // Interrupt Clear +#define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw + // Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAILR register. +// +//***************************************************************************** +#define TIMER_TAILR_M 0xFFFFFFFF // GPTM Timer A Interval Load + // Register +#define TIMER_TAILR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBILR register. +// +//***************************************************************************** +#define TIMER_TBILR_M 0xFFFFFFFF // GPTM Timer B Interval Load + // Register +#define TIMER_TBILR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAMATCHR +// register. +// +//***************************************************************************** +#define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF // GPTM Timer A Match Register +#define TIMER_TAMATCHR_TAMR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBMATCHR +// register. +// +//***************************************************************************** +#define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF // GPTM Timer B Match Register +#define TIMER_TBMATCHR_TBMR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPR register. +// +//***************************************************************************** +#define TIMER_TAPR_TAPSRH_M 0x0000FF00 // GPTM Timer A Prescale High Byte +#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale +#define TIMER_TAPR_TAPSRH_S 8 +#define TIMER_TAPR_TAPSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPR register. +// +//***************************************************************************** +#define TIMER_TBPR_TBPSRH_M 0x0000FF00 // GPTM Timer B Prescale High Byte +#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale +#define TIMER_TBPR_TBPSRH_S 8 +#define TIMER_TBPR_TBPSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPMR register. +// +//***************************************************************************** +#define TIMER_TAPMR_TAPSMRH_M 0x0000FF00 // GPTM Timer A Prescale Match High + // Byte +#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match +#define TIMER_TAPMR_TAPSMRH_S 8 +#define TIMER_TAPMR_TAPSMR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPMR register. +// +//***************************************************************************** +#define TIMER_TBPMR_TBPSMRH_M 0x0000FF00 // GPTM Timer B Prescale Match High + // Byte +#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match +#define TIMER_TBPMR_TBPSMRH_S 8 +#define TIMER_TBPMR_TBPSMR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAR register. +// +//***************************************************************************** +#define TIMER_TAR_M 0xFFFFFFFF // GPTM Timer A Register +#define TIMER_TAR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBR register. +// +//***************************************************************************** +#define TIMER_TBR_M 0xFFFFFFFF // GPTM Timer B Register +#define TIMER_TBR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAV register. +// +//***************************************************************************** +#define TIMER_TAV_M 0xFFFFFFFF // GPTM Timer A Value +#define TIMER_TAV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBV register. +// +//***************************************************************************** +#define TIMER_TBV_M 0xFFFFFFFF // GPTM Timer B Value +#define TIMER_TBV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_RTCPD register. +// +//***************************************************************************** +#define TIMER_RTCPD_RTCPD_M 0x0000FFFF // RTC Predivide Counter Value +#define TIMER_RTCPD_RTCPD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPS register. +// +//***************************************************************************** +#define TIMER_TAPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Snapshot +#define TIMER_TAPS_PSS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPS register. +// +//***************************************************************************** +#define TIMER_TBPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Value +#define TIMER_TBPS_PSS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPV register. +// +//***************************************************************************** +#define TIMER_TAPV_PSV_M 0x0000FFFF // GPTM Timer A Prescaler Value +#define TIMER_TAPV_PSV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPV register. +// +//***************************************************************************** +#define TIMER_TBPV_PSV_M 0x0000FFFF // GPTM Timer B Prescaler Value +#define TIMER_TBPV_PSV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_DMAEV register. +// +//***************************************************************************** +#define TIMER_DMAEV_TBMDMAEN 0x00000800 // GPTM B Mode Match Event DMA + // Trigger Enable +#define TIMER_DMAEV_CBEDMAEN 0x00000400 // GPTM B Capture Event DMA Trigger + // Enable +#define TIMER_DMAEV_CBMDMAEN 0x00000200 // GPTM B Capture Match Event DMA + // Trigger Enable +#define TIMER_DMAEV_TBTODMAEN 0x00000100 // GPTM B Time-Out Event DMA + // Trigger Enable +#define TIMER_DMAEV_TAMDMAEN 0x00000010 // GPTM A Mode Match Event DMA + // Trigger Enable +#define TIMER_DMAEV_RTCDMAEN 0x00000008 // GPTM A RTC Match Event DMA + // Trigger Enable +#define TIMER_DMAEV_CAEDMAEN 0x00000004 // GPTM A Capture Event DMA Trigger + // Enable +#define TIMER_DMAEV_CAMDMAEN 0x00000002 // GPTM A Capture Match Event DMA + // Trigger Enable +#define TIMER_DMAEV_TATODMAEN 0x00000001 // GPTM A Time-Out Event DMA + // Trigger Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_ADCEV register. +// +//***************************************************************************** +#define TIMER_ADCEV_TBMADCEN 0x00000800 // GPTM B Mode Match Event ADC + // Trigger Enable +#define TIMER_ADCEV_CBEADCEN 0x00000400 // GPTM B Capture Event ADC Trigger + // Enable +#define TIMER_ADCEV_CBMADCEN 0x00000200 // GPTM B Capture Match Event ADC + // Trigger Enable +#define TIMER_ADCEV_TBTOADCEN 0x00000100 // GPTM B Time-Out Event ADC + // Trigger Enable +#define TIMER_ADCEV_TAMADCEN 0x00000010 // GPTM A Mode Match Event ADC + // Trigger Enable +#define TIMER_ADCEV_RTCADCEN 0x00000008 // GPTM RTC Match Event ADC Trigger + // Enable +#define TIMER_ADCEV_CAEADCEN 0x00000004 // GPTM A Capture Event ADC Trigger + // Enable +#define TIMER_ADCEV_CAMADCEN 0x00000002 // GPTM A Capture Match Event ADC + // Trigger Enable +#define TIMER_ADCEV_TATOADCEN 0x00000001 // GPTM A Time-Out Event ADC + // Trigger Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_PP register. +// +//***************************************************************************** +#define TIMER_PP_ALTCLK 0x00000040 // Alternate Clock Source +#define TIMER_PP_SYNCCNT 0x00000020 // Synchronize Start +#define TIMER_PP_CHAIN 0x00000010 // Chain with Other Timers +#define TIMER_PP_SIZE_M 0x0000000F // Count Size +#define TIMER_PP_SIZE_16 0x00000000 // Timer A and Timer B counters are + // 16 bits each with an 8-bit + // prescale counter +#define TIMER_PP_SIZE_32 0x00000001 // Timer A and Timer B counters are + // 32 bits each with a 16-bit + // prescale counter + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_CC register. +// +//***************************************************************************** +#define TIMER_CC_ALTCLK 0x00000001 // Alternate Clock Source + +#endif // __HW_TIMER_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_types.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_types.h new file mode 100644 index 0000000000000000000000000000000000000000..ec493b5061a475aef624bc69d58c73ec94c3a1c1 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_types.h @@ -0,0 +1,147 @@ +//***************************************************************************** +// +// hw_types.h - Common types and macros. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_TYPES_H__ +#define __HW_TYPES_H__ + +//***************************************************************************** +// +// Macros for hardware access, both direct and via the bit-band region. +// +//***************************************************************************** +#define HWREG(x) \ + (*((volatile uint32_t *)(x))) +#define HWREGH(x) \ + (*((volatile uint16_t *)(x))) +#define HWREGB(x) \ + (*((volatile uint8_t *)(x))) +#define HWREGBITW(x, b) \ + HWREG(((uint32_t)(x) & 0xF0000000) | 0x02000000 | \ + (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITH(x, b) \ + HWREGH(((uint32_t)(x) & 0xF0000000) | 0x02000000 | \ + (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITB(x, b) \ + HWREGB(((uint32_t)(x) & 0xF0000000) | 0x02000000 | \ + (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + +//***************************************************************************** +// +// Helper Macros for determining silicon revisions, etc. +// +// These macros will be used by Driverlib at "run-time" to create necessary +// conditional code blocks that will allow a single version of the Driverlib +// "binary" code to support multiple(all) Tiva silicon revisions. +// +// It is expected that these macros will be used inside of a standard 'C' +// conditional block of code, e.g. +// +// if(CLASS_IS_TM4C123) +// { +// do some TM4C123-class specific code here. +// } +// +// By default, these macros will be defined as run-time checks of the +// appropriate register(s) to allow creation of run-time conditional code +// blocks for a common DriverLib across the entire Tiva family. +// +// However, if code-space optimization is required, these macros can be "hard- +// coded" for a specific version of Tiva silicon. Many compilers will then +// detect the "hard-coded" conditionals, and appropriately optimize the code +// blocks, eliminating any "unreachable" code. This would result in a smaller +// Driverlib, thus producing a smaller final application size, but at the cost +// of limiting the Driverlib binary to a specific Tiva silicon revision. +// +//***************************************************************************** +#ifndef CLASS_IS_TM4C123 +#define CLASS_IS_TM4C123 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \ + (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_TM4C123)) +#endif + +#ifndef CLASS_IS_TM4C129 +#define CLASS_IS_TM4C129 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \ + (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_TM4C129)) +#endif + +#ifndef REVISION_IS_A0 +#define REVISION_IS_A0 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0)) +#endif + +#ifndef REVISION_IS_A1 +#define REVISION_IS_A1 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0)) +#endif + +#ifndef REVISION_IS_A2 +#define REVISION_IS_A2 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_2)) +#endif + +#ifndef REVISION_IS_B0 +#define REVISION_IS_B0 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_0)) +#endif + +#ifndef REVISION_IS_B1 +#define REVISION_IS_B1 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_1)) +#endif + +//***************************************************************************** +// +// For TivaWare 2.1, we removed all references to Tiva IC codenames from the +// source. To ensure that existing customer code doesn't break as a result +// of this change, make sure that the old definitions are still available at +// least for the time being. +// +//***************************************************************************** +#ifndef DEPRECATED +#define CLASS_IS_BLIZZARD CLASS_IS_TM4C123 +#define CLASS_IS_SNOWFLAKE CLASS_IS_TM4C123 +#endif + +#endif // __HW_TYPES_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_uart.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_uart.h new file mode 100644 index 0000000000000000000000000000000000000000..1c40b79f3db950f3c64f9d9f3fc9228a2642c0a9 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_uart.h @@ -0,0 +1,367 @@ +//***************************************************************************** +// +// hw_uart.h - Macros and defines used when accessing the UART hardware. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_UART_H__ +#define __HW_UART_H__ + +//***************************************************************************** +// +// The following are defines for the UART register offsets. +// +//***************************************************************************** +#define UART_O_DR 0x00000000 // UART Data +#define UART_O_RSR 0x00000004 // UART Receive Status/Error Clear +#define UART_O_ECR 0x00000004 // UART Receive Status/Error Clear +#define UART_O_FR 0x00000018 // UART Flag +#define UART_O_ILPR 0x00000020 // UART IrDA Low-Power Register +#define UART_O_IBRD 0x00000024 // UART Integer Baud-Rate Divisor +#define UART_O_FBRD 0x00000028 // UART Fractional Baud-Rate + // Divisor +#define UART_O_LCRH 0x0000002C // UART Line Control +#define UART_O_CTL 0x00000030 // UART Control +#define UART_O_IFLS 0x00000034 // UART Interrupt FIFO Level Select +#define UART_O_IM 0x00000038 // UART Interrupt Mask +#define UART_O_RIS 0x0000003C // UART Raw Interrupt Status +#define UART_O_MIS 0x00000040 // UART Masked Interrupt Status +#define UART_O_ICR 0x00000044 // UART Interrupt Clear +#define UART_O_DMACTL 0x00000048 // UART DMA Control +#define UART_O_9BITADDR 0x000000A4 // UART 9-Bit Self Address +#define UART_O_9BITAMASK 0x000000A8 // UART 9-Bit Self Address Mask +#define UART_O_PP 0x00000FC0 // UART Peripheral Properties +#define UART_O_CC 0x00000FC8 // UART Clock Configuration + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_DR register. +// +//***************************************************************************** +#define UART_DR_OE 0x00000800 // UART Overrun Error +#define UART_DR_BE 0x00000400 // UART Break Error +#define UART_DR_PE 0x00000200 // UART Parity Error +#define UART_DR_FE 0x00000100 // UART Framing Error +#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received +#define UART_DR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_RSR register. +// +//***************************************************************************** +#define UART_RSR_OE 0x00000008 // UART Overrun Error +#define UART_RSR_BE 0x00000004 // UART Break Error +#define UART_RSR_PE 0x00000002 // UART Parity Error +#define UART_RSR_FE 0x00000001 // UART Framing Error + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ECR register. +// +//***************************************************************************** +#define UART_ECR_DATA_M 0x000000FF // Error Clear +#define UART_ECR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_FR register. +// +//***************************************************************************** +#define UART_FR_RI 0x00000100 // Ring Indicator +#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty +#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full +#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full +#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty +#define UART_FR_BUSY 0x00000008 // UART Busy +#define UART_FR_DCD 0x00000004 // Data Carrier Detect +#define UART_FR_DSR 0x00000002 // Data Set Ready +#define UART_FR_CTS 0x00000001 // Clear To Send + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ILPR register. +// +//***************************************************************************** +#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor +#define UART_ILPR_ILPDVSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_IBRD register. +// +//***************************************************************************** +#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor +#define UART_IBRD_DIVINT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_FBRD register. +// +//***************************************************************************** +#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor +#define UART_FBRD_DIVFRAC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_LCRH register. +// +//***************************************************************************** +#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select +#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length +#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default) +#define UART_LCRH_WLEN_6 0x00000020 // 6 bits +#define UART_LCRH_WLEN_7 0x00000040 // 7 bits +#define UART_LCRH_WLEN_8 0x00000060 // 8 bits +#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs +#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select +#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select +#define UART_LCRH_PEN 0x00000002 // UART Parity Enable +#define UART_LCRH_BRK 0x00000001 // UART Send Break + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_CTL register. +// +//***************************************************************************** +#define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send +#define UART_CTL_RTSEN 0x00004000 // Enable Request to Send +#define UART_CTL_RTS 0x00000800 // Request to Send +#define UART_CTL_DTR 0x00000400 // Data Terminal Ready +#define UART_CTL_RXE 0x00000200 // UART Receive Enable +#define UART_CTL_TXE 0x00000100 // UART Transmit Enable +#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable +#define UART_CTL_HSE 0x00000020 // High-Speed Enable +#define UART_CTL_EOT 0x00000010 // End of Transmission +#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support +#define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode +#define UART_CTL_SIREN 0x00000002 // UART SIR Enable +#define UART_CTL_UARTEN 0x00000001 // UART Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_IFLS register. +// +//***************************************************************************** +#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO + // Level Select +#define UART_IFLS_RX1_8 0x00000000 // RX FIFO >= 1/8 full +#define UART_IFLS_RX2_8 0x00000008 // RX FIFO >= 1/4 full +#define UART_IFLS_RX4_8 0x00000010 // RX FIFO >= 1/2 full (default) +#define UART_IFLS_RX6_8 0x00000018 // RX FIFO >= 3/4 full +#define UART_IFLS_RX7_8 0x00000020 // RX FIFO >= 7/8 full +#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO + // Level Select +#define UART_IFLS_TX1_8 0x00000000 // TX FIFO <= 1/8 full +#define UART_IFLS_TX2_8 0x00000001 // TX FIFO <= 1/4 full +#define UART_IFLS_TX4_8 0x00000002 // TX FIFO <= 1/2 full (default) +#define UART_IFLS_TX6_8 0x00000003 // TX FIFO <= 3/4 full +#define UART_IFLS_TX7_8 0x00000004 // TX FIFO <= 7/8 full + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_IM register. +// +//***************************************************************************** +#define UART_IM_DMATXIM 0x00020000 // Transmit DMA Interrupt Mask +#define UART_IM_DMARXIM 0x00010000 // Receive DMA Interrupt Mask +#define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask +#define UART_IM_EOTIM 0x00000800 // End of Transmission Interrupt + // Mask +#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt + // Mask +#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask +#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask +#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt + // Mask +#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt + // Mask +#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask +#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask +#define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem + // Interrupt Mask +#define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem + // Interrupt Mask +#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem + // Interrupt Mask +#define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem + // Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_RIS register. +// +//***************************************************************************** +#define UART_RIS_DMATXRIS 0x00020000 // Transmit DMA Raw Interrupt + // Status +#define UART_RIS_DMARXRIS 0x00010000 // Receive DMA Raw Interrupt Status +#define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status +#define UART_RIS_EOTRIS 0x00000800 // End of Transmission Raw + // Interrupt Status +#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt + // Status +#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt + // Status +#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt + // Status +#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt + // Status +#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw + // Interrupt Status +#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt + // Status +#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt + // Status +#define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw + // Interrupt Status +#define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect Modem + // Raw Interrupt Status +#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw + // Interrupt Status +#define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_MIS register. +// +//***************************************************************************** +#define UART_MIS_DMATXMIS 0x00020000 // Transmit DMA Masked Interrupt + // Status +#define UART_MIS_DMARXMIS 0x00010000 // Receive DMA Masked Interrupt + // Status +#define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt + // Status +#define UART_MIS_EOTMIS 0x00000800 // End of Transmission Masked + // Interrupt Status +#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked + // Interrupt Status +#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked + // Interrupt Status +#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked + // Interrupt Status +#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked + // Interrupt Status +#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked + // Interrupt Status +#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt + // Status +#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt + // Status +#define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked + // Interrupt Status +#define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect Modem + // Masked Interrupt Status +#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked + // Interrupt Status +#define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ICR register. +// +//***************************************************************************** +#define UART_ICR_DMATXIC 0x00020000 // Transmit DMA Interrupt Clear +#define UART_ICR_DMARXIC 0x00010000 // Receive DMA Interrupt Clear +#define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear +#define UART_ICR_EOTIC 0x00000800 // End of Transmission Interrupt + // Clear +#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear +#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear +#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear +#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear +#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear +#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear +#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear +#define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem + // Interrupt Clear +#define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect Modem + // Interrupt Clear +#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem + // Interrupt Clear +#define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem + // Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_DMACTL register. +// +//***************************************************************************** +#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error +#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable +#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_9BITADDR +// register. +// +//***************************************************************************** +#define UART_9BITADDR_9BITEN 0x00008000 // Enable 9-Bit Mode +#define UART_9BITADDR_ADDR_M 0x000000FF // Self Address for 9-Bit Mode +#define UART_9BITADDR_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_9BITAMASK +// register. +// +//***************************************************************************** +#define UART_9BITAMASK_MASK_M 0x000000FF // Self Address Mask for 9-Bit Mode +#define UART_9BITAMASK_MASK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_PP register. +// +//***************************************************************************** +#define UART_PP_MSE 0x00000008 // Modem Support Extended +#define UART_PP_MS 0x00000004 // Modem Support +#define UART_PP_NB 0x00000002 // 9-Bit Support +#define UART_PP_SC 0x00000001 // Smart Card Support + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_CC register. +// +//***************************************************************************** +#define UART_CC_CS_M 0x0000000F // UART Baud Clock Source +#define UART_CC_CS_SYSCLK 0x00000000 // System clock (based on clock + // source and divisor factor) +#define UART_CC_CS_PIOSC 0x00000005 // PIOSC + +#endif // __HW_UART_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_udma.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_udma.h new file mode 100644 index 0000000000000000000000000000000000000000..1d52b0090194e2600649a724fd3c3779e0acb2e7 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_udma.h @@ -0,0 +1,414 @@ +//***************************************************************************** +// +// hw_udma.h - Macros for use in accessing the UDMA registers. +// +// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_UDMA_H__ +#define __HW_UDMA_H__ + +//***************************************************************************** +// +// The following are defines for the Micro Direct Memory Access register +// addresses. +// +//***************************************************************************** +#define UDMA_STAT 0x400FF000 // DMA Status +#define UDMA_CFG 0x400FF004 // DMA Configuration +#define UDMA_CTLBASE 0x400FF008 // DMA Channel Control Base Pointer +#define UDMA_ALTBASE 0x400FF00C // DMA Alternate Channel Control + // Base Pointer +#define UDMA_WAITSTAT 0x400FF010 // DMA Channel Wait-on-Request + // Status +#define UDMA_SWREQ 0x400FF014 // DMA Channel Software Request +#define UDMA_USEBURSTSET 0x400FF018 // DMA Channel Useburst Set +#define UDMA_USEBURSTCLR 0x400FF01C // DMA Channel Useburst Clear +#define UDMA_REQMASKSET 0x400FF020 // DMA Channel Request Mask Set +#define UDMA_REQMASKCLR 0x400FF024 // DMA Channel Request Mask Clear +#define UDMA_ENASET 0x400FF028 // DMA Channel Enable Set +#define UDMA_ENACLR 0x400FF02C // DMA Channel Enable Clear +#define UDMA_ALTSET 0x400FF030 // DMA Channel Primary Alternate + // Set +#define UDMA_ALTCLR 0x400FF034 // DMA Channel Primary Alternate + // Clear +#define UDMA_PRIOSET 0x400FF038 // DMA Channel Priority Set +#define UDMA_PRIOCLR 0x400FF03C // DMA Channel Priority Clear +#define UDMA_ERRCLR 0x400FF04C // DMA Bus Error Clear +#define UDMA_CHASGN 0x400FF500 // DMA Channel Assignment +#define UDMA_CHIS 0x400FF504 // DMA Channel Interrupt Status +#define UDMA_CHMAP0 0x400FF510 // DMA Channel Map Select 0 +#define UDMA_CHMAP1 0x400FF514 // DMA Channel Map Select 1 +#define UDMA_CHMAP2 0x400FF518 // DMA Channel Map Select 2 +#define UDMA_CHMAP3 0x400FF51C // DMA Channel Map Select 3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_STAT register. +// +//***************************************************************************** +#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available uDMA Channels Minus 1 +#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine Status +#define UDMA_STAT_STATE_IDLE 0x00000000 // Idle +#define UDMA_STAT_STATE_RD_CTRL 0x00000010 // Reading channel controller data +#define UDMA_STAT_STATE_RD_SRCENDP \ + 0x00000020 // Reading source end pointer +#define UDMA_STAT_STATE_RD_DSTENDP \ + 0x00000030 // Reading destination end pointer +#define UDMA_STAT_STATE_RD_SRCDAT \ + 0x00000040 // Reading source data +#define UDMA_STAT_STATE_WR_DSTDAT \ + 0x00000050 // Writing destination data +#define UDMA_STAT_STATE_WAIT 0x00000060 // Waiting for uDMA request to + // clear +#define UDMA_STAT_STATE_WR_CTRL 0x00000070 // Writing channel controller data +#define UDMA_STAT_STATE_STALL 0x00000080 // Stalled +#define UDMA_STAT_STATE_DONE 0x00000090 // Done +#define UDMA_STAT_STATE_UNDEF 0x000000A0 // Undefined +#define UDMA_STAT_MASTEN 0x00000001 // Master Enable Status +#define UDMA_STAT_DMACHANS_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CFG register. +// +//***************************************************************************** +#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CTLBASE register. +// +//***************************************************************************** +#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address +#define UDMA_CTLBASE_ADDR_S 10 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ALTBASE register. +// +//***************************************************************************** +#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address + // Pointer +#define UDMA_ALTBASE_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_WAITSTAT register. +// +//***************************************************************************** +#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF // Channel [n] Wait Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_SWREQ register. +// +//***************************************************************************** +#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_USEBURSTSET +// register. +// +//***************************************************************************** +#define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF // Channel [n] Useburst Set + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_USEBURSTCLR +// register. +// +//***************************************************************************** +#define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF // Channel [n] Useburst Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_REQMASKSET +// register. +// +//***************************************************************************** +#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_REQMASKCLR +// register. +// +//***************************************************************************** +#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ENASET register. +// +//***************************************************************************** +#define UDMA_ENASET_SET_M 0xFFFFFFFF // Channel [n] Enable Set + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ENACLR register. +// +//***************************************************************************** +#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ALTSET register. +// +//***************************************************************************** +#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ALTCLR register. +// +//***************************************************************************** +#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_PRIOSET register. +// +//***************************************************************************** +#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_PRIOCLR register. +// +//***************************************************************************** +#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ERRCLR register. +// +//***************************************************************************** +#define UDMA_ERRCLR_ERRCLR 0x00000001 // uDMA Bus Error Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHASGN register. +// +//***************************************************************************** +#define UDMA_CHASGN_M 0xFFFFFFFF // Channel [n] Assignment Select +#define UDMA_CHASGN_PRIMARY 0x00000000 // Use the primary channel + // assignment +#define UDMA_CHASGN_SECONDARY 0x00000001 // Use the secondary channel + // assignment + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHIS register. +// +//***************************************************************************** +#define UDMA_CHIS_M 0xFFFFFFFF // Channel [n] Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHMAP0 register. +// +//***************************************************************************** +#define UDMA_CHMAP0_CH7SEL_M 0xF0000000 // uDMA Channel 7 Source Select +#define UDMA_CHMAP0_CH6SEL_M 0x0F000000 // uDMA Channel 6 Source Select +#define UDMA_CHMAP0_CH5SEL_M 0x00F00000 // uDMA Channel 5 Source Select +#define UDMA_CHMAP0_CH4SEL_M 0x000F0000 // uDMA Channel 4 Source Select +#define UDMA_CHMAP0_CH3SEL_M 0x0000F000 // uDMA Channel 3 Source Select +#define UDMA_CHMAP0_CH2SEL_M 0x00000F00 // uDMA Channel 2 Source Select +#define UDMA_CHMAP0_CH1SEL_M 0x000000F0 // uDMA Channel 1 Source Select +#define UDMA_CHMAP0_CH0SEL_M 0x0000000F // uDMA Channel 0 Source Select +#define UDMA_CHMAP0_CH7SEL_S 28 +#define UDMA_CHMAP0_CH6SEL_S 24 +#define UDMA_CHMAP0_CH5SEL_S 20 +#define UDMA_CHMAP0_CH4SEL_S 16 +#define UDMA_CHMAP0_CH3SEL_S 12 +#define UDMA_CHMAP0_CH2SEL_S 8 +#define UDMA_CHMAP0_CH1SEL_S 4 +#define UDMA_CHMAP0_CH0SEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHMAP1 register. +// +//***************************************************************************** +#define UDMA_CHMAP1_CH15SEL_M 0xF0000000 // uDMA Channel 15 Source Select +#define UDMA_CHMAP1_CH14SEL_M 0x0F000000 // uDMA Channel 14 Source Select +#define UDMA_CHMAP1_CH13SEL_M 0x00F00000 // uDMA Channel 13 Source Select +#define UDMA_CHMAP1_CH12SEL_M 0x000F0000 // uDMA Channel 12 Source Select +#define UDMA_CHMAP1_CH11SEL_M 0x0000F000 // uDMA Channel 11 Source Select +#define UDMA_CHMAP1_CH10SEL_M 0x00000F00 // uDMA Channel 10 Source Select +#define UDMA_CHMAP1_CH9SEL_M 0x000000F0 // uDMA Channel 9 Source Select +#define UDMA_CHMAP1_CH8SEL_M 0x0000000F // uDMA Channel 8 Source Select +#define UDMA_CHMAP1_CH15SEL_S 28 +#define UDMA_CHMAP1_CH14SEL_S 24 +#define UDMA_CHMAP1_CH13SEL_S 20 +#define UDMA_CHMAP1_CH12SEL_S 16 +#define UDMA_CHMAP1_CH11SEL_S 12 +#define UDMA_CHMAP1_CH10SEL_S 8 +#define UDMA_CHMAP1_CH9SEL_S 4 +#define UDMA_CHMAP1_CH8SEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHMAP2 register. +// +//***************************************************************************** +#define UDMA_CHMAP2_CH23SEL_M 0xF0000000 // uDMA Channel 23 Source Select +#define UDMA_CHMAP2_CH22SEL_M 0x0F000000 // uDMA Channel 22 Source Select +#define UDMA_CHMAP2_CH21SEL_M 0x00F00000 // uDMA Channel 21 Source Select +#define UDMA_CHMAP2_CH20SEL_M 0x000F0000 // uDMA Channel 20 Source Select +#define UDMA_CHMAP2_CH19SEL_M 0x0000F000 // uDMA Channel 19 Source Select +#define UDMA_CHMAP2_CH18SEL_M 0x00000F00 // uDMA Channel 18 Source Select +#define UDMA_CHMAP2_CH17SEL_M 0x000000F0 // uDMA Channel 17 Source Select +#define UDMA_CHMAP2_CH16SEL_M 0x0000000F // uDMA Channel 16 Source Select +#define UDMA_CHMAP2_CH23SEL_S 28 +#define UDMA_CHMAP2_CH22SEL_S 24 +#define UDMA_CHMAP2_CH21SEL_S 20 +#define UDMA_CHMAP2_CH20SEL_S 16 +#define UDMA_CHMAP2_CH19SEL_S 12 +#define UDMA_CHMAP2_CH18SEL_S 8 +#define UDMA_CHMAP2_CH17SEL_S 4 +#define UDMA_CHMAP2_CH16SEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHMAP3 register. +// +//***************************************************************************** +#define UDMA_CHMAP3_CH31SEL_M 0xF0000000 // uDMA Channel 31 Source Select +#define UDMA_CHMAP3_CH30SEL_M 0x0F000000 // uDMA Channel 30 Source Select +#define UDMA_CHMAP3_CH29SEL_M 0x00F00000 // uDMA Channel 29 Source Select +#define UDMA_CHMAP3_CH28SEL_M 0x000F0000 // uDMA Channel 28 Source Select +#define UDMA_CHMAP3_CH27SEL_M 0x0000F000 // uDMA Channel 27 Source Select +#define UDMA_CHMAP3_CH26SEL_M 0x00000F00 // uDMA Channel 26 Source Select +#define UDMA_CHMAP3_CH25SEL_M 0x000000F0 // uDMA Channel 25 Source Select +#define UDMA_CHMAP3_CH24SEL_M 0x0000000F // uDMA Channel 24 Source Select +#define UDMA_CHMAP3_CH31SEL_S 28 +#define UDMA_CHMAP3_CH30SEL_S 24 +#define UDMA_CHMAP3_CH29SEL_S 20 +#define UDMA_CHMAP3_CH28SEL_S 16 +#define UDMA_CHMAP3_CH27SEL_S 12 +#define UDMA_CHMAP3_CH26SEL_S 8 +#define UDMA_CHMAP3_CH25SEL_S 4 +#define UDMA_CHMAP3_CH24SEL_S 0 + +//***************************************************************************** +// +// The following are defines for the Micro Direct Memory Access (uDMA) offsets. +// +//***************************************************************************** +#define UDMA_O_SRCENDP 0x00000000 // DMA Channel Source Address End + // Pointer +#define UDMA_O_DSTENDP 0x00000004 // DMA Channel Destination Address + // End Pointer +#define UDMA_O_CHCTL 0x00000008 // DMA Channel Control Word + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_SRCENDP register. +// +//***************************************************************************** +#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer +#define UDMA_SRCENDP_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_DSTENDP register. +// +//***************************************************************************** +#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer +#define UDMA_DSTENDP_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CHCTL register. +// +//***************************************************************************** +#define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment +#define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte +#define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word +#define UDMA_CHCTL_DSTINC_32 0x80000000 // Word +#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment +#define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size +#define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte +#define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word +#define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word +#define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment +#define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte +#define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word +#define UDMA_CHCTL_SRCINC_32 0x08000000 // Word +#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment +#define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size +#define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte +#define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word +#define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word +#define UDMA_CHCTL_DSTPROT0 0x00200000 // Destination Privilege Access +#define UDMA_CHCTL_SRCPROT0 0x00040000 // Source Privilege Access +#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size +#define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer +#define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers +#define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers +#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers +#define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers +#define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers +#define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers +#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers +#define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers +#define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers +#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers +#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1) +#define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst +#define UDMA_CHCTL_XFERMODE_M 0x00000007 // uDMA Transfer Mode +#define UDMA_CHCTL_XFERMODE_STOP \ + 0x00000000 // Stop +#define UDMA_CHCTL_XFERMODE_BASIC \ + 0x00000001 // Basic +#define UDMA_CHCTL_XFERMODE_AUTO \ + 0x00000002 // Auto-Request +#define UDMA_CHCTL_XFERMODE_PINGPONG \ + 0x00000003 // Ping-Pong +#define UDMA_CHCTL_XFERMODE_MEM_SG \ + 0x00000004 // Memory Scatter-Gather +#define UDMA_CHCTL_XFERMODE_MEM_SGA \ + 0x00000005 // Alternate Memory Scatter-Gather +#define UDMA_CHCTL_XFERMODE_PER_SG \ + 0x00000006 // Peripheral Scatter-Gather +#define UDMA_CHCTL_XFERMODE_PER_SGA \ + 0x00000007 // Alternate Peripheral + // Scatter-Gather +#define UDMA_CHCTL_XFERSIZE_S 4 + +#endif // __HW_UDMA_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_usb.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_usb.h new file mode 100644 index 0000000000000000000000000000000000000000..7aa3b50a29fea792771f981197a5b2f8b126099f --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_usb.h @@ -0,0 +1,3032 @@ +//***************************************************************************** +// +// hw_usb.h - Macros for use in accessing the USB registers. +// +// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_USB_H__ +#define __HW_USB_H__ + +//***************************************************************************** +// +// The following are defines for the Univeral Serial Bus register offsets. +// +//***************************************************************************** +#define USB_O_FADDR 0x00000000 // USB Device Functional Address +#define USB_O_POWER 0x00000001 // USB Power +#define USB_O_TXIS 0x00000002 // USB Transmit Interrupt Status +#define USB_O_RXIS 0x00000004 // USB Receive Interrupt Status +#define USB_O_TXIE 0x00000006 // USB Transmit Interrupt Enable +#define USB_O_RXIE 0x00000008 // USB Receive Interrupt Enable +#define USB_O_IS 0x0000000A // USB General Interrupt Status +#define USB_O_IE 0x0000000B // USB Interrupt Enable +#define USB_O_FRAME 0x0000000C // USB Frame Value +#define USB_O_EPIDX 0x0000000E // USB Endpoint Index +#define USB_O_TEST 0x0000000F // USB Test Mode +#define USB_O_FIFO0 0x00000020 // USB FIFO Endpoint 0 +#define USB_O_FIFO1 0x00000024 // USB FIFO Endpoint 1 +#define USB_O_FIFO2 0x00000028 // USB FIFO Endpoint 2 +#define USB_O_FIFO3 0x0000002C // USB FIFO Endpoint 3 +#define USB_O_FIFO4 0x00000030 // USB FIFO Endpoint 4 +#define USB_O_FIFO5 0x00000034 // USB FIFO Endpoint 5 +#define USB_O_FIFO6 0x00000038 // USB FIFO Endpoint 6 +#define USB_O_FIFO7 0x0000003C // USB FIFO Endpoint 7 +#define USB_O_DEVCTL 0x00000060 // USB Device Control +#define USB_O_CCONF 0x00000061 // USB Common Configuration +#define USB_O_TXFIFOSZ 0x00000062 // USB Transmit Dynamic FIFO Sizing +#define USB_O_RXFIFOSZ 0x00000063 // USB Receive Dynamic FIFO Sizing +#define USB_O_TXFIFOADD 0x00000064 // USB Transmit FIFO Start Address +#define USB_O_RXFIFOADD 0x00000066 // USB Receive FIFO Start Address +#define USB_O_ULPIVBUSCTL 0x00000070 // USB ULPI VBUS Control +#define USB_O_ULPIREGDATA 0x00000074 // USB ULPI Register Data +#define USB_O_ULPIREGADDR 0x00000075 // USB ULPI Register Address +#define USB_O_ULPIREGCTL 0x00000076 // USB ULPI Register Control +#define USB_O_EPINFO 0x00000078 // USB Endpoint Information +#define USB_O_RAMINFO 0x00000079 // USB RAM Information +#define USB_O_CONTIM 0x0000007A // USB Connect Timing +#define USB_O_VPLEN 0x0000007B // USB OTG VBUS Pulse Timing +#define USB_O_HSEOF 0x0000007C // USB High-Speed Last Transaction + // to End of Frame Timing +#define USB_O_FSEOF 0x0000007D // USB Full-Speed Last Transaction + // to End of Frame Timing +#define USB_O_LSEOF 0x0000007E // USB Low-Speed Last Transaction + // to End of Frame Timing +#define USB_O_TXFUNCADDR0 0x00000080 // USB Transmit Functional Address + // Endpoint 0 +#define USB_O_TXHUBADDR0 0x00000082 // USB Transmit Hub Address + // Endpoint 0 +#define USB_O_TXHUBPORT0 0x00000083 // USB Transmit Hub Port Endpoint 0 +#define USB_O_TXFUNCADDR1 0x00000088 // USB Transmit Functional Address + // Endpoint 1 +#define USB_O_TXHUBADDR1 0x0000008A // USB Transmit Hub Address + // Endpoint 1 +#define USB_O_TXHUBPORT1 0x0000008B // USB Transmit Hub Port Endpoint 1 +#define USB_O_RXFUNCADDR1 0x0000008C // USB Receive Functional Address + // Endpoint 1 +#define USB_O_RXHUBADDR1 0x0000008E // USB Receive Hub Address Endpoint + // 1 +#define USB_O_RXHUBPORT1 0x0000008F // USB Receive Hub Port Endpoint 1 +#define USB_O_TXFUNCADDR2 0x00000090 // USB Transmit Functional Address + // Endpoint 2 +#define USB_O_TXHUBADDR2 0x00000092 // USB Transmit Hub Address + // Endpoint 2 +#define USB_O_TXHUBPORT2 0x00000093 // USB Transmit Hub Port Endpoint 2 +#define USB_O_RXFUNCADDR2 0x00000094 // USB Receive Functional Address + // Endpoint 2 +#define USB_O_RXHUBADDR2 0x00000096 // USB Receive Hub Address Endpoint + // 2 +#define USB_O_RXHUBPORT2 0x00000097 // USB Receive Hub Port Endpoint 2 +#define USB_O_TXFUNCADDR3 0x00000098 // USB Transmit Functional Address + // Endpoint 3 +#define USB_O_TXHUBADDR3 0x0000009A // USB Transmit Hub Address + // Endpoint 3 +#define USB_O_TXHUBPORT3 0x0000009B // USB Transmit Hub Port Endpoint 3 +#define USB_O_RXFUNCADDR3 0x0000009C // USB Receive Functional Address + // Endpoint 3 +#define USB_O_RXHUBADDR3 0x0000009E // USB Receive Hub Address Endpoint + // 3 +#define USB_O_RXHUBPORT3 0x0000009F // USB Receive Hub Port Endpoint 3 +#define USB_O_TXFUNCADDR4 0x000000A0 // USB Transmit Functional Address + // Endpoint 4 +#define USB_O_TXHUBADDR4 0x000000A2 // USB Transmit Hub Address + // Endpoint 4 +#define USB_O_TXHUBPORT4 0x000000A3 // USB Transmit Hub Port Endpoint 4 +#define USB_O_RXFUNCADDR4 0x000000A4 // USB Receive Functional Address + // Endpoint 4 +#define USB_O_RXHUBADDR4 0x000000A6 // USB Receive Hub Address Endpoint + // 4 +#define USB_O_RXHUBPORT4 0x000000A7 // USB Receive Hub Port Endpoint 4 +#define USB_O_TXFUNCADDR5 0x000000A8 // USB Transmit Functional Address + // Endpoint 5 +#define USB_O_TXHUBADDR5 0x000000AA // USB Transmit Hub Address + // Endpoint 5 +#define USB_O_TXHUBPORT5 0x000000AB // USB Transmit Hub Port Endpoint 5 +#define USB_O_RXFUNCADDR5 0x000000AC // USB Receive Functional Address + // Endpoint 5 +#define USB_O_RXHUBADDR5 0x000000AE // USB Receive Hub Address Endpoint + // 5 +#define USB_O_RXHUBPORT5 0x000000AF // USB Receive Hub Port Endpoint 5 +#define USB_O_TXFUNCADDR6 0x000000B0 // USB Transmit Functional Address + // Endpoint 6 +#define USB_O_TXHUBADDR6 0x000000B2 // USB Transmit Hub Address + // Endpoint 6 +#define USB_O_TXHUBPORT6 0x000000B3 // USB Transmit Hub Port Endpoint 6 +#define USB_O_RXFUNCADDR6 0x000000B4 // USB Receive Functional Address + // Endpoint 6 +#define USB_O_RXHUBADDR6 0x000000B6 // USB Receive Hub Address Endpoint + // 6 +#define USB_O_RXHUBPORT6 0x000000B7 // USB Receive Hub Port Endpoint 6 +#define USB_O_TXFUNCADDR7 0x000000B8 // USB Transmit Functional Address + // Endpoint 7 +#define USB_O_TXHUBADDR7 0x000000BA // USB Transmit Hub Address + // Endpoint 7 +#define USB_O_TXHUBPORT7 0x000000BB // USB Transmit Hub Port Endpoint 7 +#define USB_O_RXFUNCADDR7 0x000000BC // USB Receive Functional Address + // Endpoint 7 +#define USB_O_RXHUBADDR7 0x000000BE // USB Receive Hub Address Endpoint + // 7 +#define USB_O_RXHUBPORT7 0x000000BF // USB Receive Hub Port Endpoint 7 +#define USB_O_CSRL0 0x00000102 // USB Control and Status Endpoint + // 0 Low +#define USB_O_CSRH0 0x00000103 // USB Control and Status Endpoint + // 0 High +#define USB_O_COUNT0 0x00000108 // USB Receive Byte Count Endpoint + // 0 +#define USB_O_TYPE0 0x0000010A // USB Type Endpoint 0 +#define USB_O_NAKLMT 0x0000010B // USB NAK Limit +#define USB_O_TXMAXP1 0x00000110 // USB Maximum Transmit Data + // Endpoint 1 +#define USB_O_TXCSRL1 0x00000112 // USB Transmit Control and Status + // Endpoint 1 Low +#define USB_O_TXCSRH1 0x00000113 // USB Transmit Control and Status + // Endpoint 1 High +#define USB_O_RXMAXP1 0x00000114 // USB Maximum Receive Data + // Endpoint 1 +#define USB_O_RXCSRL1 0x00000116 // USB Receive Control and Status + // Endpoint 1 Low +#define USB_O_RXCSRH1 0x00000117 // USB Receive Control and Status + // Endpoint 1 High +#define USB_O_RXCOUNT1 0x00000118 // USB Receive Byte Count Endpoint + // 1 +#define USB_O_TXTYPE1 0x0000011A // USB Host Transmit Configure Type + // Endpoint 1 +#define USB_O_TXINTERVAL1 0x0000011B // USB Host Transmit Interval + // Endpoint 1 +#define USB_O_RXTYPE1 0x0000011C // USB Host Configure Receive Type + // Endpoint 1 +#define USB_O_RXINTERVAL1 0x0000011D // USB Host Receive Polling + // Interval Endpoint 1 +#define USB_O_TXMAXP2 0x00000120 // USB Maximum Transmit Data + // Endpoint 2 +#define USB_O_TXCSRL2 0x00000122 // USB Transmit Control and Status + // Endpoint 2 Low +#define USB_O_TXCSRH2 0x00000123 // USB Transmit Control and Status + // Endpoint 2 High +#define USB_O_RXMAXP2 0x00000124 // USB Maximum Receive Data + // Endpoint 2 +#define USB_O_RXCSRL2 0x00000126 // USB Receive Control and Status + // Endpoint 2 Low +#define USB_O_RXCSRH2 0x00000127 // USB Receive Control and Status + // Endpoint 2 High +#define USB_O_RXCOUNT2 0x00000128 // USB Receive Byte Count Endpoint + // 2 +#define USB_O_TXTYPE2 0x0000012A // USB Host Transmit Configure Type + // Endpoint 2 +#define USB_O_TXINTERVAL2 0x0000012B // USB Host Transmit Interval + // Endpoint 2 +#define USB_O_RXTYPE2 0x0000012C // USB Host Configure Receive Type + // Endpoint 2 +#define USB_O_RXINTERVAL2 0x0000012D // USB Host Receive Polling + // Interval Endpoint 2 +#define USB_O_TXMAXP3 0x00000130 // USB Maximum Transmit Data + // Endpoint 3 +#define USB_O_TXCSRL3 0x00000132 // USB Transmit Control and Status + // Endpoint 3 Low +#define USB_O_TXCSRH3 0x00000133 // USB Transmit Control and Status + // Endpoint 3 High +#define USB_O_RXMAXP3 0x00000134 // USB Maximum Receive Data + // Endpoint 3 +#define USB_O_RXCSRL3 0x00000136 // USB Receive Control and Status + // Endpoint 3 Low +#define USB_O_RXCSRH3 0x00000137 // USB Receive Control and Status + // Endpoint 3 High +#define USB_O_RXCOUNT3 0x00000138 // USB Receive Byte Count Endpoint + // 3 +#define USB_O_TXTYPE3 0x0000013A // USB Host Transmit Configure Type + // Endpoint 3 +#define USB_O_TXINTERVAL3 0x0000013B // USB Host Transmit Interval + // Endpoint 3 +#define USB_O_RXTYPE3 0x0000013C // USB Host Configure Receive Type + // Endpoint 3 +#define USB_O_RXINTERVAL3 0x0000013D // USB Host Receive Polling + // Interval Endpoint 3 +#define USB_O_TXMAXP4 0x00000140 // USB Maximum Transmit Data + // Endpoint 4 +#define USB_O_TXCSRL4 0x00000142 // USB Transmit Control and Status + // Endpoint 4 Low +#define USB_O_TXCSRH4 0x00000143 // USB Transmit Control and Status + // Endpoint 4 High +#define USB_O_RXMAXP4 0x00000144 // USB Maximum Receive Data + // Endpoint 4 +#define USB_O_RXCSRL4 0x00000146 // USB Receive Control and Status + // Endpoint 4 Low +#define USB_O_RXCSRH4 0x00000147 // USB Receive Control and Status + // Endpoint 4 High +#define USB_O_RXCOUNT4 0x00000148 // USB Receive Byte Count Endpoint + // 4 +#define USB_O_TXTYPE4 0x0000014A // USB Host Transmit Configure Type + // Endpoint 4 +#define USB_O_TXINTERVAL4 0x0000014B // USB Host Transmit Interval + // Endpoint 4 +#define USB_O_RXTYPE4 0x0000014C // USB Host Configure Receive Type + // Endpoint 4 +#define USB_O_RXINTERVAL4 0x0000014D // USB Host Receive Polling + // Interval Endpoint 4 +#define USB_O_TXMAXP5 0x00000150 // USB Maximum Transmit Data + // Endpoint 5 +#define USB_O_TXCSRL5 0x00000152 // USB Transmit Control and Status + // Endpoint 5 Low +#define USB_O_TXCSRH5 0x00000153 // USB Transmit Control and Status + // Endpoint 5 High +#define USB_O_RXMAXP5 0x00000154 // USB Maximum Receive Data + // Endpoint 5 +#define USB_O_RXCSRL5 0x00000156 // USB Receive Control and Status + // Endpoint 5 Low +#define USB_O_RXCSRH5 0x00000157 // USB Receive Control and Status + // Endpoint 5 High +#define USB_O_RXCOUNT5 0x00000158 // USB Receive Byte Count Endpoint + // 5 +#define USB_O_TXTYPE5 0x0000015A // USB Host Transmit Configure Type + // Endpoint 5 +#define USB_O_TXINTERVAL5 0x0000015B // USB Host Transmit Interval + // Endpoint 5 +#define USB_O_RXTYPE5 0x0000015C // USB Host Configure Receive Type + // Endpoint 5 +#define USB_O_RXINTERVAL5 0x0000015D // USB Host Receive Polling + // Interval Endpoint 5 +#define USB_O_TXMAXP6 0x00000160 // USB Maximum Transmit Data + // Endpoint 6 +#define USB_O_TXCSRL6 0x00000162 // USB Transmit Control and Status + // Endpoint 6 Low +#define USB_O_TXCSRH6 0x00000163 // USB Transmit Control and Status + // Endpoint 6 High +#define USB_O_RXMAXP6 0x00000164 // USB Maximum Receive Data + // Endpoint 6 +#define USB_O_RXCSRL6 0x00000166 // USB Receive Control and Status + // Endpoint 6 Low +#define USB_O_RXCSRH6 0x00000167 // USB Receive Control and Status + // Endpoint 6 High +#define USB_O_RXCOUNT6 0x00000168 // USB Receive Byte Count Endpoint + // 6 +#define USB_O_TXTYPE6 0x0000016A // USB Host Transmit Configure Type + // Endpoint 6 +#define USB_O_TXINTERVAL6 0x0000016B // USB Host Transmit Interval + // Endpoint 6 +#define USB_O_RXTYPE6 0x0000016C // USB Host Configure Receive Type + // Endpoint 6 +#define USB_O_RXINTERVAL6 0x0000016D // USB Host Receive Polling + // Interval Endpoint 6 +#define USB_O_TXMAXP7 0x00000170 // USB Maximum Transmit Data + // Endpoint 7 +#define USB_O_TXCSRL7 0x00000172 // USB Transmit Control and Status + // Endpoint 7 Low +#define USB_O_TXCSRH7 0x00000173 // USB Transmit Control and Status + // Endpoint 7 High +#define USB_O_RXMAXP7 0x00000174 // USB Maximum Receive Data + // Endpoint 7 +#define USB_O_RXCSRL7 0x00000176 // USB Receive Control and Status + // Endpoint 7 Low +#define USB_O_RXCSRH7 0x00000177 // USB Receive Control and Status + // Endpoint 7 High +#define USB_O_RXCOUNT7 0x00000178 // USB Receive Byte Count Endpoint + // 7 +#define USB_O_TXTYPE7 0x0000017A // USB Host Transmit Configure Type + // Endpoint 7 +#define USB_O_TXINTERVAL7 0x0000017B // USB Host Transmit Interval + // Endpoint 7 +#define USB_O_RXTYPE7 0x0000017C // USB Host Configure Receive Type + // Endpoint 7 +#define USB_O_RXINTERVAL7 0x0000017D // USB Host Receive Polling + // Interval Endpoint 7 +#define USB_O_DMAINTR 0x00000200 // USB DMA Interrupt +#define USB_O_DMACTL0 0x00000204 // USB DMA Control 0 +#define USB_O_DMAADDR0 0x00000208 // USB DMA Address 0 +#define USB_O_DMACOUNT0 0x0000020C // USB DMA Count 0 +#define USB_O_DMACTL1 0x00000214 // USB DMA Control 1 +#define USB_O_DMAADDR1 0x00000218 // USB DMA Address 1 +#define USB_O_DMACOUNT1 0x0000021C // USB DMA Count 1 +#define USB_O_DMACTL2 0x00000224 // USB DMA Control 2 +#define USB_O_DMAADDR2 0x00000228 // USB DMA Address 2 +#define USB_O_DMACOUNT2 0x0000022C // USB DMA Count 2 +#define USB_O_DMACTL3 0x00000234 // USB DMA Control 3 +#define USB_O_DMAADDR3 0x00000238 // USB DMA Address 3 +#define USB_O_DMACOUNT3 0x0000023C // USB DMA Count 3 +#define USB_O_DMACTL4 0x00000244 // USB DMA Control 4 +#define USB_O_DMAADDR4 0x00000248 // USB DMA Address 4 +#define USB_O_DMACOUNT4 0x0000024C // USB DMA Count 4 +#define USB_O_DMACTL5 0x00000254 // USB DMA Control 5 +#define USB_O_DMAADDR5 0x00000258 // USB DMA Address 5 +#define USB_O_DMACOUNT5 0x0000025C // USB DMA Count 5 +#define USB_O_DMACTL6 0x00000264 // USB DMA Control 6 +#define USB_O_DMAADDR6 0x00000268 // USB DMA Address 6 +#define USB_O_DMACOUNT6 0x0000026C // USB DMA Count 6 +#define USB_O_DMACTL7 0x00000274 // USB DMA Control 7 +#define USB_O_DMAADDR7 0x00000278 // USB DMA Address 7 +#define USB_O_DMACOUNT7 0x0000027C // USB DMA Count 7 +#define USB_O_RQPKTCOUNT1 0x00000304 // USB Request Packet Count in + // Block Transfer Endpoint 1 +#define USB_O_RQPKTCOUNT2 0x00000308 // USB Request Packet Count in + // Block Transfer Endpoint 2 +#define USB_O_RQPKTCOUNT3 0x0000030C // USB Request Packet Count in + // Block Transfer Endpoint 3 +#define USB_O_RQPKTCOUNT4 0x00000310 // USB Request Packet Count in + // Block Transfer Endpoint 4 +#define USB_O_RQPKTCOUNT5 0x00000314 // USB Request Packet Count in + // Block Transfer Endpoint 5 +#define USB_O_RQPKTCOUNT6 0x00000318 // USB Request Packet Count in + // Block Transfer Endpoint 6 +#define USB_O_RQPKTCOUNT7 0x0000031C // USB Request Packet Count in + // Block Transfer Endpoint 7 +#define USB_O_RXDPKTBUFDIS 0x00000340 // USB Receive Double Packet Buffer + // Disable +#define USB_O_TXDPKTBUFDIS 0x00000342 // USB Transmit Double Packet + // Buffer Disable +#define USB_O_CTO 0x00000344 // USB Chirp Timeout +#define USB_O_HHSRTN 0x00000346 // USB High Speed to UTM Operating + // Delay +#define USB_O_HSBT 0x00000348 // USB High Speed Time-out Adder +#define USB_O_LPMATTR 0x00000360 // USB LPM Attributes +#define USB_O_LPMCNTRL 0x00000362 // USB LPM Control +#define USB_O_LPMIM 0x00000363 // USB LPM Interrupt Mask +#define USB_O_LPMRIS 0x00000364 // USB LPM Raw Interrupt Status +#define USB_O_LPMFADDR 0x00000365 // USB LPM Function Address +#define USB_O_EPC 0x00000400 // USB External Power Control +#define USB_O_EPCRIS 0x00000404 // USB External Power Control Raw + // Interrupt Status +#define USB_O_EPCIM 0x00000408 // USB External Power Control + // Interrupt Mask +#define USB_O_EPCISC 0x0000040C // USB External Power Control + // Interrupt Status and Clear +#define USB_O_DRRIS 0x00000410 // USB Device RESUME Raw Interrupt + // Status +#define USB_O_DRIM 0x00000414 // USB Device RESUME Interrupt Mask +#define USB_O_DRISC 0x00000418 // USB Device RESUME Interrupt + // Status and Clear +#define USB_O_GPCS 0x0000041C // USB General-Purpose Control and + // Status +#define USB_O_VDC 0x00000430 // USB VBUS Droop Control +#define USB_O_VDCRIS 0x00000434 // USB VBUS Droop Control Raw + // Interrupt Status +#define USB_O_VDCIM 0x00000438 // USB VBUS Droop Control Interrupt + // Mask +#define USB_O_VDCISC 0x0000043C // USB VBUS Droop Control Interrupt + // Status and Clear +#define USB_O_IDVRIS 0x00000444 // USB ID Valid Detect Raw + // Interrupt Status +#define USB_O_IDVIM 0x00000448 // USB ID Valid Detect Interrupt + // Mask +#define USB_O_IDVISC 0x0000044C // USB ID Valid Detect Interrupt + // Status and Clear +#define USB_O_DMASEL 0x00000450 // USB DMA Select +#define USB_O_PP 0x00000FC0 // USB Peripheral Properties +#define USB_O_PC 0x00000FC4 // USB Peripheral Configuration +#define USB_O_CC 0x00000FC8 // USB Clock Configuration + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FADDR register. +// +//***************************************************************************** +#define USB_FADDR_M 0x0000007F // Function Address +#define USB_FADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_POWER register. +// +//***************************************************************************** +#define USB_POWER_ISOUP 0x00000080 // Isochronous Update +#define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect +#define USB_POWER_HSENAB 0x00000020 // High Speed Enable +#define USB_POWER_HSMODE 0x00000010 // High Speed Enable +#define USB_POWER_RESET 0x00000008 // RESET Signaling +#define USB_POWER_RESUME 0x00000004 // RESUME Signaling +#define USB_POWER_SUSPEND 0x00000002 // SUSPEND Mode +#define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXIS register. +// +//***************************************************************************** +#define USB_TXIS_EP7 0x00000080 // TX Endpoint 7 Interrupt +#define USB_TXIS_EP6 0x00000040 // TX Endpoint 6 Interrupt +#define USB_TXIS_EP5 0x00000020 // TX Endpoint 5 Interrupt +#define USB_TXIS_EP4 0x00000010 // TX Endpoint 4 Interrupt +#define USB_TXIS_EP3 0x00000008 // TX Endpoint 3 Interrupt +#define USB_TXIS_EP2 0x00000004 // TX Endpoint 2 Interrupt +#define USB_TXIS_EP1 0x00000002 // TX Endpoint 1 Interrupt +#define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXIS register. +// +//***************************************************************************** +#define USB_RXIS_EP7 0x00000080 // RX Endpoint 7 Interrupt +#define USB_RXIS_EP6 0x00000040 // RX Endpoint 6 Interrupt +#define USB_RXIS_EP5 0x00000020 // RX Endpoint 5 Interrupt +#define USB_RXIS_EP4 0x00000010 // RX Endpoint 4 Interrupt +#define USB_RXIS_EP3 0x00000008 // RX Endpoint 3 Interrupt +#define USB_RXIS_EP2 0x00000004 // RX Endpoint 2 Interrupt +#define USB_RXIS_EP1 0x00000002 // RX Endpoint 1 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXIE register. +// +//***************************************************************************** +#define USB_TXIE_EP7 0x00000080 // TX Endpoint 7 Interrupt Enable +#define USB_TXIE_EP6 0x00000040 // TX Endpoint 6 Interrupt Enable +#define USB_TXIE_EP5 0x00000020 // TX Endpoint 5 Interrupt Enable +#define USB_TXIE_EP4 0x00000010 // TX Endpoint 4 Interrupt Enable +#define USB_TXIE_EP3 0x00000008 // TX Endpoint 3 Interrupt Enable +#define USB_TXIE_EP2 0x00000004 // TX Endpoint 2 Interrupt Enable +#define USB_TXIE_EP1 0x00000002 // TX Endpoint 1 Interrupt Enable +#define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt + // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXIE register. +// +//***************************************************************************** +#define USB_RXIE_EP7 0x00000080 // RX Endpoint 7 Interrupt Enable +#define USB_RXIE_EP6 0x00000040 // RX Endpoint 6 Interrupt Enable +#define USB_RXIE_EP5 0x00000020 // RX Endpoint 5 Interrupt Enable +#define USB_RXIE_EP4 0x00000010 // RX Endpoint 4 Interrupt Enable +#define USB_RXIE_EP3 0x00000008 // RX Endpoint 3 Interrupt Enable +#define USB_RXIE_EP2 0x00000004 // RX Endpoint 2 Interrupt Enable +#define USB_RXIE_EP1 0x00000002 // RX Endpoint 1 Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IS register. +// +//***************************************************************************** +#define USB_IS_VBUSERR 0x00000080 // VBUS Error (OTG only) +#define USB_IS_SESREQ 0x00000040 // SESSION REQUEST (OTG only) +#define USB_IS_DISCON 0x00000020 // Session Disconnect (OTG only) +#define USB_IS_CONN 0x00000010 // Session Connect +#define USB_IS_SOF 0x00000008 // Start of Frame +#define USB_IS_BABBLE 0x00000004 // Babble Detected +#define USB_IS_RESET 0x00000004 // RESET Signaling Detected +#define USB_IS_RESUME 0x00000002 // RESUME Signaling Detected +#define USB_IS_SUSPEND 0x00000001 // SUSPEND Signaling Detected + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IE register. +// +//***************************************************************************** +#define USB_IE_VBUSERR 0x00000080 // Enable VBUS Error Interrupt (OTG + // only) +#define USB_IE_SESREQ 0x00000040 // Enable Session Request (OTG + // only) +#define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt +#define USB_IE_CONN 0x00000010 // Enable Connect Interrupt +#define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt +#define USB_IE_BABBLE 0x00000004 // Enable Babble Interrupt +#define USB_IE_RESET 0x00000004 // Enable RESET Interrupt +#define USB_IE_RESUME 0x00000002 // Enable RESUME Interrupt +#define USB_IE_SUSPND 0x00000001 // Enable SUSPEND Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FRAME register. +// +//***************************************************************************** +#define USB_FRAME_M 0x000007FF // Frame Number +#define USB_FRAME_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPIDX register. +// +//***************************************************************************** +#define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index +#define USB_EPIDX_EPIDX_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TEST register. +// +//***************************************************************************** +#define USB_TEST_FORCEH 0x00000080 // Force Host Mode +#define USB_TEST_FIFOACC 0x00000040 // FIFO Access +#define USB_TEST_FORCEFS 0x00000020 // Force Full-Speed Mode +#define USB_TEST_FORCEHS 0x00000010 // Force High-Speed Mode +#define USB_TEST_TESTPKT 0x00000008 // Test Packet Mode Enable +#define USB_TEST_TESTK 0x00000004 // Test_K Mode Enable +#define USB_TEST_TESTJ 0x00000002 // Test_J Mode Enable +#define USB_TEST_TESTSE0NAK 0x00000001 // Test_SE0_NAK Test Mode Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO0 register. +// +//***************************************************************************** +#define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO0_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO1 register. +// +//***************************************************************************** +#define USB_FIFO1_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO1_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO2 register. +// +//***************************************************************************** +#define USB_FIFO2_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO2_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO3 register. +// +//***************************************************************************** +#define USB_FIFO3_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO3_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO4 register. +// +//***************************************************************************** +#define USB_FIFO4_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO4_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO5 register. +// +//***************************************************************************** +#define USB_FIFO5_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO5_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO6 register. +// +//***************************************************************************** +#define USB_FIFO6_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO6_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO7 register. +// +//***************************************************************************** +#define USB_FIFO7_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO7_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DEVCTL register. +// +//***************************************************************************** +#define USB_DEVCTL_DEV 0x00000080 // Device Mode (OTG only) +#define USB_DEVCTL_FSDEV 0x00000040 // Full-Speed Device Detected +#define USB_DEVCTL_LSDEV 0x00000020 // Low-Speed Device Detected +#define USB_DEVCTL_VBUS_M 0x00000018 // VBUS Level (OTG only) +#define USB_DEVCTL_VBUS_NONE 0x00000000 // Below SessionEnd +#define USB_DEVCTL_VBUS_SEND 0x00000008 // Above SessionEnd, below AValid +#define USB_DEVCTL_VBUS_AVALID 0x00000010 // Above AValid, below VBUSValid +#define USB_DEVCTL_VBUS_VALID 0x00000018 // Above VBUSValid +#define USB_DEVCTL_HOST 0x00000004 // Host Mode +#define USB_DEVCTL_HOSTREQ 0x00000002 // Host Request (OTG only) +#define USB_DEVCTL_SESSION 0x00000001 // Session Start/End (OTG only) + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CCONF register. +// +//***************************************************************************** +#define USB_CCONF_TXEDMA 0x00000002 // TX Early DMA Enable +#define USB_CCONF_RXEDMA 0x00000001 // TX Early DMA Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFIFOSZ register. +// +//***************************************************************************** +#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support +#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size +#define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8 +#define USB_TXFIFOSZ_SIZE_16 0x00000001 // 16 +#define USB_TXFIFOSZ_SIZE_32 0x00000002 // 32 +#define USB_TXFIFOSZ_SIZE_64 0x00000003 // 64 +#define USB_TXFIFOSZ_SIZE_128 0x00000004 // 128 +#define USB_TXFIFOSZ_SIZE_256 0x00000005 // 256 +#define USB_TXFIFOSZ_SIZE_512 0x00000006 // 512 +#define USB_TXFIFOSZ_SIZE_1024 0x00000007 // 1024 +#define USB_TXFIFOSZ_SIZE_2048 0x00000008 // 2048 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFIFOSZ register. +// +//***************************************************************************** +#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support +#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size +#define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8 +#define USB_RXFIFOSZ_SIZE_16 0x00000001 // 16 +#define USB_RXFIFOSZ_SIZE_32 0x00000002 // 32 +#define USB_RXFIFOSZ_SIZE_64 0x00000003 // 64 +#define USB_RXFIFOSZ_SIZE_128 0x00000004 // 128 +#define USB_RXFIFOSZ_SIZE_256 0x00000005 // 256 +#define USB_RXFIFOSZ_SIZE_512 0x00000006 // 512 +#define USB_RXFIFOSZ_SIZE_1024 0x00000007 // 1024 +#define USB_RXFIFOSZ_SIZE_2048 0x00000008 // 2048 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFIFOADD +// register. +// +//***************************************************************************** +#define USB_TXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address +#define USB_TXFIFOADD_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFIFOADD +// register. +// +//***************************************************************************** +#define USB_RXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address +#define USB_RXFIFOADD_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_ULPIVBUSCTL +// register. +// +//***************************************************************************** +#define USB_ULPIVBUSCTL_USEEXTVBUSIND \ + 0x00000002 // Use External VBUS Indicator +#define USB_ULPIVBUSCTL_USEEXTVBUS \ + 0x00000001 // Use External VBUS + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_ULPIREGDATA +// register. +// +//***************************************************************************** +#define USB_ULPIREGDATA_REGDATA_M \ + 0x000000FF // Register Data +#define USB_ULPIREGDATA_REGDATA_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_ULPIREGADDR +// register. +// +//***************************************************************************** +#define USB_ULPIREGADDR_ADDR_M 0x000000FF // Register Address +#define USB_ULPIREGADDR_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_ULPIREGCTL +// register. +// +//***************************************************************************** +#define USB_ULPIREGCTL_RDWR 0x00000004 // Read/Write Control +#define USB_ULPIREGCTL_REGCMPLT 0x00000002 // Register Access Complete +#define USB_ULPIREGCTL_REGACC 0x00000001 // Initiate Register Access + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPINFO register. +// +//***************************************************************************** +#define USB_EPINFO_RXEP_M 0x000000F0 // RX Endpoints +#define USB_EPINFO_TXEP_M 0x0000000F // TX Endpoints +#define USB_EPINFO_RXEP_S 4 +#define USB_EPINFO_TXEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RAMINFO register. +// +//***************************************************************************** +#define USB_RAMINFO_DMACHAN_M 0x000000F0 // DMA Channels +#define USB_RAMINFO_RAMBITS_M 0x0000000F // RAM Address Bus Width +#define USB_RAMINFO_DMACHAN_S 4 +#define USB_RAMINFO_RAMBITS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CONTIM register. +// +//***************************************************************************** +#define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait +#define USB_CONTIM_WTID_M 0x0000000F // Wait ID +#define USB_CONTIM_WTCON_S 4 +#define USB_CONTIM_WTID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VPLEN register. +// +//***************************************************************************** +#define USB_VPLEN_VPLEN_M 0x000000FF // VBUS Pulse Length +#define USB_VPLEN_VPLEN_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_HSEOF register. +// +//***************************************************************************** +#define USB_HSEOF_HSEOFG_M 0x000000FF // HIgh-Speed End-of-Frame Gap +#define USB_HSEOF_HSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FSEOF register. +// +//***************************************************************************** +#define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap +#define USB_FSEOF_FSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LSEOF register. +// +//***************************************************************************** +#define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap +#define USB_LSEOF_LSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR0 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR0_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR0_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR0 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR0_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR0_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT0 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT0_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT0_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR1 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR1_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR1 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR1_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT1 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT1_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT1_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR1 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR1_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR1 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR1_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT1 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT1_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT1_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR2 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR2_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR2 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR2_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT2 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT2_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT2_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR2 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR2_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR2 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR2_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT2 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT2_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT2_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR3 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR3_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR3 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR3_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT3 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT3_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT3_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR3 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR3_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR3 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR3_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT3 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT3_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT3_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR4 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR4_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR4 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR4_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT4 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT4_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT4_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR4 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR4_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR4 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR4_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT4 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT4_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT4_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR5 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR5_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR5 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR5_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT5 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT5_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT5_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR5 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR5_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR5 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR5_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT5 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT5_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT5_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR6 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR6_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR6 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR6_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT6 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT6_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT6_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR6 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR6_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR6 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR6_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT6 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT6_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT6_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR7 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR7_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR7 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR7_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT7 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT7_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT7_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR7 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR7_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR7 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR7_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT7 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT7_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT7_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CSRL0 register. +// +//***************************************************************************** +#define USB_CSRL0_NAKTO 0x00000080 // NAK Timeout +#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear +#define USB_CSRL0_STATUS 0x00000040 // STATUS Packet +#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear +#define USB_CSRL0_REQPKT 0x00000020 // Request Packet +#define USB_CSRL0_STALL 0x00000020 // Send Stall +#define USB_CSRL0_SETEND 0x00000010 // Setup End +#define USB_CSRL0_ERROR 0x00000010 // Error +#define USB_CSRL0_DATAEND 0x00000008 // Data End +#define USB_CSRL0_SETUP 0x00000008 // Setup Packet +#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled +#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready +#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CSRH0 register. +// +//***************************************************************************** +#define USB_CSRH0_DISPING 0x00000008 // PING Disable +#define USB_CSRH0_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_CSRH0_DT 0x00000002 // Data Toggle +#define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_COUNT0 register. +// +//***************************************************************************** +#define USB_COUNT0_COUNT_M 0x0000007F // FIFO Count +#define USB_COUNT0_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TYPE0 register. +// +//***************************************************************************** +#define USB_TYPE0_SPEED_M 0x000000C0 // Operating Speed +#define USB_TYPE0_SPEED_HIGH 0x00000040 // High +#define USB_TYPE0_SPEED_FULL 0x00000080 // Full +#define USB_TYPE0_SPEED_LOW 0x000000C0 // Low + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_NAKLMT register. +// +//***************************************************************************** +#define USB_NAKLMT_NAKLMT_M 0x0000001F // EP0 NAK Limit +#define USB_NAKLMT_NAKLMT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP1 register. +// +//***************************************************************************** +#define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP1_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL1 register. +// +//***************************************************************************** +#define USB_TXCSRL1_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL1_STALL 0x00000010 // Send STALL +#define USB_TXCSRL1_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL1_ERROR 0x00000004 // Error +#define USB_TXCSRL1_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH1 register. +// +//***************************************************************************** +#define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH1_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH1_MODE 0x00000020 // Mode +#define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH1_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH1_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP1 register. +// +//***************************************************************************** +#define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP1_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL1 register. +// +//***************************************************************************** +#define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL1_STALL 0x00000020 // Send STALL +#define USB_RXCSRL1_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL1_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL1_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL1_OVER 0x00000004 // Overrun +#define USB_RXCSRL1_ERROR 0x00000004 // Error +#define USB_RXCSRL1_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH1 register. +// +//***************************************************************************** +#define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH1_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH1_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH1_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH1_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH1_DT 0x00000002 // Data Toggle +#define USB_RXCSRH1_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT1 register. +// +//***************************************************************************** +#define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT1_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE1 register. +// +//***************************************************************************** +#define USB_TXTYPE1_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE1_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE1_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE1_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE1_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE1_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE1_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE1_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE1_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE1_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE1_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE1_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL1 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL1_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL1_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL1_TXPOLL_S \ + 0 +#define USB_TXINTERVAL1_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE1 register. +// +//***************************************************************************** +#define USB_RXTYPE1_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE1_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE1_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE1_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE1_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE1_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE1_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE1_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE1_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE1_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE1_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE1_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL1 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL1_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL1_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL1_TXPOLL_S \ + 0 +#define USB_RXINTERVAL1_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP2 register. +// +//***************************************************************************** +#define USB_TXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP2_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL2 register. +// +//***************************************************************************** +#define USB_TXCSRL2_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL2_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL2_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL2_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL2_STALL 0x00000010 // Send STALL +#define USB_TXCSRL2_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL2_ERROR 0x00000004 // Error +#define USB_TXCSRL2_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL2_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL2_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH2 register. +// +//***************************************************************************** +#define USB_TXCSRH2_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH2_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH2_MODE 0x00000020 // Mode +#define USB_TXCSRH2_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH2_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH2_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH2_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH2_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP2 register. +// +//***************************************************************************** +#define USB_RXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP2_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL2 register. +// +//***************************************************************************** +#define USB_RXCSRL2_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL2_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL2_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL2_STALL 0x00000020 // Send STALL +#define USB_RXCSRL2_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL2_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL2_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL2_ERROR 0x00000004 // Error +#define USB_RXCSRL2_OVER 0x00000004 // Overrun +#define USB_RXCSRL2_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL2_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH2 register. +// +//***************************************************************************** +#define USB_RXCSRH2_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH2_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH2_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH2_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH2_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH2_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH2_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH2_DT 0x00000002 // Data Toggle +#define USB_RXCSRH2_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT2 register. +// +//***************************************************************************** +#define USB_RXCOUNT2_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT2_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE2 register. +// +//***************************************************************************** +#define USB_TXTYPE2_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE2_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE2_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE2_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE2_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE2_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE2_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE2_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE2_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE2_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE2_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE2_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL2 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL2_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL2_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL2_NAKLMT_S \ + 0 +#define USB_TXINTERVAL2_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE2 register. +// +//***************************************************************************** +#define USB_RXTYPE2_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE2_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE2_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE2_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE2_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE2_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE2_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE2_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE2_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE2_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE2_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE2_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL2 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL2_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL2_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL2_TXPOLL_S \ + 0 +#define USB_RXINTERVAL2_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP3 register. +// +//***************************************************************************** +#define USB_TXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP3_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL3 register. +// +//***************************************************************************** +#define USB_TXCSRL3_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL3_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL3_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL3_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL3_STALL 0x00000010 // Send STALL +#define USB_TXCSRL3_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL3_ERROR 0x00000004 // Error +#define USB_TXCSRL3_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL3_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL3_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH3 register. +// +//***************************************************************************** +#define USB_TXCSRH3_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH3_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH3_MODE 0x00000020 // Mode +#define USB_TXCSRH3_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH3_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH3_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH3_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH3_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP3 register. +// +//***************************************************************************** +#define USB_RXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP3_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL3 register. +// +//***************************************************************************** +#define USB_RXCSRL3_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL3_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL3_STALL 0x00000020 // Send STALL +#define USB_RXCSRL3_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL3_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL3_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL3_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL3_ERROR 0x00000004 // Error +#define USB_RXCSRL3_OVER 0x00000004 // Overrun +#define USB_RXCSRL3_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL3_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH3 register. +// +//***************************************************************************** +#define USB_RXCSRH3_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH3_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH3_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH3_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH3_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH3_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH3_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH3_DT 0x00000002 // Data Toggle +#define USB_RXCSRH3_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT3 register. +// +//***************************************************************************** +#define USB_RXCOUNT3_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT3_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE3 register. +// +//***************************************************************************** +#define USB_TXTYPE3_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE3_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE3_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE3_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE3_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE3_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE3_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE3_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE3_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE3_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE3_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE3_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL3 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL3_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL3_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL3_TXPOLL_S \ + 0 +#define USB_TXINTERVAL3_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE3 register. +// +//***************************************************************************** +#define USB_RXTYPE3_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE3_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE3_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE3_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE3_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE3_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE3_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE3_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE3_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE3_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE3_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE3_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL3 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL3_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL3_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL3_TXPOLL_S \ + 0 +#define USB_RXINTERVAL3_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP4 register. +// +//***************************************************************************** +#define USB_TXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP4_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL4 register. +// +//***************************************************************************** +#define USB_TXCSRL4_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL4_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL4_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL4_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL4_STALL 0x00000010 // Send STALL +#define USB_TXCSRL4_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL4_ERROR 0x00000004 // Error +#define USB_TXCSRL4_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL4_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL4_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH4 register. +// +//***************************************************************************** +#define USB_TXCSRH4_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH4_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH4_MODE 0x00000020 // Mode +#define USB_TXCSRH4_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH4_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH4_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH4_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH4_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP4 register. +// +//***************************************************************************** +#define USB_RXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP4_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL4 register. +// +//***************************************************************************** +#define USB_RXCSRL4_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL4_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL4_STALL 0x00000020 // Send STALL +#define USB_RXCSRL4_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL4_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL4_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL4_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL4_OVER 0x00000004 // Overrun +#define USB_RXCSRL4_ERROR 0x00000004 // Error +#define USB_RXCSRL4_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL4_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH4 register. +// +//***************************************************************************** +#define USB_RXCSRH4_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH4_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH4_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH4_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH4_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH4_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH4_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH4_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH4_DT 0x00000002 // Data Toggle +#define USB_RXCSRH4_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT4 register. +// +//***************************************************************************** +#define USB_RXCOUNT4_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT4_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE4 register. +// +//***************************************************************************** +#define USB_TXTYPE4_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE4_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE4_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE4_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE4_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE4_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE4_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE4_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE4_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE4_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE4_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE4_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL4 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL4_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL4_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL4_NAKLMT_S \ + 0 +#define USB_TXINTERVAL4_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE4 register. +// +//***************************************************************************** +#define USB_RXTYPE4_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE4_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE4_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE4_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE4_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE4_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE4_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE4_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE4_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE4_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE4_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE4_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL4 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL4_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL4_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL4_NAKLMT_S \ + 0 +#define USB_RXINTERVAL4_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP5 register. +// +//***************************************************************************** +#define USB_TXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP5_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL5 register. +// +//***************************************************************************** +#define USB_TXCSRL5_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL5_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL5_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL5_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL5_STALL 0x00000010 // Send STALL +#define USB_TXCSRL5_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL5_ERROR 0x00000004 // Error +#define USB_TXCSRL5_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL5_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL5_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH5 register. +// +//***************************************************************************** +#define USB_TXCSRH5_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH5_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH5_MODE 0x00000020 // Mode +#define USB_TXCSRH5_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH5_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH5_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH5_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH5_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP5 register. +// +//***************************************************************************** +#define USB_RXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP5_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL5 register. +// +//***************************************************************************** +#define USB_RXCSRL5_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL5_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL5_STALL 0x00000020 // Send STALL +#define USB_RXCSRL5_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL5_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL5_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL5_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL5_ERROR 0x00000004 // Error +#define USB_RXCSRL5_OVER 0x00000004 // Overrun +#define USB_RXCSRL5_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL5_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH5 register. +// +//***************************************************************************** +#define USB_RXCSRH5_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH5_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH5_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH5_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH5_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH5_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH5_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH5_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH5_DT 0x00000002 // Data Toggle +#define USB_RXCSRH5_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT5 register. +// +//***************************************************************************** +#define USB_RXCOUNT5_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT5_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE5 register. +// +//***************************************************************************** +#define USB_TXTYPE5_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE5_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE5_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE5_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE5_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE5_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE5_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE5_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE5_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE5_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE5_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE5_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL5 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL5_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL5_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL5_NAKLMT_S \ + 0 +#define USB_TXINTERVAL5_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE5 register. +// +//***************************************************************************** +#define USB_RXTYPE5_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE5_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE5_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE5_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE5_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE5_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE5_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE5_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE5_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE5_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE5_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE5_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL5 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL5_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL5_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL5_TXPOLL_S \ + 0 +#define USB_RXINTERVAL5_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP6 register. +// +//***************************************************************************** +#define USB_TXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP6_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL6 register. +// +//***************************************************************************** +#define USB_TXCSRL6_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL6_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL6_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL6_STALL 0x00000010 // Send STALL +#define USB_TXCSRL6_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL6_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL6_ERROR 0x00000004 // Error +#define USB_TXCSRL6_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL6_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL6_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH6 register. +// +//***************************************************************************** +#define USB_TXCSRH6_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH6_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH6_MODE 0x00000020 // Mode +#define USB_TXCSRH6_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH6_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH6_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH6_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH6_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP6 register. +// +//***************************************************************************** +#define USB_RXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP6_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL6 register. +// +//***************************************************************************** +#define USB_RXCSRL6_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL6_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL6_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL6_STALL 0x00000020 // Send STALL +#define USB_RXCSRL6_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL6_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL6_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL6_ERROR 0x00000004 // Error +#define USB_RXCSRL6_OVER 0x00000004 // Overrun +#define USB_RXCSRL6_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL6_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH6 register. +// +//***************************************************************************** +#define USB_RXCSRH6_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH6_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH6_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH6_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH6_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH6_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH6_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH6_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH6_DT 0x00000002 // Data Toggle +#define USB_RXCSRH6_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT6 register. +// +//***************************************************************************** +#define USB_RXCOUNT6_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT6_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE6 register. +// +//***************************************************************************** +#define USB_TXTYPE6_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE6_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE6_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE6_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE6_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE6_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE6_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE6_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE6_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE6_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE6_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE6_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL6 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL6_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL6_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL6_TXPOLL_S \ + 0 +#define USB_TXINTERVAL6_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE6 register. +// +//***************************************************************************** +#define USB_RXTYPE6_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE6_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE6_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE6_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE6_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE6_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE6_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE6_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE6_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE6_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE6_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE6_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL6 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL6_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL6_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL6_NAKLMT_S \ + 0 +#define USB_RXINTERVAL6_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP7 register. +// +//***************************************************************************** +#define USB_TXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP7_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL7 register. +// +//***************************************************************************** +#define USB_TXCSRL7_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL7_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL7_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL7_STALL 0x00000010 // Send STALL +#define USB_TXCSRL7_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL7_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL7_ERROR 0x00000004 // Error +#define USB_TXCSRL7_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL7_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL7_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH7 register. +// +//***************************************************************************** +#define USB_TXCSRH7_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH7_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH7_MODE 0x00000020 // Mode +#define USB_TXCSRH7_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH7_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH7_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH7_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH7_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP7 register. +// +//***************************************************************************** +#define USB_RXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP7_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL7 register. +// +//***************************************************************************** +#define USB_RXCSRL7_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL7_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL7_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL7_STALL 0x00000020 // Send STALL +#define USB_RXCSRL7_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL7_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL7_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL7_ERROR 0x00000004 // Error +#define USB_RXCSRL7_OVER 0x00000004 // Overrun +#define USB_RXCSRL7_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL7_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH7 register. +// +//***************************************************************************** +#define USB_RXCSRH7_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH7_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH7_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH7_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH7_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH7_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH7_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH7_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH7_DT 0x00000002 // Data Toggle +#define USB_RXCSRH7_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT7 register. +// +//***************************************************************************** +#define USB_RXCOUNT7_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT7_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE7 register. +// +//***************************************************************************** +#define USB_TXTYPE7_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE7_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE7_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE7_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE7_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE7_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE7_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE7_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE7_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE7_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE7_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE7_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL7 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL7_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL7_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL7_NAKLMT_S \ + 0 +#define USB_TXINTERVAL7_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE7 register. +// +//***************************************************************************** +#define USB_RXTYPE7_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE7_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE7_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE7_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE7_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE7_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE7_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE7_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE7_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE7_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE7_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE7_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL7 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL7_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL7_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL7_NAKLMT_S \ + 0 +#define USB_RXINTERVAL7_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAINTR register. +// +//***************************************************************************** +#define USB_DMAINTR_CH7 0x00000080 // Channel 7 DMA Interrupt +#define USB_DMAINTR_CH6 0x00000040 // Channel 6 DMA Interrupt +#define USB_DMAINTR_CH5 0x00000020 // Channel 5 DMA Interrupt +#define USB_DMAINTR_CH4 0x00000010 // Channel 4 DMA Interrupt +#define USB_DMAINTR_CH3 0x00000008 // Channel 3 DMA Interrupt +#define USB_DMAINTR_CH2 0x00000004 // Channel 2 DMA Interrupt +#define USB_DMAINTR_CH1 0x00000002 // Channel 1 DMA Interrupt +#define USB_DMAINTR_CH0 0x00000001 // Channel 0 DMA Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL0 register. +// +//***************************************************************************** +#define USB_DMACTL0_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL0_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL0_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL0_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL0_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL0_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL0_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL0_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL0_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL0_DIR 0x00000002 // DMA Direction +#define USB_DMACTL0_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL0_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR0 register. +// +//***************************************************************************** +#define USB_DMAADDR0_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR0_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT0 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT0_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT0_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL1 register. +// +//***************************************************************************** +#define USB_DMACTL1_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL1_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL1_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL1_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL1_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL1_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL1_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL1_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL1_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL1_DIR 0x00000002 // DMA Direction +#define USB_DMACTL1_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL1_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR1 register. +// +//***************************************************************************** +#define USB_DMAADDR1_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR1_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT1 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT1_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT1_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL2 register. +// +//***************************************************************************** +#define USB_DMACTL2_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL2_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL2_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL2_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL2_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL2_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL2_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL2_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL2_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL2_DIR 0x00000002 // DMA Direction +#define USB_DMACTL2_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL2_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR2 register. +// +//***************************************************************************** +#define USB_DMAADDR2_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR2_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT2 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT2_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT2_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL3 register. +// +//***************************************************************************** +#define USB_DMACTL3_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL3_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL3_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL3_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL3_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL3_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL3_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL3_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL3_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL3_DIR 0x00000002 // DMA Direction +#define USB_DMACTL3_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL3_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR3 register. +// +//***************************************************************************** +#define USB_DMAADDR3_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR3_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT3 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT3_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT3_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL4 register. +// +//***************************************************************************** +#define USB_DMACTL4_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL4_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL4_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL4_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL4_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL4_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL4_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL4_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL4_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL4_DIR 0x00000002 // DMA Direction +#define USB_DMACTL4_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL4_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR4 register. +// +//***************************************************************************** +#define USB_DMAADDR4_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR4_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT4 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT4_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT4_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL5 register. +// +//***************************************************************************** +#define USB_DMACTL5_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL5_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL5_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL5_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL5_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL5_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL5_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL5_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL5_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL5_DIR 0x00000002 // DMA Direction +#define USB_DMACTL5_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL5_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR5 register. +// +//***************************************************************************** +#define USB_DMAADDR5_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR5_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT5 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT5_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT5_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL6 register. +// +//***************************************************************************** +#define USB_DMACTL6_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL6_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL6_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL6_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL6_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL6_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL6_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL6_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL6_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL6_DIR 0x00000002 // DMA Direction +#define USB_DMACTL6_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL6_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR6 register. +// +//***************************************************************************** +#define USB_DMAADDR6_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR6_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT6 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT6_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT6_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL7 register. +// +//***************************************************************************** +#define USB_DMACTL7_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL7_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL7_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL7_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL7_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL7_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL7_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL7_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL7_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL7_DIR 0x00000002 // DMA Direction +#define USB_DMACTL7_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL7_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR7 register. +// +//***************************************************************************** +#define USB_DMAADDR7_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR7_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT7 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT7_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT7_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT1_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT1_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT2_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT2_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT3_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT3_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT4_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT5_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT6_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT7_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS +// register. +// +//***************************************************************************** +#define USB_RXDPKTBUFDIS_EP7 0x00000080 // EP7 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP6 0x00000040 // EP6 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP5 0x00000020 // EP5 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP4 0x00000010 // EP4 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP3 0x00000008 // EP3 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP2 0x00000004 // EP2 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP1 0x00000002 // EP1 RX Double-Packet Buffer + // Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS +// register. +// +//***************************************************************************** +#define USB_TXDPKTBUFDIS_EP7 0x00000080 // EP7 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP6 0x00000040 // EP6 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP5 0x00000020 // EP5 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP4 0x00000010 // EP4 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP3 0x00000008 // EP3 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP2 0x00000004 // EP2 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer + // Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CTO register. +// +//***************************************************************************** +#define USB_CTO_CCTV_M 0x0000FFFF // Configurable Chirp Timeout Value +#define USB_CTO_CCTV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_HHSRTN register. +// +//***************************************************************************** +#define USB_HHSRTN_HHSRTN_M 0x0000FFFF // HIgh Speed to UTM Operating + // Delay +#define USB_HHSRTN_HHSRTN_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_HSBT register. +// +//***************************************************************************** +#define USB_HSBT_HSBT_M 0x0000000F // High Speed Timeout Adder +#define USB_HSBT_HSBT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LPMATTR register. +// +//***************************************************************************** +#define USB_LPMATTR_ENDPT_M 0x0000F000 // Endpoint +#define USB_LPMATTR_RMTWAK 0x00000100 // Remote Wake +#define USB_LPMATTR_HIRD_M 0x000000F0 // Host Initiated Resume Duration +#define USB_LPMATTR_LS_M 0x0000000F // Link State +#define USB_LPMATTR_LS_L1 0x00000001 // Sleep State (L1) +#define USB_LPMATTR_ENDPT_S 12 +#define USB_LPMATTR_HIRD_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LPMCNTRL register. +// +//***************************************************************************** +#define USB_LPMCNTRL_NAK 0x00000010 // LPM NAK +#define USB_LPMCNTRL_EN_M 0x0000000C // LPM Enable +#define USB_LPMCNTRL_EN_NONE 0x00000000 // LPM and Extended transactions + // are not supported. In this case, + // the USB does not respond to LPM + // transactions and LPM + // transactions cause a timeout +#define USB_LPMCNTRL_EN_EXT 0x00000004 // LPM is not supported but + // extended transactions are + // supported. In this case, the USB + // does respond to an LPM + // transaction with a STALL +#define USB_LPMCNTRL_EN_LPMEXT 0x0000000C // The USB supports LPM extended + // transactions. In this case, the + // USB responds with a NYET or an + // ACK as determined by the value + // of TXLPM and other conditions +#define USB_LPMCNTRL_RES 0x00000002 // LPM Resume +#define USB_LPMCNTRL_TXLPM 0x00000001 // Transmit LPM Transaction Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LPMIM register. +// +//***************************************************************************** +#define USB_LPMIM_ERR 0x00000020 // LPM Error Interrupt Mask +#define USB_LPMIM_RES 0x00000010 // LPM Resume Interrupt Mask +#define USB_LPMIM_NC 0x00000008 // LPM NC Interrupt Mask +#define USB_LPMIM_ACK 0x00000004 // LPM ACK Interrupt Mask +#define USB_LPMIM_NY 0x00000002 // LPM NY Interrupt Mask +#define USB_LPMIM_STALL 0x00000001 // LPM STALL Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LPMRIS register. +// +//***************************************************************************** +#define USB_LPMRIS_ERR 0x00000020 // LPM Interrupt Status +#define USB_LPMRIS_RES 0x00000010 // LPM Resume Interrupt Status +#define USB_LPMRIS_NC 0x00000008 // LPM NC Interrupt Status +#define USB_LPMRIS_ACK 0x00000004 // LPM ACK Interrupt Status +#define USB_LPMRIS_NY 0x00000002 // LPM NY Interrupt Status +#define USB_LPMRIS_LPMST 0x00000001 // LPM STALL Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LPMFADDR register. +// +//***************************************************************************** +#define USB_LPMFADDR_ADDR_M 0x0000007F // LPM Function Address +#define USB_LPMFADDR_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPC register. +// +//***************************************************************************** +#define USB_EPC_PFLTACT_M 0x00000300 // Power Fault Action +#define USB_EPC_PFLTACT_UNCHG 0x00000000 // Unchanged +#define USB_EPC_PFLTACT_TRIS 0x00000100 // Tristate +#define USB_EPC_PFLTACT_LOW 0x00000200 // Low +#define USB_EPC_PFLTACT_HIGH 0x00000300 // High +#define USB_EPC_PFLTAEN 0x00000040 // Power Fault Action Enable +#define USB_EPC_PFLTSEN_HIGH 0x00000020 // Power Fault Sense +#define USB_EPC_PFLTEN 0x00000010 // Power Fault Input Enable +#define USB_EPC_EPENDE 0x00000004 // EPEN Drive Enable +#define USB_EPC_EPEN_M 0x00000003 // External Power Supply Enable + // Configuration +#define USB_EPC_EPEN_LOW 0x00000000 // Power Enable Active Low +#define USB_EPC_EPEN_HIGH 0x00000001 // Power Enable Active High +#define USB_EPC_EPEN_VBLOW 0x00000002 // Power Enable High if VBUS Low + // (OTG only) +#define USB_EPC_EPEN_VBHIGH 0x00000003 // Power Enable High if VBUS High + // (OTG only) + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCRIS register. +// +//***************************************************************************** +#define USB_EPCRIS_PF 0x00000001 // USB Power Fault Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCIM register. +// +//***************************************************************************** +#define USB_EPCIM_PF 0x00000001 // USB Power Fault Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCISC register. +// +//***************************************************************************** +#define USB_EPCISC_PF 0x00000001 // USB Power Fault Interrupt Status + // and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRRIS register. +// +//***************************************************************************** +#define USB_DRRIS_RESUME 0x00000001 // RESUME Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRIM register. +// +//***************************************************************************** +#define USB_DRIM_RESUME 0x00000001 // RESUME Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRISC register. +// +//***************************************************************************** +#define USB_DRISC_RESUME 0x00000001 // RESUME Interrupt Status and + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_GPCS register. +// +//***************************************************************************** +#define USB_GPCS_DEVMOD_M 0x00000007 // Device Mode +#define USB_GPCS_DEVMOD_OTG 0x00000000 // Use USB0VBUS and USB0ID pin +#define USB_GPCS_DEVMOD_HOST 0x00000002 // Force USB0VBUS and USB0ID low +#define USB_GPCS_DEVMOD_DEV 0x00000003 // Force USB0VBUS and USB0ID high +#define USB_GPCS_DEVMOD_HOSTVBUS \ + 0x00000004 // Use USB0VBUS and force USB0ID + // low +#define USB_GPCS_DEVMOD_DEVVBUS 0x00000005 // Use USB0VBUS and force USB0ID + // high +#define USB_GPCS_DEVMODOTG 0x00000002 // Enable Device Mode +#define USB_GPCS_DEVMOD 0x00000001 // Device Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDC register. +// +//***************************************************************************** +#define USB_VDC_VBDEN 0x00000001 // VBUS Droop Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCRIS register. +// +//***************************************************************************** +#define USB_VDCRIS_VD 0x00000001 // VBUS Droop Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCIM register. +// +//***************************************************************************** +#define USB_VDCIM_VD 0x00000001 // VBUS Droop Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCISC register. +// +//***************************************************************************** +#define USB_VDCISC_VD 0x00000001 // VBUS Droop Interrupt Status and + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVRIS register. +// +//***************************************************************************** +#define USB_IDVRIS_ID 0x00000001 // ID Valid Detect Raw Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVIM register. +// +//***************************************************************************** +#define USB_IDVIM_ID 0x00000001 // ID Valid Detect Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVISC register. +// +//***************************************************************************** +#define USB_IDVISC_ID 0x00000001 // ID Valid Detect Interrupt Status + // and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMASEL register. +// +//***************************************************************************** +#define USB_DMASEL_DMACTX_M 0x00F00000 // DMA C TX Select +#define USB_DMASEL_DMACRX_M 0x000F0000 // DMA C RX Select +#define USB_DMASEL_DMABTX_M 0x0000F000 // DMA B TX Select +#define USB_DMASEL_DMABRX_M 0x00000F00 // DMA B RX Select +#define USB_DMASEL_DMAATX_M 0x000000F0 // DMA A TX Select +#define USB_DMASEL_DMAARX_M 0x0000000F // DMA A RX Select +#define USB_DMASEL_DMACTX_S 20 +#define USB_DMASEL_DMACRX_S 16 +#define USB_DMASEL_DMABTX_S 12 +#define USB_DMASEL_DMABRX_S 8 +#define USB_DMASEL_DMAATX_S 4 +#define USB_DMASEL_DMAARX_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_PP register. +// +//***************************************************************************** +#define USB_PP_ECNT_M 0x0000FF00 // Endpoint Count +#define USB_PP_USB_M 0x000000C0 // USB Capability +#define USB_PP_USB_DEVICE 0x00000040 // DEVICE +#define USB_PP_USB_HOSTDEVICE 0x00000080 // HOST +#define USB_PP_USB_OTG 0x000000C0 // OTG +#define USB_PP_ULPI 0x00000020 // ULPI Present +#define USB_PP_PHY 0x00000010 // PHY Present +#define USB_PP_TYPE_M 0x0000000F // Controller Type +#define USB_PP_TYPE_0 0x00000000 // The first-generation USB + // controller +#define USB_PP_TYPE_1 0x00000001 // Second-generation USB + // controller.The controller + // implemented in post Icestorm + // devices that use the 3.0 version + // of the Mentor controller +#define USB_PP_ECNT_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_PC register. +// +//***************************************************************************** +#define USB_PC_ULPIEN 0x00010000 // ULPI Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CC register. +// +//***************************************************************************** +#define USB_CC_CLKEN 0x00000200 // USB Clock Enable +#define USB_CC_CSD 0x00000100 // Clock Source/Direction +#define USB_CC_CLKDIV_M 0x0000000F // PLL Clock Divisor +#define USB_CC_CLKDIV_S 0 + +#endif // __HW_USB_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_watchdog.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_watchdog.h new file mode 100644 index 0000000000000000000000000000000000000000..783b6f07f64c9fb6aa8d82ccc14b1bfe3d9b066d --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_watchdog.h @@ -0,0 +1,122 @@ +//***************************************************************************** +// +// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_WATCHDOG_H__ +#define __HW_WATCHDOG_H__ + +//***************************************************************************** +// +// The following are defines for the Watchdog Timer register offsets. +// +//***************************************************************************** +#define WDT_O_LOAD 0x00000000 // Watchdog Load +#define WDT_O_VALUE 0x00000004 // Watchdog Value +#define WDT_O_CTL 0x00000008 // Watchdog Control +#define WDT_O_ICR 0x0000000C // Watchdog Interrupt Clear +#define WDT_O_RIS 0x00000010 // Watchdog Raw Interrupt Status +#define WDT_O_MIS 0x00000014 // Watchdog Masked Interrupt Status +#define WDT_O_TEST 0x00000418 // Watchdog Test +#define WDT_O_LOCK 0x00000C00 // Watchdog Lock + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_LOAD register. +// +//***************************************************************************** +#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value +#define WDT_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_VALUE register. +// +//***************************************************************************** +#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value +#define WDT_VALUE_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_CTL register. +// +//***************************************************************************** +#define WDT_CTL_WRC 0x80000000 // Write Complete +#define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type +#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable +#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_ICR register. +// +//***************************************************************************** +#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear +#define WDT_ICR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_RIS register. +// +//***************************************************************************** +#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_MIS register. +// +//***************************************************************************** +#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_TEST register. +// +//***************************************************************************** +#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_LOCK register. +// +//***************************************************************************** +#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock +#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked +#define WDT_LOCK_LOCKED 0x00000001 // Locked +#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer + +#endif // __HW_WATCHDOG_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/tm4c123gh6pm.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/tm4c123gh6pm.h new file mode 100644 index 0000000000000000000000000000000000000000..6cec6f0fb9cdace77dc3f33d7d78d928f222a24b --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/tm4c123gh6pm.h @@ -0,0 +1,12867 @@ +//***************************************************************************** +// +// tm4c123gh6pm.h - TM4C123GH6PM Register Definitions +// +// Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __TM4C123GH6PM_H__ +#define __TM4C123GH6PM_H__ + +//***************************************************************************** +// +// Interrupt assignments +// +//***************************************************************************** +#define INT_GPIOA 16 // GPIO Port A +#define INT_GPIOB 17 // GPIO Port B +#define INT_GPIOC 18 // GPIO Port C +#define INT_GPIOD 19 // GPIO Port D +#define INT_GPIOE 20 // GPIO Port E +#define INT_UART0 21 // UART0 +#define INT_UART1 22 // UART1 +#define INT_SSI0 23 // SSI0 +#define INT_I2C0 24 // I2C0 +#define INT_PWM0_FAULT 25 // PWM0 Fault +#define INT_PWM0_0 26 // PWM0 Generator 0 +#define INT_PWM0_1 27 // PWM0 Generator 1 +#define INT_PWM0_2 28 // PWM0 Generator 2 +#define INT_QEI0 29 // QEI0 +#define INT_ADC0SS0 30 // ADC0 Sequence 0 +#define INT_ADC0SS1 31 // ADC0 Sequence 1 +#define INT_ADC0SS2 32 // ADC0 Sequence 2 +#define INT_ADC0SS3 33 // ADC0 Sequence 3 +#define INT_WATCHDOG 34 // Watchdog Timers 0 and 1 +#define INT_TIMER0A 35 // 16/32-Bit Timer 0A +#define INT_TIMER0B 36 // 16/32-Bit Timer 0B +#define INT_TIMER1A 37 // 16/32-Bit Timer 1A +#define INT_TIMER1B 38 // 16/32-Bit Timer 1B +#define INT_TIMER2A 39 // 16/32-Bit Timer 2A +#define INT_TIMER2B 40 // 16/32-Bit Timer 2B +#define INT_COMP0 41 // Analog Comparator 0 +#define INT_COMP1 42 // Analog Comparator 1 +#define INT_SYSCTL 44 // System Control +#define INT_FLASH 45 // Flash Memory Control and EEPROM + // Control +#define INT_GPIOF 46 // GPIO Port F +#define INT_UART2 49 // UART2 +#define INT_SSI1 50 // SSI1 +#define INT_TIMER3A 51 // 16/32-Bit Timer 3A +#define INT_TIMER3B 52 // Timer 3B +#define INT_I2C1 53 // I2C1 +#define INT_QEI1 54 // QEI1 +#define INT_CAN0 55 // CAN0 +#define INT_CAN1 56 // CAN1 +#define INT_HIBERNATE 59 // Hibernation Module +#define INT_USB0 60 // USB +#define INT_PWM0_3 61 // PWM Generator 3 +#define INT_UDMA 62 // uDMA Software +#define INT_UDMAERR 63 // uDMA Error +#define INT_ADC1SS0 64 // ADC1 Sequence 0 +#define INT_ADC1SS1 65 // ADC1 Sequence 1 +#define INT_ADC1SS2 66 // ADC1 Sequence 2 +#define INT_ADC1SS3 67 // ADC1 Sequence 3 +#define INT_SSI2 73 // SSI2 +#define INT_SSI3 74 // SSI3 +#define INT_UART3 75 // UART3 +#define INT_UART4 76 // UART4 +#define INT_UART5 77 // UART5 +#define INT_UART6 78 // UART6 +#define INT_UART7 79 // UART7 +#define INT_I2C2 84 // I2C2 +#define INT_I2C3 85 // I2C3 +#define INT_TIMER4A 86 // 16/32-Bit Timer 4A +#define INT_TIMER4B 87 // 16/32-Bit Timer 4B +#define INT_TIMER5A 108 // 16/32-Bit Timer 5A +#define INT_TIMER5B 109 // 16/32-Bit Timer 5B +#define INT_WTIMER0A 110 // 32/64-Bit Timer 0A +#define INT_WTIMER0B 111 // 32/64-Bit Timer 0B +#define INT_WTIMER1A 112 // 32/64-Bit Timer 1A +#define INT_WTIMER1B 113 // 32/64-Bit Timer 1B +#define INT_WTIMER2A 114 // 32/64-Bit Timer 2A +#define INT_WTIMER2B 115 // 32/64-Bit Timer 2B +#define INT_WTIMER3A 116 // 32/64-Bit Timer 3A +#define INT_WTIMER3B 117 // 32/64-Bit Timer 3B +#define INT_WTIMER4A 118 // 32/64-Bit Timer 4A +#define INT_WTIMER4B 119 // 32/64-Bit Timer 4B +#define INT_WTIMER5A 120 // 32/64-Bit Timer 5A +#define INT_WTIMER5B 121 // 32/64-Bit Timer 5B +#define INT_SYSEXC 122 // System Exception (imprecise) +#define INT_PWM1_0 150 // PWM1 Generator 0 +#define INT_PWM1_1 151 // PWM1 Generator 1 +#define INT_PWM1_2 152 // PWM1 Generator 2 +#define INT_PWM1_3 153 // PWM1 Generator 3 +#define INT_PWM1_FAULT 154 // PWM1 Fault + +//***************************************************************************** +// +// Watchdog Timer registers (WATCHDOG0) +// +//***************************************************************************** +#define WATCHDOG0_LOAD_R (*((volatile uint32_t *)0x40000000)) +#define WATCHDOG0_VALUE_R (*((volatile uint32_t *)0x40000004)) +#define WATCHDOG0_CTL_R (*((volatile uint32_t *)0x40000008)) +#define WATCHDOG0_ICR_R (*((volatile uint32_t *)0x4000000C)) +#define WATCHDOG0_RIS_R (*((volatile uint32_t *)0x40000010)) +#define WATCHDOG0_MIS_R (*((volatile uint32_t *)0x40000014)) +#define WATCHDOG0_TEST_R (*((volatile uint32_t *)0x40000418)) +#define WATCHDOG0_LOCK_R (*((volatile uint32_t *)0x40000C00)) + +//***************************************************************************** +// +// Watchdog Timer registers (WATCHDOG1) +// +//***************************************************************************** +#define WATCHDOG1_LOAD_R (*((volatile uint32_t *)0x40001000)) +#define WATCHDOG1_VALUE_R (*((volatile uint32_t *)0x40001004)) +#define WATCHDOG1_CTL_R (*((volatile uint32_t *)0x40001008)) +#define WATCHDOG1_ICR_R (*((volatile uint32_t *)0x4000100C)) +#define WATCHDOG1_RIS_R (*((volatile uint32_t *)0x40001010)) +#define WATCHDOG1_MIS_R (*((volatile uint32_t *)0x40001014)) +#define WATCHDOG1_TEST_R (*((volatile uint32_t *)0x40001418)) +#define WATCHDOG1_LOCK_R (*((volatile uint32_t *)0x40001C00)) + +//***************************************************************************** +// +// GPIO registers (PORTA) +// +//***************************************************************************** +#define GPIO_PORTA_DATA_BITS_R ((volatile uint32_t *)0x40004000) +#define GPIO_PORTA_DATA_R (*((volatile uint32_t *)0x400043FC)) +#define GPIO_PORTA_DIR_R (*((volatile uint32_t *)0x40004400)) +#define GPIO_PORTA_IS_R (*((volatile uint32_t *)0x40004404)) +#define GPIO_PORTA_IBE_R (*((volatile uint32_t *)0x40004408)) +#define GPIO_PORTA_IEV_R (*((volatile uint32_t *)0x4000440C)) +#define GPIO_PORTA_IM_R (*((volatile uint32_t *)0x40004410)) +#define GPIO_PORTA_RIS_R (*((volatile uint32_t *)0x40004414)) +#define GPIO_PORTA_MIS_R (*((volatile uint32_t *)0x40004418)) +#define GPIO_PORTA_ICR_R (*((volatile uint32_t *)0x4000441C)) +#define GPIO_PORTA_AFSEL_R (*((volatile uint32_t *)0x40004420)) +#define GPIO_PORTA_DR2R_R (*((volatile uint32_t *)0x40004500)) +#define GPIO_PORTA_DR4R_R (*((volatile uint32_t *)0x40004504)) +#define GPIO_PORTA_DR8R_R (*((volatile uint32_t *)0x40004508)) +#define GPIO_PORTA_ODR_R (*((volatile uint32_t *)0x4000450C)) +#define GPIO_PORTA_PUR_R (*((volatile uint32_t *)0x40004510)) +#define GPIO_PORTA_PDR_R (*((volatile uint32_t *)0x40004514)) +#define GPIO_PORTA_SLR_R (*((volatile uint32_t *)0x40004518)) +#define GPIO_PORTA_DEN_R (*((volatile uint32_t *)0x4000451C)) +#define GPIO_PORTA_LOCK_R (*((volatile uint32_t *)0x40004520)) +#define GPIO_PORTA_CR_R (*((volatile uint32_t *)0x40004524)) +#define GPIO_PORTA_AMSEL_R (*((volatile uint32_t *)0x40004528)) +#define GPIO_PORTA_PCTL_R (*((volatile uint32_t *)0x4000452C)) +#define GPIO_PORTA_ADCCTL_R (*((volatile uint32_t *)0x40004530)) +#define GPIO_PORTA_DMACTL_R (*((volatile uint32_t *)0x40004534)) + +//***************************************************************************** +// +// GPIO registers (PORTB) +// +//***************************************************************************** +#define GPIO_PORTB_DATA_BITS_R ((volatile uint32_t *)0x40005000) +#define GPIO_PORTB_DATA_R (*((volatile uint32_t *)0x400053FC)) +#define GPIO_PORTB_DIR_R (*((volatile uint32_t *)0x40005400)) +#define GPIO_PORTB_IS_R (*((volatile uint32_t *)0x40005404)) +#define GPIO_PORTB_IBE_R (*((volatile uint32_t *)0x40005408)) +#define GPIO_PORTB_IEV_R (*((volatile uint32_t *)0x4000540C)) +#define GPIO_PORTB_IM_R (*((volatile uint32_t *)0x40005410)) +#define GPIO_PORTB_RIS_R (*((volatile uint32_t *)0x40005414)) +#define GPIO_PORTB_MIS_R (*((volatile uint32_t *)0x40005418)) +#define GPIO_PORTB_ICR_R (*((volatile uint32_t *)0x4000541C)) +#define GPIO_PORTB_AFSEL_R (*((volatile uint32_t *)0x40005420)) +#define GPIO_PORTB_DR2R_R (*((volatile uint32_t *)0x40005500)) +#define GPIO_PORTB_DR4R_R (*((volatile uint32_t *)0x40005504)) +#define GPIO_PORTB_DR8R_R (*((volatile uint32_t *)0x40005508)) +#define GPIO_PORTB_ODR_R (*((volatile uint32_t *)0x4000550C)) +#define GPIO_PORTB_PUR_R (*((volatile uint32_t *)0x40005510)) +#define GPIO_PORTB_PDR_R (*((volatile uint32_t *)0x40005514)) +#define GPIO_PORTB_SLR_R (*((volatile uint32_t *)0x40005518)) +#define GPIO_PORTB_DEN_R (*((volatile uint32_t *)0x4000551C)) +#define GPIO_PORTB_LOCK_R (*((volatile uint32_t *)0x40005520)) +#define GPIO_PORTB_CR_R (*((volatile uint32_t *)0x40005524)) +#define GPIO_PORTB_AMSEL_R (*((volatile uint32_t *)0x40005528)) +#define GPIO_PORTB_PCTL_R (*((volatile uint32_t *)0x4000552C)) +#define GPIO_PORTB_ADCCTL_R (*((volatile uint32_t *)0x40005530)) +#define GPIO_PORTB_DMACTL_R (*((volatile uint32_t *)0x40005534)) + +//***************************************************************************** +// +// GPIO registers (PORTC) +// +//***************************************************************************** +#define GPIO_PORTC_DATA_BITS_R ((volatile uint32_t *)0x40006000) +#define GPIO_PORTC_DATA_R (*((volatile uint32_t *)0x400063FC)) +#define GPIO_PORTC_DIR_R (*((volatile uint32_t *)0x40006400)) +#define GPIO_PORTC_IS_R (*((volatile uint32_t *)0x40006404)) +#define GPIO_PORTC_IBE_R (*((volatile uint32_t *)0x40006408)) +#define GPIO_PORTC_IEV_R (*((volatile uint32_t *)0x4000640C)) +#define GPIO_PORTC_IM_R (*((volatile uint32_t *)0x40006410)) +#define GPIO_PORTC_RIS_R (*((volatile uint32_t *)0x40006414)) +#define GPIO_PORTC_MIS_R (*((volatile uint32_t *)0x40006418)) +#define GPIO_PORTC_ICR_R (*((volatile uint32_t *)0x4000641C)) +#define GPIO_PORTC_AFSEL_R (*((volatile uint32_t *)0x40006420)) +#define GPIO_PORTC_DR2R_R (*((volatile uint32_t *)0x40006500)) +#define GPIO_PORTC_DR4R_R (*((volatile uint32_t *)0x40006504)) +#define GPIO_PORTC_DR8R_R (*((volatile uint32_t *)0x40006508)) +#define GPIO_PORTC_ODR_R (*((volatile uint32_t *)0x4000650C)) +#define GPIO_PORTC_PUR_R (*((volatile uint32_t *)0x40006510)) +#define GPIO_PORTC_PDR_R (*((volatile uint32_t *)0x40006514)) +#define GPIO_PORTC_SLR_R (*((volatile uint32_t *)0x40006518)) +#define GPIO_PORTC_DEN_R (*((volatile uint32_t *)0x4000651C)) +#define GPIO_PORTC_LOCK_R (*((volatile uint32_t *)0x40006520)) +#define GPIO_PORTC_CR_R (*((volatile uint32_t *)0x40006524)) +#define GPIO_PORTC_AMSEL_R (*((volatile uint32_t *)0x40006528)) +#define GPIO_PORTC_PCTL_R (*((volatile uint32_t *)0x4000652C)) +#define GPIO_PORTC_ADCCTL_R (*((volatile uint32_t *)0x40006530)) +#define GPIO_PORTC_DMACTL_R (*((volatile uint32_t *)0x40006534)) + +//***************************************************************************** +// +// GPIO registers (PORTD) +// +//***************************************************************************** +#define GPIO_PORTD_DATA_BITS_R ((volatile uint32_t *)0x40007000) +#define GPIO_PORTD_DATA_R (*((volatile uint32_t *)0x400073FC)) +#define GPIO_PORTD_DIR_R (*((volatile uint32_t *)0x40007400)) +#define GPIO_PORTD_IS_R (*((volatile uint32_t *)0x40007404)) +#define GPIO_PORTD_IBE_R (*((volatile uint32_t *)0x40007408)) +#define GPIO_PORTD_IEV_R (*((volatile uint32_t *)0x4000740C)) +#define GPIO_PORTD_IM_R (*((volatile uint32_t *)0x40007410)) +#define GPIO_PORTD_RIS_R (*((volatile uint32_t *)0x40007414)) +#define GPIO_PORTD_MIS_R (*((volatile uint32_t *)0x40007418)) +#define GPIO_PORTD_ICR_R (*((volatile uint32_t *)0x4000741C)) +#define GPIO_PORTD_AFSEL_R (*((volatile uint32_t *)0x40007420)) +#define GPIO_PORTD_DR2R_R (*((volatile uint32_t *)0x40007500)) +#define GPIO_PORTD_DR4R_R (*((volatile uint32_t *)0x40007504)) +#define GPIO_PORTD_DR8R_R (*((volatile uint32_t *)0x40007508)) +#define GPIO_PORTD_ODR_R (*((volatile uint32_t *)0x4000750C)) +#define GPIO_PORTD_PUR_R (*((volatile uint32_t *)0x40007510)) +#define GPIO_PORTD_PDR_R (*((volatile uint32_t *)0x40007514)) +#define GPIO_PORTD_SLR_R (*((volatile uint32_t *)0x40007518)) +#define GPIO_PORTD_DEN_R (*((volatile uint32_t *)0x4000751C)) +#define GPIO_PORTD_LOCK_R (*((volatile uint32_t *)0x40007520)) +#define GPIO_PORTD_CR_R (*((volatile uint32_t *)0x40007524)) +#define GPIO_PORTD_AMSEL_R (*((volatile uint32_t *)0x40007528)) +#define GPIO_PORTD_PCTL_R (*((volatile uint32_t *)0x4000752C)) +#define GPIO_PORTD_ADCCTL_R (*((volatile uint32_t *)0x40007530)) +#define GPIO_PORTD_DMACTL_R (*((volatile uint32_t *)0x40007534)) + +//***************************************************************************** +// +// SSI registers (SSI0) +// +//***************************************************************************** +#define SSI0_CR0_R (*((volatile uint32_t *)0x40008000)) +#define SSI0_CR1_R (*((volatile uint32_t *)0x40008004)) +#define SSI0_DR_R (*((volatile uint32_t *)0x40008008)) +#define SSI0_SR_R (*((volatile uint32_t *)0x4000800C)) +#define SSI0_CPSR_R (*((volatile uint32_t *)0x40008010)) +#define SSI0_IM_R (*((volatile uint32_t *)0x40008014)) +#define SSI0_RIS_R (*((volatile uint32_t *)0x40008018)) +#define SSI0_MIS_R (*((volatile uint32_t *)0x4000801C)) +#define SSI0_ICR_R (*((volatile uint32_t *)0x40008020)) +#define SSI0_DMACTL_R (*((volatile uint32_t *)0x40008024)) +#define SSI0_CC_R (*((volatile uint32_t *)0x40008FC8)) + +//***************************************************************************** +// +// SSI registers (SSI1) +// +//***************************************************************************** +#define SSI1_CR0_R (*((volatile uint32_t *)0x40009000)) +#define SSI1_CR1_R (*((volatile uint32_t *)0x40009004)) +#define SSI1_DR_R (*((volatile uint32_t *)0x40009008)) +#define SSI1_SR_R (*((volatile uint32_t *)0x4000900C)) +#define SSI1_CPSR_R (*((volatile uint32_t *)0x40009010)) +#define SSI1_IM_R (*((volatile uint32_t *)0x40009014)) +#define SSI1_RIS_R (*((volatile uint32_t *)0x40009018)) +#define SSI1_MIS_R (*((volatile uint32_t *)0x4000901C)) +#define SSI1_ICR_R (*((volatile uint32_t *)0x40009020)) +#define SSI1_DMACTL_R (*((volatile uint32_t *)0x40009024)) +#define SSI1_CC_R (*((volatile uint32_t *)0x40009FC8)) + +//***************************************************************************** +// +// SSI registers (SSI2) +// +//***************************************************************************** +#define SSI2_CR0_R (*((volatile uint32_t *)0x4000A000)) +#define SSI2_CR1_R (*((volatile uint32_t *)0x4000A004)) +#define SSI2_DR_R (*((volatile uint32_t *)0x4000A008)) +#define SSI2_SR_R (*((volatile uint32_t *)0x4000A00C)) +#define SSI2_CPSR_R (*((volatile uint32_t *)0x4000A010)) +#define SSI2_IM_R (*((volatile uint32_t *)0x4000A014)) +#define SSI2_RIS_R (*((volatile uint32_t *)0x4000A018)) +#define SSI2_MIS_R (*((volatile uint32_t *)0x4000A01C)) +#define SSI2_ICR_R (*((volatile uint32_t *)0x4000A020)) +#define SSI2_DMACTL_R (*((volatile uint32_t *)0x4000A024)) +#define SSI2_CC_R (*((volatile uint32_t *)0x4000AFC8)) + +//***************************************************************************** +// +// SSI registers (SSI3) +// +//***************************************************************************** +#define SSI3_CR0_R (*((volatile uint32_t *)0x4000B000)) +#define SSI3_CR1_R (*((volatile uint32_t *)0x4000B004)) +#define SSI3_DR_R (*((volatile uint32_t *)0x4000B008)) +#define SSI3_SR_R (*((volatile uint32_t *)0x4000B00C)) +#define SSI3_CPSR_R (*((volatile uint32_t *)0x4000B010)) +#define SSI3_IM_R (*((volatile uint32_t *)0x4000B014)) +#define SSI3_RIS_R (*((volatile uint32_t *)0x4000B018)) +#define SSI3_MIS_R (*((volatile uint32_t *)0x4000B01C)) +#define SSI3_ICR_R (*((volatile uint32_t *)0x4000B020)) +#define SSI3_DMACTL_R (*((volatile uint32_t *)0x4000B024)) +#define SSI3_CC_R (*((volatile uint32_t *)0x4000BFC8)) + +//***************************************************************************** +// +// UART registers (UART0) +// +//***************************************************************************** +#define UART0_DR_R (*((volatile uint32_t *)0x4000C000)) +#define UART0_RSR_R (*((volatile uint32_t *)0x4000C004)) +#define UART0_ECR_R (*((volatile uint32_t *)0x4000C004)) +#define UART0_FR_R (*((volatile uint32_t *)0x4000C018)) +#define UART0_ILPR_R (*((volatile uint32_t *)0x4000C020)) +#define UART0_IBRD_R (*((volatile uint32_t *)0x4000C024)) +#define UART0_FBRD_R (*((volatile uint32_t *)0x4000C028)) +#define UART0_LCRH_R (*((volatile uint32_t *)0x4000C02C)) +#define UART0_CTL_R (*((volatile uint32_t *)0x4000C030)) +#define UART0_IFLS_R (*((volatile uint32_t *)0x4000C034)) +#define UART0_IM_R (*((volatile uint32_t *)0x4000C038)) +#define UART0_RIS_R (*((volatile uint32_t *)0x4000C03C)) +#define UART0_MIS_R (*((volatile uint32_t *)0x4000C040)) +#define UART0_ICR_R (*((volatile uint32_t *)0x4000C044)) +#define UART0_DMACTL_R (*((volatile uint32_t *)0x4000C048)) +#define UART0_9BITADDR_R (*((volatile uint32_t *)0x4000C0A4)) +#define UART0_9BITAMASK_R (*((volatile uint32_t *)0x4000C0A8)) +#define UART0_PP_R (*((volatile uint32_t *)0x4000CFC0)) +#define UART0_CC_R (*((volatile uint32_t *)0x4000CFC8)) + +//***************************************************************************** +// +// UART registers (UART1) +// +//***************************************************************************** +#define UART1_DR_R (*((volatile uint32_t *)0x4000D000)) +#define UART1_RSR_R (*((volatile uint32_t *)0x4000D004)) +#define UART1_ECR_R (*((volatile uint32_t *)0x4000D004)) +#define UART1_FR_R (*((volatile uint32_t *)0x4000D018)) +#define UART1_ILPR_R (*((volatile uint32_t *)0x4000D020)) +#define UART1_IBRD_R (*((volatile uint32_t *)0x4000D024)) +#define UART1_FBRD_R (*((volatile uint32_t *)0x4000D028)) +#define UART1_LCRH_R (*((volatile uint32_t *)0x4000D02C)) +#define UART1_CTL_R (*((volatile uint32_t *)0x4000D030)) +#define UART1_IFLS_R (*((volatile uint32_t *)0x4000D034)) +#define UART1_IM_R (*((volatile uint32_t *)0x4000D038)) +#define UART1_RIS_R (*((volatile uint32_t *)0x4000D03C)) +#define UART1_MIS_R (*((volatile uint32_t *)0x4000D040)) +#define UART1_ICR_R (*((volatile uint32_t *)0x4000D044)) +#define UART1_DMACTL_R (*((volatile uint32_t *)0x4000D048)) +#define UART1_9BITADDR_R (*((volatile uint32_t *)0x4000D0A4)) +#define UART1_9BITAMASK_R (*((volatile uint32_t *)0x4000D0A8)) +#define UART1_PP_R (*((volatile uint32_t *)0x4000DFC0)) +#define UART1_CC_R (*((volatile uint32_t *)0x4000DFC8)) + +//***************************************************************************** +// +// UART registers (UART2) +// +//***************************************************************************** +#define UART2_DR_R (*((volatile uint32_t *)0x4000E000)) +#define UART2_RSR_R (*((volatile uint32_t *)0x4000E004)) +#define UART2_ECR_R (*((volatile uint32_t *)0x4000E004)) +#define UART2_FR_R (*((volatile uint32_t *)0x4000E018)) +#define UART2_ILPR_R (*((volatile uint32_t *)0x4000E020)) +#define UART2_IBRD_R (*((volatile uint32_t *)0x4000E024)) +#define UART2_FBRD_R (*((volatile uint32_t *)0x4000E028)) +#define UART2_LCRH_R (*((volatile uint32_t *)0x4000E02C)) +#define UART2_CTL_R (*((volatile uint32_t *)0x4000E030)) +#define UART2_IFLS_R (*((volatile uint32_t *)0x4000E034)) +#define UART2_IM_R (*((volatile uint32_t *)0x4000E038)) +#define UART2_RIS_R (*((volatile uint32_t *)0x4000E03C)) +#define UART2_MIS_R (*((volatile uint32_t *)0x4000E040)) +#define UART2_ICR_R (*((volatile uint32_t *)0x4000E044)) +#define UART2_DMACTL_R (*((volatile uint32_t *)0x4000E048)) +#define UART2_9BITADDR_R (*((volatile uint32_t *)0x4000E0A4)) +#define UART2_9BITAMASK_R (*((volatile uint32_t *)0x4000E0A8)) +#define UART2_PP_R (*((volatile uint32_t *)0x4000EFC0)) +#define UART2_CC_R (*((volatile uint32_t *)0x4000EFC8)) + +//***************************************************************************** +// +// UART registers (UART3) +// +//***************************************************************************** +#define UART3_DR_R (*((volatile uint32_t *)0x4000F000)) +#define UART3_RSR_R (*((volatile uint32_t *)0x4000F004)) +#define UART3_ECR_R (*((volatile uint32_t *)0x4000F004)) +#define UART3_FR_R (*((volatile uint32_t *)0x4000F018)) +#define UART3_ILPR_R (*((volatile uint32_t *)0x4000F020)) +#define UART3_IBRD_R (*((volatile uint32_t *)0x4000F024)) +#define UART3_FBRD_R (*((volatile uint32_t *)0x4000F028)) +#define UART3_LCRH_R (*((volatile uint32_t *)0x4000F02C)) +#define UART3_CTL_R (*((volatile uint32_t *)0x4000F030)) +#define UART3_IFLS_R (*((volatile uint32_t *)0x4000F034)) +#define UART3_IM_R (*((volatile uint32_t *)0x4000F038)) +#define UART3_RIS_R (*((volatile uint32_t *)0x4000F03C)) +#define UART3_MIS_R (*((volatile uint32_t *)0x4000F040)) +#define UART3_ICR_R (*((volatile uint32_t *)0x4000F044)) +#define UART3_DMACTL_R (*((volatile uint32_t *)0x4000F048)) +#define UART3_9BITADDR_R (*((volatile uint32_t *)0x4000F0A4)) +#define UART3_9BITAMASK_R (*((volatile uint32_t *)0x4000F0A8)) +#define UART3_PP_R (*((volatile uint32_t *)0x4000FFC0)) +#define UART3_CC_R (*((volatile uint32_t *)0x4000FFC8)) + +//***************************************************************************** +// +// UART registers (UART4) +// +//***************************************************************************** +#define UART4_DR_R (*((volatile uint32_t *)0x40010000)) +#define UART4_RSR_R (*((volatile uint32_t *)0x40010004)) +#define UART4_ECR_R (*((volatile uint32_t *)0x40010004)) +#define UART4_FR_R (*((volatile uint32_t *)0x40010018)) +#define UART4_ILPR_R (*((volatile uint32_t *)0x40010020)) +#define UART4_IBRD_R (*((volatile uint32_t *)0x40010024)) +#define UART4_FBRD_R (*((volatile uint32_t *)0x40010028)) +#define UART4_LCRH_R (*((volatile uint32_t *)0x4001002C)) +#define UART4_CTL_R (*((volatile uint32_t *)0x40010030)) +#define UART4_IFLS_R (*((volatile uint32_t *)0x40010034)) +#define UART4_IM_R (*((volatile uint32_t *)0x40010038)) +#define UART4_RIS_R (*((volatile uint32_t *)0x4001003C)) +#define UART4_MIS_R (*((volatile uint32_t *)0x40010040)) +#define UART4_ICR_R (*((volatile uint32_t *)0x40010044)) +#define UART4_DMACTL_R (*((volatile uint32_t *)0x40010048)) +#define UART4_9BITADDR_R (*((volatile uint32_t *)0x400100A4)) +#define UART4_9BITAMASK_R (*((volatile uint32_t *)0x400100A8)) +#define UART4_PP_R (*((volatile uint32_t *)0x40010FC0)) +#define UART4_CC_R (*((volatile uint32_t *)0x40010FC8)) + +//***************************************************************************** +// +// UART registers (UART5) +// +//***************************************************************************** +#define UART5_DR_R (*((volatile uint32_t *)0x40011000)) +#define UART5_RSR_R (*((volatile uint32_t *)0x40011004)) +#define UART5_ECR_R (*((volatile uint32_t *)0x40011004)) +#define UART5_FR_R (*((volatile uint32_t *)0x40011018)) +#define UART5_ILPR_R (*((volatile uint32_t *)0x40011020)) +#define UART5_IBRD_R (*((volatile uint32_t *)0x40011024)) +#define UART5_FBRD_R (*((volatile uint32_t *)0x40011028)) +#define UART5_LCRH_R (*((volatile uint32_t *)0x4001102C)) +#define UART5_CTL_R (*((volatile uint32_t *)0x40011030)) +#define UART5_IFLS_R (*((volatile uint32_t *)0x40011034)) +#define UART5_IM_R (*((volatile uint32_t *)0x40011038)) +#define UART5_RIS_R (*((volatile uint32_t *)0x4001103C)) +#define UART5_MIS_R (*((volatile uint32_t *)0x40011040)) +#define UART5_ICR_R (*((volatile uint32_t *)0x40011044)) +#define UART5_DMACTL_R (*((volatile uint32_t *)0x40011048)) +#define UART5_9BITADDR_R (*((volatile uint32_t *)0x400110A4)) +#define UART5_9BITAMASK_R (*((volatile uint32_t *)0x400110A8)) +#define UART5_PP_R (*((volatile uint32_t *)0x40011FC0)) +#define UART5_CC_R (*((volatile uint32_t *)0x40011FC8)) + +//***************************************************************************** +// +// UART registers (UART6) +// +//***************************************************************************** +#define UART6_DR_R (*((volatile uint32_t *)0x40012000)) +#define UART6_RSR_R (*((volatile uint32_t *)0x40012004)) +#define UART6_ECR_R (*((volatile uint32_t *)0x40012004)) +#define UART6_FR_R (*((volatile uint32_t *)0x40012018)) +#define UART6_ILPR_R (*((volatile uint32_t *)0x40012020)) +#define UART6_IBRD_R (*((volatile uint32_t *)0x40012024)) +#define UART6_FBRD_R (*((volatile uint32_t *)0x40012028)) +#define UART6_LCRH_R (*((volatile uint32_t *)0x4001202C)) +#define UART6_CTL_R (*((volatile uint32_t *)0x40012030)) +#define UART6_IFLS_R (*((volatile uint32_t *)0x40012034)) +#define UART6_IM_R (*((volatile uint32_t *)0x40012038)) +#define UART6_RIS_R (*((volatile uint32_t *)0x4001203C)) +#define UART6_MIS_R (*((volatile uint32_t *)0x40012040)) +#define UART6_ICR_R (*((volatile uint32_t *)0x40012044)) +#define UART6_DMACTL_R (*((volatile uint32_t *)0x40012048)) +#define UART6_9BITADDR_R (*((volatile uint32_t *)0x400120A4)) +#define UART6_9BITAMASK_R (*((volatile uint32_t *)0x400120A8)) +#define UART6_PP_R (*((volatile uint32_t *)0x40012FC0)) +#define UART6_CC_R (*((volatile uint32_t *)0x40012FC8)) + +//***************************************************************************** +// +// UART registers (UART7) +// +//***************************************************************************** +#define UART7_DR_R (*((volatile uint32_t *)0x40013000)) +#define UART7_RSR_R (*((volatile uint32_t *)0x40013004)) +#define UART7_ECR_R (*((volatile uint32_t *)0x40013004)) +#define UART7_FR_R (*((volatile uint32_t *)0x40013018)) +#define UART7_ILPR_R (*((volatile uint32_t *)0x40013020)) +#define UART7_IBRD_R (*((volatile uint32_t *)0x40013024)) +#define UART7_FBRD_R (*((volatile uint32_t *)0x40013028)) +#define UART7_LCRH_R (*((volatile uint32_t *)0x4001302C)) +#define UART7_CTL_R (*((volatile uint32_t *)0x40013030)) +#define UART7_IFLS_R (*((volatile uint32_t *)0x40013034)) +#define UART7_IM_R (*((volatile uint32_t *)0x40013038)) +#define UART7_RIS_R (*((volatile uint32_t *)0x4001303C)) +#define UART7_MIS_R (*((volatile uint32_t *)0x40013040)) +#define UART7_ICR_R (*((volatile uint32_t *)0x40013044)) +#define UART7_DMACTL_R (*((volatile uint32_t *)0x40013048)) +#define UART7_9BITADDR_R (*((volatile uint32_t *)0x400130A4)) +#define UART7_9BITAMASK_R (*((volatile uint32_t *)0x400130A8)) +#define UART7_PP_R (*((volatile uint32_t *)0x40013FC0)) +#define UART7_CC_R (*((volatile uint32_t *)0x40013FC8)) + +//***************************************************************************** +// +// I2C registers (I2C0) +// +//***************************************************************************** +#define I2C0_MSA_R (*((volatile uint32_t *)0x40020000)) +#define I2C0_MCS_R (*((volatile uint32_t *)0x40020004)) +#define I2C0_MDR_R (*((volatile uint32_t *)0x40020008)) +#define I2C0_MTPR_R (*((volatile uint32_t *)0x4002000C)) +#define I2C0_MIMR_R (*((volatile uint32_t *)0x40020010)) +#define I2C0_MRIS_R (*((volatile uint32_t *)0x40020014)) +#define I2C0_MMIS_R (*((volatile uint32_t *)0x40020018)) +#define I2C0_MICR_R (*((volatile uint32_t *)0x4002001C)) +#define I2C0_MCR_R (*((volatile uint32_t *)0x40020020)) +#define I2C0_MCLKOCNT_R (*((volatile uint32_t *)0x40020024)) +#define I2C0_MBMON_R (*((volatile uint32_t *)0x4002002C)) +#define I2C0_MCR2_R (*((volatile uint32_t *)0x40020038)) +#define I2C0_SOAR_R (*((volatile uint32_t *)0x40020800)) +#define I2C0_SCSR_R (*((volatile uint32_t *)0x40020804)) +#define I2C0_SDR_R (*((volatile uint32_t *)0x40020808)) +#define I2C0_SIMR_R (*((volatile uint32_t *)0x4002080C)) +#define I2C0_SRIS_R (*((volatile uint32_t *)0x40020810)) +#define I2C0_SMIS_R (*((volatile uint32_t *)0x40020814)) +#define I2C0_SICR_R (*((volatile uint32_t *)0x40020818)) +#define I2C0_SOAR2_R (*((volatile uint32_t *)0x4002081C)) +#define I2C0_SACKCTL_R (*((volatile uint32_t *)0x40020820)) +#define I2C0_PP_R (*((volatile uint32_t *)0x40020FC0)) +#define I2C0_PC_R (*((volatile uint32_t *)0x40020FC4)) + +//***************************************************************************** +// +// I2C registers (I2C1) +// +//***************************************************************************** +#define I2C1_MSA_R (*((volatile uint32_t *)0x40021000)) +#define I2C1_MCS_R (*((volatile uint32_t *)0x40021004)) +#define I2C1_MDR_R (*((volatile uint32_t *)0x40021008)) +#define I2C1_MTPR_R (*((volatile uint32_t *)0x4002100C)) +#define I2C1_MIMR_R (*((volatile uint32_t *)0x40021010)) +#define I2C1_MRIS_R (*((volatile uint32_t *)0x40021014)) +#define I2C1_MMIS_R (*((volatile uint32_t *)0x40021018)) +#define I2C1_MICR_R (*((volatile uint32_t *)0x4002101C)) +#define I2C1_MCR_R (*((volatile uint32_t *)0x40021020)) +#define I2C1_MCLKOCNT_R (*((volatile uint32_t *)0x40021024)) +#define I2C1_MBMON_R (*((volatile uint32_t *)0x4002102C)) +#define I2C1_MCR2_R (*((volatile uint32_t *)0x40021038)) +#define I2C1_SOAR_R (*((volatile uint32_t *)0x40021800)) +#define I2C1_SCSR_R (*((volatile uint32_t *)0x40021804)) +#define I2C1_SDR_R (*((volatile uint32_t *)0x40021808)) +#define I2C1_SIMR_R (*((volatile uint32_t *)0x4002180C)) +#define I2C1_SRIS_R (*((volatile uint32_t *)0x40021810)) +#define I2C1_SMIS_R (*((volatile uint32_t *)0x40021814)) +#define I2C1_SICR_R (*((volatile uint32_t *)0x40021818)) +#define I2C1_SOAR2_R (*((volatile uint32_t *)0x4002181C)) +#define I2C1_SACKCTL_R (*((volatile uint32_t *)0x40021820)) +#define I2C1_PP_R (*((volatile uint32_t *)0x40021FC0)) +#define I2C1_PC_R (*((volatile uint32_t *)0x40021FC4)) + +//***************************************************************************** +// +// I2C registers (I2C2) +// +//***************************************************************************** +#define I2C2_MSA_R (*((volatile uint32_t *)0x40022000)) +#define I2C2_MCS_R (*((volatile uint32_t *)0x40022004)) +#define I2C2_MDR_R (*((volatile uint32_t *)0x40022008)) +#define I2C2_MTPR_R (*((volatile uint32_t *)0x4002200C)) +#define I2C2_MIMR_R (*((volatile uint32_t *)0x40022010)) +#define I2C2_MRIS_R (*((volatile uint32_t *)0x40022014)) +#define I2C2_MMIS_R (*((volatile uint32_t *)0x40022018)) +#define I2C2_MICR_R (*((volatile uint32_t *)0x4002201C)) +#define I2C2_MCR_R (*((volatile uint32_t *)0x40022020)) +#define I2C2_MCLKOCNT_R (*((volatile uint32_t *)0x40022024)) +#define I2C2_MBMON_R (*((volatile uint32_t *)0x4002202C)) +#define I2C2_MCR2_R (*((volatile uint32_t *)0x40022038)) +#define I2C2_SOAR_R (*((volatile uint32_t *)0x40022800)) +#define I2C2_SCSR_R (*((volatile uint32_t *)0x40022804)) +#define I2C2_SDR_R (*((volatile uint32_t *)0x40022808)) +#define I2C2_SIMR_R (*((volatile uint32_t *)0x4002280C)) +#define I2C2_SRIS_R (*((volatile uint32_t *)0x40022810)) +#define I2C2_SMIS_R (*((volatile uint32_t *)0x40022814)) +#define I2C2_SICR_R (*((volatile uint32_t *)0x40022818)) +#define I2C2_SOAR2_R (*((volatile uint32_t *)0x4002281C)) +#define I2C2_SACKCTL_R (*((volatile uint32_t *)0x40022820)) +#define I2C2_PP_R (*((volatile uint32_t *)0x40022FC0)) +#define I2C2_PC_R (*((volatile uint32_t *)0x40022FC4)) + +//***************************************************************************** +// +// I2C registers (I2C3) +// +//***************************************************************************** +#define I2C3_MSA_R (*((volatile uint32_t *)0x40023000)) +#define I2C3_MCS_R (*((volatile uint32_t *)0x40023004)) +#define I2C3_MDR_R (*((volatile uint32_t *)0x40023008)) +#define I2C3_MTPR_R (*((volatile uint32_t *)0x4002300C)) +#define I2C3_MIMR_R (*((volatile uint32_t *)0x40023010)) +#define I2C3_MRIS_R (*((volatile uint32_t *)0x40023014)) +#define I2C3_MMIS_R (*((volatile uint32_t *)0x40023018)) +#define I2C3_MICR_R (*((volatile uint32_t *)0x4002301C)) +#define I2C3_MCR_R (*((volatile uint32_t *)0x40023020)) +#define I2C3_MCLKOCNT_R (*((volatile uint32_t *)0x40023024)) +#define I2C3_MBMON_R (*((volatile uint32_t *)0x4002302C)) +#define I2C3_MCR2_R (*((volatile uint32_t *)0x40023038)) +#define I2C3_SOAR_R (*((volatile uint32_t *)0x40023800)) +#define I2C3_SCSR_R (*((volatile uint32_t *)0x40023804)) +#define I2C3_SDR_R (*((volatile uint32_t *)0x40023808)) +#define I2C3_SIMR_R (*((volatile uint32_t *)0x4002380C)) +#define I2C3_SRIS_R (*((volatile uint32_t *)0x40023810)) +#define I2C3_SMIS_R (*((volatile uint32_t *)0x40023814)) +#define I2C3_SICR_R (*((volatile uint32_t *)0x40023818)) +#define I2C3_SOAR2_R (*((volatile uint32_t *)0x4002381C)) +#define I2C3_SACKCTL_R (*((volatile uint32_t *)0x40023820)) +#define I2C3_PP_R (*((volatile uint32_t *)0x40023FC0)) +#define I2C3_PC_R (*((volatile uint32_t *)0x40023FC4)) + +//***************************************************************************** +// +// GPIO registers (PORTE) +// +//***************************************************************************** +#define GPIO_PORTE_DATA_BITS_R ((volatile uint32_t *)0x40024000) +#define GPIO_PORTE_DATA_R (*((volatile uint32_t *)0x400243FC)) +#define GPIO_PORTE_DIR_R (*((volatile uint32_t *)0x40024400)) +#define GPIO_PORTE_IS_R (*((volatile uint32_t *)0x40024404)) +#define GPIO_PORTE_IBE_R (*((volatile uint32_t *)0x40024408)) +#define GPIO_PORTE_IEV_R (*((volatile uint32_t *)0x4002440C)) +#define GPIO_PORTE_IM_R (*((volatile uint32_t *)0x40024410)) +#define GPIO_PORTE_RIS_R (*((volatile uint32_t *)0x40024414)) +#define GPIO_PORTE_MIS_R (*((volatile uint32_t *)0x40024418)) +#define GPIO_PORTE_ICR_R (*((volatile uint32_t *)0x4002441C)) +#define GPIO_PORTE_AFSEL_R (*((volatile uint32_t *)0x40024420)) +#define GPIO_PORTE_DR2R_R (*((volatile uint32_t *)0x40024500)) +#define GPIO_PORTE_DR4R_R (*((volatile uint32_t *)0x40024504)) +#define GPIO_PORTE_DR8R_R (*((volatile uint32_t *)0x40024508)) +#define GPIO_PORTE_ODR_R (*((volatile uint32_t *)0x4002450C)) +#define GPIO_PORTE_PUR_R (*((volatile uint32_t *)0x40024510)) +#define GPIO_PORTE_PDR_R (*((volatile uint32_t *)0x40024514)) +#define GPIO_PORTE_SLR_R (*((volatile uint32_t *)0x40024518)) +#define GPIO_PORTE_DEN_R (*((volatile uint32_t *)0x4002451C)) +#define GPIO_PORTE_LOCK_R (*((volatile uint32_t *)0x40024520)) +#define GPIO_PORTE_CR_R (*((volatile uint32_t *)0x40024524)) +#define GPIO_PORTE_AMSEL_R (*((volatile uint32_t *)0x40024528)) +#define GPIO_PORTE_PCTL_R (*((volatile uint32_t *)0x4002452C)) +#define GPIO_PORTE_ADCCTL_R (*((volatile uint32_t *)0x40024530)) +#define GPIO_PORTE_DMACTL_R (*((volatile uint32_t *)0x40024534)) + +//***************************************************************************** +// +// GPIO registers (PORTF) +// +//***************************************************************************** +#define GPIO_PORTF_DATA_BITS_R ((volatile uint32_t *)0x40025000) +#define GPIO_PORTF_DATA_R (*((volatile uint32_t *)0x400253FC)) +#define GPIO_PORTF_DIR_R (*((volatile uint32_t *)0x40025400)) +#define GPIO_PORTF_IS_R (*((volatile uint32_t *)0x40025404)) +#define GPIO_PORTF_IBE_R (*((volatile uint32_t *)0x40025408)) +#define GPIO_PORTF_IEV_R (*((volatile uint32_t *)0x4002540C)) +#define GPIO_PORTF_IM_R (*((volatile uint32_t *)0x40025410)) +#define GPIO_PORTF_RIS_R (*((volatile uint32_t *)0x40025414)) +#define GPIO_PORTF_MIS_R (*((volatile uint32_t *)0x40025418)) +#define GPIO_PORTF_ICR_R (*((volatile uint32_t *)0x4002541C)) +#define GPIO_PORTF_AFSEL_R (*((volatile uint32_t *)0x40025420)) +#define GPIO_PORTF_DR2R_R (*((volatile uint32_t *)0x40025500)) +#define GPIO_PORTF_DR4R_R (*((volatile uint32_t *)0x40025504)) +#define GPIO_PORTF_DR8R_R (*((volatile uint32_t *)0x40025508)) +#define GPIO_PORTF_ODR_R (*((volatile uint32_t *)0x4002550C)) +#define GPIO_PORTF_PUR_R (*((volatile uint32_t *)0x40025510)) +#define GPIO_PORTF_PDR_R (*((volatile uint32_t *)0x40025514)) +#define GPIO_PORTF_SLR_R (*((volatile uint32_t *)0x40025518)) +#define GPIO_PORTF_DEN_R (*((volatile uint32_t *)0x4002551C)) +#define GPIO_PORTF_LOCK_R (*((volatile uint32_t *)0x40025520)) +#define GPIO_PORTF_CR_R (*((volatile uint32_t *)0x40025524)) +#define GPIO_PORTF_AMSEL_R (*((volatile uint32_t *)0x40025528)) +#define GPIO_PORTF_PCTL_R (*((volatile uint32_t *)0x4002552C)) +#define GPIO_PORTF_ADCCTL_R (*((volatile uint32_t *)0x40025530)) +#define GPIO_PORTF_DMACTL_R (*((volatile uint32_t *)0x40025534)) + +//***************************************************************************** +// +// PWM registers (PWM0) +// +//***************************************************************************** +#define PWM0_CTL_R (*((volatile uint32_t *)0x40028000)) +#define PWM0_SYNC_R (*((volatile uint32_t *)0x40028004)) +#define PWM0_ENABLE_R (*((volatile uint32_t *)0x40028008)) +#define PWM0_INVERT_R (*((volatile uint32_t *)0x4002800C)) +#define PWM0_FAULT_R (*((volatile uint32_t *)0x40028010)) +#define PWM0_INTEN_R (*((volatile uint32_t *)0x40028014)) +#define PWM0_RIS_R (*((volatile uint32_t *)0x40028018)) +#define PWM0_ISC_R (*((volatile uint32_t *)0x4002801C)) +#define PWM0_STATUS_R (*((volatile uint32_t *)0x40028020)) +#define PWM0_FAULTVAL_R (*((volatile uint32_t *)0x40028024)) +#define PWM0_ENUPD_R (*((volatile uint32_t *)0x40028028)) +#define PWM0_0_CTL_R (*((volatile uint32_t *)0x40028040)) +#define PWM0_0_INTEN_R (*((volatile uint32_t *)0x40028044)) +#define PWM0_0_RIS_R (*((volatile uint32_t *)0x40028048)) +#define PWM0_0_ISC_R (*((volatile uint32_t *)0x4002804C)) +#define PWM0_0_LOAD_R (*((volatile uint32_t *)0x40028050)) +#define PWM0_0_COUNT_R (*((volatile uint32_t *)0x40028054)) +#define PWM0_0_CMPA_R (*((volatile uint32_t *)0x40028058)) +#define PWM0_0_CMPB_R (*((volatile uint32_t *)0x4002805C)) +#define PWM0_0_GENA_R (*((volatile uint32_t *)0x40028060)) +#define PWM0_0_GENB_R (*((volatile uint32_t *)0x40028064)) +#define PWM0_0_DBCTL_R (*((volatile uint32_t *)0x40028068)) +#define PWM0_0_DBRISE_R (*((volatile uint32_t *)0x4002806C)) +#define PWM0_0_DBFALL_R (*((volatile uint32_t *)0x40028070)) +#define PWM0_0_FLTSRC0_R (*((volatile uint32_t *)0x40028074)) +#define PWM0_0_FLTSRC1_R (*((volatile uint32_t *)0x40028078)) +#define PWM0_0_MINFLTPER_R (*((volatile uint32_t *)0x4002807C)) +#define PWM0_1_CTL_R (*((volatile uint32_t *)0x40028080)) +#define PWM0_1_INTEN_R (*((volatile uint32_t *)0x40028084)) +#define PWM0_1_RIS_R (*((volatile uint32_t *)0x40028088)) +#define PWM0_1_ISC_R (*((volatile uint32_t *)0x4002808C)) +#define PWM0_1_LOAD_R (*((volatile uint32_t *)0x40028090)) +#define PWM0_1_COUNT_R (*((volatile uint32_t *)0x40028094)) +#define PWM0_1_CMPA_R (*((volatile uint32_t *)0x40028098)) +#define PWM0_1_CMPB_R (*((volatile uint32_t *)0x4002809C)) +#define PWM0_1_GENA_R (*((volatile uint32_t *)0x400280A0)) +#define PWM0_1_GENB_R (*((volatile uint32_t *)0x400280A4)) +#define PWM0_1_DBCTL_R (*((volatile uint32_t *)0x400280A8)) +#define PWM0_1_DBRISE_R (*((volatile uint32_t *)0x400280AC)) +#define PWM0_1_DBFALL_R (*((volatile uint32_t *)0x400280B0)) +#define PWM0_1_FLTSRC0_R (*((volatile uint32_t *)0x400280B4)) +#define PWM0_1_FLTSRC1_R (*((volatile uint32_t *)0x400280B8)) +#define PWM0_1_MINFLTPER_R (*((volatile uint32_t *)0x400280BC)) +#define PWM0_2_CTL_R (*((volatile uint32_t *)0x400280C0)) +#define PWM0_2_INTEN_R (*((volatile uint32_t *)0x400280C4)) +#define PWM0_2_RIS_R (*((volatile uint32_t *)0x400280C8)) +#define PWM0_2_ISC_R (*((volatile uint32_t *)0x400280CC)) +#define PWM0_2_LOAD_R (*((volatile uint32_t *)0x400280D0)) +#define PWM0_2_COUNT_R (*((volatile uint32_t *)0x400280D4)) +#define PWM0_2_CMPA_R (*((volatile uint32_t *)0x400280D8)) +#define PWM0_2_CMPB_R (*((volatile uint32_t *)0x400280DC)) +#define PWM0_2_GENA_R (*((volatile uint32_t *)0x400280E0)) +#define PWM0_2_GENB_R (*((volatile uint32_t *)0x400280E4)) +#define PWM0_2_DBCTL_R (*((volatile uint32_t *)0x400280E8)) +#define PWM0_2_DBRISE_R (*((volatile uint32_t *)0x400280EC)) +#define PWM0_2_DBFALL_R (*((volatile uint32_t *)0x400280F0)) +#define PWM0_2_FLTSRC0_R (*((volatile uint32_t *)0x400280F4)) +#define PWM0_2_FLTSRC1_R (*((volatile uint32_t *)0x400280F8)) +#define PWM0_2_MINFLTPER_R (*((volatile uint32_t *)0x400280FC)) +#define PWM0_3_CTL_R (*((volatile uint32_t *)0x40028100)) +#define PWM0_3_INTEN_R (*((volatile uint32_t *)0x40028104)) +#define PWM0_3_RIS_R (*((volatile uint32_t *)0x40028108)) +#define PWM0_3_ISC_R (*((volatile uint32_t *)0x4002810C)) +#define PWM0_3_LOAD_R (*((volatile uint32_t *)0x40028110)) +#define PWM0_3_COUNT_R (*((volatile uint32_t *)0x40028114)) +#define PWM0_3_CMPA_R (*((volatile uint32_t *)0x40028118)) +#define PWM0_3_CMPB_R (*((volatile uint32_t *)0x4002811C)) +#define PWM0_3_GENA_R (*((volatile uint32_t *)0x40028120)) +#define PWM0_3_GENB_R (*((volatile uint32_t *)0x40028124)) +#define PWM0_3_DBCTL_R (*((volatile uint32_t *)0x40028128)) +#define PWM0_3_DBRISE_R (*((volatile uint32_t *)0x4002812C)) +#define PWM0_3_DBFALL_R (*((volatile uint32_t *)0x40028130)) +#define PWM0_3_FLTSRC0_R (*((volatile uint32_t *)0x40028134)) +#define PWM0_3_FLTSRC1_R (*((volatile uint32_t *)0x40028138)) +#define PWM0_3_MINFLTPER_R (*((volatile uint32_t *)0x4002813C)) +#define PWM0_0_FLTSEN_R (*((volatile uint32_t *)0x40028800)) +#define PWM0_0_FLTSTAT0_R (*((volatile uint32_t *)0x40028804)) +#define PWM0_0_FLTSTAT1_R (*((volatile uint32_t *)0x40028808)) +#define PWM0_1_FLTSEN_R (*((volatile uint32_t *)0x40028880)) +#define PWM0_1_FLTSTAT0_R (*((volatile uint32_t *)0x40028884)) +#define PWM0_1_FLTSTAT1_R (*((volatile uint32_t *)0x40028888)) +#define PWM0_2_FLTSTAT0_R (*((volatile uint32_t *)0x40028904)) +#define PWM0_2_FLTSTAT1_R (*((volatile uint32_t *)0x40028908)) +#define PWM0_3_FLTSTAT0_R (*((volatile uint32_t *)0x40028984)) +#define PWM0_3_FLTSTAT1_R (*((volatile uint32_t *)0x40028988)) +#define PWM0_PP_R (*((volatile uint32_t *)0x40028FC0)) + +//***************************************************************************** +// +// PWM registers (PWM1) +// +//***************************************************************************** +#define PWM1_CTL_R (*((volatile uint32_t *)0x40029000)) +#define PWM1_SYNC_R (*((volatile uint32_t *)0x40029004)) +#define PWM1_ENABLE_R (*((volatile uint32_t *)0x40029008)) +#define PWM1_INVERT_R (*((volatile uint32_t *)0x4002900C)) +#define PWM1_FAULT_R (*((volatile uint32_t *)0x40029010)) +#define PWM1_INTEN_R (*((volatile uint32_t *)0x40029014)) +#define PWM1_RIS_R (*((volatile uint32_t *)0x40029018)) +#define PWM1_ISC_R (*((volatile uint32_t *)0x4002901C)) +#define PWM1_STATUS_R (*((volatile uint32_t *)0x40029020)) +#define PWM1_FAULTVAL_R (*((volatile uint32_t *)0x40029024)) +#define PWM1_ENUPD_R (*((volatile uint32_t *)0x40029028)) +#define PWM1_0_CTL_R (*((volatile uint32_t *)0x40029040)) +#define PWM1_0_INTEN_R (*((volatile uint32_t *)0x40029044)) +#define PWM1_0_RIS_R (*((volatile uint32_t *)0x40029048)) +#define PWM1_0_ISC_R (*((volatile uint32_t *)0x4002904C)) +#define PWM1_0_LOAD_R (*((volatile uint32_t *)0x40029050)) +#define PWM1_0_COUNT_R (*((volatile uint32_t *)0x40029054)) +#define PWM1_0_CMPA_R (*((volatile uint32_t *)0x40029058)) +#define PWM1_0_CMPB_R (*((volatile uint32_t *)0x4002905C)) +#define PWM1_0_GENA_R (*((volatile uint32_t *)0x40029060)) +#define PWM1_0_GENB_R (*((volatile uint32_t *)0x40029064)) +#define PWM1_0_DBCTL_R (*((volatile uint32_t *)0x40029068)) +#define PWM1_0_DBRISE_R (*((volatile uint32_t *)0x4002906C)) +#define PWM1_0_DBFALL_R (*((volatile uint32_t *)0x40029070)) +#define PWM1_0_FLTSRC0_R (*((volatile uint32_t *)0x40029074)) +#define PWM1_0_FLTSRC1_R (*((volatile uint32_t *)0x40029078)) +#define PWM1_0_MINFLTPER_R (*((volatile uint32_t *)0x4002907C)) +#define PWM1_1_CTL_R (*((volatile uint32_t *)0x40029080)) +#define PWM1_1_INTEN_R (*((volatile uint32_t *)0x40029084)) +#define PWM1_1_RIS_R (*((volatile uint32_t *)0x40029088)) +#define PWM1_1_ISC_R (*((volatile uint32_t *)0x4002908C)) +#define PWM1_1_LOAD_R (*((volatile uint32_t *)0x40029090)) +#define PWM1_1_COUNT_R (*((volatile uint32_t *)0x40029094)) +#define PWM1_1_CMPA_R (*((volatile uint32_t *)0x40029098)) +#define PWM1_1_CMPB_R (*((volatile uint32_t *)0x4002909C)) +#define PWM1_1_GENA_R (*((volatile uint32_t *)0x400290A0)) +#define PWM1_1_GENB_R (*((volatile uint32_t *)0x400290A4)) +#define PWM1_1_DBCTL_R (*((volatile uint32_t *)0x400290A8)) +#define PWM1_1_DBRISE_R (*((volatile uint32_t *)0x400290AC)) +#define PWM1_1_DBFALL_R (*((volatile uint32_t *)0x400290B0)) +#define PWM1_1_FLTSRC0_R (*((volatile uint32_t *)0x400290B4)) +#define PWM1_1_FLTSRC1_R (*((volatile uint32_t *)0x400290B8)) +#define PWM1_1_MINFLTPER_R (*((volatile uint32_t *)0x400290BC)) +#define PWM1_2_CTL_R (*((volatile uint32_t *)0x400290C0)) +#define PWM1_2_INTEN_R (*((volatile uint32_t *)0x400290C4)) +#define PWM1_2_RIS_R (*((volatile uint32_t *)0x400290C8)) +#define PWM1_2_ISC_R (*((volatile uint32_t *)0x400290CC)) +#define PWM1_2_LOAD_R (*((volatile uint32_t *)0x400290D0)) +#define PWM1_2_COUNT_R (*((volatile uint32_t *)0x400290D4)) +#define PWM1_2_CMPA_R (*((volatile uint32_t *)0x400290D8)) +#define PWM1_2_CMPB_R (*((volatile uint32_t *)0x400290DC)) +#define PWM1_2_GENA_R (*((volatile uint32_t *)0x400290E0)) +#define PWM1_2_GENB_R (*((volatile uint32_t *)0x400290E4)) +#define PWM1_2_DBCTL_R (*((volatile uint32_t *)0x400290E8)) +#define PWM1_2_DBRISE_R (*((volatile uint32_t *)0x400290EC)) +#define PWM1_2_DBFALL_R (*((volatile uint32_t *)0x400290F0)) +#define PWM1_2_FLTSRC0_R (*((volatile uint32_t *)0x400290F4)) +#define PWM1_2_FLTSRC1_R (*((volatile uint32_t *)0x400290F8)) +#define PWM1_2_MINFLTPER_R (*((volatile uint32_t *)0x400290FC)) +#define PWM1_3_CTL_R (*((volatile uint32_t *)0x40029100)) +#define PWM1_3_INTEN_R (*((volatile uint32_t *)0x40029104)) +#define PWM1_3_RIS_R (*((volatile uint32_t *)0x40029108)) +#define PWM1_3_ISC_R (*((volatile uint32_t *)0x4002910C)) +#define PWM1_3_LOAD_R (*((volatile uint32_t *)0x40029110)) +#define PWM1_3_COUNT_R (*((volatile uint32_t *)0x40029114)) +#define PWM1_3_CMPA_R (*((volatile uint32_t *)0x40029118)) +#define PWM1_3_CMPB_R (*((volatile uint32_t *)0x4002911C)) +#define PWM1_3_GENA_R (*((volatile uint32_t *)0x40029120)) +#define PWM1_3_GENB_R (*((volatile uint32_t *)0x40029124)) +#define PWM1_3_DBCTL_R (*((volatile uint32_t *)0x40029128)) +#define PWM1_3_DBRISE_R (*((volatile uint32_t *)0x4002912C)) +#define PWM1_3_DBFALL_R (*((volatile uint32_t *)0x40029130)) +#define PWM1_3_FLTSRC0_R (*((volatile uint32_t *)0x40029134)) +#define PWM1_3_FLTSRC1_R (*((volatile uint32_t *)0x40029138)) +#define PWM1_3_MINFLTPER_R (*((volatile uint32_t *)0x4002913C)) +#define PWM1_0_FLTSEN_R (*((volatile uint32_t *)0x40029800)) +#define PWM1_0_FLTSTAT0_R (*((volatile uint32_t *)0x40029804)) +#define PWM1_0_FLTSTAT1_R (*((volatile uint32_t *)0x40029808)) +#define PWM1_1_FLTSEN_R (*((volatile uint32_t *)0x40029880)) +#define PWM1_1_FLTSTAT0_R (*((volatile uint32_t *)0x40029884)) +#define PWM1_1_FLTSTAT1_R (*((volatile uint32_t *)0x40029888)) +#define PWM1_2_FLTSTAT0_R (*((volatile uint32_t *)0x40029904)) +#define PWM1_2_FLTSTAT1_R (*((volatile uint32_t *)0x40029908)) +#define PWM1_3_FLTSTAT0_R (*((volatile uint32_t *)0x40029984)) +#define PWM1_3_FLTSTAT1_R (*((volatile uint32_t *)0x40029988)) +#define PWM1_PP_R (*((volatile uint32_t *)0x40029FC0)) + +//***************************************************************************** +// +// QEI registers (QEI0) +// +//***************************************************************************** +#define QEI0_CTL_R (*((volatile uint32_t *)0x4002C000)) +#define QEI0_STAT_R (*((volatile uint32_t *)0x4002C004)) +#define QEI0_POS_R (*((volatile uint32_t *)0x4002C008)) +#define QEI0_MAXPOS_R (*((volatile uint32_t *)0x4002C00C)) +#define QEI0_LOAD_R (*((volatile uint32_t *)0x4002C010)) +#define QEI0_TIME_R (*((volatile uint32_t *)0x4002C014)) +#define QEI0_COUNT_R (*((volatile uint32_t *)0x4002C018)) +#define QEI0_SPEED_R (*((volatile uint32_t *)0x4002C01C)) +#define QEI0_INTEN_R (*((volatile uint32_t *)0x4002C020)) +#define QEI0_RIS_R (*((volatile uint32_t *)0x4002C024)) +#define QEI0_ISC_R (*((volatile uint32_t *)0x4002C028)) + +//***************************************************************************** +// +// QEI registers (QEI1) +// +//***************************************************************************** +#define QEI1_CTL_R (*((volatile uint32_t *)0x4002D000)) +#define QEI1_STAT_R (*((volatile uint32_t *)0x4002D004)) +#define QEI1_POS_R (*((volatile uint32_t *)0x4002D008)) +#define QEI1_MAXPOS_R (*((volatile uint32_t *)0x4002D00C)) +#define QEI1_LOAD_R (*((volatile uint32_t *)0x4002D010)) +#define QEI1_TIME_R (*((volatile uint32_t *)0x4002D014)) +#define QEI1_COUNT_R (*((volatile uint32_t *)0x4002D018)) +#define QEI1_SPEED_R (*((volatile uint32_t *)0x4002D01C)) +#define QEI1_INTEN_R (*((volatile uint32_t *)0x4002D020)) +#define QEI1_RIS_R (*((volatile uint32_t *)0x4002D024)) +#define QEI1_ISC_R (*((volatile uint32_t *)0x4002D028)) + +//***************************************************************************** +// +// Timer registers (TIMER0) +// +//***************************************************************************** +#define TIMER0_CFG_R (*((volatile uint32_t *)0x40030000)) +#define TIMER0_TAMR_R (*((volatile uint32_t *)0x40030004)) +#define TIMER0_TBMR_R (*((volatile uint32_t *)0x40030008)) +#define TIMER0_CTL_R (*((volatile uint32_t *)0x4003000C)) +#define TIMER0_SYNC_R (*((volatile uint32_t *)0x40030010)) +#define TIMER0_IMR_R (*((volatile uint32_t *)0x40030018)) +#define TIMER0_RIS_R (*((volatile uint32_t *)0x4003001C)) +#define TIMER0_MIS_R (*((volatile uint32_t *)0x40030020)) +#define TIMER0_ICR_R (*((volatile uint32_t *)0x40030024)) +#define TIMER0_TAILR_R (*((volatile uint32_t *)0x40030028)) +#define TIMER0_TBILR_R (*((volatile uint32_t *)0x4003002C)) +#define TIMER0_TAMATCHR_R (*((volatile uint32_t *)0x40030030)) +#define TIMER0_TBMATCHR_R (*((volatile uint32_t *)0x40030034)) +#define TIMER0_TAPR_R (*((volatile uint32_t *)0x40030038)) +#define TIMER0_TBPR_R (*((volatile uint32_t *)0x4003003C)) +#define TIMER0_TAPMR_R (*((volatile uint32_t *)0x40030040)) +#define TIMER0_TBPMR_R (*((volatile uint32_t *)0x40030044)) +#define TIMER0_TAR_R (*((volatile uint32_t *)0x40030048)) +#define TIMER0_TBR_R (*((volatile uint32_t *)0x4003004C)) +#define TIMER0_TAV_R (*((volatile uint32_t *)0x40030050)) +#define TIMER0_TBV_R (*((volatile uint32_t *)0x40030054)) +#define TIMER0_RTCPD_R (*((volatile uint32_t *)0x40030058)) +#define TIMER0_TAPS_R (*((volatile uint32_t *)0x4003005C)) +#define TIMER0_TBPS_R (*((volatile uint32_t *)0x40030060)) +#define TIMER0_TAPV_R (*((volatile uint32_t *)0x40030064)) +#define TIMER0_TBPV_R (*((volatile uint32_t *)0x40030068)) +#define TIMER0_PP_R (*((volatile uint32_t *)0x40030FC0)) + +//***************************************************************************** +// +// Timer registers (TIMER1) +// +//***************************************************************************** +#define TIMER1_CFG_R (*((volatile uint32_t *)0x40031000)) +#define TIMER1_TAMR_R (*((volatile uint32_t *)0x40031004)) +#define TIMER1_TBMR_R (*((volatile uint32_t *)0x40031008)) +#define TIMER1_CTL_R (*((volatile uint32_t *)0x4003100C)) +#define TIMER1_SYNC_R (*((volatile uint32_t *)0x40031010)) +#define TIMER1_IMR_R (*((volatile uint32_t *)0x40031018)) +#define TIMER1_RIS_R (*((volatile uint32_t *)0x4003101C)) +#define TIMER1_MIS_R (*((volatile uint32_t *)0x40031020)) +#define TIMER1_ICR_R (*((volatile uint32_t *)0x40031024)) +#define TIMER1_TAILR_R (*((volatile uint32_t *)0x40031028)) +#define TIMER1_TBILR_R (*((volatile uint32_t *)0x4003102C)) +#define TIMER1_TAMATCHR_R (*((volatile uint32_t *)0x40031030)) +#define TIMER1_TBMATCHR_R (*((volatile uint32_t *)0x40031034)) +#define TIMER1_TAPR_R (*((volatile uint32_t *)0x40031038)) +#define TIMER1_TBPR_R (*((volatile uint32_t *)0x4003103C)) +#define TIMER1_TAPMR_R (*((volatile uint32_t *)0x40031040)) +#define TIMER1_TBPMR_R (*((volatile uint32_t *)0x40031044)) +#define TIMER1_TAR_R (*((volatile uint32_t *)0x40031048)) +#define TIMER1_TBR_R (*((volatile uint32_t *)0x4003104C)) +#define TIMER1_TAV_R (*((volatile uint32_t *)0x40031050)) +#define TIMER1_TBV_R (*((volatile uint32_t *)0x40031054)) +#define TIMER1_RTCPD_R (*((volatile uint32_t *)0x40031058)) +#define TIMER1_TAPS_R (*((volatile uint32_t *)0x4003105C)) +#define TIMER1_TBPS_R (*((volatile uint32_t *)0x40031060)) +#define TIMER1_TAPV_R (*((volatile uint32_t *)0x40031064)) +#define TIMER1_TBPV_R (*((volatile uint32_t *)0x40031068)) +#define TIMER1_PP_R (*((volatile uint32_t *)0x40031FC0)) + +//***************************************************************************** +// +// Timer registers (TIMER2) +// +//***************************************************************************** +#define TIMER2_CFG_R (*((volatile uint32_t *)0x40032000)) +#define TIMER2_TAMR_R (*((volatile uint32_t *)0x40032004)) +#define TIMER2_TBMR_R (*((volatile uint32_t *)0x40032008)) +#define TIMER2_CTL_R (*((volatile uint32_t *)0x4003200C)) +#define TIMER2_SYNC_R (*((volatile uint32_t *)0x40032010)) +#define TIMER2_IMR_R (*((volatile uint32_t *)0x40032018)) +#define TIMER2_RIS_R (*((volatile uint32_t *)0x4003201C)) +#define TIMER2_MIS_R (*((volatile uint32_t *)0x40032020)) +#define TIMER2_ICR_R (*((volatile uint32_t *)0x40032024)) +#define TIMER2_TAILR_R (*((volatile uint32_t *)0x40032028)) +#define TIMER2_TBILR_R (*((volatile uint32_t *)0x4003202C)) +#define TIMER2_TAMATCHR_R (*((volatile uint32_t *)0x40032030)) +#define TIMER2_TBMATCHR_R (*((volatile uint32_t *)0x40032034)) +#define TIMER2_TAPR_R (*((volatile uint32_t *)0x40032038)) +#define TIMER2_TBPR_R (*((volatile uint32_t *)0x4003203C)) +#define TIMER2_TAPMR_R (*((volatile uint32_t *)0x40032040)) +#define TIMER2_TBPMR_R (*((volatile uint32_t *)0x40032044)) +#define TIMER2_TAR_R (*((volatile uint32_t *)0x40032048)) +#define TIMER2_TBR_R (*((volatile uint32_t *)0x4003204C)) +#define TIMER2_TAV_R (*((volatile uint32_t *)0x40032050)) +#define TIMER2_TBV_R (*((volatile uint32_t *)0x40032054)) +#define TIMER2_RTCPD_R (*((volatile uint32_t *)0x40032058)) +#define TIMER2_TAPS_R (*((volatile uint32_t *)0x4003205C)) +#define TIMER2_TBPS_R (*((volatile uint32_t *)0x40032060)) +#define TIMER2_TAPV_R (*((volatile uint32_t *)0x40032064)) +#define TIMER2_TBPV_R (*((volatile uint32_t *)0x40032068)) +#define TIMER2_PP_R (*((volatile uint32_t *)0x40032FC0)) + +//***************************************************************************** +// +// Timer registers (TIMER3) +// +//***************************************************************************** +#define TIMER3_CFG_R (*((volatile uint32_t *)0x40033000)) +#define TIMER3_TAMR_R (*((volatile uint32_t *)0x40033004)) +#define TIMER3_TBMR_R (*((volatile uint32_t *)0x40033008)) +#define TIMER3_CTL_R (*((volatile uint32_t *)0x4003300C)) +#define TIMER3_SYNC_R (*((volatile uint32_t *)0x40033010)) +#define TIMER3_IMR_R (*((volatile uint32_t *)0x40033018)) +#define TIMER3_RIS_R (*((volatile uint32_t *)0x4003301C)) +#define TIMER3_MIS_R (*((volatile uint32_t *)0x40033020)) +#define TIMER3_ICR_R (*((volatile uint32_t *)0x40033024)) +#define TIMER3_TAILR_R (*((volatile uint32_t *)0x40033028)) +#define TIMER3_TBILR_R (*((volatile uint32_t *)0x4003302C)) +#define TIMER3_TAMATCHR_R (*((volatile uint32_t *)0x40033030)) +#define TIMER3_TBMATCHR_R (*((volatile uint32_t *)0x40033034)) +#define TIMER3_TAPR_R (*((volatile uint32_t *)0x40033038)) +#define TIMER3_TBPR_R (*((volatile uint32_t *)0x4003303C)) +#define TIMER3_TAPMR_R (*((volatile uint32_t *)0x40033040)) +#define TIMER3_TBPMR_R (*((volatile uint32_t *)0x40033044)) +#define TIMER3_TAR_R (*((volatile uint32_t *)0x40033048)) +#define TIMER3_TBR_R (*((volatile uint32_t *)0x4003304C)) +#define TIMER3_TAV_R (*((volatile uint32_t *)0x40033050)) +#define TIMER3_TBV_R (*((volatile uint32_t *)0x40033054)) +#define TIMER3_RTCPD_R (*((volatile uint32_t *)0x40033058)) +#define TIMER3_TAPS_R (*((volatile uint32_t *)0x4003305C)) +#define TIMER3_TBPS_R (*((volatile uint32_t *)0x40033060)) +#define TIMER3_TAPV_R (*((volatile uint32_t *)0x40033064)) +#define TIMER3_TBPV_R (*((volatile uint32_t *)0x40033068)) +#define TIMER3_PP_R (*((volatile uint32_t *)0x40033FC0)) + +//***************************************************************************** +// +// Timer registers (TIMER4) +// +//***************************************************************************** +#define TIMER4_CFG_R (*((volatile uint32_t *)0x40034000)) +#define TIMER4_TAMR_R (*((volatile uint32_t *)0x40034004)) +#define TIMER4_TBMR_R (*((volatile uint32_t *)0x40034008)) +#define TIMER4_CTL_R (*((volatile uint32_t *)0x4003400C)) +#define TIMER4_SYNC_R (*((volatile uint32_t *)0x40034010)) +#define TIMER4_IMR_R (*((volatile uint32_t *)0x40034018)) +#define TIMER4_RIS_R (*((volatile uint32_t *)0x4003401C)) +#define TIMER4_MIS_R (*((volatile uint32_t *)0x40034020)) +#define TIMER4_ICR_R (*((volatile uint32_t *)0x40034024)) +#define TIMER4_TAILR_R (*((volatile uint32_t *)0x40034028)) +#define TIMER4_TBILR_R (*((volatile uint32_t *)0x4003402C)) +#define TIMER4_TAMATCHR_R (*((volatile uint32_t *)0x40034030)) +#define TIMER4_TBMATCHR_R (*((volatile uint32_t *)0x40034034)) +#define TIMER4_TAPR_R (*((volatile uint32_t *)0x40034038)) +#define TIMER4_TBPR_R (*((volatile uint32_t *)0x4003403C)) +#define TIMER4_TAPMR_R (*((volatile uint32_t *)0x40034040)) +#define TIMER4_TBPMR_R (*((volatile uint32_t *)0x40034044)) +#define TIMER4_TAR_R (*((volatile uint32_t *)0x40034048)) +#define TIMER4_TBR_R (*((volatile uint32_t *)0x4003404C)) +#define TIMER4_TAV_R (*((volatile uint32_t *)0x40034050)) +#define TIMER4_TBV_R (*((volatile uint32_t *)0x40034054)) +#define TIMER4_RTCPD_R (*((volatile uint32_t *)0x40034058)) +#define TIMER4_TAPS_R (*((volatile uint32_t *)0x4003405C)) +#define TIMER4_TBPS_R (*((volatile uint32_t *)0x40034060)) +#define TIMER4_TAPV_R (*((volatile uint32_t *)0x40034064)) +#define TIMER4_TBPV_R (*((volatile uint32_t *)0x40034068)) +#define TIMER4_PP_R (*((volatile uint32_t *)0x40034FC0)) + +//***************************************************************************** +// +// Timer registers (TIMER5) +// +//***************************************************************************** +#define TIMER5_CFG_R (*((volatile uint32_t *)0x40035000)) +#define TIMER5_TAMR_R (*((volatile uint32_t *)0x40035004)) +#define TIMER5_TBMR_R (*((volatile uint32_t *)0x40035008)) +#define TIMER5_CTL_R (*((volatile uint32_t *)0x4003500C)) +#define TIMER5_SYNC_R (*((volatile uint32_t *)0x40035010)) +#define TIMER5_IMR_R (*((volatile uint32_t *)0x40035018)) +#define TIMER5_RIS_R (*((volatile uint32_t *)0x4003501C)) +#define TIMER5_MIS_R (*((volatile uint32_t *)0x40035020)) +#define TIMER5_ICR_R (*((volatile uint32_t *)0x40035024)) +#define TIMER5_TAILR_R (*((volatile uint32_t *)0x40035028)) +#define TIMER5_TBILR_R (*((volatile uint32_t *)0x4003502C)) +#define TIMER5_TAMATCHR_R (*((volatile uint32_t *)0x40035030)) +#define TIMER5_TBMATCHR_R (*((volatile uint32_t *)0x40035034)) +#define TIMER5_TAPR_R (*((volatile uint32_t *)0x40035038)) +#define TIMER5_TBPR_R (*((volatile uint32_t *)0x4003503C)) +#define TIMER5_TAPMR_R (*((volatile uint32_t *)0x40035040)) +#define TIMER5_TBPMR_R (*((volatile uint32_t *)0x40035044)) +#define TIMER5_TAR_R (*((volatile uint32_t *)0x40035048)) +#define TIMER5_TBR_R (*((volatile uint32_t *)0x4003504C)) +#define TIMER5_TAV_R (*((volatile uint32_t *)0x40035050)) +#define TIMER5_TBV_R (*((volatile uint32_t *)0x40035054)) +#define TIMER5_RTCPD_R (*((volatile uint32_t *)0x40035058)) +#define TIMER5_TAPS_R (*((volatile uint32_t *)0x4003505C)) +#define TIMER5_TBPS_R (*((volatile uint32_t *)0x40035060)) +#define TIMER5_TAPV_R (*((volatile uint32_t *)0x40035064)) +#define TIMER5_TBPV_R (*((volatile uint32_t *)0x40035068)) +#define TIMER5_PP_R (*((volatile uint32_t *)0x40035FC0)) + +//***************************************************************************** +// +// Timer registers (WTIMER0) +// +//***************************************************************************** +#define WTIMER0_CFG_R (*((volatile uint32_t *)0x40036000)) +#define WTIMER0_TAMR_R (*((volatile uint32_t *)0x40036004)) +#define WTIMER0_TBMR_R (*((volatile uint32_t *)0x40036008)) +#define WTIMER0_CTL_R (*((volatile uint32_t *)0x4003600C)) +#define WTIMER0_SYNC_R (*((volatile uint32_t *)0x40036010)) +#define WTIMER0_IMR_R (*((volatile uint32_t *)0x40036018)) +#define WTIMER0_RIS_R (*((volatile uint32_t *)0x4003601C)) +#define WTIMER0_MIS_R (*((volatile uint32_t *)0x40036020)) +#define WTIMER0_ICR_R (*((volatile uint32_t *)0x40036024)) +#define WTIMER0_TAILR_R (*((volatile uint32_t *)0x40036028)) +#define WTIMER0_TBILR_R (*((volatile uint32_t *)0x4003602C)) +#define WTIMER0_TAMATCHR_R (*((volatile uint32_t *)0x40036030)) +#define WTIMER0_TBMATCHR_R (*((volatile uint32_t *)0x40036034)) +#define WTIMER0_TAPR_R (*((volatile uint32_t *)0x40036038)) +#define WTIMER0_TBPR_R (*((volatile uint32_t *)0x4003603C)) +#define WTIMER0_TAPMR_R (*((volatile uint32_t *)0x40036040)) +#define WTIMER0_TBPMR_R (*((volatile uint32_t *)0x40036044)) +#define WTIMER0_TAR_R (*((volatile uint32_t *)0x40036048)) +#define WTIMER0_TBR_R (*((volatile uint32_t *)0x4003604C)) +#define WTIMER0_TAV_R (*((volatile uint32_t *)0x40036050)) +#define WTIMER0_TBV_R (*((volatile uint32_t *)0x40036054)) +#define WTIMER0_RTCPD_R (*((volatile uint32_t *)0x40036058)) +#define WTIMER0_TAPS_R (*((volatile uint32_t *)0x4003605C)) +#define WTIMER0_TBPS_R (*((volatile uint32_t *)0x40036060)) +#define WTIMER0_TAPV_R (*((volatile uint32_t *)0x40036064)) +#define WTIMER0_TBPV_R (*((volatile uint32_t *)0x40036068)) +#define WTIMER0_PP_R (*((volatile uint32_t *)0x40036FC0)) + +//***************************************************************************** +// +// Timer registers (WTIMER1) +// +//***************************************************************************** +#define WTIMER1_CFG_R (*((volatile uint32_t *)0x40037000)) +#define WTIMER1_TAMR_R (*((volatile uint32_t *)0x40037004)) +#define WTIMER1_TBMR_R (*((volatile uint32_t *)0x40037008)) +#define WTIMER1_CTL_R (*((volatile uint32_t *)0x4003700C)) +#define WTIMER1_SYNC_R (*((volatile uint32_t *)0x40037010)) +#define WTIMER1_IMR_R (*((volatile uint32_t *)0x40037018)) +#define WTIMER1_RIS_R (*((volatile uint32_t *)0x4003701C)) +#define WTIMER1_MIS_R (*((volatile uint32_t *)0x40037020)) +#define WTIMER1_ICR_R (*((volatile uint32_t *)0x40037024)) +#define WTIMER1_TAILR_R (*((volatile uint32_t *)0x40037028)) +#define WTIMER1_TBILR_R (*((volatile uint32_t *)0x4003702C)) +#define WTIMER1_TAMATCHR_R (*((volatile uint32_t *)0x40037030)) +#define WTIMER1_TBMATCHR_R (*((volatile uint32_t *)0x40037034)) +#define WTIMER1_TAPR_R (*((volatile uint32_t *)0x40037038)) +#define WTIMER1_TBPR_R (*((volatile uint32_t *)0x4003703C)) +#define WTIMER1_TAPMR_R (*((volatile uint32_t *)0x40037040)) +#define WTIMER1_TBPMR_R (*((volatile uint32_t *)0x40037044)) +#define WTIMER1_TAR_R (*((volatile uint32_t *)0x40037048)) +#define WTIMER1_TBR_R (*((volatile uint32_t *)0x4003704C)) +#define WTIMER1_TAV_R (*((volatile uint32_t *)0x40037050)) +#define WTIMER1_TBV_R (*((volatile uint32_t *)0x40037054)) +#define WTIMER1_RTCPD_R (*((volatile uint32_t *)0x40037058)) +#define WTIMER1_TAPS_R (*((volatile uint32_t *)0x4003705C)) +#define WTIMER1_TBPS_R (*((volatile uint32_t *)0x40037060)) +#define WTIMER1_TAPV_R (*((volatile uint32_t *)0x40037064)) +#define WTIMER1_TBPV_R (*((volatile uint32_t *)0x40037068)) +#define WTIMER1_PP_R (*((volatile uint32_t *)0x40037FC0)) + +//***************************************************************************** +// +// ADC registers (ADC0) +// +//***************************************************************************** +#define ADC0_ACTSS_R (*((volatile uint32_t *)0x40038000)) +#define ADC0_RIS_R (*((volatile uint32_t *)0x40038004)) +#define ADC0_IM_R (*((volatile uint32_t *)0x40038008)) +#define ADC0_ISC_R (*((volatile uint32_t *)0x4003800C)) +#define ADC0_OSTAT_R (*((volatile uint32_t *)0x40038010)) +#define ADC0_EMUX_R (*((volatile uint32_t *)0x40038014)) +#define ADC0_USTAT_R (*((volatile uint32_t *)0x40038018)) +#define ADC0_TSSEL_R (*((volatile uint32_t *)0x4003801C)) +#define ADC0_SSPRI_R (*((volatile uint32_t *)0x40038020)) +#define ADC0_SPC_R (*((volatile uint32_t *)0x40038024)) +#define ADC0_PSSI_R (*((volatile uint32_t *)0x40038028)) +#define ADC0_SAC_R (*((volatile uint32_t *)0x40038030)) +#define ADC0_DCISC_R (*((volatile uint32_t *)0x40038034)) +#define ADC0_CTL_R (*((volatile uint32_t *)0x40038038)) +#define ADC0_SSMUX0_R (*((volatile uint32_t *)0x40038040)) +#define ADC0_SSCTL0_R (*((volatile uint32_t *)0x40038044)) +#define ADC0_SSFIFO0_R (*((volatile uint32_t *)0x40038048)) +#define ADC0_SSFSTAT0_R (*((volatile uint32_t *)0x4003804C)) +#define ADC0_SSOP0_R (*((volatile uint32_t *)0x40038050)) +#define ADC0_SSDC0_R (*((volatile uint32_t *)0x40038054)) +#define ADC0_SSMUX1_R (*((volatile uint32_t *)0x40038060)) +#define ADC0_SSCTL1_R (*((volatile uint32_t *)0x40038064)) +#define ADC0_SSFIFO1_R (*((volatile uint32_t *)0x40038068)) +#define ADC0_SSFSTAT1_R (*((volatile uint32_t *)0x4003806C)) +#define ADC0_SSOP1_R (*((volatile uint32_t *)0x40038070)) +#define ADC0_SSDC1_R (*((volatile uint32_t *)0x40038074)) +#define ADC0_SSMUX2_R (*((volatile uint32_t *)0x40038080)) +#define ADC0_SSCTL2_R (*((volatile uint32_t *)0x40038084)) +#define ADC0_SSFIFO2_R (*((volatile uint32_t *)0x40038088)) +#define ADC0_SSFSTAT2_R (*((volatile uint32_t *)0x4003808C)) +#define ADC0_SSOP2_R (*((volatile uint32_t *)0x40038090)) +#define ADC0_SSDC2_R (*((volatile uint32_t *)0x40038094)) +#define ADC0_SSMUX3_R (*((volatile uint32_t *)0x400380A0)) +#define ADC0_SSCTL3_R (*((volatile uint32_t *)0x400380A4)) +#define ADC0_SSFIFO3_R (*((volatile uint32_t *)0x400380A8)) +#define ADC0_SSFSTAT3_R (*((volatile uint32_t *)0x400380AC)) +#define ADC0_SSOP3_R (*((volatile uint32_t *)0x400380B0)) +#define ADC0_SSDC3_R (*((volatile uint32_t *)0x400380B4)) +#define ADC0_DCRIC_R (*((volatile uint32_t *)0x40038D00)) +#define ADC0_DCCTL0_R (*((volatile uint32_t *)0x40038E00)) +#define ADC0_DCCTL1_R (*((volatile uint32_t *)0x40038E04)) +#define ADC0_DCCTL2_R (*((volatile uint32_t *)0x40038E08)) +#define ADC0_DCCTL3_R (*((volatile uint32_t *)0x40038E0C)) +#define ADC0_DCCTL4_R (*((volatile uint32_t *)0x40038E10)) +#define ADC0_DCCTL5_R (*((volatile uint32_t *)0x40038E14)) +#define ADC0_DCCTL6_R (*((volatile uint32_t *)0x40038E18)) +#define ADC0_DCCTL7_R (*((volatile uint32_t *)0x40038E1C)) +#define ADC0_DCCMP0_R (*((volatile uint32_t *)0x40038E40)) +#define ADC0_DCCMP1_R (*((volatile uint32_t *)0x40038E44)) +#define ADC0_DCCMP2_R (*((volatile uint32_t *)0x40038E48)) +#define ADC0_DCCMP3_R (*((volatile uint32_t *)0x40038E4C)) +#define ADC0_DCCMP4_R (*((volatile uint32_t *)0x40038E50)) +#define ADC0_DCCMP5_R (*((volatile uint32_t *)0x40038E54)) +#define ADC0_DCCMP6_R (*((volatile uint32_t *)0x40038E58)) +#define ADC0_DCCMP7_R (*((volatile uint32_t *)0x40038E5C)) +#define ADC0_PP_R (*((volatile uint32_t *)0x40038FC0)) +#define ADC0_PC_R (*((volatile uint32_t *)0x40038FC4)) +#define ADC0_CC_R (*((volatile uint32_t *)0x40038FC8)) + +//***************************************************************************** +// +// ADC registers (ADC1) +// +//***************************************************************************** +#define ADC1_ACTSS_R (*((volatile uint32_t *)0x40039000)) +#define ADC1_RIS_R (*((volatile uint32_t *)0x40039004)) +#define ADC1_IM_R (*((volatile uint32_t *)0x40039008)) +#define ADC1_ISC_R (*((volatile uint32_t *)0x4003900C)) +#define ADC1_OSTAT_R (*((volatile uint32_t *)0x40039010)) +#define ADC1_EMUX_R (*((volatile uint32_t *)0x40039014)) +#define ADC1_USTAT_R (*((volatile uint32_t *)0x40039018)) +#define ADC1_TSSEL_R (*((volatile uint32_t *)0x4003901C)) +#define ADC1_SSPRI_R (*((volatile uint32_t *)0x40039020)) +#define ADC1_SPC_R (*((volatile uint32_t *)0x40039024)) +#define ADC1_PSSI_R (*((volatile uint32_t *)0x40039028)) +#define ADC1_SAC_R (*((volatile uint32_t *)0x40039030)) +#define ADC1_DCISC_R (*((volatile uint32_t *)0x40039034)) +#define ADC1_CTL_R (*((volatile uint32_t *)0x40039038)) +#define ADC1_SSMUX0_R (*((volatile uint32_t *)0x40039040)) +#define ADC1_SSCTL0_R (*((volatile uint32_t *)0x40039044)) +#define ADC1_SSFIFO0_R (*((volatile uint32_t *)0x40039048)) +#define ADC1_SSFSTAT0_R (*((volatile uint32_t *)0x4003904C)) +#define ADC1_SSOP0_R (*((volatile uint32_t *)0x40039050)) +#define ADC1_SSDC0_R (*((volatile uint32_t *)0x40039054)) +#define ADC1_SSMUX1_R (*((volatile uint32_t *)0x40039060)) +#define ADC1_SSCTL1_R (*((volatile uint32_t *)0x40039064)) +#define ADC1_SSFIFO1_R (*((volatile uint32_t *)0x40039068)) +#define ADC1_SSFSTAT1_R (*((volatile uint32_t *)0x4003906C)) +#define ADC1_SSOP1_R (*((volatile uint32_t *)0x40039070)) +#define ADC1_SSDC1_R (*((volatile uint32_t *)0x40039074)) +#define ADC1_SSMUX2_R (*((volatile uint32_t *)0x40039080)) +#define ADC1_SSCTL2_R (*((volatile uint32_t *)0x40039084)) +#define ADC1_SSFIFO2_R (*((volatile uint32_t *)0x40039088)) +#define ADC1_SSFSTAT2_R (*((volatile uint32_t *)0x4003908C)) +#define ADC1_SSOP2_R (*((volatile uint32_t *)0x40039090)) +#define ADC1_SSDC2_R (*((volatile uint32_t *)0x40039094)) +#define ADC1_SSMUX3_R (*((volatile uint32_t *)0x400390A0)) +#define ADC1_SSCTL3_R (*((volatile uint32_t *)0x400390A4)) +#define ADC1_SSFIFO3_R (*((volatile uint32_t *)0x400390A8)) +#define ADC1_SSFSTAT3_R (*((volatile uint32_t *)0x400390AC)) +#define ADC1_SSOP3_R (*((volatile uint32_t *)0x400390B0)) +#define ADC1_SSDC3_R (*((volatile uint32_t *)0x400390B4)) +#define ADC1_DCRIC_R (*((volatile uint32_t *)0x40039D00)) +#define ADC1_DCCTL0_R (*((volatile uint32_t *)0x40039E00)) +#define ADC1_DCCTL1_R (*((volatile uint32_t *)0x40039E04)) +#define ADC1_DCCTL2_R (*((volatile uint32_t *)0x40039E08)) +#define ADC1_DCCTL3_R (*((volatile uint32_t *)0x40039E0C)) +#define ADC1_DCCTL4_R (*((volatile uint32_t *)0x40039E10)) +#define ADC1_DCCTL5_R (*((volatile uint32_t *)0x40039E14)) +#define ADC1_DCCTL6_R (*((volatile uint32_t *)0x40039E18)) +#define ADC1_DCCTL7_R (*((volatile uint32_t *)0x40039E1C)) +#define ADC1_DCCMP0_R (*((volatile uint32_t *)0x40039E40)) +#define ADC1_DCCMP1_R (*((volatile uint32_t *)0x40039E44)) +#define ADC1_DCCMP2_R (*((volatile uint32_t *)0x40039E48)) +#define ADC1_DCCMP3_R (*((volatile uint32_t *)0x40039E4C)) +#define ADC1_DCCMP4_R (*((volatile uint32_t *)0x40039E50)) +#define ADC1_DCCMP5_R (*((volatile uint32_t *)0x40039E54)) +#define ADC1_DCCMP6_R (*((volatile uint32_t *)0x40039E58)) +#define ADC1_DCCMP7_R (*((volatile uint32_t *)0x40039E5C)) +#define ADC1_PP_R (*((volatile uint32_t *)0x40039FC0)) +#define ADC1_PC_R (*((volatile uint32_t *)0x40039FC4)) +#define ADC1_CC_R (*((volatile uint32_t *)0x40039FC8)) + +//***************************************************************************** +// +// Comparator registers (COMP) +// +//***************************************************************************** +#define COMP_ACMIS_R (*((volatile uint32_t *)0x4003C000)) +#define COMP_ACRIS_R (*((volatile uint32_t *)0x4003C004)) +#define COMP_ACINTEN_R (*((volatile uint32_t *)0x4003C008)) +#define COMP_ACREFCTL_R (*((volatile uint32_t *)0x4003C010)) +#define COMP_ACSTAT0_R (*((volatile uint32_t *)0x4003C020)) +#define COMP_ACCTL0_R (*((volatile uint32_t *)0x4003C024)) +#define COMP_ACSTAT1_R (*((volatile uint32_t *)0x4003C040)) +#define COMP_ACCTL1_R (*((volatile uint32_t *)0x4003C044)) +#define COMP_PP_R (*((volatile uint32_t *)0x4003CFC0)) + +//***************************************************************************** +// +// CAN registers (CAN0) +// +//***************************************************************************** +#define CAN0_CTL_R (*((volatile uint32_t *)0x40040000)) +#define CAN0_STS_R (*((volatile uint32_t *)0x40040004)) +#define CAN0_ERR_R (*((volatile uint32_t *)0x40040008)) +#define CAN0_BIT_R (*((volatile uint32_t *)0x4004000C)) +#define CAN0_INT_R (*((volatile uint32_t *)0x40040010)) +#define CAN0_TST_R (*((volatile uint32_t *)0x40040014)) +#define CAN0_BRPE_R (*((volatile uint32_t *)0x40040018)) +#define CAN0_IF1CRQ_R (*((volatile uint32_t *)0x40040020)) +#define CAN0_IF1CMSK_R (*((volatile uint32_t *)0x40040024)) +#define CAN0_IF1MSK1_R (*((volatile uint32_t *)0x40040028)) +#define CAN0_IF1MSK2_R (*((volatile uint32_t *)0x4004002C)) +#define CAN0_IF1ARB1_R (*((volatile uint32_t *)0x40040030)) +#define CAN0_IF1ARB2_R (*((volatile uint32_t *)0x40040034)) +#define CAN0_IF1MCTL_R (*((volatile uint32_t *)0x40040038)) +#define CAN0_IF1DA1_R (*((volatile uint32_t *)0x4004003C)) +#define CAN0_IF1DA2_R (*((volatile uint32_t *)0x40040040)) +#define CAN0_IF1DB1_R (*((volatile uint32_t *)0x40040044)) +#define CAN0_IF1DB2_R (*((volatile uint32_t *)0x40040048)) +#define CAN0_IF2CRQ_R (*((volatile uint32_t *)0x40040080)) +#define CAN0_IF2CMSK_R (*((volatile uint32_t *)0x40040084)) +#define CAN0_IF2MSK1_R (*((volatile uint32_t *)0x40040088)) +#define CAN0_IF2MSK2_R (*((volatile uint32_t *)0x4004008C)) +#define CAN0_IF2ARB1_R (*((volatile uint32_t *)0x40040090)) +#define CAN0_IF2ARB2_R (*((volatile uint32_t *)0x40040094)) +#define CAN0_IF2MCTL_R (*((volatile uint32_t *)0x40040098)) +#define CAN0_IF2DA1_R (*((volatile uint32_t *)0x4004009C)) +#define CAN0_IF2DA2_R (*((volatile uint32_t *)0x400400A0)) +#define CAN0_IF2DB1_R (*((volatile uint32_t *)0x400400A4)) +#define CAN0_IF2DB2_R (*((volatile uint32_t *)0x400400A8)) +#define CAN0_TXRQ1_R (*((volatile uint32_t *)0x40040100)) +#define CAN0_TXRQ2_R (*((volatile uint32_t *)0x40040104)) +#define CAN0_NWDA1_R (*((volatile uint32_t *)0x40040120)) +#define CAN0_NWDA2_R (*((volatile uint32_t *)0x40040124)) +#define CAN0_MSG1INT_R (*((volatile uint32_t *)0x40040140)) +#define CAN0_MSG2INT_R (*((volatile uint32_t *)0x40040144)) +#define CAN0_MSG1VAL_R (*((volatile uint32_t *)0x40040160)) +#define CAN0_MSG2VAL_R (*((volatile uint32_t *)0x40040164)) + +//***************************************************************************** +// +// CAN registers (CAN1) +// +//***************************************************************************** +#define CAN1_CTL_R (*((volatile uint32_t *)0x40041000)) +#define CAN1_STS_R (*((volatile uint32_t *)0x40041004)) +#define CAN1_ERR_R (*((volatile uint32_t *)0x40041008)) +#define CAN1_BIT_R (*((volatile uint32_t *)0x4004100C)) +#define CAN1_INT_R (*((volatile uint32_t *)0x40041010)) +#define CAN1_TST_R (*((volatile uint32_t *)0x40041014)) +#define CAN1_BRPE_R (*((volatile uint32_t *)0x40041018)) +#define CAN1_IF1CRQ_R (*((volatile uint32_t *)0x40041020)) +#define CAN1_IF1CMSK_R (*((volatile uint32_t *)0x40041024)) +#define CAN1_IF1MSK1_R (*((volatile uint32_t *)0x40041028)) +#define CAN1_IF1MSK2_R (*((volatile uint32_t *)0x4004102C)) +#define CAN1_IF1ARB1_R (*((volatile uint32_t *)0x40041030)) +#define CAN1_IF1ARB2_R (*((volatile uint32_t *)0x40041034)) +#define CAN1_IF1MCTL_R (*((volatile uint32_t *)0x40041038)) +#define CAN1_IF1DA1_R (*((volatile uint32_t *)0x4004103C)) +#define CAN1_IF1DA2_R (*((volatile uint32_t *)0x40041040)) +#define CAN1_IF1DB1_R (*((volatile uint32_t *)0x40041044)) +#define CAN1_IF1DB2_R (*((volatile uint32_t *)0x40041048)) +#define CAN1_IF2CRQ_R (*((volatile uint32_t *)0x40041080)) +#define CAN1_IF2CMSK_R (*((volatile uint32_t *)0x40041084)) +#define CAN1_IF2MSK1_R (*((volatile uint32_t *)0x40041088)) +#define CAN1_IF2MSK2_R (*((volatile uint32_t *)0x4004108C)) +#define CAN1_IF2ARB1_R (*((volatile uint32_t *)0x40041090)) +#define CAN1_IF2ARB2_R (*((volatile uint32_t *)0x40041094)) +#define CAN1_IF2MCTL_R (*((volatile uint32_t *)0x40041098)) +#define CAN1_IF2DA1_R (*((volatile uint32_t *)0x4004109C)) +#define CAN1_IF2DA2_R (*((volatile uint32_t *)0x400410A0)) +#define CAN1_IF2DB1_R (*((volatile uint32_t *)0x400410A4)) +#define CAN1_IF2DB2_R (*((volatile uint32_t *)0x400410A8)) +#define CAN1_TXRQ1_R (*((volatile uint32_t *)0x40041100)) +#define CAN1_TXRQ2_R (*((volatile uint32_t *)0x40041104)) +#define CAN1_NWDA1_R (*((volatile uint32_t *)0x40041120)) +#define CAN1_NWDA2_R (*((volatile uint32_t *)0x40041124)) +#define CAN1_MSG1INT_R (*((volatile uint32_t *)0x40041140)) +#define CAN1_MSG2INT_R (*((volatile uint32_t *)0x40041144)) +#define CAN1_MSG1VAL_R (*((volatile uint32_t *)0x40041160)) +#define CAN1_MSG2VAL_R (*((volatile uint32_t *)0x40041164)) + +//***************************************************************************** +// +// Timer registers (WTIMER2) +// +//***************************************************************************** +#define WTIMER2_CFG_R (*((volatile uint32_t *)0x4004C000)) +#define WTIMER2_TAMR_R (*((volatile uint32_t *)0x4004C004)) +#define WTIMER2_TBMR_R (*((volatile uint32_t *)0x4004C008)) +#define WTIMER2_CTL_R (*((volatile uint32_t *)0x4004C00C)) +#define WTIMER2_SYNC_R (*((volatile uint32_t *)0x4004C010)) +#define WTIMER2_IMR_R (*((volatile uint32_t *)0x4004C018)) +#define WTIMER2_RIS_R (*((volatile uint32_t *)0x4004C01C)) +#define WTIMER2_MIS_R (*((volatile uint32_t *)0x4004C020)) +#define WTIMER2_ICR_R (*((volatile uint32_t *)0x4004C024)) +#define WTIMER2_TAILR_R (*((volatile uint32_t *)0x4004C028)) +#define WTIMER2_TBILR_R (*((volatile uint32_t *)0x4004C02C)) +#define WTIMER2_TAMATCHR_R (*((volatile uint32_t *)0x4004C030)) +#define WTIMER2_TBMATCHR_R (*((volatile uint32_t *)0x4004C034)) +#define WTIMER2_TAPR_R (*((volatile uint32_t *)0x4004C038)) +#define WTIMER2_TBPR_R (*((volatile uint32_t *)0x4004C03C)) +#define WTIMER2_TAPMR_R (*((volatile uint32_t *)0x4004C040)) +#define WTIMER2_TBPMR_R (*((volatile uint32_t *)0x4004C044)) +#define WTIMER2_TAR_R (*((volatile uint32_t *)0x4004C048)) +#define WTIMER2_TBR_R (*((volatile uint32_t *)0x4004C04C)) +#define WTIMER2_TAV_R (*((volatile uint32_t *)0x4004C050)) +#define WTIMER2_TBV_R (*((volatile uint32_t *)0x4004C054)) +#define WTIMER2_RTCPD_R (*((volatile uint32_t *)0x4004C058)) +#define WTIMER2_TAPS_R (*((volatile uint32_t *)0x4004C05C)) +#define WTIMER2_TBPS_R (*((volatile uint32_t *)0x4004C060)) +#define WTIMER2_TAPV_R (*((volatile uint32_t *)0x4004C064)) +#define WTIMER2_TBPV_R (*((volatile uint32_t *)0x4004C068)) +#define WTIMER2_PP_R (*((volatile uint32_t *)0x4004CFC0)) + +//***************************************************************************** +// +// Timer registers (WTIMER3) +// +//***************************************************************************** +#define WTIMER3_CFG_R (*((volatile uint32_t *)0x4004D000)) +#define WTIMER3_TAMR_R (*((volatile uint32_t *)0x4004D004)) +#define WTIMER3_TBMR_R (*((volatile uint32_t *)0x4004D008)) +#define WTIMER3_CTL_R (*((volatile uint32_t *)0x4004D00C)) +#define WTIMER3_SYNC_R (*((volatile uint32_t *)0x4004D010)) +#define WTIMER3_IMR_R (*((volatile uint32_t *)0x4004D018)) +#define WTIMER3_RIS_R (*((volatile uint32_t *)0x4004D01C)) +#define WTIMER3_MIS_R (*((volatile uint32_t *)0x4004D020)) +#define WTIMER3_ICR_R (*((volatile uint32_t *)0x4004D024)) +#define WTIMER3_TAILR_R (*((volatile uint32_t *)0x4004D028)) +#define WTIMER3_TBILR_R (*((volatile uint32_t *)0x4004D02C)) +#define WTIMER3_TAMATCHR_R (*((volatile uint32_t *)0x4004D030)) +#define WTIMER3_TBMATCHR_R (*((volatile uint32_t *)0x4004D034)) +#define WTIMER3_TAPR_R (*((volatile uint32_t *)0x4004D038)) +#define WTIMER3_TBPR_R (*((volatile uint32_t *)0x4004D03C)) +#define WTIMER3_TAPMR_R (*((volatile uint32_t *)0x4004D040)) +#define WTIMER3_TBPMR_R (*((volatile uint32_t *)0x4004D044)) +#define WTIMER3_TAR_R (*((volatile uint32_t *)0x4004D048)) +#define WTIMER3_TBR_R (*((volatile uint32_t *)0x4004D04C)) +#define WTIMER3_TAV_R (*((volatile uint32_t *)0x4004D050)) +#define WTIMER3_TBV_R (*((volatile uint32_t *)0x4004D054)) +#define WTIMER3_RTCPD_R (*((volatile uint32_t *)0x4004D058)) +#define WTIMER3_TAPS_R (*((volatile uint32_t *)0x4004D05C)) +#define WTIMER3_TBPS_R (*((volatile uint32_t *)0x4004D060)) +#define WTIMER3_TAPV_R (*((volatile uint32_t *)0x4004D064)) +#define WTIMER3_TBPV_R (*((volatile uint32_t *)0x4004D068)) +#define WTIMER3_PP_R (*((volatile uint32_t *)0x4004DFC0)) + +//***************************************************************************** +// +// Timer registers (WTIMER4) +// +//***************************************************************************** +#define WTIMER4_CFG_R (*((volatile uint32_t *)0x4004E000)) +#define WTIMER4_TAMR_R (*((volatile uint32_t *)0x4004E004)) +#define WTIMER4_TBMR_R (*((volatile uint32_t *)0x4004E008)) +#define WTIMER4_CTL_R (*((volatile uint32_t *)0x4004E00C)) +#define WTIMER4_SYNC_R (*((volatile uint32_t *)0x4004E010)) +#define WTIMER4_IMR_R (*((volatile uint32_t *)0x4004E018)) +#define WTIMER4_RIS_R (*((volatile uint32_t *)0x4004E01C)) +#define WTIMER4_MIS_R (*((volatile uint32_t *)0x4004E020)) +#define WTIMER4_ICR_R (*((volatile uint32_t *)0x4004E024)) +#define WTIMER4_TAILR_R (*((volatile uint32_t *)0x4004E028)) +#define WTIMER4_TBILR_R (*((volatile uint32_t *)0x4004E02C)) +#define WTIMER4_TAMATCHR_R (*((volatile uint32_t *)0x4004E030)) +#define WTIMER4_TBMATCHR_R (*((volatile uint32_t *)0x4004E034)) +#define WTIMER4_TAPR_R (*((volatile uint32_t *)0x4004E038)) +#define WTIMER4_TBPR_R (*((volatile uint32_t *)0x4004E03C)) +#define WTIMER4_TAPMR_R (*((volatile uint32_t *)0x4004E040)) +#define WTIMER4_TBPMR_R (*((volatile uint32_t *)0x4004E044)) +#define WTIMER4_TAR_R (*((volatile uint32_t *)0x4004E048)) +#define WTIMER4_TBR_R (*((volatile uint32_t *)0x4004E04C)) +#define WTIMER4_TAV_R (*((volatile uint32_t *)0x4004E050)) +#define WTIMER4_TBV_R (*((volatile uint32_t *)0x4004E054)) +#define WTIMER4_RTCPD_R (*((volatile uint32_t *)0x4004E058)) +#define WTIMER4_TAPS_R (*((volatile uint32_t *)0x4004E05C)) +#define WTIMER4_TBPS_R (*((volatile uint32_t *)0x4004E060)) +#define WTIMER4_TAPV_R (*((volatile uint32_t *)0x4004E064)) +#define WTIMER4_TBPV_R (*((volatile uint32_t *)0x4004E068)) +#define WTIMER4_PP_R (*((volatile uint32_t *)0x4004EFC0)) + +//***************************************************************************** +// +// Timer registers (WTIMER5) +// +//***************************************************************************** +#define WTIMER5_CFG_R (*((volatile uint32_t *)0x4004F000)) +#define WTIMER5_TAMR_R (*((volatile uint32_t *)0x4004F004)) +#define WTIMER5_TBMR_R (*((volatile uint32_t *)0x4004F008)) +#define WTIMER5_CTL_R (*((volatile uint32_t *)0x4004F00C)) +#define WTIMER5_SYNC_R (*((volatile uint32_t *)0x4004F010)) +#define WTIMER5_IMR_R (*((volatile uint32_t *)0x4004F018)) +#define WTIMER5_RIS_R (*((volatile uint32_t *)0x4004F01C)) +#define WTIMER5_MIS_R (*((volatile uint32_t *)0x4004F020)) +#define WTIMER5_ICR_R (*((volatile uint32_t *)0x4004F024)) +#define WTIMER5_TAILR_R (*((volatile uint32_t *)0x4004F028)) +#define WTIMER5_TBILR_R (*((volatile uint32_t *)0x4004F02C)) +#define WTIMER5_TAMATCHR_R (*((volatile uint32_t *)0x4004F030)) +#define WTIMER5_TBMATCHR_R (*((volatile uint32_t *)0x4004F034)) +#define WTIMER5_TAPR_R (*((volatile uint32_t *)0x4004F038)) +#define WTIMER5_TBPR_R (*((volatile uint32_t *)0x4004F03C)) +#define WTIMER5_TAPMR_R (*((volatile uint32_t *)0x4004F040)) +#define WTIMER5_TBPMR_R (*((volatile uint32_t *)0x4004F044)) +#define WTIMER5_TAR_R (*((volatile uint32_t *)0x4004F048)) +#define WTIMER5_TBR_R (*((volatile uint32_t *)0x4004F04C)) +#define WTIMER5_TAV_R (*((volatile uint32_t *)0x4004F050)) +#define WTIMER5_TBV_R (*((volatile uint32_t *)0x4004F054)) +#define WTIMER5_RTCPD_R (*((volatile uint32_t *)0x4004F058)) +#define WTIMER5_TAPS_R (*((volatile uint32_t *)0x4004F05C)) +#define WTIMER5_TBPS_R (*((volatile uint32_t *)0x4004F060)) +#define WTIMER5_TAPV_R (*((volatile uint32_t *)0x4004F064)) +#define WTIMER5_TBPV_R (*((volatile uint32_t *)0x4004F068)) +#define WTIMER5_PP_R (*((volatile uint32_t *)0x4004FFC0)) + +//***************************************************************************** +// +// Univeral Serial Bus registers (USB0) +// +//***************************************************************************** +#define USB0_FADDR_R (*((volatile uint8_t *)0x40050000)) +#define USB0_POWER_R (*((volatile uint8_t *)0x40050001)) +#define USB0_TXIS_R (*((volatile uint16_t *)0x40050002)) +#define USB0_RXIS_R (*((volatile uint16_t *)0x40050004)) +#define USB0_TXIE_R (*((volatile uint16_t *)0x40050006)) +#define USB0_RXIE_R (*((volatile uint16_t *)0x40050008)) +#define USB0_IS_R (*((volatile uint8_t *)0x4005000A)) +#define USB0_IE_R (*((volatile uint8_t *)0x4005000B)) +#define USB0_FRAME_R (*((volatile uint16_t *)0x4005000C)) +#define USB0_EPIDX_R (*((volatile uint8_t *)0x4005000E)) +#define USB0_TEST_R (*((volatile uint8_t *)0x4005000F)) +#define USB0_FIFO0_R (*((volatile uint32_t *)0x40050020)) +#define USB0_FIFO1_R (*((volatile uint32_t *)0x40050024)) +#define USB0_FIFO2_R (*((volatile uint32_t *)0x40050028)) +#define USB0_FIFO3_R (*((volatile uint32_t *)0x4005002C)) +#define USB0_FIFO4_R (*((volatile uint32_t *)0x40050030)) +#define USB0_FIFO5_R (*((volatile uint32_t *)0x40050034)) +#define USB0_FIFO6_R (*((volatile uint32_t *)0x40050038)) +#define USB0_FIFO7_R (*((volatile uint32_t *)0x4005003C)) +#define USB0_DEVCTL_R (*((volatile uint8_t *)0x40050060)) +#define USB0_TXFIFOSZ_R (*((volatile uint8_t *)0x40050062)) +#define USB0_RXFIFOSZ_R (*((volatile uint8_t *)0x40050063)) +#define USB0_TXFIFOADD_R (*((volatile uint16_t *)0x40050064)) +#define USB0_RXFIFOADD_R (*((volatile uint16_t *)0x40050066)) +#define USB0_CONTIM_R (*((volatile uint8_t *)0x4005007A)) +#define USB0_VPLEN_R (*((volatile uint8_t *)0x4005007B)) +#define USB0_FSEOF_R (*((volatile uint8_t *)0x4005007D)) +#define USB0_LSEOF_R (*((volatile uint8_t *)0x4005007E)) +#define USB0_TXFUNCADDR0_R (*((volatile uint8_t *)0x40050080)) +#define USB0_TXHUBADDR0_R (*((volatile uint8_t *)0x40050082)) +#define USB0_TXHUBPORT0_R (*((volatile uint8_t *)0x40050083)) +#define USB0_TXFUNCADDR1_R (*((volatile uint8_t *)0x40050088)) +#define USB0_TXHUBADDR1_R (*((volatile uint8_t *)0x4005008A)) +#define USB0_TXHUBPORT1_R (*((volatile uint8_t *)0x4005008B)) +#define USB0_RXFUNCADDR1_R (*((volatile uint8_t *)0x4005008C)) +#define USB0_RXHUBADDR1_R (*((volatile uint8_t *)0x4005008E)) +#define USB0_RXHUBPORT1_R (*((volatile uint8_t *)0x4005008F)) +#define USB0_TXFUNCADDR2_R (*((volatile uint8_t *)0x40050090)) +#define USB0_TXHUBADDR2_R (*((volatile uint8_t *)0x40050092)) +#define USB0_TXHUBPORT2_R (*((volatile uint8_t *)0x40050093)) +#define USB0_RXFUNCADDR2_R (*((volatile uint8_t *)0x40050094)) +#define USB0_RXHUBADDR2_R (*((volatile uint8_t *)0x40050096)) +#define USB0_RXHUBPORT2_R (*((volatile uint8_t *)0x40050097)) +#define USB0_TXFUNCADDR3_R (*((volatile uint8_t *)0x40050098)) +#define USB0_TXHUBADDR3_R (*((volatile uint8_t *)0x4005009A)) +#define USB0_TXHUBPORT3_R (*((volatile uint8_t *)0x4005009B)) +#define USB0_RXFUNCADDR3_R (*((volatile uint8_t *)0x4005009C)) +#define USB0_RXHUBADDR3_R (*((volatile uint8_t *)0x4005009E)) +#define USB0_RXHUBPORT3_R (*((volatile uint8_t *)0x4005009F)) +#define USB0_TXFUNCADDR4_R (*((volatile uint8_t *)0x400500A0)) +#define USB0_TXHUBADDR4_R (*((volatile uint8_t *)0x400500A2)) +#define USB0_TXHUBPORT4_R (*((volatile uint8_t *)0x400500A3)) +#define USB0_RXFUNCADDR4_R (*((volatile uint8_t *)0x400500A4)) +#define USB0_RXHUBADDR4_R (*((volatile uint8_t *)0x400500A6)) +#define USB0_RXHUBPORT4_R (*((volatile uint8_t *)0x400500A7)) +#define USB0_TXFUNCADDR5_R (*((volatile uint8_t *)0x400500A8)) +#define USB0_TXHUBADDR5_R (*((volatile uint8_t *)0x400500AA)) +#define USB0_TXHUBPORT5_R (*((volatile uint8_t *)0x400500AB)) +#define USB0_RXFUNCADDR5_R (*((volatile uint8_t *)0x400500AC)) +#define USB0_RXHUBADDR5_R (*((volatile uint8_t *)0x400500AE)) +#define USB0_RXHUBPORT5_R (*((volatile uint8_t *)0x400500AF)) +#define USB0_TXFUNCADDR6_R (*((volatile uint8_t *)0x400500B0)) +#define USB0_TXHUBADDR6_R (*((volatile uint8_t *)0x400500B2)) +#define USB0_TXHUBPORT6_R (*((volatile uint8_t *)0x400500B3)) +#define USB0_RXFUNCADDR6_R (*((volatile uint8_t *)0x400500B4)) +#define USB0_RXHUBADDR6_R (*((volatile uint8_t *)0x400500B6)) +#define USB0_RXHUBPORT6_R (*((volatile uint8_t *)0x400500B7)) +#define USB0_TXFUNCADDR7_R (*((volatile uint8_t *)0x400500B8)) +#define USB0_TXHUBADDR7_R (*((volatile uint8_t *)0x400500BA)) +#define USB0_TXHUBPORT7_R (*((volatile uint8_t *)0x400500BB)) +#define USB0_RXFUNCADDR7_R (*((volatile uint8_t *)0x400500BC)) +#define USB0_RXHUBADDR7_R (*((volatile uint8_t *)0x400500BE)) +#define USB0_RXHUBPORT7_R (*((volatile uint8_t *)0x400500BF)) +#define USB0_CSRL0_R (*((volatile uint8_t *)0x40050102)) +#define USB0_CSRH0_R (*((volatile uint8_t *)0x40050103)) +#define USB0_COUNT0_R (*((volatile uint8_t *)0x40050108)) +#define USB0_TYPE0_R (*((volatile uint8_t *)0x4005010A)) +#define USB0_NAKLMT_R (*((volatile uint8_t *)0x4005010B)) +#define USB0_TXMAXP1_R (*((volatile uint16_t *)0x40050110)) +#define USB0_TXCSRL1_R (*((volatile uint8_t *)0x40050112)) +#define USB0_TXCSRH1_R (*((volatile uint8_t *)0x40050113)) +#define USB0_RXMAXP1_R (*((volatile uint16_t *)0x40050114)) +#define USB0_RXCSRL1_R (*((volatile uint8_t *)0x40050116)) +#define USB0_RXCSRH1_R (*((volatile uint8_t *)0x40050117)) +#define USB0_RXCOUNT1_R (*((volatile uint16_t *)0x40050118)) +#define USB0_TXTYPE1_R (*((volatile uint8_t *)0x4005011A)) +#define USB0_TXINTERVAL1_R (*((volatile uint8_t *)0x4005011B)) +#define USB0_RXTYPE1_R (*((volatile uint8_t *)0x4005011C)) +#define USB0_RXINTERVAL1_R (*((volatile uint8_t *)0x4005011D)) +#define USB0_TXMAXP2_R (*((volatile uint16_t *)0x40050120)) +#define USB0_TXCSRL2_R (*((volatile uint8_t *)0x40050122)) +#define USB0_TXCSRH2_R (*((volatile uint8_t *)0x40050123)) +#define USB0_RXMAXP2_R (*((volatile uint16_t *)0x40050124)) +#define USB0_RXCSRL2_R (*((volatile uint8_t *)0x40050126)) +#define USB0_RXCSRH2_R (*((volatile uint8_t *)0x40050127)) +#define USB0_RXCOUNT2_R (*((volatile uint16_t *)0x40050128)) +#define USB0_TXTYPE2_R (*((volatile uint8_t *)0x4005012A)) +#define USB0_TXINTERVAL2_R (*((volatile uint8_t *)0x4005012B)) +#define USB0_RXTYPE2_R (*((volatile uint8_t *)0x4005012C)) +#define USB0_RXINTERVAL2_R (*((volatile uint8_t *)0x4005012D)) +#define USB0_TXMAXP3_R (*((volatile uint16_t *)0x40050130)) +#define USB0_TXCSRL3_R (*((volatile uint8_t *)0x40050132)) +#define USB0_TXCSRH3_R (*((volatile uint8_t *)0x40050133)) +#define USB0_RXMAXP3_R (*((volatile uint16_t *)0x40050134)) +#define USB0_RXCSRL3_R (*((volatile uint8_t *)0x40050136)) +#define USB0_RXCSRH3_R (*((volatile uint8_t *)0x40050137)) +#define USB0_RXCOUNT3_R (*((volatile uint16_t *)0x40050138)) +#define USB0_TXTYPE3_R (*((volatile uint8_t *)0x4005013A)) +#define USB0_TXINTERVAL3_R (*((volatile uint8_t *)0x4005013B)) +#define USB0_RXTYPE3_R (*((volatile uint8_t *)0x4005013C)) +#define USB0_RXINTERVAL3_R (*((volatile uint8_t *)0x4005013D)) +#define USB0_TXMAXP4_R (*((volatile uint16_t *)0x40050140)) +#define USB0_TXCSRL4_R (*((volatile uint8_t *)0x40050142)) +#define USB0_TXCSRH4_R (*((volatile uint8_t *)0x40050143)) +#define USB0_RXMAXP4_R (*((volatile uint16_t *)0x40050144)) +#define USB0_RXCSRL4_R (*((volatile uint8_t *)0x40050146)) +#define USB0_RXCSRH4_R (*((volatile uint8_t *)0x40050147)) +#define USB0_RXCOUNT4_R (*((volatile uint16_t *)0x40050148)) +#define USB0_TXTYPE4_R (*((volatile uint8_t *)0x4005014A)) +#define USB0_TXINTERVAL4_R (*((volatile uint8_t *)0x4005014B)) +#define USB0_RXTYPE4_R (*((volatile uint8_t *)0x4005014C)) +#define USB0_RXINTERVAL4_R (*((volatile uint8_t *)0x4005014D)) +#define USB0_TXMAXP5_R (*((volatile uint16_t *)0x40050150)) +#define USB0_TXCSRL5_R (*((volatile uint8_t *)0x40050152)) +#define USB0_TXCSRH5_R (*((volatile uint8_t *)0x40050153)) +#define USB0_RXMAXP5_R (*((volatile uint16_t *)0x40050154)) +#define USB0_RXCSRL5_R (*((volatile uint8_t *)0x40050156)) +#define USB0_RXCSRH5_R (*((volatile uint8_t *)0x40050157)) +#define USB0_RXCOUNT5_R (*((volatile uint16_t *)0x40050158)) +#define USB0_TXTYPE5_R (*((volatile uint8_t *)0x4005015A)) +#define USB0_TXINTERVAL5_R (*((volatile uint8_t *)0x4005015B)) +#define USB0_RXTYPE5_R (*((volatile uint8_t *)0x4005015C)) +#define USB0_RXINTERVAL5_R (*((volatile uint8_t *)0x4005015D)) +#define USB0_TXMAXP6_R (*((volatile uint16_t *)0x40050160)) +#define USB0_TXCSRL6_R (*((volatile uint8_t *)0x40050162)) +#define USB0_TXCSRH6_R (*((volatile uint8_t *)0x40050163)) +#define USB0_RXMAXP6_R (*((volatile uint16_t *)0x40050164)) +#define USB0_RXCSRL6_R (*((volatile uint8_t *)0x40050166)) +#define USB0_RXCSRH6_R (*((volatile uint8_t *)0x40050167)) +#define USB0_RXCOUNT6_R (*((volatile uint16_t *)0x40050168)) +#define USB0_TXTYPE6_R (*((volatile uint8_t *)0x4005016A)) +#define USB0_TXINTERVAL6_R (*((volatile uint8_t *)0x4005016B)) +#define USB0_RXTYPE6_R (*((volatile uint8_t *)0x4005016C)) +#define USB0_RXINTERVAL6_R (*((volatile uint8_t *)0x4005016D)) +#define USB0_TXMAXP7_R (*((volatile uint16_t *)0x40050170)) +#define USB0_TXCSRL7_R (*((volatile uint8_t *)0x40050172)) +#define USB0_TXCSRH7_R (*((volatile uint8_t *)0x40050173)) +#define USB0_RXMAXP7_R (*((volatile uint16_t *)0x40050174)) +#define USB0_RXCSRL7_R (*((volatile uint8_t *)0x40050176)) +#define USB0_RXCSRH7_R (*((volatile uint8_t *)0x40050177)) +#define USB0_RXCOUNT7_R (*((volatile uint16_t *)0x40050178)) +#define USB0_TXTYPE7_R (*((volatile uint8_t *)0x4005017A)) +#define USB0_TXINTERVAL7_R (*((volatile uint8_t *)0x4005017B)) +#define USB0_RXTYPE7_R (*((volatile uint8_t *)0x4005017C)) +#define USB0_RXINTERVAL7_R (*((volatile uint8_t *)0x4005017D)) +#define USB0_RQPKTCOUNT1_R (*((volatile uint16_t *)0x40050304)) +#define USB0_RQPKTCOUNT2_R (*((volatile uint16_t *)0x40050308)) +#define USB0_RQPKTCOUNT3_R (*((volatile uint16_t *)0x4005030C)) +#define USB0_RQPKTCOUNT4_R (*((volatile uint16_t *)0x40050310)) +#define USB0_RQPKTCOUNT5_R (*((volatile uint16_t *)0x40050314)) +#define USB0_RQPKTCOUNT6_R (*((volatile uint16_t *)0x40050318)) +#define USB0_RQPKTCOUNT7_R (*((volatile uint16_t *)0x4005031C)) +#define USB0_RXDPKTBUFDIS_R (*((volatile uint16_t *)0x40050340)) +#define USB0_TXDPKTBUFDIS_R (*((volatile uint16_t *)0x40050342)) +#define USB0_EPC_R (*((volatile uint32_t *)0x40050400)) +#define USB0_EPCRIS_R (*((volatile uint32_t *)0x40050404)) +#define USB0_EPCIM_R (*((volatile uint32_t *)0x40050408)) +#define USB0_EPCISC_R (*((volatile uint32_t *)0x4005040C)) +#define USB0_DRRIS_R (*((volatile uint32_t *)0x40050410)) +#define USB0_DRIM_R (*((volatile uint32_t *)0x40050414)) +#define USB0_DRISC_R (*((volatile uint32_t *)0x40050418)) +#define USB0_GPCS_R (*((volatile uint32_t *)0x4005041C)) +#define USB0_VDC_R (*((volatile uint32_t *)0x40050430)) +#define USB0_VDCRIS_R (*((volatile uint32_t *)0x40050434)) +#define USB0_VDCIM_R (*((volatile uint32_t *)0x40050438)) +#define USB0_VDCISC_R (*((volatile uint32_t *)0x4005043C)) +#define USB0_IDVRIS_R (*((volatile uint32_t *)0x40050444)) +#define USB0_IDVIM_R (*((volatile uint32_t *)0x40050448)) +#define USB0_IDVISC_R (*((volatile uint32_t *)0x4005044C)) +#define USB0_DMASEL_R (*((volatile uint32_t *)0x40050450)) +#define USB0_PP_R (*((volatile uint32_t *)0x40050FC0)) + +//***************************************************************************** +// +// GPIO registers (PORTA AHB) +// +//***************************************************************************** +#define GPIO_PORTA_AHB_DATA_BITS_R \ + ((volatile uint32_t *)0x40058000) +#define GPIO_PORTA_AHB_DATA_R (*((volatile uint32_t *)0x400583FC)) +#define GPIO_PORTA_AHB_DIR_R (*((volatile uint32_t *)0x40058400)) +#define GPIO_PORTA_AHB_IS_R (*((volatile uint32_t *)0x40058404)) +#define GPIO_PORTA_AHB_IBE_R (*((volatile uint32_t *)0x40058408)) +#define GPIO_PORTA_AHB_IEV_R (*((volatile uint32_t *)0x4005840C)) +#define GPIO_PORTA_AHB_IM_R (*((volatile uint32_t *)0x40058410)) +#define GPIO_PORTA_AHB_RIS_R (*((volatile uint32_t *)0x40058414)) +#define GPIO_PORTA_AHB_MIS_R (*((volatile uint32_t *)0x40058418)) +#define GPIO_PORTA_AHB_ICR_R (*((volatile uint32_t *)0x4005841C)) +#define GPIO_PORTA_AHB_AFSEL_R (*((volatile uint32_t *)0x40058420)) +#define GPIO_PORTA_AHB_DR2R_R (*((volatile uint32_t *)0x40058500)) +#define GPIO_PORTA_AHB_DR4R_R (*((volatile uint32_t *)0x40058504)) +#define GPIO_PORTA_AHB_DR8R_R (*((volatile uint32_t *)0x40058508)) +#define GPIO_PORTA_AHB_ODR_R (*((volatile uint32_t *)0x4005850C)) +#define GPIO_PORTA_AHB_PUR_R (*((volatile uint32_t *)0x40058510)) +#define GPIO_PORTA_AHB_PDR_R (*((volatile uint32_t *)0x40058514)) +#define GPIO_PORTA_AHB_SLR_R (*((volatile uint32_t *)0x40058518)) +#define GPIO_PORTA_AHB_DEN_R (*((volatile uint32_t *)0x4005851C)) +#define GPIO_PORTA_AHB_LOCK_R (*((volatile uint32_t *)0x40058520)) +#define GPIO_PORTA_AHB_CR_R (*((volatile uint32_t *)0x40058524)) +#define GPIO_PORTA_AHB_AMSEL_R (*((volatile uint32_t *)0x40058528)) +#define GPIO_PORTA_AHB_PCTL_R (*((volatile uint32_t *)0x4005852C)) +#define GPIO_PORTA_AHB_ADCCTL_R (*((volatile uint32_t *)0x40058530)) +#define GPIO_PORTA_AHB_DMACTL_R (*((volatile uint32_t *)0x40058534)) + +//***************************************************************************** +// +// GPIO registers (PORTB AHB) +// +//***************************************************************************** +#define GPIO_PORTB_AHB_DATA_BITS_R \ + ((volatile uint32_t *)0x40059000) +#define GPIO_PORTB_AHB_DATA_R (*((volatile uint32_t *)0x400593FC)) +#define GPIO_PORTB_AHB_DIR_R (*((volatile uint32_t *)0x40059400)) +#define GPIO_PORTB_AHB_IS_R (*((volatile uint32_t *)0x40059404)) +#define GPIO_PORTB_AHB_IBE_R (*((volatile uint32_t *)0x40059408)) +#define GPIO_PORTB_AHB_IEV_R (*((volatile uint32_t *)0x4005940C)) +#define GPIO_PORTB_AHB_IM_R (*((volatile uint32_t *)0x40059410)) +#define GPIO_PORTB_AHB_RIS_R (*((volatile uint32_t *)0x40059414)) +#define GPIO_PORTB_AHB_MIS_R (*((volatile uint32_t *)0x40059418)) +#define GPIO_PORTB_AHB_ICR_R (*((volatile uint32_t *)0x4005941C)) +#define GPIO_PORTB_AHB_AFSEL_R (*((volatile uint32_t *)0x40059420)) +#define GPIO_PORTB_AHB_DR2R_R (*((volatile uint32_t *)0x40059500)) +#define GPIO_PORTB_AHB_DR4R_R (*((volatile uint32_t *)0x40059504)) +#define GPIO_PORTB_AHB_DR8R_R (*((volatile uint32_t *)0x40059508)) +#define GPIO_PORTB_AHB_ODR_R (*((volatile uint32_t *)0x4005950C)) +#define GPIO_PORTB_AHB_PUR_R (*((volatile uint32_t *)0x40059510)) +#define GPIO_PORTB_AHB_PDR_R (*((volatile uint32_t *)0x40059514)) +#define GPIO_PORTB_AHB_SLR_R (*((volatile uint32_t *)0x40059518)) +#define GPIO_PORTB_AHB_DEN_R (*((volatile uint32_t *)0x4005951C)) +#define GPIO_PORTB_AHB_LOCK_R (*((volatile uint32_t *)0x40059520)) +#define GPIO_PORTB_AHB_CR_R (*((volatile uint32_t *)0x40059524)) +#define GPIO_PORTB_AHB_AMSEL_R (*((volatile uint32_t *)0x40059528)) +#define GPIO_PORTB_AHB_PCTL_R (*((volatile uint32_t *)0x4005952C)) +#define GPIO_PORTB_AHB_ADCCTL_R (*((volatile uint32_t *)0x40059530)) +#define GPIO_PORTB_AHB_DMACTL_R (*((volatile uint32_t *)0x40059534)) + +//***************************************************************************** +// +// GPIO registers (PORTC AHB) +// +//***************************************************************************** +#define GPIO_PORTC_AHB_DATA_BITS_R \ + ((volatile uint32_t *)0x4005A000) +#define GPIO_PORTC_AHB_DATA_R (*((volatile uint32_t *)0x4005A3FC)) +#define GPIO_PORTC_AHB_DIR_R (*((volatile uint32_t *)0x4005A400)) +#define GPIO_PORTC_AHB_IS_R (*((volatile uint32_t *)0x4005A404)) +#define GPIO_PORTC_AHB_IBE_R (*((volatile uint32_t *)0x4005A408)) +#define GPIO_PORTC_AHB_IEV_R (*((volatile uint32_t *)0x4005A40C)) +#define GPIO_PORTC_AHB_IM_R (*((volatile uint32_t *)0x4005A410)) +#define GPIO_PORTC_AHB_RIS_R (*((volatile uint32_t *)0x4005A414)) +#define GPIO_PORTC_AHB_MIS_R (*((volatile uint32_t *)0x4005A418)) +#define GPIO_PORTC_AHB_ICR_R (*((volatile uint32_t *)0x4005A41C)) +#define GPIO_PORTC_AHB_AFSEL_R (*((volatile uint32_t *)0x4005A420)) +#define GPIO_PORTC_AHB_DR2R_R (*((volatile uint32_t *)0x4005A500)) +#define GPIO_PORTC_AHB_DR4R_R (*((volatile uint32_t *)0x4005A504)) +#define GPIO_PORTC_AHB_DR8R_R (*((volatile uint32_t *)0x4005A508)) +#define GPIO_PORTC_AHB_ODR_R (*((volatile uint32_t *)0x4005A50C)) +#define GPIO_PORTC_AHB_PUR_R (*((volatile uint32_t *)0x4005A510)) +#define GPIO_PORTC_AHB_PDR_R (*((volatile uint32_t *)0x4005A514)) +#define GPIO_PORTC_AHB_SLR_R (*((volatile uint32_t *)0x4005A518)) +#define GPIO_PORTC_AHB_DEN_R (*((volatile uint32_t *)0x4005A51C)) +#define GPIO_PORTC_AHB_LOCK_R (*((volatile uint32_t *)0x4005A520)) +#define GPIO_PORTC_AHB_CR_R (*((volatile uint32_t *)0x4005A524)) +#define GPIO_PORTC_AHB_AMSEL_R (*((volatile uint32_t *)0x4005A528)) +#define GPIO_PORTC_AHB_PCTL_R (*((volatile uint32_t *)0x4005A52C)) +#define GPIO_PORTC_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005A530)) +#define GPIO_PORTC_AHB_DMACTL_R (*((volatile uint32_t *)0x4005A534)) + +//***************************************************************************** +// +// GPIO registers (PORTD AHB) +// +//***************************************************************************** +#define GPIO_PORTD_AHB_DATA_BITS_R \ + ((volatile uint32_t *)0x4005B000) +#define GPIO_PORTD_AHB_DATA_R (*((volatile uint32_t *)0x4005B3FC)) +#define GPIO_PORTD_AHB_DIR_R (*((volatile uint32_t *)0x4005B400)) +#define GPIO_PORTD_AHB_IS_R (*((volatile uint32_t *)0x4005B404)) +#define GPIO_PORTD_AHB_IBE_R (*((volatile uint32_t *)0x4005B408)) +#define GPIO_PORTD_AHB_IEV_R (*((volatile uint32_t *)0x4005B40C)) +#define GPIO_PORTD_AHB_IM_R (*((volatile uint32_t *)0x4005B410)) +#define GPIO_PORTD_AHB_RIS_R (*((volatile uint32_t *)0x4005B414)) +#define GPIO_PORTD_AHB_MIS_R (*((volatile uint32_t *)0x4005B418)) +#define GPIO_PORTD_AHB_ICR_R (*((volatile uint32_t *)0x4005B41C)) +#define GPIO_PORTD_AHB_AFSEL_R (*((volatile uint32_t *)0x4005B420)) +#define GPIO_PORTD_AHB_DR2R_R (*((volatile uint32_t *)0x4005B500)) +#define GPIO_PORTD_AHB_DR4R_R (*((volatile uint32_t *)0x4005B504)) +#define GPIO_PORTD_AHB_DR8R_R (*((volatile uint32_t *)0x4005B508)) +#define GPIO_PORTD_AHB_ODR_R (*((volatile uint32_t *)0x4005B50C)) +#define GPIO_PORTD_AHB_PUR_R (*((volatile uint32_t *)0x4005B510)) +#define GPIO_PORTD_AHB_PDR_R (*((volatile uint32_t *)0x4005B514)) +#define GPIO_PORTD_AHB_SLR_R (*((volatile uint32_t *)0x4005B518)) +#define GPIO_PORTD_AHB_DEN_R (*((volatile uint32_t *)0x4005B51C)) +#define GPIO_PORTD_AHB_LOCK_R (*((volatile uint32_t *)0x4005B520)) +#define GPIO_PORTD_AHB_CR_R (*((volatile uint32_t *)0x4005B524)) +#define GPIO_PORTD_AHB_AMSEL_R (*((volatile uint32_t *)0x4005B528)) +#define GPIO_PORTD_AHB_PCTL_R (*((volatile uint32_t *)0x4005B52C)) +#define GPIO_PORTD_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005B530)) +#define GPIO_PORTD_AHB_DMACTL_R (*((volatile uint32_t *)0x4005B534)) + +//***************************************************************************** +// +// GPIO registers (PORTE AHB) +// +//***************************************************************************** +#define GPIO_PORTE_AHB_DATA_BITS_R \ + ((volatile uint32_t *)0x4005C000) +#define GPIO_PORTE_AHB_DATA_R (*((volatile uint32_t *)0x4005C3FC)) +#define GPIO_PORTE_AHB_DIR_R (*((volatile uint32_t *)0x4005C400)) +#define GPIO_PORTE_AHB_IS_R (*((volatile uint32_t *)0x4005C404)) +#define GPIO_PORTE_AHB_IBE_R (*((volatile uint32_t *)0x4005C408)) +#define GPIO_PORTE_AHB_IEV_R (*((volatile uint32_t *)0x4005C40C)) +#define GPIO_PORTE_AHB_IM_R (*((volatile uint32_t *)0x4005C410)) +#define GPIO_PORTE_AHB_RIS_R (*((volatile uint32_t *)0x4005C414)) +#define GPIO_PORTE_AHB_MIS_R (*((volatile uint32_t *)0x4005C418)) +#define GPIO_PORTE_AHB_ICR_R (*((volatile uint32_t *)0x4005C41C)) +#define GPIO_PORTE_AHB_AFSEL_R (*((volatile uint32_t *)0x4005C420)) +#define GPIO_PORTE_AHB_DR2R_R (*((volatile uint32_t *)0x4005C500)) +#define GPIO_PORTE_AHB_DR4R_R (*((volatile uint32_t *)0x4005C504)) +#define GPIO_PORTE_AHB_DR8R_R (*((volatile uint32_t *)0x4005C508)) +#define GPIO_PORTE_AHB_ODR_R (*((volatile uint32_t *)0x4005C50C)) +#define GPIO_PORTE_AHB_PUR_R (*((volatile uint32_t *)0x4005C510)) +#define GPIO_PORTE_AHB_PDR_R (*((volatile uint32_t *)0x4005C514)) +#define GPIO_PORTE_AHB_SLR_R (*((volatile uint32_t *)0x4005C518)) +#define GPIO_PORTE_AHB_DEN_R (*((volatile uint32_t *)0x4005C51C)) +#define GPIO_PORTE_AHB_LOCK_R (*((volatile uint32_t *)0x4005C520)) +#define GPIO_PORTE_AHB_CR_R (*((volatile uint32_t *)0x4005C524)) +#define GPIO_PORTE_AHB_AMSEL_R (*((volatile uint32_t *)0x4005C528)) +#define GPIO_PORTE_AHB_PCTL_R (*((volatile uint32_t *)0x4005C52C)) +#define GPIO_PORTE_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005C530)) +#define GPIO_PORTE_AHB_DMACTL_R (*((volatile uint32_t *)0x4005C534)) + +//***************************************************************************** +// +// GPIO registers (PORTF AHB) +// +//***************************************************************************** +#define GPIO_PORTF_AHB_DATA_BITS_R \ + ((volatile uint32_t *)0x4005D000) +#define GPIO_PORTF_AHB_DATA_R (*((volatile uint32_t *)0x4005D3FC)) +#define GPIO_PORTF_AHB_DIR_R (*((volatile uint32_t *)0x4005D400)) +#define GPIO_PORTF_AHB_IS_R (*((volatile uint32_t *)0x4005D404)) +#define GPIO_PORTF_AHB_IBE_R (*((volatile uint32_t *)0x4005D408)) +#define GPIO_PORTF_AHB_IEV_R (*((volatile uint32_t *)0x4005D40C)) +#define GPIO_PORTF_AHB_IM_R (*((volatile uint32_t *)0x4005D410)) +#define GPIO_PORTF_AHB_RIS_R (*((volatile uint32_t *)0x4005D414)) +#define GPIO_PORTF_AHB_MIS_R (*((volatile uint32_t *)0x4005D418)) +#define GPIO_PORTF_AHB_ICR_R (*((volatile uint32_t *)0x4005D41C)) +#define GPIO_PORTF_AHB_AFSEL_R (*((volatile uint32_t *)0x4005D420)) +#define GPIO_PORTF_AHB_DR2R_R (*((volatile uint32_t *)0x4005D500)) +#define GPIO_PORTF_AHB_DR4R_R (*((volatile uint32_t *)0x4005D504)) +#define GPIO_PORTF_AHB_DR8R_R (*((volatile uint32_t *)0x4005D508)) +#define GPIO_PORTF_AHB_ODR_R (*((volatile uint32_t *)0x4005D50C)) +#define GPIO_PORTF_AHB_PUR_R (*((volatile uint32_t *)0x4005D510)) +#define GPIO_PORTF_AHB_PDR_R (*((volatile uint32_t *)0x4005D514)) +#define GPIO_PORTF_AHB_SLR_R (*((volatile uint32_t *)0x4005D518)) +#define GPIO_PORTF_AHB_DEN_R (*((volatile uint32_t *)0x4005D51C)) +#define GPIO_PORTF_AHB_LOCK_R (*((volatile uint32_t *)0x4005D520)) +#define GPIO_PORTF_AHB_CR_R (*((volatile uint32_t *)0x4005D524)) +#define GPIO_PORTF_AHB_AMSEL_R (*((volatile uint32_t *)0x4005D528)) +#define GPIO_PORTF_AHB_PCTL_R (*((volatile uint32_t *)0x4005D52C)) +#define GPIO_PORTF_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005D530)) +#define GPIO_PORTF_AHB_DMACTL_R (*((volatile uint32_t *)0x4005D534)) + +//***************************************************************************** +// +// EEPROM registers (EEPROM) +// +//***************************************************************************** +#define EEPROM_EESIZE_R (*((volatile uint32_t *)0x400AF000)) +#define EEPROM_EEBLOCK_R (*((volatile uint32_t *)0x400AF004)) +#define EEPROM_EEOFFSET_R (*((volatile uint32_t *)0x400AF008)) +#define EEPROM_EERDWR_R (*((volatile uint32_t *)0x400AF010)) +#define EEPROM_EERDWRINC_R (*((volatile uint32_t *)0x400AF014)) +#define EEPROM_EEDONE_R (*((volatile uint32_t *)0x400AF018)) +#define EEPROM_EESUPP_R (*((volatile uint32_t *)0x400AF01C)) +#define EEPROM_EEUNLOCK_R (*((volatile uint32_t *)0x400AF020)) +#define EEPROM_EEPROT_R (*((volatile uint32_t *)0x400AF030)) +#define EEPROM_EEPASS0_R (*((volatile uint32_t *)0x400AF034)) +#define EEPROM_EEPASS1_R (*((volatile uint32_t *)0x400AF038)) +#define EEPROM_EEPASS2_R (*((volatile uint32_t *)0x400AF03C)) +#define EEPROM_EEINT_R (*((volatile uint32_t *)0x400AF040)) +#define EEPROM_EEHIDE_R (*((volatile uint32_t *)0x400AF050)) +#define EEPROM_EEDBGME_R (*((volatile uint32_t *)0x400AF080)) +#define EEPROM_PP_R (*((volatile uint32_t *)0x400AFFC0)) + +//***************************************************************************** +// +// System Exception Module registers (SYSEXC) +// +//***************************************************************************** +#define SYSEXC_RIS_R (*((volatile uint32_t *)0x400F9000)) +#define SYSEXC_IM_R (*((volatile uint32_t *)0x400F9004)) +#define SYSEXC_MIS_R (*((volatile uint32_t *)0x400F9008)) +#define SYSEXC_IC_R (*((volatile uint32_t *)0x400F900C)) + +//***************************************************************************** +// +// Hibernation module registers (HIB) +// +//***************************************************************************** +#define HIB_RTCC_R (*((volatile uint32_t *)0x400FC000)) +#define HIB_RTCM0_R (*((volatile uint32_t *)0x400FC004)) +#define HIB_RTCLD_R (*((volatile uint32_t *)0x400FC00C)) +#define HIB_CTL_R (*((volatile uint32_t *)0x400FC010)) +#define HIB_IM_R (*((volatile uint32_t *)0x400FC014)) +#define HIB_RIS_R (*((volatile uint32_t *)0x400FC018)) +#define HIB_MIS_R (*((volatile uint32_t *)0x400FC01C)) +#define HIB_IC_R (*((volatile uint32_t *)0x400FC020)) +#define HIB_RTCT_R (*((volatile uint32_t *)0x400FC024)) +#define HIB_RTCSS_R (*((volatile uint32_t *)0x400FC028)) +#define HIB_DATA_R (*((volatile uint32_t *)0x400FC030)) + +//***************************************************************************** +// +// FLASH registers (FLASH CTRL) +// +//***************************************************************************** +#define FLASH_FMA_R (*((volatile uint32_t *)0x400FD000)) +#define FLASH_FMD_R (*((volatile uint32_t *)0x400FD004)) +#define FLASH_FMC_R (*((volatile uint32_t *)0x400FD008)) +#define FLASH_FCRIS_R (*((volatile uint32_t *)0x400FD00C)) +#define FLASH_FCIM_R (*((volatile uint32_t *)0x400FD010)) +#define FLASH_FCMISC_R (*((volatile uint32_t *)0x400FD014)) +#define FLASH_FMC2_R (*((volatile uint32_t *)0x400FD020)) +#define FLASH_FWBVAL_R (*((volatile uint32_t *)0x400FD030)) +#define FLASH_FWBN_R (*((volatile uint32_t *)0x400FD100)) +#define FLASH_FSIZE_R (*((volatile uint32_t *)0x400FDFC0)) +#define FLASH_SSIZE_R (*((volatile uint32_t *)0x400FDFC4)) +#define FLASH_ROMSWMAP_R (*((volatile uint32_t *)0x400FDFCC)) +#define FLASH_RMCTL_R (*((volatile uint32_t *)0x400FE0F0)) +#define FLASH_BOOTCFG_R (*((volatile uint32_t *)0x400FE1D0)) +#define FLASH_USERREG0_R (*((volatile uint32_t *)0x400FE1E0)) +#define FLASH_USERREG1_R (*((volatile uint32_t *)0x400FE1E4)) +#define FLASH_USERREG2_R (*((volatile uint32_t *)0x400FE1E8)) +#define FLASH_USERREG3_R (*((volatile uint32_t *)0x400FE1EC)) +#define FLASH_FMPRE0_R (*((volatile uint32_t *)0x400FE200)) +#define FLASH_FMPRE1_R (*((volatile uint32_t *)0x400FE204)) +#define FLASH_FMPRE2_R (*((volatile uint32_t *)0x400FE208)) +#define FLASH_FMPRE3_R (*((volatile uint32_t *)0x400FE20C)) +#define FLASH_FMPPE0_R (*((volatile uint32_t *)0x400FE400)) +#define FLASH_FMPPE1_R (*((volatile uint32_t *)0x400FE404)) +#define FLASH_FMPPE2_R (*((volatile uint32_t *)0x400FE408)) +#define FLASH_FMPPE3_R (*((volatile uint32_t *)0x400FE40C)) + +//***************************************************************************** +// +// System Control registers (SYSCTL) +// +//***************************************************************************** +#define SYSCTL_DID0_R (*((volatile uint32_t *)0x400FE000)) +#define SYSCTL_DID1_R (*((volatile uint32_t *)0x400FE004)) +#define SYSCTL_DC0_R (*((volatile uint32_t *)0x400FE008)) +#define SYSCTL_DC1_R (*((volatile uint32_t *)0x400FE010)) +#define SYSCTL_DC2_R (*((volatile uint32_t *)0x400FE014)) +#define SYSCTL_DC3_R (*((volatile uint32_t *)0x400FE018)) +#define SYSCTL_DC4_R (*((volatile uint32_t *)0x400FE01C)) +#define SYSCTL_DC5_R (*((volatile uint32_t *)0x400FE020)) +#define SYSCTL_DC6_R (*((volatile uint32_t *)0x400FE024)) +#define SYSCTL_DC7_R (*((volatile uint32_t *)0x400FE028)) +#define SYSCTL_DC8_R (*((volatile uint32_t *)0x400FE02C)) +#define SYSCTL_PBORCTL_R (*((volatile uint32_t *)0x400FE030)) +#define SYSCTL_SRCR0_R (*((volatile uint32_t *)0x400FE040)) +#define SYSCTL_SRCR1_R (*((volatile uint32_t *)0x400FE044)) +#define SYSCTL_SRCR2_R (*((volatile uint32_t *)0x400FE048)) +#define SYSCTL_RIS_R (*((volatile uint32_t *)0x400FE050)) +#define SYSCTL_IMC_R (*((volatile uint32_t *)0x400FE054)) +#define SYSCTL_MISC_R (*((volatile uint32_t *)0x400FE058)) +#define SYSCTL_RESC_R (*((volatile uint32_t *)0x400FE05C)) +#define SYSCTL_RCC_R (*((volatile uint32_t *)0x400FE060)) +#define SYSCTL_GPIOHBCTL_R (*((volatile uint32_t *)0x400FE06C)) +#define SYSCTL_RCC2_R (*((volatile uint32_t *)0x400FE070)) +#define SYSCTL_MOSCCTL_R (*((volatile uint32_t *)0x400FE07C)) +#define SYSCTL_RCGC0_R (*((volatile uint32_t *)0x400FE100)) +#define SYSCTL_RCGC1_R (*((volatile uint32_t *)0x400FE104)) +#define SYSCTL_RCGC2_R (*((volatile uint32_t *)0x400FE108)) +#define SYSCTL_SCGC0_R (*((volatile uint32_t *)0x400FE110)) +#define SYSCTL_SCGC1_R (*((volatile uint32_t *)0x400FE114)) +#define SYSCTL_SCGC2_R (*((volatile uint32_t *)0x400FE118)) +#define SYSCTL_DCGC0_R (*((volatile uint32_t *)0x400FE120)) +#define SYSCTL_DCGC1_R (*((volatile uint32_t *)0x400FE124)) +#define SYSCTL_DCGC2_R (*((volatile uint32_t *)0x400FE128)) +#define SYSCTL_DSLPCLKCFG_R (*((volatile uint32_t *)0x400FE144)) +#define SYSCTL_SYSPROP_R (*((volatile uint32_t *)0x400FE14C)) +#define SYSCTL_PIOSCCAL_R (*((volatile uint32_t *)0x400FE150)) +#define SYSCTL_PIOSCSTAT_R (*((volatile uint32_t *)0x400FE154)) +#define SYSCTL_PLLFREQ0_R (*((volatile uint32_t *)0x400FE160)) +#define SYSCTL_PLLFREQ1_R (*((volatile uint32_t *)0x400FE164)) +#define SYSCTL_PLLSTAT_R (*((volatile uint32_t *)0x400FE168)) +#define SYSCTL_SLPPWRCFG_R (*((volatile uint32_t *)0x400FE188)) +#define SYSCTL_DSLPPWRCFG_R (*((volatile uint32_t *)0x400FE18C)) +#define SYSCTL_DC9_R (*((volatile uint32_t *)0x400FE190)) +#define SYSCTL_NVMSTAT_R (*((volatile uint32_t *)0x400FE1A0)) +#define SYSCTL_LDOSPCTL_R (*((volatile uint32_t *)0x400FE1B4)) +#define SYSCTL_LDODPCTL_R (*((volatile uint32_t *)0x400FE1BC)) +#define SYSCTL_PPWD_R (*((volatile uint32_t *)0x400FE300)) +#define SYSCTL_PPTIMER_R (*((volatile uint32_t *)0x400FE304)) +#define SYSCTL_PPGPIO_R (*((volatile uint32_t *)0x400FE308)) +#define SYSCTL_PPDMA_R (*((volatile uint32_t *)0x400FE30C)) +#define SYSCTL_PPHIB_R (*((volatile uint32_t *)0x400FE314)) +#define SYSCTL_PPUART_R (*((volatile uint32_t *)0x400FE318)) +#define SYSCTL_PPSSI_R (*((volatile uint32_t *)0x400FE31C)) +#define SYSCTL_PPI2C_R (*((volatile uint32_t *)0x400FE320)) +#define SYSCTL_PPUSB_R (*((volatile uint32_t *)0x400FE328)) +#define SYSCTL_PPCAN_R (*((volatile uint32_t *)0x400FE334)) +#define SYSCTL_PPADC_R (*((volatile uint32_t *)0x400FE338)) +#define SYSCTL_PPACMP_R (*((volatile uint32_t *)0x400FE33C)) +#define SYSCTL_PPPWM_R (*((volatile uint32_t *)0x400FE340)) +#define SYSCTL_PPQEI_R (*((volatile uint32_t *)0x400FE344)) +#define SYSCTL_PPEEPROM_R (*((volatile uint32_t *)0x400FE358)) +#define SYSCTL_PPWTIMER_R (*((volatile uint32_t *)0x400FE35C)) +#define SYSCTL_SRWD_R (*((volatile uint32_t *)0x400FE500)) +#define SYSCTL_SRTIMER_R (*((volatile uint32_t *)0x400FE504)) +#define SYSCTL_SRGPIO_R (*((volatile uint32_t *)0x400FE508)) +#define SYSCTL_SRDMA_R (*((volatile uint32_t *)0x400FE50C)) +#define SYSCTL_SRHIB_R (*((volatile uint32_t *)0x400FE514)) +#define SYSCTL_SRUART_R (*((volatile uint32_t *)0x400FE518)) +#define SYSCTL_SRSSI_R (*((volatile uint32_t *)0x400FE51C)) +#define SYSCTL_SRI2C_R (*((volatile uint32_t *)0x400FE520)) +#define SYSCTL_SRUSB_R (*((volatile uint32_t *)0x400FE528)) +#define SYSCTL_SRCAN_R (*((volatile uint32_t *)0x400FE534)) +#define SYSCTL_SRADC_R (*((volatile uint32_t *)0x400FE538)) +#define SYSCTL_SRACMP_R (*((volatile uint32_t *)0x400FE53C)) +#define SYSCTL_SRPWM_R (*((volatile uint32_t *)0x400FE540)) +#define SYSCTL_SRQEI_R (*((volatile uint32_t *)0x400FE544)) +#define SYSCTL_SREEPROM_R (*((volatile uint32_t *)0x400FE558)) +#define SYSCTL_SRWTIMER_R (*((volatile uint32_t *)0x400FE55C)) +#define SYSCTL_RCGCWD_R (*((volatile uint32_t *)0x400FE600)) +#define SYSCTL_RCGCTIMER_R (*((volatile uint32_t *)0x400FE604)) +#define SYSCTL_RCGCGPIO_R (*((volatile uint32_t *)0x400FE608)) +#define SYSCTL_RCGCDMA_R (*((volatile uint32_t *)0x400FE60C)) +#define SYSCTL_RCGCHIB_R (*((volatile uint32_t *)0x400FE614)) +#define SYSCTL_RCGCUART_R (*((volatile uint32_t *)0x400FE618)) +#define SYSCTL_RCGCSSI_R (*((volatile uint32_t *)0x400FE61C)) +#define SYSCTL_RCGCI2C_R (*((volatile uint32_t *)0x400FE620)) +#define SYSCTL_RCGCUSB_R (*((volatile uint32_t *)0x400FE628)) +#define SYSCTL_RCGCCAN_R (*((volatile uint32_t *)0x400FE634)) +#define SYSCTL_RCGCADC_R (*((volatile uint32_t *)0x400FE638)) +#define SYSCTL_RCGCACMP_R (*((volatile uint32_t *)0x400FE63C)) +#define SYSCTL_RCGCPWM_R (*((volatile uint32_t *)0x400FE640)) +#define SYSCTL_RCGCQEI_R (*((volatile uint32_t *)0x400FE644)) +#define SYSCTL_RCGCEEPROM_R (*((volatile uint32_t *)0x400FE658)) +#define SYSCTL_RCGCWTIMER_R (*((volatile uint32_t *)0x400FE65C)) +#define SYSCTL_SCGCWD_R (*((volatile uint32_t *)0x400FE700)) +#define SYSCTL_SCGCTIMER_R (*((volatile uint32_t *)0x400FE704)) +#define SYSCTL_SCGCGPIO_R (*((volatile uint32_t *)0x400FE708)) +#define SYSCTL_SCGCDMA_R (*((volatile uint32_t *)0x400FE70C)) +#define SYSCTL_SCGCHIB_R (*((volatile uint32_t *)0x400FE714)) +#define SYSCTL_SCGCUART_R (*((volatile uint32_t *)0x400FE718)) +#define SYSCTL_SCGCSSI_R (*((volatile uint32_t *)0x400FE71C)) +#define SYSCTL_SCGCI2C_R (*((volatile uint32_t *)0x400FE720)) +#define SYSCTL_SCGCUSB_R (*((volatile uint32_t *)0x400FE728)) +#define SYSCTL_SCGCCAN_R (*((volatile uint32_t *)0x400FE734)) +#define SYSCTL_SCGCADC_R (*((volatile uint32_t *)0x400FE738)) +#define SYSCTL_SCGCACMP_R (*((volatile uint32_t *)0x400FE73C)) +#define SYSCTL_SCGCPWM_R (*((volatile uint32_t *)0x400FE740)) +#define SYSCTL_SCGCQEI_R (*((volatile uint32_t *)0x400FE744)) +#define SYSCTL_SCGCEEPROM_R (*((volatile uint32_t *)0x400FE758)) +#define SYSCTL_SCGCWTIMER_R (*((volatile uint32_t *)0x400FE75C)) +#define SYSCTL_DCGCWD_R (*((volatile uint32_t *)0x400FE800)) +#define SYSCTL_DCGCTIMER_R (*((volatile uint32_t *)0x400FE804)) +#define SYSCTL_DCGCGPIO_R (*((volatile uint32_t *)0x400FE808)) +#define SYSCTL_DCGCDMA_R (*((volatile uint32_t *)0x400FE80C)) +#define SYSCTL_DCGCHIB_R (*((volatile uint32_t *)0x400FE814)) +#define SYSCTL_DCGCUART_R (*((volatile uint32_t *)0x400FE818)) +#define SYSCTL_DCGCSSI_R (*((volatile uint32_t *)0x400FE81C)) +#define SYSCTL_DCGCI2C_R (*((volatile uint32_t *)0x400FE820)) +#define SYSCTL_DCGCUSB_R (*((volatile uint32_t *)0x400FE828)) +#define SYSCTL_DCGCCAN_R (*((volatile uint32_t *)0x400FE834)) +#define SYSCTL_DCGCADC_R (*((volatile uint32_t *)0x400FE838)) +#define SYSCTL_DCGCACMP_R (*((volatile uint32_t *)0x400FE83C)) +#define SYSCTL_DCGCPWM_R (*((volatile uint32_t *)0x400FE840)) +#define SYSCTL_DCGCQEI_R (*((volatile uint32_t *)0x400FE844)) +#define SYSCTL_DCGCEEPROM_R (*((volatile uint32_t *)0x400FE858)) +#define SYSCTL_DCGCWTIMER_R (*((volatile uint32_t *)0x400FE85C)) +#define SYSCTL_PRWD_R (*((volatile uint32_t *)0x400FEA00)) +#define SYSCTL_PRTIMER_R (*((volatile uint32_t *)0x400FEA04)) +#define SYSCTL_PRGPIO_R (*((volatile uint32_t *)0x400FEA08)) +#define SYSCTL_PRDMA_R (*((volatile uint32_t *)0x400FEA0C)) +#define SYSCTL_PRHIB_R (*((volatile uint32_t *)0x400FEA14)) +#define SYSCTL_PRUART_R (*((volatile uint32_t *)0x400FEA18)) +#define SYSCTL_PRSSI_R (*((volatile uint32_t *)0x400FEA1C)) +#define SYSCTL_PRI2C_R (*((volatile uint32_t *)0x400FEA20)) +#define SYSCTL_PRUSB_R (*((volatile uint32_t *)0x400FEA28)) +#define SYSCTL_PRCAN_R (*((volatile uint32_t *)0x400FEA34)) +#define SYSCTL_PRADC_R (*((volatile uint32_t *)0x400FEA38)) +#define SYSCTL_PRACMP_R (*((volatile uint32_t *)0x400FEA3C)) +#define SYSCTL_PRPWM_R (*((volatile uint32_t *)0x400FEA40)) +#define SYSCTL_PRQEI_R (*((volatile uint32_t *)0x400FEA44)) +#define SYSCTL_PREEPROM_R (*((volatile uint32_t *)0x400FEA58)) +#define SYSCTL_PRWTIMER_R (*((volatile uint32_t *)0x400FEA5C)) + +//***************************************************************************** +// +// Micro Direct Memory Access registers (UDMA) +// +//***************************************************************************** +#define UDMA_STAT_R (*((volatile uint32_t *)0x400FF000)) +#define UDMA_CFG_R (*((volatile uint32_t *)0x400FF004)) +#define UDMA_CTLBASE_R (*((volatile uint32_t *)0x400FF008)) +#define UDMA_ALTBASE_R (*((volatile uint32_t *)0x400FF00C)) +#define UDMA_WAITSTAT_R (*((volatile uint32_t *)0x400FF010)) +#define UDMA_SWREQ_R (*((volatile uint32_t *)0x400FF014)) +#define UDMA_USEBURSTSET_R (*((volatile uint32_t *)0x400FF018)) +#define UDMA_USEBURSTCLR_R (*((volatile uint32_t *)0x400FF01C)) +#define UDMA_REQMASKSET_R (*((volatile uint32_t *)0x400FF020)) +#define UDMA_REQMASKCLR_R (*((volatile uint32_t *)0x400FF024)) +#define UDMA_ENASET_R (*((volatile uint32_t *)0x400FF028)) +#define UDMA_ENACLR_R (*((volatile uint32_t *)0x400FF02C)) +#define UDMA_ALTSET_R (*((volatile uint32_t *)0x400FF030)) +#define UDMA_ALTCLR_R (*((volatile uint32_t *)0x400FF034)) +#define UDMA_PRIOSET_R (*((volatile uint32_t *)0x400FF038)) +#define UDMA_PRIOCLR_R (*((volatile uint32_t *)0x400FF03C)) +#define UDMA_ERRCLR_R (*((volatile uint32_t *)0x400FF04C)) +#define UDMA_CHASGN_R (*((volatile uint32_t *)0x400FF500)) +#define UDMA_CHIS_R (*((volatile uint32_t *)0x400FF504)) +#define UDMA_CHMAP0_R (*((volatile uint32_t *)0x400FF510)) +#define UDMA_CHMAP1_R (*((volatile uint32_t *)0x400FF514)) +#define UDMA_CHMAP2_R (*((volatile uint32_t *)0x400FF518)) +#define UDMA_CHMAP3_R (*((volatile uint32_t *)0x400FF51C)) + +//***************************************************************************** +// +// Micro Direct Memory Access (uDMA) offsets (UDMA) +// +//***************************************************************************** +#define UDMA_SRCENDP 0x00000000 // DMA Channel Source Address End + // Pointer +#define UDMA_DSTENDP 0x00000004 // DMA Channel Destination Address + // End Pointer +#define UDMA_CHCTL 0x00000008 // DMA Channel Control Word + +//***************************************************************************** +// +// NVIC registers (NVIC) +// +//***************************************************************************** +#define NVIC_ACTLR_R (*((volatile uint32_t *)0xE000E008)) +#define NVIC_ST_CTRL_R (*((volatile uint32_t *)0xE000E010)) +#define NVIC_ST_RELOAD_R (*((volatile uint32_t *)0xE000E014)) +#define NVIC_ST_CURRENT_R (*((volatile uint32_t *)0xE000E018)) +#define NVIC_EN0_R (*((volatile uint32_t *)0xE000E100)) +#define NVIC_EN1_R (*((volatile uint32_t *)0xE000E104)) +#define NVIC_EN2_R (*((volatile uint32_t *)0xE000E108)) +#define NVIC_EN3_R (*((volatile uint32_t *)0xE000E10C)) +#define NVIC_EN4_R (*((volatile uint32_t *)0xE000E110)) +#define NVIC_DIS0_R (*((volatile uint32_t *)0xE000E180)) +#define NVIC_DIS1_R (*((volatile uint32_t *)0xE000E184)) +#define NVIC_DIS2_R (*((volatile uint32_t *)0xE000E188)) +#define NVIC_DIS3_R (*((volatile uint32_t *)0xE000E18C)) +#define NVIC_DIS4_R (*((volatile uint32_t *)0xE000E190)) +#define NVIC_PEND0_R (*((volatile uint32_t *)0xE000E200)) +#define NVIC_PEND1_R (*((volatile uint32_t *)0xE000E204)) +#define NVIC_PEND2_R (*((volatile uint32_t *)0xE000E208)) +#define NVIC_PEND3_R (*((volatile uint32_t *)0xE000E20C)) +#define NVIC_PEND4_R (*((volatile uint32_t *)0xE000E210)) +#define NVIC_UNPEND0_R (*((volatile uint32_t *)0xE000E280)) +#define NVIC_UNPEND1_R (*((volatile uint32_t *)0xE000E284)) +#define NVIC_UNPEND2_R (*((volatile uint32_t *)0xE000E288)) +#define NVIC_UNPEND3_R (*((volatile uint32_t *)0xE000E28C)) +#define NVIC_UNPEND4_R (*((volatile uint32_t *)0xE000E290)) +#define NVIC_ACTIVE0_R (*((volatile uint32_t *)0xE000E300)) +#define NVIC_ACTIVE1_R (*((volatile uint32_t *)0xE000E304)) +#define NVIC_ACTIVE2_R (*((volatile uint32_t *)0xE000E308)) +#define NVIC_ACTIVE3_R (*((volatile uint32_t *)0xE000E30C)) +#define NVIC_ACTIVE4_R (*((volatile uint32_t *)0xE000E310)) +#define NVIC_PRI0_R (*((volatile uint32_t *)0xE000E400)) +#define NVIC_PRI1_R (*((volatile uint32_t *)0xE000E404)) +#define NVIC_PRI2_R (*((volatile uint32_t *)0xE000E408)) +#define NVIC_PRI3_R (*((volatile uint32_t *)0xE000E40C)) +#define NVIC_PRI4_R (*((volatile uint32_t *)0xE000E410)) +#define NVIC_PRI5_R (*((volatile uint32_t *)0xE000E414)) +#define NVIC_PRI6_R (*((volatile uint32_t *)0xE000E418)) +#define NVIC_PRI7_R (*((volatile uint32_t *)0xE000E41C)) +#define NVIC_PRI8_R (*((volatile uint32_t *)0xE000E420)) +#define NVIC_PRI9_R (*((volatile uint32_t *)0xE000E424)) +#define NVIC_PRI10_R (*((volatile uint32_t *)0xE000E428)) +#define NVIC_PRI11_R (*((volatile uint32_t *)0xE000E42C)) +#define NVIC_PRI12_R (*((volatile uint32_t *)0xE000E430)) +#define NVIC_PRI13_R (*((volatile uint32_t *)0xE000E434)) +#define NVIC_PRI14_R (*((volatile uint32_t *)0xE000E438)) +#define NVIC_PRI15_R (*((volatile uint32_t *)0xE000E43C)) +#define NVIC_PRI16_R (*((volatile uint32_t *)0xE000E440)) +#define NVIC_PRI17_R (*((volatile uint32_t *)0xE000E444)) +#define NVIC_PRI18_R (*((volatile uint32_t *)0xE000E448)) +#define NVIC_PRI19_R (*((volatile uint32_t *)0xE000E44C)) +#define NVIC_PRI20_R (*((volatile uint32_t *)0xE000E450)) +#define NVIC_PRI21_R (*((volatile uint32_t *)0xE000E454)) +#define NVIC_PRI22_R (*((volatile uint32_t *)0xE000E458)) +#define NVIC_PRI23_R (*((volatile uint32_t *)0xE000E45C)) +#define NVIC_PRI24_R (*((volatile uint32_t *)0xE000E460)) +#define NVIC_PRI25_R (*((volatile uint32_t *)0xE000E464)) +#define NVIC_PRI26_R (*((volatile uint32_t *)0xE000E468)) +#define NVIC_PRI27_R (*((volatile uint32_t *)0xE000E46C)) +#define NVIC_PRI28_R (*((volatile uint32_t *)0xE000E470)) +#define NVIC_PRI29_R (*((volatile uint32_t *)0xE000E474)) +#define NVIC_PRI30_R (*((volatile uint32_t *)0xE000E478)) +#define NVIC_PRI31_R (*((volatile uint32_t *)0xE000E47C)) +#define NVIC_PRI32_R (*((volatile uint32_t *)0xE000E480)) +#define NVIC_PRI33_R (*((volatile uint32_t *)0xE000E484)) +#define NVIC_PRI34_R (*((volatile uint32_t *)0xE000E488)) +#define NVIC_CPUID_R (*((volatile uint32_t *)0xE000ED00)) +#define NVIC_INT_CTRL_R (*((volatile uint32_t *)0xE000ED04)) +#define NVIC_VTABLE_R (*((volatile uint32_t *)0xE000ED08)) +#define NVIC_APINT_R (*((volatile uint32_t *)0xE000ED0C)) +#define NVIC_SYS_CTRL_R (*((volatile uint32_t *)0xE000ED10)) +#define NVIC_CFG_CTRL_R (*((volatile uint32_t *)0xE000ED14)) +#define NVIC_SYS_PRI1_R (*((volatile uint32_t *)0xE000ED18)) +#define NVIC_SYS_PRI2_R (*((volatile uint32_t *)0xE000ED1C)) +#define NVIC_SYS_PRI3_R (*((volatile uint32_t *)0xE000ED20)) +#define NVIC_SYS_HND_CTRL_R (*((volatile uint32_t *)0xE000ED24)) +#define NVIC_FAULT_STAT_R (*((volatile uint32_t *)0xE000ED28)) +#define NVIC_HFAULT_STAT_R (*((volatile uint32_t *)0xE000ED2C)) +#define NVIC_DEBUG_STAT_R (*((volatile uint32_t *)0xE000ED30)) +#define NVIC_MM_ADDR_R (*((volatile uint32_t *)0xE000ED34)) +#define NVIC_FAULT_ADDR_R (*((volatile uint32_t *)0xE000ED38)) +#define NVIC_CPAC_R (*((volatile uint32_t *)0xE000ED88)) +#define NVIC_MPU_TYPE_R (*((volatile uint32_t *)0xE000ED90)) +#define NVIC_MPU_CTRL_R (*((volatile uint32_t *)0xE000ED94)) +#define NVIC_MPU_NUMBER_R (*((volatile uint32_t *)0xE000ED98)) +#define NVIC_MPU_BASE_R (*((volatile uint32_t *)0xE000ED9C)) +#define NVIC_MPU_ATTR_R (*((volatile uint32_t *)0xE000EDA0)) +#define NVIC_MPU_BASE1_R (*((volatile uint32_t *)0xE000EDA4)) +#define NVIC_MPU_ATTR1_R (*((volatile uint32_t *)0xE000EDA8)) +#define NVIC_MPU_BASE2_R (*((volatile uint32_t *)0xE000EDAC)) +#define NVIC_MPU_ATTR2_R (*((volatile uint32_t *)0xE000EDB0)) +#define NVIC_MPU_BASE3_R (*((volatile uint32_t *)0xE000EDB4)) +#define NVIC_MPU_ATTR3_R (*((volatile uint32_t *)0xE000EDB8)) +#define NVIC_DBG_CTRL_R (*((volatile uint32_t *)0xE000EDF0)) +#define NVIC_DBG_XFER_R (*((volatile uint32_t *)0xE000EDF4)) +#define NVIC_DBG_DATA_R (*((volatile uint32_t *)0xE000EDF8)) +#define NVIC_DBG_INT_R (*((volatile uint32_t *)0xE000EDFC)) +#define NVIC_SW_TRIG_R (*((volatile uint32_t *)0xE000EF00)) +#define NVIC_FPCC_R (*((volatile uint32_t *)0xE000EF34)) +#define NVIC_FPCA_R (*((volatile uint32_t *)0xE000EF38)) +#define NVIC_FPDSC_R (*((volatile uint32_t *)0xE000EF3C)) + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_LOAD register. +// +//***************************************************************************** +#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value +#define WDT_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_VALUE register. +// +//***************************************************************************** +#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value +#define WDT_VALUE_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_CTL register. +// +//***************************************************************************** +#define WDT_CTL_WRC 0x80000000 // Write Complete +#define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type +#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable +#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_ICR register. +// +//***************************************************************************** +#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear +#define WDT_ICR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_RIS register. +// +//***************************************************************************** +#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_MIS register. +// +//***************************************************************************** +#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_TEST register. +// +//***************************************************************************** +#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_LOCK register. +// +//***************************************************************************** +#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock +#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked +#define WDT_LOCK_LOCKED 0x00000001 // Locked +#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_IM register. +// +//***************************************************************************** +#define GPIO_IM_GPIO_M 0x000000FF // GPIO Interrupt Mask Enable +#define GPIO_IM_GPIO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_RIS register. +// +//***************************************************************************** +#define GPIO_RIS_GPIO_M 0x000000FF // GPIO Interrupt Raw Status +#define GPIO_RIS_GPIO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_MIS register. +// +//***************************************************************************** +#define GPIO_MIS_GPIO_M 0x000000FF // GPIO Masked Interrupt Status +#define GPIO_MIS_GPIO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_ICR register. +// +//***************************************************************************** +#define GPIO_ICR_GPIO_M 0x000000FF // GPIO Interrupt Clear +#define GPIO_ICR_GPIO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_LOCK register. +// +//***************************************************************************** +#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock +#define GPIO_LOCK_UNLOCKED 0x00000000 // The GPIOCR register is unlocked + // and may be modified +#define GPIO_LOCK_LOCKED 0x00000001 // The GPIOCR register is locked + // and may not be modified +#define GPIO_LOCK_KEY 0x4C4F434B // Unlocks the GPIO_CR register + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port A. +// +//***************************************************************************** +#define GPIO_PCTL_PA7_M 0xF0000000 // PA7 Mask +#define GPIO_PCTL_PA7_I2C1SDA 0x30000000 // I2C1SDA on PA7 +#define GPIO_PCTL_PA7_M1PWM3 0x50000000 // M1PWM3 on PA7 +#define GPIO_PCTL_PA6_M 0x0F000000 // PA6 Mask +#define GPIO_PCTL_PA6_I2C1SCL 0x03000000 // I2C1SCL on PA6 +#define GPIO_PCTL_PA6_M1PWM2 0x05000000 // M1PWM2 on PA6 +#define GPIO_PCTL_PA5_M 0x00F00000 // PA5 Mask +#define GPIO_PCTL_PA5_SSI0TX 0x00200000 // SSI0TX on PA5 +#define GPIO_PCTL_PA4_M 0x000F0000 // PA4 Mask +#define GPIO_PCTL_PA4_SSI0RX 0x00020000 // SSI0RX on PA4 +#define GPIO_PCTL_PA3_M 0x0000F000 // PA3 Mask +#define GPIO_PCTL_PA3_SSI0FSS 0x00002000 // SSI0FSS on PA3 +#define GPIO_PCTL_PA2_M 0x00000F00 // PA2 Mask +#define GPIO_PCTL_PA2_SSI0CLK 0x00000200 // SSI0CLK on PA2 +#define GPIO_PCTL_PA1_M 0x000000F0 // PA1 Mask +#define GPIO_PCTL_PA1_U0TX 0x00000010 // U0TX on PA1 +#define GPIO_PCTL_PA1_CAN1TX 0x00000080 // CAN1TX on PA1 +#define GPIO_PCTL_PA0_M 0x0000000F // PA0 Mask +#define GPIO_PCTL_PA0_U0RX 0x00000001 // U0RX on PA0 +#define GPIO_PCTL_PA0_CAN1RX 0x00000008 // CAN1RX on PA0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port B. +// +//***************************************************************************** +#define GPIO_PCTL_PB7_M 0xF0000000 // PB7 Mask +#define GPIO_PCTL_PB7_SSI2TX 0x20000000 // SSI2TX on PB7 +#define GPIO_PCTL_PB7_M0PWM1 0x40000000 // M0PWM1 on PB7 +#define GPIO_PCTL_PB7_T0CCP1 0x70000000 // T0CCP1 on PB7 +#define GPIO_PCTL_PB6_M 0x0F000000 // PB6 Mask +#define GPIO_PCTL_PB6_SSI2RX 0x02000000 // SSI2RX on PB6 +#define GPIO_PCTL_PB6_M0PWM0 0x04000000 // M0PWM0 on PB6 +#define GPIO_PCTL_PB6_T0CCP0 0x07000000 // T0CCP0 on PB6 +#define GPIO_PCTL_PB5_M 0x00F00000 // PB5 Mask +#define GPIO_PCTL_PB5_SSI2FSS 0x00200000 // SSI2FSS on PB5 +#define GPIO_PCTL_PB5_M0PWM3 0x00400000 // M0PWM3 on PB5 +#define GPIO_PCTL_PB5_T1CCP1 0x00700000 // T1CCP1 on PB5 +#define GPIO_PCTL_PB5_CAN0TX 0x00800000 // CAN0TX on PB5 +#define GPIO_PCTL_PB4_M 0x000F0000 // PB4 Mask +#define GPIO_PCTL_PB4_SSI2CLK 0x00020000 // SSI2CLK on PB4 +#define GPIO_PCTL_PB4_M0PWM2 0x00040000 // M0PWM2 on PB4 +#define GPIO_PCTL_PB4_T1CCP0 0x00070000 // T1CCP0 on PB4 +#define GPIO_PCTL_PB4_CAN0RX 0x00080000 // CAN0RX on PB4 +#define GPIO_PCTL_PB3_M 0x0000F000 // PB3 Mask +#define GPIO_PCTL_PB3_I2C0SDA 0x00003000 // I2C0SDA on PB3 +#define GPIO_PCTL_PB3_T3CCP1 0x00007000 // T3CCP1 on PB3 +#define GPIO_PCTL_PB2_M 0x00000F00 // PB2 Mask +#define GPIO_PCTL_PB2_I2C0SCL 0x00000300 // I2C0SCL on PB2 +#define GPIO_PCTL_PB2_T3CCP0 0x00000700 // T3CCP0 on PB2 +#define GPIO_PCTL_PB1_M 0x000000F0 // PB1 Mask +#define GPIO_PCTL_PB1_USB0VBUS 0x00000000 // USB0VBUS on PB1 +#define GPIO_PCTL_PB1_U1TX 0x00000010 // U1TX on PB1 +#define GPIO_PCTL_PB1_T2CCP1 0x00000070 // T2CCP1 on PB1 +#define GPIO_PCTL_PB0_M 0x0000000F // PB0 Mask +#define GPIO_PCTL_PB0_USB0ID 0x00000000 // USB0ID on PB0 +#define GPIO_PCTL_PB0_U1RX 0x00000001 // U1RX on PB0 +#define GPIO_PCTL_PB0_T2CCP0 0x00000007 // T2CCP0 on PB0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port C. +// +//***************************************************************************** +#define GPIO_PCTL_PC7_M 0xF0000000 // PC7 Mask +#define GPIO_PCTL_PC7_U3TX 0x10000000 // U3TX on PC7 +#define GPIO_PCTL_PC7_WT1CCP1 0x70000000 // WT1CCP1 on PC7 +#define GPIO_PCTL_PC7_USB0PFLT 0x80000000 // USB0PFLT on PC7 +#define GPIO_PCTL_PC6_M 0x0F000000 // PC6 Mask +#define GPIO_PCTL_PC6_U3RX 0x01000000 // U3RX on PC6 +#define GPIO_PCTL_PC6_PHB1 0x06000000 // PHB1 on PC6 +#define GPIO_PCTL_PC6_WT1CCP0 0x07000000 // WT1CCP0 on PC6 +#define GPIO_PCTL_PC6_USB0EPEN 0x08000000 // USB0EPEN on PC6 +#define GPIO_PCTL_PC5_M 0x00F00000 // PC5 Mask +#define GPIO_PCTL_PC5_U4TX 0x00100000 // U4TX on PC5 +#define GPIO_PCTL_PC5_U1TX 0x00200000 // U1TX on PC5 +#define GPIO_PCTL_PC5_M0PWM7 0x00400000 // M0PWM7 on PC5 +#define GPIO_PCTL_PC5_PHA1 0x00600000 // PHA1 on PC5 +#define GPIO_PCTL_PC5_WT0CCP1 0x00700000 // WT0CCP1 on PC5 +#define GPIO_PCTL_PC5_U1CTS 0x00800000 // U1CTS on PC5 +#define GPIO_PCTL_PC4_M 0x000F0000 // PC4 Mask +#define GPIO_PCTL_PC4_U4RX 0x00010000 // U4RX on PC4 +#define GPIO_PCTL_PC4_U1RX 0x00020000 // U1RX on PC4 +#define GPIO_PCTL_PC4_M0PWM6 0x00040000 // M0PWM6 on PC4 +#define GPIO_PCTL_PC4_IDX1 0x00060000 // IDX1 on PC4 +#define GPIO_PCTL_PC4_WT0CCP0 0x00070000 // WT0CCP0 on PC4 +#define GPIO_PCTL_PC4_U1RTS 0x00080000 // U1RTS on PC4 +#define GPIO_PCTL_PC3_M 0x0000F000 // PC3 Mask +#define GPIO_PCTL_PC3_TDO 0x00001000 // TDO on PC3 +#define GPIO_PCTL_PC3_T5CCP1 0x00007000 // T5CCP1 on PC3 +#define GPIO_PCTL_PC2_M 0x00000F00 // PC2 Mask +#define GPIO_PCTL_PC2_TDI 0x00000100 // TDI on PC2 +#define GPIO_PCTL_PC2_T5CCP0 0x00000700 // T5CCP0 on PC2 +#define GPIO_PCTL_PC1_M 0x000000F0 // PC1 Mask +#define GPIO_PCTL_PC1_TMS 0x00000010 // TMS on PC1 +#define GPIO_PCTL_PC1_T4CCP1 0x00000070 // T4CCP1 on PC1 +#define GPIO_PCTL_PC0_M 0x0000000F // PC0 Mask +#define GPIO_PCTL_PC0_TCK 0x00000001 // TCK on PC0 +#define GPIO_PCTL_PC0_T4CCP0 0x00000007 // T4CCP0 on PC0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port D. +// +//***************************************************************************** +#define GPIO_PCTL_PD7_M 0xF0000000 // PD7 Mask +#define GPIO_PCTL_PD7_U2TX 0x10000000 // U2TX on PD7 +#define GPIO_PCTL_PD7_PHB0 0x60000000 // PHB0 on PD7 +#define GPIO_PCTL_PD7_WT5CCP1 0x70000000 // WT5CCP1 on PD7 +#define GPIO_PCTL_PD7_NMI 0x80000000 // NMI on PD7 +#define GPIO_PCTL_PD6_M 0x0F000000 // PD6 Mask +#define GPIO_PCTL_PD6_U2RX 0x01000000 // U2RX on PD6 +#define GPIO_PCTL_PD6_M0FAULT0 0x04000000 // M0FAULT0 on PD6 +#define GPIO_PCTL_PD6_PHA0 0x06000000 // PHA0 on PD6 +#define GPIO_PCTL_PD6_WT5CCP0 0x07000000 // WT5CCP0 on PD6 +#define GPIO_PCTL_PD5_M 0x00F00000 // PD5 Mask +#define GPIO_PCTL_PD5_USB0DP 0x00000000 // USB0DP on PD5 +#define GPIO_PCTL_PD5_U6TX 0x00100000 // U6TX on PD5 +#define GPIO_PCTL_PD5_WT4CCP1 0x00700000 // WT4CCP1 on PD5 +#define GPIO_PCTL_PD4_M 0x000F0000 // PD4 Mask +#define GPIO_PCTL_PD4_USB0DM 0x00000000 // USB0DM on PD4 +#define GPIO_PCTL_PD4_U6RX 0x00010000 // U6RX on PD4 +#define GPIO_PCTL_PD4_WT4CCP0 0x00070000 // WT4CCP0 on PD4 +#define GPIO_PCTL_PD3_M 0x0000F000 // PD3 Mask +#define GPIO_PCTL_PD3_AIN4 0x00000000 // AIN4 on PD3 +#define GPIO_PCTL_PD3_SSI3TX 0x00001000 // SSI3TX on PD3 +#define GPIO_PCTL_PD3_SSI1TX 0x00002000 // SSI1TX on PD3 +#define GPIO_PCTL_PD3_IDX0 0x00006000 // IDX0 on PD3 +#define GPIO_PCTL_PD3_WT3CCP1 0x00007000 // WT3CCP1 on PD3 +#define GPIO_PCTL_PD3_USB0PFLT 0x00008000 // USB0PFLT on PD3 +#define GPIO_PCTL_PD2_M 0x00000F00 // PD2 Mask +#define GPIO_PCTL_PD2_AIN5 0x00000000 // AIN5 on PD2 +#define GPIO_PCTL_PD2_SSI3RX 0x00000100 // SSI3RX on PD2 +#define GPIO_PCTL_PD2_SSI1RX 0x00000200 // SSI1RX on PD2 +#define GPIO_PCTL_PD2_M0FAULT0 0x00000400 // M0FAULT0 on PD2 +#define GPIO_PCTL_PD2_WT3CCP0 0x00000700 // WT3CCP0 on PD2 +#define GPIO_PCTL_PD2_USB0EPEN 0x00000800 // USB0EPEN on PD2 +#define GPIO_PCTL_PD1_M 0x000000F0 // PD1 Mask +#define GPIO_PCTL_PD1_AIN6 0x00000000 // AIN6 on PD1 +#define GPIO_PCTL_PD1_SSI3FSS 0x00000010 // SSI3FSS on PD1 +#define GPIO_PCTL_PD1_SSI1FSS 0x00000020 // SSI1FSS on PD1 +#define GPIO_PCTL_PD1_I2C3SDA 0x00000030 // I2C3SDA on PD1 +#define GPIO_PCTL_PD1_M0PWM7 0x00000040 // M0PWM7 on PD1 +#define GPIO_PCTL_PD1_M1PWM1 0x00000050 // M1PWM1 on PD1 +#define GPIO_PCTL_PD1_WT2CCP1 0x00000070 // WT2CCP1 on PD1 +#define GPIO_PCTL_PD0_M 0x0000000F // PD0 Mask +#define GPIO_PCTL_PD0_AIN7 0x00000000 // AIN7 on PD0 +#define GPIO_PCTL_PD0_SSI3CLK 0x00000001 // SSI3CLK on PD0 +#define GPIO_PCTL_PD0_SSI1CLK 0x00000002 // SSI1CLK on PD0 +#define GPIO_PCTL_PD0_I2C3SCL 0x00000003 // I2C3SCL on PD0 +#define GPIO_PCTL_PD0_M0PWM6 0x00000004 // M0PWM6 on PD0 +#define GPIO_PCTL_PD0_M1PWM0 0x00000005 // M1PWM0 on PD0 +#define GPIO_PCTL_PD0_WT2CCP0 0x00000007 // WT2CCP0 on PD0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port E. +// +//***************************************************************************** +#define GPIO_PCTL_PE5_M 0x00F00000 // PE5 Mask +#define GPIO_PCTL_PE5_AIN8 0x00000000 // AIN8 on PE5 +#define GPIO_PCTL_PE5_U5TX 0x00100000 // U5TX on PE5 +#define GPIO_PCTL_PE5_I2C2SDA 0x00300000 // I2C2SDA on PE5 +#define GPIO_PCTL_PE5_M0PWM5 0x00400000 // M0PWM5 on PE5 +#define GPIO_PCTL_PE5_M1PWM3 0x00500000 // M1PWM3 on PE5 +#define GPIO_PCTL_PE5_CAN0TX 0x00800000 // CAN0TX on PE5 +#define GPIO_PCTL_PE4_M 0x000F0000 // PE4 Mask +#define GPIO_PCTL_PE4_AIN9 0x00000000 // AIN9 on PE4 +#define GPIO_PCTL_PE4_U5RX 0x00010000 // U5RX on PE4 +#define GPIO_PCTL_PE4_I2C2SCL 0x00030000 // I2C2SCL on PE4 +#define GPIO_PCTL_PE4_M0PWM4 0x00040000 // M0PWM4 on PE4 +#define GPIO_PCTL_PE4_M1PWM2 0x00050000 // M1PWM2 on PE4 +#define GPIO_PCTL_PE4_CAN0RX 0x00080000 // CAN0RX on PE4 +#define GPIO_PCTL_PE3_M 0x0000F000 // PE3 Mask +#define GPIO_PCTL_PE3_AIN0 0x00000000 // AIN0 on PE3 +#define GPIO_PCTL_PE2_M 0x00000F00 // PE2 Mask +#define GPIO_PCTL_PE2_AIN1 0x00000000 // AIN1 on PE2 +#define GPIO_PCTL_PE1_M 0x000000F0 // PE1 Mask +#define GPIO_PCTL_PE1_AIN2 0x00000000 // AIN2 on PE1 +#define GPIO_PCTL_PE1_U7TX 0x00000010 // U7TX on PE1 +#define GPIO_PCTL_PE0_M 0x0000000F // PE0 Mask +#define GPIO_PCTL_PE0_AIN3 0x00000000 // AIN3 on PE0 +#define GPIO_PCTL_PE0_U7RX 0x00000001 // U7RX on PE0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port F. +// +//***************************************************************************** +#define GPIO_PCTL_PF4_M 0x000F0000 // PF4 Mask +#define GPIO_PCTL_PF4_M1FAULT0 0x00050000 // M1FAULT0 on PF4 +#define GPIO_PCTL_PF4_IDX0 0x00060000 // IDX0 on PF4 +#define GPIO_PCTL_PF4_T2CCP0 0x00070000 // T2CCP0 on PF4 +#define GPIO_PCTL_PF4_USB0EPEN 0x00080000 // USB0EPEN on PF4 +#define GPIO_PCTL_PF3_M 0x0000F000 // PF3 Mask +#define GPIO_PCTL_PF3_SSI1FSS 0x00002000 // SSI1FSS on PF3 +#define GPIO_PCTL_PF3_CAN0TX 0x00003000 // CAN0TX on PF3 +#define GPIO_PCTL_PF3_M1PWM7 0x00005000 // M1PWM7 on PF3 +#define GPIO_PCTL_PF3_T1CCP1 0x00007000 // T1CCP1 on PF3 +#define GPIO_PCTL_PF3_TRCLK 0x0000E000 // TRCLK on PF3 +#define GPIO_PCTL_PF2_M 0x00000F00 // PF2 Mask +#define GPIO_PCTL_PF2_SSI1CLK 0x00000200 // SSI1CLK on PF2 +#define GPIO_PCTL_PF2_M0FAULT0 0x00000400 // M0FAULT0 on PF2 +#define GPIO_PCTL_PF2_M1PWM6 0x00000500 // M1PWM6 on PF2 +#define GPIO_PCTL_PF2_T1CCP0 0x00000700 // T1CCP0 on PF2 +#define GPIO_PCTL_PF2_TRD0 0x00000E00 // TRD0 on PF2 +#define GPIO_PCTL_PF1_M 0x000000F0 // PF1 Mask +#define GPIO_PCTL_PF1_U1CTS 0x00000010 // U1CTS on PF1 +#define GPIO_PCTL_PF1_SSI1TX 0x00000020 // SSI1TX on PF1 +#define GPIO_PCTL_PF1_M1PWM5 0x00000050 // M1PWM5 on PF1 +#define GPIO_PCTL_PF1_PHB0 0x00000060 // PHB0 on PF1 +#define GPIO_PCTL_PF1_T0CCP1 0x00000070 // T0CCP1 on PF1 +#define GPIO_PCTL_PF1_C1O 0x00000090 // C1O on PF1 +#define GPIO_PCTL_PF1_TRD1 0x000000E0 // TRD1 on PF1 +#define GPIO_PCTL_PF0_M 0x0000000F // PF0 Mask +#define GPIO_PCTL_PF0_U1RTS 0x00000001 // U1RTS on PF0 +#define GPIO_PCTL_PF0_SSI1RX 0x00000002 // SSI1RX on PF0 +#define GPIO_PCTL_PF0_CAN0RX 0x00000003 // CAN0RX on PF0 +#define GPIO_PCTL_PF0_M1PWM4 0x00000005 // M1PWM4 on PF0 +#define GPIO_PCTL_PF0_PHA0 0x00000006 // PHA0 on PF0 +#define GPIO_PCTL_PF0_T0CCP0 0x00000007 // T0CCP0 on PF0 +#define GPIO_PCTL_PF0_NMI 0x00000008 // NMI on PF0 +#define GPIO_PCTL_PF0_C0O 0x00000009 // C0O on PF0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_CR0 register. +// +//***************************************************************************** +#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate +#define SSI_CR0_SPH 0x00000080 // SSI Serial Clock Phase +#define SSI_CR0_SPO 0x00000040 // SSI Serial Clock Polarity +#define SSI_CR0_FRF_M 0x00000030 // SSI Frame Format Select +#define SSI_CR0_FRF_MOTO 0x00000000 // Freescale SPI Frame Format +#define SSI_CR0_FRF_TI 0x00000010 // Synchronous Serial Frame Format +#define SSI_CR0_FRF_NMW 0x00000020 // MICROWIRE Frame Format +#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select +#define SSI_CR0_DSS_4 0x00000003 // 4-bit data +#define SSI_CR0_DSS_5 0x00000004 // 5-bit data +#define SSI_CR0_DSS_6 0x00000005 // 6-bit data +#define SSI_CR0_DSS_7 0x00000006 // 7-bit data +#define SSI_CR0_DSS_8 0x00000007 // 8-bit data +#define SSI_CR0_DSS_9 0x00000008 // 9-bit data +#define SSI_CR0_DSS_10 0x00000009 // 10-bit data +#define SSI_CR0_DSS_11 0x0000000A // 11-bit data +#define SSI_CR0_DSS_12 0x0000000B // 12-bit data +#define SSI_CR0_DSS_13 0x0000000C // 13-bit data +#define SSI_CR0_DSS_14 0x0000000D // 14-bit data +#define SSI_CR0_DSS_15 0x0000000E // 15-bit data +#define SSI_CR0_DSS_16 0x0000000F // 16-bit data +#define SSI_CR0_SCR_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_CR1 register. +// +//***************************************************************************** +#define SSI_CR1_EOT 0x00000010 // End of Transmission +#define SSI_CR1_MS 0x00000004 // SSI Master/Slave Select +#define SSI_CR1_SSE 0x00000002 // SSI Synchronous Serial Port + // Enable +#define SSI_CR1_LBM 0x00000001 // SSI Loopback Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_DR register. +// +//***************************************************************************** +#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data +#define SSI_DR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_SR register. +// +//***************************************************************************** +#define SSI_SR_BSY 0x00000010 // SSI Busy Bit +#define SSI_SR_RFF 0x00000008 // SSI Receive FIFO Full +#define SSI_SR_RNE 0x00000004 // SSI Receive FIFO Not Empty +#define SSI_SR_TNF 0x00000002 // SSI Transmit FIFO Not Full +#define SSI_SR_TFE 0x00000001 // SSI Transmit FIFO Empty + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_CPSR register. +// +//***************************************************************************** +#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor +#define SSI_CPSR_CPSDVSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_IM register. +// +//***************************************************************************** +#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt Mask +#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask +#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt + // Mask +#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt + // Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_RIS register. +// +//***************************************************************************** +#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt + // Status +#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt + // Status +#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw + // Interrupt Status +#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_MIS register. +// +//***************************************************************************** +#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked + // Interrupt Status +#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked + // Interrupt Status +#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked + // Interrupt Status +#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_ICR register. +// +//***************************************************************************** +#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt + // Clear +#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_DMACTL register. +// +//***************************************************************************** +#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable +#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_CC register. +// +//***************************************************************************** +#define SSI_CC_CS_M 0x0000000F // SSI Baud Clock Source +#define SSI_CC_CS_SYSPLL 0x00000000 // System clock (based on clock + // source and divisor factor) +#define SSI_CC_CS_PIOSC 0x00000005 // PIOSC + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_DR register. +// +//***************************************************************************** +#define UART_DR_OE 0x00000800 // UART Overrun Error +#define UART_DR_BE 0x00000400 // UART Break Error +#define UART_DR_PE 0x00000200 // UART Parity Error +#define UART_DR_FE 0x00000100 // UART Framing Error +#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received +#define UART_DR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_RSR register. +// +//***************************************************************************** +#define UART_RSR_OE 0x00000008 // UART Overrun Error +#define UART_RSR_BE 0x00000004 // UART Break Error +#define UART_RSR_PE 0x00000002 // UART Parity Error +#define UART_RSR_FE 0x00000001 // UART Framing Error + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ECR register. +// +//***************************************************************************** +#define UART_ECR_DATA_M 0x000000FF // Error Clear +#define UART_ECR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_FR register. +// +//***************************************************************************** +#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty +#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full +#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full +#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty +#define UART_FR_BUSY 0x00000008 // UART Busy +#define UART_FR_CTS 0x00000001 // Clear To Send + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ILPR register. +// +//***************************************************************************** +#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor +#define UART_ILPR_ILPDVSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_IBRD register. +// +//***************************************************************************** +#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor +#define UART_IBRD_DIVINT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_FBRD register. +// +//***************************************************************************** +#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor +#define UART_FBRD_DIVFRAC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_LCRH register. +// +//***************************************************************************** +#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select +#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length +#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default) +#define UART_LCRH_WLEN_6 0x00000020 // 6 bits +#define UART_LCRH_WLEN_7 0x00000040 // 7 bits +#define UART_LCRH_WLEN_8 0x00000060 // 8 bits +#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs +#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select +#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select +#define UART_LCRH_PEN 0x00000002 // UART Parity Enable +#define UART_LCRH_BRK 0x00000001 // UART Send Break + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_CTL register. +// +//***************************************************************************** +#define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send +#define UART_CTL_RTSEN 0x00004000 // Enable Request to Send +#define UART_CTL_RTS 0x00000800 // Request to Send +#define UART_CTL_RXE 0x00000200 // UART Receive Enable +#define UART_CTL_TXE 0x00000100 // UART Transmit Enable +#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable +#define UART_CTL_HSE 0x00000020 // High-Speed Enable +#define UART_CTL_EOT 0x00000010 // End of Transmission +#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support +#define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode +#define UART_CTL_SIREN 0x00000002 // UART SIR Enable +#define UART_CTL_UARTEN 0x00000001 // UART Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_IFLS register. +// +//***************************************************************************** +#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO + // Level Select +#define UART_IFLS_RX1_8 0x00000000 // RX FIFO >= 1/8 full +#define UART_IFLS_RX2_8 0x00000008 // RX FIFO >= 1/4 full +#define UART_IFLS_RX4_8 0x00000010 // RX FIFO >= 1/2 full (default) +#define UART_IFLS_RX6_8 0x00000018 // RX FIFO >= 3/4 full +#define UART_IFLS_RX7_8 0x00000020 // RX FIFO >= 7/8 full +#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO + // Level Select +#define UART_IFLS_TX1_8 0x00000000 // TX FIFO <= 1/8 full +#define UART_IFLS_TX2_8 0x00000001 // TX FIFO <= 1/4 full +#define UART_IFLS_TX4_8 0x00000002 // TX FIFO <= 1/2 full (default) +#define UART_IFLS_TX6_8 0x00000003 // TX FIFO <= 3/4 full +#define UART_IFLS_TX7_8 0x00000004 // TX FIFO <= 7/8 full + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_IM register. +// +//***************************************************************************** +#define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask +#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt + // Mask +#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask +#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask +#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt + // Mask +#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt + // Mask +#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask +#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask +#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem + // Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_RIS register. +// +//***************************************************************************** +#define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status +#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt + // Status +#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt + // Status +#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt + // Status +#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt + // Status +#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw + // Interrupt Status +#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt + // Status +#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt + // Status +#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_MIS register. +// +//***************************************************************************** +#define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt + // Status +#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked + // Interrupt Status +#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked + // Interrupt Status +#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked + // Interrupt Status +#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked + // Interrupt Status +#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked + // Interrupt Status +#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt + // Status +#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt + // Status +#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ICR register. +// +//***************************************************************************** +#define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear +#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear +#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear +#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear +#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear +#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear +#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear +#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear +#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem + // Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_DMACTL register. +// +//***************************************************************************** +#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error +#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable +#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_9BITADDR +// register. +// +//***************************************************************************** +#define UART_9BITADDR_9BITEN 0x00008000 // Enable 9-Bit Mode +#define UART_9BITADDR_ADDR_M 0x000000FF // Self Address for 9-Bit Mode +#define UART_9BITADDR_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_9BITAMASK +// register. +// +//***************************************************************************** +#define UART_9BITAMASK_MASK_M 0x000000FF // Self Address Mask for 9-Bit Mode +#define UART_9BITAMASK_MASK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_PP register. +// +//***************************************************************************** +#define UART_PP_NB 0x00000002 // 9-Bit Support +#define UART_PP_SC 0x00000001 // Smart Card Support + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_CC register. +// +//***************************************************************************** +#define UART_CC_CS_M 0x0000000F // UART Baud Clock Source +#define UART_CC_CS_SYSCLK 0x00000000 // System clock (based on clock + // source and divisor factor) +#define UART_CC_CS_PIOSC 0x00000005 // PIOSC + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MSA register. +// +//***************************************************************************** +#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address +#define I2C_MSA_RS 0x00000001 // Receive not send +#define I2C_MSA_SA_S 1 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCS register. +// +//***************************************************************************** +#define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error +#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy +#define I2C_MCS_IDLE 0x00000020 // I2C Idle +#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost +#define I2C_MCS_HS 0x00000010 // High-Speed Enable +#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable +#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data +#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address +#define I2C_MCS_STOP 0x00000004 // Generate STOP +#define I2C_MCS_ERROR 0x00000002 // Error +#define I2C_MCS_START 0x00000002 // Generate START +#define I2C_MCS_RUN 0x00000001 // I2C Master Enable +#define I2C_MCS_BUSY 0x00000001 // I2C Busy + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MDR register. +// +//***************************************************************************** +#define I2C_MDR_DATA_M 0x000000FF // This byte contains the data + // transferred during a transaction +#define I2C_MDR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MTPR register. +// +//***************************************************************************** +#define I2C_MTPR_HS 0x00000080 // High-Speed Enable +#define I2C_MTPR_TPR_M 0x0000007F // Timer Period +#define I2C_MTPR_TPR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MIMR register. +// +//***************************************************************************** +#define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask +#define I2C_MIMR_IM 0x00000001 // Master Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MRIS register. +// +//***************************************************************************** +#define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt + // Status +#define I2C_MRIS_RIS 0x00000001 // Master Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MMIS register. +// +//***************************************************************************** +#define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt + // Status +#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MICR register. +// +//***************************************************************************** +#define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear +#define I2C_MICR_IC 0x00000001 // Master Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCR register. +// +//***************************************************************************** +#define I2C_MCR_GFE 0x00000040 // I2C Glitch Filter Enable +#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable +#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable +#define I2C_MCR_LPBK 0x00000001 // I2C Loopback + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCLKOCNT register. +// +//***************************************************************************** +#define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count +#define I2C_MCLKOCNT_CNTL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MBMON register. +// +//***************************************************************************** +#define I2C_MBMON_SDA 0x00000002 // I2C SDA Status +#define I2C_MBMON_SCL 0x00000001 // I2C SCL Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCR2 register. +// +//***************************************************************************** +#define I2C_MCR2_GFPW_M 0x00000070 // I2C Glitch Filter Pulse Width +#define I2C_MCR2_GFPW_BYPASS 0x00000000 // Bypass +#define I2C_MCR2_GFPW_1 0x00000010 // 1 clock +#define I2C_MCR2_GFPW_2 0x00000020 // 2 clocks +#define I2C_MCR2_GFPW_3 0x00000030 // 3 clocks +#define I2C_MCR2_GFPW_4 0x00000040 // 4 clocks +#define I2C_MCR2_GFPW_8 0x00000050 // 8 clocks +#define I2C_MCR2_GFPW_16 0x00000060 // 16 clocks +#define I2C_MCR2_GFPW_31 0x00000070 // 31 clocks + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SOAR register. +// +//***************************************************************************** +#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address +#define I2C_SOAR_OAR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SCSR register. +// +//***************************************************************************** +#define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched +#define I2C_SCSR_FBR 0x00000004 // First Byte Received +#define I2C_SCSR_TREQ 0x00000002 // Transmit Request +#define I2C_SCSR_DA 0x00000001 // Device Active +#define I2C_SCSR_RREQ 0x00000001 // Receive Request + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SDR register. +// +//***************************************************************************** +#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer +#define I2C_SDR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SIMR register. +// +//***************************************************************************** +#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask +#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask +#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SRIS register. +// +//***************************************************************************** +#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt + // Status +#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt + // Status +#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SMIS register. +// +//***************************************************************************** +#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt + // Status +#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt + // Status +#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SICR register. +// +//***************************************************************************** +#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear +#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear +#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SOAR2 register. +// +//***************************************************************************** +#define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable +#define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2 +#define I2C_SOAR2_OAR2_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SACKCTL register. +// +//***************************************************************************** +#define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value +#define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_PP register. +// +//***************************************************************************** +#define I2C_PP_HS 0x00000001 // High-Speed Capable + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_PC register. +// +//***************************************************************************** +#define I2C_PC_HS 0x00000001 // High-Speed Capable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_CTL register. +// +//***************************************************************************** +#define PWM_CTL_GLOBALSYNC3 0x00000008 // Update PWM Generator 3 +#define PWM_CTL_GLOBALSYNC2 0x00000004 // Update PWM Generator 2 +#define PWM_CTL_GLOBALSYNC1 0x00000002 // Update PWM Generator 1 +#define PWM_CTL_GLOBALSYNC0 0x00000001 // Update PWM Generator 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_SYNC register. +// +//***************************************************************************** +#define PWM_SYNC_SYNC3 0x00000008 // Reset Generator 3 Counter +#define PWM_SYNC_SYNC2 0x00000004 // Reset Generator 2 Counter +#define PWM_SYNC_SYNC1 0x00000002 // Reset Generator 1 Counter +#define PWM_SYNC_SYNC0 0x00000001 // Reset Generator 0 Counter + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_ENABLE register. +// +//***************************************************************************** +#define PWM_ENABLE_PWM7EN 0x00000080 // MnPWM7 Output Enable +#define PWM_ENABLE_PWM6EN 0x00000040 // MnPWM6 Output Enable +#define PWM_ENABLE_PWM5EN 0x00000020 // MnPWM5 Output Enable +#define PWM_ENABLE_PWM4EN 0x00000010 // MnPWM4 Output Enable +#define PWM_ENABLE_PWM3EN 0x00000008 // MnPWM3 Output Enable +#define PWM_ENABLE_PWM2EN 0x00000004 // MnPWM2 Output Enable +#define PWM_ENABLE_PWM1EN 0x00000002 // MnPWM1 Output Enable +#define PWM_ENABLE_PWM0EN 0x00000001 // MnPWM0 Output Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_INVERT register. +// +//***************************************************************************** +#define PWM_INVERT_PWM7INV 0x00000080 // Invert MnPWM7 Signal +#define PWM_INVERT_PWM6INV 0x00000040 // Invert MnPWM6 Signal +#define PWM_INVERT_PWM5INV 0x00000020 // Invert MnPWM5 Signal +#define PWM_INVERT_PWM4INV 0x00000010 // Invert MnPWM4 Signal +#define PWM_INVERT_PWM3INV 0x00000008 // Invert MnPWM3 Signal +#define PWM_INVERT_PWM2INV 0x00000004 // Invert MnPWM2 Signal +#define PWM_INVERT_PWM1INV 0x00000002 // Invert MnPWM1 Signal +#define PWM_INVERT_PWM0INV 0x00000001 // Invert MnPWM0 Signal + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_FAULT register. +// +//***************************************************************************** +#define PWM_FAULT_FAULT7 0x00000080 // MnPWM7 Fault +#define PWM_FAULT_FAULT6 0x00000040 // MnPWM6 Fault +#define PWM_FAULT_FAULT5 0x00000020 // MnPWM5 Fault +#define PWM_FAULT_FAULT4 0x00000010 // MnPWM4 Fault +#define PWM_FAULT_FAULT3 0x00000008 // MnPWM3 Fault +#define PWM_FAULT_FAULT2 0x00000004 // MnPWM2 Fault +#define PWM_FAULT_FAULT1 0x00000002 // MnPWM1 Fault +#define PWM_FAULT_FAULT0 0x00000001 // MnPWM0 Fault + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_INTEN register. +// +//***************************************************************************** +#define PWM_INTEN_INTFAULT1 0x00020000 // Interrupt Fault 1 +#define PWM_INTEN_INTFAULT0 0x00010000 // Interrupt Fault 0 +#define PWM_INTEN_INTPWM3 0x00000008 // PWM3 Interrupt Enable +#define PWM_INTEN_INTPWM2 0x00000004 // PWM2 Interrupt Enable +#define PWM_INTEN_INTPWM1 0x00000002 // PWM1 Interrupt Enable +#define PWM_INTEN_INTPWM0 0x00000001 // PWM0 Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_RIS register. +// +//***************************************************************************** +#define PWM_RIS_INTFAULT1 0x00020000 // Interrupt Fault PWM 1 +#define PWM_RIS_INTFAULT0 0x00010000 // Interrupt Fault PWM 0 +#define PWM_RIS_INTPWM3 0x00000008 // PWM3 Interrupt Asserted +#define PWM_RIS_INTPWM2 0x00000004 // PWM2 Interrupt Asserted +#define PWM_RIS_INTPWM1 0x00000002 // PWM1 Interrupt Asserted +#define PWM_RIS_INTPWM0 0x00000001 // PWM0 Interrupt Asserted + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_ISC register. +// +//***************************************************************************** +#define PWM_ISC_INTFAULT1 0x00020000 // FAULT1 Interrupt Asserted +#define PWM_ISC_INTFAULT0 0x00010000 // FAULT0 Interrupt Asserted +#define PWM_ISC_INTPWM3 0x00000008 // PWM3 Interrupt Status +#define PWM_ISC_INTPWM2 0x00000004 // PWM2 Interrupt Status +#define PWM_ISC_INTPWM1 0x00000002 // PWM1 Interrupt Status +#define PWM_ISC_INTPWM0 0x00000001 // PWM0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_STATUS register. +// +//***************************************************************************** +#define PWM_STATUS_FAULT1 0x00000002 // Generator 1 Fault Status +#define PWM_STATUS_FAULT0 0x00000001 // Generator 0 Fault Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_FAULTVAL register. +// +//***************************************************************************** +#define PWM_FAULTVAL_PWM7 0x00000080 // MnPWM7 Fault Value +#define PWM_FAULTVAL_PWM6 0x00000040 // MnPWM6 Fault Value +#define PWM_FAULTVAL_PWM5 0x00000020 // MnPWM5 Fault Value +#define PWM_FAULTVAL_PWM4 0x00000010 // MnPWM4 Fault Value +#define PWM_FAULTVAL_PWM3 0x00000008 // MnPWM3 Fault Value +#define PWM_FAULTVAL_PWM2 0x00000004 // MnPWM2 Fault Value +#define PWM_FAULTVAL_PWM1 0x00000002 // MnPWM1 Fault Value +#define PWM_FAULTVAL_PWM0 0x00000001 // MnPWM0 Fault Value + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_ENUPD register. +// +//***************************************************************************** +#define PWM_ENUPD_ENUPD7_M 0x0000C000 // MnPWM7 Enable Update Mode +#define PWM_ENUPD_ENUPD7_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD7_LSYNC 0x00008000 // Locally Synchronized +#define PWM_ENUPD_ENUPD7_GSYNC 0x0000C000 // Globally Synchronized +#define PWM_ENUPD_ENUPD6_M 0x00003000 // MnPWM6 Enable Update Mode +#define PWM_ENUPD_ENUPD6_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD6_LSYNC 0x00002000 // Locally Synchronized +#define PWM_ENUPD_ENUPD6_GSYNC 0x00003000 // Globally Synchronized +#define PWM_ENUPD_ENUPD5_M 0x00000C00 // MnPWM5 Enable Update Mode +#define PWM_ENUPD_ENUPD5_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD5_LSYNC 0x00000800 // Locally Synchronized +#define PWM_ENUPD_ENUPD5_GSYNC 0x00000C00 // Globally Synchronized +#define PWM_ENUPD_ENUPD4_M 0x00000300 // MnPWM4 Enable Update Mode +#define PWM_ENUPD_ENUPD4_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD4_LSYNC 0x00000200 // Locally Synchronized +#define PWM_ENUPD_ENUPD4_GSYNC 0x00000300 // Globally Synchronized +#define PWM_ENUPD_ENUPD3_M 0x000000C0 // MnPWM3 Enable Update Mode +#define PWM_ENUPD_ENUPD3_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD3_LSYNC 0x00000080 // Locally Synchronized +#define PWM_ENUPD_ENUPD3_GSYNC 0x000000C0 // Globally Synchronized +#define PWM_ENUPD_ENUPD2_M 0x00000030 // MnPWM2 Enable Update Mode +#define PWM_ENUPD_ENUPD2_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD2_LSYNC 0x00000020 // Locally Synchronized +#define PWM_ENUPD_ENUPD2_GSYNC 0x00000030 // Globally Synchronized +#define PWM_ENUPD_ENUPD1_M 0x0000000C // MnPWM1 Enable Update Mode +#define PWM_ENUPD_ENUPD1_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD1_LSYNC 0x00000008 // Locally Synchronized +#define PWM_ENUPD_ENUPD1_GSYNC 0x0000000C // Globally Synchronized +#define PWM_ENUPD_ENUPD0_M 0x00000003 // MnPWM0 Enable Update Mode +#define PWM_ENUPD_ENUPD0_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD0_LSYNC 0x00000002 // Locally Synchronized +#define PWM_ENUPD_ENUPD0_GSYNC 0x00000003 // Globally Synchronized + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_CTL register. +// +//***************************************************************************** +#define PWM_0_CTL_LATCH 0x00040000 // Latch Fault Input +#define PWM_0_CTL_MINFLTPER 0x00020000 // Minimum Fault Period +#define PWM_0_CTL_FLTSRC 0x00010000 // Fault Condition Source +#define PWM_0_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode +#define PWM_0_CTL_DBFALLUPD_I 0x00000000 // Immediate +#define PWM_0_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized +#define PWM_0_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized +#define PWM_0_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode +#define PWM_0_CTL_DBRISEUPD_I 0x00000000 // Immediate +#define PWM_0_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized +#define PWM_0_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized +#define PWM_0_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode +#define PWM_0_CTL_DBCTLUPD_I 0x00000000 // Immediate +#define PWM_0_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized +#define PWM_0_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized +#define PWM_0_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode +#define PWM_0_CTL_GENBUPD_I 0x00000000 // Immediate +#define PWM_0_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized +#define PWM_0_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized +#define PWM_0_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode +#define PWM_0_CTL_GENAUPD_I 0x00000000 // Immediate +#define PWM_0_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized +#define PWM_0_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized +#define PWM_0_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode +#define PWM_0_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode +#define PWM_0_CTL_LOADUPD 0x00000008 // Load Register Update Mode +#define PWM_0_CTL_DEBUG 0x00000004 // Debug Mode +#define PWM_0_CTL_MODE 0x00000002 // Counter Mode +#define PWM_0_CTL_ENABLE 0x00000001 // PWM Block Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_INTEN register. +// +//***************************************************************************** +#define PWM_0_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB + // Down +#define PWM_0_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up +#define PWM_0_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA + // Down +#define PWM_0_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up +#define PWM_0_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD +#define PWM_0_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 +#define PWM_0_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB + // Down +#define PWM_0_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB + // Up +#define PWM_0_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA + // Down +#define PWM_0_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA + // Up +#define PWM_0_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD +#define PWM_0_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_RIS register. +// +//***************************************************************************** +#define PWM_0_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt + // Status +#define PWM_0_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status +#define PWM_0_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt + // Status +#define PWM_0_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status +#define PWM_0_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status +#define PWM_0_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_ISC register. +// +//***************************************************************************** +#define PWM_0_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt +#define PWM_0_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt +#define PWM_0_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt +#define PWM_0_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt +#define PWM_0_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt +#define PWM_0_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_LOAD register. +// +//***************************************************************************** +#define PWM_0_LOAD_M 0x0000FFFF // Counter Load Value +#define PWM_0_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_COUNT register. +// +//***************************************************************************** +#define PWM_0_COUNT_M 0x0000FFFF // Counter Value +#define PWM_0_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_CMPA register. +// +//***************************************************************************** +#define PWM_0_CMPA_M 0x0000FFFF // Comparator A Value +#define PWM_0_CMPA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_CMPB register. +// +//***************************************************************************** +#define PWM_0_CMPB_M 0x0000FFFF // Comparator B Value +#define PWM_0_CMPB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_GENA register. +// +//***************************************************************************** +#define PWM_0_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_0_GENA_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA +#define PWM_0_GENA_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmA Low +#define PWM_0_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High +#define PWM_0_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_0_GENA_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA +#define PWM_0_GENA_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmA Low +#define PWM_0_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High +#define PWM_0_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_0_GENA_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA +#define PWM_0_GENA_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmA Low +#define PWM_0_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High +#define PWM_0_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_0_GENA_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA +#define PWM_0_GENA_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmA Low +#define PWM_0_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High +#define PWM_0_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_0_GENA_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_0_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA +#define PWM_0_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low +#define PWM_0_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High +#define PWM_0_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_0_GENA_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_0_GENA_ACTZERO_INV 0x00000001 // Invert pwmA +#define PWM_0_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low +#define PWM_0_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_GENB register. +// +//***************************************************************************** +#define PWM_0_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_0_GENB_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB +#define PWM_0_GENB_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmB Low +#define PWM_0_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High +#define PWM_0_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_0_GENB_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB +#define PWM_0_GENB_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmB Low +#define PWM_0_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High +#define PWM_0_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_0_GENB_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB +#define PWM_0_GENB_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmB Low +#define PWM_0_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High +#define PWM_0_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_0_GENB_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB +#define PWM_0_GENB_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmB Low +#define PWM_0_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High +#define PWM_0_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_0_GENB_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_0_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB +#define PWM_0_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low +#define PWM_0_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High +#define PWM_0_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_0_GENB_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_0_GENB_ACTZERO_INV 0x00000001 // Invert pwmB +#define PWM_0_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low +#define PWM_0_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_DBCTL register. +// +//***************************************************************************** +#define PWM_0_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_DBRISE register. +// +//***************************************************************************** +#define PWM_0_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay +#define PWM_0_DBRISE_DELAY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_DBFALL register. +// +//***************************************************************************** +#define PWM_0_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay +#define PWM_0_DBFALL_DELAY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_FLTSRC0 +// register. +// +//***************************************************************************** +#define PWM_0_FLTSRC0_FAULT1 0x00000002 // Fault1 Input +#define PWM_0_FLTSRC0_FAULT0 0x00000001 // Fault0 Input + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_FLTSRC1 +// register. +// +//***************************************************************************** +#define PWM_0_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 +#define PWM_0_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 +#define PWM_0_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 +#define PWM_0_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 +#define PWM_0_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 +#define PWM_0_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 +#define PWM_0_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 +#define PWM_0_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_MINFLTPER +// register. +// +//***************************************************************************** +#define PWM_0_MINFLTPER_M 0x0000FFFF // Minimum Fault Period +#define PWM_0_MINFLTPER_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_CTL register. +// +//***************************************************************************** +#define PWM_1_CTL_LATCH 0x00040000 // Latch Fault Input +#define PWM_1_CTL_MINFLTPER 0x00020000 // Minimum Fault Period +#define PWM_1_CTL_FLTSRC 0x00010000 // Fault Condition Source +#define PWM_1_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode +#define PWM_1_CTL_DBFALLUPD_I 0x00000000 // Immediate +#define PWM_1_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized +#define PWM_1_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized +#define PWM_1_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode +#define PWM_1_CTL_DBRISEUPD_I 0x00000000 // Immediate +#define PWM_1_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized +#define PWM_1_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized +#define PWM_1_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode +#define PWM_1_CTL_DBCTLUPD_I 0x00000000 // Immediate +#define PWM_1_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized +#define PWM_1_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized +#define PWM_1_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode +#define PWM_1_CTL_GENBUPD_I 0x00000000 // Immediate +#define PWM_1_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized +#define PWM_1_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized +#define PWM_1_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode +#define PWM_1_CTL_GENAUPD_I 0x00000000 // Immediate +#define PWM_1_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized +#define PWM_1_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized +#define PWM_1_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode +#define PWM_1_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode +#define PWM_1_CTL_LOADUPD 0x00000008 // Load Register Update Mode +#define PWM_1_CTL_DEBUG 0x00000004 // Debug Mode +#define PWM_1_CTL_MODE 0x00000002 // Counter Mode +#define PWM_1_CTL_ENABLE 0x00000001 // PWM Block Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_INTEN register. +// +//***************************************************************************** +#define PWM_1_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB + // Down +#define PWM_1_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up +#define PWM_1_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA + // Down +#define PWM_1_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up +#define PWM_1_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD +#define PWM_1_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 +#define PWM_1_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB + // Down +#define PWM_1_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB + // Up +#define PWM_1_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA + // Down +#define PWM_1_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA + // Up +#define PWM_1_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD +#define PWM_1_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_RIS register. +// +//***************************************************************************** +#define PWM_1_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt + // Status +#define PWM_1_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status +#define PWM_1_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt + // Status +#define PWM_1_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status +#define PWM_1_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status +#define PWM_1_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_ISC register. +// +//***************************************************************************** +#define PWM_1_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt +#define PWM_1_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt +#define PWM_1_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt +#define PWM_1_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt +#define PWM_1_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt +#define PWM_1_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_LOAD register. +// +//***************************************************************************** +#define PWM_1_LOAD_LOAD_M 0x0000FFFF // Counter Load Value +#define PWM_1_LOAD_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_COUNT register. +// +//***************************************************************************** +#define PWM_1_COUNT_COUNT_M 0x0000FFFF // Counter Value +#define PWM_1_COUNT_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_CMPA register. +// +//***************************************************************************** +#define PWM_1_CMPA_COMPA_M 0x0000FFFF // Comparator A Value +#define PWM_1_CMPA_COMPA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_CMPB register. +// +//***************************************************************************** +#define PWM_1_CMPB_COMPB_M 0x0000FFFF // Comparator B Value +#define PWM_1_CMPB_COMPB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_GENA register. +// +//***************************************************************************** +#define PWM_1_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_1_GENA_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA +#define PWM_1_GENA_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmA Low +#define PWM_1_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High +#define PWM_1_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_1_GENA_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA +#define PWM_1_GENA_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmA Low +#define PWM_1_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High +#define PWM_1_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_1_GENA_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA +#define PWM_1_GENA_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmA Low +#define PWM_1_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High +#define PWM_1_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_1_GENA_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA +#define PWM_1_GENA_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmA Low +#define PWM_1_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High +#define PWM_1_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_1_GENA_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_1_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA +#define PWM_1_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low +#define PWM_1_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High +#define PWM_1_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_1_GENA_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_1_GENA_ACTZERO_INV 0x00000001 // Invert pwmA +#define PWM_1_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low +#define PWM_1_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_GENB register. +// +//***************************************************************************** +#define PWM_1_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_1_GENB_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB +#define PWM_1_GENB_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmB Low +#define PWM_1_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High +#define PWM_1_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_1_GENB_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB +#define PWM_1_GENB_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmB Low +#define PWM_1_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High +#define PWM_1_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_1_GENB_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB +#define PWM_1_GENB_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmB Low +#define PWM_1_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High +#define PWM_1_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_1_GENB_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB +#define PWM_1_GENB_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmB Low +#define PWM_1_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High +#define PWM_1_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_1_GENB_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_1_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB +#define PWM_1_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low +#define PWM_1_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High +#define PWM_1_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_1_GENB_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_1_GENB_ACTZERO_INV 0x00000001 // Invert pwmB +#define PWM_1_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low +#define PWM_1_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_DBCTL register. +// +//***************************************************************************** +#define PWM_1_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_DBRISE register. +// +//***************************************************************************** +#define PWM_1_DBRISE_RISEDELAY_M \ + 0x00000FFF // Dead-Band Rise Delay +#define PWM_1_DBRISE_RISEDELAY_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_DBFALL register. +// +//***************************************************************************** +#define PWM_1_DBFALL_FALLDELAY_M \ + 0x00000FFF // Dead-Band Fall Delay +#define PWM_1_DBFALL_FALLDELAY_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_FLTSRC0 +// register. +// +//***************************************************************************** +#define PWM_1_FLTSRC0_FAULT1 0x00000002 // Fault1 Input +#define PWM_1_FLTSRC0_FAULT0 0x00000001 // Fault0 Input + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_FLTSRC1 +// register. +// +//***************************************************************************** +#define PWM_1_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 +#define PWM_1_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 +#define PWM_1_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 +#define PWM_1_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 +#define PWM_1_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 +#define PWM_1_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 +#define PWM_1_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 +#define PWM_1_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_MINFLTPER +// register. +// +//***************************************************************************** +#define PWM_1_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period +#define PWM_1_MINFLTPER_MFP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_CTL register. +// +//***************************************************************************** +#define PWM_2_CTL_LATCH 0x00040000 // Latch Fault Input +#define PWM_2_CTL_MINFLTPER 0x00020000 // Minimum Fault Period +#define PWM_2_CTL_FLTSRC 0x00010000 // Fault Condition Source +#define PWM_2_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode +#define PWM_2_CTL_DBFALLUPD_I 0x00000000 // Immediate +#define PWM_2_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized +#define PWM_2_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized +#define PWM_2_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode +#define PWM_2_CTL_DBRISEUPD_I 0x00000000 // Immediate +#define PWM_2_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized +#define PWM_2_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized +#define PWM_2_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode +#define PWM_2_CTL_DBCTLUPD_I 0x00000000 // Immediate +#define PWM_2_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized +#define PWM_2_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized +#define PWM_2_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode +#define PWM_2_CTL_GENBUPD_I 0x00000000 // Immediate +#define PWM_2_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized +#define PWM_2_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized +#define PWM_2_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode +#define PWM_2_CTL_GENAUPD_I 0x00000000 // Immediate +#define PWM_2_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized +#define PWM_2_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized +#define PWM_2_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode +#define PWM_2_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode +#define PWM_2_CTL_LOADUPD 0x00000008 // Load Register Update Mode +#define PWM_2_CTL_DEBUG 0x00000004 // Debug Mode +#define PWM_2_CTL_MODE 0x00000002 // Counter Mode +#define PWM_2_CTL_ENABLE 0x00000001 // PWM Block Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_INTEN register. +// +//***************************************************************************** +#define PWM_2_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB + // Down +#define PWM_2_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up +#define PWM_2_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA + // Down +#define PWM_2_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up +#define PWM_2_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD +#define PWM_2_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 +#define PWM_2_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB + // Down +#define PWM_2_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB + // Up +#define PWM_2_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA + // Down +#define PWM_2_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA + // Up +#define PWM_2_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD +#define PWM_2_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_RIS register. +// +//***************************************************************************** +#define PWM_2_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt + // Status +#define PWM_2_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status +#define PWM_2_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt + // Status +#define PWM_2_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status +#define PWM_2_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status +#define PWM_2_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_ISC register. +// +//***************************************************************************** +#define PWM_2_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt +#define PWM_2_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt +#define PWM_2_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt +#define PWM_2_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt +#define PWM_2_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt +#define PWM_2_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_LOAD register. +// +//***************************************************************************** +#define PWM_2_LOAD_LOAD_M 0x0000FFFF // Counter Load Value +#define PWM_2_LOAD_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_COUNT register. +// +//***************************************************************************** +#define PWM_2_COUNT_COUNT_M 0x0000FFFF // Counter Value +#define PWM_2_COUNT_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_CMPA register. +// +//***************************************************************************** +#define PWM_2_CMPA_COMPA_M 0x0000FFFF // Comparator A Value +#define PWM_2_CMPA_COMPA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_CMPB register. +// +//***************************************************************************** +#define PWM_2_CMPB_COMPB_M 0x0000FFFF // Comparator B Value +#define PWM_2_CMPB_COMPB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_GENA register. +// +//***************************************************************************** +#define PWM_2_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_2_GENA_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA +#define PWM_2_GENA_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmA Low +#define PWM_2_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High +#define PWM_2_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_2_GENA_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA +#define PWM_2_GENA_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmA Low +#define PWM_2_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High +#define PWM_2_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_2_GENA_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA +#define PWM_2_GENA_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmA Low +#define PWM_2_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High +#define PWM_2_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_2_GENA_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA +#define PWM_2_GENA_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmA Low +#define PWM_2_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High +#define PWM_2_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_2_GENA_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_2_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA +#define PWM_2_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low +#define PWM_2_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High +#define PWM_2_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_2_GENA_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_2_GENA_ACTZERO_INV 0x00000001 // Invert pwmA +#define PWM_2_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low +#define PWM_2_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_GENB register. +// +//***************************************************************************** +#define PWM_2_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_2_GENB_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB +#define PWM_2_GENB_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmB Low +#define PWM_2_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High +#define PWM_2_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_2_GENB_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB +#define PWM_2_GENB_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmB Low +#define PWM_2_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High +#define PWM_2_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_2_GENB_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB +#define PWM_2_GENB_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmB Low +#define PWM_2_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High +#define PWM_2_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_2_GENB_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB +#define PWM_2_GENB_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmB Low +#define PWM_2_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High +#define PWM_2_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_2_GENB_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_2_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB +#define PWM_2_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low +#define PWM_2_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High +#define PWM_2_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_2_GENB_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_2_GENB_ACTZERO_INV 0x00000001 // Invert pwmB +#define PWM_2_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low +#define PWM_2_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_DBCTL register. +// +//***************************************************************************** +#define PWM_2_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_DBRISE register. +// +//***************************************************************************** +#define PWM_2_DBRISE_RISEDELAY_M \ + 0x00000FFF // Dead-Band Rise Delay +#define PWM_2_DBRISE_RISEDELAY_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_DBFALL register. +// +//***************************************************************************** +#define PWM_2_DBFALL_FALLDELAY_M \ + 0x00000FFF // Dead-Band Fall Delay +#define PWM_2_DBFALL_FALLDELAY_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_FLTSRC0 +// register. +// +//***************************************************************************** +#define PWM_2_FLTSRC0_FAULT1 0x00000002 // Fault1 Input +#define PWM_2_FLTSRC0_FAULT0 0x00000001 // Fault0 Input + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_FLTSRC1 +// register. +// +//***************************************************************************** +#define PWM_2_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 +#define PWM_2_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 +#define PWM_2_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 +#define PWM_2_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 +#define PWM_2_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 +#define PWM_2_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 +#define PWM_2_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 +#define PWM_2_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_MINFLTPER +// register. +// +//***************************************************************************** +#define PWM_2_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period +#define PWM_2_MINFLTPER_MFP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_CTL register. +// +//***************************************************************************** +#define PWM_3_CTL_LATCH 0x00040000 // Latch Fault Input +#define PWM_3_CTL_MINFLTPER 0x00020000 // Minimum Fault Period +#define PWM_3_CTL_FLTSRC 0x00010000 // Fault Condition Source +#define PWM_3_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode +#define PWM_3_CTL_DBFALLUPD_I 0x00000000 // Immediate +#define PWM_3_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized +#define PWM_3_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized +#define PWM_3_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode +#define PWM_3_CTL_DBRISEUPD_I 0x00000000 // Immediate +#define PWM_3_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized +#define PWM_3_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized +#define PWM_3_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode +#define PWM_3_CTL_DBCTLUPD_I 0x00000000 // Immediate +#define PWM_3_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized +#define PWM_3_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized +#define PWM_3_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode +#define PWM_3_CTL_GENBUPD_I 0x00000000 // Immediate +#define PWM_3_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized +#define PWM_3_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized +#define PWM_3_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode +#define PWM_3_CTL_GENAUPD_I 0x00000000 // Immediate +#define PWM_3_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized +#define PWM_3_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized +#define PWM_3_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode +#define PWM_3_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode +#define PWM_3_CTL_LOADUPD 0x00000008 // Load Register Update Mode +#define PWM_3_CTL_DEBUG 0x00000004 // Debug Mode +#define PWM_3_CTL_MODE 0x00000002 // Counter Mode +#define PWM_3_CTL_ENABLE 0x00000001 // PWM Block Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_INTEN register. +// +//***************************************************************************** +#define PWM_3_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB + // Down +#define PWM_3_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up +#define PWM_3_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA + // Down +#define PWM_3_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up +#define PWM_3_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD +#define PWM_3_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 +#define PWM_3_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB + // Down +#define PWM_3_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB + // Up +#define PWM_3_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA + // Down +#define PWM_3_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA + // Up +#define PWM_3_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD +#define PWM_3_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_RIS register. +// +//***************************************************************************** +#define PWM_3_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt + // Status +#define PWM_3_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status +#define PWM_3_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt + // Status +#define PWM_3_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status +#define PWM_3_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status +#define PWM_3_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_ISC register. +// +//***************************************************************************** +#define PWM_3_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt +#define PWM_3_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt +#define PWM_3_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt +#define PWM_3_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt +#define PWM_3_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt +#define PWM_3_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_LOAD register. +// +//***************************************************************************** +#define PWM_3_LOAD_LOAD_M 0x0000FFFF // Counter Load Value +#define PWM_3_LOAD_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_COUNT register. +// +//***************************************************************************** +#define PWM_3_COUNT_COUNT_M 0x0000FFFF // Counter Value +#define PWM_3_COUNT_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_CMPA register. +// +//***************************************************************************** +#define PWM_3_CMPA_COMPA_M 0x0000FFFF // Comparator A Value +#define PWM_3_CMPA_COMPA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_CMPB register. +// +//***************************************************************************** +#define PWM_3_CMPB_COMPB_M 0x0000FFFF // Comparator B Value +#define PWM_3_CMPB_COMPB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_GENA register. +// +//***************************************************************************** +#define PWM_3_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_3_GENA_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA +#define PWM_3_GENA_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmA Low +#define PWM_3_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High +#define PWM_3_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_3_GENA_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA +#define PWM_3_GENA_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmA Low +#define PWM_3_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High +#define PWM_3_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_3_GENA_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA +#define PWM_3_GENA_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmA Low +#define PWM_3_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High +#define PWM_3_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_3_GENA_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA +#define PWM_3_GENA_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmA Low +#define PWM_3_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High +#define PWM_3_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_3_GENA_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_3_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA +#define PWM_3_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low +#define PWM_3_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High +#define PWM_3_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_3_GENA_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_3_GENA_ACTZERO_INV 0x00000001 // Invert pwmA +#define PWM_3_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low +#define PWM_3_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_GENB register. +// +//***************************************************************************** +#define PWM_3_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_3_GENB_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB +#define PWM_3_GENB_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmB Low +#define PWM_3_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High +#define PWM_3_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_3_GENB_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB +#define PWM_3_GENB_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmB Low +#define PWM_3_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High +#define PWM_3_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_3_GENB_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB +#define PWM_3_GENB_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmB Low +#define PWM_3_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High +#define PWM_3_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_3_GENB_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB +#define PWM_3_GENB_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmB Low +#define PWM_3_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High +#define PWM_3_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_3_GENB_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_3_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB +#define PWM_3_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low +#define PWM_3_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High +#define PWM_3_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_3_GENB_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_3_GENB_ACTZERO_INV 0x00000001 // Invert pwmB +#define PWM_3_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low +#define PWM_3_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_DBCTL register. +// +//***************************************************************************** +#define PWM_3_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_DBRISE register. +// +//***************************************************************************** +#define PWM_3_DBRISE_RISEDELAY_M \ + 0x00000FFF // Dead-Band Rise Delay +#define PWM_3_DBRISE_RISEDELAY_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_DBFALL register. +// +//***************************************************************************** +#define PWM_3_DBFALL_FALLDELAY_M \ + 0x00000FFF // Dead-Band Fall Delay +#define PWM_3_DBFALL_FALLDELAY_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_FLTSRC0 +// register. +// +//***************************************************************************** +#define PWM_3_FLTSRC0_FAULT1 0x00000002 // Fault1 Input +#define PWM_3_FLTSRC0_FAULT0 0x00000001 // Fault0 Input + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_FLTSRC1 +// register. +// +//***************************************************************************** +#define PWM_3_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 +#define PWM_3_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 +#define PWM_3_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 +#define PWM_3_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 +#define PWM_3_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 +#define PWM_3_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 +#define PWM_3_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 +#define PWM_3_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_MINFLTPER +// register. +// +//***************************************************************************** +#define PWM_3_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period +#define PWM_3_MINFLTPER_MFP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_FLTSEN register. +// +//***************************************************************************** +#define PWM_0_FLTSEN_FAULT1 0x00000002 // Fault1 Sense +#define PWM_0_FLTSEN_FAULT0 0x00000001 // Fault0 Sense + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_FLTSTAT0 +// register. +// +//***************************************************************************** +#define PWM_0_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 +#define PWM_0_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_FLTSTAT1 +// register. +// +//***************************************************************************** +#define PWM_0_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger +#define PWM_0_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger +#define PWM_0_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger +#define PWM_0_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger +#define PWM_0_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger +#define PWM_0_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger +#define PWM_0_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger +#define PWM_0_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_FLTSEN register. +// +//***************************************************************************** +#define PWM_1_FLTSEN_FAULT1 0x00000002 // Fault1 Sense +#define PWM_1_FLTSEN_FAULT0 0x00000001 // Fault0 Sense + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_FLTSTAT0 +// register. +// +//***************************************************************************** +#define PWM_1_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 +#define PWM_1_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_FLTSTAT1 +// register. +// +//***************************************************************************** +#define PWM_1_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger +#define PWM_1_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger +#define PWM_1_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger +#define PWM_1_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger +#define PWM_1_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger +#define PWM_1_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger +#define PWM_1_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger +#define PWM_1_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_FLTSTAT0 +// register. +// +//***************************************************************************** +#define PWM_2_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 +#define PWM_2_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_FLTSTAT1 +// register. +// +//***************************************************************************** +#define PWM_2_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger +#define PWM_2_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger +#define PWM_2_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger +#define PWM_2_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger +#define PWM_2_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger +#define PWM_2_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger +#define PWM_2_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger +#define PWM_2_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_FLTSTAT0 +// register. +// +//***************************************************************************** +#define PWM_3_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 +#define PWM_3_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_FLTSTAT1 +// register. +// +//***************************************************************************** +#define PWM_3_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger +#define PWM_3_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger +#define PWM_3_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger +#define PWM_3_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger +#define PWM_3_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger +#define PWM_3_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger +#define PWM_3_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger +#define PWM_3_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_PP register. +// +//***************************************************************************** +#define PWM_PP_ONE 0x00000400 // One-Shot Mode +#define PWM_PP_EFAULT 0x00000200 // Extended Fault +#define PWM_PP_ESYNC 0x00000100 // Extended Synchronization +#define PWM_PP_FCNT_M 0x000000F0 // Fault Inputs (per PWM unit) +#define PWM_PP_GCNT_M 0x0000000F // Generators +#define PWM_PP_FCNT_S 4 +#define PWM_PP_GCNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_CTL register. +// +//***************************************************************************** +#define QEI_CTL_FILTCNT_M 0x000F0000 // Input Filter Prescale Count +#define QEI_CTL_FILTEN 0x00002000 // Enable Input Filter +#define QEI_CTL_STALLEN 0x00001000 // Stall QEI +#define QEI_CTL_INVI 0x00000800 // Invert Index Pulse +#define QEI_CTL_INVB 0x00000400 // Invert PhB +#define QEI_CTL_INVA 0x00000200 // Invert PhA +#define QEI_CTL_VELDIV_M 0x000001C0 // Predivide Velocity +#define QEI_CTL_VELDIV_1 0x00000000 // QEI clock /1 +#define QEI_CTL_VELDIV_2 0x00000040 // QEI clock /2 +#define QEI_CTL_VELDIV_4 0x00000080 // QEI clock /4 +#define QEI_CTL_VELDIV_8 0x000000C0 // QEI clock /8 +#define QEI_CTL_VELDIV_16 0x00000100 // QEI clock /16 +#define QEI_CTL_VELDIV_32 0x00000140 // QEI clock /32 +#define QEI_CTL_VELDIV_64 0x00000180 // QEI clock /64 +#define QEI_CTL_VELDIV_128 0x000001C0 // QEI clock /128 +#define QEI_CTL_VELEN 0x00000020 // Capture Velocity +#define QEI_CTL_RESMODE 0x00000010 // Reset Mode +#define QEI_CTL_CAPMODE 0x00000008 // Capture Mode +#define QEI_CTL_SIGMODE 0x00000004 // Signal Mode +#define QEI_CTL_SWAP 0x00000002 // Swap Signals +#define QEI_CTL_ENABLE 0x00000001 // Enable QEI +#define QEI_CTL_FILTCNT_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_STAT register. +// +//***************************************************************************** +#define QEI_STAT_DIRECTION 0x00000002 // Direction of Rotation +#define QEI_STAT_ERROR 0x00000001 // Error Detected + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_POS register. +// +//***************************************************************************** +#define QEI_POS_M 0xFFFFFFFF // Current Position Integrator + // Value +#define QEI_POS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_MAXPOS register. +// +//***************************************************************************** +#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum Position Integrator + // Value +#define QEI_MAXPOS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_LOAD register. +// +//***************************************************************************** +#define QEI_LOAD_M 0xFFFFFFFF // Velocity Timer Load Value +#define QEI_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_TIME register. +// +//***************************************************************************** +#define QEI_TIME_M 0xFFFFFFFF // Velocity Timer Current Value +#define QEI_TIME_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_COUNT register. +// +//***************************************************************************** +#define QEI_COUNT_M 0xFFFFFFFF // Velocity Pulse Count +#define QEI_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_SPEED register. +// +//***************************************************************************** +#define QEI_SPEED_M 0xFFFFFFFF // Velocity +#define QEI_SPEED_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_INTEN register. +// +//***************************************************************************** +#define QEI_INTEN_ERROR 0x00000008 // Phase Error Interrupt Enable +#define QEI_INTEN_DIR 0x00000004 // Direction Change Interrupt + // Enable +#define QEI_INTEN_TIMER 0x00000002 // Timer Expires Interrupt Enable +#define QEI_INTEN_INDEX 0x00000001 // Index Pulse Detected Interrupt + // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_RIS register. +// +//***************************************************************************** +#define QEI_RIS_ERROR 0x00000008 // Phase Error Detected +#define QEI_RIS_DIR 0x00000004 // Direction Change Detected +#define QEI_RIS_TIMER 0x00000002 // Velocity Timer Expired +#define QEI_RIS_INDEX 0x00000001 // Index Pulse Asserted + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_ISC register. +// +//***************************************************************************** +#define QEI_ISC_ERROR 0x00000008 // Phase Error Interrupt +#define QEI_ISC_DIR 0x00000004 // Direction Change Interrupt +#define QEI_ISC_TIMER 0x00000002 // Velocity Timer Expired Interrupt +#define QEI_ISC_INDEX 0x00000001 // Index Pulse Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_CFG register. +// +//***************************************************************************** +#define TIMER_CFG_M 0x00000007 // GPTM Configuration +#define TIMER_CFG_32_BIT_TIMER 0x00000000 // For a 16/32-bit timer, this + // value selects the 32-bit timer + // configuration +#define TIMER_CFG_32_BIT_RTC 0x00000001 // For a 16/32-bit timer, this + // value selects the 32-bit + // real-time clock (RTC) counter + // configuration +#define TIMER_CFG_16_BIT 0x00000004 // For a 16/32-bit timer, this + // value selects the 16-bit timer + // configuration + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAMR register. +// +//***************************************************************************** +#define TIMER_TAMR_TAPLO 0x00000800 // GPTM Timer A PWM Legacy + // Operation +#define TIMER_TAMR_TAMRSU 0x00000400 // GPTM Timer A Match Register + // Update +#define TIMER_TAMR_TAPWMIE 0x00000200 // GPTM Timer A PWM Interrupt + // Enable +#define TIMER_TAMR_TAILD 0x00000100 // GPTM Timer A Interval Load Write +#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode +#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger +#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt + // Enable +#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction +#define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode + // Select +#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode +#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode +#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode +#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode +#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBMR register. +// +//***************************************************************************** +#define TIMER_TBMR_TBPLO 0x00000800 // GPTM Timer B PWM Legacy + // Operation +#define TIMER_TBMR_TBMRSU 0x00000400 // GPTM Timer B Match Register + // Update +#define TIMER_TBMR_TBPWMIE 0x00000200 // GPTM Timer B PWM Interrupt + // Enable +#define TIMER_TBMR_TBILD 0x00000100 // GPTM Timer B Interval Load Write +#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode +#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger +#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt + // Enable +#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction +#define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode + // Select +#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode +#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode +#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode +#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode +#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_CTL register. +// +//***************************************************************************** +#define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level +#define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger + // Enable +#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode +#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge +#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge +#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges +#define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable +#define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable +#define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level +#define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger + // Enable +#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Stall Enable +#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode +#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge +#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge +#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges +#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable +#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_SYNC register. +// +//***************************************************************************** +#define TIMER_SYNC_SYNCWT5_M 0x00C00000 // Synchronize GPTM 32/64-Bit Timer + // 5 +#define TIMER_SYNC_SYNCWT5_NONE 0x00000000 // GPTM 32/64-Bit Timer 5 is not + // affected +#define TIMER_SYNC_SYNCWT5_TA 0x00400000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 5 is + // triggered +#define TIMER_SYNC_SYNCWT5_TB 0x00800000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 5 is + // triggered +#define TIMER_SYNC_SYNCWT5_TATB 0x00C00000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 5 is triggered +#define TIMER_SYNC_SYNCWT4_M 0x00300000 // Synchronize GPTM 32/64-Bit Timer + // 4 +#define TIMER_SYNC_SYNCWT4_NONE 0x00000000 // GPTM 32/64-Bit Timer 4 is not + // affected +#define TIMER_SYNC_SYNCWT4_TA 0x00100000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 4 is + // triggered +#define TIMER_SYNC_SYNCWT4_TB 0x00200000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 4 is + // triggered +#define TIMER_SYNC_SYNCWT4_TATB 0x00300000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 4 is triggered +#define TIMER_SYNC_SYNCWT3_M 0x000C0000 // Synchronize GPTM 32/64-Bit Timer + // 3 +#define TIMER_SYNC_SYNCWT3_NONE 0x00000000 // GPTM 32/64-Bit Timer 3 is not + // affected +#define TIMER_SYNC_SYNCWT3_TA 0x00040000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 3 is + // triggered +#define TIMER_SYNC_SYNCWT3_TB 0x00080000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 3 is + // triggered +#define TIMER_SYNC_SYNCWT3_TATB 0x000C0000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 3 is triggered +#define TIMER_SYNC_SYNCWT2_M 0x00030000 // Synchronize GPTM 32/64-Bit Timer + // 2 +#define TIMER_SYNC_SYNCWT2_NONE 0x00000000 // GPTM 32/64-Bit Timer 2 is not + // affected +#define TIMER_SYNC_SYNCWT2_TA 0x00010000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 2 is + // triggered +#define TIMER_SYNC_SYNCWT2_TB 0x00020000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 2 is + // triggered +#define TIMER_SYNC_SYNCWT2_TATB 0x00030000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 2 is triggered +#define TIMER_SYNC_SYNCWT1_M 0x0000C000 // Synchronize GPTM 32/64-Bit Timer + // 1 +#define TIMER_SYNC_SYNCWT1_NONE 0x00000000 // GPTM 32/64-Bit Timer 1 is not + // affected +#define TIMER_SYNC_SYNCWT1_TA 0x00004000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 1 is + // triggered +#define TIMER_SYNC_SYNCWT1_TB 0x00008000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 1 is + // triggered +#define TIMER_SYNC_SYNCWT1_TATB 0x0000C000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 1 is triggered +#define TIMER_SYNC_SYNCWT0_M 0x00003000 // Synchronize GPTM 32/64-Bit Timer + // 0 +#define TIMER_SYNC_SYNCWT0_NONE 0x00000000 // GPTM 32/64-Bit Timer 0 is not + // affected +#define TIMER_SYNC_SYNCWT0_TA 0x00001000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 0 is + // triggered +#define TIMER_SYNC_SYNCWT0_TB 0x00002000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 0 is + // triggered +#define TIMER_SYNC_SYNCWT0_TATB 0x00003000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 0 is triggered +#define TIMER_SYNC_SYNCT5_M 0x00000C00 // Synchronize GPTM Timer 5 +#define TIMER_SYNC_SYNCT5_NONE 0x00000000 // GPTM5 is not affected +#define TIMER_SYNC_SYNCT5_TA 0x00000400 // A timeout event for Timer A of + // GPTM5 is triggered +#define TIMER_SYNC_SYNCT5_TB 0x00000800 // A timeout event for Timer B of + // GPTM5 is triggered +#define TIMER_SYNC_SYNCT5_TATB 0x00000C00 // A timeout event for both Timer A + // and Timer B of GPTM5 is + // triggered +#define TIMER_SYNC_SYNCT4_M 0x00000300 // Synchronize GPTM Timer 4 +#define TIMER_SYNC_SYNCT4_NONE 0x00000000 // GPTM4 is not affected +#define TIMER_SYNC_SYNCT4_TA 0x00000100 // A timeout event for Timer A of + // GPTM4 is triggered +#define TIMER_SYNC_SYNCT4_TB 0x00000200 // A timeout event for Timer B of + // GPTM4 is triggered +#define TIMER_SYNC_SYNCT4_TATB 0x00000300 // A timeout event for both Timer A + // and Timer B of GPTM4 is + // triggered +#define TIMER_SYNC_SYNCT3_M 0x000000C0 // Synchronize GPTM Timer 3 +#define TIMER_SYNC_SYNCT3_NONE 0x00000000 // GPTM3 is not affected +#define TIMER_SYNC_SYNCT3_TA 0x00000040 // A timeout event for Timer A of + // GPTM3 is triggered +#define TIMER_SYNC_SYNCT3_TB 0x00000080 // A timeout event for Timer B of + // GPTM3 is triggered +#define TIMER_SYNC_SYNCT3_TATB 0x000000C0 // A timeout event for both Timer A + // and Timer B of GPTM3 is + // triggered +#define TIMER_SYNC_SYNCT2_M 0x00000030 // Synchronize GPTM Timer 2 +#define TIMER_SYNC_SYNCT2_NONE 0x00000000 // GPTM2 is not affected +#define TIMER_SYNC_SYNCT2_TA 0x00000010 // A timeout event for Timer A of + // GPTM2 is triggered +#define TIMER_SYNC_SYNCT2_TB 0x00000020 // A timeout event for Timer B of + // GPTM2 is triggered +#define TIMER_SYNC_SYNCT2_TATB 0x00000030 // A timeout event for both Timer A + // and Timer B of GPTM2 is + // triggered +#define TIMER_SYNC_SYNCT1_M 0x0000000C // Synchronize GPTM Timer 1 +#define TIMER_SYNC_SYNCT1_NONE 0x00000000 // GPTM1 is not affected +#define TIMER_SYNC_SYNCT1_TA 0x00000004 // A timeout event for Timer A of + // GPTM1 is triggered +#define TIMER_SYNC_SYNCT1_TB 0x00000008 // A timeout event for Timer B of + // GPTM1 is triggered +#define TIMER_SYNC_SYNCT1_TATB 0x0000000C // A timeout event for both Timer A + // and Timer B of GPTM1 is + // triggered +#define TIMER_SYNC_SYNCT0_M 0x00000003 // Synchronize GPTM Timer 0 +#define TIMER_SYNC_SYNCT0_NONE 0x00000000 // GPTM0 is not affected +#define TIMER_SYNC_SYNCT0_TA 0x00000001 // A timeout event for Timer A of + // GPTM0 is triggered +#define TIMER_SYNC_SYNCT0_TB 0x00000002 // A timeout event for Timer B of + // GPTM0 is triggered +#define TIMER_SYNC_SYNCT0_TATB 0x00000003 // A timeout event for both Timer A + // and Timer B of GPTM0 is + // triggered + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_IMR register. +// +//***************************************************************************** +#define TIMER_IMR_WUEIM 0x00010000 // 32/64-Bit Wide GPTM Write Update + // Error Interrupt Mask +#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Match Interrupt + // Mask +#define TIMER_IMR_CBEIM 0x00000400 // GPTM Timer B Capture Mode Event + // Interrupt Mask +#define TIMER_IMR_CBMIM 0x00000200 // GPTM Timer B Capture Mode Match + // Interrupt Mask +#define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt + // Mask +#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Match Interrupt + // Mask +#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask +#define TIMER_IMR_CAEIM 0x00000004 // GPTM Timer A Capture Mode Event + // Interrupt Mask +#define TIMER_IMR_CAMIM 0x00000002 // GPTM Timer A Capture Mode Match + // Interrupt Mask +#define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt + // Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_RIS register. +// +//***************************************************************************** +#define TIMER_RIS_WUERIS 0x00010000 // 32/64-Bit Wide GPTM Write Update + // Error Raw Interrupt Status +#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Match Raw Interrupt +#define TIMER_RIS_CBERIS 0x00000400 // GPTM Timer B Capture Mode Event + // Raw Interrupt +#define TIMER_RIS_CBMRIS 0x00000200 // GPTM Timer B Capture Mode Match + // Raw Interrupt +#define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw + // Interrupt +#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Match Raw Interrupt +#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt +#define TIMER_RIS_CAERIS 0x00000004 // GPTM Timer A Capture Mode Event + // Raw Interrupt +#define TIMER_RIS_CAMRIS 0x00000002 // GPTM Timer A Capture Mode Match + // Raw Interrupt +#define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw + // Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_MIS register. +// +//***************************************************************************** +#define TIMER_MIS_WUEMIS 0x00010000 // 32/64-Bit Wide GPTM Write Update + // Error Masked Interrupt Status +#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Match Masked + // Interrupt +#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Timer B Capture Mode Event + // Masked Interrupt +#define TIMER_MIS_CBMMIS 0x00000200 // GPTM Timer B Capture Mode Match + // Masked Interrupt +#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked + // Interrupt +#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Match Masked + // Interrupt +#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt +#define TIMER_MIS_CAEMIS 0x00000004 // GPTM Timer A Capture Mode Event + // Masked Interrupt +#define TIMER_MIS_CAMMIS 0x00000002 // GPTM Timer A Capture Mode Match + // Masked Interrupt +#define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked + // Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_ICR register. +// +//***************************************************************************** +#define TIMER_ICR_WUECINT 0x00010000 // 32/64-Bit Wide GPTM Write Update + // Error Interrupt Clear +#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Match Interrupt + // Clear +#define TIMER_ICR_CBECINT 0x00000400 // GPTM Timer B Capture Mode Event + // Interrupt Clear +#define TIMER_ICR_CBMCINT 0x00000200 // GPTM Timer B Capture Mode Match + // Interrupt Clear +#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt + // Clear +#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Match Interrupt + // Clear +#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear +#define TIMER_ICR_CAECINT 0x00000004 // GPTM Timer A Capture Mode Event + // Interrupt Clear +#define TIMER_ICR_CAMCINT 0x00000002 // GPTM Timer A Capture Mode Match + // Interrupt Clear +#define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw + // Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAILR register. +// +//***************************************************************************** +#define TIMER_TAILR_M 0xFFFFFFFF // GPTM Timer A Interval Load + // Register +#define TIMER_TAILR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBILR register. +// +//***************************************************************************** +#define TIMER_TBILR_M 0xFFFFFFFF // GPTM Timer B Interval Load + // Register +#define TIMER_TBILR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAMATCHR +// register. +// +//***************************************************************************** +#define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF // GPTM Timer A Match Register +#define TIMER_TAMATCHR_TAMR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBMATCHR +// register. +// +//***************************************************************************** +#define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF // GPTM Timer B Match Register +#define TIMER_TBMATCHR_TBMR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPR register. +// +//***************************************************************************** +#define TIMER_TAPR_TAPSRH_M 0x0000FF00 // GPTM Timer A Prescale High Byte +#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale +#define TIMER_TAPR_TAPSRH_S 8 +#define TIMER_TAPR_TAPSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPR register. +// +//***************************************************************************** +#define TIMER_TBPR_TBPSRH_M 0x0000FF00 // GPTM Timer B Prescale High Byte +#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale +#define TIMER_TBPR_TBPSRH_S 8 +#define TIMER_TBPR_TBPSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPMR register. +// +//***************************************************************************** +#define TIMER_TAPMR_TAPSMRH_M 0x0000FF00 // GPTM Timer A Prescale Match High + // Byte +#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match +#define TIMER_TAPMR_TAPSMRH_S 8 +#define TIMER_TAPMR_TAPSMR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPMR register. +// +//***************************************************************************** +#define TIMER_TBPMR_TBPSMRH_M 0x0000FF00 // GPTM Timer B Prescale Match High + // Byte +#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match +#define TIMER_TBPMR_TBPSMRH_S 8 +#define TIMER_TBPMR_TBPSMR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAR register. +// +//***************************************************************************** +#define TIMER_TAR_M 0xFFFFFFFF // GPTM Timer A Register +#define TIMER_TAR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBR register. +// +//***************************************************************************** +#define TIMER_TBR_M 0xFFFFFFFF // GPTM Timer B Register +#define TIMER_TBR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAV register. +// +//***************************************************************************** +#define TIMER_TAV_M 0xFFFFFFFF // GPTM Timer A Value +#define TIMER_TAV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBV register. +// +//***************************************************************************** +#define TIMER_TBV_M 0xFFFFFFFF // GPTM Timer B Value +#define TIMER_TBV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_RTCPD register. +// +//***************************************************************************** +#define TIMER_RTCPD_RTCPD_M 0x0000FFFF // RTC Predivide Counter Value +#define TIMER_RTCPD_RTCPD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPS register. +// +//***************************************************************************** +#define TIMER_TAPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Snapshot +#define TIMER_TAPS_PSS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPS register. +// +//***************************************************************************** +#define TIMER_TBPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Value +#define TIMER_TBPS_PSS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPV register. +// +//***************************************************************************** +#define TIMER_TAPV_PSV_M 0x0000FFFF // GPTM Timer A Prescaler Value +#define TIMER_TAPV_PSV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPV register. +// +//***************************************************************************** +#define TIMER_TBPV_PSV_M 0x0000FFFF // GPTM Timer B Prescaler Value +#define TIMER_TBPV_PSV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_PP register. +// +//***************************************************************************** +#define TIMER_PP_SIZE_M 0x0000000F // Count Size +#define TIMER_PP_SIZE_16 0x00000000 // Timer A and Timer B counters are + // 16 bits each with an 8-bit + // prescale counter +#define TIMER_PP_SIZE_32 0x00000001 // Timer A and Timer B counters are + // 32 bits each with a 16-bit + // prescale counter + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_ACTSS register. +// +//***************************************************************************** +#define ADC_ACTSS_BUSY 0x00010000 // ADC Busy +#define ADC_ACTSS_ASEN3 0x00000008 // ADC SS3 Enable +#define ADC_ACTSS_ASEN2 0x00000004 // ADC SS2 Enable +#define ADC_ACTSS_ASEN1 0x00000002 // ADC SS1 Enable +#define ADC_ACTSS_ASEN0 0x00000001 // ADC SS0 Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_RIS register. +// +//***************************************************************************** +#define ADC_RIS_INRDC 0x00010000 // Digital Comparator Raw Interrupt + // Status +#define ADC_RIS_INR3 0x00000008 // SS3 Raw Interrupt Status +#define ADC_RIS_INR2 0x00000004 // SS2 Raw Interrupt Status +#define ADC_RIS_INR1 0x00000002 // SS1 Raw Interrupt Status +#define ADC_RIS_INR0 0x00000001 // SS0 Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_IM register. +// +//***************************************************************************** +#define ADC_IM_DCONSS3 0x00080000 // Digital Comparator Interrupt on + // SS3 +#define ADC_IM_DCONSS2 0x00040000 // Digital Comparator Interrupt on + // SS2 +#define ADC_IM_DCONSS1 0x00020000 // Digital Comparator Interrupt on + // SS1 +#define ADC_IM_DCONSS0 0x00010000 // Digital Comparator Interrupt on + // SS0 +#define ADC_IM_MASK3 0x00000008 // SS3 Interrupt Mask +#define ADC_IM_MASK2 0x00000004 // SS2 Interrupt Mask +#define ADC_IM_MASK1 0x00000002 // SS1 Interrupt Mask +#define ADC_IM_MASK0 0x00000001 // SS0 Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_ISC register. +// +//***************************************************************************** +#define ADC_ISC_DCINSS3 0x00080000 // Digital Comparator Interrupt + // Status on SS3 +#define ADC_ISC_DCINSS2 0x00040000 // Digital Comparator Interrupt + // Status on SS2 +#define ADC_ISC_DCINSS1 0x00020000 // Digital Comparator Interrupt + // Status on SS1 +#define ADC_ISC_DCINSS0 0x00010000 // Digital Comparator Interrupt + // Status on SS0 +#define ADC_ISC_IN3 0x00000008 // SS3 Interrupt Status and Clear +#define ADC_ISC_IN2 0x00000004 // SS2 Interrupt Status and Clear +#define ADC_ISC_IN1 0x00000002 // SS1 Interrupt Status and Clear +#define ADC_ISC_IN0 0x00000001 // SS0 Interrupt Status and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_OSTAT register. +// +//***************************************************************************** +#define ADC_OSTAT_OV3 0x00000008 // SS3 FIFO Overflow +#define ADC_OSTAT_OV2 0x00000004 // SS2 FIFO Overflow +#define ADC_OSTAT_OV1 0x00000002 // SS1 FIFO Overflow +#define ADC_OSTAT_OV0 0x00000001 // SS0 FIFO Overflow + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_EMUX register. +// +//***************************************************************************** +#define ADC_EMUX_EM3_M 0x0000F000 // SS3 Trigger Select +#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor (default) +#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog Comparator 0 +#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog Comparator 1 +#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External (GPIO Pins) +#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer +#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM generator 0 +#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM generator 1 +#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM generator 2 +#define ADC_EMUX_EM3_PWM3 0x00009000 // PWM generator 3 +#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always (continuously sample) +#define ADC_EMUX_EM2_M 0x00000F00 // SS2 Trigger Select +#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor (default) +#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog Comparator 0 +#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog Comparator 1 +#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External (GPIO Pins) +#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer +#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM generator 0 +#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM generator 1 +#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM generator 2 +#define ADC_EMUX_EM2_PWM3 0x00000900 // PWM generator 3 +#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always (continuously sample) +#define ADC_EMUX_EM1_M 0x000000F0 // SS1 Trigger Select +#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor (default) +#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog Comparator 0 +#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog Comparator 1 +#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External (GPIO Pins) +#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer +#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM generator 0 +#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM generator 1 +#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM generator 2 +#define ADC_EMUX_EM1_PWM3 0x00000090 // PWM generator 3 +#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always (continuously sample) +#define ADC_EMUX_EM0_M 0x0000000F // SS0 Trigger Select +#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor (default) +#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog Comparator 0 +#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog Comparator 1 +#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External (GPIO Pins) +#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer +#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM generator 0 +#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM generator 1 +#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM generator 2 +#define ADC_EMUX_EM0_PWM3 0x00000009 // PWM generator 3 +#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always (continuously sample) + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_USTAT register. +// +//***************************************************************************** +#define ADC_USTAT_UV3 0x00000008 // SS3 FIFO Underflow +#define ADC_USTAT_UV2 0x00000004 // SS2 FIFO Underflow +#define ADC_USTAT_UV1 0x00000002 // SS1 FIFO Underflow +#define ADC_USTAT_UV0 0x00000001 // SS0 FIFO Underflow + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_TSSEL register. +// +//***************************************************************************** +#define ADC_TSSEL_PS3_M 0x30000000 // Generator 3 PWM Module Trigger + // Select +#define ADC_TSSEL_PS3_0 0x00000000 // Use Generator 3 (and its + // trigger) in PWM module 0 +#define ADC_TSSEL_PS3_1 0x10000000 // Use Generator 3 (and its + // trigger) in PWM module 1 +#define ADC_TSSEL_PS2_M 0x00300000 // Generator 2 PWM Module Trigger + // Select +#define ADC_TSSEL_PS2_0 0x00000000 // Use Generator 2 (and its + // trigger) in PWM module 0 +#define ADC_TSSEL_PS2_1 0x00100000 // Use Generator 2 (and its + // trigger) in PWM module 1 +#define ADC_TSSEL_PS1_M 0x00003000 // Generator 1 PWM Module Trigger + // Select +#define ADC_TSSEL_PS1_0 0x00000000 // Use Generator 1 (and its + // trigger) in PWM module 0 +#define ADC_TSSEL_PS1_1 0x00001000 // Use Generator 1 (and its + // trigger) in PWM module 1 +#define ADC_TSSEL_PS0_M 0x00000030 // Generator 0 PWM Module Trigger + // Select +#define ADC_TSSEL_PS0_0 0x00000000 // Use Generator 0 (and its + // trigger) in PWM module 0 +#define ADC_TSSEL_PS0_1 0x00000010 // Use Generator 0 (and its + // trigger) in PWM module 1 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSPRI register. +// +//***************************************************************************** +#define ADC_SSPRI_SS3_M 0x00003000 // SS3 Priority +#define ADC_SSPRI_SS2_M 0x00000300 // SS2 Priority +#define ADC_SSPRI_SS1_M 0x00000030 // SS1 Priority +#define ADC_SSPRI_SS0_M 0x00000003 // SS0 Priority + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SPC register. +// +//***************************************************************************** +#define ADC_SPC_PHASE_M 0x0000000F // Phase Difference +#define ADC_SPC_PHASE_0 0x00000000 // ADC sample lags by 0.0 +#define ADC_SPC_PHASE_22_5 0x00000001 // ADC sample lags by 22.5 +#define ADC_SPC_PHASE_45 0x00000002 // ADC sample lags by 45.0 +#define ADC_SPC_PHASE_67_5 0x00000003 // ADC sample lags by 67.5 +#define ADC_SPC_PHASE_90 0x00000004 // ADC sample lags by 90.0 +#define ADC_SPC_PHASE_112_5 0x00000005 // ADC sample lags by 112.5 +#define ADC_SPC_PHASE_135 0x00000006 // ADC sample lags by 135.0 +#define ADC_SPC_PHASE_157_5 0x00000007 // ADC sample lags by 157.5 +#define ADC_SPC_PHASE_180 0x00000008 // ADC sample lags by 180.0 +#define ADC_SPC_PHASE_202_5 0x00000009 // ADC sample lags by 202.5 +#define ADC_SPC_PHASE_225 0x0000000A // ADC sample lags by 225.0 +#define ADC_SPC_PHASE_247_5 0x0000000B // ADC sample lags by 247.5 +#define ADC_SPC_PHASE_270 0x0000000C // ADC sample lags by 270.0 +#define ADC_SPC_PHASE_292_5 0x0000000D // ADC sample lags by 292.5 +#define ADC_SPC_PHASE_315 0x0000000E // ADC sample lags by 315.0 +#define ADC_SPC_PHASE_337_5 0x0000000F // ADC sample lags by 337.5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_PSSI register. +// +//***************************************************************************** +#define ADC_PSSI_GSYNC 0x80000000 // Global Synchronize +#define ADC_PSSI_SYNCWAIT 0x08000000 // Synchronize Wait +#define ADC_PSSI_SS3 0x00000008 // SS3 Initiate +#define ADC_PSSI_SS2 0x00000004 // SS2 Initiate +#define ADC_PSSI_SS1 0x00000002 // SS1 Initiate +#define ADC_PSSI_SS0 0x00000001 // SS0 Initiate + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SAC register. +// +//***************************************************************************** +#define ADC_SAC_AVG_M 0x00000007 // Hardware Averaging Control +#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling +#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling +#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling +#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling +#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling +#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling +#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCISC register. +// +//***************************************************************************** +#define ADC_DCISC_DCINT7 0x00000080 // Digital Comparator 7 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT6 0x00000040 // Digital Comparator 6 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT5 0x00000020 // Digital Comparator 5 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT4 0x00000010 // Digital Comparator 4 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT3 0x00000008 // Digital Comparator 3 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT2 0x00000004 // Digital Comparator 2 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT1 0x00000002 // Digital Comparator 1 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT0 0x00000001 // Digital Comparator 0 Interrupt + // Status and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_CTL register. +// +//***************************************************************************** +#define ADC_CTL_VREF_M 0x00000001 // Voltage Reference Select +#define ADC_CTL_VREF_INTERNAL 0x00000000 // VDDA and GNDA are the voltage + // references + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX0 register. +// +//***************************************************************************** +#define ADC_SSMUX0_MUX7_M 0xF0000000 // 8th Sample Input Select +#define ADC_SSMUX0_MUX6_M 0x0F000000 // 7th Sample Input Select +#define ADC_SSMUX0_MUX5_M 0x00F00000 // 6th Sample Input Select +#define ADC_SSMUX0_MUX4_M 0x000F0000 // 5th Sample Input Select +#define ADC_SSMUX0_MUX3_M 0x0000F000 // 4th Sample Input Select +#define ADC_SSMUX0_MUX2_M 0x00000F00 // 3rd Sample Input Select +#define ADC_SSMUX0_MUX1_M 0x000000F0 // 2nd Sample Input Select +#define ADC_SSMUX0_MUX0_M 0x0000000F // 1st Sample Input Select +#define ADC_SSMUX0_MUX7_S 28 +#define ADC_SSMUX0_MUX6_S 24 +#define ADC_SSMUX0_MUX5_S 20 +#define ADC_SSMUX0_MUX4_S 16 +#define ADC_SSMUX0_MUX3_S 12 +#define ADC_SSMUX0_MUX2_S 8 +#define ADC_SSMUX0_MUX1_S 4 +#define ADC_SSMUX0_MUX0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL0 register. +// +//***************************************************************************** +#define ADC_SSCTL0_TS7 0x80000000 // 8th Sample Temp Sensor Select +#define ADC_SSCTL0_IE7 0x40000000 // 8th Sample Interrupt Enable +#define ADC_SSCTL0_END7 0x20000000 // 8th Sample is End of Sequence +#define ADC_SSCTL0_D7 0x10000000 // 8th Sample Differential Input + // Select +#define ADC_SSCTL0_TS6 0x08000000 // 7th Sample Temp Sensor Select +#define ADC_SSCTL0_IE6 0x04000000 // 7th Sample Interrupt Enable +#define ADC_SSCTL0_END6 0x02000000 // 7th Sample is End of Sequence +#define ADC_SSCTL0_D6 0x01000000 // 7th Sample Differential Input + // Select +#define ADC_SSCTL0_TS5 0x00800000 // 6th Sample Temp Sensor Select +#define ADC_SSCTL0_IE5 0x00400000 // 6th Sample Interrupt Enable +#define ADC_SSCTL0_END5 0x00200000 // 6th Sample is End of Sequence +#define ADC_SSCTL0_D5 0x00100000 // 6th Sample Differential Input + // Select +#define ADC_SSCTL0_TS4 0x00080000 // 5th Sample Temp Sensor Select +#define ADC_SSCTL0_IE4 0x00040000 // 5th Sample Interrupt Enable +#define ADC_SSCTL0_END4 0x00020000 // 5th Sample is End of Sequence +#define ADC_SSCTL0_D4 0x00010000 // 5th Sample Differential Input + // Select +#define ADC_SSCTL0_TS3 0x00008000 // 4th Sample Temp Sensor Select +#define ADC_SSCTL0_IE3 0x00004000 // 4th Sample Interrupt Enable +#define ADC_SSCTL0_END3 0x00002000 // 4th Sample is End of Sequence +#define ADC_SSCTL0_D3 0x00001000 // 4th Sample Differential Input + // Select +#define ADC_SSCTL0_TS2 0x00000800 // 3rd Sample Temp Sensor Select +#define ADC_SSCTL0_IE2 0x00000400 // 3rd Sample Interrupt Enable +#define ADC_SSCTL0_END2 0x00000200 // 3rd Sample is End of Sequence +#define ADC_SSCTL0_D2 0x00000100 // 3rd Sample Differential Input + // Select +#define ADC_SSCTL0_TS1 0x00000080 // 2nd Sample Temp Sensor Select +#define ADC_SSCTL0_IE1 0x00000040 // 2nd Sample Interrupt Enable +#define ADC_SSCTL0_END1 0x00000020 // 2nd Sample is End of Sequence +#define ADC_SSCTL0_D1 0x00000010 // 2nd Sample Differential Input + // Select +#define ADC_SSCTL0_TS0 0x00000008 // 1st Sample Temp Sensor Select +#define ADC_SSCTL0_IE0 0x00000004 // 1st Sample Interrupt Enable +#define ADC_SSCTL0_END0 0x00000002 // 1st Sample is End of Sequence +#define ADC_SSCTL0_D0 0x00000001 // 1st Sample Differential Input + // Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO0 register. +// +//***************************************************************************** +#define ADC_SSFIFO0_DATA_M 0x00000FFF // Conversion Result Data +#define ADC_SSFIFO0_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register. +// +//***************************************************************************** +#define ADC_SSFSTAT0_FULL 0x00001000 // FIFO Full +#define ADC_SSFSTAT0_EMPTY 0x00000100 // FIFO Empty +#define ADC_SSFSTAT0_HPTR_M 0x000000F0 // FIFO Head Pointer +#define ADC_SSFSTAT0_TPTR_M 0x0000000F // FIFO Tail Pointer +#define ADC_SSFSTAT0_HPTR_S 4 +#define ADC_SSFSTAT0_TPTR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSOP0 register. +// +//***************************************************************************** +#define ADC_SSOP0_S7DCOP 0x10000000 // Sample 7 Digital Comparator + // Operation +#define ADC_SSOP0_S6DCOP 0x01000000 // Sample 6 Digital Comparator + // Operation +#define ADC_SSOP0_S5DCOP 0x00100000 // Sample 5 Digital Comparator + // Operation +#define ADC_SSOP0_S4DCOP 0x00010000 // Sample 4 Digital Comparator + // Operation +#define ADC_SSOP0_S3DCOP 0x00001000 // Sample 3 Digital Comparator + // Operation +#define ADC_SSOP0_S2DCOP 0x00000100 // Sample 2 Digital Comparator + // Operation +#define ADC_SSOP0_S1DCOP 0x00000010 // Sample 1 Digital Comparator + // Operation +#define ADC_SSOP0_S0DCOP 0x00000001 // Sample 0 Digital Comparator + // Operation + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSDC0 register. +// +//***************************************************************************** +#define ADC_SSDC0_S7DCSEL_M 0xF0000000 // Sample 7 Digital Comparator + // Select +#define ADC_SSDC0_S6DCSEL_M 0x0F000000 // Sample 6 Digital Comparator + // Select +#define ADC_SSDC0_S5DCSEL_M 0x00F00000 // Sample 5 Digital Comparator + // Select +#define ADC_SSDC0_S4DCSEL_M 0x000F0000 // Sample 4 Digital Comparator + // Select +#define ADC_SSDC0_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator + // Select +#define ADC_SSDC0_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator + // Select +#define ADC_SSDC0_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator + // Select +#define ADC_SSDC0_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator + // Select +#define ADC_SSDC0_S6DCSEL_S 24 +#define ADC_SSDC0_S5DCSEL_S 20 +#define ADC_SSDC0_S4DCSEL_S 16 +#define ADC_SSDC0_S3DCSEL_S 12 +#define ADC_SSDC0_S2DCSEL_S 8 +#define ADC_SSDC0_S1DCSEL_S 4 +#define ADC_SSDC0_S0DCSEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX1 register. +// +//***************************************************************************** +#define ADC_SSMUX1_MUX3_M 0x0000F000 // 4th Sample Input Select +#define ADC_SSMUX1_MUX2_M 0x00000F00 // 3rd Sample Input Select +#define ADC_SSMUX1_MUX1_M 0x000000F0 // 2nd Sample Input Select +#define ADC_SSMUX1_MUX0_M 0x0000000F // 1st Sample Input Select +#define ADC_SSMUX1_MUX3_S 12 +#define ADC_SSMUX1_MUX2_S 8 +#define ADC_SSMUX1_MUX1_S 4 +#define ADC_SSMUX1_MUX0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL1 register. +// +//***************************************************************************** +#define ADC_SSCTL1_TS3 0x00008000 // 4th Sample Temp Sensor Select +#define ADC_SSCTL1_IE3 0x00004000 // 4th Sample Interrupt Enable +#define ADC_SSCTL1_END3 0x00002000 // 4th Sample is End of Sequence +#define ADC_SSCTL1_D3 0x00001000 // 4th Sample Differential Input + // Select +#define ADC_SSCTL1_TS2 0x00000800 // 3rd Sample Temp Sensor Select +#define ADC_SSCTL1_IE2 0x00000400 // 3rd Sample Interrupt Enable +#define ADC_SSCTL1_END2 0x00000200 // 3rd Sample is End of Sequence +#define ADC_SSCTL1_D2 0x00000100 // 3rd Sample Differential Input + // Select +#define ADC_SSCTL1_TS1 0x00000080 // 2nd Sample Temp Sensor Select +#define ADC_SSCTL1_IE1 0x00000040 // 2nd Sample Interrupt Enable +#define ADC_SSCTL1_END1 0x00000020 // 2nd Sample is End of Sequence +#define ADC_SSCTL1_D1 0x00000010 // 2nd Sample Differential Input + // Select +#define ADC_SSCTL1_TS0 0x00000008 // 1st Sample Temp Sensor Select +#define ADC_SSCTL1_IE0 0x00000004 // 1st Sample Interrupt Enable +#define ADC_SSCTL1_END0 0x00000002 // 1st Sample is End of Sequence +#define ADC_SSCTL1_D0 0x00000001 // 1st Sample Differential Input + // Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO1 register. +// +//***************************************************************************** +#define ADC_SSFIFO1_DATA_M 0x00000FFF // Conversion Result Data +#define ADC_SSFIFO1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register. +// +//***************************************************************************** +#define ADC_SSFSTAT1_FULL 0x00001000 // FIFO Full +#define ADC_SSFSTAT1_EMPTY 0x00000100 // FIFO Empty +#define ADC_SSFSTAT1_HPTR_M 0x000000F0 // FIFO Head Pointer +#define ADC_SSFSTAT1_TPTR_M 0x0000000F // FIFO Tail Pointer +#define ADC_SSFSTAT1_HPTR_S 4 +#define ADC_SSFSTAT1_TPTR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSOP1 register. +// +//***************************************************************************** +#define ADC_SSOP1_S3DCOP 0x00001000 // Sample 3 Digital Comparator + // Operation +#define ADC_SSOP1_S2DCOP 0x00000100 // Sample 2 Digital Comparator + // Operation +#define ADC_SSOP1_S1DCOP 0x00000010 // Sample 1 Digital Comparator + // Operation +#define ADC_SSOP1_S0DCOP 0x00000001 // Sample 0 Digital Comparator + // Operation + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSDC1 register. +// +//***************************************************************************** +#define ADC_SSDC1_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator + // Select +#define ADC_SSDC1_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator + // Select +#define ADC_SSDC1_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator + // Select +#define ADC_SSDC1_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator + // Select +#define ADC_SSDC1_S2DCSEL_S 8 +#define ADC_SSDC1_S1DCSEL_S 4 +#define ADC_SSDC1_S0DCSEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX2 register. +// +//***************************************************************************** +#define ADC_SSMUX2_MUX3_M 0x0000F000 // 4th Sample Input Select +#define ADC_SSMUX2_MUX2_M 0x00000F00 // 3rd Sample Input Select +#define ADC_SSMUX2_MUX1_M 0x000000F0 // 2nd Sample Input Select +#define ADC_SSMUX2_MUX0_M 0x0000000F // 1st Sample Input Select +#define ADC_SSMUX2_MUX3_S 12 +#define ADC_SSMUX2_MUX2_S 8 +#define ADC_SSMUX2_MUX1_S 4 +#define ADC_SSMUX2_MUX0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL2 register. +// +//***************************************************************************** +#define ADC_SSCTL2_TS3 0x00008000 // 4th Sample Temp Sensor Select +#define ADC_SSCTL2_IE3 0x00004000 // 4th Sample Interrupt Enable +#define ADC_SSCTL2_END3 0x00002000 // 4th Sample is End of Sequence +#define ADC_SSCTL2_D3 0x00001000 // 4th Sample Differential Input + // Select +#define ADC_SSCTL2_TS2 0x00000800 // 3rd Sample Temp Sensor Select +#define ADC_SSCTL2_IE2 0x00000400 // 3rd Sample Interrupt Enable +#define ADC_SSCTL2_END2 0x00000200 // 3rd Sample is End of Sequence +#define ADC_SSCTL2_D2 0x00000100 // 3rd Sample Differential Input + // Select +#define ADC_SSCTL2_TS1 0x00000080 // 2nd Sample Temp Sensor Select +#define ADC_SSCTL2_IE1 0x00000040 // 2nd Sample Interrupt Enable +#define ADC_SSCTL2_END1 0x00000020 // 2nd Sample is End of Sequence +#define ADC_SSCTL2_D1 0x00000010 // 2nd Sample Differential Input + // Select +#define ADC_SSCTL2_TS0 0x00000008 // 1st Sample Temp Sensor Select +#define ADC_SSCTL2_IE0 0x00000004 // 1st Sample Interrupt Enable +#define ADC_SSCTL2_END0 0x00000002 // 1st Sample is End of Sequence +#define ADC_SSCTL2_D0 0x00000001 // 1st Sample Differential Input + // Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO2 register. +// +//***************************************************************************** +#define ADC_SSFIFO2_DATA_M 0x00000FFF // Conversion Result Data +#define ADC_SSFIFO2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register. +// +//***************************************************************************** +#define ADC_SSFSTAT2_FULL 0x00001000 // FIFO Full +#define ADC_SSFSTAT2_EMPTY 0x00000100 // FIFO Empty +#define ADC_SSFSTAT2_HPTR_M 0x000000F0 // FIFO Head Pointer +#define ADC_SSFSTAT2_TPTR_M 0x0000000F // FIFO Tail Pointer +#define ADC_SSFSTAT2_HPTR_S 4 +#define ADC_SSFSTAT2_TPTR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSOP2 register. +// +//***************************************************************************** +#define ADC_SSOP2_S3DCOP 0x00001000 // Sample 3 Digital Comparator + // Operation +#define ADC_SSOP2_S2DCOP 0x00000100 // Sample 2 Digital Comparator + // Operation +#define ADC_SSOP2_S1DCOP 0x00000010 // Sample 1 Digital Comparator + // Operation +#define ADC_SSOP2_S0DCOP 0x00000001 // Sample 0 Digital Comparator + // Operation + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSDC2 register. +// +//***************************************************************************** +#define ADC_SSDC2_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator + // Select +#define ADC_SSDC2_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator + // Select +#define ADC_SSDC2_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator + // Select +#define ADC_SSDC2_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator + // Select +#define ADC_SSDC2_S2DCSEL_S 8 +#define ADC_SSDC2_S1DCSEL_S 4 +#define ADC_SSDC2_S0DCSEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX3 register. +// +//***************************************************************************** +#define ADC_SSMUX3_MUX0_M 0x0000000F // 1st Sample Input Select +#define ADC_SSMUX3_MUX0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL3 register. +// +//***************************************************************************** +#define ADC_SSCTL3_TS0 0x00000008 // 1st Sample Temp Sensor Select +#define ADC_SSCTL3_IE0 0x00000004 // Sample Interrupt Enable +#define ADC_SSCTL3_END0 0x00000002 // End of Sequence +#define ADC_SSCTL3_D0 0x00000001 // Sample Differential Input Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO3 register. +// +//***************************************************************************** +#define ADC_SSFIFO3_DATA_M 0x00000FFF // Conversion Result Data +#define ADC_SSFIFO3_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register. +// +//***************************************************************************** +#define ADC_SSFSTAT3_FULL 0x00001000 // FIFO Full +#define ADC_SSFSTAT3_EMPTY 0x00000100 // FIFO Empty +#define ADC_SSFSTAT3_HPTR_M 0x000000F0 // FIFO Head Pointer +#define ADC_SSFSTAT3_TPTR_M 0x0000000F // FIFO Tail Pointer +#define ADC_SSFSTAT3_HPTR_S 4 +#define ADC_SSFSTAT3_TPTR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSOP3 register. +// +//***************************************************************************** +#define ADC_SSOP3_S0DCOP 0x00000001 // Sample 0 Digital Comparator + // Operation + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSDC3 register. +// +//***************************************************************************** +#define ADC_SSDC3_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator + // Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCRIC register. +// +//***************************************************************************** +#define ADC_DCRIC_DCTRIG7 0x00800000 // Digital Comparator Trigger 7 +#define ADC_DCRIC_DCTRIG6 0x00400000 // Digital Comparator Trigger 6 +#define ADC_DCRIC_DCTRIG5 0x00200000 // Digital Comparator Trigger 5 +#define ADC_DCRIC_DCTRIG4 0x00100000 // Digital Comparator Trigger 4 +#define ADC_DCRIC_DCTRIG3 0x00080000 // Digital Comparator Trigger 3 +#define ADC_DCRIC_DCTRIG2 0x00040000 // Digital Comparator Trigger 2 +#define ADC_DCRIC_DCTRIG1 0x00020000 // Digital Comparator Trigger 1 +#define ADC_DCRIC_DCTRIG0 0x00010000 // Digital Comparator Trigger 0 +#define ADC_DCRIC_DCINT7 0x00000080 // Digital Comparator Interrupt 7 +#define ADC_DCRIC_DCINT6 0x00000040 // Digital Comparator Interrupt 6 +#define ADC_DCRIC_DCINT5 0x00000020 // Digital Comparator Interrupt 5 +#define ADC_DCRIC_DCINT4 0x00000010 // Digital Comparator Interrupt 4 +#define ADC_DCRIC_DCINT3 0x00000008 // Digital Comparator Interrupt 3 +#define ADC_DCRIC_DCINT2 0x00000004 // Digital Comparator Interrupt 2 +#define ADC_DCRIC_DCINT1 0x00000002 // Digital Comparator Interrupt 1 +#define ADC_DCRIC_DCINT0 0x00000001 // Digital Comparator Interrupt 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL0 register. +// +//***************************************************************************** +#define ADC_DCCTL0_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL0_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL0_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL0_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL0_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL0_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL0_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL0_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL0_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL0_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL0_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL0_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL0_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL0_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL0_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL0_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL0_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL0_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL0_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL0_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL1 register. +// +//***************************************************************************** +#define ADC_DCCTL1_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL1_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL1_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL1_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL1_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL1_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL1_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL1_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL1_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL1_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL1_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL1_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL1_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL1_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL1_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL1_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL1_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL1_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL1_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL1_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL2 register. +// +//***************************************************************************** +#define ADC_DCCTL2_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL2_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL2_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL2_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL2_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL2_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL2_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL2_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL2_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL2_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL2_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL2_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL2_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL2_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL2_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL2_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL2_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL2_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL2_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL2_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL3 register. +// +//***************************************************************************** +#define ADC_DCCTL3_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL3_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL3_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL3_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL3_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL3_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL3_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL3_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL3_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL3_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL3_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL3_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL3_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL3_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL3_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL3_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL3_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL3_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL3_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL3_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL4 register. +// +//***************************************************************************** +#define ADC_DCCTL4_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL4_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL4_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL4_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL4_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL4_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL4_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL4_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL4_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL4_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL4_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL4_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL4_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL4_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL4_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL4_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL4_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL4_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL4_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL4_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL5 register. +// +//***************************************************************************** +#define ADC_DCCTL5_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL5_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL5_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL5_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL5_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL5_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL5_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL5_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL5_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL5_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL5_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL5_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL5_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL5_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL5_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL5_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL5_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL5_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL5_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL5_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL6 register. +// +//***************************************************************************** +#define ADC_DCCTL6_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL6_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL6_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL6_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL6_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL6_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL6_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL6_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL6_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL6_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL6_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL6_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL6_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL6_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL6_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL6_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL6_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL6_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL6_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL6_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL7 register. +// +//***************************************************************************** +#define ADC_DCCTL7_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL7_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL7_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL7_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL7_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL7_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL7_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL7_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL7_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL7_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL7_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL7_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL7_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL7_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL7_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL7_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL7_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL7_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL7_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL7_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP0 register. +// +//***************************************************************************** +#define ADC_DCCMP0_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP0_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP0_COMP1_S 16 +#define ADC_DCCMP0_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP1 register. +// +//***************************************************************************** +#define ADC_DCCMP1_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP1_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP1_COMP1_S 16 +#define ADC_DCCMP1_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP2 register. +// +//***************************************************************************** +#define ADC_DCCMP2_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP2_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP2_COMP1_S 16 +#define ADC_DCCMP2_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP3 register. +// +//***************************************************************************** +#define ADC_DCCMP3_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP3_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP3_COMP1_S 16 +#define ADC_DCCMP3_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP4 register. +// +//***************************************************************************** +#define ADC_DCCMP4_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP4_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP4_COMP1_S 16 +#define ADC_DCCMP4_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP5 register. +// +//***************************************************************************** +#define ADC_DCCMP5_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP5_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP5_COMP1_S 16 +#define ADC_DCCMP5_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP6 register. +// +//***************************************************************************** +#define ADC_DCCMP6_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP6_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP6_COMP1_S 16 +#define ADC_DCCMP6_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP7 register. +// +//***************************************************************************** +#define ADC_DCCMP7_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP7_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP7_COMP1_S 16 +#define ADC_DCCMP7_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_PP register. +// +//***************************************************************************** +#define ADC_PP_TS 0x00800000 // Temperature Sensor +#define ADC_PP_RSL_M 0x007C0000 // Resolution +#define ADC_PP_TYPE_M 0x00030000 // ADC Architecture +#define ADC_PP_TYPE_SAR 0x00000000 // SAR +#define ADC_PP_DC_M 0x0000FC00 // Digital Comparator Count +#define ADC_PP_CH_M 0x000003F0 // ADC Channel Count +#define ADC_PP_MSR_M 0x0000000F // Maximum ADC Sample Rate +#define ADC_PP_MSR_125K 0x00000001 // 125 ksps +#define ADC_PP_MSR_250K 0x00000003 // 250 ksps +#define ADC_PP_MSR_500K 0x00000005 // 500 ksps +#define ADC_PP_MSR_1M 0x00000007 // 1 Msps +#define ADC_PP_RSL_S 18 +#define ADC_PP_DC_S 10 +#define ADC_PP_CH_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_PC register. +// +//***************************************************************************** +#define ADC_PC_SR_M 0x0000000F // ADC Sample Rate +#define ADC_PC_SR_125K 0x00000001 // 125 ksps +#define ADC_PC_SR_250K 0x00000003 // 250 ksps +#define ADC_PC_SR_500K 0x00000005 // 500 ksps +#define ADC_PC_SR_1M 0x00000007 // 1 Msps + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_CC register. +// +//***************************************************************************** +#define ADC_CC_CS_M 0x0000000F // ADC Clock Source +#define ADC_CC_CS_SYSPLL 0x00000000 // PLL VCO divided by CLKDIV +#define ADC_CC_CS_PIOSC 0x00000001 // PIOSC + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACMIS register. +// +//***************************************************************************** +#define COMP_ACMIS_IN1 0x00000002 // Comparator 1 Masked Interrupt + // Status +#define COMP_ACMIS_IN0 0x00000001 // Comparator 0 Masked Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACRIS register. +// +//***************************************************************************** +#define COMP_ACRIS_IN1 0x00000002 // Comparator 1 Interrupt Status +#define COMP_ACRIS_IN0 0x00000001 // Comparator 0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACINTEN register. +// +//***************************************************************************** +#define COMP_ACINTEN_IN1 0x00000002 // Comparator 1 Interrupt Enable +#define COMP_ACINTEN_IN0 0x00000001 // Comparator 0 Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACREFCTL +// register. +// +//***************************************************************************** +#define COMP_ACREFCTL_EN 0x00000200 // Resistor Ladder Enable +#define COMP_ACREFCTL_RNG 0x00000100 // Resistor Ladder Range +#define COMP_ACREFCTL_VREF_M 0x0000000F // Resistor Ladder Voltage Ref +#define COMP_ACREFCTL_VREF_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACSTAT0 register. +// +//***************************************************************************** +#define COMP_ACSTAT0_OVAL 0x00000002 // Comparator Output Value + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACCTL0 register. +// +//***************************************************************************** +#define COMP_ACCTL0_TOEN 0x00000800 // Trigger Output Enable +#define COMP_ACCTL0_ASRCP_M 0x00000600 // Analog Source Positive +#define COMP_ACCTL0_ASRCP_PIN 0x00000000 // Pin value of Cn+ +#define COMP_ACCTL0_ASRCP_PIN0 0x00000200 // Pin value of C0+ +#define COMP_ACCTL0_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_ACCTL0_TSLVAL 0x00000080 // Trigger Sense Level Value +#define COMP_ACCTL0_TSEN_M 0x00000060 // Trigger Sense +#define COMP_ACCTL0_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL +#define COMP_ACCTL0_TSEN_FALL 0x00000020 // Falling edge +#define COMP_ACCTL0_TSEN_RISE 0x00000040 // Rising edge +#define COMP_ACCTL0_TSEN_BOTH 0x00000060 // Either edge +#define COMP_ACCTL0_ISLVAL 0x00000010 // Interrupt Sense Level Value +#define COMP_ACCTL0_ISEN_M 0x0000000C // Interrupt Sense +#define COMP_ACCTL0_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL +#define COMP_ACCTL0_ISEN_FALL 0x00000004 // Falling edge +#define COMP_ACCTL0_ISEN_RISE 0x00000008 // Rising edge +#define COMP_ACCTL0_ISEN_BOTH 0x0000000C // Either edge +#define COMP_ACCTL0_CINV 0x00000002 // Comparator Output Invert + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACSTAT1 register. +// +//***************************************************************************** +#define COMP_ACSTAT1_OVAL 0x00000002 // Comparator Output Value + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACCTL1 register. +// +//***************************************************************************** +#define COMP_ACCTL1_TOEN 0x00000800 // Trigger Output Enable +#define COMP_ACCTL1_ASRCP_M 0x00000600 // Analog Source Positive +#define COMP_ACCTL1_ASRCP_PIN 0x00000000 // Pin value of Cn+ +#define COMP_ACCTL1_ASRCP_PIN0 0x00000200 // Pin value of C0+ +#define COMP_ACCTL1_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_ACCTL1_TSLVAL 0x00000080 // Trigger Sense Level Value +#define COMP_ACCTL1_TSEN_M 0x00000060 // Trigger Sense +#define COMP_ACCTL1_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL +#define COMP_ACCTL1_TSEN_FALL 0x00000020 // Falling edge +#define COMP_ACCTL1_TSEN_RISE 0x00000040 // Rising edge +#define COMP_ACCTL1_TSEN_BOTH 0x00000060 // Either edge +#define COMP_ACCTL1_ISLVAL 0x00000010 // Interrupt Sense Level Value +#define COMP_ACCTL1_ISEN_M 0x0000000C // Interrupt Sense +#define COMP_ACCTL1_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL +#define COMP_ACCTL1_ISEN_FALL 0x00000004 // Falling edge +#define COMP_ACCTL1_ISEN_RISE 0x00000008 // Rising edge +#define COMP_ACCTL1_ISEN_BOTH 0x0000000C // Either edge +#define COMP_ACCTL1_CINV 0x00000002 // Comparator Output Invert + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_PP register. +// +//***************************************************************************** +#define COMP_PP_C1O 0x00020000 // Comparator Output 1 Present +#define COMP_PP_C0O 0x00010000 // Comparator Output 0 Present +#define COMP_PP_CMP1 0x00000002 // Comparator 1 Present +#define COMP_PP_CMP0 0x00000001 // Comparator 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_CTL register. +// +//***************************************************************************** +#define CAN_CTL_TEST 0x00000080 // Test Mode Enable +#define CAN_CTL_CCE 0x00000040 // Configuration Change Enable +#define CAN_CTL_DAR 0x00000020 // Disable Automatic-Retransmission +#define CAN_CTL_EIE 0x00000008 // Error Interrupt Enable +#define CAN_CTL_SIE 0x00000004 // Status Interrupt Enable +#define CAN_CTL_IE 0x00000002 // CAN Interrupt Enable +#define CAN_CTL_INIT 0x00000001 // Initialization + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_STS register. +// +//***************************************************************************** +#define CAN_STS_BOFF 0x00000080 // Bus-Off Status +#define CAN_STS_EWARN 0x00000040 // Warning Status +#define CAN_STS_EPASS 0x00000020 // Error Passive +#define CAN_STS_RXOK 0x00000010 // Received a Message Successfully +#define CAN_STS_TXOK 0x00000008 // Transmitted a Message + // Successfully +#define CAN_STS_LEC_M 0x00000007 // Last Error Code +#define CAN_STS_LEC_NONE 0x00000000 // No Error +#define CAN_STS_LEC_STUFF 0x00000001 // Stuff Error +#define CAN_STS_LEC_FORM 0x00000002 // Format Error +#define CAN_STS_LEC_ACK 0x00000003 // ACK Error +#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 Error +#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 Error +#define CAN_STS_LEC_CRC 0x00000006 // CRC Error +#define CAN_STS_LEC_NOEVENT 0x00000007 // No Event + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_ERR register. +// +//***************************************************************************** +#define CAN_ERR_RP 0x00008000 // Received Error Passive +#define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter +#define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter +#define CAN_ERR_REC_S 8 +#define CAN_ERR_TEC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_BIT register. +// +//***************************************************************************** +#define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point +#define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample Point +#define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width +#define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescaler +#define CAN_BIT_TSEG2_S 12 +#define CAN_BIT_TSEG1_S 8 +#define CAN_BIT_SJW_S 6 +#define CAN_BIT_BRP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_INT register. +// +//***************************************************************************** +#define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier +#define CAN_INT_INTID_NONE 0x00000000 // No interrupt pending +#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_TST register. +// +//***************************************************************************** +#define CAN_TST_RX 0x00000080 // Receive Observation +#define CAN_TST_TX_M 0x00000060 // Transmit Control +#define CAN_TST_TX_CANCTL 0x00000000 // CAN Module Control +#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point +#define CAN_TST_TX_DOMINANT 0x00000040 // Driven Low +#define CAN_TST_TX_RECESSIVE 0x00000060 // Driven High +#define CAN_TST_LBACK 0x00000010 // Loopback Mode +#define CAN_TST_SILENT 0x00000008 // Silent Mode +#define CAN_TST_BASIC 0x00000004 // Basic Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_BRPE register. +// +//***************************************************************************** +#define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescaler Extension +#define CAN_BRPE_BRPE_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1CRQ register. +// +//***************************************************************************** +#define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag +#define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number +#define CAN_IF1CRQ_MNUM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1CMSK register. +// +//***************************************************************************** +#define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read +#define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits +#define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits +#define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits +#define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit +#define CAN_IF1CMSK_NEWDAT 0x00000004 // Access New Data +#define CAN_IF1CMSK_TXRQST 0x00000004 // Access Transmission Request +#define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3 +#define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1MSK1 register. +// +//***************************************************************************** +#define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask +#define CAN_IF1MSK1_IDMSK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1MSK2 register. +// +//***************************************************************************** +#define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier +#define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction +#define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask +#define CAN_IF1MSK2_IDMSK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1ARB1 register. +// +//***************************************************************************** +#define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier +#define CAN_IF1ARB1_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1ARB2 register. +// +//***************************************************************************** +#define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid +#define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier +#define CAN_IF1ARB2_DIR 0x00002000 // Message Direction +#define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier +#define CAN_IF1ARB2_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1MCTL register. +// +//***************************************************************************** +#define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data +#define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost +#define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending +#define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask +#define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable +#define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable +#define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable +#define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request +#define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer +#define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code +#define CAN_IF1MCTL_DLC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1DA1 register. +// +//***************************************************************************** +#define CAN_IF1DA1_DATA_M 0x0000FFFF // Data +#define CAN_IF1DA1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1DA2 register. +// +//***************************************************************************** +#define CAN_IF1DA2_DATA_M 0x0000FFFF // Data +#define CAN_IF1DA2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1DB1 register. +// +//***************************************************************************** +#define CAN_IF1DB1_DATA_M 0x0000FFFF // Data +#define CAN_IF1DB1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1DB2 register. +// +//***************************************************************************** +#define CAN_IF1DB2_DATA_M 0x0000FFFF // Data +#define CAN_IF1DB2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2CRQ register. +// +//***************************************************************************** +#define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag +#define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number +#define CAN_IF2CRQ_MNUM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2CMSK register. +// +//***************************************************************************** +#define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read +#define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits +#define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits +#define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits +#define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit +#define CAN_IF2CMSK_NEWDAT 0x00000004 // Access New Data +#define CAN_IF2CMSK_TXRQST 0x00000004 // Access Transmission Request +#define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3 +#define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2MSK1 register. +// +//***************************************************************************** +#define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask +#define CAN_IF2MSK1_IDMSK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2MSK2 register. +// +//***************************************************************************** +#define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier +#define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction +#define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask +#define CAN_IF2MSK2_IDMSK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2ARB1 register. +// +//***************************************************************************** +#define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier +#define CAN_IF2ARB1_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2ARB2 register. +// +//***************************************************************************** +#define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid +#define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier +#define CAN_IF2ARB2_DIR 0x00002000 // Message Direction +#define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier +#define CAN_IF2ARB2_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2MCTL register. +// +//***************************************************************************** +#define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data +#define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost +#define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending +#define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask +#define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable +#define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable +#define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable +#define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request +#define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer +#define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code +#define CAN_IF2MCTL_DLC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2DA1 register. +// +//***************************************************************************** +#define CAN_IF2DA1_DATA_M 0x0000FFFF // Data +#define CAN_IF2DA1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2DA2 register. +// +//***************************************************************************** +#define CAN_IF2DA2_DATA_M 0x0000FFFF // Data +#define CAN_IF2DA2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2DB1 register. +// +//***************************************************************************** +#define CAN_IF2DB1_DATA_M 0x0000FFFF // Data +#define CAN_IF2DB1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2DB2 register. +// +//***************************************************************************** +#define CAN_IF2DB2_DATA_M 0x0000FFFF // Data +#define CAN_IF2DB2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_TXRQ1 register. +// +//***************************************************************************** +#define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits +#define CAN_TXRQ1_TXRQST_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_TXRQ2 register. +// +//***************************************************************************** +#define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits +#define CAN_TXRQ2_TXRQST_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_NWDA1 register. +// +//***************************************************************************** +#define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits +#define CAN_NWDA1_NEWDAT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_NWDA2 register. +// +//***************************************************************************** +#define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits +#define CAN_NWDA2_NEWDAT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_MSG1INT register. +// +//***************************************************************************** +#define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits +#define CAN_MSG1INT_INTPND_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_MSG2INT register. +// +//***************************************************************************** +#define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits +#define CAN_MSG2INT_INTPND_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_MSG1VAL register. +// +//***************************************************************************** +#define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits +#define CAN_MSG1VAL_MSGVAL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_MSG2VAL register. +// +//***************************************************************************** +#define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits +#define CAN_MSG2VAL_MSGVAL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FADDR register. +// +//***************************************************************************** +#define USB_FADDR_M 0x0000007F // Function Address +#define USB_FADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_POWER register. +// +//***************************************************************************** +#define USB_POWER_ISOUP 0x00000080 // Isochronous Update +#define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect +#define USB_POWER_RESET 0x00000008 // RESET Signaling +#define USB_POWER_RESUME 0x00000004 // RESUME Signaling +#define USB_POWER_SUSPEND 0x00000002 // SUSPEND Mode +#define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXIS register. +// +//***************************************************************************** +#define USB_TXIS_EP7 0x00000080 // TX Endpoint 7 Interrupt +#define USB_TXIS_EP6 0x00000040 // TX Endpoint 6 Interrupt +#define USB_TXIS_EP5 0x00000020 // TX Endpoint 5 Interrupt +#define USB_TXIS_EP4 0x00000010 // TX Endpoint 4 Interrupt +#define USB_TXIS_EP3 0x00000008 // TX Endpoint 3 Interrupt +#define USB_TXIS_EP2 0x00000004 // TX Endpoint 2 Interrupt +#define USB_TXIS_EP1 0x00000002 // TX Endpoint 1 Interrupt +#define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXIS register. +// +//***************************************************************************** +#define USB_RXIS_EP7 0x00000080 // RX Endpoint 7 Interrupt +#define USB_RXIS_EP6 0x00000040 // RX Endpoint 6 Interrupt +#define USB_RXIS_EP5 0x00000020 // RX Endpoint 5 Interrupt +#define USB_RXIS_EP4 0x00000010 // RX Endpoint 4 Interrupt +#define USB_RXIS_EP3 0x00000008 // RX Endpoint 3 Interrupt +#define USB_RXIS_EP2 0x00000004 // RX Endpoint 2 Interrupt +#define USB_RXIS_EP1 0x00000002 // RX Endpoint 1 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXIE register. +// +//***************************************************************************** +#define USB_TXIE_EP7 0x00000080 // TX Endpoint 7 Interrupt Enable +#define USB_TXIE_EP6 0x00000040 // TX Endpoint 6 Interrupt Enable +#define USB_TXIE_EP5 0x00000020 // TX Endpoint 5 Interrupt Enable +#define USB_TXIE_EP4 0x00000010 // TX Endpoint 4 Interrupt Enable +#define USB_TXIE_EP3 0x00000008 // TX Endpoint 3 Interrupt Enable +#define USB_TXIE_EP2 0x00000004 // TX Endpoint 2 Interrupt Enable +#define USB_TXIE_EP1 0x00000002 // TX Endpoint 1 Interrupt Enable +#define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt + // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXIE register. +// +//***************************************************************************** +#define USB_RXIE_EP7 0x00000080 // RX Endpoint 7 Interrupt Enable +#define USB_RXIE_EP6 0x00000040 // RX Endpoint 6 Interrupt Enable +#define USB_RXIE_EP5 0x00000020 // RX Endpoint 5 Interrupt Enable +#define USB_RXIE_EP4 0x00000010 // RX Endpoint 4 Interrupt Enable +#define USB_RXIE_EP3 0x00000008 // RX Endpoint 3 Interrupt Enable +#define USB_RXIE_EP2 0x00000004 // RX Endpoint 2 Interrupt Enable +#define USB_RXIE_EP1 0x00000002 // RX Endpoint 1 Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IS register. +// +//***************************************************************************** +#define USB_IS_VBUSERR 0x00000080 // VBUS Error (OTG only) +#define USB_IS_SESREQ 0x00000040 // SESSION REQUEST (OTG only) +#define USB_IS_DISCON 0x00000020 // Session Disconnect (OTG only) +#define USB_IS_CONN 0x00000010 // Session Connect +#define USB_IS_SOF 0x00000008 // Start of Frame +#define USB_IS_BABBLE 0x00000004 // Babble Detected +#define USB_IS_RESET 0x00000004 // RESET Signaling Detected +#define USB_IS_RESUME 0x00000002 // RESUME Signaling Detected +#define USB_IS_SUSPEND 0x00000001 // SUSPEND Signaling Detected + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IE register. +// +//***************************************************************************** +#define USB_IE_VBUSERR 0x00000080 // Enable VBUS Error Interrupt (OTG + // only) +#define USB_IE_SESREQ 0x00000040 // Enable Session Request (OTG + // only) +#define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt +#define USB_IE_CONN 0x00000010 // Enable Connect Interrupt +#define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt +#define USB_IE_BABBLE 0x00000004 // Enable Babble Interrupt +#define USB_IE_RESET 0x00000004 // Enable RESET Interrupt +#define USB_IE_RESUME 0x00000002 // Enable RESUME Interrupt +#define USB_IE_SUSPND 0x00000001 // Enable SUSPEND Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FRAME register. +// +//***************************************************************************** +#define USB_FRAME_M 0x000007FF // Frame Number +#define USB_FRAME_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPIDX register. +// +//***************************************************************************** +#define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index +#define USB_EPIDX_EPIDX_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TEST register. +// +//***************************************************************************** +#define USB_TEST_FORCEH 0x00000080 // Force Host Mode +#define USB_TEST_FIFOACC 0x00000040 // FIFO Access +#define USB_TEST_FORCEFS 0x00000020 // Force Full-Speed Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO0 register. +// +//***************************************************************************** +#define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO0_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO1 register. +// +//***************************************************************************** +#define USB_FIFO1_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO1_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO2 register. +// +//***************************************************************************** +#define USB_FIFO2_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO2_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO3 register. +// +//***************************************************************************** +#define USB_FIFO3_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO3_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO4 register. +// +//***************************************************************************** +#define USB_FIFO4_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO4_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO5 register. +// +//***************************************************************************** +#define USB_FIFO5_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO5_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO6 register. +// +//***************************************************************************** +#define USB_FIFO6_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO6_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO7 register. +// +//***************************************************************************** +#define USB_FIFO7_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO7_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DEVCTL register. +// +//***************************************************************************** +#define USB_DEVCTL_DEV 0x00000080 // Device Mode (OTG only) +#define USB_DEVCTL_FSDEV 0x00000040 // Full-Speed Device Detected +#define USB_DEVCTL_LSDEV 0x00000020 // Low-Speed Device Detected +#define USB_DEVCTL_VBUS_M 0x00000018 // VBUS Level (OTG only) +#define USB_DEVCTL_VBUS_NONE 0x00000000 // Below SessionEnd +#define USB_DEVCTL_VBUS_SEND 0x00000008 // Above SessionEnd, below AValid +#define USB_DEVCTL_VBUS_AVALID 0x00000010 // Above AValid, below VBUSValid +#define USB_DEVCTL_VBUS_VALID 0x00000018 // Above VBUSValid +#define USB_DEVCTL_HOST 0x00000004 // Host Mode +#define USB_DEVCTL_HOSTREQ 0x00000002 // Host Request (OTG only) +#define USB_DEVCTL_SESSION 0x00000001 // Session Start/End (OTG only) + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFIFOSZ register. +// +//***************************************************************************** +#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support +#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size +#define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8 +#define USB_TXFIFOSZ_SIZE_16 0x00000001 // 16 +#define USB_TXFIFOSZ_SIZE_32 0x00000002 // 32 +#define USB_TXFIFOSZ_SIZE_64 0x00000003 // 64 +#define USB_TXFIFOSZ_SIZE_128 0x00000004 // 128 +#define USB_TXFIFOSZ_SIZE_256 0x00000005 // 256 +#define USB_TXFIFOSZ_SIZE_512 0x00000006 // 512 +#define USB_TXFIFOSZ_SIZE_1024 0x00000007 // 1024 +#define USB_TXFIFOSZ_SIZE_2048 0x00000008 // 2048 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFIFOSZ register. +// +//***************************************************************************** +#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support +#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size +#define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8 +#define USB_RXFIFOSZ_SIZE_16 0x00000001 // 16 +#define USB_RXFIFOSZ_SIZE_32 0x00000002 // 32 +#define USB_RXFIFOSZ_SIZE_64 0x00000003 // 64 +#define USB_RXFIFOSZ_SIZE_128 0x00000004 // 128 +#define USB_RXFIFOSZ_SIZE_256 0x00000005 // 256 +#define USB_RXFIFOSZ_SIZE_512 0x00000006 // 512 +#define USB_RXFIFOSZ_SIZE_1024 0x00000007 // 1024 +#define USB_RXFIFOSZ_SIZE_2048 0x00000008 // 2048 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFIFOADD +// register. +// +//***************************************************************************** +#define USB_TXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address +#define USB_TXFIFOADD_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFIFOADD +// register. +// +//***************************************************************************** +#define USB_RXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address +#define USB_RXFIFOADD_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CONTIM register. +// +//***************************************************************************** +#define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait +#define USB_CONTIM_WTID_M 0x0000000F // Wait ID +#define USB_CONTIM_WTCON_S 4 +#define USB_CONTIM_WTID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VPLEN register. +// +//***************************************************************************** +#define USB_VPLEN_VPLEN_M 0x000000FF // VBUS Pulse Length +#define USB_VPLEN_VPLEN_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FSEOF register. +// +//***************************************************************************** +#define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap +#define USB_FSEOF_FSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LSEOF register. +// +//***************************************************************************** +#define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap +#define USB_LSEOF_LSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR0 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR0_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR0_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR0 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR0_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR0_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT0 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT0_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT0_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR1 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR1_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR1 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR1_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT1 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT1_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT1_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR1 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR1_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR1 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR1_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT1 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT1_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT1_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR2 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR2_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR2 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR2_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT2 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT2_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT2_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR2 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR2_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR2 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR2_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT2 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT2_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT2_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR3 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR3_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR3 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR3_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT3 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT3_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT3_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR3 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR3_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR3 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR3_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT3 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT3_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT3_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR4 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR4_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR4 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR4_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT4 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT4_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT4_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR4 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR4_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR4 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR4_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT4 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT4_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT4_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR5 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR5_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR5 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR5_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT5 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT5_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT5_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR5 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR5_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR5 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR5_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT5 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT5_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT5_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR6 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR6_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR6 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR6_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT6 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT6_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT6_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR6 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR6_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR6 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR6_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT6 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT6_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT6_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR7 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR7_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR7 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR7_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT7 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT7_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT7_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR7 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR7_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR7 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR7_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT7 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT7_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT7_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CSRL0 register. +// +//***************************************************************************** +#define USB_CSRL0_NAKTO 0x00000080 // NAK Timeout +#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear +#define USB_CSRL0_STATUS 0x00000040 // STATUS Packet +#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear +#define USB_CSRL0_REQPKT 0x00000020 // Request Packet +#define USB_CSRL0_STALL 0x00000020 // Send Stall +#define USB_CSRL0_SETEND 0x00000010 // Setup End +#define USB_CSRL0_ERROR 0x00000010 // Error +#define USB_CSRL0_DATAEND 0x00000008 // Data End +#define USB_CSRL0_SETUP 0x00000008 // Setup Packet +#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled +#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready +#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CSRH0 register. +// +//***************************************************************************** +#define USB_CSRH0_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_CSRH0_DT 0x00000002 // Data Toggle +#define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_COUNT0 register. +// +//***************************************************************************** +#define USB_COUNT0_COUNT_M 0x0000007F // FIFO Count +#define USB_COUNT0_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TYPE0 register. +// +//***************************************************************************** +#define USB_TYPE0_SPEED_M 0x000000C0 // Operating Speed +#define USB_TYPE0_SPEED_FULL 0x00000080 // Full +#define USB_TYPE0_SPEED_LOW 0x000000C0 // Low + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_NAKLMT register. +// +//***************************************************************************** +#define USB_NAKLMT_NAKLMT_M 0x0000001F // EP0 NAK Limit +#define USB_NAKLMT_NAKLMT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP1 register. +// +//***************************************************************************** +#define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP1_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL1 register. +// +//***************************************************************************** +#define USB_TXCSRL1_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL1_STALL 0x00000010 // Send STALL +#define USB_TXCSRL1_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL1_ERROR 0x00000004 // Error +#define USB_TXCSRL1_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH1 register. +// +//***************************************************************************** +#define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH1_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH1_MODE 0x00000020 // Mode +#define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH1_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH1_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP1 register. +// +//***************************************************************************** +#define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP1_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL1 register. +// +//***************************************************************************** +#define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL1_STALL 0x00000020 // Send STALL +#define USB_RXCSRL1_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL1_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL1_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL1_OVER 0x00000004 // Overrun +#define USB_RXCSRL1_ERROR 0x00000004 // Error +#define USB_RXCSRL1_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH1 register. +// +//***************************************************************************** +#define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH1_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH1_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH1_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH1_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH1_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT1 register. +// +//***************************************************************************** +#define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT1_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE1 register. +// +//***************************************************************************** +#define USB_TXTYPE1_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE1_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE1_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE1_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE1_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE1_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE1_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE1_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE1_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE1_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE1_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL1 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL1_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL1_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL1_TXPOLL_S \ + 0 +#define USB_TXINTERVAL1_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE1 register. +// +//***************************************************************************** +#define USB_RXTYPE1_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE1_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE1_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE1_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE1_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE1_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE1_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE1_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE1_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE1_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE1_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL1 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL1_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL1_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL1_TXPOLL_S \ + 0 +#define USB_RXINTERVAL1_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP2 register. +// +//***************************************************************************** +#define USB_TXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP2_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL2 register. +// +//***************************************************************************** +#define USB_TXCSRL2_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL2_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL2_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL2_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL2_STALL 0x00000010 // Send STALL +#define USB_TXCSRL2_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL2_ERROR 0x00000004 // Error +#define USB_TXCSRL2_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL2_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL2_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH2 register. +// +//***************************************************************************** +#define USB_TXCSRH2_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH2_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH2_MODE 0x00000020 // Mode +#define USB_TXCSRH2_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH2_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH2_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH2_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH2_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP2 register. +// +//***************************************************************************** +#define USB_RXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP2_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL2 register. +// +//***************************************************************************** +#define USB_RXCSRL2_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL2_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL2_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL2_STALL 0x00000020 // Send STALL +#define USB_RXCSRL2_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL2_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL2_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL2_ERROR 0x00000004 // Error +#define USB_RXCSRL2_OVER 0x00000004 // Overrun +#define USB_RXCSRL2_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL2_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH2 register. +// +//***************************************************************************** +#define USB_RXCSRH2_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH2_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH2_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH2_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH2_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH2_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH2_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH2_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT2 register. +// +//***************************************************************************** +#define USB_RXCOUNT2_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT2_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE2 register. +// +//***************************************************************************** +#define USB_TXTYPE2_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE2_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE2_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE2_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE2_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE2_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE2_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE2_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE2_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE2_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE2_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL2 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL2_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL2_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL2_NAKLMT_S \ + 0 +#define USB_TXINTERVAL2_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE2 register. +// +//***************************************************************************** +#define USB_RXTYPE2_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE2_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE2_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE2_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE2_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE2_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE2_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE2_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE2_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE2_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE2_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL2 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL2_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL2_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL2_TXPOLL_S \ + 0 +#define USB_RXINTERVAL2_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP3 register. +// +//***************************************************************************** +#define USB_TXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP3_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL3 register. +// +//***************************************************************************** +#define USB_TXCSRL3_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL3_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL3_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL3_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL3_STALL 0x00000010 // Send STALL +#define USB_TXCSRL3_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL3_ERROR 0x00000004 // Error +#define USB_TXCSRL3_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL3_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL3_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH3 register. +// +//***************************************************************************** +#define USB_TXCSRH3_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH3_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH3_MODE 0x00000020 // Mode +#define USB_TXCSRH3_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH3_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH3_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH3_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH3_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP3 register. +// +//***************************************************************************** +#define USB_RXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP3_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL3 register. +// +//***************************************************************************** +#define USB_RXCSRL3_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL3_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL3_STALL 0x00000020 // Send STALL +#define USB_RXCSRL3_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL3_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL3_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL3_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL3_ERROR 0x00000004 // Error +#define USB_RXCSRL3_OVER 0x00000004 // Overrun +#define USB_RXCSRL3_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL3_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH3 register. +// +//***************************************************************************** +#define USB_RXCSRH3_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH3_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH3_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH3_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH3_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH3_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH3_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH3_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT3 register. +// +//***************************************************************************** +#define USB_RXCOUNT3_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT3_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE3 register. +// +//***************************************************************************** +#define USB_TXTYPE3_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE3_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE3_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE3_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE3_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE3_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE3_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE3_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE3_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE3_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE3_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL3 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL3_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL3_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL3_TXPOLL_S \ + 0 +#define USB_TXINTERVAL3_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE3 register. +// +//***************************************************************************** +#define USB_RXTYPE3_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE3_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE3_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE3_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE3_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE3_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE3_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE3_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE3_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE3_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE3_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL3 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL3_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL3_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL3_TXPOLL_S \ + 0 +#define USB_RXINTERVAL3_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP4 register. +// +//***************************************************************************** +#define USB_TXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP4_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL4 register. +// +//***************************************************************************** +#define USB_TXCSRL4_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL4_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL4_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL4_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL4_STALL 0x00000010 // Send STALL +#define USB_TXCSRL4_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL4_ERROR 0x00000004 // Error +#define USB_TXCSRL4_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL4_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL4_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH4 register. +// +//***************************************************************************** +#define USB_TXCSRH4_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH4_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH4_MODE 0x00000020 // Mode +#define USB_TXCSRH4_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH4_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH4_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH4_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH4_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP4 register. +// +//***************************************************************************** +#define USB_RXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP4_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL4 register. +// +//***************************************************************************** +#define USB_RXCSRL4_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL4_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL4_STALL 0x00000020 // Send STALL +#define USB_RXCSRL4_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL4_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL4_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL4_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL4_OVER 0x00000004 // Overrun +#define USB_RXCSRL4_ERROR 0x00000004 // Error +#define USB_RXCSRL4_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL4_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH4 register. +// +//***************************************************************************** +#define USB_RXCSRH4_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH4_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH4_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH4_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH4_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH4_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH4_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH4_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH4_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT4 register. +// +//***************************************************************************** +#define USB_RXCOUNT4_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT4_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE4 register. +// +//***************************************************************************** +#define USB_TXTYPE4_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE4_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE4_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE4_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE4_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE4_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE4_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE4_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE4_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE4_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE4_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL4 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL4_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL4_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL4_NAKLMT_S \ + 0 +#define USB_TXINTERVAL4_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE4 register. +// +//***************************************************************************** +#define USB_RXTYPE4_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE4_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE4_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE4_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE4_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE4_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE4_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE4_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE4_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE4_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE4_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL4 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL4_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL4_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL4_NAKLMT_S \ + 0 +#define USB_RXINTERVAL4_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP5 register. +// +//***************************************************************************** +#define USB_TXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP5_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL5 register. +// +//***************************************************************************** +#define USB_TXCSRL5_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL5_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL5_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL5_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL5_STALL 0x00000010 // Send STALL +#define USB_TXCSRL5_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL5_ERROR 0x00000004 // Error +#define USB_TXCSRL5_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL5_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL5_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH5 register. +// +//***************************************************************************** +#define USB_TXCSRH5_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH5_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH5_MODE 0x00000020 // Mode +#define USB_TXCSRH5_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH5_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH5_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH5_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH5_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP5 register. +// +//***************************************************************************** +#define USB_RXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP5_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL5 register. +// +//***************************************************************************** +#define USB_RXCSRL5_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL5_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL5_STALL 0x00000020 // Send STALL +#define USB_RXCSRL5_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL5_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL5_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL5_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL5_ERROR 0x00000004 // Error +#define USB_RXCSRL5_OVER 0x00000004 // Overrun +#define USB_RXCSRL5_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL5_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH5 register. +// +//***************************************************************************** +#define USB_RXCSRH5_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH5_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH5_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH5_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH5_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH5_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH5_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH5_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH5_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT5 register. +// +//***************************************************************************** +#define USB_RXCOUNT5_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT5_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE5 register. +// +//***************************************************************************** +#define USB_TXTYPE5_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE5_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE5_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE5_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE5_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE5_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE5_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE5_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE5_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE5_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE5_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL5 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL5_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL5_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL5_NAKLMT_S \ + 0 +#define USB_TXINTERVAL5_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE5 register. +// +//***************************************************************************** +#define USB_RXTYPE5_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE5_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE5_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE5_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE5_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE5_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE5_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE5_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE5_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE5_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE5_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL5 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL5_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL5_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL5_TXPOLL_S \ + 0 +#define USB_RXINTERVAL5_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP6 register. +// +//***************************************************************************** +#define USB_TXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP6_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL6 register. +// +//***************************************************************************** +#define USB_TXCSRL6_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL6_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL6_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL6_STALL 0x00000010 // Send STALL +#define USB_TXCSRL6_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL6_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL6_ERROR 0x00000004 // Error +#define USB_TXCSRL6_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL6_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL6_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH6 register. +// +//***************************************************************************** +#define USB_TXCSRH6_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH6_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH6_MODE 0x00000020 // Mode +#define USB_TXCSRH6_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH6_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH6_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH6_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH6_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP6 register. +// +//***************************************************************************** +#define USB_RXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP6_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL6 register. +// +//***************************************************************************** +#define USB_RXCSRL6_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL6_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL6_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL6_STALL 0x00000020 // Send STALL +#define USB_RXCSRL6_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL6_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL6_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL6_ERROR 0x00000004 // Error +#define USB_RXCSRL6_OVER 0x00000004 // Overrun +#define USB_RXCSRL6_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL6_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH6 register. +// +//***************************************************************************** +#define USB_RXCSRH6_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH6_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH6_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH6_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH6_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH6_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH6_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH6_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH6_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT6 register. +// +//***************************************************************************** +#define USB_RXCOUNT6_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT6_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE6 register. +// +//***************************************************************************** +#define USB_TXTYPE6_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE6_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE6_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE6_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE6_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE6_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE6_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE6_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE6_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE6_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE6_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL6 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL6_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL6_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL6_TXPOLL_S \ + 0 +#define USB_TXINTERVAL6_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE6 register. +// +//***************************************************************************** +#define USB_RXTYPE6_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE6_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE6_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE6_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE6_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE6_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE6_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE6_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE6_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE6_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE6_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL6 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL6_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL6_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL6_NAKLMT_S \ + 0 +#define USB_RXINTERVAL6_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP7 register. +// +//***************************************************************************** +#define USB_TXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP7_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL7 register. +// +//***************************************************************************** +#define USB_TXCSRL7_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL7_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL7_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL7_STALL 0x00000010 // Send STALL +#define USB_TXCSRL7_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL7_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL7_ERROR 0x00000004 // Error +#define USB_TXCSRL7_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL7_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL7_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH7 register. +// +//***************************************************************************** +#define USB_TXCSRH7_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH7_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH7_MODE 0x00000020 // Mode +#define USB_TXCSRH7_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH7_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH7_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH7_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH7_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP7 register. +// +//***************************************************************************** +#define USB_RXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP7_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL7 register. +// +//***************************************************************************** +#define USB_RXCSRL7_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL7_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL7_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL7_STALL 0x00000020 // Send STALL +#define USB_RXCSRL7_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL7_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL7_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL7_ERROR 0x00000004 // Error +#define USB_RXCSRL7_OVER 0x00000004 // Overrun +#define USB_RXCSRL7_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL7_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH7 register. +// +//***************************************************************************** +#define USB_RXCSRH7_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH7_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH7_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH7_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH7_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH7_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH7_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH7_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH7_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT7 register. +// +//***************************************************************************** +#define USB_RXCOUNT7_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT7_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE7 register. +// +//***************************************************************************** +#define USB_TXTYPE7_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE7_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE7_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE7_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE7_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE7_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE7_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE7_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE7_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE7_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE7_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL7 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL7_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL7_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL7_NAKLMT_S \ + 0 +#define USB_TXINTERVAL7_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE7 register. +// +//***************************************************************************** +#define USB_RXTYPE7_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE7_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE7_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE7_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE7_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE7_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE7_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE7_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE7_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE7_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE7_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL7 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL7_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL7_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL7_NAKLMT_S \ + 0 +#define USB_RXINTERVAL7_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT1_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT1_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT2_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT2_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT3_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT3_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT4_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT5_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT6_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT7_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS +// register. +// +//***************************************************************************** +#define USB_RXDPKTBUFDIS_EP7 0x00000080 // EP7 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP6 0x00000040 // EP6 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP5 0x00000020 // EP5 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP4 0x00000010 // EP4 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP3 0x00000008 // EP3 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP2 0x00000004 // EP2 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP1 0x00000002 // EP1 RX Double-Packet Buffer + // Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS +// register. +// +//***************************************************************************** +#define USB_TXDPKTBUFDIS_EP7 0x00000080 // EP7 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP6 0x00000040 // EP6 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP5 0x00000020 // EP5 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP4 0x00000010 // EP4 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP3 0x00000008 // EP3 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP2 0x00000004 // EP2 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer + // Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPC register. +// +//***************************************************************************** +#define USB_EPC_PFLTACT_M 0x00000300 // Power Fault Action +#define USB_EPC_PFLTACT_UNCHG 0x00000000 // Unchanged +#define USB_EPC_PFLTACT_TRIS 0x00000100 // Tristate +#define USB_EPC_PFLTACT_LOW 0x00000200 // Low +#define USB_EPC_PFLTACT_HIGH 0x00000300 // High +#define USB_EPC_PFLTAEN 0x00000040 // Power Fault Action Enable +#define USB_EPC_PFLTSEN_HIGH 0x00000020 // Power Fault Sense +#define USB_EPC_PFLTEN 0x00000010 // Power Fault Input Enable +#define USB_EPC_EPENDE 0x00000004 // EPEN Drive Enable +#define USB_EPC_EPEN_M 0x00000003 // External Power Supply Enable + // Configuration +#define USB_EPC_EPEN_LOW 0x00000000 // Power Enable Active Low +#define USB_EPC_EPEN_HIGH 0x00000001 // Power Enable Active High +#define USB_EPC_EPEN_VBLOW 0x00000002 // Power Enable High if VBUS Low + // (OTG only) +#define USB_EPC_EPEN_VBHIGH 0x00000003 // Power Enable High if VBUS High + // (OTG only) + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCRIS register. +// +//***************************************************************************** +#define USB_EPCRIS_PF 0x00000001 // USB Power Fault Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCIM register. +// +//***************************************************************************** +#define USB_EPCIM_PF 0x00000001 // USB Power Fault Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCISC register. +// +//***************************************************************************** +#define USB_EPCISC_PF 0x00000001 // USB Power Fault Interrupt Status + // and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRRIS register. +// +//***************************************************************************** +#define USB_DRRIS_RESUME 0x00000001 // RESUME Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRIM register. +// +//***************************************************************************** +#define USB_DRIM_RESUME 0x00000001 // RESUME Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRISC register. +// +//***************************************************************************** +#define USB_DRISC_RESUME 0x00000001 // RESUME Interrupt Status and + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_GPCS register. +// +//***************************************************************************** +#define USB_GPCS_DEVMODOTG 0x00000002 // Enable Device Mode +#define USB_GPCS_DEVMOD 0x00000001 // Device Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDC register. +// +//***************************************************************************** +#define USB_VDC_VBDEN 0x00000001 // VBUS Droop Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCRIS register. +// +//***************************************************************************** +#define USB_VDCRIS_VD 0x00000001 // VBUS Droop Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCIM register. +// +//***************************************************************************** +#define USB_VDCIM_VD 0x00000001 // VBUS Droop Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCISC register. +// +//***************************************************************************** +#define USB_VDCISC_VD 0x00000001 // VBUS Droop Interrupt Status and + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVRIS register. +// +//***************************************************************************** +#define USB_IDVRIS_ID 0x00000001 // ID Valid Detect Raw Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVIM register. +// +//***************************************************************************** +#define USB_IDVIM_ID 0x00000001 // ID Valid Detect Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVISC register. +// +//***************************************************************************** +#define USB_IDVISC_ID 0x00000001 // ID Valid Detect Interrupt Status + // and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMASEL register. +// +//***************************************************************************** +#define USB_DMASEL_DMACTX_M 0x00F00000 // DMA C TX Select +#define USB_DMASEL_DMACRX_M 0x000F0000 // DMA C RX Select +#define USB_DMASEL_DMABTX_M 0x0000F000 // DMA B TX Select +#define USB_DMASEL_DMABRX_M 0x00000F00 // DMA B RX Select +#define USB_DMASEL_DMAATX_M 0x000000F0 // DMA A TX Select +#define USB_DMASEL_DMAARX_M 0x0000000F // DMA A RX Select +#define USB_DMASEL_DMACTX_S 20 +#define USB_DMASEL_DMACRX_S 16 +#define USB_DMASEL_DMABTX_S 12 +#define USB_DMASEL_DMABRX_S 8 +#define USB_DMASEL_DMAATX_S 4 +#define USB_DMASEL_DMAARX_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_PP register. +// +//***************************************************************************** +#define USB_PP_ECNT_M 0x0000FF00 // Endpoint Count +#define USB_PP_USB_M 0x000000C0 // USB Capability +#define USB_PP_USB_DEVICE 0x00000040 // DEVICE +#define USB_PP_USB_HOSTDEVICE 0x00000080 // HOST +#define USB_PP_USB_OTG 0x000000C0 // OTG +#define USB_PP_PHY 0x00000010 // PHY Present +#define USB_PP_TYPE_M 0x0000000F // Controller Type +#define USB_PP_TYPE_0 0x00000000 // The first-generation USB + // controller +#define USB_PP_ECNT_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EESIZE register. +// +//***************************************************************************** +#define EEPROM_EESIZE_BLKCNT_M 0x07FF0000 // Number of 16-Word Blocks +#define EEPROM_EESIZE_WORDCNT_M 0x0000FFFF // Number of 32-Bit Words +#define EEPROM_EESIZE_BLKCNT_S 16 +#define EEPROM_EESIZE_WORDCNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEBLOCK register. +// +//***************************************************************************** +#define EEPROM_EEBLOCK_BLOCK_M 0x0000FFFF // Current Block +#define EEPROM_EEBLOCK_BLOCK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEOFFSET +// register. +// +//***************************************************************************** +#define EEPROM_EEOFFSET_OFFSET_M \ + 0x0000000F // Current Address Offset +#define EEPROM_EEOFFSET_OFFSET_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EERDWR register. +// +//***************************************************************************** +#define EEPROM_EERDWR_VALUE_M 0xFFFFFFFF // EEPROM Read or Write Data +#define EEPROM_EERDWR_VALUE_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EERDWRINC +// register. +// +//***************************************************************************** +#define EEPROM_EERDWRINC_VALUE_M \ + 0xFFFFFFFF // EEPROM Read or Write Data with + // Increment +#define EEPROM_EERDWRINC_VALUE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEDONE register. +// +//***************************************************************************** +#define EEPROM_EEDONE_WRBUSY 0x00000020 // Write Busy +#define EEPROM_EEDONE_NOPERM 0x00000010 // Write Without Permission +#define EEPROM_EEDONE_WKCOPY 0x00000008 // Working on a Copy +#define EEPROM_EEDONE_WKERASE 0x00000004 // Working on an Erase +#define EEPROM_EEDONE_WORKING 0x00000001 // EEPROM Working + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EESUPP register. +// +//***************************************************************************** +#define EEPROM_EESUPP_PRETRY 0x00000008 // Programming Must Be Retried +#define EEPROM_EESUPP_ERETRY 0x00000004 // Erase Must Be Retried + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEUNLOCK +// register. +// +//***************************************************************************** +#define EEPROM_EEUNLOCK_UNLOCK_M \ + 0xFFFFFFFF // EEPROM Unlock + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEPROT register. +// +//***************************************************************************** +#define EEPROM_EEPROT_ACC 0x00000008 // Access Control +#define EEPROM_EEPROT_PROT_M 0x00000007 // Protection Control +#define EEPROM_EEPROT_PROT_RWNPW \ + 0x00000000 // This setting is the default. If + // there is no password, the block + // is not protected and is readable + // and writable +#define EEPROM_EEPROT_PROT_RWPW 0x00000001 // If there is a password, the + // block is readable or writable + // only when unlocked +#define EEPROM_EEPROT_PROT_RONPW \ + 0x00000002 // If there is no password, the + // block is readable, not writable + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEPASS0 register. +// +//***************************************************************************** +#define EEPROM_EEPASS0_PASS_M 0xFFFFFFFF // Password +#define EEPROM_EEPASS0_PASS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEPASS1 register. +// +//***************************************************************************** +#define EEPROM_EEPASS1_PASS_M 0xFFFFFFFF // Password +#define EEPROM_EEPASS1_PASS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEPASS2 register. +// +//***************************************************************************** +#define EEPROM_EEPASS2_PASS_M 0xFFFFFFFF // Password +#define EEPROM_EEPASS2_PASS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEINT register. +// +//***************************************************************************** +#define EEPROM_EEINT_INT 0x00000001 // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEHIDE register. +// +//***************************************************************************** +#define EEPROM_EEHIDE_HN_M 0xFFFFFFFE // Hide Block + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEDBGME register. +// +//***************************************************************************** +#define EEPROM_EEDBGME_KEY_M 0xFFFF0000 // Erase Key +#define EEPROM_EEDBGME_ME 0x00000001 // Mass Erase +#define EEPROM_EEDBGME_KEY_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_PP register. +// +//***************************************************************************** +#define EEPROM_PP_SIZE_M 0x0000001F // EEPROM Size +#define EEPROM_PP_SIZE_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSEXC_RIS register. +// +//***************************************************************************** +#define SYSEXC_RIS_FPIXCRIS 0x00000020 // Floating-Point Inexact Exception + // Raw Interrupt Status +#define SYSEXC_RIS_FPOFCRIS 0x00000010 // Floating-Point Overflow + // Exception Raw Interrupt Status +#define SYSEXC_RIS_FPUFCRIS 0x00000008 // Floating-Point Underflow + // Exception Raw Interrupt Status +#define SYSEXC_RIS_FPIOCRIS 0x00000004 // Floating-Point Invalid Operation + // Raw Interrupt Status +#define SYSEXC_RIS_FPDZCRIS 0x00000002 // Floating-Point Divide By 0 + // Exception Raw Interrupt Status +#define SYSEXC_RIS_FPIDCRIS 0x00000001 // Floating-Point Input Denormal + // Exception Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSEXC_IM register. +// +//***************************************************************************** +#define SYSEXC_IM_FPIXCIM 0x00000020 // Floating-Point Inexact Exception + // Interrupt Mask +#define SYSEXC_IM_FPOFCIM 0x00000010 // Floating-Point Overflow + // Exception Interrupt Mask +#define SYSEXC_IM_FPUFCIM 0x00000008 // Floating-Point Underflow + // Exception Interrupt Mask +#define SYSEXC_IM_FPIOCIM 0x00000004 // Floating-Point Invalid Operation + // Interrupt Mask +#define SYSEXC_IM_FPDZCIM 0x00000002 // Floating-Point Divide By 0 + // Exception Interrupt Mask +#define SYSEXC_IM_FPIDCIM 0x00000001 // Floating-Point Input Denormal + // Exception Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSEXC_MIS register. +// +//***************************************************************************** +#define SYSEXC_MIS_FPIXCMIS 0x00000020 // Floating-Point Inexact Exception + // Masked Interrupt Status +#define SYSEXC_MIS_FPOFCMIS 0x00000010 // Floating-Point Overflow + // Exception Masked Interrupt + // Status +#define SYSEXC_MIS_FPUFCMIS 0x00000008 // Floating-Point Underflow + // Exception Masked Interrupt + // Status +#define SYSEXC_MIS_FPIOCMIS 0x00000004 // Floating-Point Invalid Operation + // Masked Interrupt Status +#define SYSEXC_MIS_FPDZCMIS 0x00000002 // Floating-Point Divide By 0 + // Exception Masked Interrupt + // Status +#define SYSEXC_MIS_FPIDCMIS 0x00000001 // Floating-Point Input Denormal + // Exception Masked Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSEXC_IC register. +// +//***************************************************************************** +#define SYSEXC_IC_FPIXCIC 0x00000020 // Floating-Point Inexact Exception + // Interrupt Clear +#define SYSEXC_IC_FPOFCIC 0x00000010 // Floating-Point Overflow + // Exception Interrupt Clear +#define SYSEXC_IC_FPUFCIC 0x00000008 // Floating-Point Underflow + // Exception Interrupt Clear +#define SYSEXC_IC_FPIOCIC 0x00000004 // Floating-Point Invalid Operation + // Interrupt Clear +#define SYSEXC_IC_FPDZCIC 0x00000002 // Floating-Point Divide By 0 + // Exception Interrupt Clear +#define SYSEXC_IC_FPIDCIC 0x00000001 // Floating-Point Input Denormal + // Exception Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCC register. +// +//***************************************************************************** +#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter +#define HIB_RTCC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCM0 register. +// +//***************************************************************************** +#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0 +#define HIB_RTCM0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCLD register. +// +//***************************************************************************** +#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load +#define HIB_RTCLD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_CTL register. +// +//***************************************************************************** +#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable +#define HIB_CTL_OSCDRV 0x00020000 // Oscillator Drive Capability +#define HIB_CTL_OSCBYP 0x00010000 // Oscillator Bypass +#define HIB_CTL_VBATSEL_M 0x00006000 // Select for Low-Battery + // Comparator +#define HIB_CTL_VBATSEL_1_9V 0x00000000 // 1.9 Volts +#define HIB_CTL_VBATSEL_2_1V 0x00002000 // 2.1 Volts (default) +#define HIB_CTL_VBATSEL_2_3V 0x00004000 // 2.3 Volts +#define HIB_CTL_VBATSEL_2_5V 0x00006000 // 2.5 Volts +#define HIB_CTL_BATCHK 0x00000400 // Check Battery Status +#define HIB_CTL_BATWKEN 0x00000200 // Wake on Low Battery +#define HIB_CTL_VDD3ON 0x00000100 // VDD Powered +#define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable +#define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable +#define HIB_CTL_PINWEN 0x00000010 // External Wake Pin Enable +#define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable +#define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request +#define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_IM register. +// +//***************************************************************************** +#define HIB_IM_WC 0x00000010 // External Write Complete/Capable + // Interrupt Mask +#define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask +#define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt + // Mask +#define HIB_IM_RTCALT0 0x00000001 // RTC Alert 0 Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RIS register. +// +//***************************************************************************** +#define HIB_RIS_WC 0x00000010 // Write Complete/Capable Raw + // Interrupt Status +#define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt + // Status +#define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw + // Interrupt Status +#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert 0 Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_MIS register. +// +//***************************************************************************** +#define HIB_MIS_WC 0x00000010 // Write Complete/Capable Masked + // Interrupt Status +#define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked + // Interrupt Status +#define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked + // Interrupt Status +#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert 0 Masked Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_IC register. +// +//***************************************************************************** +#define HIB_IC_WC 0x00000010 // Write Complete/Capable Interrupt + // Clear +#define HIB_IC_EXTW 0x00000008 // External Wake-Up Interrupt Clear +#define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Interrupt + // Clear +#define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCT register. +// +//***************************************************************************** +#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value +#define HIB_RTCT_TRIM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCSS register. +// +//***************************************************************************** +#define HIB_RTCSS_RTCSSM_M 0x7FFF0000 // RTC Sub Seconds Match +#define HIB_RTCSS_RTCSSC_M 0x00007FFF // RTC Sub Seconds Count +#define HIB_RTCSS_RTCSSM_S 16 +#define HIB_RTCSS_RTCSSC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_DATA register. +// +//***************************************************************************** +#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV Data +#define HIB_DATA_RTD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMA register. +// +//***************************************************************************** +#define FLASH_FMA_OFFSET_M 0x0003FFFF // Address Offset +#define FLASH_FMA_OFFSET_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMD register. +// +//***************************************************************************** +#define FLASH_FMD_DATA_M 0xFFFFFFFF // Data Value +#define FLASH_FMD_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMC register. +// +//***************************************************************************** +#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key +#define FLASH_FMC_COMT 0x00000008 // Commit Register Value +#define FLASH_FMC_MERASE 0x00000004 // Mass Erase Flash Memory +#define FLASH_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory +#define FLASH_FMC_WRITE 0x00000001 // Write a Word into Flash Memory + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FCRIS register. +// +//***************************************************************************** +#define FLASH_FCRIS_PROGRIS 0x00002000 // Program Verify Error Raw + // Interrupt Status +#define FLASH_FCRIS_ERRIS 0x00000800 // Erase Verify Error Raw Interrupt + // Status +#define FLASH_FCRIS_INVDRIS 0x00000400 // Invalid Data Raw Interrupt + // Status +#define FLASH_FCRIS_VOLTRIS 0x00000200 // Pump Voltage Raw Interrupt + // Status +#define FLASH_FCRIS_ERIS 0x00000004 // EEPROM Raw Interrupt Status +#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt Status +#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FCIM register. +// +//***************************************************************************** +#define FLASH_FCIM_PROGMASK 0x00002000 // PROGVER Interrupt Mask +#define FLASH_FCIM_ERMASK 0x00000800 // ERVER Interrupt Mask +#define FLASH_FCIM_INVDMASK 0x00000400 // Invalid Data Interrupt Mask +#define FLASH_FCIM_VOLTMASK 0x00000200 // VOLT Interrupt Mask +#define FLASH_FCIM_EMASK 0x00000004 // EEPROM Interrupt Mask +#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask +#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FCMISC register. +// +//***************************************************************************** +#define FLASH_FCMISC_PROGMISC 0x00002000 // PROGVER Masked Interrupt Status + // and Clear +#define FLASH_FCMISC_ERMISC 0x00000800 // ERVER Masked Interrupt Status + // and Clear +#define FLASH_FCMISC_INVDMISC 0x00000400 // Invalid Data Masked Interrupt + // Status and Clear +#define FLASH_FCMISC_VOLTMISC 0x00000200 // VOLT Masked Interrupt Status and + // Clear +#define FLASH_FCMISC_EMISC 0x00000004 // EEPROM Masked Interrupt Status + // and Clear +#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt + // Status and Clear +#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status + // and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMC2 register. +// +//***************************************************************************** +#define FLASH_FMC2_WRBUF 0x00000001 // Buffered Flash Memory Write + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FWBVAL register. +// +//***************************************************************************** +#define FLASH_FWBVAL_FWB_M 0xFFFFFFFF // Flash Memory Write Buffer + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FWBN register. +// +//***************************************************************************** +#define FLASH_FWBN_DATA_M 0xFFFFFFFF // Data + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FSIZE register. +// +//***************************************************************************** +#define FLASH_FSIZE_SIZE_M 0x0000FFFF // Flash Size +#define FLASH_FSIZE_SIZE_256KB 0x0000007F // 256 KB of Flash + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_SSIZE register. +// +//***************************************************************************** +#define FLASH_SSIZE_SIZE_M 0x0000FFFF // SRAM Size +#define FLASH_SSIZE_SIZE_32KB 0x0000007F // 32 KB of SRAM + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_ROMSWMAP register. +// +//***************************************************************************** +#define FLASH_ROMSWMAP_SAFERTOS 0x00000001 // SafeRTOS Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_RMCTL register. +// +//***************************************************************************** +#define FLASH_RMCTL_BA 0x00000001 // Boot Alias + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_BOOTCFG register. +// +//***************************************************************************** +#define FLASH_BOOTCFG_NW 0x80000000 // Not Written +#define FLASH_BOOTCFG_PORT_M 0x0000E000 // Boot GPIO Port +#define FLASH_BOOTCFG_PORT_A 0x00000000 // Port A +#define FLASH_BOOTCFG_PORT_B 0x00002000 // Port B +#define FLASH_BOOTCFG_PORT_C 0x00004000 // Port C +#define FLASH_BOOTCFG_PORT_D 0x00006000 // Port D +#define FLASH_BOOTCFG_PORT_E 0x00008000 // Port E +#define FLASH_BOOTCFG_PORT_F 0x0000A000 // Port F +#define FLASH_BOOTCFG_PORT_G 0x0000C000 // Port G +#define FLASH_BOOTCFG_PORT_H 0x0000E000 // Port H +#define FLASH_BOOTCFG_PIN_M 0x00001C00 // Boot GPIO Pin +#define FLASH_BOOTCFG_PIN_0 0x00000000 // Pin 0 +#define FLASH_BOOTCFG_PIN_1 0x00000400 // Pin 1 +#define FLASH_BOOTCFG_PIN_2 0x00000800 // Pin 2 +#define FLASH_BOOTCFG_PIN_3 0x00000C00 // Pin 3 +#define FLASH_BOOTCFG_PIN_4 0x00001000 // Pin 4 +#define FLASH_BOOTCFG_PIN_5 0x00001400 // Pin 5 +#define FLASH_BOOTCFG_PIN_6 0x00001800 // Pin 6 +#define FLASH_BOOTCFG_PIN_7 0x00001C00 // Pin 7 +#define FLASH_BOOTCFG_POL 0x00000200 // Boot GPIO Polarity +#define FLASH_BOOTCFG_EN 0x00000100 // Boot GPIO Enable +#define FLASH_BOOTCFG_KEY 0x00000010 // KEY Select +#define FLASH_BOOTCFG_DBG1 0x00000002 // Debug Control 1 +#define FLASH_BOOTCFG_DBG0 0x00000001 // Debug Control 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USERREG0 register. +// +//***************************************************************************** +#define FLASH_USERREG0_DATA_M 0xFFFFFFFF // User Data +#define FLASH_USERREG0_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USERREG1 register. +// +//***************************************************************************** +#define FLASH_USERREG1_DATA_M 0xFFFFFFFF // User Data +#define FLASH_USERREG1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USERREG2 register. +// +//***************************************************************************** +#define FLASH_USERREG2_DATA_M 0xFFFFFFFF // User Data +#define FLASH_USERREG2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USERREG3 register. +// +//***************************************************************************** +#define FLASH_USERREG3_DATA_M 0xFFFFFFFF // User Data +#define FLASH_USERREG3_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DID0 register. +// +//***************************************************************************** +#define SYSCTL_DID0_VER_M 0x70000000 // DID0 Version +#define SYSCTL_DID0_VER_1 0x10000000 // Second version of the DID0 + // register format. +#define SYSCTL_DID0_CLASS_M 0x00FF0000 // Device Class +#define SYSCTL_DID0_CLASS_TM4C123 \ + 0x00050000 // Tiva TM4C123x and TM4E123x + // microcontrollers +#define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major Revision +#define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device) +#define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer + // revision) +#define SYSCTL_DID0_MAJ_REVC 0x00000200 // Revision C (second base layer + // revision) +#define SYSCTL_DID0_MIN_M 0x000000FF // Minor Revision +#define SYSCTL_DID0_MIN_0 0x00000000 // Initial device, or a major + // revision update +#define SYSCTL_DID0_MIN_1 0x00000001 // First metal layer change +#define SYSCTL_DID0_MIN_2 0x00000002 // Second metal layer change + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DID1 register. +// +//***************************************************************************** +#define SYSCTL_DID1_VER_M 0xF0000000 // DID1 Version +#define SYSCTL_DID1_VER_1 0x10000000 // fury_ib +#define SYSCTL_DID1_FAM_M 0x0F000000 // Family +#define SYSCTL_DID1_FAM_TIVA 0x00000000 // Tiva family of microcontollers +#define SYSCTL_DID1_PRTNO_M 0x00FF0000 // Part Number +#define SYSCTL_DID1_PRTNO_TM4C123GH6PM \ + 0x00A10000 // TM4C123GH6PM +#define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count +#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100-pin LQFP package +#define SYSCTL_DID1_PINCNT_64 0x00006000 // 64-pin LQFP package +#define SYSCTL_DID1_PINCNT_144 0x00008000 // 144-pin LQFP package +#define SYSCTL_DID1_PINCNT_157 0x0000A000 // 157-pin BGA package +#define SYSCTL_DID1_PINCNT_128 0x0000C000 // 128-pin TQFP package +#define SYSCTL_DID1_TEMP_M 0x000000E0 // Temperature Range +#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temperature range +#define SYSCTL_DID1_TEMP_E 0x00000040 // Extended temperature range +#define SYSCTL_DID1_TEMP_IE 0x00000060 // Available in both industrial + // temperature range (-40C to 85C) + // and extended temperature range + // (-40C to 105C) devices. See +#define SYSCTL_DID1_PKG_M 0x00000018 // Package Type +#define SYSCTL_DID1_PKG_QFP 0x00000008 // QFP package +#define SYSCTL_DID1_PKG_BGA 0x00000010 // BGA package +#define SYSCTL_DID1_ROHS 0x00000004 // RoHS-Compliance +#define SYSCTL_DID1_QUAL_M 0x00000003 // Qualification Status +#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering Sample (unqualified) +#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot Production (unqualified) +#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully Qualified + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC0 register. +// +//***************************************************************************** +#define SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 // SRAM Size +#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_6KB 0x00170000 // 6 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_12KB 0x002F0000 // 12 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_20KB 0x004F0000 // 20 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_24KB 0x005F0000 // 24 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM +#define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF // Flash Size +#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of Flash +#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of Flash +#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of Flash +#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of Flash +#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of Flash +#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of Flash +#define SYSCTL_DC0_FLASHSZ_192K 0x0000005F // 192 KB of Flash +#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of Flash + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC1 register. +// +//***************************************************************************** +#define SYSCTL_DC1_WDT1 0x10000000 // Watchdog Timer1 Present +#define SYSCTL_DC1_CAN1 0x02000000 // CAN Module 1 Present +#define SYSCTL_DC1_CAN0 0x01000000 // CAN Module 0 Present +#define SYSCTL_DC1_PWM1 0x00200000 // PWM Module 1 Present +#define SYSCTL_DC1_PWM0 0x00100000 // PWM Module 0 Present +#define SYSCTL_DC1_ADC1 0x00020000 // ADC Module 1 Present +#define SYSCTL_DC1_ADC0 0x00010000 // ADC Module 0 Present +#define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 // System Clock Divider +#define SYSCTL_DC1_MINSYSDIV_80 0x00002000 // Specifies an 80-MHz CPU clock + // with a PLL divider of 2.5 +#define SYSCTL_DC1_MINSYSDIV_50 0x00003000 // Specifies a 50-MHz CPU clock + // with a PLL divider of 4 +#define SYSCTL_DC1_MINSYSDIV_40 0x00004000 // Specifies a 40-MHz CPU clock + // with a PLL divider of 5 +#define SYSCTL_DC1_MINSYSDIV_25 0x00007000 // Specifies a 25-MHz clock with a + // PLL divider of 8 +#define SYSCTL_DC1_MINSYSDIV_20 0x00009000 // Specifies a 20-MHz clock with a + // PLL divider of 10 +#define SYSCTL_DC1_ADC1SPD_M 0x00000C00 // Max ADC1 Speed +#define SYSCTL_DC1_ADC1SPD_125K 0x00000000 // 125K samples/second +#define SYSCTL_DC1_ADC1SPD_250K 0x00000400 // 250K samples/second +#define SYSCTL_DC1_ADC1SPD_500K 0x00000800 // 500K samples/second +#define SYSCTL_DC1_ADC1SPD_1M 0x00000C00 // 1M samples/second +#define SYSCTL_DC1_ADC0SPD_M 0x00000300 // Max ADC0 Speed +#define SYSCTL_DC1_ADC0SPD_125K 0x00000000 // 125K samples/second +#define SYSCTL_DC1_ADC0SPD_250K 0x00000100 // 250K samples/second +#define SYSCTL_DC1_ADC0SPD_500K 0x00000200 // 500K samples/second +#define SYSCTL_DC1_ADC0SPD_1M 0x00000300 // 1M samples/second +#define SYSCTL_DC1_MPU 0x00000080 // MPU Present +#define SYSCTL_DC1_HIB 0x00000040 // Hibernation Module Present +#define SYSCTL_DC1_TEMP 0x00000020 // Temp Sensor Present +#define SYSCTL_DC1_PLL 0x00000010 // PLL Present +#define SYSCTL_DC1_WDT0 0x00000008 // Watchdog Timer 0 Present +#define SYSCTL_DC1_SWO 0x00000004 // SWO Trace Port Present +#define SYSCTL_DC1_SWD 0x00000002 // SWD Present +#define SYSCTL_DC1_JTAG 0x00000001 // JTAG Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC2 register. +// +//***************************************************************************** +#define SYSCTL_DC2_EPI0 0x40000000 // EPI Module 0 Present +#define SYSCTL_DC2_I2S0 0x10000000 // I2S Module 0 Present +#define SYSCTL_DC2_COMP2 0x04000000 // Analog Comparator 2 Present +#define SYSCTL_DC2_COMP1 0x02000000 // Analog Comparator 1 Present +#define SYSCTL_DC2_COMP0 0x01000000 // Analog Comparator 0 Present +#define SYSCTL_DC2_TIMER3 0x00080000 // Timer Module 3 Present +#define SYSCTL_DC2_TIMER2 0x00040000 // Timer Module 2 Present +#define SYSCTL_DC2_TIMER1 0x00020000 // Timer Module 1 Present +#define SYSCTL_DC2_TIMER0 0x00010000 // Timer Module 0 Present +#define SYSCTL_DC2_I2C1HS 0x00008000 // I2C Module 1 Speed +#define SYSCTL_DC2_I2C1 0x00004000 // I2C Module 1 Present +#define SYSCTL_DC2_I2C0HS 0x00002000 // I2C Module 0 Speed +#define SYSCTL_DC2_I2C0 0x00001000 // I2C Module 0 Present +#define SYSCTL_DC2_QEI1 0x00000200 // QEI Module 1 Present +#define SYSCTL_DC2_QEI0 0x00000100 // QEI Module 0 Present +#define SYSCTL_DC2_SSI1 0x00000020 // SSI Module 1 Present +#define SYSCTL_DC2_SSI0 0x00000010 // SSI Module 0 Present +#define SYSCTL_DC2_UART2 0x00000004 // UART Module 2 Present +#define SYSCTL_DC2_UART1 0x00000002 // UART Module 1 Present +#define SYSCTL_DC2_UART0 0x00000001 // UART Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC3 register. +// +//***************************************************************************** +#define SYSCTL_DC3_32KHZ 0x80000000 // 32KHz Input Clock Available +#define SYSCTL_DC3_CCP5 0x20000000 // T2CCP1 Pin Present +#define SYSCTL_DC3_CCP4 0x10000000 // T2CCP0 Pin Present +#define SYSCTL_DC3_CCP3 0x08000000 // T1CCP1 Pin Present +#define SYSCTL_DC3_CCP2 0x04000000 // T1CCP0 Pin Present +#define SYSCTL_DC3_CCP1 0x02000000 // T0CCP1 Pin Present +#define SYSCTL_DC3_CCP0 0x01000000 // T0CCP0 Pin Present +#define SYSCTL_DC3_ADC0AIN7 0x00800000 // ADC Module 0 AIN7 Pin Present +#define SYSCTL_DC3_ADC0AIN6 0x00400000 // ADC Module 0 AIN6 Pin Present +#define SYSCTL_DC3_ADC0AIN5 0x00200000 // ADC Module 0 AIN5 Pin Present +#define SYSCTL_DC3_ADC0AIN4 0x00100000 // ADC Module 0 AIN4 Pin Present +#define SYSCTL_DC3_ADC0AIN3 0x00080000 // ADC Module 0 AIN3 Pin Present +#define SYSCTL_DC3_ADC0AIN2 0x00040000 // ADC Module 0 AIN2 Pin Present +#define SYSCTL_DC3_ADC0AIN1 0x00020000 // ADC Module 0 AIN1 Pin Present +#define SYSCTL_DC3_ADC0AIN0 0x00010000 // ADC Module 0 AIN0 Pin Present +#define SYSCTL_DC3_PWMFAULT 0x00008000 // PWM Fault Pin Present +#define SYSCTL_DC3_C2O 0x00004000 // C2o Pin Present +#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ Pin Present +#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- Pin Present +#define SYSCTL_DC3_C1O 0x00000800 // C1o Pin Present +#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ Pin Present +#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- Pin Present +#define SYSCTL_DC3_C0O 0x00000100 // C0o Pin Present +#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ Pin Present +#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- Pin Present +#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 Pin Present +#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 Pin Present +#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 Pin Present +#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 Pin Present +#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 Pin Present +#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 Pin Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC4 register. +// +//***************************************************************************** +#define SYSCTL_DC4_EPHY0 0x40000000 // Ethernet PHY Layer 0 Present +#define SYSCTL_DC4_EMAC0 0x10000000 // Ethernet MAC Layer 0 Present +#define SYSCTL_DC4_E1588 0x01000000 // 1588 Capable +#define SYSCTL_DC4_PICAL 0x00040000 // PIOSC Calibrate +#define SYSCTL_DC4_CCP7 0x00008000 // T3CCP1 Pin Present +#define SYSCTL_DC4_CCP6 0x00004000 // T3CCP0 Pin Present +#define SYSCTL_DC4_UDMA 0x00002000 // Micro-DMA Module Present +#define SYSCTL_DC4_ROM 0x00001000 // Internal Code ROM Present +#define SYSCTL_DC4_GPIOJ 0x00000100 // GPIO Port J Present +#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO Port H Present +#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO Port G Present +#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO Port F Present +#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO Port E Present +#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO Port D Present +#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO Port C Present +#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO Port B Present +#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO Port A Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC5 register. +// +//***************************************************************************** +#define SYSCTL_DC5_PWMFAULT3 0x08000000 // PWM Fault 3 Pin Present +#define SYSCTL_DC5_PWMFAULT2 0x04000000 // PWM Fault 2 Pin Present +#define SYSCTL_DC5_PWMFAULT1 0x02000000 // PWM Fault 1 Pin Present +#define SYSCTL_DC5_PWMFAULT0 0x01000000 // PWM Fault 0 Pin Present +#define SYSCTL_DC5_PWMEFLT 0x00200000 // PWM Extended Fault Active +#define SYSCTL_DC5_PWMESYNC 0x00100000 // PWM Extended SYNC Active +#define SYSCTL_DC5_PWM7 0x00000080 // PWM7 Pin Present +#define SYSCTL_DC5_PWM6 0x00000040 // PWM6 Pin Present +#define SYSCTL_DC5_PWM5 0x00000020 // PWM5 Pin Present +#define SYSCTL_DC5_PWM4 0x00000010 // PWM4 Pin Present +#define SYSCTL_DC5_PWM3 0x00000008 // PWM3 Pin Present +#define SYSCTL_DC5_PWM2 0x00000004 // PWM2 Pin Present +#define SYSCTL_DC5_PWM1 0x00000002 // PWM1 Pin Present +#define SYSCTL_DC5_PWM0 0x00000001 // PWM0 Pin Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC6 register. +// +//***************************************************************************** +#define SYSCTL_DC6_USB0PHY 0x00000010 // USB Module 0 PHY Present +#define SYSCTL_DC6_USB0_M 0x00000003 // USB Module 0 Present +#define SYSCTL_DC6_USB0_DEV 0x00000001 // USB0 is Device Only +#define SYSCTL_DC6_USB0_HOSTDEV 0x00000002 // USB is Device or Host +#define SYSCTL_DC6_USB0_OTG 0x00000003 // USB0 is OTG + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC7 register. +// +//***************************************************************************** +#define SYSCTL_DC7_DMACH30 0x40000000 // DMA Channel 30 +#define SYSCTL_DC7_DMACH29 0x20000000 // DMA Channel 29 +#define SYSCTL_DC7_DMACH28 0x10000000 // DMA Channel 28 +#define SYSCTL_DC7_DMACH27 0x08000000 // DMA Channel 27 +#define SYSCTL_DC7_DMACH26 0x04000000 // DMA Channel 26 +#define SYSCTL_DC7_DMACH25 0x02000000 // DMA Channel 25 +#define SYSCTL_DC7_DMACH24 0x01000000 // DMA Channel 24 +#define SYSCTL_DC7_DMACH23 0x00800000 // DMA Channel 23 +#define SYSCTL_DC7_DMACH22 0x00400000 // DMA Channel 22 +#define SYSCTL_DC7_DMACH21 0x00200000 // DMA Channel 21 +#define SYSCTL_DC7_DMACH20 0x00100000 // DMA Channel 20 +#define SYSCTL_DC7_DMACH19 0x00080000 // DMA Channel 19 +#define SYSCTL_DC7_DMACH18 0x00040000 // DMA Channel 18 +#define SYSCTL_DC7_DMACH17 0x00020000 // DMA Channel 17 +#define SYSCTL_DC7_DMACH16 0x00010000 // DMA Channel 16 +#define SYSCTL_DC7_DMACH15 0x00008000 // DMA Channel 15 +#define SYSCTL_DC7_DMACH14 0x00004000 // DMA Channel 14 +#define SYSCTL_DC7_DMACH13 0x00002000 // DMA Channel 13 +#define SYSCTL_DC7_DMACH12 0x00001000 // DMA Channel 12 +#define SYSCTL_DC7_DMACH11 0x00000800 // DMA Channel 11 +#define SYSCTL_DC7_DMACH10 0x00000400 // DMA Channel 10 +#define SYSCTL_DC7_DMACH9 0x00000200 // DMA Channel 9 +#define SYSCTL_DC7_DMACH8 0x00000100 // DMA Channel 8 +#define SYSCTL_DC7_DMACH7 0x00000080 // DMA Channel 7 +#define SYSCTL_DC7_DMACH6 0x00000040 // DMA Channel 6 +#define SYSCTL_DC7_DMACH5 0x00000020 // DMA Channel 5 +#define SYSCTL_DC7_DMACH4 0x00000010 // DMA Channel 4 +#define SYSCTL_DC7_DMACH3 0x00000008 // DMA Channel 3 +#define SYSCTL_DC7_DMACH2 0x00000004 // DMA Channel 2 +#define SYSCTL_DC7_DMACH1 0x00000002 // DMA Channel 1 +#define SYSCTL_DC7_DMACH0 0x00000001 // DMA Channel 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC8 register. +// +//***************************************************************************** +#define SYSCTL_DC8_ADC1AIN15 0x80000000 // ADC Module 1 AIN15 Pin Present +#define SYSCTL_DC8_ADC1AIN14 0x40000000 // ADC Module 1 AIN14 Pin Present +#define SYSCTL_DC8_ADC1AIN13 0x20000000 // ADC Module 1 AIN13 Pin Present +#define SYSCTL_DC8_ADC1AIN12 0x10000000 // ADC Module 1 AIN12 Pin Present +#define SYSCTL_DC8_ADC1AIN11 0x08000000 // ADC Module 1 AIN11 Pin Present +#define SYSCTL_DC8_ADC1AIN10 0x04000000 // ADC Module 1 AIN10 Pin Present +#define SYSCTL_DC8_ADC1AIN9 0x02000000 // ADC Module 1 AIN9 Pin Present +#define SYSCTL_DC8_ADC1AIN8 0x01000000 // ADC Module 1 AIN8 Pin Present +#define SYSCTL_DC8_ADC1AIN7 0x00800000 // ADC Module 1 AIN7 Pin Present +#define SYSCTL_DC8_ADC1AIN6 0x00400000 // ADC Module 1 AIN6 Pin Present +#define SYSCTL_DC8_ADC1AIN5 0x00200000 // ADC Module 1 AIN5 Pin Present +#define SYSCTL_DC8_ADC1AIN4 0x00100000 // ADC Module 1 AIN4 Pin Present +#define SYSCTL_DC8_ADC1AIN3 0x00080000 // ADC Module 1 AIN3 Pin Present +#define SYSCTL_DC8_ADC1AIN2 0x00040000 // ADC Module 1 AIN2 Pin Present +#define SYSCTL_DC8_ADC1AIN1 0x00020000 // ADC Module 1 AIN1 Pin Present +#define SYSCTL_DC8_ADC1AIN0 0x00010000 // ADC Module 1 AIN0 Pin Present +#define SYSCTL_DC8_ADC0AIN15 0x00008000 // ADC Module 0 AIN15 Pin Present +#define SYSCTL_DC8_ADC0AIN14 0x00004000 // ADC Module 0 AIN14 Pin Present +#define SYSCTL_DC8_ADC0AIN13 0x00002000 // ADC Module 0 AIN13 Pin Present +#define SYSCTL_DC8_ADC0AIN12 0x00001000 // ADC Module 0 AIN12 Pin Present +#define SYSCTL_DC8_ADC0AIN11 0x00000800 // ADC Module 0 AIN11 Pin Present +#define SYSCTL_DC8_ADC0AIN10 0x00000400 // ADC Module 0 AIN10 Pin Present +#define SYSCTL_DC8_ADC0AIN9 0x00000200 // ADC Module 0 AIN9 Pin Present +#define SYSCTL_DC8_ADC0AIN8 0x00000100 // ADC Module 0 AIN8 Pin Present +#define SYSCTL_DC8_ADC0AIN7 0x00000080 // ADC Module 0 AIN7 Pin Present +#define SYSCTL_DC8_ADC0AIN6 0x00000040 // ADC Module 0 AIN6 Pin Present +#define SYSCTL_DC8_ADC0AIN5 0x00000020 // ADC Module 0 AIN5 Pin Present +#define SYSCTL_DC8_ADC0AIN4 0x00000010 // ADC Module 0 AIN4 Pin Present +#define SYSCTL_DC8_ADC0AIN3 0x00000008 // ADC Module 0 AIN3 Pin Present +#define SYSCTL_DC8_ADC0AIN2 0x00000004 // ADC Module 0 AIN2 Pin Present +#define SYSCTL_DC8_ADC0AIN1 0x00000002 // ADC Module 0 AIN1 Pin Present +#define SYSCTL_DC8_ADC0AIN0 0x00000001 // ADC Module 0 AIN0 Pin Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PBORCTL register. +// +//***************************************************************************** +#define SYSCTL_PBORCTL_BOR0 0x00000004 // VDD under BOR0 Event Action +#define SYSCTL_PBORCTL_BOR1 0x00000002 // VDD under BOR1 Event Action + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCR0 register. +// +//***************************************************************************** +#define SYSCTL_SRCR0_WDT1 0x10000000 // WDT1 Reset Control +#define SYSCTL_SRCR0_CAN1 0x02000000 // CAN1 Reset Control +#define SYSCTL_SRCR0_CAN0 0x01000000 // CAN0 Reset Control +#define SYSCTL_SRCR0_PWM0 0x00100000 // PWM Reset Control +#define SYSCTL_SRCR0_ADC1 0x00020000 // ADC1 Reset Control +#define SYSCTL_SRCR0_ADC0 0x00010000 // ADC0 Reset Control +#define SYSCTL_SRCR0_HIB 0x00000040 // HIB Reset Control +#define SYSCTL_SRCR0_WDT0 0x00000008 // WDT0 Reset Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCR1 register. +// +//***************************************************************************** +#define SYSCTL_SRCR1_COMP1 0x02000000 // Analog Comp 1 Reset Control +#define SYSCTL_SRCR1_COMP0 0x01000000 // Analog Comp 0 Reset Control +#define SYSCTL_SRCR1_TIMER3 0x00080000 // Timer 3 Reset Control +#define SYSCTL_SRCR1_TIMER2 0x00040000 // Timer 2 Reset Control +#define SYSCTL_SRCR1_TIMER1 0x00020000 // Timer 1 Reset Control +#define SYSCTL_SRCR1_TIMER0 0x00010000 // Timer 0 Reset Control +#define SYSCTL_SRCR1_I2C1 0x00004000 // I2C1 Reset Control +#define SYSCTL_SRCR1_I2C0 0x00001000 // I2C0 Reset Control +#define SYSCTL_SRCR1_QEI1 0x00000200 // QEI1 Reset Control +#define SYSCTL_SRCR1_QEI0 0x00000100 // QEI0 Reset Control +#define SYSCTL_SRCR1_SSI1 0x00000020 // SSI1 Reset Control +#define SYSCTL_SRCR1_SSI0 0x00000010 // SSI0 Reset Control +#define SYSCTL_SRCR1_UART2 0x00000004 // UART2 Reset Control +#define SYSCTL_SRCR1_UART1 0x00000002 // UART1 Reset Control +#define SYSCTL_SRCR1_UART0 0x00000001 // UART0 Reset Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCR2 register. +// +//***************************************************************************** +#define SYSCTL_SRCR2_USB0 0x00010000 // USB0 Reset Control +#define SYSCTL_SRCR2_UDMA 0x00002000 // Micro-DMA Reset Control +#define SYSCTL_SRCR2_GPIOF 0x00000020 // Port F Reset Control +#define SYSCTL_SRCR2_GPIOE 0x00000010 // Port E Reset Control +#define SYSCTL_SRCR2_GPIOD 0x00000008 // Port D Reset Control +#define SYSCTL_SRCR2_GPIOC 0x00000004 // Port C Reset Control +#define SYSCTL_SRCR2_GPIOB 0x00000002 // Port B Reset Control +#define SYSCTL_SRCR2_GPIOA 0x00000001 // Port A Reset Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RIS register. +// +//***************************************************************************** +#define SYSCTL_RIS_BOR0RIS 0x00000800 // VDD under BOR0 Raw Interrupt + // Status +#define SYSCTL_RIS_VDDARIS 0x00000400 // VDDA Power OK Event Raw + // Interrupt Status +#define SYSCTL_RIS_MOSCPUPRIS 0x00000100 // MOSC Power Up Raw Interrupt + // Status +#define SYSCTL_RIS_USBPLLLRIS 0x00000080 // USB PLL Lock Raw Interrupt + // Status +#define SYSCTL_RIS_PLLLRIS 0x00000040 // PLL Lock Raw Interrupt Status +#define SYSCTL_RIS_MOFRIS 0x00000008 // Main Oscillator Failure Raw + // Interrupt Status +#define SYSCTL_RIS_BOR1RIS 0x00000002 // VDD under BOR1 Raw Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_IMC register. +// +//***************************************************************************** +#define SYSCTL_IMC_BOR0IM 0x00000800 // VDD under BOR0 Interrupt Mask +#define SYSCTL_IMC_VDDAIM 0x00000400 // VDDA Power OK Interrupt Mask +#define SYSCTL_IMC_MOSCPUPIM 0x00000100 // MOSC Power Up Interrupt Mask +#define SYSCTL_IMC_USBPLLLIM 0x00000080 // USB PLL Lock Interrupt Mask +#define SYSCTL_IMC_PLLLIM 0x00000040 // PLL Lock Interrupt Mask +#define SYSCTL_IMC_MOFIM 0x00000008 // Main Oscillator Failure + // Interrupt Mask +#define SYSCTL_IMC_BOR1IM 0x00000002 // VDD under BOR1 Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_MISC register. +// +//***************************************************************************** +#define SYSCTL_MISC_BOR0MIS 0x00000800 // VDD under BOR0 Masked Interrupt + // Status +#define SYSCTL_MISC_VDDAMIS 0x00000400 // VDDA Power OK Masked Interrupt + // Status +#define SYSCTL_MISC_MOSCPUPMIS 0x00000100 // MOSC Power Up Masked Interrupt + // Status +#define SYSCTL_MISC_USBPLLLMIS 0x00000080 // USB PLL Lock Masked Interrupt + // Status +#define SYSCTL_MISC_PLLLMIS 0x00000040 // PLL Lock Masked Interrupt Status +#define SYSCTL_MISC_MOFMIS 0x00000008 // Main Oscillator Failure Masked + // Interrupt Status +#define SYSCTL_MISC_BOR1MIS 0x00000002 // VDD under BOR1 Masked Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RESC register. +// +//***************************************************************************** +#define SYSCTL_RESC_MOSCFAIL 0x00010000 // MOSC Failure Reset +#define SYSCTL_RESC_WDT1 0x00000020 // Watchdog Timer 1 Reset +#define SYSCTL_RESC_SW 0x00000010 // Software Reset +#define SYSCTL_RESC_WDT0 0x00000008 // Watchdog Timer 0 Reset +#define SYSCTL_RESC_BOR 0x00000004 // Brown-Out Reset +#define SYSCTL_RESC_POR 0x00000002 // Power-On Reset +#define SYSCTL_RESC_EXT 0x00000001 // External Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCC register. +// +//***************************************************************************** +#define SYSCTL_RCC_ACG 0x08000000 // Auto Clock Gating +#define SYSCTL_RCC_SYSDIV_M 0x07800000 // System Clock Divisor +#define SYSCTL_RCC_USESYSDIV 0x00400000 // Enable System Clock Divider +#define SYSCTL_RCC_USEPWMDIV 0x00100000 // Enable PWM Clock Divisor +#define SYSCTL_RCC_PWMDIV_M 0x000E0000 // PWM Unit Clock Divisor +#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2 +#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4 +#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8 +#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16 +#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32 +#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64 +#define SYSCTL_RCC_PWRDN 0x00002000 // PLL Power Down +#define SYSCTL_RCC_BYPASS 0x00000800 // PLL Bypass +#define SYSCTL_RCC_XTAL_M 0x000007C0 // Crystal Value +#define SYSCTL_RCC_XTAL_4MHZ 0x00000180 // 4 MHz +#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // 4.096 MHz +#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // 4.9152 MHz +#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // 5 MHz +#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // 5.12 MHz +#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // 6 MHz +#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // 6.144 MHz +#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // 7.3728 MHz +#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // 8 MHz +#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // 8.192 MHz +#define SYSCTL_RCC_XTAL_10MHZ 0x00000400 // 10 MHz +#define SYSCTL_RCC_XTAL_12MHZ 0x00000440 // 12 MHz +#define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480 // 12.288 MHz +#define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0 // 13.56 MHz +#define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500 // 14.31818 MHz +#define SYSCTL_RCC_XTAL_16MHZ 0x00000540 // 16 MHz +#define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580 // 16.384 MHz +#define SYSCTL_RCC_XTAL_18MHZ 0x000005C0 // 18.0 MHz (USB) +#define SYSCTL_RCC_XTAL_20MHZ 0x00000600 // 20.0 MHz (USB) +#define SYSCTL_RCC_XTAL_24MHZ 0x00000640 // 24.0 MHz (USB) +#define SYSCTL_RCC_XTAL_25MHZ 0x00000680 // 25.0 MHz (USB) +#define SYSCTL_RCC_OSCSRC_M 0x00000030 // Oscillator Source +#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // MOSC +#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // IOSC +#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // IOSC/4 +#define SYSCTL_RCC_OSCSRC_30 0x00000030 // LFIOSC +#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main Oscillator Disable +#define SYSCTL_RCC_SYSDIV_S 23 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_GPIOHBCTL +// register. +// +//***************************************************************************** +#define SYSCTL_GPIOHBCTL_PORTF 0x00000020 // Port F Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTE 0x00000010 // Port E Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTD 0x00000008 // Port D Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTC 0x00000004 // Port C Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTB 0x00000002 // Port B Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTA 0x00000001 // Port A Advanced High-Performance + // Bus + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCC2 register. +// +//***************************************************************************** +#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2 +#define SYSCTL_RCC2_DIV400 0x40000000 // Divide PLL as 400 MHz vs. 200 + // MHz +#define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 // System Clock Divisor 2 +#define SYSCTL_RCC2_SYSDIV2LSB 0x00400000 // Additional LSB for SYSDIV2 +#define SYSCTL_RCC2_USBPWRDN 0x00004000 // Power-Down USB PLL +#define SYSCTL_RCC2_PWRDN2 0x00002000 // Power-Down PLL 2 +#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL Bypass 2 +#define SYSCTL_RCC2_OSCSRC2_M 0x00000070 // Oscillator Source 2 +#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // MOSC +#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // PIOSC +#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // PIOSC/4 +#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // LFIOSC +#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // 32.768 kHz +#define SYSCTL_RCC2_SYSDIV2_S 23 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_MOSCCTL register. +// +//***************************************************************************** +#define SYSCTL_MOSCCTL_NOXTAL 0x00000004 // No Crystal Connected +#define SYSCTL_MOSCCTL_MOSCIM 0x00000002 // MOSC Failure Action +#define SYSCTL_MOSCCTL_CVAL 0x00000001 // Clock Validation for MOSC + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGC0 register. +// +//***************************************************************************** +#define SYSCTL_RCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control +#define SYSCTL_RCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control +#define SYSCTL_RCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control +#define SYSCTL_RCGC0_PWM0 0x00100000 // PWM Clock Gating Control +#define SYSCTL_RCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control +#define SYSCTL_RCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control +#define SYSCTL_RCGC0_ADC1SPD_M 0x00000C00 // ADC1 Sample Speed +#define SYSCTL_RCGC0_ADC1SPD_125K \ + 0x00000000 // 125K samples/second +#define SYSCTL_RCGC0_ADC1SPD_250K \ + 0x00000400 // 250K samples/second +#define SYSCTL_RCGC0_ADC1SPD_500K \ + 0x00000800 // 500K samples/second +#define SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00 // 1M samples/second +#define SYSCTL_RCGC0_ADC0SPD_M 0x00000300 // ADC0 Sample Speed +#define SYSCTL_RCGC0_ADC0SPD_125K \ + 0x00000000 // 125K samples/second +#define SYSCTL_RCGC0_ADC0SPD_250K \ + 0x00000100 // 250K samples/second +#define SYSCTL_RCGC0_ADC0SPD_500K \ + 0x00000200 // 500K samples/second +#define SYSCTL_RCGC0_ADC0SPD_1M 0x00000300 // 1M samples/second +#define SYSCTL_RCGC0_HIB 0x00000040 // HIB Clock Gating Control +#define SYSCTL_RCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGC1 register. +// +//***************************************************************************** +#define SYSCTL_RCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating +#define SYSCTL_RCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating +#define SYSCTL_RCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control +#define SYSCTL_RCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control +#define SYSCTL_RCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control +#define SYSCTL_RCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control +#define SYSCTL_RCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control +#define SYSCTL_RCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control +#define SYSCTL_RCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control +#define SYSCTL_RCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control +#define SYSCTL_RCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control +#define SYSCTL_RCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control +#define SYSCTL_RCGC1_UART2 0x00000004 // UART2 Clock Gating Control +#define SYSCTL_RCGC1_UART1 0x00000002 // UART1 Clock Gating Control +#define SYSCTL_RCGC1_UART0 0x00000001 // UART0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGC2 register. +// +//***************************************************************************** +#define SYSCTL_RCGC2_USB0 0x00010000 // USB0 Clock Gating Control +#define SYSCTL_RCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control +#define SYSCTL_RCGC2_GPIOF 0x00000020 // Port F Clock Gating Control +#define SYSCTL_RCGC2_GPIOE 0x00000010 // Port E Clock Gating Control +#define SYSCTL_RCGC2_GPIOD 0x00000008 // Port D Clock Gating Control +#define SYSCTL_RCGC2_GPIOC 0x00000004 // Port C Clock Gating Control +#define SYSCTL_RCGC2_GPIOB 0x00000002 // Port B Clock Gating Control +#define SYSCTL_RCGC2_GPIOA 0x00000001 // Port A Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGC0 register. +// +//***************************************************************************** +#define SYSCTL_SCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control +#define SYSCTL_SCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control +#define SYSCTL_SCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control +#define SYSCTL_SCGC0_PWM0 0x00100000 // PWM Clock Gating Control +#define SYSCTL_SCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control +#define SYSCTL_SCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control +#define SYSCTL_SCGC0_HIB 0x00000040 // HIB Clock Gating Control +#define SYSCTL_SCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGC1 register. +// +//***************************************************************************** +#define SYSCTL_SCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating +#define SYSCTL_SCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating +#define SYSCTL_SCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control +#define SYSCTL_SCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control +#define SYSCTL_SCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control +#define SYSCTL_SCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control +#define SYSCTL_SCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control +#define SYSCTL_SCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control +#define SYSCTL_SCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control +#define SYSCTL_SCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control +#define SYSCTL_SCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control +#define SYSCTL_SCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control +#define SYSCTL_SCGC1_UART2 0x00000004 // UART2 Clock Gating Control +#define SYSCTL_SCGC1_UART1 0x00000002 // UART1 Clock Gating Control +#define SYSCTL_SCGC1_UART0 0x00000001 // UART0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGC2 register. +// +//***************************************************************************** +#define SYSCTL_SCGC2_USB0 0x00010000 // USB0 Clock Gating Control +#define SYSCTL_SCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control +#define SYSCTL_SCGC2_GPIOF 0x00000020 // Port F Clock Gating Control +#define SYSCTL_SCGC2_GPIOE 0x00000010 // Port E Clock Gating Control +#define SYSCTL_SCGC2_GPIOD 0x00000008 // Port D Clock Gating Control +#define SYSCTL_SCGC2_GPIOC 0x00000004 // Port C Clock Gating Control +#define SYSCTL_SCGC2_GPIOB 0x00000002 // Port B Clock Gating Control +#define SYSCTL_SCGC2_GPIOA 0x00000001 // Port A Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGC0 register. +// +//***************************************************************************** +#define SYSCTL_DCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control +#define SYSCTL_DCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control +#define SYSCTL_DCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control +#define SYSCTL_DCGC0_PWM0 0x00100000 // PWM Clock Gating Control +#define SYSCTL_DCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control +#define SYSCTL_DCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control +#define SYSCTL_DCGC0_HIB 0x00000040 // HIB Clock Gating Control +#define SYSCTL_DCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGC1 register. +// +//***************************************************************************** +#define SYSCTL_DCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating +#define SYSCTL_DCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating +#define SYSCTL_DCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control +#define SYSCTL_DCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control +#define SYSCTL_DCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control +#define SYSCTL_DCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control +#define SYSCTL_DCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control +#define SYSCTL_DCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control +#define SYSCTL_DCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control +#define SYSCTL_DCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control +#define SYSCTL_DCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control +#define SYSCTL_DCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control +#define SYSCTL_DCGC1_UART2 0x00000004 // UART2 Clock Gating Control +#define SYSCTL_DCGC1_UART1 0x00000002 // UART1 Clock Gating Control +#define SYSCTL_DCGC1_UART0 0x00000001 // UART0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGC2 register. +// +//***************************************************************************** +#define SYSCTL_DCGC2_USB0 0x00010000 // USB0 Clock Gating Control +#define SYSCTL_DCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control +#define SYSCTL_DCGC2_GPIOF 0x00000020 // Port F Clock Gating Control +#define SYSCTL_DCGC2_GPIOE 0x00000010 // Port E Clock Gating Control +#define SYSCTL_DCGC2_GPIOD 0x00000008 // Port D Clock Gating Control +#define SYSCTL_DCGC2_GPIOC 0x00000004 // Port C Clock Gating Control +#define SYSCTL_DCGC2_GPIOB 0x00000002 // Port B Clock Gating Control +#define SYSCTL_DCGC2_GPIOA 0x00000001 // Port A Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG +// register. +// +//***************************************************************************** +#define SYSCTL_DSLPCLKCFG_D_M 0x1F800000 // Divider Field Override +#define SYSCTL_DSLPCLKCFG_O_M 0x00000070 // Clock Source +#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // MOSC +#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // PIOSC +#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // LFIOSC +#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // 32.768 kHz +#define SYSCTL_DSLPCLKCFG_PIOSCPD \ + 0x00000002 // PIOSC Power Down Request +#define SYSCTL_DSLPCLKCFG_D_S 23 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SYSPROP register. +// +//***************************************************************************** +#define SYSCTL_SYSPROP_FPU 0x00000001 // FPU Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PIOSCCAL +// register. +// +//***************************************************************************** +#define SYSCTL_PIOSCCAL_UTEN 0x80000000 // Use User Trim Value +#define SYSCTL_PIOSCCAL_CAL 0x00000200 // Start Calibration +#define SYSCTL_PIOSCCAL_UPDATE 0x00000100 // Update Trim +#define SYSCTL_PIOSCCAL_UT_M 0x0000007F // User Trim Value +#define SYSCTL_PIOSCCAL_UT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PIOSCSTAT +// register. +// +//***************************************************************************** +#define SYSCTL_PIOSCSTAT_DT_M 0x007F0000 // Default Trim Value +#define SYSCTL_PIOSCSTAT_CR_M 0x00000300 // Calibration Result +#define SYSCTL_PIOSCSTAT_CRNONE 0x00000000 // Calibration has not been + // attempted +#define SYSCTL_PIOSCSTAT_CRPASS 0x00000100 // The last calibration operation + // completed to meet 1% accuracy +#define SYSCTL_PIOSCSTAT_CRFAIL 0x00000200 // The last calibration operation + // failed to meet 1% accuracy +#define SYSCTL_PIOSCSTAT_CT_M 0x0000007F // Calibration Trim Value +#define SYSCTL_PIOSCSTAT_DT_S 16 +#define SYSCTL_PIOSCSTAT_CT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PLLFREQ0 +// register. +// +//***************************************************************************** +#define SYSCTL_PLLFREQ0_MFRAC_M 0x000FFC00 // PLL M Fractional Value +#define SYSCTL_PLLFREQ0_MINT_M 0x000003FF // PLL M Integer Value +#define SYSCTL_PLLFREQ0_MFRAC_S 10 +#define SYSCTL_PLLFREQ0_MINT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PLLFREQ1 +// register. +// +//***************************************************************************** +#define SYSCTL_PLLFREQ1_Q_M 0x00001F00 // PLL Q Value +#define SYSCTL_PLLFREQ1_N_M 0x0000001F // PLL N Value +#define SYSCTL_PLLFREQ1_Q_S 8 +#define SYSCTL_PLLFREQ1_N_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PLLSTAT register. +// +//***************************************************************************** +#define SYSCTL_PLLSTAT_LOCK 0x00000001 // PLL Lock + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SLPPWRCFG +// register. +// +//***************************************************************************** +#define SYSCTL_SLPPWRCFG_FLASHPM_M \ + 0x00000030 // Flash Power Modes +#define SYSCTL_SLPPWRCFG_FLASHPM_NRM \ + 0x00000000 // Active Mode +#define SYSCTL_SLPPWRCFG_FLASHPM_SLP \ + 0x00000020 // Low Power Mode +#define SYSCTL_SLPPWRCFG_SRAMPM_M \ + 0x00000003 // SRAM Power Modes +#define SYSCTL_SLPPWRCFG_SRAMPM_NRM \ + 0x00000000 // Active Mode +#define SYSCTL_SLPPWRCFG_SRAMPM_SBY \ + 0x00000001 // Standby Mode +#define SYSCTL_SLPPWRCFG_SRAMPM_LP \ + 0x00000003 // Low Power Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DSLPPWRCFG +// register. +// +//***************************************************************************** +#define SYSCTL_DSLPPWRCFG_FLASHPM_M \ + 0x00000030 // Flash Power Modes +#define SYSCTL_DSLPPWRCFG_FLASHPM_NRM \ + 0x00000000 // Active Mode +#define SYSCTL_DSLPPWRCFG_FLASHPM_SLP \ + 0x00000020 // Low Power Mode +#define SYSCTL_DSLPPWRCFG_SRAMPM_M \ + 0x00000003 // SRAM Power Modes +#define SYSCTL_DSLPPWRCFG_SRAMPM_NRM \ + 0x00000000 // Active Mode +#define SYSCTL_DSLPPWRCFG_SRAMPM_SBY \ + 0x00000001 // Standby Mode +#define SYSCTL_DSLPPWRCFG_SRAMPM_LP \ + 0x00000003 // Low Power Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC9 register. +// +//***************************************************************************** +#define SYSCTL_DC9_ADC1DC7 0x00800000 // ADC1 DC7 Present +#define SYSCTL_DC9_ADC1DC6 0x00400000 // ADC1 DC6 Present +#define SYSCTL_DC9_ADC1DC5 0x00200000 // ADC1 DC5 Present +#define SYSCTL_DC9_ADC1DC4 0x00100000 // ADC1 DC4 Present +#define SYSCTL_DC9_ADC1DC3 0x00080000 // ADC1 DC3 Present +#define SYSCTL_DC9_ADC1DC2 0x00040000 // ADC1 DC2 Present +#define SYSCTL_DC9_ADC1DC1 0x00020000 // ADC1 DC1 Present +#define SYSCTL_DC9_ADC1DC0 0x00010000 // ADC1 DC0 Present +#define SYSCTL_DC9_ADC0DC7 0x00000080 // ADC0 DC7 Present +#define SYSCTL_DC9_ADC0DC6 0x00000040 // ADC0 DC6 Present +#define SYSCTL_DC9_ADC0DC5 0x00000020 // ADC0 DC5 Present +#define SYSCTL_DC9_ADC0DC4 0x00000010 // ADC0 DC4 Present +#define SYSCTL_DC9_ADC0DC3 0x00000008 // ADC0 DC3 Present +#define SYSCTL_DC9_ADC0DC2 0x00000004 // ADC0 DC2 Present +#define SYSCTL_DC9_ADC0DC1 0x00000002 // ADC0 DC1 Present +#define SYSCTL_DC9_ADC0DC0 0x00000001 // ADC0 DC0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_NVMSTAT register. +// +//***************************************************************************** +#define SYSCTL_NVMSTAT_FWB 0x00000001 // 32 Word Flash Write Buffer + // Available + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_LDOSPCTL +// register. +// +//***************************************************************************** +#define SYSCTL_LDOSPCTL_VADJEN 0x80000000 // Voltage Adjust Enable +#define SYSCTL_LDOSPCTL_VLDO_M 0x000000FF // LDO Output Voltage +#define SYSCTL_LDOSPCTL_VLDO_0_90V \ + 0x00000012 // 0.90 V +#define SYSCTL_LDOSPCTL_VLDO_0_95V \ + 0x00000013 // 0.95 V +#define SYSCTL_LDOSPCTL_VLDO_1_00V \ + 0x00000014 // 1.00 V +#define SYSCTL_LDOSPCTL_VLDO_1_05V \ + 0x00000015 // 1.05 V +#define SYSCTL_LDOSPCTL_VLDO_1_10V \ + 0x00000016 // 1.10 V +#define SYSCTL_LDOSPCTL_VLDO_1_15V \ + 0x00000017 // 1.15 V +#define SYSCTL_LDOSPCTL_VLDO_1_20V \ + 0x00000018 // 1.20 V + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_LDODPCTL +// register. +// +//***************************************************************************** +#define SYSCTL_LDODPCTL_VADJEN 0x80000000 // Voltage Adjust Enable +#define SYSCTL_LDODPCTL_VLDO_M 0x000000FF // LDO Output Voltage +#define SYSCTL_LDODPCTL_VLDO_0_90V \ + 0x00000012 // 0.90 V +#define SYSCTL_LDODPCTL_VLDO_0_95V \ + 0x00000013 // 0.95 V +#define SYSCTL_LDODPCTL_VLDO_1_00V \ + 0x00000014 // 1.00 V +#define SYSCTL_LDODPCTL_VLDO_1_05V \ + 0x00000015 // 1.05 V +#define SYSCTL_LDODPCTL_VLDO_1_10V \ + 0x00000016 // 1.10 V +#define SYSCTL_LDODPCTL_VLDO_1_15V \ + 0x00000017 // 1.15 V +#define SYSCTL_LDODPCTL_VLDO_1_20V \ + 0x00000018 // 1.20 V + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPWD register. +// +//***************************************************************************** +#define SYSCTL_PPWD_P1 0x00000002 // Watchdog Timer 1 Present +#define SYSCTL_PPWD_P0 0x00000001 // Watchdog Timer 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPTIMER register. +// +//***************************************************************************** +#define SYSCTL_PPTIMER_P5 0x00000020 // 16/32-Bit General-Purpose Timer + // 5 Present +#define SYSCTL_PPTIMER_P4 0x00000010 // 16/32-Bit General-Purpose Timer + // 4 Present +#define SYSCTL_PPTIMER_P3 0x00000008 // 16/32-Bit General-Purpose Timer + // 3 Present +#define SYSCTL_PPTIMER_P2 0x00000004 // 16/32-Bit General-Purpose Timer + // 2 Present +#define SYSCTL_PPTIMER_P1 0x00000002 // 16/32-Bit General-Purpose Timer + // 1 Present +#define SYSCTL_PPTIMER_P0 0x00000001 // 16/32-Bit General-Purpose Timer + // 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPGPIO register. +// +//***************************************************************************** +#define SYSCTL_PPGPIO_P14 0x00004000 // GPIO Port Q Present +#define SYSCTL_PPGPIO_P13 0x00002000 // GPIO Port P Present +#define SYSCTL_PPGPIO_P12 0x00001000 // GPIO Port N Present +#define SYSCTL_PPGPIO_P11 0x00000800 // GPIO Port M Present +#define SYSCTL_PPGPIO_P10 0x00000400 // GPIO Port L Present +#define SYSCTL_PPGPIO_P9 0x00000200 // GPIO Port K Present +#define SYSCTL_PPGPIO_P8 0x00000100 // GPIO Port J Present +#define SYSCTL_PPGPIO_P7 0x00000080 // GPIO Port H Present +#define SYSCTL_PPGPIO_P6 0x00000040 // GPIO Port G Present +#define SYSCTL_PPGPIO_P5 0x00000020 // GPIO Port F Present +#define SYSCTL_PPGPIO_P4 0x00000010 // GPIO Port E Present +#define SYSCTL_PPGPIO_P3 0x00000008 // GPIO Port D Present +#define SYSCTL_PPGPIO_P2 0x00000004 // GPIO Port C Present +#define SYSCTL_PPGPIO_P1 0x00000002 // GPIO Port B Present +#define SYSCTL_PPGPIO_P0 0x00000001 // GPIO Port A Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPDMA register. +// +//***************************************************************************** +#define SYSCTL_PPDMA_P0 0x00000001 // uDMA Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPHIB register. +// +//***************************************************************************** +#define SYSCTL_PPHIB_P0 0x00000001 // Hibernation Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPUART register. +// +//***************************************************************************** +#define SYSCTL_PPUART_P7 0x00000080 // UART Module 7 Present +#define SYSCTL_PPUART_P6 0x00000040 // UART Module 6 Present +#define SYSCTL_PPUART_P5 0x00000020 // UART Module 5 Present +#define SYSCTL_PPUART_P4 0x00000010 // UART Module 4 Present +#define SYSCTL_PPUART_P3 0x00000008 // UART Module 3 Present +#define SYSCTL_PPUART_P2 0x00000004 // UART Module 2 Present +#define SYSCTL_PPUART_P1 0x00000002 // UART Module 1 Present +#define SYSCTL_PPUART_P0 0x00000001 // UART Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPSSI register. +// +//***************************************************************************** +#define SYSCTL_PPSSI_P3 0x00000008 // SSI Module 3 Present +#define SYSCTL_PPSSI_P2 0x00000004 // SSI Module 2 Present +#define SYSCTL_PPSSI_P1 0x00000002 // SSI Module 1 Present +#define SYSCTL_PPSSI_P0 0x00000001 // SSI Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPI2C register. +// +//***************************************************************************** +#define SYSCTL_PPI2C_P5 0x00000020 // I2C Module 5 Present +#define SYSCTL_PPI2C_P4 0x00000010 // I2C Module 4 Present +#define SYSCTL_PPI2C_P3 0x00000008 // I2C Module 3 Present +#define SYSCTL_PPI2C_P2 0x00000004 // I2C Module 2 Present +#define SYSCTL_PPI2C_P1 0x00000002 // I2C Module 1 Present +#define SYSCTL_PPI2C_P0 0x00000001 // I2C Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPUSB register. +// +//***************************************************************************** +#define SYSCTL_PPUSB_P0 0x00000001 // USB Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPCAN register. +// +//***************************************************************************** +#define SYSCTL_PPCAN_P1 0x00000002 // CAN Module 1 Present +#define SYSCTL_PPCAN_P0 0x00000001 // CAN Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPADC register. +// +//***************************************************************************** +#define SYSCTL_PPADC_P1 0x00000002 // ADC Module 1 Present +#define SYSCTL_PPADC_P0 0x00000001 // ADC Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPACMP register. +// +//***************************************************************************** +#define SYSCTL_PPACMP_P0 0x00000001 // Analog Comparator Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPPWM register. +// +//***************************************************************************** +#define SYSCTL_PPPWM_P1 0x00000002 // PWM Module 1 Present +#define SYSCTL_PPPWM_P0 0x00000001 // PWM Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPQEI register. +// +//***************************************************************************** +#define SYSCTL_PPQEI_P1 0x00000002 // QEI Module 1 Present +#define SYSCTL_PPQEI_P0 0x00000001 // QEI Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPEEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_PPEEPROM_P0 0x00000001 // EEPROM Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_PPWTIMER_P5 0x00000020 // 32/64-Bit Wide General-Purpose + // Timer 5 Present +#define SYSCTL_PPWTIMER_P4 0x00000010 // 32/64-Bit Wide General-Purpose + // Timer 4 Present +#define SYSCTL_PPWTIMER_P3 0x00000008 // 32/64-Bit Wide General-Purpose + // Timer 3 Present +#define SYSCTL_PPWTIMER_P2 0x00000004 // 32/64-Bit Wide General-Purpose + // Timer 2 Present +#define SYSCTL_PPWTIMER_P1 0x00000002 // 32/64-Bit Wide General-Purpose + // Timer 1 Present +#define SYSCTL_PPWTIMER_P0 0x00000001 // 32/64-Bit Wide General-Purpose + // Timer 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRWD register. +// +//***************************************************************************** +#define SYSCTL_SRWD_R1 0x00000002 // Watchdog Timer 1 Software Reset +#define SYSCTL_SRWD_R0 0x00000001 // Watchdog Timer 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRTIMER register. +// +//***************************************************************************** +#define SYSCTL_SRTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer + // 5 Software Reset +#define SYSCTL_SRTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer + // 4 Software Reset +#define SYSCTL_SRTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer + // 3 Software Reset +#define SYSCTL_SRTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer + // 2 Software Reset +#define SYSCTL_SRTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer + // 1 Software Reset +#define SYSCTL_SRTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer + // 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRGPIO register. +// +//***************************************************************************** +#define SYSCTL_SRGPIO_R5 0x00000020 // GPIO Port F Software Reset +#define SYSCTL_SRGPIO_R4 0x00000010 // GPIO Port E Software Reset +#define SYSCTL_SRGPIO_R3 0x00000008 // GPIO Port D Software Reset +#define SYSCTL_SRGPIO_R2 0x00000004 // GPIO Port C Software Reset +#define SYSCTL_SRGPIO_R1 0x00000002 // GPIO Port B Software Reset +#define SYSCTL_SRGPIO_R0 0x00000001 // GPIO Port A Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRDMA register. +// +//***************************************************************************** +#define SYSCTL_SRDMA_R0 0x00000001 // uDMA Module Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRHIB register. +// +//***************************************************************************** +#define SYSCTL_SRHIB_R0 0x00000001 // Hibernation Module Software + // Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRUART register. +// +//***************************************************************************** +#define SYSCTL_SRUART_R7 0x00000080 // UART Module 7 Software Reset +#define SYSCTL_SRUART_R6 0x00000040 // UART Module 6 Software Reset +#define SYSCTL_SRUART_R5 0x00000020 // UART Module 5 Software Reset +#define SYSCTL_SRUART_R4 0x00000010 // UART Module 4 Software Reset +#define SYSCTL_SRUART_R3 0x00000008 // UART Module 3 Software Reset +#define SYSCTL_SRUART_R2 0x00000004 // UART Module 2 Software Reset +#define SYSCTL_SRUART_R1 0x00000002 // UART Module 1 Software Reset +#define SYSCTL_SRUART_R0 0x00000001 // UART Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRSSI register. +// +//***************************************************************************** +#define SYSCTL_SRSSI_R3 0x00000008 // SSI Module 3 Software Reset +#define SYSCTL_SRSSI_R2 0x00000004 // SSI Module 2 Software Reset +#define SYSCTL_SRSSI_R1 0x00000002 // SSI Module 1 Software Reset +#define SYSCTL_SRSSI_R0 0x00000001 // SSI Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRI2C register. +// +//***************************************************************************** +#define SYSCTL_SRI2C_R3 0x00000008 // I2C Module 3 Software Reset +#define SYSCTL_SRI2C_R2 0x00000004 // I2C Module 2 Software Reset +#define SYSCTL_SRI2C_R1 0x00000002 // I2C Module 1 Software Reset +#define SYSCTL_SRI2C_R0 0x00000001 // I2C Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRUSB register. +// +//***************************************************************************** +#define SYSCTL_SRUSB_R0 0x00000001 // USB Module Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCAN register. +// +//***************************************************************************** +#define SYSCTL_SRCAN_R1 0x00000002 // CAN Module 1 Software Reset +#define SYSCTL_SRCAN_R0 0x00000001 // CAN Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRADC register. +// +//***************************************************************************** +#define SYSCTL_SRADC_R1 0x00000002 // ADC Module 1 Software Reset +#define SYSCTL_SRADC_R0 0x00000001 // ADC Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRACMP register. +// +//***************************************************************************** +#define SYSCTL_SRACMP_R0 0x00000001 // Analog Comparator Module 0 + // Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRPWM register. +// +//***************************************************************************** +#define SYSCTL_SRPWM_R1 0x00000002 // PWM Module 1 Software Reset +#define SYSCTL_SRPWM_R0 0x00000001 // PWM Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRQEI register. +// +//***************************************************************************** +#define SYSCTL_SRQEI_R1 0x00000002 // QEI Module 1 Software Reset +#define SYSCTL_SRQEI_R0 0x00000001 // QEI Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SREEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_SREEPROM_R0 0x00000001 // EEPROM Module Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_SRWTIMER_R5 0x00000020 // 32/64-Bit Wide General-Purpose + // Timer 5 Software Reset +#define SYSCTL_SRWTIMER_R4 0x00000010 // 32/64-Bit Wide General-Purpose + // Timer 4 Software Reset +#define SYSCTL_SRWTIMER_R3 0x00000008 // 32/64-Bit Wide General-Purpose + // Timer 3 Software Reset +#define SYSCTL_SRWTIMER_R2 0x00000004 // 32/64-Bit Wide General-Purpose + // Timer 2 Software Reset +#define SYSCTL_SRWTIMER_R1 0x00000002 // 32/64-Bit Wide General-Purpose + // Timer 1 Software Reset +#define SYSCTL_SRWTIMER_R0 0x00000001 // 32/64-Bit Wide General-Purpose + // Timer 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCWD register. +// +//***************************************************************************** +#define SYSCTL_RCGCWD_R1 0x00000002 // Watchdog Timer 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCWD_R0 0x00000001 // Watchdog Timer 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer + // 5 Run Mode Clock Gating Control +#define SYSCTL_RCGCTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer + // 4 Run Mode Clock Gating Control +#define SYSCTL_RCGCTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer + // 3 Run Mode Clock Gating Control +#define SYSCTL_RCGCTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer + // 2 Run Mode Clock Gating Control +#define SYSCTL_RCGCTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer + // 1 Run Mode Clock Gating Control +#define SYSCTL_RCGCTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer + // 0 Run Mode Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCGPIO +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCGPIO_R5 0x00000020 // GPIO Port F Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R4 0x00000010 // GPIO Port E Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R3 0x00000008 // GPIO Port D Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R2 0x00000004 // GPIO Port C Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R1 0x00000002 // GPIO Port B Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R0 0x00000001 // GPIO Port A Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCDMA register. +// +//***************************************************************************** +#define SYSCTL_RCGCDMA_R0 0x00000001 // uDMA Module Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCHIB register. +// +//***************************************************************************** +#define SYSCTL_RCGCHIB_R0 0x00000001 // Hibernation Module Run Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCUART +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCUART_R7 0x00000080 // UART Module 7 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R6 0x00000040 // UART Module 6 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R5 0x00000020 // UART Module 5 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R4 0x00000010 // UART Module 4 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R3 0x00000008 // UART Module 3 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R2 0x00000004 // UART Module 2 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R1 0x00000002 // UART Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R0 0x00000001 // UART Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCSSI register. +// +//***************************************************************************** +#define SYSCTL_RCGCSSI_R3 0x00000008 // SSI Module 3 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCSSI_R2 0x00000004 // SSI Module 2 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCSSI_R1 0x00000002 // SSI Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCSSI_R0 0x00000001 // SSI Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCI2C register. +// +//***************************************************************************** +#define SYSCTL_RCGCI2C_R3 0x00000008 // I2C Module 3 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R2 0x00000004 // I2C Module 2 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R1 0x00000002 // I2C Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R0 0x00000001 // I2C Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCUSB register. +// +//***************************************************************************** +#define SYSCTL_RCGCUSB_R0 0x00000001 // USB Module Run Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCCAN register. +// +//***************************************************************************** +#define SYSCTL_RCGCCAN_R1 0x00000002 // CAN Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCCAN_R0 0x00000001 // CAN Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCADC register. +// +//***************************************************************************** +#define SYSCTL_RCGCADC_R1 0x00000002 // ADC Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCADC_R0 0x00000001 // ADC Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCACMP +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCACMP_R0 0x00000001 // Analog Comparator Module 0 Run + // Mode Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCPWM register. +// +//***************************************************************************** +#define SYSCTL_RCGCPWM_R1 0x00000002 // PWM Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCPWM_R0 0x00000001 // PWM Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCQEI register. +// +//***************************************************************************** +#define SYSCTL_RCGCQEI_R1 0x00000002 // QEI Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCQEI_R0 0x00000001 // QEI Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCEEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCEEPROM_R0 0x00000001 // EEPROM Module Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCWTIMER_R5 0x00000020 // 32/64-Bit Wide General-Purpose + // Timer 5 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCWTIMER_R4 0x00000010 // 32/64-Bit Wide General-Purpose + // Timer 4 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCWTIMER_R3 0x00000008 // 32/64-Bit Wide General-Purpose + // Timer 3 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCWTIMER_R2 0x00000004 // 32/64-Bit Wide General-Purpose + // Timer 2 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCWTIMER_R1 0x00000002 // 32/64-Bit Wide General-Purpose + // Timer 1 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCWTIMER_R0 0x00000001 // 32/64-Bit Wide General-Purpose + // Timer 0 Run Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCWD register. +// +//***************************************************************************** +#define SYSCTL_SCGCWD_S1 0x00000002 // Watchdog Timer 1 Sleep Mode + // Clock Gating Control +#define SYSCTL_SCGCWD_S0 0x00000001 // Watchdog Timer 0 Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCTIMER_S5 0x00000020 // 16/32-Bit General-Purpose Timer + // 5 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S4 0x00000010 // 16/32-Bit General-Purpose Timer + // 4 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S3 0x00000008 // 16/32-Bit General-Purpose Timer + // 3 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S2 0x00000004 // 16/32-Bit General-Purpose Timer + // 2 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S1 0x00000002 // 16/32-Bit General-Purpose Timer + // 1 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S0 0x00000001 // 16/32-Bit General-Purpose Timer + // 0 Sleep Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCGPIO +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCGPIO_S5 0x00000020 // GPIO Port F Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S4 0x00000010 // GPIO Port E Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S3 0x00000008 // GPIO Port D Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S2 0x00000004 // GPIO Port C Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S1 0x00000002 // GPIO Port B Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S0 0x00000001 // GPIO Port A Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCDMA register. +// +//***************************************************************************** +#define SYSCTL_SCGCDMA_S0 0x00000001 // uDMA Module Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCHIB register. +// +//***************************************************************************** +#define SYSCTL_SCGCHIB_S0 0x00000001 // Hibernation Module Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCUART +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCUART_S7 0x00000080 // UART Module 7 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S6 0x00000040 // UART Module 6 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S5 0x00000020 // UART Module 5 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S4 0x00000010 // UART Module 4 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S3 0x00000008 // UART Module 3 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S2 0x00000004 // UART Module 2 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S1 0x00000002 // UART Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S0 0x00000001 // UART Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCSSI register. +// +//***************************************************************************** +#define SYSCTL_SCGCSSI_S3 0x00000008 // SSI Module 3 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCSSI_S2 0x00000004 // SSI Module 2 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCSSI_S1 0x00000002 // SSI Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCSSI_S0 0x00000001 // SSI Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCI2C register. +// +//***************************************************************************** +#define SYSCTL_SCGCI2C_S3 0x00000008 // I2C Module 3 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S2 0x00000004 // I2C Module 2 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S1 0x00000002 // I2C Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S0 0x00000001 // I2C Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCUSB register. +// +//***************************************************************************** +#define SYSCTL_SCGCUSB_S0 0x00000001 // USB Module Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCCAN register. +// +//***************************************************************************** +#define SYSCTL_SCGCCAN_S1 0x00000002 // CAN Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCCAN_S0 0x00000001 // CAN Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCADC register. +// +//***************************************************************************** +#define SYSCTL_SCGCADC_S1 0x00000002 // ADC Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCADC_S0 0x00000001 // ADC Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCACMP +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCACMP_S0 0x00000001 // Analog Comparator Module 0 Sleep + // Mode Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCPWM register. +// +//***************************************************************************** +#define SYSCTL_SCGCPWM_S1 0x00000002 // PWM Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCPWM_S0 0x00000001 // PWM Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCQEI register. +// +//***************************************************************************** +#define SYSCTL_SCGCQEI_S1 0x00000002 // QEI Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCQEI_S0 0x00000001 // QEI Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCEEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCEEPROM_S0 0x00000001 // EEPROM Module Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCWTIMER_S5 0x00000020 // 32/64-Bit Wide General-Purpose + // Timer 5 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCWTIMER_S4 0x00000010 // 32/64-Bit Wide General-Purpose + // Timer 4 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCWTIMER_S3 0x00000008 // 32/64-Bit Wide General-Purpose + // Timer 3 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCWTIMER_S2 0x00000004 // 32/64-Bit Wide General-Purpose + // Timer 2 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCWTIMER_S1 0x00000002 // 32/64-Bit Wide General-Purpose + // Timer 1 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCWTIMER_S0 0x00000001 // 32/64-Bit Wide General-Purpose + // Timer 0 Sleep Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCWD register. +// +//***************************************************************************** +#define SYSCTL_DCGCWD_D1 0x00000002 // Watchdog Timer 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCWD_D0 0x00000001 // Watchdog Timer 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCTIMER_D5 0x00000020 // 16/32-Bit General-Purpose Timer + // 5 Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCTIMER_D4 0x00000010 // 16/32-Bit General-Purpose Timer + // 4 Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCTIMER_D3 0x00000008 // 16/32-Bit General-Purpose Timer + // 3 Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCTIMER_D2 0x00000004 // 16/32-Bit General-Purpose Timer + // 2 Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCTIMER_D1 0x00000002 // 16/32-Bit General-Purpose Timer + // 1 Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCTIMER_D0 0x00000001 // 16/32-Bit General-Purpose Timer + // 0 Deep-Sleep Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCGPIO +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCGPIO_D5 0x00000020 // GPIO Port F Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D4 0x00000010 // GPIO Port E Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D3 0x00000008 // GPIO Port D Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D2 0x00000004 // GPIO Port C Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D1 0x00000002 // GPIO Port B Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D0 0x00000001 // GPIO Port A Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCDMA register. +// +//***************************************************************************** +#define SYSCTL_DCGCDMA_D0 0x00000001 // uDMA Module Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCHIB register. +// +//***************************************************************************** +#define SYSCTL_DCGCHIB_D0 0x00000001 // Hibernation Module Deep-Sleep + // Mode Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCUART +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCUART_D7 0x00000080 // UART Module 7 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D6 0x00000040 // UART Module 6 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D5 0x00000020 // UART Module 5 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D4 0x00000010 // UART Module 4 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D3 0x00000008 // UART Module 3 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D2 0x00000004 // UART Module 2 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D1 0x00000002 // UART Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D0 0x00000001 // UART Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCSSI register. +// +//***************************************************************************** +#define SYSCTL_DCGCSSI_D3 0x00000008 // SSI Module 3 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCSSI_D2 0x00000004 // SSI Module 2 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCSSI_D1 0x00000002 // SSI Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCSSI_D0 0x00000001 // SSI Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCI2C register. +// +//***************************************************************************** +#define SYSCTL_DCGCI2C_D3 0x00000008 // I2C Module 3 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D2 0x00000004 // I2C Module 2 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D1 0x00000002 // I2C Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D0 0x00000001 // I2C Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCUSB register. +// +//***************************************************************************** +#define SYSCTL_DCGCUSB_D0 0x00000001 // USB Module Deep-Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCCAN register. +// +//***************************************************************************** +#define SYSCTL_DCGCCAN_D1 0x00000002 // CAN Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCCAN_D0 0x00000001 // CAN Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCADC register. +// +//***************************************************************************** +#define SYSCTL_DCGCADC_D1 0x00000002 // ADC Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCADC_D0 0x00000001 // ADC Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCACMP +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCACMP_D0 0x00000001 // Analog Comparator Module 0 + // Deep-Sleep Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCPWM register. +// +//***************************************************************************** +#define SYSCTL_DCGCPWM_D1 0x00000002 // PWM Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCPWM_D0 0x00000001 // PWM Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCQEI register. +// +//***************************************************************************** +#define SYSCTL_DCGCQEI_D1 0x00000002 // QEI Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCQEI_D0 0x00000001 // QEI Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCEEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCEEPROM_D0 0x00000001 // EEPROM Module Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCWTIMER_D5 0x00000020 // 32/64-Bit Wide General-Purpose + // Timer 5 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCWTIMER_D4 0x00000010 // 32/64-Bit Wide General-Purpose + // Timer 4 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCWTIMER_D3 0x00000008 // 32/64-Bit Wide General-Purpose + // Timer 3 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCWTIMER_D2 0x00000004 // 32/64-Bit Wide General-Purpose + // Timer 2 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCWTIMER_D1 0x00000002 // 32/64-Bit Wide General-Purpose + // Timer 1 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCWTIMER_D0 0x00000001 // 32/64-Bit Wide General-Purpose + // Timer 0 Deep-Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRWD register. +// +//***************************************************************************** +#define SYSCTL_PRWD_R1 0x00000002 // Watchdog Timer 1 Peripheral + // Ready +#define SYSCTL_PRWD_R0 0x00000001 // Watchdog Timer 0 Peripheral + // Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRTIMER register. +// +//***************************************************************************** +#define SYSCTL_PRTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer + // 5 Peripheral Ready +#define SYSCTL_PRTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer + // 4 Peripheral Ready +#define SYSCTL_PRTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer + // 3 Peripheral Ready +#define SYSCTL_PRTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer + // 2 Peripheral Ready +#define SYSCTL_PRTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer + // 1 Peripheral Ready +#define SYSCTL_PRTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer + // 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRGPIO register. +// +//***************************************************************************** +#define SYSCTL_PRGPIO_R5 0x00000020 // GPIO Port F Peripheral Ready +#define SYSCTL_PRGPIO_R4 0x00000010 // GPIO Port E Peripheral Ready +#define SYSCTL_PRGPIO_R3 0x00000008 // GPIO Port D Peripheral Ready +#define SYSCTL_PRGPIO_R2 0x00000004 // GPIO Port C Peripheral Ready +#define SYSCTL_PRGPIO_R1 0x00000002 // GPIO Port B Peripheral Ready +#define SYSCTL_PRGPIO_R0 0x00000001 // GPIO Port A Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRDMA register. +// +//***************************************************************************** +#define SYSCTL_PRDMA_R0 0x00000001 // uDMA Module Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRHIB register. +// +//***************************************************************************** +#define SYSCTL_PRHIB_R0 0x00000001 // Hibernation Module Peripheral + // Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRUART register. +// +//***************************************************************************** +#define SYSCTL_PRUART_R7 0x00000080 // UART Module 7 Peripheral Ready +#define SYSCTL_PRUART_R6 0x00000040 // UART Module 6 Peripheral Ready +#define SYSCTL_PRUART_R5 0x00000020 // UART Module 5 Peripheral Ready +#define SYSCTL_PRUART_R4 0x00000010 // UART Module 4 Peripheral Ready +#define SYSCTL_PRUART_R3 0x00000008 // UART Module 3 Peripheral Ready +#define SYSCTL_PRUART_R2 0x00000004 // UART Module 2 Peripheral Ready +#define SYSCTL_PRUART_R1 0x00000002 // UART Module 1 Peripheral Ready +#define SYSCTL_PRUART_R0 0x00000001 // UART Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRSSI register. +// +//***************************************************************************** +#define SYSCTL_PRSSI_R3 0x00000008 // SSI Module 3 Peripheral Ready +#define SYSCTL_PRSSI_R2 0x00000004 // SSI Module 2 Peripheral Ready +#define SYSCTL_PRSSI_R1 0x00000002 // SSI Module 1 Peripheral Ready +#define SYSCTL_PRSSI_R0 0x00000001 // SSI Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRI2C register. +// +//***************************************************************************** +#define SYSCTL_PRI2C_R3 0x00000008 // I2C Module 3 Peripheral Ready +#define SYSCTL_PRI2C_R2 0x00000004 // I2C Module 2 Peripheral Ready +#define SYSCTL_PRI2C_R1 0x00000002 // I2C Module 1 Peripheral Ready +#define SYSCTL_PRI2C_R0 0x00000001 // I2C Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRUSB register. +// +//***************************************************************************** +#define SYSCTL_PRUSB_R0 0x00000001 // USB Module Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRCAN register. +// +//***************************************************************************** +#define SYSCTL_PRCAN_R1 0x00000002 // CAN Module 1 Peripheral Ready +#define SYSCTL_PRCAN_R0 0x00000001 // CAN Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRADC register. +// +//***************************************************************************** +#define SYSCTL_PRADC_R1 0x00000002 // ADC Module 1 Peripheral Ready +#define SYSCTL_PRADC_R0 0x00000001 // ADC Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRACMP register. +// +//***************************************************************************** +#define SYSCTL_PRACMP_R0 0x00000001 // Analog Comparator Module 0 + // Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRPWM register. +// +//***************************************************************************** +#define SYSCTL_PRPWM_R1 0x00000002 // PWM Module 1 Peripheral Ready +#define SYSCTL_PRPWM_R0 0x00000001 // PWM Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRQEI register. +// +//***************************************************************************** +#define SYSCTL_PRQEI_R1 0x00000002 // QEI Module 1 Peripheral Ready +#define SYSCTL_PRQEI_R0 0x00000001 // QEI Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PREEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_PREEPROM_R0 0x00000001 // EEPROM Module Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_PRWTIMER_R5 0x00000020 // 32/64-Bit Wide General-Purpose + // Timer 5 Peripheral Ready +#define SYSCTL_PRWTIMER_R4 0x00000010 // 32/64-Bit Wide General-Purpose + // Timer 4 Peripheral Ready +#define SYSCTL_PRWTIMER_R3 0x00000008 // 32/64-Bit Wide General-Purpose + // Timer 3 Peripheral Ready +#define SYSCTL_PRWTIMER_R2 0x00000004 // 32/64-Bit Wide General-Purpose + // Timer 2 Peripheral Ready +#define SYSCTL_PRWTIMER_R1 0x00000002 // 32/64-Bit Wide General-Purpose + // Timer 1 Peripheral Ready +#define SYSCTL_PRWTIMER_R0 0x00000001 // 32/64-Bit Wide General-Purpose + // Timer 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_STAT register. +// +//***************************************************************************** +#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available uDMA Channels Minus 1 +#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine Status +#define UDMA_STAT_STATE_IDLE 0x00000000 // Idle +#define UDMA_STAT_STATE_RD_CTRL 0x00000010 // Reading channel controller data +#define UDMA_STAT_STATE_RD_SRCENDP \ + 0x00000020 // Reading source end pointer +#define UDMA_STAT_STATE_RD_DSTENDP \ + 0x00000030 // Reading destination end pointer +#define UDMA_STAT_STATE_RD_SRCDAT \ + 0x00000040 // Reading source data +#define UDMA_STAT_STATE_WR_DSTDAT \ + 0x00000050 // Writing destination data +#define UDMA_STAT_STATE_WAIT 0x00000060 // Waiting for uDMA request to + // clear +#define UDMA_STAT_STATE_WR_CTRL 0x00000070 // Writing channel controller data +#define UDMA_STAT_STATE_STALL 0x00000080 // Stalled +#define UDMA_STAT_STATE_DONE 0x00000090 // Done +#define UDMA_STAT_STATE_UNDEF 0x000000A0 // Undefined +#define UDMA_STAT_MASTEN 0x00000001 // Master Enable Status +#define UDMA_STAT_DMACHANS_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CFG register. +// +//***************************************************************************** +#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CTLBASE register. +// +//***************************************************************************** +#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address +#define UDMA_CTLBASE_ADDR_S 10 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ALTBASE register. +// +//***************************************************************************** +#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address + // Pointer +#define UDMA_ALTBASE_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_WAITSTAT register. +// +//***************************************************************************** +#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF // Channel [n] Wait Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_SWREQ register. +// +//***************************************************************************** +#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_USEBURSTSET +// register. +// +//***************************************************************************** +#define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF // Channel [n] Useburst Set + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_USEBURSTCLR +// register. +// +//***************************************************************************** +#define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF // Channel [n] Useburst Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_REQMASKSET +// register. +// +//***************************************************************************** +#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_REQMASKCLR +// register. +// +//***************************************************************************** +#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ENASET register. +// +//***************************************************************************** +#define UDMA_ENASET_SET_M 0xFFFFFFFF // Channel [n] Enable Set + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ENACLR register. +// +//***************************************************************************** +#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ALTSET register. +// +//***************************************************************************** +#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ALTCLR register. +// +//***************************************************************************** +#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_PRIOSET register. +// +//***************************************************************************** +#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_PRIOCLR register. +// +//***************************************************************************** +#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ERRCLR register. +// +//***************************************************************************** +#define UDMA_ERRCLR_ERRCLR 0x00000001 // uDMA Bus Error Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHASGN register. +// +//***************************************************************************** +#define UDMA_CHASGN_M 0xFFFFFFFF // Channel [n] Assignment Select +#define UDMA_CHASGN_PRIMARY 0x00000000 // Use the primary channel + // assignment +#define UDMA_CHASGN_SECONDARY 0x00000001 // Use the secondary channel + // assignment + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHIS register. +// +//***************************************************************************** +#define UDMA_CHIS_M 0xFFFFFFFF // Channel [n] Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHMAP0 register. +// +//***************************************************************************** +#define UDMA_CHMAP0_CH7SEL_M 0xF0000000 // uDMA Channel 7 Source Select +#define UDMA_CHMAP0_CH6SEL_M 0x0F000000 // uDMA Channel 6 Source Select +#define UDMA_CHMAP0_CH5SEL_M 0x00F00000 // uDMA Channel 5 Source Select +#define UDMA_CHMAP0_CH4SEL_M 0x000F0000 // uDMA Channel 4 Source Select +#define UDMA_CHMAP0_CH3SEL_M 0x0000F000 // uDMA Channel 3 Source Select +#define UDMA_CHMAP0_CH2SEL_M 0x00000F00 // uDMA Channel 2 Source Select +#define UDMA_CHMAP0_CH1SEL_M 0x000000F0 // uDMA Channel 1 Source Select +#define UDMA_CHMAP0_CH0SEL_M 0x0000000F // uDMA Channel 0 Source Select +#define UDMA_CHMAP0_CH7SEL_S 28 +#define UDMA_CHMAP0_CH6SEL_S 24 +#define UDMA_CHMAP0_CH5SEL_S 20 +#define UDMA_CHMAP0_CH4SEL_S 16 +#define UDMA_CHMAP0_CH3SEL_S 12 +#define UDMA_CHMAP0_CH2SEL_S 8 +#define UDMA_CHMAP0_CH1SEL_S 4 +#define UDMA_CHMAP0_CH0SEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHMAP1 register. +// +//***************************************************************************** +#define UDMA_CHMAP1_CH15SEL_M 0xF0000000 // uDMA Channel 15 Source Select +#define UDMA_CHMAP1_CH14SEL_M 0x0F000000 // uDMA Channel 14 Source Select +#define UDMA_CHMAP1_CH13SEL_M 0x00F00000 // uDMA Channel 13 Source Select +#define UDMA_CHMAP1_CH12SEL_M 0x000F0000 // uDMA Channel 12 Source Select +#define UDMA_CHMAP1_CH11SEL_M 0x0000F000 // uDMA Channel 11 Source Select +#define UDMA_CHMAP1_CH10SEL_M 0x00000F00 // uDMA Channel 10 Source Select +#define UDMA_CHMAP1_CH9SEL_M 0x000000F0 // uDMA Channel 9 Source Select +#define UDMA_CHMAP1_CH8SEL_M 0x0000000F // uDMA Channel 8 Source Select +#define UDMA_CHMAP1_CH15SEL_S 28 +#define UDMA_CHMAP1_CH14SEL_S 24 +#define UDMA_CHMAP1_CH13SEL_S 20 +#define UDMA_CHMAP1_CH12SEL_S 16 +#define UDMA_CHMAP1_CH11SEL_S 12 +#define UDMA_CHMAP1_CH10SEL_S 8 +#define UDMA_CHMAP1_CH9SEL_S 4 +#define UDMA_CHMAP1_CH8SEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHMAP2 register. +// +//***************************************************************************** +#define UDMA_CHMAP2_CH23SEL_M 0xF0000000 // uDMA Channel 23 Source Select +#define UDMA_CHMAP2_CH22SEL_M 0x0F000000 // uDMA Channel 22 Source Select +#define UDMA_CHMAP2_CH21SEL_M 0x00F00000 // uDMA Channel 21 Source Select +#define UDMA_CHMAP2_CH20SEL_M 0x000F0000 // uDMA Channel 20 Source Select +#define UDMA_CHMAP2_CH19SEL_M 0x0000F000 // uDMA Channel 19 Source Select +#define UDMA_CHMAP2_CH18SEL_M 0x00000F00 // uDMA Channel 18 Source Select +#define UDMA_CHMAP2_CH17SEL_M 0x000000F0 // uDMA Channel 17 Source Select +#define UDMA_CHMAP2_CH16SEL_M 0x0000000F // uDMA Channel 16 Source Select +#define UDMA_CHMAP2_CH23SEL_S 28 +#define UDMA_CHMAP2_CH22SEL_S 24 +#define UDMA_CHMAP2_CH21SEL_S 20 +#define UDMA_CHMAP2_CH20SEL_S 16 +#define UDMA_CHMAP2_CH19SEL_S 12 +#define UDMA_CHMAP2_CH18SEL_S 8 +#define UDMA_CHMAP2_CH17SEL_S 4 +#define UDMA_CHMAP2_CH16SEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHMAP3 register. +// +//***************************************************************************** +#define UDMA_CHMAP3_CH31SEL_M 0xF0000000 // uDMA Channel 31 Source Select +#define UDMA_CHMAP3_CH30SEL_M 0x0F000000 // uDMA Channel 30 Source Select +#define UDMA_CHMAP3_CH29SEL_M 0x00F00000 // uDMA Channel 29 Source Select +#define UDMA_CHMAP3_CH28SEL_M 0x000F0000 // uDMA Channel 28 Source Select +#define UDMA_CHMAP3_CH27SEL_M 0x0000F000 // uDMA Channel 27 Source Select +#define UDMA_CHMAP3_CH26SEL_M 0x00000F00 // uDMA Channel 26 Source Select +#define UDMA_CHMAP3_CH25SEL_M 0x000000F0 // uDMA Channel 25 Source Select +#define UDMA_CHMAP3_CH24SEL_M 0x0000000F // uDMA Channel 24 Source Select +#define UDMA_CHMAP3_CH31SEL_S 28 +#define UDMA_CHMAP3_CH30SEL_S 24 +#define UDMA_CHMAP3_CH29SEL_S 20 +#define UDMA_CHMAP3_CH28SEL_S 16 +#define UDMA_CHMAP3_CH27SEL_S 12 +#define UDMA_CHMAP3_CH26SEL_S 8 +#define UDMA_CHMAP3_CH25SEL_S 4 +#define UDMA_CHMAP3_CH24SEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_SRCENDP register. +// +//***************************************************************************** +#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer +#define UDMA_SRCENDP_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_DSTENDP register. +// +//***************************************************************************** +#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer +#define UDMA_DSTENDP_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CHCTL register. +// +//***************************************************************************** +#define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment +#define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte +#define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word +#define UDMA_CHCTL_DSTINC_32 0x80000000 // Word +#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment +#define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size +#define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte +#define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word +#define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word +#define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment +#define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte +#define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word +#define UDMA_CHCTL_SRCINC_32 0x08000000 // Word +#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment +#define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size +#define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte +#define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word +#define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word +#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size +#define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer +#define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers +#define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers +#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers +#define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers +#define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers +#define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers +#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers +#define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers +#define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers +#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers +#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1) +#define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst +#define UDMA_CHCTL_XFERMODE_M 0x00000007 // uDMA Transfer Mode +#define UDMA_CHCTL_XFERMODE_STOP \ + 0x00000000 // Stop +#define UDMA_CHCTL_XFERMODE_BASIC \ + 0x00000001 // Basic +#define UDMA_CHCTL_XFERMODE_AUTO \ + 0x00000002 // Auto-Request +#define UDMA_CHCTL_XFERMODE_PINGPONG \ + 0x00000003 // Ping-Pong +#define UDMA_CHCTL_XFERMODE_MEM_SG \ + 0x00000004 // Memory Scatter-Gather +#define UDMA_CHCTL_XFERMODE_MEM_SGA \ + 0x00000005 // Alternate Memory Scatter-Gather +#define UDMA_CHCTL_XFERMODE_PER_SG \ + 0x00000006 // Peripheral Scatter-Gather +#define UDMA_CHCTL_XFERMODE_PER_SGA \ + 0x00000007 // Alternate Peripheral + // Scatter-Gather +#define UDMA_CHCTL_XFERSIZE_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTLR register. +// +//***************************************************************************** +#define NVIC_ACTLR_DISOOFP 0x00000200 // Disable Out-Of-Order Floating + // Point +#define NVIC_ACTLR_DISFPCA 0x00000100 // Disable CONTROL +#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding +#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer +#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple + // Cycle Instructions + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CTRL register. +// +//***************************************************************************** +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag +#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_RELOAD register. +// +//***************************************************************************** +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value +#define NVIC_ST_RELOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CURRENT +// register. +// +//***************************************************************************** +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value +#define NVIC_ST_CURRENT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN0 register. +// +//***************************************************************************** +#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN1 register. +// +//***************************************************************************** +#define NVIC_EN1_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN2 register. +// +//***************************************************************************** +#define NVIC_EN2_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN3 register. +// +//***************************************************************************** +#define NVIC_EN3_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN4 register. +// +//***************************************************************************** +#define NVIC_EN4_INT_M 0x000007FF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS0 register. +// +//***************************************************************************** +#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS1 register. +// +//***************************************************************************** +#define NVIC_DIS1_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS2 register. +// +//***************************************************************************** +#define NVIC_DIS2_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS3 register. +// +//***************************************************************************** +#define NVIC_DIS3_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS4 register. +// +//***************************************************************************** +#define NVIC_DIS4_INT_M 0x000007FF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND0 register. +// +//***************************************************************************** +#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND1 register. +// +//***************************************************************************** +#define NVIC_PEND1_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND2 register. +// +//***************************************************************************** +#define NVIC_PEND2_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND3 register. +// +//***************************************************************************** +#define NVIC_PEND3_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND4 register. +// +//***************************************************************************** +#define NVIC_PEND4_INT_M 0x000007FF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND0 register. +// +//***************************************************************************** +#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND1 register. +// +//***************************************************************************** +#define NVIC_UNPEND1_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND2 register. +// +//***************************************************************************** +#define NVIC_UNPEND2_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND3 register. +// +//***************************************************************************** +#define NVIC_UNPEND3_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND4 register. +// +//***************************************************************************** +#define NVIC_UNPEND4_INT_M 0x000007FF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE0 register. +// +//***************************************************************************** +#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE1 register. +// +//***************************************************************************** +#define NVIC_ACTIVE1_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE2 register. +// +//***************************************************************************** +#define NVIC_ACTIVE2_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE3 register. +// +//***************************************************************************** +#define NVIC_ACTIVE3_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE4 register. +// +//***************************************************************************** +#define NVIC_ACTIVE4_INT_M 0x000007FF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI0 register. +// +//***************************************************************************** +#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask +#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask +#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask +#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask +#define NVIC_PRI0_INT3_S 29 +#define NVIC_PRI0_INT2_S 21 +#define NVIC_PRI0_INT1_S 13 +#define NVIC_PRI0_INT0_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI1 register. +// +//***************************************************************************** +#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask +#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask +#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask +#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask +#define NVIC_PRI1_INT7_S 29 +#define NVIC_PRI1_INT6_S 21 +#define NVIC_PRI1_INT5_S 13 +#define NVIC_PRI1_INT4_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI2 register. +// +//***************************************************************************** +#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask +#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask +#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask +#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask +#define NVIC_PRI2_INT11_S 29 +#define NVIC_PRI2_INT10_S 21 +#define NVIC_PRI2_INT9_S 13 +#define NVIC_PRI2_INT8_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI3 register. +// +//***************************************************************************** +#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask +#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask +#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask +#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask +#define NVIC_PRI3_INT15_S 29 +#define NVIC_PRI3_INT14_S 21 +#define NVIC_PRI3_INT13_S 13 +#define NVIC_PRI3_INT12_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI4 register. +// +//***************************************************************************** +#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask +#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask +#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask +#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask +#define NVIC_PRI4_INT19_S 29 +#define NVIC_PRI4_INT18_S 21 +#define NVIC_PRI4_INT17_S 13 +#define NVIC_PRI4_INT16_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI5 register. +// +//***************************************************************************** +#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask +#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask +#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask +#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask +#define NVIC_PRI5_INT23_S 29 +#define NVIC_PRI5_INT22_S 21 +#define NVIC_PRI5_INT21_S 13 +#define NVIC_PRI5_INT20_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI6 register. +// +//***************************************************************************** +#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask +#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask +#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask +#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask +#define NVIC_PRI6_INT27_S 29 +#define NVIC_PRI6_INT26_S 21 +#define NVIC_PRI6_INT25_S 13 +#define NVIC_PRI6_INT24_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI7 register. +// +//***************************************************************************** +#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask +#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask +#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask +#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask +#define NVIC_PRI7_INT31_S 29 +#define NVIC_PRI7_INT30_S 21 +#define NVIC_PRI7_INT29_S 13 +#define NVIC_PRI7_INT28_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI8 register. +// +//***************************************************************************** +#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask +#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask +#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask +#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask +#define NVIC_PRI8_INT35_S 29 +#define NVIC_PRI8_INT34_S 21 +#define NVIC_PRI8_INT33_S 13 +#define NVIC_PRI8_INT32_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI9 register. +// +//***************************************************************************** +#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask +#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask +#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask +#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask +#define NVIC_PRI9_INT39_S 29 +#define NVIC_PRI9_INT38_S 21 +#define NVIC_PRI9_INT37_S 13 +#define NVIC_PRI9_INT36_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI10 register. +// +//***************************************************************************** +#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask +#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask +#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask +#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask +#define NVIC_PRI10_INT43_S 29 +#define NVIC_PRI10_INT42_S 21 +#define NVIC_PRI10_INT41_S 13 +#define NVIC_PRI10_INT40_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI11 register. +// +//***************************************************************************** +#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask +#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask +#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask +#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask +#define NVIC_PRI11_INT47_S 29 +#define NVIC_PRI11_INT46_S 21 +#define NVIC_PRI11_INT45_S 13 +#define NVIC_PRI11_INT44_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI12 register. +// +//***************************************************************************** +#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask +#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask +#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask +#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask +#define NVIC_PRI12_INT51_S 29 +#define NVIC_PRI12_INT50_S 21 +#define NVIC_PRI12_INT49_S 13 +#define NVIC_PRI12_INT48_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI13 register. +// +//***************************************************************************** +#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask +#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask +#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask +#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask +#define NVIC_PRI13_INT55_S 29 +#define NVIC_PRI13_INT54_S 21 +#define NVIC_PRI13_INT53_S 13 +#define NVIC_PRI13_INT52_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI14 register. +// +//***************************************************************************** +#define NVIC_PRI14_INTD_M 0xE0000000 // Interrupt 59 Priority Mask +#define NVIC_PRI14_INTC_M 0x00E00000 // Interrupt 58 Priority Mask +#define NVIC_PRI14_INTB_M 0x0000E000 // Interrupt 57 Priority Mask +#define NVIC_PRI14_INTA_M 0x000000E0 // Interrupt 56 Priority Mask +#define NVIC_PRI14_INTD_S 29 +#define NVIC_PRI14_INTC_S 21 +#define NVIC_PRI14_INTB_S 13 +#define NVIC_PRI14_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI15 register. +// +//***************************************************************************** +#define NVIC_PRI15_INTD_M 0xE0000000 // Interrupt 63 Priority Mask +#define NVIC_PRI15_INTC_M 0x00E00000 // Interrupt 62 Priority Mask +#define NVIC_PRI15_INTB_M 0x0000E000 // Interrupt 61 Priority Mask +#define NVIC_PRI15_INTA_M 0x000000E0 // Interrupt 60 Priority Mask +#define NVIC_PRI15_INTD_S 29 +#define NVIC_PRI15_INTC_S 21 +#define NVIC_PRI15_INTB_S 13 +#define NVIC_PRI15_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI16 register. +// +//***************************************************************************** +#define NVIC_PRI16_INTD_M 0xE0000000 // Interrupt 67 Priority Mask +#define NVIC_PRI16_INTC_M 0x00E00000 // Interrupt 66 Priority Mask +#define NVIC_PRI16_INTB_M 0x0000E000 // Interrupt 65 Priority Mask +#define NVIC_PRI16_INTA_M 0x000000E0 // Interrupt 64 Priority Mask +#define NVIC_PRI16_INTD_S 29 +#define NVIC_PRI16_INTC_S 21 +#define NVIC_PRI16_INTB_S 13 +#define NVIC_PRI16_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI17 register. +// +//***************************************************************************** +#define NVIC_PRI17_INTD_M 0xE0000000 // Interrupt 71 Priority Mask +#define NVIC_PRI17_INTC_M 0x00E00000 // Interrupt 70 Priority Mask +#define NVIC_PRI17_INTB_M 0x0000E000 // Interrupt 69 Priority Mask +#define NVIC_PRI17_INTA_M 0x000000E0 // Interrupt 68 Priority Mask +#define NVIC_PRI17_INTD_S 29 +#define NVIC_PRI17_INTC_S 21 +#define NVIC_PRI17_INTB_S 13 +#define NVIC_PRI17_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI18 register. +// +//***************************************************************************** +#define NVIC_PRI18_INTD_M 0xE0000000 // Interrupt 75 Priority Mask +#define NVIC_PRI18_INTC_M 0x00E00000 // Interrupt 74 Priority Mask +#define NVIC_PRI18_INTB_M 0x0000E000 // Interrupt 73 Priority Mask +#define NVIC_PRI18_INTA_M 0x000000E0 // Interrupt 72 Priority Mask +#define NVIC_PRI18_INTD_S 29 +#define NVIC_PRI18_INTC_S 21 +#define NVIC_PRI18_INTB_S 13 +#define NVIC_PRI18_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI19 register. +// +//***************************************************************************** +#define NVIC_PRI19_INTD_M 0xE0000000 // Interrupt 79 Priority Mask +#define NVIC_PRI19_INTC_M 0x00E00000 // Interrupt 78 Priority Mask +#define NVIC_PRI19_INTB_M 0x0000E000 // Interrupt 77 Priority Mask +#define NVIC_PRI19_INTA_M 0x000000E0 // Interrupt 76 Priority Mask +#define NVIC_PRI19_INTD_S 29 +#define NVIC_PRI19_INTC_S 21 +#define NVIC_PRI19_INTB_S 13 +#define NVIC_PRI19_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI20 register. +// +//***************************************************************************** +#define NVIC_PRI20_INTD_M 0xE0000000 // Interrupt 83 Priority Mask +#define NVIC_PRI20_INTC_M 0x00E00000 // Interrupt 82 Priority Mask +#define NVIC_PRI20_INTB_M 0x0000E000 // Interrupt 81 Priority Mask +#define NVIC_PRI20_INTA_M 0x000000E0 // Interrupt 80 Priority Mask +#define NVIC_PRI20_INTD_S 29 +#define NVIC_PRI20_INTC_S 21 +#define NVIC_PRI20_INTB_S 13 +#define NVIC_PRI20_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI21 register. +// +//***************************************************************************** +#define NVIC_PRI21_INTD_M 0xE0000000 // Interrupt 87 Priority Mask +#define NVIC_PRI21_INTC_M 0x00E00000 // Interrupt 86 Priority Mask +#define NVIC_PRI21_INTB_M 0x0000E000 // Interrupt 85 Priority Mask +#define NVIC_PRI21_INTA_M 0x000000E0 // Interrupt 84 Priority Mask +#define NVIC_PRI21_INTD_S 29 +#define NVIC_PRI21_INTC_S 21 +#define NVIC_PRI21_INTB_S 13 +#define NVIC_PRI21_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI22 register. +// +//***************************************************************************** +#define NVIC_PRI22_INTD_M 0xE0000000 // Interrupt 91 Priority Mask +#define NVIC_PRI22_INTC_M 0x00E00000 // Interrupt 90 Priority Mask +#define NVIC_PRI22_INTB_M 0x0000E000 // Interrupt 89 Priority Mask +#define NVIC_PRI22_INTA_M 0x000000E0 // Interrupt 88 Priority Mask +#define NVIC_PRI22_INTD_S 29 +#define NVIC_PRI22_INTC_S 21 +#define NVIC_PRI22_INTB_S 13 +#define NVIC_PRI22_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI23 register. +// +//***************************************************************************** +#define NVIC_PRI23_INTD_M 0xE0000000 // Interrupt 95 Priority Mask +#define NVIC_PRI23_INTC_M 0x00E00000 // Interrupt 94 Priority Mask +#define NVIC_PRI23_INTB_M 0x0000E000 // Interrupt 93 Priority Mask +#define NVIC_PRI23_INTA_M 0x000000E0 // Interrupt 92 Priority Mask +#define NVIC_PRI23_INTD_S 29 +#define NVIC_PRI23_INTC_S 21 +#define NVIC_PRI23_INTB_S 13 +#define NVIC_PRI23_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI24 register. +// +//***************************************************************************** +#define NVIC_PRI24_INTD_M 0xE0000000 // Interrupt 99 Priority Mask +#define NVIC_PRI24_INTC_M 0x00E00000 // Interrupt 98 Priority Mask +#define NVIC_PRI24_INTB_M 0x0000E000 // Interrupt 97 Priority Mask +#define NVIC_PRI24_INTA_M 0x000000E0 // Interrupt 96 Priority Mask +#define NVIC_PRI24_INTD_S 29 +#define NVIC_PRI24_INTC_S 21 +#define NVIC_PRI24_INTB_S 13 +#define NVIC_PRI24_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI25 register. +// +//***************************************************************************** +#define NVIC_PRI25_INTD_M 0xE0000000 // Interrupt 103 Priority Mask +#define NVIC_PRI25_INTC_M 0x00E00000 // Interrupt 102 Priority Mask +#define NVIC_PRI25_INTB_M 0x0000E000 // Interrupt 101 Priority Mask +#define NVIC_PRI25_INTA_M 0x000000E0 // Interrupt 100 Priority Mask +#define NVIC_PRI25_INTD_S 29 +#define NVIC_PRI25_INTC_S 21 +#define NVIC_PRI25_INTB_S 13 +#define NVIC_PRI25_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI26 register. +// +//***************************************************************************** +#define NVIC_PRI26_INTD_M 0xE0000000 // Interrupt 107 Priority Mask +#define NVIC_PRI26_INTC_M 0x00E00000 // Interrupt 106 Priority Mask +#define NVIC_PRI26_INTB_M 0x0000E000 // Interrupt 105 Priority Mask +#define NVIC_PRI26_INTA_M 0x000000E0 // Interrupt 104 Priority Mask +#define NVIC_PRI26_INTD_S 29 +#define NVIC_PRI26_INTC_S 21 +#define NVIC_PRI26_INTB_S 13 +#define NVIC_PRI26_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI27 register. +// +//***************************************************************************** +#define NVIC_PRI27_INTD_M 0xE0000000 // Interrupt 111 Priority Mask +#define NVIC_PRI27_INTC_M 0x00E00000 // Interrupt 110 Priority Mask +#define NVIC_PRI27_INTB_M 0x0000E000 // Interrupt 109 Priority Mask +#define NVIC_PRI27_INTA_M 0x000000E0 // Interrupt 108 Priority Mask +#define NVIC_PRI27_INTD_S 29 +#define NVIC_PRI27_INTC_S 21 +#define NVIC_PRI27_INTB_S 13 +#define NVIC_PRI27_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI28 register. +// +//***************************************************************************** +#define NVIC_PRI28_INTD_M 0xE0000000 // Interrupt 115 Priority Mask +#define NVIC_PRI28_INTC_M 0x00E00000 // Interrupt 114 Priority Mask +#define NVIC_PRI28_INTB_M 0x0000E000 // Interrupt 113 Priority Mask +#define NVIC_PRI28_INTA_M 0x000000E0 // Interrupt 112 Priority Mask +#define NVIC_PRI28_INTD_S 29 +#define NVIC_PRI28_INTC_S 21 +#define NVIC_PRI28_INTB_S 13 +#define NVIC_PRI28_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI29 register. +// +//***************************************************************************** +#define NVIC_PRI29_INTD_M 0xE0000000 // Interrupt 119 Priority Mask +#define NVIC_PRI29_INTC_M 0x00E00000 // Interrupt 118 Priority Mask +#define NVIC_PRI29_INTB_M 0x0000E000 // Interrupt 117 Priority Mask +#define NVIC_PRI29_INTA_M 0x000000E0 // Interrupt 116 Priority Mask +#define NVIC_PRI29_INTD_S 29 +#define NVIC_PRI29_INTC_S 21 +#define NVIC_PRI29_INTB_S 13 +#define NVIC_PRI29_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI30 register. +// +//***************************************************************************** +#define NVIC_PRI30_INTD_M 0xE0000000 // Interrupt 123 Priority Mask +#define NVIC_PRI30_INTC_M 0x00E00000 // Interrupt 122 Priority Mask +#define NVIC_PRI30_INTB_M 0x0000E000 // Interrupt 121 Priority Mask +#define NVIC_PRI30_INTA_M 0x000000E0 // Interrupt 120 Priority Mask +#define NVIC_PRI30_INTD_S 29 +#define NVIC_PRI30_INTC_S 21 +#define NVIC_PRI30_INTB_S 13 +#define NVIC_PRI30_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI31 register. +// +//***************************************************************************** +#define NVIC_PRI31_INTD_M 0xE0000000 // Interrupt 127 Priority Mask +#define NVIC_PRI31_INTC_M 0x00E00000 // Interrupt 126 Priority Mask +#define NVIC_PRI31_INTB_M 0x0000E000 // Interrupt 125 Priority Mask +#define NVIC_PRI31_INTA_M 0x000000E0 // Interrupt 124 Priority Mask +#define NVIC_PRI31_INTD_S 29 +#define NVIC_PRI31_INTC_S 21 +#define NVIC_PRI31_INTB_S 13 +#define NVIC_PRI31_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI32 register. +// +//***************************************************************************** +#define NVIC_PRI32_INTD_M 0xE0000000 // Interrupt 131 Priority Mask +#define NVIC_PRI32_INTC_M 0x00E00000 // Interrupt 130 Priority Mask +#define NVIC_PRI32_INTB_M 0x0000E000 // Interrupt 129 Priority Mask +#define NVIC_PRI32_INTA_M 0x000000E0 // Interrupt 128 Priority Mask +#define NVIC_PRI32_INTD_S 29 +#define NVIC_PRI32_INTC_S 21 +#define NVIC_PRI32_INTB_S 13 +#define NVIC_PRI32_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI33 register. +// +//***************************************************************************** +#define NVIC_PRI33_INTD_M 0xE0000000 // Interrupt Priority for Interrupt + // [4n+3] +#define NVIC_PRI33_INTC_M 0x00E00000 // Interrupt Priority for Interrupt + // [4n+2] +#define NVIC_PRI33_INTB_M 0x0000E000 // Interrupt Priority for Interrupt + // [4n+1] +#define NVIC_PRI33_INTA_M 0x000000E0 // Interrupt Priority for Interrupt + // [4n] +#define NVIC_PRI33_INTD_S 29 +#define NVIC_PRI33_INTC_S 21 +#define NVIC_PRI33_INTB_S 13 +#define NVIC_PRI33_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI34 register. +// +//***************************************************************************** +#define NVIC_PRI34_INTD_M 0xE0000000 // Interrupt Priority for Interrupt + // [4n+3] +#define NVIC_PRI34_INTC_M 0x00E00000 // Interrupt Priority for Interrupt + // [4n+2] +#define NVIC_PRI34_INTB_M 0x0000E000 // Interrupt Priority for Interrupt + // [4n+1] +#define NVIC_PRI34_INTA_M 0x000000E0 // Interrupt Priority for Interrupt + // [4n] +#define NVIC_PRI34_INTD_S 29 +#define NVIC_PRI34_INTC_S 21 +#define NVIC_PRI34_INTB_S 13 +#define NVIC_PRI34_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CPUID register. +// +//***************************************************************************** +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code +#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number +#define NVIC_CPUID_CON_M 0x000F0000 // Constant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number +#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor +#define NVIC_CPUID_REV_M 0x0000000F // Revision Number + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_INT_CTRL register. +// +//***************************************************************************** +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending +#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending +#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number +#define NVIC_INT_CTRL_VEC_PEN_NMI \ + 0x00002000 // NMI +#define NVIC_INT_CTRL_VEC_PEN_HARD \ + 0x00003000 // Hard fault +#define NVIC_INT_CTRL_VEC_PEN_MEM \ + 0x00004000 // Memory management fault +#define NVIC_INT_CTRL_VEC_PEN_BUS \ + 0x00005000 // Bus fault +#define NVIC_INT_CTRL_VEC_PEN_USG \ + 0x00006000 // Usage fault +#define NVIC_INT_CTRL_VEC_PEN_SVC \ + 0x0000B000 // SVCall +#define NVIC_INT_CTRL_VEC_PEN_PNDSV \ + 0x0000E000 // PendSV +#define NVIC_INT_CTRL_VEC_PEN_TICK \ + 0x0000F000 // SysTick +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base +#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number +#define NVIC_INT_CTRL_VEC_ACT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_VTABLE register. +// +//***************************************************************************** +#define NVIC_VTABLE_OFFSET_M 0xFFFFFC00 // Vector Table Offset +#define NVIC_VTABLE_OFFSET_S 10 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_APINT register. +// +//***************************************************************************** +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key +#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key +#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping +#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split +#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split +#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split +#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split +#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split +#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split +#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split +#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault +#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CFG_CTRL register. +// +//***************************************************************************** +#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception + // Entry +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and + // Fault +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI1 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority +#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority +#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority +#define NVIC_SYS_PRI1_USAGE_S 21 +#define NVIC_SYS_PRI1_BUS_S 13 +#define NVIC_SYS_PRI1_MEM_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI2 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority +#define NVIC_SYS_PRI2_SVC_S 29 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI3 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority +#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority +#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority +#define NVIC_SYS_PRI3_TICK_S 29 +#define NVIC_SYS_PRI3_PENDSV_S 21 +#define NVIC_SYS_PRI3_DEBUG_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL +// register. +// +//***************************************************************************** +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending +#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending +#define NVIC_SYS_HND_CTRL_USAGEP \ + 0x00001000 // Usage Fault Pending +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage + // Fault +#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid +#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy + // State Preservation +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error +#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address + // Register Valid +#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on + // Floating-Point Lazy State + // Preservation +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_HFAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DEBUG_STAT +// register. +// +//***************************************************************************** +#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted +#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch +#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match +#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction +#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MM_ADDR register. +// +//***************************************************************************** +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_MM_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_ADDR +// register. +// +//***************************************************************************** +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_FAULT_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CPAC register. +// +//***************************************************************************** +#define NVIC_CPAC_CP11_M 0x00C00000 // CP11 Coprocessor Access + // Privilege +#define NVIC_CPAC_CP11_DIS 0x00000000 // Access Denied +#define NVIC_CPAC_CP11_PRIV 0x00400000 // Privileged Access Only +#define NVIC_CPAC_CP11_FULL 0x00C00000 // Full Access +#define NVIC_CPAC_CP10_M 0x00300000 // CP10 Coprocessor Access + // Privilege +#define NVIC_CPAC_CP10_DIS 0x00000000 // Access Denied +#define NVIC_CPAC_CP10_PRIV 0x00100000 // Privileged Access Only +#define NVIC_CPAC_CP10_FULL 0x00300000 // Full Access + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_TYPE register. +// +//***************************************************************************** +#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I Regions +#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D Regions +#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or Unified MPU +#define NVIC_MPU_TYPE_IREGION_S 16 +#define NVIC_MPU_TYPE_DREGION_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_CTRL register. +// +//***************************************************************************** +#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU Default Region +#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU Enabled During Faults +#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_NUMBER +// register. +// +//***************************************************************************** +#define NVIC_MPU_NUMBER_M 0x00000007 // MPU Region to Access +#define NVIC_MPU_NUMBER_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE register. +// +//***************************************************************************** +#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE_ADDR_S 5 +#define NVIC_MPU_BASE_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable +#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable +#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable +#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE1 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE1_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE1_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE1_ADDR_S 5 +#define NVIC_MPU_BASE1_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR1_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR1_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR1_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR1_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR1_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR1_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR1_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR1_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR1_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE2 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE2_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE2_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE2_ADDR_S 5 +#define NVIC_MPU_BASE2_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR2_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR2_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR2_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR2_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR2_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR2_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR2_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR2_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR2_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE3 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE3_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE3_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE3_ADDR_S 5 +#define NVIC_MPU_BASE3_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR3_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR3_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR3_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR3_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR3_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR3_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR3_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR3_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR3_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_CTRL register. +// +//***************************************************************************** +#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask +#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key +#define NVIC_DBG_CTRL_S_RESET_ST \ + 0x02000000 // Core has reset since last read +#define NVIC_DBG_CTRL_S_RETIRE_ST \ + 0x01000000 // Core has executed insruction + // since last read +#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up +#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping +#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt +#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available +#define NVIC_DBG_CTRL_C_SNAPSTALL \ + 0x00000020 // Breaks a stalled load/store +#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping +#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core +#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core +#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_XFER register. +// +//***************************************************************************** +#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read +#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register +#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 +#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 +#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 +#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 +#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 +#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 +#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 +#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 +#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 +#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 +#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 +#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 +#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 +#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 +#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 +#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 +#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register +#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP +#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP +#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP +#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_DATA register. +// +//***************************************************************************** +#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache +#define NVIC_DBG_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_INT register. +// +//***************************************************************************** +#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault +#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors +#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error +#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state +#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check +#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error +#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault +#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status +#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset +#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending +#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SW_TRIG register. +// +//***************************************************************************** +#define NVIC_SW_TRIG_INTID_M 0x000000FF // Interrupt ID +#define NVIC_SW_TRIG_INTID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FPCC register. +// +//***************************************************************************** +#define NVIC_FPCC_ASPEN 0x80000000 // Automatic State Preservation + // Enable +#define NVIC_FPCC_LSPEN 0x40000000 // Lazy State Preservation Enable +#define NVIC_FPCC_MONRDY 0x00000100 // Monitor Ready +#define NVIC_FPCC_BFRDY 0x00000040 // Bus Fault Ready +#define NVIC_FPCC_MMRDY 0x00000020 // Memory Management Fault Ready +#define NVIC_FPCC_HFRDY 0x00000010 // Hard Fault Ready +#define NVIC_FPCC_THREAD 0x00000008 // Thread Mode +#define NVIC_FPCC_USER 0x00000002 // User Privilege Level +#define NVIC_FPCC_LSPACT 0x00000001 // Lazy State Preservation Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FPCA register. +// +//***************************************************************************** +#define NVIC_FPCA_ADDRESS_M 0xFFFFFFF8 // Address +#define NVIC_FPCA_ADDRESS_S 3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FPDSC register. +// +//***************************************************************************** +#define NVIC_FPDSC_AHP 0x04000000 // AHP Bit Default +#define NVIC_FPDSC_DN 0x02000000 // DN Bit Default +#define NVIC_FPDSC_FZ 0x01000000 // FZ Bit Default +#define NVIC_FPDSC_RMODE_M 0x00C00000 // RMODE Bit Default +#define NVIC_FPDSC_RMODE_RN 0x00000000 // Round to Nearest (RN) mode +#define NVIC_FPDSC_RMODE_RP 0x00400000 // Round towards Plus Infinity (RP) + // mode +#define NVIC_FPDSC_RMODE_RM 0x00800000 // Round towards Minus Infinity + // (RM) mode +#define NVIC_FPDSC_RMODE_RZ 0x00C00000 // Round towards Zero (RZ) mode + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED +#define SYSCTL_DID0_CLASS_BLIZZARD \ + 0x00050000 // Tiva(TM) C Series TM4C123-class + // microcontrollers + +#endif + +#endif // __TM4C123GH6PM_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/tm4c123gh6pz.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/tm4c123gh6pz.h new file mode 100644 index 0000000000000000000000000000000000000000..b51f715956263f023ebd8c87008371ab318a1c27 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/tm4c123gh6pz.h @@ -0,0 +1,13577 @@ +//***************************************************************************** +// +// tm4c123gh6pz.h - TM4C123GH6PZ Register Definitions +// +// Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __TM4C123GH6PZ_H__ +#define __TM4C123GH6PZ_H__ + +//***************************************************************************** +// +// Interrupt assignments +// +//***************************************************************************** +#define INT_GPIOA 16 // GPIO Port A +#define INT_GPIOB 17 // GPIO Port B +#define INT_GPIOC 18 // GPIO Port C +#define INT_GPIOD 19 // GPIO Port D +#define INT_GPIOE 20 // GPIO Port E +#define INT_UART0 21 // UART0 +#define INT_UART1 22 // UART1 +#define INT_SSI0 23 // SSI0 +#define INT_I2C0 24 // I2C0 +#define INT_PWM0_FAULT 25 // PWM0 Fault +#define INT_PWM0_0 26 // PWM0 Generator 0 +#define INT_PWM0_1 27 // PWM0 Generator 1 +#define INT_PWM0_2 28 // PWM0 Generator 2 +#define INT_QEI0 29 // QEI0 +#define INT_ADC0SS0 30 // ADC0 Sequence 0 +#define INT_ADC0SS1 31 // ADC0 Sequence 1 +#define INT_ADC0SS2 32 // ADC0 Sequence 2 +#define INT_ADC0SS3 33 // ADC0 Sequence 3 +#define INT_WATCHDOG 34 // Watchdog Timers 0 and 1 +#define INT_TIMER0A 35 // 16/32-Bit Timer 0A +#define INT_TIMER0B 36 // 16/32-Bit Timer 0B +#define INT_TIMER1A 37 // 16/32-Bit Timer 1A +#define INT_TIMER1B 38 // 16/32-Bit Timer 1B +#define INT_TIMER2A 39 // 16/32-Bit Timer 2A +#define INT_TIMER2B 40 // 16/32-Bit Timer 2B +#define INT_COMP0 41 // Analog Comparator 0 +#define INT_COMP1 42 // Analog Comparator 1 +#define INT_COMP2 43 // Analog Comparator 2 +#define INT_SYSCTL 44 // System Control +#define INT_FLASH 45 // Flash Memory Control and EEPROM + // Control +#define INT_GPIOF 46 // GPIO Port F +#define INT_GPIOG 47 // GPIO Port G +#define INT_GPIOH 48 // GPIO Port H +#define INT_UART2 49 // UART2 +#define INT_SSI1 50 // SSI1 +#define INT_TIMER3A 51 // 16/32-Bit Timer 3A +#define INT_TIMER3B 52 // Timer 3B +#define INT_I2C1 53 // I2C1 +#define INT_QEI1 54 // QEI1 +#define INT_CAN0 55 // CAN0 +#define INT_CAN1 56 // CAN1 +#define INT_HIBERNATE 59 // Hibernation Module +#define INT_USB0 60 // USB +#define INT_PWM0_3 61 // PWM Generator 3 +#define INT_UDMA 62 // uDMA Software +#define INT_UDMAERR 63 // uDMA Error +#define INT_ADC1SS0 64 // ADC1 Sequence 0 +#define INT_ADC1SS1 65 // ADC1 Sequence 1 +#define INT_ADC1SS2 66 // ADC1 Sequence 2 +#define INT_ADC1SS3 67 // ADC1 Sequence 3 +#define INT_GPIOJ 70 // GPIO Port J +#define INT_GPIOK 71 // GPIO Port K +#define INT_SSI2 73 // SSI2 +#define INT_SSI3 74 // SSI3 +#define INT_UART3 75 // UART3 +#define INT_UART4 76 // UART4 +#define INT_UART5 77 // UART5 +#define INT_UART6 78 // UART6 +#define INT_UART7 79 // UART7 +#define INT_I2C2 84 // I2C2 +#define INT_I2C3 85 // I2C3 +#define INT_TIMER4A 86 // 16/32-Bit Timer 4A +#define INT_TIMER4B 87 // 16/32-Bit Timer 4B +#define INT_TIMER5A 108 // 16/32-Bit Timer 5A +#define INT_TIMER5B 109 // 16/32-Bit Timer 5B +#define INT_WTIMER0A 110 // 32/64-Bit Timer 0A +#define INT_WTIMER0B 111 // 32/64-Bit Timer 0B +#define INT_WTIMER1A 112 // 32/64-Bit Timer 1A +#define INT_WTIMER1B 113 // 32/64-Bit Timer 1B +#define INT_WTIMER2A 114 // 32/64-Bit Timer 2A +#define INT_WTIMER2B 115 // 32/64-Bit Timer 2B +#define INT_WTIMER3A 116 // 32/64-Bit Timer 3A +#define INT_WTIMER3B 117 // 32/64-Bit Timer 3B +#define INT_WTIMER4A 118 // 32/64-Bit Timer 4A +#define INT_WTIMER4B 119 // 32/64-Bit Timer 4B +#define INT_WTIMER5A 120 // 32/64-Bit Timer 5A +#define INT_WTIMER5B 121 // 32/64-Bit Timer 5B +#define INT_SYSEXC 122 // System Exception (imprecise) +#define INT_I2C4 125 // I2C4 +#define INT_I2C5 126 // I2C5 +#define INT_PWM1_0 150 // PWM1 Generator 0 +#define INT_PWM1_1 151 // PWM1 Generator 1 +#define INT_PWM1_2 152 // PWM1 Generator 2 +#define INT_PWM1_3 153 // PWM1 Generator 3 +#define INT_PWM1_FAULT 154 // PWM1 Fault + +//***************************************************************************** +// +// Watchdog Timer registers (WATCHDOG0) +// +//***************************************************************************** +#define WATCHDOG0_LOAD_R (*((volatile uint32_t *)0x40000000)) +#define WATCHDOG0_VALUE_R (*((volatile uint32_t *)0x40000004)) +#define WATCHDOG0_CTL_R (*((volatile uint32_t *)0x40000008)) +#define WATCHDOG0_ICR_R (*((volatile uint32_t *)0x4000000C)) +#define WATCHDOG0_RIS_R (*((volatile uint32_t *)0x40000010)) +#define WATCHDOG0_MIS_R (*((volatile uint32_t *)0x40000014)) +#define WATCHDOG0_TEST_R (*((volatile uint32_t *)0x40000418)) +#define WATCHDOG0_LOCK_R (*((volatile uint32_t *)0x40000C00)) + +//***************************************************************************** +// +// Watchdog Timer registers (WATCHDOG1) +// +//***************************************************************************** +#define WATCHDOG1_LOAD_R (*((volatile uint32_t *)0x40001000)) +#define WATCHDOG1_VALUE_R (*((volatile uint32_t *)0x40001004)) +#define WATCHDOG1_CTL_R (*((volatile uint32_t *)0x40001008)) +#define WATCHDOG1_ICR_R (*((volatile uint32_t *)0x4000100C)) +#define WATCHDOG1_RIS_R (*((volatile uint32_t *)0x40001010)) +#define WATCHDOG1_MIS_R (*((volatile uint32_t *)0x40001014)) +#define WATCHDOG1_TEST_R (*((volatile uint32_t *)0x40001418)) +#define WATCHDOG1_LOCK_R (*((volatile uint32_t *)0x40001C00)) + +//***************************************************************************** +// +// GPIO registers (PORTA) +// +//***************************************************************************** +#define GPIO_PORTA_DATA_BITS_R ((volatile uint32_t *)0x40004000) +#define GPIO_PORTA_DATA_R (*((volatile uint32_t *)0x400043FC)) +#define GPIO_PORTA_DIR_R (*((volatile uint32_t *)0x40004400)) +#define GPIO_PORTA_IS_R (*((volatile uint32_t *)0x40004404)) +#define GPIO_PORTA_IBE_R (*((volatile uint32_t *)0x40004408)) +#define GPIO_PORTA_IEV_R (*((volatile uint32_t *)0x4000440C)) +#define GPIO_PORTA_IM_R (*((volatile uint32_t *)0x40004410)) +#define GPIO_PORTA_RIS_R (*((volatile uint32_t *)0x40004414)) +#define GPIO_PORTA_MIS_R (*((volatile uint32_t *)0x40004418)) +#define GPIO_PORTA_ICR_R (*((volatile uint32_t *)0x4000441C)) +#define GPIO_PORTA_AFSEL_R (*((volatile uint32_t *)0x40004420)) +#define GPIO_PORTA_DR2R_R (*((volatile uint32_t *)0x40004500)) +#define GPIO_PORTA_DR4R_R (*((volatile uint32_t *)0x40004504)) +#define GPIO_PORTA_DR8R_R (*((volatile uint32_t *)0x40004508)) +#define GPIO_PORTA_ODR_R (*((volatile uint32_t *)0x4000450C)) +#define GPIO_PORTA_PUR_R (*((volatile uint32_t *)0x40004510)) +#define GPIO_PORTA_PDR_R (*((volatile uint32_t *)0x40004514)) +#define GPIO_PORTA_SLR_R (*((volatile uint32_t *)0x40004518)) +#define GPIO_PORTA_DEN_R (*((volatile uint32_t *)0x4000451C)) +#define GPIO_PORTA_LOCK_R (*((volatile uint32_t *)0x40004520)) +#define GPIO_PORTA_CR_R (*((volatile uint32_t *)0x40004524)) +#define GPIO_PORTA_AMSEL_R (*((volatile uint32_t *)0x40004528)) +#define GPIO_PORTA_PCTL_R (*((volatile uint32_t *)0x4000452C)) +#define GPIO_PORTA_ADCCTL_R (*((volatile uint32_t *)0x40004530)) +#define GPIO_PORTA_DMACTL_R (*((volatile uint32_t *)0x40004534)) + +//***************************************************************************** +// +// GPIO registers (PORTB) +// +//***************************************************************************** +#define GPIO_PORTB_DATA_BITS_R ((volatile uint32_t *)0x40005000) +#define GPIO_PORTB_DATA_R (*((volatile uint32_t *)0x400053FC)) +#define GPIO_PORTB_DIR_R (*((volatile uint32_t *)0x40005400)) +#define GPIO_PORTB_IS_R (*((volatile uint32_t *)0x40005404)) +#define GPIO_PORTB_IBE_R (*((volatile uint32_t *)0x40005408)) +#define GPIO_PORTB_IEV_R (*((volatile uint32_t *)0x4000540C)) +#define GPIO_PORTB_IM_R (*((volatile uint32_t *)0x40005410)) +#define GPIO_PORTB_RIS_R (*((volatile uint32_t *)0x40005414)) +#define GPIO_PORTB_MIS_R (*((volatile uint32_t *)0x40005418)) +#define GPIO_PORTB_ICR_R (*((volatile uint32_t *)0x4000541C)) +#define GPIO_PORTB_AFSEL_R (*((volatile uint32_t *)0x40005420)) +#define GPIO_PORTB_DR2R_R (*((volatile uint32_t *)0x40005500)) +#define GPIO_PORTB_DR4R_R (*((volatile uint32_t *)0x40005504)) +#define GPIO_PORTB_DR8R_R (*((volatile uint32_t *)0x40005508)) +#define GPIO_PORTB_ODR_R (*((volatile uint32_t *)0x4000550C)) +#define GPIO_PORTB_PUR_R (*((volatile uint32_t *)0x40005510)) +#define GPIO_PORTB_PDR_R (*((volatile uint32_t *)0x40005514)) +#define GPIO_PORTB_SLR_R (*((volatile uint32_t *)0x40005518)) +#define GPIO_PORTB_DEN_R (*((volatile uint32_t *)0x4000551C)) +#define GPIO_PORTB_LOCK_R (*((volatile uint32_t *)0x40005520)) +#define GPIO_PORTB_CR_R (*((volatile uint32_t *)0x40005524)) +#define GPIO_PORTB_AMSEL_R (*((volatile uint32_t *)0x40005528)) +#define GPIO_PORTB_PCTL_R (*((volatile uint32_t *)0x4000552C)) +#define GPIO_PORTB_ADCCTL_R (*((volatile uint32_t *)0x40005530)) +#define GPIO_PORTB_DMACTL_R (*((volatile uint32_t *)0x40005534)) + +//***************************************************************************** +// +// GPIO registers (PORTC) +// +//***************************************************************************** +#define GPIO_PORTC_DATA_BITS_R ((volatile uint32_t *)0x40006000) +#define GPIO_PORTC_DATA_R (*((volatile uint32_t *)0x400063FC)) +#define GPIO_PORTC_DIR_R (*((volatile uint32_t *)0x40006400)) +#define GPIO_PORTC_IS_R (*((volatile uint32_t *)0x40006404)) +#define GPIO_PORTC_IBE_R (*((volatile uint32_t *)0x40006408)) +#define GPIO_PORTC_IEV_R (*((volatile uint32_t *)0x4000640C)) +#define GPIO_PORTC_IM_R (*((volatile uint32_t *)0x40006410)) +#define GPIO_PORTC_RIS_R (*((volatile uint32_t *)0x40006414)) +#define GPIO_PORTC_MIS_R (*((volatile uint32_t *)0x40006418)) +#define GPIO_PORTC_ICR_R (*((volatile uint32_t *)0x4000641C)) +#define GPIO_PORTC_AFSEL_R (*((volatile uint32_t *)0x40006420)) +#define GPIO_PORTC_DR2R_R (*((volatile uint32_t *)0x40006500)) +#define GPIO_PORTC_DR4R_R (*((volatile uint32_t *)0x40006504)) +#define GPIO_PORTC_DR8R_R (*((volatile uint32_t *)0x40006508)) +#define GPIO_PORTC_ODR_R (*((volatile uint32_t *)0x4000650C)) +#define GPIO_PORTC_PUR_R (*((volatile uint32_t *)0x40006510)) +#define GPIO_PORTC_PDR_R (*((volatile uint32_t *)0x40006514)) +#define GPIO_PORTC_SLR_R (*((volatile uint32_t *)0x40006518)) +#define GPIO_PORTC_DEN_R (*((volatile uint32_t *)0x4000651C)) +#define GPIO_PORTC_LOCK_R (*((volatile uint32_t *)0x40006520)) +#define GPIO_PORTC_CR_R (*((volatile uint32_t *)0x40006524)) +#define GPIO_PORTC_AMSEL_R (*((volatile uint32_t *)0x40006528)) +#define GPIO_PORTC_PCTL_R (*((volatile uint32_t *)0x4000652C)) +#define GPIO_PORTC_ADCCTL_R (*((volatile uint32_t *)0x40006530)) +#define GPIO_PORTC_DMACTL_R (*((volatile uint32_t *)0x40006534)) + +//***************************************************************************** +// +// GPIO registers (PORTD) +// +//***************************************************************************** +#define GPIO_PORTD_DATA_BITS_R ((volatile uint32_t *)0x40007000) +#define GPIO_PORTD_DATA_R (*((volatile uint32_t *)0x400073FC)) +#define GPIO_PORTD_DIR_R (*((volatile uint32_t *)0x40007400)) +#define GPIO_PORTD_IS_R (*((volatile uint32_t *)0x40007404)) +#define GPIO_PORTD_IBE_R (*((volatile uint32_t *)0x40007408)) +#define GPIO_PORTD_IEV_R (*((volatile uint32_t *)0x4000740C)) +#define GPIO_PORTD_IM_R (*((volatile uint32_t *)0x40007410)) +#define GPIO_PORTD_RIS_R (*((volatile uint32_t *)0x40007414)) +#define GPIO_PORTD_MIS_R (*((volatile uint32_t *)0x40007418)) +#define GPIO_PORTD_ICR_R (*((volatile uint32_t *)0x4000741C)) +#define GPIO_PORTD_AFSEL_R (*((volatile uint32_t *)0x40007420)) +#define GPIO_PORTD_DR2R_R (*((volatile uint32_t *)0x40007500)) +#define GPIO_PORTD_DR4R_R (*((volatile uint32_t *)0x40007504)) +#define GPIO_PORTD_DR8R_R (*((volatile uint32_t *)0x40007508)) +#define GPIO_PORTD_ODR_R (*((volatile uint32_t *)0x4000750C)) +#define GPIO_PORTD_PUR_R (*((volatile uint32_t *)0x40007510)) +#define GPIO_PORTD_PDR_R (*((volatile uint32_t *)0x40007514)) +#define GPIO_PORTD_SLR_R (*((volatile uint32_t *)0x40007518)) +#define GPIO_PORTD_DEN_R (*((volatile uint32_t *)0x4000751C)) +#define GPIO_PORTD_LOCK_R (*((volatile uint32_t *)0x40007520)) +#define GPIO_PORTD_CR_R (*((volatile uint32_t *)0x40007524)) +#define GPIO_PORTD_AMSEL_R (*((volatile uint32_t *)0x40007528)) +#define GPIO_PORTD_PCTL_R (*((volatile uint32_t *)0x4000752C)) +#define GPIO_PORTD_ADCCTL_R (*((volatile uint32_t *)0x40007530)) +#define GPIO_PORTD_DMACTL_R (*((volatile uint32_t *)0x40007534)) + +//***************************************************************************** +// +// SSI registers (SSI0) +// +//***************************************************************************** +#define SSI0_CR0_R (*((volatile uint32_t *)0x40008000)) +#define SSI0_CR1_R (*((volatile uint32_t *)0x40008004)) +#define SSI0_DR_R (*((volatile uint32_t *)0x40008008)) +#define SSI0_SR_R (*((volatile uint32_t *)0x4000800C)) +#define SSI0_CPSR_R (*((volatile uint32_t *)0x40008010)) +#define SSI0_IM_R (*((volatile uint32_t *)0x40008014)) +#define SSI0_RIS_R (*((volatile uint32_t *)0x40008018)) +#define SSI0_MIS_R (*((volatile uint32_t *)0x4000801C)) +#define SSI0_ICR_R (*((volatile uint32_t *)0x40008020)) +#define SSI0_DMACTL_R (*((volatile uint32_t *)0x40008024)) +#define SSI0_CC_R (*((volatile uint32_t *)0x40008FC8)) + +//***************************************************************************** +// +// SSI registers (SSI1) +// +//***************************************************************************** +#define SSI1_CR0_R (*((volatile uint32_t *)0x40009000)) +#define SSI1_CR1_R (*((volatile uint32_t *)0x40009004)) +#define SSI1_DR_R (*((volatile uint32_t *)0x40009008)) +#define SSI1_SR_R (*((volatile uint32_t *)0x4000900C)) +#define SSI1_CPSR_R (*((volatile uint32_t *)0x40009010)) +#define SSI1_IM_R (*((volatile uint32_t *)0x40009014)) +#define SSI1_RIS_R (*((volatile uint32_t *)0x40009018)) +#define SSI1_MIS_R (*((volatile uint32_t *)0x4000901C)) +#define SSI1_ICR_R (*((volatile uint32_t *)0x40009020)) +#define SSI1_DMACTL_R (*((volatile uint32_t *)0x40009024)) +#define SSI1_CC_R (*((volatile uint32_t *)0x40009FC8)) + +//***************************************************************************** +// +// SSI registers (SSI2) +// +//***************************************************************************** +#define SSI2_CR0_R (*((volatile uint32_t *)0x4000A000)) +#define SSI2_CR1_R (*((volatile uint32_t *)0x4000A004)) +#define SSI2_DR_R (*((volatile uint32_t *)0x4000A008)) +#define SSI2_SR_R (*((volatile uint32_t *)0x4000A00C)) +#define SSI2_CPSR_R (*((volatile uint32_t *)0x4000A010)) +#define SSI2_IM_R (*((volatile uint32_t *)0x4000A014)) +#define SSI2_RIS_R (*((volatile uint32_t *)0x4000A018)) +#define SSI2_MIS_R (*((volatile uint32_t *)0x4000A01C)) +#define SSI2_ICR_R (*((volatile uint32_t *)0x4000A020)) +#define SSI2_DMACTL_R (*((volatile uint32_t *)0x4000A024)) +#define SSI2_CC_R (*((volatile uint32_t *)0x4000AFC8)) + +//***************************************************************************** +// +// SSI registers (SSI3) +// +//***************************************************************************** +#define SSI3_CR0_R (*((volatile uint32_t *)0x4000B000)) +#define SSI3_CR1_R (*((volatile uint32_t *)0x4000B004)) +#define SSI3_DR_R (*((volatile uint32_t *)0x4000B008)) +#define SSI3_SR_R (*((volatile uint32_t *)0x4000B00C)) +#define SSI3_CPSR_R (*((volatile uint32_t *)0x4000B010)) +#define SSI3_IM_R (*((volatile uint32_t *)0x4000B014)) +#define SSI3_RIS_R (*((volatile uint32_t *)0x4000B018)) +#define SSI3_MIS_R (*((volatile uint32_t *)0x4000B01C)) +#define SSI3_ICR_R (*((volatile uint32_t *)0x4000B020)) +#define SSI3_DMACTL_R (*((volatile uint32_t *)0x4000B024)) +#define SSI3_CC_R (*((volatile uint32_t *)0x4000BFC8)) + +//***************************************************************************** +// +// UART registers (UART0) +// +//***************************************************************************** +#define UART0_DR_R (*((volatile uint32_t *)0x4000C000)) +#define UART0_RSR_R (*((volatile uint32_t *)0x4000C004)) +#define UART0_ECR_R (*((volatile uint32_t *)0x4000C004)) +#define UART0_FR_R (*((volatile uint32_t *)0x4000C018)) +#define UART0_ILPR_R (*((volatile uint32_t *)0x4000C020)) +#define UART0_IBRD_R (*((volatile uint32_t *)0x4000C024)) +#define UART0_FBRD_R (*((volatile uint32_t *)0x4000C028)) +#define UART0_LCRH_R (*((volatile uint32_t *)0x4000C02C)) +#define UART0_CTL_R (*((volatile uint32_t *)0x4000C030)) +#define UART0_IFLS_R (*((volatile uint32_t *)0x4000C034)) +#define UART0_IM_R (*((volatile uint32_t *)0x4000C038)) +#define UART0_RIS_R (*((volatile uint32_t *)0x4000C03C)) +#define UART0_MIS_R (*((volatile uint32_t *)0x4000C040)) +#define UART0_ICR_R (*((volatile uint32_t *)0x4000C044)) +#define UART0_DMACTL_R (*((volatile uint32_t *)0x4000C048)) +#define UART0_9BITADDR_R (*((volatile uint32_t *)0x4000C0A4)) +#define UART0_9BITAMASK_R (*((volatile uint32_t *)0x4000C0A8)) +#define UART0_PP_R (*((volatile uint32_t *)0x4000CFC0)) +#define UART0_CC_R (*((volatile uint32_t *)0x4000CFC8)) + +//***************************************************************************** +// +// UART registers (UART1) +// +//***************************************************************************** +#define UART1_DR_R (*((volatile uint32_t *)0x4000D000)) +#define UART1_RSR_R (*((volatile uint32_t *)0x4000D004)) +#define UART1_ECR_R (*((volatile uint32_t *)0x4000D004)) +#define UART1_FR_R (*((volatile uint32_t *)0x4000D018)) +#define UART1_ILPR_R (*((volatile uint32_t *)0x4000D020)) +#define UART1_IBRD_R (*((volatile uint32_t *)0x4000D024)) +#define UART1_FBRD_R (*((volatile uint32_t *)0x4000D028)) +#define UART1_LCRH_R (*((volatile uint32_t *)0x4000D02C)) +#define UART1_CTL_R (*((volatile uint32_t *)0x4000D030)) +#define UART1_IFLS_R (*((volatile uint32_t *)0x4000D034)) +#define UART1_IM_R (*((volatile uint32_t *)0x4000D038)) +#define UART1_RIS_R (*((volatile uint32_t *)0x4000D03C)) +#define UART1_MIS_R (*((volatile uint32_t *)0x4000D040)) +#define UART1_ICR_R (*((volatile uint32_t *)0x4000D044)) +#define UART1_DMACTL_R (*((volatile uint32_t *)0x4000D048)) +#define UART1_9BITADDR_R (*((volatile uint32_t *)0x4000D0A4)) +#define UART1_9BITAMASK_R (*((volatile uint32_t *)0x4000D0A8)) +#define UART1_PP_R (*((volatile uint32_t *)0x4000DFC0)) +#define UART1_CC_R (*((volatile uint32_t *)0x4000DFC8)) + +//***************************************************************************** +// +// UART registers (UART2) +// +//***************************************************************************** +#define UART2_DR_R (*((volatile uint32_t *)0x4000E000)) +#define UART2_RSR_R (*((volatile uint32_t *)0x4000E004)) +#define UART2_ECR_R (*((volatile uint32_t *)0x4000E004)) +#define UART2_FR_R (*((volatile uint32_t *)0x4000E018)) +#define UART2_ILPR_R (*((volatile uint32_t *)0x4000E020)) +#define UART2_IBRD_R (*((volatile uint32_t *)0x4000E024)) +#define UART2_FBRD_R (*((volatile uint32_t *)0x4000E028)) +#define UART2_LCRH_R (*((volatile uint32_t *)0x4000E02C)) +#define UART2_CTL_R (*((volatile uint32_t *)0x4000E030)) +#define UART2_IFLS_R (*((volatile uint32_t *)0x4000E034)) +#define UART2_IM_R (*((volatile uint32_t *)0x4000E038)) +#define UART2_RIS_R (*((volatile uint32_t *)0x4000E03C)) +#define UART2_MIS_R (*((volatile uint32_t *)0x4000E040)) +#define UART2_ICR_R (*((volatile uint32_t *)0x4000E044)) +#define UART2_DMACTL_R (*((volatile uint32_t *)0x4000E048)) +#define UART2_9BITADDR_R (*((volatile uint32_t *)0x4000E0A4)) +#define UART2_9BITAMASK_R (*((volatile uint32_t *)0x4000E0A8)) +#define UART2_PP_R (*((volatile uint32_t *)0x4000EFC0)) +#define UART2_CC_R (*((volatile uint32_t *)0x4000EFC8)) + +//***************************************************************************** +// +// UART registers (UART3) +// +//***************************************************************************** +#define UART3_DR_R (*((volatile uint32_t *)0x4000F000)) +#define UART3_RSR_R (*((volatile uint32_t *)0x4000F004)) +#define UART3_ECR_R (*((volatile uint32_t *)0x4000F004)) +#define UART3_FR_R (*((volatile uint32_t *)0x4000F018)) +#define UART3_ILPR_R (*((volatile uint32_t *)0x4000F020)) +#define UART3_IBRD_R (*((volatile uint32_t *)0x4000F024)) +#define UART3_FBRD_R (*((volatile uint32_t *)0x4000F028)) +#define UART3_LCRH_R (*((volatile uint32_t *)0x4000F02C)) +#define UART3_CTL_R (*((volatile uint32_t *)0x4000F030)) +#define UART3_IFLS_R (*((volatile uint32_t *)0x4000F034)) +#define UART3_IM_R (*((volatile uint32_t *)0x4000F038)) +#define UART3_RIS_R (*((volatile uint32_t *)0x4000F03C)) +#define UART3_MIS_R (*((volatile uint32_t *)0x4000F040)) +#define UART3_ICR_R (*((volatile uint32_t *)0x4000F044)) +#define UART3_DMACTL_R (*((volatile uint32_t *)0x4000F048)) +#define UART3_9BITADDR_R (*((volatile uint32_t *)0x4000F0A4)) +#define UART3_9BITAMASK_R (*((volatile uint32_t *)0x4000F0A8)) +#define UART3_PP_R (*((volatile uint32_t *)0x4000FFC0)) +#define UART3_CC_R (*((volatile uint32_t *)0x4000FFC8)) + +//***************************************************************************** +// +// UART registers (UART4) +// +//***************************************************************************** +#define UART4_DR_R (*((volatile uint32_t *)0x40010000)) +#define UART4_RSR_R (*((volatile uint32_t *)0x40010004)) +#define UART4_ECR_R (*((volatile uint32_t *)0x40010004)) +#define UART4_FR_R (*((volatile uint32_t *)0x40010018)) +#define UART4_ILPR_R (*((volatile uint32_t *)0x40010020)) +#define UART4_IBRD_R (*((volatile uint32_t *)0x40010024)) +#define UART4_FBRD_R (*((volatile uint32_t *)0x40010028)) +#define UART4_LCRH_R (*((volatile uint32_t *)0x4001002C)) +#define UART4_CTL_R (*((volatile uint32_t *)0x40010030)) +#define UART4_IFLS_R (*((volatile uint32_t *)0x40010034)) +#define UART4_IM_R (*((volatile uint32_t *)0x40010038)) +#define UART4_RIS_R (*((volatile uint32_t *)0x4001003C)) +#define UART4_MIS_R (*((volatile uint32_t *)0x40010040)) +#define UART4_ICR_R (*((volatile uint32_t *)0x40010044)) +#define UART4_DMACTL_R (*((volatile uint32_t *)0x40010048)) +#define UART4_9BITADDR_R (*((volatile uint32_t *)0x400100A4)) +#define UART4_9BITAMASK_R (*((volatile uint32_t *)0x400100A8)) +#define UART4_PP_R (*((volatile uint32_t *)0x40010FC0)) +#define UART4_CC_R (*((volatile uint32_t *)0x40010FC8)) + +//***************************************************************************** +// +// UART registers (UART5) +// +//***************************************************************************** +#define UART5_DR_R (*((volatile uint32_t *)0x40011000)) +#define UART5_RSR_R (*((volatile uint32_t *)0x40011004)) +#define UART5_ECR_R (*((volatile uint32_t *)0x40011004)) +#define UART5_FR_R (*((volatile uint32_t *)0x40011018)) +#define UART5_ILPR_R (*((volatile uint32_t *)0x40011020)) +#define UART5_IBRD_R (*((volatile uint32_t *)0x40011024)) +#define UART5_FBRD_R (*((volatile uint32_t *)0x40011028)) +#define UART5_LCRH_R (*((volatile uint32_t *)0x4001102C)) +#define UART5_CTL_R (*((volatile uint32_t *)0x40011030)) +#define UART5_IFLS_R (*((volatile uint32_t *)0x40011034)) +#define UART5_IM_R (*((volatile uint32_t *)0x40011038)) +#define UART5_RIS_R (*((volatile uint32_t *)0x4001103C)) +#define UART5_MIS_R (*((volatile uint32_t *)0x40011040)) +#define UART5_ICR_R (*((volatile uint32_t *)0x40011044)) +#define UART5_DMACTL_R (*((volatile uint32_t *)0x40011048)) +#define UART5_9BITADDR_R (*((volatile uint32_t *)0x400110A4)) +#define UART5_9BITAMASK_R (*((volatile uint32_t *)0x400110A8)) +#define UART5_PP_R (*((volatile uint32_t *)0x40011FC0)) +#define UART5_CC_R (*((volatile uint32_t *)0x40011FC8)) + +//***************************************************************************** +// +// UART registers (UART6) +// +//***************************************************************************** +#define UART6_DR_R (*((volatile uint32_t *)0x40012000)) +#define UART6_RSR_R (*((volatile uint32_t *)0x40012004)) +#define UART6_ECR_R (*((volatile uint32_t *)0x40012004)) +#define UART6_FR_R (*((volatile uint32_t *)0x40012018)) +#define UART6_ILPR_R (*((volatile uint32_t *)0x40012020)) +#define UART6_IBRD_R (*((volatile uint32_t *)0x40012024)) +#define UART6_FBRD_R (*((volatile uint32_t *)0x40012028)) +#define UART6_LCRH_R (*((volatile uint32_t *)0x4001202C)) +#define UART6_CTL_R (*((volatile uint32_t *)0x40012030)) +#define UART6_IFLS_R (*((volatile uint32_t *)0x40012034)) +#define UART6_IM_R (*((volatile uint32_t *)0x40012038)) +#define UART6_RIS_R (*((volatile uint32_t *)0x4001203C)) +#define UART6_MIS_R (*((volatile uint32_t *)0x40012040)) +#define UART6_ICR_R (*((volatile uint32_t *)0x40012044)) +#define UART6_DMACTL_R (*((volatile uint32_t *)0x40012048)) +#define UART6_9BITADDR_R (*((volatile uint32_t *)0x400120A4)) +#define UART6_9BITAMASK_R (*((volatile uint32_t *)0x400120A8)) +#define UART6_PP_R (*((volatile uint32_t *)0x40012FC0)) +#define UART6_CC_R (*((volatile uint32_t *)0x40012FC8)) + +//***************************************************************************** +// +// UART registers (UART7) +// +//***************************************************************************** +#define UART7_DR_R (*((volatile uint32_t *)0x40013000)) +#define UART7_RSR_R (*((volatile uint32_t *)0x40013004)) +#define UART7_ECR_R (*((volatile uint32_t *)0x40013004)) +#define UART7_FR_R (*((volatile uint32_t *)0x40013018)) +#define UART7_ILPR_R (*((volatile uint32_t *)0x40013020)) +#define UART7_IBRD_R (*((volatile uint32_t *)0x40013024)) +#define UART7_FBRD_R (*((volatile uint32_t *)0x40013028)) +#define UART7_LCRH_R (*((volatile uint32_t *)0x4001302C)) +#define UART7_CTL_R (*((volatile uint32_t *)0x40013030)) +#define UART7_IFLS_R (*((volatile uint32_t *)0x40013034)) +#define UART7_IM_R (*((volatile uint32_t *)0x40013038)) +#define UART7_RIS_R (*((volatile uint32_t *)0x4001303C)) +#define UART7_MIS_R (*((volatile uint32_t *)0x40013040)) +#define UART7_ICR_R (*((volatile uint32_t *)0x40013044)) +#define UART7_DMACTL_R (*((volatile uint32_t *)0x40013048)) +#define UART7_9BITADDR_R (*((volatile uint32_t *)0x400130A4)) +#define UART7_9BITAMASK_R (*((volatile uint32_t *)0x400130A8)) +#define UART7_PP_R (*((volatile uint32_t *)0x40013FC0)) +#define UART7_CC_R (*((volatile uint32_t *)0x40013FC8)) + +//***************************************************************************** +// +// I2C registers (I2C0) +// +//***************************************************************************** +#define I2C0_MSA_R (*((volatile uint32_t *)0x40020000)) +#define I2C0_MCS_R (*((volatile uint32_t *)0x40020004)) +#define I2C0_MDR_R (*((volatile uint32_t *)0x40020008)) +#define I2C0_MTPR_R (*((volatile uint32_t *)0x4002000C)) +#define I2C0_MIMR_R (*((volatile uint32_t *)0x40020010)) +#define I2C0_MRIS_R (*((volatile uint32_t *)0x40020014)) +#define I2C0_MMIS_R (*((volatile uint32_t *)0x40020018)) +#define I2C0_MICR_R (*((volatile uint32_t *)0x4002001C)) +#define I2C0_MCR_R (*((volatile uint32_t *)0x40020020)) +#define I2C0_MCLKOCNT_R (*((volatile uint32_t *)0x40020024)) +#define I2C0_MBMON_R (*((volatile uint32_t *)0x4002002C)) +#define I2C0_MCR2_R (*((volatile uint32_t *)0x40020038)) +#define I2C0_SOAR_R (*((volatile uint32_t *)0x40020800)) +#define I2C0_SCSR_R (*((volatile uint32_t *)0x40020804)) +#define I2C0_SDR_R (*((volatile uint32_t *)0x40020808)) +#define I2C0_SIMR_R (*((volatile uint32_t *)0x4002080C)) +#define I2C0_SRIS_R (*((volatile uint32_t *)0x40020810)) +#define I2C0_SMIS_R (*((volatile uint32_t *)0x40020814)) +#define I2C0_SICR_R (*((volatile uint32_t *)0x40020818)) +#define I2C0_SOAR2_R (*((volatile uint32_t *)0x4002081C)) +#define I2C0_SACKCTL_R (*((volatile uint32_t *)0x40020820)) +#define I2C0_PP_R (*((volatile uint32_t *)0x40020FC0)) +#define I2C0_PC_R (*((volatile uint32_t *)0x40020FC4)) + +//***************************************************************************** +// +// I2C registers (I2C1) +// +//***************************************************************************** +#define I2C1_MSA_R (*((volatile uint32_t *)0x40021000)) +#define I2C1_MCS_R (*((volatile uint32_t *)0x40021004)) +#define I2C1_MDR_R (*((volatile uint32_t *)0x40021008)) +#define I2C1_MTPR_R (*((volatile uint32_t *)0x4002100C)) +#define I2C1_MIMR_R (*((volatile uint32_t *)0x40021010)) +#define I2C1_MRIS_R (*((volatile uint32_t *)0x40021014)) +#define I2C1_MMIS_R (*((volatile uint32_t *)0x40021018)) +#define I2C1_MICR_R (*((volatile uint32_t *)0x4002101C)) +#define I2C1_MCR_R (*((volatile uint32_t *)0x40021020)) +#define I2C1_MCLKOCNT_R (*((volatile uint32_t *)0x40021024)) +#define I2C1_MBMON_R (*((volatile uint32_t *)0x4002102C)) +#define I2C1_MCR2_R (*((volatile uint32_t *)0x40021038)) +#define I2C1_SOAR_R (*((volatile uint32_t *)0x40021800)) +#define I2C1_SCSR_R (*((volatile uint32_t *)0x40021804)) +#define I2C1_SDR_R (*((volatile uint32_t *)0x40021808)) +#define I2C1_SIMR_R (*((volatile uint32_t *)0x4002180C)) +#define I2C1_SRIS_R (*((volatile uint32_t *)0x40021810)) +#define I2C1_SMIS_R (*((volatile uint32_t *)0x40021814)) +#define I2C1_SICR_R (*((volatile uint32_t *)0x40021818)) +#define I2C1_SOAR2_R (*((volatile uint32_t *)0x4002181C)) +#define I2C1_SACKCTL_R (*((volatile uint32_t *)0x40021820)) +#define I2C1_PP_R (*((volatile uint32_t *)0x40021FC0)) +#define I2C1_PC_R (*((volatile uint32_t *)0x40021FC4)) + +//***************************************************************************** +// +// I2C registers (I2C2) +// +//***************************************************************************** +#define I2C2_MSA_R (*((volatile uint32_t *)0x40022000)) +#define I2C2_MCS_R (*((volatile uint32_t *)0x40022004)) +#define I2C2_MDR_R (*((volatile uint32_t *)0x40022008)) +#define I2C2_MTPR_R (*((volatile uint32_t *)0x4002200C)) +#define I2C2_MIMR_R (*((volatile uint32_t *)0x40022010)) +#define I2C2_MRIS_R (*((volatile uint32_t *)0x40022014)) +#define I2C2_MMIS_R (*((volatile uint32_t *)0x40022018)) +#define I2C2_MICR_R (*((volatile uint32_t *)0x4002201C)) +#define I2C2_MCR_R (*((volatile uint32_t *)0x40022020)) +#define I2C2_MCLKOCNT_R (*((volatile uint32_t *)0x40022024)) +#define I2C2_MBMON_R (*((volatile uint32_t *)0x4002202C)) +#define I2C2_MCR2_R (*((volatile uint32_t *)0x40022038)) +#define I2C2_SOAR_R (*((volatile uint32_t *)0x40022800)) +#define I2C2_SCSR_R (*((volatile uint32_t *)0x40022804)) +#define I2C2_SDR_R (*((volatile uint32_t *)0x40022808)) +#define I2C2_SIMR_R (*((volatile uint32_t *)0x4002280C)) +#define I2C2_SRIS_R (*((volatile uint32_t *)0x40022810)) +#define I2C2_SMIS_R (*((volatile uint32_t *)0x40022814)) +#define I2C2_SICR_R (*((volatile uint32_t *)0x40022818)) +#define I2C2_SOAR2_R (*((volatile uint32_t *)0x4002281C)) +#define I2C2_SACKCTL_R (*((volatile uint32_t *)0x40022820)) +#define I2C2_PP_R (*((volatile uint32_t *)0x40022FC0)) +#define I2C2_PC_R (*((volatile uint32_t *)0x40022FC4)) + +//***************************************************************************** +// +// I2C registers (I2C3) +// +//***************************************************************************** +#define I2C3_MSA_R (*((volatile uint32_t *)0x40023000)) +#define I2C3_MCS_R (*((volatile uint32_t *)0x40023004)) +#define I2C3_MDR_R (*((volatile uint32_t *)0x40023008)) +#define I2C3_MTPR_R (*((volatile uint32_t *)0x4002300C)) +#define I2C3_MIMR_R (*((volatile uint32_t *)0x40023010)) +#define I2C3_MRIS_R (*((volatile uint32_t *)0x40023014)) +#define I2C3_MMIS_R (*((volatile uint32_t *)0x40023018)) +#define I2C3_MICR_R (*((volatile uint32_t *)0x4002301C)) +#define I2C3_MCR_R (*((volatile uint32_t *)0x40023020)) +#define I2C3_MCLKOCNT_R (*((volatile uint32_t *)0x40023024)) +#define I2C3_MBMON_R (*((volatile uint32_t *)0x4002302C)) +#define I2C3_MCR2_R (*((volatile uint32_t *)0x40023038)) +#define I2C3_SOAR_R (*((volatile uint32_t *)0x40023800)) +#define I2C3_SCSR_R (*((volatile uint32_t *)0x40023804)) +#define I2C3_SDR_R (*((volatile uint32_t *)0x40023808)) +#define I2C3_SIMR_R (*((volatile uint32_t *)0x4002380C)) +#define I2C3_SRIS_R (*((volatile uint32_t *)0x40023810)) +#define I2C3_SMIS_R (*((volatile uint32_t *)0x40023814)) +#define I2C3_SICR_R (*((volatile uint32_t *)0x40023818)) +#define I2C3_SOAR2_R (*((volatile uint32_t *)0x4002381C)) +#define I2C3_SACKCTL_R (*((volatile uint32_t *)0x40023820)) +#define I2C3_PP_R (*((volatile uint32_t *)0x40023FC0)) +#define I2C3_PC_R (*((volatile uint32_t *)0x40023FC4)) + +//***************************************************************************** +// +// GPIO registers (PORTE) +// +//***************************************************************************** +#define GPIO_PORTE_DATA_BITS_R ((volatile uint32_t *)0x40024000) +#define GPIO_PORTE_DATA_R (*((volatile uint32_t *)0x400243FC)) +#define GPIO_PORTE_DIR_R (*((volatile uint32_t *)0x40024400)) +#define GPIO_PORTE_IS_R (*((volatile uint32_t *)0x40024404)) +#define GPIO_PORTE_IBE_R (*((volatile uint32_t *)0x40024408)) +#define GPIO_PORTE_IEV_R (*((volatile uint32_t *)0x4002440C)) +#define GPIO_PORTE_IM_R (*((volatile uint32_t *)0x40024410)) +#define GPIO_PORTE_RIS_R (*((volatile uint32_t *)0x40024414)) +#define GPIO_PORTE_MIS_R (*((volatile uint32_t *)0x40024418)) +#define GPIO_PORTE_ICR_R (*((volatile uint32_t *)0x4002441C)) +#define GPIO_PORTE_AFSEL_R (*((volatile uint32_t *)0x40024420)) +#define GPIO_PORTE_DR2R_R (*((volatile uint32_t *)0x40024500)) +#define GPIO_PORTE_DR4R_R (*((volatile uint32_t *)0x40024504)) +#define GPIO_PORTE_DR8R_R (*((volatile uint32_t *)0x40024508)) +#define GPIO_PORTE_ODR_R (*((volatile uint32_t *)0x4002450C)) +#define GPIO_PORTE_PUR_R (*((volatile uint32_t *)0x40024510)) +#define GPIO_PORTE_PDR_R (*((volatile uint32_t *)0x40024514)) +#define GPIO_PORTE_SLR_R (*((volatile uint32_t *)0x40024518)) +#define GPIO_PORTE_DEN_R (*((volatile uint32_t *)0x4002451C)) +#define GPIO_PORTE_LOCK_R (*((volatile uint32_t *)0x40024520)) +#define GPIO_PORTE_CR_R (*((volatile uint32_t *)0x40024524)) +#define GPIO_PORTE_AMSEL_R (*((volatile uint32_t *)0x40024528)) +#define GPIO_PORTE_PCTL_R (*((volatile uint32_t *)0x4002452C)) +#define GPIO_PORTE_ADCCTL_R (*((volatile uint32_t *)0x40024530)) +#define GPIO_PORTE_DMACTL_R (*((volatile uint32_t *)0x40024534)) + +//***************************************************************************** +// +// GPIO registers (PORTF) +// +//***************************************************************************** +#define GPIO_PORTF_DATA_BITS_R ((volatile uint32_t *)0x40025000) +#define GPIO_PORTF_DATA_R (*((volatile uint32_t *)0x400253FC)) +#define GPIO_PORTF_DIR_R (*((volatile uint32_t *)0x40025400)) +#define GPIO_PORTF_IS_R (*((volatile uint32_t *)0x40025404)) +#define GPIO_PORTF_IBE_R (*((volatile uint32_t *)0x40025408)) +#define GPIO_PORTF_IEV_R (*((volatile uint32_t *)0x4002540C)) +#define GPIO_PORTF_IM_R (*((volatile uint32_t *)0x40025410)) +#define GPIO_PORTF_RIS_R (*((volatile uint32_t *)0x40025414)) +#define GPIO_PORTF_MIS_R (*((volatile uint32_t *)0x40025418)) +#define GPIO_PORTF_ICR_R (*((volatile uint32_t *)0x4002541C)) +#define GPIO_PORTF_AFSEL_R (*((volatile uint32_t *)0x40025420)) +#define GPIO_PORTF_DR2R_R (*((volatile uint32_t *)0x40025500)) +#define GPIO_PORTF_DR4R_R (*((volatile uint32_t *)0x40025504)) +#define GPIO_PORTF_DR8R_R (*((volatile uint32_t *)0x40025508)) +#define GPIO_PORTF_ODR_R (*((volatile uint32_t *)0x4002550C)) +#define GPIO_PORTF_PUR_R (*((volatile uint32_t *)0x40025510)) +#define GPIO_PORTF_PDR_R (*((volatile uint32_t *)0x40025514)) +#define GPIO_PORTF_SLR_R (*((volatile uint32_t *)0x40025518)) +#define GPIO_PORTF_DEN_R (*((volatile uint32_t *)0x4002551C)) +#define GPIO_PORTF_LOCK_R (*((volatile uint32_t *)0x40025520)) +#define GPIO_PORTF_CR_R (*((volatile uint32_t *)0x40025524)) +#define GPIO_PORTF_AMSEL_R (*((volatile uint32_t *)0x40025528)) +#define GPIO_PORTF_PCTL_R (*((volatile uint32_t *)0x4002552C)) +#define GPIO_PORTF_ADCCTL_R (*((volatile uint32_t *)0x40025530)) +#define GPIO_PORTF_DMACTL_R (*((volatile uint32_t *)0x40025534)) + +//***************************************************************************** +// +// GPIO registers (PORTG) +// +//***************************************************************************** +#define GPIO_PORTG_DATA_BITS_R ((volatile uint32_t *)0x40026000) +#define GPIO_PORTG_DATA_R (*((volatile uint32_t *)0x400263FC)) +#define GPIO_PORTG_DIR_R (*((volatile uint32_t *)0x40026400)) +#define GPIO_PORTG_IS_R (*((volatile uint32_t *)0x40026404)) +#define GPIO_PORTG_IBE_R (*((volatile uint32_t *)0x40026408)) +#define GPIO_PORTG_IEV_R (*((volatile uint32_t *)0x4002640C)) +#define GPIO_PORTG_IM_R (*((volatile uint32_t *)0x40026410)) +#define GPIO_PORTG_RIS_R (*((volatile uint32_t *)0x40026414)) +#define GPIO_PORTG_MIS_R (*((volatile uint32_t *)0x40026418)) +#define GPIO_PORTG_ICR_R (*((volatile uint32_t *)0x4002641C)) +#define GPIO_PORTG_AFSEL_R (*((volatile uint32_t *)0x40026420)) +#define GPIO_PORTG_DR2R_R (*((volatile uint32_t *)0x40026500)) +#define GPIO_PORTG_DR4R_R (*((volatile uint32_t *)0x40026504)) +#define GPIO_PORTG_DR8R_R (*((volatile uint32_t *)0x40026508)) +#define GPIO_PORTG_ODR_R (*((volatile uint32_t *)0x4002650C)) +#define GPIO_PORTG_PUR_R (*((volatile uint32_t *)0x40026510)) +#define GPIO_PORTG_PDR_R (*((volatile uint32_t *)0x40026514)) +#define GPIO_PORTG_SLR_R (*((volatile uint32_t *)0x40026518)) +#define GPIO_PORTG_DEN_R (*((volatile uint32_t *)0x4002651C)) +#define GPIO_PORTG_LOCK_R (*((volatile uint32_t *)0x40026520)) +#define GPIO_PORTG_CR_R (*((volatile uint32_t *)0x40026524)) +#define GPIO_PORTG_AMSEL_R (*((volatile uint32_t *)0x40026528)) +#define GPIO_PORTG_PCTL_R (*((volatile uint32_t *)0x4002652C)) +#define GPIO_PORTG_ADCCTL_R (*((volatile uint32_t *)0x40026530)) +#define GPIO_PORTG_DMACTL_R (*((volatile uint32_t *)0x40026534)) + +//***************************************************************************** +// +// GPIO registers (PORTH) +// +//***************************************************************************** +#define GPIO_PORTH_DATA_BITS_R ((volatile uint32_t *)0x40027000) +#define GPIO_PORTH_DATA_R (*((volatile uint32_t *)0x400273FC)) +#define GPIO_PORTH_DIR_R (*((volatile uint32_t *)0x40027400)) +#define GPIO_PORTH_IS_R (*((volatile uint32_t *)0x40027404)) +#define GPIO_PORTH_IBE_R (*((volatile uint32_t *)0x40027408)) +#define GPIO_PORTH_IEV_R (*((volatile uint32_t *)0x4002740C)) +#define GPIO_PORTH_IM_R (*((volatile uint32_t *)0x40027410)) +#define GPIO_PORTH_RIS_R (*((volatile uint32_t *)0x40027414)) +#define GPIO_PORTH_MIS_R (*((volatile uint32_t *)0x40027418)) +#define GPIO_PORTH_ICR_R (*((volatile uint32_t *)0x4002741C)) +#define GPIO_PORTH_AFSEL_R (*((volatile uint32_t *)0x40027420)) +#define GPIO_PORTH_DR2R_R (*((volatile uint32_t *)0x40027500)) +#define GPIO_PORTH_DR4R_R (*((volatile uint32_t *)0x40027504)) +#define GPIO_PORTH_DR8R_R (*((volatile uint32_t *)0x40027508)) +#define GPIO_PORTH_ODR_R (*((volatile uint32_t *)0x4002750C)) +#define GPIO_PORTH_PUR_R (*((volatile uint32_t *)0x40027510)) +#define GPIO_PORTH_PDR_R (*((volatile uint32_t *)0x40027514)) +#define GPIO_PORTH_SLR_R (*((volatile uint32_t *)0x40027518)) +#define GPIO_PORTH_DEN_R (*((volatile uint32_t *)0x4002751C)) +#define GPIO_PORTH_LOCK_R (*((volatile uint32_t *)0x40027520)) +#define GPIO_PORTH_CR_R (*((volatile uint32_t *)0x40027524)) +#define GPIO_PORTH_AMSEL_R (*((volatile uint32_t *)0x40027528)) +#define GPIO_PORTH_PCTL_R (*((volatile uint32_t *)0x4002752C)) +#define GPIO_PORTH_ADCCTL_R (*((volatile uint32_t *)0x40027530)) +#define GPIO_PORTH_DMACTL_R (*((volatile uint32_t *)0x40027534)) + +//***************************************************************************** +// +// PWM registers (PWM0) +// +//***************************************************************************** +#define PWM0_CTL_R (*((volatile uint32_t *)0x40028000)) +#define PWM0_SYNC_R (*((volatile uint32_t *)0x40028004)) +#define PWM0_ENABLE_R (*((volatile uint32_t *)0x40028008)) +#define PWM0_INVERT_R (*((volatile uint32_t *)0x4002800C)) +#define PWM0_FAULT_R (*((volatile uint32_t *)0x40028010)) +#define PWM0_INTEN_R (*((volatile uint32_t *)0x40028014)) +#define PWM0_RIS_R (*((volatile uint32_t *)0x40028018)) +#define PWM0_ISC_R (*((volatile uint32_t *)0x4002801C)) +#define PWM0_STATUS_R (*((volatile uint32_t *)0x40028020)) +#define PWM0_FAULTVAL_R (*((volatile uint32_t *)0x40028024)) +#define PWM0_ENUPD_R (*((volatile uint32_t *)0x40028028)) +#define PWM0_0_CTL_R (*((volatile uint32_t *)0x40028040)) +#define PWM0_0_INTEN_R (*((volatile uint32_t *)0x40028044)) +#define PWM0_0_RIS_R (*((volatile uint32_t *)0x40028048)) +#define PWM0_0_ISC_R (*((volatile uint32_t *)0x4002804C)) +#define PWM0_0_LOAD_R (*((volatile uint32_t *)0x40028050)) +#define PWM0_0_COUNT_R (*((volatile uint32_t *)0x40028054)) +#define PWM0_0_CMPA_R (*((volatile uint32_t *)0x40028058)) +#define PWM0_0_CMPB_R (*((volatile uint32_t *)0x4002805C)) +#define PWM0_0_GENA_R (*((volatile uint32_t *)0x40028060)) +#define PWM0_0_GENB_R (*((volatile uint32_t *)0x40028064)) +#define PWM0_0_DBCTL_R (*((volatile uint32_t *)0x40028068)) +#define PWM0_0_DBRISE_R (*((volatile uint32_t *)0x4002806C)) +#define PWM0_0_DBFALL_R (*((volatile uint32_t *)0x40028070)) +#define PWM0_0_FLTSRC0_R (*((volatile uint32_t *)0x40028074)) +#define PWM0_0_FLTSRC1_R (*((volatile uint32_t *)0x40028078)) +#define PWM0_0_MINFLTPER_R (*((volatile uint32_t *)0x4002807C)) +#define PWM0_1_CTL_R (*((volatile uint32_t *)0x40028080)) +#define PWM0_1_INTEN_R (*((volatile uint32_t *)0x40028084)) +#define PWM0_1_RIS_R (*((volatile uint32_t *)0x40028088)) +#define PWM0_1_ISC_R (*((volatile uint32_t *)0x4002808C)) +#define PWM0_1_LOAD_R (*((volatile uint32_t *)0x40028090)) +#define PWM0_1_COUNT_R (*((volatile uint32_t *)0x40028094)) +#define PWM0_1_CMPA_R (*((volatile uint32_t *)0x40028098)) +#define PWM0_1_CMPB_R (*((volatile uint32_t *)0x4002809C)) +#define PWM0_1_GENA_R (*((volatile uint32_t *)0x400280A0)) +#define PWM0_1_GENB_R (*((volatile uint32_t *)0x400280A4)) +#define PWM0_1_DBCTL_R (*((volatile uint32_t *)0x400280A8)) +#define PWM0_1_DBRISE_R (*((volatile uint32_t *)0x400280AC)) +#define PWM0_1_DBFALL_R (*((volatile uint32_t *)0x400280B0)) +#define PWM0_1_FLTSRC0_R (*((volatile uint32_t *)0x400280B4)) +#define PWM0_1_FLTSRC1_R (*((volatile uint32_t *)0x400280B8)) +#define PWM0_1_MINFLTPER_R (*((volatile uint32_t *)0x400280BC)) +#define PWM0_2_CTL_R (*((volatile uint32_t *)0x400280C0)) +#define PWM0_2_INTEN_R (*((volatile uint32_t *)0x400280C4)) +#define PWM0_2_RIS_R (*((volatile uint32_t *)0x400280C8)) +#define PWM0_2_ISC_R (*((volatile uint32_t *)0x400280CC)) +#define PWM0_2_LOAD_R (*((volatile uint32_t *)0x400280D0)) +#define PWM0_2_COUNT_R (*((volatile uint32_t *)0x400280D4)) +#define PWM0_2_CMPA_R (*((volatile uint32_t *)0x400280D8)) +#define PWM0_2_CMPB_R (*((volatile uint32_t *)0x400280DC)) +#define PWM0_2_GENA_R (*((volatile uint32_t *)0x400280E0)) +#define PWM0_2_GENB_R (*((volatile uint32_t *)0x400280E4)) +#define PWM0_2_DBCTL_R (*((volatile uint32_t *)0x400280E8)) +#define PWM0_2_DBRISE_R (*((volatile uint32_t *)0x400280EC)) +#define PWM0_2_DBFALL_R (*((volatile uint32_t *)0x400280F0)) +#define PWM0_2_FLTSRC0_R (*((volatile uint32_t *)0x400280F4)) +#define PWM0_2_FLTSRC1_R (*((volatile uint32_t *)0x400280F8)) +#define PWM0_2_MINFLTPER_R (*((volatile uint32_t *)0x400280FC)) +#define PWM0_3_CTL_R (*((volatile uint32_t *)0x40028100)) +#define PWM0_3_INTEN_R (*((volatile uint32_t *)0x40028104)) +#define PWM0_3_RIS_R (*((volatile uint32_t *)0x40028108)) +#define PWM0_3_ISC_R (*((volatile uint32_t *)0x4002810C)) +#define PWM0_3_LOAD_R (*((volatile uint32_t *)0x40028110)) +#define PWM0_3_COUNT_R (*((volatile uint32_t *)0x40028114)) +#define PWM0_3_CMPA_R (*((volatile uint32_t *)0x40028118)) +#define PWM0_3_CMPB_R (*((volatile uint32_t *)0x4002811C)) +#define PWM0_3_GENA_R (*((volatile uint32_t *)0x40028120)) +#define PWM0_3_GENB_R (*((volatile uint32_t *)0x40028124)) +#define PWM0_3_DBCTL_R (*((volatile uint32_t *)0x40028128)) +#define PWM0_3_DBRISE_R (*((volatile uint32_t *)0x4002812C)) +#define PWM0_3_DBFALL_R (*((volatile uint32_t *)0x40028130)) +#define PWM0_3_FLTSRC0_R (*((volatile uint32_t *)0x40028134)) +#define PWM0_3_FLTSRC1_R (*((volatile uint32_t *)0x40028138)) +#define PWM0_3_MINFLTPER_R (*((volatile uint32_t *)0x4002813C)) +#define PWM0_0_FLTSEN_R (*((volatile uint32_t *)0x40028800)) +#define PWM0_0_FLTSTAT0_R (*((volatile uint32_t *)0x40028804)) +#define PWM0_0_FLTSTAT1_R (*((volatile uint32_t *)0x40028808)) +#define PWM0_1_FLTSEN_R (*((volatile uint32_t *)0x40028880)) +#define PWM0_1_FLTSTAT0_R (*((volatile uint32_t *)0x40028884)) +#define PWM0_1_FLTSTAT1_R (*((volatile uint32_t *)0x40028888)) +#define PWM0_2_FLTSEN_R (*((volatile uint32_t *)0x40028900)) +#define PWM0_2_FLTSTAT0_R (*((volatile uint32_t *)0x40028904)) +#define PWM0_2_FLTSTAT1_R (*((volatile uint32_t *)0x40028908)) +#define PWM0_3_FLTSEN_R (*((volatile uint32_t *)0x40028980)) +#define PWM0_3_FLTSTAT0_R (*((volatile uint32_t *)0x40028984)) +#define PWM0_3_FLTSTAT1_R (*((volatile uint32_t *)0x40028988)) +#define PWM0_PP_R (*((volatile uint32_t *)0x40028FC0)) + +//***************************************************************************** +// +// PWM registers (PWM1) +// +//***************************************************************************** +#define PWM1_CTL_R (*((volatile uint32_t *)0x40029000)) +#define PWM1_SYNC_R (*((volatile uint32_t *)0x40029004)) +#define PWM1_ENABLE_R (*((volatile uint32_t *)0x40029008)) +#define PWM1_INVERT_R (*((volatile uint32_t *)0x4002900C)) +#define PWM1_FAULT_R (*((volatile uint32_t *)0x40029010)) +#define PWM1_INTEN_R (*((volatile uint32_t *)0x40029014)) +#define PWM1_RIS_R (*((volatile uint32_t *)0x40029018)) +#define PWM1_ISC_R (*((volatile uint32_t *)0x4002901C)) +#define PWM1_STATUS_R (*((volatile uint32_t *)0x40029020)) +#define PWM1_FAULTVAL_R (*((volatile uint32_t *)0x40029024)) +#define PWM1_ENUPD_R (*((volatile uint32_t *)0x40029028)) +#define PWM1_0_CTL_R (*((volatile uint32_t *)0x40029040)) +#define PWM1_0_INTEN_R (*((volatile uint32_t *)0x40029044)) +#define PWM1_0_RIS_R (*((volatile uint32_t *)0x40029048)) +#define PWM1_0_ISC_R (*((volatile uint32_t *)0x4002904C)) +#define PWM1_0_LOAD_R (*((volatile uint32_t *)0x40029050)) +#define PWM1_0_COUNT_R (*((volatile uint32_t *)0x40029054)) +#define PWM1_0_CMPA_R (*((volatile uint32_t *)0x40029058)) +#define PWM1_0_CMPB_R (*((volatile uint32_t *)0x4002905C)) +#define PWM1_0_GENA_R (*((volatile uint32_t *)0x40029060)) +#define PWM1_0_GENB_R (*((volatile uint32_t *)0x40029064)) +#define PWM1_0_DBCTL_R (*((volatile uint32_t *)0x40029068)) +#define PWM1_0_DBRISE_R (*((volatile uint32_t *)0x4002906C)) +#define PWM1_0_DBFALL_R (*((volatile uint32_t *)0x40029070)) +#define PWM1_0_FLTSRC0_R (*((volatile uint32_t *)0x40029074)) +#define PWM1_0_FLTSRC1_R (*((volatile uint32_t *)0x40029078)) +#define PWM1_0_MINFLTPER_R (*((volatile uint32_t *)0x4002907C)) +#define PWM1_1_CTL_R (*((volatile uint32_t *)0x40029080)) +#define PWM1_1_INTEN_R (*((volatile uint32_t *)0x40029084)) +#define PWM1_1_RIS_R (*((volatile uint32_t *)0x40029088)) +#define PWM1_1_ISC_R (*((volatile uint32_t *)0x4002908C)) +#define PWM1_1_LOAD_R (*((volatile uint32_t *)0x40029090)) +#define PWM1_1_COUNT_R (*((volatile uint32_t *)0x40029094)) +#define PWM1_1_CMPA_R (*((volatile uint32_t *)0x40029098)) +#define PWM1_1_CMPB_R (*((volatile uint32_t *)0x4002909C)) +#define PWM1_1_GENA_R (*((volatile uint32_t *)0x400290A0)) +#define PWM1_1_GENB_R (*((volatile uint32_t *)0x400290A4)) +#define PWM1_1_DBCTL_R (*((volatile uint32_t *)0x400290A8)) +#define PWM1_1_DBRISE_R (*((volatile uint32_t *)0x400290AC)) +#define PWM1_1_DBFALL_R (*((volatile uint32_t *)0x400290B0)) +#define PWM1_1_FLTSRC0_R (*((volatile uint32_t *)0x400290B4)) +#define PWM1_1_FLTSRC1_R (*((volatile uint32_t *)0x400290B8)) +#define PWM1_1_MINFLTPER_R (*((volatile uint32_t *)0x400290BC)) +#define PWM1_2_CTL_R (*((volatile uint32_t *)0x400290C0)) +#define PWM1_2_INTEN_R (*((volatile uint32_t *)0x400290C4)) +#define PWM1_2_RIS_R (*((volatile uint32_t *)0x400290C8)) +#define PWM1_2_ISC_R (*((volatile uint32_t *)0x400290CC)) +#define PWM1_2_LOAD_R (*((volatile uint32_t *)0x400290D0)) +#define PWM1_2_COUNT_R (*((volatile uint32_t *)0x400290D4)) +#define PWM1_2_CMPA_R (*((volatile uint32_t *)0x400290D8)) +#define PWM1_2_CMPB_R (*((volatile uint32_t *)0x400290DC)) +#define PWM1_2_GENA_R (*((volatile uint32_t *)0x400290E0)) +#define PWM1_2_GENB_R (*((volatile uint32_t *)0x400290E4)) +#define PWM1_2_DBCTL_R (*((volatile uint32_t *)0x400290E8)) +#define PWM1_2_DBRISE_R (*((volatile uint32_t *)0x400290EC)) +#define PWM1_2_DBFALL_R (*((volatile uint32_t *)0x400290F0)) +#define PWM1_2_FLTSRC0_R (*((volatile uint32_t *)0x400290F4)) +#define PWM1_2_FLTSRC1_R (*((volatile uint32_t *)0x400290F8)) +#define PWM1_2_MINFLTPER_R (*((volatile uint32_t *)0x400290FC)) +#define PWM1_3_CTL_R (*((volatile uint32_t *)0x40029100)) +#define PWM1_3_INTEN_R (*((volatile uint32_t *)0x40029104)) +#define PWM1_3_RIS_R (*((volatile uint32_t *)0x40029108)) +#define PWM1_3_ISC_R (*((volatile uint32_t *)0x4002910C)) +#define PWM1_3_LOAD_R (*((volatile uint32_t *)0x40029110)) +#define PWM1_3_COUNT_R (*((volatile uint32_t *)0x40029114)) +#define PWM1_3_CMPA_R (*((volatile uint32_t *)0x40029118)) +#define PWM1_3_CMPB_R (*((volatile uint32_t *)0x4002911C)) +#define PWM1_3_GENA_R (*((volatile uint32_t *)0x40029120)) +#define PWM1_3_GENB_R (*((volatile uint32_t *)0x40029124)) +#define PWM1_3_DBCTL_R (*((volatile uint32_t *)0x40029128)) +#define PWM1_3_DBRISE_R (*((volatile uint32_t *)0x4002912C)) +#define PWM1_3_DBFALL_R (*((volatile uint32_t *)0x40029130)) +#define PWM1_3_FLTSRC0_R (*((volatile uint32_t *)0x40029134)) +#define PWM1_3_FLTSRC1_R (*((volatile uint32_t *)0x40029138)) +#define PWM1_3_MINFLTPER_R (*((volatile uint32_t *)0x4002913C)) +#define PWM1_0_FLTSEN_R (*((volatile uint32_t *)0x40029800)) +#define PWM1_0_FLTSTAT0_R (*((volatile uint32_t *)0x40029804)) +#define PWM1_0_FLTSTAT1_R (*((volatile uint32_t *)0x40029808)) +#define PWM1_1_FLTSEN_R (*((volatile uint32_t *)0x40029880)) +#define PWM1_1_FLTSTAT0_R (*((volatile uint32_t *)0x40029884)) +#define PWM1_1_FLTSTAT1_R (*((volatile uint32_t *)0x40029888)) +#define PWM1_2_FLTSEN_R (*((volatile uint32_t *)0x40029900)) +#define PWM1_2_FLTSTAT0_R (*((volatile uint32_t *)0x40029904)) +#define PWM1_2_FLTSTAT1_R (*((volatile uint32_t *)0x40029908)) +#define PWM1_3_FLTSEN_R (*((volatile uint32_t *)0x40029980)) +#define PWM1_3_FLTSTAT0_R (*((volatile uint32_t *)0x40029984)) +#define PWM1_3_FLTSTAT1_R (*((volatile uint32_t *)0x40029988)) +#define PWM1_PP_R (*((volatile uint32_t *)0x40029FC0)) + +//***************************************************************************** +// +// QEI registers (QEI0) +// +//***************************************************************************** +#define QEI0_CTL_R (*((volatile uint32_t *)0x4002C000)) +#define QEI0_STAT_R (*((volatile uint32_t *)0x4002C004)) +#define QEI0_POS_R (*((volatile uint32_t *)0x4002C008)) +#define QEI0_MAXPOS_R (*((volatile uint32_t *)0x4002C00C)) +#define QEI0_LOAD_R (*((volatile uint32_t *)0x4002C010)) +#define QEI0_TIME_R (*((volatile uint32_t *)0x4002C014)) +#define QEI0_COUNT_R (*((volatile uint32_t *)0x4002C018)) +#define QEI0_SPEED_R (*((volatile uint32_t *)0x4002C01C)) +#define QEI0_INTEN_R (*((volatile uint32_t *)0x4002C020)) +#define QEI0_RIS_R (*((volatile uint32_t *)0x4002C024)) +#define QEI0_ISC_R (*((volatile uint32_t *)0x4002C028)) + +//***************************************************************************** +// +// QEI registers (QEI1) +// +//***************************************************************************** +#define QEI1_CTL_R (*((volatile uint32_t *)0x4002D000)) +#define QEI1_STAT_R (*((volatile uint32_t *)0x4002D004)) +#define QEI1_POS_R (*((volatile uint32_t *)0x4002D008)) +#define QEI1_MAXPOS_R (*((volatile uint32_t *)0x4002D00C)) +#define QEI1_LOAD_R (*((volatile uint32_t *)0x4002D010)) +#define QEI1_TIME_R (*((volatile uint32_t *)0x4002D014)) +#define QEI1_COUNT_R (*((volatile uint32_t *)0x4002D018)) +#define QEI1_SPEED_R (*((volatile uint32_t *)0x4002D01C)) +#define QEI1_INTEN_R (*((volatile uint32_t *)0x4002D020)) +#define QEI1_RIS_R (*((volatile uint32_t *)0x4002D024)) +#define QEI1_ISC_R (*((volatile uint32_t *)0x4002D028)) + +//***************************************************************************** +// +// Timer registers (TIMER0) +// +//***************************************************************************** +#define TIMER0_CFG_R (*((volatile uint32_t *)0x40030000)) +#define TIMER0_TAMR_R (*((volatile uint32_t *)0x40030004)) +#define TIMER0_TBMR_R (*((volatile uint32_t *)0x40030008)) +#define TIMER0_CTL_R (*((volatile uint32_t *)0x4003000C)) +#define TIMER0_SYNC_R (*((volatile uint32_t *)0x40030010)) +#define TIMER0_IMR_R (*((volatile uint32_t *)0x40030018)) +#define TIMER0_RIS_R (*((volatile uint32_t *)0x4003001C)) +#define TIMER0_MIS_R (*((volatile uint32_t *)0x40030020)) +#define TIMER0_ICR_R (*((volatile uint32_t *)0x40030024)) +#define TIMER0_TAILR_R (*((volatile uint32_t *)0x40030028)) +#define TIMER0_TBILR_R (*((volatile uint32_t *)0x4003002C)) +#define TIMER0_TAMATCHR_R (*((volatile uint32_t *)0x40030030)) +#define TIMER0_TBMATCHR_R (*((volatile uint32_t *)0x40030034)) +#define TIMER0_TAPR_R (*((volatile uint32_t *)0x40030038)) +#define TIMER0_TBPR_R (*((volatile uint32_t *)0x4003003C)) +#define TIMER0_TAPMR_R (*((volatile uint32_t *)0x40030040)) +#define TIMER0_TBPMR_R (*((volatile uint32_t *)0x40030044)) +#define TIMER0_TAR_R (*((volatile uint32_t *)0x40030048)) +#define TIMER0_TBR_R (*((volatile uint32_t *)0x4003004C)) +#define TIMER0_TAV_R (*((volatile uint32_t *)0x40030050)) +#define TIMER0_TBV_R (*((volatile uint32_t *)0x40030054)) +#define TIMER0_RTCPD_R (*((volatile uint32_t *)0x40030058)) +#define TIMER0_TAPS_R (*((volatile uint32_t *)0x4003005C)) +#define TIMER0_TBPS_R (*((volatile uint32_t *)0x40030060)) +#define TIMER0_TAPV_R (*((volatile uint32_t *)0x40030064)) +#define TIMER0_TBPV_R (*((volatile uint32_t *)0x40030068)) +#define TIMER0_PP_R (*((volatile uint32_t *)0x40030FC0)) + +//***************************************************************************** +// +// Timer registers (TIMER1) +// +//***************************************************************************** +#define TIMER1_CFG_R (*((volatile uint32_t *)0x40031000)) +#define TIMER1_TAMR_R (*((volatile uint32_t *)0x40031004)) +#define TIMER1_TBMR_R (*((volatile uint32_t *)0x40031008)) +#define TIMER1_CTL_R (*((volatile uint32_t *)0x4003100C)) +#define TIMER1_SYNC_R (*((volatile uint32_t *)0x40031010)) +#define TIMER1_IMR_R (*((volatile uint32_t *)0x40031018)) +#define TIMER1_RIS_R (*((volatile uint32_t *)0x4003101C)) +#define TIMER1_MIS_R (*((volatile uint32_t *)0x40031020)) +#define TIMER1_ICR_R (*((volatile uint32_t *)0x40031024)) +#define TIMER1_TAILR_R (*((volatile uint32_t *)0x40031028)) +#define TIMER1_TBILR_R (*((volatile uint32_t *)0x4003102C)) +#define TIMER1_TAMATCHR_R (*((volatile uint32_t *)0x40031030)) +#define TIMER1_TBMATCHR_R (*((volatile uint32_t *)0x40031034)) +#define TIMER1_TAPR_R (*((volatile uint32_t *)0x40031038)) +#define TIMER1_TBPR_R (*((volatile uint32_t *)0x4003103C)) +#define TIMER1_TAPMR_R (*((volatile uint32_t *)0x40031040)) +#define TIMER1_TBPMR_R (*((volatile uint32_t *)0x40031044)) +#define TIMER1_TAR_R (*((volatile uint32_t *)0x40031048)) +#define TIMER1_TBR_R (*((volatile uint32_t *)0x4003104C)) +#define TIMER1_TAV_R (*((volatile uint32_t *)0x40031050)) +#define TIMER1_TBV_R (*((volatile uint32_t *)0x40031054)) +#define TIMER1_RTCPD_R (*((volatile uint32_t *)0x40031058)) +#define TIMER1_TAPS_R (*((volatile uint32_t *)0x4003105C)) +#define TIMER1_TBPS_R (*((volatile uint32_t *)0x40031060)) +#define TIMER1_TAPV_R (*((volatile uint32_t *)0x40031064)) +#define TIMER1_TBPV_R (*((volatile uint32_t *)0x40031068)) +#define TIMER1_PP_R (*((volatile uint32_t *)0x40031FC0)) + +//***************************************************************************** +// +// Timer registers (TIMER2) +// +//***************************************************************************** +#define TIMER2_CFG_R (*((volatile uint32_t *)0x40032000)) +#define TIMER2_TAMR_R (*((volatile uint32_t *)0x40032004)) +#define TIMER2_TBMR_R (*((volatile uint32_t *)0x40032008)) +#define TIMER2_CTL_R (*((volatile uint32_t *)0x4003200C)) +#define TIMER2_SYNC_R (*((volatile uint32_t *)0x40032010)) +#define TIMER2_IMR_R (*((volatile uint32_t *)0x40032018)) +#define TIMER2_RIS_R (*((volatile uint32_t *)0x4003201C)) +#define TIMER2_MIS_R (*((volatile uint32_t *)0x40032020)) +#define TIMER2_ICR_R (*((volatile uint32_t *)0x40032024)) +#define TIMER2_TAILR_R (*((volatile uint32_t *)0x40032028)) +#define TIMER2_TBILR_R (*((volatile uint32_t *)0x4003202C)) +#define TIMER2_TAMATCHR_R (*((volatile uint32_t *)0x40032030)) +#define TIMER2_TBMATCHR_R (*((volatile uint32_t *)0x40032034)) +#define TIMER2_TAPR_R (*((volatile uint32_t *)0x40032038)) +#define TIMER2_TBPR_R (*((volatile uint32_t *)0x4003203C)) +#define TIMER2_TAPMR_R (*((volatile uint32_t *)0x40032040)) +#define TIMER2_TBPMR_R (*((volatile uint32_t *)0x40032044)) +#define TIMER2_TAR_R (*((volatile uint32_t *)0x40032048)) +#define TIMER2_TBR_R (*((volatile uint32_t *)0x4003204C)) +#define TIMER2_TAV_R (*((volatile uint32_t *)0x40032050)) +#define TIMER2_TBV_R (*((volatile uint32_t *)0x40032054)) +#define TIMER2_RTCPD_R (*((volatile uint32_t *)0x40032058)) +#define TIMER2_TAPS_R (*((volatile uint32_t *)0x4003205C)) +#define TIMER2_TBPS_R (*((volatile uint32_t *)0x40032060)) +#define TIMER2_TAPV_R (*((volatile uint32_t *)0x40032064)) +#define TIMER2_TBPV_R (*((volatile uint32_t *)0x40032068)) +#define TIMER2_PP_R (*((volatile uint32_t *)0x40032FC0)) + +//***************************************************************************** +// +// Timer registers (TIMER3) +// +//***************************************************************************** +#define TIMER3_CFG_R (*((volatile uint32_t *)0x40033000)) +#define TIMER3_TAMR_R (*((volatile uint32_t *)0x40033004)) +#define TIMER3_TBMR_R (*((volatile uint32_t *)0x40033008)) +#define TIMER3_CTL_R (*((volatile uint32_t *)0x4003300C)) +#define TIMER3_SYNC_R (*((volatile uint32_t *)0x40033010)) +#define TIMER3_IMR_R (*((volatile uint32_t *)0x40033018)) +#define TIMER3_RIS_R (*((volatile uint32_t *)0x4003301C)) +#define TIMER3_MIS_R (*((volatile uint32_t *)0x40033020)) +#define TIMER3_ICR_R (*((volatile uint32_t *)0x40033024)) +#define TIMER3_TAILR_R (*((volatile uint32_t *)0x40033028)) +#define TIMER3_TBILR_R (*((volatile uint32_t *)0x4003302C)) +#define TIMER3_TAMATCHR_R (*((volatile uint32_t *)0x40033030)) +#define TIMER3_TBMATCHR_R (*((volatile uint32_t *)0x40033034)) +#define TIMER3_TAPR_R (*((volatile uint32_t *)0x40033038)) +#define TIMER3_TBPR_R (*((volatile uint32_t *)0x4003303C)) +#define TIMER3_TAPMR_R (*((volatile uint32_t *)0x40033040)) +#define TIMER3_TBPMR_R (*((volatile uint32_t *)0x40033044)) +#define TIMER3_TAR_R (*((volatile uint32_t *)0x40033048)) +#define TIMER3_TBR_R (*((volatile uint32_t *)0x4003304C)) +#define TIMER3_TAV_R (*((volatile uint32_t *)0x40033050)) +#define TIMER3_TBV_R (*((volatile uint32_t *)0x40033054)) +#define TIMER3_RTCPD_R (*((volatile uint32_t *)0x40033058)) +#define TIMER3_TAPS_R (*((volatile uint32_t *)0x4003305C)) +#define TIMER3_TBPS_R (*((volatile uint32_t *)0x40033060)) +#define TIMER3_TAPV_R (*((volatile uint32_t *)0x40033064)) +#define TIMER3_TBPV_R (*((volatile uint32_t *)0x40033068)) +#define TIMER3_PP_R (*((volatile uint32_t *)0x40033FC0)) + +//***************************************************************************** +// +// Timer registers (TIMER4) +// +//***************************************************************************** +#define TIMER4_CFG_R (*((volatile uint32_t *)0x40034000)) +#define TIMER4_TAMR_R (*((volatile uint32_t *)0x40034004)) +#define TIMER4_TBMR_R (*((volatile uint32_t *)0x40034008)) +#define TIMER4_CTL_R (*((volatile uint32_t *)0x4003400C)) +#define TIMER4_SYNC_R (*((volatile uint32_t *)0x40034010)) +#define TIMER4_IMR_R (*((volatile uint32_t *)0x40034018)) +#define TIMER4_RIS_R (*((volatile uint32_t *)0x4003401C)) +#define TIMER4_MIS_R (*((volatile uint32_t *)0x40034020)) +#define TIMER4_ICR_R (*((volatile uint32_t *)0x40034024)) +#define TIMER4_TAILR_R (*((volatile uint32_t *)0x40034028)) +#define TIMER4_TBILR_R (*((volatile uint32_t *)0x4003402C)) +#define TIMER4_TAMATCHR_R (*((volatile uint32_t *)0x40034030)) +#define TIMER4_TBMATCHR_R (*((volatile uint32_t *)0x40034034)) +#define TIMER4_TAPR_R (*((volatile uint32_t *)0x40034038)) +#define TIMER4_TBPR_R (*((volatile uint32_t *)0x4003403C)) +#define TIMER4_TAPMR_R (*((volatile uint32_t *)0x40034040)) +#define TIMER4_TBPMR_R (*((volatile uint32_t *)0x40034044)) +#define TIMER4_TAR_R (*((volatile uint32_t *)0x40034048)) +#define TIMER4_TBR_R (*((volatile uint32_t *)0x4003404C)) +#define TIMER4_TAV_R (*((volatile uint32_t *)0x40034050)) +#define TIMER4_TBV_R (*((volatile uint32_t *)0x40034054)) +#define TIMER4_RTCPD_R (*((volatile uint32_t *)0x40034058)) +#define TIMER4_TAPS_R (*((volatile uint32_t *)0x4003405C)) +#define TIMER4_TBPS_R (*((volatile uint32_t *)0x40034060)) +#define TIMER4_TAPV_R (*((volatile uint32_t *)0x40034064)) +#define TIMER4_TBPV_R (*((volatile uint32_t *)0x40034068)) +#define TIMER4_PP_R (*((volatile uint32_t *)0x40034FC0)) + +//***************************************************************************** +// +// Timer registers (TIMER5) +// +//***************************************************************************** +#define TIMER5_CFG_R (*((volatile uint32_t *)0x40035000)) +#define TIMER5_TAMR_R (*((volatile uint32_t *)0x40035004)) +#define TIMER5_TBMR_R (*((volatile uint32_t *)0x40035008)) +#define TIMER5_CTL_R (*((volatile uint32_t *)0x4003500C)) +#define TIMER5_SYNC_R (*((volatile uint32_t *)0x40035010)) +#define TIMER5_IMR_R (*((volatile uint32_t *)0x40035018)) +#define TIMER5_RIS_R (*((volatile uint32_t *)0x4003501C)) +#define TIMER5_MIS_R (*((volatile uint32_t *)0x40035020)) +#define TIMER5_ICR_R (*((volatile uint32_t *)0x40035024)) +#define TIMER5_TAILR_R (*((volatile uint32_t *)0x40035028)) +#define TIMER5_TBILR_R (*((volatile uint32_t *)0x4003502C)) +#define TIMER5_TAMATCHR_R (*((volatile uint32_t *)0x40035030)) +#define TIMER5_TBMATCHR_R (*((volatile uint32_t *)0x40035034)) +#define TIMER5_TAPR_R (*((volatile uint32_t *)0x40035038)) +#define TIMER5_TBPR_R (*((volatile uint32_t *)0x4003503C)) +#define TIMER5_TAPMR_R (*((volatile uint32_t *)0x40035040)) +#define TIMER5_TBPMR_R (*((volatile uint32_t *)0x40035044)) +#define TIMER5_TAR_R (*((volatile uint32_t *)0x40035048)) +#define TIMER5_TBR_R (*((volatile uint32_t *)0x4003504C)) +#define TIMER5_TAV_R (*((volatile uint32_t *)0x40035050)) +#define TIMER5_TBV_R (*((volatile uint32_t *)0x40035054)) +#define TIMER5_RTCPD_R (*((volatile uint32_t *)0x40035058)) +#define TIMER5_TAPS_R (*((volatile uint32_t *)0x4003505C)) +#define TIMER5_TBPS_R (*((volatile uint32_t *)0x40035060)) +#define TIMER5_TAPV_R (*((volatile uint32_t *)0x40035064)) +#define TIMER5_TBPV_R (*((volatile uint32_t *)0x40035068)) +#define TIMER5_PP_R (*((volatile uint32_t *)0x40035FC0)) + +//***************************************************************************** +// +// Timer registers (WTIMER0) +// +//***************************************************************************** +#define WTIMER0_CFG_R (*((volatile uint32_t *)0x40036000)) +#define WTIMER0_TAMR_R (*((volatile uint32_t *)0x40036004)) +#define WTIMER0_TBMR_R (*((volatile uint32_t *)0x40036008)) +#define WTIMER0_CTL_R (*((volatile uint32_t *)0x4003600C)) +#define WTIMER0_SYNC_R (*((volatile uint32_t *)0x40036010)) +#define WTIMER0_IMR_R (*((volatile uint32_t *)0x40036018)) +#define WTIMER0_RIS_R (*((volatile uint32_t *)0x4003601C)) +#define WTIMER0_MIS_R (*((volatile uint32_t *)0x40036020)) +#define WTIMER0_ICR_R (*((volatile uint32_t *)0x40036024)) +#define WTIMER0_TAILR_R (*((volatile uint32_t *)0x40036028)) +#define WTIMER0_TBILR_R (*((volatile uint32_t *)0x4003602C)) +#define WTIMER0_TAMATCHR_R (*((volatile uint32_t *)0x40036030)) +#define WTIMER0_TBMATCHR_R (*((volatile uint32_t *)0x40036034)) +#define WTIMER0_TAPR_R (*((volatile uint32_t *)0x40036038)) +#define WTIMER0_TBPR_R (*((volatile uint32_t *)0x4003603C)) +#define WTIMER0_TAPMR_R (*((volatile uint32_t *)0x40036040)) +#define WTIMER0_TBPMR_R (*((volatile uint32_t *)0x40036044)) +#define WTIMER0_TAR_R (*((volatile uint32_t *)0x40036048)) +#define WTIMER0_TBR_R (*((volatile uint32_t *)0x4003604C)) +#define WTIMER0_TAV_R (*((volatile uint32_t *)0x40036050)) +#define WTIMER0_TBV_R (*((volatile uint32_t *)0x40036054)) +#define WTIMER0_RTCPD_R (*((volatile uint32_t *)0x40036058)) +#define WTIMER0_TAPS_R (*((volatile uint32_t *)0x4003605C)) +#define WTIMER0_TBPS_R (*((volatile uint32_t *)0x40036060)) +#define WTIMER0_TAPV_R (*((volatile uint32_t *)0x40036064)) +#define WTIMER0_TBPV_R (*((volatile uint32_t *)0x40036068)) +#define WTIMER0_PP_R (*((volatile uint32_t *)0x40036FC0)) + +//***************************************************************************** +// +// Timer registers (WTIMER1) +// +//***************************************************************************** +#define WTIMER1_CFG_R (*((volatile uint32_t *)0x40037000)) +#define WTIMER1_TAMR_R (*((volatile uint32_t *)0x40037004)) +#define WTIMER1_TBMR_R (*((volatile uint32_t *)0x40037008)) +#define WTIMER1_CTL_R (*((volatile uint32_t *)0x4003700C)) +#define WTIMER1_SYNC_R (*((volatile uint32_t *)0x40037010)) +#define WTIMER1_IMR_R (*((volatile uint32_t *)0x40037018)) +#define WTIMER1_RIS_R (*((volatile uint32_t *)0x4003701C)) +#define WTIMER1_MIS_R (*((volatile uint32_t *)0x40037020)) +#define WTIMER1_ICR_R (*((volatile uint32_t *)0x40037024)) +#define WTIMER1_TAILR_R (*((volatile uint32_t *)0x40037028)) +#define WTIMER1_TBILR_R (*((volatile uint32_t *)0x4003702C)) +#define WTIMER1_TAMATCHR_R (*((volatile uint32_t *)0x40037030)) +#define WTIMER1_TBMATCHR_R (*((volatile uint32_t *)0x40037034)) +#define WTIMER1_TAPR_R (*((volatile uint32_t *)0x40037038)) +#define WTIMER1_TBPR_R (*((volatile uint32_t *)0x4003703C)) +#define WTIMER1_TAPMR_R (*((volatile uint32_t *)0x40037040)) +#define WTIMER1_TBPMR_R (*((volatile uint32_t *)0x40037044)) +#define WTIMER1_TAR_R (*((volatile uint32_t *)0x40037048)) +#define WTIMER1_TBR_R (*((volatile uint32_t *)0x4003704C)) +#define WTIMER1_TAV_R (*((volatile uint32_t *)0x40037050)) +#define WTIMER1_TBV_R (*((volatile uint32_t *)0x40037054)) +#define WTIMER1_RTCPD_R (*((volatile uint32_t *)0x40037058)) +#define WTIMER1_TAPS_R (*((volatile uint32_t *)0x4003705C)) +#define WTIMER1_TBPS_R (*((volatile uint32_t *)0x40037060)) +#define WTIMER1_TAPV_R (*((volatile uint32_t *)0x40037064)) +#define WTIMER1_TBPV_R (*((volatile uint32_t *)0x40037068)) +#define WTIMER1_PP_R (*((volatile uint32_t *)0x40037FC0)) + +//***************************************************************************** +// +// ADC registers (ADC0) +// +//***************************************************************************** +#define ADC0_ACTSS_R (*((volatile uint32_t *)0x40038000)) +#define ADC0_RIS_R (*((volatile uint32_t *)0x40038004)) +#define ADC0_IM_R (*((volatile uint32_t *)0x40038008)) +#define ADC0_ISC_R (*((volatile uint32_t *)0x4003800C)) +#define ADC0_OSTAT_R (*((volatile uint32_t *)0x40038010)) +#define ADC0_EMUX_R (*((volatile uint32_t *)0x40038014)) +#define ADC0_USTAT_R (*((volatile uint32_t *)0x40038018)) +#define ADC0_TSSEL_R (*((volatile uint32_t *)0x4003801C)) +#define ADC0_SSPRI_R (*((volatile uint32_t *)0x40038020)) +#define ADC0_SPC_R (*((volatile uint32_t *)0x40038024)) +#define ADC0_PSSI_R (*((volatile uint32_t *)0x40038028)) +#define ADC0_SAC_R (*((volatile uint32_t *)0x40038030)) +#define ADC0_DCISC_R (*((volatile uint32_t *)0x40038034)) +#define ADC0_CTL_R (*((volatile uint32_t *)0x40038038)) +#define ADC0_SSMUX0_R (*((volatile uint32_t *)0x40038040)) +#define ADC0_SSCTL0_R (*((volatile uint32_t *)0x40038044)) +#define ADC0_SSFIFO0_R (*((volatile uint32_t *)0x40038048)) +#define ADC0_SSFSTAT0_R (*((volatile uint32_t *)0x4003804C)) +#define ADC0_SSOP0_R (*((volatile uint32_t *)0x40038050)) +#define ADC0_SSDC0_R (*((volatile uint32_t *)0x40038054)) +#define ADC0_SSEMUX0_R (*((volatile uint32_t *)0x40038058)) +#define ADC0_SSMUX1_R (*((volatile uint32_t *)0x40038060)) +#define ADC0_SSCTL1_R (*((volatile uint32_t *)0x40038064)) +#define ADC0_SSFIFO1_R (*((volatile uint32_t *)0x40038068)) +#define ADC0_SSFSTAT1_R (*((volatile uint32_t *)0x4003806C)) +#define ADC0_SSOP1_R (*((volatile uint32_t *)0x40038070)) +#define ADC0_SSDC1_R (*((volatile uint32_t *)0x40038074)) +#define ADC0_SSEMUX1_R (*((volatile uint32_t *)0x40038078)) +#define ADC0_SSMUX2_R (*((volatile uint32_t *)0x40038080)) +#define ADC0_SSCTL2_R (*((volatile uint32_t *)0x40038084)) +#define ADC0_SSFIFO2_R (*((volatile uint32_t *)0x40038088)) +#define ADC0_SSFSTAT2_R (*((volatile uint32_t *)0x4003808C)) +#define ADC0_SSOP2_R (*((volatile uint32_t *)0x40038090)) +#define ADC0_SSDC2_R (*((volatile uint32_t *)0x40038094)) +#define ADC0_SSEMUX2_R (*((volatile uint32_t *)0x40038098)) +#define ADC0_SSMUX3_R (*((volatile uint32_t *)0x400380A0)) +#define ADC0_SSCTL3_R (*((volatile uint32_t *)0x400380A4)) +#define ADC0_SSFIFO3_R (*((volatile uint32_t *)0x400380A8)) +#define ADC0_SSFSTAT3_R (*((volatile uint32_t *)0x400380AC)) +#define ADC0_SSOP3_R (*((volatile uint32_t *)0x400380B0)) +#define ADC0_SSDC3_R (*((volatile uint32_t *)0x400380B4)) +#define ADC0_SSEMUX3_R (*((volatile uint32_t *)0x400380B8)) +#define ADC0_DCRIC_R (*((volatile uint32_t *)0x40038D00)) +#define ADC0_DCCTL0_R (*((volatile uint32_t *)0x40038E00)) +#define ADC0_DCCTL1_R (*((volatile uint32_t *)0x40038E04)) +#define ADC0_DCCTL2_R (*((volatile uint32_t *)0x40038E08)) +#define ADC0_DCCTL3_R (*((volatile uint32_t *)0x40038E0C)) +#define ADC0_DCCTL4_R (*((volatile uint32_t *)0x40038E10)) +#define ADC0_DCCTL5_R (*((volatile uint32_t *)0x40038E14)) +#define ADC0_DCCTL6_R (*((volatile uint32_t *)0x40038E18)) +#define ADC0_DCCTL7_R (*((volatile uint32_t *)0x40038E1C)) +#define ADC0_DCCMP0_R (*((volatile uint32_t *)0x40038E40)) +#define ADC0_DCCMP1_R (*((volatile uint32_t *)0x40038E44)) +#define ADC0_DCCMP2_R (*((volatile uint32_t *)0x40038E48)) +#define ADC0_DCCMP3_R (*((volatile uint32_t *)0x40038E4C)) +#define ADC0_DCCMP4_R (*((volatile uint32_t *)0x40038E50)) +#define ADC0_DCCMP5_R (*((volatile uint32_t *)0x40038E54)) +#define ADC0_DCCMP6_R (*((volatile uint32_t *)0x40038E58)) +#define ADC0_DCCMP7_R (*((volatile uint32_t *)0x40038E5C)) +#define ADC0_PP_R (*((volatile uint32_t *)0x40038FC0)) +#define ADC0_PC_R (*((volatile uint32_t *)0x40038FC4)) +#define ADC0_CC_R (*((volatile uint32_t *)0x40038FC8)) + +//***************************************************************************** +// +// ADC registers (ADC1) +// +//***************************************************************************** +#define ADC1_ACTSS_R (*((volatile uint32_t *)0x40039000)) +#define ADC1_RIS_R (*((volatile uint32_t *)0x40039004)) +#define ADC1_IM_R (*((volatile uint32_t *)0x40039008)) +#define ADC1_ISC_R (*((volatile uint32_t *)0x4003900C)) +#define ADC1_OSTAT_R (*((volatile uint32_t *)0x40039010)) +#define ADC1_EMUX_R (*((volatile uint32_t *)0x40039014)) +#define ADC1_USTAT_R (*((volatile uint32_t *)0x40039018)) +#define ADC1_TSSEL_R (*((volatile uint32_t *)0x4003901C)) +#define ADC1_SSPRI_R (*((volatile uint32_t *)0x40039020)) +#define ADC1_SPC_R (*((volatile uint32_t *)0x40039024)) +#define ADC1_PSSI_R (*((volatile uint32_t *)0x40039028)) +#define ADC1_SAC_R (*((volatile uint32_t *)0x40039030)) +#define ADC1_DCISC_R (*((volatile uint32_t *)0x40039034)) +#define ADC1_CTL_R (*((volatile uint32_t *)0x40039038)) +#define ADC1_SSMUX0_R (*((volatile uint32_t *)0x40039040)) +#define ADC1_SSCTL0_R (*((volatile uint32_t *)0x40039044)) +#define ADC1_SSFIFO0_R (*((volatile uint32_t *)0x40039048)) +#define ADC1_SSFSTAT0_R (*((volatile uint32_t *)0x4003904C)) +#define ADC1_SSOP0_R (*((volatile uint32_t *)0x40039050)) +#define ADC1_SSDC0_R (*((volatile uint32_t *)0x40039054)) +#define ADC1_SSEMUX0_R (*((volatile uint32_t *)0x40039058)) +#define ADC1_SSMUX1_R (*((volatile uint32_t *)0x40039060)) +#define ADC1_SSCTL1_R (*((volatile uint32_t *)0x40039064)) +#define ADC1_SSFIFO1_R (*((volatile uint32_t *)0x40039068)) +#define ADC1_SSFSTAT1_R (*((volatile uint32_t *)0x4003906C)) +#define ADC1_SSOP1_R (*((volatile uint32_t *)0x40039070)) +#define ADC1_SSDC1_R (*((volatile uint32_t *)0x40039074)) +#define ADC1_SSEMUX1_R (*((volatile uint32_t *)0x40039078)) +#define ADC1_SSMUX2_R (*((volatile uint32_t *)0x40039080)) +#define ADC1_SSCTL2_R (*((volatile uint32_t *)0x40039084)) +#define ADC1_SSFIFO2_R (*((volatile uint32_t *)0x40039088)) +#define ADC1_SSFSTAT2_R (*((volatile uint32_t *)0x4003908C)) +#define ADC1_SSOP2_R (*((volatile uint32_t *)0x40039090)) +#define ADC1_SSDC2_R (*((volatile uint32_t *)0x40039094)) +#define ADC1_SSEMUX2_R (*((volatile uint32_t *)0x40039098)) +#define ADC1_SSMUX3_R (*((volatile uint32_t *)0x400390A0)) +#define ADC1_SSCTL3_R (*((volatile uint32_t *)0x400390A4)) +#define ADC1_SSFIFO3_R (*((volatile uint32_t *)0x400390A8)) +#define ADC1_SSFSTAT3_R (*((volatile uint32_t *)0x400390AC)) +#define ADC1_SSOP3_R (*((volatile uint32_t *)0x400390B0)) +#define ADC1_SSDC3_R (*((volatile uint32_t *)0x400390B4)) +#define ADC1_SSEMUX3_R (*((volatile uint32_t *)0x400390B8)) +#define ADC1_DCRIC_R (*((volatile uint32_t *)0x40039D00)) +#define ADC1_DCCTL0_R (*((volatile uint32_t *)0x40039E00)) +#define ADC1_DCCTL1_R (*((volatile uint32_t *)0x40039E04)) +#define ADC1_DCCTL2_R (*((volatile uint32_t *)0x40039E08)) +#define ADC1_DCCTL3_R (*((volatile uint32_t *)0x40039E0C)) +#define ADC1_DCCTL4_R (*((volatile uint32_t *)0x40039E10)) +#define ADC1_DCCTL5_R (*((volatile uint32_t *)0x40039E14)) +#define ADC1_DCCTL6_R (*((volatile uint32_t *)0x40039E18)) +#define ADC1_DCCTL7_R (*((volatile uint32_t *)0x40039E1C)) +#define ADC1_DCCMP0_R (*((volatile uint32_t *)0x40039E40)) +#define ADC1_DCCMP1_R (*((volatile uint32_t *)0x40039E44)) +#define ADC1_DCCMP2_R (*((volatile uint32_t *)0x40039E48)) +#define ADC1_DCCMP3_R (*((volatile uint32_t *)0x40039E4C)) +#define ADC1_DCCMP4_R (*((volatile uint32_t *)0x40039E50)) +#define ADC1_DCCMP5_R (*((volatile uint32_t *)0x40039E54)) +#define ADC1_DCCMP6_R (*((volatile uint32_t *)0x40039E58)) +#define ADC1_DCCMP7_R (*((volatile uint32_t *)0x40039E5C)) +#define ADC1_PP_R (*((volatile uint32_t *)0x40039FC0)) +#define ADC1_PC_R (*((volatile uint32_t *)0x40039FC4)) +#define ADC1_CC_R (*((volatile uint32_t *)0x40039FC8)) + +//***************************************************************************** +// +// Comparator registers (COMP) +// +//***************************************************************************** +#define COMP_ACMIS_R (*((volatile uint32_t *)0x4003C000)) +#define COMP_ACRIS_R (*((volatile uint32_t *)0x4003C004)) +#define COMP_ACINTEN_R (*((volatile uint32_t *)0x4003C008)) +#define COMP_ACREFCTL_R (*((volatile uint32_t *)0x4003C010)) +#define COMP_ACSTAT0_R (*((volatile uint32_t *)0x4003C020)) +#define COMP_ACCTL0_R (*((volatile uint32_t *)0x4003C024)) +#define COMP_ACSTAT1_R (*((volatile uint32_t *)0x4003C040)) +#define COMP_ACCTL1_R (*((volatile uint32_t *)0x4003C044)) +#define COMP_ACSTAT2_R (*((volatile uint32_t *)0x4003C060)) +#define COMP_ACCTL2_R (*((volatile uint32_t *)0x4003C064)) +#define COMP_PP_R (*((volatile uint32_t *)0x4003CFC0)) + +//***************************************************************************** +// +// GPIO registers (PORTJ) +// +//***************************************************************************** +#define GPIO_PORTJ_DATA_BITS_R ((volatile uint32_t *)0x4003D000) +#define GPIO_PORTJ_DATA_R (*((volatile uint32_t *)0x4003D3FC)) +#define GPIO_PORTJ_DIR_R (*((volatile uint32_t *)0x4003D400)) +#define GPIO_PORTJ_IS_R (*((volatile uint32_t *)0x4003D404)) +#define GPIO_PORTJ_IBE_R (*((volatile uint32_t *)0x4003D408)) +#define GPIO_PORTJ_IEV_R (*((volatile uint32_t *)0x4003D40C)) +#define GPIO_PORTJ_IM_R (*((volatile uint32_t *)0x4003D410)) +#define GPIO_PORTJ_RIS_R (*((volatile uint32_t *)0x4003D414)) +#define GPIO_PORTJ_MIS_R (*((volatile uint32_t *)0x4003D418)) +#define GPIO_PORTJ_ICR_R (*((volatile uint32_t *)0x4003D41C)) +#define GPIO_PORTJ_AFSEL_R (*((volatile uint32_t *)0x4003D420)) +#define GPIO_PORTJ_DR2R_R (*((volatile uint32_t *)0x4003D500)) +#define GPIO_PORTJ_DR4R_R (*((volatile uint32_t *)0x4003D504)) +#define GPIO_PORTJ_DR8R_R (*((volatile uint32_t *)0x4003D508)) +#define GPIO_PORTJ_ODR_R (*((volatile uint32_t *)0x4003D50C)) +#define GPIO_PORTJ_PUR_R (*((volatile uint32_t *)0x4003D510)) +#define GPIO_PORTJ_PDR_R (*((volatile uint32_t *)0x4003D514)) +#define GPIO_PORTJ_SLR_R (*((volatile uint32_t *)0x4003D518)) +#define GPIO_PORTJ_DEN_R (*((volatile uint32_t *)0x4003D51C)) +#define GPIO_PORTJ_LOCK_R (*((volatile uint32_t *)0x4003D520)) +#define GPIO_PORTJ_CR_R (*((volatile uint32_t *)0x4003D524)) +#define GPIO_PORTJ_AMSEL_R (*((volatile uint32_t *)0x4003D528)) +#define GPIO_PORTJ_PCTL_R (*((volatile uint32_t *)0x4003D52C)) +#define GPIO_PORTJ_ADCCTL_R (*((volatile uint32_t *)0x4003D530)) +#define GPIO_PORTJ_DMACTL_R (*((volatile uint32_t *)0x4003D534)) + +//***************************************************************************** +// +// CAN registers (CAN0) +// +//***************************************************************************** +#define CAN0_CTL_R (*((volatile uint32_t *)0x40040000)) +#define CAN0_STS_R (*((volatile uint32_t *)0x40040004)) +#define CAN0_ERR_R (*((volatile uint32_t *)0x40040008)) +#define CAN0_BIT_R (*((volatile uint32_t *)0x4004000C)) +#define CAN0_INT_R (*((volatile uint32_t *)0x40040010)) +#define CAN0_TST_R (*((volatile uint32_t *)0x40040014)) +#define CAN0_BRPE_R (*((volatile uint32_t *)0x40040018)) +#define CAN0_IF1CRQ_R (*((volatile uint32_t *)0x40040020)) +#define CAN0_IF1CMSK_R (*((volatile uint32_t *)0x40040024)) +#define CAN0_IF1MSK1_R (*((volatile uint32_t *)0x40040028)) +#define CAN0_IF1MSK2_R (*((volatile uint32_t *)0x4004002C)) +#define CAN0_IF1ARB1_R (*((volatile uint32_t *)0x40040030)) +#define CAN0_IF1ARB2_R (*((volatile uint32_t *)0x40040034)) +#define CAN0_IF1MCTL_R (*((volatile uint32_t *)0x40040038)) +#define CAN0_IF1DA1_R (*((volatile uint32_t *)0x4004003C)) +#define CAN0_IF1DA2_R (*((volatile uint32_t *)0x40040040)) +#define CAN0_IF1DB1_R (*((volatile uint32_t *)0x40040044)) +#define CAN0_IF1DB2_R (*((volatile uint32_t *)0x40040048)) +#define CAN0_IF2CRQ_R (*((volatile uint32_t *)0x40040080)) +#define CAN0_IF2CMSK_R (*((volatile uint32_t *)0x40040084)) +#define CAN0_IF2MSK1_R (*((volatile uint32_t *)0x40040088)) +#define CAN0_IF2MSK2_R (*((volatile uint32_t *)0x4004008C)) +#define CAN0_IF2ARB1_R (*((volatile uint32_t *)0x40040090)) +#define CAN0_IF2ARB2_R (*((volatile uint32_t *)0x40040094)) +#define CAN0_IF2MCTL_R (*((volatile uint32_t *)0x40040098)) +#define CAN0_IF2DA1_R (*((volatile uint32_t *)0x4004009C)) +#define CAN0_IF2DA2_R (*((volatile uint32_t *)0x400400A0)) +#define CAN0_IF2DB1_R (*((volatile uint32_t *)0x400400A4)) +#define CAN0_IF2DB2_R (*((volatile uint32_t *)0x400400A8)) +#define CAN0_TXRQ1_R (*((volatile uint32_t *)0x40040100)) +#define CAN0_TXRQ2_R (*((volatile uint32_t *)0x40040104)) +#define CAN0_NWDA1_R (*((volatile uint32_t *)0x40040120)) +#define CAN0_NWDA2_R (*((volatile uint32_t *)0x40040124)) +#define CAN0_MSG1INT_R (*((volatile uint32_t *)0x40040140)) +#define CAN0_MSG2INT_R (*((volatile uint32_t *)0x40040144)) +#define CAN0_MSG1VAL_R (*((volatile uint32_t *)0x40040160)) +#define CAN0_MSG2VAL_R (*((volatile uint32_t *)0x40040164)) + +//***************************************************************************** +// +// CAN registers (CAN1) +// +//***************************************************************************** +#define CAN1_CTL_R (*((volatile uint32_t *)0x40041000)) +#define CAN1_STS_R (*((volatile uint32_t *)0x40041004)) +#define CAN1_ERR_R (*((volatile uint32_t *)0x40041008)) +#define CAN1_BIT_R (*((volatile uint32_t *)0x4004100C)) +#define CAN1_INT_R (*((volatile uint32_t *)0x40041010)) +#define CAN1_TST_R (*((volatile uint32_t *)0x40041014)) +#define CAN1_BRPE_R (*((volatile uint32_t *)0x40041018)) +#define CAN1_IF1CRQ_R (*((volatile uint32_t *)0x40041020)) +#define CAN1_IF1CMSK_R (*((volatile uint32_t *)0x40041024)) +#define CAN1_IF1MSK1_R (*((volatile uint32_t *)0x40041028)) +#define CAN1_IF1MSK2_R (*((volatile uint32_t *)0x4004102C)) +#define CAN1_IF1ARB1_R (*((volatile uint32_t *)0x40041030)) +#define CAN1_IF1ARB2_R (*((volatile uint32_t *)0x40041034)) +#define CAN1_IF1MCTL_R (*((volatile uint32_t *)0x40041038)) +#define CAN1_IF1DA1_R (*((volatile uint32_t *)0x4004103C)) +#define CAN1_IF1DA2_R (*((volatile uint32_t *)0x40041040)) +#define CAN1_IF1DB1_R (*((volatile uint32_t *)0x40041044)) +#define CAN1_IF1DB2_R (*((volatile uint32_t *)0x40041048)) +#define CAN1_IF2CRQ_R (*((volatile uint32_t *)0x40041080)) +#define CAN1_IF2CMSK_R (*((volatile uint32_t *)0x40041084)) +#define CAN1_IF2MSK1_R (*((volatile uint32_t *)0x40041088)) +#define CAN1_IF2MSK2_R (*((volatile uint32_t *)0x4004108C)) +#define CAN1_IF2ARB1_R (*((volatile uint32_t *)0x40041090)) +#define CAN1_IF2ARB2_R (*((volatile uint32_t *)0x40041094)) +#define CAN1_IF2MCTL_R (*((volatile uint32_t *)0x40041098)) +#define CAN1_IF2DA1_R (*((volatile uint32_t *)0x4004109C)) +#define CAN1_IF2DA2_R (*((volatile uint32_t *)0x400410A0)) +#define CAN1_IF2DB1_R (*((volatile uint32_t *)0x400410A4)) +#define CAN1_IF2DB2_R (*((volatile uint32_t *)0x400410A8)) +#define CAN1_TXRQ1_R (*((volatile uint32_t *)0x40041100)) +#define CAN1_TXRQ2_R (*((volatile uint32_t *)0x40041104)) +#define CAN1_NWDA1_R (*((volatile uint32_t *)0x40041120)) +#define CAN1_NWDA2_R (*((volatile uint32_t *)0x40041124)) +#define CAN1_MSG1INT_R (*((volatile uint32_t *)0x40041140)) +#define CAN1_MSG2INT_R (*((volatile uint32_t *)0x40041144)) +#define CAN1_MSG1VAL_R (*((volatile uint32_t *)0x40041160)) +#define CAN1_MSG2VAL_R (*((volatile uint32_t *)0x40041164)) + +//***************************************************************************** +// +// Timer registers (WTIMER2) +// +//***************************************************************************** +#define WTIMER2_CFG_R (*((volatile uint32_t *)0x4004C000)) +#define WTIMER2_TAMR_R (*((volatile uint32_t *)0x4004C004)) +#define WTIMER2_TBMR_R (*((volatile uint32_t *)0x4004C008)) +#define WTIMER2_CTL_R (*((volatile uint32_t *)0x4004C00C)) +#define WTIMER2_SYNC_R (*((volatile uint32_t *)0x4004C010)) +#define WTIMER2_IMR_R (*((volatile uint32_t *)0x4004C018)) +#define WTIMER2_RIS_R (*((volatile uint32_t *)0x4004C01C)) +#define WTIMER2_MIS_R (*((volatile uint32_t *)0x4004C020)) +#define WTIMER2_ICR_R (*((volatile uint32_t *)0x4004C024)) +#define WTIMER2_TAILR_R (*((volatile uint32_t *)0x4004C028)) +#define WTIMER2_TBILR_R (*((volatile uint32_t *)0x4004C02C)) +#define WTIMER2_TAMATCHR_R (*((volatile uint32_t *)0x4004C030)) +#define WTIMER2_TBMATCHR_R (*((volatile uint32_t *)0x4004C034)) +#define WTIMER2_TAPR_R (*((volatile uint32_t *)0x4004C038)) +#define WTIMER2_TBPR_R (*((volatile uint32_t *)0x4004C03C)) +#define WTIMER2_TAPMR_R (*((volatile uint32_t *)0x4004C040)) +#define WTIMER2_TBPMR_R (*((volatile uint32_t *)0x4004C044)) +#define WTIMER2_TAR_R (*((volatile uint32_t *)0x4004C048)) +#define WTIMER2_TBR_R (*((volatile uint32_t *)0x4004C04C)) +#define WTIMER2_TAV_R (*((volatile uint32_t *)0x4004C050)) +#define WTIMER2_TBV_R (*((volatile uint32_t *)0x4004C054)) +#define WTIMER2_RTCPD_R (*((volatile uint32_t *)0x4004C058)) +#define WTIMER2_TAPS_R (*((volatile uint32_t *)0x4004C05C)) +#define WTIMER2_TBPS_R (*((volatile uint32_t *)0x4004C060)) +#define WTIMER2_TAPV_R (*((volatile uint32_t *)0x4004C064)) +#define WTIMER2_TBPV_R (*((volatile uint32_t *)0x4004C068)) +#define WTIMER2_PP_R (*((volatile uint32_t *)0x4004CFC0)) + +//***************************************************************************** +// +// Timer registers (WTIMER3) +// +//***************************************************************************** +#define WTIMER3_CFG_R (*((volatile uint32_t *)0x4004D000)) +#define WTIMER3_TAMR_R (*((volatile uint32_t *)0x4004D004)) +#define WTIMER3_TBMR_R (*((volatile uint32_t *)0x4004D008)) +#define WTIMER3_CTL_R (*((volatile uint32_t *)0x4004D00C)) +#define WTIMER3_SYNC_R (*((volatile uint32_t *)0x4004D010)) +#define WTIMER3_IMR_R (*((volatile uint32_t *)0x4004D018)) +#define WTIMER3_RIS_R (*((volatile uint32_t *)0x4004D01C)) +#define WTIMER3_MIS_R (*((volatile uint32_t *)0x4004D020)) +#define WTIMER3_ICR_R (*((volatile uint32_t *)0x4004D024)) +#define WTIMER3_TAILR_R (*((volatile uint32_t *)0x4004D028)) +#define WTIMER3_TBILR_R (*((volatile uint32_t *)0x4004D02C)) +#define WTIMER3_TAMATCHR_R (*((volatile uint32_t *)0x4004D030)) +#define WTIMER3_TBMATCHR_R (*((volatile uint32_t *)0x4004D034)) +#define WTIMER3_TAPR_R (*((volatile uint32_t *)0x4004D038)) +#define WTIMER3_TBPR_R (*((volatile uint32_t *)0x4004D03C)) +#define WTIMER3_TAPMR_R (*((volatile uint32_t *)0x4004D040)) +#define WTIMER3_TBPMR_R (*((volatile uint32_t *)0x4004D044)) +#define WTIMER3_TAR_R (*((volatile uint32_t *)0x4004D048)) +#define WTIMER3_TBR_R (*((volatile uint32_t *)0x4004D04C)) +#define WTIMER3_TAV_R (*((volatile uint32_t *)0x4004D050)) +#define WTIMER3_TBV_R (*((volatile uint32_t *)0x4004D054)) +#define WTIMER3_RTCPD_R (*((volatile uint32_t *)0x4004D058)) +#define WTIMER3_TAPS_R (*((volatile uint32_t *)0x4004D05C)) +#define WTIMER3_TBPS_R (*((volatile uint32_t *)0x4004D060)) +#define WTIMER3_TAPV_R (*((volatile uint32_t *)0x4004D064)) +#define WTIMER3_TBPV_R (*((volatile uint32_t *)0x4004D068)) +#define WTIMER3_PP_R (*((volatile uint32_t *)0x4004DFC0)) + +//***************************************************************************** +// +// Timer registers (WTIMER4) +// +//***************************************************************************** +#define WTIMER4_CFG_R (*((volatile uint32_t *)0x4004E000)) +#define WTIMER4_TAMR_R (*((volatile uint32_t *)0x4004E004)) +#define WTIMER4_TBMR_R (*((volatile uint32_t *)0x4004E008)) +#define WTIMER4_CTL_R (*((volatile uint32_t *)0x4004E00C)) +#define WTIMER4_SYNC_R (*((volatile uint32_t *)0x4004E010)) +#define WTIMER4_IMR_R (*((volatile uint32_t *)0x4004E018)) +#define WTIMER4_RIS_R (*((volatile uint32_t *)0x4004E01C)) +#define WTIMER4_MIS_R (*((volatile uint32_t *)0x4004E020)) +#define WTIMER4_ICR_R (*((volatile uint32_t *)0x4004E024)) +#define WTIMER4_TAILR_R (*((volatile uint32_t *)0x4004E028)) +#define WTIMER4_TBILR_R (*((volatile uint32_t *)0x4004E02C)) +#define WTIMER4_TAMATCHR_R (*((volatile uint32_t *)0x4004E030)) +#define WTIMER4_TBMATCHR_R (*((volatile uint32_t *)0x4004E034)) +#define WTIMER4_TAPR_R (*((volatile uint32_t *)0x4004E038)) +#define WTIMER4_TBPR_R (*((volatile uint32_t *)0x4004E03C)) +#define WTIMER4_TAPMR_R (*((volatile uint32_t *)0x4004E040)) +#define WTIMER4_TBPMR_R (*((volatile uint32_t *)0x4004E044)) +#define WTIMER4_TAR_R (*((volatile uint32_t *)0x4004E048)) +#define WTIMER4_TBR_R (*((volatile uint32_t *)0x4004E04C)) +#define WTIMER4_TAV_R (*((volatile uint32_t *)0x4004E050)) +#define WTIMER4_TBV_R (*((volatile uint32_t *)0x4004E054)) +#define WTIMER4_RTCPD_R (*((volatile uint32_t *)0x4004E058)) +#define WTIMER4_TAPS_R (*((volatile uint32_t *)0x4004E05C)) +#define WTIMER4_TBPS_R (*((volatile uint32_t *)0x4004E060)) +#define WTIMER4_TAPV_R (*((volatile uint32_t *)0x4004E064)) +#define WTIMER4_TBPV_R (*((volatile uint32_t *)0x4004E068)) +#define WTIMER4_PP_R (*((volatile uint32_t *)0x4004EFC0)) + +//***************************************************************************** +// +// Timer registers (WTIMER5) +// +//***************************************************************************** +#define WTIMER5_CFG_R (*((volatile uint32_t *)0x4004F000)) +#define WTIMER5_TAMR_R (*((volatile uint32_t *)0x4004F004)) +#define WTIMER5_TBMR_R (*((volatile uint32_t *)0x4004F008)) +#define WTIMER5_CTL_R (*((volatile uint32_t *)0x4004F00C)) +#define WTIMER5_SYNC_R (*((volatile uint32_t *)0x4004F010)) +#define WTIMER5_IMR_R (*((volatile uint32_t *)0x4004F018)) +#define WTIMER5_RIS_R (*((volatile uint32_t *)0x4004F01C)) +#define WTIMER5_MIS_R (*((volatile uint32_t *)0x4004F020)) +#define WTIMER5_ICR_R (*((volatile uint32_t *)0x4004F024)) +#define WTIMER5_TAILR_R (*((volatile uint32_t *)0x4004F028)) +#define WTIMER5_TBILR_R (*((volatile uint32_t *)0x4004F02C)) +#define WTIMER5_TAMATCHR_R (*((volatile uint32_t *)0x4004F030)) +#define WTIMER5_TBMATCHR_R (*((volatile uint32_t *)0x4004F034)) +#define WTIMER5_TAPR_R (*((volatile uint32_t *)0x4004F038)) +#define WTIMER5_TBPR_R (*((volatile uint32_t *)0x4004F03C)) +#define WTIMER5_TAPMR_R (*((volatile uint32_t *)0x4004F040)) +#define WTIMER5_TBPMR_R (*((volatile uint32_t *)0x4004F044)) +#define WTIMER5_TAR_R (*((volatile uint32_t *)0x4004F048)) +#define WTIMER5_TBR_R (*((volatile uint32_t *)0x4004F04C)) +#define WTIMER5_TAV_R (*((volatile uint32_t *)0x4004F050)) +#define WTIMER5_TBV_R (*((volatile uint32_t *)0x4004F054)) +#define WTIMER5_RTCPD_R (*((volatile uint32_t *)0x4004F058)) +#define WTIMER5_TAPS_R (*((volatile uint32_t *)0x4004F05C)) +#define WTIMER5_TBPS_R (*((volatile uint32_t *)0x4004F060)) +#define WTIMER5_TAPV_R (*((volatile uint32_t *)0x4004F064)) +#define WTIMER5_TBPV_R (*((volatile uint32_t *)0x4004F068)) +#define WTIMER5_PP_R (*((volatile uint32_t *)0x4004FFC0)) + +//***************************************************************************** +// +// Univeral Serial Bus registers (USB0) +// +//***************************************************************************** +#define USB0_FADDR_R (*((volatile uint8_t *)0x40050000)) +#define USB0_POWER_R (*((volatile uint8_t *)0x40050001)) +#define USB0_TXIS_R (*((volatile uint16_t *)0x40050002)) +#define USB0_RXIS_R (*((volatile uint16_t *)0x40050004)) +#define USB0_TXIE_R (*((volatile uint16_t *)0x40050006)) +#define USB0_RXIE_R (*((volatile uint16_t *)0x40050008)) +#define USB0_IS_R (*((volatile uint8_t *)0x4005000A)) +#define USB0_IE_R (*((volatile uint8_t *)0x4005000B)) +#define USB0_FRAME_R (*((volatile uint16_t *)0x4005000C)) +#define USB0_EPIDX_R (*((volatile uint8_t *)0x4005000E)) +#define USB0_TEST_R (*((volatile uint8_t *)0x4005000F)) +#define USB0_FIFO0_R (*((volatile uint32_t *)0x40050020)) +#define USB0_FIFO1_R (*((volatile uint32_t *)0x40050024)) +#define USB0_FIFO2_R (*((volatile uint32_t *)0x40050028)) +#define USB0_FIFO3_R (*((volatile uint32_t *)0x4005002C)) +#define USB0_FIFO4_R (*((volatile uint32_t *)0x40050030)) +#define USB0_FIFO5_R (*((volatile uint32_t *)0x40050034)) +#define USB0_FIFO6_R (*((volatile uint32_t *)0x40050038)) +#define USB0_FIFO7_R (*((volatile uint32_t *)0x4005003C)) +#define USB0_DEVCTL_R (*((volatile uint8_t *)0x40050060)) +#define USB0_TXFIFOSZ_R (*((volatile uint8_t *)0x40050062)) +#define USB0_RXFIFOSZ_R (*((volatile uint8_t *)0x40050063)) +#define USB0_TXFIFOADD_R (*((volatile uint16_t *)0x40050064)) +#define USB0_RXFIFOADD_R (*((volatile uint16_t *)0x40050066)) +#define USB0_CONTIM_R (*((volatile uint8_t *)0x4005007A)) +#define USB0_VPLEN_R (*((volatile uint8_t *)0x4005007B)) +#define USB0_FSEOF_R (*((volatile uint8_t *)0x4005007D)) +#define USB0_LSEOF_R (*((volatile uint8_t *)0x4005007E)) +#define USB0_TXFUNCADDR0_R (*((volatile uint8_t *)0x40050080)) +#define USB0_TXHUBADDR0_R (*((volatile uint8_t *)0x40050082)) +#define USB0_TXHUBPORT0_R (*((volatile uint8_t *)0x40050083)) +#define USB0_TXFUNCADDR1_R (*((volatile uint8_t *)0x40050088)) +#define USB0_TXHUBADDR1_R (*((volatile uint8_t *)0x4005008A)) +#define USB0_TXHUBPORT1_R (*((volatile uint8_t *)0x4005008B)) +#define USB0_RXFUNCADDR1_R (*((volatile uint8_t *)0x4005008C)) +#define USB0_RXHUBADDR1_R (*((volatile uint8_t *)0x4005008E)) +#define USB0_RXHUBPORT1_R (*((volatile uint8_t *)0x4005008F)) +#define USB0_TXFUNCADDR2_R (*((volatile uint8_t *)0x40050090)) +#define USB0_TXHUBADDR2_R (*((volatile uint8_t *)0x40050092)) +#define USB0_TXHUBPORT2_R (*((volatile uint8_t *)0x40050093)) +#define USB0_RXFUNCADDR2_R (*((volatile uint8_t *)0x40050094)) +#define USB0_RXHUBADDR2_R (*((volatile uint8_t *)0x40050096)) +#define USB0_RXHUBPORT2_R (*((volatile uint8_t *)0x40050097)) +#define USB0_TXFUNCADDR3_R (*((volatile uint8_t *)0x40050098)) +#define USB0_TXHUBADDR3_R (*((volatile uint8_t *)0x4005009A)) +#define USB0_TXHUBPORT3_R (*((volatile uint8_t *)0x4005009B)) +#define USB0_RXFUNCADDR3_R (*((volatile uint8_t *)0x4005009C)) +#define USB0_RXHUBADDR3_R (*((volatile uint8_t *)0x4005009E)) +#define USB0_RXHUBPORT3_R (*((volatile uint8_t *)0x4005009F)) +#define USB0_TXFUNCADDR4_R (*((volatile uint8_t *)0x400500A0)) +#define USB0_TXHUBADDR4_R (*((volatile uint8_t *)0x400500A2)) +#define USB0_TXHUBPORT4_R (*((volatile uint8_t *)0x400500A3)) +#define USB0_RXFUNCADDR4_R (*((volatile uint8_t *)0x400500A4)) +#define USB0_RXHUBADDR4_R (*((volatile uint8_t *)0x400500A6)) +#define USB0_RXHUBPORT4_R (*((volatile uint8_t *)0x400500A7)) +#define USB0_TXFUNCADDR5_R (*((volatile uint8_t *)0x400500A8)) +#define USB0_TXHUBADDR5_R (*((volatile uint8_t *)0x400500AA)) +#define USB0_TXHUBPORT5_R (*((volatile uint8_t *)0x400500AB)) +#define USB0_RXFUNCADDR5_R (*((volatile uint8_t *)0x400500AC)) +#define USB0_RXHUBADDR5_R (*((volatile uint8_t *)0x400500AE)) +#define USB0_RXHUBPORT5_R (*((volatile uint8_t *)0x400500AF)) +#define USB0_TXFUNCADDR6_R (*((volatile uint8_t *)0x400500B0)) +#define USB0_TXHUBADDR6_R (*((volatile uint8_t *)0x400500B2)) +#define USB0_TXHUBPORT6_R (*((volatile uint8_t *)0x400500B3)) +#define USB0_RXFUNCADDR6_R (*((volatile uint8_t *)0x400500B4)) +#define USB0_RXHUBADDR6_R (*((volatile uint8_t *)0x400500B6)) +#define USB0_RXHUBPORT6_R (*((volatile uint8_t *)0x400500B7)) +#define USB0_TXFUNCADDR7_R (*((volatile uint8_t *)0x400500B8)) +#define USB0_TXHUBADDR7_R (*((volatile uint8_t *)0x400500BA)) +#define USB0_TXHUBPORT7_R (*((volatile uint8_t *)0x400500BB)) +#define USB0_RXFUNCADDR7_R (*((volatile uint8_t *)0x400500BC)) +#define USB0_RXHUBADDR7_R (*((volatile uint8_t *)0x400500BE)) +#define USB0_RXHUBPORT7_R (*((volatile uint8_t *)0x400500BF)) +#define USB0_CSRL0_R (*((volatile uint8_t *)0x40050102)) +#define USB0_CSRH0_R (*((volatile uint8_t *)0x40050103)) +#define USB0_COUNT0_R (*((volatile uint8_t *)0x40050108)) +#define USB0_TYPE0_R (*((volatile uint8_t *)0x4005010A)) +#define USB0_NAKLMT_R (*((volatile uint8_t *)0x4005010B)) +#define USB0_TXMAXP1_R (*((volatile uint16_t *)0x40050110)) +#define USB0_TXCSRL1_R (*((volatile uint8_t *)0x40050112)) +#define USB0_TXCSRH1_R (*((volatile uint8_t *)0x40050113)) +#define USB0_RXMAXP1_R (*((volatile uint16_t *)0x40050114)) +#define USB0_RXCSRL1_R (*((volatile uint8_t *)0x40050116)) +#define USB0_RXCSRH1_R (*((volatile uint8_t *)0x40050117)) +#define USB0_RXCOUNT1_R (*((volatile uint16_t *)0x40050118)) +#define USB0_TXTYPE1_R (*((volatile uint8_t *)0x4005011A)) +#define USB0_TXINTERVAL1_R (*((volatile uint8_t *)0x4005011B)) +#define USB0_RXTYPE1_R (*((volatile uint8_t *)0x4005011C)) +#define USB0_RXINTERVAL1_R (*((volatile uint8_t *)0x4005011D)) +#define USB0_TXMAXP2_R (*((volatile uint16_t *)0x40050120)) +#define USB0_TXCSRL2_R (*((volatile uint8_t *)0x40050122)) +#define USB0_TXCSRH2_R (*((volatile uint8_t *)0x40050123)) +#define USB0_RXMAXP2_R (*((volatile uint16_t *)0x40050124)) +#define USB0_RXCSRL2_R (*((volatile uint8_t *)0x40050126)) +#define USB0_RXCSRH2_R (*((volatile uint8_t *)0x40050127)) +#define USB0_RXCOUNT2_R (*((volatile uint16_t *)0x40050128)) +#define USB0_TXTYPE2_R (*((volatile uint8_t *)0x4005012A)) +#define USB0_TXINTERVAL2_R (*((volatile uint8_t *)0x4005012B)) +#define USB0_RXTYPE2_R (*((volatile uint8_t *)0x4005012C)) +#define USB0_RXINTERVAL2_R (*((volatile uint8_t *)0x4005012D)) +#define USB0_TXMAXP3_R (*((volatile uint16_t *)0x40050130)) +#define USB0_TXCSRL3_R (*((volatile uint8_t *)0x40050132)) +#define USB0_TXCSRH3_R (*((volatile uint8_t *)0x40050133)) +#define USB0_RXMAXP3_R (*((volatile uint16_t *)0x40050134)) +#define USB0_RXCSRL3_R (*((volatile uint8_t *)0x40050136)) +#define USB0_RXCSRH3_R (*((volatile uint8_t *)0x40050137)) +#define USB0_RXCOUNT3_R (*((volatile uint16_t *)0x40050138)) +#define USB0_TXTYPE3_R (*((volatile uint8_t *)0x4005013A)) +#define USB0_TXINTERVAL3_R (*((volatile uint8_t *)0x4005013B)) +#define USB0_RXTYPE3_R (*((volatile uint8_t *)0x4005013C)) +#define USB0_RXINTERVAL3_R (*((volatile uint8_t *)0x4005013D)) +#define USB0_TXMAXP4_R (*((volatile uint16_t *)0x40050140)) +#define USB0_TXCSRL4_R (*((volatile uint8_t *)0x40050142)) +#define USB0_TXCSRH4_R (*((volatile uint8_t *)0x40050143)) +#define USB0_RXMAXP4_R (*((volatile uint16_t *)0x40050144)) +#define USB0_RXCSRL4_R (*((volatile uint8_t *)0x40050146)) +#define USB0_RXCSRH4_R (*((volatile uint8_t *)0x40050147)) +#define USB0_RXCOUNT4_R (*((volatile uint16_t *)0x40050148)) +#define USB0_TXTYPE4_R (*((volatile uint8_t *)0x4005014A)) +#define USB0_TXINTERVAL4_R (*((volatile uint8_t *)0x4005014B)) +#define USB0_RXTYPE4_R (*((volatile uint8_t *)0x4005014C)) +#define USB0_RXINTERVAL4_R (*((volatile uint8_t *)0x4005014D)) +#define USB0_TXMAXP5_R (*((volatile uint16_t *)0x40050150)) +#define USB0_TXCSRL5_R (*((volatile uint8_t *)0x40050152)) +#define USB0_TXCSRH5_R (*((volatile uint8_t *)0x40050153)) +#define USB0_RXMAXP5_R (*((volatile uint16_t *)0x40050154)) +#define USB0_RXCSRL5_R (*((volatile uint8_t *)0x40050156)) +#define USB0_RXCSRH5_R (*((volatile uint8_t *)0x40050157)) +#define USB0_RXCOUNT5_R (*((volatile uint16_t *)0x40050158)) +#define USB0_TXTYPE5_R (*((volatile uint8_t *)0x4005015A)) +#define USB0_TXINTERVAL5_R (*((volatile uint8_t *)0x4005015B)) +#define USB0_RXTYPE5_R (*((volatile uint8_t *)0x4005015C)) +#define USB0_RXINTERVAL5_R (*((volatile uint8_t *)0x4005015D)) +#define USB0_TXMAXP6_R (*((volatile uint16_t *)0x40050160)) +#define USB0_TXCSRL6_R (*((volatile uint8_t *)0x40050162)) +#define USB0_TXCSRH6_R (*((volatile uint8_t *)0x40050163)) +#define USB0_RXMAXP6_R (*((volatile uint16_t *)0x40050164)) +#define USB0_RXCSRL6_R (*((volatile uint8_t *)0x40050166)) +#define USB0_RXCSRH6_R (*((volatile uint8_t *)0x40050167)) +#define USB0_RXCOUNT6_R (*((volatile uint16_t *)0x40050168)) +#define USB0_TXTYPE6_R (*((volatile uint8_t *)0x4005016A)) +#define USB0_TXINTERVAL6_R (*((volatile uint8_t *)0x4005016B)) +#define USB0_RXTYPE6_R (*((volatile uint8_t *)0x4005016C)) +#define USB0_RXINTERVAL6_R (*((volatile uint8_t *)0x4005016D)) +#define USB0_TXMAXP7_R (*((volatile uint16_t *)0x40050170)) +#define USB0_TXCSRL7_R (*((volatile uint8_t *)0x40050172)) +#define USB0_TXCSRH7_R (*((volatile uint8_t *)0x40050173)) +#define USB0_RXMAXP7_R (*((volatile uint16_t *)0x40050174)) +#define USB0_RXCSRL7_R (*((volatile uint8_t *)0x40050176)) +#define USB0_RXCSRH7_R (*((volatile uint8_t *)0x40050177)) +#define USB0_RXCOUNT7_R (*((volatile uint16_t *)0x40050178)) +#define USB0_TXTYPE7_R (*((volatile uint8_t *)0x4005017A)) +#define USB0_TXINTERVAL7_R (*((volatile uint8_t *)0x4005017B)) +#define USB0_RXTYPE7_R (*((volatile uint8_t *)0x4005017C)) +#define USB0_RXINTERVAL7_R (*((volatile uint8_t *)0x4005017D)) +#define USB0_RQPKTCOUNT1_R (*((volatile uint16_t *)0x40050304)) +#define USB0_RQPKTCOUNT2_R (*((volatile uint16_t *)0x40050308)) +#define USB0_RQPKTCOUNT3_R (*((volatile uint16_t *)0x4005030C)) +#define USB0_RQPKTCOUNT4_R (*((volatile uint16_t *)0x40050310)) +#define USB0_RQPKTCOUNT5_R (*((volatile uint16_t *)0x40050314)) +#define USB0_RQPKTCOUNT6_R (*((volatile uint16_t *)0x40050318)) +#define USB0_RQPKTCOUNT7_R (*((volatile uint16_t *)0x4005031C)) +#define USB0_RXDPKTBUFDIS_R (*((volatile uint16_t *)0x40050340)) +#define USB0_TXDPKTBUFDIS_R (*((volatile uint16_t *)0x40050342)) +#define USB0_EPC_R (*((volatile uint32_t *)0x40050400)) +#define USB0_EPCRIS_R (*((volatile uint32_t *)0x40050404)) +#define USB0_EPCIM_R (*((volatile uint32_t *)0x40050408)) +#define USB0_EPCISC_R (*((volatile uint32_t *)0x4005040C)) +#define USB0_DRRIS_R (*((volatile uint32_t *)0x40050410)) +#define USB0_DRIM_R (*((volatile uint32_t *)0x40050414)) +#define USB0_DRISC_R (*((volatile uint32_t *)0x40050418)) +#define USB0_GPCS_R (*((volatile uint32_t *)0x4005041C)) +#define USB0_VDC_R (*((volatile uint32_t *)0x40050430)) +#define USB0_VDCRIS_R (*((volatile uint32_t *)0x40050434)) +#define USB0_VDCIM_R (*((volatile uint32_t *)0x40050438)) +#define USB0_VDCISC_R (*((volatile uint32_t *)0x4005043C)) +#define USB0_IDVRIS_R (*((volatile uint32_t *)0x40050444)) +#define USB0_IDVIM_R (*((volatile uint32_t *)0x40050448)) +#define USB0_IDVISC_R (*((volatile uint32_t *)0x4005044C)) +#define USB0_DMASEL_R (*((volatile uint32_t *)0x40050450)) +#define USB0_PP_R (*((volatile uint32_t *)0x40050FC0)) + +//***************************************************************************** +// +// GPIO registers (PORTA AHB) +// +//***************************************************************************** +#define GPIO_PORTA_AHB_DATA_BITS_R \ + ((volatile uint32_t *)0x40058000) +#define GPIO_PORTA_AHB_DATA_R (*((volatile uint32_t *)0x400583FC)) +#define GPIO_PORTA_AHB_DIR_R (*((volatile uint32_t *)0x40058400)) +#define GPIO_PORTA_AHB_IS_R (*((volatile uint32_t *)0x40058404)) +#define GPIO_PORTA_AHB_IBE_R (*((volatile uint32_t *)0x40058408)) +#define GPIO_PORTA_AHB_IEV_R (*((volatile uint32_t *)0x4005840C)) +#define GPIO_PORTA_AHB_IM_R (*((volatile uint32_t *)0x40058410)) +#define GPIO_PORTA_AHB_RIS_R (*((volatile uint32_t *)0x40058414)) +#define GPIO_PORTA_AHB_MIS_R (*((volatile uint32_t *)0x40058418)) +#define GPIO_PORTA_AHB_ICR_R (*((volatile uint32_t *)0x4005841C)) +#define GPIO_PORTA_AHB_AFSEL_R (*((volatile uint32_t *)0x40058420)) +#define GPIO_PORTA_AHB_DR2R_R (*((volatile uint32_t *)0x40058500)) +#define GPIO_PORTA_AHB_DR4R_R (*((volatile uint32_t *)0x40058504)) +#define GPIO_PORTA_AHB_DR8R_R (*((volatile uint32_t *)0x40058508)) +#define GPIO_PORTA_AHB_ODR_R (*((volatile uint32_t *)0x4005850C)) +#define GPIO_PORTA_AHB_PUR_R (*((volatile uint32_t *)0x40058510)) +#define GPIO_PORTA_AHB_PDR_R (*((volatile uint32_t *)0x40058514)) +#define GPIO_PORTA_AHB_SLR_R (*((volatile uint32_t *)0x40058518)) +#define GPIO_PORTA_AHB_DEN_R (*((volatile uint32_t *)0x4005851C)) +#define GPIO_PORTA_AHB_LOCK_R (*((volatile uint32_t *)0x40058520)) +#define GPIO_PORTA_AHB_CR_R (*((volatile uint32_t *)0x40058524)) +#define GPIO_PORTA_AHB_AMSEL_R (*((volatile uint32_t *)0x40058528)) +#define GPIO_PORTA_AHB_PCTL_R (*((volatile uint32_t *)0x4005852C)) +#define GPIO_PORTA_AHB_ADCCTL_R (*((volatile uint32_t *)0x40058530)) +#define GPIO_PORTA_AHB_DMACTL_R (*((volatile uint32_t *)0x40058534)) + +//***************************************************************************** +// +// GPIO registers (PORTB AHB) +// +//***************************************************************************** +#define GPIO_PORTB_AHB_DATA_BITS_R \ + ((volatile uint32_t *)0x40059000) +#define GPIO_PORTB_AHB_DATA_R (*((volatile uint32_t *)0x400593FC)) +#define GPIO_PORTB_AHB_DIR_R (*((volatile uint32_t *)0x40059400)) +#define GPIO_PORTB_AHB_IS_R (*((volatile uint32_t *)0x40059404)) +#define GPIO_PORTB_AHB_IBE_R (*((volatile uint32_t *)0x40059408)) +#define GPIO_PORTB_AHB_IEV_R (*((volatile uint32_t *)0x4005940C)) +#define GPIO_PORTB_AHB_IM_R (*((volatile uint32_t *)0x40059410)) +#define GPIO_PORTB_AHB_RIS_R (*((volatile uint32_t *)0x40059414)) +#define GPIO_PORTB_AHB_MIS_R (*((volatile uint32_t *)0x40059418)) +#define GPIO_PORTB_AHB_ICR_R (*((volatile uint32_t *)0x4005941C)) +#define GPIO_PORTB_AHB_AFSEL_R (*((volatile uint32_t *)0x40059420)) +#define GPIO_PORTB_AHB_DR2R_R (*((volatile uint32_t *)0x40059500)) +#define GPIO_PORTB_AHB_DR4R_R (*((volatile uint32_t *)0x40059504)) +#define GPIO_PORTB_AHB_DR8R_R (*((volatile uint32_t *)0x40059508)) +#define GPIO_PORTB_AHB_ODR_R (*((volatile uint32_t *)0x4005950C)) +#define GPIO_PORTB_AHB_PUR_R (*((volatile uint32_t *)0x40059510)) +#define GPIO_PORTB_AHB_PDR_R (*((volatile uint32_t *)0x40059514)) +#define GPIO_PORTB_AHB_SLR_R (*((volatile uint32_t *)0x40059518)) +#define GPIO_PORTB_AHB_DEN_R (*((volatile uint32_t *)0x4005951C)) +#define GPIO_PORTB_AHB_LOCK_R (*((volatile uint32_t *)0x40059520)) +#define GPIO_PORTB_AHB_CR_R (*((volatile uint32_t *)0x40059524)) +#define GPIO_PORTB_AHB_AMSEL_R (*((volatile uint32_t *)0x40059528)) +#define GPIO_PORTB_AHB_PCTL_R (*((volatile uint32_t *)0x4005952C)) +#define GPIO_PORTB_AHB_ADCCTL_R (*((volatile uint32_t *)0x40059530)) +#define GPIO_PORTB_AHB_DMACTL_R (*((volatile uint32_t *)0x40059534)) + +//***************************************************************************** +// +// GPIO registers (PORTC AHB) +// +//***************************************************************************** +#define GPIO_PORTC_AHB_DATA_BITS_R \ + ((volatile uint32_t *)0x4005A000) +#define GPIO_PORTC_AHB_DATA_R (*((volatile uint32_t *)0x4005A3FC)) +#define GPIO_PORTC_AHB_DIR_R (*((volatile uint32_t *)0x4005A400)) +#define GPIO_PORTC_AHB_IS_R (*((volatile uint32_t *)0x4005A404)) +#define GPIO_PORTC_AHB_IBE_R (*((volatile uint32_t *)0x4005A408)) +#define GPIO_PORTC_AHB_IEV_R (*((volatile uint32_t *)0x4005A40C)) +#define GPIO_PORTC_AHB_IM_R (*((volatile uint32_t *)0x4005A410)) +#define GPIO_PORTC_AHB_RIS_R (*((volatile uint32_t *)0x4005A414)) +#define GPIO_PORTC_AHB_MIS_R (*((volatile uint32_t *)0x4005A418)) +#define GPIO_PORTC_AHB_ICR_R (*((volatile uint32_t *)0x4005A41C)) +#define GPIO_PORTC_AHB_AFSEL_R (*((volatile uint32_t *)0x4005A420)) +#define GPIO_PORTC_AHB_DR2R_R (*((volatile uint32_t *)0x4005A500)) +#define GPIO_PORTC_AHB_DR4R_R (*((volatile uint32_t *)0x4005A504)) +#define GPIO_PORTC_AHB_DR8R_R (*((volatile uint32_t *)0x4005A508)) +#define GPIO_PORTC_AHB_ODR_R (*((volatile uint32_t *)0x4005A50C)) +#define GPIO_PORTC_AHB_PUR_R (*((volatile uint32_t *)0x4005A510)) +#define GPIO_PORTC_AHB_PDR_R (*((volatile uint32_t *)0x4005A514)) +#define GPIO_PORTC_AHB_SLR_R (*((volatile uint32_t *)0x4005A518)) +#define GPIO_PORTC_AHB_DEN_R (*((volatile uint32_t *)0x4005A51C)) +#define GPIO_PORTC_AHB_LOCK_R (*((volatile uint32_t *)0x4005A520)) +#define GPIO_PORTC_AHB_CR_R (*((volatile uint32_t *)0x4005A524)) +#define GPIO_PORTC_AHB_AMSEL_R (*((volatile uint32_t *)0x4005A528)) +#define GPIO_PORTC_AHB_PCTL_R (*((volatile uint32_t *)0x4005A52C)) +#define GPIO_PORTC_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005A530)) +#define GPIO_PORTC_AHB_DMACTL_R (*((volatile uint32_t *)0x4005A534)) + +//***************************************************************************** +// +// GPIO registers (PORTD AHB) +// +//***************************************************************************** +#define GPIO_PORTD_AHB_DATA_BITS_R \ + ((volatile uint32_t *)0x4005B000) +#define GPIO_PORTD_AHB_DATA_R (*((volatile uint32_t *)0x4005B3FC)) +#define GPIO_PORTD_AHB_DIR_R (*((volatile uint32_t *)0x4005B400)) +#define GPIO_PORTD_AHB_IS_R (*((volatile uint32_t *)0x4005B404)) +#define GPIO_PORTD_AHB_IBE_R (*((volatile uint32_t *)0x4005B408)) +#define GPIO_PORTD_AHB_IEV_R (*((volatile uint32_t *)0x4005B40C)) +#define GPIO_PORTD_AHB_IM_R (*((volatile uint32_t *)0x4005B410)) +#define GPIO_PORTD_AHB_RIS_R (*((volatile uint32_t *)0x4005B414)) +#define GPIO_PORTD_AHB_MIS_R (*((volatile uint32_t *)0x4005B418)) +#define GPIO_PORTD_AHB_ICR_R (*((volatile uint32_t *)0x4005B41C)) +#define GPIO_PORTD_AHB_AFSEL_R (*((volatile uint32_t *)0x4005B420)) +#define GPIO_PORTD_AHB_DR2R_R (*((volatile uint32_t *)0x4005B500)) +#define GPIO_PORTD_AHB_DR4R_R (*((volatile uint32_t *)0x4005B504)) +#define GPIO_PORTD_AHB_DR8R_R (*((volatile uint32_t *)0x4005B508)) +#define GPIO_PORTD_AHB_ODR_R (*((volatile uint32_t *)0x4005B50C)) +#define GPIO_PORTD_AHB_PUR_R (*((volatile uint32_t *)0x4005B510)) +#define GPIO_PORTD_AHB_PDR_R (*((volatile uint32_t *)0x4005B514)) +#define GPIO_PORTD_AHB_SLR_R (*((volatile uint32_t *)0x4005B518)) +#define GPIO_PORTD_AHB_DEN_R (*((volatile uint32_t *)0x4005B51C)) +#define GPIO_PORTD_AHB_LOCK_R (*((volatile uint32_t *)0x4005B520)) +#define GPIO_PORTD_AHB_CR_R (*((volatile uint32_t *)0x4005B524)) +#define GPIO_PORTD_AHB_AMSEL_R (*((volatile uint32_t *)0x4005B528)) +#define GPIO_PORTD_AHB_PCTL_R (*((volatile uint32_t *)0x4005B52C)) +#define GPIO_PORTD_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005B530)) +#define GPIO_PORTD_AHB_DMACTL_R (*((volatile uint32_t *)0x4005B534)) + +//***************************************************************************** +// +// GPIO registers (PORTE AHB) +// +//***************************************************************************** +#define GPIO_PORTE_AHB_DATA_BITS_R \ + ((volatile uint32_t *)0x4005C000) +#define GPIO_PORTE_AHB_DATA_R (*((volatile uint32_t *)0x4005C3FC)) +#define GPIO_PORTE_AHB_DIR_R (*((volatile uint32_t *)0x4005C400)) +#define GPIO_PORTE_AHB_IS_R (*((volatile uint32_t *)0x4005C404)) +#define GPIO_PORTE_AHB_IBE_R (*((volatile uint32_t *)0x4005C408)) +#define GPIO_PORTE_AHB_IEV_R (*((volatile uint32_t *)0x4005C40C)) +#define GPIO_PORTE_AHB_IM_R (*((volatile uint32_t *)0x4005C410)) +#define GPIO_PORTE_AHB_RIS_R (*((volatile uint32_t *)0x4005C414)) +#define GPIO_PORTE_AHB_MIS_R (*((volatile uint32_t *)0x4005C418)) +#define GPIO_PORTE_AHB_ICR_R (*((volatile uint32_t *)0x4005C41C)) +#define GPIO_PORTE_AHB_AFSEL_R (*((volatile uint32_t *)0x4005C420)) +#define GPIO_PORTE_AHB_DR2R_R (*((volatile uint32_t *)0x4005C500)) +#define GPIO_PORTE_AHB_DR4R_R (*((volatile uint32_t *)0x4005C504)) +#define GPIO_PORTE_AHB_DR8R_R (*((volatile uint32_t *)0x4005C508)) +#define GPIO_PORTE_AHB_ODR_R (*((volatile uint32_t *)0x4005C50C)) +#define GPIO_PORTE_AHB_PUR_R (*((volatile uint32_t *)0x4005C510)) +#define GPIO_PORTE_AHB_PDR_R (*((volatile uint32_t *)0x4005C514)) +#define GPIO_PORTE_AHB_SLR_R (*((volatile uint32_t *)0x4005C518)) +#define GPIO_PORTE_AHB_DEN_R (*((volatile uint32_t *)0x4005C51C)) +#define GPIO_PORTE_AHB_LOCK_R (*((volatile uint32_t *)0x4005C520)) +#define GPIO_PORTE_AHB_CR_R (*((volatile uint32_t *)0x4005C524)) +#define GPIO_PORTE_AHB_AMSEL_R (*((volatile uint32_t *)0x4005C528)) +#define GPIO_PORTE_AHB_PCTL_R (*((volatile uint32_t *)0x4005C52C)) +#define GPIO_PORTE_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005C530)) +#define GPIO_PORTE_AHB_DMACTL_R (*((volatile uint32_t *)0x4005C534)) + +//***************************************************************************** +// +// GPIO registers (PORTF AHB) +// +//***************************************************************************** +#define GPIO_PORTF_AHB_DATA_BITS_R \ + ((volatile uint32_t *)0x4005D000) +#define GPIO_PORTF_AHB_DATA_R (*((volatile uint32_t *)0x4005D3FC)) +#define GPIO_PORTF_AHB_DIR_R (*((volatile uint32_t *)0x4005D400)) +#define GPIO_PORTF_AHB_IS_R (*((volatile uint32_t *)0x4005D404)) +#define GPIO_PORTF_AHB_IBE_R (*((volatile uint32_t *)0x4005D408)) +#define GPIO_PORTF_AHB_IEV_R (*((volatile uint32_t *)0x4005D40C)) +#define GPIO_PORTF_AHB_IM_R (*((volatile uint32_t *)0x4005D410)) +#define GPIO_PORTF_AHB_RIS_R (*((volatile uint32_t *)0x4005D414)) +#define GPIO_PORTF_AHB_MIS_R (*((volatile uint32_t *)0x4005D418)) +#define GPIO_PORTF_AHB_ICR_R (*((volatile uint32_t *)0x4005D41C)) +#define GPIO_PORTF_AHB_AFSEL_R (*((volatile uint32_t *)0x4005D420)) +#define GPIO_PORTF_AHB_DR2R_R (*((volatile uint32_t *)0x4005D500)) +#define GPIO_PORTF_AHB_DR4R_R (*((volatile uint32_t *)0x4005D504)) +#define GPIO_PORTF_AHB_DR8R_R (*((volatile uint32_t *)0x4005D508)) +#define GPIO_PORTF_AHB_ODR_R (*((volatile uint32_t *)0x4005D50C)) +#define GPIO_PORTF_AHB_PUR_R (*((volatile uint32_t *)0x4005D510)) +#define GPIO_PORTF_AHB_PDR_R (*((volatile uint32_t *)0x4005D514)) +#define GPIO_PORTF_AHB_SLR_R (*((volatile uint32_t *)0x4005D518)) +#define GPIO_PORTF_AHB_DEN_R (*((volatile uint32_t *)0x4005D51C)) +#define GPIO_PORTF_AHB_LOCK_R (*((volatile uint32_t *)0x4005D520)) +#define GPIO_PORTF_AHB_CR_R (*((volatile uint32_t *)0x4005D524)) +#define GPIO_PORTF_AHB_AMSEL_R (*((volatile uint32_t *)0x4005D528)) +#define GPIO_PORTF_AHB_PCTL_R (*((volatile uint32_t *)0x4005D52C)) +#define GPIO_PORTF_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005D530)) +#define GPIO_PORTF_AHB_DMACTL_R (*((volatile uint32_t *)0x4005D534)) + +//***************************************************************************** +// +// GPIO registers (PORTG AHB) +// +//***************************************************************************** +#define GPIO_PORTG_AHB_DATA_BITS_R \ + ((volatile uint32_t *)0x4005E000) +#define GPIO_PORTG_AHB_DATA_R (*((volatile uint32_t *)0x4005E3FC)) +#define GPIO_PORTG_AHB_DIR_R (*((volatile uint32_t *)0x4005E400)) +#define GPIO_PORTG_AHB_IS_R (*((volatile uint32_t *)0x4005E404)) +#define GPIO_PORTG_AHB_IBE_R (*((volatile uint32_t *)0x4005E408)) +#define GPIO_PORTG_AHB_IEV_R (*((volatile uint32_t *)0x4005E40C)) +#define GPIO_PORTG_AHB_IM_R (*((volatile uint32_t *)0x4005E410)) +#define GPIO_PORTG_AHB_RIS_R (*((volatile uint32_t *)0x4005E414)) +#define GPIO_PORTG_AHB_MIS_R (*((volatile uint32_t *)0x4005E418)) +#define GPIO_PORTG_AHB_ICR_R (*((volatile uint32_t *)0x4005E41C)) +#define GPIO_PORTG_AHB_AFSEL_R (*((volatile uint32_t *)0x4005E420)) +#define GPIO_PORTG_AHB_DR2R_R (*((volatile uint32_t *)0x4005E500)) +#define GPIO_PORTG_AHB_DR4R_R (*((volatile uint32_t *)0x4005E504)) +#define GPIO_PORTG_AHB_DR8R_R (*((volatile uint32_t *)0x4005E508)) +#define GPIO_PORTG_AHB_ODR_R (*((volatile uint32_t *)0x4005E50C)) +#define GPIO_PORTG_AHB_PUR_R (*((volatile uint32_t *)0x4005E510)) +#define GPIO_PORTG_AHB_PDR_R (*((volatile uint32_t *)0x4005E514)) +#define GPIO_PORTG_AHB_SLR_R (*((volatile uint32_t *)0x4005E518)) +#define GPIO_PORTG_AHB_DEN_R (*((volatile uint32_t *)0x4005E51C)) +#define GPIO_PORTG_AHB_LOCK_R (*((volatile uint32_t *)0x4005E520)) +#define GPIO_PORTG_AHB_CR_R (*((volatile uint32_t *)0x4005E524)) +#define GPIO_PORTG_AHB_AMSEL_R (*((volatile uint32_t *)0x4005E528)) +#define GPIO_PORTG_AHB_PCTL_R (*((volatile uint32_t *)0x4005E52C)) +#define GPIO_PORTG_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005E530)) +#define GPIO_PORTG_AHB_DMACTL_R (*((volatile uint32_t *)0x4005E534)) + +//***************************************************************************** +// +// GPIO registers (PORTH AHB) +// +//***************************************************************************** +#define GPIO_PORTH_AHB_DATA_BITS_R \ + ((volatile uint32_t *)0x4005F000) +#define GPIO_PORTH_AHB_DATA_R (*((volatile uint32_t *)0x4005F3FC)) +#define GPIO_PORTH_AHB_DIR_R (*((volatile uint32_t *)0x4005F400)) +#define GPIO_PORTH_AHB_IS_R (*((volatile uint32_t *)0x4005F404)) +#define GPIO_PORTH_AHB_IBE_R (*((volatile uint32_t *)0x4005F408)) +#define GPIO_PORTH_AHB_IEV_R (*((volatile uint32_t *)0x4005F40C)) +#define GPIO_PORTH_AHB_IM_R (*((volatile uint32_t *)0x4005F410)) +#define GPIO_PORTH_AHB_RIS_R (*((volatile uint32_t *)0x4005F414)) +#define GPIO_PORTH_AHB_MIS_R (*((volatile uint32_t *)0x4005F418)) +#define GPIO_PORTH_AHB_ICR_R (*((volatile uint32_t *)0x4005F41C)) +#define GPIO_PORTH_AHB_AFSEL_R (*((volatile uint32_t *)0x4005F420)) +#define GPIO_PORTH_AHB_DR2R_R (*((volatile uint32_t *)0x4005F500)) +#define GPIO_PORTH_AHB_DR4R_R (*((volatile uint32_t *)0x4005F504)) +#define GPIO_PORTH_AHB_DR8R_R (*((volatile uint32_t *)0x4005F508)) +#define GPIO_PORTH_AHB_ODR_R (*((volatile uint32_t *)0x4005F50C)) +#define GPIO_PORTH_AHB_PUR_R (*((volatile uint32_t *)0x4005F510)) +#define GPIO_PORTH_AHB_PDR_R (*((volatile uint32_t *)0x4005F514)) +#define GPIO_PORTH_AHB_SLR_R (*((volatile uint32_t *)0x4005F518)) +#define GPIO_PORTH_AHB_DEN_R (*((volatile uint32_t *)0x4005F51C)) +#define GPIO_PORTH_AHB_LOCK_R (*((volatile uint32_t *)0x4005F520)) +#define GPIO_PORTH_AHB_CR_R (*((volatile uint32_t *)0x4005F524)) +#define GPIO_PORTH_AHB_AMSEL_R (*((volatile uint32_t *)0x4005F528)) +#define GPIO_PORTH_AHB_PCTL_R (*((volatile uint32_t *)0x4005F52C)) +#define GPIO_PORTH_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005F530)) +#define GPIO_PORTH_AHB_DMACTL_R (*((volatile uint32_t *)0x4005F534)) + +//***************************************************************************** +// +// GPIO registers (PORTJ AHB) +// +//***************************************************************************** +#define GPIO_PORTJ_AHB_DATA_BITS_R \ + ((volatile uint32_t *)0x40060000) +#define GPIO_PORTJ_AHB_DATA_R (*((volatile uint32_t *)0x400603FC)) +#define GPIO_PORTJ_AHB_DIR_R (*((volatile uint32_t *)0x40060400)) +#define GPIO_PORTJ_AHB_IS_R (*((volatile uint32_t *)0x40060404)) +#define GPIO_PORTJ_AHB_IBE_R (*((volatile uint32_t *)0x40060408)) +#define GPIO_PORTJ_AHB_IEV_R (*((volatile uint32_t *)0x4006040C)) +#define GPIO_PORTJ_AHB_IM_R (*((volatile uint32_t *)0x40060410)) +#define GPIO_PORTJ_AHB_RIS_R (*((volatile uint32_t *)0x40060414)) +#define GPIO_PORTJ_AHB_MIS_R (*((volatile uint32_t *)0x40060418)) +#define GPIO_PORTJ_AHB_ICR_R (*((volatile uint32_t *)0x4006041C)) +#define GPIO_PORTJ_AHB_AFSEL_R (*((volatile uint32_t *)0x40060420)) +#define GPIO_PORTJ_AHB_DR2R_R (*((volatile uint32_t *)0x40060500)) +#define GPIO_PORTJ_AHB_DR4R_R (*((volatile uint32_t *)0x40060504)) +#define GPIO_PORTJ_AHB_DR8R_R (*((volatile uint32_t *)0x40060508)) +#define GPIO_PORTJ_AHB_ODR_R (*((volatile uint32_t *)0x4006050C)) +#define GPIO_PORTJ_AHB_PUR_R (*((volatile uint32_t *)0x40060510)) +#define GPIO_PORTJ_AHB_PDR_R (*((volatile uint32_t *)0x40060514)) +#define GPIO_PORTJ_AHB_SLR_R (*((volatile uint32_t *)0x40060518)) +#define GPIO_PORTJ_AHB_DEN_R (*((volatile uint32_t *)0x4006051C)) +#define GPIO_PORTJ_AHB_LOCK_R (*((volatile uint32_t *)0x40060520)) +#define GPIO_PORTJ_AHB_CR_R (*((volatile uint32_t *)0x40060524)) +#define GPIO_PORTJ_AHB_AMSEL_R (*((volatile uint32_t *)0x40060528)) +#define GPIO_PORTJ_AHB_PCTL_R (*((volatile uint32_t *)0x4006052C)) +#define GPIO_PORTJ_AHB_ADCCTL_R (*((volatile uint32_t *)0x40060530)) +#define GPIO_PORTJ_AHB_DMACTL_R (*((volatile uint32_t *)0x40060534)) + +//***************************************************************************** +// +// GPIO registers (PORTK) +// +//***************************************************************************** +#define GPIO_PORTK_DATA_BITS_R ((volatile uint32_t *)0x40061000) +#define GPIO_PORTK_DATA_R (*((volatile uint32_t *)0x400613FC)) +#define GPIO_PORTK_DIR_R (*((volatile uint32_t *)0x40061400)) +#define GPIO_PORTK_IS_R (*((volatile uint32_t *)0x40061404)) +#define GPIO_PORTK_IBE_R (*((volatile uint32_t *)0x40061408)) +#define GPIO_PORTK_IEV_R (*((volatile uint32_t *)0x4006140C)) +#define GPIO_PORTK_IM_R (*((volatile uint32_t *)0x40061410)) +#define GPIO_PORTK_RIS_R (*((volatile uint32_t *)0x40061414)) +#define GPIO_PORTK_MIS_R (*((volatile uint32_t *)0x40061418)) +#define GPIO_PORTK_ICR_R (*((volatile uint32_t *)0x4006141C)) +#define GPIO_PORTK_AFSEL_R (*((volatile uint32_t *)0x40061420)) +#define GPIO_PORTK_DR2R_R (*((volatile uint32_t *)0x40061500)) +#define GPIO_PORTK_DR4R_R (*((volatile uint32_t *)0x40061504)) +#define GPIO_PORTK_DR8R_R (*((volatile uint32_t *)0x40061508)) +#define GPIO_PORTK_ODR_R (*((volatile uint32_t *)0x4006150C)) +#define GPIO_PORTK_PUR_R (*((volatile uint32_t *)0x40061510)) +#define GPIO_PORTK_PDR_R (*((volatile uint32_t *)0x40061514)) +#define GPIO_PORTK_SLR_R (*((volatile uint32_t *)0x40061518)) +#define GPIO_PORTK_DEN_R (*((volatile uint32_t *)0x4006151C)) +#define GPIO_PORTK_LOCK_R (*((volatile uint32_t *)0x40061520)) +#define GPIO_PORTK_CR_R (*((volatile uint32_t *)0x40061524)) +#define GPIO_PORTK_AMSEL_R (*((volatile uint32_t *)0x40061528)) +#define GPIO_PORTK_PCTL_R (*((volatile uint32_t *)0x4006152C)) +#define GPIO_PORTK_ADCCTL_R (*((volatile uint32_t *)0x40061530)) +#define GPIO_PORTK_DMACTL_R (*((volatile uint32_t *)0x40061534)) + +//***************************************************************************** +// +// EEPROM registers (EEPROM) +// +//***************************************************************************** +#define EEPROM_EESIZE_R (*((volatile uint32_t *)0x400AF000)) +#define EEPROM_EEBLOCK_R (*((volatile uint32_t *)0x400AF004)) +#define EEPROM_EEOFFSET_R (*((volatile uint32_t *)0x400AF008)) +#define EEPROM_EERDWR_R (*((volatile uint32_t *)0x400AF010)) +#define EEPROM_EERDWRINC_R (*((volatile uint32_t *)0x400AF014)) +#define EEPROM_EEDONE_R (*((volatile uint32_t *)0x400AF018)) +#define EEPROM_EESUPP_R (*((volatile uint32_t *)0x400AF01C)) +#define EEPROM_EEUNLOCK_R (*((volatile uint32_t *)0x400AF020)) +#define EEPROM_EEPROT_R (*((volatile uint32_t *)0x400AF030)) +#define EEPROM_EEPASS0_R (*((volatile uint32_t *)0x400AF034)) +#define EEPROM_EEPASS1_R (*((volatile uint32_t *)0x400AF038)) +#define EEPROM_EEPASS2_R (*((volatile uint32_t *)0x400AF03C)) +#define EEPROM_EEINT_R (*((volatile uint32_t *)0x400AF040)) +#define EEPROM_EEHIDE_R (*((volatile uint32_t *)0x400AF050)) +#define EEPROM_EEDBGME_R (*((volatile uint32_t *)0x400AF080)) +#define EEPROM_PP_R (*((volatile uint32_t *)0x400AFFC0)) + +//***************************************************************************** +// +// I2C registers (I2C4) +// +//***************************************************************************** +#define I2C4_MSA_R (*((volatile uint32_t *)0x400C0000)) +#define I2C4_MCS_R (*((volatile uint32_t *)0x400C0004)) +#define I2C4_MDR_R (*((volatile uint32_t *)0x400C0008)) +#define I2C4_MTPR_R (*((volatile uint32_t *)0x400C000C)) +#define I2C4_MIMR_R (*((volatile uint32_t *)0x400C0010)) +#define I2C4_MRIS_R (*((volatile uint32_t *)0x400C0014)) +#define I2C4_MMIS_R (*((volatile uint32_t *)0x400C0018)) +#define I2C4_MICR_R (*((volatile uint32_t *)0x400C001C)) +#define I2C4_MCR_R (*((volatile uint32_t *)0x400C0020)) +#define I2C4_MCLKOCNT_R (*((volatile uint32_t *)0x400C0024)) +#define I2C4_MBMON_R (*((volatile uint32_t *)0x400C002C)) +#define I2C4_MCR2_R (*((volatile uint32_t *)0x400C0038)) +#define I2C4_SOAR_R (*((volatile uint32_t *)0x400C0800)) +#define I2C4_SCSR_R (*((volatile uint32_t *)0x400C0804)) +#define I2C4_SDR_R (*((volatile uint32_t *)0x400C0808)) +#define I2C4_SIMR_R (*((volatile uint32_t *)0x400C080C)) +#define I2C4_SRIS_R (*((volatile uint32_t *)0x400C0810)) +#define I2C4_SMIS_R (*((volatile uint32_t *)0x400C0814)) +#define I2C4_SICR_R (*((volatile uint32_t *)0x400C0818)) +#define I2C4_SOAR2_R (*((volatile uint32_t *)0x400C081C)) +#define I2C4_SACKCTL_R (*((volatile uint32_t *)0x400C0820)) +#define I2C4_PP_R (*((volatile uint32_t *)0x400C0FC0)) +#define I2C4_PC_R (*((volatile uint32_t *)0x400C0FC4)) + +//***************************************************************************** +// +// I2C registers (I2C5) +// +//***************************************************************************** +#define I2C5_MSA_R (*((volatile uint32_t *)0x400C1000)) +#define I2C5_MCS_R (*((volatile uint32_t *)0x400C1004)) +#define I2C5_MDR_R (*((volatile uint32_t *)0x400C1008)) +#define I2C5_MTPR_R (*((volatile uint32_t *)0x400C100C)) +#define I2C5_MIMR_R (*((volatile uint32_t *)0x400C1010)) +#define I2C5_MRIS_R (*((volatile uint32_t *)0x400C1014)) +#define I2C5_MMIS_R (*((volatile uint32_t *)0x400C1018)) +#define I2C5_MICR_R (*((volatile uint32_t *)0x400C101C)) +#define I2C5_MCR_R (*((volatile uint32_t *)0x400C1020)) +#define I2C5_MCLKOCNT_R (*((volatile uint32_t *)0x400C1024)) +#define I2C5_MBMON_R (*((volatile uint32_t *)0x400C102C)) +#define I2C5_MCR2_R (*((volatile uint32_t *)0x400C1038)) +#define I2C5_SOAR_R (*((volatile uint32_t *)0x400C1800)) +#define I2C5_SCSR_R (*((volatile uint32_t *)0x400C1804)) +#define I2C5_SDR_R (*((volatile uint32_t *)0x400C1808)) +#define I2C5_SIMR_R (*((volatile uint32_t *)0x400C180C)) +#define I2C5_SRIS_R (*((volatile uint32_t *)0x400C1810)) +#define I2C5_SMIS_R (*((volatile uint32_t *)0x400C1814)) +#define I2C5_SICR_R (*((volatile uint32_t *)0x400C1818)) +#define I2C5_SOAR2_R (*((volatile uint32_t *)0x400C181C)) +#define I2C5_SACKCTL_R (*((volatile uint32_t *)0x400C1820)) +#define I2C5_PP_R (*((volatile uint32_t *)0x400C1FC0)) +#define I2C5_PC_R (*((volatile uint32_t *)0x400C1FC4)) + +//***************************************************************************** +// +// System Exception Module registers (SYSEXC) +// +//***************************************************************************** +#define SYSEXC_RIS_R (*((volatile uint32_t *)0x400F9000)) +#define SYSEXC_IM_R (*((volatile uint32_t *)0x400F9004)) +#define SYSEXC_MIS_R (*((volatile uint32_t *)0x400F9008)) +#define SYSEXC_IC_R (*((volatile uint32_t *)0x400F900C)) + +//***************************************************************************** +// +// Hibernation module registers (HIB) +// +//***************************************************************************** +#define HIB_RTCC_R (*((volatile uint32_t *)0x400FC000)) +#define HIB_RTCM0_R (*((volatile uint32_t *)0x400FC004)) +#define HIB_RTCLD_R (*((volatile uint32_t *)0x400FC00C)) +#define HIB_CTL_R (*((volatile uint32_t *)0x400FC010)) +#define HIB_IM_R (*((volatile uint32_t *)0x400FC014)) +#define HIB_RIS_R (*((volatile uint32_t *)0x400FC018)) +#define HIB_MIS_R (*((volatile uint32_t *)0x400FC01C)) +#define HIB_IC_R (*((volatile uint32_t *)0x400FC020)) +#define HIB_RTCT_R (*((volatile uint32_t *)0x400FC024)) +#define HIB_RTCSS_R (*((volatile uint32_t *)0x400FC028)) +#define HIB_DATA_R (*((volatile uint32_t *)0x400FC030)) + +//***************************************************************************** +// +// FLASH registers (FLASH CTRL) +// +//***************************************************************************** +#define FLASH_FMA_R (*((volatile uint32_t *)0x400FD000)) +#define FLASH_FMD_R (*((volatile uint32_t *)0x400FD004)) +#define FLASH_FMC_R (*((volatile uint32_t *)0x400FD008)) +#define FLASH_FCRIS_R (*((volatile uint32_t *)0x400FD00C)) +#define FLASH_FCIM_R (*((volatile uint32_t *)0x400FD010)) +#define FLASH_FCMISC_R (*((volatile uint32_t *)0x400FD014)) +#define FLASH_FMC2_R (*((volatile uint32_t *)0x400FD020)) +#define FLASH_FWBVAL_R (*((volatile uint32_t *)0x400FD030)) +#define FLASH_FWBN_R (*((volatile uint32_t *)0x400FD100)) +#define FLASH_FSIZE_R (*((volatile uint32_t *)0x400FDFC0)) +#define FLASH_SSIZE_R (*((volatile uint32_t *)0x400FDFC4)) +#define FLASH_ROMSWMAP_R (*((volatile uint32_t *)0x400FDFCC)) +#define FLASH_RMCTL_R (*((volatile uint32_t *)0x400FE0F0)) +#define FLASH_BOOTCFG_R (*((volatile uint32_t *)0x400FE1D0)) +#define FLASH_USERREG0_R (*((volatile uint32_t *)0x400FE1E0)) +#define FLASH_USERREG1_R (*((volatile uint32_t *)0x400FE1E4)) +#define FLASH_USERREG2_R (*((volatile uint32_t *)0x400FE1E8)) +#define FLASH_USERREG3_R (*((volatile uint32_t *)0x400FE1EC)) +#define FLASH_FMPRE0_R (*((volatile uint32_t *)0x400FE200)) +#define FLASH_FMPRE1_R (*((volatile uint32_t *)0x400FE204)) +#define FLASH_FMPRE2_R (*((volatile uint32_t *)0x400FE208)) +#define FLASH_FMPRE3_R (*((volatile uint32_t *)0x400FE20C)) +#define FLASH_FMPPE0_R (*((volatile uint32_t *)0x400FE400)) +#define FLASH_FMPPE1_R (*((volatile uint32_t *)0x400FE404)) +#define FLASH_FMPPE2_R (*((volatile uint32_t *)0x400FE408)) +#define FLASH_FMPPE3_R (*((volatile uint32_t *)0x400FE40C)) + +//***************************************************************************** +// +// System Control registers (SYSCTL) +// +//***************************************************************************** +#define SYSCTL_DID0_R (*((volatile uint32_t *)0x400FE000)) +#define SYSCTL_DID1_R (*((volatile uint32_t *)0x400FE004)) +#define SYSCTL_DC0_R (*((volatile uint32_t *)0x400FE008)) +#define SYSCTL_DC1_R (*((volatile uint32_t *)0x400FE010)) +#define SYSCTL_DC2_R (*((volatile uint32_t *)0x400FE014)) +#define SYSCTL_DC3_R (*((volatile uint32_t *)0x400FE018)) +#define SYSCTL_DC4_R (*((volatile uint32_t *)0x400FE01C)) +#define SYSCTL_DC5_R (*((volatile uint32_t *)0x400FE020)) +#define SYSCTL_DC6_R (*((volatile uint32_t *)0x400FE024)) +#define SYSCTL_DC7_R (*((volatile uint32_t *)0x400FE028)) +#define SYSCTL_DC8_R (*((volatile uint32_t *)0x400FE02C)) +#define SYSCTL_PBORCTL_R (*((volatile uint32_t *)0x400FE030)) +#define SYSCTL_SRCR0_R (*((volatile uint32_t *)0x400FE040)) +#define SYSCTL_SRCR1_R (*((volatile uint32_t *)0x400FE044)) +#define SYSCTL_SRCR2_R (*((volatile uint32_t *)0x400FE048)) +#define SYSCTL_RIS_R (*((volatile uint32_t *)0x400FE050)) +#define SYSCTL_IMC_R (*((volatile uint32_t *)0x400FE054)) +#define SYSCTL_MISC_R (*((volatile uint32_t *)0x400FE058)) +#define SYSCTL_RESC_R (*((volatile uint32_t *)0x400FE05C)) +#define SYSCTL_RCC_R (*((volatile uint32_t *)0x400FE060)) +#define SYSCTL_GPIOHBCTL_R (*((volatile uint32_t *)0x400FE06C)) +#define SYSCTL_RCC2_R (*((volatile uint32_t *)0x400FE070)) +#define SYSCTL_MOSCCTL_R (*((volatile uint32_t *)0x400FE07C)) +#define SYSCTL_RCGC0_R (*((volatile uint32_t *)0x400FE100)) +#define SYSCTL_RCGC1_R (*((volatile uint32_t *)0x400FE104)) +#define SYSCTL_RCGC2_R (*((volatile uint32_t *)0x400FE108)) +#define SYSCTL_SCGC0_R (*((volatile uint32_t *)0x400FE110)) +#define SYSCTL_SCGC1_R (*((volatile uint32_t *)0x400FE114)) +#define SYSCTL_SCGC2_R (*((volatile uint32_t *)0x400FE118)) +#define SYSCTL_DCGC0_R (*((volatile uint32_t *)0x400FE120)) +#define SYSCTL_DCGC1_R (*((volatile uint32_t *)0x400FE124)) +#define SYSCTL_DCGC2_R (*((volatile uint32_t *)0x400FE128)) +#define SYSCTL_DSLPCLKCFG_R (*((volatile uint32_t *)0x400FE144)) +#define SYSCTL_SYSPROP_R (*((volatile uint32_t *)0x400FE14C)) +#define SYSCTL_PIOSCCAL_R (*((volatile uint32_t *)0x400FE150)) +#define SYSCTL_PIOSCSTAT_R (*((volatile uint32_t *)0x400FE154)) +#define SYSCTL_PLLFREQ0_R (*((volatile uint32_t *)0x400FE160)) +#define SYSCTL_PLLFREQ1_R (*((volatile uint32_t *)0x400FE164)) +#define SYSCTL_PLLSTAT_R (*((volatile uint32_t *)0x400FE168)) +#define SYSCTL_SLPPWRCFG_R (*((volatile uint32_t *)0x400FE188)) +#define SYSCTL_DSLPPWRCFG_R (*((volatile uint32_t *)0x400FE18C)) +#define SYSCTL_DC9_R (*((volatile uint32_t *)0x400FE190)) +#define SYSCTL_NVMSTAT_R (*((volatile uint32_t *)0x400FE1A0)) +#define SYSCTL_LDOSPCTL_R (*((volatile uint32_t *)0x400FE1B4)) +#define SYSCTL_LDODPCTL_R (*((volatile uint32_t *)0x400FE1BC)) +#define SYSCTL_PPWD_R (*((volatile uint32_t *)0x400FE300)) +#define SYSCTL_PPTIMER_R (*((volatile uint32_t *)0x400FE304)) +#define SYSCTL_PPGPIO_R (*((volatile uint32_t *)0x400FE308)) +#define SYSCTL_PPDMA_R (*((volatile uint32_t *)0x400FE30C)) +#define SYSCTL_PPHIB_R (*((volatile uint32_t *)0x400FE314)) +#define SYSCTL_PPUART_R (*((volatile uint32_t *)0x400FE318)) +#define SYSCTL_PPSSI_R (*((volatile uint32_t *)0x400FE31C)) +#define SYSCTL_PPI2C_R (*((volatile uint32_t *)0x400FE320)) +#define SYSCTL_PPUSB_R (*((volatile uint32_t *)0x400FE328)) +#define SYSCTL_PPCAN_R (*((volatile uint32_t *)0x400FE334)) +#define SYSCTL_PPADC_R (*((volatile uint32_t *)0x400FE338)) +#define SYSCTL_PPACMP_R (*((volatile uint32_t *)0x400FE33C)) +#define SYSCTL_PPPWM_R (*((volatile uint32_t *)0x400FE340)) +#define SYSCTL_PPQEI_R (*((volatile uint32_t *)0x400FE344)) +#define SYSCTL_PPEEPROM_R (*((volatile uint32_t *)0x400FE358)) +#define SYSCTL_PPWTIMER_R (*((volatile uint32_t *)0x400FE35C)) +#define SYSCTL_SRWD_R (*((volatile uint32_t *)0x400FE500)) +#define SYSCTL_SRTIMER_R (*((volatile uint32_t *)0x400FE504)) +#define SYSCTL_SRGPIO_R (*((volatile uint32_t *)0x400FE508)) +#define SYSCTL_SRDMA_R (*((volatile uint32_t *)0x400FE50C)) +#define SYSCTL_SRHIB_R (*((volatile uint32_t *)0x400FE514)) +#define SYSCTL_SRUART_R (*((volatile uint32_t *)0x400FE518)) +#define SYSCTL_SRSSI_R (*((volatile uint32_t *)0x400FE51C)) +#define SYSCTL_SRI2C_R (*((volatile uint32_t *)0x400FE520)) +#define SYSCTL_SRUSB_R (*((volatile uint32_t *)0x400FE528)) +#define SYSCTL_SRCAN_R (*((volatile uint32_t *)0x400FE534)) +#define SYSCTL_SRADC_R (*((volatile uint32_t *)0x400FE538)) +#define SYSCTL_SRACMP_R (*((volatile uint32_t *)0x400FE53C)) +#define SYSCTL_SRPWM_R (*((volatile uint32_t *)0x400FE540)) +#define SYSCTL_SRQEI_R (*((volatile uint32_t *)0x400FE544)) +#define SYSCTL_SREEPROM_R (*((volatile uint32_t *)0x400FE558)) +#define SYSCTL_SRWTIMER_R (*((volatile uint32_t *)0x400FE55C)) +#define SYSCTL_RCGCWD_R (*((volatile uint32_t *)0x400FE600)) +#define SYSCTL_RCGCTIMER_R (*((volatile uint32_t *)0x400FE604)) +#define SYSCTL_RCGCGPIO_R (*((volatile uint32_t *)0x400FE608)) +#define SYSCTL_RCGCDMA_R (*((volatile uint32_t *)0x400FE60C)) +#define SYSCTL_RCGCHIB_R (*((volatile uint32_t *)0x400FE614)) +#define SYSCTL_RCGCUART_R (*((volatile uint32_t *)0x400FE618)) +#define SYSCTL_RCGCSSI_R (*((volatile uint32_t *)0x400FE61C)) +#define SYSCTL_RCGCI2C_R (*((volatile uint32_t *)0x400FE620)) +#define SYSCTL_RCGCUSB_R (*((volatile uint32_t *)0x400FE628)) +#define SYSCTL_RCGCCAN_R (*((volatile uint32_t *)0x400FE634)) +#define SYSCTL_RCGCADC_R (*((volatile uint32_t *)0x400FE638)) +#define SYSCTL_RCGCACMP_R (*((volatile uint32_t *)0x400FE63C)) +#define SYSCTL_RCGCPWM_R (*((volatile uint32_t *)0x400FE640)) +#define SYSCTL_RCGCQEI_R (*((volatile uint32_t *)0x400FE644)) +#define SYSCTL_RCGCEEPROM_R (*((volatile uint32_t *)0x400FE658)) +#define SYSCTL_RCGCWTIMER_R (*((volatile uint32_t *)0x400FE65C)) +#define SYSCTL_SCGCWD_R (*((volatile uint32_t *)0x400FE700)) +#define SYSCTL_SCGCTIMER_R (*((volatile uint32_t *)0x400FE704)) +#define SYSCTL_SCGCGPIO_R (*((volatile uint32_t *)0x400FE708)) +#define SYSCTL_SCGCDMA_R (*((volatile uint32_t *)0x400FE70C)) +#define SYSCTL_SCGCHIB_R (*((volatile uint32_t *)0x400FE714)) +#define SYSCTL_SCGCUART_R (*((volatile uint32_t *)0x400FE718)) +#define SYSCTL_SCGCSSI_R (*((volatile uint32_t *)0x400FE71C)) +#define SYSCTL_SCGCI2C_R (*((volatile uint32_t *)0x400FE720)) +#define SYSCTL_SCGCUSB_R (*((volatile uint32_t *)0x400FE728)) +#define SYSCTL_SCGCCAN_R (*((volatile uint32_t *)0x400FE734)) +#define SYSCTL_SCGCADC_R (*((volatile uint32_t *)0x400FE738)) +#define SYSCTL_SCGCACMP_R (*((volatile uint32_t *)0x400FE73C)) +#define SYSCTL_SCGCPWM_R (*((volatile uint32_t *)0x400FE740)) +#define SYSCTL_SCGCQEI_R (*((volatile uint32_t *)0x400FE744)) +#define SYSCTL_SCGCEEPROM_R (*((volatile uint32_t *)0x400FE758)) +#define SYSCTL_SCGCWTIMER_R (*((volatile uint32_t *)0x400FE75C)) +#define SYSCTL_DCGCWD_R (*((volatile uint32_t *)0x400FE800)) +#define SYSCTL_DCGCTIMER_R (*((volatile uint32_t *)0x400FE804)) +#define SYSCTL_DCGCGPIO_R (*((volatile uint32_t *)0x400FE808)) +#define SYSCTL_DCGCDMA_R (*((volatile uint32_t *)0x400FE80C)) +#define SYSCTL_DCGCHIB_R (*((volatile uint32_t *)0x400FE814)) +#define SYSCTL_DCGCUART_R (*((volatile uint32_t *)0x400FE818)) +#define SYSCTL_DCGCSSI_R (*((volatile uint32_t *)0x400FE81C)) +#define SYSCTL_DCGCI2C_R (*((volatile uint32_t *)0x400FE820)) +#define SYSCTL_DCGCUSB_R (*((volatile uint32_t *)0x400FE828)) +#define SYSCTL_DCGCCAN_R (*((volatile uint32_t *)0x400FE834)) +#define SYSCTL_DCGCADC_R (*((volatile uint32_t *)0x400FE838)) +#define SYSCTL_DCGCACMP_R (*((volatile uint32_t *)0x400FE83C)) +#define SYSCTL_DCGCPWM_R (*((volatile uint32_t *)0x400FE840)) +#define SYSCTL_DCGCQEI_R (*((volatile uint32_t *)0x400FE844)) +#define SYSCTL_DCGCEEPROM_R (*((volatile uint32_t *)0x400FE858)) +#define SYSCTL_DCGCWTIMER_R (*((volatile uint32_t *)0x400FE85C)) +#define SYSCTL_PRWD_R (*((volatile uint32_t *)0x400FEA00)) +#define SYSCTL_PRTIMER_R (*((volatile uint32_t *)0x400FEA04)) +#define SYSCTL_PRGPIO_R (*((volatile uint32_t *)0x400FEA08)) +#define SYSCTL_PRDMA_R (*((volatile uint32_t *)0x400FEA0C)) +#define SYSCTL_PRHIB_R (*((volatile uint32_t *)0x400FEA14)) +#define SYSCTL_PRUART_R (*((volatile uint32_t *)0x400FEA18)) +#define SYSCTL_PRSSI_R (*((volatile uint32_t *)0x400FEA1C)) +#define SYSCTL_PRI2C_R (*((volatile uint32_t *)0x400FEA20)) +#define SYSCTL_PRUSB_R (*((volatile uint32_t *)0x400FEA28)) +#define SYSCTL_PRCAN_R (*((volatile uint32_t *)0x400FEA34)) +#define SYSCTL_PRADC_R (*((volatile uint32_t *)0x400FEA38)) +#define SYSCTL_PRACMP_R (*((volatile uint32_t *)0x400FEA3C)) +#define SYSCTL_PRPWM_R (*((volatile uint32_t *)0x400FEA40)) +#define SYSCTL_PRQEI_R (*((volatile uint32_t *)0x400FEA44)) +#define SYSCTL_PREEPROM_R (*((volatile uint32_t *)0x400FEA58)) +#define SYSCTL_PRWTIMER_R (*((volatile uint32_t *)0x400FEA5C)) + +//***************************************************************************** +// +// Micro Direct Memory Access registers (UDMA) +// +//***************************************************************************** +#define UDMA_STAT_R (*((volatile uint32_t *)0x400FF000)) +#define UDMA_CFG_R (*((volatile uint32_t *)0x400FF004)) +#define UDMA_CTLBASE_R (*((volatile uint32_t *)0x400FF008)) +#define UDMA_ALTBASE_R (*((volatile uint32_t *)0x400FF00C)) +#define UDMA_WAITSTAT_R (*((volatile uint32_t *)0x400FF010)) +#define UDMA_SWREQ_R (*((volatile uint32_t *)0x400FF014)) +#define UDMA_USEBURSTSET_R (*((volatile uint32_t *)0x400FF018)) +#define UDMA_USEBURSTCLR_R (*((volatile uint32_t *)0x400FF01C)) +#define UDMA_REQMASKSET_R (*((volatile uint32_t *)0x400FF020)) +#define UDMA_REQMASKCLR_R (*((volatile uint32_t *)0x400FF024)) +#define UDMA_ENASET_R (*((volatile uint32_t *)0x400FF028)) +#define UDMA_ENACLR_R (*((volatile uint32_t *)0x400FF02C)) +#define UDMA_ALTSET_R (*((volatile uint32_t *)0x400FF030)) +#define UDMA_ALTCLR_R (*((volatile uint32_t *)0x400FF034)) +#define UDMA_PRIOSET_R (*((volatile uint32_t *)0x400FF038)) +#define UDMA_PRIOCLR_R (*((volatile uint32_t *)0x400FF03C)) +#define UDMA_ERRCLR_R (*((volatile uint32_t *)0x400FF04C)) +#define UDMA_CHASGN_R (*((volatile uint32_t *)0x400FF500)) +#define UDMA_CHIS_R (*((volatile uint32_t *)0x400FF504)) +#define UDMA_CHMAP0_R (*((volatile uint32_t *)0x400FF510)) +#define UDMA_CHMAP1_R (*((volatile uint32_t *)0x400FF514)) +#define UDMA_CHMAP2_R (*((volatile uint32_t *)0x400FF518)) +#define UDMA_CHMAP3_R (*((volatile uint32_t *)0x400FF51C)) + +//***************************************************************************** +// +// Micro Direct Memory Access (uDMA) offsets (UDMA) +// +//***************************************************************************** +#define UDMA_SRCENDP 0x00000000 // DMA Channel Source Address End + // Pointer +#define UDMA_DSTENDP 0x00000004 // DMA Channel Destination Address + // End Pointer +#define UDMA_CHCTL 0x00000008 // DMA Channel Control Word + +//***************************************************************************** +// +// NVIC registers (NVIC) +// +//***************************************************************************** +#define NVIC_ACTLR_R (*((volatile uint32_t *)0xE000E008)) +#define NVIC_ST_CTRL_R (*((volatile uint32_t *)0xE000E010)) +#define NVIC_ST_RELOAD_R (*((volatile uint32_t *)0xE000E014)) +#define NVIC_ST_CURRENT_R (*((volatile uint32_t *)0xE000E018)) +#define NVIC_EN0_R (*((volatile uint32_t *)0xE000E100)) +#define NVIC_EN1_R (*((volatile uint32_t *)0xE000E104)) +#define NVIC_EN2_R (*((volatile uint32_t *)0xE000E108)) +#define NVIC_EN3_R (*((volatile uint32_t *)0xE000E10C)) +#define NVIC_EN4_R (*((volatile uint32_t *)0xE000E110)) +#define NVIC_DIS0_R (*((volatile uint32_t *)0xE000E180)) +#define NVIC_DIS1_R (*((volatile uint32_t *)0xE000E184)) +#define NVIC_DIS2_R (*((volatile uint32_t *)0xE000E188)) +#define NVIC_DIS3_R (*((volatile uint32_t *)0xE000E18C)) +#define NVIC_DIS4_R (*((volatile uint32_t *)0xE000E190)) +#define NVIC_PEND0_R (*((volatile uint32_t *)0xE000E200)) +#define NVIC_PEND1_R (*((volatile uint32_t *)0xE000E204)) +#define NVIC_PEND2_R (*((volatile uint32_t *)0xE000E208)) +#define NVIC_PEND3_R (*((volatile uint32_t *)0xE000E20C)) +#define NVIC_PEND4_R (*((volatile uint32_t *)0xE000E210)) +#define NVIC_UNPEND0_R (*((volatile uint32_t *)0xE000E280)) +#define NVIC_UNPEND1_R (*((volatile uint32_t *)0xE000E284)) +#define NVIC_UNPEND2_R (*((volatile uint32_t *)0xE000E288)) +#define NVIC_UNPEND3_R (*((volatile uint32_t *)0xE000E28C)) +#define NVIC_UNPEND4_R (*((volatile uint32_t *)0xE000E290)) +#define NVIC_ACTIVE0_R (*((volatile uint32_t *)0xE000E300)) +#define NVIC_ACTIVE1_R (*((volatile uint32_t *)0xE000E304)) +#define NVIC_ACTIVE2_R (*((volatile uint32_t *)0xE000E308)) +#define NVIC_ACTIVE3_R (*((volatile uint32_t *)0xE000E30C)) +#define NVIC_ACTIVE4_R (*((volatile uint32_t *)0xE000E310)) +#define NVIC_PRI0_R (*((volatile uint32_t *)0xE000E400)) +#define NVIC_PRI1_R (*((volatile uint32_t *)0xE000E404)) +#define NVIC_PRI2_R (*((volatile uint32_t *)0xE000E408)) +#define NVIC_PRI3_R (*((volatile uint32_t *)0xE000E40C)) +#define NVIC_PRI4_R (*((volatile uint32_t *)0xE000E410)) +#define NVIC_PRI5_R (*((volatile uint32_t *)0xE000E414)) +#define NVIC_PRI6_R (*((volatile uint32_t *)0xE000E418)) +#define NVIC_PRI7_R (*((volatile uint32_t *)0xE000E41C)) +#define NVIC_PRI8_R (*((volatile uint32_t *)0xE000E420)) +#define NVIC_PRI9_R (*((volatile uint32_t *)0xE000E424)) +#define NVIC_PRI10_R (*((volatile uint32_t *)0xE000E428)) +#define NVIC_PRI11_R (*((volatile uint32_t *)0xE000E42C)) +#define NVIC_PRI12_R (*((volatile uint32_t *)0xE000E430)) +#define NVIC_PRI13_R (*((volatile uint32_t *)0xE000E434)) +#define NVIC_PRI14_R (*((volatile uint32_t *)0xE000E438)) +#define NVIC_PRI15_R (*((volatile uint32_t *)0xE000E43C)) +#define NVIC_PRI16_R (*((volatile uint32_t *)0xE000E440)) +#define NVIC_PRI17_R (*((volatile uint32_t *)0xE000E444)) +#define NVIC_PRI18_R (*((volatile uint32_t *)0xE000E448)) +#define NVIC_PRI19_R (*((volatile uint32_t *)0xE000E44C)) +#define NVIC_PRI20_R (*((volatile uint32_t *)0xE000E450)) +#define NVIC_PRI21_R (*((volatile uint32_t *)0xE000E454)) +#define NVIC_PRI22_R (*((volatile uint32_t *)0xE000E458)) +#define NVIC_PRI23_R (*((volatile uint32_t *)0xE000E45C)) +#define NVIC_PRI24_R (*((volatile uint32_t *)0xE000E460)) +#define NVIC_PRI25_R (*((volatile uint32_t *)0xE000E464)) +#define NVIC_PRI26_R (*((volatile uint32_t *)0xE000E468)) +#define NVIC_PRI27_R (*((volatile uint32_t *)0xE000E46C)) +#define NVIC_PRI28_R (*((volatile uint32_t *)0xE000E470)) +#define NVIC_PRI29_R (*((volatile uint32_t *)0xE000E474)) +#define NVIC_PRI30_R (*((volatile uint32_t *)0xE000E478)) +#define NVIC_PRI31_R (*((volatile uint32_t *)0xE000E47C)) +#define NVIC_PRI32_R (*((volatile uint32_t *)0xE000E480)) +#define NVIC_PRI33_R (*((volatile uint32_t *)0xE000E484)) +#define NVIC_PRI34_R (*((volatile uint32_t *)0xE000E488)) +#define NVIC_CPUID_R (*((volatile uint32_t *)0xE000ED00)) +#define NVIC_INT_CTRL_R (*((volatile uint32_t *)0xE000ED04)) +#define NVIC_VTABLE_R (*((volatile uint32_t *)0xE000ED08)) +#define NVIC_APINT_R (*((volatile uint32_t *)0xE000ED0C)) +#define NVIC_SYS_CTRL_R (*((volatile uint32_t *)0xE000ED10)) +#define NVIC_CFG_CTRL_R (*((volatile uint32_t *)0xE000ED14)) +#define NVIC_SYS_PRI1_R (*((volatile uint32_t *)0xE000ED18)) +#define NVIC_SYS_PRI2_R (*((volatile uint32_t *)0xE000ED1C)) +#define NVIC_SYS_PRI3_R (*((volatile uint32_t *)0xE000ED20)) +#define NVIC_SYS_HND_CTRL_R (*((volatile uint32_t *)0xE000ED24)) +#define NVIC_FAULT_STAT_R (*((volatile uint32_t *)0xE000ED28)) +#define NVIC_HFAULT_STAT_R (*((volatile uint32_t *)0xE000ED2C)) +#define NVIC_DEBUG_STAT_R (*((volatile uint32_t *)0xE000ED30)) +#define NVIC_MM_ADDR_R (*((volatile uint32_t *)0xE000ED34)) +#define NVIC_FAULT_ADDR_R (*((volatile uint32_t *)0xE000ED38)) +#define NVIC_CPAC_R (*((volatile uint32_t *)0xE000ED88)) +#define NVIC_MPU_TYPE_R (*((volatile uint32_t *)0xE000ED90)) +#define NVIC_MPU_CTRL_R (*((volatile uint32_t *)0xE000ED94)) +#define NVIC_MPU_NUMBER_R (*((volatile uint32_t *)0xE000ED98)) +#define NVIC_MPU_BASE_R (*((volatile uint32_t *)0xE000ED9C)) +#define NVIC_MPU_ATTR_R (*((volatile uint32_t *)0xE000EDA0)) +#define NVIC_MPU_BASE1_R (*((volatile uint32_t *)0xE000EDA4)) +#define NVIC_MPU_ATTR1_R (*((volatile uint32_t *)0xE000EDA8)) +#define NVIC_MPU_BASE2_R (*((volatile uint32_t *)0xE000EDAC)) +#define NVIC_MPU_ATTR2_R (*((volatile uint32_t *)0xE000EDB0)) +#define NVIC_MPU_BASE3_R (*((volatile uint32_t *)0xE000EDB4)) +#define NVIC_MPU_ATTR3_R (*((volatile uint32_t *)0xE000EDB8)) +#define NVIC_DBG_CTRL_R (*((volatile uint32_t *)0xE000EDF0)) +#define NVIC_DBG_XFER_R (*((volatile uint32_t *)0xE000EDF4)) +#define NVIC_DBG_DATA_R (*((volatile uint32_t *)0xE000EDF8)) +#define NVIC_DBG_INT_R (*((volatile uint32_t *)0xE000EDFC)) +#define NVIC_SW_TRIG_R (*((volatile uint32_t *)0xE000EF00)) +#define NVIC_FPCC_R (*((volatile uint32_t *)0xE000EF34)) +#define NVIC_FPCA_R (*((volatile uint32_t *)0xE000EF38)) +#define NVIC_FPDSC_R (*((volatile uint32_t *)0xE000EF3C)) + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_LOAD register. +// +//***************************************************************************** +#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value +#define WDT_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_VALUE register. +// +//***************************************************************************** +#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value +#define WDT_VALUE_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_CTL register. +// +//***************************************************************************** +#define WDT_CTL_WRC 0x80000000 // Write Complete +#define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type +#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable +#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_ICR register. +// +//***************************************************************************** +#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear +#define WDT_ICR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_RIS register. +// +//***************************************************************************** +#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_MIS register. +// +//***************************************************************************** +#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_TEST register. +// +//***************************************************************************** +#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_LOCK register. +// +//***************************************************************************** +#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock +#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked +#define WDT_LOCK_LOCKED 0x00000001 // Locked +#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_IM register. +// +//***************************************************************************** +#define GPIO_IM_GPIO_M 0x000000FF // GPIO Interrupt Mask Enable +#define GPIO_IM_GPIO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_RIS register. +// +//***************************************************************************** +#define GPIO_RIS_GPIO_M 0x000000FF // GPIO Interrupt Raw Status +#define GPIO_RIS_GPIO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_MIS register. +// +//***************************************************************************** +#define GPIO_MIS_GPIO_M 0x000000FF // GPIO Masked Interrupt Status +#define GPIO_MIS_GPIO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_ICR register. +// +//***************************************************************************** +#define GPIO_ICR_GPIO_M 0x000000FF // GPIO Interrupt Clear +#define GPIO_ICR_GPIO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_LOCK register. +// +//***************************************************************************** +#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock +#define GPIO_LOCK_UNLOCKED 0x00000000 // The GPIOCR register is unlocked + // and may be modified +#define GPIO_LOCK_LOCKED 0x00000001 // The GPIOCR register is locked + // and may not be modified +#define GPIO_LOCK_KEY 0x4C4F434B // Unlocks the GPIO_CR register + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port A. +// +//***************************************************************************** +#define GPIO_PCTL_PA7_M 0xF0000000 // PA7 Mask +#define GPIO_PCTL_PA7_I2C1SDA 0x30000000 // I2C1SDA on PA7 +#define GPIO_PCTL_PA7_M1PWM3 0x50000000 // M1PWM3 on PA7 +#define GPIO_PCTL_PA6_M 0x0F000000 // PA6 Mask +#define GPIO_PCTL_PA6_I2C1SCL 0x03000000 // I2C1SCL on PA6 +#define GPIO_PCTL_PA6_M1PWM2 0x05000000 // M1PWM2 on PA6 +#define GPIO_PCTL_PA5_M 0x00F00000 // PA5 Mask +#define GPIO_PCTL_PA5_SSI0TX 0x00200000 // SSI0TX on PA5 +#define GPIO_PCTL_PA4_M 0x000F0000 // PA4 Mask +#define GPIO_PCTL_PA4_SSI0RX 0x00020000 // SSI0RX on PA4 +#define GPIO_PCTL_PA3_M 0x0000F000 // PA3 Mask +#define GPIO_PCTL_PA3_SSI0FSS 0x00002000 // SSI0FSS on PA3 +#define GPIO_PCTL_PA2_M 0x00000F00 // PA2 Mask +#define GPIO_PCTL_PA2_SSI0CLK 0x00000200 // SSI0CLK on PA2 +#define GPIO_PCTL_PA1_M 0x000000F0 // PA1 Mask +#define GPIO_PCTL_PA1_U0TX 0x00000010 // U0TX on PA1 +#define GPIO_PCTL_PA1_CAN1TX 0x00000080 // CAN1TX on PA1 +#define GPIO_PCTL_PA0_M 0x0000000F // PA0 Mask +#define GPIO_PCTL_PA0_U0RX 0x00000001 // U0RX on PA0 +#define GPIO_PCTL_PA0_CAN1RX 0x00000008 // CAN1RX on PA0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port B. +// +//***************************************************************************** +#define GPIO_PCTL_PB5_M 0x00F00000 // PB5 Mask +#define GPIO_PCTL_PB5_SSI2FSS 0x00200000 // SSI2FSS on PB5 +#define GPIO_PCTL_PB5_M0PWM3 0x00400000 // M0PWM3 on PB5 +#define GPIO_PCTL_PB5_T1CCP1 0x00700000 // T1CCP1 on PB5 +#define GPIO_PCTL_PB5_CAN0TX 0x00800000 // CAN0TX on PB5 +#define GPIO_PCTL_PB4_M 0x000F0000 // PB4 Mask +#define GPIO_PCTL_PB4_SSI2CLK 0x00020000 // SSI2CLK on PB4 +#define GPIO_PCTL_PB4_M0PWM2 0x00040000 // M0PWM2 on PB4 +#define GPIO_PCTL_PB4_T1CCP0 0x00070000 // T1CCP0 on PB4 +#define GPIO_PCTL_PB4_CAN0RX 0x00080000 // CAN0RX on PB4 +#define GPIO_PCTL_PB3_M 0x0000F000 // PB3 Mask +#define GPIO_PCTL_PB3_I2C0SDA 0x00003000 // I2C0SDA on PB3 +#define GPIO_PCTL_PB3_T3CCP1 0x00007000 // T3CCP1 on PB3 +#define GPIO_PCTL_PB2_M 0x00000F00 // PB2 Mask +#define GPIO_PCTL_PB2_I2C0SCL 0x00000300 // I2C0SCL on PB2 +#define GPIO_PCTL_PB2_T3CCP0 0x00000700 // T3CCP0 on PB2 +#define GPIO_PCTL_PB1_M 0x000000F0 // PB1 Mask +#define GPIO_PCTL_PB1_USB0VBUS 0x00000000 // USB0VBUS on PB1 +#define GPIO_PCTL_PB1_U1TX 0x00000010 // U1TX on PB1 +#define GPIO_PCTL_PB1_T2CCP1 0x00000070 // T2CCP1 on PB1 +#define GPIO_PCTL_PB0_M 0x0000000F // PB0 Mask +#define GPIO_PCTL_PB0_USB0ID 0x00000000 // USB0ID on PB0 +#define GPIO_PCTL_PB0_U1RX 0x00000001 // U1RX on PB0 +#define GPIO_PCTL_PB0_T2CCP0 0x00000007 // T2CCP0 on PB0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port C. +// +//***************************************************************************** +#define GPIO_PCTL_PC7_M 0xF0000000 // PC7 Mask +#define GPIO_PCTL_PC7_U3TX 0x10000000 // U3TX on PC7 +#define GPIO_PCTL_PC7_WT1CCP1 0x70000000 // WT1CCP1 on PC7 +#define GPIO_PCTL_PC7_USB0PFLT 0x80000000 // USB0PFLT on PC7 +#define GPIO_PCTL_PC6_M 0x0F000000 // PC6 Mask +#define GPIO_PCTL_PC6_U3RX 0x01000000 // U3RX on PC6 +#define GPIO_PCTL_PC6_PHB1 0x06000000 // PHB1 on PC6 +#define GPIO_PCTL_PC6_WT1CCP0 0x07000000 // WT1CCP0 on PC6 +#define GPIO_PCTL_PC6_USB0EPEN 0x08000000 // USB0EPEN on PC6 +#define GPIO_PCTL_PC5_M 0x00F00000 // PC5 Mask +#define GPIO_PCTL_PC5_U4TX 0x00100000 // U4TX on PC5 +#define GPIO_PCTL_PC5_U1TX 0x00200000 // U1TX on PC5 +#define GPIO_PCTL_PC5_M0PWM7 0x00400000 // M0PWM7 on PC5 +#define GPIO_PCTL_PC5_PHA1 0x00600000 // PHA1 on PC5 +#define GPIO_PCTL_PC5_WT0CCP1 0x00700000 // WT0CCP1 on PC5 +#define GPIO_PCTL_PC5_U1CTS 0x00800000 // U1CTS on PC5 +#define GPIO_PCTL_PC4_M 0x000F0000 // PC4 Mask +#define GPIO_PCTL_PC4_U4RX 0x00010000 // U4RX on PC4 +#define GPIO_PCTL_PC4_U1RX 0x00020000 // U1RX on PC4 +#define GPIO_PCTL_PC4_M0PWM6 0x00040000 // M0PWM6 on PC4 +#define GPIO_PCTL_PC4_IDX1 0x00060000 // IDX1 on PC4 +#define GPIO_PCTL_PC4_WT0CCP0 0x00070000 // WT0CCP0 on PC4 +#define GPIO_PCTL_PC4_U1RTS 0x00080000 // U1RTS on PC4 +#define GPIO_PCTL_PC3_M 0x0000F000 // PC3 Mask +#define GPIO_PCTL_PC3_TDO 0x00001000 // TDO on PC3 +#define GPIO_PCTL_PC3_T5CCP1 0x00007000 // T5CCP1 on PC3 +#define GPIO_PCTL_PC2_M 0x00000F00 // PC2 Mask +#define GPIO_PCTL_PC2_TDI 0x00000100 // TDI on PC2 +#define GPIO_PCTL_PC2_T5CCP0 0x00000700 // T5CCP0 on PC2 +#define GPIO_PCTL_PC1_M 0x000000F0 // PC1 Mask +#define GPIO_PCTL_PC1_TMS 0x00000010 // TMS on PC1 +#define GPIO_PCTL_PC1_T4CCP1 0x00000070 // T4CCP1 on PC1 +#define GPIO_PCTL_PC0_M 0x0000000F // PC0 Mask +#define GPIO_PCTL_PC0_TCK 0x00000001 // TCK on PC0 +#define GPIO_PCTL_PC0_T4CCP0 0x00000007 // T4CCP0 on PC0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port D. +// +//***************************************************************************** +#define GPIO_PCTL_PD7_M 0xF0000000 // PD7 Mask +#define GPIO_PCTL_PD7_AIN4 0x00000000 // AIN4 on PD7 +#define GPIO_PCTL_PD7_U2TX 0x10000000 // U2TX on PD7 +#define GPIO_PCTL_PD7_M0FAULT1 0x40000000 // M0FAULT1 on PD7 +#define GPIO_PCTL_PD7_PHB0 0x60000000 // PHB0 on PD7 +#define GPIO_PCTL_PD7_WT5CCP1 0x70000000 // WT5CCP1 on PD7 +#define GPIO_PCTL_PD7_NMI 0x80000000 // NMI on PD7 +#define GPIO_PCTL_PD6_M 0x0F000000 // PD6 Mask +#define GPIO_PCTL_PD6_AIN5 0x00000000 // AIN5 on PD6 +#define GPIO_PCTL_PD6_U2RX 0x01000000 // U2RX on PD6 +#define GPIO_PCTL_PD6_M0FAULT0 0x04000000 // M0FAULT0 on PD6 +#define GPIO_PCTL_PD6_PHA0 0x06000000 // PHA0 on PD6 +#define GPIO_PCTL_PD6_WT5CCP0 0x07000000 // WT5CCP0 on PD6 +#define GPIO_PCTL_PD5_M 0x00F00000 // PD5 Mask +#define GPIO_PCTL_PD5_U6TX 0x00100000 // U6TX on PD5 +#define GPIO_PCTL_PD5_WT4CCP1 0x00700000 // WT4CCP1 on PD5 +#define GPIO_PCTL_PD4_M 0x000F0000 // PD4 Mask +#define GPIO_PCTL_PD4_AIN7 0x00000000 // AIN7 on PD4 +#define GPIO_PCTL_PD4_U6RX 0x00010000 // U6RX on PD4 +#define GPIO_PCTL_PD4_WT4CCP0 0x00070000 // WT4CCP0 on PD4 +#define GPIO_PCTL_PD3_M 0x0000F000 // PD3 Mask +#define GPIO_PCTL_PD3_AIN12 0x00000000 // AIN12 on PD3 +#define GPIO_PCTL_PD3_SSI3TX 0x00001000 // SSI3TX on PD3 +#define GPIO_PCTL_PD3_SSI1TX 0x00002000 // SSI1TX on PD3 +#define GPIO_PCTL_PD3_IDX0 0x00006000 // IDX0 on PD3 +#define GPIO_PCTL_PD3_WT3CCP1 0x00007000 // WT3CCP1 on PD3 +#define GPIO_PCTL_PD3_USB0PFLT 0x00008000 // USB0PFLT on PD3 +#define GPIO_PCTL_PD2_M 0x00000F00 // PD2 Mask +#define GPIO_PCTL_PD2_AIN13 0x00000000 // AIN13 on PD2 +#define GPIO_PCTL_PD2_SSI3RX 0x00000100 // SSI3RX on PD2 +#define GPIO_PCTL_PD2_SSI1RX 0x00000200 // SSI1RX on PD2 +#define GPIO_PCTL_PD2_M0FAULT0 0x00000400 // M0FAULT0 on PD2 +#define GPIO_PCTL_PD2_WT3CCP0 0x00000700 // WT3CCP0 on PD2 +#define GPIO_PCTL_PD2_USB0EPEN 0x00000800 // USB0EPEN on PD2 +#define GPIO_PCTL_PD1_M 0x000000F0 // PD1 Mask +#define GPIO_PCTL_PD1_AIN14 0x00000000 // AIN14 on PD1 +#define GPIO_PCTL_PD1_SSI3FSS 0x00000010 // SSI3FSS on PD1 +#define GPIO_PCTL_PD1_SSI1FSS 0x00000020 // SSI1FSS on PD1 +#define GPIO_PCTL_PD1_I2C3SDA 0x00000030 // I2C3SDA on PD1 +#define GPIO_PCTL_PD1_M0PWM7 0x00000040 // M0PWM7 on PD1 +#define GPIO_PCTL_PD1_M1PWM1 0x00000050 // M1PWM1 on PD1 +#define GPIO_PCTL_PD1_WT2CCP1 0x00000070 // WT2CCP1 on PD1 +#define GPIO_PCTL_PD0_M 0x0000000F // PD0 Mask +#define GPIO_PCTL_PD0_AIN15 0x00000000 // AIN15 on PD0 +#define GPIO_PCTL_PD0_SSI3CLK 0x00000001 // SSI3CLK on PD0 +#define GPIO_PCTL_PD0_SSI1CLK 0x00000002 // SSI1CLK on PD0 +#define GPIO_PCTL_PD0_I2C3SCL 0x00000003 // I2C3SCL on PD0 +#define GPIO_PCTL_PD0_M0PWM6 0x00000004 // M0PWM6 on PD0 +#define GPIO_PCTL_PD0_M1PWM0 0x00000005 // M1PWM0 on PD0 +#define GPIO_PCTL_PD0_WT2CCP0 0x00000007 // WT2CCP0 on PD0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port E. +// +//***************************************************************************** +#define GPIO_PCTL_PE7_M 0xF0000000 // PE7 Mask +#define GPIO_PCTL_PE7_AIN20 0x00000000 // AIN20 on PE7 +#define GPIO_PCTL_PE7_U1RI 0x10000000 // U1RI on PE7 +#define GPIO_PCTL_PE7_CAN1TX 0x80000000 // CAN1TX on PE7 +#define GPIO_PCTL_PE6_M 0x0F000000 // PE6 Mask +#define GPIO_PCTL_PE6_AIN21 0x00000000 // AIN21 on PE6 +#define GPIO_PCTL_PE6_CAN1RX 0x08000000 // CAN1RX on PE6 +#define GPIO_PCTL_PE5_M 0x00F00000 // PE5 Mask +#define GPIO_PCTL_PE5_AIN8 0x00000000 // AIN8 on PE5 +#define GPIO_PCTL_PE5_U5TX 0x00100000 // U5TX on PE5 +#define GPIO_PCTL_PE5_I2C2SDA 0x00300000 // I2C2SDA on PE5 +#define GPIO_PCTL_PE5_M0PWM5 0x00400000 // M0PWM5 on PE5 +#define GPIO_PCTL_PE5_M1PWM3 0x00500000 // M1PWM3 on PE5 +#define GPIO_PCTL_PE5_CAN0TX 0x00800000 // CAN0TX on PE5 +#define GPIO_PCTL_PE4_M 0x000F0000 // PE4 Mask +#define GPIO_PCTL_PE4_AIN9 0x00000000 // AIN9 on PE4 +#define GPIO_PCTL_PE4_U5RX 0x00010000 // U5RX on PE4 +#define GPIO_PCTL_PE4_I2C2SCL 0x00030000 // I2C2SCL on PE4 +#define GPIO_PCTL_PE4_M0PWM4 0x00040000 // M0PWM4 on PE4 +#define GPIO_PCTL_PE4_M1PWM2 0x00050000 // M1PWM2 on PE4 +#define GPIO_PCTL_PE4_CAN0RX 0x00080000 // CAN0RX on PE4 +#define GPIO_PCTL_PE3_M 0x0000F000 // PE3 Mask +#define GPIO_PCTL_PE3_AIN0 0x00000000 // AIN0 on PE3 +#define GPIO_PCTL_PE2_M 0x00000F00 // PE2 Mask +#define GPIO_PCTL_PE2_AIN1 0x00000000 // AIN1 on PE2 +#define GPIO_PCTL_PE1_M 0x000000F0 // PE1 Mask +#define GPIO_PCTL_PE1_AIN2 0x00000000 // AIN2 on PE1 +#define GPIO_PCTL_PE1_U7TX 0x00000010 // U7TX on PE1 +#define GPIO_PCTL_PE0_M 0x0000000F // PE0 Mask +#define GPIO_PCTL_PE0_AIN3 0x00000000 // AIN3 on PE0 +#define GPIO_PCTL_PE0_U7RX 0x00000001 // U7RX on PE0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port F. +// +//***************************************************************************** +#define GPIO_PCTL_PF7_M 0xF0000000 // PF7 Mask +#define GPIO_PCTL_PF7_I2C2SDA 0x30000000 // I2C2SDA on PF7 +#define GPIO_PCTL_PF7_M1FAULT0 0x50000000 // M1FAULT0 on PF7 +#define GPIO_PCTL_PF7_T3CCP1 0x70000000 // T3CCP1 on PF7 +#define GPIO_PCTL_PF6_M 0x0F000000 // PF6 Mask +#define GPIO_PCTL_PF6_I2C2SCL 0x03000000 // I2C2SCL on PF6 +#define GPIO_PCTL_PF6_T3CCP0 0x07000000 // T3CCP0 on PF6 +#define GPIO_PCTL_PF5_M 0x00F00000 // PF5 Mask +#define GPIO_PCTL_PF5_M0FAULT3 0x00400000 // M0FAULT3 on PF5 +#define GPIO_PCTL_PF5_T2CCP1 0x00700000 // T2CCP1 on PF5 +#define GPIO_PCTL_PF5_USB0PFLT 0x00800000 // USB0PFLT on PF5 +#define GPIO_PCTL_PF4_M 0x000F0000 // PF4 Mask +#define GPIO_PCTL_PF4_U1DTR 0x00010000 // U1DTR on PF4 +#define GPIO_PCTL_PF4_M0FAULT2 0x00040000 // M0FAULT2 on PF4 +#define GPIO_PCTL_PF4_M1FAULT0 0x00050000 // M1FAULT0 on PF4 +#define GPIO_PCTL_PF4_IDX0 0x00060000 // IDX0 on PF4 +#define GPIO_PCTL_PF4_T2CCP0 0x00070000 // T2CCP0 on PF4 +#define GPIO_PCTL_PF4_USB0EPEN 0x00080000 // USB0EPEN on PF4 +#define GPIO_PCTL_PF4_TRD3 0x000E0000 // TRD3 on PF4 +#define GPIO_PCTL_PF3_M 0x0000F000 // PF3 Mask +#define GPIO_PCTL_PF3_U1DSR 0x00001000 // U1DSR on PF3 +#define GPIO_PCTL_PF3_SSI1FSS 0x00002000 // SSI1FSS on PF3 +#define GPIO_PCTL_PF3_CAN0TX 0x00003000 // CAN0TX on PF3 +#define GPIO_PCTL_PF3_M0FAULT1 0x00004000 // M0FAULT1 on PF3 +#define GPIO_PCTL_PF3_M1PWM7 0x00005000 // M1PWM7 on PF3 +#define GPIO_PCTL_PF3_T1CCP1 0x00007000 // T1CCP1 on PF3 +#define GPIO_PCTL_PF3_TRCLK 0x0000E000 // TRCLK on PF3 +#define GPIO_PCTL_PF2_M 0x00000F00 // PF2 Mask +#define GPIO_PCTL_PF2_U1DCD 0x00000100 // U1DCD on PF2 +#define GPIO_PCTL_PF2_SSI1CLK 0x00000200 // SSI1CLK on PF2 +#define GPIO_PCTL_PF2_M0FAULT0 0x00000400 // M0FAULT0 on PF2 +#define GPIO_PCTL_PF2_M1PWM6 0x00000500 // M1PWM6 on PF2 +#define GPIO_PCTL_PF2_T1CCP0 0x00000700 // T1CCP0 on PF2 +#define GPIO_PCTL_PF2_C2O 0x00000900 // C2O on PF2 +#define GPIO_PCTL_PF2_TRD0 0x00000E00 // TRD0 on PF2 +#define GPIO_PCTL_PF1_M 0x000000F0 // PF1 Mask +#define GPIO_PCTL_PF1_U1CTS 0x00000010 // U1CTS on PF1 +#define GPIO_PCTL_PF1_SSI1TX 0x00000020 // SSI1TX on PF1 +#define GPIO_PCTL_PF1_M1PWM5 0x00000050 // M1PWM5 on PF1 +#define GPIO_PCTL_PF1_PHB0 0x00000060 // PHB0 on PF1 +#define GPIO_PCTL_PF1_T0CCP1 0x00000070 // T0CCP1 on PF1 +#define GPIO_PCTL_PF1_C1O 0x00000090 // C1O on PF1 +#define GPIO_PCTL_PF1_TRD1 0x000000E0 // TRD1 on PF1 +#define GPIO_PCTL_PF0_M 0x0000000F // PF0 Mask +#define GPIO_PCTL_PF0_U1RTS 0x00000001 // U1RTS on PF0 +#define GPIO_PCTL_PF0_SSI1RX 0x00000002 // SSI1RX on PF0 +#define GPIO_PCTL_PF0_CAN0RX 0x00000003 // CAN0RX on PF0 +#define GPIO_PCTL_PF0_M1PWM4 0x00000005 // M1PWM4 on PF0 +#define GPIO_PCTL_PF0_PHA0 0x00000006 // PHA0 on PF0 +#define GPIO_PCTL_PF0_T0CCP0 0x00000007 // T0CCP0 on PF0 +#define GPIO_PCTL_PF0_NMI 0x00000008 // NMI on PF0 +#define GPIO_PCTL_PF0_C0O 0x00000009 // C0O on PF0 +#define GPIO_PCTL_PF0_TRD2 0x0000000E // TRD2 on PF0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port G. +// +//***************************************************************************** +#define GPIO_PCTL_PG7_M 0xF0000000 // PG7 Mask +#define GPIO_PCTL_PG7_C2M 0x00000000 // C2- on PG7 +#define GPIO_PCTL_PG7_I2C5SDA 0x30000000 // I2C5SDA on PG7 +#define GPIO_PCTL_PG7_M0PWM7 0x40000000 // M0PWM7 on PG7 +#define GPIO_PCTL_PG7_IDX1 0x50000000 // IDX1 on PG7 +#define GPIO_PCTL_PG7_WT1CCP1 0x70000000 // WT1CCP1 on PG7 +#define GPIO_PCTL_PG6_M 0x0F000000 // PG6 Mask +#define GPIO_PCTL_PG6_C2P 0x00000000 // C2+ on PG6 +#define GPIO_PCTL_PG6_I2C5SCL 0x03000000 // I2C5SCL on PG6 +#define GPIO_PCTL_PG6_M0PWM6 0x04000000 // M0PWM6 on PG6 +#define GPIO_PCTL_PG6_WT1CCP0 0x07000000 // WT1CCP0 on PG6 +#define GPIO_PCTL_PG5_M 0x00F00000 // PG5 Mask +#define GPIO_PCTL_PG5_U2TX 0x00100000 // U2TX on PG5 +#define GPIO_PCTL_PG5_I2C1SDA 0x00300000 // I2C1SDA on PG5 +#define GPIO_PCTL_PG5_M0PWM5 0x00400000 // M0PWM5 on PG5 +#define GPIO_PCTL_PG5_M1PWM3 0x00500000 // M1PWM3 on PG5 +#define GPIO_PCTL_PG5_IDX1 0x00600000 // IDX1 on PG5 +#define GPIO_PCTL_PG5_WT0CCP1 0x00700000 // WT0CCP1 on PG5 +#define GPIO_PCTL_PG5_USB0PFLT 0x00800000 // USB0PFLT on PG5 +#define GPIO_PCTL_PG4_M 0x000F0000 // PG4 Mask +#define GPIO_PCTL_PG4_U2RX 0x00010000 // U2RX on PG4 +#define GPIO_PCTL_PG4_I2C1SCL 0x00030000 // I2C1SCL on PG4 +#define GPIO_PCTL_PG4_M0PWM4 0x00040000 // M0PWM4 on PG4 +#define GPIO_PCTL_PG4_M1PWM2 0x00050000 // M1PWM2 on PG4 +#define GPIO_PCTL_PG4_PHB1 0x00060000 // PHB1 on PG4 +#define GPIO_PCTL_PG4_WT0CCP0 0x00070000 // WT0CCP0 on PG4 +#define GPIO_PCTL_PG4_USB0EPEN 0x00080000 // USB0EPEN on PG4 +#define GPIO_PCTL_PG3_M 0x0000F000 // PG3 Mask +#define GPIO_PCTL_PG3_I2C4SDA 0x00003000 // I2C4SDA on PG3 +#define GPIO_PCTL_PG3_M0FAULT2 0x00004000 // M0FAULT2 on PG3 +#define GPIO_PCTL_PG3_M1PWM1 0x00005000 // M1PWM1 on PG3 +#define GPIO_PCTL_PG3_PHA1 0x00006000 // PHA1 on PG3 +#define GPIO_PCTL_PG3_T5CCP1 0x00007000 // T5CCP1 on PG3 +#define GPIO_PCTL_PG2_M 0x00000F00 // PG2 Mask +#define GPIO_PCTL_PG2_I2C4SCL 0x00000300 // I2C4SCL on PG2 +#define GPIO_PCTL_PG2_M0FAULT1 0x00000400 // M0FAULT1 on PG2 +#define GPIO_PCTL_PG2_M1PWM0 0x00000500 // M1PWM0 on PG2 +#define GPIO_PCTL_PG2_T5CCP0 0x00000700 // T5CCP0 on PG2 +#define GPIO_PCTL_PG1_M 0x000000F0 // PG1 Mask +#define GPIO_PCTL_PG1_I2C3SDA 0x00000030 // I2C3SDA on PG1 +#define GPIO_PCTL_PG1_M1FAULT2 0x00000050 // M1FAULT2 on PG1 +#define GPIO_PCTL_PG1_PHB1 0x00000060 // PHB1 on PG1 +#define GPIO_PCTL_PG1_T4CCP1 0x00000070 // T4CCP1 on PG1 +#define GPIO_PCTL_PG0_M 0x0000000F // PG0 Mask +#define GPIO_PCTL_PG0_I2C3SCL 0x00000003 // I2C3SCL on PG0 +#define GPIO_PCTL_PG0_M1FAULT1 0x00000005 // M1FAULT1 on PG0 +#define GPIO_PCTL_PG0_PHA1 0x00000006 // PHA1 on PG0 +#define GPIO_PCTL_PG0_T4CCP0 0x00000007 // T4CCP0 on PG0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port H. +// +//***************************************************************************** +#define GPIO_PCTL_PH7_M 0xF0000000 // PH7 Mask +#define GPIO_PCTL_PH7_SSI2TX 0x20000000 // SSI2TX on PH7 +#define GPIO_PCTL_PH7_M0PWM7 0x40000000 // M0PWM7 on PH7 +#define GPIO_PCTL_PH7_WT4CCP1 0x70000000 // WT4CCP1 on PH7 +#define GPIO_PCTL_PH6_M 0x0F000000 // PH6 Mask +#define GPIO_PCTL_PH6_SSI2RX 0x02000000 // SSI2RX on PH6 +#define GPIO_PCTL_PH6_M0PWM6 0x04000000 // M0PWM6 on PH6 +#define GPIO_PCTL_PH6_WT4CCP0 0x07000000 // WT4CCP0 on PH6 +#define GPIO_PCTL_PH5_M 0x00F00000 // PH5 Mask +#define GPIO_PCTL_PH5_SSI2FSS 0x00200000 // SSI2FSS on PH5 +#define GPIO_PCTL_PH5_M0PWM5 0x00400000 // M0PWM5 on PH5 +#define GPIO_PCTL_PH5_PHB0 0x00500000 // PHB0 on PH5 +#define GPIO_PCTL_PH5_WT3CCP1 0x00700000 // WT3CCP1 on PH5 +#define GPIO_PCTL_PH4_M 0x000F0000 // PH4 Mask +#define GPIO_PCTL_PH4_SSI2CLK 0x00020000 // SSI2CLK on PH4 +#define GPIO_PCTL_PH4_M0PWM4 0x00040000 // M0PWM4 on PH4 +#define GPIO_PCTL_PH4_PHA0 0x00050000 // PHA0 on PH4 +#define GPIO_PCTL_PH4_WT3CCP0 0x00070000 // WT3CCP0 on PH4 +#define GPIO_PCTL_PH3_M 0x0000F000 // PH3 Mask +#define GPIO_PCTL_PH3_AIN19 0x00000000 // AIN19 on PH3 +#define GPIO_PCTL_PH3_SSI3TX 0x00002000 // SSI3TX on PH3 +#define GPIO_PCTL_PH3_M0PWM3 0x00004000 // M0PWM3 on PH3 +#define GPIO_PCTL_PH3_M0FAULT3 0x00006000 // M0FAULT3 on PH3 +#define GPIO_PCTL_PH3_WT5CCP1 0x00007000 // WT5CCP1 on PH3 +#define GPIO_PCTL_PH2_M 0x00000F00 // PH2 Mask +#define GPIO_PCTL_PH2_AIN18 0x00000000 // AIN18 on PH2 +#define GPIO_PCTL_PH2_SSI3RX 0x00000200 // SSI3RX on PH2 +#define GPIO_PCTL_PH2_M0PWM2 0x00000400 // M0PWM2 on PH2 +#define GPIO_PCTL_PH2_M0FAULT2 0x00000600 // M0FAULT2 on PH2 +#define GPIO_PCTL_PH2_WT5CCP0 0x00000700 // WT5CCP0 on PH2 +#define GPIO_PCTL_PH1_M 0x000000F0 // PH1 Mask +#define GPIO_PCTL_PH1_AIN17 0x00000000 // AIN17 on PH1 +#define GPIO_PCTL_PH1_SSI3FSS 0x00000020 // SSI3FSS on PH1 +#define GPIO_PCTL_PH1_M0PWM1 0x00000040 // M0PWM1 on PH1 +#define GPIO_PCTL_PH1_IDX0 0x00000050 // IDX0 on PH1 +#define GPIO_PCTL_PH1_M0FAULT1 0x00000060 // M0FAULT1 on PH1 +#define GPIO_PCTL_PH1_WT2CCP1 0x00000070 // WT2CCP1 on PH1 +#define GPIO_PCTL_PH0_M 0x0000000F // PH0 Mask +#define GPIO_PCTL_PH0_AIN16 0x00000000 // AIN16 on PH0 +#define GPIO_PCTL_PH0_SSI3CLK 0x00000002 // SSI3CLK on PH0 +#define GPIO_PCTL_PH0_M0PWM0 0x00000004 // M0PWM0 on PH0 +#define GPIO_PCTL_PH0_M0FAULT0 0x00000006 // M0FAULT0 on PH0 +#define GPIO_PCTL_PH0_WT2CCP0 0x00000007 // WT2CCP0 on PH0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port J. +// +//***************************************************************************** +#define GPIO_PCTL_PJ2_M 0x00000F00 // PJ2 Mask +#define GPIO_PCTL_PJ2_U5RX 0x00000100 // U5RX on PJ2 +#define GPIO_PCTL_PJ2_IDX0 0x00000500 // IDX0 on PJ2 +#define GPIO_PCTL_PJ2_T2CCP0 0x00000700 // T2CCP0 on PJ2 +#define GPIO_PCTL_PJ1_M 0x000000F0 // PJ1 Mask +#define GPIO_PCTL_PJ1_USB0DP 0x00000000 // USB0DP on PJ1 +#define GPIO_PCTL_PJ1_U4TX 0x00000010 // U4TX on PJ1 +#define GPIO_PCTL_PJ1_T1CCP1 0x00000070 // T1CCP1 on PJ1 +#define GPIO_PCTL_PJ0_M 0x0000000F // PJ0 Mask +#define GPIO_PCTL_PJ0_USB0DM 0x00000000 // USB0DM on PJ0 +#define GPIO_PCTL_PJ0_U4RX 0x00000001 // U4RX on PJ0 +#define GPIO_PCTL_PJ0_T1CCP0 0x00000007 // T1CCP0 on PJ0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port K. +// +//***************************************************************************** +#define GPIO_PCTL_PK3_M 0x0000F000 // PK3 Mask +#define GPIO_PCTL_PK3_SSI3TX 0x00002000 // SSI3TX on PK3 +#define GPIO_PCTL_PK3_M1FAULT3 0x00006000 // M1FAULT3 on PK3 +#define GPIO_PCTL_PK2_M 0x00000F00 // PK2 Mask +#define GPIO_PCTL_PK2_SSI3RX 0x00000200 // SSI3RX on PK2 +#define GPIO_PCTL_PK2_M1FAULT2 0x00000600 // M1FAULT2 on PK2 +#define GPIO_PCTL_PK1_M 0x000000F0 // PK1 Mask +#define GPIO_PCTL_PK1_SSI3FSS 0x00000020 // SSI3FSS on PK1 +#define GPIO_PCTL_PK1_M1FAULT1 0x00000060 // M1FAULT1 on PK1 +#define GPIO_PCTL_PK0_M 0x0000000F // PK0 Mask +#define GPIO_PCTL_PK0_SSI3CLK 0x00000002 // SSI3CLK on PK0 +#define GPIO_PCTL_PK0_M1FAULT0 0x00000006 // M1FAULT0 on PK0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_CR0 register. +// +//***************************************************************************** +#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate +#define SSI_CR0_SPH 0x00000080 // SSI Serial Clock Phase +#define SSI_CR0_SPO 0x00000040 // SSI Serial Clock Polarity +#define SSI_CR0_FRF_M 0x00000030 // SSI Frame Format Select +#define SSI_CR0_FRF_MOTO 0x00000000 // Freescale SPI Frame Format +#define SSI_CR0_FRF_TI 0x00000010 // Synchronous Serial Frame Format +#define SSI_CR0_FRF_NMW 0x00000020 // MICROWIRE Frame Format +#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select +#define SSI_CR0_DSS_4 0x00000003 // 4-bit data +#define SSI_CR0_DSS_5 0x00000004 // 5-bit data +#define SSI_CR0_DSS_6 0x00000005 // 6-bit data +#define SSI_CR0_DSS_7 0x00000006 // 7-bit data +#define SSI_CR0_DSS_8 0x00000007 // 8-bit data +#define SSI_CR0_DSS_9 0x00000008 // 9-bit data +#define SSI_CR0_DSS_10 0x00000009 // 10-bit data +#define SSI_CR0_DSS_11 0x0000000A // 11-bit data +#define SSI_CR0_DSS_12 0x0000000B // 12-bit data +#define SSI_CR0_DSS_13 0x0000000C // 13-bit data +#define SSI_CR0_DSS_14 0x0000000D // 14-bit data +#define SSI_CR0_DSS_15 0x0000000E // 15-bit data +#define SSI_CR0_DSS_16 0x0000000F // 16-bit data +#define SSI_CR0_SCR_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_CR1 register. +// +//***************************************************************************** +#define SSI_CR1_EOT 0x00000010 // End of Transmission +#define SSI_CR1_MS 0x00000004 // SSI Master/Slave Select +#define SSI_CR1_SSE 0x00000002 // SSI Synchronous Serial Port + // Enable +#define SSI_CR1_LBM 0x00000001 // SSI Loopback Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_DR register. +// +//***************************************************************************** +#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data +#define SSI_DR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_SR register. +// +//***************************************************************************** +#define SSI_SR_BSY 0x00000010 // SSI Busy Bit +#define SSI_SR_RFF 0x00000008 // SSI Receive FIFO Full +#define SSI_SR_RNE 0x00000004 // SSI Receive FIFO Not Empty +#define SSI_SR_TNF 0x00000002 // SSI Transmit FIFO Not Full +#define SSI_SR_TFE 0x00000001 // SSI Transmit FIFO Empty + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_CPSR register. +// +//***************************************************************************** +#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor +#define SSI_CPSR_CPSDVSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_IM register. +// +//***************************************************************************** +#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt Mask +#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask +#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt + // Mask +#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt + // Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_RIS register. +// +//***************************************************************************** +#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt + // Status +#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt + // Status +#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw + // Interrupt Status +#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_MIS register. +// +//***************************************************************************** +#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked + // Interrupt Status +#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked + // Interrupt Status +#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked + // Interrupt Status +#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_ICR register. +// +//***************************************************************************** +#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt + // Clear +#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_DMACTL register. +// +//***************************************************************************** +#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable +#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_CC register. +// +//***************************************************************************** +#define SSI_CC_CS_M 0x0000000F // SSI Baud Clock Source +#define SSI_CC_CS_SYSPLL 0x00000000 // System clock (based on clock + // source and divisor factor) +#define SSI_CC_CS_PIOSC 0x00000005 // PIOSC + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_DR register. +// +//***************************************************************************** +#define UART_DR_OE 0x00000800 // UART Overrun Error +#define UART_DR_BE 0x00000400 // UART Break Error +#define UART_DR_PE 0x00000200 // UART Parity Error +#define UART_DR_FE 0x00000100 // UART Framing Error +#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received +#define UART_DR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_RSR register. +// +//***************************************************************************** +#define UART_RSR_OE 0x00000008 // UART Overrun Error +#define UART_RSR_BE 0x00000004 // UART Break Error +#define UART_RSR_PE 0x00000002 // UART Parity Error +#define UART_RSR_FE 0x00000001 // UART Framing Error + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ECR register. +// +//***************************************************************************** +#define UART_ECR_DATA_M 0x000000FF // Error Clear +#define UART_ECR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_FR register. +// +//***************************************************************************** +#define UART_FR_RI 0x00000100 // Ring Indicator +#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty +#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full +#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full +#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty +#define UART_FR_BUSY 0x00000008 // UART Busy +#define UART_FR_DCD 0x00000004 // Data Carrier Detect +#define UART_FR_DSR 0x00000002 // Data Set Ready +#define UART_FR_CTS 0x00000001 // Clear To Send + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ILPR register. +// +//***************************************************************************** +#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor +#define UART_ILPR_ILPDVSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_IBRD register. +// +//***************************************************************************** +#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor +#define UART_IBRD_DIVINT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_FBRD register. +// +//***************************************************************************** +#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor +#define UART_FBRD_DIVFRAC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_LCRH register. +// +//***************************************************************************** +#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select +#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length +#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default) +#define UART_LCRH_WLEN_6 0x00000020 // 6 bits +#define UART_LCRH_WLEN_7 0x00000040 // 7 bits +#define UART_LCRH_WLEN_8 0x00000060 // 8 bits +#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs +#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select +#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select +#define UART_LCRH_PEN 0x00000002 // UART Parity Enable +#define UART_LCRH_BRK 0x00000001 // UART Send Break + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_CTL register. +// +//***************************************************************************** +#define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send +#define UART_CTL_RTSEN 0x00004000 // Enable Request to Send +#define UART_CTL_RTS 0x00000800 // Request to Send +#define UART_CTL_DTR 0x00000400 // Data Terminal Ready +#define UART_CTL_RXE 0x00000200 // UART Receive Enable +#define UART_CTL_TXE 0x00000100 // UART Transmit Enable +#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable +#define UART_CTL_HSE 0x00000020 // High-Speed Enable +#define UART_CTL_EOT 0x00000010 // End of Transmission +#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support +#define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode +#define UART_CTL_SIREN 0x00000002 // UART SIR Enable +#define UART_CTL_UARTEN 0x00000001 // UART Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_IFLS register. +// +//***************************************************************************** +#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO + // Level Select +#define UART_IFLS_RX1_8 0x00000000 // RX FIFO >= 1/8 full +#define UART_IFLS_RX2_8 0x00000008 // RX FIFO >= 1/4 full +#define UART_IFLS_RX4_8 0x00000010 // RX FIFO >= 1/2 full (default) +#define UART_IFLS_RX6_8 0x00000018 // RX FIFO >= 3/4 full +#define UART_IFLS_RX7_8 0x00000020 // RX FIFO >= 7/8 full +#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO + // Level Select +#define UART_IFLS_TX1_8 0x00000000 // TX FIFO <= 1/8 full +#define UART_IFLS_TX2_8 0x00000001 // TX FIFO <= 1/4 full +#define UART_IFLS_TX4_8 0x00000002 // TX FIFO <= 1/2 full (default) +#define UART_IFLS_TX6_8 0x00000003 // TX FIFO <= 3/4 full +#define UART_IFLS_TX7_8 0x00000004 // TX FIFO <= 7/8 full + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_IM register. +// +//***************************************************************************** +#define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask +#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt + // Mask +#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask +#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask +#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt + // Mask +#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt + // Mask +#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask +#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask +#define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem + // Interrupt Mask +#define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem + // Interrupt Mask +#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem + // Interrupt Mask +#define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem + // Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_RIS register. +// +//***************************************************************************** +#define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status +#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt + // Status +#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt + // Status +#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt + // Status +#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt + // Status +#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw + // Interrupt Status +#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt + // Status +#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt + // Status +#define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw + // Interrupt Status +#define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect Modem + // Raw Interrupt Status +#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw + // Interrupt Status +#define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_MIS register. +// +//***************************************************************************** +#define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt + // Status +#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked + // Interrupt Status +#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked + // Interrupt Status +#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked + // Interrupt Status +#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked + // Interrupt Status +#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked + // Interrupt Status +#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt + // Status +#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt + // Status +#define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked + // Interrupt Status +#define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect Modem + // Masked Interrupt Status +#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked + // Interrupt Status +#define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ICR register. +// +//***************************************************************************** +#define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear +#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear +#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear +#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear +#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear +#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear +#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear +#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear +#define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem + // Interrupt Clear +#define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect Modem + // Interrupt Clear +#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem + // Interrupt Clear +#define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem + // Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_DMACTL register. +// +//***************************************************************************** +#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error +#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable +#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_9BITADDR +// register. +// +//***************************************************************************** +#define UART_9BITADDR_9BITEN 0x00008000 // Enable 9-Bit Mode +#define UART_9BITADDR_ADDR_M 0x000000FF // Self Address for 9-Bit Mode +#define UART_9BITADDR_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_9BITAMASK +// register. +// +//***************************************************************************** +#define UART_9BITAMASK_MASK_M 0x000000FF // Self Address Mask for 9-Bit Mode +#define UART_9BITAMASK_MASK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_PP register. +// +//***************************************************************************** +#define UART_PP_NB 0x00000002 // 9-Bit Support +#define UART_PP_SC 0x00000001 // Smart Card Support + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_CC register. +// +//***************************************************************************** +#define UART_CC_CS_M 0x0000000F // UART Baud Clock Source +#define UART_CC_CS_SYSCLK 0x00000000 // System clock (based on clock + // source and divisor factor) +#define UART_CC_CS_PIOSC 0x00000005 // PIOSC + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MSA register. +// +//***************************************************************************** +#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address +#define I2C_MSA_RS 0x00000001 // Receive not send +#define I2C_MSA_SA_S 1 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCS register. +// +//***************************************************************************** +#define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error +#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy +#define I2C_MCS_IDLE 0x00000020 // I2C Idle +#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost +#define I2C_MCS_HS 0x00000010 // High-Speed Enable +#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable +#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data +#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address +#define I2C_MCS_STOP 0x00000004 // Generate STOP +#define I2C_MCS_ERROR 0x00000002 // Error +#define I2C_MCS_START 0x00000002 // Generate START +#define I2C_MCS_RUN 0x00000001 // I2C Master Enable +#define I2C_MCS_BUSY 0x00000001 // I2C Busy + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MDR register. +// +//***************************************************************************** +#define I2C_MDR_DATA_M 0x000000FF // This byte contains the data + // transferred during a transaction +#define I2C_MDR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MTPR register. +// +//***************************************************************************** +#define I2C_MTPR_HS 0x00000080 // High-Speed Enable +#define I2C_MTPR_TPR_M 0x0000007F // Timer Period +#define I2C_MTPR_TPR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MIMR register. +// +//***************************************************************************** +#define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask +#define I2C_MIMR_IM 0x00000001 // Master Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MRIS register. +// +//***************************************************************************** +#define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt + // Status +#define I2C_MRIS_RIS 0x00000001 // Master Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MMIS register. +// +//***************************************************************************** +#define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt + // Status +#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MICR register. +// +//***************************************************************************** +#define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear +#define I2C_MICR_IC 0x00000001 // Master Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCR register. +// +//***************************************************************************** +#define I2C_MCR_GFE 0x00000040 // I2C Glitch Filter Enable +#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable +#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable +#define I2C_MCR_LPBK 0x00000001 // I2C Loopback + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCLKOCNT register. +// +//***************************************************************************** +#define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count +#define I2C_MCLKOCNT_CNTL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MBMON register. +// +//***************************************************************************** +#define I2C_MBMON_SDA 0x00000002 // I2C SDA Status +#define I2C_MBMON_SCL 0x00000001 // I2C SCL Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCR2 register. +// +//***************************************************************************** +#define I2C_MCR2_GFPW_M 0x00000070 // I2C Glitch Filter Pulse Width +#define I2C_MCR2_GFPW_BYPASS 0x00000000 // Bypass +#define I2C_MCR2_GFPW_1 0x00000010 // 1 clock +#define I2C_MCR2_GFPW_2 0x00000020 // 2 clocks +#define I2C_MCR2_GFPW_3 0x00000030 // 3 clocks +#define I2C_MCR2_GFPW_4 0x00000040 // 4 clocks +#define I2C_MCR2_GFPW_8 0x00000050 // 8 clocks +#define I2C_MCR2_GFPW_16 0x00000060 // 16 clocks +#define I2C_MCR2_GFPW_31 0x00000070 // 31 clocks + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SOAR register. +// +//***************************************************************************** +#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address +#define I2C_SOAR_OAR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SCSR register. +// +//***************************************************************************** +#define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched +#define I2C_SCSR_FBR 0x00000004 // First Byte Received +#define I2C_SCSR_TREQ 0x00000002 // Transmit Request +#define I2C_SCSR_DA 0x00000001 // Device Active +#define I2C_SCSR_RREQ 0x00000001 // Receive Request + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SDR register. +// +//***************************************************************************** +#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer +#define I2C_SDR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SIMR register. +// +//***************************************************************************** +#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask +#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask +#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SRIS register. +// +//***************************************************************************** +#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt + // Status +#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt + // Status +#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SMIS register. +// +//***************************************************************************** +#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt + // Status +#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt + // Status +#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SICR register. +// +//***************************************************************************** +#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear +#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear +#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SOAR2 register. +// +//***************************************************************************** +#define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable +#define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2 +#define I2C_SOAR2_OAR2_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SACKCTL register. +// +//***************************************************************************** +#define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value +#define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_PP register. +// +//***************************************************************************** +#define I2C_PP_HS 0x00000001 // High-Speed Capable + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_PC register. +// +//***************************************************************************** +#define I2C_PC_HS 0x00000001 // High-Speed Capable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_CTL register. +// +//***************************************************************************** +#define PWM_CTL_GLOBALSYNC3 0x00000008 // Update PWM Generator 3 +#define PWM_CTL_GLOBALSYNC2 0x00000004 // Update PWM Generator 2 +#define PWM_CTL_GLOBALSYNC1 0x00000002 // Update PWM Generator 1 +#define PWM_CTL_GLOBALSYNC0 0x00000001 // Update PWM Generator 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_SYNC register. +// +//***************************************************************************** +#define PWM_SYNC_SYNC3 0x00000008 // Reset Generator 3 Counter +#define PWM_SYNC_SYNC2 0x00000004 // Reset Generator 2 Counter +#define PWM_SYNC_SYNC1 0x00000002 // Reset Generator 1 Counter +#define PWM_SYNC_SYNC0 0x00000001 // Reset Generator 0 Counter + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_ENABLE register. +// +//***************************************************************************** +#define PWM_ENABLE_PWM7EN 0x00000080 // MnPWM7 Output Enable +#define PWM_ENABLE_PWM6EN 0x00000040 // MnPWM6 Output Enable +#define PWM_ENABLE_PWM5EN 0x00000020 // MnPWM5 Output Enable +#define PWM_ENABLE_PWM4EN 0x00000010 // MnPWM4 Output Enable +#define PWM_ENABLE_PWM3EN 0x00000008 // MnPWM3 Output Enable +#define PWM_ENABLE_PWM2EN 0x00000004 // MnPWM2 Output Enable +#define PWM_ENABLE_PWM1EN 0x00000002 // MnPWM1 Output Enable +#define PWM_ENABLE_PWM0EN 0x00000001 // MnPWM0 Output Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_INVERT register. +// +//***************************************************************************** +#define PWM_INVERT_PWM7INV 0x00000080 // Invert MnPWM7 Signal +#define PWM_INVERT_PWM6INV 0x00000040 // Invert MnPWM6 Signal +#define PWM_INVERT_PWM5INV 0x00000020 // Invert MnPWM5 Signal +#define PWM_INVERT_PWM4INV 0x00000010 // Invert MnPWM4 Signal +#define PWM_INVERT_PWM3INV 0x00000008 // Invert MnPWM3 Signal +#define PWM_INVERT_PWM2INV 0x00000004 // Invert MnPWM2 Signal +#define PWM_INVERT_PWM1INV 0x00000002 // Invert MnPWM1 Signal +#define PWM_INVERT_PWM0INV 0x00000001 // Invert MnPWM0 Signal + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_FAULT register. +// +//***************************************************************************** +#define PWM_FAULT_FAULT7 0x00000080 // MnPWM7 Fault +#define PWM_FAULT_FAULT6 0x00000040 // MnPWM6 Fault +#define PWM_FAULT_FAULT5 0x00000020 // MnPWM5 Fault +#define PWM_FAULT_FAULT4 0x00000010 // MnPWM4 Fault +#define PWM_FAULT_FAULT3 0x00000008 // MnPWM3 Fault +#define PWM_FAULT_FAULT2 0x00000004 // MnPWM2 Fault +#define PWM_FAULT_FAULT1 0x00000002 // MnPWM1 Fault +#define PWM_FAULT_FAULT0 0x00000001 // MnPWM0 Fault + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_INTEN register. +// +//***************************************************************************** +#define PWM_INTEN_INTFAULT3 0x00080000 // Interrupt Fault 3 +#define PWM_INTEN_INTFAULT2 0x00040000 // Interrupt Fault 2 +#define PWM_INTEN_INTFAULT1 0x00020000 // Interrupt Fault 1 +#define PWM_INTEN_INTFAULT0 0x00010000 // Interrupt Fault 0 +#define PWM_INTEN_INTPWM3 0x00000008 // PWM3 Interrupt Enable +#define PWM_INTEN_INTPWM2 0x00000004 // PWM2 Interrupt Enable +#define PWM_INTEN_INTPWM1 0x00000002 // PWM1 Interrupt Enable +#define PWM_INTEN_INTPWM0 0x00000001 // PWM0 Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_RIS register. +// +//***************************************************************************** +#define PWM_RIS_INTFAULT3 0x00080000 // Interrupt Fault PWM 3 +#define PWM_RIS_INTFAULT2 0x00040000 // Interrupt Fault PWM 2 +#define PWM_RIS_INTFAULT1 0x00020000 // Interrupt Fault PWM 1 +#define PWM_RIS_INTFAULT0 0x00010000 // Interrupt Fault PWM 0 +#define PWM_RIS_INTPWM3 0x00000008 // PWM3 Interrupt Asserted +#define PWM_RIS_INTPWM2 0x00000004 // PWM2 Interrupt Asserted +#define PWM_RIS_INTPWM1 0x00000002 // PWM1 Interrupt Asserted +#define PWM_RIS_INTPWM0 0x00000001 // PWM0 Interrupt Asserted + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_ISC register. +// +//***************************************************************************** +#define PWM_ISC_INTFAULT3 0x00080000 // FAULT3 Interrupt Asserted +#define PWM_ISC_INTFAULT2 0x00040000 // FAULT2 Interrupt Asserted +#define PWM_ISC_INTFAULT1 0x00020000 // FAULT1 Interrupt Asserted +#define PWM_ISC_INTFAULT0 0x00010000 // FAULT0 Interrupt Asserted +#define PWM_ISC_INTPWM3 0x00000008 // PWM3 Interrupt Status +#define PWM_ISC_INTPWM2 0x00000004 // PWM2 Interrupt Status +#define PWM_ISC_INTPWM1 0x00000002 // PWM1 Interrupt Status +#define PWM_ISC_INTPWM0 0x00000001 // PWM0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_STATUS register. +// +//***************************************************************************** +#define PWM_STATUS_FAULT3 0x00000008 // Generator 3 Fault Status +#define PWM_STATUS_FAULT2 0x00000004 // Generator 2 Fault Status +#define PWM_STATUS_FAULT1 0x00000002 // Generator 1 Fault Status +#define PWM_STATUS_FAULT0 0x00000001 // Generator 0 Fault Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_FAULTVAL register. +// +//***************************************************************************** +#define PWM_FAULTVAL_PWM7 0x00000080 // MnPWM7 Fault Value +#define PWM_FAULTVAL_PWM6 0x00000040 // MnPWM6 Fault Value +#define PWM_FAULTVAL_PWM5 0x00000020 // MnPWM5 Fault Value +#define PWM_FAULTVAL_PWM4 0x00000010 // MnPWM4 Fault Value +#define PWM_FAULTVAL_PWM3 0x00000008 // MnPWM3 Fault Value +#define PWM_FAULTVAL_PWM2 0x00000004 // MnPWM2 Fault Value +#define PWM_FAULTVAL_PWM1 0x00000002 // MnPWM1 Fault Value +#define PWM_FAULTVAL_PWM0 0x00000001 // MnPWM0 Fault Value + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_ENUPD register. +// +//***************************************************************************** +#define PWM_ENUPD_ENUPD7_M 0x0000C000 // MnPWM7 Enable Update Mode +#define PWM_ENUPD_ENUPD7_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD7_LSYNC 0x00008000 // Locally Synchronized +#define PWM_ENUPD_ENUPD7_GSYNC 0x0000C000 // Globally Synchronized +#define PWM_ENUPD_ENUPD6_M 0x00003000 // MnPWM6 Enable Update Mode +#define PWM_ENUPD_ENUPD6_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD6_LSYNC 0x00002000 // Locally Synchronized +#define PWM_ENUPD_ENUPD6_GSYNC 0x00003000 // Globally Synchronized +#define PWM_ENUPD_ENUPD5_M 0x00000C00 // MnPWM5 Enable Update Mode +#define PWM_ENUPD_ENUPD5_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD5_LSYNC 0x00000800 // Locally Synchronized +#define PWM_ENUPD_ENUPD5_GSYNC 0x00000C00 // Globally Synchronized +#define PWM_ENUPD_ENUPD4_M 0x00000300 // MnPWM4 Enable Update Mode +#define PWM_ENUPD_ENUPD4_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD4_LSYNC 0x00000200 // Locally Synchronized +#define PWM_ENUPD_ENUPD4_GSYNC 0x00000300 // Globally Synchronized +#define PWM_ENUPD_ENUPD3_M 0x000000C0 // MnPWM3 Enable Update Mode +#define PWM_ENUPD_ENUPD3_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD3_LSYNC 0x00000080 // Locally Synchronized +#define PWM_ENUPD_ENUPD3_GSYNC 0x000000C0 // Globally Synchronized +#define PWM_ENUPD_ENUPD2_M 0x00000030 // MnPWM2 Enable Update Mode +#define PWM_ENUPD_ENUPD2_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD2_LSYNC 0x00000020 // Locally Synchronized +#define PWM_ENUPD_ENUPD2_GSYNC 0x00000030 // Globally Synchronized +#define PWM_ENUPD_ENUPD1_M 0x0000000C // MnPWM1 Enable Update Mode +#define PWM_ENUPD_ENUPD1_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD1_LSYNC 0x00000008 // Locally Synchronized +#define PWM_ENUPD_ENUPD1_GSYNC 0x0000000C // Globally Synchronized +#define PWM_ENUPD_ENUPD0_M 0x00000003 // MnPWM0 Enable Update Mode +#define PWM_ENUPD_ENUPD0_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD0_LSYNC 0x00000002 // Locally Synchronized +#define PWM_ENUPD_ENUPD0_GSYNC 0x00000003 // Globally Synchronized + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_CTL register. +// +//***************************************************************************** +#define PWM_0_CTL_LATCH 0x00040000 // Latch Fault Input +#define PWM_0_CTL_MINFLTPER 0x00020000 // Minimum Fault Period +#define PWM_0_CTL_FLTSRC 0x00010000 // Fault Condition Source +#define PWM_0_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode +#define PWM_0_CTL_DBFALLUPD_I 0x00000000 // Immediate +#define PWM_0_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized +#define PWM_0_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized +#define PWM_0_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode +#define PWM_0_CTL_DBRISEUPD_I 0x00000000 // Immediate +#define PWM_0_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized +#define PWM_0_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized +#define PWM_0_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode +#define PWM_0_CTL_DBCTLUPD_I 0x00000000 // Immediate +#define PWM_0_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized +#define PWM_0_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized +#define PWM_0_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode +#define PWM_0_CTL_GENBUPD_I 0x00000000 // Immediate +#define PWM_0_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized +#define PWM_0_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized +#define PWM_0_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode +#define PWM_0_CTL_GENAUPD_I 0x00000000 // Immediate +#define PWM_0_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized +#define PWM_0_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized +#define PWM_0_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode +#define PWM_0_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode +#define PWM_0_CTL_LOADUPD 0x00000008 // Load Register Update Mode +#define PWM_0_CTL_DEBUG 0x00000004 // Debug Mode +#define PWM_0_CTL_MODE 0x00000002 // Counter Mode +#define PWM_0_CTL_ENABLE 0x00000001 // PWM Block Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_INTEN register. +// +//***************************************************************************** +#define PWM_0_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB + // Down +#define PWM_0_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up +#define PWM_0_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA + // Down +#define PWM_0_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up +#define PWM_0_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD +#define PWM_0_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 +#define PWM_0_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB + // Down +#define PWM_0_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB + // Up +#define PWM_0_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA + // Down +#define PWM_0_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA + // Up +#define PWM_0_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD +#define PWM_0_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_RIS register. +// +//***************************************************************************** +#define PWM_0_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt + // Status +#define PWM_0_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status +#define PWM_0_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt + // Status +#define PWM_0_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status +#define PWM_0_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status +#define PWM_0_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_ISC register. +// +//***************************************************************************** +#define PWM_0_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt +#define PWM_0_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt +#define PWM_0_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt +#define PWM_0_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt +#define PWM_0_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt +#define PWM_0_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_LOAD register. +// +//***************************************************************************** +#define PWM_0_LOAD_M 0x0000FFFF // Counter Load Value +#define PWM_0_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_COUNT register. +// +//***************************************************************************** +#define PWM_0_COUNT_M 0x0000FFFF // Counter Value +#define PWM_0_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_CMPA register. +// +//***************************************************************************** +#define PWM_0_CMPA_M 0x0000FFFF // Comparator A Value +#define PWM_0_CMPA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_CMPB register. +// +//***************************************************************************** +#define PWM_0_CMPB_M 0x0000FFFF // Comparator B Value +#define PWM_0_CMPB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_GENA register. +// +//***************************************************************************** +#define PWM_0_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_0_GENA_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA +#define PWM_0_GENA_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmA Low +#define PWM_0_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High +#define PWM_0_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_0_GENA_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA +#define PWM_0_GENA_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmA Low +#define PWM_0_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High +#define PWM_0_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_0_GENA_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA +#define PWM_0_GENA_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmA Low +#define PWM_0_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High +#define PWM_0_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_0_GENA_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA +#define PWM_0_GENA_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmA Low +#define PWM_0_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High +#define PWM_0_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_0_GENA_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_0_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA +#define PWM_0_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low +#define PWM_0_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High +#define PWM_0_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_0_GENA_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_0_GENA_ACTZERO_INV 0x00000001 // Invert pwmA +#define PWM_0_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low +#define PWM_0_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_GENB register. +// +//***************************************************************************** +#define PWM_0_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_0_GENB_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB +#define PWM_0_GENB_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmB Low +#define PWM_0_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High +#define PWM_0_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_0_GENB_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB +#define PWM_0_GENB_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmB Low +#define PWM_0_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High +#define PWM_0_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_0_GENB_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB +#define PWM_0_GENB_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmB Low +#define PWM_0_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High +#define PWM_0_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_0_GENB_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB +#define PWM_0_GENB_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmB Low +#define PWM_0_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High +#define PWM_0_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_0_GENB_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_0_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB +#define PWM_0_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low +#define PWM_0_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High +#define PWM_0_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_0_GENB_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_0_GENB_ACTZERO_INV 0x00000001 // Invert pwmB +#define PWM_0_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low +#define PWM_0_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_DBCTL register. +// +//***************************************************************************** +#define PWM_0_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_DBRISE register. +// +//***************************************************************************** +#define PWM_0_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay +#define PWM_0_DBRISE_DELAY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_DBFALL register. +// +//***************************************************************************** +#define PWM_0_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay +#define PWM_0_DBFALL_DELAY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_FLTSRC0 +// register. +// +//***************************************************************************** +#define PWM_0_FLTSRC0_FAULT3 0x00000008 // Fault3 Input +#define PWM_0_FLTSRC0_FAULT2 0x00000004 // Fault2 Input +#define PWM_0_FLTSRC0_FAULT1 0x00000002 // Fault1 Input +#define PWM_0_FLTSRC0_FAULT0 0x00000001 // Fault0 Input + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_FLTSRC1 +// register. +// +//***************************************************************************** +#define PWM_0_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 +#define PWM_0_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 +#define PWM_0_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 +#define PWM_0_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 +#define PWM_0_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 +#define PWM_0_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 +#define PWM_0_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 +#define PWM_0_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_MINFLTPER +// register. +// +//***************************************************************************** +#define PWM_0_MINFLTPER_M 0x0000FFFF // Minimum Fault Period +#define PWM_0_MINFLTPER_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_CTL register. +// +//***************************************************************************** +#define PWM_1_CTL_LATCH 0x00040000 // Latch Fault Input +#define PWM_1_CTL_MINFLTPER 0x00020000 // Minimum Fault Period +#define PWM_1_CTL_FLTSRC 0x00010000 // Fault Condition Source +#define PWM_1_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode +#define PWM_1_CTL_DBFALLUPD_I 0x00000000 // Immediate +#define PWM_1_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized +#define PWM_1_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized +#define PWM_1_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode +#define PWM_1_CTL_DBRISEUPD_I 0x00000000 // Immediate +#define PWM_1_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized +#define PWM_1_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized +#define PWM_1_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode +#define PWM_1_CTL_DBCTLUPD_I 0x00000000 // Immediate +#define PWM_1_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized +#define PWM_1_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized +#define PWM_1_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode +#define PWM_1_CTL_GENBUPD_I 0x00000000 // Immediate +#define PWM_1_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized +#define PWM_1_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized +#define PWM_1_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode +#define PWM_1_CTL_GENAUPD_I 0x00000000 // Immediate +#define PWM_1_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized +#define PWM_1_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized +#define PWM_1_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode +#define PWM_1_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode +#define PWM_1_CTL_LOADUPD 0x00000008 // Load Register Update Mode +#define PWM_1_CTL_DEBUG 0x00000004 // Debug Mode +#define PWM_1_CTL_MODE 0x00000002 // Counter Mode +#define PWM_1_CTL_ENABLE 0x00000001 // PWM Block Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_INTEN register. +// +//***************************************************************************** +#define PWM_1_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB + // Down +#define PWM_1_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up +#define PWM_1_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA + // Down +#define PWM_1_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up +#define PWM_1_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD +#define PWM_1_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 +#define PWM_1_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB + // Down +#define PWM_1_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB + // Up +#define PWM_1_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA + // Down +#define PWM_1_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA + // Up +#define PWM_1_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD +#define PWM_1_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_RIS register. +// +//***************************************************************************** +#define PWM_1_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt + // Status +#define PWM_1_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status +#define PWM_1_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt + // Status +#define PWM_1_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status +#define PWM_1_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status +#define PWM_1_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_ISC register. +// +//***************************************************************************** +#define PWM_1_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt +#define PWM_1_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt +#define PWM_1_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt +#define PWM_1_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt +#define PWM_1_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt +#define PWM_1_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_LOAD register. +// +//***************************************************************************** +#define PWM_1_LOAD_LOAD_M 0x0000FFFF // Counter Load Value +#define PWM_1_LOAD_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_COUNT register. +// +//***************************************************************************** +#define PWM_1_COUNT_COUNT_M 0x0000FFFF // Counter Value +#define PWM_1_COUNT_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_CMPA register. +// +//***************************************************************************** +#define PWM_1_CMPA_COMPA_M 0x0000FFFF // Comparator A Value +#define PWM_1_CMPA_COMPA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_CMPB register. +// +//***************************************************************************** +#define PWM_1_CMPB_COMPB_M 0x0000FFFF // Comparator B Value +#define PWM_1_CMPB_COMPB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_GENA register. +// +//***************************************************************************** +#define PWM_1_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_1_GENA_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA +#define PWM_1_GENA_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmA Low +#define PWM_1_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High +#define PWM_1_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_1_GENA_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA +#define PWM_1_GENA_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmA Low +#define PWM_1_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High +#define PWM_1_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_1_GENA_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA +#define PWM_1_GENA_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmA Low +#define PWM_1_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High +#define PWM_1_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_1_GENA_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA +#define PWM_1_GENA_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmA Low +#define PWM_1_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High +#define PWM_1_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_1_GENA_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_1_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA +#define PWM_1_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low +#define PWM_1_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High +#define PWM_1_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_1_GENA_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_1_GENA_ACTZERO_INV 0x00000001 // Invert pwmA +#define PWM_1_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low +#define PWM_1_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_GENB register. +// +//***************************************************************************** +#define PWM_1_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_1_GENB_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB +#define PWM_1_GENB_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmB Low +#define PWM_1_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High +#define PWM_1_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_1_GENB_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB +#define PWM_1_GENB_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmB Low +#define PWM_1_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High +#define PWM_1_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_1_GENB_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB +#define PWM_1_GENB_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmB Low +#define PWM_1_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High +#define PWM_1_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_1_GENB_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB +#define PWM_1_GENB_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmB Low +#define PWM_1_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High +#define PWM_1_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_1_GENB_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_1_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB +#define PWM_1_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low +#define PWM_1_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High +#define PWM_1_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_1_GENB_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_1_GENB_ACTZERO_INV 0x00000001 // Invert pwmB +#define PWM_1_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low +#define PWM_1_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_DBCTL register. +// +//***************************************************************************** +#define PWM_1_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_DBRISE register. +// +//***************************************************************************** +#define PWM_1_DBRISE_RISEDELAY_M \ + 0x00000FFF // Dead-Band Rise Delay +#define PWM_1_DBRISE_RISEDELAY_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_DBFALL register. +// +//***************************************************************************** +#define PWM_1_DBFALL_FALLDELAY_M \ + 0x00000FFF // Dead-Band Fall Delay +#define PWM_1_DBFALL_FALLDELAY_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_FLTSRC0 +// register. +// +//***************************************************************************** +#define PWM_1_FLTSRC0_FAULT3 0x00000008 // Fault3 Input +#define PWM_1_FLTSRC0_FAULT2 0x00000004 // Fault2 Input +#define PWM_1_FLTSRC0_FAULT1 0x00000002 // Fault1 Input +#define PWM_1_FLTSRC0_FAULT0 0x00000001 // Fault0 Input + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_FLTSRC1 +// register. +// +//***************************************************************************** +#define PWM_1_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 +#define PWM_1_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 +#define PWM_1_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 +#define PWM_1_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 +#define PWM_1_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 +#define PWM_1_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 +#define PWM_1_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 +#define PWM_1_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_MINFLTPER +// register. +// +//***************************************************************************** +#define PWM_1_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period +#define PWM_1_MINFLTPER_MFP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_CTL register. +// +//***************************************************************************** +#define PWM_2_CTL_LATCH 0x00040000 // Latch Fault Input +#define PWM_2_CTL_MINFLTPER 0x00020000 // Minimum Fault Period +#define PWM_2_CTL_FLTSRC 0x00010000 // Fault Condition Source +#define PWM_2_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode +#define PWM_2_CTL_DBFALLUPD_I 0x00000000 // Immediate +#define PWM_2_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized +#define PWM_2_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized +#define PWM_2_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode +#define PWM_2_CTL_DBRISEUPD_I 0x00000000 // Immediate +#define PWM_2_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized +#define PWM_2_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized +#define PWM_2_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode +#define PWM_2_CTL_DBCTLUPD_I 0x00000000 // Immediate +#define PWM_2_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized +#define PWM_2_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized +#define PWM_2_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode +#define PWM_2_CTL_GENBUPD_I 0x00000000 // Immediate +#define PWM_2_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized +#define PWM_2_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized +#define PWM_2_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode +#define PWM_2_CTL_GENAUPD_I 0x00000000 // Immediate +#define PWM_2_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized +#define PWM_2_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized +#define PWM_2_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode +#define PWM_2_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode +#define PWM_2_CTL_LOADUPD 0x00000008 // Load Register Update Mode +#define PWM_2_CTL_DEBUG 0x00000004 // Debug Mode +#define PWM_2_CTL_MODE 0x00000002 // Counter Mode +#define PWM_2_CTL_ENABLE 0x00000001 // PWM Block Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_INTEN register. +// +//***************************************************************************** +#define PWM_2_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB + // Down +#define PWM_2_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up +#define PWM_2_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA + // Down +#define PWM_2_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up +#define PWM_2_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD +#define PWM_2_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 +#define PWM_2_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB + // Down +#define PWM_2_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB + // Up +#define PWM_2_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA + // Down +#define PWM_2_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA + // Up +#define PWM_2_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD +#define PWM_2_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_RIS register. +// +//***************************************************************************** +#define PWM_2_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt + // Status +#define PWM_2_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status +#define PWM_2_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt + // Status +#define PWM_2_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status +#define PWM_2_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status +#define PWM_2_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_ISC register. +// +//***************************************************************************** +#define PWM_2_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt +#define PWM_2_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt +#define PWM_2_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt +#define PWM_2_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt +#define PWM_2_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt +#define PWM_2_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_LOAD register. +// +//***************************************************************************** +#define PWM_2_LOAD_LOAD_M 0x0000FFFF // Counter Load Value +#define PWM_2_LOAD_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_COUNT register. +// +//***************************************************************************** +#define PWM_2_COUNT_COUNT_M 0x0000FFFF // Counter Value +#define PWM_2_COUNT_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_CMPA register. +// +//***************************************************************************** +#define PWM_2_CMPA_COMPA_M 0x0000FFFF // Comparator A Value +#define PWM_2_CMPA_COMPA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_CMPB register. +// +//***************************************************************************** +#define PWM_2_CMPB_COMPB_M 0x0000FFFF // Comparator B Value +#define PWM_2_CMPB_COMPB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_GENA register. +// +//***************************************************************************** +#define PWM_2_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_2_GENA_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA +#define PWM_2_GENA_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmA Low +#define PWM_2_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High +#define PWM_2_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_2_GENA_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA +#define PWM_2_GENA_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmA Low +#define PWM_2_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High +#define PWM_2_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_2_GENA_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA +#define PWM_2_GENA_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmA Low +#define PWM_2_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High +#define PWM_2_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_2_GENA_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA +#define PWM_2_GENA_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmA Low +#define PWM_2_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High +#define PWM_2_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_2_GENA_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_2_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA +#define PWM_2_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low +#define PWM_2_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High +#define PWM_2_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_2_GENA_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_2_GENA_ACTZERO_INV 0x00000001 // Invert pwmA +#define PWM_2_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low +#define PWM_2_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_GENB register. +// +//***************************************************************************** +#define PWM_2_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_2_GENB_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB +#define PWM_2_GENB_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmB Low +#define PWM_2_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High +#define PWM_2_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_2_GENB_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB +#define PWM_2_GENB_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmB Low +#define PWM_2_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High +#define PWM_2_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_2_GENB_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB +#define PWM_2_GENB_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmB Low +#define PWM_2_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High +#define PWM_2_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_2_GENB_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB +#define PWM_2_GENB_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmB Low +#define PWM_2_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High +#define PWM_2_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_2_GENB_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_2_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB +#define PWM_2_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low +#define PWM_2_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High +#define PWM_2_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_2_GENB_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_2_GENB_ACTZERO_INV 0x00000001 // Invert pwmB +#define PWM_2_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low +#define PWM_2_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_DBCTL register. +// +//***************************************************************************** +#define PWM_2_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_DBRISE register. +// +//***************************************************************************** +#define PWM_2_DBRISE_RISEDELAY_M \ + 0x00000FFF // Dead-Band Rise Delay +#define PWM_2_DBRISE_RISEDELAY_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_DBFALL register. +// +//***************************************************************************** +#define PWM_2_DBFALL_FALLDELAY_M \ + 0x00000FFF // Dead-Band Fall Delay +#define PWM_2_DBFALL_FALLDELAY_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_FLTSRC0 +// register. +// +//***************************************************************************** +#define PWM_2_FLTSRC0_FAULT3 0x00000008 // Fault3 Input +#define PWM_2_FLTSRC0_FAULT2 0x00000004 // Fault2 Input +#define PWM_2_FLTSRC0_FAULT1 0x00000002 // Fault1 Input +#define PWM_2_FLTSRC0_FAULT0 0x00000001 // Fault0 Input + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_FLTSRC1 +// register. +// +//***************************************************************************** +#define PWM_2_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 +#define PWM_2_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 +#define PWM_2_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 +#define PWM_2_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 +#define PWM_2_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 +#define PWM_2_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 +#define PWM_2_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 +#define PWM_2_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_MINFLTPER +// register. +// +//***************************************************************************** +#define PWM_2_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period +#define PWM_2_MINFLTPER_MFP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_CTL register. +// +//***************************************************************************** +#define PWM_3_CTL_LATCH 0x00040000 // Latch Fault Input +#define PWM_3_CTL_MINFLTPER 0x00020000 // Minimum Fault Period +#define PWM_3_CTL_FLTSRC 0x00010000 // Fault Condition Source +#define PWM_3_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode +#define PWM_3_CTL_DBFALLUPD_I 0x00000000 // Immediate +#define PWM_3_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized +#define PWM_3_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized +#define PWM_3_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode +#define PWM_3_CTL_DBRISEUPD_I 0x00000000 // Immediate +#define PWM_3_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized +#define PWM_3_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized +#define PWM_3_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode +#define PWM_3_CTL_DBCTLUPD_I 0x00000000 // Immediate +#define PWM_3_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized +#define PWM_3_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized +#define PWM_3_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode +#define PWM_3_CTL_GENBUPD_I 0x00000000 // Immediate +#define PWM_3_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized +#define PWM_3_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized +#define PWM_3_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode +#define PWM_3_CTL_GENAUPD_I 0x00000000 // Immediate +#define PWM_3_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized +#define PWM_3_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized +#define PWM_3_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode +#define PWM_3_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode +#define PWM_3_CTL_LOADUPD 0x00000008 // Load Register Update Mode +#define PWM_3_CTL_DEBUG 0x00000004 // Debug Mode +#define PWM_3_CTL_MODE 0x00000002 // Counter Mode +#define PWM_3_CTL_ENABLE 0x00000001 // PWM Block Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_INTEN register. +// +//***************************************************************************** +#define PWM_3_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB + // Down +#define PWM_3_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up +#define PWM_3_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA + // Down +#define PWM_3_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up +#define PWM_3_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD +#define PWM_3_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 +#define PWM_3_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB + // Down +#define PWM_3_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB + // Up +#define PWM_3_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA + // Down +#define PWM_3_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA + // Up +#define PWM_3_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD +#define PWM_3_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_RIS register. +// +//***************************************************************************** +#define PWM_3_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt + // Status +#define PWM_3_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status +#define PWM_3_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt + // Status +#define PWM_3_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status +#define PWM_3_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status +#define PWM_3_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_ISC register. +// +//***************************************************************************** +#define PWM_3_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt +#define PWM_3_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt +#define PWM_3_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt +#define PWM_3_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt +#define PWM_3_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt +#define PWM_3_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_LOAD register. +// +//***************************************************************************** +#define PWM_3_LOAD_LOAD_M 0x0000FFFF // Counter Load Value +#define PWM_3_LOAD_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_COUNT register. +// +//***************************************************************************** +#define PWM_3_COUNT_COUNT_M 0x0000FFFF // Counter Value +#define PWM_3_COUNT_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_CMPA register. +// +//***************************************************************************** +#define PWM_3_CMPA_COMPA_M 0x0000FFFF // Comparator A Value +#define PWM_3_CMPA_COMPA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_CMPB register. +// +//***************************************************************************** +#define PWM_3_CMPB_COMPB_M 0x0000FFFF // Comparator B Value +#define PWM_3_CMPB_COMPB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_GENA register. +// +//***************************************************************************** +#define PWM_3_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_3_GENA_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA +#define PWM_3_GENA_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmA Low +#define PWM_3_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High +#define PWM_3_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_3_GENA_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA +#define PWM_3_GENA_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmA Low +#define PWM_3_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High +#define PWM_3_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_3_GENA_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA +#define PWM_3_GENA_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmA Low +#define PWM_3_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High +#define PWM_3_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_3_GENA_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA +#define PWM_3_GENA_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmA Low +#define PWM_3_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High +#define PWM_3_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_3_GENA_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_3_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA +#define PWM_3_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low +#define PWM_3_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High +#define PWM_3_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_3_GENA_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_3_GENA_ACTZERO_INV 0x00000001 // Invert pwmA +#define PWM_3_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low +#define PWM_3_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_GENB register. +// +//***************************************************************************** +#define PWM_3_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_3_GENB_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB +#define PWM_3_GENB_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmB Low +#define PWM_3_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High +#define PWM_3_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_3_GENB_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB +#define PWM_3_GENB_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmB Low +#define PWM_3_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High +#define PWM_3_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_3_GENB_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB +#define PWM_3_GENB_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmB Low +#define PWM_3_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High +#define PWM_3_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_3_GENB_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB +#define PWM_3_GENB_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmB Low +#define PWM_3_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High +#define PWM_3_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_3_GENB_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_3_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB +#define PWM_3_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low +#define PWM_3_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High +#define PWM_3_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_3_GENB_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_3_GENB_ACTZERO_INV 0x00000001 // Invert pwmB +#define PWM_3_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low +#define PWM_3_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_DBCTL register. +// +//***************************************************************************** +#define PWM_3_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_DBRISE register. +// +//***************************************************************************** +#define PWM_3_DBRISE_RISEDELAY_M \ + 0x00000FFF // Dead-Band Rise Delay +#define PWM_3_DBRISE_RISEDELAY_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_DBFALL register. +// +//***************************************************************************** +#define PWM_3_DBFALL_FALLDELAY_M \ + 0x00000FFF // Dead-Band Fall Delay +#define PWM_3_DBFALL_FALLDELAY_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_FLTSRC0 +// register. +// +//***************************************************************************** +#define PWM_3_FLTSRC0_FAULT3 0x00000008 // Fault3 Input +#define PWM_3_FLTSRC0_FAULT2 0x00000004 // Fault2 Input +#define PWM_3_FLTSRC0_FAULT1 0x00000002 // Fault1 Input +#define PWM_3_FLTSRC0_FAULT0 0x00000001 // Fault0 Input + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_FLTSRC1 +// register. +// +//***************************************************************************** +#define PWM_3_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 +#define PWM_3_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 +#define PWM_3_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 +#define PWM_3_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 +#define PWM_3_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 +#define PWM_3_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 +#define PWM_3_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 +#define PWM_3_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_MINFLTPER +// register. +// +//***************************************************************************** +#define PWM_3_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period +#define PWM_3_MINFLTPER_MFP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_FLTSEN register. +// +//***************************************************************************** +#define PWM_0_FLTSEN_FAULT3 0x00000008 // Fault3 Sense +#define PWM_0_FLTSEN_FAULT2 0x00000004 // Fault2 Sense +#define PWM_0_FLTSEN_FAULT1 0x00000002 // Fault1 Sense +#define PWM_0_FLTSEN_FAULT0 0x00000001 // Fault0 Sense + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_FLTSTAT0 +// register. +// +//***************************************************************************** +#define PWM_0_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 +#define PWM_0_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 +#define PWM_0_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 +#define PWM_0_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_FLTSTAT1 +// register. +// +//***************************************************************************** +#define PWM_0_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger +#define PWM_0_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger +#define PWM_0_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger +#define PWM_0_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger +#define PWM_0_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger +#define PWM_0_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger +#define PWM_0_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger +#define PWM_0_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_FLTSEN register. +// +//***************************************************************************** +#define PWM_1_FLTSEN_FAULT3 0x00000008 // Fault3 Sense +#define PWM_1_FLTSEN_FAULT2 0x00000004 // Fault2 Sense +#define PWM_1_FLTSEN_FAULT1 0x00000002 // Fault1 Sense +#define PWM_1_FLTSEN_FAULT0 0x00000001 // Fault0 Sense + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_FLTSTAT0 +// register. +// +//***************************************************************************** +#define PWM_1_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 +#define PWM_1_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 +#define PWM_1_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 +#define PWM_1_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_FLTSTAT1 +// register. +// +//***************************************************************************** +#define PWM_1_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger +#define PWM_1_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger +#define PWM_1_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger +#define PWM_1_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger +#define PWM_1_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger +#define PWM_1_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger +#define PWM_1_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger +#define PWM_1_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_FLTSEN register. +// +//***************************************************************************** +#define PWM_2_FLTSEN_FAULT3 0x00000008 // Fault3 Sense +#define PWM_2_FLTSEN_FAULT2 0x00000004 // Fault2 Sense +#define PWM_2_FLTSEN_FAULT1 0x00000002 // Fault1 Sense +#define PWM_2_FLTSEN_FAULT0 0x00000001 // Fault0 Sense + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_FLTSTAT0 +// register. +// +//***************************************************************************** +#define PWM_2_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 +#define PWM_2_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 +#define PWM_2_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 +#define PWM_2_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_FLTSTAT1 +// register. +// +//***************************************************************************** +#define PWM_2_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger +#define PWM_2_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger +#define PWM_2_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger +#define PWM_2_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger +#define PWM_2_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger +#define PWM_2_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger +#define PWM_2_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger +#define PWM_2_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_FLTSEN register. +// +//***************************************************************************** +#define PWM_3_FLTSEN_FAULT3 0x00000008 // Fault3 Sense +#define PWM_3_FLTSEN_FAULT2 0x00000004 // Fault2 Sense +#define PWM_3_FLTSEN_FAULT1 0x00000002 // Fault1 Sense +#define PWM_3_FLTSEN_FAULT0 0x00000001 // Fault0 Sense + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_FLTSTAT0 +// register. +// +//***************************************************************************** +#define PWM_3_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 +#define PWM_3_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 +#define PWM_3_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 +#define PWM_3_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_FLTSTAT1 +// register. +// +//***************************************************************************** +#define PWM_3_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger +#define PWM_3_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger +#define PWM_3_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger +#define PWM_3_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger +#define PWM_3_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger +#define PWM_3_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger +#define PWM_3_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger +#define PWM_3_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_PP register. +// +//***************************************************************************** +#define PWM_PP_ONE 0x00000400 // One-Shot Mode +#define PWM_PP_EFAULT 0x00000200 // Extended Fault +#define PWM_PP_ESYNC 0x00000100 // Extended Synchronization +#define PWM_PP_FCNT_M 0x000000F0 // Fault Inputs (per PWM unit) +#define PWM_PP_GCNT_M 0x0000000F // Generators +#define PWM_PP_FCNT_S 4 +#define PWM_PP_GCNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_CTL register. +// +//***************************************************************************** +#define QEI_CTL_FILTCNT_M 0x000F0000 // Input Filter Prescale Count +#define QEI_CTL_FILTEN 0x00002000 // Enable Input Filter +#define QEI_CTL_STALLEN 0x00001000 // Stall QEI +#define QEI_CTL_INVI 0x00000800 // Invert Index Pulse +#define QEI_CTL_INVB 0x00000400 // Invert PhB +#define QEI_CTL_INVA 0x00000200 // Invert PhA +#define QEI_CTL_VELDIV_M 0x000001C0 // Predivide Velocity +#define QEI_CTL_VELDIV_1 0x00000000 // QEI clock /1 +#define QEI_CTL_VELDIV_2 0x00000040 // QEI clock /2 +#define QEI_CTL_VELDIV_4 0x00000080 // QEI clock /4 +#define QEI_CTL_VELDIV_8 0x000000C0 // QEI clock /8 +#define QEI_CTL_VELDIV_16 0x00000100 // QEI clock /16 +#define QEI_CTL_VELDIV_32 0x00000140 // QEI clock /32 +#define QEI_CTL_VELDIV_64 0x00000180 // QEI clock /64 +#define QEI_CTL_VELDIV_128 0x000001C0 // QEI clock /128 +#define QEI_CTL_VELEN 0x00000020 // Capture Velocity +#define QEI_CTL_RESMODE 0x00000010 // Reset Mode +#define QEI_CTL_CAPMODE 0x00000008 // Capture Mode +#define QEI_CTL_SIGMODE 0x00000004 // Signal Mode +#define QEI_CTL_SWAP 0x00000002 // Swap Signals +#define QEI_CTL_ENABLE 0x00000001 // Enable QEI +#define QEI_CTL_FILTCNT_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_STAT register. +// +//***************************************************************************** +#define QEI_STAT_DIRECTION 0x00000002 // Direction of Rotation +#define QEI_STAT_ERROR 0x00000001 // Error Detected + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_POS register. +// +//***************************************************************************** +#define QEI_POS_M 0xFFFFFFFF // Current Position Integrator + // Value +#define QEI_POS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_MAXPOS register. +// +//***************************************************************************** +#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum Position Integrator + // Value +#define QEI_MAXPOS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_LOAD register. +// +//***************************************************************************** +#define QEI_LOAD_M 0xFFFFFFFF // Velocity Timer Load Value +#define QEI_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_TIME register. +// +//***************************************************************************** +#define QEI_TIME_M 0xFFFFFFFF // Velocity Timer Current Value +#define QEI_TIME_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_COUNT register. +// +//***************************************************************************** +#define QEI_COUNT_M 0xFFFFFFFF // Velocity Pulse Count +#define QEI_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_SPEED register. +// +//***************************************************************************** +#define QEI_SPEED_M 0xFFFFFFFF // Velocity +#define QEI_SPEED_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_INTEN register. +// +//***************************************************************************** +#define QEI_INTEN_ERROR 0x00000008 // Phase Error Interrupt Enable +#define QEI_INTEN_DIR 0x00000004 // Direction Change Interrupt + // Enable +#define QEI_INTEN_TIMER 0x00000002 // Timer Expires Interrupt Enable +#define QEI_INTEN_INDEX 0x00000001 // Index Pulse Detected Interrupt + // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_RIS register. +// +//***************************************************************************** +#define QEI_RIS_ERROR 0x00000008 // Phase Error Detected +#define QEI_RIS_DIR 0x00000004 // Direction Change Detected +#define QEI_RIS_TIMER 0x00000002 // Velocity Timer Expired +#define QEI_RIS_INDEX 0x00000001 // Index Pulse Asserted + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_ISC register. +// +//***************************************************************************** +#define QEI_ISC_ERROR 0x00000008 // Phase Error Interrupt +#define QEI_ISC_DIR 0x00000004 // Direction Change Interrupt +#define QEI_ISC_TIMER 0x00000002 // Velocity Timer Expired Interrupt +#define QEI_ISC_INDEX 0x00000001 // Index Pulse Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_CFG register. +// +//***************************************************************************** +#define TIMER_CFG_M 0x00000007 // GPTM Configuration +#define TIMER_CFG_32_BIT_TIMER 0x00000000 // For a 16/32-bit timer, this + // value selects the 32-bit timer + // configuration +#define TIMER_CFG_32_BIT_RTC 0x00000001 // For a 16/32-bit timer, this + // value selects the 32-bit + // real-time clock (RTC) counter + // configuration +#define TIMER_CFG_16_BIT 0x00000004 // For a 16/32-bit timer, this + // value selects the 16-bit timer + // configuration + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAMR register. +// +//***************************************************************************** +#define TIMER_TAMR_TAPLO 0x00000800 // GPTM Timer A PWM Legacy + // Operation +#define TIMER_TAMR_TAMRSU 0x00000400 // GPTM Timer A Match Register + // Update +#define TIMER_TAMR_TAPWMIE 0x00000200 // GPTM Timer A PWM Interrupt + // Enable +#define TIMER_TAMR_TAILD 0x00000100 // GPTM Timer A Interval Load Write +#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode +#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger +#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt + // Enable +#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction +#define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode + // Select +#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode +#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode +#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode +#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode +#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBMR register. +// +//***************************************************************************** +#define TIMER_TBMR_TBPLO 0x00000800 // GPTM Timer B PWM Legacy + // Operation +#define TIMER_TBMR_TBMRSU 0x00000400 // GPTM Timer B Match Register + // Update +#define TIMER_TBMR_TBPWMIE 0x00000200 // GPTM Timer B PWM Interrupt + // Enable +#define TIMER_TBMR_TBILD 0x00000100 // GPTM Timer B Interval Load Write +#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode +#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger +#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt + // Enable +#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction +#define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode + // Select +#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode +#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode +#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode +#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode +#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_CTL register. +// +//***************************************************************************** +#define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level +#define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger + // Enable +#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode +#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge +#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge +#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges +#define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable +#define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable +#define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level +#define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger + // Enable +#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Stall Enable +#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode +#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge +#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge +#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges +#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable +#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_SYNC register. +// +//***************************************************************************** +#define TIMER_SYNC_SYNCWT5_M 0x00C00000 // Synchronize GPTM 32/64-Bit Timer + // 5 +#define TIMER_SYNC_SYNCWT5_NONE 0x00000000 // GPTM 32/64-Bit Timer 5 is not + // affected +#define TIMER_SYNC_SYNCWT5_TA 0x00400000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 5 is + // triggered +#define TIMER_SYNC_SYNCWT5_TB 0x00800000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 5 is + // triggered +#define TIMER_SYNC_SYNCWT5_TATB 0x00C00000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 5 is triggered +#define TIMER_SYNC_SYNCWT4_M 0x00300000 // Synchronize GPTM 32/64-Bit Timer + // 4 +#define TIMER_SYNC_SYNCWT4_NONE 0x00000000 // GPTM 32/64-Bit Timer 4 is not + // affected +#define TIMER_SYNC_SYNCWT4_TA 0x00100000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 4 is + // triggered +#define TIMER_SYNC_SYNCWT4_TB 0x00200000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 4 is + // triggered +#define TIMER_SYNC_SYNCWT4_TATB 0x00300000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 4 is triggered +#define TIMER_SYNC_SYNCWT3_M 0x000C0000 // Synchronize GPTM 32/64-Bit Timer + // 3 +#define TIMER_SYNC_SYNCWT3_NONE 0x00000000 // GPTM 32/64-Bit Timer 3 is not + // affected +#define TIMER_SYNC_SYNCWT3_TA 0x00040000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 3 is + // triggered +#define TIMER_SYNC_SYNCWT3_TB 0x00080000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 3 is + // triggered +#define TIMER_SYNC_SYNCWT3_TATB 0x000C0000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 3 is triggered +#define TIMER_SYNC_SYNCWT2_M 0x00030000 // Synchronize GPTM 32/64-Bit Timer + // 2 +#define TIMER_SYNC_SYNCWT2_NONE 0x00000000 // GPTM 32/64-Bit Timer 2 is not + // affected +#define TIMER_SYNC_SYNCWT2_TA 0x00010000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 2 is + // triggered +#define TIMER_SYNC_SYNCWT2_TB 0x00020000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 2 is + // triggered +#define TIMER_SYNC_SYNCWT2_TATB 0x00030000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 2 is triggered +#define TIMER_SYNC_SYNCWT1_M 0x0000C000 // Synchronize GPTM 32/64-Bit Timer + // 1 +#define TIMER_SYNC_SYNCWT1_NONE 0x00000000 // GPTM 32/64-Bit Timer 1 is not + // affected +#define TIMER_SYNC_SYNCWT1_TA 0x00004000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 1 is + // triggered +#define TIMER_SYNC_SYNCWT1_TB 0x00008000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 1 is + // triggered +#define TIMER_SYNC_SYNCWT1_TATB 0x0000C000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 1 is triggered +#define TIMER_SYNC_SYNCWT0_M 0x00003000 // Synchronize GPTM 32/64-Bit Timer + // 0 +#define TIMER_SYNC_SYNCWT0_NONE 0x00000000 // GPTM 32/64-Bit Timer 0 is not + // affected +#define TIMER_SYNC_SYNCWT0_TA 0x00001000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 0 is + // triggered +#define TIMER_SYNC_SYNCWT0_TB 0x00002000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 0 is + // triggered +#define TIMER_SYNC_SYNCWT0_TATB 0x00003000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 0 is triggered +#define TIMER_SYNC_SYNCT5_M 0x00000C00 // Synchronize GPTM Timer 5 +#define TIMER_SYNC_SYNCT5_NONE 0x00000000 // GPTM5 is not affected +#define TIMER_SYNC_SYNCT5_TA 0x00000400 // A timeout event for Timer A of + // GPTM5 is triggered +#define TIMER_SYNC_SYNCT5_TB 0x00000800 // A timeout event for Timer B of + // GPTM5 is triggered +#define TIMER_SYNC_SYNCT5_TATB 0x00000C00 // A timeout event for both Timer A + // and Timer B of GPTM5 is + // triggered +#define TIMER_SYNC_SYNCT4_M 0x00000300 // Synchronize GPTM Timer 4 +#define TIMER_SYNC_SYNCT4_NONE 0x00000000 // GPTM4 is not affected +#define TIMER_SYNC_SYNCT4_TA 0x00000100 // A timeout event for Timer A of + // GPTM4 is triggered +#define TIMER_SYNC_SYNCT4_TB 0x00000200 // A timeout event for Timer B of + // GPTM4 is triggered +#define TIMER_SYNC_SYNCT4_TATB 0x00000300 // A timeout event for both Timer A + // and Timer B of GPTM4 is + // triggered +#define TIMER_SYNC_SYNCT3_M 0x000000C0 // Synchronize GPTM Timer 3 +#define TIMER_SYNC_SYNCT3_NONE 0x00000000 // GPTM3 is not affected +#define TIMER_SYNC_SYNCT3_TA 0x00000040 // A timeout event for Timer A of + // GPTM3 is triggered +#define TIMER_SYNC_SYNCT3_TB 0x00000080 // A timeout event for Timer B of + // GPTM3 is triggered +#define TIMER_SYNC_SYNCT3_TATB 0x000000C0 // A timeout event for both Timer A + // and Timer B of GPTM3 is + // triggered +#define TIMER_SYNC_SYNCT2_M 0x00000030 // Synchronize GPTM Timer 2 +#define TIMER_SYNC_SYNCT2_NONE 0x00000000 // GPTM2 is not affected +#define TIMER_SYNC_SYNCT2_TA 0x00000010 // A timeout event for Timer A of + // GPTM2 is triggered +#define TIMER_SYNC_SYNCT2_TB 0x00000020 // A timeout event for Timer B of + // GPTM2 is triggered +#define TIMER_SYNC_SYNCT2_TATB 0x00000030 // A timeout event for both Timer A + // and Timer B of GPTM2 is + // triggered +#define TIMER_SYNC_SYNCT1_M 0x0000000C // Synchronize GPTM Timer 1 +#define TIMER_SYNC_SYNCT1_NONE 0x00000000 // GPTM1 is not affected +#define TIMER_SYNC_SYNCT1_TA 0x00000004 // A timeout event for Timer A of + // GPTM1 is triggered +#define TIMER_SYNC_SYNCT1_TB 0x00000008 // A timeout event for Timer B of + // GPTM1 is triggered +#define TIMER_SYNC_SYNCT1_TATB 0x0000000C // A timeout event for both Timer A + // and Timer B of GPTM1 is + // triggered +#define TIMER_SYNC_SYNCT0_M 0x00000003 // Synchronize GPTM Timer 0 +#define TIMER_SYNC_SYNCT0_NONE 0x00000000 // GPTM0 is not affected +#define TIMER_SYNC_SYNCT0_TA 0x00000001 // A timeout event for Timer A of + // GPTM0 is triggered +#define TIMER_SYNC_SYNCT0_TB 0x00000002 // A timeout event for Timer B of + // GPTM0 is triggered +#define TIMER_SYNC_SYNCT0_TATB 0x00000003 // A timeout event for both Timer A + // and Timer B of GPTM0 is + // triggered + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_IMR register. +// +//***************************************************************************** +#define TIMER_IMR_WUEIM 0x00010000 // 32/64-Bit Wide GPTM Write Update + // Error Interrupt Mask +#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Match Interrupt + // Mask +#define TIMER_IMR_CBEIM 0x00000400 // GPTM Timer B Capture Mode Event + // Interrupt Mask +#define TIMER_IMR_CBMIM 0x00000200 // GPTM Timer B Capture Mode Match + // Interrupt Mask +#define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt + // Mask +#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Match Interrupt + // Mask +#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask +#define TIMER_IMR_CAEIM 0x00000004 // GPTM Timer A Capture Mode Event + // Interrupt Mask +#define TIMER_IMR_CAMIM 0x00000002 // GPTM Timer A Capture Mode Match + // Interrupt Mask +#define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt + // Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_RIS register. +// +//***************************************************************************** +#define TIMER_RIS_WUERIS 0x00010000 // 32/64-Bit Wide GPTM Write Update + // Error Raw Interrupt Status +#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Match Raw Interrupt +#define TIMER_RIS_CBERIS 0x00000400 // GPTM Timer B Capture Mode Event + // Raw Interrupt +#define TIMER_RIS_CBMRIS 0x00000200 // GPTM Timer B Capture Mode Match + // Raw Interrupt +#define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw + // Interrupt +#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Match Raw Interrupt +#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt +#define TIMER_RIS_CAERIS 0x00000004 // GPTM Timer A Capture Mode Event + // Raw Interrupt +#define TIMER_RIS_CAMRIS 0x00000002 // GPTM Timer A Capture Mode Match + // Raw Interrupt +#define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw + // Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_MIS register. +// +//***************************************************************************** +#define TIMER_MIS_WUEMIS 0x00010000 // 32/64-Bit Wide GPTM Write Update + // Error Masked Interrupt Status +#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Match Masked + // Interrupt +#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Timer B Capture Mode Event + // Masked Interrupt +#define TIMER_MIS_CBMMIS 0x00000200 // GPTM Timer B Capture Mode Match + // Masked Interrupt +#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked + // Interrupt +#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Match Masked + // Interrupt +#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt +#define TIMER_MIS_CAEMIS 0x00000004 // GPTM Timer A Capture Mode Event + // Masked Interrupt +#define TIMER_MIS_CAMMIS 0x00000002 // GPTM Timer A Capture Mode Match + // Masked Interrupt +#define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked + // Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_ICR register. +// +//***************************************************************************** +#define TIMER_ICR_WUECINT 0x00010000 // 32/64-Bit Wide GPTM Write Update + // Error Interrupt Clear +#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Match Interrupt + // Clear +#define TIMER_ICR_CBECINT 0x00000400 // GPTM Timer B Capture Mode Event + // Interrupt Clear +#define TIMER_ICR_CBMCINT 0x00000200 // GPTM Timer B Capture Mode Match + // Interrupt Clear +#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt + // Clear +#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Match Interrupt + // Clear +#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear +#define TIMER_ICR_CAECINT 0x00000004 // GPTM Timer A Capture Mode Event + // Interrupt Clear +#define TIMER_ICR_CAMCINT 0x00000002 // GPTM Timer A Capture Mode Match + // Interrupt Clear +#define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw + // Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAILR register. +// +//***************************************************************************** +#define TIMER_TAILR_M 0xFFFFFFFF // GPTM Timer A Interval Load + // Register +#define TIMER_TAILR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBILR register. +// +//***************************************************************************** +#define TIMER_TBILR_M 0xFFFFFFFF // GPTM Timer B Interval Load + // Register +#define TIMER_TBILR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAMATCHR +// register. +// +//***************************************************************************** +#define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF // GPTM Timer A Match Register +#define TIMER_TAMATCHR_TAMR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBMATCHR +// register. +// +//***************************************************************************** +#define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF // GPTM Timer B Match Register +#define TIMER_TBMATCHR_TBMR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPR register. +// +//***************************************************************************** +#define TIMER_TAPR_TAPSRH_M 0x0000FF00 // GPTM Timer A Prescale High Byte +#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale +#define TIMER_TAPR_TAPSRH_S 8 +#define TIMER_TAPR_TAPSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPR register. +// +//***************************************************************************** +#define TIMER_TBPR_TBPSRH_M 0x0000FF00 // GPTM Timer B Prescale High Byte +#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale +#define TIMER_TBPR_TBPSRH_S 8 +#define TIMER_TBPR_TBPSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPMR register. +// +//***************************************************************************** +#define TIMER_TAPMR_TAPSMRH_M 0x0000FF00 // GPTM Timer A Prescale Match High + // Byte +#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match +#define TIMER_TAPMR_TAPSMRH_S 8 +#define TIMER_TAPMR_TAPSMR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPMR register. +// +//***************************************************************************** +#define TIMER_TBPMR_TBPSMRH_M 0x0000FF00 // GPTM Timer B Prescale Match High + // Byte +#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match +#define TIMER_TBPMR_TBPSMRH_S 8 +#define TIMER_TBPMR_TBPSMR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAR register. +// +//***************************************************************************** +#define TIMER_TAR_M 0xFFFFFFFF // GPTM Timer A Register +#define TIMER_TAR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBR register. +// +//***************************************************************************** +#define TIMER_TBR_M 0xFFFFFFFF // GPTM Timer B Register +#define TIMER_TBR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAV register. +// +//***************************************************************************** +#define TIMER_TAV_M 0xFFFFFFFF // GPTM Timer A Value +#define TIMER_TAV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBV register. +// +//***************************************************************************** +#define TIMER_TBV_M 0xFFFFFFFF // GPTM Timer B Value +#define TIMER_TBV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_RTCPD register. +// +//***************************************************************************** +#define TIMER_RTCPD_RTCPD_M 0x0000FFFF // RTC Predivide Counter Value +#define TIMER_RTCPD_RTCPD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPS register. +// +//***************************************************************************** +#define TIMER_TAPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Snapshot +#define TIMER_TAPS_PSS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPS register. +// +//***************************************************************************** +#define TIMER_TBPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Value +#define TIMER_TBPS_PSS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPV register. +// +//***************************************************************************** +#define TIMER_TAPV_PSV_M 0x0000FFFF // GPTM Timer A Prescaler Value +#define TIMER_TAPV_PSV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPV register. +// +//***************************************************************************** +#define TIMER_TBPV_PSV_M 0x0000FFFF // GPTM Timer B Prescaler Value +#define TIMER_TBPV_PSV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_PP register. +// +//***************************************************************************** +#define TIMER_PP_SIZE_M 0x0000000F // Count Size +#define TIMER_PP_SIZE_16 0x00000000 // Timer A and Timer B counters are + // 16 bits each with an 8-bit + // prescale counter +#define TIMER_PP_SIZE_32 0x00000001 // Timer A and Timer B counters are + // 32 bits each with a 16-bit + // prescale counter + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_ACTSS register. +// +//***************************************************************************** +#define ADC_ACTSS_BUSY 0x00010000 // ADC Busy +#define ADC_ACTSS_ASEN3 0x00000008 // ADC SS3 Enable +#define ADC_ACTSS_ASEN2 0x00000004 // ADC SS2 Enable +#define ADC_ACTSS_ASEN1 0x00000002 // ADC SS1 Enable +#define ADC_ACTSS_ASEN0 0x00000001 // ADC SS0 Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_RIS register. +// +//***************************************************************************** +#define ADC_RIS_INRDC 0x00010000 // Digital Comparator Raw Interrupt + // Status +#define ADC_RIS_INR3 0x00000008 // SS3 Raw Interrupt Status +#define ADC_RIS_INR2 0x00000004 // SS2 Raw Interrupt Status +#define ADC_RIS_INR1 0x00000002 // SS1 Raw Interrupt Status +#define ADC_RIS_INR0 0x00000001 // SS0 Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_IM register. +// +//***************************************************************************** +#define ADC_IM_DCONSS3 0x00080000 // Digital Comparator Interrupt on + // SS3 +#define ADC_IM_DCONSS2 0x00040000 // Digital Comparator Interrupt on + // SS2 +#define ADC_IM_DCONSS1 0x00020000 // Digital Comparator Interrupt on + // SS1 +#define ADC_IM_DCONSS0 0x00010000 // Digital Comparator Interrupt on + // SS0 +#define ADC_IM_MASK3 0x00000008 // SS3 Interrupt Mask +#define ADC_IM_MASK2 0x00000004 // SS2 Interrupt Mask +#define ADC_IM_MASK1 0x00000002 // SS1 Interrupt Mask +#define ADC_IM_MASK0 0x00000001 // SS0 Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_ISC register. +// +//***************************************************************************** +#define ADC_ISC_DCINSS3 0x00080000 // Digital Comparator Interrupt + // Status on SS3 +#define ADC_ISC_DCINSS2 0x00040000 // Digital Comparator Interrupt + // Status on SS2 +#define ADC_ISC_DCINSS1 0x00020000 // Digital Comparator Interrupt + // Status on SS1 +#define ADC_ISC_DCINSS0 0x00010000 // Digital Comparator Interrupt + // Status on SS0 +#define ADC_ISC_IN3 0x00000008 // SS3 Interrupt Status and Clear +#define ADC_ISC_IN2 0x00000004 // SS2 Interrupt Status and Clear +#define ADC_ISC_IN1 0x00000002 // SS1 Interrupt Status and Clear +#define ADC_ISC_IN0 0x00000001 // SS0 Interrupt Status and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_OSTAT register. +// +//***************************************************************************** +#define ADC_OSTAT_OV3 0x00000008 // SS3 FIFO Overflow +#define ADC_OSTAT_OV2 0x00000004 // SS2 FIFO Overflow +#define ADC_OSTAT_OV1 0x00000002 // SS1 FIFO Overflow +#define ADC_OSTAT_OV0 0x00000001 // SS0 FIFO Overflow + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_EMUX register. +// +//***************************************************************************** +#define ADC_EMUX_EM3_M 0x0000F000 // SS3 Trigger Select +#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor (default) +#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog Comparator 0 +#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog Comparator 1 +#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog Comparator 2 +#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External (GPIO Pins) +#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer +#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM generator 0 +#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM generator 1 +#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM generator 2 +#define ADC_EMUX_EM3_PWM3 0x00009000 // PWM generator 3 +#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always (continuously sample) +#define ADC_EMUX_EM2_M 0x00000F00 // SS2 Trigger Select +#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor (default) +#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog Comparator 0 +#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog Comparator 1 +#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog Comparator 2 +#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External (GPIO Pins) +#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer +#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM generator 0 +#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM generator 1 +#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM generator 2 +#define ADC_EMUX_EM2_PWM3 0x00000900 // PWM generator 3 +#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always (continuously sample) +#define ADC_EMUX_EM1_M 0x000000F0 // SS1 Trigger Select +#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor (default) +#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog Comparator 0 +#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog Comparator 1 +#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog Comparator 2 +#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External (GPIO Pins) +#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer +#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM generator 0 +#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM generator 1 +#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM generator 2 +#define ADC_EMUX_EM1_PWM3 0x00000090 // PWM generator 3 +#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always (continuously sample) +#define ADC_EMUX_EM0_M 0x0000000F // SS0 Trigger Select +#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor (default) +#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog Comparator 0 +#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog Comparator 1 +#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog Comparator 2 +#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External (GPIO Pins) +#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer +#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM generator 0 +#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM generator 1 +#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM generator 2 +#define ADC_EMUX_EM0_PWM3 0x00000009 // PWM generator 3 +#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always (continuously sample) + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_USTAT register. +// +//***************************************************************************** +#define ADC_USTAT_UV3 0x00000008 // SS3 FIFO Underflow +#define ADC_USTAT_UV2 0x00000004 // SS2 FIFO Underflow +#define ADC_USTAT_UV1 0x00000002 // SS1 FIFO Underflow +#define ADC_USTAT_UV0 0x00000001 // SS0 FIFO Underflow + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_TSSEL register. +// +//***************************************************************************** +#define ADC_TSSEL_PS3_M 0x30000000 // Generator 3 PWM Module Trigger + // Select +#define ADC_TSSEL_PS3_0 0x00000000 // Use Generator 3 (and its + // trigger) in PWM module 0 +#define ADC_TSSEL_PS3_1 0x10000000 // Use Generator 3 (and its + // trigger) in PWM module 1 +#define ADC_TSSEL_PS2_M 0x00300000 // Generator 2 PWM Module Trigger + // Select +#define ADC_TSSEL_PS2_0 0x00000000 // Use Generator 2 (and its + // trigger) in PWM module 0 +#define ADC_TSSEL_PS2_1 0x00100000 // Use Generator 2 (and its + // trigger) in PWM module 1 +#define ADC_TSSEL_PS1_M 0x00003000 // Generator 1 PWM Module Trigger + // Select +#define ADC_TSSEL_PS1_0 0x00000000 // Use Generator 1 (and its + // trigger) in PWM module 0 +#define ADC_TSSEL_PS1_1 0x00001000 // Use Generator 1 (and its + // trigger) in PWM module 1 +#define ADC_TSSEL_PS0_M 0x00000030 // Generator 0 PWM Module Trigger + // Select +#define ADC_TSSEL_PS0_0 0x00000000 // Use Generator 0 (and its + // trigger) in PWM module 0 +#define ADC_TSSEL_PS0_1 0x00000010 // Use Generator 0 (and its + // trigger) in PWM module 1 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSPRI register. +// +//***************************************************************************** +#define ADC_SSPRI_SS3_M 0x00003000 // SS3 Priority +#define ADC_SSPRI_SS2_M 0x00000300 // SS2 Priority +#define ADC_SSPRI_SS1_M 0x00000030 // SS1 Priority +#define ADC_SSPRI_SS0_M 0x00000003 // SS0 Priority + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SPC register. +// +//***************************************************************************** +#define ADC_SPC_PHASE_M 0x0000000F // Phase Difference +#define ADC_SPC_PHASE_0 0x00000000 // ADC sample lags by 0.0 +#define ADC_SPC_PHASE_22_5 0x00000001 // ADC sample lags by 22.5 +#define ADC_SPC_PHASE_45 0x00000002 // ADC sample lags by 45.0 +#define ADC_SPC_PHASE_67_5 0x00000003 // ADC sample lags by 67.5 +#define ADC_SPC_PHASE_90 0x00000004 // ADC sample lags by 90.0 +#define ADC_SPC_PHASE_112_5 0x00000005 // ADC sample lags by 112.5 +#define ADC_SPC_PHASE_135 0x00000006 // ADC sample lags by 135.0 +#define ADC_SPC_PHASE_157_5 0x00000007 // ADC sample lags by 157.5 +#define ADC_SPC_PHASE_180 0x00000008 // ADC sample lags by 180.0 +#define ADC_SPC_PHASE_202_5 0x00000009 // ADC sample lags by 202.5 +#define ADC_SPC_PHASE_225 0x0000000A // ADC sample lags by 225.0 +#define ADC_SPC_PHASE_247_5 0x0000000B // ADC sample lags by 247.5 +#define ADC_SPC_PHASE_270 0x0000000C // ADC sample lags by 270.0 +#define ADC_SPC_PHASE_292_5 0x0000000D // ADC sample lags by 292.5 +#define ADC_SPC_PHASE_315 0x0000000E // ADC sample lags by 315.0 +#define ADC_SPC_PHASE_337_5 0x0000000F // ADC sample lags by 337.5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_PSSI register. +// +//***************************************************************************** +#define ADC_PSSI_GSYNC 0x80000000 // Global Synchronize +#define ADC_PSSI_SYNCWAIT 0x08000000 // Synchronize Wait +#define ADC_PSSI_SS3 0x00000008 // SS3 Initiate +#define ADC_PSSI_SS2 0x00000004 // SS2 Initiate +#define ADC_PSSI_SS1 0x00000002 // SS1 Initiate +#define ADC_PSSI_SS0 0x00000001 // SS0 Initiate + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SAC register. +// +//***************************************************************************** +#define ADC_SAC_AVG_M 0x00000007 // Hardware Averaging Control +#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling +#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling +#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling +#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling +#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling +#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling +#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCISC register. +// +//***************************************************************************** +#define ADC_DCISC_DCINT7 0x00000080 // Digital Comparator 7 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT6 0x00000040 // Digital Comparator 6 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT5 0x00000020 // Digital Comparator 5 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT4 0x00000010 // Digital Comparator 4 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT3 0x00000008 // Digital Comparator 3 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT2 0x00000004 // Digital Comparator 2 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT1 0x00000002 // Digital Comparator 1 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT0 0x00000001 // Digital Comparator 0 Interrupt + // Status and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_CTL register. +// +//***************************************************************************** +#define ADC_CTL_VREF_M 0x00000001 // Voltage Reference Select +#define ADC_CTL_VREF_INTERNAL 0x00000000 // VDDA and GNDA are the voltage + // references +#define ADC_CTL_VREF_EXT_3V 0x00000001 // The external VREFA+ and VREFA- + // inputs are the voltage + // references + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX0 register. +// +//***************************************************************************** +#define ADC_SSMUX0_MUX7_M 0xF0000000 // 8th Sample Input Select +#define ADC_SSMUX0_MUX6_M 0x0F000000 // 7th Sample Input Select +#define ADC_SSMUX0_MUX5_M 0x00F00000 // 6th Sample Input Select +#define ADC_SSMUX0_MUX4_M 0x000F0000 // 5th Sample Input Select +#define ADC_SSMUX0_MUX3_M 0x0000F000 // 4th Sample Input Select +#define ADC_SSMUX0_MUX2_M 0x00000F00 // 3rd Sample Input Select +#define ADC_SSMUX0_MUX1_M 0x000000F0 // 2nd Sample Input Select +#define ADC_SSMUX0_MUX0_M 0x0000000F // 1st Sample Input Select +#define ADC_SSMUX0_MUX7_S 28 +#define ADC_SSMUX0_MUX6_S 24 +#define ADC_SSMUX0_MUX5_S 20 +#define ADC_SSMUX0_MUX4_S 16 +#define ADC_SSMUX0_MUX3_S 12 +#define ADC_SSMUX0_MUX2_S 8 +#define ADC_SSMUX0_MUX1_S 4 +#define ADC_SSMUX0_MUX0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL0 register. +// +//***************************************************************************** +#define ADC_SSCTL0_TS7 0x80000000 // 8th Sample Temp Sensor Select +#define ADC_SSCTL0_IE7 0x40000000 // 8th Sample Interrupt Enable +#define ADC_SSCTL0_END7 0x20000000 // 8th Sample is End of Sequence +#define ADC_SSCTL0_D7 0x10000000 // 8th Sample Differential Input + // Select +#define ADC_SSCTL0_TS6 0x08000000 // 7th Sample Temp Sensor Select +#define ADC_SSCTL0_IE6 0x04000000 // 7th Sample Interrupt Enable +#define ADC_SSCTL0_END6 0x02000000 // 7th Sample is End of Sequence +#define ADC_SSCTL0_D6 0x01000000 // 7th Sample Differential Input + // Select +#define ADC_SSCTL0_TS5 0x00800000 // 6th Sample Temp Sensor Select +#define ADC_SSCTL0_IE5 0x00400000 // 6th Sample Interrupt Enable +#define ADC_SSCTL0_END5 0x00200000 // 6th Sample is End of Sequence +#define ADC_SSCTL0_D5 0x00100000 // 6th Sample Differential Input + // Select +#define ADC_SSCTL0_TS4 0x00080000 // 5th Sample Temp Sensor Select +#define ADC_SSCTL0_IE4 0x00040000 // 5th Sample Interrupt Enable +#define ADC_SSCTL0_END4 0x00020000 // 5th Sample is End of Sequence +#define ADC_SSCTL0_D4 0x00010000 // 5th Sample Differential Input + // Select +#define ADC_SSCTL0_TS3 0x00008000 // 4th Sample Temp Sensor Select +#define ADC_SSCTL0_IE3 0x00004000 // 4th Sample Interrupt Enable +#define ADC_SSCTL0_END3 0x00002000 // 4th Sample is End of Sequence +#define ADC_SSCTL0_D3 0x00001000 // 4th Sample Differential Input + // Select +#define ADC_SSCTL0_TS2 0x00000800 // 3rd Sample Temp Sensor Select +#define ADC_SSCTL0_IE2 0x00000400 // 3rd Sample Interrupt Enable +#define ADC_SSCTL0_END2 0x00000200 // 3rd Sample is End of Sequence +#define ADC_SSCTL0_D2 0x00000100 // 3rd Sample Differential Input + // Select +#define ADC_SSCTL0_TS1 0x00000080 // 2nd Sample Temp Sensor Select +#define ADC_SSCTL0_IE1 0x00000040 // 2nd Sample Interrupt Enable +#define ADC_SSCTL0_END1 0x00000020 // 2nd Sample is End of Sequence +#define ADC_SSCTL0_D1 0x00000010 // 2nd Sample Differential Input + // Select +#define ADC_SSCTL0_TS0 0x00000008 // 1st Sample Temp Sensor Select +#define ADC_SSCTL0_IE0 0x00000004 // 1st Sample Interrupt Enable +#define ADC_SSCTL0_END0 0x00000002 // 1st Sample is End of Sequence +#define ADC_SSCTL0_D0 0x00000001 // 1st Sample Differential Input + // Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO0 register. +// +//***************************************************************************** +#define ADC_SSFIFO0_DATA_M 0x00000FFF // Conversion Result Data +#define ADC_SSFIFO0_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register. +// +//***************************************************************************** +#define ADC_SSFSTAT0_FULL 0x00001000 // FIFO Full +#define ADC_SSFSTAT0_EMPTY 0x00000100 // FIFO Empty +#define ADC_SSFSTAT0_HPTR_M 0x000000F0 // FIFO Head Pointer +#define ADC_SSFSTAT0_TPTR_M 0x0000000F // FIFO Tail Pointer +#define ADC_SSFSTAT0_HPTR_S 4 +#define ADC_SSFSTAT0_TPTR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSOP0 register. +// +//***************************************************************************** +#define ADC_SSOP0_S7DCOP 0x10000000 // Sample 7 Digital Comparator + // Operation +#define ADC_SSOP0_S6DCOP 0x01000000 // Sample 6 Digital Comparator + // Operation +#define ADC_SSOP0_S5DCOP 0x00100000 // Sample 5 Digital Comparator + // Operation +#define ADC_SSOP0_S4DCOP 0x00010000 // Sample 4 Digital Comparator + // Operation +#define ADC_SSOP0_S3DCOP 0x00001000 // Sample 3 Digital Comparator + // Operation +#define ADC_SSOP0_S2DCOP 0x00000100 // Sample 2 Digital Comparator + // Operation +#define ADC_SSOP0_S1DCOP 0x00000010 // Sample 1 Digital Comparator + // Operation +#define ADC_SSOP0_S0DCOP 0x00000001 // Sample 0 Digital Comparator + // Operation + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSDC0 register. +// +//***************************************************************************** +#define ADC_SSDC0_S7DCSEL_M 0xF0000000 // Sample 7 Digital Comparator + // Select +#define ADC_SSDC0_S6DCSEL_M 0x0F000000 // Sample 6 Digital Comparator + // Select +#define ADC_SSDC0_S5DCSEL_M 0x00F00000 // Sample 5 Digital Comparator + // Select +#define ADC_SSDC0_S4DCSEL_M 0x000F0000 // Sample 4 Digital Comparator + // Select +#define ADC_SSDC0_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator + // Select +#define ADC_SSDC0_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator + // Select +#define ADC_SSDC0_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator + // Select +#define ADC_SSDC0_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator + // Select +#define ADC_SSDC0_S6DCSEL_S 24 +#define ADC_SSDC0_S5DCSEL_S 20 +#define ADC_SSDC0_S4DCSEL_S 16 +#define ADC_SSDC0_S3DCSEL_S 12 +#define ADC_SSDC0_S2DCSEL_S 8 +#define ADC_SSDC0_S1DCSEL_S 4 +#define ADC_SSDC0_S0DCSEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSEMUX0 register. +// +//***************************************************************************** +#define ADC_SSEMUX0_EMUX7 0x10000000 // 8th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX0_EMUX6 0x01000000 // 7th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX0_EMUX5 0x00100000 // 6th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX0_EMUX4 0x00010000 // 5th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX0_EMUX3 0x00001000 // 4th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX0_EMUX2 0x00000100 // 3rd Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX0_EMUX1 0x00000010 // 2th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX0_EMUX0 0x00000001 // 1st Sample Input Select (Upper + // Bit) + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX1 register. +// +//***************************************************************************** +#define ADC_SSMUX1_MUX3_M 0x0000F000 // 4th Sample Input Select +#define ADC_SSMUX1_MUX2_M 0x00000F00 // 3rd Sample Input Select +#define ADC_SSMUX1_MUX1_M 0x000000F0 // 2nd Sample Input Select +#define ADC_SSMUX1_MUX0_M 0x0000000F // 1st Sample Input Select +#define ADC_SSMUX1_MUX3_S 12 +#define ADC_SSMUX1_MUX2_S 8 +#define ADC_SSMUX1_MUX1_S 4 +#define ADC_SSMUX1_MUX0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL1 register. +// +//***************************************************************************** +#define ADC_SSCTL1_TS3 0x00008000 // 4th Sample Temp Sensor Select +#define ADC_SSCTL1_IE3 0x00004000 // 4th Sample Interrupt Enable +#define ADC_SSCTL1_END3 0x00002000 // 4th Sample is End of Sequence +#define ADC_SSCTL1_D3 0x00001000 // 4th Sample Differential Input + // Select +#define ADC_SSCTL1_TS2 0x00000800 // 3rd Sample Temp Sensor Select +#define ADC_SSCTL1_IE2 0x00000400 // 3rd Sample Interrupt Enable +#define ADC_SSCTL1_END2 0x00000200 // 3rd Sample is End of Sequence +#define ADC_SSCTL1_D2 0x00000100 // 3rd Sample Differential Input + // Select +#define ADC_SSCTL1_TS1 0x00000080 // 2nd Sample Temp Sensor Select +#define ADC_SSCTL1_IE1 0x00000040 // 2nd Sample Interrupt Enable +#define ADC_SSCTL1_END1 0x00000020 // 2nd Sample is End of Sequence +#define ADC_SSCTL1_D1 0x00000010 // 2nd Sample Differential Input + // Select +#define ADC_SSCTL1_TS0 0x00000008 // 1st Sample Temp Sensor Select +#define ADC_SSCTL1_IE0 0x00000004 // 1st Sample Interrupt Enable +#define ADC_SSCTL1_END0 0x00000002 // 1st Sample is End of Sequence +#define ADC_SSCTL1_D0 0x00000001 // 1st Sample Differential Input + // Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO1 register. +// +//***************************************************************************** +#define ADC_SSFIFO1_DATA_M 0x00000FFF // Conversion Result Data +#define ADC_SSFIFO1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register. +// +//***************************************************************************** +#define ADC_SSFSTAT1_FULL 0x00001000 // FIFO Full +#define ADC_SSFSTAT1_EMPTY 0x00000100 // FIFO Empty +#define ADC_SSFSTAT1_HPTR_M 0x000000F0 // FIFO Head Pointer +#define ADC_SSFSTAT1_TPTR_M 0x0000000F // FIFO Tail Pointer +#define ADC_SSFSTAT1_HPTR_S 4 +#define ADC_SSFSTAT1_TPTR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSOP1 register. +// +//***************************************************************************** +#define ADC_SSOP1_S3DCOP 0x00001000 // Sample 3 Digital Comparator + // Operation +#define ADC_SSOP1_S2DCOP 0x00000100 // Sample 2 Digital Comparator + // Operation +#define ADC_SSOP1_S1DCOP 0x00000010 // Sample 1 Digital Comparator + // Operation +#define ADC_SSOP1_S0DCOP 0x00000001 // Sample 0 Digital Comparator + // Operation + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSDC1 register. +// +//***************************************************************************** +#define ADC_SSDC1_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator + // Select +#define ADC_SSDC1_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator + // Select +#define ADC_SSDC1_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator + // Select +#define ADC_SSDC1_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator + // Select +#define ADC_SSDC1_S2DCSEL_S 8 +#define ADC_SSDC1_S1DCSEL_S 4 +#define ADC_SSDC1_S0DCSEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSEMUX1 register. +// +//***************************************************************************** +#define ADC_SSEMUX1_EMUX3 0x00001000 // 4th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX1_EMUX2 0x00000100 // 3rd Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX1_EMUX1 0x00000010 // 2th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX1_EMUX0 0x00000001 // 1st Sample Input Select (Upper + // Bit) + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX2 register. +// +//***************************************************************************** +#define ADC_SSMUX2_MUX3_M 0x0000F000 // 4th Sample Input Select +#define ADC_SSMUX2_MUX2_M 0x00000F00 // 3rd Sample Input Select +#define ADC_SSMUX2_MUX1_M 0x000000F0 // 2nd Sample Input Select +#define ADC_SSMUX2_MUX0_M 0x0000000F // 1st Sample Input Select +#define ADC_SSMUX2_MUX3_S 12 +#define ADC_SSMUX2_MUX2_S 8 +#define ADC_SSMUX2_MUX1_S 4 +#define ADC_SSMUX2_MUX0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL2 register. +// +//***************************************************************************** +#define ADC_SSCTL2_TS3 0x00008000 // 4th Sample Temp Sensor Select +#define ADC_SSCTL2_IE3 0x00004000 // 4th Sample Interrupt Enable +#define ADC_SSCTL2_END3 0x00002000 // 4th Sample is End of Sequence +#define ADC_SSCTL2_D3 0x00001000 // 4th Sample Differential Input + // Select +#define ADC_SSCTL2_TS2 0x00000800 // 3rd Sample Temp Sensor Select +#define ADC_SSCTL2_IE2 0x00000400 // 3rd Sample Interrupt Enable +#define ADC_SSCTL2_END2 0x00000200 // 3rd Sample is End of Sequence +#define ADC_SSCTL2_D2 0x00000100 // 3rd Sample Differential Input + // Select +#define ADC_SSCTL2_TS1 0x00000080 // 2nd Sample Temp Sensor Select +#define ADC_SSCTL2_IE1 0x00000040 // 2nd Sample Interrupt Enable +#define ADC_SSCTL2_END1 0x00000020 // 2nd Sample is End of Sequence +#define ADC_SSCTL2_D1 0x00000010 // 2nd Sample Differential Input + // Select +#define ADC_SSCTL2_TS0 0x00000008 // 1st Sample Temp Sensor Select +#define ADC_SSCTL2_IE0 0x00000004 // 1st Sample Interrupt Enable +#define ADC_SSCTL2_END0 0x00000002 // 1st Sample is End of Sequence +#define ADC_SSCTL2_D0 0x00000001 // 1st Sample Differential Input + // Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO2 register. +// +//***************************************************************************** +#define ADC_SSFIFO2_DATA_M 0x00000FFF // Conversion Result Data +#define ADC_SSFIFO2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register. +// +//***************************************************************************** +#define ADC_SSFSTAT2_FULL 0x00001000 // FIFO Full +#define ADC_SSFSTAT2_EMPTY 0x00000100 // FIFO Empty +#define ADC_SSFSTAT2_HPTR_M 0x000000F0 // FIFO Head Pointer +#define ADC_SSFSTAT2_TPTR_M 0x0000000F // FIFO Tail Pointer +#define ADC_SSFSTAT2_HPTR_S 4 +#define ADC_SSFSTAT2_TPTR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSOP2 register. +// +//***************************************************************************** +#define ADC_SSOP2_S3DCOP 0x00001000 // Sample 3 Digital Comparator + // Operation +#define ADC_SSOP2_S2DCOP 0x00000100 // Sample 2 Digital Comparator + // Operation +#define ADC_SSOP2_S1DCOP 0x00000010 // Sample 1 Digital Comparator + // Operation +#define ADC_SSOP2_S0DCOP 0x00000001 // Sample 0 Digital Comparator + // Operation + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSDC2 register. +// +//***************************************************************************** +#define ADC_SSDC2_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator + // Select +#define ADC_SSDC2_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator + // Select +#define ADC_SSDC2_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator + // Select +#define ADC_SSDC2_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator + // Select +#define ADC_SSDC2_S2DCSEL_S 8 +#define ADC_SSDC2_S1DCSEL_S 4 +#define ADC_SSDC2_S0DCSEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSEMUX2 register. +// +//***************************************************************************** +#define ADC_SSEMUX2_EMUX3 0x00001000 // 4th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX2_EMUX2 0x00000100 // 3rd Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX2_EMUX1 0x00000010 // 2th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX2_EMUX0 0x00000001 // 1st Sample Input Select (Upper + // Bit) + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX3 register. +// +//***************************************************************************** +#define ADC_SSMUX3_MUX0_M 0x0000000F // 1st Sample Input Select +#define ADC_SSMUX3_MUX0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL3 register. +// +//***************************************************************************** +#define ADC_SSCTL3_TS0 0x00000008 // 1st Sample Temp Sensor Select +#define ADC_SSCTL3_IE0 0x00000004 // Sample Interrupt Enable +#define ADC_SSCTL3_END0 0x00000002 // End of Sequence +#define ADC_SSCTL3_D0 0x00000001 // Sample Differential Input Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO3 register. +// +//***************************************************************************** +#define ADC_SSFIFO3_DATA_M 0x00000FFF // Conversion Result Data +#define ADC_SSFIFO3_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register. +// +//***************************************************************************** +#define ADC_SSFSTAT3_FULL 0x00001000 // FIFO Full +#define ADC_SSFSTAT3_EMPTY 0x00000100 // FIFO Empty +#define ADC_SSFSTAT3_HPTR_M 0x000000F0 // FIFO Head Pointer +#define ADC_SSFSTAT3_TPTR_M 0x0000000F // FIFO Tail Pointer +#define ADC_SSFSTAT3_HPTR_S 4 +#define ADC_SSFSTAT3_TPTR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSOP3 register. +// +//***************************************************************************** +#define ADC_SSOP3_S0DCOP 0x00000001 // Sample 0 Digital Comparator + // Operation + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSDC3 register. +// +//***************************************************************************** +#define ADC_SSDC3_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator + // Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSEMUX3 register. +// +//***************************************************************************** +#define ADC_SSEMUX3_EMUX0 0x00000001 // 1st Sample Input Select (Upper + // Bit) + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCRIC register. +// +//***************************************************************************** +#define ADC_DCRIC_DCTRIG7 0x00800000 // Digital Comparator Trigger 7 +#define ADC_DCRIC_DCTRIG6 0x00400000 // Digital Comparator Trigger 6 +#define ADC_DCRIC_DCTRIG5 0x00200000 // Digital Comparator Trigger 5 +#define ADC_DCRIC_DCTRIG4 0x00100000 // Digital Comparator Trigger 4 +#define ADC_DCRIC_DCTRIG3 0x00080000 // Digital Comparator Trigger 3 +#define ADC_DCRIC_DCTRIG2 0x00040000 // Digital Comparator Trigger 2 +#define ADC_DCRIC_DCTRIG1 0x00020000 // Digital Comparator Trigger 1 +#define ADC_DCRIC_DCTRIG0 0x00010000 // Digital Comparator Trigger 0 +#define ADC_DCRIC_DCINT7 0x00000080 // Digital Comparator Interrupt 7 +#define ADC_DCRIC_DCINT6 0x00000040 // Digital Comparator Interrupt 6 +#define ADC_DCRIC_DCINT5 0x00000020 // Digital Comparator Interrupt 5 +#define ADC_DCRIC_DCINT4 0x00000010 // Digital Comparator Interrupt 4 +#define ADC_DCRIC_DCINT3 0x00000008 // Digital Comparator Interrupt 3 +#define ADC_DCRIC_DCINT2 0x00000004 // Digital Comparator Interrupt 2 +#define ADC_DCRIC_DCINT1 0x00000002 // Digital Comparator Interrupt 1 +#define ADC_DCRIC_DCINT0 0x00000001 // Digital Comparator Interrupt 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL0 register. +// +//***************************************************************************** +#define ADC_DCCTL0_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL0_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL0_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL0_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL0_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL0_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL0_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL0_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL0_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL0_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL0_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL0_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL0_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL0_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL0_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL0_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL0_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL0_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL0_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL0_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL1 register. +// +//***************************************************************************** +#define ADC_DCCTL1_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL1_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL1_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL1_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL1_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL1_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL1_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL1_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL1_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL1_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL1_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL1_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL1_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL1_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL1_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL1_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL1_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL1_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL1_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL1_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL2 register. +// +//***************************************************************************** +#define ADC_DCCTL2_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL2_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL2_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL2_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL2_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL2_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL2_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL2_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL2_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL2_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL2_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL2_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL2_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL2_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL2_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL2_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL2_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL2_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL2_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL2_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL3 register. +// +//***************************************************************************** +#define ADC_DCCTL3_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL3_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL3_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL3_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL3_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL3_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL3_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL3_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL3_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL3_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL3_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL3_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL3_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL3_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL3_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL3_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL3_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL3_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL3_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL3_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL4 register. +// +//***************************************************************************** +#define ADC_DCCTL4_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL4_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL4_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL4_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL4_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL4_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL4_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL4_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL4_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL4_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL4_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL4_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL4_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL4_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL4_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL4_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL4_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL4_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL4_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL4_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL5 register. +// +//***************************************************************************** +#define ADC_DCCTL5_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL5_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL5_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL5_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL5_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL5_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL5_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL5_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL5_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL5_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL5_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL5_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL5_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL5_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL5_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL5_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL5_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL5_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL5_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL5_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL6 register. +// +//***************************************************************************** +#define ADC_DCCTL6_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL6_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL6_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL6_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL6_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL6_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL6_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL6_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL6_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL6_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL6_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL6_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL6_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL6_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL6_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL6_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL6_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL6_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL6_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL6_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL7 register. +// +//***************************************************************************** +#define ADC_DCCTL7_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL7_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL7_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL7_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL7_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL7_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL7_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL7_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL7_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL7_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL7_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL7_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL7_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL7_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL7_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL7_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL7_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL7_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL7_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL7_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP0 register. +// +//***************************************************************************** +#define ADC_DCCMP0_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP0_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP0_COMP1_S 16 +#define ADC_DCCMP0_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP1 register. +// +//***************************************************************************** +#define ADC_DCCMP1_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP1_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP1_COMP1_S 16 +#define ADC_DCCMP1_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP2 register. +// +//***************************************************************************** +#define ADC_DCCMP2_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP2_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP2_COMP1_S 16 +#define ADC_DCCMP2_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP3 register. +// +//***************************************************************************** +#define ADC_DCCMP3_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP3_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP3_COMP1_S 16 +#define ADC_DCCMP3_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP4 register. +// +//***************************************************************************** +#define ADC_DCCMP4_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP4_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP4_COMP1_S 16 +#define ADC_DCCMP4_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP5 register. +// +//***************************************************************************** +#define ADC_DCCMP5_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP5_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP5_COMP1_S 16 +#define ADC_DCCMP5_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP6 register. +// +//***************************************************************************** +#define ADC_DCCMP6_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP6_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP6_COMP1_S 16 +#define ADC_DCCMP6_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP7 register. +// +//***************************************************************************** +#define ADC_DCCMP7_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP7_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP7_COMP1_S 16 +#define ADC_DCCMP7_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_PP register. +// +//***************************************************************************** +#define ADC_PP_TS 0x00800000 // Temperature Sensor +#define ADC_PP_RSL_M 0x007C0000 // Resolution +#define ADC_PP_TYPE_M 0x00030000 // ADC Architecture +#define ADC_PP_TYPE_SAR 0x00000000 // SAR +#define ADC_PP_DC_M 0x0000FC00 // Digital Comparator Count +#define ADC_PP_CH_M 0x000003F0 // ADC Channel Count +#define ADC_PP_MSR_M 0x0000000F // Maximum ADC Sample Rate +#define ADC_PP_MSR_125K 0x00000001 // 125 ksps +#define ADC_PP_MSR_250K 0x00000003 // 250 ksps +#define ADC_PP_MSR_500K 0x00000005 // 500 ksps +#define ADC_PP_MSR_1M 0x00000007 // 1 Msps +#define ADC_PP_RSL_S 18 +#define ADC_PP_DC_S 10 +#define ADC_PP_CH_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_PC register. +// +//***************************************************************************** +#define ADC_PC_SR_M 0x0000000F // ADC Sample Rate +#define ADC_PC_SR_125K 0x00000001 // 125 ksps +#define ADC_PC_SR_250K 0x00000003 // 250 ksps +#define ADC_PC_SR_500K 0x00000005 // 500 ksps +#define ADC_PC_SR_1M 0x00000007 // 1 Msps + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_CC register. +// +//***************************************************************************** +#define ADC_CC_CS_M 0x0000000F // ADC Clock Source +#define ADC_CC_CS_SYSPLL 0x00000000 // PLL VCO divided by CLKDIV +#define ADC_CC_CS_PIOSC 0x00000001 // PIOSC + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACMIS register. +// +//***************************************************************************** +#define COMP_ACMIS_IN2 0x00000004 // Comparator 2 Masked Interrupt + // Status +#define COMP_ACMIS_IN1 0x00000002 // Comparator 1 Masked Interrupt + // Status +#define COMP_ACMIS_IN0 0x00000001 // Comparator 0 Masked Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACRIS register. +// +//***************************************************************************** +#define COMP_ACRIS_IN2 0x00000004 // Comparator 2 Interrupt Status +#define COMP_ACRIS_IN1 0x00000002 // Comparator 1 Interrupt Status +#define COMP_ACRIS_IN0 0x00000001 // Comparator 0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACINTEN register. +// +//***************************************************************************** +#define COMP_ACINTEN_IN2 0x00000004 // Comparator 2 Interrupt Enable +#define COMP_ACINTEN_IN1 0x00000002 // Comparator 1 Interrupt Enable +#define COMP_ACINTEN_IN0 0x00000001 // Comparator 0 Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACREFCTL +// register. +// +//***************************************************************************** +#define COMP_ACREFCTL_EN 0x00000200 // Resistor Ladder Enable +#define COMP_ACREFCTL_RNG 0x00000100 // Resistor Ladder Range +#define COMP_ACREFCTL_VREF_M 0x0000000F // Resistor Ladder Voltage Ref +#define COMP_ACREFCTL_VREF_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACSTAT0 register. +// +//***************************************************************************** +#define COMP_ACSTAT0_OVAL 0x00000002 // Comparator Output Value + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACCTL0 register. +// +//***************************************************************************** +#define COMP_ACCTL0_TOEN 0x00000800 // Trigger Output Enable +#define COMP_ACCTL0_ASRCP_M 0x00000600 // Analog Source Positive +#define COMP_ACCTL0_ASRCP_PIN 0x00000000 // Pin value of Cn+ +#define COMP_ACCTL0_ASRCP_PIN0 0x00000200 // Pin value of C0+ +#define COMP_ACCTL0_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_ACCTL0_TSLVAL 0x00000080 // Trigger Sense Level Value +#define COMP_ACCTL0_TSEN_M 0x00000060 // Trigger Sense +#define COMP_ACCTL0_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL +#define COMP_ACCTL0_TSEN_FALL 0x00000020 // Falling edge +#define COMP_ACCTL0_TSEN_RISE 0x00000040 // Rising edge +#define COMP_ACCTL0_TSEN_BOTH 0x00000060 // Either edge +#define COMP_ACCTL0_ISLVAL 0x00000010 // Interrupt Sense Level Value +#define COMP_ACCTL0_ISEN_M 0x0000000C // Interrupt Sense +#define COMP_ACCTL0_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL +#define COMP_ACCTL0_ISEN_FALL 0x00000004 // Falling edge +#define COMP_ACCTL0_ISEN_RISE 0x00000008 // Rising edge +#define COMP_ACCTL0_ISEN_BOTH 0x0000000C // Either edge +#define COMP_ACCTL0_CINV 0x00000002 // Comparator Output Invert + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACSTAT1 register. +// +//***************************************************************************** +#define COMP_ACSTAT1_OVAL 0x00000002 // Comparator Output Value + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACCTL1 register. +// +//***************************************************************************** +#define COMP_ACCTL1_TOEN 0x00000800 // Trigger Output Enable +#define COMP_ACCTL1_ASRCP_M 0x00000600 // Analog Source Positive +#define COMP_ACCTL1_ASRCP_PIN 0x00000000 // Pin value of Cn+ +#define COMP_ACCTL1_ASRCP_PIN0 0x00000200 // Pin value of C0+ +#define COMP_ACCTL1_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_ACCTL1_TSLVAL 0x00000080 // Trigger Sense Level Value +#define COMP_ACCTL1_TSEN_M 0x00000060 // Trigger Sense +#define COMP_ACCTL1_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL +#define COMP_ACCTL1_TSEN_FALL 0x00000020 // Falling edge +#define COMP_ACCTL1_TSEN_RISE 0x00000040 // Rising edge +#define COMP_ACCTL1_TSEN_BOTH 0x00000060 // Either edge +#define COMP_ACCTL1_ISLVAL 0x00000010 // Interrupt Sense Level Value +#define COMP_ACCTL1_ISEN_M 0x0000000C // Interrupt Sense +#define COMP_ACCTL1_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL +#define COMP_ACCTL1_ISEN_FALL 0x00000004 // Falling edge +#define COMP_ACCTL1_ISEN_RISE 0x00000008 // Rising edge +#define COMP_ACCTL1_ISEN_BOTH 0x0000000C // Either edge +#define COMP_ACCTL1_CINV 0x00000002 // Comparator Output Invert + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACSTAT2 register. +// +//***************************************************************************** +#define COMP_ACSTAT2_OVAL 0x00000002 // Comparator Output Value + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACCTL2 register. +// +//***************************************************************************** +#define COMP_ACCTL2_TOEN 0x00000800 // Trigger Output Enable +#define COMP_ACCTL2_ASRCP_M 0x00000600 // Analog Source Positive +#define COMP_ACCTL2_ASRCP_PIN 0x00000000 // Pin value of Cn+ +#define COMP_ACCTL2_ASRCP_PIN0 0x00000200 // Pin value of C0+ +#define COMP_ACCTL2_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_ACCTL2_TSLVAL 0x00000080 // Trigger Sense Level Value +#define COMP_ACCTL2_TSEN_M 0x00000060 // Trigger Sense +#define COMP_ACCTL2_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL +#define COMP_ACCTL2_TSEN_FALL 0x00000020 // Falling edge +#define COMP_ACCTL2_TSEN_RISE 0x00000040 // Rising edge +#define COMP_ACCTL2_TSEN_BOTH 0x00000060 // Either edge +#define COMP_ACCTL2_ISLVAL 0x00000010 // Interrupt Sense Level Value +#define COMP_ACCTL2_ISEN_M 0x0000000C // Interrupt Sense +#define COMP_ACCTL2_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL +#define COMP_ACCTL2_ISEN_FALL 0x00000004 // Falling edge +#define COMP_ACCTL2_ISEN_RISE 0x00000008 // Rising edge +#define COMP_ACCTL2_ISEN_BOTH 0x0000000C // Either edge +#define COMP_ACCTL2_CINV 0x00000002 // Comparator Output Invert + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_PP register. +// +//***************************************************************************** +#define COMP_PP_C2O 0x00040000 // Comparator Output 2 Present +#define COMP_PP_C1O 0x00020000 // Comparator Output 1 Present +#define COMP_PP_C0O 0x00010000 // Comparator Output 0 Present +#define COMP_PP_CMP2 0x00000004 // Comparator 2 Present +#define COMP_PP_CMP1 0x00000002 // Comparator 1 Present +#define COMP_PP_CMP0 0x00000001 // Comparator 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_CTL register. +// +//***************************************************************************** +#define CAN_CTL_TEST 0x00000080 // Test Mode Enable +#define CAN_CTL_CCE 0x00000040 // Configuration Change Enable +#define CAN_CTL_DAR 0x00000020 // Disable Automatic-Retransmission +#define CAN_CTL_EIE 0x00000008 // Error Interrupt Enable +#define CAN_CTL_SIE 0x00000004 // Status Interrupt Enable +#define CAN_CTL_IE 0x00000002 // CAN Interrupt Enable +#define CAN_CTL_INIT 0x00000001 // Initialization + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_STS register. +// +//***************************************************************************** +#define CAN_STS_BOFF 0x00000080 // Bus-Off Status +#define CAN_STS_EWARN 0x00000040 // Warning Status +#define CAN_STS_EPASS 0x00000020 // Error Passive +#define CAN_STS_RXOK 0x00000010 // Received a Message Successfully +#define CAN_STS_TXOK 0x00000008 // Transmitted a Message + // Successfully +#define CAN_STS_LEC_M 0x00000007 // Last Error Code +#define CAN_STS_LEC_NONE 0x00000000 // No Error +#define CAN_STS_LEC_STUFF 0x00000001 // Stuff Error +#define CAN_STS_LEC_FORM 0x00000002 // Format Error +#define CAN_STS_LEC_ACK 0x00000003 // ACK Error +#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 Error +#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 Error +#define CAN_STS_LEC_CRC 0x00000006 // CRC Error +#define CAN_STS_LEC_NOEVENT 0x00000007 // No Event + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_ERR register. +// +//***************************************************************************** +#define CAN_ERR_RP 0x00008000 // Received Error Passive +#define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter +#define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter +#define CAN_ERR_REC_S 8 +#define CAN_ERR_TEC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_BIT register. +// +//***************************************************************************** +#define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point +#define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample Point +#define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width +#define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescaler +#define CAN_BIT_TSEG2_S 12 +#define CAN_BIT_TSEG1_S 8 +#define CAN_BIT_SJW_S 6 +#define CAN_BIT_BRP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_INT register. +// +//***************************************************************************** +#define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier +#define CAN_INT_INTID_NONE 0x00000000 // No interrupt pending +#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_TST register. +// +//***************************************************************************** +#define CAN_TST_RX 0x00000080 // Receive Observation +#define CAN_TST_TX_M 0x00000060 // Transmit Control +#define CAN_TST_TX_CANCTL 0x00000000 // CAN Module Control +#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point +#define CAN_TST_TX_DOMINANT 0x00000040 // Driven Low +#define CAN_TST_TX_RECESSIVE 0x00000060 // Driven High +#define CAN_TST_LBACK 0x00000010 // Loopback Mode +#define CAN_TST_SILENT 0x00000008 // Silent Mode +#define CAN_TST_BASIC 0x00000004 // Basic Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_BRPE register. +// +//***************************************************************************** +#define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescaler Extension +#define CAN_BRPE_BRPE_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1CRQ register. +// +//***************************************************************************** +#define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag +#define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number +#define CAN_IF1CRQ_MNUM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1CMSK register. +// +//***************************************************************************** +#define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read +#define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits +#define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits +#define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits +#define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit +#define CAN_IF1CMSK_NEWDAT 0x00000004 // Access New Data +#define CAN_IF1CMSK_TXRQST 0x00000004 // Access Transmission Request +#define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3 +#define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1MSK1 register. +// +//***************************************************************************** +#define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask +#define CAN_IF1MSK1_IDMSK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1MSK2 register. +// +//***************************************************************************** +#define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier +#define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction +#define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask +#define CAN_IF1MSK2_IDMSK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1ARB1 register. +// +//***************************************************************************** +#define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier +#define CAN_IF1ARB1_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1ARB2 register. +// +//***************************************************************************** +#define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid +#define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier +#define CAN_IF1ARB2_DIR 0x00002000 // Message Direction +#define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier +#define CAN_IF1ARB2_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1MCTL register. +// +//***************************************************************************** +#define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data +#define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost +#define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending +#define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask +#define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable +#define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable +#define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable +#define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request +#define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer +#define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code +#define CAN_IF1MCTL_DLC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1DA1 register. +// +//***************************************************************************** +#define CAN_IF1DA1_DATA_M 0x0000FFFF // Data +#define CAN_IF1DA1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1DA2 register. +// +//***************************************************************************** +#define CAN_IF1DA2_DATA_M 0x0000FFFF // Data +#define CAN_IF1DA2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1DB1 register. +// +//***************************************************************************** +#define CAN_IF1DB1_DATA_M 0x0000FFFF // Data +#define CAN_IF1DB1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1DB2 register. +// +//***************************************************************************** +#define CAN_IF1DB2_DATA_M 0x0000FFFF // Data +#define CAN_IF1DB2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2CRQ register. +// +//***************************************************************************** +#define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag +#define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number +#define CAN_IF2CRQ_MNUM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2CMSK register. +// +//***************************************************************************** +#define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read +#define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits +#define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits +#define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits +#define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit +#define CAN_IF2CMSK_NEWDAT 0x00000004 // Access New Data +#define CAN_IF2CMSK_TXRQST 0x00000004 // Access Transmission Request +#define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3 +#define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2MSK1 register. +// +//***************************************************************************** +#define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask +#define CAN_IF2MSK1_IDMSK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2MSK2 register. +// +//***************************************************************************** +#define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier +#define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction +#define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask +#define CAN_IF2MSK2_IDMSK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2ARB1 register. +// +//***************************************************************************** +#define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier +#define CAN_IF2ARB1_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2ARB2 register. +// +//***************************************************************************** +#define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid +#define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier +#define CAN_IF2ARB2_DIR 0x00002000 // Message Direction +#define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier +#define CAN_IF2ARB2_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2MCTL register. +// +//***************************************************************************** +#define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data +#define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost +#define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending +#define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask +#define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable +#define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable +#define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable +#define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request +#define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer +#define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code +#define CAN_IF2MCTL_DLC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2DA1 register. +// +//***************************************************************************** +#define CAN_IF2DA1_DATA_M 0x0000FFFF // Data +#define CAN_IF2DA1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2DA2 register. +// +//***************************************************************************** +#define CAN_IF2DA2_DATA_M 0x0000FFFF // Data +#define CAN_IF2DA2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2DB1 register. +// +//***************************************************************************** +#define CAN_IF2DB1_DATA_M 0x0000FFFF // Data +#define CAN_IF2DB1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2DB2 register. +// +//***************************************************************************** +#define CAN_IF2DB2_DATA_M 0x0000FFFF // Data +#define CAN_IF2DB2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_TXRQ1 register. +// +//***************************************************************************** +#define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits +#define CAN_TXRQ1_TXRQST_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_TXRQ2 register. +// +//***************************************************************************** +#define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits +#define CAN_TXRQ2_TXRQST_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_NWDA1 register. +// +//***************************************************************************** +#define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits +#define CAN_NWDA1_NEWDAT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_NWDA2 register. +// +//***************************************************************************** +#define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits +#define CAN_NWDA2_NEWDAT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_MSG1INT register. +// +//***************************************************************************** +#define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits +#define CAN_MSG1INT_INTPND_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_MSG2INT register. +// +//***************************************************************************** +#define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits +#define CAN_MSG2INT_INTPND_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_MSG1VAL register. +// +//***************************************************************************** +#define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits +#define CAN_MSG1VAL_MSGVAL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_MSG2VAL register. +// +//***************************************************************************** +#define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits +#define CAN_MSG2VAL_MSGVAL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FADDR register. +// +//***************************************************************************** +#define USB_FADDR_M 0x0000007F // Function Address +#define USB_FADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_POWER register. +// +//***************************************************************************** +#define USB_POWER_ISOUP 0x00000080 // Isochronous Update +#define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect +#define USB_POWER_RESET 0x00000008 // RESET Signaling +#define USB_POWER_RESUME 0x00000004 // RESUME Signaling +#define USB_POWER_SUSPEND 0x00000002 // SUSPEND Mode +#define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXIS register. +// +//***************************************************************************** +#define USB_TXIS_EP7 0x00000080 // TX Endpoint 7 Interrupt +#define USB_TXIS_EP6 0x00000040 // TX Endpoint 6 Interrupt +#define USB_TXIS_EP5 0x00000020 // TX Endpoint 5 Interrupt +#define USB_TXIS_EP4 0x00000010 // TX Endpoint 4 Interrupt +#define USB_TXIS_EP3 0x00000008 // TX Endpoint 3 Interrupt +#define USB_TXIS_EP2 0x00000004 // TX Endpoint 2 Interrupt +#define USB_TXIS_EP1 0x00000002 // TX Endpoint 1 Interrupt +#define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXIS register. +// +//***************************************************************************** +#define USB_RXIS_EP7 0x00000080 // RX Endpoint 7 Interrupt +#define USB_RXIS_EP6 0x00000040 // RX Endpoint 6 Interrupt +#define USB_RXIS_EP5 0x00000020 // RX Endpoint 5 Interrupt +#define USB_RXIS_EP4 0x00000010 // RX Endpoint 4 Interrupt +#define USB_RXIS_EP3 0x00000008 // RX Endpoint 3 Interrupt +#define USB_RXIS_EP2 0x00000004 // RX Endpoint 2 Interrupt +#define USB_RXIS_EP1 0x00000002 // RX Endpoint 1 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXIE register. +// +//***************************************************************************** +#define USB_TXIE_EP7 0x00000080 // TX Endpoint 7 Interrupt Enable +#define USB_TXIE_EP6 0x00000040 // TX Endpoint 6 Interrupt Enable +#define USB_TXIE_EP5 0x00000020 // TX Endpoint 5 Interrupt Enable +#define USB_TXIE_EP4 0x00000010 // TX Endpoint 4 Interrupt Enable +#define USB_TXIE_EP3 0x00000008 // TX Endpoint 3 Interrupt Enable +#define USB_TXIE_EP2 0x00000004 // TX Endpoint 2 Interrupt Enable +#define USB_TXIE_EP1 0x00000002 // TX Endpoint 1 Interrupt Enable +#define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt + // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXIE register. +// +//***************************************************************************** +#define USB_RXIE_EP7 0x00000080 // RX Endpoint 7 Interrupt Enable +#define USB_RXIE_EP6 0x00000040 // RX Endpoint 6 Interrupt Enable +#define USB_RXIE_EP5 0x00000020 // RX Endpoint 5 Interrupt Enable +#define USB_RXIE_EP4 0x00000010 // RX Endpoint 4 Interrupt Enable +#define USB_RXIE_EP3 0x00000008 // RX Endpoint 3 Interrupt Enable +#define USB_RXIE_EP2 0x00000004 // RX Endpoint 2 Interrupt Enable +#define USB_RXIE_EP1 0x00000002 // RX Endpoint 1 Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IS register. +// +//***************************************************************************** +#define USB_IS_VBUSERR 0x00000080 // VBUS Error (OTG only) +#define USB_IS_SESREQ 0x00000040 // SESSION REQUEST (OTG only) +#define USB_IS_DISCON 0x00000020 // Session Disconnect (OTG only) +#define USB_IS_CONN 0x00000010 // Session Connect +#define USB_IS_SOF 0x00000008 // Start of Frame +#define USB_IS_BABBLE 0x00000004 // Babble Detected +#define USB_IS_RESET 0x00000004 // RESET Signaling Detected +#define USB_IS_RESUME 0x00000002 // RESUME Signaling Detected +#define USB_IS_SUSPEND 0x00000001 // SUSPEND Signaling Detected + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IE register. +// +//***************************************************************************** +#define USB_IE_VBUSERR 0x00000080 // Enable VBUS Error Interrupt (OTG + // only) +#define USB_IE_SESREQ 0x00000040 // Enable Session Request (OTG + // only) +#define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt +#define USB_IE_CONN 0x00000010 // Enable Connect Interrupt +#define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt +#define USB_IE_BABBLE 0x00000004 // Enable Babble Interrupt +#define USB_IE_RESET 0x00000004 // Enable RESET Interrupt +#define USB_IE_RESUME 0x00000002 // Enable RESUME Interrupt +#define USB_IE_SUSPND 0x00000001 // Enable SUSPEND Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FRAME register. +// +//***************************************************************************** +#define USB_FRAME_M 0x000007FF // Frame Number +#define USB_FRAME_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPIDX register. +// +//***************************************************************************** +#define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index +#define USB_EPIDX_EPIDX_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TEST register. +// +//***************************************************************************** +#define USB_TEST_FORCEH 0x00000080 // Force Host Mode +#define USB_TEST_FIFOACC 0x00000040 // FIFO Access +#define USB_TEST_FORCEFS 0x00000020 // Force Full-Speed Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO0 register. +// +//***************************************************************************** +#define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO0_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO1 register. +// +//***************************************************************************** +#define USB_FIFO1_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO1_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO2 register. +// +//***************************************************************************** +#define USB_FIFO2_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO2_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO3 register. +// +//***************************************************************************** +#define USB_FIFO3_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO3_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO4 register. +// +//***************************************************************************** +#define USB_FIFO4_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO4_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO5 register. +// +//***************************************************************************** +#define USB_FIFO5_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO5_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO6 register. +// +//***************************************************************************** +#define USB_FIFO6_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO6_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO7 register. +// +//***************************************************************************** +#define USB_FIFO7_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO7_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DEVCTL register. +// +//***************************************************************************** +#define USB_DEVCTL_DEV 0x00000080 // Device Mode (OTG only) +#define USB_DEVCTL_FSDEV 0x00000040 // Full-Speed Device Detected +#define USB_DEVCTL_LSDEV 0x00000020 // Low-Speed Device Detected +#define USB_DEVCTL_VBUS_M 0x00000018 // VBUS Level (OTG only) +#define USB_DEVCTL_VBUS_NONE 0x00000000 // Below SessionEnd +#define USB_DEVCTL_VBUS_SEND 0x00000008 // Above SessionEnd, below AValid +#define USB_DEVCTL_VBUS_AVALID 0x00000010 // Above AValid, below VBUSValid +#define USB_DEVCTL_VBUS_VALID 0x00000018 // Above VBUSValid +#define USB_DEVCTL_HOST 0x00000004 // Host Mode +#define USB_DEVCTL_HOSTREQ 0x00000002 // Host Request (OTG only) +#define USB_DEVCTL_SESSION 0x00000001 // Session Start/End (OTG only) + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFIFOSZ register. +// +//***************************************************************************** +#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support +#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size +#define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8 +#define USB_TXFIFOSZ_SIZE_16 0x00000001 // 16 +#define USB_TXFIFOSZ_SIZE_32 0x00000002 // 32 +#define USB_TXFIFOSZ_SIZE_64 0x00000003 // 64 +#define USB_TXFIFOSZ_SIZE_128 0x00000004 // 128 +#define USB_TXFIFOSZ_SIZE_256 0x00000005 // 256 +#define USB_TXFIFOSZ_SIZE_512 0x00000006 // 512 +#define USB_TXFIFOSZ_SIZE_1024 0x00000007 // 1024 +#define USB_TXFIFOSZ_SIZE_2048 0x00000008 // 2048 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFIFOSZ register. +// +//***************************************************************************** +#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support +#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size +#define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8 +#define USB_RXFIFOSZ_SIZE_16 0x00000001 // 16 +#define USB_RXFIFOSZ_SIZE_32 0x00000002 // 32 +#define USB_RXFIFOSZ_SIZE_64 0x00000003 // 64 +#define USB_RXFIFOSZ_SIZE_128 0x00000004 // 128 +#define USB_RXFIFOSZ_SIZE_256 0x00000005 // 256 +#define USB_RXFIFOSZ_SIZE_512 0x00000006 // 512 +#define USB_RXFIFOSZ_SIZE_1024 0x00000007 // 1024 +#define USB_RXFIFOSZ_SIZE_2048 0x00000008 // 2048 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFIFOADD +// register. +// +//***************************************************************************** +#define USB_TXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address +#define USB_TXFIFOADD_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFIFOADD +// register. +// +//***************************************************************************** +#define USB_RXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address +#define USB_RXFIFOADD_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CONTIM register. +// +//***************************************************************************** +#define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait +#define USB_CONTIM_WTID_M 0x0000000F // Wait ID +#define USB_CONTIM_WTCON_S 4 +#define USB_CONTIM_WTID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VPLEN register. +// +//***************************************************************************** +#define USB_VPLEN_VPLEN_M 0x000000FF // VBUS Pulse Length +#define USB_VPLEN_VPLEN_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FSEOF register. +// +//***************************************************************************** +#define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap +#define USB_FSEOF_FSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LSEOF register. +// +//***************************************************************************** +#define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap +#define USB_LSEOF_LSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR0 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR0_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR0_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR0 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR0_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR0_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT0 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT0_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT0_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR1 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR1_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR1 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR1_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT1 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT1_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT1_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR1 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR1_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR1 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR1_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT1 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT1_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT1_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR2 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR2_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR2 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR2_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT2 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT2_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT2_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR2 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR2_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR2 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR2_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT2 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT2_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT2_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR3 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR3_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR3 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR3_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT3 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT3_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT3_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR3 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR3_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR3 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR3_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT3 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT3_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT3_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR4 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR4_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR4 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR4_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT4 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT4_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT4_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR4 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR4_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR4 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR4_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT4 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT4_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT4_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR5 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR5_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR5 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR5_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT5 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT5_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT5_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR5 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR5_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR5 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR5_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT5 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT5_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT5_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR6 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR6_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR6 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR6_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT6 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT6_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT6_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR6 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR6_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR6 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR6_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT6 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT6_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT6_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR7 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR7_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR7 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR7_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT7 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT7_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT7_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR7 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR7_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR7 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR7_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT7 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT7_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT7_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CSRL0 register. +// +//***************************************************************************** +#define USB_CSRL0_NAKTO 0x00000080 // NAK Timeout +#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear +#define USB_CSRL0_STATUS 0x00000040 // STATUS Packet +#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear +#define USB_CSRL0_REQPKT 0x00000020 // Request Packet +#define USB_CSRL0_STALL 0x00000020 // Send Stall +#define USB_CSRL0_SETEND 0x00000010 // Setup End +#define USB_CSRL0_ERROR 0x00000010 // Error +#define USB_CSRL0_DATAEND 0x00000008 // Data End +#define USB_CSRL0_SETUP 0x00000008 // Setup Packet +#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled +#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready +#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CSRH0 register. +// +//***************************************************************************** +#define USB_CSRH0_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_CSRH0_DT 0x00000002 // Data Toggle +#define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_COUNT0 register. +// +//***************************************************************************** +#define USB_COUNT0_COUNT_M 0x0000007F // FIFO Count +#define USB_COUNT0_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TYPE0 register. +// +//***************************************************************************** +#define USB_TYPE0_SPEED_M 0x000000C0 // Operating Speed +#define USB_TYPE0_SPEED_FULL 0x00000080 // Full +#define USB_TYPE0_SPEED_LOW 0x000000C0 // Low + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_NAKLMT register. +// +//***************************************************************************** +#define USB_NAKLMT_NAKLMT_M 0x0000001F // EP0 NAK Limit +#define USB_NAKLMT_NAKLMT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP1 register. +// +//***************************************************************************** +#define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP1_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL1 register. +// +//***************************************************************************** +#define USB_TXCSRL1_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL1_STALL 0x00000010 // Send STALL +#define USB_TXCSRL1_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL1_ERROR 0x00000004 // Error +#define USB_TXCSRL1_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH1 register. +// +//***************************************************************************** +#define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH1_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH1_MODE 0x00000020 // Mode +#define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH1_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH1_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP1 register. +// +//***************************************************************************** +#define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP1_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL1 register. +// +//***************************************************************************** +#define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL1_STALL 0x00000020 // Send STALL +#define USB_RXCSRL1_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL1_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL1_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL1_OVER 0x00000004 // Overrun +#define USB_RXCSRL1_ERROR 0x00000004 // Error +#define USB_RXCSRL1_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH1 register. +// +//***************************************************************************** +#define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH1_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH1_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH1_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH1_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH1_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT1 register. +// +//***************************************************************************** +#define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT1_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE1 register. +// +//***************************************************************************** +#define USB_TXTYPE1_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE1_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE1_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE1_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE1_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE1_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE1_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE1_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE1_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE1_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE1_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL1 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL1_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL1_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL1_TXPOLL_S \ + 0 +#define USB_TXINTERVAL1_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE1 register. +// +//***************************************************************************** +#define USB_RXTYPE1_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE1_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE1_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE1_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE1_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE1_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE1_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE1_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE1_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE1_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE1_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL1 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL1_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL1_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL1_TXPOLL_S \ + 0 +#define USB_RXINTERVAL1_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP2 register. +// +//***************************************************************************** +#define USB_TXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP2_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL2 register. +// +//***************************************************************************** +#define USB_TXCSRL2_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL2_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL2_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL2_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL2_STALL 0x00000010 // Send STALL +#define USB_TXCSRL2_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL2_ERROR 0x00000004 // Error +#define USB_TXCSRL2_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL2_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL2_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH2 register. +// +//***************************************************************************** +#define USB_TXCSRH2_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH2_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH2_MODE 0x00000020 // Mode +#define USB_TXCSRH2_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH2_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH2_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH2_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH2_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP2 register. +// +//***************************************************************************** +#define USB_RXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP2_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL2 register. +// +//***************************************************************************** +#define USB_RXCSRL2_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL2_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL2_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL2_STALL 0x00000020 // Send STALL +#define USB_RXCSRL2_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL2_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL2_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL2_ERROR 0x00000004 // Error +#define USB_RXCSRL2_OVER 0x00000004 // Overrun +#define USB_RXCSRL2_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL2_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH2 register. +// +//***************************************************************************** +#define USB_RXCSRH2_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH2_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH2_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH2_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH2_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH2_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH2_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH2_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT2 register. +// +//***************************************************************************** +#define USB_RXCOUNT2_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT2_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE2 register. +// +//***************************************************************************** +#define USB_TXTYPE2_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE2_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE2_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE2_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE2_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE2_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE2_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE2_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE2_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE2_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE2_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL2 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL2_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL2_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL2_NAKLMT_S \ + 0 +#define USB_TXINTERVAL2_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE2 register. +// +//***************************************************************************** +#define USB_RXTYPE2_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE2_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE2_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE2_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE2_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE2_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE2_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE2_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE2_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE2_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE2_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL2 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL2_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL2_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL2_TXPOLL_S \ + 0 +#define USB_RXINTERVAL2_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP3 register. +// +//***************************************************************************** +#define USB_TXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP3_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL3 register. +// +//***************************************************************************** +#define USB_TXCSRL3_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL3_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL3_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL3_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL3_STALL 0x00000010 // Send STALL +#define USB_TXCSRL3_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL3_ERROR 0x00000004 // Error +#define USB_TXCSRL3_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL3_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL3_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH3 register. +// +//***************************************************************************** +#define USB_TXCSRH3_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH3_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH3_MODE 0x00000020 // Mode +#define USB_TXCSRH3_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH3_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH3_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH3_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH3_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP3 register. +// +//***************************************************************************** +#define USB_RXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP3_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL3 register. +// +//***************************************************************************** +#define USB_RXCSRL3_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL3_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL3_STALL 0x00000020 // Send STALL +#define USB_RXCSRL3_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL3_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL3_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL3_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL3_ERROR 0x00000004 // Error +#define USB_RXCSRL3_OVER 0x00000004 // Overrun +#define USB_RXCSRL3_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL3_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH3 register. +// +//***************************************************************************** +#define USB_RXCSRH3_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH3_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH3_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH3_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH3_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH3_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH3_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH3_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT3 register. +// +//***************************************************************************** +#define USB_RXCOUNT3_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT3_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE3 register. +// +//***************************************************************************** +#define USB_TXTYPE3_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE3_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE3_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE3_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE3_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE3_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE3_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE3_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE3_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE3_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE3_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL3 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL3_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL3_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL3_TXPOLL_S \ + 0 +#define USB_TXINTERVAL3_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE3 register. +// +//***************************************************************************** +#define USB_RXTYPE3_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE3_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE3_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE3_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE3_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE3_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE3_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE3_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE3_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE3_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE3_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL3 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL3_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL3_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL3_TXPOLL_S \ + 0 +#define USB_RXINTERVAL3_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP4 register. +// +//***************************************************************************** +#define USB_TXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP4_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL4 register. +// +//***************************************************************************** +#define USB_TXCSRL4_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL4_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL4_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL4_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL4_STALL 0x00000010 // Send STALL +#define USB_TXCSRL4_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL4_ERROR 0x00000004 // Error +#define USB_TXCSRL4_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL4_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL4_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH4 register. +// +//***************************************************************************** +#define USB_TXCSRH4_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH4_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH4_MODE 0x00000020 // Mode +#define USB_TXCSRH4_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH4_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH4_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH4_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH4_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP4 register. +// +//***************************************************************************** +#define USB_RXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP4_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL4 register. +// +//***************************************************************************** +#define USB_RXCSRL4_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL4_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL4_STALL 0x00000020 // Send STALL +#define USB_RXCSRL4_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL4_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL4_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL4_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL4_OVER 0x00000004 // Overrun +#define USB_RXCSRL4_ERROR 0x00000004 // Error +#define USB_RXCSRL4_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL4_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH4 register. +// +//***************************************************************************** +#define USB_RXCSRH4_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH4_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH4_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH4_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH4_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH4_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH4_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH4_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH4_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT4 register. +// +//***************************************************************************** +#define USB_RXCOUNT4_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT4_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE4 register. +// +//***************************************************************************** +#define USB_TXTYPE4_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE4_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE4_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE4_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE4_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE4_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE4_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE4_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE4_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE4_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE4_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL4 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL4_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL4_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL4_NAKLMT_S \ + 0 +#define USB_TXINTERVAL4_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE4 register. +// +//***************************************************************************** +#define USB_RXTYPE4_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE4_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE4_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE4_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE4_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE4_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE4_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE4_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE4_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE4_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE4_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL4 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL4_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL4_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL4_NAKLMT_S \ + 0 +#define USB_RXINTERVAL4_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP5 register. +// +//***************************************************************************** +#define USB_TXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP5_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL5 register. +// +//***************************************************************************** +#define USB_TXCSRL5_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL5_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL5_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL5_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL5_STALL 0x00000010 // Send STALL +#define USB_TXCSRL5_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL5_ERROR 0x00000004 // Error +#define USB_TXCSRL5_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL5_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL5_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH5 register. +// +//***************************************************************************** +#define USB_TXCSRH5_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH5_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH5_MODE 0x00000020 // Mode +#define USB_TXCSRH5_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH5_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH5_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH5_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH5_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP5 register. +// +//***************************************************************************** +#define USB_RXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP5_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL5 register. +// +//***************************************************************************** +#define USB_RXCSRL5_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL5_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL5_STALL 0x00000020 // Send STALL +#define USB_RXCSRL5_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL5_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL5_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL5_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL5_ERROR 0x00000004 // Error +#define USB_RXCSRL5_OVER 0x00000004 // Overrun +#define USB_RXCSRL5_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL5_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH5 register. +// +//***************************************************************************** +#define USB_RXCSRH5_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH5_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH5_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH5_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH5_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH5_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH5_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH5_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH5_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT5 register. +// +//***************************************************************************** +#define USB_RXCOUNT5_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT5_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE5 register. +// +//***************************************************************************** +#define USB_TXTYPE5_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE5_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE5_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE5_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE5_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE5_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE5_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE5_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE5_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE5_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE5_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL5 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL5_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL5_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL5_NAKLMT_S \ + 0 +#define USB_TXINTERVAL5_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE5 register. +// +//***************************************************************************** +#define USB_RXTYPE5_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE5_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE5_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE5_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE5_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE5_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE5_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE5_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE5_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE5_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE5_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL5 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL5_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL5_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL5_TXPOLL_S \ + 0 +#define USB_RXINTERVAL5_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP6 register. +// +//***************************************************************************** +#define USB_TXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP6_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL6 register. +// +//***************************************************************************** +#define USB_TXCSRL6_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL6_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL6_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL6_STALL 0x00000010 // Send STALL +#define USB_TXCSRL6_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL6_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL6_ERROR 0x00000004 // Error +#define USB_TXCSRL6_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL6_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL6_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH6 register. +// +//***************************************************************************** +#define USB_TXCSRH6_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH6_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH6_MODE 0x00000020 // Mode +#define USB_TXCSRH6_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH6_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH6_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH6_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH6_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP6 register. +// +//***************************************************************************** +#define USB_RXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP6_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL6 register. +// +//***************************************************************************** +#define USB_RXCSRL6_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL6_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL6_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL6_STALL 0x00000020 // Send STALL +#define USB_RXCSRL6_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL6_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL6_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL6_ERROR 0x00000004 // Error +#define USB_RXCSRL6_OVER 0x00000004 // Overrun +#define USB_RXCSRL6_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL6_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH6 register. +// +//***************************************************************************** +#define USB_RXCSRH6_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH6_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH6_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH6_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH6_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH6_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH6_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH6_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH6_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT6 register. +// +//***************************************************************************** +#define USB_RXCOUNT6_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT6_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE6 register. +// +//***************************************************************************** +#define USB_TXTYPE6_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE6_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE6_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE6_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE6_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE6_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE6_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE6_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE6_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE6_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE6_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL6 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL6_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL6_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL6_TXPOLL_S \ + 0 +#define USB_TXINTERVAL6_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE6 register. +// +//***************************************************************************** +#define USB_RXTYPE6_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE6_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE6_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE6_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE6_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE6_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE6_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE6_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE6_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE6_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE6_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL6 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL6_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL6_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL6_NAKLMT_S \ + 0 +#define USB_RXINTERVAL6_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP7 register. +// +//***************************************************************************** +#define USB_TXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP7_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL7 register. +// +//***************************************************************************** +#define USB_TXCSRL7_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL7_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL7_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL7_STALL 0x00000010 // Send STALL +#define USB_TXCSRL7_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL7_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL7_ERROR 0x00000004 // Error +#define USB_TXCSRL7_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL7_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL7_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH7 register. +// +//***************************************************************************** +#define USB_TXCSRH7_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH7_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH7_MODE 0x00000020 // Mode +#define USB_TXCSRH7_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH7_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH7_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH7_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH7_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP7 register. +// +//***************************************************************************** +#define USB_RXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP7_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL7 register. +// +//***************************************************************************** +#define USB_RXCSRL7_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL7_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL7_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL7_STALL 0x00000020 // Send STALL +#define USB_RXCSRL7_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL7_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL7_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL7_ERROR 0x00000004 // Error +#define USB_RXCSRL7_OVER 0x00000004 // Overrun +#define USB_RXCSRL7_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL7_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH7 register. +// +//***************************************************************************** +#define USB_RXCSRH7_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH7_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH7_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH7_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH7_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH7_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH7_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH7_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH7_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT7 register. +// +//***************************************************************************** +#define USB_RXCOUNT7_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT7_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE7 register. +// +//***************************************************************************** +#define USB_TXTYPE7_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE7_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE7_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE7_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE7_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE7_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE7_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE7_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE7_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE7_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE7_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL7 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL7_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL7_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL7_NAKLMT_S \ + 0 +#define USB_TXINTERVAL7_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE7 register. +// +//***************************************************************************** +#define USB_RXTYPE7_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE7_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE7_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE7_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE7_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE7_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE7_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE7_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE7_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE7_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE7_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL7 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL7_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL7_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL7_NAKLMT_S \ + 0 +#define USB_RXINTERVAL7_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT1_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT1_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT2_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT2_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT3_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT3_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT4_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT5_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT6_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT7_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS +// register. +// +//***************************************************************************** +#define USB_RXDPKTBUFDIS_EP7 0x00000080 // EP7 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP6 0x00000040 // EP6 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP5 0x00000020 // EP5 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP4 0x00000010 // EP4 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP3 0x00000008 // EP3 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP2 0x00000004 // EP2 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP1 0x00000002 // EP1 RX Double-Packet Buffer + // Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS +// register. +// +//***************************************************************************** +#define USB_TXDPKTBUFDIS_EP7 0x00000080 // EP7 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP6 0x00000040 // EP6 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP5 0x00000020 // EP5 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP4 0x00000010 // EP4 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP3 0x00000008 // EP3 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP2 0x00000004 // EP2 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer + // Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPC register. +// +//***************************************************************************** +#define USB_EPC_PFLTACT_M 0x00000300 // Power Fault Action +#define USB_EPC_PFLTACT_UNCHG 0x00000000 // Unchanged +#define USB_EPC_PFLTACT_TRIS 0x00000100 // Tristate +#define USB_EPC_PFLTACT_LOW 0x00000200 // Low +#define USB_EPC_PFLTACT_HIGH 0x00000300 // High +#define USB_EPC_PFLTAEN 0x00000040 // Power Fault Action Enable +#define USB_EPC_PFLTSEN_HIGH 0x00000020 // Power Fault Sense +#define USB_EPC_PFLTEN 0x00000010 // Power Fault Input Enable +#define USB_EPC_EPENDE 0x00000004 // EPEN Drive Enable +#define USB_EPC_EPEN_M 0x00000003 // External Power Supply Enable + // Configuration +#define USB_EPC_EPEN_LOW 0x00000000 // Power Enable Active Low +#define USB_EPC_EPEN_HIGH 0x00000001 // Power Enable Active High +#define USB_EPC_EPEN_VBLOW 0x00000002 // Power Enable High if VBUS Low + // (OTG only) +#define USB_EPC_EPEN_VBHIGH 0x00000003 // Power Enable High if VBUS High + // (OTG only) + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCRIS register. +// +//***************************************************************************** +#define USB_EPCRIS_PF 0x00000001 // USB Power Fault Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCIM register. +// +//***************************************************************************** +#define USB_EPCIM_PF 0x00000001 // USB Power Fault Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCISC register. +// +//***************************************************************************** +#define USB_EPCISC_PF 0x00000001 // USB Power Fault Interrupt Status + // and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRRIS register. +// +//***************************************************************************** +#define USB_DRRIS_RESUME 0x00000001 // RESUME Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRIM register. +// +//***************************************************************************** +#define USB_DRIM_RESUME 0x00000001 // RESUME Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRISC register. +// +//***************************************************************************** +#define USB_DRISC_RESUME 0x00000001 // RESUME Interrupt Status and + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_GPCS register. +// +//***************************************************************************** +#define USB_GPCS_DEVMODOTG 0x00000002 // Enable Device Mode +#define USB_GPCS_DEVMOD 0x00000001 // Device Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDC register. +// +//***************************************************************************** +#define USB_VDC_VBDEN 0x00000001 // VBUS Droop Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCRIS register. +// +//***************************************************************************** +#define USB_VDCRIS_VD 0x00000001 // VBUS Droop Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCIM register. +// +//***************************************************************************** +#define USB_VDCIM_VD 0x00000001 // VBUS Droop Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCISC register. +// +//***************************************************************************** +#define USB_VDCISC_VD 0x00000001 // VBUS Droop Interrupt Status and + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVRIS register. +// +//***************************************************************************** +#define USB_IDVRIS_ID 0x00000001 // ID Valid Detect Raw Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVIM register. +// +//***************************************************************************** +#define USB_IDVIM_ID 0x00000001 // ID Valid Detect Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVISC register. +// +//***************************************************************************** +#define USB_IDVISC_ID 0x00000001 // ID Valid Detect Interrupt Status + // and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMASEL register. +// +//***************************************************************************** +#define USB_DMASEL_DMACTX_M 0x00F00000 // DMA C TX Select +#define USB_DMASEL_DMACRX_M 0x000F0000 // DMA C RX Select +#define USB_DMASEL_DMABTX_M 0x0000F000 // DMA B TX Select +#define USB_DMASEL_DMABRX_M 0x00000F00 // DMA B RX Select +#define USB_DMASEL_DMAATX_M 0x000000F0 // DMA A TX Select +#define USB_DMASEL_DMAARX_M 0x0000000F // DMA A RX Select +#define USB_DMASEL_DMACTX_S 20 +#define USB_DMASEL_DMACRX_S 16 +#define USB_DMASEL_DMABTX_S 12 +#define USB_DMASEL_DMABRX_S 8 +#define USB_DMASEL_DMAATX_S 4 +#define USB_DMASEL_DMAARX_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_PP register. +// +//***************************************************************************** +#define USB_PP_ECNT_M 0x0000FF00 // Endpoint Count +#define USB_PP_USB_M 0x000000C0 // USB Capability +#define USB_PP_USB_DEVICE 0x00000040 // DEVICE +#define USB_PP_USB_HOSTDEVICE 0x00000080 // HOST +#define USB_PP_USB_OTG 0x000000C0 // OTG +#define USB_PP_PHY 0x00000010 // PHY Present +#define USB_PP_TYPE_M 0x0000000F // Controller Type +#define USB_PP_TYPE_0 0x00000000 // The first-generation USB + // controller +#define USB_PP_ECNT_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EESIZE register. +// +//***************************************************************************** +#define EEPROM_EESIZE_BLKCNT_M 0x07FF0000 // Number of 16-Word Blocks +#define EEPROM_EESIZE_WORDCNT_M 0x0000FFFF // Number of 32-Bit Words +#define EEPROM_EESIZE_BLKCNT_S 16 +#define EEPROM_EESIZE_WORDCNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEBLOCK register. +// +//***************************************************************************** +#define EEPROM_EEBLOCK_BLOCK_M 0x0000FFFF // Current Block +#define EEPROM_EEBLOCK_BLOCK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEOFFSET +// register. +// +//***************************************************************************** +#define EEPROM_EEOFFSET_OFFSET_M \ + 0x0000000F // Current Address Offset +#define EEPROM_EEOFFSET_OFFSET_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EERDWR register. +// +//***************************************************************************** +#define EEPROM_EERDWR_VALUE_M 0xFFFFFFFF // EEPROM Read or Write Data +#define EEPROM_EERDWR_VALUE_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EERDWRINC +// register. +// +//***************************************************************************** +#define EEPROM_EERDWRINC_VALUE_M \ + 0xFFFFFFFF // EEPROM Read or Write Data with + // Increment +#define EEPROM_EERDWRINC_VALUE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEDONE register. +// +//***************************************************************************** +#define EEPROM_EEDONE_WRBUSY 0x00000020 // Write Busy +#define EEPROM_EEDONE_NOPERM 0x00000010 // Write Without Permission +#define EEPROM_EEDONE_WKCOPY 0x00000008 // Working on a Copy +#define EEPROM_EEDONE_WKERASE 0x00000004 // Working on an Erase +#define EEPROM_EEDONE_WORKING 0x00000001 // EEPROM Working + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EESUPP register. +// +//***************************************************************************** +#define EEPROM_EESUPP_PRETRY 0x00000008 // Programming Must Be Retried +#define EEPROM_EESUPP_ERETRY 0x00000004 // Erase Must Be Retried + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEUNLOCK +// register. +// +//***************************************************************************** +#define EEPROM_EEUNLOCK_UNLOCK_M \ + 0xFFFFFFFF // EEPROM Unlock + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEPROT register. +// +//***************************************************************************** +#define EEPROM_EEPROT_ACC 0x00000008 // Access Control +#define EEPROM_EEPROT_PROT_M 0x00000007 // Protection Control +#define EEPROM_EEPROT_PROT_RWNPW \ + 0x00000000 // This setting is the default. If + // there is no password, the block + // is not protected and is readable + // and writable +#define EEPROM_EEPROT_PROT_RWPW 0x00000001 // If there is a password, the + // block is readable or writable + // only when unlocked +#define EEPROM_EEPROT_PROT_RONPW \ + 0x00000002 // If there is no password, the + // block is readable, not writable + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEPASS0 register. +// +//***************************************************************************** +#define EEPROM_EEPASS0_PASS_M 0xFFFFFFFF // Password +#define EEPROM_EEPASS0_PASS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEPASS1 register. +// +//***************************************************************************** +#define EEPROM_EEPASS1_PASS_M 0xFFFFFFFF // Password +#define EEPROM_EEPASS1_PASS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEPASS2 register. +// +//***************************************************************************** +#define EEPROM_EEPASS2_PASS_M 0xFFFFFFFF // Password +#define EEPROM_EEPASS2_PASS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEINT register. +// +//***************************************************************************** +#define EEPROM_EEINT_INT 0x00000001 // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEHIDE register. +// +//***************************************************************************** +#define EEPROM_EEHIDE_HN_M 0xFFFFFFFE // Hide Block + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEDBGME register. +// +//***************************************************************************** +#define EEPROM_EEDBGME_KEY_M 0xFFFF0000 // Erase Key +#define EEPROM_EEDBGME_ME 0x00000001 // Mass Erase +#define EEPROM_EEDBGME_KEY_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_PP register. +// +//***************************************************************************** +#define EEPROM_PP_SIZE_M 0x0000001F // EEPROM Size +#define EEPROM_PP_SIZE_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSEXC_RIS register. +// +//***************************************************************************** +#define SYSEXC_RIS_FPIXCRIS 0x00000020 // Floating-Point Inexact Exception + // Raw Interrupt Status +#define SYSEXC_RIS_FPOFCRIS 0x00000010 // Floating-Point Overflow + // Exception Raw Interrupt Status +#define SYSEXC_RIS_FPUFCRIS 0x00000008 // Floating-Point Underflow + // Exception Raw Interrupt Status +#define SYSEXC_RIS_FPIOCRIS 0x00000004 // Floating-Point Invalid Operation + // Raw Interrupt Status +#define SYSEXC_RIS_FPDZCRIS 0x00000002 // Floating-Point Divide By 0 + // Exception Raw Interrupt Status +#define SYSEXC_RIS_FPIDCRIS 0x00000001 // Floating-Point Input Denormal + // Exception Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSEXC_IM register. +// +//***************************************************************************** +#define SYSEXC_IM_FPIXCIM 0x00000020 // Floating-Point Inexact Exception + // Interrupt Mask +#define SYSEXC_IM_FPOFCIM 0x00000010 // Floating-Point Overflow + // Exception Interrupt Mask +#define SYSEXC_IM_FPUFCIM 0x00000008 // Floating-Point Underflow + // Exception Interrupt Mask +#define SYSEXC_IM_FPIOCIM 0x00000004 // Floating-Point Invalid Operation + // Interrupt Mask +#define SYSEXC_IM_FPDZCIM 0x00000002 // Floating-Point Divide By 0 + // Exception Interrupt Mask +#define SYSEXC_IM_FPIDCIM 0x00000001 // Floating-Point Input Denormal + // Exception Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSEXC_MIS register. +// +//***************************************************************************** +#define SYSEXC_MIS_FPIXCMIS 0x00000020 // Floating-Point Inexact Exception + // Masked Interrupt Status +#define SYSEXC_MIS_FPOFCMIS 0x00000010 // Floating-Point Overflow + // Exception Masked Interrupt + // Status +#define SYSEXC_MIS_FPUFCMIS 0x00000008 // Floating-Point Underflow + // Exception Masked Interrupt + // Status +#define SYSEXC_MIS_FPIOCMIS 0x00000004 // Floating-Point Invalid Operation + // Masked Interrupt Status +#define SYSEXC_MIS_FPDZCMIS 0x00000002 // Floating-Point Divide By 0 + // Exception Masked Interrupt + // Status +#define SYSEXC_MIS_FPIDCMIS 0x00000001 // Floating-Point Input Denormal + // Exception Masked Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSEXC_IC register. +// +//***************************************************************************** +#define SYSEXC_IC_FPIXCIC 0x00000020 // Floating-Point Inexact Exception + // Interrupt Clear +#define SYSEXC_IC_FPOFCIC 0x00000010 // Floating-Point Overflow + // Exception Interrupt Clear +#define SYSEXC_IC_FPUFCIC 0x00000008 // Floating-Point Underflow + // Exception Interrupt Clear +#define SYSEXC_IC_FPIOCIC 0x00000004 // Floating-Point Invalid Operation + // Interrupt Clear +#define SYSEXC_IC_FPDZCIC 0x00000002 // Floating-Point Divide By 0 + // Exception Interrupt Clear +#define SYSEXC_IC_FPIDCIC 0x00000001 // Floating-Point Input Denormal + // Exception Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCC register. +// +//***************************************************************************** +#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter +#define HIB_RTCC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCM0 register. +// +//***************************************************************************** +#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0 +#define HIB_RTCM0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCLD register. +// +//***************************************************************************** +#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load +#define HIB_RTCLD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_CTL register. +// +//***************************************************************************** +#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable +#define HIB_CTL_OSCDRV 0x00020000 // Oscillator Drive Capability +#define HIB_CTL_OSCBYP 0x00010000 // Oscillator Bypass +#define HIB_CTL_VBATSEL_M 0x00006000 // Select for Low-Battery + // Comparator +#define HIB_CTL_VBATSEL_1_9V 0x00000000 // 1.9 Volts +#define HIB_CTL_VBATSEL_2_1V 0x00002000 // 2.1 Volts (default) +#define HIB_CTL_VBATSEL_2_3V 0x00004000 // 2.3 Volts +#define HIB_CTL_VBATSEL_2_5V 0x00006000 // 2.5 Volts +#define HIB_CTL_BATCHK 0x00000400 // Check Battery Status +#define HIB_CTL_BATWKEN 0x00000200 // Wake on Low Battery +#define HIB_CTL_VDD3ON 0x00000100 // VDD Powered +#define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable +#define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable +#define HIB_CTL_PINWEN 0x00000010 // External Wake Pin Enable +#define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable +#define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request +#define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_IM register. +// +//***************************************************************************** +#define HIB_IM_WC 0x00000010 // External Write Complete/Capable + // Interrupt Mask +#define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask +#define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt + // Mask +#define HIB_IM_RTCALT0 0x00000001 // RTC Alert 0 Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RIS register. +// +//***************************************************************************** +#define HIB_RIS_WC 0x00000010 // Write Complete/Capable Raw + // Interrupt Status +#define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt + // Status +#define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw + // Interrupt Status +#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert 0 Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_MIS register. +// +//***************************************************************************** +#define HIB_MIS_WC 0x00000010 // Write Complete/Capable Masked + // Interrupt Status +#define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked + // Interrupt Status +#define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked + // Interrupt Status +#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert 0 Masked Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_IC register. +// +//***************************************************************************** +#define HIB_IC_WC 0x00000010 // Write Complete/Capable Interrupt + // Clear +#define HIB_IC_EXTW 0x00000008 // External Wake-Up Interrupt Clear +#define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Interrupt + // Clear +#define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCT register. +// +//***************************************************************************** +#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value +#define HIB_RTCT_TRIM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCSS register. +// +//***************************************************************************** +#define HIB_RTCSS_RTCSSM_M 0x7FFF0000 // RTC Sub Seconds Match +#define HIB_RTCSS_RTCSSC_M 0x00007FFF // RTC Sub Seconds Count +#define HIB_RTCSS_RTCSSM_S 16 +#define HIB_RTCSS_RTCSSC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_DATA register. +// +//***************************************************************************** +#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV Data +#define HIB_DATA_RTD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMA register. +// +//***************************************************************************** +#define FLASH_FMA_OFFSET_M 0x0003FFFF // Address Offset +#define FLASH_FMA_OFFSET_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMD register. +// +//***************************************************************************** +#define FLASH_FMD_DATA_M 0xFFFFFFFF // Data Value +#define FLASH_FMD_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMC register. +// +//***************************************************************************** +#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key +#define FLASH_FMC_COMT 0x00000008 // Commit Register Value +#define FLASH_FMC_MERASE 0x00000004 // Mass Erase Flash Memory +#define FLASH_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory +#define FLASH_FMC_WRITE 0x00000001 // Write a Word into Flash Memory + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FCRIS register. +// +//***************************************************************************** +#define FLASH_FCRIS_PROGRIS 0x00002000 // Program Verify Error Raw + // Interrupt Status +#define FLASH_FCRIS_ERRIS 0x00000800 // Erase Verify Error Raw Interrupt + // Status +#define FLASH_FCRIS_INVDRIS 0x00000400 // Invalid Data Raw Interrupt + // Status +#define FLASH_FCRIS_VOLTRIS 0x00000200 // Pump Voltage Raw Interrupt + // Status +#define FLASH_FCRIS_ERIS 0x00000004 // EEPROM Raw Interrupt Status +#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt Status +#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FCIM register. +// +//***************************************************************************** +#define FLASH_FCIM_PROGMASK 0x00002000 // PROGVER Interrupt Mask +#define FLASH_FCIM_ERMASK 0x00000800 // ERVER Interrupt Mask +#define FLASH_FCIM_INVDMASK 0x00000400 // Invalid Data Interrupt Mask +#define FLASH_FCIM_VOLTMASK 0x00000200 // VOLT Interrupt Mask +#define FLASH_FCIM_EMASK 0x00000004 // EEPROM Interrupt Mask +#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask +#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FCMISC register. +// +//***************************************************************************** +#define FLASH_FCMISC_PROGMISC 0x00002000 // PROGVER Masked Interrupt Status + // and Clear +#define FLASH_FCMISC_ERMISC 0x00000800 // ERVER Masked Interrupt Status + // and Clear +#define FLASH_FCMISC_INVDMISC 0x00000400 // Invalid Data Masked Interrupt + // Status and Clear +#define FLASH_FCMISC_VOLTMISC 0x00000200 // VOLT Masked Interrupt Status and + // Clear +#define FLASH_FCMISC_EMISC 0x00000004 // EEPROM Masked Interrupt Status + // and Clear +#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt + // Status and Clear +#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status + // and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMC2 register. +// +//***************************************************************************** +#define FLASH_FMC2_WRBUF 0x00000001 // Buffered Flash Memory Write + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FWBVAL register. +// +//***************************************************************************** +#define FLASH_FWBVAL_FWB_M 0xFFFFFFFF // Flash Memory Write Buffer + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FWBN register. +// +//***************************************************************************** +#define FLASH_FWBN_DATA_M 0xFFFFFFFF // Data + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FSIZE register. +// +//***************************************************************************** +#define FLASH_FSIZE_SIZE_M 0x0000FFFF // Flash Size +#define FLASH_FSIZE_SIZE_256KB 0x0000007F // 256 KB of Flash + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_SSIZE register. +// +//***************************************************************************** +#define FLASH_SSIZE_SIZE_M 0x0000FFFF // SRAM Size +#define FLASH_SSIZE_SIZE_32KB 0x0000007F // 32 KB of SRAM + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_ROMSWMAP register. +// +//***************************************************************************** +#define FLASH_ROMSWMAP_SAFERTOS 0x00000001 // SafeRTOS Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_RMCTL register. +// +//***************************************************************************** +#define FLASH_RMCTL_BA 0x00000001 // Boot Alias + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_BOOTCFG register. +// +//***************************************************************************** +#define FLASH_BOOTCFG_NW 0x80000000 // Not Written +#define FLASH_BOOTCFG_PORT_M 0x0000E000 // Boot GPIO Port +#define FLASH_BOOTCFG_PORT_A 0x00000000 // Port A +#define FLASH_BOOTCFG_PORT_B 0x00002000 // Port B +#define FLASH_BOOTCFG_PORT_C 0x00004000 // Port C +#define FLASH_BOOTCFG_PORT_D 0x00006000 // Port D +#define FLASH_BOOTCFG_PORT_E 0x00008000 // Port E +#define FLASH_BOOTCFG_PORT_F 0x0000A000 // Port F +#define FLASH_BOOTCFG_PORT_G 0x0000C000 // Port G +#define FLASH_BOOTCFG_PORT_H 0x0000E000 // Port H +#define FLASH_BOOTCFG_PIN_M 0x00001C00 // Boot GPIO Pin +#define FLASH_BOOTCFG_PIN_0 0x00000000 // Pin 0 +#define FLASH_BOOTCFG_PIN_1 0x00000400 // Pin 1 +#define FLASH_BOOTCFG_PIN_2 0x00000800 // Pin 2 +#define FLASH_BOOTCFG_PIN_3 0x00000C00 // Pin 3 +#define FLASH_BOOTCFG_PIN_4 0x00001000 // Pin 4 +#define FLASH_BOOTCFG_PIN_5 0x00001400 // Pin 5 +#define FLASH_BOOTCFG_PIN_6 0x00001800 // Pin 6 +#define FLASH_BOOTCFG_PIN_7 0x00001C00 // Pin 7 +#define FLASH_BOOTCFG_POL 0x00000200 // Boot GPIO Polarity +#define FLASH_BOOTCFG_EN 0x00000100 // Boot GPIO Enable +#define FLASH_BOOTCFG_KEY 0x00000010 // KEY Select +#define FLASH_BOOTCFG_DBG1 0x00000002 // Debug Control 1 +#define FLASH_BOOTCFG_DBG0 0x00000001 // Debug Control 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USERREG0 register. +// +//***************************************************************************** +#define FLASH_USERREG0_DATA_M 0xFFFFFFFF // User Data +#define FLASH_USERREG0_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USERREG1 register. +// +//***************************************************************************** +#define FLASH_USERREG1_DATA_M 0xFFFFFFFF // User Data +#define FLASH_USERREG1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USERREG2 register. +// +//***************************************************************************** +#define FLASH_USERREG2_DATA_M 0xFFFFFFFF // User Data +#define FLASH_USERREG2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USERREG3 register. +// +//***************************************************************************** +#define FLASH_USERREG3_DATA_M 0xFFFFFFFF // User Data +#define FLASH_USERREG3_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DID0 register. +// +//***************************************************************************** +#define SYSCTL_DID0_VER_M 0x70000000 // DID0 Version +#define SYSCTL_DID0_VER_1 0x10000000 // Second version of the DID0 + // register format. +#define SYSCTL_DID0_CLASS_M 0x00FF0000 // Device Class +#define SYSCTL_DID0_CLASS_TM4C123 \ + 0x00050000 // Tiva TM4C123x and TM4E123x + // microcontrollers +#define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major Revision +#define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device) +#define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer + // revision) +#define SYSCTL_DID0_MAJ_REVC 0x00000200 // Revision C (second base layer + // revision) +#define SYSCTL_DID0_MIN_M 0x000000FF // Minor Revision +#define SYSCTL_DID0_MIN_0 0x00000000 // Initial device, or a major + // revision update +#define SYSCTL_DID0_MIN_1 0x00000001 // First metal layer change +#define SYSCTL_DID0_MIN_2 0x00000002 // Second metal layer change + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DID1 register. +// +//***************************************************************************** +#define SYSCTL_DID1_VER_M 0xF0000000 // DID1 Version +#define SYSCTL_DID1_VER_1 0x10000000 // fury_ib +#define SYSCTL_DID1_FAM_M 0x0F000000 // Family +#define SYSCTL_DID1_FAM_TIVA 0x00000000 // Tiva family of microcontollers +#define SYSCTL_DID1_PRTNO_M 0x00FF0000 // Part Number +#define SYSCTL_DID1_PRTNO_TM4C123GH6PZ \ + 0x00C10000 // TM4C123GH6PZ +#define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count +#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100-pin LQFP package +#define SYSCTL_DID1_PINCNT_64 0x00006000 // 64-pin LQFP package +#define SYSCTL_DID1_PINCNT_144 0x00008000 // 144-pin LQFP package +#define SYSCTL_DID1_PINCNT_157 0x0000A000 // 157-pin BGA package +#define SYSCTL_DID1_PINCNT_128 0x0000C000 // 128-pin TQFP package +#define SYSCTL_DID1_TEMP_M 0x000000E0 // Temperature Range +#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temperature range +#define SYSCTL_DID1_TEMP_E 0x00000040 // Extended temperature range +#define SYSCTL_DID1_TEMP_IE 0x00000060 // Available in both industrial + // temperature range (-40C to 85C) + // and extended temperature range + // (-40C to 105C) devices. See +#define SYSCTL_DID1_PKG_M 0x00000018 // Package Type +#define SYSCTL_DID1_PKG_QFP 0x00000008 // QFP package +#define SYSCTL_DID1_PKG_BGA 0x00000010 // BGA package +#define SYSCTL_DID1_ROHS 0x00000004 // RoHS-Compliance +#define SYSCTL_DID1_QUAL_M 0x00000003 // Qualification Status +#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering Sample (unqualified) +#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot Production (unqualified) +#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully Qualified + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC0 register. +// +//***************************************************************************** +#define SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 // SRAM Size +#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_6KB 0x00170000 // 6 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_12KB 0x002F0000 // 12 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_20KB 0x004F0000 // 20 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_24KB 0x005F0000 // 24 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM +#define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF // Flash Size +#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of Flash +#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of Flash +#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of Flash +#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of Flash +#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of Flash +#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of Flash +#define SYSCTL_DC0_FLASHSZ_192K 0x0000005F // 192 KB of Flash +#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of Flash + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC1 register. +// +//***************************************************************************** +#define SYSCTL_DC1_WDT1 0x10000000 // Watchdog Timer1 Present +#define SYSCTL_DC1_CAN1 0x02000000 // CAN Module 1 Present +#define SYSCTL_DC1_CAN0 0x01000000 // CAN Module 0 Present +#define SYSCTL_DC1_PWM1 0x00200000 // PWM Module 1 Present +#define SYSCTL_DC1_PWM0 0x00100000 // PWM Module 0 Present +#define SYSCTL_DC1_ADC1 0x00020000 // ADC Module 1 Present +#define SYSCTL_DC1_ADC0 0x00010000 // ADC Module 0 Present +#define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 // System Clock Divider +#define SYSCTL_DC1_MINSYSDIV_80 0x00002000 // Specifies an 80-MHz CPU clock + // with a PLL divider of 2.5 +#define SYSCTL_DC1_MINSYSDIV_50 0x00003000 // Specifies a 50-MHz CPU clock + // with a PLL divider of 4 +#define SYSCTL_DC1_MINSYSDIV_40 0x00004000 // Specifies a 40-MHz CPU clock + // with a PLL divider of 5 +#define SYSCTL_DC1_MINSYSDIV_25 0x00007000 // Specifies a 25-MHz clock with a + // PLL divider of 8 +#define SYSCTL_DC1_MINSYSDIV_20 0x00009000 // Specifies a 20-MHz clock with a + // PLL divider of 10 +#define SYSCTL_DC1_ADC1SPD_M 0x00000C00 // Max ADC1 Speed +#define SYSCTL_DC1_ADC1SPD_125K 0x00000000 // 125K samples/second +#define SYSCTL_DC1_ADC1SPD_250K 0x00000400 // 250K samples/second +#define SYSCTL_DC1_ADC1SPD_500K 0x00000800 // 500K samples/second +#define SYSCTL_DC1_ADC1SPD_1M 0x00000C00 // 1M samples/second +#define SYSCTL_DC1_ADC0SPD_M 0x00000300 // Max ADC0 Speed +#define SYSCTL_DC1_ADC0SPD_125K 0x00000000 // 125K samples/second +#define SYSCTL_DC1_ADC0SPD_250K 0x00000100 // 250K samples/second +#define SYSCTL_DC1_ADC0SPD_500K 0x00000200 // 500K samples/second +#define SYSCTL_DC1_ADC0SPD_1M 0x00000300 // 1M samples/second +#define SYSCTL_DC1_MPU 0x00000080 // MPU Present +#define SYSCTL_DC1_HIB 0x00000040 // Hibernation Module Present +#define SYSCTL_DC1_TEMP 0x00000020 // Temp Sensor Present +#define SYSCTL_DC1_PLL 0x00000010 // PLL Present +#define SYSCTL_DC1_WDT0 0x00000008 // Watchdog Timer 0 Present +#define SYSCTL_DC1_SWO 0x00000004 // SWO Trace Port Present +#define SYSCTL_DC1_SWD 0x00000002 // SWD Present +#define SYSCTL_DC1_JTAG 0x00000001 // JTAG Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC2 register. +// +//***************************************************************************** +#define SYSCTL_DC2_EPI0 0x40000000 // EPI Module 0 Present +#define SYSCTL_DC2_I2S0 0x10000000 // I2S Module 0 Present +#define SYSCTL_DC2_COMP2 0x04000000 // Analog Comparator 2 Present +#define SYSCTL_DC2_COMP1 0x02000000 // Analog Comparator 1 Present +#define SYSCTL_DC2_COMP0 0x01000000 // Analog Comparator 0 Present +#define SYSCTL_DC2_TIMER3 0x00080000 // Timer Module 3 Present +#define SYSCTL_DC2_TIMER2 0x00040000 // Timer Module 2 Present +#define SYSCTL_DC2_TIMER1 0x00020000 // Timer Module 1 Present +#define SYSCTL_DC2_TIMER0 0x00010000 // Timer Module 0 Present +#define SYSCTL_DC2_I2C1HS 0x00008000 // I2C Module 1 Speed +#define SYSCTL_DC2_I2C1 0x00004000 // I2C Module 1 Present +#define SYSCTL_DC2_I2C0HS 0x00002000 // I2C Module 0 Speed +#define SYSCTL_DC2_I2C0 0x00001000 // I2C Module 0 Present +#define SYSCTL_DC2_QEI1 0x00000200 // QEI Module 1 Present +#define SYSCTL_DC2_QEI0 0x00000100 // QEI Module 0 Present +#define SYSCTL_DC2_SSI1 0x00000020 // SSI Module 1 Present +#define SYSCTL_DC2_SSI0 0x00000010 // SSI Module 0 Present +#define SYSCTL_DC2_UART2 0x00000004 // UART Module 2 Present +#define SYSCTL_DC2_UART1 0x00000002 // UART Module 1 Present +#define SYSCTL_DC2_UART0 0x00000001 // UART Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC3 register. +// +//***************************************************************************** +#define SYSCTL_DC3_32KHZ 0x80000000 // 32KHz Input Clock Available +#define SYSCTL_DC3_CCP5 0x20000000 // T2CCP1 Pin Present +#define SYSCTL_DC3_CCP4 0x10000000 // T2CCP0 Pin Present +#define SYSCTL_DC3_CCP3 0x08000000 // T1CCP1 Pin Present +#define SYSCTL_DC3_CCP2 0x04000000 // T1CCP0 Pin Present +#define SYSCTL_DC3_CCP1 0x02000000 // T0CCP1 Pin Present +#define SYSCTL_DC3_CCP0 0x01000000 // T0CCP0 Pin Present +#define SYSCTL_DC3_ADC0AIN7 0x00800000 // ADC Module 0 AIN7 Pin Present +#define SYSCTL_DC3_ADC0AIN6 0x00400000 // ADC Module 0 AIN6 Pin Present +#define SYSCTL_DC3_ADC0AIN5 0x00200000 // ADC Module 0 AIN5 Pin Present +#define SYSCTL_DC3_ADC0AIN4 0x00100000 // ADC Module 0 AIN4 Pin Present +#define SYSCTL_DC3_ADC0AIN3 0x00080000 // ADC Module 0 AIN3 Pin Present +#define SYSCTL_DC3_ADC0AIN2 0x00040000 // ADC Module 0 AIN2 Pin Present +#define SYSCTL_DC3_ADC0AIN1 0x00020000 // ADC Module 0 AIN1 Pin Present +#define SYSCTL_DC3_ADC0AIN0 0x00010000 // ADC Module 0 AIN0 Pin Present +#define SYSCTL_DC3_PWMFAULT 0x00008000 // PWM Fault Pin Present +#define SYSCTL_DC3_C2O 0x00004000 // C2o Pin Present +#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ Pin Present +#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- Pin Present +#define SYSCTL_DC3_C1O 0x00000800 // C1o Pin Present +#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ Pin Present +#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- Pin Present +#define SYSCTL_DC3_C0O 0x00000100 // C0o Pin Present +#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ Pin Present +#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- Pin Present +#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 Pin Present +#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 Pin Present +#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 Pin Present +#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 Pin Present +#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 Pin Present +#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 Pin Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC4 register. +// +//***************************************************************************** +#define SYSCTL_DC4_EPHY0 0x40000000 // Ethernet PHY Layer 0 Present +#define SYSCTL_DC4_EMAC0 0x10000000 // Ethernet MAC Layer 0 Present +#define SYSCTL_DC4_E1588 0x01000000 // 1588 Capable +#define SYSCTL_DC4_PICAL 0x00040000 // PIOSC Calibrate +#define SYSCTL_DC4_CCP7 0x00008000 // T3CCP1 Pin Present +#define SYSCTL_DC4_CCP6 0x00004000 // T3CCP0 Pin Present +#define SYSCTL_DC4_UDMA 0x00002000 // Micro-DMA Module Present +#define SYSCTL_DC4_ROM 0x00001000 // Internal Code ROM Present +#define SYSCTL_DC4_GPIOJ 0x00000100 // GPIO Port J Present +#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO Port H Present +#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO Port G Present +#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO Port F Present +#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO Port E Present +#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO Port D Present +#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO Port C Present +#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO Port B Present +#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO Port A Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC5 register. +// +//***************************************************************************** +#define SYSCTL_DC5_PWMFAULT3 0x08000000 // PWM Fault 3 Pin Present +#define SYSCTL_DC5_PWMFAULT2 0x04000000 // PWM Fault 2 Pin Present +#define SYSCTL_DC5_PWMFAULT1 0x02000000 // PWM Fault 1 Pin Present +#define SYSCTL_DC5_PWMFAULT0 0x01000000 // PWM Fault 0 Pin Present +#define SYSCTL_DC5_PWMEFLT 0x00200000 // PWM Extended Fault Active +#define SYSCTL_DC5_PWMESYNC 0x00100000 // PWM Extended SYNC Active +#define SYSCTL_DC5_PWM7 0x00000080 // PWM7 Pin Present +#define SYSCTL_DC5_PWM6 0x00000040 // PWM6 Pin Present +#define SYSCTL_DC5_PWM5 0x00000020 // PWM5 Pin Present +#define SYSCTL_DC5_PWM4 0x00000010 // PWM4 Pin Present +#define SYSCTL_DC5_PWM3 0x00000008 // PWM3 Pin Present +#define SYSCTL_DC5_PWM2 0x00000004 // PWM2 Pin Present +#define SYSCTL_DC5_PWM1 0x00000002 // PWM1 Pin Present +#define SYSCTL_DC5_PWM0 0x00000001 // PWM0 Pin Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC6 register. +// +//***************************************************************************** +#define SYSCTL_DC6_USB0PHY 0x00000010 // USB Module 0 PHY Present +#define SYSCTL_DC6_USB0_M 0x00000003 // USB Module 0 Present +#define SYSCTL_DC6_USB0_DEV 0x00000001 // USB0 is Device Only +#define SYSCTL_DC6_USB0_HOSTDEV 0x00000002 // USB is Device or Host +#define SYSCTL_DC6_USB0_OTG 0x00000003 // USB0 is OTG + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC7 register. +// +//***************************************************************************** +#define SYSCTL_DC7_DMACH30 0x40000000 // DMA Channel 30 +#define SYSCTL_DC7_DMACH29 0x20000000 // DMA Channel 29 +#define SYSCTL_DC7_DMACH28 0x10000000 // DMA Channel 28 +#define SYSCTL_DC7_DMACH27 0x08000000 // DMA Channel 27 +#define SYSCTL_DC7_DMACH26 0x04000000 // DMA Channel 26 +#define SYSCTL_DC7_DMACH25 0x02000000 // DMA Channel 25 +#define SYSCTL_DC7_DMACH24 0x01000000 // DMA Channel 24 +#define SYSCTL_DC7_DMACH23 0x00800000 // DMA Channel 23 +#define SYSCTL_DC7_DMACH22 0x00400000 // DMA Channel 22 +#define SYSCTL_DC7_DMACH21 0x00200000 // DMA Channel 21 +#define SYSCTL_DC7_DMACH20 0x00100000 // DMA Channel 20 +#define SYSCTL_DC7_DMACH19 0x00080000 // DMA Channel 19 +#define SYSCTL_DC7_DMACH18 0x00040000 // DMA Channel 18 +#define SYSCTL_DC7_DMACH17 0x00020000 // DMA Channel 17 +#define SYSCTL_DC7_DMACH16 0x00010000 // DMA Channel 16 +#define SYSCTL_DC7_DMACH15 0x00008000 // DMA Channel 15 +#define SYSCTL_DC7_DMACH14 0x00004000 // DMA Channel 14 +#define SYSCTL_DC7_DMACH13 0x00002000 // DMA Channel 13 +#define SYSCTL_DC7_DMACH12 0x00001000 // DMA Channel 12 +#define SYSCTL_DC7_DMACH11 0x00000800 // DMA Channel 11 +#define SYSCTL_DC7_DMACH10 0x00000400 // DMA Channel 10 +#define SYSCTL_DC7_DMACH9 0x00000200 // DMA Channel 9 +#define SYSCTL_DC7_DMACH8 0x00000100 // DMA Channel 8 +#define SYSCTL_DC7_DMACH7 0x00000080 // DMA Channel 7 +#define SYSCTL_DC7_DMACH6 0x00000040 // DMA Channel 6 +#define SYSCTL_DC7_DMACH5 0x00000020 // DMA Channel 5 +#define SYSCTL_DC7_DMACH4 0x00000010 // DMA Channel 4 +#define SYSCTL_DC7_DMACH3 0x00000008 // DMA Channel 3 +#define SYSCTL_DC7_DMACH2 0x00000004 // DMA Channel 2 +#define SYSCTL_DC7_DMACH1 0x00000002 // DMA Channel 1 +#define SYSCTL_DC7_DMACH0 0x00000001 // DMA Channel 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC8 register. +// +//***************************************************************************** +#define SYSCTL_DC8_ADC1AIN15 0x80000000 // ADC Module 1 AIN15 Pin Present +#define SYSCTL_DC8_ADC1AIN14 0x40000000 // ADC Module 1 AIN14 Pin Present +#define SYSCTL_DC8_ADC1AIN13 0x20000000 // ADC Module 1 AIN13 Pin Present +#define SYSCTL_DC8_ADC1AIN12 0x10000000 // ADC Module 1 AIN12 Pin Present +#define SYSCTL_DC8_ADC1AIN11 0x08000000 // ADC Module 1 AIN11 Pin Present +#define SYSCTL_DC8_ADC1AIN10 0x04000000 // ADC Module 1 AIN10 Pin Present +#define SYSCTL_DC8_ADC1AIN9 0x02000000 // ADC Module 1 AIN9 Pin Present +#define SYSCTL_DC8_ADC1AIN8 0x01000000 // ADC Module 1 AIN8 Pin Present +#define SYSCTL_DC8_ADC1AIN7 0x00800000 // ADC Module 1 AIN7 Pin Present +#define SYSCTL_DC8_ADC1AIN6 0x00400000 // ADC Module 1 AIN6 Pin Present +#define SYSCTL_DC8_ADC1AIN5 0x00200000 // ADC Module 1 AIN5 Pin Present +#define SYSCTL_DC8_ADC1AIN4 0x00100000 // ADC Module 1 AIN4 Pin Present +#define SYSCTL_DC8_ADC1AIN3 0x00080000 // ADC Module 1 AIN3 Pin Present +#define SYSCTL_DC8_ADC1AIN2 0x00040000 // ADC Module 1 AIN2 Pin Present +#define SYSCTL_DC8_ADC1AIN1 0x00020000 // ADC Module 1 AIN1 Pin Present +#define SYSCTL_DC8_ADC1AIN0 0x00010000 // ADC Module 1 AIN0 Pin Present +#define SYSCTL_DC8_ADC0AIN15 0x00008000 // ADC Module 0 AIN15 Pin Present +#define SYSCTL_DC8_ADC0AIN14 0x00004000 // ADC Module 0 AIN14 Pin Present +#define SYSCTL_DC8_ADC0AIN13 0x00002000 // ADC Module 0 AIN13 Pin Present +#define SYSCTL_DC8_ADC0AIN12 0x00001000 // ADC Module 0 AIN12 Pin Present +#define SYSCTL_DC8_ADC0AIN11 0x00000800 // ADC Module 0 AIN11 Pin Present +#define SYSCTL_DC8_ADC0AIN10 0x00000400 // ADC Module 0 AIN10 Pin Present +#define SYSCTL_DC8_ADC0AIN9 0x00000200 // ADC Module 0 AIN9 Pin Present +#define SYSCTL_DC8_ADC0AIN8 0x00000100 // ADC Module 0 AIN8 Pin Present +#define SYSCTL_DC8_ADC0AIN7 0x00000080 // ADC Module 0 AIN7 Pin Present +#define SYSCTL_DC8_ADC0AIN6 0x00000040 // ADC Module 0 AIN6 Pin Present +#define SYSCTL_DC8_ADC0AIN5 0x00000020 // ADC Module 0 AIN5 Pin Present +#define SYSCTL_DC8_ADC0AIN4 0x00000010 // ADC Module 0 AIN4 Pin Present +#define SYSCTL_DC8_ADC0AIN3 0x00000008 // ADC Module 0 AIN3 Pin Present +#define SYSCTL_DC8_ADC0AIN2 0x00000004 // ADC Module 0 AIN2 Pin Present +#define SYSCTL_DC8_ADC0AIN1 0x00000002 // ADC Module 0 AIN1 Pin Present +#define SYSCTL_DC8_ADC0AIN0 0x00000001 // ADC Module 0 AIN0 Pin Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PBORCTL register. +// +//***************************************************************************** +#define SYSCTL_PBORCTL_BOR0 0x00000004 // VDD under BOR0 Event Action +#define SYSCTL_PBORCTL_BOR1 0x00000002 // VDD under BOR1 Event Action + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCR0 register. +// +//***************************************************************************** +#define SYSCTL_SRCR0_WDT1 0x10000000 // WDT1 Reset Control +#define SYSCTL_SRCR0_CAN1 0x02000000 // CAN1 Reset Control +#define SYSCTL_SRCR0_CAN0 0x01000000 // CAN0 Reset Control +#define SYSCTL_SRCR0_PWM0 0x00100000 // PWM Reset Control +#define SYSCTL_SRCR0_ADC1 0x00020000 // ADC1 Reset Control +#define SYSCTL_SRCR0_ADC0 0x00010000 // ADC0 Reset Control +#define SYSCTL_SRCR0_HIB 0x00000040 // HIB Reset Control +#define SYSCTL_SRCR0_WDT0 0x00000008 // WDT0 Reset Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCR1 register. +// +//***************************************************************************** +#define SYSCTL_SRCR1_COMP2 0x04000000 // Analog Comp 2 Reset Control +#define SYSCTL_SRCR1_COMP1 0x02000000 // Analog Comp 1 Reset Control +#define SYSCTL_SRCR1_COMP0 0x01000000 // Analog Comp 0 Reset Control +#define SYSCTL_SRCR1_TIMER3 0x00080000 // Timer 3 Reset Control +#define SYSCTL_SRCR1_TIMER2 0x00040000 // Timer 2 Reset Control +#define SYSCTL_SRCR1_TIMER1 0x00020000 // Timer 1 Reset Control +#define SYSCTL_SRCR1_TIMER0 0x00010000 // Timer 0 Reset Control +#define SYSCTL_SRCR1_I2C1 0x00004000 // I2C1 Reset Control +#define SYSCTL_SRCR1_I2C0 0x00001000 // I2C0 Reset Control +#define SYSCTL_SRCR1_QEI1 0x00000200 // QEI1 Reset Control +#define SYSCTL_SRCR1_QEI0 0x00000100 // QEI0 Reset Control +#define SYSCTL_SRCR1_SSI1 0x00000020 // SSI1 Reset Control +#define SYSCTL_SRCR1_SSI0 0x00000010 // SSI0 Reset Control +#define SYSCTL_SRCR1_UART2 0x00000004 // UART2 Reset Control +#define SYSCTL_SRCR1_UART1 0x00000002 // UART1 Reset Control +#define SYSCTL_SRCR1_UART0 0x00000001 // UART0 Reset Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCR2 register. +// +//***************************************************************************** +#define SYSCTL_SRCR2_USB0 0x00010000 // USB0 Reset Control +#define SYSCTL_SRCR2_UDMA 0x00002000 // Micro-DMA Reset Control +#define SYSCTL_SRCR2_GPIOJ 0x00000100 // Port J Reset Control +#define SYSCTL_SRCR2_GPIOH 0x00000080 // Port H Reset Control +#define SYSCTL_SRCR2_GPIOG 0x00000040 // Port G Reset Control +#define SYSCTL_SRCR2_GPIOF 0x00000020 // Port F Reset Control +#define SYSCTL_SRCR2_GPIOE 0x00000010 // Port E Reset Control +#define SYSCTL_SRCR2_GPIOD 0x00000008 // Port D Reset Control +#define SYSCTL_SRCR2_GPIOC 0x00000004 // Port C Reset Control +#define SYSCTL_SRCR2_GPIOB 0x00000002 // Port B Reset Control +#define SYSCTL_SRCR2_GPIOA 0x00000001 // Port A Reset Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RIS register. +// +//***************************************************************************** +#define SYSCTL_RIS_BOR0RIS 0x00000800 // VDD under BOR0 Raw Interrupt + // Status +#define SYSCTL_RIS_VDDARIS 0x00000400 // VDDA Power OK Event Raw + // Interrupt Status +#define SYSCTL_RIS_MOSCPUPRIS 0x00000100 // MOSC Power Up Raw Interrupt + // Status +#define SYSCTL_RIS_USBPLLLRIS 0x00000080 // USB PLL Lock Raw Interrupt + // Status +#define SYSCTL_RIS_PLLLRIS 0x00000040 // PLL Lock Raw Interrupt Status +#define SYSCTL_RIS_MOFRIS 0x00000008 // Main Oscillator Failure Raw + // Interrupt Status +#define SYSCTL_RIS_BOR1RIS 0x00000002 // VDD under BOR1 Raw Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_IMC register. +// +//***************************************************************************** +#define SYSCTL_IMC_BOR0IM 0x00000800 // VDD under BOR0 Interrupt Mask +#define SYSCTL_IMC_VDDAIM 0x00000400 // VDDA Power OK Interrupt Mask +#define SYSCTL_IMC_MOSCPUPIM 0x00000100 // MOSC Power Up Interrupt Mask +#define SYSCTL_IMC_USBPLLLIM 0x00000080 // USB PLL Lock Interrupt Mask +#define SYSCTL_IMC_PLLLIM 0x00000040 // PLL Lock Interrupt Mask +#define SYSCTL_IMC_MOFIM 0x00000008 // Main Oscillator Failure + // Interrupt Mask +#define SYSCTL_IMC_BOR1IM 0x00000002 // VDD under BOR1 Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_MISC register. +// +//***************************************************************************** +#define SYSCTL_MISC_BOR0MIS 0x00000800 // VDD under BOR0 Masked Interrupt + // Status +#define SYSCTL_MISC_VDDAMIS 0x00000400 // VDDA Power OK Masked Interrupt + // Status +#define SYSCTL_MISC_MOSCPUPMIS 0x00000100 // MOSC Power Up Masked Interrupt + // Status +#define SYSCTL_MISC_USBPLLLMIS 0x00000080 // USB PLL Lock Masked Interrupt + // Status +#define SYSCTL_MISC_PLLLMIS 0x00000040 // PLL Lock Masked Interrupt Status +#define SYSCTL_MISC_MOFMIS 0x00000008 // Main Oscillator Failure Masked + // Interrupt Status +#define SYSCTL_MISC_BOR1MIS 0x00000002 // VDD under BOR1 Masked Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RESC register. +// +//***************************************************************************** +#define SYSCTL_RESC_MOSCFAIL 0x00010000 // MOSC Failure Reset +#define SYSCTL_RESC_WDT1 0x00000020 // Watchdog Timer 1 Reset +#define SYSCTL_RESC_SW 0x00000010 // Software Reset +#define SYSCTL_RESC_WDT0 0x00000008 // Watchdog Timer 0 Reset +#define SYSCTL_RESC_BOR 0x00000004 // Brown-Out Reset +#define SYSCTL_RESC_POR 0x00000002 // Power-On Reset +#define SYSCTL_RESC_EXT 0x00000001 // External Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCC register. +// +//***************************************************************************** +#define SYSCTL_RCC_ACG 0x08000000 // Auto Clock Gating +#define SYSCTL_RCC_SYSDIV_M 0x07800000 // System Clock Divisor +#define SYSCTL_RCC_USESYSDIV 0x00400000 // Enable System Clock Divider +#define SYSCTL_RCC_USEPWMDIV 0x00100000 // Enable PWM Clock Divisor +#define SYSCTL_RCC_PWMDIV_M 0x000E0000 // PWM Unit Clock Divisor +#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2 +#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4 +#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8 +#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16 +#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32 +#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64 +#define SYSCTL_RCC_PWRDN 0x00002000 // PLL Power Down +#define SYSCTL_RCC_BYPASS 0x00000800 // PLL Bypass +#define SYSCTL_RCC_XTAL_M 0x000007C0 // Crystal Value +#define SYSCTL_RCC_XTAL_4MHZ 0x00000180 // 4 MHz +#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // 4.096 MHz +#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // 4.9152 MHz +#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // 5 MHz +#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // 5.12 MHz +#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // 6 MHz +#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // 6.144 MHz +#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // 7.3728 MHz +#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // 8 MHz +#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // 8.192 MHz +#define SYSCTL_RCC_XTAL_10MHZ 0x00000400 // 10 MHz +#define SYSCTL_RCC_XTAL_12MHZ 0x00000440 // 12 MHz +#define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480 // 12.288 MHz +#define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0 // 13.56 MHz +#define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500 // 14.31818 MHz +#define SYSCTL_RCC_XTAL_16MHZ 0x00000540 // 16 MHz +#define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580 // 16.384 MHz +#define SYSCTL_RCC_XTAL_18MHZ 0x000005C0 // 18.0 MHz (USB) +#define SYSCTL_RCC_XTAL_20MHZ 0x00000600 // 20.0 MHz (USB) +#define SYSCTL_RCC_XTAL_24MHZ 0x00000640 // 24.0 MHz (USB) +#define SYSCTL_RCC_XTAL_25MHZ 0x00000680 // 25.0 MHz (USB) +#define SYSCTL_RCC_OSCSRC_M 0x00000030 // Oscillator Source +#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // MOSC +#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // IOSC +#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // IOSC/4 +#define SYSCTL_RCC_OSCSRC_30 0x00000030 // LFIOSC +#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main Oscillator Disable +#define SYSCTL_RCC_SYSDIV_S 23 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_GPIOHBCTL +// register. +// +//***************************************************************************** +#define SYSCTL_GPIOHBCTL_PORTJ 0x00000100 // Port J Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTH 0x00000080 // Port H Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTG 0x00000040 // Port G Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTF 0x00000020 // Port F Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTE 0x00000010 // Port E Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTD 0x00000008 // Port D Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTC 0x00000004 // Port C Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTB 0x00000002 // Port B Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTA 0x00000001 // Port A Advanced High-Performance + // Bus + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCC2 register. +// +//***************************************************************************** +#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2 +#define SYSCTL_RCC2_DIV400 0x40000000 // Divide PLL as 400 MHz vs. 200 + // MHz +#define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 // System Clock Divisor 2 +#define SYSCTL_RCC2_SYSDIV2LSB 0x00400000 // Additional LSB for SYSDIV2 +#define SYSCTL_RCC2_USBPWRDN 0x00004000 // Power-Down USB PLL +#define SYSCTL_RCC2_PWRDN2 0x00002000 // Power-Down PLL 2 +#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL Bypass 2 +#define SYSCTL_RCC2_OSCSRC2_M 0x00000070 // Oscillator Source 2 +#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // MOSC +#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // PIOSC +#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // PIOSC/4 +#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // LFIOSC +#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // 32.768 kHz +#define SYSCTL_RCC2_SYSDIV2_S 23 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_MOSCCTL register. +// +//***************************************************************************** +#define SYSCTL_MOSCCTL_NOXTAL 0x00000004 // No Crystal Connected +#define SYSCTL_MOSCCTL_MOSCIM 0x00000002 // MOSC Failure Action +#define SYSCTL_MOSCCTL_CVAL 0x00000001 // Clock Validation for MOSC + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGC0 register. +// +//***************************************************************************** +#define SYSCTL_RCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control +#define SYSCTL_RCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control +#define SYSCTL_RCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control +#define SYSCTL_RCGC0_PWM0 0x00100000 // PWM Clock Gating Control +#define SYSCTL_RCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control +#define SYSCTL_RCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control +#define SYSCTL_RCGC0_ADC1SPD_M 0x00000C00 // ADC1 Sample Speed +#define SYSCTL_RCGC0_ADC1SPD_125K \ + 0x00000000 // 125K samples/second +#define SYSCTL_RCGC0_ADC1SPD_250K \ + 0x00000400 // 250K samples/second +#define SYSCTL_RCGC0_ADC1SPD_500K \ + 0x00000800 // 500K samples/second +#define SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00 // 1M samples/second +#define SYSCTL_RCGC0_ADC0SPD_M 0x00000300 // ADC0 Sample Speed +#define SYSCTL_RCGC0_ADC0SPD_125K \ + 0x00000000 // 125K samples/second +#define SYSCTL_RCGC0_ADC0SPD_250K \ + 0x00000100 // 250K samples/second +#define SYSCTL_RCGC0_ADC0SPD_500K \ + 0x00000200 // 500K samples/second +#define SYSCTL_RCGC0_ADC0SPD_1M 0x00000300 // 1M samples/second +#define SYSCTL_RCGC0_HIB 0x00000040 // HIB Clock Gating Control +#define SYSCTL_RCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGC1 register. +// +//***************************************************************************** +#define SYSCTL_RCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating +#define SYSCTL_RCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating +#define SYSCTL_RCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating +#define SYSCTL_RCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control +#define SYSCTL_RCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control +#define SYSCTL_RCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control +#define SYSCTL_RCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control +#define SYSCTL_RCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control +#define SYSCTL_RCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control +#define SYSCTL_RCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control +#define SYSCTL_RCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control +#define SYSCTL_RCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control +#define SYSCTL_RCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control +#define SYSCTL_RCGC1_UART2 0x00000004 // UART2 Clock Gating Control +#define SYSCTL_RCGC1_UART1 0x00000002 // UART1 Clock Gating Control +#define SYSCTL_RCGC1_UART0 0x00000001 // UART0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGC2 register. +// +//***************************************************************************** +#define SYSCTL_RCGC2_USB0 0x00010000 // USB0 Clock Gating Control +#define SYSCTL_RCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control +#define SYSCTL_RCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control +#define SYSCTL_RCGC2_GPIOH 0x00000080 // Port H Clock Gating Control +#define SYSCTL_RCGC2_GPIOG 0x00000040 // Port G Clock Gating Control +#define SYSCTL_RCGC2_GPIOF 0x00000020 // Port F Clock Gating Control +#define SYSCTL_RCGC2_GPIOE 0x00000010 // Port E Clock Gating Control +#define SYSCTL_RCGC2_GPIOD 0x00000008 // Port D Clock Gating Control +#define SYSCTL_RCGC2_GPIOC 0x00000004 // Port C Clock Gating Control +#define SYSCTL_RCGC2_GPIOB 0x00000002 // Port B Clock Gating Control +#define SYSCTL_RCGC2_GPIOA 0x00000001 // Port A Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGC0 register. +// +//***************************************************************************** +#define SYSCTL_SCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control +#define SYSCTL_SCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control +#define SYSCTL_SCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control +#define SYSCTL_SCGC0_PWM0 0x00100000 // PWM Clock Gating Control +#define SYSCTL_SCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control +#define SYSCTL_SCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control +#define SYSCTL_SCGC0_HIB 0x00000040 // HIB Clock Gating Control +#define SYSCTL_SCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGC1 register. +// +//***************************************************************************** +#define SYSCTL_SCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating +#define SYSCTL_SCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating +#define SYSCTL_SCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating +#define SYSCTL_SCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control +#define SYSCTL_SCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control +#define SYSCTL_SCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control +#define SYSCTL_SCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control +#define SYSCTL_SCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control +#define SYSCTL_SCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control +#define SYSCTL_SCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control +#define SYSCTL_SCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control +#define SYSCTL_SCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control +#define SYSCTL_SCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control +#define SYSCTL_SCGC1_UART2 0x00000004 // UART2 Clock Gating Control +#define SYSCTL_SCGC1_UART1 0x00000002 // UART1 Clock Gating Control +#define SYSCTL_SCGC1_UART0 0x00000001 // UART0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGC2 register. +// +//***************************************************************************** +#define SYSCTL_SCGC2_USB0 0x00010000 // USB0 Clock Gating Control +#define SYSCTL_SCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control +#define SYSCTL_SCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control +#define SYSCTL_SCGC2_GPIOH 0x00000080 // Port H Clock Gating Control +#define SYSCTL_SCGC2_GPIOG 0x00000040 // Port G Clock Gating Control +#define SYSCTL_SCGC2_GPIOF 0x00000020 // Port F Clock Gating Control +#define SYSCTL_SCGC2_GPIOE 0x00000010 // Port E Clock Gating Control +#define SYSCTL_SCGC2_GPIOD 0x00000008 // Port D Clock Gating Control +#define SYSCTL_SCGC2_GPIOC 0x00000004 // Port C Clock Gating Control +#define SYSCTL_SCGC2_GPIOB 0x00000002 // Port B Clock Gating Control +#define SYSCTL_SCGC2_GPIOA 0x00000001 // Port A Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGC0 register. +// +//***************************************************************************** +#define SYSCTL_DCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control +#define SYSCTL_DCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control +#define SYSCTL_DCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control +#define SYSCTL_DCGC0_PWM0 0x00100000 // PWM Clock Gating Control +#define SYSCTL_DCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control +#define SYSCTL_DCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control +#define SYSCTL_DCGC0_HIB 0x00000040 // HIB Clock Gating Control +#define SYSCTL_DCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGC1 register. +// +//***************************************************************************** +#define SYSCTL_DCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating +#define SYSCTL_DCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating +#define SYSCTL_DCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating +#define SYSCTL_DCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control +#define SYSCTL_DCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control +#define SYSCTL_DCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control +#define SYSCTL_DCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control +#define SYSCTL_DCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control +#define SYSCTL_DCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control +#define SYSCTL_DCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control +#define SYSCTL_DCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control +#define SYSCTL_DCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control +#define SYSCTL_DCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control +#define SYSCTL_DCGC1_UART2 0x00000004 // UART2 Clock Gating Control +#define SYSCTL_DCGC1_UART1 0x00000002 // UART1 Clock Gating Control +#define SYSCTL_DCGC1_UART0 0x00000001 // UART0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGC2 register. +// +//***************************************************************************** +#define SYSCTL_DCGC2_USB0 0x00010000 // USB0 Clock Gating Control +#define SYSCTL_DCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control +#define SYSCTL_DCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control +#define SYSCTL_DCGC2_GPIOH 0x00000080 // Port H Clock Gating Control +#define SYSCTL_DCGC2_GPIOG 0x00000040 // Port G Clock Gating Control +#define SYSCTL_DCGC2_GPIOF 0x00000020 // Port F Clock Gating Control +#define SYSCTL_DCGC2_GPIOE 0x00000010 // Port E Clock Gating Control +#define SYSCTL_DCGC2_GPIOD 0x00000008 // Port D Clock Gating Control +#define SYSCTL_DCGC2_GPIOC 0x00000004 // Port C Clock Gating Control +#define SYSCTL_DCGC2_GPIOB 0x00000002 // Port B Clock Gating Control +#define SYSCTL_DCGC2_GPIOA 0x00000001 // Port A Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG +// register. +// +//***************************************************************************** +#define SYSCTL_DSLPCLKCFG_D_M 0x1F800000 // Divider Field Override +#define SYSCTL_DSLPCLKCFG_O_M 0x00000070 // Clock Source +#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // MOSC +#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // PIOSC +#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // LFIOSC +#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // 32.768 kHz +#define SYSCTL_DSLPCLKCFG_PIOSCPD \ + 0x00000002 // PIOSC Power Down Request +#define SYSCTL_DSLPCLKCFG_D_S 23 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SYSPROP register. +// +//***************************************************************************** +#define SYSCTL_SYSPROP_FPU 0x00000001 // FPU Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PIOSCCAL +// register. +// +//***************************************************************************** +#define SYSCTL_PIOSCCAL_UTEN 0x80000000 // Use User Trim Value +#define SYSCTL_PIOSCCAL_CAL 0x00000200 // Start Calibration +#define SYSCTL_PIOSCCAL_UPDATE 0x00000100 // Update Trim +#define SYSCTL_PIOSCCAL_UT_M 0x0000007F // User Trim Value +#define SYSCTL_PIOSCCAL_UT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PIOSCSTAT +// register. +// +//***************************************************************************** +#define SYSCTL_PIOSCSTAT_DT_M 0x007F0000 // Default Trim Value +#define SYSCTL_PIOSCSTAT_CR_M 0x00000300 // Calibration Result +#define SYSCTL_PIOSCSTAT_CRNONE 0x00000000 // Calibration has not been + // attempted +#define SYSCTL_PIOSCSTAT_CRPASS 0x00000100 // The last calibration operation + // completed to meet 1% accuracy +#define SYSCTL_PIOSCSTAT_CRFAIL 0x00000200 // The last calibration operation + // failed to meet 1% accuracy +#define SYSCTL_PIOSCSTAT_CT_M 0x0000007F // Calibration Trim Value +#define SYSCTL_PIOSCSTAT_DT_S 16 +#define SYSCTL_PIOSCSTAT_CT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PLLFREQ0 +// register. +// +//***************************************************************************** +#define SYSCTL_PLLFREQ0_MFRAC_M 0x000FFC00 // PLL M Fractional Value +#define SYSCTL_PLLFREQ0_MINT_M 0x000003FF // PLL M Integer Value +#define SYSCTL_PLLFREQ0_MFRAC_S 10 +#define SYSCTL_PLLFREQ0_MINT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PLLFREQ1 +// register. +// +//***************************************************************************** +#define SYSCTL_PLLFREQ1_Q_M 0x00001F00 // PLL Q Value +#define SYSCTL_PLLFREQ1_N_M 0x0000001F // PLL N Value +#define SYSCTL_PLLFREQ1_Q_S 8 +#define SYSCTL_PLLFREQ1_N_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PLLSTAT register. +// +//***************************************************************************** +#define SYSCTL_PLLSTAT_LOCK 0x00000001 // PLL Lock + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SLPPWRCFG +// register. +// +//***************************************************************************** +#define SYSCTL_SLPPWRCFG_FLASHPM_M \ + 0x00000030 // Flash Power Modes +#define SYSCTL_SLPPWRCFG_FLASHPM_NRM \ + 0x00000000 // Active Mode +#define SYSCTL_SLPPWRCFG_FLASHPM_SLP \ + 0x00000020 // Low Power Mode +#define SYSCTL_SLPPWRCFG_SRAMPM_M \ + 0x00000003 // SRAM Power Modes +#define SYSCTL_SLPPWRCFG_SRAMPM_NRM \ + 0x00000000 // Active Mode +#define SYSCTL_SLPPWRCFG_SRAMPM_SBY \ + 0x00000001 // Standby Mode +#define SYSCTL_SLPPWRCFG_SRAMPM_LP \ + 0x00000003 // Low Power Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DSLPPWRCFG +// register. +// +//***************************************************************************** +#define SYSCTL_DSLPPWRCFG_FLASHPM_M \ + 0x00000030 // Flash Power Modes +#define SYSCTL_DSLPPWRCFG_FLASHPM_NRM \ + 0x00000000 // Active Mode +#define SYSCTL_DSLPPWRCFG_FLASHPM_SLP \ + 0x00000020 // Low Power Mode +#define SYSCTL_DSLPPWRCFG_SRAMPM_M \ + 0x00000003 // SRAM Power Modes +#define SYSCTL_DSLPPWRCFG_SRAMPM_NRM \ + 0x00000000 // Active Mode +#define SYSCTL_DSLPPWRCFG_SRAMPM_SBY \ + 0x00000001 // Standby Mode +#define SYSCTL_DSLPPWRCFG_SRAMPM_LP \ + 0x00000003 // Low Power Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC9 register. +// +//***************************************************************************** +#define SYSCTL_DC9_ADC1DC7 0x00800000 // ADC1 DC7 Present +#define SYSCTL_DC9_ADC1DC6 0x00400000 // ADC1 DC6 Present +#define SYSCTL_DC9_ADC1DC5 0x00200000 // ADC1 DC5 Present +#define SYSCTL_DC9_ADC1DC4 0x00100000 // ADC1 DC4 Present +#define SYSCTL_DC9_ADC1DC3 0x00080000 // ADC1 DC3 Present +#define SYSCTL_DC9_ADC1DC2 0x00040000 // ADC1 DC2 Present +#define SYSCTL_DC9_ADC1DC1 0x00020000 // ADC1 DC1 Present +#define SYSCTL_DC9_ADC1DC0 0x00010000 // ADC1 DC0 Present +#define SYSCTL_DC9_ADC0DC7 0x00000080 // ADC0 DC7 Present +#define SYSCTL_DC9_ADC0DC6 0x00000040 // ADC0 DC6 Present +#define SYSCTL_DC9_ADC0DC5 0x00000020 // ADC0 DC5 Present +#define SYSCTL_DC9_ADC0DC4 0x00000010 // ADC0 DC4 Present +#define SYSCTL_DC9_ADC0DC3 0x00000008 // ADC0 DC3 Present +#define SYSCTL_DC9_ADC0DC2 0x00000004 // ADC0 DC2 Present +#define SYSCTL_DC9_ADC0DC1 0x00000002 // ADC0 DC1 Present +#define SYSCTL_DC9_ADC0DC0 0x00000001 // ADC0 DC0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_NVMSTAT register. +// +//***************************************************************************** +#define SYSCTL_NVMSTAT_FWB 0x00000001 // 32 Word Flash Write Buffer + // Available + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_LDOSPCTL +// register. +// +//***************************************************************************** +#define SYSCTL_LDOSPCTL_VADJEN 0x80000000 // Voltage Adjust Enable +#define SYSCTL_LDOSPCTL_VLDO_M 0x000000FF // LDO Output Voltage +#define SYSCTL_LDOSPCTL_VLDO_0_90V \ + 0x00000012 // 0.90 V +#define SYSCTL_LDOSPCTL_VLDO_0_95V \ + 0x00000013 // 0.95 V +#define SYSCTL_LDOSPCTL_VLDO_1_00V \ + 0x00000014 // 1.00 V +#define SYSCTL_LDOSPCTL_VLDO_1_05V \ + 0x00000015 // 1.05 V +#define SYSCTL_LDOSPCTL_VLDO_1_10V \ + 0x00000016 // 1.10 V +#define SYSCTL_LDOSPCTL_VLDO_1_15V \ + 0x00000017 // 1.15 V +#define SYSCTL_LDOSPCTL_VLDO_1_20V \ + 0x00000018 // 1.20 V + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_LDODPCTL +// register. +// +//***************************************************************************** +#define SYSCTL_LDODPCTL_VADJEN 0x80000000 // Voltage Adjust Enable +#define SYSCTL_LDODPCTL_VLDO_M 0x000000FF // LDO Output Voltage +#define SYSCTL_LDODPCTL_VLDO_0_90V \ + 0x00000012 // 0.90 V +#define SYSCTL_LDODPCTL_VLDO_0_95V \ + 0x00000013 // 0.95 V +#define SYSCTL_LDODPCTL_VLDO_1_00V \ + 0x00000014 // 1.00 V +#define SYSCTL_LDODPCTL_VLDO_1_05V \ + 0x00000015 // 1.05 V +#define SYSCTL_LDODPCTL_VLDO_1_10V \ + 0x00000016 // 1.10 V +#define SYSCTL_LDODPCTL_VLDO_1_15V \ + 0x00000017 // 1.15 V +#define SYSCTL_LDODPCTL_VLDO_1_20V \ + 0x00000018 // 1.20 V + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPWD register. +// +//***************************************************************************** +#define SYSCTL_PPWD_P1 0x00000002 // Watchdog Timer 1 Present +#define SYSCTL_PPWD_P0 0x00000001 // Watchdog Timer 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPTIMER register. +// +//***************************************************************************** +#define SYSCTL_PPTIMER_P5 0x00000020 // 16/32-Bit General-Purpose Timer + // 5 Present +#define SYSCTL_PPTIMER_P4 0x00000010 // 16/32-Bit General-Purpose Timer + // 4 Present +#define SYSCTL_PPTIMER_P3 0x00000008 // 16/32-Bit General-Purpose Timer + // 3 Present +#define SYSCTL_PPTIMER_P2 0x00000004 // 16/32-Bit General-Purpose Timer + // 2 Present +#define SYSCTL_PPTIMER_P1 0x00000002 // 16/32-Bit General-Purpose Timer + // 1 Present +#define SYSCTL_PPTIMER_P0 0x00000001 // 16/32-Bit General-Purpose Timer + // 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPGPIO register. +// +//***************************************************************************** +#define SYSCTL_PPGPIO_P14 0x00004000 // GPIO Port Q Present +#define SYSCTL_PPGPIO_P13 0x00002000 // GPIO Port P Present +#define SYSCTL_PPGPIO_P12 0x00001000 // GPIO Port N Present +#define SYSCTL_PPGPIO_P11 0x00000800 // GPIO Port M Present +#define SYSCTL_PPGPIO_P10 0x00000400 // GPIO Port L Present +#define SYSCTL_PPGPIO_P9 0x00000200 // GPIO Port K Present +#define SYSCTL_PPGPIO_P8 0x00000100 // GPIO Port J Present +#define SYSCTL_PPGPIO_P7 0x00000080 // GPIO Port H Present +#define SYSCTL_PPGPIO_P6 0x00000040 // GPIO Port G Present +#define SYSCTL_PPGPIO_P5 0x00000020 // GPIO Port F Present +#define SYSCTL_PPGPIO_P4 0x00000010 // GPIO Port E Present +#define SYSCTL_PPGPIO_P3 0x00000008 // GPIO Port D Present +#define SYSCTL_PPGPIO_P2 0x00000004 // GPIO Port C Present +#define SYSCTL_PPGPIO_P1 0x00000002 // GPIO Port B Present +#define SYSCTL_PPGPIO_P0 0x00000001 // GPIO Port A Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPDMA register. +// +//***************************************************************************** +#define SYSCTL_PPDMA_P0 0x00000001 // uDMA Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPHIB register. +// +//***************************************************************************** +#define SYSCTL_PPHIB_P0 0x00000001 // Hibernation Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPUART register. +// +//***************************************************************************** +#define SYSCTL_PPUART_P7 0x00000080 // UART Module 7 Present +#define SYSCTL_PPUART_P6 0x00000040 // UART Module 6 Present +#define SYSCTL_PPUART_P5 0x00000020 // UART Module 5 Present +#define SYSCTL_PPUART_P4 0x00000010 // UART Module 4 Present +#define SYSCTL_PPUART_P3 0x00000008 // UART Module 3 Present +#define SYSCTL_PPUART_P2 0x00000004 // UART Module 2 Present +#define SYSCTL_PPUART_P1 0x00000002 // UART Module 1 Present +#define SYSCTL_PPUART_P0 0x00000001 // UART Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPSSI register. +// +//***************************************************************************** +#define SYSCTL_PPSSI_P3 0x00000008 // SSI Module 3 Present +#define SYSCTL_PPSSI_P2 0x00000004 // SSI Module 2 Present +#define SYSCTL_PPSSI_P1 0x00000002 // SSI Module 1 Present +#define SYSCTL_PPSSI_P0 0x00000001 // SSI Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPI2C register. +// +//***************************************************************************** +#define SYSCTL_PPI2C_P5 0x00000020 // I2C Module 5 Present +#define SYSCTL_PPI2C_P4 0x00000010 // I2C Module 4 Present +#define SYSCTL_PPI2C_P3 0x00000008 // I2C Module 3 Present +#define SYSCTL_PPI2C_P2 0x00000004 // I2C Module 2 Present +#define SYSCTL_PPI2C_P1 0x00000002 // I2C Module 1 Present +#define SYSCTL_PPI2C_P0 0x00000001 // I2C Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPUSB register. +// +//***************************************************************************** +#define SYSCTL_PPUSB_P0 0x00000001 // USB Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPCAN register. +// +//***************************************************************************** +#define SYSCTL_PPCAN_P1 0x00000002 // CAN Module 1 Present +#define SYSCTL_PPCAN_P0 0x00000001 // CAN Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPADC register. +// +//***************************************************************************** +#define SYSCTL_PPADC_P1 0x00000002 // ADC Module 1 Present +#define SYSCTL_PPADC_P0 0x00000001 // ADC Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPACMP register. +// +//***************************************************************************** +#define SYSCTL_PPACMP_P0 0x00000001 // Analog Comparator Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPPWM register. +// +//***************************************************************************** +#define SYSCTL_PPPWM_P1 0x00000002 // PWM Module 1 Present +#define SYSCTL_PPPWM_P0 0x00000001 // PWM Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPQEI register. +// +//***************************************************************************** +#define SYSCTL_PPQEI_P1 0x00000002 // QEI Module 1 Present +#define SYSCTL_PPQEI_P0 0x00000001 // QEI Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPEEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_PPEEPROM_P0 0x00000001 // EEPROM Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_PPWTIMER_P5 0x00000020 // 32/64-Bit Wide General-Purpose + // Timer 5 Present +#define SYSCTL_PPWTIMER_P4 0x00000010 // 32/64-Bit Wide General-Purpose + // Timer 4 Present +#define SYSCTL_PPWTIMER_P3 0x00000008 // 32/64-Bit Wide General-Purpose + // Timer 3 Present +#define SYSCTL_PPWTIMER_P2 0x00000004 // 32/64-Bit Wide General-Purpose + // Timer 2 Present +#define SYSCTL_PPWTIMER_P1 0x00000002 // 32/64-Bit Wide General-Purpose + // Timer 1 Present +#define SYSCTL_PPWTIMER_P0 0x00000001 // 32/64-Bit Wide General-Purpose + // Timer 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRWD register. +// +//***************************************************************************** +#define SYSCTL_SRWD_R1 0x00000002 // Watchdog Timer 1 Software Reset +#define SYSCTL_SRWD_R0 0x00000001 // Watchdog Timer 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRTIMER register. +// +//***************************************************************************** +#define SYSCTL_SRTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer + // 5 Software Reset +#define SYSCTL_SRTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer + // 4 Software Reset +#define SYSCTL_SRTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer + // 3 Software Reset +#define SYSCTL_SRTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer + // 2 Software Reset +#define SYSCTL_SRTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer + // 1 Software Reset +#define SYSCTL_SRTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer + // 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRGPIO register. +// +//***************************************************************************** +#define SYSCTL_SRGPIO_R9 0x00000200 // GPIO Port K Software Reset +#define SYSCTL_SRGPIO_R8 0x00000100 // GPIO Port J Software Reset +#define SYSCTL_SRGPIO_R7 0x00000080 // GPIO Port H Software Reset +#define SYSCTL_SRGPIO_R6 0x00000040 // GPIO Port G Software Reset +#define SYSCTL_SRGPIO_R5 0x00000020 // GPIO Port F Software Reset +#define SYSCTL_SRGPIO_R4 0x00000010 // GPIO Port E Software Reset +#define SYSCTL_SRGPIO_R3 0x00000008 // GPIO Port D Software Reset +#define SYSCTL_SRGPIO_R2 0x00000004 // GPIO Port C Software Reset +#define SYSCTL_SRGPIO_R1 0x00000002 // GPIO Port B Software Reset +#define SYSCTL_SRGPIO_R0 0x00000001 // GPIO Port A Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRDMA register. +// +//***************************************************************************** +#define SYSCTL_SRDMA_R0 0x00000001 // uDMA Module Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRHIB register. +// +//***************************************************************************** +#define SYSCTL_SRHIB_R0 0x00000001 // Hibernation Module Software + // Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRUART register. +// +//***************************************************************************** +#define SYSCTL_SRUART_R7 0x00000080 // UART Module 7 Software Reset +#define SYSCTL_SRUART_R6 0x00000040 // UART Module 6 Software Reset +#define SYSCTL_SRUART_R5 0x00000020 // UART Module 5 Software Reset +#define SYSCTL_SRUART_R4 0x00000010 // UART Module 4 Software Reset +#define SYSCTL_SRUART_R3 0x00000008 // UART Module 3 Software Reset +#define SYSCTL_SRUART_R2 0x00000004 // UART Module 2 Software Reset +#define SYSCTL_SRUART_R1 0x00000002 // UART Module 1 Software Reset +#define SYSCTL_SRUART_R0 0x00000001 // UART Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRSSI register. +// +//***************************************************************************** +#define SYSCTL_SRSSI_R3 0x00000008 // SSI Module 3 Software Reset +#define SYSCTL_SRSSI_R2 0x00000004 // SSI Module 2 Software Reset +#define SYSCTL_SRSSI_R1 0x00000002 // SSI Module 1 Software Reset +#define SYSCTL_SRSSI_R0 0x00000001 // SSI Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRI2C register. +// +//***************************************************************************** +#define SYSCTL_SRI2C_R5 0x00000020 // I2C Module 5 Software Reset +#define SYSCTL_SRI2C_R4 0x00000010 // I2C Module 4 Software Reset +#define SYSCTL_SRI2C_R3 0x00000008 // I2C Module 3 Software Reset +#define SYSCTL_SRI2C_R2 0x00000004 // I2C Module 2 Software Reset +#define SYSCTL_SRI2C_R1 0x00000002 // I2C Module 1 Software Reset +#define SYSCTL_SRI2C_R0 0x00000001 // I2C Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRUSB register. +// +//***************************************************************************** +#define SYSCTL_SRUSB_R0 0x00000001 // USB Module Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCAN register. +// +//***************************************************************************** +#define SYSCTL_SRCAN_R1 0x00000002 // CAN Module 1 Software Reset +#define SYSCTL_SRCAN_R0 0x00000001 // CAN Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRADC register. +// +//***************************************************************************** +#define SYSCTL_SRADC_R1 0x00000002 // ADC Module 1 Software Reset +#define SYSCTL_SRADC_R0 0x00000001 // ADC Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRACMP register. +// +//***************************************************************************** +#define SYSCTL_SRACMP_R0 0x00000001 // Analog Comparator Module 0 + // Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRPWM register. +// +//***************************************************************************** +#define SYSCTL_SRPWM_R1 0x00000002 // PWM Module 1 Software Reset +#define SYSCTL_SRPWM_R0 0x00000001 // PWM Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRQEI register. +// +//***************************************************************************** +#define SYSCTL_SRQEI_R1 0x00000002 // QEI Module 1 Software Reset +#define SYSCTL_SRQEI_R0 0x00000001 // QEI Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SREEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_SREEPROM_R0 0x00000001 // EEPROM Module Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_SRWTIMER_R5 0x00000020 // 32/64-Bit Wide General-Purpose + // Timer 5 Software Reset +#define SYSCTL_SRWTIMER_R4 0x00000010 // 32/64-Bit Wide General-Purpose + // Timer 4 Software Reset +#define SYSCTL_SRWTIMER_R3 0x00000008 // 32/64-Bit Wide General-Purpose + // Timer 3 Software Reset +#define SYSCTL_SRWTIMER_R2 0x00000004 // 32/64-Bit Wide General-Purpose + // Timer 2 Software Reset +#define SYSCTL_SRWTIMER_R1 0x00000002 // 32/64-Bit Wide General-Purpose + // Timer 1 Software Reset +#define SYSCTL_SRWTIMER_R0 0x00000001 // 32/64-Bit Wide General-Purpose + // Timer 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCWD register. +// +//***************************************************************************** +#define SYSCTL_RCGCWD_R1 0x00000002 // Watchdog Timer 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCWD_R0 0x00000001 // Watchdog Timer 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer + // 5 Run Mode Clock Gating Control +#define SYSCTL_RCGCTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer + // 4 Run Mode Clock Gating Control +#define SYSCTL_RCGCTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer + // 3 Run Mode Clock Gating Control +#define SYSCTL_RCGCTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer + // 2 Run Mode Clock Gating Control +#define SYSCTL_RCGCTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer + // 1 Run Mode Clock Gating Control +#define SYSCTL_RCGCTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer + // 0 Run Mode Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCGPIO +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCGPIO_R9 0x00000200 // GPIO Port K Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R8 0x00000100 // GPIO Port J Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R7 0x00000080 // GPIO Port H Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R6 0x00000040 // GPIO Port G Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R5 0x00000020 // GPIO Port F Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R4 0x00000010 // GPIO Port E Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R3 0x00000008 // GPIO Port D Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R2 0x00000004 // GPIO Port C Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R1 0x00000002 // GPIO Port B Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R0 0x00000001 // GPIO Port A Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCDMA register. +// +//***************************************************************************** +#define SYSCTL_RCGCDMA_R0 0x00000001 // uDMA Module Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCHIB register. +// +//***************************************************************************** +#define SYSCTL_RCGCHIB_R0 0x00000001 // Hibernation Module Run Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCUART +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCUART_R7 0x00000080 // UART Module 7 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R6 0x00000040 // UART Module 6 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R5 0x00000020 // UART Module 5 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R4 0x00000010 // UART Module 4 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R3 0x00000008 // UART Module 3 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R2 0x00000004 // UART Module 2 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R1 0x00000002 // UART Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R0 0x00000001 // UART Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCSSI register. +// +//***************************************************************************** +#define SYSCTL_RCGCSSI_R3 0x00000008 // SSI Module 3 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCSSI_R2 0x00000004 // SSI Module 2 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCSSI_R1 0x00000002 // SSI Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCSSI_R0 0x00000001 // SSI Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCI2C register. +// +//***************************************************************************** +#define SYSCTL_RCGCI2C_R5 0x00000020 // I2C Module 5 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R4 0x00000010 // I2C Module 4 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R3 0x00000008 // I2C Module 3 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R2 0x00000004 // I2C Module 2 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R1 0x00000002 // I2C Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R0 0x00000001 // I2C Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCUSB register. +// +//***************************************************************************** +#define SYSCTL_RCGCUSB_R0 0x00000001 // USB Module Run Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCCAN register. +// +//***************************************************************************** +#define SYSCTL_RCGCCAN_R1 0x00000002 // CAN Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCCAN_R0 0x00000001 // CAN Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCADC register. +// +//***************************************************************************** +#define SYSCTL_RCGCADC_R1 0x00000002 // ADC Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCADC_R0 0x00000001 // ADC Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCACMP +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCACMP_R0 0x00000001 // Analog Comparator Module 0 Run + // Mode Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCPWM register. +// +//***************************************************************************** +#define SYSCTL_RCGCPWM_R1 0x00000002 // PWM Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCPWM_R0 0x00000001 // PWM Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCQEI register. +// +//***************************************************************************** +#define SYSCTL_RCGCQEI_R1 0x00000002 // QEI Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCQEI_R0 0x00000001 // QEI Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCEEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCEEPROM_R0 0x00000001 // EEPROM Module Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCWTIMER_R5 0x00000020 // 32/64-Bit Wide General-Purpose + // Timer 5 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCWTIMER_R4 0x00000010 // 32/64-Bit Wide General-Purpose + // Timer 4 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCWTIMER_R3 0x00000008 // 32/64-Bit Wide General-Purpose + // Timer 3 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCWTIMER_R2 0x00000004 // 32/64-Bit Wide General-Purpose + // Timer 2 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCWTIMER_R1 0x00000002 // 32/64-Bit Wide General-Purpose + // Timer 1 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCWTIMER_R0 0x00000001 // 32/64-Bit Wide General-Purpose + // Timer 0 Run Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCWD register. +// +//***************************************************************************** +#define SYSCTL_SCGCWD_S1 0x00000002 // Watchdog Timer 1 Sleep Mode + // Clock Gating Control +#define SYSCTL_SCGCWD_S0 0x00000001 // Watchdog Timer 0 Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCTIMER_S5 0x00000020 // 16/32-Bit General-Purpose Timer + // 5 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S4 0x00000010 // 16/32-Bit General-Purpose Timer + // 4 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S3 0x00000008 // 16/32-Bit General-Purpose Timer + // 3 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S2 0x00000004 // 16/32-Bit General-Purpose Timer + // 2 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S1 0x00000002 // 16/32-Bit General-Purpose Timer + // 1 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S0 0x00000001 // 16/32-Bit General-Purpose Timer + // 0 Sleep Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCGPIO +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCGPIO_S9 0x00000200 // GPIO Port K Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S8 0x00000100 // GPIO Port J Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S7 0x00000080 // GPIO Port H Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S6 0x00000040 // GPIO Port G Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S5 0x00000020 // GPIO Port F Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S4 0x00000010 // GPIO Port E Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S3 0x00000008 // GPIO Port D Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S2 0x00000004 // GPIO Port C Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S1 0x00000002 // GPIO Port B Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S0 0x00000001 // GPIO Port A Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCDMA register. +// +//***************************************************************************** +#define SYSCTL_SCGCDMA_S0 0x00000001 // uDMA Module Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCHIB register. +// +//***************************************************************************** +#define SYSCTL_SCGCHIB_S0 0x00000001 // Hibernation Module Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCUART +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCUART_S7 0x00000080 // UART Module 7 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S6 0x00000040 // UART Module 6 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S5 0x00000020 // UART Module 5 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S4 0x00000010 // UART Module 4 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S3 0x00000008 // UART Module 3 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S2 0x00000004 // UART Module 2 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S1 0x00000002 // UART Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S0 0x00000001 // UART Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCSSI register. +// +//***************************************************************************** +#define SYSCTL_SCGCSSI_S3 0x00000008 // SSI Module 3 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCSSI_S2 0x00000004 // SSI Module 2 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCSSI_S1 0x00000002 // SSI Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCSSI_S0 0x00000001 // SSI Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCI2C register. +// +//***************************************************************************** +#define SYSCTL_SCGCI2C_S5 0x00000020 // I2C Module 5 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S4 0x00000010 // I2C Module 4 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S3 0x00000008 // I2C Module 3 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S2 0x00000004 // I2C Module 2 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S1 0x00000002 // I2C Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S0 0x00000001 // I2C Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCUSB register. +// +//***************************************************************************** +#define SYSCTL_SCGCUSB_S0 0x00000001 // USB Module Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCCAN register. +// +//***************************************************************************** +#define SYSCTL_SCGCCAN_S1 0x00000002 // CAN Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCCAN_S0 0x00000001 // CAN Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCADC register. +// +//***************************************************************************** +#define SYSCTL_SCGCADC_S1 0x00000002 // ADC Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCADC_S0 0x00000001 // ADC Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCACMP +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCACMP_S0 0x00000001 // Analog Comparator Module 0 Sleep + // Mode Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCPWM register. +// +//***************************************************************************** +#define SYSCTL_SCGCPWM_S1 0x00000002 // PWM Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCPWM_S0 0x00000001 // PWM Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCQEI register. +// +//***************************************************************************** +#define SYSCTL_SCGCQEI_S1 0x00000002 // QEI Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCQEI_S0 0x00000001 // QEI Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCEEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCEEPROM_S0 0x00000001 // EEPROM Module Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCWTIMER_S5 0x00000020 // 32/64-Bit Wide General-Purpose + // Timer 5 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCWTIMER_S4 0x00000010 // 32/64-Bit Wide General-Purpose + // Timer 4 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCWTIMER_S3 0x00000008 // 32/64-Bit Wide General-Purpose + // Timer 3 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCWTIMER_S2 0x00000004 // 32/64-Bit Wide General-Purpose + // Timer 2 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCWTIMER_S1 0x00000002 // 32/64-Bit Wide General-Purpose + // Timer 1 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCWTIMER_S0 0x00000001 // 32/64-Bit Wide General-Purpose + // Timer 0 Sleep Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCWD register. +// +//***************************************************************************** +#define SYSCTL_DCGCWD_D1 0x00000002 // Watchdog Timer 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCWD_D0 0x00000001 // Watchdog Timer 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCTIMER_D5 0x00000020 // 16/32-Bit General-Purpose Timer + // 5 Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCTIMER_D4 0x00000010 // 16/32-Bit General-Purpose Timer + // 4 Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCTIMER_D3 0x00000008 // 16/32-Bit General-Purpose Timer + // 3 Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCTIMER_D2 0x00000004 // 16/32-Bit General-Purpose Timer + // 2 Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCTIMER_D1 0x00000002 // 16/32-Bit General-Purpose Timer + // 1 Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCTIMER_D0 0x00000001 // 16/32-Bit General-Purpose Timer + // 0 Deep-Sleep Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCGPIO +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCGPIO_D9 0x00000200 // GPIO Port K Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D8 0x00000100 // GPIO Port J Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D7 0x00000080 // GPIO Port H Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D6 0x00000040 // GPIO Port G Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D5 0x00000020 // GPIO Port F Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D4 0x00000010 // GPIO Port E Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D3 0x00000008 // GPIO Port D Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D2 0x00000004 // GPIO Port C Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D1 0x00000002 // GPIO Port B Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D0 0x00000001 // GPIO Port A Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCDMA register. +// +//***************************************************************************** +#define SYSCTL_DCGCDMA_D0 0x00000001 // uDMA Module Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCHIB register. +// +//***************************************************************************** +#define SYSCTL_DCGCHIB_D0 0x00000001 // Hibernation Module Deep-Sleep + // Mode Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCUART +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCUART_D7 0x00000080 // UART Module 7 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D6 0x00000040 // UART Module 6 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D5 0x00000020 // UART Module 5 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D4 0x00000010 // UART Module 4 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D3 0x00000008 // UART Module 3 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D2 0x00000004 // UART Module 2 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D1 0x00000002 // UART Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D0 0x00000001 // UART Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCSSI register. +// +//***************************************************************************** +#define SYSCTL_DCGCSSI_D3 0x00000008 // SSI Module 3 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCSSI_D2 0x00000004 // SSI Module 2 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCSSI_D1 0x00000002 // SSI Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCSSI_D0 0x00000001 // SSI Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCI2C register. +// +//***************************************************************************** +#define SYSCTL_DCGCI2C_D5 0x00000020 // I2C Module 5 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D4 0x00000010 // I2C Module 4 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D3 0x00000008 // I2C Module 3 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D2 0x00000004 // I2C Module 2 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D1 0x00000002 // I2C Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D0 0x00000001 // I2C Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCUSB register. +// +//***************************************************************************** +#define SYSCTL_DCGCUSB_D0 0x00000001 // USB Module Deep-Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCCAN register. +// +//***************************************************************************** +#define SYSCTL_DCGCCAN_D1 0x00000002 // CAN Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCCAN_D0 0x00000001 // CAN Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCADC register. +// +//***************************************************************************** +#define SYSCTL_DCGCADC_D1 0x00000002 // ADC Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCADC_D0 0x00000001 // ADC Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCACMP +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCACMP_D0 0x00000001 // Analog Comparator Module 0 + // Deep-Sleep Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCPWM register. +// +//***************************************************************************** +#define SYSCTL_DCGCPWM_D1 0x00000002 // PWM Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCPWM_D0 0x00000001 // PWM Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCQEI register. +// +//***************************************************************************** +#define SYSCTL_DCGCQEI_D1 0x00000002 // QEI Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCQEI_D0 0x00000001 // QEI Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCEEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCEEPROM_D0 0x00000001 // EEPROM Module Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCWTIMER_D5 0x00000020 // 32/64-Bit Wide General-Purpose + // Timer 5 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCWTIMER_D4 0x00000010 // 32/64-Bit Wide General-Purpose + // Timer 4 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCWTIMER_D3 0x00000008 // 32/64-Bit Wide General-Purpose + // Timer 3 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCWTIMER_D2 0x00000004 // 32/64-Bit Wide General-Purpose + // Timer 2 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCWTIMER_D1 0x00000002 // 32/64-Bit Wide General-Purpose + // Timer 1 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCWTIMER_D0 0x00000001 // 32/64-Bit Wide General-Purpose + // Timer 0 Deep-Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRWD register. +// +//***************************************************************************** +#define SYSCTL_PRWD_R1 0x00000002 // Watchdog Timer 1 Peripheral + // Ready +#define SYSCTL_PRWD_R0 0x00000001 // Watchdog Timer 0 Peripheral + // Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRTIMER register. +// +//***************************************************************************** +#define SYSCTL_PRTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer + // 5 Peripheral Ready +#define SYSCTL_PRTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer + // 4 Peripheral Ready +#define SYSCTL_PRTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer + // 3 Peripheral Ready +#define SYSCTL_PRTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer + // 2 Peripheral Ready +#define SYSCTL_PRTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer + // 1 Peripheral Ready +#define SYSCTL_PRTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer + // 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRGPIO register. +// +//***************************************************************************** +#define SYSCTL_PRGPIO_R9 0x00000200 // GPIO Port K Peripheral Ready +#define SYSCTL_PRGPIO_R8 0x00000100 // GPIO Port J Peripheral Ready +#define SYSCTL_PRGPIO_R7 0x00000080 // GPIO Port H Peripheral Ready +#define SYSCTL_PRGPIO_R6 0x00000040 // GPIO Port G Peripheral Ready +#define SYSCTL_PRGPIO_R5 0x00000020 // GPIO Port F Peripheral Ready +#define SYSCTL_PRGPIO_R4 0x00000010 // GPIO Port E Peripheral Ready +#define SYSCTL_PRGPIO_R3 0x00000008 // GPIO Port D Peripheral Ready +#define SYSCTL_PRGPIO_R2 0x00000004 // GPIO Port C Peripheral Ready +#define SYSCTL_PRGPIO_R1 0x00000002 // GPIO Port B Peripheral Ready +#define SYSCTL_PRGPIO_R0 0x00000001 // GPIO Port A Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRDMA register. +// +//***************************************************************************** +#define SYSCTL_PRDMA_R0 0x00000001 // uDMA Module Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRHIB register. +// +//***************************************************************************** +#define SYSCTL_PRHIB_R0 0x00000001 // Hibernation Module Peripheral + // Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRUART register. +// +//***************************************************************************** +#define SYSCTL_PRUART_R7 0x00000080 // UART Module 7 Peripheral Ready +#define SYSCTL_PRUART_R6 0x00000040 // UART Module 6 Peripheral Ready +#define SYSCTL_PRUART_R5 0x00000020 // UART Module 5 Peripheral Ready +#define SYSCTL_PRUART_R4 0x00000010 // UART Module 4 Peripheral Ready +#define SYSCTL_PRUART_R3 0x00000008 // UART Module 3 Peripheral Ready +#define SYSCTL_PRUART_R2 0x00000004 // UART Module 2 Peripheral Ready +#define SYSCTL_PRUART_R1 0x00000002 // UART Module 1 Peripheral Ready +#define SYSCTL_PRUART_R0 0x00000001 // UART Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRSSI register. +// +//***************************************************************************** +#define SYSCTL_PRSSI_R3 0x00000008 // SSI Module 3 Peripheral Ready +#define SYSCTL_PRSSI_R2 0x00000004 // SSI Module 2 Peripheral Ready +#define SYSCTL_PRSSI_R1 0x00000002 // SSI Module 1 Peripheral Ready +#define SYSCTL_PRSSI_R0 0x00000001 // SSI Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRI2C register. +// +//***************************************************************************** +#define SYSCTL_PRI2C_R5 0x00000020 // I2C Module 5 Peripheral Ready +#define SYSCTL_PRI2C_R4 0x00000010 // I2C Module 4 Peripheral Ready +#define SYSCTL_PRI2C_R3 0x00000008 // I2C Module 3 Peripheral Ready +#define SYSCTL_PRI2C_R2 0x00000004 // I2C Module 2 Peripheral Ready +#define SYSCTL_PRI2C_R1 0x00000002 // I2C Module 1 Peripheral Ready +#define SYSCTL_PRI2C_R0 0x00000001 // I2C Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRUSB register. +// +//***************************************************************************** +#define SYSCTL_PRUSB_R0 0x00000001 // USB Module Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRCAN register. +// +//***************************************************************************** +#define SYSCTL_PRCAN_R1 0x00000002 // CAN Module 1 Peripheral Ready +#define SYSCTL_PRCAN_R0 0x00000001 // CAN Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRADC register. +// +//***************************************************************************** +#define SYSCTL_PRADC_R1 0x00000002 // ADC Module 1 Peripheral Ready +#define SYSCTL_PRADC_R0 0x00000001 // ADC Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRACMP register. +// +//***************************************************************************** +#define SYSCTL_PRACMP_R0 0x00000001 // Analog Comparator Module 0 + // Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRPWM register. +// +//***************************************************************************** +#define SYSCTL_PRPWM_R1 0x00000002 // PWM Module 1 Peripheral Ready +#define SYSCTL_PRPWM_R0 0x00000001 // PWM Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRQEI register. +// +//***************************************************************************** +#define SYSCTL_PRQEI_R1 0x00000002 // QEI Module 1 Peripheral Ready +#define SYSCTL_PRQEI_R0 0x00000001 // QEI Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PREEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_PREEPROM_R0 0x00000001 // EEPROM Module Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_PRWTIMER_R5 0x00000020 // 32/64-Bit Wide General-Purpose + // Timer 5 Peripheral Ready +#define SYSCTL_PRWTIMER_R4 0x00000010 // 32/64-Bit Wide General-Purpose + // Timer 4 Peripheral Ready +#define SYSCTL_PRWTIMER_R3 0x00000008 // 32/64-Bit Wide General-Purpose + // Timer 3 Peripheral Ready +#define SYSCTL_PRWTIMER_R2 0x00000004 // 32/64-Bit Wide General-Purpose + // Timer 2 Peripheral Ready +#define SYSCTL_PRWTIMER_R1 0x00000002 // 32/64-Bit Wide General-Purpose + // Timer 1 Peripheral Ready +#define SYSCTL_PRWTIMER_R0 0x00000001 // 32/64-Bit Wide General-Purpose + // Timer 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_STAT register. +// +//***************************************************************************** +#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available uDMA Channels Minus 1 +#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine Status +#define UDMA_STAT_STATE_IDLE 0x00000000 // Idle +#define UDMA_STAT_STATE_RD_CTRL 0x00000010 // Reading channel controller data +#define UDMA_STAT_STATE_RD_SRCENDP \ + 0x00000020 // Reading source end pointer +#define UDMA_STAT_STATE_RD_DSTENDP \ + 0x00000030 // Reading destination end pointer +#define UDMA_STAT_STATE_RD_SRCDAT \ + 0x00000040 // Reading source data +#define UDMA_STAT_STATE_WR_DSTDAT \ + 0x00000050 // Writing destination data +#define UDMA_STAT_STATE_WAIT 0x00000060 // Waiting for uDMA request to + // clear +#define UDMA_STAT_STATE_WR_CTRL 0x00000070 // Writing channel controller data +#define UDMA_STAT_STATE_STALL 0x00000080 // Stalled +#define UDMA_STAT_STATE_DONE 0x00000090 // Done +#define UDMA_STAT_STATE_UNDEF 0x000000A0 // Undefined +#define UDMA_STAT_MASTEN 0x00000001 // Master Enable Status +#define UDMA_STAT_DMACHANS_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CFG register. +// +//***************************************************************************** +#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CTLBASE register. +// +//***************************************************************************** +#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address +#define UDMA_CTLBASE_ADDR_S 10 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ALTBASE register. +// +//***************************************************************************** +#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address + // Pointer +#define UDMA_ALTBASE_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_WAITSTAT register. +// +//***************************************************************************** +#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF // Channel [n] Wait Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_SWREQ register. +// +//***************************************************************************** +#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_USEBURSTSET +// register. +// +//***************************************************************************** +#define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF // Channel [n] Useburst Set + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_USEBURSTCLR +// register. +// +//***************************************************************************** +#define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF // Channel [n] Useburst Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_REQMASKSET +// register. +// +//***************************************************************************** +#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_REQMASKCLR +// register. +// +//***************************************************************************** +#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ENASET register. +// +//***************************************************************************** +#define UDMA_ENASET_SET_M 0xFFFFFFFF // Channel [n] Enable Set + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ENACLR register. +// +//***************************************************************************** +#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ALTSET register. +// +//***************************************************************************** +#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ALTCLR register. +// +//***************************************************************************** +#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_PRIOSET register. +// +//***************************************************************************** +#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_PRIOCLR register. +// +//***************************************************************************** +#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ERRCLR register. +// +//***************************************************************************** +#define UDMA_ERRCLR_ERRCLR 0x00000001 // uDMA Bus Error Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHASGN register. +// +//***************************************************************************** +#define UDMA_CHASGN_M 0xFFFFFFFF // Channel [n] Assignment Select +#define UDMA_CHASGN_PRIMARY 0x00000000 // Use the primary channel + // assignment +#define UDMA_CHASGN_SECONDARY 0x00000001 // Use the secondary channel + // assignment + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHIS register. +// +//***************************************************************************** +#define UDMA_CHIS_M 0xFFFFFFFF // Channel [n] Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHMAP0 register. +// +//***************************************************************************** +#define UDMA_CHMAP0_CH7SEL_M 0xF0000000 // uDMA Channel 7 Source Select +#define UDMA_CHMAP0_CH6SEL_M 0x0F000000 // uDMA Channel 6 Source Select +#define UDMA_CHMAP0_CH5SEL_M 0x00F00000 // uDMA Channel 5 Source Select +#define UDMA_CHMAP0_CH4SEL_M 0x000F0000 // uDMA Channel 4 Source Select +#define UDMA_CHMAP0_CH3SEL_M 0x0000F000 // uDMA Channel 3 Source Select +#define UDMA_CHMAP0_CH2SEL_M 0x00000F00 // uDMA Channel 2 Source Select +#define UDMA_CHMAP0_CH1SEL_M 0x000000F0 // uDMA Channel 1 Source Select +#define UDMA_CHMAP0_CH0SEL_M 0x0000000F // uDMA Channel 0 Source Select +#define UDMA_CHMAP0_CH7SEL_S 28 +#define UDMA_CHMAP0_CH6SEL_S 24 +#define UDMA_CHMAP0_CH5SEL_S 20 +#define UDMA_CHMAP0_CH4SEL_S 16 +#define UDMA_CHMAP0_CH3SEL_S 12 +#define UDMA_CHMAP0_CH2SEL_S 8 +#define UDMA_CHMAP0_CH1SEL_S 4 +#define UDMA_CHMAP0_CH0SEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHMAP1 register. +// +//***************************************************************************** +#define UDMA_CHMAP1_CH15SEL_M 0xF0000000 // uDMA Channel 15 Source Select +#define UDMA_CHMAP1_CH14SEL_M 0x0F000000 // uDMA Channel 14 Source Select +#define UDMA_CHMAP1_CH13SEL_M 0x00F00000 // uDMA Channel 13 Source Select +#define UDMA_CHMAP1_CH12SEL_M 0x000F0000 // uDMA Channel 12 Source Select +#define UDMA_CHMAP1_CH11SEL_M 0x0000F000 // uDMA Channel 11 Source Select +#define UDMA_CHMAP1_CH10SEL_M 0x00000F00 // uDMA Channel 10 Source Select +#define UDMA_CHMAP1_CH9SEL_M 0x000000F0 // uDMA Channel 9 Source Select +#define UDMA_CHMAP1_CH8SEL_M 0x0000000F // uDMA Channel 8 Source Select +#define UDMA_CHMAP1_CH15SEL_S 28 +#define UDMA_CHMAP1_CH14SEL_S 24 +#define UDMA_CHMAP1_CH13SEL_S 20 +#define UDMA_CHMAP1_CH12SEL_S 16 +#define UDMA_CHMAP1_CH11SEL_S 12 +#define UDMA_CHMAP1_CH10SEL_S 8 +#define UDMA_CHMAP1_CH9SEL_S 4 +#define UDMA_CHMAP1_CH8SEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHMAP2 register. +// +//***************************************************************************** +#define UDMA_CHMAP2_CH23SEL_M 0xF0000000 // uDMA Channel 23 Source Select +#define UDMA_CHMAP2_CH22SEL_M 0x0F000000 // uDMA Channel 22 Source Select +#define UDMA_CHMAP2_CH21SEL_M 0x00F00000 // uDMA Channel 21 Source Select +#define UDMA_CHMAP2_CH20SEL_M 0x000F0000 // uDMA Channel 20 Source Select +#define UDMA_CHMAP2_CH19SEL_M 0x0000F000 // uDMA Channel 19 Source Select +#define UDMA_CHMAP2_CH18SEL_M 0x00000F00 // uDMA Channel 18 Source Select +#define UDMA_CHMAP2_CH17SEL_M 0x000000F0 // uDMA Channel 17 Source Select +#define UDMA_CHMAP2_CH16SEL_M 0x0000000F // uDMA Channel 16 Source Select +#define UDMA_CHMAP2_CH23SEL_S 28 +#define UDMA_CHMAP2_CH22SEL_S 24 +#define UDMA_CHMAP2_CH21SEL_S 20 +#define UDMA_CHMAP2_CH20SEL_S 16 +#define UDMA_CHMAP2_CH19SEL_S 12 +#define UDMA_CHMAP2_CH18SEL_S 8 +#define UDMA_CHMAP2_CH17SEL_S 4 +#define UDMA_CHMAP2_CH16SEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHMAP3 register. +// +//***************************************************************************** +#define UDMA_CHMAP3_CH31SEL_M 0xF0000000 // uDMA Channel 31 Source Select +#define UDMA_CHMAP3_CH30SEL_M 0x0F000000 // uDMA Channel 30 Source Select +#define UDMA_CHMAP3_CH29SEL_M 0x00F00000 // uDMA Channel 29 Source Select +#define UDMA_CHMAP3_CH28SEL_M 0x000F0000 // uDMA Channel 28 Source Select +#define UDMA_CHMAP3_CH27SEL_M 0x0000F000 // uDMA Channel 27 Source Select +#define UDMA_CHMAP3_CH26SEL_M 0x00000F00 // uDMA Channel 26 Source Select +#define UDMA_CHMAP3_CH25SEL_M 0x000000F0 // uDMA Channel 25 Source Select +#define UDMA_CHMAP3_CH24SEL_M 0x0000000F // uDMA Channel 24 Source Select +#define UDMA_CHMAP3_CH31SEL_S 28 +#define UDMA_CHMAP3_CH30SEL_S 24 +#define UDMA_CHMAP3_CH29SEL_S 20 +#define UDMA_CHMAP3_CH28SEL_S 16 +#define UDMA_CHMAP3_CH27SEL_S 12 +#define UDMA_CHMAP3_CH26SEL_S 8 +#define UDMA_CHMAP3_CH25SEL_S 4 +#define UDMA_CHMAP3_CH24SEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_SRCENDP register. +// +//***************************************************************************** +#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer +#define UDMA_SRCENDP_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_DSTENDP register. +// +//***************************************************************************** +#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer +#define UDMA_DSTENDP_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CHCTL register. +// +//***************************************************************************** +#define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment +#define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte +#define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word +#define UDMA_CHCTL_DSTINC_32 0x80000000 // Word +#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment +#define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size +#define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte +#define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word +#define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word +#define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment +#define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte +#define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word +#define UDMA_CHCTL_SRCINC_32 0x08000000 // Word +#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment +#define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size +#define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte +#define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word +#define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word +#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size +#define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer +#define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers +#define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers +#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers +#define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers +#define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers +#define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers +#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers +#define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers +#define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers +#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers +#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1) +#define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst +#define UDMA_CHCTL_XFERMODE_M 0x00000007 // uDMA Transfer Mode +#define UDMA_CHCTL_XFERMODE_STOP \ + 0x00000000 // Stop +#define UDMA_CHCTL_XFERMODE_BASIC \ + 0x00000001 // Basic +#define UDMA_CHCTL_XFERMODE_AUTO \ + 0x00000002 // Auto-Request +#define UDMA_CHCTL_XFERMODE_PINGPONG \ + 0x00000003 // Ping-Pong +#define UDMA_CHCTL_XFERMODE_MEM_SG \ + 0x00000004 // Memory Scatter-Gather +#define UDMA_CHCTL_XFERMODE_MEM_SGA \ + 0x00000005 // Alternate Memory Scatter-Gather +#define UDMA_CHCTL_XFERMODE_PER_SG \ + 0x00000006 // Peripheral Scatter-Gather +#define UDMA_CHCTL_XFERMODE_PER_SGA \ + 0x00000007 // Alternate Peripheral + // Scatter-Gather +#define UDMA_CHCTL_XFERSIZE_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTLR register. +// +//***************************************************************************** +#define NVIC_ACTLR_DISOOFP 0x00000200 // Disable Out-Of-Order Floating + // Point +#define NVIC_ACTLR_DISFPCA 0x00000100 // Disable CONTROL +#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding +#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer +#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple + // Cycle Instructions + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CTRL register. +// +//***************************************************************************** +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag +#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_RELOAD register. +// +//***************************************************************************** +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value +#define NVIC_ST_RELOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CURRENT +// register. +// +//***************************************************************************** +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value +#define NVIC_ST_CURRENT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN0 register. +// +//***************************************************************************** +#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN1 register. +// +//***************************************************************************** +#define NVIC_EN1_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN2 register. +// +//***************************************************************************** +#define NVIC_EN2_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN3 register. +// +//***************************************************************************** +#define NVIC_EN3_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN4 register. +// +//***************************************************************************** +#define NVIC_EN4_INT_M 0x000007FF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS0 register. +// +//***************************************************************************** +#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS1 register. +// +//***************************************************************************** +#define NVIC_DIS1_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS2 register. +// +//***************************************************************************** +#define NVIC_DIS2_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS3 register. +// +//***************************************************************************** +#define NVIC_DIS3_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS4 register. +// +//***************************************************************************** +#define NVIC_DIS4_INT_M 0x000007FF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND0 register. +// +//***************************************************************************** +#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND1 register. +// +//***************************************************************************** +#define NVIC_PEND1_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND2 register. +// +//***************************************************************************** +#define NVIC_PEND2_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND3 register. +// +//***************************************************************************** +#define NVIC_PEND3_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND4 register. +// +//***************************************************************************** +#define NVIC_PEND4_INT_M 0x000007FF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND0 register. +// +//***************************************************************************** +#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND1 register. +// +//***************************************************************************** +#define NVIC_UNPEND1_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND2 register. +// +//***************************************************************************** +#define NVIC_UNPEND2_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND3 register. +// +//***************************************************************************** +#define NVIC_UNPEND3_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND4 register. +// +//***************************************************************************** +#define NVIC_UNPEND4_INT_M 0x000007FF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE0 register. +// +//***************************************************************************** +#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE1 register. +// +//***************************************************************************** +#define NVIC_ACTIVE1_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE2 register. +// +//***************************************************************************** +#define NVIC_ACTIVE2_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE3 register. +// +//***************************************************************************** +#define NVIC_ACTIVE3_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE4 register. +// +//***************************************************************************** +#define NVIC_ACTIVE4_INT_M 0x000007FF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI0 register. +// +//***************************************************************************** +#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask +#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask +#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask +#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask +#define NVIC_PRI0_INT3_S 29 +#define NVIC_PRI0_INT2_S 21 +#define NVIC_PRI0_INT1_S 13 +#define NVIC_PRI0_INT0_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI1 register. +// +//***************************************************************************** +#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask +#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask +#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask +#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask +#define NVIC_PRI1_INT7_S 29 +#define NVIC_PRI1_INT6_S 21 +#define NVIC_PRI1_INT5_S 13 +#define NVIC_PRI1_INT4_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI2 register. +// +//***************************************************************************** +#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask +#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask +#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask +#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask +#define NVIC_PRI2_INT11_S 29 +#define NVIC_PRI2_INT10_S 21 +#define NVIC_PRI2_INT9_S 13 +#define NVIC_PRI2_INT8_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI3 register. +// +//***************************************************************************** +#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask +#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask +#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask +#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask +#define NVIC_PRI3_INT15_S 29 +#define NVIC_PRI3_INT14_S 21 +#define NVIC_PRI3_INT13_S 13 +#define NVIC_PRI3_INT12_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI4 register. +// +//***************************************************************************** +#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask +#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask +#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask +#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask +#define NVIC_PRI4_INT19_S 29 +#define NVIC_PRI4_INT18_S 21 +#define NVIC_PRI4_INT17_S 13 +#define NVIC_PRI4_INT16_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI5 register. +// +//***************************************************************************** +#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask +#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask +#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask +#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask +#define NVIC_PRI5_INT23_S 29 +#define NVIC_PRI5_INT22_S 21 +#define NVIC_PRI5_INT21_S 13 +#define NVIC_PRI5_INT20_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI6 register. +// +//***************************************************************************** +#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask +#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask +#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask +#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask +#define NVIC_PRI6_INT27_S 29 +#define NVIC_PRI6_INT26_S 21 +#define NVIC_PRI6_INT25_S 13 +#define NVIC_PRI6_INT24_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI7 register. +// +//***************************************************************************** +#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask +#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask +#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask +#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask +#define NVIC_PRI7_INT31_S 29 +#define NVIC_PRI7_INT30_S 21 +#define NVIC_PRI7_INT29_S 13 +#define NVIC_PRI7_INT28_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI8 register. +// +//***************************************************************************** +#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask +#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask +#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask +#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask +#define NVIC_PRI8_INT35_S 29 +#define NVIC_PRI8_INT34_S 21 +#define NVIC_PRI8_INT33_S 13 +#define NVIC_PRI8_INT32_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI9 register. +// +//***************************************************************************** +#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask +#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask +#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask +#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask +#define NVIC_PRI9_INT39_S 29 +#define NVIC_PRI9_INT38_S 21 +#define NVIC_PRI9_INT37_S 13 +#define NVIC_PRI9_INT36_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI10 register. +// +//***************************************************************************** +#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask +#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask +#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask +#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask +#define NVIC_PRI10_INT43_S 29 +#define NVIC_PRI10_INT42_S 21 +#define NVIC_PRI10_INT41_S 13 +#define NVIC_PRI10_INT40_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI11 register. +// +//***************************************************************************** +#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask +#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask +#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask +#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask +#define NVIC_PRI11_INT47_S 29 +#define NVIC_PRI11_INT46_S 21 +#define NVIC_PRI11_INT45_S 13 +#define NVIC_PRI11_INT44_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI12 register. +// +//***************************************************************************** +#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask +#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask +#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask +#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask +#define NVIC_PRI12_INT51_S 29 +#define NVIC_PRI12_INT50_S 21 +#define NVIC_PRI12_INT49_S 13 +#define NVIC_PRI12_INT48_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI13 register. +// +//***************************************************************************** +#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask +#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask +#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask +#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask +#define NVIC_PRI13_INT55_S 29 +#define NVIC_PRI13_INT54_S 21 +#define NVIC_PRI13_INT53_S 13 +#define NVIC_PRI13_INT52_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI14 register. +// +//***************************************************************************** +#define NVIC_PRI14_INTD_M 0xE0000000 // Interrupt 59 Priority Mask +#define NVIC_PRI14_INTC_M 0x00E00000 // Interrupt 58 Priority Mask +#define NVIC_PRI14_INTB_M 0x0000E000 // Interrupt 57 Priority Mask +#define NVIC_PRI14_INTA_M 0x000000E0 // Interrupt 56 Priority Mask +#define NVIC_PRI14_INTD_S 29 +#define NVIC_PRI14_INTC_S 21 +#define NVIC_PRI14_INTB_S 13 +#define NVIC_PRI14_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI15 register. +// +//***************************************************************************** +#define NVIC_PRI15_INTD_M 0xE0000000 // Interrupt 63 Priority Mask +#define NVIC_PRI15_INTC_M 0x00E00000 // Interrupt 62 Priority Mask +#define NVIC_PRI15_INTB_M 0x0000E000 // Interrupt 61 Priority Mask +#define NVIC_PRI15_INTA_M 0x000000E0 // Interrupt 60 Priority Mask +#define NVIC_PRI15_INTD_S 29 +#define NVIC_PRI15_INTC_S 21 +#define NVIC_PRI15_INTB_S 13 +#define NVIC_PRI15_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI16 register. +// +//***************************************************************************** +#define NVIC_PRI16_INTD_M 0xE0000000 // Interrupt 67 Priority Mask +#define NVIC_PRI16_INTC_M 0x00E00000 // Interrupt 66 Priority Mask +#define NVIC_PRI16_INTB_M 0x0000E000 // Interrupt 65 Priority Mask +#define NVIC_PRI16_INTA_M 0x000000E0 // Interrupt 64 Priority Mask +#define NVIC_PRI16_INTD_S 29 +#define NVIC_PRI16_INTC_S 21 +#define NVIC_PRI16_INTB_S 13 +#define NVIC_PRI16_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI17 register. +// +//***************************************************************************** +#define NVIC_PRI17_INTD_M 0xE0000000 // Interrupt 71 Priority Mask +#define NVIC_PRI17_INTC_M 0x00E00000 // Interrupt 70 Priority Mask +#define NVIC_PRI17_INTB_M 0x0000E000 // Interrupt 69 Priority Mask +#define NVIC_PRI17_INTA_M 0x000000E0 // Interrupt 68 Priority Mask +#define NVIC_PRI17_INTD_S 29 +#define NVIC_PRI17_INTC_S 21 +#define NVIC_PRI17_INTB_S 13 +#define NVIC_PRI17_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI18 register. +// +//***************************************************************************** +#define NVIC_PRI18_INTD_M 0xE0000000 // Interrupt 75 Priority Mask +#define NVIC_PRI18_INTC_M 0x00E00000 // Interrupt 74 Priority Mask +#define NVIC_PRI18_INTB_M 0x0000E000 // Interrupt 73 Priority Mask +#define NVIC_PRI18_INTA_M 0x000000E0 // Interrupt 72 Priority Mask +#define NVIC_PRI18_INTD_S 29 +#define NVIC_PRI18_INTC_S 21 +#define NVIC_PRI18_INTB_S 13 +#define NVIC_PRI18_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI19 register. +// +//***************************************************************************** +#define NVIC_PRI19_INTD_M 0xE0000000 // Interrupt 79 Priority Mask +#define NVIC_PRI19_INTC_M 0x00E00000 // Interrupt 78 Priority Mask +#define NVIC_PRI19_INTB_M 0x0000E000 // Interrupt 77 Priority Mask +#define NVIC_PRI19_INTA_M 0x000000E0 // Interrupt 76 Priority Mask +#define NVIC_PRI19_INTD_S 29 +#define NVIC_PRI19_INTC_S 21 +#define NVIC_PRI19_INTB_S 13 +#define NVIC_PRI19_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI20 register. +// +//***************************************************************************** +#define NVIC_PRI20_INTD_M 0xE0000000 // Interrupt 83 Priority Mask +#define NVIC_PRI20_INTC_M 0x00E00000 // Interrupt 82 Priority Mask +#define NVIC_PRI20_INTB_M 0x0000E000 // Interrupt 81 Priority Mask +#define NVIC_PRI20_INTA_M 0x000000E0 // Interrupt 80 Priority Mask +#define NVIC_PRI20_INTD_S 29 +#define NVIC_PRI20_INTC_S 21 +#define NVIC_PRI20_INTB_S 13 +#define NVIC_PRI20_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI21 register. +// +//***************************************************************************** +#define NVIC_PRI21_INTD_M 0xE0000000 // Interrupt 87 Priority Mask +#define NVIC_PRI21_INTC_M 0x00E00000 // Interrupt 86 Priority Mask +#define NVIC_PRI21_INTB_M 0x0000E000 // Interrupt 85 Priority Mask +#define NVIC_PRI21_INTA_M 0x000000E0 // Interrupt 84 Priority Mask +#define NVIC_PRI21_INTD_S 29 +#define NVIC_PRI21_INTC_S 21 +#define NVIC_PRI21_INTB_S 13 +#define NVIC_PRI21_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI22 register. +// +//***************************************************************************** +#define NVIC_PRI22_INTD_M 0xE0000000 // Interrupt 91 Priority Mask +#define NVIC_PRI22_INTC_M 0x00E00000 // Interrupt 90 Priority Mask +#define NVIC_PRI22_INTB_M 0x0000E000 // Interrupt 89 Priority Mask +#define NVIC_PRI22_INTA_M 0x000000E0 // Interrupt 88 Priority Mask +#define NVIC_PRI22_INTD_S 29 +#define NVIC_PRI22_INTC_S 21 +#define NVIC_PRI22_INTB_S 13 +#define NVIC_PRI22_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI23 register. +// +//***************************************************************************** +#define NVIC_PRI23_INTD_M 0xE0000000 // Interrupt 95 Priority Mask +#define NVIC_PRI23_INTC_M 0x00E00000 // Interrupt 94 Priority Mask +#define NVIC_PRI23_INTB_M 0x0000E000 // Interrupt 93 Priority Mask +#define NVIC_PRI23_INTA_M 0x000000E0 // Interrupt 92 Priority Mask +#define NVIC_PRI23_INTD_S 29 +#define NVIC_PRI23_INTC_S 21 +#define NVIC_PRI23_INTB_S 13 +#define NVIC_PRI23_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI24 register. +// +//***************************************************************************** +#define NVIC_PRI24_INTD_M 0xE0000000 // Interrupt 99 Priority Mask +#define NVIC_PRI24_INTC_M 0x00E00000 // Interrupt 98 Priority Mask +#define NVIC_PRI24_INTB_M 0x0000E000 // Interrupt 97 Priority Mask +#define NVIC_PRI24_INTA_M 0x000000E0 // Interrupt 96 Priority Mask +#define NVIC_PRI24_INTD_S 29 +#define NVIC_PRI24_INTC_S 21 +#define NVIC_PRI24_INTB_S 13 +#define NVIC_PRI24_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI25 register. +// +//***************************************************************************** +#define NVIC_PRI25_INTD_M 0xE0000000 // Interrupt 103 Priority Mask +#define NVIC_PRI25_INTC_M 0x00E00000 // Interrupt 102 Priority Mask +#define NVIC_PRI25_INTB_M 0x0000E000 // Interrupt 101 Priority Mask +#define NVIC_PRI25_INTA_M 0x000000E0 // Interrupt 100 Priority Mask +#define NVIC_PRI25_INTD_S 29 +#define NVIC_PRI25_INTC_S 21 +#define NVIC_PRI25_INTB_S 13 +#define NVIC_PRI25_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI26 register. +// +//***************************************************************************** +#define NVIC_PRI26_INTD_M 0xE0000000 // Interrupt 107 Priority Mask +#define NVIC_PRI26_INTC_M 0x00E00000 // Interrupt 106 Priority Mask +#define NVIC_PRI26_INTB_M 0x0000E000 // Interrupt 105 Priority Mask +#define NVIC_PRI26_INTA_M 0x000000E0 // Interrupt 104 Priority Mask +#define NVIC_PRI26_INTD_S 29 +#define NVIC_PRI26_INTC_S 21 +#define NVIC_PRI26_INTB_S 13 +#define NVIC_PRI26_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI27 register. +// +//***************************************************************************** +#define NVIC_PRI27_INTD_M 0xE0000000 // Interrupt 111 Priority Mask +#define NVIC_PRI27_INTC_M 0x00E00000 // Interrupt 110 Priority Mask +#define NVIC_PRI27_INTB_M 0x0000E000 // Interrupt 109 Priority Mask +#define NVIC_PRI27_INTA_M 0x000000E0 // Interrupt 108 Priority Mask +#define NVIC_PRI27_INTD_S 29 +#define NVIC_PRI27_INTC_S 21 +#define NVIC_PRI27_INTB_S 13 +#define NVIC_PRI27_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI28 register. +// +//***************************************************************************** +#define NVIC_PRI28_INTD_M 0xE0000000 // Interrupt 115 Priority Mask +#define NVIC_PRI28_INTC_M 0x00E00000 // Interrupt 114 Priority Mask +#define NVIC_PRI28_INTB_M 0x0000E000 // Interrupt 113 Priority Mask +#define NVIC_PRI28_INTA_M 0x000000E0 // Interrupt 112 Priority Mask +#define NVIC_PRI28_INTD_S 29 +#define NVIC_PRI28_INTC_S 21 +#define NVIC_PRI28_INTB_S 13 +#define NVIC_PRI28_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI29 register. +// +//***************************************************************************** +#define NVIC_PRI29_INTD_M 0xE0000000 // Interrupt 119 Priority Mask +#define NVIC_PRI29_INTC_M 0x00E00000 // Interrupt 118 Priority Mask +#define NVIC_PRI29_INTB_M 0x0000E000 // Interrupt 117 Priority Mask +#define NVIC_PRI29_INTA_M 0x000000E0 // Interrupt 116 Priority Mask +#define NVIC_PRI29_INTD_S 29 +#define NVIC_PRI29_INTC_S 21 +#define NVIC_PRI29_INTB_S 13 +#define NVIC_PRI29_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI30 register. +// +//***************************************************************************** +#define NVIC_PRI30_INTD_M 0xE0000000 // Interrupt 123 Priority Mask +#define NVIC_PRI30_INTC_M 0x00E00000 // Interrupt 122 Priority Mask +#define NVIC_PRI30_INTB_M 0x0000E000 // Interrupt 121 Priority Mask +#define NVIC_PRI30_INTA_M 0x000000E0 // Interrupt 120 Priority Mask +#define NVIC_PRI30_INTD_S 29 +#define NVIC_PRI30_INTC_S 21 +#define NVIC_PRI30_INTB_S 13 +#define NVIC_PRI30_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI31 register. +// +//***************************************************************************** +#define NVIC_PRI31_INTD_M 0xE0000000 // Interrupt 127 Priority Mask +#define NVIC_PRI31_INTC_M 0x00E00000 // Interrupt 126 Priority Mask +#define NVIC_PRI31_INTB_M 0x0000E000 // Interrupt 125 Priority Mask +#define NVIC_PRI31_INTA_M 0x000000E0 // Interrupt 124 Priority Mask +#define NVIC_PRI31_INTD_S 29 +#define NVIC_PRI31_INTC_S 21 +#define NVIC_PRI31_INTB_S 13 +#define NVIC_PRI31_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI32 register. +// +//***************************************************************************** +#define NVIC_PRI32_INTD_M 0xE0000000 // Interrupt 131 Priority Mask +#define NVIC_PRI32_INTC_M 0x00E00000 // Interrupt 130 Priority Mask +#define NVIC_PRI32_INTB_M 0x0000E000 // Interrupt 129 Priority Mask +#define NVIC_PRI32_INTA_M 0x000000E0 // Interrupt 128 Priority Mask +#define NVIC_PRI32_INTD_S 29 +#define NVIC_PRI32_INTC_S 21 +#define NVIC_PRI32_INTB_S 13 +#define NVIC_PRI32_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI33 register. +// +//***************************************************************************** +#define NVIC_PRI33_INTD_M 0xE0000000 // Interrupt Priority for Interrupt + // [4n+3] +#define NVIC_PRI33_INTC_M 0x00E00000 // Interrupt Priority for Interrupt + // [4n+2] +#define NVIC_PRI33_INTB_M 0x0000E000 // Interrupt Priority for Interrupt + // [4n+1] +#define NVIC_PRI33_INTA_M 0x000000E0 // Interrupt Priority for Interrupt + // [4n] +#define NVIC_PRI33_INTD_S 29 +#define NVIC_PRI33_INTC_S 21 +#define NVIC_PRI33_INTB_S 13 +#define NVIC_PRI33_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI34 register. +// +//***************************************************************************** +#define NVIC_PRI34_INTD_M 0xE0000000 // Interrupt Priority for Interrupt + // [4n+3] +#define NVIC_PRI34_INTC_M 0x00E00000 // Interrupt Priority for Interrupt + // [4n+2] +#define NVIC_PRI34_INTB_M 0x0000E000 // Interrupt Priority for Interrupt + // [4n+1] +#define NVIC_PRI34_INTA_M 0x000000E0 // Interrupt Priority for Interrupt + // [4n] +#define NVIC_PRI34_INTD_S 29 +#define NVIC_PRI34_INTC_S 21 +#define NVIC_PRI34_INTB_S 13 +#define NVIC_PRI34_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CPUID register. +// +//***************************************************************************** +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code +#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number +#define NVIC_CPUID_CON_M 0x000F0000 // Constant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number +#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor +#define NVIC_CPUID_REV_M 0x0000000F // Revision Number + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_INT_CTRL register. +// +//***************************************************************************** +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending +#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending +#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number +#define NVIC_INT_CTRL_VEC_PEN_NMI \ + 0x00002000 // NMI +#define NVIC_INT_CTRL_VEC_PEN_HARD \ + 0x00003000 // Hard fault +#define NVIC_INT_CTRL_VEC_PEN_MEM \ + 0x00004000 // Memory management fault +#define NVIC_INT_CTRL_VEC_PEN_BUS \ + 0x00005000 // Bus fault +#define NVIC_INT_CTRL_VEC_PEN_USG \ + 0x00006000 // Usage fault +#define NVIC_INT_CTRL_VEC_PEN_SVC \ + 0x0000B000 // SVCall +#define NVIC_INT_CTRL_VEC_PEN_PNDSV \ + 0x0000E000 // PendSV +#define NVIC_INT_CTRL_VEC_PEN_TICK \ + 0x0000F000 // SysTick +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base +#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number +#define NVIC_INT_CTRL_VEC_ACT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_VTABLE register. +// +//***************************************************************************** +#define NVIC_VTABLE_OFFSET_M 0xFFFFFC00 // Vector Table Offset +#define NVIC_VTABLE_OFFSET_S 10 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_APINT register. +// +//***************************************************************************** +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key +#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key +#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping +#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split +#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split +#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split +#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split +#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split +#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split +#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split +#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault +#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CFG_CTRL register. +// +//***************************************************************************** +#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception + // Entry +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and + // Fault +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI1 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority +#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority +#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority +#define NVIC_SYS_PRI1_USAGE_S 21 +#define NVIC_SYS_PRI1_BUS_S 13 +#define NVIC_SYS_PRI1_MEM_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI2 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority +#define NVIC_SYS_PRI2_SVC_S 29 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI3 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority +#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority +#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority +#define NVIC_SYS_PRI3_TICK_S 29 +#define NVIC_SYS_PRI3_PENDSV_S 21 +#define NVIC_SYS_PRI3_DEBUG_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL +// register. +// +//***************************************************************************** +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending +#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending +#define NVIC_SYS_HND_CTRL_USAGEP \ + 0x00001000 // Usage Fault Pending +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage + // Fault +#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid +#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy + // State Preservation +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error +#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address + // Register Valid +#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on + // Floating-Point Lazy State + // Preservation +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_HFAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DEBUG_STAT +// register. +// +//***************************************************************************** +#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted +#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch +#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match +#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction +#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MM_ADDR register. +// +//***************************************************************************** +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_MM_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_ADDR +// register. +// +//***************************************************************************** +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_FAULT_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CPAC register. +// +//***************************************************************************** +#define NVIC_CPAC_CP11_M 0x00C00000 // CP11 Coprocessor Access + // Privilege +#define NVIC_CPAC_CP11_DIS 0x00000000 // Access Denied +#define NVIC_CPAC_CP11_PRIV 0x00400000 // Privileged Access Only +#define NVIC_CPAC_CP11_FULL 0x00C00000 // Full Access +#define NVIC_CPAC_CP10_M 0x00300000 // CP10 Coprocessor Access + // Privilege +#define NVIC_CPAC_CP10_DIS 0x00000000 // Access Denied +#define NVIC_CPAC_CP10_PRIV 0x00100000 // Privileged Access Only +#define NVIC_CPAC_CP10_FULL 0x00300000 // Full Access + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_TYPE register. +// +//***************************************************************************** +#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I Regions +#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D Regions +#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or Unified MPU +#define NVIC_MPU_TYPE_IREGION_S 16 +#define NVIC_MPU_TYPE_DREGION_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_CTRL register. +// +//***************************************************************************** +#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU Default Region +#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU Enabled During Faults +#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_NUMBER +// register. +// +//***************************************************************************** +#define NVIC_MPU_NUMBER_M 0x00000007 // MPU Region to Access +#define NVIC_MPU_NUMBER_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE register. +// +//***************************************************************************** +#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE_ADDR_S 5 +#define NVIC_MPU_BASE_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable +#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable +#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable +#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE1 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE1_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE1_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE1_ADDR_S 5 +#define NVIC_MPU_BASE1_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR1_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR1_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR1_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR1_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR1_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR1_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR1_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR1_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR1_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE2 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE2_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE2_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE2_ADDR_S 5 +#define NVIC_MPU_BASE2_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR2_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR2_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR2_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR2_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR2_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR2_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR2_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR2_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR2_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE3 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE3_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE3_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE3_ADDR_S 5 +#define NVIC_MPU_BASE3_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR3_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR3_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR3_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR3_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR3_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR3_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR3_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR3_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR3_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_CTRL register. +// +//***************************************************************************** +#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask +#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key +#define NVIC_DBG_CTRL_S_RESET_ST \ + 0x02000000 // Core has reset since last read +#define NVIC_DBG_CTRL_S_RETIRE_ST \ + 0x01000000 // Core has executed insruction + // since last read +#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up +#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping +#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt +#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available +#define NVIC_DBG_CTRL_C_SNAPSTALL \ + 0x00000020 // Breaks a stalled load/store +#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping +#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core +#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core +#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_XFER register. +// +//***************************************************************************** +#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read +#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register +#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 +#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 +#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 +#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 +#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 +#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 +#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 +#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 +#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 +#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 +#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 +#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 +#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 +#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 +#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 +#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 +#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register +#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP +#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP +#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP +#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_DATA register. +// +//***************************************************************************** +#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache +#define NVIC_DBG_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_INT register. +// +//***************************************************************************** +#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault +#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors +#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error +#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state +#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check +#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error +#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault +#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status +#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset +#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending +#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SW_TRIG register. +// +//***************************************************************************** +#define NVIC_SW_TRIG_INTID_M 0x000000FF // Interrupt ID +#define NVIC_SW_TRIG_INTID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FPCC register. +// +//***************************************************************************** +#define NVIC_FPCC_ASPEN 0x80000000 // Automatic State Preservation + // Enable +#define NVIC_FPCC_LSPEN 0x40000000 // Lazy State Preservation Enable +#define NVIC_FPCC_MONRDY 0x00000100 // Monitor Ready +#define NVIC_FPCC_BFRDY 0x00000040 // Bus Fault Ready +#define NVIC_FPCC_MMRDY 0x00000020 // Memory Management Fault Ready +#define NVIC_FPCC_HFRDY 0x00000010 // Hard Fault Ready +#define NVIC_FPCC_THREAD 0x00000008 // Thread Mode +#define NVIC_FPCC_USER 0x00000002 // User Privilege Level +#define NVIC_FPCC_LSPACT 0x00000001 // Lazy State Preservation Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FPCA register. +// +//***************************************************************************** +#define NVIC_FPCA_ADDRESS_M 0xFFFFFFF8 // Address +#define NVIC_FPCA_ADDRESS_S 3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FPDSC register. +// +//***************************************************************************** +#define NVIC_FPDSC_AHP 0x04000000 // AHP Bit Default +#define NVIC_FPDSC_DN 0x02000000 // DN Bit Default +#define NVIC_FPDSC_FZ 0x01000000 // FZ Bit Default +#define NVIC_FPDSC_RMODE_M 0x00C00000 // RMODE Bit Default +#define NVIC_FPDSC_RMODE_RN 0x00000000 // Round to Nearest (RN) mode +#define NVIC_FPDSC_RMODE_RP 0x00400000 // Round towards Plus Infinity (RP) + // mode +#define NVIC_FPDSC_RMODE_RM 0x00800000 // Round towards Minus Infinity + // (RM) mode +#define NVIC_FPDSC_RMODE_RZ 0x00C00000 // Round towards Zero (RZ) mode + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED +#define SYSCTL_DID0_CLASS_BLIZZARD \ + 0x00050000 // Tiva(TM) C Series TM4C123-class + // microcontrollers + +#endif + +#endif // __TM4C123GH6PZ_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/interrupt.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/interrupt.h new file mode 100644 index 0000000000000000000000000000000000000000..effb30c88a494db7cb7c24268d8d7f30edd99389 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/interrupt.h @@ -0,0 +1,94 @@ +//***************************************************************************** +// +// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_INTERRUPT_H__ +#define __DRIVERLIB_INTERRUPT_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Macro to generate an interrupt priority mask based on the number of bits +// of priority supported by the hardware. +// +//***************************************************************************** +#define INT_PRIORITY_MASK ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF) + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern bool IntMasterEnable(void); +extern bool IntMasterDisable(void); +extern void IntRegister(uint32_t ui32Interrupt, void (*pfnHandler)(void)); +extern void IntUnregister(uint32_t ui32Interrupt); +extern void IntPriorityGroupingSet(uint32_t ui32Bits); +extern uint32_t IntPriorityGroupingGet(void); +extern void IntPrioritySet(uint32_t ui32Interrupt, + uint8_t ui8Priority); +extern int32_t IntPriorityGet(uint32_t ui32Interrupt); +extern void IntEnable(uint32_t ui32Interrupt); +extern void IntDisable(uint32_t ui32Interrupt); +extern uint32_t IntIsEnabled(uint32_t ui32Interrupt); +extern void IntPendSet(uint32_t ui32Interrupt); +extern void IntPendClear(uint32_t ui32Interrupt); +extern void IntPriorityMaskSet(uint32_t ui32PriorityMask); +extern uint32_t IntPriorityMaskGet(void); +extern void IntTrigger(uint32_t ui32Interrupt); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_INTERRUPT_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/lcd.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/lcd.h new file mode 100644 index 0000000000000000000000000000000000000000..766cf943615ac1f1634026844788fd1501d92b8c --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/lcd.h @@ -0,0 +1,487 @@ +//***************************************************************************** +// +// lcd.h - Defines and Macros for the LCD Controller module. +// +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_LCD_H__ +#define __DRIVERLIB_LCD_H__ + +//***************************************************************************** +// +//! \addtogroup lcd_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! This macro can be used to convert a 24-bit RGB color value as used by the +//! TivaWare Graphics Library into a 12-bit LCD controller color palette +//! entry. +// +//***************************************************************************** +#define PAL_FROM_RGB(ui32RGBColor) (((ui32RGBColor & 0xF0) >> 4) | \ + ((ui32RGBColor & 0xF000) >> 8) | \ + ((ui32RGBColor & 0xF00000) >> 12)) + +//***************************************************************************** +// +//! This macro can be used to convert from time in microseconds to periods of +//! the supplied clock in Hertz as required when setting up the LIDD and raster +//! timing structures. The calculation will round such that the number of +//! cycles returned represents no longer a time than specified in the +//! ui32Time_uS parameter. Values of ui32Time_uS less than or equal to +//! 4294967uS (4.29 seconds) are supported by the macro. Larger values will +//! cause arithmetic overflow and yield incorrect values. It is further +//! assumed that ui32ClockFreq is a non-zero multiple of 1000000 (1MHz). +// +//***************************************************************************** +#define CYCLES_FROM_TIME_US(ui32ClockFreq, ui32Time_uS) \ + (((ui32Time_uS) == 0) ? 0 : \ + (((ui32ClockFreq) / 1000000) * ((((ui32Time_uS) * 1000) - 1) / 1000)) + 1) + +//***************************************************************************** +// +//! This macro can be used to convert from time in nanoseconds to periods of +//! the supplied clock in Hertz as required when setting up the LIDD and raster +//! timing structures. The calculation will round such that the number of +//! cycles returned represents no longer a time than specified in the +//! ui32Time_nS parameter. Values of ui32Time_nS less than or equal to +//! 35791394 (35.79 milliseconds) are supported by the macro. Larger values +//! will cause arithmetic overflow and yield incorrect values. It is further +//! assumed that ui32ClockFreq is a non-zero multiple of 1000000 (1MHz). +// +//***************************************************************************** +#define CYCLES_FROM_TIME_NS(ui32ClockFreq, ui32Time_nS) \ + (((ui32Time_nS) == 0) ? 0 : \ + ((((((ui32ClockFreq) / 1000000) * ((ui32Time_nS) - 1)) / 1000)) + 1)) + +//***************************************************************************** +// +//! A structure containing timing parameters for the LIDD (LCD Interface +//! Display Driver) interface. This is used with the LCDIDDTimingSet function. +// +//***************************************************************************** +typedef struct +{ + // + //! Write Strobe Set-Up cycles. When performing a write access, this + //! field defines the number of MCLK cycles that Data Bus/Pad Output + //! Enable, ALE, the Direction bit, and Chip Select have to be ready before + //! the Write Strobe is asserted. Valid values are from 0 to 31. + // + uint8_t ui8WSSetup; + + // + //! Write Strobe Duration cycles. Field value defines the number of MCLK + //! cycles for which the Write Strobe is held active when performing a + //! write access. Valid values are from 1 to 63. + // + uint8_t ui8WSDuration; + + // + //! Write Strobe Hold cycles. Field value defines the number of MCLK + //! cycles for which Data Bus/Pad Output Enable, ALE, the Direction bit, + //! and Chip Select are held after the Write Strobe is deasserted when + //! performing a write access. Valid values are from 1 to 15. + // + uint8_t ui8WSHold; + + // + //! Read Strobe Set-Up cycles. When performing a read access, this field + //! defines the number of MCLK cycles that Data Bus/Pad Output Enable, ALE, + //! the Direction bit, and Chip Select have to be ready before the Read + //! Strobe is asserted. Valid values are from 0 to 31. + // + uint8_t ui8RSSetup; + + // + //! Read Strobe Duration cycles. Field value defines the number of MCLK + //! cycles for which the Read Strobe is held active when performing a read + //! access. Valid values are from 1 to 63. + // + uint8_t ui8RSDuration; + + // + //! Read Strobe Hold cycles. Field value defines the number of MCLK cycles + //! for which Data Bus/Pad Output Enable, ALE, the Direction bit, and Chip + //! Select are held after the Read Strobe is deasserted when performing a + //! read access. Valid values are from 1 to 15. + // + uint8_t ui8RSHold; + + // + //! Field value defines the number of MCLK cycles between the end of one + //! device access and the start of another device access using the same + //! Chip Select unless the two accesses are both Reads. In this case, + //! this delay is not incurred. Valid vales are from 1 to 4. + // + uint8_t ui8DelayCycles; +} +tLCDIDDTiming; + +// +// Values which can be ORed together within the ui32Flags field of the +// tLCDRasterTiming structure. +// +#define RASTER_TIMING_SYNCS_OPPOSITE_PIXCLK \ + 0x00000000 +#define RASTER_TIMING_SYNCS_ON_RISING_PIXCLK \ + 0x02000000 +#define RASTER_TIMING_SYNCS_ON_FALLING_PIXCLK \ + 0x03000000 +#define RASTER_TIMING_ACTIVE_HIGH_OE \ + 0x00000000 +#define RASTER_TIMING_ACTIVE_LOW_OE \ + 0x00800000 +#define RASTER_TIMING_ACTIVE_HIGH_PIXCLK \ + 0x00000000 +#define RASTER_TIMING_ACTIVE_LOW_PIXCLK \ + 0x00400000 +#define RASTER_TIMING_ACTIVE_HIGH_HSYNC \ + 0x00000000 +#define RASTER_TIMING_ACTIVE_LOW_HSYNC \ + 0x00200000 +#define RASTER_TIMING_ACTIVE_HIGH_VSYNC \ + 0x00000000 +#define RASTER_TIMING_ACTIVE_LOW_VSYNC \ + 0x00100000 + +// +//! A structure containing timing parameters for the raster interface. This is +//! used with the LCDRasterTimingSet function. +// +typedef struct +{ + // + //! Flags configuring the polarity and active edges of the various signals + //! in the raster interface. This field is comprised of a logical OR of + //! the labels with prefix ``RASTER_TIMING_''. + // + uint32_t ui32Flags; + + // + //! The number of pixels contained within each line on the LCD display. + //! Valid values are multiple of 16 less than or equal to 2048. + // + uint16_t ui16PanelWidth; + + // + //! The number of lines on the LCD display. Valid values are from 1 to + //! 2048. + // + uint16_t ui16PanelHeight; + + // + //! A value from 1 to 1024 that specifies the number of pixel clock periods + //! to add to the end of each line after active video has ended. + // + uint16_t ui16HFrontPorch; + + // + //! A value from 1 to 1024 that specifies the number of pixel clock periods + //! to add to the beginning of a line before active video is asserted. + // + uint16_t ui16HBackPorch; + + // + //! A value from 1 to 1024 that specifies the number of pixel clock periods + //! to pulse the line clock at the end of each line. + // + uint16_t ui16HSyncWidth; + + // + //! A value from 0 to 255 that specifies the number of line clock periods + //! to add to the end of each frame after the last active line. + // + uint8_t ui8VFrontPorch; + + // + //! A value from 0 to 255 that specifies the number of line clock periods + //! to add to the beginning of a frame before the first active line is + //! output to the display. + // + uint8_t ui8VBackPorch; + + // + //! In active mode, a value from 1 to 64 that specifies the number of + //! line clock periods to set the lcd_fp pin active at the end of each + //! frame after the vertical front porch period elapses. The number of + //! The frame clock is used as the VSYNC signal in active mode. + //! + //! In passive mode, a value from 1 to 64 that specifies the number of + //! extra line clock periods to insert after the vertical front porch + //! period has elapsed. Note that the width of lcd_fp is not affected by + //! this value in passive mode. + // + uint8_t ui8VSyncWidth; + + // + //! A value from 0 to 255 that specifies the number of line clocks to + //! count before transitioning the AC Bias pin. This pin is used to + //! periodically invert the polarity of the power supply to prevent DC + //! charge build-up within the display. + // + uint8_t ui8ACBiasLineCount; +} +tLCDRasterTiming; + +//***************************************************************************** +// +// Possible values for the ui8Mode parameter to LCDModeSet(). The label +// LCD_MODE_AUTO_UFLOW_RESTART may be ORed with either of the other two. +// +//***************************************************************************** +#define LCD_MODE_LIDD ((uint8_t)0x00) +#define LCD_MODE_RASTER ((uint8_t)0x01) +#define LCD_MODE_AUTO_UFLOW_RESTART \ + ((uint8_t)0x02) + +//***************************************************************************** +// +// Values used to construct the ui32Config parameter to LCDIDDConfigSet(). +// +//***************************************************************************** +#define LIDD_CONFIG_SYNC_MPU68 0x00000000 +#define LIDD_CONFIG_ASYNC_MPU68 0x00000001 +#define LIDD_CONFIG_SYNC_MPU80 0x00000002 +#define LIDD_CONFIG_ASYNC_MPU80 0x00000003 +#define LIDD_CONFIG_ASYNC_HITACHI \ + 0x00000004 +#define LIDD_CONFIG_INVERT_ALE 0x00000008 +#define LIDD_CONFIG_INVERT_RS_EN \ + 0x00000010 +#define LIDD_CONFIG_INVERT_WS_DIR \ + 0x00000020 +#define LIDD_CONFIG_INVERT_CS0 0x00000040 +#define LIDD_CONFIG_INVERT_CS1 0x00000080 + +//***************************************************************************** +// +// Values used to construct the ui32Config parameter to +// LCDRasterConfigSet(). Valid parameters contain one of the RASTER_FMT_xxx +// labels optionally ORed with the other flags. Only one of +// RASTER_LOAD_DATA_ONLY and RASTER_LOAD_PALETTE_ONLY may be specified (if +// neither is specified, the controller will load both palette and data when +// scanning out the frame buffer). +// +//***************************************************************************** +#define RASTER_FMT_ACTIVE_24BPP_PACKED \ + 0x02000080 +#define RASTER_FMT_ACTIVE_24BPP_UNPACKED \ + 0x06000080 +#define RASTER_FMT_ACTIVE_PALETTIZED_12BIT \ + 0x00000080 +#define RASTER_FMT_ACTIVE_PALETTIZED_16BIT \ + 0x00800080 +#define RASTER_FMT_PASSIVE_MONO_4PIX \ + 0x00000002 +#define RASTER_FMT_PASSIVE_MONO_8PIX \ + 0x00000202 +#define RASTER_FMT_PASSIVE_PALETTIZED \ + 0x00000000 +#define RASTER_FMT_PASSIVE_COLOR_12BIT \ + 0x00000000 +#define RASTER_FMT_PASSIVE_COLOR_16BIT \ + 0x01000000 +#define RASTER_ACTVID_DURING_BLANK \ + 0x08000000 +#define RASTER_NIBBLE_MODE_ENABLED \ + 0x00400000 +#define RASTER_LOAD_DATA_ONLY 0x00200000 +#define RASTER_LOAD_PALETTE_ONLY \ + 0x00100000 +#define RASTER_READ_ORDER_REVERSED \ + 0x00000100 + +//***************************************************************************** +// +// Interrupt sources for the LCD controller. These may be ORed together and +// passed to LCDIntEnable(), LCDIntDisable() and LCDIntClear(). They are also +// returned by LCDIntStatus(). +// +//***************************************************************************** +#define LCD_INT_DMA_DONE 0x00000001 +#define LCD_INT_RASTER_FRAME_DONE \ + 0x00000002 +#define LCD_INT_SYNC_LOST 0x00000004 +#define LCD_INT_AC_BIAS_CNT 0x00000008 +#define LCD_INT_UNDERFLOW 0x00000020 +#define LCD_INT_PAL_LOAD 0x00000040 +#define LCD_INT_EOF0 0x00000100 +#define LCD_INT_EOF1 0x00000200 + +//***************************************************************************** +// +// Configuration values used with LCDDMAConfigSet(). +// +//***************************************************************************** +#define LCD_DMA_FIFORDY_8_WORDS 0x00000000 +#define LCD_DMA_FIFORDY_16_WORDS \ + 0x00000100 +#define LCD_DMA_FIFORDY_32_WORDS \ + 0x00000200 +#define LCD_DMA_FIFORDY_64_WORDS \ + 0x00000300 +#define LCD_DMA_FIFORDY_128_WORDS \ + 0x00000400 +#define LCD_DMA_FIFORDY_256_WORDS \ + 0x00000500 +#define LCD_DMA_FIFORDY_512_WORDS \ + 0x00000600 +#define LCD_DMA_BURST_1 0x00000010 +#define LCD_DMA_BURST_2 0x00000010 +#define LCD_DMA_BURST_4 0x00000020 +#define LCD_DMA_BURST_8 0x00000030 +#define LCD_DMA_BURST_16 0x00000040 +#define LCD_DMA_BYTE_ORDER_0123 0x00000000 +#define LCD_DMA_BYTE_ORDER_1023 0x00000008 +#define LCD_DMA_BYTE_ORDER_3210 0x00000002 +#define LCD_DMA_BYTE_ORDER_2301 0x0000000A +#define LCD_DMA_PING_PONG 0x00000001 + +//***************************************************************************** +// +// Type values used with LCDRasterPaletteSet(). +// +//***************************************************************************** +#define LCD_PALETTE_TYPE_1BPP 0x00000000 +#define LCD_PALETTE_TYPE_2BPP 0x00001000 +#define LCD_PALETTE_TYPE_4BPP 0x00002000 +#define LCD_PALETTE_TYPE_8BPP 0x00003000 +#define LCD_PALETTE_TYPE_DIRECT 0x00004000 +#define LCD_PALETTE_SRC_24BIT 0x80000000 + +//***************************************************************************** +// +// Flags used in the ui32Clocks parameter to LCDClockReset(). +// +//***************************************************************************** +#define LCD_CLOCK_MAIN 0x00000008 +#define LCD_CLOCK_DMA 0x00000004 +#define LCD_CLOCK_LIDD 0x00000002 +#define LCD_CLOCK_CORE 0x00000001 + +//***************************************************************************** +// +// Flags used in with LCDSubPanelConfigSet(). +// +//***************************************************************************** +#define LCD_SUBPANEL_AT_TOP 0x20000000 +#define LCD_SUBPANEL_AT_BOTTOM 0x00000000 + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Function Prototypes. +// +//***************************************************************************** +extern uint32_t LCDModeSet(uint32_t ui32Base, uint8_t ui8Mode, + uint32_t ui32PixClk, uint32_t ui32SysClk); +extern void LCDClockReset(uint32_t ui32Base, uint32_t ui32Clocks); +extern void LCDIDDConfigSet(uint32_t ui32Base, uint32_t ui32Config); +extern void LCDIDDTimingSet(uint32_t ui32Base, uint32_t ui32CS, + const tLCDIDDTiming *pTiming); +extern void LCDIDDDMADisable(uint32_t ui32Base); +extern void LCDIDDCommandWrite(uint32_t ui32Base, uint32_t ui32CS, + uint16_t ui16Cmd); +extern void LCDIDDDataWrite(uint32_t ui32Base, uint32_t ui32CS, + uint16_t ui16Data); +extern void LCDIDDIndexedWrite(uint32_t ui32Base, uint32_t ui32CS, + uint16_t ui16Addr, uint16_t ui16Data); +extern uint16_t LCDIDDStatusRead(uint32_t ui32Base, uint32_t ui32CS); +extern uint16_t LCDIDDDataRead(uint32_t ui32Base, uint32_t ui32CS); +extern uint16_t LCDIDDIndexedRead(uint32_t ui32Base, uint32_t ui32CS, + uint16_t ui16Addr); +extern void LCDIDDDMAWrite(uint32_t ui32Base, uint32_t ui32CS, + const uint32_t *pui32Data, uint32_t ui32Count); +extern void LCDRasterConfigSet(uint32_t ui32Base, uint32_t ui32Config, + uint8_t ui8PalLoadDelay); +extern void LCDRasterTimingSet(uint32_t ui32Base, + const tLCDRasterTiming *pTiming); +extern void LCDRasterACBiasIntCountSet(uint32_t ui32Base, uint8_t ui8Count); +extern void LCDRasterEnable(uint32_t ui32Base); +extern bool LCDRasterEnabled(uint32_t ui32Base); +extern void LCDRasterDisable(uint32_t ui32Base); +extern void LCDRasterSubPanelConfigSet(uint32_t ui32Base, uint32_t ui32Flags, + uint32_t ui32BottomLines, + uint32_t ui32DefaultPixel); +extern void LCDRasterSubPanelEnable(uint32_t ui32Base); +extern void LCDRasterSubPanelDisable(uint32_t ui32Base); +extern void LCDDMAConfigSet(uint32_t ui32Base, uint32_t ui32Config); +extern void LCDRasterPaletteSet(uint32_t ui32Base, uint32_t ui32Type, + uint32_t *pui32PalAddr, + const uint32_t *pui32SrcColors, + uint32_t ui32Start, + uint32_t ui32Count); +extern void LCDRasterFrameBufferSet(uint32_t ui32Base, uint8_t ui8Buffer, + uint32_t *pui32Addr, + uint32_t ui32NumBytes); +extern void LCDIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void LCDIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern uint32_t LCDIntStatus(uint32_t ui32Base, bool bMasked); +extern void LCDIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void LCDIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); +extern void LCDIntUnregister(uint32_t ui32Base); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_LCD_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/mpu.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/mpu.h new file mode 100644 index 0000000000000000000000000000000000000000..9c8377f8cef7c7c9d32e5b4ad51753ec50164736 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/mpu.h @@ -0,0 +1,162 @@ +//***************************************************************************** +// +// mpu.h - Defines and Macros for the memory protection unit. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_MPU_H__ +#define __DRIVERLIB_MPU_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Flags that can be passed to MPUEnable. +// +//***************************************************************************** +#define MPU_CONFIG_PRIV_DEFAULT 4 +#define MPU_CONFIG_HARDFLT_NMI 2 +#define MPU_CONFIG_NONE 0 + +//***************************************************************************** +// +// Flags for the region size to be passed to MPURegionSet. +// +//***************************************************************************** +#define MPU_RGN_SIZE_32B (4 << 1) +#define MPU_RGN_SIZE_64B (5 << 1) +#define MPU_RGN_SIZE_128B (6 << 1) +#define MPU_RGN_SIZE_256B (7 << 1) +#define MPU_RGN_SIZE_512B (8 << 1) + +#define MPU_RGN_SIZE_1K (9 << 1) +#define MPU_RGN_SIZE_2K (10 << 1) +#define MPU_RGN_SIZE_4K (11 << 1) +#define MPU_RGN_SIZE_8K (12 << 1) +#define MPU_RGN_SIZE_16K (13 << 1) +#define MPU_RGN_SIZE_32K (14 << 1) +#define MPU_RGN_SIZE_64K (15 << 1) +#define MPU_RGN_SIZE_128K (16 << 1) +#define MPU_RGN_SIZE_256K (17 << 1) +#define MPU_RGN_SIZE_512K (18 << 1) + +#define MPU_RGN_SIZE_1M (19 << 1) +#define MPU_RGN_SIZE_2M (20 << 1) +#define MPU_RGN_SIZE_4M (21 << 1) +#define MPU_RGN_SIZE_8M (22 << 1) +#define MPU_RGN_SIZE_16M (23 << 1) +#define MPU_RGN_SIZE_32M (24 << 1) +#define MPU_RGN_SIZE_64M (25 << 1) +#define MPU_RGN_SIZE_128M (26 << 1) +#define MPU_RGN_SIZE_256M (27 << 1) +#define MPU_RGN_SIZE_512M (28 << 1) + +#define MPU_RGN_SIZE_1G (29 << 1) +#define MPU_RGN_SIZE_2G (30 << 1) +#define MPU_RGN_SIZE_4G (31 << 1) + +//***************************************************************************** +// +// Flags for the permissions to be passed to MPURegionSet. +// +//***************************************************************************** +#define MPU_RGN_PERM_EXEC 0x00000000 +#define MPU_RGN_PERM_NOEXEC 0x10000000 +#define MPU_RGN_PERM_PRV_NO_USR_NO 0x00000000 +#define MPU_RGN_PERM_PRV_RW_USR_NO 0x01000000 +#define MPU_RGN_PERM_PRV_RW_USR_RO 0x02000000 +#define MPU_RGN_PERM_PRV_RW_USR_RW 0x03000000 +#define MPU_RGN_PERM_PRV_RO_USR_NO 0x05000000 +#define MPU_RGN_PERM_PRV_RO_USR_RO 0x06000000 + +//***************************************************************************** +// +// Flags for the sub-region to be passed to MPURegionSet. +// +//***************************************************************************** +#define MPU_SUB_RGN_DISABLE_0 0x00000100 +#define MPU_SUB_RGN_DISABLE_1 0x00000200 +#define MPU_SUB_RGN_DISABLE_2 0x00000400 +#define MPU_SUB_RGN_DISABLE_3 0x00000800 +#define MPU_SUB_RGN_DISABLE_4 0x00001000 +#define MPU_SUB_RGN_DISABLE_5 0x00002000 +#define MPU_SUB_RGN_DISABLE_6 0x00004000 +#define MPU_SUB_RGN_DISABLE_7 0x00008000 + +//***************************************************************************** +// +// Flags to enable or disable a region, to be passed to MPURegionSet. +// +//***************************************************************************** +#define MPU_RGN_ENABLE 1 +#define MPU_RGN_DISABLE 0 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void MPUEnable(uint32_t ui32MPUConfig); +extern void MPUDisable(void); +extern uint32_t MPURegionCountGet(void); +extern void MPURegionEnable(uint32_t ui32Region); +extern void MPURegionDisable(uint32_t ui32Region); +extern void MPURegionSet(uint32_t ui32Region, uint32_t ui32Addr, + uint32_t ui32Flags); +extern void MPURegionGet(uint32_t ui32Region, uint32_t *pui32Addr, + uint32_t *pui32Flags); +extern void MPUIntRegister(void (*pfnHandler)(void)); +extern void MPUIntUnregister(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_MPU_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/onewire.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/onewire.h new file mode 100644 index 0000000000000000000000000000000000000000..731f3f99bbc21a51efe1418a7813a52b591410b7 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/onewire.h @@ -0,0 +1,307 @@ +//***************************************************************************** +// +// onewire.h - Prototypes for the OneWire Driver. +// +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_ONEWIRE_H__ +#define __DRIVERLIB_ONEWIRE_H__ + +//***************************************************************************** +// +//! \addtogroup onewire_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Defines used in the OneWireInit() function call. +// +//***************************************************************************** + +// +// This define is used in initialization to request standard speed bus +// timings. This is the default. +// +#define ONEWIRE_INIT_SPD_STD 0x00000000 + +// +// This define is used in initialization to request overdrive speed bus +// timings. +// +#define ONEWIRE_INIT_SPD_OD 0x00000020 + +// +// This define is used in initialization to request standard read sampling +// timing (2us for ONEWIRE_INIT_SPD_OD and 16us for ONEWIRE_INIT_SPD_STD). +// This is the default. +// +#define ONEWIRE_INIT_READ_STD 0x00000000 + +// +// This define is used in initialization to request late read sampling +// timing (7us for ONEWIRE_INIT_SPD_OD and 50us for ONEWIRE_INIT_SPD_STD). +// +#define ONEWIRE_INIT_READ_LATE 0x00000040 + +// +// This define is used in initialization to request a standard +// Answer-to-Reset (presence detect) monitor. This is the default. +// +#define ONEWIRE_INIT_ATR 0x00000000 + +// +// This define is used in initialization to request no Answer-to-Reset +// (presence detect) monitor. The module will delay operations after a bus +// reset for the expected presence detect period in this case. +// +#define ONEWIRE_INIT_NO_ATR 0x00000080 + +// +// This define is used in initialization to request standard signal polarity +// on the 1-Wire bus (pin is driven low to drive bus low). This is the +// default. +// +#define ONEWIRE_INIT_STD_POL 0x00000000 + +// +// This define is used in initialization to request alternate signal polarity +// on the 1-Wire bus (pin is driven high to drive bus low). +// +#define ONEWIRE_INIT_ALT_POL 0x40000000 + +// +// This define is used in initialization to request normal 1-Wire operational +// mode. This is the default. +// +#define ONEWIRE_INIT_1_WIRE_CFG 0x00000000 + +// +// This define is used in initialization to request a 2 pin operational +// mode where one pin is used exclusively for TX operations and the other +// for RX. +// +#define ONEWIRE_INIT_2_WIRE_CFG 0x80000000 + +//***************************************************************************** +// +// Defines for bus status conditions. These values can be returned by +// OneWireBusStatus(). +// +//***************************************************************************** + +// +// This will be set if the bus is busy handling a Read, Write or +// Reset activity. +// +#define ONEWIRE_BUS_STATUS_BUSY 0x00000100 + +// +// This will be set if the module did not detect any slave presence pulses +// after a bus reset. +// +#define ONEWIRE_BUS_STATUS_NO_SLAVE \ + 0x00000200 + +// +// This will be set if the bus is being held low outside of a normal Read, +// Write or Reset activity. +// +#define ONEWIRE_BUS_STATUS_STUCK \ + 0x00000400 + +//***************************************************************************** +// +// OneWire operation modes used with OneWireTransaction(). +// +//***************************************************************************** + +// +// This mode flag indicates a single reset should be issued prior to a write +// and/or read operation. +// +#define ONEWIRE_OP_RESET 0x00000001 + +// +// This mode flag indicates a read operation. +// +#define ONEWIRE_OP_READ 0x00000002 + +// +// This mode flag indicates a write operation. +// +#define ONEWIRE_OP_WRITE 0x00000004 + +//***************************************************************************** +// +// OneWire DMA used with OneWireDMAEnable(). +// +//***************************************************************************** + +// +// This indicates the DMA should issue a 1-Wire bus reset before starting. +// +#define ONEWIRE_DMA_BUS_RESET 0x00000001 + +// +// The DMA operation will be a single Read after each module transaction. +// +#define ONEWIRE_DMA_OP_READ 0x00000002 + +// +// The DMA will write values to the 1-Wire interface as each previous DMA +// write operation completes. +// +#define ONEWIRE_DMA_OP_MULTI_WRITE \ + 0x00000004 + +// +// The DMA will read values from the 1-Wire interface as each previous DMA +// read operation completes. +// +#define ONEWIRE_DMA_OP_MULTI_READ \ + 0x00000006 + +// +// This Scatter Gather DMA mode is paired with ONEWIRE_DMA_OP_READ to instruct +// the 1-Wire DMA to initiate an operation at the start of and then on each +// transition completion thereafter. +// +#define ONEWIRE_DMA_MODE_SG 0x00000008 + +// +// DMA expects a Read/Write bus operation size of 8 bits. This should match +// the uDMA channel setup. +// +#define ONEWIRE_DMA_OP_SZ_8 0x00000000 + +// +// DMA expects a Read/Write bus operation size of 16 bits. This should match +// the uDMA channel setup. +// +#define ONEWIRE_DMA_OP_SZ_16 0x00000800 + +// +// DMA expects a Read/Write bus operation size of 32 bits. This should match +// the uDMA channel setup. +// +#define ONEWIRE_DMA_OP_SZ_32 0x00001800 + +//***************************************************************************** +// +// OneWire interrupt defines. Use in calls to OneWireIntEnable(), +// OneWireIntDisable(), OneWireIntClear() and returned by OneWireIntStatus(). +// +//***************************************************************************** + +// +// This interrupt indicates a bus reset has just completed. +// +#define ONEWIRE_INT_RESET_DONE 0x00000001 + +// +// The interrupt indicates a Read or Write master initiated operation +// has just completed. +// +#define ONEWIRE_INT_OP_DONE 0x00000002 + +// +// This interrupt indicates that no presence detect was signaled by a slave +// on the bus after a reset. +// +#define ONEWIRE_INT_NO_SLAVE 0x00000004 + +// +// This interrupt indicates the bus is being held low outside of normal +// operations. +// +#define ONEWIRE_INT_STUCK 0x00000008 + +// +// This interrupt indicates a OneWire DMA operation has completed. +// +#define ONEWIRE_INT_DMA_DONE 0x00000010 + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void OneWireBusReset(uint32_t ui32Base); +extern uint32_t OneWireBusStatus(uint32_t ui32Base); +extern void OneWireDataGet(uint32_t u3i2Base, uint32_t *pui32Data); +extern bool OneWireDataGetNonBlocking(uint32_t ui32Base, uint32_t *pui32Data); +extern void OneWireDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags); +extern void OneWireDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags); +extern void OneWireInit(uint32_t ui32Base, uint32_t ui32InitFlags); +extern void OneWireIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void OneWireIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void OneWireIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void OneWireIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); +extern void OneWireIntUnregister(uint32_t ui32Base); +extern uint32_t OneWireIntStatus(uint32_t ui32Base, bool bMasked); +extern void OneWireTransaction(uint32_t ui32Base, uint32_t ui32OpFlags, + uint32_t ui32Data, uint32_t ui32BitCnt); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_ONEWIRE_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/pin_map.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/pin_map.h new file mode 100644 index 0000000000000000000000000000000000000000..9d686098616d980c55f9614161868bc3ef7e6a2b --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/pin_map.h @@ -0,0 +1,20953 @@ +//***************************************************************************** +// +// pin_map.h - Mapping of peripherals to pins for all parts. +// +// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_PIN_MAP_H__ +#define __DRIVERLIB_PIN_MAP_H__ + +//***************************************************************************** +// +// TM4C1230C3PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1230C3PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_TM4C1230C3PM + +//***************************************************************************** +// +// TM4C1230D5PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1230D5PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_TM4C1230D5PM + +//***************************************************************************** +// +// TM4C1230E6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1230E6PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_TM4C1230E6PM + +//***************************************************************************** +// +// TM4C1230H6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1230H6PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_TM4C1230H6PM + +//***************************************************************************** +// +// TM4C1231C3PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1231C3PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_TM4C1231C3PM + +//***************************************************************************** +// +// TM4C1231D5PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1231D5PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_TM4C1231D5PM + +//***************************************************************************** +// +// TM4C1231D5PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1231D5PZ + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_TM4C1231D5PZ + +//***************************************************************************** +// +// TM4C1231E6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1231E6PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_TM4C1231E6PM + +//***************************************************************************** +// +// TM4C1231E6PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1231E6PZ + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_TM4C1231E6PZ + +//***************************************************************************** +// +// TM4C1231H6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1231H6PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_TM4C1231H6PM + +//***************************************************************************** +// +// TM4C1231H6PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1231H6PZ + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_TM4C1231H6PZ + +//***************************************************************************** +// +// TM4C1232C3PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1232C3PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_TM4C1232C3PM + +//***************************************************************************** +// +// TM4C1232D5PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1232D5PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_TM4C1232D5PM + +//***************************************************************************** +// +// TM4C1232E6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1232E6PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_TM4C1232E6PM + +//***************************************************************************** +// +// TM4C1232H6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1232H6PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_TM4C1232H6PM + +//***************************************************************************** +// +// TM4C1233C3PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1233C3PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_TM4C1233C3PM + +//***************************************************************************** +// +// TM4C1233D5PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1233D5PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_TM4C1233D5PM + +//***************************************************************************** +// +// TM4C1233D5PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1233D5PZ + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_TM4C1233D5PZ + +//***************************************************************************** +// +// TM4C1233E6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1233E6PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_TM4C1233E6PM + +//***************************************************************************** +// +// TM4C1233E6PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1233E6PZ + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_TM4C1233E6PZ + +//***************************************************************************** +// +// TM4C1233H6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1233H6PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_TM4C1233H6PM + +//***************************************************************************** +// +// TM4C1233H6PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1233H6PZ + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_TM4C1233H6PZ + +//***************************************************************************** +// +// TM4C1236D5PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1236D5PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#endif // PART_TM4C1236D5PM + +//***************************************************************************** +// +// TM4C1236E6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1236E6PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#endif // PART_TM4C1236E6PM + +//***************************************************************************** +// +// TM4C1236H6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1236H6PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#endif // PART_TM4C1236H6PM + +//***************************************************************************** +// +// TM4C1237D5PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1237D5PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#endif // PART_TM4C1237D5PM + +//***************************************************************************** +// +// TM4C1237D5PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1237D5PZ + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_TM4C1237D5PZ + +//***************************************************************************** +// +// TM4C1237E6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1237E6PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#endif // PART_TM4C1237E6PM + +//***************************************************************************** +// +// TM4C1237E6PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1237E6PZ + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_TM4C1237E6PZ + +//***************************************************************************** +// +// TM4C1237H6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1237H6PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#endif // PART_TM4C1237H6PM + +//***************************************************************************** +// +// TM4C1237H6PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1237H6PZ + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_TM4C1237H6PZ + +//***************************************************************************** +// +// TM4C123AE6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123AE6PM + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_TM4C123AE6PM + +//***************************************************************************** +// +// TM4C123AH6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123AH6PM + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_TM4C123AH6PM + +//***************************************************************************** +// +// TM4C123BE6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123BE6PM + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_TM4C123BE6PM + +//***************************************************************************** +// +// TM4C123BE6PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123BE6PZ + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#endif // PART_TM4C123BE6PZ + +//***************************************************************************** +// +// TM4C123BH6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123BH6PM + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_TM4C123BH6PM + +//***************************************************************************** +// +// TM4C123BH6PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123BH6PZ + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#endif // PART_TM4C123BH6PZ + +//***************************************************************************** +// +// TM4C123FE6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123FE6PM + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#endif // PART_TM4C123FE6PM + +//***************************************************************************** +// +// TM4C123FH6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123FH6PM + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#endif // PART_TM4C123FH6PM + +//***************************************************************************** +// +// TM4C123GE6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123GE6PM + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#endif // PART_TM4C123GE6PM + +//***************************************************************************** +// +// TM4C123GE6PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123GE6PZ + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#endif // PART_TM4C123GE6PZ + +//***************************************************************************** +// +// TM4C123GH6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123GH6PM + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#endif // PART_TM4C123GH6PM + +//***************************************************************************** +// +// TM4C123GH6PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123GH6PZ + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#endif // PART_TM4C123GH6PZ + +//***************************************************************************** +// +// TM4C1231H6PGE Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1231H6PGE + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_T5CCP0 0x000D0807 + +#endif // PART_TM4C1231H6PGE + +//***************************************************************************** +// +// TM4C1233H6PGE Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1233H6PGE + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_T5CCP0 0x000D0807 + +#endif // PART_TM4C1233H6PGE + +//***************************************************************************** +// +// TM4C1237H6PGE Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1237H6PGE + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_T5CCP0 0x000D0807 + +#endif // PART_TM4C1237H6PGE + +//***************************************************************************** +// +// TM4C123BH6PGE Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123BH6PGE + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_M0FAULT0 0x00091006 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_M0FAULT1 0x00091406 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_M0FAULT2 0x00091806 +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_M0FAULT3 0x00091C06 +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM6_M0PWM4 0x000B1802 +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_M0PWM5 0x000B1C02 +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_M0PWM6 0x000C0802 +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_M0PWM7 0x000C0C02 +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_M1PWM4 0x000C1002 +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_M1PWM5 0x000C1402 +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_M1PWM6 0x000C1802 +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_M1PWM7 0x000C1C02 +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_M0PWM0 0x000D0001 +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_M0PWM1 0x000D0401 +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_M0PWM2 0x000D0801 +#define GPIO_PP2_T5CCP0 0x000D0807 + +#endif // PART_TM4C123BH6PGE + +//***************************************************************************** +// +// TM4C123BH6ZRB Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123BH6ZRB + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_M0FAULT0 0x00091006 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_M0FAULT1 0x00091406 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_M0FAULT2 0x00091806 +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_M0FAULT3 0x00091C06 +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM6_M0PWM4 0x000B1802 +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_M0PWM5 0x000B1C02 +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_M0PWM6 0x000C0802 +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_M0PWM7 0x000C0C02 +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_M1PWM4 0x000C1002 +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_M1PWM5 0x000C1402 +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_M1PWM6 0x000C1802 +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_M1PWM7 0x000C1C02 +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_M0PWM0 0x000D0001 +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_M0PWM1 0x000D0401 +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_M0PWM2 0x000D0801 +#define GPIO_PP2_T5CCP0 0x000D0807 + +#define GPIO_PP3_M0PWM3 0x000D0C01 +#define GPIO_PP3_T5CCP1 0x000D0C07 + +#define GPIO_PP4_M0PWM4 0x000D1001 +#define GPIO_PP4_WT0CCP0 0x000D1007 + +#define GPIO_PP5_M0PWM5 0x000D1401 +#define GPIO_PP5_WT0CCP1 0x000D1407 + +#define GPIO_PP6_M0PWM6 0x000D1801 +#define GPIO_PP6_WT1CCP0 0x000D1807 + +#define GPIO_PP7_M0PWM7 0x000D1C01 +#define GPIO_PP7_WT1CCP1 0x000D1C07 + +#define GPIO_PQ0_M1PWM0 0x000E0001 +#define GPIO_PQ0_WT2CCP0 0x000E0007 + +#define GPIO_PQ1_M1PWM1 0x000E0401 +#define GPIO_PQ1_WT2CCP1 0x000E0407 + +#define GPIO_PQ2_M1PWM2 0x000E0801 +#define GPIO_PQ2_WT3CCP0 0x000E0807 + +#define GPIO_PQ3_M1PWM3 0x000E0C01 +#define GPIO_PQ3_WT3CCP1 0x000E0C07 + +#define GPIO_PQ4_M1PWM4 0x000E1001 +#define GPIO_PQ4_WT4CCP0 0x000E1007 + +#define GPIO_PQ5_M1PWM5 0x000E1401 +#define GPIO_PQ5_WT4CCP1 0x000E1407 + +#define GPIO_PQ6_M1PWM6 0x000E1801 +#define GPIO_PQ6_WT5CCP0 0x000E1807 + +#define GPIO_PQ7_M1PWM7 0x000E1C01 +#define GPIO_PQ7_WT5CCP1 0x000E1C07 + +#endif // PART_TM4C123BH6ZRB + +//***************************************************************************** +// +// TM4C123GH6PGE Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123GH6PGE + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_M0FAULT0 0x00091006 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_M0FAULT1 0x00091406 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_M0FAULT2 0x00091806 +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_M0FAULT3 0x00091C06 +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM6_M0PWM4 0x000B1802 +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_M0PWM5 0x000B1C02 +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_M0PWM6 0x000C0802 +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_M0PWM7 0x000C0C02 +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_M1PWM4 0x000C1002 +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_M1PWM5 0x000C1402 +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_M1PWM6 0x000C1802 +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_M1PWM7 0x000C1C02 +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_M0PWM0 0x000D0001 +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_M0PWM1 0x000D0401 +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_M0PWM2 0x000D0801 +#define GPIO_PP2_T5CCP0 0x000D0807 + +#endif // PART_TM4C123GH6PGE + +//***************************************************************************** +// +// TM4C123GH6ZRB Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123GH6ZRB + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_M0FAULT0 0x00091006 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_M0FAULT1 0x00091406 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_M0FAULT2 0x00091806 +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_M0FAULT3 0x00091C06 +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM6_M0PWM4 0x000B1802 +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_M0PWM5 0x000B1C02 +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_M0PWM6 0x000C0802 +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_M0PWM7 0x000C0C02 +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_M1PWM4 0x000C1002 +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_M1PWM5 0x000C1402 +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_M1PWM6 0x000C1802 +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_M1PWM7 0x000C1C02 +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_M0PWM0 0x000D0001 +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_M0PWM1 0x000D0401 +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_M0PWM2 0x000D0801 +#define GPIO_PP2_T5CCP0 0x000D0807 + +#define GPIO_PP3_M0PWM3 0x000D0C01 +#define GPIO_PP3_T5CCP1 0x000D0C07 + +#define GPIO_PP4_M0PWM4 0x000D1001 +#define GPIO_PP4_WT0CCP0 0x000D1007 + +#define GPIO_PP5_M0PWM5 0x000D1401 +#define GPIO_PP5_WT0CCP1 0x000D1407 + +#define GPIO_PP6_M0PWM6 0x000D1801 +#define GPIO_PP6_WT1CCP0 0x000D1807 + +#define GPIO_PP7_M0PWM7 0x000D1C01 +#define GPIO_PP7_WT1CCP1 0x000D1C07 + +#define GPIO_PQ0_M1PWM0 0x000E0001 +#define GPIO_PQ0_WT2CCP0 0x000E0007 + +#define GPIO_PQ1_M1PWM1 0x000E0401 +#define GPIO_PQ1_WT2CCP1 0x000E0407 + +#define GPIO_PQ2_M1PWM2 0x000E0801 +#define GPIO_PQ2_WT3CCP0 0x000E0807 + +#define GPIO_PQ3_M1PWM3 0x000E0C01 +#define GPIO_PQ3_WT3CCP1 0x000E0C07 + +#define GPIO_PQ4_M1PWM4 0x000E1001 +#define GPIO_PQ4_WT4CCP0 0x000E1007 + +#define GPIO_PQ5_M1PWM5 0x000E1401 +#define GPIO_PQ5_WT4CCP1 0x000E1407 + +#define GPIO_PQ6_M1PWM6 0x000E1801 +#define GPIO_PQ6_WT5CCP0 0x000E1807 + +#define GPIO_PQ7_M1PWM7 0x000E1C01 +#define GPIO_PQ7_WT5CCP1 0x000E1C07 + +#endif // PART_TM4C123GH6ZRB + +//***************************************************************************** +// +// TM4C123GH6ZXR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123GH6ZXR + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_M0FAULT0 0x00091006 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_M0FAULT1 0x00091406 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_M0FAULT2 0x00091806 +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_M0FAULT3 0x00091C06 +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM6_M0PWM4 0x000B1802 +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_M0PWM5 0x000B1C02 +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_M0PWM6 0x000C0802 +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_M0PWM7 0x000C0C02 +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_M1PWM4 0x000C1002 +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_M1PWM5 0x000C1402 +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_M1PWM6 0x000C1802 +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_M1PWM7 0x000C1C02 +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_M0PWM0 0x000D0001 +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_M0PWM1 0x000D0401 +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_M0PWM2 0x000D0801 +#define GPIO_PP2_T5CCP0 0x000D0807 + +#define GPIO_PP3_M0PWM3 0x000D0C01 +#define GPIO_PP3_T5CCP1 0x000D0C07 + +#define GPIO_PP4_M0PWM4 0x000D1001 +#define GPIO_PP4_WT0CCP0 0x000D1007 + +#define GPIO_PP5_M0PWM5 0x000D1401 +#define GPIO_PP5_WT0CCP1 0x000D1407 + +#define GPIO_PP6_M0PWM6 0x000D1801 +#define GPIO_PP6_WT1CCP0 0x000D1807 + +#define GPIO_PP7_M0PWM7 0x000D1C01 +#define GPIO_PP7_WT1CCP1 0x000D1C07 + +#define GPIO_PQ0_M1PWM0 0x000E0001 +#define GPIO_PQ0_WT2CCP0 0x000E0007 + +#define GPIO_PQ1_M1PWM1 0x000E0401 +#define GPIO_PQ1_WT2CCP1 0x000E0407 + +#define GPIO_PQ2_M1PWM2 0x000E0801 +#define GPIO_PQ2_WT3CCP0 0x000E0807 + +#define GPIO_PQ3_M1PWM3 0x000E0C01 +#define GPIO_PQ3_WT3CCP1 0x000E0C07 + +#define GPIO_PQ4_M1PWM4 0x000E1001 +#define GPIO_PQ4_WT4CCP0 0x000E1007 + +#define GPIO_PQ5_M1PWM5 0x000E1401 +#define GPIO_PQ5_WT4CCP1 0x000E1407 + +#define GPIO_PQ6_M1PWM6 0x000E1801 +#define GPIO_PQ6_WT5CCP0 0x000E1807 + +#define GPIO_PQ7_M1PWM7 0x000E1C01 +#define GPIO_PQ7_WT5CCP1 0x000E1C07 + +#endif // PART_TM4C123GH6ZXR + +//***************************************************************************** +// +// TM4C1290NCPDT Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1290NCPDT + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PJ0_U3RX 0x00080001 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 + +#define GPIO_PQ6_U1DTR 0x000E1801 + +#endif // PART_TM4C1290NCPDT + +//***************************************************************************** +// +// TM4C1290NCZAD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1290NCZAD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PB6_I2C6SCL 0x00011802 +#define GPIO_PB6_T6CCP0 0x00011803 + +#define GPIO_PB7_I2C6SDA 0x00011C02 +#define GPIO_PB7_T6CCP1 0x00011C03 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_T7CCP0 0x00021003 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_T7CCP1 0x00021403 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PE6_U0CTS 0x00041801 +#define GPIO_PE6_I2C9SCL 0x00041802 + +#define GPIO_PE7_U0RTS 0x00041C01 +#define GPIO_PE7_I2C9SDA 0x00041C02 +#define GPIO_PE7_NMI 0x00041C08 + +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PF5_SSI3XDAT3 0x0005140E + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PH4_U0DTR 0x00071001 + +#define GPIO_PH5_U0RI 0x00071401 + +#define GPIO_PH6_U5RX 0x00071801 +#define GPIO_PH6_U7RX 0x00071802 + +#define GPIO_PH7_U5TX 0x00071C01 +#define GPIO_PH7_U7TX 0x00071C02 + +#define GPIO_PJ0_U3RX 0x00080001 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PJ2_U2RTS 0x00080801 + +#define GPIO_PJ3_U2CTS 0x00080C01 + +#define GPIO_PJ4_U3RTS 0x00081001 + +#define GPIO_PJ5_U3CTS 0x00081401 + +#define GPIO_PJ6_U4RTS 0x00081801 + +#define GPIO_PJ7_U4CTS 0x00081C01 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PN6_U4RTS 0x000C1802 + +#define GPIO_PN7_U1RTS 0x000C1C01 +#define GPIO_PN7_U4CTS 0x000C1C02 + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_T6CCP0 0x000D0005 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_T6CCP1 0x000D0405 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PP6_U1DCD 0x000D1801 +#define GPIO_PP6_I2C2SDA 0x000D1802 + +#define GPIO_PQ0_T6CCP0 0x000E0003 +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_T6CCP1 0x000E0403 +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_T7CCP0 0x000E0803 +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_T7CCP1 0x000E0C03 +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 + +#define GPIO_PQ6_U1DTR 0x000E1801 + +#define GPIO_PQ7_U1RI 0x000E1C01 + +#define GPIO_PR0_U4TX 0x000F0001 +#define GPIO_PR0_I2C1SCL 0x000F0002 +#define GPIO_PR0_M0PWM0 0x000F0006 + +#define GPIO_PR1_U4RX 0x000F0401 +#define GPIO_PR1_I2C1SDA 0x000F0402 +#define GPIO_PR1_M0PWM1 0x000F0406 + +#define GPIO_PR2_I2C2SCL 0x000F0802 +#define GPIO_PR2_M0PWM2 0x000F0806 + +#define GPIO_PR3_I2C2SDA 0x000F0C02 +#define GPIO_PR3_M0PWM3 0x000F0C06 + +#define GPIO_PR4_I2C3SCL 0x000F1002 +#define GPIO_PR4_T0CCP0 0x000F1003 +#define GPIO_PR4_M0PWM4 0x000F1006 + +#define GPIO_PR5_U1RX 0x000F1401 +#define GPIO_PR5_I2C3SDA 0x000F1402 +#define GPIO_PR5_T0CCP1 0x000F1403 +#define GPIO_PR5_M0PWM5 0x000F1406 + +#define GPIO_PR6_U1TX 0x000F1801 +#define GPIO_PR6_I2C4SCL 0x000F1802 +#define GPIO_PR6_T1CCP0 0x000F1803 +#define GPIO_PR6_M0PWM6 0x000F1806 + +#define GPIO_PR7_I2C4SDA 0x000F1C02 +#define GPIO_PR7_T1CCP1 0x000F1C03 +#define GPIO_PR7_M0PWM7 0x000F1C06 + +#define GPIO_PS0_T2CCP0 0x00100003 +#define GPIO_PS0_M0FAULT0 0x00100006 + +#define GPIO_PS1_T2CCP1 0x00100403 +#define GPIO_PS1_M0FAULT1 0x00100406 + +#define GPIO_PS2_U1DSR 0x00100801 +#define GPIO_PS2_T3CCP0 0x00100803 +#define GPIO_PS2_M0FAULT2 0x00100806 + +#define GPIO_PS3_T3CCP1 0x00100C03 +#define GPIO_PS3_M0FAULT3 0x00100C06 + +#define GPIO_PS4_T4CCP0 0x00101003 +#define GPIO_PS4_PHA0 0x00101006 + +#define GPIO_PS5_T4CCP1 0x00101403 +#define GPIO_PS5_PHB0 0x00101406 + +#define GPIO_PS6_T5CCP0 0x00101803 +#define GPIO_PS6_IDX0 0x00101806 + +#define GPIO_PS7_T5CCP1 0x00101C03 + +#define GPIO_PT0_T6CCP0 0x00110003 +#define GPIO_PT0_CAN0RX 0x00110007 + +#define GPIO_PT1_T6CCP1 0x00110403 +#define GPIO_PT1_CAN0TX 0x00110407 + +#define GPIO_PT2_T7CCP0 0x00110803 +#define GPIO_PT2_CAN1RX 0x00110807 + +#define GPIO_PT3_T7CCP1 0x00110C03 +#define GPIO_PT3_CAN1TX 0x00110C07 + +#endif // PART_TM4C1290NCZAD + +//***************************************************************************** +// +// TM4C1292NCPDT Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1292NCPDT + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EN0RXCK 0x0000180E +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_EN0MDC 0x00010805 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_EN0MDIO 0x00010C05 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_EN0MDC 0x00050805 +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_EN0MDIO 0x00050C05 +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_EN0TXCK 0x0006080E +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_EN0TXEN 0x00060C0E +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_EN0TXD0 0x0006100E +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_EN0TXD1 0x0006140E +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_EN0RXER 0x0006180E +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_EN0RXDV 0x00061C0E +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PJ0_U3RX 0x00080001 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EN0INTRN 0x00091007 +#define GPIO_PK4_EN0RXD3 0x0009100E +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EN0RXD2 0x0009140E +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EN0TXD2 0x0009180E +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EN0TXD3 0x00091C0E +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 +#define GPIO_PM4_EN0RREF_CLK 0x000B100E + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 +#define GPIO_PM6_EN0CRS 0x000B180E + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 +#define GPIO_PM7_EN0COL 0x000B1C0E + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_EN0INTRN 0x000D0007 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 +#define GPIO_PQ5_EN0RXD0 0x000E140E + +#define GPIO_PQ6_U1DTR 0x000E1801 +#define GPIO_PQ6_EN0RXD1 0x000E180E + +#endif // PART_TM4C1292NCPDT + +//***************************************************************************** +// +// TM4C1292NCZAD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1292NCZAD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EN0RXCK 0x0000180E +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_EN0MDC 0x00010805 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_EN0MDIO 0x00010C05 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PB6_I2C6SCL 0x00011802 +#define GPIO_PB6_T6CCP0 0x00011803 + +#define GPIO_PB7_I2C6SDA 0x00011C02 +#define GPIO_PB7_T6CCP1 0x00011C03 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_T7CCP0 0x00021003 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_T7CCP1 0x00021403 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PE6_U0CTS 0x00041801 +#define GPIO_PE6_I2C9SCL 0x00041802 + +#define GPIO_PE7_U0RTS 0x00041C01 +#define GPIO_PE7_I2C9SDA 0x00041C02 +#define GPIO_PE7_NMI 0x00041C08 + +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_EN0MDC 0x00050805 +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_EN0MDIO 0x00050C05 +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PF5_SSI3XDAT3 0x0005140E + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_EN0TXCK 0x0006080E +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_EN0TXEN 0x00060C0E +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_EN0TXD0 0x0006100E +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_EN0TXD1 0x0006140E +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_EN0RXER 0x0006180E +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_EN0RXDV 0x00061C0E +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PH4_U0DTR 0x00071001 + +#define GPIO_PH5_U0RI 0x00071401 + +#define GPIO_PH6_U5RX 0x00071801 +#define GPIO_PH6_U7RX 0x00071802 + +#define GPIO_PH7_U5TX 0x00071C01 +#define GPIO_PH7_U7TX 0x00071C02 + +#define GPIO_PJ0_U3RX 0x00080001 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PJ2_U2RTS 0x00080801 + +#define GPIO_PJ3_U2CTS 0x00080C01 + +#define GPIO_PJ4_U3RTS 0x00081001 + +#define GPIO_PJ5_U3CTS 0x00081401 + +#define GPIO_PJ6_U4RTS 0x00081801 + +#define GPIO_PJ7_U4CTS 0x00081C01 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EN0INTRN 0x00091007 +#define GPIO_PK4_EN0RXD3 0x0009100E +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EN0RXD2 0x0009140E +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EN0TXD2 0x0009180E +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EN0TXD3 0x00091C0E +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 +#define GPIO_PM4_EN0RREF_CLK 0x000B100E + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 +#define GPIO_PM6_EN0CRS 0x000B180E + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 +#define GPIO_PM7_EN0COL 0x000B1C0E + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PN6_U4RTS 0x000C1802 +#define GPIO_PN6_EN0TXER 0x000C180E + +#define GPIO_PN7_U1RTS 0x000C1C01 +#define GPIO_PN7_U4CTS 0x000C1C02 + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_T6CCP0 0x000D0005 +#define GPIO_PP0_EN0INTRN 0x000D0007 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_T6CCP1 0x000D0405 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PP6_U1DCD 0x000D1801 +#define GPIO_PP6_I2C2SDA 0x000D1802 + +#define GPIO_PQ0_T6CCP0 0x000E0003 +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_T6CCP1 0x000E0403 +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_T7CCP0 0x000E0803 +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_T7CCP1 0x000E0C03 +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 +#define GPIO_PQ5_EN0RXD0 0x000E140E + +#define GPIO_PQ6_U1DTR 0x000E1801 +#define GPIO_PQ6_EN0RXD1 0x000E180E + +#define GPIO_PQ7_U1RI 0x000E1C01 + +#define GPIO_PR0_U4TX 0x000F0001 +#define GPIO_PR0_I2C1SCL 0x000F0002 +#define GPIO_PR0_M0PWM0 0x000F0006 + +#define GPIO_PR1_U4RX 0x000F0401 +#define GPIO_PR1_I2C1SDA 0x000F0402 +#define GPIO_PR1_M0PWM1 0x000F0406 + +#define GPIO_PR2_I2C2SCL 0x000F0802 +#define GPIO_PR2_M0PWM2 0x000F0806 + +#define GPIO_PR3_I2C2SDA 0x000F0C02 +#define GPIO_PR3_M0PWM3 0x000F0C06 + +#define GPIO_PR4_I2C3SCL 0x000F1002 +#define GPIO_PR4_T0CCP0 0x000F1003 +#define GPIO_PR4_M0PWM4 0x000F1006 + +#define GPIO_PR5_U1RX 0x000F1401 +#define GPIO_PR5_I2C3SDA 0x000F1402 +#define GPIO_PR5_T0CCP1 0x000F1403 +#define GPIO_PR5_M0PWM5 0x000F1406 + +#define GPIO_PR6_U1TX 0x000F1801 +#define GPIO_PR6_I2C4SCL 0x000F1802 +#define GPIO_PR6_T1CCP0 0x000F1803 +#define GPIO_PR6_M0PWM6 0x000F1806 + +#define GPIO_PR7_I2C4SDA 0x000F1C02 +#define GPIO_PR7_T1CCP1 0x000F1C03 +#define GPIO_PR7_M0PWM7 0x000F1C06 +#define GPIO_PR7_EN0TXEN 0x000F1C0E + +#define GPIO_PS0_T2CCP0 0x00100003 +#define GPIO_PS0_M0FAULT0 0x00100006 + +#define GPIO_PS1_T2CCP1 0x00100403 +#define GPIO_PS1_M0FAULT1 0x00100406 + +#define GPIO_PS2_U1DSR 0x00100801 +#define GPIO_PS2_T3CCP0 0x00100803 +#define GPIO_PS2_M0FAULT2 0x00100806 + +#define GPIO_PS3_T3CCP1 0x00100C03 +#define GPIO_PS3_M0FAULT3 0x00100C06 + +#define GPIO_PS4_T4CCP0 0x00101003 +#define GPIO_PS4_PHA0 0x00101006 +#define GPIO_PS4_EN0TXD0 0x0010100E + +#define GPIO_PS5_T4CCP1 0x00101403 +#define GPIO_PS5_PHB0 0x00101406 +#define GPIO_PS5_EN0TXD1 0x0010140E + +#define GPIO_PS6_T5CCP0 0x00101803 +#define GPIO_PS6_IDX0 0x00101806 +#define GPIO_PS6_EN0RXER 0x0010180E + +#define GPIO_PS7_T5CCP1 0x00101C03 +#define GPIO_PS7_EN0RXDV 0x00101C0E + +#define GPIO_PT0_T6CCP0 0x00110003 +#define GPIO_PT0_CAN0RX 0x00110007 +#define GPIO_PT0_EN0RXD0 0x0011000E + +#define GPIO_PT1_T6CCP1 0x00110403 +#define GPIO_PT1_CAN0TX 0x00110407 +#define GPIO_PT1_EN0RXD1 0x0011040E + +#define GPIO_PT2_T7CCP0 0x00110803 +#define GPIO_PT2_CAN1RX 0x00110807 + +#define GPIO_PT3_T7CCP1 0x00110C03 +#define GPIO_PT3_CAN1TX 0x00110C07 + +#endif // PART_TM4C1292NCZAD + +//***************************************************************************** +// +// TM4C1294KCPDT Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1294KCPDT + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PF0_EN0LED0 0x00050005 +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_EN0LED2 0x00050405 +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_EN0LED1 0x00051005 +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_EN0PPS 0x00060005 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PJ0_U3RX 0x00080001 +#define GPIO_PJ0_EN0PPS 0x00080005 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_EN0LED0 0x00091005 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_EN0LED2 0x00091405 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_EN0LED1 0x00091805 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#endif // PART_TM4C1294KCPDT + +//***************************************************************************** +// +// TM4C1294NCPDT Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1294NCPDT + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PF0_EN0LED0 0x00050005 +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_EN0LED2 0x00050405 +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_EN0LED1 0x00051005 +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_EN0PPS 0x00060005 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PJ0_U3RX 0x00080001 +#define GPIO_PJ0_EN0PPS 0x00080005 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_EN0LED0 0x00091005 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_EN0LED2 0x00091405 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_EN0LED1 0x00091805 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#endif // PART_TM4C1294NCPDT + +//***************************************************************************** +// +// TM4C1294NCZAD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1294NCZAD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PB6_I2C6SCL 0x00011802 +#define GPIO_PB6_T6CCP0 0x00011803 + +#define GPIO_PB7_I2C6SDA 0x00011C02 +#define GPIO_PB7_T6CCP1 0x00011C03 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_T7CCP0 0x00021003 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_T7CCP1 0x00021403 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PE6_U0CTS 0x00041801 +#define GPIO_PE6_I2C9SCL 0x00041802 + +#define GPIO_PE7_U0RTS 0x00041C01 +#define GPIO_PE7_I2C9SDA 0x00041C02 +#define GPIO_PE7_NMI 0x00041C08 + +#define GPIO_PF0_EN0LED0 0x00050005 +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_EN0LED2 0x00050405 +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_EN0LED1 0x00051005 +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PF5_SSI3XDAT3 0x0005140E + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_EN0PPS 0x00060005 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PH4_U0DTR 0x00071001 + +#define GPIO_PH5_U0RI 0x00071401 +#define GPIO_PH5_EN0PPS 0x00071405 + +#define GPIO_PH6_U5RX 0x00071801 +#define GPIO_PH6_U7RX 0x00071802 + +#define GPIO_PH7_U5TX 0x00071C01 +#define GPIO_PH7_U7TX 0x00071C02 + +#define GPIO_PJ0_U3RX 0x00080001 +#define GPIO_PJ0_EN0PPS 0x00080005 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PJ2_U2RTS 0x00080801 + +#define GPIO_PJ3_U2CTS 0x00080C01 + +#define GPIO_PJ4_U3RTS 0x00081001 + +#define GPIO_PJ5_U3CTS 0x00081401 + +#define GPIO_PJ6_U4RTS 0x00081801 + +#define GPIO_PJ7_U4CTS 0x00081C01 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_EN0LED0 0x00091005 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_EN0LED2 0x00091405 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_EN0LED1 0x00091805 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PN6_U4RTS 0x000C1802 + +#define GPIO_PN7_U1RTS 0x000C1C01 +#define GPIO_PN7_U4CTS 0x000C1C02 + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_T6CCP0 0x000D0005 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_T6CCP1 0x000D0405 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PP6_U1DCD 0x000D1801 +#define GPIO_PP6_I2C2SDA 0x000D1802 + +#define GPIO_PQ0_T6CCP0 0x000E0003 +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_T6CCP1 0x000E0403 +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_T7CCP0 0x000E0803 +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_T7CCP1 0x000E0C03 +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 + +#define GPIO_PQ6_U1DTR 0x000E1801 + +#define GPIO_PQ7_U1RI 0x000E1C01 + +#define GPIO_PR0_U4TX 0x000F0001 +#define GPIO_PR0_I2C1SCL 0x000F0002 +#define GPIO_PR0_M0PWM0 0x000F0006 + +#define GPIO_PR1_U4RX 0x000F0401 +#define GPIO_PR1_I2C1SDA 0x000F0402 +#define GPIO_PR1_M0PWM1 0x000F0406 + +#define GPIO_PR2_I2C2SCL 0x000F0802 +#define GPIO_PR2_M0PWM2 0x000F0806 + +#define GPIO_PR3_I2C2SDA 0x000F0C02 +#define GPIO_PR3_M0PWM3 0x000F0C06 + +#define GPIO_PR4_I2C3SCL 0x000F1002 +#define GPIO_PR4_T0CCP0 0x000F1003 +#define GPIO_PR4_M0PWM4 0x000F1006 + +#define GPIO_PR5_U1RX 0x000F1401 +#define GPIO_PR5_I2C3SDA 0x000F1402 +#define GPIO_PR5_T0CCP1 0x000F1403 +#define GPIO_PR5_M0PWM5 0x000F1406 + +#define GPIO_PR6_U1TX 0x000F1801 +#define GPIO_PR6_I2C4SCL 0x000F1802 +#define GPIO_PR6_T1CCP0 0x000F1803 +#define GPIO_PR6_M0PWM6 0x000F1806 + +#define GPIO_PR7_I2C4SDA 0x000F1C02 +#define GPIO_PR7_T1CCP1 0x000F1C03 +#define GPIO_PR7_M0PWM7 0x000F1C06 + +#define GPIO_PS0_T2CCP0 0x00100003 +#define GPIO_PS0_M0FAULT0 0x00100006 + +#define GPIO_PS1_T2CCP1 0x00100403 +#define GPIO_PS1_M0FAULT1 0x00100406 + +#define GPIO_PS2_U1DSR 0x00100801 +#define GPIO_PS2_T3CCP0 0x00100803 +#define GPIO_PS2_M0FAULT2 0x00100806 + +#define GPIO_PS3_T3CCP1 0x00100C03 +#define GPIO_PS3_M0FAULT3 0x00100C06 + +#define GPIO_PS4_T4CCP0 0x00101003 +#define GPIO_PS4_PHA0 0x00101006 + +#define GPIO_PS5_T4CCP1 0x00101403 +#define GPIO_PS5_PHB0 0x00101406 + +#define GPIO_PS6_T5CCP0 0x00101803 +#define GPIO_PS6_IDX0 0x00101806 + +#define GPIO_PS7_T5CCP1 0x00101C03 + +#define GPIO_PT0_T6CCP0 0x00110003 +#define GPIO_PT0_CAN0RX 0x00110007 + +#define GPIO_PT1_T6CCP1 0x00110403 +#define GPIO_PT1_CAN0TX 0x00110407 + +#define GPIO_PT2_T7CCP0 0x00110803 +#define GPIO_PT2_CAN1RX 0x00110807 + +#define GPIO_PT3_T7CCP1 0x00110C03 +#define GPIO_PT3_CAN1TX 0x00110C07 + +#endif // PART_TM4C1294NCZAD + +//***************************************************************************** +// +// TM4C1297NCZAD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1297NCZAD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PB6_I2C6SCL 0x00011802 +#define GPIO_PB6_T6CCP0 0x00011803 + +#define GPIO_PB7_I2C6SDA 0x00011C02 +#define GPIO_PB7_T6CCP1 0x00011C03 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_T7CCP0 0x00021003 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_T7CCP1 0x00021403 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PE6_U0CTS 0x00041801 +#define GPIO_PE6_I2C9SCL 0x00041802 + +#define GPIO_PE7_U0RTS 0x00041C01 +#define GPIO_PE7_I2C9SDA 0x00041C02 +#define GPIO_PE7_NMI 0x00041C08 + +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PF5_SSI3XDAT3 0x0005140E + +#define GPIO_PF6_LCDMCLK 0x0005180F + +#define GPIO_PF7_LCDDATA02 0x00051C0F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PH4_U0DTR 0x00071001 + +#define GPIO_PH5_U0RI 0x00071401 + +#define GPIO_PH6_U5RX 0x00071801 +#define GPIO_PH6_U7RX 0x00071802 + +#define GPIO_PH7_U5TX 0x00071C01 +#define GPIO_PH7_U7TX 0x00071C02 + +#define GPIO_PJ0_U3RX 0x00080001 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PJ2_U2RTS 0x00080801 +#define GPIO_PJ2_LCDDATA14 0x0008080F + +#define GPIO_PJ3_U2CTS 0x00080C01 +#define GPIO_PJ3_LCDDATA15 0x00080C0F + +#define GPIO_PJ4_U3RTS 0x00081001 +#define GPIO_PJ4_LCDDATA16 0x0008100F + +#define GPIO_PJ5_U3CTS 0x00081401 +#define GPIO_PJ5_LCDDATA17 0x0008140F + +#define GPIO_PJ6_U4RTS 0x00081801 +#define GPIO_PJ6_LCDAC 0x0008180F + +#define GPIO_PJ7_U4CTS 0x00081C01 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PN6_U4RTS 0x000C1802 +#define GPIO_PN6_LCDDATA13 0x000C180F + +#define GPIO_PN7_U1RTS 0x000C1C01 +#define GPIO_PN7_U4CTS 0x000C1C02 +#define GPIO_PN7_LCDDATA12 0x000C1C0F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_T6CCP0 0x000D0005 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_T6CCP1 0x000D0405 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PP6_U1DCD 0x000D1801 +#define GPIO_PP6_I2C2SDA 0x000D1802 + +#define GPIO_PQ0_T6CCP0 0x000E0003 +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_T6CCP1 0x000E0403 +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_T7CCP0 0x000E0803 +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_T7CCP1 0x000E0C03 +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 + +#define GPIO_PQ6_U1DTR 0x000E1801 + +#define GPIO_PQ7_U1RI 0x000E1C01 + +#define GPIO_PR0_U4TX 0x000F0001 +#define GPIO_PR0_I2C1SCL 0x000F0002 +#define GPIO_PR0_M0PWM0 0x000F0006 +#define GPIO_PR0_LCDCP 0x000F000F + +#define GPIO_PR1_U4RX 0x000F0401 +#define GPIO_PR1_I2C1SDA 0x000F0402 +#define GPIO_PR1_M0PWM1 0x000F0406 +#define GPIO_PR1_LCDFP 0x000F040F + +#define GPIO_PR2_I2C2SCL 0x000F0802 +#define GPIO_PR2_M0PWM2 0x000F0806 +#define GPIO_PR2_LCDLP 0x000F080F + +#define GPIO_PR3_I2C2SDA 0x000F0C02 +#define GPIO_PR3_M0PWM3 0x000F0C06 +#define GPIO_PR3_LCDDATA03 0x000F0C0F + +#define GPIO_PR4_I2C3SCL 0x000F1002 +#define GPIO_PR4_T0CCP0 0x000F1003 +#define GPIO_PR4_M0PWM4 0x000F1006 +#define GPIO_PR4_LCDDATA00 0x000F100F + +#define GPIO_PR5_U1RX 0x000F1401 +#define GPIO_PR5_I2C3SDA 0x000F1402 +#define GPIO_PR5_T0CCP1 0x000F1403 +#define GPIO_PR5_M0PWM5 0x000F1406 +#define GPIO_PR5_LCDDATA01 0x000F140F + +#define GPIO_PR6_U1TX 0x000F1801 +#define GPIO_PR6_I2C4SCL 0x000F1802 +#define GPIO_PR6_T1CCP0 0x000F1803 +#define GPIO_PR6_M0PWM6 0x000F1806 +#define GPIO_PR6_LCDDATA04 0x000F180F + +#define GPIO_PR7_I2C4SDA 0x000F1C02 +#define GPIO_PR7_T1CCP1 0x000F1C03 +#define GPIO_PR7_M0PWM7 0x000F1C06 +#define GPIO_PR7_LCDDATA05 0x000F1C0F + +#define GPIO_PS0_T2CCP0 0x00100003 +#define GPIO_PS0_M0FAULT0 0x00100006 +#define GPIO_PS0_LCDDATA20 0x0010000F + +#define GPIO_PS1_T2CCP1 0x00100403 +#define GPIO_PS1_M0FAULT1 0x00100406 +#define GPIO_PS1_LCDDATA21 0x0010040F + +#define GPIO_PS2_U1DSR 0x00100801 +#define GPIO_PS2_T3CCP0 0x00100803 +#define GPIO_PS2_M0FAULT2 0x00100806 +#define GPIO_PS2_LCDDATA22 0x0010080F + +#define GPIO_PS3_T3CCP1 0x00100C03 +#define GPIO_PS3_M0FAULT3 0x00100C06 +#define GPIO_PS3_LCDDATA23 0x00100C0F + +#define GPIO_PS4_T4CCP0 0x00101003 +#define GPIO_PS4_PHA0 0x00101006 +#define GPIO_PS4_LCDDATA06 0x0010100F + +#define GPIO_PS5_T4CCP1 0x00101403 +#define GPIO_PS5_PHB0 0x00101406 +#define GPIO_PS5_LCDDATA07 0x0010140F + +#define GPIO_PS6_T5CCP0 0x00101803 +#define GPIO_PS6_IDX0 0x00101806 +#define GPIO_PS6_LCDDATA08 0x0010180F + +#define GPIO_PS7_T5CCP1 0x00101C03 +#define GPIO_PS7_LCDDATA09 0x00101C0F + +#define GPIO_PT0_T6CCP0 0x00110003 +#define GPIO_PT0_CAN0RX 0x00110007 +#define GPIO_PT0_LCDDATA10 0x0011000F + +#define GPIO_PT1_T6CCP1 0x00110403 +#define GPIO_PT1_CAN0TX 0x00110407 +#define GPIO_PT1_LCDDATA11 0x0011040F + +#define GPIO_PT2_T7CCP0 0x00110803 +#define GPIO_PT2_CAN1RX 0x00110807 +#define GPIO_PT2_LCDDATA18 0x0011080F + +#define GPIO_PT3_T7CCP1 0x00110C03 +#define GPIO_PT3_CAN1TX 0x00110C07 +#define GPIO_PT3_LCDDATA19 0x00110C0F + +#endif // PART_TM4C1297NCZAD + +//***************************************************************************** +// +// TM4C1299KCZAD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1299KCZAD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PB6_I2C6SCL 0x00011802 +#define GPIO_PB6_T6CCP0 0x00011803 + +#define GPIO_PB7_I2C6SDA 0x00011C02 +#define GPIO_PB7_T6CCP1 0x00011C03 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_T7CCP0 0x00021003 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_T7CCP1 0x00021403 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PE6_U0CTS 0x00041801 +#define GPIO_PE6_I2C9SCL 0x00041802 + +#define GPIO_PE7_U0RTS 0x00041C01 +#define GPIO_PE7_I2C9SDA 0x00041C02 +#define GPIO_PE7_NMI 0x00041C08 + +#define GPIO_PF0_EN0LED0 0x00050005 +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_EN0LED2 0x00050405 +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_EN0LED1 0x00051005 +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PF5_SSI3XDAT3 0x0005140E + +#define GPIO_PF6_LCDMCLK 0x0005180F + +#define GPIO_PF7_LCDDATA02 0x00051C0F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_EN0PPS 0x00060005 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PH4_U0DTR 0x00071001 + +#define GPIO_PH5_U0RI 0x00071401 +#define GPIO_PH5_EN0PPS 0x00071405 + +#define GPIO_PH6_U5RX 0x00071801 +#define GPIO_PH6_U7RX 0x00071802 + +#define GPIO_PH7_U5TX 0x00071C01 +#define GPIO_PH7_U7TX 0x00071C02 + +#define GPIO_PJ0_U3RX 0x00080001 +#define GPIO_PJ0_EN0PPS 0x00080005 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PJ2_U2RTS 0x00080801 +#define GPIO_PJ2_LCDDATA14 0x0008080F + +#define GPIO_PJ3_U2CTS 0x00080C01 +#define GPIO_PJ3_LCDDATA15 0x00080C0F + +#define GPIO_PJ4_U3RTS 0x00081001 +#define GPIO_PJ4_LCDDATA16 0x0008100F + +#define GPIO_PJ5_U3CTS 0x00081401 +#define GPIO_PJ5_LCDDATA17 0x0008140F + +#define GPIO_PJ6_U4RTS 0x00081801 +#define GPIO_PJ6_LCDAC 0x0008180F + +#define GPIO_PJ7_U4CTS 0x00081C01 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_EN0LED0 0x00091005 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_EN0LED2 0x00091405 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_EN0LED1 0x00091805 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PN6_U4RTS 0x000C1802 +#define GPIO_PN6_LCDDATA13 0x000C180F + +#define GPIO_PN7_U1RTS 0x000C1C01 +#define GPIO_PN7_U4CTS 0x000C1C02 +#define GPIO_PN7_LCDDATA12 0x000C1C0F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_T6CCP0 0x000D0005 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_T6CCP1 0x000D0405 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PP6_U1DCD 0x000D1801 +#define GPIO_PP6_I2C2SDA 0x000D1802 + +#define GPIO_PQ0_T6CCP0 0x000E0003 +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_T6CCP1 0x000E0403 +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_T7CCP0 0x000E0803 +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_T7CCP1 0x000E0C03 +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 + +#define GPIO_PQ6_U1DTR 0x000E1801 + +#define GPIO_PQ7_U1RI 0x000E1C01 + +#define GPIO_PR0_U4TX 0x000F0001 +#define GPIO_PR0_I2C1SCL 0x000F0002 +#define GPIO_PR0_M0PWM0 0x000F0006 +#define GPIO_PR0_LCDCP 0x000F000F + +#define GPIO_PR1_U4RX 0x000F0401 +#define GPIO_PR1_I2C1SDA 0x000F0402 +#define GPIO_PR1_M0PWM1 0x000F0406 +#define GPIO_PR1_LCDFP 0x000F040F + +#define GPIO_PR2_I2C2SCL 0x000F0802 +#define GPIO_PR2_M0PWM2 0x000F0806 +#define GPIO_PR2_LCDLP 0x000F080F + +#define GPIO_PR3_I2C2SDA 0x000F0C02 +#define GPIO_PR3_M0PWM3 0x000F0C06 +#define GPIO_PR3_LCDDATA03 0x000F0C0F + +#define GPIO_PR4_I2C3SCL 0x000F1002 +#define GPIO_PR4_T0CCP0 0x000F1003 +#define GPIO_PR4_M0PWM4 0x000F1006 +#define GPIO_PR4_LCDDATA00 0x000F100F + +#define GPIO_PR5_U1RX 0x000F1401 +#define GPIO_PR5_I2C3SDA 0x000F1402 +#define GPIO_PR5_T0CCP1 0x000F1403 +#define GPIO_PR5_M0PWM5 0x000F1406 +#define GPIO_PR5_LCDDATA01 0x000F140F + +#define GPIO_PR6_U1TX 0x000F1801 +#define GPIO_PR6_I2C4SCL 0x000F1802 +#define GPIO_PR6_T1CCP0 0x000F1803 +#define GPIO_PR6_M0PWM6 0x000F1806 +#define GPIO_PR6_LCDDATA04 0x000F180F + +#define GPIO_PR7_I2C4SDA 0x000F1C02 +#define GPIO_PR7_T1CCP1 0x000F1C03 +#define GPIO_PR7_M0PWM7 0x000F1C06 +#define GPIO_PR7_LCDDATA05 0x000F1C0F + +#define GPIO_PS0_T2CCP0 0x00100003 +#define GPIO_PS0_M0FAULT0 0x00100006 +#define GPIO_PS0_LCDDATA20 0x0010000F + +#define GPIO_PS1_T2CCP1 0x00100403 +#define GPIO_PS1_M0FAULT1 0x00100406 +#define GPIO_PS1_LCDDATA21 0x0010040F + +#define GPIO_PS2_U1DSR 0x00100801 +#define GPIO_PS2_T3CCP0 0x00100803 +#define GPIO_PS2_M0FAULT2 0x00100806 +#define GPIO_PS2_LCDDATA22 0x0010080F + +#define GPIO_PS3_T3CCP1 0x00100C03 +#define GPIO_PS3_M0FAULT3 0x00100C06 +#define GPIO_PS3_LCDDATA23 0x00100C0F + +#define GPIO_PS4_T4CCP0 0x00101003 +#define GPIO_PS4_PHA0 0x00101006 +#define GPIO_PS4_LCDDATA06 0x0010100F + +#define GPIO_PS5_T4CCP1 0x00101403 +#define GPIO_PS5_PHB0 0x00101406 +#define GPIO_PS5_LCDDATA07 0x0010140F + +#define GPIO_PS6_T5CCP0 0x00101803 +#define GPIO_PS6_IDX0 0x00101806 +#define GPIO_PS6_LCDDATA08 0x0010180F + +#define GPIO_PS7_T5CCP1 0x00101C03 +#define GPIO_PS7_LCDDATA09 0x00101C0F + +#define GPIO_PT0_T6CCP0 0x00110003 +#define GPIO_PT0_CAN0RX 0x00110007 +#define GPIO_PT0_LCDDATA10 0x0011000F + +#define GPIO_PT1_T6CCP1 0x00110403 +#define GPIO_PT1_CAN0TX 0x00110407 +#define GPIO_PT1_LCDDATA11 0x0011040F + +#define GPIO_PT2_T7CCP0 0x00110803 +#define GPIO_PT2_CAN1RX 0x00110807 +#define GPIO_PT2_LCDDATA18 0x0011080F + +#define GPIO_PT3_T7CCP1 0x00110C03 +#define GPIO_PT3_CAN1TX 0x00110C07 +#define GPIO_PT3_LCDDATA19 0x00110C0F + +#endif // PART_TM4C1299KCZAD + +//***************************************************************************** +// +// TM4C1299NCZAD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1299NCZAD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PB6_I2C6SCL 0x00011802 +#define GPIO_PB6_T6CCP0 0x00011803 + +#define GPIO_PB7_I2C6SDA 0x00011C02 +#define GPIO_PB7_T6CCP1 0x00011C03 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_T7CCP0 0x00021003 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_T7CCP1 0x00021403 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PE6_U0CTS 0x00041801 +#define GPIO_PE6_I2C9SCL 0x00041802 + +#define GPIO_PE7_U0RTS 0x00041C01 +#define GPIO_PE7_I2C9SDA 0x00041C02 +#define GPIO_PE7_NMI 0x00041C08 + +#define GPIO_PF0_EN0LED0 0x00050005 +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_EN0LED2 0x00050405 +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_EN0LED1 0x00051005 +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PF5_SSI3XDAT3 0x0005140E + +#define GPIO_PF6_LCDMCLK 0x0005180F + +#define GPIO_PF7_LCDDATA02 0x00051C0F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_EN0PPS 0x00060005 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PH4_U0DTR 0x00071001 + +#define GPIO_PH5_U0RI 0x00071401 +#define GPIO_PH5_EN0PPS 0x00071405 + +#define GPIO_PH6_U5RX 0x00071801 +#define GPIO_PH6_U7RX 0x00071802 + +#define GPIO_PH7_U5TX 0x00071C01 +#define GPIO_PH7_U7TX 0x00071C02 + +#define GPIO_PJ0_U3RX 0x00080001 +#define GPIO_PJ0_EN0PPS 0x00080005 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PJ2_U2RTS 0x00080801 +#define GPIO_PJ2_LCDDATA14 0x0008080F + +#define GPIO_PJ3_U2CTS 0x00080C01 +#define GPIO_PJ3_LCDDATA15 0x00080C0F + +#define GPIO_PJ4_U3RTS 0x00081001 +#define GPIO_PJ4_LCDDATA16 0x0008100F + +#define GPIO_PJ5_U3CTS 0x00081401 +#define GPIO_PJ5_LCDDATA17 0x0008140F + +#define GPIO_PJ6_U4RTS 0x00081801 +#define GPIO_PJ6_LCDAC 0x0008180F + +#define GPIO_PJ7_U4CTS 0x00081C01 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_EN0LED0 0x00091005 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_EN0LED2 0x00091405 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_EN0LED1 0x00091805 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PN6_U4RTS 0x000C1802 +#define GPIO_PN6_LCDDATA13 0x000C180F + +#define GPIO_PN7_U1RTS 0x000C1C01 +#define GPIO_PN7_U4CTS 0x000C1C02 +#define GPIO_PN7_LCDDATA12 0x000C1C0F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_T6CCP0 0x000D0005 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_T6CCP1 0x000D0405 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PP6_U1DCD 0x000D1801 +#define GPIO_PP6_I2C2SDA 0x000D1802 + +#define GPIO_PQ0_T6CCP0 0x000E0003 +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_T6CCP1 0x000E0403 +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_T7CCP0 0x000E0803 +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_T7CCP1 0x000E0C03 +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 + +#define GPIO_PQ6_U1DTR 0x000E1801 + +#define GPIO_PQ7_U1RI 0x000E1C01 + +#define GPIO_PR0_U4TX 0x000F0001 +#define GPIO_PR0_I2C1SCL 0x000F0002 +#define GPIO_PR0_M0PWM0 0x000F0006 +#define GPIO_PR0_LCDCP 0x000F000F + +#define GPIO_PR1_U4RX 0x000F0401 +#define GPIO_PR1_I2C1SDA 0x000F0402 +#define GPIO_PR1_M0PWM1 0x000F0406 +#define GPIO_PR1_LCDFP 0x000F040F + +#define GPIO_PR2_I2C2SCL 0x000F0802 +#define GPIO_PR2_M0PWM2 0x000F0806 +#define GPIO_PR2_LCDLP 0x000F080F + +#define GPIO_PR3_I2C2SDA 0x000F0C02 +#define GPIO_PR3_M0PWM3 0x000F0C06 +#define GPIO_PR3_LCDDATA03 0x000F0C0F + +#define GPIO_PR4_I2C3SCL 0x000F1002 +#define GPIO_PR4_T0CCP0 0x000F1003 +#define GPIO_PR4_M0PWM4 0x000F1006 +#define GPIO_PR4_LCDDATA00 0x000F100F + +#define GPIO_PR5_U1RX 0x000F1401 +#define GPIO_PR5_I2C3SDA 0x000F1402 +#define GPIO_PR5_T0CCP1 0x000F1403 +#define GPIO_PR5_M0PWM5 0x000F1406 +#define GPIO_PR5_LCDDATA01 0x000F140F + +#define GPIO_PR6_U1TX 0x000F1801 +#define GPIO_PR6_I2C4SCL 0x000F1802 +#define GPIO_PR6_T1CCP0 0x000F1803 +#define GPIO_PR6_M0PWM6 0x000F1806 +#define GPIO_PR6_LCDDATA04 0x000F180F + +#define GPIO_PR7_I2C4SDA 0x000F1C02 +#define GPIO_PR7_T1CCP1 0x000F1C03 +#define GPIO_PR7_M0PWM7 0x000F1C06 +#define GPIO_PR7_LCDDATA05 0x000F1C0F + +#define GPIO_PS0_T2CCP0 0x00100003 +#define GPIO_PS0_M0FAULT0 0x00100006 +#define GPIO_PS0_LCDDATA20 0x0010000F + +#define GPIO_PS1_T2CCP1 0x00100403 +#define GPIO_PS1_M0FAULT1 0x00100406 +#define GPIO_PS1_LCDDATA21 0x0010040F + +#define GPIO_PS2_U1DSR 0x00100801 +#define GPIO_PS2_T3CCP0 0x00100803 +#define GPIO_PS2_M0FAULT2 0x00100806 +#define GPIO_PS2_LCDDATA22 0x0010080F + +#define GPIO_PS3_T3CCP1 0x00100C03 +#define GPIO_PS3_M0FAULT3 0x00100C06 +#define GPIO_PS3_LCDDATA23 0x00100C0F + +#define GPIO_PS4_T4CCP0 0x00101003 +#define GPIO_PS4_PHA0 0x00101006 +#define GPIO_PS4_LCDDATA06 0x0010100F + +#define GPIO_PS5_T4CCP1 0x00101403 +#define GPIO_PS5_PHB0 0x00101406 +#define GPIO_PS5_LCDDATA07 0x0010140F + +#define GPIO_PS6_T5CCP0 0x00101803 +#define GPIO_PS6_IDX0 0x00101806 +#define GPIO_PS6_LCDDATA08 0x0010180F + +#define GPIO_PS7_T5CCP1 0x00101C03 +#define GPIO_PS7_LCDDATA09 0x00101C0F + +#define GPIO_PT0_T6CCP0 0x00110003 +#define GPIO_PT0_CAN0RX 0x00110007 +#define GPIO_PT0_LCDDATA10 0x0011000F + +#define GPIO_PT1_T6CCP1 0x00110403 +#define GPIO_PT1_CAN0TX 0x00110407 +#define GPIO_PT1_LCDDATA11 0x0011040F + +#define GPIO_PT2_T7CCP0 0x00110803 +#define GPIO_PT2_CAN1RX 0x00110807 +#define GPIO_PT2_LCDDATA18 0x0011080F + +#define GPIO_PT3_T7CCP1 0x00110C03 +#define GPIO_PT3_CAN1TX 0x00110C07 +#define GPIO_PT3_LCDDATA19 0x00110C0F + +#endif // PART_TM4C1299NCZAD + +//***************************************************************************** +// +// TM4C129CNCPDT Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C129CNCPDT + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PJ0_U3RX 0x00080001 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 + +#define GPIO_PQ6_U1DTR 0x000E1801 + +#endif // PART_TM4C129CNCPDT + +//***************************************************************************** +// +// TM4C129CNCZAD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C129CNCZAD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PB6_I2C6SCL 0x00011802 +#define GPIO_PB6_T6CCP0 0x00011803 + +#define GPIO_PB7_I2C6SDA 0x00011C02 +#define GPIO_PB7_T6CCP1 0x00011C03 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_T7CCP0 0x00021003 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_T7CCP1 0x00021403 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PE6_U0CTS 0x00041801 +#define GPIO_PE6_I2C9SCL 0x00041802 + +#define GPIO_PE7_U0RTS 0x00041C01 +#define GPIO_PE7_I2C9SDA 0x00041C02 +#define GPIO_PE7_NMI 0x00041C08 + +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PF5_SSI3XDAT3 0x0005140E + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PH4_U0DTR 0x00071001 + +#define GPIO_PH5_U0RI 0x00071401 + +#define GPIO_PH6_U5RX 0x00071801 +#define GPIO_PH6_U7RX 0x00071802 + +#define GPIO_PH7_U5TX 0x00071C01 +#define GPIO_PH7_U7TX 0x00071C02 + +#define GPIO_PJ0_U3RX 0x00080001 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PJ2_U2RTS 0x00080801 + +#define GPIO_PJ3_U2CTS 0x00080C01 + +#define GPIO_PJ4_U3RTS 0x00081001 + +#define GPIO_PJ5_U3CTS 0x00081401 + +#define GPIO_PJ6_U4RTS 0x00081801 + +#define GPIO_PJ7_U4CTS 0x00081C01 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PN6_U4RTS 0x000C1802 + +#define GPIO_PN7_U1RTS 0x000C1C01 +#define GPIO_PN7_U4CTS 0x000C1C02 + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_T6CCP0 0x000D0005 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_T6CCP1 0x000D0405 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PP6_U1DCD 0x000D1801 +#define GPIO_PP6_I2C2SDA 0x000D1802 + +#define GPIO_PQ0_T6CCP0 0x000E0003 +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_T6CCP1 0x000E0403 +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_T7CCP0 0x000E0803 +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_T7CCP1 0x000E0C03 +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 + +#define GPIO_PQ6_U1DTR 0x000E1801 + +#define GPIO_PQ7_U1RI 0x000E1C01 + +#define GPIO_PR0_U4TX 0x000F0001 +#define GPIO_PR0_I2C1SCL 0x000F0002 +#define GPIO_PR0_M0PWM0 0x000F0006 + +#define GPIO_PR1_U4RX 0x000F0401 +#define GPIO_PR1_I2C1SDA 0x000F0402 +#define GPIO_PR1_M0PWM1 0x000F0406 + +#define GPIO_PR2_I2C2SCL 0x000F0802 +#define GPIO_PR2_M0PWM2 0x000F0806 + +#define GPIO_PR3_I2C2SDA 0x000F0C02 +#define GPIO_PR3_M0PWM3 0x000F0C06 + +#define GPIO_PR4_I2C3SCL 0x000F1002 +#define GPIO_PR4_T0CCP0 0x000F1003 +#define GPIO_PR4_M0PWM4 0x000F1006 + +#define GPIO_PR5_U1RX 0x000F1401 +#define GPIO_PR5_I2C3SDA 0x000F1402 +#define GPIO_PR5_T0CCP1 0x000F1403 +#define GPIO_PR5_M0PWM5 0x000F1406 + +#define GPIO_PR6_U1TX 0x000F1801 +#define GPIO_PR6_I2C4SCL 0x000F1802 +#define GPIO_PR6_T1CCP0 0x000F1803 +#define GPIO_PR6_M0PWM6 0x000F1806 + +#define GPIO_PR7_I2C4SDA 0x000F1C02 +#define GPIO_PR7_T1CCP1 0x000F1C03 +#define GPIO_PR7_M0PWM7 0x000F1C06 + +#define GPIO_PS0_T2CCP0 0x00100003 +#define GPIO_PS0_M0FAULT0 0x00100006 + +#define GPIO_PS1_T2CCP1 0x00100403 +#define GPIO_PS1_M0FAULT1 0x00100406 + +#define GPIO_PS2_U1DSR 0x00100801 +#define GPIO_PS2_T3CCP0 0x00100803 +#define GPIO_PS2_M0FAULT2 0x00100806 + +#define GPIO_PS3_T3CCP1 0x00100C03 +#define GPIO_PS3_M0FAULT3 0x00100C06 + +#define GPIO_PS4_T4CCP0 0x00101003 +#define GPIO_PS4_PHA0 0x00101006 + +#define GPIO_PS5_T4CCP1 0x00101403 +#define GPIO_PS5_PHB0 0x00101406 + +#define GPIO_PS6_T5CCP0 0x00101803 +#define GPIO_PS6_IDX0 0x00101806 + +#define GPIO_PS7_T5CCP1 0x00101C03 + +#define GPIO_PT0_T6CCP0 0x00110003 +#define GPIO_PT0_CAN0RX 0x00110007 + +#define GPIO_PT1_T6CCP1 0x00110403 +#define GPIO_PT1_CAN0TX 0x00110407 + +#define GPIO_PT2_T7CCP0 0x00110803 +#define GPIO_PT2_CAN1RX 0x00110807 + +#define GPIO_PT3_T7CCP1 0x00110C03 +#define GPIO_PT3_CAN1TX 0x00110C07 + +#endif // PART_TM4C129CNCZAD + +//***************************************************************************** +// +// TM4C129DNCPDT Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C129DNCPDT + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EN0RXCK 0x0000180E +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_EN0MDC 0x00010805 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_EN0MDIO 0x00010C05 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_EN0MDC 0x00050805 +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_EN0MDIO 0x00050C05 +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_EN0TXCK 0x0006080E +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_EN0TXEN 0x00060C0E +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_EN0TXD0 0x0006100E +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_EN0TXD1 0x0006140E +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_EN0RXER 0x0006180E +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_EN0RXDV 0x00061C0E +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PJ0_U3RX 0x00080001 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EN0INTRN 0x00091007 +#define GPIO_PK4_EN0RXD3 0x0009100E +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EN0RXD2 0x0009140E +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EN0TXD2 0x0009180E +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EN0TXD3 0x00091C0E +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 +#define GPIO_PM4_EN0RREF_CLK 0x000B100E + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 +#define GPIO_PM6_EN0CRS 0x000B180E + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 +#define GPIO_PM7_EN0COL 0x000B1C0E + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_EN0INTRN 0x000D0007 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 +#define GPIO_PQ5_EN0RXD0 0x000E140E + +#define GPIO_PQ6_U1DTR 0x000E1801 +#define GPIO_PQ6_EN0RXD1 0x000E180E + +#endif // PART_TM4C129DNCPDT + +//***************************************************************************** +// +// TM4C129DNCZAD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C129DNCZAD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EN0RXCK 0x0000180E +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_EN0MDC 0x00010805 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_EN0MDIO 0x00010C05 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PB6_I2C6SCL 0x00011802 +#define GPIO_PB6_T6CCP0 0x00011803 + +#define GPIO_PB7_I2C6SDA 0x00011C02 +#define GPIO_PB7_T6CCP1 0x00011C03 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_T7CCP0 0x00021003 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_T7CCP1 0x00021403 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PE6_U0CTS 0x00041801 +#define GPIO_PE6_I2C9SCL 0x00041802 + +#define GPIO_PE7_U0RTS 0x00041C01 +#define GPIO_PE7_I2C9SDA 0x00041C02 +#define GPIO_PE7_NMI 0x00041C08 + +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_EN0MDC 0x00050805 +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_EN0MDIO 0x00050C05 +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PF5_SSI3XDAT3 0x0005140E + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_EN0TXCK 0x0006080E +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_EN0TXEN 0x00060C0E +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_EN0TXD0 0x0006100E +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_EN0TXD1 0x0006140E +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_EN0RXER 0x0006180E +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_EN0RXDV 0x00061C0E +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PH4_U0DTR 0x00071001 + +#define GPIO_PH5_U0RI 0x00071401 + +#define GPIO_PH6_U5RX 0x00071801 +#define GPIO_PH6_U7RX 0x00071802 + +#define GPIO_PH7_U5TX 0x00071C01 +#define GPIO_PH7_U7TX 0x00071C02 + +#define GPIO_PJ0_U3RX 0x00080001 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PJ2_U2RTS 0x00080801 + +#define GPIO_PJ3_U2CTS 0x00080C01 + +#define GPIO_PJ4_U3RTS 0x00081001 + +#define GPIO_PJ5_U3CTS 0x00081401 + +#define GPIO_PJ6_U4RTS 0x00081801 + +#define GPIO_PJ7_U4CTS 0x00081C01 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EN0INTRN 0x00091007 +#define GPIO_PK4_EN0RXD3 0x0009100E +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EN0RXD2 0x0009140E +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EN0TXD2 0x0009180E +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EN0TXD3 0x00091C0E +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 +#define GPIO_PM4_EN0RREF_CLK 0x000B100E + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 +#define GPIO_PM6_EN0CRS 0x000B180E + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 +#define GPIO_PM7_EN0COL 0x000B1C0E + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PN6_U4RTS 0x000C1802 +#define GPIO_PN6_EN0TXER 0x000C180E + +#define GPIO_PN7_U1RTS 0x000C1C01 +#define GPIO_PN7_U4CTS 0x000C1C02 + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_T6CCP0 0x000D0005 +#define GPIO_PP0_EN0INTRN 0x000D0007 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_T6CCP1 0x000D0405 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PP6_U1DCD 0x000D1801 +#define GPIO_PP6_I2C2SDA 0x000D1802 + +#define GPIO_PQ0_T6CCP0 0x000E0003 +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_T6CCP1 0x000E0403 +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_T7CCP0 0x000E0803 +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_T7CCP1 0x000E0C03 +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 +#define GPIO_PQ5_EN0RXD0 0x000E140E + +#define GPIO_PQ6_U1DTR 0x000E1801 +#define GPIO_PQ6_EN0RXD1 0x000E180E + +#define GPIO_PQ7_U1RI 0x000E1C01 + +#define GPIO_PR0_U4TX 0x000F0001 +#define GPIO_PR0_I2C1SCL 0x000F0002 +#define GPIO_PR0_M0PWM0 0x000F0006 + +#define GPIO_PR1_U4RX 0x000F0401 +#define GPIO_PR1_I2C1SDA 0x000F0402 +#define GPIO_PR1_M0PWM1 0x000F0406 + +#define GPIO_PR2_I2C2SCL 0x000F0802 +#define GPIO_PR2_M0PWM2 0x000F0806 + +#define GPIO_PR3_I2C2SDA 0x000F0C02 +#define GPIO_PR3_M0PWM3 0x000F0C06 + +#define GPIO_PR4_I2C3SCL 0x000F1002 +#define GPIO_PR4_T0CCP0 0x000F1003 +#define GPIO_PR4_M0PWM4 0x000F1006 + +#define GPIO_PR5_U1RX 0x000F1401 +#define GPIO_PR5_I2C3SDA 0x000F1402 +#define GPIO_PR5_T0CCP1 0x000F1403 +#define GPIO_PR5_M0PWM5 0x000F1406 + +#define GPIO_PR6_U1TX 0x000F1801 +#define GPIO_PR6_I2C4SCL 0x000F1802 +#define GPIO_PR6_T1CCP0 0x000F1803 +#define GPIO_PR6_M0PWM6 0x000F1806 + +#define GPIO_PR7_I2C4SDA 0x000F1C02 +#define GPIO_PR7_T1CCP1 0x000F1C03 +#define GPIO_PR7_M0PWM7 0x000F1C06 +#define GPIO_PR7_EN0TXEN 0x000F1C0E + +#define GPIO_PS0_T2CCP0 0x00100003 +#define GPIO_PS0_M0FAULT0 0x00100006 + +#define GPIO_PS1_T2CCP1 0x00100403 +#define GPIO_PS1_M0FAULT1 0x00100406 + +#define GPIO_PS2_U1DSR 0x00100801 +#define GPIO_PS2_T3CCP0 0x00100803 +#define GPIO_PS2_M0FAULT2 0x00100806 + +#define GPIO_PS3_T3CCP1 0x00100C03 +#define GPIO_PS3_M0FAULT3 0x00100C06 + +#define GPIO_PS4_T4CCP0 0x00101003 +#define GPIO_PS4_PHA0 0x00101006 +#define GPIO_PS4_EN0TXD0 0x0010100E + +#define GPIO_PS5_T4CCP1 0x00101403 +#define GPIO_PS5_PHB0 0x00101406 +#define GPIO_PS5_EN0TXD1 0x0010140E + +#define GPIO_PS6_T5CCP0 0x00101803 +#define GPIO_PS6_IDX0 0x00101806 +#define GPIO_PS6_EN0RXER 0x0010180E + +#define GPIO_PS7_T5CCP1 0x00101C03 +#define GPIO_PS7_EN0RXDV 0x00101C0E + +#define GPIO_PT0_T6CCP0 0x00110003 +#define GPIO_PT0_CAN0RX 0x00110007 +#define GPIO_PT0_EN0RXD0 0x0011000E + +#define GPIO_PT1_T6CCP1 0x00110403 +#define GPIO_PT1_CAN0TX 0x00110407 +#define GPIO_PT1_EN0RXD1 0x0011040E + +#define GPIO_PT2_T7CCP0 0x00110803 +#define GPIO_PT2_CAN1RX 0x00110807 + +#define GPIO_PT3_T7CCP1 0x00110C03 +#define GPIO_PT3_CAN1TX 0x00110C07 + +#endif // PART_TM4C129DNCZAD + +//***************************************************************************** +// +// TM4C129EKCPDT Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C129EKCPDT + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PF0_EN0LED0 0x00050005 +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_EN0LED2 0x00050405 +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_EN0LED1 0x00051005 +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_EN0PPS 0x00060005 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PJ0_U3RX 0x00080001 +#define GPIO_PJ0_EN0PPS 0x00080005 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_EN0LED0 0x00091005 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_EN0LED2 0x00091405 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_EN0LED1 0x00091805 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#endif // PART_TM4C129EKCPDT + +//***************************************************************************** +// +// TM4C129ENCPDT Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C129ENCPDT + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PF0_EN0LED0 0x00050005 +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_EN0LED2 0x00050405 +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_EN0LED1 0x00051005 +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_EN0PPS 0x00060005 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PJ0_U3RX 0x00080001 +#define GPIO_PJ0_EN0PPS 0x00080005 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_EN0LED0 0x00091005 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_EN0LED2 0x00091405 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_EN0LED1 0x00091805 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#endif // PART_TM4C129ENCPDT + +//***************************************************************************** +// +// TM4C129ENCZAD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C129ENCZAD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PB6_I2C6SCL 0x00011802 +#define GPIO_PB6_T6CCP0 0x00011803 + +#define GPIO_PB7_I2C6SDA 0x00011C02 +#define GPIO_PB7_T6CCP1 0x00011C03 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_T7CCP0 0x00021003 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_T7CCP1 0x00021403 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PE6_U0CTS 0x00041801 +#define GPIO_PE6_I2C9SCL 0x00041802 + +#define GPIO_PE7_U0RTS 0x00041C01 +#define GPIO_PE7_I2C9SDA 0x00041C02 +#define GPIO_PE7_NMI 0x00041C08 + +#define GPIO_PF0_EN0LED0 0x00050005 +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_EN0LED2 0x00050405 +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_EN0LED1 0x00051005 +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PF5_SSI3XDAT3 0x0005140E + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_EN0PPS 0x00060005 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PH4_U0DTR 0x00071001 + +#define GPIO_PH5_U0RI 0x00071401 +#define GPIO_PH5_EN0PPS 0x00071405 + +#define GPIO_PH6_U5RX 0x00071801 +#define GPIO_PH6_U7RX 0x00071802 + +#define GPIO_PH7_U5TX 0x00071C01 +#define GPIO_PH7_U7TX 0x00071C02 + +#define GPIO_PJ0_U3RX 0x00080001 +#define GPIO_PJ0_EN0PPS 0x00080005 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PJ2_U2RTS 0x00080801 + +#define GPIO_PJ3_U2CTS 0x00080C01 + +#define GPIO_PJ4_U3RTS 0x00081001 + +#define GPIO_PJ5_U3CTS 0x00081401 + +#define GPIO_PJ6_U4RTS 0x00081801 + +#define GPIO_PJ7_U4CTS 0x00081C01 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_EN0LED0 0x00091005 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_EN0LED2 0x00091405 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_EN0LED1 0x00091805 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PN6_U4RTS 0x000C1802 + +#define GPIO_PN7_U1RTS 0x000C1C01 +#define GPIO_PN7_U4CTS 0x000C1C02 + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_T6CCP0 0x000D0005 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_T6CCP1 0x000D0405 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PP6_U1DCD 0x000D1801 +#define GPIO_PP6_I2C2SDA 0x000D1802 + +#define GPIO_PQ0_T6CCP0 0x000E0003 +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_T6CCP1 0x000E0403 +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_T7CCP0 0x000E0803 +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_T7CCP1 0x000E0C03 +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 + +#define GPIO_PQ6_U1DTR 0x000E1801 + +#define GPIO_PQ7_U1RI 0x000E1C01 + +#define GPIO_PR0_U4TX 0x000F0001 +#define GPIO_PR0_I2C1SCL 0x000F0002 +#define GPIO_PR0_M0PWM0 0x000F0006 + +#define GPIO_PR1_U4RX 0x000F0401 +#define GPIO_PR1_I2C1SDA 0x000F0402 +#define GPIO_PR1_M0PWM1 0x000F0406 + +#define GPIO_PR2_I2C2SCL 0x000F0802 +#define GPIO_PR2_M0PWM2 0x000F0806 + +#define GPIO_PR3_I2C2SDA 0x000F0C02 +#define GPIO_PR3_M0PWM3 0x000F0C06 + +#define GPIO_PR4_I2C3SCL 0x000F1002 +#define GPIO_PR4_T0CCP0 0x000F1003 +#define GPIO_PR4_M0PWM4 0x000F1006 + +#define GPIO_PR5_U1RX 0x000F1401 +#define GPIO_PR5_I2C3SDA 0x000F1402 +#define GPIO_PR5_T0CCP1 0x000F1403 +#define GPIO_PR5_M0PWM5 0x000F1406 + +#define GPIO_PR6_U1TX 0x000F1801 +#define GPIO_PR6_I2C4SCL 0x000F1802 +#define GPIO_PR6_T1CCP0 0x000F1803 +#define GPIO_PR6_M0PWM6 0x000F1806 + +#define GPIO_PR7_I2C4SDA 0x000F1C02 +#define GPIO_PR7_T1CCP1 0x000F1C03 +#define GPIO_PR7_M0PWM7 0x000F1C06 + +#define GPIO_PS0_T2CCP0 0x00100003 +#define GPIO_PS0_M0FAULT0 0x00100006 + +#define GPIO_PS1_T2CCP1 0x00100403 +#define GPIO_PS1_M0FAULT1 0x00100406 + +#define GPIO_PS2_U1DSR 0x00100801 +#define GPIO_PS2_T3CCP0 0x00100803 +#define GPIO_PS2_M0FAULT2 0x00100806 + +#define GPIO_PS3_T3CCP1 0x00100C03 +#define GPIO_PS3_M0FAULT3 0x00100C06 + +#define GPIO_PS4_T4CCP0 0x00101003 +#define GPIO_PS4_PHA0 0x00101006 + +#define GPIO_PS5_T4CCP1 0x00101403 +#define GPIO_PS5_PHB0 0x00101406 + +#define GPIO_PS6_T5CCP0 0x00101803 +#define GPIO_PS6_IDX0 0x00101806 + +#define GPIO_PS7_T5CCP1 0x00101C03 + +#define GPIO_PT0_T6CCP0 0x00110003 +#define GPIO_PT0_CAN0RX 0x00110007 + +#define GPIO_PT1_T6CCP1 0x00110403 +#define GPIO_PT1_CAN0TX 0x00110407 + +#define GPIO_PT2_T7CCP0 0x00110803 +#define GPIO_PT2_CAN1RX 0x00110807 + +#define GPIO_PT3_T7CCP1 0x00110C03 +#define GPIO_PT3_CAN1TX 0x00110C07 + +#endif // PART_TM4C129ENCZAD + +//***************************************************************************** +// +// TM4C129LNCZAD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C129LNCZAD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PB6_I2C6SCL 0x00011802 +#define GPIO_PB6_T6CCP0 0x00011803 + +#define GPIO_PB7_I2C6SDA 0x00011C02 +#define GPIO_PB7_T6CCP1 0x00011C03 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_T7CCP0 0x00021003 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_T7CCP1 0x00021403 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PE6_U0CTS 0x00041801 +#define GPIO_PE6_I2C9SCL 0x00041802 + +#define GPIO_PE7_U0RTS 0x00041C01 +#define GPIO_PE7_I2C9SDA 0x00041C02 +#define GPIO_PE7_NMI 0x00041C08 + +#define GPIO_PF0_EN0LED0 0x00050005 +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_EN0LED2 0x00050405 +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_EN0LED1 0x00051005 +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PF5_SSI3XDAT3 0x0005140E + +#define GPIO_PF6_LCDMCLK 0x0005180F + +#define GPIO_PF7_LCDDATA02 0x00051C0F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_EN0PPS 0x00060005 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PH4_U0DTR 0x00071001 + +#define GPIO_PH5_U0RI 0x00071401 +#define GPIO_PH5_EN0PPS 0x00071405 + +#define GPIO_PH6_U5RX 0x00071801 +#define GPIO_PH6_U7RX 0x00071802 + +#define GPIO_PH7_U5TX 0x00071C01 +#define GPIO_PH7_U7TX 0x00071C02 + +#define GPIO_PJ0_U3RX 0x00080001 +#define GPIO_PJ0_EN0PPS 0x00080005 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PJ2_U2RTS 0x00080801 +#define GPIO_PJ2_LCDDATA14 0x0008080F + +#define GPIO_PJ3_U2CTS 0x00080C01 +#define GPIO_PJ3_LCDDATA15 0x00080C0F + +#define GPIO_PJ4_U3RTS 0x00081001 +#define GPIO_PJ4_LCDDATA16 0x0008100F + +#define GPIO_PJ5_U3CTS 0x00081401 +#define GPIO_PJ5_LCDDATA17 0x0008140F + +#define GPIO_PJ6_U4RTS 0x00081801 +#define GPIO_PJ6_LCDAC 0x0008180F + +#define GPIO_PJ7_U4CTS 0x00081C01 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_EN0LED0 0x00091005 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_EN0LED2 0x00091405 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_EN0LED1 0x00091805 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PN6_U4RTS 0x000C1802 +#define GPIO_PN6_LCDDATA13 0x000C180F + +#define GPIO_PN7_U1RTS 0x000C1C01 +#define GPIO_PN7_U4CTS 0x000C1C02 +#define GPIO_PN7_LCDDATA12 0x000C1C0F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_T6CCP0 0x000D0005 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_T6CCP1 0x000D0405 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PP6_U1DCD 0x000D1801 +#define GPIO_PP6_I2C2SDA 0x000D1802 + +#define GPIO_PQ0_T6CCP0 0x000E0003 +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_T6CCP1 0x000E0403 +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_T7CCP0 0x000E0803 +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_T7CCP1 0x000E0C03 +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 + +#define GPIO_PQ6_U1DTR 0x000E1801 + +#define GPIO_PQ7_U1RI 0x000E1C01 + +#define GPIO_PR0_U4TX 0x000F0001 +#define GPIO_PR0_I2C1SCL 0x000F0002 +#define GPIO_PR0_M0PWM0 0x000F0006 +#define GPIO_PR0_LCDCP 0x000F000F + +#define GPIO_PR1_U4RX 0x000F0401 +#define GPIO_PR1_I2C1SDA 0x000F0402 +#define GPIO_PR1_M0PWM1 0x000F0406 +#define GPIO_PR1_LCDFP 0x000F040F + +#define GPIO_PR2_I2C2SCL 0x000F0802 +#define GPIO_PR2_M0PWM2 0x000F0806 +#define GPIO_PR2_LCDLP 0x000F080F + +#define GPIO_PR3_I2C2SDA 0x000F0C02 +#define GPIO_PR3_M0PWM3 0x000F0C06 +#define GPIO_PR3_LCDDATA03 0x000F0C0F + +#define GPIO_PR4_I2C3SCL 0x000F1002 +#define GPIO_PR4_T0CCP0 0x000F1003 +#define GPIO_PR4_M0PWM4 0x000F1006 +#define GPIO_PR4_LCDDATA00 0x000F100F + +#define GPIO_PR5_U1RX 0x000F1401 +#define GPIO_PR5_I2C3SDA 0x000F1402 +#define GPIO_PR5_T0CCP1 0x000F1403 +#define GPIO_PR5_M0PWM5 0x000F1406 +#define GPIO_PR5_LCDDATA01 0x000F140F + +#define GPIO_PR6_U1TX 0x000F1801 +#define GPIO_PR6_I2C4SCL 0x000F1802 +#define GPIO_PR6_T1CCP0 0x000F1803 +#define GPIO_PR6_M0PWM6 0x000F1806 +#define GPIO_PR6_LCDDATA04 0x000F180F + +#define GPIO_PR7_I2C4SDA 0x000F1C02 +#define GPIO_PR7_T1CCP1 0x000F1C03 +#define GPIO_PR7_M0PWM7 0x000F1C06 +#define GPIO_PR7_LCDDATA05 0x000F1C0F + +#define GPIO_PS0_T2CCP0 0x00100003 +#define GPIO_PS0_M0FAULT0 0x00100006 +#define GPIO_PS0_LCDDATA20 0x0010000F + +#define GPIO_PS1_T2CCP1 0x00100403 +#define GPIO_PS1_M0FAULT1 0x00100406 +#define GPIO_PS1_LCDDATA21 0x0010040F + +#define GPIO_PS2_U1DSR 0x00100801 +#define GPIO_PS2_T3CCP0 0x00100803 +#define GPIO_PS2_M0FAULT2 0x00100806 +#define GPIO_PS2_LCDDATA22 0x0010080F + +#define GPIO_PS3_T3CCP1 0x00100C03 +#define GPIO_PS3_M0FAULT3 0x00100C06 +#define GPIO_PS3_LCDDATA23 0x00100C0F + +#define GPIO_PS4_T4CCP0 0x00101003 +#define GPIO_PS4_PHA0 0x00101006 +#define GPIO_PS4_LCDDATA06 0x0010100F + +#define GPIO_PS5_T4CCP1 0x00101403 +#define GPIO_PS5_PHB0 0x00101406 +#define GPIO_PS5_LCDDATA07 0x0010140F + +#define GPIO_PS6_T5CCP0 0x00101803 +#define GPIO_PS6_IDX0 0x00101806 +#define GPIO_PS6_LCDDATA08 0x0010180F + +#define GPIO_PS7_T5CCP1 0x00101C03 +#define GPIO_PS7_LCDDATA09 0x00101C0F + +#define GPIO_PT0_T6CCP0 0x00110003 +#define GPIO_PT0_CAN0RX 0x00110007 +#define GPIO_PT0_LCDDATA10 0x0011000F + +#define GPIO_PT1_T6CCP1 0x00110403 +#define GPIO_PT1_CAN0TX 0x00110407 +#define GPIO_PT1_LCDDATA11 0x0011040F + +#define GPIO_PT2_T7CCP0 0x00110803 +#define GPIO_PT2_CAN1RX 0x00110807 +#define GPIO_PT2_LCDDATA18 0x0011080F + +#define GPIO_PT3_T7CCP1 0x00110C03 +#define GPIO_PT3_CAN1TX 0x00110C07 +#define GPIO_PT3_LCDDATA19 0x00110C0F + +#endif // PART_TM4C129LNCZAD + +//***************************************************************************** +// +// TM4C129XKCZAD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C129XKCZAD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EN0RXCK 0x0000180E +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_EN0MDC 0x00010805 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_EN0MDIO 0x00010C05 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PB6_I2C6SCL 0x00011802 +#define GPIO_PB6_T6CCP0 0x00011803 + +#define GPIO_PB7_I2C6SDA 0x00011C02 +#define GPIO_PB7_T6CCP1 0x00011C03 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_T7CCP0 0x00021003 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_T7CCP1 0x00021403 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 +#define GPIO_PE3_OWIRE 0x00040C05 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PE6_U0CTS 0x00041801 +#define GPIO_PE6_I2C9SCL 0x00041802 + +#define GPIO_PE7_U0RTS 0x00041C01 +#define GPIO_PE7_I2C9SDA 0x00041C02 +#define GPIO_PE7_NMI 0x00041C08 + +#define GPIO_PF0_EN0LED0 0x00050005 +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_EN0LED2 0x00050405 +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_EN0MDC 0x00050805 +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_EN0MDIO 0x00050C05 +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_EN0LED1 0x00051005 +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PF5_SSI3XDAT3 0x0005140E + +#define GPIO_PF6_LCDMCLK 0x0005180F + +#define GPIO_PF7_LCDDATA02 0x00051C0F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_EN0PPS 0x00060005 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_EN0TXCK 0x0006080E +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_EN0TXEN 0x00060C0E +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_OWIRE 0x00061005 +#define GPIO_PG4_EN0TXD0 0x0006100E +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_OWALT 0x00061405 +#define GPIO_PG5_EN0TXD1 0x0006140E +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_OWIRE 0x00061805 +#define GPIO_PG6_EN0RXER 0x0006180E +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_OWIRE 0x00061C05 +#define GPIO_PG7_EN0RXDV 0x00061C0E +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PH4_U0DTR 0x00071001 + +#define GPIO_PH5_U0RI 0x00071401 +#define GPIO_PH5_EN0PPS 0x00071405 + +#define GPIO_PH6_U5RX 0x00071801 +#define GPIO_PH6_U7RX 0x00071802 + +#define GPIO_PH7_U5TX 0x00071C01 +#define GPIO_PH7_U7TX 0x00071C02 + +#define GPIO_PJ0_U3RX 0x00080001 +#define GPIO_PJ0_EN0PPS 0x00080005 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PJ2_U2RTS 0x00080801 +#define GPIO_PJ2_LCDDATA14 0x0008080F + +#define GPIO_PJ3_U2CTS 0x00080C01 +#define GPIO_PJ3_LCDDATA15 0x00080C0F + +#define GPIO_PJ4_U3RTS 0x00081001 +#define GPIO_PJ4_LCDDATA16 0x0008100F + +#define GPIO_PJ5_U3CTS 0x00081401 +#define GPIO_PJ5_LCDDATA17 0x0008140F + +#define GPIO_PJ6_U4RTS 0x00081801 +#define GPIO_PJ6_LCDAC 0x0008180F + +#define GPIO_PJ7_U4CTS 0x00081C01 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_EN0LED0 0x00091005 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EN0INTRN 0x00091007 +#define GPIO_PK4_EN0RXD3 0x0009100E +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_EN0LED2 0x00091405 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EN0RXD2 0x0009140E +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_EN0LED1 0x00091805 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EN0TXD2 0x0009180E +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EN0TXD3 0x00091C0E +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 +#define GPIO_PM4_EN0RREF_CLK 0x000B100E + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 +#define GPIO_PM6_EN0CRS 0x000B180E + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 +#define GPIO_PM7_EN0COL 0x000B1C0E + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PN6_U4RTS 0x000C1802 +#define GPIO_PN6_EN0TXER 0x000C180E +#define GPIO_PN6_LCDDATA13 0x000C180F + +#define GPIO_PN7_U1RTS 0x000C1C01 +#define GPIO_PN7_U4CTS 0x000C1C02 +#define GPIO_PN7_LCDDATA12 0x000C1C0F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_T6CCP0 0x000D0005 +#define GPIO_PP0_EN0INTRN 0x000D0007 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_T6CCP1 0x000D0405 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_OWIRE 0x000D1004 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_OWALT 0x000D1404 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PP6_U1DCD 0x000D1801 +#define GPIO_PP6_I2C2SDA 0x000D1802 + +#define GPIO_PP7_OWIRE 0x000D1C05 + +#define GPIO_PQ0_T6CCP0 0x000E0003 +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_T6CCP1 0x000E0403 +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_T7CCP0 0x000E0803 +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_T7CCP1 0x000E0C03 +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 +#define GPIO_PQ5_EN0RXD0 0x000E140E + +#define GPIO_PQ6_U1DTR 0x000E1801 +#define GPIO_PQ6_EN0RXD1 0x000E180E + +#define GPIO_PQ7_U1RI 0x000E1C01 + +#define GPIO_PR0_U4TX 0x000F0001 +#define GPIO_PR0_I2C1SCL 0x000F0002 +#define GPIO_PR0_M0PWM0 0x000F0006 +#define GPIO_PR0_LCDCP 0x000F000F + +#define GPIO_PR1_U4RX 0x000F0401 +#define GPIO_PR1_I2C1SDA 0x000F0402 +#define GPIO_PR1_M0PWM1 0x000F0406 +#define GPIO_PR1_LCDFP 0x000F040F + +#define GPIO_PR2_I2C2SCL 0x000F0802 +#define GPIO_PR2_M0PWM2 0x000F0806 +#define GPIO_PR2_LCDLP 0x000F080F + +#define GPIO_PR3_I2C2SDA 0x000F0C02 +#define GPIO_PR3_M0PWM3 0x000F0C06 +#define GPIO_PR3_LCDDATA03 0x000F0C0F + +#define GPIO_PR4_I2C3SCL 0x000F1002 +#define GPIO_PR4_T0CCP0 0x000F1003 +#define GPIO_PR4_M0PWM4 0x000F1006 +#define GPIO_PR4_LCDDATA00 0x000F100F + +#define GPIO_PR5_U1RX 0x000F1401 +#define GPIO_PR5_I2C3SDA 0x000F1402 +#define GPIO_PR5_T0CCP1 0x000F1403 +#define GPIO_PR5_M0PWM5 0x000F1406 +#define GPIO_PR5_LCDDATA01 0x000F140F + +#define GPIO_PR6_U1TX 0x000F1801 +#define GPIO_PR6_I2C4SCL 0x000F1802 +#define GPIO_PR6_T1CCP0 0x000F1803 +#define GPIO_PR6_M0PWM6 0x000F1806 +#define GPIO_PR6_LCDDATA04 0x000F180F + +#define GPIO_PR7_I2C4SDA 0x000F1C02 +#define GPIO_PR7_T1CCP1 0x000F1C03 +#define GPIO_PR7_M0PWM7 0x000F1C06 +#define GPIO_PR7_EN0TXEN 0x000F1C0E +#define GPIO_PR7_LCDDATA05 0x000F1C0F + +#define GPIO_PS0_T2CCP0 0x00100003 +#define GPIO_PS0_M0FAULT0 0x00100006 +#define GPIO_PS0_LCDDATA20 0x0010000F + +#define GPIO_PS1_T2CCP1 0x00100403 +#define GPIO_PS1_M0FAULT1 0x00100406 +#define GPIO_PS1_LCDDATA21 0x0010040F + +#define GPIO_PS2_U1DSR 0x00100801 +#define GPIO_PS2_T3CCP0 0x00100803 +#define GPIO_PS2_M0FAULT2 0x00100806 +#define GPIO_PS2_LCDDATA22 0x0010080F + +#define GPIO_PS3_T3CCP1 0x00100C03 +#define GPIO_PS3_M0FAULT3 0x00100C06 +#define GPIO_PS3_LCDDATA23 0x00100C0F + +#define GPIO_PS4_T4CCP0 0x00101003 +#define GPIO_PS4_PHA0 0x00101006 +#define GPIO_PS4_EN0TXD0 0x0010100E +#define GPIO_PS4_LCDDATA06 0x0010100F + +#define GPIO_PS5_T4CCP1 0x00101403 +#define GPIO_PS5_PHB0 0x00101406 +#define GPIO_PS5_EN0TXD1 0x0010140E +#define GPIO_PS5_LCDDATA07 0x0010140F + +#define GPIO_PS6_T5CCP0 0x00101803 +#define GPIO_PS6_IDX0 0x00101806 +#define GPIO_PS6_EN0RXER 0x0010180E +#define GPIO_PS6_LCDDATA08 0x0010180F + +#define GPIO_PS7_T5CCP1 0x00101C03 +#define GPIO_PS7_EN0RXDV 0x00101C0E +#define GPIO_PS7_LCDDATA09 0x00101C0F + +#define GPIO_PT0_T6CCP0 0x00110003 +#define GPIO_PT0_CAN0RX 0x00110007 +#define GPIO_PT0_EN0RXD0 0x0011000E +#define GPIO_PT0_LCDDATA10 0x0011000F + +#define GPIO_PT1_T6CCP1 0x00110403 +#define GPIO_PT1_CAN0TX 0x00110407 +#define GPIO_PT1_EN0RXD1 0x0011040E +#define GPIO_PT1_LCDDATA11 0x0011040F + +#define GPIO_PT2_T7CCP0 0x00110803 +#define GPIO_PT2_CAN1RX 0x00110807 +#define GPIO_PT2_LCDDATA18 0x0011080F + +#define GPIO_PT3_T7CCP1 0x00110C03 +#define GPIO_PT3_CAN1TX 0x00110C07 +#define GPIO_PT3_LCDDATA19 0x00110C0F + +#endif // PART_TM4C129XKCZAD + +//***************************************************************************** +// +// TM4C129XNCZAD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C129XNCZAD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EN0RXCK 0x0000180E +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_EN0MDC 0x00010805 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_EN0MDIO 0x00010C05 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PB6_I2C6SCL 0x00011802 +#define GPIO_PB6_T6CCP0 0x00011803 + +#define GPIO_PB7_I2C6SDA 0x00011C02 +#define GPIO_PB7_T6CCP1 0x00011C03 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_T7CCP0 0x00021003 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_T7CCP1 0x00021403 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 +#define GPIO_PE3_OWIRE 0x00040C05 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PE6_U0CTS 0x00041801 +#define GPIO_PE6_I2C9SCL 0x00041802 + +#define GPIO_PE7_U0RTS 0x00041C01 +#define GPIO_PE7_I2C9SDA 0x00041C02 +#define GPIO_PE7_NMI 0x00041C08 + +#define GPIO_PF0_EN0LED0 0x00050005 +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_EN0LED2 0x00050405 +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_EN0MDC 0x00050805 +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_EN0MDIO 0x00050C05 +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_EN0LED1 0x00051005 +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PF5_SSI3XDAT3 0x0005140E + +#define GPIO_PF6_LCDMCLK 0x0005180F + +#define GPIO_PF7_LCDDATA02 0x00051C0F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_EN0PPS 0x00060005 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_EN0TXCK 0x0006080E +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_EN0TXEN 0x00060C0E +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_OWIRE 0x00061005 +#define GPIO_PG4_EN0TXD0 0x0006100E +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_OWALT 0x00061405 +#define GPIO_PG5_EN0TXD1 0x0006140E +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_OWIRE 0x00061805 +#define GPIO_PG6_EN0RXER 0x0006180E +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_OWIRE 0x00061C05 +#define GPIO_PG7_EN0RXDV 0x00061C0E +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PH4_U0DTR 0x00071001 + +#define GPIO_PH5_U0RI 0x00071401 +#define GPIO_PH5_EN0PPS 0x00071405 + +#define GPIO_PH6_U5RX 0x00071801 +#define GPIO_PH6_U7RX 0x00071802 + +#define GPIO_PH7_U5TX 0x00071C01 +#define GPIO_PH7_U7TX 0x00071C02 + +#define GPIO_PJ0_U3RX 0x00080001 +#define GPIO_PJ0_EN0PPS 0x00080005 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PJ2_U2RTS 0x00080801 +#define GPIO_PJ2_LCDDATA14 0x0008080F + +#define GPIO_PJ3_U2CTS 0x00080C01 +#define GPIO_PJ3_LCDDATA15 0x00080C0F + +#define GPIO_PJ4_U3RTS 0x00081001 +#define GPIO_PJ4_LCDDATA16 0x0008100F + +#define GPIO_PJ5_U3CTS 0x00081401 +#define GPIO_PJ5_LCDDATA17 0x0008140F + +#define GPIO_PJ6_U4RTS 0x00081801 +#define GPIO_PJ6_LCDAC 0x0008180F + +#define GPIO_PJ7_U4CTS 0x00081C01 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_EN0LED0 0x00091005 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EN0INTRN 0x00091007 +#define GPIO_PK4_EN0RXD3 0x0009100E +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_EN0LED2 0x00091405 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EN0RXD2 0x0009140E +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_EN0LED1 0x00091805 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EN0TXD2 0x0009180E +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EN0TXD3 0x00091C0E +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 +#define GPIO_PM4_EN0RREF_CLK 0x000B100E + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 +#define GPIO_PM6_EN0CRS 0x000B180E + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 +#define GPIO_PM7_EN0COL 0x000B1C0E + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PN6_U4RTS 0x000C1802 +#define GPIO_PN6_EN0TXER 0x000C180E +#define GPIO_PN6_LCDDATA13 0x000C180F + +#define GPIO_PN7_U1RTS 0x000C1C01 +#define GPIO_PN7_U4CTS 0x000C1C02 +#define GPIO_PN7_LCDDATA12 0x000C1C0F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_T6CCP0 0x000D0005 +#define GPIO_PP0_EN0INTRN 0x000D0007 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_T6CCP1 0x000D0405 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_OWIRE 0x000D1004 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_OWALT 0x000D1404 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PP6_U1DCD 0x000D1801 +#define GPIO_PP6_I2C2SDA 0x000D1802 + +#define GPIO_PP7_OWIRE 0x000D1C05 + +#define GPIO_PQ0_T6CCP0 0x000E0003 +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_T6CCP1 0x000E0403 +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_T7CCP0 0x000E0803 +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_T7CCP1 0x000E0C03 +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 +#define GPIO_PQ5_EN0RXD0 0x000E140E + +#define GPIO_PQ6_U1DTR 0x000E1801 +#define GPIO_PQ6_EN0RXD1 0x000E180E + +#define GPIO_PQ7_U1RI 0x000E1C01 + +#define GPIO_PR0_U4TX 0x000F0001 +#define GPIO_PR0_I2C1SCL 0x000F0002 +#define GPIO_PR0_M0PWM0 0x000F0006 +#define GPIO_PR0_LCDCP 0x000F000F + +#define GPIO_PR1_U4RX 0x000F0401 +#define GPIO_PR1_I2C1SDA 0x000F0402 +#define GPIO_PR1_M0PWM1 0x000F0406 +#define GPIO_PR1_LCDFP 0x000F040F + +#define GPIO_PR2_I2C2SCL 0x000F0802 +#define GPIO_PR2_M0PWM2 0x000F0806 +#define GPIO_PR2_LCDLP 0x000F080F + +#define GPIO_PR3_I2C2SDA 0x000F0C02 +#define GPIO_PR3_M0PWM3 0x000F0C06 +#define GPIO_PR3_LCDDATA03 0x000F0C0F + +#define GPIO_PR4_I2C3SCL 0x000F1002 +#define GPIO_PR4_T0CCP0 0x000F1003 +#define GPIO_PR4_M0PWM4 0x000F1006 +#define GPIO_PR4_LCDDATA00 0x000F100F + +#define GPIO_PR5_U1RX 0x000F1401 +#define GPIO_PR5_I2C3SDA 0x000F1402 +#define GPIO_PR5_T0CCP1 0x000F1403 +#define GPIO_PR5_M0PWM5 0x000F1406 +#define GPIO_PR5_LCDDATA01 0x000F140F + +#define GPIO_PR6_U1TX 0x000F1801 +#define GPIO_PR6_I2C4SCL 0x000F1802 +#define GPIO_PR6_T1CCP0 0x000F1803 +#define GPIO_PR6_M0PWM6 0x000F1806 +#define GPIO_PR6_LCDDATA04 0x000F180F + +#define GPIO_PR7_I2C4SDA 0x000F1C02 +#define GPIO_PR7_T1CCP1 0x000F1C03 +#define GPIO_PR7_M0PWM7 0x000F1C06 +#define GPIO_PR7_EN0TXEN 0x000F1C0E +#define GPIO_PR7_LCDDATA05 0x000F1C0F + +#define GPIO_PS0_T2CCP0 0x00100003 +#define GPIO_PS0_M0FAULT0 0x00100006 +#define GPIO_PS0_LCDDATA20 0x0010000F + +#define GPIO_PS1_T2CCP1 0x00100403 +#define GPIO_PS1_M0FAULT1 0x00100406 +#define GPIO_PS1_LCDDATA21 0x0010040F + +#define GPIO_PS2_U1DSR 0x00100801 +#define GPIO_PS2_T3CCP0 0x00100803 +#define GPIO_PS2_M0FAULT2 0x00100806 +#define GPIO_PS2_LCDDATA22 0x0010080F + +#define GPIO_PS3_T3CCP1 0x00100C03 +#define GPIO_PS3_M0FAULT3 0x00100C06 +#define GPIO_PS3_LCDDATA23 0x00100C0F + +#define GPIO_PS4_T4CCP0 0x00101003 +#define GPIO_PS4_PHA0 0x00101006 +#define GPIO_PS4_EN0TXD0 0x0010100E +#define GPIO_PS4_LCDDATA06 0x0010100F + +#define GPIO_PS5_T4CCP1 0x00101403 +#define GPIO_PS5_PHB0 0x00101406 +#define GPIO_PS5_EN0TXD1 0x0010140E +#define GPIO_PS5_LCDDATA07 0x0010140F + +#define GPIO_PS6_T5CCP0 0x00101803 +#define GPIO_PS6_IDX0 0x00101806 +#define GPIO_PS6_EN0RXER 0x0010180E +#define GPIO_PS6_LCDDATA08 0x0010180F + +#define GPIO_PS7_T5CCP1 0x00101C03 +#define GPIO_PS7_EN0RXDV 0x00101C0E +#define GPIO_PS7_LCDDATA09 0x00101C0F + +#define GPIO_PT0_T6CCP0 0x00110003 +#define GPIO_PT0_CAN0RX 0x00110007 +#define GPIO_PT0_EN0RXD0 0x0011000E +#define GPIO_PT0_LCDDATA10 0x0011000F + +#define GPIO_PT1_T6CCP1 0x00110403 +#define GPIO_PT1_CAN0TX 0x00110407 +#define GPIO_PT1_EN0RXD1 0x0011040E +#define GPIO_PT1_LCDDATA11 0x0011040F + +#define GPIO_PT2_T7CCP0 0x00110803 +#define GPIO_PT2_CAN1RX 0x00110807 +#define GPIO_PT2_LCDDATA18 0x0011080F + +#define GPIO_PT3_T7CCP1 0x00110C03 +#define GPIO_PT3_CAN1TX 0x00110C07 +#define GPIO_PT3_LCDDATA19 0x00110C0F + +#endif // PART_TM4C129XNCZAD + +#endif // __DRIVERLIB_PIN_MAP_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/pwm.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/pwm.h new file mode 100644 index 0000000000000000000000000000000000000000..c18d98acb229e2552585fcc5679e457e32da9c65 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/pwm.h @@ -0,0 +1,326 @@ +//***************************************************************************** +// +// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_PWM_H__ +#define __DRIVERLIB_PWM_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following defines are passed to PWMGenConfigure() as the ui32Config +// parameter and specify the configuration of the PWM generator. +// +//***************************************************************************** +#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode +#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode +#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates +#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates +#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode +#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode +#define PWM_GEN_MODE_FAULT_LATCHED \ + 0x00040000 // Fault is latched +#define PWM_GEN_MODE_FAULT_UNLATCHED \ + 0x00000000 // Fault is not latched +#define PWM_GEN_MODE_FAULT_MINPER \ + 0x00020000 // Enable min fault period +#define PWM_GEN_MODE_FAULT_NO_MINPER \ + 0x00000000 // Disable min fault period +#define PWM_GEN_MODE_FAULT_EXT 0x00010000 // Enable extended fault support +#define PWM_GEN_MODE_FAULT_LEGACY \ + 0x00000000 // Disable extended fault support +#define PWM_GEN_MODE_DB_NO_SYNC 0x00000000 // Deadband updates occur + // immediately +#define PWM_GEN_MODE_DB_SYNC_LOCAL \ + 0x0000A800 // Deadband updates locally + // synchronized +#define PWM_GEN_MODE_DB_SYNC_GLOBAL \ + 0x0000FC00 // Deadband updates globally + // synchronized +#define PWM_GEN_MODE_GEN_NO_SYNC \ + 0x00000000 // Generator mode updates occur + // immediately +#define PWM_GEN_MODE_GEN_SYNC_LOCAL \ + 0x00000280 // Generator mode updates locally + // synchronized +#define PWM_GEN_MODE_GEN_SYNC_GLOBAL \ + 0x000003C0 // Generator mode updates globally + // synchronized + +//***************************************************************************** +// +// Defines for enabling, disabling, and clearing PWM generator interrupts and +// triggers. +// +//***************************************************************************** +#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0 +#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD +#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U +#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D +#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U +#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D +#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0 +#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD +#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U +#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D +#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U +#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D + +//***************************************************************************** +// +// Defines for enabling, disabling, and clearing PWM interrupts. +// +//***************************************************************************** +#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt +#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt +#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt +#define PWM_INT_GEN_3 0x00000008 // Generator 3 interrupt +#define PWM_INT_FAULT0 0x00010000 // Fault0 interrupt +#define PWM_INT_FAULT1 0x00020000 // Fault1 interrupt +#define PWM_INT_FAULT2 0x00040000 // Fault2 interrupt +#define PWM_INT_FAULT3 0x00080000 // Fault3 interrupt +#define PWM_INT_FAULT_M 0x000F0000 // Fault interrupt source mask + +//***************************************************************************** +// +// Defines to identify the generators within a module. +// +//***************************************************************************** +#define PWM_GEN_0 0x00000040 // Offset address of Gen0 +#define PWM_GEN_1 0x00000080 // Offset address of Gen1 +#define PWM_GEN_2 0x000000C0 // Offset address of Gen2 +#define PWM_GEN_3 0x00000100 // Offset address of Gen3 + +#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0 +#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1 +#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2 +#define PWM_GEN_3_BIT 0x00000008 // Bit-wise ID for Gen3 + +#define PWM_GEN_EXT_0 0x00000800 // Offset of Gen0 ext address range +#define PWM_GEN_EXT_1 0x00000880 // Offset of Gen1 ext address range +#define PWM_GEN_EXT_2 0x00000900 // Offset of Gen2 ext address range +#define PWM_GEN_EXT_3 0x00000980 // Offset of Gen3 ext address range + +//***************************************************************************** +// +// Defines to identify the outputs within a module. +// +//***************************************************************************** +#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0 +#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1 +#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2 +#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3 +#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4 +#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5 +#define PWM_OUT_6 0x00000106 // Encoded offset address of PWM6 +#define PWM_OUT_7 0x00000107 // Encoded offset address of PWM7 + +#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0 +#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1 +#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2 +#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3 +#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4 +#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5 +#define PWM_OUT_6_BIT 0x00000040 // Bit-wise ID for PWM6 +#define PWM_OUT_7_BIT 0x00000080 // Bit-wise ID for PWM7 + +//***************************************************************************** +// +// Defines to identify each of the possible fault trigger conditions in +// PWM_FAULT_GROUP_0. +// +//***************************************************************************** +#define PWM_FAULT_GROUP_0 0 + +#define PWM_FAULT_FAULT0 0x00000001 +#define PWM_FAULT_FAULT1 0x00000002 +#define PWM_FAULT_FAULT2 0x00000004 +#define PWM_FAULT_FAULT3 0x00000008 +#define PWM_FAULT_ACMP0 0x00010000 +#define PWM_FAULT_ACMP1 0x00020000 +#define PWM_FAULT_ACMP2 0x00040000 + +//***************************************************************************** +// +// Defines to identify each of the possible fault trigger conditions in +// PWM_FAULT_GROUP_1. +// +//***************************************************************************** +#define PWM_FAULT_GROUP_1 1 + +#define PWM_FAULT_DCMP0 0x00000001 +#define PWM_FAULT_DCMP1 0x00000002 +#define PWM_FAULT_DCMP2 0x00000004 +#define PWM_FAULT_DCMP3 0x00000008 +#define PWM_FAULT_DCMP4 0x00000010 +#define PWM_FAULT_DCMP5 0x00000020 +#define PWM_FAULT_DCMP6 0x00000040 +#define PWM_FAULT_DCMP7 0x00000080 + +//***************************************************************************** +// +// Defines to identify the sense of each of the external FAULTn signals +// +//***************************************************************************** +#define PWM_FAULT0_SENSE_HIGH 0x00000000 +#define PWM_FAULT0_SENSE_LOW 0x00000001 +#define PWM_FAULT1_SENSE_HIGH 0x00000000 +#define PWM_FAULT1_SENSE_LOW 0x00000002 +#define PWM_FAULT2_SENSE_HIGH 0x00000000 +#define PWM_FAULT2_SENSE_LOW 0x00000004 +#define PWM_FAULT3_SENSE_HIGH 0x00000000 +#define PWM_FAULT3_SENSE_LOW 0x00000008 + +//***************************************************************************** +// +// Defines that can be passed to the PWMClockSet() API as the ui32Config +// parameter, and can be returned by the PWMClockGet() API. +// +//***************************************************************************** +#define PWM_SYSCLK_DIV_1 0x00000000 // PWM clock is system clock +#define PWM_SYSCLK_DIV_2 0x00000100 // PWM clock is system clock /2 +#define PWM_SYSCLK_DIV_4 0x00000101 // PWM clock is system clock /4 +#define PWM_SYSCLK_DIV_8 0x00000102 // PWM clock is system clock /8 +#define PWM_SYSCLK_DIV_16 0x00000103 // PWM clock is system clock /16 +#define PWM_SYSCLK_DIV_32 0x00000104 // PWM clock is system clock /32 +#define PWM_SYSCLK_DIV_64 0x00000105 // PWM clock is system clock /64 + +//***************************************************************************** +// +// Defines passed to PWMOutputUpdateMode() to identify the synchronization mode +// to use when enabling or disabling outputs using PWMOutputState(). +// +//***************************************************************************** +#define PWM_OUTPUT_MODE_NO_SYNC 0x00000000 // Updates to occur immediately +#define PWM_OUTPUT_MODE_SYNC_LOCAL \ + 0x00000002 // Updates are locally synchronized +#define PWM_OUTPUT_MODE_SYNC_GLOBAL \ + 0x00000003 // Updates are globally synchronized + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void PWMGenConfigure(uint32_t ui32Base, uint32_t ui32Gen, + uint32_t ui32Config); +extern void PWMGenPeriodSet(uint32_t ui32Base, uint32_t ui32Gen, + uint32_t ui32Period); +extern uint32_t PWMGenPeriodGet(uint32_t ui32Base, + uint32_t ui32Gen); +extern void PWMGenEnable(uint32_t ui32Base, uint32_t ui32Gen); +extern void PWMGenDisable(uint32_t ui32Base, uint32_t ui32Gen); +extern void PWMPulseWidthSet(uint32_t ui32Base, uint32_t ui32PWMOut, + uint32_t ui32Width); +extern uint32_t PWMPulseWidthGet(uint32_t ui32Base, + uint32_t ui32PWMOut); +extern void PWMDeadBandEnable(uint32_t ui32Base, uint32_t ui32Gen, + uint16_t ui16Rise, uint16_t ui16Fall); +extern void PWMDeadBandDisable(uint32_t ui32Base, uint32_t ui32Gen); +extern void PWMSyncUpdate(uint32_t ui32Base, uint32_t ui32GenBits); +extern void PWMSyncTimeBase(uint32_t ui32Base, uint32_t ui32GenBits); +extern void PWMOutputState(uint32_t ui32Base, uint32_t ui32PWMOutBits, + bool bEnable); +extern void PWMOutputInvert(uint32_t ui32Base, uint32_t ui32PWMOutBits, + bool bInvert); +extern void PWMOutputFaultLevel(uint32_t ui32Base, + uint32_t ui32PWMOutBits, + bool bDriveHigh); +extern void PWMOutputFault(uint32_t ui32Base, uint32_t ui32PWMOutBits, + bool bFaultSuppress); +extern void PWMGenIntRegister(uint32_t ui32Base, uint32_t ui32Gen, + void (*pfnIntHandler)(void)); +extern void PWMGenIntUnregister(uint32_t ui32Base, uint32_t ui32Gen); +extern void PWMFaultIntRegister(uint32_t ui32Base, + void (*pfnIntHandler)(void)); +extern void PWMFaultIntUnregister(uint32_t ui32Base); +extern void PWMGenIntTrigEnable(uint32_t ui32Base, uint32_t ui32Gen, + uint32_t ui32IntTrig); +extern void PWMGenIntTrigDisable(uint32_t ui32Base, uint32_t ui32Gen, + uint32_t ui32IntTrig); +extern uint32_t PWMGenIntStatus(uint32_t ui32Base, uint32_t ui32Gen, + bool bMasked); +extern void PWMGenIntClear(uint32_t ui32Base, uint32_t ui32Gen, + uint32_t ui32Ints); +extern void PWMIntEnable(uint32_t ui32Base, uint32_t ui32GenFault); +extern void PWMIntDisable(uint32_t ui32Base, uint32_t ui32GenFault); +extern void PWMFaultIntClear(uint32_t ui32Base); +extern uint32_t PWMIntStatus(uint32_t ui32Base, bool bMasked); +extern void PWMFaultIntClearExt(uint32_t ui32Base, + uint32_t ui32FaultInts); +extern void PWMGenFaultConfigure(uint32_t ui32Base, uint32_t ui32Gen, + uint32_t ui32MinFaultPeriod, + uint32_t ui32FaultSenses); +extern void PWMGenFaultTriggerSet(uint32_t ui32Base, uint32_t ui32Gen, + uint32_t ui32Group, + uint32_t ui32FaultTriggers); +extern uint32_t PWMGenFaultTriggerGet(uint32_t ui32Base, + uint32_t ui32Gen, + uint32_t ui32Group); +extern uint32_t PWMGenFaultStatus(uint32_t ui32Base, + uint32_t ui32Gen, + uint32_t ui32Group); +extern void PWMGenFaultClear(uint32_t ui32Base, uint32_t ui32Gen, + uint32_t ui32Group, + uint32_t ui32FaultTriggers); +extern void PWMClockSet(uint32_t ui32Base, uint32_t ui32Config); +extern uint32_t PWMClockGet(uint32_t ui32Base); +extern void PWMOutputUpdateMode(uint32_t ui32Base, + uint32_t ui32PWMOutBits, + uint32_t ui32Mode); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_PWM_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/qei.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/qei.h new file mode 100644 index 0000000000000000000000000000000000000000..031897ae31db0a0bbc208f0ef1cebf97a862c886 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/qei.h @@ -0,0 +1,154 @@ +//***************************************************************************** +// +// qei.h - Prototypes for the Quadrature Encoder Driver. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_QEI_H__ +#define __DRIVERLIB_QEI_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to QEIConfigure as the ui32Config paramater. +// +//***************************************************************************** +#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only +#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges +#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse +#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse +#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature +#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir +#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB +#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB + +//***************************************************************************** +// +// Values that can be passed to QEIFilterConfigure as the ui32PreDiv +// parameter. +// +//***************************************************************************** +#define QEI_FILTCNT_2 0x00000000 // Filter Count of 2 System Clocks +#define QEI_FILTCNT_3 0x00010000 // Filter Count of 3 System Clocks +#define QEI_FILTCNT_4 0x00020000 // Filter Count of 4 System Clocks +#define QEI_FILTCNT_5 0x00030000 // Filter Count of 5 System Clocks +#define QEI_FILTCNT_6 0x00040000 // Filter Count of 6 System Clocks +#define QEI_FILTCNT_7 0x00050000 // Filter Count of 7 System Clocks +#define QEI_FILTCNT_8 0x00060000 // Filter Count of 8 System Clocks +#define QEI_FILTCNT_9 0x00070000 // Filter Count of 9 System Clocks +#define QEI_FILTCNT_10 0x00080000 // Filter Count of 10 System Clocks +#define QEI_FILTCNT_11 0x00090000 // Filter Count of 11 System Clocks +#define QEI_FILTCNT_12 0x000A0000 // Filter Count of 12 System Clocks +#define QEI_FILTCNT_13 0x000B0000 // Filter Count of 13 System Clocks +#define QEI_FILTCNT_14 0x000C0000 // Filter Count of 14 System Clocks +#define QEI_FILTCNT_15 0x000D0000 // Filter Count of 15 System Clocks +#define QEI_FILTCNT_16 0x000E0000 // Filter Count of 16 System Clocks +#define QEI_FILTCNT_17 0x000F0000 // Filter Count of 17 System Clocks + +//***************************************************************************** +// +// Values that can be passed to QEIVelocityConfigure as the ui32PreDiv +// parameter. +// +//***************************************************************************** +#define QEI_VELDIV_1 0x00000000 // Predivide by 1 +#define QEI_VELDIV_2 0x00000040 // Predivide by 2 +#define QEI_VELDIV_4 0x00000080 // Predivide by 4 +#define QEI_VELDIV_8 0x000000C0 // Predivide by 8 +#define QEI_VELDIV_16 0x00000100 // Predivide by 16 +#define QEI_VELDIV_32 0x00000140 // Predivide by 32 +#define QEI_VELDIV_64 0x00000180 // Predivide by 64 +#define QEI_VELDIV_128 0x000001C0 // Predivide by 128 + +//***************************************************************************** +// +// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts +// as the ui32IntFlags parameter, and returned by QEIGetIntStatus. +// +//***************************************************************************** +#define QEI_INTERROR 0x00000008 // Phase error detected +#define QEI_INTDIR 0x00000004 // Direction change +#define QEI_INTTIMER 0x00000002 // Velocity timer expired +#define QEI_INTINDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void QEIEnable(uint32_t ui32Base); +extern void QEIDisable(uint32_t ui32Base); +extern void QEIConfigure(uint32_t ui32Base, uint32_t ui32Config, + uint32_t ui32MaxPosition); +extern uint32_t QEIPositionGet(uint32_t ui32Base); +extern void QEIPositionSet(uint32_t ui32Base, uint32_t ui32Position); +extern int32_t QEIDirectionGet(uint32_t ui32Base); +extern bool QEIErrorGet(uint32_t ui32Base); +extern void QEIFilterEnable(uint32_t ui32Base); +extern void QEIFilterDisable(uint32_t ui32Base); +extern void QEIFilterConfigure(uint32_t ui32Base, uint32_t ui32FiltCnt); +extern void QEIVelocityEnable(uint32_t ui32Base); +extern void QEIVelocityDisable(uint32_t ui32Base); +extern void QEIVelocityConfigure(uint32_t ui32Base, uint32_t ui32PreDiv, + uint32_t ui32Period); +extern uint32_t QEIVelocityGet(uint32_t ui32Base); +extern void QEIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); +extern void QEIIntUnregister(uint32_t ui32Base); +extern void QEIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void QEIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern uint32_t QEIIntStatus(uint32_t ui32Base, bool bMasked); +extern void QEIIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_QEI_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/rom.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/rom.h new file mode 100644 index 0000000000000000000000000000000000000000..2ffdab87e5f7daf5d0ea4a46e9a31f36680605cd --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/rom.h @@ -0,0 +1,8346 @@ +//***************************************************************************** +// +// rom.h - Macros to facilitate calling functions in the ROM. +// +// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_ROM_H__ +#define __DRIVERLIB_ROM_H__ + +#ifndef DEPRECATED +//***************************************************************************** +// +// ROM selection labels changed between TivaWare 2.0.1 and 2.1. The following +// labels are intended to ensure backwards compatibility for applications +// which have not yet been updated to use the replacement labels. +// +//***************************************************************************** +#ifdef TARGET_IS_SNOWFLAKE_RA0 +#define TARGET_IS_TM4C129_RA0 +#endif +#ifdef TARGET_IS_SNOWFLAKE_RA1 +#define TARGET_IS_TM4C129_RA1 +#endif +#ifdef TARGET_IS_SNOWFLAKE_RA2 +#define TARGET_IS_TM4C129_RA2 +#endif +#ifdef TARGET_IS_BLIZZARD_RA1 +#define TARGET_IS_TM4C123_RA1 +#endif +#ifdef TARGET_IS_BLIZZARD_RA2 +#define TARGET_IS_TM4C123_RA2 +#endif +#ifdef TARGET_IS_BLIZZARD_RA3 +#define TARGET_IS_TM4C123_RA3 +#endif +#ifdef TARGET_IS_BLIZZARD_RB0 +#define TARGET_IS_TM4C123_RB0 +#endif +#ifdef TARGET_IS_BLIZZARD_RB1 +#define TARGET_IS_TM4C123_RB1 +#endif +#endif + +//***************************************************************************** +// +// Pointers to the main API tables. +// +//***************************************************************************** +#define ROM_APITABLE ((uint32_t *)0x01000010) +#define ROM_VERSION (ROM_APITABLE[0]) +#define ROM_UARTTABLE ((uint32_t *)(ROM_APITABLE[1])) +#define ROM_SSITABLE ((uint32_t *)(ROM_APITABLE[2])) +#define ROM_I2CTABLE ((uint32_t *)(ROM_APITABLE[3])) +#define ROM_GPIOTABLE ((uint32_t *)(ROM_APITABLE[4])) +#define ROM_ADCTABLE ((uint32_t *)(ROM_APITABLE[5])) +#define ROM_COMPARATORTABLE ((uint32_t *)(ROM_APITABLE[6])) +#define ROM_FLASHTABLE ((uint32_t *)(ROM_APITABLE[7])) +#define ROM_PWMTABLE ((uint32_t *)(ROM_APITABLE[8])) +#define ROM_QEITABLE ((uint32_t *)(ROM_APITABLE[9])) +#define ROM_SYSTICKTABLE ((uint32_t *)(ROM_APITABLE[10])) +#define ROM_TIMERTABLE ((uint32_t *)(ROM_APITABLE[11])) +#define ROM_WATCHDOGTABLE ((uint32_t *)(ROM_APITABLE[12])) +#define ROM_SYSCTLTABLE ((uint32_t *)(ROM_APITABLE[13])) +#define ROM_INTERRUPTTABLE ((uint32_t *)(ROM_APITABLE[14])) +#define ROM_USBTABLE ((uint32_t *)(ROM_APITABLE[16])) +#define ROM_UDMATABLE ((uint32_t *)(ROM_APITABLE[17])) +#define ROM_CANTABLE ((uint32_t *)(ROM_APITABLE[18])) +#define ROM_HIBERNATETABLE ((uint32_t *)(ROM_APITABLE[19])) +#define ROM_MPUTABLE ((uint32_t *)(ROM_APITABLE[20])) +#define ROM_SOFTWARETABLE ((uint32_t *)(ROM_APITABLE[21])) +#define ROM_EPITABLE ((uint32_t *)(ROM_APITABLE[23])) +#define ROM_EEPROMTABLE ((uint32_t *)(ROM_APITABLE[24])) +#define ROM_FPUTABLE ((uint32_t *)(ROM_APITABLE[26])) +#define ROM_SMBUSTABLE ((uint32_t *)(ROM_APITABLE[29])) +#define ROM_SYSEXCTABLE ((uint32_t *)(ROM_APITABLE[30])) +#define ROM_ONEWIRETABLE ((uint32_t *)(ROM_APITABLE[34])) +#define ROM_SPIFLASHTABLE ((uint32_t *)(ROM_APITABLE[38])) +#define ROM_LCDTABLE ((uint32_t *)(ROM_APITABLE[41])) +#define ROM_EMACTABLE ((uint32_t *)(ROM_APITABLE[42])) +#define ROM_AESTABLE ((uint32_t *)(ROM_APITABLE[43])) +#define ROM_CRCTABLE ((uint32_t *)(ROM_APITABLE[44])) +#define ROM_DESTABLE ((uint32_t *)(ROM_APITABLE[45])) +#define ROM_SHAMD5TABLE ((uint32_t *)(ROM_APITABLE[46])) + +//***************************************************************************** +// +// Macros for calling ROM functions in the ADC API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceDataGet \ + ((int32_t (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum, \ + uint32_t *pui32Buffer))ROM_ADCTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum, \ + bool bMasked))ROM_ADCTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum, \ + uint32_t ui32Trigger, \ + uint32_t ui32Priority))ROM_ADCTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceStepConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum, \ + uint32_t ui32Step, \ + uint32_t ui32Config))ROM_ADCTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceOverflow \ + ((int32_t (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceOverflowClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceUnderflow \ + ((int32_t (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceUnderflowClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCProcessorTrigger \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCHardwareOversampleConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Factor))ROM_ADCTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCComparatorConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Comp, \ + uint32_t ui32Config))ROM_ADCTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCComparatorRegionSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Comp, \ + uint32_t ui32LowRef, \ + uint32_t ui32HighRef))ROM_ADCTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCComparatorReset \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Comp, \ + bool bTrigger, \ + bool bInterrupt))ROM_ADCTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCComparatorIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCComparatorIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCComparatorIntStatus \ + ((uint32_t (*)(uint32_t ui32Base))ROM_ADCTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCComparatorIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Status))ROM_ADCTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCReferenceSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Ref))ROM_ADCTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCReferenceGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_ADCTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCPhaseDelaySet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Phase))ROM_ADCTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCPhaseDelayGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_ADCTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCIntDisableEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_ADCTABLE[29]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCIntEnableEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_ADCTABLE[30]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCIntStatusEx \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_ADCTABLE[31]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceDMAEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[32]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceDMADisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[33]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCBusy \ + ((bool (*)(uint32_t ui32Base))ROM_ADCTABLE[34]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the AES API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_AESTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESAuthLengthSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Length))ROM_AESTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_AESTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESDataAuth \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Src, \ + uint32_t ui32Length, \ + uint32_t *pui32Tag))ROM_AESTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESDataProcess \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Src, \ + uint32_t *pui32Dest, \ + uint32_t ui32Length))ROM_AESTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESDataProcessAuth \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Src, \ + uint32_t *pui32Dest, \ + uint32_t ui32Length, \ + uint32_t *pui32AuthSrc, \ + uint32_t ui32AuthLength, \ + uint32_t *pui32Tag))ROM_AESTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESDataRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Dest))ROM_AESTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESDataReadNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Dest))ROM_AESTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESDataWrite \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Src))ROM_AESTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESDataWriteNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Src))ROM_AESTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESDMADisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Flags))ROM_AESTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESDMAEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Flags))ROM_AESTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_AESTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_AESTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_AESTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESIVSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32IVdata))ROM_AESTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESKey1Set \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Key, \ + uint32_t ui32Keysize))ROM_AESTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESKey2Set \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Key, \ + uint32_t ui32Keysize))ROM_AESTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESKey3Set \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Key))ROM_AESTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESLengthSet \ + ((void (*)(uint32_t ui32Base, \ + uint64_t ui64Length))ROM_AESTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESReset \ + ((void (*)(uint32_t ui32Base))ROM_AESTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESTagRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32TagData))ROM_AESTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESIVRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32IVdata))ROM_AESTABLE[22]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the CAN API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntClr))ROM_CANTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANInit \ + ((void (*)(uint32_t ui32Base))ROM_CANTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANEnable \ + ((void (*)(uint32_t ui32Base))ROM_CANTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANDisable \ + ((void (*)(uint32_t ui32Base))ROM_CANTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANBitTimingSet \ + ((void (*)(uint32_t ui32Base, \ + tCANBitClkParms *psClkParms))ROM_CANTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANBitTimingGet \ + ((void (*)(uint32_t ui32Base, \ + tCANBitClkParms *psClkParms))ROM_CANTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANMessageSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32ObjID, \ + tCANMsgObject *psMsgObject, \ + tMsgObjType eMsgType))ROM_CANTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANMessageGet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32ObjID, \ + tCANMsgObject *psMsgObject, \ + bool bClrPendingInt))ROM_CANTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANStatusGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + tCANStsReg eStatusReg))ROM_CANTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANMessageClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32ObjID))ROM_CANTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_CANTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_CANTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + tCANIntStsReg eIntStsReg))ROM_CANTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANRetryGet \ + ((bool (*)(uint32_t ui32Base))ROM_CANTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANRetrySet \ + ((void (*)(uint32_t ui32Base, \ + bool bAutoRetry))ROM_CANTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANErrCntrGet \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32RxCount, \ + uint32_t *pui32TxCount))ROM_CANTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANBitRateSet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32SourceClock, \ + uint32_t ui32BitRate))ROM_CANTABLE[16]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Comparator API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ComparatorIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Comp))ROM_COMPARATORTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ComparatorConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Comp, \ + uint32_t ui32Config))ROM_COMPARATORTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ComparatorRefSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Ref))ROM_COMPARATORTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ComparatorValueGet \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t ui32Comp))ROM_COMPARATORTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ComparatorIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Comp))ROM_COMPARATORTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ComparatorIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Comp))ROM_COMPARATORTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ComparatorIntStatus \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t ui32Comp, \ + bool bMasked))ROM_COMPARATORTABLE[6]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the CRC API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CRCConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CRCConfig))ROM_CRCTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CRCDataProcess \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t *pui32DataIn, \ + uint32_t ui32DataLength, \ + bool bPPResult))ROM_CRCTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CRCDataWrite \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Data))ROM_CRCTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CRCResultRead \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bPPResult))ROM_CRCTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CRCSeedSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Seed))ROM_CRCTABLE[4]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the DES API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_DESTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_DESTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESDataRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Dest))ROM_DESTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESDataReadNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Dest))ROM_DESTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESDataProcess \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Src, \ + uint32_t *pui32Dest, \ + uint32_t ui32Length))ROM_DESTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESDataWrite \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Src))ROM_DESTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESDataWriteNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Src))ROM_DESTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESDMADisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Flags))ROM_DESTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESDMAEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Flags))ROM_DESTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_DESTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_DESTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_DESTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESIVSet \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32IVdata))ROM_DESTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESKeySet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Key))ROM_DESTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESLengthSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Length))ROM_DESTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESReset \ + ((void (*)(uint32_t ui32Base))ROM_DESTABLE[15]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the EEPROM API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMRead \ + ((void (*)(uint32_t *pui32Data, \ + uint32_t ui32Address, \ + uint32_t ui32Count))ROM_EEPROMTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMBlockCountGet \ + ((uint32_t (*)(void))ROM_EEPROMTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMBlockHide \ + ((void (*)(uint32_t ui32Block))ROM_EEPROMTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMBlockLock \ + ((uint32_t (*)(uint32_t ui32Block))ROM_EEPROMTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMBlockPasswordSet \ + ((uint32_t (*)(uint32_t ui32Block, \ + uint32_t *pui32Password, \ + uint32_t ui32Count))ROM_EEPROMTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMBlockProtectGet \ + ((uint32_t (*)(uint32_t ui32Block))ROM_EEPROMTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMBlockProtectSet \ + ((uint32_t (*)(uint32_t ui32Block, \ + uint32_t ui32Protect))ROM_EEPROMTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMBlockUnlock \ + ((uint32_t (*)(uint32_t ui32Block, \ + uint32_t *pui32Password, \ + uint32_t ui32Count))ROM_EEPROMTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMIntClear \ + ((void (*)(uint32_t ui32IntFlags))ROM_EEPROMTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMIntDisable \ + ((void (*)(uint32_t ui32IntFlags))ROM_EEPROMTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMIntEnable \ + ((void (*)(uint32_t ui32IntFlags))ROM_EEPROMTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMIntStatus \ + ((uint32_t (*)(bool bMasked))ROM_EEPROMTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) +#define ROM_EEPROMMassErase \ + ((uint32_t (*)(void))ROM_EEPROMTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMProgram \ + ((uint32_t (*)(uint32_t *pui32Data, \ + uint32_t ui32Address, \ + uint32_t ui32Count))ROM_EEPROMTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMProgramNonBlocking \ + ((uint32_t (*)(uint32_t ui32Data, \ + uint32_t ui32Address))ROM_EEPROMTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMSizeGet \ + ((uint32_t (*)(void))ROM_EEPROMTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMStatusGet \ + ((uint32_t (*)(void))ROM_EEPROMTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMInit \ + ((uint32_t (*)(void))ROM_EEPROMTABLE[17]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the EPI API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_EPITABLE[0]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIModeSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Mode))ROM_EPITABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIDividerSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Divider))ROM_EPITABLE[2]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIConfigSDRAMSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config, \ + uint32_t ui32Refresh))ROM_EPITABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIConfigGPModeSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config, \ + uint32_t ui32FrameCount, \ + uint32_t ui32MaxWait))ROM_EPITABLE[4]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIConfigHB8Set \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config, \ + uint32_t ui32MaxWait))ROM_EPITABLE[5]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIConfigHB16Set \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config, \ + uint32_t ui32MaxWait))ROM_EPITABLE[6]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIAddressMapSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Map))ROM_EPITABLE[7]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPINonBlockingReadConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel, \ + uint32_t ui32DataSize, \ + uint32_t ui32Address))ROM_EPITABLE[8]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPINonBlockingReadStart \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel, \ + uint32_t ui32Count))ROM_EPITABLE[9]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPINonBlockingReadStop \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel))ROM_EPITABLE[10]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPINonBlockingReadCount \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Channel))ROM_EPITABLE[11]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPINonBlockingReadAvail \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EPITABLE[12]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPINonBlockingReadGet32 \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Count, \ + uint32_t *pui32Buf))ROM_EPITABLE[13]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPINonBlockingReadGet16 \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Count, \ + uint16_t *pui16Buf))ROM_EPITABLE[14]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPINonBlockingReadGet8 \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Count, \ + uint8_t *pui8Buf))ROM_EPITABLE[15]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIFIFOConfig \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_EPITABLE[16]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIWriteFIFOCountGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EPITABLE[17]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_EPITABLE[18]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_EPITABLE[19]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIIntErrorStatus \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EPITABLE[20]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIIntErrorClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32ErrFlags))ROM_EPITABLE[21]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIDividerCSSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint32_t ui32Divider))ROM_EPITABLE[22]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIDMATxCount \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Count))ROM_EPITABLE[23]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIConfigHB8CSSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint32_t ui32Config))ROM_EPITABLE[24]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIConfigHB16CSSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint32_t ui32Config))ROM_EPITABLE[25]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIConfigHB8TimingSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint32_t ui32Config))ROM_EPITABLE[26]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIConfigHB16TimingSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint32_t ui32Config))ROM_EPITABLE[27]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIPSRAMConfigRegSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint32_t ui32CR))ROM_EPITABLE[28]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIPSRAMConfigRegRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS))ROM_EPITABLE[29]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIPSRAMConfigRegGetNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint32_t *pui32CR))ROM_EPITABLE[30]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIPSRAMConfigRegGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32CS))ROM_EPITABLE[31]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the EMAC API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_EMACTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACAddrGet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Index, \ + uint8_t *pui8MACAddr))ROM_EMACTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACAddrSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Index, \ + const uint8_t *pui8MACAddr))ROM_EMACTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACConfigGet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Config, \ + uint32_t *pui32Mode, \ + uint32_t *pui32RxMaxFrameSize))ROM_EMACTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config, \ + uint32_t ui32ModeFlags, \ + uint32_t ui32RxMaxFrameSize))ROM_EMACTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACDMAStateGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACFrameFilterGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACFrameFilterSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32FilterOpts))ROM_EMACTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACInit \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SysClk, \ + uint32_t ui32BusConfig, \ + uint32_t ui32RxBurst, \ + uint32_t ui32TxBurst, \ + uint32_t ui32DescSkipSize))ROM_EMACTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_EMACTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_EMACTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_EMACTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPHYConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_EMACTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPHYPowerOff \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8PhyAddr))ROM_EMACTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPHYPowerOn \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8PhyAddr))ROM_EMACTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPHYRead \ + ((uint16_t (*)(uint32_t ui32Base, \ + uint8_t ui8PhyAddr, \ + uint8_t ui8RegAddr))ROM_EMACTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPHYWrite \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8PhyAddr, \ + uint8_t ui8RegAddr, \ + uint16_t ui16Data))ROM_EMACTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACReset \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRxDisable \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRxDMACurrentBufferGet \ + ((uint8_t * (*)(uint32_t ui32Base))ROM_EMACTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRxDMACurrentDescriptorGet \ + ((tEMACDMADescriptor * (*)(uint32_t ui32Base))ROM_EMACTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRxDMADescriptorListGet \ + ((tEMACDMADescriptor * (*)(uint32_t ui32Base))ROM_EMACTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRxDMADescriptorListSet \ + ((void (*)(uint32_t ui32Base, \ + tEMACDMADescriptor *pDescriptor))ROM_EMACTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRxDMAPollDemand \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRxEnable \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRxWatchdogTimerSet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Timeout))ROM_EMACTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACStatusGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTxDisable \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[27]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTxDMACurrentBufferGet \ + ((uint8_t * (*)(uint32_t ui32Base))ROM_EMACTABLE[28]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTxDMACurrentDescriptorGet \ + ((tEMACDMADescriptor * (*)(uint32_t ui32Base))ROM_EMACTABLE[29]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTxDMADescriptorListGet \ + ((tEMACDMADescriptor * (*)(uint32_t ui32Base))ROM_EMACTABLE[30]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTxDMADescriptorListSet \ + ((void (*)(uint32_t ui32Base, \ + tEMACDMADescriptor *pDescriptor))ROM_EMACTABLE[31]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTxDMAPollDemand \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[32]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTxEnable \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[33]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTxFlush \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[34]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACAddrFilterGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Index))ROM_EMACTABLE[35]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACAddrFilterSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Index, \ + uint32_t ui32Config))ROM_EMACTABLE[36]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACHashFilterBitCalculate \ + ((uint32_t (*)(uint8_t *pui8MACAddr))ROM_EMACTABLE[37]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACHashFilterGet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32HashHi, \ + uint32_t *pui32HashLo))ROM_EMACTABLE[38]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACHashFilterSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32HashHi, \ + uint32_t ui32HashLo))ROM_EMACTABLE[39]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACNumAddrGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[40]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPHYExtendedRead \ + ((uint16_t (*)(uint32_t ui32Base, \ + uint8_t ui8PhyAddr, \ + uint16_t ui16RegAddr))ROM_EMACTABLE[41]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPHYExtendedWrite \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8PhyAddr, \ + uint16_t ui16RegAddr, \ + uint16_t ui16Data))ROM_EMACTABLE[42]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPowerManagementControlGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[43]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPowerManagementControlSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Flags))ROM_EMACTABLE[44]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPowerManagementStatusGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[45]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRemoteWakeUpFrameFilterGet \ + ((void (*)(uint32_t ui32Base, \ + tEMACWakeUpFrameFilter *pFilter))ROM_EMACTABLE[46]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRemoteWakeUpFrameFilterSet \ + ((void (*)(uint32_t ui32Base, \ + const tEMACWakeUpFrameFilter *pFilter))ROM_EMACTABLE[47]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampAddendSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Seconds))ROM_EMACTABLE[48]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampConfigGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t *pui32SubSecondInc))ROM_EMACTABLE[49]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config, \ + uint32_t ui32SubSecondInc))ROM_EMACTABLE[50]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampDisable \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[51]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampEnable \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[52]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampIntStatus \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[53]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampPPSCommand \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Cmd))ROM_EMACTABLE[54]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampPPSCommandModeSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_EMACTABLE[55]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampPPSPeriodSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Period, \ + uint32_t ui32Width))ROM_EMACTABLE[56]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampPPSSimpleModeSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32FreqConfig))ROM_EMACTABLE[57]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampSysTimeGet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Seconds, \ + uint32_t *pui32SubSeconds))ROM_EMACTABLE[58]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampSysTimeSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Seconds, \ + uint32_t ui32SubSeconds))ROM_EMACTABLE[59]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampSysTimeUpdate \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Seconds, \ + uint32_t ui32SubSeconds, \ + bool bInc))ROM_EMACTABLE[60]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampTargetIntDisable \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[61]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampTargetIntEnable \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[62]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampTargetSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Seconds, \ + uint32_t ui32Nanoseconds))ROM_EMACTABLE[63]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACVLANHashFilterBitCalculate \ + ((uint32_t (*)(uint16_t ui16Tag))ROM_EMACTABLE[64]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACVLANHashFilterGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[65]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACVLANHashFilterSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Hash))ROM_EMACTABLE[66]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACVLANRxConfigGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint16_t *pui16Tag))ROM_EMACTABLE[67]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACVLANRxConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint16_t ui16Tag, \ + uint32_t ui32Config))ROM_EMACTABLE[68]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACVLANTxConfigGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint16_t *pui16Tag))ROM_EMACTABLE[69]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACVLANTxConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint16_t ui16Tag, \ + uint32_t ui32Config))ROM_EMACTABLE[70]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UpdateEMAC \ + ((void (*)(uint32_t ui32Clock))ROM_EMACTABLE[71]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Flash API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashProgram \ + ((int32_t (*)(uint32_t *pui32Data, \ + uint32_t ui32Address, \ + uint32_t ui32Count))ROM_FLASHTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashErase \ + ((int32_t (*)(uint32_t ui32Address))ROM_FLASHTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashProtectGet \ + ((tFlashProtection (*)(uint32_t ui32Address))ROM_FLASHTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashProtectSet \ + ((int32_t (*)(uint32_t ui32Address, \ + tFlashProtection eProtect))ROM_FLASHTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashProtectSave \ + ((int32_t (*)(void))ROM_FLASHTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashUserGet \ + ((int32_t (*)(uint32_t *pui32User0, \ + uint32_t *pui32User1))ROM_FLASHTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashUserSet \ + ((int32_t (*)(uint32_t ui32User0, \ + uint32_t ui32User1))ROM_FLASHTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashUserSave \ + ((int32_t (*)(void))ROM_FLASHTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashIntEnable \ + ((void (*)(uint32_t ui32IntFlags))ROM_FLASHTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashIntDisable \ + ((void (*)(uint32_t ui32IntFlags))ROM_FLASHTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashIntStatus \ + ((uint32_t (*)(bool bMasked))ROM_FLASHTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashIntClear \ + ((void (*)(uint32_t ui32IntFlags))ROM_FLASHTABLE[13]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the FPU API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FPUEnable \ + ((void (*)(void))ROM_FPUTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FPUDisable \ + ((void (*)(void))ROM_FPUTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FPUFlushToZeroModeSet \ + ((void (*)(uint32_t ui32Mode))ROM_FPUTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FPUHalfPrecisionModeSet \ + ((void (*)(uint32_t ui32Mode))ROM_FPUTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FPULazyStackingEnable \ + ((void (*)(void))ROM_FPUTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FPUNaNModeSet \ + ((void (*)(uint32_t ui32Mode))ROM_FPUTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FPURoundingModeSet \ + ((void (*)(uint32_t ui32Mode))ROM_FPUTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FPUStackingDisable \ + ((void (*)(void))ROM_FPUTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FPUStackingEnable \ + ((void (*)(void))ROM_FPUTABLE[8]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the GPIO API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinWrite \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins, \ + uint8_t ui8Val))ROM_GPIOTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIODirModeSet \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins, \ + uint32_t ui32PinIO))ROM_GPIOTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIODirModeGet \ + ((uint32_t (*)(uint32_t ui32Port, \ + uint8_t ui8Pin))ROM_GPIOTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOIntTypeSet \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins, \ + uint32_t ui32IntType))ROM_GPIOTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOIntTypeGet \ + ((uint32_t (*)(uint32_t ui32Port, \ + uint8_t ui8Pin))ROM_GPIOTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_GPIOPadConfigSet \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins, \ + uint32_t ui32Strength, \ + uint32_t ui32PadType))ROM_GPIOTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPadConfigGet \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pin, \ + uint32_t *pui32Strength, \ + uint32_t *pui32PadType))ROM_GPIOTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinRead \ + ((int32_t (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_GPIOPinTypeCAN \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeComparator \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeGPIOInput \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeGPIOOutput \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeI2C \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypePWM \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeQEI \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeSSI \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeTimer \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeUART \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeGPIOOutputOD \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeADC \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeUSBDigital \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinConfigure \ + ((void (*)(uint32_t ui32PinConfig))ROM_GPIOTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeUSBAnalog \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[28]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIODMATriggerEnable \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[31]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIODMATriggerDisable \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[32]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOADCTriggerEnable \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[33]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOADCTriggerDisable \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[34]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeI2CSCL \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[39]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeOneWire \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[44]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeWakeHigh \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[48]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeWakeLow \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[49]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOIntClear \ + ((void (*)(uint32_t ui32Port, \ + uint32_t ui32IntFlags))ROM_GPIOTABLE[51]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOIntDisable \ + ((void (*)(uint32_t ui32Port, \ + uint32_t ui32IntFlags))ROM_GPIOTABLE[52]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOIntEnable \ + ((void (*)(uint32_t ui32Port, \ + uint32_t ui32IntFlags))ROM_GPIOTABLE[53]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOIntStatus \ + ((uint32_t (*)(uint32_t ui32Port, \ + bool bMasked))ROM_GPIOTABLE[54]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Hibernate API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateIntClear \ + ((void (*)(uint32_t ui32IntFlags))ROM_HIBERNATETABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateEnableExpClk \ + ((void (*)(uint32_t ui32HibClk))ROM_HIBERNATETABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateDisable \ + ((void (*)(void))ROM_HIBERNATETABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCEnable \ + ((void (*)(void))ROM_HIBERNATETABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCDisable \ + ((void (*)(void))ROM_HIBERNATETABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateWakeSet \ + ((void (*)(uint32_t ui32WakeFlags))ROM_HIBERNATETABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateWakeGet \ + ((uint32_t (*)(void))ROM_HIBERNATETABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateLowBatSet \ + ((void (*)(uint32_t ui32LowBatFlags))ROM_HIBERNATETABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateLowBatGet \ + ((uint32_t (*)(void))ROM_HIBERNATETABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCSet \ + ((void (*)(uint32_t ui32RTCValue))ROM_HIBERNATETABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCGet \ + ((uint32_t (*)(void))ROM_HIBERNATETABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCTrimSet \ + ((void (*)(uint32_t ui32Trim))ROM_HIBERNATETABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCTrimGet \ + ((uint32_t (*)(void))ROM_HIBERNATETABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateDataSet \ + ((void (*)(uint32_t *pui32Data, \ + uint32_t ui32Count))ROM_HIBERNATETABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateDataGet \ + ((void (*)(uint32_t *pui32Data, \ + uint32_t ui32Count))ROM_HIBERNATETABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRequest \ + ((void (*)(void))ROM_HIBERNATETABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateIntEnable \ + ((void (*)(uint32_t ui32IntFlags))ROM_HIBERNATETABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateIntDisable \ + ((void (*)(uint32_t ui32IntFlags))ROM_HIBERNATETABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateIntStatus \ + ((uint32_t (*)(bool bMasked))ROM_HIBERNATETABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateIsActive \ + ((uint32_t (*)(void))ROM_HIBERNATETABLE[24]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCSSGet \ + ((uint32_t (*)(void))ROM_HIBERNATETABLE[27]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateClockConfig \ + ((void (*)(uint32_t ui32Config))ROM_HIBERNATETABLE[28]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateBatCheckStart \ + ((void (*)(void))ROM_HIBERNATETABLE[29]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateBatCheckDone \ + ((uint32_t (*)(void))ROM_HIBERNATETABLE[30]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateGPIORetentionEnable \ + ((void (*)(void))ROM_HIBERNATETABLE[31]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateGPIORetentionDisable \ + ((void (*)(void))ROM_HIBERNATETABLE[32]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateGPIORetentionGet \ + ((bool (*)(void))ROM_HIBERNATETABLE[33]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateCounterMode \ + ((void (*)(uint32_t ui32Config))ROM_HIBERNATETABLE[34]) +#endif +#if defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateCalendarSet \ + ((void (*)(struct tm *psTime))ROM_HIBERNATETABLE[35]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateCalendarGet \ + ((int (*)(struct tm *psTime))ROM_HIBERNATETABLE[36]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateCalendarMatchSet \ + ((void (*)(uint32_t ui32Index, \ + struct tm *psTime))ROM_HIBERNATETABLE[37]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateCalendarMatchGet \ + ((void (*)(uint32_t ui32Index, \ + struct tm *psTime))ROM_HIBERNATETABLE[38]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperDisable \ + ((void (*)(void))ROM_HIBERNATETABLE[39]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperEnable \ + ((void (*)(void))ROM_HIBERNATETABLE[40]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperEventsClear \ + ((void (*)(void))ROM_HIBERNATETABLE[41]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperEventsConfig \ + ((void (*)(uint32_t ui32Config))ROM_HIBERNATETABLE[42]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperEventsGet \ + ((bool (*)(uint32_t ui32Index, \ + uint32_t *pui32RTC, \ + uint32_t *pui32Event))ROM_HIBERNATETABLE[43]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperExtOscValid \ + ((bool (*)(void))ROM_HIBERNATETABLE[44]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperExtOscRecover \ + ((void (*)(void))ROM_HIBERNATETABLE[45]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperIODisable \ + ((void (*)(uint32_t ui32Input))ROM_HIBERNATETABLE[46]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperIOEnable \ + ((void (*)(uint32_t ui32Input, \ + uint32_t ui32Config))ROM_HIBERNATETABLE[47]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperStatusGet \ + ((uint32_t (*)(void))ROM_HIBERNATETABLE[48]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCMatchGet \ + ((uint32_t (*)(uint32_t ui32Match))ROM_HIBERNATETABLE[49]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCMatchSet \ + ((void (*)(uint32_t ui32Match, \ + uint32_t ui32Value))ROM_HIBERNATETABLE[50]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCSSMatchGet \ + ((uint32_t (*)(uint32_t ui32Match))ROM_HIBERNATETABLE[51]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCSSMatchSet \ + ((void (*)(uint32_t ui32Match, \ + uint32_t ui32Value))ROM_HIBERNATETABLE[52]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the I2C API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterDataPut \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Data))ROM_I2CTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterInitExpClk \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32I2CClk, \ + bool bFast))ROM_I2CTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveInit \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8SlaveAddr))ROM_I2CTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterEnable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveEnable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterDisable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveDisable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterIntEnable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveIntEnable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterIntDisable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveIntDisable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterIntStatus \ + ((bool (*)(uint32_t ui32Base, \ + bool bMasked))ROM_I2CTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveIntStatus \ + ((bool (*)(uint32_t ui32Base, \ + bool bMasked))ROM_I2CTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterIntClear \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveIntClear \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterSlaveAddrSet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8SlaveAddr, \ + bool bReceive))ROM_I2CTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterBusy \ + ((bool (*)(uint32_t ui32Base))ROM_I2CTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterBusBusy \ + ((bool (*)(uint32_t ui32Base))ROM_I2CTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterControl \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Cmd))ROM_I2CTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterErr \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterDataGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveStatus \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveDataPut \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Data))ROM_I2CTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveDataGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UpdateI2C \ + ((void (*)(void))ROM_I2CTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveIntEnableEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_I2CTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveIntDisableEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_I2CTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveIntStatusEx \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_I2CTABLE[27]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveIntClearEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_I2CTABLE[28]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterIntEnableEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_I2CTABLE[29]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterIntDisableEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_I2CTABLE[30]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterIntStatusEx \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_I2CTABLE[31]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterIntClearEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_I2CTABLE[32]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterTimeoutSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Value))ROM_I2CTABLE[33]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveACKOverride \ + ((void (*)(uint32_t ui32Base, \ + bool bEnable))ROM_I2CTABLE[34]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveACKValueSet \ + ((void (*)(uint32_t ui32Base, \ + bool bACK))ROM_I2CTABLE[35]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveAddressSet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8AddrNum, \ + uint8_t ui8SlaveAddr))ROM_I2CTABLE[37]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterLineStateGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[38]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CTxFIFOConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_I2CTABLE[39]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CTxFIFOFlush \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[40]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CRxFIFOConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_I2CTABLE[41]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CRxFIFOFlush \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[42]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CFIFOStatus \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[43]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CFIFODataPut \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Data))ROM_I2CTABLE[44]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CFIFODataPutNonBlocking \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint8_t ui8Data))ROM_I2CTABLE[45]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CFIFODataGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[46]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CFIFODataGetNonBlocking \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint8_t *pui8Data))ROM_I2CTABLE[47]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterBurstLengthSet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Length))ROM_I2CTABLE[48]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterBurstCountGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[49]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveFIFODisable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[50]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveFIFOEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_I2CTABLE[51]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterGlitchFilterConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_I2CTABLE[54]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Interrupt API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntEnable \ + ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntMasterEnable \ + ((bool (*)(void))ROM_INTERRUPTTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntMasterDisable \ + ((bool (*)(void))ROM_INTERRUPTTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntDisable \ + ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntPriorityGroupingSet \ + ((void (*)(uint32_t ui32Bits))ROM_INTERRUPTTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntPriorityGroupingGet \ + ((uint32_t (*)(void))ROM_INTERRUPTTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntPrioritySet \ + ((void (*)(uint32_t ui32Interrupt, \ + uint8_t ui8Priority))ROM_INTERRUPTTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntPriorityGet \ + ((int32_t (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntPendSet \ + ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntPendClear \ + ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntPriorityMaskSet \ + ((void (*)(uint32_t ui32PriorityMask))ROM_INTERRUPTTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntPriorityMaskGet \ + ((uint32_t (*)(void))ROM_INTERRUPTTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntIsEnabled \ + ((uint32_t (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntTrigger \ + ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[13]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the LCD API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_LCDTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDClockReset \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Clocks))ROM_LCDTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDDMAConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_LCDTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDCommandWrite \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint16_t ui16Cmd))ROM_LCDTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_LCDTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDDataRead \ + ((uint16_t (*)(uint32_t ui32Base, \ + uint32_t ui32CS))ROM_LCDTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDDataWrite \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint16_t ui16Data))ROM_LCDTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDDMADisable \ + ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDDMAWrite \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + const uint32_t *pui32Data, \ + uint32_t ui32Count))ROM_LCDTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDIndexedRead \ + ((uint16_t (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint16_t ui16Addr))ROM_LCDTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDIndexedWrite \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint16_t ui16Addr, \ + uint16_t ui16Data))ROM_LCDTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDStatusRead \ + ((uint16_t (*)(uint32_t ui32Base, \ + uint32_t ui32CS))ROM_LCDTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDTimingSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + const tLCDIDDTiming *pTiming))ROM_LCDTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_LCDTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_LCDTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_LCDTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDModeSet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint8_t ui8Mode, \ + uint32_t ui32PixClk, \ + uint32_t ui32SysClk))ROM_LCDTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterACBiasIntCountSet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Count))ROM_LCDTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config, \ + uint8_t ui8PalLoadDelay))ROM_LCDTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterDisable \ + ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterEnable \ + ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterFrameBufferSet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Buffer, \ + uint32_t *pui32Addr, \ + uint32_t ui32NumBytes))ROM_LCDTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterPaletteSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Type, \ + uint32_t *pui32PalAddr, \ + const uint32_t *pui32SrcColors, \ + uint32_t ui32Start, \ + uint32_t ui32Count))ROM_LCDTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterSubPanelConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Flags, \ + uint32_t ui32BottomLines, \ + uint32_t ui32DefaultPixel))ROM_LCDTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterSubPanelDisable \ + ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterSubPanelEnable \ + ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterTimingSet \ + ((void (*)(uint32_t ui32Base, \ + const tLCDRasterTiming *pTiming))ROM_LCDTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterEnabled \ + ((bool (*)(uint32_t ui32Base))ROM_LCDTABLE[27]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the MPU API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_MPUEnable \ + ((void (*)(uint32_t ui32MPUConfig))ROM_MPUTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_MPUDisable \ + ((void (*)(void))ROM_MPUTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_MPURegionCountGet \ + ((uint32_t (*)(void))ROM_MPUTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_MPURegionEnable \ + ((void (*)(uint32_t ui32Region))ROM_MPUTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_MPURegionDisable \ + ((void (*)(uint32_t ui32Region))ROM_MPUTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_MPURegionSet \ + ((void (*)(uint32_t ui32Region, \ + uint32_t ui32Addr, \ + uint32_t ui32Flags))ROM_MPUTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_MPURegionGet \ + ((void (*)(uint32_t ui32Region, \ + uint32_t *pui32Addr, \ + uint32_t *pui32Flags))ROM_MPUTABLE[6]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the OneWire API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_ONEWIRETABLE[0]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireBusReset \ + ((void (*)(uint32_t ui32Base))ROM_ONEWIRETABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireBusStatus \ + ((uint32_t (*)(uint32_t ui32Base))ROM_ONEWIRETABLE[2]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireDataGet \ + ((void (*)(uint32_t u3i2Base, \ + uint32_t *pui32Data))ROM_ONEWIRETABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireDataGetNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Data))ROM_ONEWIRETABLE[4]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireInit \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32InitFlags))ROM_ONEWIRETABLE[5]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_ONEWIRETABLE[6]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_ONEWIRETABLE[7]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_ONEWIRETABLE[8]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireTransaction \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32OpFlags, \ + uint32_t ui32Data, \ + uint32_t ui32BitCnt))ROM_ONEWIRETABLE[9]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireDMADisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32DMAFlags))ROM_ONEWIRETABLE[10]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireDMAEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32DMAFlags))ROM_ONEWIRETABLE[11]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the PWM API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMPulseWidthSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32PWMOut, \ + uint32_t ui32Width))ROM_PWMTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32Config))ROM_PWMTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenPeriodSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32Period))ROM_PWMTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenPeriodGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Gen))ROM_PWMTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen))ROM_PWMTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen))ROM_PWMTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMPulseWidthGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32PWMOut))ROM_PWMTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMDeadBandEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint16_t ui16Rise, \ + uint16_t ui16Fall))ROM_PWMTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMDeadBandDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen))ROM_PWMTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMSyncUpdate \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32GenBits))ROM_PWMTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMSyncTimeBase \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32GenBits))ROM_PWMTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMOutputState \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32PWMOutBits, \ + bool bEnable))ROM_PWMTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMOutputInvert \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32PWMOutBits, \ + bool bInvert))ROM_PWMTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMOutputFault \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32PWMOutBits, \ + bool bFaultSuppress))ROM_PWMTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenIntTrigEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32IntTrig))ROM_PWMTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenIntTrigDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32IntTrig))ROM_PWMTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + bool bMasked))ROM_PWMTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32Ints))ROM_PWMTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32GenFault))ROM_PWMTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32GenFault))ROM_PWMTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMFaultIntClear \ + ((void (*)(uint32_t ui32Base))ROM_PWMTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_PWMTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMOutputFaultLevel \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32PWMOutBits, \ + bool bDriveHigh))ROM_PWMTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMFaultIntClearExt \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32FaultInts))ROM_PWMTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenFaultConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32MinFaultPeriod, \ + uint32_t ui32FaultSenses))ROM_PWMTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenFaultTriggerSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32Group, \ + uint32_t ui32FaultTriggers))ROM_PWMTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenFaultTriggerGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32Group))ROM_PWMTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenFaultStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32Group))ROM_PWMTABLE[27]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenFaultClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32Group, \ + uint32_t ui32FaultTriggers))ROM_PWMTABLE[28]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMClockSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_PWMTABLE[29]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMClockGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_PWMTABLE[30]) +#endif +#if defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMOutputUpdateMode \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32PWMOutBits, \ + uint32_t ui32Mode))ROM_PWMTABLE[31]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the QEI API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIPositionGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_QEITABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIEnable \ + ((void (*)(uint32_t ui32Base))ROM_QEITABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIDisable \ + ((void (*)(uint32_t ui32Base))ROM_QEITABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config, \ + uint32_t ui32MaxPosition))ROM_QEITABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIPositionSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Position))ROM_QEITABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIDirectionGet \ + ((int32_t (*)(uint32_t ui32Base))ROM_QEITABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIErrorGet \ + ((bool (*)(uint32_t ui32Base))ROM_QEITABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIVelocityEnable \ + ((void (*)(uint32_t ui32Base))ROM_QEITABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIVelocityDisable \ + ((void (*)(uint32_t ui32Base))ROM_QEITABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIVelocityConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32PreDiv, \ + uint32_t ui32Period))ROM_QEITABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIVelocityGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_QEITABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_QEITABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_QEITABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_QEITABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_QEITABLE[14]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SHAMD5 API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5IntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_SHAMD5TABLE[0]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5ConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Mode))ROM_SHAMD5TABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5DataProcess \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32DataSrc, \ + uint32_t ui32DataLength, \ + uint32_t *pui32HashResult))ROM_SHAMD5TABLE[2]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5DataWrite \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Src))ROM_SHAMD5TABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5DataWriteNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Src))ROM_SHAMD5TABLE[4]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5DMADisable \ + ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[5]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5DMAEnable \ + ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[6]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5HashLengthSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Length))ROM_SHAMD5TABLE[7]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5HMACKeySet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Src))ROM_SHAMD5TABLE[8]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5HMACPPKeyGenerate \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Key, \ + uint32_t *pui32PPKey))ROM_SHAMD5TABLE[9]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5HMACPPKeySet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Src))ROM_SHAMD5TABLE[10]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5HMACProcess \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32DataSrc, \ + uint32_t ui32DataLength, \ + uint32_t *pui32HashResult))ROM_SHAMD5TABLE[11]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5IntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_SHAMD5TABLE[12]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5IntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_SHAMD5TABLE[13]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5IntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_SHAMD5TABLE[14]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5Reset \ + ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[15]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5ResultRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Dest))ROM_SHAMD5TABLE[16]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SMBus API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterIntProcess \ + ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusARPDisable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusARPEnable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusARPUDIDPacketDecode \ + ((void (*)(tSMBusUDID *pUDID, \ + uint8_t *pui8Address, \ + uint8_t *pui8Data))ROM_SMBUSTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusARPUDIDPacketEncode \ + ((void (*)(tSMBusUDID *pUDID, \ + uint8_t ui8Address, \ + uint8_t *pui8Data))ROM_SMBUSTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterARPAssignAddress \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t *pui8Data))ROM_SMBUSTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterARPGetUDIDDir \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t *pui8Data))ROM_SMBUSTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterARPGetUDIDGen \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t *pui8Data))ROM_SMBUSTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterARPNotifyMaster \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t *pui8Data))ROM_SMBUSTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterARPPrepareToARP \ + ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterARPResetDeviceDir \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress))ROM_SMBUSTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterARPResetDeviceGen \ + ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterBlockProcessCall \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t ui8Command, \ + uint8_t *pui8TxData, \ + uint8_t ui8TxSize, \ + uint8_t *pui8RxData))ROM_SMBUSTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterBlockRead \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t ui8Command, \ + uint8_t *pui8Data))ROM_SMBUSTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterBlockWrite \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t ui8Command, \ + uint8_t *pui8Data, \ + uint8_t ui8Size))ROM_SMBUSTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterByteReceive \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t *pui8Data))ROM_SMBUSTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterByteSend \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t ui8Data))ROM_SMBUSTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterByteWordRead \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t ui8Command, \ + uint8_t *pui8Data, \ + uint8_t ui8Size))ROM_SMBUSTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterByteWordWrite \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t ui8Command, \ + uint8_t *pui8Data, \ + uint8_t ui8Size))ROM_SMBUSTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterHostNotify \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8OwnSlaveAddress, \ + uint8_t *pui8Data))ROM_SMBUSTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterI2CRead \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t *pui8Data, \ + uint8_t ui8Size))ROM_SMBUSTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterI2CWrite \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t *pui8Data, \ + uint8_t ui8Size))ROM_SMBUSTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterI2CWriteRead \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t *pui8TxData, \ + uint8_t ui8TxSize, \ + uint8_t *pui8RxData, \ + uint8_t ui8RxSize))ROM_SMBUSTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterInit \ + ((void (*)(tSMBus *psSMBus, \ + uint32_t ui32I2CBase, \ + uint32_t ui32SMBusClock))ROM_SMBUSTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterIntEnable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterProcessCall \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t ui8Command, \ + uint8_t *pui8TxData, \ + uint8_t *pui8RxData))ROM_SMBUSTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterQuickCommand \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + bool bData))ROM_SMBUSTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusPECDisable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[27]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusPECEnable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[28]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusRxPacketSizeGet \ + ((uint8_t (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[29]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveACKSend \ + ((void (*)(tSMBus *psSMBus, \ + bool bACK))ROM_SMBUSTABLE[30]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveAddressSet \ + ((void (*)(tSMBus *psSMBus, \ + uint8_t ui8AddressNum, \ + uint8_t ui8SlaveAddress))ROM_SMBUSTABLE[31]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveARPFlagARGet \ + ((bool (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[32]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveARPFlagARSet \ + ((void (*)(tSMBus *psSMBus, \ + bool bValue))ROM_SMBUSTABLE[33]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveARPFlagAVGet \ + ((bool (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[34]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveARPFlagAVSet \ + ((void (*)(tSMBus *psSMBus, \ + bool bValue))ROM_SMBUSTABLE[35]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveBlockTransferDisable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[36]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveBlockTransferEnable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[37]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveCommandGet \ + ((uint8_t (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[38]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveI2CDisable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[39]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveI2CEnable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[40]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveInit \ + ((void (*)(tSMBus *psSMBus, \ + uint32_t ui32I2CBase))ROM_SMBUSTABLE[41]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveIntAddressGet \ + ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[42]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveIntEnable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[43]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveIntProcess \ + ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[44]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveManualACKDisable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[45]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveManualACKEnable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[46]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveManualACKStatusGet \ + ((bool (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[47]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveProcessCallDisable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[48]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveProcessCallEnable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[49]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveRxBufferSet \ + ((void (*)(tSMBus *psSMBus, \ + uint8_t *pui8Data, \ + uint8_t ui8Size))ROM_SMBUSTABLE[50]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveTransferInit \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[51]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveTxBufferSet \ + ((void (*)(tSMBus *psSMBus, \ + uint8_t *pui8Data, \ + uint8_t ui8Size))ROM_SMBUSTABLE[52]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveUDIDSet \ + ((void (*)(tSMBus *psSMBus, \ + tSMBusUDID *pUDID))ROM_SMBUSTABLE[53]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusStatusGet \ + ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[54]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveDataSend \ + ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[55]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusFIFOEnable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[56]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusFIFODisable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[57]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusDMAEnable \ + ((void (*)(tSMBus *psSMBus, \ + uint8_t ui8TxChannel, \ + uint8_t ui8RxChannel))ROM_SMBUSTABLE[58]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusDMADisable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[59]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SPIFlash API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashIntHandler \ + ((uint32_t (*)(tSPIFlashState *pState))ROM_SPIFLASHTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashInit \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Clock, \ + uint32_t ui32BitRate))ROM_SPIFLASHTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashWriteStatus \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Status))ROM_SPIFLASHTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashPageProgram \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Addr, \ + const uint8_t *pui8Data, \ + uint32_t ui32Count))ROM_SPIFLASHTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashPageProgramNonBlocking \ + ((void (*)(tSPIFlashState *pState, \ + uint32_t ui32Base, \ + uint32_t ui32Addr, \ + const uint8_t *pui8Data, \ + uint32_t ui32Count, \ + bool bUseDMA, \ + uint32_t ui32TxChannel))ROM_SPIFLASHTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Addr, \ + uint8_t *pui8Data, \ + uint32_t ui32Count))ROM_SPIFLASHTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashReadNonBlocking \ + ((void (*)(tSPIFlashState *pState, \ + uint32_t ui32Base, \ + uint32_t ui32Addr, \ + uint8_t *pui8Data, \ + uint32_t ui32Count, \ + bool bUseDMA, \ + uint32_t ui32TxChannel, \ + uint32_t ui32RxChannel))ROM_SPIFLASHTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashWriteDisable \ + ((void (*)(uint32_t ui32Base))ROM_SPIFLASHTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashReadStatus \ + ((uint8_t (*)(uint32_t ui32Base))ROM_SPIFLASHTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashWriteEnable \ + ((void (*)(uint32_t ui32Base))ROM_SPIFLASHTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashFastRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Addr, \ + uint8_t *pui8Data, \ + uint32_t ui32Count))ROM_SPIFLASHTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashFastReadNonBlocking \ + ((void (*)(tSPIFlashState *pState, \ + uint32_t ui32Base, \ + uint32_t ui32Addr, \ + uint8_t *pui8Data, \ + uint32_t ui32Count, \ + bool bUseDMA, \ + uint32_t ui32TxChannel, \ + uint32_t ui32RxChannel))ROM_SPIFLASHTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashSectorErase \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Addr))ROM_SPIFLASHTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashDualRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Addr, \ + uint8_t *pui8Data, \ + uint32_t ui32Count))ROM_SPIFLASHTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashDualReadNonBlocking \ + ((void (*)(tSPIFlashState *pState, \ + uint32_t ui32Base, \ + uint32_t ui32Addr, \ + uint8_t *pui8Data, \ + uint32_t ui32Count, \ + bool bUseDMA, \ + uint32_t ui32TxChannel, \ + uint32_t ui32RxChannel))ROM_SPIFLASHTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashBlockErase32 \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Addr))ROM_SPIFLASHTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashQuadRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Addr, \ + uint8_t *pui8Data, \ + uint32_t ui32Count))ROM_SPIFLASHTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashQuadReadNonBlocking \ + ((void (*)(tSPIFlashState *pState, \ + uint32_t ui32Base, \ + uint32_t ui32Addr, \ + uint8_t *pui8Data, \ + uint32_t ui32Count, \ + bool bUseDMA, \ + uint32_t ui32TxChannel, \ + uint32_t ui32RxChannel))ROM_SPIFLASHTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashReadID \ + ((void (*)(uint32_t ui32Base, \ + uint8_t *pui8ManufacturerID, \ + uint16_t *pui16DeviceID))ROM_SPIFLASHTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashChipErase \ + ((void (*)(uint32_t ui32Base))ROM_SPIFLASHTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashBlockErase64 \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Addr))ROM_SPIFLASHTABLE[20]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SSI API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIDataPut \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Data))ROM_SSITABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIConfigSetExpClk \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SSIClk, \ + uint32_t ui32Protocol, \ + uint32_t ui32Mode, \ + uint32_t ui32BitRate, \ + uint32_t ui32DataWidth))ROM_SSITABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIEnable \ + ((void (*)(uint32_t ui32Base))ROM_SSITABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIDisable \ + ((void (*)(uint32_t ui32Base))ROM_SSITABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_SSITABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_SSITABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_SSITABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_SSITABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIDataPutNonBlocking \ + ((int32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Data))ROM_SSITABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIDataGet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Data))ROM_SSITABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIDataGetNonBlocking \ + ((int32_t (*)(uint32_t ui32Base, \ + uint32_t *pui32Data))ROM_SSITABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UpdateSSI \ + ((void (*)(void))ROM_SSITABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIDMAEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32DMAFlags))ROM_SSITABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIDMADisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32DMAFlags))ROM_SSITABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIBusy \ + ((bool (*)(uint32_t ui32Base))ROM_SSITABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIClockSourceGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_SSITABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIClockSourceSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Source))ROM_SSITABLE[16]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIAdvModeSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Mode))ROM_SSITABLE[17]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIAdvDataPutFrameEnd \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Data))ROM_SSITABLE[18]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIAdvDataPutFrameEndNonBlocking \ + ((int32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Data))ROM_SSITABLE[19]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIAdvFrameHoldEnable \ + ((void (*)(uint32_t ui32Base))ROM_SSITABLE[20]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIAdvFrameHoldDisable \ + ((void (*)(uint32_t ui32Base))ROM_SSITABLE[21]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SysCtl API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlSleep \ + ((void (*)(void))ROM_SYSCTLTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlSRAMSizeGet \ + ((uint32_t (*)(void))ROM_SYSCTLTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlFlashSizeGet \ + ((uint32_t (*)(void))ROM_SYSCTLTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralPresent \ + ((bool (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralReset \ + ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralEnable \ + ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralDisable \ + ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralSleepEnable \ + ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralSleepDisable \ + ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralDeepSleepEnable \ + ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralDeepSleepDisable \ + ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralClockGating \ + ((void (*)(bool bEnable))ROM_SYSCTLTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlIntEnable \ + ((void (*)(uint32_t ui32Ints))ROM_SYSCTLTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlIntDisable \ + ((void (*)(uint32_t ui32Ints))ROM_SYSCTLTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlIntClear \ + ((void (*)(uint32_t ui32Ints))ROM_SYSCTLTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlIntStatus \ + ((uint32_t (*)(bool bMasked))ROM_SYSCTLTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlReset \ + ((void (*)(void))ROM_SYSCTLTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlDeepSleep \ + ((void (*)(void))ROM_SYSCTLTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlResetCauseGet \ + ((uint32_t (*)(void))ROM_SYSCTLTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlResetCauseClear \ + ((void (*)(uint32_t ui32Causes))ROM_SYSCTLTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_SysCtlClockSet \ + ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_SysCtlClockGet \ + ((uint32_t (*)(void))ROM_SYSCTLTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_SysCtlPWMClockSet \ + ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_SysCtlPWMClockGet \ + ((uint32_t (*)(void))ROM_SYSCTLTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_SysCtlUSBPLLEnable \ + ((void (*)(void))ROM_SYSCTLTABLE[31]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_SysCtlUSBPLLDisable \ + ((void (*)(void))ROM_SYSCTLTABLE[32]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlDelay \ + ((void (*)(uint32_t ui32Count))ROM_SYSCTLTABLE[34]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralReady \ + ((bool (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[35]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralPowerOn \ + ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[36]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralPowerOff \ + ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[37]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlMOSCConfigSet \ + ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[44]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPIOSCCalibrate \ + ((uint32_t (*)(uint32_t ui32Type))ROM_SYSCTLTABLE[45]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_SysCtlDeepSleepClockSet \ + ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[46]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlDeepSleepClockConfigSet \ + ((void (*)(uint32_t ui32Div, \ + uint32_t ui32Config))ROM_SYSCTLTABLE[47]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlResetBehaviorSet \ + ((void (*)(uint32_t ui32Behavior))ROM_SYSCTLTABLE[51]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlResetBehaviorGet \ + ((uint32_t (*)(void))ROM_SYSCTLTABLE[52]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlFlashSectorSizeGet \ + ((uint32_t (*)(void))ROM_SYSCTLTABLE[54]) +#endif +#if defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlVoltageEventConfig \ + ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[55]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlVoltageEventStatus \ + ((uint32_t (*)(void))ROM_SYSCTLTABLE[56]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlVoltageEventClear \ + ((void (*)(uint32_t ui32Status))ROM_SYSCTLTABLE[57]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlNMIStatus \ + ((uint32_t (*)(void))ROM_SYSCTLTABLE[58]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlNMIClear \ + ((void (*)(uint32_t ui32Status))ROM_SYSCTLTABLE[59]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlClockOutConfig \ + ((void (*)(uint32_t ui32Config, \ + uint32_t ui32Div))ROM_SYSCTLTABLE[60]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlAltClkConfig \ + ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[61]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SysExc API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysExcIntStatus \ + ((uint32_t (*)(bool bMasked))ROM_SYSEXCTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysExcIntClear \ + ((void (*)(uint32_t ui32IntFlags))ROM_SYSEXCTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysExcIntDisable \ + ((void (*)(uint32_t ui32IntFlags))ROM_SYSEXCTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysExcIntEnable \ + ((void (*)(uint32_t ui32IntFlags))ROM_SYSEXCTABLE[3]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SysTick API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysTickValueGet \ + ((uint32_t (*)(void))ROM_SYSTICKTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysTickEnable \ + ((void (*)(void))ROM_SYSTICKTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysTickDisable \ + ((void (*)(void))ROM_SYSTICKTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysTickIntEnable \ + ((void (*)(void))ROM_SYSTICKTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysTickIntDisable \ + ((void (*)(void))ROM_SYSTICKTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysTickPeriodSet \ + ((void (*)(uint32_t ui32Period))ROM_SYSTICKTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysTickPeriodGet \ + ((uint32_t (*)(void))ROM_SYSTICKTABLE[6]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Timer API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_TIMERTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer))ROM_TIMERTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer))ROM_TIMERTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_TIMERTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerControlLevel \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer, \ + bool bInvert))ROM_TIMERTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA1) +#define ROM_TimerControlTrigger \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer, \ + bool bEnable))ROM_TIMERTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerControlEvent \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer, \ + uint32_t ui32Event))ROM_TIMERTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerControlStall \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer, \ + bool bStall))ROM_TIMERTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerRTCEnable \ + ((void (*)(uint32_t ui32Base))ROM_TIMERTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerRTCDisable \ + ((void (*)(uint32_t ui32Base))ROM_TIMERTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerPrescaleSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer, \ + uint32_t ui32Value))ROM_TIMERTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerPrescaleGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Timer))ROM_TIMERTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerPrescaleMatchSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer, \ + uint32_t ui32Value))ROM_TIMERTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerPrescaleMatchGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Timer))ROM_TIMERTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerLoadSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer, \ + uint32_t ui32Value))ROM_TIMERTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerLoadGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Timer))ROM_TIMERTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerValueGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Timer))ROM_TIMERTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerMatchSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer, \ + uint32_t ui32Value))ROM_TIMERTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerMatchGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Timer))ROM_TIMERTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_TIMERTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_TIMERTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_TIMERTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerControlWaitOnTrigger \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer, \ + bool bWait))ROM_TIMERTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_TimerLoadSet64 \ + ((void (*)(uint32_t ui32Base, \ + uint64_t ui64Value))ROM_TIMERTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_TimerLoadGet64 \ + ((uint64_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_TimerValueGet64 \ + ((uint64_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_TimerMatchSet64 \ + ((void (*)(uint32_t ui32Base, \ + uint64_t ui64Value))ROM_TIMERTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_TimerMatchGet64 \ + ((uint64_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[27]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerClockSourceGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[28]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerClockSourceSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Source))ROM_TIMERTABLE[29]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerADCEventGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[30]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerADCEventSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32ADCEvent))ROM_TIMERTABLE[31]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerDMAEventGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[32]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerDMAEventSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32DMAEvent))ROM_TIMERTABLE[33]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerSynchronize \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timers))ROM_TIMERTABLE[34]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the UART API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTCharPut \ + ((void (*)(uint32_t ui32Base, \ + unsigned char ucData))ROM_UARTTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTParityModeSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Parity))ROM_UARTTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTParityModeGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTFIFOLevelSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32TxLevel, \ + uint32_t ui32RxLevel))ROM_UARTTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTFIFOLevelGet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32TxLevel, \ + uint32_t *pui32RxLevel))ROM_UARTTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTConfigSetExpClk \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32UARTClk, \ + uint32_t ui32Baud, \ + uint32_t ui32Config))ROM_UARTTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTConfigGetExpClk \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32UARTClk, \ + uint32_t *pui32Baud, \ + uint32_t *pui32Config))ROM_UARTTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTEnable \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTDisable \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTEnableSIR \ + ((void (*)(uint32_t ui32Base, \ + bool bLowPower))ROM_UARTTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTDisableSIR \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTCharsAvail \ + ((bool (*)(uint32_t ui32Base))ROM_UARTTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTSpaceAvail \ + ((bool (*)(uint32_t ui32Base))ROM_UARTTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTCharGetNonBlocking \ + ((int32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTCharGet \ + ((int32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTCharPutNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + unsigned char ucData))ROM_UARTTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTBreakCtl \ + ((void (*)(uint32_t ui32Base, \ + bool bBreakState))ROM_UARTTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_UARTTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_UARTTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_UARTTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_UARTTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UpdateUART \ + ((void (*)(void))ROM_UARTTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTDMAEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32DMAFlags))ROM_UARTTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTDMADisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32DMAFlags))ROM_UARTTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTFIFOEnable \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTFIFODisable \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTBusy \ + ((bool (*)(uint32_t ui32Base))ROM_UARTTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTTxIntModeSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Mode))ROM_UARTTABLE[27]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTTxIntModeGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[28]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTRxErrorGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[29]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTRxErrorClear \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[30]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTClockSourceSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Source))ROM_UARTTABLE[31]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTClockSourceGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[32]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UART9BitEnable \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[33]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UART9BitDisable \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[34]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UART9BitAddrSet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Addr, \ + uint8_t ui8Mask))ROM_UARTTABLE[35]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UART9BitAddrSend \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Addr))ROM_UARTTABLE[36]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTSmartCardDisable \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[37]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTSmartCardEnable \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[38]) +#endif +#if defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTModemControlClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Control))ROM_UARTTABLE[39]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTModemControlGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[40]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTModemControlSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Control))ROM_UARTTABLE[41]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTModemStatusGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[42]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTFlowControlGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[43]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTFlowControlSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Mode))ROM_UARTTABLE[44]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the uDMA API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelTransferSet \ + ((void (*)(uint32_t ui32ChannelStructIndex, \ + uint32_t ui32Mode, \ + void *pvSrcAddr, \ + void *pvDstAddr, \ + uint32_t ui32TransferSize))ROM_UDMATABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAEnable \ + ((void (*)(void))ROM_UDMATABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMADisable \ + ((void (*)(void))ROM_UDMATABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAErrorStatusGet \ + ((uint32_t (*)(void))ROM_UDMATABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAErrorStatusClear \ + ((void (*)(void))ROM_UDMATABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelEnable \ + ((void (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelDisable \ + ((void (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelIsEnabled \ + ((bool (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAControlBaseSet \ + ((void (*)(void *pControlTable))ROM_UDMATABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAControlBaseGet \ + ((void * (*)(void))ROM_UDMATABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelRequest \ + ((void (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelAttributeEnable \ + ((void (*)(uint32_t ui32ChannelNum, \ + uint32_t ui32Attr))ROM_UDMATABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelAttributeDisable \ + ((void (*)(uint32_t ui32ChannelNum, \ + uint32_t ui32Attr))ROM_UDMATABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelAttributeGet \ + ((uint32_t (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelControlSet \ + ((void (*)(uint32_t ui32ChannelStructIndex, \ + uint32_t ui32Control))ROM_UDMATABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelSizeGet \ + ((uint32_t (*)(uint32_t ui32ChannelStructIndex))ROM_UDMATABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelModeGet \ + ((uint32_t (*)(uint32_t ui32ChannelStructIndex))ROM_UDMATABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelSelectSecondary \ + ((void (*)(uint32_t ui32SecPeriphs))ROM_UDMATABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelSelectDefault \ + ((void (*)(uint32_t ui32DefPeriphs))ROM_UDMATABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAIntStatus \ + ((uint32_t (*)(void))ROM_UDMATABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAIntClear \ + ((void (*)(uint32_t ui32ChanMask))ROM_UDMATABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAControlAlternateBaseGet \ + ((void * (*)(void))ROM_UDMATABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelScatterGatherSet \ + ((void (*)(uint32_t ui32ChannelNum, \ + uint32_t ui32TaskCount, \ + void *pvTaskList, \ + uint32_t ui32IsPeriphSG))ROM_UDMATABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelAssign \ + ((void (*)(uint32_t ui32Mapping))ROM_UDMATABLE[23]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the USB API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevAddrGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevAddrSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Address))ROM_USBTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevConnect \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevDisconnect \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevEndpointConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32MaxPacketSize, \ + uint32_t ui32Flags))ROM_USBTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevEndpointDataAck \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + bool bIsLastPacket))ROM_USBTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevEndpointStall \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevEndpointStallClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevEndpointStatusClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointDataGet \ + ((int32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint8_t *pui8Data, \ + uint32_t *pui32Size))ROM_USBTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointDataPut \ + ((int32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint8_t *pui8Data, \ + uint32_t ui32Size))ROM_USBTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointDataSend \ + ((int32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32TransType))ROM_USBTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointDataToggleClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint))ROM_USBTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBFIFOAddrGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint))ROM_USBTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBFIFOConfigGet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t *pui32FIFOAddress, \ + uint32_t *pui32FIFOSize, \ + uint32_t ui32Flags))ROM_USBTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBFIFOConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32FIFOAddress, \ + uint32_t ui32FIFOSize, \ + uint32_t ui32Flags))ROM_USBTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBFIFOFlush \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBFrameNumberGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostAddrGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostAddrSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Addr, \ + uint32_t ui32Flags))ROM_USBTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostEndpointConfig \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32MaxPacketSize, \ + uint32_t ui32NAKPollInterval, \ + uint32_t ui32TargetEndpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostEndpointDataAck \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint))ROM_USBTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostEndpointDataToggle \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + bool bDataToggle, \ + uint32_t ui32Flags))ROM_USBTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostEndpointStatusClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostHubAddrGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostHubAddrSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Addr, \ + uint32_t ui32Flags))ROM_USBTABLE[27]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostPwrDisable \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[28]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostPwrEnable \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[29]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostPwrConfig \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Flags))ROM_USBTABLE[30]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostPwrFaultDisable \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[31]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostPwrFaultEnable \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[32]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostRequestIN \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint))ROM_USBTABLE[33]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostRequestStatus \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[34]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostReset \ + ((void (*)(uint32_t ui32Base, \ + bool bStart))ROM_USBTABLE[35]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostResume \ + ((void (*)(uint32_t ui32Base, \ + bool bStart))ROM_USBTABLE[36]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostSpeedGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[37]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostSuspend \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[38]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevEndpointConfigGet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t *pui32MaxPacketSize, \ + uint32_t *pui32Flags))ROM_USBTABLE[41]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointDMAEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[42]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointDMADisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[43]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointDataAvail \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint))ROM_USBTABLE[44]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBModeGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[46]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointDMAChannel \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Channel))ROM_USBTABLE[47]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBIntDisableControl \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_USBTABLE[48]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBIntEnableControl \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_USBTABLE[49]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBIntStatusControl \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[50]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBIntDisableEndpoint \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_USBTABLE[51]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBIntEnableEndpoint \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_USBTABLE[52]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBIntStatusEndpoint \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[53]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostMode \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[54]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevMode \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[55]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBPHYPowerOff \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[56]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBPHYPowerOn \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[57]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UpdateUSB \ + ((void (*)(uint8_t *pui8DescriptorInfo))ROM_USBTABLE[58]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBOTGMode \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[59]) +#endif +#if defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostRequestINClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint))ROM_USBTABLE[60]) +#endif +#if defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBNumEndpointsGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[61]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBClockDisable \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[62]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBClockEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Div, \ + uint32_t ui32Flags))ROM_USBTABLE[63]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBControllerVersion \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[64]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevLPMConfig \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_USBTABLE[65]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevLPMDisable \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[66]) +#endif +#if defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevLPMEnable \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[67]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevLPMRemoteWake \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[68]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevSpeedGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[69]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelAddressGet \ + ((void * (*)(uint32_t ui32Base, \ + uint32_t ui32Channel))ROM_USBTABLE[70]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelAddressSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel, \ + void *pvAddress))ROM_USBTABLE[71]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Config))ROM_USBTABLE[72]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel))ROM_USBTABLE[73]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel))ROM_USBTABLE[74]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel))ROM_USBTABLE[75]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel))ROM_USBTABLE[76]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelCountGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Channel))ROM_USBTABLE[77]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelCountSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Count, \ + uint32_t ui32Channel))ROM_USBTABLE[78]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelIntStatus \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[79]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Channel))ROM_USBTABLE[80]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelStatusClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel, \ + uint32_t ui32Status))ROM_USBTABLE[81]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHighSpeed \ + ((void (*)(uint32_t ui32Base, \ + bool bEnable))ROM_USBTABLE[82]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostEndpointPing \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + bool bEnable))ROM_USBTABLE[83]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostEndpointSpeed \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[84]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostLPMConfig \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32ResumeTime, \ + uint32_t ui32Config))ROM_USBTABLE[85]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostLPMResume \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[86]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostLPMSend \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Address, \ + uint32_t uiEndpoint))ROM_USBTABLE[87]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBLPMIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Ints))ROM_USBTABLE[88]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBLPMIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Ints))ROM_USBTABLE[89]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBLPMIntStatus \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[90]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBLPMLinkStateGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[91]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointPacketCountSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Count))ROM_USBTABLE[92]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBULPIConfig \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_USBTABLE[93]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBULPIDisable \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[94]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBULPIEnable \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[95]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBULPIRegRead \ + ((uint8_t (*)(uint32_t ui32Base, \ + uint8_t ui8Reg))ROM_USBTABLE[96]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBULPIRegWrite \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Reg, \ + uint8_t ui8Data))ROM_USBTABLE[97]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBOTGSessionRequest \ + ((void (*)(uint32_t ui32Base, \ + bool bStart))ROM_USBTABLE[98]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMANumChannels \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[99]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointDMAConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Config))ROM_USBTABLE[100]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBLPMRemoteWakeEnabled \ + ((bool (*)(uint32_t ui32Base))ROM_USBTABLE[102]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBModeConfig \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Mode))ROM_USBTABLE[103]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Watchdog API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogIntClear \ + ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogRunning \ + ((bool (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogEnable \ + ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogResetEnable \ + ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogResetDisable \ + ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogLock \ + ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogUnlock \ + ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogLockState \ + ((bool (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogReloadSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32LoadVal))ROM_WATCHDOGTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogReloadGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogValueGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogIntEnable \ + ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_WATCHDOGTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogStallEnable \ + ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogStallDisable \ + ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogIntTypeSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Type))ROM_WATCHDOGTABLE[15]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Software API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_Crc16Array \ + ((uint16_t (*)(uint32_t ui32WordLen, \ + const uint32_t *pui32Data))ROM_SOFTWARETABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_Crc16Array3 \ + ((void (*)(uint32_t ui32WordLen, \ + const uint32_t *pui32Data, \ + uint16_t *pui16Crc3))ROM_SOFTWARETABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_Crc16 \ + ((uint16_t (*)(uint16_t ui16Crc, \ + const uint8_t *pui8Data, \ + uint32_t ui32Count))ROM_SOFTWARETABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_Crc8CCITT \ + ((uint8_t (*)(uint8_t ui8Crc, \ + const uint8_t *pui8Data, \ + uint32_t ui32Count))ROM_SOFTWARETABLE[4]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_Crc32 \ + ((uint32_t (*)(uint32_t ui32Crc, \ + const uint8_t *pui8Data, \ + uint32_t ui32Count))ROM_SOFTWARETABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_pvAESTable \ + ((void *)&(ROM_SOFTWARETABLE[7])) +#endif + +#endif // __DRIVERLIB_ROM_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/rom_map.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/rom_map.h new file mode 100644 index 0000000000000000000000000000000000000000..e45ede445fb4ba4d04d63f5ca40886dd24d39c6f --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/rom_map.h @@ -0,0 +1,6409 @@ +//***************************************************************************** +// +// rom_map.h - Macros to facilitate calling functions in the ROM when they are +// available and in flash otherwise. +// +// Copyright (c) 2008-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_ROM_MAP_H__ +#define __DRIVERLIB_ROM_MAP_H__ + +//***************************************************************************** +// +// Macros for the ADC API. +// +//***************************************************************************** +#ifdef ROM_ADCSequenceDataGet +#define MAP_ADCSequenceDataGet \ + ROM_ADCSequenceDataGet +#else +#define MAP_ADCSequenceDataGet \ + ADCSequenceDataGet +#endif +#ifdef ROM_ADCIntDisable +#define MAP_ADCIntDisable \ + ROM_ADCIntDisable +#else +#define MAP_ADCIntDisable \ + ADCIntDisable +#endif +#ifdef ROM_ADCIntEnable +#define MAP_ADCIntEnable \ + ROM_ADCIntEnable +#else +#define MAP_ADCIntEnable \ + ADCIntEnable +#endif +#ifdef ROM_ADCIntStatus +#define MAP_ADCIntStatus \ + ROM_ADCIntStatus +#else +#define MAP_ADCIntStatus \ + ADCIntStatus +#endif +#ifdef ROM_ADCIntClear +#define MAP_ADCIntClear \ + ROM_ADCIntClear +#else +#define MAP_ADCIntClear \ + ADCIntClear +#endif +#ifdef ROM_ADCSequenceEnable +#define MAP_ADCSequenceEnable \ + ROM_ADCSequenceEnable +#else +#define MAP_ADCSequenceEnable \ + ADCSequenceEnable +#endif +#ifdef ROM_ADCSequenceDisable +#define MAP_ADCSequenceDisable \ + ROM_ADCSequenceDisable +#else +#define MAP_ADCSequenceDisable \ + ADCSequenceDisable +#endif +#ifdef ROM_ADCSequenceConfigure +#define MAP_ADCSequenceConfigure \ + ROM_ADCSequenceConfigure +#else +#define MAP_ADCSequenceConfigure \ + ADCSequenceConfigure +#endif +#ifdef ROM_ADCSequenceStepConfigure +#define MAP_ADCSequenceStepConfigure \ + ROM_ADCSequenceStepConfigure +#else +#define MAP_ADCSequenceStepConfigure \ + ADCSequenceStepConfigure +#endif +#ifdef ROM_ADCSequenceOverflow +#define MAP_ADCSequenceOverflow \ + ROM_ADCSequenceOverflow +#else +#define MAP_ADCSequenceOverflow \ + ADCSequenceOverflow +#endif +#ifdef ROM_ADCSequenceOverflowClear +#define MAP_ADCSequenceOverflowClear \ + ROM_ADCSequenceOverflowClear +#else +#define MAP_ADCSequenceOverflowClear \ + ADCSequenceOverflowClear +#endif +#ifdef ROM_ADCSequenceUnderflow +#define MAP_ADCSequenceUnderflow \ + ROM_ADCSequenceUnderflow +#else +#define MAP_ADCSequenceUnderflow \ + ADCSequenceUnderflow +#endif +#ifdef ROM_ADCSequenceUnderflowClear +#define MAP_ADCSequenceUnderflowClear \ + ROM_ADCSequenceUnderflowClear +#else +#define MAP_ADCSequenceUnderflowClear \ + ADCSequenceUnderflowClear +#endif +#ifdef ROM_ADCProcessorTrigger +#define MAP_ADCProcessorTrigger \ + ROM_ADCProcessorTrigger +#else +#define MAP_ADCProcessorTrigger \ + ADCProcessorTrigger +#endif +#ifdef ROM_ADCHardwareOversampleConfigure +#define MAP_ADCHardwareOversampleConfigure \ + ROM_ADCHardwareOversampleConfigure +#else +#define MAP_ADCHardwareOversampleConfigure \ + ADCHardwareOversampleConfigure +#endif +#ifdef ROM_ADCComparatorConfigure +#define MAP_ADCComparatorConfigure \ + ROM_ADCComparatorConfigure +#else +#define MAP_ADCComparatorConfigure \ + ADCComparatorConfigure +#endif +#ifdef ROM_ADCComparatorRegionSet +#define MAP_ADCComparatorRegionSet \ + ROM_ADCComparatorRegionSet +#else +#define MAP_ADCComparatorRegionSet \ + ADCComparatorRegionSet +#endif +#ifdef ROM_ADCComparatorReset +#define MAP_ADCComparatorReset \ + ROM_ADCComparatorReset +#else +#define MAP_ADCComparatorReset \ + ADCComparatorReset +#endif +#ifdef ROM_ADCComparatorIntDisable +#define MAP_ADCComparatorIntDisable \ + ROM_ADCComparatorIntDisable +#else +#define MAP_ADCComparatorIntDisable \ + ADCComparatorIntDisable +#endif +#ifdef ROM_ADCComparatorIntEnable +#define MAP_ADCComparatorIntEnable \ + ROM_ADCComparatorIntEnable +#else +#define MAP_ADCComparatorIntEnable \ + ADCComparatorIntEnable +#endif +#ifdef ROM_ADCComparatorIntStatus +#define MAP_ADCComparatorIntStatus \ + ROM_ADCComparatorIntStatus +#else +#define MAP_ADCComparatorIntStatus \ + ADCComparatorIntStatus +#endif +#ifdef ROM_ADCComparatorIntClear +#define MAP_ADCComparatorIntClear \ + ROM_ADCComparatorIntClear +#else +#define MAP_ADCComparatorIntClear \ + ADCComparatorIntClear +#endif +#ifdef ROM_ADCReferenceSet +#define MAP_ADCReferenceSet \ + ROM_ADCReferenceSet +#else +#define MAP_ADCReferenceSet \ + ADCReferenceSet +#endif +#ifdef ROM_ADCReferenceGet +#define MAP_ADCReferenceGet \ + ROM_ADCReferenceGet +#else +#define MAP_ADCReferenceGet \ + ADCReferenceGet +#endif +#ifdef ROM_ADCPhaseDelaySet +#define MAP_ADCPhaseDelaySet \ + ROM_ADCPhaseDelaySet +#else +#define MAP_ADCPhaseDelaySet \ + ADCPhaseDelaySet +#endif +#ifdef ROM_ADCPhaseDelayGet +#define MAP_ADCPhaseDelayGet \ + ROM_ADCPhaseDelayGet +#else +#define MAP_ADCPhaseDelayGet \ + ADCPhaseDelayGet +#endif +#ifdef ROM_ADCIntClearEx +#define MAP_ADCIntClearEx \ + ROM_ADCIntClearEx +#else +#define MAP_ADCIntClearEx \ + ADCIntClearEx +#endif +#ifdef ROM_ADCIntDisableEx +#define MAP_ADCIntDisableEx \ + ROM_ADCIntDisableEx +#else +#define MAP_ADCIntDisableEx \ + ADCIntDisableEx +#endif +#ifdef ROM_ADCIntEnableEx +#define MAP_ADCIntEnableEx \ + ROM_ADCIntEnableEx +#else +#define MAP_ADCIntEnableEx \ + ADCIntEnableEx +#endif +#ifdef ROM_ADCIntStatusEx +#define MAP_ADCIntStatusEx \ + ROM_ADCIntStatusEx +#else +#define MAP_ADCIntStatusEx \ + ADCIntStatusEx +#endif +#ifdef ROM_ADCSequenceDMAEnable +#define MAP_ADCSequenceDMAEnable \ + ROM_ADCSequenceDMAEnable +#else +#define MAP_ADCSequenceDMAEnable \ + ADCSequenceDMAEnable +#endif +#ifdef ROM_ADCSequenceDMADisable +#define MAP_ADCSequenceDMADisable \ + ROM_ADCSequenceDMADisable +#else +#define MAP_ADCSequenceDMADisable \ + ADCSequenceDMADisable +#endif +#ifdef ROM_ADCBusy +#define MAP_ADCBusy \ + ROM_ADCBusy +#else +#define MAP_ADCBusy \ + ADCBusy +#endif + +//***************************************************************************** +// +// Macros for the AES API. +// +//***************************************************************************** +#ifdef ROM_AESIntStatus +#define MAP_AESIntStatus \ + ROM_AESIntStatus +#else +#define MAP_AESIntStatus \ + AESIntStatus +#endif +#ifdef ROM_AESAuthLengthSet +#define MAP_AESAuthLengthSet \ + ROM_AESAuthLengthSet +#else +#define MAP_AESAuthLengthSet \ + AESAuthLengthSet +#endif +#ifdef ROM_AESConfigSet +#define MAP_AESConfigSet \ + ROM_AESConfigSet +#else +#define MAP_AESConfigSet \ + AESConfigSet +#endif +#ifdef ROM_AESDataAuth +#define MAP_AESDataAuth \ + ROM_AESDataAuth +#else +#define MAP_AESDataAuth \ + AESDataAuth +#endif +#ifdef ROM_AESDataProcess +#define MAP_AESDataProcess \ + ROM_AESDataProcess +#else +#define MAP_AESDataProcess \ + AESDataProcess +#endif +#ifdef ROM_AESDataProcessAuth +#define MAP_AESDataProcessAuth \ + ROM_AESDataProcessAuth +#else +#define MAP_AESDataProcessAuth \ + AESDataProcessAuth +#endif +#ifdef ROM_AESDataRead +#define MAP_AESDataRead \ + ROM_AESDataRead +#else +#define MAP_AESDataRead \ + AESDataRead +#endif +#ifdef ROM_AESDataReadNonBlocking +#define MAP_AESDataReadNonBlocking \ + ROM_AESDataReadNonBlocking +#else +#define MAP_AESDataReadNonBlocking \ + AESDataReadNonBlocking +#endif +#ifdef ROM_AESDataWrite +#define MAP_AESDataWrite \ + ROM_AESDataWrite +#else +#define MAP_AESDataWrite \ + AESDataWrite +#endif +#ifdef ROM_AESDataWriteNonBlocking +#define MAP_AESDataWriteNonBlocking \ + ROM_AESDataWriteNonBlocking +#else +#define MAP_AESDataWriteNonBlocking \ + AESDataWriteNonBlocking +#endif +#ifdef ROM_AESDMADisable +#define MAP_AESDMADisable \ + ROM_AESDMADisable +#else +#define MAP_AESDMADisable \ + AESDMADisable +#endif +#ifdef ROM_AESDMAEnable +#define MAP_AESDMAEnable \ + ROM_AESDMAEnable +#else +#define MAP_AESDMAEnable \ + AESDMAEnable +#endif +#ifdef ROM_AESIntClear +#define MAP_AESIntClear \ + ROM_AESIntClear +#else +#define MAP_AESIntClear \ + AESIntClear +#endif +#ifdef ROM_AESIntDisable +#define MAP_AESIntDisable \ + ROM_AESIntDisable +#else +#define MAP_AESIntDisable \ + AESIntDisable +#endif +#ifdef ROM_AESIntEnable +#define MAP_AESIntEnable \ + ROM_AESIntEnable +#else +#define MAP_AESIntEnable \ + AESIntEnable +#endif +#ifdef ROM_AESIVSet +#define MAP_AESIVSet \ + ROM_AESIVSet +#else +#define MAP_AESIVSet \ + AESIVSet +#endif +#ifdef ROM_AESKey1Set +#define MAP_AESKey1Set \ + ROM_AESKey1Set +#else +#define MAP_AESKey1Set \ + AESKey1Set +#endif +#ifdef ROM_AESKey2Set +#define MAP_AESKey2Set \ + ROM_AESKey2Set +#else +#define MAP_AESKey2Set \ + AESKey2Set +#endif +#ifdef ROM_AESKey3Set +#define MAP_AESKey3Set \ + ROM_AESKey3Set +#else +#define MAP_AESKey3Set \ + AESKey3Set +#endif +#ifdef ROM_AESLengthSet +#define MAP_AESLengthSet \ + ROM_AESLengthSet +#else +#define MAP_AESLengthSet \ + AESLengthSet +#endif +#ifdef ROM_AESReset +#define MAP_AESReset \ + ROM_AESReset +#else +#define MAP_AESReset \ + AESReset +#endif +#ifdef ROM_AESTagRead +#define MAP_AESTagRead \ + ROM_AESTagRead +#else +#define MAP_AESTagRead \ + AESTagRead +#endif +#ifdef ROM_AESIVRead +#define MAP_AESIVRead \ + ROM_AESIVRead +#else +#define MAP_AESIVRead \ + AESIVRead +#endif + +//***************************************************************************** +// +// Macros for the CAN API. +// +//***************************************************************************** +#ifdef ROM_CANIntClear +#define MAP_CANIntClear \ + ROM_CANIntClear +#else +#define MAP_CANIntClear \ + CANIntClear +#endif +#ifdef ROM_CANInit +#define MAP_CANInit \ + ROM_CANInit +#else +#define MAP_CANInit \ + CANInit +#endif +#ifdef ROM_CANEnable +#define MAP_CANEnable \ + ROM_CANEnable +#else +#define MAP_CANEnable \ + CANEnable +#endif +#ifdef ROM_CANDisable +#define MAP_CANDisable \ + ROM_CANDisable +#else +#define MAP_CANDisable \ + CANDisable +#endif +#ifdef ROM_CANBitTimingSet +#define MAP_CANBitTimingSet \ + ROM_CANBitTimingSet +#else +#define MAP_CANBitTimingSet \ + CANBitTimingSet +#endif +#ifdef ROM_CANBitTimingGet +#define MAP_CANBitTimingGet \ + ROM_CANBitTimingGet +#else +#define MAP_CANBitTimingGet \ + CANBitTimingGet +#endif +#ifdef ROM_CANMessageSet +#define MAP_CANMessageSet \ + ROM_CANMessageSet +#else +#define MAP_CANMessageSet \ + CANMessageSet +#endif +#ifdef ROM_CANMessageGet +#define MAP_CANMessageGet \ + ROM_CANMessageGet +#else +#define MAP_CANMessageGet \ + CANMessageGet +#endif +#ifdef ROM_CANStatusGet +#define MAP_CANStatusGet \ + ROM_CANStatusGet +#else +#define MAP_CANStatusGet \ + CANStatusGet +#endif +#ifdef ROM_CANMessageClear +#define MAP_CANMessageClear \ + ROM_CANMessageClear +#else +#define MAP_CANMessageClear \ + CANMessageClear +#endif +#ifdef ROM_CANIntEnable +#define MAP_CANIntEnable \ + ROM_CANIntEnable +#else +#define MAP_CANIntEnable \ + CANIntEnable +#endif +#ifdef ROM_CANIntDisable +#define MAP_CANIntDisable \ + ROM_CANIntDisable +#else +#define MAP_CANIntDisable \ + CANIntDisable +#endif +#ifdef ROM_CANIntStatus +#define MAP_CANIntStatus \ + ROM_CANIntStatus +#else +#define MAP_CANIntStatus \ + CANIntStatus +#endif +#ifdef ROM_CANRetryGet +#define MAP_CANRetryGet \ + ROM_CANRetryGet +#else +#define MAP_CANRetryGet \ + CANRetryGet +#endif +#ifdef ROM_CANRetrySet +#define MAP_CANRetrySet \ + ROM_CANRetrySet +#else +#define MAP_CANRetrySet \ + CANRetrySet +#endif +#ifdef ROM_CANErrCntrGet +#define MAP_CANErrCntrGet \ + ROM_CANErrCntrGet +#else +#define MAP_CANErrCntrGet \ + CANErrCntrGet +#endif +#ifdef ROM_CANBitRateSet +#define MAP_CANBitRateSet \ + ROM_CANBitRateSet +#else +#define MAP_CANBitRateSet \ + CANBitRateSet +#endif + +//***************************************************************************** +// +// Macros for the Comparator API. +// +//***************************************************************************** +#ifdef ROM_ComparatorIntClear +#define MAP_ComparatorIntClear \ + ROM_ComparatorIntClear +#else +#define MAP_ComparatorIntClear \ + ComparatorIntClear +#endif +#ifdef ROM_ComparatorConfigure +#define MAP_ComparatorConfigure \ + ROM_ComparatorConfigure +#else +#define MAP_ComparatorConfigure \ + ComparatorConfigure +#endif +#ifdef ROM_ComparatorRefSet +#define MAP_ComparatorRefSet \ + ROM_ComparatorRefSet +#else +#define MAP_ComparatorRefSet \ + ComparatorRefSet +#endif +#ifdef ROM_ComparatorValueGet +#define MAP_ComparatorValueGet \ + ROM_ComparatorValueGet +#else +#define MAP_ComparatorValueGet \ + ComparatorValueGet +#endif +#ifdef ROM_ComparatorIntEnable +#define MAP_ComparatorIntEnable \ + ROM_ComparatorIntEnable +#else +#define MAP_ComparatorIntEnable \ + ComparatorIntEnable +#endif +#ifdef ROM_ComparatorIntDisable +#define MAP_ComparatorIntDisable \ + ROM_ComparatorIntDisable +#else +#define MAP_ComparatorIntDisable \ + ComparatorIntDisable +#endif +#ifdef ROM_ComparatorIntStatus +#define MAP_ComparatorIntStatus \ + ROM_ComparatorIntStatus +#else +#define MAP_ComparatorIntStatus \ + ComparatorIntStatus +#endif + +//***************************************************************************** +// +// Macros for the CRC API. +// +//***************************************************************************** +#ifdef ROM_CRCConfigSet +#define MAP_CRCConfigSet \ + ROM_CRCConfigSet +#else +#define MAP_CRCConfigSet \ + CRCConfigSet +#endif +#ifdef ROM_CRCDataProcess +#define MAP_CRCDataProcess \ + ROM_CRCDataProcess +#else +#define MAP_CRCDataProcess \ + CRCDataProcess +#endif +#ifdef ROM_CRCDataWrite +#define MAP_CRCDataWrite \ + ROM_CRCDataWrite +#else +#define MAP_CRCDataWrite \ + CRCDataWrite +#endif +#ifdef ROM_CRCResultRead +#define MAP_CRCResultRead \ + ROM_CRCResultRead +#else +#define MAP_CRCResultRead \ + CRCResultRead +#endif +#ifdef ROM_CRCSeedSet +#define MAP_CRCSeedSet \ + ROM_CRCSeedSet +#else +#define MAP_CRCSeedSet \ + CRCSeedSet +#endif + +//***************************************************************************** +// +// Macros for the DES API. +// +//***************************************************************************** +#ifdef ROM_DESIntStatus +#define MAP_DESIntStatus \ + ROM_DESIntStatus +#else +#define MAP_DESIntStatus \ + DESIntStatus +#endif +#ifdef ROM_DESConfigSet +#define MAP_DESConfigSet \ + ROM_DESConfigSet +#else +#define MAP_DESConfigSet \ + DESConfigSet +#endif +#ifdef ROM_DESDataRead +#define MAP_DESDataRead \ + ROM_DESDataRead +#else +#define MAP_DESDataRead \ + DESDataRead +#endif +#ifdef ROM_DESDataReadNonBlocking +#define MAP_DESDataReadNonBlocking \ + ROM_DESDataReadNonBlocking +#else +#define MAP_DESDataReadNonBlocking \ + DESDataReadNonBlocking +#endif +#ifdef ROM_DESDataProcess +#define MAP_DESDataProcess \ + ROM_DESDataProcess +#else +#define MAP_DESDataProcess \ + DESDataProcess +#endif +#ifdef ROM_DESDataWrite +#define MAP_DESDataWrite \ + ROM_DESDataWrite +#else +#define MAP_DESDataWrite \ + DESDataWrite +#endif +#ifdef ROM_DESDataWriteNonBlocking +#define MAP_DESDataWriteNonBlocking \ + ROM_DESDataWriteNonBlocking +#else +#define MAP_DESDataWriteNonBlocking \ + DESDataWriteNonBlocking +#endif +#ifdef ROM_DESDMADisable +#define MAP_DESDMADisable \ + ROM_DESDMADisable +#else +#define MAP_DESDMADisable \ + DESDMADisable +#endif +#ifdef ROM_DESDMAEnable +#define MAP_DESDMAEnable \ + ROM_DESDMAEnable +#else +#define MAP_DESDMAEnable \ + DESDMAEnable +#endif +#ifdef ROM_DESIntClear +#define MAP_DESIntClear \ + ROM_DESIntClear +#else +#define MAP_DESIntClear \ + DESIntClear +#endif +#ifdef ROM_DESIntDisable +#define MAP_DESIntDisable \ + ROM_DESIntDisable +#else +#define MAP_DESIntDisable \ + DESIntDisable +#endif +#ifdef ROM_DESIntEnable +#define MAP_DESIntEnable \ + ROM_DESIntEnable +#else +#define MAP_DESIntEnable \ + DESIntEnable +#endif +#ifdef ROM_DESIVSet +#define MAP_DESIVSet \ + ROM_DESIVSet +#else +#define MAP_DESIVSet \ + DESIVSet +#endif +#ifdef ROM_DESKeySet +#define MAP_DESKeySet \ + ROM_DESKeySet +#else +#define MAP_DESKeySet \ + DESKeySet +#endif +#ifdef ROM_DESLengthSet +#define MAP_DESLengthSet \ + ROM_DESLengthSet +#else +#define MAP_DESLengthSet \ + DESLengthSet +#endif +#ifdef ROM_DESReset +#define MAP_DESReset \ + ROM_DESReset +#else +#define MAP_DESReset \ + DESReset +#endif + +//***************************************************************************** +// +// Macros for the EEPROM API. +// +//***************************************************************************** +#ifdef ROM_EEPROMRead +#define MAP_EEPROMRead \ + ROM_EEPROMRead +#else +#define MAP_EEPROMRead \ + EEPROMRead +#endif +#ifdef ROM_EEPROMBlockCountGet +#define MAP_EEPROMBlockCountGet \ + ROM_EEPROMBlockCountGet +#else +#define MAP_EEPROMBlockCountGet \ + EEPROMBlockCountGet +#endif +#ifdef ROM_EEPROMBlockHide +#define MAP_EEPROMBlockHide \ + ROM_EEPROMBlockHide +#else +#define MAP_EEPROMBlockHide \ + EEPROMBlockHide +#endif +#ifdef ROM_EEPROMBlockLock +#define MAP_EEPROMBlockLock \ + ROM_EEPROMBlockLock +#else +#define MAP_EEPROMBlockLock \ + EEPROMBlockLock +#endif +#ifdef ROM_EEPROMBlockPasswordSet +#define MAP_EEPROMBlockPasswordSet \ + ROM_EEPROMBlockPasswordSet +#else +#define MAP_EEPROMBlockPasswordSet \ + EEPROMBlockPasswordSet +#endif +#ifdef ROM_EEPROMBlockProtectGet +#define MAP_EEPROMBlockProtectGet \ + ROM_EEPROMBlockProtectGet +#else +#define MAP_EEPROMBlockProtectGet \ + EEPROMBlockProtectGet +#endif +#ifdef ROM_EEPROMBlockProtectSet +#define MAP_EEPROMBlockProtectSet \ + ROM_EEPROMBlockProtectSet +#else +#define MAP_EEPROMBlockProtectSet \ + EEPROMBlockProtectSet +#endif +#ifdef ROM_EEPROMBlockUnlock +#define MAP_EEPROMBlockUnlock \ + ROM_EEPROMBlockUnlock +#else +#define MAP_EEPROMBlockUnlock \ + EEPROMBlockUnlock +#endif +#ifdef ROM_EEPROMIntClear +#define MAP_EEPROMIntClear \ + ROM_EEPROMIntClear +#else +#define MAP_EEPROMIntClear \ + EEPROMIntClear +#endif +#ifdef ROM_EEPROMIntDisable +#define MAP_EEPROMIntDisable \ + ROM_EEPROMIntDisable +#else +#define MAP_EEPROMIntDisable \ + EEPROMIntDisable +#endif +#ifdef ROM_EEPROMIntEnable +#define MAP_EEPROMIntEnable \ + ROM_EEPROMIntEnable +#else +#define MAP_EEPROMIntEnable \ + EEPROMIntEnable +#endif +#ifdef ROM_EEPROMIntStatus +#define MAP_EEPROMIntStatus \ + ROM_EEPROMIntStatus +#else +#define MAP_EEPROMIntStatus \ + EEPROMIntStatus +#endif +#ifdef ROM_EEPROMMassErase +#define MAP_EEPROMMassErase \ + ROM_EEPROMMassErase +#else +#define MAP_EEPROMMassErase \ + EEPROMMassErase +#endif +#ifdef ROM_EEPROMProgram +#define MAP_EEPROMProgram \ + ROM_EEPROMProgram +#else +#define MAP_EEPROMProgram \ + EEPROMProgram +#endif +#ifdef ROM_EEPROMProgramNonBlocking +#define MAP_EEPROMProgramNonBlocking \ + ROM_EEPROMProgramNonBlocking +#else +#define MAP_EEPROMProgramNonBlocking \ + EEPROMProgramNonBlocking +#endif +#ifdef ROM_EEPROMSizeGet +#define MAP_EEPROMSizeGet \ + ROM_EEPROMSizeGet +#else +#define MAP_EEPROMSizeGet \ + EEPROMSizeGet +#endif +#ifdef ROM_EEPROMStatusGet +#define MAP_EEPROMStatusGet \ + ROM_EEPROMStatusGet +#else +#define MAP_EEPROMStatusGet \ + EEPROMStatusGet +#endif +#ifdef ROM_EEPROMInit +#define MAP_EEPROMInit \ + ROM_EEPROMInit +#else +#define MAP_EEPROMInit \ + EEPROMInit +#endif + +//***************************************************************************** +// +// Macros for the EPI API. +// +//***************************************************************************** +#ifdef ROM_EPIIntStatus +#define MAP_EPIIntStatus \ + ROM_EPIIntStatus +#else +#define MAP_EPIIntStatus \ + EPIIntStatus +#endif +#ifdef ROM_EPIModeSet +#define MAP_EPIModeSet \ + ROM_EPIModeSet +#else +#define MAP_EPIModeSet \ + EPIModeSet +#endif +#ifdef ROM_EPIDividerSet +#define MAP_EPIDividerSet \ + ROM_EPIDividerSet +#else +#define MAP_EPIDividerSet \ + EPIDividerSet +#endif +#ifdef ROM_EPIConfigSDRAMSet +#define MAP_EPIConfigSDRAMSet \ + ROM_EPIConfigSDRAMSet +#else +#define MAP_EPIConfigSDRAMSet \ + EPIConfigSDRAMSet +#endif +#ifdef ROM_EPIConfigGPModeSet +#define MAP_EPIConfigGPModeSet \ + ROM_EPIConfigGPModeSet +#else +#define MAP_EPIConfigGPModeSet \ + EPIConfigGPModeSet +#endif +#ifdef ROM_EPIConfigHB8Set +#define MAP_EPIConfigHB8Set \ + ROM_EPIConfigHB8Set +#else +#define MAP_EPIConfigHB8Set \ + EPIConfigHB8Set +#endif +#ifdef ROM_EPIConfigHB16Set +#define MAP_EPIConfigHB16Set \ + ROM_EPIConfigHB16Set +#else +#define MAP_EPIConfigHB16Set \ + EPIConfigHB16Set +#endif +#ifdef ROM_EPIAddressMapSet +#define MAP_EPIAddressMapSet \ + ROM_EPIAddressMapSet +#else +#define MAP_EPIAddressMapSet \ + EPIAddressMapSet +#endif +#ifdef ROM_EPINonBlockingReadConfigure +#define MAP_EPINonBlockingReadConfigure \ + ROM_EPINonBlockingReadConfigure +#else +#define MAP_EPINonBlockingReadConfigure \ + EPINonBlockingReadConfigure +#endif +#ifdef ROM_EPINonBlockingReadStart +#define MAP_EPINonBlockingReadStart \ + ROM_EPINonBlockingReadStart +#else +#define MAP_EPINonBlockingReadStart \ + EPINonBlockingReadStart +#endif +#ifdef ROM_EPINonBlockingReadStop +#define MAP_EPINonBlockingReadStop \ + ROM_EPINonBlockingReadStop +#else +#define MAP_EPINonBlockingReadStop \ + EPINonBlockingReadStop +#endif +#ifdef ROM_EPINonBlockingReadCount +#define MAP_EPINonBlockingReadCount \ + ROM_EPINonBlockingReadCount +#else +#define MAP_EPINonBlockingReadCount \ + EPINonBlockingReadCount +#endif +#ifdef ROM_EPINonBlockingReadAvail +#define MAP_EPINonBlockingReadAvail \ + ROM_EPINonBlockingReadAvail +#else +#define MAP_EPINonBlockingReadAvail \ + EPINonBlockingReadAvail +#endif +#ifdef ROM_EPINonBlockingReadGet32 +#define MAP_EPINonBlockingReadGet32 \ + ROM_EPINonBlockingReadGet32 +#else +#define MAP_EPINonBlockingReadGet32 \ + EPINonBlockingReadGet32 +#endif +#ifdef ROM_EPINonBlockingReadGet16 +#define MAP_EPINonBlockingReadGet16 \ + ROM_EPINonBlockingReadGet16 +#else +#define MAP_EPINonBlockingReadGet16 \ + EPINonBlockingReadGet16 +#endif +#ifdef ROM_EPINonBlockingReadGet8 +#define MAP_EPINonBlockingReadGet8 \ + ROM_EPINonBlockingReadGet8 +#else +#define MAP_EPINonBlockingReadGet8 \ + EPINonBlockingReadGet8 +#endif +#ifdef ROM_EPIFIFOConfig +#define MAP_EPIFIFOConfig \ + ROM_EPIFIFOConfig +#else +#define MAP_EPIFIFOConfig \ + EPIFIFOConfig +#endif +#ifdef ROM_EPIWriteFIFOCountGet +#define MAP_EPIWriteFIFOCountGet \ + ROM_EPIWriteFIFOCountGet +#else +#define MAP_EPIWriteFIFOCountGet \ + EPIWriteFIFOCountGet +#endif +#ifdef ROM_EPIIntEnable +#define MAP_EPIIntEnable \ + ROM_EPIIntEnable +#else +#define MAP_EPIIntEnable \ + EPIIntEnable +#endif +#ifdef ROM_EPIIntDisable +#define MAP_EPIIntDisable \ + ROM_EPIIntDisable +#else +#define MAP_EPIIntDisable \ + EPIIntDisable +#endif +#ifdef ROM_EPIIntErrorStatus +#define MAP_EPIIntErrorStatus \ + ROM_EPIIntErrorStatus +#else +#define MAP_EPIIntErrorStatus \ + EPIIntErrorStatus +#endif +#ifdef ROM_EPIIntErrorClear +#define MAP_EPIIntErrorClear \ + ROM_EPIIntErrorClear +#else +#define MAP_EPIIntErrorClear \ + EPIIntErrorClear +#endif +#ifdef ROM_EPIDividerCSSet +#define MAP_EPIDividerCSSet \ + ROM_EPIDividerCSSet +#else +#define MAP_EPIDividerCSSet \ + EPIDividerCSSet +#endif +#ifdef ROM_EPIDMATxCount +#define MAP_EPIDMATxCount \ + ROM_EPIDMATxCount +#else +#define MAP_EPIDMATxCount \ + EPIDMATxCount +#endif +#ifdef ROM_EPIConfigHB8CSSet +#define MAP_EPIConfigHB8CSSet \ + ROM_EPIConfigHB8CSSet +#else +#define MAP_EPIConfigHB8CSSet \ + EPIConfigHB8CSSet +#endif +#ifdef ROM_EPIConfigHB16CSSet +#define MAP_EPIConfigHB16CSSet \ + ROM_EPIConfigHB16CSSet +#else +#define MAP_EPIConfigHB16CSSet \ + EPIConfigHB16CSSet +#endif +#ifdef ROM_EPIConfigHB8TimingSet +#define MAP_EPIConfigHB8TimingSet \ + ROM_EPIConfigHB8TimingSet +#else +#define MAP_EPIConfigHB8TimingSet \ + EPIConfigHB8TimingSet +#endif +#ifdef ROM_EPIConfigHB16TimingSet +#define MAP_EPIConfigHB16TimingSet \ + ROM_EPIConfigHB16TimingSet +#else +#define MAP_EPIConfigHB16TimingSet \ + EPIConfigHB16TimingSet +#endif +#ifdef ROM_EPIPSRAMConfigRegSet +#define MAP_EPIPSRAMConfigRegSet \ + ROM_EPIPSRAMConfigRegSet +#else +#define MAP_EPIPSRAMConfigRegSet \ + EPIPSRAMConfigRegSet +#endif +#ifdef ROM_EPIPSRAMConfigRegRead +#define MAP_EPIPSRAMConfigRegRead \ + ROM_EPIPSRAMConfigRegRead +#else +#define MAP_EPIPSRAMConfigRegRead \ + EPIPSRAMConfigRegRead +#endif +#ifdef ROM_EPIPSRAMConfigRegGetNonBlocking +#define MAP_EPIPSRAMConfigRegGetNonBlocking \ + ROM_EPIPSRAMConfigRegGetNonBlocking +#else +#define MAP_EPIPSRAMConfigRegGetNonBlocking \ + EPIPSRAMConfigRegGetNonBlocking +#endif +#ifdef ROM_EPIPSRAMConfigRegGet +#define MAP_EPIPSRAMConfigRegGet \ + ROM_EPIPSRAMConfigRegGet +#else +#define MAP_EPIPSRAMConfigRegGet \ + EPIPSRAMConfigRegGet +#endif + +//***************************************************************************** +// +// Macros for the EMAC API. +// +//***************************************************************************** +#ifdef ROM_EMACIntStatus +#define MAP_EMACIntStatus \ + ROM_EMACIntStatus +#else +#define MAP_EMACIntStatus \ + EMACIntStatus +#endif +#ifdef ROM_EMACAddrGet +#define MAP_EMACAddrGet \ + ROM_EMACAddrGet +#else +#define MAP_EMACAddrGet \ + EMACAddrGet +#endif +#ifdef ROM_EMACAddrSet +#define MAP_EMACAddrSet \ + ROM_EMACAddrSet +#else +#define MAP_EMACAddrSet \ + EMACAddrSet +#endif +#ifdef ROM_EMACConfigGet +#define MAP_EMACConfigGet \ + ROM_EMACConfigGet +#else +#define MAP_EMACConfigGet \ + EMACConfigGet +#endif +#ifdef ROM_EMACConfigSet +#define MAP_EMACConfigSet \ + ROM_EMACConfigSet +#else +#define MAP_EMACConfigSet \ + EMACConfigSet +#endif +#ifdef ROM_EMACDMAStateGet +#define MAP_EMACDMAStateGet \ + ROM_EMACDMAStateGet +#else +#define MAP_EMACDMAStateGet \ + EMACDMAStateGet +#endif +#ifdef ROM_EMACFrameFilterGet +#define MAP_EMACFrameFilterGet \ + ROM_EMACFrameFilterGet +#else +#define MAP_EMACFrameFilterGet \ + EMACFrameFilterGet +#endif +#ifdef ROM_EMACFrameFilterSet +#define MAP_EMACFrameFilterSet \ + ROM_EMACFrameFilterSet +#else +#define MAP_EMACFrameFilterSet \ + EMACFrameFilterSet +#endif +#ifdef ROM_EMACInit +#define MAP_EMACInit \ + ROM_EMACInit +#else +#define MAP_EMACInit \ + EMACInit +#endif +#ifdef ROM_EMACIntClear +#define MAP_EMACIntClear \ + ROM_EMACIntClear +#else +#define MAP_EMACIntClear \ + EMACIntClear +#endif +#ifdef ROM_EMACIntDisable +#define MAP_EMACIntDisable \ + ROM_EMACIntDisable +#else +#define MAP_EMACIntDisable \ + EMACIntDisable +#endif +#ifdef ROM_EMACIntEnable +#define MAP_EMACIntEnable \ + ROM_EMACIntEnable +#else +#define MAP_EMACIntEnable \ + EMACIntEnable +#endif +#ifdef ROM_EMACPHYConfigSet +#define MAP_EMACPHYConfigSet \ + ROM_EMACPHYConfigSet +#else +#define MAP_EMACPHYConfigSet \ + EMACPHYConfigSet +#endif +#ifdef ROM_EMACPHYPowerOff +#define MAP_EMACPHYPowerOff \ + ROM_EMACPHYPowerOff +#else +#define MAP_EMACPHYPowerOff \ + EMACPHYPowerOff +#endif +#ifdef ROM_EMACPHYPowerOn +#define MAP_EMACPHYPowerOn \ + ROM_EMACPHYPowerOn +#else +#define MAP_EMACPHYPowerOn \ + EMACPHYPowerOn +#endif +#ifdef ROM_EMACPHYRead +#define MAP_EMACPHYRead \ + ROM_EMACPHYRead +#else +#define MAP_EMACPHYRead \ + EMACPHYRead +#endif +#ifdef ROM_EMACPHYWrite +#define MAP_EMACPHYWrite \ + ROM_EMACPHYWrite +#else +#define MAP_EMACPHYWrite \ + EMACPHYWrite +#endif +#ifdef ROM_EMACReset +#define MAP_EMACReset \ + ROM_EMACReset +#else +#define MAP_EMACReset \ + EMACReset +#endif +#ifdef ROM_EMACRxDisable +#define MAP_EMACRxDisable \ + ROM_EMACRxDisable +#else +#define MAP_EMACRxDisable \ + EMACRxDisable +#endif +#ifdef ROM_EMACRxDMACurrentBufferGet +#define MAP_EMACRxDMACurrentBufferGet \ + ROM_EMACRxDMACurrentBufferGet +#else +#define MAP_EMACRxDMACurrentBufferGet \ + EMACRxDMACurrentBufferGet +#endif +#ifdef ROM_EMACRxDMACurrentDescriptorGet +#define MAP_EMACRxDMACurrentDescriptorGet \ + ROM_EMACRxDMACurrentDescriptorGet +#else +#define MAP_EMACRxDMACurrentDescriptorGet \ + EMACRxDMACurrentDescriptorGet +#endif +#ifdef ROM_EMACRxDMADescriptorListGet +#define MAP_EMACRxDMADescriptorListGet \ + ROM_EMACRxDMADescriptorListGet +#else +#define MAP_EMACRxDMADescriptorListGet \ + EMACRxDMADescriptorListGet +#endif +#ifdef ROM_EMACRxDMADescriptorListSet +#define MAP_EMACRxDMADescriptorListSet \ + ROM_EMACRxDMADescriptorListSet +#else +#define MAP_EMACRxDMADescriptorListSet \ + EMACRxDMADescriptorListSet +#endif +#ifdef ROM_EMACRxDMAPollDemand +#define MAP_EMACRxDMAPollDemand \ + ROM_EMACRxDMAPollDemand +#else +#define MAP_EMACRxDMAPollDemand \ + EMACRxDMAPollDemand +#endif +#ifdef ROM_EMACRxEnable +#define MAP_EMACRxEnable \ + ROM_EMACRxEnable +#else +#define MAP_EMACRxEnable \ + EMACRxEnable +#endif +#ifdef ROM_EMACRxWatchdogTimerSet +#define MAP_EMACRxWatchdogTimerSet \ + ROM_EMACRxWatchdogTimerSet +#else +#define MAP_EMACRxWatchdogTimerSet \ + EMACRxWatchdogTimerSet +#endif +#ifdef ROM_EMACStatusGet +#define MAP_EMACStatusGet \ + ROM_EMACStatusGet +#else +#define MAP_EMACStatusGet \ + EMACStatusGet +#endif +#ifdef ROM_EMACTxDisable +#define MAP_EMACTxDisable \ + ROM_EMACTxDisable +#else +#define MAP_EMACTxDisable \ + EMACTxDisable +#endif +#ifdef ROM_EMACTxDMACurrentBufferGet +#define MAP_EMACTxDMACurrentBufferGet \ + ROM_EMACTxDMACurrentBufferGet +#else +#define MAP_EMACTxDMACurrentBufferGet \ + EMACTxDMACurrentBufferGet +#endif +#ifdef ROM_EMACTxDMACurrentDescriptorGet +#define MAP_EMACTxDMACurrentDescriptorGet \ + ROM_EMACTxDMACurrentDescriptorGet +#else +#define MAP_EMACTxDMACurrentDescriptorGet \ + EMACTxDMACurrentDescriptorGet +#endif +#ifdef ROM_EMACTxDMADescriptorListGet +#define MAP_EMACTxDMADescriptorListGet \ + ROM_EMACTxDMADescriptorListGet +#else +#define MAP_EMACTxDMADescriptorListGet \ + EMACTxDMADescriptorListGet +#endif +#ifdef ROM_EMACTxDMADescriptorListSet +#define MAP_EMACTxDMADescriptorListSet \ + ROM_EMACTxDMADescriptorListSet +#else +#define MAP_EMACTxDMADescriptorListSet \ + EMACTxDMADescriptorListSet +#endif +#ifdef ROM_EMACTxDMAPollDemand +#define MAP_EMACTxDMAPollDemand \ + ROM_EMACTxDMAPollDemand +#else +#define MAP_EMACTxDMAPollDemand \ + EMACTxDMAPollDemand +#endif +#ifdef ROM_EMACTxEnable +#define MAP_EMACTxEnable \ + ROM_EMACTxEnable +#else +#define MAP_EMACTxEnable \ + EMACTxEnable +#endif +#ifdef ROM_EMACTxFlush +#define MAP_EMACTxFlush \ + ROM_EMACTxFlush +#else +#define MAP_EMACTxFlush \ + EMACTxFlush +#endif +#ifdef ROM_EMACAddrFilterGet +#define MAP_EMACAddrFilterGet \ + ROM_EMACAddrFilterGet +#else +#define MAP_EMACAddrFilterGet \ + EMACAddrFilterGet +#endif +#ifdef ROM_EMACAddrFilterSet +#define MAP_EMACAddrFilterSet \ + ROM_EMACAddrFilterSet +#else +#define MAP_EMACAddrFilterSet \ + EMACAddrFilterSet +#endif +#ifdef ROM_EMACHashFilterBitCalculate +#define MAP_EMACHashFilterBitCalculate \ + ROM_EMACHashFilterBitCalculate +#else +#define MAP_EMACHashFilterBitCalculate \ + EMACHashFilterBitCalculate +#endif +#ifdef ROM_EMACHashFilterGet +#define MAP_EMACHashFilterGet \ + ROM_EMACHashFilterGet +#else +#define MAP_EMACHashFilterGet \ + EMACHashFilterGet +#endif +#ifdef ROM_EMACHashFilterSet +#define MAP_EMACHashFilterSet \ + ROM_EMACHashFilterSet +#else +#define MAP_EMACHashFilterSet \ + EMACHashFilterSet +#endif +#ifdef ROM_EMACNumAddrGet +#define MAP_EMACNumAddrGet \ + ROM_EMACNumAddrGet +#else +#define MAP_EMACNumAddrGet \ + EMACNumAddrGet +#endif +#ifdef ROM_EMACPHYExtendedRead +#define MAP_EMACPHYExtendedRead \ + ROM_EMACPHYExtendedRead +#else +#define MAP_EMACPHYExtendedRead \ + EMACPHYExtendedRead +#endif +#ifdef ROM_EMACPHYExtendedWrite +#define MAP_EMACPHYExtendedWrite \ + ROM_EMACPHYExtendedWrite +#else +#define MAP_EMACPHYExtendedWrite \ + EMACPHYExtendedWrite +#endif +#ifdef ROM_EMACPowerManagementControlGet +#define MAP_EMACPowerManagementControlGet \ + ROM_EMACPowerManagementControlGet +#else +#define MAP_EMACPowerManagementControlGet \ + EMACPowerManagementControlGet +#endif +#ifdef ROM_EMACPowerManagementControlSet +#define MAP_EMACPowerManagementControlSet \ + ROM_EMACPowerManagementControlSet +#else +#define MAP_EMACPowerManagementControlSet \ + EMACPowerManagementControlSet +#endif +#ifdef ROM_EMACPowerManagementStatusGet +#define MAP_EMACPowerManagementStatusGet \ + ROM_EMACPowerManagementStatusGet +#else +#define MAP_EMACPowerManagementStatusGet \ + EMACPowerManagementStatusGet +#endif +#ifdef ROM_EMACRemoteWakeUpFrameFilterGet +#define MAP_EMACRemoteWakeUpFrameFilterGet \ + ROM_EMACRemoteWakeUpFrameFilterGet +#else +#define MAP_EMACRemoteWakeUpFrameFilterGet \ + EMACRemoteWakeUpFrameFilterGet +#endif +#ifdef ROM_EMACRemoteWakeUpFrameFilterSet +#define MAP_EMACRemoteWakeUpFrameFilterSet \ + ROM_EMACRemoteWakeUpFrameFilterSet +#else +#define MAP_EMACRemoteWakeUpFrameFilterSet \ + EMACRemoteWakeUpFrameFilterSet +#endif +#ifdef ROM_EMACTimestampAddendSet +#define MAP_EMACTimestampAddendSet \ + ROM_EMACTimestampAddendSet +#else +#define MAP_EMACTimestampAddendSet \ + EMACTimestampAddendSet +#endif +#ifdef ROM_EMACTimestampConfigGet +#define MAP_EMACTimestampConfigGet \ + ROM_EMACTimestampConfigGet +#else +#define MAP_EMACTimestampConfigGet \ + EMACTimestampConfigGet +#endif +#ifdef ROM_EMACTimestampConfigSet +#define MAP_EMACTimestampConfigSet \ + ROM_EMACTimestampConfigSet +#else +#define MAP_EMACTimestampConfigSet \ + EMACTimestampConfigSet +#endif +#ifdef ROM_EMACTimestampDisable +#define MAP_EMACTimestampDisable \ + ROM_EMACTimestampDisable +#else +#define MAP_EMACTimestampDisable \ + EMACTimestampDisable +#endif +#ifdef ROM_EMACTimestampEnable +#define MAP_EMACTimestampEnable \ + ROM_EMACTimestampEnable +#else +#define MAP_EMACTimestampEnable \ + EMACTimestampEnable +#endif +#ifdef ROM_EMACTimestampIntStatus +#define MAP_EMACTimestampIntStatus \ + ROM_EMACTimestampIntStatus +#else +#define MAP_EMACTimestampIntStatus \ + EMACTimestampIntStatus +#endif +#ifdef ROM_EMACTimestampPPSCommand +#define MAP_EMACTimestampPPSCommand \ + ROM_EMACTimestampPPSCommand +#else +#define MAP_EMACTimestampPPSCommand \ + EMACTimestampPPSCommand +#endif +#ifdef ROM_EMACTimestampPPSCommandModeSet +#define MAP_EMACTimestampPPSCommandModeSet \ + ROM_EMACTimestampPPSCommandModeSet +#else +#define MAP_EMACTimestampPPSCommandModeSet \ + EMACTimestampPPSCommandModeSet +#endif +#ifdef ROM_EMACTimestampPPSPeriodSet +#define MAP_EMACTimestampPPSPeriodSet \ + ROM_EMACTimestampPPSPeriodSet +#else +#define MAP_EMACTimestampPPSPeriodSet \ + EMACTimestampPPSPeriodSet +#endif +#ifdef ROM_EMACTimestampPPSSimpleModeSet +#define MAP_EMACTimestampPPSSimpleModeSet \ + ROM_EMACTimestampPPSSimpleModeSet +#else +#define MAP_EMACTimestampPPSSimpleModeSet \ + EMACTimestampPPSSimpleModeSet +#endif +#ifdef ROM_EMACTimestampSysTimeGet +#define MAP_EMACTimestampSysTimeGet \ + ROM_EMACTimestampSysTimeGet +#else +#define MAP_EMACTimestampSysTimeGet \ + EMACTimestampSysTimeGet +#endif +#ifdef ROM_EMACTimestampSysTimeSet +#define MAP_EMACTimestampSysTimeSet \ + ROM_EMACTimestampSysTimeSet +#else +#define MAP_EMACTimestampSysTimeSet \ + EMACTimestampSysTimeSet +#endif +#ifdef ROM_EMACTimestampSysTimeUpdate +#define MAP_EMACTimestampSysTimeUpdate \ + ROM_EMACTimestampSysTimeUpdate +#else +#define MAP_EMACTimestampSysTimeUpdate \ + EMACTimestampSysTimeUpdate +#endif +#ifdef ROM_EMACTimestampTargetIntDisable +#define MAP_EMACTimestampTargetIntDisable \ + ROM_EMACTimestampTargetIntDisable +#else +#define MAP_EMACTimestampTargetIntDisable \ + EMACTimestampTargetIntDisable +#endif +#ifdef ROM_EMACTimestampTargetIntEnable +#define MAP_EMACTimestampTargetIntEnable \ + ROM_EMACTimestampTargetIntEnable +#else +#define MAP_EMACTimestampTargetIntEnable \ + EMACTimestampTargetIntEnable +#endif +#ifdef ROM_EMACTimestampTargetSet +#define MAP_EMACTimestampTargetSet \ + ROM_EMACTimestampTargetSet +#else +#define MAP_EMACTimestampTargetSet \ + EMACTimestampTargetSet +#endif +#ifdef ROM_EMACVLANHashFilterBitCalculate +#define MAP_EMACVLANHashFilterBitCalculate \ + ROM_EMACVLANHashFilterBitCalculate +#else +#define MAP_EMACVLANHashFilterBitCalculate \ + EMACVLANHashFilterBitCalculate +#endif +#ifdef ROM_EMACVLANHashFilterGet +#define MAP_EMACVLANHashFilterGet \ + ROM_EMACVLANHashFilterGet +#else +#define MAP_EMACVLANHashFilterGet \ + EMACVLANHashFilterGet +#endif +#ifdef ROM_EMACVLANHashFilterSet +#define MAP_EMACVLANHashFilterSet \ + ROM_EMACVLANHashFilterSet +#else +#define MAP_EMACVLANHashFilterSet \ + EMACVLANHashFilterSet +#endif +#ifdef ROM_EMACVLANRxConfigGet +#define MAP_EMACVLANRxConfigGet \ + ROM_EMACVLANRxConfigGet +#else +#define MAP_EMACVLANRxConfigGet \ + EMACVLANRxConfigGet +#endif +#ifdef ROM_EMACVLANRxConfigSet +#define MAP_EMACVLANRxConfigSet \ + ROM_EMACVLANRxConfigSet +#else +#define MAP_EMACVLANRxConfigSet \ + EMACVLANRxConfigSet +#endif +#ifdef ROM_EMACVLANTxConfigGet +#define MAP_EMACVLANTxConfigGet \ + ROM_EMACVLANTxConfigGet +#else +#define MAP_EMACVLANTxConfigGet \ + EMACVLANTxConfigGet +#endif +#ifdef ROM_EMACVLANTxConfigSet +#define MAP_EMACVLANTxConfigSet \ + ROM_EMACVLANTxConfigSet +#else +#define MAP_EMACVLANTxConfigSet \ + EMACVLANTxConfigSet +#endif + +//***************************************************************************** +// +// Macros for the Flash API. +// +//***************************************************************************** +#ifdef ROM_FlashProgram +#define MAP_FlashProgram \ + ROM_FlashProgram +#else +#define MAP_FlashProgram \ + FlashProgram +#endif +#ifdef ROM_FlashErase +#define MAP_FlashErase \ + ROM_FlashErase +#else +#define MAP_FlashErase \ + FlashErase +#endif +#ifdef ROM_FlashProtectGet +#define MAP_FlashProtectGet \ + ROM_FlashProtectGet +#else +#define MAP_FlashProtectGet \ + FlashProtectGet +#endif +#ifdef ROM_FlashProtectSet +#define MAP_FlashProtectSet \ + ROM_FlashProtectSet +#else +#define MAP_FlashProtectSet \ + FlashProtectSet +#endif +#ifdef ROM_FlashProtectSave +#define MAP_FlashProtectSave \ + ROM_FlashProtectSave +#else +#define MAP_FlashProtectSave \ + FlashProtectSave +#endif +#ifdef ROM_FlashUserGet +#define MAP_FlashUserGet \ + ROM_FlashUserGet +#else +#define MAP_FlashUserGet \ + FlashUserGet +#endif +#ifdef ROM_FlashUserSet +#define MAP_FlashUserSet \ + ROM_FlashUserSet +#else +#define MAP_FlashUserSet \ + FlashUserSet +#endif +#ifdef ROM_FlashUserSave +#define MAP_FlashUserSave \ + ROM_FlashUserSave +#else +#define MAP_FlashUserSave \ + FlashUserSave +#endif +#ifdef ROM_FlashIntEnable +#define MAP_FlashIntEnable \ + ROM_FlashIntEnable +#else +#define MAP_FlashIntEnable \ + FlashIntEnable +#endif +#ifdef ROM_FlashIntDisable +#define MAP_FlashIntDisable \ + ROM_FlashIntDisable +#else +#define MAP_FlashIntDisable \ + FlashIntDisable +#endif +#ifdef ROM_FlashIntStatus +#define MAP_FlashIntStatus \ + ROM_FlashIntStatus +#else +#define MAP_FlashIntStatus \ + FlashIntStatus +#endif +#ifdef ROM_FlashIntClear +#define MAP_FlashIntClear \ + ROM_FlashIntClear +#else +#define MAP_FlashIntClear \ + FlashIntClear +#endif + +//***************************************************************************** +// +// Macros for the FPU API. +// +//***************************************************************************** +#ifdef ROM_FPUEnable +#define MAP_FPUEnable \ + ROM_FPUEnable +#else +#define MAP_FPUEnable \ + FPUEnable +#endif +#ifdef ROM_FPUDisable +#define MAP_FPUDisable \ + ROM_FPUDisable +#else +#define MAP_FPUDisable \ + FPUDisable +#endif +#ifdef ROM_FPUFlushToZeroModeSet +#define MAP_FPUFlushToZeroModeSet \ + ROM_FPUFlushToZeroModeSet +#else +#define MAP_FPUFlushToZeroModeSet \ + FPUFlushToZeroModeSet +#endif +#ifdef ROM_FPUHalfPrecisionModeSet +#define MAP_FPUHalfPrecisionModeSet \ + ROM_FPUHalfPrecisionModeSet +#else +#define MAP_FPUHalfPrecisionModeSet \ + FPUHalfPrecisionModeSet +#endif +#ifdef ROM_FPULazyStackingEnable +#define MAP_FPULazyStackingEnable \ + ROM_FPULazyStackingEnable +#else +#define MAP_FPULazyStackingEnable \ + FPULazyStackingEnable +#endif +#ifdef ROM_FPUNaNModeSet +#define MAP_FPUNaNModeSet \ + ROM_FPUNaNModeSet +#else +#define MAP_FPUNaNModeSet \ + FPUNaNModeSet +#endif +#ifdef ROM_FPURoundingModeSet +#define MAP_FPURoundingModeSet \ + ROM_FPURoundingModeSet +#else +#define MAP_FPURoundingModeSet \ + FPURoundingModeSet +#endif +#ifdef ROM_FPUStackingDisable +#define MAP_FPUStackingDisable \ + ROM_FPUStackingDisable +#else +#define MAP_FPUStackingDisable \ + FPUStackingDisable +#endif +#ifdef ROM_FPUStackingEnable +#define MAP_FPUStackingEnable \ + ROM_FPUStackingEnable +#else +#define MAP_FPUStackingEnable \ + FPUStackingEnable +#endif + +//***************************************************************************** +// +// Macros for the GPIO API. +// +//***************************************************************************** +#ifdef ROM_GPIOPinWrite +#define MAP_GPIOPinWrite \ + ROM_GPIOPinWrite +#else +#define MAP_GPIOPinWrite \ + GPIOPinWrite +#endif +#ifdef ROM_GPIODirModeSet +#define MAP_GPIODirModeSet \ + ROM_GPIODirModeSet +#else +#define MAP_GPIODirModeSet \ + GPIODirModeSet +#endif +#ifdef ROM_GPIODirModeGet +#define MAP_GPIODirModeGet \ + ROM_GPIODirModeGet +#else +#define MAP_GPIODirModeGet \ + GPIODirModeGet +#endif +#ifdef ROM_GPIOIntTypeSet +#define MAP_GPIOIntTypeSet \ + ROM_GPIOIntTypeSet +#else +#define MAP_GPIOIntTypeSet \ + GPIOIntTypeSet +#endif +#ifdef ROM_GPIOIntTypeGet +#define MAP_GPIOIntTypeGet \ + ROM_GPIOIntTypeGet +#else +#define MAP_GPIOIntTypeGet \ + GPIOIntTypeGet +#endif +#ifdef ROM_GPIOPadConfigSet +#define MAP_GPIOPadConfigSet \ + ROM_GPIOPadConfigSet +#else +#define MAP_GPIOPadConfigSet \ + GPIOPadConfigSet +#endif +#ifdef ROM_GPIOPadConfigGet +#define MAP_GPIOPadConfigGet \ + ROM_GPIOPadConfigGet +#else +#define MAP_GPIOPadConfigGet \ + GPIOPadConfigGet +#endif +#ifdef ROM_GPIOPinRead +#define MAP_GPIOPinRead \ + ROM_GPIOPinRead +#else +#define MAP_GPIOPinRead \ + GPIOPinRead +#endif +#ifdef ROM_GPIOPinTypeCAN +#define MAP_GPIOPinTypeCAN \ + ROM_GPIOPinTypeCAN +#else +#define MAP_GPIOPinTypeCAN \ + GPIOPinTypeCAN +#endif +#ifdef ROM_GPIOPinTypeComparator +#define MAP_GPIOPinTypeComparator \ + ROM_GPIOPinTypeComparator +#else +#define MAP_GPIOPinTypeComparator \ + GPIOPinTypeComparator +#endif +#ifdef ROM_GPIOPinTypeGPIOInput +#define MAP_GPIOPinTypeGPIOInput \ + ROM_GPIOPinTypeGPIOInput +#else +#define MAP_GPIOPinTypeGPIOInput \ + GPIOPinTypeGPIOInput +#endif +#ifdef ROM_GPIOPinTypeGPIOOutput +#define MAP_GPIOPinTypeGPIOOutput \ + ROM_GPIOPinTypeGPIOOutput +#else +#define MAP_GPIOPinTypeGPIOOutput \ + GPIOPinTypeGPIOOutput +#endif +#ifdef ROM_GPIOPinTypeI2C +#define MAP_GPIOPinTypeI2C \ + ROM_GPIOPinTypeI2C +#else +#define MAP_GPIOPinTypeI2C \ + GPIOPinTypeI2C +#endif +#ifdef ROM_GPIOPinTypePWM +#define MAP_GPIOPinTypePWM \ + ROM_GPIOPinTypePWM +#else +#define MAP_GPIOPinTypePWM \ + GPIOPinTypePWM +#endif +#ifdef ROM_GPIOPinTypeQEI +#define MAP_GPIOPinTypeQEI \ + ROM_GPIOPinTypeQEI +#else +#define MAP_GPIOPinTypeQEI \ + GPIOPinTypeQEI +#endif +#ifdef ROM_GPIOPinTypeSSI +#define MAP_GPIOPinTypeSSI \ + ROM_GPIOPinTypeSSI +#else +#define MAP_GPIOPinTypeSSI \ + GPIOPinTypeSSI +#endif +#ifdef ROM_GPIOPinTypeTimer +#define MAP_GPIOPinTypeTimer \ + ROM_GPIOPinTypeTimer +#else +#define MAP_GPIOPinTypeTimer \ + GPIOPinTypeTimer +#endif +#ifdef ROM_GPIOPinTypeUART +#define MAP_GPIOPinTypeUART \ + ROM_GPIOPinTypeUART +#else +#define MAP_GPIOPinTypeUART \ + GPIOPinTypeUART +#endif +#ifdef ROM_GPIOPinTypeGPIOOutputOD +#define MAP_GPIOPinTypeGPIOOutputOD \ + ROM_GPIOPinTypeGPIOOutputOD +#else +#define MAP_GPIOPinTypeGPIOOutputOD \ + GPIOPinTypeGPIOOutputOD +#endif +#ifdef ROM_GPIOPinTypeADC +#define MAP_GPIOPinTypeADC \ + ROM_GPIOPinTypeADC +#else +#define MAP_GPIOPinTypeADC \ + GPIOPinTypeADC +#endif +#ifdef ROM_GPIOPinTypeUSBDigital +#define MAP_GPIOPinTypeUSBDigital \ + ROM_GPIOPinTypeUSBDigital +#else +#define MAP_GPIOPinTypeUSBDigital \ + GPIOPinTypeUSBDigital +#endif +#ifdef ROM_GPIOPinConfigure +#define MAP_GPIOPinConfigure \ + ROM_GPIOPinConfigure +#else +#define MAP_GPIOPinConfigure \ + GPIOPinConfigure +#endif +#ifdef ROM_GPIOPinTypeUSBAnalog +#define MAP_GPIOPinTypeUSBAnalog \ + ROM_GPIOPinTypeUSBAnalog +#else +#define MAP_GPIOPinTypeUSBAnalog \ + GPIOPinTypeUSBAnalog +#endif +#ifdef ROM_GPIODMATriggerEnable +#define MAP_GPIODMATriggerEnable \ + ROM_GPIODMATriggerEnable +#else +#define MAP_GPIODMATriggerEnable \ + GPIODMATriggerEnable +#endif +#ifdef ROM_GPIODMATriggerDisable +#define MAP_GPIODMATriggerDisable \ + ROM_GPIODMATriggerDisable +#else +#define MAP_GPIODMATriggerDisable \ + GPIODMATriggerDisable +#endif +#ifdef ROM_GPIOADCTriggerEnable +#define MAP_GPIOADCTriggerEnable \ + ROM_GPIOADCTriggerEnable +#else +#define MAP_GPIOADCTriggerEnable \ + GPIOADCTriggerEnable +#endif +#ifdef ROM_GPIOADCTriggerDisable +#define MAP_GPIOADCTriggerDisable \ + ROM_GPIOADCTriggerDisable +#else +#define MAP_GPIOADCTriggerDisable \ + GPIOADCTriggerDisable +#endif +#ifdef ROM_GPIOPinTypeI2CSCL +#define MAP_GPIOPinTypeI2CSCL \ + ROM_GPIOPinTypeI2CSCL +#else +#define MAP_GPIOPinTypeI2CSCL \ + GPIOPinTypeI2CSCL +#endif +#ifdef ROM_GPIOPinTypeOneWire +#define MAP_GPIOPinTypeOneWire \ + ROM_GPIOPinTypeOneWire +#else +#define MAP_GPIOPinTypeOneWire \ + GPIOPinTypeOneWire +#endif +#ifdef ROM_GPIOPinTypeWakeHigh +#define MAP_GPIOPinTypeWakeHigh \ + ROM_GPIOPinTypeWakeHigh +#else +#define MAP_GPIOPinTypeWakeHigh \ + GPIOPinTypeWakeHigh +#endif +#ifdef ROM_GPIOPinTypeWakeLow +#define MAP_GPIOPinTypeWakeLow \ + ROM_GPIOPinTypeWakeLow +#else +#define MAP_GPIOPinTypeWakeLow \ + GPIOPinTypeWakeLow +#endif +#ifdef ROM_GPIOIntClear +#define MAP_GPIOIntClear \ + ROM_GPIOIntClear +#else +#define MAP_GPIOIntClear \ + GPIOIntClear +#endif +#ifdef ROM_GPIOIntDisable +#define MAP_GPIOIntDisable \ + ROM_GPIOIntDisable +#else +#define MAP_GPIOIntDisable \ + GPIOIntDisable +#endif +#ifdef ROM_GPIOIntEnable +#define MAP_GPIOIntEnable \ + ROM_GPIOIntEnable +#else +#define MAP_GPIOIntEnable \ + GPIOIntEnable +#endif +#ifdef ROM_GPIOIntStatus +#define MAP_GPIOIntStatus \ + ROM_GPIOIntStatus +#else +#define MAP_GPIOIntStatus \ + GPIOIntStatus +#endif +#ifdef ROM_GPIOPinWakeStatus +#define MAP_GPIOPinWakeStatus \ + ROM_GPIOPinWakeStatus +#else +#define MAP_GPIOPinWakeStatus \ + GPIOPinWakeStatus +#endif + +//***************************************************************************** +// +// Macros for the Hibernate API. +// +//***************************************************************************** +#ifdef ROM_HibernateIntClear +#define MAP_HibernateIntClear \ + ROM_HibernateIntClear +#else +#define MAP_HibernateIntClear \ + HibernateIntClear +#endif +#ifdef ROM_HibernateEnableExpClk +#define MAP_HibernateEnableExpClk \ + ROM_HibernateEnableExpClk +#else +#define MAP_HibernateEnableExpClk \ + HibernateEnableExpClk +#endif +#ifdef ROM_HibernateDisable +#define MAP_HibernateDisable \ + ROM_HibernateDisable +#else +#define MAP_HibernateDisable \ + HibernateDisable +#endif +#ifdef ROM_HibernateRTCEnable +#define MAP_HibernateRTCEnable \ + ROM_HibernateRTCEnable +#else +#define MAP_HibernateRTCEnable \ + HibernateRTCEnable +#endif +#ifdef ROM_HibernateRTCDisable +#define MAP_HibernateRTCDisable \ + ROM_HibernateRTCDisable +#else +#define MAP_HibernateRTCDisable \ + HibernateRTCDisable +#endif +#ifdef ROM_HibernateWakeSet +#define MAP_HibernateWakeSet \ + ROM_HibernateWakeSet +#else +#define MAP_HibernateWakeSet \ + HibernateWakeSet +#endif +#ifdef ROM_HibernateWakeGet +#define MAP_HibernateWakeGet \ + ROM_HibernateWakeGet +#else +#define MAP_HibernateWakeGet \ + HibernateWakeGet +#endif +#ifdef ROM_HibernateLowBatSet +#define MAP_HibernateLowBatSet \ + ROM_HibernateLowBatSet +#else +#define MAP_HibernateLowBatSet \ + HibernateLowBatSet +#endif +#ifdef ROM_HibernateLowBatGet +#define MAP_HibernateLowBatGet \ + ROM_HibernateLowBatGet +#else +#define MAP_HibernateLowBatGet \ + HibernateLowBatGet +#endif +#ifdef ROM_HibernateRTCSet +#define MAP_HibernateRTCSet \ + ROM_HibernateRTCSet +#else +#define MAP_HibernateRTCSet \ + HibernateRTCSet +#endif +#ifdef ROM_HibernateRTCGet +#define MAP_HibernateRTCGet \ + ROM_HibernateRTCGet +#else +#define MAP_HibernateRTCGet \ + HibernateRTCGet +#endif +#ifdef ROM_HibernateRTCTrimSet +#define MAP_HibernateRTCTrimSet \ + ROM_HibernateRTCTrimSet +#else +#define MAP_HibernateRTCTrimSet \ + HibernateRTCTrimSet +#endif +#ifdef ROM_HibernateRTCTrimGet +#define MAP_HibernateRTCTrimGet \ + ROM_HibernateRTCTrimGet +#else +#define MAP_HibernateRTCTrimGet \ + HibernateRTCTrimGet +#endif +#ifdef ROM_HibernateDataSet +#define MAP_HibernateDataSet \ + ROM_HibernateDataSet +#else +#define MAP_HibernateDataSet \ + HibernateDataSet +#endif +#ifdef ROM_HibernateDataGet +#define MAP_HibernateDataGet \ + ROM_HibernateDataGet +#else +#define MAP_HibernateDataGet \ + HibernateDataGet +#endif +#ifdef ROM_HibernateRequest +#define MAP_HibernateRequest \ + ROM_HibernateRequest +#else +#define MAP_HibernateRequest \ + HibernateRequest +#endif +#ifdef ROM_HibernateIntEnable +#define MAP_HibernateIntEnable \ + ROM_HibernateIntEnable +#else +#define MAP_HibernateIntEnable \ + HibernateIntEnable +#endif +#ifdef ROM_HibernateIntDisable +#define MAP_HibernateIntDisable \ + ROM_HibernateIntDisable +#else +#define MAP_HibernateIntDisable \ + HibernateIntDisable +#endif +#ifdef ROM_HibernateIntStatus +#define MAP_HibernateIntStatus \ + ROM_HibernateIntStatus +#else +#define MAP_HibernateIntStatus \ + HibernateIntStatus +#endif +#ifdef ROM_HibernateIsActive +#define MAP_HibernateIsActive \ + ROM_HibernateIsActive +#else +#define MAP_HibernateIsActive \ + HibernateIsActive +#endif +#ifdef ROM_HibernateRTCSSGet +#define MAP_HibernateRTCSSGet \ + ROM_HibernateRTCSSGet +#else +#define MAP_HibernateRTCSSGet \ + HibernateRTCSSGet +#endif +#ifdef ROM_HibernateClockConfig +#define MAP_HibernateClockConfig \ + ROM_HibernateClockConfig +#else +#define MAP_HibernateClockConfig \ + HibernateClockConfig +#endif +#ifdef ROM_HibernateBatCheckStart +#define MAP_HibernateBatCheckStart \ + ROM_HibernateBatCheckStart +#else +#define MAP_HibernateBatCheckStart \ + HibernateBatCheckStart +#endif +#ifdef ROM_HibernateBatCheckDone +#define MAP_HibernateBatCheckDone \ + ROM_HibernateBatCheckDone +#else +#define MAP_HibernateBatCheckDone \ + HibernateBatCheckDone +#endif +#ifdef ROM_HibernateGPIORetentionEnable +#define MAP_HibernateGPIORetentionEnable \ + ROM_HibernateGPIORetentionEnable +#else +#define MAP_HibernateGPIORetentionEnable \ + HibernateGPIORetentionEnable +#endif +#ifdef ROM_HibernateGPIORetentionDisable +#define MAP_HibernateGPIORetentionDisable \ + ROM_HibernateGPIORetentionDisable +#else +#define MAP_HibernateGPIORetentionDisable \ + HibernateGPIORetentionDisable +#endif +#ifdef ROM_HibernateGPIORetentionGet +#define MAP_HibernateGPIORetentionGet \ + ROM_HibernateGPIORetentionGet +#else +#define MAP_HibernateGPIORetentionGet \ + HibernateGPIORetentionGet +#endif +#ifdef ROM_HibernateCounterMode +#define MAP_HibernateCounterMode \ + ROM_HibernateCounterMode +#else +#define MAP_HibernateCounterMode \ + HibernateCounterMode +#endif +#ifdef ROM_HibernateCalendarSet +#define MAP_HibernateCalendarSet \ + ROM_HibernateCalendarSet +#else +#define MAP_HibernateCalendarSet \ + HibernateCalendarSet +#endif +#ifdef ROM_HibernateCalendarGet +#define MAP_HibernateCalendarGet \ + ROM_HibernateCalendarGet +#else +#define MAP_HibernateCalendarGet \ + HibernateCalendarGet +#endif +#ifdef ROM_HibernateCalendarMatchSet +#define MAP_HibernateCalendarMatchSet \ + ROM_HibernateCalendarMatchSet +#else +#define MAP_HibernateCalendarMatchSet \ + HibernateCalendarMatchSet +#endif +#ifdef ROM_HibernateCalendarMatchGet +#define MAP_HibernateCalendarMatchGet \ + ROM_HibernateCalendarMatchGet +#else +#define MAP_HibernateCalendarMatchGet \ + HibernateCalendarMatchGet +#endif +#ifdef ROM_HibernateTamperDisable +#define MAP_HibernateTamperDisable \ + ROM_HibernateTamperDisable +#else +#define MAP_HibernateTamperDisable \ + HibernateTamperDisable +#endif +#ifdef ROM_HibernateTamperEnable +#define MAP_HibernateTamperEnable \ + ROM_HibernateTamperEnable +#else +#define MAP_HibernateTamperEnable \ + HibernateTamperEnable +#endif +#ifdef ROM_HibernateTamperEventsClear +#define MAP_HibernateTamperEventsClear \ + ROM_HibernateTamperEventsClear +#else +#define MAP_HibernateTamperEventsClear \ + HibernateTamperEventsClear +#endif +#ifdef ROM_HibernateTamperEventsConfig +#define MAP_HibernateTamperEventsConfig \ + ROM_HibernateTamperEventsConfig +#else +#define MAP_HibernateTamperEventsConfig \ + HibernateTamperEventsConfig +#endif +#ifdef ROM_HibernateTamperEventsGet +#define MAP_HibernateTamperEventsGet \ + ROM_HibernateTamperEventsGet +#else +#define MAP_HibernateTamperEventsGet \ + HibernateTamperEventsGet +#endif +#ifdef ROM_HibernateTamperExtOscValid +#define MAP_HibernateTamperExtOscValid \ + ROM_HibernateTamperExtOscValid +#else +#define MAP_HibernateTamperExtOscValid \ + HibernateTamperExtOscValid +#endif +#ifdef ROM_HibernateTamperExtOscRecover +#define MAP_HibernateTamperExtOscRecover \ + ROM_HibernateTamperExtOscRecover +#else +#define MAP_HibernateTamperExtOscRecover \ + HibernateTamperExtOscRecover +#endif +#ifdef ROM_HibernateTamperIODisable +#define MAP_HibernateTamperIODisable \ + ROM_HibernateTamperIODisable +#else +#define MAP_HibernateTamperIODisable \ + HibernateTamperIODisable +#endif +#ifdef ROM_HibernateTamperIOEnable +#define MAP_HibernateTamperIOEnable \ + ROM_HibernateTamperIOEnable +#else +#define MAP_HibernateTamperIOEnable \ + HibernateTamperIOEnable +#endif +#ifdef ROM_HibernateTamperStatusGet +#define MAP_HibernateTamperStatusGet \ + ROM_HibernateTamperStatusGet +#else +#define MAP_HibernateTamperStatusGet \ + HibernateTamperStatusGet +#endif +#ifdef ROM_HibernateRTCMatchGet +#define MAP_HibernateRTCMatchGet \ + ROM_HibernateRTCMatchGet +#else +#define MAP_HibernateRTCMatchGet \ + HibernateRTCMatchGet +#endif +#ifdef ROM_HibernateRTCMatchSet +#define MAP_HibernateRTCMatchSet \ + ROM_HibernateRTCMatchSet +#else +#define MAP_HibernateRTCMatchSet \ + HibernateRTCMatchSet +#endif +#ifdef ROM_HibernateRTCSSMatchGet +#define MAP_HibernateRTCSSMatchGet \ + ROM_HibernateRTCSSMatchGet +#else +#define MAP_HibernateRTCSSMatchGet \ + HibernateRTCSSMatchGet +#endif +#ifdef ROM_HibernateRTCSSMatchSet +#define MAP_HibernateRTCSSMatchSet \ + ROM_HibernateRTCSSMatchSet +#else +#define MAP_HibernateRTCSSMatchSet \ + HibernateRTCSSMatchSet +#endif + +//***************************************************************************** +// +// Macros for the I2C API. +// +//***************************************************************************** +#ifdef ROM_I2CMasterDataPut +#define MAP_I2CMasterDataPut \ + ROM_I2CMasterDataPut +#else +#define MAP_I2CMasterDataPut \ + I2CMasterDataPut +#endif +#ifdef ROM_I2CMasterInitExpClk +#define MAP_I2CMasterInitExpClk \ + ROM_I2CMasterInitExpClk +#else +#define MAP_I2CMasterInitExpClk \ + I2CMasterInitExpClk +#endif +#ifdef ROM_I2CSlaveInit +#define MAP_I2CSlaveInit \ + ROM_I2CSlaveInit +#else +#define MAP_I2CSlaveInit \ + I2CSlaveInit +#endif +#ifdef ROM_I2CMasterEnable +#define MAP_I2CMasterEnable \ + ROM_I2CMasterEnable +#else +#define MAP_I2CMasterEnable \ + I2CMasterEnable +#endif +#ifdef ROM_I2CSlaveEnable +#define MAP_I2CSlaveEnable \ + ROM_I2CSlaveEnable +#else +#define MAP_I2CSlaveEnable \ + I2CSlaveEnable +#endif +#ifdef ROM_I2CMasterDisable +#define MAP_I2CMasterDisable \ + ROM_I2CMasterDisable +#else +#define MAP_I2CMasterDisable \ + I2CMasterDisable +#endif +#ifdef ROM_I2CSlaveDisable +#define MAP_I2CSlaveDisable \ + ROM_I2CSlaveDisable +#else +#define MAP_I2CSlaveDisable \ + I2CSlaveDisable +#endif +#ifdef ROM_I2CMasterIntEnable +#define MAP_I2CMasterIntEnable \ + ROM_I2CMasterIntEnable +#else +#define MAP_I2CMasterIntEnable \ + I2CMasterIntEnable +#endif +#ifdef ROM_I2CSlaveIntEnable +#define MAP_I2CSlaveIntEnable \ + ROM_I2CSlaveIntEnable +#else +#define MAP_I2CSlaveIntEnable \ + I2CSlaveIntEnable +#endif +#ifdef ROM_I2CMasterIntDisable +#define MAP_I2CMasterIntDisable \ + ROM_I2CMasterIntDisable +#else +#define MAP_I2CMasterIntDisable \ + I2CMasterIntDisable +#endif +#ifdef ROM_I2CSlaveIntDisable +#define MAP_I2CSlaveIntDisable \ + ROM_I2CSlaveIntDisable +#else +#define MAP_I2CSlaveIntDisable \ + I2CSlaveIntDisable +#endif +#ifdef ROM_I2CMasterIntStatus +#define MAP_I2CMasterIntStatus \ + ROM_I2CMasterIntStatus +#else +#define MAP_I2CMasterIntStatus \ + I2CMasterIntStatus +#endif +#ifdef ROM_I2CSlaveIntStatus +#define MAP_I2CSlaveIntStatus \ + ROM_I2CSlaveIntStatus +#else +#define MAP_I2CSlaveIntStatus \ + I2CSlaveIntStatus +#endif +#ifdef ROM_I2CMasterIntClear +#define MAP_I2CMasterIntClear \ + ROM_I2CMasterIntClear +#else +#define MAP_I2CMasterIntClear \ + I2CMasterIntClear +#endif +#ifdef ROM_I2CSlaveIntClear +#define MAP_I2CSlaveIntClear \ + ROM_I2CSlaveIntClear +#else +#define MAP_I2CSlaveIntClear \ + I2CSlaveIntClear +#endif +#ifdef ROM_I2CMasterSlaveAddrSet +#define MAP_I2CMasterSlaveAddrSet \ + ROM_I2CMasterSlaveAddrSet +#else +#define MAP_I2CMasterSlaveAddrSet \ + I2CMasterSlaveAddrSet +#endif +#ifdef ROM_I2CMasterBusy +#define MAP_I2CMasterBusy \ + ROM_I2CMasterBusy +#else +#define MAP_I2CMasterBusy \ + I2CMasterBusy +#endif +#ifdef ROM_I2CMasterBusBusy +#define MAP_I2CMasterBusBusy \ + ROM_I2CMasterBusBusy +#else +#define MAP_I2CMasterBusBusy \ + I2CMasterBusBusy +#endif +#ifdef ROM_I2CMasterControl +#define MAP_I2CMasterControl \ + ROM_I2CMasterControl +#else +#define MAP_I2CMasterControl \ + I2CMasterControl +#endif +#ifdef ROM_I2CMasterErr +#define MAP_I2CMasterErr \ + ROM_I2CMasterErr +#else +#define MAP_I2CMasterErr \ + I2CMasterErr +#endif +#ifdef ROM_I2CMasterDataGet +#define MAP_I2CMasterDataGet \ + ROM_I2CMasterDataGet +#else +#define MAP_I2CMasterDataGet \ + I2CMasterDataGet +#endif +#ifdef ROM_I2CSlaveStatus +#define MAP_I2CSlaveStatus \ + ROM_I2CSlaveStatus +#else +#define MAP_I2CSlaveStatus \ + I2CSlaveStatus +#endif +#ifdef ROM_I2CSlaveDataPut +#define MAP_I2CSlaveDataPut \ + ROM_I2CSlaveDataPut +#else +#define MAP_I2CSlaveDataPut \ + I2CSlaveDataPut +#endif +#ifdef ROM_I2CSlaveDataGet +#define MAP_I2CSlaveDataGet \ + ROM_I2CSlaveDataGet +#else +#define MAP_I2CSlaveDataGet \ + I2CSlaveDataGet +#endif +#ifdef ROM_I2CSlaveIntEnableEx +#define MAP_I2CSlaveIntEnableEx \ + ROM_I2CSlaveIntEnableEx +#else +#define MAP_I2CSlaveIntEnableEx \ + I2CSlaveIntEnableEx +#endif +#ifdef ROM_I2CSlaveIntDisableEx +#define MAP_I2CSlaveIntDisableEx \ + ROM_I2CSlaveIntDisableEx +#else +#define MAP_I2CSlaveIntDisableEx \ + I2CSlaveIntDisableEx +#endif +#ifdef ROM_I2CSlaveIntStatusEx +#define MAP_I2CSlaveIntStatusEx \ + ROM_I2CSlaveIntStatusEx +#else +#define MAP_I2CSlaveIntStatusEx \ + I2CSlaveIntStatusEx +#endif +#ifdef ROM_I2CSlaveIntClearEx +#define MAP_I2CSlaveIntClearEx \ + ROM_I2CSlaveIntClearEx +#else +#define MAP_I2CSlaveIntClearEx \ + I2CSlaveIntClearEx +#endif +#ifdef ROM_I2CMasterIntEnableEx +#define MAP_I2CMasterIntEnableEx \ + ROM_I2CMasterIntEnableEx +#else +#define MAP_I2CMasterIntEnableEx \ + I2CMasterIntEnableEx +#endif +#ifdef ROM_I2CMasterIntDisableEx +#define MAP_I2CMasterIntDisableEx \ + ROM_I2CMasterIntDisableEx +#else +#define MAP_I2CMasterIntDisableEx \ + I2CMasterIntDisableEx +#endif +#ifdef ROM_I2CMasterIntStatusEx +#define MAP_I2CMasterIntStatusEx \ + ROM_I2CMasterIntStatusEx +#else +#define MAP_I2CMasterIntStatusEx \ + I2CMasterIntStatusEx +#endif +#ifdef ROM_I2CMasterIntClearEx +#define MAP_I2CMasterIntClearEx \ + ROM_I2CMasterIntClearEx +#else +#define MAP_I2CMasterIntClearEx \ + I2CMasterIntClearEx +#endif +#ifdef ROM_I2CMasterTimeoutSet +#define MAP_I2CMasterTimeoutSet \ + ROM_I2CMasterTimeoutSet +#else +#define MAP_I2CMasterTimeoutSet \ + I2CMasterTimeoutSet +#endif +#ifdef ROM_I2CSlaveACKOverride +#define MAP_I2CSlaveACKOverride \ + ROM_I2CSlaveACKOverride +#else +#define MAP_I2CSlaveACKOverride \ + I2CSlaveACKOverride +#endif +#ifdef ROM_I2CSlaveACKValueSet +#define MAP_I2CSlaveACKValueSet \ + ROM_I2CSlaveACKValueSet +#else +#define MAP_I2CSlaveACKValueSet \ + I2CSlaveACKValueSet +#endif +#ifdef ROM_I2CSlaveAddressSet +#define MAP_I2CSlaveAddressSet \ + ROM_I2CSlaveAddressSet +#else +#define MAP_I2CSlaveAddressSet \ + I2CSlaveAddressSet +#endif +#ifdef ROM_I2CMasterLineStateGet +#define MAP_I2CMasterLineStateGet \ + ROM_I2CMasterLineStateGet +#else +#define MAP_I2CMasterLineStateGet \ + I2CMasterLineStateGet +#endif +#ifdef ROM_I2CTxFIFOConfigSet +#define MAP_I2CTxFIFOConfigSet \ + ROM_I2CTxFIFOConfigSet +#else +#define MAP_I2CTxFIFOConfigSet \ + I2CTxFIFOConfigSet +#endif +#ifdef ROM_I2CTxFIFOFlush +#define MAP_I2CTxFIFOFlush \ + ROM_I2CTxFIFOFlush +#else +#define MAP_I2CTxFIFOFlush \ + I2CTxFIFOFlush +#endif +#ifdef ROM_I2CRxFIFOConfigSet +#define MAP_I2CRxFIFOConfigSet \ + ROM_I2CRxFIFOConfigSet +#else +#define MAP_I2CRxFIFOConfigSet \ + I2CRxFIFOConfigSet +#endif +#ifdef ROM_I2CRxFIFOFlush +#define MAP_I2CRxFIFOFlush \ + ROM_I2CRxFIFOFlush +#else +#define MAP_I2CRxFIFOFlush \ + I2CRxFIFOFlush +#endif +#ifdef ROM_I2CFIFOStatus +#define MAP_I2CFIFOStatus \ + ROM_I2CFIFOStatus +#else +#define MAP_I2CFIFOStatus \ + I2CFIFOStatus +#endif +#ifdef ROM_I2CFIFODataPut +#define MAP_I2CFIFODataPut \ + ROM_I2CFIFODataPut +#else +#define MAP_I2CFIFODataPut \ + I2CFIFODataPut +#endif +#ifdef ROM_I2CFIFODataPutNonBlocking +#define MAP_I2CFIFODataPutNonBlocking \ + ROM_I2CFIFODataPutNonBlocking +#else +#define MAP_I2CFIFODataPutNonBlocking \ + I2CFIFODataPutNonBlocking +#endif +#ifdef ROM_I2CFIFODataGet +#define MAP_I2CFIFODataGet \ + ROM_I2CFIFODataGet +#else +#define MAP_I2CFIFODataGet \ + I2CFIFODataGet +#endif +#ifdef ROM_I2CFIFODataGetNonBlocking +#define MAP_I2CFIFODataGetNonBlocking \ + ROM_I2CFIFODataGetNonBlocking +#else +#define MAP_I2CFIFODataGetNonBlocking \ + I2CFIFODataGetNonBlocking +#endif +#ifdef ROM_I2CMasterBurstLengthSet +#define MAP_I2CMasterBurstLengthSet \ + ROM_I2CMasterBurstLengthSet +#else +#define MAP_I2CMasterBurstLengthSet \ + I2CMasterBurstLengthSet +#endif +#ifdef ROM_I2CMasterBurstCountGet +#define MAP_I2CMasterBurstCountGet \ + ROM_I2CMasterBurstCountGet +#else +#define MAP_I2CMasterBurstCountGet \ + I2CMasterBurstCountGet +#endif +#ifdef ROM_I2CSlaveFIFODisable +#define MAP_I2CSlaveFIFODisable \ + ROM_I2CSlaveFIFODisable +#else +#define MAP_I2CSlaveFIFODisable \ + I2CSlaveFIFODisable +#endif +#ifdef ROM_I2CSlaveFIFOEnable +#define MAP_I2CSlaveFIFOEnable \ + ROM_I2CSlaveFIFOEnable +#else +#define MAP_I2CSlaveFIFOEnable \ + I2CSlaveFIFOEnable +#endif +#ifdef ROM_I2CMasterGlitchFilterConfigSet +#define MAP_I2CMasterGlitchFilterConfigSet \ + ROM_I2CMasterGlitchFilterConfigSet +#else +#define MAP_I2CMasterGlitchFilterConfigSet \ + I2CMasterGlitchFilterConfigSet +#endif + +//***************************************************************************** +// +// Macros for the Interrupt API. +// +//***************************************************************************** +#ifdef ROM_IntEnable +#define MAP_IntEnable \ + ROM_IntEnable +#else +#define MAP_IntEnable \ + IntEnable +#endif +#ifdef ROM_IntMasterEnable +#define MAP_IntMasterEnable \ + ROM_IntMasterEnable +#else +#define MAP_IntMasterEnable \ + IntMasterEnable +#endif +#ifdef ROM_IntMasterDisable +#define MAP_IntMasterDisable \ + ROM_IntMasterDisable +#else +#define MAP_IntMasterDisable \ + IntMasterDisable +#endif +#ifdef ROM_IntDisable +#define MAP_IntDisable \ + ROM_IntDisable +#else +#define MAP_IntDisable \ + IntDisable +#endif +#ifdef ROM_IntPriorityGroupingSet +#define MAP_IntPriorityGroupingSet \ + ROM_IntPriorityGroupingSet +#else +#define MAP_IntPriorityGroupingSet \ + IntPriorityGroupingSet +#endif +#ifdef ROM_IntPriorityGroupingGet +#define MAP_IntPriorityGroupingGet \ + ROM_IntPriorityGroupingGet +#else +#define MAP_IntPriorityGroupingGet \ + IntPriorityGroupingGet +#endif +#ifdef ROM_IntPrioritySet +#define MAP_IntPrioritySet \ + ROM_IntPrioritySet +#else +#define MAP_IntPrioritySet \ + IntPrioritySet +#endif +#ifdef ROM_IntPriorityGet +#define MAP_IntPriorityGet \ + ROM_IntPriorityGet +#else +#define MAP_IntPriorityGet \ + IntPriorityGet +#endif +#ifdef ROM_IntPendSet +#define MAP_IntPendSet \ + ROM_IntPendSet +#else +#define MAP_IntPendSet \ + IntPendSet +#endif +#ifdef ROM_IntPendClear +#define MAP_IntPendClear \ + ROM_IntPendClear +#else +#define MAP_IntPendClear \ + IntPendClear +#endif +#ifdef ROM_IntPriorityMaskSet +#define MAP_IntPriorityMaskSet \ + ROM_IntPriorityMaskSet +#else +#define MAP_IntPriorityMaskSet \ + IntPriorityMaskSet +#endif +#ifdef ROM_IntPriorityMaskGet +#define MAP_IntPriorityMaskGet \ + ROM_IntPriorityMaskGet +#else +#define MAP_IntPriorityMaskGet \ + IntPriorityMaskGet +#endif +#ifdef ROM_IntIsEnabled +#define MAP_IntIsEnabled \ + ROM_IntIsEnabled +#else +#define MAP_IntIsEnabled \ + IntIsEnabled +#endif +#ifdef ROM_IntTrigger +#define MAP_IntTrigger \ + ROM_IntTrigger +#else +#define MAP_IntTrigger \ + IntTrigger +#endif + +//***************************************************************************** +// +// Macros for the LCD API. +// +//***************************************************************************** +#ifdef ROM_LCDIntStatus +#define MAP_LCDIntStatus \ + ROM_LCDIntStatus +#else +#define MAP_LCDIntStatus \ + LCDIntStatus +#endif +#ifdef ROM_LCDClockReset +#define MAP_LCDClockReset \ + ROM_LCDClockReset +#else +#define MAP_LCDClockReset \ + LCDClockReset +#endif +#ifdef ROM_LCDDMAConfigSet +#define MAP_LCDDMAConfigSet \ + ROM_LCDDMAConfigSet +#else +#define MAP_LCDDMAConfigSet \ + LCDDMAConfigSet +#endif +#ifdef ROM_LCDIDDCommandWrite +#define MAP_LCDIDDCommandWrite \ + ROM_LCDIDDCommandWrite +#else +#define MAP_LCDIDDCommandWrite \ + LCDIDDCommandWrite +#endif +#ifdef ROM_LCDIDDConfigSet +#define MAP_LCDIDDConfigSet \ + ROM_LCDIDDConfigSet +#else +#define MAP_LCDIDDConfigSet \ + LCDIDDConfigSet +#endif +#ifdef ROM_LCDIDDDataRead +#define MAP_LCDIDDDataRead \ + ROM_LCDIDDDataRead +#else +#define MAP_LCDIDDDataRead \ + LCDIDDDataRead +#endif +#ifdef ROM_LCDIDDDataWrite +#define MAP_LCDIDDDataWrite \ + ROM_LCDIDDDataWrite +#else +#define MAP_LCDIDDDataWrite \ + LCDIDDDataWrite +#endif +#ifdef ROM_LCDIDDDMADisable +#define MAP_LCDIDDDMADisable \ + ROM_LCDIDDDMADisable +#else +#define MAP_LCDIDDDMADisable \ + LCDIDDDMADisable +#endif +#ifdef ROM_LCDIDDDMAWrite +#define MAP_LCDIDDDMAWrite \ + ROM_LCDIDDDMAWrite +#else +#define MAP_LCDIDDDMAWrite \ + LCDIDDDMAWrite +#endif +#ifdef ROM_LCDIDDIndexedRead +#define MAP_LCDIDDIndexedRead \ + ROM_LCDIDDIndexedRead +#else +#define MAP_LCDIDDIndexedRead \ + LCDIDDIndexedRead +#endif +#ifdef ROM_LCDIDDIndexedWrite +#define MAP_LCDIDDIndexedWrite \ + ROM_LCDIDDIndexedWrite +#else +#define MAP_LCDIDDIndexedWrite \ + LCDIDDIndexedWrite +#endif +#ifdef ROM_LCDIDDStatusRead +#define MAP_LCDIDDStatusRead \ + ROM_LCDIDDStatusRead +#else +#define MAP_LCDIDDStatusRead \ + LCDIDDStatusRead +#endif +#ifdef ROM_LCDIDDTimingSet +#define MAP_LCDIDDTimingSet \ + ROM_LCDIDDTimingSet +#else +#define MAP_LCDIDDTimingSet \ + LCDIDDTimingSet +#endif +#ifdef ROM_LCDIntClear +#define MAP_LCDIntClear \ + ROM_LCDIntClear +#else +#define MAP_LCDIntClear \ + LCDIntClear +#endif +#ifdef ROM_LCDIntDisable +#define MAP_LCDIntDisable \ + ROM_LCDIntDisable +#else +#define MAP_LCDIntDisable \ + LCDIntDisable +#endif +#ifdef ROM_LCDIntEnable +#define MAP_LCDIntEnable \ + ROM_LCDIntEnable +#else +#define MAP_LCDIntEnable \ + LCDIntEnable +#endif +#ifdef ROM_LCDModeSet +#define MAP_LCDModeSet \ + ROM_LCDModeSet +#else +#define MAP_LCDModeSet \ + LCDModeSet +#endif +#ifdef ROM_LCDRasterACBiasIntCountSet +#define MAP_LCDRasterACBiasIntCountSet \ + ROM_LCDRasterACBiasIntCountSet +#else +#define MAP_LCDRasterACBiasIntCountSet \ + LCDRasterACBiasIntCountSet +#endif +#ifdef ROM_LCDRasterConfigSet +#define MAP_LCDRasterConfigSet \ + ROM_LCDRasterConfigSet +#else +#define MAP_LCDRasterConfigSet \ + LCDRasterConfigSet +#endif +#ifdef ROM_LCDRasterDisable +#define MAP_LCDRasterDisable \ + ROM_LCDRasterDisable +#else +#define MAP_LCDRasterDisable \ + LCDRasterDisable +#endif +#ifdef ROM_LCDRasterEnable +#define MAP_LCDRasterEnable \ + ROM_LCDRasterEnable +#else +#define MAP_LCDRasterEnable \ + LCDRasterEnable +#endif +#ifdef ROM_LCDRasterFrameBufferSet +#define MAP_LCDRasterFrameBufferSet \ + ROM_LCDRasterFrameBufferSet +#else +#define MAP_LCDRasterFrameBufferSet \ + LCDRasterFrameBufferSet +#endif +#ifdef ROM_LCDRasterPaletteSet +#define MAP_LCDRasterPaletteSet \ + ROM_LCDRasterPaletteSet +#else +#define MAP_LCDRasterPaletteSet \ + LCDRasterPaletteSet +#endif +#ifdef ROM_LCDRasterSubPanelConfigSet +#define MAP_LCDRasterSubPanelConfigSet \ + ROM_LCDRasterSubPanelConfigSet +#else +#define MAP_LCDRasterSubPanelConfigSet \ + LCDRasterSubPanelConfigSet +#endif +#ifdef ROM_LCDRasterSubPanelDisable +#define MAP_LCDRasterSubPanelDisable \ + ROM_LCDRasterSubPanelDisable +#else +#define MAP_LCDRasterSubPanelDisable \ + LCDRasterSubPanelDisable +#endif +#ifdef ROM_LCDRasterSubPanelEnable +#define MAP_LCDRasterSubPanelEnable \ + ROM_LCDRasterSubPanelEnable +#else +#define MAP_LCDRasterSubPanelEnable \ + LCDRasterSubPanelEnable +#endif +#ifdef ROM_LCDRasterTimingSet +#define MAP_LCDRasterTimingSet \ + ROM_LCDRasterTimingSet +#else +#define MAP_LCDRasterTimingSet \ + LCDRasterTimingSet +#endif +#ifdef ROM_LCDRasterEnabled +#define MAP_LCDRasterEnabled \ + ROM_LCDRasterEnabled +#else +#define MAP_LCDRasterEnabled \ + LCDRasterEnabled +#endif + +//***************************************************************************** +// +// Macros for the MPU API. +// +//***************************************************************************** +#ifdef ROM_MPUEnable +#define MAP_MPUEnable \ + ROM_MPUEnable +#else +#define MAP_MPUEnable \ + MPUEnable +#endif +#ifdef ROM_MPUDisable +#define MAP_MPUDisable \ + ROM_MPUDisable +#else +#define MAP_MPUDisable \ + MPUDisable +#endif +#ifdef ROM_MPURegionCountGet +#define MAP_MPURegionCountGet \ + ROM_MPURegionCountGet +#else +#define MAP_MPURegionCountGet \ + MPURegionCountGet +#endif +#ifdef ROM_MPURegionEnable +#define MAP_MPURegionEnable \ + ROM_MPURegionEnable +#else +#define MAP_MPURegionEnable \ + MPURegionEnable +#endif +#ifdef ROM_MPURegionDisable +#define MAP_MPURegionDisable \ + ROM_MPURegionDisable +#else +#define MAP_MPURegionDisable \ + MPURegionDisable +#endif +#ifdef ROM_MPURegionSet +#define MAP_MPURegionSet \ + ROM_MPURegionSet +#else +#define MAP_MPURegionSet \ + MPURegionSet +#endif +#ifdef ROM_MPURegionGet +#define MAP_MPURegionGet \ + ROM_MPURegionGet +#else +#define MAP_MPURegionGet \ + MPURegionGet +#endif + +//***************************************************************************** +// +// Macros for the OneWire API. +// +//***************************************************************************** +#ifdef ROM_OneWireIntStatus +#define MAP_OneWireIntStatus \ + ROM_OneWireIntStatus +#else +#define MAP_OneWireIntStatus \ + OneWireIntStatus +#endif +#ifdef ROM_OneWireBusReset +#define MAP_OneWireBusReset \ + ROM_OneWireBusReset +#else +#define MAP_OneWireBusReset \ + OneWireBusReset +#endif +#ifdef ROM_OneWireBusStatus +#define MAP_OneWireBusStatus \ + ROM_OneWireBusStatus +#else +#define MAP_OneWireBusStatus \ + OneWireBusStatus +#endif +#ifdef ROM_OneWireDataGet +#define MAP_OneWireDataGet \ + ROM_OneWireDataGet +#else +#define MAP_OneWireDataGet \ + OneWireDataGet +#endif +#ifdef ROM_OneWireDataGetNonBlocking +#define MAP_OneWireDataGetNonBlocking \ + ROM_OneWireDataGetNonBlocking +#else +#define MAP_OneWireDataGetNonBlocking \ + OneWireDataGetNonBlocking +#endif +#ifdef ROM_OneWireInit +#define MAP_OneWireInit \ + ROM_OneWireInit +#else +#define MAP_OneWireInit \ + OneWireInit +#endif +#ifdef ROM_OneWireIntClear +#define MAP_OneWireIntClear \ + ROM_OneWireIntClear +#else +#define MAP_OneWireIntClear \ + OneWireIntClear +#endif +#ifdef ROM_OneWireIntDisable +#define MAP_OneWireIntDisable \ + ROM_OneWireIntDisable +#else +#define MAP_OneWireIntDisable \ + OneWireIntDisable +#endif +#ifdef ROM_OneWireIntEnable +#define MAP_OneWireIntEnable \ + ROM_OneWireIntEnable +#else +#define MAP_OneWireIntEnable \ + OneWireIntEnable +#endif +#ifdef ROM_OneWireTransaction +#define MAP_OneWireTransaction \ + ROM_OneWireTransaction +#else +#define MAP_OneWireTransaction \ + OneWireTransaction +#endif +#ifdef ROM_OneWireDMADisable +#define MAP_OneWireDMADisable \ + ROM_OneWireDMADisable +#else +#define MAP_OneWireDMADisable \ + OneWireDMADisable +#endif +#ifdef ROM_OneWireDMAEnable +#define MAP_OneWireDMAEnable \ + ROM_OneWireDMAEnable +#else +#define MAP_OneWireDMAEnable \ + OneWireDMAEnable +#endif + +//***************************************************************************** +// +// Macros for the PWM API. +// +//***************************************************************************** +#ifdef ROM_PWMPulseWidthSet +#define MAP_PWMPulseWidthSet \ + ROM_PWMPulseWidthSet +#else +#define MAP_PWMPulseWidthSet \ + PWMPulseWidthSet +#endif +#ifdef ROM_PWMGenConfigure +#define MAP_PWMGenConfigure \ + ROM_PWMGenConfigure +#else +#define MAP_PWMGenConfigure \ + PWMGenConfigure +#endif +#ifdef ROM_PWMGenPeriodSet +#define MAP_PWMGenPeriodSet \ + ROM_PWMGenPeriodSet +#else +#define MAP_PWMGenPeriodSet \ + PWMGenPeriodSet +#endif +#ifdef ROM_PWMGenPeriodGet +#define MAP_PWMGenPeriodGet \ + ROM_PWMGenPeriodGet +#else +#define MAP_PWMGenPeriodGet \ + PWMGenPeriodGet +#endif +#ifdef ROM_PWMGenEnable +#define MAP_PWMGenEnable \ + ROM_PWMGenEnable +#else +#define MAP_PWMGenEnable \ + PWMGenEnable +#endif +#ifdef ROM_PWMGenDisable +#define MAP_PWMGenDisable \ + ROM_PWMGenDisable +#else +#define MAP_PWMGenDisable \ + PWMGenDisable +#endif +#ifdef ROM_PWMPulseWidthGet +#define MAP_PWMPulseWidthGet \ + ROM_PWMPulseWidthGet +#else +#define MAP_PWMPulseWidthGet \ + PWMPulseWidthGet +#endif +#ifdef ROM_PWMDeadBandEnable +#define MAP_PWMDeadBandEnable \ + ROM_PWMDeadBandEnable +#else +#define MAP_PWMDeadBandEnable \ + PWMDeadBandEnable +#endif +#ifdef ROM_PWMDeadBandDisable +#define MAP_PWMDeadBandDisable \ + ROM_PWMDeadBandDisable +#else +#define MAP_PWMDeadBandDisable \ + PWMDeadBandDisable +#endif +#ifdef ROM_PWMSyncUpdate +#define MAP_PWMSyncUpdate \ + ROM_PWMSyncUpdate +#else +#define MAP_PWMSyncUpdate \ + PWMSyncUpdate +#endif +#ifdef ROM_PWMSyncTimeBase +#define MAP_PWMSyncTimeBase \ + ROM_PWMSyncTimeBase +#else +#define MAP_PWMSyncTimeBase \ + PWMSyncTimeBase +#endif +#ifdef ROM_PWMOutputState +#define MAP_PWMOutputState \ + ROM_PWMOutputState +#else +#define MAP_PWMOutputState \ + PWMOutputState +#endif +#ifdef ROM_PWMOutputInvert +#define MAP_PWMOutputInvert \ + ROM_PWMOutputInvert +#else +#define MAP_PWMOutputInvert \ + PWMOutputInvert +#endif +#ifdef ROM_PWMOutputFault +#define MAP_PWMOutputFault \ + ROM_PWMOutputFault +#else +#define MAP_PWMOutputFault \ + PWMOutputFault +#endif +#ifdef ROM_PWMGenIntTrigEnable +#define MAP_PWMGenIntTrigEnable \ + ROM_PWMGenIntTrigEnable +#else +#define MAP_PWMGenIntTrigEnable \ + PWMGenIntTrigEnable +#endif +#ifdef ROM_PWMGenIntTrigDisable +#define MAP_PWMGenIntTrigDisable \ + ROM_PWMGenIntTrigDisable +#else +#define MAP_PWMGenIntTrigDisable \ + PWMGenIntTrigDisable +#endif +#ifdef ROM_PWMGenIntStatus +#define MAP_PWMGenIntStatus \ + ROM_PWMGenIntStatus +#else +#define MAP_PWMGenIntStatus \ + PWMGenIntStatus +#endif +#ifdef ROM_PWMGenIntClear +#define MAP_PWMGenIntClear \ + ROM_PWMGenIntClear +#else +#define MAP_PWMGenIntClear \ + PWMGenIntClear +#endif +#ifdef ROM_PWMIntEnable +#define MAP_PWMIntEnable \ + ROM_PWMIntEnable +#else +#define MAP_PWMIntEnable \ + PWMIntEnable +#endif +#ifdef ROM_PWMIntDisable +#define MAP_PWMIntDisable \ + ROM_PWMIntDisable +#else +#define MAP_PWMIntDisable \ + PWMIntDisable +#endif +#ifdef ROM_PWMFaultIntClear +#define MAP_PWMFaultIntClear \ + ROM_PWMFaultIntClear +#else +#define MAP_PWMFaultIntClear \ + PWMFaultIntClear +#endif +#ifdef ROM_PWMIntStatus +#define MAP_PWMIntStatus \ + ROM_PWMIntStatus +#else +#define MAP_PWMIntStatus \ + PWMIntStatus +#endif +#ifdef ROM_PWMOutputFaultLevel +#define MAP_PWMOutputFaultLevel \ + ROM_PWMOutputFaultLevel +#else +#define MAP_PWMOutputFaultLevel \ + PWMOutputFaultLevel +#endif +#ifdef ROM_PWMFaultIntClearExt +#define MAP_PWMFaultIntClearExt \ + ROM_PWMFaultIntClearExt +#else +#define MAP_PWMFaultIntClearExt \ + PWMFaultIntClearExt +#endif +#ifdef ROM_PWMGenFaultConfigure +#define MAP_PWMGenFaultConfigure \ + ROM_PWMGenFaultConfigure +#else +#define MAP_PWMGenFaultConfigure \ + PWMGenFaultConfigure +#endif +#ifdef ROM_PWMGenFaultTriggerSet +#define MAP_PWMGenFaultTriggerSet \ + ROM_PWMGenFaultTriggerSet +#else +#define MAP_PWMGenFaultTriggerSet \ + PWMGenFaultTriggerSet +#endif +#ifdef ROM_PWMGenFaultTriggerGet +#define MAP_PWMGenFaultTriggerGet \ + ROM_PWMGenFaultTriggerGet +#else +#define MAP_PWMGenFaultTriggerGet \ + PWMGenFaultTriggerGet +#endif +#ifdef ROM_PWMGenFaultStatus +#define MAP_PWMGenFaultStatus \ + ROM_PWMGenFaultStatus +#else +#define MAP_PWMGenFaultStatus \ + PWMGenFaultStatus +#endif +#ifdef ROM_PWMGenFaultClear +#define MAP_PWMGenFaultClear \ + ROM_PWMGenFaultClear +#else +#define MAP_PWMGenFaultClear \ + PWMGenFaultClear +#endif +#ifdef ROM_PWMClockSet +#define MAP_PWMClockSet \ + ROM_PWMClockSet +#else +#define MAP_PWMClockSet \ + PWMClockSet +#endif +#ifdef ROM_PWMClockGet +#define MAP_PWMClockGet \ + ROM_PWMClockGet +#else +#define MAP_PWMClockGet \ + PWMClockGet +#endif +#ifdef ROM_PWMOutputUpdateMode +#define MAP_PWMOutputUpdateMode \ + ROM_PWMOutputUpdateMode +#else +#define MAP_PWMOutputUpdateMode \ + PWMOutputUpdateMode +#endif + +//***************************************************************************** +// +// Macros for the QEI API. +// +//***************************************************************************** +#ifdef ROM_QEIPositionGet +#define MAP_QEIPositionGet \ + ROM_QEIPositionGet +#else +#define MAP_QEIPositionGet \ + QEIPositionGet +#endif +#ifdef ROM_QEIEnable +#define MAP_QEIEnable \ + ROM_QEIEnable +#else +#define MAP_QEIEnable \ + QEIEnable +#endif +#ifdef ROM_QEIDisable +#define MAP_QEIDisable \ + ROM_QEIDisable +#else +#define MAP_QEIDisable \ + QEIDisable +#endif +#ifdef ROM_QEIConfigure +#define MAP_QEIConfigure \ + ROM_QEIConfigure +#else +#define MAP_QEIConfigure \ + QEIConfigure +#endif +#ifdef ROM_QEIPositionSet +#define MAP_QEIPositionSet \ + ROM_QEIPositionSet +#else +#define MAP_QEIPositionSet \ + QEIPositionSet +#endif +#ifdef ROM_QEIDirectionGet +#define MAP_QEIDirectionGet \ + ROM_QEIDirectionGet +#else +#define MAP_QEIDirectionGet \ + QEIDirectionGet +#endif +#ifdef ROM_QEIErrorGet +#define MAP_QEIErrorGet \ + ROM_QEIErrorGet +#else +#define MAP_QEIErrorGet \ + QEIErrorGet +#endif +#ifdef ROM_QEIVelocityEnable +#define MAP_QEIVelocityEnable \ + ROM_QEIVelocityEnable +#else +#define MAP_QEIVelocityEnable \ + QEIVelocityEnable +#endif +#ifdef ROM_QEIVelocityDisable +#define MAP_QEIVelocityDisable \ + ROM_QEIVelocityDisable +#else +#define MAP_QEIVelocityDisable \ + QEIVelocityDisable +#endif +#ifdef ROM_QEIVelocityConfigure +#define MAP_QEIVelocityConfigure \ + ROM_QEIVelocityConfigure +#else +#define MAP_QEIVelocityConfigure \ + QEIVelocityConfigure +#endif +#ifdef ROM_QEIVelocityGet +#define MAP_QEIVelocityGet \ + ROM_QEIVelocityGet +#else +#define MAP_QEIVelocityGet \ + QEIVelocityGet +#endif +#ifdef ROM_QEIIntEnable +#define MAP_QEIIntEnable \ + ROM_QEIIntEnable +#else +#define MAP_QEIIntEnable \ + QEIIntEnable +#endif +#ifdef ROM_QEIIntDisable +#define MAP_QEIIntDisable \ + ROM_QEIIntDisable +#else +#define MAP_QEIIntDisable \ + QEIIntDisable +#endif +#ifdef ROM_QEIIntStatus +#define MAP_QEIIntStatus \ + ROM_QEIIntStatus +#else +#define MAP_QEIIntStatus \ + QEIIntStatus +#endif +#ifdef ROM_QEIIntClear +#define MAP_QEIIntClear \ + ROM_QEIIntClear +#else +#define MAP_QEIIntClear \ + QEIIntClear +#endif + +//***************************************************************************** +// +// Macros for the SHAMD5 API. +// +//***************************************************************************** +#ifdef ROM_SHAMD5IntStatus +#define MAP_SHAMD5IntStatus \ + ROM_SHAMD5IntStatus +#else +#define MAP_SHAMD5IntStatus \ + SHAMD5IntStatus +#endif +#ifdef ROM_SHAMD5ConfigSet +#define MAP_SHAMD5ConfigSet \ + ROM_SHAMD5ConfigSet +#else +#define MAP_SHAMD5ConfigSet \ + SHAMD5ConfigSet +#endif +#ifdef ROM_SHAMD5DataProcess +#define MAP_SHAMD5DataProcess \ + ROM_SHAMD5DataProcess +#else +#define MAP_SHAMD5DataProcess \ + SHAMD5DataProcess +#endif +#ifdef ROM_SHAMD5DataWrite +#define MAP_SHAMD5DataWrite \ + ROM_SHAMD5DataWrite +#else +#define MAP_SHAMD5DataWrite \ + SHAMD5DataWrite +#endif +#ifdef ROM_SHAMD5DataWriteNonBlocking +#define MAP_SHAMD5DataWriteNonBlocking \ + ROM_SHAMD5DataWriteNonBlocking +#else +#define MAP_SHAMD5DataWriteNonBlocking \ + SHAMD5DataWriteNonBlocking +#endif +#ifdef ROM_SHAMD5DMADisable +#define MAP_SHAMD5DMADisable \ + ROM_SHAMD5DMADisable +#else +#define MAP_SHAMD5DMADisable \ + SHAMD5DMADisable +#endif +#ifdef ROM_SHAMD5DMAEnable +#define MAP_SHAMD5DMAEnable \ + ROM_SHAMD5DMAEnable +#else +#define MAP_SHAMD5DMAEnable \ + SHAMD5DMAEnable +#endif +#ifdef ROM_SHAMD5HashLengthSet +#define MAP_SHAMD5HashLengthSet \ + ROM_SHAMD5HashLengthSet +#else +#define MAP_SHAMD5HashLengthSet \ + SHAMD5HashLengthSet +#endif +#ifdef ROM_SHAMD5HMACKeySet +#define MAP_SHAMD5HMACKeySet \ + ROM_SHAMD5HMACKeySet +#else +#define MAP_SHAMD5HMACKeySet \ + SHAMD5HMACKeySet +#endif +#ifdef ROM_SHAMD5HMACPPKeyGenerate +#define MAP_SHAMD5HMACPPKeyGenerate \ + ROM_SHAMD5HMACPPKeyGenerate +#else +#define MAP_SHAMD5HMACPPKeyGenerate \ + SHAMD5HMACPPKeyGenerate +#endif +#ifdef ROM_SHAMD5HMACPPKeySet +#define MAP_SHAMD5HMACPPKeySet \ + ROM_SHAMD5HMACPPKeySet +#else +#define MAP_SHAMD5HMACPPKeySet \ + SHAMD5HMACPPKeySet +#endif +#ifdef ROM_SHAMD5HMACProcess +#define MAP_SHAMD5HMACProcess \ + ROM_SHAMD5HMACProcess +#else +#define MAP_SHAMD5HMACProcess \ + SHAMD5HMACProcess +#endif +#ifdef ROM_SHAMD5IntClear +#define MAP_SHAMD5IntClear \ + ROM_SHAMD5IntClear +#else +#define MAP_SHAMD5IntClear \ + SHAMD5IntClear +#endif +#ifdef ROM_SHAMD5IntDisable +#define MAP_SHAMD5IntDisable \ + ROM_SHAMD5IntDisable +#else +#define MAP_SHAMD5IntDisable \ + SHAMD5IntDisable +#endif +#ifdef ROM_SHAMD5IntEnable +#define MAP_SHAMD5IntEnable \ + ROM_SHAMD5IntEnable +#else +#define MAP_SHAMD5IntEnable \ + SHAMD5IntEnable +#endif +#ifdef ROM_SHAMD5Reset +#define MAP_SHAMD5Reset \ + ROM_SHAMD5Reset +#else +#define MAP_SHAMD5Reset \ + SHAMD5Reset +#endif +#ifdef ROM_SHAMD5ResultRead +#define MAP_SHAMD5ResultRead \ + ROM_SHAMD5ResultRead +#else +#define MAP_SHAMD5ResultRead \ + SHAMD5ResultRead +#endif + +//***************************************************************************** +// +// Macros for the SMBus API. +// +//***************************************************************************** +#ifdef ROM_SMBusMasterIntProcess +#define MAP_SMBusMasterIntProcess \ + ROM_SMBusMasterIntProcess +#else +#define MAP_SMBusMasterIntProcess \ + SMBusMasterIntProcess +#endif +#ifdef ROM_SMBusARPDisable +#define MAP_SMBusARPDisable \ + ROM_SMBusARPDisable +#else +#define MAP_SMBusARPDisable \ + SMBusARPDisable +#endif +#ifdef ROM_SMBusARPEnable +#define MAP_SMBusARPEnable \ + ROM_SMBusARPEnable +#else +#define MAP_SMBusARPEnable \ + SMBusARPEnable +#endif +#ifdef ROM_SMBusARPUDIDPacketDecode +#define MAP_SMBusARPUDIDPacketDecode \ + ROM_SMBusARPUDIDPacketDecode +#else +#define MAP_SMBusARPUDIDPacketDecode \ + SMBusARPUDIDPacketDecode +#endif +#ifdef ROM_SMBusARPUDIDPacketEncode +#define MAP_SMBusARPUDIDPacketEncode \ + ROM_SMBusARPUDIDPacketEncode +#else +#define MAP_SMBusARPUDIDPacketEncode \ + SMBusARPUDIDPacketEncode +#endif +#ifdef ROM_SMBusMasterARPAssignAddress +#define MAP_SMBusMasterARPAssignAddress \ + ROM_SMBusMasterARPAssignAddress +#else +#define MAP_SMBusMasterARPAssignAddress \ + SMBusMasterARPAssignAddress +#endif +#ifdef ROM_SMBusMasterARPGetUDIDDir +#define MAP_SMBusMasterARPGetUDIDDir \ + ROM_SMBusMasterARPGetUDIDDir +#else +#define MAP_SMBusMasterARPGetUDIDDir \ + SMBusMasterARPGetUDIDDir +#endif +#ifdef ROM_SMBusMasterARPGetUDIDGen +#define MAP_SMBusMasterARPGetUDIDGen \ + ROM_SMBusMasterARPGetUDIDGen +#else +#define MAP_SMBusMasterARPGetUDIDGen \ + SMBusMasterARPGetUDIDGen +#endif +#ifdef ROM_SMBusMasterARPNotifyMaster +#define MAP_SMBusMasterARPNotifyMaster \ + ROM_SMBusMasterARPNotifyMaster +#else +#define MAP_SMBusMasterARPNotifyMaster \ + SMBusMasterARPNotifyMaster +#endif +#ifdef ROM_SMBusMasterARPPrepareToARP +#define MAP_SMBusMasterARPPrepareToARP \ + ROM_SMBusMasterARPPrepareToARP +#else +#define MAP_SMBusMasterARPPrepareToARP \ + SMBusMasterARPPrepareToARP +#endif +#ifdef ROM_SMBusMasterARPResetDeviceDir +#define MAP_SMBusMasterARPResetDeviceDir \ + ROM_SMBusMasterARPResetDeviceDir +#else +#define MAP_SMBusMasterARPResetDeviceDir \ + SMBusMasterARPResetDeviceDir +#endif +#ifdef ROM_SMBusMasterARPResetDeviceGen +#define MAP_SMBusMasterARPResetDeviceGen \ + ROM_SMBusMasterARPResetDeviceGen +#else +#define MAP_SMBusMasterARPResetDeviceGen \ + SMBusMasterARPResetDeviceGen +#endif +#ifdef ROM_SMBusMasterBlockProcessCall +#define MAP_SMBusMasterBlockProcessCall \ + ROM_SMBusMasterBlockProcessCall +#else +#define MAP_SMBusMasterBlockProcessCall \ + SMBusMasterBlockProcessCall +#endif +#ifdef ROM_SMBusMasterBlockRead +#define MAP_SMBusMasterBlockRead \ + ROM_SMBusMasterBlockRead +#else +#define MAP_SMBusMasterBlockRead \ + SMBusMasterBlockRead +#endif +#ifdef ROM_SMBusMasterBlockWrite +#define MAP_SMBusMasterBlockWrite \ + ROM_SMBusMasterBlockWrite +#else +#define MAP_SMBusMasterBlockWrite \ + SMBusMasterBlockWrite +#endif +#ifdef ROM_SMBusMasterByteReceive +#define MAP_SMBusMasterByteReceive \ + ROM_SMBusMasterByteReceive +#else +#define MAP_SMBusMasterByteReceive \ + SMBusMasterByteReceive +#endif +#ifdef ROM_SMBusMasterByteSend +#define MAP_SMBusMasterByteSend \ + ROM_SMBusMasterByteSend +#else +#define MAP_SMBusMasterByteSend \ + SMBusMasterByteSend +#endif +#ifdef ROM_SMBusMasterByteWordRead +#define MAP_SMBusMasterByteWordRead \ + ROM_SMBusMasterByteWordRead +#else +#define MAP_SMBusMasterByteWordRead \ + SMBusMasterByteWordRead +#endif +#ifdef ROM_SMBusMasterByteWordWrite +#define MAP_SMBusMasterByteWordWrite \ + ROM_SMBusMasterByteWordWrite +#else +#define MAP_SMBusMasterByteWordWrite \ + SMBusMasterByteWordWrite +#endif +#ifdef ROM_SMBusMasterHostNotify +#define MAP_SMBusMasterHostNotify \ + ROM_SMBusMasterHostNotify +#else +#define MAP_SMBusMasterHostNotify \ + SMBusMasterHostNotify +#endif +#ifdef ROM_SMBusMasterI2CRead +#define MAP_SMBusMasterI2CRead \ + ROM_SMBusMasterI2CRead +#else +#define MAP_SMBusMasterI2CRead \ + SMBusMasterI2CRead +#endif +#ifdef ROM_SMBusMasterI2CWrite +#define MAP_SMBusMasterI2CWrite \ + ROM_SMBusMasterI2CWrite +#else +#define MAP_SMBusMasterI2CWrite \ + SMBusMasterI2CWrite +#endif +#ifdef ROM_SMBusMasterI2CWriteRead +#define MAP_SMBusMasterI2CWriteRead \ + ROM_SMBusMasterI2CWriteRead +#else +#define MAP_SMBusMasterI2CWriteRead \ + SMBusMasterI2CWriteRead +#endif +#ifdef ROM_SMBusMasterInit +#define MAP_SMBusMasterInit \ + ROM_SMBusMasterInit +#else +#define MAP_SMBusMasterInit \ + SMBusMasterInit +#endif +#ifdef ROM_SMBusMasterIntEnable +#define MAP_SMBusMasterIntEnable \ + ROM_SMBusMasterIntEnable +#else +#define MAP_SMBusMasterIntEnable \ + SMBusMasterIntEnable +#endif +#ifdef ROM_SMBusMasterProcessCall +#define MAP_SMBusMasterProcessCall \ + ROM_SMBusMasterProcessCall +#else +#define MAP_SMBusMasterProcessCall \ + SMBusMasterProcessCall +#endif +#ifdef ROM_SMBusMasterQuickCommand +#define MAP_SMBusMasterQuickCommand \ + ROM_SMBusMasterQuickCommand +#else +#define MAP_SMBusMasterQuickCommand \ + SMBusMasterQuickCommand +#endif +#ifdef ROM_SMBusPECDisable +#define MAP_SMBusPECDisable \ + ROM_SMBusPECDisable +#else +#define MAP_SMBusPECDisable \ + SMBusPECDisable +#endif +#ifdef ROM_SMBusPECEnable +#define MAP_SMBusPECEnable \ + ROM_SMBusPECEnable +#else +#define MAP_SMBusPECEnable \ + SMBusPECEnable +#endif +#ifdef ROM_SMBusRxPacketSizeGet +#define MAP_SMBusRxPacketSizeGet \ + ROM_SMBusRxPacketSizeGet +#else +#define MAP_SMBusRxPacketSizeGet \ + SMBusRxPacketSizeGet +#endif +#ifdef ROM_SMBusSlaveACKSend +#define MAP_SMBusSlaveACKSend \ + ROM_SMBusSlaveACKSend +#else +#define MAP_SMBusSlaveACKSend \ + SMBusSlaveACKSend +#endif +#ifdef ROM_SMBusSlaveAddressSet +#define MAP_SMBusSlaveAddressSet \ + ROM_SMBusSlaveAddressSet +#else +#define MAP_SMBusSlaveAddressSet \ + SMBusSlaveAddressSet +#endif +#ifdef ROM_SMBusSlaveARPFlagARGet +#define MAP_SMBusSlaveARPFlagARGet \ + ROM_SMBusSlaveARPFlagARGet +#else +#define MAP_SMBusSlaveARPFlagARGet \ + SMBusSlaveARPFlagARGet +#endif +#ifdef ROM_SMBusSlaveARPFlagARSet +#define MAP_SMBusSlaveARPFlagARSet \ + ROM_SMBusSlaveARPFlagARSet +#else +#define MAP_SMBusSlaveARPFlagARSet \ + SMBusSlaveARPFlagARSet +#endif +#ifdef ROM_SMBusSlaveARPFlagAVGet +#define MAP_SMBusSlaveARPFlagAVGet \ + ROM_SMBusSlaveARPFlagAVGet +#else +#define MAP_SMBusSlaveARPFlagAVGet \ + SMBusSlaveARPFlagAVGet +#endif +#ifdef ROM_SMBusSlaveARPFlagAVSet +#define MAP_SMBusSlaveARPFlagAVSet \ + ROM_SMBusSlaveARPFlagAVSet +#else +#define MAP_SMBusSlaveARPFlagAVSet \ + SMBusSlaveARPFlagAVSet +#endif +#ifdef ROM_SMBusSlaveBlockTransferDisable +#define MAP_SMBusSlaveBlockTransferDisable \ + ROM_SMBusSlaveBlockTransferDisable +#else +#define MAP_SMBusSlaveBlockTransferDisable \ + SMBusSlaveBlockTransferDisable +#endif +#ifdef ROM_SMBusSlaveBlockTransferEnable +#define MAP_SMBusSlaveBlockTransferEnable \ + ROM_SMBusSlaveBlockTransferEnable +#else +#define MAP_SMBusSlaveBlockTransferEnable \ + SMBusSlaveBlockTransferEnable +#endif +#ifdef ROM_SMBusSlaveCommandGet +#define MAP_SMBusSlaveCommandGet \ + ROM_SMBusSlaveCommandGet +#else +#define MAP_SMBusSlaveCommandGet \ + SMBusSlaveCommandGet +#endif +#ifdef ROM_SMBusSlaveI2CDisable +#define MAP_SMBusSlaveI2CDisable \ + ROM_SMBusSlaveI2CDisable +#else +#define MAP_SMBusSlaveI2CDisable \ + SMBusSlaveI2CDisable +#endif +#ifdef ROM_SMBusSlaveI2CEnable +#define MAP_SMBusSlaveI2CEnable \ + ROM_SMBusSlaveI2CEnable +#else +#define MAP_SMBusSlaveI2CEnable \ + SMBusSlaveI2CEnable +#endif +#ifdef ROM_SMBusSlaveInit +#define MAP_SMBusSlaveInit \ + ROM_SMBusSlaveInit +#else +#define MAP_SMBusSlaveInit \ + SMBusSlaveInit +#endif +#ifdef ROM_SMBusSlaveIntAddressGet +#define MAP_SMBusSlaveIntAddressGet \ + ROM_SMBusSlaveIntAddressGet +#else +#define MAP_SMBusSlaveIntAddressGet \ + SMBusSlaveIntAddressGet +#endif +#ifdef ROM_SMBusSlaveIntEnable +#define MAP_SMBusSlaveIntEnable \ + ROM_SMBusSlaveIntEnable +#else +#define MAP_SMBusSlaveIntEnable \ + SMBusSlaveIntEnable +#endif +#ifdef ROM_SMBusSlaveIntProcess +#define MAP_SMBusSlaveIntProcess \ + ROM_SMBusSlaveIntProcess +#else +#define MAP_SMBusSlaveIntProcess \ + SMBusSlaveIntProcess +#endif +#ifdef ROM_SMBusSlaveManualACKDisable +#define MAP_SMBusSlaveManualACKDisable \ + ROM_SMBusSlaveManualACKDisable +#else +#define MAP_SMBusSlaveManualACKDisable \ + SMBusSlaveManualACKDisable +#endif +#ifdef ROM_SMBusSlaveManualACKEnable +#define MAP_SMBusSlaveManualACKEnable \ + ROM_SMBusSlaveManualACKEnable +#else +#define MAP_SMBusSlaveManualACKEnable \ + SMBusSlaveManualACKEnable +#endif +#ifdef ROM_SMBusSlaveManualACKStatusGet +#define MAP_SMBusSlaveManualACKStatusGet \ + ROM_SMBusSlaveManualACKStatusGet +#else +#define MAP_SMBusSlaveManualACKStatusGet \ + SMBusSlaveManualACKStatusGet +#endif +#ifdef ROM_SMBusSlaveProcessCallDisable +#define MAP_SMBusSlaveProcessCallDisable \ + ROM_SMBusSlaveProcessCallDisable +#else +#define MAP_SMBusSlaveProcessCallDisable \ + SMBusSlaveProcessCallDisable +#endif +#ifdef ROM_SMBusSlaveProcessCallEnable +#define MAP_SMBusSlaveProcessCallEnable \ + ROM_SMBusSlaveProcessCallEnable +#else +#define MAP_SMBusSlaveProcessCallEnable \ + SMBusSlaveProcessCallEnable +#endif +#ifdef ROM_SMBusSlaveRxBufferSet +#define MAP_SMBusSlaveRxBufferSet \ + ROM_SMBusSlaveRxBufferSet +#else +#define MAP_SMBusSlaveRxBufferSet \ + SMBusSlaveRxBufferSet +#endif +#ifdef ROM_SMBusSlaveTransferInit +#define MAP_SMBusSlaveTransferInit \ + ROM_SMBusSlaveTransferInit +#else +#define MAP_SMBusSlaveTransferInit \ + SMBusSlaveTransferInit +#endif +#ifdef ROM_SMBusSlaveTxBufferSet +#define MAP_SMBusSlaveTxBufferSet \ + ROM_SMBusSlaveTxBufferSet +#else +#define MAP_SMBusSlaveTxBufferSet \ + SMBusSlaveTxBufferSet +#endif +#ifdef ROM_SMBusSlaveUDIDSet +#define MAP_SMBusSlaveUDIDSet \ + ROM_SMBusSlaveUDIDSet +#else +#define MAP_SMBusSlaveUDIDSet \ + SMBusSlaveUDIDSet +#endif +#ifdef ROM_SMBusStatusGet +#define MAP_SMBusStatusGet \ + ROM_SMBusStatusGet +#else +#define MAP_SMBusStatusGet \ + SMBusStatusGet +#endif +#ifdef ROM_SMBusSlaveDataSend +#define MAP_SMBusSlaveDataSend \ + ROM_SMBusSlaveDataSend +#else +#define MAP_SMBusSlaveDataSend \ + SMBusSlaveDataSend +#endif +#ifdef ROM_SMBusFIFOEnable +#define MAP_SMBusFIFOEnable \ + ROM_SMBusFIFOEnable +#else +#define MAP_SMBusFIFOEnable \ + SMBusFIFOEnable +#endif +#ifdef ROM_SMBusFIFODisable +#define MAP_SMBusFIFODisable \ + ROM_SMBusFIFODisable +#else +#define MAP_SMBusFIFODisable \ + SMBusFIFODisable +#endif +#ifdef ROM_SMBusDMAEnable +#define MAP_SMBusDMAEnable \ + ROM_SMBusDMAEnable +#else +#define MAP_SMBusDMAEnable \ + SMBusDMAEnable +#endif +#ifdef ROM_SMBusDMADisable +#define MAP_SMBusDMADisable \ + ROM_SMBusDMADisable +#else +#define MAP_SMBusDMADisable \ + SMBusDMADisable +#endif + +//***************************************************************************** +// +// Macros for the SPIFlash API. +// +//***************************************************************************** +#ifdef ROM_SPIFlashIntHandler +#define MAP_SPIFlashIntHandler \ + ROM_SPIFlashIntHandler +#else +#define MAP_SPIFlashIntHandler \ + SPIFlashIntHandler +#endif +#ifdef ROM_SPIFlashInit +#define MAP_SPIFlashInit \ + ROM_SPIFlashInit +#else +#define MAP_SPIFlashInit \ + SPIFlashInit +#endif +#ifdef ROM_SPIFlashWriteStatus +#define MAP_SPIFlashWriteStatus \ + ROM_SPIFlashWriteStatus +#else +#define MAP_SPIFlashWriteStatus \ + SPIFlashWriteStatus +#endif +#ifdef ROM_SPIFlashPageProgram +#define MAP_SPIFlashPageProgram \ + ROM_SPIFlashPageProgram +#else +#define MAP_SPIFlashPageProgram \ + SPIFlashPageProgram +#endif +#ifdef ROM_SPIFlashPageProgramNonBlocking +#define MAP_SPIFlashPageProgramNonBlocking \ + ROM_SPIFlashPageProgramNonBlocking +#else +#define MAP_SPIFlashPageProgramNonBlocking \ + SPIFlashPageProgramNonBlocking +#endif +#ifdef ROM_SPIFlashRead +#define MAP_SPIFlashRead \ + ROM_SPIFlashRead +#else +#define MAP_SPIFlashRead \ + SPIFlashRead +#endif +#ifdef ROM_SPIFlashReadNonBlocking +#define MAP_SPIFlashReadNonBlocking \ + ROM_SPIFlashReadNonBlocking +#else +#define MAP_SPIFlashReadNonBlocking \ + SPIFlashReadNonBlocking +#endif +#ifdef ROM_SPIFlashWriteDisable +#define MAP_SPIFlashWriteDisable \ + ROM_SPIFlashWriteDisable +#else +#define MAP_SPIFlashWriteDisable \ + SPIFlashWriteDisable +#endif +#ifdef ROM_SPIFlashReadStatus +#define MAP_SPIFlashReadStatus \ + ROM_SPIFlashReadStatus +#else +#define MAP_SPIFlashReadStatus \ + SPIFlashReadStatus +#endif +#ifdef ROM_SPIFlashWriteEnable +#define MAP_SPIFlashWriteEnable \ + ROM_SPIFlashWriteEnable +#else +#define MAP_SPIFlashWriteEnable \ + SPIFlashWriteEnable +#endif +#ifdef ROM_SPIFlashFastRead +#define MAP_SPIFlashFastRead \ + ROM_SPIFlashFastRead +#else +#define MAP_SPIFlashFastRead \ + SPIFlashFastRead +#endif +#ifdef ROM_SPIFlashFastReadNonBlocking +#define MAP_SPIFlashFastReadNonBlocking \ + ROM_SPIFlashFastReadNonBlocking +#else +#define MAP_SPIFlashFastReadNonBlocking \ + SPIFlashFastReadNonBlocking +#endif +#ifdef ROM_SPIFlashSectorErase +#define MAP_SPIFlashSectorErase \ + ROM_SPIFlashSectorErase +#else +#define MAP_SPIFlashSectorErase \ + SPIFlashSectorErase +#endif +#ifdef ROM_SPIFlashDualRead +#define MAP_SPIFlashDualRead \ + ROM_SPIFlashDualRead +#else +#define MAP_SPIFlashDualRead \ + SPIFlashDualRead +#endif +#ifdef ROM_SPIFlashDualReadNonBlocking +#define MAP_SPIFlashDualReadNonBlocking \ + ROM_SPIFlashDualReadNonBlocking +#else +#define MAP_SPIFlashDualReadNonBlocking \ + SPIFlashDualReadNonBlocking +#endif +#ifdef ROM_SPIFlashBlockErase32 +#define MAP_SPIFlashBlockErase32 \ + ROM_SPIFlashBlockErase32 +#else +#define MAP_SPIFlashBlockErase32 \ + SPIFlashBlockErase32 +#endif +#ifdef ROM_SPIFlashQuadRead +#define MAP_SPIFlashQuadRead \ + ROM_SPIFlashQuadRead +#else +#define MAP_SPIFlashQuadRead \ + SPIFlashQuadRead +#endif +#ifdef ROM_SPIFlashQuadReadNonBlocking +#define MAP_SPIFlashQuadReadNonBlocking \ + ROM_SPIFlashQuadReadNonBlocking +#else +#define MAP_SPIFlashQuadReadNonBlocking \ + SPIFlashQuadReadNonBlocking +#endif +#ifdef ROM_SPIFlashReadID +#define MAP_SPIFlashReadID \ + ROM_SPIFlashReadID +#else +#define MAP_SPIFlashReadID \ + SPIFlashReadID +#endif +#ifdef ROM_SPIFlashChipErase +#define MAP_SPIFlashChipErase \ + ROM_SPIFlashChipErase +#else +#define MAP_SPIFlashChipErase \ + SPIFlashChipErase +#endif +#ifdef ROM_SPIFlashBlockErase64 +#define MAP_SPIFlashBlockErase64 \ + ROM_SPIFlashBlockErase64 +#else +#define MAP_SPIFlashBlockErase64 \ + SPIFlashBlockErase64 +#endif + +//***************************************************************************** +// +// Macros for the SSI API. +// +//***************************************************************************** +#ifdef ROM_SSIDataPut +#define MAP_SSIDataPut \ + ROM_SSIDataPut +#else +#define MAP_SSIDataPut \ + SSIDataPut +#endif +#ifdef ROM_SSIConfigSetExpClk +#define MAP_SSIConfigSetExpClk \ + ROM_SSIConfigSetExpClk +#else +#define MAP_SSIConfigSetExpClk \ + SSIConfigSetExpClk +#endif +#ifdef ROM_SSIEnable +#define MAP_SSIEnable \ + ROM_SSIEnable +#else +#define MAP_SSIEnable \ + SSIEnable +#endif +#ifdef ROM_SSIDisable +#define MAP_SSIDisable \ + ROM_SSIDisable +#else +#define MAP_SSIDisable \ + SSIDisable +#endif +#ifdef ROM_SSIIntEnable +#define MAP_SSIIntEnable \ + ROM_SSIIntEnable +#else +#define MAP_SSIIntEnable \ + SSIIntEnable +#endif +#ifdef ROM_SSIIntDisable +#define MAP_SSIIntDisable \ + ROM_SSIIntDisable +#else +#define MAP_SSIIntDisable \ + SSIIntDisable +#endif +#ifdef ROM_SSIIntStatus +#define MAP_SSIIntStatus \ + ROM_SSIIntStatus +#else +#define MAP_SSIIntStatus \ + SSIIntStatus +#endif +#ifdef ROM_SSIIntClear +#define MAP_SSIIntClear \ + ROM_SSIIntClear +#else +#define MAP_SSIIntClear \ + SSIIntClear +#endif +#ifdef ROM_SSIDataPutNonBlocking +#define MAP_SSIDataPutNonBlocking \ + ROM_SSIDataPutNonBlocking +#else +#define MAP_SSIDataPutNonBlocking \ + SSIDataPutNonBlocking +#endif +#ifdef ROM_SSIDataGet +#define MAP_SSIDataGet \ + ROM_SSIDataGet +#else +#define MAP_SSIDataGet \ + SSIDataGet +#endif +#ifdef ROM_SSIDataGetNonBlocking +#define MAP_SSIDataGetNonBlocking \ + ROM_SSIDataGetNonBlocking +#else +#define MAP_SSIDataGetNonBlocking \ + SSIDataGetNonBlocking +#endif +#ifdef ROM_SSIDMAEnable +#define MAP_SSIDMAEnable \ + ROM_SSIDMAEnable +#else +#define MAP_SSIDMAEnable \ + SSIDMAEnable +#endif +#ifdef ROM_SSIDMADisable +#define MAP_SSIDMADisable \ + ROM_SSIDMADisable +#else +#define MAP_SSIDMADisable \ + SSIDMADisable +#endif +#ifdef ROM_SSIBusy +#define MAP_SSIBusy \ + ROM_SSIBusy +#else +#define MAP_SSIBusy \ + SSIBusy +#endif +#ifdef ROM_SSIClockSourceGet +#define MAP_SSIClockSourceGet \ + ROM_SSIClockSourceGet +#else +#define MAP_SSIClockSourceGet \ + SSIClockSourceGet +#endif +#ifdef ROM_SSIClockSourceSet +#define MAP_SSIClockSourceSet \ + ROM_SSIClockSourceSet +#else +#define MAP_SSIClockSourceSet \ + SSIClockSourceSet +#endif +#ifdef ROM_SSIAdvModeSet +#define MAP_SSIAdvModeSet \ + ROM_SSIAdvModeSet +#else +#define MAP_SSIAdvModeSet \ + SSIAdvModeSet +#endif +#ifdef ROM_SSIAdvDataPutFrameEnd +#define MAP_SSIAdvDataPutFrameEnd \ + ROM_SSIAdvDataPutFrameEnd +#else +#define MAP_SSIAdvDataPutFrameEnd \ + SSIAdvDataPutFrameEnd +#endif +#ifdef ROM_SSIAdvDataPutFrameEndNonBlocking +#define MAP_SSIAdvDataPutFrameEndNonBlocking \ + ROM_SSIAdvDataPutFrameEndNonBlocking +#else +#define MAP_SSIAdvDataPutFrameEndNonBlocking \ + SSIAdvDataPutFrameEndNonBlocking +#endif +#ifdef ROM_SSIAdvFrameHoldEnable +#define MAP_SSIAdvFrameHoldEnable \ + ROM_SSIAdvFrameHoldEnable +#else +#define MAP_SSIAdvFrameHoldEnable \ + SSIAdvFrameHoldEnable +#endif +#ifdef ROM_SSIAdvFrameHoldDisable +#define MAP_SSIAdvFrameHoldDisable \ + ROM_SSIAdvFrameHoldDisable +#else +#define MAP_SSIAdvFrameHoldDisable \ + SSIAdvFrameHoldDisable +#endif + +//***************************************************************************** +// +// Macros for the SysCtl API. +// +//***************************************************************************** +#ifdef ROM_SysCtlSleep +#define MAP_SysCtlSleep \ + ROM_SysCtlSleep +#else +#define MAP_SysCtlSleep \ + SysCtlSleep +#endif +#ifdef ROM_SysCtlSRAMSizeGet +#define MAP_SysCtlSRAMSizeGet \ + ROM_SysCtlSRAMSizeGet +#else +#define MAP_SysCtlSRAMSizeGet \ + SysCtlSRAMSizeGet +#endif +#ifdef ROM_SysCtlFlashSizeGet +#define MAP_SysCtlFlashSizeGet \ + ROM_SysCtlFlashSizeGet +#else +#define MAP_SysCtlFlashSizeGet \ + SysCtlFlashSizeGet +#endif +#ifdef ROM_SysCtlPeripheralPresent +#define MAP_SysCtlPeripheralPresent \ + ROM_SysCtlPeripheralPresent +#else +#define MAP_SysCtlPeripheralPresent \ + SysCtlPeripheralPresent +#endif +#ifdef ROM_SysCtlPeripheralReset +#define MAP_SysCtlPeripheralReset \ + ROM_SysCtlPeripheralReset +#else +#define MAP_SysCtlPeripheralReset \ + SysCtlPeripheralReset +#endif +#ifdef ROM_SysCtlPeripheralEnable +#define MAP_SysCtlPeripheralEnable \ + ROM_SysCtlPeripheralEnable +#else +#define MAP_SysCtlPeripheralEnable \ + SysCtlPeripheralEnable +#endif +#ifdef ROM_SysCtlPeripheralDisable +#define MAP_SysCtlPeripheralDisable \ + ROM_SysCtlPeripheralDisable +#else +#define MAP_SysCtlPeripheralDisable \ + SysCtlPeripheralDisable +#endif +#ifdef ROM_SysCtlPeripheralSleepEnable +#define MAP_SysCtlPeripheralSleepEnable \ + ROM_SysCtlPeripheralSleepEnable +#else +#define MAP_SysCtlPeripheralSleepEnable \ + SysCtlPeripheralSleepEnable +#endif +#ifdef ROM_SysCtlPeripheralSleepDisable +#define MAP_SysCtlPeripheralSleepDisable \ + ROM_SysCtlPeripheralSleepDisable +#else +#define MAP_SysCtlPeripheralSleepDisable \ + SysCtlPeripheralSleepDisable +#endif +#ifdef ROM_SysCtlPeripheralDeepSleepEnable +#define MAP_SysCtlPeripheralDeepSleepEnable \ + ROM_SysCtlPeripheralDeepSleepEnable +#else +#define MAP_SysCtlPeripheralDeepSleepEnable \ + SysCtlPeripheralDeepSleepEnable +#endif +#ifdef ROM_SysCtlPeripheralDeepSleepDisable +#define MAP_SysCtlPeripheralDeepSleepDisable \ + ROM_SysCtlPeripheralDeepSleepDisable +#else +#define MAP_SysCtlPeripheralDeepSleepDisable \ + SysCtlPeripheralDeepSleepDisable +#endif +#ifdef ROM_SysCtlPeripheralClockGating +#define MAP_SysCtlPeripheralClockGating \ + ROM_SysCtlPeripheralClockGating +#else +#define MAP_SysCtlPeripheralClockGating \ + SysCtlPeripheralClockGating +#endif +#ifdef ROM_SysCtlIntEnable +#define MAP_SysCtlIntEnable \ + ROM_SysCtlIntEnable +#else +#define MAP_SysCtlIntEnable \ + SysCtlIntEnable +#endif +#ifdef ROM_SysCtlIntDisable +#define MAP_SysCtlIntDisable \ + ROM_SysCtlIntDisable +#else +#define MAP_SysCtlIntDisable \ + SysCtlIntDisable +#endif +#ifdef ROM_SysCtlIntClear +#define MAP_SysCtlIntClear \ + ROM_SysCtlIntClear +#else +#define MAP_SysCtlIntClear \ + SysCtlIntClear +#endif +#ifdef ROM_SysCtlIntStatus +#define MAP_SysCtlIntStatus \ + ROM_SysCtlIntStatus +#else +#define MAP_SysCtlIntStatus \ + SysCtlIntStatus +#endif +#ifdef ROM_SysCtlReset +#define MAP_SysCtlReset \ + ROM_SysCtlReset +#else +#define MAP_SysCtlReset \ + SysCtlReset +#endif +#ifdef ROM_SysCtlDeepSleep +#define MAP_SysCtlDeepSleep \ + ROM_SysCtlDeepSleep +#else +#define MAP_SysCtlDeepSleep \ + SysCtlDeepSleep +#endif +#ifdef ROM_SysCtlResetCauseGet +#define MAP_SysCtlResetCauseGet \ + ROM_SysCtlResetCauseGet +#else +#define MAP_SysCtlResetCauseGet \ + SysCtlResetCauseGet +#endif +#ifdef ROM_SysCtlResetCauseClear +#define MAP_SysCtlResetCauseClear \ + ROM_SysCtlResetCauseClear +#else +#define MAP_SysCtlResetCauseClear \ + SysCtlResetCauseClear +#endif +#ifdef ROM_SysCtlClockSet +#define MAP_SysCtlClockSet \ + ROM_SysCtlClockSet +#else +#define MAP_SysCtlClockSet \ + SysCtlClockSet +#endif +#ifdef ROM_SysCtlClockGet +#define MAP_SysCtlClockGet \ + ROM_SysCtlClockGet +#else +#define MAP_SysCtlClockGet \ + SysCtlClockGet +#endif +#ifdef ROM_SysCtlPWMClockSet +#define MAP_SysCtlPWMClockSet \ + ROM_SysCtlPWMClockSet +#else +#define MAP_SysCtlPWMClockSet \ + SysCtlPWMClockSet +#endif +#ifdef ROM_SysCtlPWMClockGet +#define MAP_SysCtlPWMClockGet \ + ROM_SysCtlPWMClockGet +#else +#define MAP_SysCtlPWMClockGet \ + SysCtlPWMClockGet +#endif +#ifdef ROM_SysCtlUSBPLLEnable +#define MAP_SysCtlUSBPLLEnable \ + ROM_SysCtlUSBPLLEnable +#else +#define MAP_SysCtlUSBPLLEnable \ + SysCtlUSBPLLEnable +#endif +#ifdef ROM_SysCtlUSBPLLDisable +#define MAP_SysCtlUSBPLLDisable \ + ROM_SysCtlUSBPLLDisable +#else +#define MAP_SysCtlUSBPLLDisable \ + SysCtlUSBPLLDisable +#endif +#ifdef ROM_SysCtlDelay +#define MAP_SysCtlDelay \ + ROM_SysCtlDelay +#else +#define MAP_SysCtlDelay \ + SysCtlDelay +#endif +#ifdef ROM_SysCtlPeripheralReady +#define MAP_SysCtlPeripheralReady \ + ROM_SysCtlPeripheralReady +#else +#define MAP_SysCtlPeripheralReady \ + SysCtlPeripheralReady +#endif +#ifdef ROM_SysCtlPeripheralPowerOn +#define MAP_SysCtlPeripheralPowerOn \ + ROM_SysCtlPeripheralPowerOn +#else +#define MAP_SysCtlPeripheralPowerOn \ + SysCtlPeripheralPowerOn +#endif +#ifdef ROM_SysCtlPeripheralPowerOff +#define MAP_SysCtlPeripheralPowerOff \ + ROM_SysCtlPeripheralPowerOff +#else +#define MAP_SysCtlPeripheralPowerOff \ + SysCtlPeripheralPowerOff +#endif +#ifdef ROM_SysCtlMOSCConfigSet +#define MAP_SysCtlMOSCConfigSet \ + ROM_SysCtlMOSCConfigSet +#else +#define MAP_SysCtlMOSCConfigSet \ + SysCtlMOSCConfigSet +#endif +#ifdef ROM_SysCtlPIOSCCalibrate +#define MAP_SysCtlPIOSCCalibrate \ + ROM_SysCtlPIOSCCalibrate +#else +#define MAP_SysCtlPIOSCCalibrate \ + SysCtlPIOSCCalibrate +#endif +#ifdef ROM_SysCtlDeepSleepClockSet +#define MAP_SysCtlDeepSleepClockSet \ + ROM_SysCtlDeepSleepClockSet +#else +#define MAP_SysCtlDeepSleepClockSet \ + SysCtlDeepSleepClockSet +#endif +#ifdef ROM_SysCtlDeepSleepClockConfigSet +#define MAP_SysCtlDeepSleepClockConfigSet \ + ROM_SysCtlDeepSleepClockConfigSet +#else +#define MAP_SysCtlDeepSleepClockConfigSet \ + SysCtlDeepSleepClockConfigSet +#endif +#ifdef ROM_SysCtlClockFreqSet +#define MAP_SysCtlClockFreqSet \ + ROM_SysCtlClockFreqSet +#else +#define MAP_SysCtlClockFreqSet \ + SysCtlClockFreqSet +#endif +#ifdef ROM_SysCtlResetBehaviorSet +#define MAP_SysCtlResetBehaviorSet \ + ROM_SysCtlResetBehaviorSet +#else +#define MAP_SysCtlResetBehaviorSet \ + SysCtlResetBehaviorSet +#endif +#ifdef ROM_SysCtlResetBehaviorGet +#define MAP_SysCtlResetBehaviorGet \ + ROM_SysCtlResetBehaviorGet +#else +#define MAP_SysCtlResetBehaviorGet \ + SysCtlResetBehaviorGet +#endif +#ifdef ROM_SysCtlFlashSectorSizeGet +#define MAP_SysCtlFlashSectorSizeGet \ + ROM_SysCtlFlashSectorSizeGet +#else +#define MAP_SysCtlFlashSectorSizeGet \ + SysCtlFlashSectorSizeGet +#endif +#ifdef ROM_SysCtlVoltageEventConfig +#define MAP_SysCtlVoltageEventConfig \ + ROM_SysCtlVoltageEventConfig +#else +#define MAP_SysCtlVoltageEventConfig \ + SysCtlVoltageEventConfig +#endif +#ifdef ROM_SysCtlVoltageEventStatus +#define MAP_SysCtlVoltageEventStatus \ + ROM_SysCtlVoltageEventStatus +#else +#define MAP_SysCtlVoltageEventStatus \ + SysCtlVoltageEventStatus +#endif +#ifdef ROM_SysCtlVoltageEventClear +#define MAP_SysCtlVoltageEventClear \ + ROM_SysCtlVoltageEventClear +#else +#define MAP_SysCtlVoltageEventClear \ + SysCtlVoltageEventClear +#endif +#ifdef ROM_SysCtlNMIStatus +#define MAP_SysCtlNMIStatus \ + ROM_SysCtlNMIStatus +#else +#define MAP_SysCtlNMIStatus \ + SysCtlNMIStatus +#endif +#ifdef ROM_SysCtlNMIClear +#define MAP_SysCtlNMIClear \ + ROM_SysCtlNMIClear +#else +#define MAP_SysCtlNMIClear \ + SysCtlNMIClear +#endif +#ifdef ROM_SysCtlClockOutConfig +#define MAP_SysCtlClockOutConfig \ + ROM_SysCtlClockOutConfig +#else +#define MAP_SysCtlClockOutConfig \ + SysCtlClockOutConfig +#endif +#ifdef ROM_SysCtlAltClkConfig +#define MAP_SysCtlAltClkConfig \ + ROM_SysCtlAltClkConfig +#else +#define MAP_SysCtlAltClkConfig \ + SysCtlAltClkConfig +#endif + +//***************************************************************************** +// +// Macros for the SysExc API. +// +//***************************************************************************** +#ifdef ROM_SysExcIntStatus +#define MAP_SysExcIntStatus \ + ROM_SysExcIntStatus +#else +#define MAP_SysExcIntStatus \ + SysExcIntStatus +#endif +#ifdef ROM_SysExcIntClear +#define MAP_SysExcIntClear \ + ROM_SysExcIntClear +#else +#define MAP_SysExcIntClear \ + SysExcIntClear +#endif +#ifdef ROM_SysExcIntDisable +#define MAP_SysExcIntDisable \ + ROM_SysExcIntDisable +#else +#define MAP_SysExcIntDisable \ + SysExcIntDisable +#endif +#ifdef ROM_SysExcIntEnable +#define MAP_SysExcIntEnable \ + ROM_SysExcIntEnable +#else +#define MAP_SysExcIntEnable \ + SysExcIntEnable +#endif + +//***************************************************************************** +// +// Macros for the SysTick API. +// +//***************************************************************************** +#ifdef ROM_SysTickValueGet +#define MAP_SysTickValueGet \ + ROM_SysTickValueGet +#else +#define MAP_SysTickValueGet \ + SysTickValueGet +#endif +#ifdef ROM_SysTickEnable +#define MAP_SysTickEnable \ + ROM_SysTickEnable +#else +#define MAP_SysTickEnable \ + SysTickEnable +#endif +#ifdef ROM_SysTickDisable +#define MAP_SysTickDisable \ + ROM_SysTickDisable +#else +#define MAP_SysTickDisable \ + SysTickDisable +#endif +#ifdef ROM_SysTickIntEnable +#define MAP_SysTickIntEnable \ + ROM_SysTickIntEnable +#else +#define MAP_SysTickIntEnable \ + SysTickIntEnable +#endif +#ifdef ROM_SysTickIntDisable +#define MAP_SysTickIntDisable \ + ROM_SysTickIntDisable +#else +#define MAP_SysTickIntDisable \ + SysTickIntDisable +#endif +#ifdef ROM_SysTickPeriodSet +#define MAP_SysTickPeriodSet \ + ROM_SysTickPeriodSet +#else +#define MAP_SysTickPeriodSet \ + SysTickPeriodSet +#endif +#ifdef ROM_SysTickPeriodGet +#define MAP_SysTickPeriodGet \ + ROM_SysTickPeriodGet +#else +#define MAP_SysTickPeriodGet \ + SysTickPeriodGet +#endif + +//***************************************************************************** +// +// Macros for the Timer API. +// +//***************************************************************************** +#ifdef ROM_TimerIntClear +#define MAP_TimerIntClear \ + ROM_TimerIntClear +#else +#define MAP_TimerIntClear \ + TimerIntClear +#endif +#ifdef ROM_TimerEnable +#define MAP_TimerEnable \ + ROM_TimerEnable +#else +#define MAP_TimerEnable \ + TimerEnable +#endif +#ifdef ROM_TimerDisable +#define MAP_TimerDisable \ + ROM_TimerDisable +#else +#define MAP_TimerDisable \ + TimerDisable +#endif +#ifdef ROM_TimerConfigure +#define MAP_TimerConfigure \ + ROM_TimerConfigure +#else +#define MAP_TimerConfigure \ + TimerConfigure +#endif +#ifdef ROM_TimerControlLevel +#define MAP_TimerControlLevel \ + ROM_TimerControlLevel +#else +#define MAP_TimerControlLevel \ + TimerControlLevel +#endif +#ifdef ROM_TimerControlTrigger +#define MAP_TimerControlTrigger \ + ROM_TimerControlTrigger +#else +#define MAP_TimerControlTrigger \ + TimerControlTrigger +#endif +#ifdef ROM_TimerControlEvent +#define MAP_TimerControlEvent \ + ROM_TimerControlEvent +#else +#define MAP_TimerControlEvent \ + TimerControlEvent +#endif +#ifdef ROM_TimerControlStall +#define MAP_TimerControlStall \ + ROM_TimerControlStall +#else +#define MAP_TimerControlStall \ + TimerControlStall +#endif +#ifdef ROM_TimerRTCEnable +#define MAP_TimerRTCEnable \ + ROM_TimerRTCEnable +#else +#define MAP_TimerRTCEnable \ + TimerRTCEnable +#endif +#ifdef ROM_TimerRTCDisable +#define MAP_TimerRTCDisable \ + ROM_TimerRTCDisable +#else +#define MAP_TimerRTCDisable \ + TimerRTCDisable +#endif +#ifdef ROM_TimerPrescaleSet +#define MAP_TimerPrescaleSet \ + ROM_TimerPrescaleSet +#else +#define MAP_TimerPrescaleSet \ + TimerPrescaleSet +#endif +#ifdef ROM_TimerPrescaleGet +#define MAP_TimerPrescaleGet \ + ROM_TimerPrescaleGet +#else +#define MAP_TimerPrescaleGet \ + TimerPrescaleGet +#endif +#ifdef ROM_TimerPrescaleMatchSet +#define MAP_TimerPrescaleMatchSet \ + ROM_TimerPrescaleMatchSet +#else +#define MAP_TimerPrescaleMatchSet \ + TimerPrescaleMatchSet +#endif +#ifdef ROM_TimerPrescaleMatchGet +#define MAP_TimerPrescaleMatchGet \ + ROM_TimerPrescaleMatchGet +#else +#define MAP_TimerPrescaleMatchGet \ + TimerPrescaleMatchGet +#endif +#ifdef ROM_TimerLoadSet +#define MAP_TimerLoadSet \ + ROM_TimerLoadSet +#else +#define MAP_TimerLoadSet \ + TimerLoadSet +#endif +#ifdef ROM_TimerLoadGet +#define MAP_TimerLoadGet \ + ROM_TimerLoadGet +#else +#define MAP_TimerLoadGet \ + TimerLoadGet +#endif +#ifdef ROM_TimerValueGet +#define MAP_TimerValueGet \ + ROM_TimerValueGet +#else +#define MAP_TimerValueGet \ + TimerValueGet +#endif +#ifdef ROM_TimerMatchSet +#define MAP_TimerMatchSet \ + ROM_TimerMatchSet +#else +#define MAP_TimerMatchSet \ + TimerMatchSet +#endif +#ifdef ROM_TimerMatchGet +#define MAP_TimerMatchGet \ + ROM_TimerMatchGet +#else +#define MAP_TimerMatchGet \ + TimerMatchGet +#endif +#ifdef ROM_TimerIntEnable +#define MAP_TimerIntEnable \ + ROM_TimerIntEnable +#else +#define MAP_TimerIntEnable \ + TimerIntEnable +#endif +#ifdef ROM_TimerIntDisable +#define MAP_TimerIntDisable \ + ROM_TimerIntDisable +#else +#define MAP_TimerIntDisable \ + TimerIntDisable +#endif +#ifdef ROM_TimerIntStatus +#define MAP_TimerIntStatus \ + ROM_TimerIntStatus +#else +#define MAP_TimerIntStatus \ + TimerIntStatus +#endif +#ifdef ROM_TimerControlWaitOnTrigger +#define MAP_TimerControlWaitOnTrigger \ + ROM_TimerControlWaitOnTrigger +#else +#define MAP_TimerControlWaitOnTrigger \ + TimerControlWaitOnTrigger +#endif +#ifdef ROM_TimerLoadSet64 +#define MAP_TimerLoadSet64 \ + ROM_TimerLoadSet64 +#else +#define MAP_TimerLoadSet64 \ + TimerLoadSet64 +#endif +#ifdef ROM_TimerLoadGet64 +#define MAP_TimerLoadGet64 \ + ROM_TimerLoadGet64 +#else +#define MAP_TimerLoadGet64 \ + TimerLoadGet64 +#endif +#ifdef ROM_TimerValueGet64 +#define MAP_TimerValueGet64 \ + ROM_TimerValueGet64 +#else +#define MAP_TimerValueGet64 \ + TimerValueGet64 +#endif +#ifdef ROM_TimerMatchSet64 +#define MAP_TimerMatchSet64 \ + ROM_TimerMatchSet64 +#else +#define MAP_TimerMatchSet64 \ + TimerMatchSet64 +#endif +#ifdef ROM_TimerMatchGet64 +#define MAP_TimerMatchGet64 \ + ROM_TimerMatchGet64 +#else +#define MAP_TimerMatchGet64 \ + TimerMatchGet64 +#endif +#ifdef ROM_TimerClockSourceGet +#define MAP_TimerClockSourceGet \ + ROM_TimerClockSourceGet +#else +#define MAP_TimerClockSourceGet \ + TimerClockSourceGet +#endif +#ifdef ROM_TimerClockSourceSet +#define MAP_TimerClockSourceSet \ + ROM_TimerClockSourceSet +#else +#define MAP_TimerClockSourceSet \ + TimerClockSourceSet +#endif +#ifdef ROM_TimerADCEventGet +#define MAP_TimerADCEventGet \ + ROM_TimerADCEventGet +#else +#define MAP_TimerADCEventGet \ + TimerADCEventGet +#endif +#ifdef ROM_TimerADCEventSet +#define MAP_TimerADCEventSet \ + ROM_TimerADCEventSet +#else +#define MAP_TimerADCEventSet \ + TimerADCEventSet +#endif +#ifdef ROM_TimerDMAEventGet +#define MAP_TimerDMAEventGet \ + ROM_TimerDMAEventGet +#else +#define MAP_TimerDMAEventGet \ + TimerDMAEventGet +#endif +#ifdef ROM_TimerDMAEventSet +#define MAP_TimerDMAEventSet \ + ROM_TimerDMAEventSet +#else +#define MAP_TimerDMAEventSet \ + TimerDMAEventSet +#endif +#ifdef ROM_TimerSynchronize +#define MAP_TimerSynchronize \ + ROM_TimerSynchronize +#else +#define MAP_TimerSynchronize \ + TimerSynchronize +#endif + +//***************************************************************************** +// +// Macros for the UART API. +// +//***************************************************************************** +#ifdef ROM_UARTCharPut +#define MAP_UARTCharPut \ + ROM_UARTCharPut +#else +#define MAP_UARTCharPut \ + UARTCharPut +#endif +#ifdef ROM_UARTParityModeSet +#define MAP_UARTParityModeSet \ + ROM_UARTParityModeSet +#else +#define MAP_UARTParityModeSet \ + UARTParityModeSet +#endif +#ifdef ROM_UARTParityModeGet +#define MAP_UARTParityModeGet \ + ROM_UARTParityModeGet +#else +#define MAP_UARTParityModeGet \ + UARTParityModeGet +#endif +#ifdef ROM_UARTFIFOLevelSet +#define MAP_UARTFIFOLevelSet \ + ROM_UARTFIFOLevelSet +#else +#define MAP_UARTFIFOLevelSet \ + UARTFIFOLevelSet +#endif +#ifdef ROM_UARTFIFOLevelGet +#define MAP_UARTFIFOLevelGet \ + ROM_UARTFIFOLevelGet +#else +#define MAP_UARTFIFOLevelGet \ + UARTFIFOLevelGet +#endif +#ifdef ROM_UARTConfigSetExpClk +#define MAP_UARTConfigSetExpClk \ + ROM_UARTConfigSetExpClk +#else +#define MAP_UARTConfigSetExpClk \ + UARTConfigSetExpClk +#endif +#ifdef ROM_UARTConfigGetExpClk +#define MAP_UARTConfigGetExpClk \ + ROM_UARTConfigGetExpClk +#else +#define MAP_UARTConfigGetExpClk \ + UARTConfigGetExpClk +#endif +#ifdef ROM_UARTEnable +#define MAP_UARTEnable \ + ROM_UARTEnable +#else +#define MAP_UARTEnable \ + UARTEnable +#endif +#ifdef ROM_UARTDisable +#define MAP_UARTDisable \ + ROM_UARTDisable +#else +#define MAP_UARTDisable \ + UARTDisable +#endif +#ifdef ROM_UARTEnableSIR +#define MAP_UARTEnableSIR \ + ROM_UARTEnableSIR +#else +#define MAP_UARTEnableSIR \ + UARTEnableSIR +#endif +#ifdef ROM_UARTDisableSIR +#define MAP_UARTDisableSIR \ + ROM_UARTDisableSIR +#else +#define MAP_UARTDisableSIR \ + UARTDisableSIR +#endif +#ifdef ROM_UARTCharsAvail +#define MAP_UARTCharsAvail \ + ROM_UARTCharsAvail +#else +#define MAP_UARTCharsAvail \ + UARTCharsAvail +#endif +#ifdef ROM_UARTSpaceAvail +#define MAP_UARTSpaceAvail \ + ROM_UARTSpaceAvail +#else +#define MAP_UARTSpaceAvail \ + UARTSpaceAvail +#endif +#ifdef ROM_UARTCharGetNonBlocking +#define MAP_UARTCharGetNonBlocking \ + ROM_UARTCharGetNonBlocking +#else +#define MAP_UARTCharGetNonBlocking \ + UARTCharGetNonBlocking +#endif +#ifdef ROM_UARTCharGet +#define MAP_UARTCharGet \ + ROM_UARTCharGet +#else +#define MAP_UARTCharGet \ + UARTCharGet +#endif +#ifdef ROM_UARTCharPutNonBlocking +#define MAP_UARTCharPutNonBlocking \ + ROM_UARTCharPutNonBlocking +#else +#define MAP_UARTCharPutNonBlocking \ + UARTCharPutNonBlocking +#endif +#ifdef ROM_UARTBreakCtl +#define MAP_UARTBreakCtl \ + ROM_UARTBreakCtl +#else +#define MAP_UARTBreakCtl \ + UARTBreakCtl +#endif +#ifdef ROM_UARTIntEnable +#define MAP_UARTIntEnable \ + ROM_UARTIntEnable +#else +#define MAP_UARTIntEnable \ + UARTIntEnable +#endif +#ifdef ROM_UARTIntDisable +#define MAP_UARTIntDisable \ + ROM_UARTIntDisable +#else +#define MAP_UARTIntDisable \ + UARTIntDisable +#endif +#ifdef ROM_UARTIntStatus +#define MAP_UARTIntStatus \ + ROM_UARTIntStatus +#else +#define MAP_UARTIntStatus \ + UARTIntStatus +#endif +#ifdef ROM_UARTIntClear +#define MAP_UARTIntClear \ + ROM_UARTIntClear +#else +#define MAP_UARTIntClear \ + UARTIntClear +#endif +#ifdef ROM_UARTDMAEnable +#define MAP_UARTDMAEnable \ + ROM_UARTDMAEnable +#else +#define MAP_UARTDMAEnable \ + UARTDMAEnable +#endif +#ifdef ROM_UARTDMADisable +#define MAP_UARTDMADisable \ + ROM_UARTDMADisable +#else +#define MAP_UARTDMADisable \ + UARTDMADisable +#endif +#ifdef ROM_UARTFIFOEnable +#define MAP_UARTFIFOEnable \ + ROM_UARTFIFOEnable +#else +#define MAP_UARTFIFOEnable \ + UARTFIFOEnable +#endif +#ifdef ROM_UARTFIFODisable +#define MAP_UARTFIFODisable \ + ROM_UARTFIFODisable +#else +#define MAP_UARTFIFODisable \ + UARTFIFODisable +#endif +#ifdef ROM_UARTBusy +#define MAP_UARTBusy \ + ROM_UARTBusy +#else +#define MAP_UARTBusy \ + UARTBusy +#endif +#ifdef ROM_UARTTxIntModeSet +#define MAP_UARTTxIntModeSet \ + ROM_UARTTxIntModeSet +#else +#define MAP_UARTTxIntModeSet \ + UARTTxIntModeSet +#endif +#ifdef ROM_UARTTxIntModeGet +#define MAP_UARTTxIntModeGet \ + ROM_UARTTxIntModeGet +#else +#define MAP_UARTTxIntModeGet \ + UARTTxIntModeGet +#endif +#ifdef ROM_UARTRxErrorGet +#define MAP_UARTRxErrorGet \ + ROM_UARTRxErrorGet +#else +#define MAP_UARTRxErrorGet \ + UARTRxErrorGet +#endif +#ifdef ROM_UARTRxErrorClear +#define MAP_UARTRxErrorClear \ + ROM_UARTRxErrorClear +#else +#define MAP_UARTRxErrorClear \ + UARTRxErrorClear +#endif +#ifdef ROM_UARTClockSourceSet +#define MAP_UARTClockSourceSet \ + ROM_UARTClockSourceSet +#else +#define MAP_UARTClockSourceSet \ + UARTClockSourceSet +#endif +#ifdef ROM_UARTClockSourceGet +#define MAP_UARTClockSourceGet \ + ROM_UARTClockSourceGet +#else +#define MAP_UARTClockSourceGet \ + UARTClockSourceGet +#endif +#ifdef ROM_UART9BitEnable +#define MAP_UART9BitEnable \ + ROM_UART9BitEnable +#else +#define MAP_UART9BitEnable \ + UART9BitEnable +#endif +#ifdef ROM_UART9BitDisable +#define MAP_UART9BitDisable \ + ROM_UART9BitDisable +#else +#define MAP_UART9BitDisable \ + UART9BitDisable +#endif +#ifdef ROM_UART9BitAddrSet +#define MAP_UART9BitAddrSet \ + ROM_UART9BitAddrSet +#else +#define MAP_UART9BitAddrSet \ + UART9BitAddrSet +#endif +#ifdef ROM_UART9BitAddrSend +#define MAP_UART9BitAddrSend \ + ROM_UART9BitAddrSend +#else +#define MAP_UART9BitAddrSend \ + UART9BitAddrSend +#endif +#ifdef ROM_UARTSmartCardDisable +#define MAP_UARTSmartCardDisable \ + ROM_UARTSmartCardDisable +#else +#define MAP_UARTSmartCardDisable \ + UARTSmartCardDisable +#endif +#ifdef ROM_UARTSmartCardEnable +#define MAP_UARTSmartCardEnable \ + ROM_UARTSmartCardEnable +#else +#define MAP_UARTSmartCardEnable \ + UARTSmartCardEnable +#endif +#ifdef ROM_UARTModemControlClear +#define MAP_UARTModemControlClear \ + ROM_UARTModemControlClear +#else +#define MAP_UARTModemControlClear \ + UARTModemControlClear +#endif +#ifdef ROM_UARTModemControlGet +#define MAP_UARTModemControlGet \ + ROM_UARTModemControlGet +#else +#define MAP_UARTModemControlGet \ + UARTModemControlGet +#endif +#ifdef ROM_UARTModemControlSet +#define MAP_UARTModemControlSet \ + ROM_UARTModemControlSet +#else +#define MAP_UARTModemControlSet \ + UARTModemControlSet +#endif +#ifdef ROM_UARTModemStatusGet +#define MAP_UARTModemStatusGet \ + ROM_UARTModemStatusGet +#else +#define MAP_UARTModemStatusGet \ + UARTModemStatusGet +#endif +#ifdef ROM_UARTFlowControlGet +#define MAP_UARTFlowControlGet \ + ROM_UARTFlowControlGet +#else +#define MAP_UARTFlowControlGet \ + UARTFlowControlGet +#endif +#ifdef ROM_UARTFlowControlSet +#define MAP_UARTFlowControlSet \ + ROM_UARTFlowControlSet +#else +#define MAP_UARTFlowControlSet \ + UARTFlowControlSet +#endif + +//***************************************************************************** +// +// Macros for the uDMA API. +// +//***************************************************************************** +#ifdef ROM_uDMAChannelTransferSet +#define MAP_uDMAChannelTransferSet \ + ROM_uDMAChannelTransferSet +#else +#define MAP_uDMAChannelTransferSet \ + uDMAChannelTransferSet +#endif +#ifdef ROM_uDMAEnable +#define MAP_uDMAEnable \ + ROM_uDMAEnable +#else +#define MAP_uDMAEnable \ + uDMAEnable +#endif +#ifdef ROM_uDMADisable +#define MAP_uDMADisable \ + ROM_uDMADisable +#else +#define MAP_uDMADisable \ + uDMADisable +#endif +#ifdef ROM_uDMAErrorStatusGet +#define MAP_uDMAErrorStatusGet \ + ROM_uDMAErrorStatusGet +#else +#define MAP_uDMAErrorStatusGet \ + uDMAErrorStatusGet +#endif +#ifdef ROM_uDMAErrorStatusClear +#define MAP_uDMAErrorStatusClear \ + ROM_uDMAErrorStatusClear +#else +#define MAP_uDMAErrorStatusClear \ + uDMAErrorStatusClear +#endif +#ifdef ROM_uDMAChannelEnable +#define MAP_uDMAChannelEnable \ + ROM_uDMAChannelEnable +#else +#define MAP_uDMAChannelEnable \ + uDMAChannelEnable +#endif +#ifdef ROM_uDMAChannelDisable +#define MAP_uDMAChannelDisable \ + ROM_uDMAChannelDisable +#else +#define MAP_uDMAChannelDisable \ + uDMAChannelDisable +#endif +#ifdef ROM_uDMAChannelIsEnabled +#define MAP_uDMAChannelIsEnabled \ + ROM_uDMAChannelIsEnabled +#else +#define MAP_uDMAChannelIsEnabled \ + uDMAChannelIsEnabled +#endif +#ifdef ROM_uDMAControlBaseSet +#define MAP_uDMAControlBaseSet \ + ROM_uDMAControlBaseSet +#else +#define MAP_uDMAControlBaseSet \ + uDMAControlBaseSet +#endif +#ifdef ROM_uDMAControlBaseGet +#define MAP_uDMAControlBaseGet \ + ROM_uDMAControlBaseGet +#else +#define MAP_uDMAControlBaseGet \ + uDMAControlBaseGet +#endif +#ifdef ROM_uDMAChannelRequest +#define MAP_uDMAChannelRequest \ + ROM_uDMAChannelRequest +#else +#define MAP_uDMAChannelRequest \ + uDMAChannelRequest +#endif +#ifdef ROM_uDMAChannelAttributeEnable +#define MAP_uDMAChannelAttributeEnable \ + ROM_uDMAChannelAttributeEnable +#else +#define MAP_uDMAChannelAttributeEnable \ + uDMAChannelAttributeEnable +#endif +#ifdef ROM_uDMAChannelAttributeDisable +#define MAP_uDMAChannelAttributeDisable \ + ROM_uDMAChannelAttributeDisable +#else +#define MAP_uDMAChannelAttributeDisable \ + uDMAChannelAttributeDisable +#endif +#ifdef ROM_uDMAChannelAttributeGet +#define MAP_uDMAChannelAttributeGet \ + ROM_uDMAChannelAttributeGet +#else +#define MAP_uDMAChannelAttributeGet \ + uDMAChannelAttributeGet +#endif +#ifdef ROM_uDMAChannelControlSet +#define MAP_uDMAChannelControlSet \ + ROM_uDMAChannelControlSet +#else +#define MAP_uDMAChannelControlSet \ + uDMAChannelControlSet +#endif +#ifdef ROM_uDMAChannelSizeGet +#define MAP_uDMAChannelSizeGet \ + ROM_uDMAChannelSizeGet +#else +#define MAP_uDMAChannelSizeGet \ + uDMAChannelSizeGet +#endif +#ifdef ROM_uDMAChannelModeGet +#define MAP_uDMAChannelModeGet \ + ROM_uDMAChannelModeGet +#else +#define MAP_uDMAChannelModeGet \ + uDMAChannelModeGet +#endif +#ifdef ROM_uDMAChannelSelectSecondary +#define MAP_uDMAChannelSelectSecondary \ + ROM_uDMAChannelSelectSecondary +#else +#define MAP_uDMAChannelSelectSecondary \ + uDMAChannelSelectSecondary +#endif +#ifdef ROM_uDMAChannelSelectDefault +#define MAP_uDMAChannelSelectDefault \ + ROM_uDMAChannelSelectDefault +#else +#define MAP_uDMAChannelSelectDefault \ + uDMAChannelSelectDefault +#endif +#ifdef ROM_uDMAIntStatus +#define MAP_uDMAIntStatus \ + ROM_uDMAIntStatus +#else +#define MAP_uDMAIntStatus \ + uDMAIntStatus +#endif +#ifdef ROM_uDMAIntClear +#define MAP_uDMAIntClear \ + ROM_uDMAIntClear +#else +#define MAP_uDMAIntClear \ + uDMAIntClear +#endif +#ifdef ROM_uDMAControlAlternateBaseGet +#define MAP_uDMAControlAlternateBaseGet \ + ROM_uDMAControlAlternateBaseGet +#else +#define MAP_uDMAControlAlternateBaseGet \ + uDMAControlAlternateBaseGet +#endif +#ifdef ROM_uDMAChannelScatterGatherSet +#define MAP_uDMAChannelScatterGatherSet \ + ROM_uDMAChannelScatterGatherSet +#else +#define MAP_uDMAChannelScatterGatherSet \ + uDMAChannelScatterGatherSet +#endif +#ifdef ROM_uDMAChannelAssign +#define MAP_uDMAChannelAssign \ + ROM_uDMAChannelAssign +#else +#define MAP_uDMAChannelAssign \ + uDMAChannelAssign +#endif + +//***************************************************************************** +// +// Macros for the USB API. +// +//***************************************************************************** +#ifdef ROM_USBDevAddrGet +#define MAP_USBDevAddrGet \ + ROM_USBDevAddrGet +#else +#define MAP_USBDevAddrGet \ + USBDevAddrGet +#endif +#ifdef ROM_USBDevAddrSet +#define MAP_USBDevAddrSet \ + ROM_USBDevAddrSet +#else +#define MAP_USBDevAddrSet \ + USBDevAddrSet +#endif +#ifdef ROM_USBDevConnect +#define MAP_USBDevConnect \ + ROM_USBDevConnect +#else +#define MAP_USBDevConnect \ + USBDevConnect +#endif +#ifdef ROM_USBDevDisconnect +#define MAP_USBDevDisconnect \ + ROM_USBDevDisconnect +#else +#define MAP_USBDevDisconnect \ + USBDevDisconnect +#endif +#ifdef ROM_USBDevEndpointConfigSet +#define MAP_USBDevEndpointConfigSet \ + ROM_USBDevEndpointConfigSet +#else +#define MAP_USBDevEndpointConfigSet \ + USBDevEndpointConfigSet +#endif +#ifdef ROM_USBDevEndpointDataAck +#define MAP_USBDevEndpointDataAck \ + ROM_USBDevEndpointDataAck +#else +#define MAP_USBDevEndpointDataAck \ + USBDevEndpointDataAck +#endif +#ifdef ROM_USBDevEndpointStall +#define MAP_USBDevEndpointStall \ + ROM_USBDevEndpointStall +#else +#define MAP_USBDevEndpointStall \ + USBDevEndpointStall +#endif +#ifdef ROM_USBDevEndpointStallClear +#define MAP_USBDevEndpointStallClear \ + ROM_USBDevEndpointStallClear +#else +#define MAP_USBDevEndpointStallClear \ + USBDevEndpointStallClear +#endif +#ifdef ROM_USBDevEndpointStatusClear +#define MAP_USBDevEndpointStatusClear \ + ROM_USBDevEndpointStatusClear +#else +#define MAP_USBDevEndpointStatusClear \ + USBDevEndpointStatusClear +#endif +#ifdef ROM_USBEndpointDataGet +#define MAP_USBEndpointDataGet \ + ROM_USBEndpointDataGet +#else +#define MAP_USBEndpointDataGet \ + USBEndpointDataGet +#endif +#ifdef ROM_USBEndpointDataPut +#define MAP_USBEndpointDataPut \ + ROM_USBEndpointDataPut +#else +#define MAP_USBEndpointDataPut \ + USBEndpointDataPut +#endif +#ifdef ROM_USBEndpointDataSend +#define MAP_USBEndpointDataSend \ + ROM_USBEndpointDataSend +#else +#define MAP_USBEndpointDataSend \ + USBEndpointDataSend +#endif +#ifdef ROM_USBEndpointDataToggleClear +#define MAP_USBEndpointDataToggleClear \ + ROM_USBEndpointDataToggleClear +#else +#define MAP_USBEndpointDataToggleClear \ + USBEndpointDataToggleClear +#endif +#ifdef ROM_USBEndpointStatus +#define MAP_USBEndpointStatus \ + ROM_USBEndpointStatus +#else +#define MAP_USBEndpointStatus \ + USBEndpointStatus +#endif +#ifdef ROM_USBFIFOAddrGet +#define MAP_USBFIFOAddrGet \ + ROM_USBFIFOAddrGet +#else +#define MAP_USBFIFOAddrGet \ + USBFIFOAddrGet +#endif +#ifdef ROM_USBFIFOConfigGet +#define MAP_USBFIFOConfigGet \ + ROM_USBFIFOConfigGet +#else +#define MAP_USBFIFOConfigGet \ + USBFIFOConfigGet +#endif +#ifdef ROM_USBFIFOConfigSet +#define MAP_USBFIFOConfigSet \ + ROM_USBFIFOConfigSet +#else +#define MAP_USBFIFOConfigSet \ + USBFIFOConfigSet +#endif +#ifdef ROM_USBFIFOFlush +#define MAP_USBFIFOFlush \ + ROM_USBFIFOFlush +#else +#define MAP_USBFIFOFlush \ + USBFIFOFlush +#endif +#ifdef ROM_USBFrameNumberGet +#define MAP_USBFrameNumberGet \ + ROM_USBFrameNumberGet +#else +#define MAP_USBFrameNumberGet \ + USBFrameNumberGet +#endif +#ifdef ROM_USBHostAddrGet +#define MAP_USBHostAddrGet \ + ROM_USBHostAddrGet +#else +#define MAP_USBHostAddrGet \ + USBHostAddrGet +#endif +#ifdef ROM_USBHostAddrSet +#define MAP_USBHostAddrSet \ + ROM_USBHostAddrSet +#else +#define MAP_USBHostAddrSet \ + USBHostAddrSet +#endif +#ifdef ROM_USBHostEndpointConfig +#define MAP_USBHostEndpointConfig \ + ROM_USBHostEndpointConfig +#else +#define MAP_USBHostEndpointConfig \ + USBHostEndpointConfig +#endif +#ifdef ROM_USBHostEndpointDataAck +#define MAP_USBHostEndpointDataAck \ + ROM_USBHostEndpointDataAck +#else +#define MAP_USBHostEndpointDataAck \ + USBHostEndpointDataAck +#endif +#ifdef ROM_USBHostEndpointDataToggle +#define MAP_USBHostEndpointDataToggle \ + ROM_USBHostEndpointDataToggle +#else +#define MAP_USBHostEndpointDataToggle \ + USBHostEndpointDataToggle +#endif +#ifdef ROM_USBHostEndpointStatusClear +#define MAP_USBHostEndpointStatusClear \ + ROM_USBHostEndpointStatusClear +#else +#define MAP_USBHostEndpointStatusClear \ + USBHostEndpointStatusClear +#endif +#ifdef ROM_USBHostHubAddrGet +#define MAP_USBHostHubAddrGet \ + ROM_USBHostHubAddrGet +#else +#define MAP_USBHostHubAddrGet \ + USBHostHubAddrGet +#endif +#ifdef ROM_USBHostHubAddrSet +#define MAP_USBHostHubAddrSet \ + ROM_USBHostHubAddrSet +#else +#define MAP_USBHostHubAddrSet \ + USBHostHubAddrSet +#endif +#ifdef ROM_USBHostPwrDisable +#define MAP_USBHostPwrDisable \ + ROM_USBHostPwrDisable +#else +#define MAP_USBHostPwrDisable \ + USBHostPwrDisable +#endif +#ifdef ROM_USBHostPwrEnable +#define MAP_USBHostPwrEnable \ + ROM_USBHostPwrEnable +#else +#define MAP_USBHostPwrEnable \ + USBHostPwrEnable +#endif +#ifdef ROM_USBHostPwrConfig +#define MAP_USBHostPwrConfig \ + ROM_USBHostPwrConfig +#else +#define MAP_USBHostPwrConfig \ + USBHostPwrConfig +#endif +#ifdef ROM_USBHostPwrFaultDisable +#define MAP_USBHostPwrFaultDisable \ + ROM_USBHostPwrFaultDisable +#else +#define MAP_USBHostPwrFaultDisable \ + USBHostPwrFaultDisable +#endif +#ifdef ROM_USBHostPwrFaultEnable +#define MAP_USBHostPwrFaultEnable \ + ROM_USBHostPwrFaultEnable +#else +#define MAP_USBHostPwrFaultEnable \ + USBHostPwrFaultEnable +#endif +#ifdef ROM_USBHostRequestIN +#define MAP_USBHostRequestIN \ + ROM_USBHostRequestIN +#else +#define MAP_USBHostRequestIN \ + USBHostRequestIN +#endif +#ifdef ROM_USBHostRequestStatus +#define MAP_USBHostRequestStatus \ + ROM_USBHostRequestStatus +#else +#define MAP_USBHostRequestStatus \ + USBHostRequestStatus +#endif +#ifdef ROM_USBHostReset +#define MAP_USBHostReset \ + ROM_USBHostReset +#else +#define MAP_USBHostReset \ + USBHostReset +#endif +#ifdef ROM_USBHostResume +#define MAP_USBHostResume \ + ROM_USBHostResume +#else +#define MAP_USBHostResume \ + USBHostResume +#endif +#ifdef ROM_USBHostSpeedGet +#define MAP_USBHostSpeedGet \ + ROM_USBHostSpeedGet +#else +#define MAP_USBHostSpeedGet \ + USBHostSpeedGet +#endif +#ifdef ROM_USBHostSuspend +#define MAP_USBHostSuspend \ + ROM_USBHostSuspend +#else +#define MAP_USBHostSuspend \ + USBHostSuspend +#endif +#ifdef ROM_USBDevEndpointConfigGet +#define MAP_USBDevEndpointConfigGet \ + ROM_USBDevEndpointConfigGet +#else +#define MAP_USBDevEndpointConfigGet \ + USBDevEndpointConfigGet +#endif +#ifdef ROM_USBEndpointDMAEnable +#define MAP_USBEndpointDMAEnable \ + ROM_USBEndpointDMAEnable +#else +#define MAP_USBEndpointDMAEnable \ + USBEndpointDMAEnable +#endif +#ifdef ROM_USBEndpointDMADisable +#define MAP_USBEndpointDMADisable \ + ROM_USBEndpointDMADisable +#else +#define MAP_USBEndpointDMADisable \ + USBEndpointDMADisable +#endif +#ifdef ROM_USBEndpointDataAvail +#define MAP_USBEndpointDataAvail \ + ROM_USBEndpointDataAvail +#else +#define MAP_USBEndpointDataAvail \ + USBEndpointDataAvail +#endif +#ifdef ROM_USBModeGet +#define MAP_USBModeGet \ + ROM_USBModeGet +#else +#define MAP_USBModeGet \ + USBModeGet +#endif +#ifdef ROM_USBEndpointDMAChannel +#define MAP_USBEndpointDMAChannel \ + ROM_USBEndpointDMAChannel +#else +#define MAP_USBEndpointDMAChannel \ + USBEndpointDMAChannel +#endif +#ifdef ROM_USBIntDisableControl +#define MAP_USBIntDisableControl \ + ROM_USBIntDisableControl +#else +#define MAP_USBIntDisableControl \ + USBIntDisableControl +#endif +#ifdef ROM_USBIntEnableControl +#define MAP_USBIntEnableControl \ + ROM_USBIntEnableControl +#else +#define MAP_USBIntEnableControl \ + USBIntEnableControl +#endif +#ifdef ROM_USBIntStatusControl +#define MAP_USBIntStatusControl \ + ROM_USBIntStatusControl +#else +#define MAP_USBIntStatusControl \ + USBIntStatusControl +#endif +#ifdef ROM_USBIntDisableEndpoint +#define MAP_USBIntDisableEndpoint \ + ROM_USBIntDisableEndpoint +#else +#define MAP_USBIntDisableEndpoint \ + USBIntDisableEndpoint +#endif +#ifdef ROM_USBIntEnableEndpoint +#define MAP_USBIntEnableEndpoint \ + ROM_USBIntEnableEndpoint +#else +#define MAP_USBIntEnableEndpoint \ + USBIntEnableEndpoint +#endif +#ifdef ROM_USBIntStatusEndpoint +#define MAP_USBIntStatusEndpoint \ + ROM_USBIntStatusEndpoint +#else +#define MAP_USBIntStatusEndpoint \ + USBIntStatusEndpoint +#endif +#ifdef ROM_USBHostMode +#define MAP_USBHostMode \ + ROM_USBHostMode +#else +#define MAP_USBHostMode \ + USBHostMode +#endif +#ifdef ROM_USBDevMode +#define MAP_USBDevMode \ + ROM_USBDevMode +#else +#define MAP_USBDevMode \ + USBDevMode +#endif +#ifdef ROM_USBPHYPowerOff +#define MAP_USBPHYPowerOff \ + ROM_USBPHYPowerOff +#else +#define MAP_USBPHYPowerOff \ + USBPHYPowerOff +#endif +#ifdef ROM_USBPHYPowerOn +#define MAP_USBPHYPowerOn \ + ROM_USBPHYPowerOn +#else +#define MAP_USBPHYPowerOn \ + USBPHYPowerOn +#endif +#ifdef ROM_USBOTGMode +#define MAP_USBOTGMode \ + ROM_USBOTGMode +#else +#define MAP_USBOTGMode \ + USBOTGMode +#endif +#ifdef ROM_USBHostRequestINClear +#define MAP_USBHostRequestINClear \ + ROM_USBHostRequestINClear +#else +#define MAP_USBHostRequestINClear \ + USBHostRequestINClear +#endif +#ifdef ROM_USBNumEndpointsGet +#define MAP_USBNumEndpointsGet \ + ROM_USBNumEndpointsGet +#else +#define MAP_USBNumEndpointsGet \ + USBNumEndpointsGet +#endif +#ifdef ROM_USBClockDisable +#define MAP_USBClockDisable \ + ROM_USBClockDisable +#else +#define MAP_USBClockDisable \ + USBClockDisable +#endif +#ifdef ROM_USBClockEnable +#define MAP_USBClockEnable \ + ROM_USBClockEnable +#else +#define MAP_USBClockEnable \ + USBClockEnable +#endif +#ifdef ROM_USBControllerVersion +#define MAP_USBControllerVersion \ + ROM_USBControllerVersion +#else +#define MAP_USBControllerVersion \ + USBControllerVersion +#endif +#ifdef ROM_USBDevLPMConfig +#define MAP_USBDevLPMConfig \ + ROM_USBDevLPMConfig +#else +#define MAP_USBDevLPMConfig \ + USBDevLPMConfig +#endif +#ifdef ROM_USBDevLPMDisable +#define MAP_USBDevLPMDisable \ + ROM_USBDevLPMDisable +#else +#define MAP_USBDevLPMDisable \ + USBDevLPMDisable +#endif +#ifdef ROM_USBDevLPMEnable +#define MAP_USBDevLPMEnable \ + ROM_USBDevLPMEnable +#else +#define MAP_USBDevLPMEnable \ + USBDevLPMEnable +#endif +#ifdef ROM_USBDevLPMRemoteWake +#define MAP_USBDevLPMRemoteWake \ + ROM_USBDevLPMRemoteWake +#else +#define MAP_USBDevLPMRemoteWake \ + USBDevLPMRemoteWake +#endif +#ifdef ROM_USBDevSpeedGet +#define MAP_USBDevSpeedGet \ + ROM_USBDevSpeedGet +#else +#define MAP_USBDevSpeedGet \ + USBDevSpeedGet +#endif +#ifdef ROM_USBDMAChannelAddressGet +#define MAP_USBDMAChannelAddressGet \ + ROM_USBDMAChannelAddressGet +#else +#define MAP_USBDMAChannelAddressGet \ + USBDMAChannelAddressGet +#endif +#ifdef ROM_USBDMAChannelAddressSet +#define MAP_USBDMAChannelAddressSet \ + ROM_USBDMAChannelAddressSet +#else +#define MAP_USBDMAChannelAddressSet \ + USBDMAChannelAddressSet +#endif +#ifdef ROM_USBDMAChannelConfigSet +#define MAP_USBDMAChannelConfigSet \ + ROM_USBDMAChannelConfigSet +#else +#define MAP_USBDMAChannelConfigSet \ + USBDMAChannelConfigSet +#endif +#ifdef ROM_USBDMAChannelDisable +#define MAP_USBDMAChannelDisable \ + ROM_USBDMAChannelDisable +#else +#define MAP_USBDMAChannelDisable \ + USBDMAChannelDisable +#endif +#ifdef ROM_USBDMAChannelEnable +#define MAP_USBDMAChannelEnable \ + ROM_USBDMAChannelEnable +#else +#define MAP_USBDMAChannelEnable \ + USBDMAChannelEnable +#endif +#ifdef ROM_USBDMAChannelIntDisable +#define MAP_USBDMAChannelIntDisable \ + ROM_USBDMAChannelIntDisable +#else +#define MAP_USBDMAChannelIntDisable \ + USBDMAChannelIntDisable +#endif +#ifdef ROM_USBDMAChannelIntEnable +#define MAP_USBDMAChannelIntEnable \ + ROM_USBDMAChannelIntEnable +#else +#define MAP_USBDMAChannelIntEnable \ + USBDMAChannelIntEnable +#endif +#ifdef ROM_USBDMAChannelCountGet +#define MAP_USBDMAChannelCountGet \ + ROM_USBDMAChannelCountGet +#else +#define MAP_USBDMAChannelCountGet \ + USBDMAChannelCountGet +#endif +#ifdef ROM_USBDMAChannelCountSet +#define MAP_USBDMAChannelCountSet \ + ROM_USBDMAChannelCountSet +#else +#define MAP_USBDMAChannelCountSet \ + USBDMAChannelCountSet +#endif +#ifdef ROM_USBDMAChannelIntStatus +#define MAP_USBDMAChannelIntStatus \ + ROM_USBDMAChannelIntStatus +#else +#define MAP_USBDMAChannelIntStatus \ + USBDMAChannelIntStatus +#endif +#ifdef ROM_USBDMAChannelStatus +#define MAP_USBDMAChannelStatus \ + ROM_USBDMAChannelStatus +#else +#define MAP_USBDMAChannelStatus \ + USBDMAChannelStatus +#endif +#ifdef ROM_USBDMAChannelStatusClear +#define MAP_USBDMAChannelStatusClear \ + ROM_USBDMAChannelStatusClear +#else +#define MAP_USBDMAChannelStatusClear \ + USBDMAChannelStatusClear +#endif +#ifdef ROM_USBHighSpeed +#define MAP_USBHighSpeed \ + ROM_USBHighSpeed +#else +#define MAP_USBHighSpeed \ + USBHighSpeed +#endif +#ifdef ROM_USBHostEndpointPing +#define MAP_USBHostEndpointPing \ + ROM_USBHostEndpointPing +#else +#define MAP_USBHostEndpointPing \ + USBHostEndpointPing +#endif +#ifdef ROM_USBHostEndpointSpeed +#define MAP_USBHostEndpointSpeed \ + ROM_USBHostEndpointSpeed +#else +#define MAP_USBHostEndpointSpeed \ + USBHostEndpointSpeed +#endif +#ifdef ROM_USBHostLPMConfig +#define MAP_USBHostLPMConfig \ + ROM_USBHostLPMConfig +#else +#define MAP_USBHostLPMConfig \ + USBHostLPMConfig +#endif +#ifdef ROM_USBHostLPMResume +#define MAP_USBHostLPMResume \ + ROM_USBHostLPMResume +#else +#define MAP_USBHostLPMResume \ + USBHostLPMResume +#endif +#ifdef ROM_USBHostLPMSend +#define MAP_USBHostLPMSend \ + ROM_USBHostLPMSend +#else +#define MAP_USBHostLPMSend \ + USBHostLPMSend +#endif +#ifdef ROM_USBLPMIntDisable +#define MAP_USBLPMIntDisable \ + ROM_USBLPMIntDisable +#else +#define MAP_USBLPMIntDisable \ + USBLPMIntDisable +#endif +#ifdef ROM_USBLPMIntEnable +#define MAP_USBLPMIntEnable \ + ROM_USBLPMIntEnable +#else +#define MAP_USBLPMIntEnable \ + USBLPMIntEnable +#endif +#ifdef ROM_USBLPMIntStatus +#define MAP_USBLPMIntStatus \ + ROM_USBLPMIntStatus +#else +#define MAP_USBLPMIntStatus \ + USBLPMIntStatus +#endif +#ifdef ROM_USBLPMLinkStateGet +#define MAP_USBLPMLinkStateGet \ + ROM_USBLPMLinkStateGet +#else +#define MAP_USBLPMLinkStateGet \ + USBLPMLinkStateGet +#endif +#ifdef ROM_USBEndpointPacketCountSet +#define MAP_USBEndpointPacketCountSet \ + ROM_USBEndpointPacketCountSet +#else +#define MAP_USBEndpointPacketCountSet \ + USBEndpointPacketCountSet +#endif +#ifdef ROM_USBULPIConfig +#define MAP_USBULPIConfig \ + ROM_USBULPIConfig +#else +#define MAP_USBULPIConfig \ + USBULPIConfig +#endif +#ifdef ROM_USBULPIDisable +#define MAP_USBULPIDisable \ + ROM_USBULPIDisable +#else +#define MAP_USBULPIDisable \ + USBULPIDisable +#endif +#ifdef ROM_USBULPIEnable +#define MAP_USBULPIEnable \ + ROM_USBULPIEnable +#else +#define MAP_USBULPIEnable \ + USBULPIEnable +#endif +#ifdef ROM_USBULPIRegRead +#define MAP_USBULPIRegRead \ + ROM_USBULPIRegRead +#else +#define MAP_USBULPIRegRead \ + USBULPIRegRead +#endif +#ifdef ROM_USBULPIRegWrite +#define MAP_USBULPIRegWrite \ + ROM_USBULPIRegWrite +#else +#define MAP_USBULPIRegWrite \ + USBULPIRegWrite +#endif +#ifdef ROM_USBOTGSessionRequest +#define MAP_USBOTGSessionRequest \ + ROM_USBOTGSessionRequest +#else +#define MAP_USBOTGSessionRequest \ + USBOTGSessionRequest +#endif +#ifdef ROM_USBDMANumChannels +#define MAP_USBDMANumChannels \ + ROM_USBDMANumChannels +#else +#define MAP_USBDMANumChannels \ + USBDMANumChannels +#endif +#ifdef ROM_USBEndpointDMAConfigSet +#define MAP_USBEndpointDMAConfigSet \ + ROM_USBEndpointDMAConfigSet +#else +#define MAP_USBEndpointDMAConfigSet \ + USBEndpointDMAConfigSet +#endif +#ifdef ROM_USBLPMRemoteWakeEnabled +#define MAP_USBLPMRemoteWakeEnabled \ + ROM_USBLPMRemoteWakeEnabled +#else +#define MAP_USBLPMRemoteWakeEnabled \ + USBLPMRemoteWakeEnabled +#endif +#ifdef ROM_USBModeConfig +#define MAP_USBModeConfig \ + ROM_USBModeConfig +#else +#define MAP_USBModeConfig \ + USBModeConfig +#endif + +//***************************************************************************** +// +// Macros for the Watchdog API. +// +//***************************************************************************** +#ifdef ROM_WatchdogIntClear +#define MAP_WatchdogIntClear \ + ROM_WatchdogIntClear +#else +#define MAP_WatchdogIntClear \ + WatchdogIntClear +#endif +#ifdef ROM_WatchdogRunning +#define MAP_WatchdogRunning \ + ROM_WatchdogRunning +#else +#define MAP_WatchdogRunning \ + WatchdogRunning +#endif +#ifdef ROM_WatchdogEnable +#define MAP_WatchdogEnable \ + ROM_WatchdogEnable +#else +#define MAP_WatchdogEnable \ + WatchdogEnable +#endif +#ifdef ROM_WatchdogResetEnable +#define MAP_WatchdogResetEnable \ + ROM_WatchdogResetEnable +#else +#define MAP_WatchdogResetEnable \ + WatchdogResetEnable +#endif +#ifdef ROM_WatchdogResetDisable +#define MAP_WatchdogResetDisable \ + ROM_WatchdogResetDisable +#else +#define MAP_WatchdogResetDisable \ + WatchdogResetDisable +#endif +#ifdef ROM_WatchdogLock +#define MAP_WatchdogLock \ + ROM_WatchdogLock +#else +#define MAP_WatchdogLock \ + WatchdogLock +#endif +#ifdef ROM_WatchdogUnlock +#define MAP_WatchdogUnlock \ + ROM_WatchdogUnlock +#else +#define MAP_WatchdogUnlock \ + WatchdogUnlock +#endif +#ifdef ROM_WatchdogLockState +#define MAP_WatchdogLockState \ + ROM_WatchdogLockState +#else +#define MAP_WatchdogLockState \ + WatchdogLockState +#endif +#ifdef ROM_WatchdogReloadSet +#define MAP_WatchdogReloadSet \ + ROM_WatchdogReloadSet +#else +#define MAP_WatchdogReloadSet \ + WatchdogReloadSet +#endif +#ifdef ROM_WatchdogReloadGet +#define MAP_WatchdogReloadGet \ + ROM_WatchdogReloadGet +#else +#define MAP_WatchdogReloadGet \ + WatchdogReloadGet +#endif +#ifdef ROM_WatchdogValueGet +#define MAP_WatchdogValueGet \ + ROM_WatchdogValueGet +#else +#define MAP_WatchdogValueGet \ + WatchdogValueGet +#endif +#ifdef ROM_WatchdogIntEnable +#define MAP_WatchdogIntEnable \ + ROM_WatchdogIntEnable +#else +#define MAP_WatchdogIntEnable \ + WatchdogIntEnable +#endif +#ifdef ROM_WatchdogIntStatus +#define MAP_WatchdogIntStatus \ + ROM_WatchdogIntStatus +#else +#define MAP_WatchdogIntStatus \ + WatchdogIntStatus +#endif +#ifdef ROM_WatchdogStallEnable +#define MAP_WatchdogStallEnable \ + ROM_WatchdogStallEnable +#else +#define MAP_WatchdogStallEnable \ + WatchdogStallEnable +#endif +#ifdef ROM_WatchdogStallDisable +#define MAP_WatchdogStallDisable \ + ROM_WatchdogStallDisable +#else +#define MAP_WatchdogStallDisable \ + WatchdogStallDisable +#endif +#ifdef ROM_WatchdogIntTypeSet +#define MAP_WatchdogIntTypeSet \ + ROM_WatchdogIntTypeSet +#else +#define MAP_WatchdogIntTypeSet \ + WatchdogIntTypeSet +#endif + +//***************************************************************************** +// +// Macros for the Software API. +// +//***************************************************************************** +#ifdef ROM_Crc16Array +#define MAP_Crc16Array \ + ROM_Crc16Array +#else +#define MAP_Crc16Array \ + Crc16Array +#endif +#ifdef ROM_Crc16Array3 +#define MAP_Crc16Array3 \ + ROM_Crc16Array3 +#else +#define MAP_Crc16Array3 \ + Crc16Array3 +#endif +#ifdef ROM_Crc16 +#define MAP_Crc16 \ + ROM_Crc16 +#else +#define MAP_Crc16 \ + Crc16 +#endif +#ifdef ROM_Crc8CCITT +#define MAP_Crc8CCITT \ + ROM_Crc8CCITT +#else +#define MAP_Crc8CCITT \ + Crc8CCITT +#endif +#ifdef ROM_Crc32 +#define MAP_Crc32 \ + ROM_Crc32 +#else +#define MAP_Crc32 \ + Crc32 +#endif + +#endif // __DRIVERLIB_ROM_MAP_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/rtos_bindings.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/rtos_bindings.h new file mode 100644 index 0000000000000000000000000000000000000000..90762502c02e9506d6a073977c96c323a7e94f27 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/rtos_bindings.h @@ -0,0 +1,108 @@ +//***************************************************************************** +// +// rtos_bindings.h - Macros intended to aid porting of TivaWare modules +// for use with an RTOS. +// +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_RTOS_BINDINGS_H__ +#define __DRIVERLIB_RTOS_BINDINGS_H__ + +#ifdef USE_RTOS +//***************************************************************************** +// +// If an RTOS is in use, implement a header file called "tiva_rtos.h" +// which contains RTOS-specific versions of each of the macros defined below +// and make sure it appears on the include path set when you build your +// project. +// +// Note that there is no default implementation of this header file included +// in TivaWare - it is your responsibility to create it specifically for +// your RTOS. +// +//***************************************************************************** +#include "tiva_rtos.h" + +#else +//***************************************************************************** +// +// When no RTOS is in use, the follow macros compile to either nothing or a +// minimal implementation that works in a bare-metal environment. +// +// Each of these macros must be redefined in tiva_rtos.h if you are using +// TivaWare under an RTOS. +// +//***************************************************************************** + +//***************************************************************************** +// +// A simple macro used to yield within polling loops. In the default, non-RTOS +// implementation, this compiles to nothing. +// +//***************************************************************************** +#define OS_YIELD() + +//***************************************************************************** +// +// A simple macro around the SysCtlDelay function. The parameter is the number +// of 3 cycle loops to wait before returning (as for SysCtlDelay). In an RTOS +// implementation, this could be replaced with an OS delay call with +// appropriate parameter scaling. +// +//***************************************************************************** +#define OS_DELAY(ul3Cycles) MAP_SysCtlDelay(ul3Cycles) + +//***************************************************************************** +// +// Wrappers around low level interrupt control functions. For information +// on each of these functions, please see the appropriate API documentation +// for the DriverLib Interrupt driver. +// +// The macros defined here represent interrupt-control functions that may be +// called from within TivaWare code. It is expected that application +// code will use RTOS-specific functions to control interrupt priority, to +// pend interrupts and to perform runtime vector manipulation. As a result, +// no macros are defined to wrap any of these functions from interrupt.c. +// +//***************************************************************************** +#define OS_INT_MASTER_ENABLE() MAP_IntMasterEnable() +#define OS_INT_MASTER_DISABLE() MAP_IntMasterDisable() +#define OS_INT_DISABLE(ui32IntID) MAP_IntDisable(ui32IntID) +#define OS_INT_ENABLE(ui32IntID) MAP_IntEnable(ui32IntID) + +#endif // USE_RTOS + +#endif // __DRIVERLIB_RTOS_BINDINGS_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/shamd5.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/shamd5.h new file mode 100644 index 0000000000000000000000000000000000000000..3b0e793b4f53bcd5667d94ea78828f1a2cfe77cf --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/shamd5.h @@ -0,0 +1,127 @@ +//***************************************************************************** +// +// shamd5.h - Defines and Macros for the SHA/MD5. +// +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_SHAMD5_H__ +#define __DRIVERLIB_SHAMD5_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following defines are used to specify the algorithm in use in the +// SHA/MD5 module. +// +//***************************************************************************** +#define SHAMD5_ALGO_MD5 0x00000018 +#define SHAMD5_ALGO_SHA1 0x0000001a +#define SHAMD5_ALGO_SHA224 0x0000001c +#define SHAMD5_ALGO_SHA256 0x0000001e +#define SHAMD5_ALGO_HMAC_MD5 0x00000000 +#define SHAMD5_ALGO_HMAC_SHA1 0x00000002 +#define SHAMD5_ALGO_HMAC_SHA224 0x00000004 +#define SHAMD5_ALGO_HMAC_SHA256 0x00000006 + +//***************************************************************************** +// +// The following defines are used to represent the different interrupt sources +// in SHAMD5IntEnable(), SHAMD5IntDisable(), SHAMD5GetIntStatus(), and +// SHAMD5BlockOnIntStatus() functions. +// +//***************************************************************************** +#define SHAMD5_INT_CONTEXT_READY \ + 0x00000008 +#define SHAMD5_INT_PARTHASH_READY \ + 0x00000004 +#define SHAMD5_INT_INPUT_READY 0x00000002 +#define SHAMD5_INT_OUTPUT_READY 0x00000001 +#define SHAMD5_INT_DMA_CONTEXT_IN \ + 0x00080000 +#define SHAMD5_INT_DMA_DATA_IN 0x00020000 +#define SHAMD5_INT_DMA_CONTEXT_OUT \ + 0x00010000 + +//***************************************************************************** +// +// Function prototypes +// +//***************************************************************************** +extern void SHAMD5ConfigSet(uint32_t ui32Base, uint32_t ui32Mode); +extern void SHAMD5DataProcess(uint32_t ui32Base, uint32_t *pui32DataSrc, + uint32_t ui32DataLength, + uint32_t *pui32HashResult); +extern void SHAMD5DataWrite(uint32_t ui32Base, uint32_t *pui32Src); +extern bool SHAMD5DataWriteNonBlocking(uint32_t ui32Base, uint32_t *pui32Src); +extern void SHAMD5DMADisable(uint32_t ui32Base); +extern void SHAMD5DMAEnable(uint32_t ui32Base); +extern void SHAMD5HashLengthSet(uint32_t ui32Base, uint32_t ui32Length); +extern void SHAMD5HMACKeySet(uint32_t ui32Base, uint32_t *pui32Src); +extern void SHAMD5HMACPPKeyGenerate(uint32_t ui32Base, uint32_t *pui32Key, + uint32_t *pui32PPKey); +extern void SHAMD5HMACPPKeySet(uint32_t ui32Base, uint32_t *pui32Src); +extern void SHAMD5HMACProcess(uint32_t ui32Base, uint32_t *pui32DataSrc, + uint32_t ui32DataLength, + uint32_t *pui32HashResult); +extern void SHAMD5IntClear(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void SHAMD5IntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void SHAMD5IntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void SHAMD5IntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); +extern uint32_t SHAMD5IntStatus(uint32_t ui32Base, bool bMasked); +extern void SHAMD5IntUnregister(uint32_t ui32Base); +extern void SHAMD5Reset(uint32_t ui32Base); +extern void SHAMD5ResultRead(uint32_t ui32Base, uint32_t *pui32Dest); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_SHAMD5_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/ssi.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/ssi.h new file mode 100644 index 0000000000000000000000000000000000000000..37d928dd1b905c587dba824847abf2f3304aa0cb --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/ssi.h @@ -0,0 +1,157 @@ +//***************************************************************************** +// +// ssi.h - Prototypes for the Synchronous Serial Interface Driver. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_SSI_H__ +#define __DRIVERLIB_SSI_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear +// as the ui32IntFlags parameter, and returned by SSIIntStatus. +// +//***************************************************************************** +#define SSI_TXEOT 0x00000040 // Transmit FIFO is empty +#define SSI_DMATX 0x00000020 // DMA Transmit complete +#define SSI_DMARX 0x00000010 // DMA Receive complete +#define SSI_TXFF 0x00000008 // TX FIFO half full or less +#define SSI_RXFF 0x00000004 // RX FIFO half full or more +#define SSI_RXTO 0x00000002 // RX timeout +#define SSI_RXOR 0x00000001 // RX overrun + +//***************************************************************************** +// +// Values that can be passed to SSIConfigSetExpClk. +// +//***************************************************************************** +#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 +#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 +#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 +#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 +#define SSI_FRF_TI 0x00000010 // TI frame format +#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format + +#define SSI_MODE_MASTER 0x00000000 // SSI master +#define SSI_MODE_SLAVE 0x00000001 // SSI slave +#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled + +//***************************************************************************** +// +// Values that can be passed to SSIDMAEnable() and SSIDMADisable(). +// +//***************************************************************************** +#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit +#define SSI_DMA_RX 0x00000001 // Enable DMA for receive + +//***************************************************************************** +// +// Values that can be passed to SSIClockSourceSet() or returned from +// SSIClockSourceGet(). +// +//***************************************************************************** +#define SSI_CLOCK_SYSTEM 0x00000000 +#define SSI_CLOCK_PIOSC 0x00000005 + +//***************************************************************************** +// +// Values that can be passed to SSIAdvModeSet(). +// +//***************************************************************************** +#define SSI_ADV_MODE_LEGACY 0x00000000 +#define SSI_ADV_MODE_READ_WRITE 0x000001c0 +#define SSI_ADV_MODE_WRITE 0x000000c0 +#define SSI_ADV_MODE_BI_READ 0x00000140 +#define SSI_ADV_MODE_BI_WRITE 0x00000040 +#define SSI_ADV_MODE_QUAD_READ 0x00000180 +#define SSI_ADV_MODE_QUAD_WRITE 0x00000080 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk, + uint32_t ui32Protocol, uint32_t ui32Mode, + uint32_t ui32BitRate, + uint32_t ui32DataWidth); +extern void SSIDataGet(uint32_t ui32Base, uint32_t *pui32Data); +extern int32_t SSIDataGetNonBlocking(uint32_t ui32Base, + uint32_t *pui32Data); +extern void SSIDataPut(uint32_t ui32Base, uint32_t ui32Data); +extern int32_t SSIDataPutNonBlocking(uint32_t ui32Base, uint32_t ui32Data); +extern void SSIDisable(uint32_t ui32Base); +extern void SSIEnable(uint32_t ui32Base); +extern void SSIIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void SSIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void SSIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void SSIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); +extern uint32_t SSIIntStatus(uint32_t ui32Base, bool bMasked); +extern void SSIIntUnregister(uint32_t ui32Base); +extern void SSIDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags); +extern void SSIDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags); +extern bool SSIBusy(uint32_t ui32Base); +extern void SSIClockSourceSet(uint32_t ui32Base, uint32_t ui32Source); +extern uint32_t SSIClockSourceGet(uint32_t ui32Base); +extern void SSIAdvModeSet(uint32_t ui32Base, uint32_t ui32Mode); +extern void SSIAdvDataPutFrameEnd(uint32_t ui32Base, uint32_t ui32Data); +extern int32_t SSIAdvDataPutFrameEndNonBlocking(uint32_t ui32Base, + uint32_t ui32Data); +extern void SSIAdvFrameHoldEnable(uint32_t ui32Base); +extern void SSIAdvFrameHoldDisable(uint32_t ui32Base); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_SSI_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/sw_crc.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/sw_crc.h new file mode 100644 index 0000000000000000000000000000000000000000..0e60775ffc293d1a16f78c01d76c19a152fe735d --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/sw_crc.h @@ -0,0 +1,78 @@ +//***************************************************************************** +// +// sw_crc.h - Prototypes for the software CRC functions. +// +// Copyright (c) 2010-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_SW_CRC_H__ +#define __DRIVERLIB_SW_CRC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the functions. +// +//***************************************************************************** +extern uint8_t Crc8CCITT(uint8_t ui8Crc, const uint8_t *pui8Data, + uint32_t ui32Count); +extern uint16_t Crc16(uint16_t ui16Crc, const uint8_t *pui8Data, + uint32_t ui32Count); +extern uint16_t Crc16Array(uint32_t ui32WordLen, const uint32_t *pui32Data); +extern void Crc16Array3(uint32_t ui32WordLen, const uint32_t *pui32Data, + uint16_t *pui16Crc3); +extern uint32_t Crc32(uint32_t ui32Crc, const uint8_t *pui8Data, + uint32_t ui32Count); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_SW_CRC_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/sysctl.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/sysctl.h new file mode 100644 index 0000000000000000000000000000000000000000..0bce4852d7c19d0652233972f7f509c98c5bb5e9 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/sysctl.h @@ -0,0 +1,656 @@ +//***************************************************************************** +// +// sysctl.h - Prototypes for the system control driver. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_SYSCTL_H__ +#define __DRIVERLIB_SYSCTL_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the +// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), +// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the +// ui32Peripheral parameter. The peripherals in the fourth group (upper nibble +// is 3) can only be used with the SysCtlPeripheralPresent() API. +// +//***************************************************************************** +#define SYSCTL_PERIPH_ADC0 0xf0003800 // ADC 0 +#define SYSCTL_PERIPH_ADC1 0xf0003801 // ADC 1 +#define SYSCTL_PERIPH_CAN0 0xf0003400 // CAN 0 +#define SYSCTL_PERIPH_CAN1 0xf0003401 // CAN 1 +#define SYSCTL_PERIPH_COMP0 0xf0003c00 // Analog Comparator Module 0 +#define SYSCTL_PERIPH_EMAC0 0xf0009c00 // Ethernet MAC0 +#define SYSCTL_PERIPH_EPHY0 0xf0003000 // Ethernet PHY0 +#define SYSCTL_PERIPH_EPI0 0xf0001000 // EPI0 +#define SYSCTL_PERIPH_GPIOA 0xf0000800 // GPIO A +#define SYSCTL_PERIPH_GPIOB 0xf0000801 // GPIO B +#define SYSCTL_PERIPH_GPIOC 0xf0000802 // GPIO C +#define SYSCTL_PERIPH_GPIOD 0xf0000803 // GPIO D +#define SYSCTL_PERIPH_GPIOE 0xf0000804 // GPIO E +#define SYSCTL_PERIPH_GPIOF 0xf0000805 // GPIO F +#define SYSCTL_PERIPH_GPIOG 0xf0000806 // GPIO G +#define SYSCTL_PERIPH_GPIOH 0xf0000807 // GPIO H +#define SYSCTL_PERIPH_GPIOJ 0xf0000808 // GPIO J +#define SYSCTL_PERIPH_HIBERNATE 0xf0001400 // Hibernation module +#define SYSCTL_PERIPH_CCM0 0xf0007400 // CCM 0 +#define SYSCTL_PERIPH_EEPROM0 0xf0005800 // EEPROM 0 +#define SYSCTL_PERIPH_FAN0 0xf0005400 // FAN 0 +#define SYSCTL_PERIPH_FAN1 0xf0005401 // FAN 1 +#define SYSCTL_PERIPH_GPIOK 0xf0000809 // GPIO K +#define SYSCTL_PERIPH_GPIOL 0xf000080a // GPIO L +#define SYSCTL_PERIPH_GPIOM 0xf000080b // GPIO M +#define SYSCTL_PERIPH_GPION 0xf000080c // GPIO N +#define SYSCTL_PERIPH_GPIOP 0xf000080d // GPIO P +#define SYSCTL_PERIPH_GPIOQ 0xf000080e // GPIO Q +#define SYSCTL_PERIPH_GPIOR 0xf000080f // GPIO R +#define SYSCTL_PERIPH_GPIOS 0xf0000810 // GPIO S +#define SYSCTL_PERIPH_GPIOT 0xf0000811 // GPIO T +#define SYSCTL_PERIPH_I2C0 0xf0002000 // I2C 0 +#define SYSCTL_PERIPH_I2C1 0xf0002001 // I2C 1 +#define SYSCTL_PERIPH_I2C2 0xf0002002 // I2C 2 +#define SYSCTL_PERIPH_I2C3 0xf0002003 // I2C 3 +#define SYSCTL_PERIPH_I2C4 0xf0002004 // I2C 4 +#define SYSCTL_PERIPH_I2C5 0xf0002005 // I2C 5 +#define SYSCTL_PERIPH_I2C6 0xf0002006 // I2C 6 +#define SYSCTL_PERIPH_I2C7 0xf0002007 // I2C 7 +#define SYSCTL_PERIPH_I2C8 0xf0002008 // I2C 8 +#define SYSCTL_PERIPH_I2C9 0xf0002009 // I2C 9 +#define SYSCTL_PERIPH_LCD0 0xf0009000 // LCD 0 +#define SYSCTL_PERIPH_ONEWIRE0 0xf0009800 // One Wire 0 +#define SYSCTL_PERIPH_PWM0 0xf0004000 // PWM 0 +#define SYSCTL_PERIPH_PWM1 0xf0004001 // PWM 1 +#define SYSCTL_PERIPH_QEI0 0xf0004400 // QEI 0 +#define SYSCTL_PERIPH_QEI1 0xf0004401 // QEI 1 +#define SYSCTL_PERIPH_SSI0 0xf0001c00 // SSI 0 +#define SYSCTL_PERIPH_SSI1 0xf0001c01 // SSI 1 +#define SYSCTL_PERIPH_SSI2 0xf0001c02 // SSI 2 +#define SYSCTL_PERIPH_SSI3 0xf0001c03 // SSI 3 +#define SYSCTL_PERIPH_TIMER0 0xf0000400 // Timer 0 +#define SYSCTL_PERIPH_TIMER1 0xf0000401 // Timer 1 +#define SYSCTL_PERIPH_TIMER2 0xf0000402 // Timer 2 +#define SYSCTL_PERIPH_TIMER3 0xf0000403 // Timer 3 +#define SYSCTL_PERIPH_TIMER4 0xf0000404 // Timer 4 +#define SYSCTL_PERIPH_TIMER5 0xf0000405 // Timer 5 +#define SYSCTL_PERIPH_TIMER6 0xf0000406 // Timer 6 +#define SYSCTL_PERIPH_TIMER7 0xf0000407 // Timer 7 +#define SYSCTL_PERIPH_UART0 0xf0001800 // UART 0 +#define SYSCTL_PERIPH_UART1 0xf0001801 // UART 1 +#define SYSCTL_PERIPH_UART2 0xf0001802 // UART 2 +#define SYSCTL_PERIPH_UART3 0xf0001803 // UART 3 +#define SYSCTL_PERIPH_UART4 0xf0001804 // UART 4 +#define SYSCTL_PERIPH_UART5 0xf0001805 // UART 5 +#define SYSCTL_PERIPH_UART6 0xf0001806 // UART 6 +#define SYSCTL_PERIPH_UART7 0xf0001807 // UART 7 +#define SYSCTL_PERIPH_UDMA 0xf0000c00 // uDMA +#define SYSCTL_PERIPH_USB0 0xf0002800 // USB 0 +#define SYSCTL_PERIPH_WDOG0 0xf0000000 // Watchdog 0 +#define SYSCTL_PERIPH_WDOG1 0xf0000001 // Watchdog 1 +#define SYSCTL_PERIPH_WTIMER0 0xf0005c00 // Wide Timer 0 +#define SYSCTL_PERIPH_WTIMER1 0xf0005c01 // Wide Timer 1 +#define SYSCTL_PERIPH_WTIMER2 0xf0005c02 // Wide Timer 2 +#define SYSCTL_PERIPH_WTIMER3 0xf0005c03 // Wide Timer 3 +#define SYSCTL_PERIPH_WTIMER4 0xf0005c04 // Wide Timer 4 +#define SYSCTL_PERIPH_WTIMER5 0xf0005c05 // Wide Timer 5 + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOSleepSet() and +// SysCtlLDODeepSleepSet() APIs as the ui32Voltage value, or returned by the +// SysCtlLDOSleepGet() and SysCtlLDODeepSleepGet() APIs. +// +//***************************************************************************** +#define SYSCTL_LDO_0_90V 0x80000012 // LDO output of 0.90V +#define SYSCTL_LDO_0_95V 0x80000013 // LDO output of 0.95V +#define SYSCTL_LDO_1_00V 0x80000014 // LDO output of 1.00V +#define SYSCTL_LDO_1_05V 0x80000015 // LDO output of 1.05V +#define SYSCTL_LDO_1_10V 0x80000016 // LDO output of 1.10V +#define SYSCTL_LDO_1_15V 0x80000017 // LDO output of 1.15V +#define SYSCTL_LDO_1_20V 0x80000018 // LDO output of 1.20V + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlIntEnable(), +// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask +// by the SysCtlIntStatus() API. +// +//***************************************************************************** +#define SYSCTL_INT_BOR0 0x00000800 // VDD under BOR0 +#define SYSCTL_INT_VDDA_OK 0x00000400 // VDDA Power OK +#define SYSCTL_INT_MOSC_PUP 0x00000100 // MOSC power-up interrupt +#define SYSCTL_INT_USBPLL_LOCK 0x00000080 // USB PLL lock interrupt +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_BOR1 0x00000002 // VDD under BOR1 +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlResetCauseClear() +// API or returned by the SysCtlResetCauseGet() API. +// +//***************************************************************************** +#define SYSCTL_CAUSE_HSRVREQ 0x00001000 // Hardware System Service Request +#define SYSCTL_CAUSE_HIB 0x00000040 // Hibernate reset +#define SYSCTL_CAUSE_WDOG1 0x00000020 // Watchdog 1 reset +#define SYSCTL_CAUSE_SW 0x00000010 // Software reset +#define SYSCTL_CAUSE_WDOG0 0x00000008 // Watchdog 0 reset +#ifndef DEPRECATED +#define SYSCTL_CAUSE_WDOG SYSCTL_CAUSE_WDOG0 + // Watchdog reset(Deprecated) +#endif +#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset +#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset +#define SYSCTL_CAUSE_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlBrownOutConfigSet() +// API as the ui32Config parameter. +// +//***************************************************************************** +#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting +#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPWMClockSet() API +// as the ui32Config parameter, and can be returned by the SysCtlPWMClockGet() +// API. +// +//***************************************************************************** +#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1 +#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2 +#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4 +#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8 +#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16 +#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32 +#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64 + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlClockSet() API as +// the ui32Config parameter. +// +//***************************************************************************** +#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 +#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 +#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 +#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 +#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 +#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 +#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 +#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 +#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 +#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 +#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 +#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 +#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 +#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 +#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 +#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 +#define SYSCTL_SYSDIV_17 0x88400000 // Processor clock is osc/pll /17 +#define SYSCTL_SYSDIV_18 0x88C00000 // Processor clock is osc/pll /18 +#define SYSCTL_SYSDIV_19 0x89400000 // Processor clock is osc/pll /19 +#define SYSCTL_SYSDIV_20 0x89C00000 // Processor clock is osc/pll /20 +#define SYSCTL_SYSDIV_21 0x8A400000 // Processor clock is osc/pll /21 +#define SYSCTL_SYSDIV_22 0x8AC00000 // Processor clock is osc/pll /22 +#define SYSCTL_SYSDIV_23 0x8B400000 // Processor clock is osc/pll /23 +#define SYSCTL_SYSDIV_24 0x8BC00000 // Processor clock is osc/pll /24 +#define SYSCTL_SYSDIV_25 0x8C400000 // Processor clock is osc/pll /25 +#define SYSCTL_SYSDIV_26 0x8CC00000 // Processor clock is osc/pll /26 +#define SYSCTL_SYSDIV_27 0x8D400000 // Processor clock is osc/pll /27 +#define SYSCTL_SYSDIV_28 0x8DC00000 // Processor clock is osc/pll /28 +#define SYSCTL_SYSDIV_29 0x8E400000 // Processor clock is osc/pll /29 +#define SYSCTL_SYSDIV_30 0x8EC00000 // Processor clock is osc/pll /30 +#define SYSCTL_SYSDIV_31 0x8F400000 // Processor clock is osc/pll /31 +#define SYSCTL_SYSDIV_32 0x8FC00000 // Processor clock is osc/pll /32 +#define SYSCTL_SYSDIV_33 0x90400000 // Processor clock is osc/pll /33 +#define SYSCTL_SYSDIV_34 0x90C00000 // Processor clock is osc/pll /34 +#define SYSCTL_SYSDIV_35 0x91400000 // Processor clock is osc/pll /35 +#define SYSCTL_SYSDIV_36 0x91C00000 // Processor clock is osc/pll /36 +#define SYSCTL_SYSDIV_37 0x92400000 // Processor clock is osc/pll /37 +#define SYSCTL_SYSDIV_38 0x92C00000 // Processor clock is osc/pll /38 +#define SYSCTL_SYSDIV_39 0x93400000 // Processor clock is osc/pll /39 +#define SYSCTL_SYSDIV_40 0x93C00000 // Processor clock is osc/pll /40 +#define SYSCTL_SYSDIV_41 0x94400000 // Processor clock is osc/pll /41 +#define SYSCTL_SYSDIV_42 0x94C00000 // Processor clock is osc/pll /42 +#define SYSCTL_SYSDIV_43 0x95400000 // Processor clock is osc/pll /43 +#define SYSCTL_SYSDIV_44 0x95C00000 // Processor clock is osc/pll /44 +#define SYSCTL_SYSDIV_45 0x96400000 // Processor clock is osc/pll /45 +#define SYSCTL_SYSDIV_46 0x96C00000 // Processor clock is osc/pll /46 +#define SYSCTL_SYSDIV_47 0x97400000 // Processor clock is osc/pll /47 +#define SYSCTL_SYSDIV_48 0x97C00000 // Processor clock is osc/pll /48 +#define SYSCTL_SYSDIV_49 0x98400000 // Processor clock is osc/pll /49 +#define SYSCTL_SYSDIV_50 0x98C00000 // Processor clock is osc/pll /50 +#define SYSCTL_SYSDIV_51 0x99400000 // Processor clock is osc/pll /51 +#define SYSCTL_SYSDIV_52 0x99C00000 // Processor clock is osc/pll /52 +#define SYSCTL_SYSDIV_53 0x9A400000 // Processor clock is osc/pll /53 +#define SYSCTL_SYSDIV_54 0x9AC00000 // Processor clock is osc/pll /54 +#define SYSCTL_SYSDIV_55 0x9B400000 // Processor clock is osc/pll /55 +#define SYSCTL_SYSDIV_56 0x9BC00000 // Processor clock is osc/pll /56 +#define SYSCTL_SYSDIV_57 0x9C400000 // Processor clock is osc/pll /57 +#define SYSCTL_SYSDIV_58 0x9CC00000 // Processor clock is osc/pll /58 +#define SYSCTL_SYSDIV_59 0x9D400000 // Processor clock is osc/pll /59 +#define SYSCTL_SYSDIV_60 0x9DC00000 // Processor clock is osc/pll /60 +#define SYSCTL_SYSDIV_61 0x9E400000 // Processor clock is osc/pll /61 +#define SYSCTL_SYSDIV_62 0x9EC00000 // Processor clock is osc/pll /62 +#define SYSCTL_SYSDIV_63 0x9F400000 // Processor clock is osc/pll /63 +#define SYSCTL_SYSDIV_64 0x9FC00000 // Processor clock is osc/pll /64 +#define SYSCTL_SYSDIV_2_5 0xC1000000 // Processor clock is pll / 2.5 +#define SYSCTL_SYSDIV_3_5 0xC1800000 // Processor clock is pll / 3.5 +#define SYSCTL_SYSDIV_4_5 0xC2000000 // Processor clock is pll / 4.5 +#define SYSCTL_SYSDIV_5_5 0xC2800000 // Processor clock is pll / 5.5 +#define SYSCTL_SYSDIV_6_5 0xC3000000 // Processor clock is pll / 6.5 +#define SYSCTL_SYSDIV_7_5 0xC3800000 // Processor clock is pll / 7.5 +#define SYSCTL_SYSDIV_8_5 0xC4000000 // Processor clock is pll / 8.5 +#define SYSCTL_SYSDIV_9_5 0xC4800000 // Processor clock is pll / 9.5 +#define SYSCTL_SYSDIV_10_5 0xC5000000 // Processor clock is pll / 10.5 +#define SYSCTL_SYSDIV_11_5 0xC5800000 // Processor clock is pll / 11.5 +#define SYSCTL_SYSDIV_12_5 0xC6000000 // Processor clock is pll / 12.5 +#define SYSCTL_SYSDIV_13_5 0xC6800000 // Processor clock is pll / 13.5 +#define SYSCTL_SYSDIV_14_5 0xC7000000 // Processor clock is pll / 14.5 +#define SYSCTL_SYSDIV_15_5 0xC7800000 // Processor clock is pll / 15.5 +#define SYSCTL_SYSDIV_16_5 0xC8000000 // Processor clock is pll / 16.5 +#define SYSCTL_SYSDIV_17_5 0xC8800000 // Processor clock is pll / 17.5 +#define SYSCTL_SYSDIV_18_5 0xC9000000 // Processor clock is pll / 18.5 +#define SYSCTL_SYSDIV_19_5 0xC9800000 // Processor clock is pll / 19.5 +#define SYSCTL_SYSDIV_20_5 0xCA000000 // Processor clock is pll / 20.5 +#define SYSCTL_SYSDIV_21_5 0xCA800000 // Processor clock is pll / 21.5 +#define SYSCTL_SYSDIV_22_5 0xCB000000 // Processor clock is pll / 22.5 +#define SYSCTL_SYSDIV_23_5 0xCB800000 // Processor clock is pll / 23.5 +#define SYSCTL_SYSDIV_24_5 0xCC000000 // Processor clock is pll / 24.5 +#define SYSCTL_SYSDIV_25_5 0xCC800000 // Processor clock is pll / 25.5 +#define SYSCTL_SYSDIV_26_5 0xCD000000 // Processor clock is pll / 26.5 +#define SYSCTL_SYSDIV_27_5 0xCD800000 // Processor clock is pll / 27.5 +#define SYSCTL_SYSDIV_28_5 0xCE000000 // Processor clock is pll / 28.5 +#define SYSCTL_SYSDIV_29_5 0xCE800000 // Processor clock is pll / 29.5 +#define SYSCTL_SYSDIV_30_5 0xCF000000 // Processor clock is pll / 30.5 +#define SYSCTL_SYSDIV_31_5 0xCF800000 // Processor clock is pll / 31.5 +#define SYSCTL_SYSDIV_32_5 0xD0000000 // Processor clock is pll / 32.5 +#define SYSCTL_SYSDIV_33_5 0xD0800000 // Processor clock is pll / 33.5 +#define SYSCTL_SYSDIV_34_5 0xD1000000 // Processor clock is pll / 34.5 +#define SYSCTL_SYSDIV_35_5 0xD1800000 // Processor clock is pll / 35.5 +#define SYSCTL_SYSDIV_36_5 0xD2000000 // Processor clock is pll / 36.5 +#define SYSCTL_SYSDIV_37_5 0xD2800000 // Processor clock is pll / 37.5 +#define SYSCTL_SYSDIV_38_5 0xD3000000 // Processor clock is pll / 38.5 +#define SYSCTL_SYSDIV_39_5 0xD3800000 // Processor clock is pll / 39.5 +#define SYSCTL_SYSDIV_40_5 0xD4000000 // Processor clock is pll / 40.5 +#define SYSCTL_SYSDIV_41_5 0xD4800000 // Processor clock is pll / 41.5 +#define SYSCTL_SYSDIV_42_5 0xD5000000 // Processor clock is pll / 42.5 +#define SYSCTL_SYSDIV_43_5 0xD5800000 // Processor clock is pll / 43.5 +#define SYSCTL_SYSDIV_44_5 0xD6000000 // Processor clock is pll / 44.5 +#define SYSCTL_SYSDIV_45_5 0xD6800000 // Processor clock is pll / 45.5 +#define SYSCTL_SYSDIV_46_5 0xD7000000 // Processor clock is pll / 46.5 +#define SYSCTL_SYSDIV_47_5 0xD7800000 // Processor clock is pll / 47.5 +#define SYSCTL_SYSDIV_48_5 0xD8000000 // Processor clock is pll / 48.5 +#define SYSCTL_SYSDIV_49_5 0xD8800000 // Processor clock is pll / 49.5 +#define SYSCTL_SYSDIV_50_5 0xD9000000 // Processor clock is pll / 50.5 +#define SYSCTL_SYSDIV_51_5 0xD9800000 // Processor clock is pll / 51.5 +#define SYSCTL_SYSDIV_52_5 0xDA000000 // Processor clock is pll / 52.5 +#define SYSCTL_SYSDIV_53_5 0xDA800000 // Processor clock is pll / 53.5 +#define SYSCTL_SYSDIV_54_5 0xDB000000 // Processor clock is pll / 54.5 +#define SYSCTL_SYSDIV_55_5 0xDB800000 // Processor clock is pll / 55.5 +#define SYSCTL_SYSDIV_56_5 0xDC000000 // Processor clock is pll / 56.5 +#define SYSCTL_SYSDIV_57_5 0xDC800000 // Processor clock is pll / 57.5 +#define SYSCTL_SYSDIV_58_5 0xDD000000 // Processor clock is pll / 58.5 +#define SYSCTL_SYSDIV_59_5 0xDD800000 // Processor clock is pll / 59.5 +#define SYSCTL_SYSDIV_60_5 0xDE000000 // Processor clock is pll / 60.5 +#define SYSCTL_SYSDIV_61_5 0xDE800000 // Processor clock is pll / 61.5 +#define SYSCTL_SYSDIV_62_5 0xDF000000 // Processor clock is pll / 62.5 +#define SYSCTL_SYSDIV_63_5 0xDF800000 // Processor clock is pll / 63.5 +#define SYSCTL_CFG_VCO_480 0xF1000000 // VCO is 480 MHz +#define SYSCTL_CFG_VCO_320 0xF0000000 // VCO is 320 MHz +#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock +#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock +#define SYSCTL_XTAL_1MHZ 0x00000000 // External crystal is 1MHz +#define SYSCTL_XTAL_1_84MHZ 0x00000040 // External crystal is 1.8432MHz +#define SYSCTL_XTAL_2MHZ 0x00000080 // External crystal is 2MHz +#define SYSCTL_XTAL_2_45MHZ 0x000000C0 // External crystal is 2.4576MHz +#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz +#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz +#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz +#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz +#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz +#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz +#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz +#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz +#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz +#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz +#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz +#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz +#define SYSCTL_XTAL_10MHZ 0x00000400 // External crystal is 10 MHz +#define SYSCTL_XTAL_12MHZ 0x00000440 // External crystal is 12 MHz +#define SYSCTL_XTAL_12_2MHZ 0x00000480 // External crystal is 12.288 MHz +#define SYSCTL_XTAL_13_5MHZ 0x000004C0 // External crystal is 13.56 MHz +#define SYSCTL_XTAL_14_3MHZ 0x00000500 // External crystal is 14.31818 MHz +#define SYSCTL_XTAL_16MHZ 0x00000540 // External crystal is 16 MHz +#define SYSCTL_XTAL_16_3MHZ 0x00000580 // External crystal is 16.384 MHz +#define SYSCTL_XTAL_18MHZ 0x000005C0 // External crystal is 18.0 MHz +#define SYSCTL_XTAL_20MHZ 0x00000600 // External crystal is 20.0 MHz +#define SYSCTL_XTAL_24MHZ 0x00000640 // External crystal is 24.0 MHz +#define SYSCTL_XTAL_25MHZ 0x00000680 // External crystal is 25.0 MHz +#define SYSCTL_OSC_MAIN 0x00000000 // Osc source is main osc +#define SYSCTL_OSC_INT 0x00000010 // Osc source is int. osc +#define SYSCTL_OSC_INT4 0x00000020 // Osc source is int. osc /4 +#define SYSCTL_OSC_INT30 0x00000030 // Osc source is int. 30 KHz +#define SYSCTL_OSC_EXT32 0x80000038 // Osc source is ext. 32 KHz +#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator +#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlDeepSleepClockSet() +// API as the ui32Config parameter. +// +//***************************************************************************** +#define SYSCTL_DSLP_DIV_1 0x00000000 // Deep-sleep clock is osc /1 +#define SYSCTL_DSLP_DIV_2 0x00800000 // Deep-sleep clock is osc /2 +#define SYSCTL_DSLP_DIV_3 0x01000000 // Deep-sleep clock is osc /3 +#define SYSCTL_DSLP_DIV_4 0x01800000 // Deep-sleep clock is osc /4 +#define SYSCTL_DSLP_DIV_5 0x02000000 // Deep-sleep clock is osc /5 +#define SYSCTL_DSLP_DIV_6 0x02800000 // Deep-sleep clock is osc /6 +#define SYSCTL_DSLP_DIV_7 0x03000000 // Deep-sleep clock is osc /7 +#define SYSCTL_DSLP_DIV_8 0x03800000 // Deep-sleep clock is osc /8 +#define SYSCTL_DSLP_DIV_9 0x04000000 // Deep-sleep clock is osc /9 +#define SYSCTL_DSLP_DIV_10 0x04800000 // Deep-sleep clock is osc /10 +#define SYSCTL_DSLP_DIV_11 0x05000000 // Deep-sleep clock is osc /11 +#define SYSCTL_DSLP_DIV_12 0x05800000 // Deep-sleep clock is osc /12 +#define SYSCTL_DSLP_DIV_13 0x06000000 // Deep-sleep clock is osc /13 +#define SYSCTL_DSLP_DIV_14 0x06800000 // Deep-sleep clock is osc /14 +#define SYSCTL_DSLP_DIV_15 0x07000000 // Deep-sleep clock is osc /15 +#define SYSCTL_DSLP_DIV_16 0x07800000 // Deep-sleep clock is osc /16 +#define SYSCTL_DSLP_DIV_17 0x08000000 // Deep-sleep clock is osc /17 +#define SYSCTL_DSLP_DIV_18 0x08800000 // Deep-sleep clock is osc /18 +#define SYSCTL_DSLP_DIV_19 0x09000000 // Deep-sleep clock is osc /19 +#define SYSCTL_DSLP_DIV_20 0x09800000 // Deep-sleep clock is osc /20 +#define SYSCTL_DSLP_DIV_21 0x0A000000 // Deep-sleep clock is osc /21 +#define SYSCTL_DSLP_DIV_22 0x0A800000 // Deep-sleep clock is osc /22 +#define SYSCTL_DSLP_DIV_23 0x0B000000 // Deep-sleep clock is osc /23 +#define SYSCTL_DSLP_DIV_24 0x0B800000 // Deep-sleep clock is osc /24 +#define SYSCTL_DSLP_DIV_25 0x0C000000 // Deep-sleep clock is osc /25 +#define SYSCTL_DSLP_DIV_26 0x0C800000 // Deep-sleep clock is osc /26 +#define SYSCTL_DSLP_DIV_27 0x0D000000 // Deep-sleep clock is osc /27 +#define SYSCTL_DSLP_DIV_28 0x0D800000 // Deep-sleep clock is osc /28 +#define SYSCTL_DSLP_DIV_29 0x0E000000 // Deep-sleep clock is osc /29 +#define SYSCTL_DSLP_DIV_30 0x0E800000 // Deep-sleep clock is osc /30 +#define SYSCTL_DSLP_DIV_31 0x0F000000 // Deep-sleep clock is osc /31 +#define SYSCTL_DSLP_DIV_32 0x0F800000 // Deep-sleep clock is osc /32 +#define SYSCTL_DSLP_DIV_33 0x10000000 // Deep-sleep clock is osc /33 +#define SYSCTL_DSLP_DIV_34 0x10800000 // Deep-sleep clock is osc /34 +#define SYSCTL_DSLP_DIV_35 0x11000000 // Deep-sleep clock is osc /35 +#define SYSCTL_DSLP_DIV_36 0x11800000 // Deep-sleep clock is osc /36 +#define SYSCTL_DSLP_DIV_37 0x12000000 // Deep-sleep clock is osc /37 +#define SYSCTL_DSLP_DIV_38 0x12800000 // Deep-sleep clock is osc /38 +#define SYSCTL_DSLP_DIV_39 0x13000000 // Deep-sleep clock is osc /39 +#define SYSCTL_DSLP_DIV_40 0x13800000 // Deep-sleep clock is osc /40 +#define SYSCTL_DSLP_DIV_41 0x14000000 // Deep-sleep clock is osc /41 +#define SYSCTL_DSLP_DIV_42 0x14800000 // Deep-sleep clock is osc /42 +#define SYSCTL_DSLP_DIV_43 0x15000000 // Deep-sleep clock is osc /43 +#define SYSCTL_DSLP_DIV_44 0x15800000 // Deep-sleep clock is osc /44 +#define SYSCTL_DSLP_DIV_45 0x16000000 // Deep-sleep clock is osc /45 +#define SYSCTL_DSLP_DIV_46 0x16800000 // Deep-sleep clock is osc /46 +#define SYSCTL_DSLP_DIV_47 0x17000000 // Deep-sleep clock is osc /47 +#define SYSCTL_DSLP_DIV_48 0x17800000 // Deep-sleep clock is osc /48 +#define SYSCTL_DSLP_DIV_49 0x18000000 // Deep-sleep clock is osc /49 +#define SYSCTL_DSLP_DIV_50 0x18800000 // Deep-sleep clock is osc /50 +#define SYSCTL_DSLP_DIV_51 0x19000000 // Deep-sleep clock is osc /51 +#define SYSCTL_DSLP_DIV_52 0x19800000 // Deep-sleep clock is osc /52 +#define SYSCTL_DSLP_DIV_53 0x1A000000 // Deep-sleep clock is osc /53 +#define SYSCTL_DSLP_DIV_54 0x1A800000 // Deep-sleep clock is osc /54 +#define SYSCTL_DSLP_DIV_55 0x1B000000 // Deep-sleep clock is osc /55 +#define SYSCTL_DSLP_DIV_56 0x1B800000 // Deep-sleep clock is osc /56 +#define SYSCTL_DSLP_DIV_57 0x1C000000 // Deep-sleep clock is osc /57 +#define SYSCTL_DSLP_DIV_58 0x1C800000 // Deep-sleep clock is osc /58 +#define SYSCTL_DSLP_DIV_59 0x1D000000 // Deep-sleep clock is osc /59 +#define SYSCTL_DSLP_DIV_60 0x1D800000 // Deep-sleep clock is osc /60 +#define SYSCTL_DSLP_DIV_61 0x1E000000 // Deep-sleep clock is osc /61 +#define SYSCTL_DSLP_DIV_62 0x1E800000 // Deep-sleep clock is osc /62 +#define SYSCTL_DSLP_DIV_63 0x1F000000 // Deep-sleep clock is osc /63 +#define SYSCTL_DSLP_DIV_64 0x1F800000 // Deep-sleep clock is osc /64 +#define SYSCTL_DSLP_OSC_MAIN 0x00000000 // Osc source is main osc +#define SYSCTL_DSLP_OSC_INT 0x00000010 // Osc source is int. osc +#define SYSCTL_DSLP_OSC_INT30 0x00000030 // Osc source is int. 30 KHz +#define SYSCTL_DSLP_OSC_EXT32 0x00000070 // Osc source is ext. 32 KHz +#define SYSCTL_DSLP_PIOSC_PD 0x00000002 // Power down PIOSC in deep-sleep +#define SYSCTL_DSLP_MOSC_PD 0x40000000 // Power down MOSC in deep-sleep + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPIOSCCalibrate() +// API as the ui32Type parameter. +// +//***************************************************************************** +#define SYSCTL_PIOSC_CAL_AUTO 0x00000200 // Automatic calibration +#define SYSCTL_PIOSC_CAL_FACT 0x00000100 // Factory calibration +#define SYSCTL_PIOSC_CAL_USER 0x80000100 // User-supplied calibration + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlMOSCConfigSet() API +// as the ui32Config parameter. +// +//***************************************************************************** +#define SYSCTL_MOSC_VALIDATE 0x00000001 // Enable MOSC validation +#define SYSCTL_MOSC_INTERRUPT 0x00000002 // Generate interrupt on MOSC fail +#define SYSCTL_MOSC_NO_XTAL 0x00000004 // No crystal is attached to MOSC +#define SYSCTL_MOSC_PWR_DIS 0x00000008 // Power down the MOSC. +#define SYSCTL_MOSC_LOWFREQ 0x00000000 // MOSC is less than 10MHz +#define SYSCTL_MOSC_HIGHFREQ 0x00000010 // MOSC is greater than 10MHz +#define SYSCTL_MOSC_SESRC 0x00000020 // Singled ended oscillator source. + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlSleepPowerSet() and +// SysCtlDeepSleepPowerSet() APIs as the ui32Config parameter. +// +//***************************************************************************** +#define SYSCTL_LDO_SLEEP 0x00000200 // LDO in sleep mode + // (Deep Sleep Only) +#define SYSCTL_TEMP_LOW_POWER 0x00000100 // Temp sensor in low power mode + // (Deep Sleep Only) +#define SYSCTL_FLASH_NORMAL 0x00000000 // Flash in normal mode +#define SYSCTL_FLASH_LOW_POWER 0x00000020 // Flash in low power mode +#define SYSCTL_SRAM_NORMAL 0x00000000 // SRAM in normal mode +#define SYSCTL_SRAM_STANDBY 0x00000001 // SRAM in standby mode +#define SYSCTL_SRAM_LOW_POWER 0x00000003 // SRAM in low power mode + +//***************************************************************************** +// +// Defines for the SysCtlResetBehaviorSet() and SysCtlResetBehaviorGet() APIs. +// +//***************************************************************************** +#define SYSCTL_ONRST_WDOG0_POR 0x00000030 +#define SYSCTL_ONRST_WDOG0_SYS 0x00000020 +#define SYSCTL_ONRST_WDOG1_POR 0x000000C0 +#define SYSCTL_ONRST_WDOG1_SYS 0x00000080 +#define SYSCTL_ONRST_BOR_POR 0x0000000C +#define SYSCTL_ONRST_BOR_SYS 0x00000008 +#define SYSCTL_ONRST_EXT_POR 0x00000003 +#define SYSCTL_ONRST_EXT_SYS 0x00000002 + +//***************************************************************************** +// +// Values used with the SysCtlVoltageEventConfig() API. +// +//***************************************************************************** +#define SYSCTL_VEVENT_VDDABO_NONE \ + 0x00000000 +#define SYSCTL_VEVENT_VDDABO_INT \ + 0x00000100 +#define SYSCTL_VEVENT_VDDABO_NMI \ + 0x00000200 +#define SYSCTL_VEVENT_VDDABO_RST \ + 0x00000300 +#define SYSCTL_VEVENT_VDDBO_NONE \ + 0x00000000 +#define SYSCTL_VEVENT_VDDBO_INT 0x00000001 +#define SYSCTL_VEVENT_VDDBO_NMI 0x00000002 +#define SYSCTL_VEVENT_VDDBO_RST 0x00000003 + +//***************************************************************************** +// +// Values used with the SysCtlVoltageEventStatus() and +// SysCtlVoltageEventClear() APIs. +// +//***************************************************************************** +#define SYSCTL_VESTAT_VDDBOR 0x00000040 +#define SYSCTL_VESTAT_VDDABOR 0x00000010 + +//***************************************************************************** +// +// Values used with the SysCtlNMIStatus() API. +// +//***************************************************************************** +#define SYSCTL_NMI_MOSCFAIL 0x00010000 +#define SYSCTL_NMI_TAMPER 0x00000200 +#define SYSCTL_NMI_WDT1 0x00000020 +#define SYSCTL_NMI_WDT0 0x00000008 +#define SYSCTL_NMI_POWER 0x00000004 +#define SYSCTL_NMI_EXTERNAL 0x00000001 + +//***************************************************************************** +// +// The defines for the SysCtlClockOutConfig() API. +// +//***************************************************************************** +#define SYSCTL_CLKOUT_EN 0x80000000 +#define SYSCTL_CLKOUT_DIS 0x00000000 +#define SYSCTL_CLKOUT_SYSCLK 0x00000000 +#define SYSCTL_CLKOUT_PIOSC 0x00010000 +#define SYSCTL_CLKOUT_MOSC 0x00020000 + +//***************************************************************************** +// +// The following defines are used with the SysCtlAltClkConfig() function. +// +//***************************************************************************** +#define SYSCTL_ALTCLK_PIOSC 0x00000000 +#define SYSCTL_ALTCLK_RTCOSC 0x00000003 +#define SYSCTL_ALTCLK_LFIOSC 0x00000004 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern uint32_t SysCtlSRAMSizeGet(void); +extern uint32_t SysCtlFlashSizeGet(void); +extern uint32_t SysCtlFlashSectorSizeGet(void); +extern bool SysCtlPeripheralPresent(uint32_t ui32Peripheral); +extern bool SysCtlPeripheralReady(uint32_t ui32Peripheral); +extern void SysCtlPeripheralPowerOn(uint32_t ui32Peripheral); +extern void SysCtlPeripheralPowerOff(uint32_t ui32Peripheral); +extern void SysCtlPeripheralReset(uint32_t ui32Peripheral); +extern void SysCtlPeripheralEnable(uint32_t ui32Peripheral); +extern void SysCtlPeripheralDisable(uint32_t ui32Peripheral); +extern void SysCtlPeripheralSleepEnable(uint32_t ui32Peripheral); +extern void SysCtlPeripheralSleepDisable(uint32_t ui32Peripheral); +extern void SysCtlPeripheralDeepSleepEnable(uint32_t ui32Peripheral); +extern void SysCtlPeripheralDeepSleepDisable(uint32_t ui32Peripheral); +extern void SysCtlPeripheralClockGating(bool bEnable); +extern void SysCtlIntRegister(void (*pfnHandler)(void)); +extern void SysCtlIntUnregister(void); +extern void SysCtlIntEnable(uint32_t ui32Ints); +extern void SysCtlIntDisable(uint32_t ui32Ints); +extern void SysCtlIntClear(uint32_t ui32Ints); +extern uint32_t SysCtlIntStatus(bool bMasked); +extern void SysCtlLDOSleepSet(uint32_t ui32Voltage); +extern uint32_t SysCtlLDOSleepGet(void); +extern void SysCtlLDODeepSleepSet(uint32_t ui32Voltage); +extern uint32_t SysCtlLDODeepSleepGet(void); +extern void SysCtlSleepPowerSet(uint32_t ui32Config); +extern void SysCtlDeepSleepPowerSet(uint32_t ui32Config); +extern void SysCtlReset(void); +extern void SysCtlSleep(void); +extern void SysCtlDeepSleep(void); +extern uint32_t SysCtlResetCauseGet(void); +extern void SysCtlResetCauseClear(uint32_t ui32Causes); +extern void SysCtlBrownOutConfigSet(uint32_t ui32Config, + uint32_t ui32Delay); +extern void SysCtlDelay(uint32_t ui32Count); +extern void SysCtlMOSCConfigSet(uint32_t ui32Config); +extern uint32_t SysCtlPIOSCCalibrate(uint32_t ui32Type); +extern void SysCtlClockSet(uint32_t ui32Config); +extern uint32_t SysCtlClockGet(void); +extern void SysCtlDeepSleepClockSet(uint32_t ui32Config); +extern void SysCtlDeepSleepClockConfigSet(uint32_t ui32Div, + uint32_t ui32Config); +extern void SysCtlPWMClockSet(uint32_t ui32Config); +extern uint32_t SysCtlPWMClockGet(void); +extern void SysCtlIOSCVerificationSet(bool bEnable); +extern void SysCtlMOSCVerificationSet(bool bEnable); +extern void SysCtlPLLVerificationSet(bool bEnable); +extern void SysCtlClkVerificationClear(void); +extern void SysCtlGPIOAHBEnable(uint32_t ui32GPIOPeripheral); +extern void SysCtlGPIOAHBDisable(uint32_t ui32GPIOPeripheral); +extern void SysCtlUSBPLLEnable(void); +extern void SysCtlUSBPLLDisable(void); +extern uint32_t SysCtlClockFreqSet(uint32_t ui32Config, + uint32_t ui32SysClock); +extern void SysCtlResetBehaviorSet(uint32_t ui32Behavior); +extern uint32_t SysCtlResetBehaviorGet(void); +extern void SysCtlClockOutConfig(uint32_t ui32Config, uint32_t ui32Div); +extern void SysCtlAltClkConfig(uint32_t ui32Config); +extern uint32_t SysCtlNMIStatus(void); +extern void SysCtlNMIClear(uint32_t ui32Status); +extern void SysCtlVoltageEventConfig(uint32_t ui32Config); +extern uint32_t SysCtlVoltageEventStatus(void); +extern void SysCtlVoltageEventClear(uint32_t ui32Status); +extern bool SysCtlVCOGet(uint32_t ui32Crystal, uint32_t *pui32VCOFrequency); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_SYSCTL_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/sysexc.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/sysexc.h new file mode 100644 index 0000000000000000000000000000000000000000..aece4409d18708e4c9dbb2804a180760af093ad3 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/sysexc.h @@ -0,0 +1,89 @@ +//***************************************************************************** +// +// sysexc.h - Prototypes for the System Exception Module routines. +// +// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_SYSEXC_H__ +#define __DRIVERLIB_SYSEXC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to SysExcIntEnable, SysExcIntDisable, and +// SysExcIntClear as the ui32IntFlags parameter, and returned from +// SysExcIntStatus. +// +//***************************************************************************** +#define SYSEXC_INT_FP_IXC 0x00000020 // FP Inexact exception interrupt +#define SYSEXC_INT_FP_OFC 0x00000010 // FP Overflow exception interrupt +#define SYSEXC_INT_FP_UFC 0x00000008 // FP Underflow exception interrupt +#define SYSEXC_INT_FP_IOC 0x00000004 // FP Invalid operation interrupt +#define SYSEXC_INT_FP_DZC 0x00000002 // FP Divide by zero exception int +#define SYSEXC_INT_FP_IDC 0x00000001 // FP Input denormal exception int + +//***************************************************************************** +// +// Prototypes. +// +//***************************************************************************** +extern void SysExcIntRegister(void (*pfnHandler)(void)); +extern void SysExcIntUnregister(void); +extern void SysExcIntEnable(uint32_t ui32IntFlags); +extern void SysExcIntDisable(uint32_t ui32IntFlags); +extern uint32_t SysExcIntStatus(bool bMasked); +extern void SysExcIntClear(uint32_t ui32IntFlags); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_SYSEXC_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/systick.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/systick.h new file mode 100644 index 0000000000000000000000000000000000000000..35909ee3fb8a975463952e9cdd9eb916ff47d4dc --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/systick.h @@ -0,0 +1,78 @@ +//***************************************************************************** +// +// systick.h - Prototypes for the SysTick driver. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_SYSTICK_H__ +#define __DRIVERLIB_SYSTICK_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SysTickEnable(void); +extern void SysTickDisable(void); +extern void SysTickIntRegister(void (*pfnHandler)(void)); +extern void SysTickIntUnregister(void); +extern void SysTickIntEnable(void); +extern void SysTickIntDisable(void); +extern void SysTickPeriodSet(uint32_t ui32Period); +extern uint32_t SysTickPeriodGet(void); +extern uint32_t SysTickValueGet(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_SYSTICK_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/tiva_timer.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/tiva_timer.h new file mode 100644 index 0000000000000000000000000000000000000000..7eb619a7e09d05ca03f13b1271dce7192445f37d --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/tiva_timer.h @@ -0,0 +1,301 @@ +//***************************************************************************** +// +// timer.h - Prototypes for the timer module +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_TIMER_H__ +#define __DRIVERLIB_TIMER_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to TimerConfigure as the ui32Config parameter. +// +//***************************************************************************** +#define TIMER_CFG_ONE_SHOT 0x00000021 // Full-width one-shot timer +#define TIMER_CFG_ONE_SHOT_UP 0x00000031 // Full-width one-shot up-count + // timer +#define TIMER_CFG_PERIODIC 0x00000022 // Full-width periodic timer +#define TIMER_CFG_PERIODIC_UP 0x00000032 // Full-width periodic up-count + // timer +#define TIMER_CFG_RTC 0x01000000 // Full-width RTC timer +#define TIMER_CFG_SPLIT_PAIR 0x04000000 // Two half-width timers +#define TIMER_CFG_A_ONE_SHOT 0x00000021 // Timer A one-shot timer +#define TIMER_CFG_A_ONE_SHOT_UP 0x00000031 // Timer A one-shot up-count timer +#define TIMER_CFG_A_PERIODIC 0x00000022 // Timer A periodic timer +#define TIMER_CFG_A_PERIODIC_UP 0x00000032 // Timer A periodic up-count timer +#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter +#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter +#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer +#define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer +#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output +#define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer +#define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer +#define TIMER_CFG_B_PERIODIC 0x00002200 // Timer B periodic timer +#define TIMER_CFG_B_PERIODIC_UP 0x00003200 // Timer B periodic up-count timer +#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter +#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter +#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer +#define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer +#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output +#define TIMER_CFG_A_ACT_TOINTD 0x00010000 // Timer A compare action disable + // time-out interrupt. +#define TIMER_CFG_A_ACT_NONE 0x00000000 // Timer A compare action none. +#define TIMER_CFG_A_ACT_TOGGLE 0x00020000 // Timer A compare action toggle. +#define TIMER_CFG_A_ACT_CLRTO 0x00040000 // Timer A compare action CCP + // clear on time-out. +#define TIMER_CFG_A_ACT_SETTO 0x00060000 // Timer A compare action CCP set + // on time-out. +#define TIMER_CFG_A_ACT_SETTOGTO 0x00080000 // Timer A compare action set CCP + // toggle on time-out. +#define TIMER_CFG_A_ACT_CLRTOGTO 0x000A0000 // Timer A compare action clear + // CCP toggle on time-out. +#define TIMER_CFG_A_ACT_SETCLRTO 0x000C0000 // Timer A compare action set CCP + // clear on time-out. +#define TIMER_CFG_A_ACT_CLRSETTO 0x000E0000 // Timer A compare action clear + // CCP set on time-out. +#define TIMER_CFG_B_ACT_TOINTD 0x00100000 // Timer B compare action disable + // time-out interrupt. +#define TIMER_CFG_B_ACT_NONE 0x00000000 // Timer A compare action none. +#define TIMER_CFG_B_ACT_TOGGLE 0x00200000 // Timer A compare action toggle. +#define TIMER_CFG_B_ACT_CLRTO 0x00400000 // Timer A compare action CCP + // clear on time-out. +#define TIMER_CFG_B_ACT_SETTO 0x00600000 // Timer A compare action CCP set + // on time-out. +#define TIMER_CFG_B_ACT_SETTOGTO 0x00800000 // Timer A compare action set CCP + // toggle on time-out. +#define TIMER_CFG_B_ACT_CLRTOGTO 0x00A00000 // Timer A compare action clear + // CCP toggle on time-out. +#define TIMER_CFG_B_ACT_SETCLRTO 0x00C00000 // Timer A compare action set CCP + // clear on time-out. +#define TIMER_CFG_B_ACT_CLRSETTO 0x0000E000 // Timer A compare action clear + // CCP set on time-out. + +//***************************************************************************** +// +// Values that can be passed to TimerIntEnable, TimerIntDisable, and +// TimerIntClear as the ui32IntFlags parameter, and returned from +// TimerIntStatus. +// +//***************************************************************************** +#define TIMER_TIMB_DMA 0x00002000 // TimerB DMA Complete Interrupt. +#define TIMER_TIMB_MATCH 0x00000800 // TimerB match interrupt +#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt +#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt +#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt +#define TIMER_TIMA_DMA 0x00000020 // TimerA DMA Complete Interrupt. +#define TIMER_TIMA_MATCH 0x00000010 // TimerA match interrupt +#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask +#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt +#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt +#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt + +//***************************************************************************** +// +// Values that can be passed to TimerControlEvent as the ui32Event parameter. +// +//***************************************************************************** +#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges +#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges +#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges + +//***************************************************************************** +// +// Values that can be passed to most of the timer APIs as the ui32Timer +// parameter. +// +//***************************************************************************** +#define TIMER_A 0x000000ff // Timer A +#define TIMER_B 0x0000ff00 // Timer B +#define TIMER_BOTH 0x0000ffff // Timer Both + +//***************************************************************************** +// +// Values that can be passed to TimerSynchronize as the ui32Timers parameter. +// +//***************************************************************************** +#define TIMER_0A_SYNC 0x00000001 // Synchronize Timer 0A +#define TIMER_0B_SYNC 0x00000002 // Synchronize Timer 0B +#define TIMER_1A_SYNC 0x00000004 // Synchronize Timer 1A +#define TIMER_1B_SYNC 0x00000008 // Synchronize Timer 1B +#define TIMER_2A_SYNC 0x00000010 // Synchronize Timer 2A +#define TIMER_2B_SYNC 0x00000020 // Synchronize Timer 2B +#define TIMER_3A_SYNC 0x00000040 // Synchronize Timer 3A +#define TIMER_3B_SYNC 0x00000080 // Synchronize Timer 3B +#define TIMER_4A_SYNC 0x00000100 // Synchronize Timer 4A +#define TIMER_4B_SYNC 0x00000200 // Synchronize Timer 4B +#define TIMER_5A_SYNC 0x00000400 // Synchronize Timer 5A +#define TIMER_5B_SYNC 0x00000800 // Synchronize Timer 5B +#define WTIMER_0A_SYNC 0x00001000 // Synchronize Wide Timer 0A +#define WTIMER_0B_SYNC 0x00002000 // Synchronize Wide Timer 0B +#define WTIMER_1A_SYNC 0x00004000 // Synchronize Wide Timer 1A +#define WTIMER_1B_SYNC 0x00008000 // Synchronize Wide Timer 1B +#define WTIMER_2A_SYNC 0x00010000 // Synchronize Wide Timer 2A +#define WTIMER_2B_SYNC 0x00020000 // Synchronize Wide Timer 2B +#define WTIMER_3A_SYNC 0x00040000 // Synchronize Wide Timer 3A +#define WTIMER_3B_SYNC 0x00080000 // Synchronize Wide Timer 3B +#define WTIMER_4A_SYNC 0x00100000 // Synchronize Wide Timer 4A +#define WTIMER_4B_SYNC 0x00200000 // Synchronize Wide Timer 4B +#define WTIMER_5A_SYNC 0x00400000 // Synchronize Wide Timer 5A +#define WTIMER_5B_SYNC 0x00800000 // Synchronize Wide Timer 5B + +//***************************************************************************** +// +// Values that can be passed to TimerClockSourceSet() or returned from +// TimerClockSourceGet(). +// +//***************************************************************************** +#define TIMER_CLOCK_SYSTEM 0x00000000 +#define TIMER_CLOCK_PIOSC 0x00000001 + +//***************************************************************************** +// +// Values that can be passed to TimerDMAEventSet() or returned from +// TimerDMAEventGet(). +// +//***************************************************************************** +#define TIMER_DMA_MODEMATCH_B 0x00000800 +#define TIMER_DMA_CAPEVENT_B 0x00000400 +#define TIMER_DMA_CAPMATCH_B 0x00000200 +#define TIMER_DMA_TIMEOUT_B 0x00000100 +#define TIMER_DMA_MODEMATCH_A 0x00000010 +#define TIMER_DMA_RTC_A 0x00000008 +#define TIMER_DMA_CAPEVENT_A 0x00000004 +#define TIMER_DMA_CAPMATCH_A 0x00000002 +#define TIMER_DMA_TIMEOUT_A 0x00000001 + +//***************************************************************************** +// +// Values that can be passed to TimerADCEventSet() or returned from +// TimerADCEventGet(). +// +//***************************************************************************** +#define TIMER_ADC_MODEMATCH_B 0x00000800 +#define TIMER_ADC_CAPEVENT_B 0x00000400 +#define TIMER_ADC_CAPMATCH_B 0x00000200 +#define TIMER_ADC_TIMEOUT_B 0x00000100 +#define TIMER_ADC_MODEMATCH_A 0x00000010 +#define TIMER_ADC_RTC_A 0x00000008 +#define TIMER_ADC_CAPEVENT_A 0x00000004 +#define TIMER_ADC_CAPMATCH_A 0x00000002 +#define TIMER_ADC_TIMEOUT_A 0x00000001 + +//***************************************************************************** +// +// Values that can be passed to TimerUpdateMode(). +// +//***************************************************************************** +#define TIMER_UP_LOAD_IMMEDIATE 0x00000000 +#define TIMER_UP_LOAD_TIMEOUT 0x00000100 +#define TIMER_UP_MATCH_IMMEDIATE \ + 0x00000000 +#define TIMER_UP_MATCH_TIMEOUT 0x00000400 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void TimerEnable(uint32_t ui32Base, uint32_t ui32Timer); +extern void TimerDisable(uint32_t ui32Base, uint32_t ui32Timer); +extern void TimerConfigure(uint32_t ui32Base, uint32_t ui32Config); +extern void TimerControlLevel(uint32_t ui32Base, uint32_t ui32Timer, + bool bInvert); +extern void TimerControlTrigger(uint32_t ui32Base, uint32_t ui32Timer, + bool bEnable); +extern void TimerControlEvent(uint32_t ui32Base, uint32_t ui32Timer, + uint32_t ui32Event); +extern void TimerControlStall(uint32_t ui32Base, uint32_t ui32Timer, + bool bStall); +extern void TimerControlWaitOnTrigger(uint32_t ui32Base, uint32_t ui32Timer, + bool bWait); +extern void TimerRTCEnable(uint32_t ui32Base); +extern void TimerRTCDisable(uint32_t ui32Base); +extern void TimerPrescaleSet(uint32_t ui32Base, uint32_t ui32Timer, + uint32_t ui32Value); +extern uint32_t TimerPrescaleGet(uint32_t ui32Base, uint32_t ui32Timer); +extern void TimerPrescaleMatchSet(uint32_t ui32Base, uint32_t ui32Timer, + uint32_t ui32Value); +extern uint32_t TimerPrescaleMatchGet(uint32_t ui32Base, uint32_t ui32Timer); +extern void TimerLoadSet(uint32_t ui32Base, uint32_t ui32Timer, + uint32_t ui32Value); +extern uint32_t TimerLoadGet(uint32_t ui32Base, uint32_t ui32Timer); +extern void TimerLoadSet64(uint32_t ui32Base, uint64_t ui64Value); +extern uint64_t TimerLoadGet64(uint32_t ui32Base); +extern uint32_t TimerValueGet(uint32_t ui32Base, uint32_t ui32Timer); +extern uint64_t TimerValueGet64(uint32_t ui32Base); +extern void TimerMatchSet(uint32_t ui32Base, uint32_t ui32Timer, + uint32_t ui32Value); +extern uint32_t TimerMatchGet(uint32_t ui32Base, uint32_t ui32Timer); +extern void TimerMatchSet64(uint32_t ui32Base, uint64_t ui64Value); +extern uint64_t TimerMatchGet64(uint32_t ui32Base); +extern void TimerIntRegister(uint32_t ui32Base, uint32_t ui32Timer, + void (*pfnHandler)(void)); +extern void TimerIntUnregister(uint32_t ui32Base, uint32_t ui32Timer); +extern void TimerIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void TimerIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern uint32_t TimerIntStatus(uint32_t ui32Base, bool bMasked); +extern void TimerIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void TimerSynchronize(uint32_t ui32Base, uint32_t ui32Timers); +extern uint32_t TimerClockSourceGet(uint32_t ui32Base); +extern void TimerClockSourceSet(uint32_t ui32Base, uint32_t ui32Source); +extern uint32_t TimerADCEventGet(uint32_t ui32Base); +extern void TimerADCEventSet(uint32_t ui32Base, uint32_t ui32ADCEvent); +extern uint32_t TimerDMAEventGet(uint32_t ui32Base); +extern void TimerDMAEventSet(uint32_t ui32Base, uint32_t ui32DMAEvent); +extern void TimerUpdateMode(uint32_t ui32Base, uint32_t ui32Timer, + uint32_t ui32Config); +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_TIMER_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/uart.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/uart.h new file mode 100644 index 0000000000000000000000000000000000000000..3a9397550da02a495963a35bb6159f7cca944549 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/uart.h @@ -0,0 +1,256 @@ +//***************************************************************************** +// +// uart.h - Defines and Macros for the UART. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_UART_H__ +#define __DRIVERLIB_UART_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear +// as the ui32IntFlags parameter, and returned from UARTIntStatus. +// +//***************************************************************************** +#define UART_INT_DMATX 0x20000 // DMA TX interrupt +#define UART_INT_DMARX 0x10000 // DMA RX interrupt +#define UART_INT_9BIT 0x1000 // 9-bit address match interrupt +#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask +#define UART_INT_BE 0x200 // Break Error Interrupt Mask +#define UART_INT_PE 0x100 // Parity Error Interrupt Mask +#define UART_INT_FE 0x080 // Framing Error Interrupt Mask +#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask +#define UART_INT_TX 0x020 // Transmit Interrupt Mask +#define UART_INT_RX 0x010 // Receive Interrupt Mask +#define UART_INT_DSR 0x008 // DSR Modem Interrupt Mask +#define UART_INT_DCD 0x004 // DCD Modem Interrupt Mask +#define UART_INT_CTS 0x002 // CTS Modem Interrupt Mask +#define UART_INT_RI 0x001 // RI Modem Interrupt Mask + +//***************************************************************************** +// +// Values that can be passed to UARTConfigSetExpClk as the ui32Config parameter +// and returned by UARTConfigGetExpClk in the pui32Config parameter. +// Additionally, the UART_CONFIG_PAR_* subset can be passed to +// UARTParityModeSet as the ui32Parity parameter, and are returned by +// UARTParityModeGet. +// +//***************************************************************************** +#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length +#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data +#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data +#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data +#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data +#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits +#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit +#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits +#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity +#define UART_CONFIG_PAR_NONE 0x00000000 // No parity +#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity +#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity +#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one +#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero + +//***************************************************************************** +// +// Values that can be passed to UARTFIFOLevelSet as the ui32TxLevel parameter +// and returned by UARTFIFOLevelGet in the pui32TxLevel. +// +//***************************************************************************** +#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full +#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full +#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full +#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full +#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full + +//***************************************************************************** +// +// Values that can be passed to UARTFIFOLevelSet as the ui32RxLevel parameter +// and returned by UARTFIFOLevelGet in the pui32RxLevel. +// +//***************************************************************************** +#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full +#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full +#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full +#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full +#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full + +//***************************************************************************** +// +// Values that can be passed to UARTDMAEnable() and UARTDMADisable(). +// +//***************************************************************************** +#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error +#define UART_DMA_TX 0x00000002 // Enable DMA for transmit +#define UART_DMA_RX 0x00000001 // Enable DMA for receive + +//***************************************************************************** +// +// Values returned from UARTRxErrorGet(). +// +//***************************************************************************** +#define UART_RXERROR_OVERRUN 0x00000008 +#define UART_RXERROR_BREAK 0x00000004 +#define UART_RXERROR_PARITY 0x00000002 +#define UART_RXERROR_FRAMING 0x00000001 + +//***************************************************************************** +// +// Values that can be passed to UARTHandshakeOutputsSet() or returned from +// UARTHandshakeOutputGet(). +// +//***************************************************************************** +#define UART_OUTPUT_RTS 0x00000800 +#define UART_OUTPUT_DTR 0x00000400 + +//***************************************************************************** +// +// Values that can be returned from UARTHandshakeInputsGet(). +// +//***************************************************************************** +#define UART_INPUT_RI 0x00000100 +#define UART_INPUT_DCD 0x00000004 +#define UART_INPUT_DSR 0x00000002 +#define UART_INPUT_CTS 0x00000001 + +//***************************************************************************** +// +// Values that can be passed to UARTFlowControl() or returned from +// UARTFlowControlGet(). +// +//***************************************************************************** +#define UART_FLOWCONTROL_TX 0x00008000 +#define UART_FLOWCONTROL_RX 0x00004000 +#define UART_FLOWCONTROL_NONE 0x00000000 + +//***************************************************************************** +// +// Values that can be passed to UARTTxIntModeSet() or returned from +// UARTTxIntModeGet(). +// +//***************************************************************************** +#define UART_TXINT_MODE_FIFO 0x00000000 +#define UART_TXINT_MODE_EOT 0x00000010 + +//***************************************************************************** +// +// Values that can be passed to UARTClockSourceSet() or returned from +// UARTClockSourceGet(). +// +//***************************************************************************** +#define UART_CLOCK_SYSTEM 0x00000000 +#define UART_CLOCK_PIOSC 0x00000005 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void UARTParityModeSet(uint32_t ui32Base, uint32_t ui32Parity); +extern uint32_t UARTParityModeGet(uint32_t ui32Base); +extern void UARTFIFOLevelSet(uint32_t ui32Base, uint32_t ui32TxLevel, + uint32_t ui32RxLevel); +extern void UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel, + uint32_t *pui32RxLevel); +extern void UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, + uint32_t ui32Baud, uint32_t ui32Config); +extern void UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, + uint32_t *pui32Baud, uint32_t *pui32Config); +extern void UARTEnable(uint32_t ui32Base); +extern void UARTDisable(uint32_t ui32Base); +extern void UARTFIFOEnable(uint32_t ui32Base); +extern void UARTFIFODisable(uint32_t ui32Base); +extern void UARTEnableSIR(uint32_t ui32Base, bool bLowPower); +extern void UARTDisableSIR(uint32_t ui32Base); +extern bool UARTCharsAvail(uint32_t ui32Base); +extern bool UARTSpaceAvail(uint32_t ui32Base); +extern int32_t UARTCharGetNonBlocking(uint32_t ui32Base); +extern int32_t UARTCharGet(uint32_t ui32Base); +extern bool UARTCharPutNonBlocking(uint32_t ui32Base, unsigned char ucData); +extern void UARTCharPut(uint32_t ui32Base, unsigned char ucData); +extern void UARTBreakCtl(uint32_t ui32Base, bool bBreakState); +extern bool UARTBusy(uint32_t ui32Base); +extern void UARTIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); +extern void UARTIntUnregister(uint32_t ui32Base); +extern void UARTIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void UARTIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern uint32_t UARTIntStatus(uint32_t ui32Base, bool bMasked); +extern void UARTIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void UARTDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags); +extern void UARTDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags); +extern uint32_t UARTRxErrorGet(uint32_t ui32Base); +extern void UARTRxErrorClear(uint32_t ui32Base); +extern void UARTSmartCardEnable(uint32_t ui32Base); +extern void UARTSmartCardDisable(uint32_t ui32Base); +extern void UARTModemControlSet(uint32_t ui32Base, uint32_t ui32Control); +extern void UARTModemControlClear(uint32_t ui32Base, uint32_t ui32Control); +extern uint32_t UARTModemControlGet(uint32_t ui32Base); +extern uint32_t UARTModemStatusGet(uint32_t ui32Base); +extern void UARTFlowControlSet(uint32_t ui32Base, uint32_t ui32Mode); +extern uint32_t UARTFlowControlGet(uint32_t ui32Base); +extern void UARTTxIntModeSet(uint32_t ui32Base, uint32_t ui32Mode); +extern uint32_t UARTTxIntModeGet(uint32_t ui32Base); +extern void UARTClockSourceSet(uint32_t ui32Base, uint32_t ui32Source); +extern uint32_t UARTClockSourceGet(uint32_t ui32Base); +extern void UART9BitEnable(uint32_t ui32Base); +extern void UART9BitDisable(uint32_t ui32Base); +extern void UART9BitAddrSet(uint32_t ui32Base, uint8_t ui8Addr, + uint8_t ui8Mask); +extern void UART9BitAddrSend(uint32_t ui32Base, uint8_t ui8Addr); +extern void UARTLoopbackEnable(uint32_t ui32Base); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_UART_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/udma.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/udma.h new file mode 100644 index 0000000000000000000000000000000000000000..a8d3684489587cee20a50470ad34506f9fb7e1df --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/udma.h @@ -0,0 +1,890 @@ +//***************************************************************************** +// +// udma.h - Prototypes and macros for the uDMA controller. +// +// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_UDMA_H__ +#define __DRIVERLIB_UDMA_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup udma_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// A structure that defines an entry in the channel control table. These +// fields are used by the uDMA controller and normally it is not necessary for +// software to directly read or write fields in the table. +// +//***************************************************************************** +typedef struct +{ + // + // The ending source address of the data transfer. + // + volatile void *pvSrcEndAddr; + + // + // The ending destination address of the data transfer. + // + volatile void *pvDstEndAddr; + + // + // The channel control mode. + // + volatile uint32_t ui32Control; + + // + // An unused location. + // + volatile uint32_t ui32Spare; +} +tDMAControlTable; + +//***************************************************************************** +// +//! A helper macro for building scatter-gather task table entries. +//! +//! \param ui32TransferCount is the count of items to transfer for this task. +//! \param ui32ItemSize is the bit size of the items to transfer for this task. +//! \param ui32SrcIncrement is the bit size increment for source data. +//! \param pvSrcAddr is the starting address of the data to transfer. +//! \param ui32DstIncrement is the bit size increment for destination data. +//! \param pvDstAddr is the starting address of the destination data. +//! \param ui32ArbSize is the arbitration size to use for the transfer task. +//! \param ui32Mode is the transfer mode for this task. +//! +//! This macro is intended to be used to help populate a table of uDMA tasks +//! for a scatter-gather transfer. This macro will calculate the values for +//! the fields of a task structure entry based on the input parameters. +//! +//! There are specific requirements for the values of each parameter. No +//! checking is done so it is up to the caller to ensure that correct values +//! are used for the parameters. +//! +//! The \e ui32TransferCount parameter is the number of items that will be +//! transferred by this task. It must be in the range 1-1024. +//! +//! The \e ui32ItemSize parameter is the bit size of the transfer data. It +//! must be one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or \b UDMA_SIZE_32. +//! +//! The \e ui32SrcIncrement parameter is the increment size for the source +//! data. It must be one of \b UDMA_SRC_INC_8, \b UDMA_SRC_INC_16, +//! \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE. +//! +//! The \e pvSrcAddr parameter is a void pointer to the beginning of the source +//! data. +//! +//! The \e ui32DstIncrement parameter is the increment size for the destination +//! data. It must be one of \b UDMA_DST_INC_8, \b UDMA_DST_INC_16, +//! \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE. +//! +//! The \e pvDstAddr parameter is a void pointer to the beginning of the +//! location where the data will be transferred. +//! +//! The \e ui32ArbSize parameter is the arbitration size for the transfer, and +//! must be one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, and so on +//! up to \b UDMA_ARB_1024. This is used to select the arbitration size in +//! powers of 2, from 1 to 1024. +//! +//! The \e ui32Mode parameter is the mode to use for this transfer task. It +//! must be one of \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO, +//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER. Note +//! that normally all tasks will be one of the scatter-gather modes while the +//! last task is a task list will be AUTO or BASIC. +//! +//! This macro is intended to be used to initialize individual entries of +//! a structure of tDMAControlTable type, like this: +//! +//! \verbatim +//! tDMAControlTable MyTaskList[] = +//! { +//! uDMATaskStructEntry(Task1Count, UDMA_SIZE_8, +//! UDMA_SRC_INC_8, MySourceBuf, +//! UDMA_DST_INC_8, MyDestBuf, +//! UDMA_ARB_8, UDMA_MODE_MEM_SCATTER_GATHER), +//! uDMATaskStructEntry(Task2Count, ...), +//! } +//! \endverbatim +//! +//! \return Nothing; this is not a function. +// +//***************************************************************************** +#define uDMATaskStructEntry(ui32TransferCount, \ + ui32ItemSize, \ + ui32SrcIncrement, \ + pvSrcAddr, \ + ui32DstIncrement, \ + pvDstAddr, \ + ui32ArbSize, \ + ui32Mode) \ + { \ + (((ui32SrcIncrement) == UDMA_SRC_INC_NONE) ? (void *)(pvSrcAddr) : \ + ((void *)(&((uint8_t *)(pvSrcAddr))[((ui32TransferCount) << \ + ((ui32SrcIncrement) >> 26)) - 1]))), \ + (((ui32DstIncrement) == UDMA_DST_INC_NONE) ? (void *)(pvDstAddr) :\ + ((void *)(&((uint8_t *)(pvDstAddr))[((ui32TransferCount) << \ + ((ui32DstIncrement) >> 30)) - 1]))), \ + (ui32SrcIncrement) | (ui32DstIncrement) | (ui32ItemSize) | \ + (ui32ArbSize) | \ + (((ui32TransferCount) - 1) << 4) | \ + ((((ui32Mode) == UDMA_MODE_MEM_SCATTER_GATHER) || \ + ((ui32Mode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \ + (ui32Mode) | UDMA_MODE_ALT_SELECT : (ui32Mode)), 0 \ + } + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Flags that can be passed to uDMAChannelAttributeEnable(), +// uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet(). +// +//***************************************************************************** +#define UDMA_ATTR_USEBURST 0x00000001 +#define UDMA_ATTR_ALTSELECT 0x00000002 +#define UDMA_ATTR_HIGH_PRIORITY 0x00000004 +#define UDMA_ATTR_REQMASK 0x00000008 +#define UDMA_ATTR_ALL 0x0000000F + +//***************************************************************************** +// +// DMA control modes that can be passed to uDMAModeSet() and returned +// uDMAModeGet(). +// +//***************************************************************************** +#define UDMA_MODE_STOP 0x00000000 +#define UDMA_MODE_BASIC 0x00000001 +#define UDMA_MODE_AUTO 0x00000002 +#define UDMA_MODE_PINGPONG 0x00000003 +#define UDMA_MODE_MEM_SCATTER_GATHER \ + 0x00000004 +#define UDMA_MODE_PER_SCATTER_GATHER \ + 0x00000006 +#define UDMA_MODE_ALT_SELECT 0x00000001 + +//***************************************************************************** +// +// Channel configuration values that can be passed to uDMAControlSet(). +// +//***************************************************************************** +#define UDMA_DST_INC_8 0x00000000 +#define UDMA_DST_INC_16 0x40000000 +#define UDMA_DST_INC_32 0x80000000 +#define UDMA_DST_INC_NONE 0xc0000000 +#define UDMA_SRC_INC_8 0x00000000 +#define UDMA_SRC_INC_16 0x04000000 +#define UDMA_SRC_INC_32 0x08000000 +#define UDMA_SRC_INC_NONE 0x0c000000 +#define UDMA_SIZE_8 0x00000000 +#define UDMA_SIZE_16 0x11000000 +#define UDMA_SIZE_32 0x22000000 +#define UDMA_DST_PROT_PRIV 0x00200000 +#define UDMA_SRC_PROT_PRIV 0x00040000 +#define UDMA_ARB_1 0x00000000 +#define UDMA_ARB_2 0x00004000 +#define UDMA_ARB_4 0x00008000 +#define UDMA_ARB_8 0x0000c000 +#define UDMA_ARB_16 0x00010000 +#define UDMA_ARB_32 0x00014000 +#define UDMA_ARB_64 0x00018000 +#define UDMA_ARB_128 0x0001c000 +#define UDMA_ARB_256 0x00020000 +#define UDMA_ARB_512 0x00024000 +#define UDMA_ARB_1024 0x00028000 +#define UDMA_NEXT_USEBURST 0x00000008 + +//***************************************************************************** +// +// Channel numbers to be passed to API functions that require a channel number +// ID. +// +//***************************************************************************** +#define UDMA_CHANNEL_USBEP1RX 0 +#define UDMA_CHANNEL_USBEP1TX 1 +#define UDMA_CHANNEL_USBEP2RX 2 +#define UDMA_CHANNEL_USBEP2TX 3 +#define UDMA_CHANNEL_USBEP3RX 4 +#define UDMA_CHANNEL_USBEP3TX 5 +#define UDMA_CHANNEL_ETH0RX 6 +#define UDMA_CHANNEL_ETH0TX 7 +#define UDMA_CHANNEL_UART0RX 8 +#define UDMA_CHANNEL_UART0TX 9 +#define UDMA_CHANNEL_SSI0RX 10 +#define UDMA_CHANNEL_SSI0TX 11 +#define UDMA_CHANNEL_ADC0 14 +#define UDMA_CHANNEL_ADC1 15 +#define UDMA_CHANNEL_ADC2 16 +#define UDMA_CHANNEL_ADC3 17 +#define UDMA_CHANNEL_TMR0A 18 +#define UDMA_CHANNEL_TMR0B 19 +#define UDMA_CHANNEL_TMR1A 20 +#define UDMA_CHANNEL_TMR1B 21 +#define UDMA_CHANNEL_UART1RX 22 +#define UDMA_CHANNEL_UART1TX 23 +#define UDMA_CHANNEL_SSI1RX 24 +#define UDMA_CHANNEL_SSI1TX 25 +#define UDMA_CHANNEL_I2S0RX 28 +#define UDMA_CHANNEL_I2S0TX 29 +#define UDMA_CHANNEL_SW 30 + +//***************************************************************************** +// +// Flags to be OR'd with the channel ID to indicate if the primary or alternate +// control structure should be used. +// +//***************************************************************************** +#define UDMA_PRI_SELECT 0x00000000 +#define UDMA_ALT_SELECT 0x00000020 + +//***************************************************************************** +// +// Channel numbers to be passed to API functions that require a channel number +// ID. These are for secondary peripheral assignments. +// +//***************************************************************************** +#define UDMA_SEC_CHANNEL_UART2RX_0 \ + 0 +#define UDMA_SEC_CHANNEL_UART2TX_1 \ + 1 +#define UDMA_SEC_CHANNEL_TMR3A 2 +#define UDMA_SEC_CHANNEL_TMR3B 3 +#define UDMA_SEC_CHANNEL_TMR2A_4 \ + 4 +#define UDMA_SEC_CHANNEL_TMR2B_5 \ + 5 +#define UDMA_SEC_CHANNEL_TMR2A_6 \ + 6 +#define UDMA_SEC_CHANNEL_TMR2B_7 \ + 7 +#define UDMA_SEC_CHANNEL_UART1RX \ + 8 +#define UDMA_SEC_CHANNEL_UART1TX \ + 9 +#define UDMA_SEC_CHANNEL_SSI1RX 10 +#define UDMA_SEC_CHANNEL_SSI1TX 11 +#define UDMA_SEC_CHANNEL_UART2RX_12 \ + 12 +#define UDMA_SEC_CHANNEL_UART2TX_13 \ + 13 +#define UDMA_SEC_CHANNEL_TMR2A_14 \ + 14 +#define UDMA_SEC_CHANNEL_TMR2B_15 \ + 15 +#define UDMA_SEC_CHANNEL_TMR1A 18 +#define UDMA_SEC_CHANNEL_TMR1B 19 +#define UDMA_SEC_CHANNEL_EPI0RX 20 +#define UDMA_SEC_CHANNEL_EPI0TX 21 +#define UDMA_SEC_CHANNEL_ADC10 24 +#define UDMA_SEC_CHANNEL_ADC11 25 +#define UDMA_SEC_CHANNEL_ADC12 26 +#define UDMA_SEC_CHANNEL_ADC13 27 +#define UDMA_SEC_CHANNEL_SW 30 + +//***************************************************************************** +// +// Values that can be passed to uDMAChannelAssign() to select peripheral +// mapping for each channel. The channels named RESERVED may be assigned +// to a peripheral in future parts. +// +//***************************************************************************** +// +// Channel 0 +// +#define UDMA_CH0_USB0EP1RX 0x00000000 +#define UDMA_CH0_UART2RX 0x00010000 +#define UDMA_CH0_RESERVED2 0x00020000 +#define UDMA_CH0_TIMER4A 0x00030000 +#define UDMA_CH0_RESERVED4 0x00040000 +#define UDMA_CH0_RESERVED5 0x00050000 +#define UDMA_CH0_I2C0RX 0x00060000 +#define UDMA_CH0_RESERVED7 0x00070000 +#define UDMA_CH0_RESERVED8 0x00080000 + +// +// Channel 1 +// +#define UDMA_CH1_USB0EP1TX 0x00000001 +#define UDMA_CH1_UART2TX 0x00010001 +#define UDMA_CH1_RESERVED2 0x00020001 +#define UDMA_CH1_TIMER4B 0x00030001 +#define UDMA_CH1_RESERVED4 0x00040001 +#define UDMA_CH1_RESERVED5 0x00050001 +#define UDMA_CH1_I2C0TX 0x00060001 +#define UDMA_CH1_RESERVED7 0x00070001 +#define UDMA_CH1_RESERVED8 0x00080001 + +// +// Channel 2 +// +#define UDMA_CH2_USB0EP2RX 0x00000002 +#define UDMA_CH2_TIMER3A 0x00010002 +#define UDMA_CH2_RESERVED2 0x00020002 +#define UDMA_CH2_RESERVED3 0x00030002 +#define UDMA_CH2_RESERVED4 0x00040002 +#define UDMA_CH2_RESERVED5 0x00050002 +#define UDMA_CH2_I2C1RX 0x00060002 +#define UDMA_CH2_RESERVED7 0x00070002 +#define UDMA_CH2_RESERVED8 0x00080002 + +// +// Channel 3 +// +#define UDMA_CH3_USB0EP2TX 0x00000003 +#define UDMA_CH3_TIMER3B 0x00010003 +#define UDMA_CH3_RESERVED2 0x00020003 +#define UDMA_CH3_LPC0_3 0x00030003 +#define UDMA_CH3_RESERVED4 0x00040003 +#define UDMA_CH3_RESERVED5 0x00050003 +#define UDMA_CH3_I2C1TX 0x00060003 +#define UDMA_CH3_RESERVED7 0x00070003 +#define UDMA_CH3_RESERVED8 0x00080003 + +// +// Channel 4 +// +#define UDMA_CH4_USB0EP3RX 0x00000004 +#define UDMA_CH4_TIMER2A 0x00010004 +#define UDMA_CH4_RESERVED2 0x00020004 +#define UDMA_CH4_GPIOA 0x00030004 +#define UDMA_CH4_RESERVED4 0x00040004 +#define UDMA_CH4_SHAMD50CIN 0x00050004 +#define UDMA_CH4_I2C2RX 0x00060004 +#define UDMA_CH4_RESERVED7 0x00070004 +#define UDMA_CH4_RESERVED8 0x00080004 + +// +// Channel 5 +// +#define UDMA_CH5_USB0EP3TX 0x00000005 +#define UDMA_CH5_TIMER2B 0x00010005 +#define UDMA_CH5_RESERVED2 0x00020005 +#define UDMA_CH5_GPIOB 0x00030005 +#define UDMA_CH5_RESERVED4 0x00040005 +#define UDMA_CH5_SHAMD50DIN 0x00050005 +#define UDMA_CH5_I2C2TX 0x00060005 +#define UDMA_CH5_RESERVED7 0x00070005 +#define UDMA_CH5_RESERVED8 0x00080005 + +// +// Channel 6 +// +#define UDMA_CH6_RESERVED0 0x00000006 +#define UDMA_CH6_ETH0RX 0x00000006 +#define UDMA_CH6_TIMER2A 0x00010006 +#define UDMA_CH6_UART5RX 0x00020006 +#define UDMA_CH6_GPIOC 0x00030006 +#define UDMA_CH6_I2C0RX 0x00040006 +#define UDMA_CH6_SHAMD50COUT 0x00050006 +#define UDMA_CH6_RESERVED6 0x00060006 +#define UDMA_CH6_RESERVED7 0x00070006 +#define UDMA_CH6_RESERVED8 0x00080006 + +// +// Channel 7 +// +#define UDMA_CH7_RESERVED0 0x00000007 +#define UDMA_CH7_ETH0TX 0x00000007 +#define UDMA_CH7_TIMER2B 0x00010007 +#define UDMA_CH7_UART5TX 0x00020007 +#define UDMA_CH7_GPIOD 0x00030007 +#define UDMA_CH7_I2C0TX 0x00040007 +#define UDMA_CH7_RESERVED5 0x00050007 +#define UDMA_CH7_RESERVED6 0x00060007 +#define UDMA_CH7_RESERVED7 0x00070007 +#define UDMA_CH7_RESERVED8 0x00080007 + +// +// Channel 8 +// +#define UDMA_CH8_UART0RX 0x00000008 +#define UDMA_CH8_UART1RX 0x00010008 +#define UDMA_CH8_RESERVED2 0x00020008 +#define UDMA_CH8_TIMER5A 0x00030008 +#define UDMA_CH8_I2C1RX 0x00040008 +#define UDMA_CH8_RESERVED5 0x00050008 +#define UDMA_CH8_RESERVED6 0x00060008 +#define UDMA_CH8_RESERVED7 0x00070008 +#define UDMA_CH8_RESERVED8 0x00080008 + +// +// Channel 9 +// +#define UDMA_CH9_UART0TX 0x00000009 +#define UDMA_CH9_UART1TX 0x00010009 +#define UDMA_CH9_RESERVED2 0x00020009 +#define UDMA_CH9_TIMER5B 0x00030009 +#define UDMA_CH9_I2C1TX 0x00040009 +#define UDMA_CH9_RESERVED5 0x00050009 +#define UDMA_CH9_RESERVED6 0x00060009 +#define UDMA_CH9_RESERVED7 0x00070009 +#define UDMA_CH9_RESERVED8 0x00080009 + +// +// Channel 10 +// +#define UDMA_CH10_SSI0RX 0x0000000A +#define UDMA_CH10_SSI1RX 0x0001000A +#define UDMA_CH10_UART6RX 0x0002000A +#define UDMA_CH10_WTIMER0A 0x0003000A +#define UDMA_CH10_I2C2RX 0x0004000A +#define UDMA_CH10_RESERVED5 0x0005000A +#define UDMA_CH10_RESERVED6 0x0006000A +#define UDMA_CH10_TIMER6A 0x0007000A +#define UDMA_CH10_RESERVED8 0x0008000A + +// +// Channel 11 +// +#define UDMA_CH11_SSI0TX 0x0000000B +#define UDMA_CH11_SSI1TX 0x0001000B +#define UDMA_CH11_UART6TX 0x0002000B +#define UDMA_CH11_WTIMER0B 0x0003000B +#define UDMA_CH11_I2C2TX 0x0004000B +#define UDMA_CH11_RESERVED5 0x0005000B +#define UDMA_CH11_RESERVED6 0x0006000B +#define UDMA_CH11_TIMER6B 0x0007000B +#define UDMA_CH11_RESERVED8 0x0008000B + +// +// Channel 12 +// +#define UDMA_CH12_RESERVED0 0x0000000C +#define UDMA_CH12_UART2RX 0x0001000C +#define UDMA_CH12_SSI2RX 0x0002000C +#define UDMA_CH12_WTIMER1A 0x0003000C +#define UDMA_CH12_GPIOK 0x0004000C +#define UDMA_CH12_AES0CIN 0x0005000C +#define UDMA_CH12_RESERVED6 0x0006000C +#define UDMA_CH12_TIMER7A 0x0007000C +#define UDMA_CH12_RESERVED8 0x0008000C + +// +// Channel 13 +// +#define UDMA_CH13_RESERVED0 0x0000000D +#define UDMA_CH13_UART2TX 0x0001000D +#define UDMA_CH13_SSI2TX 0x0002000D +#define UDMA_CH13_WTIMER1B 0x0003000D +#define UDMA_CH13_GPIOL 0x0004000D +#define UDMA_CH13_AES0COUT 0x0005000D +#define UDMA_CH13_RESERVED6 0x0006000D +#define UDMA_CH13_TIMER7B 0x0007000D +#define UDMA_CH13_RESERVED8 0x0008000D + +// +// Channel 14 +// +#define UDMA_CH14_ADC0_0 0x0000000E +#define UDMA_CH14_TIMER2A 0x0001000E +#define UDMA_CH14_SSI3RX 0x0002000E +#define UDMA_CH14_GPIOE 0x0003000E +#define UDMA_CH14_GPIOM 0x0004000E +#define UDMA_CH14_AES0DIN 0x0005000E +#define UDMA_CH14_RESERVED6 0x0006000E +#define UDMA_CH14_RESERVED7 0x0007000E +#define UDMA_CH14_RESERVED8 0x0008000E + +// +// Channel 15 +// +#define UDMA_CH15_ADC0_1 0x0000000F +#define UDMA_CH15_TIMER2B 0x0001000F +#define UDMA_CH15_SSI3TX 0x0002000F +#define UDMA_CH15_GPIOF 0x0003000F +#define UDMA_CH15_GPION 0x0004000F +#define UDMA_CH15_AES0DOUT 0x0005000F +#define UDMA_CH15_RESERVED6 0x0006000F +#define UDMA_CH15_RESERVED7 0x0007000F +#define UDMA_CH15_RESERVED8 0x0008000F + +// +// Channel 16 +// +#define UDMA_CH16_ADC0_2 0x00000010 +#define UDMA_CH16_RESERVED1 0x00010010 +#define UDMA_CH16_UART3RX 0x00020010 +#define UDMA_CH16_WTIMER2A 0x00030010 +#define UDMA_CH16_GPIOP 0x00040010 +#define UDMA_CH16_RESERVED5 0x00050010 +#define UDMA_CH16_RESERVED6 0x00060010 +#define UDMA_CH16_RESERVED7 0x00070010 +#define UDMA_CH16_RESERVED8 0x00080010 + +// +// Channel 17 +// +#define UDMA_CH17_ADC0_3 0x00000011 +#define UDMA_CH17_RESERVED1 0x00010011 +#define UDMA_CH17_UART3TX 0x00020011 +#define UDMA_CH17_WTIMER2B 0x00030011 +#define UDMA_CH17_RESERVED4 0x00040011 +#define UDMA_CH17_RESERVED5 0x00050011 +#define UDMA_CH17_RESERVED6 0x00060011 +#define UDMA_CH17_RESERVED7 0x00070011 +#define UDMA_CH17_RESERVED8 0x00080011 + +// +// Channel 18 +// +#define UDMA_CH18_TIMER0A 0x00000012 +#define UDMA_CH18_TIMER1A 0x00010012 +#define UDMA_CH18_UART4RX 0x00020012 +#define UDMA_CH18_GPIOB 0x00030012 +#define UDMA_CH18_I2C3RX 0x00040012 +#define UDMA_CH18_RESERVED5 0x00050012 +#define UDMA_CH18_RESERVED6 0x00060012 +#define UDMA_CH18_RESERVED7 0x00070012 +#define UDMA_CH18_RESERVED8 0x00080012 + +// +// Channel 19 +// +#define UDMA_CH19_TIMER0B 0x00000013 +#define UDMA_CH19_TIMER1B 0x00010013 +#define UDMA_CH19_UART4TX 0x00020013 +#define UDMA_CH19_GPIOG 0x00030013 +#define UDMA_CH19_I2C3TX 0x00040013 +#define UDMA_CH19_RESERVED5 0x00050013 +#define UDMA_CH19_RESERVED6 0x00060013 +#define UDMA_CH19_RESERVED7 0x00070013 +#define UDMA_CH19_RESERVED8 0x00080013 + +// +// Channel 20 +// +#define UDMA_CH20_TIMER1A 0x00000014 +#define UDMA_CH20_RESERVED1 0x00010014 +#define UDMA_CH20_EPI0RX 0x00010014 +#define UDMA_CH20_UART7RX 0x00020014 +#define UDMA_CH20_GPIOH 0x00030014 +#define UDMA_CH20_I2C4RX 0x00040014 +#define UDMA_CH20_DES0CIN 0x00050014 +#define UDMA_CH20_RESERVED6 0x00060014 +#define UDMA_CH20_RESERVED7 0x00070014 +#define UDMA_CH20_RESERVED8 0x00080014 + +// +// Channel 21 +// +#define UDMA_CH21_TIMER1B 0x00000015 +#define UDMA_CH21_RESERVED1 0x00010015 +#define UDMA_CH21_EPI0TX 0x00010015 +#define UDMA_CH21_UART7TX 0x00020015 +#define UDMA_CH21_GPIOJ 0x00030015 +#define UDMA_CH21_I2C4TX 0x00040015 +#define UDMA_CH21_DES0DIN 0x00050015 +#define UDMA_CH21_RESERVED6 0x00060015 +#define UDMA_CH21_RESERVED7 0x00070015 +#define UDMA_CH21_RESERVED8 0x00080015 + +// +// Channel 22 +// +#define UDMA_CH22_UART1RX 0x00000016 +#define UDMA_CH22_RESERVED1 0x00010016 +#define UDMA_CH22_RESERVED2 0x00020016 +#define UDMA_CH22_LPC0_2 0x00030016 +#define UDMA_CH22_I2C5RX 0x00040016 +#define UDMA_CH22_DES0DOUT 0x00050016 +#define UDMA_CH22_RESERVED6 0x00060016 +#define UDMA_CH22_RESERVED7 0x00070016 +#define UDMA_CH22_I2C8RX 0x00080016 + +// +// Channel 23 +// +#define UDMA_CH23_UART1TX 0x00000017 +#define UDMA_CH23_RESERVED1 0x00010017 +#define UDMA_CH23_RESERVED2 0x00020017 +#define UDMA_CH23_LPC0_1 0x00030017 +#define UDMA_CH23_I2C5TX 0x00040017 +#define UDMA_CH23_RESERVED5 0x00050017 +#define UDMA_CH23_RESERVED6 0x00060017 +#define UDMA_CH23_RESERVED7 0x00070017 +#define UDMA_CH23_I2C8TX 0x00080017 + +// +// Channel 24 +// +#define UDMA_CH24_SSI1RX 0x00000018 +#define UDMA_CH24_ADC1_0 0x00010018 +#define UDMA_CH24_RESERVED2 0x00020018 +#define UDMA_CH24_WTIMER3A 0x00030018 +#define UDMA_CH24_GPIOQ 0x00040018 +#define UDMA_CH24_RESERVED5 0x00050018 +#define UDMA_CH24_RESERVED6 0x00060018 +#define UDMA_CH24_RESERVED7 0x00070018 +#define UDMA_CH24_I2C9RX 0x00080018 + +// +// Channel 25 +// +#define UDMA_CH25_SSI1TX 0x00000019 +#define UDMA_CH25_ADC1_1 0x00010019 +#define UDMA_CH25_RESERVED2 0x00020019 +#define UDMA_CH25_WTIMER3B 0x00030019 +#define UDMA_CH25_RESERVED4 0x00040019 +#define UDMA_CH25_RESERVED5 0x00050019 +#define UDMA_CH25_RESERVED6 0x00060019 +#define UDMA_CH25_RESERVED7 0x00070019 +#define UDMA_CH25_I2C9TX 0x00080019 + +// +// Channel 26 +// +#define UDMA_CH26_RESERVED0 0x0000001A +#define UDMA_CH26_ADC1_2 0x0001001A +#define UDMA_CH26_RESERVED2 0x0002001A +#define UDMA_CH26_WTIMER4A 0x0003001A +#define UDMA_CH26_RESERVED4 0x0004001A +#define UDMA_CH26_RESERVED5 0x0005001A +#define UDMA_CH26_RESERVED6 0x0006001A +#define UDMA_CH26_RESERVED7 0x0007001A +#define UDMA_CH26_I2C6RX 0x0008001A + +// +// Channel 27 +// +#define UDMA_CH27_RESERVED0 0x0000001B +#define UDMA_CH27_ADC1_3 0x0001001B +#define UDMA_CH27_RESERVED2 0x0002001B +#define UDMA_CH27_WTIMER4B 0x0003001B +#define UDMA_CH27_RESERVED4 0x0004001B +#define UDMA_CH27_RESERVED5 0x0005001B +#define UDMA_CH27_RESERVED6 0x0006001B +#define UDMA_CH27_RESERVED7 0x0007001B +#define UDMA_CH27_I2C6TX 0x0008001B + +// +// Channel 28 +// +#define UDMA_CH28_RESERVED0 0x0000001C +#define UDMA_CH28_RESERVED1 0x0001001C +#define UDMA_CH28_RESERVED2 0x0002001C +#define UDMA_CH28_WTIMER5A 0x0003001C +#define UDMA_CH28_RESERVED4 0x0004001C +#define UDMA_CH28_RESERVED5 0x0005001C +#define UDMA_CH28_RESERVED6 0x0006001C +#define UDMA_CH28_RESERVED7 0x0007001C +#define UDMA_CH28_I2C7RX 0x0008001C + +// +// Channel 29 +// +#define UDMA_CH29_RESERVED0 0x0000001D +#define UDMA_CH29_RESERVED1 0x0001001D +#define UDMA_CH29_RESERVED2 0x0002001D +#define UDMA_CH29_WTIMER5B 0x0003001D +#define UDMA_CH29_RESERVED4 0x0004001D +#define UDMA_CH29_RESERVED5 0x0005001D +#define UDMA_CH29_RESERVED6 0x0006001D +#define UDMA_CH29_RESERVED7 0x0007001D +#define UDMA_CH29_I2C7TX 0x0008001D + +// +// Channel 30 +// +#define UDMA_CH30_SW 0x0000001E +#define UDMA_CH30_RESERVED1 0x0001001E +#define UDMA_CH30_RESERVED2 0x0002001E +#define UDMA_CH30_RESERVED3 0x0003001E +#define UDMA_CH30_RESERVED4 0x0004001E +#define UDMA_CH30_RESERVED5 0x0005001E +#define UDMA_CH30_RESERVED6 0x0006001E +#define UDMA_CH30_EPI0RX 0x0007001E +#define UDMA_CH30_1WIRE0 0x0008001E + +// +// Channel 31 +// +#define UDMA_CH31_RESERVED0 0x0000001F +#define UDMA_CH31_RESERVED1 0x0001001F +#define UDMA_CH31_RESERVED2 0x0002001F +#define UDMA_CH31_LPC0_0 0x0003001F +#define UDMA_CH31_RESERVED4 0x0004001F +#define UDMA_CH31_RESERVED5 0x0005001F +#define UDMA_CH31_RESERVED6 0x0006001F +#define UDMA_CH31_EPI0RX 0x0007001F +#define UDMA_CH31_RESERVED8 0x0008001F + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void uDMAEnable(void); +extern void uDMADisable(void); +extern uint32_t uDMAErrorStatusGet(void); +extern void uDMAErrorStatusClear(void); +extern void uDMAChannelEnable(uint32_t ui32ChannelNum); +extern void uDMAChannelDisable(uint32_t ui32ChannelNum); +extern bool uDMAChannelIsEnabled(uint32_t ui32ChannelNum); +extern void uDMAControlBaseSet(void *pControlTable); +extern void *uDMAControlBaseGet(void); +extern void *uDMAControlAlternateBaseGet(void); +extern void uDMAChannelRequest(uint32_t ui32ChannelNum); +extern void uDMAChannelAttributeEnable(uint32_t ui32ChannelNum, + uint32_t ui32Attr); +extern void uDMAChannelAttributeDisable(uint32_t ui32ChannelNum, + uint32_t ui32Attr); +extern uint32_t uDMAChannelAttributeGet(uint32_t ui32ChannelNum); +extern void uDMAChannelControlSet(uint32_t ui32ChannelStructIndex, + uint32_t ui32Control); +extern void uDMAChannelTransferSet(uint32_t ui32ChannelStructIndex, + uint32_t ui32Mode, void *pvSrcAddr, + void *pvDstAddr, uint32_t ui32TransferSize); +extern void uDMAChannelScatterGatherSet(uint32_t ui32ChannelNum, + uint32_t ui32TaskCount, + void *pvTaskList, + uint32_t ui32IsPeriphSG); +extern uint32_t uDMAChannelSizeGet(uint32_t ui32ChannelStructIndex); +extern uint32_t uDMAChannelModeGet(uint32_t ui32ChannelStructIndex); +extern void uDMAIntRegister(uint32_t ui32IntChannel, void (*pfnHandler)(void)); +extern void uDMAIntUnregister(uint32_t ui32IntChannel); +extern uint32_t uDMAIntStatus(void); +extern void uDMAIntClear(uint32_t ui32ChanMask); +extern void uDMAChannelAssign(uint32_t ui32Mapping); + +//***************************************************************************** +// +// The following functions and definitions are deprecated and will be removed +// from the API in the future. Use uDMAChannelAssign() instead to accomplish +// the same end. +// +//***************************************************************************** +#ifndef DEPRECATED +//***************************************************************************** +// +// uDMA default/secondary peripheral selections, to be passed to +// uDMAChannelSelectSecondary() and uDMAChannelSelectDefault(). +// +//***************************************************************************** +#define UDMA_DEF_USBEP1RX_SEC_UART2RX \ + 0x00000001 +#define UDMA_DEF_USBEP1TX_SEC_UART2TX \ + 0x00000002 +#define UDMA_DEF_USBEP2RX_SEC_TMR3A \ + 0x00000004 +#define UDMA_DEF_USBEP2TX_SEC_TMR3B \ + 0x00000008 +#define UDMA_DEF_USBEP3RX_SEC_TMR2A \ + 0x00000010 +#define UDMA_DEF_USBEP3TX_SEC_TMR2B \ + 0x00000020 +#define UDMA_DEF_ETH0RX_SEC_TMR2A \ + 0x00000040 +#define UDMA_DEF_ETH0TX_SEC_TMR2B \ + 0x00000080 +#define UDMA_DEF_UART0RX_SEC_UART1RX \ + 0x00000100 +#define UDMA_DEF_UART0TX_SEC_UART1TX \ + 0x00000200 +#define UDMA_DEF_SSI0RX_SEC_SSI1RX \ + 0x00000400 +#define UDMA_DEF_SSI0TX_SEC_SSI1TX \ + 0x00000800 +#define UDMA_DEF_RESERVED_SEC_UART2RX \ + 0x00001000 +#define UDMA_DEF_RESERVED_SEC_UART2TX \ + 0x00002000 +#define UDMA_DEF_ADC00_SEC_TMR2A \ + 0x00004000 +#define UDMA_DEF_ADC01_SEC_TMR2B \ + 0x00008000 +#define UDMA_DEF_ADC02_SEC_RESERVED \ + 0x00010000 +#define UDMA_DEF_ADC03_SEC_RESERVED \ + 0x00020000 +#define UDMA_DEF_TMR0A_SEC_TMR1A \ + 0x00040000 +#define UDMA_DEF_TMR0B_SEC_TMR1B \ + 0x00080000 +#define UDMA_DEF_TMR1A_SEC_EPI0RX \ + 0x00100000 +#define UDMA_DEF_TMR1B_SEC_EPI0TX \ + 0x00200000 +#define UDMA_DEF_UART1RX_SEC_RESERVED \ + 0x00400000 +#define UDMA_DEF_UART1TX_SEC_RESERVED \ + 0x00800000 +#define UDMA_DEF_SSI1RX_SEC_ADC10 \ + 0x01000000 +#define UDMA_DEF_SSI1TX_SEC_ADC11 \ + 0x02000000 +#define UDMA_DEF_RESERVED_SEC_ADC12 \ + 0x04000000 +#define UDMA_DEF_RESERVED_SEC_ADC13 \ + 0x08000000 +#define UDMA_DEF_I2S0RX_SEC_RESERVED \ + 0x10000000 +#define UDMA_DEF_I2S0TX_SEC_RESERVED \ + 0x20000000 + +extern void uDMAChannelSelectDefault(uint32_t ui32DefPeriphs); +extern void uDMAChannelSelectSecondary(uint32_t ui32SecPeriphs); + +#endif +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_UDMA_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/usb.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/usb.h new file mode 100644 index 0000000000000000000000000000000000000000..1fed815842adf29e0e6b67382f6c7fac397388b0 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/usb.h @@ -0,0 +1,658 @@ +//***************************************************************************** +// +// usb.h - Prototypes for the USB Interface Driver. +// +// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_USB_H__ +#define __DRIVERLIB_USB_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to USBIntEnableControl() and +// USBIntDisableControl() as the ui32Flags parameter, and are returned from +// USBIntStatusControl(). +// +//***************************************************************************** +#define USB_INTCTRL_ALL 0x000003FF // All control interrupt sources +#define USB_INTCTRL_STATUS 0x000000FF // Status Interrupts +#define USB_INTCTRL_VBUS_ERR 0x00000080 // VBUS Error +#define USB_INTCTRL_SESSION 0x00000040 // Session Start Detected +#define USB_INTCTRL_SESSION_END 0x00000040 // Session End Detected +#define USB_INTCTRL_DISCONNECT 0x00000020 // Disconnect Detected +#define USB_INTCTRL_CONNECT 0x00000010 // Device Connect Detected +#define USB_INTCTRL_SOF 0x00000008 // Start of Frame Detected +#define USB_INTCTRL_BABBLE 0x00000004 // Babble signaled +#define USB_INTCTRL_RESET 0x00000004 // Reset signaled +#define USB_INTCTRL_RESUME 0x00000002 // Resume detected +#define USB_INTCTRL_SUSPEND 0x00000001 // Suspend detected +#define USB_INTCTRL_MODE_DETECT 0x00000200 // Mode value valid +#define USB_INTCTRL_POWER_FAULT 0x00000100 // Power Fault detected + +//***************************************************************************** +// +// The following are values that can be passed to USBIntEnableEndpoint() and +// USBIntDisableEndpoint() as the ui32Flags parameter, and are returned from +// USBIntStatusEndpoint(). +// +//***************************************************************************** +#define USB_INTEP_ALL 0xFFFFFFFF // Host IN Interrupts +#define USB_INTEP_HOST_IN 0xFFFE0000 // Host IN Interrupts +#define USB_INTEP_HOST_IN_15 0x80000000 // Endpoint 15 Host IN Interrupt +#define USB_INTEP_HOST_IN_14 0x40000000 // Endpoint 14 Host IN Interrupt +#define USB_INTEP_HOST_IN_13 0x20000000 // Endpoint 13 Host IN Interrupt +#define USB_INTEP_HOST_IN_12 0x10000000 // Endpoint 12 Host IN Interrupt +#define USB_INTEP_HOST_IN_11 0x08000000 // Endpoint 11 Host IN Interrupt +#define USB_INTEP_HOST_IN_10 0x04000000 // Endpoint 10 Host IN Interrupt +#define USB_INTEP_HOST_IN_9 0x02000000 // Endpoint 9 Host IN Interrupt +#define USB_INTEP_HOST_IN_8 0x01000000 // Endpoint 8 Host IN Interrupt +#define USB_INTEP_HOST_IN_7 0x00800000 // Endpoint 7 Host IN Interrupt +#define USB_INTEP_HOST_IN_6 0x00400000 // Endpoint 6 Host IN Interrupt +#define USB_INTEP_HOST_IN_5 0x00200000 // Endpoint 5 Host IN Interrupt +#define USB_INTEP_HOST_IN_4 0x00100000 // Endpoint 4 Host IN Interrupt +#define USB_INTEP_HOST_IN_3 0x00080000 // Endpoint 3 Host IN Interrupt +#define USB_INTEP_HOST_IN_2 0x00040000 // Endpoint 2 Host IN Interrupt +#define USB_INTEP_HOST_IN_1 0x00020000 // Endpoint 1 Host IN Interrupt + +#define USB_INTEP_DEV_OUT 0xFFFE0000 // Device OUT Interrupts +#define USB_INTEP_DEV_OUT_15 0x80000000 // Endpoint 15 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_14 0x40000000 // Endpoint 14 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_13 0x20000000 // Endpoint 13 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_12 0x10000000 // Endpoint 12 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_11 0x08000000 // Endpoint 11 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_10 0x04000000 // Endpoint 10 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_9 0x02000000 // Endpoint 9 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_8 0x01000000 // Endpoint 8 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_7 0x00800000 // Endpoint 7 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_6 0x00400000 // Endpoint 6 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_5 0x00200000 // Endpoint 5 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_4 0x00100000 // Endpoint 4 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_3 0x00080000 // Endpoint 3 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_2 0x00040000 // Endpoint 2 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_1 0x00020000 // Endpoint 1 Device OUT Interrupt + +#define USB_INTEP_HOST_OUT 0x0000FFFE // Host OUT Interrupts +#define USB_INTEP_HOST_OUT_15 0x00008000 // Endpoint 15 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_14 0x00004000 // Endpoint 14 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_13 0x00002000 // Endpoint 13 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_12 0x00001000 // Endpoint 12 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_11 0x00000800 // Endpoint 11 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_10 0x00000400 // Endpoint 10 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_9 0x00000200 // Endpoint 9 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_8 0x00000100 // Endpoint 8 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_7 0x00000080 // Endpoint 7 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_6 0x00000040 // Endpoint 6 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_5 0x00000020 // Endpoint 5 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_4 0x00000010 // Endpoint 4 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_3 0x00000008 // Endpoint 3 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_2 0x00000004 // Endpoint 2 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_1 0x00000002 // Endpoint 1 Host OUT Interrupt + +#define USB_INTEP_DEV_IN 0x0000FFFE // Device IN Interrupts +#define USB_INTEP_DEV_IN_15 0x00008000 // Endpoint 15 Device IN Interrupt +#define USB_INTEP_DEV_IN_14 0x00004000 // Endpoint 14 Device IN Interrupt +#define USB_INTEP_DEV_IN_13 0x00002000 // Endpoint 13 Device IN Interrupt +#define USB_INTEP_DEV_IN_12 0x00001000 // Endpoint 12 Device IN Interrupt +#define USB_INTEP_DEV_IN_11 0x00000800 // Endpoint 11 Device IN Interrupt +#define USB_INTEP_DEV_IN_10 0x00000400 // Endpoint 10 Device IN Interrupt +#define USB_INTEP_DEV_IN_9 0x00000200 // Endpoint 9 Device IN Interrupt +#define USB_INTEP_DEV_IN_8 0x00000100 // Endpoint 8 Device IN Interrupt +#define USB_INTEP_DEV_IN_7 0x00000080 // Endpoint 7 Device IN Interrupt +#define USB_INTEP_DEV_IN_6 0x00000040 // Endpoint 6 Device IN Interrupt +#define USB_INTEP_DEV_IN_5 0x00000020 // Endpoint 5 Device IN Interrupt +#define USB_INTEP_DEV_IN_4 0x00000010 // Endpoint 4 Device IN Interrupt +#define USB_INTEP_DEV_IN_3 0x00000008 // Endpoint 3 Device IN Interrupt +#define USB_INTEP_DEV_IN_2 0x00000004 // Endpoint 2 Device IN Interrupt +#define USB_INTEP_DEV_IN_1 0x00000002 // Endpoint 1 Device IN Interrupt + +#define USB_INTEP_0 0x00000001 // Endpoint 0 Interrupt + +//***************************************************************************** +// +// The following are values that are returned from USBSpeedGet(). +// +//***************************************************************************** +#define USB_UNDEF_SPEED 0x80000000 // Current speed is undefined +#define USB_HIGH_SPEED 0x00000002 // Current speed is High Speed +#define USB_FULL_SPEED 0x00000001 // Current speed is Full Speed +#define USB_LOW_SPEED 0x00000000 // Current speed is Low Speed + +//***************************************************************************** +// +// The following are values that are returned from USBEndpointStatus(). The +// USB_HOST_* values are used when the USB controller is in host mode and the +// USB_DEV_* values are used when the USB controller is in device mode. +// +//***************************************************************************** +#define USB_HOST_IN_STATUS 0x114F0000 // Mask of all host IN interrupts +#define USB_HOST_IN_PID_ERROR 0x10000000 // Stall on this endpoint received +#define USB_HOST_IN_NOT_COMP 0x01000000 // Device failed to respond +#define USB_HOST_IN_STALL 0x00400000 // Stall on this endpoint received +#define USB_HOST_IN_DATA_ERROR 0x00080000 // CRC or bit-stuff error + // (ISOC Mode) +#define USB_HOST_IN_NAK_TO 0x00080000 // NAK received for more than the + // specified timeout period +#define USB_HOST_IN_ERROR 0x00040000 // Failed to communicate with a + // device +#define USB_HOST_IN_FIFO_FULL 0x00020000 // RX FIFO full +#define USB_HOST_IN_PKTRDY 0x00010000 // Data packet ready +#define USB_HOST_OUT_STATUS 0x000000A7 // Mask of all host OUT interrupts +#define USB_HOST_OUT_NAK_TO 0x00000080 // NAK received for more than the + // specified timeout period +#define USB_HOST_OUT_NOT_COMP 0x00000080 // No response from device + // (ISOC mode) +#define USB_HOST_OUT_STALL 0x00000020 // Stall on this endpoint received +#define USB_HOST_OUT_ERROR 0x00000004 // Failed to communicate with a + // device +#define USB_HOST_OUT_FIFO_NE 0x00000002 // TX FIFO is not empty +#define USB_HOST_OUT_PKTPEND 0x00000001 // Transmit still being transmitted +#define USB_HOST_EP0_NAK_TO 0x00000080 // NAK received for more than the + // specified timeout period +#define USB_HOST_EP0_STATUS 0x00000040 // This was a status packet +#define USB_HOST_EP0_ERROR 0x00000010 // Failed to communicate with a + // device +#define USB_HOST_EP0_RX_STALL 0x00000004 // Stall on this endpoint received +#define USB_HOST_EP0_RXPKTRDY 0x00000001 // Receive data packet ready +#define USB_DEV_RX_PID_ERROR 0x01000000 // PID error in isochronous + // transfer +#define USB_DEV_RX_SENT_STALL 0x00400000 // Stall was sent on this endpoint +#define USB_DEV_RX_DATA_ERROR 0x00080000 // CRC error on the data +#define USB_DEV_RX_OVERRUN 0x00040000 // OUT packet was not loaded due to + // a full FIFO +#define USB_DEV_RX_FIFO_FULL 0x00020000 // RX FIFO full +#define USB_DEV_RX_PKT_RDY 0x00010000 // Data packet ready +#define USB_DEV_TX_NOT_COMP 0x00000080 // Large packet split up, more data + // to come +#define USB_DEV_TX_SENT_STALL 0x00000020 // Stall was sent on this endpoint +#define USB_DEV_TX_UNDERRUN 0x00000004 // IN received with no data ready +#define USB_DEV_TX_FIFO_NE 0x00000002 // The TX FIFO is not empty +#define USB_DEV_TX_TXPKTRDY 0x00000001 // Transmit still being transmitted +#define USB_DEV_EP0_SETUP_END 0x00000010 // Control transaction ended before + // Data End seen +#define USB_DEV_EP0_SENT_STALL 0x00000004 // Stall was sent on this endpoint +#define USB_DEV_EP0_IN_PKTPEND 0x00000002 // Transmit data packet pending +#define USB_DEV_EP0_OUT_PKTRDY 0x00000001 // Receive data packet ready + +//***************************************************************************** +// +// The following are values that can be passed to USBHostEndpointConfig() and +// USBDevEndpointConfigSet() as the ui32Flags parameter. +// +//***************************************************************************** +#define USB_EP_AUTO_SET 0x00000001 // Auto set feature enabled +#define USB_EP_AUTO_REQUEST 0x00000002 // Auto request feature enabled +#define USB_EP_AUTO_CLEAR 0x00000004 // Auto clear feature enabled +#define USB_EP_DMA_MODE_0 0x00000008 // Enable DMA access using mode 0 +#define USB_EP_DMA_MODE_1 0x00000010 // Enable DMA access using mode 1 +#define USB_EP_DIS_NYET 0x00000020 // Disable NYET response for + // high-speed Bulk and Interrupt + // endpoints in device mode. +#define USB_EP_MODE_ISOC 0x00000000 // Isochronous endpoint +#define USB_EP_MODE_BULK 0x00000100 // Bulk endpoint +#define USB_EP_MODE_INT 0x00000200 // Interrupt endpoint +#define USB_EP_MODE_CTRL 0x00000300 // Control endpoint +#define USB_EP_MODE_MASK 0x00000300 // Mode Mask +#define USB_EP_SPEED_LOW 0x00000000 // Low Speed +#define USB_EP_SPEED_FULL 0x00001000 // Full Speed +#define USB_EP_SPEED_HIGH 0x00004000 // High Speed +#define USB_EP_HOST_IN 0x00000000 // Host IN endpoint +#define USB_EP_HOST_OUT 0x00002000 // Host OUT endpoint +#define USB_EP_DEV_IN 0x00002000 // Device IN endpoint +#define USB_EP_DEV_OUT 0x00000000 // Device OUT endpoint + +//***************************************************************************** +// +// The following are values that can be passed to USBHostPwrConfig() as the +// ui32Flags parameter. +// +//***************************************************************************** +#define USB_HOST_PWRFLT_LOW 0x00000010 +#define USB_HOST_PWRFLT_HIGH 0x00000030 +#define USB_HOST_PWRFLT_EP_NONE 0x00000000 +#define USB_HOST_PWRFLT_EP_TRI 0x00000140 +#define USB_HOST_PWRFLT_EP_LOW 0x00000240 +#define USB_HOST_PWRFLT_EP_HIGH 0x00000340 +#define USB_HOST_PWREN_MAN_LOW 0x00000000 +#define USB_HOST_PWREN_MAN_HIGH 0x00000001 +#define USB_HOST_PWREN_AUTOLOW 0x00000002 +#define USB_HOST_PWREN_AUTOHIGH 0x00000003 +#define USB_HOST_PWREN_FILTER 0x00010000 + +//***************************************************************************** +// +// The following are the valid values that can be passed to the +// USBHostLPMConfig() function in the ui32Config parameter. +// +//***************************************************************************** +#define USB_HOST_LPM_RMTWAKE 0x00000100 +#define USB_HOST_LPM_L1 0x00000001 + +//***************************************************************************** +// +// The following are the valid values that can be passed to the +// USBDevLPMConfig() function in the ui32Config parameter. +// +//***************************************************************************** +#define USB_DEV_LPM_NAK 0x00000010 +#define USB_DEV_LPM_NONE 0x00000000 +#define USB_DEV_LPM_EN 0x0000000c +#define USB_DEV_LPM_EXTONLY 0x00000004 + +//***************************************************************************** +// +// The following are the valid values that are returned from the +// USBLPMLinkStateGet() function. +// +//***************************************************************************** +#define USB_DEV_LPM_LS_RMTWAKE 0x00000100 +#define USB_DEV_LPM_LS_L1 0x00000001 + +//***************************************************************************** +// +// The following are the valid values that are passed to the USBLPMIntEnable() +// or USBLPMIntDisable() functions or are returned from the USBLPMIntStatus() +// function. +// +//***************************************************************************** +#define USB_INTLPM_ERROR 0x00000020 +#define USB_INTLPM_RESUME 0x00000010 +#define USB_INTLPM_INCOMPLETE 0x00000008 +#define USB_INTLPM_ACK 0x00000004 +#define USB_INTLPM_NYET 0x00000002 +#define USB_INTLPM_STALL 0x00000001 + +//***************************************************************************** +// +// The following are the valid values that are passed to the USBClockEnable() +// functions. +// +//***************************************************************************** +#define USB_CLOCK_INTERNAL 0x00000200 +#define USB_CLOCK_EXTERNAL 0x00000300 + +//***************************************************************************** +// +// The configuration options used with the USBULPIConfig() API. +// +//***************************************************************************** +#define USB_ULPI_EXTVBUS 0x00000001 +#define USB_ULPI_EXTVBUS_IND 0x00000002 + +//***************************************************************************** +// +// The following are special values that can be passed to +// USBHostEndpointConfig() as the ui32NAKPollInterval parameter. +// +//***************************************************************************** +#define MAX_NAK_LIMIT 31 // Maximum NAK interval +#define DISABLE_NAK_LIMIT 0 // No NAK timeouts + +//***************************************************************************** +// +// This value specifies the maximum size of transfers on endpoint 0 as 64 +// bytes. This value is fixed in hardware as the FIFO size for endpoint 0. +// +//***************************************************************************** +#define MAX_PACKET_SIZE_EP0 64 + +//***************************************************************************** +// +// These values are used to indicate which endpoint to access. +// +//***************************************************************************** +#define USB_EP_0 0x00000000 // Endpoint 0 +#define USB_EP_1 0x00000010 // Endpoint 1 +#define USB_EP_2 0x00000020 // Endpoint 2 +#define USB_EP_3 0x00000030 // Endpoint 3 +#define USB_EP_4 0x00000040 // Endpoint 4 +#define USB_EP_5 0x00000050 // Endpoint 5 +#define USB_EP_6 0x00000060 // Endpoint 6 +#define USB_EP_7 0x00000070 // Endpoint 7 +#define NUM_USB_EP 8 // Number of supported endpoints + +//***************************************************************************** +// +// These macros allow conversion between 0-based endpoint indices and the +// USB_EP_x values required when calling various USB APIs. +// +//***************************************************************************** +#define IndexToUSBEP(x) ((x) << 4) +#define USBEPToIndex(x) ((x) >> 4) + +//***************************************************************************** +// +// The following are values that can be passed to USBFIFOConfigSet() as the +// ui32FIFOSize parameter. +// +//***************************************************************************** +#define USB_FIFO_SZ_8 0x00000000 // 8 byte FIFO +#define USB_FIFO_SZ_16 0x00000001 // 16 byte FIFO +#define USB_FIFO_SZ_32 0x00000002 // 32 byte FIFO +#define USB_FIFO_SZ_64 0x00000003 // 64 byte FIFO +#define USB_FIFO_SZ_128 0x00000004 // 128 byte FIFO +#define USB_FIFO_SZ_256 0x00000005 // 256 byte FIFO +#define USB_FIFO_SZ_512 0x00000006 // 512 byte FIFO +#define USB_FIFO_SZ_1024 0x00000007 // 1024 byte FIFO +#define USB_FIFO_SZ_2048 0x00000008 // 2048 byte FIFO + +//***************************************************************************** +// +// This macro allow conversion from a FIFO size label as defined above to +// a number of bytes +// +//***************************************************************************** +#define USBFIFOSizeToBytes(x) (8 << (x)) + +//***************************************************************************** +// +// The following are values that can be passed to USBEndpointDataSend() as the +// ui32TransType parameter. +// +//***************************************************************************** +#define USB_TRANS_OUT 0x00000102 // Normal OUT transaction +#define USB_TRANS_IN 0x00000102 // Normal IN transaction +#define USB_TRANS_IN_LAST 0x0000010a // Final IN transaction (for + // endpoint 0 in device mode) +#define USB_TRANS_SETUP 0x0000110a // Setup transaction (for endpoint + // 0) +#define USB_TRANS_STATUS 0x00000142 // Status transaction (for endpoint + // 0) + +//***************************************************************************** +// +// The following are values are returned by the USBModeGet function. +// +//***************************************************************************** +#define USB_DUAL_MODE_HOST 0x00000001 // Dual mode controller is in Host + // mode. +#define USB_DUAL_MODE_DEVICE 0x00000081 // Dual mode controller is in + // Device mode. +#define USB_DUAL_MODE_NONE 0x00000080 // Dual mode controller mode is not + // set. +#define USB_OTG_MODE_ASIDE_HOST 0x0000001d // OTG controller on the A side of + // the cable. +#define USB_OTG_MODE_ASIDE_NPWR 0x00000001 // OTG controller on the A side of + // the cable. +#define USB_OTG_MODE_ASIDE_SESS 0x00000009 // OTG controller on the A side of + // the cable Session Valid. +#define USB_OTG_MODE_ASIDE_AVAL 0x00000011 // OTG controller on the A side of + // the cable A valid. +#define USB_OTG_MODE_ASIDE_DEV 0x00000019 // OTG controller on the A side of + // the cable. +#define USB_OTG_MODE_BSIDE_HOST 0x0000009d // OTG controller on the B side of + // the cable. +#define USB_OTG_MODE_BSIDE_DEV 0x00000099 // OTG controller on the B side of + // the cable. +#define USB_OTG_MODE_BSIDE_NPWR 0x00000081 // OTG controller on the B side of + // the cable. +#define USB_OTG_MODE_NONE 0x00000080 // OTG controller mode is not set. + +//***************************************************************************** +// +// The values for the USBDMAChannelIntEnable() and USBDMAChannelIntStatus() +// APIs. +// +//***************************************************************************** +#define USB_DMA_INT_CH8 0x00000080 +#define USB_DMA_INT_CH7 0x00000040 +#define USB_DMA_INT_CH6 0x00000020 +#define USB_DMA_INT_CH5 0x00000010 +#define USB_DMA_INT_CH4 0x00000008 +#define USB_DMA_INT_CH3 0x00000004 +#define USB_DMA_INT_CH2 0x00000002 +#define USB_DMA_INT_CH1 0x00000001 + +//***************************************************************************** +// +// The values for the USBDMAChannelStatus() API. +// +//***************************************************************************** +#define USB_DMA_STATUS_ERROR 0x00000100 + +//***************************************************************************** +// +// The valid return values for the USBControllerVersion() API. +// +//***************************************************************************** +#define USB_CONTROLLER_VER_0 0x00000000 // This is for Blizzard class + // devices. +#define USB_CONTROLLER_VER_1 0x00000001 // This is for Snowflake class + // devices. + +//***************************************************************************** +// +// The valid return values for the USBDMAModeSet() and USBDMAModeGet() APIs or +// USBDMAChannelConfig(). +// +//***************************************************************************** +#define USB_DMA_CFG_BURST_NONE 0x00000000 +#define USB_DMA_CFG_BURST_4 0x00000200 +#define USB_DMA_CFG_BURST_8 0x00000400 +#define USB_DMA_CFG_BURST_16 0x00000600 +#define USB_DMA_CFG_INT_EN 0x00000008 +#define USB_DMA_CFG_MODE_0 0x00000000 +#define USB_DMA_CFG_MODE_1 0x00000004 +#define USB_DMA_CFG_DIR_RX 0x00000000 +#define USB_DMA_CFG_DIR_TX 0x00000002 +#define USB_DMA_CFG_EN 0x00000001 + +//***************************************************************************** +// +// The following are values that can be passed to USBModeConfig() as the +// ui3Mode parameter. +// +//***************************************************************************** +#define USB_MODE_HOST_VBUS 0x00000004 +#define USB_MODE_HOST 0x00000002 +#define USB_MODE_DEV_VBUS 0x00000005 +#define USB_MODE_DEV 0x00000003 +#define USB_MODE_OTG 0x00000000 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern uint32_t USBDevAddrGet(uint32_t ui32Base); +extern void USBDevAddrSet(uint32_t ui32Base, uint32_t ui32Address); +extern void USBDevConnect(uint32_t ui32Base); +extern void USBDevDisconnect(uint32_t ui32Base); +extern void USBDevEndpointConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32MaxPacketSize, + uint32_t ui32Flags); +extern void USBDevEndpointConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t *pui32MaxPacketSize, + uint32_t *pui32Flags); +extern void USBDevEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint, + bool bIsLastPacket); +extern void USBDevEndpointStall(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBDevEndpointStallClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBDevEndpointStatusClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern uint32_t USBEndpointDataAvail(uint32_t ui32Base, uint32_t ui32Endpoint); +extern void USBEndpointDMAEnable(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBEndpointDMADisable(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBEndpointDMAConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Config); +extern int32_t USBEndpointDataGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint8_t *pui8Data, uint32_t *pui32Size); +extern int32_t USBEndpointDataPut(uint32_t ui32Base, uint32_t ui32Endpoint, + uint8_t *pui8Data, uint32_t ui32Size); +extern int32_t USBEndpointDataSend(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32TransType); +extern void USBEndpointDataToggleClear(uint32_t ui32Base, + uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBEndpointPacketCountSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Count); +extern uint32_t USBEndpointStatus(uint32_t ui32Base, uint32_t ui32Endpoint); +extern uint32_t USBFIFOAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint); +extern void USBFIFOConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t *pui32FIFOAddress, + uint32_t *pui32FIFOSize, uint32_t ui32Flags); +extern void USBFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32FIFOAddress, uint32_t ui32FIFOSize, + uint32_t ui32Flags); +extern void USBFIFOFlush(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern uint32_t USBFrameNumberGet(uint32_t ui32Base); +extern uint32_t USBHostAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBHostAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Addr, uint32_t ui32Flags); +extern void USBHostEndpointConfig(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32MaxPacketSize, + uint32_t ui32NAKPollInterval, + uint32_t ui32TargetEndpoint, + uint32_t ui32Flags); +extern void USBHostEndpointDataAck(uint32_t ui32Base, + uint32_t ui32Endpoint); +extern void USBHostEndpointDataToggle(uint32_t ui32Base, uint32_t ui32Endpoint, + bool bDataToggle, uint32_t ui32Flags); +extern void USBHostEndpointStatusClear(uint32_t ui32Base, + uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern uint32_t USBHostHubAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBHostHubAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Addr, uint32_t ui32Flags); +extern void USBHostPwrDisable(uint32_t ui32Base); +extern void USBHostPwrEnable(uint32_t ui32Base); +extern void USBHostPwrConfig(uint32_t ui32Base, uint32_t ui32Flags); +extern void USBHostPwrFaultDisable(uint32_t ui32Base); +extern void USBHostPwrFaultEnable(uint32_t ui32Base); +extern void USBHostRequestIN(uint32_t ui32Base, uint32_t ui32Endpoint); +extern void USBHostRequestINClear(uint32_t ui32Base, uint32_t ui32Endpoint); +extern void USBHostRequestStatus(uint32_t ui32Base); +extern void USBHostReset(uint32_t ui32Base, bool bStart); +extern void USBHostResume(uint32_t ui32Base, bool bStart); +extern uint32_t USBHostSpeedGet(uint32_t ui32Base); +extern void USBHostSuspend(uint32_t ui32Base); +extern void USBIntDisableControl(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void USBIntEnableControl(uint32_t ui32Base, uint32_t ui32IntFlags); +extern uint32_t USBIntStatusControl(uint32_t ui32Base); +extern void USBIntDisableEndpoint(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void USBIntEnableEndpoint(uint32_t ui32Base, uint32_t ui32IntFlags); +extern uint32_t USBIntStatusEndpoint(uint32_t ui32Base); +extern void USBIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); +extern void USBIntUnregister(uint32_t ui32Base); +extern void USBOTGSessionRequest(uint32_t ui32Base, bool bStart); +extern uint32_t USBModeGet(uint32_t ui32Base); +extern void USBEndpointDMAChannel(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Channel); +extern uint32_t USBControllerVersion(uint32_t ui32Base); +extern uint32_t USBDMAChannelIntStatus(uint32_t ui32Base); +extern void USBDMAChannelConfigSet(uint32_t ui32Base, uint32_t ui32Channel, + uint32_t ui32Endpoint, uint32_t ui32Config); +extern void USBDMAChannelAddressSet(uint32_t ui32Base, uint32_t ui32Channel, + void *pvAddress); +extern void *USBDMAChannelAddressGet(uint32_t ui32Base, uint32_t ui32Channel); +extern void USBDMAChannelCountSet(uint32_t ui32Base, uint32_t ui32Count, + uint32_t ui32Channel); +extern uint32_t USBDMAChannelCountGet(uint32_t ui32Base, uint32_t ui32Channel); +extern uint32_t USBDMANumChannels(uint32_t ui32Base); +extern void USBDMAChannelAssign(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Channel, uint32_t ui32Flags); +extern void USBDMAChannelIntEnable(uint32_t ui32Base, uint32_t ui32Channel); +extern void USBDMAChannelIntDisable(uint32_t ui32Base, uint32_t ui32Channel); +extern void USBDMAChannelEnable(uint32_t ui32Base, uint32_t ui32Channel); +extern void USBDMAChannelDisable(uint32_t ui32Base, uint32_t ui32Channel); +extern uint32_t USBDMAChannelStatus(uint32_t ui32Base, uint32_t ui32Channel); +extern void USBDMAChannelStatusClear(uint32_t ui32Base, uint32_t ui32Channel, + uint32_t ui32Status); +extern void USBHostEndpointSpeed(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBHostEndpointPing(uint32_t ui32Base, uint32_t ui32Endpoint, + bool bEnable); +extern void USBHostLPMSend(uint32_t ui32Base, uint32_t ui32Address, + uint32_t uiEndpoint); +extern void USBHostLPMConfig(uint32_t ui32Base, uint32_t ui32ResumeTime, + uint32_t ui32Config); +extern bool USBLPMRemoteWakeEnabled(uint32_t ui32Base); +extern void USBHostLPMResume(uint32_t ui32Base); +extern void USBDevLPMRemoteWake(uint32_t ui32Base); +extern void USBDevLPMConfig(uint32_t ui32Base, uint32_t ui32Config); +extern void USBDevLPMEnable(uint32_t ui32Base); +extern void USBDevLPMDisable(uint32_t ui32Base); +extern uint32_t USBLPMLinkStateGet(uint32_t ui32Base); +extern uint32_t USBLPMEndpointGet(uint32_t ui32Base); +extern uint32_t USBLPMIntStatus(uint32_t ui32Base); +extern void USBLPMIntDisable(uint32_t ui32Base, uint32_t ui32Ints); +extern void USBLPMIntEnable(uint32_t ui32Base, uint32_t ui32Ints); +extern void USBHighSpeed(uint32_t ui32Base, bool bEnable); +extern uint32_t USBDevSpeedGet(uint32_t ui32Base); +extern void USBClockEnable(uint32_t ui32Base, uint32_t ui32Div, + uint32_t ui32Flags); +extern void USBClockDisable(uint32_t ui32Base); +extern void USBULPIConfig(uint32_t ui32Base, uint32_t ui32Config); +extern void USBULPIEnable(uint32_t ui32Base); +extern void USBULPIDisable(uint32_t ui32Base); +extern uint8_t USBULPIRegRead(uint32_t ui32Base, uint8_t ui8Reg); +extern void USBULPIRegWrite(uint32_t ui32Base, uint8_t ui8Reg, + uint8_t ui8Data); +extern void USBHostMode(uint32_t ui32Base); +extern void USBDevMode(uint32_t ui32Base); +extern void USBOTGMode(uint32_t ui32Base); +extern void USBModeConfig(uint32_t ui32Base, uint32_t ui32Mode); +extern void USBPHYPowerOff(uint32_t ui32Base); +extern void USBPHYPowerOn(uint32_t ui32Base); +extern uint32_t USBNumEndpointsGet(uint32_t ui32Base); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_USB_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/watchdog.h b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/watchdog.h new file mode 100644 index 0000000000000000000000000000000000000000..a14a4fb04cc59487cd29c0e44d0458bf69c03c8f --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/watchdog.h @@ -0,0 +1,95 @@ +//***************************************************************************** +// +// watchdog.h - Prototypes for the Watchdog Timer API +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_WATCHDOG_H__ +#define __DRIVERLIB_WATCHDOG_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The type of interrupt that can be generated by the watchdog. +// +//***************************************************************************** +#define WATCHDOG_INT_TYPE_INT 0x00000000 +#define WATCHDOG_INT_TYPE_NMI 0x00000004 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern bool WatchdogRunning(uint32_t ui32Base); +extern void WatchdogEnable(uint32_t ui32Base); +extern void WatchdogResetEnable(uint32_t ui32Base); +extern void WatchdogResetDisable(uint32_t ui32Base); +extern void WatchdogLock(uint32_t ui32Base); +extern void WatchdogUnlock(uint32_t ui32Base); +extern bool WatchdogLockState(uint32_t ui32Base); +extern void WatchdogReloadSet(uint32_t ui32Base, uint32_t ui32LoadVal); +extern uint32_t WatchdogReloadGet(uint32_t ui32Base); +extern uint32_t WatchdogValueGet(uint32_t ui32Base); +extern void WatchdogIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); +extern void WatchdogIntUnregister(uint32_t ui32Base); +extern void WatchdogIntEnable(uint32_t ui32Base); +extern uint32_t WatchdogIntStatus(uint32_t ui32Base, bool bMasked); +extern void WatchdogIntClear(uint32_t ui32Base); +extern void WatchdogIntTypeSet(uint32_t ui32Base, uint32_t ui32Type); +extern void WatchdogStallEnable(uint32_t ui32Base); +extern void WatchdogStallDisable(uint32_t ui32Base); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_WATCHDOG_H__ diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/adc.c b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/adc.c new file mode 100644 index 0000000000000000000000000000000000000000..81e7dc05fc7a7f242629087da27896b6fa97ee37 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/adc.c @@ -0,0 +1,2073 @@ +//***************************************************************************** +// +// adc.c - Driver for the ADC. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup adc_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_adc.h" +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_sysctl.h" +#include "driverlib/adc.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" + +//***************************************************************************** +// +// These defines are used by the ADC driver to simplify access to the ADC +// sequencer's registers. +// +//***************************************************************************** +#define ADC_SEQ (ADC_O_SSMUX0) +#define ADC_SEQ_STEP (ADC_O_SSMUX1 - ADC_O_SSMUX0) +#define ADC_SSMUX (ADC_O_SSMUX0 - ADC_O_SSMUX0) +#define ADC_SSEMUX (ADC_O_SSEMUX0 - ADC_O_SSMUX0) +#define ADC_SSCTL (ADC_O_SSCTL0 - ADC_O_SSMUX0) +#define ADC_SSFIFO (ADC_O_SSFIFO0 - ADC_O_SSMUX0) +#define ADC_SSFSTAT (ADC_O_SSFSTAT0 - ADC_O_SSMUX0) +#define ADC_SSOP (ADC_O_SSOP0 - ADC_O_SSMUX0) +#define ADC_SSDC (ADC_O_SSDC0 - ADC_O_SSMUX0) +#define ADC_SSTSH (ADC_O_SSTSH0 - ADC_O_SSMUX0) + +//***************************************************************************** +// +// The currently configured software oversampling factor for each of the ADC +// sequencers. +// +//***************************************************************************** +static uint8_t g_pui8OversampleFactor[2][3]; + +//***************************************************************************** +// +//! Returns the interrupt number for a given ADC base address and sequence +//! number. +//! +//! \param ui32Base is the base address of the ADC module. +//! \param ui32SequenceNum is the sample sequence number. +//! +//! This function returns the interrupt number for the ADC module and sequence +//! number provided in the \e ui32Base and \e ui32SequenceNum parameters. +//! +//! \return Returns the ADC sequence interrupt number or 0 if the interrupt +//! does not exist. +// +//***************************************************************************** +static uint_fast8_t +_ADCIntNumberGet(uint32_t ui32Base, uint32_t ui32SequenceNum) +{ + uint_fast8_t ui8Int; + + // + // Determine the interrupt to register based on the sequence number. + // + if(CLASS_IS_TM4C123) + { + ui8Int = ((ui32Base == ADC0_BASE) ? + (INT_ADC0SS0_TM4C123 + ui32SequenceNum) : + (INT_ADC1SS0_TM4C123 + ui32SequenceNum)); + } + else if(CLASS_IS_TM4C129) + { + ui8Int = ((ui32Base == ADC0_BASE) ? + (INT_ADC0SS0_TM4C129 + ui32SequenceNum) : + (INT_ADC1SS0_TM4C129 + ui32SequenceNum)); + } + else + { + ui8Int = 0; + } + + return(ui8Int); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for an ADC interrupt. +//! +//! \param ui32Base is the base address of the ADC module. +//! \param ui32SequenceNum is the sample sequence number. +//! \param pfnHandler is a pointer to the function to be called when the +//! ADC sample sequence interrupt occurs. +//! +//! This function sets the handler to be called when a sample sequence +//! interrupt occurs. This function enables the global interrupt in the +//! interrupt controller; the sequence interrupt must be enabled with +//! ADCIntEnable(). It is the interrupt handler's responsibility to clear the +//! interrupt source via ADCIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +ADCIntRegister(uint32_t ui32Base, uint32_t ui32SequenceNum, + void (*pfnHandler)(void)) +{ + uint_fast8_t ui8Int; + + // + // Check the arguments. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + ASSERT(ui32SequenceNum < 4); + + // + // Determine the interrupt to register based on the sequence number. + // + ui8Int = _ADCIntNumberGet(ui32Base, ui32SequenceNum); + ASSERT(ui8Int != 0); + + // + // Register the interrupt handler. + // + IntRegister(ui8Int, pfnHandler); + + // + // Enable the timer interrupt. + // + IntEnable(ui8Int); +} + +//***************************************************************************** +// +//! Unregisters the interrupt handler for an ADC interrupt. +//! +//! \param ui32Base is the base address of the ADC module. +//! \param ui32SequenceNum is the sample sequence number. +//! +//! This function unregisters the interrupt handler. This function disables +//! the global interrupt in the interrupt controller; the sequence interrupt +//! must be disabled via ADCIntDisable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +ADCIntUnregister(uint32_t ui32Base, uint32_t ui32SequenceNum) +{ + uint_fast8_t ui8Int; + + // + // Check the arguments. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + ASSERT(ui32SequenceNum < 4); + + // + // Determine the interrupt to unregister based on the sequence number. + // + ui8Int = _ADCIntNumberGet(ui32Base, ui32SequenceNum); + ASSERT(ui8Int != 0); + + // + // Disable the interrupt. + // + IntDisable(ui8Int); + + // + // Unregister the interrupt handler. + // + IntUnregister(ui8Int); +} + +//***************************************************************************** +// +//! Disables a sample sequence interrupt. +//! +//! \param ui32Base is the base address of the ADC module. +//! \param ui32SequenceNum is the sample sequence number. +//! +//! This function disables the requested sample sequence interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +ADCIntDisable(uint32_t ui32Base, uint32_t ui32SequenceNum) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + ASSERT(ui32SequenceNum < 4); + + // + // Disable this sample sequence interrupt. + // + HWREG(ui32Base + ADC_O_IM) &= ~(1 << ui32SequenceNum); +} + +//***************************************************************************** +// +//! Enables a sample sequence interrupt. +//! +//! \param ui32Base is the base address of the ADC module. +//! \param ui32SequenceNum is the sample sequence number. +//! +//! This function enables the requested sample sequence interrupt. Any +//! outstanding interrupts are cleared before enabling the sample sequence +//! interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +ADCIntEnable(uint32_t ui32Base, uint32_t ui32SequenceNum) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + ASSERT(ui32SequenceNum < 4); + + // + // Clear any outstanding interrupts on this sample sequence. + // + HWREG(ui32Base + ADC_O_ISC) = 1 << ui32SequenceNum; + + // + // Enable this sample sequence interrupt. + // + HWREG(ui32Base + ADC_O_IM) |= 1 << ui32SequenceNum; +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ui32Base is the base address of the ADC module. +//! \param ui32SequenceNum is the sample sequence number. +//! \param bMasked is false if the raw interrupt status is required and true if +//! the masked interrupt status is required. +//! +//! This function returns the interrupt status for the specified sample +//! sequence. Either the raw interrupt status or the status of interrupts that +//! are allowed to reflect to the processor can be returned. +//! +//! \return The current raw or masked interrupt status. +// +//***************************************************************************** +uint32_t +ADCIntStatus(uint32_t ui32Base, uint32_t ui32SequenceNum, bool bMasked) +{ + uint32_t ui32Temp; + + // + // Check the arguments. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + ASSERT(ui32SequenceNum < 4); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + ui32Temp = HWREG(ui32Base + ADC_O_ISC) & (0x10001 << ui32SequenceNum); + } + else + { + ui32Temp = (HWREG(ui32Base + ADC_O_RIS) & + (0x10000 | (1 << ui32SequenceNum))); + + // + // If the digital comparator status bit is set, reflect it to the + // appropriate sequence bit. + // + if(ui32Temp & 0x10000) + { + ui32Temp |= 0xF0000; + ui32Temp &= ~(0x10000 << ui32SequenceNum); + } + } + + // + // Return the interrupt status + // + return(ui32Temp); +} + +//***************************************************************************** +// +//! Clears sample sequence interrupt source. +//! +//! \param ui32Base is the base address of the ADC module. +//! \param ui32SequenceNum is the sample sequence number. +//! +//! The specified sample sequence interrupt is cleared, so that it no longer +//! asserts. This function must be called in the interrupt handler to keep +//! the interrupt from being triggered again immediately upon exit. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +ADCIntClear(uint32_t ui32Base, uint32_t ui32SequenceNum) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + ASSERT(ui32SequenceNum < 4); + + // + // Clear the interrupt. + // + HWREG(ui32Base + ADC_O_ISC) = 1 << ui32SequenceNum; +} + +//***************************************************************************** +// +//! Enables a sample sequence. +//! +//! \param ui32Base is the base address of the ADC module. +//! \param ui32SequenceNum is the sample sequence number. +//! +//! Allows the specified sample sequence to be captured when its trigger is +//! detected. A sample sequence must be configured before it is enabled. +//! +//! \return None. +// +//***************************************************************************** +void +ADCSequenceEnable(uint32_t ui32Base, uint32_t ui32SequenceNum) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + ASSERT(ui32SequenceNum < 4); + + // + // Enable the specified sequence. + // + HWREG(ui32Base + ADC_O_ACTSS) |= 1 << ui32SequenceNum; +} + +//***************************************************************************** +// +//! Disables a sample sequence. +//! +//! \param ui32Base is the base address of the ADC module. +//! \param ui32SequenceNum is the sample sequence number. +//! +//! Prevents the specified sample sequence from being captured when its trigger +//! is detected. A sample sequence must be disabled before it is configured. +//! +//! \return None. +// +//***************************************************************************** +void +ADCSequenceDisable(uint32_t ui32Base, uint32_t ui32SequenceNum) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + ASSERT(ui32SequenceNum < 4); + + // + // Disable the specified sequences. + // + HWREG(ui32Base + ADC_O_ACTSS) &= ~(1 << ui32SequenceNum); +} + +//***************************************************************************** +// +//! Configures the trigger source and priority of a sample sequence. +//! +//! \param ui32Base is the base address of the ADC module. +//! \param ui32SequenceNum is the sample sequence number. +//! \param ui32Trigger is the trigger source that initiates the sample +//! sequence; must be one of the \b ADC_TRIGGER_* values. +//! \param ui32Priority is the relative priority of the sample sequence with +//! respect to the other sample sequences. +//! +//! This function configures the initiation criteria for a sample sequence. +//! Valid sample sequencers range from zero to three; sequencer zero captures +//! up to eight samples, sequencers one and two capture up to four samples, +//! and sequencer three captures a single sample. The trigger condition and +//! priority (with respect to other sample sequencer execution) are set. +//! +//! The \e ui32Trigger parameter can take on the following values: +//! +//! - \b ADC_TRIGGER_PROCESSOR - A trigger generated by the processor, via the +//! ADCProcessorTrigger() function. +//! - \b ADC_TRIGGER_COMP0 - A trigger generated by the first analog +//! comparator; configured with ComparatorConfigure(). +//! - \b ADC_TRIGGER_COMP1 - A trigger generated by the second analog +//! comparator; configured with ComparatorConfigure(). +//! - \b ADC_TRIGGER_COMP2 - A trigger generated by the third analog +//! comparator; configured with ComparatorConfigure(). +//! - \b ADC_TRIGGER_EXTERNAL - A trigger generated by an input from the Port +//! B4 pin. Note that some microcontrollers can +//! select from any GPIO using the +//! GPIOADCTriggerEnable() function. +//! - \b ADC_TRIGGER_TIMER - A trigger generated by a timer; configured with +//! TimerControlTrigger(). +//! - \b ADC_TRIGGER_PWM0 - A trigger generated by the first PWM generator; +//! configured with PWMGenIntTrigEnable(). +//! - \b ADC_TRIGGER_PWM1 - A trigger generated by the second PWM generator; +//! configured with PWMGenIntTrigEnable(). +//! - \b ADC_TRIGGER_PWM2 - A trigger generated by the third PWM generator; +//! configured with PWMGenIntTrigEnable(). +//! - \b ADC_TRIGGER_PWM3 - A trigger generated by the fourth PWM generator; +//! configured with PWMGenIntTrigEnable(). +//! - \b ADC_TRIGGER_ALWAYS - A trigger that is always asserted, causing the +//! sample sequence to capture repeatedly (so long as +//! there is not a higher priority source active). +//! +//! When \b ADC_TRIGGER_PWM0, \b ADC_TRIGGER_PWM1, \b ADC_TRIGGER_PWM2 or +//! \b ADC_TRIGGER_PWM3 is specified, one of the following should be ORed into +//! \e ui32Trigger to select the PWM module from which the triggers will be +//! routed for this sequence: +//! +//! - \b ADC_TRIGGER_PWM_MOD0 - Selects PWM module 0 as the source of the +//! PWM0 to PWM3 triggers for this sequence. +//! - \b ADC_TRIGGER_PWM_MOD1 - Selects PWM module 1 as the source of the +//! PWM0 to PWM3 triggers for this sequence. +//! +//! Note that not all trigger sources are available on all Tiva family +//! members; consult the data sheet for the device in question to determine the +//! availability of triggers. +//! +//! The \e ui32Priority parameter is a value between 0 and 3, where 0 +//! represents the highest priority and 3 the lowest. Note that when +//! programming the priority among a set of sample sequences, each must have +//! unique priority; it is up to the caller to guarantee the uniqueness of the +//! priorities. +//! +//! \return None. +// +//***************************************************************************** +void +ADCSequenceConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum, + uint32_t ui32Trigger, uint32_t ui32Priority) +{ + uint32_t ui32Gen; + + // + // Check the arugments. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + ASSERT(ui32SequenceNum < 4); + ASSERT(((ui32Trigger & 0xF) == ADC_TRIGGER_PROCESSOR) || + ((ui32Trigger & 0xF) == ADC_TRIGGER_COMP0) || + ((ui32Trigger & 0xF) == ADC_TRIGGER_COMP1) || + ((ui32Trigger & 0xF) == ADC_TRIGGER_COMP2) || + ((ui32Trigger & 0xF) == ADC_TRIGGER_EXTERNAL) || + ((ui32Trigger & 0xF) == ADC_TRIGGER_TIMER) || + ((ui32Trigger & 0xF) == ADC_TRIGGER_PWM0) || + ((ui32Trigger & 0xF) == ADC_TRIGGER_PWM1) || + ((ui32Trigger & 0xF) == ADC_TRIGGER_PWM2) || + ((ui32Trigger & 0xF) == ADC_TRIGGER_PWM3) || + ((ui32Trigger & 0xF) == ADC_TRIGGER_ALWAYS) || + ((ui32Trigger & 0x30) == ADC_TRIGGER_PWM_MOD0) || + ((ui32Trigger & 0x30) == ADC_TRIGGER_PWM_MOD1)); + ASSERT(ui32Priority < 4); + + // + // Compute the shift for the bits that control this sample sequence. + // + ui32SequenceNum *= 4; + + // + // Set the trigger event for this sample sequence. + // + HWREG(ui32Base + ADC_O_EMUX) = ((HWREG(ui32Base + ADC_O_EMUX) & + ~(0xf << ui32SequenceNum)) | + ((ui32Trigger & 0xf) << ui32SequenceNum)); + + // + // Set the priority for this sample sequence. + // + HWREG(ui32Base + ADC_O_SSPRI) = ((HWREG(ui32Base + ADC_O_SSPRI) & + ~(0xf << ui32SequenceNum)) | + ((ui32Priority & 0x3) << + ui32SequenceNum)); + + // + // Set the source PWM module for this sequence's PWM triggers. + // + ui32Gen = ui32Trigger & 0x0f; + if(ui32Gen >= ADC_TRIGGER_PWM0 && ui32Gen <= ADC_TRIGGER_PWM3) + { + // + // Set the shift for the module and generator + // + ui32Gen = (ui32Gen - ADC_TRIGGER_PWM0) * 8; + + HWREG(ui32Base + ADC_O_TSSEL) = ((HWREG(ui32Base + ADC_O_TSSEL) & + ~(0x30 << ui32Gen)) | + ((ui32Trigger & 0x30) << ui32Gen)); + } +} + +//***************************************************************************** +// +//! Configure a step of the sample sequencer. +//! +//! \param ui32Base is the base address of the ADC module. +//! \param ui32SequenceNum is the sample sequence number. +//! \param ui32Step is the step to be configured. +//! \param ui32Config is the configuration of this step; must be a logical OR +//! of \b ADC_CTL_TS, \b ADC_CTL_IE, \b ADC_CTL_END, \b ADC_CTL_D, one of the +//! input channel selects (\b ADC_CTL_CH0 through \b ADC_CTL_CH23), and one of +//! the digital comparator selects (\b ADC_CTL_CMP0 through \b ADC_CTL_CMP7). +//! +//! This function configures the ADC for one step of a sample sequence. The +//! ADC can be configured for single-ended or differential operation (the +//! \b ADC_CTL_D bit selects differential operation when set), the channel to +//! be sampled can be chosen (the \b ADC_CTL_CH0 through \b ADC_CTL_CH23 +//! values), and the internal temperature sensor can be selected (the +//! \b ADC_CTL_TS bit). Additionally, this step can be defined as the last in +//! the sequence (the \b ADC_CTL_END bit) and it can be configured to cause an +//! interrupt when the step is complete (the \b ADC_CTL_IE bit). If the +//! digital comparators are present on the device, this step may also be +//! configured to send the ADC sample to the selected comparator using +//! \b ADC_CTL_CMP0 through \b ADC_CTL_CMP7. The configuration is used by the +//! ADC at the appropriate time when the trigger for this sequence occurs. +//! +//! \note If the Digital Comparator is present and enabled using the +//! \b ADC_CTL_CMP0 through \b ADC_CTL_CMP7 selects, the ADC sample is NOT +//! written into the ADC sequence data FIFO. +//! +//! The \e ui32Step parameter determines the order in which the samples are +//! captured by the ADC when the trigger occurs. It can range from zero to +//! seven for the first sample sequencer, from zero to three for the second and +//! third sample sequencer, and can only be zero for the fourth sample +//! sequencer. +//! +//! Differential mode only works with adjacent channel pairs (for example, 0 +//! and 1). The channel select must be the number of the channel pair to +//! sample (for example, \b ADC_CTL_CH0 for 0 and 1, or \b ADC_CTL_CH1 for 2 +//! and 3) or undefined results are returned by the ADC. Additionally, if +//! differential mode is selected when the temperature sensor is being sampled, +//! undefined results are returned by the ADC. +//! +//! It is the responsibility of the caller to ensure that a valid configuration +//! is specified; this function does not check the validity of the specified +//! configuration. +//! +//! \return None. +// +//***************************************************************************** +void +ADCSequenceStepConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum, + uint32_t ui32Step, uint32_t ui32Config) +{ + uint32_t ui32Temp; + + // + // Check the arguments. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + ASSERT(ui32SequenceNum < 4); + ASSERT(((ui32SequenceNum == 0) && (ui32Step < 8)) || + ((ui32SequenceNum == 1) && (ui32Step < 4)) || + ((ui32SequenceNum == 2) && (ui32Step < 4)) || + ((ui32SequenceNum == 3) && (ui32Step < 1))); + + // + // Get the offset of the sequence to be configured. + // + ui32Base += ADC_SEQ + (ADC_SEQ_STEP * ui32SequenceNum); + + // + // Compute the shift for the bits that control this step. + // + ui32Step *= 4; + + // + // Set the analog mux value for this step. + // + HWREG(ui32Base + ADC_SSMUX) = ((HWREG(ui32Base + ADC_SSMUX) & + ~(0x0000000f << ui32Step)) | + ((ui32Config & 0x0f) << ui32Step)); + + // + // Set the upper bits of the analog mux value for this step. + // + HWREG(ui32Base + ADC_SSEMUX) = ((HWREG(ui32Base + ADC_SSEMUX) & + ~(0x0000000f << ui32Step)) | + (((ui32Config & 0xf00) >> 8) << ui32Step)); + + // + // Set the control value for this step. + // + HWREG(ui32Base + ADC_SSCTL) = ((HWREG(ui32Base + ADC_SSCTL) & + ~(0x0000000f << ui32Step)) | + (((ui32Config & 0xf0) >> 4) << ui32Step)); + + // + // Set the sample and hold time for this step. This is not available on + // all devices, however on devices that do not support this feature these + // reserved bits are ignored on write access. + // + HWREG(ui32Base + ADC_SSTSH) = ((HWREG(ui32Base + ADC_SSTSH) & + ~(0x0000000f << ui32Step)) | + (((ui32Config & 0xf00000) >> 20) << ui32Step)); + + // + // Enable digital comparator if specified in the ui32Config bit-fields. + // + if(ui32Config & 0x000F0000) + { + // + // Program the comparator for the specified step. + // + ui32Temp = HWREG(ui32Base + ADC_SSDC); + ui32Temp &= ~(0xF << ui32Step); + ui32Temp |= (((ui32Config & 0x00070000) >> 16) << ui32Step); + HWREG(ui32Base + ADC_SSDC) = ui32Temp; + + // + // Enable the comparator. + // + HWREG(ui32Base + ADC_SSOP) |= (1 << ui32Step); + } + + // + // Disable digital comparator if not specified. + // + else + { + HWREG(ui32Base + ADC_SSOP) &= ~(1 << ui32Step); + } +} + +//***************************************************************************** +// +//! Determines if a sample sequence overflow occurred. +//! +//! \param ui32Base is the base address of the ADC module. +//! \param ui32SequenceNum is the sample sequence number. +//! +//! This function determines if a sample sequence overflow has occurred. +//! Overflow happens if the captured samples are not read from the FIFO before +//! the next trigger occurs. +//! +//! \return Returns zero if there was not an overflow, and non-zero if there +//! was. +// +//***************************************************************************** +int32_t +ADCSequenceOverflow(uint32_t ui32Base, uint32_t ui32SequenceNum) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + ASSERT(ui32SequenceNum < 4); + + // + // Determine if there was an overflow on this sequence. + // + return(HWREG(ui32Base + ADC_O_OSTAT) & (1 << ui32SequenceNum)); +} + +//***************************************************************************** +// +//! Clears the overflow condition on a sample sequence. +//! +//! \param ui32Base is the base address of the ADC module. +//! \param ui32SequenceNum is the sample sequence number. +//! +//! This function clears an overflow condition on one of the sample sequences. +//! The overflow condition must be cleared in order to detect a subsequent +//! overflow condition (it otherwise causes no harm). +//! +//! \return None. +// +//***************************************************************************** +void +ADCSequenceOverflowClear(uint32_t ui32Base, uint32_t ui32SequenceNum) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + ASSERT(ui32SequenceNum < 4); + + // + // Clear the overflow condition for this sequence. + // + HWREG(ui32Base + ADC_O_OSTAT) = 1 << ui32SequenceNum; +} + +//***************************************************************************** +// +//! Determines if a sample sequence underflow occurred. +//! +//! \param ui32Base is the base address of the ADC module. +//! \param ui32SequenceNum is the sample sequence number. +//! +//! This function determines if a sample sequence underflow has occurred. +//! Underflow happens if too many samples are read from the FIFO. +//! +//! \return Returns zero if there was not an underflow, and non-zero if there +//! was. +// +//***************************************************************************** +int32_t +ADCSequenceUnderflow(uint32_t ui32Base, uint32_t ui32SequenceNum) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + ASSERT(ui32SequenceNum < 4); + + // + // Determine if there was an underflow on this sequence. + // + return(HWREG(ui32Base + ADC_O_USTAT) & (1 << ui32SequenceNum)); +} + +//***************************************************************************** +// +//! Clears the underflow condition on a sample sequence. +//! +//! \param ui32Base is the base address of the ADC module. +//! \param ui32SequenceNum is the sample sequence number. +//! +//! This function clears an underflow condition on one of the sample +//! sequencers. The underflow condition must be cleared in order to detect a +//! subsequent underflow condition (it otherwise causes no harm). +//! +//! \return None. +// +//***************************************************************************** +void +ADCSequenceUnderflowClear(uint32_t ui32Base, uint32_t ui32SequenceNum) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + ASSERT(ui32SequenceNum < 4); + + // + // Clear the underflow condition for this sequence. + // + HWREG(ui32Base + ADC_O_USTAT) = 1 << ui32SequenceNum; +} + +//***************************************************************************** +// +//! Gets the captured data for a sample sequence. +//! +//! \param ui32Base is the base address of the ADC module. +//! \param ui32SequenceNum is the sample sequence number. +//! \param pui32Buffer is the address where the data is stored. +//! +//! This function copies data from the specified sample sequencer output FIFO +//! to a memory resident buffer. The number of samples available in the +//! hardware FIFO are copied into the buffer, which is assumed to be large +//! enough to hold that many samples. This function only returns the samples +//! that are presently available, which may not be the entire sample sequence +//! if it is in the process of being executed. +//! +//! \return Returns the number of samples copied to the buffer. +// +//***************************************************************************** +int32_t +ADCSequenceDataGet(uint32_t ui32Base, uint32_t ui32SequenceNum, + uint32_t *pui32Buffer) +{ + uint32_t ui32Count; + + // + // Check the arguments. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + ASSERT(ui32SequenceNum < 4); + + // + // Get the offset of the sequence to be read. + // + ui32Base += ADC_SEQ + (ADC_SEQ_STEP * ui32SequenceNum); + + // + // Read samples from the FIFO until it is empty. + // + ui32Count = 0; + while(!(HWREG(ui32Base + ADC_SSFSTAT) & ADC_SSFSTAT0_EMPTY) && + (ui32Count < 8)) + { + // + // Read the FIFO and copy it to the destination. + // + *pui32Buffer++ = HWREG(ui32Base + ADC_SSFIFO); + + // + // Increment the count of samples read. + // + ui32Count++; + } + + // + // Return the number of samples read. + // + return(ui32Count); +} + +//***************************************************************************** +// +//! Causes a processor trigger for a sample sequence. +//! +//! \param ui32Base is the base address of the ADC module. +//! \param ui32SequenceNum is the sample sequence number, with +//! \b ADC_TRIGGER_WAIT or \b ADC_TRIGGER_SIGNAL optionally ORed into it. +//! +//! This function triggers a processor-initiated sample sequence if the sample +//! sequence trigger is configured to \b ADC_TRIGGER_PROCESSOR. If +//! \b ADC_TRIGGER_WAIT is ORed into the sequence number, the +//! processor-initiated trigger is delayed until a later processor-initiated +//! trigger to a different ADC module that specifies \b ADC_TRIGGER_SIGNAL, +//! allowing multiple ADCs to start from a processor-initiated trigger in a +//! synchronous manner. +//! +//! \return None. +// +//***************************************************************************** +void +ADCProcessorTrigger(uint32_t ui32Base, uint32_t ui32SequenceNum) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + ASSERT(ui32SequenceNum < 4); + + // + // Generate a processor trigger for this sample sequence. + // + HWREG(ui32Base + ADC_O_PSSI) |= ((ui32SequenceNum & 0xffff0000) | + (1 << (ui32SequenceNum & 0xf))); +} + +//***************************************************************************** +// +//! Configures the software oversampling factor of the ADC. +//! +//! \param ui32Base is the base address of the ADC module. +//! \param ui32SequenceNum is the sample sequence number. +//! \param ui32Factor is the number of samples to be averaged. +//! +//! This function configures the software oversampling for the ADC, which can +//! be used to provide better resolution on the sampled data. Oversampling is +//! accomplished by averaging multiple samples from the same analog input. +//! Three different oversampling rates are supported; 2x, 4x, and 8x. +//! +//! Oversampling is only supported on the sample sequencers that are more than +//! one sample in depth (that is, the fourth sample sequencer is not +//! supported). Oversampling by 2x (for example) divides the depth of the +//! sample sequencer by two; so 2x oversampling on the first sample sequencer +//! can only provide four samples per trigger. This also means that 8x +//! oversampling is only available on the first sample sequencer. +//! +//! \return None. +// +//***************************************************************************** +void +ADCSoftwareOversampleConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum, + uint32_t ui32Factor) +{ + uint32_t ui32Value; + uint32_t ui32ADCInst; + + // + // Check the arguments. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + ASSERT(ui32SequenceNum < 3); + ASSERT(((ui32Factor == 2) || (ui32Factor == 4) || (ui32Factor == 8)) && + ((ui32SequenceNum == 0) || (ui32Factor != 8))); + + // + // Convert the oversampling factor to a shift factor. + // + for(ui32Value = 0, ui32Factor >>= 1; ui32Factor; + ui32Value++, ui32Factor >>= 1) + { + } + + // + // Evaluate the ADC Instance. + // + if(ui32Base == ADC0_BASE) + { + ui32ADCInst = 0; + } + else + { + ui32ADCInst = 1; + } + + // + // Save the shift factor. + // + g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum] = ui32Value; +} + +//***************************************************************************** +// +//! Configures a step of the software oversampled sequencer. +//! +//! \param ui32Base is the base address of the ADC module. +//! \param ui32SequenceNum is the sample sequence number. +//! \param ui32Step is the step to be configured. +//! \param ui32Config is the configuration of this step. +//! +//! This function configures a step of the sample sequencer when using the +//! software oversampling feature. The number of steps available depends on +//! the oversampling factor set by ADCSoftwareOversampleConfigure(). The value +//! of \e ui32Config is the same as defined for ADCSequenceStepConfigure(). +//! +//! \return None. +// +//***************************************************************************** +void +ADCSoftwareOversampleStepConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum, + uint32_t ui32Step, uint32_t ui32Config) +{ + uint32_t ui32ADCInst; + + // + // Evaluate the ADC Instance. + // + if(ui32Base == ADC0_BASE) + { + ui32ADCInst = 0; + } + else + { + ui32ADCInst = 1; + } + + // + // Check the arguments. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + ASSERT(ui32SequenceNum < 3); + ASSERT(((ui32SequenceNum == 0) && + (ui32Step < + (8 >> g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]))) || + (ui32Step < + (4 >> g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]))); + + // + // Get the offset of the sequence to be configured. + // + ui32Base += ADC_SEQ + (ADC_SEQ_STEP * ui32SequenceNum); + + // + // Compute the shift for the bits that control this step. + // + ui32Step *= 4 << g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]; + + // + // Loop through the hardware steps that make up this step of the software + // oversampled sequence. + // + for(ui32SequenceNum = + (1 << g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]); + ui32SequenceNum; ui32SequenceNum--) + { + // + // Set the analog mux value for this step. + // + HWREG(ui32Base + ADC_SSMUX) = ((HWREG(ui32Base + ADC_SSMUX) & + ~(0x0000000f << ui32Step)) | + ((ui32Config & 0x0f) << ui32Step)); + + // + // Set the upper bits of the analog mux value for this step. + // + HWREG(ui32Base + ADC_SSEMUX) = ((HWREG(ui32Base + ADC_SSEMUX) & + ~(0x0000000f << ui32Step)) | + (((ui32Config & 0xf00) >> 8) << + ui32Step)); + + // + // Set the control value for this step. + // + HWREG(ui32Base + ADC_SSCTL) = ((HWREG(ui32Base + ADC_SSCTL) & + ~(0x0000000f << ui32Step)) | + (((ui32Config & 0xf0) >> 4) << + ui32Step)); + if(ui32SequenceNum != 1) + { + HWREG(ui32Base + ADC_SSCTL) &= ~((ADC_SSCTL0_IE0 | + ADC_SSCTL0_END0) << ui32Step); + } + + // + // Go to the next hardware step. + // + ui32Step += 4; + } +} + +//***************************************************************************** +// +//! Gets the captured data for a sample sequence using software oversampling. +//! +//! \param ui32Base is the base address of the ADC module. +//! \param ui32SequenceNum is the sample sequence number. +//! \param pui32Buffer is the address where the data is stored. +//! \param ui32Count is the number of samples to be read. +//! +//! This function copies data from the specified sample sequence output FIFO to +//! a memory resident buffer with software oversampling applied. The requested +//! number of samples are copied into the data buffer; if there are not enough +//! samples in the hardware FIFO to satisfy this many oversampled data items, +//! then incorrect results are returned. It is the caller's responsibility to +//! read only the samples that are available and wait until enough data is +//! available, for example as a result of receiving an interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +ADCSoftwareOversampleDataGet(uint32_t ui32Base, uint32_t ui32SequenceNum, + uint32_t *pui32Buffer, uint32_t ui32Count) +{ + uint32_t ui32Idx, ui32Accum; + uint32_t ui32ADCInst; + + // + // Evaluate the ADC Instance. + // + if(ui32Base == ADC0_BASE) + { + ui32ADCInst = 0; + } + else + { + ui32ADCInst = 1; + } + + + // + // Check the arguments. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + ASSERT(ui32SequenceNum < 3); + ASSERT(((ui32SequenceNum == 0) && + (ui32Count < + (8 >> g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]))) || + (ui32Count < + (4 >> g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]))); + + // + // Get the offset of the sequence to be read. + // + ui32Base += ADC_SEQ + (ADC_SEQ_STEP * ui32SequenceNum); + + // + // Read the samples from the FIFO until it is empty. + // + while(ui32Count--) + { + // + // Compute the sum of the samples. + // + ui32Accum = 0; + for(ui32Idx = 1 << g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]; + ui32Idx; ui32Idx--) + { + // + // Read the FIFO and add it to the accumulator. + // + ui32Accum += HWREG(ui32Base + ADC_SSFIFO); + } + + // + // Write the averaged sample to the output buffer. + // + *pui32Buffer++ = + ui32Accum >> g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]; + } +} + +//***************************************************************************** +// +//! Configures the hardware oversampling factor of the ADC. +//! +//! \param ui32Base is the base address of the ADC module. +//! \param ui32Factor is the number of samples to be averaged. +//! +//! This function configures the hardware oversampling for the ADC, which can +//! be used to provide better resolution on the sampled data. Oversampling is +//! accomplished by averaging multiple samples from the same analog input. Six +//! different oversampling rates are supported; 2x, 4x, 8x, 16x, 32x, and 64x. +//! Specifying an oversampling factor of zero disables hardware +//! oversampling. +//! +//! Hardware oversampling applies uniformly to all sample sequencers. It does +//! not reduce the depth of the sample sequencers like the software +//! oversampling APIs; each sample written into the sample sequencer FIFO is a +//! fully oversampled analog input reading. +//! +//! Enabling hardware averaging increases the precision of the ADC at the cost +//! of throughput. For example, enabling 4x oversampling reduces the +//! throughput of a 250 k samples/second ADC to 62.5 k samples/second. +//! +//! \return None. +// +//***************************************************************************** +void +ADCHardwareOversampleConfigure(uint32_t ui32Base, uint32_t ui32Factor) +{ + uint32_t ui32Value; + + // + // Check the arguments. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + ASSERT(((ui32Factor == 0) || (ui32Factor == 2) || (ui32Factor == 4) || + (ui32Factor == 8) || (ui32Factor == 16) || (ui32Factor == 32) || + (ui32Factor == 64))); + + // + // Convert the oversampling factor to a shift factor. + // + for(ui32Value = 0, ui32Factor >>= 1; ui32Factor; + ui32Value++, ui32Factor >>= 1) + { + } + + // + // Write the shift factor to the ADC to configure the hardware oversampler. + // + HWREG(ui32Base + ADC_O_SAC) = ui32Value; +} + +//***************************************************************************** +// +//! Configures an ADC digital comparator. +//! +//! \param ui32Base is the base address of the ADC module. +//! \param ui32Comp is the index of the comparator to configure. +//! \param ui32Config is the configuration of the comparator. +//! +//! This function configures a comparator. The \e ui32Config parameter is +//! the result of a logical OR operation between the \b ADC_COMP_TRIG_xxx, and +//! \b ADC_COMP_INT_xxx values. +//! +//! The \b ADC_COMP_TRIG_xxx term can take on the following values: +//! +//! - \b ADC_COMP_TRIG_NONE to never trigger PWM fault condition. +//! - \b ADC_COMP_TRIG_LOW_ALWAYS to always trigger PWM fault condition when +//! ADC output is in the low-band. +//! - \b ADC_COMP_TRIG_LOW_ONCE to trigger PWM fault condition once when ADC +//! output transitions into the low-band. +//! - \b ADC_COMP_TRIG_LOW_HALWAYS to always trigger PWM fault condition when +//! ADC output is in the low-band only if ADC output has been in the high-band +//! since the last trigger output. +//! - \b ADC_COMP_TRIG_LOW_HONCE to trigger PWM fault condition once when ADC +//! output transitions into low-band only if ADC output has been in the +//! high-band since the last trigger output. +//! - \b ADC_COMP_TRIG_MID_ALWAYS to always trigger PWM fault condition when +//! ADC output is in the mid-band. +//! - \b ADC_COMP_TRIG_MID_ONCE to trigger PWM fault condition once when ADC +//! output transitions into the mid-band. +//! - \b ADC_COMP_TRIG_HIGH_ALWAYS to always trigger PWM fault condition when +//! ADC output is in the high-band. +//! - \b ADC_COMP_TRIG_HIGH_ONCE to trigger PWM fault condition once when ADC +//! output transitions into the high-band. +//! - \b ADC_COMP_TRIG_HIGH_HALWAYS to always trigger PWM fault condition when +//! ADC output is in the high-band only if ADC output has been in the low-band +//! since the last trigger output. +//! - \b ADC_COMP_TRIG_HIGH_HONCE to trigger PWM fault condition once when ADC +//! output transitions into high-band only if ADC output has been in the +//! low-band since the last trigger output. +//! +//! The \b ADC_COMP_INT_xxx term can take on the following values: +//! +//! - \b ADC_COMP_INT_NONE to never generate ADC interrupt. +//! - \b ADC_COMP_INT_LOW_ALWAYS to always generate ADC interrupt when ADC +//! output is in the low-band. +//! - \b ADC_COMP_INT_LOW_ONCE to generate ADC interrupt once when ADC output +//! transitions into the low-band. +//! - \b ADC_COMP_INT_LOW_HALWAYS to always generate ADC interrupt when ADC +//! output is in the low-band only if ADC output has been in the high-band +//! since the last trigger output. +//! - \b ADC_COMP_INT_LOW_HONCE to generate ADC interrupt once when ADC output +//! transitions into low-band only if ADC output has been in the high-band +//! since the last trigger output. +//! - \b ADC_COMP_INT_MID_ALWAYS to always generate ADC interrupt when ADC +//! output is in the mid-band. +//! - \b ADC_COMP_INT_MID_ONCE to generate ADC interrupt once when ADC output +//! transitions into the mid-band. +//! - \b ADC_COMP_INT_HIGH_ALWAYS to always generate ADC interrupt when ADC +//! output is in the high-band. +//! - \b ADC_COMP_INT_HIGH_ONCE to generate ADC interrupt once when ADC output +//! transitions into the high-band. +//! - \b ADC_COMP_INT_HIGH_HALWAYS to always generate ADC interrupt when ADC +//! output is in the high-band only if ADC output has been in the low-band +//! since the last trigger output. +//! - \b ADC_COMP_INT_HIGH_HONCE to generate ADC interrupt once when ADC output +//! transitions into high-band only if ADC output has been in the low-band +//! since the last trigger output. +//! +//! \return None. +// +//***************************************************************************** +void +ADCComparatorConfigure(uint32_t ui32Base, uint32_t ui32Comp, + uint32_t ui32Config) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + ASSERT(ui32Comp < 8); + + // + // Save the new setting. + // + HWREG(ui32Base + ADC_O_DCCTL0 + (ui32Comp * 4)) = ui32Config; +} + +//***************************************************************************** +// +//! Defines the ADC digital comparator regions. +//! +//! \param ui32Base is the base address of the ADC module. +//! \param ui32Comp is the index of the comparator to configure. +//! \param ui32LowRef is the reference point for the low/mid band threshold. +//! \param ui32HighRef is the reference point for the mid/high band threshold. +//! +//! The ADC digital comparator operation is based on three ADC value regions: +//! - \b low-band is defined as any ADC value less than or equal to the +//! \e ui32LowRef value. +//! - \b mid-band is defined as any ADC value greater than the \e ui32LowRef +//! value but less than or equal to the \e ui32HighRef value. +//! - \b high-band is defined as any ADC value greater than the \e ui32HighRef +//! value. +//! +//! \return None. +// +//***************************************************************************** +void +ADCComparatorRegionSet(uint32_t ui32Base, uint32_t ui32Comp, + uint32_t ui32LowRef, uint32_t ui32HighRef) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + ASSERT(ui32Comp < 8); + ASSERT((ui32LowRef < 4096) && (ui32LowRef <= ui32HighRef)); + ASSERT(ui32HighRef < 4096); + + // + // Save the new region settings. + // + HWREG(ui32Base + ADC_O_DCCMP0 + (ui32Comp * 4)) = ((ui32HighRef << 16) | + ui32LowRef); +} + +//***************************************************************************** +// +//! Resets the current ADC digital comparator conditions. +//! +//! \param ui32Base is the base address of the ADC module. +//! \param ui32Comp is the index of the comparator. +//! \param bTrigger is the flag to indicate reset of Trigger conditions. +//! \param bInterrupt is the flag to indicate reset of Interrupt conditions. +//! +//! Because the digital comparator uses current and previous ADC values, this +//! function allows the comparator to be reset to its initial +//! value to prevent stale data from being used when a sequence is enabled. +//! +//! \return None. +// +//***************************************************************************** +void +ADCComparatorReset(uint32_t ui32Base, uint32_t ui32Comp, bool bTrigger, + bool bInterrupt) +{ + uint32_t ui32Temp; + + // + // Check the arguments. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + ASSERT(ui32Comp < 8); + + // + // Set the appropriate bits to reset the trigger and/or interrupt + // comparator conditions. + // + ui32Temp = 0; + if(bTrigger) + { + ui32Temp |= (1 << (16 + ui32Comp)); + } + if(bInterrupt) + { + ui32Temp |= (1 << ui32Comp); + } + + HWREG(ui32Base + ADC_O_DCRIC) = ui32Temp; +} + +//***************************************************************************** +// +//! Disables a sample sequence comparator interrupt. +//! +//! \param ui32Base is the base address of the ADC module. +//! \param ui32SequenceNum is the sample sequence number. +//! +//! This function disables the requested sample sequence comparator interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +ADCComparatorIntDisable(uint32_t ui32Base, uint32_t ui32SequenceNum) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + ASSERT(ui32SequenceNum < 4); + + // + // Disable this sample sequence comparator interrupt. + // + HWREG(ui32Base + ADC_O_IM) &= ~(0x10000 << ui32SequenceNum); +} + +//***************************************************************************** +// +//! Enables a sample sequence comparator interrupt. +//! +//! \param ui32Base is the base address of the ADC module. +//! \param ui32SequenceNum is the sample sequence number. +//! +//! This function enables the requested sample sequence comparator interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +ADCComparatorIntEnable(uint32_t ui32Base, uint32_t ui32SequenceNum) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + ASSERT(ui32SequenceNum < 4); + + // + // Enable this sample sequence interrupt. + // + HWREG(ui32Base + ADC_O_IM) |= 0x10000 << ui32SequenceNum; +} + +//***************************************************************************** +// +//! Gets the current comparator interrupt status. +//! +//! \param ui32Base is the base address of the ADC module. +//! +//! This function returns the digital comparator interrupt status bits. This +//! status is sequence agnostic. +//! +//! \return The current comparator interrupt status. +// +//***************************************************************************** +uint32_t +ADCComparatorIntStatus(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + + // + // Return the digital comparator interrupt status. + // + return(HWREG(ui32Base + ADC_O_DCISC)); +} + +//***************************************************************************** +// +//! Clears sample sequence comparator interrupt source. +//! +//! \param ui32Base is the base address of the ADC module. +//! \param ui32Status is the bit-mapped interrupts status to clear. +//! +//! The specified interrupt status is cleared. +//! +//! \return None. +// +//***************************************************************************** +void +ADCComparatorIntClear(uint32_t ui32Base, uint32_t ui32Status) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + + // + // Clear the interrupt. + // + HWREG(ui32Base + ADC_O_DCISC) = ui32Status; +} + +//***************************************************************************** +// +//! Disables ADC interrupt sources. +//! +//! \param ui32Base is the base address of the ADC module. +//! \param ui32IntFlags is the bit mask of the interrupt sources to disable. +//! +//! This function disables the indicated ADC interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ui32IntFlags parameter is the logical OR of any of the following: +//! +//! - \b ADC_INT_SS0 - interrupt due to ADC sample sequence 0. +//! - \b ADC_INT_SS1 - interrupt due to ADC sample sequence 1. +//! - \b ADC_INT_SS2 - interrupt due to ADC sample sequence 2. +//! - \b ADC_INT_SS3 - interrupt due to ADC sample sequence 3. +//! - \b ADC_INT_DMA_SS0 - interrupt due to DMA on ADC sample sequence 0. +//! - \b ADC_INT_DMA_SS1 - interrupt due to DMA on ADC sample sequence 1. +//! - \b ADC_INT_DMA_SS2 - interrupt due to DMA on ADC sample sequence 2. +//! - \b ADC_INT_DMA_SS3 - interrupt due to DMA on ADC sample sequence 3. +//! - \b ADC_INT_DCON_SS0 - interrupt due to digital comparator on ADC sample +//! sequence 0. +//! - \b ADC_INT_DCON_SS1 - interrupt due to digital comparator on ADC sample +//! sequence 1. +//! - \b ADC_INT_DCON_SS2 - interrupt due to digital comparator on ADC sample +//! sequence 2. +//! - \b ADC_INT_DCON_SS3 - interrupt due to digital comparator on ADC sample +//! sequence 3. +//! +//! \return None. +// +//***************************************************************************** +void +ADCIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + + // + // Disable the requested interrupts. + // + HWREG(ui32Base + ADC_O_IM) &= ~ui32IntFlags; +} + +//***************************************************************************** +// +//! Enables ADC interrupt sources. +//! +//! \param ui32Base is the base address of the ADC module. +//! \param ui32IntFlags is the bit mask of the interrupt sources to disable. +//! +//! This function enables the indicated ADC interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ui32IntFlags parameter is the logical OR of any of the following: +//! +//! - \b ADC_INT_SS0 - interrupt due to ADC sample sequence 0. +//! - \b ADC_INT_SS1 - interrupt due to ADC sample sequence 1. +//! - \b ADC_INT_SS2 - interrupt due to ADC sample sequence 2. +//! - \b ADC_INT_SS3 - interrupt due to ADC sample sequence 3. +//! - \b ADC_INT_DMA_SS0 - interrupt due to DMA on ADC sample sequence 0. +//! - \b ADC_INT_DMA_SS1 - interrupt due to DMA on ADC sample sequence 1. +//! - \b ADC_INT_DMA_SS2 - interrupt due to DMA on ADC sample sequence 2. +//! - \b ADC_INT_DMA_SS3 - interrupt due to DMA on ADC sample sequence 3. +//! - \b ADC_INT_DCON_SS0 - interrupt due to digital comparator on ADC sample +//! sequence 0. +//! - \b ADC_INT_DCON_SS1 - interrupt due to digital comparator on ADC sample +//! sequence 1. +//! - \b ADC_INT_DCON_SS2 - interrupt due to digital comparator on ADC sample +//! sequence 2. +//! - \b ADC_INT_DCON_SS3 - interrupt due to digital comparator on ADC sample +//! sequence 3. +//! +//! \return None. +// +//***************************************************************************** +void +ADCIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + + // + // Enable the requested interrupts. + // + HWREG(ui32Base + ADC_O_IM) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! Gets interrupt status for the specified ADC module. +//! +//! \param ui32Base is the base address of the ADC module. +//! \param bMasked specifies whether masked or raw interrupt status is +//! returned. +//! +//! If \e bMasked is set as \b true, then the masked interrupt status is +//! returned; otherwise, the raw interrupt status is returned. +//! +//! \return Returns the current interrupt status for the specified ADC module. +//! The value returned is the logical OR of the \b ADC_INT_* values that are +//! currently active. +// +//***************************************************************************** +uint32_t +ADCIntStatusEx(uint32_t ui32Base, bool bMasked) +{ + uint32_t ui32Temp; + + // + // Check the arguments. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + + // + // Return either the masked interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + ui32Temp = HWREG(ui32Base + ADC_O_ISC); + } + else + { + // + // Read the Raw interrupt status to see if a digital comparator + // interrupt is active. + // + ui32Temp = HWREG(ui32Base + ADC_O_RIS); + + // + // Since, the raw interrupt status only indicates that any one of the + // digital comparators caused an interrupt, if the raw interrupt status + // is set then the return value is modified to indicate that all sample + // sequences have a pending digital comparator interrupt. + // This is exactly how the hardware works so the return code is + // modified to match this behavior. + // + if(ui32Temp & ADC_RIS_INRDC) + { + ui32Temp |= (ADC_INT_DCON_SS3 | ADC_INT_DCON_SS2 | + ADC_INT_DCON_SS1 | ADC_INT_DCON_SS0); + } + } + return(ui32Temp); +} + +//***************************************************************************** +// +//! Clears the specified ADC interrupt sources. +//! +//! \param ui32Base is the base address of the ADC port. +//! \param ui32IntFlags is the bit mask of the interrupt sources to disable. +//! +//! Clears the interrupt for the specified interrupt source(s). +//! +//! The \e ui32IntFlags parameter is the logical OR of the \b ADC_INT_* values. +//! See the ADCIntEnableEx() function for the list of possible \b ADC_INT* +//! values. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +ADCIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Note: The interrupt bits are "W1C" so we DO NOT use a logical OR + // here to clear the requested bits. Doing so would clear all outstanding + // interrupts rather than just those which the caller has specified. + // + HWREG(ui32Base + ADC_O_ISC) = ui32IntFlags; +} + +//***************************************************************************** +// +//! Selects the ADC reference. +//! +//! \param ui32Base is the base address of the ADC module. +//! \param ui32Ref is the reference to use. +//! +//! The ADC reference is set as specified by \e ui32Ref. It must be one of +//! \b ADC_REF_INT, or \b ADC_REF_EXT_3V for internal or external reference +//! If \b ADC_REF_INT is chosen, then an internal 3V reference is used and +//! no external reference is needed. If \b ADC_REF_EXT_3V is chosen, then +//! a 3V reference must be supplied to the AVREF pin. +//! +//! \note The ADC reference can only be selected on parts that have an external +//! reference. Consult the data sheet for your part to determine if there is +//! an external reference. +//! +//! \return None. +// +//***************************************************************************** +void +ADCReferenceSet(uint32_t ui32Base, uint32_t ui32Ref) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + ASSERT((ui32Ref == ADC_REF_INT) || (ui32Ref == ADC_REF_EXT_3V)); + + // + // Set the reference. + // + HWREG(ui32Base + ADC_O_CTL) = + (HWREG(ui32Base + ADC_O_CTL) & ~ADC_CTL_VREF_M) | ui32Ref; +} + +//***************************************************************************** +// +//! Returns the current setting of the ADC reference. +//! +//! \param ui32Base is the base address of the ADC module. +//! +//! Returns the value of the ADC reference setting. The returned value is one +//! of \b ADC_REF_INT, or \b ADC_REF_EXT_3V. +//! +//! \note The value returned by this function is only meaningful if used on a +//! part that is capable of using an external reference. Consult the data +//! sheet for your part to determine if it has an external reference input. +//! +//! \return The current setting of the ADC reference. +// +//***************************************************************************** +uint32_t +ADCReferenceGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + + // + // Return the value of the reference. + // + return(HWREG(ui32Base + ADC_O_CTL) & ADC_CTL_VREF_M); +} + +//***************************************************************************** +// +//! Sets the phase delay between a trigger and the start of a sequence. +//! +//! \param ui32Base is the base address of the ADC module. +//! \param ui32Phase is the phase delay, specified as one of \b ADC_PHASE_0, +//! \b ADC_PHASE_22_5, \b ADC_PHASE_45, \b ADC_PHASE_67_5, \b ADC_PHASE_90, +//! \b ADC_PHASE_112_5, \b ADC_PHASE_135, \b ADC_PHASE_157_5, \b ADC_PHASE_180, +//! \b ADC_PHASE_202_5, \b ADC_PHASE_225, \b ADC_PHASE_247_5, \b ADC_PHASE_270, +//! \b ADC_PHASE_292_5, \b ADC_PHASE_315, or \b ADC_PHASE_337_5. +//! +//! This function sets the phase delay between the detection of an ADC trigger +//! event and the start of the sample sequence. By selecting a different phase +//! delay for a pair of ADC modules (such as \b ADC_PHASE_0 and +//! \b ADC_PHASE_180) and having each ADC module sample the same analog input, +//! it is possible to increase the sampling rate of the analog input (with +//! samples N, N+2, N+4, and so on, coming from the first ADC and samples N+1, +//! N+3, N+5, and so on, coming from the second ADC). The ADC module has a +//! single phase delay that is applied to all sample sequences within that +//! module. +//! +//! \note This capability is not available on all parts. +//! +//! \return None. +// +//***************************************************************************** +void +ADCPhaseDelaySet(uint32_t ui32Base, uint32_t ui32Phase) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + ASSERT((ui32Phase == ADC_PHASE_0) || (ui32Phase == ADC_PHASE_22_5) || + (ui32Phase == ADC_PHASE_45) || (ui32Phase == ADC_PHASE_67_5) || + (ui32Phase == ADC_PHASE_90) || (ui32Phase == ADC_PHASE_112_5) || + (ui32Phase == ADC_PHASE_135) || (ui32Phase == ADC_PHASE_157_5) || + (ui32Phase == ADC_PHASE_180) || (ui32Phase == ADC_PHASE_202_5) || + (ui32Phase == ADC_PHASE_225) || (ui32Phase == ADC_PHASE_247_5) || + (ui32Phase == ADC_PHASE_270) || (ui32Phase == ADC_PHASE_292_5) || + (ui32Phase == ADC_PHASE_315) || (ui32Phase == ADC_PHASE_337_5)); + + // + // Set the phase delay. + // + HWREG(ui32Base + ADC_O_SPC) = ui32Phase; +} + +//***************************************************************************** +// +//! Gets the phase delay between a trigger and the start of a sequence. +//! +//! \param ui32Base is the base address of the ADC module. +//! +//! This function gets the current phase delay between the detection of an ADC +//! trigger event and the start of the sample sequence. +//! +//! \return Returns the phase delay, specified as one of \b ADC_PHASE_0, +//! \b ADC_PHASE_22_5, \b ADC_PHASE_45, \b ADC_PHASE_67_5, \b ADC_PHASE_90, +//! \b ADC_PHASE_112_5, \b ADC_PHASE_135, \b ADC_PHASE_157_5, \b ADC_PHASE_180, +//! \b ADC_PHASE_202_5, \b ADC_PHASE_225, \b ADC_PHASE_247_5, \b ADC_PHASE_270, +//! \b ADC_PHASE_292_5, \b ADC_PHASE_315, or \b ADC_PHASE_337_5. +// +//***************************************************************************** +uint32_t +ADCPhaseDelayGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + + // + // Return the phase delay. + // + return(HWREG(ui32Base + ADC_O_SPC)); +} + +//***************************************************************************** +// +//! Enables DMA for sample sequencers. +//! +//! \param ui32Base is the base address of the ADC module. +//! \param ui32SequenceNum is the sample sequence number. +//! +//! Allows DMA requests to be generated based on the FIFO level of the sample +//! sequencer. +//! +//! \return None. +// +//***************************************************************************** +void +ADCSequenceDMAEnable(uint32_t ui32Base, uint32_t ui32SequenceNum) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + ASSERT(ui32SequenceNum < 4); + + // + // Enable the DMA on the specified sequencer. + // + HWREG(ui32Base + ADC_O_ACTSS) |= 0x100 << ui32SequenceNum; +} + +//***************************************************************************** +// +//! Disables DMA for sample sequencers. +//! +//! \param ui32Base is the base address of the ADC module. +//! \param ui32SequenceNum is the sample sequence number. +//! +//! Prevents the specified sample sequencer from generating DMA requests. +//! +//! \return None. +// +//***************************************************************************** +void +ADCSequenceDMADisable(uint32_t ui32Base, uint32_t ui32SequenceNum) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + ASSERT(ui32SequenceNum < 4); + + // + // Disable the DMA on the specified sequencer. + // + HWREG(ui32Base + ADC_O_ACTSS) &= ~(0x100 << ui32SequenceNum); +} + +//***************************************************************************** +// +//! Determines whether the ADC is busy or not. +//! +//! \param ui32Base is the base address of the ADC. +//! +//! This function allows the caller to determine whether or not the ADC is +//! currently sampling . If \b false is returned, then the ADC is not +//! sampling data. +//! +//! Use this function to detect that the ADC is finished sampling data before +//! putting the device into deep sleep. Before using this function, it is +//! highly recommended that the event trigger is changed to +//! \b ADC_TRIGGER_NEVER on all enabled sequencers to prevent the ADC from +//! starting after checking the busy status. +//! +//! \return Returns \b true if the ADC is sampling or \b false if all +//! samples are complete. +// +//***************************************************************************** +bool +ADCBusy(uint32_t ui32Base) +{ + // + // Check the argument. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + + // + // Determine if the ADC is busy. + // + return((HWREG(ui32Base + ADC_O_ACTSS) & ADC_ACTSS_BUSY) ? true : false); +} + +//***************************************************************************** +// +//! Sets the clock configuration for the ADC. +//! +//! \param ui32Base is the base address of the ADC to configure, which must +//! always be \b ADC0_BASE. +//! \param ui32Config is a combination of the \b ADC_CLOCK_SRC_ and +//! \b ADC_CLOCK_RATE_* values used to configure the ADC clock input. +//! \param ui32ClockDiv is the input clock divider for the clock selected by +//! the \b ADC_CLOCK_SRC value. +//! +//! This function is used to configure the input clock to the ADC modules. The +//! clock configuration is shared across ADC units so \e ui32Base must +//! always be \b ADC0_BASE. The \e ui32Config value is logical OR of one +//! of the \b ADC_CLOCK_RATE_ and one of the \b ADC_CLOCK_SRC_ values defined +//! below. The \b ADC_CLOCK_SRC_* values determine the input clock for the ADC. +//! Not all values are available on all devices so check the device data sheet +//! to determine value configuration options. Regardless of the source, the +//! final frequency for TM4C123x devices must be 16 MHz and for TM4C129x parts +//! after dividing must be between 16 and 32 MHz. +//! +//! \note For TM4C123x devices, if the PLL is enabled, the PLL/25 is used as +//! the ADC clock unless ADC_CLOCK_SRC_PIOSC is specified. If the PLL is +//! disabled, the MOSC is used as the clock source unless ADC_CLOCK_SRC_PIOSC +//! is specified. +//! +//! - \b ADC_CLOCK_SRC_PLL - The main PLL output (TM4x129 class only). +//! - \b ADC_CLOCK_SRC_PIOSC - The internal PIOSC at 16 MHz. +//! - \b ADC_CLOCK_SRC_ALTCLK - The output of the ALTCLK in the system control +//! module (TM4x129 class only). +//! - \b ADC_CLOCK_SRC_MOSC - The external MOSC (TM4x129 class only). +//! +//! \b ADC_CLOCK_RATE values control how often samples are provided back to the +//! application. The values are the following: +//! +//! - \b ADC_CLOCK_RATE_FULL - All samples. +//! - \b ADC_CLOCK_RATE_HALF - Every other sample. +//! - \b ADC_CLOCK_RATE_QUARTER - Every fourth sample. +//! - \b ADC_CLOCK_RATE_EIGHTH - Every either sample. +//! +//! The \e ui32ClockDiv parameter allows for dividing a higher frequency down +//! into the valid range for the ADCs. This parameter is typically only used +//! \b ADC_CLOCK_SRC_PLL option because it is the only clock value that can be +//! with the in the correct range to use the divider. The actual value ranges +//! from 1 to 64. +//! +//! \b Example: ADC Clock Configurations +//! +//! \verbatim +//! +//! // +//! // Configure the ADC to use PIOSC divided by one (16 MHz) and sample at +//! // half the rate. +//! // +//! ADCClockConfigSet(ADC0_BASE, ADC_CLOCK_SRC_PIOSC | ADC_CLOCK_RATE_HALF, 1); +//! +//! ... +//! +//! // +//! // Configure the ADC to use PLL at 480 MHz divided by 24 to get an ADC +//! // clock of 20 MHz. +//! // +//! ADCClockConfigSet(ADC0_BASE, ADC_CLOCK_SRC_PLL | ADC_CLOCK_RATE_FULL, 24); +//! \endverbatim +//! +//! \return None. +// +//***************************************************************************** +void +ADCClockConfigSet(uint32_t ui32Base, uint32_t ui32Config, + uint32_t ui32ClockDiv) +{ + // + // Check the argument. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + ASSERT((ui32ClockDiv - 1) <= (ADC_CC_CLKDIV_M >> ADC_CC_CLKDIV_S)); + + // + // A rate must be supplied. + // + ASSERT((ui32Config & ADC_CLOCK_RATE_FULL) != 0); + + // + // Write the sample conversion rate. + // + HWREG(ui32Base + ADC_O_PC) = (ui32Config >> 4) & ADC_PC_SR_M; + + // + // Write the clock select and divider. + // + HWREG(ui32Base + ADC_O_CC) = (ui32Config & ADC_CC_CS_M) | + (((ui32ClockDiv - 1) << ADC_CC_CLKDIV_S)) ; +} + +//***************************************************************************** +// +//! Returns the clock configuration for the ADC. +//! +//! \param ui32Base is the base address of the ADC to configure, which must +//! always be \b ADC0_BASE. +//! \param pui32ClockDiv is a pointer to the input clock divider for the clock +//! selected by the \b ADC_CLOCK_SRC in use by the ADCs. +//! +//! This function returns the ADC clock configuration and the clock divider for +//! the ADCs. +//! +//! \b Example: Read the current ADC clock configuration. +//! +//! \verbatim +//! uint32_t ui32Config, ui32ClockDiv; +//! +//! // +//! // Read the current ADC clock configuration. +//! // +//! ui32Config = ADCClockConfigGet(ADC0_BASE, &ui32ClockDiv); +//! \endverbatim +//! +//! \return The current clock configuration of the ADC defined as a combination +//! of one of \b ADC_CLOCK_SRC_PLL, \b ADC_CLOCK_SRC_PIOSC, +//! \b ADC_CLOCK_SRC_MOSC, or \b ADC_CLOCK_SRC_ALTCLK logical ORed with one of +//! \b ADC_CLOCK_RATE_FULL, \b ADC_CLOCK_RATE_HALF, \b ADC_CLOCK_RATE_QUARTER, +//! or \b ADC_CLOCK_RATE_EIGHTH. See ADCClockConfigSet() for more information +//! on these values. +// +//***************************************************************************** +uint32_t +ADCClockConfigGet(uint32_t ui32Base, uint32_t *pui32ClockDiv) +{ + uint32_t ui32Config; + + // + // Check the argument. + // + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + + // + // Read the current configuration. + // + ui32Config = HWREG(ui32Base + ADC_O_CC); + + // + // If the clock divider was requested provide the current value. + // + if(pui32ClockDiv) + { + *pui32ClockDiv = + ((ui32Config & ADC_CC_CLKDIV_M) >> ADC_CC_CLKDIV_S) + 1; + } + + // + // Clear out the divider bits. + // + ui32Config &= ~ADC_CC_CLKDIV_M; + + // + // Add in the sample interval to the configuration. + // + ui32Config |= (HWREG(ui32Base + ADC_O_PC) & ADC_PC_SR_M) << 4; + + return(ui32Config); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/aes.c b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/aes.c new file mode 100644 index 0000000000000000000000000000000000000000..06cf55bb0b10d8cc40b7ee422236404fcccb7574 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/aes.c @@ -0,0 +1,1305 @@ +//***************************************************************************** +// +// aes.c - Driver for the AES module. +// +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup aes_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include +#include "inc/hw_aes.h" +#include "inc/hw_ccm.h" +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_nvic.h" +#include "inc/hw_types.h" +#include "driverlib/aes.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" + +//***************************************************************************** +// +//! Resets the AES module. +//! +//! \param ui32Base is the base address of the AES module. +//! +//! This function performs a softreset the AES module. +//! +//! \return None. +// +//***************************************************************************** +void +AESReset(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + + // + // Trigger the reset. + // + HWREG(ui32Base + AES_O_SYSCONFIG) |= AES_SYSCONFIG_SOFTRESET; + + // + // Wait for the reset to finish. + // + while((HWREG(ui32Base + AES_O_SYSSTATUS) & + AES_SYSSTATUS_RESETDONE) == 0) + { + } +} + +//***************************************************************************** +// +//! Configures the AES module. +//! +//! \param ui32Base is the base address of the AES module. +//! \param ui32Config is the configuration of the AES module. +//! +//! This function configures the AES module based on the specified parameters. +//! It does not change any DMA- or interrupt-related parameters. +//! +//! The ui32Config parameter is a bit-wise OR of a number of configuration +//! flags. The valid flags are grouped based on their function. +//! +//! The direction of the operation is specified with only of following flags: +//! +//! - \b AES_CFG_DIR_ENCRYPT - Encryption mode +//! - \b AES_CFG_DIR_DECRYPT - Decryption mode +//! +//! The key size is specified with only one of the following flags: +//! +//! - \b AES_CFG_KEY_SIZE_128BIT - Key size of 128 bits +//! - \b AES_CFG_KEY_SIZE_192BIT - Key size of 192 bits +//! - \b AES_CFG_KEY_SIZE_256BIT - Key size of 256 bits +//! +//! The mode of operation is specified with only one of the following flags. +//! +//! - \b AES_CFG_MODE_ECB - Electronic codebook mode +//! - \b AES_CFG_MODE_CBC - Cipher-block chaining mode +//! - \b AES_CFG_MODE_CFB - Cipher feedback mode +//! - \b AES_CFG_MODE_CTR - Counter mode +//! - \b AES_CFG_MODE_ICM - Integer counter mode +//! - \b AES_CFG_MODE_XTS - Ciphertext stealing mode +//! - \b AES_CFG_MODE_XTS_TWEAKJL - XEX-based tweaked-codebook mode with +//! ciphertext stealing with previous/intermediate tweak value and j loaded +//! - \b AES_CFG_MODE_XTS_K2IJL - XEX-based tweaked-codebook mode with +//! ciphertext stealing with key2, i and j loaded +//! - \b AES_CFG_MODE_XTS_K2ILJ0 - XEX-based tweaked-codebook mode with +//! ciphertext stealing with key2 and i loaded, j = 0 +//! - \b AES_CFG_MODE_F8 - F8 mode +//! - \b AES_CFG_MODE_F9 - F9 mode +//! - \b AES_CFG_MODE_CBCMAC - Cipher block chaining message authentication +//! code mode +//! - \b AES_CFG_MODE_GCM_HLY0ZERO - Galois/counter mode with GHASH with H +//! loaded, Y0-encrypted forced to zero and counter is not enabled. +//! - \b AES_CFG_MODE_GCM_HLY0CALC - Galois/counter mode with GHASH with H +//! loaded, Y0-encrypted calculated internally and counter is enabled. +//! - \b AES_CFG_MODE_GCM_HY0CALC - Galois/Counter mode with autonomous GHASH +//! (both H and Y0-encrypted calculated internally) and counter is enabled. +//! - \b AES_CFG_MODE_CCM - Counter with CBC-MAC mode +//! +//! The following defines are used to specify the counter width. It is only +//! required to be defined when using CTR, CCM, or GCM modes, only one of the +//! following defines must be used to specify the counter width length: +//! +//! - \b AES_CFG_CTR_WIDTH_32 - Counter is 32 bits +//! - \b AES_CFG_CTR_WIDTH_64 - Counter is 64 bits +//! - \b AES_CFG_CTR_WIDTH_96 - Counter is 96 bits +//! - \b AES_CFG_CTR_WIDTH_128 - Counter is 128 bits +//! +//! Only one of the following defines must be used to specify the length field +//! for CCM operations (L): +//! +//! - \b AES_CFG_CCM_L_1 - 1 byte +//! - \b AES_CFG_CCM_L_2 - 2 bytes +//! - \b AES_CFG_CCM_L_3 - 3 bytes +//! - \b AES_CFG_CCM_L_4 - 4 bytes +//! - \b AES_CFG_CCM_L_5 - 5 bytes +//! - \b AES_CFG_CCM_L_6 - 6 bytes +//! - \b AES_CFG_CCM_L_7 - 7 bytes +//! - \b AES_CFG_CCM_L_8 - 8 bytes +//! +//! Only one of the following defines must be used to specify the length of the +//! authentication field for CCM operations (M) through the \e ui32Config +//! argument in the AESConfigSet() function: +//! +//! - \b AES_CFG_CCM_M_4 - 4 bytes +//! - \b AES_CFG_CCM_M_6 - 6 bytes +//! - \b AES_CFG_CCM_M_8 - 8 bytes +//! - \b AES_CFG_CCM_M_10 - 10 bytes +//! - \b AES_CFG_CCM_M_12 - 12 bytes +//! - \b AES_CFG_CCM_M_14 - 14 bytes +//! - \b AES_CFG_CCM_M_16 - 16 bytes +//! +//! \note When performing a basic GHASH operation for used with GCM mode, use +//! the \b AES_CFG_MODE_GCM_HLY0ZERO and do not specify a direction. +//! +//! \return None. +// +//***************************************************************************** +void +AESConfigSet(uint32_t ui32Base, uint32_t ui32Config) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + ASSERT((ui32Config & AES_CFG_DIR_ENCRYPT) || + (ui32Config & AES_CFG_DIR_DECRYPT)); + ASSERT((ui32Config & AES_CFG_KEY_SIZE_128BIT) || + (ui32Config & AES_CFG_KEY_SIZE_192BIT) || + (ui32Config & AES_CFG_KEY_SIZE_256BIT)); + ASSERT((ui32Config & AES_CFG_MODE_ECB) || + (ui32Config & AES_CFG_MODE_CBC) || + (ui32Config & AES_CFG_MODE_CTR) || + (ui32Config & AES_CFG_MODE_ICM) || + (ui32Config & AES_CFG_MODE_CFB) || + (ui32Config & AES_CFG_MODE_XTS_TWEAKJL) || + (ui32Config & AES_CFG_MODE_XTS_K2IJL) || + (ui32Config & AES_CFG_MODE_XTS_K2ILJ0) || + (ui32Config & AES_CFG_MODE_F8) || + (ui32Config & AES_CFG_MODE_F9) || + (ui32Config & AES_CFG_MODE_CTR) || + (ui32Config & AES_CFG_MODE_CBCMAC) || + (ui32Config & AES_CFG_MODE_GCM_HLY0ZERO) || + (ui32Config & AES_CFG_MODE_GCM_HLY0CALC) || + (ui32Config & AES_CFG_MODE_GCM_HY0CALC) || + (ui32Config & AES_CFG_MODE_CCM)); + ASSERT(((ui32Config & AES_CFG_MODE_CTR) || + (ui32Config & AES_CFG_MODE_GCM_HLY0ZERO) || + (ui32Config & AES_CFG_MODE_GCM_HLY0CALC) || + (ui32Config & AES_CFG_MODE_GCM_HY0CALC) || + (ui32Config & AES_CFG_MODE_CCM)) && + ((ui32Config & AES_CFG_CTR_WIDTH_32) || + (ui32Config & AES_CFG_CTR_WIDTH_64) || + (ui32Config & AES_CFG_CTR_WIDTH_96) || + (ui32Config & AES_CFG_CTR_WIDTH_128))); + ASSERT((ui32Config & AES_CFG_MODE_CCM) && + ((ui32Config & AES_CFG_CCM_L_1) || + (ui32Config & AES_CFG_CCM_L_2) || + (ui32Config & AES_CFG_CCM_L_3) || + (ui32Config & AES_CFG_CCM_L_4) || + (ui32Config & AES_CFG_CCM_L_5) || + (ui32Config & AES_CFG_CCM_L_6) || + (ui32Config & AES_CFG_CCM_L_7) || + (ui32Config & AES_CFG_CCM_L_8)) && + ((ui32Config & AES_CFG_CCM_M_4) || + (ui32Config & AES_CFG_CCM_M_6) || + (ui32Config & AES_CFG_CCM_M_8) || + (ui32Config & AES_CFG_CCM_M_10) || + (ui32Config & AES_CFG_CCM_M_12) || + (ui32Config & AES_CFG_CCM_M_14) || + (ui32Config & AES_CFG_CCM_M_16))); + + // + // Backup the save context field before updating the register. + // + if(HWREG(ui32Base + AES_O_CTRL) & AES_CTRL_SAVE_CONTEXT) + { + ui32Config |= AES_CTRL_SAVE_CONTEXT; + } + + // + // Write the CTRL register with the new value + // + HWREG(ui32Base + AES_O_CTRL) = ui32Config; +} + +//***************************************************************************** +// +//! Writes the key 1 configuration registers, which are used for encryption or +//! decryption. +//! +//! \param ui32Base is the base address for the AES module. +//! \param pui32Key is an array of 32-bit words, containing the key to be +//! configured. The least significant word in the 0th index. +//! \param ui32Keysize is the size of the key, which must be one of the +//! following values: \b AES_CFG_KEY_SIZE_128, \b AES_CFG_KEY_SIZE_192, or +//! \b AES_CFG_KEY_SIZE_256. +//! +//! This function writes key 1 configuration registers based on the key +//! size. This function is used in all modes. +//! +//! \return None. +// +//***************************************************************************** +void +AESKey1Set(uint32_t ui32Base, uint32_t *pui32Key, uint32_t ui32Keysize) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + ASSERT((ui32Keysize == AES_CFG_KEY_SIZE_128BIT) || + (ui32Keysize == AES_CFG_KEY_SIZE_192BIT) || + (ui32Keysize == AES_CFG_KEY_SIZE_256BIT)); + + // + // With all key sizes, the first 4 words are written. + // + HWREG(ui32Base + AES_O_KEY1_0) = pui32Key[0]; + HWREG(ui32Base + AES_O_KEY1_1) = pui32Key[1]; + HWREG(ui32Base + AES_O_KEY1_2) = pui32Key[2]; + HWREG(ui32Base + AES_O_KEY1_3) = pui32Key[3]; + + // + // The key is 192 or 256 bits. Write the next 2 words. + // + if(ui32Keysize != AES_CFG_KEY_SIZE_128BIT) + { + HWREG(ui32Base + AES_O_KEY1_4) = pui32Key[4]; + HWREG(ui32Base + AES_O_KEY1_5) = pui32Key[5]; + } + + // + // The key is 256 bits. Write the last 2 words. + // + if(ui32Keysize == AES_CFG_KEY_SIZE_256BIT) + { + HWREG(ui32Base + AES_O_KEY1_6) = pui32Key[6]; + HWREG(ui32Base + AES_O_KEY1_7) = pui32Key[7]; + } +} + +//***************************************************************************** +// +//! Writes the key 2 configuration registers, which are used for encryption or +//! decryption. +//! +//! \param ui32Base is the base address for the AES module. +//! \param pui32Key is an array of 32-bit words, containing the key to be +//! configured. The least significant word in the 0th index. +//! \param ui32Keysize is the size of the key, which must be one of the +//! following values: \b AES_CFG_KEY_SIZE_128, \b AES_CFG_KEY_SIZE_192, or +//! \b AES_CFG_KEY_SIZE_256. +//! +//! This function writes the key 2 configuration registers based on the key +//! size. This function is used in the F8, F9, XTS, CCM, and CBC-MAC modes. +//! +//! \return None. +// +//***************************************************************************** +void +AESKey2Set(uint32_t ui32Base, uint32_t *pui32Key, uint32_t ui32Keysize) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + ASSERT((ui32Keysize == AES_CFG_KEY_SIZE_128BIT) || + (ui32Keysize == AES_CFG_KEY_SIZE_192BIT) || + (ui32Keysize == AES_CFG_KEY_SIZE_256BIT)); + + // + // With all key sizes, the first 4 words are written. + // + HWREG(ui32Base + AES_O_KEY2_0) = pui32Key[0]; + HWREG(ui32Base + AES_O_KEY2_1) = pui32Key[1]; + HWREG(ui32Base + AES_O_KEY2_2) = pui32Key[2]; + HWREG(ui32Base + AES_O_KEY2_3) = pui32Key[3]; + + // + // The key is 192 or 256 bits. Write the next 2 words. + // + if(ui32Keysize != AES_CFG_KEY_SIZE_128BIT) + { + HWREG(ui32Base + AES_O_KEY2_4) = pui32Key[4]; + HWREG(ui32Base + AES_O_KEY2_5) = pui32Key[5]; + } + + // + // The key is 256 bits. Write the last 2 words. + // + if(ui32Keysize == AES_CFG_KEY_SIZE_256BIT) + { + HWREG(ui32Base + AES_O_KEY2_6) = pui32Key[6]; + HWREG(ui32Base + AES_O_KEY2_7) = pui32Key[7]; + } +} + +//***************************************************************************** +// +//! Writes key 3 configuration registers, which are used for encryption or +//! decryption. +//! +//! \param ui32Base is the base address for the AES module. +//! \param pui32Key is a pointer to an array of 4 words (128 bits), containing +//! the key to be configured. The least significant word is in the 0th index. +//! +//! This function writes the key 2 configuration registers with key 3 data +//! used in CBC-MAC and F8 modes. This key is always 128 bits. +//! +//! \return None. +// +//***************************************************************************** +void +AESKey3Set(uint32_t ui32Base, uint32_t *pui32Key) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + + // + // Write the key into the upper 4 key registers + // + HWREG(ui32Base + AES_O_KEY2_4) = pui32Key[0]; + HWREG(ui32Base + AES_O_KEY2_5) = pui32Key[1]; + HWREG(ui32Base + AES_O_KEY2_6) = pui32Key[2]; + HWREG(ui32Base + AES_O_KEY2_7) = pui32Key[3]; +} + +//***************************************************************************** +// +//! Writes the Initial Vector (IV) register, needed in some of the AES Modes. +//! +//! \param ui32Base is the base address of the AES module. +//! \param pui32IVdata is an array of 4 words (128 bits), containing the IV +//! value to be configured. The least significant word is in the 0th index. +//! +//! This functions writes the initial vector registers in the AES module. +//! +//! \return None. +// +//***************************************************************************** +void +AESIVSet(uint32_t ui32Base, uint32_t *pui32IVdata) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + + // + // Write the initial vector registers. + // + HWREG(ui32Base + AES_O_IV_IN_0) = pui32IVdata[0]; + HWREG(ui32Base + AES_O_IV_IN_1) = pui32IVdata[1]; + HWREG(ui32Base + AES_O_IV_IN_2) = pui32IVdata[2]; + HWREG(ui32Base + AES_O_IV_IN_3) = pui32IVdata[3]; +} + +//***************************************************************************** +// +//! Saves the Initial Vector (IV) registers to a user-defined location. +//! +//! \param ui32Base is the base address of the AES module. +//! \param pui32IVData is pointer to the location that stores the IV data. +//! +//! This function stores the IV for use with authenticated encryption and +//! decryption operations. It is assumed that the AES_CTRL_SAVE_CONTEXT +//! bit is set in the AES_CTRL register. +//! +//! \return None. +// +//***************************************************************************** +void +AESIVRead(uint32_t ui32Base, uint32_t *pui32IVData) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + + // + // Wait for the output context to be ready. + // + while((AES_CTRL_SVCTXTRDY & (HWREG(ui32Base + AES_O_CTRL))) == 0) + { + } + + // + // Read the tag data. + // + pui32IVData[0] = HWREG((ui32Base + AES_O_IV_IN_0)); + pui32IVData[1] = HWREG((ui32Base + AES_O_IV_IN_1)); + pui32IVData[2] = HWREG((ui32Base + AES_O_IV_IN_2)); + pui32IVData[3] = HWREG((ui32Base + AES_O_IV_IN_3)); +} + +//***************************************************************************** +// +//! Saves the tag registers to a user-defined location. +//! +//! \param ui32Base is the base address of the AES module. +//! \param pui32TagData is pointer to the location that stores the tag data. +//! +//! This function stores the tag data for use authenticated encryption and +//! decryption operations. It is assumed that the AES_CTRL_SAVE_CONTEXT +//! bit is set in the AES_CTRL register. +//! +//! \return None. +// +//***************************************************************************** +void +AESTagRead(uint32_t ui32Base, uint32_t *pui32TagData) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + + // + // Wait for the output context to be ready. + // + while((AES_CTRL_SVCTXTRDY & (HWREG(ui32Base + AES_O_CTRL))) == 0) + { + } + + // + // Read the tag data. + // + pui32TagData[0] = HWREG((ui32Base + AES_O_TAG_OUT_0)); + pui32TagData[1] = HWREG((ui32Base + AES_O_TAG_OUT_1)); + pui32TagData[2] = HWREG((ui32Base + AES_O_TAG_OUT_2)); + pui32TagData[3] = HWREG((ui32Base + AES_O_TAG_OUT_3)); +} + +//***************************************************************************** +// +//! Used to set the write crypto data length in the AES module. +//! +//! \param ui32Base is the base address of the AES module. +//! \param ui64Length is the crypto data length in bytes. +//! +//! This function stores the cryptographic data length in blocks for all modes. +//! Data lengths up to (2^61 - 1) bytes are allowed. For GCM, any value up +//! to (2^36 - 2) bytes are allowed because a 32-bit block counter is used. +//! For basic modes (ECB/CBC/CTR/ICM/CFB128), zero can be programmed into the +//! length field, indicating that the length is infinite. +//! +//! When this function is called, the engine is triggered to start using +//! this context. +//! +//! \note This length does not include the authentication-only data used in +//! some modes. Use the AESAuthLengthSet() function to specify the +//! authentication data length. +//! +//! \return None +// +//***************************************************************************** +void +AESLengthSet(uint32_t ui32Base, uint64_t ui64Length) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + + // + // Write the length register by shifting the 64-bit ui64Length. + // + HWREG(ui32Base + AES_O_C_LENGTH_0) = (uint32_t)(ui64Length); + HWREG(ui32Base + AES_O_C_LENGTH_1) = (uint32_t)(ui64Length >> 32); +} + +//***************************************************************************** +// +//! Sets the authentication data length in the AES module. +//! +//! \param ui32Base is the base address of the AES module. +//! \param ui32Length is the length in bytes. +//! +//! This function is only used to write the authentication data length in the +//! combined modes (GCM or CCM) and XTS mode. Supported AAD lengths for CCM +//! are from 0 to (2^16 - 28) bytes. For GCM, any value up to (2^32 - 1) can +//! be used. For XTS mode, this register is used to load j. Loading of j is +//! only required if j != 0. j represents the sequential number of the 128-bit +//! blocks inside the data unit. Consequently, j must be multiplied by 16 +//! when passed to this function, thereby placing the block number in +//! bits [31:4] of the register. +//! +//! When this function is called, the engine is triggered to start using +//! this context for GCM and CCM. +//! +//! \return None +// +//***************************************************************************** +void +AESAuthLengthSet(uint32_t ui32Base, uint32_t ui32Length) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + + // + // Write the length into the register. + // + HWREG(ui32Base + AES_O_AUTH_LENGTH) = ui32Length; +} + +//***************************************************************************** +// +//! Reads plaintext/ciphertext from data registers without blocking. +//! +//! \param ui32Base is the base address of the AES module. +//! \param pui32Dest is a pointer to an array of words of data. +//! +//! This function reads a block of either plaintext or ciphertext out of the +//! AES module. If the output data is not ready, the function returns +//! false. If the read completed successfully, the function returns true. +//! A block is 16 bytes or 4 words. +//! +//! \return true or false. +// +//***************************************************************************** +bool +AESDataReadNonBlocking(uint32_t ui32Base, uint32_t *pui32Dest) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + + // + // Check if the output is ready before reading the data. If it not ready, + // return false. + // + if((AES_CTRL_OUTPUT_READY & (HWREG(ui32Base + AES_O_CTRL))) == 0) + { + return(false); + } + + // + // Read a block of data from the data registers + // + pui32Dest[0] = HWREG(ui32Base + AES_O_DATA_IN_3); + pui32Dest[1] = HWREG(ui32Base + AES_O_DATA_IN_2); + pui32Dest[2] = HWREG(ui32Base + AES_O_DATA_IN_1); + pui32Dest[3] = HWREG(ui32Base + AES_O_DATA_IN_0); + + // + // Read successful, return true. + // + return(true); +} + +//***************************************************************************** +// +//! Reads plaintext/ciphertext from data registers with blocking. +//! +//! \param ui32Base is the base address of the AES module. +//! \param pui32Dest is a pointer to an array of words. +//! +//! This function reads a block of either plaintext or ciphertext out of the +//! AES module. If the output is not ready, the function waits until it is +//! ready. A block is 16 bytes or 4 words. +//! +//! \return None. +// +//***************************************************************************** +void +AESDataRead(uint32_t ui32Base, uint32_t *pui32Dest) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + + // + // Wait for the output to be ready before reading the data. + // + while((AES_CTRL_OUTPUT_READY & (HWREG(ui32Base + AES_O_CTRL))) == 0) + { + } + + // + // Read a block of data from the data registers + // + pui32Dest[0] = HWREG(ui32Base + AES_O_DATA_IN_3); + pui32Dest[1] = HWREG(ui32Base + AES_O_DATA_IN_2); + pui32Dest[2] = HWREG(ui32Base + AES_O_DATA_IN_1); + pui32Dest[3] = HWREG(ui32Base + AES_O_DATA_IN_0); +} + +//***************************************************************************** +// +//! Writes plaintext/ciphertext to data registers without blocking. +//! +//! \param ui32Base is the base address of the AES module. +//! \param pui32Src is a pointer to an array of words of data. +//! +//! This function writes a block of either plaintext or ciphertext into the +//! AES module. If the input is not ready, the function returns false. If the +//! write completed successfully, the function returns true. A block is 16 +//! bytes or 4 words. +//! +//! \return True or false. +// +//***************************************************************************** +bool +AESDataWriteNonBlocking(uint32_t ui32Base, uint32_t *pui32Src) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + + // + // Check if the input is ready. If not, then return false. + // + if(!(AES_CTRL_INPUT_READY & (HWREG(ui32Base + AES_O_CTRL)))) + { + return(false); + } + + // + // Write a block of data into the data registers. + // + HWREG(ui32Base + AES_O_DATA_IN_3) = pui32Src[0]; + HWREG(ui32Base + AES_O_DATA_IN_2) = pui32Src[1]; + HWREG(ui32Base + AES_O_DATA_IN_1) = pui32Src[2]; + HWREG(ui32Base + AES_O_DATA_IN_0) = pui32Src[3]; + + // + // Write successful, return true. + // + return(true); +} + +//***************************************************************************** +// +//! Writes plaintext/ciphertext to data registers with blocking. +//! +//! \param ui32Base is the base address of the AES module. +//! \param pui32Src is a pointer to an array of bytes. +//! +//! This function writes a block of either plaintext or ciphertext into the +//! AES module. If the input is not ready, the function waits until it is +//! ready before performing the write. A block is 16 bytes or 4 words. +//! +//! \return None. +// +//***************************************************************************** +void +AESDataWrite(uint32_t ui32Base, uint32_t *pui32Src) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + + // + // Wait for input ready. + // + while((AES_CTRL_INPUT_READY & (HWREG(ui32Base + AES_O_CTRL))) == 0) + { + } + + // + // Write a block of data into the data registers. + // + HWREG(ui32Base + AES_O_DATA_IN_3) = pui32Src[0]; + HWREG(ui32Base + AES_O_DATA_IN_2) = pui32Src[1]; + HWREG(ui32Base + AES_O_DATA_IN_1) = pui32Src[2]; + HWREG(ui32Base + AES_O_DATA_IN_0) = pui32Src[3]; +} + +//***************************************************************************** +// +//! Used to process(transform) blocks of data, either encrypt or decrypt it. +//! +//! \param ui32Base is the base address of the AES module. +//! \param pui32Src is a pointer to the memory location where the input data +//! is stored. The data must be padded to the 16-byte boundary. +//! \param pui32Dest is a pointer to the memory location output is written. +//! The space for written data must be rounded up to the 16-byte boundary. +//! \param ui32Length is the length of the cryptographic data in bytes. +//! +//! This function iterates the encryption or decryption mechanism number over +//! the data length. Before calling this function, ensure that the AES +//! module is properly configured the key, data size, mode, etc. Only ECB, +//! CBC, CTR, ICM, CFB, XTS and F8 operating modes should be used. The data +//! is processed in 4-word (16-byte) blocks. +//! +//! \note This function only supports values of \e ui32Length less than 2^32, +//! because the memory size is restricted to between 0 to 2^32 bytes. +//! +//! \return Returns true if data was processed successfully. Returns false +//! if data processing failed. +// +//***************************************************************************** +bool +AESDataProcess(uint32_t ui32Base, uint32_t *pui32Src, uint32_t *pui32Dest, + uint32_t ui32Length) +{ + uint32_t ui32Count; + + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + + // + // Write the length register first, which triggers the engine to start + // using this context. + // + AESLengthSet(AES_BASE, (uint64_t)ui32Length); + + // + // Now loop until the blocks are written. + // + for(ui32Count = 0; ui32Count < ui32Length; ui32Count += 16) + { + // + // Write the data registers. + // + AESDataWrite(ui32Base, pui32Src + (ui32Count / 4)); + + // + // Read the data registers. + // + AESDataRead(ui32Base, pui32Dest + (ui32Count / 4)); + } + + // + // Return true to indicate successful completion of the function. + // + return(true); +} + +//***************************************************************************** +// +//! Used to authenticate blocks of data by generating a hash tag. +//! +//! \param ui32Base is the base address of the AES module. +//! \param pui32Src is a pointer to the memory location where the input data +//! is stored. The data must be padded to the 16-byte boundary. +//! \param ui32Length is the length of the cryptographic data in bytes. +//! \param pui32Tag is a pointer to a 4-word array where the hash tag is +//! written. +//! +//! This function processes data to produce a hash tag that can be used tor +//! authentication. Before calling this function, ensure that the AES +//! module is properly configured the key, data size, mode, etc. Only +//! CBC-MAC and F9 modes should be used. +//! +//! \return Returns true if data was processed successfully. Returns false +//! if data processing failed. +// +//***************************************************************************** +bool +AESDataAuth(uint32_t ui32Base, uint32_t *pui32Src, uint32_t ui32Length, + uint32_t *pui32Tag) +{ + uint32_t ui32Count; + + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + + // + // Write the length register first, which triggers the engine to start + // using this context. + // + AESLengthSet(ui32Base, (uint64_t)ui32Length); + + // + // Now loop until the blocks are written. + // + for(ui32Count = 0; ui32Count < ui32Length; ui32Count += 16) + { + // + // Write the data registers. + // + AESDataWrite(ui32Base, pui32Src + (ui32Count / 4)); + } + + // + // Read the hash tag value. + // + AESTagRead(ui32Base, pui32Tag); + + // + // Return true to indicate successful completion of the function. + // + return(true); +} + +//***************************************************************************** +// +//! Processes and authenticates blocks of data, either encrypt it or decrypts +//! it. +//! +//! \param ui32Base is the base address of the AES module. +//! \param pui32Src is a pointer to the memory location where the input data +//! is stored. The data must be padded to the 16-byte boundary. +//! \param pui32Dest is a pointer to the memory location output is written. +//! The space for written data must be rounded up to the 16-byte boundary. +//! \param ui32Length is the length of the cryptographic data in bytes. +//! \param pui32AuthSrc is a pointer to the memory location where the +//! additional authentication data is stored. The data must be padded to the +//! 16-byte boundary. +//! \param ui32AuthLength is the length of the additional authentication +//! data in bytes. +//! \param pui32Tag is a pointer to a 4-word array where the hash tag is +//! written. +//! +//! This function encrypts or decrypts blocks of data in addition to +//! authentication data. A hash tag is also produced. Before calling this +//! function, ensure that the AES module is properly configured the key, +//! data size, mode, etc. Only CCM and GCM modes should be used. +//! +//! \return Returns true if data was processed successfully. Returns false +//! if data processing failed. +// +//***************************************************************************** +bool +AESDataProcessAuth(uint32_t ui32Base, uint32_t *pui32Src, + uint32_t *pui32Dest, uint32_t ui32Length, + uint32_t *pui32AuthSrc, uint32_t ui32AuthLength, + uint32_t *pui32Tag) +{ + uint32_t ui32Count; + + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + + // + // Set the data length. + // + AESLengthSet(ui32Base, (uint64_t)ui32Length); + + // + // Set the additional authentication data length. + // + AESAuthLengthSet(ui32Base, ui32AuthLength); + + // + // Now loop until the authentication data blocks are written. + // + for(ui32Count = 0; ui32Count < ui32AuthLength; ui32Count += 16) + { + // + // Write the data registers. + // + AESDataWrite(ui32Base, pui32AuthSrc + (ui32Count / 4)); + } + + // + // Now loop until the data blocks are written. + // + for(ui32Count = 0; ui32Count < ui32Length; ui32Count += 16) + { + // + // Write the data registers. + // + AESDataWrite(ui32Base, pui32Src + (ui32Count / 4)); + + // + // + // Read the data registers. + // + AESDataRead(ui32Base, pui32Dest + (ui32Count / 4)); + } + + // + // Read the hash tag value. + // + AESTagRead(ui32Base, pui32Tag); + + // + // Return true to indicate successful completion of the function. + // + return(true); +} + +//***************************************************************************** +// +//! Returns the current AES module interrupt status. +//! +//! \param ui32Base is the base address of the AES module. +//! \param bMasked is \b false if the raw interrupt status is required and +//! \b true if the masked interrupt status is required. +//! +//! \return Returns a bit mask of the interrupt sources, which is a logical OR +//! of any of the following: +//! +//! - \b AES_INT_CONTEXT_IN - Context interrupt +//! - \b AES_INT_CONTEXT_OUT - Authentication tag (and IV) interrupt. +//! - \b AES_INT_DATA_IN - Data input interrupt +//! - \b AES_INT_DATA_OUT - Data output interrupt +//! - \b AES_INT_DMA_CONTEXT_IN - Context DMA done interrupt +//! - \b AES_INT_DMA_CONTEXT_OUT - Authentication tag (and IV) DMA done +//! interrupt +//! - \b AES_INT_DMA_DATA_IN - Data input DMA done interrupt +//! - \b AES_INT_DMA_DATA_OUT - Data output DMA done interrupt +// +//***************************************************************************** +uint32_t +AESIntStatus(uint32_t ui32Base, bool bMasked) +{ + uint32_t ui32Status, ui32Enable, ui32Temp; + + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + + // + // Read the IRQ status register and return the value. + // + ui32Status = HWREG(ui32Base + AES_O_IRQSTATUS); + if(bMasked) + { + ui32Enable = HWREG(ui32Base + AES_O_IRQENABLE); + ui32Temp = HWREG(ui32Base + AES_O_DMAMIS); + return((ui32Status & ui32Enable) | + (((ui32Temp & 0x00000001) << 16) | + ((ui32Temp & 0x00000002) << 18) | + ((ui32Temp & 0x0000000c) << 15))); + } + else + { + ui32Temp = HWREG(ui32Base + AES_O_DMARIS); + return(ui32Status | + (((ui32Temp & 0x00000001) << 16) | + ((ui32Temp & 0x00000002) << 18) | + ((ui32Temp & 0x0000000c) << 15))); + } +} + +//***************************************************************************** +// +//! Enables AES module interrupts. +//! +//! \param ui32Base is the base address of the AES module. +//! \param ui32IntFlags is a bit mask of the interrupt sources to enable. +//! +//! This function enables the interrupts in the AES module. The +//! \e ui32IntFlags parameter is the logical OR of any of the following: +//! +//! - \b AES_INT_CONTEXT_IN - Context interrupt +//! - \b AES_INT_CONTEXT_OUT - Authentication tag (and IV) interrupt +//! - \b AES_INT_DATA_IN - Data input interrupt +//! - \b AES_INT_DATA_OUT - Data output interrupt +//! - \b AES_INT_DMA_CONTEXT_IN - Context DMA done interrupt +//! - \b AES_INT_DMA_CONTEXT_OUT - Authentication tag (and IV) DMA done +//! interrupt +//! - \b AES_INT_DMA_DATA_IN - Data input DMA done interrupt +//! - \b AES_INT_DMA_DATA_OUT - Data output DMA done interrupt +//! +//! \note Interrupts that have been previously been enabled are not disabled +//! when this function is called. +//! +//! \return None. +// +//***************************************************************************** +void +AESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + ASSERT((ui32IntFlags == AES_INT_CONTEXT_IN) || + (ui32IntFlags == AES_INT_CONTEXT_OUT) || + (ui32IntFlags == AES_INT_DATA_IN) || + (ui32IntFlags == AES_INT_DATA_OUT) || + (ui32IntFlags == AES_INT_DMA_CONTEXT_IN) || + (ui32IntFlags == AES_INT_DMA_CONTEXT_OUT) || + (ui32IntFlags == AES_INT_DMA_DATA_IN) || + (ui32IntFlags == AES_INT_DMA_DATA_OUT)); + + // + // Set the flags. + // + HWREG(ui32Base + AES_O_DMAIM) |= (((ui32IntFlags & 0x00010000) >> 16) | + ((ui32IntFlags & 0x00060000) >> 15) | + ((ui32IntFlags & 0x00080000) >> 18)); + HWREG(ui32Base + AES_O_IRQENABLE) |= ui32IntFlags & 0x0000ffff; +} + +//***************************************************************************** +// +//! Disables AES module interrupts. +//! +//! \param ui32Base is the base address of the AES module. +//! \param ui32IntFlags is a bit mask of the interrupt sources to disable. +//! +//! This function disables the interrupt sources in the AES module. The +//! \e ui32IntFlags parameter is the logical OR of any of the following: +//! +//! - \b AES_INT_CONTEXT_IN - Context interrupt +//! - \b AES_INT_CONTEXT_OUT - Authentication tag (and IV) interrupt +//! - \b AES_INT_DATA_IN - Data input interrupt +//! - \b AES_INT_DATA_OUT - Data output interrupt +//! - \b AES_INT_DMA_CONTEXT_IN - Context DMA done interrupt +//! - \b AES_INT_DMA_CONTEXT_OUT - Authentication tag (and IV) DMA done +//! interrupt +//! - \b AES_INT_DMA_DATA_IN - Data input DMA done interrupt +//! - \b AES_INT_DMA_DATA_OUT - Data output DMA done interrupt +//! +//! \note The DMA done interrupts are the only interrupts that can be cleared. +//! The remaining interrupts can be disabled instead using AESIntDisable(). +//! +//! \return None. +// +//***************************************************************************** +void +AESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + ASSERT((ui32IntFlags == AES_INT_CONTEXT_IN) || + (ui32IntFlags == AES_INT_CONTEXT_OUT) || + (ui32IntFlags == AES_INT_DATA_IN) || + (ui32IntFlags == AES_INT_DATA_OUT) || + (ui32IntFlags == AES_INT_DMA_CONTEXT_IN) || + (ui32IntFlags == AES_INT_DMA_CONTEXT_OUT) || + (ui32IntFlags == AES_INT_DMA_DATA_IN) || + (ui32IntFlags == AES_INT_DMA_DATA_OUT)); + + // + // Clear the flags. + // + HWREG(ui32Base + AES_O_DMAIM) &= ~(((ui32IntFlags & 0x00010000) >> 16) | + ((ui32IntFlags & 0x00060000) >> 15) | + ((ui32IntFlags & 0x00080000) >> 18)); + HWREG(ui32Base + AES_O_IRQENABLE) &= ~(ui32IntFlags & 0x0000ffff); +} + +//***************************************************************************** +// +//! Clears AES module interrupts. +//! +//! \param ui32Base is the base address of the AES module. +//! \param ui32IntFlags is a bit mask of the interrupt sources to disable. +//! +//! This function clears the interrupt sources in the AES module. The +//! \e ui32IntFlags parameter is the logical OR of any of the following: +//! +//! - \b AES_INT_DMA_CONTEXT_IN - Context DMA done interrupt +//! - \b AES_INT_DMA_CONTEXT_OUT - Authentication tag (and IV) DMA done +//! interrupt +//! - \b AES_INT_DMA_DATA_IN - Data input DMA done interrupt +//! - \b AES_INT_DMA_DATA_OUT - Data output DMA done interrupt +//! +//! \note Only the DMA done interrupts can be cleared. The remaining +//! interrupts should be disabled with AESIntDisable(). +//! +//! \return None. +// +//***************************************************************************** +void +AESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + ASSERT((ui32IntFlags == AES_INT_DMA_CONTEXT_IN) || + (ui32IntFlags == AES_INT_DMA_CONTEXT_OUT) || + (ui32IntFlags == AES_INT_DMA_DATA_IN) || + (ui32IntFlags == AES_INT_DMA_DATA_OUT)); + + HWREG(ui32Base + AES_O_DMAIC) = (((ui32IntFlags & 0x00010000) >> 16) | + ((ui32IntFlags & 0x00060000) >> 15) | + ((ui32IntFlags & 0x00080000) >> 18)); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the AES module. +//! +//! \param ui32Base is the base address of the AES module. +//! \param pfnHandler is a pointer to the function to be called when the +//! enabled AES interrupts occur. +//! +//! This function registers the interrupt handler in the interrupt vector +//! table, and enables AES interrupts on the interrupt controller; specific AES +//! interrupt sources must be enabled using AESIntEnable(). The interrupt +//! handler being registered must clear the source of the interrupt using +//! AESIntClear(). +//! +//! If the application is using a static interrupt vector table stored in +//! flash, then it is not necessary to register the interrupt handler this way. +//! Instead, IntEnable() is used to enable AES interrupts on the +//! interrupt controller. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +AESIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + + // + // Register the interrupt handler. + // + IntRegister(INT_AES0_TM4C129, pfnHandler); + + // + // Enable the interrupt + // + IntEnable(INT_AES0_TM4C129); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the AES module. +//! +//! \param ui32Base is the base address of the AES module. +//! +//! This function unregisters the previously registered interrupt handler and +//! disables the interrupt in the interrupt controller. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +AESIntUnregister(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + + // + // Disable the interrupt. + // + IntDisable(INT_AES0_TM4C129); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_AES0_TM4C129); +} + +//***************************************************************************** +// +//! Enables uDMA requests for the AES module. +//! +//! \param ui32Base is the base address of the AES module. +//! \param ui32Flags is a bit mask of the uDMA requests to be enabled. +//! +//! This function enables the uDMA request sources in the AES module. +//! The \e ui32Flags parameter is the logical OR of any of the following: +//! +//! - \b AES_DMA_DATA_IN +//! - \b AES_DMA_DATA_OUT +//! - \b AES_DMA_CONTEXT_IN +//! - \b AES_DMA_CONTEXT_OUT +//! +//! \return None. +// +//***************************************************************************** +void +AESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + ASSERT((ui32Flags == AES_DMA_DATA_IN) || + (ui32Flags == AES_DMA_DATA_OUT) || + (ui32Flags == AES_DMA_CONTEXT_IN) || + (ui32Flags == AES_DMA_CONTEXT_OUT)); + + // + // Set the flags in the current register value. + // + HWREG(ui32Base + AES_O_SYSCONFIG) |= ui32Flags; +} + +//***************************************************************************** +// +//! Disables uDMA requests for the AES module. +//! +//! \param ui32Base is the base address of the AES module. +//! \param ui32Flags is a bit mask of the uDMA requests to be disabled. +//! +//! This function disables the uDMA request sources in the AES module. +//! The \e ui32Flags parameter is the logical OR of any of the +//! following: +//! +//! - \b AES_DMA_DATA_IN +//! - \b AES_DMA_DATA_OUT +//! - \b AES_DMA_CONTEXT_IN +//! - \b AES_DMA_CONTEXT_OUT +//! +//! \return None. +// +//***************************************************************************** +void +AESDMADisable(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + ASSERT((ui32Flags == AES_DMA_DATA_IN) || + (ui32Flags == AES_DMA_DATA_OUT) || + (ui32Flags == AES_DMA_CONTEXT_IN) || + (ui32Flags == AES_DMA_CONTEXT_OUT)); + + // + // Clear the flags in the current register value. + // + HWREG(ui32Base + AES_O_SYSCONFIG) &= ~ui32Flags; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/can.c b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/can.c new file mode 100644 index 0000000000000000000000000000000000000000..d53584585c4ceb31c5b7c3afbf6279f402ccda94 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/can.c @@ -0,0 +1,2117 @@ +//***************************************************************************** +// +// can.c - Driver for the CAN module. +// +// Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup can_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_can.h" +#include "inc/hw_ints.h" +#include "inc/hw_nvic.h" +#include "inc/hw_memmap.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" +#include "driverlib/can.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" + +//***************************************************************************** +// +// This is the maximum number that can be stored as an 11bit Message +// identifier. +// +//***************************************************************************** +#define CAN_MAX_11BIT_MSG_ID 0x7ff + +//***************************************************************************** +// +// The maximum CAN bit timing divisor is 19. +// +//***************************************************************************** +#define CAN_MAX_BIT_DIVISOR 19 + +//***************************************************************************** +// +// The minimum CAN bit timing divisor is 4. +// +//***************************************************************************** +#define CAN_MIN_BIT_DIVISOR 4 + +//***************************************************************************** +// +// The maximum CAN pre-divisor is 1024. +// +//***************************************************************************** +#define CAN_MAX_PRE_DIVISOR 1024 + +//***************************************************************************** +// +// The minimum CAN pre-divisor is 1. +// +//***************************************************************************** +#define CAN_MIN_PRE_DIVISOR 1 + +//***************************************************************************** +// +// Converts a set of CAN bit timing values into the value that needs to be +// programmed into the CAN_BIT register to achieve those timings. +// +//***************************************************************************** +#define CAN_BIT_VALUE(seg1, seg2, sjw) \ + ((((seg1 - 1) << CAN_BIT_TSEG1_S) & \ + CAN_BIT_TSEG1_M) | \ + (((seg2 - 1) << CAN_BIT_TSEG2_S) & \ + CAN_BIT_TSEG2_M) | \ + (((sjw - 1) << CAN_BIT_SJW_S) & \ + CAN_BIT_SJW_M)) + +//***************************************************************************** +// +// This table is used by the CANBitRateSet() API as the register defaults for +// the bit timing values. +// +//***************************************************************************** +static const uint16_t g_ui16CANBitValues[] = +{ + CAN_BIT_VALUE(2, 1, 1), // 4 clocks/bit + CAN_BIT_VALUE(3, 1, 1), // 5 clocks/bit + CAN_BIT_VALUE(3, 2, 2), // 6 clocks/bit + CAN_BIT_VALUE(4, 2, 2), // 7 clocks/bit + CAN_BIT_VALUE(4, 3, 3), // 8 clocks/bit + CAN_BIT_VALUE(5, 3, 3), // 9 clocks/bit + CAN_BIT_VALUE(5, 4, 4), // 10 clocks/bit + CAN_BIT_VALUE(6, 4, 4), // 11 clocks/bit + CAN_BIT_VALUE(6, 5, 4), // 12 clocks/bit + CAN_BIT_VALUE(7, 5, 4), // 13 clocks/bit + CAN_BIT_VALUE(7, 6, 4), // 14 clocks/bit + CAN_BIT_VALUE(8, 6, 4), // 15 clocks/bit + CAN_BIT_VALUE(8, 7, 4), // 16 clocks/bit + CAN_BIT_VALUE(9, 7, 4), // 17 clocks/bit + CAN_BIT_VALUE(9, 8, 4), // 18 clocks/bit + CAN_BIT_VALUE(10, 8, 4) // 19 clocks/bit +}; + +//***************************************************************************** +// +//! \internal +//! Checks a CAN base address. +//! +//! \param ui32Base is the base address of the CAN controller. +//! +//! This function determines if a CAN controller base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static bool +_CANBaseValid(uint32_t ui32Base) +{ + return((ui32Base == CAN0_BASE) || (ui32Base == CAN1_BASE)); +} +#endif + +//***************************************************************************** +// +//! Returns the CAN controller interrupt number. +//! +//! \param ui32Base is the base address of the selected CAN controller +//! +//! This function returns the interrupt number for the CAN module with the base +//! address passed in the \e ui32Base parameter. +//! +//! \return Returns a CAN interrupt number or 0 if the interrupt does not +//! exist. +// +//***************************************************************************** +static uint_fast8_t +_CANIntNumberGet(uint32_t ui32Base) +{ + uint_fast8_t ui8Int; + + ASSERT((ui32Base == CAN0_BASE) || (ui32Base == CAN1_BASE)); + + ui8Int = 0; + + // + // Find the valid interrupt number for this CAN controller. + // + if(CLASS_IS_TM4C123) + { + if(ui32Base == CAN0_BASE) + { + ui8Int = INT_CAN0_TM4C123; + } + else if(ui32Base == CAN1_BASE) + { + ui8Int = INT_CAN1_TM4C123; + } + } + else if(CLASS_IS_TM4C129) + { + if(ui32Base == CAN0_BASE) + { + ui8Int = INT_CAN0_TM4C129; + } + else if(ui32Base == CAN1_BASE) + { + ui8Int = INT_CAN1_TM4C129; + } + } + + return(ui8Int); +} + +//***************************************************************************** +// +//! \internal +//! Copies data from a buffer to the CAN Data registers. +//! +//! \param pui8Data is a pointer to the data to be written out to the CAN +//! controller's data registers. +//! \param pui32Register is an uint32_t pointer to the first register of the +//! CAN controller's data registers. For example, in order to use the IF1 +//! register set on CAN controller 0, the value would be: \b CAN0_BASE \b + +//! \b CAN_O_IF1DA1. +//! \param iSize is the number of bytes to copy into the CAN controller. +//! +//! This function takes the steps necessary to copy data from a contiguous +//! buffer in memory into the non-contiguous data registers used by the CAN +//! controller. This function is rarely used outside of the CANMessageSet() +//! function. +//! +//! \return None. +// +//***************************************************************************** +static void +_CANDataRegWrite(uint8_t *pui8Data, uint32_t *pui32Register, uint32_t ui32Size) +{ + uint32_t ui32Idx, ui32Value; + + // + // Loop always copies 1 or 2 bytes per iteration. + // + for(ui32Idx = 0; ui32Idx < ui32Size; ) + { + // + // Write out the data 16 bits at a time since this is how the registers + // are aligned in memory. + // + ui32Value = pui8Data[ui32Idx++]; + + // + // Only write the second byte if needed otherwise the value is zero. + // + if(ui32Idx < ui32Size) + { + ui32Value |= (pui8Data[ui32Idx++] << 8); + } + + HWREG(pui32Register++) = ui32Value; + } +} + +//***************************************************************************** +// +//! \internal +//! Copies data from a buffer to the CAN Data registers. +//! +//! \param pui8Data is a pointer to the location to store the data read from +//! the CAN controller's data registers. +//! \param pui32Register is an uint32_t pointer to the first register of the +//! CAN controller's data registers. For example, in order to use the IF1 +//! register set on CAN controller 1, the value would be: \b CAN0_BASE \b + +//! \b CAN_O_IF1DA1. +//! \param iSize is the number of bytes to copy from the CAN controller. +//! +//! This function takes the steps necessary to copy data to a contiguous buffer +//! in memory from the non-contiguous data registers used by the CAN +//! controller. This function is rarely used outside of the CANMessageGet() +//! function. +//! +//! \return None. +// +//***************************************************************************** +static void +_CANDataRegRead(uint8_t *pui8Data, uint32_t *pui32Register, uint32_t ui32Size) +{ + uint32_t ui32Idx, ui32Value; + + // + // Loop always copies 1 or 2 bytes per iteration. + // + for(ui32Idx = 0; ui32Idx < ui32Size; ) + { + // + // Read out the data 16 bits at a time since this is how the registers + // are aligned in memory. + // + ui32Value = HWREG(pui32Register++); + + // + // Store the first byte. + // + pui8Data[ui32Idx++] = (uint8_t)ui32Value; + + // + // Only read the second byte if needed. + // + if(ui32Idx < ui32Size) + { + pui8Data[ui32Idx++] = (uint8_t)(ui32Value >> 8); + } + } +} + +//***************************************************************************** +// +//! Initializes the CAN controller after reset. +//! +//! \param ui32Base is the base address of the CAN controller. +//! +//! After reset, the CAN controller is left in the disabled state. However, +//! the memory used for message objects contains undefined values and must be +//! cleared prior to enabling the CAN controller the first time. This prevents +//! unwanted transmission or reception of data before the message objects are +//! configured. This function must be called before enabling the controller +//! the first time. +//! +//! \return None. +// +//***************************************************************************** +void +CANInit(uint32_t ui32Base) +{ + uint32_t ui32Msg; + + // + // Check the arguments. + // + ASSERT(_CANBaseValid(ui32Base)); + + // + // Place CAN controller in init state, regardless of previous state. This + // puts controller in idle, and allow the message object RAM to be + // programmed. + // + HWREG(ui32Base + CAN_O_CTL) = CAN_CTL_INIT; + + // + // Wait for busy bit to clear + // + while(HWREG(ui32Base + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY) + { + } + + // + // Clear the message value bit in the arbitration register. This indicates + // the message is not valid and is a "safe" condition to leave the message + // object. The same arb reg is used to program all the message objects. + // + HWREG(ui32Base + CAN_O_IF1CMSK) = (CAN_IF1CMSK_WRNRD | CAN_IF1CMSK_ARB | + CAN_IF1CMSK_CONTROL); + HWREG(ui32Base + CAN_O_IF1ARB2) = 0; + HWREG(ui32Base + CAN_O_IF1MCTL) = 0; + + // + // Loop through to program all 32 message objects + // + for(ui32Msg = 1; ui32Msg <= 32; ui32Msg++) + { + // + // Wait for busy bit to clear + // + while(HWREG(ui32Base + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY) + { + } + + // + // Initiate programming the message object + // + HWREG(ui32Base + CAN_O_IF1CRQ) = ui32Msg; + } + + // + // Make sure that the interrupt and new data flags are updated for the + // message objects. + // + HWREG(ui32Base + CAN_O_IF1CMSK) = (CAN_IF1CMSK_NEWDAT | + CAN_IF1CMSK_CLRINTPND); + + // + // Loop through to program all 32 message objects + // + for(ui32Msg = 1; ui32Msg <= 32; ui32Msg++) + { + // + // Wait for busy bit to clear. + // + while(HWREG(ui32Base + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY) + { + } + + // + // Initiate programming the message object + // + HWREG(ui32Base + CAN_O_IF1CRQ) = ui32Msg; + } + + // + // Acknowledge any pending status interrupts. + // + HWREG(ui32Base + CAN_O_STS); +} + +//***************************************************************************** +// +//! Enables the CAN controller. +//! +//! \param ui32Base is the base address of the CAN controller to enable. +//! +//! Enables the CAN controller for message processing. Once enabled, the +//! controller automatically transmits any pending frames, and processes any +//! received frames. The controller can be stopped by calling CANDisable(). +//! Prior to calling CANEnable(), CANInit() must have been called to +//! initialize the controller and the CAN bus clock must be configured by +//! calling CANBitTimingSet(). +//! +//! \return None. +// +//***************************************************************************** +void +CANEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_CANBaseValid(ui32Base)); + + // + // Clear the init bit in the control register. + // + HWREG(ui32Base + CAN_O_CTL) &= ~CAN_CTL_INIT; +} + +//***************************************************************************** +// +//! Disables the CAN controller. +//! +//! \param ui32Base is the base address of the CAN controller to disable. +//! +//! Disables the CAN controller for message processing. When disabled, the +//! controller no longer automatically processes data on the CAN bus. The +//! controller can be restarted by calling CANEnable(). The state of the CAN +//! controller and the message objects in the controller are left as they were +//! before this call was made. +//! +//! \return None. +// +//***************************************************************************** +void +CANDisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_CANBaseValid(ui32Base)); + + // + // Set the init bit in the control register. + // + HWREG(ui32Base + CAN_O_CTL) |= CAN_CTL_INIT; +} + +//***************************************************************************** +// +//! Reads the current settings for the CAN controller bit timing. +//! +//! \param ui32Base is the base address of the CAN controller. +//! \param psClkParms is a pointer to a structure to hold the timing +//! parameters. +//! +//! This function reads the current configuration of the CAN controller bit +//! clock timing and stores the resulting information in the structure +//! supplied by the caller. Refer to CANBitTimingSet() for the meaning of the +//! values that are returned in the structure pointed to by \e psClkParms. +//! +//! \return None. +// +//***************************************************************************** +void +CANBitTimingGet(uint32_t ui32Base, tCANBitClkParms *psClkParms) +{ + uint32_t ui32BitReg; + + // + // Check the arguments. + // + ASSERT(_CANBaseValid(ui32Base)); + ASSERT(psClkParms); + + // + // Read out all the bit timing values from the CAN controller registers. + // + ui32BitReg = HWREG(ui32Base + CAN_O_BIT); + + // + // Set the phase 2 segment. + // + psClkParms->ui32Phase2Seg = + ((ui32BitReg & CAN_BIT_TSEG2_M) >> CAN_BIT_TSEG2_S) + 1; + + // + // Set the phase 1 segment. + // + psClkParms->ui32SyncPropPhase1Seg = + ((ui32BitReg & CAN_BIT_TSEG1_M) >> CAN_BIT_TSEG1_S) + 1; + + // + // Set the synchronous jump width. + // + psClkParms->ui32SJW = ((ui32BitReg & CAN_BIT_SJW_M) >> CAN_BIT_SJW_S) + 1; + + // + // Set the pre-divider for the CAN bus bit clock. + // + psClkParms->ui32QuantumPrescaler = + ((ui32BitReg & CAN_BIT_BRP_M) | + ((HWREG(ui32Base + CAN_O_BRPE) & CAN_BRPE_BRPE_M) << 6)) + 1; +} + +//***************************************************************************** +// +//! Sets the CAN bit timing values to a nominal setting based on a desired +//! bit rate. +//! +//! \param ui32Base is the base address of the CAN controller. +//! \param ui32SourceClock is the system clock for the device in Hz. +//! \param ui32BitRate is the desired bit rate. +//! +//! This function sets the CAN bit timing for the bit rate passed in the +//! \e ui32BitRate parameter based on the \e ui32SourceClock parameter. +//! Because the CAN clock is based off of the system clock, the calling +//! function must pass in the source clock rate either by retrieving it from +//! SysCtlClockGet() or using a specific value in Hz. The CAN bit timing is +//! calculated assuming a minimal amount of propagation delay, which works for +//! most cases where the network length is short. If tighter timing +//! requirements or longer network lengths are needed, then the +//! CANBitTimingSet() function is available for full customization of all of +//! the CAN bit timing values. Because not all bit rates can be matched +//! exactly, the bit rate is set to the value closest to the desired bit rate +//! without being higher than the \e ui32BitRate value. +//! +//! \note On some devices the source clock is fixed at 8MHz so the +//! \e ui32SourceClock must be set to 8000000. +//! +//! \return This function returns the bit rate that the CAN controller was +//! configured to use or it returns 0 to indicate that the bit rate was not +//! changed because the requested bit rate was not valid. +//! +//***************************************************************************** +uint32_t +CANBitRateSet(uint32_t ui32Base, uint32_t ui32SourceClock, + uint32_t ui32BitRate) +{ + uint32_t ui32DesiredRatio; + uint32_t ui32CANBits; + uint32_t ui32PreDivide; + uint32_t ui32RegValue; + uint16_t ui16CANCTL; + + // + // Check the arguments. + // + ASSERT(_CANBaseValid(ui32Base)); + ASSERT(ui32SourceClock); + ASSERT(ui32BitRate); + + // + // Calculate the desired clock rate. + // + ui32DesiredRatio = ui32SourceClock / ui32BitRate; + + // + // Make sure that the ratio of CAN bit rate to processor clock is not too + // small or too large. + // + ASSERT(ui32DesiredRatio <= (CAN_MAX_PRE_DIVISOR * CAN_MAX_BIT_DIVISOR)); + ASSERT(ui32DesiredRatio >= (CAN_MIN_PRE_DIVISOR * CAN_MIN_BIT_DIVISOR)); + + // + // Make sure that the Desired Ratio is not too large. This enforces the + // requirement that the bit rate is larger than requested. + // + if((ui32SourceClock / ui32DesiredRatio) > ui32BitRate) + { + ui32DesiredRatio += 1; + } + + // + // Check all possible values to find a matching value. + // + while(ui32DesiredRatio <= (CAN_MAX_PRE_DIVISOR * CAN_MAX_BIT_DIVISOR)) + { + // + // Loop through all possible CAN bit divisors. + // + for(ui32CANBits = CAN_MAX_BIT_DIVISOR; + ui32CANBits >= CAN_MIN_BIT_DIVISOR; ui32CANBits--) + { + // + // For a given CAN bit divisor save the pre divisor. + // + ui32PreDivide = ui32DesiredRatio / ui32CANBits; + + // + // If the calculated divisors match the desired clock ratio then + // return these bit rate and set the CAN bit timing. + // + if((ui32PreDivide * ui32CANBits) == ui32DesiredRatio) + { + // + // Start building the bit timing value by adding the bit timing + // in time quanta. + // + ui32RegValue = g_ui16CANBitValues[ui32CANBits - + CAN_MIN_BIT_DIVISOR]; + + // + // To set the bit timing register, the controller must be + // placed in init mode (if not already), and also configuration + // change bit enabled. The state of the register must be + // saved so it can be restored. + // + ui16CANCTL = HWREG(ui32Base + CAN_O_CTL); + HWREG(ui32Base + CAN_O_CTL) = ui16CANCTL | CAN_CTL_INIT | + CAN_CTL_CCE; + + // + // Now add in the pre-scalar on the bit rate. + // + ui32RegValue |= ((ui32PreDivide - 1) & CAN_BIT_BRP_M); + + // + // Set the clock bits in the and the lower bits of the + // pre-scalar. + // + HWREG(ui32Base + CAN_O_BIT) = ui32RegValue; + + // + // Set the divider upper bits in the extension register. + // + HWREG(ui32Base + CAN_O_BRPE) = ((ui32PreDivide - 1) >> 6) & + CAN_BRPE_BRPE_M; + + // + // Restore the saved CAN Control register. + // + HWREG(ui32Base + CAN_O_CTL) = ui16CANCTL; + + // + // Return the computed bit rate. + // + return(ui32SourceClock / (ui32PreDivide * ui32CANBits)); + } + } + + // + // Move the divisor up one and look again. Only in rare cases are + // more than 2 loops required to find the value. + // + ui32DesiredRatio++; + } + + // + // A valid combination could not be found, so return 0 to indicate that the + // bit rate was not changed. + // + return(0); +} + +//***************************************************************************** +// +//! Configures the CAN controller bit timing. +//! +//! \param ui32Base is the base address of the CAN controller. +//! \param psClkParms points to the structure with the clock parameters. +//! +//! Configures the various timing parameters for the CAN bus bit timing: +//! Propagation segment, Phase Buffer 1 segment, Phase Buffer 2 segment, and +//! the Synchronization Jump Width. The values for Propagation and Phase +//! Buffer 1 segments are derived from the combination +//! \e psClkParms->ui32SyncPropPhase1Seg parameter. Phase Buffer 2 is +//! determined from the \e psClkParms->ui32Phase2Seg parameter. These two +//! parameters, along with \e psClkParms->ui32SJW are based in units of bit +//! time quanta. The actual quantum time is determined by the +//! \e psClkParms->ui32QuantumPrescaler value, which specifies the divisor for +//! the CAN module clock. +//! +//! The total bit time, in quanta, is the sum of the two Seg parameters, +//! as follows: +//! +//! bit_time_q = ui32SyncPropPhase1Seg + ui32Phase2Seg + 1 +//! +//! Note that the Sync_Seg is always one quantum in duration, and is added +//! to derive the correct duration of Prop_Seg and Phase1_Seg. +//! +//! The equation to determine the actual bit rate is as follows: +//! +//! CAN Clock / +//! ((\e ui32SyncPropPhase1Seg + \e ui32Phase2Seg + 1) * +//! (\e ui32QuantumPrescaler)) +//! +//! Thus with \e ui32SyncPropPhase1Seg = 4, \e ui32Phase2Seg = 1, +//! \e ui32QuantumPrescaler = 2 and an 8 MHz CAN clock, the bit rate is +//! (8 MHz) / ((5 + 2 + 1) * 2) or 500 Kbit/sec. +//! +//! \return None. +// +//***************************************************************************** +void +CANBitTimingSet(uint32_t ui32Base, tCANBitClkParms *psClkParms) +{ + uint32_t ui32BitReg, ui32SavedInit; + + // + // Check the arguments. + // + ASSERT(_CANBaseValid(ui32Base)); + ASSERT(psClkParms); + + // + // The phase 1 segment must be in the range from 2 to 16. + // + ASSERT((psClkParms->ui32SyncPropPhase1Seg >= 2) && + (psClkParms->ui32SyncPropPhase1Seg <= 16)); + + // + // The phase 2 segment must be in the range from 1 to 8. + // + ASSERT((psClkParms->ui32Phase2Seg >= 1) && + (psClkParms->ui32Phase2Seg <= 8)); + + // + // The synchronous jump windows must be in the range from 1 to 4. + // + ASSERT((psClkParms->ui32SJW >= 1) && (psClkParms->ui32SJW <= 4)); + + // + // The CAN clock pre-divider must be in the range from 1 to 1024. + // + ASSERT((psClkParms->ui32QuantumPrescaler <= 1024) && + (psClkParms->ui32QuantumPrescaler >= 1)); + + // + // To set the bit timing register, the controller must be placed in init + // mode (if not already), and also configuration change bit enabled. State + // of the init bit must be saved so it can be restored at the end. + // + ui32SavedInit = HWREG(ui32Base + CAN_O_CTL); + HWREG(ui32Base + CAN_O_CTL) = ui32SavedInit | CAN_CTL_INIT | CAN_CTL_CCE; + + // + // Set the bit fields of the bit timing register according to the parms. + // + ui32BitReg = (((psClkParms->ui32Phase2Seg - 1) << CAN_BIT_TSEG2_S) & + CAN_BIT_TSEG2_M); + ui32BitReg |= (((psClkParms->ui32SyncPropPhase1Seg - 1) << + CAN_BIT_TSEG1_S) & CAN_BIT_TSEG1_M); + ui32BitReg |= ((psClkParms->ui32SJW - 1) << CAN_BIT_SJW_S) & CAN_BIT_SJW_M; + ui32BitReg |= (psClkParms->ui32QuantumPrescaler - 1) & CAN_BIT_BRP_M; + HWREG(ui32Base + CAN_O_BIT) = ui32BitReg; + + // + // Set the divider upper bits in the extension register. + // + HWREG(ui32Base + CAN_O_BRPE) = + ((psClkParms->ui32QuantumPrescaler - 1) >> 6) & CAN_BRPE_BRPE_M; + + // + // Clear the config change bit, and restore the init bit. + // + ui32SavedInit &= ~CAN_CTL_CCE; + + // + // If Init was not set before, then clear it. + // + if(ui32SavedInit & CAN_CTL_INIT) + { + ui32SavedInit &= ~CAN_CTL_INIT; + } + + HWREG(ui32Base + CAN_O_CTL) = ui32SavedInit; +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the CAN controller. +//! +//! \param ui32Base is the base address of the CAN controller. +//! \param pfnHandler is a pointer to the function to be called when the +//! enabled CAN interrupts occur. +//! +//! This function registers the interrupt handler in the interrupt vector +//! table, and enables CAN interrupts on the interrupt controller; specific CAN +//! interrupt sources must be enabled using CANIntEnable(). The interrupt +//! handler being registered must clear the source of the interrupt using +//! CANIntClear(). +//! +//! If the application is using a static interrupt vector table stored in +//! flash, then it is not necessary to register the interrupt handler this way. +//! Instead, IntEnable() is used to enable CAN interrupts on the +//! interrupt controller. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +CANIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) +{ + uint_fast8_t ui8IntNumber; + + // + // Check the arguments. + // + ASSERT(_CANBaseValid(ui32Base)); + + // + // Get the actual interrupt number for this CAN controller. + // + ui8IntNumber = _CANIntNumberGet(ui32Base); + ASSERT(ui8IntNumber != 0); + + // + // Register the interrupt handler. + // + IntRegister(ui8IntNumber, pfnHandler); + + // + // Enable the Ethernet interrupt. + // + IntEnable(ui8IntNumber); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the CAN controller. +//! +//! \param ui32Base is the base address of the controller. +//! +//! This function unregisters the previously registered interrupt handler and +//! disables the interrupt in the interrupt controller. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +CANIntUnregister(uint32_t ui32Base) +{ + uint_fast8_t ui8IntNumber; + + // + // Check the arguments. + // + ASSERT(_CANBaseValid(ui32Base)); + + // + // Get the actual interrupt number for this CAN controller. + // + ui8IntNumber = _CANIntNumberGet(ui32Base); + ASSERT(ui8IntNumber != 0); + + // + // Disable the CAN interrupt. + // + IntDisable(ui8IntNumber); + + // + // Register the interrupt handler. + // + IntUnregister(ui8IntNumber); +} + +//***************************************************************************** +// +//! Enables individual CAN controller interrupt sources. +//! +//! \param ui32Base is the base address of the CAN controller. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! This function enables specific interrupt sources of the CAN controller. +//! Only enabled sources cause a processor interrupt. +//! +//! The \e ui32IntFlags parameter is the logical OR of any of the following: +//! +//! - \b CAN_INT_ERROR - a controller error condition has occurred +//! - \b CAN_INT_STATUS - a message transfer has completed, or a bus error has +//! been detected +//! - \b CAN_INT_MASTER - allow CAN controller to generate interrupts +//! +//! In order to generate any interrupts, \b CAN_INT_MASTER must be enabled. +//! Further, for any particular transaction from a message object to generate +//! an interrupt, that message object must have interrupts enabled (see +//! CANMessageSet()). \b CAN_INT_ERROR generates an interrupt if the +//! controller enters the ``bus off'' condition, or if the error counters reach +//! a limit. \b CAN_INT_STATUS generates an interrupt under quite a few +//! status conditions and may provide more interrupts than the application +//! needs to handle. When an interrupt occurs, use CANIntStatus() to determine +//! the cause. +//! +//! \return None. +// +//***************************************************************************** +void +CANIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(_CANBaseValid(ui32Base)); + ASSERT((ui32IntFlags & ~(CAN_CTL_EIE | CAN_CTL_SIE | CAN_CTL_IE)) == 0); + + // + // Enable the specified interrupts. + // + HWREG(ui32Base + CAN_O_CTL) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! Disables individual CAN controller interrupt sources. +//! +//! \param ui32Base is the base address of the CAN controller. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be +//! disabled. +//! +//! Disables the specified CAN controller interrupt sources. Only enabled +//! interrupt sources can cause a processor interrupt. +//! +//! The \e ui32IntFlags parameter has the same definition as in the +//! CANIntEnable() function. +//! +//! \return None. +// +//***************************************************************************** +void +CANIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(_CANBaseValid(ui32Base)); + ASSERT((ui32IntFlags & ~(CAN_CTL_EIE | CAN_CTL_SIE | CAN_CTL_IE)) == 0); + + // + // Disable the specified interrupts. + // + HWREG(ui32Base + CAN_O_CTL) &= ~ui32IntFlags; +} + +//***************************************************************************** +// +//! Returns the current CAN controller interrupt status. +//! +//! \param ui32Base is the base address of the CAN controller. +//! \param eIntStsReg indicates which interrupt status register to read +//! +//! This function returns the value of one of two interrupt status registers. +//! The interrupt status register read is determined by the \e eIntStsReg +//! parameter, which can have one of the following values: +//! +//! - \b CAN_INT_STS_CAUSE - indicates the cause of the interrupt +//! - \b CAN_INT_STS_OBJECT - indicates pending interrupts of all message +//! objects +//! +//! \b CAN_INT_STS_CAUSE returns the value of the controller interrupt register +//! and indicates the cause of the interrupt. The value returned is +//! \b CAN_INT_INTID_STATUS if the cause is a status interrupt. In this case, +//! the status register is read with the CANStatusGet() function. +//! Calling this function to read the status also clears the status +//! interrupt. If the value of the interrupt register is in the range 1-32, +//! then this indicates the number of the highest priority message object that +//! has an interrupt pending. The message object interrupt can be cleared by +//! using the CANIntClear() function, or by reading the message using +//! CANMessageGet() in the case of a received message. The interrupt handler +//! can read the interrupt status again to make sure all pending interrupts are +//! cleared before returning from the interrupt. +//! +//! \b CAN_INT_STS_OBJECT returns a bit mask indicating which message objects +//! have pending interrupts. This value can be used to discover all of the +//! pending interrupts at once, as opposed to repeatedly reading the interrupt +//! register by using \b CAN_INT_STS_CAUSE. +//! +//! \return Returns the value of one of the interrupt status registers. +// +//***************************************************************************** +uint32_t +CANIntStatus(uint32_t ui32Base, tCANIntStsReg eIntStsReg) +{ + uint32_t ui32Status; + + // + // Check the arguments. + // + ASSERT(_CANBaseValid(ui32Base)); + + // + // See which status the caller is looking for. + // + switch(eIntStsReg) + { + // + // The caller wants the global interrupt status for the CAN controller + // specified by ui32Base. + // + case CAN_INT_STS_CAUSE: + { + ui32Status = HWREG(ui32Base + CAN_O_INT); + break; + } + + // + // The caller wants the current message status interrupt for all + // messages. + // + case CAN_INT_STS_OBJECT: + { + // + // Read and combine both 16 bit values into one 32bit status. + // + ui32Status = (HWREG(ui32Base + CAN_O_MSG1INT) & + CAN_MSG1INT_INTPND_M); + ui32Status |= (HWREG(ui32Base + CAN_O_MSG2INT) << 16); + break; + } + + // + // Request was for unknown status so just return 0. + // + default: + { + ui32Status = 0; + break; + } + } + + // + // Return the interrupt status value + // + return(ui32Status); +} + +//***************************************************************************** +// +//! Clears a CAN interrupt source. +//! +//! \param ui32Base is the base address of the CAN controller. +//! \param ui32IntClr is a value indicating which interrupt source to clear. +//! +//! This function can be used to clear a specific interrupt source. The +//! \e ui32IntClr parameter must be one of the following values: +//! +//! - \b CAN_INT_INTID_STATUS - Clears a status interrupt. +//! - 1-32 - Clears the specified message object interrupt +//! +//! It is not necessary to use this function to clear an interrupt. This +//! function is only used if the application wants to clear an interrupt +//! source without taking the normal interrupt action. +//! +//! Normally, the status interrupt is cleared by reading the controller status +//! using CANStatusGet(). A specific message object interrupt is normally +//! cleared by reading the message object using CANMessageGet(). +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +CANIntClear(uint32_t ui32Base, uint32_t ui32IntClr) +{ + // + // Check the arguments. + // + ASSERT(_CANBaseValid(ui32Base)); + ASSERT((ui32IntClr == CAN_INT_INTID_STATUS) || + ((ui32IntClr >= 1) && (ui32IntClr <= 32))); + + if(ui32IntClr == CAN_INT_INTID_STATUS) + { + // + // Simply read and discard the status to clear the interrupt. + // + HWREG(ui32Base + CAN_O_STS); + } + else + { + // + // Wait to be sure that this interface is not busy. + // + while(HWREG(ui32Base + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY) + { + } + + // + // Only change the interrupt pending state by setting only the + // CAN_IF1CMSK_CLRINTPND bit. + // + HWREG(ui32Base + CAN_O_IF1CMSK) = CAN_IF1CMSK_CLRINTPND; + + // + // Send the clear pending interrupt command to the CAN controller. + // + HWREG(ui32Base + CAN_O_IF1CRQ) = ui32IntClr & CAN_IF1CRQ_MNUM_M; + + // + // Wait to be sure that this interface is not busy. + // + while(HWREG(ui32Base + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY) + { + } + } +} + +//***************************************************************************** +// +//! Sets the CAN controller automatic retransmission behavior. +//! +//! \param ui32Base is the base address of the CAN controller. +//! \param bAutoRetry enables automatic retransmission. +//! +//! This function enables or disables automatic retransmission of messages with +//! detected errors. If \e bAutoRetry is \b true, then automatic +//! retransmission is enabled, otherwise it is disabled. +//! +//! \return None. +// +//***************************************************************************** +void +CANRetrySet(uint32_t ui32Base, bool bAutoRetry) +{ + uint32_t ui32CtlReg; + + // + // Check the arguments. + // + ASSERT(_CANBaseValid(ui32Base)); + + ui32CtlReg = HWREG(ui32Base + CAN_O_CTL); + + // + // Conditionally set the DAR bit to enable/disable auto-retry. + // + if(bAutoRetry) + { + // + // Clearing the DAR bit tells the controller to not disable the + // auto-retry of messages which were not transmitted or received + // correctly. + // + ui32CtlReg &= ~CAN_CTL_DAR; + } + else + { + // + // Setting the DAR bit tells the controller to disable the auto-retry + // of messages which were not transmitted or received correctly. + // + ui32CtlReg |= CAN_CTL_DAR; + } + + HWREG(ui32Base + CAN_O_CTL) = ui32CtlReg; +} + +//***************************************************************************** +// +//! Returns the current setting for automatic retransmission. +//! +//! \param ui32Base is the base address of the CAN controller. +//! +//! This function reads the current setting for automatic retransmission in the +//! CAN controller and returns it to the caller. +//! +//! \return Returns \b true if automatic retransmission is enabled, \b false +//! otherwise. +// +//***************************************************************************** +bool +CANRetryGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_CANBaseValid(ui32Base)); + + // + // Read the disable automatic retry setting from the CAN controller. + // + if(HWREG(ui32Base + CAN_O_CTL) & CAN_CTL_DAR) + { + // + // Automatic data retransmission is not enabled. + // + return(false); + } + + // + // Automatic data retransmission is enabled. + // + return(true); +} + +//***************************************************************************** +// +//! Reads one of the controller status registers. +//! +//! \param ui32Base is the base address of the CAN controller. +//! \param eStatusReg is the status register to read. +//! +//! This function reads a status register of the CAN controller and returns it +//! to the caller. +//! The different status registers are: +//! +//! - \b CAN_STS_CONTROL - the main controller status +//! - \b CAN_STS_TXREQUEST - bit mask of objects pending transmission +//! - \b CAN_STS_NEWDAT - bit mask of objects with new data +//! - \b CAN_STS_MSGVAL - bit mask of objects with valid configuration +//! +//! When reading the main controller status register, a pending status +//! interrupt is cleared. This parameter is used in the interrupt +//! handler for the CAN controller if the cause is a status interrupt. The +//! controller status register fields are as follows: +//! +//! - \b CAN_STATUS_BUS_OFF - controller is in bus-off condition +//! - \b CAN_STATUS_EWARN - an error counter has reached a limit of at least 96 +//! - \b CAN_STATUS_EPASS - CAN controller is in the error passive state +//! - \b CAN_STATUS_RXOK - a message was received successfully (independent of +//! any message filtering). +//! - \b CAN_STATUS_TXOK - a message was successfully transmitted +//! - \b CAN_STATUS_LEC_MSK - mask of last error code bits (3 bits) +//! - \b CAN_STATUS_LEC_NONE - no error +//! - \b CAN_STATUS_LEC_STUFF - stuffing error detected +//! - \b CAN_STATUS_LEC_FORM - a format error occurred in the fixed format part +//! of a message +//! - \b CAN_STATUS_LEC_ACK - a transmitted message was not acknowledged +//! - \b CAN_STATUS_LEC_BIT1 - dominant level detected when trying to send in +//! recessive mode +//! - \b CAN_STATUS_LEC_BIT0 - recessive level detected when trying to send in +//! dominant mode +//! - \b CAN_STATUS_LEC_CRC - CRC error in received message +//! +//! The remaining status registers consist of 32-bit-wide bit maps to the +//! message objects. They can be used to quickly obtain information about the +//! status of all the message objects without needing to query each one. They +//! contain the following information: +//! +//! - \b CAN_STS_TXREQUEST - if a message object's TXRQST bit is set, a +//! transmission is pending on that object. The application can use this +//! information to determine which objects are still waiting to send a +//! message. +//! - \b CAN_STS_NEWDAT - if a message object's NEWDAT bit is set, a new +//! message has been received in that object, and has not yet been picked up +//! by the host application +//! - \b CAN_STS_MSGVAL - if a message object's MSGVAL bit is set, the object +//! has a valid configuration programmed. The host application can use this +//! information to determine which message objects are empty/unused. +//! +//! \return Returns the value of the status register. +// +//***************************************************************************** +uint32_t +CANStatusGet(uint32_t ui32Base, tCANStsReg eStatusReg) +{ + uint32_t ui32Status; + + // + // Check the arguments. + // + ASSERT(_CANBaseValid(ui32Base)); + + switch(eStatusReg) + { + // + // Just return the global CAN status register since that is what was + // requested. + // + case CAN_STS_CONTROL: + { + ui32Status = HWREG(ui32Base + CAN_O_STS); + HWREG(ui32Base + CAN_O_STS) = ~(CAN_STS_RXOK | CAN_STS_TXOK | + CAN_STS_LEC_M); + break; + } + + // + // Combine the Transmit status bits into one 32bit value. + // + case CAN_STS_TXREQUEST: + { + ui32Status = HWREG(ui32Base + CAN_O_TXRQ1); + ui32Status |= HWREG(ui32Base + CAN_O_TXRQ2) << 16; + break; + } + + // + // Combine the New Data status bits into one 32bit value. + // + case CAN_STS_NEWDAT: + { + ui32Status = HWREG(ui32Base + CAN_O_NWDA1); + ui32Status |= HWREG(ui32Base + CAN_O_NWDA2) << 16; + break; + } + + // + // Combine the Message valid status bits into one 32bit value. + // + case CAN_STS_MSGVAL: + { + ui32Status = HWREG(ui32Base + CAN_O_MSG1VAL); + ui32Status |= HWREG(ui32Base + CAN_O_MSG2VAL) << 16; + break; + } + + // + // Unknown CAN status requested so return 0. + // + default: + { + ui32Status = 0; + break; + } + } + return(ui32Status); +} + +//***************************************************************************** +// +//! Reads the CAN controller error counter register. +//! +//! \param ui32Base is the base address of the CAN controller. +//! \param pui32RxCount is a pointer to storage for the receive error counter. +//! \param pui32TxCount is a pointer to storage for the transmit error counter. +//! +//! This function reads the error counter register and returns the transmit and +//! receive error counts to the caller along with a flag indicating if the +//! controller receive counter has reached the error passive limit. The values +//! of the receive and transmit error counters are returned through the +//! pointers provided as parameters. +//! +//! After this call, \e *pui32RxCount holds the current receive error count +//! and \e *pui32TxCount holds the current transmit error count. +//! +//! \return Returns \b true if the receive error count has reached the error +//! passive limit, and \b false if the error count is below the error passive +//! limit. +// +//***************************************************************************** +bool +CANErrCntrGet(uint32_t ui32Base, uint32_t *pui32RxCount, + uint32_t *pui32TxCount) +{ + uint32_t ui32CANError; + + // + // Check the arguments. + // + ASSERT(_CANBaseValid(ui32Base)); + + // + // Read the current count of transmit/receive errors. + // + ui32CANError = HWREG(ui32Base + CAN_O_ERR); + + // + // Extract the error numbers from the register value. + // + *pui32RxCount = (ui32CANError & CAN_ERR_REC_M) >> CAN_ERR_REC_S; + *pui32TxCount = (ui32CANError & CAN_ERR_TEC_M) >> CAN_ERR_TEC_S; + + if(ui32CANError & CAN_ERR_RP) + { + return(true); + } + return(false); +} + +//***************************************************************************** +// +//! Configures a message object in the CAN controller. +//! +//! \param ui32Base is the base address of the CAN controller. +//! \param ui32ObjID is the object number to configure (1-32). +//! \param psMsgObject is a pointer to a structure containing message object +//! settings. +//! \param eMsgType indicates the type of message for this object. +//! +//! This function is used to configure any one of the 32 message objects in the +//! CAN controller. A message object can be configured to be any type of CAN +//! message object as well as to use automatic transmission and reception. +//! This call also allows the message object to be configured to generate +//! interrupts on completion of message receipt or transmission. The +//! message object can also be configured with a filter/mask so that actions +//! are only taken when a message that meets certain parameters is seen on the +//! CAN bus. +//! +//! The \e eMsgType parameter must be one of the following values: +//! +//! - \b MSG_OBJ_TYPE_TX - CAN transmit message object. +//! - \b MSG_OBJ_TYPE_TX_REMOTE - CAN transmit remote request message object. +//! - \b MSG_OBJ_TYPE_RX - CAN receive message object. +//! - \b MSG_OBJ_TYPE_RX_REMOTE - CAN receive remote request message object. +//! - \b MSG_OBJ_TYPE_RXTX_REMOTE - CAN remote frame receive remote, then +//! transmit message object. +//! +//! The message object pointed to by \e psMsgObject must be populated by the +//! caller, as follows: +//! +//! - \e ui32MsgID - contains the message ID, either 11 or 29 bits. +//! - \e ui32MsgIDMask - mask of bits from \e ui32MsgID that must match if +//! identifier filtering is enabled. +//! - \e ui32Flags +//! - Set \b MSG_OBJ_TX_INT_ENABLE flag to enable interrupt on transmission. +//! - Set \b MSG_OBJ_RX_INT_ENABLE flag to enable interrupt on receipt. +//! - Set \b MSG_OBJ_USE_ID_FILTER flag to enable filtering based on the +//! identifier mask specified by \e ui32MsgIDMask. +//! - \e ui32MsgLen - the number of bytes in the message data. This parameter +//! must be non-zero even for a remote frame; it must match the expected +//! bytes of data in the responding data frame. +//! - \e pui8MsgData - points to a buffer containing up to 8 bytes of data for +//! a data frame. +//! +//! \b Example: To send a data frame or remote frame (in response to a remote +//! request), take the following steps: +//! +//! -# Set \e eMsgType to \b MSG_OBJ_TYPE_TX. +//! -# Set \e psMsgObject->ui32MsgID to the message ID. +//! -# Set \e psMsgObject->ui32Flags. Make sure to set +//! \b MSG_OBJ_TX_INT_ENABLE to allow an interrupt to be generated when the +//! message is sent. +//! -# Set \e psMsgObject->ui32MsgLen to the number of bytes in the data frame. +//! -# Set \e psMsgObject->pui8MsgData to point to an array containing the +//! bytes to send in the message. +//! -# Call this function with \e ui32ObjID set to one of the 32 object +//! buffers. +//! +//! \b Example: To receive a specific data frame, take the following steps: +//! +//! -# Set \e eMsgObjType to \b MSG_OBJ_TYPE_RX. +//! -# Set \e psMsgObject->ui32MsgID to the full message ID, or a partial mask +//! to use partial ID matching. +//! -# Set \e psMsgObject->ui32MsgIDMask bits that are used for masking +//! during comparison. +//! -# Set \e psMsgObject->ui32Flags as follows: +//! - Set \b MSG_OBJ_RX_INT_ENABLE flag to be interrupted when the data +//! frame is received. +//! - Set \b MSG_OBJ_USE_ID_FILTER flag to enable identifier-based +//! filtering. +//! -# Set \e psMsgObject->ui32MsgLen to the number of bytes in the expected +//! data frame. +//! -# The buffer pointed to by \e psMsgObject->pui8MsgData is not used by this +//! call as no data is present at the time of the call. +//! -# Call this function with \e ui32ObjID set to one of the 32 object +//! buffers. +//! +//! If you specify a message object buffer that already contains a message +//! definition, it is overwritten. +//! +//! \return None. +// +//***************************************************************************** +void +CANMessageSet(uint32_t ui32Base, uint32_t ui32ObjID, + tCANMsgObject *psMsgObject, tMsgObjType eMsgType) +{ + uint16_t ui16CmdMaskReg; + uint16_t ui16MaskReg0, ui16MaskReg1; + uint16_t ui16ArbReg0, ui16ArbReg1; + uint16_t ui16MsgCtrl; + bool bTransferData; + bool bUseExtendedID; + + bTransferData = 0; + + // + // Check the arguments. + // + ASSERT(_CANBaseValid(ui32Base)); + ASSERT((ui32ObjID <= 32) && (ui32ObjID != 0)); + ASSERT((eMsgType == MSG_OBJ_TYPE_TX) || + (eMsgType == MSG_OBJ_TYPE_TX_REMOTE) || + (eMsgType == MSG_OBJ_TYPE_RX) || + (eMsgType == MSG_OBJ_TYPE_RX_REMOTE) || + (eMsgType == MSG_OBJ_TYPE_TX_REMOTE) || + (eMsgType == MSG_OBJ_TYPE_RXTX_REMOTE)); + + // + // Wait for busy bit to clear + // + while(HWREG(ui32Base + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY) + { + } + + // + // See if we need to use an extended identifier or not. + // + if((psMsgObject->ui32MsgID > CAN_MAX_11BIT_MSG_ID) || + (psMsgObject->ui32Flags & MSG_OBJ_EXTENDED_ID)) + { + bUseExtendedID = 1; + } + else + { + bUseExtendedID = 0; + } + + // + // This is always a write to the Message object as this call is setting a + // message object. This call always sets all size bits so it sets + // both data bits. The call uses the CONTROL register to set control + // bits so this bit needs to be set as well. + // + ui16CmdMaskReg = (CAN_IF1CMSK_WRNRD | CAN_IF1CMSK_DATAA | + CAN_IF1CMSK_DATAB | CAN_IF1CMSK_CONTROL); + + // + // Initialize the values to a known state before filling them in based on + // the type of message object that is being configured. + // + ui16ArbReg0 = 0; + ui16ArbReg1 = 0; + ui16MsgCtrl = 0; + ui16MaskReg0 = 0; + ui16MaskReg1 = 0; + + switch(eMsgType) + { + // + // Transmit message object. + // + case MSG_OBJ_TYPE_TX: + { + // + // Set the TXRQST bit and the reset the rest of the register. + // + ui16MsgCtrl |= CAN_IF1MCTL_TXRQST; + ui16ArbReg1 = CAN_IF1ARB2_DIR; + bTransferData = 1; + break; + } + + // + // Transmit remote request message object + // + case MSG_OBJ_TYPE_TX_REMOTE: + { + // + // Set the TXRQST bit and the reset the rest of the register. + // + ui16MsgCtrl |= CAN_IF1MCTL_TXRQST; + ui16ArbReg1 = 0; + break; + } + + // + // Receive message object. + // + case MSG_OBJ_TYPE_RX: + { + // + // This clears the DIR bit along with everything else. The TXRQST + // bit was cleared by defaulting ui16MsgCtrl to 0. + // + ui16ArbReg1 = 0; + break; + } + + // + // Receive remote request message object. + // + case MSG_OBJ_TYPE_RX_REMOTE: + { + // + // The DIR bit is set to one for remote receivers. The TXRQST bit + // was cleared by defaulting ui16MsgCtrl to 0. + // + ui16ArbReg1 = CAN_IF1ARB2_DIR; + + // + // Set this object so that it only indicates that a remote frame + // was received and allow for software to handle it by sending back + // a data frame. + // + ui16MsgCtrl = CAN_IF1MCTL_UMASK; + + // + // Use the full Identifier by default. + // + ui16MaskReg0 = 0xffff; + ui16MaskReg1 = 0x1fff; + + // + // Make sure to send the mask to the message object. + // + ui16CmdMaskReg |= CAN_IF1CMSK_MASK; + break; + } + + // + // Remote frame receive remote, with auto-transmit message object. + // + case MSG_OBJ_TYPE_RXTX_REMOTE: + { + // + // Oddly the DIR bit is set to one for remote receivers. + // + ui16ArbReg1 = CAN_IF1ARB2_DIR; + + // + // Set this object to auto answer if a matching identifier is seen. + // + ui16MsgCtrl = CAN_IF1MCTL_RMTEN | CAN_IF1MCTL_UMASK; + + // + // The data to be returned needs to be filled in. + // + bTransferData = 1; + break; + } + + // + // This case never happens due to the ASSERT statement at the + // beginning of this function. + // + default: + { + return; + } + } + + // + // Configure the Mask Registers. + // + if(psMsgObject->ui32Flags & MSG_OBJ_USE_ID_FILTER) + { + if(bUseExtendedID) + { + // + // Set the 29 bits of Identifier mask that were requested. + // + ui16MaskReg0 = psMsgObject->ui32MsgIDMask & CAN_IF1MSK1_IDMSK_M; + ui16MaskReg1 = ((psMsgObject->ui32MsgIDMask >> 16) & + CAN_IF1MSK2_IDMSK_M); + } + else + { + // + // Lower 16 bit are unused so set them to zero. + // + ui16MaskReg0 = 0; + + // + // Put the 11 bit Mask Identifier into the upper bits of the field + // in the register. + // + ui16MaskReg1 = ((psMsgObject->ui32MsgIDMask << 2) & + CAN_IF1MSK2_IDMSK_M); + } + } + + // + // If the caller wants to filter on the extended ID bit then set it. + // + if((psMsgObject->ui32Flags & MSG_OBJ_USE_EXT_FILTER) == + MSG_OBJ_USE_EXT_FILTER) + { + ui16MaskReg1 |= CAN_IF1MSK2_MXTD; + } + + // + // The caller wants to filter on the message direction field. + // + if((psMsgObject->ui32Flags & MSG_OBJ_USE_DIR_FILTER) == + MSG_OBJ_USE_DIR_FILTER) + { + ui16MaskReg1 |= CAN_IF1MSK2_MDIR; + } + + if(psMsgObject->ui32Flags & + (MSG_OBJ_USE_ID_FILTER | MSG_OBJ_USE_DIR_FILTER | + MSG_OBJ_USE_EXT_FILTER)) + { + // + // Set the UMASK bit to enable using the mask register. + // + ui16MsgCtrl |= CAN_IF1MCTL_UMASK; + + // + // Set the MASK bit so that this gets transferred to the Message + // Object. + // + ui16CmdMaskReg |= CAN_IF1CMSK_MASK; + } + + // + // Set the Arb bit so that this gets transferred to the Message object. + // + ui16CmdMaskReg |= CAN_IF1CMSK_ARB; + + // + // Configure the Arbitration registers. + // + if(bUseExtendedID) + { + // + // Set the 29 bit version of the Identifier for this message object. + // + ui16ArbReg0 |= psMsgObject->ui32MsgID & CAN_IF1ARB1_ID_M; + ui16ArbReg1 |= (psMsgObject->ui32MsgID >> 16) & CAN_IF1ARB2_ID_M; + + // + // Mark the message as valid and set the extended ID bit. + // + ui16ArbReg1 |= CAN_IF1ARB2_MSGVAL | CAN_IF1ARB2_XTD; + } + else + { + // + // Set the 11 bit version of the Identifier for this message object. + // The lower 18 bits are set to zero. + // + ui16ArbReg1 |= (psMsgObject->ui32MsgID << 2) & CAN_IF1ARB2_ID_M; + + // + // Mark the message as valid. + // + ui16ArbReg1 |= CAN_IF1ARB2_MSGVAL; + } + + // + // Set the data length since this is set for all transfers. This is also a + // single transfer and not a FIFO transfer so set EOB bit. + // + ui16MsgCtrl |= (psMsgObject->ui32MsgLen & CAN_IF1MCTL_DLC_M); + + // + // Mark this as the last entry if this is not the last entry in a FIFO. + // + if((psMsgObject->ui32Flags & MSG_OBJ_FIFO) == 0) + { + ui16MsgCtrl |= CAN_IF1MCTL_EOB; + } + + // + // Enable transmit interrupts if they should be enabled. + // + if(psMsgObject->ui32Flags & MSG_OBJ_TX_INT_ENABLE) + { + ui16MsgCtrl |= CAN_IF1MCTL_TXIE; + } + + // + // Enable receive interrupts if they should be enabled. + // + if(psMsgObject->ui32Flags & MSG_OBJ_RX_INT_ENABLE) + { + ui16MsgCtrl |= CAN_IF1MCTL_RXIE; + } + + // + // Write the data out to the CAN Data registers if needed. + // + if(bTransferData) + { + _CANDataRegWrite(psMsgObject->pui8MsgData, + (uint32_t *)(ui32Base + CAN_O_IF1DA1), + psMsgObject->ui32MsgLen); + } + + // + // Write out the registers to program the message object. + // + HWREG(ui32Base + CAN_O_IF1CMSK) = ui16CmdMaskReg; + HWREG(ui32Base + CAN_O_IF1MSK1) = ui16MaskReg0; + HWREG(ui32Base + CAN_O_IF1MSK2) = ui16MaskReg1; + HWREG(ui32Base + CAN_O_IF1ARB1) = ui16ArbReg0; + HWREG(ui32Base + CAN_O_IF1ARB2) = ui16ArbReg1; + HWREG(ui32Base + CAN_O_IF1MCTL) = ui16MsgCtrl; + + // + // Transfer the message object to the message object specified by + // ui32ObjID. + // + HWREG(ui32Base + CAN_O_IF1CRQ) = ui32ObjID & CAN_IF1CRQ_MNUM_M; +} + +//***************************************************************************** +// +//! Reads a CAN message from one of the message object buffers. +//! +//! \param ui32Base is the base address of the CAN controller. +//! \param ui32ObjID is the object number to read (1-32). +//! \param psMsgObject points to a structure containing message object fields. +//! \param bClrPendingInt indicates whether an associated interrupt should be +//! cleared. +//! +//! This function is used to read the contents of one of the 32 message objects +//! in the CAN controller and return it to the caller. The data returned is +//! stored in the fields of the caller-supplied structure pointed to by +//! \e psMsgObject. The data consists of all of the parts of a CAN message, +//! plus some control and status information. +//! +//! Normally, this function is used to read a message object that has received +//! and stored a CAN message with a certain identifier. However, this function +//! could also be used to read the contents of a message object in order to +//! load the fields of the structure in case only part of the structure must +//! be changed from a previous setting. +//! +//! When using CANMessageGet(), all of the same fields of the structure are +//! populated in the same way as when the CANMessageSet() function is used, +//! with the following exceptions: +//! +//! \e psMsgObject->ui32Flags: +//! +//! - \b MSG_OBJ_NEW_DATA indicates if this data is new since the last time it +//! was read +//! - \b MSG_OBJ_DATA_LOST indicates that at least one message was received on +//! this message object and not read by the host before being overwritten. +//! +//! \return None. +// +//***************************************************************************** +void +CANMessageGet(uint32_t ui32Base, uint32_t ui32ObjID, + tCANMsgObject *psMsgObject, bool bClrPendingInt) +{ + uint16_t ui16CmdMaskReg; + uint16_t ui16MaskReg0, ui16MaskReg1; + uint16_t ui16ArbReg0, ui16ArbReg1; + uint16_t ui16MsgCtrl; + + // + // Check the arguments. + // + ASSERT(_CANBaseValid(ui32Base)); + ASSERT((ui32ObjID <= 32) && (ui32ObjID != 0)); + + // + // This is always a read to the Message object as this call is setting a + // message object. + // + ui16CmdMaskReg = (CAN_IF1CMSK_DATAA | CAN_IF1CMSK_DATAB | + CAN_IF1CMSK_CONTROL | CAN_IF1CMSK_MASK | + CAN_IF1CMSK_ARB); + + // + // Clear a pending interrupt and new data in a message object. + // + if(bClrPendingInt) + { + ui16CmdMaskReg |= CAN_IF1CMSK_CLRINTPND; + } + + // + // Set up the request for data from the message object. + // + HWREG(ui32Base + CAN_O_IF2CMSK) = ui16CmdMaskReg; + + // + // Transfer the message object to the message object specified by + // ui32ObjID. + // + HWREG(ui32Base + CAN_O_IF2CRQ) = ui32ObjID & CAN_IF1CRQ_MNUM_M; + + // + // Wait for busy bit to clear + // + while(HWREG(ui32Base + CAN_O_IF2CRQ) & CAN_IF1CRQ_BUSY) + { + } + + // + // Read out the IF Registers. + // + ui16MaskReg0 = HWREG(ui32Base + CAN_O_IF2MSK1); + ui16MaskReg1 = HWREG(ui32Base + CAN_O_IF2MSK2); + ui16ArbReg0 = HWREG(ui32Base + CAN_O_IF2ARB1); + ui16ArbReg1 = HWREG(ui32Base + CAN_O_IF2ARB2); + ui16MsgCtrl = HWREG(ui32Base + CAN_O_IF2MCTL); + + psMsgObject->ui32Flags = MSG_OBJ_NO_FLAGS; + + // + // Determine if this is a remote frame by checking the TXRQST and DIR bits. + // + if((!(ui16MsgCtrl & CAN_IF1MCTL_TXRQST) && + (ui16ArbReg1 & CAN_IF1ARB2_DIR)) || + ((ui16MsgCtrl & CAN_IF1MCTL_TXRQST) && + (!(ui16ArbReg1 & CAN_IF1ARB2_DIR)))) + { + psMsgObject->ui32Flags |= MSG_OBJ_REMOTE_FRAME; + } + + // + // Get the identifier out of the register, the format depends on size of + // the mask. + // + if(ui16ArbReg1 & CAN_IF1ARB2_XTD) + { + // + // Set the 29 bit version of the Identifier for this message object. + // + psMsgObject->ui32MsgID = (((ui16ArbReg1 & CAN_IF1ARB2_ID_M) << 16) | + ui16ArbReg0); + + psMsgObject->ui32Flags |= MSG_OBJ_EXTENDED_ID; + } + else + { + // + // The Identifier is an 11 bit value. + // + psMsgObject->ui32MsgID = (ui16ArbReg1 & CAN_IF1ARB2_ID_M) >> 2; + } + + // + // Indicate that we lost some data. + // + if(ui16MsgCtrl & CAN_IF1MCTL_MSGLST) + { + psMsgObject->ui32Flags |= MSG_OBJ_DATA_LOST; + } + + // + // Set the flag to indicate if ID masking was used. + // + if(ui16MsgCtrl & CAN_IF1MCTL_UMASK) + { + if(ui16ArbReg1 & CAN_IF1ARB2_XTD) + { + // + // The Identifier Mask is assumed to also be a 29 bit value. + // + psMsgObject->ui32MsgIDMask = + ((ui16MaskReg1 & CAN_IF1MSK2_IDMSK_M) << 16) | ui16MaskReg0; + + // + // If this is a fully specified Mask and a remote frame then don't + // set the MSG_OBJ_USE_ID_FILTER because the ID was not really + // filtered. + // + if((psMsgObject->ui32MsgIDMask != 0x1fffffff) || + ((psMsgObject->ui32Flags & MSG_OBJ_REMOTE_FRAME) == 0)) + { + psMsgObject->ui32Flags |= MSG_OBJ_USE_ID_FILTER; + } + } + else + { + // + // The Identifier Mask is assumed to also be an 11 bit value. + // + psMsgObject->ui32MsgIDMask = + (ui16MaskReg1 & CAN_IF1MSK2_IDMSK_M) >> 2; + + // + // If this is a fully specified Mask and a remote frame then don't + // set the MSG_OBJ_USE_ID_FILTER because the ID was not really + // filtered. + // + if((psMsgObject->ui32MsgIDMask != 0x7ff) || + ((psMsgObject->ui32Flags & MSG_OBJ_REMOTE_FRAME) == 0)) + { + psMsgObject->ui32Flags |= MSG_OBJ_USE_ID_FILTER; + } + } + + // + // Indicate if the extended bit was used in filtering. + // + if(ui16MaskReg1 & CAN_IF1MSK2_MXTD) + { + psMsgObject->ui32Flags |= MSG_OBJ_USE_EXT_FILTER; + } + + // + // Indicate if direction filtering was enabled. + // + if(ui16MaskReg1 & CAN_IF1MSK2_MDIR) + { + psMsgObject->ui32Flags |= MSG_OBJ_USE_DIR_FILTER; + } + } + + // + // Set the interrupt flags. + // + if(ui16MsgCtrl & CAN_IF1MCTL_TXIE) + { + psMsgObject->ui32Flags |= MSG_OBJ_TX_INT_ENABLE; + } + if(ui16MsgCtrl & CAN_IF1MCTL_RXIE) + { + psMsgObject->ui32Flags |= MSG_OBJ_RX_INT_ENABLE; + } + + // + // See if there is new data available. + // + if(ui16MsgCtrl & CAN_IF1MCTL_NEWDAT) + { + // + // Get the amount of data needed to be read. + // + psMsgObject->ui32MsgLen = (ui16MsgCtrl & CAN_IF1MCTL_DLC_M); + + // + // Don't read any data for a remote frame, there is nothing valid in + // that buffer anyway. + // + if((psMsgObject->ui32Flags & MSG_OBJ_REMOTE_FRAME) == 0) + { + // + // Read out the data from the CAN registers. + // + _CANDataRegRead(psMsgObject->pui8MsgData, + (uint32_t *)(ui32Base + CAN_O_IF2DA1), + psMsgObject->ui32MsgLen); + } + + // + // Now clear out the new data flag. + // + HWREG(ui32Base + CAN_O_IF2CMSK) = CAN_IF1CMSK_NEWDAT; + + // + // Transfer the message object to the message object specified by + // ui32ObjID. + // + HWREG(ui32Base + CAN_O_IF2CRQ) = ui32ObjID & CAN_IF1CRQ_MNUM_M; + + // + // Wait for busy bit to clear + // + while(HWREG(ui32Base + CAN_O_IF2CRQ) & CAN_IF1CRQ_BUSY) + { + } + + // + // Indicate that there is new data in this message. + // + psMsgObject->ui32Flags |= MSG_OBJ_NEW_DATA; + } + else + { + // + // Along with the MSG_OBJ_NEW_DATA not being set the amount of data + // needs to be set to zero if none was available. + // + psMsgObject->ui32MsgLen = 0; + } +} + +//***************************************************************************** +// +//! Clears a message object so that it is no longer used. +//! +//! \param ui32Base is the base address of the CAN controller. +//! \param ui32ObjID is the message object number to disable (1-32). +//! +//! This function frees the specified message object from use. Once a message +//! object has been ``cleared,'' it no longer automatically sends or receives +//! messages, nor does it generate interrupts. +//! +//! \return None. +// +//***************************************************************************** +void +CANMessageClear(uint32_t ui32Base, uint32_t ui32ObjID) +{ + // + // Check the arguments. + // + ASSERT(_CANBaseValid(ui32Base)); + ASSERT((ui32ObjID >= 1) && (ui32ObjID <= 32)); + + // + // Wait for busy bit to clear + // + while(HWREG(ui32Base + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY) + { + } + + // + // Clear the message value bit in the arbitration register. This indicates + // the message is not valid. + // + HWREG(ui32Base + CAN_O_IF1CMSK) = CAN_IF1CMSK_WRNRD | CAN_IF1CMSK_ARB; + HWREG(ui32Base + CAN_O_IF1ARB1) = 0; + HWREG(ui32Base + CAN_O_IF1ARB2) = 0; + + // + // Initiate programming the message object + // + HWREG(ui32Base + CAN_O_IF1CRQ) = ui32ObjID & CAN_IF1CRQ_MNUM_M; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/comp.c b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/comp.c new file mode 100644 index 0000000000000000000000000000000000000000..6f03b7c01a75f8c8bce5feff761634adf7c00d48 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/comp.c @@ -0,0 +1,452 @@ +//***************************************************************************** +// +// comp.c - Driver for the analog comparator. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup comp_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_comp.h" +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "driverlib/comp.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" + +//***************************************************************************** +// +//! Configures a comparator. +//! +//! \param ui32Base is the base address of the comparator module. +//! \param ui32Comp is the index of the comparator to configure. +//! \param ui32Config is the configuration of the comparator. +//! +//! This function configures a comparator. The \e ui32Config parameter is the +//! result of a logical OR operation between the \b COMP_TRIG_xxx, +//! \b COMP_INT_xxx, \b COMP_ASRCP_xxx, and \b COMP_OUTPUT_xxx values. +//! +//! The \b COMP_TRIG_xxx term can take on the following values: +//! +//! - \b COMP_TRIG_NONE to have no trigger to the ADC. +//! - \b COMP_TRIG_HIGH to trigger the ADC when the comparator output is high. +//! - \b COMP_TRIG_LOW to trigger the ADC when the comparator output is low. +//! - \b COMP_TRIG_FALL to trigger the ADC when the comparator output goes low. +//! - \b COMP_TRIG_RISE to trigger the ADC when the comparator output goes +//! high. +//! - \b COMP_TRIG_BOTH to trigger the ADC when the comparator output goes low +//! or high. +//! +//! The \b COMP_INT_xxx term can take on the following values: +//! +//! - \b COMP_INT_HIGH to generate an interrupt when the comparator output is +//! high. +//! - \b COMP_INT_LOW to generate an interrupt when the comparator output is +//! low. +//! - \b COMP_INT_FALL to generate an interrupt when the comparator output goes +//! low. +//! - \b COMP_INT_RISE to generate an interrupt when the comparator output goes +//! high. +//! - \b COMP_INT_BOTH to generate an interrupt when the comparator output goes +//! low or high. +//! +//! The \b COMP_ASRCP_xxx term can take on the following values: +//! +//! - \b COMP_ASRCP_PIN to use the dedicated Comp+ pin as the reference +//! voltage. +//! - \b COMP_ASRCP_PIN0 to use the Comp0+ pin as the reference voltage (this +//! the same as \b COMP_ASRCP_PIN for the comparator 0). +//! - \b COMP_ASRCP_REF to use the internally generated voltage as the +//! reference voltage. +//! +//! The \b COMP_OUTPUT_xxx term can take on the following values: +//! +//! - \b COMP_OUTPUT_NORMAL to enable a non-inverted output from the comparator +//! to a device pin. +//! - \b COMP_OUTPUT_INVERT to enable an inverted output from the comparator to +//! a device pin. +//! +//! \return None. +// +//***************************************************************************** +void +ComparatorConfigure(uint32_t ui32Base, uint32_t ui32Comp, uint32_t ui32Config) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == COMP_BASE); + ASSERT(ui32Comp < 3); + + // + // Configure this comparator. + // + HWREG(ui32Base + (ui32Comp * 0x20) + COMP_O_ACCTL0) = ui32Config; +} + +//***************************************************************************** +// +//! Sets the internal reference voltage. +//! +//! \param ui32Base is the base address of the comparator module. +//! \param ui32Ref is the desired reference voltage. +//! +//! This function sets the internal reference voltage value. The voltage is +//! specified as one of the following values: +//! +//! - \b COMP_REF_OFF to turn off the reference voltage +//! - \b COMP_REF_0V to set the reference voltage to 0 V +//! - \b COMP_REF_0_1375V to set the reference voltage to 0.1375 V +//! - \b COMP_REF_0_275V to set the reference voltage to 0.275 V +//! - \b COMP_REF_0_4125V to set the reference voltage to 0.4125 V +//! - \b COMP_REF_0_55V to set the reference voltage to 0.55 V +//! - \b COMP_REF_0_6875V to set the reference voltage to 0.6875 V +//! - \b COMP_REF_0_825V to set the reference voltage to 0.825 V +//! - \b COMP_REF_0_928125V to set the reference voltage to 0.928125 V +//! - \b COMP_REF_0_9625V to set the reference voltage to 0.9625 V +//! - \b COMP_REF_1_03125V to set the reference voltage to 1.03125 V +//! - \b COMP_REF_1_134375V to set the reference voltage to 1.134375 V +//! - \b COMP_REF_1_1V to set the reference voltage to 1.1 V +//! - \b COMP_REF_1_2375V to set the reference voltage to 1.2375 V +//! - \b COMP_REF_1_340625V to set the reference voltage to 1.340625 V +//! - \b COMP_REF_1_375V to set the reference voltage to 1.375 V +//! - \b COMP_REF_1_44375V to set the reference voltage to 1.44375 V +//! - \b COMP_REF_1_5125V to set the reference voltage to 1.5125 V +//! - \b COMP_REF_1_546875V to set the reference voltage to 1.546875 V +//! - \b COMP_REF_1_65V to set the reference voltage to 1.65 V +//! - \b COMP_REF_1_753125V to set the reference voltage to 1.753125 V +//! - \b COMP_REF_1_7875V to set the reference voltage to 1.7875 V +//! - \b COMP_REF_1_85625V to set the reference voltage to 1.85625 V +//! - \b COMP_REF_1_925V to set the reference voltage to 1.925 V +//! - \b COMP_REF_1_959375V to set the reference voltage to 1.959375 V +//! - \b COMP_REF_2_0625V to set the reference voltage to 2.0625 V +//! - \b COMP_REF_2_165625V to set the reference voltage to 2.165625 V +//! - \b COMP_REF_2_26875V to set the reference voltage to 2.26875 V +//! - \b COMP_REF_2_371875V to set the reference voltage to 2.371875 V +//! +//! \return None. +// +//***************************************************************************** +void +ComparatorRefSet(uint32_t ui32Base, uint32_t ui32Ref) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == COMP_BASE); + + // + // Set the voltage reference voltage as requested. + // + HWREG(ui32Base + COMP_O_ACREFCTL) = ui32Ref; +} + +//***************************************************************************** +// +//! Gets the current comparator output value. +//! +//! \param ui32Base is the base address of the comparator module. +//! \param ui32Comp is the index of the comparator. +//! +//! This function retrieves the current value of the comparator output. +//! +//! \return Returns \b true if the comparator output is high and \b false if +//! the comparator output is low. +// +//***************************************************************************** +bool +ComparatorValueGet(uint32_t ui32Base, uint32_t ui32Comp) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == COMP_BASE); + ASSERT(ui32Comp < 3); + + // + // Return the appropriate value based on the comparator's present output + // value. + // + if(HWREG(ui32Base + (ui32Comp * 0x20) + COMP_O_ACSTAT0) & + COMP_ACSTAT0_OVAL) + { + return(true); + } + else + { + return(false); + } +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the comparator interrupt. +//! +//! \param ui32Base is the base address of the comparator module. +//! \param ui32Comp is the index of the comparator. +//! \param pfnHandler is a pointer to the function to be called when the +//! comparator interrupt occurs. +//! +//! This function sets the handler to be called when the comparator interrupt +//! occurs and enables the interrupt in the interrupt controller. It is the +//! interrupt handler's responsibility to clear the interrupt source via +//! ComparatorIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +ComparatorIntRegister(uint32_t ui32Base, uint32_t ui32Comp, + void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == COMP_BASE); + ASSERT(ui32Comp < 3); + + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(INT_COMP0_TM4C123 + ui32Comp, pfnHandler); + + // + // Enable the interrupt in the interrupt controller. + // + IntEnable(INT_COMP0_TM4C123 + ui32Comp); + + // + // Enable the comparator interrupt. + // + HWREG(ui32Base + COMP_O_ACINTEN) |= 1 << ui32Comp; +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for a comparator interrupt. +//! +//! \param ui32Base is the base address of the comparator module. +//! \param ui32Comp is the index of the comparator. +//! +//! This function clears the handler to be called when a comparator interrupt +//! occurs. This function also masks off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +ComparatorIntUnregister(uint32_t ui32Base, uint32_t ui32Comp) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == COMP_BASE); + ASSERT(ui32Comp < 3); + + // + // Disable the comparator interrupt. + // + HWREG(ui32Base + COMP_O_ACINTEN) &= ~(1 << ui32Comp); + + // + // Disable the interrupt in the interrupt controller. + // + IntDisable(INT_COMP0_TM4C123 + ui32Comp); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_COMP0_TM4C123 + ui32Comp); +} + +//***************************************************************************** +// +//! Enables the comparator interrupt. +//! +//! \param ui32Base is the base address of the comparator module. +//! \param ui32Comp is the index of the comparator. +//! +//! This function enables generation of an interrupt from the specified +//! comparator. Only enabled comparator interrupts can be reflected +//! to the processor. +//! +//! \return None. +// +//***************************************************************************** +void +ComparatorIntEnable(uint32_t ui32Base, uint32_t ui32Comp) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == COMP_BASE); + ASSERT(ui32Comp < 3); + + // + // Enable the comparator interrupt. + // + HWREG(ui32Base + COMP_O_ACINTEN) |= 1 << ui32Comp; +} + +//***************************************************************************** +// +//! Disables the comparator interrupt. +//! +//! \param ui32Base is the base address of the comparator module. +//! \param ui32Comp is the index of the comparator. +//! +//! This function disables generation of an interrupt from the specified +//! comparator. Only enabled comparator interrupts can be reflected +//! to the processor. +//! +//! \return None. +// +//***************************************************************************** +void +ComparatorIntDisable(uint32_t ui32Base, uint32_t ui32Comp) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == COMP_BASE); + ASSERT(ui32Comp < 3); + + // + // Disable the comparator interrupt. + // + HWREG(ui32Base + COMP_O_ACINTEN) &= ~(1 << ui32Comp); +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ui32Base is the base address of the comparator module. +//! \param ui32Comp is the index of the comparator. +//! \param bMasked is \b false if the raw interrupt status is required and +//! \b true if the masked interrupt status is required. +//! +//! This function returns the interrupt status for the comparator. Either the +//! raw or the masked interrupt status can be returned. +//! +//! \return \b true if the interrupt is asserted and \b false if it is not +//! asserted. +// +//***************************************************************************** +bool +ComparatorIntStatus(uint32_t ui32Base, uint32_t ui32Comp, bool bMasked) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == COMP_BASE); + ASSERT(ui32Comp < 3); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(((HWREG(ui32Base + COMP_O_ACMIS) >> ui32Comp) & 1) ? true : + false); + } + else + { + return(((HWREG(ui32Base + COMP_O_ACRIS) >> ui32Comp) & 1) ? true : + false); + } +} + +//***************************************************************************** +// +//! Clears a comparator interrupt. +//! +//! \param ui32Base is the base address of the comparator module. +//! \param ui32Comp is the index of the comparator. +//! +//! The comparator interrupt is cleared, so that it no longer asserts. This +//! function must be called in the interrupt handler to keep the handler from +//! being called again immediately upon exit. Note that for a level-triggered +//! interrupt, the interrupt cannot be cleared until it stops asserting. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +ComparatorIntClear(uint32_t ui32Base, uint32_t ui32Comp) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == COMP_BASE); + ASSERT(ui32Comp < 3); + + // + // Clear the interrupt. + // + HWREG(ui32Base + COMP_O_ACMIS) = 1 << ui32Comp; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/cpu.c b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/cpu.c new file mode 100644 index 0000000000000000000000000000000000000000..0cddffc3405aeb707727a4df209dc4fd23cb2554 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/cpu.c @@ -0,0 +1,457 @@ +//***************************************************************************** +// +// cpu.c - Instruction wrappers for special CPU instructions needed by the +// drivers. +// +// Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#include +#include "driverlib/cpu.h" + +//***************************************************************************** +// +// Wrapper function for the CPSID instruction. Returns the state of PRIMASK +// on entry. +// +//***************************************************************************** +#if defined(codered) || defined(gcc) || defined(sourcerygxx) +uint32_t __attribute__((naked)) +CPUcpsid(void) +{ + uint32_t ui32Ret; + + // + // Read PRIMASK and disable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " cpsid i\n" + " bx lr\n" + : "=r" (ui32Ret)); + + // + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + // + return(ui32Ret); +} +#endif +#if defined(ewarm) +uint32_t +CPUcpsid(void) +{ + // + // Read PRIMASK and disable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " cpsid i\n"); + + // + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. + // +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#endif +#if defined(rvmdk) || defined(__ARMCC_VERSION) +__asm uint32_t +CPUcpsid(void) +{ + // + // Read PRIMASK and disable interrupts. + // + mrs r0, PRIMASK; + cpsid i; + bx lr +} +#endif +#if defined(ccs) +uint32_t +CPUcpsid(void) +{ + // + // Read PRIMASK and disable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " cpsid i\n" + " bx lr\n"); + + // + // The following keeps the compiler happy, because it wants to see a + // return value from this function. It will generate code to return + // a zero. However, the real return is the "bx lr" above, so the + // return(0) is never executed and the function returns with the value + // you expect in R0. + // + return(0); +} +#endif + +//***************************************************************************** +// +// Wrapper function returning the state of PRIMASK (indicating whether +// interrupts are enabled or disabled). +// +//***************************************************************************** +#if defined(codered) || defined(gcc) || defined(sourcerygxx) +uint32_t __attribute__((naked)) +CPUprimask(void) +{ + uint32_t ui32Ret; + + // + // Read PRIMASK and disable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " bx lr\n" + : "=r" (ui32Ret)); + + // + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + // + return(ui32Ret); +} +#endif +#if defined(ewarm) +uint32_t +CPUprimask(void) +{ + // + // Read PRIMASK and disable interrupts. + // + __asm(" mrs r0, PRIMASK\n"); + + // + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. + // +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#endif +#if defined(rvmdk) || defined(__ARMCC_VERSION) +__asm uint32_t +CPUprimask(void) +{ + // + // Read PRIMASK and disable interrupts. + // + mrs r0, PRIMASK; + bx lr +} +#endif +#if defined(ccs) +uint32_t +CPUprimask(void) +{ + // + // Read PRIMASK and disable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " bx lr\n"); + + // + // The following keeps the compiler happy, because it wants to see a + // return value from this function. It will generate code to return + // a zero. However, the real return is the "bx lr" above, so the + // return(0) is never executed and the function returns with the value + // you expect in R0. + // + return(0); +} +#endif + +//***************************************************************************** +// +// Wrapper function for the CPSIE instruction. Returns the state of PRIMASK +// on entry. +// +//***************************************************************************** +#if defined(codered) || defined(gcc) || defined(sourcerygxx) +uint32_t __attribute__((naked)) +CPUcpsie(void) +{ + uint32_t ui32Ret; + + // + // Read PRIMASK and enable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " cpsie i\n" + " bx lr\n" + : "=r" (ui32Ret)); + + // + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + // + return(ui32Ret); +} +#endif +#if defined(ewarm) +uint32_t +CPUcpsie(void) +{ + // + // Read PRIMASK and enable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " cpsie i\n"); + + // + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. + // +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#endif +#if defined(rvmdk) || defined(__ARMCC_VERSION) +__asm uint32_t +CPUcpsie(void) +{ + // + // Read PRIMASK and enable interrupts. + // + mrs r0, PRIMASK; + cpsie i; + bx lr +} +#endif +#if defined(ccs) +uint32_t +CPUcpsie(void) +{ + // + // Read PRIMASK and enable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " cpsie i\n" + " bx lr\n"); + + // + // The following keeps the compiler happy, because it wants to see a + // return value from this function. It will generate code to return + // a zero. However, the real return is the "bx lr" above, so the + // return(0) is never executed and the function returns with the value + // you expect in R0. + // + return(0); +} +#endif + +//***************************************************************************** +// +// Wrapper function for the WFI instruction. +// +//***************************************************************************** +#if defined(codered) || defined(gcc) || defined(sourcerygxx) +void __attribute__((naked)) +CPUwfi(void) +{ + // + // Wait for the next interrupt. + // + __asm(" wfi\n" + " bx lr\n"); +} +#endif +#if defined(ewarm) +void +CPUwfi(void) +{ + // + // Wait for the next interrupt. + // + __asm(" wfi\n"); +} +#endif +#if defined(rvmdk) || defined(__ARMCC_VERSION) +__asm void +CPUwfi(void) +{ + // + // Wait for the next interrupt. + // + wfi; + bx lr +} +#endif +#if defined(ccs) +void +CPUwfi(void) +{ + // + // Wait for the next interrupt. + // + __asm(" wfi\n"); +} +#endif + +//***************************************************************************** +// +// Wrapper function for writing the BASEPRI register. +// +//***************************************************************************** +#if defined(codered) || defined(gcc) || defined(sourcerygxx) +void __attribute__((naked)) +CPUbasepriSet(uint32_t ui32NewBasepri) +{ + // + // Set the BASEPRI register + // + __asm(" msr BASEPRI, r0\n" + " bx lr\n"); +} +#endif +#if defined(ewarm) +void +CPUbasepriSet(uint32_t ui32NewBasepri) +{ + // + // Set the BASEPRI register + // + __asm(" msr BASEPRI, r0\n"); +} +#endif +#if defined(rvmdk) || defined(__ARMCC_VERSION) +__asm void +CPUbasepriSet(uint32_t ui32NewBasepri) +{ + // + // Set the BASEPRI register + // + msr BASEPRI, r0; + bx lr +} +#endif +#if defined(ccs) +void +CPUbasepriSet(uint32_t ui32NewBasepri) +{ + // + // Set the BASEPRI register + // + __asm(" msr BASEPRI, r0\n"); +} +#endif + +//***************************************************************************** +// +// Wrapper function for reading the BASEPRI register. +// +//***************************************************************************** +#if defined(codered) || defined(gcc) || defined(sourcerygxx) +uint32_t __attribute__((naked)) +CPUbasepriGet(void) +{ + uint32_t ui32Ret; + + // + // Read BASEPRI + // + __asm(" mrs r0, BASEPRI\n" + " bx lr\n" + : "=r" (ui32Ret)); + + // + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + // + return(ui32Ret); +} +#endif +#if defined(ewarm) +uint32_t +CPUbasepriGet(void) +{ + // + // Read BASEPRI + // + __asm(" mrs r0, BASEPRI\n"); + + // + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. + // +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#endif +#if defined(rvmdk) || defined(__ARMCC_VERSION) +__asm uint32_t +CPUbasepriGet(void) +{ + // + // Read BASEPRI + // + mrs r0, BASEPRI; + bx lr +} +#endif +#if defined(ccs) +uint32_t +CPUbasepriGet(void) +{ + // + // Read BASEPRI + // + __asm(" mrs r0, BASEPRI\n" + " bx lr\n"); + + // + // The following keeps the compiler happy, because it wants to see a + // return value from this function. It will generate code to return + // a zero. However, the real return is the "bx lr" above, so the + // return(0) is never executed and the function returns with the value + // you expect in R0. + // + return(0); +} +#endif diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/crc.c b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/crc.c new file mode 100644 index 0000000000000000000000000000000000000000..55bd4d60484cf2e24aa7a37a87165600daff6225 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/crc.c @@ -0,0 +1,311 @@ +//***************************************************************************** +// +// crc.c - Driver for the CRC module. +// +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup crc_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_ccm.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "driverlib/crc.h" +#include "driverlib/debug.h" + + +//***************************************************************************** +// +//! Set the configuration of CRC functionality with the EC module. +//! +//! \param ui32Base is the base address of the EC module. +//! \param ui32CRCConfig is the configuration of the CRC engine. +//! +//! This function configures the operation of the CRC engine within the EC +//! module. The configuration is specified with the \e ui32CRCConfig argument. +//! It is the logical OR of any of the following options: +//! +//! CRC Initialization Value +//! - \b CRC_CFG_INIT_SEED - Initialize with seed value +//! - \b CRC_CFG_INIT_0 - Initialize to all '0s' +//! - \b CRC_CFG_INIT_1 - Initialize to all '1s' +//! +//! Input Data Size +//! - \b CRC_CFG_SIZE_8BIT - Input data size of 8 bits +//! - \b CRC_CFG_SIZE_32BIT - Input data size of 32 bits +//! +//! Post Process Reverse/Inverse +//! - \b CRC_CFG_RESINV - Result inverse enable +//! - \b CRC_CFG_OBR - Output reverse enable +//! +//! Input Bit Reverse +//! - \b CRC_CFG_IBR - Bit reverse enable +//! +//! Endian Control +//! - \b CRC_CFG_ENDIAN_SBHW - Swap byte in half-word +//! - \b CRC_CFG_ENDIAN_SHW - Swap half-word +//! +//! Operation Type +//! - \b CRC_CFG_TYPE_P8005 - Polynomial 0x8005 +//! - \b CRC_CFG_TYPE_P1021 - Polynomial 0x1021 +//! - \b CRC_CFG_TYPE_P4C11DB7 - Polynomial 0x4C11DB7 +//! - \b CRC_CFG_TYPE_P1EDC6F41 - Polynomial 0x1EDC6F41 +//! - \b CRC_CFG_TYPE_TCPCHKSUM - TCP checksum +//! +//! \return None. +// +//***************************************************************************** +void +CRCConfigSet(uint32_t ui32Base, uint32_t ui32CRCConfig) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == CCM0_BASE); + ASSERT((ui32CRCConfig & CRC_CFG_INIT_SEED) || + (ui32CRCConfig & CRC_CFG_INIT_0) || + (ui32CRCConfig & CRC_CFG_INIT_1) || + (ui32CRCConfig & CRC_CFG_SIZE_8BIT) || + (ui32CRCConfig & CRC_CFG_SIZE_32BIT) || + (ui32CRCConfig & CRC_CFG_RESINV) || + (ui32CRCConfig & CRC_CFG_OBR) || + (ui32CRCConfig & CRC_CFG_IBR) || + (ui32CRCConfig & CRC_CFG_ENDIAN_SBHW) || + (ui32CRCConfig & CRC_CFG_ENDIAN_SHW) || + (ui32CRCConfig & CRC_CFG_TYPE_P8005) || + (ui32CRCConfig & CRC_CFG_TYPE_P1021) || + (ui32CRCConfig & CRC_CFG_TYPE_P4C11DB7) || + (ui32CRCConfig & CRC_CFG_TYPE_P1EDC6F41) || + (ui32CRCConfig & CRC_CFG_TYPE_TCPCHKSUM)); + + // + // Write the control register with the configuration. + // + HWREG(ui32Base + CCM_O_CRCCTRL) = ui32CRCConfig; +} + +//***************************************************************************** +// +//! Write the seed value for CRC operations in the EC module. +//! +//! \param ui32Base is the base address of the EC module. +//! \param ui32Seed is the seed value. +//! +//! This function writes the seed value for use with CRC operations in the +//! EC module. This value is the start value for CRC operations. If this +//! value is not written, then the residual seed from the previous operation +//! is used as the starting value. +//! +//! \note The seed must be written only if \b CRC_CFG_INIT_SEED is +//! set with the CRCConfigSet() function. +// +//***************************************************************************** +void +CRCSeedSet(uint32_t ui32Base, uint32_t ui32Seed) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == CCM0_BASE); + + // + // Write the seed value to the seed register. + // + HWREG(ui32Base + CCM_O_CRCSEED) = ui32Seed; +} + +//***************************************************************************** +// +//! Write data into the EC module for CRC operations. +//! +//! \param ui32Base is the base address of the EC module. +//! \param ui32Data is the data to be written. +//! +//! This function writes either 8 or 32 bits of data into the EC module for +//! CRC operations. The distinction between 8 and 32 bits of data is made +//! when the \b CRC_CFG_SIZE_8BIT or \b CRC_CFG_SIZE_32BIT flag +//! is set using the CRCConfigSet() function. +//! +//! When writing 8 bits of data, ensure the data is in the least significant +//! byte position. The remaining bytes should be written with zero. For +//! example, when writing 0xAB, \e ui32Data should be 0x000000AB. +//! +//! \return None +// +//***************************************************************************** +void +CRCDataWrite(uint32_t ui32Base, uint32_t ui32Data) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == CCM0_BASE); + + // + // Write the data + // + HWREG(ui32Base + CCM_O_CRCDIN) = ui32Data; +} + +//***************************************************************************** +// +//! Reads the result of a CRC operation in the EC module. +//! +//! \param ui32Base is the base address of the EC module. +//! \param bPPResult is \b true to read the post-processed result, or \b false +//! to read the unmodified result. +//! +//! This function reads either the unmodified CRC result or the post +//! processed CRC result from the EC module. The post-processing options +//! are selectable through \b CRC_CFG_RESINV and \b CRC_CFG_OBR +//! parameters in the CRCConfigSet() function. +//! +//! \return The CRC result. +// +//***************************************************************************** +uint32_t +CRCResultRead(uint32_t ui32Base, bool bPPResult) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == CCM0_BASE); + + // + // Depending on the value of bPPResult, read the appropriate register and + // return value. + // + if(bPPResult) + { + return(HWREG(ui32Base + CCM_O_CRCRSLTPP)); + } + else + { + return(HWREG(ui32Base + CCM_O_CRCSEED)); + } +} + +//***************************************************************************** +// +//! Process data to generate a CRC with the EC module. +//! +//! \param ui32Base is the base address of the EC module. +//! \param pui32DataIn is a pointer to an array of data that is processed. +//! \param ui32DataLength is the number of data items that are processed +//! to produce the CRC. +//! \param bPPResult is \b true to read the post-processed result, or \b false +//! to read the unmodified result. +//! +//! This function processes an array of data to produce a CRC result. +//! +//! The data in the array pointed to be \e pui32DataIn is either an array +//! of bytes or an array or words depending on the selection of the input +//! data size options \b CRC_CFG_SIZE_8BIT and +//! \b CRC_CFG_SIZE_32BIT. +//! +//! This function returns either the unmodified CRC result or the +//! post- processed CRC result from the EC module. The post-processing +//! options are selectable through \b CRC_CFG_RESINV and +//! \b CRC_CFG_OBR parameters. +//! +//! \return The CRC result. +// +//***************************************************************************** +uint32_t +CRCDataProcess(uint32_t ui32Base, uint32_t *pui32DataIn, + uint32_t ui32DataLength, bool bPPResult) +{ + uint8_t *pui8DataIn; + + // + // Check the arguments. + // + ASSERT(ui32Base == CCM0_BASE); + + // + // See if the CRC is operating in 8-bit or 32-bit mode. + // + if(HWREG(ui32Base + CCM_O_CRCCTRL) & CCM_CRCCTRL_SIZE) + { + // + // The CRC is operating in 8-bit mode, so create an 8-bit pointer to + // the data. + // + pui8DataIn = (uint8_t *)pui32DataIn; + + // + // Loop through the input data. + // + while(ui32DataLength--) + { + // + // Write the next data byte. + // + HWREG(ui32Base + CCM_O_CRCDIN) = *pui8DataIn++; + } + } + else + { + // + // The CRC is operating in 32-bit mode, so loop through the input data. + // + while(ui32DataLength--) + { + // + // Write the next data word. + // + HWREG(ui32Base + CCM_O_CRCDIN) = *pui32DataIn++; + } + } + + // + // Return the result. + // + return(CRCResultRead(ui32Base, bPPResult)); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/des.c b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/des.c new file mode 100644 index 0000000000000000000000000000000000000000..1b6e86a2a8473413e5625e3a782976d85b1bbc02 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/des.c @@ -0,0 +1,807 @@ +//***************************************************************************** +// +// des.c - Driver for the DES data transformation. +// +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup des_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_des.h" +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/des.h" +#include "driverlib/interrupt.h" + +//***************************************************************************** +// +//! Resets the DES Module. +//! +//! \param ui32Base is the base address of the DES module. +//! +//! This function performs a soft-reset sequence of the DES module. +//! +//! \return None. +// +//***************************************************************************** +void +DESReset(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == DES_BASE); + + // + // Trigger the soft reset. + // + HWREG(ui32Base + DES_O_SYSCONFIG) |= DES_SYSCONFIG_SOFTRESET; + + // + // Wait for the reset to finish. + // + while((HWREG(ui32Base + DES_O_SYSSTATUS) & + DES_SYSSTATUS_RESETDONE) == 0) + { + } +} + +//***************************************************************************** +// +//! Configures the DES module for operation. +//! +//! \param ui32Base is the base address of the DES module. +//! \param ui32Config is the configuration of the DES module. +//! +//! This function configures the DES module for operation. +//! +//! The \e ui32Config parameter is a bit-wise OR of a number of configuration +//! flags. The valid flags are grouped below based on their function. +//! +//! The direction of the operation is specified with one of the following two +//! flags. Only one is permitted. +//! +//! - \b DES_CFG_DIR_ENCRYPT - Encryption +//! - \b DES_CFG_DIR_DECRYPT - Decryption +//! +//! The operational mode of the DES engine is specified with one of the +//! following flags. Only one is permitted. +//! +//! - \b DES_CFG_MODE_ECB - Electronic Codebook Mode +//! - \b DES_CFG_MODE_CBC - Cipher-Block Chaining Mode +//! - \b DES_CFG_MODE_CFB - Cipher Feedback Mode +//! +//! The selection of single DES or triple DES is specified with one of the +//! following two flags. Only one is permitted. +//! +//! - \b DES_CFG_SINGLE - Single DES +//! - \b DES_CFG_TRIPLE - Triple DES +//! +//! \return None. +// +//***************************************************************************** +void +DESConfigSet(uint32_t ui32Base, uint32_t ui32Config) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == DES_BASE); + + // + // Backup the save context field. + // + ui32Config |= (HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_CONTEXT); + + // + // Write the control register. + // + HWREG(ui32Base + DES_O_CTRL) = ui32Config; +} + +//***************************************************************************** +// +//! Sets the key used for DES operations. +//! +//! \param ui32Base is the base address of the DES module. +//! \param pui32Key is a pointer to an array that holds the key +//! +//! This function sets the key used for DES operations. +//! +//! \e pui32Key should be 64 bits long (2 words) if single DES is being used or +//! 192 bits (6 words) if triple DES is being used. +//! +//! \return None. +// +//***************************************************************************** +void +DESKeySet(uint32_t ui32Base, uint32_t *pui32Key) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == DES_BASE); + + // + // Write the first part of the key. + // + HWREG(ui32Base + DES_O_KEY1_L) = pui32Key[0]; + HWREG(ui32Base + DES_O_KEY1_H) = pui32Key[1]; + + // + // If we are performing tripe DES, then write the key registers for + // the second and third rounds. + // + if(HWREG(ui32Base + DES_O_CTRL) & DES_CFG_TRIPLE) + { + HWREG(ui32Base + DES_O_KEY2_L) = pui32Key[2]; + HWREG(ui32Base + DES_O_KEY2_H) = pui32Key[3]; + HWREG(ui32Base + DES_O_KEY3_L) = pui32Key[4]; + HWREG(ui32Base + DES_O_KEY3_H) = pui32Key[5]; + } +} + +//***************************************************************************** +// +//! Sets the initialization vector in the DES module. +//! +//! \param ui32Base is the base address of the DES module. +//! \param pui32IVdata is a pointer to an array of 64 bits (2 words) of data to +//! be written into the initialization vectors registers. +//! +//! This function sets the initialization vector in the DES module. It returns +//! true if the registers were successfully written. If the context registers +//! cannot be written at the time the function was called, then false is +//! returned. +//! +//! \return True or false. +// +//***************************************************************************** +bool +DESIVSet(uint32_t ui32Base, uint32_t *pui32IVdata) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == DES_BASE); + + // + // Check to see if context registers can be overwritten. If not, return + // false. + // + if((HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_CONTEXT) == 0) + { + return(false); + } + + // + // Write the initialization vector registers. + // + HWREG(ui32Base + DES_O_IV_L) = pui32IVdata[0]; + HWREG(ui32Base + DES_O_IV_H) = pui32IVdata[1]; + + // + // Return true to indicate the write was successful. + // + return(true); +} + +//***************************************************************************** +// +//! Sets the crytographic data length in the DES module. +//! +//! \param ui32Base is the base address of the DES module. +//! \param ui32Length is the length of the data in bytes. +//! +//! This function writes the cryptographic data length into the DES module. +//! When this register is written, the engine is triggered to start using this +//! context. +//! +//! \note Data lengths up to (2^32 - 1) bytes are allowed. +//! +//! \return None. +// +//***************************************************************************** +void +DESLengthSet(uint32_t ui32Base, uint32_t ui32Length) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == DES_BASE); + + // + // Write the length register. + // + HWREG(ui32Base + DES_O_LENGTH) = ui32Length; +} + +//***************************************************************************** +// +//! Reads plaintext/ciphertext from data registers without blocking +//! +//! \param ui32Base is the base address of the DES module. +//! \param pui32Dest is a pointer to an array of 2 words. +//! +//! This function returns true if the data was ready when the function was +//! called. If the data was not ready, false is returned. +//! +//! \return True or false. +// +//***************************************************************************** +bool +DESDataReadNonBlocking(uint32_t ui32Base, uint32_t *pui32Dest) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == DES_BASE); + + // + // Check to see if the data is ready to be read. + // + if((DES_CTRL_OUTPUT_READY & (HWREG(ui32Base + DES_O_CTRL))) == 0) + { + return(false); + } + + // + // Read two words of data from the data registers. + // + pui32Dest[0] = HWREG(DES_BASE + DES_O_DATA_L); + pui32Dest[1] = HWREG(DES_BASE + DES_O_DATA_H); + + // + // Return true to indicate a successful write. + // + return(true); +} + +//***************************************************************************** +// +//! Reads plaintext/ciphertext from data registers with blocking. +//! +//! \param ui32Base is the base address of the DES module. +//! \param pui32Dest is a pointer to an array of bytes. +//! +//! This function waits until the DES module is finished and encrypted or +//! decrypted data is ready. The output data is then stored in the pui32Dest +//! array. +//! +//! \return None +// +//***************************************************************************** +void +DESDataRead(uint32_t ui32Base, uint32_t *pui32Dest) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == DES_BASE); + + // + // Wait for data output to be ready. + // + while((HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_OUTPUT_READY) == 0) + { + } + + // + // Read two words of data from the data registers. + // + pui32Dest[0] = HWREG(DES_BASE + DES_O_DATA_L); + pui32Dest[1] = HWREG(DES_BASE + DES_O_DATA_H); +} + +//***************************************************************************** +// +//! Writes plaintext/ciphertext to data registers without blocking +//! +//! \param ui32Base is the base address of the DES module. +//! \param pui32Src is a pointer to an array of 2 words. +//! +//! This function returns false if the DES module is not ready to accept +//! data. It returns true if the data was written successfully. +//! +//! \return true or false. +// +//***************************************************************************** +bool +DESDataWriteNonBlocking(uint32_t ui32Base, uint32_t *pui32Src) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == DES_BASE); + + // + // Check if the DES module is ready to encrypt or decrypt data. If it + // is not, return false. + // + if(!(DES_CTRL_INPUT_READY & (HWREG(ui32Base + DES_O_CTRL)))) + { + return(false); + } + + // + // Write the data. + // + HWREG(DES_BASE + DES_O_DATA_L) = pui32Src[0]; + HWREG(DES_BASE + DES_O_DATA_H) = pui32Src[1]; + + // + // Return true to indicate a successful write. + // + return(true); +} + +//***************************************************************************** +// +//! Writes plaintext/ciphertext to data registers without blocking +//! +//! \param ui32Base is the base address of the DES module. +//! \param pui32Src is a pointer to an array of bytes. +//! +//! This function waits until the DES module is ready before writing the +//! data contained in the pui32Src array. +//! +//! \return None. +// +//***************************************************************************** +void +DESDataWrite(uint32_t ui32Base, uint32_t *pui32Src) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == DES_BASE); + + // + // Wait for the input ready bit to go high. + // + while(((HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_INPUT_READY)) == 0) + { + } + + // + // Write the data. + // + HWREG(DES_BASE + DES_O_DATA_L) = pui32Src[0]; + HWREG(DES_BASE + DES_O_DATA_H) = pui32Src[1]; +} + +//***************************************************************************** +// +//! Processes blocks of data through the DES module. +//! +//! \param ui32Base is the base address of the DES module. +//! \param pui32Src is a pointer to an array of words that contains the +//! source data for processing. +//! \param pui32Dest is a pointer to an array of words consisting of the +//! processed data. +//! \param ui32Length is the length of the cryptographic data in bytes. +//! It must be a multiple of eight. +//! +//! This function takes the data contained in the pui32Src array and processes +//! it using the DES engine. The resulting data is stored in the +//! pui32Dest array. The function blocks until all of the data has been +//! processed. If processing is successful, the function returns true. +//! +//! \note This functions assumes that the DES module has been configured, +//! and initialization values and keys have been written. +//! +//! \return true or false. +// +//***************************************************************************** +bool +DESDataProcess(uint32_t ui32Base, uint32_t *pui32Src, uint32_t *pui32Dest, + uint32_t ui32Length) +{ + uint32_t ui32Count; + + // + // Check the arguments. + // + ASSERT(ui32Base == DES_BASE); + ASSERT((ui32Length % 8) == 0); + + // + // Write the length register first. This triggers the engine to start + // using this context. + // + HWREG(ui32Base + DES_O_LENGTH) = ui32Length; + + // + // Now loop until the blocks are written. + // + for(ui32Count = 0; ui32Count < (ui32Length / 4); ui32Count += 2) + { + // + // Check if the input ready is fine + // + while((DES_CTRL_INPUT_READY & (HWREG(ui32Base + DES_O_CTRL))) == 0) + { + } + + // + // Write the block data. + // + DESDataWriteNonBlocking(ui32Base, pui32Src + ui32Count); + + // + // Wait for the output ready + // + while((DES_CTRL_OUTPUT_READY & (HWREG(ui32Base + DES_O_CTRL))) == 0) + { + } + + // + // Read the processed data block. + // + DESDataReadNonBlocking(ui32Base, pui32Dest + ui32Count); + } + + // + // Return true to indicate the process was successful. + // + return(true); +} + +//***************************************************************************** +// +//! Returns the current interrupt status of the DES module. +//! +//! \param ui32Base is the base address of the DES module. +//! \param bMasked is \b false if the raw interrupt status is required and +//! \b true if the masked interrupt status is required. +//! +//! This function gets the current interrupt status of the DES module. +//! The value returned is a logical OR of the following values: +//! +//! - \b DES_INT_CONTEXT_IN - Context interrupt +//! - \b DES_INT_DATA_IN - Data input interrupt +//! - \b DES_INT_DATA_OUT_INT - Data output interrupt +//! - \b DES_INT_DMA_CONTEXT_IN - Context DMA done interrupt +//! - \b DES_INT_DMA_DATA_IN - Data input DMA done interrupt +//! - \b DES_INT_DMA_DATA_OUT - Data output DMA done interrupt +//! +//! \return A bit mask of the current interrupt status. +// +//***************************************************************************** +uint32_t +DESIntStatus(uint32_t ui32Base, bool bMasked) +{ + uint32_t ui32Status, ui32Enable; + + // + // Check the arguments. + // + ASSERT(ui32Base == DES_BASE); + + // + // Read the status register and return the value. + // + ui32Status = HWREG(ui32Base + DES_O_IRQSTATUS); + if(bMasked) + { + ui32Enable = HWREG(ui32Base + DES_O_IRQENABLE); + return((ui32Status & ui32Enable) | + (HWREG(ui32Base + DES_O_DMAMIS) << 16)); + } + else + { + return(ui32Status | (HWREG(ui32Base + DES_O_DMARIS) << 16)); + } +} + +//***************************************************************************** +// +//! Enables interrupts in the DES module. +//! +//! \param ui32Base is the base address of the DES module. +//! \param ui32IntFlags is a bit mask of the interrupts to be enabled. +//! +//! \e ui32IntFlags should be a logical OR of one or more of the following +//! values: +//! +//! - \b DES_INT_CONTEXT_IN - Context interrupt +//! - \b DES_INT_DATA_IN - Data input interrupt +//! - \b DES_INT_DATA_OUT - Data output interrupt +//! - \b DES_INT_DMA_CONTEXT_IN - Context DMA done interrupt +//! - \b DES_INT_DMA_DATA_IN - Data input DMA done interrupt +//! - \b DES_INT_DMA_DATA_OUT - Data output DMA done interrupt +//! +//! \return None. +// +//***************************************************************************** +void +DESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == DES_BASE); + ASSERT((ui32IntFlags & DES_INT_CONTEXT_IN) || + (ui32IntFlags & DES_INT_DATA_IN) || + (ui32IntFlags & DES_INT_DATA_OUT) || + (ui32IntFlags & DES_INT_DMA_CONTEXT_IN) || + (ui32IntFlags & DES_INT_DMA_DATA_IN) || + (ui32IntFlags & DES_INT_DMA_DATA_OUT)); + + // + // Enable the interrupts from the flags. + // + HWREG(ui32Base + DES_O_DMAIM) |= (ui32IntFlags & 0x00070000) >> 16; + HWREG(ui32Base + DES_O_IRQENABLE) |= ui32IntFlags & 0x0000ffff; +} + +//***************************************************************************** +// +//! Disables interrupts in the DES module. +//! +//! \param ui32Base is the base address of the DES module. +//! \param ui32IntFlags is a bit mask of the interrupts to be disabled. +//! +//! This function disables interrupt sources in the DES module. +//! \e ui32IntFlags should be a logical OR of one or more of the following +//! values: +//! +//! - \b DES_INT_CONTEXT_IN - Context interrupt +//! - \b DES_INT_DATA_IN - Data input interrupt +//! - \b DES_INT_DATA_OUT - Data output interrupt +//! - \b DES_INT_DMA_CONTEXT_IN - Context DMA done interrupt +//! - \b DES_INT_DMA_DATA_IN - Data input DMA done interrupt +//! - \b DES_INT_DMA_DATA_OUT - Data output DMA done interrupt +//! +//! \return None. +// +//***************************************************************************** +void +DESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == DES_BASE); + ASSERT((ui32IntFlags & DES_INT_CONTEXT_IN) || + (ui32IntFlags & DES_INT_DATA_IN) || + (ui32IntFlags & DES_INT_DATA_OUT) || + (ui32IntFlags & DES_INT_DMA_CONTEXT_IN) || + (ui32IntFlags & DES_INT_DMA_DATA_IN) || + (ui32IntFlags & DES_INT_DMA_DATA_OUT)); + + // + // Clear the interrupts from the flags. + // + HWREG(ui32Base + DES_O_DMAIM) &= ~((ui32IntFlags & 0x00070000) >> 16); + HWREG(ui32Base + DES_O_IRQENABLE) &= ~(ui32IntFlags & 0x0000ffff); +} + +//***************************************************************************** +// +//! Clears interrupts in the DES module. +//! +//! \param ui32Base is the base address of the DES module. +//! \param ui32IntFlags is a bit mask of the interrupts to be disabled. +//! +//! This function disables interrupt sources in the DES module. +//! \e ui32IntFlags should be a logical OR of one or more of the following +//! values: +//! +//! - \b DES_INT_DMA_CONTEXT_IN - Context interrupt +//! - \b DES_INT_DMA_DATA_IN - Data input interrupt +//! - \b DES_INT_DMA_DATA_OUT - Data output interrupt +//! +//! \note The DMA done interrupts are the only interrupts that can be cleared. +//! The remaining interrupts can be disabled instead using DESIntDisable(). +//! +//! \return None. +// +//***************************************************************************** +void +DESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == DES_BASE); + ASSERT((ui32IntFlags & DES_INT_DMA_CONTEXT_IN) || + (ui32IntFlags & DES_INT_DMA_DATA_IN) || + (ui32IntFlags & DES_INT_DMA_DATA_OUT)); + + HWREG(ui32Base + DES_O_DMAIC) = (ui32IntFlags & 0x00070000) >> 16; +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the DES module. +//! +//! \param ui32Base is the base address of the DES module. +//! \param pfnHandler is a pointer to the function to be called when the +//! enabled DES interrupts occur. +//! +//! This function registers the interrupt handler in the interrupt vector +//! table, and enables DES interrupts on the interrupt controller; specific DES +//! interrupt sources must be enabled using DESIntEnable(). The interrupt +//! handler being registered must clear the source of the interrupt using +//! DESIntClear(). +//! +//! If the application is using a static interrupt vector table stored in +//! flash, then it is not necessary to register the interrupt handler this way. +//! Instead, IntEnable() should be used to enable DES interrupts on the +//! interrupt controller. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +DESIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == DES_BASE); + + // + // Register the interrupt handler. + // + IntRegister(INT_DES0_TM4C129, pfnHandler); + + // + // Enable the interrupt. + // + IntEnable(INT_DES0_TM4C129); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the DES module. +//! +//! \param ui32Base is the base address of the DES module. +//! +//! This function unregisters the previously registered interrupt handler and +//! disables the interrupt in the interrupt controller. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +DESIntUnregister(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == DES_BASE); + + // + // Disable the interrupt. + // + IntDisable(INT_DES0_TM4C129); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_DES0_TM4C129); +} + +//***************************************************************************** +// +//! Enables DMA request sources in the DES module. +//! +//! \param ui32Base is the base address of the DES module. +//! \param ui32Flags is a bit mask of the DMA requests to be enabled. +//! +//! This function enables DMA request sources in the DES module. The +//! \e ui32Flags parameter should be the logical OR of any of the following: +//! +//! - \b DES_DMA_CONTEXT_IN - Context In +//! - \b DES_DMA_DATA_OUT - Data Out +//! - \b DES_DMA_DATA_IN - Data In +//! +//! \return None. +// +//***************************************************************************** +void +DESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == DES_BASE); + ASSERT((ui32Flags & DES_DMA_CONTEXT_IN) || + (ui32Flags & DES_DMA_DATA_OUT) || + (ui32Flags & DES_DMA_DATA_IN)); + + // + // Set the data in and data out DMA request enable bits. + // + HWREG(ui32Base + DES_O_SYSCONFIG) |= ui32Flags; +} + +//***************************************************************************** +// +//! Disables DMA request sources in the DES module. +//! +//! \param ui32Base is the base address of the DES module. +//! \param ui32Flags is a bit mask of the DMA requests to be disabled. +//! +//! This function disables DMA request sources in the DES module. The +//! \e ui32Flags parameter should be the logical OR of any of the following: +//! +//! - \b DES_DMA_CONTEXT_IN - Context In +//! - \b DES_DMA_DATA_OUT - Data Out +//! - \b DES_DMA_DATA_IN - Data In +//! +//! \return None. +// +//***************************************************************************** +void +DESDMADisable(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == DES_BASE); + ASSERT((ui32Flags & DES_DMA_CONTEXT_IN) || + (ui32Flags & DES_DMA_DATA_OUT) || + (ui32Flags & DES_DMA_DATA_IN)); + + // + // Disable the DMA sources. + // + HWREG(ui32Base + DES_O_SYSCONFIG) &= ~ui32Flags; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/eeprom.c b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/eeprom.c new file mode 100644 index 0000000000000000000000000000000000000000..6daae87be0b81ddb569d6bc3e69e6e05621eca57 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/eeprom.c @@ -0,0 +1,1156 @@ +//***************************************************************************** +// +// eeprom.c - Driver for programming the on-chip EEPROM. +// +// Copyright (c) 2010-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#include +#include +#include "inc/hw_eeprom.h" +#include "inc/hw_flash.h" +#include "inc/hw_ints.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/flash.h" +#include "driverlib/interrupt.h" +#include "driverlib/sysctl.h" +#include "driverlib/eeprom.h" + +//***************************************************************************** +// +//! \addtogroup eeprom_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Useful macros to extract the number of EEPROM blocks available on the target +// device and the total EEPROM storage in bytes from the EESIZE register. +// +//***************************************************************************** +#define BLOCKS_FROM_EESIZE(x) (((x) & EEPROM_EESIZE_BLKCNT_M) >> \ + EEPROM_EESIZE_BLKCNT_S) +#define SIZE_FROM_EESIZE(x) ((((x) & EEPROM_EESIZE_WORDCNT_M) >> \ + EEPROM_EESIZE_WORDCNT_S) * 4) + +//***************************************************************************** +// +// Useful macro to extract the offset from a linear address. +// +//***************************************************************************** +#define OFFSET_FROM_ADDR(x) (((x) >> 2) & 0x0F) + +//***************************************************************************** +// +// The key value required to initiate a mass erase. +// +//***************************************************************************** +#define EEPROM_MASS_ERASE_KEY ((uint32_t)0xE37B << EEPROM_EEDBGME_KEY_S) + +//***************************************************************************** +// +// This function implements a workaround for a bug in Blizzard rev A silicon. +// It ensures that only the 1KB flash sector containing a given EEPROM address +// is erased if an erase/copy operation is required as a result of a following +// EEPROM write. +// +//***************************************************************************** +static void +_EEPROMSectorMaskSet(uint32_t ui32Address) +{ + uint32_t ui32Mask; + + // + // Determine which page contains the passed EEPROM address. The 2KB EEPROM + // is implemented in 16KB of flash with each 1KB sector of flash holding + // values for 32 consecutive EEPROM words (or 128 bytes). + // + ui32Mask = ~(1 << (ui32Address >> 7)); + + SysCtlDelay(10); + HWREG(0x400FD0FC) = 3; + SysCtlDelay(10); + HWREG(0x400AE2C0) = ui32Mask; + SysCtlDelay(10); + HWREG(0x400FD0FC) = 0; + SysCtlDelay(10); +} + +//***************************************************************************** +// +// Clear the FSM sector erase mask to ensure that any following main array +// flash erase operations operate as expected. +// +//***************************************************************************** +static void +_EEPROMSectorMaskClear(void) +{ + SysCtlDelay(10); + HWREG(0x400FD0FC) = 3; + SysCtlDelay(10); + HWREG(0x400AE2C0) = 0; + SysCtlDelay(10); + HWREG(0x400FD0FC) = 0; + SysCtlDelay(10); +} + +//***************************************************************************** +// +// Block until the EEPROM peripheral is not busy. +// +//***************************************************************************** +static void +_EEPROMWaitForDone(void) +{ + // + // Is the EEPROM still busy? + // + while(HWREG(EEPROM_EEDONE) & EEPROM_EEDONE_WORKING) + { + // + // Spin while EEPROM is busy. + // + } +} + +//***************************************************************************** +// +//! Performs any necessary recovery in case of power failures during write. +//! +//! This function \b must be called after SysCtlPeripheralEnable() and before +//! the EEPROM is accessed. It is used to check for errors in the EEPROM state +//! such as from power failure during a previous write operation. The function +//! detects these errors and performs as much recovery as possible. +//! +//! If \b EEPROM_INIT_ERROR is returned, the EEPROM was unable to recover its +//! state. If power is stable when this occurs, this indicates a fatal +//! error and is likely an indication that the EEPROM memory has exceeded its +//! specified lifetime write/erase specification. If the supply voltage is +//! unstable when this return code is observed, retrying the operation once the +//! voltage is stabilized may clear the error. +//! +//! Failure to call this function after a reset may lead to incorrect operation +//! or permanent data loss if the EEPROM is later written. +//! +//! \return Returns \b EEPROM_INIT_OK if no errors were detected or \b +//! EEPROM_INIT_ERROR if the EEPROM peripheral cannot currently recover from +//! an interrupted write or erase operation. +// +//***************************************************************************** +uint32_t +EEPROMInit(void) +{ + uint32_t ui32Status; + + // + // Insert a small delay (6 cycles + call overhead) to guard against the + // possibility that this function is called immediately after the EEPROM + // peripheral is enabled. Without this delay, there is a slight chance + // that the first EEPROM register read will fault if you are using a + // compiler with a ridiculously good optimizer! + // + SysCtlDelay(2); + + // + // Make sure the EEPROM has finished any ongoing processing. + // + _EEPROMWaitForDone(); + + // + // Read the EESUPP register to see if any errors have been reported. + // + ui32Status = HWREG(EEPROM_EESUPP); + + // + // Did an error of some sort occur during initialization? + // + if(ui32Status & (EEPROM_EESUPP_PRETRY | EEPROM_EESUPP_ERETRY)) + { + return(EEPROM_INIT_ERROR); + } + + // + // Perform a second EEPROM reset. + // + SysCtlPeripheralReset(SYSCTL_PERIPH_EEPROM0); + + // + // Wait for the EEPROM to complete its reset processing once again. + // + SysCtlDelay(2); + _EEPROMWaitForDone(); + + // + // Read EESUPP once again to determine if any error occurred. + // + ui32Status = HWREG(EEPROM_EESUPP); + + // + // Was an error reported following the second reset? + // + if(ui32Status & (EEPROM_EESUPP_PRETRY | EEPROM_EESUPP_ERETRY)) + { + return(EEPROM_INIT_ERROR); + } + + // + // The EEPROM does not indicate that any error occurred. + // + return(EEPROM_INIT_OK); +} + + +//***************************************************************************** +// +//! Determines the size of the EEPROM. +//! +//! This function returns the size of the EEPROM in bytes. +//! +//! \return Returns the total number of bytes in the EEPROM. +// +//***************************************************************************** +uint32_t +EEPROMSizeGet(void) +{ + // + // Return the size of the EEPROM in bytes. + // + return(SIZE_FROM_EESIZE(HWREG(EEPROM_EESIZE))); +} + +//***************************************************************************** +// +//! Determines the number of blocks in the EEPROM. +//! +//! This function may be called to determine the number of blocks in the +//! EEPROM. Each block is the same size and the number of bytes of storage +//! contained in a block may be determined by dividing the size of the device, +//! obtained via a call to the EEPROMSizeGet() function, by the number of +//! blocks returned by this function. +//! +//! \return Returns the total number of blocks in the device EEPROM. +// +//***************************************************************************** +uint32_t +EEPROMBlockCountGet(void) +{ + // + // Extract the number of blocks and return it to the caller. + // +#ifdef EEPROM_SIZE_LIMIT + // + // If a size limit has been specified, fake the number of blocks to match. + // + return(EEPROM_SIZE_LIMIT / 48); +#else + // + // Return the actual number of blocks supported by the hardware. + // + return(BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE))); +#endif +} + +//***************************************************************************** +// +//! Reads data from the EEPROM. +//! +//! \param pui32Data is a pointer to storage for the data read from the EEPROM. +//! This pointer must point to at least \e ui32Count bytes of available memory. +//! \param ui32Address is the byte address within the EEPROM from which data is +//! to be read. This value must be a multiple of 4. +//! \param ui32Count is the number of bytes of data to read from the EEPROM. +//! This value must be a multiple of 4. +//! +//! This function may be called to read a number of words of data from a +//! word-aligned address within the EEPROM. Data read is copied into the +//! buffer pointed to by the \e pui32Data parameter. +//! +//! \return None. +// +//***************************************************************************** +void +EEPROMRead(uint32_t *pui32Data, uint32_t ui32Address, uint32_t ui32Count) +{ + // + // Check parameters in a debug build. + // + ASSERT(pui32Data); + ASSERT(ui32Address < SIZE_FROM_EESIZE(HWREG(EEPROM_EESIZE))); + ASSERT((ui32Address + ui32Count) <= + SIZE_FROM_EESIZE(HWREG(EEPROM_EESIZE))); + ASSERT((ui32Address & 3) == 0); + ASSERT((ui32Count & 3) == 0); + + // + // Set the block and offset appropriately to read the first word. + // + HWREG(EEPROM_EEBLOCK) = EEPROMBlockFromAddr(ui32Address); + HWREG(EEPROM_EEOFFSET) = OFFSET_FROM_ADDR(ui32Address); + + // + // Convert the byte count to a word count. + // + ui32Count /= 4; + + // + // Read each word in turn. + // + while(ui32Count) + { + // + // Read the next word through the autoincrementing register. + // + *pui32Data = HWREG(EEPROM_EERDWRINC); + + // + // Move on to the next word. + // + pui32Data++; + ui32Count--; + + // + // Do we need to move to the next block? This is the case if the + // offset register has just wrapped back to 0. Note that we only + // write the block register if we have more data to read. If this + // register is written, the hardware expects a read or write operation + // next. If a mass erase is requested instead, the mass erase will + // fail. + // + if(ui32Count && (HWREG(EEPROM_EEOFFSET) == 0)) + { + HWREG(EEPROM_EEBLOCK) += 1; + } + } +} + +//***************************************************************************** +// +//! Writes data to the EEPROM. +//! +//! \param pui32Data points to the first word of data to write to the EEPROM. +//! \param ui32Address defines the byte address within the EEPROM that the data +//! is to be written to. This value must be a multiple of 4. +//! \param ui32Count defines the number of bytes of data that is to be written. +//! This value must be a multiple of 4. +//! +//! This function may be called to write data into the EEPROM at a given +//! word-aligned address. The call is synchronous and returns only after +//! all data has been written or an error occurs. +//! +//! \return Returns 0 on success or non-zero values on failure. Failure codes +//! are logical OR combinations of \b EEPROM_RC_WRBUSY, \b EEPROM_RC_NOPERM, +//! \b EEPROM_RC_WKCOPY, \b EEPROM_RC_WKERASE, and \b EEPROM_RC_WORKING. +// +//***************************************************************************** +uint32_t +EEPROMProgram(uint32_t *pui32Data, uint32_t ui32Address, uint32_t ui32Count) +{ + uint32_t ui32Status; + + // + // Check parameters in a debug build. + // + ASSERT(pui32Data); + ASSERT(ui32Address < SIZE_FROM_EESIZE(HWREG(EEPROM_EESIZE))); + ASSERT((ui32Address + ui32Count) <= + SIZE_FROM_EESIZE(HWREG(EEPROM_EESIZE))); + ASSERT((ui32Address & 3) == 0); + ASSERT((ui32Count & 3) == 0); + + // + // Make sure the EEPROM is idle before we start. + // + do + { + // + // Read the status. + // + ui32Status = HWREG(EEPROM_EEDONE); + } + while(ui32Status & EEPROM_EEDONE_WORKING); + + // + // Set the block and offset appropriately to program the first word. + // + HWREG(EEPROM_EEBLOCK) = EEPROMBlockFromAddr(ui32Address); + HWREG(EEPROM_EEOFFSET) = OFFSET_FROM_ADDR(ui32Address); + + // + // Convert the byte count to a word count. + // + ui32Count /= 4; + + // + // Write each word in turn. + // + while(ui32Count) + { + // + // This is a workaround for a silicon problem on Blizzard rev A. We + // need to do this before every word write to ensure that we don't + // have problems in multi-word writes that span multiple flash sectors. + // + if(CLASS_IS_TM4C123 && REVISION_IS_A0) + { + _EEPROMSectorMaskSet(ui32Address); + } + + // + // Write the next word through the autoincrementing register. + // + HWREG(EEPROM_EERDWRINC) = *pui32Data; + + // + // Wait a few cycles. In some cases, the WRBUSY bit is not set + // immediately and this prevents us from dropping through the polling + // loop before the bit is set. + // + SysCtlDelay(10); + + // + // Wait for the write to complete. + // + do + { + // + // Read the status. + // + ui32Status = HWREG(EEPROM_EEDONE); + } + while(ui32Status & EEPROM_EEDONE_WORKING); + + // + // Make sure we completed the write without errors. Note that we + // must check this per-word because write permission can be set per + // block resulting in only a section of the write not being performed. + // + if(ui32Status & EEPROM_EEDONE_NOPERM) + { + // + // An error was reported that would prevent the values from + // being written correctly. + // + if(CLASS_IS_TM4C123 && REVISION_IS_A0) + { + _EEPROMSectorMaskClear(); + } + return(ui32Status); + } + + // + // Move on to the next word. + // + pui32Data++; + ui32Count--; + + // + // Do we need to move to the next block? This is the case if the + // offset register has just wrapped back to 0. Note that we only + // write the block register if we have more data to read. If this + // register is written, the hardware expects a read or write operation + // next. If a mass erase is requested instead, the mass erase will + // fail. + // + if(ui32Count && (HWREG(EEPROM_EEOFFSET) == 0)) + { + HWREG(EEPROM_EEBLOCK) += 1; + } + } + + // + // Clear the sector protection bits to prevent possible problems when + // programming the main flash array later. + // + if(CLASS_IS_TM4C123 && REVISION_IS_A0) + { + _EEPROMSectorMaskClear(); + } + + // + // Return the current status to the caller. + // + return(HWREG(EEPROM_EEDONE)); +} + +//***************************************************************************** +// +//! Writes a word to the EEPROM. +//! +//! \param ui32Data is the word to write to the EEPROM. +//! \param ui32Address defines the byte address within the EEPROM to which the +//! data is to be written. This value must be a multiple of 4. +//! +//! This function is intended to allow EEPROM programming under interrupt +//! control. It may be called to start the process of writing a single word of +//! data into the EEPROM at a given word-aligned address. The call is +//! asynchronous and returns immediately without waiting for the write to +//! complete. Completion of the operation is signaled by means of an +//! interrupt from the EEPROM module. The EEPROM peripheral shares a single +//! interrupt vector with the flash memory subsystem, \b INT_FLASH. +//! +//! \return Returns status and error information in the form of a logical OR +//! combinations of \b EEPROM_RC_WRBUSY, \b EEPROM_RC_NOPERM, +//! \b EEPROM_RC_WKCOPY, \b EEPROM_RC_WKERASE and \b EEPROM_RC_WORKING. Flags +//! \b EEPROM_RC_WKCOPY, \b EEPROM_RC_WKERASE, and \b EEPROM_RC_WORKING are +//! expected in normal operation and do not indicate an error. +// +//***************************************************************************** +uint32_t +EEPROMProgramNonBlocking(uint32_t ui32Data, uint32_t ui32Address) +{ + // + // Check parameters in a debug build. + // + ASSERT(ui32Address < SIZE_FROM_EESIZE(HWREG(EEPROM_EESIZE))); + ASSERT((ui32Address & 3) == 0); + + // + // This is a workaround for a silicon problem on Blizzard rev A. + // + if(CLASS_IS_TM4C123 && REVISION_IS_A0) + { + _EEPROMSectorMaskSet(ui32Address); + } + + // + // Set the block and offset appropriately to program the desired word. + // + HWREG(EEPROM_EEBLOCK) = EEPROMBlockFromAddr(ui32Address); + HWREG(EEPROM_EEOFFSET) = OFFSET_FROM_ADDR(ui32Address); + + // + // Write the new word using the auto-incrementing register just in case + // the caller wants to write follow-on words using direct register access + // + HWREG(EEPROM_EERDWRINC) = ui32Data; + + // + // Return the current status to the caller. + // + return(HWREG(EEPROM_EEDONE)); +} + +//***************************************************************************** +// +//! Erases the EEPROM and returns it to the factory default condition. +//! +//! This function completely erases the EEPROM and removes any and +//! all access protection on its blocks, leaving the device in the factory +//! default condition. After this operation, all EEPROM words contain the +//! value 0xFFFFFFFF and all blocks are accessible for both read and write +//! operations in all CPU modes. No passwords are active. +//! +//! The function is synchronous and does not return until the erase operation +//! has completed. +//! +//! \return Returns 0 on success or non-zero values on failure. Failure codes +//! are logical OR combinations of \b EEPROM_RC_WRBUSY, \b EEPROM_RC_NOPERM, +//! \b EEPROM_RC_WKCOPY, \b EEPROM_RC_WKERASE, and \b EEPROM_RC_WORKING. +// +//***************************************************************************** +uint32_t +EEPROMMassErase(void) +{ + // + // This is a workaround for a silicon problem on Blizzard rev A. + // + if(CLASS_IS_TM4C123 && REVISION_IS_A0) + { + _EEPROMSectorMaskClear(); + } + + // + // Start the mass erase processing + // + HWREG(EEPROM_EEDBGME) = EEPROM_MASS_ERASE_KEY | EEPROM_EEDBGME_ME; + + // + // Wait for completion. + // + _EEPROMWaitForDone(); + + // + // Reset the peripheral. This is required so that all protection + // mechanisms and passwords are reset now that the EEPROM data has been + // scrubbed. + // + SysCtlPeripheralReset(SYSCTL_PERIPH_EEPROM0); + + // + // Wait for completion again. + // + SysCtlDelay(2); + _EEPROMWaitForDone(); + + // + // Pass any error codes back to the caller. + // + return(HWREG(EEPROM_EEDONE)); +} + +//***************************************************************************** +// +//! Returns the current protection level for an EEPROM block. +//! +//! \param ui32Block is the block number for which the protection level is to +//! be queried. +//! +//! This function returns the current protection settings for a given +//! EEPROM block. If block 0 is currently locked, it must be unlocked prior +//! to calling this function to query the protection setting for other blocks. +//! +//! \return Returns one of \b EEPROM_PROT_RW_LRO_URW, \b EEPROM_PROT_NA_LNA_URW +//! or \b EEPROM_PROT_RO_LNA_URO optionally OR-ed with +//! \b EEPROM_PROT_SUPERVISOR_ONLY. +// +//***************************************************************************** +uint32_t +EEPROMBlockProtectGet(uint32_t ui32Block) +{ + // + // Parameter validity check. + // + ASSERT(ui32Block < BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE))); + + // + // Set the current block. + // + HWREG(EEPROM_EEBLOCK) = ui32Block; + + // + // Return the protection flags for this block. + // + return(HWREG(EEPROM_EEPROT)); +} + +//***************************************************************************** +// +//! Set the current protection options for an EEPROM block. +//! +//! \param ui32Block is the block number for which the protection options are +//! to be set. +//! \param ui32Protect consists of one of the values \b EEPROM_PROT_RW_LRO_URW, +//! \b EEPROM_PROT_NA_LNA_URW or \b EEPROM_PROT_RO_LNA_URO optionally ORed with +//! \b EEPROM_PROT_SUPERVISOR_ONLY. +//! +//! This function sets the protection settings for a given EEPROM block +//! assuming no protection settings have previously been written. Note that +//! protection settings applied to block 0 have special meaning and control +//! access to the EEPROM peripheral as a whole. Protection settings applied to +//! blocks numbered 1 and above are layered above any protection set on block 0 +//! such that the effective protection on each block is the logical OR of the +//! protection flags set for block 0 and for the target block. This protocol +//! allows global protection options to be set for the whole device via block +//! 0 and more restrictive protection settings to be set on a block-by-block +//! basis. +//! +//! The protection flags indicate access permissions as follow: +//! +//! \b EEPROM_PROT_SUPERVISOR_ONLY restricts access to the block to threads +//! running in supervisor mode. If clear, both user and supervisor threads +//! can access the block. +//! +//! \b EEPROM_PROT_RW_LRO_URW provides read/write access to the block if no +//! password is set or if a password is set and the block is unlocked. If the +//! block is locked, only read access is permitted. +//! +//! \b EEPROM_PROT_NA_LNA_URW provides neither read nor write access unless +//! a password is set and the block is unlocked. If the block is unlocked, +//! both read and write access are permitted. +//! +//! \b EEPROM_PROT_RO_LNA_URO provides read access to the block if no password +//! is set or if a password is set and the block is unlocked. If the block is +//! password protected and locked, neither read nor write access is permitted. +//! +//! \return Returns a logical OR combination of \b EEPROM_RC_WRBUSY, \b +//! EEPROM_RC_NOPERM, \b EEPROM_RC_WKCOPY, \b EEPROM_RC_WKERASE, and \b +//! EEPROM_RC_WORKING to indicate status and error conditions. +// +//***************************************************************************** +uint32_t +EEPROMBlockProtectSet(uint32_t ui32Block, uint32_t ui32Protect) +{ + // + // Parameter validity check. + // + ASSERT(ui32Block < BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE))); + + // + // Set the current block. + // + HWREG(EEPROM_EEBLOCK) = ui32Block; + + // + // Set the protection options for this block. + // + HWREG(EEPROM_EEPROT) = ui32Protect; + + // + // Wait for the write to complete. + // + while(HWREG(EEPROM_EEDONE) & EEPROM_EEDONE_WORKING) + { + // + // Still working. + // + } + + // + // Pass any error codes back to the caller. + // + return(HWREG(EEPROM_EEDONE)); +} + +//***************************************************************************** +// +//! Sets the password used to protect an EEPROM block. +//! +//! \param ui32Block is the EEPROM block number for which the password is to be +//! set. +//! \param pui32Password points to an array of uint32_t values comprising +//! the password to set. Each element may be any 32-bit value other than +//! 0xFFFFFFFF. This array must contain the number of elements given by the +//! \e ui32Count parameter. +//! \param ui32Count provides the number of uint32_ts in the \e ui32Password. +//! Valid values are 1, 2 and 3. +//! +//! This function allows the password used to unlock an EEPROM block to be +//! set. Valid passwords may be either 32, 64 or 96 bits comprising words +//! with any value other than 0xFFFFFFFF. The password may only be set once. +//! Any further attempts to set the password result in an error. Once the +//! password is set, the block remains unlocked until EEPROMBlockLock() is +//! called for that block or block 0, or a reset occurs. +//! +//! If a password is set on block 0, this affects locking of the peripheral as +//! a whole. When block 0 is locked, all other EEPROM blocks are inaccessible +//! until block 0 is unlocked. Once block 0 is unlocked, other blocks +//! become accessible according to any passwords set on those blocks and the +//! protection set for that block via a call to EEPROMBlockProtectSet(). +//! +//! \return Returns a logical OR combination of \b EEPROM_RC_WRBUSY, \b +//! EEPROM_RC_NOPERM, \b EEPROM_RC_WKCOPY, \b EEPROM_RC_WKERASE, and \b +//! EEPROM_RC_WORKING to indicate status and error conditions. +// +//***************************************************************************** +uint32_t +EEPROMBlockPasswordSet(uint32_t ui32Block, uint32_t *pui32Password, + uint32_t ui32Count) +{ + uint32_t ui32Reg; + + // + // Check parameters in a debug build. + // + ASSERT(pui32Password); + ASSERT(ui32Block < BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE))); + ASSERT(ui32Count <= 3); + + // + // Set the block number whose password we are about to write. + // + HWREG(EEPROM_EEBLOCK) = ui32Block; + + // + // Start with the first password word. + // + ui32Reg = EEPROM_EEPASS0; + + // + // Write the password. + // + while(ui32Count) + { + // + // Start the process of writing the password. + // + HWREG(ui32Reg) = *pui32Password; + + // + // Update values in preparation for writing the next word. + // + pui32Password++; + ui32Reg += 4; + ui32Count--; + + // + // Wait for the last word write to complete or an error to be reported. + // + while(HWREG(EEPROM_EEDONE) & EEPROM_EEDONE_WORKING) + { + // + // Still working. + // + } + } + + // + // Return the final write status. + // + return(HWREG(EEPROM_EEDONE)); +} + +//***************************************************************************** +// +//! Locks a password-protected EEPROM block. +//! +//! \param ui32Block is the EEPROM block number which is to be locked. +//! +//! This function locks an EEPROM block that has previously been protected by +//! writing a password. Access to the block once it is locked is determined +//! by the protection settings applied via a previous call to the +//! EEPROMBlockProtectSet() function. If no password has previously been set +//! for the block, this function has no effect. +//! +//! Locking block 0 has the effect of making all other blocks in the EEPROM +//! inaccessible. +//! +//! \return Returns the lock state for the block on exit, 1 if unlocked (as +//! would be the case if no password was set) or 0 if locked. +//! +//***************************************************************************** +uint32_t +EEPROMBlockLock(uint32_t ui32Block) +{ + // + // Check parameters in a debug build. + // + ASSERT(ui32Block < BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE))); + + // + // Select the block we are going to lock. + // + HWREG(EEPROM_EEBLOCK) = ui32Block; + + // + // Lock the block. + // + HWREG(EEPROM_EEUNLOCK) = 0xFFFFFFFF; + + // + // Return the current lock state. + // + return(HWREG(EEPROM_EEUNLOCK)); +} + +//***************************************************************************** +// +//! Unlocks a password-protected EEPROM block. +//! +//! \param ui32Block is the EEPROM block number which is to be unlocked. +//! \param pui32Password points to an array of uint32_t values containing +//! the password for the block. Each element must match the password +//! originally set via a call to EEPROMBlockPasswordSet(). +//! \param ui32Count provides the number of elements in the \e pui32Password +//! array and must match the value originally passed to +//! EEPROMBlockPasswordSet(). Valid values are 1, 2 and 3. +//! +//! This function unlocks an EEPROM block that has previously been protected by +//! writing a password. Access to the block once it is unlocked is determined +//! by the protection settings applied via a previous call to the +//! EEPROMBlockProtectSet() function. +//! +//! To successfully unlock an EEPROM block, the password provided must match +//! the password provided on the original call to EEPROMBlockPasswordSet(). If +//! an incorrect password is provided, the block remains locked. +//! +//! Unlocking block 0 has the effect of making all other blocks in the device +//! accessible according to their own access protection settings. When block +//! 0 is locked, all other EEPROM blocks are inaccessible. +//! +//! \return Returns the lock state for the block on exit, 1 if unlocked or 0 if +//! locked. +//! +//***************************************************************************** +uint32_t +EEPROMBlockUnlock(uint32_t ui32Block, uint32_t *pui32Password, + uint32_t ui32Count) +{ + // + // Check parameters in a debug build. + // + ASSERT(pui32Password); + ASSERT(ui32Block < BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE))); + ASSERT(ui32Count <= 3); + + // + // Set the block that we are trying to unlock. + // + HWREG(EEPROM_EEBLOCK) = ui32Block; + + // + // Write the unlock register with 0xFFFFFFFF to reset the unlock + // sequence just in case a short password was previously used to try to + // unlock the block. + // + HWREG(EEPROM_EEUNLOCK) = 0xFFFFFFFF; + + // + // We need to write the password words in the opposite order when unlocking + // compared to locking so start at the end of the array. + // + pui32Password += (ui32Count - 1); + + // + // Write the supplied password to unlock the block. + // + while(ui32Count) + { + HWREG(EEPROM_EEUNLOCK) = *pui32Password--; + ui32Count--; + } + + // + // Let the caller know if their password worked. + // + return(HWREG(EEPROM_EEUNLOCK)); +} + +//***************************************************************************** +// +//! Hides an EEPROM block until the next reset. +//! +//! \param ui32Block is the EEPROM block number which is to be hidden. +//! +//! This function hides an EEPROM block other than block 0. Once hidden, a +//! block is completely inaccessible until the next reset. This mechanism +//! allows initialization code to have access to data which is to be hidden +//! from the rest of the application. Unlike applications using passwords, an +//! application making using of block hiding need not contain any embedded +//! passwords which could be found through disassembly. +//! +//! \return None. +//! +//***************************************************************************** +void +EEPROMBlockHide(uint32_t ui32Block) +{ + // + // Check parameters in a debug build. + // + ASSERT(!ui32Block); + ASSERT(ui32Block < BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE))); + + // + // Hide the requested block. + // + HWREG(EEPROM_EEHIDE) = (1 << ui32Block); +} + +//***************************************************************************** +// +//! Enables the EEPROM interrupt. +//! +//! \param ui32IntFlags indicates which EEPROM interrupt source to enable. +//! This must be \b EEPROM_INT_PROGRAM currently. +//! +//! This function enables the EEPROM interrupt. When enabled, an interrupt +//! is generated when any EEPROM write or erase operation completes. The +//! EEPROM peripheral shares a single interrupt vector with the flash memory +//! subsystem, \b INT_FLASH. This function is provided as a convenience but +//! the EEPROM interrupt can also be enabled using a call to FlashIntEnable() +//! passing FLASH_INT_EEPROM in the \e ui32IntFlags parameter. +//! +//! \return None. +//! +//***************************************************************************** +void +EEPROMIntEnable(uint32_t ui32IntFlags) +{ + // + // Look for valid interrupt sources. + // + ASSERT(ui32IntFlags == EEPROM_INT_PROGRAM); + + // + // Enable interrupts from the EEPROM module. + // + HWREG(EEPROM_EEINT) |= EEPROM_EEINT_INT; + + // + // Enable the EEPROM interrupt in the flash controller module. + // + HWREG(FLASH_FCIM) |= FLASH_FCRIS_ERIS; +} + +//***************************************************************************** +// +//! Disables the EEPROM interrupt. +//! +//! \param ui32IntFlags indicates which EEPROM interrupt source to disable. +//! This must be \b EEPROM_INT_PROGRAM currently. +//! +//! This function disables the EEPROM interrupt and prevents calls to the +//! interrupt vector when any EEPROM write or erase operation completes. The +//! EEPROM peripheral shares a single interrupt vector with the flash memory +//! subsystem, \b INT_FLASH. This function is provided as a convenience but +//! the EEPROM interrupt can also be disabled using a call to FlashIntDisable() +//! passing FLASH_INT_EEPROM in the \e ui32IntFlags parameter. +//! +//! \return None. +//! +//***************************************************************************** +void +EEPROMIntDisable(uint32_t ui32IntFlags) +{ + // + // Look for valid interrupt sources. + // + ASSERT(ui32IntFlags == EEPROM_INT_PROGRAM); + + // + // Disable the EEPROM interrupt in the flash controller module. + // + HWREG(FLASH_FCIM) &= ~FLASH_FCIM_EMASK; + + // + // Disable interrupts from the EEPROM module. + // + HWREG(EEPROM_EEINT) &= ~EEPROM_EEINT_INT; +} + +//***************************************************************************** +// +//! Reports the state of the EEPROM interrupt. +//! +//! \param bMasked determines whether the masked or unmasked state of the +//! interrupt is to be returned. If bMasked is \b true, the masked state is +//! returned, otherwise the unmasked state is returned. +//! +//! This function allows an application to query the state of the EEPROM +//! interrupt. If active, the interrupt may be cleared by calling +//! EEPROMIntClear(). +//! +//! \return Returns \b EEPROM_INT_PROGRAM if an interrupt is being signaled or +//! 0 otherwise. +// +//***************************************************************************** +uint32_t +EEPROMIntStatus(bool bMasked) +{ + if(bMasked) + { + // + // If asked for the masked interrupt status, we check to see if the + // relevant interrupt is pending in the flash controller then return + // the appropriate EEPROM flag if it is. + // + return((HWREG(FLASH_FCMISC) & FLASH_FCMISC_EMISC) ? + EEPROM_INT_PROGRAM : 0); + } + else + { + // + // If asked for the unmasked interrupt status, infer that an interrupt + // is pending if the WORKING bit of the EEDONE register is clear. The + // actual interrupt fires on the high to low transition of this bit + // but we don't have access to an unmasked interrupt status for the + // EEPROM because it's handled via the flash controller so we have to + // make do with this instead. + // + return((HWREG(EEPROM_EEDONE) & EEPROM_EEDONE_WORKING) ? + 0 : EEPROM_INT_PROGRAM); + } +} + +//***************************************************************************** +// +//! Clears the EEPROM interrupt. +//! +//! \param ui32IntFlags indicates which interrupt sources to clear. Currently, +//! the only valid value is \b EEPROM_INT_PROGRAM. +//! +//! This function allows an application to clear the EEPROM interrupt. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +//! +//***************************************************************************** +void +EEPROMIntClear(uint32_t ui32IntFlags) +{ + // + // Clear the flash interrupt. + // + HWREG(FLASH_FCMISC) = FLASH_FCMISC_EMISC; + + // + // Clear the sector protection bits to prevent possible problems when + // programming the main flash array later. + // + if(CLASS_IS_TM4C123 && REVISION_IS_A0) + { + _EEPROMSectorMaskClear(); + } +} + +//***************************************************************************** +// +//! Returns status on the last EEPROM program or erase operation. +//! +//! This function returns the current status of the last program or erase +//! operation performed by the EEPROM. It is intended to provide error +//! information to applications programming or setting EEPROM protection +//! options under interrupt control. +//! +//! \return Returns 0 if the last program or erase operation completed without +//! any errors. If an operation is ongoing or an error occurred, the return +//! value is a logical OR combination of \b EEPROM_RC_WRBUSY, \b +//! EEPROM_RC_NOPERM, \b EEPROM_RC_WKCOPY, \b EEPROM_RC_WKERASE, and \b +//! EEPROM_RC_WORKING. +//! +//***************************************************************************** +uint32_t +EEPROMStatusGet(void) +{ + return(HWREG(EEPROM_EEDONE)); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/emac.c b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/emac.c new file mode 100644 index 0000000000000000000000000000000000000000..8c238d299e04d722c471785ea0f0f70e0bb984c0 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/emac.c @@ -0,0 +1,4983 @@ +//***************************************************************************** +// +// emac.c - Driver for the Integrated Ethernet Controller on Snowflake-class +// Tiva devices. +// +// Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup emac_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_emac.h" +#include "driverlib/debug.h" +#include "driverlib/emac.h" +#include "driverlib/sysctl.h" +#include "driverlib/interrupt.h" +#include "driverlib/sw_crc.h" + +//***************************************************************************** +// +// Combined defines used in parameter validity checks. +// +//***************************************************************************** + +//***************************************************************************** +// +// Combined valid configuration flags. +// +//***************************************************************************** +#define VALID_CONFIG_FLAGS (EMAC_CONFIG_USE_MACADDR1 | \ + EMAC_CONFIG_SA_INSERT | \ + EMAC_CONFIG_SA_REPLACE | \ + EMAC_CONFIG_2K_PACKETS | \ + EMAC_CONFIG_STRIP_CRC | \ + EMAC_CONFIG_JABBER_DISABLE | \ + EMAC_CONFIG_JUMBO_ENABLE | \ + EMAC_CONFIG_IF_GAP_MASK | \ + EMAC_CONFIG_CS_DISABLE | \ + EMAC_CONFIG_100MBPS | \ + EMAC_CONFIG_RX_OWN_DISABLE | \ + EMAC_CONFIG_LOOPBACK | \ + EMAC_CONFIG_FULL_DUPLEX | \ + EMAC_CONFIG_CHECKSUM_OFFLOAD | \ + EMAC_CONFIG_RETRY_DISABLE | \ + EMAC_CONFIG_AUTO_CRC_STRIPPING | \ + EMAC_CONFIG_BO_MASK | \ + EMAC_CONFIG_DEFERRAL_CHK_ENABLE | \ + EMAC_CONFIG_PREAMBLE_MASK) + +//***************************************************************************** +// +// Combined valid frame filter flags. +// +//***************************************************************************** +#define VALID_FRMFILTER_FLAGS (EMAC_FRMFILTER_RX_ALL | \ + EMAC_FRMFILTER_VLAN | \ + EMAC_FRMFILTER_HASH_AND_PERFECT | \ + EMAC_FRMFILTER_SADDR | \ + EMAC_FRMFILTER_INV_SADDR | \ + EMAC_FRMFILTER_PASS_NO_PAUSE | \ + EMAC_FRMFILTER_PASS_ALL_CTRL | \ + EMAC_FRMFILTER_PASS_ADDR_CTRL | \ + EMAC_FRMFILTER_BROADCAST | \ + EMAC_FRMFILTER_PASS_MULTICAST | \ + EMAC_FRMFILTER_INV_DADDR | \ + EMAC_FRMFILTER_HASH_MULTICAST | \ + EMAC_FRMFILTER_HASH_UNICAST | \ + EMAC_FRMFILTER_PROMISCUOUS) + +//***************************************************************************** +// +// Combined valid maskable interrupts. +// +//***************************************************************************** +#define EMAC_MASKABLE_INTS (EMAC_INT_EARLY_RECEIVE | \ + EMAC_INT_BUS_ERROR | \ + EMAC_INT_EARLY_TRANSMIT | \ + EMAC_INT_RX_WATCHDOG | \ + EMAC_INT_RX_STOPPED | \ + EMAC_INT_RX_NO_BUFFER | \ + EMAC_INT_RECEIVE | \ + EMAC_INT_TX_UNDERFLOW | \ + EMAC_INT_RX_OVERFLOW | \ + EMAC_INT_TX_JABBER | \ + EMAC_INT_TX_NO_BUFFER | \ + EMAC_INT_TX_STOPPED | \ + EMAC_INT_TRANSMIT | \ + EMAC_INT_NORMAL_INT | \ + EMAC_INT_ABNORMAL_INT | \ + EMAC_INT_PHY) + +//***************************************************************************** +// +// Combined valid normal interrupts. +// +//***************************************************************************** +#define EMAC_NORMAL_INTS (EMAC_INT_TRANSMIT | \ + EMAC_INT_RECEIVE | \ + EMAC_INT_EARLY_RECEIVE | \ + EMAC_INT_TX_NO_BUFFER) + +//***************************************************************************** +// +// Combined valid abnormal interrupts. +// +//***************************************************************************** +#define EMAC_ABNORMAL_INTS (EMAC_INT_TX_STOPPED | \ + EMAC_INT_TX_JABBER | \ + EMAC_INT_RX_OVERFLOW | \ + EMAC_INT_TX_UNDERFLOW | \ + EMAC_INT_RX_NO_BUFFER | \ + EMAC_INT_RX_STOPPED | \ + EMAC_INT_RX_WATCHDOG | \ + EMAC_INT_EARLY_TRANSMIT | \ + EMAC_INT_BUS_ERROR) + +//***************************************************************************** +// +// Interrupt sources reported via the DMARIS register but which are not +// masked (or enabled) via the DMAIM register. +// +//***************************************************************************** +#define EMAC_NON_MASKED_INTS (EMAC_DMARIS_LPI | \ + EMAC_DMARIS_TT | \ + EMAC_DMARIS_PMT | \ + EMAC_DMARIS_MMC) + +//***************************************************************************** +// +// The number of MAC addresses the module can store for filtering purposes. +// +//***************************************************************************** +#define NUM_MAC_ADDR 4 + +//***************************************************************************** +// +// Macros aiding access to the MAC address registers. +// +//***************************************************************************** +#define MAC_ADDR_OFFSET (EMAC_O_ADDR1L - EMAC_O_ADDR0L) +#define EMAC_O_ADDRL(n) (EMAC_O_ADDR0L + (MAC_ADDR_OFFSET * (n))) +#define EMAC_O_ADDRH(n) (EMAC_O_ADDR0H + (MAC_ADDR_OFFSET * (n))) + +//***************************************************************************** +// +// A structure used to help in choosing the correct clock divisor for the MII +// based on the current system clock rate. +// +//***************************************************************************** +static const struct +{ + uint32_t ui32SysClockMax; + uint32_t ui32Divisor; +} +g_pi16MIIClockDiv[] = +{ + { 64000000, EMAC_MIIADDR_CR_35_60 }, + { 104000000, EMAC_MIIADDR_CR_60_100 }, + { 150000000, EMAC_MIIADDR_CR_100_150 } +}; + +//***************************************************************************** +// +// The number of clock divisors in the above table. +// +//***************************************************************************** +#define NUM_CLOCK_DIVISORS (sizeof(g_pi16MIIClockDiv) / \ + sizeof(g_pi16MIIClockDiv[0])) + +//***************************************************************************** +// +// The define for accessing PHY registers in the MMD address space. +// +//***************************************************************************** +#define DEV_ADDR(x) ((x & 0xF000) >> 12) +#define REG_ADDR(x) ((x & 0x0FFF)) + +//***************************************************************************** +// +//! Initializes the Ethernet MAC and sets bus-related DMA parameters. +//! +//! \param ui32Base is the base address of the Ethernet controller. +//! \param ui32SysClk is the current system clock frequency in Hertz. +//! \param ui32BusConfig defines the bus operating mode for the Ethernet MAC +//! DMA controller. +//! \param ui32RxBurst is the maximum receive burst size in words. +//! \param ui32TxBurst is the maximum transmit burst size in words. +//! \param ui32DescSkipSize is the number of 32-bit words to skip between +//! two unchained DMA descriptors. Values in the range 0 to 31 are valid. +//! +//! This function sets bus-related parameters for the Ethernet MAC DMA +//! engines. It must be called after EMACPHYConfigSet() and called again +//! after any subsequent call to EMACPHYConfigSet(). +//! +//! The \e ui32BusConfig parameter is the logical OR of various fields. The +//! first sets the DMA channel priority weight: +//! +//! - \b EMAC_BCONFIG_DMA_PRIO_WEIGHT_1 +//! - \b EMAC_BCONFIG_DMA_PRIO_WEIGHT_2 +//! - \b EMAC_BCONFIG_DMA_PRIO_WEIGHT_3 +//! - \b EMAC_BCONFIG_DMA_PRIO_WEIGHT_4 +//! +//! The second field sets the receive and transmit priorities used when +//! arbitrating between the Rx and Tx DMA. The priorities are Rx:Tx unless +//! \b EMAC_BCONFIG_TX_PRIORITY is also specified, in which case they become +//! Tx:Rx. The priority provided here is ignored if +//! \b EMAC_BCONFIG_PRIORITY_FIXED is specified. +//! +//! - \b EMAC_BCONFIG_PRIORITY_1_1 +//! - \b EMAC_BCONFIG_PRIORITY_2_1 +//! - \b EMAC_BCONFIG_PRIORITY_3_1 +//! - \b EMAC_BCONFIG_PRIORITY_4_1 +//! +//! The following additional flags may also be defined: +//! +//! - \b EMAC_BCONFIG_TX_PRIORITY indicates that the transmit DMA should be +//! higher priority in all arbitration for the system-side bus. If this is not +//! defined, the receive DMA has higher priority. +//! - \b EMAC_BCONFIG_ADDR_ALIGNED works in tandem with +//! \b EMAC_BCONFIG_FIXED_BURST to control address alignment of AHB bursts. +//! When both flags are specified, all bursts are aligned to the start address +//! least significant bits. If \b EMAC_BCONFIG_FIXED_BURST is not specified, +//! the first burst is unaligned but subsequent bursts are aligned to the +//! address. +//! - \b EMAC_BCONFIG_ALT_DESCRIPTORS indicates that the DMA engine should +//! use the alternate descriptor format as defined in type +//! \b tEMACDMADescriptor. If absent, the basic descriptor type is used. +//! Alternate descriptors are required if using IEEE 1588-2008 advanced +//! timestamping, VLAN or TCP/UDP/ICMP CRC insertion features. Note that, +//! for clarity, emac.h does not contain type definitions for the basic +//! descriptor type. Please see the part datasheet for information on basic +//! descriptor structures. +//! - \b EMAC_BCONFIG_PRIORITY_FIXED indicates that a fixed priority scheme +//! should be employed when arbitrating between the transmit and receive DMA +//! for system-side bus access. In this case, the receive channel always has +//! priority unless \b EMAC_BCONFIG_TX_PRIORITY is set, in which case the +//! transmit channel has priority. If \b EMAC_BCONFIG_PRIORITY_FIXED is not +//! specified, a weighted round-robin arbitration scheme is used with the +//! weighting defined using \b EMAC_BCONFIG_PRIORITY_1_1, +//! \b EMAC_BCONFIG_PRIORITY_2_1, \b EMAC_BCONFIG_PRIORITY_3_1 or +//! \b EMAC_BCONFIG_PRIORITY_4_1, and \b EMAC_BCONFIG_TX_PRIORITY. +//! - \b EMAC_BCONFIG_FIXED_BURST indicates that fixed burst transfers should +//! be used. +//! - \b EMAC_BCONFIG_MIXED_BURST indicates that the DMA engine should use +//! mixed burst types depending on the length of data to be transferred +//! across the system bus. +//! +//! The \e ui32RxBurst and \e ui32TxBurst parameters indicate the maximum +//! number of words that the relevant DMA should transfer in a single +//! transaction. Valid values are 1, 2, 4, 8, 16 and 32. Any other value +//! results in undefined behavior. +//! +//! The \e ui32DescSkipSize parameter is used when the descriptor lists are +//! using ring mode (where descriptors are contiguous in memory with the last +//! descriptor marked with the \b END_OF_RING flag) rather than chained mode +//! (where each descriptor includes a field that points to the next descriptor +//! in the list). In ring mode, the hardware uses the \e ui32DescSkipSize to +//! skip past any application-defined fields after the end of the hardware- +//! defined descriptor fields. The parameter value indicates the number of +//! 32-bit words to skip after the last field of the hardware-defined +//! descriptor to get to the first field of the next descriptor. When using +//! arrays of either the \b tEMACDMADescriptor or \b tEMACAltDMADescriptor +//! types defined for this driver, \e ui32DescSkipSize must be set to 1 to skip +//! the \e pvNext pointer added to the end of each of these structures. +//! Applications may modify these structure definitions to include their own +//! application-specific data and modify \e ui32DescSkipSize appropriately if +//! desired. +//! +//! \return None. +// +//***************************************************************************** +void +EMACInit(uint32_t ui32Base, uint32_t ui32SysClk, uint32_t ui32BusConfig, + uint32_t ui32RxBurst, uint32_t ui32TxBurst, uint32_t ui32DescSkipSize) +{ + uint32_t ui32Val, ui32Div; + + // + // Parameter sanity checks. + // + ASSERT(ui32DescSkipSize < 32); + ASSERT(ui32TxBurst < (32 * 8)); + ASSERT(ui32RxBurst < (32 * 8)); + + // + // Make sure that the DMA software reset is clear before continuing. + // + while(HWREG(EMAC0_BASE + EMAC_O_DMABUSMOD) & EMAC_DMABUSMOD_SWR) + { + } + + // + // Set common flags. Note that this driver assumes we are always using + // 8 word descriptors so we need to OR in EMAC_DMABUSMOD_ATDS here. + // + ui32Val = (ui32BusConfig | (ui32DescSkipSize << EMAC_DMABUSMOD_DSL_S) | + EMAC_DMABUSMOD_ATDS); + + // + // Do we need to use the 8X burst length multiplier? + // + if((ui32TxBurst > 32) || (ui32RxBurst > 32)) + { + // + // Divide both burst lengths by 8 and set the 8X burst length + // multiplier. + // + ui32Val |= EMAC_DMABUSMOD_8XPBL; + ui32TxBurst >>= 3; + ui32RxBurst >>= 3; + + // + // Sanity check - neither burst length should have become zero. If + // they did, this indicates that the values passed are invalid. + // + ASSERT(ui32RxBurst); + ASSERT(ui32TxBurst); + } + + // + // Are the receive and transmit burst lengths the same? + // + if(ui32RxBurst == ui32TxBurst) + { + // + // Yes - set up to use a single burst length. + // + ui32Val |= (ui32TxBurst << EMAC_DMABUSMOD_PBL_S); + } + else + { + // + // No - we need to use separate burst lengths for each. + // + ui32Val |= (EMAC_DMABUSMOD_USP | + (ui32TxBurst << EMAC_DMABUSMOD_PBL_S) | + (ui32RxBurst << EMAC_DMABUSMOD_RPBL_S)); + } + + // + // Finally, write the bus mode register. + // + HWREG(ui32Base + EMAC_O_DMABUSMOD) = ui32Val; + + // + // Default the MII CSR clock divider based on the fastest system clock. + // + ui32Div = g_pi16MIIClockDiv[NUM_CLOCK_DIVISORS - 1].ui32Divisor; + + // + // Find the MII CSR clock divider to use based on the current system clock. + // + for(ui32Val = 0; ui32Val < NUM_CLOCK_DIVISORS; ui32Val++) + { + if(ui32SysClk <= g_pi16MIIClockDiv[ui32Val].ui32SysClockMax) + { + ui32Div = g_pi16MIIClockDiv[ui32Val].ui32Divisor; + break; + } + } + + // + // Set the MII CSR clock speed. + // + HWREG(ui32Base + EMAC_O_MIIADDR) = ((HWREG(ui32Base + EMAC_O_MIIADDR) & + ~EMAC_MIIADDR_CR_M) | ui32Div); + + // + // Disable all the MMC interrupts as these are enabled by default at reset. + // + HWREG(ui32Base + EMAC_O_MMCRXIM) = 0xFFFFFFFF; + HWREG(ui32Base + EMAC_O_MMCTXIM) = 0xFFFFFFFF; +} + +//***************************************************************************** +// +//! Resets the Ethernet MAC. +//! +//! \param ui32Base is the base address of the Ethernet controller. +//! +//! This function performs a reset of the Ethernet MAC by resetting all logic +//! and returning all registers to their default values. The function returns +//! only after the hardware indicates that the reset has completed. +//! +//! \note To ensure that the reset completes, the selected PHY clock must be +//! enabled when this function is called. If the PHY clock is absent, this +//! function does not return. +//! +//! \return None. +// +//***************************************************************************** +void +EMACReset(uint32_t ui32Base) +{ + // + // Reset the Ethernet MAC. + // + HWREG(ui32Base + EMAC_O_DMABUSMOD) |= EMAC_DMABUSMOD_SWR; + + // + // Wait for the reset to complete. + // + while(HWREG(ui32Base + EMAC_O_DMABUSMOD) & EMAC_DMABUSMOD_SWR) + { + } +} + +//***************************************************************************** +// +//! Selects the Ethernet PHY in use. +//! +//! \param ui32Base is the base address of the Ethernet controller. +//! \param ui32Config selects the PHY in use and, when using the internal +//! PHY, allows various various PHY parameters to be configured. +//! +//! This function must be called prior to EMACInit() and EMACConfigSet() to +//! select the Ethernet PHY to be used. If the internal PHY is selected, the +//! function also allows configuration of various PHY parameters. Note that +//! the Ethernet MAC is reset during this function call because parameters used +//! by this function are latched by the hardware only on a MAC reset. The call +//! sequence to select and configure the PHY, therefore, must be as follows: +//! +//! \verbatim +//! // Enable and reset the MAC. +//! SysCtlPeripheralEnable(SYSCTL_PERIPH_EMAC0); +//! SysCtlPeripheralReset(SYSCTL_PERIPH_EMAC0); +//! if() +//! { +//! // Enable and reset the internal PHY. +//! SysCtlPeripheralEnable(SYSCTL_PERIPH_EPHY0); +//! SysCtlPeripheralReset(SYSCTL_PERIPH_EPHY0); +//! } +//! +//! // Ensure the MAC is completed its reset. +//! while(!MAP_SysCtlPeripheralReady(SYSCTL_PERIPH_EMAC0)) +//! { +//! } +//! +//! // Set the PHY type and configuration options. +//! EMACPHYConfigSet(EMAC0_BASE, ); +//! +//! // Initialize and configure the MAC. +//! EMACInit(EMAC0_BASE, , , +//! , , ); +//! EMACConfigSet(EMAC0_BASE, ); +//! \endverbatim +//! +//! The \e ui32Config parameter must specify one of the following values: +//! +//! - \b EMAC_PHY_TYPE_INTERNAL selects the internal Ethernet PHY. +//! - \b EMAC_PHY_TYPE_EXTERNAL_MII selects an external PHY connected via the +//! MII interface. +//! - \b EMAC_PHY_TYPE_EXTERNAL_RMII selects an external PHY connected via the +//! RMII interface. +//! +//! If \b EMAC_PHY_TYPE_INTERNAL is selected, the following flags may be ORed +//! into \e ui32Config to control various PHY features and modes. These flags +//! are ignored if an external PHY is selected. +//! +//! - \b EMAC_PHY_INT_NIB_TXERR_DET_DIS disables odd nibble transmit error +//! detection (sets the default value of PHY register MR10, bit 1). +//! - \b EMAC_PHY_INT_RX_ER_DURING_IDLE enables receive error detection during +//! idle (sets the default value of PHY register MR10, bit 2). +//! - \b EMAC_PHY_INT_ISOLATE_MII_LLOSS ties the MII outputs low if no link is +//! established in 100B-T and full duplex modes (sets the default value of PHY +//! register MR10, bit 3). +//! - \b EMAC_PHY_INT_LINK_LOSS_RECOVERY enables link loss recovery (sets the +//! default value of PHY register MR9, bit 7). +//! - \b EMAC_PHY_INT_TDRRUN enables execution of the TDR procedure after a link +//! down event (sets the default value of PHY register MR9, bit 8). +//! - \b EMAC_PHY_INT_LD_ON_RX_ERR_COUNT enables link down if the receiver +//! error count reaches 32 within a 10-us interval (sets the default value of +//! PHY register MR11 bit 3). +//! - \b EMAC_PHY_INT_LD_ON_MTL3_ERR_COUNT enables link down if the MTL3 error +//! count reaches 20 in a 10 us-interval (sets the default value of PHY register +//! MR11 bit 2). +//! - \b EMAC_PHY_INT_LD_ON_LOW_SNR enables link down if the low SNR threshold +//! is crossed 20 times in a 10 us-interval (sets the default value of PHY +//! register MR11 bit 1). +//! - \b EMAC_PHY_INT_LD_ON_SIGNAL_ENERGY enables link down if energy detector +//! indicates Energy Loss (sets the default value of PHY register MR11 bit 0). +//! - \b EMAC_PHY_INT_POLARITY_SWAP inverts the polarity on both TPTD and TPRD +//! pairs (sets the default value of PHY register MR11 bit 5). +//! - \b EMAC_PHY_INT_MDI_SWAP swaps the MDI pairs putting receive on the TPTD +//! pair and transmit on TPRD (sets the default value of PHY register MR11 bit +//! 6). +//! - \b EMAC_PHY_INT_ROBUST_MDIX enables robust auto MDI-X resolution (sets the +//! default value of PHY register MR9 bit 5). +//! - \b EMAC_PHY_INT_FAST_MDIX enables fast auto-MDI/MDIX resolution (sets the +//! default value of PHY register MR9 bit 6). +//! - \b EMAC_PHY_INT_MDIX_EN enables auto-MDI/MDIX crossover (sets the +//! default value of PHY register MR9 bit 14). +//! - \b EMAC_PHY_INT_FAST_RXDV_DETECT enables fast RXDV detection (set the +//! default value of PHY register MR9 bit 1). +//! - \b EMAC_PHY_INT_FAST_L_UP_DETECT enables fast link-up time during parallel +//! detection (sets the default value of PHY register MR10 bit 6) +//! - \b EMAC_PHY_INT_EXT_FULL_DUPLEX forces full-duplex while working with a +//! link partner in forced 100B-TX (sets the default value of PHY register +//! MR10 bit 5). +//! - \b EMAC_PHY_INT_FAST_AN_80_50_35 enables fast auto-negotiation using +//! break link, link fail inhibit and wait timers set to 80, 50 and 35 +//! respectively (sets the default value of PHY register MR9 bits [4:2] to +//! 3b100). +//! - \b EMAC_PHY_INT_FAST_AN_120_75_50 enables fast auto-negotiation using +//! break link, link fail inhibit and wait timers set to 120, 75 and 50 +//! respectively (sets the default value of PHY register MR9 bits [4:2] to +//! 3b101). +//! - \b EMAC_PHY_INT_FAST_AN_140_150_100 enables fast auto-negotiation using +//! break link, link fail inhibit and wait timers set to 140, 150 and 100 +//! respectively (sets the default value of PHY register MR9 bits [4:2] to +//! 3b110). +//! - \b EMAC_PHY_FORCE_10B_T_HALF_DUPLEX disables auto-negotiation and forces +//! operation in 10Base-T, half duplex mode (sets the default value of PHY +//! register MR9 bits [13:11] to 3b000). +//! - \b EMAC_PHY_FORCE_10B_T_FULL_DUPLEX disables auto-negotiation and forces +//! operation in 10Base-T, full duplex mode (sets the default value of PHY +//! register MR9 bits [13:11] to 3b001). +//! - \b EMAC_PHY_FORCE_100B_T_HALF_DUPLEX disables auto-negotiation and forces +//! operation in 100Base-T, half duplex mode (sets the default value of PHY +//! register MR9 bits [13:11] to 3b010). +//! - \b EMAC_PHY_FORCE_100B_T_FULL_DUPLEX disables auto-negotiation and forces +//! operation in 100Base-T, full duplex mode (sets the default value of PHY +//! register MR9 bits [13:11] to 3b011). +//! - \b EMAC_PHY_AN_10B_T_HALF_DUPLEX enables auto-negotiation and advertises +//! 10Base-T, half duplex mode (sets the default value of PHY register MR9 bits +//! [13:11] to 3b100). +//! - \b EMAC_PHY_AN_10B_T_FULL_DUPLEX enables auto-negotiation and advertises +//! 10Base-T half or full duplex modes (sets the default value of PHY register +//! MR9 bits [13:11] to 3b101). +//! - \b EMAC_PHY_AN_100B_T_HALF_DUPLEX enables auto-negotiation and advertises +//! 10Base-T half or full duplex, and 100Base-T half duplex modes (sets the +//! default value of PHY register MR9 bits [13:11] to 3b110). +//! - \b EMAC_PHY_AN_100B_T_FULL_DUPLEX enables auto-negotiation and advertises +//! 10Base-T half or full duplex, and 100Base-T half or full duplex modes (sets +//! the default value of PHY register MR9 bits [13:11] to 3b111). +//! - \b EMAC_PHY_INT_HOLD prevents the PHY from transmitting energy on the +//! line. +//! +//! As a side effect of this function, the Ethernet MAC is reset so any +//! previous MAC configuration is lost. +//! +//! \return None. +// +//***************************************************************************** +void +EMACPHYConfigSet(uint32_t ui32Base, uint32_t ui32Config) +{ + // + // Write the Ethernet PHY configuration to the peripheral configuration + // register. + // + HWREG(ui32Base + EMAC_O_PC) = ui32Config; + + // + // If using the internal PHY, reset it to ensure that new configuration is + // latched there. + // + if((ui32Config & EMAC_PHY_TYPE_MASK) == EMAC_PHY_TYPE_INTERNAL) + { + SysCtlPeripheralReset(SYSCTL_PERIPH_EPHY0); + while(!SysCtlPeripheralReady(SYSCTL_PERIPH_EPHY0)) + { + // + // Wait for the PHY reset to complete. + // + } + + // + // Delay a bit longer to ensure that the PHY reset has completed. + // + SysCtlDelay(10000); + } + + // + // If using an external RMII PHY, we must set 2 bits in the Ethernet MAC + // Clock Configuration Register. + // + if((ui32Config & EMAC_PHY_TYPE_MASK) == EMAC_PHY_TYPE_EXTERNAL_RMII) + { + // + // Select and enable the external clock from the RMII PHY. + // + HWREG(EMAC0_BASE + EMAC_O_CC) |= EMAC_CC_CLKEN; + } + else + { + // + // Disable the external clock. + // + HWREG(EMAC0_BASE + EMAC_O_CC) &= ~EMAC_CC_CLKEN; + } + + // + // Reset the MAC regardless of whether the PHY connection changed or not. + // + EMACReset(EMAC0_BASE); + + SysCtlDelay(1000); +} + +//***************************************************************************** +// +//! Configures basic Ethernet MAC operation parameters. +//! +//! \param ui32Base is the base address of the Ethernet controller. +//! \param ui32Config provides various flags and values configuring the MAC. +//! \param ui32ModeFlags provides configuration relating to the transmit and +//! receive DMA engines. +//! \param ui32RxMaxFrameSize sets the maximum receive frame size above which +//! an error is reported. +//! +//! This function is called to configure basic operating parameters for the +//! MAC and its DMA engines. +//! +//! The \e ui32Config parameter is the logical OR of various fields and +//! flags. The first field determines which MAC address is used during +//! insertion or replacement for all transmitted frames. Valid options are +//! +//! - \b EMAC_CONFIG_USE_MACADDR1 and +//! - \b EMAC_CONFIG_USE_MACADDR0 +//! +//! The interframe gap between transmitted frames is controlled using one of +//! the following values: +//! +//! - \b EMAC_CONFIG_IF_GAP_96BITS +//! - \b EMAC_CONFIG_IF_GAP_88BITS +//! - \b EMAC_CONFIG_IF_GAP_80BITS +//! - \b EMAC_CONFIG_IF_GAP_72BITS +//! - \b EMAC_CONFIG_IF_GAP_64BITS +//! - \b EMAC_CONFIG_IF_GAP_56BITS +//! - \b EMAC_CONFIG_IF_GAP_48BITS +//! - \b EMAC_CONFIG_IF_GAP_40BITS +//! +//! The number of bytes of preamble added to the beginning of every transmitted +//! frame is selected using one of the following values: +//! +//! - \b EMAC_CONFIG_7BYTE_PREAMBLE +//! - \b EMAC_CONFIG_5BYTE_PREAMBLE +//! - \b EMAC_CONFIG_3BYTE_PREAMBLE +//! +//! The back-off limit determines the range of the random time that the MAC +//! delays after a collision and before attempting to retransmit a frame. One +//! of the following values must be used to select this limit. In each case, +//! the retransmission delay in terms of 512 bit time slots, is the lower of +//! (2 ** N) and a random number between 0 and the selected backoff-limit. +//! +//! - \b EMAC_CONFIG_BO_LIMIT_1024 +//! - \b EMAC_CONFIG_BO_LIMIT_256 +//! - \b EMAC_CONFIG_BO_LIMIT_16 +//! - \b EMAC_CONFIG_BO_LIMIT_2 +//! +//! Control over insertion or replacement of the source address in all +//! transmitted frames is provided by using one of the following fields: +//! +//! - \b EMAC_CONFIG_SA_INSERT causes the MAC address (0 or 1 depending +//! on whether \b EMAC_CONFIG_USE_MACADDR0 or \b EMAC_CONFIG_USE_MACADDR1 +//! was specified) to be inserted into all transmitted frames. +//! - \b EMAC_CONFIG_SA_REPLACE causes the MAC address to be replaced with +//! the selected address in all transmitted frames. +//! - \b EMAC_CONFIG_SA_FROM_DESCRIPTOR causes control of source address +//! insertion or deletion to be controlled by fields in the DMA transmit +//! descriptor, allowing control on a frame-by-frame basis. +//! +//! Whether the interface attempts to operate in full- or half-duplex mode is +//! controlled by one of the following flags: +//! +//! - \b EMAC_CONFIG_FULL_DUPLEX +//! - \b EMAC_CONFIG_HALF_DUPLEX +//! +//! The following additional flags may also be specified: +//! +//! - \b EMAC_CONFIG_2K_PACKETS enables IEEE802.3as support for 2K packets. +//! When specified, the MAC considers all frames up to 2000 bytes in length as +//! normal packets. When \b EMAC_CONFIG_JUMBO_ENABLE is not specified, all +//! frames larger than 2000 bytes are treated as Giant frames. This flag is +//! ignored if \b EMAC_CONFIG_JUMBO_ENABLE is specified. +//! - \b EMAC_CONFIG_STRIP_CRC causes the 4-byte CRC of all Ethernet type +//! frames to be stripped and dropped before the frame is forwarded to the +//! application. +//! - \b EMAC_CONFIG_JABBER_DISABLE disables the jabber timer on the +//! transmitter and enables frames of up to 16384 bytes to be transmitted. If +//! this flag is absent, the MAC does not allow more than 2048 (or 10240 if +//! \b EMAC_CONFIG_JUMBO_ENABLE is specified) bytes to be sent in any one +//! frame. +//! - \b EMAC_CONFIG_JUMBO_ENABLE enables Jumbo Frames, allowing frames of +//! up to 9018 (or 9022 if using VLAN tagging) to be handled without reporting +//! giant frame errors. +//! - \b EMAC_CONFIG_100MBPS forces the MAC to communicate with the PHY using +//! 100Mbps signaling. If this option is not specified, the MAC uses 10Mbps +//! signaling. This speed setting is important when using an external RMII +//! PHY where the selected rate must match the PHY's setting which may have +//! been made as a result of auto-negotiation. When using the internal PHY +//! or an external MII PHY, the signaling rate is controlled by the PHY- +//! provided transmit and receive clocks. +//! - \b EMAC_CONFIG_CS_DISABLE disables Carrier Sense during transmission +//! when operating in half-duplex mode. +//! - \b EMAC_CONFIG_RX_OWN_DISABLE disables reception of transmitted frames +//! when operating in half-duplex mode. +//! - \b EMAC_CONFIG_LOOPBACK enables internal loopback. +//! - \b EMAC_CONFIG_CHECKSUM_OFFLOAD enables IPv4 header checksum checking +//! and IPv4 or IPv6 TCP, UPD or ICMP payload checksum checking. The results +//! of the checksum calculations are reported via status fields in the DMA +//! receive descriptors. +//! - \b EMAC_CONFIG_RETRY_DISABLE disables retransmission in cases where +//! half-duplex mode is in use and a collision occurs. This condition causes +//! the current frame to be ignored and a frame abort to be reported in the +//! transmit frame status. +//! - \b EMAC_CONFIG_AUTO_CRC_STRIPPING strips the last 4 bytes (frame check +//! sequence) from all Ether type frames before forwarding the frames to the +//! application. +//! - \b EMAC_CONFIG_DEFERRAL_CHK_ENABLE enables transmit deferral checking +//! in half-duplex mode. When enabled, the transmitter reports an error if it +//! is unable to transmit a frame for more than 24288 bit times (or 155680 +//! bit times in Jumbo frame mode) due to an active carrier sense signal on +//! the MII. +//! +//! The \e ui32ModeFlags parameter sets operating parameters related to the +//! internal MAC FIFOs. It comprises a logical OR of the following fields. +//! The first selects the transmit FIFO threshold. Transmission of a frame +//! begins when this amount of data or a full frame exists in the transmit +//! FIFO. This field is ignored if \b EMAC_MODE_TX_STORE_FORWARD is +//! included. One of the following must be specified: +//! +//! - \b EMAC_MODE_TX_THRESHOLD_16_BYTES +//! - \b EMAC_MODE_TX_THRESHOLD_24_BYTES +//! - \b EMAC_MODE_TX_THRESHOLD_32_BYTES +//! - \b EMAC_MODE_TX_THRESHOLD_40_BYTES +//! - \b EMAC_MODE_TX_THRESHOLD_64_BYTES +//! - \b EMAC_MODE_TX_THRESHOLD_128_BYTES +//! - \b EMAC_MODE_TX_THRESHOLD_192_BYTES +//! - \b EMAC_MODE_TX_THRESHOLD_256_BYTES +//! +//! The second field controls the receive FIFO threshold. DMA transfers of +//! received data begin either when the receive FIFO contains a full frame +//! or this number of bytes. This field is ignored if +//! \b EMAC_MODE_RX_STORE_FORWARD is included. One of the following must be +//! specified: +//! +//! - \b EMAC_MODE_RX_THRESHOLD_64_BYTES +//! - \b EMAC_MODE_RX_THRESHOLD_32_BYTES +//! - \b EMAC_MODE_RX_THRESHOLD_96_BYTES +//! - \b EMAC_MODE_RX_THRESHOLD_128_BYTES +//! +//! The following additional flags may be specified: +//! +//! - \b EMAC_MODE_KEEP_BAD_CRC causes frames with TCP/IP checksum errors +//! to be forwarded to the application if those frames do not have any errors +//! (including FCS errors) in the Ethernet framing. In these cases, the frames +//! have errors only in the payload. If this flag is not specified, all frames +//! with any detected error are discarded unless \b EMAC_MODE_RX_ERROR_FRAMES +//! is also specified. +//! - \b EMAC_MODE_RX_STORE_FORWARD causes the receive DMA to read frames +//! from the FIFO only after the complete frame has been written to it. If +//! this mode is enabled, the receive threshold is ignored. +//! - \b EMAC_MODE_RX_FLUSH_DISABLE disables the flushing of received frames +//! in cases where receive descriptors or buffers are unavailable. +//! - \b EMAC_MODE_TX_STORE_FORWARD causes the transmitter to start +//! transmitting a frame only after the whole frame has been written to the +//! transmit FIFO. If this mode is enabled, the transmit threshold is ignored. +//! - \b EMAC_MODE_RX_ERROR_FRAMES causes all frames other than runt error +//! frames to be forwarded to the receive DMA regardless of any errors detected +//! in the frames. +//! - \b EMAC_MODE_RX_UNDERSIZED_FRAMES causes undersized frames (frames +//! shorter than 64 bytes but with no errors) to the application. If this +//! option is not selected, all undersized frames are dropped by the receiver +//! unless it has already started transferring them to the receive FIFO due to +//! the receive threshold setting. +//! - \b EMAC_MODE_OPERATE_2ND_FRAME enables the transmit DMA to operate on a +//! second frame while waiting for the previous frame to be transmitted and +//! associated status and timestamps to be reported. If absent, the transmit +//! DMA works on a single frame at any one time, waiting for that frame to be +//! transmitted and its status to be received before moving on to the next +//! frame. +//! +//! The \e ui32RxMaxFrameSize parameter may be used to override the default +//! setting for the maximum number of bytes that can be received in a frame +//! before that frame is flagged as being in error. If the parameter is set +//! to 0, the default hardware settings are applied. If non-zero, any frame +//! received which is longer than the \e ui32RxMaxFrameSize, regardless of +//! whether the MAC is configured for normal or Jumbo frame operation, is +//! flagged as an error. +//! +//! \return None. +// +//***************************************************************************** +void +EMACConfigSet(uint32_t ui32Base, uint32_t ui32Config, uint32_t ui32ModeFlags, + uint32_t ui32RxMaxFrameSize) +{ + // + // Parameter sanity check. Note that we allow TX_ENABLED and RX_ENABLED + // here because we'll mask them off before writing the value and this + // makes back-to-back EMACConfigGet/EMACConfigSet calls work without the + // caller needing to explicitly remove these bits from the parameter. + // + ASSERT((ui32Config & ~(VALID_CONFIG_FLAGS | EMAC_CONFIG_TX_ENABLED | + EMAC_CONFIG_RX_ENABLED)) == 0); + ASSERT(!ui32RxMaxFrameSize || ((ui32RxMaxFrameSize < 0x4000) && + (ui32RxMaxFrameSize > 1522))); + + // + // Set the configuration flags as specified. Note that we unconditionally + // OR in the EMAC_CFG_PS bit here since this implementation supports only + // MII and RMII interfaces to the PHYs. + // + HWREG(ui32Base + EMAC_O_CFG) = + ((HWREG(ui32Base + EMAC_O_CFG) & ~VALID_CONFIG_FLAGS) | ui32Config | + EMAC_CFG_PS); + + // + // Set the maximum receive frame size. If 0 is passed, this implies + // that the default maximum frame size should be used so just turn off + // the override. + // + if(ui32RxMaxFrameSize) + { + HWREG(ui32Base + EMAC_O_WDOGTO) = ui32RxMaxFrameSize | EMAC_WDOGTO_PWE; + } + else + { + HWREG(ui32Base + EMAC_O_WDOGTO) &= ~EMAC_WDOGTO_PWE; + } + + // + // Set the operating mode register. + // + HWREG(ui32Base + EMAC_O_DMAOPMODE) = ui32ModeFlags; +} + +//***************************************************************************** +// +//! Returns the Ethernet MAC's current basic configuration parameters. +//! +//! \param ui32Base is the base address of the Ethernet controller. +//! \param pui32Config points to storage that is written with Ethernet MAC +//! configuration. +//! \param pui32Mode points to storage that is written with Ethernet MAC mode +//! information. +//! \param pui32RxMaxFrameSize points to storage that is written with the +//! maximum receive frame size. +//! +//! This function is called to query the basic operating parameters for the +//! MAC and its DMA engines. +//! +//! The \e pui32Config parameter is written with the logical OR of various +//! fields and flags. The first field describes which MAC address is used +//! during insertion or replacement for all transmitted frames. Valid options +//! are +//! +//! - \b EMAC_CONFIG_USE_MACADDR1 +//! - \b EMAC_CONFIG_USE_MACADDR0 +//! +//! The interframe gap between transmitted frames is given using one of the +//! following values: +//! +//! - \b EMAC_CONFIG_IF_GAP_96BITS +//! - \b EMAC_CONFIG_IF_GAP_88BITS +//! - \b EMAC_CONFIG_IF_GAP_80BITS +//! - \b EMAC_CONFIG_IF_GAP_72BITS +//! - \b EMAC_CONFIG_IF_GAP_64BITS +//! - \b EMAC_CONFIG_IF_GAP_56BITS +//! - \b EMAC_CONFIG_IF_GAP_48BITS +//! - \b EMAC_CONFIG_IF_GAP_40BITS +//! +//! The number of bytes of preamble added to the beginning of every transmitted +//! frame is described using one of the following values: +//! +//! - \b EMAC_CONFIG_7BYTE_PREAMBLE +//! - \b EMAC_CONFIG_5BYTE_PREAMBLE +//! - \b EMAC_CONFIG_3BYTE_PREAMBLE +//! +//! The back-off limit determines the range of the random time that the MAC +//! delays after a collision and before attempting to retransmit a frame. One +//! of the following values provides the currently selected limit. In each +//! case the retransmission delay in terms of 512 bit time slots, is the +//! lower of (2 ** N) and a random number between 0 and the reported +//! backoff-limit. +//! +//! - \b EMAC_CONFIG_BO_LIMIT_1024 +//! - \b EMAC_CONFIG_BO_LIMIT_256 +//! - \b EMAC_CONFIG_BO_LIMIT_16 +//! - \b EMAC_CONFIG_BO_LIMIT_2 +//! +//! Handling of insertion or replacement of the source address in all +//! transmitted frames is described by one of the following fields: +//! +//! - \b EMAC_CONFIG_SA_INSERT causes the MAC address (0 or 1 depending +//! on whether \b EMAC_CONFIG_USE_MACADDR0 or \b EMAC_CONFIG_USE_MACADDR1 +//! was specified) to be inserted into all transmitted frames. +//! - \b EMAC_CONFIG_SA_REPLACE causes the MAC address to be replaced with +//! the selected address in all transmitted frames. +//! - \b EMAC_CONFIG_SA_FROM_DESCRIPTOR causes control of source address +//! insertion or deletion to be controlled by fields in the DMA transmit +//! descriptor, allowing control on a frame-by-frame basis. +//! +//! Whether the interface attempts to operate in full- or half-duplex mode is +//! reported by one of the following flags: +//! +//! - \b EMAC_CONFIG_FULL_DUPLEX +//! - \b EMAC_CONFIG_HALF_DUPLEX +//! +//! The following additional flags may also be included: +//! +//! - \b EMAC_CONFIG_2K_PACKETS indicates that IEEE802.3as support for 2K +//! packets is enabled. When present, the MAC considers all frames up to 2000 +//! bytes in length as normal packets. When \b EMAC_CONFIG_JUMBO_ENABLE is +//! not reported, all frames larger than 2000 bytes are treated as Giant +//! frames. The value of this flag should be ignored if +//! \b EMAC_CONFIG_JUMBO_ENABLE is also reported. +//! - \b EMAC_CONFIG_STRIP_CRC indicates that the 4-byte CRC of all Ethernet +//! type frames is being stripped and dropped before the frame is forwarded to +//! the application. +//! - \b EMAC_CONFIG_JABBER_DISABLE indicates that the the jabber timer on the +//! transmitter is disabled, allowing frames of up to 16384 bytes to be +//! transmitted. If this flag is absent, the MAC does not allow more than 2048 +//! (or 10240 if \b EMAC_CONFIG_JUMBO_ENABLE is reported) bytes to be sent in +//! any one frame. +//! - \b EMAC_CONFIG_JUMBO_ENABLE indicates that Jumbo Frames of up to 9018 +//! (or 9022 if using VLAN tagging) are enabled. +//! - \b EMAC_CONFIG_CS_DISABLE indicates that Carrier Sense is disabled +//! during transmission when operating in half-duplex mode. +//! - \b EMAC_CONFIG_100MBPS indicates that the MAC is using 100Mbps +//! signaling to communicate with the PHY. +//! - \b EMAC_CONFIG_RX_OWN_DISABLE indicates that reception of transmitted +//! frames is disabled when operating in half-duplex mode. +//! - \b EMAC_CONFIG_LOOPBACK indicates that internal loopback is enabled. +//! - \b EMAC_CONFIG_CHECKSUM_OFFLOAD indicates that IPv4 header checksum +//! checking and IPv4 or IPv6 TCP, UPD or ICMP payload checksum checking is +//! enabled. The results of the checksum calculations are reported via status +//! fields in the DMA receive descriptors. +//! - \b EMAC_CONFIG_RETRY_DISABLE indicates that retransmission is disabled +//! in cases where half-duplex mode is in use and a collision occurs. This +//! condition causes the current frame to be ignored and a frame abort to be +//! reported in the transmit frame status. +//! - \b EMAC_CONFIG_AUTO_CRC_STRIPPING indicates that the last 4 bytes +//! (frame check sequence) from all Ether type frames are being stripped before +//! frames are forwarded to the application. +//! - \b EMAC_CONFIG_DEFERRAL_CHK_ENABLE indicates that transmit deferral +//! checking is disabled in half-duplex mode. When enabled, the transmitter +//! reports an error if it is unable to transmit a frame for more than 24288 +//! bit times (or 155680 bit times in Jumbo frame mode) due to an active +//! carrier sense signal on the MII. +//! - \b EMAC_CONFIG_TX_ENABLED indicates that the MAC transmitter is +//! currently enabled. +//! - \b EMAC_CONFIG_RX_ENABLED indicates that the MAC receiver is +//! currently enabled. +//! +//! The \e pui32ModeFlags parameter is written with operating parameters +//! related to the internal MAC FIFOs. It comprises a logical OR of the +//! following fields. The first field reports the transmit FIFO threshold. +//! Transmission of a frame begins when this amount of data or a full frame +//! exists in the transmit FIFO. This field should be ignored if +//! \b EMAC_MODE_TX_STORE_FORWARD is also reported. One of the following +//! values is reported: +//! +//! - \b EMAC_MODE_TX_THRESHOLD_16_BYTES +//! - \b EMAC_MODE_TX_THRESHOLD_24_BYTES +//! - \b EMAC_MODE_TX_THRESHOLD_32_BYTES +//! - \b EMAC_MODE_TX_THRESHOLD_40_BYTES +//! - \b EMAC_MODE_TX_THRESHOLD_64_BYTES +//! - \b EMAC_MODE_TX_THRESHOLD_128_BYTES +//! - \b EMAC_MODE_TX_THRESHOLD_192_BYTES +//! - \b EMAC_MODE_TX_THRESHOLD_256_BYTES +//! +//! The second field reports the receive FIFO threshold. DMA transfers of +//! received data begin either when the receive FIFO contains a full frame +//! or this number of bytes. This field should be ignored if +//! \b EMAC_MODE_RX_STORE_FORWARD is included. One of the following values +//! is reported: +//! +//! - \b EMAC_MODE_RX_THRESHOLD_64_BYTES +//! - \b EMAC_MODE_RX_THRESHOLD_32_BYTES +//! - \b EMAC_MODE_RX_THRESHOLD_96_BYTES +//! - \b EMAC_MODE_RX_THRESHOLD_128_BYTES +//! +//! The following additional flags may be included: +//! +//! - \b EMAC_MODE_KEEP_BAD_CRC indicates that frames with TCP/IP checksum +//! errors are being forwarded to the application if those frames do not have +//! any errors (including FCS errors) in the Ethernet framing. In these cases, +//! the frames have errors only in the payload. If this flag is not reported, +//! all frames with any detected error are discarded unless +//! \b EMAC_MODE_RX_ERROR_FRAMES is also reported. +//! - \b EMAC_MODE_RX_STORE_FORWARD indicates that the receive DMA is +//! configured to read frames from the FIFO only after the complete frame has +//! been written to it. If this mode is enabled, the receive threshold is +//! ignored. +//! - \b EMAC_MODE_RX_FLUSH_DISABLE indicates that the flushing of received +//! frames is disabled in cases where receive descriptors or buffers are +//! unavailable. +//! - \b EMAC_MODE_TX_STORE_FORWARD indicates that the transmitter is +//! configured to transmit a frame only after the whole frame has been written +//! to the transmit FIFO. If this mode is enabled, the transmit threshold is +//! ignored. +//! - \b EMAC_MODE_RX_ERROR_FRAMES indicates that all frames other than runt +//! error frames are being forwarded to the receive DMA regardless of any +//! errors detected in the frames. +//! - \b EMAC_MODE_RX_UNDERSIZED_FRAMES indicates that undersized frames +//! (frames shorter than 64 bytes but with no errors) are being forwarded to +//! the application. If this option is not reported, all undersized frames are +//! dropped by the receiver unless it has already started transferring them to +//! the receive FIFO due to the receive threshold setting. +//! - \b EMAC_MODE_OPERATE_2ND_FRAME indicates that the transmit DMA is +//! configured to operate on a second frame while waiting for the previous +//! frame to be transmitted and associated status and timestamps to be reported. +//! If absent, the transmit DMA works on a single frame at any one time, +//! waiting for that frame to be transmitted and its status to be received +//! before moving on to the next frame. +//! - \b EMAC_MODE_TX_DMA_ENABLED indicates that the transmit DMA engine is +//! currently enabled. +//! - \b EMAC_MODE_RX_DMA_ENABLED indicates that the receive DMA engine is +//! currently enabled. +//! +//! The \e pui32RxMaxFrameSize is written with the currently configured maximum +//! receive packet size. Packets larger than this are flagged as being in +//! error. +//! +//! \return None. +// +//***************************************************************************** +void +EMACConfigGet(uint32_t ui32Base, uint32_t *pui32Config, uint32_t *pui32Mode, + uint32_t *pui32RxMaxFrameSize) +{ + uint32_t ui32Value; + + // + // Parameter sanity check. + // + ASSERT(pui32Mode); + ASSERT(pui32Config); + ASSERT(pui32RxMaxFrameSize); + + // + // Return the mode information from the operation mode register. + // + *pui32Mode = HWREG(ui32Base + EMAC_O_DMAOPMODE); + + // + // Return the current configuration flags from the EMAC_O_CFG register. + // + *pui32Config = (HWREG(ui32Base + EMAC_O_CFG) & + (VALID_CONFIG_FLAGS | EMAC_CONFIG_TX_ENABLED | + EMAC_CONFIG_RX_ENABLED)); + + // + // Get the receive packet size watchdog value. + // + ui32Value = HWREG(ui32Base + EMAC_O_WDOGTO); + if(ui32Value & EMAC_WDOGTO_PWE) + { + // + // The watchdog is enables so the maximum packet length can be read + // from the watchdog timeout register. + // + *pui32RxMaxFrameSize = ui32Value & EMAC_WDOGTO_WTO_M; + } + else + { + // + // The maximum packet size override found in the watchdog timer + // register is not enabled so the maximum packet size is determined + // by whether or not jumbo frame mode is enabled. + // + if(HWREG(ui32Base + EMAC_O_CFG) & EMAC_CFG_JFEN) + { + // + // Jumbo frames are enabled so the watchdog kicks in at 10240 + // bytes. + // + *pui32RxMaxFrameSize = 10240; + } + else + { + // + // Jumbo frames are not enabled so the watchdog kicks in at + // 2048 bytes. + // + *pui32RxMaxFrameSize = 2048; + } + } +} + +//***************************************************************************** +// +//! Sets the MAC address of the Ethernet controller. +//! +//! \param ui32Base is the base address of the Ethernet controller. +//! \param ui32Index is the zero-based index of the MAC address to set. +//! \param pui8MACAddr is the pointer to the array of MAC-48 address octets. +//! +//! This function programs the IEEE-defined MAC-48 address specified in +//! \e pui8MACAddr into the Ethernet controller. This address is used by the +//! Ethernet controller for hardware-level filtering of incoming Ethernet +//! packets (when promiscuous mode is not enabled). Index 0 is used to hold +//! the local node's MAC address which is inserted into all transmitted +//! packets. +//! +//! The controller may support several Ethernet MAC address slots, each of which +//! may be programmed independently and used to filter incoming packets. The +//! number of MAC addresses that the hardware supports may be queried using a +//! call to EMACNumAddrGet(). The value of the \e ui32Index parameter must +//! lie in the range from 0 to (number of MAC addresses - 1) inclusive. +//! +//! The MAC-48 address is defined as 6 octets, illustrated by the following +//! example address. The numbers are shown in hexadecimal format. +//! +//! AC-DE-48-00-00-80 +//! +//! In this representation, the first three octets (AC-DE-48) are the +//! Organizationally Unique Identifier (OUI). This is a number assigned by +//! the IEEE to an organization that requests a block of MAC addresses. The +//! last three octets (00-00-80) are a 24-bit number managed by the OUI owner +//! to uniquely identify a piece of hardware within that organization that is +//! to be connected to the Ethernet. +//! +//! In this representation, the octets are transmitted from left to right, +//! with the ``AC'' octet being transmitted first and the ``80'' octet being +//! transmitted last. Within an octet, the bits are transmitted LSB to MSB. +//! For this address, the first bit to be transmitted would be ``0'', the LSB +//! of ``AC'', and the last bit to be transmitted would be ``1'', the MSB of +//! ``80''. +//! +//! The address passed to this function in the \e pui8MACAddr array is +//! ordered with the first byte to be transmitted in the first array entry. +//! For example, the address given above could be represented using the +//! following array: +//! +//! uint8_t g_pui8MACAddr[] = { 0xAC, 0xDE, 0x48, 0x00, 0x00, 0x80 }; +//! +//! If the MAC address set by this function is currently enabled, it remains +//! enabled following this call. Similarly, any filter configured for +//! the MAC address remains unaffected by a change in the address. +//! +//! \return None. +// +//***************************************************************************** +void +EMACAddrSet(uint32_t ui32Base, uint32_t ui32Index, const uint8_t *pui8MACAddr) +{ + // + // Parameter sanity check. + // + ASSERT(ui32Index < NUM_MAC_ADDR); + ASSERT(pui8MACAddr); + + // + // Set the high 2 bytes of the MAC address. Note that we must set the + // registers in this order since the address is latched internally + // on the write to EMAC_O_ADDRL. + // + HWREG(ui32Base + EMAC_O_ADDRH(ui32Index)) = + ((HWREG(ui32Base + EMAC_O_ADDRH(ui32Index)) & 0xFFFF0000) | + pui8MACAddr[4] | (pui8MACAddr[5] << 8)); + + // + // Set the first 4 bytes of the MAC address + // + HWREG(ui32Base + EMAC_O_ADDRL(ui32Index)) = + (pui8MACAddr[0] | (pui8MACAddr[1] << 8) | (pui8MACAddr[2] << 16) | + (pui8MACAddr[3] << 24)); +} + +//***************************************************************************** +// +//! Gets one of the MAC addresses stored in the Ethernet controller. +//! +//! \param ui32Base is the base address of the controller. +//! \param ui32Index is the zero-based index of the MAC address to return. +//! \param pui8MACAddr is the pointer to the location in which to store the +//! array of MAC-48 address octets. +//! +//! This function reads the currently programmed MAC address into the +//! \e pui8MACAddr buffer. The \e ui32Index parameter defines which of the +//! hardware's MAC addresses to return. The number of MAC addresses supported +//! by the controller may be queried using a call to EMACNumAddrGet(). +//! Index 0 refers to the MAC address of the local node. Other indices are +//! used to define MAC addresses when filtering incoming packets. +//! +//! The address is written to the pui8MACAddr array ordered with the first byte +//! to be transmitted in the first array entry. For example, if the address +//! is written in its usual form with the Organizationally Unique Identifier +//! (OUI) shown first as: +//! +//! AC-DE-48-00-00-80 +//! +//! the data is returned with 0xAC in the first byte of the array, 0xDE in +//! the second, 0x48 in the third and so on. +//! +//! \return None. +// +//***************************************************************************** +void +EMACAddrGet(uint32_t ui32Base, uint32_t ui32Index, uint8_t *pui8MACAddr) +{ + uint32_t ui32Val; + + // + // Parameter sanity check. + // + ASSERT(ui32Index < NUM_MAC_ADDR); + ASSERT(pui8MACAddr); + + // + // Get the first 4 bytes of the MAC address. + // + ui32Val = HWREG(ui32Base + EMAC_O_ADDRL(ui32Index)); + pui8MACAddr[0] = ui32Val & 0xFF; + pui8MACAddr[1] = (ui32Val >> 8) & 0xFF; + pui8MACAddr[2] = (ui32Val >> 16) & 0xFF; + pui8MACAddr[3] = (ui32Val >> 24) & 0xFF; + + // + // Get the last 2 bytes of the MAC address. + // + ui32Val = HWREG(ui32Base + EMAC_O_ADDRH(ui32Index)); + pui8MACAddr[4] = ui32Val & 0xFF; + pui8MACAddr[5] = (ui32Val >> 8) & 0xFF; +} + +//***************************************************************************** +// +//! Returns the number of MAC addresses supported by the Ethernet controller. +//! +//! \param ui32Base is the base address of the Ethernet controller. +//! +//! This function may be used to determine the number of MAC addresses that the +//! given controller supports. MAC address slots may be used when performing +//! perfect (rather than hash table) filtering of packets. +//! +//! \return Returns the number of supported MAC addresses. +// +//***************************************************************************** +uint32_t +EMACNumAddrGet(uint32_t ui32Base) +{ + // + // The only Ethernet controller on Snowflake supports 4 MAC addresses. + // + return(NUM_MAC_ADDR); +} + +//***************************************************************************** +// +//! Sets filtering parameters associated with one of the configured MAC +//! addresses. +//! +//! \param ui32Base is the base address of the controller. +//! \param ui32Index is the index of the MAC address slot for which the filter +//! is to be set. +//! \param ui32Config sets the filter parameters for the given MAC address. +//! +//! This function sets filtering parameters associated with one of the MAC +//! address slots that the controller supports. This configuration is used +//! when perfect filtering (rather than hash table filtering) is selected. +//! +//! Valid values for \e ui32Index are from 1 to (number of MAC address +//! slots - 1). The number of supported MAC address slots may be found by +//! calling EMACNumAddrGet(). MAC index 0 is the local MAC address and does +//! not have filtering parameters associated with it. +//! +//! The \e ui32Config parameter determines how the given MAC address is used +//! when filtering incoming Ethernet frames. It is comprised of a logical OR +//! of the fields: +//! +//! - \b EMAC_FILTER_ADDR_ENABLE indicates that this MAC address is enabled +//! and should be used when performing perfect filtering. If this flag is +//! absent, the MAC address at the given index is disabled and is not used +//! in filtering. +//! - \b EMAC_FILTER_SOURCE_ADDR indicates that the MAC address at the given +//! index is compared to the source address of incoming frames while +//! performing perfect filtering. If absent, the MAC address is compared +//! against the destination address. +//! - \b EMAC_FILTER_MASK_BYTE_6 indicates that the MAC should ignore the +//! sixth byte of the source or destination address when filtering. +//! - \b EMAC_FILTER_MASK_BYTE_5 indicates that the MAC should ignore the +//! fifth byte of the source or destination address when filtering. +//! - \b EMAC_FILTER_MASK_BYTE_4 indicates that the MAC should ignore the +//! fourth byte of the source or destination address when filtering. +//! - \b EMAC_FILTER_MASK_BYTE_3 indicates that the MAC should ignore the +//! third byte of the source or destination address when filtering. +//! - \b EMAC_FILTER_MASK_BYTE_2 indicates that the MAC should ignore the +//! second byte of the source or destination address when filtering. +//! - \b EMAC_FILTER_MASK_BYTE_1 indicates that the MAC should ignore the +//! first byte of the source or destination address when filtering. +//! +//! \return None. +// +//***************************************************************************** +void +EMACAddrFilterSet(uint32_t ui32Base, uint32_t ui32Index, uint32_t ui32Config) +{ + uint32_t ui32Val; + + // + // Parameter sanity check. + // + ASSERT(ui32Index < NUM_MAC_ADDR); + ASSERT((ui32Config & ~(EMAC_FILTER_BYTE_MASK_M | + EMAC_FILTER_ADDR_ENABLE | + EMAC_FILTER_SOURCE_ADDR)) == 0); + ASSERT(ui32Index); + + // + // Set the filter configuration for a particular MAC address. + // + HWREG(ui32Base + EMAC_O_ADDRH(ui32Index)) = + (HWREG(ui32Base + EMAC_O_ADDRH(ui32Index)) & 0xFFFF) | ui32Config; + + // + // Read and rewrite the low half of the MAC address register to ensure + // that the upper half's data is latched. + // + ui32Val = HWREG(ui32Base + EMAC_O_ADDRL(ui32Index)); + HWREG(ui32Base + EMAC_O_ADDRL(ui32Index)) = ui32Val; +} + +//***************************************************************************** +// +//! Gets filtering parameters associated with one of the configured MAC +//! addresses. +//! +//! \param ui32Base is the base address of the controller. +//! \param ui32Index is the index of the MAC address slot for which the filter +//! is to be queried. +//! +//! This function returns filtering parameters associated with one of the MAC +//! address slots that the controller supports. This configuration is used +//! when perfect filtering (rather than hash table filtering) is selected. +//! +//! Valid values for \e ui32Index are from 1 to (number of MAC address +//! slots - 1). The number of supported MAC address slots may be found by +//! calling EMACNumAddrGet(). MAC index 0 is the local MAC address and does +//! not have filtering parameters associated with it. +//! +//! \return Returns the filter configuration as the logical OR of the +//! following labels: +//! +//! - \b EMAC_FILTER_ADDR_ENABLE indicates that this MAC address is enabled +//! and is used when performing perfect filtering. If this flag is absent, +//! the MAC address at the given index is disabled and is not used in +//! filtering. +//! - \b EMAC_FILTER_SOURCE_ADDR indicates that the MAC address at the given +//! index is compared to the source address of incoming frames while performing +//! perfect filtering. If absent, the MAC address is compared against the +//! destination address. +//! - \b EMAC_FILTER_MASK_BYTE_6 indicates that the MAC ignores the +//! sixth byte of the source or destination address when filtering. +//! - \b EMAC_FILTER_MASK_BYTE_5 indicates that the MAC ignores the +//! fifth byte of the source or destination address when filtering. +//! - \b EMAC_FILTER_MASK_BYTE_4 indicates that the MAC ignores the +//! fourth byte of the source or destination address when filtering. +//! - \b EMAC_FILTER_MASK_BYTE_3 indicates that the MAC ignores the +//! third byte of the source or destination address when filtering. +//! - \b EMAC_FILTER_MASK_BYTE_2 indicates that the MAC ignores the +//! second byte of the source or destination address when filtering. +//! - \b EMAC_FILTER_MASK_BYTE_1 indicates that the MAC ignores the +//! first byte of the source or destination address when filtering. +// +//***************************************************************************** +uint32_t +EMACAddrFilterGet(uint32_t ui32Base, uint32_t ui32Index) +{ + // + // Parameter sanity check. + // + ASSERT(ui32Index < NUM_MAC_ADDR); + ASSERT(ui32Index); + + // + // Read and return the filter settings for the requested MAC address slot. + // + return(HWREG(ui32Base + EMAC_O_ADDRH(ui32Index)) & + (EMAC_FILTER_BYTE_MASK_M | EMAC_FILTER_ADDR_ENABLE | + EMAC_FILTER_SOURCE_ADDR)); +} + +//***************************************************************************** +// +//! Sets options related to Ethernet frame filtering. +//! +//! \param ui32Base is the base address of the controller. +//! \param ui32FilterOpts is a logical OR of flags defining the required MAC +//! address filtering options. +//! +//! This function allows various filtering options to be defined and allows +//! an application to control which frames are received based on various +//! criteria related to the frame source and destination MAC addresses or VLAN +//! tagging. +//! +//! The \e ui32FilterOpts parameter is a logical OR of any of the following +//! flags: +//! +//! - \b EMAC_FRMFILTER_RX_ALL configures the MAC to pass all received frames +//! regardless of whether or not they pass any address filter that is +//! configured. The receive status word in the relevant DMA descriptor is +//! updated to indicate whether the configured filter passed or failed for +//! the frame. +//! - \b EMAC_FRMFILTER_VLAN configures the MAC to drop any frames that do +//! not pass the VLAN tag comparison. +//! - \b EMAC_FRMFILTER_HASH_AND_PERFECT configures the MAC to filter frames +//! based on both any perfect filters set and the hash filter if enabled using +//! \b EMAC_FRMFILTER_HASH_UNICAST or \b EMAC_FRMFILTER_HASH_MULTICAST. In +//! this case, only if both filters fail is the packet rejected. If this +//! option is absent, only one of the filter types is used, as controlled by +//! \b EMAC_FRMFILTER_HASH_UNICAST and \b EMAC_FRMFILTER_HASH_MULTICAST +//! for unicast and multicast frames respectively. +//! - \b EMAC_FRMFILTER_SADDR configures the MAC to drop received frames +//! when the source address field in the frame does not match the values +//! programmed into the enabled SA registers. +//! - \b EMAC_FRMFILTER_INV_SADDR enables inverse source address filtering. +//! When this option is specified, frames for which the SA does not match the +//! SA registers are marked as passing the source address filter. +//! - \b EMAC_FRMFILTER_BROADCAST configures the MAC to discard all incoming +//! broadcast frames. +//! - \b EMAC_FRMFILTER_PASS_MULTICAST configures the MAC to pass all +//! incoming frames with multicast destinations addresses. +//! - \b EMAC_FRMFILTER_INV_DADDR inverts the sense of the destination +//! address filtering for both unicast and multicast frames. +//! - \b EMAC_FRMFILTER_HASH_MULTICAST enables destination address filtering +//! of received multicast frames using the hash table. If absent, perfect +//! destination address filtering is used. If used in conjunction with \b +//! EMAC_FRMFILTER_HASH_AND_PERFECT, this flag indicates that the hash filter +//! should be used for incoming multicast packets along with the perfect +//! filter. +//! - \b EMAC_FRMFILTER_HASH_UNICAST enables destination address filtering +//! of received unicast frames using the hash table. If absent, perfect +//! destination address filtering is used. If used in conjunction with \b +//! EMAC_FRMFILTER_HASH_AND_PERFECT, this flag indicates that the hash filter +//! should be used for incoming unicast packets along with the perfect filter. +//! - \b EMAC_FRMFILTER_PROMISCUOUS configures the MAC to operate in +//! promiscuous mode where all received frames are passed to the application +//! and the SA and DA filter status bits of the descriptor receive status word +//! are always cleared. +//! +//! Control frame filtering may be configured by ORing one of the following +//! values into \e ui32FilterOpts: +//! +//! - \b EMAC_FRMFILTER_PASS_NO_CTRL prevents any control frame from reaching +//! the application. +//! - \b EMAC_FRMFILTER_PASS_NO_PAUSE passes all control frames other than +//! PAUSE even if they fail the configured address filter. +//! - \b EMAC_FRMFILTER_PASS_ALL_CTRL passes all control frames, including +//! PAUSE even if they fail the configured address filter. +//! - \b EMAC_FRMFILTER_PASS_ADDR_CTRL passes all control frames only if they +//! pass the configured address filter. +//! +//! \return None. +// +//***************************************************************************** +void +EMACFrameFilterSet(uint32_t ui32Base, uint32_t ui32FilterOpts) +{ + ASSERT((ui32FilterOpts & ~VALID_FRMFILTER_FLAGS) == 0); + + // + // Set the Ethernet MAC frame filter according to the flags passed. + // + HWREG(ui32Base + EMAC_O_FRAMEFLTR) = + ((HWREG(ui32Base + EMAC_O_FRAMEFLTR) & ~VALID_FRMFILTER_FLAGS) | + ui32FilterOpts); +} + +//***************************************************************************** +// +//! Returns the current Ethernet frame filtering settings. +//! +//! \param ui32Base is the base address of the controller. +//! +//! This function may be called to retrieve the frame filtering configuration +//! set using a prior call to EMACFrameFilterSet(). +//! +//! \return Returns a value comprising the logical OR of various flags +//! indicating the frame filtering options in use. Possible flags are: +//! +//! - \b EMAC_FRMFILTER_RX_ALL indicates that the MAC to is configured to +//! pass all received frames regardless of whether or not they pass any +//! address filter that is configured. The receive status word in the +//! relevant DMA descriptor is updated to indicate whether the configured +//! filter passed or failed for the frame. +//! - \b EMAC_FRMFILTER_VLAN indicates that the MAC is configured to drop any +//! frames which do not pass the VLAN tag comparison. +//! - \b EMAC_FRMFILTER_HASH_AND_PERFECT indicates that the MAC is configured +//! to pass frames if they match either the hash filter or the perfect filter. +//! If this flag is absent, frames passing based on the result of a single +//! filter, the perfect filter if \b EMAC_FRMFILTER_HASH_MULTICAST or +//! \b EMAC_FRMFILTER_HASH_UNICAST are clear or the hash filter otherwise. +//! - \b EMAC_FRMFILTER_SADDR indicates that the MAC is configured to drop +//! received frames when the source address field in the frame does not match +//! the values programmed into the enabled SA registers. +//! - \b EMAC_FRMFILTER_INV_SADDR enables inverse source address filtering. +//! When this option is specified, frames for which the SA does not match the +//! SA registers are marked as passing the source address filter. +//! - \b EMAC_FRMFILTER_BROADCAST indicates that the MAC is configured to +//! discard all incoming broadcast frames. +//! - \b EMAC_FRMFILTER_PASS_MULTICAST indicates that the MAC is configured +//! to pass all incoming frames with multicast destinations addresses. +//! - \b EMAC_FRMFILTER_INV_DADDR indicates that the sense of the destination +//! address filtering for both unicast and multicast frames is inverted. +//! - \b EMAC_FRMFILTER_HASH_MULTICAST indicates that destination address +//! filtering of received multicast frames is enabled using the hash table. If +//! absent, perfect destination address filtering is used. If used in +//! conjunction with \b EMAC_FRMFILTER_HASH_AND_PERFECT, this flag indicates +//! that the hash filter should be used for incoming multicast packets along +//! with the perfect filter. +//! - \b EMAC_FRMFILTER_HASH_UNICAST indicates that destination address +//! filtering of received unicast frames is enabled using the hash table. If +//! absent, perfect destination address filtering is used. If used in +//! conjunction with \b EMAC_FRMFILTER_HASH_AND_PERFECT, this flag indicates +//! that the hash filter should be used for incoming unicast packets along with +//! the perfect filter. +//! - \b EMAC_FRMFILTER_PROMISCUOUS indicates that the MAC is configured to +//! operate in promiscuous mode where all received frames are passed to the +//! application and the SA and DA filter status bits of the descriptor receive +//! status word are always cleared. +//! +//! Control frame filtering configuration is indicated by one of the following +//! values which may be extracted from the returned value using the mask +//! \b EMAC_FRMFILTER_PASS_MASK: +//! +//! - \b EMAC_FRMFILTER_PASS_NO_CTRL prevents any control frame from reaching +//! the application. +//! - \b EMAC_FRMFILTER_PASS_NO_PAUSE passes all control frames other than +//! PAUSE even if they fail the configured address filter. +//! - \b EMAC_FRMFILTER_PASS_ALL_CTRL passes all control frames, including +//! PAUSE even if they fail the configured address filter. +//! - \b EMAC_FRMFILTER_PASS_ADDR_CTRL passes all control frames only if they +//! pass the configured address filter. +// +//***************************************************************************** +uint32_t +EMACFrameFilterGet(uint32_t ui32Base) +{ + // + // Return the current MAC frame filter setting. + // + return(HWREG(ui32Base + EMAC_O_FRAMEFLTR) & VALID_FRMFILTER_FLAGS); +} + +//***************************************************************************** +// +//! Sets the MAC address hash filter table. +//! +//! \param ui32Base is the base address of the controller. +//! \param ui32HashHi is the upper 32 bits of the current 64-bit hash filter +//! table to set. +//! \param ui32HashLo is the lower 32 bits of the current 64-bit hash filter +//! table to set. +//! +//! This function may be used to set the current 64-bit hash filter table +//! used by the MAC to filter incoming packets when hash filtering is enabled. +//! Hash filtering is enabled by passing \b EMAC_FRMFILTER_HASH_UNICAST +//! and/or \b EMAC_FRMFILTER_HASH_MULTICAST in the \e ui32FilterOpts parameter +//! to EMACFrameFilterSet(). The current hash filter may be retrieved +//! by calling EMACHashFilterGet(). +//! +//! Hash table filtering allows many different MAC addresses to be filtered +//! simultaneously at the cost of some false-positive results (in the form of +//! packets passing the filter when their MAC address was not one of those +//! required). A CRC of the packet source or destination MAC address is +//! calculated and the bottom 6 bits are used as a bit index into the 64-bit +//! hash filter table. If the bit in the hash table is set, the filter is +//! considered to have passed. If the bit is clear, the filter fails and the +//! packet is rejected (assuming normal rather than inverse filtering is +//! configured). +//! +//! \return None. +// +//***************************************************************************** +void +EMACHashFilterSet(uint32_t ui32Base, uint32_t ui32HashHi, uint32_t ui32HashLo) +{ + // Set the hash table with the values provided. + HWREG(ui32Base + EMAC_O_HASHTBLL) = ui32HashLo; + HWREG(ui32Base + EMAC_O_HASHTBLH) = ui32HashHi; +} + +//***************************************************************************** +// +//! Returns the current MAC address hash filter table. +//! +//! \param ui32Base is the base address of the controller. +//! \param pui32HashHi points to storage to be written with the upper 32 bits +//! of the current 64-bit hash filter table. +//! \param pui32HashLo points to storage to be written with the lower 32 bits +//! of the current 64-bit hash filter table. +//! +//! This function may be used to retrieve the current 64-bit hash filter table +//! from the MAC prior to making changes and setting the new hash filter via a +//! call to EMACHashFilterSet(). +//! +//! Hash table filtering allows many different MAC addresses to be filtered +//! simultaneously at the cost of some false-positive results in the form of +//! packets passing the filter when their MAC address was not one of those +//! required. A CRC of the packet source or destination MAC address is +//! calculated and the bottom 6 bits are used as a bit index into the 64-bit +//! hash filter table. If the bit in the hash table is set, the filter is +//! considered to have passed. If the bit is clear, the filter fails and the +//! packet is rejected (assuming normal rather than inverse filtering is +//! configured). +//! +//! \return None. +// +//***************************************************************************** +void +EMACHashFilterGet(uint32_t ui32Base, uint32_t *pui32HashHi, + uint32_t *pui32HashLo) +{ + ASSERT(pui32HashHi); + ASSERT(pui32HashLo); + + // + // Get the current hash table values. + // + *pui32HashLo = HWREG(ui32Base + EMAC_O_HASHTBLL); + *pui32HashHi = HWREG(ui32Base + EMAC_O_HASHTBLH); +} + +//***************************************************************************** +// +//! Returns the bit number to set in the MAC hash filter corresponding to a +//! given MAC address. +//! +//! \param pui8MACAddr points to a buffer containing the 6-byte MAC address +//! for which the hash filter bit is to be determined. +//! +//! This function may be used to determine which bit in the MAC address hash +//! filter to set to describe a given 6-byte MAC address. The returned value is +//! a 6-bit number where bit 5 indicates which of the two hash table words is +//! affected and the bottom 5 bits indicate the bit number to set within that +//! word. For example, if 0x22 (100010b) is returned, this indicates that bit +//! 2 of word 1 (\e ui32HashHi as passed to EMACHashFilterSet()) must be set +//! to describe the passed MAC address. +//! +//! \return Returns the bit number to set in the MAC hash table to describe the +//! passed MAC address. +// +//***************************************************************************** +uint32_t +EMACHashFilterBitCalculate(uint8_t *pui8MACAddr) +{ + uint32_t ui32CRC, ui32Mask, ui32Loop; + + // + // Parameter sanity check. + // + ASSERT(pui8MACAddr); + + // + // Calculate the CRC for the MAC address. + // + ui32CRC = Crc32(0xFFFFFFFF, pui8MACAddr, 6); + ui32CRC ^= 0xFFFFFFFF; + + // + // Determine the hash bit to use from the calculated CRC. This is the + // top 6 bits of the reversed CRC (or the bottom 6 bits of the calculated + // CRC with the bit order of those 6 bits reversed). + // + ui32Mask = 0; + + // + // Reverse the order of the bottom 6 bits of the calculated CRC. + // + for(ui32Loop = 0; ui32Loop < 6; ui32Loop++) + { + ui32Mask <<= 1; + ui32Mask |= (ui32CRC & 1); + ui32CRC >>= 1; + } + + // + // Return the final hash table bit index. + // + return(ui32Mask); +} + +//***************************************************************************** +// +//! Sets the receive interrupt watchdog timer period. +//! +//! \param ui32Base is the base address of the Ethernet controller. +//! \param ui8Timeout is the desired timeout expressed as a number of 256 +//! system clock periods. +//! +//! This function configures the receive interrupt watchdog timer. +//! The \e uiTimeout parameter specifies the number of 256 system clock periods +//! that elapse before the timer expires. In cases where the DMA has +//! transferred a frame using a descriptor that has +//! \b DES1_RX_CTRL_DISABLE_INT set, the watchdog causes a receive +//! interrupt to be generated when it times out. The watchdog timer is reset +//! whenever a packet is transferred to memory using a DMA descriptor that +//! does not disable the receive interrupt. +//! +//! To disable the receive interrupt watchdog function, set \e ui8Timeout to 0. +//! +//! \return None. +// +//***************************************************************************** +void +EMACRxWatchdogTimerSet(uint32_t ui32Base, uint8_t ui8Timeout) +{ + // + // Set the receive interrupt watchdog timeout period. + // + HWREG(ui32Base + EMAC_O_RXINTWDT) = (uint32_t)ui8Timeout; +} + +//***************************************************************************** +// +//! Returns the current Ethernet MAC status. +//! +//! \param ui32Base is the base address of the Ethernet controller. +//! +//! This function returns information on the current status of all the main +//! modules in the MAC transmit and receive data paths. +//! +//! \return Returns the current MAC status as a logical OR of any of the +//! following flags: +//! +//! - \b EMAC_STATUS_TX_NOT_EMPTY +//! - \b EMAC_STATUS_TX_WRITING_FIFO +//! - \b EMAC_STATUS_TX_PAUSED +//! - \b EMAC_STATUS_MAC_NOT_IDLE +//! - \b EMAC_STATUS_RWC_ACTIVE +//! - \b EMAC_STATUS_RPE_ACTIVE +//! +//! The transmit frame controller status can be extracted from the returned +//! value by ANDing with \b EMAC_STATUS_TFC_STATE_MASK and is one of the +//! following: +//! +//! - \b EMAC_STATUS_TFC_STATE_IDLE +//! - \b EMAC_STATUS_TFC_STATE_WAITING +//! - \b EMAC_STATUS_TFC_STATE_PAUSING +//! - \b EMAC_STATUS_TFC_STATE_WRITING +//! +//! The transmit FIFO read controller status can be extracted from the returned +//! value by ANDing with \b EMAC_STATUS_TRC_STATE_MASK and is one of the +//! following: +//! +//! - \b EMAC_STATUS_TRC_STATE_IDLE +//! - \b EMAC_STATUS_TRC_STATE_READING +//! - \b EMAC_STATUS_TRC_STATE_WAITING +//! - \b EMAC_STATUS_TRC_STATE_STATUS +//! +//! The current receive FIFO levels can be extracted from the returned value +//! by ANDing with \b EMAC_STATUS_RX_FIFO_LEVEL_MASK and is one of the +//! following: +//! +//! - \b EMAC_STATUS_RX_FIFO_EMPTY indicating that the FIFO is empty. +//! - \b EMAC_STATUS_RX_FIFO_BELOW indicating that the FIFO fill level is +//! below the flow-control deactivate threshold. +//! - \b EMAC_STATUS_RX_FIFO_ABOVE indicating that the FIFO fill level is +//! above the flow-control activate threshold. +//! - \b EMAC_STATUS_RX_FIFO_FULL indicating that the FIFO is full. +//! +//! The current receive FIFO state can be extracted from the returned value +//! by ANDing with \b EMAC_STATUS_RX_FIFO_STATE_MASK and is one of the +//! following: +//! +//! - \b EMAC_STATUS_RX_FIFO_IDLE +//! - \b EMAC_STATUS_RX_FIFO_READING +//! - \b EMAC_STATUS_RX_FIFO_STATUS +//! - \b EMAC_STATUS_RX_FIFO_FLUSHING +// +//***************************************************************************** +uint32_t +EMACStatusGet(uint32_t ui32Base) +{ + // + // Read and return the MAC status register content. + // + return(HWREG(ui32Base + EMAC_O_STATUS)); +} + +//***************************************************************************** +// +//! Orders the MAC DMA controller to attempt to acquire the next transmit +//! descriptor. +//! +//! \param ui32Base is the base address of the Ethernet controller. +//! +//! This function must be called to restart the transmitter if it has been +//! suspended due to the current transmit DMA descriptor being owned by the +//! host. Once the application writes new values to the descriptor and marks +//! it as being owned by the MAC DMA, this function causes the hardware to +//! attempt to acquire the descriptor and start transmission of the new +//! data. +//! +//! \return None. +// +//***************************************************************************** +void +EMACTxDMAPollDemand(uint32_t ui32Base) +{ + // + // Any write to the MACTXPOLLD register causes the transmit DMA to attempt + // to resume. + // + HWREG(ui32Base + EMAC_O_TXPOLLD) = 0; +} + +//***************************************************************************** +// +//! Orders the MAC DMA controller to attempt to acquire the next receive +//! descriptor. +//! +//! \param ui32Base is the base address of the Ethernet controller. +//! +//! This function must be called to restart the receiver if it has been +//! suspended due to the current receive DMA descriptor being owned by the +//! host. Once the application reads any data from the descriptor and marks +//! it as being owned by the MAC DMA, this function causes the hardware to +//! attempt to acquire the descriptor before writing the next received packet +//! into its buffer(s). +//! +//! \return None. +// +//***************************************************************************** +void +EMACRxDMAPollDemand(uint32_t ui32Base) +{ + // + // Any write to the MACRXPOLLD register causes the receive DMA to attempt + // to resume. + // + HWREG(ui32Base + EMAC_O_RXPOLLD) = 0; +} + +//***************************************************************************** +// +//! Sets the DMA receive descriptor list pointer. +//! +//! \param ui32Base is the base address of the controller. +//! \param pDescriptor points to the first DMA descriptor in the list to +//! be passed to the receive DMA engine. +//! +//! This function sets the Ethernet MAC's receive DMA descriptor list pointer. +//! The \e pDescriptor pointer must point to one or more descriptor +//! structures. +//! +//! When multiple descriptors are provided, they can be either chained or +//! unchained. Chained descriptors are indicated by setting the +//! \b DES0_TX_CTRL_CHAINED or \b DES1_RX_CTRL_CHAINED bit in the relevant +//! word of the transmit or receive descriptor. If this bit is clear, +//! unchained descriptors are assumed. +//! +//! Chained descriptors use a link pointer in each descriptor to +//! point to the next descriptor in the chain. +//! +//! Unchained descriptors are assumed to be contiguous in memory with a +//! consistent offset between the start of one descriptor and the next. +//! If unchained descriptors are used, the \e pvLink field in the descriptor +//! becomes available to store a second buffer pointer, allowing each +//! descriptor to point to two buffers rather than one. In this case, +//! the \e ui32DescSkipSize parameter to EMACInit() must previously have +//! been set to the number of words between the end of one descriptor and +//! the start of the next. This value must be 0 in cases where a packed array +//! of \b tEMACDMADescriptor structures is used. If the application wishes to +//! add new state fields to the end of the descriptor structure, the skip size +//! should be set to accommodate the newly sized structure. +//! +//! Applications are responsible for initializing all descriptor fields +//! appropriately before passing the descriptor list to the hardware. +//! +//! \return None. +// +//***************************************************************************** +void +EMACRxDMADescriptorListSet(uint32_t ui32Base, tEMACDMADescriptor *pDescriptor) +{ + // + // Parameter sanity check. + // + ASSERT(pDescriptor); + ASSERT(((uint32_t)pDescriptor & 3) == 0); + + // + // Write the supplied address to the MACRXDLADDR register. + // + HWREG(ui32Base + EMAC_O_RXDLADDR) = (uint32_t)pDescriptor; +} + +//***************************************************************************** +// +//! Returns a pointer to the start of the DMA receive descriptor list. +//! +//! \param ui32Base is the base address of the controller. +//! +//! This function returns a pointer to the head of the Ethernet MAC's receive +//! DMA descriptor list. This value corresponds to the pointer originally set +//! using a call to EMACRxDMADescriptorListSet(). +//! +//! \return Returns a pointer to the start of the DMA receive descriptor list. +// +//***************************************************************************** +tEMACDMADescriptor * +EMACRxDMADescriptorListGet(uint32_t ui32Base) +{ + // + // Return the current receive DMA descriptor list pointer. + // + return((tEMACDMADescriptor *)HWREG(ui32Base + EMAC_O_RXDLADDR)); +} + +//***************************************************************************** +// +//! Returns the current DMA receive descriptor pointer. +//! +//! \param ui32Base is the base address of the controller. +//! +//! This function returns a pointer to the current Ethernet receive descriptor +//! read by the DMA. +//! +//! \return Returns a pointer to the start of the current receive DMA +//! descriptor. +// +//***************************************************************************** +tEMACDMADescriptor * +EMACRxDMACurrentDescriptorGet(uint32_t ui32Base) +{ + // + // Return the address of the current receive descriptor written by the DMA. + // + return((tEMACDMADescriptor *)HWREG(ui32Base + EMAC_O_HOSRXDESC)); +} + +//***************************************************************************** +// +//! Returns the current DMA receive buffer pointer. +//! +//! \param ui32Base is the base address of the controller. +//! +//! This function may be called to determine which buffer the receive DMA +//! engine is currently writing to. +//! +//! \return Returns the receive buffer address currently being written by +//! the DMA engine. +// +//***************************************************************************** +uint8_t * +EMACRxDMACurrentBufferGet(uint32_t ui32Base) +{ + // + // Return the receive buffer address currently being written by the DMA. + // + return((uint8_t *)HWREG(ui32Base + EMAC_O_HOSRXBA)); +} + +//***************************************************************************** +// +//! Sets the DMA transmit descriptor list pointer. +//! +//! \param ui32Base is the base address of the controller. +//! \param pDescriptor points to the first DMA descriptor in the list to +//! be passed to the transmit DMA engine. +//! +//! This function sets the Ethernet MAC's transmit DMA descriptor list pointer. +//! The \e pDescriptor pointer must point to one or more descriptor +//! structures. +//! +//! When multiple descriptors are provided, they can be either chained or +//! unchained. Chained descriptors are indicated by setting the +//! \b DES0_TX_CTRL_CHAINED or \b DES1_RX_CTRL_CHAINED bit in the relevant +//! word of the transmit or receive descriptor. If this bit is clear, +//! unchained descriptors are assumed. +//! +//! Chained descriptors use a link pointer in each descriptor to +//! point to the next descriptor in the chain. +//! +//! Unchained descriptors are assumed to be contiguous in memory with a +//! consistent offset between the start of one descriptor and the next. +//! If unchained descriptors are used, the \e pvLink field in the descriptor +//! becomes available to store a second buffer pointer, allowing each +//! descriptor to point to two buffers rather than one. In this case, +//! the \e ui32DescSkipSize parameter to EMACInit() must previously have +//! been set to the number of words between the end of one descriptor and +//! the start of the next. This value must be 0 in cases where a packed array +//! of \b tEMACDMADescriptor structures is used. If the application wishes to +//! add new state fields to the end of the descriptor structure, the skip size +//! should be set to accommodate the newly sized structure. +//! +//! Applications are responsible for initializing all descriptor fields +//! appropriately before passing the descriptor list to the hardware. +//! +//! \return None. +// +//***************************************************************************** +void +EMACTxDMADescriptorListSet(uint32_t ui32Base, tEMACDMADescriptor *pDescriptor) +{ + // + // Parameter sanity check. + // + ASSERT(pDescriptor); + ASSERT(((uint32_t)pDescriptor & 3) == 0); + + // + // Write the supplied address to the MACTXDLADDR register. + // + HWREG(ui32Base + EMAC_O_TXDLADDR) = (uint32_t)pDescriptor; +} + +//***************************************************************************** +// +//! Returns a pointer to the start of the DMA transmit descriptor list. +//! +//! \param ui32Base is the base address of the controller. +//! +//! This function returns a pointer to the head of the Ethernet MAC's transmit +//! DMA descriptor list. This value corresponds to the pointer originally set +//! using a call to EMACTxDMADescriptorListSet(). +//! +//! \return Returns a pointer to the start of the DMA transmit descriptor list. +// +//***************************************************************************** +tEMACDMADescriptor * +EMACTxDMADescriptorListGet(uint32_t ui32Base) +{ + // + // Return the current transmit DMA descriptor list pointer. + // + return((tEMACDMADescriptor *)HWREG(ui32Base + EMAC_O_TXDLADDR)); +} + +//***************************************************************************** +// +//! Returns the current DMA transmit descriptor pointer. +//! +//! \param ui32Base is the base address of the controller. +//! +//! This function returns a pointer to the current Ethernet transmit descriptor +//! read by the DMA. +//! +//! \return Returns a pointer to the start of the current transmit DMA +//! descriptor. +// +//***************************************************************************** +tEMACDMADescriptor * +EMACTxDMACurrentDescriptorGet(uint32_t ui32Base) +{ + // + // Return the address of the current transmit descriptor read by the DMA. + // + return((tEMACDMADescriptor *)HWREG(ui32Base + EMAC_O_HOSTXDESC)); +} + +//***************************************************************************** +// +//! Returns the current DMA transmit buffer pointer. +//! +//! \param ui32Base is the base address of the controller. +//! +//! This function may be called to determine which buffer the transmit DMA +//! engine is currently reading from. +//! +//! \return Returns the transmit buffer address currently being read by the +//! DMA engine. +// +//***************************************************************************** +uint8_t * +EMACTxDMACurrentBufferGet(uint32_t ui32Base) +{ + // + // Return the transmit buffer address currently being read by the DMA. + // + return((uint8_t *)HWREG(ui32Base + EMAC_O_HOSTXBA)); +} + +//***************************************************************************** +// +//! Returns the current states of the Ethernet MAC transmit and receive DMA +//! engines. +//! +//! \param ui32Base is the base address of the controller. +//! +//! This function may be used to query the current states of the transmit and +//! receive DMA engines. The return value contains two fields, one providing +//! the transmit state and the other the receive state. Macros +//! \b EMAC_TX_DMA_STATE() and \b EMAC_RX_DMA_STATE() may be used to +//! extract these fields from the returned value. Alternatively, masks +//! \b EMAC_DMA_TXSTAT_MASK and \b EMAC_DMA_RXSTAT_MASK may be used +//! directly to mask out the individual states from the returned value. +//! +//! \return Returns the states of the transmit and receive DMA engines. These +//! states are ORed together into a single word containing one of: +//! +//! - \b EMAC_DMA_TXSTAT_STOPPED indicating that the transmit engine is +//! stopped. +//! - \b EMAC_DMA_TXSTAT_RUN_FETCH_DESC indicating that the transmit engine +//! is fetching the next descriptor. +//! - \b EMAC_DMA_TXSTAT_RUN_WAIT_STATUS indicating that the transmit engine +//! is waiting for status from the MAC. +//! - \b EMAC_DMA_TXSTAT_RUN_READING indicating that the transmit engine is +//! currently transferring data from memory to the MAC transmit FIFO. +//! - \b EMAC_DMA_TXSTAT_RUN_CLOSE_DESC indicating that the transmit engine +//! is closing the descriptor after transmission of the buffer data. +//! - \b EMAC_DMA_TXSTAT_TS_WRITE indicating that the transmit engine is +//! currently writing timestamp information to the descriptor. +//! - \b EMAC_DMA_TXSTAT_SUSPENDED indicating that the transmit engine is +//! suspended due to the next descriptor being unavailable (owned by the host) +//! or a transmit buffer underflow. +//! +//! and one of: +//! +//! - \b EMAC_DMA_RXSTAT_STOPPED indicating that the receive engine is +//! stopped. +//! - \b EMAC_DMA_RXSTAT_RUN_FETCH_DESC indicating that the receive engine +//! is fetching the next descriptor. +//! - \b EMAC_DMA_RXSTAT_RUN_WAIT_PACKET indicating that the receive engine +//! is waiting for the next packet. +//! - \b EMAC_DMA_RXSTAT_SUSPENDED indicating that the receive engine is +//! suspended due to the next descriptor being unavailable. +//! - \b EMAC_DMA_RXSTAT_RUN_CLOSE_DESC indicating that the receive engine +//! is closing the descriptor after receiving a buffer of data. +//! - \b EMAC_DMA_RXSTAT_TS_WRITE indicating that the transmit engine is +//! currently writing timestamp information to the descriptor. +//! - \b EMAC_DMA_RXSTAT_RUN_RECEIVING indicating that the receive engine is +//! currently transferring data from the MAC receive FIFO to memory. +//! +//! Additionally, a DMA bus error may be signaled using \b EMAC_DMA_ERROR. +//! If this flag is present, the source of the error is identified using one +//! of the following values which may be extracted from the return value using +//! \b EMAC_DMA_ERR_MASK: +//! +//! - \b EMAC_DMA_ERR_RX_DATA_WRITE indicates that an error occurred when +//! writing received data to memory. +//! - \b EMAC_DMA_ERR_TX_DATA_READ indicates that an error occurred when +//! reading data from memory for transmission. +//! - \b EMAC_DMA_ERR_RX_DESC_WRITE indicates that an error occurred when +//! writing to the receive descriptor. +//! - \b EMAC_DMA_ERR_TX_DESC_WRITE indicates that an error occurred when +//! writing to the transmit descriptor. +//! - \b EMAC_DMA_ERR_RX_DESC_READ indicates that an error occurred when +//! reading the receive descriptor. +//! - \b EMAC_DMA_ERR_TX_DESC_READ indicates that an error occurred when +//! reading the transmit descriptor. +// +//***************************************************************************** +uint32_t +EMACDMAStateGet(uint32_t ui32Base) +{ + // + // Return the status of the DMA channels. + // + return(HWREG(ui32Base + EMAC_O_DMARIS) & + (EMAC_DMARIS_FBI | EMAC_DMARIS_AE_M | EMAC_DMARIS_RS_M | + EMAC_DMARIS_TS_M)); +} + +//***************************************************************************** +// +//! Flushes the Ethernet controller transmit FIFO. +//! +//! \param ui32Base is the base address of the controller. +//! +//! This function flushes any data currently held in the Ethernet transmit +//! FIFO. Data that has already been passed to the MAC for transmission is +//! transmitted, possibly resulting in a transmit underflow or runt frame +//! transmission. +//! +//! \return None. +// +//***************************************************************************** +void +EMACTxFlush(uint32_t ui32Base) +{ + // + // Check to make sure that the FIFO is not already empty. + // + if(HWREG(ui32Base + EMAC_O_STATUS) & EMAC_STATUS_TXFE) + { + // + // Flush the transmit FIFO since it is not currently empty. + // + HWREG(ui32Base + EMAC_O_DMAOPMODE) |= EMAC_DMAOPMODE_FTF; + + // + // Wait for the flush to complete. + // + while(HWREG(ui32Base + EMAC_O_DMAOPMODE) & EMAC_DMAOPMODE_FTF) + { + } + } +} + +//***************************************************************************** +// +//! Enables the Ethernet controller transmitter. +//! +//! \param ui32Base is the base address of the controller. +//! +//! When starting operations on the Ethernet interface, this function should +//! be called to enable the transmitter after all configuration has been +//! completed. +//! +//! \return None. +// +//***************************************************************************** +void +EMACTxEnable(uint32_t ui32Base) +{ + // + // Enable the MAC transmit path in the opmode register. + // + HWREG(ui32Base + EMAC_O_DMAOPMODE) |= EMAC_DMAOPMODE_ST; + + // + // Enable transmission in the MAC configuration register. + // + HWREG(ui32Base + EMAC_O_CFG) |= EMAC_CFG_TE; +} + +//***************************************************************************** +// +//! Disables the Ethernet controller transmitter. +//! +//! \param ui32Base is the base address of the controller. +//! +//! When terminating operations on the Ethernet interface, this function should +//! be called. This function disables the transmitter. +//! +//! \return None. +// +//***************************************************************************** +void +EMACTxDisable(uint32_t ui32Base) +{ + // + // Disable transmission in the MAC configuration register. + // + HWREG(ui32Base + EMAC_O_CFG) &= ~EMAC_CFG_TE; + + // + // Disable the MAC transmit path in the opmode register. + // + HWREG(ui32Base + EMAC_O_DMAOPMODE) &= ~EMAC_DMAOPMODE_ST; +} + +//***************************************************************************** +// +//! Enables the Ethernet controller receiver. +//! +//! \param ui32Base is the base address of the controller. +//! +//! When starting operations on the Ethernet interface, this function should +//! be called to enable the receiver after all configuration has been +//! completed. +//! +//! \return None. +// +//***************************************************************************** +void +EMACRxEnable(uint32_t ui32Base) +{ + // + // Enable the MAC receive path. + // + HWREG(ui32Base + EMAC_O_DMAOPMODE) |= EMAC_DMAOPMODE_SR; + + // + // Enable receive in the MAC configuration register. + // + HWREG(ui32Base + EMAC_O_CFG) |= EMAC_CFG_RE; +} + +//***************************************************************************** +// +//! Disables the Ethernet controller receiver. +//! +//! \param ui32Base is the base address of the controller. +//! +//! When terminating operations on the Ethernet interface, this function should +//! be called. This function disables the receiver. +//! +//! \return None. +// +//***************************************************************************** +void +EMACRxDisable(uint32_t ui32Base) +{ + // + // Disable reception in the MAC configuration register. + // + HWREG(ui32Base + EMAC_O_CFG) &= ~EMAC_CFG_RE; + + // + // Disable the MAC receive path. + // + HWREG(ui32Base + EMAC_O_DMAOPMODE) &= ~EMAC_DMAOPMODE_SR; +} + +//***************************************************************************** +// +//! Registers an interrupt handler for an Ethernet interrupt. +//! +//! \param ui32Base is the base address of the controller. +//! \param pfnHandler is a pointer to the function to be called when the +//! enabled Ethernet interrupts occur. +//! +//! This function sets the handler to be called when the Ethernet interrupt +//! occurs. This function enables the global interrupt in the interrupt +//! controller; specific Ethernet interrupts must be enabled via +//! EMACIntEnable(). It is the interrupt handler's responsibility to clear +//! the interrupt source. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +EMACIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(pfnHandler != 0); + + // + // Register the interrupt handler. + // + IntRegister(INT_EMAC0_TM4C129, pfnHandler); + + // + // Enable the Ethernet interrupt. + // + IntEnable(INT_EMAC0_TM4C129); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for an Ethernet interrupt. +//! +//! \param ui32Base is the base address of the controller. +//! +//! This function unregisters the interrupt handler. This function disables +//! the global interrupt in the interrupt controller so that the interrupt +//! handler is no longer called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +EMACIntUnregister(uint32_t ui32Base) +{ + // + // Disable the interrupt. + // + IntDisable(INT_EMAC0_TM4C129); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_EMAC0_TM4C129); +} + +//***************************************************************************** +// +//! Enables individual Ethernet MAC interrupt sources. +//! +//! \param ui32Base is the base address of the Ethernet MAC. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated Ethernet MAC interrupt sources. Only +//! the sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ui32IntFlags parameter is the logical OR of any of the following: +//! +//! - \b EMAC_INT_PHY indicates that the PHY has signaled a change of state. +//! Software must read and write the appropriate PHY registers to enable and +//! disable particular notifications. +//! - \b EMAC_INT_EARLY_RECEIVE indicates that the DMA engine has filled the +//! first data buffer of a packet. +//! - \b EMAC_INT_BUS_ERROR indicates that a fatal bus error has occurred and +//! that the DMA engine has been disabled. +//! - \b EMAC_INT_EARLY_TRANSMIT indicates that a frame to be transmitted has +//! been fully written from memory into the MAC transmit FIFO. +//! - \b EMAC_INT_RX_WATCHDOG indicates that a frame with length greater than +//! 2048 bytes (of 10240 bytes in Jumbo Frame mode) was received. +//! - \b EMAC_INT_RX_STOPPED indicates that the receive process has entered +//! the stopped state. +//! - \b EMAC_INT_RX_NO_BUFFER indicates that the host owns the next buffer +//! in the DMA's receive descriptor list and the DMA cannot, therefore, acquire +//! a buffer. The receive process is suspended and can be resumed by changing +//! the descriptor ownership and calling EMACRxDMAPollDemand(). +//! - \b EMAC_INT_RECEIVE indicates that reception of a frame has completed +//! and all requested status has been written to the appropriate DMA receive +//! descriptor. +//! - \b EMAC_INT_TX_UNDERFLOW indicates that the transmitter experienced an +//! underflow during transmission. The transmit process is suspended. +//! - \b EMAC_INT_RX_OVERFLOW indicates that an overflow was experienced +//! during reception. +//! - \b EMAC_INT_TX_JABBER indicates that the transmit jabber timer expired. +//! This condition occurs when the frame size exceeds 2048 bytes (or 10240 +//! bytes in Jumbo Frame mode) and causes the transmit process to abort and +//! enter the Stopped state. +//! - \b EMAC_INT_TX_NO_BUFFER indicates that the host owns the next buffer +//! in the DMA's transmit descriptor list and that the DMA cannot, therefore, +//! acquire a buffer. Transmission is suspended and can be resumed by changing +//! the descriptor ownership and calling EMACTxDMAPollDemand(). +//! - \b EMAC_INT_TX_STOPPED indicates that the transmit process has stopped. +//! - \b EMAC_INT_TRANSMIT indicates that transmission of a frame has +//! completed and that all requested status has been updated in the descriptor. +//! +//! Summary interrupt bits \b EMAC_INT_NORMAL_INT and +//! \b EMAC_INT_ABNORMAL_INT are enabled automatically by the driver if any +//! of their constituent sources are enabled. Applications do not need to +//! explicitly enable these bits. +//! +//! \note Timestamp-related interrupts from the IEEE 1588 module must be +//! enabled independently by using a call to EMACTimestampTargetIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +EMACIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Parameter sanity check. + // + ASSERT((ui32IntFlags & ~EMAC_MASKABLE_INTS) == 0); + + // + // Enable the normal interrupt if any of its individual sources are + // enabled. + // + if(ui32IntFlags & EMAC_NORMAL_INTS) + { + ui32IntFlags |= EMAC_INT_NORMAL_INT; + } + + // + // Similarly, enable the abnormal interrupt if any of its individual + // sources are enabled. + // + if(ui32IntFlags & EMAC_ABNORMAL_INTS) + { + ui32IntFlags |= EMAC_INT_ABNORMAL_INT; + } + + // + // Set the MAC DMA interrupt mask appropriately if any of the sources + // we've been asked to enable are found in that register. + // + if(ui32IntFlags & ~EMAC_INT_PHY) + { + HWREG(ui32Base + EMAC_O_DMAIM) |= ui32IntFlags & ~EMAC_INT_PHY; + } + + // + // Enable the PHY interrupt if we've been asked to do this. + // + if(ui32IntFlags & EMAC_INT_PHY) + { + HWREG(ui32Base + EMAC_O_EPHYIM) |= EMAC_EPHYIM_INT; + } +} + +//***************************************************************************** +// +//! Disables individual Ethernet MAC interrupt sources. +//! +//! \param ui32Base is the base address of the Ethernet MAC. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. +//! +//! This function disables the indicated Ethernet MAC interrupt sources. +//! +//! The \e ui32IntFlags parameter is the logical OR of any of the following: +//! +//! - \b EMAC_INT_PHY indicates that the PHY has signaled a change of state. +//! Software must read and write the appropriate PHY registers to enable and +//! disable particular notifications. +//! - \b EMAC_INT_EARLY_RECEIVE indicates that the DMA engine has filled the +//! first data buffer of a packet. +//! - \b EMAC_INT_BUS_ERROR indicates that a fatal bus error has occurred and +//! that the DMA engine has been disabled. +//! - \b EMAC_INT_EARLY_TRANSMIT indicates that a frame to be transmitted has +//! been fully written from memory into the MAC transmit FIFO. +//! - \b EMAC_INT_RX_WATCHDOG indicates that a frame with length greater than +//! 2048 bytes (of 10240 bytes in Jumbo Frame mode) was received. +//! - \b EMAC_INT_RX_STOPPED indicates that the receive process has entered +//! the stopped state. +//! - \b EMAC_INT_RX_NO_BUFFER indicates that the host owns the next buffer +//! in the DMA's receive descriptor list and the DMA cannot, therefore, acquire +//! a buffer. The receive process is suspended and can be resumed by changing +//! the descriptor ownership and calling EMACRxDMAPollDemand(). +//! - \b EMAC_INT_RECEIVE indicates that reception of a frame has completed +//! and all requested status has been written to the appropriate DMA receive +//! descriptor. +//! - \b EMAC_INT_TX_UNDERFLOW indicates that the transmitter experienced an +//! underflow during transmission. The transmit process is suspended. +//! - \b EMAC_INT_RX_OVERFLOW indicates that an overflow was experienced +//! during reception. +//! - \b EMAC_INT_TX_JABBER indicates that the transmit jabber timer expired. +//! This condition occurs when the frame size exceeds 2048 bytes (or 10240 +//! bytes in Jumbo Frame mode) and causes the transmit process to abort and +//! enter the Stopped state. +//! - \b EMAC_INT_TX_NO_BUFFER indicates that the host owns the next buffer +//! in the DMA's transmit descriptor list and that the DMA cannot, therefore, +//! acquire a buffer. Transmission is suspended and can be resumed by changing +//! the descriptor ownership and calling EMACTxDMAPollDemand(). +//! - \b EMAC_INT_TX_STOPPED indicates that the transmit process has stopped. +//! - \b EMAC_INT_TRANSMIT indicates that transmission of a frame has +//! completed and that all requested status has been updated in the descriptor. +//! - \b EMAC_INT_TIMESTAMP indicates that an interrupt from the timestamp +//! module has occurred. This precise source of the interrupt can be +//! determined by calling EMACTimestampIntStatus(), which also clears this +//! bit. +//! +//! Summary interrupt bits \b EMAC_INT_NORMAL_INT and +//! \b EMAC_INT_ABNORMAL_INT are disabled automatically by the driver if none +//! of their constituent sources are enabled. Applications do not need to +//! explicitly disable these bits. +//! +//! \note Timestamp-related interrupts from the IEEE 1588 module must be +//! disabled independently by using a call to EMACTimestampTargetIntDisable(). +//! +//! \return None. +// +//***************************************************************************** +void +EMACIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + uint32_t ui32Mask; + + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + ASSERT((ui32IntFlags & ~EMAC_MASKABLE_INTS) == 0); + + // + // Get the current interrupt mask. + // + ui32Mask = HWREG(ui32Base + EMAC_O_DMAIM); + + // + // Clear the requested bits. + // + ui32Mask &= ~(ui32IntFlags & ~EMAC_INT_PHY); + + // + // If none of the normal interrupt sources are enabled, disable the + // normal interrupt. + // + if(!(ui32Mask & EMAC_NORMAL_INTS)) + { + ui32Mask &= ~EMAC_INT_NORMAL_INT; + } + + // + // Similarly, if none of the abnormal interrupt sources are enabled, + // disable the abnormal interrupt. + // + if(!(ui32Mask & EMAC_ABNORMAL_INTS)) + { + ui32Mask &= ~EMAC_INT_ABNORMAL_INT; + } + + // + // Write the new mask back to the hardware. + // + HWREG(ui32Base + EMAC_O_DMAIM) = ui32Mask; + + // + // Disable the PHY interrupt if we've been asked to do this. + // + if(ui32IntFlags & EMAC_INT_PHY) + { + HWREG(ui32Base + EMAC_O_EPHYIM) &= ~EMAC_EPHYIM_INT; + } +} + +//***************************************************************************** +// +//! Gets the current Ethernet MAC interrupt status. +//! +//! \param ui32Base is the base address of the Ethernet MAC. +//! \param bMasked is \b true to return the masked interrupt status or \b false +//! to return the unmasked status. +//! +//! This function returns the interrupt status for the Ethernet MAC. Either +//! the raw interrupt status or the status of interrupts that are allowed +//! to reflect to the processor can be returned. +//! +//! \return Returns the current interrupt status as the logical OR of any of +//! the following: +//! +//! - \b EMAC_INT_PHY indicates that the PHY interrupt has occurred. +//! Software must read the relevant PHY interrupt status register to determine +//! the cause. +//! - \b EMAC_INT_EARLY_RECEIVE indicates that the DMA engine has filled the +//! first data buffer of a packet. +//! - \b EMAC_INT_BUS_ERROR indicates that a fatal bus error has occurred and +//! that the DMA engine has been disabled. The cause of the error can be +//! determined by calling EMACDMAStateGet(). +//! - \b EMAC_INT_EARLY_TRANSMIT indicates that a frame to be transmitted has +//! been fully written from memory into the MAC transmit FIFO. +//! - \b EMAC_INT_RX_WATCHDOG indicates that a frame with length greater than +//! 2048 bytes (of 10240 bytes in Jumbo Frame mode) was received. +//! - \b EMAC_INT_RX_STOPPED indicates that the receive process has entered +//! the stopped state. +//! - \b EMAC_INT_RX_NO_BUFFER indicates that the host owns the next buffer +//! in the DMA's receive descriptor list and the DMA cannot, therefore, acquire +//! a buffer. The receive process is suspended and can be resumed by changing +//! the descriptor ownership and calling EMACRxDMAPollDemand(). +//! - \b EMAC_INT_RECEIVE indicates that reception of a frame has completed +//! and all requested status has been written to the appropriate DMA receive +//! descriptor. +//! - \b EMAC_INT_TX_UNDERFLOW indicates that the transmitter experienced an +//! underflow during transmission. The transmit process is suspended. +//! - \b EMAC_INT_RX_OVERFLOW indicates that an overflow was experienced +//! during reception. +//! - \b EMAC_INT_TX_JABBER indicates that the transmit jabber timer expired. +//! This condition occurs when the frame size exceeds 2048 bytes (or 10240 +//! bytes in Jumbo Frame mode) and causes the transmit process to abort and +//! enter the Stopped state. +//! - \b EMAC_INT_TX_NO_BUFFER indicates that the host owns the next buffer +//! in the DMA's transmit descriptor list and that the DMA cannot, therefore, +//! acquire a buffer. Transmission is suspended and can be resumed by changing +//! the descriptor ownership and calling EMACTxDMAPollDemand(). +//! - \b EMAC_INT_TX_STOPPED indicates that the transmit process has stopped. +//! - \b EMAC_INT_TRANSMIT indicates that transmission of a frame has +//! completed and that all requested status has been updated in the descriptor. +//! - \b EMAC_INT_NORMAL_INT is a summary interrupt comprising the logical +//! OR of the masked state of \b EMAC_INT_TRANSMIT, \b EMAC_INT_RECEIVE, +//! \b EMAC_INT_TX_NO_BUFFER and \b EMAC_INT_EARLY_RECEIVE. +//! - \b EMAC_INT_ABNORMAL_INT is a summary interrupt comprising the logical +//! OR of the masked state of \b EMAC_INT_TX_STOPPED, \b EMAC_INT_TX_JABBER, +//! \b EMAC_INT_RX_OVERFLOW, \b EMAC_INT_TX_UNDERFLOW, +//! \b EMAC_INT_RX_NO_BUFFER, \b EMAC_INT_RX_STOPPED, +//! \b EMAC_INT_RX_WATCHDOG, \b EMAC_INT_EARLY_TRANSMIT and +//! \b EMAC_INT_BUS_ERROR. +// +//***************************************************************************** +uint32_t +EMACIntStatus(uint32_t ui32Base, bool bMasked) +{ + uint32_t ui32Val, ui32PHYStat; + + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + + // + // Get the unmasked interrupt status and clear any unwanted status fields. + // + ui32Val = HWREG(ui32Base + EMAC_O_DMARIS); + ui32Val &= ~(EMAC_DMARIS_AE_M | EMAC_DMARIS_TS_M | EMAC_DMARIS_RS_M); + + // + // This peripheral doesn't have a masked interrupt status register + // so perform the masking manually. Note that only the bottom 16 bits + // of the register can be masked so make sure we take this into account. + // + if(bMasked) + { + ui32Val &= (EMAC_NON_MASKED_INTS | HWREG(ui32Base + EMAC_O_DMAIM)); + } + + // + // Read the PHY interrupt status. + // + if(bMasked) + { + ui32PHYStat = HWREG(ui32Base + EMAC_O_EPHYMISC); + } + else + { + ui32PHYStat = HWREG(ui32Base + EMAC_O_EPHYRIS); + } + + // + // If the PHY interrupt is reported, add the appropriate flag to the + // return value. + // + if(ui32PHYStat & EMAC_EPHYMISC_INT) + { + ui32Val |= EMAC_INT_PHY; + } + + return(ui32Val); +} + +//***************************************************************************** +// +//! Clears individual Ethernet MAC interrupt sources. +//! +//! \param ui32Base is the base address of the Ethernet MAC. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be cleared. +//! +//! This function disables the indicated Ethernet MAC interrupt sources. +//! +//! The \e ui32IntFlags parameter is the logical OR of any of the following: +//! +//! - \b EMAC_INT_PHY indicates that the PHY has signaled a change of state. +//! Software must read and write the appropriate PHY registers to enable, +//! disable and clear particular notifications. +//! - \b EMAC_INT_EARLY_RECEIVE indicates that the DMA engine has filled the +//! first data buffer of a packet. +//! - \b EMAC_INT_BUS_ERROR indicates that a fatal bus error has occurred and +//! that the DMA engine has been disabled. +//! - \b EMAC_INT_EARLY_TRANSMIT indicates that a frame to be transmitted has +//! been fully written from memory into the MAC transmit FIFO. +//! - \b EMAC_INT_RX_WATCHDOG indicates that a frame with length greater than +//! 2048 bytes (of 10240 bytes in Jumbo Frame mode) was received. +//! - \b EMAC_INT_RX_STOPPED indicates that the receive process has entered +//! the stopped state. +//! - \b EMAC_INT_RX_NO_BUFFER indicates that the host owns the next buffer +//! in the DMA's receive descriptor list and the DMA cannot, therefore, acquire +//! a buffer. The receive process is suspended and can be resumed by changing +//! the descriptor ownership and calling EMACRxDMAPollDemand(). +//! - \b EMAC_INT_RECEIVE indicates that reception of a frame has completed +//! and all requested status has been written to the appropriate DMA receive +//! descriptor. +//! - \b EMAC_INT_TX_UNDERFLOW indicates that the transmitter experienced an +//! underflow during transmission. The transmit process is suspended. +//! - \b EMAC_INT_RX_OVERFLOW indicates that an overflow was experienced +//! during reception. +//! - \b EMAC_INT_TX_JABBER indicates that the transmit jabber timer expired. +//! This condition occurs when the frame size exceeds 2048 bytes (or 10240 +//! bytes in Jumbo Frame mode) and causes the transmit process to abort and +//! enter the Stopped state. +//! - \b EMAC_INT_TX_NO_BUFFER indicates that the host owns the next buffer +//! in the DMA's transmit descriptor list and that the DMA cannot, therefore, +//! acquire a buffer. Transmission is suspended and can be resumed by changing +//! the descriptor ownership and calling EMACTxDMAPollDemand(). +//! - \b EMAC_INT_TX_STOPPED indicates that the transmit process has stopped. +//! - \b EMAC_INT_TRANSMIT indicates that transmission of a frame has +//! completed and that all requested status has been updated in the descriptor. +//! +//! Summary interrupt bits \b EMAC_INT_NORMAL_INT and +//! \b EMAC_INT_ABNORMAL_INT are cleared automatically by the driver if any +//! of their constituent sources are cleared. Applications do not need to +//! explicitly clear these bits. +//! +//! \return None. +// +//***************************************************************************** +void +EMACIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + + // + // Mask in the normal interrupt if one of the sources it relates to is + // specified. + // + if(ui32IntFlags & EMAC_NORMAL_INTS) + { + ui32IntFlags |= EMAC_INT_NORMAL_INT; + } + + // + // Similarly, mask in the abnormal interrupt if one of the sources it + // relates to is specified. + // + if(ui32IntFlags & EMAC_ABNORMAL_INTS) + { + ui32IntFlags |= EMAC_INT_ABNORMAL_INT; + } + + // + // Clear the maskable interrupt sources. We write exactly the value passed + // (with the summary sources added if necessary) but remember that only + // the bottom 17 bits of the register are actually clearable. Only do + // this if some bits are actually set that refer to the DMA interrupt + // sources. + // + if(ui32IntFlags & ~EMAC_INT_PHY) + { + HWREG(ui32Base + EMAC_O_DMARIS) = (ui32IntFlags & ~EMAC_INT_PHY); + } + + // + // Clear the PHY interrupt if we've been asked to do this. + // + if(ui32IntFlags & EMAC_INT_PHY) + { + HWREG(ui32Base + EMAC_O_EPHYMISC) |= EMAC_EPHYMISC_INT; + } +} + +//***************************************************************************** +// +//! Writes to the PHY register. +//! +//! \param ui32Base is the base address of the controller. +//! \param ui8PhyAddr is the physical address of the PHY to access. +//! \param ui8RegAddr is the address of the PHY register to be accessed. +//! \param ui16Data is the data to be written to the PHY register. +//! +//! This function writes the \e ui16Data value to the PHY register specified by +//! \e ui8RegAddr. +//! +//! \return None. +// +//***************************************************************************** +void +EMACPHYWrite(uint32_t ui32Base, uint8_t ui8PhyAddr, uint8_t ui8RegAddr, + uint16_t ui16Data) +{ + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + + // + // Parameter sanity check. + // + ASSERT(ui8PhyAddr < 32); + + // + // Make sure the MII is idle. + // + while(HWREG(ui32Base + EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB) + { + } + + // + // Write the value provided. + // + HWREG(ui32Base + EMAC_O_MIIDATA) = ui16Data; + + // + // Tell the MAC to write the given PHY register. + // + HWREG(ui32Base + EMAC_O_MIIADDR) = + ((HWREG(ui32Base + EMAC_O_MIIADDR) & + EMAC_MIIADDR_CR_M) | (ui8RegAddr << EMAC_MIIADDR_MII_S) | + (ui8PhyAddr << EMAC_MIIADDR_PLA_S) | EMAC_MIIADDR_MIIW | + EMAC_MIIADDR_MIIB); + + // + // Wait for the write to complete. + // + while(HWREG(ui32Base + EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB) + { + } +} + +//***************************************************************************** +// +//! Reads from a PHY register. +//! +//! \param ui32Base is the base address of the controller. +//! \param ui8PhyAddr is the physical address of the PHY to access. +//! \param ui8RegAddr is the address of the PHY register to be accessed. +//! +//! This function returns the contents of the PHY register specified by +//! \e ui8RegAddr. +//! +//! \return Returns the 16-bit value read from the PHY. +// +//***************************************************************************** +uint16_t +EMACPHYRead(uint32_t ui32Base, uint8_t ui8PhyAddr, uint8_t ui8RegAddr) +{ + // + // Parameter sanity check. + // + ASSERT(ui8PhyAddr < 32); + ASSERT(ui32Base == EMAC0_BASE); + + // + // Make sure the MII is idle. + // + while(HWREG(ui32Base + EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB) + { + } + + // + // Tell the MAC to read the given PHY register. + // + HWREG(ui32Base + EMAC_O_MIIADDR) = + ((HWREG(ui32Base + EMAC_O_MIIADDR) & EMAC_MIIADDR_CR_M) | + (ui8RegAddr << EMAC_MIIADDR_MII_S) | + (ui8PhyAddr << EMAC_MIIADDR_PLA_S) | EMAC_MIIADDR_MIIB); + + // + // Wait for the read to complete. + // + while(HWREG(ui32Base + EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB) + { + } + + // + // Return the result. + // + return(HWREG(ui32Base + EMAC_O_MIIDATA) & EMAC_MIIDATA_DATA_M); +} + +//***************************************************************************** +// +//! Reads from an extended PHY register. +//! +//! \param ui32Base is the base address of the controller. +//! \param ui8PhyAddr is the physical address of the PHY to access. +//! \param ui16RegAddr is the address of the PHY extended register to be +//! accessed. +//! +//! When using the internal PHY or when connected to an external PHY +//! supporting extended registers, this function returns the contents of the +//! extended PHY register specified by \e ui16RegAddr. +//! +//! \return Returns the 16-bit value read from the PHY. +// +//***************************************************************************** +uint16_t +EMACPHYExtendedRead(uint32_t ui32Base, uint8_t ui8PhyAddr, + uint16_t ui16RegAddr) +{ + // + // Parameter sanity check. + // + ASSERT(ui8PhyAddr < 32); + ASSERT(ui32Base == EMAC0_BASE); + + // + // Set the address of the register we're about to read. + // + EMACPHYWrite(EMAC0_BASE, ui8PhyAddr, EPHY_REGCTL, 0x001F); + EMACPHYWrite(EMAC0_BASE, ui8PhyAddr, EPHY_ADDAR, ui16RegAddr); + + // + // Read the extended register value. + // + EMACPHYWrite(EMAC0_BASE, ui8PhyAddr, EPHY_REGCTL, 0x401F); + return(EMACPHYRead(EMAC0_BASE, ui8PhyAddr, EPHY_ADDAR)); +} + +//***************************************************************************** +// +//! Writes a value to an extended PHY register. +//! +//! \param ui32Base is the base address of the controller. +//! \param ui8PhyAddr is the physical address of the PHY to access. +//! \param ui16RegAddr is the address of the PHY extended register to be +//! accessed. +//! \param ui16Value is the value to write to the register. +//! +//! When using the internal PHY or when connected to an external PHY +//! supporting extended registers, this function allows a value to be written +//! to the extended PHY register specified by \e ui16RegAddr. +//! +//! \return None. +// +//***************************************************************************** +void +EMACPHYExtendedWrite(uint32_t ui32Base, uint8_t ui8PhyAddr, + uint16_t ui16RegAddr, uint16_t ui16Value) +{ + // + // Parameter sanity check. + // + ASSERT(ui8PhyAddr < 32); + ASSERT(ui32Base == EMAC0_BASE); + + // + // Set the address of the register we're about to write. + // + EMACPHYWrite(EMAC0_BASE, ui8PhyAddr, EPHY_REGCTL, 0x001F); + EMACPHYWrite(EMAC0_BASE, ui8PhyAddr, EPHY_ADDAR, ui16RegAddr); + + // + // Write the extended register. + // + EMACPHYWrite(EMAC0_BASE, ui8PhyAddr, EPHY_REGCTL, 0x401F); + EMACPHYWrite(EMAC0_BASE, ui8PhyAddr, EPHY_ADDAR, ui16Value); +} + +//***************************************************************************** +// +//! Powers off the Ethernet PHY. +//! +//! \param ui32Base is the base address of the controller. +//! \param ui8PhyAddr is the physical address of the PHY to power down. +//! +//! This function powers off the Ethernet PHY, reducing the current +//! consumption of the device. While in the powered-off state, the Ethernet +//! controller is unable to connect to Ethernet. +//! +//! \return None. +// +//***************************************************************************** +void +EMACPHYPowerOff(uint32_t ui32Base, uint8_t ui8PhyAddr) +{ + // + // Set the PWRDN bit and clear the ANEN bit in the PHY, putting it into + // its low power mode. + // + EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_BMCR, + (EMACPHYRead(ui32Base, ui8PhyAddr, EPHY_BMCR) & + ~EPHY_BMCR_ANEN) | EPHY_BMCR_PWRDWN); +} + +//***************************************************************************** +// +//! Powers on the Ethernet PHY. +//! +//! \param ui32Base is the base address of the controller. +//! \param ui8PhyAddr is the physical address of the PHY to power up. +//! +//! This function powers on the Ethernet PHY, enabling it return to normal +//! operation. By default, the PHY is powered on, so this function is only +//! called if EMACPHYPowerOff() has previously been called. +//! +//! \return None. +// +//***************************************************************************** +void +EMACPHYPowerOn(uint32_t ui32Base, uint8_t ui8PhyAddr) +{ + // + // Clear the PWRDN bit and set the ANEGEN bit in the PHY, putting it into + // normal operating mode. + // + EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_BMCR, + (EMACPHYRead(ui32Base, ui8PhyAddr, EPHY_BMCR) & + ~EPHY_BMCR_PWRDWN) | EPHY_BMCR_ANEN); +} + +//***************************************************************************** +// +//! Configures the Ethernet MAC's IEEE 1588 timestamping options. +//! +//! \param ui32Base is the base address of the controller. +//! \param ui32Config contains flags selecting particular configuration +//! options. +//! \param ui32SubSecondInc is the number that the IEEE 1588 subsecond clock +//! should increment on each tick. +//! +//! This function is used to configure the operation of the Ethernet MAC's +//! internal timestamping clock. This clock is used to timestamp incoming +//! and outgoing packets and as an accurate system time reference when +//! IEEE 1588 Precision Time Protocol is in use. +//! +//! The \e ui32Config parameter contains a collection of flags selecting the +//! desired options. Valid flags are: +//! +//! One of the following to determine whether IEEE 1588 version 1 or version 2 +//! packet format is to be processed: +//! +//! - \b EMAC_TS_PTP_VERSION_2 +//! - \b EMAC_TS_PTP_VERSION_1 +//! +//! One of the following to determine how the IEEE 1588 clock's subsecond +//! value should be interpreted and handled: +//! +//! - \b EMAC_TS_DIGITAL_ROLLOVER causes the clock's subsecond value to roll +//! over at 0x3BA9C9FF (999999999 decimal). In this mode, it can be considered +//! as a nanosecond counter with each digit representing 1 ns. +//! - \b EMAC_TS_BINARY_ROLLOVER causes the clock's subsecond value to roll +//! over at 0x7FFFFFFF. In this mode, the subsecond value counts 0.465 ns +//! periods. +//! +//! One of the following to enable or disable MAC address filtering. When +//! enabled, PTP frames are filtered unless the destination MAC address matches +//! any of the currently programmed MAC addresses. +//! +//! - \b EMAC_TS_MAC_FILTER_ENABLE +//! - \b EMAC_TS_MAC_FILTER_DISABLE +//! +//! One of the following to determine how the clock is updated: +//! - \b EMAC_TS_UPDATE_COARSE causes the IEEE 1588 clock to advance by +//! the value supplied in the \e ui32SubSecondInc parameter on each main +//! oscillator clock cycle. +//! - \b EMAC_TS_UPDATE_FINE selects the fine update method which causes the +//! IEEE 1588 clock to advance by the the value supplied in the +//! \e ui32SubSecondInc parameter each time a carry is generated from the +//! addend accumulator register. +//! +//! One of the following to determine which IEEE 1588 messages are timestamped: +//! +//! - \b EMAC_TS_SYNC_FOLLOW_DREQ_DRESP timestamps SYNC, Follow_Up, Delay_Req +//! and Delay_Resp messages. +//! - \b EMAC_TS_SYNC_ONLY timestamps only SYNC messages. +//! - \b EMAC_TS_DELAYREQ_ONLY timestamps only Delay_Req messages. +//! - \b EMAC_TS_ALL timestamps all IEEE 1588 messages. +//! - \b EMAC_TS_SYNC_PDREQ_PDRESP timestamps only SYNC, Pdelay_Req and +//! Pdelay_Resp messages. +//! - \b EMAC_TS_DREQ_PDREQ_PDRESP timestamps only Delay_Req, Pdelay_Req and +//! Pdelay_Resp messages. +//! - \b EMAC_TS_SYNC_DELAYREQ timestamps only Delay_Req messages. +//! - \b EMAC_TS_PDREQ_PDRESP timestamps only Pdelay_Req and Pdelay_Resp +//! messages. +//! +//! Optional, additional flags are: +//! +//! - \b EMAC_TS_PROCESS_IPV4_UDP processes PTP packets encapsulated in UDP +//! over IPv4 packets. If absent, the MAC ignores these frames. +//! - \b EMAC_TS_PROCESS_IPV6_UDP processes PTP packets encapsulated in UDP +//! over IPv6 packets. If absent, the MAC ignores these frames. +//! - \b EMAC_TS_PROCESS_ETHERNET processes PTP packets encapsulated directly +//! in Ethernet frames. If absent, the MAC ignores these frames. +//! - \b EMAC_TS_ALL_RX_FRAMES enables timestamping for all frames received +//! by the MAC, regardless of type. +//! +//! The \e ui32SubSecondInc controls the rate at which the timestamp clock's +//! subsecond count increments. Its meaning depends on which of \b +//! EMAC_TS_DIGITAL_ROLLOVER or \b EMAC_TS_BINARY_ROLLOVER and +//! \b EMAC_TS_UPDATE_FINE or \b EMAC_TS_UPDATE_COARSE were included +//! in \e ui32Config. +//! +//! The timestamp second counter is incremented each time the subsecond counter +//! rolls over. In digital rollover mode, the subsecond counter acts as a +//! simple 31-bit counter, rolling over to 0 after reaching 0x7FFFFFFF. In +//! this case, each lsb of the subsecond counter represents 0.465 ns (assuming +//! the definition of 1 second resolution for the seconds counter). When +//! binary rollover mode is selected, the subsecond counter acts as a +//! nanosecond counter and rolls over to 0 after reaching 999,999,999 making +//! each lsb represent 1 nanosecond. +//! +//! In coarse update mode, the timestamp subsecond counter is incremented by +//! \e ui32SubSecondInc on each main oscillator clock tick. Setting +//! \e ui32SubSecondInc to the main oscillator clock period in either 1 ns or +//! 0.465 ns units ensures that the time stamp, read as seconds and +//! subseconds, increments at the same rate as the main oscillator clock. For +//! example, if the main oscillator is 25 MHz, \e ui32SubSecondInc is set to 40 +//! if digital rollover mode is selected or (40 / 0.465) = 86 in binary +//! rollover mode. +//! +//! In fine update mode, the subsecond increment value must be set according +//! to the desired accuracy of the recovered IEEE 1588 clock which must be +//! lower than the system clock rate. Fine update mode is typically used when +//! synchronizing the local clock to the IEEE 1588 master clock. The subsecond +//! counter is incremented by \e ui32SubSecondInc counts each time a 32-bit +//! accumulator register generates a carry. The accumulator register is +//! incremented by the addend value on each main oscillator tick and this +//! addend value is modified to allow fine control over the rate of change of +//! the timestamp counter. The addend value is calculated using the ratio of +//! the main oscillator clock rate and the desired IEEE 1588 clock rate and the +//! \e ui32SubSecondInc value is set to correspond to the desired IEEE 1588 +//! clock rate. As an example, using digital rollover mode and a 25-MHz +//! main oscillator clock with a desired IEEE 1588 clock accuracy of 12.5 MHz, +//! we would set \e ui32SubSecondInc to the 12.5-MHz clock period of 80 ns and +//! set the initial addend value to 0x80000000 to generate a carry on every +//! second system clock. +//! +//! \sa EMACTimestampAddendSet() +//! +//! \return None. +// +//***************************************************************************** +void +EMACTimestampConfigSet(uint32_t ui32Base, uint32_t ui32Config, + uint32_t ui32SubSecondInc) +{ + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + + // + // Ensure that the PTP module clock is enabled. + // + HWREG(ui32Base + EMAC_O_CC) |= EMAC_CC_PTPCEN; + + // + // Write the subsecond increment value. + // + HWREG(ui32Base + EMAC_O_SUBSECINC) = ((ui32SubSecondInc << + EMAC_SUBSECINC_SSINC_S) & + EMAC_SUBSECINC_SSINC_M); + + // + // Set the timestamp configuration. + // + HWREG(ui32Base + EMAC_O_TIMSTCTRL) = ui32Config; +} + +//***************************************************************************** +// +//! Returns the current IEEE 1588 timestamping configuration. +//! +//! \param ui32Base is the base address of the controller. +//! \param pui32SubSecondInc points to storage that is written with the +//! current subsecond increment value for the IEEE 1588 clock. +//! +//! This function may be used to retreive the current MAC timestamping +//! configuration. +//! +//! \sa EMACTimestampConfigSet() +//! +//! \return Returns the current timestamping configuration as a logical OR of +//! the following flags: +//! +//! - \b EMAC_TS_PTP_VERSION_2 indicates that the MAC is processing PTP +//! version 2 messages. If this flag is absent, PTP version 1 messages are +//! expected. +//! - \b EMAC_TS_DIGITAL_ROLLOVER causes the clock's subsecond value to roll +//! over at 0x3BA9C9FF (999999999 decimal). In this mode, it can be considered +//! as a nanosecond counter with each digit representing 1 ns. If this flag is +//! absent, the subsecond value rolls over at 0x7FFFFFFF, effectively counting +//! increments of 0.465 ns. +//! - \b EMAC_TS_MAC_FILTER_ENABLE indicates that incoming PTP messages +//! are filtered using any of the configured MAC addresses. Messages with a +//! destination address programmed into the MAC address filter are passed, +//! others are discarded. If this flag is absent, the MAC address is ignored. +//! - \b EMAC_TS_UPDATE_FINE implements the fine update method that causes the +//! IEEE 1588 clock to advance by the the value returned in the +//! \e *pui32SubSecondInc parameter each time a carry is generated from the +//! addend accumulator register. If this flag is absent, the coarse update +//! method is in use and the clock is advanced by the \e *pui32SubSecondInc +//! value on each system clock tick. +//! - \b EMAC_TS_SYNC_ONLY indicates that timestamps are only generated for +//! SYNC messages. +//! - \b EMAC_TS_DELAYREQ_ONLY indicates that timestamps are only generated +//! for Delay_Req messages. +//! - \b EMAC_TS_ALL indicates that timestamps are generated for all +//! IEEE 1588 messages. +//! - \b EMAC_TS_SYNC_PDREQ_PDRESP timestamps only SYNC, Pdelay_Req and +//! Pdelay_Resp messages. +//! - \b EMAC_TS_DREQ_PDREQ_PDRESP indicates that timestamps are only +//! generated for Delay_Req, Pdelay_Req and Pdelay_Resp messages. +//! - \b EMAC_TS_SYNC_DELAYREQ indicates that timestamps are only generated +//! for Delay_Req messages. +//! - \b EMAC_TS_PDREQ_PDRESP indicates that timestamps are only generated +//! for Pdelay_Req and Pdelay_Resp messages. +//! - \b EMAC_TS_PROCESS_IPV4_UDP indicates that PTP packets encapsulated in +//! UDP over IPv4 packets are being processed. If absent, the MAC ignores +//! these frames. +//! - \b EMAC_TS_PROCESS_IPV6_UDP indicates that PTP packets encapsulated in +//! UDP over IPv6 packets are being processed. If absent, the MAC ignores +//! these frames. +//! - \b EMAC_TS_PROCESS_ETHERNET indicates that PTP packets encapsulated +//! directly in Ethernet frames are being processd. If absent, the MAC ignores +//! these frames. +//! - \b EMAC_TS_ALL_RX_FRAMES indicates that timestamping is enabled for all +//! frames received by the MAC, regardless of type. +//! +//! If \b EMAC_TS_ALL_RX_FRAMES and none of the options specifying subsets +//! of PTP packets to timestamp are set, the MAC is configured to timestamp +//! SYNC, Follow_Up, Delay_Req and Delay_Resp messages only. +// +//***************************************************************************** +uint32_t +EMACTimestampConfigGet(uint32_t ui32Base, uint32_t *pui32SubSecondInc) +{ + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + ASSERT(pui32SubSecondInc); + + // + // Read the current subsecond increment value. + // + *pui32SubSecondInc = (HWREG(ui32Base + EMAC_O_SUBSECINC) & + EMAC_SUBSECINC_SSINC_M) >> EMAC_SUBSECINC_SSINC_S; + + // + // Return the current timestamp configuration. + // + return(HWREG(ui32Base + EMAC_O_TIMSTCTRL)); +} + +//***************************************************************************** +// +//! Enables packet timestamping and starts the system clock running. +//! +//! \param ui32Base is the base address of the controller. +//! +//! This function is used to enable the system clock used to timestamp +//! Ethernet frames and to enable that timestamping. +//! +//! \return None. +// +//***************************************************************************** +void +EMACTimestampEnable(uint32_t ui32Base) +{ + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + + // + // Enable IEEE 1588 timestamping. + // + HWREG(ui32Base + EMAC_O_TIMSTCTRL) |= EMAC_TIMSTCTRL_TSEN; + + // + // If necessary, initialize the timestamping system. This bit self-clears + // once the system time is loaded. Only do this if initialization is not + // currently ongoing. + // + if(!(HWREG(ui32Base + EMAC_O_TIMSTCTRL) & EMAC_TIMSTCTRL_TSINIT)) + { + HWREG(ui32Base + EMAC_O_TIMSTCTRL) |= EMAC_TIMSTCTRL_TSINIT; + } +} + +//***************************************************************************** +// +//! Disables packet timestamping and stops the system clock. +//! +//! \param ui32Base is the base address of the controller. +//! +//! This function is used to stop the system clock used to timestamp +//! Ethernet frames and to disable timestamping. +//! +//! \return None. +// +//***************************************************************************** +void +EMACTimestampDisable(uint32_t ui32Base) +{ + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + + // + // Disable IEEE 1588 timestamping. + // + HWREG(ui32Base + EMAC_O_TIMSTCTRL) &= ~EMAC_TIMSTCTRL_TSEN; +} + +//***************************************************************************** +// +//! Sets the current system time. +//! +//! \param ui32Base is the base address of the controller. +//! \param ui32Seconds is the seconds value of the new system clock setting. +//! \param ui32SubSeconds is the subseconds value of the new system clock +//! setting. +//! +//! This function may be used to set the current system time. The system +//! clock is set to the value passed in the \e ui32Seconds and +//! \e ui32SubSeconds parameters. +//! +//! The meaning of \e ui32SubSeconds depends on the current system time +//! configuration. If EMACTimestampConfigSet() was previously called with +//! the \e EMAC_TS_DIGITAL_ROLLOVER configuration option, each bit in the +//! \e ui32SubSeconds value represents 1 ns. If \e EMAC_TS_BINARY_ROLLOVER was +//! specified instead, a \e ui32SubSeconds bit represents 0.46 ns. +//! +//! \return None. +// +//***************************************************************************** +void +EMACTimestampSysTimeSet(uint32_t ui32Base, uint32_t ui32Seconds, + uint32_t ui32SubSeconds) +{ + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + + // + // Write the new time to the system time update registers. + // + HWREG(ui32Base + EMAC_O_TIMSECU) = ui32Seconds; + HWREG(ui32Base + EMAC_O_TIMNANOU) = ui32SubSeconds; + + // + // Wait for any previous update to complete. + // + while(HWREG(ui32Base + EMAC_O_TIMSTCTRL) & EMAC_TIMSTCTRL_TSINIT) + { + // + // Spin for a while. + // + } + + // + // Force the system clock to reset. + // + HWREG(ui32Base + EMAC_O_TIMSTCTRL) |= EMAC_TIMSTCTRL_TSINIT; +} + +//***************************************************************************** +// +//! Gets the current system time. +//! +//! \param ui32Base is the base address of the controller. +//! \param pui32Seconds points to storage for the current seconds value. +//! \param pui32SubSeconds points to storage for the current subseconds value. +//! +//! This function may be used to get the current system time. +//! +//! The meaning of \e ui32SubSeconds depends on the current system time +//! configuration. If EMACTimestampConfigSet() was previously called with +//! the \e EMAC_TS_DIGITAL_ROLLOVER configuration option, each bit in the +//! \e ui32SubSeconds value represents 1 ns. If \e EMAC_TS_BINARY_ROLLOVER was +//! specified instead, a \e ui32SubSeconds bit represents 0.46 ns. +//! +//! \return None. +// +//***************************************************************************** +void +EMACTimestampSysTimeGet(uint32_t ui32Base, uint32_t *pui32Seconds, + uint32_t *pui32SubSeconds) +{ + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + ASSERT(pui32Seconds); + ASSERT(pui32SubSeconds); + + // + // Read the two-part system time from the seconds and nanoseconds + // registers. We do this in a way that should guard against us reading + // the registers across a nanosecond wrap. + // + do + { + *pui32Seconds = HWREG(ui32Base + EMAC_O_TIMSEC); + *pui32SubSeconds = HWREG(ui32Base + EMAC_O_TIMNANO); + } + while(*pui32SubSeconds > HWREG(ui32Base + EMAC_O_TIMNANO)); +} + +//***************************************************************************** +// +//! Adjusts the current system time upwards or downwards by a given amount. +//! +//! \param ui32Base is the base address of the controller. +//! \param ui32Seconds is the seconds value of the time update to apply. +//! \param ui32SubSeconds is the subseconds value of the time update to apply. +//! \param bInc defines the direction of the update. +//! +//! This function may be used to adjust the current system time either upwards +//! or downwards by a given amount. The size of the adjustment is given by +//! the \e ui32Seconds and \e ui32SubSeconds parameter and the direction +//! by the \e bInc parameter. When \e bInc is \e true, the system time is +//! advanced by the interval given. When it is \e false, the time is retarded +//! by the interval. +//! +//! The meaning of \e ui32SubSeconds depends on the current system time +//! configuration. If EMACTimestampConfigSet() was previously called with +//! the \e EMAC_TS_DIGITAL_ROLLOVER configuration option, each bit in the +//! subsecond value represents 1 ns. If \e EMAC_TS_BINARY_ROLLOVER was +//! specified instead, a subsecond bit represents 0.46 ns. +//! +//! \return None. +// +//***************************************************************************** +void +EMACTimestampSysTimeUpdate(uint32_t ui32Base, uint32_t ui32Seconds, + uint32_t ui32SubSeconds, bool bInc) +{ + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + + // + // Write the new time to the system time update registers. + // + HWREG(ui32Base + EMAC_O_TIMSECU) = ui32Seconds; + HWREG(ui32Base + EMAC_O_TIMNANOU) = ui32SubSeconds | + (bInc ? 0 : EMAC_TIMNANOU_ADDSUB); + + // + // Wait for any previous update to complete. + // + while(HWREG(ui32Base + EMAC_O_TIMSTCTRL) & EMAC_TIMSTCTRL_TSUPDT) + { + // + // Spin for a while. + // + } + + // + // Force the system clock to update by the value provided. + // + HWREG(ui32Base + EMAC_O_TIMSTCTRL) |= EMAC_TIMSTCTRL_TSUPDT; +} + +//***************************************************************************** +// +//! Adjusts the system time update rate when using the fine correction method. +//! +//! \param ui32Base is the base address of the controller. +//! \param ui32Increment is the number to add to the accumulator register on +//! each tick of the 25-MHz main oscillator. +//! +//! This function is used to control the rate of update of the system time +//! when in fine update mode. Fine correction mode is selected if +//! \e EMAC_TS_UPDATE_FINE is supplied in the \e ui32Config parameter passed +//! to a previous call to EMACTimestampConfigSet(). Fine update mode is +//! typically used when synchronizing the local clock to the IEEE 1588 master +//! clock. The subsecond counter is incremented by the number passed to +//! EMACTimestampConfigSet() in the \e ui32SubSecondInc parameter each time a +//! 32-bit accumulator register generates a carry. The accumulator register is +//! incremented by the "addend" value on each main oscillator tick, and this +//! addend value is modified to allow fine control over the rate of change of +//! the timestamp counter. The addend value is calculated using the ratio of +//! the main oscillator clock rate and the desired IEEE 1588 clock rate and the +//! \e ui32SubSecondInc value is set to correspond to the desired IEEE 1588 +//! clock rate. +//! +//! As an example, using digital rollover mode and a 25-MHz main oscillator +//! clock with a desired IEEE 1588 clock accuracy of 12.5 MHz, and having made +//! a previous call to EMACTimestampConfigSet() with \e ui32SubSecondInc set to +//! the 12.5-MHz clock period of 80 ns, the initial \e ui32Increment value +//! would be set to 0x80000000 to generate a carry on every second main +//! oscillator tick. Because the system time updates each time the accumulator +//! overflows, small changes in the \e ui32Increment value can be used to very +//! finely control the system time rate. +//! +//! \return None. +//! +//! \sa EMACTimestampConfigSet() +// +//***************************************************************************** +void +EMACTimestampAddendSet(uint32_t ui32Base, uint32_t ui32Increment) +{ + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + + HWREG(ui32Base + EMAC_O_TIMADD) = ui32Increment; + + // + // Wait for any previous update to complete. + // + while(HWREG(ui32Base + EMAC_O_TIMSTCTRL) & EMAC_TIMSTCTRL_ADDREGUP) + { + // + // Spin for a while. + // + } + + // + // Force the system clock to update by the value provided. + // + HWREG(ui32Base + EMAC_O_TIMSTCTRL) |= EMAC_TIMSTCTRL_ADDREGUP; +} + +//***************************************************************************** +// +//! Sets the target system time at which the next Ethernet timer interrupt is +//! generated. +//! +//! \param ui32Base is the base address of the controller. +//! \param ui32Seconds is the second value of the desired target time. +//! \param ui32SubSeconds is the subseconds value of the desired target time. +//! +//! This function may be used to schedule an interrupt at some future time. +//! The time reference for the function is the IEEE 1588 time as returned by +//! EMACTimestampSysTimeGet(). To generate an interrupt when the system +//! time exceeds a given value, call this function to set the desired time, +//! then EMACTimestampTargetIntEnable() to enable the interrupt. When the +//! system time increments past the target time, an Ethernet interrupt with +//! status \b EMAC_INT_TIMESTAMP is generated. +//! +//! The accuracy of the interrupt timing depends on the Ethernet timer +//! update frequency and the subsecond increment value currently in use. The +//! interrupt is generated on the first timer increment that causes the +//! system time to be greater than or equal to the target time set. +//! +//! \return None. +// +//***************************************************************************** +void +EMACTimestampTargetSet(uint32_t ui32Base, uint32_t ui32Seconds, + uint32_t ui32SubSeconds) +{ + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + + // + // Wait for any previous write to complete. + // + while(HWREG(ui32Base + EMAC_O_TARGNANO) & EMAC_TARGNANO_TRGTBUSY) + { + } + + // + // Write the new target time. + // + HWREG(ui32Base + EMAC_O_TARGSEC) = ui32Seconds; + HWREG(ui32Base + EMAC_O_TARGNANO) = ui32SubSeconds; +} + +//***************************************************************************** +// +//! Enables the Ethernet system time interrupt. +//! +//! \param ui32Base is the base address of the controller. +//! +//! This function may be used after EMACTimestampTargetSet() to schedule an +//! interrupt at some future time. The time reference for the function is +//! the IEEE 1588 time as returned by EMACTimestampSysTimeGet(). To generate +//! an interrupt when the system time exceeds a given value, call this function +//! to set the desired time, then EMACTimestampTargetIntEnable() to enable the +//! interrupt. When the system time increments past the target time, an +//! Ethernet interrupt with status \b EMAC_INT_TIMESTAMP is generated. +//! +//! \return None. +// +//***************************************************************************** +void +EMACTimestampTargetIntEnable(uint32_t ui32Base) +{ + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + + // + // Set the bit to enable the timestamp target interrupt. This bit clears + // automatically when the interrupt fires after which point, you must + // set a new target time and re-enable the interrupts. + // + HWREG(ui32Base + EMAC_O_TIMSTCTRL) |= EMAC_TIMSTCTRL_INTTRIG; +} + +//***************************************************************************** +// +//! Disables the Ethernet system time interrupt. +//! +//! \param ui32Base is the base address of the controller. +//! +//! This function may be used to disable any pending Ethernet system time +//! interrupt previously scheduled using calls to EMACTimestampTargetSet() +//! and EMACTimestampTargetIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +EMACTimestampTargetIntDisable(uint32_t ui32Base) +{ + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + + // + // Clear the bit to disable the timestamp target interrupt. This bit + // clears automatically when the interrupt fires, so it only must be + // disabled if you want to cancel a previously-set interrupt. + // + HWREG(ui32Base + EMAC_O_TIMSTCTRL) &= ~EMAC_TIMSTCTRL_INTTRIG; +} + +//***************************************************************************** +// +//! Reads the status of the Ethernet system time interrupt. +//! +//! \param ui32Base is the base address of the controller. +//! +//! When an Ethernet interrupt occurs and \b EMAC_INT_TIMESTAMP is reported +//! bu EMACIntStatus(), this function must be called to read and clear the +//! timer interrupt status. +//! +//! \return The return value is the logical OR of the values +//! \b EMAC_TS_INT_TS_SEC_OVERFLOW and \b EMAC_TS_INT_TARGET_REACHED. +//! +//! - \b EMAC_TS_INT_TS_SEC_OVERFLOW indicates that the second counter in the +//! hardware timer has rolled over. +//! - \b EMAC_TS_INT_TARGET_REACHED indicates that the system time incremented +//! past the value set in an earlier call to EMACTimestampTargetSet(). When +//! this occurs, a new target time may be set and the interrupt re-enabled +//! using calls to EMACTimestampTargetSet() and +//! EMACTimestampTargetIntEnable(). +// +//***************************************************************************** +uint32_t +EMACTimestampIntStatus(uint32_t ui32Base) +{ + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + + // + // Return the current interrupt status from the timestamp module. + // + return(HWREG(ui32Base + EMAC_O_TIMSTAT)); +} + +//***************************************************************************** +// +//! Configures the Ethernet MAC PPS output in simple mode. +//! +//! \param ui32Base is the base address of the controller. +//! \param ui32FreqConfig determines the frequency of the output generated on +//! the PPS pin. +//! +//! This function configures the Ethernet MAC PPS (Pulse Per Second) engine to +//! operate in its simple mode which allows the generation of a few, fixed +//! frequencies and pulse widths on the PPS pin. If more complex pulse +//! train generation is required, the MAC also provides a command-based +//! PPS control mode that can be selected by calling +//! EMACTimestampPPSCommandModeSet(). +//! +//! The \e ui32FreqConfig parameter may take one of the following values: +//! +//! - \b EMAC_PPS_SINGLE_PULSE generates a single high pulse on the PPS +//! output once per second. The pulse width is the same as the system clock +//! period. +//! - \b EMAC_PPS_1HZ generates a 1Hz signal on the PPS output. This option +//! is not available if the system time subsecond counter is currently +//! configured to operate in binary rollover mode. +//! - \b EMAC_PPS_2HZ, \b EMAC_PPS_4HZ, \b EMAC_PPS_8HZ, +//! \b EMAC_PPS_16HZ, \b EMAC_PPS_32HZ, \b EMAC_PPS_64HZ, +//! \b EMAC_PPS_128HZ, \b EMAC_PPS_256HZ, \b EMAC_PPS_512HZ, +//! \b EMAC_PPS_1024HZ, \b EMAC_PPS_2048HZ, \b EMAC_PPS_4096HZ, +//! \b EMAC_PPS_8192HZ, \b EMAC_PPS_16384HZ generate the requested +//! frequency on the PPS output in both binary and digital rollover modes. +//! - \b EMAC_PPS_32768HZ generates a 32KHz signal on the PPS output. This +//! option is not available if the system time subsecond counter is currently +//! configured to operate in digital rollover mode. +//! +//! Except when \b EMAC_PPS_SINGLE_PULSE is specified, the signal generated +//! on PPS has a duty cycle of 50% when binary rollover mode is used for the +//! system time subsecond count. In digital mode, the output frequency +//! averages the value requested and is resynchronized each second. For +//! example, if \b EMAC_PPS_4HZ is selected in digital rollover mode, the +//! output generates three clocks with 50 percent duty cycle and 268 ms +//! period followed by a fourth clock of 195 ms period, 134 ms low and 61 ms high. +//! +//! \return None. +// +//***************************************************************************** +void +EMACTimestampPPSSimpleModeSet(uint32_t ui32Base, uint32_t ui32FreqConfig) +{ + bool bDigital; + + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + + // + // Are we currently running the clock in digital or binary rollover mode? + // + bDigital = (HWREG(ui32Base + EMAC_O_TIMSTCTRL) & + EMAC_TS_DIGITAL_ROLLOVER) ? true : false; + + // + // Weed out some unsupported frequencies. The hardware can't produce a + // 1Hz output when we are in binary rollover mode and can't produce a + // 32KHz output when we are digital rollover mode. + // + ASSERT(bDigital || (ui32FreqConfig != EMAC_PPS_1HZ)); + ASSERT(!bDigital || (ui32FreqConfig != EMAC_PPS_32768HZ)); + + // + // Adjust the supplied frequency if we are currently in binary update mode + // where the control value generates an output that is twice as fast as + // in digital mode. + // + if((ui32FreqConfig != EMAC_PPS_SINGLE_PULSE) && !bDigital) + { + ui32FreqConfig--; + } + + // + // Write the frequency control value to the PPS control register, clearing + // the PPSEN0 bit to ensure that the PPS engine is in simple mode and not + // waiting for a command. We also clear the TRGMODS0 field to revert to + // the default operation of the target time registers. + // + HWREG(ui32Base + EMAC_O_PPSCTRL) = ui32FreqConfig; +} + +//***************************************************************************** +// +//! Configures the Ethernet MAC PPS output in command mode. + +//! \param ui32Base is the base address of the controller. +//! \param ui32Config determines how the system target time is used. +//! +//! The simple mode of operation offered by the PPS (Pulse Per Second) engine +//! may be too restrictive for some applications. The second mode, however, +//! allows complex pulse trains to be generated using commands that tell the +//! engine to send individual pulses or start and stop trains if pulses. In +//! this mode, the pulse width and period may be set arbitrarily based on +//! ticks of the clock used to update the system time. Commands are triggered +//! at specific times using the target time last set using a call to +//! EMACTimestampTargetSet(). +//! +//! The \e ui32Config parameter may be used to control whether the target +//! time is used to trigger commands only or can also generate an interrupt +//! to the CPU. Valid values are: +//! +//! - \b EMAC_PPS_TARGET_INT configures the target time to only raise +//! an interrupt and not to trigger any pending PPS command. +//! - \b EMAC_PPS_TARGET_PPS configures the target time to trigger a pending +//! PPS command but not raise an interrupt. +//! - \b EMAC_PPS_TARGET_BOTH configures the target time to trigger any +//! pending PPS command and also raise an interrupt. +//! +//! To use command mode, an application must call this function to enable the +//! mode, then call: +//! +//! - EMACTimestampPPSPeriodSet() to set the desired pulse width and period +//! then +//! - EMACTimestampTargetSet() to set the time at which the next command is +//! executed, and finally +//! - EMACTimestampPPSCommand() to send a command to cause the pulse or +//! pulse train to be started at the required time. +//! +//! \return None. +// +//***************************************************************************** +void +EMACTimestampPPSCommandModeSet(uint32_t ui32Base, uint32_t ui32Config) +{ + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + ASSERT(!(ui32Config & (EMAC_PPS_TARGET_INT | EMAC_PPS_TARGET_PPS | + EMAC_PPS_TARGET_BOTH))); + + // + // Wait for any previous command write to complete. + // + while(HWREG(ui32Base + EMAC_O_PPSCTRL) & EMAC_PPSCTRL_PPSCTRL_M) + { + // + // Wait a bit. + // + } + + // + // Write the configuration value to the PPS control register, setting the + // PPSEN0 bit to ensure that the PPS engine is in command mode and + // clearing the command in the PPSCTRL field. + // + HWREG(ui32Base + EMAC_O_PPSCTRL) = (EMAC_PPSCTRL_PPSEN0 | ui32Config); +} + +//***************************************************************************** +// +//! Sends a command to control the PPS output from the Ethernet MAC. +//! +//! \param ui32Base is the base address of the controller. +//! \param ui8Cmd identifies the command to be sent. +//! +//! This function may be used to send a command to the MAC PPS (Pulse Per +//! Second) controller when it is operating in command mode. Command mode +//! is selected by calling EMACTimestampPPSCommandModeSet(). Valid +//! commands are as follow: +//! +//! - \b EMAC_PPS_COMMAND_NONE indicates no command. +//! - \b EMAC_PPS_COMMAND_START_SINGLE indicates that a single high pulse +//! should be generated when the system time reaches the current target time. +//! - \b EMAC_PPS_COMMAND_START_TRAIN indicates that a train of pulses +//! should be started when the system time reaches the current target time. +//! - \b EMAC_PPS_COMMAND_CANCEL_START cancels any pending start command if +//! the system time has not yet reached the programmed target time. +//! - \b EMAC_PPS_COMMAND_STOP_AT_TIME indicates that the current pulse +//! train should be stopped when the system time reaches the current target +//! time. +//! - \b EMAC_PPS_COMMAND_STOP_NOW indicates that the current pulse train +//! should be stopped immediately. +//! - \b EMAC_PPS_COMMAND_CANCEL_STOP cancels any pending stop command if +//! the system time has not yet reached the programmed target time. +//! +//! In all cases, the width of the pulses generated is governed by the +//! \e ui32Width parameter passed to EMACTimestampPPSPeriodSet(). If a +//! command starts a train of pulses, the period of the pulses is governed +//! by the \e ui32Period parameter passed to the same function. +//! Target times associated with PPS commands are set by calling +//! EMACTimestampTargetSet(). +//! +//! \return None. +// +//***************************************************************************** +void +EMACTimestampPPSCommand(uint32_t ui32Base, uint8_t ui8Cmd) +{ + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + + // + // Wait for any previous command write to complete. + // + while(HWREG(ui32Base + EMAC_O_PPSCTRL) & EMAC_PPSCTRL_PPSCTRL_M) + { + // + // Wait a bit. + // + } + + // + // Write the command to the PPS control register. + // + HWREG(ui32Base + EMAC_O_PPSCTRL) = (EMAC_PPSCTRL_PPSEN0 | ui8Cmd); +} + +//***************************************************************************** +// +//! Sets the period and width of the pulses on the Ethernet MAC PPS output. +//! +//! \param ui32Base is the base address of the controller. +//! \param ui32Period is the period of the PPS output expressed in terms of +//! system time update ticks. +//! \param ui32Width is the width of the high portion of the PPS output +//! expressed in terms of system time update ticks. +//! +//! This function may be used to control the period and duty cycle of the +//! signal output on the Ethernet MAC PPS pin when the PPS generator is +//! operating in command mode and a command to send one or more pulses has been +//! executed. Command mode is selected by calling +//! EMACTimestampPPSCommandModeSet(). +//! +//! In simple mode, the PPS output signal frequency is controlled by the +//! \e ui32FreqConfig parameter passed to EMACTimestampPPSSimpleModeSet(). +//! +//! The \e ui32Period and \e ui32Width parameters are expressed in terms of +//! system time update ticks. When the system time is operating in coarse +//! update mode, each tick is equivalent to the system clock. In fine update +//! mode, a tick occurs every time the 32-bit system time accumulator overflows +//! and this, in turn, is determined by the value passed to the function +//! EMACTimestampAddendSet(). Regardless of the tick source, each tick +//! increments the actual system time, queried using EMACTimestampSysTimeGet() +//! by the subsecond increment value passed in the \e ui32SubSecondInc to +//! EMACTimestampConfigSet(). +//! +//! \return None. +// +//***************************************************************************** +void +EMACTimestampPPSPeriodSet(uint32_t ui32Base, uint32_t ui32Period, + uint32_t ui32Width) +{ + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + + // + // Write the desired PPS period and pulse width. + // + HWREG(ui32Base + EMAC_O_PPS0INTVL) = ui32Period; + HWREG(ui32Base + EMAC_O_PPS0WIDTH) = ui32Width; +} + +//***************************************************************************** +// +//! Sets options related to reception of VLAN-tagged frames. +//! +//! \param ui32Base is the base address of the controller. +//! \param ui16Tag is the IEEE 802.1Q VLAN tag expected for incoming frames. +//! \param ui32Config determines how the receiver handles VLAN-tagged frames. +//! +//! This function configures the receiver's handling of IEEE 802.1Q VLAN +//! tagged frames. Incoming tagged frames are filtered using either a perfect +//! filter or a hash filter. When hash filtering is disabled, VLAN frames +//! tagged with the value of \e ui16Tag pass the filter and all others are +//! rejected. The tag comparison may involve all 16 bits or only the 12-bit +//! VLAN ID portion of the tag. +//! +//! The \e ui32Config parameter is a logical OR of the following values: +//! +//! - \b EMAC_VLAN_RX_HASH_ENABLE enables hash filtering for VLAN tags. If +//! this flag is absent, perfect filtering using the tag supplied in \e ui16Tag +//! is performed. The hash filter may be set using EMACVLANHashFilterSet(), +//! and EMACVLANHashFilterBitCalculate() may be used to determine which bits +//! to set in the filter for given VLAN tags. +//! - \b EMAC_VLAN_RX_SVLAN_ENABLE causes the receiver to recognize S-VLAN +//! (Type = 0x88A8) frames as valid VLAN-tagged frames. If absent, only +//! frames with type 0x8100 are considered valid VLAN frames. +//! - \b EMAC_VLAN_RX_INVERSE_MATCH causes the receiver to pass all VLAN +//! frames for which the tags do not match the supplied \e ui16Tag value. If +//! this flag is absent, only tagged frames matching \e ui16Tag are passed. +//! - \b EMAC_VLAN_RX_12BIT_TAG causes the receiver to compare only the +//! bottom 12 bits of \e ui16Tag when performing either perfect or hash +//! filtering of VLAN frames. If this flag is absent, all 16 bits of the frame +//! tag are examined when filtering. If this flag is set and \e ui16Tag has +//! all bottom 12 bits clear, the receiver passes all frames with types +//! 0x8100 or 0x88A8 regardless of the tag values they contain. +//! +//! \note To ensure that VLAN frames that fail the tag filter are dropped +//! by the MAC, EMACFrameFilterSet() must be called with the \b +//! EMAC_FRMFILTER_VLAN flag set in the \e ui32FilterOpts parameter. If +//! this flag is not set, failing VLAN packets are received by the +//! application, but bit 10 of RDES0 (\b EMAC_FRMFILTER_VLAN) is clear +//! indicating that the packet did not match the current VLAG tag filter. +//! +//! \sa EMACVLANRxConfigGet() +//! +//! \return None +// +//***************************************************************************** +void +EMACVLANRxConfigSet(uint32_t ui32Base, uint16_t ui16Tag, uint32_t ui32Config) +{ + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + + // + // Write the VLAN tag register. + // + HWREG(ui32Base + EMAC_O_VLANTG) = + ui32Config | (((uint32_t)ui16Tag) << EMAC_VLANTG_VL_S); +} + +//***************************************************************************** +// +//! Returns the currently-set options related to reception of VLAN-tagged +//! frames. +//! +//! \param ui32Base is the base address of the controller. +//! \param pui16Tag points to storage which is written with the currently +//! configured VLAN tag used for perfect filtering. +//! +//! This function returns information on how the receiver is currently +//! handling IEEE 802.1Q VLAN-tagged frames. +//! +//! \sa EMACVLANRxConfigSet() +//! +//! \return Returns flags defining how VLAN-tagged frames are handled. The +//! value is a logical OR of the following flags: +//! +//! - \b EMAC_VLAN_RX_HASH_ENABLE indicates that hash filtering is enabled +//! for VLAN tags. If this flag is absent, perfect filtering using the tag +//! returned in \e *pui16Tag is performed. +//! - \b EMAC_VLAN_RX_SVLAN_ENABLE indicates that the receiver recognizes +//! S-VLAN (Type = 0x88A8) frames as valid VLAN-tagged frames. If absent, only +//! frames with type 0x8100 are considered valid VLAN frames. +//! - \b EMAC_VLAN_RX_INVERSE_MATCH indicates that the receiver passes all +//! VLAN frames for which the tags do not match the \e *pui16Tag value. If +//! this flag is absent, only tagged frames matching \e *pui16Tag are passed. +//! - \b EMAC_VLAN_RX_12BIT_TAG indicates that the receiver is comparing only +//! the bottom 12 bits of \e *pui16Tag when performing either perfect or hash +//! filtering of VLAN frames. If this flag is absent, all 16 bits of the frame +//! tag are examined when filtering. If this flag is set and \e *pui16Tag has +//! all bottom 12 bits clear, the receiver passes all frames with types +//! 0x8100 or 0x88A8 regardless of the tag values they contain. +// +//***************************************************************************** +uint32_t +EMACVLANRxConfigGet(uint32_t ui32Base, uint16_t *pui16Tag) +{ + uint32_t ui32Value; + + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + ASSERT(pui16Tag); + + // + // Read the VLAN tag register. + // + ui32Value = HWREG(ui32Base + EMAC_O_VLANTG); + + // + // Extract the VLAN tag from the register. + // + *pui16Tag = (ui32Value & EMAC_VLANTG_VL_M) >> EMAC_VLANTG_VL_S; + + // + // Return the configuration flags. + // + return(ui32Value & ~EMAC_VLANTG_VL_M); +} + +//***************************************************************************** +// +//! Sets options related to transmission of VLAN-tagged frames. +//! +//! \param ui32Base is the base address of the controller. +//! \param ui16Tag is the VLAN tag to be used when inserting or replacing tags +//! in transmitted frames. +//! \param ui32Config determines the VLAN-related processing performed by +//! the transmitter. +//! +//! This function is used to configure transmitter options relating to +//! IEEE 802.1Q VLAN tagging. The transmitter may be set to insert tagging +//! into untagged frames or replace existing tags with new values. +//! +//! The \e ui16Tag parameter contains the VLAN tag to be used in outgoing +//! tagged frames. The \e ui32Config parameter is a logical OR of the +//! following labels: +//! +//! - \b EMAC_VLAN_TX_SVLAN uses the S-VLAN type (0x88A8) when inserting or +//! replacing tags in transmitted frames. If this label is absent, C-VLAN +//! type (0x8100) is used. +//! - \b EMAC_VLAN_TX_USE_VLC informs the transmitter that the VLAN tag +//! handling should be defined by the VLAN control (VLC) value provided in +//! this function call. If this tag is absent, VLAN handling is controlled +//! by fields in the transmit descriptor. +//! +//! If \b EMAC_VLAN_TX_USE_VLC is set, one of the following four labels +//! must also be included to define the transmit VLAN tag handling: +//! +//! - \b EMAC_VLAN_TX_VLC_NONE instructs the transmitter to perform no VLAN +//! tag insertion, deletion or replacement. +//! - \b EMAC_VLAN_TX_VLC_DELETE instructs the transmitter to remove VLAN +//! tags from all transmitted frames that contain them. As a result, bytes +//! 13, 14, 15 and 16 are removed from all frames with types 0x8100 or 0x88A8. +//! - \b EMAC_VLAN_TX_VLC_INSERT instructs the transmitter to insert a VLAN +//! type and tag into all outgoing frames regardless of whether or not they +//! already contain a VLAN tag. +//! - \b EMAC_VLAN_TX_VLC_REPLACE instructs the transmitter to replace the +//! VLAN tag in all frames of type 0x8100 or 0x88A8 with the value provided to +//! this function in the \e ui16Tag parameter. +//! +//! \return None +// +//***************************************************************************** +void +EMACVLANTxConfigSet(uint32_t ui32Base, uint16_t ui16Tag, uint32_t ui32Config) +{ + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + + // + // Write the VLAN Tag Inclusion or Replacement register. + // + HWREG(ui32Base + EMAC_O_VLNINCREP) = + ui32Config | ((uint32_t)ui16Tag << EMAC_VLNINCREP_VLT_S); +} + +//***************************************************************************** +// +//! Returns currently-selected options related to transmission of VLAN-tagged +//! frames. +//! +//! \param ui32Base is the base address of the controller. +//! \param pui16Tag points to storage that is written with the VLAN tag +//! currently being used for insertion or replacement. +//! +//! This function returns information on the current settings related to VLAN +//! tagging of transmitted frames. +//! +//! \sa EMACVLANTxConfigSet() +//! +//! \return Returns flags describing the current VLAN configuration relating +//! to frame transmission. The return value is a logical OR of the following +//! values: +//! +//! - \b EMAC_VLAN_TX_SVLAN indicates that the S-VLAN type (0x88A8) is +//! being used when inserting or replacing tags in transmitted frames. If +//! this label is absent, C-VLAN type (0x8100) is being used. +//! - \b EMAC_VLAN_TX_USE_VLC indicates that the transmitter is processing +//! VLAN frames according to the VLAN control (VLC) value returned here. If +//! this tag is absent, VLAN handling is controlled by fields in the transmit +//! descriptor. +//! +//! If \b EMAC_VLAN_TX_USE_VLC is returned, one of the following four labels +//! is also included to define the transmit VLAN tag handling. Note that this +//! value may be extracted from the return value using the mask \b +//! EMAC_VLAN_TX_VLC_MASK. +//! +//! - \b EMAC_VLAN_TX_VLC_NONE indicates that the transmitter is not +//! performing VLAN tag insertion, deletion or replacement. +//! - \b EMAC_VLAN_TX_VLC_DELETE indicates that the transmitter is removing +//! VLAN tags from all transmitted frames which contain them. +//! - \b EMAC_VLAN_TX_VLC_INSERT indicates that the transmitter is inserting +//! a VLAN type and tag into all outgoing frames regardless of whether or not +//! they already contain a VLAN tag. +//! - \b EMAC_VLAN_TX_VLC_REPLACE indicates that the transmitter is replacing +//! the VLAN tag in all transmitted frames of type 0x8100 or 0x88A8 with the +//! value returned in \e *pui16Tag. +// +//***************************************************************************** +uint32_t +EMACVLANTxConfigGet(uint32_t ui32Base, uint16_t *pui16Tag) +{ + uint32_t ui32Value; + + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + ASSERT(pui16Tag); + + // + // Read the VLAN Tag Inclusion or Replacement register. + // + ui32Value = HWREG(ui32Base + EMAC_O_VLNINCREP); + + // + // Extract the tag. + // + *pui16Tag = (uint16_t)((ui32Value & EMAC_VLNINCREP_VLT_M) >> + EMAC_VLNINCREP_VLT_S); + + // + // Return the configuration flags. + // + return(ui32Value & ~EMAC_VLNINCREP_VLT_M); +} + +//***************************************************************************** +// +//! Returns the bit number to set in the VLAN hash filter corresponding to a +//! given tag. +//! +//! \param ui16Tag is the VLAN tag for which the hash filter bit number is to +//! be determined. +//! +//! This function may be used to determine which bit in the VLAN hash filter +//! to set to describe a given 12- or 16-bit VLAN tag. The returned value is +//! a 4-bit value indicating the bit number to set within the 16-bit VLAN +//! hash filter. For example, if 0x02 is returned, this indicates that bit +//! 2 of the hash filter must be set to pass the supplied VLAN tag. +//! +//! \return Returns the bit number to set in the VLAN hash filter to describe +//! the passed tag. +// +//***************************************************************************** +uint32_t +EMACVLANHashFilterBitCalculate(uint16_t ui16Tag) +{ + uint32_t ui32CRC, ui32Mask, ui32Loop; + + // + // Calculate the CRC for the MAC address. + // + ui32CRC = Crc32(0xFFFFFFFF, (uint8_t *)&ui16Tag, 2); + ui32CRC ^= 0xFFFFFFFF; + + // + // Determine the hash bit to use from the calculated CRC. This is the + // top 4 bits of the reversed CRC (or the bottom 4 bits of the calculated + // CRC with the bit order of those 4 bits reversed). + // + ui32Mask = 0; + + // + // Reverse the order of the bottom 4 bits of the calculated CRC. + // + for(ui32Loop = 0; ui32Loop < 4; ui32Loop++) + { + ui32Mask <<= 1; + ui32Mask |= (ui32CRC & 1); + ui32CRC >>= 1; + } + + // + // Return the final hash filter bit index. + // + return(ui32Mask); +} + +//***************************************************************************** +// +//! Sets the hash filter used to control reception of VLAN-tagged frames. +//! +//! \param ui32Base is the base address of the controller. +//! \param ui32Hash is the hash filter value to set. +//! +//! This function allows the VLAG tag hash filter to be set. By using hash +//! filtering, several different VLAN tags can be filtered very easily at the +//! cost of some false positive results that must be removed by software. +//! +//! The hash filter value passed in \e ui32Hash may be built up by calling +//! EMACVLANHashFilterBitCalculate() for each VLAN tag that is to pass the +//! filter and then set each of the bits for which the numbers are returned by +//! that function. Care must be taken when clearing bits in the hash filter +//! due to the fact that there is a many-to-one correspondence between VLAN +//! tags and hash filter bits. +//! +//! \return None +// +//***************************************************************************** +void +EMACVLANHashFilterSet(uint32_t ui32Base, uint32_t ui32Hash) +{ + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + + // + // Write the VLAN Hash Table register. + // + HWREG(ui32Base + EMAC_O_VLANHASH) = ui32Hash; +} + +//***************************************************************************** +// +//! Returns the current value of the hash filter used to control reception of +//! VLAN-tagged frames. +//! +//! \param ui32Base is the base address of the controller. +//! +//! This function allows the current VLAN tag hash filter value to be returned. +//! Additional VLAN tags may be added to this filter by setting the appropriate +//! bits, determined by calling EMACVLANHashFilterBitCalculate(), and then +//! calling EMACVLANHashFilterSet() to set the new filter value. +//! +//! \return Returns the current value of the VLAN hash filter. +// +//***************************************************************************** +uint32_t +EMACVLANHashFilterGet(uint32_t ui32Base) +{ + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + + // + // Return the VLAN Hash Table register. + // + return(HWREG(ui32Base + EMAC_O_VLANHASH)); +} + +//***************************************************************************** +// +//! Sets values defining up to four frames used to trigger a remote wake-up. +//! +//! \param ui32Base is the base address of the controller. +//! \param pFilter points to the structure containing remote wake-up frame +//! filter information. +//! +//! This function may be used to define up to four different frames that +//! are considered by the Ethernet MAC to be remote wake-up signals. The +//! data passed to the function describes a wake-up frame in terms of a CRC +//! calculated on up to 31 payload bytes in the frame. The actual bytes used +//! in the CRC calculation are defined by means of a bit mask where a ``1'' +//! indicates that a byte in the frame should contribute to the CRC +//! calculation and a ``0'' indicates that the byte should be skipped, as well +//! as an offset from the start of the frame to the payload byte that represents +//! the first byte in the 31-byte CRC-checked sequence. +//! +//! The \e pFilter parameter points to a structure containing the information +//! necessary to set up the filters. This structure contains the following +//! fields, each of which is replicated 4 times, once for each possible wake-up +//! frame: +//! +//! - \b pui32ByteMask defines whether a given byte in the chosen 31-byte +//! sequence within the frame should contribute to the CRC calculation or not. +//! A 1 indicates that the byte should contribute to the calculation, a 0 +//! causes the byte to be skipped. +//! - \b pui8Command contains flags defining whether this filter is enabled +//! and, if so, whether it refers to unicast or multicast packets. Valid +//! values are one of \b EMAC_RWU_FILTER_MULTICAST or \b +//! EMAC_RWU_FILTER_UNICAST ORed with one of \b EMAC_RWU_FILTER_ENABLE or +//! \b EMAC_RWU_FILTER_DISABLE. +//! - \b pui8Offset defines the zero-based index of the byte within the frame +//! at which CRC checking defined by \b pui32ByteMask begins. +//! Alternatively, this value can be thought of as the number of bytes in the +//! frame that the MAC skips before accumulating the CRC based on the pattern +//! in \b pui32ByteMask. +//! - \b pui16CRC provides the value of the calculated CRC for a valid remote +//! wake-up frame. If the incoming frame is processed according to the filter +//! values provided and the final CRC calculation equals this value, the +//! frame is considered to be a valid remote wake-up frame. +//! +//! Note that this filter uses CRC16 rather than CRC32 as used in frame +//! checksums. The required CRC uses a direct algorithm with polynomial 0x8005, +//! initial seed value 0xFFFF, no final XOR and reversed data order. CRCs +//! for use in this function may be determined using the online calculator +//! found at http://www.zorc.breitbandkatze.de/crc.html. +//! +//! \return None. +// +//***************************************************************************** +void +EMACRemoteWakeUpFrameFilterSet(uint32_t ui32Base, + const tEMACWakeUpFrameFilter *pFilter) +{ + uint32_t *pui32Data; + uint32_t ui32Loop; + + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + ASSERT(pFilter); + + // + // Make sure that the internal register counter for the frame filter + // is reset. This bit automatically resets after 1 clock cycle. + // + HWREG(ui32Base + EMAC_O_PMTCTLSTAT) |= EMAC_PMTCTLSTAT_WUPFRRST; + + // + // Get a word pointer to the supplied structure. + // + pui32Data = (uint32_t *)pFilter; + + // + // Write the 8 words of the wake-up filter definition to the hardware. + // + for(ui32Loop = 0; ui32Loop < 8; ui32Loop++) + { + // + // Write a word of the filter definition. + // + HWREG(ui32Base + EMAC_O_RWUFF) = pui32Data[ui32Loop]; + } +} + +//***************************************************************************** +// +//! Returns the current remote wake-up frame filter configuration. +//! +//! \param ui32Base is the base address of the controller. +//! \param pFilter points to the structure that is written with the current +//! remote wake-up frame filter information. +//! +//! This function may be used to read the current wake-up frame filter +//! settings. The data returned by the function describes wake-up frames in +//! terms of a CRC calculated on up to 31 payload bytes in the frame. The +//! actual bytes used in the CRC calculation are defined by means of a bit mask +//! where a ``1'' indicates that a byte in the frame should contribute to the +//! CRC calculation and a ``0'' indicates that the byte should be skipped, and +//! an offset from the start of the frame to the payload byte that represents +//! the first byte in the 31-byte CRC-checked sequence. +//! +//! The \e pFilter parameter points to storage that is written with a +//! structure containing the information defining the frame filters. This +//! structure contains the following fields, each of which is replicated 4 +//! times, once for each possible wake-up frame: +//! +//! - \b pui32ByteMask defines whether a given byte in the chosen 31-byte +//! sequence within the frame should contribute to the CRC calculation or not. +//! A 1 indicates that the byte should contribute to the calculation, a 0 +//! causes the byte to be skipped. +//! - \b pui8Command contains flags defining whether this filter is enabled +//! and, if so, whether it refers to unicast or multicast packets. Valid +//! values are one of \b EMAC_RWU_FILTER_MULTICAST or \b +//! EMAC_RWU_FILTER_UNICAST ORed with one of \b EMAC_RWU_FILTER_ENABLE or +//! \b EMAC_RWU_FILTER_DISABLE. +//! - \b pui8Offset defines the zero-based index of the byte within the frame +//! at which CRC checking defined by \b pui32ByteMask begins. +//! Alternatively, this value can be thought of as the number of bytes in the +//! frame that the MAC skips before accumulating the CRC based on the pattern +//! in \b pui32ByteMask. +//! - \b pui16CRC provides the value of the calculated CRC for a valid remote +//! wake-up frame. If the incoming frame is processed according to the filter +//! values provided and the final CRC calculation equals this value, the +//! frame is considered to be a valid remote wake-up frame. +//! +//! Note that this filter uses CRC16 rather than CRC32 as used in frame +//! checksums. +//! +//! \return None. +// +//***************************************************************************** +void +EMACRemoteWakeUpFrameFilterGet(uint32_t ui32Base, + tEMACWakeUpFrameFilter *pFilter) +{ + uint32_t *pui32Data; + uint32_t ui32Loop; + + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + ASSERT(pFilter); + + // + // Make sure that the internal register counter for the frame filter + // is reset. This bit automatically resets after 1 clock cycle. + // + HWREG(ui32Base + EMAC_O_PMTCTLSTAT) |= EMAC_PMTCTLSTAT_WUPFRRST; + + // + // Get a word pointer to the supplied structure. + // + pui32Data = (uint32_t *)pFilter; + + // + // Read the 8 words of the wake-up filter definition from the hardware. + // + for(ui32Loop = 0; ui32Loop < 8; ui32Loop++) + { + // + // Read a word of the filter definition. + // + pui32Data[ui32Loop] = HWREG(ui32Base + EMAC_O_RWUFF); + } +} + +//***************************************************************************** +// +//! Sets the Ethernet MAC remote wake-up configuration. +//! +//! \param ui32Base is the base address of the controller. +//! \param ui32Flags defines which types of frame should trigger a remote +//! wake-up and allows the MAC to be put into power-down mode. +//! +//! This function allows the MAC's remote wake-up features to be configured, +//! determining which types of frame should trigger a wake-up event and +//! allowing an application to place the MAC in power-down mode. In this +//! mode, the MAC ignores all received frames until one matching a +//! configured remote wake-up frame is received, at which point the MAC +//! automatically exits power-down mode and continues to receive frames. +//! +//! The \e ui32Flags parameter is a logical OR of the following flags: +//! +//! - \b EMAC_PMT_GLOBAL_UNICAST_ENABLE instructs the MAC to wake up when any +//! unicast frame matching the MAC destination address filter is received. +//! - \b EMAC_PMT_WAKEUP_PACKET_ENABLE instructs the MAC to wake up when any +//! received frame matches the remote wake-up filter configured via a call +//! to EMACRemoteWakeUpFrameFilterSet(). +//! - \b EMAC_PMT_MAGIC_PACKET_ENABLE instructs the MAC to wake up when a +//! standard Wake-on-LAN "magic packet" is received. The magic packet contains +//! 6 bytes of 0xFF followed immediately by 16 repetitions of the destination +//! MAC address. +//! - \b EMAC_PMT_POWER_DOWN instructs the MAC to enter power-down mode and +//! wait for an incoming frame matching the remote wake-up frames as described +//! by other flags and via the remote wake-up filter. This flag should only +//! set set if at least one other flag is specified to configure a wake-up +//! frame type. +//! +//! When the MAC is in power-down mode, software may exit the mode by calling +//! this function with the \b EMAC_PMT_POWER_DOWN flag absent from \e ui32Flags. +//! If a configured wake-up frame is received while in power-down mode, the +//! \b EMAC_INT_POWER_MGMNT interrupt is signaled and may be cleared by reading +//! the status using EMACPowerManagementStatusGet(). +//! +//! \note While it is possible to gate the clock to the MAC while it is in +//! power-down mode, doing so prevents the reading of the registers required +//! to determine the interrupt status and also prevents power-down mode from +//! exiting via another call to this function. +//! +//! \return None. +// +//***************************************************************************** +void +EMACPowerManagementControlSet(uint32_t ui32Base, uint32_t ui32Flags) +{ + uint32_t ui32Value; + + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + ASSERT(~(ui32Flags & ~(EMAC_PMT_GLOBAL_UNICAST_ENABLE | + EMAC_PMT_WAKEUP_PACKET_ENABLE | + EMAC_PMT_MAGIC_PACKET_ENABLE | + EMAC_PMT_POWER_DOWN))); + + // + // Read the control/status register, clear all the bits we can set, mask + // in the new values then rewrite the new register value. + // + ui32Value = HWREG(ui32Base + EMAC_O_PMTCTLSTAT); + ui32Value &= ~(EMAC_PMTCTLSTAT_GLBLUCAST | EMAC_PMTCTLSTAT_WUPFREN | + EMAC_PMTCTLSTAT_MGKPKTEN | EMAC_PMTCTLSTAT_PWRDWN); + ui32Value |= ui32Flags; + HWREG(ui32Base + EMAC_O_PMTCTLSTAT) = ui32Value; +} + +//***************************************************************************** +// +//! Queries the current Ethernet MAC remote wake-up configuration. +//! +//! \param ui32Base is the base address of the controller. +//! +//! This function allows the MAC's remote wake-up settings to be queried. +//! These settings determine which types of frame should trigger a remote +//! wake-up event +//! +//! \return Returns a logical OR of the following flags: +//! +//! - \b EMAC_PMT_GLOBAL_UNICAST_ENABLE indicates that the MAC wakes up when +//! any unicast frame matching the MAC destination address filter is received. +//! - \b EMAC_PMT_WAKEUP_PACKET_ENABLE indicates that the MAC wakes up when any +//! received frame matches the remote wake-up filter configured via a call +//! to EMACRemoteWakeUpFrameFilterSet(). +//! - \b EMAC_PMT_MAGIC_PACKET_ENABLE indicates that the MAC wakes up when a +//! standard Wake-on-LAN "magic packet" is received. The magic packet contains +//! 6 bytes of 0xFF followed immediately by 16 repetitions of the destination +//! MAC address. +//! - \b EMAC_PMT_POWER_DOWN indicates that the MAC is currently in power-down +//! mode and is waiting for an incoming frame matching the remote wake-up +//! frames as described by other returned flags and via the remote wake-up +//! filter. +// +//***************************************************************************** +uint32_t +EMACPowerManagementControlGet(uint32_t ui32Base) +{ + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + + // + // Read the control/status register and mask off the control bits to return + // them to the caller. + // + return(HWREG(ui32Base + EMAC_O_PMTCTLSTAT) & + (EMAC_PMTCTLSTAT_GLBLUCAST | EMAC_PMTCTLSTAT_WUPFREN | + EMAC_PMTCTLSTAT_MGKPKTEN | EMAC_PMTCTLSTAT_PWRDWN)); +} + +//***************************************************************************** +// +//! Queries the current Ethernet MAC remote wake-up status. +//! +//! \param ui32Base is the base address of the controller. +//! +//! This function returns information on the remote wake-up state of the +//! Ethernet MAC. If the MAC has been woken up since the last call, the +//! returned value indicates the type of received frame that caused the MAC +//! to exit power-down state. +//! +//! \return Returns a logical OR of the following flags: +//! +//! - \b EMAC_PMT_POWER_DOWN indicates that the MAC is currently in power-down +//! mode. +//! - \b EMAC_PMT_WAKEUP_PACKET_RECEIVED indicates that the MAC exited +//! power-down mode due to a remote wake-up frame being received. This +//! function call clears this flag. +//! - \b EMAC_PMT_MAGIC_PACKET_RECEIVED indicates that the MAC exited +//! power-down mode due to a wake-on-LAN magic packet being received. This +//! function call clears this flag. +// +//***************************************************************************** +uint32_t +EMACPowerManagementStatusGet(uint32_t ui32Base) +{ + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + + // + // Read the control/status register and mask off the status bits to return + // them to the caller. + // + return(HWREG(ui32Base + EMAC_O_PMTCTLSTAT) & + (EMAC_PMTCTLSTAT_WUPRX | EMAC_PMTCTLSTAT_MGKPRX | + EMAC_PMTCTLSTAT_PWRDWN)); +} + +//***************************************************************************** +// +//! Enables the wake-on-LAN feature of the MAC controller. +//! +//! \param ui32Base is the base address of the controller. +//! +//! This function is used to enable the wake-on-LAN feature of the MAC +//! controller. It is done by first checking if the transmit path is idle and +//! disabling the trasnmitter and the transmit DMA controller. Then it checks +//! if any data from the network is being actively received and if not then it +//! disables the receive DMA controller. +//! +//! \return None. +// +//***************************************************************************** +void +EMACWoLEnter(uint32_t ui32Base) +{ + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + + // + // Check if the Transmit interrupt bit is clear. + // + while(HWREG(ui32Base + EMAC_O_DMARIS) == EMAC_DMARIS_TI) + { + } + + // + // Disable transmission in the MAC configuration register. + // + HWREG(ui32Base + EMAC_O_CFG) &= ~EMAC_CFG_TE; + + // + // Disable the MAC transmit path in the opmode register. + // + HWREG(ui32Base + EMAC_O_DMAOPMODE) &= ~EMAC_DMAOPMODE_ST; + + // + // Check if the Receive FIFO is empty. + // + while((HWREG(ui32Base + EMAC_O_STATUS) & EMAC_STATUS_RX_FIFO_LEVEL_MASK) == + EMAC_STATUS_RX_FIFO_EMPTY) + { + } + + // + // Disable the MAC receive path. + // + HWREG(ui32Base + EMAC_O_DMAOPMODE) &= ~EMAC_DMAOPMODE_SR; +} + +//***************************************************************************** +// +//! Configures the LPI timers and control register. +//! +//! \param ui32Base is the base address of the controller. +//! \param bLPIConfig is state of LPI trasnmit automate bit. +//! \param ui16LPILSTimer is the value of LS timer in milli-seconds. +//! \param ui16LPITWTimer is the value of TW timer in micro-seconds. +//! +//! This function is used to configure the LPI timer and control registers when +//! the link is established as EEE mode or when the link is lost. When the link +//! is established as EEE, then \e ui16LPILSTimer is programmed as the link +//! status timer value and \e ui16LPITWTimer is programmed as the transmit wait +//! timer value. The parameter \e bLPIConfig is used to decide if the transmit +//! path must be automated or should be under user control. +//! +//! \return None. +// +//***************************************************************************** +void +EMACLPIConfig(uint32_t ui32Base, bool bLPIConfig, uint16_t ui16LPILSTimer, + uint16_t ui16LPITWTimer) +{ + uint32_t ui32TimerValue; + + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + + ui32TimerValue = ((ui16LPILSTimer << EMAC_LPITIMERCTL_LST_S) & + EMAC_LPITIMERCTL_LST_M); + ui32TimerValue |= ui16LPITWTimer & EMAC_LPITIMERCTL_TWT_M; + + // + // Update the LPI Timer. + // + HWREG(ui32Base + EMAC_O_LPITIMERCTL) = ui32TimerValue; + + // + // Configure the LPI Control registers. + // + if(bLPIConfig) + { + HWREG(ui32Base + EMAC_O_LPICTLSTAT) |= EMAC_LPICTLSTAT_LPITXA; + } + else + { + HWREG(ui32Base + EMAC_O_LPICTLSTAT) = 0x0; + } +} + +//***************************************************************************** +// +//! Enables the transmit path for LPI mode entry. +//! +//! \param ui32Base is the base address of the controller. +//! +//! This function is used to enable the transmit path in LPI mode when there +//! is no more data to be transmitted by the MAC controller. +//! +//! \return None. +// +//***************************************************************************** +void +EMACLPIEnter(uint32_t ui32Base) +{ + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + + HWREG(ui32Base + EMAC_O_LPICTLSTAT) |= EMAC_LPICTLSTAT_LPIEN; +} + +//***************************************************************************** +// +//! Returns the status of the LPI link. +//! +//! \param ui32Base is the base address of the controller. +//! +//! This function may be used to read the status of the transmit and receive +//! path when the link is configured in LPI mode. +//! +//! \return Returns the lower 16 bits of the LPI Control and Status register. +// +//***************************************************************************** +uint16_t +EMACLPIStatus(uint32_t ui32Base) +{ + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + + // + // Configure the LPI Control registers. + // + return(HWREG(ui32Base + EMAC_O_LPICTLSTAT) & 0xFFFF); +} + +//***************************************************************************** +// +//! Sets the link status of the external PHY. +//! +//! \param ui32Base is the base address of the controller. +//! +//! This function is used to set the link status of the external PHY when the +//! link is established in EEE mode. +//! +//! \return None. +// +//***************************************************************************** +void +EMACLPILinkSet(uint32_t ui32Base) +{ + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + + // + // Configure the LPI Control registers. + // + HWREG(ui32Base + EMAC_O_LPICTLSTAT) |= EMAC_LPICTLSTAT_PLS; +} + +//***************************************************************************** +// +//! Clears the link status of the external PHY. +//! +//! \param ui32Base is the base address of the controller. +//! +//! This function is used to clear the link status of the external PHY when the +//! link is lost due to a disconnect or EEE mode link is not established. +//! +//! \return None. +// +//***************************************************************************** +void +EMACLPILinkClear(uint32_t ui32Base) +{ + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + + // + // Configure the LPI Control registers. + // + HWREG(ui32Base + EMAC_O_LPICTLSTAT) &= ~(EMAC_LPICTLSTAT_PLS); +} + +//***************************************************************************** +// +//! Writes a value to an extended PHY register in MMD address space. +//! +//! \param ui32Base is the base address of the controller. +//! \param ui8PhyAddr is the physical address of the PHY to access. +//! \param ui16RegAddr is the address of the PHY extended register to be +//! accessed. +//! \param ui16Value is the value to write to the register. +//! +//! When uhen connected to an external PHY supporting extended registers in MMD +//! address space, this function allows a value to be written to the MMD +//! register specified by \e ui16RegAddr. +//! +//! \return None. +// +//***************************************************************************** +void +EMACPHYMMDWrite(uint32_t ui32Base, uint8_t ui8PhyAddr, uint16_t ui16RegAddr, + uint16_t ui16Data) +{ + // + // Parameter sanity check. + // + ASSERT(ui8PhyAddr < 32); + + // + // Set the address of the register we're about to write. + // + EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_REGCTL, DEV_ADDR(ui16RegAddr)); + EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_ADDAR, REG_ADDR(ui16RegAddr)); + + // + // Write the extended register value. + // + EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_REGCTL, + (0x4000 | DEV_ADDR(ui16RegAddr))); + EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_REGCTL, ui16Data); +} + +//***************************************************************************** +// +//! Reads from an extended PHY register in MMD address space. +//! +//! \param ui32Base is the base address of the controller. +//! \param ui8PhyAddr is the physical address of the PHY to access. +//! \param ui16RegAddr is the address of the PHY extended register to be +//! accessed. +//! +//! When connected to an external PHY supporting extended registers, this +//! this function returns the contents of the MMD register specified by +//! \e ui16RegAddr. +//! +//! \return Returns the 16-bit value read from the PHY. +// +//***************************************************************************** +uint16_t +EMACPHYMMDRead(uint32_t ui32Base, uint8_t ui8PhyAddr, uint16_t ui16RegAddr) +{ + // + // Parameter sanity check. + // + ASSERT(ui8PhyAddr < 32); + + // + // Set the address of the register we're about to read. + // + EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_REGCTL, DEV_ADDR(ui16RegAddr)); + EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_ADDAR, REG_ADDR(ui16RegAddr)); + + // + // Read the extended register value. + // + EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_REGCTL, + (0x4000 | DEV_ADDR(ui16RegAddr))); + return(EMACPHYRead(ui32Base, ui8PhyAddr, EPHY_ADDAR)); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/epi.c b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/epi.c new file mode 100644 index 0000000000000000000000000000000000000000..c85a02621e8aff6e210bcbdcb3b1181b5395b656 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/epi.c @@ -0,0 +1,2187 @@ +//***************************************************************************** +// +// epi.c - Driver for the EPI module. +// +// Copyright (c) 2008-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#include +#include +#include "inc/hw_epi.h" +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/epi.h" +#include "driverlib/interrupt.h" + +//***************************************************************************** +// +//! \addtogroup epi_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Helper masks for chip select configuration options. +// +//***************************************************************************** +#define EPI_HB8_CS_MASK (EPI_HB8_MODE_FIFO | EPI_HB8_RDWAIT_3 | \ + EPI_HB8_WRWAIT_3 | EPI_HB8_RDHIGH | \ + EPI_HB8_WRHIGH | EPI_HB8_ALE_HIGH) + +#define EPI_HB16_CS_MASK (EPI_HB8_CS_MASK | EPI_HB16_BURST_TRAFFIC) + +//***************************************************************************** +// +// Ensure that erratum workaround inline functions have a public version +// available in exactly one object module (this one). +// +//***************************************************************************** + +//***************************************************************************** +// +//! Safely writes a word to the EPI 0x10000000 address space. +//! +//! \param pui32Addr is the address which is to be written. +//! \param ui32Value is the 32-bit word to write. +//! +//! This function must be used when writing words to EPI-attached memory +//! configured to use the address space at 0x10000000 on devices affected by +//! the EPI#01 erratum. Direct access to memory in these cases can cause data +//! corruption depending upon memory accesses immediately before or after the +//! EPI access but using this function will allow EPI accesses to complete +//! correctly. The function is defined as ``inline'' in epi.h. +//! +//! Use of this function on a device not affected by the erratum is safe but +//! will impact performance due to an additional overhead of at least 2 cycles +//! per access. This erratum affects only the 0x10000000 address space +//! typically used to store the LCD controller frame buffer. The 0x60000000 +//! address space is not affected and applications using this address mapping +//! need not use this function. +//! +//! \return None. +// +//***************************************************************************** +extern void EPIWorkaroundWordWrite(uint32_t *pui32Addr, uint32_t ui32Value); + +//***************************************************************************** +// +//! Safely reads a word from the EPI 0x10000000 address space. +//! +//! \param pui32Addr is the address which is to be read. +//! +//! This function must be used when reading words from EPI-attached memory +//! configured to use the address space at 0x10000000 on devices affected by +//! the EPI#01 erratum. Direct access to memory in these cases can cause data +//! corruption depending upon memory accesses immediately before or after the +//! EPI access but using this function will allow EPI accesses to complete +//! correctly. The function is defined as ``inline'' in epi.h. +//! +//! Use of this function on a device not affected by the erratum is safe but +//! will impact performance due to an additional overhead of at least 2 cycles +//! per access. This erratum affects only the 0x10000000 address space +//! typically used to store the LCD controller frame buffer. The 0x60000000 +//! address space is not affected and applications using this address mapping +//! need not use this function. +//! +//! \return The 32-bit word stored at address \e pui32Addr. +// +//***************************************************************************** +extern uint32_t EPIWorkaroundWordRead(uint32_t *pui32Addr); + +//***************************************************************************** +// +//! Safely writes a half-word to the EPI 0x10000000 address space. +//! +//! \param pui16Addr is the address which is to be written. +//! \param ui16Value is the 16-bit half-word to write. +//! +//! This function must be used when writing half-words to EPI-attached memory +//! configured to use the address space at 0x10000000 on devices affected by +//! the EPI#01 erratum. Direct access to memory in these cases can cause data +//! corruption depending upon memory accesses immediately before or after the +//! EPI access but using this function will allow EPI accesses to complete +//! correctly. The function is defined as ``inline'' in epi.h. +//! +//! Use of this function on a device not affected by the erratum is safe but +//! will impact performance due to an additional overhead of at least 2 cycles +//! per access. This erratum affects only the 0x10000000 address space +//! typically used to store the LCD controller frame buffer. The 0x60000000 +//! address space is not affected and applications using this address mapping +//! need not use this function. +//! +//! \return None. +// +//***************************************************************************** +extern void EPIWorkaroundHWordWrite(uint16_t *pui16Addr, uint16_t ui16Value); + +//***************************************************************************** +// +//! Safely reads a half-word from the EPI 0x10000000 address space. +//! +//! \param pui16Addr is the address which is to be read. +//! +//! This function must be used when reading half-words from EPI-attached memory +//! configured to use the address space at 0x10000000 on devices affected by +//! the EPI#01 erratum. Direct access to memory in these cases can cause data +//! corruption depending upon memory accesses immediately before or after the +//! EPI access but using this function will allow EPI accesses to complete +//! correctly. The function is defined as ``inline'' in epi.h. +//! +//! Use of this function on a device not affected by the erratum is safe but +//! will impact performance due to an additional overhead of at least 2 cycles +//! per access. This erratum affects only the 0x10000000 address space +//! typically used to store the LCD controller frame buffer. The 0x60000000 +//! address space is not affected and applications using this address mapping +//! need not use this function. +//! +//! \return The 16-bit word stored at address \e pui16Addr. +// +//***************************************************************************** +extern uint16_t EPIWorkaroundHWordRead(uint16_t *pui16Addr); + +//***************************************************************************** +// +//! Safely writes a byte to the EPI 0x10000000 address space. +//! +//! \param pui8Addr is the address which is to be written. +//! \param ui8Value is the 8-bit byte to write. +//! +//! This function must be used when writing bytes to EPI-attached memory +//! configured to use the address space at 0x10000000 on devices affected by +//! the EPI#01 erratum. Direct access to memory in these cases can cause data +//! corruption depending upon memory accesses immediately before or after the +//! EPI access but using this function will allow EPI accesses to complete +//! correctly. The function is defined as ``inline'' in epi.h. +//! +//! Use of this function on a device not affected by the erratum is safe but +//! will impact performance due to an additional overhead of at least 2 cycles +//! per access. This erratum affects only the 0x10000000 address space +//! typically used to store the LCD controller frame buffer. The 0x60000000 +//! address space is not affected and applications using this address mapping +//! need not use this function. +//! +//! \return None. +// +//***************************************************************************** +extern void EPIWorkaroundByteWrite(uint8_t *pui8Addr, uint8_t ui8Value); + +//***************************************************************************** +// +//! Safely reads a byte from the EPI 0x10000000 address space. +//! +//! \param pui8Addr is the address which is to be read. +//! +//! This function must be used when reading bytes from EPI-attached memory +//! configured to use the address space at 0x10000000 on devices affected by +//! the EPI#01 erratum. Direct access to memory in these cases can cause data +//! corruption depending upon memory accesses immediately before or after the +//! EPI access but using this function will allow EPI accesses to complete +//! correctly. The function is defined as ``inline'' in epi.h. +//! +//! Use of this function on a device not affected by the erratum is safe but +//! will impact performance due to an additional overhead of at least 2 cycles +//! per access. This erratum affects only the 0x10000000 address space +//! typically used to store the LCD controller frame buffer. The 0x60000000 +//! address space is not affected and applications using this address mapping +//! need not use this function. +//! +//! \return The 8-bit byte stored at address \e pui8Addr. +// +//***************************************************************************** +extern uint8_t EPIWorkaroundByteRead(uint8_t *pui8Addr); + +//***************************************************************************** +// +//! Sets the usage mode of the EPI module. +//! +//! \param ui32Base is the EPI module base address. +//! \param ui32Mode is the usage mode of the EPI module. +//! +//! This functions sets the operating mode of the EPI module. The parameter +//! \e ui32Mode must be one of the following: +//! +//! - \b EPI_MODE_GENERAL - use for general-purpose mode operation +//! - \b EPI_MODE_SDRAM - use with SDRAM device +//! - \b EPI_MODE_HB8 - use with host-bus 8-bit interface +//! - \b EPI_MODE_HB16 - use with host-bus 16-bit interface +//! - \b EPI_MODE_DISABLE - disable the EPI module +//! +//! Selection of any of the above modes enables the EPI module, except +//! for \b EPI_MODE_DISABLE, which is used to disable the module. +//! +//! \return None. +// +//***************************************************************************** +void +EPIModeSet(uint32_t ui32Base, uint32_t ui32Mode) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == EPI0_BASE); + ASSERT((ui32Mode == EPI_MODE_GENERAL) || + (ui32Mode == EPI_MODE_SDRAM) || + (ui32Mode == EPI_MODE_HB8) || + (ui32Mode == EPI_MODE_HB16) || + (ui32Mode == EPI_MODE_DISABLE)); + + // + // Write the mode word to the register. + // + HWREG(ui32Base + EPI_O_CFG) = ui32Mode; +} + +//***************************************************************************** +// +//! Sets the clock divider for the EPI module's CS0n/CS1n. +//! +//! \param ui32Base is the EPI module base address. +//! \param ui32Divider is the value of the clock divider to be applied to +//! the external interface (0-65535). +//! +//! This function sets the clock divider(s) that is used to determine the +//! clock rate of the external interface. The \e ui32Divider value is used to +//! derive the EPI clock rate from the system clock based on the following +//! formula. +//! +//! EPIClk = (Divider == 0) ? SysClk : (SysClk / (((Divider / 2) + 1) * 2)) +//! +//! For example, a divider value of 1 results in an EPI clock rate of half +//! the system clock, value of 2 or 3 yields one quarter of the system clock +//! and a value of 4 results in one sixth of the system clock rate. +//! +//! In cases where a dual chip select mode is in use and different clock rates +//! are required for each chip select, the \e ui32Divider parameter must +//! contain two dividers. The lower 16 bits define the divider to be used with +//! CS0n and the upper 16 bits define the divider for CS1n. +//! +//! \return None. +// +//***************************************************************************** +void +EPIDividerSet(uint32_t ui32Base, uint32_t ui32Divider) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == EPI0_BASE); + + // + // Write the divider value to the register. + // + HWREG(ui32Base + EPI_O_BAUD) = ui32Divider; +} + +//***************************************************************************** +// +//! Sets the clock divider for the specified CS in the EPI module. +//! +//! \param ui32Base is the EPI module base address. +//! \param ui32CS is the chip select to modify and has a valid range of 0-3. +//! \param ui32Divider is the value of the clock divider to be applied to +//! the external interface (0-65535). +//! +//! This function sets the clock divider(s) for the specified CS that is used +//! to determine the clock rate of the external interface. The \e ui32Divider +//! value is used to derive the EPI clock rate from the system clock based on +//! the following formula. +//! +//! EPIClk = (Divider == 0) ? SysClk : (SysClk / (((Divider / 2) + 1) * 2)) +//! +//! For example, a divider value of 1 results in an EPI clock rate of half +//! the system clock, value of 2 or 3 yields one quarter of the system clock +//! and a value of 4 results in one sixth of the system clock rate. +//! +//! \note The availability of CS2n and CS3n varies based on the Tiva part +//! in use. Please consult the data sheet to determine if this feature is +//! available. +//! +//! \return None. +// +//***************************************************************************** +void +EPIDividerCSSet(uint32_t ui32Base, uint32_t ui32CS, + uint32_t ui32Divider) +{ + uint32_t ui32Reg; + + // + // Check the arguments. + // + ASSERT(ui32Base == EPI0_BASE); + ASSERT(ui32CS < 4); + + // + // Write the divider value to the register bitfield. + // + if(ui32CS < 2) + { + ui32Reg = HWREG(ui32Base + EPI_O_BAUD) & ~(0xffff << (16 * ui32CS)); + ui32Reg |= ((ui32Divider & 0xffff) << (16 * ui32CS)); + HWREG(ui32Base + EPI_O_BAUD) = ui32Reg; + } + else + { + ui32Reg = (HWREG(ui32Base + EPI_O_BAUD2) & + ~(0xffff << (16 * (ui32CS - 2)))); + ui32Reg |= ((ui32Divider & 0xffff) << (16 * (ui32CS - 2))); + HWREG(ui32Base + EPI_O_BAUD2) = ui32Reg; + } +} + +//***************************************************************************** +// +//! Sets the transfer count for uDMA transmit operations on EPI. +//! +//! \param ui32Base is the EPI module base address. +//! \param ui32Count is the number of units to transmit by uDMA to WRFIFO. +//! +//! This function is used to help configure the EPI uDMA transmit operations. +//! A non-zero transmit count in combination with a FIFO threshold trigger +//! asserts an EPI uDMA transmit. +//! +//! Note that, although the EPI peripheral can handle counts of up to 65535, +//! a single uDMA transfer has a maximum length of 1024 units so \e ui32Count +//! should be set to values less than or equal to 1024. +//! +//! \note The availability of the EPI DMA TX count varies based on the +//! Tiva part in use. Please consult the data sheet to determine if this +//! feature is available. +//! +//! \return None. +// +//***************************************************************************** +void +EPIDMATxCount(uint32_t ui32Base, uint32_t ui32Count) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == EPI0_BASE); + ASSERT(ui32Count <= 1024); + + // + // Assign the DMA TX count value provided. + // + HWREG(ui32Base + EPI_O_DMATXCNT) = ui32Count & 0xffff; +} + +//***************************************************************************** +// +//! Configures the SDRAM mode of operation. +//! +//! \param ui32Base is the EPI module base address. +//! \param ui32Config is the SDRAM interface configuration. +//! \param ui32Refresh is the refresh count in core clocks (0-2047). +//! +//! This function is used to configure the SDRAM interface, when the SDRAM +//! mode is chosen with the function EPIModeSet(). The parameter +//! \e ui32Config is the logical OR of several sets of choices: +//! +//! The processor core frequency must be specified with one of the following: +//! +//! - \b EPI_SDRAM_CORE_FREQ_0_15 defines core clock as 0 MHz < clk <= 15 MHz +//! - \b EPI_SDRAM_CORE_FREQ_15_30 defines core clock as 15 MHz < clk <= 30 MHz +//! - \b EPI_SDRAM_CORE_FREQ_30_50 defines core clock as 30 MHz < clk <= 50 MHz +//! - \b EPI_SDRAM_CORE_FREQ_50_100 defines core clock as 50 MHz < clk <= +//! 100 MHz +//! +//! The low power mode is specified with one of the following: +//! +//! - \b EPI_SDRAM_LOW_POWER enter low power, self-refresh state. +//! - \b EPI_SDRAM_FULL_POWER normal operating state. +//! +//! The SDRAM device size is specified with one of the following: +//! +//! - \b EPI_SDRAM_SIZE_64MBIT size is a 64 Mbit device (8 MB). +//! - \b EPI_SDRAM_SIZE_128MBIT size is a 128 Mbit device (16 MB). +//! - \b EPI_SDRAM_SIZE_256MBIT size is a 256 Mbit device (32 MB). +//! - \b EPI_SDRAM_SIZE_512MBIT size is a 512 Mbit device (64 MB). +//! +//! The parameter \e ui16Refresh sets the refresh counter in units of core +//! clock ticks. It is an 11-bit value with a range of 0 - 2047 counts. +//! +//! \return None. +// +//***************************************************************************** +void +EPIConfigSDRAMSet(uint32_t ui32Base, uint32_t ui32Config, + uint32_t ui32Refresh) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == EPI0_BASE); + ASSERT(ui32Refresh < 2048); + + // + // Fill in the refresh count field of the configuration word. + // + ui32Config &= ~EPI_SDRAMCFG_RFSH_M; + ui32Config |= ui32Refresh << EPI_SDRAMCFG_RFSH_S; + + // + // Write the SDRAM configuration register. + // + HWREG(ui32Base + EPI_O_SDRAMCFG) = ui32Config; +} + +//***************************************************************************** +// +//! Configures the interface for Host-bus 8 operation. +//! +//! \param ui32Base is the EPI module base address. +//! \param ui32Config is the interface configuration. +//! \param ui32MaxWait is the maximum number of external clocks to wait +//! if a FIFO ready signal is holding off the transaction, 0-255. +//! +//! This function is used to configure the interface when used in host-bus 8 +//! operation as chosen with the function EPIModeSet(). The parameter +//! \e ui32Config is the logical OR of the following: +//! +//! - Host-bus 8 submode, select one of: +//! - \b EPI_HB8_MODE_ADMUX sets data and address muxed, AD[7:0] +//! - \b EPI_HB8_MODE_ADDEMUX sets up data and address separate, D[7:0] +//! - \b EPI_HB8_MODE_SRAM as \b EPI_HB8_MODE_ADDEMUX, but uses address +//! switch for multiple reads instead of OEn strobing, D[7:0] +//! - \b EPI_HB8_MODE_FIFO adds XFIFO with sense of XFIFO full and XFIFO +//! empty, D[7:0] +//! +//! - \b EPI_HB8_USE_TXEMPTY enables TXEMPTY signal with FIFO +//! - \b EPI_HB8_USE_RXFULL enables RXFULL signal with FIFO +//! - \b EPI_HB8_WRHIGH sets active high write strobe, otherwise it is +//! active low +//! - \b EPI_HB8_RDHIGH sets active high read strobe, otherwise it is +//! active low +//! +//! - Write wait state when \b EPI_HB8_BAUD is used, select one of: +//! - \b EPI_HB8_WRWAIT_0 sets write wait state to 2 EPI clocks (default) +//! - \b EPI_HB8_WRWAIT_1 sets write wait state to 4 EPI clocks +//! - \b EPI_HB8_WRWAIT_2 sets write wait state to 6 EPI clocks +//! - \b EPI_HB8_WRWAIT_3 sets write wait state to 8 EPI clocks +//! +//! - Read wait state when \b EPI_HB8_BAUD is used, select one of: +//! - \b EPI_HB8_RDWAIT_0 sets read wait state to 2 EPI clocks (default) +//! - \b EPI_HB8_RDWAIT_1 sets read wait state to 4 EPI clocks +//! - \b EPI_HB8_RDWAIT_2 sets read wait state to 6 EPI clocks +//! - \b EPI_HB8_RDWAIT_3 sets read wait state to 8 EPI clocks +//! +//! - \b EPI_HB8_WORD_ACCESS - use Word Access mode to route bytes to the +//! correct byte lanes allowing data to be stored in bits [31:8]. If absent, +//! all data transfers use bits [7:0]. +//! +//! - \b EPI_HB8_CLOCK_GATE_IDLE sets the EPI clock to be held low when no data +//! is available to read or write +//! - \b EPI_HB8_CLOCK_INVERT inverts the EPI clock +//! - \b EPI_HB8_IN_READY_EN sets EPIS032 as a ready/stall signal, active high +//! - \b EPI_HB8_IN_READY_EN_INVERT sets EPIS032 as ready/stall signal, active +//! low +//! - \b EPI_HB8_ALE_HIGH sets the address latch active high (default) +//! - \b EPI_HB8_ALE_LOW sets address latch active low +//! - \b EPI_HB8_CSBAUD use different baud rates when accessing devices on each +//! chip select. CS0n uses the baud rate specified by the lower 16 bits +//! of the divider passed to EPIDividerSet() and CS1n uses the divider passed +//! in the upper 16 bits. If this option is absent, both chip selects use +//! the baud rate resulting from the divider in the lower 16 bits of the +//! parameter passed to EPIDividerSet(). +//! +//! In addition, some parts support CS2n and CS3n for a total of 4 chip +//! selects. If \b EPI_HB8_CSBAUD is configured, EPIDividerCSSet() should be +//! used to to configure the divider for CS2n and CS3n. They both also use the +//! lower 16 bits passed to EPIDividerSet() if this option is absent. +//! +//! The use of \b EPI_HB8_CSBAUD also allows for unique chip select +//! configurations. CS0n, CS1n, CS2n, and CS3n can each be configured by +//! calling EPIConfigHB8CSSet() if \b EPI_HB8_CSBAUD is used. Otherwise, the +//! configuration provided in \e ui32Config is used for all chip selects +//! enabled. +//! +//! - Chip select configuration, select one of: +//! - \b EPI_HB8_CSCFG_CS sets EPIS030 to operate as a chip select signal. +//! - \b EPI_HB8_CSCFG_ALE sets EPIS030 to operate as an address latch +//! (ALE). +//! - \b EPI_HB8_CSCFG_DUAL_CS sets EPIS030 to operate as CS0n and EPIS027 +//! as CS1n with the asserted chip select determined from the most +//! significant address bit for the respective external address map. +//! - \b EPI_HB8_CSCFG_ALE_DUAL_CS sets EPIS030 as an address latch (ALE), +//! EPIS027 as CS0n and EPIS026 as CS1n with the asserted chip select +//! determined from the most significant address bit for the respective +//! external address map. +//! - \b EPI_HB8_CSCFG_ALE_SINGLE_CS sets EPIS030 to operate as an address +//! latch (ALE) and EPIS027 is used as a chip select. +//! - \b EPI_HB8_CSCFG_QUAD_CS sets EPIS030 as CS0n, EPIS027 as CS1n, +//! EPIS034 as CS2n and EPIS033 as CS3n. +//! - \b EPI_HB8_CSCFG_ALE_QUAD_CS sets EPIS030 as an address latch (ALE), +//! EPIS026 as CS0n, EPIS027 as CS1n, EPIS034 as CS2n and EPIS033 as CS3n. +//! \note Dual or quad chip select configurations cannot be used with +//! EPI_HB8_MODE_SRAM. +//! +//! The parameter \e ui32MaxWait is used if the FIFO mode is chosen. If a +//! FIFO is used aint32_t with RXFULL or TXEMPTY ready signals, then this +//! parameter determines the maximum number of clocks to wait when the +//! transaction is being held off by by the FIFO using one of these ready +//! signals. A value of 0 means to wait forever. +//! +//! \note Availability of configuration options varies based on the Tiva +//! part in use. Please consult the data sheet to determine if the features +//! desired are available. +//! +//! \return None. +// +//***************************************************************************** +void +EPIConfigHB8Set(uint32_t ui32Base, uint32_t ui32Config, + uint32_t ui32MaxWait) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == EPI0_BASE); + ASSERT(ui32MaxWait < 256); + + // + // Determine the CS and word access modes. + // + HWREG(ui32Base + EPI_O_HB8CFG2) = + ((ui32Config & EPI_HB8_CSBAUD) ? EPI_HB8CFG2_CSBAUD : 0) | + ((ui32Config & EPI_HB8_CSCFG_MASK) << 15); + + // + // Fill in the max wait field of the configuration word. + // + ui32Config &= ~EPI_HB8CFG_MAXWAIT_M; + ui32Config |= ui32MaxWait << EPI_HB8CFG_MAXWAIT_S; + + // + // Write the main HostBus8 configuration register. + // + HWREG(ui32Base + EPI_O_HB8CFG) = ui32Config; +} + +//***************************************************************************** +// +//! Configures the interface for Host-bus 16 operation. +//! +//! \param ui32Base is the EPI module base address. +//! \param ui32Config is the interface configuration. +//! \param ui32MaxWait is the maximum number of external clocks to wait +//! if a FIFO ready signal is holding off the transaction. +//! +//! This function is used to configure the interface when used in Host-bus 16 +//! operation as chosen with the function EPIModeSet(). The parameter +//! \e ui32Config is the logical OR of the following: +//! - Host-bus 16 submode, select one of: +//! - \b EPI_HB16_MODE_ADMUX sets data and address muxed, AD[15:0]. +//! - \b EPI_HB16_MODE_ADDEMUX sets up data and address as separate, +//! D[15:0]. +//! - \b EPI_HB16_MODE_SRAM sets as \b EPI_HB16_MODE_ADDEMUX but uses +//! address switch for multiple reads instead of OEn strobing, D[15:0]. +//! - \b EPI_HB16_MODE_FIFO addes XFIFO controls with sense of XFIFO full +//! and XFIFO empty, D[15:0]. This submode uses no address or ALE. +//! +//! - \b EPI_HB16_USE_TXEMPTY enables TXEMPTY signal with FIFO. +//! - \b EPI_HB16_USE_RXFULL enables RXFULL signal with FIFO. +//! - \b EPI_HB16_WRHIGH use active high write strobe, otherwise it is +//! active low. +//! - \b EPI_HB16_RDHIGH use active high read strobe, otherwise it is +//! active low. +//! - Write wait state, select one of: +//! - \b EPI_HB16_WRWAIT_0 sets write wait state to 2 EPI clocks. +//! - \b EPI_HB16_WRWAIT_1 sets write wait state to 4 EPI clocks. +//! - \b EPI_HB16_WRWAIT_2 sets write wait state to 6 EPI clocks. +//! - \b EPI_HB16_WRWAIT_3 sets write wait state to 8 EPI clocks. +//! +//! - Read wait state, select one of: +//! - \b EPI_HB16_RDWAIT_0 sets read wait state to 2 EPI clocks. +//! - \b EPI_HB16_RDWAIT_1 sets read wait state to 4 EPI clocks. +//! - \b EPI_HB16_RDWAIT_2 sets read wait state to 6 EPI clocks. +//! - \b EPI_HB16_RDWAIT_3 sets read wait state to 8 EPI clocks. +//! +//! - \b EPI_HB16_WORD_ACCESS use Word Access mode to route bytes to the +//! correct byte lanes allowing data to be stored in bits [31:16]. If +//! absent, all data transfers use bits [15:0]. +//! +//! \note \b EPI_HB16_WORD_ACCESS is not available on all parts. Please +//! consult the data sheet to determine if this feature is available. +//! +//! - \b EPI_HB16_CLOCK_GATE_IDLE holds the EPI clock low when no data is +//! available to read or write. +//! - \b EPI_HB16_CLOCK_INVERT inverts the EPI clock. +//! - \b EPI_HB16_IN_READY_EN sets EPIS032 as a ready/stall signal, active +//! high. +//! - \b EPI_HB16_IN_READY_EN_INVERTED sets EPIS032 as ready/stall signal, +//! active low. +//! - Address latch logic, select one of: +//! - \b EPI_HB16_ALE_HIGH sets the address latch active high (default). +//! - \b EPI_HB16_ALE_LOW sets address latch active low. +//! +//! - \b EPI_HB16_BURST_TRAFFIC enables burst traffic. Only valid with +//! \b EPI_HB16_MODE_ADMUX and a chip select configuration that utilizes an +//! ALE. +//! - \b EPI_HB16_BSEL enables byte selects. In this mode, two EPI signals +//! operate as byte selects allowing 8-bit transfers. If this flag is not +//! specified, data must be read and written using only 16-bit transfers. +//! - \b EPI_HB16_CSBAUD use different baud rates when accessing devices +//! on each chip select. CS0n uses the baud rate specified by the lower 16 +//! bits of the divider passed to EPIDividerSet() and CS1n uses the divider +//! passed in the upper 16 bits. If this option is absent, both chip selects +//! use the baud rate resulting from the divider in the lower 16 bits of the +//! parameter passed to EPIDividerSet(). +//! +//! In addition, some parts support CS2n and CS3n for a total of 4 chip +//! selects. If \b EPI_HB16_CSBAUD is configured, EPIDividerCSSet() should be +//! used to to configure the divider for CS2n and CS3n. They both also use the +//! lower 16 bits passed to EPIDividerSet() if this option is absent. +//! +//! The use of \b EPI_HB16_CSBAUD also allows for unique chip select +//! configurations. CS0n, CS1n, CS2n, and CS3n can each be configured by +//! calling EPIConfigHB16CSSet() if \b EPI_HB16_CSBAUD is used. Otherwise, the +//! configuration provided in \e ui32Config is used for all chip selects. +//! +//! - Chip select configuration, select one of: +//! - \b EPI_HB16_CSCFG_CS sets EPIS030 to operate as a chip select signal. +//! - \b EPI_HB16_CSCFG_ALE sets EPIS030 to operate as an address latch +//! (ALE). +//! - \b EPI_HB16_CSCFG_DUAL_CS sets EPIS030 to operate as CS0n and EPIS027 +//! as CS1n with the asserted chip select determined from the most +//! significant address bit for the respective external address map. +//! - \b EPI_HB16_CSCFG_ALE_DUAL_CS sets EPIS030 as an address latch (ALE), +//! EPIS027 as CS0n and EPIS026 as CS1n with the asserted chip select +//! determined from the most significant address bit for the respective +//! external address map. +//! - \b EPI_HB16_CSCFG_ALE_SINGLE_CS sets EPIS030 to operate as an address +//! latch (ALE) and EPIS027 is used as a chip select. +//! - \b EPI_HB16_CSCFG_QUAD_CS sets EPIS030 as CS0n, EPIS027 as CS1n, +//! EPIS034 as CS2n and EPIS033 as CS3n. +//! - \b EPI_HB16_CSCFG_ALE_QUAD_CS sets EPIS030 as an address latch +//! (ALE), EPIS026 as CS0n, EPIS027 as CS1n, EPIS034 as CS2n and EPIS033 +//! as CS3n. +//! \note Dual or quad chip select configurations cannot be used with +//! EPI_HB16_MODE_SRAM. +//! +//! The parameter \e ui32MaxWait is used if the FIFO mode is chosen. If a +//! FIFO is used along with RXFULL or TXEMPTY ready signals, then this +//! parameter determines the maximum number of clocks to wait when the +//! transaction is being held off by by the FIFO using one of these ready +//! signals. A value of 0 means to wait forever. +//! +//! \note Availability of configuration options varies based on the Tiva +//! part in use. Please consult the data sheet to determine if the features +//! desired are available. +//! +//! \return None. +// +//***************************************************************************** +void +EPIConfigHB16Set(uint32_t ui32Base, uint32_t ui32Config, uint32_t ui32MaxWait) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == EPI0_BASE); + ASSERT(ui32MaxWait < 256); + + // + // Determine the CS and word access modes. + // + HWREG(ui32Base + EPI_O_HB16CFG2) = + ((ui32Config & EPI_HB16_CSBAUD) ? EPI_HB16CFG2_CSBAUD : 0) | + ((ui32Config & EPI_HB16_CSCFG_MASK) << 15); + + // + // Fill in the max wait field of the configuration word. + // + ui32Config &= ~EPI_HB16CFG_MAXWAIT_M; + ui32Config |= ui32MaxWait << EPI_HB16CFG_MAXWAIT_S; + + // + // Write the main HostBus16 configuration register. + // + HWREG(ui32Base + EPI_O_HB16CFG) = ui32Config; +} + +//***************************************************************************** +// +//! Sets the individual chip select configuration for the Host-bus 8 interface. +//! +//! \param ui32Base is the EPI module base address. +//! \param ui32CS is the chip select value to configure. +//! \param ui32Config is the configuration settings. +//! +//! This function is used to configure individual chip select settings for the +//! Host-bus 8 interface mode. EPIConfigHB8Set() must have been setup with +//! the \b EPI_HB8_CSBAUD flag for the individual chip select configuration +//! option to be available. +//! +//! The \e ui32Base parameter is the base address for the EPI hardware module. +//! The \e ui32CS parameter specifies the chip select to configure and has a +//! valid range of 0-3. The parameter \e ui32Config is the logical OR of the +//! following: +//! +//! - Host-bus 8 submode, select one of: +//! - \b EPI_HB8_MODE_ADMUX sets data and address muxed, AD[7:0]. +//! - \b EPI_HB8_MODE_ADDEMUX sets up data and address separate, D[7:0]. +//! - \b EPI_HB8_MODE_SRAM as \b EPI_HB8_MODE_ADDEMUX, but uses address +//! switch for multiple reads instead of OEn strobing, D[7:0]. +//! - \b EPI_HB8_MODE_FIFO adds XFIFO with sense of XFIFO full and XFIFO +//! empty, D[7:0]. This is only available for CS0n and CS1n. +//! +//! - \b EPI_HB8_WRHIGH sets active high write strobe, otherwise it is +//! active low. +//! - \b EPI_HB8_RDHIGH sets active high read strobe, otherwise it is +//! active low. +//! - Write wait state when \b EPI_HB8_BAUD is used, select one of: +//! - \b EPI_HB8_WRWAIT_0 sets write wait state to 2 EPI clocks (default). +//! - \b EPI_HB8_WRWAIT_1 sets write wait state to 4 EPI clocks. +//! - \b EPI_HB8_WRWAIT_2 sets write wait state to 6 EPI clocks. +//! - \b EPI_HB8_WRWAIT_3 sets write wait state to 8 EPI clocks. +//! - Read wait state when \b EPI_HB8_BAUD is used, select one of: +//! - \b EPI_HB8_RDWAIT_0 sets read wait state to 2 EPI clocks (default). +//! - \b EPI_HB8_RDWAIT_1 sets read wait state to 4 EPI clocks. +//! - \b EPI_HB8_RDWAIT_2 sets read wait state to 6 EPI clocks. +//! - \b EPI_HB8_RDWAIT_3 sets read wait state to 8 EPI clocks. +//! - \b EPI_HB8_ALE_HIGH sets the address latch active high (default). +//! - \b EPI_HB8_ALE_LOW sets address latch active low. +//! +//! \note The availability of a unique chip select configuration within +//! Host-bus 8 interface mode varies based on the Tiva part in use. +//! Please consult the data sheet to determine if this feature is available. +//! +//! \return None. +// +//***************************************************************************** +void +EPIConfigHB8CSSet(uint32_t ui32Base, uint32_t ui32CS, uint32_t ui32Config) +{ + uint32_t ui32Offset, ui32Reg; + + // + // Check the arguments. + // + ASSERT(ui32Base == EPI0_BASE); + ASSERT(ui32CS < 4); + + // + // Determine the register offset based on the ui32CS provided. + // + if(ui32CS < 2) + { + ui32Offset = EPI_O_HB8CFG + (ui32CS << 2); + } + else + { + ui32Offset = EPI_O_HB8CFG3 + ((ui32CS - 2) << 2); + } + + // + // Preserve the bits that will not be modified. + // + ui32Reg = HWREG(ui32Base + ui32Offset) & ~EPI_HB8_CS_MASK; + + // + // Write the target chip select HostBus8 configuration fields. + // + HWREG(ui32Base + ui32Offset) = (ui32Reg | ui32Config); +} + +//***************************************************************************** +// +//! Sets the individual chip select configuration for the Host-bus 16 +//! interface. +//! +//! \param ui32Base is the EPI module base address. +//! \param ui32CS is the chip select value to configure. +//! \param ui32Config is the configuration settings. +//! +//! This function is used to configure individual chip select settings for the +//! Host-bus 16 interface mode. EPIConfigHB16Set() must have been set up with +//! the \b EPI_HB16_CSBAUD flag for the individual chip select configuration +//! option to be available. +//! +//! The \e ui32Base parameter is the base address for the EPI hardware module. +//! The \e ui32CS parameter specifies the chip select to configure and has a +//! valid range of 0-3. The parameter \e ui32Config is the logical OR the +//! following: +//! +//! - Host-bus 16 submode, select one of: +//! - \b EPI_HB16_MODE_ADMUX sets data and address muxed, AD[15:0]. +//! - \b EPI_HB16_MODE_ADDEMUX sets up data and address separate, D[15:0]. +//! - \b EPI_HB16_MODE_SRAM same as \b EPI_HB8_MODE_ADDEMUX, but uses +//! address switch for multiple reads instead of OEn strobing, D[15:0]. +//! - \b EPI_HB16_MODE_FIFO adds XFIFO with sense of XFIFO full and XFIFO +//! empty, D[15:0]. This feature is only available on CS0n and CS1n. +//! - \b EPI_HB16_WRHIGH sets active high write strobe, otherwise it is +//! active low. +//! - \b EPI_HB16_RDHIGH sets active high read strobe, otherwise it is +//! active low. +//! - Write wait state when \b EPI_HB16_BAUD is used, select one of: +//! - \b EPI_HB16_WRWAIT_0 sets write wait state to 2 EPI clocks (default). +//! - \b EPI_HB16_WRWAIT_1 sets write wait state to 4 EPI clocks. +//! - \b EPI_HB16_WRWAIT_2 sets write wait state to 6 EPI clocks. +//! - \b EPI_HB16_WRWAIT_3 sets write wait state to 8 EPI clocks. +//! - Read wait state when \b EPI_HB16_BAUD is used, select one of: +//! - \b EPI_HB16_RDWAIT_0 sets read wait state to 2 EPI clocks (default). +//! - \b EPI_HB16_RDWAIT_1 sets read wait state to 4 EPI clocks. +//! - \b EPI_HB16_RDWAIT_2 sets read wait state to 6 EPI clocks. +//! - \b EPI_HB16_RDWAIT_3 sets read wait state to 8 EPI clocks. +//! - \b EPI_HB16_ALE_HIGH sets the address latch active high (default). +//! - \b EPI_HB16_ALE_LOW sets address latch active low. +//! - \b EPI_HB16_BURST_TRAFFIC enables burst traffic. Only valid with +//! \b EPI_HB16_MODE_ADMUX and a chip select configuration that utilizes an +//! ALE. +//! +//! \note The availability of the unique chip select configuration within the +//! Host-bus 16 interface mode varies based on the Tiva part in use. +//! Please consult the data sheet to determine if this feature is available. +//! +//! \return None. +// +//***************************************************************************** +void +EPIConfigHB16CSSet(uint32_t ui32Base, uint32_t ui32CS, uint32_t ui32Config) +{ + uint32_t ui32Offset, ui32Reg; + + // + // Check the arguments. + // + ASSERT(ui32Base == EPI0_BASE); + ASSERT(ui32CS < 4); + + // + // Determine the register offset based on the ui32CS provided. + // + if(ui32CS < 2) + { + ui32Offset = EPI_O_HB16CFG + (ui32CS << 2); + } + else + { + ui32Offset = EPI_O_HB16CFG3 + ((ui32CS - 2) << 2); + } + + // + // Preserve the bits that will not be modified. + // + ui32Reg = HWREG(ui32Base + ui32Offset) & ~EPI_HB16_CS_MASK; + + // + // Write the target chip select HostBus16 configuration fields. + // + HWREG(ui32Base + ui32Offset) = (ui32Reg | ui32Config); +} + +//***************************************************************************** +// +//! Sets the individual chip select timing settings for the Host-bus 8 +//! interface. +//! +//! \param ui32Base is the EPI module base address. +//! \param ui32CS is the chip select value to configure. +//! \param ui32Config is the configuration settings. +//! +//! This function is used to set individual chip select timings for the +//! Host-bus 8 interface mode. +//! +//! The \e ui32Base parameter is the base address for the EPI hardware module. +//! The \e ui32CS parameter specifies the chip select to configure and has a +//! valid range of 0-3. The parameter \e ui32Config is the logical OR of the +//! following: +//! +//! - Input ready stall delay, select one of: +//! - \b EPI_HB8_IN_READY_DELAY_1 sets the stall on input ready (EPIS032) +//! to start 1 EPI clock after signaled. +//! - \b EPI_HB8_IN_READY_DELAY_2 sets the stall on input ready (EPIS032) +//! to start 2 EPI clocks after signaled. +//! - \b EPI_HB8_IN_READY_DELAY_3 sets the stall on input ready (EPIS032) +//! to start 3 EPI clocks after signaled. +//! +//! - Host bus transfer delay, select one of: +//! - \b EPI_HB8_CAP_WIDTH_1 defines the inter-transfer capture width to +//! create a delay of 1 EPI clock. +//! - \b EPI_HB8_CAP_WIDTH_2 defines the inter-transfer capture width +//! to create a delay of 2 EPI clocks. +//! +//! - \b EPI_HB8_WRWAIT_MINUS_DISABLE disables the additional write wait state +//! reduction. +//! - \b EPI_HB8_WRWAIT_MINUS_ENABLE enables a 1 EPI clock write wait state +//! reduction. +//! - \b EPI_HB8_RDWAIT_MINUS_DISABLE disables the additional read wait state +//! reduction. +//! - \b EPI_HB8_RDWAIT_MINUS_ENABLE enables a 1 EPI clock read wait state +//!reduction. +//! +//! \note The availability of unique chip select timings within Host-bus 8 +//! interface mode varies based on the Tiva part in use. Please consult +//! the data sheet to determine if this feature is available. +//! +//! \return None. +// +//***************************************************************************** +void +EPIConfigHB8TimingSet(uint32_t ui32Base, uint32_t ui32CS, uint32_t ui32Config) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == EPI0_BASE); + ASSERT(ui32CS < 4); + + // + // Write the target chip select HostBus8 timing register. + // + HWREG(ui32Base + (EPI_O_HB8TIME + (ui32CS << 2))) = ui32Config; +} + +//***************************************************************************** +// +//! Sets the individual chip select timing settings for the Host-bus 16 +//! interface. +//! +//! \param ui32Base is the EPI module base address. +//! \param ui32CS is the chip select value to configure. +//! \param ui32Config is the configuration settings. +//! +//! This function is used to set individual chip select timings for the +//! Host-bus 16 interface mode. +//! +//! The \e ui32Base parameter is the base address for the EPI hardware module. +//! The \e ui32CS parameter specifies the chip select to configure and has a +//! valid range of 0-3. The parameter \e ui32Config is the logical OR of the +//! following: +//! +//! - Input ready stall delay, select one of: +//! - \b EPI_HB16_IN_READY_DELAY_1 sets the stall on input ready (EPIS032) +//! to start 1 EPI clock after signaled. +//! - \b EPI_HB16_IN_READY_DELAY_2 sets the stall on input ready (EPIS032) +//! to start 2 EPI clocks after signaled. +//! - \b EPI_HB16_IN_READY_DELAY_3 sets the stall on input ready (EPIS032) +//! to start 3 EPI clocks after signaled. +//! +//! - PSRAM size limitation, select one of: +//! - \b EPI_HB16_PSRAM_NO_LIMIT defines no row size limitation. +//! - \b EPI_HB16_PSRAM_128 defines the PSRAM row size to 128 bytes. +//! - \b EPI_HB16_PSRAM_256 defines the PSRAM row size to 256 bytes. +//! - \b EPI_HB16_PSRAM_512 defines the PSRAM row size to 512 bytes. +//! - \b EPI_HB16_PSRAM_1024 defines the PSRAM row size to 1024 bytes. +//! - \b EPI_HB16_PSRAM_2048 defines the PSRAM row size to 2048 bytes. +//! - \b EPI_HB16_PSRAM_4096 defines the PSRAM row size to 4096 bytes. +//! - \b EPI_HB16_PSRAM_8192 defines the PSRAM row size to 8192 bytes. +//! +//! - Host bus transfer delay, select one of: +//! - \b EPI_HB16_CAP_WIDTH_1 defines the inter-transfer capture width to +//! create a delay of 1 EPI clock +//! - \b EPI_HB16_CAP_WIDTH_2 defines the inter-transfer capture width +//! to create a delay of 2 EPI clocks. +//! +//! - Write wait state timing reduction, select one of: +//! - \b EPI_HB16_WRWAIT_MINUS_DISABLE disables the additional write wait +//! state reduction. +//! - \b EPI_HB16_WRWAIT_MINUS_ENABLE enables a 1 EPI clock write wait +//! state reduction. +//! +//! - Read wait state timing reduction, select one of: +//! - \b EPI_HB16_RDWAIT_MINUS_DISABLE disables the additional read wait +//! state reduction. +//! - \b EPI_HB16_RDWAIT_MINUS_ENABLE enables a 1 EPI clock read wait state +//! reduction. +//! +//! \note The availability of unique chip select timings within Host-bus 16 +//! interface mode varies based on the Tiva part in use. Please consult +//! the data sheet to determine if this feature is available. +//! +//! \return None. +// +//***************************************************************************** +void +EPIConfigHB16TimingSet(uint32_t ui32Base, uint32_t ui32CS, uint32_t ui32Config) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == EPI0_BASE); + ASSERT(ui32CS < 4); + + // + // Write the target chip select HostBus16 timing register. + // + HWREG(ui32Base + (EPI_O_HB16TIME + (ui32CS << 2))) = ui32Config; +} + +//***************************************************************************** +// +//! Sets the PSRAM configuration register. +//! +//! \param ui32Base is the EPI module base address. +//! \param ui32CS is the chip select target. +//! \param ui32CR is the PSRAM configuration register value. +//! +//! This function sets the PSRAM's configuration register by using the PSRAM +//! configuration register enable signal. The Host-bus 16 interface mode +//! should be configured prior to calling this function. +//! +//! The \e ui32Base parameter is the base address for the EPI hardware module. +//! The \e ui32CS parameter specifies the chip select to configure and has a +//! valid range of 0-3. The parameter \e ui32CR value is determined by +//! consulting the PSRAM's data sheet. +//! +//! \note The availability of PSRAM support varies based on the Tiva part +//! in use. Please consult the data sheet to determine if this feature is +//! available. +//! +//! \return None. +// +//***************************************************************************** +void +EPIPSRAMConfigRegSet(uint32_t ui32Base, uint32_t ui32CS, uint32_t ui32CR) +{ + uint32_t ui32Offset; + + // + // Check the arguments. + // + ASSERT(ui32Base == EPI0_BASE); + ASSERT(ui32CS < 4); + + // + // Determine the register offset based on the ui32CS provided. + // + if(ui32CS < 2) + { + ui32Offset = EPI_O_HB16CFG + (ui32CS << 2); + } + else + { + ui32Offset = EPI_O_HB16CFG3 + ((ui32CS - 2) << 2); + } + + // + // Setup for the PSRAM configuration register write. Only 21 bits are + // valid on a write. + // + HWREG(ui32Base + EPI_O_HBPSRAM) = (ui32CR & 0x1fffff); + + // + // Set the PSRAM configuration register write enable. + // + HWREG(ui32Base + ui32Offset) |= EPI_HB16CFG_WRCRE; +} + +//***************************************************************************** +// +//! Requests a configuration register read from the PSRAM. +//! +//! \param ui32Base is the EPI module base address. +//! \param ui32CS is the chip select target. +//! +//! This function requests a read of the PSRAM's configuration register. The +//! Host-bus 16 interface mode should be configured prior to calling this +//! function. +//! The EPIPSRAMConfigRegGet() and EPIPSRAMConfigRegGetNonBlocking() can +//! be used to retrieve the configuration register value. +//! +//! The \e ui32Base parameter is the base address for the EPI hardware module. +//! The \e ui32CS parameter specifies the chip select to configure and has a +//! valid range of 0-3. +//! +//! \note The availability of PSRAM support varies based on the Tiva part +//! in use. Please consult the data sheet to determine if this feature is +//! available. +//! +//! \return none. +// +//***************************************************************************** +void +EPIPSRAMConfigRegRead(uint32_t ui32Base, uint32_t ui32CS) +{ + uint32_t ui32Offset; + + // + // Check the arguments. + // + ASSERT(ui32Base == EPI0_BASE); + ASSERT(ui32CS < 4); + + // + // Determine the register offset based on the ui32CS provided. + // + if(ui32CS < 2) + { + ui32Offset = EPI_O_HB16CFG + (ui32CS << 2); + } + else + { + ui32Offset = EPI_O_HB16CFG3 + ((ui32CS - 2) << 2); + } + + // + // Set the PSRAM configuration register read enable. + // + HWREG(ui32Base + ui32Offset) |= EPI_HB16CFG_RDCRE; +} + +//***************************************************************************** +// +//! Retrieves the contents of the EPI PSRAM configuration register. +//! +//! \param ui32Base is the EPI module base address. +//! \param ui32CS is the chip select target. +//! \param pui32CR is the provided storage used to hold the register value. +//! +//! This function copies the contents of the EPI PSRAM configuration register +//! to the provided storage if the PSRAM read configuration register enable +//! is no longer asserted. Otherwise the provided storage is not modified. +//! +//! The Host-bus 16 interface mode should be set up and EPIPSRAMConfigRegRead() +//! should be called prior to calling this function. +//! +//! The \e ui32Base parameter is the base address for the EPI hardware module. +//! The \e ui32CS parameter specifies the chip select to configure and has a +//! valid range of 0-3. The \e pui32CR parameter is a pointer to provided +//! storage used to hold the register value. +//! +//! \note The availability of PSRAM support varies based on the Tiva part +//! in use. Please consult the data sheet to determine if this feature is +//! available. +//! +//! \return \b true if the value was copied to the provided storage and +//! \b false if it was not. +// +//***************************************************************************** +bool +EPIPSRAMConfigRegGetNonBlocking(uint32_t ui32Base, uint32_t ui32CS, + uint32_t *pui32CR) +{ + uint32_t ui32Offset; + + // + // Check the arguments. + // + ASSERT(ui32Base == EPI0_BASE); + ASSERT(ui32CS < 4); + + // + // Determine the register offset based on the ui32CS provided. + // + if(ui32CS < 2) + { + ui32Offset = EPI_O_HB16CFG + (ui32CS << 2); + } + else + { + ui32Offset = EPI_O_HB16CFG3 + ((ui32CS - 2) << 2); + } + + // + // Verify PSRAM read enable is not asserted. + // + if(HWREG(ui32Base + ui32Offset) & EPI_HB16CFG_RDCRE) + { + return(false); + } + + // + // Copy the PSRAM configuration register value to the provided storage. + // Only the lower 16 bits are valid on a read. + // + *pui32CR = HWREG(ui32Base + EPI_O_HBPSRAM) & 0xffff; + + // + // Notify caller the provided storage holds the EPI PSRAM configuration + // register contents. + // + return(true); +} + +//***************************************************************************** +// +//! Retrieves the contents of the EPI PSRAM configuration register. +//! +//! \param ui32Base is the EPI module base address. +//! \param ui32CS is the chip select target. +//! +//! This function retrieves the EPI PSRAM configuration register. The register +//! is read once the EPI PSRAM configuration register read enable signal is +//! de-asserted. +//! +//! The Host-bus 16 interface mode should be set up and EPIPSRAMConfigRegRead() +//! should be called prior to calling this function. +//! +//! The \e ui32Base parameter is the base address for the EPI hardware module. +//! The \e ui32CS parameter specifies the chip select to configure and has a +//! valid range of 0-3. +//! +//! \note The availability of PSRAM support varies based on the Tiva part +//! in use. Please consult the data sheet to determine if this feature is +//! available. +//! +//! \return none. +// +//***************************************************************************** +uint32_t +EPIPSRAMConfigRegGet(uint32_t ui32Base, uint32_t ui32CS) +{ + uint32_t ui32Offset; + + // + // Check the arguments. + // + ASSERT(ui32Base == EPI0_BASE); + ASSERT(ui32CS < 4); + + // + // Determine the register offset based on the ui32CS provided. + // + if(ui32CS < 2) + { + ui32Offset = EPI_O_HB16CFG + (ui32CS << 2); + } + else + { + ui32Offset = EPI_O_HB16CFG3 + ((ui32CS - 2) << 2); + } + + // + // Wait for PSRAM read enable to deassert if necessary. + // + while(HWREG(ui32Base + ui32Offset) & EPI_HB16CFG_RDCRE) + { + } + + // + // Return the EPI PSRAM configuration register contents. + // Only the lower 16 bits are valid on a read. + // + return(HWREG(ui32Base + EPI_O_HBPSRAM) & 0xffff); +} + +//***************************************************************************** +// +//! Configures the interface for general-purpose mode operation. +//! +//! \param ui32Base is the EPI module base address. +//! \param ui32Config is the interface configuration. +//! \param ui32FrameCount is the frame size in clocks, if the frame signal +//! is used (0-15). +//! \param ui32MaxWait is currently not used. +//! +//! This function is used to configure the interface when used in +//! general-purpose operation as chosen with the function EPIModeSet(). The +//! parameter \e ui32Config is the logical OR of the following: +//! +//! - \b EPI_GPMODE_CLKPIN interface clock as output on a pin. +//! - \b EPI_GPMODE_CLKGATE clock is stopped when there is no transaction, +//! otherwise it is free-running. +//! - \b EPI_GPMODE_FRAME50 framing signal is 50/50 duty cycle, otherwise it +//! is a pulse. +//! - \b EPI_GPMODE_WRITE2CYCLE a two-cycle write is used, otherwise a +//! single-cycle write is used. +//! - Address bus size, select one of: +//! - \b EPI_GPMODE_ASIZE_NONE sets no address bus. +//! - \b EPI_GPMODE_ASIZE_4 sets an address bus size of 4 bits. +//! - \b EPI_GPMODE_ASIZE_12 sets an address bus size of 12 bits. +//! - \b EPI_GPMODE_ASIZE_20 sets an address bus size of 20 bits. +//! - Data bus size, select one of: +//! - \b EPI_GPMODE_DSIZE_8 sets a data bus size of 8 bits. +//! - \b EPI_GPMODE_DSIZE_16 sets a data bus size of 16 bits. +//! - \b EPI_GPMODE_DSIZE_24 sets a data bus size of 24 bits. +//! - \b EPI_GPMODE_DSIZE_32 sets a data bus size of 32 bits. +//! +//! The parameter \e ui32FrameCount is the number of clocks used to form the +//! framing signal, if the framing signal is used. The behavior depends on +//! whether the frame signal is a pulse or a 50/50 duty cycle. +//! +//! +//! \return None. +// +//***************************************************************************** +void +EPIConfigGPModeSet(uint32_t ui32Base, uint32_t ui32Config, + uint32_t ui32FrameCount, uint32_t ui32MaxWait) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == EPI0_BASE); + ASSERT(ui32FrameCount < 16); + ASSERT(ui32MaxWait < 256); + + // + // Fill in the frame count field of the configuration word. + // + ui32Config &= ~EPI_GPCFG_FRMCNT_M; + ui32Config |= ui32FrameCount << EPI_GPCFG_FRMCNT_S; + + // + // Write the non-moded configuration register. + // + HWREG(ui32Base + EPI_O_GPCFG) = ui32Config; +} + +//***************************************************************************** +// +//! Configures the address map for the external interface. +//! +//! \param ui32Base is the EPI module base address. +//! \param ui32Map is the address mapping configuration. +//! +//! This function is used to configure the address mapping for the external +//! interface, which then determines the base address of the external memory or +//! device within the processor peripheral and/or memory space. +//! +//! The parameter \e ui32Map is the logical OR of the following: +//! +//! - Peripheral address space size, select one of: +//! - \b EPI_ADDR_PER_SIZE_256B sets the peripheral address space to 256 +//! bytes. +//! - \b EPI_ADDR_PER_SIZE_64KB sets the peripheral address space to 64 +//! Kbytes. +//! - \b EPI_ADDR_PER_SIZE_16MB sets the peripheral address space to 16 +//! Mbytes. +//! - \b EPI_ADDR_PER_SIZE_256MB sets the peripheral address space to 256 +//! Mbytes. +//! - Peripheral base address, select one of: +//! - \b EPI_ADDR_PER_BASE_NONE sets the peripheral base address to none. +//! - \b EPI_ADDR_PER_BASE_A sets the peripheral base address to +//! 0xA0000000. +//! - \b EPI_ADDR_PER_BASE_C sets the peripheral base address to +//! 0xC0000000. +//! - RAM address space, select one of: +//! - \b EPI_ADDR_RAM_SIZE_256B sets the RAM address space to 256 bytes. +//! - \b EPI_ADDR_RAM_SIZE_64KB sets the RAM address space to 64 Kbytes. +//! - \b EPI_ADDR_RAM_SIZE_16MB sets the RAM address space to 16 Mbytes. +//! - \b EPI_ADDR_RAM_SIZE_256MB sets the RAM address space to 256 Mbytes. +//! - RAM base address, select one of: +//! - \b EPI_ADDR_RAM_BASE_NONE sets the RAM space address to none. +//! - \b EPI_ADDR_RAM_BASE_6 sets the RAM space address to 0x60000000. +//! - \b EPI_ADDR_RAM_BASE_8 sets the RAM space address to 0x80000000. +//! - \b EPI_ADDR_RAM_QUAD_MODE maps CS0n to 0x60000000, CS1n to 0x80000000, +//! CS2n to 0xA0000000, and CS3n to 0xC0000000. +//! - \b EPI_ADDR_CODE_SIZE_256B sets an external code size of 256 bytes, range +//! 0x00 to 0xFF. +//! - \b EPI_ADDR_CODE_SIZE_64KB sets an external code size of 64 Kbytes, range +//! 0x0000 to 0xFFFF. +//! - \b EPI_ADDR_CODE_SIZE_16MB sets an external code size of 16 Mbytes, range +//! 0x000000 to 0xFFFFFF. +//! - \b EPI_ADDR_CODE_SIZE_256MB sets an external code size of 256 Mbytes, +//! range 0x0000000 to 0xFFFFFFF. +//! - \b EPI_ADDR_CODE_BASE_NONE sets external code base to not mapped. +//! - \b EPI_ADDR_CODE_BASE_1 sets external code base to 0x10000000. +//! +//! \note The availability of \b EPI_ADDR_RAM_QUAD_MODE and \b EPI_ADDR_CODE_* +//! varies based on the Tiva part in use. Please consult the data sheet +//! to determine if these features are available. +//! +//! \return None. +// +//***************************************************************************** +void +EPIAddressMapSet(uint32_t ui32Base, uint32_t ui32Map) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == EPI0_BASE); + ASSERT(ui32Map < 0x1000); + + // + // Set the value of the address mapping register. + // + HWREG(ui32Base + EPI_O_ADDRMAP) = ui32Map; +} + +//***************************************************************************** +// +//! Configures a non-blocking read transaction. +//! +//! \param ui32Base is the EPI module base address. +//! \param ui32Channel is the read channel (0 or 1). +//! \param ui32DataSize is the size of the data items to read. +//! \param ui32Address is the starting address to read. +//! +//! This function is used to configure a non-blocking read channel for a +//! transaction. Two channels are available that can be used in a ping-pong +//! method for continuous reading. It is not necessary to use both channels +//! to perform a non-blocking read. +//! +//! The parameter \e ui8DataSize is one of \b EPI_NBCONFIG_SIZE_8, +//! \b EPI_NBCONFIG_SIZE_16, or \b EPI_NBCONFIG_SIZE_32 for 8-bit, 16-bit, +//! or 32-bit sized data transfers. +//! +//! The parameter \e ui32Address is the starting address for the read, relative +//! to the external device. The start of the device is address 0. +//! +//! Once configured, the non-blocking read is started by calling +//! EPINonBlockingReadStart(). If the addresses to be read from the device +//! are in a sequence, it is not necessary to call this function multiple +//! times. Until it is changed, the EPI module stores the last address +//! that was used for a non-blocking read (per channel). +//! +//! \return None. +// +//***************************************************************************** +void +EPINonBlockingReadConfigure(uint32_t ui32Base, uint32_t ui32Channel, + uint32_t ui32DataSize, uint32_t ui32Address) +{ + uint32_t ui32Offset; + + // + // Check the arguments. + // + ASSERT(ui32Base == EPI0_BASE); + ASSERT(ui32Channel < 2); + ASSERT(ui32DataSize < 4); + ASSERT(ui32Address < 0x20000000); + + // + // Compute the offset needed to select the correct channel regs. + // + ui32Offset = ui32Channel * (EPI_O_RSIZE1 - EPI_O_RSIZE0); + + // + // Write the data size register for the channel. + // + HWREG(ui32Base + EPI_O_RSIZE0 + ui32Offset) = ui32DataSize; + + // + // Write the starting address register for the channel. + // + HWREG(ui32Base + EPI_O_RADDR0 + ui32Offset) = ui32Address; +} + +//***************************************************************************** +// +//! Starts a non-blocking read transaction. +//! +//! \param ui32Base is the EPI module base address. +//! \param ui32Channel is the read channel (0 or 1). +//! \param ui32Count is the number of items to read (1-4095). +//! +//! This function starts a non-blocking read that was previously configured +//! with the function EPINonBlockingReadConfigure(). Once this function is +//! called, the EPI module begins reading data from the external device +//! into the read FIFO. The EPI stops reading when the FIFO fills up +//! and resumes reading when the application drains the FIFO, until the +//! total specified count of data items has been read. +//! +//! Once a read transaction is completed and the FIFO drained, another +//! transaction can be started from the next address by calling this +//! function again. +//! +//! \return None. +// +//***************************************************************************** +void +EPINonBlockingReadStart(uint32_t ui32Base, uint32_t ui32Channel, + uint32_t ui32Count) +{ + uint32_t ui32Offset; + + // + // Check the arguments. + // + ASSERT(ui32Base == EPI0_BASE); + ASSERT(ui32Channel < 2); + ASSERT(ui32Count < 4096); + + // + // Compute the offset needed to select the correct channel regs. + // + ui32Offset = ui32Channel * (EPI_O_RPSTD1 - EPI_O_RPSTD0); + + // + // Write to the read count register. + // + HWREG(ui32Base + EPI_O_RPSTD0 + ui32Offset) = ui32Count; +} + +//***************************************************************************** +// +//! Stops a non-blocking read transaction. +//! +//! \param ui32Base is the EPI module base address. +//! \param ui32Channel is the read channel (0 or 1). +//! +//! This function cancels a non-blocking read transaction that is already +//! in progress. +//! +//! \return None. +// +//***************************************************************************** +void +EPINonBlockingReadStop(uint32_t ui32Base, uint32_t ui32Channel) +{ + uint32_t ui32Offset; + + // + // Check the arguments. + // + ASSERT(ui32Base == EPI0_BASE); + ASSERT(ui32Channel < 2); + + // + // Compute the offset needed to select the correct channel regs. + // + ui32Offset = ui32Channel * (EPI_O_RPSTD1 - EPI_O_RPSTD0); + + // + // Write a 0 to the read count register, which cancels the transaction. + // + HWREG(ui32Base + EPI_O_RPSTD0 + ui32Offset) = 0; +} + +//***************************************************************************** +// +//! Get the count remaining for a non-blocking transaction. +//! +//! \param ui32Base is the EPI module base address. +//! \param ui32Channel is the read channel (0 or 1). +//! +//! This function gets the remaining count of items for a non-blocking read +//! transaction. +//! +//! \return The number of items remaining in the non-blocking read transaction. +// +//***************************************************************************** +uint32_t +EPINonBlockingReadCount(uint32_t ui32Base, uint32_t ui32Channel) +{ + uint32_t ui32Offset; + + // + // Check the arguments. + // + ASSERT(ui32Base == EPI0_BASE); + ASSERT(ui32Channel < 2); + + // + // Compute the offset needed to select the correct channel regs. + // + ui32Offset = ui32Channel * (EPI_O_RPSTD1 - EPI_O_RPSTD0); + + // + // Read the count remaining and return the value to the caller. + // + return(HWREG(ui32Base + EPI_O_RPSTD0 + ui32Offset)); +} + +//***************************************************************************** +// +//! Get the count of items available in the read FIFO. +//! +//! \param ui32Base is the EPI module base address. +//! +//! This function gets the number of items that are available to read in +//! the read FIFO. The read FIFO is filled by a non-blocking read transaction +//! which is configured by the functions EPINonBlockingReadConfigure() and +//! EPINonBlockingReadStart(). +//! +//! \return The number of items available to read in the read FIFO. +// +//***************************************************************************** +uint32_t +EPINonBlockingReadAvail(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == EPI0_BASE); + + // + // Read the FIFO count and return it to the caller. + // + return(HWREG(ui32Base + EPI_O_RFIFOCNT)); +} + +//***************************************************************************** +// +//! Read available data from the read FIFO, as 32-bit data items. +//! +//! \param ui32Base is the EPI module base address. +//! \param ui32Count is the maximum count of items to read. +//! \param pui32Buf is the caller supplied buffer where the read data is +//! stored. +//! +//! This function reads 32-bit data items from the read FIFO and stores +//! the values in a caller-supplied buffer. The function reads and stores +//! data from the FIFO until there is no more data in the FIFO or the maximum +//! count is reached as specified in the parameter \e ui32Count. The actual +//! count of items is returned. +//! +//! \return The number of items read from the FIFO. +// +//***************************************************************************** +uint32_t +EPINonBlockingReadGet32(uint32_t ui32Base, uint32_t ui32Count, + uint32_t *pui32Buf) +{ + uint32_t ui32CountRead = 0; + + // + // Check the arguments. + // + ASSERT(ui32Base == EPI0_BASE); + ASSERT(ui32Count < 4096); + ASSERT(pui32Buf); + + // + // Read from the FIFO while there are any items to read and + // the caller's specified count is not exceeded. + // + while(HWREG(ui32Base + EPI_O_RFIFOCNT) && ui32Count--) + { + // + // Read from the FIFO and store in the caller supplied buffer. + // + *pui32Buf = HWREG(ui32Base + EPI_O_READFIFO0); + + // + // Update the caller's buffer pointer and the count of items read. + // + pui32Buf++; + ui32CountRead++; + } + + // + // Return the count of items read to the caller. + // + return(ui32CountRead); +} + +//***************************************************************************** +// +//! Read available data from the read FIFO, as 16-bit data items. +//! +//! \param ui32Base is the EPI module base address. +//! \param ui32Count is the maximum count of items to read. +//! \param pui16Buf is the caller-supplied buffer where the read data is +//! stored. +//! +//! This function reads 16-bit data items from the read FIFO and stores +//! the values in a caller-supplied buffer. The function reads and stores +//! data from the FIFO until there is no more data in the FIFO or the maximum +//! count is reached as specified in the parameter \e ui32Count. The actual +//! count of items is returned. +//! +//! \return The number of items read from the FIFO. +// +//***************************************************************************** +uint32_t +EPINonBlockingReadGet16(uint32_t ui32Base, uint32_t ui32Count, + uint16_t *pui16Buf) +{ + uint32_t ui32CountRead = 0; + + // + // Check the arguments. + // + ASSERT(ui32Base == EPI0_BASE); + ASSERT(ui32Count < 4096); + ASSERT(pui16Buf); + + // + // Read from the FIFO while there are any items to read, and + // the caller's specified count is not exceeded. + // + while(HWREG(ui32Base + EPI_O_RFIFOCNT) && ui32Count--) + { + // + // Read from the FIFO and store in the caller-supplied buffer. + // + *pui16Buf = (uint16_t)HWREG(ui32Base + EPI_O_READFIFO0); + + // + // Update the caller's buffer pointer and the count of items read. + // + pui16Buf++; + ui32CountRead++; + } + + // + // Return the count of items read to the caller. + // + return(ui32CountRead); +} + +//***************************************************************************** +// +//! Read available data from the read FIFO, as 8-bit data items. +//! +//! \param ui32Base is the EPI module base address. +//! \param ui32Count is the maximum count of items to read. +//! \param pui8Buf is the caller-supplied buffer where the read data is +//! stored. +//! +//! This function reads 8-bit data items from the read FIFO and stores +//! the values in a caller-supplied buffer. The function reads and stores +//! data from the FIFO until there is no more data in the FIFO or the maximum +//! count is reached as specified in the parameter \e ui32Count. The actual +//! count of items is returned. +//! +//! \return The number of items read from the FIFO. +// +//***************************************************************************** +uint32_t +EPINonBlockingReadGet8(uint32_t ui32Base, uint32_t ui32Count, + uint8_t *pui8Buf) +{ + uint32_t ui32CountRead = 0; + + // + // Check the arguments. + // + ASSERT(ui32Base == EPI0_BASE); + ASSERT(ui32Count < 4096); + ASSERT(pui8Buf); + + // + // Read from the FIFO while there are any items to read, and + // the caller's specified count is not exceeded. + // + while(HWREG(ui32Base + EPI_O_RFIFOCNT) && ui32Count--) + { + // + // Read from the FIFO and store in the caller supplied buffer. + // + *pui8Buf = (uint8_t)HWREG(ui32Base + EPI_O_READFIFO0); + + // + // Update the caller's buffer pointer and the count of items read. + // + pui8Buf++; + ui32CountRead++; + } + + // + // Return the count of items read to the caller. + // + return(ui32CountRead); +} + +//***************************************************************************** +// +//! Configures the read FIFO. +//! +//! \param ui32Base is the EPI module base address. +//! \param ui32Config is the FIFO configuration. +//! +//! This function configures the FIFO trigger levels and error +//! generation. The parameter \e ui32Config is the logical OR of the +//! following: +//! +//! - \b EPI_FIFO_CONFIG_WTFULLERR enables an error interrupt when a write is +//! attempted and the write FIFO is full +//! - \b EPI_FIFO_CONFIG_RSTALLERR enables an error interrupt when a read is +//! stalled due to an interleaved write or other reason +//! - FIFO TX trigger level, select one of: +//! - \b EPI_FIFO_CONFIG_TX_EMPTY sets the FIFO TX trigger level to empty. +//! - \b EPI_FIFO_CONFIG_TX_1_4 sets the FIFO TX trigger level to 1/4. +//! - \b EPI_FIFO_CONFIG_TX_1_2 sets the FIFO TX trigger level to 1/2. +//! - \b EPI_FIFO_CONFIG_TX_3_4 sets the FIFO TX trigger level to 3/4. +//! - FIFO RX trigger level, select one of: +//! - \b EPI_FIFO_CONFIG_RX_1_8 sets the FIFO RX trigger level to 1/8. +//! - \b EPI_FIFO_CONFIG_RX_1_4 sets the FIFO RX trigger level to 1/4. +//! - \b EPI_FIFO_CONFIG_RX_1_2 sets the FIFO RX trigger level to 1/2. +//! - \b EPI_FIFO_CONFIG_RX_3_4 sets the FIFO RX trigger level to 3/4. +//! - \b EPI_FIFO_CONFIG_RX_7_8 sets the FIFO RX trigger level to 7/8. +//! - \b EPI_FIFO_CONFIG_RX_FULL sets the FIFO RX trigger level to full. +//! +//! \return None. +// +//***************************************************************************** +void +EPIFIFOConfig(uint32_t ui32Base, uint32_t ui32Config) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == EPI0_BASE); + ASSERT(ui32Config == (ui32Config & 0x00030077)); + + // + // Load the configuration into the FIFO config reg. + // + HWREG(ui32Base + EPI_O_FIFOLVL) = ui32Config; +} + +//***************************************************************************** +// +//! Reads the number of empty slots in the write transaction FIFO. +//! +//! \param ui32Base is the EPI module base address. +//! +//! This function returns the number of slots available in the transaction +//! FIFO. It can be used in a polling method to avoid attempting a write +//! that would stall. +//! +//! \return The number of empty slots in the transaction FIFO. +// +//***************************************************************************** +uint32_t +EPIWriteFIFOCountGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == EPI0_BASE); + + // + // Read the FIFO count and return it to the caller. + // + return(HWREG(ui32Base + EPI_O_WFIFOCNT)); +} + +//***************************************************************************** +// +//! Enables EPI interrupt sources. +//! +//! \param ui32Base is the EPI module base address. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be enabled. +//! +//! This function enables the specified EPI sources to generate interrupts. +//! The \e ui32IntFlags parameter can be the logical OR of any of the following +//! values: +//! +//! - \b EPI_INT_TXREQ interrupt when transmit FIFO is below the trigger level. +//! - \b EPI_INT_RXREQ interrupt when read FIFO is above the trigger level. +//! - \b EPI_INT_ERR interrupt when an error condition occurs. +//! - \b EPI_INT_DMA_TX_DONE interrupt when the transmit DMA completes. +//! - \b EPI_INT_DMA_RX_DONE interrupt when the read DMA completes. +//! +//! \return Returns None. +// +//***************************************************************************** +void +EPIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == EPI0_BASE); + ASSERT(ui32IntFlags < 17); + + // + // Write the interrupt flags mask to the mask register. + // + HWREG(ui32Base + EPI_O_IM) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! Disables EPI interrupt sources. +//! +//! \param ui32Base is the EPI module base address. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be disabled. +//! +//! This function disables the specified EPI sources for interrupt +//! generation. The \e ui32IntFlags parameter can be the logical OR of any of +//! the following values: +//! +//! - \b EPI_INT_TXREQ interrupt when transmit FIFO is below the trigger level. +//! - \b EPI_INT_RXREQ interrupt when read FIFO is above the trigger level. +//! - \b EPI_INT_ERR interrupt when an error condition occurs. +//! - \b EPI_INT_DMA_TX_DONE interrupt when the transmit DMA completes. +//! - \b EPI_INT_DMA_RX_DONE interrupt when the read DMA completes. +//! +//! \return Returns None. +// +//***************************************************************************** +void +EPIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == EPI0_BASE); + ASSERT(ui32IntFlags < 17); + + // + // Write the interrupt flags mask to the mask register. + // + HWREG(ui32Base + EPI_O_IM) &= ~ui32IntFlags; +} + +//***************************************************************************** +// +//! Gets the EPI interrupt status. +//! +//! \param ui32Base is the EPI module base address. +//! \param bMasked is set \b true to get the masked interrupt status, or +//! \b false to get the raw interrupt status. +//! +//! This function returns the EPI interrupt status. It can return either +//! the raw or masked interrupt status. +//! +//! \return Returns the masked or raw EPI interrupt status, as a bit field +//! of any of the following values: +//! +//! - \b EPI_INT_TXREQ interrupt when transmit FIFO is below the trigger level. +//! - \b EPI_INT_RXREQ interrupt when read FIFO is above the trigger level. +//! - \b EPI_INT_ERR interrupt when an error condition occurs. +//! - \b EPI_INT_DMA_TX_DONE interrupt when the transmit DMA completes. +//! - \b EPI_INT_DMA_RX_DONE interrupt when the read DMA completes. +// +//***************************************************************************** +uint32_t +EPIIntStatus(uint32_t ui32Base, bool bMasked) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == EPI0_BASE); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ui32Base + EPI_O_MIS)); + } + else + { + return(HWREG(ui32Base + EPI_O_RIS)); + } +} + +//***************************************************************************** +// +//! Gets the EPI error interrupt status. +//! +//! \param ui32Base is the EPI module base address. +//! +//! This function returns the error status of the EPI. If the return value of +//! the function EPIIntStatus() has the flag \b EPI_INT_ERR set, then this +//! function can be used to determine the cause of the error. +//! +//! \return Returns a bit mask of error flags, which can be the logical +//! OR of any of the following: +//! +//! - \b EPI_INT_ERR_WTFULL occurs when a write stalled when the transaction +//! FIFO was full +//! - \b EPI_INT_ERR_RSTALL occurs when a read stalled +//! - \b EPI_INT_ERR_TIMEOUT occurs when the external clock enable held +//! off a transaction longer than the configured maximum wait time +// +//***************************************************************************** +uint32_t +EPIIntErrorStatus(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == EPI0_BASE); + + // + // Read the error status and return to caller. + // + return(HWREG(ui32Base + EPI_O_EISC)); +} + +//***************************************************************************** +// +//! Clears pending EPI error sources. +//! +//! \param ui32Base is the EPI module base address. +//! \param ui32ErrFlags is a bit mask of the error sources to be cleared. +//! +//! This function clears the specified pending EPI errors. The \e ui32ErrFlags +//! parameter can be the logical OR of any of the following values: +//! +//! - \b EPI_INT_ERR_DMAWRIC clears the EPI_INT_DMA_TX_DONE as an interrupt +//! source +//! - \b EPI_INT_ERR_DMARDIC clears the EPI_INT_DMA_RX_DONE as an interrupt +//! source +//! - \b EPI_INT_ERR_WTFULL occurs when a write stalled when the transaction +//! FIFO was full +//! - \b EPI_INT_ERR_RSTALL occurs when a read stalled +//! - \b EPI_INT_ERR_TIMEOUT occurs when the external clock enable held +//! off a transaction longer than the configured maximum wait time +//! +//! \return Returns None. +// +//***************************************************************************** +void +EPIIntErrorClear(uint32_t ui32Base, uint32_t ui32ErrFlags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == EPI0_BASE); + ASSERT(ui32ErrFlags < 0x20); + + // + // Write the error flags to the register to clear the pending errors. + // + HWREG(ui32Base + EPI_O_EISC) = ui32ErrFlags; +} + +//***************************************************************************** +// +//! Returns the interrupt number for a given EPI base address. +//! +//! \param ui32Base is the base address of the EPI module. +//! +//! This function returns the interrupt number for the EPI module with the base +//! address passed in the \e ui32Base parameter. +//! +//! \return Returns the EPI interrupt number or 0 if the interrupt does not +//! exist. +// +//***************************************************************************** +static uint32_t +_EPIIntNumberGet(uint32_t ui32Base) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT(ui32Base == EPI0_BASE); + + // + // By default, assume EPI is not supported. + // + ui32Int = 0; + + if(CLASS_IS_TM4C129) + { + ui32Int = INT_EPI0_TM4C129; + } + + return(ui32Int); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the EPI module. +//! +//! \param ui32Base is the EPI module base address. +//! \param pfnHandler is a pointer to the function to be called when the +//! interrupt is activated. +//! +//! This sets and enables the handler to be called when the EPI module +//! generates an interrupt. Specific EPI interrupts must still be enabled +//! with the EPIIntEnable() function. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +EPIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT(ui32Base == EPI0_BASE); + ASSERT(pfnHandler); + + // + // Get the interrupt number for the EPI interface. + // + ui32Int = _EPIIntNumberGet(ui32Base); + + ASSERT(ui32Int != 0); + + // + // Register the interrupt handler. + // + IntRegister(ui32Int, pfnHandler); + + // + // Enable the EPI interface interrupt. + // + IntEnable(ui32Int); +} + +//***************************************************************************** +// +//! Removes a registered interrupt handler for the EPI module. +//! +//! \param ui32Base is the EPI module base address. +//! +//! This function disables and clears the handler to be called when the +//! EPI interrupt occurs. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +EPIIntUnregister(uint32_t ui32Base) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT(ui32Base == EPI0_BASE); + + // + // Get the interrupt number for the EPI interface. + // + ui32Int = _EPIIntNumberGet(ui32Base); + + ASSERT(ui32Int != 0); + + // + // Disable the EPI interface interrupt. + // + IntDisable(ui32Int); + + // + // Unregister the interrupt handler. + // + IntUnregister(ui32Int); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/flash.c b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/flash.c new file mode 100644 index 0000000000000000000000000000000000000000..158176a766cd4031be9a3883928388d519ab5780 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/flash.c @@ -0,0 +1,977 @@ +//***************************************************************************** +// +// flash.c - Driver for programming the on-chip flash. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup flash_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_flash.h" +#include "inc/hw_ints.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/flash.h" +#include "driverlib/interrupt.h" + +//***************************************************************************** +// +// An array that maps the specified memory bank to the appropriate Flash +// Memory Protection Program Enable (FMPPE) register. +// +//***************************************************************************** +static const uint32_t g_pui32FMPPERegs[] = +{ + FLASH_FMPPE0, + FLASH_FMPPE1, + FLASH_FMPPE2, + FLASH_FMPPE3, + FLASH_FMPPE4, + FLASH_FMPPE5, + FLASH_FMPPE6, + FLASH_FMPPE7, + FLASH_FMPPE8, + FLASH_FMPPE9, + FLASH_FMPPE10, + FLASH_FMPPE11, + FLASH_FMPPE12, + FLASH_FMPPE13, + FLASH_FMPPE14, + FLASH_FMPPE15, +}; + +//***************************************************************************** +// +// An array that maps the specified memory bank to the appropriate Flash +// Memory Protection Read Enable (FMPRE) register. +// +//***************************************************************************** +static const uint32_t g_pui32FMPRERegs[] = +{ + FLASH_FMPRE0, + FLASH_FMPRE1, + FLASH_FMPRE2, + FLASH_FMPRE3, + FLASH_FMPRE4, + FLASH_FMPRE5, + FLASH_FMPRE6, + FLASH_FMPRE7, + FLASH_FMPRE8, + FLASH_FMPRE9, + FLASH_FMPRE10, + FLASH_FMPRE11, + FLASH_FMPRE12, + FLASH_FMPRE13, + FLASH_FMPRE14, + FLASH_FMPRE15, +}; + +//***************************************************************************** +// +//! Erases a block of flash. +//! +//! \param ui32Address is the start address of the flash block to be erased. +//! +//! This function erases a block of the on-chip flash. After erasing, the +//! block is filled with 0xFF bytes. Read-only and execute-only blocks cannot +//! be erased. +//! +//! The flash block size is device-class dependent. All TM4C123x devices use +//! 1-KB blocks but TM4C129x devices use 16-KB blocks. Please consult the +//! device datasheet to determine the block size in use. +//! +//! This function does not return until the block has been erased. +//! +//! \return Returns 0 on success, or -1 if an invalid block address was +//! specified or the block is write-protected. +// +//***************************************************************************** +int32_t +FlashErase(uint32_t ui32Address) +{ + // + // Check the arguments. + // + ASSERT(!(ui32Address & (FLASH_ERASE_SIZE - 1))); + + // + // Clear the flash access and error interrupts. + // + HWREG(FLASH_FCMISC) = (FLASH_FCMISC_AMISC | FLASH_FCMISC_VOLTMISC | + FLASH_FCMISC_ERMISC); + + // + // Erase the block. + // + HWREG(FLASH_FMA) = ui32Address; + HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_ERASE; + + // + // Wait until the block has been erased. + // + while(HWREG(FLASH_FMC) & FLASH_FMC_ERASE) + { + } + + // + // Return an error if an access violation or erase error occurred. + // + if(HWREG(FLASH_FCRIS) & (FLASH_FCRIS_ARIS | FLASH_FCRIS_VOLTRIS | + FLASH_FCRIS_ERRIS)) + { + return(-1); + } + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Programs flash. +//! +//! \param pui32Data is a pointer to the data to be programmed. +//! \param ui32Address is the starting address in flash to be programmed. Must +//! be a multiple of four. +//! \param ui32Count is the number of bytes to be programmed. Must be a +//! multiple of four. +//! +//! This function programs a sequence of words into the on-chip flash. +//! Because the flash is programmed one word at a time, the starting address +//! and byte count must both be multiples of four. It is up to the caller to +//! verify the programmed contents, if such verification is required. +//! +//! This function does not return until the data has been programmed. +//! +//! \return Returns 0 on success, or -1 if a programming error is encountered. +// +//***************************************************************************** +int32_t +FlashProgram(uint32_t *pui32Data, uint32_t ui32Address, uint32_t ui32Count) +{ + // + // Check the arguments. + // + ASSERT(!(ui32Address & 3)); + ASSERT(!(ui32Count & 3)); + + // + // Clear the flash access and error interrupts. + // + HWREG(FLASH_FCMISC) = (FLASH_FCMISC_AMISC | FLASH_FCMISC_VOLTMISC | + FLASH_FCMISC_INVDMISC | FLASH_FCMISC_PROGMISC); + + // + // Loop over the words to be programmed. + // + while(ui32Count) + { + // + // Set the address of this block of words. + // + HWREG(FLASH_FMA) = ui32Address & ~(0x7f); + + // + // Loop over the words in this 32-word block. + // + while(((ui32Address & 0x7c) || (HWREG(FLASH_FWBVAL) == 0)) && + (ui32Count != 0)) + { + // + // Write this word into the write buffer. + // + HWREG(FLASH_FWBN + (ui32Address & 0x7c)) = *pui32Data++; + ui32Address += 4; + ui32Count -= 4; + } + + // + // Program the contents of the write buffer into flash. + // + HWREG(FLASH_FMC2) = FLASH_FMC2_WRKEY | FLASH_FMC2_WRBUF; + + // + // Wait until the write buffer has been programmed. + // + while(HWREG(FLASH_FMC2) & FLASH_FMC2_WRBUF) + { + } + } + + // + // Return an error if an access violation occurred. + // + if(HWREG(FLASH_FCRIS) & (FLASH_FCRIS_ARIS | FLASH_FCRIS_VOLTRIS | + FLASH_FCRIS_INVDRIS | FLASH_FCRIS_PROGRIS)) + { + return(-1); + } + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Gets the protection setting for a block of flash. +//! +//! \param ui32Address is the start address of the flash block to be queried. +//! +//! This function gets the current protection for the specified block of flash. +//! Refer to the device data sheet to determine the granularity for each +//! protection option. A block can be read/write, read-only, or execute-only. +//! Read/write blocks can be read, executed, erased, and programmed. Read-only +//! blocks can be read and executed. Execute-only blocks can only be executed; +//! processor and debugger data reads are not allowed. +//! +//! \return Returns the protection setting for this block. See +//! FlashProtectSet() for possible values. +// +//***************************************************************************** +tFlashProtection +FlashProtectGet(uint32_t ui32Address) +{ + uint32_t ui32FMPRE, ui32FMPPE; + uint32_t ui32Bank; + + // + // Check the argument. + // + ASSERT(!(ui32Address & (FLASH_PROTECT_SIZE - 1))); + + // + // Calculate the Flash Bank from Base Address, and mask off the Bank + // from ui32Address for subsequent reference. + // + ui32Bank = (((ui32Address / FLASH_PROTECT_SIZE) / 32) % 4); + ui32Address &= ((FLASH_PROTECT_SIZE * 32) - 1); + + // + // Read the appropriate flash protection registers for the specified + // flash bank. + // + ui32FMPRE = HWREG(g_pui32FMPRERegs[ui32Bank]); + ui32FMPPE = HWREG(g_pui32FMPPERegs[ui32Bank]); + + // + // Check the appropriate protection bits for the block of memory that + // is specified by the address. + // + switch((((ui32FMPRE >> (ui32Address / FLASH_PROTECT_SIZE)) & 0x1) << 1) | + ((ui32FMPPE >> (ui32Address / FLASH_PROTECT_SIZE)) & 0x1)) + { + // + // This block is marked as execute only (that is, it can not be erased + // or programmed, and the only reads allowed are via the instruction + // fetch interface). + // + case 0: + case 1: + { + return(FlashExecuteOnly); + } + + // + // This block is marked as read only (that is, it can not be erased or + // programmed). + // + case 2: + { + return(FlashReadOnly); + } + + // + // This block is read/write; it can be read, erased, and programmed. + // + case 3: + default: + { + return(FlashReadWrite); + } + } +} + +//***************************************************************************** +// +//! Sets the protection setting for a block of flash. +//! +//! \param ui32Address is the start address of the flash block to be protected. +//! \param eProtect is the protection to be applied to the block. Can be one +//! of \b FlashReadWrite, \b FlashReadOnly, or \b FlashExecuteOnly. +//! +//! This function sets the protection for the specified block of flash. Refer +//! to the device data sheet to determine the granularity for each protection +//! option. Blocks that are read/write can be made read-only or execute-only. +//! Blocks that are read-only can be made execute-only. Blocks that are +//! execute-only cannot have their protection modified. Attempts to make the +//! block protection less stringent (that is, read-only to read/write) +//! result in a failure (and are prevented by the hardware). +//! +//! Changes to the flash protection are maintained only until the next reset. +//! This protocol allows the application to be executed in the desired flash +//! protection environment to check for inappropriate flash access (via the +//! flash interrupt). To make the flash protection permanent, use the +//! FlashProtectSave() function. +//! +//! \return Returns 0 on success, or -1 if an invalid address or an invalid +//! protection was specified. +// +//***************************************************************************** +int32_t +FlashProtectSet(uint32_t ui32Address, tFlashProtection eProtect) +{ + uint32_t ui32ProtectRE, ui32ProtectPE; + uint32_t ui32Bank; + + // + // Check the argument. + // + ASSERT(!(ui32Address & (FLASH_PROTECT_SIZE - 1))); + ASSERT((eProtect == FlashReadWrite) || (eProtect == FlashReadOnly) || + (eProtect == FlashExecuteOnly)); + + // + // Convert the address into a block number. + // + ui32Address /= FLASH_PROTECT_SIZE; + + // + // ui32Address contains a "raw" block number. Derive the Flash Bank from + // the "raw" block number, and convert ui32Address to a "relative" + // block number. + // + ui32Bank = ((ui32Address / 32) % 4); + ui32Address %= 32; + + // + // Get the current protection for the specified flash bank. + // + ui32ProtectRE = HWREG(g_pui32FMPRERegs[ui32Bank]); + ui32ProtectPE = HWREG(g_pui32FMPPERegs[ui32Bank]); + + // + // Set the protection based on the requested protection. + // + switch(eProtect) + { + // + // Make this block execute only. + // + case FlashExecuteOnly: + { + // + // Turn off the read and program bits for this block. + // + ui32ProtectRE &= ~(0x1 << ui32Address); + ui32ProtectPE &= ~(0x1 << ui32Address); + + // + // We're done handling this protection. + // + break; + } + + // + // Make this block read only. + // + case FlashReadOnly: + { + // + // The block can not be made read only if it is execute only. + // + if(((ui32ProtectRE >> ui32Address) & 0x1) != 0x1) + { + return(-1); + } + + // + // Make this block read only. + // + ui32ProtectPE &= ~(0x1 << ui32Address); + + // + // We're done handling this protection. + // + break; + } + + // + // Make this block read/write. + // + case FlashReadWrite: + default: + { + // + // The block can not be made read/write if it is not already + // read/write. + // + if((((ui32ProtectRE >> ui32Address) & 0x1) != 0x1) || + (((ui32ProtectPE >> ui32Address) & 0x1) != 0x1)) + { + return(-1); + } + + // + // The block is already read/write, so there is nothing to do. + // + return(0); + } + } + + // + // Set the new protection for the specified flash bank. + // + HWREG(g_pui32FMPRERegs[ui32Bank]) = ui32ProtectRE; + HWREG(g_pui32FMPPERegs[ui32Bank]) = ui32ProtectPE; + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Saves the flash protection settings. +//! +//! This function makes the currently programmed flash protection settings +//! permanent. This operation is non-reversible; a chip reset or power cycle +//! does not change the flash protection. +//! +//! This function does not return until the protection has been saved. +//! +//! \return Returns 0 on success, or -1 if a hardware error is encountered. +// +//***************************************************************************** +int32_t +FlashProtectSave(void) +{ + uint32_t ui32Temp; + + // + // Save the entire bank of 8 flash protection registers. + // + for(ui32Temp = 0; ui32Temp < 8; ui32Temp++) + { + // + // Tell the flash controller to write the flash protection register. + // + HWREG(FLASH_FMA) = ui32Temp; + HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT; + + // + // Wait until the write has completed. + // + while(HWREG(FLASH_FMC) & FLASH_FMC_COMT) + { + } + } + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Gets the user registers. +//! +//! \param pui32User0 is a pointer to the location to store USER Register 0. +//! \param pui32User1 is a pointer to the location to store USER Register 1. +//! +//! This function reads the contents of user registers 0 and 1, and +//! stores them in the specified locations. +//! +//! \return Returns 0 on success, or -1 if a hardware error is encountered. +// +//***************************************************************************** +int32_t +FlashUserGet(uint32_t *pui32User0, uint32_t *pui32User1) +{ + // + // Verify that the pointers are valid. + // + ASSERT(pui32User0 != 0); + ASSERT(pui32User1 != 0); + + // + // Get and store the current value of the user registers. + // + *pui32User0 = HWREG(FLASH_USERREG0); + *pui32User1 = HWREG(FLASH_USERREG1); + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Sets the user registers. +//! +//! \param ui32User0 is the value to store in USER Register 0. +//! \param ui32User1 is the value to store in USER Register 1. +//! +//! This function sets the contents of the user registers 0 and 1 to +//! the specified values. +//! +//! \return Returns 0 on success, or -1 if a hardware error is encountered. +// +//***************************************************************************** +int32_t +FlashUserSet(uint32_t ui32User0, uint32_t ui32User1) +{ + // + // Save the new values into the user registers. + // + HWREG(FLASH_USERREG0) = ui32User0; + HWREG(FLASH_USERREG1) = ui32User1; + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Gets all the user registers. +//! +//! \param pui32User0 is a pointer to the location to store USER Register 0. +//! \param pui32User1 is a pointer to the location to store USER Register 1. +//! \param pui32User2 is a pointer to the location to store USER Register 2. +//! \param pui32User3 is a pointer to the location to store USER Register 3. +//! +//! This function reads the contents of user registers 0, 1, 2 and 3, and +//! stores them in the specified locations. +//! +//! \return Returns 0 on success, or -1 if a hardware error is encountered. +// +//***************************************************************************** +int32_t +FlashAllUserRegisterGet(uint32_t *pui32User0, uint32_t *pui32User1, + uint32_t *pui32User2, uint32_t *pui32User3) +{ + // + // Verify that the pointers are valid. + // + ASSERT(pui32User0 != 0); + ASSERT(pui32User1 != 0); + ASSERT(pui32User2 != 0); + ASSERT(pui32User3 != 0); + + // + // Get and store the current value of the user registers. + // + *pui32User0 = HWREG(FLASH_USERREG0); + *pui32User1 = HWREG(FLASH_USERREG1); + *pui32User2 = HWREG(FLASH_USERREG2); + *pui32User3 = HWREG(FLASH_USERREG3); + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Sets the user registers 0 to 3 +//! +//! \param ui32User0 is the value to store in USER Register 0. +//! \param ui32User1 is the value to store in USER Register 1. +//! \param ui32User2 is the value to store in USER Register 2. +//! \param ui32User3 is the value to store in USER Register 3. +//! +//! This function sets the contents of the user registers 0, 1, 2 and 3 to +//! the specified values. +//! +//! \return Returns 0 on success, or -1 if a hardware error is encountered. +// +//***************************************************************************** +int32_t +FlashAllUserRegisterSet(uint32_t ui32User0, uint32_t ui32User1, + uint32_t ui32User2, uint32_t ui32User3) +{ + // + // Save the new values into the user registers. + // + HWREG(FLASH_USERREG0) = ui32User0; + HWREG(FLASH_USERREG1) = ui32User1; + HWREG(FLASH_USERREG2) = ui32User2; + HWREG(FLASH_USERREG3) = ui32User3; + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Saves the user registers 0 and 1. +//! +//! This function makes the currently programmed user register 0 and 1 settings +//! permanent. This operation is non-reversible; a chip reset or power cycle +//! does not change the flash protection. +//! +//! This function does not return until the protection has been saved. +//! +//! \return Returns 0 on success, or -1 if a hardware error is encountered. +// +//***************************************************************************** +int32_t +FlashUserSave(void) +{ + // + // Setting the MSB of FMA will trigger a permanent save of a USER + // register. Bit 0 will indicate User 0 (0) or User 1 (1). + // + HWREG(FLASH_FMA) = 0x80000000; + HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT; + + // + // Wait until the write has completed. + // + while(HWREG(FLASH_FMC) & FLASH_FMC_COMT) + { + } + + // + // Tell the flash controller to write the USER1 Register. + // + HWREG(FLASH_FMA) = 0x80000001; + HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT; + + // + // Wait until the write has completed. + // + while(HWREG(FLASH_FMC) & FLASH_FMC_COMT) + { + } + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Saves the user registers. +//! +//! This function makes the currently programmed user register 0, 1, 2 and 3 +//! settings permanent. This operation is non-reversible; a chip reset or +//! power cycle does not change the flash protection. +//! +//! This function does not return until the protection has been saved. +//! +//! \note To ensure data integrity of the user registers, the commits should +//! not be interrupted with a power loss. +//! +//! \return Returns 0 on success, or -1 if a hardware error is encountered. +// +//***************************************************************************** +int32_t +FlashAllUserRegisterSave(void) +{ + uint32_t ui32Index; + + // + // Setting the MSB of FMA will trigger a permanent save of a USER Register. + // The 2 least signigicant bits, specify the exact User Register to save. + // The value of the least significant bits for + // USER Register 0 is 00, + // USER Register 1 is 01, + // USER Register 2 is 10 and + // USER Register 3 is 11. + // + for(ui32Index = 0; ui32Index < 4; ui32Index++) + { + // + // Tell the flash controller to commit a USER Register. + // + HWREG(FLASH_FMA) = (0x80000000 + ui32Index); + HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT; + + // + // Wait until the write has completed. + // + while(HWREG(FLASH_FMC) & FLASH_FMC_COMT) + { + } + } + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the flash interrupt. +//! +//! \param pfnHandler is a pointer to the function to be called when the flash +//! interrupt occurs. +//! +//! This function sets the handler to be called when the flash interrupt +//! occurs. The flash controller can generate an interrupt when an invalid +//! flash access occurs, such as trying to program or erase a read-only block, +//! or trying to read from an execute-only block. It can also generate an +//! interrupt when a program or erase operation has completed. The interrupt +//! is automatically enabled when the handler is registered. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +FlashIntRegister(void (*pfnHandler)(void)) +{ + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(INT_FLASH_TM4C123, pfnHandler); + + // + // Enable the flash interrupt. + // + IntEnable(INT_FLASH_TM4C123); +} + +//***************************************************************************** +// +//! Unregisters the interrupt handler for the flash interrupt. +//! +//! This function clears the handler to be called when the flash interrupt +//! occurs. This function also masks off the interrupt in the interrupt +//! controller so that the interrupt handler is no longer called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +FlashIntUnregister(void) +{ + // + // Disable the interrupt. + // + IntDisable(INT_FLASH_TM4C123); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_FLASH_TM4C123); +} + +//***************************************************************************** +// +//! Enables individual flash controller interrupt sources. +//! +//! \param ui32IntFlags is a bit mask of the interrupt sources to be enabled. +//! The ui32IntFlags parameter can be the logical OR of any of the following +//! values: +//! +//! - \b FLASH_INT_ACCESS occurs when a program or erase action was attempted +//! on a block of flash that is marked as read-only or execute-only. +//! - \b FLASH_INT_PROGRAM occurs when a programming or erase cycle completes. +//! - \b FLASH_INT_EEPROM occurs when an EEPROM interrupt occurs. The source of +//! the EEPROM interrupt can be determined by reading the EEDONE register. +//! - \b FLASH_INT_VOLTAGE_ERR occurs when the voltage was out of spec during +//! the flash operation and the operation was terminated. +//! - \b FLASH_INT_DATA_ERR occurs when an operation attempts to program a bit that +//! contains a 0 to a 1. +//! - \b FLASH_INT_ERASE_ERR occurs when an erase operation fails. +//! - \b FLASH_INT_PROGRAM_ERR occurs when a program operation fails. +//! +//! This function enables the indicated flash controller interrupt sources. +//! Only the sources that are enabled can be reflected to the processor +//! interrupt; disabled sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +void +FlashIntEnable(uint32_t ui32IntFlags) +{ + // + // Enable the specified interrupts. + // + HWREG(FLASH_FCIM) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! Disables individual flash controller interrupt sources. +//! +//! \param ui32IntFlags is a bit mask of the interrupt sources to be disabled. +//! The ui32IntFlags parameter can be the logical OR of any of the following +//! values: +//! +//! - \b FLASH_INT_ACCESS occurs when a program or erase action was attempted +//! on a block of flash that is marked as read-only or execute-only. +//! - \b FLASH_INT_PROGRAM occurs when a programming or erase cycle completes. +//! - \b FLASH_INT_EEPROM occurs when an EEPROM interrupt occurs. The source of +//! the EEPROM interrupt can be determined by reading the EEDONE register. +//! - \b FLASH_INT_VOLTAGE_ERR occurs when the voltage was out of spec during +//! the flash operation and the operation was terminated. +//! - \b FLASH_INT_DATA_ERR occurs when an operation attempts to program a bit that +//! contains a 0 to a 1. +//! - \b FLASH_INT_ERASE_ERR occurs when an erase operation fails. +//! - \b FLASH_INT_PROGRAM_ERR occurs when a program operation fails. +//! +//! This function disables the indicated flash controller interrupt sources. +//! Only the sources that are enabled can be reflected to the processor +//! interrupt; disabled sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +void +FlashIntDisable(uint32_t ui32IntFlags) +{ + // + // Disable the specified interrupts. + // + HWREG(FLASH_FCIM) &= ~(ui32IntFlags); +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param bMasked is false if the raw interrupt status is required and true if +//! the masked interrupt status is required. +//! +//! This function returns the interrupt status for the flash controller. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! \b FLASH_INT_ACCESS, \b FLASH_INT_PROGRAM, \b FLASH_INT_EEPROM, +//! FLASH_INT_VOLTAGE_ERR, FLASH_INT_DATA_ERR, FLASH_INT_ERASE_ERR, and +//! FLASH_INT_PROGRAM_ERR. +// +//***************************************************************************** +uint32_t +FlashIntStatus(bool bMasked) +{ + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(FLASH_FCMISC)); + } + else + { + return(HWREG(FLASH_FCRIS)); + } +} + +//***************************************************************************** +// +//! Clears flash controller interrupt sources. +//! +//! \param ui32IntFlags is the bit mask of the interrupt sources to be cleared. +//! +//! The specified flash controller interrupt sources are cleared, so that they +//! no longer assert. The +//! ui32IntFlags parameter can be the logical OR of any of the following +//! values: +//! +//! - \b FLASH_INT_ACCESS occurs when a program or erase action was attempted +//! on a block of flash that is marked as read-only or execute-only. +//! - \b FLASH_INT_PROGRAM occurs when a programming or erase cycle completes. +//! - \b FLASH_INT_EEPROM occurs when an EEPROM interrupt occurs. The source of +//! the EEPROM interrupt can be determined by reading the EEDONE register. +//! - \b FLASH_INT_VOLTAGE_ERR occurs when the voltage was out of spec during +//! the flash operation and the operation was terminated. +//! - \b FLASH_INT_DATA_ERR occurs when an operation attempts to program a bit that +//! contains a 0 to a 1. +//! - \b FLASH_INT_ERASE_ERR occurs when an erase operation fails. +//! - \b FLASH_INT_PROGRAM_ERR occurs when a program operation fails. +//! +//! This function must be called in the interrupt handler to keep the +//! interrupt from being triggered again immediately upon exit. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +FlashIntClear(uint32_t ui32IntFlags) +{ + // + // Clear the flash interrupt. + // + HWREG(FLASH_FCMISC) = ui32IntFlags; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/fpu.c b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/fpu.c new file mode 100644 index 0000000000000000000000000000000000000000..ca741a27985a9a9778bcbffb4742bd7164a628d0 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/fpu.c @@ -0,0 +1,300 @@ +//***************************************************************************** +// +// fpu.c - Routines for manipulating the floating-point unit in the Cortex-M +// processor. +// +// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup fpu_api +//! @{ +// +//***************************************************************************** + +#include +#include "hw_nvic.h" +#include "hw_types.h" +#include "fpu.h" + +//***************************************************************************** +// +//! Enables the floating-point unit. +//! +//! This function enables the floating-point unit, allowing the floating-point +//! instructions to be executed. This function must be called prior to +//! performing any hardware floating-point operations; failure to do so results +//! in a NOCP usage fault. +//! +//! \return None. +// +//***************************************************************************** +void +FPUEnable(void) +{ + // + // Enable the coprocessors used by the floating-point unit. + // + HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) & + ~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) | + NVIC_CPAC_CP10_FULL | NVIC_CPAC_CP11_FULL); +} + +//***************************************************************************** +// +//! Disables the floating-point unit. +//! +//! This function disables the floating-point unit, preventing floating-point +//! instructions from executing (generating a NOCP usage fault instead). +//! +//! \return None. +// +//***************************************************************************** +void +FPUDisable(void) +{ + // + // Disable the coprocessors used by the floating-point unit. + // + HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) & + ~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) | + NVIC_CPAC_CP10_DIS | NVIC_CPAC_CP11_DIS); +} + +//***************************************************************************** +// +//! Enables the stacking of floating-point registers. +//! +//! This function enables the stacking of floating-point registers s0-s15 when +//! an interrupt is handled. When enabled, space is reserved on the stack for +//! the floating-point context and the floating-point state is saved into this +//! stack space. Upon return from the interrupt, the floating-point context is +//! restored. +//! +//! If the floating-point registers are not stacked, floating-point +//! instructions cannot be safely executed in an interrupt handler because the +//! values of s0-s15 are not likely to be preserved for the interrupted code. +//! On the other hand, stacking the floating-point registers increases the +//! stacking operation from 8 words to 26 words, also increasing the interrupt +//! response latency. +//! +//! \return None. +// +//***************************************************************************** +void +FPUStackingEnable(void) +{ + // + // Enable automatic state preservation for the floating-point unit, and + // disable lazy state preservation (meaning that the floating-point state + // is always stacked when floating-point instructions are used). + // + HWREG(NVIC_FPCC) = (HWREG(NVIC_FPCC) & ~NVIC_FPCC_LSPEN) | NVIC_FPCC_ASPEN; +} + +//***************************************************************************** +// +//! Enables the lazy stacking of floating-point registers. +//! +//! This function enables the lazy stacking of floating-point registers s0-s15 +//! when an interrupt is handled. When lazy stacking is enabled, space is +//! reserved on the stack for the floating-point context, but the +//! floating-point state is not saved. If a floating-point instruction is +//! executed from within the interrupt context, the floating-point context is +//! first saved into the space reserved on the stack. On completion of the +//! interrupt handler, the floating-point context is only restored if it was +//! saved (as the result of executing a floating-point instruction). +//! +//! This method provides a compromise between fast interrupt response (because +//! the floating-point state is not saved on interrupt entry) and the ability +//! to use floating-point in interrupt handlers (because the floating-point +//! state is saved if floating-point instructions are used). +//! +//! \return None. +// +//***************************************************************************** +void +FPULazyStackingEnable(void) +{ + // + // Enable automatic and lazy state preservation for the floating-point + // unit. + // + HWREG(NVIC_FPCC) |= NVIC_FPCC_ASPEN | NVIC_FPCC_LSPEN; +} + +//***************************************************************************** +// +//! Disables the stacking of floating-point registers. +//! +//! This function disables the stacking of floating-point registers s0-s15 when +//! an interrupt is handled. When floating-point context stacking is disabled, +//! floating-point operations performed in an interrupt handler destroy the +//! floating-point context of the main thread of execution. +//! +//! \return None. +// +//***************************************************************************** +void +FPUStackingDisable(void) +{ + // + // Disable automatic and lazy state preservation for the floating-point + // unit. + // + HWREG(NVIC_FPCC) &= ~(NVIC_FPCC_ASPEN | NVIC_FPCC_LSPEN); +} + +//***************************************************************************** +// +//! Selects the format of half-precision floating-point values. +//! +//! \param ui32Mode is the format for half-precision floating-point value, +//! which is either \b FPU_HALF_IEEE or \b FPU_HALF_ALTERNATE. +//! +//! This function selects between the IEEE half-precision floating-point +//! representation and the Cortex-M processor alternative representation. The +//! alternative representation has a larger range but does not have a way to +//! encode infinity (positive or negative) or NaN (quiet or signaling). The +//! default setting is the IEEE format. +//! +//! \note Unless this function is called prior to executing any floating-point +//! instructions, the default mode is used. +//! +//! \return None. +// +//***************************************************************************** +void +FPUHalfPrecisionModeSet(uint32_t ui32Mode) +{ + // + // Set the half-precision floating-point format. + // + HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_AHP)) | ui32Mode; +} + +//***************************************************************************** +// +//! Selects the NaN mode. +//! +//! \param ui32Mode is the mode for NaN results; which is either +//! \b FPU_NAN_PROPAGATE or \b FPU_NAN_DEFAULT. +//! +//! This function selects the handling of NaN results during floating-point +//! computations. NaNs can either propagate (the default), or they can return +//! the default NaN. +//! +//! \note Unless this function is called prior to executing any floating-point +//! instructions, the default mode is used. +//! +//! \return None. +// +//***************************************************************************** +void +FPUNaNModeSet(uint32_t ui32Mode) +{ + // + // Set the NaN mode. + // + HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_DN)) | ui32Mode; +} + +//***************************************************************************** +// +//! Selects the flush-to-zero mode. +//! +//! \param ui32Mode is the flush-to-zero mode; which is either +//! \b FPU_FLUSH_TO_ZERO_DIS or \b FPU_FLUSH_TO_ZERO_EN. +//! +//! This function enables or disables the flush-to-zero mode of the +//! floating-point unit. When disabled (the default), the floating-point unit +//! is fully IEEE compliant. When enabled, values close to zero are treated as +//! zero, greatly improving the execution speed at the expense of some accuracy +//! (as well as IEEE compliance). +//! +//! \note Unless this function is called prior to executing any floating-point +//! instructions, the default mode is used. +//! +//! \return None. +// +//***************************************************************************** +void +FPUFlushToZeroModeSet(uint32_t ui32Mode) +{ + // + // Set the flush-to-zero mode. + // + HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_FZ)) | ui32Mode; +} + +//***************************************************************************** +// +//! Selects the rounding mode for floating-point results. +//! +//! \param ui32Mode is the rounding mode. +//! +//! This function selects the rounding mode for floating-point results. After +//! a floating-point operation, the result is rounded toward the specified +//! value. The default mode is \b FPU_ROUND_NEAREST. +//! +//! The following rounding modes are available (as specified by \e ui32Mode): +//! +//! - \b FPU_ROUND_NEAREST - round toward the nearest value +//! - \b FPU_ROUND_POS_INF - round toward positive infinity +//! - \b FPU_ROUND_NEG_INF - round toward negative infinity +//! - \b FPU_ROUND_ZERO - round toward zero +//! +//! \note Unless this function is called prior to executing any floating-point +//! instructions, the default mode is used. +//! +//! \return None. +// +//***************************************************************************** +void +FPURoundingModeSet(uint32_t ui32Mode) +{ + // + // Set the rounding mode. + // + HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_RMODE_M)) | ui32Mode; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/gpio.c b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/gpio.c new file mode 100644 index 0000000000000000000000000000000000000000..a6388c680d869532a12c2ac2f6101261a17be1d9 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/gpio.c @@ -0,0 +1,2622 @@ +//***************************************************************************** +// +// gpio.c - API for GPIO ports +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup gpio_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include "hw_gpio.h" +#include "hw_ints.h" +#include "hw_memmap.h" +#include "hw_sysctl.h" +#include "hw_types.h" +#include "debug.h" +#include "gpio.h" +#include "interrupt.h" + +//***************************************************************************** +// +// A mapping of GPIO port address to interrupt number. +// +//***************************************************************************** +static const uint32_t g_ppui32GPIOIntMapBlizzard[][2] = +{ + { GPIO_PORTA_BASE, INT_GPIOA_TM4C123 }, + { GPIO_PORTA_AHB_BASE, INT_GPIOA_TM4C123 }, + { GPIO_PORTB_BASE, INT_GPIOB_TM4C123 }, + { GPIO_PORTB_AHB_BASE, INT_GPIOB_TM4C123 }, + { GPIO_PORTC_BASE, INT_GPIOC_TM4C123 }, + { GPIO_PORTC_AHB_BASE, INT_GPIOC_TM4C123 }, + { GPIO_PORTD_BASE, INT_GPIOD_TM4C123 }, + { GPIO_PORTD_AHB_BASE, INT_GPIOD_TM4C123 }, + { GPIO_PORTE_BASE, INT_GPIOE_TM4C123 }, + { GPIO_PORTE_AHB_BASE, INT_GPIOE_TM4C123 }, + { GPIO_PORTF_BASE, INT_GPIOF_TM4C123 }, + { GPIO_PORTF_AHB_BASE, INT_GPIOF_TM4C123 }, + { GPIO_PORTG_BASE, INT_GPIOG_TM4C123 }, + { GPIO_PORTG_AHB_BASE, INT_GPIOG_TM4C123 }, + { GPIO_PORTH_BASE, INT_GPIOH_TM4C123 }, + { GPIO_PORTH_AHB_BASE, INT_GPIOH_TM4C123 }, + { GPIO_PORTJ_BASE, INT_GPIOJ_TM4C123 }, + { GPIO_PORTJ_AHB_BASE, INT_GPIOJ_TM4C123 }, + { GPIO_PORTK_BASE, INT_GPIOK_TM4C123 }, + { GPIO_PORTL_BASE, INT_GPIOL_TM4C123 }, + { GPIO_PORTM_BASE, INT_GPIOM_TM4C123 }, + { GPIO_PORTN_BASE, INT_GPION_TM4C123 }, + { GPIO_PORTP_BASE, INT_GPIOP0_TM4C123 }, + { GPIO_PORTQ_BASE, INT_GPIOQ0_TM4C123 }, +}; +static const uint_fast32_t g_ui32GPIOIntMapBlizzardRows = + sizeof(g_ppui32GPIOIntMapBlizzard) / sizeof(g_ppui32GPIOIntMapBlizzard[0]); + +static const uint32_t g_ppui32GPIOIntMapSnowflake[][2] = +{ + { GPIO_PORTA_BASE, INT_GPIOA_TM4C129 }, + { GPIO_PORTA_AHB_BASE, INT_GPIOA_TM4C129 }, + { GPIO_PORTB_BASE, INT_GPIOB_TM4C129 }, + { GPIO_PORTB_AHB_BASE, INT_GPIOB_TM4C129 }, + { GPIO_PORTC_BASE, INT_GPIOC_TM4C129 }, + { GPIO_PORTC_AHB_BASE, INT_GPIOC_TM4C129 }, + { GPIO_PORTD_BASE, INT_GPIOD_TM4C129 }, + { GPIO_PORTD_AHB_BASE, INT_GPIOD_TM4C129 }, + { GPIO_PORTE_BASE, INT_GPIOE_TM4C129 }, + { GPIO_PORTE_AHB_BASE, INT_GPIOE_TM4C129 }, + { GPIO_PORTF_BASE, INT_GPIOF_TM4C129 }, + { GPIO_PORTF_AHB_BASE, INT_GPIOF_TM4C129 }, + { GPIO_PORTG_BASE, INT_GPIOG_TM4C129 }, + { GPIO_PORTG_AHB_BASE, INT_GPIOG_TM4C129 }, + { GPIO_PORTH_BASE, INT_GPIOH_TM4C129 }, + { GPIO_PORTH_AHB_BASE, INT_GPIOH_TM4C129 }, + { GPIO_PORTJ_BASE, INT_GPIOJ_TM4C129 }, + { GPIO_PORTJ_AHB_BASE, INT_GPIOJ_TM4C129 }, + { GPIO_PORTK_BASE, INT_GPIOK_TM4C129 }, + { GPIO_PORTL_BASE, INT_GPIOL_TM4C129 }, + { GPIO_PORTM_BASE, INT_GPIOM_TM4C129 }, + { GPIO_PORTN_BASE, INT_GPION_TM4C129 }, + { GPIO_PORTP_BASE, INT_GPIOP0_TM4C129 }, + { GPIO_PORTQ_BASE, INT_GPIOQ0_TM4C129 }, + { GPIO_PORTR_BASE, INT_GPIOR_TM4C129 }, + { GPIO_PORTS_BASE, INT_GPIOS_TM4C129 }, + { GPIO_PORTT_BASE, INT_GPIOT_TM4C129 }, +}; +static const uint_fast32_t g_ui32GPIOIntMapSnowflakeRows = + (sizeof(g_ppui32GPIOIntMapSnowflake) / + sizeof(g_ppui32GPIOIntMapSnowflake[0])); + +//***************************************************************************** +// +// The base addresses of all the GPIO modules. Both the APB and AHB apertures +// are provided. +// +//***************************************************************************** +static const uint32_t g_pui32GPIOBaseAddrs[] = +{ + GPIO_PORTA_BASE, GPIO_PORTA_AHB_BASE, + GPIO_PORTB_BASE, GPIO_PORTB_AHB_BASE, + GPIO_PORTC_BASE, GPIO_PORTC_AHB_BASE, + GPIO_PORTD_BASE, GPIO_PORTD_AHB_BASE, + GPIO_PORTE_BASE, GPIO_PORTE_AHB_BASE, + GPIO_PORTF_BASE, GPIO_PORTF_AHB_BASE, + GPIO_PORTG_BASE, GPIO_PORTG_AHB_BASE, + GPIO_PORTH_BASE, GPIO_PORTH_AHB_BASE, + GPIO_PORTJ_BASE, GPIO_PORTJ_AHB_BASE, + GPIO_PORTK_BASE, GPIO_PORTK_BASE, + GPIO_PORTL_BASE, GPIO_PORTL_BASE, + GPIO_PORTM_BASE, GPIO_PORTM_BASE, + GPIO_PORTN_BASE, GPIO_PORTN_BASE, + GPIO_PORTP_BASE, GPIO_PORTP_BASE, + GPIO_PORTQ_BASE, GPIO_PORTQ_BASE, + GPIO_PORTR_BASE, GPIO_PORTR_BASE, + GPIO_PORTS_BASE, GPIO_PORTS_BASE, + GPIO_PORTT_BASE, GPIO_PORTT_BASE, +}; + +//***************************************************************************** +// +//! \internal +//! Checks a GPIO base address. +//! +//! \param ui32Port is the base address of the GPIO port. +//! +//! This function determines if a GPIO port base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static bool +_GPIOBaseValid(uint32_t ui32Port) +{ + return((ui32Port == GPIO_PORTA_BASE) || + (ui32Port == GPIO_PORTA_AHB_BASE) || + (ui32Port == GPIO_PORTB_BASE) || + (ui32Port == GPIO_PORTB_AHB_BASE) || + (ui32Port == GPIO_PORTC_BASE) || + (ui32Port == GPIO_PORTC_AHB_BASE) || + (ui32Port == GPIO_PORTD_BASE) || + (ui32Port == GPIO_PORTD_AHB_BASE) || + (ui32Port == GPIO_PORTE_BASE) || + (ui32Port == GPIO_PORTE_AHB_BASE) || + (ui32Port == GPIO_PORTF_BASE) || + (ui32Port == GPIO_PORTF_AHB_BASE) || + (ui32Port == GPIO_PORTG_BASE) || + (ui32Port == GPIO_PORTG_AHB_BASE) || + (ui32Port == GPIO_PORTH_BASE) || + (ui32Port == GPIO_PORTH_AHB_BASE) || + (ui32Port == GPIO_PORTJ_BASE) || + (ui32Port == GPIO_PORTJ_AHB_BASE) || + (ui32Port == GPIO_PORTK_BASE) || + (ui32Port == GPIO_PORTL_BASE) || + (ui32Port == GPIO_PORTM_BASE) || + (ui32Port == GPIO_PORTN_BASE) || + (ui32Port == GPIO_PORTP_BASE) || + (ui32Port == GPIO_PORTQ_BASE) || + (ui32Port == GPIO_PORTR_BASE) || + (ui32Port == GPIO_PORTS_BASE) || + (ui32Port == GPIO_PORTT_BASE)); +} +#endif + +//***************************************************************************** +// +//! Gets the GPIO interrupt number. +//! +//! \param ui32Port is the base address of the GPIO port. +//! +//! Given a GPIO base address, this function returns the corresponding +//! interrupt number. +//! +//! \return Returns a GPIO interrupt number, or 0 if \e ui32Port is invalid. +// +//***************************************************************************** +static uint32_t +_GPIOIntNumberGet(uint32_t ui32Port) +{ + uint_fast32_t ui32Idx, ui32Rows; + const uint32_t (*ppui32GPIOIntMap)[2]; + + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + ppui32GPIOIntMap = g_ppui32GPIOIntMapBlizzard; + ui32Rows = g_ui32GPIOIntMapBlizzardRows; + + if(CLASS_IS_TM4C129) + { + ppui32GPIOIntMap = g_ppui32GPIOIntMapSnowflake; + ui32Rows = g_ui32GPIOIntMapSnowflakeRows; + } + + // + // Loop through the table that maps I2C base addresses to interrupt + // numbers. + // + for(ui32Idx = 0; ui32Idx < ui32Rows; ui32Idx++) + { + // + // See if this base address matches. + // + if(ppui32GPIOIntMap[ui32Idx][0] == ui32Port) + { + // + // Return the corresponding interrupt number. + // + return(ppui32GPIOIntMap[ui32Idx][1]); + } + } + + // + // The base address could not be found, so return an error. + // + return(0); +} + +//***************************************************************************** +// +//! Sets the direction and mode of the specified pin(s). +//! +//! \param ui32Port is the base address of the GPIO port +//! \param ui8Pins is the bit-packed representation of the pin(s). +//! \param ui32PinIO is the pin direction and/or mode. +//! +//! This function configures the specified pin(s) on the selected GPIO port +//! as either input or output under software control, or it configures the +//! pin to be under hardware control. +//! +//! The parameter \e ui32PinIO is an enumerated data type that can be one of +//! the following values: +//! +//! - \b GPIO_DIR_MODE_IN +//! - \b GPIO_DIR_MODE_OUT +//! - \b GPIO_DIR_MODE_HW +//! +//! where \b GPIO_DIR_MODE_IN specifies that the pin is programmed as a +//! software controlled input, \b GPIO_DIR_MODE_OUT specifies that the pin is +//! programmed as a software controlled output, and \b GPIO_DIR_MODE_HW +//! specifies that the pin is placed under hardware control. +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note GPIOPadConfigSet() must also be used to configure the corresponding +//! pad(s) in order for them to propagate the signal to/from the GPIO. +//! +//! \note A subset of GPIO pins on Tiva devices, notably those used by the +//! JTAG/SWD interface and any pin capable of acting as an NMI input, are +//! locked against inadvertent reconfiguration. These pins must be unlocked +//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR +//! registers before this function can be called. Please see the ``gpio_jtag'' +//! example application for the mechanism required and consult your part +//! datasheet for information on affected pins. +//! +//! \return None. +// +//***************************************************************************** +void +GPIODirModeSet(uint32_t ui32Port, uint8_t ui8Pins, uint32_t ui32PinIO) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + ASSERT((ui32PinIO == GPIO_DIR_MODE_IN) || + (ui32PinIO == GPIO_DIR_MODE_OUT) || + (ui32PinIO == GPIO_DIR_MODE_HW)); + + // + // Set the pin direction and mode. + // + HWREG(ui32Port + GPIO_O_DIR) = ((ui32PinIO & 1) ? + (HWREG(ui32Port + GPIO_O_DIR) | ui8Pins) : + (HWREG(ui32Port + GPIO_O_DIR) & ~(ui8Pins))); + HWREG(ui32Port + GPIO_O_AFSEL) = ((ui32PinIO & 2) ? + (HWREG(ui32Port + GPIO_O_AFSEL) | + ui8Pins) : + (HWREG(ui32Port + GPIO_O_AFSEL) & + ~(ui8Pins))); +} + +//***************************************************************************** +// +//! Gets the direction and mode of a pin. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pin is the pin number. +//! +//! This function gets the direction and control mode for a specified pin on +//! the selected GPIO port. The pin can be configured as either an input or +//! output under software control, or it can be under hardware control. The +//! type of control and direction are returned as an enumerated data type. +//! +//! \return Returns one of the enumerated data types described for +//! GPIODirModeSet(). +// +//***************************************************************************** +uint32_t +GPIODirModeGet(uint32_t ui32Port, uint8_t ui8Pin) +{ + uint32_t ui32Dir, ui32AFSEL; + + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + ASSERT(ui8Pin < 8); + + // + // Convert from a pin number to a bit position. + // + ui8Pin = 1 << ui8Pin; + + // + // Return the pin direction and mode. + // + ui32Dir = HWREG(ui32Port + GPIO_O_DIR); + ui32AFSEL = HWREG(ui32Port + GPIO_O_AFSEL); + return(((ui32Dir & ui8Pin) ? 1 : 0) | ((ui32AFSEL & ui8Pin) ? 2 : 0)); +} + +//***************************************************************************** +// +//! Sets the interrupt type for the specified pin(s). +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin(s). +//! \param ui32IntType specifies the type of interrupt trigger mechanism. +//! +//! This function sets up the various interrupt trigger mechanisms for the +//! specified pin(s) on the selected GPIO port. +//! +//! One of the following flags can be used to define the \e ui32IntType +//! parameter: +//! +//! - \b GPIO_FALLING_EDGE sets detection to edge and trigger to falling +//! - \b GPIO_RISING_EDGE sets detection to edge and trigger to rising +//! - \b GPIO_BOTH_EDGES sets detection to both edges +//! - \b GPIO_LOW_LEVEL sets detection to low level +//! - \b GPIO_HIGH_LEVEL sets detection to high level +//! +//! In addition to the above flags, the following flag can be OR'd in to the +//! \e ui32IntType parameter: +//! +//! - \b GPIO_DISCRETE_INT sets discrete interrupts for each pin on a GPIO +//! port. +//! +//! The \b GPIO_DISCRETE_INT is not available on all devices or all GPIO ports, +//! consult the data sheet to ensure that the device and the GPIO port supports +//! discrete interrupts. +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note In order to avoid any spurious interrupts, the user must ensure that +//! the GPIO inputs remain stable for the duration of this function. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOIntTypeSet(uint32_t ui32Port, uint8_t ui8Pins, + uint32_t ui32IntType) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + ASSERT(((ui32IntType & 0xF) == GPIO_FALLING_EDGE) || + ((ui32IntType & 0xF) == GPIO_RISING_EDGE) || + ((ui32IntType & 0xF) == GPIO_BOTH_EDGES) || + ((ui32IntType & 0xF) == GPIO_LOW_LEVEL) || + ((ui32IntType & 0xF) == GPIO_HIGH_LEVEL)); + ASSERT(((ui32IntType & 0x000F0000) == 0) || + (((ui32IntType & 0x000F0000) == GPIO_DISCRETE_INT) && + ((ui32Port == GPIO_PORTP_BASE) || (ui32Port == GPIO_PORTQ_BASE)))); + + // + // Set the pin interrupt type. + // + HWREG(ui32Port + GPIO_O_IBE) = ((ui32IntType & 1) ? + (HWREG(ui32Port + GPIO_O_IBE) | ui8Pins) : + (HWREG(ui32Port + GPIO_O_IBE) & ~(ui8Pins))); + HWREG(ui32Port + GPIO_O_IS) = ((ui32IntType & 2) ? + (HWREG(ui32Port + GPIO_O_IS) | ui8Pins) : + (HWREG(ui32Port + GPIO_O_IS) & ~(ui8Pins))); + HWREG(ui32Port + GPIO_O_IEV) = ((ui32IntType & 4) ? + (HWREG(ui32Port + GPIO_O_IEV) | ui8Pins) : + (HWREG(ui32Port + GPIO_O_IEV) & ~(ui8Pins))); + + // + // Set or clear the discrete interrupt feature. This is not available + // on all parts or ports but is safe to write in all cases. + // + HWREG(ui32Port + GPIO_O_SI) = ((ui32IntType & 0x10000) ? + (HWREG(ui32Port + GPIO_O_SI) | 0x01) : + (HWREG(ui32Port + GPIO_O_SI) & ~(0x01))); +} + +//***************************************************************************** +// +//! Gets the interrupt type for a pin. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pin is the pin number. +//! +//! This function gets the interrupt type for a specified pin on the selected +//! GPIO port. The pin can be configured as a falling-edge, rising-edge, or +//! both-edges detected interrupt, or it can be configured as a low-level or +//! high-level detected interrupt. The type of interrupt detection mechanism +//! is returned and can include the \b GPIO_DISCRETE_INT flag. +//! +//! \return Returns one of the flags described for GPIOIntTypeSet(). +// +//***************************************************************************** +uint32_t +GPIOIntTypeGet(uint32_t ui32Port, uint8_t ui8Pin) +{ + uint32_t ui32IBE, ui32IS, ui32IEV, ui32SI; + + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + ASSERT(ui8Pin < 8); + + // + // Convert from a pin number to a bit position. + // + ui8Pin = 1 << ui8Pin; + + // + // Return the pin interrupt type. + // + ui32IBE = HWREG(ui32Port + GPIO_O_IBE); + ui32IS = HWREG(ui32Port + GPIO_O_IS); + ui32IEV = HWREG(ui32Port + GPIO_O_IEV); + ui32SI = HWREG(ui32Port + GPIO_O_SI); + return(((ui32IBE & ui8Pin) ? 1 : 0) | ((ui32IS & ui8Pin) ? 2 : 0) | + ((ui32IEV & ui8Pin) ? 4 : 0) | (ui32SI & 0x01) ? 0x10000 : 0); +} + +//***************************************************************************** +// +//! Sets the pad configuration for the specified pin(s). +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin(s). +//! \param ui32Strength specifies the output drive strength. +//! \param ui32PinType specifies the pin type. +//! +//! This function sets the drive strength and type for the specified pin(s) +//! on the selected GPIO port. For pin(s) configured as input ports, the +//! pad is configured as requested, but the only real effect on the input +//! is the configuration of the pull-up or pull-down termination. +//! +//! The parameter \e ui32Strength can be one of the following values: +//! +//! - \b GPIO_STRENGTH_2MA +//! - \b GPIO_STRENGTH_4MA +//! - \b GPIO_STRENGTH_8MA +//! - \b GPIO_STRENGTH_8MA_SC +//! - \b GPIO_STRENGTH_6MA +//! - \b GPIO_STRENGTH_10MA +//! - \b GPIO_STRENGTH_12MA +//! +//! where \b GPIO_STRENGTH_xMA specifies either 2, 4, or 8 mA output drive +//! strength, and \b GPIO_OUT_STRENGTH_8MA_SC specifies 8 mA output drive with +//! slew control. +//! +//! Some Tiva devices also support output drive strengths of 6, 10, and 12 +//! mA. +//! +//! The parameter \e ui32PinType can be one of the following values: +//! +//! - \b GPIO_PIN_TYPE_STD +//! - \b GPIO_PIN_TYPE_STD_WPU +//! - \b GPIO_PIN_TYPE_STD_WPD +//! - \b GPIO_PIN_TYPE_OD +//! - \b GPIO_PIN_TYPE_ANALOG +//! - \b GPIO_PIN_TYPE_WAKE_HIGH +//! - \b GPIO_PIN_TYPE_WAKE_LOW +//! +//! where \b GPIO_PIN_TYPE_STD* specifies a push-pull pin, \b GPIO_PIN_TYPE_OD* +//! specifies an open-drain pin, \b *_WPU specifies a weak pull-up, \b *_WPD +//! specifies a weak pull-down, and \b GPIO_PIN_TYPE_ANALOG specifies an analog +//! input. +//! +//! The \b GPIO_PIN_TYPE_WAKE_* settings specify the pin to be used as a +//! hibernation wake source. The pin sense level can be high or low. These +//! settings are only available on some Tiva devices. +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note A subset of GPIO pins on Tiva devices, notably those used by the +//! JTAG/SWD interface and any pin capable of acting as an NMI input, are +//! locked against inadvertent reconfiguration. These pins must be unlocked +//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR +//! registers before this function can be called. Please see the ``gpio_jtag'' +//! example application for the mechanism required and consult your part +//! datasheet for information on affected pins. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPadConfigSet(uint32_t ui32Port, uint8_t ui8Pins, + uint32_t ui32Strength, uint32_t ui32PinType) +{ + uint8_t ui8Bit; + + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + ASSERT((ui32Strength == GPIO_STRENGTH_2MA) || + (ui32Strength == GPIO_STRENGTH_4MA) || + (ui32Strength == GPIO_STRENGTH_6MA) || + (ui32Strength == GPIO_STRENGTH_8MA) || + (ui32Strength == GPIO_STRENGTH_8MA_SC) || + (ui32Strength == GPIO_STRENGTH_10MA) || + (ui32Strength == GPIO_STRENGTH_12MA)); + ASSERT((ui32PinType == GPIO_PIN_TYPE_STD) || + (ui32PinType == GPIO_PIN_TYPE_STD_WPU) || + (ui32PinType == GPIO_PIN_TYPE_STD_WPD) || + (ui32PinType == GPIO_PIN_TYPE_OD) || + (ui32PinType == GPIO_PIN_TYPE_WAKE_LOW) || + (ui32PinType == GPIO_PIN_TYPE_WAKE_HIGH) || + (ui32PinType == GPIO_PIN_TYPE_ANALOG)); + + + // + // Set the GPIO peripheral configuration register first as required. This + // register only appears in TM4E111 and later device classes, but is a + // harmless write on older devices. Walk pins 0-7 and clear or set the + // provided PC[EDMn] encoding. + // + for(ui8Bit = 0; ui8Bit < 8; ui8Bit++) + { + if(ui8Pins & (1 << ui8Bit)) + { + HWREG(ui32Port + GPIO_O_PC) = (HWREG(ui32Port + GPIO_O_PC) & + ~(0x3 << (2 * ui8Bit))); + HWREG(ui32Port + GPIO_O_PC) |= (((ui32Strength >> 5) & 0x3) << + (2 * ui8Bit)); + } + } + + // + // Set the output drive strength. + // + HWREG(ui32Port + GPIO_O_DR2R) = ((ui32Strength & 1) ? + (HWREG(ui32Port + GPIO_O_DR2R) | + ui8Pins) : + (HWREG(ui32Port + GPIO_O_DR2R) & + ~(ui8Pins))); + HWREG(ui32Port + GPIO_O_DR4R) = ((ui32Strength & 2) ? + (HWREG(ui32Port + GPIO_O_DR4R) | + ui8Pins) : + (HWREG(ui32Port + GPIO_O_DR4R) & + ~(ui8Pins))); + HWREG(ui32Port + GPIO_O_DR8R) = ((ui32Strength & 4) ? + (HWREG(ui32Port + GPIO_O_DR8R) | + ui8Pins) : + (HWREG(ui32Port + GPIO_O_DR8R) & + ~(ui8Pins))); + HWREG(ui32Port + GPIO_O_SLR) = ((ui32Strength & 8) ? + (HWREG(ui32Port + GPIO_O_SLR) | + ui8Pins) : + (HWREG(ui32Port + GPIO_O_SLR) & + ~(ui8Pins))); + + // + // Set the 12-mA drive select register. This register only appears in + // TM4E111 and later device classes, but is a harmless write on older + // devices. + // + HWREG(ui32Port + GPIO_O_DR12R) = ((ui32Strength & 0x10) ? + (HWREG(ui32Port + GPIO_O_DR12R) | + ui8Pins) : + (HWREG(ui32Port + GPIO_O_DR12R) & + ~(ui8Pins))); + + // + // Set the pin type. + // + HWREG(ui32Port + GPIO_O_ODR) = ((ui32PinType & 1) ? + (HWREG(ui32Port + GPIO_O_ODR) | ui8Pins) : + (HWREG(ui32Port + GPIO_O_ODR) & ~(ui8Pins))); + HWREG(ui32Port + GPIO_O_PUR) = ((ui32PinType & 2) ? + (HWREG(ui32Port + GPIO_O_PUR) | ui8Pins) : + (HWREG(ui32Port + GPIO_O_PUR) & ~(ui8Pins))); + HWREG(ui32Port + GPIO_O_PDR) = ((ui32PinType & 4) ? + (HWREG(ui32Port + GPIO_O_PDR) | ui8Pins) : + (HWREG(ui32Port + GPIO_O_PDR) & ~(ui8Pins))); + HWREG(ui32Port + GPIO_O_DEN) = ((ui32PinType & 8) ? + (HWREG(ui32Port + GPIO_O_DEN) | ui8Pins) : + (HWREG(ui32Port + GPIO_O_DEN) & ~(ui8Pins))); + + // + // Set the wake pin enable register and the wake level register. These + // registers only appear in TM4E111 and later device classes, but are + // harmless writes on older devices. + // + HWREG(ui32Port + GPIO_O_WAKELVL) = ((ui32PinType & 0x200) ? + (HWREG(ui32Port + GPIO_O_WAKELVL) | + ui8Pins) : + (HWREG(ui32Port + GPIO_O_WAKELVL) & + ~(ui8Pins))); + HWREG(ui32Port + GPIO_O_WAKEPEN) = ((ui32PinType & 0x300) ? + (HWREG(ui32Port + GPIO_O_WAKEPEN) | + ui8Pins) : + (HWREG(ui32Port + GPIO_O_WAKEPEN) & + ~(ui8Pins))); + + // + // Set the analog mode select register. + // + HWREG(ui32Port + GPIO_O_AMSEL) = + ((ui32PinType == GPIO_PIN_TYPE_ANALOG) ? + (HWREG(ui32Port + GPIO_O_AMSEL) | ui8Pins) : + (HWREG(ui32Port + GPIO_O_AMSEL) & ~(ui8Pins))); +} + +//***************************************************************************** +// +//! Gets the pad configuration for a pin. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pin is the pin number. +//! \param pui32Strength is a pointer to storage for the output drive strength. +//! \param pui32PinType is a pointer to storage for the output drive type. +//! +//! This function gets the pad configuration for a specified pin on the +//! selected GPIO port. The values returned in \e pui32Strength and +//! \e pui32PinType correspond to the values used in GPIOPadConfigSet(). This +//! function also works for pin(s) configured as input pin(s); however, the +//! only meaningful data returned is whether the pin is terminated with a +//! pull-up or down resistor. +//! +//! \return None +// +//***************************************************************************** +void +GPIOPadConfigGet(uint32_t ui32Port, uint8_t ui8Pin, + uint32_t *pui32Strength, uint32_t *pui32PinType) +{ + uint32_t ui32PinType, ui32Strength; + + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + ASSERT(ui8Pin < 8); + + // + // Convert from a pin number to a bit position. + // + ui8Pin = (1 << ui8Pin); + + // + // Get the drive strength for this pin. + // + ui32Strength = ((HWREG(ui32Port + GPIO_O_DR2R) & ui8Pin) ? 1 : 0); + ui32Strength |= ((HWREG(ui32Port + GPIO_O_DR4R) & ui8Pin) ? 2 : 0); + ui32Strength |= ((HWREG(ui32Port + GPIO_O_DR8R) & ui8Pin) ? 4 : 0); + ui32Strength |= ((HWREG(ui32Port + GPIO_O_SLR) & ui8Pin) ? 8 : 0); + ui32Strength |= ((HWREG(ui32Port + GPIO_O_DR12R) & ui8Pin) ? 0x10 : 0); + ui32Strength |= (((HWREG(ui32Port + GPIO_O_PC) >> + (2 * ui8Pin)) & 0x3) << 5); + *pui32Strength = ui32Strength; + + // + // Get the pin type. + // + ui32PinType = ((HWREG(ui32Port + GPIO_O_ODR) & ui8Pin) ? 1 : 0); + ui32PinType |= ((HWREG(ui32Port + GPIO_O_PUR) & ui8Pin) ? 2 : 0); + ui32PinType |= ((HWREG(ui32Port + GPIO_O_PDR) & ui8Pin) ? 4 : 0); + ui32PinType |= ((HWREG(ui32Port + GPIO_O_DEN) & ui8Pin) ? 8 : 0); + if(HWREG(ui32Port + GPIO_O_WAKEPEN) & ui8Pin) + { + ui32PinType |= ((HWREG(ui32Port + GPIO_O_WAKELVL) & ui8Pin) ? + 0x200 : 0x100); + } + *pui32PinType = ui32PinType; +} + +//***************************************************************************** +// +//! Enables the specified GPIO interrupts. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui32IntFlags is the bit mask of the interrupt sources to enable. +//! +//! This function enables the indicated GPIO interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ui32IntFlags parameter is the logical OR of any of the following: +//! +//! - \b GPIO_INT_PIN_0 - interrupt due to activity on Pin 0. +//! - \b GPIO_INT_PIN_1 - interrupt due to activity on Pin 1. +//! - \b GPIO_INT_PIN_2 - interrupt due to activity on Pin 2. +//! - \b GPIO_INT_PIN_3 - interrupt due to activity on Pin 3. +//! - \b GPIO_INT_PIN_4 - interrupt due to activity on Pin 4. +//! - \b GPIO_INT_PIN_5 - interrupt due to activity on Pin 5. +//! - \b GPIO_INT_PIN_6 - interrupt due to activity on Pin 6. +//! - \b GPIO_INT_PIN_7 - interrupt due to activity on Pin 7. +//! - \b GPIO_INT_DMA - interrupt due to DMA activity on this GPIO module. +//! +//! \note If this call is being used to enable summary interrupts on GPIO port +//! P or Q (GPIOIntTypeSet() with GPIO_DISCRETE_INT not enabled), then all +//! individual interrupts for these ports must be enabled in the GPIO module +//! using GPIOIntEnable() and all but the interrupt for pin 0 must be disabled +//! in the NVIC using the IntDisable() function. The summary interrupts for +//! the ports are routed to the INT_GPIOP0 or INT_GPIOQ0 which must be enabled +//! to handle the interrupt. If this is not done then any individual GPIO pin +//! interrupts that are left enabled also trigger the individual interrupts. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOIntEnable(uint32_t ui32Port, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Enable the interrupts. + // + HWREG(ui32Port + GPIO_O_IM) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! Disables the specified GPIO interrupts. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui32IntFlags is the bit mask of the interrupt sources to disable. +//! +//! This function disables the indicated GPIO interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ui32IntFlags parameter is the logical OR of any of the following: +//! +//! - \b GPIO_INT_PIN_0 - interrupt due to activity on Pin 0. +//! - \b GPIO_INT_PIN_1 - interrupt due to activity on Pin 1. +//! - \b GPIO_INT_PIN_2 - interrupt due to activity on Pin 2. +//! - \b GPIO_INT_PIN_3 - interrupt due to activity on Pin 3. +//! - \b GPIO_INT_PIN_4 - interrupt due to activity on Pin 4. +//! - \b GPIO_INT_PIN_5 - interrupt due to activity on Pin 5. +//! - \b GPIO_INT_PIN_6 - interrupt due to activity on Pin 6. +//! - \b GPIO_INT_PIN_7 - interrupt due to activity on Pin 7. +//! - \b GPIO_INT_DMA - interrupt due to DMA activity on this GPIO module. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOIntDisable(uint32_t ui32Port, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Disable the interrupts. + // + HWREG(ui32Port + GPIO_O_IM) &= ~(ui32IntFlags); +} + +//***************************************************************************** +// +//! Gets interrupt status for the specified GPIO port. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param bMasked specifies whether masked or raw interrupt status is +//! returned. +//! +//! If \e bMasked is set as \b true, then the masked interrupt status is +//! returned; otherwise, the raw interrupt status is returned. +//! +//! \return Returns the current interrupt status for the specified GPIO module. +//! The value returned is the logical OR of the \b GPIO_INT_* values that are +//! currently active. +// +//***************************************************************************** +uint32_t +GPIOIntStatus(uint32_t ui32Port, bool bMasked) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Return the interrupt status. + // + if(bMasked) + { + return(HWREG(ui32Port + GPIO_O_MIS)); + } + else + { + return(HWREG(ui32Port + GPIO_O_RIS)); + } +} + +//***************************************************************************** +// +//! Clears the specified interrupt sources. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui32IntFlags is the bit mask of the interrupt sources to disable. +//! +//! Clears the interrupt for the specified interrupt source(s). +//! +//! The \e ui32IntFlags parameter is the logical OR of the \b GPIO_INT_* +//! values. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +GPIOIntClear(uint32_t ui32Port, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Clear the interrupts. + // + HWREG(ui32Port + GPIO_O_ICR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! Registers an interrupt handler for a GPIO port. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param pfnIntHandler is a pointer to the GPIO port interrupt handling +//! function. +//! +//! This function ensures that the interrupt handler specified by +//! \e pfnIntHandler is called when an interrupt is detected from the selected +//! GPIO port. This function also enables the corresponding GPIO interrupt +//! in the interrupt controller; individual pin interrupts and interrupt +//! sources must be enabled with GPIOIntEnable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOIntRegister(uint32_t ui32Port, void (*pfnIntHandler)(void)) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Get the interrupt number associated with the specified GPIO. + // + ui32Int = _GPIOIntNumberGet(ui32Port); + + ASSERT(ui32Int != 0); + + // + // Register the interrupt handler. + // + IntRegister(ui32Int, pfnIntHandler); + + // + // Enable the GPIO interrupt. + // + IntEnable(ui32Int); +} + +//***************************************************************************** +// +//! Removes an interrupt handler for a GPIO port. +//! +//! \param ui32Port is the base address of the GPIO port. +//! +//! This function unregisters the interrupt handler for the specified +//! GPIO port. This function also disables the corresponding +//! GPIO port interrupt in the interrupt controller; individual GPIO interrupts +//! and interrupt sources must be disabled with GPIOIntDisable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOIntUnregister(uint32_t ui32Port) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Get the interrupt number associated with the specified GPIO. + // + ui32Int = _GPIOIntNumberGet(ui32Port); + + ASSERT(ui32Int != 0); + + // + // Disable the GPIO interrupt. + // + IntDisable(ui32Int); + + // + // Unregister the interrupt handler. + // + IntUnregister(ui32Int); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for an individual pin of a GPIO port. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui32Pin is the pin whose interrupt is to be registered. +//! \param pfnIntHandler is a pointer to the GPIO port interrupt handling +//! function. +//! +//! This function ensures that the interrupt handler specified by +//! \e pfnIntHandler is called when an interrupt is detected from the selected +//! pin of a GPIO port. This function also enables the corresponding GPIO pin +//! interrupt in the interrupt controller. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOIntRegisterPin(uint32_t ui32Port, uint32_t ui32Pin, + void (*pfnIntHandler)(void)) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT((ui32Port == GPIO_PORTP_BASE) || (ui32Port == GPIO_PORTQ_BASE)); + ASSERT((ui32Pin > 0) && (ui32Pin < 8)); + ASSERT(pfnIntHandler != 0); + + // + // Get the interrupt number associated with the specified GPIO. + // + ui32Int = _GPIOIntNumberGet(ui32Port); + + // + // Register the interrupt handler. + // + IntRegister((ui32Int + ui32Pin), pfnIntHandler); + + // + // Enable the GPIO pin interrupt. + // + IntEnable(ui32Int + ui32Pin); +} + +//***************************************************************************** +// +//! Removes an interrupt handler for an individual pin of a GPIO port. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui32Pin is the pin whose interrupt is to be unregistered. +//! +//! This function unregisters the interrupt handler for the specified pin of a +//! GPIO port. This function also disables the corresponding GPIO pin +//! interrupt in the interrupt controller. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOIntUnregisterPin(uint32_t ui32Port, uint32_t ui32Pin) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT((ui32Port == GPIO_PORTP_BASE) || (ui32Port == GPIO_PORTQ_BASE)); + ASSERT((ui32Pin > 0) && (ui32Pin < 8)); + + // + // Get the interrupt number associated with the specified GPIO. + // + ui32Int = _GPIOIntNumberGet(ui32Port); + + // + // Disable the GPIO pin interrupt. + // + IntDisable(ui32Int + ui32Pin); + + // + // UnRegister the interrupt handler. + // + IntUnregister(ui32Int + ui32Pin); +} + +//***************************************************************************** +// +//! Reads the values present of the specified pin(s). +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin(s). +//! +//! The values at the specified pin(s) are read, as specified by \e ui8Pins. +//! Values are returned for both input and output pin(s), and the value +//! for pin(s) that are not specified by \e ui8Pins are set to 0. +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \return Returns a bit-packed byte providing the state of the specified +//! pin, where bit 0 of the byte represents GPIO port pin 0, bit 1 represents +//! GPIO port pin 1, and so on. Any bit that is not specified by \e ui8Pins +//! is returned as a 0. Bits 31:8 should be ignored. +// +//***************************************************************************** +int32_t +GPIOPinRead(uint32_t ui32Port, uint8_t ui8Pins) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Return the pin value(s). + // + return(HWREG(ui32Port + (GPIO_O_DATA + (ui8Pins << 2)))); +} + +//***************************************************************************** +// +//! Writes a value to the specified pin(s). +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin(s). +//! \param ui8Val is the value to write to the pin(s). +//! +//! Writes the corresponding bit values to the output pin(s) specified by +//! \e ui8Pins. Writing to a pin configured as an input pin has no effect. +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinWrite(uint32_t ui32Port, uint8_t ui8Pins, uint8_t ui8Val) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Write the pins. + // + HWREG(ui32Port + (GPIO_O_DATA + (ui8Pins << 2))) = ui8Val; +} + +//***************************************************************************** +// +//! Configures pin(s) for use as analog-to-digital converter inputs. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin(s). +//! +//! The analog-to-digital converter input pins must be properly configured for +//! the analog-to-digital peripheral to function correctly. This function +//! provides the proper configuration for those pin(s). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into an ADC input; it +//! only configures an ADC input pin for proper operation. +//! +//! \note A subset of GPIO pins on Tiva devices, notably those used by the +//! JTAG/SWD interface and any pin capable of acting as an NMI input, are +//! locked against inadvertent reconfiguration. These pins must be unlocked +//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR +//! registers before this function can be called. Please see the ``gpio_jtag'' +//! example application for the mechanism required and consult your part +//! datasheet for information on affected pins. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeADC(uint32_t ui32Port, uint8_t ui8Pins) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Make the pin(s) be inputs. + // + GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_IN); + + // + // Set the pad(s) for analog operation. + // + GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, + GPIO_PIN_TYPE_ANALOG); +} + +//***************************************************************************** +// +//! Configures pin(s) for use as a CAN device. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin(s). +//! +//! The CAN pins must be properly configured for the CAN peripherals to +//! function correctly. This function provides a typical configuration for +//! those pin(s); other configurations may work as well depending upon the +//! board setup (for example, using the on-chip pull-ups). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into a CAN pin; it only +//! configures a CAN pin for proper operation. Note that a GPIOPinConfigure() +//! function call is also required to properly configure a pin for the CAN +//! function. +//! +//! \note A subset of GPIO pins on Tiva devices, notably those used by the +//! JTAG/SWD interface and any pin capable of acting as an NMI input, are +//! locked against inadvertent reconfiguration. These pins must be unlocked +//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR +//! registers before this function can be called. Please see the ``gpio_jtag'' +//! example application for the mechanism required and consult your part +//! datasheet for information on affected pins. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeCAN(uint32_t ui32Port, uint8_t ui8Pins) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Make the pin(s) be inputs. + // + GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use as an analog comparator input. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin(s). +//! +//! The analog comparator input pins must be properly configured for the analog +//! comparator to function correctly. This function provides the proper +//! configuration for those pin(s). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into an analog +//! comparator input; it only configures an analog comparator pin for proper +//! operation. Note that a GPIOPinConfigure() function call is also required +//! to properly configure a pin for the analog comparator function. +//! +//! \note A subset of GPIO pins on Tiva devices, notably those used by the +//! JTAG/SWD interface and any pin capable of acting as an NMI input, are +//! locked against inadvertent reconfiguration. These pins must be unlocked +//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR +//! registers before this function can be called. Please see the ``gpio_jtag'' +//! example application for the mechanism required and consult your part +//! datasheet for information on affected pins. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeComparator(uint32_t ui32Port, uint8_t ui8Pins) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Make the pin(s) be inputs. + // + GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_IN); + + // + // Set the pad(s) for analog operation. + // + GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, + GPIO_PIN_TYPE_ANALOG); +} + +//***************************************************************************** +// +//! Configures pin(s) for use as an analog comparator output. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin(s). +//! +//! The analog comparator output pins must be properly configured for the analog +//! comparator to function correctly. This function provides the proper +//! configuration for those pin(s). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +void GPIOPinTypeComparatorOutput(uint32_t ui32Port, uint8_t ui8Pins) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Make the pin(s) be inputs. + // + GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use as an clock to be output from the device. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin(s). +//! +//! The system control output pin must be properly configured for the DIVSCLK to +//! function correctly. This function provides the proper configuration for +//! those pin(s). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +void GPIOPinTypeDIVSCLK(uint32_t ui32Port, uint8_t ui8Pins) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Make the pin(s) be inputs. + // + GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the external peripheral interface. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin(s). +//! +//! The external peripheral interface pins must be properly configured for the +//! external peripheral interface to function correctly. This function +//! provides a typical configuration for those pin(s); other configurations may +//! work as well depending upon the board setup (for example, using the on-chip +//! pull-ups). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into an external +//! peripheral interface pin; it only configures an external peripheral +//! interface pin for proper operation. Note that a GPIOPinConfigure() +//! function call is also required to properly configure a pin for the +//! external peripheral interface function. +//! +//! \note A subset of GPIO pins on Tiva devices, notably those used by the +//! JTAG/SWD interface and any pin capable of acting as an NMI input, are +//! locked against inadvertent reconfiguration. These pins must be unlocked +//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR +//! registers before this function can be called. Please see the ``gpio_jtag'' +//! example application for the mechanism required and consult your part +//! datasheet for information on affected pins. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeEPI(uint32_t ui32Port, uint8_t ui8Pins) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the Ethernet peripheral as LED signals. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin(s). +//! +//! The Ethernet peripheral provides four signals that can be used to drive +//! an LED (for example, for link status/activity). This function provides a +//! typical configuration for the pins. +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into an Ethernet LED +//! pin; it only configures an Ethernet LED pin for proper operation. Note +//! that a GPIOPinConfigure() function call is also required to properly +//! configure the pin for the Ethernet LED function. +//! +//! \note A subset of GPIO pins on Tiva devices, notably those used by the +//! JTAG/SWD interface and any pin capable of acting as an NMI input, are +//! locked against inadvertent reconfiguration. These pins must be unlocked +//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR +//! registers before this function can be called. Please see the ``gpio_jtag'' +//! example application for the mechanism required and consult your part +//! datasheet for information on affected pins. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeEthernetLED(uint32_t ui32Port, uint8_t ui8Pins) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the Ethernet peripheral as MII signals. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin(s). +//! +//! The Ethernet peripheral on some parts provides a set of MII signals that +//! are used to connect to an external PHY. This function provides a typical +//! configuration for the pins. +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into an Ethernet MII +//! pin; it only configures an Ethernet MII pin for proper operation. Note +//! that a GPIOPinConfigure() function call is also required to properly +//! configure the pin for the Ethernet MII function. +//! +//! \note A subset of GPIO pins on Tiva devices, notably those used by the +//! JTAG/SWD interface and any pin capable of acting as an NMI input, are +//! locked against inadvertent reconfiguration. These pins must be unlocked +//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR +//! registers before this function can be called. Please see the ``gpio_jtag'' +//! example application for the mechanism required and consult your part +//! datasheet for information on affected pins. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeEthernetMII(uint32_t ui32Port, uint8_t ui8Pins) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use as GPIO inputs. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin(s). +//! +//! The GPIO pins must be properly configured in order to function correctly as +//! GPIO inputs. This function provides the proper configuration for those +//! pin(s). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note A subset of GPIO pins on Tiva devices, notably those used by the +//! JTAG/SWD interface and any pin capable of acting as an NMI input, are +//! locked against inadvertent reconfiguration. These pins must be unlocked +//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR +//! registers before this function can be called. Please see the ``gpio_jtag'' +//! example application for the mechanism required and consult your part +//! datasheet for information on affected pins. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeGPIOInput(uint32_t ui32Port, uint8_t ui8Pins) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Make the pin(s) be inputs. + // + GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_IN); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use as GPIO outputs. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin(s). +//! +//! The GPIO pins must be properly configured in order to function correctly as +//! GPIO outputs. This function provides the proper configuration for those +//! pin(s). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note A subset of GPIO pins on Tiva devices, notably those used by the +//! JTAG/SWD interface and any pin capable of acting as an NMI input, are +//! locked against inadvertent reconfiguration. These pins must be unlocked +//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR +//! registers before this function can be called. Please see the ``gpio_jtag'' +//! example application for the mechanism required and consult your part +//! datasheet for information on affected pins. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeGPIOOutput(uint32_t ui32Port, uint8_t ui8Pins) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); + + // + // Make the pin(s) be outputs. + // + GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_OUT); +} + +//***************************************************************************** +// +//! Configures pin(s) for use as GPIO open drain outputs. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin(s). +//! +//! The GPIO pins must be properly configured in order to function correctly as +//! GPIO outputs. This function provides the proper configuration for those +//! pin(s). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note A subset of GPIO pins on Tiva devices, notably those used by the +//! JTAG/SWD interface and any pin capable of acting as an NMI input, are +//! locked against inadvertent reconfiguration. These pins must be unlocked +//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR +//! registers before this function can be called. Please see the ``gpio_jtag'' +//! example application for the mechanism required and consult your part +//! datasheet for information on affected pins. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeGPIOOutputOD(uint32_t ui32Port, uint8_t ui8Pins) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD); + + // + // Make the pin(s) be outputs. + // + GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_OUT); +} + +//***************************************************************************** +// +//! Configures pin(s) for use as an Hibernate RTC Clock. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin(s). +//! +//! The hibernate output pin must be properly configured for the RTCCLK to +//! function correctly. This function provides the proper configuration for the +//! RTC Clock to be output from the device. +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +void GPIOPinTypeHibernateRTCCLK(uint32_t ui32Port, uint8_t ui8Pins) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Make the pin(s) be inputs. + // + GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin for use as SDA by the I2C peripheral. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin. +//! +//! The I2C pins must be properly configured for the I2C peripheral to function +//! correctly. This function provides the proper configuration for the SDA +//! pin. +//! +//! The pin is specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into an I2C SDA pin; it +//! only configures an I2C SDA pin for proper operation. Note that a +//! GPIOPinConfigure() function call is also required to properly configure a +//! pin for the I2C SDA function. +//! +//! \note A subset of GPIO pins on Tiva devices, notably those used by the +//! JTAG/SWD interface and any pin capable of acting as an NMI input, are +//! locked against inadvertent reconfiguration. These pins must be unlocked +//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR +//! registers before this function can be called. Please see the ``gpio_jtag'' +//! example application for the mechanism required and consult your part +//! datasheet for information on affected pins. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeI2C(uint32_t ui32Port, uint8_t ui8Pins) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for open-drain operation with a weak pull-up. + // + GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD); +} + +//***************************************************************************** +// +//! Configures pin for use as SCL by the I2C peripheral. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin. +//! +//! The I2C pins must be properly configured for the I2C peripheral to function +//! correctly. This function provides the proper configuration for the SCL +//! pin. +//! +//! The pin is specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into an I2C SCL pin; it +//! only configures an I2C SCL pin for proper operation. Note that a +//! GPIOPinConfigure() function call is also required to properly configure a +//! pin for the I2C SCL function. +//! +//! \note A subset of GPIO pins on Tiva devices, notably those used by the +//! JTAG/SWD interface and any pin capable of acting as an NMI input, are +//! locked against inadvertent reconfiguration. These pins must be unlocked +//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR +//! registers before this function can be called. Please see the ``gpio_jtag'' +//! example application for the mechanism required and consult your part +//! datasheet for information on affected pins. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeI2CSCL(uint32_t ui32Port, uint8_t ui8Pins) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for push-pull operation. + // + GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the LCD Controller. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin(s). +//! +//! The LCD controller pins must be properly configured for the LCD controller +//! to function correctly. This function provides a typical configuration for +//! those pin(s); other configurations may work as well depending upon the +//! board setup (for example, using the on-chip pull-ups). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into an LCD pin; it only +//! configures an LCD pin for proper operation. Note that a GPIOPinConfigure() +//! function call is also required to properly configure a pin for the LCD +//! controller function. +//! +//! \note A subset of GPIO pins on Tiva devices, notably those used by the +//! JTAG/SWD interface and any pin capable of acting as an NMI input, are +//! locked against inadvertent reconfiguration. These pins must be unlocked +//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR +//! registers before this function can be called. Please see the ``gpio_jtag'' +//! example application for the mechanism required and consult your part +//! datasheet for information on affected pins. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeLCD(uint32_t ui32Port, uint8_t ui8Pins) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation and beefed up drive. + // + GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the 1-Wire module. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin(s). +//! +//! The 1-Wire pin must be properly configured for the 1-Wire peripheral to +//! function correctly. This function provides a typical configuration for +//! those pin(s); other configurations may work as well depending upon the +//! board setup (for example, using the on-chip pull-ups). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into a 1-Wire pin; it +//! only configures a 1-Wire pin for proper operation. Note that a +//! GPIOPinConfigure() function call is also required to properly configure a +//! pin for the 1-Wire function. +//! +//! \note A subset of GPIO pins on Tiva devices, notably those used by the +//! JTAG/SWD interface and any pin capable of acting as an NMI input, are +//! locked against inadvertent reconfiguration. These pins must be unlocked +//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR +//! registers before this function can be called. Please see the ``gpio_jtag'' +//! example application for the mechanism required and consult your part +//! datasheet for information on affected pins. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeOneWire(uint32_t ui32Port, uint8_t ui8Pins) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the PWM peripheral. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin(s). +//! +//! The PWM pins must be properly configured for the PWM peripheral to function +//! correctly. This function provides a typical configuration for those +//! pin(s); other configurations may work as well depending upon the board +//! setup (for example, using the on-chip pull-ups). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into a PWM pin; it only +//! configures a PWM pin for proper operation. Note that a GPIOPinConfigure() +//! function call is also required to properly configure a pin for the PWM +//! function. +//! +//! \note A subset of GPIO pins on Tiva devices, notably those used by the +//! JTAG/SWD interface and any pin capable of acting as an NMI input, are +//! locked against inadvertent reconfiguration. These pins must be unlocked +//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR +//! registers before this function can be called. Please see the ``gpio_jtag'' +//! example application for the mechanism required and consult your part +//! datasheet for information on affected pins. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypePWM(uint32_t ui32Port, uint8_t ui8Pins) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the QEI peripheral. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin(s). +//! +//! The QEI pins must be properly configured for the QEI peripheral to function +//! correctly. This function provides a typical configuration for those +//! pin(s); other configurations may work as well depending upon the board +//! setup (for example, not using the on-chip pull-ups). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into a QEI pin; it only +//! configures a QEI pin for proper operation. Note that a GPIOPinConfigure() +//! function call is also required to properly configure a pin for the QEI +//! function. +//! +//! \note A subset of GPIO pins on Tiva devices, notably those used by the +//! JTAG/SWD interface and any pin capable of acting as an NMI input, are +//! locked against inadvertent reconfiguration. These pins must be unlocked +//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR +//! registers before this function can be called. Please see the ``gpio_jtag'' +//! example application for the mechanism required and consult your part +//! datasheet for information on affected pins. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeQEI(uint32_t ui32Port, uint8_t ui8Pins) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation with a weak pull-up. + // + GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, + GPIO_PIN_TYPE_STD_WPU); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the SSI peripheral. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin(s). +//! +//! The SSI pins must be properly configured for the SSI peripheral to function +//! correctly. This function provides a typical configuration for those +//! pin(s); other configurations may work as well depending upon the board +//! setup (for example, using the on-chip pull-ups). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into a SSI pin; it only +//! configures a SSI pin for proper operation. Note that a GPIOPinConfigure() +//! function call is also required to properly configure a pin for the SSI +//! function. +//! +//! \note A subset of GPIO pins on Tiva devices, notably those used by the +//! JTAG/SWD interface and any pin capable of acting as an NMI input, are +//! locked against inadvertent reconfiguration. These pins must be unlocked +//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR +//! registers before this function can be called. Please see the ``gpio_jtag'' +//! example application for the mechanism required and consult your part +//! datasheet for information on affected pins. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeSSI(uint32_t ui32Port, uint8_t ui8Pins) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the Timer peripheral. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin(s). +//! +//! The CCP pins must be properly configured for the timer peripheral to +//! function correctly. This function provides a typical configuration for +//! those pin(s); other configurations may work as well depending upon the +//! board setup (for example, using the on-chip pull-ups). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into a timer pin; it +//! only configures a timer pin for proper operation. Note that a +//! GPIOPinConfigure() function call is also required to properly configure a +//! pin for the CCP function. +//! +//! \note A subset of GPIO pins on Tiva devices, notably those used by the +//! JTAG/SWD interface and any pin capable of acting as an NMI input, are +//! locked against inadvertent reconfiguration. These pins must be unlocked +//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR +//! registers before this function can be called. Please see the ``gpio_jtag'' +//! example application for the mechanism required and consult your part +//! datasheet for information on affected pins. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeTimer(uint32_t ui32Port, uint8_t ui8Pins) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the Trace peripheral. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin(s). +//! +//! The Trace pins must be properly configured for the Trace peripheral to +//! function correctly. This function provides a typical configuration for +//! those pin(s). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into a trace pin; it +//! only configures a trace pin for proper operation. Note that a +//! GPIOPinConfigure() function call is also required to properly configure a +//! pin for the Trace function. +//! +//! \note A subset of GPIO pins on Tiva devices, notably those used by the +//! JTAG/SWD interface and any pin capable of acting as an NMI input, are +//! locked against inadvertent reconfiguration. These pins must be unlocked +//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR +//! registers before this function can be called. Please see the ``gpio_jtag'' +//! example application for the mechanism required and consult your part +//! datasheet for information on affected pins. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeTrace(uint32_t ui32Port, uint8_t ui8Pins) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the UART peripheral. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin(s). +//! +//! The UART pins must be properly configured for the UART peripheral to +//! function correctly. This function provides a typical configuration for +//! those pin(s); other configurations may work as well depending upon the +//! board setup (for example, using the on-chip pull-ups). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into a UART pin; it +//! only configures a UART pin for proper operation. Note that a +//! GPIOPinConfigure() function call is also required to properly configure a +//! pin for the UART function. +//! +//! \note A subset of GPIO pins on Tiva devices, notably those used by the +//! JTAG/SWD interface and any pin capable of acting as an NMI input, are +//! locked against inadvertent reconfiguration. These pins must be unlocked +//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR +//! registers before this function can be called. Please see the ``gpio_jtag'' +//! example application for the mechanism required and consult your part +//! datasheet for information on affected pins. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeUART(uint32_t ui32Port, uint8_t ui8Pins) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the USB peripheral. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin(s). +//! +//! USB analog pins must be properly configured for the USB peripheral to +//! function correctly. This function provides the proper configuration for +//! any USB analog pin(s). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into a USB pin; it only +//! configures a USB pin for proper operation. Note that a GPIOPinConfigure() +//! function call is also required to properly configure a pin for the USB +//! function. +//! +//! \note A subset of GPIO pins on Tiva devices, notably those used by the +//! JTAG/SWD interface and any pin capable of acting as an NMI input, are +//! locked against inadvertent reconfiguration. These pins must be unlocked +//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR +//! registers before this function can be called. Please see the ``gpio_jtag'' +//! example application for the mechanism required and consult your part +//! datasheet for information on affected pins. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeUSBAnalog(uint32_t ui32Port, uint8_t ui8Pins) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Make the pin(s) be inputs. + // + GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_IN); + + // + // Set the pad(s) for analog operation. + // + GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, + GPIO_PIN_TYPE_ANALOG); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the USB peripheral. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin(s). +//! +//! USB digital pins must be properly configured for the USB peripheral to +//! function correctly. This function provides a typical configuration for +//! the digital USB pin(s); other configurations may work as well depending +//! upon the board setup (for example, using the on-chip pull-ups). +//! +//! This function should only be used with EPEN and PFAULT pins as all other +//! USB pins are analog in nature or are not used in devices without OTG +//! functionality. +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into a USB pin; it only +//! configures a USB pin for proper operation. Note that a GPIOPinConfigure() +//! function call is also required to properly configure a pin for the USB +//! function. +//! +//! \note A subset of GPIO pins on Tiva devices, notably those used by the +//! JTAG/SWD interface and any pin capable of acting as an NMI input, are +//! locked against inadvertent reconfiguration. These pins must be unlocked +//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR +//! registers before this function can be called. Please see the ``gpio_jtag'' +//! example application for the mechanism required and consult your part +//! datasheet for information on affected pins. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeUSBDigital(uint32_t ui32Port, uint8_t ui8Pins) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use as a hibernate wake-on-high source. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin(s). +//! +//! The GPIO pins must be properly configured in order to function correctly as +//! hibernate wake-high inputs. This function provides the proper +//! configuration for those pin(s). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note A subset of GPIO pins on Tiva devices, notably those used by the +//! JTAG/SWD interface and any pin capable of acting as an NMI input, are +//! locked against inadvertent reconfiguration. These pins must be unlocked +//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR +//! registers before this function can be called. Please see the ``gpio_jtag'' +//! example application for the mechanism required and consult your part +//! datasheet for information on affected pins. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeWakeHigh(uint32_t ui32Port, uint8_t ui8Pins) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Make the pin(s) inputs. + // + GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_IN); + + // + // Set the pad(s) for wake-high operation. + // + GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, + GPIO_PIN_TYPE_WAKE_HIGH); +} + +//***************************************************************************** +// +//! Configures pin(s) for use as a hibernate wake-on-low source. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin(s). +//! +//! The GPIO pins must be properly configured in order to function correctly as +//! hibernate wake-low inputs. This function provides the proper +//! configuration for those pin(s). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note A subset of GPIO pins on Tiva devices, notably those used by the +//! JTAG/SWD interface and any pin capable of acting as an NMI input, are +//! locked against inadvertent reconfiguration. These pins must be unlocked +//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR +//! registers before this function can be called. Please see the ``gpio_jtag'' +//! example application for the mechanism required and consult your part +//! datasheet for information on affected pins. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeWakeLow(uint32_t ui32Port, uint8_t ui8Pins) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Make the pin(s) inputs. + // + GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_IN); + + // + // Set the pad(s) for wake-high operation. + // + GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, + GPIO_PIN_TYPE_WAKE_LOW); +} + +//***************************************************************************** +// +//! Retrieves the wake pins status. +//! +//! \param ui32Port is the base address of the GPIO port. +//! +//! This function returns the GPIO wake pin status values. The returned +//! bitfield shows low or high pin state via a value of 0 or 1. +//! +//! \note This function is not available on all devices, consult the data sheet +//! to ensure that the device you are using supports GPIO wake pins. +//! +//! \note A subset of GPIO pins on Tiva devices, notably those used by the +//! JTAG/SWD interface and any pin capable of acting as an NMI input, are +//! locked against inadvertent reconfiguration. These pins must be unlocked +//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR +//! registers before this function can be called. Please see the ``gpio_jtag'' +//! example application for the mechanism required and consult your part +//! datasheet for information on affected pins. +//! +//! \return Returns the wake pin status. +// +//***************************************************************************** +uint32_t +GPIOPinWakeStatus(uint32_t ui32Port) +{ + return(HWREG(ui32Port + GPIO_O_WAKESTAT)); +} + +//***************************************************************************** +// +//! Configures the alternate function of a GPIO pin. +//! +//! \param ui32PinConfig is the pin configuration value, specified as only one +//! of the \b GPIO_P??_??? values. +//! +//! This function configures the pin mux that selects the peripheral function +//! associated with a particular GPIO pin. Only one peripheral function at a +//! time can be associated with a GPIO pin, and each peripheral function should +//! only be associated with a single GPIO pin at a time (despite the fact that +//! many of them can be associated with more than one GPIO pin). To fully +//! configure a pin, a GPIOPinType*() function should also be called. +//! +//! The available mappings are supplied on a per-device basis in +//! pin_map.h. The \b PART_ defines controls which set of +//! defines are included so that they match the device that is being used. +//! For example, \b PART_TM4C129XNCZAD must be defined in order to get the +//! correct pin mappings for the TM4C129XNCZAD device. +//! +//! \note If the same signal is assigned to two different GPIO port +//! pins, the signal is assigned to the port with the lowest letter and the +//! assignment to the higher letter port is ignored. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinConfigure(uint32_t ui32PinConfig) +{ + uint32_t ui32Base, ui32Shift; + + // + // Check the argument. + // + ASSERT(((ui32PinConfig >> 16) & 0xff) < 18); + ASSERT(((ui32PinConfig >> 8) & 0xe3) == 0); + + // + // Extract the base address index from the input value. + // + ui32Base = (ui32PinConfig >> 16) & 0xff; + + // + // Get the base address of the GPIO module, selecting either the APB or the + // AHB aperture as appropriate. + // + if(HWREG(SYSCTL_GPIOHBCTL) & (1 << ui32Base)) + { + ui32Base = g_pui32GPIOBaseAddrs[(ui32Base << 1) + 1]; + } + else + { + ui32Base = g_pui32GPIOBaseAddrs[ui32Base << 1]; + } + + // + // Extract the shift from the input value. + // + ui32Shift = (ui32PinConfig >> 8) & 0xff; + + // + // Write the requested pin muxing value for this GPIO pin. + // + HWREG(ui32Base + GPIO_O_PCTL) = ((HWREG(ui32Base + GPIO_O_PCTL) & + ~(0xf << ui32Shift)) | + ((ui32PinConfig & 0xf) << ui32Shift)); +} + +//***************************************************************************** +// +//! Enables a GPIO pin as a trigger to start a DMA transaction. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin(s). +//! +//! This function enables a GPIO pin to be used as a trigger to start a uDMA +//! transaction. Any GPIO pin can be configured to be an external trigger for +//! the uDMA. The GPIO pin still generates interrupts if the interrupt is +//! enabled for the selected pin. +//! +//! \return None. +// +//***************************************************************************** +void +GPIODMATriggerEnable(uint32_t ui32Port, uint8_t ui8Pins) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Set the pin as a DMA trigger. + // + HWREG(ui32Port + GPIO_O_DMACTL) |= ui8Pins; +} + +//***************************************************************************** +// +//! Disables a GPIO pin as a trigger to start a DMA transaction. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin(s). +//! +//! This function disables a GPIO pin from being used as a trigger to start a +//! uDMA transaction. This function can be used to disable this feature if it +//! was enabled via a call to GPIODMATriggerEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +GPIODMATriggerDisable(uint32_t ui32Port, uint8_t ui8Pins) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Set the pin as a DMA trigger. + // + HWREG(ui32Port + GPIO_O_DMACTL) &= (~ui8Pins); +} + +//***************************************************************************** +// +//! Enables a GPIO pin as a trigger to start an ADC capture. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin(s). +//! +//! This function enables a GPIO pin to be used as a trigger to start an ADC +//! sequence. Any GPIO pin can be configured to be an external trigger for an +//! ADC sequence. The GPIO pin still generates interrupts if the interrupt is +//! enabled for the selected pin. To enable the use of a GPIO pin to trigger +//! the ADC module, the ADCSequenceConfigure() function must be called with the +//! \b ADC_TRIGGER_EXTERNAL parameter. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOADCTriggerEnable(uint32_t ui32Port, uint8_t ui8Pins) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Set the pin as a DMA trigger. + // + HWREG(ui32Port + GPIO_O_ADCCTL) |= ui8Pins; +} + +//***************************************************************************** +// +//! Disable a GPIO pin as a trigger to start an ADC capture. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin(s). +//! +//! This function disables a GPIO pin to be used as a trigger to start an ADC +//! sequence. This function can be used to disable this feature if it was +//! enabled via a call to GPIOADCTriggerEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +GPIOADCTriggerDisable(uint32_t ui32Port, uint8_t ui8Pins) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Set the pin as a DMA trigger. + // + HWREG(ui32Port + GPIO_O_ADCCTL) &= (~ui8Pins); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/hibernate.c b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/hibernate.c new file mode 100644 index 0000000000000000000000000000000000000000..a3715783871f145029f7724f525a32d00e195ef9 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/hibernate.c @@ -0,0 +1,2553 @@ +//***************************************************************************** +// +// hibernate.c - Driver for the Hibernation module +// +// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup hibernate_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include +#include "inc/hw_hibernate.h" +#include "inc/hw_ints.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/hibernate.h" +#include "driverlib/interrupt.h" +#include "driverlib/sysctl.h" + +//***************************************************************************** +// +// The delay in microseconds for writing to the Hibernation module registers. +// +//***************************************************************************** +#define DELAY_USECS 95 + +//***************************************************************************** +// +// The number of processor cycles to execute one pass of the delay loop. +// +//***************************************************************************** +#define LOOP_CYCLES 3 + +//***************************************************************************** +// +// A macro used to determine whether the target part supports Wake from IO +// pins. +// +//***************************************************************************** +#define HIBERNATE_WAKE_IO CLASS_IS_TM4C129 + +//***************************************************************************** +// +// A macro used to determine whether the target part supports Wake from IO +// pins. +// +//***************************************************************************** +#define HIBERNATE_CLOCK_OUTPUT CLASS_IS_TM4C129 + +//***************************************************************************** +// +//! \internal +//! +//! Polls until the write complete (WRC) bit in the hibernate control register +//! is set. +//! +//! \param None. +//! +//! The Hibernation module provides an indication when any write is completed. +//! This mechanism is used to pace writes to the module. This function merely +//! polls this bit and returns as soon as it is set. At this point, it is safe +//! to perform another write to the module. +//! +//! \return None. +// +//***************************************************************************** +static void +_HibernateWriteComplete(void) +{ + // + // Spin until the write complete bit is set. + // + while(!(HWREG(HIB_CTL) & HIB_CTL_WRC)) + { + } +} + +//***************************************************************************** +// +//! Enables the Hibernation module for operation. +//! +//! \param ui32HibClk is the rate of the clock supplied to the Hibernation +//! module. +//! +//! This function enables the Hibernation module for operation. This function +//! should be called before any of the Hibernation module features are used. +//! +//! The peripheral clock is the same as the processor clock. The frequency of +//! the system clock is the value returned by SysCtlClockGet() for TM4C123x +//! devices or the value returned by SysCtlClockFreqSet() for TM4C129x devices, +//! or it can be explicitly hard coded if it is constant and known (to save the +//! code/execution overhead of a call to SysCtlClockGet() or fetch of the +//! variable call holding the return value of SysCtlClockFreqSet()). +//! +//! \return None. +// +//***************************************************************************** +void +HibernateEnableExpClk(uint32_t ui32HibClk) +{ + // + // Turn on the clock enable bit. + // + HWREG(HIB_CTL) |= HIB_CTL_CLK32EN; + + // + // Wait for write complete following register load (above). + // + _HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Disables the Hibernation module for operation. +//! +//! This function disables the Hibernation module. After this function is +//! called, none of the Hibernation module features are available. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateDisable(void) +{ + // + // Turn off the clock enable bit. + // + HWREG(HIB_CTL) &= ~HIB_CTL_CLK32EN; + + // + // Wait for write completion + // + _HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Configures the clock input for the Hibernation module. +//! +//! \param ui32Config is one of the possible configuration options for the +//! clock input listed below. +//! +//! This function is used to configure the clock input for the Hibernation +//! module. The \e ui32Config parameter can be one of the following values: +//! +//! - \b HIBERNATE_OSC_DISABLE specifies that the internal oscillator +//! is powered off. This option is used when an externally supplied oscillator +//! is connected to the XOSC0 pin or to save power when the LFIOSC is used in +//! devices that have an LFIOSC in the Hibernation module. +//! - \b HIBERNATE_OSC_HIGHDRIVE specifies a higher drive strength when a 24-pF +//! filter capacitor is used with a crystal. +//! - \b HIBERNATE_OSC_LOWDRIVE specifies a lower drive strength when a 12-pF +//! filter capacitor is used with a crystal. +//! +//! On some devices, there is an option to use an internal low frequency +//! oscillator (LFIOSC) as the clock source for the Hibernation module. +//! Because of the low accuracy of this oscillator, this option should not be +//! used when the system requires a real time counter. Adding the +//! \b HIBERNATE_OSC_LFIOSC value enables the LFIOSC as the clock source to +//! the Hibernation module. +//! +//! - \b HIBERNATE_OSC_LFIOSC enables the Hibernation module's internal low +//! frequency oscillator as the clock to the Hibernation module. +//! +//! This \e ui32Config also configures how the clock output from the +//! hibernation is used to clock other peripherals in the system. The ALT +//! clock settings allow clocking a subset of the peripherals. See the +//! hibernate section in the datasheet to determine which peripherals can be +//! clocked by the ALT clock outputs from the Hibernation module. +//! The \e ui32Config parameter can have any combination of the following +//! values: +//! +//! - \b HIBERNATE_OUT_SYSCLK enables the hibernate clock output to the system +//! clock. +//! +//! The \b HIBERNATE_OSC_DISABLE option is used to disable and power down the +//! internal oscillator if an external clock source or no clock source is used +//! instead of a 32.768-kHz crystal. In the case where an external crystal is +//! used, either the \b HIBERNATE_OSC_HIGHDRIVE or \b HIBERNATE_OSC_LOWDRIVE is +//! used. These settings optimizes the oscillator drive strength to match the +//! size of the filter capacitor that is used with the external crystal +//! circuit. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateClockConfig(uint32_t ui32Config) +{ + uint32_t ui32HIBCtl; + + ASSERT((ui32Config & ~(HIBERNATE_OSC_HIGHDRIVE | HIBERNATE_OSC_LOWDRIVE | + HIBERNATE_OSC_DISABLE)) == 0); + + ui32HIBCtl = HWREG(HIB_CTL); + + // + // Clear the current configuration bits. + // + ui32HIBCtl &= ~(HIBERNATE_OSC_HIGHDRIVE | HIBERNATE_OSC_LOWDRIVE | + HIBERNATE_OSC_LFIOSC | HIBERNATE_OSC_DISABLE); + + // + // Set the new configuration bits. + // + ui32HIBCtl |= ui32Config & (HIBERNATE_OSC_HIGHDRIVE | + HIBERNATE_OSC_LOWDRIVE | + HIBERNATE_OSC_LFIOSC | + HIBERNATE_OSC_DISABLE); + + // + // Must be sure that the 32KHz clock is enabled if the hibernate is about + // to switch to it. + // + if(ui32Config & HIBERNATE_OSC_LFIOSC) + { + ui32HIBCtl |= HIB_CTL_CLK32EN; + } + + // + // Set the hibernation clocking configuration. + // + HWREG(HIB_CTL) = ui32HIBCtl; + + // + // Wait for write completion + // + _HibernateWriteComplete(); + + // + // Write the output clock configuration for devices that support + // controlling the output clocks from the hibernate module. + // + if(HIBERNATE_CLOCK_OUTPUT) + { + HWREG(HIB_CC) = ui32Config & (HIBERNATE_OUT_SYSCLK | + HIBERNATE_OUT_ALT1CLK); + } +} + +//***************************************************************************** +// +//! Enables the RTC feature of the Hibernation module. +//! +//! This function enables the RTC in the Hibernation module. The RTC can be +//! used to wake the processor from hibernation at a certain time, or to +//! generate interrupts at certain times. This function must be called before +//! using any of the RTC features of the Hibernation module. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateRTCEnable(void) +{ + // + // Turn on the RTC enable bit. + // + HWREG(HIB_CTL) |= HIB_CTL_RTCEN; + + // + // Wait for write completion + // + _HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Disables the RTC feature of the Hibernation module. +//! +//! This function disables the RTC in the Hibernation module. After calling +//! this function, the RTC features of the Hibernation module are not +//! available. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateRTCDisable(void) +{ + // + // Turn off the RTC enable bit. + // + HWREG(HIB_CTL) &= ~HIB_CTL_RTCEN; + + // + // Wait for write completion + // + _HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Forces the Hibernation module to initiate a check of the battery voltage. +//! +//! This function forces the Hibernation module to initiate a check of the +//! battery voltage immediately rather than waiting for the next check interval +//! to pass. After calling this function, the application should call the +//! HibernateBatCheckDone() function and wait for the function to return a zero +//! value before calling the HibernateIntStatus() to check if the return code +//! has the \b HIBERNATE_INT_LOW_BAT set. If \b HIBERNATE_INT_LOW_BAT is set, +//! the battery level is low. The application can also enable the +//! \b HIBERNATE_INT_LOW_BAT interrupt and wait for an interrupt to indicate +//! that the battery level is low. +//! +//! \note A hibernation request is held off if a battery check is in progress. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateBatCheckStart(void) +{ + // + // Initiated a forced battery check. + // + HWREG(HIB_CTL) |= HIB_CTL_BATCHK; + + // + // Wait for write completion + // + _HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Determines whether or not a forced battery check has completed. +//! +//! This function determines whether the forced battery check initiated by a +//! call to the HibernateBatCheckStart() function has completed. This function +//! returns a non-zero value until the battery level check has completed. Once +//! this function returns a value of zero, the Hibernation module has completed +//! the battery check and the HibernateIntStatus() function can be used to +//! check if the battery was low by checking if the value returned has the +//! \b HIBERNATE_INT_LOW_BAT set. +//! +//! \return The value is zero when the battery level check has completed or +//! non-zero if the check is still in process. +// +//***************************************************************************** +uint32_t +HibernateBatCheckDone(void) +{ + // + // Read the current state of the battery check. + // + return(HWREG(HIB_CTL) & HIB_CTL_BATCHK); +} + +//***************************************************************************** +// +//! Configures the wake conditions for the Hibernation module. +//! +//! \param ui32WakeFlags specifies which conditions should be used for waking. +//! +//! This function enables the conditions under which the Hibernation module +//! wakes. The \e ui32WakeFlags parameter is the logical OR of any combination +//! of the following: +//! +//! - \b HIBERNATE_WAKE_PIN - wake when the external wake pin is asserted. +//! - \b HIBERNATE_WAKE_RTC - wake when the RTC match occurs. +//! - \b HIBERNATE_WAKE_LOW_BAT - wake from hibernate due to a low-battery +//! level being detected. +//! - \b HIBERNATE_WAKE_GPIO - wake when a GPIO pin is asserted. +//! - \b HIBERNATE_WAKE_RESET - wake when a reset pin is asserted. +//! +//! If the \b HIBERNATE_WAKE_GPIO flag is set, then one of the GPIO +//! configuration functions GPIOPinTypeWakeHigh() or GPIOPinTypeWakeLow() must +//! be called to properly configure and enable a GPIO as a wake source for +//! hibernation. +//! +//! \note The \b HIBERNATE_WAKE_GPIO and \b HIBERNATE_WAKE_RESET parameters are +//! only available on some Tiva devices. +//! +//! \note On some Tiva devices a tamper event acts as a wake source for the +//! Hibernation module. Refer the function \b HibernateTamperEventsConfig() to +//! wake from hibernation on a tamper event. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateWakeSet(uint32_t ui32WakeFlags) +{ + // + // Check the arguments. + // + ASSERT(!(ui32WakeFlags & ~(HIBERNATE_WAKE_PIN | HIBERNATE_WAKE_RTC | + HIBERNATE_WAKE_GPIO | HIBERNATE_WAKE_RESET | + HIBERNATE_WAKE_LOW_BAT))); + + // + // Set the specified wake flags in the control register. + // + HWREG(HIB_CTL) = (ui32WakeFlags | (HWREG(HIB_CTL) & + ~(HIBERNATE_WAKE_PIN | + HIBERNATE_WAKE_RTC | + HIBERNATE_WAKE_LOW_BAT))); + + // + // Wait for write completion + // + _HibernateWriteComplete(); + + // + // Write the hibernate IO register if requested. + // + if(HIBERNATE_WAKE_IO) + { + // + // If the reset or GPIOs are begin used as a wake source then the + // the VDD3ON needs to be set to allow the pads to remained + // powered. + // + if((ui32WakeFlags & (HIBERNATE_WAKE_RESET | HIBERNATE_WAKE_GPIO)) && + ((HWREG(HIB_CTL) & HIB_CTL_VDD3ON) == 0)) + { + // + // Make sure that VDD3ON mode is enabled so that the pads can + // retain their state. + // + HWREG(HIB_CTL) |= HIB_CTL_VDD3ON; + + // + // Wait for write completion + // + _HibernateWriteComplete(); + } + + // + // Set the requested flags. + // + HWREG(HIB_IO) = (ui32WakeFlags >> 16) | HIB_IO_WUUNLK; + + // + // Spin until the write complete bit is set. + // + while((HWREG(HIB_IO) & HIB_IO_IOWRC) == 0) + { + } + + // + // Clear the write unlock bit. + // + HWREG(HIB_IO) &= ~HIB_IO_WUUNLK; + } +} + +//***************************************************************************** +// +//! Gets the currently configured wake conditions for the Hibernation module. +//! +//! This function returns the flags representing the wake configuration for the +//! Hibernation module. The return value is a combination of the following +//! flags: +//! +//! - \b HIBERNATE_WAKE_PIN - wake when the external wake pin is asserted +//! - \b HIBERNATE_WAKE_RTC - wake when the RTC matches occurs +//! - \b HIBERNATE_WAKE_LOW_BAT - wake from hibernation due to a low-battery +//! level being detected +//! - \b HIBERNATE_WAKE_GPIO - wake when a GPIO pin is asserted +//! - \b HIBERNATE_WAKE_RESET - wake when a reset pin is asserted +//! +//! \note The \b HIBERNATE_WAKE_LOW_BAT, \b HIBERNATE_WAKE_GPIO, and +//! \b HIBERNATE_WAKE_RESET parameters are only available on some Tiva devices. +//! +//! \note On some Tiva devices a tamper event acts as a wake source for the +//! Hibernation module. Refer the function \b HibernateTamperEventsConfig() to +//! wake from hibernation on a tamper event. +//! +//! \return Returns flags indicating the configured wake conditions. +// +//***************************************************************************** +uint32_t +HibernateWakeGet(void) +{ + uint32_t ui32Ctrl; + + // + // Read the wake bits from the control register and return those bits to + // the caller. + // + if(HIBERNATE_WAKE_IO) + { + ui32Ctrl = HWREG(HIB_CTL); + return((ui32Ctrl & (HIBERNATE_WAKE_PIN | HIBERNATE_WAKE_RTC | + HIBERNATE_WAKE_LOW_BAT)) | + ((HWREG(HIB_IO) << 16) & (HIBERNATE_WAKE_RESET | + HIBERNATE_WAKE_GPIO))); + } + else + { + return(HWREG(HIB_CTL) & (HIBERNATE_WAKE_PIN | HIBERNATE_WAKE_RTC | + HIBERNATE_WAKE_LOW_BAT)); + } +} + +//***************************************************************************** +// +//! Configures the low-battery detection. +//! +//! \param ui32LowBatFlags specifies behavior of low-battery detection. +//! +//! This function enables the low-battery detection and whether hibernation is +//! allowed if a low battery is detected. If low-battery detection is enabled, +//! then a low-battery condition is indicated in the raw interrupt status +//! register, which can be enabled to trigger an interrupt. Optionally, +//! hibernation can be aborted if a low battery condition is detected. +//! +//! The \e ui32LowBatFlags parameter is one of the following values: +//! +//! - \b HIBERNATE_LOW_BAT_DETECT - detect a low-battery condition +//! - \b HIBERNATE_LOW_BAT_ABORT - detect a low-battery condition and abort +//! hibernation if low-battery is detected +//! +//! The other setting in the \e ui32LowBatFlags allows the caller to set one of +//! the following voltage level trigger values : +//! +//! - \b HIBERNATE_LOW_BAT_1_9V - voltage low level is 1.9 V +//! - \b HIBERNATE_LOW_BAT_2_1V - voltage low level is 2.1 V +//! - \b HIBERNATE_LOW_BAT_2_3V - voltage low level is 2.3 V +//! - \b HIBERNATE_LOW_BAT_2_5V - voltage low level is 2.5 V +//! +//! \b Example: Abort hibernate if the voltage level is below 2.1 V. +//! +//! \verbatim +//! HibernateLowBatSet(HIBERNATE_LOW_BAT_ABORT | HIBERNATE_LOW_BAT_2_1V); +//! \endverbatim +//! +//! \return None. +// +//***************************************************************************** +void +HibernateLowBatSet(uint32_t ui32LowBatFlags) +{ + // + // Check the arguments. + // + ASSERT(!(ui32LowBatFlags & + ~(HIB_CTL_VBATSEL_M | HIBERNATE_LOW_BAT_ABORT))); + + // + // Set the low-battery detect and abort bits in the control register, + // according to the parameter. + // + HWREG(HIB_CTL) = (ui32LowBatFlags | + (HWREG(HIB_CTL) & ~(HIB_CTL_VBATSEL_M | + HIBERNATE_LOW_BAT_ABORT))); + + // + // Wait for write completion + // + _HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Gets the currently configured low-battery detection behavior. +//! +//! This function returns a value representing the currently configured low +//! battery detection behavior. +//! +//! The return value is a combination of the values described in the +//! HibernateLowBatSet() function. +//! +//! \return Returns a value indicating the configured low-battery detection. +// +//***************************************************************************** +uint32_t +HibernateLowBatGet(void) +{ + // + // Read the supported low bat bits from the control register and return + // those bits to the caller. + // + return(HWREG(HIB_CTL) & (HIB_CTL_VBATSEL_M | HIBERNATE_LOW_BAT_ABORT)); +} + +//***************************************************************************** +// +//! Sets the value of the real time clock (RTC) counter. +//! +//! \param ui32RTCValue is the new value for the RTC. +//! +//! This function sets the value of the RTC. The RTC counter contains the +//! count in seconds when a 32.768kHz clock source is in use. The RTC must be +//! enabled by calling HibernateRTCEnable() before calling this function. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateRTCSet(uint32_t ui32RTCValue) +{ + // + // Load register requires unlock. + // + HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY; + _HibernateWriteComplete(); + + // + // Write the new RTC value to the RTC load register. + // + HWREG(HIB_RTCLD) = ui32RTCValue; + + // + // Wait for write completion + // + _HibernateWriteComplete(); + + // + // Unlock. + // + HWREG(HIB_LOCK) = 0; + _HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Gets the value of the real time clock (RTC) counter. +//! +//! This function gets the value of the RTC and returns it to the caller. +//! +//! \return Returns the value of the RTC counter in seconds. +// +//***************************************************************************** +uint32_t +HibernateRTCGet(void) +{ + // + // Return the value of the RTC counter register to the caller. + // + return(HWREG(HIB_RTCC)); +} + +//***************************************************************************** +// +//! Sets the value of the RTC match register. +//! +//! \param ui32Match is the index of the match register. +//! \param ui32Value is the value for the match register. +//! +//! This function sets a match register for the RTC. The Hibernation +//! module can be configured to wake from hibernation, and/or generate an +//! interrupt when the value of the RTC counter is the same as the match +//! register. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateRTCMatchSet(uint32_t ui32Match, uint32_t ui32Value) +{ + ASSERT(ui32Match == 0); + + // + // Write the new match value to the match register. + // + HWREG(HIB_RTCM0) = ui32Value; + + // + // Wait for write completion + // + _HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Gets the value of the requested RTC match register. +//! +//! \param ui32Match is the index of the match register. +//! +//! This function gets the value of the match register for the RTC. The only +//! value that can be used with the \e ui32Match parameter is zero, other +//! values are reserved for future use. +//! +//! \return Returns the value of the requested match register. +// +//***************************************************************************** +uint32_t +HibernateRTCMatchGet(uint32_t ui32Match) +{ + ASSERT(ui32Match == 0); + + // + // Return the value of the match register to the caller. + // + return(HWREG(HIB_RTCM0)); +} + +//***************************************************************************** +// +//! Sets the value of the RTC sub second match register. +//! +//! \param ui32Match is the index of the match register. +//! \param ui32Value is the value for the sub second match register. +//! +//! This function sets the sub second match register for the RTC in 1/32768 +//! of a second increments. The Hibernation module can be configured to wake +//! from hibernation, and/or generate an interrupt when the value of the RTC +//! counter is the same as the match combined with the sub second match +//! register. The only value that can be used with the \e ui32Match +//! parameter is zero, other values are reserved for future use. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateRTCSSMatchSet(uint32_t ui32Match, uint32_t ui32Value) +{ + ASSERT(ui32Match == 0); + + // + // Write the new sub second match value to the sub second match register. + // + HWREG(HIB_RTCSS) = ui32Value << HIB_RTCSS_RTCSSM_S; + + // + // Wait for write complete to be signaled on later devices. + // + _HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Returns the value of the requested RTC sub second match register. +//! +//! \param ui32Match is the index of the match register. +//! +//! This function returns the current value of the sub second match register +//! for the RTC. The value returned is in 1/32768 second increments. The only +//! value that can be used with the \e ui32Match parameter is zero, other +//! values are reserved for future use. +//! +//! \return Returns the value of the requested sub section match register. +// +//***************************************************************************** +uint32_t +HibernateRTCSSMatchGet(uint32_t ui32Match) +{ + ASSERT(ui32Match == 0); + + // + // Read the current second RTC count. + // + return(HWREG(HIB_RTCSS) >> HIB_RTCSS_RTCSSM_S); +} + +//***************************************************************************** +// +//! Returns the current value of the RTC sub second count. +//! +//! This function returns the current value of the sub second count for the RTC +//! in 1/32768 of a second increments. The only value that can be used with +//! the \e ui32Match parameter is zero, other values are reserved for future +//! use. +//! +//! \return The current RTC sub second count in 1/32768 seconds. +// +//***************************************************************************** +uint32_t +HibernateRTCSSGet(void) +{ + // + // Read the current second RTC count. + // + return(HWREG(HIB_RTCSS) & HIB_RTCSS_RTCSSC_M); +} + +//***************************************************************************** +// +//! Sets the value of the RTC pre-divider trim register. +//! +//! \param ui32Trim is the new value for the pre-divider trim register. +//! +//! This function sets the value of the pre-divider trim register. The input +//! time source is divided by the pre-divider to achieve a one-second clock +//! rate. Once every 64 seconds, the value of the pre-divider trim register is +//! applied to the pre-divider to allow fine-tuning of the RTC rate, in order +//! to make corrections to the rate. The software application can make +//! adjustments to the pre-divider trim register to account for variations in +//! the accuracy of the input time source. The nominal value is 0x7FFF, and it +//! can be adjusted up or down in order to fine-tune the RTC rate. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateRTCTrimSet(uint32_t ui32Trim) +{ + // + // Check the arguments. + // + ASSERT(ui32Trim < 0x10000); + + // + // Write the new trim value to the trim register. + // + HWREG(HIB_RTCT) = ui32Trim; + + // + // Wait for write completion + // + _HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Gets the value of the RTC pre-divider trim register. +//! +//! This function gets the value of the pre-divider trim register. This +//! function can be used to get the current value of the trim register prior +//! to making an adjustment by using the HibernateRTCTrimSet() function. +//! +//! \return None. +// +//***************************************************************************** +uint32_t +HibernateRTCTrimGet(void) +{ + // + // Return the value of the trim register to the caller. + // + return(HWREG(HIB_RTCT)); +} + +//***************************************************************************** +// +//! Stores data in the battery-backed memory of the Hibernation module. +//! +//! \param pui32Data points to the data that the caller wants to store in the +//! memory of the Hibernation module. +//! \param ui32Count is the count of 32-bit words to store. +//! +//! Stores a set of data in the Hibernation module battery-backed memory. +//! This memory is preserved when the power to the processor is turned off +//! and can be used to store application state information that is needed when +//! the processor wakes. Up to 16 32-bit words can be stored in the +//! battery-backed memory. The data can be restored by calling the +//! HibernateDataGet() function. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateDataSet(uint32_t *pui32Data, uint32_t ui32Count) +{ + uint32_t ui32Idx; + + // + // Check the arguments. + // + ASSERT(ui32Count <= 64); + ASSERT(pui32Data != 0); + + // + // Loop through all the words to be stored, storing one at a time. + // + for(ui32Idx = 0; ui32Idx < ui32Count; ui32Idx++) + { + // + // Write a word to the battery-backed storage area. + // + HWREG(HIB_DATA + (ui32Idx * 4)) = pui32Data[ui32Idx]; + + // + // Wait for write completion + // + _HibernateWriteComplete(); + } +} + +//***************************************************************************** +// +//! Reads a set of data from the battery-backed memory of the Hibernation +//! module. +//! +//! \param pui32Data points to a location where the data that is read from the +//! Hibernation module is stored. +//! \param ui32Count is the count of 32-bit words to read. +//! +//! This function retrieves a set of data from the Hibernation module +//! battery-backed memory that was previously stored with the +//! HibernateDataSet() function. The caller must ensure that \e pui32Data +//! points to a large enough memory block to hold all the data that is read +//! from the battery-backed memory. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateDataGet(uint32_t *pui32Data, uint32_t ui32Count) +{ + uint32_t ui32Idx; + + // + // Check the arguments. + // + ASSERT(ui32Count <= 64); + ASSERT(pui32Data != 0); + + // + // Loop through all the words to be restored, reading one at a time. + // + for(ui32Idx = 0; ui32Idx < ui32Count; ui32Idx++) + { + // + // Read a word from the battery-backed storage area. No delay is + // required between reads. + // + pui32Data[ui32Idx] = HWREG(HIB_DATA + (ui32Idx * 4)); + } +} + +//***************************************************************************** +// +//! Requests hibernation mode. +//! +//! This function requests the Hibernation module to disable the external +//! regulator, thus removing power from the processor and all peripherals. The +//! Hibernation module remains powered from the battery or auxiliary power +//! supply. +//! +//! The Hibernation module re-enables the external regulator when one of +//! the configured wake conditions occurs (such as RTC match or external +//! \b WAKE pin). When the power is restored, the processor goes through a +//! power-on reset although the Hibernation module is not reset. The processor +//! can retrieve saved state information with the HibernateDataGet() function. +//! Prior to calling the function to request hibernation mode, the conditions +//! for waking must have already been set by using the HibernateWakeSet() +//! function. +//! +//! Note that this function may return because some time may elapse before the +//! power is actually removed, or it may not be removed at all. For this +//! reason, the processor continues to execute instructions for some time, +//! and the caller should be prepared for this function to return. There are +//! various reasons why the power may not be removed. For example, if the +//! HibernateLowBatSet() function was used to configure an abort if low +//! battery is detected, then the power is not removed if the battery +//! voltage is too low. There may be other reasons related to the external +//! circuit design, that a request for hibernation may not actually occur. +//! +//! For all these reasons, the caller must be prepared for this function to +//! return. The simplest way to handle it is to just enter an infinite loop +//! and wait for the power to be removed. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateRequest(void) +{ + // + // Set the bit in the control register to cut main power to the processor. + // + HWREG(HIB_CTL) |= HIB_CTL_HIBREQ; + + // + // Wait for write completion + // + _HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Enables interrupts for the Hibernation module. +//! +//! \param ui32IntFlags is the bit mask of the interrupts to be enabled. +//! +//! This function enables the specified interrupt sources from the Hibernation +//! module. +//! +//! The \e ui32IntFlags parameter must be the logical OR of any combination of +//! the following: +//! +//! - \b HIBERNATE_INT_WR_COMPLETE - write complete interrupt +//! - \b HIBERNATE_INT_PIN_WAKE - wake from pin interrupt +//! - \b HIBERNATE_INT_LOW_BAT - low-battery interrupt +//! - \b HIBERNATE_INT_RTC_MATCH_0 - RTC match 0 interrupt +//! - \b HIBERNATE_INT_VDDFAIL - supply failure interrupt. +//! - \b HIBERNATE_INT_RESET_WAKE - wake from reset pin interrupt +//! - \b HIBERNATE_INT_GPIO_WAKE - wake from GPIO pin or reset pin interrupt. +//! +//! \note The \b HIBERNATE_INT_RESET_WAKE, \b HIBERNATE_INT_GPIO_WAKE, and +//! \b HIBERNATE_INT_VDDFAIL settings are not available on all Tiva devices. +//! Please consult the data sheet for the Tiva device that you are using to +//! determine if these interrupt sources are available. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateIntEnable(uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(!(ui32IntFlags & ~(HIBERNATE_INT_PIN_WAKE | HIBERNATE_INT_LOW_BAT | + HIBERNATE_INT_VDDFAIL | + HIBERNATE_INT_RESET_WAKE | + HIBERNATE_INT_GPIO_WAKE | + HIBERNATE_INT_RTC_MATCH_0 | + HIBERNATE_INT_WR_COMPLETE))); + + // + // Set the specified interrupt mask bits. + // + HWREG(HIB_IM) |= ui32IntFlags; + + // + // Wait for write completion + // + _HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Disables interrupts for the Hibernation module. +//! +//! \param ui32IntFlags is the bit mask of the interrupts to be disabled. +//! +//! This function disables the specified interrupt sources from the +//! Hibernation module. +//! +//! The \e ui32IntFlags parameter has the same definition as the +//! \e ui32IntFlags parameter to the HibernateIntEnable() function. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateIntDisable(uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(!(ui32IntFlags & ~(HIBERNATE_INT_PIN_WAKE | HIBERNATE_INT_LOW_BAT | + HIBERNATE_INT_VDDFAIL | + HIBERNATE_INT_RESET_WAKE | + HIBERNATE_INT_GPIO_WAKE | + HIBERNATE_INT_RTC_MATCH_0 | + HIBERNATE_INT_WR_COMPLETE))); + + // + // Clear the specified interrupt mask bits. + // + HWREG(HIB_IM) &= ~ui32IntFlags; + + // + // Wait for write completion + // + _HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Returns the hibernate module interrupt number. +//! +//! This function returns the interrupt number for the hibernate module. +//! +//! \return Returns a hibernate interrupt number or 0 if the interrupt does not +//! exist. +// +//***************************************************************************** +static uint32_t +_HibernateIntNumberGet(void) +{ + uint32_t ui32Int; + + // + // Find the valid interrupt number for the hibernate module. + // + if(CLASS_IS_TM4C129) + { + ui32Int = INT_HIBERNATE_TM4C129; + } + else + { + ui32Int = INT_HIBERNATE_TM4C123; + } + + return(ui32Int); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the Hibernation module interrupt. +//! +//! \param pfnHandler points to the function to be called when a hibernation +//! interrupt occurs. +//! +//! This function registers the interrupt handler in the system interrupt +//! controller. The interrupt is enabled at the global level, but individual +//! interrupt sources must still be enabled with a call to +//! HibernateIntEnable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateIntRegister(void (*pfnHandler)(void)) +{ + uint32_t ui32Int; + + // + // Get the interrupt number for the Hibernate module. + // + ui32Int = _HibernateIntNumberGet(); + + ASSERT(ui32Int != 0); + + // + // Register the interrupt handler. + // + IntRegister(ui32Int, pfnHandler); + + // + // Enable the hibernate module interrupt. + // + IntEnable(ui32Int); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the Hibernation module interrupt. +//! +//! This function unregisters the interrupt handler in the system interrupt +//! controller. The interrupt is disabled at the global level, and the +//! interrupt handler is no longer called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateIntUnregister(void) +{ + uint32_t ui32Int; + + // + // Get the interrupt number for the Hibernate module. + // + ui32Int = _HibernateIntNumberGet(); + + ASSERT(ui32Int != 0); + + // + // Disable the hibernate interrupt. + // + IntDisable(ui32Int); + + // + // Unregister the interrupt handler. + // + IntUnregister(ui32Int); +} + +//***************************************************************************** +// +//! Gets the current interrupt status of the Hibernation module. +//! +//! \param bMasked is false to retrieve the raw interrupt status, and true to +//! retrieve the masked interrupt status. +//! +//! This function returns the interrupt status of the Hibernation module. The +//! caller can use this function to determine the cause of a hibernation +//! interrupt. Either the masked or raw interrupt status can be returned. +//! +//! \note A wake from reset pin also signals a wake from GPIO pin with the +//! value returned being HIBERNATE_INT_GPIO_WAKE | HIBERNATE_INT_RESET_WAKE. +//! Hence a wake from reset pin should take priority over wake from GPIO pin. +//! +//! \return Returns the interrupt status as a bit field with the values as +//! described in the HibernateIntEnable() function. +// +//***************************************************************************** +uint32_t +HibernateIntStatus(bool bMasked) +{ + // + // Read and return the Hibernation module raw or masked interrupt status. + // + if(bMasked == true) + { + return(HWREG(HIB_MIS)); + } + else + { + return(HWREG(HIB_RIS)); + } +} + +//***************************************************************************** +// +//! Clears pending interrupts from the Hibernation module. +//! +//! \param ui32IntFlags is the bit mask of the interrupts to be cleared. +//! +//! This function clears the specified interrupt sources. This function must +//! be called within the interrupt handler or else the handler is called again +//! upon exit. +//! +//! The \e ui32IntFlags parameter has the same definition as the +//! \e ui32IntFlags parameter to the HibernateIntEnable() function. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +HibernateIntClear(uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(!(ui32IntFlags & ~(HIBERNATE_INT_PIN_WAKE | HIBERNATE_INT_LOW_BAT | + HIBERNATE_INT_VDDFAIL | + HIBERNATE_INT_RESET_WAKE | + HIBERNATE_INT_GPIO_WAKE | + HIBERNATE_INT_RTC_MATCH_0 | + HIBERNATE_INT_WR_COMPLETE))); + + // + // Write the specified interrupt bits into the interrupt clear register. + // + HWREG(HIB_IC) |= ui32IntFlags; + + // + // Wait for write completion + // + _HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Checks to see if the Hibernation module is already powered up. +//! +//! This function queries the control register to determine if the module is +//! already active. This function can be called at a power-on reset to help +//! determine if the reset is due to a wake from hibernation or a cold start. +//! If the Hibernation module is already active, then it does not need to be +//! re-enabled, and its status can be queried immediately. +//! +//! The software application should also use the HibernateIntStatus() function +//! to read the raw interrupt status to determine the cause of the wake. The +//! HibernateDataGet() function can be used to restore state. These +//! combinations of functions can be used by the software to determine if the +//! processor is waking from hibernation and the appropriate action to take as +//! a result. +//! +//! \return Returns \b true if the module is already active, and \b false if +//! not. +// +//***************************************************************************** +uint32_t +HibernateIsActive(void) +{ + // + // Read the control register, and return true if the module is enabled. + // + return(HWREG(HIB_CTL) & HIB_CTL_CLK32EN ? 1 : 0); +} + +//***************************************************************************** +// +//! Enables GPIO retention after wake from hibernation. +//! +//! This function enables the GPIO pin state to be maintained during +//! hibernation and remain active even when waking from hibernation. The GPIO +//! module itself is reset upon entering hibernation and no longer controls the +//! output pins. To maintain the current output level after waking from +//! hibernation, the GPIO module must be reconfigured and then the +//! HibernateGPIORetentionDisable() function must be called to return control +//! of the GPIO pin to the GPIO module. +//! +//! \note The hibernation GPIO retention setting is not available on all +//! Tiva devices. Please consult the data sheet to determine if the +//! device you are using supports this feature in the Hibernation module. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateGPIORetentionEnable(void) +{ + // + // Enable power to the pads and enable GPIO retention during hibernate. + // + HWREG(HIB_CTL) |= HIB_CTL_VDD3ON | HIB_CTL_RETCLR; + + // + // Wait for write completion + // + _HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Disables GPIO retention after wake from hibernation. +//! +//! This function disables the retention of the GPIO pin state during +//! hibernation and allows the GPIO pins to be controlled by the system. If +//! the HibernateGPIORetentionEnable() function is called before entering +//! hibernation, this function must be called after returning from hibernation +//! to allow the GPIO pins to be controlled by GPIO module. +//! +//! \note The hibernate GPIO retention setting is not available on all +//! Tiva devices. Please consult the data sheet to determine if the +//! device you are using supports this feature in the Hibernation module. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateGPIORetentionDisable(void) +{ + // + // Reset the GPIO configuration after waking from hibernate and disable + // the hibernate power to the pads. + // + HWREG(HIB_CTL) &= ~(HIB_CTL_RETCLR | HIB_CTL_VDD3ON); + + // + // Wait for write completion + // + _HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Returns the current setting for GPIO retention. +//! +//! This function returns the current setting for GPIO retention in the +//! hibernate module. +//! +//! \note The hibernation GPIO retention setting is not available on all +//! Tiva devices. Please consult the data sheet to determine if the +//! device you are using supports this feature in the Hibernation module. +//! +//! \return Returns true if GPIO retention is enabled and false if GPIO +//! retention is disabled. +// +//***************************************************************************** +bool +HibernateGPIORetentionGet(void) +{ + // + // Read the current GPIO retention configuration. + // + if((HWREG(HIB_CTL) & (HIB_CTL_RETCLR | HIB_CTL_VDD3ON)) == + (HIB_CTL_RETCLR | HIB_CTL_VDD3ON)) + { + return(true); + } + return(false); +} + +//***************************************************************************** +// +//! Configures the Hibernation module's internal counter mode. +//! +//! \param ui32Config is the configuration to use for the Hibernation module's +//! counter. +//! +//! This function configures the Hibernate module's counter mode to operate +//! as a standard RTC counter or to operate in a calendar mode. The +//! \e ui32Config parameter is used to provide the configuration for +//! the counter and must include only one of the following values: +//! +//! - \b HIBERNATE_COUNTER_24HR specifies 24-hour calendar mode. +//! - \b HIBERNATE_COUNTER_12HR specifies 12-hour AM/PM calendar mode. +//! - \b HIBERNATE_COUNTER_RTC specifies RTC counter mode. +//! +//! The HibernateCalendar functions can only be called when either +//! \b HIBERNATE_COUNTER_24HR or \b HIBERNATE_COUNTER_12HR is specified. +//! +//! \b Example: Configure hibernate counter to 24-hour calendar mode. +//! +//! \verbatim +//! +//! // +//! // Configure the hibernate module counter to 24-hour calendar mode. +//! // +//! HibernateCounterMode(HIBERNATE_COUNTER_24HR); +//! +//! \endverbatim +//! +//! \note The hibernate calendar mode is not available on all Tiva +//! devices. Please consult the data sheet to determine if the device you are +//! using supports this feature in the Hibernation module. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateCounterMode(uint32_t ui32Config) +{ + // + // Set the requested configuration. + // + HWREG(HIB_CALCTL) = ui32Config; + + // + // Wait for write completion + // + _HibernateWriteComplete(); +} + +//***************************************************************************** +// +// Internal function to parse the time structure to set the calendar fields. +// +//***************************************************************************** +static void +_HibernateCalendarSet(uint32_t ui32Reg, struct tm *psTime) +{ + uint32_t ui32Time, ui32Date; + + ASSERT(HWREG(HIB_CALCTL) & HIB_CALCTL_CALEN); + + // + // Minutes and seconds are consistent in all modes. + // + ui32Time = (((psTime->tm_min << HIB_CALLD0_MIN_S) & HIB_CALLD0_MIN_M) | + ((psTime->tm_sec << HIB_CALLD0_SEC_S) & HIB_CALLD0_SEC_M)); + + // + // 24 Hour time is used directly for Calendar set. + // + if(HWREG(HIB_CALCTL) & HIB_CALCTL_CAL24) + { + ui32Time |= (psTime->tm_hour << HIB_CALLD0_HR_S); + + // + // for Calendar match, if it is every hour, AMPM bit should be clear + // + if((ui32Reg == HIB_CALM0) && (psTime->tm_hour == 0xFF) ) + { + // + // clear AMPM bit + // + ui32Time &= ~HIB_CAL0_AMPM; + } + } + else + { + // + // In AM/PM time hours have to be capped at 12. + // If the hours are all 1s, it means the match for the hour is + // always true. We need to set 1F in the hw field. + // + if(psTime->tm_hour == 0xFF) + { + // + // Match every hour. + // + ui32Time |= HIB_CALLD0_HR_M; + } + else if(psTime->tm_hour >= 12) + { + // + // Need to set the PM bit if it is noon or later. + // + ui32Time |= (((psTime->tm_hour - 12) << HIB_CALLD0_HR_S) | + HIB_CAL0_AMPM); + } + else + { + // + // All other times are normal and AM. + // + ui32Time |= (psTime->tm_hour << HIB_CALLD0_HR_S); + } + } + + // + // Create the date in the correct register format. + // + if(ui32Reg == HIB_CAL0) + { + // + // We must add 1 to the month, since the time structure lists + // the month from 0 to 11 and the HIB lists it from 1 to 12. + // + ui32Date = ((psTime->tm_mday << HIB_CAL1_DOM_S) | + ((psTime->tm_mon + 1) << HIB_CAL1_MON_S) | + (psTime->tm_wday << HIB_CAL1_DOW_S) | + ((psTime->tm_year - 100) << HIB_CAL1_YEAR_S)); + } + else + { + // + // Wday, month and year are not included in the match + // Functionality. + // + if(psTime->tm_mday == 0xFF) + { + // + // program 0 to match every day + // + ui32Date = 0 << HIB_CAL1_DOM_M; + } + else + { + ui32Date = (psTime->tm_mday << HIB_CAL1_DOM_S); + } + } + + // + // Load register requires unlock. + // + if(ui32Reg == HIB_CAL0) + { + // + // Unlock the hibernate counter load registers. + // + HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY; + _HibernateWriteComplete(); + } + + // + // Set the requested time and date. + // + if(ui32Reg == HIB_CAL0) + { + HWREG(HIB_CALLD0) = ui32Time; + _HibernateWriteComplete(); + HWREG(HIB_CALLD1) = ui32Date; + _HibernateWriteComplete(); + } + else + { + HWREG(HIB_CALM0) = ui32Time; + _HibernateWriteComplete(); + HWREG(HIB_CALM1) = ui32Date; + _HibernateWriteComplete(); + } + + // + // Load register requires unlock. + // + if(ui32Reg == HIB_CAL0) + { + // + // Lock the hibernate counter load registers. + // + HWREG(HIB_LOCK) = 0; + _HibernateWriteComplete(); + } +} + +//***************************************************************************** +// +//! Sets the Hibernation module's date and time in calendar mode. +//! +//! \param psTime is the structure that holds the information for the current +//! date and time. +//! +//! This function uses the \e psTime parameter to set the current date and +//! time when the Hibernation module is in calendar mode. Regardless of +//! whether 24-hour or 12-hour mode is in use, the \e psTime structure uses a +//! 24-hour representation of the time. This function can only be called when +//! the hibernate counter is configured in calendar mode using the +//! HibernateCounterMode() function with one of the calendar modes. +//! +//! \note The hibernate calendar mode is not available on all Tiva +//! devices. Please consult the data sheet to determine if the device you are +//! using supports this feature in the Hibernation module. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateCalendarSet(struct tm *psTime) +{ + // + // Load a new date/time. + // + _HibernateCalendarSet(HIB_CAL0, psTime); +} + +//***************************************************************************** +// +//! Returns the Hibernation module's date and time in calendar mode. +//! +//! \param psTime is the structure that is filled with the current date and +//! time. +//! +//! This function returns the current date and time in the structure provided +//! by the \e psTime parameter. Regardless of the calendar mode, the +//! \e psTime parameter uses a 24-hour representation of the time. This +//! function can only be called when the Hibernation module is configured in +//! calendar mode using the HibernateCounterMode() function with one of the +//! calendar modes. +//! +//! The only case where this function fails and returns a non-zero value is +//! when the function detects that the counter is passing from the last second +//! of the day to the first second of the next day. This exception must be +//! handled in the application by waiting at least one second before calling +//! again to get the updated calendar information. +//! +//! \note The hibernate calendar mode is not available on all Tiva +//! devices. Please consult the data sheet to determine if the device you are +//! using supports this feature in the Hibernation module. +//! +//! \return Returns zero if the time and date were read successfully and +//! returns a non-zero value if the \e psTime structure was not updated. +// +//***************************************************************************** +int +HibernateCalendarGet(struct tm *psTime) +{ + uint32_t ui32Date, ui32Time; + + ASSERT(HWREG(HIB_CALCTL) & HIB_CALCTL_CALEN); + + // + // Wait for the value to be valid, this should never be more than a few + // loops and should never hang. + // + do + { + ui32Date = HWREG(HIB_CAL1); + } + while((ui32Date & HIB_CAL1_VALID) == 0); + + // + // Wait for the value to be valid, this should never be more than a few + // loops and should never hang. + // + do + { + ui32Time = HWREG(HIB_CAL0); + } + while((ui32Time & HIB_CAL0_VALID) == 0); + + // + // The date changed after reading the time so fail this call and let the + // application call again since it knows how int32_t to wait until another + // second passes. + // + if(ui32Date != HWREG(HIB_CAL1)) + { + return(-1); + } + + // + // Populate the date and time fields in the psTime structure. + // We must subtract 1 from the month, since the time structure lists + // the month from 0 to 11 and the HIB lists it from 1 to 12. + // + psTime->tm_min = (ui32Time & HIB_CAL0_MIN_M) >> HIB_CAL0_MIN_S; + psTime->tm_sec = (ui32Time & HIB_CAL0_SEC_M) >> HIB_CAL0_SEC_S; + psTime->tm_mon = (((ui32Date & HIB_CAL1_MON_M) >> HIB_CAL1_MON_S) - 1); + psTime->tm_mday = (ui32Date & HIB_CAL1_DOM_M) >> HIB_CAL1_DOM_S; + psTime->tm_wday = (ui32Date & HIB_CAL1_DOW_M) >> HIB_CAL1_DOW_S; + psTime->tm_year = ((ui32Date & HIB_CAL1_YEAR_M) >> HIB_CAL1_YEAR_S) + 100; + psTime->tm_hour = (ui32Time & HIB_CAL0_HR_M) >> HIB_CAL0_HR_S; + + // + // Fix up the hour in the non-24-hour mode and the time is in PM. + // + if(((HWREG(HIB_CALCTL) & HIB_CALCTL_CAL24) == 0) && + (ui32Time & HIB_CAL0_AMPM)) + { + psTime->tm_hour += 12; + } + + return(0); +} + +//***************************************************************************** +// +//! Sets the Hibernation module's date and time match value in calendar mode. +//! +//! \param ui32Index indicates which match register to access. +//! \param psTime is the structure that holds all of the information to set +//! the current date and time match values. +//! +//! This function uses the \e psTime parameter to set the current date and time +//! match value in the Hibernation module's calendar. Regardless of the mode, +//! the \e psTime parameter uses a 24-hour clock representation of time. +//! This function can only be called when the Hibernation module is +//! configured in calendar mode using the HibernateCounterMode() +//! function. The \e ui32Index value is reserved for future use and should +//! always be zero. +//! Calendar match can be enabled for every day, every hour, every minute or +//! every second, setting any of these fields to 0xFF causes a match for +//! that field. For example, setting the day of month field to 0xFF +//! results in a calendar match daily at the same time. +//! +//! \note The hibernate calendar mode is not available on all Tiva +//! devices. Please consult the data sheet to determine if the device you are +//! using supports this feature in the Hibernation module. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateCalendarMatchSet(uint32_t ui32Index, struct tm *psTime) +{ + // + // Set the Match value. + // + _HibernateCalendarSet(HIB_CALM0, psTime); +} + +//***************************************************************************** +// +//! Returns the Hibernation module's date and time match value in calendar +//! mode. +//! +//! \param ui32Index indicates which match register to access. +//! \param psTime is the structure to fill with the current date and time +//! match value. +//! +//! This function returns the current date and time match value in the +//! structure provided by the \e psTime parameter. Regardless of the mode, the +//! \e psTime parameter uses a 24-hour clock representation of time. +//! This function can only be called when the Hibernation module is configured +//! in calendar mode using the HibernateCounterMode() function. +//! The \e ui32Index value is reserved for future use and should always be +//! zero. +//! +//! \note The hibernate calendar mode is not available on all Tiva +//! devices. Please consult the data sheet to determine if the device you are +//! using supports this feature in the Hibernation module. +//! +//! \return Returns zero if the time and date match value were read +//! successfully and returns a non-zero value if the psTime structure was not +//! updated. +// +//***************************************************************************** +void +HibernateCalendarMatchGet(uint32_t ui32Index, struct tm *psTime) +{ + uint32_t ui32Date, ui32Time; + + ASSERT(HWREG(HIB_CALCTL) & HIB_CALCTL_CALEN); + + // + // Get the date field. + // + ui32Date = HWREG(HIB_CALM1); + + // + // Get the time field. + // + ui32Time = HWREG(HIB_CALM0); + + // + // Populate the date and time fields in the psTime structure. + // + if((ui32Time & HIB_CAL0_MIN_M) == HIB_CAL0_MIN_M) + { + // + // Match every minute + // + psTime->tm_min = 0xFF; + } + else + { + psTime->tm_min = (ui32Time & HIB_CAL0_MIN_M) >> HIB_CAL0_MIN_S; + } + + if((ui32Time & HIB_CAL0_SEC_M) == HIB_CAL0_SEC_M) + { + // + // Match every second + // + psTime->tm_sec = 0xFF; + } + else + { + psTime->tm_sec = (ui32Time & HIB_CAL0_SEC_M) >> HIB_CAL0_SEC_S; + } + + if((ui32Time & HIB_CAL0_HR_M) == HIB_CAL0_HR_M) + { + // + // Match every hour + // + psTime->tm_hour = 0xFF; + } + else + { + psTime->tm_hour = (ui32Time & HIB_CAL0_HR_M) >> HIB_CAL0_HR_S; + } + + if((ui32Date & HIB_CAL1_DOM_M) == 0) + { + // + // Match every day + // + psTime->tm_mday = 0xFF; + } + else + { + psTime->tm_mday = (ui32Date & HIB_CAL1_DOM_M) >> HIB_CAL1_DOM_S; + } + + // + // Fix up the hour in the non-24-hour mode and the time is in PM. + // + if(((HWREG(HIB_CALCTL) & HIB_CALCTL_CAL24) == 0) && + (ui32Time & HIB_CAL0_AMPM)) + { + psTime->tm_hour += 12; + } +} + +//***************************************************************************** +// +//! Configures the tamper feature event response. +//! +//! \param ui32Config specifies the configuration options for tamper events. +//! +//! This function is used to configure the event response options for the +//! tamper feature. The \e ui32Config parameter provides a combination of the +//! \b HIBERNATE_TAMPER_EVENTS_* features to set these options. The +//! application should choose from the following set of defines to determine +//! what happens to the system when a tamper event occurs: +//! +//! - \b HIBERNATE_TAMPER_EVENTS_ERASE_ALL_HIB_MEM all of the Hibernation +//! module's battery-backed RAM is cleared due to a tamper event +//! - \b HIBERNATE_TAMPER_EVENTS_ERASE_HIGH_HIB_MEM the upper half of the +//! Hibernation module's battery-backed RAM is cleared due to a tamper event +//! - \b HIBERNATE_TAMPER_EVENTS_ERASE_LOW_HIB_MEM the lower half of the +//! Hibernation module's battery-backed RAM is cleared due to a tamper event +//! - \b HIBERNATE_TAMPER_EVENTS_ERASE_NO_HIB_MEM the Hibernation module's +//! battery-backed RAM is not changed due to a tamper event +//! - \b HIBERNATE_TAMPER_EVENTS_HIB_WAKE a tamper event wakes the MCU from +//! hibernation +//! - \b HIBERNATE_TAMPER_EVENTS_NO_HIB_WAKE a tamper event does not wake the +//! MCU from hibernation +//! +//! \note The hibernate tamper feature is not available on all Tiva +//! devices. Please consult the data sheet for the Tiva device that you +//! are using to determine if this feature is available. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateTamperEventsConfig(uint32_t ui32Config) +{ + uint32_t ui32Temp; + + // + // Mask out the on-event configuration options. + // + ui32Temp = (HWREG(HIB_TPCTL) & ~HIB_TPCTL_MEMCLR_M); + + // + // Unlock the tamper registers. + // + HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY; + _HibernateWriteComplete(); + + // + // Set the on-event configuration. + // + HWREG(HIB_TPCTL) = (ui32Temp | ui32Config); + + // + // Wait for write completion. + // + _HibernateWriteComplete(); + + // + // Lock the tamper registers. + // + HWREG(HIB_LOCK) = 0; + _HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Enables the tamper feature. +//! +//! This function is used to enable the tamper feature functionality. This +//! function should only be called after the global configuration is set with +//! a call to HibernateTamperEventsConfig() and the tamper inputs have been +//! configured with a call to HibernateTamperIOEnable(). +//! +//! \note The hibernate tamper feature is not available on all Tiva +//! devices. Please consult the data sheet for the Tiva device that you +//! are using to determine if this feature is available. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateTamperEnable(void) +{ + // + // Unlock the tamper registers. + // + HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY; + _HibernateWriteComplete(); + + // + // Set the tamper enable bit. + // + HWREG(HIB_TPCTL) |= HIB_TPCTL_TPEN; + + // + // Wait for write completion. + // + _HibernateWriteComplete(); + + // + // Lock the tamper registers. + // + HWREG(HIB_LOCK) = 0; + _HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Disables the tamper feature. +//! +//! This function is used to disable the tamper feature functionality. All +//! other configuration settings are left unmodified, allowing a call to +//! HibernateTamperEnable() to quickly enable the tamper feature with its +//! previous configuration. +//! +//! \note The hibernate tamper feature is not available on all Tiva +//! devices. Please consult the data sheet for the Tiva device that you +//! are using to determine if this feature is available. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateTamperDisable(void) +{ + // + // Unlock the tamper registers. + // + HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY; + _HibernateWriteComplete(); + + // + // Clear the tamper enable bit. + // + HWREG(HIB_TPCTL) &= ~HIB_TPCTL_TPEN; + + // + // Wait for write completion. + // + _HibernateWriteComplete(); + + // + // Lock the tamper registers. + // + HWREG(HIB_LOCK) = 0; + _HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Configures an input to the tamper feature. +//! +//! \param ui32Input is the tamper input to configure. +//! \param ui32Config holds the configuration options for a given input to the +//! tamper feature. +//! +//! This function is used to configure an input to the tamper feature. The +//! \e ui32Input parameter specifies the tamper signal to configure and has a +//! valid range of 0-3. The \e ui32Config parameter provides the set of tamper +//! features in the \b HIBERNATE_TAMPER_IO_* values. The values that are valid +//! in the \e ui32Config parameter are: +//! +//! - \b HIBERNATE_TAMPER_IO_MATCH_SHORT configures the trigger to match after +//! 2 hibernation clocks +//! - \b HIBERNATE_TAMPER_IO_MATCH_LONG configures the trigger to match after +//! 3071 hibernation clocks +//! - \b HIBERNATE_TAMPER_IO_WPU_ENABLED turns on an internal weak pull up +//! - \b HIBERNATE_TAMPER_IO_WPU_DISABLED turns off an internal weak pull up +//! - \b HIBERNATE_TAMPER_IO_TRIGGER_HIGH sets the tamper event to active high +//! - \b HIBERNATE_TAMPER_IO_TRIGGER_LOW sets the tamper event to active low +//! +//! \note None of the GPIO API functions are needed to configure the tamper +//! pins. The tamper pins configured by using this function overrides any +//! configuration by GPIO APIs. +//! +//! \note The hibernate tamper feature is not available on all Tiva +//! devices. Please consult the data sheet for the Tiva device that you +//! are using to determine if this feature is available. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateTamperIOEnable(uint32_t ui32Input, uint32_t ui32Config) +{ + uint32_t ui32Temp, ui32Mask; + + // + // Verify parameters. + // + ASSERT(ui32Input < 4); + + // + // Read the current tamper I/O configuration. + // + ui32Temp = HWREG(HIB_TPIO); + + // + // Mask out configuration options for the requested input. + // + ui32Mask = (ui32Temp & (~((HIB_TPIO_GFLTR0 | HIB_TPIO_PUEN0 | + HIB_TPIO_LEV0 | HIB_TPIO_EN0) << + (ui32Input << 3)))); + + // + // Set tamper I/O configuration for the requested input. + // + ui32Temp = (ui32Mask | ((ui32Config | HIB_TPIO_EN0) << (ui32Input << 3))); + + // + // Unlock the tamper registers. + // + HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY; + _HibernateWriteComplete(); + + // + // Write to the register. + // + HWREG(HIB_TPIO) = ui32Temp; + + // + // Wait for write completion. + // + _HibernateWriteComplete(); + + // + // Lock the tamper registers. + // + HWREG(HIB_LOCK) = 0; + _HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Disables an input to the tamper feature. +//! +//! \param ui32Input is the tamper input to disable. +//! +//! This function is used to disable an input to the tamper feature. The +//! \e ui32Input parameter specifies the tamper signal to disable and has a +//! valid range of 0-3. +//! +//! \note None of the GPIO API functions are needed to configure the tamper +//! pins. The tamper pins configured by using this function overrides any +//! configuration by GPIO APIs. +//! +//! \note The hibernate tamper feature is not available on all Tiva +//! devices. Please consult the data sheet for the Tiva device that you +//! are using to determine if this feature is available. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateTamperIODisable(uint32_t ui32Input) +{ + // + // Verify parameters. + // + ASSERT(ui32Input < 4); + + // + // Unlock the tamper registers. + // + HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY; + _HibernateWriteComplete(); + + // + // Clear the I/O enable bit. + // + HWREG(HIB_TPIO) &= ((~HIB_TPIO_EN0) << (ui32Input << 3)); + + // + // Wait for write completion. + // + _HibernateWriteComplete(); + + // + // Lock the tamper registers. + // + HWREG(HIB_LOCK) = 0; + _HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Clears the tamper feature events. +//! +//! This function is used to clear all tamper events. This function always +//! clears the tamper feature event state indicator along with all tamper log +//! entries. Logged event data should be retrieved with +//! HibernateTamperEventsGet() prior to requesting a event clear. +//! +//! HibernateTamperEventsClear() should be called prior to clearing the system +//! control NMI that resulted from the tamper event. +//! +//! \note The hibernate tamper feature is not available on all Tiva +//! devices. Please consult the data sheet for the Tiva device that you +//! are using to determine if this feature is available. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateTamperEventsClear(void) +{ + // + // Unlock the tamper registers. + // + HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY; + _HibernateWriteComplete(); + + // + // Set the tamper event clear bit. + // + HWREG(HIB_TPCTL) |= HIB_TPCTL_TPCLR; + + // + // Wait for write completion. + // + _HibernateWriteComplete(); + + // + // Lock the tamper registers. + // + HWREG(HIB_LOCK) = 0; + _HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Clears the tamper feature events without Unlock and Lock. +//! +//! This function is used to clear all tamper events without unlock/locking +//! the tamper control registers, so API HibernateTamperUnLock() should be +//! called before this function, and API HibernateTamperLock() should be +//! called after to ensure that tamper control registers are locked. +//! +//! This function doesn't block until the write is complete. +//! Therefore, care must be taken to ensure the next immediate write will +//! occure only after the write complete bit is set. +//! +//! This function is used to implement a software workaround in NMI interrupt +//! handler to fix an issue when a new tamper event could be missed during +//! the clear of current tamper event. +//! +//! \note The hibernate tamper feature is not available on all Tiva +//! devices. Please consult the data sheet for the Tiva device that you +//! are using to determine if this feature is available. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateTamperEventsClearNoLock(void) +{ + // + // Wait for write completion. + // + _HibernateWriteComplete(); + + // + // Set the tamper event clear bit. + // + HWREG(HIB_TPCTL) |= HIB_TPCTL_TPCLR; + +} + +//***************************************************************************** +// +//! Unlock temper registers. +//! +//! This function is used to unlock the temper control registers. This +//! function should be only used before calling API +//! HibernateTamperEventsClearNoLock(). +//! +//! \note The hibernate tamper feature is not available on all Tiva +//! devices. Please consult the data sheet for the Tiva device that you +//! are using to determine if this feature is available. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateTamperUnLock(void) +{ + // + // Unlock the tamper registers. + // + HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY; + _HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Lock temper registers. +//! +//! This function is used to lock the temper control registers. This +//! function should be used after calling API +//! HibernateTamperEventsClearNoLock(). +//! +//! \note The hibernate tamper feature is not available on all Tiva +//! devices. Please consult the data sheet for the Tiva device that you +//! are using to determine if this feature is available. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateTamperLock(void) +{ + // + // Wait for write completion. + // + _HibernateWriteComplete(); + + // + // Lock the tamper registers. + // + HWREG(HIB_LOCK) = 0; + _HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Returns the current tamper feature status. +//! +//! This function is used to return the tamper feature status. This function +//! returns one of the values from this group of options: +//! +//! - \b HIBERNATE_TAMPER_STATUS_INACTIVE indicates tamper detection is +//! disabled +//! - \b HIBERNATE_TAMPER_STATUS_ACTIVE indicates tamper detection is enabled +//! and ready +//! - \b HIBERNATE_TAMPER_STATUS_EVENT indicates tamper event was detected +//! +//! In addition, one of the values is included from this group: +//! +//! - \b HIBERNATE_TAMPER_STATUS_EXT_OSC_INACTIVE indicates the external +//! oscillator is not active +//! - \b HIBERNATE_TAMPER_STATUS_EXT_OSC_ACTIVE indicates the external +//! oscillator is active +//! +//! And one of the values is included from this group: +//! +//! - \b HIBERNATE_TAMPER_STATUS_EXT_OSC_FAILED indicates the external +//! oscillator signal has transitioned from valid to invalid +//! - \b HIBERNATE_TAMPER_STATUS_EXT_OSC_VALID indicates the external +//! oscillator is providing a valid signal +//! +//! \note The hibernate tamper feature is not available on all Tiva +//! devices. Please consult the data sheet for the Tiva device that you +//! are using to determine if this feature is available. +//! +//! \return Returns a combination of the \b HIBERNATE_TAMPER_STATUS_* values. +// +//***************************************************************************** +uint32_t +HibernateTamperStatusGet(void) +{ + uint32_t ui32Status, ui32Reg; + + // + // Retrieve the raw register value. + // + ui32Reg = HWREG(HIB_TPSTAT); + + // + // Setup the oscillator status indicators. + // + ui32Status = (ui32Reg & (HIB_TPSTAT_XOSCST | HIB_TPSTAT_XOSCFAIL)); + ui32Status |= ((ui32Reg & HIB_TPSTAT_XOSCST) ? 0 : + HIBERNATE_TAMPER_STATUS_EXT_OSC_ACTIVE); + ui32Status |= ((ui32Reg & HIB_TPSTAT_XOSCFAIL) ? 0 : + HIBERNATE_TAMPER_STATUS_EXT_OSC_VALID); + + // + // Retrieve the tamper status indicators. + // + ui32Status |= ((ui32Reg & HIB_TPSTAT_STATE_M) << 3); + + // + // The HW shows "disabled" with a zero value, use bit[0] as a flag + // for this purpose. + // + if((ui32Reg & HIB_TPSTAT_STATE_M) == 0) + { + ui32Status |= HIBERNATE_TAMPER_STATUS_INACTIVE; + } + + // + // Return the API status flags. + // + return(ui32Status); +} + +//***************************************************************************** +// +//! Returns a tamper log entry. +//! +//! \param ui32Index is the index of the log entry to return. +//! \param pui32RTC is a pointer to the memory to store the logged RTC data. +//! \param pui32Event is a pointer to the memory to store the logged tamper +//! event. +//! +//! This function is used to return a tamper log entry from the hibernate +//! feature. The \e ui32Index specifies the zero-based index of the log entry +//! to query and has a valid range of 0-3. +//! +//! When this function returns, the \e pui32RTC value contains the time value +//! and \e pui32Event parameter contains the tamper I/O event that triggered +//! this log. +//! +//! The format of the returned \e pui32RTC data is dependent on the +//! configuration of the RTC within the Hibernation module. If the RTC is +//! configured for counter mode, the returned data contains counted seconds +//! from the RTC enable. If the RTC is configured for calendar mode, the data +//! returned is formatted as follows: +//! +//! \verbatim +//! +----------------------------------------------------------------------+ +//! | 31:26 | 25:22 | 21:17 | 16:12 | 11:6 | 5:0 | +//! +----------------------------------------------------------------------+ +//! | year | month | day of month | hours | minutes | seconds | +//! +----------------------------------------------------------------------+ +//! \endverbatim +//! +//! The data returned in the \e pui32Events parameter could include any of the +//! following flags: +//! +//! - \b HIBERNATE_TAMPER_EVENT_0 indicates a tamper event was triggered on I/O +//! signal 0 +//! - \b HIBERNATE_TAMPER_EVENT_1 indicates a tamper event was triggered on I/O +//! signal 1 +//! - \b HIBERNATE_TAMPER_EVENT_2 indicates a tamper event was triggered on I/O +//! signal 2 +//! - \b HIBERNATE_TAMPER_EVENT_3 indicates a tamper event was triggered on I/O +//! signal 3 +//! - \b HIBERNATE_TAMPER_EVENT_XOSC indicates an external oscillator failure +//! triggered the tamper event +//! +//! \note Tamper event logs are not consumed when read and remain available +//! until cleared. Events are only logged if unused log space is available. +//! +//! \note The hibernate tamper feature is not available on all Tiva +//! devices. Please consult the data sheet for the Tiva device that you +//! are using to determine if this feature is available. +//! +//! \return Returns \b true if the \e pui32RTC and \e pui32Events were updated +//! successfully and returns \b false if the values were not updated. +// +//***************************************************************************** +bool +HibernateTamperEventsGet(uint32_t ui32Index, uint32_t *pui32RTC, + uint32_t *pui32Event) +{ + uint32_t ui32Reg; + + // + // Verify parameters. + // + ASSERT(pui32RTC); + ASSERT(pui32Event); + ASSERT(ui32Index < 4); + + // + // Retrieve the event log data for the requested index if available. + // + ui32Reg = HWREG(HIB_TPLOG0 + ((ui32Index << 3) + 4)); + if(ui32Reg == 0) + { + // + // No event data is available for this index. + // + return(false); + } + + // + // Store the event data in the provided location. + // + *pui32Event = ui32Reg; + + // + // Retrieve the calendar information. + // + *pui32RTC = HWREG(HIB_TPLOG0 + (ui32Index << 3)); + + // + // Convert the hour to 24hr mode if the Calendar is enabled + // and in 24hr mode. + // + if((HWREG(HIB_CALCTL) & (HIB_CALCTL_CALEN | HIB_CALCTL_CAL24)) == + (HIB_CALCTL_CALEN | HIB_CALCTL_CAL24)) + { + if(HWREG(HIB_CAL0) & HIB_CAL0_AMPM) + { + // + // Add 12 hour since it is PM + // + ui32Reg = ((*pui32RTC & 0X0001f000) + (12<<12)) & 0X0001f000; + *pui32RTC &= ~0X0001f000; + *pui32RTC |= ui32Reg; + } + } + + // + // Return success. + // + return(true); +} + +//***************************************************************************** +// +//! Attempts to recover the external oscillator. +//! +//! This function is used to attempt to recover the external oscillator after a +//! \b HIBERNATE_TAMPER_STATUS_EXT_OSC_FAILED status is reported. This +//! function must not be called if the external oscillator is not used as +//! the hibernation clock input. HibernateTamperExtOscValid() should be called +//! before calling this function. +//! +//! \note The hibernate tamper feature is not available on all Tiva +//! devices. Please consult the data sheet for the Tiva device that you +//! are using to determine if this feature is available. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateTamperExtOscRecover(void) +{ + // + // Unlock the tamper registers. + // + HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY; + _HibernateWriteComplete(); + + // + // Set the XOSCFAIL clear bit. + // + HWREG(HIB_TPSTAT) |= HIB_TPSTAT_XOSCFAIL; + + // + // Wait for write completion. + // + _HibernateWriteComplete(); + + // + // Lock the tamper registers. + // + HWREG(HIB_LOCK) = 0; + _HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Reports if the external oscillator signal is active and stable. +//! +//! This function should be used to verify the external oscillator is active +//! and valid before attempting to recover from a +//! \b HIBERNATE_TAMPER_STATUS_EXT_OSC_FAILED status by calling +//! HibernateTamperExtOscRecover(). +//! +//! \note The hibernate tamper feature is not available on all Tiva +//! devices. Please consult the data sheet for the Tiva device that you +//! are using to determine if this feature is available. +//! +//! \return Returns \b true if the external oscillator is both active and +//! stable, otherwise a \b false indicator is returned. +// +//***************************************************************************** +bool +HibernateTamperExtOscValid(void) +{ + if(HibernateTamperStatusGet() & (HIBERNATE_TAMPER_STATUS_EXT_OSC_ACTIVE | + HIBERNATE_TAMPER_STATUS_EXT_OSC_VALID)) + { + return(true); + } + + return(false); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/i2c.c b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/i2c.c new file mode 100644 index 0000000000000000000000000000000000000000..37aa1d764b8fc618048fe56ab3d89ebfeb049e79 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/i2c.c @@ -0,0 +1,2193 @@ +//***************************************************************************** +// +// i2c.c - Driver for Inter-IC (I2C) bus block. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup i2c_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_i2c.h" +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/i2c.h" +#include "driverlib/interrupt.h" + +//***************************************************************************** +// +// A mapping of I2C base address to interrupt number. +// +//***************************************************************************** +static const uint32_t g_ppui32I2CIntMap[][2] = +{ + { I2C0_BASE, INT_I2C0_TM4C123 }, + { I2C1_BASE, INT_I2C1_TM4C123 }, + { I2C2_BASE, INT_I2C2_TM4C123 }, + { I2C3_BASE, INT_I2C3_TM4C123 }, + { I2C4_BASE, INT_I2C4_TM4C123 }, + { I2C5_BASE, INT_I2C5_TM4C123 }, +}; + +static const int_fast8_t g_i8I2CIntMapRows = + sizeof(g_ppui32I2CIntMap) / sizeof(g_ppui32I2CIntMap[0]); + +static const uint32_t g_ppui32I2CIntMapSnowflake[][2] = +{ + { I2C0_BASE, INT_I2C0_TM4C129 }, + { I2C1_BASE, INT_I2C1_TM4C129 }, + { I2C2_BASE, INT_I2C2_TM4C129 }, + { I2C3_BASE, INT_I2C3_TM4C129 }, + { I2C4_BASE, INT_I2C4_TM4C129 }, + { I2C5_BASE, INT_I2C5_TM4C129 }, + { I2C6_BASE, INT_I2C6_TM4C129 }, + { I2C7_BASE, INT_I2C7_TM4C129 }, + { I2C8_BASE, INT_I2C8_TM4C129 }, + { I2C9_BASE, INT_I2C9_TM4C129 }, +}; +static const int_fast8_t g_i8I2CIntMapSnowflakeRows = + sizeof(g_ppui32I2CIntMapSnowflake) / sizeof(g_ppui32I2CIntMapSnowflake[0]); + +//***************************************************************************** +// +//! \internal +//! Checks an I2C base address. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! This function determines if a I2C module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static bool +_I2CBaseValid(uint32_t ui32Base) +{ + return((ui32Base == I2C0_BASE) || (ui32Base == I2C1_BASE) || + (ui32Base == I2C2_BASE) || (ui32Base == I2C3_BASE) || + (ui32Base == I2C4_BASE) || (ui32Base == I2C5_BASE) || + (ui32Base == I2C6_BASE) || (ui32Base == I2C7_BASE) || + (ui32Base == I2C8_BASE) || (ui32Base == I2C9_BASE)); +} +#endif + +//***************************************************************************** +// +//! \internal +//! Gets the I2C interrupt number. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! Given a I2C base address, this function returns the corresponding +//! interrupt number. +//! +//! \return Returns an I2C interrupt number, or 0 if \e ui32Base is invalid. +// +//***************************************************************************** +static uint32_t +_I2CIntNumberGet(uint32_t ui32Base) +{ + int_fast8_t i8Idx, i8Rows; + const uint32_t (*ppui32I2CIntMap)[2]; + + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + ppui32I2CIntMap = g_ppui32I2CIntMap; + i8Rows = g_i8I2CIntMapRows; + + if(CLASS_IS_TM4C129) + { + ppui32I2CIntMap = g_ppui32I2CIntMapSnowflake; + i8Rows = g_i8I2CIntMapSnowflakeRows; + } + + // + // Loop through the table that maps I2C base addresses to interrupt + // numbers. + // + for(i8Idx = 0; i8Idx < i8Rows; i8Idx++) + { + // + // See if this base address matches. + // + if(ppui32I2CIntMap[i8Idx][0] == ui32Base) + { + // + // Return the corresponding interrupt number. + // + return(ppui32I2CIntMap[i8Idx][1]); + } + } + + // + // The base address could not be found, so return an error. + // + return(0); +} + +//***************************************************************************** +// +//! Initializes the I2C Master block. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui32I2CClk is the rate of the clock supplied to the I2C module. +//! \param bFast set up for fast data transfers. +//! +//! This function initializes operation of the I2C Master block by configuring +//! the bus speed for the master and enabling the I2C Master block. +//! +//! If the parameter \e bFast is \b true, then the master block is set up to +//! transfer data at 400 Kbps; otherwise, it is set up to transfer data at +//! 100 Kbps. If Fast Mode Plus (1 Mbps) is desired, software should manually +//! write the I2CMTPR after calling this function. For High Speed (3.4 Mbps) +//! mode, a specific command is used to switch to the faster clocks after the +//! initial communication with the slave is done at either 100 Kbps or +//! 400 Kbps. +//! +//! The peripheral clock is the same as the processor clock. The frequency of +//! the system clock is the value returned by SysCtlClockGet() for TM4C123x +//! devices or the value returned by SysCtlClockFreqSet() for TM4C129x devices, +//! or it can be explicitly hard coded if it is constant and known (to save the +//! code/execution overhead of a call to SysCtlClockGet() or fetch of the +//! variable call holding the return value of SysCtlClockFreqSet()). +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk, + bool bFast) +{ + uint32_t ui32SCLFreq; + uint32_t ui32TPR; + + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Must enable the device before doing anything else. + // + I2CMasterEnable(ui32Base); + + // + // Get the desired SCL speed. + // + if(bFast == true) + { + ui32SCLFreq = 400000; + } + else + { + ui32SCLFreq = 100000; + } + + // + // Compute the clock divider that achieves the fastest speed less than or + // equal to the desired speed. The numerator is biased to favor a larger + // clock divider so that the resulting clock is always less than or equal + // to the desired clock, never greater. + // + ui32TPR = ((ui32I2CClk + (2 * 10 * ui32SCLFreq) - 1) / + (2 * 10 * ui32SCLFreq)) - 1; + HWREG(ui32Base + I2C_O_MTPR) = ui32TPR; + + // + // Check to see if this I2C peripheral is High-Speed enabled. If yes, also + // choose the fastest speed that is less than or equal to 3.4 Mbps. + // + if(HWREG(ui32Base + I2C_O_PP) & I2C_PP_HS) + { + ui32TPR = ((ui32I2CClk + (2 * 3 * 3400000) - 1) / + (2 * 3 * 3400000)) - 1; + HWREG(ui32Base + I2C_O_MTPR) = I2C_MTPR_HS | ui32TPR; + } +} + +//***************************************************************************** +// +//! Initializes the I2C Slave block. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui8SlaveAddr 7-bit slave address +//! +//! This function initializes operation of the I2C Slave block by configuring +//! the slave address and enabling the I2C Slave block. +//! +//! The parameter \e ui8SlaveAddr is the value that is compared against the +//! slave address sent by an I2C master. +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + ASSERT(!(ui8SlaveAddr & 0x80)); + + // + // Must enable the device before doing anything else. + // + I2CSlaveEnable(ui32Base); + + // + // Set up the slave address. + // + HWREG(ui32Base + I2C_O_SOAR) = ui8SlaveAddr; +} + +//***************************************************************************** +// +//! Sets the I2C slave address. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui8AddrNum determines which slave address is set. +//! \param ui8SlaveAddr is the 7-bit slave address +//! +//! This function writes the specified slave address. The \e ui32AddrNum field +//! dictates which slave address is configured. For example, a value of 0 +//! configures the primary address and a value of 1 configures the secondary. +//! +//! \note Not all Tiva devices support a secondary address. Please +//! consult the device data sheet to determine if this feature is supported. +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8AddrNum, uint8_t ui8SlaveAddr) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + ASSERT(!(ui8AddrNum > 1)); + ASSERT(!(ui8SlaveAddr & 0x80)); + + // + // Determine which slave address is being set. + // + switch(ui8AddrNum) + { + // + // Set up the primary slave address. + // + case 0: + { + HWREG(ui32Base + I2C_O_SOAR) = ui8SlaveAddr; + break; + } + + // + // Set up and enable the secondary slave address. + // + case 1: + { + HWREG(ui32Base + I2C_O_SOAR2) = I2C_SOAR2_OAR2EN | ui8SlaveAddr; + break; + } + } +} + +//***************************************************************************** +// +//! Enables the I2C Master block. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! This function enables operation of the I2C Master block. +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Enable the master block. + // + HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_MFE; +} + +//***************************************************************************** +// +//! Enables the I2C Slave block. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! This fucntion enables operation of the I2C Slave block. +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Enable the clock to the slave block. + // + HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_SFE; + + // + // Enable the slave. + // + HWREG(ui32Base + I2C_O_SCSR) = I2C_SCSR_DA; +} + +//***************************************************************************** +// +//! Disables the I2C master block. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! This function disables operation of the I2C master block. +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterDisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Disable the master block. + // + HWREG(ui32Base + I2C_O_MCR) &= ~(I2C_MCR_MFE); +} + +//***************************************************************************** +// +//! Disables the I2C slave block. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! This function disables operation of the I2C slave block. +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveDisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Disable the slave. + // + HWREG(ui32Base + I2C_O_SCSR) = 0; + + // + // Disable the clock to the slave block. + // + HWREG(ui32Base + I2C_O_MCR) &= ~(I2C_MCR_SFE); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the I2C module. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param pfnHandler is a pointer to the function to be called when the +//! I2C interrupt occurs. +//! +//! This function sets the handler to be called when an I2C interrupt occurs. +//! This function enables the global interrupt in the interrupt controller; +//! specific I2C interrupts must be enabled via I2CMasterIntEnable() and +//! I2CSlaveIntEnable(). If necessary, it is the interrupt handler's +//! responsibility to clear the interrupt source via I2CMasterIntClear() and +//! I2CSlaveIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +I2CIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Determine the interrupt number based on the I2C port. + // + ui32Int = _I2CIntNumberGet(ui32Base); + + ASSERT(ui32Int != 0); + + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(ui32Int, pfnHandler); + + // + // Enable the I2C interrupt. + // + IntEnable(ui32Int); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the I2C module. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! This function clears the handler to be called when an I2C interrupt +//! occurs. This function also masks off the interrupt in the interrupt r +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +I2CIntUnregister(uint32_t ui32Base) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Determine the interrupt number based on the I2C port. + // + ui32Int = _I2CIntNumberGet(ui32Base); + + ASSERT(ui32Int != 0); + + // + // Disable the interrupt. + // + IntDisable(ui32Int); + + // + // Unregister the interrupt handler. + // + IntUnregister(ui32Int); +} + +//***************************************************************************** +// +//! Enables the I2C Master interrupt. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! This function enables the I2C Master interrupt source. +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterIntEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Enable the master interrupt. + // + HWREG(ui32Base + I2C_O_MIMR) = 1; +} + +//***************************************************************************** +// +//! Enables individual I2C Master interrupt sources. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated I2C Master interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ui32IntFlags parameter is the logical OR of any of the following: +//! +//! - \b I2C_MASTER_INT_RX_FIFO_FULL - RX FIFO Full interrupt +//! - \b I2C_MASTER_INT_TX_FIFO_EMPTY - TX FIFO Empty interrupt +//! - \b I2C_MASTER_INT_RX_FIFO_REQ - RX FIFO Request interrupt +//! - \b I2C_MASTER_INT_TX_FIFO_REQ - TX FIFO Request interrupt +//! - \b I2C_MASTER_INT_ARB_LOST - Arbitration Lost interrupt +//! - \b I2C_MASTER_INT_STOP - Stop Condition interrupt +//! - \b I2C_MASTER_INT_START - Start Condition interrupt +//! - \b I2C_MASTER_INT_NACK - Address/Data NACK interrupt +//! - \b I2C_MASTER_INT_TX_DMA_DONE - TX DMA Complete interrupt +//! - \b I2C_MASTER_INT_RX_DMA_DONE - RX DMA Complete interrupt +//! - \b I2C_MASTER_INT_TIMEOUT - Clock Timeout interrupt +//! - \b I2C_MASTER_INT_DATA - Data interrupt +//! +//! \note Not all Tiva devices support all of the listed interrupt +//! sources. Please consult the device data sheet to determine if these +//! features are supported. +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Enable the master interrupt. + // + HWREG(ui32Base + I2C_O_MIMR) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! Enables the I2C Slave interrupt. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! This function enables the I2C Slave interrupt source. +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveIntEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Enable the slave interrupt. + // + HWREG(ui32Base + I2C_O_SIMR) |= I2C_SLAVE_INT_DATA; +} + +//***************************************************************************** +// +//! Enables individual I2C Slave interrupt sources. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated I2C Slave interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ui32IntFlags parameter is the logical OR of any of the following: +//! +//! - \b I2C_SLAVE_INT_RX_FIFO_FULL - RX FIFO Full interrupt +//! - \b I2C_SLAVE_INT_TX_FIFO_EMPTY - TX FIFO Empty interrupt +//! - \b I2C_SLAVE_INT_RX_FIFO_REQ - RX FIFO Request interrupt +//! - \b I2C_SLAVE_INT_TX_FIFO_REQ - TX FIFO Request interrupt +//! - \b I2C_SLAVE_INT_TX_DMA_DONE - TX DMA Complete interrupt +//! - \b I2C_SLAVE_INT_RX_DMA_DONE - RX DMA Complete interrupt +//! - \b I2C_SLAVE_INT_STOP - Stop condition detected interrupt +//! - \b I2C_SLAVE_INT_START - Start condition detected interrupt +//! - \b I2C_SLAVE_INT_DATA - Data interrupt +//! +//! \note Not all Tiva devices support the all of the listed interrupts. +//! Please consult the device data sheet to determine if these features are +//! supported. +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Enable the slave interrupt. + // + HWREG(ui32Base + I2C_O_SIMR) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! Disables the I2C Master interrupt. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! This function disables the I2C Master interrupt source. +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterIntDisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Disable the master interrupt. + // + HWREG(ui32Base + I2C_O_MIMR) = 0; +} + +//***************************************************************************** +// +//! Disables individual I2C Master interrupt sources. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be +//! disabled. +//! +//! This function disables the indicated I2C Master interrupt sources. Only +//! the sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ui32IntFlags parameter has the same definition as the +//! \e ui32IntFlags parameter to I2CMasterIntEnableEx(). +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Disable the master interrupt. + // + HWREG(ui32Base + I2C_O_MIMR) &= ~ui32IntFlags; +} + +//***************************************************************************** +// +//! Disables the I2C Slave interrupt. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! This function disables the I2C Slave interrupt source. +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveIntDisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Disable the slave interrupt. + // + HWREG(ui32Base + I2C_O_SIMR) &= ~I2C_SLAVE_INT_DATA; +} + +//***************************************************************************** +// +//! Disables individual I2C Slave interrupt sources. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be +//! disabled. +//! +//! This function disables the indicated I2C Slave interrupt sources. Only +//! the sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ui32IntFlags parameter has the same definition as the +//! \e ui32IntFlags parameter to I2CSlaveIntEnableEx(). +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Disable the slave interrupt. + // + HWREG(ui32Base + I2C_O_SIMR) &= ~ui32IntFlags; +} + +//***************************************************************************** +// +//! Gets the current I2C Master interrupt status. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param bMasked is false if the raw interrupt status is requested and +//! true if the masked interrupt status is requested. +//! +//! This function returns the interrupt status for the I2C module. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return The current interrupt status, returned as \b true if active +//! or \b false if not active. +// +//***************************************************************************** +bool +I2CMasterIntStatus(uint32_t ui32Base, bool bMasked) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return((HWREG(ui32Base + I2C_O_MMIS)) ? true : false); + } + else + { + return((HWREG(ui32Base + I2C_O_MRIS)) ? true : false); + } +} + +//***************************************************************************** +// +//! Gets the current I2C Master interrupt status. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param bMasked is false if the raw interrupt status is requested and +//! true if the masked interrupt status is requested. +//! +//! This function returns the interrupt status for the I2C module. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of +//! values described in I2CMasterIntEnableEx(). +// +//***************************************************************************** +uint32_t +I2CMasterIntStatusEx(uint32_t ui32Base, bool bMasked) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ui32Base + I2C_O_MMIS)); + } + else + { + return(HWREG(ui32Base + I2C_O_MRIS)); + } +} + +//***************************************************************************** +// +//! Gets the current I2C Slave interrupt status. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param bMasked is false if the raw interrupt status is requested and +//! true if the masked interrupt status is requested. +//! +//! This function returns the interrupt status for the I2C Slave. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return The current interrupt status, returned as \b true if active +//! or \b false if not active. +// +//***************************************************************************** +bool +I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return((HWREG(ui32Base + I2C_O_SMIS)) ? true : false); + } + else + { + return((HWREG(ui32Base + I2C_O_SRIS)) ? true : false); + } +} + +//***************************************************************************** +// +//! Gets the current I2C Slave interrupt status. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param bMasked is false if the raw interrupt status is requested and +//! true if the masked interrupt status is requested. +//! +//! This function returns the interrupt status for the I2C Slave. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of +//! values described in I2CSlaveIntEnableEx(). +// +//***************************************************************************** +uint32_t +I2CSlaveIntStatusEx(uint32_t ui32Base, bool bMasked) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ui32Base + I2C_O_SMIS)); + } + else + { + return(HWREG(ui32Base + I2C_O_SRIS)); + } +} + +//***************************************************************************** +// +//! Clears I2C Master interrupt sources. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! The I2C Master interrupt source is cleared, so that it no longer +//! asserts. This function must be called in the interrupt handler to keep the +//! interrupt from being triggered again immediately upon exit. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterIntClear(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Clear the I2C master interrupt source. + // + HWREG(ui32Base + I2C_O_MICR) = I2C_MICR_IC; + + // + // Workaround for I2C master interrupt clear errata for rev B Tiva + // devices. For later devices, this write is ignored and therefore + // harmless (other than the slight performance hit). + // + HWREG(ui32Base + I2C_O_MMIS) = I2C_MICR_IC; +} + +//***************************************************************************** +// +//! Clears I2C Master interrupt sources. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified I2C Master interrupt sources are cleared, so that they no +//! longer assert. This function must be called in the interrupt handler to +//! keep the interrupt from being triggered again immediately upon exit. +//! +//! The \e ui32IntFlags parameter has the same definition as the +//! \e ui32IntFlags parameter to I2CMasterIntEnableEx(). +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Clear the I2C master interrupt source. + // + HWREG(ui32Base + I2C_O_MICR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! Clears I2C Slave interrupt sources. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! The I2C Slave interrupt source is cleared, so that it no longer asserts. +//! This function must be called in the interrupt handler to keep the interrupt +//! from being triggered again immediately upon exit. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveIntClear(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Clear the I2C slave interrupt source. + // + HWREG(ui32Base + I2C_O_SICR) = I2C_SICR_DATAIC; +} + +//***************************************************************************** +// +//! Clears I2C Slave interrupt sources. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified I2C Slave interrupt sources are cleared, so that they no +//! longer assert. This function must be called in the interrupt handler to +//! keep the interrupt from being triggered again immediately upon exit. +//! +//! The \e ui32IntFlags parameter has the same definition as the +//! \e ui32IntFlags parameter to I2CSlaveIntEnableEx(). +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Clear the I2C slave interrupt source. + // + HWREG(ui32Base + I2C_O_SICR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! Sets the address that the I2C Master places on the bus. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui8SlaveAddr 7-bit slave address +//! \param bReceive flag indicating the type of communication with the slave +//! +//! This function configures the address that the I2C Master places on the +//! bus when initiating a transaction. When the \e bReceive parameter is set +//! to \b true, the address indicates that the I2C Master is initiating a +//! read from the slave; otherwise the address indicates that the I2C +//! Master is initiating a write to the slave. +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterSlaveAddrSet(uint32_t ui32Base, uint8_t ui8SlaveAddr, + bool bReceive) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + ASSERT(!(ui8SlaveAddr & 0x80)); + + // + // Set the address of the slave with which the master will communicate. + // + HWREG(ui32Base + I2C_O_MSA) = (ui8SlaveAddr << 1) | bReceive; +} + +//***************************************************************************** +// +//! Reads the state of the SDA and SCL pins. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! This function returns the state of the I2C bus by providing the real time +//! values of the SDA and SCL pins. +//! +//! \note Not all Tiva devices support this function. Please consult the +//! device data sheet to determine if this feature is supported. +//! +//! \return Returns the state of the bus with SDA in bit position 1 and SCL in +//! bit position 0. +// +//***************************************************************************** +uint32_t +I2CMasterLineStateGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Return the line state. + // + return(HWREG(ui32Base + I2C_O_MBMON)); +} + +//***************************************************************************** +// +//! Indicates whether or not the I2C Master is busy. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! This function returns an indication of whether or not the I2C Master is +//! busy transmitting or receiving data. +//! +//! \return Returns \b true if the I2C Master is busy; otherwise, returns +//! \b false. +// +//***************************************************************************** +bool +I2CMasterBusy(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Return the busy status. + // + if(HWREG(ui32Base + I2C_O_MCS) & I2C_MCS_BUSY) + { + return(true); + } + else + { + return(false); + } +} + +//***************************************************************************** +// +//! Indicates whether or not the I2C bus is busy. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! This function returns an indication of whether or not the I2C bus is busy. +//! This function can be used in a multi-master environment to determine if +//! another master is currently using the bus. +//! +//! \return Returns \b true if the I2C bus is busy; otherwise, returns +//! \b false. +// +//***************************************************************************** +bool +I2CMasterBusBusy(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Return the bus busy status. + // + if(HWREG(ui32Base + I2C_O_MCS) & I2C_MCS_BUSBSY) + { + return(true); + } + else + { + return(false); + } +} + +//***************************************************************************** +// +//! Controls the state of the I2C Master. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui32Cmd command to be issued to the I2C Master. +//! +//! This function is used to control the state of the Master send and +//! receive operations. The \e ui8Cmd parameter can be one of the following +//! values: +//! +//! - \b I2C_MASTER_CMD_SINGLE_SEND +//! - \b I2C_MASTER_CMD_SINGLE_RECEIVE +//! - \b I2C_MASTER_CMD_BURST_SEND_START +//! - \b I2C_MASTER_CMD_BURST_SEND_CONT +//! - \b I2C_MASTER_CMD_BURST_SEND_FINISH +//! - \b I2C_MASTER_CMD_BURST_SEND_ERROR_STOP +//! - \b I2C_MASTER_CMD_BURST_RECEIVE_START +//! - \b I2C_MASTER_CMD_BURST_RECEIVE_CONT +//! - \b I2C_MASTER_CMD_BURST_RECEIVE_FINISH +//! - \b I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP +//! - \b I2C_MASTER_CMD_QUICK_COMMAND +//! - \b I2C_MASTER_CMD_HS_MASTER_CODE_SEND +//! - \b I2C_MASTER_CMD_FIFO_SINGLE_SEND +//! - \b I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE +//! - \b I2C_MASTER_CMD_FIFO_BURST_SEND_START +//! - \b I2C_MASTER_CMD_FIFO_BURST_SEND_CONT +//! - \b I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH +//! - \b I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP +//! - \b I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START +//! - \b I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT +//! - \b I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH +//! - \b I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP +//! +//! \note Not all Tiva devices have an I2C FIFO and support the FIFO +//! commands. Please consult the device data sheet to determine if this +//! feature is supported. +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + ASSERT((ui32Cmd == I2C_MASTER_CMD_SINGLE_SEND) || + (ui32Cmd == I2C_MASTER_CMD_SINGLE_RECEIVE) || + (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_START) || + (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_CONT) || + (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_FINISH) || + (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_ERROR_STOP) || + (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_START) || + (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_CONT) || + (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_FINISH) || + (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP) || + (ui32Cmd == I2C_MASTER_CMD_QUICK_COMMAND) || + (ui32Cmd == I2C_MASTER_CMD_FIFO_SINGLE_SEND) || + (ui32Cmd == I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE) || + (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_SEND_START) || + (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_SEND_CONT) || + (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH) || + (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP) || + (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START) || + (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT) || + (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH) || + (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP) || + (ui32Cmd == I2C_MASTER_CMD_HS_MASTER_CODE_SEND)); + + // + // Send the command. + // + HWREG(ui32Base + I2C_O_MCS) = ui32Cmd; +} + +//***************************************************************************** +// +//! Gets the error status of the I2C Master. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! This function is used to obtain the error status of the Master send +//! and receive operations. +//! +//! \return Returns the error status, as one of \b I2C_MASTER_ERR_NONE, +//! \b I2C_MASTER_ERR_ADDR_ACK, \b I2C_MASTER_ERR_DATA_ACK, or +//! \b I2C_MASTER_ERR_ARB_LOST. +// +//***************************************************************************** +uint32_t +I2CMasterErr(uint32_t ui32Base) +{ + uint32_t ui32Err; + + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Get the raw error state + // + ui32Err = HWREG(ui32Base + I2C_O_MCS); + + // + // If the I2C master is busy, then all the other bit are invalid, and + // don't have an error to report. + // + if(ui32Err & I2C_MCS_BUSY) + { + return(I2C_MASTER_ERR_NONE); + } + + // + // Check for errors. + // + if(ui32Err & (I2C_MCS_ERROR | I2C_MCS_ARBLST)) + { + return(ui32Err & (I2C_MCS_ARBLST | I2C_MCS_DATACK | I2C_MCS_ADRACK)); + } + else + { + return(I2C_MASTER_ERR_NONE); + } +} + +//***************************************************************************** +// +//! Transmits a byte from the I2C Master. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui8Data data to be transmitted from the I2C Master. +//! +//! This function places the supplied data into I2C Master Data Register. +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Write the byte. + // + HWREG(ui32Base + I2C_O_MDR) = ui8Data; +} + +//***************************************************************************** +// +//! Receives a byte that has been sent to the I2C Master. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! This function reads a byte of data from the I2C Master Data Register. +//! +//! \return Returns the byte received from by the I2C Master, cast as an +//! uint32_t. +// +//***************************************************************************** +uint32_t +I2CMasterDataGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Read a byte. + // + return(HWREG(ui32Base + I2C_O_MDR)); +} + +//***************************************************************************** +// +//! Sets the Master clock timeout value. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui32Value is the number of I2C clocks before the timeout is +//! asserted. +//! +//! This function enables and configures the clock low timeout feature in the +//! I2C peripheral. This feature is implemented as a 12-bit counter, with the +//! upper 8-bits being programmable. For example, to program a timeout of 20ms +//! with a 100-kHz SCL frequency, \e ui32Value is 0x7d. +//! +//! \note Not all Tiva devices support this function. Please consult the +//! device data sheet to determine if this feature is supported. +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterTimeoutSet(uint32_t ui32Base, uint32_t ui32Value) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Write the timeout value. + // + HWREG(ui32Base + I2C_O_MCLKOCNT) = ui32Value; +} + +//***************************************************************************** +// +//! Configures ACK override behavior of the I2C Slave. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param bEnable enables or disables ACK override. +//! +//! This function enables or disables ACK override, allowing the user +//! application to drive the value on SDA during the ACK cycle. +//! +//! \note Not all Tiva devices support this function. Please consult the +//! device data sheet to determine if this feature is supported. +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveACKOverride(uint32_t ui32Base, bool bEnable) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Enable or disable based on bEnable. + // + if(bEnable) + { + HWREG(ui32Base + I2C_O_SACKCTL) |= I2C_SACKCTL_ACKOEN; + } + else + { + HWREG(ui32Base + I2C_O_SACKCTL) &= ~I2C_SACKCTL_ACKOEN; + } +} + +//***************************************************************************** +// +//! Writes the ACK value. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param bACK chooses whether to ACK (true) or NACK (false) the transfer. +//! +//! This function puts the desired ACK value on SDA during the ACK cycle. The +//! value written is only valid when ACK override is enabled using +//! I2CSlaveACKOverride(). +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveACKValueSet(uint32_t ui32Base, bool bACK) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // ACK or NACK based on the value of bACK. + // + if(bACK) + { + HWREG(ui32Base + I2C_O_SACKCTL) &= ~I2C_SACKCTL_ACKOVAL; + } + else + { + HWREG(ui32Base + I2C_O_SACKCTL) |= I2C_SACKCTL_ACKOVAL; + } +} + +//***************************************************************************** +// +//! Gets the I2C Slave status +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! This function returns the action requested from a master, if any. +//! Possible values are: +//! +//! - \b I2C_SLAVE_ACT_NONE +//! - \b I2C_SLAVE_ACT_RREQ +//! - \b I2C_SLAVE_ACT_TREQ +//! - \b I2C_SLAVE_ACT_RREQ_FBR +//! - \b I2C_SLAVE_ACT_OWN2SEL +//! - \b I2C_SLAVE_ACT_QCMD +//! - \b I2C_SLAVE_ACT_QCMD_DATA +//! +//! \note Not all Tiva devices support the second I2C slave's own address +//! or the quick command function. Please consult the device data sheet to +//! determine if these features are supported. +//! +//! \return Returns \b I2C_SLAVE_ACT_NONE to indicate that no action has been +//! requested of the I2C Slave, \b I2C_SLAVE_ACT_RREQ to indicate that +//! an I2C master has sent data to the I2C Slave, \b I2C_SLAVE_ACT_TREQ +//! to indicate that an I2C master has requested that the I2C Slave send +//! data, \b I2C_SLAVE_ACT_RREQ_FBR to indicate that an I2C master has sent +//! data to the I2C slave and the first byte following the slave's own address +//! has been received, \b I2C_SLAVE_ACT_OWN2SEL to indicate that the second I2C +//! slave address was matched, \b I2C_SLAVE_ACT_QCMD to indicate that a quick +//! command was received, and \b I2C_SLAVE_ACT_QCMD_DATA to indicate that the +//! data bit was set when the quick command was received. +// +//***************************************************************************** +uint32_t +I2CSlaveStatus(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Return the slave status. + // + return(HWREG(ui32Base + I2C_O_SCSR)); +} + +//***************************************************************************** +// +//! Transmits a byte from the I2C Slave. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui8Data is the data to be transmitted from the I2C Slave +//! +//! This function places the supplied data into I2C Slave Data Register. +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Write the byte. + // + HWREG(ui32Base + I2C_O_SDR) = ui8Data; +} + +//***************************************************************************** +// +//! Receives a byte that has been sent to the I2C Slave. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! This function reads a byte of data from the I2C Slave Data Register. +//! +//! \return Returns the byte received from by the I2C Slave, cast as an +//! uint32_t. +// +//***************************************************************************** +uint32_t +I2CSlaveDataGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Read a byte. + // + return(HWREG(ui32Base + I2C_O_SDR)); +} + +//***************************************************************************** +// +//! Configures the I2C transmit (TX) FIFO. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui32Config is the configuration of the FIFO using specified macros. +//! +//! This configures the I2C peripheral's transmit FIFO. The transmit FIFO can +//! be used by the master or slave, but not both. The following macros are +//! used to configure the TX FIFO behavior for master or slave, with or without +//! DMA: +//! +//! \b I2C_FIFO_CFG_TX_MASTER, \b I2C_FIFO_CFG_TX_SLAVE, +//! \b I2C_FIFO_CFG_TX_MASTER_DMA, \b I2C_FIFO_CFG_TX_SLAVE_DMA +//! +//! To select the trigger level, one of the following macros should be used: +//! +//! \b I2C_FIFO_CFG_TX_TRIG_1, \b I2C_FIFO_CFG_TX_TRIG_2, +//! \b I2C_FIFO_CFG_TX_TRIG_3, \b I2C_FIFO_CFG_TX_TRIG_4, +//! \b I2C_FIFO_CFG_TX_TRIG_5, \b I2C_FIFO_CFG_TX_TRIG_6, +//! \b I2C_FIFO_CFG_TX_TRIG_7, \b I2C_FIFO_CFG_TX_TRIG_8 +//! +//! \note Not all Tiva devices have an I2C FIFO. Please consult the +//! device data sheet to determine if this feature is supported. +//! +//! \return None. +// +//***************************************************************************** +void +I2CTxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Clear transmit configuration data. + // + HWREG(ui32Base + I2C_O_FIFOCTL) &= 0xffff0000; + + // + // Store new transmit configuration data. + // + HWREG(ui32Base + I2C_O_FIFOCTL) |= ui32Config; +} + +//***************************************************************************** +// +//! Flushes the transmit (TX) FIFO. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! This function flushes the I2C transmit FIFO. +//! +//! \note Not all Tiva devices have an I2C FIFO. Please consult the +//! device data sheet to determine if this feature is supported. +//! +//! \return None. +// +//***************************************************************************** +void +I2CTxFIFOFlush(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Flush the TX FIFO. + // + HWREG(ui32Base + I2C_O_FIFOCTL) |= I2C_FIFOCTL_TXFLUSH; +} + +//***************************************************************************** +// +//! Configures the I2C receive (RX) FIFO. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui32Config is the configuration of the FIFO using specified macros. +//! +//! This configures the I2C peripheral's receive FIFO. The receive FIFO can be +//! used by the master or slave, but not both. The following macros are used +//! to configure the RX FIFO behavior for master or slave, with or without DMA: +//! +//! \b I2C_FIFO_CFG_RX_MASTER, \b I2C_FIFO_CFG_RX_SLAVE, +//! \b I2C_FIFO_CFG_RX_MASTER_DMA, \b I2C_FIFO_CFG_RX_SLAVE_DMA +//! +//! To select the trigger level, one of the following macros should be used: +//! +//! \b I2C_FIFO_CFG_RX_TRIG_1, \b I2C_FIFO_CFG_RX_TRIG_2, +//! \b I2C_FIFO_CFG_RX_TRIG_3, \b I2C_FIFO_CFG_RX_TRIG_4, +//! \b I2C_FIFO_CFG_RX_TRIG_5, \b I2C_FIFO_CFG_RX_TRIG_6, +//! \b I2C_FIFO_CFG_RX_TRIG_7, \b I2C_FIFO_CFG_RX_TRIG_8 +//! +//! \note Not all Tiva devices have an I2C FIFO. Please consult the +//! device data sheet to determine if this feature is supported. +//! +//! \return None. +// +//***************************************************************************** +void +I2CRxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Clear receive configuration data. + // + HWREG(ui32Base + I2C_O_FIFOCTL) &= 0x0000ffff; + + // + // Store new receive configuration data. + // + HWREG(ui32Base + I2C_O_FIFOCTL) |= ui32Config; +} + +//***************************************************************************** +// +//! Flushes the receive (RX) FIFO. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! This function flushes the I2C receive FIFO. +//! +//! \note Not all Tiva devices have an I2C FIFO. Please consult the +//! device data sheet to determine if this feature is supported. +//! +//! \return None. +// +//***************************************************************************** +void +I2CRxFIFOFlush(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Flush the TX FIFO. + // + HWREG(ui32Base + I2C_O_FIFOCTL) |= I2C_FIFOCTL_RXFLUSH; +} + +//***************************************************************************** +// +//! Gets the current FIFO status. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! This function retrieves the status for both the transmit (TX) and receive +//! (RX) FIFOs. The trigger level for the transmit FIFO is set using +//! I2CTxFIFOConfigSet() and for the receive FIFO using I2CTxFIFOConfigSet(). +//! +//! \note Not all Tiva devices have an I2C FIFO. Please consult the +//! device data sheet to determine if this feature is supported. +//! +//! \return Returns the FIFO status, enumerated as a bit field containing +//! \b I2C_FIFO_RX_BELOW_TRIG_LEVEL, \b I2C_FIFO_RX_FULL, \b I2C_FIFO_RX_EMPTY, +//! \b I2C_FIFO_TX_BELOW_TRIG_LEVEL, \b I2C_FIFO_TX_FULL, and +//! \b I2C_FIFO_TX_EMPTY. +// +//***************************************************************************** +uint32_t +I2CFIFOStatus(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Return the contents of the FIFO status register. + // + return(HWREG(ui32Base + I2C_O_FIFOSTATUS)); +} + +//***************************************************************************** +// +//! Writes a data byte to the I2C transmit FIFO. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui8Data is the data to be placed into the transmit FIFO. +//! +//! This function adds a byte of data to the I2C transmit FIFO. If there is +//! no space available in the FIFO, this function waits for space to become +//! available before returning. +//! +//! \note Not all Tiva devices have an I2C FIFO. Please consult the +//! device data sheet to determine if this feature is supported. +//! +//! \return None. +// +//***************************************************************************** +void +I2CFIFODataPut(uint32_t ui32Base, uint8_t ui8Data) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Wait until there is space. + // + while(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_TXFF) + { + } + + // + // Place data into the FIFO. + // + HWREG(ui32Base + I2C_O_FIFODATA) = ui8Data; +} + +//***************************************************************************** +// +//! Writes a data byte to the I2C transmit FIFO. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui8Data is the data to be placed into the transmit FIFO. +//! +//! This function adds a byte of data to the I2C transmit FIFO. If there is +//! no space available in the FIFO, this function returns a zero. +//! +//! \note Not all Tiva devices have an I2C FIFO. Please consult the +//! device data sheet to determine if this feature is supported. +//! +//! \return The number of elements added to the I2C transmit FIFO. +// +//***************************************************************************** +uint32_t +I2CFIFODataPutNonBlocking(uint32_t ui32Base, uint8_t ui8Data) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // If FIFO is full, return zero. + // + if(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_TXFF) + { + return(0); + } + else + { + HWREG(ui32Base + I2C_O_FIFODATA) = ui8Data; + return(1); + } +} + +//***************************************************************************** +// +//! Reads a byte from the I2C receive FIFO. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! This function reads a byte of data from I2C receive FIFO and places it in +//! the location specified by the \e pui8Data parameter. If there is no data +//! available, this function waits until data is received before returning. +//! +//! \note Not all Tiva devices have an I2C FIFO. Please consult the +//! device data sheet to determine if this feature is supported. +//! +//! \return The data byte. +// +//***************************************************************************** +uint32_t +I2CFIFODataGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Wait until there is data to read. + // + while(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_RXFE) + { + } + + // + // Read a byte. + // + return(HWREG(ui32Base + I2C_O_FIFODATA)); +} + +//***************************************************************************** +// +//! Reads a byte from the I2C receive FIFO. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param pui8Data is a pointer where the read data is stored. +//! +//! This function reads a byte of data from I2C receive FIFO and places it in +//! the location specified by the \e pui8Data parameter. If there is no data +//! available, this functions returns 0. +//! +//! \note Not all Tiva devices have an I2C FIFO. Please consult the +//! device data sheet to determine if this feature is supported. +//! +//! \return The number of elements read from the I2C receive FIFO. +// +//***************************************************************************** +uint32_t +I2CFIFODataGetNonBlocking(uint32_t ui32Base, uint8_t *pui8Data) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // If nothing in the FIFO, return zero. + // + if(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_RXFE) + { + return(0); + } + else + { + *pui8Data = HWREG(ui32Base + I2C_O_FIFODATA); + return(1); + } +} + +//***************************************************************************** +// +//! Set the burst length for a I2C master FIFO operation. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui8Length is the length of the burst transfer. +//! +//! This function configures the burst length for a I2C Master FIFO operation. +//! The burst field is limited to 8 bits or 256 bytes. The burst length +//! applies to a single I2CMCS BURST operation meaning that it specifies the +//! burst length for only the current operation (can be TX or RX). Each burst +//! operation must configure the burst length prior to writing the BURST bit +//! in the I2CMCS using I2CMasterControl(). +//! +//! \note Not all Tiva devices have an I2C FIFO. Please consult the +//! device data sheet to determine if this feature is supported. +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterBurstLengthSet(uint32_t ui32Base, uint8_t ui8Length) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base) && (ui8Length < 256)); + + // + // Set the burst length. + // + HWREG(ui32Base + I2C_O_MBLEN) = ui8Length; +} + +//***************************************************************************** +// +//! Returns the current value of the burst transfer counter. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! This function returns the current value of the burst transfer counter that +//! is used by the FIFO mechanism. Software can use this value to determine +//! how many bytes remain in a transfer, or where in the transfer the burst +//! operation was if an error has occurred. +//! +//! \note Not all Tiva devices have an I2C FIFO. Please consult the +//! device data sheet to determine if this feature is supported. +//! +//! \return None. +// +//***************************************************************************** +uint32_t +I2CMasterBurstCountGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Get burst count. + // + return(HWREG(ui32Base + I2C_O_MBCNT)); +} + +//***************************************************************************** +// +//! Configures the I2C Master glitch filter. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui32Config is the glitch filter configuration. +//! +//! This function configures the I2C Master glitch filter. The value passed in +//! to \e ui32Config determines the sampling range of the glitch filter, which +//! is configurable between 1 and 32 system clock cycles. The default +//! configuration of the glitch filter is 0 system clock cycles, which means +//! that it's disabled. +//! +//! The \e ui32Config field should be any of the following values: +//! +//! - \b I2C_MASTER_GLITCH_FILTER_DISABLED +//! - \b I2C_MASTER_GLITCH_FILTER_1 +//! - \b I2C_MASTER_GLITCH_FILTER_2 +//! - \b I2C_MASTER_GLITCH_FILTER_3 +//! - \b I2C_MASTER_GLITCH_FILTER_4 +//! - \b I2C_MASTER_GLITCH_FILTER_8 +//! - \b I2C_MASTER_GLITCH_FILTER_16 +//! - \b I2C_MASTER_GLITCH_FILTER_32 +//! +//! \note Not all Tiva devices support this function. Please consult the +//! device data sheet to determine if this feature is supported. +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterGlitchFilterConfigSet(uint32_t ui32Base, uint32_t ui32Config) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Configure the glitch filter field of MTPR if it is TM4C129 + // + if(CLASS_IS_TM4C129) + { + HWREG(ui32Base + I2C_O_MTPR) |= ui32Config; + } + + // + // Configure the glitch filter if it is TM4C123 + // + if(CLASS_IS_TM4C123) + { + // + // Configure the glitch filter pulse width + // + HWREG(ui32Base + I2C_O_MCR2) |= (ui32Config >> 12); + + // + // Enable the glitch filter by setting the GFE bit + // + HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_GFE; + } +} + +//***************************************************************************** +// +//! Enables FIFO usage for the I2C Slave. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui32Config is the desired FIFO configuration of the I2C Slave. +//! +//! This function configures the I2C Slave to use the FIFO(s). This +//! function should be used in combination with I2CTxFIFOConfigSet() and/or +//! I2CRxFIFOConfigSet(), which configure the FIFO trigger level and tell +//! the FIFO hardware whether to interact with the I2C Master or Slave. The +//! application appropriate combination of \b I2C_SLAVE_TX_FIFO_ENABLE and +//! \b I2C_SLAVE_RX_FIFO_ENABLE should be passed in to the \e ui32Config +//! field. +//! +//! The Slave I2CSCSR register is write-only, so any call to I2CSlaveEnable(), +//! I2CSlaveDisable or I2CSlaveFIFOEnable() overwrites the slave configuration. +//! Therefore, application software should call I2CSlaveEnable() followed by +//! I2CSlaveFIFOEnable() with the desired FIFO configuration. +//! +//! \note Not all Tiva devices have an I2C FIFO. Please consult the +//! device data sheet to determine if this feature is supported. +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveFIFOEnable(uint32_t ui32Base, uint32_t ui32Config) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Enable the FIFOs for the slave. + // + HWREG(ui32Base + I2C_O_SCSR) = ui32Config | I2C_SCSR_DA; +} + +//***************************************************************************** +// +//! Disable FIFO usage for the I2C Slave. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! This function disables the FIFOs for the I2C Slave. After calling this +//! this function, the FIFOs are disabled, but the Slave remains active. +//! +//! \note Not all Tiva devices have an I2C FIFO. Please consult the +//! device data sheet to determine if this feature is supported. +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveFIFODisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Disable slave FIFOs. + // + HWREG(ui32Base + I2C_O_SCSR) = I2C_SCSR_DA; +} + +//***************************************************************************** +// +//! Enables internal loopback mode for an I2C port. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! This function configures an I2C port in internal loopback mode to help with +//! diagnostics and debug. In this mode, the SDA and SCL signals from master +//! and slave modules are internally connected. This allows data to be +//! transferred between the master and slave modules of the same I2C port, +//! without having to go through I/O's. I2CMasterDataPut(), I2CSlaveDataPut(), +//! I2CMasterDataGet(),I2CSlaveDataGet() can be used along with this function. +//! +//! \return None. +// +//***************************************************************************** +void I2CLoopbackEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Write the loopback enable bit to the register. + // + HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_LPBK; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/interrupt.c b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/interrupt.c new file mode 100644 index 0000000000000000000000000000000000000000..97dce2c1d69be605e1f37dc13fc097a38edd0303 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/interrupt.c @@ -0,0 +1,1060 @@ +//***************************************************************************** +// +// interrupt.c - Driver for the NVIC Interrupt Controller. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup interrupt_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include "hw_ints.h" +#include "hw_nvic.h" +#include "hw_types.h" +#include "cpu.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// This is a mapping between priority grouping encodings and the number of +// preemption priority bits. +// +//***************************************************************************** +static const uint32_t g_pui32Priority[] = +{ + NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6, + NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3, + NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1 +}; + +//***************************************************************************** +// +// This is a mapping between interrupt number and the register that contains +// the priority encoding for that interrupt. +// +//***************************************************************************** +static const uint32_t g_pui32Regs[] = +{ + 0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1, + NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7, + NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13, + NVIC_PRI14, NVIC_PRI15, NVIC_PRI16, NVIC_PRI17, NVIC_PRI18, NVIC_PRI19, + NVIC_PRI20, NVIC_PRI21, NVIC_PRI22, NVIC_PRI23, NVIC_PRI24, NVIC_PRI25, + NVIC_PRI26, NVIC_PRI27, NVIC_PRI28, NVIC_PRI29, NVIC_PRI30, NVIC_PRI31, + NVIC_PRI32, NVIC_PRI33, NVIC_PRI34 +}; + +//***************************************************************************** +// +// This is a mapping between interrupt number (for the peripheral interrupts +// only) and the register that contains the interrupt enable for that +// interrupt. +// +//***************************************************************************** +static const uint32_t g_pui32EnRegs[] = +{ + NVIC_EN0, NVIC_EN1, NVIC_EN2, NVIC_EN3, NVIC_EN4 +}; + +//***************************************************************************** +// +// This is a mapping between interrupt number (for the peripheral interrupts +// only) and the register that contains the interrupt disable for that +// interrupt. +// +//***************************************************************************** +static const uint32_t g_pui32Dii16Regs[] = +{ + NVIC_DIS0, NVIC_DIS1, NVIC_DIS2, NVIC_DIS3, NVIC_DIS4 +}; + +//***************************************************************************** +// +// This is a mapping between interrupt number (for the peripheral interrupts +// only) and the register that contains the interrupt pend for that interrupt. +// +//***************************************************************************** +static const uint32_t g_pui32PendRegs[] = +{ + NVIC_PEND0, NVIC_PEND1, NVIC_PEND2, NVIC_PEND3, NVIC_PEND4 +}; + +//***************************************************************************** +// +// This is a mapping between interrupt number (for the peripheral interrupts +// only) and the register that contains the interrupt unpend for that +// interrupt. +// +//***************************************************************************** +static const uint32_t g_pui32UnpendRegs[] = +{ + NVIC_UNPEND0, NVIC_UNPEND1, NVIC_UNPEND2, NVIC_UNPEND3, NVIC_UNPEND4 +}; + +//***************************************************************************** +// +//! \internal +//! The default interrupt handler. +//! +//! This is the default interrupt handler for all interrupts. It simply loops +//! forever so that the system state is preserved for observation by a +//! debugger. Since interrupts must be disabled before unregistering the +//! corresponding handler, this should never be called during normal operation. +//! +//! \return None. +// +//***************************************************************************** +static void +_IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// The processor vector table. +// +// This contains a list of the handlers for the various interrupt sources in +// the system. The layout of this list is defined by the hardware; assertion +// of an interrupt causes the processor to start executing directly at the +// address given in the corresponding location in this list. +// +//***************************************************************************** +// +// Set the size of the vector table to the largest number of interrupts of +// any device +// +#undef NUM_INTERRUPTS +#define NUM_INTERRUPTS 155 +#if defined(ewarm) +#pragma data_alignment=1024 +static __no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) @ "VTABLE"; +#elif defined(sourcerygxx) +static __attribute__((section(".cs3.region-head.ram"))) +void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__ ((aligned(1024))); +#elif defined(ccs) || defined(DOXYGEN) +#pragma DATA_ALIGN(g_pfnRAMVectors, 1024) +#pragma DATA_SECTION(g_pfnRAMVectors, ".vtable") +void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void); +#else +static __attribute__((section("vtable"))) +void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__((aligned(1024))); +#endif + +//***************************************************************************** +// +//! Enables the processor interrupt. +//! +//! This function allows the processor to respond to interrupts. This function +//! does not affect the set of interrupts enabled in the interrupt controller; +//! it just gates the single interrupt from the controller to the processor. +//! +//! \b Example: Enable interrupts to the processor. +//! +//! \verbatim +//! // +//! // Enable interrupts to the processor. +//! // +//! IntMasterEnable(); +//! +//! \endverbatim +//! +//! \return Returns \b true if interrupts were disabled when the function was +//! called or \b false if they were initially enabled. +// +//***************************************************************************** +bool +IntMasterEnable(void) +{ + // + // Enable processor interrupts. + // + return(CPUcpsie()); +} + +//***************************************************************************** +// +//! Disables the processor interrupt. +//! +//! This function prevents the processor from receiving interrupts. This +//! function does not affect the set of interrupts enabled in the interrupt +//! controller; it just gates the single interrupt from the controller to the +//! processor. +//! +//! \note Previously, this function had no return value. As such, it was +//! possible to include interrupt.h and call this function without +//! having included hw_types.h. Now that the return is a +//! bool, a compiler error occurs in this case. The solution +//! is to include hw_types.h before including interrupt.h. +//! +//! \b Example: Disable interrupts to the processor. +//! +//! \verbatim +//! // +//! // Disable interrupts to the processor. +//! // +//! IntMasterDisable(); +//! +//! \endverbatim +//! +//! \return Returns \b true if interrupts were already disabled when the +//! function was called or \b false if they were initially enabled. +// +//***************************************************************************** +bool +IntMasterDisable(void) +{ + // + // Disable processor interrupts. + // + return(CPUcpsid()); +} + +//***************************************************************************** +// +//! Registers a function to be called when an interrupt occurs. +//! +//! \param ui32Interrupt specifies the interrupt in question. +//! \param pfnHandler is a pointer to the function to be called. +//! +//! This function is used to specify the handler function to be called when the +//! given interrupt is asserted to the processor. The \e ui32Interrupt +//! parameter must be one of the valid \b INT_* values listed in Peripheral +//! Driver Library User's Guide and defined in the inc/hw_ints.h header file. +//! When the interrupt occurs, if it is enabled (via IntEnable()), the handler +//! function is called in interrupt context. Because the handler function can +//! preempt other code, care must be taken to protect memory or peripherals +//! that are accessed by the handler and other non-handler code. +//! +//! \note The use of this function (directly or indirectly via a peripheral +//! driver interrupt register function) moves the interrupt vector table from +//! flash to SRAM. Therefore, care must be taken when linking the application +//! to ensure that the SRAM vector table is located at the beginning of SRAM; +//! otherwise the NVIC does not look in the correct portion of memory for the +//! vector table (it requires the vector table be on a 1 kB memory alignment). +//! Normally, the SRAM vector table is so placed via the use of linker scripts. +//! See the discussion of compile-time versus run-time interrupt handler +//! registration in the introduction to this chapter. +//! +//! \b Example: Set the UART 0 interrupt handler. +//! +//! \verbatim +//! +//! // +//! // UART 0 interrupt handler. +//! // +//! void +//! UART0Handler(void) +//! { +//! // +//! // Handle interrupt. +//! // +//! } +//! +//! // +//! // Set the UART 0 interrupt handler. +//! // +//! IntRegister(INT_UART0, UART0Handler); +//! +//! \endverbatim +//! +//! \return None. +// +//***************************************************************************** +void +IntRegister(uint32_t ui32Interrupt, void (*pfnHandler)(void)) +{ + uint32_t ui32Idx, ui32Value; + + // + // Check the arguments. + // + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // + // Make sure that the RAM vector table is correctly aligned. + // + ASSERT(((uint32_t)g_pfnRAMVectors & 0x000003ff) == 0); + + // + // See if the RAM vector table has been initialized. + // + if(HWREG(NVIC_VTABLE) != (uint32_t)g_pfnRAMVectors) + { + // + // Copy the vector table from the beginning of FLASH to the RAM vector + // table. + // + ui32Value = HWREG(NVIC_VTABLE); + for(ui32Idx = 0; ui32Idx < NUM_INTERRUPTS; ui32Idx++) + { + g_pfnRAMVectors[ui32Idx] = (void (*)(void))HWREG((ui32Idx * 4) + + ui32Value); + } + + // + // Point the NVIC at the RAM vector table. + // + HWREG(NVIC_VTABLE) = (uint32_t)g_pfnRAMVectors; + } + + // + // Save the interrupt handler. + // + g_pfnRAMVectors[ui32Interrupt] = pfnHandler; +} + +//***************************************************************************** +// +//! Unregisters the function to be called when an interrupt occurs. +//! +//! \param ui32Interrupt specifies the interrupt in question. +//! +//! This function is used to indicate that no handler is called when the +//! given interrupt is asserted to the processor. The \e ui32Interrupt +//! parameter must be one of the valid \b INT_* values listed in Peripheral +//! Driver Library User's Guide and defined in the inc/hw_ints.h header file. +//! The interrupt source is automatically disabled (via IntDisable()) if +//! necessary. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \b Example: Reset the UART 0 interrupt handler to the default handler. +//! +//! \verbatim +//! // +//! // Reset the UART 0 interrupt handler to the default handler. +//! // +//! IntUnregister(INT_UART0); +//! +//! \endverbatim +//! +//! \return None. +// +//***************************************************************************** +void +IntUnregister(uint32_t ui32Interrupt) +{ + // + // Check the arguments. + // + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // + // Reset the interrupt handler. + // + g_pfnRAMVectors[ui32Interrupt] = _IntDefaultHandler; +} + +//***************************************************************************** +// +//! Sets the priority grouping of the interrupt controller. +//! +//! \param ui32Bits specifies the number of bits of preemptable priority. +//! +//! This function specifies the split between preemptable priority levels and +//! sub-priority levels in the interrupt priority specification. The range of +//! the grouping values are dependent upon the hardware implementation; on +//! the Tiva C and E Series family, three bits are available for hardware +//! interrupt prioritization and therefore priority grouping values of three +//! through seven have the same effect. +//! +//! \b Example: Set the priority grouping for the interrupt controller. +//! +//! \verbatim +//! // +//! // Set the priority grouping for the interrupt controller to 2 bits. +//! // +//! IntPriorityGroupingSet(2); +//! +//! \endverbatim +//! +//! \return None. +// +//***************************************************************************** +void +IntPriorityGroupingSet(uint32_t ui32Bits) +{ + // + // Check the arguments. + // + ASSERT(ui32Bits < NUM_PRIORITY); + + // + // Set the priority grouping. + // + HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pui32Priority[ui32Bits]; +} + +//***************************************************************************** +// +//! Gets the priority grouping of the interrupt controller. +//! +//! This function returns the split between preemptable priority levels and +//! sub-priority levels in the interrupt priority specification. +//! +//! \b Example: Get the priority grouping for the interrupt controller. +//! +//! \verbatim +//! // +//! // Get the priority grouping for the interrupt controller. +//! // +//! IntPriorityGroupingGet(); +//! +//! \endverbatim +//! +//! \return The number of bits of preemptable priority. +// +//***************************************************************************** +uint32_t +IntPriorityGroupingGet(void) +{ + uint32_t ui32Loop, ui32Value; + + // + // Read the priority grouping. + // + ui32Value = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M; + + // + // Loop through the priority grouping values. + // + for(ui32Loop = 0; ui32Loop < NUM_PRIORITY; ui32Loop++) + { + // + // Stop looping if this value matches. + // + if(ui32Value == g_pui32Priority[ui32Loop]) + { + break; + } + } + + // + // Return the number of priority bits. + // + return(ui32Loop); +} + +//***************************************************************************** +// +//! Sets the priority of an interrupt. +//! +//! \param ui32Interrupt specifies the interrupt in question. +//! \param ui8Priority specifies the priority of the interrupt. +//! +//! This function is used to set the priority of an interrupt. The +//! \e ui32Interrupt parameter must be one of the valid \b INT_* values listed +//! in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h +//! header file. The \e ui8Priority parameter specifies the interrupts +//! hardware priority level of the interrupt in the interrupt controller. +//! When multiple interrupts are asserted simultaneously, the ones with the +//! highest priority are processed before the lower priority interrupts. +//! Smaller numbers correspond to higher interrupt priorities; priority 0 is +//! the highest interrupt priority. +//! +//! \note The hardware priority mechanism only looks at the upper 3 bits of the +//! priority level, so any prioritization must be performed in those bits. The +//! remaining bits can be used to sub-prioritize the interrupt sources, and may +//! be used by the hardware priority mechanism on a future part. This +//! arrangement allows priorities to migrate to different NVIC implementations +//! without changing the gross prioritization of the interrupts. +//! +//! \b Example: Set priorities for UART 0 and USB interrupts. +//! +//! \verbatim +//! // +//! // Set the UART 0 interrupt priority to the lowest priority. +//! // +//! IntPrioritySet(INT_UART0, 0xE0); +//! +//! // +//! // Set the USB 0 interrupt priority to the highest priority. +//! // +//! IntPrioritySet(INT_USB0, 0); +//! +//! \endverbatim +//! +//! \return None. +// +//***************************************************************************** +void +IntPrioritySet(uint32_t ui32Interrupt, uint8_t ui8Priority) +{ + uint32_t ui32Temp; + + // + // Check the arguments. + // + ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS)); + + // + // Set the interrupt priority. + // + ui32Temp = HWREG(g_pui32Regs[ui32Interrupt >> 2]); + ui32Temp &= ~(0xFF << (8 * (ui32Interrupt & 3))); + ui32Temp |= ui8Priority << (8 * (ui32Interrupt & 3)); + HWREG(g_pui32Regs[ui32Interrupt >> 2]) = ui32Temp; +} + +//***************************************************************************** +// +//! Gets the priority of an interrupt. +//! +//! \param ui32Interrupt specifies the interrupt in question. +//! +//! This function gets the priority of an interrupt. The \e ui32Interrupt +//! parameter must be one of the valid \b INT_* values listed in Peripheral +//! Driver Library User's Guide and defined in the inc/hw_ints.h header file. +//! See IntPrioritySet() for a full definition of the priority value. +//! +//! \b Example: Get the current UART 0 interrupt priority. +//! +//! \verbatim +//! // +//! // Get the current UART 0 interrupt priority. +//! // +//! IntPriorityGet(INT_UART0); +//! +//! \endverbatim +//! +//! \return Returns the interrupt priority for the given interrupt. +// +//***************************************************************************** +int32_t +IntPriorityGet(uint32_t ui32Interrupt) +{ + // + // Check the arguments. + // + ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS)); + + // + // Return the interrupt priority. + // + return((HWREG(g_pui32Regs[ui32Interrupt >> 2]) >> + (8 * (ui32Interrupt & 3))) & 0xFF); +} + +//***************************************************************************** +// +//! Enables an interrupt. +//! +//! \param ui32Interrupt specifies the interrupt to be enabled. +//! +//! The specified interrupt is enabled in the interrupt controller. The +//! \e ui32Interrupt parameter must be one of the valid \b INT_* values listed +//! in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h +//! header file. Other enables for the interrupt (such as at the peripheral +//! level) are unaffected by this function. +//! +//! \b Example: Enable the UART 0 interrupt. +//! +//! \verbatim +//! // +//! // Enable the UART 0 interrupt in the interrupt controller. +//! // +//! IntEnable(INT_UART0); +//! +//! \endverbatim +//! +//! \return None. +// +//***************************************************************************** +void +IntEnable(uint32_t ui32Interrupt) +{ + // + // Check the arguments. + // + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // + // Determine the interrupt to enable. + // + if(ui32Interrupt == FAULT_MPU) + { + // + // Enable the MemManage interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM; + } + else if(ui32Interrupt == FAULT_BUS) + { + // + // Enable the bus fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS; + } + else if(ui32Interrupt == FAULT_USAGE) + { + // + // Enable the usage fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE; + } + else if(ui32Interrupt == FAULT_SYSTICK) + { + // + // Enable the System Tick interrupt. + // + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; + } + else if(ui32Interrupt >= 16) + { + // + // Enable the general interrupt. + // + HWREG(g_pui32EnRegs[(ui32Interrupt - 16) / 32]) = + 1 << ((ui32Interrupt - 16) & 31); + } +} + +//***************************************************************************** +// +//! Disables an interrupt. +//! +//! \param ui32Interrupt specifies the interrupt to be disabled. +//! +//! The specified interrupt is disabled in the interrupt controller. The +//! \e ui32Interrupt parameter must be one of the valid \b INT_* values listed +//! in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h +//! header file. Other enables for the interrupt (such as at the peripheral +//! level) are unaffected by this function. +//! +//! \b Example: Disable the UART 0 interrupt. +//! +//! \verbatim +//! // +//! // Disable the UART 0 interrupt in the interrupt controller. +//! // +//! IntDisable(INT_UART0); +//! +//! \endverbatim +//! +//! \return None. +// +//***************************************************************************** +void +IntDisable(uint32_t ui32Interrupt) +{ + // + // Check the arguments. + // + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // + // Determine the interrupt to disable. + // + if(ui32Interrupt == FAULT_MPU) + { + // + // Disable the MemManage interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM); + } + else if(ui32Interrupt == FAULT_BUS) + { + // + // Disable the bus fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS); + } + else if(ui32Interrupt == FAULT_USAGE) + { + // + // Disable the usage fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE); + } + else if(ui32Interrupt == FAULT_SYSTICK) + { + // + // Disable the System Tick interrupt. + // + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); + } + else if(ui32Interrupt >= 16) + { + // + // Disable the general interrupt. + // + HWREG(g_pui32Dii16Regs[(ui32Interrupt - 16) / 32]) = + 1 << ((ui32Interrupt - 16) & 31); + } +} + +//***************************************************************************** +// +//! Returns if a peripheral interrupt is enabled. +//! +//! \param ui32Interrupt specifies the interrupt to check. +//! +//! This function checks if the specified interrupt is enabled in the interrupt +//! controller. The \e ui32Interrupt parameter must be one of the valid +//! \b INT_* values listed in Peripheral Driver Library User's Guide and +//! defined in the inc/hw_ints.h header file. +//! +//! \b Example: Disable the UART 0 interrupt if it is enabled. +//! +//! \verbatim +//! // +//! // Disable the UART 0 interrupt if it is enabled. +//! // +//! if(IntIsEnabled(INT_UART0)) +//! { +//! IntDisable(INT_UART0); +//! } +//! \endverbatim +//! +//! \return A non-zero value if the interrupt is enabled. +// +//***************************************************************************** +uint32_t +IntIsEnabled(uint32_t ui32Interrupt) +{ + uint32_t ui32Ret; + + // + // Check the arguments. + // + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // + // Initialize the return value. + // + ui32Ret = 0; + + // + // Determine the interrupt to disable. + // + if(ui32Interrupt == FAULT_MPU) + { + // + // Check the MemManage interrupt. + // + ui32Ret = HWREG(NVIC_SYS_HND_CTRL) & NVIC_SYS_HND_CTRL_MEM; + } + else if(ui32Interrupt == FAULT_BUS) + { + // + // Check the bus fault interrupt. + // + ui32Ret = HWREG(NVIC_SYS_HND_CTRL) & NVIC_SYS_HND_CTRL_BUS; + } + else if(ui32Interrupt == FAULT_USAGE) + { + // + // Check the usage fault interrupt. + // + ui32Ret = HWREG(NVIC_SYS_HND_CTRL) & NVIC_SYS_HND_CTRL_USAGE; + } + else if(ui32Interrupt == FAULT_SYSTICK) + { + // + // Check the System Tick interrupt. + // + ui32Ret = HWREG(NVIC_ST_CTRL) & NVIC_ST_CTRL_INTEN; + } + else if(ui32Interrupt >= 16) + { + // + // Check the general interrupt. + // + ui32Ret = HWREG(g_pui32EnRegs[(ui32Interrupt - 16) / 32]) & + (1 << ((ui32Interrupt - 16) & 31)); + } + return(ui32Ret); +} + +//***************************************************************************** +// +//! Pends an interrupt. +//! +//! \param ui32Interrupt specifies the interrupt to be pended. +//! +//! The specified interrupt is pended in the interrupt controller. The +//! \e ui32Interrupt parameter must be one of the valid \b INT_* values listed +//! in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h +//! header file. Pending an interrupt causes the interrupt controller to +//! execute the corresponding interrupt handler at the next available time, +//! based on the current interrupt state priorities. For example, if called by +//! a higher priority interrupt handler, the specified interrupt handler is not +//! called until after the current interrupt handler has completed execution. +//! The interrupt must have been enabled for it to be called. +//! +//! \b Example: Pend a UART 0 interrupt. +//! +//! \verbatim +//! // +//! // Pend a UART 0 interrupt. +//! // +//! IntPendSet(INT_UART0); +//! \endverbatim +//! +//! \return None. +// +//***************************************************************************** +void +IntPendSet(uint32_t ui32Interrupt) +{ + // + // Check the arguments. + // + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // + // Determine the interrupt to pend. + // + if(ui32Interrupt == FAULT_NMI) + { + // + // Pend the NMI interrupt. + // + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_NMI_SET; + } + else if(ui32Interrupt == FAULT_PENDSV) + { + // + // Pend the PendSV interrupt. + // + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PEND_SV; + } + else if(ui32Interrupt == FAULT_SYSTICK) + { + // + // Pend the SysTick interrupt. + // + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTSET; + } + else if(ui32Interrupt >= 16) + { + // + // Pend the general interrupt. + // + HWREG(g_pui32PendRegs[(ui32Interrupt - 16) / 32]) = + 1 << ((ui32Interrupt - 16) & 31); + } +} + +//***************************************************************************** +// +//! Un-pends an interrupt. +//! +//! \param ui32Interrupt specifies the interrupt to be un-pended. The +//! \e ui32Interrupt parameter must be one of the valid \b INT_* values listed +//! in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h +//! header file. +//! +//! The specified interrupt is un-pended in the interrupt controller. This +//! causes any previously generated interrupts that have not been handled +//! yet (due to higher priority interrupts or the interrupt not having been +//! enabled yet) to be discarded. +//! +//! \b Example: Un-pend a UART 0 interrupt. +//! +//! \verbatim +//! // +//! // Un-pend a UART 0 interrupt. +//! // +//! IntPendClear(INT_UART0); +//! \endverbatim +//! +//! \return None. +// +//***************************************************************************** +void +IntPendClear(uint32_t ui32Interrupt) +{ + // + // Check the arguments. + // + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // + // Determine the interrupt to unpend. + // + if(ui32Interrupt == FAULT_PENDSV) + { + // + // Unpend the PendSV interrupt. + // + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_UNPEND_SV; + } + else if(ui32Interrupt == FAULT_SYSTICK) + { + // + // Unpend the SysTick interrupt. + // + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTCLR; + } + else if(ui32Interrupt >= 16) + { + // + // Unpend the general interrupt. + // + HWREG(g_pui32UnpendRegs[(ui32Interrupt - 16) / 32]) = + 1 << ((ui32Interrupt - 16) & 31); + } +} + +//***************************************************************************** +// +//! Sets the priority masking level +//! +//! \param ui32PriorityMask is the priority level that is masked. +//! +//! This function sets the interrupt priority masking level so that all +//! interrupts at the specified or lesser priority level are masked. Masking +//! interrupts can be used to globally disable a set of interrupts with +//! priority below a predetermined threshold. A value of 0 disables priority +//! masking. +//! +//! Smaller numbers correspond to higher interrupt priorities. So for example +//! a priority level mask of 4 allows interrupts of priority level 0-3, +//! and interrupts with a numerical priority of 4 and greater are blocked. +//! +//! \note The hardware priority mechanism only looks at the upper 3 bits of the +//! priority level, so any prioritization must be performed in those bits. +//! +//! \b Example: Mask of interrupt priorities greater than or equal to 0x80. +//! +//! \verbatim +//! // +//! // Mask of interrupt priorities greater than or equal to 0x80. +//! // +//! IntPriorityMaskSet(0x80); +//! \endverbatim +//! +//! \return None. +// +//***************************************************************************** +void +IntPriorityMaskSet(uint32_t ui32PriorityMask) +{ + // + // Set the priority mask. + // + CPUbasepriSet(ui32PriorityMask); +} + +//***************************************************************************** +// +//! Gets the priority masking level +//! +//! This function gets the current setting of the interrupt priority masking +//! level. The value returned is the priority level such that all interrupts +//! of that and lesser priority are masked. A value of 0 means that priority +//! masking is disabled. +//! +//! Smaller numbers correspond to higher interrupt priorities. So for example +//! a priority level mask of 4 allows interrupts of priority level 0-3, +//! and interrupts with a numerical priority of 4 and greater are blocked. +//! +//! The hardware priority mechanism only looks at the upper 3 bits of the +//! priority level, so any prioritization must be performed in those bits. +//! +//! \b Example: Get the current interrupt priority mask. +//! +//! \verbatim +//! // +//! // Get the current interrupt priority mask. +//! // +//! IntPriorityMaskGet(); +//! \endverbatim +//! +//! \return Returns the value of the interrupt priority level mask. +// +//***************************************************************************** +uint32_t +IntPriorityMaskGet(void) +{ + // + // Return the current priority mask. + // + return(CPUbasepriGet()); +} + +//***************************************************************************** +// +//! Triggers an interrupt. +//! +//! \param ui32Interrupt specifies the interrupt to be triggered. +//! +//! This function performs a software trigger of an interrupt. The +//! \e ui32Interrupt parameter must be one of the valid \b INT_* values listed +//! in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h +//! header file. The interrupt controller behaves as if the corresponding +//! interrupt line was asserted, and the interrupt is handled in the same +//! manner (meaning that it must be enabled in order to be processed, and the +//! processing is based on its priority with respect to other unhandled +//! interrupts). +//! +//! \return None. +// +//***************************************************************************** +void +IntTrigger(uint32_t ui32Interrupt) +{ + // + // Check the arguments. + // + ASSERT((ui32Interrupt >= 16) && (ui32Interrupt < NUM_INTERRUPTS)); + + // + // Trigger this interrupt. + // + HWREG(NVIC_SW_TRIG) = ui32Interrupt - 16; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/lcd.c b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/lcd.c new file mode 100644 index 0000000000000000000000000000000000000000..195d0ef0ba19590592d7e22545e3a38b3836ced5 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/lcd.c @@ -0,0 +1,1805 @@ +//***************************************************************************** +// +// lcd.c - Defines and Macros for the LCD Controller module. +// +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup lcd_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_ints.h" +#include "inc/hw_lcd.h" +#include "driverlib/interrupt.h" +#include "driverlib/sysctl.h" +#include "driverlib/lcd.h" +#include "driverlib/debug.h" + +//***************************************************************************** +// +// These are currently missing from hw_lcd.h and included here as a stopgap +// until the hardware header is updated. +// +//***************************************************************************** +#ifndef LCD_RASTRTIM0_MSBPPL_S +#define LCD_RASTRTIM0_MSBPPL_S 3 +#endif +#ifndef LCD_RASTRTIM2_MSBLPP_S +#define LCD_RASTRTIM2_MSBLPP_S 26 +#endif + +//***************************************************************************** +// +//! Configures the basic operating mode and clock rate for the LCD controller. +//! +//! \param ui32Base specifies the LCD controller module base address. +//! \param ui8Mode specifies the basic operating mode to be used. +//! \param ui32PixClk specifies the desired LCD controller pixel or master +//! clock rate in Hz. +//! \param ui32SysClk specifies the current system clock rate in Hz. +//! +//! This function sets the basic operating mode of the LCD controller and also +//! its master clock. The \e ui8Mode parameter may be set to either \b +//! LCD_MODE_LIDD or \b LCD_MODE_RASTER. \b LCD_MODE_LIDD is used to select +//! LCD Interface Display Driver mode for character panels connected via +//! an asynchronous interface (CS, WE, OE, ALE, data) and \b LCD_MODE_RASTER +//! is used to communicate with panels via a synchronous video interface using +//! data and sync signals. Additionally, \b LCD_MODE_AUTO_UFLOW_RESTART may +//! be ORed with either of these modes to indicate that the hardware should +//! restart automatically if a data underflow occurs. +//! +//! The \e ui32PixClk parameter specifies the desired master clock for the +//! the LCD controller. In LIDD mode, this value controls the MCLK used in +//! communication with the display and valid values are between \e ui32SysClk +//! and \e ui32SysClk/255. In raster mode, \e ui32PixClk specifies the pixel +//! clock rate for the raster interface and valid values are between \e +//! ui32SysClk/2 and \e ui32SysClk/255. The actual clock rate set may differ +//! slightly from the desired rate due to the fact that only integer dividers +//! are supported. The rate set will, however, be no higher than the requested +//! value. +//! +//! The \e ui32SysClk parameter provides the current system clock rate and is +//! used to allow the LCD controller clock rate divisor to be correctly set +//! to give the desired \e ui32PixClk rate. +//! +//! \return Returns the actual LCD controller pixel clock or MCLK rate set. +// +//***************************************************************************** +uint32_t +LCDModeSet(uint32_t ui32Base, uint8_t ui8Mode, uint32_t ui32PixClk, + uint32_t ui32SysClk) +{ + uint32_t ui32Div; + + // + // Sanity check parameters. + // + ASSERT(ui32Base == LCD0_BASE); + ASSERT((ui8Mode & ~(LCD_MODE_RASTER | LCD_MODE_LIDD | + LCD_MODE_AUTO_UFLOW_RESTART)) == 0); + + // + // Enable clocks to the LCD controller submodules. + // + HWREG(ui32Base + LCD_O_CLKEN) = (LCD_CLKEN_DMA | LCD_CLKEN_CORE | + LCD_CLKEN_LIDD); + + // + // Determine the clock divider to use to get as close as possible to the + // desired pixel clock. Note that we set the division up so that we + // round the divisor up and ensure that the clock used is never faster + // than the requested rate. + // + ui32Div = (ui32SysClk + (ui32PixClk - 1)) / ui32PixClk; + + // + // Check that the calculated value is valid. + // + ASSERT(ui32Div); + ASSERT(ui32Div < 256); + ASSERT(!((ui8Mode & LCD_MODE_RASTER) && (ui32Div < 2))); + + // + // Write the LCDCTL register to set the mode. + // + HWREG(ui32Base + LCD_O_CTL) = (uint32_t)ui8Mode | + (ui32Div << LCD_CTL_CLKDIV_S); + + // + // Return the selected clock rate. Finding ui32Div set to 0 should not + // happen unless someone passed pathological arguments and builds without + // the ASSERTS, but we guard against it just in case. + // + return(ui32Div ? (ui32SysClk / ui32Div) : ui32SysClk); +} + +//***************************************************************************** +// +//! Resets one or more of the LCD controller clock domains. +//! +//! \param ui32Base specifies the LCD controller module base address. +//! \param ui32Clocks defines the subset of clock domains to be reset. +//! +//! This function allows sub-modules of the LCD controller to be reset under +//! software control. The \e ui32Clocks parameter is the logical OR of the +//! following clocks: +//! +//! - \b LCD_CLOCK_MAIN causes the entire LCD controller module to be reset. +//! - \b LCD_CLOCK_DMA causes the DMA controller submodule to be reset. +//! - \b LCD_CLOCK_LIDD causes the LIDD submodule to be reset. +//! - \b LCD_CLOCK_CORE causes the core module, including the raster logic to +//! be reset. +//! +//! In all cases, LCD controller register values are preserved across these +//! resets. +//! +//! \return None. +// +//***************************************************************************** +void +LCDClockReset(uint32_t ui32Base, uint32_t ui32Clocks) +{ + // + // Sanity check parameters. + // + ASSERT(ui32Base == LCD0_BASE); + ASSERT(!(ui32Clocks & ~(LCD_CLOCK_MAIN | LCD_CLOCK_LIDD | LCD_CLOCK_DMA | + LCD_CLOCK_CORE))); + + // + // Reset the required LCD controller sub-module(s). + // + HWREG(LCD0_BASE + 0x70) = ui32Clocks; + + // + // Wait a while. + // + SysCtlDelay(10); + + // + // Remove software reset. + // + HWREG(LCD0_BASE + 0x70) = 0x00000000; + + // + // Wait a while. + // + SysCtlDelay(10); +} + +//***************************************************************************** +// +//! Sets the LCD controller communication parameters when in LIDD mode. +//! +//! \param ui32Base specifies the LCD controller module base address. +//! \param ui32Config defines the display interface configuration. +//! +//! This function is used when the LCD controller is configured in LIDD +//! mode and specifies the configuration of the interface between the +//! controller and the display panel. The \e ui32Config parameter is +//! comprised of one of the following modes: +//! +//! - \b LIDD_CONFIG_SYNC_MPU68 selects Sync MPU68 mode. LCDCP = EN, LCDLP = +//! DIR, LCDFP = ALE, LCDAC = CS0, LCDMCLK = MCLK. +//! - \b LIDD_CONFIG_ASYNC_MPU68 selects Async MPU68 mode. LCDCP = EN, LCDLP = +//! DIR, LCDFP = ALE, LCDAC = CS0, LCDMCLK = CS1. +//! - \b LIDD_CONFIG_SYNC_MPU80 selects Sync MPU80 mode. LCDCP = RS, LCDLP = +//! WS, LCDFP = ALE, LCDAC = CS0, LCDMCLK = MCLK. +//! - \b LIDD_CONFIG_ASYNC_MPU80 selects Async MPU80 mode. LCDCP = RS, LCDLP = +//! WS, LCDFP = ALE, LCDAC = CS0, LCDMCLK = CS1. +//! - \b LIDD_CONFIG_ASYNC_HITACHI selects Hitachi (async) mode. LCDCP = N/C, +//! LCDLP = DIR, LCDFP = ALE, LCDAC = E0, LCDMCLK = E1. +//! +//! Additional flags may be ORed into \e ui32Config to control the polarities +//! of various control signals: +//! +//! - \b LIDD_CONFIG_INVERT_ALE - Address Latch Enable (ALE) polarity control. +//! By default, ALE is active low. If this flag is set, it becomes active +//! high. +//! - \b LIDD_CONFIG_INVERT_RS_EN - Read Strobe/Enable polarity control. By +//! default, RS is active low and Enable is active high. If this flag is set, +//! RS becomes active high and Enable active low. +//! - \b LIDD_CONFIG_INVERT_WS_DIR - Write Strobe/Direction polarity control. +//! By default, WS is active low and Direction write low/read high. If this +//! flag is set, WS becomes active high and Direction becomes write high/read +//! low. +//! - \b LIDD_CONFIG_INVERT_CS0 - Chip Select 0/Enable 0 polarity control. By +//! default, CS0 and E0 are active high. If this flag is set, they become +//! active low. +//! - \b LIDD_CONFIG_INVERT_CS1 - Chip Select 1/Enable 1 polarity control. By +//! default, CS1 and E1 are active high. If this flag is set, they become +//! active low. +//! +//! \return None. +// +//***************************************************************************** +void +LCDIDDConfigSet(uint32_t ui32Base, uint32_t ui32Config) +{ + // + // Sanity check parameters. + // + ASSERT(ui32Base == LCD0_BASE); + ASSERT(!(ui32Config & ~(LIDD_CONFIG_SYNC_MPU68 | LIDD_CONFIG_ASYNC_MPU68 | + LIDD_CONFIG_SYNC_MPU80 | LIDD_CONFIG_ASYNC_MPU80 | + LIDD_CONFIG_ASYNC_HITACHI | + LIDD_CONFIG_INVERT_ALE | + LIDD_CONFIG_INVERT_RS_EN | + LIDD_CONFIG_INVERT_WS_DIR | + LIDD_CONFIG_INVERT_CS0 | LIDD_CONFIG_INVERT_CS1))); + + // + // Write the LIDD Control Register. + // + HWREG(ui32Base + LCD_O_LIDDCTL) = ui32Config; +} + +//***************************************************************************** +// +//! Sets the LCD controller interface timing when in LIDD mode. +//! +//! \param ui32Base specifies the LCD controller module base address. +//! \param ui32CS specifies the chip select whose timings are to be set. +//! \param pTiming points to a structure containing the desired timing +//! parameters. +//! +//! This function is used in LIDD mode to set the setup, strobe and hold times +//! for the various interface control signals. Independent timings are stored +//! for each of the two supported chip selects offered by the LCD controller. +//! +//! For a definition of the timing parameters required, see the definition of +//! tLCDIDDTiming. +//! +//! \note CS1 is not available when operating in Sync MPU68 or Sync MPU80 +//! modes. +//! +//! \return None +// +//***************************************************************************** +void +LCDIDDTimingSet(uint32_t ui32Base, uint32_t ui32CS, + const tLCDIDDTiming *pTiming) +{ + uint32_t ui32Val; + + // + // Sanity check parameters. + // + ASSERT(ui32Base == LCD0_BASE); + ASSERT((ui32CS == 0) || (ui32CS == 1)); + ASSERT(pTiming); + ASSERT(pTiming->ui8WSSetup < 32); + ASSERT(pTiming->ui8WSDuration && (pTiming->ui8WSDuration < 64)); + ASSERT(pTiming->ui8WSHold && (pTiming->ui8WSHold < 16)); + ASSERT(pTiming->ui8RSSetup < 32); + ASSERT(pTiming->ui8RSDuration && (pTiming->ui8RSDuration < 64)); + ASSERT(pTiming->ui8RSHold && (pTiming->ui8RSHold < 16)); + ASSERT(pTiming->ui8DelayCycles && (pTiming->ui8DelayCycles < 5)); + + // + // Convert the timings provided into a value ready for the register. + // + ui32Val = + (((uint32_t)(pTiming->ui8WSSetup) << LCD_LIDDCS0CFG_WRSU_S) | + ((uint32_t)(pTiming->ui8WSDuration) << LCD_LIDDCS0CFG_WRDUR_S) | + ((uint32_t)(pTiming->ui8WSHold) << LCD_LIDDCS0CFG_WRHOLD_S) | + ((uint32_t)(pTiming->ui8RSSetup) << LCD_LIDDCS0CFG_RDSU_S) | + ((uint32_t)(pTiming->ui8RSDuration) << LCD_LIDDCS0CFG_RDDUR_S) | + ((uint32_t)(pTiming->ui8RSHold) << LCD_LIDDCS0CFG_RDHOLD_S) | + ((uint32_t)(pTiming->ui8DelayCycles - 1) << LCD_LIDDCS0CFG_GAP_S)); + + // + // Write the appropriate LCD LIDD CS configuration register. + // + if(!ui32CS) + { + HWREG(ui32Base + LCD_O_LIDDCS0CFG) = ui32Val; + } + else + { + HWREG(ui32Base + LCD_O_LIDDCS1CFG) = ui32Val; + } +} + +//***************************************************************************** +// +//! Disables internal DMA operation when the LCD controller is in LIDD mode. +//! +//! \param ui32Base specifies the LCD controller module base address. +//! +//! When the LCD controller is operating in LCD Interface Display Driver mode, +//! this function must be called after completion of a DMA transaction and +//! before calling LCDIDDCommandWrite(), LCDIDDDataWrite(), LCDIDDStatusRead(), +//! LCDIDDIndexedWrite(), LCDIDDIndexedRead() or LCDIDDDataRead() to disable +//! DMA mode and allow CPU-initiated transactions to the display. +//! +//! \note LIDD DMA mode is enabled automatically when LCDIDDDMAWrite() is +//! called. +//! +//! \return None. +// +//***************************************************************************** +void +LCDIDDDMADisable(uint32_t ui32Base) +{ + // + // Sanity check parameters. + // + ASSERT(ui32Base == LCD0_BASE); + + // + // Disable DMA. + // + HWREG(ui32Base + LCD_O_LIDDCTL) &= ~LCD_LIDDCTL_DMAEN; +} + +//***************************************************************************** +// +//! Writes a command to the display when the LCD controller is in LIDD mode. +//! +//! \param ui32Base specifies the LCD controller module base address. +//! \param ui32CS specifies the chip select to use. Valid values are 0 and 1. +//! \param ui16Cmd is the 16-bit command word to write. +//! +//! This function writes a 16-bit command word to the display when the LCD +//! controller is in LIDD mode. A command write occurs with the ALE signal +//! active. +//! +//! This function must not be called if the LIDD interface is currently +//! configured to expect DMA transactions. If DMA was previously used to +//! write to the panel, LCDIDDDMADisable() must be called before this function +//! can be used. +//! +//! \note CS1 is not available when operating in Sync MPU68 or Sync MPU80 +//! modes. +//! +//! \return None. +// +//***************************************************************************** +void +LCDIDDCommandWrite(uint32_t ui32Base, uint32_t ui32CS, uint16_t ui16Cmd) +{ + uint32_t ui32Reg; + + // + // Sanity check parameters. + // + ASSERT(ui32Base == LCD0_BASE); + ASSERT((ui32CS == 0) || (ui32CS == 1)); + + // + // Determine the register to write based on the CS value supplied. + // + ui32Reg = ui32CS ? LCD_O_LIDDCS1ADDR : LCD_O_LIDDCS0ADDR; + + // + // Write the command/address to the register. + // + HWREG(ui32Base + ui32Reg) = ui16Cmd; +} + +//***************************************************************************** +// +//! Writes a data value to the display when the LCD controller is in LIDD mode. +//! +//! \param ui32Base specifies the LCD controller module base address. +//! \param ui32CS specifies the chip select to use. Valid values are 0 and 1. +//! \param ui16Data is the 16-bit data word to write. +//! +//! This function writes a 16-bit data word to the display when the LCD +//! controller is in LIDD mode. A data write occurs with the ALE signal +//! inactive. +//! +//! This function must not be called if the LIDD interface is currently +//! configured to expect DMA transactions. If DMA was previously used to +//! write to the panel, LCDIDDDMADisable() must be called before this function +//! can be used. +//! +//! \note CS1 is not available when operating in Sync MPU68 or Sync MPU80 +//! modes. +//! +//! \return None. +// +//***************************************************************************** +void +LCDIDDDataWrite(uint32_t ui32Base, uint32_t ui32CS, uint16_t ui16Data) +{ + uint32_t ui32Reg; + + // + // Sanity check parameters. + // + ASSERT(ui32Base == LCD0_BASE); + ASSERT((ui32CS == 0) || (ui32CS == 1)); + + // + // Determine the register to write based on the CS value supplied. + // + ui32Reg = ui32CS ? LCD_O_LIDDCS1DATA : LCD_O_LIDDCS0DATA; + + // + // Write the data value to the register. + // + HWREG(ui32Base + ui32Reg) = ui16Data; +} + +//***************************************************************************** +// +//! Writes data to a given display register when the LCD controller is in LIDD +//! mode. +//! +//! \param ui32Base specifies the LCD controller module base address. +//! \param ui32CS specifies the chip select to use. Valid values are 0 and 1. +//! \param ui16Addr is the address of the display register to write. +//! \param ui16Data is the data to write. +//! +//! This function writes a 16-bit data word to a register in the display when +//! the LCD controller is in LIDD mode and configured to use either the +//! Motorola (\b LIDD_CONFIG_SYNC_MPU68 or \b LIDD_CONFIG_ASYNC_MPU68) or +//! Intel (\b LIDD_CONFIG_SYNC_MPU80 or \b LIDD_CONFIG_ASYNC_MPU80) modes +//! that employ an external address latch. +//! +//! When configured in Hitachi mode (\b LIDD_CONFIG_ASYNC_HITACHI), this +//! function should not be used. In this case the functions +//! LCDIDDCommandWrite() and LCDIDDDataWrite() may be used to transfer +//! command and data bytes to the panel. +//! +//! This function must not be called if the LIDD interface is currently +//! configured to expect DMA transactions. If DMA was previously used to +//! write to the panel, LCDIDDDMADisable() must be called before this function +//! can be used. +//! +//! \note CS1 is not available when operating in Sync MPU68 or Sync MPU80 +//! modes. +//! +//! \return None. +// +//***************************************************************************** +void +LCDIDDIndexedWrite(uint32_t ui32Base, uint32_t ui32CS, uint16_t ui16Addr, + uint16_t ui16Data) +{ + uint32_t ui32Addr; + + // + // Sanity check parameters. + // + ASSERT(ui32Base == LCD0_BASE); + ASSERT((ui32CS == 0) || (ui32CS == 1)); + + // + // Determine the address register to write. + // + ui32Addr = ui32CS ? LCD_O_LIDDCS1ADDR : LCD_O_LIDDCS0ADDR; + + // + // Write the address. + // + HWREG(ui32Base + ui32Addr) = ui16Addr; + + // + // Determine the data register to write. + // + ui32Addr = ui32CS ? LCD_O_LIDDCS1DATA : LCD_O_LIDDCS0DATA; + + // + // Write the data. + // + HWREG(ui32Base + ui32Addr) = ui16Data; +} + +//***************************************************************************** +// +//! Reads a status word from the display when the LCD controller is in LIDD +//! mode. +//! +//! \param ui32Base specifies the LCD controller module base address. +//! \param ui32CS specifies the chip select to use. Valid values are 0 and 1. +//! +//! This function reads the 16-bit status word from the display when the LCD +//! controller is in LIDD mode. A status read occurs with the ALE signal +//! active. If the interface is configured in Hitachi mode (\b +//! LIDD_CONFIG_ASYNC_HITACHI), this operation corresponds to a command mode +//! read. +//! +//! This function must not be called if the LIDD interface is currently +//! configured to expect DMA transactions. If DMA was previously used to +//! write to the panel, LCDIDDDMADisable() must be called before this function +//! can be used. +//! +//! \note CS1 is not available when operating in Sync MPU68 or Sync MPU80 +//! modes. +//! +//! \return Returns the status word read from the display panel. +// +//***************************************************************************** +uint16_t +LCDIDDStatusRead(uint32_t ui32Base, uint32_t ui32CS) +{ + uint32_t ui32Reg; + + // + // Sanity check parameters. + // + ASSERT(ui32Base == LCD0_BASE); + ASSERT((ui32CS == 0) || (ui32CS == 1)); + + // + // Determine the register to read based on the CS value supplied. + // + ui32Reg = ui32CS ? LCD_O_LIDDCS1ADDR : LCD_O_LIDDCS0ADDR; + + // + // Read the relevant status register. + // + return((uint16_t)HWREG(ui32Base + ui32Reg)); +} + +//***************************************************************************** +// +//! Reads a data word from the display when the LCD controller is in LIDD +//! mode. +//! +//! \param ui32Base specifies the LCD controller module base address. +//! \param ui32CS specifies the chip select to use. Valid values are 0 and 1. +//! +//! This function reads the 16-bit data word from the display when the LCD +//! controller is in LIDD mode. A data read occurs with the ALE signal +//! inactive. +//! +//! This function must not be called if the LIDD interface is currently +//! configured to expect DMA transactions. If DMA was previously used to +//! write to the panel, LCDIDDDMADisable() must be called before this function +//! can be used. +//! +//! \note CS1 is not available when operating in Sync MPU68 or Sync MPU80 +//! modes. +//! +//! \return Returns the status word read from the display panel. +// +//***************************************************************************** +uint16_t +LCDIDDDataRead(uint32_t ui32Base, uint32_t ui32CS) +{ + uint32_t ui32Reg; + + // + // Sanity check parameters. + // + ASSERT(ui32Base == LCD0_BASE); + ASSERT((ui32CS == 0) || (ui32CS == 1)); + + // + // Determine the register to read based on the CS value supplied. + // + ui32Reg = ui32CS ? LCD_O_LIDDCS1DATA : LCD_O_LIDDCS0DATA; + + // + // Read the relevant data register. + // + return((uint16_t)HWREG(ui32Base + ui32Reg)); +} + +//***************************************************************************** +// +//! Reads a given display register when the LCD controller is in LIDD mode. +//! +//! \param ui32Base specifies the LCD controller module base address. +//! \param ui32CS specifies the chip select to use. Valid values are 0 and 1. +//! \param ui16Addr is the address of the display register to read. +//! +//! This function reads a 16-bit word from a register in the display when +//! the LCD controller is in LIDD mode and configured to use either the +//! Motorola (\b LIDD_CONFIG_SYNC_MPU68 or \b LIDD_CONFIG_ASYNC_MPU68) or +//! Intel (\b LIDD_CONFIG_SYNC_MPU80 or \b LIDD_CONFIG_ASYNC_MPU80) modes +//! that employ an external address latch. +//! +//! When configured in Hitachi mode (\b LIDD_CONFIG_ASYNC_HITACHI), this +//! function should not be used. In this case, the functions +//! LCDIDDStatusRead() and LCDIDDDataRead() may be used to read status +//! and data bytes from the panel. +//! +//! This function must not be called if the LIDD interface is currently +//! configured to expect DMA transactions. If DMA was previously used to +//! write to the panel, LCDIDDDMADisable() must be called before this function +//! can be used. +//! +//! \note CS1 is not available when operating in Sync MPU68 or Sync MPU80 +//! modes. +//! +//! \return None. +// +//***************************************************************************** +uint16_t +LCDIDDIndexedRead(uint32_t ui32Base, uint32_t ui32CS, uint16_t ui16Addr) +{ + uint32_t ui32Addr; + + // + // Sanity check parameters. + // + ASSERT(ui32Base == LCD0_BASE); + ASSERT((ui32CS == 0) || (ui32CS == 1)); + + // + // Determine the address register to write. + // + ui32Addr = ui32CS ? LCD_O_LIDDCS1ADDR : LCD_O_LIDDCS0ADDR; + + // + // Write the address. + // + HWREG(ui32Base + ui32Addr) = ui16Addr; + + // + // Determine the data register to read. + // + ui32Addr = ui32CS ? LCD_O_LIDDCS1DATA : LCD_O_LIDDCS0DATA; + + // + // Return the data read. + // + return((uint16_t)HWREG(ui32Base + ui32Addr)); +} + +//***************************************************************************** +// +//! Writes a block of data to the display using DMA when the LCD controller is +//! in LIDD mode. +//! +//! \param ui32Base specifies the LCD controller module base address. +//! \param ui32CS specifies the chip select to use. Valid values are 0 and 1. +//! \param pui32Data is the address of the first 16-bit word to write. This +//! address must be aligned on a 32-bit word boundary. +//! \param ui32Count is the number of 16-bit words to write. This value must +//! be a multiple of 2. +//! +//! This function writes a block of 16-bit data words to the display using +//! DMA. It is only valid when the LCD controller is in LIDD mode. +//! Completion of the DMA transfer is signaled by the \b +//! LCD_INT_DMA_DONE interrupt. +//! +//! This function enables DMA mode prior to starting the transfer. The +//! caller is responsible for ensuring that any earlier DMA transfer has +//! completed before initiating another transfer. +//! +//! During the time that DMA is enabled, none of the other LCD LIDD data +//! transfer functions may be called. When the DMA transfer is complete and +//! the application wishes to use the CPU to communicate with the display, +//! LCDIDDDMADisable() must be called to disable DMA access prior to calling +//! LCDIDDCommandWrite(), LCDIDDDataWrite(), LCDIDDStatusRead(), +//! LCDIDDIndexedWrite(), LCDIDDIndexedRead() or LCDIDDDataRead(). +//! +//! \note CS1 is not available when operating in Sync MPU68 or Sync MPU80 +//! modes. +//! +//! \return None. +// +//***************************************************************************** +void +LCDIDDDMAWrite(uint32_t ui32Base, uint32_t ui32CS, const uint32_t *pui32Data, + uint32_t ui32Count) +{ + // + // Sanity check parameters. + // + ASSERT(ui32Base == LCD0_BASE); + ASSERT((ui32CS == 0) || (ui32CS == 1)); + ASSERT(!((uint32_t)pui32Data & 3)); + ASSERT(!(ui32Count & 1)); + + // + // Make sure DMA is disabled so that enabling it triggers this new + // transfer. + // + HWREG(ui32Base + LCD_O_LIDDCTL) &= ~LCD_LIDDCTL_DMAEN; + + // + // Set up the transfer. Note that the ceiling register must contain the + // address of the last word which contains data we want transfered and NOT + // the first location after the data we want written. + // + HWREG(ui32Base + LCD_O_DMABAFB0) = (uint32_t)pui32Data; + HWREG(ui32Base + LCD_O_DMACAFB0) = ((uint32_t)pui32Data + + (ui32Count * 2) - 4); + + // + // Tell the controller which CS to use for the DMA transaction. + // + if(!ui32CS) + { + // + // Use CS0. + // + HWREG(ui32Base + LCD_O_LIDDCTL) &= ~LCD_LIDDCTL_DMACS; + } + else + { + // + // Use CS1. + // + HWREG(ui32Base + LCD_O_LIDDCTL) |= LCD_LIDDCTL_DMACS; + } + + // + // Enable the DMA engine and start the transaction. + // + HWREG(ui32Base + LCD_O_LIDDCTL) |= LCD_LIDDCTL_DMAEN; +} + +//***************************************************************************** +// +//! Sets the LCD controller interface timing when in raster mode. +//! +//! \param ui32Base specifies the LCD controller module base address. +//! \param ui32Config specifies properties of the raster interface and the +//! attached display panel. +//! \param ui8PalLoadDelay specifies the number of system clocks to wait +//! between each 16 halfword (16-bit) burst when loading the palette from +//! SRAM into the internal palette RAM of the controller. +//! +//! This function configures the basic operating mode of the raster interface +//! and specifies the type of panel that the controller is to drive. +//! +//! The \e ui32Config parameter must be defined as one of the following to +//! select the required target panel type and output pixel format: +//! +//! - \b RASTER_FMT_ACTIVE_24BPP_PACKED selects an active matrix display +//! and uses a packed 24-bit per pixel packet frame buffer where 4 pixels +//! are described within 3 consecutive 32-bit words. +//! - \b RASTER_FMT_ACTIVE_24BPP_UNPACKED selects an active matrix display +//! and uses an unpacked 24-bit per pixel packet frame buffer where each +//! 32-bit word contains a single pixel and 8 bits of padding. +//! - \b RASTER_FMT_ACTIVE_16BPP selects an active matrix display +//! and uses a 16-bit per pixel frame buffer with 2 pixels in each 32-bit +//! word. +//! - \b RASTER_FMT_ACTIVE_PALETTIZED_12BIT selects an active matrix display +//! and uses a 1, 2, 4 or 8bpp frame buffer with palette lookup. Output color +//! data is described in 12-bit format using bits 11:0 of the data bus. The +//! frame buffer pixel format is defined by the value passed in the \e ui32Type +//! parameter to LCDRasterPaletteSet(). +//! - \b RASTER_FMT_ACTIVE_PALETTIZED_16BIT selects an active matrix display +//! and uses a 1, 2, 4 or 8bpp frame buffer with palette lookup. Output color +//! data is described in 16-bit 5:6:5 format. The frame buffer pixel format is +//! defined by the value passed in the \e ui32Type parameter to +//! LCDRasterPaletteSet(). +//! - \b RASTER_FMT_PASSIVE_MONO_4PIX selects a monochrome, passive matrix +//! display that outputs 4 pixels on each pixel clock. +//! - \b RASTER_FMT_PASSIVE_MONO_8PIX selects a monochrome, passive matrix +//! display that outputs 8 pixels on each pixel clock. +//! - \b RASTER_FMT_PASSIVE_COLOR_12BIT selects a passive matrix display +//! and uses a 12bpp frame buffer. The palette is bypassed and 12-bit pixel +//! data is sent to the grayscaler for the display. +//! - \b RASTER_FMT_PASSIVE_COLOR_16BIT selects a passive matrix display +//! and uses a 16bpp frame buffer with pixels in 5:6:5 format. Only the 4 +//! most significant bits of each color component are sent to the grayscaler +//! for the display. +//! +//! Additionally, the following flags may be ORed into \e ui32Config: +//! +//! - \b RASTER_ACTVID_DURING_BLANK sets Actvid to toggle during vertical +//! blanking. +//! - \b RASTER_NIBBLE_MODE_ENABLED enables nibble mode. This parameter works +//! with \b RASTER_READ_ORDER_REVERSED to determine how 1, 2 and 4bpp pixels +//! are extracted from words read from the frame buffer. If specified, words +//! read from the frame buffer are byte swapped prior to individual pixels +//! being parsed from them. +//! - \b RASTER_LOAD_DATA_ONLY tells the controller to read only pixel data +//! from the frame buffer and to use the last palette read. No palette load +//! is performed. +//! - \b RASTER_LOAD_PALETTE_ONLY tells the controller to read only the palette +//! data from the frame buffer. +//! - \b RASTER_READ_ORDER_REVERSED when using 1, 2, 4 and 8bpp frame buffers, +//! this option reverses the order in which frame buffer words are parsed. +//! When this option is specified, the leftmost pixel in a word is taken from +//! the most significant bits. When absent, the leftmost pixel is parsed from +//! the least significant bits. +//! +//! If the LCD controller's raster engine is enabled when this function is +//! called, it is disabled as a result of the call. +//! +//! \return None. +// +//***************************************************************************** +void +LCDRasterConfigSet(uint32_t ui32Base, uint32_t ui32Config, + uint8_t ui8PalLoadDelay) +{ + // + // Sanity check parameters. + // + ASSERT(ui32Base == LCD0_BASE); + ASSERT(!(ui32Config & ~(RASTER_FMT_ACTIVE_24BPP_PACKED | + RASTER_FMT_ACTIVE_24BPP_UNPACKED | + RASTER_FMT_ACTIVE_PALETTIZED_12BIT | + RASTER_FMT_ACTIVE_PALETTIZED_16BIT | + RASTER_FMT_PASSIVE_MONO_4PIX | + RASTER_FMT_PASSIVE_MONO_8PIX | + RASTER_FMT_PASSIVE_PALETTIZED | + RASTER_FMT_PASSIVE_COLOR_12BIT | + RASTER_FMT_PASSIVE_COLOR_16BIT | + RASTER_ACTVID_DURING_BLANK | + RASTER_NIBBLE_MODE_ENABLED | + RASTER_LOAD_DATA_ONLY | + RASTER_LOAD_PALETTE_ONLY | + RASTER_READ_ORDER_REVERSED))); + + // + // Write the raster control register. + // + HWREG(ui32Base + LCD_O_RASTRCTL) = (ui32Config | + ((uint32_t)ui8PalLoadDelay << + LCD_RASTRCTL_REQDLY_S)); +} + +//***************************************************************************** +// +//! Sets the LCD controller interface timing when in raster mode. +//! +//! \param ui32Base specifies the LCD controller module base address. +//! \param pTiming points to a structure containing the desired timing +//! parameters. +//! +//! This function is used in raster mode to set the panel size and sync timing +//! parameters. +//! +//! For a definition of the timing parameters required, see the definition of +//! tLCDRasterTiming. +//! +//! \return None +// +//***************************************************************************** +void +LCDRasterTimingSet(uint32_t ui32Base, const tLCDRasterTiming *pTiming) +{ + uint32_t ui32T0, ui32T1, ui32T2; + + // + // Sanity check parameters. + // + ASSERT(ui32Base == LCD0_BASE); + ASSERT(pTiming); + ASSERT(!(pTiming->ui32Flags & ~(RASTER_TIMING_SYNCS_OPPOSITE_PIXCLK | + RASTER_TIMING_SYNCS_ON_FALLING_PIXCLK | + RASTER_TIMING_SYNCS_ON_RISING_PIXCLK | + RASTER_TIMING_ACTIVE_LOW_OE | + RASTER_TIMING_ACTIVE_LOW_PIXCLK | + RASTER_TIMING_ACTIVE_LOW_HSYNC | + RASTER_TIMING_ACTIVE_LOW_VSYNC))); + ASSERT(pTiming->ui16PanelWidth && (pTiming->ui16PanelWidth <= 2048) && + ((pTiming->ui16PanelWidth % 16) == 0)); + ASSERT(pTiming->ui16PanelHeight && (pTiming->ui16PanelHeight <= 2048)); + ASSERT(pTiming->ui16HFrontPorch && (pTiming->ui16HFrontPorch <= 1024)); + ASSERT(pTiming->ui16HBackPorch && (pTiming->ui16HBackPorch <= 1024)); + ASSERT(pTiming->ui16HSyncWidth && (pTiming->ui16HSyncWidth <= 1024)); + ASSERT(pTiming->ui8VSyncWidth && (pTiming->ui8VSyncWidth <= 64)); + + // + // Construct the values we need for the three raster timing registers. + // + ui32T0 = ((uint32_t)((pTiming->ui16HBackPorch - 1) & 0xFF) << + LCD_RASTRTIM0_HBP_S) | + ((uint32_t)((pTiming->ui16HFrontPorch - 1) & 0xFF) << + LCD_RASTRTIM0_HFP_S) | + ((uint32_t)((pTiming->ui16HSyncWidth - 1) & 0x3F) << + LCD_RASTRTIM0_HSW_S) | + (((uint32_t)((pTiming->ui16PanelWidth - 1) & 0x3F0) >> 4) << + LCD_RASTRTIM0_PPL_S) | + (((uint32_t)((pTiming->ui16PanelWidth - 1) & 0x400) >> 10) << + LCD_RASTRTIM0_MSBPPL_S); + ui32T1 = ((uint32_t)pTiming->ui8VBackPorch << LCD_RASTRTIM1_VBP_S) | + ((uint32_t)pTiming->ui8VFrontPorch << LCD_RASTRTIM1_VFP_S) | + ((uint32_t)((pTiming->ui8VSyncWidth - 1) & 0x3F) << + LCD_RASTRTIM1_VSW_S) | + ((uint32_t)(pTiming->ui16PanelHeight - 1) & 0x3FF) << + LCD_RASTRTIM1_LPP_S; + ui32T2 = pTiming->ui32Flags | + ((((pTiming->ui16HSyncWidth - 1) & 0x3C0) >> 6) << + LCD_RASTRTIM2_HSW_S) | + ((((pTiming->ui16PanelHeight - 1) & 0x400) >> 10) << + LCD_RASTRTIM2_MSBLPP_S) | + ((((pTiming->ui16HBackPorch - 1) & 0x300) >> 8) << + LCD_RASTRTIM2_MSBHBP_S) | + ((((pTiming->ui16HFrontPorch - 1) & 0x300) >> 8) << + LCD_RASTRTIM2_MSBHFP_S) | + (pTiming->ui8ACBiasLineCount << LCD_RASTRTIM2_ACBF_S); + + // + // Write the timing registers, taking care to preserve any existing value + // in the AC Bias interrupt field of RASTRTIM2. + // + HWREG(ui32Base + LCD_O_RASTRTIM0) = ui32T0; + HWREG(ui32Base + LCD_O_RASTRTIM1) = ui32T1; + HWREG(ui32Base + LCD_O_RASTRTIM2) = (HWREG(ui32Base + LCD_O_RASTRTIM2) & + LCD_RASTRTIM2_ACBI_M) | ui32T2; +} + +//***************************************************************************** +// +//! Sets the number of AC bias pin transitions per interrupt. +//! +//! \param ui32Base is the base address of the controller. +//! \param ui8Count is the number of AC bias pin transitions to count before +//! the AC bias count interrupt is asserted. Valid values are from 0 to 15. +//! +//! This function is used to set the number of AC bias transitions between +//! each AC bias count interrupt (\b LCD_INT_AC_BIAS_CNT). If \e ui8Count is +//! 0, no AC bias count interrupt is generated. +//! +//! \return None. +// +//***************************************************************************** +void +LCDRasterACBiasIntCountSet(uint32_t ui32Base, uint8_t ui8Count) +{ + uint32_t ui32Val; + + // + // Sanity check parameters. + // + ASSERT(ui32Base == LCD0_BASE); + ASSERT(ui8Count < 16); + + // + // Get the existing raster timing 2 register value and mask in the new + // AC Bias interrupt count. + // + ui32Val = HWREG(ui32Base + LCD_O_RASTRTIM2); + ui32Val &= ~LCD_RASTRTIM2_ACBI_M; + ui32Val |= ((ui8Count << LCD_RASTRTIM2_ACBI_S) & LCD_RASTRTIM2_ACBI_M); + + // + // Write the new value back to the register. + // + HWREG(ui32Base + LCD_O_RASTRTIM2) = ui32Val; +} + +//***************************************************************************** +// +//! Enables the raster output. +//! +//! \param ui32Base is the base address of the controller. +//! +//! This function enables the LCD controller raster output and starts +//! displaying the content of the current frame buffer on the attached panel. +//! Prior to enabling the raster output, LCDModeSet(), LCDRasterConfigSet(), +//! LCDDMAConfigSet(), LCDRasterTimingSet(), LCDRasterPaletteSet() and +//! LCDRasterFrameBufferSet() must have been called. +//! +//! \return None. +// +//***************************************************************************** +void +LCDRasterEnable(uint32_t ui32Base) +{ + // + // Sanity check parameters. + // + ASSERT(ui32Base == LCD0_BASE); + + // + // Reset the module prior to starting the raster. This is required to + // ensure correct operation of the raster engine. + // + LCDClockReset(ui32Base, LCD_CLOCK_MAIN); + + // + // Enable the raster engine. + // + HWREG(ui32Base + LCD_O_RASTRCTL) |= LCD_RASTRCTL_LCDEN; +} + +//***************************************************************************** +// +//! Determines whether or not the raster output is currently enabled. +//! +//! \param ui32Base is the base address of the controller. +//! +//! This function may be used to query whether or not the raster output is +//! currently enabled. +//! +//! \return Returns \b true if the raster is enabled or \b false if it is +//! disabled. +// +//***************************************************************************** +bool +LCDRasterEnabled(uint32_t ui32Base) +{ + // + // Sanity check parameters. + // + ASSERT(ui32Base == LCD0_BASE); + + // + // Return the current raster engine status. + // + return((HWREG(ui32Base + LCD_O_RASTRCTL) & LCD_RASTRCTL_LCDEN) ? + true : false); +} + +//***************************************************************************** +// +//! Disables the raster output. +//! +//! \param ui32Base is the base address of the controller. +//! +//! This function disables the LCD controller raster output and stops driving +//! the attached display. +//! +//! \note Once disabled, the raster engine continues to scan data until the +//! end of the current frame. If the display is to be re-enabled, wait until +//! after the final \b LCD_INT_RASTER_FRAME_DONE has been received, indicating +//! that the raster engine has stopped. +//! +//! \return None. +// +//***************************************************************************** +void +LCDRasterDisable(uint32_t ui32Base) +{ + // + // Sanity check parameters. + // + ASSERT(ui32Base == LCD0_BASE); + + // + // Disable the raster engine. + // + HWREG(ui32Base + LCD_O_RASTRCTL) &= ~LCD_RASTRCTL_LCDEN; +} + +//***************************************************************************** +// +//! Sets the position and size of the subpanel on the raster display. +//! +//! \param ui32Base is the base address of the controller. +//! \param ui32Flags may be either \b LCD_SUBPANEL_AT_TOP to show frame buffer +//! image data in the top portion of the display and default color in the +//! bottom portion, or \b LCD_SUBPANEL_AT_BOTTOM to show image data at the +//! bottom of the display and default color at the top. +//! \param ui32BottomLines defines the number of lines comprising the bottom +//! portion of the display. If \b LCD_SUBPANEL_AT_TOP is set in \e ui32Flags, +//! these lines contain the default pixel color when the subpanel is +//! enabled, otherwise they contain image data. +//! \param ui32DefaultPixel is the 24-bit RGB color to show in the portion of +//! the display not configured to show image data. +//! +//! The LCD controller provides a feature that allows a portion of the display +//! to be filled with a default color rather than image data from the frame +//! buffer. This feature reduces SRAM bandwidth requirements because no data +//! is fetched for lines containing the default color. This feature is only +//! available when the LCD controller is in raster mode and configured to drive +//! an active matrix display. +//! +//! The subpanel area containing image data from the frame buffer may be +//! positioned either at the top or bottom of the display as controlled by +//! the value of \e ui32Flags. The height of the bottom portion of the display +//! is defined by \e ui32BottomLines. +//! +//! When a subpanel is configured, the application must also reconfigure the +//! frame buffer to ensure that it contains the correct number of lines for +//! the subpanel size in use. This configuration can be achieved by calling +//! LCDRasterFrameBufferSet() with the \e ui32NumBytes parameter set +//! appropriately to describe the required number of active video lines in +//! the subpanel area. +//! +//! The subpanel display mode is not enabled using this function. To enable +//! the subpanel once it has been configured, call LCDRasterSubPanelEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +LCDRasterSubPanelConfigSet(uint32_t ui32Base, uint32_t ui32Flags, + uint32_t ui32BottomLines, uint32_t ui32DefaultPixel) +{ + // + // Sanity check parameters. + // + ASSERT(ui32Base == LCD0_BASE); + ASSERT((ui32Flags == LCD_SUBPANEL_AT_TOP) || + (ui32Flags == LCD_SUBPANEL_AT_BOTTOM)); + ASSERT(ui32BottomLines && (ui32BottomLines <= 2048)); + + // + // Adjust the line count into the 0-2047 range. + // + ui32BottomLines--; + + // + // Set the first subpanel configuration register, taking care to leave the + // subpanel enabled if it already was. + // + HWREG(ui32Base + LCD_O_RASTRSUBP1) = (HWREG(ui32Base + LCD_O_RASTRSUBP1) & + LCD_RASTRSUBP1_SPEN) | ui32Flags | + ((ui32DefaultPixel & 0xFFFF) << + LCD_RASTRSUBP1_DPDLSB_S) | + ((ui32BottomLines << + LCD_RASTRSUBP1_LPPT_S) & + LCD_RASTRSUBP1_LPPT_M); + + // + // Set the second subpanel configuration register. + // + HWREG(ui32Base + LCD_O_RASTRSUBP2) = + ((ui32DefaultPixel >> 16) & LCD_RASTRSUBP2_DPDMSB_M) | + (((ui32BottomLines >> LCD_RASTRSUBP1_LPPT_S) & 1) << 8); +} + +//***************************************************************************** +// +//! Enables subpanel display mode. +//! +//! \param ui32Base is the base address of the controller. +//! +//! This function enables subpanel display mode and displays a default color +//! rather than image data in the number of lines and at the position specified +//! by a previous call to LCDRasterSubPanelConfigSet(). Prior to calling +//! LCDRasterSubPanelEnable(), the frame buffer should have been reconfigured +//! to match the desired subpanel size using a call to +//! LCDRasterFrameBufferSet(). +//! +//! Subpanel display is only possible when the LCD controller is in raster +//! mode and is configured to drive an active matrix display. +//! +//! \return None. +// +//***************************************************************************** +void +LCDRasterSubPanelEnable(uint32_t ui32Base) +{ + // + // Sanity check parameters. + // + ASSERT(ui32Base == LCD0_BASE); + + // + // Enable the subpanel. + // + HWREG(ui32Base + LCD_O_RASTRSUBP1) |= LCD_RASTRSUBP1_SPEN; +} + +//***************************************************************************** +// +//! Disables subpanel display mode. +//! +//! \param ui32Base is the base address of the controller. +//! +//! This function disables subpanel display mode and reverts to showing the +//! entire frame buffer image on the display. After the subpanel is disabled, +//! the frame buffer size must be reconfigured to match the full dimensions of +//! the display area by calling LCDRasterFrameBufferSet() with an appropriate +//! value for the \e ui32NumBytes parameter. +//! +//! \return None. +// +//***************************************************************************** +void +LCDRasterSubPanelDisable(uint32_t ui32Base) +{ + // + // Sanity check parameters. + // + ASSERT(ui32Base == LCD0_BASE); + + // + // Disable the subpanel. + // + HWREG(ui32Base + LCD_O_RASTRSUBP1) &= ~LCD_RASTRSUBP1_SPEN; +} + +//***************************************************************************** +// +//! Configures the LCD controller's internal DMA engine. +//! +//! \param ui32Base is the base address of the controller. +//! \param ui32Config provides flags defining the desired DMA parameters. +//! +//! This function is used to configure the DMA engine within the LCD +//! controller. This engine is responsible for performing bulk data transfers +//! to the display when in LIDD mode or for transferring palette and pixel data +//! from SRAM to the display panel when in raster mode. +//! +//! The \e ui32Config parameter is a logical OR of various flags. It must +//! contain one value from each of the following groups. +//! +//! The first group of flags set the number of words that have to be in the +//! FIFO before it signals that it is ready: +//! +//! - \b LCD_DMA_FIFORDY_8_WORDS +//! - \b LCD_DMA_FIFORDY_16_WORDS +//! - \b LCD_DMA_FIFORDY_32_WORDS +//! - \b LCD_DMA_FIFORDY_64_WORDS +//! - \b LCD_DMA_FIFORDY_128_WORDS +//! - \b LCD_DMA_FIFORDY_256_WORDS +//! - \b LCD_DMA_FIFORDY_512_WORDS +//! +//! The second group of flags set the number of 32-bit words in each DMA burst +//! transfer: +//! +//! - \b LCD_DMA_BURST_1 +//! - \b LCD_DMA_BURST_2 +//! - \b LCD_DMA_BURST_4 +//! - \b LCD_DMA_BURST_8 +//! - \b LCD_DMA_BURST_16 +//! +//! The final group of flags set internal byte lane controls and allow byte +//! swapping within the DMA engine. The label represents the output byte order +//! for an input 32-bit word ordered ``0123''. +//! +//! - \b LCD_DMA_BYTE_ORDER_0123 +//! - \b LCD_DMA_BYTE_ORDER_1023 +//! - \b LCD_DMA_BYTE_ORDER_3210 +//! - \b LCD_DMA_BYTE_ORDER_2301 +//! +//! Additionally, \b LCD_DMA_PING_PONG may be specified. This flag configures +//! the controller to operate in double-buffered mode. When data is scanned +//! out from the first frame buffer, the DMA engine immediately moves to +//! the second frame buffer and scans from there before moving back to the +//! first. If this flag is clear, the DMA engine uses a single frame buffer, +//! restarting the scan from the beginning of the buffer each time it completes +//! a frame. +//! +//! \note DMA burst size \b LCD_DMA_BURST_16 should be set when using frame +//! buffers in external, EPI-connected memory. Using a smaller burst size in +//! this case is likely to result in occasional FIFO underflows and associated +//! display glitches. +//! +//! \return None. +// +//***************************************************************************** +void +LCDDMAConfigSet(uint32_t ui32Base, uint32_t ui32Config) +{ + // + // Sanity check parameters. + // + ASSERT(ui32Base == LCD0_BASE); + ASSERT(!(ui32Config & ~(LCD_DMACTL_FIFORDY_M | LCD_DMACTL_BURSTSZ_M | + LCD_DMACTL_BYTESWAP | LCD_DMACTL_BIGDEND | + LCD_DMACTL_FMODE))); + + // + // Write the DMA control register. + // + HWREG(ui32Base + LCD_O_DMACTL) = ui32Config; +} + +//***************************************************************************** +// +//! Initializes the color palette in a frame buffer. +//! +//! \param ui32Base is the base address of the controller. +//! \param ui32Type specifies the type of pixel data to be held in the frame +//! buffer and also the format of the source color values passed. +//! \param pui32Addr points to the start of the frame buffer into which the +//! palette information is to be written. +//! \param pui32SrcColors points to the first color value that is to be +//! written into the frame buffer palette. +//! \param ui32Start specifies the index of the first color in the palette +//! to update. +//! \param ui32Count specifies the number of source colors to be copied into +//! the frame buffer palette. +//! +//! This function is used to initialize the color palette stored at the +//! beginning of a frame buffer. It writes the relevant pixel type into the +//! first entry of the frame buffer and copies the requested number of colors +//! from a source buffer into the palette starting at the required index, +//! optionally converting them from 24-bit color format into the 12-bit format +//! used by the LCD controller. +//! +//! \e ui32Type must be set to one of the following values to indicate the +//! type of frame buffer for which the palette is being initialized: +//! +//! - \b LCD_PALETTE_TYPE_1BPP indicates a 1 bit per pixel +//! (monochrome) frame buffer. This format requires a 2 entry palette. +//! - \b LCD_PALETTE_TYPE_2BPP indicates a 2 bit per pixel frame +//! buffer. This format requires a 4 entry palette. +//! - \b LCD_PALETTE_TYPE_4BPP indicates a 4 bit per pixel frame +//! buffer. This format requires a 4 entry palette. +//! - \b LCD_PALETTE_TYPE_8BPP indicates an 8 bit per pixel frame +//! buffer. This format requires a 256 entry palette. +//! - \b LCD_PALETTE_TYPE_DIRECT indicates a direct color (12, 16 or +//! 24 bit per pixel). The color palette is not used in these modes, but the +//! frame buffer type must still be initialized to ensure that the hardware +//! uses the correct pixel type. When this value is used, the format of the +//! pixels in the frame buffer is defined by the \e ui32Config parameter +//! previously passed to LCDRasterConfigSet(). +//! +//! Optionally, the \b LCD_PALETTE_SRC_24BIT flag may be ORed into \e ui32Type +//! to indicate that the supplied colors in the \e pui32SrcColors array are in +//! the 24-bit format as used by the TivaWare Graphics Library with one color +//! stored in each 32-bit word. In this case, the colors read from the source +//! array are converted to the 12-bit format used by the LCD controller before +//! being written into the frame buffer palette. +//! +//! If \b LCD_PALETTE_SRC_24BIT is not present, it is assumed that the +//! \e pui32SrcColors array contains 12-bit colors in the format required by +//! the LCD controller with 2 colors stored in each 32-bit word. In this case, +//! the values are copied directly into the frame buffer palette without any +//! reformatting. +//! +//! \return None. +// +//***************************************************************************** +void +LCDRasterPaletteSet(uint32_t ui32Base, uint32_t ui32Type, uint32_t *pui32Addr, + const uint32_t *pui32SrcColors, uint32_t ui32Start, + uint32_t ui32Count) +{ + uint16_t *pui16Pal; + uint16_t *pui16Src; + uint32_t ui32Loop; + + // + // Sanity check parameters. + // + ASSERT(ui32Base == LCD0_BASE); + ASSERT(ui32Start < 256); + ASSERT((ui32Start + ui32Count) <= 256); + ASSERT(pui32Addr); + ASSERT((pui32SrcColors) || (ui32Count == 0)); + ASSERT(!(ui32Type & ~(LCD_PALETTE_SRC_24BIT | LCD_PALETTE_TYPE_DIRECT | + LCD_PALETTE_TYPE_8BPP | LCD_PALETTE_TYPE_4BPP | + LCD_PALETTE_TYPE_2BPP | LCD_PALETTE_TYPE_1BPP))); + + // + // Get a pointer to the start of the palette. + // + pui16Pal = (uint16_t *)pui32Addr; + + // + // Are we converting the palette color format? + // + if(ui32Type & LCD_PALETTE_SRC_24BIT) + { + // + // Yes - loop through each of the supplied 24-bit colors converting + // and storing each. + // + ui32Loop = 0; + while(ui32Count) + { + pui16Pal[ui32Start + ui32Loop] = + PAL_FROM_RGB(pui32SrcColors[ui32Loop]); + ui32Loop++; + ui32Count--; + } + } + else + { + // + // No - loop through the supplied 12-bit colors storing each. + // + + pui16Src = (uint16_t *)pui32SrcColors; + while(ui32Count) + { + pui16Pal[ui32Start] = pui16Src[ui32Start]; + ui32Start++; + ui32Count--; + } + } + + // + // Write the pixel type into the first palette entry. + // + pui16Pal[0] &= ~(LCD_PALETTE_TYPE_8BPP | LCD_PALETTE_TYPE_DIRECT); + pui16Pal[0] |= (ui32Type & ~LCD_PALETTE_SRC_24BIT); +} + +//***************************************************************************** +// +//! Sets the LCD controller frame buffer start address and size in raster mode. +//! +//! \param ui32Base is the base address of the controller. +//! \param ui8Buffer specifies which frame buffer to configure. Valid values +//! are 0 and 1. +//! \param pui32Addr points to the first byte of the frame buffer. This +//! pointer must be aligned on a 32-bit (word) boundary. +//! \param ui32NumBytes specifies the size of the frame buffer in bytes. This +//! value must be a multiple of 4. +//! +//! This function is used to configure the position and size of one of the +//! two supported frame buffers while in raster mode. The second frame buffer +//! (configured when ui8Buffer is set to 1) is only used if the controller +//! is set to operate in ping-pong mode (by specifying the \b LCD_DMA_PING_PONG +//! configuration flag on a call to LCDDMAConfigSet()). +//! +//! The format of the frame buffer depends on the image type in use and +//! the current raster configuration settings. If \b RASTER_LOAD_DATA_ONLY +//! was specified in a previous call to LCDRasterConfigSet(), the frame buffer +//! contains only packed pixel data in the required bit depth and format. +//! In other cases, the frame buffer comprises a palette of either 8 or 128 +//! 32-bit words followed by the packed pixel data. The palette size is 8 +//! words (16 16-bit entries) for all pixel formats other than 8bpp which +//! uses a palette of 128 words (256 16-bit entries). Note that the 8 word +//! palette is still present even for 12, 16 and 24-bit formats, which do not +//! use the lookup table. +//! +//! The frame buffer size, specified using the \e ui32NumBytes parameter, must +//! be the palette size (if any) plus the size of the image bitmap required +//! for the currently configured display resolution. +//! +//! \e ui32NumBytes = (Palette Size) + ((Width * Height) * BPP) / 8) +//! +//! If \b RASTER_LOAD_DATA_ONLY is not specified, frame buffers passed to this +//! function must be initialized using a call to LCDRasterPaletteSet() prior to +//! enabling the raster output. If this is not done, the pixel format +//! identifier and color table required by the hardware is not present +//! and the results are unpredictable. +//! +//! \return None. +//***************************************************************************** +void +LCDRasterFrameBufferSet(uint32_t ui32Base, uint8_t ui8Buffer, + uint32_t *pui32Addr, uint32_t ui32NumBytes) +{ + // + // Sanity check parameters. + // + ASSERT(ui32Base == LCD0_BASE); + ASSERT(!((uint32_t)pui32Addr & 3)); + ASSERT(!(ui32NumBytes & 3)); + ASSERT(ui8Buffer < 2); + + // + // Are we setting the values for frame buffer 0? + // + if(!ui8Buffer) + { + // + // Yes - set the registers for frame buffer 0. + // + HWREG(ui32Base + LCD_O_DMABAFB0) = (uint32_t)pui32Addr; + HWREG(ui32Base + LCD_O_DMACAFB0) = (uint32_t)pui32Addr + + ui32NumBytes - 4; + } + else + { + // + // No - set the registers for frame buffer 1. + // + HWREG(ui32Base + LCD_O_DMABAFB1) = (uint32_t)pui32Addr; + HWREG(ui32Base + LCD_O_DMACAFB1) = (uint32_t)pui32Addr + + ui32NumBytes - 4; + } +} + +//***************************************************************************** +// +//! Enables individual LCD controller interrupt sources. +//! +//! \param ui32Base is the base address of the controller. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated LCD controller interrupt sources. +//! Only the sources that are enabled can be reflected to the processor +//! interrupt; disabled sources have no effect on the processor. +//! +//! The \e ui32IntFlags parameter is the logical OR of any of the following: +//! +//! - \b LCD_INT_DMA_DONE - indicates that a LIDD DMA transfer is complete. +//! - \b LCD_INT_RASTER_FRAME_DONE - indicates that a raster-mode frame is +//! complete. +//! - \b LCD_INT_SYNC_LOST - indicates that frame synchronization was lost. +//! - \b LCD_INT_AC_BIAS_CNT - indicates that that AC bias transition counter +//! has decremented to zero and is is valid for passive matrix panels only. +//! The counter, set by a call to LCDRasterACBiasIntCountSet(), is reloaded +//! but remains disabled until this interrupt is cleared. +//! - \b LCD_INT_UNDERFLOW - indicates that a data underflow occurred. The +//! internal FIFO was empty when the output logic attempted to read data to +//! send to the display. +//! - \b LCD_INT_PAL_LOAD - indicates that the color palette has been loaded. +//! - \b LCD_INT_EOF0 - indicates that the raw End-of-Frame 0 has been +//! signaled. +//! - \b LCD_INT_EOF2 - indicates that the raw End-of-Frame 1 has been +//! signaled. +//! +//! \return None. +// +//***************************************************************************** +void +LCDIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + ASSERT(ui32Base == LCD0_BASE); + ASSERT(!(ui32IntFlags & ~(LCD_INT_DMA_DONE | LCD_INT_SYNC_LOST | + LCD_INT_AC_BIAS_CNT | LCD_INT_UNDERFLOW | + LCD_INT_PAL_LOAD | LCD_INT_EOF0 | LCD_INT_EOF1 | + LCD_INT_RASTER_FRAME_DONE))); + + // + // Enable the interrupt sources by setting the appropriate bits in the + // mask register. + // + HWREG(ui32Base + LCD_O_IM) = ui32IntFlags; +} + +//***************************************************************************** +// +//! Disables individual LCD controller interrupt sources. +//! +//! \param ui32Base is the base address of the controller. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be +//! disabled. +//! +//! This function disables the indicated LCD controller interrupt sources. +//! Only the sources that are enabled can be reflected to the processor +//! interrupt; disabled sources have no effect on the processor. +//! +//! The \e ui32IntFlags parameter is the logical OR of any of the following: +//! +//! - \b LCD_INT_DMA_DONE - indicates that a LIDD DMA transfer is complete. +//! - \b LCD_INT_RASTER_FRAME_DONE - indicates that a raster-mode frame is +//! complete. +//! - \b LCD_INT_SYNC_LOST - indicates that frame synchronization was lost. +//! - \b LCD_INT_AC_BIAS_CNT - indicates that that AC bias transition counter +//! has decremented to zero and is is valid for passive matrix panels only. +//! The counter, set by a call to LCDRasterACBiasIntCountSet(), is reloaded +//! but remains disabled until this interrupt is cleared. +//! - \b LCD_INT_UNDERFLOW - indicates that a data underflow occurred. The +//! internal FIFO was empty when the output logic attempted to read data to +//! send to the display. +//! - \b LCD_INT_PAL_LOAD - indicates that the color palette has been loaded. +//! - \b LCD_INT_EOF0 - indicates that the raw End-of-Frame 0 has been +//! signaled. +//! - \b LCD_INT_EOF2 - indicates that the raw End-of-Frame 1 has been +//! signaled. +//! +//! \return None. +// +//***************************************************************************** +void +LCDIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + ASSERT(ui32Base == LCD0_BASE); + ASSERT(!(ui32IntFlags & ~(LCD_INT_DMA_DONE | LCD_INT_SYNC_LOST | + LCD_INT_AC_BIAS_CNT | LCD_INT_UNDERFLOW | + LCD_INT_PAL_LOAD | LCD_INT_EOF0 | LCD_INT_EOF1 | + LCD_INT_RASTER_FRAME_DONE))); + + // + // Disable the interrupt sources by clearing the appropriate bits in the + // mask register. + // + HWREG(ui32Base + LCD_O_IENC) = ui32IntFlags; +} + +//***************************************************************************** +// +//! Gets the current LCD controller interrupt status. +//! +//! \param ui32Base is the base address of the controller. +//! \param bMasked is false if the raw interrupt status is required and true +//! if the masked interrupt status is required. +//! +//! This function returns the interrupt status for the LCD controller. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return Returns the current interrupt status as the logical OR of any of +//! the following: +//! +//! - \b LCD_INT_DMA_DONE - indicates that a LIDD DMA transfer is complete. +//! - \b LCD_INT_RASTER_FRAME_DONE - indicates that a raster-mode frame is +//! complete. +//! - \b LCD_INT_SYNC_LOST - indicates that frame synchronization was lost. +//! - \b LCD_INT_AC_BIAS_CNT - indicates that that AC bias transition counter +//! has decremented to zero and is is valid for passive matrix panels only. +//! The counter, set by a call to LCDRasterACBiasIntCountSet(), is reloaded +//! but remains disabled until this interrupt is cleared. +//! - \b LCD_INT_UNDERFLOW - indicates that a data underflow occurred. The +//! internal FIFO was empty when the output logic attempted to read data to +//! send to the display. +//! - \b LCD_INT_PAL_LOAD - indicates that the color palette has been loaded. +//! - \b LCD_INT_EOF0 - indicates that the raw End-of-Frame 0 has been +//! signaled. +//! - \b LCD_INT_EOF2 - indicates that the raw End-of-Frame 1 has been +//! signaled. +// +//***************************************************************************** +uint32_t +LCDIntStatus(uint32_t ui32Base, bool bMasked) +{ + ASSERT(ui32Base == LCD0_BASE); + + // + // Were we asked for the masked or raw interrupt status? + // + if(bMasked) + { + // + // Return the masked interrupt status. + // + return(HWREG(ui32Base + LCD_O_MISCLR)); + } + else + { + // + // Return the raw interrupts status. + // + return(HWREG(ui32Base + LCD_O_RISSET)); + } +} + +//***************************************************************************** +// +//! Clears LCD controller interrupt sources. +//! +//! \param ui32Base is the base address of the controller. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified LCD controller interrupt sources are cleared so that they no +//! longer assert. This function must be called in the interrupt handler to +//! keep the interrupt from being triggered again immediately upon exit. +//! +//! The \e ui32IntFlags parameter is the logical OR of any of the following: +//! +//! - \b LCD_INT_DMA_DONE - indicates that a LIDD DMA transfer is complete. +//! - \b LCD_INT_RASTER_FRAME_DONE - indicates that a raster-mode frame is +//! complete. +//! - \b LCD_INT_SYNC_LOST - indicates that frame synchronization was lost. +//! - \b LCD_INT_AC_BIAS_CNT - indicates that that AC bias transition counter +//! has decremented to zero and is is valid for passive matrix panels only. +//! The counter, set by a call to LCDRasterACBiasIntCountSet(), is reloaded +//! but remains disabled until this interrupt is cleared. +//! - \b LCD_INT_UNDERFLOW - indicates that a data underflow occurred. The +//! internal FIFO was empty when the output logic attempted to read data to +//! send to the display. +//! - \b LCD_INT_PAL_LOAD - indicates that the color palette has been loaded. +//! - \b LCD_INT_EOF0 - indicates that the raw End-of-Frame 0 has been +//! signaled. +//! - \b LCD_INT_EOF2 - indicates that the raw End-of-Frame 1 has been +//! signaled. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +LCDIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + ASSERT(ui32Base == LCD0_BASE); + ASSERT(!(ui32IntFlags & ~(LCD_INT_DMA_DONE | LCD_INT_SYNC_LOST | + LCD_INT_AC_BIAS_CNT | LCD_INT_UNDERFLOW | + LCD_INT_PAL_LOAD | LCD_INT_EOF0 | LCD_INT_EOF1 | + LCD_INT_RASTER_FRAME_DONE))); + + // + // Clear the requested interrupts. + // + HWREG(ui32Base + LCD_O_MISCLR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the LCD controller module. +//! +//! \param ui32Base specifies the LCD controller module base address. +//! \param pfnHandler is a pointer to the function to be called when the LCD +//! controller interrupt occurs. +//! +//! This function registers the handler to be called when the LCD controller +//! module interrupt occurs. +//! +//! \note This function need not be called if the appropriate interrupt vector +//! is statically linked into the vector table in the application startup code. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +LCDIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == LCD0_BASE); + ASSERT(pfnHandler); + + // + // Register the interrupt handler. + // + IntRegister(INT_LCD0_TM4C129, pfnHandler); + + // + // Enable the interrupt in the interrupt controller. + // + IntEnable(INT_LCD0_TM4C129); +} + +//***************************************************************************** +// +//! Unregisters the interrupt handler for the LCD controller module. +//! +//! \param ui32Base specifies the LCD controller module base address. +//! +//! This function unregisters the interrupt handler and disables the global LCD +//! controller interrupt in the interrupt controller. +//! +//! \note This function need not be called if the appropriate interrupt vector +//! is statically linked into the vector table in the application startup code. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +LCDIntUnregister(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == LCD0_BASE); + + // + // Disable the interrupt in the interrupt controller. + // + IntDisable(INT_LCD0_TM4C129); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_LCD0_TM4C129); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/mpu.c b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/mpu.c new file mode 100644 index 0000000000000000000000000000000000000000..4d01f1b403cd87d6c2c2932946d2fe3fafea3c6f --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/mpu.c @@ -0,0 +1,459 @@ +//***************************************************************************** +// +// mpu.c - Driver for the Cortex-M3 memory protection unit (MPU). +// +// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup mpu_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_ints.h" +#include "inc/hw_nvic.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/mpu.h" + +//***************************************************************************** +// +//! Enables and configures the MPU for use. +//! +//! \param ui32MPUConfig is the logical OR of the possible configurations. +//! +//! This function enables the Cortex-M memory protection unit. It also +//! configures the default behavior when in privileged mode and while handling +//! a hard fault or NMI. Prior to enabling the MPU, at least one region must +//! be set by calling MPURegionSet() or else by enabling the default region for +//! privileged mode by passing the \b MPU_CONFIG_PRIV_DEFAULT flag to +//! MPUEnable(). Once the MPU is enabled, a memory management fault is +//! generated for memory access violations. +//! +//! The \e ui32MPUConfig parameter should be the logical OR of any of the +//! following: +//! +//! - \b MPU_CONFIG_PRIV_DEFAULT enables the default memory map when in +//! privileged mode and when no other regions are defined. If this option +//! is not enabled, then there must be at least one valid region already +//! defined when the MPU is enabled. +//! - \b MPU_CONFIG_HARDFLT_NMI enables the MPU while in a hard fault or NMI +//! exception handler. If this option is not enabled, then the MPU is +//! disabled while in one of these exception handlers and the default +//! memory map is applied. +//! - \b MPU_CONFIG_NONE chooses none of the above options. In this case, +//! no default memory map is provided in privileged mode, and the MPU is not +//! enabled in the fault handlers. +//! +//! \return None. +// +//***************************************************************************** +void +MPUEnable(uint32_t ui32MPUConfig) +{ + // + // Check the arguments. + // + ASSERT(!(ui32MPUConfig & ~(MPU_CONFIG_PRIV_DEFAULT | + MPU_CONFIG_HARDFLT_NMI))); + + // + // Set the MPU control bits according to the flags passed by the user, + // and also set the enable bit. + // + HWREG(NVIC_MPU_CTRL) = ui32MPUConfig | NVIC_MPU_CTRL_ENABLE; +} + +//***************************************************************************** +// +//! Disables the MPU for use. +//! +//! This function disables the Cortex-M memory protection unit. When the +//! MPU is disabled, the default memory map is used and memory management +//! faults are not generated. +//! +//! \return None. +// +//***************************************************************************** +void +MPUDisable(void) +{ + // + // Turn off the MPU enable bit. + // + HWREG(NVIC_MPU_CTRL) &= ~NVIC_MPU_CTRL_ENABLE; +} + +//***************************************************************************** +// +//! Gets the count of regions supported by the MPU. +//! +//! This function is used to get the total number of regions that are supported +//! by the MPU, including regions that are already programmed. +//! +//! \return The number of memory protection regions that are available +//! for programming using MPURegionSet(). +// +//***************************************************************************** +uint32_t +MPURegionCountGet(void) +{ + // + // Read the DREGION field of the MPU type register and mask off + // the bits of interest to get the count of regions. + // + return((HWREG(NVIC_MPU_TYPE) & NVIC_MPU_TYPE_DREGION_M) >> + NVIC_MPU_TYPE_DREGION_S); +} + +//***************************************************************************** +// +//! Enables a specific region. +//! +//! \param ui32Region is the region number to enable. +//! +//! This function is used to enable a memory protection region. The region +//! should already be configured with the MPURegionSet() function. Once +//! enabled, the memory protection rules of the region are applied and access +//! violations cause a memory management fault. +//! +//! \return None. +// +//***************************************************************************** +void +MPURegionEnable(uint32_t ui32Region) +{ + // + // Check the arguments. + // + ASSERT(ui32Region < 8); + + // + // Select the region to modify. + // + HWREG(NVIC_MPU_NUMBER) = ui32Region; + + // + // Modify the enable bit in the region attributes. + // + HWREG(NVIC_MPU_ATTR) |= NVIC_MPU_ATTR_ENABLE; +} + +//***************************************************************************** +// +//! Disables a specific region. +//! +//! \param ui32Region is the region number to disable. +//! +//! This function is used to disable a previously enabled memory protection +//! region. The region remains configured if it is not overwritten with +//! another call to MPURegionSet(), and can be enabled again by calling +//! MPURegionEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +MPURegionDisable(uint32_t ui32Region) +{ + // + // Check the arguments. + // + ASSERT(ui32Region < 8); + + // + // Select the region to modify. + // + HWREG(NVIC_MPU_NUMBER) = ui32Region; + + // + // Modify the enable bit in the region attributes. + // + HWREG(NVIC_MPU_ATTR) &= ~NVIC_MPU_ATTR_ENABLE; +} + +//***************************************************************************** +// +//! Sets up the access rules for a specific region. +//! +//! \param ui32Region is the region number to set up. +//! \param ui32Addr is the base address of the region. It must be aligned +//! according to the size of the region specified in ui32Flags. +//! \param ui32Flags is a set of flags to define the attributes of the region. +//! +//! This function sets up the protection rules for a region. The region has +//! a base address and a set of attributes including the size. The base +//! address parameter, \e ui32Addr, must be aligned according to the size, and +//! the size must be a power of 2. +//! +//! The \e ui32Flags parameter is the logical OR of all of the attributes +//! of the region. It is a combination of choices for region size, +//! execute permission, read/write permissions, disabled sub-regions, +//! and a flag to determine if the region is enabled. +//! +//! The size flag determines the size of a region and must be one of the +//! following: +//! +//! - \b MPU_RGN_SIZE_32B +//! - \b MPU_RGN_SIZE_64B +//! - \b MPU_RGN_SIZE_128B +//! - \b MPU_RGN_SIZE_256B +//! - \b MPU_RGN_SIZE_512B +//! - \b MPU_RGN_SIZE_1K +//! - \b MPU_RGN_SIZE_2K +//! - \b MPU_RGN_SIZE_4K +//! - \b MPU_RGN_SIZE_8K +//! - \b MPU_RGN_SIZE_16K +//! - \b MPU_RGN_SIZE_32K +//! - \b MPU_RGN_SIZE_64K +//! - \b MPU_RGN_SIZE_128K +//! - \b MPU_RGN_SIZE_256K +//! - \b MPU_RGN_SIZE_512K +//! - \b MPU_RGN_SIZE_1M +//! - \b MPU_RGN_SIZE_2M +//! - \b MPU_RGN_SIZE_4M +//! - \b MPU_RGN_SIZE_8M +//! - \b MPU_RGN_SIZE_16M +//! - \b MPU_RGN_SIZE_32M +//! - \b MPU_RGN_SIZE_64M +//! - \b MPU_RGN_SIZE_128M +//! - \b MPU_RGN_SIZE_256M +//! - \b MPU_RGN_SIZE_512M +//! - \b MPU_RGN_SIZE_1G +//! - \b MPU_RGN_SIZE_2G +//! - \b MPU_RGN_SIZE_4G +//! +//! The execute permission flag must be one of the following: +//! +//! - \b MPU_RGN_PERM_EXEC enables the region for execution of code +//! - \b MPU_RGN_PERM_NOEXEC disables the region for execution of code +//! +//! The read/write access permissions are applied separately for the +//! privileged and user modes. The read/write access flags must be one +//! of the following: +//! +//! - \b MPU_RGN_PERM_PRV_NO_USR_NO - no access in privileged or user mode +//! - \b MPU_RGN_PERM_PRV_RW_USR_NO - privileged read/write, user no access +//! - \b MPU_RGN_PERM_PRV_RW_USR_RO - privileged read/write, user read-only +//! - \b MPU_RGN_PERM_PRV_RW_USR_RW - privileged read/write, user read/write +//! - \b MPU_RGN_PERM_PRV_RO_USR_NO - privileged read-only, user no access +//! - \b MPU_RGN_PERM_PRV_RO_USR_RO - privileged read-only, user read-only +//! +//! The region is automatically divided into 8 equally-sized sub-regions by +//! the MPU. Sub-regions can only be used in regions of size 256 bytes +//! or larger. Any of these 8 sub-regions can be disabled, allowing for +//! creation of ``holes'' in a region which can be left open, or overlaid +//! by another region with different attributes. Any of the 8 sub-regions +//! can be disabled with a logical OR of any of the following flags: +//! +//! - \b MPU_SUB_RGN_DISABLE_0 +//! - \b MPU_SUB_RGN_DISABLE_1 +//! - \b MPU_SUB_RGN_DISABLE_2 +//! - \b MPU_SUB_RGN_DISABLE_3 +//! - \b MPU_SUB_RGN_DISABLE_4 +//! - \b MPU_SUB_RGN_DISABLE_5 +//! - \b MPU_SUB_RGN_DISABLE_6 +//! - \b MPU_SUB_RGN_DISABLE_7 +//! +//! Finally, the region can be initially enabled or disabled with one of +//! the following flags: +//! +//! - \b MPU_RGN_ENABLE +//! - \b MPU_RGN_DISABLE +//! +//! As an example, to set a region with the following attributes: size of +//! 32 KB, execution enabled, read-only for both privileged and user, one +//! sub-region disabled, and initially enabled; the \e ui32Flags parameter +//! would have the following value: +//! +//! +//! (MPU_RGN_SIZE_32K | MPU_RGN_PERM_EXEC | MPU_RGN_PERM_PRV_RO_USR_RO | +//! MPU_SUB_RGN_DISABLE_2 | MPU_RGN_ENABLE) +//! +//! +//! \note This function writes to multiple registers and is not protected +//! from interrupts. It is possible that an interrupt which accesses a +//! region may occur while that region is in the process of being changed. +//! The safest way to handle this is to disable a region before changing it. +//! Refer to the discussion of this in the API Detailed Description section. +//! +//! \return None. +// +//***************************************************************************** +void +MPURegionSet(uint32_t ui32Region, uint32_t ui32Addr, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Region < 8); + ASSERT(ui32Addr == + (ui32Addr & ~0 << (((ui32Flags & NVIC_MPU_ATTR_SIZE_M) >> 1) + 1))); + + // + // Program the base address, use the region field to select the + // region at the same time. + // + HWREG(NVIC_MPU_BASE) = ui32Addr | ui32Region | NVIC_MPU_BASE_VALID; + + // + // Program the region attributes. Set the TEX field and the S, C, + // and B bits to fixed values that are suitable for all Tiva C and + // E Series memory. + // + HWREG(NVIC_MPU_ATTR) = ((ui32Flags & ~(NVIC_MPU_ATTR_TEX_M | + NVIC_MPU_ATTR_CACHEABLE)) | + NVIC_MPU_ATTR_SHAREABLE | NVIC_MPU_ATTR_BUFFRABLE); +} + +//***************************************************************************** +// +//! Gets the current settings for a specific region. +//! +//! \param ui32Region is the region number to get. +//! \param pui32Addr points to storage for the base address of the region. +//! \param pui32Flags points to the attribute flags for the region. +//! +//! This function retrieves the configuration of a specific region. The +//! meanings and format of the parameters is the same as that of the +//! MPURegionSet() function. +//! +//! This function can be used to save the configuration of a region for later +//! use with the MPURegionSet() function. The region's enable state is +//! preserved in the attributes that are saved. +//! +//! \return None. +// +//***************************************************************************** +void +MPURegionGet(uint32_t ui32Region, uint32_t *pui32Addr, uint32_t *pui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Region < 8); + ASSERT(pui32Addr); + ASSERT(pui32Flags); + + // + // Select the region to get. + // + HWREG(NVIC_MPU_NUMBER) = ui32Region; + + // + // Read and store the base address for the region. + // + *pui32Addr = HWREG(NVIC_MPU_BASE) & NVIC_MPU_BASE_ADDR_M; + + // + // Read and store the region attributes. + // + *pui32Flags = HWREG(NVIC_MPU_ATTR); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the memory management fault. +//! +//! \param pfnHandler is a pointer to the function to be called when the +//! memory management fault occurs. +//! +//! This function sets and enables the handler to be called when the MPU +//! generates a memory management fault due to a protection region access +//! violation. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +MPUIntRegister(void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(pfnHandler); + + // + // Register the interrupt handler. + // + IntRegister(FAULT_MPU, pfnHandler); + + // + // Enable the memory management fault. + // + IntEnable(FAULT_MPU); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the memory management fault. +//! +//! This function disables and clears the handler to be called when a +//! memory management fault occurs. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +MPUIntUnregister(void) +{ + // + // Disable the interrupt. + // + IntDisable(FAULT_MPU); + + // + // Unregister the interrupt handler. + // + IntUnregister(FAULT_MPU); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/onewire.c b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/onewire.c new file mode 100644 index 0000000000000000000000000000000000000000..24d671f12533c6cff7f1ec4be6f2f31672a76889 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/onewire.c @@ -0,0 +1,767 @@ +//***************************************************************************** +// +// onewire.c - Driver for OneWire master module. +// +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup onewire_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_onewire.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/onewire.h" +#include "driverlib/sysctl.h" + +//***************************************************************************** +// +// A bit mask for all transaction related fields in the 1-Wire control +// register. +// +//***************************************************************************** +#define ONEWIRE_TXN_MASK (ONEWIRE_CS_OP_M | ONEWIRE_CS_SZ_M | \ + ONEWIRE_CS_BSIZE_M) + +//***************************************************************************** +// +// Left-shift value for the control register's transaction size. +// +//***************************************************************************** +#define ONEWIRE_TXN_SIZE_LSHIFT 3 + +//***************************************************************************** +// +// Left-shift value for the control register's last byte bit size. +// +//***************************************************************************** +#define ONEWIRE_TXN_BSIZE_LSHIFT \ + 16 + +//***************************************************************************** +// +//! Initializes the 1-Wire module. +//! +//! \param ui32Base specifies the base address of the 1-Wire module. +//! \param ui32InitFlags provides the initialization flags. +//! +//! This function configures and initializes the 1-Wire interface for use. +//! +//! The \e ui32InitFlags parameter is a combination of the following: +//! +//! - \b ONEWIRE_INIT_SPD_STD - standard speed bus timings +//! - \b ONEWIRE_INIT_SPD_OD - overdrive speed bus timings +//! - \b ONEWIRE_INIT_READ_STD - standard read sampling timing +//! - \b ONEWIRE_INIT_READ_LATE - late read sampling timing +//! - \b ONEWIRE_INIT_ATR - standard answer-to-reset presence detect +//! - \b ONEWIRE_INIT_NO_ATR - no answer-to-reset presence detect +//! - \b ONEWIRE_INIT_STD_POL - normal signal polarity +//! - \b ONEWIRE_INIT_ALT_POL - alternate (reverse) signal polarity +//! - \b ONEWIRE_INIT_1_WIRE_CFG - standard 1-Wire (1 data pin) setup +//! - \b ONEWIRE_INIT_2_WIRE_CFG - alternate 2-Wire (2 data pin) setup +//! +//! \return None. +// +//***************************************************************************** +void +OneWireInit(uint32_t ui32Base, uint32_t ui32InitFlags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == ONEWIRE0_BASE); + + // + // Initialize control register. + // + HWREG(ui32Base + ONEWIRE_O_CS) = ui32InitFlags; +} + +//***************************************************************************** +// +//! Issues a reset on the 1-Wire bus. +//! +//! \param ui32Base specifies the base address of the 1-Wire module. +//! +//! This function causes the 1-Wire module to generate a reset signal on the +//! 1-Wire bus. +//! +//! \return None. +// +//***************************************************************************** +void +OneWireBusReset(uint32_t ui32Base) +{ + // + // Check the argument. + // + ASSERT(ui32Base == ONEWIRE0_BASE); + + // + // Issue a bus reset. + // + HWREG(ui32Base + ONEWIRE_O_CS) |= ONEWIRE_CS_RST; +} + +//***************************************************************************** +// +//! Retrieves the 1-Wire bus condition status. +//! +//! \param ui32Base specifies the base address of the 1-Wire module. +//! +//! This function returns the 1-Wire bus conditions reported by the 1-Wire +//! module. These conditions could be a logical OR of any of the following: +//! +//! - \b ONEWIRE_BUS_STATUS_BUSY - A read, write, or reset is active. +//! - \b ONEWIRE_BUS_STATUS_NO_SLAVE - No slave presence pulses detected. +//! - \b ONEWIRE_BUS_STATUS_STUCK - The bus is being held low by non-master. +//! +//! \return Returns the 1-Wire bus conditions if detected else zero. +// +//***************************************************************************** +uint32_t +OneWireBusStatus(uint32_t ui32Base) +{ + // + // Check the argument. + // + ASSERT(ui32Base == ONEWIRE0_BASE); + + // + // Return the status bits from control and status register. + // + return(HWREG(ui32Base + ONEWIRE_O_CS) & (ONEWIRE_CS_BUSY | + ONEWIRE_CS_NOATR | + ONEWIRE_CS_STUCK)); +} + +//***************************************************************************** +// +//! Retrieves data from the 1-Wire interface. +//! +//! \param ui32Base specifies the base address of the 1-Wire module. +//! \param pui32Data is a pointer to storage to hold the read data. +//! +//! This function reads data from the 1-Wire module once all active bus +//! operations are completed. By protocol definition, bit data defaults to +//! a 1. Thus if a slave did not signal any 0-bit data, this read returns +//! 0xffffffff. +//! +//! \return None. +// +//***************************************************************************** +void +OneWireDataGet(uint32_t ui32Base, uint32_t *pui32Data) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == ONEWIRE0_BASE); + ASSERT(pui32Data); + + // + // Wait for any active operations to complete. + // + while(HWREG(ui32Base + ONEWIRE_O_CS) & ONEWIRE_CS_BUSY) + { + } + + // + // Copy the data into the provided storage. + // + *pui32Data = HWREG(ui32Base + ONEWIRE_O_DATR); +} + +//***************************************************************************** +// +//! Retrieves data from the 1-Wire interface. +//! +//! \param ui32Base specifies the base address of the 1-Wire module. +//! \param pui32Data is a pointer to storage to hold the read data. +//! +//! This function reads data from the 1-Wire module if there are no active +//! operations on the bus. Otherwise it returns without reading the data from +//! the module. +//! +//! By protocol definition, bit data defaults to a 1. Thus if a slave did +//! not signal any 0-bit data, this read returns 0xffffffff. +//! +//! \return Returns \b true if a data read was performed, or \b false if the +//! bus was not idle and no data was read. +// +//***************************************************************************** +bool +OneWireDataGetNonBlocking(uint32_t ui32Base, uint32_t *pui32Data) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == ONEWIRE0_BASE); + ASSERT(pui32Data); + + // + // If the bus is busy, return without reading. + // + if(HWREG(ui32Base + ONEWIRE_O_CS) & ONEWIRE_CS_BUSY) + { + return(false); + } + + // + // Copy the data into the provided storage. + // + *pui32Data = HWREG(ui32Base + ONEWIRE_O_DATR); + + // + // Notify the caller data was read from the read register. + // + return(true); +} + +//***************************************************************************** +// +//! Clears the 1-Wire module interrupt sources. +//! +//! \param ui32Base specifies the base address of the 1-Wire module. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! This function clears the specified 1-Wire interrupt sources so that they no +//! longer assert. This function must be called in the interrupt handler to +//! keep the interrupts from being triggered again immediately upon exit. The +//! \e ui32IntFlags parameter can be a logical OR of any of the following: +//! +//! - \b ONEWIRE_INT_RESET_DONE - Bus reset has just completed. +//! - \b ONEWIRE_INT_OP_DONE - Read or write operation completed. If a +//! combined write and read operation was set up, the interrupt signals the +//! read is done. +//! - \b ONEWIRE_INT_NO_SLAVE - No presence detect was signaled by a slave. +//! - \b ONEWIRE_INT_STUCK - Bus is being held low by non-master. +//! - \b ONEWIRE_INT_DMA_DONE - DMA operation has completed. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +OneWireIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the argument. + // + ASSERT(ui32Base == ONEWIRE0_BASE); + ASSERT((ui32IntFlags & ~(ONEWIRE_IM_RST | ONEWIRE_IM_OPC | ONEWIRE_IM_DMA | + ONEWIRE_IM_NOATR | ONEWIRE_IM_STUCK)) == 0); + + // + // Clear the requested interrupts. + // + HWREG(ui32Base + ONEWIRE_O_ICR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! Disables individual 1-Wire module interrupt sources. +//! +//! \param ui32Base specifies the base address of the 1-Wire module. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be disabled. +//! +//! This function disables the indicated 1-Wire interrupt sources. The +//! \e ui32IntFlags parameter can be a logical OR of any of the following: +//! +//! - \b ONEWIRE_INT_RESET_DONE - Bus reset has just completed. +//! - \b ONEWIRE_INT_OP_DONE - Read or write operation completed. If a +//! combined write and read operation was set up, the interrupt signals the +//! read is done. +//! - \b ONEWIRE_INT_NO_SLAVE - No presence detect was signaled by a slave. +//! - \b ONEWIRE_INT_STUCK - Bus is being held low by non-master. +//! - \b ONEWIRE_INT_DMA_DONE - DMA operation has completed +//! +//! \return None. +// +//***************************************************************************** +void +OneWireIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == ONEWIRE0_BASE); + ASSERT((ui32IntFlags & ~(ONEWIRE_IM_RST | ONEWIRE_IM_OPC | ONEWIRE_IM_DMA | + ONEWIRE_IM_NOATR | ONEWIRE_IM_STUCK)) == 0); + + // + // Disable the requested interrupts. + // + HWREG(ui32Base + ONEWIRE_O_IM) &= ~ui32IntFlags; +} + +//***************************************************************************** +// +//! Enables individual 1-Wire module interrupt sources. +//! +//! \param ui32Base specifies the base address of the 1-Wire module. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated 1-Wire interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. The \e ui32IntFlags +//! parameter can be a logical OR of any of the following: +//! +//! - \b ONEWIRE_INT_RESET_DONE - Bus reset has just completed. +//! - \b ONEWIRE_INT_OP_DONE - Read or write operation completed. If a +//! combined write and read operation was set up, the interrupt signals the +//! read is done. +//! - \b ONEWIRE_INT_NO_SLAVE - No presence detect was signaled by a slave. +//! - \b ONEWIRE_INT_STUCK - Bus is being held low by non-master. +//! - \b ONEWIRE_INT_DMA_DONE - DMA operation has completed +//! +//! \return None. +// +//***************************************************************************** +void +OneWireIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == ONEWIRE0_BASE); + ASSERT((ui32IntFlags & ~(ONEWIRE_IM_RST | ONEWIRE_IM_OPC | ONEWIRE_IM_DMA | + ONEWIRE_IM_NOATR | ONEWIRE_IM_STUCK)) == 0); + + // + // Enable the requested interrupts. + // + HWREG(ui32Base + ONEWIRE_O_IM) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! Gets the current 1-Wire interrupt status. +//! +//! \param ui32Base specifies the base address of the 1-Wire module. +//! \param bMasked is \b false if the raw interrupt status is required or +//! \b true if the masked interrupt status is required. +//! +//! This function returns the interrupt status for the 1-Wire module. Either +//! the raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \return Returns the masked or raw 1-Wire interrupt status, as a bit field +//! of any of the following values: +//! +//! - \b ONEWIRE_INT_RESET_DONE - Bus reset has just completed. +//! - \b ONEWIRE_INT_OP_DONE - Read or write operation completed. +//! - \b ONEWIRE_INT_NO_SLAVE - No presence detect was signaled by a slave. +//! - \b ONEWIRE_INT_STUCK - Bus is being held low by non-master. +//! - \b ONEWIRE_INT_DMA_DONE - DMA operation has completed +// +//***************************************************************************** +uint32_t +OneWireIntStatus(uint32_t ui32Base, bool bMasked) +{ + // + // Check the argument. + // + ASSERT(ui32Base == ONEWIRE0_BASE); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ui32Base + ONEWIRE_O_MIS)); + } + else + { + return(HWREG(ui32Base + ONEWIRE_O_RIS)); + } +} + +//***************************************************************************** +// +//! Returns the 1-Wire controller interrupt number. +//! +//! \param ui32Base specifies the 1-Wire module base address. +//! +//! This function returns the interrupt number for the 1-Wire module with the +//! base address passed in the \e ui32Base parameter. +//! +//! \return Returns a 1-Wire interrupt number or 0 if the interrupt does not +//! exist. +// +//***************************************************************************** +static uint32_t +_OneWireIntNumberGet(uint32_t ui32Base) +{ + uint32_t ui32Int; + + ASSERT(ui32Base == ONEWIRE0_BASE); + + ui32Int = 0; + + // + // Find the valid interrupt number for the 1-Wire module. + // + if(CLASS_IS_TM4C129) + { + ui32Int = INT_ONEWIRE0_TM4C129; + } + + return(ui32Int); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the 1-Wire module. +//! +//! \param ui32Base is the base address of the 1-Wire module. +//! \param pfnHandler is a pointer to the function to be called when the +//! 1-Wire interrupt occurs. +//! +//! This function sets the handler to be called when a 1-Wire interrupt occurs. +//! This function enables the global interrupt in the interrupt controller; +//! specific 1-Wire interrupts must be enabled via OneWireIntEnable(). If +//! necessary, it is the interrupt handler's responsibility to clear the +//! interrupt source via OneWireIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +OneWireIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) +{ + uint32_t ui32Int; + + // + // Check the argument. + // + ASSERT(ui32Base == ONEWIRE0_BASE); + ASSERT(pfnHandler); + + // + // Get the actual interrupt number for the 1-Wire module. + // + ui32Int = _OneWireIntNumberGet(ui32Base); + + ASSERT(ui32Int != 0); + + // + // Register the interrupt handler. + // + IntRegister(ui32Int, pfnHandler); + + // + // Enable the 1-Wire peripheral interrupt. + // + IntEnable(ui32Int); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the 1-Wire module. +//! +//! \param ui32Base is the base address of the 1-Wire module. +//! +//! This function clears the handler to be called when an 1-Wire interrupt +//! occurs. This function also masks off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +OneWireIntUnregister(uint32_t ui32Base) +{ + uint32_t ui32Int; + + // + // Check the argument. + // + ASSERT(ui32Base == ONEWIRE0_BASE); + + // + // Get the actual interrupt number for the 1-Wire module. + // + ui32Int = _OneWireIntNumberGet(ui32Base); + ASSERT(ui32Int != 0); + + // + // Disable the 1-Wire peripheral interrupt. + // + IntDisable(ui32Int); + + // + // Unregister the interrupt handler. + // + IntUnregister(ui32Int); +} + +//***************************************************************************** +// +//! Disables 1-Wire DMA operations. +//! +//! \param ui32Base is the base address of the 1-Wire module. +//! \param ui32DMAFlags is a bit mask of the DMA features to disable. +//! +//! This function is used to disable 1-Wire DMA features that were enabled +//! by OneWireDMAEnable(). The specified 1-Wire DMA features are disabled. +//! The \e ui32DMAFlags parameter is a combination of the following: +//! +//! - \b ONEWIRE_DMA_BUS_RESET - Issue a 1-Wire bus reset before starting +//! - \b ONEWIRE_DMA_OP_READ - Read after each module transaction +//! - \b ONEWIRE_DMA_OP_MULTI_WRITE - Write after each previous write +//! - \b ONEWIRE_DMA_OP_MULTI_READ - Read after each previous read +//! - \b ONEWIRE_DMA_MODE_SG - Start DMA on enable then repeat on each +//! completion +//! - \b ONEWIRE_DMA_OP_SZ_8 - Bus read/write of 8 bits +//! - \b ONEWIRE_DMA_OP_SZ_16 - Bus read/write of 16 bits +//! - \b ONEWIRE_DMA_OP_SZ_32 - Bus read/write of 32 bits +//! +//! \return None. +// +//***************************************************************************** +void +OneWireDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == ONEWIRE0_BASE); + ASSERT(ui32DMAFlags > 0); + + // + // Clear the transaction size bits + // + HWREG(ui32Base + ONEWIRE_O_CS) = (HWREG(ui32Base + ONEWIRE_O_CS) & + ~(ONEWIRE_TXN_MASK)); + + // + // Disable the DMA features as requested. + // + HWREG(ui32Base + ONEWIRE_O_DMA) &= ~(ui32DMAFlags & 0xff); +} + +//***************************************************************************** +// +//! Enables 1-Wire DMA operations. +//! +//! \param ui32Base is the base address of the 1-Wire module. +//! \param ui32DMAFlags is a bit mask of the DMA features to enable. +//! +//! This function enables the specified 1-Wire DMA features. The 1-Wire module +//! can be configured for write operations, read operations, small write and +//! read operations, and scatter-gather support of mixed operations. +//! +//! The \e ui32DMAFlags parameter is a combination of the following: +//! +//! - \b ONEWIRE_DMA_BUS_RESET - Issue a 1-Wire bus reset before starting +//! - \b ONEWIRE_DMA_OP_READ - Read after each module transaction +//! - \b ONEWIRE_DMA_OP_MULTI_WRITE - Write after each previous write +//! - \b ONEWIRE_DMA_OP_MULTI_READ - Read after each previous read +//! - \b ONEWIRE_DMA_MODE_SG - Start DMA on enable then repeat on each +//! completion +//! - \b ONEWIRE_DMA_OP_SZ_8 - Bus read/write of 8 bits +//! - \b ONEWIRE_DMA_OP_SZ_16 - Bus read/write of 16 bits +//! - \b ONEWIRE_DMA_OP_SZ_32 - Bus read/write of 32 bits +//! +//! \note The uDMA controller must be properly configured before DMA can be +//! used with the 1-Wire module. +//! +//! \return None. +// +//***************************************************************************** +void +OneWireDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == ONEWIRE0_BASE); + ASSERT(ui32DMAFlags > 0); + + // + // set up the transaction size. + // + HWREG(ui32Base + ONEWIRE_O_CS) = ((HWREG(ui32Base + ONEWIRE_O_CS) & + ~(ONEWIRE_TXN_MASK)) | + (ui32DMAFlags >> 8)); + + // + // Enable DMA with the parameters provided. + // + HWREG(ui32Base + ONEWIRE_O_DMA) = (ui32DMAFlags & 0xf); + + // + // If a read transaction was requested, seed the write data register. This + // will trigger the DMA reads to start. This should not be done for + // scatter-gather operations. + // + if((ui32DMAFlags & (ONEWIRE_DMA_DMAOP_RDSNG | ONEWIRE_DMA_DMAOP_RDMUL)) && + !(ui32DMAFlags & ONEWIRE_DMA_SG)) + { + // + // Workaround for Snowflake DMA receive trigger errata. + // + if(CLASS_IS_TM4C129) + { + SysCtlDelay(9); + } + + // + // Write DATW to trigger DMA receive start. + // + HWREG(ui32Base + ONEWIRE_O_DATW) = 0xffffffff; + } +} + +//***************************************************************************** +// +//! Performs a 1-Wire protocol transaction on the bus. +//! +//! \param ui32Base specifies the base address of the 1-Wire module. +//! \param ui32OpMode sets the transaction type. +//! \param ui32Data is the data for a write operation. +//! \param ui32BitCnt specifies the number of valid bits (1-32) for the +//! operation. +//! +//! This function performs a 1-Wire protocol transaction, read and/or write, on +//! the bus. The application should confirm the bus is idle before starting a +//! read or write transaction. +//! +//! The \e ui32OpMode defines the activity for the bus operations and is a +//! logical OR of the following: +//! +//! - \b ONEWIRE_OP_RESET - Indicates the operation should be started with +//! a bus reset. +//! - \b ONEWIRE_OP_WRITE - A write operation +//! - \b ONEWIRE_OP_READ - A read operation +//! +//! \note If both a read and write operation are requested, the write will be +//! performed prior to the read. +//! +//! \return None. +// +//***************************************************************************** +void +OneWireTransaction(uint32_t ui32Base, uint32_t ui32OpMode, uint32_t ui32Data, + uint32_t ui32BitCnt) +{ + uint32_t ui32Transaction; + + // + // Check the arguments. + // + ASSERT(ui32Base == ONEWIRE0_BASE); + ASSERT((ui32OpMode & (ONEWIRE_OP_RESET | ONEWIRE_OP_WRITE | + ONEWIRE_OP_READ)) > 0); + ASSERT((ui32BitCnt >= 1) && (ui32BitCnt <= 32)); + + // + // Read the control register and clear any transaction related + // bit fields. + // + ui32Transaction = HWREG(ui32Base + ONEWIRE_O_CS) & ~(ONEWIRE_TXN_MASK); + + // + // Add the user specified operation flags. + // + ui32Transaction |= (ui32OpMode & (ONEWIRE_OP_RESET | ONEWIRE_OP_WRITE | + ONEWIRE_OP_READ)); + + // + // set up for a read or write transaction. + // + if(ui32Transaction & (ONEWIRE_CS_OP_WR | ONEWIRE_CS_OP_RD)) + { + // + // Configure the 1-Wire module for the transaction size. This is + // specified as 1-4 bytes and the specific bit size for the last + // byte therein. + // + ui32Transaction |= ((((ui32BitCnt % 8) ? (ui32BitCnt / 8) + 1 : + (ui32BitCnt / 8)) - 1) << + ONEWIRE_TXN_SIZE_LSHIFT); + ui32Transaction |= ((ui32BitCnt % 8) << ONEWIRE_TXN_BSIZE_LSHIFT); + + // + // Write specific setup. + // + if(ui32Transaction & ONEWIRE_CS_OP_WR) + { + // + // Load the data into the write register. + // + HWREG(ui32Base + ONEWIRE_O_DATW) = ui32Data; + } + } + + // + // Start the transaction. + // + HWREG(ui32Base + ONEWIRE_O_CS) = ui32Transaction; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/pwm.c b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/pwm.c new file mode 100644 index 0000000000000000000000000000000000000000..54fbe52e5c02265edc5a47aec54ddc9f4a2ca2f4 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/pwm.c @@ -0,0 +1,2162 @@ +//***************************************************************************** +// +// pwm.c - API for the PWM modules +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup pwm_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_pwm.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/pwm.h" + +//***************************************************************************** +// +// Misc macros for manipulating the encoded generator and output defines used +// by the API. +// +//***************************************************************************** +#define PWM_GEN_BADDR(_mod_, _gen_) \ + ((_mod_) + (_gen_)) +#define PWM_GEN_EXT_BADDR(_mod_, _gen_) \ + ((_mod_) + PWM_GEN_EXT_0 + \ + ((_gen_) - PWM_GEN_0) * 2) +#define PWM_OUT_BADDR(_mod_, _out_) \ + ((_mod_) + ((_out_) & 0xFFFFFFC0)) +#define PWM_IS_OUTPUT_ODD(_out_) \ + ((_out_) & 0x00000001) + +//***************************************************************************** +// +//! \internal +//! Checks a PWM generator number. +//! +//! \param ui32Gen is the generator number. +//! +//! This function determines if a PWM generator number is valid. +//! +//! \return Returnes \b true if the generator number is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static bool +_PWMGenValid(uint32_t ui32Gen) +{ + return((ui32Gen == PWM_GEN_0) || (ui32Gen == PWM_GEN_1) || + (ui32Gen == PWM_GEN_2) || (ui32Gen == PWM_GEN_3)); +} +#endif + +//***************************************************************************** +// +//! \internal +//! Checks a PWM output number. +//! +//! \param ui32PWMOut is the output number. +//! +//! This function determines if a PWM output number is valid. +//! +//! \return Returns \b true if the output number is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static bool +_PWMOutValid(uint32_t ui32PWMOut) +{ + return((ui32PWMOut == PWM_OUT_0) || (ui32PWMOut == PWM_OUT_1) || + (ui32PWMOut == PWM_OUT_2) || (ui32PWMOut == PWM_OUT_3) || + (ui32PWMOut == PWM_OUT_4) || (ui32PWMOut == PWM_OUT_5) || + (ui32PWMOut == PWM_OUT_6) || (ui32PWMOut == PWM_OUT_7)); +} +#endif + +//***************************************************************************** +// +//! Configures a PWM generator. +//! +//! \param ui32Base is the base address of the PWM module. +//! \param ui32Gen is the PWM generator to configure. This parameter must be +//! one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ui32Config is the configuration for the PWM generator. +//! +//! This function is used to set the mode of operation for a PWM generator. +//! The counting mode, synchronization mode, and debug behavior are all +//! configured. After configuration, the generator is left in the disabled +//! state. +//! +//! A PWM generator can count in two different modes: count down mode or count +//! up/down mode. In count down mode, it counts from a value down to zero, +//! and then resets to the preset value, producing left-aligned PWM +//! signals (that is, the rising edge of the two PWM signals produced by the +//! generator occur at the same time). In count up/down mode, it counts up +//! from zero to the preset value, counts back down to zero, and then repeats +//! the process, producing center-aligned PWM signals (that is, +//! the middle of the high/low period of the PWM signals produced by the +//! generator occurs at the same time). +//! +//! When the PWM generator parameters (period and pulse width) are modified, +//! their effect on the output PWM signals can be delayed. In synchronous +//! mode, the parameter updates are not applied until a synchronization event +//! occurs. This mode allows multiple parameters to be modified and take +//! effect simultaneously, instead of one at a time. Additionally, parameters +//! to multiple PWM generators in synchronous mode can be updated +//! simultaneously, allowing them to be treated as if they were a unified +//! generator. In non-synchronous mode, the parameter updates are not delayed +//! until a synchronization event. In either mode, the parameter updates only +//! occur when the counter is at zero to help prevent oddly formed PWM signals +//! during the update (that is, a PWM pulse that is too short or too long). +//! +//! The PWM generator can either pause or continue running when the processor +//! is stopped via the debugger. If configured to pause, it continues to +//! count until it reaches zero, at which point it pauses until the +//! processor is restarted. If configured to continue running, it keeps +//! counting as if nothing had happened. +//! +//! The \e ui32Config parameter contains the desired configuration. It is the +//! logical OR of the following: +//! +//! - \b PWM_GEN_MODE_DOWN or \b PWM_GEN_MODE_UP_DOWN to specify the counting +//! mode +//! - \b PWM_GEN_MODE_SYNC or \b PWM_GEN_MODE_NO_SYNC to specify the counter +//! load and comparator update synchronization mode +//! - \b PWM_GEN_MODE_DBG_RUN or \b PWM_GEN_MODE_DBG_STOP to specify the debug +//! behavior +//! - \b PWM_GEN_MODE_GEN_NO_SYNC, \b PWM_GEN_MODE_GEN_SYNC_LOCAL, or +//! \b PWM_GEN_MODE_GEN_SYNC_GLOBAL to specify the update synchronization +//! mode for generator counting mode changes +//! - \b PWM_GEN_MODE_DB_NO_SYNC, \b PWM_GEN_MODE_DB_SYNC_LOCAL, or +//! \b PWM_GEN_MODE_DB_SYNC_GLOBAL to specify the deadband parameter +//! synchronization mode +//! - \b PWM_GEN_MODE_FAULT_LATCHED or \b PWM_GEN_MODE_FAULT_UNLATCHED to +//! specify whether fault conditions are latched or not +//! - \b PWM_GEN_MODE_FAULT_MINPER or \b PWM_GEN_MODE_FAULT_NO_MINPER to +//! specify whether minimum fault period support is required +//! - \b PWM_GEN_MODE_FAULT_EXT or \b PWM_GEN_MODE_FAULT_LEGACY to specify +//! whether extended fault source selection support is enabled or not +//! +//! Setting \b PWM_GEN_MODE_FAULT_MINPER allows an application to set the +//! minimum duration of a PWM fault signal. Faults are signaled for at +//! least this time even if the external fault pin deasserts earlier. Care +//! should be taken when using this mode because during the fault signal +//! period, the fault interrupt from the PWM generator remains asserted. The +//! fault interrupt handler may, therefore, reenter immediately if it exits +//! prior to expiration of the fault timer. +//! +//! \note Changes to the counter mode affect the period of the PWM signals +//! produced. PWMGenPeriodSet() and PWMPulseWidthSet() should be called after +//! any changes to the counter mode of a generator. +//! +//! \return None. +// +//***************************************************************************** +void +PWMGenConfigure(uint32_t ui32Base, uint32_t ui32Gen, + uint32_t ui32Config) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); + ASSERT(_PWMGenValid(ui32Gen)); + + // + // Compute the generator's base address. + // + ui32Gen = PWM_GEN_BADDR(ui32Base, ui32Gen); + + // + // Change the global configuration of the generator. + // + HWREG(ui32Gen + PWM_O_X_CTL) = ((HWREG(ui32Gen + PWM_O_X_CTL) & + ~(PWM_X_CTL_MODE | PWM_X_CTL_DEBUG | + PWM_X_CTL_LATCH | PWM_X_CTL_MINFLTPER | + PWM_X_CTL_FLTSRC | + PWM_X_CTL_DBFALLUPD_M | + PWM_X_CTL_DBRISEUPD_M | + PWM_X_CTL_DBCTLUPD_M | + PWM_X_CTL_GENBUPD_M | + PWM_X_CTL_GENAUPD_M | + PWM_X_CTL_LOADUPD | PWM_X_CTL_CMPAUPD | + PWM_X_CTL_CMPBUPD)) | ui32Config); + + // + // Set the individual PWM generator controls. + // + if(ui32Config & PWM_X_CTL_MODE) + { + // + // In up/down count mode, set the signal high on up count comparison + // and low on down count comparison (that is, center align the + // signals). + // + HWREG(ui32Gen + PWM_O_X_GENA) = (PWM_X_GENA_ACTCMPAU_ONE | + PWM_X_GENA_ACTCMPAD_ZERO); + HWREG(ui32Gen + PWM_O_X_GENB) = (PWM_X_GENB_ACTCMPBU_ONE | + PWM_X_GENB_ACTCMPBD_ZERO); + } + else + { + // + // In down count mode, set the signal high on load and low on count + // comparison (that is, left align the signals). + // + HWREG(ui32Gen + PWM_O_X_GENA) = (PWM_X_GENA_ACTLOAD_ONE | + PWM_X_GENA_ACTCMPAD_ZERO); + HWREG(ui32Gen + PWM_O_X_GENB) = (PWM_X_GENB_ACTLOAD_ONE | + PWM_X_GENB_ACTCMPBD_ZERO); + } +} + +//***************************************************************************** +// +//! Sets the period of a PWM generator. +//! +//! \param ui32Base is the base address of the PWM module. +//! \param ui32Gen is the PWM generator to be modified. This parameter must be +//! one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ui32Period specifies the period of PWM generator output, measured +//! in clock ticks. +//! +//! This function sets the period of the specified PWM generator block, where +//! the period of the generator block is defined as the number of PWM clock +//! ticks between pulses on the generator block zero signal. +//! +//! \note Any subsequent calls made to this function before an update occurs +//! cause the previous values to be overwritten. +//! +//! \return None. +// +//***************************************************************************** +void +PWMGenPeriodSet(uint32_t ui32Base, uint32_t ui32Gen, + uint32_t ui32Period) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); + ASSERT(_PWMGenValid(ui32Gen)); + + // + // Compute the generator's base address. + // + ui32Gen = PWM_GEN_BADDR(ui32Base, ui32Gen); + + // + // Set the reload register based on the mode. + // + if(HWREG(ui32Gen + PWM_O_X_CTL) & PWM_X_CTL_MODE) + { + // + // In up/down count mode, set the reload register to half the requested + // period. + // + ASSERT((ui32Period / 2) < 65536); + HWREG(ui32Gen + PWM_O_X_LOAD) = ui32Period / 2; + } + else + { + // + // In down count mode, set the reload register to the requested period + // minus one. + // + ASSERT((ui32Period <= 65536) && (ui32Period != 0)); + HWREG(ui32Gen + PWM_O_X_LOAD) = ui32Period - 1; + } +} + +//***************************************************************************** +// +//! Gets the period of a PWM generator block. +//! +//! \param ui32Base is the base address of the PWM module. +//! \param ui32Gen is the PWM generator to query. This parameter must be one +//! of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! +//! This function gets the period of the specified PWM generator block. The +//! period of the generator block is defined as the number of PWM clock ticks +//! between pulses on the generator block zero signal. +//! +//! If the update of the counter for the specified PWM generator has yet +//! to be completed, the value returned may not be the active period. The +//! value returned is the programmed period, measured in PWM clock ticks. +//! +//! \return Returns the programmed period of the specified generator block +//! in PWM clock ticks. +// +//***************************************************************************** +uint32_t +PWMGenPeriodGet(uint32_t ui32Base, uint32_t ui32Gen) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); + ASSERT(_PWMGenValid(ui32Gen)); + + // + // Compute the generator's base address. + // + ui32Gen = PWM_GEN_BADDR(ui32Base, ui32Gen); + + // + // Figure out the counter mode. + // + if(HWREG(ui32Gen + PWM_O_X_CTL) & PWM_X_CTL_MODE) + { + // + // The period is twice the reload register value. + // + return(HWREG(ui32Gen + PWM_O_X_LOAD) * 2); + } + else + { + // + // The period is the reload register value plus one. + // + return(HWREG(ui32Gen + PWM_O_X_LOAD) + 1); + } +} + +//***************************************************************************** +// +//! Enables the timer/counter for a PWM generator block. +//! +//! \param ui32Base is the base address of the PWM module. +//! \param ui32Gen is the PWM generator to be enabled. This parameter must be +//! one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! +//! This function allows the PWM clock to drive the timer/counter for the +//! specified generator block. +//! +//! \return None. +// +//***************************************************************************** +void +PWMGenEnable(uint32_t ui32Base, uint32_t ui32Gen) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); + ASSERT(_PWMGenValid(ui32Gen)); + + // + // Enable the PWM generator. + // + HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_CTL) |= PWM_X_CTL_ENABLE; +} + +//***************************************************************************** +// +//! Disables the timer/counter for a PWM generator block. +//! +//! \param ui32Base is the base address of the PWM module. +//! \param ui32Gen is the PWM generator to be disabled. This parameter must be +//! one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! +//! This function blocks the PWM clock from driving the timer/counter for the +//! specified generator block. +//! +//! \return None. +// +//***************************************************************************** +void +PWMGenDisable(uint32_t ui32Base, uint32_t ui32Gen) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); + ASSERT(_PWMGenValid(ui32Gen)); + + // + // Disable the PWM generator. + // + HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_CTL) &= + ~(PWM_X_CTL_ENABLE); +} + +//***************************************************************************** +// +//! Sets the pulse width for the specified PWM output. +//! +//! \param ui32Base is the base address of the PWM module. +//! \param ui32PWMOut is the PWM output to modify. This parameter must be one +//! of \b PWM_OUT_0, \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, +//! \b PWM_OUT_5, \b PWM_OUT_6, or \b PWM_OUT_7. +//! \param ui32Width specifies the width of the positive portion of the pulse. +//! +//! This function sets the pulse width for the specified PWM output, where the +//! pulse width is defined as the number of PWM clock ticks. +//! +//! \note Any subsequent calls made to this function before an update occurs +//! cause the previous values to be overwritten. +//! +//! \return None. +// +//***************************************************************************** +void +PWMPulseWidthSet(uint32_t ui32Base, uint32_t ui32PWMOut, + uint32_t ui32Width) +{ + uint32_t ui32GenBase, ui32Reg; + + // + // Check the arguments. + // + ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); + ASSERT(_PWMOutValid(ui32PWMOut)); + + // + // Compute the generator's base address. + // + ui32GenBase = PWM_OUT_BADDR(ui32Base, ui32PWMOut); + + // + // If the counter is in up/down count mode, divide the width by two. + // + if(HWREG(ui32GenBase + PWM_O_X_CTL) & PWM_X_CTL_MODE) + { + ui32Width /= 2; + } + + // + // Get the period. + // + ui32Reg = HWREG(ui32GenBase + PWM_O_X_LOAD); + + // + // Make sure the width is not too large. + // + ASSERT(ui32Width < ui32Reg); + + // + // Compute the compare value. + // + ui32Reg = ui32Reg - ui32Width; + + // + // Write to the appropriate registers. + // + if(PWM_IS_OUTPUT_ODD(ui32PWMOut)) + { + HWREG(ui32GenBase + PWM_O_X_CMPB) = ui32Reg; + } + else + { + HWREG(ui32GenBase + PWM_O_X_CMPA) = ui32Reg; + } +} + +//***************************************************************************** +// +//! Gets the pulse width of a PWM output. +//! +//! \param ui32Base is the base address of the PWM module. +//! \param ui32PWMOut is the PWM output to query. This parameter must be one +//! of \b PWM_OUT_0, \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, +//! \b PWM_OUT_5, \b PWM_OUT_6, or \b PWM_OUT_7. +//! +//! This function gets the currently programmed pulse width for the specified +//! PWM output. If the update of the comparator for the specified output has +//! yet to be completed, the value returned may not be the active pulse width. +//! The value returned is the programmed pulse width, measured in PWM clock +//! ticks. +//! +//! \return Returns the width of the pulse in PWM clock ticks. +// +//***************************************************************************** +uint32_t +PWMPulseWidthGet(uint32_t ui32Base, uint32_t ui32PWMOut) +{ + uint32_t ui32GenBase, ui32Reg, ui32Load; + + // + // Check the arguments. + // + ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); + ASSERT(_PWMOutValid(ui32PWMOut)); + + // + // Compute the generator's base address. + // + ui32GenBase = PWM_OUT_BADDR(ui32Base, ui32PWMOut); + + // + // Then compute the pulse width. If mode is UpDown, set + // width = (load - compare) * 2. Otherwise, set width = load - compare. + // + ui32Load = HWREG(ui32GenBase + PWM_O_X_LOAD); + if(PWM_IS_OUTPUT_ODD(ui32PWMOut)) + { + ui32Reg = HWREG(ui32GenBase + PWM_O_X_CMPB); + } + else + { + ui32Reg = HWREG(ui32GenBase + PWM_O_X_CMPA); + } + ui32Reg = ui32Load - ui32Reg; + + // + // If in up/down count mode, double the pulse width. + // + if(HWREG(ui32GenBase + PWM_O_X_CTL) & PWM_X_CTL_MODE) + { + ui32Reg = ui32Reg * 2; + } + + // + // Return the pulse width. + // + return(ui32Reg); +} + +//***************************************************************************** +// +//! Enables the PWM dead band output and sets the dead band delays. +//! +//! \param ui32Base is the base address of the PWM module. +//! \param ui32Gen is the PWM generator to modify. This parameter must be one +//! of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ui16Rise specifies the width of delay from the rising edge. +//! \param ui16Fall specifies the width of delay from the falling edge. +//! +//! This function sets the dead bands for the specified PWM generator, where +//! the dead bands are defined as the number of \b PWM clock ticks from the +//! rising or falling edge of the generator's \b OutA signal. Note that this +//! function causes the coupling of \b OutB to \b OutA. +//! +//! \return None. +// +//***************************************************************************** +void +PWMDeadBandEnable(uint32_t ui32Base, uint32_t ui32Gen, + uint16_t ui16Rise, uint16_t ui16Fall) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); + ASSERT(_PWMGenValid(ui32Gen)); + ASSERT(ui16Rise < 4096); + ASSERT(ui16Fall < 4096); + + // + // Compute the generator's base address. + // + ui32Gen = PWM_GEN_BADDR(ui32Base, ui32Gen); + + // + // Write the dead band delay values. + // + HWREG(ui32Gen + PWM_O_X_DBRISE) = ui16Rise; + HWREG(ui32Gen + PWM_O_X_DBFALL) = ui16Fall; + + // + // Enable the deadband functionality. + // + HWREG(ui32Gen + PWM_O_X_DBCTL) |= PWM_X_DBCTL_ENABLE; +} + +//***************************************************************************** +// +//! Disables the PWM dead band output. +//! +//! \param ui32Base is the base address of the PWM module. +//! \param ui32Gen is the PWM generator to modify. This parameter must be one +//! of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! +//! This function disables the dead band mode for the specified PWM generator. +//! Doing so decouples the \b OutA and \b OutB signals. +//! +//! \return None. +// +//***************************************************************************** +void +PWMDeadBandDisable(uint32_t ui32Base, uint32_t ui32Gen) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); + ASSERT(_PWMGenValid(ui32Gen)); + + // + // Disable the deadband functionality. + // + HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_DBCTL) &= + ~(PWM_X_DBCTL_ENABLE); +} + +//***************************************************************************** +// +//! Synchronizes all pending updates. +//! +//! \param ui32Base is the base address of the PWM module. +//! \param ui32GenBits are the PWM generator blocks to be updated. This +//! parameter must be the logical OR of any of \b PWM_GEN_0_BIT, +//! \b PWM_GEN_1_BIT, \b PWM_GEN_2_BIT, or \b PWM_GEN_3_BIT. +//! +//! For the selected PWM generators, this function causes all queued updates to +//! the period or pulse width to be applied the next time the corresponding +//! counter becomes zero. +//! +//! \return None. +// +//***************************************************************************** +void +PWMSyncUpdate(uint32_t ui32Base, uint32_t ui32GenBits) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); + ASSERT(!(ui32GenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT | + PWM_GEN_3_BIT))); + + // + // Synchronize pending PWM register changes. + // + HWREG(ui32Base + PWM_O_CTL) = ui32GenBits; +} + +//***************************************************************************** +// +//! Synchronizes the counters in one or multiple PWM generator blocks. +//! +//! \param ui32Base is the base address of the PWM module. +//! \param ui32GenBits are the PWM generator blocks to be synchronized. This +//! parameter must be the logical OR of any of \b PWM_GEN_0_BIT, +//! \b PWM_GEN_1_BIT, \b PWM_GEN_2_BIT, or \b PWM_GEN_3_BIT. +//! +//! For the selected PWM module, this function synchronizes the time base of +//! the generator blocks by causing the specified generator counters to be +//! reset to zero. +//! +//! \return None. +// +//***************************************************************************** +void +PWMSyncTimeBase(uint32_t ui32Base, uint32_t ui32GenBits) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); + ASSERT(!(ui32GenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT | + PWM_GEN_3_BIT))); + + // + // Synchronize the counters in the specified generators by writing to the + // module's synchronization register. + // + HWREG(ui32Base + PWM_O_SYNC) = ui32GenBits; +} + +//***************************************************************************** +// +//! Enables or disables PWM outputs. +//! +//! \param ui32Base is the base address of the PWM module. +//! \param ui32PWMOutBits are the PWM outputs to be modified. This parameter +//! must be the logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, +//! \b PWM_OUT_2_BIT, \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, +//! \b PWM_OUT_6_BIT, or \b PWM_OUT_7_BIT. +//! \param bEnable determines if the signal is enabled or disabled. +//! +//! This function enables or disables the selected PWM outputs. The outputs +//! are selected using the parameter \e ui32PWMOutBits. The parameter \e +//! bEnable determines the state of the selected outputs. If \e bEnable is +//! \b true, then the selected PWM outputs are enabled, or placed in the active +//! state. If \e bEnable is \b false, then the selected outputs are disabled +//! or placed in the inactive state. +//! +//! \return None. +// +//***************************************************************************** +void +PWMOutputState(uint32_t ui32Base, uint32_t ui32PWMOutBits, + bool bEnable) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); + ASSERT(!(ui32PWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | + PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT | + PWM_OUT_6_BIT | PWM_OUT_7_BIT))); + + // + // Read the module's ENABLE output control register and set or clear the + // requested bits. + // + if(bEnable == true) + { + HWREG(ui32Base + PWM_O_ENABLE) |= ui32PWMOutBits; + } + else + { + HWREG(ui32Base + PWM_O_ENABLE) &= ~(ui32PWMOutBits); + } +} + +//***************************************************************************** +// +//! Selects the inversion mode for PWM outputs. +//! +//! \param ui32Base is the base address of the PWM module. +//! \param ui32PWMOutBits are the PWM outputs to be modified. This parameter +//! must be the logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, +//! \b PWM_OUT_2_BIT, \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, +//! \b PWM_OUT_6_BIT, or \b PWM_OUT_7_BIT. +//! \param bInvert determines if the signal is inverted or passed through. +//! +//! This function is used to select the inversion mode for the selected PWM +//! outputs. The outputs are selected using the parameter \e ui32PWMOutBits. +//! The parameter \e bInvert determines the inversion mode for the selected +//! outputs. If \e bInvert is \b true, this function causes the specified +//! PWM output signals to be inverted or made active low. If \e bInvert is +//! \b false, the specified outputs are passed through as is or made active +//! high. +//! +//! \return None. +// +//***************************************************************************** +void +PWMOutputInvert(uint32_t ui32Base, uint32_t ui32PWMOutBits, + bool bInvert) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); + ASSERT(!(ui32PWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | + PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT | + PWM_OUT_6_BIT | PWM_OUT_7_BIT))); + + // + // Read the module's INVERT output control register and set or clear the + // requested bits. + // + if(bInvert == true) + { + HWREG(ui32Base + PWM_O_INVERT) |= ui32PWMOutBits; + } + else + { + HWREG(ui32Base + PWM_O_INVERT) &= ~(ui32PWMOutBits); + } +} + +//***************************************************************************** +// +//! Specifies the level of PWM outputs suppressed in response to a fault +//! condition. +//! +//! \param ui32Base is the base address of the PWM module. +//! \param ui32PWMOutBits are the PWM outputs to be modified. This parameter +//! must be the logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, +//! \b PWM_OUT_2_BIT, \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, +//! \b PWM_OUT_6_BIT, or \b PWM_OUT_7_BIT. +//! \param bDriveHigh determines if the signal is driven high or low during an +//! active fault condition. +//! +//! This function determines whether a PWM output pin that is suppressed in +//! response to a fault condition is driven high or low. The affected outputs +//! are selected using the parameter \e ui32PWMOutBits. The parameter +//! \e bDriveHigh determines the output level for the pins identified by +//! \e ui32PWMOutBits. If \e bDriveHigh is \b true then the selected outputs +//! are driven high when a fault is detected. If it is \e false, the pins are +//! driven low. +//! +//! In a fault condition, pins which have not been configured to be suppressed +//! via a call to PWMOutputFault() are unaffected by this function. +//! +//! \note This function is available only on devices which support extended +//! PWM fault handling. +//! +//! \return None. +// +//***************************************************************************** +void +PWMOutputFaultLevel(uint32_t ui32Base, uint32_t ui32PWMOutBits, + bool bDriveHigh) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); + ASSERT(!(ui32PWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | + PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT | + PWM_OUT_6_BIT | PWM_OUT_7_BIT))); + + // + // Read the module's FAULT output control register and set or clear the + // requested bits. + // + if(bDriveHigh == true) + { + HWREG(ui32Base + PWM_O_FAULTVAL) |= ui32PWMOutBits; + } + else + { + HWREG(ui32Base + PWM_O_FAULTVAL) &= ~(ui32PWMOutBits); + } +} + +//***************************************************************************** +// +//! Specifies the state of PWM outputs in response to a fault condition. +//! +//! \param ui32Base is the base address of the PWM module. +//! \param ui32PWMOutBits are the PWM outputs to be modified. This parameter +//! must be the logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, +//! \b PWM_OUT_2_BIT, \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, +//! \b PWM_OUT_6_BIT, or \b PWM_OUT_7_BIT. +//! \param bFaultSuppress determines if the signal is suppressed or passed +//! through during an active fault condition. +//! +//! This function sets the fault handling characteristics of the selected PWM +//! outputs. The outputs are selected using the parameter \e ui32PWMOutBits. +//! The parameter \e bFaultSuppress determines the fault handling +//! characteristics for the selected outputs. If \e bFaultSuppress is \b true, +//! then the selected outputs are made inactive. If \e bFaultSuppress is +//! \b false, then the selected outputs are unaffected by the detected fault. +//! +//! On devices supporting extended PWM fault handling, the state the affected +//! output pins are driven to can be configured with PWMOutputFaultLevel(). If +//! not configured, or if the device does not support extended PWM fault +//! handling, affected outputs are driven low on a fault condition. +//! +//! \return None. +// +//***************************************************************************** +void +PWMOutputFault(uint32_t ui32Base, uint32_t ui32PWMOutBits, + bool bFaultSuppress) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); + ASSERT(!(ui32PWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | + PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT | + PWM_OUT_6_BIT | PWM_OUT_7_BIT))); + + // + // Read the module's FAULT output control register and set or clear the + // requested bits. + // + if(bFaultSuppress == true) + { + HWREG(ui32Base + PWM_O_FAULT) |= ui32PWMOutBits; + } + else + { + HWREG(ui32Base + PWM_O_FAULT) &= ~(ui32PWMOutBits); + } +} + +//***************************************************************************** +// +//! Gets the PWM generator interrupt number. +//! +//! \param ui32Base is the base address of the PWM module. +//! \param ui32Gen is the PWM generator in question. This parameter must be +//! one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! +//! This function returns the interrupt number of the corresponding PWM +//! generator. +//! +//! \return Returns the interrupt number. +// +//***************************************************************************** +static uint32_t +_PWMGenIntNumberGet(uint32_t ui32Base, uint32_t ui32Gen) +{ + // + // Determine the generator and PWM module in question. + // + switch(ui32Base + ui32Gen) + { + // + // The first PWM generator in the first PWM module. + // + case PWM0_BASE + PWM_GEN_0: + { + if(CLASS_IS_TM4C123) + { + return(INT_PWM0_0_TM4C123); + } + else if(CLASS_IS_TM4C129) + { + return(INT_PWM0_0_TM4C129); + } + else + { + return(0); + } + } + + // + // The second PWM generator in the first PWM module. + // + case PWM0_BASE + PWM_GEN_1: + { + if(CLASS_IS_TM4C129) + { + return(INT_PWM0_1_TM4C129); + } + else + { + return(0); + } + } + + // + // The third PWM generator in the first PWM module. + // + case PWM0_BASE + PWM_GEN_2: + { + if(CLASS_IS_TM4C129) + { + return(INT_PWM0_2_TM4C129); + } + else + { + return(0); + } + } + + // + // The fourth PWM generator in the first PWM module. + // + case PWM0_BASE + PWM_GEN_3: + { + if(CLASS_IS_TM4C129) + { + return(INT_PWM0_3_TM4C129); + } + else + { + return(0); + } + } + + // + // The first PWM generator in the second PWM module. + // + case PWM1_BASE + PWM_GEN_0: + { + if(CLASS_IS_TM4C123) + { + return(INT_PWM1_0_TM4C123); + } + else + { + return(0); + } + } + + // + // The first PWM generator in the second PWM module. + // + case PWM1_BASE + PWM_GEN_1: + { + if(CLASS_IS_TM4C123) + { + return(INT_PWM1_1_TM4C123); + } + else + { + return(0); + } + } + + // + // The first PWM generator in the second PWM module. + // + case PWM1_BASE + PWM_GEN_2: + { + if(CLASS_IS_TM4C123) + { + return(INT_PWM1_2_TM4C123); + } + else + { + return(0); + } + } + + // + // The first PWM generator in the second PWM module. + // + case PWM1_BASE + PWM_GEN_3: + { + if(CLASS_IS_TM4C123) + { + return(INT_PWM1_3_TM4C123); + } + else + { + return(0); + } + } + + // + // An unknown PWM module/generator was specified. + // + default: + { + return(0); + } + } +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the specified PWM generator block. +//! +//! \param ui32Base is the base address of the PWM module. +//! \param ui32Gen is the PWM generator in question. This parameter must be +//! one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param pfnIntHandler is a pointer to the function to be called when the PWM +//! generator interrupt occurs. +//! +//! This function ensures that the interrupt handler specified by +//! \e pfnIntHandler is called when an interrupt is detected for the specified +//! PWM generator block. This function also enables the corresponding +//! PWM generator interrupt in the interrupt controller; individual generator +//! interrupts and interrupt sources must be enabled with PWMIntEnable() and +//! PWMGenIntTrigEnable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +PWMGenIntRegister(uint32_t ui32Base, uint32_t ui32Gen, + void (*pfnIntHandler)(void)) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); + ASSERT(_PWMGenValid(ui32Gen)); + + // + // Get the interrupt number associated with the specified generator. + // + ui32Int = _PWMGenIntNumberGet(ui32Base, ui32Gen); + + ASSERT(ui32Int != 0); + + // + // Register the interrupt handler. + // + IntRegister(ui32Int, pfnIntHandler); + + // + // Enable the PWMx interrupt. + // + IntEnable(ui32Int); +} + +//***************************************************************************** +// +//! Removes an interrupt handler for the specified PWM generator block. +//! +//! \param ui32Base is the base address of the PWM module. +//! \param ui32Gen is the PWM generator in question. This parameter must be +//! one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! +//! This function unregisters the interrupt handler for the specified +//! PWM generator block. This function also disables the corresponding +//! PWM generator interrupt in the interrupt controller; individual generator +//! interrupts and interrupt sources must be disabled with PWMIntDisable() and +//! PWMGenIntTrigDisable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +PWMGenIntUnregister(uint32_t ui32Base, uint32_t ui32Gen) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); + ASSERT(_PWMGenValid(ui32Gen)); + + // + // Get the interrupt number associated with the specified generator. + // + ui32Int = _PWMGenIntNumberGet(ui32Base, ui32Gen); + + ASSERT(ui32Int != 0); + + // + // Disable the PWMx interrupt. + // + IntDisable(ui32Int); + + // + // Unregister the interrupt handler. + // + IntUnregister(ui32Int); +} + +//***************************************************************************** +// +//! Gets the PWM fault interrupt number. +//! +//! \param ui32Base is the base address of the PWM module. +//! +//! This function returns the fault interrupt number of the corresponding +//! PWM module. +//! +//! \return Returns the interrupt number. +// +//***************************************************************************** +static uint32_t +_PWMFaultIntNumberGet(uint32_t ui32Base) +{ + // + // Return the fault interrupt number. + // + if(CLASS_IS_TM4C123) + { + return((ui32Base == PWM0_BASE) ? INT_PWM0_FAULT_TM4C123 : + INT_PWM1_FAULT_TM4C123); + } + else if(CLASS_IS_TM4C129) + { + return((ui32Base == PWM0_BASE) ? INT_PWM0_FAULT_TM4C129 : 0); + } + else + { + return(0); + } +} + +//***************************************************************************** +// +//! Registers an interrupt handler for a fault condition detected in a PWM +//! module. +//! +//! \param ui32Base is the base address of the PWM module. +//! \param pfnIntHandler is a pointer to the function to be called when the PWM +//! fault interrupt occurs. +//! +//! This function ensures that the interrupt handler specified by +//! \e pfnIntHandler is called when a fault interrupt is detected for the +//! selected PWM module. This function also enables the PWM fault +//! interrupt in the NVIC; the PWM fault interrupt must also be enabled at the +//! module level using PWMIntEnable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +PWMFaultIntRegister(uint32_t ui32Base, void (*pfnIntHandler)(void)) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); + + // + // Get the interrupt number associated with the specified module. + // + ui32Int = _PWMFaultIntNumberGet(ui32Base); + + ASSERT(ui32Int != 0); + + // + // Register the interrupt handler, returning an error if one occurs. + // + IntRegister(ui32Int, pfnIntHandler); + + // + // Enable the PWM fault interrupt. + // + IntEnable(ui32Int); +} + +//***************************************************************************** +// +//! Removes the PWM fault condition interrupt handler. +//! +//! \param ui32Base is the base address of the PWM module. +//! +//! This function removes the interrupt handler for a PWM fault interrupt +//! from the selected PWM module. This function also disables the PWM +//! fault interrupt in the NVIC; the PWM fault interrupt must also be disabled +//! at the module level using PWMIntDisable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +PWMFaultIntUnregister(uint32_t ui32Base) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); + + // + // Get the interrupt number associated with the specified module. + // + ui32Int = _PWMFaultIntNumberGet(ui32Base); + + ASSERT(ui32Int != 0); + + // + // Disable the PWM fault interrupt. + // + IntDisable(ui32Int); + + // + // Unregister the interrupt handler, returning an error if one occurs. + // + IntUnregister(ui32Int); +} + +//***************************************************************************** +// +//! Enables interrupts and triggers for the specified PWM generator block. +//! +//! \param ui32Base is the base address of the PWM module. +//! \param ui32Gen is the PWM generator to have interrupts and triggers +//! enabled. This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1, +//! \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ui32IntTrig specifies the interrupts and triggers to be enabled. +//! +//! This function unmasks the specified interrupt(s) and trigger(s) by setting +//! the specified bits of the interrupt/trigger enable register for the +//! specified PWM generator. The \e ui32IntTrig parameter is the logical OR of +//! \b PWM_INT_CNT_ZERO, \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU, +//! \b PWM_INT_CNT_AD, \b PWM_INT_CNT_BU, \b PWM_INT_CNT_BD, +//! \b PWM_TR_CNT_ZERO, \b PWM_TR_CNT_LOAD, \b PWM_TR_CNT_AU, \b PWM_TR_CNT_AD, +//! \b PWM_TR_CNT_BU, or \b PWM_TR_CNT_BD. +//! +//! \return None. +// +//***************************************************************************** +void +PWMGenIntTrigEnable(uint32_t ui32Base, uint32_t ui32Gen, + uint32_t ui32IntTrig) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); + ASSERT(_PWMGenValid(ui32Gen)); + ASSERT((ui32IntTrig & ~(PWM_INT_CNT_ZERO | PWM_INT_CNT_LOAD | + PWM_INT_CNT_AU | PWM_INT_CNT_AD | PWM_INT_CNT_BU | + PWM_INT_CNT_BD | PWM_TR_CNT_ZERO | + PWM_TR_CNT_LOAD | PWM_TR_CNT_AU | PWM_TR_CNT_AD | + PWM_TR_CNT_BU | PWM_TR_CNT_BD)) == 0); + + // + // Enable the specified interrupts/triggers. + // + HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_INTEN) |= ui32IntTrig; +} + +//***************************************************************************** +// +//! Disables interrupts for the specified PWM generator block. +//! +//! \param ui32Base is the base address of the PWM module. +//! \param ui32Gen is the PWM generator to have interrupts and triggers +//! disabled. This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1, +//! \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ui32IntTrig specifies the interrupts and triggers to be disabled. +//! +//! This function masks the specified interrupt(s) and trigger(s) by clearing +//! the specified bits of the interrupt/trigger enable register for the +//! specified PWM generator. The \e ui32IntTrig parameter is the logical OR of +//! \b PWM_INT_CNT_ZERO, \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU, +//! \b PWM_INT_CNT_AD, \b PWM_INT_CNT_BU, \b PWM_INT_CNT_BD, +//! \b PWM_TR_CNT_ZERO, \b PWM_TR_CNT_LOAD, \b PWM_TR_CNT_AU, \b PWM_TR_CNT_AD, +//! \b PWM_TR_CNT_BU, or \b PWM_TR_CNT_BD. +//! +//! \return None. +// +//***************************************************************************** +void +PWMGenIntTrigDisable(uint32_t ui32Base, uint32_t ui32Gen, + uint32_t ui32IntTrig) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); + ASSERT(_PWMGenValid(ui32Gen)); + ASSERT((ui32IntTrig & ~(PWM_INT_CNT_ZERO | PWM_INT_CNT_LOAD | + PWM_INT_CNT_AU | PWM_INT_CNT_AD | PWM_INT_CNT_BU | + PWM_INT_CNT_BD | PWM_TR_CNT_ZERO | + PWM_TR_CNT_LOAD | PWM_TR_CNT_AU | PWM_TR_CNT_AD | + PWM_TR_CNT_BU | PWM_TR_CNT_BD)) == 0); + + // + // Disable the specified interrupts/triggers. + // + HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_INTEN) &= ~(ui32IntTrig); +} + +//***************************************************************************** +// +//! Gets interrupt status for the specified PWM generator block. +//! +//! \param ui32Base is the base address of the PWM module. +//! \param ui32Gen is the PWM generator to query. This parameter must be one +//! of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param bMasked specifies whether masked or raw interrupt status is +//! returned. +//! +//! If \e bMasked is set as \b true, then the masked interrupt status is +//! returned; otherwise, the raw interrupt status is returned. +//! +//! \return Returns the contents of the interrupt status register or the +//! contents of the raw interrupt status register for the specified +//! PWM generator. +// +//***************************************************************************** +uint32_t +PWMGenIntStatus(uint32_t ui32Base, uint32_t ui32Gen, bool bMasked) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); + ASSERT(_PWMGenValid(ui32Gen)); + + // + // Compute the generator's base address. + // + ui32Gen = PWM_GEN_BADDR(ui32Base, ui32Gen); + + // + // Read and return the specified generator's raw or enabled interrupt + // status. + // + if(bMasked == true) + { + return(HWREG(ui32Gen + PWM_O_X_ISC)); + } + else + { + return(HWREG(ui32Gen + PWM_O_X_RIS)); + } +} + +//***************************************************************************** +// +//! Clears the specified interrupt(s) for the specified PWM generator block. +//! +//! \param ui32Base is the base address of the PWM module. +//! \param ui32Gen is the PWM generator to query. This parameter must be one +//! of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ui32Ints specifies the interrupts to be cleared. +//! +//! This function clears the specified interrupt(s) by writing a 1 to the +//! specified bits of the interrupt status register for the specified PWM +//! generator. The \e ui32Ints parameter is the logical OR of +//! \b PWM_INT_CNT_ZERO, \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU, +//! \b PWM_INT_CNT_AD, \b PWM_INT_CNT_BU, or \b PWM_INT_CNT_BD. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +PWMGenIntClear(uint32_t ui32Base, uint32_t ui32Gen, uint32_t ui32Ints) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); + ASSERT(_PWMGenValid(ui32Gen)); + ASSERT((ui32Ints & + ~(PWM_INT_CNT_ZERO | PWM_INT_CNT_LOAD | PWM_INT_CNT_AU | + PWM_INT_CNT_AD | PWM_INT_CNT_BU | PWM_INT_CNT_BD)) == 0); + + // + // Clear the requested interrupts by writing ones to the specified bit + // of the module's interrupt enable register. + // + HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_ISC) = ui32Ints; +} + +//***************************************************************************** +// +//! Enables generator and fault interrupts for a PWM module. +//! +//! \param ui32Base is the base address of the PWM module. +//! \param ui32GenFault contains the interrupts to be enabled. This parameter +//! must be a logical OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, +//! \b PWM_INT_GEN_2, \b PWM_INT_GEN_3, \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, +//! \b PWM_INT_FAULT2, or \b PWM_INT_FAULT3. +//! +//! This function unmasks the specified interrupt(s) by setting the specified +//! bits of the interrupt enable register for the selected PWM module. +//! +//! \return None. +// +//***************************************************************************** +void +PWMIntEnable(uint32_t ui32Base, uint32_t ui32GenFault) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); + ASSERT((ui32GenFault & ~(PWM_INT_GEN_0 | PWM_INT_GEN_1 | PWM_INT_GEN_2 | + PWM_INT_GEN_3 | PWM_INT_FAULT0 | PWM_INT_FAULT1 | + PWM_INT_FAULT2 | PWM_INT_FAULT3)) == 0); + + // + // Read the module's interrupt enable register and enable interrupts + // for the specified PWM generators. + // + HWREG(ui32Base + PWM_O_INTEN) |= ui32GenFault; +} + +//***************************************************************************** +// +//! Disables generator and fault interrupts for a PWM module. +//! +//! \param ui32Base is the base address of the PWM module. +//! \param ui32GenFault contains the interrupts to be disabled. This parameter +//! must be a logical OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, +//! \b PWM_INT_GEN_2, \b PWM_INT_GEN_3, \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, +//! \b PWM_INT_FAULT2, or \b PWM_INT_FAULT3. +//! +//! This function masks the specified interrupt(s) by clearing the specified +//! bits of the interrupt enable register for the selected PWM module. +//! +//! \return None. +// +//***************************************************************************** +void +PWMIntDisable(uint32_t ui32Base, uint32_t ui32GenFault) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); + ASSERT((ui32GenFault & ~(PWM_INT_GEN_0 | PWM_INT_GEN_1 | PWM_INT_GEN_2 | + PWM_INT_GEN_3 | PWM_INT_FAULT0 | PWM_INT_FAULT1 | + PWM_INT_FAULT2 | PWM_INT_FAULT3)) == 0); + + // + // Read the module's interrupt enable register and disable interrupts + // for the specified PWM generators. + // + HWREG(ui32Base + PWM_O_INTEN) &= ~(ui32GenFault); +} + +//***************************************************************************** +// +//! Clears the fault interrupt for a PWM module. +//! +//! \param ui32Base is the base address of the PWM module. +//! +//! This function clears the fault interrupt by writing to the appropriate bit +//! of the interrupt status register for the selected PWM module. +//! +//! This function clears only the FAULT0 interrupt and is retained for +//! backwards compatibility. It is recommended that PWMFaultIntClearExt() be +//! used instead because it supports all fault interrupts supported on devices +//! with and without extended PWM fault handling support. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +PWMFaultIntClear(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); + + // + // Write the only writeable bit in the module's interrupt register. + // + HWREG(ui32Base + PWM_O_ISC) = PWM_ISC_INTFAULT0; +} + +//***************************************************************************** +// +//! Gets the interrupt status for a PWM module. +//! +//! \param ui32Base is the base address of the PWM module. +//! \param bMasked specifies whether masked or raw interrupt status is +//! returned. +//! +//! If \e bMasked is set as \b true, then the masked interrupt status is +//! returned; otherwise, the raw interrupt status is returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, \b PWM_INT_GEN_3, +//! \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, \b PWM_INT_FAULT2, and +//! \b PWM_INT_FAULT3. +//! +//***************************************************************************** +uint32_t +PWMIntStatus(uint32_t ui32Base, bool bMasked) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); + + // + // Read and return either the module's raw or enabled interrupt status. + // + if(bMasked == true) + { + return(HWREG(ui32Base + PWM_O_ISC)); + } + else + { + return(HWREG(ui32Base + PWM_O_RIS)); + } +} + +//***************************************************************************** +// +//! Clears the fault interrupt for a PWM module. +//! +//! \param ui32Base is the base address of the PWM module. +//! \param ui32FaultInts specifies the fault interrupts to clear. +//! +//! This function clears one or more fault interrupts by writing to the +//! appropriate bit of the PWM interrupt status register. The parameter +//! \e ui32FaultInts must be the logical OR of any of \b PWM_INT_FAULT0, +//! \b PWM_INT_FAULT1, \b PWM_INT_FAULT2, or \b PWM_INT_FAULT3. +//! +//! The fault interrupts are derived by performing a logical OR of each of the +//! configured fault trigger signals for a given generator. Therefore, these +//! interrupts are not directly related to the four possible FAULTn inputs to +//! the device but indicate that a fault has been signaled to one of the four +//! possible PWM generators. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +PWMFaultIntClearExt(uint32_t ui32Base, uint32_t ui32FaultInts) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); + ASSERT((ui32FaultInts & ~(PWM_INT_FAULT0 | PWM_INT_FAULT1 | + PWM_INT_FAULT2 | PWM_INT_FAULT3)) == 0); + + // + // Clear the supplied fault bits. + // + HWREG(ui32Base + PWM_O_ISC) = ui32FaultInts; +} + +//***************************************************************************** +// +//! Configures the minimum fault period and fault pin senses for a given +//! PWM generator. +//! +//! \param ui32Base is the base address of the PWM module. +//! \param ui32Gen is the PWM generator for which fault configuration is being +//! set. This function must be one of \b PWM_GEN_0, \b PWM_GEN_1, +//! \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ui32MinFaultPeriod is the minimum fault active period expressed in +//! PWM clock cycles. +//! \param ui32FaultSenses indicates which sense of each FAULT input should be +//! considered the ``asserted'' state. Valid values are logical OR +//! combinations of \b PWM_FAULTn_SENSE_HIGH and \b PWM_FAULTn_SENSE_LOW. +//! +//! This function configures the minimum fault period for a given generator +//! along with the sense of each of the 4 possible fault inputs. The minimum +//! fault period is expressed in PWM clock cycles and takes effect only if +//! PWMGenConfigure() is called with flag \b PWM_GEN_MODE_FAULT_PER set in the +//! \e ui32Config parameter. When a fault input is asserted, the minimum fault +//! period timer ensures that it remains asserted for at least the number of +//! clock cycles specified. +//! +//! \note This function is only available on devices supporting extended PWM +//! fault handling. +//! +//! \return None. +// +//***************************************************************************** +void +PWMGenFaultConfigure(uint32_t ui32Base, uint32_t ui32Gen, + uint32_t ui32MinFaultPeriod, + uint32_t ui32FaultSenses) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); + ASSERT(_PWMGenValid(ui32Gen)); + ASSERT(ui32MinFaultPeriod < PWM_X_MINFLTPER_M); + ASSERT((ui32FaultSenses & ~(PWM_FAULT0_SENSE_HIGH | PWM_FAULT0_SENSE_LOW | + PWM_FAULT1_SENSE_HIGH | PWM_FAULT1_SENSE_LOW | + PWM_FAULT2_SENSE_HIGH | PWM_FAULT2_SENSE_LOW | + PWM_FAULT3_SENSE_HIGH | + PWM_FAULT3_SENSE_LOW)) == 0); + + // + // Write the minimum fault period. + // + HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_MINFLTPER) = + ui32MinFaultPeriod; + + // + // Write the fault senses. + // + HWREG(PWM_GEN_EXT_BADDR(ui32Base, ui32Gen) + PWM_O_X_FLTSEN) = + ui32FaultSenses; +} + +//***************************************************************************** +// +//! Configures the set of fault triggers for a given PWM generator. +//! +//! \param ui32Base is the base address of the PWM module. +//! \param ui32Gen is the PWM generator for which fault triggers are being set. +//! This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or +//! \b PWM_GEN_3. +//! \param ui32Group indicates the subset of possible faults that are to be +//! configured. This parameter must be \b PWM_FAULT_GROUP_0 or +//! \b PWM_FAULT_GROUP_1. +//! \param ui32FaultTriggers defines the set of inputs that are to contribute +//! towards generation of the fault signal to the given PWM generator. For +//! \b PWM_FAULT_GROUP_0, this is the logical OR of \b PWM_FAULT_FAULT0, +//! \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or \b PWM_FAULT_FAULT3. For +//! \b PWM_FAULT_GROUP_1, this is the logical OR of \b PWM_FAULT_DCMP0, +//! \b PWM_FAULT_DCMP1, \b PWM_FAULT_DCMP2, \b PWM_FAULT_DCMP3, +//! \b PWM_FAULT_DCMP4, \b PWM_FAULT_DCMP5, \b PWM_FAULT_DCMP6, or +//! \b PWM_FAULT_DCMP7. +//! +//! This function allows selection of the set of fault inputs that is combined +//! to generate a fault condition to a given PWM generator. By default, all +//! generators use only FAULT0 (for backwards compatibility) but if +//! PWMGenConfigure() is called with flag \b PWM_GEN_MODE_FAULT_SRC in the +//! \e ui32Config parameter, extended fault handling is enabled and this +//! function must be called to configure the fault triggers. +//! +//! The fault signal to the PWM generator is generated by ORing together each +//! of the signals specified in the \e ui32FaultTriggers parameter after having +//! adjusted the sense of each FAULTn input based on the configuration +//! previously set using a call to PWMGenFaultConfigure(). +//! +//! \note This function is only available on devices supporting extended PWM +//! fault handling. +//! +//! \return None. +// +//***************************************************************************** +void +PWMGenFaultTriggerSet(uint32_t ui32Base, uint32_t ui32Gen, + uint32_t ui32Group, uint32_t ui32FaultTriggers) +{ + // + // Check for valid parameters. + // + ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); + ASSERT(_PWMGenValid(ui32Gen)); + ASSERT((ui32Group == PWM_FAULT_GROUP_0) || + (ui32Group == PWM_FAULT_GROUP_1)); + ASSERT((ui32Group == PWM_FAULT_GROUP_0) && + ((ui32FaultTriggers & ~(PWM_FAULT_FAULT0 | PWM_FAULT_FAULT1 | + PWM_FAULT_FAULT2 | PWM_FAULT_FAULT3)) == + 0)); + ASSERT((ui32Group == PWM_FAULT_GROUP_1) && + ((ui32FaultTriggers & ~(PWM_FAULT_DCMP0 | PWM_FAULT_DCMP1 | + PWM_FAULT_DCMP2 | PWM_FAULT_DCMP3 | + PWM_FAULT_DCMP4 | PWM_FAULT_DCMP5 | + PWM_FAULT_DCMP6 | PWM_FAULT_DCMP7)) == 0)); + + // + // Write the fault triggers to the appropriate register. + // + if(ui32Group == PWM_FAULT_GROUP_0) + { + HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_FLTSRC0) = + ui32FaultTriggers; + } + else + { + HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_FLTSRC1) = + ui32FaultTriggers; + } +} + +//***************************************************************************** +// +//! Returns the set of fault triggers currently configured for a given PWM +//! generator. +//! +//! \param ui32Base is the base address of the PWM module. +//! \param ui32Gen is the PWM generator for which fault triggers are being +//! queried. This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1, +//! \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ui32Group indicates the subset of faults that are being queried. +//! This parameter must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1. +//! +//! This function allows an application to query the current set of inputs that +//! contribute to the generation of a fault condition to a given PWM generator. +//! +//! \note This function is only available on devices supporting extended PWM +//! fault handling. +//! +//! \return Returns the current fault triggers configured for the fault group +//! provided. For \b PWM_FAULT_GROUP_0, the returned value is a logical OR of +//! \b PWM_FAULT_FAULT0, \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or +//! \b PWM_FAULT_FAULT3. For \b PWM_FAULT_GROUP_1, the return value is the +//! logical OR of \b PWM_FAULT_DCMP0, \b PWM_FAULT_DCMP1, +//! \b PWM_FAULT_DCMP2, \b PWM_FAULT_DCMP3, \b PWM_FAULT_DCMP4, +//! \b PWM_FAULT_DCMP5, \b PWM_FAULT_DCMP6, or \b PWM_FAULT_DCMP7. +// +//***************************************************************************** +uint32_t +PWMGenFaultTriggerGet(uint32_t ui32Base, uint32_t ui32Gen, + uint32_t ui32Group) +{ + // + // Check for valid parameters. + // + ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); + ASSERT(_PWMGenValid(ui32Gen)); + ASSERT((ui32Group == PWM_FAULT_GROUP_0) || + (ui32Group == PWM_FAULT_GROUP_1)); + + // + // Return the current fault triggers. + // + if(ui32Group == PWM_FAULT_GROUP_0) + { + return(HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_FLTSRC0)); + } + else + { + return(HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_FLTSRC1)); + } +} + +//***************************************************************************** +// +//! Returns the current state of the fault triggers for a given PWM generator. +//! +//! \param ui32Base is the base address of the PWM module. +//! \param ui32Gen is the PWM generator for which fault trigger states are +//! being queried. This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1, +//! \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ui32Group indicates the subset of faults that are being queried. +//! This parameter must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1. +//! +//! This function allows an application to query the current state of each of +//! the fault trigger inputs to a given PWM generator. The current state of +//! each fault trigger input is returned unless PWMGenConfigure() has +//! previously been called with flag \b PWM_GEN_MODE_FAULT_LATCHED in the +//! \e ui32Config parameter, in which case the returned status is the latched +//! fault trigger status. +//! +//! If latched faults are configured, the application must call +//! PWMGenFaultClear() to clear each trigger. +//! +//! \note This function is only available on devices supporting extended PWM +//! fault handling. +//! +//! \return Returns the current state of the fault triggers for the given PWM +//! generator. A set bit indicates that the associated trigger is active. +//! For \b PWM_FAULT_GROUP_0, the returned value is a logical OR of +//! \b PWM_FAULT_FAULT0, \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or +//! \b PWM_FAULT_FAULT3. For \b PWM_FAULT_GROUP_1, the return value is the +//! logical OR of \b PWM_FAULT_DCMP0, \b PWM_FAULT_DCMP1, +//! \b PWM_FAULT_DCMP2, \b PWM_FAULT_DCMP3, \b PWM_FAULT_DCMP4, +//! \b PWM_FAULT_DCMP5, \b PWM_FAULT_DCMP6, or \b PWM_FAULT_DCMP7. +// +//***************************************************************************** +uint32_t +PWMGenFaultStatus(uint32_t ui32Base, uint32_t ui32Gen, + uint32_t ui32Group) +{ + // + // Check for valid parameters. + // + ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); + ASSERT(_PWMGenValid(ui32Gen)); + ASSERT((ui32Group == PWM_FAULT_GROUP_0) || + (ui32Group == PWM_FAULT_GROUP_1)); + + // + // Return the current fault status. + // + if(ui32Group == PWM_FAULT_GROUP_0) + { + return(HWREG(PWM_GEN_EXT_BADDR(ui32Base, ui32Gen) + PWM_O_X_FLTSTAT0)); + } + else + { + return(HWREG(PWM_GEN_EXT_BADDR(ui32Base, ui32Gen) + PWM_O_X_FLTSTAT1)); + } +} + +//***************************************************************************** +// +//! Clears one or more latched fault triggers for a given PWM generator. +//! +//! \param ui32Base is the base address of the PWM module. +//! \param ui32Gen is the PWM generator for which fault trigger states are +//! being queried. This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1, +//! \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ui32Group indicates the subset of faults that are being queried. +//! This parameter must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1. +//! \param ui32FaultTriggers is the set of fault triggers which are to be +//! cleared. +//! +//! This function allows an application to clear the fault triggers for a +//! given PWM generator. This function is only required if PWMGenConfigure() +//! has previously been called with flag \b PWM_GEN_MODE_FAULT_LATCHED in +//! parameter \e ui32Config. +//! +//! \note This function is only available on devices supporting extended PWM +//! fault handling. +//! +//! \return None. +// +//***************************************************************************** +void +PWMGenFaultClear(uint32_t ui32Base, uint32_t ui32Gen, + uint32_t ui32Group, uint32_t ui32FaultTriggers) +{ + // + // Check for valid parameters. + // + ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); + ASSERT(_PWMGenValid(ui32Gen)); + ASSERT((ui32Group == PWM_FAULT_GROUP_0) || + (ui32Group == PWM_FAULT_GROUP_1)); + ASSERT((ui32Group == PWM_FAULT_GROUP_0) && + ((ui32FaultTriggers & ~(PWM_FAULT_FAULT0 | PWM_FAULT_FAULT1 | + PWM_FAULT_FAULT2 | PWM_FAULT_FAULT3)) == + 0)); + ASSERT((ui32Group == PWM_FAULT_GROUP_1) && + ((ui32FaultTriggers & ~(PWM_FAULT_DCMP0 | PWM_FAULT_DCMP1 | + PWM_FAULT_DCMP2 | PWM_FAULT_DCMP3 | + PWM_FAULT_DCMP4 | PWM_FAULT_DCMP5 | + PWM_FAULT_DCMP6 | PWM_FAULT_DCMP7)) == 0)); + + // + // Clear the given faults. + // + if(ui32Group == PWM_FAULT_GROUP_0) + { + HWREG(PWM_GEN_EXT_BADDR(ui32Base, ui32Gen) + PWM_O_X_FLTSTAT0) = + ui32FaultTriggers; + } + else + { + HWREG(PWM_GEN_EXT_BADDR(ui32Base, ui32Gen) + PWM_O_X_FLTSTAT1) = + ui32FaultTriggers; + } +} + +//***************************************************************************** +/// +//! Sets the PWM clock configuration. +//! +//! \param ui32Base is the base address of the PWM module. +//! \param ui32Config is the configuration for the PWM clock; it must be one of +//! \b PWM_SYSCLK_DIV_1, \b PWM_SYSCLK_DIV_2, \b PWM_SYSCLK_DIV_4, +//! \b PWM_SYSCLK_DIV_8, \b PWM_SYSCLK_DIV_16, \b PWM_SYSCLK_DIV_32, or +//! \b PWM_SYSCLK_DIV_64. +//! +//! This function sets the PWM clock divider as the PWM clock source. It also +//! configures the clock frequency to the PWM module as a division of the +//! system clock. This clock is used by the PWM module to generate PWM +//! signals; its rate forms the basis for all PWM signals. +//! +//! \note This function should not be used with TM4C123 devices. For +//! TM4C123 devices, the SysCtlPWMClockGet() function should be used. +//! +//! \note The clocking of the PWM is dependent upon the system clock rate as +//! configured by SysCtlClockFreqSet(). +//! +//! \return None. +// +//***************************************************************************** +void +PWMClockSet(uint32_t ui32Base, uint32_t ui32Config) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); + ASSERT((ui32Config == PWM_SYSCLK_DIV_2) || + (ui32Config == PWM_SYSCLK_DIV_4) || + (ui32Config == PWM_SYSCLK_DIV_8) || + (ui32Config == PWM_SYSCLK_DIV_16) || + (ui32Config == PWM_SYSCLK_DIV_32) || + (ui32Config == PWM_SYSCLK_DIV_64)); + + // + // Set the PWM clock configuration into the PWM clock configuration + // register. + // + HWREG(ui32Base + PWM_O_CC) = ((HWREG(ui32Base + PWM_O_CC) & + ~(PWM_CC_USEPWM | PWM_CC_PWMDIV_M)) | + ui32Config); +} + +//***************************************************************************** +// +//! Gets the current PWM clock configuration. +//! +//! \param ui32Base is the base address of the PWM module. +//! +//! This function returns the current PWM clock configuration. +//! +//! \note This function should not be used with TM4C123 devices. For +//! TM4C123 devices, the SysCtlPWMClockGet() function should be used. +//! +//! \return Returns the current PWM clock configuration; is one of +//! \b PWM_SYSCLK_DIV_1, \b PWM_SYSCLK_DIV_2, \b PWM_SYSCLK_DIV_4, +//! \b PWM_SYSCLK_DIV_8, \b PWM_SYSCLK_DIV_16, \b PWM_SYSCLK_DIV_32, +//! or \b PWM_SYSCLK_DIV_64. +// +//***************************************************************************** +uint32_t +PWMClockGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); + + // + // Return the current PWM clock configuration. Make sure that + // PWM_SYSCLK_DIV_1 is returned in all cases where the divider is disabled. + // + if(!(HWREG(ui32Base + PWM_O_CC) & PWM_CC_USEPWM)) + { + // + // The divider is not active so reflect this in the value we return. + // + return(PWM_SYSCLK_DIV_1); + } + else + { + // + // The divider is active so directly return the masked register value. + // + return(HWREG(ui32Base + PWM_O_CC) & (PWM_CC_USEPWM | PWM_CC_PWMDIV_M)); + } +} + +//***************************************************************************** +// +//! Sets the update mode or synchronization mode to the PWM outputs. +//! +//! \param ui32Base is the base address of the PWM module. +//! \param ui32PWMOutBits are the PWM outputs to be modified. This parameter +//! must be the logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, +//! \b PWM_OUT_2_BIT, \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, +//! \b PWM_OUT_6_BIT, or \b PWM_OUT_7_BIT. +//! \param ui32Mode specifies the enable update mode to use when enabling or +//! disabling PWM outputs. +//! +//! This function sets one of three possible update modes to enable or disable +//! the requested PWM outputs. The \e ui32Mode parameter controls when changes +//! made via calls to PWMOutputState() take effect. Possible values are: +//! +//! - \b PWM_OUTPUT_MODE_NO_SYNC, which enables/disables changes to take effect +//! immediately. +//! - \b PWM_OUTPUT_MODE_SYNC_LOCAL, which causes changes to take effect when +//! the local PWM generator's count next reaches 0. +//! - \b PWM_OUTPUT_MODE_SYNC_GLOBAL, which causes changes to take effect when +//! the local PWM generator's count next reaches 0 following a call to +//! PWMSyncUpdate() which specifies the same generator in its \e ui32GenBits +//! parameter. +//! +//! \note This function is only available on Snowflake class devices. +//! +//! \return None. +// +//***************************************************************************** +void +PWMOutputUpdateMode(uint32_t ui32Base, uint32_t ui32PWMOutBits, + uint32_t ui32Mode) +{ + uint_fast8_t ui8Index; + uint32_t ui32PWMOutputMask; + uint32_t ui32UpdateValueMask; + uint32_t ui32UpdateValue; + uint32_t ui32Temp; + + // + // Check the arguments. + // + ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); + ASSERT(!(ui32PWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | + PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT | + PWM_OUT_6_BIT | PWM_OUT_7_BIT))); + ASSERT((ui32Mode == PWM_OUTPUT_MODE_NO_SYNC) || + (ui32Mode == PWM_OUTPUT_MODE_SYNC_LOCAL) || + (ui32Mode == PWM_OUTPUT_MODE_SYNC_GLOBAL)); + + // + // Initialize the local variables + // + ui8Index = 0; + ui32PWMOutputMask = 1; + ui32UpdateValue = 0; + ui32UpdateValueMask = 0; + + // + // Loop to find out which PWM outputs are to be modified. + // + while(ui8Index < 8) + { + // + // Check if this PWM output is to be modified. + // + if(ui32PWMOutputMask & ui32PWMOutBits) + { + // + // Set the update mode value for the requested PWM output by + // writing to the appropriate field. + // + ui32UpdateValue |= ui32Mode << (ui8Index * 2); + + // + // Compute the mask for the bits to be updated. + // + ui32UpdateValueMask |= 3 << (ui8Index * 2); + } + + // + // Update the PWM output to be checked and the index. + // + ui32PWMOutputMask = ui32PWMOutputMask << 1; + ui8Index++; + } + + // + // Read the Enable Update register and mask the bits that are to be + // updated. + // + ui32Temp = ~ui32UpdateValueMask & HWREG(ui32Base + PWM_O_ENUPD); + + // + // Write the updated values to Enable Update register. + // + HWREG(ui32Base + PWM_O_ENUPD) = ui32Temp | ui32UpdateValue; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/qei.c b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/qei.c new file mode 100644 index 0000000000000000000000000000000000000000..b4def78493344c4eb41e4a5ce89488f329e7de75 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/qei.c @@ -0,0 +1,783 @@ +//***************************************************************************** +// +// qei.c - Driver for the Quadrature Encoder with Index. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup qei_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_qei.h" +#include "inc/hw_types.h" +#include "inc/hw_sysctl.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/qei.h" + +//***************************************************************************** +// +//! Enables the quadrature encoder. +//! +//! \param ui32Base is the base address of the quadrature encoder module. +//! +//! This function enables operation of the quadrature encoder module. The +//! module must be configured before it is enabled. +//! +//! \sa QEIConfigure() +//! +//! \return None. +// +//***************************************************************************** +void +QEIEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); + + // + // Enable the QEI module. + // + HWREG(ui32Base + QEI_O_CTL) |= QEI_CTL_ENABLE; +} + +//***************************************************************************** +// +//! Disables the quadrature encoder. +//! +//! \param ui32Base is the base address of the quadrature encoder module. +//! +//! This function disables operation of the quadrature encoder module. +//! +//! \return None. +// +//***************************************************************************** +void +QEIDisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); + + // + // Disable the QEI module. + // + HWREG(ui32Base + QEI_O_CTL) &= ~(QEI_CTL_ENABLE); +} + +//***************************************************************************** +// +//! Configures the quadrature encoder. +//! +//! \param ui32Base is the base address of the quadrature encoder module. +//! \param ui32Config is the configuration for the quadrature encoder. See +//! below for a description of this parameter. +//! \param ui32MaxPosition specifies the maximum position value. +//! +//! This function configures the operation of the quadrature encoder. The +//! \e ui32Config parameter provides the configuration of the encoder and is +//! the logical OR of several values: +//! +//! - \b QEI_CONFIG_CAPTURE_A or \b QEI_CONFIG_CAPTURE_A_B specify if edges +//! on channel A or on both channels A and B should be counted by the +//! position integrator and velocity accumulator. +//! - \b QEI_CONFIG_NO_RESET or \b QEI_CONFIG_RESET_IDX specify if the +//! position integrator should be reset when the index pulse is detected. +//! - \b QEI_CONFIG_QUADRATURE or \b QEI_CONFIG_CLOCK_DIR specify if +//! quadrature signals are being provided on ChA and ChB, or if a direction +//! signal and a clock are being provided instead. +//! - \b QEI_CONFIG_NO_SWAP or \b QEI_CONFIG_SWAP to specify if the signals +//! provided on ChA and ChB should be swapped before being processed. +//! +//! \e ui32MaxPosition is the maximum value of the position integrator and is +//! the value used to reset the position capture when in index reset mode and +//! moving in the reverse (negative) direction. +//! +//! \return None. +// +//***************************************************************************** +void +QEIConfigure(uint32_t ui32Base, uint32_t ui32Config, + uint32_t ui32MaxPosition) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); + + // + // Write the new configuration to the hardware. + // + HWREG(ui32Base + QEI_O_CTL) = ((HWREG(ui32Base + QEI_O_CTL) & + ~(QEI_CTL_CAPMODE | QEI_CTL_RESMODE | + QEI_CTL_SIGMODE | QEI_CTL_SWAP)) | + ui32Config); + + // + // Set the maximum position. + // + HWREG(ui32Base + QEI_O_MAXPOS) = ui32MaxPosition; +} + +//***************************************************************************** +// +//! Gets the current encoder position. +//! +//! \param ui32Base is the base address of the quadrature encoder module. +//! +//! This function returns the current position of the encoder. Depending upon +//! the configuration of the encoder, and the incident of an index pulse, this +//! value may or may not contain the expected data (that is, if in reset on +//! index mode, if an index pulse has not been encountered, the position +//! counter is not yet aligned with the index pulse). +//! +//! \return The current position of the encoder. +// +//***************************************************************************** +uint32_t +QEIPositionGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); + + // + // Return the current position counter. + // + return(HWREG(ui32Base + QEI_O_POS)); +} + +//***************************************************************************** +// +//! Sets the current encoder position. +//! +//! \param ui32Base is the base address of the quadrature encoder module. +//! \param ui32Position is the new position for the encoder. +//! +//! This function sets the current position of the encoder; the encoder +//! position is then measured relative to this value. +//! +//! \return None. +// +//***************************************************************************** +void +QEIPositionSet(uint32_t ui32Base, uint32_t ui32Position) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); + + // + // Set the position counter. + // + HWREG(ui32Base + QEI_O_POS) = ui32Position; +} + +//***************************************************************************** +// +//! Gets the current direction of rotation. +//! +//! \param ui32Base is the base address of the quadrature encoder module. +//! +//! This function returns the current direction of rotation. In this case, +//! current means the most recently detected direction of the encoder; it may +//! not be presently moving but this is the direction it last moved before it +//! stopped. +//! +//! \return Returns 1 if moving in the forward direction or -1 if moving in the +//! reverse direction. +// +//***************************************************************************** +int32_t +QEIDirectionGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); + + // + // Return the direction of rotation. + // + return((HWREG(ui32Base + QEI_O_STAT) & QEI_STAT_DIRECTION) ? -1 : 1); +} + +//***************************************************************************** +// +//! Gets the encoder error indicator. +//! +//! \param ui32Base is the base address of the quadrature encoder module. +//! +//! This function returns the error indicator for the quadrature encoder. It +//! is an error for both of the signals of the quadrature input to change at +//! the same time. +//! +//! \return Returns \b true if an error has occurred and \b false otherwise. +// +//***************************************************************************** +bool +QEIErrorGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); + + // + // Return the error indicator. + // + return((HWREG(ui32Base + QEI_O_STAT) & QEI_STAT_ERROR) ? true : false); +} + +//***************************************************************************** +// +//! Enables the input filter. +//! +//! \param ui32Base is the base address of the quadrature encoder module. +//! +//! This function enables operation of the input filter in the quadrature +//! encoder module. The module must be configured before input filter is +//! enabled. +//! +//! \sa QEIFilterConfigure() and QEIEnable() +//! +//! \return None. +// +//***************************************************************************** +void +QEIFilterEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); + + // + // Enable the input filter. + // + HWREG(ui32Base + QEI_O_CTL) |= QEI_CTL_FILTEN; +} + +//***************************************************************************** +// +//! Disables the input filter. +//! +//! \param ui32Base is the base address of the quadrature encoder module. +//! +//! This function disables operation of the input filter in the quadrature +//! encoder module. +//! +//! \return None. +// +//***************************************************************************** +void +QEIFilterDisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); + + // + // Disable the input filter. + // + HWREG(ui32Base + QEI_O_CTL) &= ~(QEI_CTL_FILTEN); +} + +//***************************************************************************** +// +//! Configures the input filter. +//! +//! \param ui32Base is the base address of the quadrature encoder module. +//! \param ui32FiltCnt specifies the filter count applied to the input quadrature +//! signal before it is counted; can be one of \b QEI_FILTCNT_2, +//! \b QEI_FILTCNT_3, \b QEI_FILTCNT_4, \b QEI_FILTCNT_5, \b QEI_FILTCNT_6, +//! \b QEI_FILTCNT_7, \b QEI_FILTCNT_8, \b QEI_FILTCNT_9, \b QEI_FILTCNT_10, +//! \b QEI_FILTCNT_11, \b QEI_FILTCNT_12, \b QEI_FILTCNT_13, \b QEI_FILTCNT_14, +//! \b QEI_FILTCNT_15, \b QEI_FILTCNT_16 or \b QEI_FILTCNT_17 +//! +//! This function configures the operation of the input filter prescale count. +//! as specified by \e ui32FiltCnt before the input signals are sent to the +//! quadrature encoder module. +//! +//! \return None. +// +//***************************************************************************** +void +QEIFilterConfigure(uint32_t ui32Base, uint32_t ui32FiltCnt) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); + ASSERT(!(ui32FiltCnt & ~(QEI_CTL_FILTCNT_M))); + + // + // Set the input filter prescale count. + // + HWREG(ui32Base + QEI_O_CTL) = ((HWREG(ui32Base + QEI_O_CTL) & + ~(QEI_CTL_FILTCNT_M)) | ui32FiltCnt); +} + +//***************************************************************************** +// +//! Enables the velocity capture. +//! +//! \param ui32Base is the base address of the quadrature encoder module. +//! +//! This function enables operation of the velocity capture in the quadrature +//! encoder module. The module must be configured before velocity capture is +//! enabled. +//! +//! \sa QEIVelocityConfigure() and QEIEnable() +//! +//! \return None. +// +//***************************************************************************** +void +QEIVelocityEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); + + // + // Enable the velocity capture. + // + HWREG(ui32Base + QEI_O_CTL) |= QEI_CTL_VELEN; +} + +//***************************************************************************** +// +//! Disables the velocity capture. +//! +//! \param ui32Base is the base address of the quadrature encoder module. +//! +//! This function disables operation of the velocity capture in the quadrature +//! encoder module. +//! +//! \return None. +// +//***************************************************************************** +void +QEIVelocityDisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); + + // + // Disable the velocity capture. + // + HWREG(ui32Base + QEI_O_CTL) &= ~(QEI_CTL_VELEN); +} + +//***************************************************************************** +// +//! Configures the velocity capture. +//! +//! \param ui32Base is the base address of the quadrature encoder module. +//! \param ui32PreDiv specifies the predivider applied to the input quadrature +//! signal before it is counted; can be one of \b QEI_VELDIV_1, +//! \b QEI_VELDIV_2, \b QEI_VELDIV_4, \b QEI_VELDIV_8, \b QEI_VELDIV_16, +//! \b QEI_VELDIV_32, \b QEI_VELDIV_64, or \b QEI_VELDIV_128. +//! \param ui32Period specifies the number of clock ticks over which to measure +//! the velocity; must be non-zero. +//! +//! This function configures the operation of the velocity capture portion of +//! the quadrature encoder. The position increment signal is predivided as +//! specified by \e ui32PreDiv before being accumulated by the velocity +//! capture. The divided signal is accumulated over \e ui32Period system clock +//! before being saved and resetting the accumulator. +//! +//! \return None. +// +//***************************************************************************** +void +QEIVelocityConfigure(uint32_t ui32Base, uint32_t ui32PreDiv, + uint32_t ui32Period) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); + ASSERT(!(ui32PreDiv & ~(QEI_CTL_VELDIV_M))); + ASSERT(ui32Period != 0); + + // + // Set the velocity predivider. + // + HWREG(ui32Base + QEI_O_CTL) = ((HWREG(ui32Base + QEI_O_CTL) & + ~(QEI_CTL_VELDIV_M)) | ui32PreDiv); + + // + // Set the timer period. + // + HWREG(ui32Base + QEI_O_LOAD) = ui32Period - 1; +} + +//***************************************************************************** +// +//! Gets the current encoder speed. +//! +//! \param ui32Base is the base address of the quadrature encoder module. +//! +//! This function returns the current speed of the encoder. The value returned +//! is the number of pulses detected in the specified time period; this number +//! can be multiplied by the number of time periods per second and divided by +//! the number of pulses per revolution to obtain the number of revolutions per +//! second. +//! +//! \return Returns the number of pulses captured in the given time period. +// +//***************************************************************************** +uint32_t +QEIVelocityGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); + + // + // Return the speed capture value. + // + return(HWREG(ui32Base + QEI_O_SPEED)); +} + +//***************************************************************************** +// +//! Returns the quadrature encoder interrupt number. +//! +//! \param ui32Base is the base address of the selected quadrature encoder +//! +//! This function returns the interrupt number for the quadrature encoder with +//! the base address passed in the \e ui32Base parameter. +//! +//! \return Returns a quadrature encoder interrupt number or 0 if the interrupt +//! does not exist. +// +//***************************************************************************** +static uint32_t +_QEIIntNumberGet(uint32_t ui32Base) +{ + uint32_t ui32Int; + + ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); + + // + // Find the valid interrupt number for this quadrature encoder. + // + if(CLASS_IS_TM4C123) + { + if(ui32Base == QEI0_BASE) + { + ui32Int = INT_QEI0_TM4C123; + } + else + { + ui32Int = INT_QEI1_TM4C123; + } + } + else if(CLASS_IS_TM4C129) + { + if(ui32Base == QEI0_BASE) + { + ui32Int = INT_QEI0_TM4C129; + } + else + { + ui32Int = 0; + } + } + else + { + ui32Int = 0; + } + + return(ui32Int); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the quadrature encoder interrupt. +//! +//! \param ui32Base is the base address of the quadrature encoder module. +//! \param pfnHandler is a pointer to the function to be called when the +//! quadrature encoder interrupt occurs. +//! +//! This function registers the handler to be called when a quadrature encoder +//! interrupt occurs. This function enables the global interrupt in the +//! interrupt controller; specific quadrature encoder interrupts must be +//! enabled via QEIIntEnable(). It is the interrupt handler's responsibility +//! to clear the interrupt source via QEIIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +QEIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); + + // + // Determine the interrupt number based on the QEI module. + // + ui32Int = _QEIIntNumberGet(ui32Base); + + ASSERT(ui32Int != 0); + + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(ui32Int, pfnHandler); + + // + // Enable the quadrature encoder interrupt. + // + IntEnable(ui32Int); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the quadrature encoder interrupt. +//! +//! \param ui32Base is the base address of the quadrature encoder module. +//! +//! This function unregisters the handler to be called when a quadrature +//! encoder interrupt occurs. This function also masks off the interrupt in +//! the interrupt controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +QEIIntUnregister(uint32_t ui32Base) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); + + // + // Determine the interrupt number based on the QEI module. + // + ui32Int = _QEIIntNumberGet(ui32Base); + + ASSERT(ui32Int != 0); + + // + // Disable the interrupt. + // + IntDisable(ui32Int); + + // + // Unregister the interrupt handler. + // + IntUnregister(ui32Int); +} + +//***************************************************************************** +// +//! Enables individual quadrature encoder interrupt sources. +//! +//! \param ui32Base is the base address of the quadrature encoder module. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be enabled. +//! Can be any of the \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, or +//! \b QEI_INTINDEX values. +//! +//! This function enables the indicated quadrature encoder interrupt sources. +//! Only the sources that are enabled can be reflected to the processor +//! interrupt; disabled sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +void +QEIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); + + // + // Enable the specified interrupts. + // + HWREG(ui32Base + QEI_O_INTEN) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! Disables individual quadrature encoder interrupt sources. +//! +//! \param ui32Base is the base address of the quadrature encoder module. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be disabled. +//! This parameter can be any of the \b QEI_INTERROR, \b QEI_INTDIR, +//! \b QEI_INTTIMER, or \b QEI_INTINDEX values. +//! +//! This function disables the indicated quadrature encoder interrupt sources. +//! Only the sources that are enabled can be reflected to the processor +//! interrupt; disabled sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +void +QEIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); + + // + // Disable the specified interrupts. + // + HWREG(ui32Base + QEI_O_INTEN) &= ~(ui32IntFlags); +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ui32Base is the base address of the quadrature encoder module. +//! \param bMasked is false if the raw interrupt status is required and true if +//! the masked interrupt status is required. +//! +//! This function returns the interrupt status for the quadrature encoder +//! module. Either the raw interrupt status or the status of interrupts that +//! are allowed to reflect to the processor can be returned. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of +//! \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, and \b QEI_INTINDEX. +// +//***************************************************************************** +uint32_t +QEIIntStatus(uint32_t ui32Base, bool bMasked) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ui32Base + QEI_O_ISC)); + } + else + { + return(HWREG(ui32Base + QEI_O_RIS)); + } +} + +//***************************************************************************** +// +//! Clears quadrature encoder interrupt sources. +//! +//! \param ui32Base is the base address of the quadrature encoder module. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! This parameter can be any of the \b QEI_INTERROR, \b QEI_INTDIR, +//! \b QEI_INTTIMER, or \b QEI_INTINDEX values. +//! +//! The specified quadrature encoder interrupt sources are cleared, so that +//! they no longer assert. This function must be called in the interrupt +//! handler to keep the interrupt from being triggered again immediately upon +//! exit. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +QEIIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); + + // + // Clear the requested interrupt sources. + // + HWREG(ui32Base + QEI_O_ISC) = ui32IntFlags; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/shamd5.c b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/shamd5.c new file mode 100644 index 0000000000000000000000000000000000000000..d748ac4bb5310b48399d428d9f0a1d2dbc4506d6 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/shamd5.c @@ -0,0 +1,1092 @@ +//***************************************************************************** +// +// shamd5.c - Driver for the SHA/MD5 module. +// +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#include +#include +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_nvic.h" +#include "inc/hw_shamd5.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/shamd5.h" + +//***************************************************************************** +// +//! \addtogroup shamd5_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! Resets the SHA/MD5 module. +//! +//! \param ui32Base is the base address of the SHA/MD5 module. +//! +//! This function performs a soft-reset of the SHA/MD5 module using the +//! SYSCONFIG register. +//! +//! \return None. +// +//***************************************************************************** +void +SHAMD5Reset(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == SHAMD5_BASE); + + // + // Set the soft-reset bit. + // + HWREG(ui32Base + SHAMD5_O_SYSCONFIG) |= SHAMD5_SYSCONFIG_SOFTRESET; + + // + // Wait for the reset to complete. + // + while((HWREG(ui32Base + SHAMD5_O_SYSSTATUS) & + SHAMD5_SYSSTATUS_RESETDONE) == 0) + { + } + + // + // Force idle mode. + // + HWREG(ui32Base + SHAMD5_O_SYSCONFIG) = + ((HWREG(ui32Base + SHAMD5_O_SYSCONFIG) & ~SHAMD5_SYSCONFIG_SIDLE_M) | + SHAMD5_SYSCONFIG_SIDLE_FORCE); +} + +//***************************************************************************** +// +//! Enables the uDMA requests in the SHA/MD5 module. +//! +//! \param ui32Base is the base address of the SHA/MD5 module. +//! +//! This function configures the DMA options of the SHA/MD5 module. +//! +//! \return None +// +//***************************************************************************** +void +SHAMD5DMAEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == SHAMD5_BASE); + + // + // Write the new configuration into the register. + // + HWREG(ui32Base + SHAMD5_O_SYSCONFIG) |= + SHAMD5_SYSCONFIG_SADVANCED | SHAMD5_SYSCONFIG_DMA_EN; +} + +//***************************************************************************** +// +//! Disables the uDMA requests in the SHA/MD5 module. +//! +//! \param ui32Base is the base address of the SHA/MD5 module. +//! +//! This function configures the DMA options of the SHA/MD5 module. +//! +//! \return None +// +//***************************************************************************** +void +SHAMD5DMADisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == SHAMD5_BASE); + + // + // Write the new configuration into the register. + // + HWREG(ui32Base + SHAMD5_O_SYSCONFIG) &= + ~(SHAMD5_SYSCONFIG_SADVANCED | SHAMD5_SYSCONFIG_DMA_EN); +} + +//***************************************************************************** +// +//! Get the interrupt status of the SHA/MD5 module. +//! +//! \param ui32Base is the base address of the SHA/MD5 module. +//! \param bMasked is \b false if the raw interrupt status is required and +//! \b true if the masked interrupt status is required. +//! +//! This function returns the current value of the IRQSTATUS register. The +//! value will be a logical OR of the following: +//! +//! - \b SHAMD5_INT_CONTEXT_READY - Context input registers are ready. +//! - \b SHAMD5_INT_PARTHASH_READY - Context output registers are ready after +//! a context switch. +//! - \b SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data. +//! - \b SHAMD5_INT_OUTPUT_READY - Context output registers are ready. +//! +//! \return Interrupt status +// +//***************************************************************************** +uint32_t +SHAMD5IntStatus(uint32_t ui32Base, bool bMasked) +{ + uint32_t ui32Status, ui32Enable, ui32Temp; + + // + // Check the arguments. + // + ASSERT(ui32Base == SHAMD5_BASE); + + // + // Return the value of the IRQSTATUS register. + // + ui32Status = HWREG(ui32Base + SHAMD5_O_IRQSTATUS); + if(bMasked) + { + ui32Enable = HWREG(ui32Base + SHAMD5_O_IRQENABLE); + ui32Temp = HWREG(ui32Base + SHAMD5_O_DMAMIS); + return((ui32Status & ui32Enable) | + ((ui32Temp & 0x00000001) << 19) | + ((ui32Temp & 0x00000002) << 16) | + ((ui32Temp & 0x00000004) << 14)); + } + else + { + ui32Temp = HWREG(ui32Base + SHAMD5_O_DMARIS); + return(ui32Status | + ((ui32Temp & 0x00000001) << 19) | + ((ui32Temp & 0x00000002) << 16) | + ((ui32Temp & 0x00000004) << 14)); + } +} + +//***************************************************************************** +// +//! Enable interrupt sources in the SHA/MD5 module. +//! +//! \param ui32Base is the base address of the SHA/MD5 module. +//! \param ui32IntFlags contains desired interrupts to enable. +//! +//! This function enables interrupt sources in the SHA/MD5 module. +//! ui32IntFlags must be a logical OR of one or more of the following +//! values: +//! +//! - \b SHAMD5_INT_CONTEXT_READY - Context input registers are ready. +//! - \b SHAMD5_INT_PARTHASH_READY - Context output registers are ready after +//! a context switch. +//! - \b SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data. +//! - \b SHAMD5_INT_OUTPUT_READY - Context output registers are ready. +//! +//! \return None. +// +//***************************************************************************** +void +SHAMD5IntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == SHAMD5_BASE); + ASSERT((ui32IntFlags == SHAMD5_INT_CONTEXT_READY) || + (ui32IntFlags == SHAMD5_INT_PARTHASH_READY) || + (ui32IntFlags == SHAMD5_INT_INPUT_READY) || + (ui32IntFlags == SHAMD5_INT_OUTPUT_READY)); + + // + // Enable the interrupt sources. + // + HWREG(ui32Base + SHAMD5_O_DMAIM) |= (((ui32IntFlags & 0x00010000) >> 14) | + ((ui32IntFlags & 0x00020000) >> 16) | + ((ui32IntFlags & 0x00040000) >> 19)); + HWREG(ui32Base + SHAMD5_O_IRQENABLE) |= ui32IntFlags & 0x0000ffff; + + // + // Enable all interrupts. + // + HWREG(ui32Base + SHAMD5_O_SYSCONFIG) |= SHAMD5_SYSCONFIG_IT_EN; +} + +//***************************************************************************** +// +//! Disable interrupt sources in the SHA/MD5 module. +//! +//! \param ui32Base is the base address of the SHA/MD5 module. +//! \param ui32IntFlags contains desired interrupts to disable. +//! +//! \e ui32IntFlags must be a logical OR of one or more of the following +//! values: +//! +//! - \b SHAMD5_INT_CONTEXT_READY - Context input registers are ready. +//! - \b SHAMD5_INT_PARTHASH_READY - Context output registers are ready after +//! a context switch. +//! - \b SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data. +//! - \b SHAMD5_INT_OUTPUT_READY - Context output registers are ready. +//! +//! \return None. +// +//***************************************************************************** +void +SHAMD5IntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == SHAMD5_BASE); + ASSERT((ui32IntFlags == SHAMD5_INT_CONTEXT_READY) || + (ui32IntFlags == SHAMD5_INT_PARTHASH_READY) || + (ui32IntFlags == SHAMD5_INT_INPUT_READY) || + (ui32IntFlags == SHAMD5_INT_OUTPUT_READY)); + + // + // Clear the corresponding flags disabling the interrupt sources. + // + HWREG(ui32Base + SHAMD5_O_DMAIM) &= ~(((ui32IntFlags & 0x00010000) >> 14) | + ((ui32IntFlags & 0x00020000) >> 16) | + ((ui32IntFlags & 0x00040000) >> 19)); + HWREG(ui32Base + SHAMD5_O_IRQENABLE) &= ~(ui32IntFlags & 0x0000ffff); + + // + // If there are no interrupts enabled, then disable all interrupts. + // + if(HWREG(ui32Base + SHAMD5_O_IRQENABLE) == 0x0) + { + HWREG(ui32Base + SHAMD5_O_SYSCONFIG) &= ~SHAMD5_SYSCONFIG_IT_EN; + } +} + +//***************************************************************************** +// +//! Clears interrupt sources in the SHA/MD5 module. +//! +//! \param ui32Base is the base address of the SHA/MD5 module. +//! \param ui32IntFlags contains desired interrupts to disable. +//! +//! \e ui32IntFlags must be a logical OR of one or more of the following +//! values: +//! +//! - \b SHAMD5_INT_CONTEXT_READY - Context input registers are ready. +//! - \b SHAMD5_INT_PARTHASH_READY - Context output registers are ready after +//! a context switch. +//! - \b SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data. +//! - \b SHAMD5_INT_OUTPUT_READY - Context output registers are ready. +//! +//! \return None. +// +//***************************************************************************** +void +SHAMD5IntClear(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == SHAMD5_BASE); + ASSERT((ui32IntFlags == SHAMD5_INT_CONTEXT_READY) || + (ui32IntFlags == SHAMD5_INT_PARTHASH_READY) || + (ui32IntFlags == SHAMD5_INT_INPUT_READY) || + (ui32IntFlags == SHAMD5_INT_OUTPUT_READY)); + + // + // Clear the corresponding flags disabling the interrupt sources. + // + HWREG(ui32Base + SHAMD5_O_DMAIC) = (((ui32IntFlags & 0x00010000) >> 14) | + ((ui32IntFlags & 0x00020000) >> 16) | + ((ui32IntFlags & 0x00040000) >> 19)); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the SHA/MD5 module. +//! +//! \param ui32Base is the base address of the SHA/MD5 module. +//! \param pfnHandler is a pointer to the function to be called when the +//! enabled SHA/MD5 interrupts occur. +//! +//! This function registers the interrupt handler in the interrupt vector +//! table, and enables SHA/MD5 interrupts on the interrupt controller; +//! specific SHA/MD5 interrupt sources must be enabled using +//! SHAMD5IntEnable(). The interrupt handler being registered must clear +//! the source of the interrupt using SHAMD5IntClear(). +//! +//! If the application is using a static interrupt vector table stored in +//! flash, then it is not necessary to register the interrupt handler this way. +//! Instead, IntEnable() should be used to enable SHA/MD5 interrupts on the +//! interrupt controller. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +SHAMD5IntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == SHAMD5_BASE); + + // + // Register the interrupt handler. + // + IntRegister(INT_SHA0_TM4C129, pfnHandler); + + // + // Enable the interrupt + // + IntEnable(INT_SHA0_TM4C129); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the SHA/MD5 module. +//! +//! \param ui32Base is the base address of the SHA/MD5 module. +//! +//! This function unregisters the previously registered interrupt handler and +//! disables the interrupt in the interrupt controller. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +SHAMD5IntUnregister(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == SHAMD5_BASE); + + // + // Disable the interrupt. + // + IntDisable(INT_SHA0_TM4C129); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_SHA0_TM4C129); +} + +//***************************************************************************** +// +//! Write the hash length to the SHA/MD5 module. +//! +//! \param ui32Base is the base address of the SHA/MD5 module. +//! \param ui32Length is the hash length in bytes. +//! +//! This function writes the length of the hash data of the current operation +//! to the SHA/MD5 module. The value must be a multiple of 64 if the close +//! hash is not set in the mode register. +//! +//! \note When this register is written, hash processing is triggered. +//! +//! \return None. +// +//***************************************************************************** +void +SHAMD5HashLengthSet(uint32_t ui32Base, uint32_t ui32Length) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == SHAMD5_BASE); + + // + // Set the LENGTH register and start processing. + // + HWREG(ui32Base + SHAMD5_O_LENGTH) = ui32Length; +} + +//***************************************************************************** +// +//! Writes the mode in the SHA/MD5 module. +//! +//! \param ui32Base is the base address of the SHA/MD5 module. +//! \param ui32Mode is the mode of the SHA/MD5 module. +//! +//! This function writes the mode register configuring the SHA/MD5 module. +//! +//! The ui32Mode parameter is a bit-wise OR of values: +//! +//! - \b SHAMD5_ALGO_MD5 - Regular hash with MD5 +//! - \b SHAMD5_ALGO_SHA1 - Regular hash with SHA-1 +//! - \b SHAMD5_ALGO_SHA224 - Regular hash with SHA-224 +//! - \b SHAMD5_ALGO_SHA256 - Regular hash with SHA-256 +//! - \b SHAMD5_ALGO_HMAC_MD5 - HMAC with MD5 +//! - \b SHAMD5_ALGO_HMAC_SHA1 - HMAC with SHA-1 +//! - \b SHAMD5_ALGO_HMAC_SHA224 - HMAC with SHA-224 +//! - \b SHAMD5_ALGO_HMAC_SHA256 - HMAC with SHA-256 +//! +//! \return None +// +//***************************************************************************** +void +SHAMD5ConfigSet(uint32_t ui32Base, uint32_t ui32Mode) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == SHAMD5_BASE); + ASSERT((ui32Mode == SHAMD5_ALGO_MD5) || + (ui32Mode == SHAMD5_ALGO_SHA1) || + (ui32Mode == SHAMD5_ALGO_SHA224) || + (ui32Mode == SHAMD5_ALGO_SHA256) || + (ui32Mode == SHAMD5_ALGO_HMAC_MD5) || + (ui32Mode == SHAMD5_ALGO_HMAC_SHA1) || + (ui32Mode == SHAMD5_ALGO_HMAC_SHA224) || + (ui32Mode == SHAMD5_ALGO_HMAC_SHA256)); + + // + // Write the value in the MODE register. + // + HWREG(ui32Base + SHAMD5_O_MODE) = ui32Mode; +} + +//***************************************************************************** +// +//! Perform a non-blocking write of 16 words of data to the SHA/MD5 module. +//! +//! \param ui32Base is the base address of the SHA/MD5 module. +//! \param pui32Src is the pointer to the 16-word array of data that will be +//! written. +//! +//! This function writes 16 words of data into the data register regardless +//! of whether or not the module is ready to accept the data. +//! +//! \return This function returns true if the write completed successfully. +//! It returns false if the module was not ready. +// +//***************************************************************************** +bool +SHAMD5DataWriteNonBlocking(uint32_t ui32Base, uint32_t *pui32Src) +{ + uint32_t ui32Counter; + + // + // Check the arguments. + // + ASSERT(ui32Base == SHAMD5_BASE); + + // + // Check that the SHA/MD5 module is ready for data. If not, return false. + // + if((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_INPUT_READY) == 0) + { + return(false); + } + + // + // Write the 16 words of data. + // + for(ui32Counter = 0; ui32Counter < 64; ui32Counter += 4) + { + HWREG(ui32Base + SHAMD5_O_DATA_0_IN + ui32Counter) = *pui32Src++; + } + + // + // Return true as a sign of successfully completing the function. + // + return(true); +} + +//***************************************************************************** +// +//! Perform a blocking write of 16 words of data to the SHA/MD5 module. +//! +//! \param ui32Base is the base address of the SHA/MD5 module. +//! \param pui32Src is the pointer to the 16-word array of data that will be +//! written. +//! +//! This function does not return until the module is ready to accept data and +//! the data has been written. +//! +//! \return None. +// +//***************************************************************************** +void +SHAMD5DataWrite(uint32_t ui32Base, uint32_t *pui32Src) +{ + uint32_t ui32Counter; + + // + // Check the arguments. + // + ASSERT(ui32Base == SHAMD5_BASE); + + // + // Wait for the module to be ready to accept data. + // + while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_INPUT_READY) == 0) + { + } + + // + // Write the 16 words of data. + // + for(ui32Counter = 0; ui32Counter < 64; ui32Counter += 4) + { + HWREG(ui32Base + SHAMD5_O_DATA_0_IN + ui32Counter) = *pui32Src++; + } +} + +//***************************************************************************** +// +//! Reads the result of a hashing operation. +//! +//! \param ui32Base is the base address of the SHA/MD5 module. +//! \param pui32Dest is the pointer to the 16-word array of data that will be +//! written. +//! +//! This function does not return until the module is ready to accept data and +//! the data has been written. +//! +//! \return None. +// +//***************************************************************************** +void +SHAMD5ResultRead(uint32_t ui32Base, uint32_t *pui32Dest) +{ + uint32_t ui32Idx, ui32Count; + + // + // Check the arguments. + // + ASSERT(ui32Base == SHAMD5_BASE); + + // + // Determine the number of bytes in the result, based on the hash type. + // + switch(HWREG(ui32Base + SHAMD5_O_MODE) & SHAMD5_MODE_ALGO_M) + { + // + // The MD5 hash is being used. + // + case SHAMD5_MODE_ALGO_MD5: + { + // + // There are 16 bytes in the MD5 hash. + // + ui32Count = 16; + + // + // Done. + // + break; + } + + // + // The SHA-1 hash is being used. + // + case SHAMD5_MODE_ALGO_SHA1: + { + // + // There are 20 bytes in the SHA-1 hash. + // + ui32Count = 20; + + // + // Done. + // + break; + } + + // + // The SHA-224 hash is being used. + // + case SHAMD5_MODE_ALGO_SHA224: + { + // + // There are 28 bytes in the SHA-224 hash. + // + ui32Count = 28; + + // + // Done. + // + break; + } + + // + // The SHA-256 hash is being used. + // + case SHAMD5_MODE_ALGO_SHA256: + { + // + // There are 32 bytes in the SHA-256 hash. + // + ui32Count = 32; + + // + // Done. + // + break; + } + + // + // The hash type is not recognized. + // + default: + { + // + // Return without reading a result since the hardware appears to be + // misconfigured. + // + return; + } + } + + // + // Read the hash result. + // + for(ui32Idx = 0; ui32Idx < ui32Count; ui32Idx += 4) + { + *pui32Dest++ = HWREG(ui32Base + SHAMD5_O_IDIGEST_A + ui32Idx); + } +} + +//***************************************************************************** +// +//! Writes multiple words of data into the SHA/MD5 data registers. +//! +//! \param ui32Base is the base address of the SHA/MD5 module. +//! \param pui32DataSrc is a pointer to an array of data to be written. +//! \param ui32DataLength is the length of the data to be written in bytes. +//! +//! This function writes a variable number of words into the SHA/MD5 data +//! registers. The function waits for each block of data to be processed +//! before another is written. The \e ui32DataLength parameter must be a +//! multiple of 4 to fall on a word boundry. +//! +//! \note This function is used by SHAMD5DataProcess() and SHAMD5HMACProcess() +//! to process data. +//! +//! \return None. +// +//***************************************************************************** +static void +_SHAMD5DataWriteMultiple(uint32_t ui32Base, uint32_t *pui32DataSrc, + uint32_t ui32DataLength) +{ + uint32_t ui32Idx, ui32Count; + + // + // Check the arguments. + // + ASSERT(ui32Base == SHAMD5_BASE); + + // + // Calculate the number of blocks of data. + // + ui32Count = ui32DataLength / 64; + + // + // Loop through all the blocks and write them into the data registers + // making sure to block additional operations until we can write the + // next 16 words. + // + for(ui32Idx = 0; ui32Idx < ui32Count; ui32Idx++) + { + // + // Write the block of data. + // + SHAMD5DataWrite(ui32Base, pui32DataSrc); + + // + // Increment the pointer to next block of data. + // + pui32DataSrc += 16; + } + + // + // Calculate the remaining bytes of data that don't make up a full block. + // + ui32Count = ui32DataLength % 64; + + // + // If there are bytes that do not make up a whole block, then + // write them separately. + // + if(ui32Count) + { + // + // Wait until the engine has finished processing the previous block. + // + while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & + SHAMD5_INT_INPUT_READY) == 0) + { + } + + // + // Loop through the remaining words. + // + for(ui32Idx = 0; ui32Idx < ui32Count; ui32Idx += 4) + { + // + // Write the word into the data register. + // + HWREG(ui32Base + SHAMD5_O_DATA_0_IN + ui32Idx) = *pui32DataSrc++; + } + } +} + +//***************************************************************************** +// +//! Compute a hash using the SHA/MD5 module. +//! +//! \param ui32Base is the base address of the SHA/MD5 module. +//! \param pui32DataSrc is a pointer to an array of data that contains the +//! data that will be hashed. +//! \param ui32DataLength specifies the length of the data to be hashed in +//! bytes. +//! \param pui32HashResult is a pointer to an array that holds the result +//! of the hashing operation. +//! +//! This function computes the hash of an array of data using the SHA/MD5 +//! module. +//! +//! The length of the hash result is dependent on the algorithm that is in use. +//! The following table shows the correct array size for each algorithm: +//! +//! ----------------------------------------- +//! | Algorithm | Number of Words in Result | +//! ----------------------------------------- +//! | MD5 | 4 Words (128 bits) | +//! | SHA-1 | 5 Words (160 bits) | +//! | SHA-224 | 7 Words (224 bits) | +//! | SHA-256 | 8 Words (256 bits) | +//! ----------------------------------------- +//! +//! \return None +// +//***************************************************************************** +void +SHAMD5DataProcess(uint32_t ui32Base, uint32_t *pui32DataSrc, + uint32_t ui32DataLength, uint32_t *pui32HashResult) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == SHAMD5_BASE); + ASSERT((ui32DataLength % 64) == 0); + + // + // Wait for the context to be ready before writing the mode. + // + while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_CONTEXT_READY) == + 0) + { + } + + // + // Write the length. + // + SHAMD5HashLengthSet(ui32Base, ui32DataLength); + + // + // Write the data. + // + _SHAMD5DataWriteMultiple(ui32Base, pui32DataSrc, ui32DataLength); + + // + // Wait for the output to be ready. + // + while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_OUTPUT_READY) == + 0) + { + } + + // + // Read the result. + // + SHAMD5ResultRead(ui32Base, pui32HashResult); +} + +//***************************************************************************** +// +//! Compute a HMAC with key pre-processing using the SHA/MD5 module. +//! +//! \param ui32Base is the base address of the SHA/MD5 module. +//! \param pui32DataSrc is a pointer to an array of data that contains the +//! data that is to be hashed. +//! \param ui32DataLength specifies the length of the data to be hashed in +//! bytes. +//! \param pui32HashResult is a pointer to an array that holds the result +//! of the hashing operation. +//! +//! This function computes a HMAC with the given data using the SHA/MD5 +//! module with a preprocessed key. +//! +//! The length of the hash result is dependent on the algorithm that is +//! selected with the \e ui32Algo argument. The following table shows the +//! correct array size for each algorithm: +//! +//! ----------------------------------------- +//! | Algorithm | Number of Words in Result | +//! ----------------------------------------- +//! | MD5 | 4 Words (128 bits) | +//! | SHA-1 | 5 Words (160 bits) | +//! | SHA-224 | 7 Words (224 bits) | +//! | SHA-256 | 8 Words (256 bits) | +//! ----------------------------------------- +//! +//! \return None +// +//***************************************************************************** +void +SHAMD5HMACProcess(uint32_t ui32Base, uint32_t *pui32DataSrc, + uint32_t ui32DataLength, uint32_t *pui32HashResult) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == SHAMD5_BASE); + + // + // Wait for the context to be ready before writing the mode. + // + while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_CONTEXT_READY) == + 0) + { + } + + // + // Write the length. + // + SHAMD5HashLengthSet(ui32Base, ui32DataLength); + + // + // Write the data in the registers. + // + _SHAMD5DataWriteMultiple(ui32Base, pui32DataSrc, ui32DataLength); + + // + // Wait for the output to be ready. + // + while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_OUTPUT_READY) == + 0) + { + } + + // + // Read the result. + // + SHAMD5ResultRead(ui32Base, pui32HashResult); +} + +//***************************************************************************** +// +//! Process an HMAC key using the SHA/MD5 module. +//! +//! \param ui32Base is the base address of the SHA/MD5 module. +//! \param pui32Key is a pointer to an array that contains the key to be +//! processed. +//! \param pui32PPKey is the pointer to the array that contains the +//! pre-processed key. +//! +//! This function processes an HMAC key using the SHA/MD5. The resultant +//! pre-processed key can then be used with later HMAC operations to speed +//! processing time. +//! +//! The \e pui32Key array must be 16 words (512 bits) long. If the key is less +//! than 512 bits, it must be padded with zeros. The \e pui32PPKey array must +//! each be 16 words (512 bits) long. +//! +//! \return None +// +//***************************************************************************** +void +SHAMD5HMACPPKeyGenerate(uint32_t ui32Base, uint32_t *pui32Key, + uint32_t *pui32PPKey) +{ + uint32_t ui32Index; + + // + // Check the arguments. + // + ASSERT(ui32Base == SHAMD5_BASE); + + // + // Wait for the context to be ready before writing the mode. + // + while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_CONTEXT_READY) == + 0) + { + } + + // + // Write the HMAC key. + // + for(ui32Index = 0; ui32Index < 64; ui32Index += 4) + { + HWREG(ui32Base + SHAMD5_O_ODIGEST_A + ui32Index) = *pui32Key++; + } + + // + // Set the flag to cause the HMAC key to be pre-processed. + // + HWREG(ui32Base + SHAMD5_O_MODE) |= SHAMD5_MODE_HMAC_KEY_PROC; + + // + // Set the length to zero to start the HMAC key pre-processing. + // + HWREG(ui32Base + SHAMD5_O_LENGTH) = 0; + + // + // Wait for key to be processed. + // + while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_OUTPUT_READY) == + 0) + { + } + + // + // Read the pre-processed key from the SHA/MD5 module. + // + for(ui32Index = 0; ui32Index < 64; ui32Index += 4) + { + *pui32PPKey++ = HWREG(ui32Base + SHAMD5_O_ODIGEST_A + ui32Index); + } +} + +//***************************************************************************** +// +//! Writes an HMAC key to the digest registers in the SHA/MD5 module. +//! +//! \param ui32Base is the base address of the SHA/MD5 module. +//! \param pui32Src is the pointer to the 16-word array of the HMAC key. +//! +//! This function is used to write HMAC key to the digest registers for +//! key preprocessing. The size of pui32Src must be 512 bytes. If the key is +//! less than 512 bytes, then it must be padded with zeros. +//! +//! \note It is recommended to use the SHAMD5IntStatus() function to check +//! whether the context is ready before writing the key. +//! +//! \return None +// +//***************************************************************************** +void +SHAMD5HMACKeySet(uint32_t ui32Base, uint32_t *pui32Src) +{ + uint32_t ui32Idx; + + // + // Check the arguments. + // + ASSERT(ui32Base == SHAMD5_BASE); + + // + // Write the key to the digest registers. + // + for(ui32Idx = 0; ui32Idx < 64; ui32Idx += 4) + { + HWREG(ui32Base + SHAMD5_O_ODIGEST_A + ui32Idx) = *pui32Src++; + } + + // + // Configure the SHA engine for HMAC operation. + // + HWREG(ui32Base + SHAMD5_O_MODE) |= (SHAMD5_MODE_HMAC_OUTER_HASH | + SHAMD5_MODE_HMAC_KEY_PROC | + SHAMD5_MODE_CLOSE_HASH); +} + +//***************************************************************************** +// +//! Writes a pre-processed HMAC key to the digest registers in the SHA/MD5 +//! module. +//! +//! \param ui32Base is the base address of the SHA/MD5 module. +//! \param pui32Src is the pointer to the 16-word array of the HMAC key. +//! +//! This function is used to write HMAC key to the digest registers for +//! key preprocessing. The size of pui32Src must be 512 bytes. If the key is +//! less than 512 bytes, then it must be padded with zeros. +//! +//! \note It is recommended to use the SHAMD5IntStatus() function to check +//! whether the context is ready before writing the key. +//! +//! \return None +// +//***************************************************************************** +void +SHAMD5HMACPPKeySet(uint32_t ui32Base, uint32_t *pui32Src) +{ + uint32_t ui32Idx; + + // + // Check the arguments. + // + ASSERT(ui32Base == SHAMD5_BASE); + + // + // Write the key to the digest registers. + // + for(ui32Idx = 0; ui32Idx < 64; ui32Idx += 4) + { + HWREG(ui32Base + SHAMD5_O_ODIGEST_A + ui32Idx) = *pui32Src++; + } + + // + // Configure the SHA engine to continue the HMAC. + // + HWREG(ui32Base + SHAMD5_O_MODE) |= (SHAMD5_MODE_HMAC_OUTER_HASH | + SHAMD5_MODE_CLOSE_HASH); + + // + // Write the digest count to 64 to account for the preprocessed key. + // + HWREG(ui32Base + SHAMD5_O_DIGEST_COUNT) = 64; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/ssi.c b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/ssi.c new file mode 100644 index 0000000000000000000000000000000000000000..cf7a2d3bc2aa087a837b840ebc0c849f4e9aa8c6 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/ssi.c @@ -0,0 +1,1150 @@ +//***************************************************************************** +// +// ssi.c - Driver for Synchronous Serial Interface. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup ssi_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_ssi.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/ssi.h" + +//***************************************************************************** +// +// A mapping of timer base address to interrupt number. +// +//***************************************************************************** +static const uint32_t g_ppui32SSIIntMap[][2] = +{ + { SSI0_BASE, INT_SSI0_TM4C123 }, + { SSI1_BASE, INT_SSI1_TM4C123 }, + { SSI2_BASE, INT_SSI2_TM4C123 }, + { SSI3_BASE, INT_SSI3_TM4C123 }, +}; +static const uint_fast8_t g_ui8SSIIntMapRows = + sizeof(g_ppui32SSIIntMap) / sizeof(g_ppui32SSIIntMap[0]); + +static const uint32_t g_ppui32SSIIntMapSnowflake[][2] = +{ + { SSI0_BASE, INT_SSI0_TM4C129 }, + { SSI1_BASE, INT_SSI1_TM4C129 }, + { SSI2_BASE, INT_SSI2_TM4C129 }, + { SSI3_BASE, INT_SSI3_TM4C129 }, +}; +static const uint_fast8_t g_ui8SSIIntMapSnowflakeRows = + sizeof(g_ppui32SSIIntMapSnowflake) / sizeof(g_ppui32SSIIntMapSnowflake[0]); + +//***************************************************************************** +// +//! \internal +//! Checks an SSI base address. +//! +//! \param ui32Base specifies the SSI module base address. +//! +//! This function determines if a SSI module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static bool +_SSIBaseValid(uint32_t ui32Base) +{ + return((ui32Base == SSI0_BASE) || (ui32Base == SSI1_BASE) || + (ui32Base == SSI2_BASE) || (ui32Base == SSI3_BASE)); +} +#endif + +//***************************************************************************** +// +//! Returns the interrupt number of SSI module . +//! +//! \param ui32Base is the base address of the SSI module. +//! +//! This function returns the interrupt number for the SSI module with the base +//! address passed in the \e ui32Base parameter. +//! +//! \return Returns an SSI interrupt number, or 0 if the interrupt does not +//! exist. +// +//***************************************************************************** +static uint32_t +_SSIIntNumberGet(uint32_t ui32Base) +{ + uint_fast8_t ui8Idx, ui8Rows; + const uint32_t (*ppui32SSIIntMap)[2]; + + // + // Check the arguments. + // + ASSERT(_SSIBaseValid(ui32Base)); + + ppui32SSIIntMap = g_ppui32SSIIntMap; + ui8Rows = g_ui8SSIIntMapRows; + + if(CLASS_IS_TM4C129) + { + ppui32SSIIntMap = g_ppui32SSIIntMapSnowflake; + ui8Rows = g_ui8SSIIntMapSnowflakeRows; + } + + // + // Loop through the table that maps SSI base addresses to interrupt + // numbers. + // + for(ui8Idx = 0; ui8Idx < ui8Rows; ui8Idx++) + { + // + // See if this base address matches. + // + if(ppui32SSIIntMap[ui8Idx][0] == ui32Base) + { + // + // Return the corresponding interrupt number. + // + return(ppui32SSIIntMap[ui8Idx][1]); + } + } + + // + // The base address could not be found, so return an error. + // + return(0); +} + +//***************************************************************************** +// +//! Configures the synchronous serial interface. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param ui32SSIClk is the rate of the clock supplied to the SSI module. +//! \param ui32Protocol specifies the data transfer protocol. +//! \param ui32Mode specifies the mode of operation. +//! \param ui32BitRate specifies the clock rate. +//! \param ui32DataWidth specifies number of bits transferred per frame. +//! +//! This function configures the synchronous serial interface. It sets +//! the SSI protocol, mode of operation, bit rate, and data width. +//! +//! The \e ui32Protocol parameter defines the data frame format. The +//! \e ui32Protocol parameter can be one of the following values: +//! \b SSI_FRF_MOTO_MODE_0, \b SSI_FRF_MOTO_MODE_1, \b SSI_FRF_MOTO_MODE_2, +//! \b SSI_FRF_MOTO_MODE_3, \b SSI_FRF_TI, or \b SSI_FRF_NMW. Note that +//! the \b SSI_FRF_NMW option is only available on some devices. Refer to the +//! device data sheet to determine if the Microwire format is supported on +//! a particular device. The Motorola frame formats encode the following +//! polarity and phase configurations: +//! +//! 
+//! Polarity Phase       Mode
+//!   0       0   SSI_FRF_MOTO_MODE_0
+//!   0       1   SSI_FRF_MOTO_MODE_1
+//!   1       0   SSI_FRF_MOTO_MODE_2
+//!   1       1   SSI_FRF_MOTO_MODE_3
+//!
+//! +//! The \e ui32Mode parameter defines the operating mode of the SSI module. +//! The SSI module can operate as a master or slave; if it is a slave, the SSI +//! can be configured to disable output on its serial output line. The +//! \e ui32Mode parameter can be one of the following values: +//! \b SSI_MODE_MASTER, \b SSI_MODE_SLAVE, or \b SSI_MODE_SLAVE_OD. +//! +//! The \e ui32BitRate parameter defines the bit rate for the SSI. This bit +//! rate must satisfy the following clock ratio criteria: +//! +//! - FSSI >= 2 * bit rate (master mode) +//! - FSSI >= 12 * bit rate (slave modes) +//! +//! where FSSI is the frequency of the clock supplied to the SSI module. Note +//! that there are frequency limits for FSSI that are described in the Bit Rate +//! Generation section of the SSI chapter in the data sheet. +//! +//! The \e ui32DataWidth parameter defines the width of the data transfers and +//! can be a value between 4 and 16, inclusive. +//! +//! The peripheral clock is the same as the processor clock. The frequency of +//! the system clock is the value returned by SysCtlClockGet() for TM4C123x +//! devices or the value returned by SysCtlClockFreqSet() for TM4C129x devices, +//! or it can be explicitly hard coded if it is constant and known (to save the +//! code/execution overhead of a call to SysCtlClockGet() or fetch of the +//! variable call holding the return value of SysCtlClockFreqSet()). +//! +//! \return None. +// +//***************************************************************************** +void +SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk, + uint32_t ui32Protocol, uint32_t ui32Mode, + uint32_t ui32BitRate, uint32_t ui32DataWidth) +{ + uint32_t ui32MaxBitRate; + uint32_t ui32RegVal; + uint32_t ui32PreDiv; + uint32_t ui32SCR; + uint32_t ui32SPH_SPO; + + // + // Check the arguments. + // + ASSERT(_SSIBaseValid(ui32Base)); + ASSERT((ui32Protocol == SSI_FRF_MOTO_MODE_0) || + (ui32Protocol == SSI_FRF_MOTO_MODE_1) || + (ui32Protocol == SSI_FRF_MOTO_MODE_2) || + (ui32Protocol == SSI_FRF_MOTO_MODE_3) || + (ui32Protocol == SSI_FRF_TI) || + (ui32Protocol == SSI_FRF_NMW)); + ASSERT((ui32Mode == SSI_MODE_MASTER) || + (ui32Mode == SSI_MODE_SLAVE)); + ASSERT(((ui32Mode == SSI_MODE_MASTER) && + (ui32BitRate <= (ui32SSIClk / 2))) || + ((ui32Mode != SSI_MODE_MASTER) && + (ui32BitRate <= (ui32SSIClk / 12)))); + ASSERT((ui32SSIClk / ui32BitRate) <= (254 * 256)); + ASSERT((ui32DataWidth >= 4) && (ui32DataWidth <= 16)); + + // + // Set the mode. + // + ui32RegVal = (ui32Mode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS; + HWREG(ui32Base + SSI_O_CR1) = ui32RegVal; + + // + // Set the clock predivider. + // + ui32MaxBitRate = ui32SSIClk / ui32BitRate; + ui32PreDiv = 0; + do + { + ui32PreDiv += 2; + ui32SCR = (ui32MaxBitRate / ui32PreDiv) - 1; + } + while(ui32SCR > 255); + HWREG(ui32Base + SSI_O_CPSR) = ui32PreDiv; + + // + // Set protocol and clock rate. + // + ui32SPH_SPO = (ui32Protocol & 3) << 6; + ui32Protocol &= SSI_CR0_FRF_M; + ui32RegVal = (ui32SCR << 8) | ui32SPH_SPO | ui32Protocol | + (ui32DataWidth - 1); + HWREG(ui32Base + SSI_O_CR0) = ui32RegVal; +} + +//***************************************************************************** +// +//! Enables the synchronous serial interface. +//! +//! \param ui32Base specifies the SSI module base address. +//! +//! This function enables operation of the synchronous serial interface. The +//! synchronous serial interface must be configured before it is enabled. +//! +//! \return None. +// +//***************************************************************************** +void +SSIEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_SSIBaseValid(ui32Base)); + + // + // Read-modify-write the enable bit. + // + HWREG(ui32Base + SSI_O_CR1) |= SSI_CR1_SSE; +} + +//***************************************************************************** +// +//! Disables the synchronous serial interface. +//! +//! \param ui32Base specifies the SSI module base address. +//! +//! This function disables operation of the synchronous serial interface. +//! +//! \return None. +// +//***************************************************************************** +void +SSIDisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_SSIBaseValid(ui32Base)); + + // + // Read-modify-write the enable bit. + // + HWREG(ui32Base + SSI_O_CR1) &= ~(SSI_CR1_SSE); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the synchronous serial interface. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param pfnHandler is a pointer to the function to be called when the +//! synchronous serial interface interrupt occurs. +//! +//! This function registers the handler to be called when an SSI interrupt +//! occurs. This function enables the global interrupt in the interrupt +//! controller; specific SSI interrupts must be enabled via SSIIntEnable(). If +//! necessary, it is the interrupt handler's responsibility to clear the +//! interrupt source via SSIIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +SSIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT(_SSIBaseValid(ui32Base)); + + // + // Determine the interrupt number based on the SSI module. + // + ui32Int = _SSIIntNumberGet(ui32Base); + + ASSERT(ui32Int != 0); + + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(ui32Int, pfnHandler); + + // + // Enable the synchronous serial interface interrupt. + // + IntEnable(ui32Int); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the synchronous serial interface. +//! +//! \param ui32Base specifies the SSI module base address. +//! +//! This function clears the handler to be called when an SSI interrupt +//! occurs. This function also masks off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +SSIIntUnregister(uint32_t ui32Base) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT(_SSIBaseValid(ui32Base)); + + // + // Determine the interrupt number based on the SSI module. + // + ui32Int = _SSIIntNumberGet(ui32Base); + + ASSERT(ui32Int != 0); + + // + // Disable the interrupt. + // + IntDisable(ui32Int); + + // + // Unregister the interrupt handler. + // + IntUnregister(ui32Int); +} + +//***************************************************************************** +// +//! Enables individual SSI interrupt sources. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated SSI interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. The \e ui32IntFlags +//! parameter can be any of the \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, or +//! \b SSI_RXOR values. +//! +//! \return None. +// +//***************************************************************************** +void +SSIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(_SSIBaseValid(ui32Base)); + + // + // Enable the specified interrupts. + // + HWREG(ui32Base + SSI_O_IM) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! Disables individual SSI interrupt sources. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be disabled. +//! +//! This function disables the indicated SSI interrupt sources. The +//! \e ui32IntFlags parameter can be any of the \b SSI_TXFF, \b SSI_RXFF, +//! \b SSI_RXTO, or \b SSI_RXOR values. +//! +//! \return None. +// +//***************************************************************************** +void +SSIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(_SSIBaseValid(ui32Base)); + + // + // Disable the specified interrupts. + // + HWREG(ui32Base + SSI_O_IM) &= ~(ui32IntFlags); +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param bMasked is \b false if the raw interrupt status is required or +//! \b true if the masked interrupt status is required. +//! +//! This function returns the interrupt status for the SSI module. Either the +//! raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, and \b SSI_RXOR. +// +//***************************************************************************** +uint32_t +SSIIntStatus(uint32_t ui32Base, bool bMasked) +{ + // + // Check the arguments. + // + ASSERT(_SSIBaseValid(ui32Base)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ui32Base + SSI_O_MIS)); + } + else + { + return(HWREG(ui32Base + SSI_O_RIS)); + } +} + +//***************************************************************************** +// +//! Clears SSI interrupt sources. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! This function clears the specified SSI interrupt sources so that they no +//! longer assert. This function must be called in the interrupt handler to +//! keep the interrupts from being triggered again immediately upon exit. The +//! \e ui32IntFlags parameter can consist of either or both the \b SSI_RXTO and +//! \b SSI_RXOR values. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +SSIIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(_SSIBaseValid(ui32Base)); + + // + // Clear the requested interrupt sources. + // + HWREG(ui32Base + SSI_O_ICR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! Puts a data element into the SSI transmit FIFO. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param ui32Data is the data to be transmitted over the SSI interface. +//! +//! This function places the supplied data into the transmit FIFO of the +//! specified SSI module. If there is no space available in the transmit FIFO, +//! this function waits until there is space available before returning. +//! +//! \note The upper 32 - N bits of \e ui32Data are discarded by the hardware, +//! where N is the data width as configured by SSIConfigSetExpClk(). For +//! example, if the interface is configured for 8-bit data width, the upper 24 +//! bits of \e ui32Data are discarded. +//! +//! \return None. +// +//***************************************************************************** +void +SSIDataPut(uint32_t ui32Base, uint32_t ui32Data) +{ + // + // Check the arguments. + // + ASSERT(_SSIBaseValid(ui32Base)); + ASSERT((ui32Data & (0xfffffffe << (HWREG(ui32Base + SSI_O_CR0) & + SSI_CR0_DSS_M))) == 0); + + // + // Wait until there is space. + // + while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF)) + { + } + + // + // Write the data to the SSI. + // + HWREG(ui32Base + SSI_O_DR) = ui32Data; +} + +//***************************************************************************** +// +//! Puts a data element into the SSI transmit FIFO. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param ui32Data is the data to be transmitted over the SSI interface. +//! +//! This function places the supplied data into the transmit FIFO of the +//! specified SSI module. If there is no space in the FIFO, then this function +//! returns a zero. +//! +//! \note The upper 32 - N bits of \e ui32Data are discarded by the hardware, +//! where N is the data width as configured by SSIConfigSetExpClk(). For +//! example, if the interface is configured for 8-bit data width, the upper 24 +//! bits of \e ui32Data are discarded. +//! +//! \return Returns the number of elements written to the SSI transmit FIFO. +// +//***************************************************************************** +int32_t +SSIDataPutNonBlocking(uint32_t ui32Base, uint32_t ui32Data) +{ + // + // Check the arguments. + // + ASSERT(_SSIBaseValid(ui32Base)); + ASSERT((ui32Data & (0xfffffffe << (HWREG(ui32Base + SSI_O_CR0) & + SSI_CR0_DSS_M))) == 0); + + // + // Check for space to write. + // + if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF) + { + HWREG(ui32Base + SSI_O_DR) = ui32Data; + return(1); + } + else + { + return(0); + } +} + +//***************************************************************************** +// +//! Gets a data element from the SSI receive FIFO. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param pui32Data is a pointer to a storage location for data that was +//! received over the SSI interface. +//! +//! This function gets received data from the receive FIFO of the specified +//! SSI module and places that data into the location specified by the +//! \e pui32Data parameter. If there is no data available, this function waits +//! until data is received before returning. +//! +//! \note Only the lower N bits of the value written to \e pui32Data contain +//! valid data, where N is the data width as configured by +//! SSIConfigSetExpClk(). For example, if the interface is configured for +//! 8-bit data width, only the lower 8 bits of the value written to +//! \e pui32Data contain valid data. +//! +//! \return None. +// +//***************************************************************************** +void +SSIDataGet(uint32_t ui32Base, uint32_t *pui32Data) +{ + // + // Check the arguments. + // + ASSERT(_SSIBaseValid(ui32Base)); + + // + // Wait until there is data to be read. + // + while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_RNE)) + { + } + + // + // Read data from SSI. + // + *pui32Data = HWREG(ui32Base + SSI_O_DR); +} + +//***************************************************************************** +// +//! Gets a data element from the SSI receive FIFO. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param pui32Data is a pointer to a storage location for data that was +//! received over the SSI interface. +//! +//! This function gets received data from the receive FIFO of the specified SSI +//! module and places that data into the location specified by the \e ui32Data +//! parameter. If there is no data in the FIFO, then this function returns a +//! zero. +//! +//! \note Only the lower N bits of the value written to \e pui32Data contain +//! valid data, where N is the data width as configured by +//! SSIConfigSetExpClk(). For example, if the interface is configured for +//! 8-bit data width, only the lower 8 bits of the value written to +//! \e pui32Data contain valid data. +//! +//! \return Returns the number of elements read from the SSI receive FIFO. +// +//***************************************************************************** +int32_t +SSIDataGetNonBlocking(uint32_t ui32Base, uint32_t *pui32Data) +{ + // + // Check the arguments. + // + ASSERT(_SSIBaseValid(ui32Base)); + + // + // Check for data to read. + // + if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_RNE) + { + *pui32Data = HWREG(ui32Base + SSI_O_DR); + return(1); + } + else + { + return(0); + } +} + +//***************************************************************************** +// +//! Enables SSI DMA operation. +//! +//! \param ui32Base is the base address of the SSI module. +//! \param ui32DMAFlags is a bit mask of the DMA features to enable. +//! +//! This function enables the specified SSI DMA features. The SSI can be +//! configured to use DMA for transmit and/or receive data transfers. +//! The \e ui32DMAFlags parameter is the logical OR of any of the following +//! values: +//! +//! - SSI_DMA_RX - enable DMA for receive +//! - SSI_DMA_TX - enable DMA for transmit +//! +//! \note The uDMA controller must also be set up before DMA can be used +//! with the SSI. +//! +//! \return None. +// +//***************************************************************************** +void +SSIDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags) +{ + // + // Check the arguments. + // + ASSERT(_SSIBaseValid(ui32Base)); + + // + // Set the requested bits in the SSI DMA control register. + // + HWREG(ui32Base + SSI_O_DMACTL) |= ui32DMAFlags; +} + +//***************************************************************************** +// +//! Disables SSI DMA operation. +//! +//! \param ui32Base is the base address of the SSI module. +//! \param ui32DMAFlags is a bit mask of the DMA features to disable. +//! +//! This function is used to disable SSI DMA features that were enabled +//! by SSIDMAEnable(). The specified SSI DMA features are disabled. The +//! \e ui32DMAFlags parameter is the logical OR of any of the following values: +//! +//! - SSI_DMA_RX - disable DMA for receive +//! - SSI_DMA_TX - disable DMA for transmit +//! +//! \return None. +// +//***************************************************************************** +void +SSIDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags) +{ + // + // Check the arguments. + // + ASSERT(_SSIBaseValid(ui32Base)); + + // + // Clear the requested bits in the SSI DMA control register. + // + HWREG(ui32Base + SSI_O_DMACTL) &= ~ui32DMAFlags; +} + +//***************************************************************************** +// +//! Determines whether the SSI transmitter is busy or not. +//! +//! \param ui32Base is the base address of the SSI module. +//! +//! This function allows the caller to determine whether all transmitted bytes +//! have cleared the transmitter hardware. If \b false is returned, then the +//! transmit FIFO is empty and all bits of the last transmitted word have left +//! the hardware shift register. +//! +//! \return Returns \b true if the SSI is transmitting or \b false if all +//! transmissions are complete. +// +//***************************************************************************** +bool +SSIBusy(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_SSIBaseValid(ui32Base)); + + // + // Determine if the SSI is busy. + // + return((HWREG(ui32Base + SSI_O_SR) & SSI_SR_BSY) ? true : false); +} + +//***************************************************************************** +// +//! Sets the data clock source for the specified SSI peripheral. +//! +//! \param ui32Base is the base address of the SSI module. +//! \param ui32Source is the baud clock source for the SSI. +//! +//! This function allows the baud clock source for the SSI to be selected. +//! The possible clock source are the system clock (\b SSI_CLOCK_SYSTEM) or +//! the precision internal oscillator (\b SSI_CLOCK_PIOSC). +//! +//! Changing the baud clock source changes the data rate generated by the +//! SSI. Therefore, the data rate should be reconfigured after any change to +//! the SSI clock source. +//! +//! \note The ability to specify the SSI baud clock source varies with the +//! Tiva part and SSI in use. Please consult the data sheet for the part +//! in use to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +SSIClockSourceSet(uint32_t ui32Base, uint32_t ui32Source) +{ + // + // Check the arguments. + // + ASSERT(_SSIBaseValid(ui32Base)); + ASSERT((ui32Source == SSI_CLOCK_SYSTEM) || + (ui32Source == SSI_CLOCK_PIOSC)); + + // + // Set the SSI clock source. + // + HWREG(ui32Base + SSI_O_CC) = ui32Source; +} + +//***************************************************************************** +// +//! Gets the data clock source for the specified SSI peripheral. +//! +//! \param ui32Base is the base address of the SSI module. +//! +//! This function returns the data clock source for the specified SSI. +//! +//! \note The ability to specify the SSI data clock source varies with the +//! Tiva part and SSI in use. Please consult the data sheet for the part +//! in use to determine whether this support is available. +//! +//! \return Returns the current clock source, which is either +//! \b SSI_CLOCK_SYSTEM or \b SSI_CLOCK_PIOSC. +// +//***************************************************************************** +uint32_t +SSIClockSourceGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_SSIBaseValid(ui32Base)); + + // + // Return the SSI clock source. + // + return(HWREG(ui32Base + SSI_O_CC)); +} + +//***************************************************************************** +// +//! Selects the advanced mode of operation for the SSI module. +//! +//! \param ui32Base is the base address of the SSI module. +//! \param ui32Mode is the mode of operation to use. +//! +//! This function selects the mode of operation for the SSI module, which is +//! needed when using the advanced operation modes (Bi- or Quad-SPI). One of +//! the following modes can be selected: +//! +//! - \b SSI_ADV_MODE_LEGACY - Disables the advanced modes of operation, +//! resulting in legacy, or backwards-compatible, operation. When this mode +//! is selected, it is not valid to switch to Bi- or Quad-SPI operation. +//! This mode is the default. +//! - \b SSI_ADV_MODE_WRITE - The advanced mode of operation where data is only +//! written to the slave; any data clocked in via the \b SSIRx pin is thrown +//! away (instead of being placed into the SSI Rx FIFO). +//! - \b SSI_ADV_MODE_READ_WRITE - The advanced mode of operation where data is +//! written to and read from the slave; this mode is the same as +//! \b SSI_ADV_MODE_LEGACY but allows transitions to Bi- or Quad-SPI +//! operation. +//! - \b SSI_ADV_MODE_BI_READ - The advanced mode of operation where data is +//! read from the slave in Bi-SPI mode, with two bits of data read on every +//! SSI clock. +//! - \b SSI_ADV_MODE_BI_WRITE - The advanced mode of operation where data is +//! written to the slave in Bi-SPI mode, with two bits of data written on +//! every SSI clock. +//! - \b SSI_ADV_MODE_QUAD_READ - The advanced mode of operation where data is +//! read from the slave in Quad-SPI mode, with four bits of data read on +//! every SSI clock. +//! - \b SSI_ADV_MODE_QUAD_WRITE - The advanced mode of operation where data is +//! written to the slave in Quad-SPI mode, with four bits of data written on +//! every SSI clock. +//! +//! The following mode transitions are valid (other transitions produce +//! undefined results): +//! +//! \verbatim +//! +----------+-------------------------------------------------------------+ +//! |FROM | TO | +//! | |Legacy|Write|Read Write|Bi Read|Bi Write|Quad Read|Quad Write| +//! +----------+------+-----+----------+-------+--------+---------+----------+ +//! |Legacy | yes | yes | yes | | | | | +//! |Write | yes | yes | yes | yes | yes | yes | yes | +//! |Read/Write| yes | yes | yes | yes | yes | yes | yes | +//! |Bi Read | | yes | yes | yes | yes | | | +//! |Bi write | | yes | yes | yes | yes | | | +//! |Quad read | | yes | yes | | | yes | yes | +//! |Quad write| | yes | yes | | | yes | yes | +//! +----------+------+-----+----------+-------+--------+---------+----------+ +//! \endverbatim +//! +//! When using an advanced mode of operation, the SSI module must have been +//! configured for eight data bits and the \b SSI_FRF_MOTO_MODE_0 protocol. +//! The advanced mode operation that is selected applies only to data newly +//! written into the FIFO; the data that is already present in the FIFO is +//! handled using the advanced mode of operation in effect when that data was +//! written. +//! +//! Switching into and out of legacy mode should only occur when the FIFO is +//! empty. +//! +//! \note The availability of the advanced mode of SSI operation varies with +//! the Tiva part and SSI in use. Please consult the data sheet for the +//! part in use to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +SSIAdvModeSet(uint32_t ui32Base, uint32_t ui32Mode) +{ + // + // Check the arguments. + // + ASSERT(_SSIBaseValid(ui32Base)); + ASSERT((ui32Mode == SSI_ADV_MODE_LEGACY) || + (ui32Mode == SSI_ADV_MODE_WRITE) || + (ui32Mode == SSI_ADV_MODE_READ_WRITE) || + (ui32Mode == SSI_ADV_MODE_BI_READ) || + (ui32Mode == SSI_ADV_MODE_BI_WRITE) || + (ui32Mode == SSI_ADV_MODE_QUAD_READ) || + (ui32Mode == SSI_ADV_MODE_QUAD_WRITE)); + + // + // Set the SSI mode of operation. + // + HWREG(ui32Base + SSI_O_CR1) = + ((HWREG(ui32Base + SSI_O_CR1) & ~(SSI_CR1_DIR | SSI_CR1_MODE_M)) | + ui32Mode); +} + +//***************************************************************************** +// +//! Puts a data element into the SSI transmit FIFO as the end of a frame. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param ui32Data is the data to be transmitted over the SSI interface. +//! +//! This function places the supplied data into the transmit FIFO of the +//! specified SSI module, marking it as the end of a frame. If there is no +//! space available in the transmit FIFO, this function waits until there is +//! space available before returning. After this byte is transmitted by the +//! SSI module, the FSS signal de-asserts for at least one SSI clock. +//! +//! \note The upper 24 bits of \e ui32Data are discarded by the hardware. +//! +//! \note The availability of the advanced mode of SSI operation varies with +//! the Tiva part and SSI in use. Please consult the data sheet for the +//! part in use to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +SSIAdvDataPutFrameEnd(uint32_t ui32Base, uint32_t ui32Data) +{ + // + // Check the arguments. + // + ASSERT(_SSIBaseValid(ui32Base)); + ASSERT((ui32Data & 0xff) == 0); + + // + // Wait until there is space. + // + while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF)) + { + } + + // + // Write the data to the SSI. + // + HWREG(ui32Base + SSI_O_CR1) |= SSI_CR1_EOM; + HWREG(ui32Base + SSI_O_DR) = ui32Data; +} + +//***************************************************************************** +// +//! Puts a data element into the SSI transmit FIFO as the end of a frame. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param ui32Data is the data to be transmitted over the SSI interface. +//! +//! This function places the supplied data into the transmit FIFO of the +//! specified SSI module, marking it as the end of a frame. After this byte is +//! transmitted by the SSI module, the FSS signal de-asserts for at least one +//! SSI clock. If there is no space in the FIFO, then this function returns a +//! zero. +//! +//! \note The upper 24 bits of \e ui32Data are discarded by the hardware. +//! +//! \note The availability of the advanced mode of SSI operation varies with +//! the Tiva part and SSI in use. Please consult the data sheet for the +//! part in use to determine whether this support is available. +//! +//! \return Returns the number of elements written to the SSI transmit FIFO. +// +//***************************************************************************** +int32_t +SSIAdvDataPutFrameEndNonBlocking(uint32_t ui32Base, uint32_t ui32Data) +{ + // + // Check the arguments. + // + ASSERT(_SSIBaseValid(ui32Base)); + ASSERT((ui32Data & 0xff) == 0); + + // + // Check for space to write. + // + if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF) + { + HWREG(ui32Base + SSI_O_CR1) |= SSI_CR1_EOM; + HWREG(ui32Base + SSI_O_DR) = ui32Data; + return(1); + } + else + { + return(0); + } +} + +//***************************************************************************** +// +//! Configures the SSI advanced mode to hold the SSIFss signal during the full +//! transfer. +//! +//! \param ui32Base is the base address of the SSI module. +//! +//! This function configures the SSI module to de-assert the SSIFss signal +//! during the entire data transfer when using one of the advanced modes +//! (instead of briefly de-asserting it after every byte). When using this +//! mode, SSIFss can be directly controlled via SSIAdvDataPutFrameEnd() and +//! SSIAdvDataPutFrameEndNonBlocking(). +//! +//! \note The availability of the advanced mode of SSI operation varies with +//! the Tiva part and SSI in use. Please consult the data sheet for the +//! part in use to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +SSIAdvFrameHoldEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_SSIBaseValid(ui32Base)); + + // + // Set the hold frame bit. + // + HWREG(ui32Base + SSI_O_CR1) |= SSI_CR1_FSSHLDFRM; +} + +//***************************************************************************** +// +//! Configures the SSI advanced mode to de-assert the SSIFss signal after every +//! byte transfer. +//! +//! \param ui32Base is the base address of the SSI module. +//! +//! This function configures the SSI module to de-assert the SSIFss signal +//! for one SSI clock cycle after every byte is transferred using one of the +//! advanced modes (instead of leaving it asserted for the entire transfer). +//! This mode is the default operation. +//! +//! \note The availability of the advanced mode of SSI operation varies with +//! the Tiva part and SSI in use. Please consult the data sheet for the +//! part in use to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +SSIAdvFrameHoldDisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_SSIBaseValid(ui32Base)); + + // + // Clear the hold frame bit. + // + HWREG(ui32Base + SSI_O_CR1) &= ~(SSI_CR1_FSSHLDFRM); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/sw_crc.c b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/sw_crc.c new file mode 100644 index 0000000000000000000000000000000000000000..0706c34d50da692516666a86324d856bff8571f1 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/sw_crc.c @@ -0,0 +1,770 @@ +//***************************************************************************** +// +// sw_crc.c - Software CRC functions. +// +// Copyright (c) 2010-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup sw_crc_api +//! @{ +// +//***************************************************************************** + +#include +#include "driverlib/sw_crc.h" + +//***************************************************************************** +// +// The CRC table for the polynomial C(x) = x^8 + x^2 + x + 1 (CRC-8-CCITT). +// +//***************************************************************************** +static const uint8_t g_pui8Crc8CCITT[256] = +{ + 0x00, 0x07, 0x0E, 0x09, 0x1C, 0x1B, 0x12, 0x15, + 0x38, 0x3F, 0x36, 0x31, 0x24, 0x23, 0x2A, 0x2D, + 0x70, 0x77, 0x7E, 0x79, 0x6C, 0x6B, 0x62, 0x65, + 0x48, 0x4F, 0x46, 0x41, 0x54, 0x53, 0x5A, 0x5D, + 0xE0, 0xE7, 0xEE, 0xE9, 0xFC, 0xFB, 0xF2, 0xF5, + 0xD8, 0xDF, 0xD6, 0xD1, 0xC4, 0xC3, 0xCA, 0xCD, + 0x90, 0x97, 0x9E, 0x99, 0x8C, 0x8B, 0x82, 0x85, + 0xA8, 0xAF, 0xA6, 0xA1, 0xB4, 0xB3, 0xBA, 0xBD, + 0xC7, 0xC0, 0xC9, 0xCE, 0xDB, 0xDC, 0xD5, 0xD2, + 0xFF, 0xF8, 0xF1, 0xF6, 0xE3, 0xE4, 0xED, 0xEA, + 0xB7, 0xB0, 0xB9, 0xBE, 0xAB, 0xAC, 0xA5, 0xA2, + 0x8F, 0x88, 0x81, 0x86, 0x93, 0x94, 0x9D, 0x9A, + 0x27, 0x20, 0x29, 0x2E, 0x3B, 0x3C, 0x35, 0x32, + 0x1F, 0x18, 0x11, 0x16, 0x03, 0x04, 0x0D, 0x0A, + 0x57, 0x50, 0x59, 0x5E, 0x4B, 0x4C, 0x45, 0x42, + 0x6F, 0x68, 0x61, 0x66, 0x73, 0x74, 0x7D, 0x7A, + 0x89, 0x8E, 0x87, 0x80, 0x95, 0x92, 0x9B, 0x9C, + 0xB1, 0xB6, 0xBF, 0xB8, 0xAD, 0xAA, 0xA3, 0xA4, + 0xF9, 0xFE, 0xF7, 0xF0, 0xE5, 0xE2, 0xEB, 0xEC, + 0xC1, 0xC6, 0xCF, 0xC8, 0xDD, 0xDA, 0xD3, 0xD4, + 0x69, 0x6E, 0x67, 0x60, 0x75, 0x72, 0x7B, 0x7C, + 0x51, 0x56, 0x5F, 0x58, 0x4D, 0x4A, 0x43, 0x44, + 0x19, 0x1E, 0x17, 0x10, 0x05, 0x02, 0x0B, 0x0C, + 0x21, 0x26, 0x2F, 0x28, 0x3D, 0x3A, 0x33, 0x34, + 0x4E, 0x49, 0x40, 0x47, 0x52, 0x55, 0x5C, 0x5B, + 0x76, 0x71, 0x78, 0x7F, 0x6A, 0x6D, 0x64, 0x63, + 0x3E, 0x39, 0x30, 0x37, 0x22, 0x25, 0x2C, 0x2B, + 0x06, 0x01, 0x08, 0x0F, 0x1A, 0x1D, 0x14, 0x13, + 0xAE, 0xA9, 0xA0, 0xA7, 0xB2, 0xB5, 0xBC, 0xBB, + 0x96, 0x91, 0x98, 0x9F, 0x8A, 0x8D, 0x84, 0x83, + 0xDE, 0xD9, 0xD0, 0xD7, 0xC2, 0xC5, 0xCC, 0xCB, + 0xE6, 0xE1, 0xE8, 0xEF, 0xFA, 0xFD, 0xF4, 0xF3 +}; + +//***************************************************************************** +// +// The CRC-16 table for the polynomial C(x) = x^16 + x^15 + x^2 + 1 (standard +// CRC-16, also known as CRC-16-IBM and CRC-16-ANSI). +// +//***************************************************************************** +static const uint16_t g_pui16Crc16[256] = +{ + 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241, + 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440, + 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40, + 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841, + 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40, + 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41, + 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641, + 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040, + 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240, + 0x3600, 0xF6C1, 0xF781, 0x3740, 0xF501, 0x35C0, 0x3480, 0xF441, + 0x3C00, 0xFCC1, 0xFD81, 0x3D40, 0xFF01, 0x3FC0, 0x3E80, 0xFE41, + 0xFA01, 0x3AC0, 0x3B80, 0xFB41, 0x3900, 0xF9C1, 0xF881, 0x3840, + 0x2800, 0xE8C1, 0xE981, 0x2940, 0xEB01, 0x2BC0, 0x2A80, 0xEA41, + 0xEE01, 0x2EC0, 0x2F80, 0xEF41, 0x2D00, 0xEDC1, 0xEC81, 0x2C40, + 0xE401, 0x24C0, 0x2580, 0xE541, 0x2700, 0xE7C1, 0xE681, 0x2640, + 0x2200, 0xE2C1, 0xE381, 0x2340, 0xE101, 0x21C0, 0x2080, 0xE041, + 0xA001, 0x60C0, 0x6180, 0xA141, 0x6300, 0xA3C1, 0xA281, 0x6240, + 0x6600, 0xA6C1, 0xA781, 0x6740, 0xA501, 0x65C0, 0x6480, 0xA441, + 0x6C00, 0xACC1, 0xAD81, 0x6D40, 0xAF01, 0x6FC0, 0x6E80, 0xAE41, + 0xAA01, 0x6AC0, 0x6B80, 0xAB41, 0x6900, 0xA9C1, 0xA881, 0x6840, + 0x7800, 0xB8C1, 0xB981, 0x7940, 0xBB01, 0x7BC0, 0x7A80, 0xBA41, + 0xBE01, 0x7EC0, 0x7F80, 0xBF41, 0x7D00, 0xBDC1, 0xBC81, 0x7C40, + 0xB401, 0x74C0, 0x7580, 0xB541, 0x7700, 0xB7C1, 0xB681, 0x7640, + 0x7200, 0xB2C1, 0xB381, 0x7340, 0xB101, 0x71C0, 0x7080, 0xB041, + 0x5000, 0x90C1, 0x9181, 0x5140, 0x9301, 0x53C0, 0x5280, 0x9241, + 0x9601, 0x56C0, 0x5780, 0x9741, 0x5500, 0x95C1, 0x9481, 0x5440, + 0x9C01, 0x5CC0, 0x5D80, 0x9D41, 0x5F00, 0x9FC1, 0x9E81, 0x5E40, + 0x5A00, 0x9AC1, 0x9B81, 0x5B40, 0x9901, 0x59C0, 0x5880, 0x9841, + 0x8801, 0x48C0, 0x4980, 0x8941, 0x4B00, 0x8BC1, 0x8A81, 0x4A40, + 0x4E00, 0x8EC1, 0x8F81, 0x4F40, 0x8D01, 0x4DC0, 0x4C80, 0x8C41, + 0x4400, 0x84C1, 0x8581, 0x4540, 0x8701, 0x47C0, 0x4680, 0x8641, + 0x8201, 0x42C0, 0x4380, 0x8341, 0x4100, 0x81C1, 0x8081, 0x4040 +}; + +//***************************************************************************** +// +// The CRC-32 table for the polynomial C(x) = x^32 + x^26 + x^23 + x^22 + +// x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1 (standard +// CRC32 as used in Ethernet, MPEG-2, PNG, etc.). +// +//***************************************************************************** +static const uint32_t g_pui32Crc32[] = +{ + 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, + 0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3, + 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, + 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, + 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de, + 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, + 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, + 0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5, + 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, + 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, + 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, + 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59, + 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, + 0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f, + 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, + 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, + 0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a, + 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433, + 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, + 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01, + 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, + 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, + 0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c, + 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65, + 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, + 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, + 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, + 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, + 0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086, + 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f, + 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, + 0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, + 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a, + 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, + 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8, + 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, + 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, + 0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7, + 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, + 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, + 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, + 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b, + 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, + 0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79, + 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, + 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, + 0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, + 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d, + 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, + 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713, + 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, + 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, + 0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e, + 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777, + 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, + 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, + 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, + 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, + 0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0, + 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, + 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, + 0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf, + 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, + 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d, +}; + +//***************************************************************************** +// +// This macro executes one iteration of the CRC-8-CCITT. +// +//***************************************************************************** +#define CRC8_ITER(crc, data) g_pui8Crc8CCITT[(uint8_t)((crc) ^ (data))] + +//***************************************************************************** +// +// This macro executes one iteration of the CRC-16. +// +//***************************************************************************** +#define CRC16_ITER(crc, data) (((crc) >> 8) ^ \ + g_pui16Crc16[(uint8_t)((crc) ^ (data))]) + +//***************************************************************************** +// +// This macro executes one iteration of the CRC-32. +// +//***************************************************************************** +#define CRC32_ITER(crc, data) (((crc) >> 8) ^ \ + g_pui32Crc32[(uint8_t)((crc & 0xFF) ^ \ + (data))]) + +//***************************************************************************** +// +//! Calculates the CRC-8-CCITT of an array of bytes. +//! +//! \param ui8Crc is the starting CRC-8-CCITT value. +//! \param pui8Data is a pointer to the data buffer. +//! \param ui32Count is the number of bytes in the data buffer. +//! +//! This function is used to calculate the CRC-8-CCITT of the input buffer. +//! The CRC-8-CCITT is computed in a running fashion, meaning that the entire +//! data block that is to have its CRC-8-CCITT computed does not need to be +//! supplied all at once. If the input buffer contains the entire block of +//! data, then \b ui8Crc should be set to 0. If, however, the entire block of +//! data is not available, then \b ui8Crc should be set to 0 for the first +//! portion of the data, and then the returned value should be passed back in +//! as \b ui8Crc for the next portion of the data. +//! +//! For example, to compute the CRC-8-CCITT of a block that has been split into +//! three pieces, use the following: +//! +//! \verbatim +//! ui8Crc = Crc8CCITT(0, pui8Data1, ui32Len1); +//! ui8Crc = Crc8CCITT(ui8Crc, pui8Data2, ui32Len2); +//! ui8Crc = Crc8CCITT(ui8Crc, pui8Data3, ui32Len3); +//! \endverbatim +//! +//! Computing a CRC-8-CCITT in a running fashion is useful in cases where the +//! data is arriving via a serial link (for example) and is therefore not all +//! available at one time. +//! +//! \return The CRC-8-CCITT of the input data. +// +//***************************************************************************** +uint8_t +Crc8CCITT(uint8_t ui8Crc, const uint8_t *pui8Data, uint32_t ui32Count) +{ + uint32_t ui32Temp; + + // + // If the data buffer is not 16 bit-aligned, then perform a single step of + // the CRC to make it 16 bit-aligned. + // + if((uint32_t)pui8Data & 1) + { + // + // Perform the CRC on this input byte. + // + ui8Crc = CRC8_ITER(ui8Crc, *pui8Data); + + // + // Skip this input byte. + // + pui8Data++; + ui32Count--; + } + + // + // If the data buffer is not word-aligned and there are at least two bytes + // of data left, then perform two steps of the CRC to make it word-aligned. + // + if(((uint32_t)pui8Data & 2) && (ui32Count > 1)) + { + // + // Read the next 16 bits. + // + ui32Temp = *(uint16_t *)pui8Data; + + // + // Perform the CRC on these two bytes. + // + ui8Crc = CRC8_ITER(ui8Crc, ui32Temp); + ui8Crc = CRC8_ITER(ui8Crc, ui32Temp >> 8); + + // + // Skip these input bytes. + // + pui8Data += 2; + ui32Count -= 2; + } + + // + // While there is at least a word remaining in the data buffer, perform + // four steps of the CRC to consume a word. + // + while(ui32Count > 3) + { + // + // Read the next word. + // + ui32Temp = *(uint32_t *)pui8Data; + + // + // Perform the CRC on these four bytes. + // + ui8Crc = CRC8_ITER(ui8Crc, ui32Temp); + ui8Crc = CRC8_ITER(ui8Crc, ui32Temp >> 8); + ui8Crc = CRC8_ITER(ui8Crc, ui32Temp >> 16); + ui8Crc = CRC8_ITER(ui8Crc, ui32Temp >> 24); + + // + // Skip these input bytes. + // + pui8Data += 4; + ui32Count -= 4; + } + + // + // If there are 16 bits left in the input buffer, then perform two steps of + // the CRC. + // + if(ui32Count > 1) + { + // + // Read the 16 bits. + // + ui32Temp = *(uint16_t *)pui8Data; + + // + // Perform the CRC on these two bytes. + // + ui8Crc = CRC8_ITER(ui8Crc, ui32Temp); + ui8Crc = CRC8_ITER(ui8Crc, ui32Temp >> 8); + + // + // Skip these input bytes. + // + pui8Data += 2; + ui32Count -= 2; + } + + // + // If there is a final byte remaining in the input buffer, then perform a + // single step of the CRC. + // + if(ui32Count != 0) + { + ui8Crc = CRC8_ITER(ui8Crc, *pui8Data); + } + + // + // Return the resulting CRC-8-CCITT value. + // + return(ui8Crc); +} + +//***************************************************************************** +// +//! Calculates the CRC-16 of an array of bytes. +//! +//! \param ui16Crc is the starting CRC-16 value. +//! \param pui8Data is a pointer to the data buffer. +//! \param ui32Count is the number of bytes in the data buffer. +//! +//! This function is used to calculate the CRC-16 of the input buffer. The +//! CRC-16 is computed in a running fashion, meaning that the entire data block +//! that is to have its CRC-16 computed does not need to be supplied all at +//! once. If the input buffer contains the entire block of data, then +//! \b ui16Crc should be set to 0. If, however, the entire block of data is +//! not available, then \b ui16Crc should be set to 0 for the first portion of +//! the data, and then the returned value should be passed back in as +//! \b ui16Crc for the next portion of the data. +//! +//! For example, to compute the CRC-16 of a block that has been split into +//! three pieces, use the following: +//! +//! \verbatim +//! ui16Crc = Crc16(0, pui8Data1, ui32Len1); +//! ui16Crc = Crc16(ui16Crc, pui8Data2, ui32Len2); +//! ui16Crc = Crc16(ui16Crc, pui8Data3, ui32Len3); +//! \endverbatim +//! +//! Computing a CRC-16 in a running fashion is useful in cases where the data +//! is arriving via a serial link (for example) and is therefore not all +//! available at one time. +//! +//! \return The CRC-16 of the input data. +// +//***************************************************************************** +uint16_t +Crc16(uint16_t ui16Crc, const uint8_t *pui8Data, uint32_t ui32Count) +{ + uint32_t ui32Temp; + + // + // If the data buffer is not 16 bit-aligned, then perform a single step of + // the CRC to make it 16 bit-aligned. + // + if((uint32_t)pui8Data & 1) + { + // + // Perform the CRC on this input byte. + // + ui16Crc = CRC16_ITER(ui16Crc, *pui8Data); + + // + // Skip this input byte. + // + pui8Data++; + ui32Count--; + } + + // + // If the data buffer is not word-aligned and there are at least two bytes + // of data left, then perform two steps of the CRC to make it word-aligned. + // + if(((uint32_t)pui8Data & 2) && (ui32Count > 1)) + { + // + // Read the next 16 bits. + // + ui32Temp = *(uint16_t *)pui8Data; + + // + // Perform the CRC on these two bytes. + // + ui16Crc = CRC16_ITER(ui16Crc, ui32Temp); + ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 8); + + // + // Skip these input bytes. + // + pui8Data += 2; + ui32Count -= 2; + } + + // + // While there is at least a word remaining in the data buffer, perform + // four steps of the CRC to consume a word. + // + while(ui32Count > 3) + { + // + // Read the next word. + // + ui32Temp = *(uint32_t *)pui8Data; + + // + // Perform the CRC on these four bytes. + // + ui16Crc = CRC16_ITER(ui16Crc, ui32Temp); + ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 8); + ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 16); + ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 24); + + // + // Skip these input bytes. + // + pui8Data += 4; + ui32Count -= 4; + } + + // + // If there are two bytes left in the input buffer, then perform two steps + // of the CRC. + // + if(ui32Count > 1) + { + // + // Read the two bytes. + // + ui32Temp = *(uint16_t *)pui8Data; + + // + // Perform the CRC on these two bytes. + // + ui16Crc = CRC16_ITER(ui16Crc, ui32Temp); + ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 8); + + // + // Skip these input bytes. + // + pui8Data += 2; + ui32Count -= 2; + } + + // + // If there is a final byte remaining in the input buffer, then perform a + // single step of the CRC. + // + if(ui32Count != 0) + { + ui16Crc = CRC16_ITER(ui16Crc, *pui8Data); + } + + // + // Return the resulting CRC-16 value. + // + return(ui16Crc); +} + +//***************************************************************************** +// +//! Calculates the CRC-16 of an array of words. +//! +//! \param ui32WordLen is the length of the array in words (the number of bytes +//! divided by 4). +//! \param pui32Data is a pointer to the data buffer. +//! +//! This function is a wrapper around the running CRC-16 function, providing +//! the CRC-16 for a single block of data. +//! +//! \return The CRC-16 of the input data. +// +//***************************************************************************** +uint16_t +Crc16Array(uint32_t ui32WordLen, const uint32_t *pui32Data) +{ + // + // Calculate and return the CRC-16 of this array of words. + // + return(Crc16(0, (const uint8_t *)pui32Data, ui32WordLen * 4)); +} + +//***************************************************************************** +// +//! Calculates three CRC-16s of an array of words. +//! +//! \param ui32WordLen is the length of the array in words (the number of bytes +//! divided by 4). +//! \param pui32Data is a pointer to the data buffer. +//! \param pui16Crc3 is a pointer to an array in which to place the three +//! CRC-16 values. +//! +//! This function is used to calculate three CRC-16s of the input buffer; the +//! first uses every byte from the array, the second uses only the even-index +//! bytes from the array (in other words, bytes 0, 2, 4, etc.), and the third +//! uses only the odd-index bytes from the array (in other words, bytes 1, 3, +//! 5, etc.). +//! +//! \return None +// +//***************************************************************************** +void +Crc16Array3(uint32_t ui32WordLen, const uint32_t *pui32Data, + uint16_t *pui16Crc3) +{ + uint16_t ui16Crc, ui16Cri8Odd, ui16Cri8Even; + uint32_t ui32Temp; + + // + // Initialize the CRC values to zero. + // + ui16Crc = 0; + ui16Cri8Odd = 0; + ui16Cri8Even = 0; + + // + // Loop while there are more words in the data buffer. + // + while(ui32WordLen--) + { + // + // Read the next word. + // + ui32Temp = *pui32Data++; + + // + // Perform the first CRC on all four data bytes. + // + ui16Crc = CRC16_ITER(ui16Crc, ui32Temp); + ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 8); + ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 16); + ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 24); + + // + // Perform the second CRC on only the even-index data bytes. + // + ui16Cri8Even = CRC16_ITER(ui16Cri8Even, ui32Temp); + ui16Cri8Even = CRC16_ITER(ui16Cri8Even, ui32Temp >> 16); + + // + // Perform the third CRC on only the odd-index data bytes. + // + ui16Cri8Odd = CRC16_ITER(ui16Cri8Odd, ui32Temp >> 8); + ui16Cri8Odd = CRC16_ITER(ui16Cri8Odd, ui32Temp >> 24); + } + + // + // Return the resulting CRC-16 values. + // + pui16Crc3[0] = ui16Crc; + pui16Crc3[1] = ui16Cri8Even; + pui16Crc3[2] = ui16Cri8Odd; +} + +//***************************************************************************** +// +//! Calculates the CRC-32 of an array of bytes. +//! +//! \param ui32Crc is the starting CRC-32 value. +//! \param pui8Data is a pointer to the data buffer. +//! \param ui32Count is the number of bytes in the data buffer. +//! +//! This function is used to calculate the CRC-32 of the input buffer. The +//! CRC-32 is computed in a running fashion, meaning that the entire data block +//! that is to have its CRC-32 computed does not need to be supplied all at +//! once. If the input buffer contains the entire block of data, then +//! \b ui32Crc should be set to 0xFFFFFFFF. If, however, the entire block of +//! data is not available, then \b ui32Crc should be set to 0xFFFFFFFF for the +//! first portion of the data, and then the returned value should be passed +//! back in as \b ui32Crc for the next portion of the data. Once all data has +//! been passed to the function, the final CRC-32 can be obtained by inverting +//! the last returned value. +//! +//! For example, to compute the CRC-32 of a block that has been split into +//! three pieces, use the following: +//! +//! \verbatim +//! ui32Crc = Crc32(0xFFFFFFFF, pui8Data1, ui32Len1); +//! ui32Crc = Crc32(ui32Crc, pui8Data2, ui32Len2); +//! ui32Crc = Crc32(ui32Crc, pui8Data3, ui32Len3); +//! ui32Crc ^= 0xFFFFFFFF; +//! \endverbatim +//! +//! Computing a CRC-32 in a running fashion is useful in cases where the data +//! is arriving via a serial link (for example) and is therefore not all +//! available at one time. +//! +//! \return The accumulated CRC-32 of the input data. +// +//***************************************************************************** +uint32_t +Crc32(uint32_t ui32Crc, const uint8_t *pui8Data, uint32_t ui32Count) +{ + uint32_t ui32Temp; + + // + // If the data buffer is not 16 bit-aligned, then perform a single step + // of the CRC to make it 16 bit-aligned. + // + if((uint32_t)pui8Data & 1) + { + // + // Perform the CRC on this input byte. + // + ui32Crc = CRC32_ITER(ui32Crc, *pui8Data); + + // + // Skip this input byte. + // + pui8Data++; + ui32Count--; + } + + // + // If the data buffer is not word-aligned and there are at least two bytes + // of data left, then perform two steps of the CRC to make it word-aligned. + // + if(((uint32_t)pui8Data & 2) && (ui32Count > 1)) + { + // + // Read the next int16_t. + // + ui32Temp = *(uint16_t *)pui8Data; + + // + // Perform the CRC on these two bytes. + // + ui32Crc = CRC32_ITER(ui32Crc, ui32Temp); + ui32Crc = CRC32_ITER(ui32Crc, ui32Temp >> 8); + + // + // Skip these input bytes. + // + pui8Data += 2; + ui32Count -= 2; + } + + // + // While there is at least a word remaining in the data buffer, perform + // four steps of the CRC to consume a word. + // + while(ui32Count > 3) + { + // + // Read the next word. + // + ui32Temp = *(uint32_t *)pui8Data; + + // + // Perform the CRC on these four bytes. + // + ui32Crc = CRC32_ITER(ui32Crc, ui32Temp); + ui32Crc = CRC32_ITER(ui32Crc, ui32Temp >> 8); + ui32Crc = CRC32_ITER(ui32Crc, ui32Temp >> 16); + ui32Crc = CRC32_ITER(ui32Crc, ui32Temp >> 24); + + // + // Skip these input bytes. + // + pui8Data += 4; + ui32Count -= 4; + } + + // + // If there are 16 bits left in the input buffer, then perform two steps of + // the CRC. + // + if(ui32Count > 1) + { + // + // Read the two bytes. + // + ui32Temp = *(uint16_t *)pui8Data; + + // + // Perform the CRC on these two bytes. + // + ui32Crc = CRC32_ITER(ui32Crc, ui32Temp); + ui32Crc = CRC32_ITER(ui32Crc, ui32Temp >> 8); + + // + // Skip these input bytes. + // + pui8Data += 2; + ui32Count -= 2; + } + + // + // If there is a final byte remaining in the input buffer, then perform a + // single step of the CRC. + // + if(ui32Count != 0) + { + ui32Crc = CRC32_ITER(ui32Crc, *pui8Data); + } + + // + // Return the resulting CRC-32 value. + // + return(ui32Crc); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/sysctl.c b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/sysctl.c new file mode 100644 index 0000000000000000000000000000000000000000..804b35009346b6b83eb5b2c705d9f8cc7c5c92ec --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/sysctl.c @@ -0,0 +1,3797 @@ +//***************************************************************************** +// +// sysctl.c - Driver for the system controller. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup sysctl_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include "hw_ints.h" +#include "hw_nvic.h" +#include "hw_sysctl.h" +#include "hw_types.h" +#include "hw_flash.h" +#include "cpu.h" +#include "debug.h" +#include "interrupt.h" +#include "sysctl.h" + +//***************************************************************************** +// +// The flash shift used in the math to calculate the flash sector size. +// +//***************************************************************************** +#ifndef FLASH_PP_MAINSS_S +#define FLASH_PP_MAINSS_S 16 +#endif + +//***************************************************************************** +// +// This macro converts the XTAL value provided in the ui32Config parameter to +// an index to the g_pui32Xtals array. +// +//***************************************************************************** +#define SysCtlXtalCfgToIndex(a) ((a & 0x7c0) >> 6) + +//***************************************************************************** +// +// An array that maps the crystal number in RCC to a frequency. +// +//***************************************************************************** +static const uint32_t g_pui32Xtals[] = +{ + 1000000, + 1843200, + 2000000, + 2457600, + 3579545, + 3686400, + 4000000, + 4096000, + 4915200, + 5000000, + 5120000, + 6000000, + 6144000, + 7372800, + 8000000, + 8192000, + 10000000, + 12000000, + 12288000, + 13560000, + 14318180, + 16000000, + 16384000, + 18000000, + 20000000, + 24000000, + 25000000 +}; + +//***************************************************************************** +// +// Maximum number of VCO entries in the g_pui32XTALtoVCO and +// g_pui32VCOFrequencies structures for a device. +// +//***************************************************************************** +#define MAX_VCO_ENTRIES 2 +#define MAX_XTAL_ENTRIES 18 + +//***************************************************************************** +// +// These macros are used in the g_pui32XTALtoVCO table to make it more +// readable. +// +//***************************************************************************** +#define PLL_M_TO_REG(mi, mf) \ + ((uint32_t)mi | (uint32_t)(mf << SYSCTL_PLLFREQ0_MFRAC_S)) +#define PLL_N_TO_REG(n) \ + ((uint32_t)(n - 1) << SYSCTL_PLLFREQ1_N_S) +#define PLL_Q_TO_REG(q) \ + ((uint32_t)(q - 1) << SYSCTL_PLLFREQ1_Q_S) + +//***************************************************************************** +// +// Look up of the values that go into the PLLFREQ0 and PLLFREQ1 registers. +// +//***************************************************************************** +static const uint32_t g_pppui32XTALtoVCO[MAX_VCO_ENTRIES][MAX_XTAL_ENTRIES][3] = +{ + { + // + // VCO 320 MHz + // + { PLL_M_TO_REG(64, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 5 MHz + { PLL_M_TO_REG(62, 512), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 5.12 MHz + { PLL_M_TO_REG(160, 0), PLL_N_TO_REG(3), PLL_Q_TO_REG(2) }, // 6 MHz + { PLL_M_TO_REG(52, 85), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 6.144 MHz + { PLL_M_TO_REG(43, 412), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 7.3728 MHz + { PLL_M_TO_REG(40, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 8 MHz + { PLL_M_TO_REG(39, 64), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 8.192 MHz + { PLL_M_TO_REG(32, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 10 MHz + { PLL_M_TO_REG(80, 0), PLL_N_TO_REG(3), PLL_Q_TO_REG(2) }, // 12 MHz + { PLL_M_TO_REG(26, 43), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 12.288 MHz + { PLL_M_TO_REG(23, 613), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 13.56 MHz + { PLL_M_TO_REG(22, 358), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 14.318180 MHz + { PLL_M_TO_REG(20, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 16 MHz + { PLL_M_TO_REG(19, 544), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 16.384 MHz + { PLL_M_TO_REG(160, 0), PLL_N_TO_REG(9), PLL_Q_TO_REG(2) }, // 18 MHz + { PLL_M_TO_REG(16, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 20 MHz + { PLL_M_TO_REG(40, 0), PLL_N_TO_REG(3), PLL_Q_TO_REG(2) }, // 24 MHz + { PLL_M_TO_REG(64, 0), PLL_N_TO_REG(5), PLL_Q_TO_REG(2) }, // 25 MHz + }, + { + // + // VCO 480 MHz + // + { PLL_M_TO_REG(96, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 5 MHz + { PLL_M_TO_REG(93, 768), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 5.12 MHz + { PLL_M_TO_REG(80, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 6 MHz + { PLL_M_TO_REG(78, 128), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 6.144 MHz + { PLL_M_TO_REG(65, 107), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 7.3728 MHz + { PLL_M_TO_REG(60, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 8 MHz + { PLL_M_TO_REG(58, 608), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 8.192 MHz + { PLL_M_TO_REG(48, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 10 MHz + { PLL_M_TO_REG(40, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 12 MHz + { PLL_M_TO_REG(39, 64), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 12.288 MHz + { PLL_M_TO_REG(35, 408), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 13.56 MHz + { PLL_M_TO_REG(33, 536), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 14.318180 MHz + { PLL_M_TO_REG(30, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 16 MHz + { PLL_M_TO_REG(29, 304), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 16.384 MHz + { PLL_M_TO_REG(80, 0), PLL_N_TO_REG(3), PLL_Q_TO_REG(2) }, // 18 MHz + { PLL_M_TO_REG(24, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 20 MHz + { PLL_M_TO_REG(20, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 24 MHz + { PLL_M_TO_REG(96, 0), PLL_N_TO_REG(5), PLL_Q_TO_REG(2) }, // 25 MHz + }, +}; + +//***************************************************************************** +// +// The mapping of system clock frequency to flash memory timing parameters. +// +//***************************************************************************** +static const struct +{ + uint32_t ui32Frequency; + uint32_t ui32MemTiming; +} +g_sXTALtoMEMTIM[] = +{ + { 16000000, (SYSCTL_MEMTIM0_FBCHT_0_5 | SYSCTL_MEMTIM0_FBCE | + (0 << SYSCTL_MEMTIM0_FWS_S) | + SYSCTL_MEMTIM0_EBCHT_0_5 | SYSCTL_MEMTIM0_EBCE | + (0 << SYSCTL_MEMTIM0_EWS_S) | + SYSCTL_MEMTIM0_MB1) }, + { 40000000, (SYSCTL_MEMTIM0_FBCHT_1_5 | (1 << SYSCTL_MEMTIM0_FWS_S) | + SYSCTL_MEMTIM0_EBCHT_1_5 | (1 << SYSCTL_MEMTIM0_EWS_S) | + SYSCTL_MEMTIM0_MB1) }, + { 60000000, (SYSCTL_MEMTIM0_FBCHT_2 | (2 << SYSCTL_MEMTIM0_FWS_S) | + SYSCTL_MEMTIM0_EBCHT_2 | (2 << SYSCTL_MEMTIM0_EWS_S) | + SYSCTL_MEMTIM0_MB1) }, + { 80000000, (SYSCTL_MEMTIM0_FBCHT_2_5 | (3 << SYSCTL_MEMTIM0_FWS_S) | + SYSCTL_MEMTIM0_EBCHT_2_5 | (3 << SYSCTL_MEMTIM0_EWS_S) | + SYSCTL_MEMTIM0_MB1) }, + { 100000000, (SYSCTL_MEMTIM0_FBCHT_3 | (4 << SYSCTL_MEMTIM0_FWS_S) | + SYSCTL_MEMTIM0_EBCHT_3 | (4 << SYSCTL_MEMTIM0_EWS_S) | + SYSCTL_MEMTIM0_MB1) }, + { 120000000, (SYSCTL_MEMTIM0_FBCHT_3_5 | (5 << SYSCTL_MEMTIM0_FWS_S) | + SYSCTL_MEMTIM0_EBCHT_3_5 | (5 << SYSCTL_MEMTIM0_EWS_S) | + SYSCTL_MEMTIM0_MB1) }, +}; + +//***************************************************************************** +// +// Get the correct memory timings for a given system clock value. +// +//***************************************************************************** +static uint32_t +_SysCtlMemTimingGet(uint32_t ui32SysClock) +{ + uint_fast8_t ui8Idx; + + // + // Loop through the flash memory timings. + // + for(ui8Idx = 0; + ui8Idx < (sizeof(g_sXTALtoMEMTIM) / sizeof(g_sXTALtoMEMTIM[0])); + ui8Idx++) + { + // + // See if the system clock frequency is less than the maximum frequency + // for this flash memory timing. + // + if(ui32SysClock <= g_sXTALtoMEMTIM[ui8Idx].ui32Frequency) + { + // + // This flash memory timing is the best choice for the system clock + // frequency, so return it now. + // + return(g_sXTALtoMEMTIM[ui8Idx].ui32MemTiming); + } + } + + // + // An appropriate flash memory timing could not be found, so the device is + // being clocked too fast. Return the default flash memory timing. + // + return(0); +} + +//***************************************************************************** +// +// Calculate the system frequency from the register settings base on the +// oscillator input. +// +//***************************************************************************** +static uint32_t +_SysCtlFrequencyGet(uint32_t ui32Xtal) +{ + uint32_t ui32Result; + uint_fast16_t ui16F1, ui16F2; + uint_fast16_t ui16PInt, ui16PFract; + uint_fast8_t ui8Q, ui8N; + + // + // Extract all of the values from the hardware registers. + // + ui16PFract = ((HWREG(SYSCTL_PLLFREQ0) & SYSCTL_PLLFREQ0_MFRAC_M) >> + SYSCTL_PLLFREQ0_MFRAC_S); + ui16PInt = HWREG(SYSCTL_PLLFREQ0) & SYSCTL_PLLFREQ0_MINT_M; + ui8Q = (((HWREG(SYSCTL_PLLFREQ1) & SYSCTL_PLLFREQ1_Q_M) >> + SYSCTL_PLLFREQ1_Q_S) + 1); + ui8N = (((HWREG(SYSCTL_PLLFREQ1) & SYSCTL_PLLFREQ1_N_M) >> + SYSCTL_PLLFREQ1_N_S) + 1); + + // + // Divide the crystal value by N. + // + ui32Xtal /= (uint32_t)ui8N; + + // + // Calculate the multiplier for bits 9:5. + // + ui16F1 = ui16PFract / 32; + + // + // Calculate the multiplier for bits 4:0. + // + ui16F2 = ui16PFract - (ui16F1 * 32); + + // + // Get the integer portion. + // + ui32Result = ui32Xtal * (uint32_t)ui16PInt; + + // + // Add first fractional bits portion(9:0). + // + ui32Result += (ui32Xtal * (uint32_t)ui16F1) / 32; + + // + // Add the second fractional bits portion(4:0). + // + ui32Result += (ui32Xtal * (uint32_t)ui16F2) / 1024; + + // + // Divide the result by Q. + // + ui32Result = ui32Result / (uint32_t)ui8Q; + + // + // Return the resulting PLL frequency. + // + return(ui32Result); +} + +//***************************************************************************** +// +// Look up of the possible VCO frequencies. +// +//***************************************************************************** +static const uint32_t g_pui32VCOFrequencies[MAX_VCO_ENTRIES] = +{ + 160000000, // VCO 320 + 240000000, // VCO 480 +}; + +//***************************************************************************** +// +// The base addresses of the various peripheral control registers. +// +//***************************************************************************** +#define SYSCTL_PPBASE 0x400fe300 +#define SYSCTL_SRBASE 0x400fe500 +#define SYSCTL_RCGCBASE 0x400fe600 +#define SYSCTL_SCGCBASE 0x400fe700 +#define SYSCTL_DCGCBASE 0x400fe800 +#define SYSCTL_PCBASE 0x400fe900 +#define SYSCTL_PRBASE 0x400fea00 + +//***************************************************************************** +// +//! \internal +//! Checks a peripheral identifier. +//! +//! \param ui32Peripheral is the peripheral identifier. +//! +//! This function determines if a peripheral identifier is valid. +//! +//! \return Returns \b true if the peripheral identifier is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static bool +_SysCtlPeripheralValid(uint32_t ui32Peripheral) +{ + return((ui32Peripheral == SYSCTL_PERIPH_ADC0) || + (ui32Peripheral == SYSCTL_PERIPH_ADC1) || + (ui32Peripheral == SYSCTL_PERIPH_CAN0) || + (ui32Peripheral == SYSCTL_PERIPH_CAN1) || + (ui32Peripheral == SYSCTL_PERIPH_COMP0) || + (ui32Peripheral == SYSCTL_PERIPH_CCM0) || + (ui32Peripheral == SYSCTL_PERIPH_EEPROM0) || + (ui32Peripheral == SYSCTL_PERIPH_EPHY0) || + (ui32Peripheral == SYSCTL_PERIPH_EMAC0) || + (ui32Peripheral == SYSCTL_PERIPH_EPI0) || + (ui32Peripheral == SYSCTL_PERIPH_FAN0) || + (ui32Peripheral == SYSCTL_PERIPH_GPIOA) || + (ui32Peripheral == SYSCTL_PERIPH_GPIOB) || + (ui32Peripheral == SYSCTL_PERIPH_GPIOC) || + (ui32Peripheral == SYSCTL_PERIPH_GPIOD) || + (ui32Peripheral == SYSCTL_PERIPH_GPIOE) || + (ui32Peripheral == SYSCTL_PERIPH_GPIOF) || + (ui32Peripheral == SYSCTL_PERIPH_GPIOG) || + (ui32Peripheral == SYSCTL_PERIPH_GPIOH) || + (ui32Peripheral == SYSCTL_PERIPH_GPIOJ) || + (ui32Peripheral == SYSCTL_PERIPH_GPIOK) || + (ui32Peripheral == SYSCTL_PERIPH_GPIOL) || + (ui32Peripheral == SYSCTL_PERIPH_GPIOM) || + (ui32Peripheral == SYSCTL_PERIPH_GPION) || + (ui32Peripheral == SYSCTL_PERIPH_GPIOP) || + (ui32Peripheral == SYSCTL_PERIPH_GPIOQ) || + (ui32Peripheral == SYSCTL_PERIPH_GPIOR) || + (ui32Peripheral == SYSCTL_PERIPH_GPIOS) || + (ui32Peripheral == SYSCTL_PERIPH_GPIOT) || + (ui32Peripheral == SYSCTL_PERIPH_HIBERNATE) || + (ui32Peripheral == SYSCTL_PERIPH_I2C0) || + (ui32Peripheral == SYSCTL_PERIPH_I2C1) || + (ui32Peripheral == SYSCTL_PERIPH_I2C2) || + (ui32Peripheral == SYSCTL_PERIPH_I2C3) || + (ui32Peripheral == SYSCTL_PERIPH_I2C4) || + (ui32Peripheral == SYSCTL_PERIPH_I2C5) || + (ui32Peripheral == SYSCTL_PERIPH_I2C6) || + (ui32Peripheral == SYSCTL_PERIPH_I2C7) || + (ui32Peripheral == SYSCTL_PERIPH_I2C8) || + (ui32Peripheral == SYSCTL_PERIPH_I2C9) || + (ui32Peripheral == SYSCTL_PERIPH_LCD0) || + (ui32Peripheral == SYSCTL_PERIPH_PWM0) || + (ui32Peripheral == SYSCTL_PERIPH_PWM1) || + (ui32Peripheral == SYSCTL_PERIPH_QEI0) || + (ui32Peripheral == SYSCTL_PERIPH_QEI1) || + (ui32Peripheral == SYSCTL_PERIPH_SSI0) || + (ui32Peripheral == SYSCTL_PERIPH_SSI1) || + (ui32Peripheral == SYSCTL_PERIPH_SSI2) || + (ui32Peripheral == SYSCTL_PERIPH_SSI3) || + (ui32Peripheral == SYSCTL_PERIPH_TIMER0) || + (ui32Peripheral == SYSCTL_PERIPH_TIMER1) || + (ui32Peripheral == SYSCTL_PERIPH_TIMER2) || + (ui32Peripheral == SYSCTL_PERIPH_TIMER3) || + (ui32Peripheral == SYSCTL_PERIPH_TIMER4) || + (ui32Peripheral == SYSCTL_PERIPH_TIMER5) || + (ui32Peripheral == SYSCTL_PERIPH_TIMER6) || + (ui32Peripheral == SYSCTL_PERIPH_TIMER7) || + (ui32Peripheral == SYSCTL_PERIPH_UART0) || + (ui32Peripheral == SYSCTL_PERIPH_UART1) || + (ui32Peripheral == SYSCTL_PERIPH_UART2) || + (ui32Peripheral == SYSCTL_PERIPH_UART3) || + (ui32Peripheral == SYSCTL_PERIPH_UART4) || + (ui32Peripheral == SYSCTL_PERIPH_UART5) || + (ui32Peripheral == SYSCTL_PERIPH_UART6) || + (ui32Peripheral == SYSCTL_PERIPH_UART7) || + (ui32Peripheral == SYSCTL_PERIPH_UDMA) || + (ui32Peripheral == SYSCTL_PERIPH_USB0) || + (ui32Peripheral == SYSCTL_PERIPH_WDOG0) || + (ui32Peripheral == SYSCTL_PERIPH_WDOG1) || + (ui32Peripheral == SYSCTL_PERIPH_WTIMER0) || + (ui32Peripheral == SYSCTL_PERIPH_WTIMER1) || + (ui32Peripheral == SYSCTL_PERIPH_WTIMER2) || + (ui32Peripheral == SYSCTL_PERIPH_WTIMER3) || + (ui32Peripheral == SYSCTL_PERIPH_WTIMER4) || + (ui32Peripheral == SYSCTL_PERIPH_WTIMER5)); +} +#endif + +//***************************************************************************** +// +//! Gets the size of the SRAM. +//! +//! This function determines the size of the SRAM on the Tiva device. +//! +//! \return The total number of bytes of SRAM. +// +//***************************************************************************** +uint32_t +SysCtlSRAMSizeGet(void) +{ + return((HWREG(FLASH_SSIZE) + 1) * 256); +} + +//***************************************************************************** +// +//! Gets the size of the flash. +//! +//! This function determines the size of the flash on the Tiva device. +//! +//! \return The total number of bytes of flash. +// +//***************************************************************************** +uint32_t +SysCtlFlashSizeGet(void) +{ + + // + // TM4C123 devices report the flash size in DC0. + // + if(CLASS_IS_TM4C123) + { + // + // Compute the size of the flash. + // + return(((HWREG(SYSCTL_DC0) & SYSCTL_DC0_FLASHSZ_M) << 11) + 0x800); + } + else + { + // + // Get the flash size from the FLASH_PP register. + // + return(2048 * ((HWREG(FLASH_PP) & FLASH_PP_SIZE_M) + 1)); + } +} + +//***************************************************************************** +// +//! Gets the size of a single eraseable sector of flash. +//! +//! This function determines the flash sector size on the Tiva device. +//! This size determines the erase granularity of the device flash. +//! +//! \return The number of bytes in a single flash sector. +// +//***************************************************************************** +uint32_t +SysCtlFlashSectorSizeGet(void) +{ + // + // TM4C129 devices store the value in a different register. + // + if(CLASS_IS_TM4C129) + { + // + // Get the flash sector size from the FLASH_PP register. + // + return(1 << (10 + + ((HWREG(FLASH_PP) & + FLASH_PP_MAINSS_M) >> FLASH_PP_MAINSS_S))); + } + else + { + // + // The sector size is fixed at 1KB. + // + return(1024); + } +} + +//***************************************************************************** +// +//! Determines if a peripheral is present. +//! +//! \param ui32Peripheral is the peripheral in question. +//! +//! This function determines if a particular peripheral is present in the +//! device. Each member of the Tiva family has a different peripheral +//! set; this function determines which peripherals are present on this device. +//! +//! The \e ui32Peripheral parameter must be only one of the following values: +//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, +//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY, +//! \b SYSCTL_PERIPH_EPI0, +//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, +//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, +//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, +//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, +//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, +//! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT, +//! \b SYSCTL_PERIPH_HIBERNATE, +//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2, +//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5, +//! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8, +//! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0, +//! \b SYSCTL_PERIPH_ONEWIRE0, +//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0, +//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1, +//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, +//! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6, +//! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, +//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, +//! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, +//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, +//! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, +//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, +//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5 +//! +//! \return Returns \b true if the specified peripheral is present and \b false +//! if it is not. +// +//***************************************************************************** +bool +SysCtlPeripheralPresent(uint32_t ui32Peripheral) +{ + // + // Check the arguments. + // + ASSERT(_SysCtlPeripheralValid(ui32Peripheral)); + + // + // See if this peripheral is present. + // + return(HWREGBITW(SYSCTL_PPBASE + ((ui32Peripheral & 0xff00) >> 8), + ui32Peripheral & 0xff)); +} + +//***************************************************************************** +// +//! Determines if a peripheral is ready. +//! +//! \param ui32Peripheral is the peripheral in question. +//! +//! This function determines if a particular peripheral is ready to be +//! accessed. The peripheral may be in a non-ready state if it is not enabled, +//! is being held in reset, or is in the process of becoming ready after being +//! enabled or taken out of reset. +//! +//! The \e ui32Peripheral parameter must be only one of the following values: +//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, +//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY, +//! \b SYSCTL_PERIPH_EPI0, +//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, +//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, +//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, +//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, +//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, +//! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT, +//! \b SYSCTL_PERIPH_HIBERNATE, +//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2, +//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5, +//! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8, +//! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0, +//! \b SYSCTL_PERIPH_ONEWIRE0, +//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0, +//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1, +//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, +//! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6, +//! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, +//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, +//! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, +//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, +//! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, +//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, +//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5 +//! +//! \note The ability to check for a peripheral being ready varies based on the +//! Tiva part in use. Please consult the data sheet for the part you are +//! using to determine if this feature is available. +//! +//! \return Returns \b true if the specified peripheral is ready and \b false +//! if it is not. +// +//***************************************************************************** +bool +SysCtlPeripheralReady(uint32_t ui32Peripheral) +{ + // + // Check the arguments. + // + ASSERT(_SysCtlPeripheralValid(ui32Peripheral)); + + // + // See if this peripheral is ready. + // + return(HWREGBITW(SYSCTL_PRBASE + ((ui32Peripheral & 0xff00) >> 8), + ui32Peripheral & 0xff)); +} + +//***************************************************************************** +// +//! Powers on a peripheral. +//! +//! \param ui32Peripheral is the peripheral to be powered on. +//! +//! This function turns on the power to a peripheral. The peripheral continues +//! to receive power even when its clock is not enabled. +//! +//! The \e ui32Peripheral parameter must be only one of the following values: +//! \b SYSCTL_PERIPH_CAN0,\b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_EMAC, +//! \b SYSCTL_PERIPH_EPHY, \b SYSCTL_PERIPH_LCD0, \b SYSCTL_PERIPH_USB0 +//! +//! \note The ability to power off a peripheral varies based on the Tiva +//! part in use. Please consult the data sheet for the part you are using to +//! determine if this feature is available. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPeripheralPowerOn(uint32_t ui32Peripheral) +{ + // + // Check the arguments. + // + ASSERT(_SysCtlPeripheralValid(ui32Peripheral)); + + // + // Power on this peripheral. + // + HWREGBITW(SYSCTL_PCBASE + ((ui32Peripheral & 0xff00) >> 8), + ui32Peripheral & 0xff) = 1; +} + +//***************************************************************************** +// +//! Powers off a peripheral. +//! +//! \param ui32Peripheral is the peripheral to be powered off. +//! +//! This function allows the power to a peripheral to be turned off. The +//! peripheral continues to receive power when its clock is enabled, but +//! the power is removed when its clock is disabled. +//! +//! The \e ui32Peripheral parameter must be only one of the following values: +//! \b SYSCTL_PERIPH_CAN0,\b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_EMAC, +//! \b SYSCTL_PERIPH_EPHY, \b SYSCTL_PERIPH_LCD0, \b SYSCTL_PERIPH_USB0 +//! +//! \note The ability to power off a peripheral varies based on the Tiva +//! part in use. Please consult the data sheet for the part you are using to +//! determine if this feature is available. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPeripheralPowerOff(uint32_t ui32Peripheral) +{ + // + // Check the arguments. + // + ASSERT(_SysCtlPeripheralValid(ui32Peripheral)); + + // + // Power off this peripheral. + // + HWREGBITW(SYSCTL_PCBASE + ((ui32Peripheral & 0xff00) >> 8), + ui32Peripheral & 0xff) = 0; +} + +//***************************************************************************** +// +//! Performs a software reset of a peripheral. +//! +//! \param ui32Peripheral is the peripheral to reset. +//! +//! This function performs a software reset of the specified peripheral. An +//! individual peripheral reset signal is asserted for a brief period and then +//! de-asserted, returning the internal state of the peripheral to its reset +//! condition. +//! +//! The \e ui32Peripheral parameter must be only one of the following values: +//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, +//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY, +//! \b SYSCTL_PERIPH_EPI0, +//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, +//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, +//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, +//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, +//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, +//! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT, +//! \b SYSCTL_PERIPH_HIBERNATE, +//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2, +//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5, +//! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8, +//! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0, +//! \b SYSCTL_PERIPH_ONEWIRE0, +//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0, +//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1, +//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, +//! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6, +//! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, +//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, +//! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, +//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, +//! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, +//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, +//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5 +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPeripheralReset(uint32_t ui32Peripheral) +{ + volatile uint_fast8_t ui8Delay; + + // + // Check the arguments. + // + ASSERT(_SysCtlPeripheralValid(ui32Peripheral)); + + // + // Put the peripheral into the reset state. + // + HWREGBITW(SYSCTL_SRBASE + ((ui32Peripheral & 0xff00) >> 8), + ui32Peripheral & 0xff) = 1; + + // + // Delay for a little bit. + // + for(ui8Delay = 0; ui8Delay < 16; ui8Delay++) + { + } + + // + // Take the peripheral out of the reset state. + // + HWREGBITW(SYSCTL_SRBASE + ((ui32Peripheral & 0xff00) >> 8), + ui32Peripheral & 0xff) = 0; +} + +//***************************************************************************** +// +//! Enables a peripheral. +//! +//! \param ui32Peripheral is the peripheral to enable. +//! +//! This function enables a peripheral. At power-up, all peripherals are +//! disabled; they must be enabled in order to operate or respond to register +//! reads/writes. +//! +//! The \e ui32Peripheral parameter must be only one of the following values: +//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, +//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY, +//! \b SYSCTL_PERIPH_EPI0, +//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, +//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, +//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, +//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, +//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, +//! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT, +//! \b SYSCTL_PERIPH_HIBERNATE, +//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2, +//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5, +//! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8, +//! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0, +//! \b SYSCTL_PERIPH_ONEWIRE0, +//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0, +//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1, +//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, +//! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6, +//! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, +//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, +//! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, +//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, +//! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, +//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, +//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5 +//! +//! \note It takes five clock cycles after the write to enable a peripheral +//! before the the peripheral is actually enabled. During this time, attempts +//! to access the peripheral result in a bus fault. Care should be taken +//! to ensure that the peripheral is not accessed during this brief time +//! period. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPeripheralEnable(uint32_t ui32Peripheral) +{ + // + // Check the arguments. + // + ASSERT(_SysCtlPeripheralValid(ui32Peripheral)); + + // + // Enable this peripheral. + // + HWREGBITW(SYSCTL_RCGCBASE + ((ui32Peripheral & 0xff00) >> 8), + ui32Peripheral & 0xff) = 1; +} + +//***************************************************************************** +// +//! Disables a peripheral. +//! +//! \param ui32Peripheral is the peripheral to disable. +//! +//! This function disables a peripheral. Once disabled, they do not operate or +//! respond to register reads/writes. +//! +//! The \e ui32Peripheral parameter must be only one of the following values: +//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, +//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY, +//! \b SYSCTL_PERIPH_EPI0, +//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, +//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, +//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, +//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, +//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, +//! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT, +//! \b SYSCTL_PERIPH_HIBERNATE, +//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2, +//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5, +//! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8, +//! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0, +//! \b SYSCTL_PERIPH_ONEWIRE0, +//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0, +//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1, +//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, +//! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6, +//! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, +//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, +//! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, +//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, +//! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, +//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, +//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5 +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPeripheralDisable(uint32_t ui32Peripheral) +{ + // + // Check the arguments. + // + ASSERT(_SysCtlPeripheralValid(ui32Peripheral)); + + // + // Disable this peripheral. + // + HWREGBITW(SYSCTL_RCGCBASE + ((ui32Peripheral & 0xff00) >> 8), + ui32Peripheral & 0xff) = 0; +} + +//***************************************************************************** +// +//! Enables a peripheral in sleep mode. +//! +//! \param ui32Peripheral is the peripheral to enable in sleep mode. +//! +//! This function allows a peripheral to continue operating when the processor +//! goes into sleep mode. Because the clocking configuration of the device +//! does not change, any peripheral can safely continue operating while the +//! processor is in sleep mode and can therefore wake the processor from sleep +//! mode. +//! +//! Sleep mode clocking of peripherals must be enabled via +//! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode +//! configuration is maintained but has no effect when sleep mode is entered. +//! +//! The \e ui32Peripheral parameter must be only one of the following values: +//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, +//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY, +//! \b SYSCTL_PERIPH_EPI0, +//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, +//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, +//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, +//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, +//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, +//! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT, +//! \b SYSCTL_PERIPH_HIBERNATE, +//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2, +//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5, +//! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8, +//! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0, +//! \b SYSCTL_PERIPH_ONEWIRE0, +//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0, +//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1, +//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, +//! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6, +//! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, +//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, +//! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, +//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, +//! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, +//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, +//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5 +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPeripheralSleepEnable(uint32_t ui32Peripheral) +{ + // + // Check the arguments. + // + ASSERT(_SysCtlPeripheralValid(ui32Peripheral)); + + // + // Enable this peripheral in sleep mode. + // + HWREGBITW(SYSCTL_SCGCBASE + ((ui32Peripheral & 0xff00) >> 8), + ui32Peripheral & 0xff) = 1; +} + +//***************************************************************************** +// +//! Disables a peripheral in sleep mode. +//! +//! \param ui32Peripheral is the peripheral to disable in sleep mode. +//! +//! This function causes a peripheral to stop operating when the processor goes +//! into sleep mode. Disabling peripherals while in sleep mode helps to lower +//! the current draw of the device. If enabled (via SysCtlPeripheralEnable()), +//! the peripheral automatically resumes operation when the processor +//! leaves sleep mode, maintaining its entire state from before sleep mode was +//! entered. +//! +//! Sleep mode clocking of peripherals must be enabled via +//! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode +//! configuration is maintained but has no effect when sleep mode is entered. +//! +//! The \e ui32Peripheral parameter must be only one of the following values: +//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, +//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY, +//! \b SYSCTL_PERIPH_EPI0, +//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, +//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, +//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, +//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, +//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, +//! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT, +//! \b SYSCTL_PERIPH_HIBERNATE, +//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2, +//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5, +//! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8, +//! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0, +//! \b SYSCTL_PERIPH_ONEWIRE0, +//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0, +//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1, +//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, +//! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6, +//! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, +//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, +//! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, +//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, +//! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, +//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, +//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5 +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPeripheralSleepDisable(uint32_t ui32Peripheral) +{ + // + // Check the arguments. + // + ASSERT(_SysCtlPeripheralValid(ui32Peripheral)); + + // + // Disable this peripheral in sleep mode. + // + HWREGBITW(SYSCTL_SCGCBASE + ((ui32Peripheral & 0xff00) >> 8), + ui32Peripheral & 0xff) = 0; +} + +//***************************************************************************** +// +//! Enables a peripheral in deep-sleep mode. +//! +//! \param ui32Peripheral is the peripheral to enable in deep-sleep mode. +//! +//! This function allows a peripheral to continue operating when the processor +//! goes into deep-sleep mode. Because the clocking configuration of the +//! device may change, not all peripherals can safely continue operating while +//! the processor is in deep-sleep mode. Those that must run at a particular +//! frequency (such as a UART) do not work as expected if the clock changes. +//! It is the responsibility of the caller to make sensible choices. +//! +//! Deep-sleep mode clocking of peripherals must be enabled via +//! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode +//! configuration is maintained but has no effect when deep-sleep mode is +//! entered. +//! +//! The \e ui32Peripheral parameter must be only one of the following values: +//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, +//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY, +//! \b SYSCTL_PERIPH_EPI0, +//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, +//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, +//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, +//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, +//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, +//! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT, +//! \b SYSCTL_PERIPH_HIBERNATE, +//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2, +//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5, +//! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8, +//! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0, +//! \b SYSCTL_PERIPH_ONEWIRE0, +//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0, +//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1, +//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, +//! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6, +//! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, +//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, +//! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, +//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, +//! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, +//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, +//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5 +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPeripheralDeepSleepEnable(uint32_t ui32Peripheral) +{ + // + // Check the arguments. + // + ASSERT(_SysCtlPeripheralValid(ui32Peripheral)); + + // + // Enable this peripheral in deep-sleep mode. + // + HWREGBITW(SYSCTL_DCGCBASE + ((ui32Peripheral & 0xff00) >> 8), + ui32Peripheral & 0xff) = 1; +} + +//***************************************************************************** +// +//! Disables a peripheral in deep-sleep mode. +//! +//! \param ui32Peripheral is the peripheral to disable in deep-sleep mode. +//! +//! This function causes a peripheral to stop operating when the processor goes +//! into deep-sleep mode. Disabling peripherals while in deep-sleep mode helps +//! to lower the current draw of the device, and can keep peripherals that +//! require a particular clock frequency from operating when the clock changes +//! as a result of entering deep-sleep mode. If enabled (via +//! SysCtlPeripheralEnable()), the peripheral automatically resumes +//! operation when the processor leaves deep-sleep mode, maintaining its entire +//! state from before deep-sleep mode was entered. +//! +//! Deep-sleep mode clocking of peripherals must be enabled via +//! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode +//! configuration is maintained but has no effect when deep-sleep mode is +//! entered. +//! +//! The \e ui32Peripheral parameter must be only one of the following values: +//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, +//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY, +//! \b SYSCTL_PERIPH_EPI0, +//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, +//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, +//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, +//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, +//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, +//! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT, +//! \b SYSCTL_PERIPH_HIBERNATE, +//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2, +//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5, +//! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8, +//! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0, +//! \b SYSCTL_PERIPH_ONEWIRE0, +//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0, +//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1, +//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, +//! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6, +//! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, +//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, +//! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, +//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, +//! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, +//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, +//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5 +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPeripheralDeepSleepDisable(uint32_t ui32Peripheral) +{ + // + // Check the arguments. + // + ASSERT(_SysCtlPeripheralValid(ui32Peripheral)); + + // + // Disable this peripheral in deep-sleep mode. + // + HWREGBITW(SYSCTL_DCGCBASE + ((ui32Peripheral & 0xff00) >> 8), + ui32Peripheral & 0xff) = 0; +} + +//***************************************************************************** +// +//! Controls peripheral clock gating in sleep and deep-sleep mode. +//! +//! \param bEnable is a boolean that is \b true if the sleep and deep-sleep +//! peripheral configuration should be used and \b false if not. +//! +//! This function controls how peripherals are clocked when the processor goes +//! into sleep or deep-sleep mode. By default, the peripherals are clocked the +//! same as in run mode; if peripheral clock gating is enabled, they are +//! clocked according to the configuration set by +//! SysCtlPeripheralSleepEnable(), SysCtlPeripheralSleepDisable(), +//! SysCtlPeripheralDeepSleepEnable(), and SysCtlPeripheralDeepSleepDisable(). +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPeripheralClockGating(bool bEnable) +{ + if(CLASS_IS_TM4C123) + { + // + // Enable peripheral clock gating as requested. + // + if(bEnable) + { + HWREG(SYSCTL_RCC) |= SYSCTL_RCC_ACG; + } + else + { + HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_ACG); + } + } + else + { + // + // Enable peripheral clock gating as requested. + // + if(bEnable) + { + HWREG(SYSCTL_RSCLKCFG) |= SYSCTL_RSCLKCFG_ACG; + } + else + { + HWREG(SYSCTL_RSCLKCFG) &= ~SYSCTL_RSCLKCFG_ACG; + } + } +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the system control interrupt. +//! +//! \param pfnHandler is a pointer to the function to be called when the system +//! control interrupt occurs. +//! +//! This function registers the handler to be called when a system control +//! interrupt occurs. This function enables the global interrupt in the +//! interrupt controller; specific system control interrupts must be enabled +//! via SysCtlIntEnable(). It is the interrupt handler's responsibility to +//! clear the interrupt source via SysCtlIntClear(). +//! +//! System control can generate interrupts when the PLL achieves lock, if the +//! internal LDO current limit is exceeded, if the internal oscillator fails, +//! if the main oscillator fails, if the internal LDO output voltage droops too +//! much, if the external voltage droops too much, or if the PLL fails. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \note The events that cause system control interrupts vary based on the +//! Tiva part in use. Please consult the data sheet for the part you are +//! using to determine which interrupt sources are available. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlIntRegister(void (*pfnHandler)(void)) +{ + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(INT_SYSCTL_TM4C123, pfnHandler); + + // + // Enable the system control interrupt. + // + IntEnable(INT_SYSCTL_TM4C123); +} + +//***************************************************************************** +// +//! Unregisters the interrupt handler for the system control interrupt. +//! +//! This function unregisters the handler to be called when a system control +//! interrupt occurs. This function also masks off the interrupt in the +//! interrupt controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlIntUnregister(void) +{ + // + // Disable the interrupt. + // + IntDisable(INT_SYSCTL_TM4C123); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_SYSCTL_TM4C123); +} + +//***************************************************************************** +// +//! Enables individual system control interrupt sources. +//! +//! \param ui32Ints is a bit mask of the interrupt sources to be enabled. Must +//! be a logical OR of \b SYSCTL_INT_BOR0, \b SYSCTL_INT_VDDA_OK, +//! \b SYSCTL_INT_MOSC_PUP, \b SYSCTL_INT_USBPLL_LOCK, +//! \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_BOR, and/or +//! \b SYSCTL_INT_BOR1. +//! +//! This function enables the indicated system control interrupt sources. Only +//! the sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \note The interrupt sources vary based on the Tiva part in use. +//! Please consult the data sheet for the part you are using to determine +//! which interrupt sources are available. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlIntEnable(uint32_t ui32Ints) +{ + // + // Enable the specified interrupts. + // + HWREG(SYSCTL_IMC) |= ui32Ints; +} + +//***************************************************************************** +// +//! Disables individual system control interrupt sources. +//! +//! \param ui32Ints is a bit mask of the interrupt sources to be disabled. +//! Must be a logical OR of \b SYSCTL_INT_BOR0, \b SYSCTL_INT_VDDA_OK, +//! \b SYSCTL_INT_MOSC_PUP, \b SYSCTL_INT_USBPLL_LOCK, +//! \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_BOR, and/or +//! \b SYSCTL_INT_BOR1. +//! +//! This function disables the indicated system control interrupt sources. +//! Only the sources that are enabled can be reflected to the processor +//! interrupt; disabled sources have no effect on the processor. +//! +//! \note The interrupt sources vary based on the Tiva part in use. +//! Please consult the data sheet for the part you are using to determine +//! which interrupt sources are available. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlIntDisable(uint32_t ui32Ints) +{ + // + // Disable the specified interrupts. + // + HWREG(SYSCTL_IMC) &= ~(ui32Ints); +} + +//***************************************************************************** +// +//! Clears system control interrupt sources. +//! +//! \param ui32Ints is a bit mask of the interrupt sources to be cleared. Must +//! be a logical OR of \b SYSCTL_INT_BOR0, \b SYSCTL_INT_VDDA_OK, +//! \b SYSCTL_INT_MOSC_PUP, \b SYSCTL_INT_USBPLL_LOCK, +//! \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_BOR, and/or +//! \b SYSCTL_INT_BOR1. +//! +//! The specified system control interrupt sources are cleared, so that they no +//! longer assert. This function must be called in the interrupt handler to +//! keep it from being called again immediately on exit. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \note The interrupt sources vary based on the Tiva part in use. +//! Please consult the data sheet for the part you are using to determine +//! which interrupt sources are available. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlIntClear(uint32_t ui32Ints) +{ + // + // Clear the requested interrupt sources. + // + HWREG(SYSCTL_MISC) = ui32Ints; +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param bMasked is false if the raw interrupt status is required and true if +//! the masked interrupt status is required. +//! +//! This function returns the interrupt status for the system controller. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \note The interrupt sources vary based on the Tiva part in use. +//! Please consult the data sheet for the part you are using to determine +//! which interrupt sources are available. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! \b SYSCTL_INT_BOR0, \b SYSCTL_INT_VDDA_OK, +//! \b SYSCTL_INT_MOSC_PUP, \b SYSCTL_INT_USBPLL_LOCK, +//! \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_BOR, and/or +//! \b SYSCTL_INT_BOR1. +// +//***************************************************************************** +uint32_t +SysCtlIntStatus(bool bMasked) +{ + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(SYSCTL_MISC)); + } + else + { + return(HWREG(SYSCTL_RIS)); + } +} + +//***************************************************************************** +// +//! Sets the output voltage of the LDO when the device enters sleep mode. +//! +//! \param ui32Voltage is the required output voltage from the LDO while in +//! sleep mode. +//! +//! This function sets the output voltage of the LDO while in sleep mode. +//! The \e ui32Voltage parameter must be one of the following values: +//! \b SYSCTL_LDO_0_90V, \b SYSCTL_LDO_0_95V, \b SYSCTL_LDO_1_00V, +//! \b SYSCTL_LDO_1_05V, \b SYSCTL_LDO_1_10V, \b SYSCTL_LDO_1_15V, or +//! \b SYSCTL_LDO_1_20V. +//! +//! \note The availability of this feature, the default LDO voltage, and the +//! adjustment range varies with the Tiva part in use. Please consult the +//! data sheet for the part you are using to determine whether this support is +//! available. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlLDOSleepSet(uint32_t ui32Voltage) +{ + // + // Check the arguments. + // + ASSERT((ui32Voltage == SYSCTL_LDO_0_90V) || + (ui32Voltage == SYSCTL_LDO_0_95V) || + (ui32Voltage == SYSCTL_LDO_1_00V) || + (ui32Voltage == SYSCTL_LDO_1_05V) || + (ui32Voltage == SYSCTL_LDO_1_10V) || + (ui32Voltage == SYSCTL_LDO_1_15V) || + (ui32Voltage == SYSCTL_LDO_1_20V)); + + // + // Set the sleep-mode LDO voltage to the requested value. + // + HWREG(SYSCTL_LDOSPCTL) = ui32Voltage; +} + +//***************************************************************************** +// +//! Returns the output voltage of the LDO when the device enters sleep mode. +//! +//! This function determines the output voltage of the LDO while in sleep mode, +//! as specified by the control register. +//! +//! \note The availability of this feature, the default LDO voltage, and the +//! adjustment range varies with the Tiva part in use. Please consult the +//! data sheet for the part you are using to determine whether this support is +//! available. +//! +//! \return Returns the sleep-mode voltage of the LDO and is one of +//! \b SYSCTL_LDO_0_90V, \b SYSCTL_LDO_0_95V, \b SYSCTL_LDO_1_00V, +//! \b SYSCTL_LDO_1_05V, \b SYSCTL_LDO_1_10V, \b SYSCTL_LDO_1_15V, or +//! \b SYSCTL_LDO_1_20V. +// +//***************************************************************************** +uint32_t +SysCtlLDOSleepGet(void) +{ + // + // Return the sleep-mode LDO voltage setting. + // + return(HWREG(SYSCTL_LDOSPCTL)); +} + +//***************************************************************************** +// +//! Sets the output voltage of the LDO when the device enters deep-sleep +//! mode. +//! +//! \param ui32Voltage is the required output voltage from the LDO while in +//! deep-sleep mode. +//! +//! This function sets the output voltage of the LDO while in deep-sleep mode. +//! The \e ui32Voltage parameter specifies the output voltage of the LDO and +//! must be one of the following values: \b SYSCTL_LDO_0_90V, +//! \b SYSCTL_LDO_0_95V, \b SYSCTL_LDO_1_00V, \b SYSCTL_LDO_1_05V, +//! \b SYSCTL_LDO_1_10V, \b SYSCTL_LDO_1_15V, or \b SYSCTL_LDO_1_20V. +//! +//! \note The availability of this feature, the default LDO voltage, and the +//! adjustment range varies with the Tiva part in use. Please consult the +//! data sheet for the part you are using to determine whether this support is +//! available. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlLDODeepSleepSet(uint32_t ui32Voltage) +{ + // + // Check the arguments. + // + ASSERT((ui32Voltage == SYSCTL_LDO_0_90V) || + (ui32Voltage == SYSCTL_LDO_0_95V) || + (ui32Voltage == SYSCTL_LDO_1_00V) || + (ui32Voltage == SYSCTL_LDO_1_05V) || + (ui32Voltage == SYSCTL_LDO_1_10V) || + (ui32Voltage == SYSCTL_LDO_1_15V) || + (ui32Voltage == SYSCTL_LDO_1_20V)); + + // + // Set the deep-sleep LDO voltage to the requested value. + // + HWREG(SYSCTL_LDODPCTL) = ui32Voltage; +} + +//***************************************************************************** +// +//! Returns the output voltage of the LDO when the device enters deep-sleep +//! mode. +//! +//! This function returns the output voltage of the LDO when the device is +//! in deep-sleep mode, as specified by the control register. +//! +//! \note The availability of this feature, the default LDO voltage, and the +//! adjustment range varies with the Tiva part in use. Please consult the +//! data sheet for the part you are using to determine whether this support is +//! available. +//! +//! \return Returns the deep-sleep-mode voltage of the LDO; is one of +//! \b SYSCTL_LDO_0_90V, \b SYSCTL_LDO_0_95V, \b SYSCTL_LDO_1_00V, +//! \b SYSCTL_LDO_1_05V, \b SYSCTL_LDO_1_10V, \b SYSCTL_LDO_1_15V, or +//! \b SYSCTL_LDO_1_20V. +// +//***************************************************************************** +uint32_t +SysCtlLDODeepSleepGet(void) +{ + // + // Return the deep-sleep-mode LDO voltage setting. + // + return(HWREG(SYSCTL_LDODPCTL)); +} + +//***************************************************************************** +// +//! Configures the power to the flash and SRAM while in sleep mode. +//! +//! \param ui32Config is the required flash and SRAM power configuration. +//! +//! This function allows the power configuration of the flash and SRAM while in +//! sleep mode to be set. The \e ui32Config parameter is the logical OR of the +//! flash power configuration and the SRAM power configuration. +//! +//! The flash power configuration is specified as either: +//! +//! - \b SYSCTL_FLASH_NORMAL - The flash is left in fully powered mode, +//! providing fast wake-up time but higher power consumption. +//! - \b SYSCTL_FLASH_LOW_POWER - The flash is in low power mode, providing +//! reduced power consumption but longer wake-up time. +//! +//! The SRAM power configuration is specified as one of: +//! +//! - \b SYSCTL_SRAM_NORMAL - The SRAM is left in fully powered mode, providing +//! fast wake-up time but higher power consumption. +//! - \b SYSCTL_SRAM_STANDBY - The SRAM is placed into a lower power mode, +//! providing reduced power consumption but longer wake-up time. +//! - \b SYSCTL_SRAM_LOW_POWER - The SRAM is placed into lowest power mode, +//! providing further reduced power consumption but longer wake-up time. +//! +//! \note The availability of this feature varies with the Tiva part in +//! use. Please consult the data sheet for the part you are using to determine +//! whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlSleepPowerSet(uint32_t ui32Config) +{ + // + // Set the sleep-mode flash and SRAM power configuration. + // + HWREG(SYSCTL_SLPPWRCFG) = ui32Config; +} + +//***************************************************************************** +// +//! Configures the power to the flash and SRAM while in deep-sleep mode. +//! +//! \param ui32Config is the required flash and SRAM power configuration. +//! +//! This function allows the power configuration of the flash and SRAM while in +//! deep-sleep mode to be set. The \e ui32Config parameter is the logical OR +//! of the flash power configuration and the SRAM power configuration. +//! +//! The flash power configuration is specified as either: +//! +//! - \b SYSCTL_FLASH_NORMAL - The flash is left in fully powered mode, +//! providing fast wake-up time but higher power consumption. +//! - \b SYSCTL_FLASH_LOW_POWER - The flash is in low power mode, providing +//! reduced power consumption but longer wake-up time. +//! +//! The SRAM power configuration is specified as one of: +//! +//! - \b SYSCTL_LDO_SLEEP - The LDO is in sleep mode. +//! - \b SYSCTL_TEMP_LOW_POWER - The temperature sensor in low power mode. +//! - \b SYSCTL_SRAM_NORMAL - The SRAM is left in fully powered mode, providing +//! fast wake-up time but higher power consumption. +//! - \b SYSCTL_SRAM_STANDBY - The SRAM is placed into a lower power mode, +//! providing reduced power consumption but longer wake-up time. +//! - \b SYSCTL_SRAM_LOW_POWER - The SRAM is placed into lowest power mode, +//! providing further reduced power consumption but longer wake-up time. +//! +//! \note The availability of this feature varies with the Tiva part in +//! use. Please consult the data sheet for the part you are using to determine +//! whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlDeepSleepPowerSet(uint32_t ui32Config) +{ + // + // Set the deep-sleep-mode flash and SRAM power configuration. + // + HWREG(SYSCTL_DSLPPWRCFG) = ui32Config; +} + +//***************************************************************************** +// +//! Resets the device. +//! +//! This function performs a software reset of the entire device. The +//! processor and all peripherals are reset and all device registers are +//! returned to their default values (with the exception of the reset cause +//! register, which maintains its current value but has the software reset +//! bit set as well). +//! +//! \return This function does not return. +// +//***************************************************************************** +void +SysCtlReset(void) +{ + // + // Perform a software reset request. This request causes the device to + // reset, no further code is executed. + // + HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | NVIC_APINT_SYSRESETREQ; + + // + // The device should have reset, so this should never be reached. Just in + // case, loop forever. + // + while(1) + { + } +} + +//***************************************************************************** +// +//! Puts the processor into sleep mode. +//! +//! This function places the processor into sleep mode; it does not return +//! until the processor returns to run mode. The peripherals that are enabled +//! via SysCtlPeripheralSleepEnable() continue to operate and can wake up the +//! processor (if automatic clock gating is enabled with +//! SysCtlPeripheralClockGating(), otherwise all peripherals continue to +//! operate). +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlSleep(void) +{ + // + // Wait for an interrupt. + // + CPUwfi(); +} + +//***************************************************************************** +// +//! Puts the processor into deep-sleep mode. +//! +//! This function places the processor into deep-sleep mode; it does not return +//! until the processor returns to run mode. The peripherals that are enabled +//! via SysCtlPeripheralDeepSleepEnable() continue to operate and can wake up +//! the processor (if automatic clock gating is enabled with +//! SysCtlPeripheralClockGating(), otherwise all peripherals continue to +//! operate). +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlDeepSleep(void) +{ + // + // Enable deep-sleep. + // + HWREG(NVIC_SYS_CTRL) |= NVIC_SYS_CTRL_SLEEPDEEP; + + // + // Wait for an interrupt. + // + CPUwfi(); + + // + // Disable deep-sleep so that a future sleep works correctly. + // + HWREG(NVIC_SYS_CTRL) &= ~(NVIC_SYS_CTRL_SLEEPDEEP); +} + +//***************************************************************************** +// +//! Gets the reason for a reset. +//! +//! This function returns the reason(s) for a reset. Because the reset +//! reasons are sticky until either cleared by software or a power-on reset, +//! multiple reset reasons may be returned if multiple resets have occurred. +//! The reset reason is a logical OR of \b SYSCTL_CAUSE_HSRVREQ, +//! \b SYSCTL_CAUSE_HIB, \b SYSCTL_CAUSE_WDOG1, \b SYSCTL_CAUSE_SW, +//! \b SYSCTL_CAUSE_WDOG0, \b SYSCTL_CAUSE_BOR, \b SYSCTL_CAUSE_POR, +//! and/or \b SYSCTL_CAUSE_EXT. +//! +//! \return Returns the reason(s) for a reset. +// +//***************************************************************************** +uint32_t +SysCtlResetCauseGet(void) +{ + // + // Return the reset reasons. + // + return(HWREG(SYSCTL_RESC)); +} + +//***************************************************************************** +// +//! Clears reset reasons. +//! +//! \param ui32Causes are the reset causes to be cleared; must be a logical OR +//! of \b SYSCTL_CAUSE_HSRVREQ, \b SYSCTL_CAUSE_HIB, \b SYSCTL_CAUSE_WDOG1, +//! \b SYSCTL_CAUSE_SW, \b SYSCTL_CAUSE_WDOG0, \b SYSCTL_CAUSE_BOR, +//! \b SYSCTL_CAUSE_POR, and/or \b SYSCTL_CAUSE_EXT. +//! +//! This function clears the specified sticky reset reasons. Once cleared, +//! another reset for the same reason can be detected, and a reset for a +//! different reason can be distinguished (instead of having two reset causes +//! set). If the reset reason is used by an application, all reset causes +//! should be cleared after they are retrieved with SysCtlResetCauseGet(). +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlResetCauseClear(uint32_t ui32Causes) +{ + // + // Clear the given reset reasons. + // + HWREG(SYSCTL_RESC) &= ~(ui32Causes); +} + +//***************************************************************************** +// +//! Provides a small delay. +//! +//! \param ui32Count is the number of delay loop iterations to perform. +//! +//! This function provides a means of generating a delay by executing a simple +//! 3 instruction cycle loop a given number of times. It is written in +//! assembly to keep the loop instruction count consistent across tool chains. +//! +//! It is important to note that this function does NOT provide an accurate +//! timing mechanism. Although the delay loop is 3 instruction cycles long, +//! the execution time of the loop will vary dramatically depending upon the +//! application's interrupt environment (the loop will be interrupted unless +//! run with interrupts disabled and this is generally an unwise thing to do) +//! and also the current system clock rate and flash timings (wait states and +//! the operation of the prefetch buffer affect the timing). +//! +//! For better accuracy, the ROM version of this function may be used. This +//! version will not suffer from flash- and prefect buffer-related timing +//! variability but will still be delayed by interrupt service routines. +//! +//! For best accuracy, a system timer should be used with code either polling +//! for a particular timer value being exceeded or processing the timer +//! interrupt to determine when a particular time period has elapsed. +//! +//! \return None. +// +//***************************************************************************** +#if defined(ewarm) || defined(DOXYGEN) +void +SysCtlDelay(uint32_t ui32Count) +{ + __asm(" subs r0, #1\n" + " bne.n SysCtlDelay\n" + " bx lr"); +} +#endif +#if defined(codered) || defined(gcc) || defined(sourcerygxx) +void __attribute__((naked)) +SysCtlDelay(uint32_t ui32Count) +{ + __asm(" subs r0, #1\n" + " bne SysCtlDelay\n" + " bx lr"); +} +#endif +#if defined(rvmdk) || defined(__ARMCC_VERSION) +__asm void +SysCtlDelay(uint32_t ui32Count) +{ + subs r0, #1; + bne SysCtlDelay; + bx lr; +} +#endif +// +// For CCS implement this function in pure assembly. This prevents the TI +// compiler from doing funny things with the optimizer. +// +#if defined(ccs) +__asm(" .sect \".text:SysCtlDelay\"\n" + " .clink\n" + " .thumbfunc SysCtlDelay\n" + " .thumb\n" + " .global SysCtlDelay\n" + "SysCtlDelay:\n" + " subs r0, #1\n" + " bne.n SysCtlDelay\n" + " bx lr\n"); +#endif + +//***************************************************************************** +// +//! Sets the configuration of the main oscillator (MOSC) control. +//! +//! \param ui32Config is the required configuration of the MOSC control. +//! +//! This function configures the control of the main oscillator. The +//! \e ui32Config is specified as the logical OR of the following values: +//! +//! - \b SYSCTL_MOSC_VALIDATE enables the MOSC verification circuit that +//! detects a failure of the main oscillator (such as a loss of the clock). +//! - \b SYSCTL_MOSC_INTERRUPT indicates that a MOSC failure should generate an +//! interrupt instead of resetting the processor. +//! - \b SYSCTL_MOSC_NO_XTAL indicates that there is no crystal or oscillator +//! connected to the OSC0/OSC1 pins, allowing power consumption to be +//! reduced. +//! - \b SYSCTL_MOSC_PWR_DIS disable power to the main oscillator. If this +//! parameter is not specified, the MOSC input remains powered. +//! - \b SYSCTL_MOSC_LOWFREQ MOSC is less than 10 MHz. +//! - \b SYSCTL_MOSC_HIGHFREQ MOSC is greater than 10 MHz. +//! - \b SYSCTL_MOSC_SESRC specifies that the MOSC is a single-ended +//! oscillator connected to OSC0. If this parameter is not specified, the +//! input is assumed to be a crystal. +//! +//! \note The availability of MOSC control varies based on the Tiva part +//! in use. Please consult the data sheet for the part you are using to +//! determine whether this support is available. In addition, the capability +//! of MOSC control varies based on the Tiva part in use. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlMOSCConfigSet(uint32_t ui32Config) +{ + // + // Configure the MOSC control. + // + HWREG(SYSCTL_MOSCCTL) = ui32Config; +} + +//***************************************************************************** +// +//! Calibrates the precision internal oscillator. +//! +//! \param ui32Type is the type of calibration to perform. +//! +//! This function performs a calibration of the PIOSC. There are three types +//! of calibration available; the desired calibration type as specified in +//! \e ui32Type is one of: +//! +//! - \b SYSCTL_PIOSC_CAL_AUTO to perform automatic calibration using the +//! 32-kHz clock from the hibernate module as a reference. This type is +//! only possible on parts that have a hibernate module, and then only if +//! it is enabled, a 32.768-kHz clock source is attached to the XOSC0/1 +//! pins and the hibernate module's RTC is also enabled. +//! +//! - \b SYSCTL_PIOSC_CAL_FACT to reset the PIOSC calibration to the factory +//! provided calibration. +//! +//! - \b SYSCTL_PIOSC_CAL_USER to set the PIOSC calibration to a user-supplied +//! value. The value to be used is ORed into the lower 7-bits of this value, +//! with 0x40 being the ``nominal'' value (in other words, if everything were +//! perfect, 0x40 provides exactly 16 MHz). Values larger than 0x40 +//! slow down PIOSC, and values smaller than 0x40 speed up PIOSC. +//! +//! \return Returns 1 if the calibration was successful and 0 if it failed. +// +//***************************************************************************** +uint32_t +SysCtlPIOSCCalibrate(uint32_t ui32Type) +{ + // + // Perform the requested calibration. If performing user calibration, the + // UTEN bit must be set with one write, then the UT field in a second + // write, and the UPDATE bit in a final write. For other calibration + // types, a single write to set UPDATE or CAL is all that is required. + // + if(ui32Type & (SYSCTL_PIOSCCAL_UTEN | SYSCTL_PIOSCCAL_UPDATE)) + { + HWREG(SYSCTL_PIOSCCAL) = ui32Type & SYSCTL_PIOSCCAL_UTEN; + HWREG(SYSCTL_PIOSCCAL) = + ui32Type & (SYSCTL_PIOSCCAL_UTEN | SYSCTL_PIOSCCAL_UT_M); + } + HWREG(SYSCTL_PIOSCCAL) = ui32Type; + + // + // See if an automatic calibration was requested. + // + if(ui32Type & SYSCTL_PIOSCCAL_CAL) + { + // + // Wait for the automatic calibration to complete. + // + while((HWREG(SYSCTL_PIOSCSTAT) & SYSCTL_PIOSCSTAT_CR_M) == 0) + { + } + + // + // If the automatic calibration failed, return an error. + // + if((HWREG(SYSCTL_PIOSCSTAT) & SYSCTL_PIOSCSTAT_CR_M) != + SYSCTL_PIOSCSTAT_CRPASS) + { + return(0); + } + } + + // + // The calibration was successful. + // + return(1); +} + +//***************************************************************************** +// +//! Sets the type of reset issued due to certain reset events. +//! +//! \param ui32Behavior specifies the types of resets for each of the +//! configurable reset events. +//! +//! This function sets the types of reset issued when a configurable reset +//! event occurs. The reset events that are configurable are: Watchdog 0 or 1, +//! a brown out and the external RSTn pin. The valid actions are either a +//! system reset or a full POR sequence. See the data sheet for more +//! information on the differences between a full POR and a system reset. All +//! reset behaviors can be configured with a single call using the logical OR +//! of the values defined below. Any reset option that is not specifically set +//! remains configured for its default behavior. Either POR or system reset +//! can be selected for each reset cause. +//! +//! Valid values are logical combinations of the following: +//! +//! - \b SYSCTL_ONRST_WDOG0_POR configures a Watchdog 0 reset to perform a full +//! POR. +//! - \b SYSCTL_ONRST_WDOG0_SYS configures a Watchdog 0 reset to perform a +//! system reset. +//! - \b SYSCTL_ONRST_WDOG1_POR configures a Watchdog 1 reset to perform a full +//! POR. +//! - \b SYSCTL_ONRST_WDOG1_SYS configures a Watchdog 1 reset to perform a +//! system reset. +//! - \b SYSCTL_ONRST_BOR_POR configures a brown-out reset to perform a full +//! POR. +//! - \b SYSCTL_ONRST_BOR_SYS configures a brown-out reset to perform a system +//! reset. +//! - \b SYSCTL_ONRST_EXT_POR configures an external pin reset to perform a +//! full POR. +//! - \b SYSCTL_ONRST_EXT_SYS configures an external pin reset to perform a +//! system reset. +//! +//! \b Example: Set Watchdog 0 reset to trigger a POR and a brown-out reset +//! to trigger a system reset while leaving the remaining resets with their +//! default behaviors. +//! +//! \verbatim +//! SysCtlResetBehaviorSet(SYSCTL_ONRST_WDOG0_POR | SYSCTL_ONRST_BOR_SYS); +//! \endverbatim +//! +//! \note This function cannot be used with TM4C123 devices. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlResetBehaviorSet(uint32_t ui32Behavior) +{ + HWREG(SYSCTL_RESBEHAVCTL) = ui32Behavior; +} + +//***************************************************************************** +// +//! Returns the current types of reset issued due to reset events. +//! +//! This function returns the types of resets issued when a configurable reset +//! occurs. The value returned is a logical OR combination of the valid values +//! that are described in the documentation for the \e ui32Behavior parameter +//! of the SysCtlResetBehaviorSet() function. +//! +//! \note This function should only be used with Flurry-class devices. +//! +//! \return The reset behaviors for all configurable resets. +// +//***************************************************************************** +uint32_t +SysCtlResetBehaviorGet(void) +{ + return(HWREG(SYSCTL_RESBEHAVCTL)); +} + +//***************************************************************************** +// +//! Configures the system clock. +//! +//! \param ui32Config is the required configuration of the device clocking. +//! \param ui32SysClock is the requested processor frequency. +//! +//! This function configures the main system clocking for the device. The +//! input frequency, oscillator source, whether or not to enable the PLL, and +//! the system clock divider are all configured with this function. This +//! function configures the system frequency to the closest available divisor +//! of one of the fixed PLL VCO settings provided in the \e ui32Config +//! parameter. The caller sets the \e ui32SysClock parameter to request the +//! system clock frequency, and this function then attempts to match this using +//! the values provided in the \e ui32Config parameter. If this function +//! cannot exactly match the requested frequency, it picks the closest +//! frequency that is lower than the requested frequency. The \e ui32Config +//! parameter provides the remaining configuration options using a set of +//! defines that are a logical OR of several different values, many of which +//! are grouped into sets where only one of the set can be chosen. This +//! function returns the current system frequency which may not match the +//! requested frequency. +//! +//! If the application is using an external crystal then the frequency is +//! set by using one of the following values: +//! \b SYSCTL_XTAL_5MHZ, \b SYSCTL_XTAL_6MHZ, \b SYSCTL_XTAL_8MHZ, +//! \b SYSCTL_XTAL_10MHZ, \b SYSCTL_XTAL_12MHZ, \b SYSCTL_XTAL_16MHZ, +//! \b SYSCTL_XTAL_18MHZ, \b SYSCTL_XTAL_20MHZ, \b SYSCTL_XTAL_24MHZ, or +//! \b SYSCTL_XTAL_25MHz. +//! +//! The oscillator source is chosen with one of the following values: +//! +//! - \b SYSCTL_OSC_MAIN to use an external crystal or oscillator. +//! - \b SYSCTL_OSC_INT to use the 16-MHz precision internal oscillator. +//! - \b SYSCTL_OSC_INT30 to use the internal low frequency oscillator. +//! - \b SYSCTL_OSC_EXT32 to use the hibernate modules 32.786-kHz oscillator. +//! This option is only available on devices that include the hibernation +//! module. +//! +//! The system clock source is chosen with one of the following values: +//! +//! - \b SYSCTL_USE_PLL is used to select the PLL output as the system clock. +//! - \b SYSCTL_USE_OSC is used to choose one of the oscillators as the +//! system clock. +//! +//! The PLL VCO frequency is chosen with one of the the following values: +//! +//! - \b SYSCTL_CFG_VCO_480 to set the PLL VCO output to 480-MHz +//! - \b SYSCTL_CFG_VCO_320 to set the PLL VCO output to 320-MHz +//! +//! Example: Configure the system clocking to be 40 MHz with a 320-MHz PLL +//! setting using the 16-MHz internal oscillator. +//! +//! \verbatim +//! SysCtlClockFreqSet(SYSCTL_OSC_INT | SYSCTL_USE_PLL | SYSCTL_CFG_VCO_320, +//! 40000000); +//! \endverbatim +//! +//! \note This function cannot be used with TM4C123 devices. For TM4C123 +//! devices use the SysCtlClockSet() function. +//! +//! \return The actual configured system clock frequency in Hz or zero if the +//! value could not be changed due to a parameter error or PLL lock failure. +// +//***************************************************************************** +uint32_t +SysCtlClockFreqSet(uint32_t ui32Config, uint32_t ui32SysClock) +{ + int32_t i32Timeout, i32VCOIdx, i32XtalIdx; + uint32_t ui32MOSCCTL; + uint32_t ui32Delay; + uint32_t ui32SysDiv, ui32Osc, ui32OscSelect, ui32RSClkConfig; + + // + // TM4C123 devices should not use this function. + // + if(CLASS_IS_TM4C123) + { + return(0); + } + + // + // Get the index of the crystal from the ui32Config parameter. + // + i32XtalIdx = SysCtlXtalCfgToIndex(ui32Config); + + // + // Determine which non-PLL source was selected. + // + if((ui32Config & 0x38) == SYSCTL_OSC_INT) + { + // + // Use the nominal frequency for the PIOSC oscillator and set the + // crystal select. + // + ui32Osc = 16000000; + ui32OscSelect = SYSCTL_RSCLKCFG_OSCSRC_PIOSC; + ui32OscSelect |= SYSCTL_RSCLKCFG_PLLSRC_PIOSC; + + // + // Force the crystal index to the value for 16-MHz. + // + i32XtalIdx = SysCtlXtalCfgToIndex(SYSCTL_XTAL_16MHZ); + } + else if((ui32Config & 0x38) == SYSCTL_OSC_INT30) + { + // + // Use the nominal frequency for the low frequency oscillator. + // + ui32Osc = 30000; + ui32OscSelect = SYSCTL_RSCLKCFG_OSCSRC_LFIOSC; + } + else if((ui32Config & 0x38) == (SYSCTL_OSC_EXT32 & 0x38)) + { + // + // Use the RTC frequency. + // + ui32Osc = 32768; + ui32OscSelect = SYSCTL_RSCLKCFG_OSCSRC_RTC; + } + else if((ui32Config & 0x38) == SYSCTL_OSC_MAIN) + { + // + // Bounds check the source frequency for the main oscillator. The is + // because the PLL tables in the g_pppui32XTALtoVCO structure range + // from 5MHz to 25MHz. + // + if((i32XtalIdx > (SysCtlXtalCfgToIndex(SYSCTL_XTAL_25MHZ))) || + (i32XtalIdx < (SysCtlXtalCfgToIndex(SYSCTL_XTAL_5MHZ)))) + { + return(0); + } + + ui32Osc = g_pui32Xtals[i32XtalIdx]; + + // + // Set the PLL source select to MOSC. + // + ui32OscSelect = SYSCTL_RSCLKCFG_OSCSRC_MOSC; + ui32OscSelect |= SYSCTL_RSCLKCFG_PLLSRC_MOSC; + + // + // Clear MOSC power down, high oscillator range setting, and no crystal + // present setting. + // + ui32MOSCCTL = HWREG(SYSCTL_MOSCCTL) & + ~(SYSCTL_MOSCCTL_OSCRNG | SYSCTL_MOSCCTL_PWRDN | + SYSCTL_MOSCCTL_NOXTAL); + + // + // Increase the drive strength for MOSC of 10 MHz and above. + // + if(i32XtalIdx >= (SysCtlXtalCfgToIndex(SYSCTL_XTAL_10MHZ) - + (SysCtlXtalCfgToIndex(SYSCTL_XTAL_5MHZ)))) + { + ui32MOSCCTL |= SYSCTL_MOSCCTL_OSCRNG; + } + + HWREG(SYSCTL_MOSCCTL) = ui32MOSCCTL; + + // + // Timeout using the legacy delay value. + // + ui32Delay = 524288; + + while((HWREG(SYSCTL_RIS) & SYSCTL_RIS_MOSCPUPRIS) == 0) + { + ui32Delay--; + + if(ui32Delay == 0) + { + break; + } + } + + // + // If the main oscillator failed to start up then do not switch to + // it and return. + // + if(ui32Delay == 0) + { + return(0); + } + + + } + else + { + // + // This was an invalid request because no oscillator source was + // indicated. + // + ui32Osc = 0; + ui32OscSelect = SYSCTL_RSCLKCFG_OSCSRC_PIOSC; + } + + // + // Check if the running with the PLL enabled was requested. + // + if((ui32Config & SYSCTL_USE_OSC) == SYSCTL_USE_PLL) + { + // + // ui32Config must be SYSCTL_OSC_MAIN or SYSCTL_OSC_INT. + // + if(((ui32Config & 0x38) != SYSCTL_OSC_MAIN) && + ((ui32Config & 0x38) != SYSCTL_OSC_INT)) + { + return(0); + } + + // + // Get the VCO index out of the ui32Config parameter. + // + i32VCOIdx = (ui32Config >> 24) & 7; + + // + // Check that the VCO index is not out of bounds. + // + ASSERT(i32VCOIdx < MAX_VCO_ENTRIES); + + // + // Set the memory timings for the maximum external frequency since + // this could be a switch to PIOSC or possibly to MOSC which can be + // up to 25MHz. + // + HWREG(SYSCTL_MEMTIM0) = _SysCtlMemTimingGet(25000000); + + // + // Clear the old PLL divider and source in case it was set. + // + ui32RSClkConfig = HWREG(SYSCTL_RSCLKCFG) & + ~(SYSCTL_RSCLKCFG_PSYSDIV_M | + SYSCTL_RSCLKCFG_OSCSRC_M | + SYSCTL_RSCLKCFG_PLLSRC_M | SYSCTL_RSCLKCFG_USEPLL); + + // + // Update the memory timings to match running from PIOSC. + // + ui32RSClkConfig |= SYSCTL_RSCLKCFG_MEMTIMU; + + // + // Update clock configuration to switch back to PIOSC. + // + HWREG(SYSCTL_RSCLKCFG) = ui32RSClkConfig; + + // + // The table starts at 5 MHz so modify the index to match this. + // + i32XtalIdx -= SysCtlXtalCfgToIndex(SYSCTL_XTAL_5MHZ); + + // + // Calculate the System divider such that we get a frequency that is + // the closest to the requested frequency without going over. + // + ui32SysDiv = (g_pui32VCOFrequencies[i32VCOIdx] + ui32SysClock - 1) / + ui32SysClock; + + // + // Set the oscillator source. + // + HWREG(SYSCTL_RSCLKCFG) |= ui32OscSelect; + + // + // Set the M, N and Q values provided from the table and preserve + // the power state of the main PLL. + // + HWREG(SYSCTL_PLLFREQ1) = + g_pppui32XTALtoVCO[i32VCOIdx][i32XtalIdx][1]; + HWREG(SYSCTL_PLLFREQ1) |= PLL_Q_TO_REG(ui32SysDiv); + HWREG(SYSCTL_PLLFREQ0) = + (g_pppui32XTALtoVCO[i32VCOIdx][i32XtalIdx][0] | + (HWREG(SYSCTL_PLLFREQ0) & SYSCTL_PLLFREQ0_PLLPWR)); + + // + // Calculate the actual system clock as PSYSDIV is always div-by 2. + // + ui32SysClock = _SysCtlFrequencyGet(ui32Osc) / 2; + + // + // Set the Flash and EEPROM timing values. + // + HWREG(SYSCTL_MEMTIM0) = _SysCtlMemTimingGet(ui32SysClock); + + // + // Check if the PLL is already powered up. + // + if(HWREG(SYSCTL_PLLFREQ0) & SYSCTL_PLLFREQ0_PLLPWR) + { + // + // Trigger the PLL to lock to the new frequency. + // + HWREG(SYSCTL_RSCLKCFG) |= SYSCTL_RSCLKCFG_NEWFREQ; + } + else + { + // + // Power up the PLL. + // + HWREG(SYSCTL_PLLFREQ0) |= SYSCTL_PLLFREQ0_PLLPWR; + } + + // + // Wait until the PLL has locked. + // + for(i32Timeout = 32768; i32Timeout > 0; i32Timeout--) + { + if((HWREG(SYSCTL_PLLSTAT) & SYSCTL_PLLSTAT_LOCK)) + { + break; + } + } + + // + // If the loop above did not timeout then switch over to the PLL + // + if(i32Timeout) + { + ui32RSClkConfig = HWREG(SYSCTL_RSCLKCFG); + ui32RSClkConfig |= (1 << SYSCTL_RSCLKCFG_PSYSDIV_S) | + ui32OscSelect | SYSCTL_RSCLKCFG_USEPLL; + ui32RSClkConfig |= SYSCTL_RSCLKCFG_MEMTIMU; + + // + // Set the new clock configuration. + // + HWREG(SYSCTL_RSCLKCFG) = ui32RSClkConfig; + } + else + { + ui32SysClock = 0; + } + } + else + { + // + // Set the Flash and EEPROM timing values for PIOSC. + // + HWREG(SYSCTL_MEMTIM0) = _SysCtlMemTimingGet(16000000); + + // + // Make sure that the PLL is powered down since it is not being used. + // + HWREG(SYSCTL_PLLFREQ0) &= ~SYSCTL_PLLFREQ0_PLLPWR; + + // + // Clear the old PLL divider and source in case it was set. + // + ui32RSClkConfig = HWREG(SYSCTL_RSCLKCFG); + ui32RSClkConfig &= ~(SYSCTL_RSCLKCFG_OSYSDIV_M | + SYSCTL_RSCLKCFG_OSCSRC_M | + SYSCTL_RSCLKCFG_USEPLL); + + // + // Update the memory timings. + // + ui32RSClkConfig |= SYSCTL_RSCLKCFG_MEMTIMU; + + // + // Set the new clock configuration. + // + HWREG(SYSCTL_RSCLKCFG) = ui32RSClkConfig; + + // + // If zero given as the system clock then default to divide by 1. + // + if(ui32SysClock == 0) + { + ui32SysDiv = 0; + } + else + { + // + // Calculate the System divider based on the requested + // frequency. + // + ui32SysDiv = ui32Osc / ui32SysClock; + + // + // If the system divisor is not already zero, subtract one to + // set the value in the register which requires the value to + // be n-1. + // + if(ui32SysDiv != 0) + { + ui32SysDiv -= 1; + } + + // + // Calculate the system clock. + // + ui32SysClock = ui32Osc / (ui32SysDiv + 1); + } + + // + // Set the memory timing values for the new system clock. + // + HWREG(SYSCTL_MEMTIM0) = _SysCtlMemTimingGet(ui32SysClock); + + // + // Set the new system clock values. + // + ui32RSClkConfig = HWREG(SYSCTL_RSCLKCFG); + ui32RSClkConfig |= (ui32SysDiv << SYSCTL_RSCLKCFG_OSYSDIV_S) | + ui32OscSelect; + + // + // Update the memory timings. + // + ui32RSClkConfig |= SYSCTL_RSCLKCFG_MEMTIMU; + + // + // Set the new clock configuration. + // + HWREG(SYSCTL_RSCLKCFG) = ui32RSClkConfig; + } + + // + // Finally change the OSCSRC back to PIOSC + // + HWREG(SYSCTL_RSCLKCFG) &= ~(SYSCTL_RSCLKCFG_OSCSRC_M); + + return(ui32SysClock); +} + +//***************************************************************************** +// +//! Sets the clocking of the device. +//! +//! \param ui32Config is the required configuration of the device clocking. +//! +//! This function configures the clocking of the device. The input crystal +//! frequency, oscillator to be used, use of the PLL, and the system clock +//! divider are all configured with this function. +//! +//! The \e ui32Config parameter is the logical OR of several different values, +//! many of which are grouped into sets where only one can be chosen. +//! +//! The system clock divider is chosen with one of the following values: +//! \b SYSCTL_SYSDIV_1, \b SYSCTL_SYSDIV_2, \b SYSCTL_SYSDIV_3, ... +//! \b SYSCTL_SYSDIV_64. +//! +//! The use of the PLL is chosen with either \b SYSCTL_USE_PLL or +//! \b SYSCTL_USE_OSC. +//! +//! The external crystal frequency is chosen with one of the following values: +//! \b SYSCTL_XTAL_4MHZ, \b SYSCTL_XTAL_4_09MHZ, \b SYSCTL_XTAL_4_91MHZ, +//! \b SYSCTL_XTAL_5MHZ, \b SYSCTL_XTAL_5_12MHZ, \b SYSCTL_XTAL_6MHZ, +//! \b SYSCTL_XTAL_6_14MHZ, \b SYSCTL_XTAL_7_37MHZ, \b SYSCTL_XTAL_8MHZ, +//! \b SYSCTL_XTAL_8_19MHZ, \b SYSCTL_XTAL_10MHZ, \b SYSCTL_XTAL_12MHZ, +//! \b SYSCTL_XTAL_12_2MHZ, \b SYSCTL_XTAL_13_5MHZ, \b SYSCTL_XTAL_14_3MHZ, +//! \b SYSCTL_XTAL_16MHZ, \b SYSCTL_XTAL_16_3MHZ, \b SYSCTL_XTAL_18MHZ, +//! \b SYSCTL_XTAL_20MHZ, \b SYSCTL_XTAL_24MHZ, or \b SYSCTL_XTAL_25MHz. +//! Values below \b SYSCTL_XTAL_5MHZ are not valid when the PLL is in +//! operation. +//! +//! The oscillator source is chosen with one of the following values: +//! \b SYSCTL_OSC_MAIN, \b SYSCTL_OSC_INT, \b SYSCTL_OSC_INT4, +//! \b SYSCTL_OSC_INT30, or \b SYSCTL_OSC_EXT32. \b SYSCTL_OSC_EXT32 is only +//! available on devices with the hibernate module, and then only when the +//! hibernate module has been enabled. +//! +//! The internal and main oscillators are disabled with the +//! \b SYSCTL_INT_OSC_DIS and \b SYSCTL_MAIN_OSC_DIS flags, respectively. +//! The external oscillator must be enabled in order to use an external clock +//! source. Note that attempts to disable the oscillator used to clock the +//! device is prevented by the hardware. +//! +//! To clock the system from an external source (such as an external crystal +//! oscillator), use \b SYSCTL_USE_OSC \b | \b SYSCTL_OSC_MAIN. To clock the +//! system from the main oscillator, use \b SYSCTL_USE_OSC \b | +//! \b SYSCTL_OSC_MAIN. To clock the system from the PLL, use +//! \b SYSCTL_USE_PLL \b | \b SYSCTL_OSC_MAIN, and select the appropriate +//! crystal with one of the \b SYSCTL_XTAL_xxx values. +//! +//! \note This function should only be called on TM4C123 devices. For +//! all other devices use the SysCtlClockFreqSet() function. +//! +//! \note If selecting the PLL as the system clock source (that is, via +//! \b SYSCTL_USE_PLL), this function polls the PLL lock interrupt to +//! determine when the PLL has locked. If an interrupt handler for the +//! system control interrupt is in place, and it responds to and clears the +//! PLL lock interrupt, this function delays until its timeout has occurred +//! instead of completing as soon as PLL lock is achieved. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlClockSet(uint32_t ui32Config) +{ + uint32_t ui32Delay, ui32RCC, ui32RCC2; + + // + // Get the current value of the RCC and RCC2 registers. + // + ui32RCC = HWREG(SYSCTL_RCC); + ui32RCC2 = HWREG(SYSCTL_RCC2); + + // + // Bypass the PLL and system clock dividers for now. + // + ui32RCC |= SYSCTL_RCC_BYPASS; + ui32RCC &= ~(SYSCTL_RCC_USESYSDIV); + ui32RCC2 |= SYSCTL_RCC2_BYPASS2; + + // + // Write the new RCC value. + // + HWREG(SYSCTL_RCC) = ui32RCC; + HWREG(SYSCTL_RCC2) = ui32RCC2; + + // + // See if the oscillator needs to be enabled. + // + if((ui32RCC & SYSCTL_RCC_MOSCDIS) && !(ui32Config & SYSCTL_MAIN_OSC_DIS)) + { + // + // Make sure that the required oscillators are enabled. For now, the + // previously enabled oscillators must be enabled along with the newly + // requested oscillators. + // + ui32RCC &= (~SYSCTL_RCC_MOSCDIS | (ui32Config & SYSCTL_MAIN_OSC_DIS)); + + // + // Clear the MOSC power up raw interrupt status to be sure it is not + // set when waiting below. + // + HWREG(SYSCTL_MISC) = SYSCTL_MISC_MOSCPUPMIS; + + // + // Write the new RCC value. + // + HWREG(SYSCTL_RCC) = ui32RCC; + + // + // Timeout using the legacy delay value. + // + ui32Delay = 524288; + + while((HWREG(SYSCTL_RIS) & SYSCTL_RIS_MOSCPUPRIS) == 0) + { + ui32Delay--; + + if(ui32Delay == 0) + { + break; + } + } + + // + // If the main oscillator failed to start up then do not switch to + // it and return. + // + if(ui32Delay == 0) + { + return; + } + + } + + // + // Set the new crystal value and oscillator source. Because the OSCSRC2 + // field in RCC2 overlaps the XTAL field in RCC, the OSCSRC field has a + // special encoding within ui32Config to avoid the overlap. + // + ui32RCC &= ~(SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M); + ui32RCC |= ui32Config & (SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M); + ui32RCC2 &= ~(SYSCTL_RCC2_USERCC2 | SYSCTL_RCC2_OSCSRC2_M); + ui32RCC2 |= ui32Config & (SYSCTL_RCC2_USERCC2 | SYSCTL_RCC_OSCSRC_M); + ui32RCC2 |= (ui32Config & 0x00000008) << 3; + + // + // Write the new RCC value. + // + HWREG(SYSCTL_RCC) = ui32RCC; + HWREG(SYSCTL_RCC2) = ui32RCC2; + + // + // Set the PLL configuration. + // + ui32RCC &= ~SYSCTL_RCC_PWRDN; + ui32RCC |= ui32Config & SYSCTL_RCC_PWRDN; + ui32RCC2 &= ~SYSCTL_RCC2_PWRDN2; + ui32RCC2 |= ui32Config & SYSCTL_RCC2_PWRDN2; + + // + // Clear the PLL lock interrupt. + // + HWREG(SYSCTL_MISC) = SYSCTL_MISC_PLLLMIS; + + // + // Write the new RCC value. + // + if(ui32RCC2 & SYSCTL_RCC2_USERCC2) + { + HWREG(SYSCTL_RCC2) = ui32RCC2; + HWREG(SYSCTL_RCC) = ui32RCC; + } + else + { + HWREG(SYSCTL_RCC) = ui32RCC; + HWREG(SYSCTL_RCC2) = ui32RCC2; + } + + // + // Set the requested system divider and disable the appropriate + // oscillators. This value is not written immediately. + // + ui32RCC &= ~(SYSCTL_RCC_SYSDIV_M | SYSCTL_RCC_USESYSDIV | + SYSCTL_RCC_MOSCDIS); + ui32RCC |= ui32Config & (SYSCTL_RCC_SYSDIV_M | SYSCTL_RCC_USESYSDIV | + SYSCTL_RCC_MOSCDIS); + ui32RCC2 &= ~(SYSCTL_RCC2_SYSDIV2_M); + ui32RCC2 |= ui32Config & SYSCTL_RCC2_SYSDIV2_M; + if(ui32Config & SYSCTL_RCC2_DIV400) + { + ui32RCC |= SYSCTL_RCC_USESYSDIV; + ui32RCC2 &= ~(SYSCTL_RCC_USESYSDIV); + ui32RCC2 |= ui32Config & (SYSCTL_RCC2_DIV400 | SYSCTL_RCC2_SYSDIV2LSB); + } + else + { + ui32RCC2 &= ~(SYSCTL_RCC2_DIV400); + } + + // + // See if the PLL output is being used to clock the system. + // + if(!(ui32Config & SYSCTL_RCC_BYPASS)) + { + // + // Wait until the PLL has locked. + // + for(ui32Delay = 32768; ui32Delay > 0; ui32Delay--) + { + if((HWREG(SYSCTL_PLLSTAT) & SYSCTL_PLLSTAT_LOCK)) + { + break; + } + } + + // + // Enable use of the PLL. + // + ui32RCC &= ~(SYSCTL_RCC_BYPASS); + ui32RCC2 &= ~(SYSCTL_RCC2_BYPASS2); + } + + // + // Write the final RCC value. + // + HWREG(SYSCTL_RCC) = ui32RCC; + HWREG(SYSCTL_RCC2) = ui32RCC2; + + // + // Delay for a little bit so that the system divider takes effect. + // + SysCtlDelay(16); +} + +//***************************************************************************** +// +//! Gets the processor clock rate. +//! +//! This function determines the clock rate of the processor clock, which is +//! also the clock rate of the peripheral modules (with the exception of +//! PWM, which has its own clock divider; other peripherals may have different +//! clocking, see the device data sheet for details). +//! +//! \note This cannot return accurate results if SysCtlClockSet() has not +//! been called to configure the clocking of the device, or if the device is +//! directly clocked from a crystal (or a clock source) that is not one of the +//! supported crystal frequencies. In the latter case, this function should be +//! modified to directly return the correct system clock rate. +//! +//! \note This function can only be called on TM4C123 devices. For TM4C129 +//! devices, the return value from SysCtlClockFreqSet() indicates the system +//! clock frequency. +//! +//! \return The processor clock rate for TM4C123 devices only. +// +//***************************************************************************** +uint32_t +SysCtlClockGet(void) +{ + uint32_t ui32RCC, ui32RCC2, ui32PLL, ui32Clk, ui32Max; + uint32_t ui32PLL1; + + // + // This function is only valid on TM4C123 devices. + // + ASSERT(CLASS_IS_TM4C123); + + // + // Read RCC and RCC2. + // + ui32RCC = HWREG(SYSCTL_RCC); + ui32RCC2 = HWREG(SYSCTL_RCC2); + + // + // Get the base clock rate. + // + switch((ui32RCC2 & SYSCTL_RCC2_USERCC2) ? + (ui32RCC2 & SYSCTL_RCC2_OSCSRC2_M) : + (ui32RCC & SYSCTL_RCC_OSCSRC_M)) + { + // + // The main oscillator is the clock source. Determine its rate from + // the crystal setting field. + // + case SYSCTL_RCC_OSCSRC_MAIN: + { + ui32Clk = g_pui32Xtals[(ui32RCC & SYSCTL_RCC_XTAL_M) >> + SYSCTL_RCC_XTAL_S]; + break; + } + + // + // The internal oscillator is the source clock. + // + case SYSCTL_RCC_OSCSRC_INT: + { + // + // The internal oscillator on all devices is 16 MHz. + // + ui32Clk = 16000000; + break; + } + + // + // The internal oscillator divided by four is the source clock. + // + case SYSCTL_RCC_OSCSRC_INT4: + { + // + // The internal oscillator on all devices is 16 MHz. + // + ui32Clk = 16000000 / 4; + break; + } + + // + // The internal 30-KHz oscillator is the source clock. + // + case SYSCTL_RCC_OSCSRC_30: + { + // + // The internal 30-KHz oscillator has an accuracy of +/- 30%. + // + ui32Clk = 30000; + break; + } + + // + // The 32.768-KHz clock from the hibernate module is the source clock. + // + case SYSCTL_RCC2_OSCSRC2_32: + { + ui32Clk = 32768; + break; + } + + // + // An unknown setting, so return a zero clock (that is, an unknown + // clock rate). + // + default: + { + return(0); + } + } + + // + // Default the maximum frequency to the maximum 32-bit unsigned value. + // + ui32Max = 0xffffffff; + + // + // See if the PLL is being used. + // + if(((ui32RCC2 & SYSCTL_RCC2_USERCC2) && + !(ui32RCC2 & SYSCTL_RCC2_BYPASS2)) || + (!(ui32RCC2 & SYSCTL_RCC2_USERCC2) && !(ui32RCC & SYSCTL_RCC_BYPASS))) + { + // + // Read the two PLL frequency registers. The formula for a + // TM4C123 device is "(xtal * m) / ((q + 1) * (n + 1))". + // + ui32PLL = HWREG(SYSCTL_PLLFREQ0); + ui32PLL1 = HWREG(SYSCTL_PLLFREQ1); + + // + // Divide the input clock by the dividers. + // + ui32Clk /= ((((ui32PLL1 & SYSCTL_PLLFREQ1_Q_M) >> + SYSCTL_PLLFREQ1_Q_S) + 1) * + (((ui32PLL1 & SYSCTL_PLLFREQ1_N_M) >> + SYSCTL_PLLFREQ1_N_S) + 1) * 2); + + // + // Multiply the clock by the multiplier, which is split into an + // integer part and a fractional part. + // + ui32Clk = ((ui32Clk * ((ui32PLL & SYSCTL_PLLFREQ0_MINT_M) >> + SYSCTL_PLLFREQ0_MINT_S)) + + ((ui32Clk * ((ui32PLL & SYSCTL_PLLFREQ0_MFRAC_M) >> + SYSCTL_PLLFREQ0_MFRAC_S)) >> 10)); + + // + // Force the system divider to be enabled. It is always used when + // using the PLL, but in some cases it does not read as being enabled. + // + ui32RCC |= SYSCTL_RCC_USESYSDIV; + + // + // Calculate the maximum system frequency. + // + switch(HWREG(SYSCTL_DC1) & SYSCTL_DC1_MINSYSDIV_M) + { + case SYSCTL_DC1_MINSYSDIV_80: + { + ui32Max = 80000000; + break; + } + case SYSCTL_DC1_MINSYSDIV_50: + { + ui32Max = 50000000; + break; + } + case SYSCTL_DC1_MINSYSDIV_40: + { + ui32Max = 40000000; + break; + } + case SYSCTL_DC1_MINSYSDIV_25: + { + ui32Max = 25000000; + break; + } + case SYSCTL_DC1_MINSYSDIV_20: + { + ui32Max = 20000000; + break; + } + default: + { + break; + } + } + } + + // + // See if the system divider is being used. + // + if(ui32RCC & SYSCTL_RCC_USESYSDIV) + { + // + // Adjust the clock rate by the system clock divider. + // + if(ui32RCC2 & SYSCTL_RCC2_USERCC2) + { + if((ui32RCC2 & SYSCTL_RCC2_DIV400) && + (((ui32RCC2 & SYSCTL_RCC2_USERCC2) && + !(ui32RCC2 & SYSCTL_RCC2_BYPASS2)) || + (!(ui32RCC2 & SYSCTL_RCC2_USERCC2) && + !(ui32RCC & SYSCTL_RCC_BYPASS)))) + + { + ui32Clk = ((ui32Clk * 2) / (((ui32RCC2 & + (SYSCTL_RCC2_SYSDIV2_M | + SYSCTL_RCC2_SYSDIV2LSB)) >> + (SYSCTL_RCC2_SYSDIV2_S - 1)) + + 1)); + } + else + { + ui32Clk /= (((ui32RCC2 & SYSCTL_RCC2_SYSDIV2_M) >> + SYSCTL_RCC2_SYSDIV2_S) + 1); + } + } + else + { + ui32Clk /= (((ui32RCC & SYSCTL_RCC_SYSDIV_M) >> + SYSCTL_RCC_SYSDIV_S) + 1); + } + } + + // + // Limit the maximum clock to the maximum clock frequency. + // + if(ui32Max < ui32Clk) + { + ui32Clk = ui32Max; + } + + // + // Return the computed clock rate. + // + return(ui32Clk); +} + +//***************************************************************************** +// +//! Sets the clocking of the device while in deep-sleep mode. +//! +//! \param ui32Config is the required configuration of the device clocking +//! while in deep-sleep mode. +//! +//! This function configures the clocking of the device while in deep-sleep +//! mode. The oscillator to be used and the system clock divider are +//! configured with this function. +//! +//! The \e ui32Config parameter is the logical OR of the following values: +//! +//! The system clock divider is chosen from one of the following values: +//! \b SYSCTL_DSLP_DIV_1, \b SYSCTL_DSLP_DIV_2, \b SYSCTL_DSLP_DIV_3, ... +//! \b SYSCTL_DSLP_DIV_64. +//! +//! The oscillator source is chosen from one of the following values: +//! \b SYSCTL_DSLP_OSC_MAIN, \b SYSCTL_DSLP_OSC_INT, \b SYSCTL_DSLP_OSC_INT30, +//! or \b SYSCTL_DSLP_OSC_EXT32. \b SYSCTL_OSC_EXT32 is only available on +//! devices with the hibernation module, and then only when the hibernation +//! module has been enabled. +//! +//! The precision internal oscillator can be powered down in deep-sleep mode by +//! specifying \b SYSCTL_DSLP_PIOSC_PD. The precision internal oscillator is +//! not powered down if it is required for operation while in deep-sleep +//! (based on other configuration settings.) +//! +//! \note This function should only be called on TM4C123 devices. For +//! other devices use the SysCtlDeepSleepClockConfigSet() function. +//! +//! \note The availability of deep-sleep clocking configuration varies with the +//! Tiva part in use. Please consult the data sheet for the part you are +//! using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlDeepSleepClockSet(uint32_t ui32Config) +{ + // + // Set the deep-sleep clock configuration. + // + HWREG(SYSCTL_DSLPCLKCFG) = ui32Config; +} + +//***************************************************************************** +// +//! Sets the clock configuration of the device while in deep-sleep mode. +//! +//! \param ui32Div is the clock divider when in deep-sleep mode. +//! \param ui32Config is the configuration of the device clocking while +//! in deep-sleep mode. +//! +//! This function configures the clocking of the device while in deep-sleep +//! mode. The \e ui32Config parameter selects the oscillator and the +//! \e ui32Div parameter sets the clock divider used in deep-sleep mode. The +//! valid values for the \e ui32Div parameter range from 1 to 1024, however not +//! all Tiva microcontrollers support this full range. This function +//! replaces the SysCtlDeepSleepClockSet() function and can be used on +//! Tiva devices that support deep-sleep mode. +//! +//! The oscillator source is chosen from one of the following values: +//! \b SYSCTL_DSLP_OSC_MAIN, \b SYSCTL_DSLP_OSC_INT, \b SYSCTL_DSLP_OSC_INT30, +//! or \b SYSCTL_DSLP_OSC_EXT32. The \b SYSCTL_DSLP_OSC_EXT32 option is only +//! available on devices with the hibernation module, and then only when the +//! hibernation module is enabled. +//! +//! The precision internal oscillator can be powered down in deep-sleep mode by +//! specifying \b SYSCTL_DSLP_PIOSC_PD. The precision internal oscillator is +//! not powered down if it is required for operation while in deep-sleep +//! (based on other configuration settings). +//! +//! The main oscillator can be powered down in deep-sleep mode by +//! specifying \b SYSCTL_DSLP_MOSC_PD. The main oscillator is +//! not powered down if it is required for operation while in deep-sleep +//! (based on other configuration settings). +//! +//! \note The availability of deep-sleep clocking configuration and the +//! configuration values vary with the Tiva device in use. Please consult +//! the data sheet for the device you are using to determine whether the +//! desired configuration options are available and to determine the valid +//! range for the clock divider. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlDeepSleepClockConfigSet(uint32_t ui32Div, uint32_t ui32Config) +{ + uint32_t ui32Value; + + ASSERT(ui32Div != 0); + + if(CLASS_IS_TM4C123) + { + // + // Set the deep-sleep clock configuration. + // + HWREG(SYSCTL_DSLPCLKCFG) = (ui32Config & ~SYSCTL_DSLPCLKCFG_D_M) | + ((ui32Div - 1) << SYSCTL_DSLPCLKCFG_D_S); + } + else + { + // + // Initialize the value with the divider. + // + ui32Value = ui32Div - 1; + + // + // Set the clock source selection based on the defines used for + // SysCtlDeepSleepClockSet() function so that there is some backwards + // compatibility. + // + switch(ui32Config & SYSCTL_DSLPCLKCFG_O_M) + { + // + // Choose the main external oscillator. + // + case SYSCTL_DSLP_OSC_MAIN: + { + ui32Value |= SYSCTL_DSCLKCFG_DSOSCSRC_MOSC; + + break; + } + + // + // Choose the low frequency oscillator. + // + case SYSCTL_DSLP_OSC_INT30: + { + ui32Value |= SYSCTL_DSCLKCFG_DSOSCSRC_LFIOSC; + + break; + } + + // + // Choose the low frequency oscillator. + // + case SYSCTL_DSLP_OSC_EXT32: + { + ui32Value |= SYSCTL_DSCLKCFG_DSOSCSRC_RTC; + + break; + } + // + // The zero value uses the PIOSC as the clock source. + // + case SYSCTL_DSLP_OSC_INT: + default: + { + break; + } + } + + // + // Set the PIOSC power down bit. + // + if(ui32Config & SYSCTL_DSLP_PIOSC_PD) + { + ui32Value |= SYSCTL_DSCLKCFG_PIOSCPD; + } + + // + // Set the PIOSC power down bit. + // + if(ui32Config & SYSCTL_DSLP_MOSC_PD) + { + ui32Value |= SYSCTL_DSCLKCFG_MOSCDPD; + } + + // + // Update the deep-sleep clock configuration. + // + HWREG(SYSCTL_DSCLKCFG) = ui32Value; + } +} + +//***************************************************************************** +// +//! Sets the PWM clock configuration. +//! +//! \param ui32Config is the configuration for the PWM clock; it must be one of +//! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4, +//! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or +//! \b SYSCTL_PWMDIV_64. +//! +//! This function configures the rate of the clock provided to the PWM module +//! as a ratio of the processor clock. This clock is used by the PWM module to +//! generate PWM signals; its rate forms the basis for all PWM signals. +//! +//! \note This function should only be used with TM4C123 devices. For +//! other TM4C devices, the PWMClockSet() function should be used. +//! +//! \note The clocking of the PWM is dependent on the system clock rate as +//! configured by SysCtlClockSet(). +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPWMClockSet(uint32_t ui32Config) +{ + // + // Check the arguments. + // + ASSERT((ui32Config == SYSCTL_PWMDIV_1) || + (ui32Config == SYSCTL_PWMDIV_2) || + (ui32Config == SYSCTL_PWMDIV_4) || + (ui32Config == SYSCTL_PWMDIV_8) || + (ui32Config == SYSCTL_PWMDIV_16) || + (ui32Config == SYSCTL_PWMDIV_32) || + (ui32Config == SYSCTL_PWMDIV_64)); + + // + // Check that there is a PWM block on this part. + // + ASSERT(HWREG(SYSCTL_DC1) & (SYSCTL_DC1_PWM0 | SYSCTL_DC1_PWM1)); + + // + // Set the PWM clock configuration into the run-mode clock configuration + // register. + // + HWREG(SYSCTL_RCC) = ((HWREG(SYSCTL_RCC) & + ~(SYSCTL_RCC_USEPWMDIV | SYSCTL_RCC_PWMDIV_M)) | + ui32Config); +} + +//***************************************************************************** +// +//! Gets the current PWM clock configuration. +//! +//! This function returns the current PWM clock configuration. +//! +//! \return Returns the current PWM clock configuration; is one of +//! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4, +//! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or +//! \b SYSCTL_PWMDIV_64. +//! +//! \note This function should only be used with TM4C123 devices. For +//! other TM4C devices, the PWMClockGet() function should be used. +// +//***************************************************************************** +uint32_t +SysCtlPWMClockGet(void) +{ + // + // Check that there is a PWM block on this part. + // + ASSERT(HWREG(SYSCTL_DC1) & (SYSCTL_DC1_PWM0 | SYSCTL_DC1_PWM1)); + + // + // Return the current PWM clock configuration. Make sure that + // SYSCTL_PWMDIV_1 is returned in all cases where the divider is disabled. + // + if(!(HWREG(SYSCTL_RCC) & SYSCTL_RCC_USEPWMDIV)) + { + // + // The divider is not active so reflect this in the value we return. + // + return(SYSCTL_PWMDIV_1); + } + else + { + // + // The divider is active so directly return the masked register value. + // + return(HWREG(SYSCTL_RCC) & + (SYSCTL_RCC_USEPWMDIV | SYSCTL_RCC_PWMDIV_M)); + } +} + +//***************************************************************************** +// +//! Enables access to a GPIO peripheral via the AHB. +//! +//! \param ui32GPIOPeripheral is the GPIO peripheral to enable. +//! +//! This function is used to enable the specified GPIO peripheral to be +//! accessed from the Advanced Host Bus (AHB) instead of the legacy Advanced +//! Peripheral Bus (APB). When a GPIO peripheral is enabled for AHB access, +//! the \b _AHB_BASE form of the base address should be used for GPIO +//! functions. For example, instead of using \b GPIO_PORTA_BASE as the base +//! address for GPIO functions, use \b GPIO_PORTA_AHB_BASE instead. +//! +//! The \e ui32GPIOPeripheral argument must be only one of the following +//! values: +//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, +//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, +//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, or \b SYSCTL_PERIPH_GPIOJ. +//! +//! \note On some devices, all GPIO ports are only available on AHB. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlGPIOAHBEnable(uint32_t ui32GPIOPeripheral) +{ + // + // Check the arguments. + // + ASSERT((ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOA) || + (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOB) || + (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOC) || + (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOD) || + (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOE) || + (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOF) || + (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOG) || + (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOH) || + (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOJ)); + + // + // Enable this GPIO for AHB access. + // + HWREG(SYSCTL_GPIOHBCTL) |= (1 << (ui32GPIOPeripheral & 0xF)); +} + +//***************************************************************************** +// +//! Disables access to a GPIO peripheral via the AHB. +//! +//! \param ui32GPIOPeripheral is the GPIO peripheral to disable. +//! +//! This function disables the specified GPIO peripheral for access from the +//! Advanced Host Bus (AHB). Once disabled, the GPIO peripheral is accessed +//! from the legacy Advanced Peripheral Bus (APB). +//! +//! The \b ui32GPIOPeripheral argument must be only one of the following +//! values: +//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, +//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, +//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, or \b SYSCTL_PERIPH_GPIOJ. +//! +//! \note Some devices allow disabling AHB access to GPIO ports that are only +//! present on the AHB. Disabling AHB access to these ports will disable +//! access to these GPIO ports. On some devices, all GPIO ports are only +//! available on AHB. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlGPIOAHBDisable(uint32_t ui32GPIOPeripheral) +{ + // + // Check the arguments. + // + ASSERT((ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOA) || + (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOB) || + (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOC) || + (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOD) || + (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOE) || + (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOF) || + (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOG) || + (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOH) || + (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOJ)); + + // + // Disable this GPIO for AHB access. + // + HWREG(SYSCTL_GPIOHBCTL) &= ~(1 << (ui32GPIOPeripheral & 0xF)); +} + +//***************************************************************************** +// +//! Powers up the USB PLL. +//! +//! This function enables the USB controller's PLL, which is used by its +//! physical layer. This call is necessary before connecting to any external +//! devices. +//! +//! \note This function should only be called on TM4C123 devices. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlUSBPLLEnable(void) +{ + // + // Turn on the USB PLL. + // + HWREG(SYSCTL_RCC2) &= ~SYSCTL_RCC2_USBPWRDN; +} + +//***************************************************************************** +// +//! Powers down the USB PLL. +//! +//! This function disables the USB controller's PLL, which is used by its +//! physical layer. The USB registers are still accessible, but the physical +//! layer no longer functions. +//! +//! \note This function should only be called on TM4C123 devices. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlUSBPLLDisable(void) +{ + // + // Turn off the USB PLL. + // + HWREG(SYSCTL_RCC2) |= SYSCTL_RCC2_USBPWRDN; +} + +//***************************************************************************** +// +//! Configures the response to system voltage events. +//! +//! \param ui32Config holds the configuration options for the voltage events. +//! +//! This function configures the response to voltage-related events. +//! These events are triggered when the voltage rails drop below certain +//! levels. The \e ui32Config parameter provides the configuration for the +//! voltage events and is a combination of the \b SYSCTL_VEVENT_* values. +//! +//! The response to a brown out on the VDDA rail is set by using one of the +//! following values: +//! - \b SYSCTL_VEVENT_VDDABO_NONE - There is no action taken on a VDDA +//! brown out. +//! - \b SYSCTL_VEVENT_VDDABO_INT - A system interrupt is generated when a +//! VDDA brown out occurs. +//! - \b SYSCTL_VEVENT_VDDABO_NMI - An NMI is generated when a VDDA brown out +//! occurs. +//! - \b SYSCTL_VEVENT_VDDABO_RST - A reset is generated when a VDDA brown out +//! occurs. The type of reset that is generated is controller by the +//! \b SYSCTL_ONRST_BOR_* setting passed into the SysCtlResetBehaviorSet() +//! function. +//! +//! The response to a brown out on the VDD rail is set by using one of the +//! following values: +//! - \b SYSCTL_VEVENT_VDDBO_NONE - There is no action taken on a VDD +//! brown out. +//! - \b SYSCTL_VEVENT_VDDBO_INT - A system interrupt is generated when a +//! VDD brown out occurs. +//! - \b SYSCTL_VEVENT_VDDBO_NMI - An NMI is generated when a VDD brown out +//! occurs. +//! - \b SYSCTL_VEVENT_VDDBO_RST - A reset is generated when a VDD brown out +//! occurs. The type of reset that is generated is controller by the +//! \b SYSCTL_ONRST_BOR_* setting passed into the SysCtlResetBehaviorSet() +//! function. +//! +//! \b Example: Configure the voltage events to trigger an interrupt on a VDDA +//! brown out, an NMI on a VDDC brown out and a reset on a VDD brown out. +//! +//! \verbatim +//! +//! // +//! // Configure the BOR rest to trigger a full POR. This is needed because +//! // the SysCtlVoltageEventConfig() call is triggering a reset so the type +//! // of reset is specified by this call. +//! // +//! SysCtlResetBehaviorSet(SYSCTL_ONRST_BOR_POR); +//! +//! // +//! // Trigger an interrupt on a VDDA brown out and a reset on a VDD brown out. +//! // +//! SysCtlVoltageEventConfig(SYSCTL_VEVENT_VDDABO_INT | +//! SYSCTL_VEVENT_VDDBO_RST); +//! \endverbatim +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlVoltageEventConfig(uint32_t ui32Config) +{ + // + // Set the requested events. + // + HWREG(SYSCTL_PTBOCTL) = ui32Config; +} + +//***************************************************************************** +// +//! Returns the voltage event status. +//! +//! This function returns the voltage event status for the system controller. +//! The value returned is a logical OR of the following values: +//! - \b SYSCTL_VESTAT_VDDBOR a brown-out event occurred on the VDD rail. +//! - \b SYSCTL_VESTAT_VDDABOR a brown-out event occurred on the VDDA rail. +//! +//! The values returned from this function can be passed to the +//! SysCtlVoltageEventClear() to clear the current voltage event status. +//! Because voltage events are not cleared due to a reset, the voltage event +//! status must be cleared by calling SysCtlVoltageEventClear(). +//! +//! \b Example: Clear the current voltage event status. +//! +//! \verbatim +//! uint32_t ui32VoltageEvents; +//! +//! // +//! // Read the current voltage event status. +//! // +//! ui32VoltageEvents = SysCtlVoltageEventStatus(); +//! +//! // +//! // Clear all the current voltage events. +//! // +//! SysCtlVoltageEventClear(ui32VoltageEvents); +//! \endverbatim +//! +//! \return The current voltage event status. +//! +//! \note The availability of voltage events varies with the Tiva part +//! in use. Please consult the data sheet for the part you are using to +//! determine which interrupt sources are available. +// +//***************************************************************************** +uint32_t +SysCtlVoltageEventStatus(void) +{ + // + // Return the current voltage event status. + // + return(HWREG(SYSCTL_PWRTC)); +} + +//***************************************************************************** +// +//! Clears the voltage event status. +//! +//! \param ui32Status is a bit mask of the voltage events to clear. +//! +//! This function clears the current voltage events status for the values +//! specified in the \e ui32Status parameter. The \e ui32Status value must be +//! a logical OR of the following values: +//! - \b SYSCTL_VESTAT_VDDBOR a brown-out event occurred on the VDD rail. +//! - \b SYSCTL_VESTAT_VDDABOR a brown-out event occurred on the VDDA rail. +//! +//! \b Example: Clear the current voltage event status. +//! +//! \verbatim +//! // +//! // Clear all the current voltage events. +//! // +//! SysCtlVoltageEventClear(SysCtlVoltageEventStatus()); +//! \endverbatim +//! +//! \note The availability of voltage event status varies with the +//! Tiva part in use. Please consult the data sheet for the part you are +//! using to determine which interrupt sources are available. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlVoltageEventClear(uint32_t ui32Status) +{ + // + // Clear the requested voltage events. + // + HWREG(SYSCTL_PWRTC) |= ui32Status; +} + +//***************************************************************************** +// +//! Gets the effective VCO frequency. +//! +//! \param ui32Crystal holds the crystal value used for the PLL. +//! \param pui32VCOFrequency is a pointer to the storage location which holds +//! value of the VCO computed. +//! +//! This function calculates the VCO of the PLL before the system divider is +//! applied +//! +//! \return \b true if the PLL is configured correctly and a VCO is valid or +//! \b false if the device is not TM4C129x or the PLL is not used +// +//***************************************************************************** +bool +SysCtlVCOGet(uint32_t ui32Crystal, uint32_t *pui32VCOFrequency) +{ + int32_t i32XtalIdx; + uint32_t ui32RSClkConfig, ui32PLLFreq0, ui32PLLFreq1, ui32Osc; + uint32_t ui32MInt, ui32MFrac, ui32NDiv, ui32QDiv, ui32TempVCO; + + // + // Check if TM4C123 device is being used. should not use this function. + // + if(CLASS_IS_TM4C123) + { + // + // Return error if TM4C123. + // + *pui32VCOFrequency = 0; + return(false); + } + + // + // Read the RSCLKCFG register to determine if PLL is being used. + // + ui32RSClkConfig = HWREG(SYSCTL_RSCLKCFG); + + // + // Check if PLL is used. + // + if((ui32RSClkConfig & SYSCTL_RSCLKCFG_USEPLL) != SYSCTL_RSCLKCFG_USEPLL) + { + // + // Return error if PLL is not used. + // + *pui32VCOFrequency = 0; + return(false); + } + + // + // Get the index of the crystal from the ui32Config parameter. + // + i32XtalIdx = SysCtlXtalCfgToIndex(ui32Crystal); + + // + // Get the value of the crystal frequency based on the index + // + ui32Osc = g_pui32Xtals[i32XtalIdx]; + + // + // Read the PLLFREQ0 and PLLFREQ1 registers to get information on the + // MINT, MFRAC, N and Q values of the PLL + // + ui32PLLFreq0 = HWREG(SYSCTL_PLLFREQ0); + ui32PLLFreq1 = HWREG(SYSCTL_PLLFREQ1); + + ui32MInt = (ui32PLLFreq0 & SYSCTL_PLLFREQ0_MINT_M) >> + SYSCTL_PLLFREQ0_MINT_S; + ui32MFrac = (ui32PLLFreq0 & SYSCTL_PLLFREQ0_MFRAC_M) >> + SYSCTL_PLLFREQ0_MFRAC_S; + ui32NDiv = (ui32PLLFreq1 & SYSCTL_PLLFREQ1_N_M) >> + SYSCTL_PLLFREQ1_N_S; + ui32QDiv = (ui32PLLFreq1 & SYSCTL_PLLFREQ1_Q_M) >> + SYSCTL_PLLFREQ1_Q_S; + + // + // Calculate the VCO at the output of the PLL + // + ui32TempVCO = (ui32Osc * ui32MInt) + ((ui32Osc * ui32MFrac) / 1024); + ui32TempVCO /= ((ui32NDiv + 1) * (ui32QDiv + 1)); + + *pui32VCOFrequency = ui32TempVCO; + return(true); +} + +//***************************************************************************** +// +//! Returns the current NMI status. +//! +//! This function returns the NMI status for the system controller. The valid +//! values for the \e ui32Ints parameter are a logical OR of the following +//! values: +//! - \b SYSCTL_NMI_MOSCFAIL the main oscillator is not present or did not +//! start. +//! - \b SYSCTL_NMI_TAMPER a tamper event has been detected. +//! - \b SYSCTL_NMI_WDT0 watchdog 0 generated a timeout. +//! - \b SYSCTL_NMI_WDT1 watchdog 1 generated a timeout. +//! - \b SYSCTL_NMI_POWER a power event occurred. +//! - \b SYSCTL_NMI_EXTERNAL an external NMI pin asserted. +//! +//! \b Example: Clear all current NMI status flags. +//! +//! \verbatim +//! +//! // +//! // Clear all the current NMI sources. +//! // +//! SysCtlNMIClear(SysCtlNMIStatus()); +//! \endverbatim +//! +//! \note The availability of the NMI status varies with the Tiva part in +//! use. Please consult the data sheet for the part you are using to determine +//! which interrupt sources are available. +//! +//! \return The current NMI status. +// +//***************************************************************************** +uint32_t +SysCtlNMIStatus(void) +{ + return(HWREG(SYSCTL_NMIC)); +} + +//***************************************************************************** +// +//! Clears NMI sources. +//! +//! \param ui32Ints is a bit mask of the non-maskable interrupt sources. +//! +//! This function clears the current NMI status specified in the \e ui32Ints +//! parameter. The valid values for the \e ui32Ints parameter are a logical OR +//! of the following values: +//! - \b SYSCTL_NMI_MOSCFAIL the main oscillator is not present or did not +//! start. +//! - \b SYSCTL_NMI_TAMPER a tamper event has been detected. +//! - \b SYSCTL_NMI_WDT0 watchdog 0 generated a timeout. +//! - \b SYSCTL_NMI_WDT1 watchdog 1 generated a timeout. +//! - \b SYSCTL_NMI_POWER a power event occurred. +//! - \b SYSCTL_NMI_EXTERNAL an external NMI pin asserted. +//! +//! \b Example: Clear all current NMI status flags. +//! +//! \verbatim +//! +//! // +//! // Clear all the current NMI sources. +//! // +//! SysCtlNMIClear(SysCtlNMIStatus()); +//! \endverbatim +//! +//! \note The availability of the NMI status varies with the Tiva part in +//! use. Please consult the data sheet for the part you are using to determine +//! which interrupt sources are available. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlNMIClear(uint32_t ui32Ints) +{ + // + // Clear the requested interrupt sources. + // + HWREG(SYSCTL_NMIC) &= ~ui32Ints; +} + +//***************************************************************************** +// +//! Configures and enables or disables the clock output on the DIVSCLK pin. +//! +//! \param ui32Config holds the configuration options including enabling or +//! disabling the clock output on the DIVSCLK pin. +//! \param ui32Div is the divisor for the clock selected in the \e ui32Config +//! parameter. +//! +//! This function selects the source for the DIVSCLK, enables or disables +//! the clock output and provides an output divider value. The \e ui32Div +//! parameter specifies the divider for the selected clock source and has a +//! valid range of 1-256. The \e ui32Config parameter configures +//! the DIVSCLK output based on the following settings: +//! +//! The first setting allows the output to be enabled or disabled. +//! - \b SYSCTL_CLKOUT_EN - enable the DIVSCLK output. +//! - \b SYSCTL_CLKOUT_DIS - disable the DIVSCLK output (default). +//! +//! The next group of settings selects the source for the DIVSCLK. +//! - \b SYSCTL_CLKOUT_SYSCLK - use the current system clock as the +//! source (default). +//! - \b SYSCTL_CLKOUT_PIOSC - use the PIOSC as the source. +//! - \b SYSCTL_CLKOUT_MOSC - use the MOSC as the source. +//! +//! \b Example: Enable the PIOSC divided by 4 as the DIVSCLK output. +//! +//! \verbatim +//! +//! // +//! // Enable the PIOSC divided by 4 as the DIVSCLK output. +//! // +//! SysCtlClockOutConfig(SYSCTL_DIVSCLK_EN | SYSCTL_DIVSCLK_SRC_PIOSC, 4); +//! \endverbatim +//! +//! \note The availability of the DIVSCLK output varies with the Tiva part +//! in use. Please consult the data sheet for the part you are using to +//! determine which interrupt sources are available. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlClockOutConfig(uint32_t ui32Config, uint32_t ui32Div) +{ + ASSERT(ui32Div != 0); + ASSERT((ui32Config & ~(SYSCTL_CLKOUT_EN | SYSCTL_CLKOUT_DIS | + SYSCTL_CLKOUT_SYSCLK | SYSCTL_CLKOUT_PIOSC | + SYSCTL_CLKOUT_MOSC)) == 0); + + // + // Set the requested configuration and divisor. + // + HWREG(SYSCTL_DIVSCLK) = ui32Config | ((ui32Div - 1) & + SYSCTL_DIVSCLK_DIV_M); +} + +//***************************************************************************** +// +//! Configures the alternate peripheral clock source. +//! +//! \param ui32Config holds the configuration options for the alternate +//! peripheral clock. +//! +//! This function configures the alternate peripheral clock. The alternate +//! peripheral clock is used to provide a known clock in all operating modes +//! to peripherals that support using the alternate peripheral clock as an +//! input clock. The \e ui32Config parameter value provides the clock input +//! source using one of the following values: +//! - \b SYSCTL_ALTCLK_PIOSC - use the PIOSC as the alternate clock +//! source (default). +//! - \b SYSCTL_ALTCLK_RTCOSC - use the Hibernate module RTC clock as the +//! alternate clock source. +//! - \b SYSCTL_ALTCLK_LFIOSC - use the low-frequency internal oscillator as +//! the alternate clock source. +//! +//! \b Example: Select the Hibernate module RTC clock as the alternate clock +//! source. +//! +//! \verbatim +//! +//! // +//! // Select the Hibernate module RTC clock as the alternate clock source. +//! // +//! SysCtlAltClkConfig(SYSCTL_ALTCLK_RTCOSC); +//! \endverbatim +//! +//! \note The availability of the alternate peripheral clock varies with the +//! Tiva part in use. Please consult the data sheet for the part you are +//! using to determine which interrupt sources are available. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlAltClkConfig(uint32_t ui32Config) +{ + // + // Set the requested configuration and divisor. + // + HWREG(SYSCTL_ALTCLKCFG) = ui32Config; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/sysexc.c b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/sysexc.c new file mode 100644 index 0000000000000000000000000000000000000000..d269b74bcd3008fc7526e3a03559741516b54c9a --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/sysexc.c @@ -0,0 +1,311 @@ +//***************************************************************************** +// +// sysexc.c - Routines for the System Exception Module. +// +// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup sysexc_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_ints.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_sysexc.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" + +//***************************************************************************** +// +//! Returns the interrupt number for a system exception. +//! +//! This function returns the interrupt number for a system exception. +//! +//! \return Returns the system exception interrupt number. +// +//***************************************************************************** +static uint32_t +_SysExcIntNumberGet(void) +{ + uint32_t ui32Int; + + // + // Get the interrupt number based on the class. + // + if(CLASS_IS_TM4C123) + { + ui32Int = INT_SYSEXC_TM4C123; + } + else if(CLASS_IS_TM4C129) + { + ui32Int = INT_SYSEXC_TM4C129; + } + else + { + ui32Int = 0; + } + return(ui32Int); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the system exception interrupt. +//! +//! \param pfnHandler is a pointer to the function to be called when the system +//! exception interrupt occurs. +//! +//! This function places the address of the system exception interrupt handler +//! into the interrupt vector table in SRAM. This function also enables the +//! global interrupt in the interrupt controller; specific system exception +//! interrupts must be enabled via SysExcIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +SysExcIntRegister(void (*pfnHandler)(void)) +{ + uint32_t ui32Int; + + // + // Get the system exception interrupt number. + // + ui32Int = _SysExcIntNumberGet(); + + ASSERT(ui32Int != 0); + + // + // Register the interrupt handler. + // + IntRegister(ui32Int, pfnHandler); + + // + // Enable the system exception interrupt. + // + IntEnable(ui32Int); +} + +//***************************************************************************** +// +//! Unregisters the system exception interrupt handler. +//! +//! This function removes the system exception interrupt handler from the +//! vector table in SRAM. This function also masks off the system exception +//! interrupt in the interrupt controller so that the interrupt handler is no +//! longer called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +SysExcIntUnregister(void) +{ + uint32_t ui32Int; + + // + // Get the system exception interrupt number. + // + ui32Int = _SysExcIntNumberGet(); + + ASSERT(ui32Int != 0); + + // + // Disable the system exception interrupt. + // + IntDisable(ui32Int); + + // + // Unregister the system exception interrupt handler. + // + IntUnregister(ui32Int); +} + +//***************************************************************************** +// +//! Enables individual system exception interrupt sources. +//! +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated system exception interrupt sources. +//! Only the sources that are enabled can be reflected to the processor +//! interrupt; disabled sources have no effect on the processor. +//! +//! The \e ui32IntFlags parameter is the logical OR of any of the following: +//! +//! - \b SYSEXC_INT_FP_IXC - Floating-point inexact exception interrupt +//! - \b SYSEXC_INT_FP_OFC - Floating-point overflow exception interrupt +//! - \b SYSEXC_INT_FP_UFC - Floating-point underflow exception interrupt +//! - \b SYSEXC_INT_FP_IOC - Floating-point invalid operation interrupt +//! - \b SYSEXC_INT_FP_DZC - Floating-point divide by zero exception interrupt +//! - \b SYSEXC_INT_FP_IDC - Floating-point input denormal exception interrupt +//! +//! \return None. +// +//***************************************************************************** +void +SysExcIntEnable(uint32_t ui32IntFlags) +{ + // + // Enable the specified interrupts. + // + HWREG(SYSEXC_IM) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! Disables individual system exception interrupt sources. +//! +//! \param ui32IntFlags is the bit mask of the interrupt sources to be +//! disabled. +//! +//! This function disables the indicated system exception interrupt sources. +//! Only sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ui32IntFlags parameter is the logical OR of any of the following: +//! +//! - \b SYSEXC_INT_FP_IXC - Floating-point inexact exception interrupt +//! - \b SYSEXC_INT_FP_OFC - Floating-point overflow exception interrupt +//! - \b SYSEXC_INT_FP_UFC - Floating-point underflow exception interrupt +//! - \b SYSEXC_INT_FP_IOC - Floating-point invalid operation interrupt +//! - \b SYSEXC_INT_FP_DZC - Floating-point divide by zero exception interrupt +//! - \b SYSEXC_INT_FP_IDC - Floating-point input denormal exception interrupt +//! +//! \return None. +// +//***************************************************************************** +void +SysExcIntDisable(uint32_t ui32IntFlags) +{ + // + // Disable the specified interrupts. + // + HWREG(SYSEXC_IM) &= ~(ui32IntFlags); +} + +//***************************************************************************** +// +//! Gets the current system exception interrupt status. +//! +//! \param bMasked is \b false if the raw interrupt status is required and +//! \b true if the masked interrupt status is required. +//! +//! This function returns the system exception interrupt status. Either the +//! raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \return Returns the current system exception interrupt status, enumerated +//! as the logical OR of \b SYSEXC_INT_FP_IXC, \b SYSEXC_INT_FP_OFC, +//! \b SYSEXC_INT_FP_UFC, \b SYSEXC_INT_FP_IOC, \b SYSEXC_INT_FP_DZC, and +//! \b SYSEXC_INT_FP_IDC. +// +//***************************************************************************** +uint32_t +SysExcIntStatus(bool bMasked) +{ + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(SYSEXC_MIS)); + } + else + { + return(HWREG(SYSEXC_RIS)); + } +} + +//***************************************************************************** +// +//! Clears system exception interrupt sources. +//! +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! This function clears the specified system exception interrupt sources, so +//! that they no longer assert. This function must be called in the interrupt +//! handler to keep the interrupt from being recognized again immediately upon +//! exit. +//! +//! The \e ui32IntFlags parameter is the logical OR of any of the following: +//! +//! - \b SYSEXC_INT_FP_IXC - Floating-point inexact exception interrupt +//! - \b SYSEXC_INT_FP_OFC - Floating-point overflow exception interrupt +//! - \b SYSEXC_INT_FP_UFC - Floating-point underflow exception interrupt +//! - \b SYSEXC_INT_FP_IOC - Floating-point invalid operation interrupt +//! - \b SYSEXC_INT_FP_DZC - Floating-point divide by zero exception interrupt +//! - \b SYSEXC_INT_FP_IDC - Floating-point input denormal exception interrupt +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +SysExcIntClear(uint32_t ui32IntFlags) +{ + // + // Clear the requested interrupt sources. + // + HWREG(SYSEXC_IC) = ui32IntFlags; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/systick.c b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/systick.c new file mode 100644 index 0000000000000000000000000000000000000000..49fbb9c51fd22c225a1b7e05e6d469ead9a69784 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/systick.c @@ -0,0 +1,277 @@ +//***************************************************************************** +// +// systick.c - Driver for the SysTick timer in NVIC. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup systick_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include "hw_ints.h" +#include "hw_nvic.h" +#include "hw_types.h" +#include "debug.h" +#include "interrupt.h" +#include "systick.h" + +//***************************************************************************** +// +//! Enables the SysTick counter. +//! +//! This function starts the SysTick counter. If an interrupt handler has been +//! registered, it is called when the SysTick counter rolls over. +//! +//! \note Calling this function causes the SysTick counter to (re)commence +//! counting from its current value. The counter is not automatically reloaded +//! with the period as specified in a previous call to SysTickPeriodSet(). If +//! an immediate reload is required, the \b NVIC_ST_CURRENT register must be +//! written to force the reload. Any write to this register clears the SysTick +//! counter to 0 and causes a reload with the supplied period on the next +//! clock. +//! +//! \return None. +// +//***************************************************************************** +void +SysTickEnable(void) +{ + // + // Enable SysTick. + // + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE; +} + +//***************************************************************************** +// +//! Disables the SysTick counter. +//! +//! This function stops the SysTick counter. If an interrupt handler has been +//! registered, it is not called until SysTick is restarted. +//! +//! \return None. +// +//***************************************************************************** +void +SysTickDisable(void) +{ + // + // Disable SysTick. + // + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the SysTick interrupt. +//! +//! \param pfnHandler is a pointer to the function to be called when the +//! SysTick interrupt occurs. +//! +//! This function registers the handler to be called when a SysTick interrupt +//! occurs. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +SysTickIntRegister(void (*pfnHandler)(void)) +{ + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(FAULT_SYSTICK, pfnHandler); + + // + // Enable the SysTick interrupt. + // + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; +} + +//***************************************************************************** +// +//! Unregisters the interrupt handler for the SysTick interrupt. +//! +//! This function unregisters the handler to be called when a SysTick interrupt +//! occurs. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +SysTickIntUnregister(void) +{ + // + // Disable the SysTick interrupt. + // + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); + + // + // Unregister the interrupt handler. + // + IntUnregister(FAULT_SYSTICK); +} + +//***************************************************************************** +// +//! Enables the SysTick interrupt. +//! +//! This function enables the SysTick interrupt, allowing it to be +//! reflected to the processor. +//! +//! \note The SysTick interrupt handler is not required to clear the SysTick +//! interrupt source because it is cleared automatically by the NVIC when the +//! interrupt handler is called. +//! +//! \return None. +// +//***************************************************************************** +void +SysTickIntEnable(void) +{ + // + // Enable the SysTick interrupt. + // + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; +} + +//***************************************************************************** +// +//! Disables the SysTick interrupt. +//! +//! This function disables the SysTick interrupt, preventing it from being +//! reflected to the processor. +//! +//! \return None. +// +//***************************************************************************** +void +SysTickIntDisable(void) +{ + // + // Disable the SysTick interrupt. + // + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); +} + +//***************************************************************************** +// +//! Sets the period of the SysTick counter. +//! +//! \param ui32Period is the number of clock ticks in each period of the +//! SysTick counter and must be between 1 and 16,777,216, inclusive. +//! +//! This function sets the rate at which the SysTick counter wraps, which +//! equates to the number of processor clocks between interrupts. +//! +//! \note Calling this function does not cause the SysTick counter to reload +//! immediately. If an immediate reload is required, the \b NVIC_ST_CURRENT +//! register must be written. Any write to this register clears the SysTick +//! counter to 0 and causes a reload with the \e ui32Period supplied here on +//! the next clock after SysTick is enabled. +//! +//! \return None. +// +//***************************************************************************** +void +SysTickPeriodSet(uint32_t ui32Period) +{ + // + // Check the arguments. + // + ASSERT((ui32Period > 0) && (ui32Period <= 16777216)); + + // + // Set the period of the SysTick counter. + // + HWREG(NVIC_ST_RELOAD) = ui32Period - 1; +} + +//***************************************************************************** +// +//! Gets the period of the SysTick counter. +//! +//! This function returns the rate at which the SysTick counter wraps, which +//! equates to the number of processor clocks between interrupts. +//! +//! \return Returns the period of the SysTick counter. +// +//***************************************************************************** +uint32_t +SysTickPeriodGet(void) +{ + // + // Return the period of the SysTick counter. + // + return(HWREG(NVIC_ST_RELOAD) + 1); +} + +//***************************************************************************** +// +//! Gets the current value of the SysTick counter. +//! +//! This function returns the current value of the SysTick counter, which is +//! a value between the period - 1 and zero, inclusive. +//! +//! \return Returns the current value of the SysTick counter. +// +//***************************************************************************** +uint32_t +SysTickValueGet(void) +{ + // + // Return the current value of the SysTick counter. + // + return(HWREG(NVIC_ST_CURRENT)); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/tiva_timer.c b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/tiva_timer.c new file mode 100644 index 0000000000000000000000000000000000000000..d348849570752c7dd9445cafc19a45e5cc4729eb --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/tiva_timer.c @@ -0,0 +1,1898 @@ +//***************************************************************************** +// +// timer.c - Driver for the timer module. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup timer_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_timer.h" +#include "inc/hw_types.h" +#include "inc/hw_sysctl.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/tiva_timer.h" + +//***************************************************************************** +// +// A macro used to determine whether the target part supports new +// configuration and control options. +// +//***************************************************************************** +#define NEW_TIMER_CONFIGURATION CLASS_IS_TM4C129 + +//***************************************************************************** +// +// A mapping of timer base address to interrupt number. +// +//***************************************************************************** +static const uint32_t g_ppui32TimerIntMap[][2] = +{ + { TIMER0_BASE, INT_TIMER0A_TM4C123 }, + { TIMER1_BASE, INT_TIMER1A_TM4C123 }, + { TIMER2_BASE, INT_TIMER2A_TM4C123 }, + { TIMER3_BASE, INT_TIMER3A_TM4C123 }, + { TIMER4_BASE, INT_TIMER4A_TM4C123 }, + { TIMER5_BASE, INT_TIMER5A_TM4C123 }, + { WTIMER0_BASE, INT_WTIMER0A_TM4C123 }, + { WTIMER1_BASE, INT_WTIMER1A_TM4C123 }, + { WTIMER2_BASE, INT_WTIMER2A_TM4C123 }, + { WTIMER3_BASE, INT_WTIMER3A_TM4C123 }, + { WTIMER4_BASE, INT_WTIMER4A_TM4C123 }, + { WTIMER5_BASE, INT_WTIMER5A_TM4C123 }, +}; +static const uint_fast8_t g_ui8TimerIntMapRows = + sizeof(g_ppui32TimerIntMap) / sizeof(g_ppui32TimerIntMap[0]); + +static const uint32_t g_ppui32TimerIntMapSnowflake[][2] = +{ + { TIMER0_BASE, INT_TIMER0A_TM4C129 }, + { TIMER1_BASE, INT_TIMER1A_TM4C129 }, + { TIMER2_BASE, INT_TIMER2A_TM4C129 }, + { TIMER3_BASE, INT_TIMER3A_TM4C129 }, + { TIMER4_BASE, INT_TIMER4A_TM4C129 }, + { TIMER5_BASE, INT_TIMER5A_TM4C129 }, + { TIMER6_BASE, INT_TIMER6A_TM4C129 }, + { TIMER7_BASE, INT_TIMER7A_TM4C129 }, +}; +static const uint_fast8_t g_ui8TimerIntMapRowsSnowflake = + sizeof(g_ppui32TimerIntMapSnowflake) / + sizeof(g_ppui32TimerIntMapSnowflake[0]); + +//***************************************************************************** +// +//! \internal +//! Checks a timer base address. +//! +//! \param ui32Base is the base address of the timer module. +//! +//! This function determines if a timer module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static bool +_TimerBaseValid(uint32_t ui32Base) +{ + return((ui32Base == TIMER0_BASE) || (ui32Base == TIMER1_BASE) || + (ui32Base == TIMER2_BASE) || (ui32Base == TIMER3_BASE) || + (ui32Base == TIMER4_BASE) || (ui32Base == TIMER5_BASE) || + (ui32Base == TIMER6_BASE) || (ui32Base == TIMER7_BASE) || + (ui32Base == WTIMER0_BASE) || (ui32Base == WTIMER1_BASE) || + (ui32Base == WTIMER2_BASE) || (ui32Base == WTIMER3_BASE) || + (ui32Base == WTIMER4_BASE) || (ui32Base == WTIMER5_BASE)); +} +#endif + +//***************************************************************************** +// +//! Returns a timer modules interrupt number. +//! +//! \param ui32Base is the base address of the selected timer. +//! \param ui32Timer specifies the timer(s) to enable; must be one of +//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. +//! +//! This function returns the interrupt number for a given timer module +//! specified by the \e ui32Base and \e ui32Timer parameter. +//! +//! \return Returns a timer module's interrupt number or 0 if the interrupt +//! does not exist. +// +//***************************************************************************** +static uint32_t +_TimerIntNumberGet(uint32_t ui32Base, uint32_t ui32Timer) +{ + uint32_t ui32Int; + uint_fast8_t ui8Idx, ui8Rows; + const uint32_t (*ppui32SSIIntMap)[2]; + + // + // Default interrupt map. + // + ppui32SSIIntMap = g_ppui32TimerIntMap; + ui8Rows = g_ui8TimerIntMapRows; + + if(CLASS_IS_TM4C129) + { + ppui32SSIIntMap = g_ppui32TimerIntMapSnowflake; + ui8Rows = g_ui8TimerIntMapRowsSnowflake; + } + + // + // Loop through the table that maps timer base addresses to interrupt + // numbers. + // + for(ui8Idx = 0; ui8Idx < ui8Rows; ui8Idx++) + { + // + // See if this base address matches. + // + if(ppui32SSIIntMap[ui8Idx][0] == ui32Base) + { + ui32Int = ppui32SSIIntMap[ui8Idx][1]; + + if(ui32Timer == TIMER_B) + { + ui32Int += 1; + } + + // + // Return the corresponding interrupt number. + // + return(ui32Int); + } + } + + // + // The base address could not be found, so return an error. + // + return(0); +} + +//***************************************************************************** +// +//! Enables the timer(s). +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to enable; must be one of +//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. +//! +//! This function enables operation of the timer module. The timer must be +//! configured before it is enabled. +//! +//! \return None. +// +//***************************************************************************** +void +TimerEnable(uint32_t ui32Base, uint32_t ui32Timer) +{ + // + // Check the arguments. + // + ASSERT(_TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // + // Enable the timer(s) module. + // + HWREG(ui32Base + TIMER_O_CTL) |= ui32Timer & (TIMER_CTL_TAEN | + TIMER_CTL_TBEN); +} + +//***************************************************************************** +// +//! Disables the timer(s). +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to disable; must be one of +//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. +//! +//! This function disables operation of the timer module. +//! +//! \return None. +// +//***************************************************************************** +void +TimerDisable(uint32_t ui32Base, uint32_t ui32Timer) +{ + // + // Check the arguments. + // + ASSERT(_TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // + // Disable the timer module. + // + HWREG(ui32Base + TIMER_O_CTL) &= ~(ui32Timer & + (TIMER_CTL_TAEN | TIMER_CTL_TBEN)); +} + +//***************************************************************************** +// +//! Configures the timer(s). +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Config is the configuration for the timer. +//! +//! This function configures the operating mode of the timer(s). The timer +//! module is disabled before being configured and is left in the disabled +//! state. The timer can be configured to be a single full-width timer +//! by using the \b TIMER_CFG_* values or a pair of half-width timers using the +//! \b TIMER_CFG_A_* and \b TIMER_CFG_B_* values passed in the \e ui32Config +//! parameter. +//! +//! The configuration is specified in \e ui32Config as one of the following +//! values: +//! +//! - \b TIMER_CFG_ONE_SHOT - Full-width one-shot timer +//! - \b TIMER_CFG_ONE_SHOT_UP - Full-width one-shot timer that counts up +//! instead of down (not available on all parts) +//! - \b TIMER_CFG_PERIODIC - Full-width periodic timer +//! - \b TIMER_CFG_PERIODIC_UP - Full-width periodic timer that counts up +//! instead of down (not available on all parts) +//! - \b TIMER_CFG_RTC - Full-width real time clock timer +//! - \b TIMER_CFG_SPLIT_PAIR - Two half-width timers +//! +//! When configured for a pair of half-width timers, each timer is separately +//! configured. The first timer is configured by setting \e ui32Config to +//! the result of a logical OR operation between one of the following values +//! and \e ui32Config: +//! +//! - \b TIMER_CFG_A_ONE_SHOT - Half-width one-shot timer +//! - \b TIMER_CFG_A_ONE_SHOT_UP - Half-width one-shot timer that counts up +//! instead of down (not available on all parts) +//! - \b TIMER_CFG_A_PERIODIC - Half-width periodic timer +//! - \b TIMER_CFG_A_PERIODIC_UP - Half-width periodic timer that counts up +//! instead of down (not available on all parts) +//! - \b TIMER_CFG_A_CAP_COUNT - Half-width edge count capture +//! - \b TIMER_CFG_A_CAP_COUNT_UP - Half-width edge count capture that counts +//! up instead of down (not available on all parts) +//! - \b TIMER_CFG_A_CAP_TIME - Half-width edge time capture +//! - \b TIMER_CFG_A_CAP_TIME_UP - Half-width edge time capture that counts up +//! instead of down (not available on all parts) +//! - \b TIMER_CFG_A_PWM - Half-width PWM output +//! +//! Some Tiva devices also allow configuring an action when the timers +//! reach their timeout. Please consult the data sheet for the part you are +//! using to determine whether configuring actions on timers is available. +//! +//! One of the following can be combined with the \b TIMER_CFG_* values to +//! enable an action on timer A: +//! +//! - \b TIMER_CFG_A_ACT_TOINTD - masks the timeout interrupt of timer A. +//! - \b TIMER_CFG_A_ACT_NONE - no additional action on timeout of timer A. +//! - \b TIMER_CFG_A_ACT_TOGGLE - toggle CCP on timeout of timer A. +//! - \b TIMER_CFG_A_ACT_SETTO - set CCP on timeout of timer A. +//! - \b TIMER_CFG_A_ACT_CLRTO - clear CCP on timeout of timer A. +//! - \b TIMER_CFG_A_ACT_SETTOGTO - set CCP immediately and then toggle it on +//! timeout of timer A. +//! - \b TIMER_CFG_A_ACT_CLRTOGTO - clear CCP immediately and then toggle it on +//! timeout of timer A. +//! - \b TIMER_CFG_A_ACT_SETCLRTO - set CCP immediately and then clear it on +//! timeout of timer A. +//! - \b TIMER_CFG_A_ACT_CLRSETTO - clear CCP immediately and then set it on +//! timeout of timer A. +//! +//! One of the following can be combined with the \b TIMER_CFG_* values to +//! enable an action on timer B: +//! +//! - \b TIMER_CFG_B_ACT_TOINTD - masks the timeout interrupt of timer B. +//! - \b TIMER_CFG_B_ACT_NONE - no additional action on timeout of timer B. +//! - \b TIMER_CFG_B_ACT_TOGGLE - toggle CCP on timeout of timer B. +//! - \b TIMER_CFG_B_ACT_SETTO - set CCP on timeout of timer B. +//! - \b TIMER_CFG_B_ACT_CLRTO - clear CCP on timeout of timer B. +//! - \b TIMER_CFG_B_ACT_SETTOGTO - set CCP immediately and then toggle it on +//! timeout of timer B. +//! - \b TIMER_CFG_B_ACT_CLRTOGTO - clear CCP immediately and then toggle it on +//! timeout of timer B. +//! - \b TIMER_CFG_B_ACT_SETCLRTO - set CCP immediately and then clear it on +//! timeout of timer B. +//! - \b TIMER_CFG_B_ACT_CLRSETTO - clear CCP immediately and then set it on +//! timeout of timer B. +//! +//! Similarly, the second timer is configured by setting \e ui32Config to +//! the result of a logical OR operation between one of the corresponding +//! \b TIMER_CFG_B_* values and \e ui32Config. +//! +//! \return None. +// +//***************************************************************************** +void +TimerConfigure(uint32_t ui32Base, uint32_t ui32Config) +{ + // + // Check the arguments. + // + ASSERT(_TimerBaseValid(ui32Base)); + ASSERT((ui32Config == TIMER_CFG_ONE_SHOT) || + (ui32Config == TIMER_CFG_ONE_SHOT_UP) || + (ui32Config == TIMER_CFG_PERIODIC) || + (ui32Config == TIMER_CFG_PERIODIC_UP) || + (ui32Config == TIMER_CFG_RTC) || + ((ui32Config & 0xff000000) == TIMER_CFG_SPLIT_PAIR)); + ASSERT(((ui32Config & 0xff000000) != TIMER_CFG_SPLIT_PAIR) || + ((((ui32Config & 0x000000ff) == TIMER_CFG_A_ONE_SHOT) || + ((ui32Config & 0x000000ff) == TIMER_CFG_A_ONE_SHOT_UP) || + ((ui32Config & 0x000000ff) == TIMER_CFG_A_PERIODIC) || + ((ui32Config & 0x000000ff) == TIMER_CFG_A_PERIODIC_UP) || + ((ui32Config & 0x000000ff) == TIMER_CFG_A_CAP_COUNT) || + ((ui32Config & 0x000000ff) == TIMER_CFG_A_CAP_COUNT_UP) || + ((ui32Config & 0x000000ff) == TIMER_CFG_A_CAP_TIME) || + ((ui32Config & 0x000000ff) == TIMER_CFG_A_CAP_TIME_UP) || + ((ui32Config & 0x000000ff) == TIMER_CFG_A_PWM)) && + (((ui32Config & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT) || + ((ui32Config & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT_UP) || + ((ui32Config & 0x0000ff00) == TIMER_CFG_B_PERIODIC) || + ((ui32Config & 0x0000ff00) == TIMER_CFG_B_PERIODIC_UP) || + ((ui32Config & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT) || + ((ui32Config & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT_UP) || + ((ui32Config & 0x0000ff00) == TIMER_CFG_B_CAP_TIME) || + ((ui32Config & 0x0000ff00) == TIMER_CFG_B_CAP_TIME_UP) || + ((ui32Config & 0x0000ff00) == TIMER_CFG_B_PWM)))); + + // + // Disable the timers. + // + HWREG(ui32Base + TIMER_O_CTL) &= ~(TIMER_CTL_TAEN | TIMER_CTL_TBEN); + + // + // Set the global timer configuration. + // + HWREG(ui32Base + TIMER_O_CFG) = ui32Config >> 24; + + // + // Set the configuration of the A and B timers and set the TxPWMIE bit. + // Note that the B timer configuration is ignored by the hardware in 32-bit + // modes. + // + if(NEW_TIMER_CONFIGURATION) + { + HWREG(ui32Base + TIMER_O_TAMR) = (((ui32Config & 0x000f0000) >> 4) | + (ui32Config & 0xff) | + TIMER_TAMR_TAPWMIE); + HWREG(ui32Base + TIMER_O_TBMR) = (((ui32Config & 0x00f00000) >> 8) | + ((ui32Config >> 8) & 0xff) | + TIMER_TBMR_TBPWMIE); + } + else + { + HWREG(ui32Base + TIMER_O_TAMR) = ((ui32Config & 0xff) | + TIMER_TAMR_TAPWMIE); + HWREG(ui32Base + TIMER_O_TBMR) = (((ui32Config >> 8) & 0xff) | + TIMER_TBMR_TBPWMIE); + } +} + +//***************************************************************************** +// +//! Controls the output level. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to adjust; must be one of +//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. +//! \param bInvert specifies the output level. +//! +//! This function configures the PWM output level for the specified timer. If +//! the \e bInvert parameter is \b true, then the timer's output is made active +//! low; otherwise, it is made active high. +//! +//! \return None. +// +//***************************************************************************** +void +TimerControlLevel(uint32_t ui32Base, uint32_t ui32Timer, bool bInvert) +{ + // + // Check the arguments. + // + ASSERT(_TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // + // Set the output levels as requested. + // + ui32Timer &= TIMER_CTL_TAPWML | TIMER_CTL_TBPWML; + HWREG(ui32Base + TIMER_O_CTL) = (bInvert ? + (HWREG(ui32Base + TIMER_O_CTL) | + ui32Timer) : + (HWREG(ui32Base + TIMER_O_CTL) & + ~(ui32Timer))); +} + +//***************************************************************************** +// +//! Enables or disables the ADC trigger output. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! \param bEnable specifies the desired ADC trigger state. +//! +//! This function controls the ADC trigger output for the specified timer. If +//! the \e bEnable parameter is \b true, then the timer's ADC output trigger is +//! enabled; otherwise it is disabled. +//! +//! \return None. +// +//***************************************************************************** +void +TimerControlTrigger(uint32_t ui32Base, uint32_t ui32Timer, + bool bEnable) +{ + // + // Check the arguments. + // + ASSERT(_TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // + // On newer devices the Timer time out ADC trigger enable must also + // be set. + // + if(NEW_TIMER_CONFIGURATION) + { + uint32_t ui32Val; + + // + // Determine which bits to set or clear in GPTMADCEV. + // + ui32Val = (TIMER_ADCEV_TATOADCEN | TIMER_ADCEV_TBTOADCEN); + ui32Val &= ui32Timer; + + // + // Write the GPTM ADC Event register to enable or disable the trigger + // to the ADC. + // + HWREG(ui32Base + TIMER_O_ADCEV) = (bEnable ? + (HWREG(ui32Base + TIMER_O_ADCEV) | + ui32Val) : + (HWREG(ui32Base + TIMER_O_ADCEV) & + ~(ui32Val))); + } + + // + // Set the trigger output as requested. + // Set the ADC trigger output as requested. + // + ui32Timer &= TIMER_CTL_TAOTE | TIMER_CTL_TBOTE; + HWREG(ui32Base + TIMER_O_CTL) = (bEnable ? + (HWREG(ui32Base + TIMER_O_CTL) | + ui32Timer) : + (HWREG(ui32Base + TIMER_O_CTL) & + ~(ui32Timer))); +} + +//***************************************************************************** +// +//! Controls the event type. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to be adjusted; must be one of +//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. +//! \param ui32Event specifies the type of event; must be one of +//! \b TIMER_EVENT_POS_EDGE, \b TIMER_EVENT_NEG_EDGE, or +//! \b TIMER_EVENT_BOTH_EDGES. +//! +//! This function configures the signal edge(s) that triggers the timer when +//! in capture mode. +//! +//! \return None. +// +//***************************************************************************** +void +TimerControlEvent(uint32_t ui32Base, uint32_t ui32Timer, + uint32_t ui32Event) +{ + // + // Check the arguments. + // + ASSERT(_TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // + // Set the event type. + // + ui32Timer &= TIMER_CTL_TAEVENT_M | TIMER_CTL_TBEVENT_M; + HWREG(ui32Base + TIMER_O_CTL) = ((HWREG(ui32Base + TIMER_O_CTL) & + ~ui32Timer) | (ui32Event & ui32Timer)); +} + +//***************************************************************************** +// +//! Controls the stall handling. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to be adjusted; must be one of +//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. +//! \param bStall specifies the response to a stall signal. +//! +//! This function controls the stall response for the specified timer. If the +//! \e bStall parameter is \b true, then the timer stops counting if the +//! processor enters debug mode; otherwise the timer keeps running while in +//! debug mode. +//! +//! \return None. +// +//***************************************************************************** +void +TimerControlStall(uint32_t ui32Base, uint32_t ui32Timer, + bool bStall) +{ + // + // Check the arguments. + // + ASSERT(_TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // + // Set the stall mode. + // + ui32Timer &= TIMER_CTL_TASTALL | TIMER_CTL_TBSTALL; + HWREG(ui32Base + TIMER_O_CTL) = (bStall ? + (HWREG(ui32Base + TIMER_O_CTL) | + ui32Timer) : + (HWREG(ui32Base + TIMER_O_CTL) & + ~(ui32Timer))); +} + +//***************************************************************************** +// +//! Controls the wait on trigger handling. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to be adjusted; must be one of +//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. +//! \param bWait specifies if the timer should wait for a trigger input. +//! +//! This function controls whether or not a timer waits for a trigger input to +//! start counting. When enabled, the previous timer in the trigger chain must +//! count to its timeout in order for this timer to start counting. Refer to +//! the part's data sheet for a description of the trigger chain. +//! +//! \note This functionality is not available on all parts. This function +//! should not be used for Timer 0A or Wide Timer 0A. +//! +//! \return None. +// +//***************************************************************************** +void +TimerControlWaitOnTrigger(uint32_t ui32Base, uint32_t ui32Timer, + bool bWait) +{ + // + // Check the arguments. + // + ASSERT(_TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // + // Set the wait on trigger mode for timer A. + // + if((ui32Timer & TIMER_A) != 0) + { + if(bWait) + { + HWREG(ui32Base + TIMER_O_TAMR) |= TIMER_TAMR_TAWOT; + } + else + { + HWREG(ui32Base + TIMER_O_TAMR) &= ~(TIMER_TAMR_TAWOT); + } + } + + // + // Set the wait on trigger mode for timer B. + // + if((ui32Timer & TIMER_B) != 0) + { + if(bWait) + { + HWREG(ui32Base + TIMER_O_TBMR) |= TIMER_TBMR_TBWOT; + } + else + { + HWREG(ui32Base + TIMER_O_TBMR) &= ~(TIMER_TBMR_TBWOT); + } + } +} + +//***************************************************************************** +// +//! Enables RTC counting. +//! +//! \param ui32Base is the base address of the timer module. +//! +//! This function causes the timer to start counting when in RTC mode. If not +//! configured for RTC mode, this function does nothing. +//! +//! \return None. +// +//***************************************************************************** +void +TimerRTCEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_TimerBaseValid(ui32Base)); + + // + // Enable RTC counting. + // + HWREG(ui32Base + TIMER_O_CTL) |= TIMER_CTL_RTCEN; +} + +//***************************************************************************** +// +//! Disables RTC counting. +//! +//! \param ui32Base is the base address of the timer module. +//! +//! This function causes the timer to stop counting when in RTC mode. +//! +//! \return None. +// +//***************************************************************************** +void +TimerRTCDisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_TimerBaseValid(ui32Base)); + + // + // Disable RTC counting. + // + HWREG(ui32Base + TIMER_O_CTL) &= ~(TIMER_CTL_RTCEN); +} + +//***************************************************************************** +// +//! Sets the clock source for the specified timer module. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Source is the clock source for the timer module. +//! +//! This function sets the clock source for both timer A and timer B for the +//! given timer module. The possible clock sources are the system clock +//! (\b TIMER_CLOCK_SYSTEM) or the precision internal oscillator +//! (\b TIMER_CLOCK_PIOSC). +//! +//! \note The ability to specify the timer clock source varies with the +//! Tiva part in use. Please consult the data sheet for the part you are +//! using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +TimerClockSourceSet(uint32_t ui32Base, uint32_t ui32Source) +{ + // + // Check the arguments. + // + ASSERT(_TimerBaseValid(ui32Base)); + ASSERT((ui32Source == TIMER_CLOCK_SYSTEM) || + (ui32Source == TIMER_CLOCK_PIOSC)); + + // + // Set the timer clock source. + // + HWREG(ui32Base + TIMER_O_CC) = ui32Source; +} + +//***************************************************************************** +// +//! Returns the clock source for the specified timer module. +//! +//! \param ui32Base is the base address of the timer module. +//! +//! This function returns the clock source for the specified timer module. The +//! possible clock sources are the system clock (\b TIMER_CLOCK_SYSTEM) or +//! the precision internal oscillator (\b TIMER_CLOCK_PIOSC). +//! +//! \note The ability to specify the timer clock source varies with the +//! Tiva part in use. Please consult the data sheet for the part you are +//! using to determine whether this support is available. +//! +//! \return Returns either \b TIMER_CLOCK_SYSTEM or \b TIMER_CLOCK_PIOSC. +// +//***************************************************************************** +uint32_t +TimerClockSourceGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_TimerBaseValid(ui32Base)); + + // + // Return the timer clock source. + // + return(HWREG(ui32Base + TIMER_O_CC)); +} + +//***************************************************************************** +// +//! Sets the timer prescale value. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to adjust; must be one of +//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. +//! \param ui32Value is the timer prescale value which must be between 0 and +//! 255 (inclusive) for 16/32-bit timers and between 0 and 65535 (inclusive) +//! for 32/64-bit timers. +//! +//! This function configures the value of the input clock prescaler. The +//! prescaler is only operational when in half-width mode and is used to extend +//! the range of the half-width timer modes. The prescaler provides the least +//! significant bits when counting down in periodic and one-shot modes; in all +//! other modes, the prescaler provides the most significant bits. +//! +//! \note The availability of the prescaler varies with the Tiva part and +//! timer mode in use. Please consult the datasheet for the part you are using +//! to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +TimerPrescaleSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value) +{ + // + // Check the arguments. + // + ASSERT(_TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + ASSERT(ui32Value < 256); + + // + // Set the timer A prescaler if requested. + // + if(ui32Timer & TIMER_A) + { + HWREG(ui32Base + TIMER_O_TAPR) = ui32Value; + } + + // + // Set the timer B prescaler if requested. + // + if(ui32Timer & TIMER_B) + { + HWREG(ui32Base + TIMER_O_TBPR) = ui32Value; + } +} + +//***************************************************************************** +// +//! Gets the timer prescale value. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. +//! +//! This function gets the value of the input clock prescaler. The prescaler +//! is only operational when in half-width mode and is used to extend the range +//! of the half-width timer modes. The prescaler provides the least +//! significant bits when counting down in periodic and one-shot modes; in all +//! other modes, the prescaler provides the most significant bits. +//! +//! \note The availability of the prescaler varies with the Tiva part and +//! timer mode in use. Please consult the datasheet for the part you are using +//! to determine whether this support is available. +//! +//! \return The value of the timer prescaler. +// +//***************************************************************************** +uint32_t +TimerPrescaleGet(uint32_t ui32Base, uint32_t ui32Timer) +{ + // + // Check the arguments. + // + ASSERT(_TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // + // Return the appropriate prescale value. + // + return((ui32Timer == TIMER_A) ? HWREG(ui32Base + TIMER_O_TAPR) : + HWREG(ui32Base + TIMER_O_TBPR)); +} + +//***************************************************************************** +// +//! Sets the timer prescale match value. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to adjust; must be one of +//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. +//! \param ui32Value is the timer prescale match value which must be between 0 +//! and 255 (inclusive) for 16/32-bit timers and between 0 and 65535 +//! (inclusive) for 32/64-bit timers. +//! +//! This function configures the value of the input clock prescaler match +//! value. When in a half-width mode that uses the counter match and the +//! prescaler, the prescale match effectively extends the range of the match. +//! The prescaler provides the least significant bits when counting down in +//! periodic and one-shot modes; in all other modes, the prescaler provides the +//! most significant bits. +//! +//! \note The availability of the prescaler match varies with the Tiva +//! part and timer mode in use. Please consult the datasheet for the part you +//! are using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +TimerPrescaleMatchSet(uint32_t ui32Base, uint32_t ui32Timer, + uint32_t ui32Value) +{ + // + // Check the arguments. + // + ASSERT(_TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + ASSERT(ui32Value < 256); + + // + // Set the timer A prescale match if requested. + // + if(ui32Timer & TIMER_A) + { + HWREG(ui32Base + TIMER_O_TAPMR) = ui32Value; + } + + // + // Set the timer B prescale match if requested. + // + if(ui32Timer & TIMER_B) + { + HWREG(ui32Base + TIMER_O_TBPMR) = ui32Value; + } +} + +//***************************************************************************** +// +//! Gets the timer prescale match value. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. +//! +//! This function gets the value of the input clock prescaler match value. +//! When in a half-width mode that uses the counter match and prescaler, the +//! prescale match effectively extends the range of the match. The prescaler +//! provides the least significant bits when counting down in periodic and +//! one-shot modes; in all other modes, the prescaler provides the most +//! significant bits. +//! +//! \note The availability of the prescaler match varies with the Tiva +//! part and timer mode in use. Please consult the datasheet for the part you +//! are using to determine whether this support is available. +//! +//! \return The value of the timer prescale match. +// +//***************************************************************************** +uint32_t +TimerPrescaleMatchGet(uint32_t ui32Base, uint32_t ui32Timer) +{ + // + // Check the arguments. + // + ASSERT(_TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // + // Return the appropriate prescale match value. + // + return((ui32Timer == TIMER_A) ? HWREG(ui32Base + TIMER_O_TAPMR) : + HWREG(ui32Base + TIMER_O_TBPMR)); +} + +//***************************************************************************** +// +//! Sets the timer load value. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to adjust; must be one of +//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used +//! when the timer is configured for full-width operation. +//! \param ui32Value is the load value. +//! +//! This function configures the timer load value; if the timer is running then +//! the value is immediately loaded into the timer. +//! +//! \note This function can be used for both full- and half-width modes of +//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use +//! TimerLoadSet64() for full-width modes of 32/64-bit timers. +//! +//! \return None. +// +//***************************************************************************** +void +TimerLoadSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value) +{ + // + // Check the arguments. + // + ASSERT(_TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // + // Set the timer A load value if requested. + // + if(ui32Timer & TIMER_A) + { + HWREG(ui32Base + TIMER_O_TAILR) = ui32Value; + } + + // + // Set the timer B load value if requested. + // + if(ui32Timer & TIMER_B) + { + HWREG(ui32Base + TIMER_O_TBILR) = ui32Value; + } +} + +//***************************************************************************** +// +//! Gets the timer load value. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured +//! for full-width operation. +//! +//! This function gets the currently programmed interval load value for the +//! specified timer. +//! +//! \note This function can be used for both full- and half-width modes of +//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use +//! TimerLoadGet64() for full-width modes of 32/64-bit timers. +//! +//! \return Returns the load value for the timer. +// +//***************************************************************************** +uint32_t +TimerLoadGet(uint32_t ui32Base, uint32_t ui32Timer) +{ + // + // Check the arguments. + // + ASSERT(_TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); + + // + // Return the appropriate load value. + // + return((ui32Timer == TIMER_A) ? HWREG(ui32Base + TIMER_O_TAILR) : + HWREG(ui32Base + TIMER_O_TBILR)); +} + +//***************************************************************************** +// +//! Sets the timer load value for a 64-bit timer. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui64Value is the load value. +//! +//! This function configures the timer load value for a 64-bit timer; if the +//! timer is running, then the value is immediately loaded into the timer. +//! +//! \return None. +// +//***************************************************************************** +void +TimerLoadSet64(uint32_t ui32Base, uint64_t ui64Value) +{ + // + // Check the arguments. + // + ASSERT(_TimerBaseValid(ui32Base)); + + // + // Set the timer load value. The upper 32-bits must be written before the + // lower 32-bits in order to adhere to the hardware interlocks on the + // 64-bit value. + // + HWREG(ui32Base + TIMER_O_TBILR) = ui64Value >> 32; + HWREG(ui32Base + TIMER_O_TAILR) = ui64Value & 0xffffffff; +} + +//***************************************************************************** +// +//! Gets the timer load value for a 64-bit timer. +//! +//! \param ui32Base is the base address of the timer module. +//! +//! This function gets the currently programmed interval load value for the +//! specified 64-bit timer. +//! +//! \return Returns the load value for the timer. +// +//***************************************************************************** +uint64_t +TimerLoadGet64(uint32_t ui32Base) +{ + uint32_t ui32High1, ui32High2, ui32Low; + + // + // Check the arguments. + // + ASSERT(_TimerBaseValid(ui32Base)); + + // + // Read the 64-bit load value. A read of the low 32-bits is performed + // between two reads of the upper 32-bits; if the upper 32-bit values match + // then the 64-bit value is consistent. If they do not match, then the + // read is performed again until they do match (it should never execute the + // loop body more than twice). + // + do + { + ui32High1 = HWREG(ui32Base + TIMER_O_TBILR); + ui32Low = HWREG(ui32Base + TIMER_O_TAILR); + ui32High2 = HWREG(ui32Base + TIMER_O_TBILR); + } + while(ui32High1 != ui32High2); + + // + // Return the load value. + // + return(((uint64_t)ui32High1 << 32) | (uint64_t)ui32Low); +} + +//***************************************************************************** +// +//! Gets the current timer value. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured +//! for full-width operation. +//! +//! This function reads the current value of the specified timer. +//! +//! \note This function can be used for both full- and half-width modes of +//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use +//! TimerValueGet64() for full-width modes of 32/64-bit timers. +//! +//! \return Returns the current value of the timer. +// +//***************************************************************************** +uint32_t +TimerValueGet(uint32_t ui32Base, uint32_t ui32Timer) +{ + // + // Check the arguments. + // + ASSERT(_TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); + + // + // Return the appropriate timer value. + // + return((ui32Timer == TIMER_A) ? HWREG(ui32Base + TIMER_O_TAR) : + HWREG(ui32Base + TIMER_O_TBR)); +} + +//***************************************************************************** +// +//! Gets the current 64-bit timer value. +//! +//! \param ui32Base is the base address of the timer module. +//! +//! This function reads the current value of the specified timer. +//! +//! \return Returns the current value of the timer. +// +//***************************************************************************** +uint64_t +TimerValueGet64(uint32_t ui32Base) +{ + uint32_t ui32High1, ui32High2, ui32Low; + + // + // Check the arguments. + // + ASSERT(_TimerBaseValid(ui32Base)); + + // + // Read the 64-bit timer value. A read of the low 32-bits is performed + // between two reads of the upper 32-bits; if the upper 32-bit values match + // then the 64-bit value is consistent. If they do not match, then the + // read is performed again until they do match (it should never execute the + // loop body more than twice). + // + do + { + ui32High1 = HWREG(ui32Base + TIMER_O_TBR); + ui32Low = HWREG(ui32Base + TIMER_O_TAR); + ui32High2 = HWREG(ui32Base + TIMER_O_TBR); + } + while(ui32High1 != ui32High2); + + // + // Return the timer value. + // + return(((uint64_t)ui32High1 << 32) | (uint64_t)ui32Low); +} + +//***************************************************************************** +// +//! Sets the timer match value. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to adjust; must be one of +//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used +//! when the timer is configured for full-width operation. +//! \param ui32Value is the match value. +//! +//! This function configures the match value for a timer. This value is used +//! in capture count mode to determine when to interrupt the processor and in +//! PWM mode to determine the duty cycle of the output signal. On some +//! Tiva devices, match interrupts can also be generated in periodic and +//! one-shot modes. +//! +//! \note This function can be used for both full- and half-width modes of +//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use +//! TimerMatchSet64() for full-width modes of 32/64-bit timers. +//! +//! \return None. +// +//***************************************************************************** +void +TimerMatchSet(uint32_t ui32Base, uint32_t ui32Timer, + uint32_t ui32Value) +{ + // + // Check the arguments. + // + ASSERT(_TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // + // Set the timer A match value if requested. + // + if(ui32Timer & TIMER_A) + { + HWREG(ui32Base + TIMER_O_TAMATCHR) = ui32Value; + } + + // + // Set the timer B match value if requested. + // + if(ui32Timer & TIMER_B) + { + HWREG(ui32Base + TIMER_O_TBMATCHR) = ui32Value; + } +} + +//***************************************************************************** +// +//! Gets the timer match value. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured +//! for full-width operation. +//! +//! This function gets the match value for the specified timer. +//! +//! \note This function can be used for both full- and half-width modes of +//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use +//! TimerMatchGet64() for full-width modes of 32/64-bit timers. +//! +//! \return Returns the match value for the timer. +// +//***************************************************************************** +uint32_t +TimerMatchGet(uint32_t ui32Base, uint32_t ui32Timer) +{ + // + // Check the arguments. + // + ASSERT(_TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); + + // + // Return the appropriate match value. + // + return((ui32Timer == TIMER_A) ? HWREG(ui32Base + TIMER_O_TAMATCHR) : + HWREG(ui32Base + TIMER_O_TBMATCHR)); +} + +//***************************************************************************** +// +//! Sets the timer match value for a 64-bit timer. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui64Value is the match value. +//! +//! This function configures the match value for a timer. This value is used +//! in capture count mode to determine when to interrupt the processor and in +//! PWM mode to determine the duty cycle of the output signal. +//! +//! \return None. +// +//***************************************************************************** +void +TimerMatchSet64(uint32_t ui32Base, uint64_t ui64Value) +{ + // + // Check the arguments. + // + ASSERT(_TimerBaseValid(ui32Base)); + + // + // Set the timer match value. The upper 32-bits must be written before the + // lower 32-bits in order to adhere to the hardware interlocks on the + // 64-bit value. + // + HWREG(ui32Base + TIMER_O_TBMATCHR) = ui64Value >> 32; + HWREG(ui32Base + TIMER_O_TAMATCHR) = ui64Value & 0xffffffff; +} + +//***************************************************************************** +// +//! Gets the timer match value for a 64-bit timer. +//! +//! \param ui32Base is the base address of the timer module. +//! +//! This function gets the match value for the specified timer. +//! +//! \return Returns the match value for the timer. +// +//***************************************************************************** +uint64_t +TimerMatchGet64(uint32_t ui32Base) +{ + uint32_t ui32High1, ui32High2, ui32Low; + + // + // Check the arguments. + // + ASSERT(_TimerBaseValid(ui32Base)); + + // + // Read the 64-bit match value. A read of the low 32-bits is performed + // between two reads of the upper 32-bits; if the upper 32-bit values match + // then the 64-bit value is consistent. If they do not match, then the + // read is performed again until they do match (it should never execute the + // loop body more than twice). + // + do + { + ui32High1 = HWREG(ui32Base + TIMER_O_TBMATCHR); + ui32Low = HWREG(ui32Base + TIMER_O_TAMATCHR); + ui32High2 = HWREG(ui32Base + TIMER_O_TBMATCHR); + } + while(ui32High1 != ui32High2); + + // + // Return the match value. + // + return(((uint64_t)ui32High1 << 32) | (uint64_t)ui32Low); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the timer interrupt. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s); must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! \param pfnHandler is a pointer to the function to be called when the timer +//! interrupt occurs. +//! +//! This function registers the handler to be called when a timer interrupt +//! occurs. In addition, this function enables the global interrupt in the +//! interrupt controller; specific timer interrupts must be enabled via +//! TimerIntEnable(). It is the interrupt handler's responsibility to clear +//! the interrupt source via TimerIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +TimerIntRegister(uint32_t ui32Base, uint32_t ui32Timer, + void (*pfnHandler)(void)) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT(_TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // + // Get the interrupt number for this timer module. + // + ui32Int = _TimerIntNumberGet(ui32Base, ui32Timer); + + ASSERT(ui32Int != 0); + + // + // Register the interrupt handler. + // + IntRegister(ui32Int, pfnHandler); + + // + // Enable the interrupt. + // + IntEnable(ui32Int); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the timer interrupt. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s); must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! +//! This function unregisters the handler to be called when a timer interrupt +//! occurs. This function also masks off the interrupt in the interrupt +//! controller so that the interrupt handler is no longer called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +TimerIntUnregister(uint32_t ui32Base, uint32_t ui32Timer) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT(_TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // + // Get the interrupt number for this timer module. + // + ui32Int = _TimerIntNumberGet(ui32Base, ui32Timer); + + // + // Disable the interrupt. + // + IntDisable(ui32Int); + + // + // Unregister the interrupt handler. + // + IntUnregister(ui32Int); +} + +//***************************************************************************** +// +//! Enables individual timer interrupt sources. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated timer interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ui32IntFlags parameter must be the logical OR of any combination of +//! the following: +//! +//! - \b TIMER_TIMB_DMA - Timer B uDMA complete +//! - \b TIMER_TIMA_DMA - Timer A uDMA complete +//! - \b TIMER_CAPB_EVENT - Capture B event interrupt +//! - \b TIMER_CAPB_MATCH - Capture B match interrupt +//! - \b TIMER_TIMB_TIMEOUT - Timer B timeout interrupt +//! - \b TIMER_RTC_MATCH - RTC interrupt mask +//! - \b TIMER_CAPA_EVENT - Capture A event interrupt +//! - \b TIMER_CAPA_MATCH - Capture A match interrupt +//! - \b TIMER_TIMA_TIMEOUT - Timer A timeout interrupt +//! +//! \return None. +// +//***************************************************************************** +void +TimerIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(_TimerBaseValid(ui32Base)); + + // + // Enable the specified interrupts. + // + HWREG(ui32Base + TIMER_O_IMR) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! Disables individual timer interrupt sources. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be +//! disabled. +//! +//! This function disables the indicated timer interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ui32IntFlags parameter has the same definition as the +//! \e ui32IntFlags parameter to TimerIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +TimerIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(_TimerBaseValid(ui32Base)); + + // + // Disable the specified interrupts. + // + HWREG(ui32Base + TIMER_O_IMR) &= ~(ui32IntFlags); +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ui32Base is the base address of the timer module. +//! \param bMasked is false if the raw interrupt status is required and true if +//! the masked interrupt status is required. +//! +//! This function returns the interrupt status for the timer module. Either +//! the raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! values described in TimerIntEnable(). +// +//***************************************************************************** +uint32_t +TimerIntStatus(uint32_t ui32Base, bool bMasked) +{ + // + // Check the arguments. + // + ASSERT(_TimerBaseValid(ui32Base)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + return(bMasked ? HWREG(ui32Base + TIMER_O_MIS) : + HWREG(ui32Base + TIMER_O_RIS)); +} + +//***************************************************************************** +// +//! Clears timer interrupt sources. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified timer interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being triggered again immediately upon exit. +//! +//! The \e ui32IntFlags parameter has the same definition as the +//! \e ui32IntFlags parameter to TimerIntEnable(). +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +TimerIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(_TimerBaseValid(ui32Base)); + + // + // Clear the requested interrupt sources. + // + HWREG(ui32Base + TIMER_O_ICR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! Synchronizes the counters in a set of timers. +//! +//! \param ui32Base is the base address of the timer module. This parameter +//! must be the base address of Timer0 (in other words, \b TIMER0_BASE). +//! \param ui32Timers is the set of timers to synchronize. +//! +//! This function synchronizes the counters in a specified set of timers. +//! When a timer is running in half-width mode, each half can be included or +//! excluded in the synchronization event. When a timer is running in +//! full-width mode, only the A timer can be synchronized (specifying the B +//! timer has no effect). +//! +//! The \e ui32Timers parameter is the logical OR of any of the following +//! defines: +//! +//! - \b TIMER_0A_SYNC +//! - \b TIMER_0B_SYNC +//! - \b TIMER_1A_SYNC +//! - \b TIMER_1B_SYNC +//! - \b TIMER_2A_SYNC +//! - \b TIMER_2B_SYNC +//! - \b TIMER_3A_SYNC +//! - \b TIMER_3B_SYNC +//! - \b TIMER_4A_SYNC +//! - \b TIMER_4B_SYNC +//! - \b TIMER_5A_SYNC +//! - \b TIMER_5B_SYNC +//! - \b WTIMER_0A_SYNC +//! - \b WTIMER_0B_SYNC +//! - \b WTIMER_1A_SYNC +//! - \b WTIMER_1B_SYNC +//! - \b WTIMER_2A_SYNC +//! - \b WTIMER_2B_SYNC +//! - \b WTIMER_3A_SYNC +//! - \b WTIMER_3B_SYNC +//! - \b WTIMER_4A_SYNC +//! - \b WTIMER_4B_SYNC +//! - \b WTIMER_5A_SYNC +//! - \b WTIMER_5B_SYNC +//! +//! \note This functionality is not available on all parts. +//! +//! \return None. +// +//***************************************************************************** +void +TimerSynchronize(uint32_t ui32Base, uint32_t ui32Timers) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == TIMER0_BASE); + + // + // Synchronize the specified timers. + // + HWREG(ui32Base + TIMER_O_SYNC) = ui32Timers; +} + +//***************************************************************************** +// +//! Enables the events that can cause an ADC trigger event. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32ADCEvent is a bit mask of the events that can cause an ADC +//! trigger event. +//! +//! This function enables the timer events that can cause an ADC trigger event. +//! The ADC trigger events are specified in the \e ui32ADCEvent parameter by +//! passing in the logical OR of any of the following values: +//! +//! - \b TIMER_ADC_MODEMATCH_B - Enables the mode match ADC trigger for timer +//! B. +//! - \b TIMER_ADC_CAPEVENT_B - Enables the capture event ADC trigger for +//! timer B. +//! - \b TIMER_ADC_CAPMATCH_B - Enables the capture match ADC trigger for +//! timer B. +//! - \b TIMER_ADC_TIMEOUT_B - Enables the timeout ADC trigger for timer B. +//! - \b TIMER_ADC_MODEMATCH_A - Enables the mode match ADC trigger for timer +//! A. +//! - \b TIMER_ADC_RTC_A - Enables the RTC ADC trigger for timer A. +//! - \b TIMER_ADC_CAPEVENT_A - Enables the capture event ADC trigger for +//! timer A. +//! - \b TIMER_ADC_CAPMATCH_A - Enables the capture match ADC trigger for +//! timer A. +//! - \b TIMER_ADC_TIMEOUT_A - Enables the timeout ADC trigger for timer A. +//! +//! \note The ability to specify ADC event triggers varies with the Tiva +//! part in use. Please consult the data sheet for the part you are +//! using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +TimerADCEventSet(uint32_t ui32Base, uint32_t ui32ADCEvent) +{ + // + // Check the arguments. + // + ASSERT(_TimerBaseValid(ui32Base)); + + // + // Set the ADC triggers. + // + HWREG(ui32Base + TIMER_O_ADCEV) = ui32ADCEvent; +} + +//***************************************************************************** +// +//! Returns the events that can cause an ADC trigger event. +//! +//! \param ui32Base is the base address of the timer module. +//! +//! This function returns the timer events that can cause an ADC trigger event. +//! The ADC trigger events are the logical OR of any of the following values: +//! +//! - \b TIMER_ADC_MODEMATCH_B - The mode match ADC trigger for timer B is +//! enabled. +//! - \b TIMER_ADC_CAPEVENT_B - The capture event ADC trigger for timer B is +//! enabled. +//! - \b TIMER_ADC_CAPMATCH_B - The capture match ADC trigger for timer B is +//! enabled. +//! - \b TIMER_ADC_TIMEOUT_B - The timeout ADC trigger for timer B is enabled. +//! - \b TIMER_ADC_MODEMATCH_A - The mode match ADC trigger for timer A is +//! enabled. +//! - \b TIMER_ADC_RTC_A - The RTC ADC trigger for timer A is enabled. +//! - \b TIMER_ADC_CAPEVENT_A - The capture event ADC trigger for timer A is +//! enabled. +//! - \b TIMER_ADC_CAPMATCH_A - The capture match ADC trigger for timer A is +//! enabled. +//! - \b TIMER_ADC_TIMEOUT_A - The timeout ADC trigger for timer A is enabled. +//! +//! \note The ability to specify ADC event triggers varies with the Tiva +//! part in use. Please consult the data sheet for the part you are +//! using to determine whether this support is available. +//! +//! \return The timer events that trigger the ADC. +// +//***************************************************************************** +uint32_t +TimerADCEventGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_TimerBaseValid(ui32Base)); + + // + // Return the current ADC triggers. + // + return(HWREG(ui32Base + TIMER_O_ADCEV)); +} + +//***************************************************************************** +// +//! Enables the events that can trigger a uDMA request. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32DMAEvent is a bit mask of the events that can trigger uDMA. +//! +//! This function enables the timer events that can trigger the start of a uDMA +//! sequence. The uDMA trigger events are specified in the \e ui32DMAEvent +//! parameter by passing in the logical OR of the following values: +//! +//! - \b TIMER_DMA_MODEMATCH_B - The mode match uDMA trigger for timer B is +//! enabled. +//! - \b TIMER_DMA_CAPEVENT_B - The capture event uDMA trigger for timer B is +//! enabled. +//! - \b TIMER_DMA_CAPMATCH_B - The capture match uDMA trigger for timer B is +//! enabled. +//! - \b TIMER_DMA_TIMEOUT_B - The timeout uDMA trigger for timer B is enabled. +//! - \b TIMER_DMA_MODEMATCH_A - The mode match uDMA trigger for timer A is +//! enabled. +//! - \b TIMER_DMA_RTC_A - The RTC uDMA trigger for timer A is enabled. +//! - \b TIMER_DMA_CAPEVENT_A - The capture event uDMA trigger for timer A is +//! enabled. +//! - \b TIMER_DMA_CAPMATCH_A - The capture match uDMA trigger for timer A is +//! enabled. +//! - \b TIMER_DMA_TIMEOUT_A - The timeout uDMA trigger for timer A is enabled. +//! +//! \note The ability to specify uDMA event triggers varies with the Tiva +//! part in use. Please consult the data sheet for the part you are +//! using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +TimerDMAEventSet(uint32_t ui32Base, uint32_t ui32DMAEvent) +{ + // + // Check the arguments. + // + ASSERT(_TimerBaseValid(ui32Base)); + + // + // Set the uDMA triggers. + // + HWREG(ui32Base + TIMER_O_DMAEV) = ui32DMAEvent; +} + +//***************************************************************************** +// +//! Returns the events that can trigger a uDMA request. +//! +//! \param ui32Base is the base address of the timer module. +//! +//! This function returns the timer events that can trigger the start of a uDMA +//! sequence. The uDMA trigger events are the logical OR of the following +//! values: +//! +//! - \b TIMER_DMA_MODEMATCH_B - Enables the mode match uDMA trigger for timer +//! B. +//! - \b TIMER_DMA_CAPEVENT_B - Enables the capture event uDMA trigger for +//! timer B. +//! - \b TIMER_DMA_CAPMATCH_B - Enables the capture match uDMA trigger for +//! timer B. +//! - \b TIMER_DMA_TIMEOUT_B - Enables the timeout uDMA trigger for timer B. +//! - \b TIMER_DMA_MODEMATCH_A - Enables the mode match uDMA trigger for timer +//! A. +//! - \b TIMER_DMA_RTC_A - Enables the RTC uDMA trigger for timer A. +//! - \b TIMER_DMA_CAPEVENT_A - Enables the capture event uDMA trigger for +//! timer A. +//! - \b TIMER_DMA_CAPMATCH_A - Enables the capture match uDMA trigger for +//! timer A. +//! - \b TIMER_DMA_TIMEOUT_A - Enables the timeout uDMA trigger for timer A. +//! +//! \note The ability to specify uDMA event triggers varies with the Tiva +//! part in use. Please consult the data sheet for the part you are +//! using to determine whether this support is available. +//! +//! \return The timer events that trigger the uDMA. +// +//***************************************************************************** +uint32_t +TimerDMAEventGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_TimerBaseValid(ui32Base)); + + // + // Return the current uDMA triggers. + // + return(HWREG(ui32Base + TIMER_O_DMAEV)); +} + +//***************************************************************************** +// +//! This function configures the update of timer load and match settings. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s); must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! \param ui32Config is a combination of the updates methods for the timers +//! specified in the \e ui32Timer parameter. +//! +//! This function configures how the timer updates the timer load and match +//! values for the timers. The \e ui32Timer values can be \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH to apply the settings in \e ui32Config to +//! either timer or both timers. If the timer is not split then the \b TIMER_A +//! should be used. The \e ui32Config values affects when the TimerLoadSet() +//! and TimerLoadSet64() values take effect. +//! +//! - \b TIMER_UP_LOAD_IMMEDIATE is the default mode that causes the +//! TimerLoadSet() or TimerLoadSet64() to update the timer counter immediately. +//! - \b TIMER_UP_LOAD_TIMEOUT causes the TimerLoadSet() or TimerLoadSet64() to +//! update the timer when it counts down to zero. +//! +//! Similarly the \e ui32Config value affects when the TimerMatchSet() and +//! TimerMatchSet64() values take effect. +//! +//! - \b TIMER_UP_MATCH_IMMEDIATE is the default mode that causes the +//! TimerMatchSet() or TimerMatchSet64() to update the timer match value +//! immediately. +//! - \b TIMER_UP_MATCH_TIMEOUT causes the TimerMatchSet() or TimerMatchSet64() +//! to update the timer match value when it counts down to zero. +//! +//! \note These settings have no effect if the timer is not in count down mode +//! and are mostly useful when operating in PWM mode to allow for synchronous +//! update of timer match and load values. +//! +//! \return None. +// +//***************************************************************************** +void +TimerUpdateMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Config) +{ + uint32_t ui32Value; + + if((ui32Timer & TIMER_A) == TIMER_A) + { + ui32Value = HWREG(ui32Base + TIMER_O_TAMR) & ~(0x00000500); + ui32Value |= ui32Config; + HWREG(ui32Base + TIMER_O_TAMR) = ui32Value; + } + + if((ui32Timer & TIMER_B) == TIMER_B) + { + ui32Value = HWREG(ui32Base + TIMER_O_TBMR) & ~(0x00000500); + ui32Value |= ui32Config; + HWREG(ui32Base + TIMER_O_TBMR) = ui32Value; + } +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/uart.c b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/uart.c new file mode 100644 index 0000000000000000000000000000000000000000..83a994d2adf1edb5ed3e69f8398434e1004570f0 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/uart.c @@ -0,0 +1,1993 @@ +//***************************************************************************** +// +// uart.c - Driver for the UART. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup uart_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include "hw_ints.h" +#include "hw_memmap.h" +#include "hw_sysctl.h" +#include "hw_types.h" +#include "hw_uart.h" +#include "debug.h" +#include "interrupt.h" +#include "uart.h" + +//***************************************************************************** +// +// The system clock divider defining the maximum baud rate supported by the +// UART. +// +//***************************************************************************** +#define UART_CLK_DIVIDER 8 + +//***************************************************************************** +// +// A mapping of UART base address to interrupt number. +// +//***************************************************************************** +static const uint32_t g_ppui32UARTIntMap[][2] = +{ + { UART0_BASE, INT_UART0_TM4C123 }, + { UART1_BASE, INT_UART1_TM4C123 }, + { UART2_BASE, INT_UART2_TM4C123 }, + { UART3_BASE, INT_UART3_TM4C123 }, + { UART4_BASE, INT_UART4_TM4C123 }, + { UART5_BASE, INT_UART5_TM4C123 }, + { UART6_BASE, INT_UART6_TM4C123 }, + { UART7_BASE, INT_UART7_TM4C123 }, +}; +static const uint_fast8_t g_ui8UARTIntMapRows = + sizeof(g_ppui32UARTIntMap) / sizeof(g_ppui32UARTIntMap[0]); +static const uint32_t g_ppui32UARTIntMapSnowflake[][2] = +{ + { UART0_BASE, INT_UART0_TM4C129 }, + { UART1_BASE, INT_UART1_TM4C129 }, + { UART2_BASE, INT_UART2_TM4C129 }, + { UART3_BASE, INT_UART3_TM4C129 }, + { UART4_BASE, INT_UART4_TM4C129 }, + { UART5_BASE, INT_UART5_TM4C129 }, + { UART6_BASE, INT_UART6_TM4C129 }, + { UART7_BASE, INT_UART7_TM4C129 }, +}; +static const uint_fast8_t g_ui8UARTIntMapRowsSnowflake = + sizeof(g_ppui32UARTIntMapSnowflake) / + sizeof(g_ppui32UARTIntMapSnowflake[0]); + +//***************************************************************************** +// +//! \internal +//! Checks a UART base address. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function determines if a UART port base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static bool +_UARTBaseValid(uint32_t ui32Base) +{ + return((ui32Base == UART0_BASE) || (ui32Base == UART1_BASE) || + (ui32Base == UART2_BASE) || (ui32Base == UART3_BASE) || + (ui32Base == UART4_BASE) || (ui32Base == UART5_BASE) || + (ui32Base == UART6_BASE) || (ui32Base == UART7_BASE)); +} +#endif + +//***************************************************************************** +// +//! \internal +//! Gets the UART interrupt number. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! Given a UART base address, this function returns the corresponding +//! interrupt number. +//! +//! \return Returns a UART interrupt number, or 0 if \e ui32Base is invalid. +// +//***************************************************************************** +static uint32_t +_UARTIntNumberGet(uint32_t ui32Base) +{ + uint_fast8_t ui8Idx, ui8Rows; + const uint32_t (*ppui32UARTIntMap)[2]; + + // + // Default interrupt map. + // + ppui32UARTIntMap = g_ppui32UARTIntMap; + ui8Rows = g_ui8UARTIntMapRows; + + if(CLASS_IS_TM4C129) + { + ppui32UARTIntMap = g_ppui32UARTIntMapSnowflake; + ui8Rows = g_ui8UARTIntMapRowsSnowflake; + } + + // + // Loop through the table that maps UART base addresses to interrupt + // numbers. + // + for(ui8Idx = 0; ui8Idx < ui8Rows; ui8Idx++) + { + // + // See if this base address matches. + // + if(ppui32UARTIntMap[ui8Idx][0] == ui32Base) + { + // + // Return the corresponding interrupt number. + // + return(ppui32UARTIntMap[ui8Idx][1]); + } + } + + // + // The base address could not be found, so return an error. + // + return(0); +} + +//***************************************************************************** +// +//! Sets the type of parity. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32Parity specifies the type of parity to use. +//! +//! This function configures the type of parity to use for transmitting and +//! expect when receiving. The \e ui32Parity parameter must be one of +//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, +//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO. The last two +//! parameters allow direct control of the parity bit; it is always either one +//! or zero based on the mode. +//! +//! \return None. +// +//***************************************************************************** +void +UARTParityModeSet(uint32_t ui32Base, uint32_t ui32Parity) +{ + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + ASSERT((ui32Parity == UART_CONFIG_PAR_NONE) || + (ui32Parity == UART_CONFIG_PAR_EVEN) || + (ui32Parity == UART_CONFIG_PAR_ODD) || + (ui32Parity == UART_CONFIG_PAR_ONE) || + (ui32Parity == UART_CONFIG_PAR_ZERO)); + + // + // Set the parity mode. + // + HWREG(ui32Base + UART_O_LCRH) = ((HWREG(ui32Base + UART_O_LCRH) & + ~(UART_LCRH_SPS | UART_LCRH_EPS | + UART_LCRH_PEN)) | ui32Parity); +} + +//***************************************************************************** +// +//! Gets the type of parity currently being used. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function gets the type of parity used for transmitting data and +//! expected when receiving data. +//! +//! \return Returns the current parity settings, specified as one of +//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, +//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO. +// +//***************************************************************************** +uint32_t +UARTParityModeGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + + // + // Return the current parity setting. + // + return(HWREG(ui32Base + UART_O_LCRH) & + (UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN)); +} + +//***************************************************************************** +// +//! Sets the FIFO level at which interrupts are generated. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32TxLevel is the transmit FIFO interrupt level, specified as one +//! of \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8, \b UART_FIFO_TX4_8, +//! \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8. +//! \param ui32RxLevel is the receive FIFO interrupt level, specified as one of +//! \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8, \b UART_FIFO_RX4_8, +//! \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8. +//! +//! This function configures the FIFO level at which transmit and receive +//! interrupts are generated. +//! +//! \return None. +// +//***************************************************************************** +void +UARTFIFOLevelSet(uint32_t ui32Base, uint32_t ui32TxLevel, + uint32_t ui32RxLevel) +{ + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + ASSERT((ui32TxLevel == UART_FIFO_TX1_8) || + (ui32TxLevel == UART_FIFO_TX2_8) || + (ui32TxLevel == UART_FIFO_TX4_8) || + (ui32TxLevel == UART_FIFO_TX6_8) || + (ui32TxLevel == UART_FIFO_TX7_8)); + ASSERT((ui32RxLevel == UART_FIFO_RX1_8) || + (ui32RxLevel == UART_FIFO_RX2_8) || + (ui32RxLevel == UART_FIFO_RX4_8) || + (ui32RxLevel == UART_FIFO_RX6_8) || + (ui32RxLevel == UART_FIFO_RX7_8)); + + // + // Set the FIFO interrupt levels. + // + HWREG(ui32Base + UART_O_IFLS) = ui32TxLevel | ui32RxLevel; +} + +//***************************************************************************** +// +//! Gets the FIFO level at which interrupts are generated. +//! +//! \param ui32Base is the base address of the UART port. +//! \param pui32TxLevel is a pointer to storage for the transmit FIFO level, +//! returned as one of \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8, +//! \b UART_FIFO_TX4_8, \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8. +//! \param pui32RxLevel is a pointer to storage for the receive FIFO level, +//! returned as one of \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8, +//! \b UART_FIFO_RX4_8, \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8. +//! +//! This function gets the FIFO level at which transmit and receive interrupts +//! are generated. +//! +//! \return None. +// +//***************************************************************************** +void +UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel, + uint32_t *pui32RxLevel) +{ + uint32_t ui32Temp; + + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + + // + // Read the FIFO level register. + // + ui32Temp = HWREG(ui32Base + UART_O_IFLS); + + // + // Extract the transmit and receive FIFO levels. + // + *pui32TxLevel = ui32Temp & UART_IFLS_TX_M; + *pui32RxLevel = ui32Temp & UART_IFLS_RX_M; +} + +//***************************************************************************** +// +//! Sets the configuration of a UART. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32UARTClk is the rate of the clock supplied to the UART module. +//! \param ui32Baud is the desired baud rate. +//! \param ui32Config is the data format for the port (number of data bits, +//! number of stop bits, and parity). +//! +//! This function configures the UART for operation in the specified data +//! format. The baud rate is provided in the \e ui32Baud parameter and the +//! data format in the \e ui32Config parameter. +//! +//! The \e ui32Config parameter is the logical OR of three values: the number +//! of data bits, the number of stop bits, and the parity. +//! \b UART_CONFIG_WLEN_8, \b UART_CONFIG_WLEN_7, \b UART_CONFIG_WLEN_6, and +//! \b UART_CONFIG_WLEN_5 select from eight to five data bits per byte +//! (respectively). \b UART_CONFIG_STOP_ONE and \b UART_CONFIG_STOP_TWO select +//! one or two stop bits (respectively). \b UART_CONFIG_PAR_NONE, +//! \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, +//! and \b UART_CONFIG_PAR_ZERO select the parity mode (no parity bit, even +//! parity bit, odd parity bit, parity bit always one, and parity bit always +//! zero, respectively). +//! +//! The peripheral clock is the same as the processor clock. The frequency of +//! the system clock is the value returned by SysCtlClockGet() for TM4C123x +//! devices or the value returned by SysCtlClockFreqSet() for TM4C129x devices, +//! or it can be explicitly hard coded if it is constant and known (to save the +//! code/execution overhead of a call to SysCtlClockGet() or fetch of the +//! variable call holding the return value of SysCtlClockFreqSet()). +//! +//! The function disables the UART by calling UARTDisable() before changing the +//! the parameters and enables the UART by calling UARTEnable(). +//! +//! For Tiva parts that have the ability to specify the UART baud clock +//! source (via UARTClockSourceSet()), the peripheral clock can be changed to +//! PIOSC. In this case, the peripheral clock should be specified as +//! 16,000,000 (the nominal rate of PIOSC). +//! +//! \return None. +// +//***************************************************************************** +void +UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, + uint32_t ui32Baud, uint32_t ui32Config) +{ + uint32_t ui32Div; + + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + ASSERT(ui32Baud != 0); + ASSERT(ui32UARTClk >= (ui32Baud * UART_CLK_DIVIDER)); + + // + // Stop the UART. + // + UARTDisable(ui32Base); + + // + // Is the required baud rate greater than the maximum rate supported + // without the use of high speed mode? + // + if((ui32Baud * 16) > ui32UARTClk) + { + // + // Enable high speed mode. + // + HWREG(ui32Base + UART_O_CTL) |= UART_CTL_HSE; + + // + // Half the supplied baud rate to compensate for enabling high speed + // mode. This allows the following code to be common to both cases. + // + ui32Baud /= 2; + } + else + { + // + // Disable high speed mode. + // + HWREG(ui32Base + UART_O_CTL) &= ~(UART_CTL_HSE); + } + + // + // Compute the fractional baud rate divider. + // + ui32Div = (((ui32UARTClk * 8) / ui32Baud) + 1) / 2; + + // + // Set the baud rate. + // + HWREG(ui32Base + UART_O_IBRD) = ui32Div / 64; + HWREG(ui32Base + UART_O_FBRD) = ui32Div % 64; + + // + // Set parity, data length, and number of stop bits. + // + HWREG(ui32Base + UART_O_LCRH) = ui32Config; + + // + // Clear the flags register. + // + HWREG(ui32Base + UART_O_FR) = 0; + + // + // Start the UART. + // + UARTEnable(ui32Base); +} + +//***************************************************************************** +// +//! Gets the current configuration of a UART. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32UARTClk is the rate of the clock supplied to the UART module. +//! \param pui32Baud is a pointer to storage for the baud rate. +//! \param pui32Config is a pointer to storage for the data format. +//! +//! This function determines the baud rate and data format for the UART, given +//! an explicitly provided peripheral clock (hence the ExpClk suffix). The +//! returned baud rate is the actual baud rate; it may not be the exact baud +//! rate requested or an ``official'' baud rate. The data format returned in +//! \e pui32Config is enumerated the same as the \e ui32Config parameter of +//! UARTConfigSetExpClk(). +//! +//! The peripheral clock is the same as the processor clock. The frequency of +//! the system clock is the value returned by SysCtlClockGet() for TM4C123x +//! devices or the value returned by SysCtlClockFreqSet() for TM4C129x devices, +//! or it can be explicitly hard coded if it is constant and known (to save the +//! code/execution overhead of a call to SysCtlClockGet() or fetch of the +//! variable call holding the return value of SysCtlClockFreqSet()). +//! +//! For Tiva parts that have the ability to specify the UART baud clock +//! source (via UARTClockSourceSet()), the peripheral clock can be changed to +//! PIOSC. In this case, the peripheral clock should be specified as +//! 16,000,000 (the nominal rate of PIOSC). +//! +//! \return None. +// +//***************************************************************************** +void +UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, + uint32_t *pui32Baud, uint32_t *pui32Config) +{ + uint32_t ui32Int, ui32Frac; + + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + + // + // Compute the baud rate. + // + ui32Int = HWREG(ui32Base + UART_O_IBRD); + ui32Frac = HWREG(ui32Base + UART_O_FBRD); + *pui32Baud = (ui32UARTClk * 4) / ((64 * ui32Int) + ui32Frac); + + // + // See if high speed mode enabled. + // + if(HWREG(ui32Base + UART_O_CTL) & UART_CTL_HSE) + { + // + // High speed mode is enabled so the actual baud rate is actually + // double what was just calculated. + // + *pui32Baud *= 2; + } + + // + // Get the parity, data length, and number of stop bits. + // + *pui32Config = (HWREG(ui32Base + UART_O_LCRH) & + (UART_LCRH_SPS | UART_LCRH_WLEN_M | UART_LCRH_STP2 | + UART_LCRH_EPS | UART_LCRH_PEN)); +} + +//***************************************************************************** +// +//! Enables transmitting and receiving. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function enables the UART and its transmit and receive FIFOs. +//! +//! \return None. +// +//***************************************************************************** +void +UARTEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + + // + // Enable the FIFO. + // + HWREG(ui32Base + UART_O_LCRH) |= UART_LCRH_FEN; + + // + // Enable RX, TX, and the UART. + // + HWREG(ui32Base + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE | + UART_CTL_RXE); +} + +//***************************************************************************** +// +//! Disables transmitting and receiving. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function disables the UART, waits for the end of transmission of the +//! current character, and flushes the transmit FIFO. +//! +//! \return None. +// +//***************************************************************************** +void +UARTDisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + + // + // Wait for end of TX. + // + while(HWREG(ui32Base + UART_O_FR) & UART_FR_BUSY) + { + } + + // + // Disable the FIFO. + // + HWREG(ui32Base + UART_O_LCRH) &= ~(UART_LCRH_FEN); + + // + // Disable the UART. + // + HWREG(ui32Base + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE | + UART_CTL_RXE); +} + +//***************************************************************************** +// +//! Enables the transmit and receive FIFOs. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This functions enables the transmit and receive FIFOs in the UART. +//! +//! \return None. +// +//***************************************************************************** +void +UARTFIFOEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + + // + // Enable the FIFO. + // + HWREG(ui32Base + UART_O_LCRH) |= UART_LCRH_FEN; +} + +//***************************************************************************** +// +//! Disables the transmit and receive FIFOs. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function disables the transmit and receive FIFOs in the UART. +//! +//! \return None. +// +//***************************************************************************** +void +UARTFIFODisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + + // + // Disable the FIFO. + // + HWREG(ui32Base + UART_O_LCRH) &= ~(UART_LCRH_FEN); +} + +//***************************************************************************** +// +//! Enables SIR (IrDA) mode on the specified UART. +//! +//! \param ui32Base is the base address of the UART port. +//! \param bLowPower indicates if SIR Low Power Mode is to be used. +//! +//! This function enables SIR (IrDA) mode on the UART. If the \e bLowPower +//! flag is set, then SIR low power mode will be selected as well. This +//! function only has an effect if the UART has not been enabled by a call to +//! UARTEnable(). The call UARTEnableSIR() must be made before a call to +//! UARTConfigSetExpClk() because the UARTConfigSetExpClk() function calls the +//! UARTEnable() function. Another option is to call UARTDisable() followed by +//! UARTEnableSIR() and then enable the UART by calling UARTEnable(). +//! +//! \note The availability of SIR (IrDA) operation varies with the Tiva +//! part in use. Please consult the datasheet for the part you are using to +//! determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UARTEnableSIR(uint32_t ui32Base, bool bLowPower) +{ + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + + // + // Enable SIR and SIRLP (if appropriate). + // + if(bLowPower) + { + HWREG(ui32Base + UART_O_CTL) |= (UART_CTL_SIREN | UART_CTL_SIRLP); + } + else + { + HWREG(ui32Base + UART_O_CTL) |= (UART_CTL_SIREN); + } +} + +//***************************************************************************** +// +//! Disables SIR (IrDA) mode on the specified UART. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function disables SIR(IrDA) mode on the UART. This function only has +//! an effect if the UART has not been enabled by a call to UARTEnable(). The +//! call UARTEnableSIR() must be made before a call to UARTConfigSetExpClk() +//! because the UARTConfigSetExpClk() function calls the UARTEnable() function. +//! Another option is to call UARTDisable() followed by UARTEnableSIR() and +//! then enable the UART by calling UARTEnable(). +//! +//! \note The availability of SIR (IrDA) operation varies with the Tiva +//! part in use. Please consult the datasheet for the part you are using to +//! determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UARTDisableSIR(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + + // + // Disable SIR and SIRLP (if appropriate). + // + HWREG(ui32Base + UART_O_CTL) &= ~(UART_CTL_SIREN | UART_CTL_SIRLP); +} + +//***************************************************************************** +// +//! Enables ISO7816 smart card mode on the specified UART. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function enables the SMART control bit for the ISO7816 smart card mode +//! on the UART. This call also sets 8-bit word length and even parity as +//! required by ISO7816. +//! +//! \note The availability of ISO7816 smart card mode varies with the Tiva +//! part and UART in use. Please consult the datasheet for the part you are +//! using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UARTSmartCardEnable(uint32_t ui32Base) +{ + uint32_t ui32Val; + + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + + // + // Set 8-bit word length, even parity, 2 stop bits (note that although the + // STP2 bit is ignored when in smartcard mode, this code lets the caller + // read back the actual setting in use). + // + ui32Val = HWREG(ui32Base + UART_O_LCRH); + ui32Val &= ~(UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN | + UART_LCRH_WLEN_M); + ui32Val |= UART_LCRH_WLEN_8 | UART_LCRH_PEN | UART_LCRH_EPS | + UART_LCRH_STP2; + HWREG(ui32Base + UART_O_LCRH) = ui32Val; + + // + // Enable SMART mode. + // + HWREG(ui32Base + UART_O_CTL) |= UART_CTL_SMART; +} + +//***************************************************************************** +// +//! Disables ISO7816 smart card mode on the specified UART. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function clears the SMART (ISO7816 smart card) bit in the UART +//! control register. +//! +//! \note The availability of ISO7816 smart card mode varies with the Tiva +//! part and UART in use. Please consult the datasheet for the part you are +//! using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UARTSmartCardDisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + + // + // Disable the SMART bit. + // + HWREG(ui32Base + UART_O_CTL) &= ~UART_CTL_SMART; +} + +//***************************************************************************** +// +//! Sets the states of the DTR and/or RTS modem control signals. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32Control is a bit-mapped flag indicating which modem control bits +//! should be set. +//! +//! This function configures the states of the DTR or RTS modem handshake +//! outputs from the UART. +//! +//! The \e ui32Control parameter is the logical OR of any of the following: +//! +//! - \b UART_OUTPUT_DTR - The modem control DTR signal +//! - \b UART_OUTPUT_RTS - The modem control RTS signal +//! +//! \note The availability of hardware modem handshake signals varies with the +//! Tiva part and UART in use. Please consult the datasheet for the part +//! you are using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UARTModemControlSet(uint32_t ui32Base, uint32_t ui32Control) +{ + uint32_t ui32Temp; + + // + // Check the arguments. + // + ASSERT(ui32Base == UART1_BASE); + ASSERT((ui32Control & ~(UART_OUTPUT_RTS | UART_OUTPUT_DTR)) == 0); + + // + // Set the appropriate modem control output bits. + // + ui32Temp = HWREG(ui32Base + UART_O_CTL); + ui32Temp |= (ui32Control & (UART_OUTPUT_RTS | UART_OUTPUT_DTR)); + HWREG(ui32Base + UART_O_CTL) = ui32Temp; +} + +//***************************************************************************** +// +//! Clears the states of the DTR and/or RTS modem control signals. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32Control is a bit-mapped flag indicating which modem control bits +//! should be set. +//! +//! This function clears the states of the DTR or RTS modem handshake outputs +//! from the UART. +//! +//! The \e ui32Control parameter is the logical OR of any of the following: +//! +//! - \b UART_OUTPUT_DTR - The modem control DTR signal +//! - \b UART_OUTPUT_RTS - The modem control RTS signal +//! +//! \note The availability of hardware modem handshake signals varies with the +//! Tiva part and UART in use. Please consult the datasheet for the part +//! you are using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UARTModemControlClear(uint32_t ui32Base, uint32_t ui32Control) +{ + uint32_t ui32Temp; + + // + // Check the arguments. + // + ASSERT(ui32Base == UART1_BASE); + ASSERT((ui32Control & ~(UART_OUTPUT_RTS | UART_OUTPUT_DTR)) == 0); + + // + // Set the appropriate modem control output bits. + // + ui32Temp = HWREG(ui32Base + UART_O_CTL); + ui32Temp &= ~(ui32Control & (UART_OUTPUT_RTS | UART_OUTPUT_DTR)); + HWREG(ui32Base + UART_O_CTL) = ui32Temp; +} + +//***************************************************************************** +// +//! Gets the states of the DTR and RTS modem control signals. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function returns the current states of each of the two UART modem +//! control signals, DTR and RTS. +//! +//! \note The availability of hardware modem handshake signals varies with the +//! Tiva part and UART in use. Please consult the datasheet for the part +//! you are using to determine whether this support is available. +//! +//! \return Returns the states of the handshake output signals. This value is +//! a logical OR combination of values \b UART_OUTPUT_RTS and +//! \b UART_OUTPUT_DTR where the presence of each flag indicates that the +//! associated signal is asserted. +// +//***************************************************************************** +uint32_t +UARTModemControlGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == UART1_BASE); + + return(HWREG(ui32Base + UART_O_CTL) & (UART_OUTPUT_RTS | UART_OUTPUT_DTR)); +} + +//***************************************************************************** +// +//! Gets the states of the RI, DCD, DSR and CTS modem status signals. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function returns the current states of each of the four UART modem +//! status signals, RI, DCD, DSR and CTS. +//! +//! \note The availability of hardware modem handshake signals varies with the +//! Tiva part and UART in use. Please consult the datasheet for the part +//! you are using to determine whether this support is available. +//! +//! \return Returns the states of the handshake output signals. This value +//! is a logical OR combination of values \b UART_INPUT_RI, +//! \b UART_INPUT_DCD, \b UART_INPUT_CTS and \b UART_INPUT_DSR where the +//! presence of each flag indicates that the associated signal is asserted. +// +//***************************************************************************** +uint32_t +UARTModemStatusGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == UART1_BASE); + + return(HWREG(ui32Base + UART_O_FR) & (UART_INPUT_RI | UART_INPUT_DCD | + UART_INPUT_CTS | UART_INPUT_DSR)); +} + +//***************************************************************************** +// +//! Sets the UART hardware flow control mode to be used. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32Mode indicates the flow control modes to be used. This +//! parameter is a logical OR combination of values \b UART_FLOWCONTROL_TX and +//! \b UART_FLOWCONTROL_RX to enable hardware transmit (CTS) and receive (RTS) +//! flow control or \b UART_FLOWCONTROL_NONE to disable hardware flow control. +//! +//! This function configures the required hardware flow control modes. If +//! \e ui32Mode contains flag \b UART_FLOWCONTROL_TX, data is only transmitted +//! if the incoming CTS signal is asserted. If \e ui32Mode contains flag +//! \b UART_FLOWCONTROL_RX, the RTS output is controlled by the hardware and is +//! asserted only when there is space available in the receive FIFO. If no +//! hardware flow control is required, \b UART_FLOWCONTROL_NONE should be +//! passed. +//! +//! \note The availability of hardware flow control varies with the Tiva +//! part and UART in use. Please consult the datasheet for the part you are +//! using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UARTFlowControlSet(uint32_t ui32Base, uint32_t ui32Mode) +{ + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + ASSERT((ui32Mode & ~(UART_FLOWCONTROL_TX | UART_FLOWCONTROL_RX)) == 0); + + // + // Set the flow control mode as requested. + // + HWREG(ui32Base + UART_O_CTL) = ((HWREG(ui32Base + UART_O_CTL) & + ~(UART_FLOWCONTROL_TX | + UART_FLOWCONTROL_RX)) | ui32Mode); +} + +//***************************************************************************** +// +//! Returns the UART hardware flow control mode currently in use. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function returns the current hardware flow control mode. +//! +//! \note The availability of hardware flow control varies with the Tiva +//! part and UART in use. Please consult the datasheet for the part you are +//! using to determine whether this support is available. +//! +//! \return Returns the current flow control mode in use. This value is a +//! logical OR combination of values \b UART_FLOWCONTROL_TX if transmit +//! (CTS) flow control is enabled and \b UART_FLOWCONTROL_RX if receive (RTS) +//! flow control is in use. If hardware flow control is disabled, +//! \b UART_FLOWCONTROL_NONE is returned. +// +//***************************************************************************** +uint32_t +UARTFlowControlGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + + return(HWREG(ui32Base + UART_O_CTL) & (UART_FLOWCONTROL_TX | + UART_FLOWCONTROL_RX)); +} + +//***************************************************************************** +// +//! Sets the operating mode for the UART transmit interrupt. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32Mode is the operating mode for the transmit interrupt. It may +//! be \b UART_TXINT_MODE_EOT to trigger interrupts when the transmitter is +//! idle or \b UART_TXINT_MODE_FIFO to trigger based on the current transmit +//! FIFO level. +//! +//! This function allows the mode of the UART transmit interrupt to be set. By +//! default, the transmit interrupt is asserted when the FIFO level falls past +//! a threshold set via a call to UARTFIFOLevelSet(). Alternatively, if this +//! function is called with \e ui32Mode set to \b UART_TXINT_MODE_EOT, the +//! transmit interrupt is asserted once the transmitter is completely idle - +//! the transmit FIFO is empty and all bits, including any stop bits, have +//! cleared the transmitter. +//! +//! \note The availability of end-of-transmission mode varies with the +//! Tiva part in use. Please consult the datasheet for the part you are +//! using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UARTTxIntModeSet(uint32_t ui32Base, uint32_t ui32Mode) +{ + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + ASSERT((ui32Mode == UART_TXINT_MODE_EOT) || + (ui32Mode == UART_TXINT_MODE_FIFO)); + + // + // Set or clear the EOT bit of the UART control register as appropriate. + // + HWREG(ui32Base + UART_O_CTL) = ((HWREG(ui32Base + UART_O_CTL) & + ~(UART_TXINT_MODE_EOT | + UART_TXINT_MODE_FIFO)) | ui32Mode); +} + +//***************************************************************************** +// +//! Returns the current operating mode for the UART transmit interrupt. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function returns the current operating mode for the UART transmit +//! interrupt. The return value is \b UART_TXINT_MODE_EOT if the transmit +//! interrupt is currently configured to be asserted once the transmitter is +//! completely idle - the transmit FIFO is empty and all bits, including any +//! stop bits, have cleared the transmitter. The return value is +//! \b UART_TXINT_MODE_FIFO if the interrupt is configured to be asserted based +//! on the level of the transmit FIFO. +//! +//! \note The availability of end-of-transmission mode varies with the +//! Tiva part in use. Please consult the datasheet for the part you are +//! using to determine whether this support is available. +//! +//! \return Returns \b UART_TXINT_MODE_FIFO or \b UART_TXINT_MODE_EOT. +// +//***************************************************************************** +uint32_t +UARTTxIntModeGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + + // + // Return the current transmit interrupt mode. + // + return(HWREG(ui32Base + UART_O_CTL) & (UART_TXINT_MODE_EOT | + UART_TXINT_MODE_FIFO)); +} + +//***************************************************************************** +// +//! Determines if there are any characters in the receive FIFO. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function returns a flag indicating whether or not there is data +//! available in the receive FIFO. +//! +//! \return Returns \b true if there is data in the receive FIFO or \b false +//! if there is no data in the receive FIFO. +// +//***************************************************************************** +bool +UARTCharsAvail(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + + // + // Return the availability of characters. + // + return((HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE) ? false : true); +} + +//***************************************************************************** +// +//! Determines if there is any space in the transmit FIFO. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function returns a flag indicating whether or not there is space +//! available in the transmit FIFO. +//! +//! \return Returns \b true if there is space available in the transmit FIFO +//! or \b false if there is no space available in the transmit FIFO. +// +//***************************************************************************** +bool +UARTSpaceAvail(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + + // + // Return the availability of space. + // + return((HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF) ? false : true); +} + +//***************************************************************************** +// +//! Receives a character from the specified port. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function gets a character from the receive FIFO for the specified +//! port. +//! +//! \return Returns the character read from the specified port, cast as a +//! \e int32_t. A \b -1 is returned if there are no characters present in the +//! receive FIFO. The UARTCharsAvail() function should be called before +//! attempting to call this function. +// +//***************************************************************************** +int32_t +UARTCharGetNonBlocking(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + + // + // See if there are any characters in the receive FIFO. + // + if(!(HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE)) + { + // + // Read and return the next character. + // + return(HWREG(ui32Base + UART_O_DR)); + } + else + { + // + // There are no characters, so return a failure. + // + return(-1); + } +} + +//***************************************************************************** +// +//! Waits for a character from the specified port. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function gets a character from the receive FIFO for the specified +//! port. If there are no characters available, this function waits until a +//! character is received before returning. +//! +//! \return Returns the character read from the specified port, cast as a +//! \e int32_t. +// +//***************************************************************************** +int32_t +UARTCharGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + + // + // Wait until a char is available. + // + while(HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE) + { + } + + // + // Now get the char. + // + return(HWREG(ui32Base + UART_O_DR)); +} + +//***************************************************************************** +// +//! Sends a character to the specified port. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ucData is the character to be transmitted. +//! +//! This function writes the character \e ucData to the transmit FIFO for the +//! specified port. This function does not block, so if there is no space +//! available, then a \b false is returned and the application must retry the +//! function later. +//! +//! \return Returns \b true if the character was successfully placed in the +//! transmit FIFO or \b false if there was no space available in the transmit +//! FIFO. +// +//***************************************************************************** +bool +UARTCharPutNonBlocking(uint32_t ui32Base, unsigned char ucData) +{ + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + + // + // See if there is space in the transmit FIFO. + // + if(!(HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF)) + { + // + // Write this character to the transmit FIFO. + // + HWREG(ui32Base + UART_O_DR) = ucData; + + // + // Success. + // + return(true); + } + else + { + // + // There is no space in the transmit FIFO, so return a failure. + // + return(false); + } +} + +//***************************************************************************** +// +//! Waits to send a character from the specified port. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ucData is the character to be transmitted. +//! +//! This function sends the character \e ucData to the transmit FIFO for the +//! specified port. If there is no space available in the transmit FIFO, this +//! function waits until there is space available before returning. +//! +//! \return None. +// +//***************************************************************************** +void +UARTCharPut(uint32_t ui32Base, unsigned char ucData) +{ + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + + // + // Wait until space is available. + // + while(HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF) + { + } + // + // Send the char. + // + HWREG(ui32Base + UART_O_DR) = ucData; +} + +//***************************************************************************** +// +//! Causes a BREAK to be sent. +//! +//! \param ui32Base is the base address of the UART port. +//! \param bBreakState controls the output level. +//! +//! Calling this function with \e bBreakState set to \b true asserts a break +//! condition on the UART. Calling this function with \e bBreakState set to +//! \b false removes the break condition. For proper transmission of a break +//! command, the break must be asserted for at least two complete frames. +//! +//! \return None. +// +//***************************************************************************** +void +UARTBreakCtl(uint32_t ui32Base, bool bBreakState) +{ + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + + // + // Set the break condition as requested. + // + HWREG(ui32Base + UART_O_LCRH) = + (bBreakState ? + (HWREG(ui32Base + UART_O_LCRH) | UART_LCRH_BRK) : + (HWREG(ui32Base + UART_O_LCRH) & ~(UART_LCRH_BRK))); +} + +//***************************************************************************** +// +//! Determines whether the UART transmitter is busy or not. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function allows the caller to determine whether all transmitted bytes +//! have cleared the transmitter hardware. If \b false is returned, the +//! transmit FIFO is empty and all bits of the last transmitted character, +//! including all stop bits, have left the hardware shift register. +//! +//! \return Returns \b true if the UART is transmitting or \b false if all +//! transmissions are complete. +// +//***************************************************************************** +bool +UARTBusy(uint32_t ui32Base) +{ + // + // Check the argument. + // + ASSERT(_UARTBaseValid(ui32Base)); + + // + // Determine if the UART is busy. + // + return((HWREG(ui32Base + UART_O_FR) & UART_FR_BUSY) ? true : false); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for a UART interrupt. +//! +//! \param ui32Base is the base address of the UART port. +//! \param pfnHandler is a pointer to the function to be called when the +//! UART interrupt occurs. +//! +//! This function does the actual registering of the interrupt handler. This +//! function enables the global interrupt in the interrupt controller; specific +//! UART interrupts must be enabled via UARTIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +UARTIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + + // + // Determine the interrupt number based on the UART port. + // + ui32Int = _UARTIntNumberGet(ui32Base); + + ASSERT(ui32Int != 0); + + // + // Register the interrupt handler. + // + IntRegister(ui32Int, pfnHandler); + + // + // Enable the UART interrupt. + // + IntEnable(ui32Int); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for a UART interrupt. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! clears the handler to be called when a UART interrupt occurs. This +//! function also masks off the interrupt in the interrupt controller so that +//! the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +UARTIntUnregister(uint32_t ui32Base) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + + // + // Determine the interrupt number based on the UART port. + // + ui32Int = _UARTIntNumberGet(ui32Base); + + ASSERT(ui32Int != 0); + + // + // Disable the interrupt. + // + IntDisable(ui32Int); + + // + // Unregister the interrupt handler. + // + IntUnregister(ui32Int); +} + +//***************************************************************************** +// +//! Enables individual UART interrupt sources. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated UART interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ui32IntFlags parameter is the logical OR of any of the following: +//! +//! - \b UART_INT_9BIT - 9-bit Address Match interrupt +//! - \b UART_INT_OE - Overrun Error interrupt +//! - \b UART_INT_BE - Break Error interrupt +//! - \b UART_INT_PE - Parity Error interrupt +//! - \b UART_INT_FE - Framing Error interrupt +//! - \b UART_INT_RT - Receive Timeout interrupt +//! - \b UART_INT_TX - Transmit interrupt +//! - \b UART_INT_RX - Receive interrupt +//! - \b UART_INT_DSR - DSR interrupt +//! - \b UART_INT_DCD - DCD interrupt +//! - \b UART_INT_CTS - CTS interrupt +//! - \b UART_INT_RI - RI interrupt +//! +//! \return None. +// +//***************************************************************************** +void +UARTIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + + // + // Enable the specified interrupts. + // + HWREG(ui32Base + UART_O_IM) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! Disables individual UART interrupt sources. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be +//! disabled. +//! +//! This function disables the indicated UART interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ui32IntFlags parameter has the same definition as the +//! \e ui32IntFlags parameter to UARTIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +UARTIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + + // + // Disable the specified interrupts. + // + HWREG(ui32Base + UART_O_IM) &= ~(ui32IntFlags); +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ui32Base is the base address of the UART port. +//! \param bMasked is \b false if the raw interrupt status is required and +//! \b true if the masked interrupt status is required. +//! +//! This function returns the interrupt status for the specified UART. Either +//! the raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of +//! values described in UARTIntEnable(). +// +//***************************************************************************** +uint32_t +UARTIntStatus(uint32_t ui32Base, bool bMasked) +{ + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ui32Base + UART_O_MIS)); + } + else + { + return(HWREG(ui32Base + UART_O_RIS)); + } +} + +//***************************************************************************** +// +//! Clears UART interrupt sources. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified UART interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being triggered again immediately upon exit. +//! +//! The \e ui32IntFlags parameter has the same definition as the +//! \e ui32IntFlags parameter to UARTIntEnable(). +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +UARTIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + + // + // Clear the requested interrupt sources. + // + HWREG(ui32Base + UART_O_ICR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! Enable UART uDMA operation. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32DMAFlags is a bit mask of the uDMA features to enable. +//! +//! The specified UART uDMA features are enabled. The UART can be +//! configured to use uDMA for transmit or receive and to disable +//! receive if an error occurs. The \e ui32DMAFlags parameter is the +//! logical OR of any of the following values: +//! +//! - \b UART_DMA_RX - enable uDMA for receive +//! - \b UART_DMA_TX - enable uDMA for transmit +//! - \b UART_DMA_ERR_RXSTOP - disable uDMA receive on UART error +//! +//! \note The uDMA controller must also be set up before DMA can be used +//! with the UART. +//! +//! \return None. +// +//***************************************************************************** +void +UARTDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags) +{ + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + + // + // Set the requested bits in the UART uDMA control register. + // + HWREG(ui32Base + UART_O_DMACTL) |= ui32DMAFlags; +} + +//***************************************************************************** +// +//! Disable UART uDMA operation. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32DMAFlags is a bit mask of the uDMA features to disable. +//! +//! This function is used to disable UART uDMA features that were enabled +//! by UARTDMAEnable(). The specified UART uDMA features are disabled. The +//! \e ui32DMAFlags parameter is the logical OR of any of the following values: +//! +//! - \b UART_DMA_RX - disable uDMA for receive +//! - \b UART_DMA_TX - disable uDMA for transmit +//! - \b UART_DMA_ERR_RXSTOP - do not disable uDMA receive on UART error +//! +//! \return None. +// +//***************************************************************************** +void +UARTDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags) +{ + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + + // + // Clear the requested bits in the UART uDMA control register. + // + HWREG(ui32Base + UART_O_DMACTL) &= ~ui32DMAFlags; +} + +//***************************************************************************** +// +//! Gets current receiver errors. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function returns the current state of each of the 4 receiver error +//! sources. The returned errors are equivalent to the four error bits +//! returned via the previous call to UARTCharGet() or UARTCharGetNonBlocking() +//! with the exception that the overrun error is set immediately when the +//! overrun occurs rather than when a character is next read. +//! +//! \return Returns a logical OR combination of the receiver error flags, +//! \b UART_RXERROR_FRAMING, \b UART_RXERROR_PARITY, \b UART_RXERROR_BREAK +//! and \b UART_RXERROR_OVERRUN. +// +//***************************************************************************** +uint32_t +UARTRxErrorGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + + // + // Return the current value of the receive status register. + // + return(HWREG(ui32Base + UART_O_RSR) & 0x0000000F); +} + +//***************************************************************************** +// +//! Clears all reported receiver errors. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function is used to clear all receiver error conditions reported via +//! UARTRxErrorGet(). If using the overrun, framing error, parity error or +//! break interrupts, this function must be called after clearing the interrupt +//! to ensure that later errors of the same type trigger another interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +UARTRxErrorClear(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + + // + // Any write to the Error Clear Register clears all bits which are + // currently set. + // + HWREG(ui32Base + UART_O_ECR) = 0; +} + +//***************************************************************************** +// +//! Sets the baud clock source for the specified UART. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32Source is the baud clock source for the UART. +//! +//! This function allows the baud clock source for the UART to be selected. +//! The possible clock source are the system clock (\b UART_CLOCK_SYSTEM) or +//! the precision internal oscillator (\b UART_CLOCK_PIOSC). +//! +//! Changing the baud clock source changes the baud rate generated by the +//! UART. Therefore, the baud rate should be reconfigured after any change to +//! the baud clock source. +//! +//! \note The ability to specify the UART baud clock source varies with the +//! Tiva part in use. Please consult the datasheet for the part you are +//! using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UARTClockSourceSet(uint32_t ui32Base, uint32_t ui32Source) +{ + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + ASSERT((ui32Source == UART_CLOCK_SYSTEM) || + (ui32Source == UART_CLOCK_PIOSC)); + + // + // Set the UART clock source. + // + HWREG(ui32Base + UART_O_CC) = ui32Source; +} + +//***************************************************************************** +// +//! Gets the baud clock source for the specified UART. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function returns the baud clock source for the specified UART. The +//! possible baud clock source are the system clock (\b UART_CLOCK_SYSTEM) or +//! the precision internal oscillator (\b UART_CLOCK_PIOSC). +//! +//! \note The ability to specify the UART baud clock source varies with the +//! Tiva part in use. Please consult the datasheet for the part you are +//! using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +uint32_t +UARTClockSourceGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + + // + // Return the UART clock source. + // + return(HWREG(ui32Base + UART_O_CC)); +} + +//***************************************************************************** +// +//! Enables 9-bit mode on the specified UART. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function enables the 9-bit operational mode of the UART. +//! +//! \note The availability of 9-bit mode varies with the Tiva part in use. +//! Please consult the datasheet for the part you are using to determine +//! whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UART9BitEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + + // + // Enable 9-bit mode. + // + HWREG(ui32Base + UART_O_9BITADDR) |= UART_9BITADDR_9BITEN; +} + +//***************************************************************************** +// +//! Disables 9-bit mode on the specified UART. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function disables the 9-bit operational mode of the UART. +//! +//! \note The availability of 9-bit mode varies with the Tiva part in use. +//! Please consult the datasheet for the part you are using to determine +//! whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UART9BitDisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + + // + // Disable 9-bit mode. + // + HWREG(ui32Base + UART_O_9BITADDR) &= ~UART_9BITADDR_9BITEN; +} + +//***************************************************************************** +// +//! Sets the device address(es) for 9-bit mode. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui8Addr is the device address. +//! \param ui8Mask is the device address mask. +//! +//! This function configures the device address or range of device addresses +//! that respond to requests on the 9-bit UART port. The received address is +//! masked with the mask and then compared against the given address, allowing +//! either a single address (if \b ui8Mask is 0xff) or a set of addresses to be +//! matched. +//! +//! \note The availability of 9-bit mode varies with the Tiva part in use. +//! Please consult the datasheet for the part you are using to determine +//! whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UART9BitAddrSet(uint32_t ui32Base, uint8_t ui8Addr, + uint8_t ui8Mask) +{ + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + + // + // Set the address and mask. + // + HWREG(ui32Base + UART_O_9BITADDR) = ui8Addr << UART_9BITADDR_ADDR_S; + HWREG(ui32Base + UART_O_9BITAMASK) = ui8Mask << UART_9BITAMASK_MASK_S; +} + +//***************************************************************************** +// +//! Sends an address character from the specified port when operating in 9-bit +//! mode. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui8Addr is the address to be transmitted. +//! +//! This function waits until all data has been sent from the specified port +//! and then sends the given address as an address byte. It then waits until +//! the address byte has been transmitted before returning. +//! +//! The normal data functions (UARTCharPut(), UARTCharPutNonBlocking(), +//! UARTCharGet(), and UARTCharGetNonBlocking()) are used to send and receive +//! data characters in 9-bit mode. +//! +//! \note The availability of 9-bit mode varies with the Tiva part in use. +//! Please consult the datasheet for the part you are using to determine +//! whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UART9BitAddrSend(uint32_t ui32Base, uint8_t ui8Addr) +{ + uint32_t ui32LCRH; + + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + + // + // Wait until the FIFO is empty and the UART is not busy. + // + while((HWREG(ui32Base + UART_O_FR) & (UART_FR_TXFE | UART_FR_BUSY)) != + UART_FR_TXFE) + { + } + + // + // Force the address/data bit to 1 to indicate this is an address byte. + // + ui32LCRH = HWREG(ui32Base + UART_O_LCRH); + HWREG(ui32Base + UART_O_LCRH) = ((ui32LCRH & ~UART_LCRH_EPS) | + UART_LCRH_SPS | UART_LCRH_PEN); + + // + // Send the address. + // + HWREG(ui32Base + UART_O_DR) = ui8Addr; + + // + // Wait until the address has been sent. + // + while((HWREG(ui32Base + UART_O_FR) & (UART_FR_TXFE | UART_FR_BUSY)) != + UART_FR_TXFE) + { + } + + // + // Restore the address/data setting. + // + HWREG(ui32Base + UART_O_LCRH) = ui32LCRH; +} + +//***************************************************************************** +// +//! Enables internal loopback mode for a UART port +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function configures a UART port in internal loopback mode to help with +//! diagnostics and debug. In this mode, the transmit and receive terminals of +//! the same UART port are internally connected. Hence, the data transmitted +//! on the UnTx output is received on the UxRx input, without having to go +//! through I/O's. UARTCharPut(), UARTCharGet() functions can be used along +//! with this function. +//! +//! \return None. +// +//***************************************************************************** +void UARTLoopbackEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + + // + // Write the Loopback Enable bit to register. + // + HWREG(ui32Base + UART_O_CTL) |= UART_CTL_LBE; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/udma.c b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/udma.c new file mode 100644 index 0000000000000000000000000000000000000000..bb2941af92eaa46facbf0c4e28aa68f2adedfeb0 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/udma.c @@ -0,0 +1,1382 @@ +//***************************************************************************** +// +// udma.c - Driver for the micro-DMA controller. +// +// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup udma_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" +#include "inc/hw_udma.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/udma.h" + +//***************************************************************************** +// +//! Enables the uDMA controller for use. +//! +//! This function enables the uDMA controller. The uDMA controller must be +//! enabled before it can be configured and used. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAEnable(void) +{ + // + // Set the master enable bit in the config register. + // + HWREG(UDMA_CFG) = UDMA_CFG_MASTEN; +} + +//***************************************************************************** +// +//! Disables the uDMA controller for use. +//! +//! This function disables the uDMA controller. Once disabled, the uDMA +//! controller cannot operate until re-enabled with uDMAEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +uDMADisable(void) +{ + // + // Clear the master enable bit in the config register. + // + HWREG(UDMA_CFG) = 0; +} + +//***************************************************************************** +// +//! Gets the uDMA error status. +//! +//! This function returns the uDMA error status. It should be called from +//! within the uDMA error interrupt handler to determine if a uDMA error +//! occurred. +//! +//! \return Returns non-zero if a uDMA error is pending. +// +//***************************************************************************** +uint32_t +uDMAErrorStatusGet(void) +{ + // + // Return the uDMA error status. + // + return(HWREG(UDMA_ERRCLR)); +} + +//***************************************************************************** +// +//! Clears the uDMA error interrupt. +//! +//! This function clears a pending uDMA error interrupt. This function should +//! be called from within the uDMA error interrupt handler to clear the +//! interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAErrorStatusClear(void) +{ + // + // Clear the uDMA error interrupt. + // + HWREG(UDMA_ERRCLR) = 1; +} + +//***************************************************************************** +// +//! Enables a uDMA channel for operation. +//! +//! \param ui32ChannelNum is the channel number to enable. +//! +//! This function enables a specific uDMA channel for use. This function must +//! be used to enable a channel before it can be used to perform a uDMA +//! transfer. +//! +//! When a uDMA transfer is completed, the channel is automatically disabled by +//! the uDMA controller. Therefore, this function should be called prior to +//! starting up any new transfer. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelEnable(uint32_t ui32ChannelNum) +{ + // + // Check the arguments. + // + ASSERT((ui32ChannelNum & 0xffff) < 32); + + // + // Set the bit for this channel in the enable set register. + // + HWREG(UDMA_ENASET) = 1 << (ui32ChannelNum & 0x1f); +} + +//***************************************************************************** +// +//! Disables a uDMA channel for operation. +//! +//! \param ui32ChannelNum is the channel number to disable. +//! +//! This function disables a specific uDMA channel. Once disabled, a channel +//! cannot respond to uDMA transfer requests until re-enabled via +//! uDMAChannelEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelDisable(uint32_t ui32ChannelNum) +{ + // + // Check the arguments. + // + ASSERT((ui32ChannelNum & 0xffff) < 32); + + // + // Set the bit for this channel in the enable clear register. + // + HWREG(UDMA_ENACLR) = 1 << (ui32ChannelNum & 0x1f); +} + +//***************************************************************************** +// +//! Checks if a uDMA channel is enabled for operation. +//! +//! \param ui32ChannelNum is the channel number to check. +//! +//! This function checks to see if a specific uDMA channel is enabled. This +//! function can be used to check the status of a transfer, as the channel is +//! automatically disabled at the end of a transfer. +//! +//! \return Returns \b true if the channel is enabled, \b false if disabled. +// +//***************************************************************************** +bool +uDMAChannelIsEnabled(uint32_t ui32ChannelNum) +{ + // + // Check the arguments. + // + ASSERT((ui32ChannelNum & 0xffff) < 32); + + // + // AND the specified channel bit with the enable register and return the + // result. + // + return((HWREG(UDMA_ENASET) & (1 << (ui32ChannelNum & 0x1f))) ? true : + false); +} + +//***************************************************************************** +// +//! Sets the base address for the channel control table. +//! +//! \param psControlTable is a pointer to the 1024-byte-aligned base address +//! of the uDMA channel control table. +//! +//! This function configures the base address of the channel control table. +//! This table resides in system memory and holds control information for each +//! uDMA channel. The table must be aligned on a 1024-byte boundary. The base +//! address must be configured before any of the channel functions can be used. +//! +//! The size of the channel control table depends on the number of uDMA +//! channels and the transfer modes that are used. Refer to the introductory +//! text and the microcontroller datasheet for more information about the +//! channel control table. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAControlBaseSet(void *psControlTable) +{ + // + // Check the arguments. + // + ASSERT(((uint32_t)psControlTable & ~0x3FF) == + (uint32_t)psControlTable); + ASSERT((uint32_t)psControlTable >= 0x20000000); + + // + // Program the base address into the register. + // + HWREG(UDMA_CTLBASE) = (uint32_t)psControlTable; +} + +//***************************************************************************** +// +//! Gets the base address for the channel control table. +//! +//! This function gets the base address of the channel control table. This +//! table resides in system memory and holds control information for each uDMA +//! channel. +//! +//! \return Returns a pointer to the base address of the channel control table. +// +//***************************************************************************** +void * +uDMAControlBaseGet(void) +{ + // + // Read the current value of the control base register and return it to + // the caller. + // + return((void *)HWREG(UDMA_CTLBASE)); +} + +//***************************************************************************** +// +//! Gets the base address for the channel control table alternate structures. +//! +//! This function gets the base address of the second half of the channel +//! control table that holds the alternate control structures for each channel. +//! +//! \return Returns a pointer to the base address of the second half of the +//! channel control table. +// +//***************************************************************************** +void * +uDMAControlAlternateBaseGet(void) +{ + // + // Read the current value of the control base register and return it to + // the caller. + // + return((void *)HWREG(UDMA_ALTBASE)); +} + +//***************************************************************************** +// +//! Requests a uDMA channel to start a transfer. +//! +//! \param ui32ChannelNum is the channel number on which to request a uDMA +//! transfer. +//! +//! This function allows software to request a uDMA channel to begin a +//! transfer. This function could be used for performing a memory-to-memory +//! transfer, or if for some reason a transfer needs to be initiated by +//! software instead of the peripheral associated with that channel. +//! +//! \note If the channel is \b UDMA_CHANNEL_SW and interrupts are used, then +//! the completion is signaled on the uDMA dedicated interrupt. If a +//! peripheral channel is used, then the completion is signaled on the +//! peripheral's interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelRequest(uint32_t ui32ChannelNum) +{ + // + // Check the arguments. + // + ASSERT((ui32ChannelNum & 0xffff) < 32); + + // + // Set the bit for this channel in the software uDMA request register. + // + HWREG(UDMA_SWREQ) = 1 << (ui32ChannelNum & 0x1f); +} + +//***************************************************************************** +// +//! Enables attributes of a uDMA channel. +//! +//! \param ui32ChannelNum is the channel to configure. +//! \param ui32Attr is a combination of attributes for the channel. +//! +//! This function is used to enable attributes of a uDMA channel. +//! +//! The \e ui32Attr parameter is the logical OR of any of the following: +//! +//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst +//! mode. +//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure +//! for this channel (it is very unlikely that this flag should be used). +//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. +//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the +//! peripheral for this channel. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelAttributeEnable(uint32_t ui32ChannelNum, uint32_t ui32Attr) +{ + // + // Check the arguments. + // + ASSERT((ui32ChannelNum & 0xffff) < 32); + ASSERT((ui32Attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | + UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); + + // + // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was + // passed as the ui32ChannelNum parameter, extract just the channel number + // from this parameter. + // + ui32ChannelNum &= 0x1f; + + // + // Set the useburst bit for this channel if set in ui32Config. + // + if(ui32Attr & UDMA_ATTR_USEBURST) + { + HWREG(UDMA_USEBURSTSET) = 1 << ui32ChannelNum; + } + + // + // Set the alternate control select bit for this channel, + // if set in ui32Config. + // + if(ui32Attr & UDMA_ATTR_ALTSELECT) + { + HWREG(UDMA_ALTSET) = 1 << ui32ChannelNum; + } + + // + // Set the high priority bit for this channel, if set in ui32Config. + // + if(ui32Attr & UDMA_ATTR_HIGH_PRIORITY) + { + HWREG(UDMA_PRIOSET) = 1 << ui32ChannelNum; + } + + // + // Set the request mask bit for this channel, if set in ui32Config. + // + if(ui32Attr & UDMA_ATTR_REQMASK) + { + HWREG(UDMA_REQMASKSET) = 1 << ui32ChannelNum; + } +} + +//***************************************************************************** +// +//! Disables attributes of a uDMA channel. +//! +//! \param ui32ChannelNum is the channel to configure. +//! \param ui32Attr is a combination of attributes for the channel. +//! +//! This function is used to disable attributes of a uDMA channel. +//! +//! The \e ui32Attr parameter is the logical OR of any of the following: +//! +//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst +//! mode. +//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure +//! for this channel. +//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. +//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the +//! peripheral for this channel. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelAttributeDisable(uint32_t ui32ChannelNum, uint32_t ui32Attr) +{ + // + // Check the arguments. + // + ASSERT((ui32ChannelNum & 0xffff) < 32); + ASSERT((ui32Attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | + UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); + + // + // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was + // passed as the ui32ChannelNum parameter, extract just the channel number + // from this parameter. + // + ui32ChannelNum &= 0x1f; + + // + // Clear the useburst bit for this channel if set in ui32Config. + // + if(ui32Attr & UDMA_ATTR_USEBURST) + { + HWREG(UDMA_USEBURSTCLR) = 1 << ui32ChannelNum; + } + + // + // Clear the alternate control select bit for this channel, if set in + // ui32Config. + // + if(ui32Attr & UDMA_ATTR_ALTSELECT) + { + HWREG(UDMA_ALTCLR) = 1 << ui32ChannelNum; + } + + // + // Clear the high priority bit for this channel, if set in ui32Config. + // + if(ui32Attr & UDMA_ATTR_HIGH_PRIORITY) + { + HWREG(UDMA_PRIOCLR) = 1 << ui32ChannelNum; + } + + // + // Clear the request mask bit for this channel, if set in ui32Config. + // + if(ui32Attr & UDMA_ATTR_REQMASK) + { + HWREG(UDMA_REQMASKCLR) = 1 << ui32ChannelNum; + } +} + +//***************************************************************************** +// +//! Gets the enabled attributes of a uDMA channel. +//! +//! \param ui32ChannelNum is the channel to configure. +//! +//! This function returns a combination of flags representing the attributes of +//! the uDMA channel. +//! +//! \return Returns the logical OR of the attributes of the uDMA channel, which +//! can be any of the following: +//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst +//! mode. +//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure +//! for this channel. +//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. +//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the +//! peripheral for this channel. +// +//***************************************************************************** +uint32_t +uDMAChannelAttributeGet(uint32_t ui32ChannelNum) +{ + uint32_t ui32Attr = 0; + + // + // Check the arguments. + // + ASSERT((ui32ChannelNum & 0xffff) < 32); + + // + // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was + // passed as the ui32ChannelNum parameter, extract just the channel number + // from this parameter. + // + ui32ChannelNum &= 0x1f; + + // + // Check to see if useburst bit is set for this channel. + // + if(HWREG(UDMA_USEBURSTSET) & (1 << ui32ChannelNum)) + { + ui32Attr |= UDMA_ATTR_USEBURST; + } + + // + // Check to see if the alternate control bit is set for this channel. + // + if(HWREG(UDMA_ALTSET) & (1 << ui32ChannelNum)) + { + ui32Attr |= UDMA_ATTR_ALTSELECT; + } + + // + // Check to see if the high priority bit is set for this channel. + // + if(HWREG(UDMA_PRIOSET) & (1 << ui32ChannelNum)) + { + ui32Attr |= UDMA_ATTR_HIGH_PRIORITY; + } + + // + // Check to see if the request mask bit is set for this channel. + // + if(HWREG(UDMA_REQMASKSET) & (1 << ui32ChannelNum)) + { + ui32Attr |= UDMA_ATTR_REQMASK; + } + + // + // Return the configuration flags. + // + return(ui32Attr); +} + +//***************************************************************************** +// +//! Sets the control parameters for a uDMA channel control structure. +//! +//! \param ui32ChannelStructIndex is the logical OR of the uDMA channel number +//! with \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. +//! \param ui32Control is logical OR of several control values to set the +//! control parameters for the channel. +//! +//! This function is used to set control parameters for a uDMA transfer. These +//! parameters are typically not changed often. +//! +//! The \e ui32ChannelStructIndex parameter should be the logical OR of the +//! channel number with one of \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to +//! choose whether the primary or alternate data structure is used. +//! +//! The \e ui32Control parameter is the logical OR of five values: the data +//! size, the source address increment, the destination address increment, the +//! arbitration size, and the use burst flag. The choices available for each +//! of these values is described below. +//! +//! Choose the data size from one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or +//! \b UDMA_SIZE_32 to select a data size of 8, 16, or 32 bits. +//! +//! Choose the source address increment from one of \b UDMA_SRC_INC_8, +//! \b UDMA_SRC_INC_16, \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE to select +//! an address increment of 8-bit bytes, 16-bit half-words, 32-bit words, or +//! to select non-incrementing. +//! +//! Choose the destination address increment from one of \b UDMA_DST_INC_8, +//! \b UDMA_DST_INC_16, \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE to select +//! an address increment of 8-bit bytes, 16-bit half-words, 32-bit words, or +//! to select non-incrementing. +//! +//! The arbitration size determines how many items are transferred before +//! the uDMA controller re-arbitrates for the bus. Choose the arbitration size +//! from one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, \b UDMA_ARB_8, +//! through \b UDMA_ARB_1024 to select the arbitration size from 1 to 1024 +//! items, in powers of 2. +//! +//! The value \b UDMA_NEXT_USEBURST is used to force the channel to only +//! respond to burst requests at the tail end of a scatter-gather transfer. +//! +//! \note The address increment cannot be smaller than the data size. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelControlSet(uint32_t ui32ChannelStructIndex, uint32_t ui32Control) +{ + tDMAControlTable *psCtl; + + // + // Check the arguments. + // + ASSERT((ui32ChannelStructIndex & 0xffff) < 64); + ASSERT(HWREG(UDMA_CTLBASE) != 0); + + // + // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was + // passed as the ui32ChannelStructIndex parameter, extract just the channel + // index from this parameter. + // + ui32ChannelStructIndex &= 0x3f; + + // + // Get the base address of the control table. + // + psCtl = (tDMAControlTable *)HWREG(UDMA_CTLBASE); + + // + // Get the current control word value and mask off the fields to be + // changed, then OR in the new settings. + // + psCtl[ui32ChannelStructIndex].ui32Control = + ((psCtl[ui32ChannelStructIndex].ui32Control & + ~(UDMA_CHCTL_DSTINC_M | + UDMA_CHCTL_DSTSIZE_M | + UDMA_CHCTL_SRCINC_M | + UDMA_CHCTL_SRCSIZE_M | + UDMA_CHCTL_ARBSIZE_M | + UDMA_CHCTL_NXTUSEBURST)) | + ui32Control); +} + +//***************************************************************************** +// +//! Sets the transfer parameters for a uDMA channel control structure. +//! +//! \param ui32ChannelStructIndex is the logical OR of the uDMA channel number +//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. +//! \param ui32Mode is the type of uDMA transfer. +//! \param pvSrcAddr is the source address for the transfer. +//! \param pvDstAddr is the destination address for the transfer. +//! \param ui32TransferSize is the number of data items to transfer. +//! +//! This function is used to configure the parameters for a uDMA transfer. +//! These parameters are not typically changed often. The function +//! uDMAChannelControlSet() MUST be called at least once for this channel prior +//! to calling this function. +//! +//! The \e ui32ChannelStructIndex parameter should be the logical OR of the +//! channel number with one of \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to +//! choose whether the primary or alternate data structure is used. +//! +//! The \e ui32Mode parameter should be one of the following values: +//! +//! - \b UDMA_MODE_STOP stops the uDMA transfer. The controller sets the mode +//! to this value at the end of a transfer. +//! - \b UDMA_MODE_BASIC to perform a basic transfer based on request. +//! - \b UDMA_MODE_AUTO to perform a transfer that always completes once +//! started even if the request is removed. +//! - \b UDMA_MODE_PINGPONG to set up a transfer that switches between the +//! primary and alternate control structures for the channel. This mode +//! allows use of ping-pong buffering for uDMA transfers. +//! - \b UDMA_MODE_MEM_SCATTER_GATHER to set up a memory scatter-gather +//! transfer. +//! - \b UDMA_MODE_PER_SCATTER_GATHER to set up a peripheral scatter-gather +//! transfer. +//! +//! The \e pvSrcAddr and \e pvDstAddr parameters are pointers to the first +//! location of the data to be transferred. These addresses should be aligned +//! according to the item size. The compiler takes care of this alignment if +//! the pointers are pointing to storage of the appropriate data type. +//! +//! The \e ui32TransferSize parameter is the number of data items, not the +//! number of bytes. +//! +//! The two scatter-gather modes, memory and peripheral, are actually different +//! depending on whether the primary or alternate control structure is +//! selected. This function looks for the \b UDMA_PRI_SELECT and +//! \b UDMA_ALT_SELECT flag along with the channel number and sets the +//! scatter-gather mode as appropriate for the primary or alternate control +//! structure. +//! +//! The channel must also be enabled using uDMAChannelEnable() after calling +//! this function. The transfer does not begin until the channel has been +//! configured and enabled. Note that the channel is automatically disabled +//! after the transfer is completed, meaning that uDMAChannelEnable() must be +//! called again after setting up the next transfer. +//! +//! \note Great care must be taken to not modify a channel control structure +//! that is in use or else the results are unpredictable, including the +//! possibility of undesired data transfers to or from memory or peripherals. +//! For BASIC and AUTO modes, it is safe to make changes when the channel is +//! disabled, or the uDMAChannelModeGet() returns \b UDMA_MODE_STOP. For +//! PINGPONG or one of the SCATTER_GATHER modes, it is safe to modify the +//! primary or alternate control structure only when the other is being used. +//! The uDMAChannelModeGet() function returns \b UDMA_MODE_STOP when a +//! channel control structure is inactive and safe to modify. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelTransferSet(uint32_t ui32ChannelStructIndex, uint32_t ui32Mode, + void *pvSrcAddr, void *pvDstAddr, + uint32_t ui32TransferSize) +{ + tDMAControlTable *psControlTable; + uint32_t ui32Control; + uint32_t ui32Inc; + uint32_t ui32BufferBytes; + + // + // Check the arguments. + // + ASSERT((ui32ChannelStructIndex & 0xffff) < 64); + ASSERT(HWREG(UDMA_CTLBASE) != 0); + ASSERT(ui32Mode <= UDMA_MODE_PER_SCATTER_GATHER); + ASSERT((uint32_t)pvSrcAddr >= 0x20000000); + ASSERT((uint32_t)pvDstAddr >= 0x20000000); + ASSERT((ui32TransferSize != 0) && (ui32TransferSize <= 1024)); + + // + // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was + // passed as the ui32ChannelStructIndex parameter, extract just the channel + // index from this parameter. + // + ui32ChannelStructIndex &= 0x3f; + + // + // Get the base address of the control table. + // + psControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE); + + // + // Get the current control word value and mask off the mode and size + // fields. + // + ui32Control = (psControlTable[ui32ChannelStructIndex].ui32Control & + ~(UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M)); + + // + // Adjust the mode if the alt control structure is selected. + // + if(ui32ChannelStructIndex & UDMA_ALT_SELECT) + { + if((ui32Mode == UDMA_MODE_MEM_SCATTER_GATHER) || + (ui32Mode == UDMA_MODE_PER_SCATTER_GATHER)) + { + ui32Mode |= UDMA_MODE_ALT_SELECT; + } + } + + // + // Set the transfer size and mode in the control word (but don't write the + // control word yet as it could kick off a transfer). + // + ui32Control |= ui32Mode | ((ui32TransferSize - 1) << 4); + + // + // Get the address increment value for the source, from the control word. + // + ui32Inc = (ui32Control & UDMA_CHCTL_SRCINC_M); + + // + // Compute the ending source address of the transfer. If the source + // increment is set to none, then the ending address is the same as the + // beginning. + // + if(ui32Inc != UDMA_SRC_INC_NONE) + { + ui32Inc = ui32Inc >> 26; + ui32BufferBytes = ui32TransferSize << ui32Inc; + pvSrcAddr = (void *)((uint32_t)pvSrcAddr + ui32BufferBytes - 1); + } + + // + // Load the source ending address into the control block. + // + psControlTable[ui32ChannelStructIndex].pvSrcEndAddr = pvSrcAddr; + + // + // Get the address increment value for the destination, from the control + // word. + // + ui32Inc = ui32Control & UDMA_CHCTL_DSTINC_M; + + // + // Compute the ending destination address of the transfer. If the + // destination increment is set to none, then the ending address is the + // same as the beginning. + // + if(ui32Inc != UDMA_DST_INC_NONE) + { + // + // There is a special case if this is setting up a scatter-gather + // transfer. The destination pointer must point to the end of + // the alternate structure for this channel instead of calculating + // the end of the buffer in the normal way. + // + if((ui32Mode == UDMA_MODE_MEM_SCATTER_GATHER) || + (ui32Mode == UDMA_MODE_PER_SCATTER_GATHER)) + { + pvDstAddr = + (void *)&psControlTable[ui32ChannelStructIndex | + UDMA_ALT_SELECT].ui32Spare; + } + // + // Not a scatter-gather transfer, calculate end pointer normally. + // + else + { + ui32Inc = ui32Inc >> 30; + ui32BufferBytes = ui32TransferSize << ui32Inc; + pvDstAddr = (void *)((uint32_t)pvDstAddr + ui32BufferBytes - 1); + } + } + + // + // Load the destination ending address into the control block. + // + psControlTable[ui32ChannelStructIndex].pvDstEndAddr = pvDstAddr; + + // + // Write the new control word value. + // + psControlTable[ui32ChannelStructIndex].ui32Control = ui32Control; +} + +//***************************************************************************** +// +//! Configures a uDMA channel for scatter-gather mode. +//! +//! \param ui32ChannelNum is the uDMA channel number. +//! \param ui32TaskCount is the number of scatter-gather tasks to execute. +//! \param pvTaskList is a pointer to the beginning of the scatter-gather +//! task list. +//! \param ui32IsPeriphSG is a flag to indicate it is a peripheral +//! scatter-gather transfer (else it is memory scatter-gather transfer) +//! +//! This function is used to configure a channel for scatter-gather mode. +//! The caller must have already set up a task list and must pass a pointer to +//! the start of the task list as the \e pvTaskList parameter. The +//! \e ui32TaskCount parameter is the count of tasks in the task list, not the +//! size of the task list. The flag \e bIsPeriphSG should be used to indicate +//! if scatter-gather should be configured for peripheral or memory +//! operation. +//! +//! \sa uDMATaskStructEntry +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelScatterGatherSet(uint32_t ui32ChannelNum, uint32_t ui32TaskCount, + void *pvTaskList, uint32_t ui32IsPeriphSG) +{ + tDMAControlTable *psControlTable; + tDMAControlTable *psTaskTable; + + // + // Check the parameters + // + ASSERT((ui32ChannelNum & 0xffff) < 32); + ASSERT(HWREG(UDMA_CTLBASE) != 0); + ASSERT(pvTaskList != 0); + ASSERT(ui32TaskCount <= 1024); + ASSERT(ui32TaskCount != 0); + + // + // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was + // passed as the ui32ChannelNum parameter, extract just the channel number + // from this parameter. + // + ui32ChannelNum &= 0x1f; + + // + // Get the base address of the control table. + // + psControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE); + + // + // Get a handy pointer to the task list + // + psTaskTable = (tDMAControlTable *)pvTaskList; + + // + // Compute the ending address for the source pointer. This address is the + // last element of the last task in the task table + // + psControlTable[ui32ChannelNum].pvSrcEndAddr = + &psTaskTable[ui32TaskCount - 1].ui32Spare; + + // + // Compute the ending address for the destination pointer. This address + // is the end of the alternate structure for this channel. + // + psControlTable[ui32ChannelNum].pvDstEndAddr = + &psControlTable[ui32ChannelNum | UDMA_ALT_SELECT].ui32Spare; + + // + // Compute the control word. Most configurable items are fixed for + // scatter-gather. Item and increment sizes are all 32-bit and arb + // size must be 4. The count is the number of items in the task list + // times 4 (4 words per task). + // + psControlTable[ui32ChannelNum].ui32Control = + (UDMA_CHCTL_DSTINC_32 | UDMA_CHCTL_DSTSIZE_32 | + UDMA_CHCTL_SRCINC_32 | UDMA_CHCTL_SRCSIZE_32 | + UDMA_CHCTL_ARBSIZE_4 | + (((ui32TaskCount * 4) - 1) << UDMA_CHCTL_XFERSIZE_S) | + (ui32IsPeriphSG ? UDMA_CHCTL_XFERMODE_PER_SG : + UDMA_CHCTL_XFERMODE_MEM_SG)); + + // + // Scatter-gather operations can leave the alt bit set. So if doing + // back to back scatter-gather transfers, the second attempt may not + // work correctly because the alt bit is set. Therefore, clear the + // alt bit here to ensure that it is always cleared before a new SG + // transfer is started. + // + HWREG(UDMA_ALTCLR) = 1 << ui32ChannelNum; +} + +//***************************************************************************** +// +//! Gets the current transfer size for a uDMA channel control structure. +//! +//! \param ui32ChannelStructIndex is the logical OR of the uDMA channel number +//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. +//! +//! This function is used to get the uDMA transfer size for a channel. The +//! transfer size is the number of items to transfer, where the size of an item +//! might be 8, 16, or 32 bits. If a partial transfer has already occurred, +//! then the number of remaining items is returned. If the transfer is +//! complete, then 0 is returned. +//! +//! \return Returns the number of items remaining to transfer. +// +//***************************************************************************** +uint32_t +uDMAChannelSizeGet(uint32_t ui32ChannelStructIndex) +{ + tDMAControlTable *psControlTable; + uint32_t ui32Control; + + // + // Check the arguments. + // + ASSERT((ui32ChannelStructIndex & 0xffff) < 64); + ASSERT(HWREG(UDMA_CTLBASE) != 0); + + // + // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was + // passed as the ui32ChannelStructIndex parameter, extract just the channel + // index from this parameter. + // + ui32ChannelStructIndex &= 0x3f; + + // + // Get the base address of the control table. + // + psControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE); + + // + // Get the current control word value and mask off all but the size field + // and the mode field. + // + ui32Control = (psControlTable[ui32ChannelStructIndex].ui32Control & + (UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M)); + + // + // If the size field and mode field are 0 then the transfer is finished + // and there are no more items to transfer + // + if(ui32Control == 0) + { + return(0); + } + + // + // Otherwise, if either the size field or more field is non-zero, then + // not all the items have been transferred. + // + else + { + // + // Shift the size field and add one, then return to user. + // + return((ui32Control >> 4) + 1); + } +} + +//***************************************************************************** +// +//! Gets the transfer mode for a uDMA channel control structure. +//! +//! \param ui32ChannelStructIndex is the logical OR of the uDMA channel number +//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. +//! +//! This function is used to get the transfer mode for the uDMA channel and +//! to query the status of a transfer on a channel. When the transfer is +//! complete the mode is \b UDMA_MODE_STOP. +//! +//! \return Returns the transfer mode of the specified channel and control +//! structure, which is one of the following values: \b UDMA_MODE_STOP, +//! \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO, \b UDMA_MODE_PINGPONG, +//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER. +// +//***************************************************************************** +uint32_t +uDMAChannelModeGet(uint32_t ui32ChannelStructIndex) +{ + tDMAControlTable *psControlTable; + uint32_t ui32Control; + + // + // Check the arguments. + // + ASSERT((ui32ChannelStructIndex & 0xffff) < 64); + ASSERT(HWREG(UDMA_CTLBASE) != 0); + + // + // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was + // passed as the ui32ChannelStructIndex parameter, extract just the channel + // index from this parameter. + // + ui32ChannelStructIndex &= 0x3f; + + // + // Get the base address of the control table. + // + psControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE); + + // + // Get the current control word value and mask off all but the mode field. + // + ui32Control = (psControlTable[ui32ChannelStructIndex].ui32Control & + UDMA_CHCTL_XFERMODE_M); + + // + // Check if scatter/gather mode, and if so, mask off the alt bit. + // + if(((ui32Control & ~UDMA_MODE_ALT_SELECT) == + UDMA_MODE_MEM_SCATTER_GATHER) || + ((ui32Control & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_PER_SCATTER_GATHER)) + { + ui32Control &= ~UDMA_MODE_ALT_SELECT; + } + + // + // Return the mode to the caller. + // + return(ui32Control); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the uDMA controller. +//! +//! \param ui32IntChannel identifies which uDMA interrupt is to be registered. +//! \param pfnHandler is a pointer to the function to be called when the +//! interrupt is activated. +//! +//! This function registers and enables the handler to be called when the uDMA +//! controller generates an interrupt. The \e ui32IntChannel parameter should +//! be one of the following: +//! +//! - \b INT_UDMA to register an interrupt handler to process interrupts +//! from the uDMA software channel (UDMA_CHANNEL_SW) +//! - \b INT_UDMAERR to register an interrupt handler to process uDMA error +//! interrupts +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \note The interrupt handler for the uDMA is for transfer completion when +//! the channel UDMA_CHANNEL_SW is used and for error interrupts. The +//! interrupts for each peripheral channel are handled through the individual +//! peripheral interrupt handlers. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAIntRegister(uint32_t ui32IntChannel, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(pfnHandler); + + // + // Register the interrupt handler. + // + IntRegister(ui32IntChannel, pfnHandler); + + // + // Enable the memory management fault. + // + IntEnable(ui32IntChannel); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the uDMA controller. +//! +//! \param ui32IntChannel identifies which uDMA interrupt to unregister. +//! +//! This function disables and unregisters the handler to be called for the +//! specified uDMA interrupt. The \e ui32IntChannel parameter should be one of +//! \b INT_UDMA or \b INT_UDMAERR as documented for the function +//! uDMAIntRegister(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAIntUnregister(uint32_t ui32IntChannel) +{ + // + // Disable the interrupt. + // + IntDisable(ui32IntChannel); + + // + // Unregister the interrupt handler. + // + IntUnregister(ui32IntChannel); +} + +//***************************************************************************** +// +//! Gets the uDMA controller channel interrupt status. +//! +//! This function is used to get the interrupt status of the uDMA controller. +//! The returned value is a 32-bit bit mask that indicates which channels are +//! requesting an interrupt. This function can be used from within an +//! interrupt handler to determine or confirm which uDMA channel has requested +//! an interrupt. +//! +//! \note This function is only available on devices that have the DMA Channel +//! Interrupt Status Register (DMACHIS). Please consult the data sheet for +//! your part. +//! +//! \return Returns a 32-bit mask which indicates requesting uDMA channels. +//! There is a bit for each channel and a 1 indicates that the channel +//! is requesting an interrupt. Multiple bits can be set. +// +//***************************************************************************** +uint32_t +uDMAIntStatus(void) +{ + // + // Return the value of the uDMA interrupt status register + // + return(HWREG(UDMA_CHIS)); +} + +//***************************************************************************** +// +//! Clears uDMA interrupt status. +//! +//! \param ui32ChanMask is a 32-bit mask with one bit for each uDMA channel. +//! +//! This function clears bits in the uDMA interrupt status register according +//! to which bits are set in \e ui32ChanMask. There is one bit for each +//! channel. If a a bit is set in \e ui32ChanMask, then that corresponding +//! channel's interrupt status is cleared (if it was set). +//! +//! \note This function is only available on devices that have the DMA Channel +//! Interrupt Status Register (DMACHIS). Please consult the data sheet for +//! your part. Devices without the DMACHIS register have uDMA done status in +//! the interrupt registers in the peripheral memory maps. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAIntClear(uint32_t ui32ChanMask) +{ + // + // Clear the requested bits in the uDMA interrupt status register + // + HWREG(UDMA_CHIS) = ui32ChanMask; +} + +//***************************************************************************** +// +//! Assigns a peripheral mapping for a uDMA channel. +//! +//! \param ui32Mapping is a macro specifying the peripheral assignment for +//! a channel. +//! +//! This function assigns a peripheral mapping to a uDMA channel. It is +//! used to select which peripheral is used for a uDMA channel. The parameter +//! \e ui32Mapping should be one of the macros named \b UDMA_CHn_tttt from the +//! header file \e udma.h. For example, to assign uDMA channel 0 to the +//! UART2 RX channel, the parameter should be the macro \b UDMA_CH0_UART2RX. +//! +//! Please consult the Tiva data sheet for a table showing all the +//! possible peripheral assignments for the uDMA channels for a particular +//! device. +//! +//! \note This function is only available on devices that have the DMA Channel +//! Map Select registers (DMACHMAP0-3). Please consult the data sheet for +//! your part. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelAssign(uint32_t ui32Mapping) +{ + uint32_t ui32MapReg; + uint_fast8_t ui8MapShift; + uint_fast8_t ui8ChannelNum; + + // + // Check the parameters + // + ASSERT((ui32Mapping & 0xffffff00) < 0x00090000); + + // + // Extract the channel number and map encoding value from the parameter. + // + ui8ChannelNum = ui32Mapping & 0xff; + ui32Mapping = ui32Mapping >> 16; + + // + // Find the uDMA channel mapping register and shift value to use for this + // channel + // + ui32MapReg = UDMA_CHMAP0 + (uint32_t)((ui8ChannelNum / 8) * 4); + ui8MapShift = (ui8ChannelNum % 8) * 4; + + // + // Set the channel map encoding for this channel + // + HWREG(ui32MapReg) = (HWREG(ui32MapReg) & ~(0xf << ui8MapShift)) | + ui32Mapping << ui8MapShift; +} + +//***************************************************************************** +// +// The following functions are deprecated. Use uDMAChannelAssign() instead +// to accomplish the same end. +// +//***************************************************************************** +#ifndef DEPRECATED +//***************************************************************************** +// +//! Selects the secondary peripheral for a set of uDMA channels. +//! +//! \param ui32SecPeriphs is the logical OR of the uDMA channels for which to +//! use the secondary peripheral, instead of the default peripheral. +//! +//! This function is used to select the secondary peripheral assignment for a +//! set of uDMA channels. By selecting the secondary peripheral assignment for +//! a channel, the default peripheral assignment is no longer available for +//! that channel. +//! +//! The parameter \e ui32SecPeriphs can be the logical OR of any of the +//! following macros. If one of the macros below is in the list passed to this +//! function, then the secondary peripheral (marked as \b _SEC_) is selected. +//! +//! - \b UDMA_DEF_USBEP1RX_SEC_UART2RX +//! - \b UDMA_DEF_USBEP1TX_SEC_UART2TX +//! - \b UDMA_DEF_USBEP2RX_SEC_TMR3A +//! - \b UDMA_DEF_USBEP2TX_SEC_TMR3B +//! - \b UDMA_DEF_USBEP3RX_SEC_TMR2A +//! - \b UDMA_DEF_USBEP3TX_SEC_TMR2B +//! - \b UDMA_DEF_ETH0RX_SEC_TMR2A +//! - \b UDMA_DEF_ETH0TX_SEC_TMR2B +//! - \b UDMA_DEF_UART0RX_SEC_UART1RX +//! - \b UDMA_DEF_UART0TX_SEC_UART1TX +//! - \b UDMA_DEF_SSI0RX_SEC_SSI1RX +//! - \b UDMA_DEF_SSI0TX_SEC_SSI1TX +//! - \b UDMA_DEF_RESERVED_SEC_UART2RX +//! - \b UDMA_DEF_RESERVED_SEC_UART2TX +//! - \b UDMA_DEF_ADC00_SEC_TMR2A +//! - \b UDMA_DEF_ADC01_SEC_TMR2B +//! - \b UDMA_DEF_ADC02_SEC_RESERVED +//! - \b UDMA_DEF_ADC03_SEC_RESERVED +//! - \b UDMA_DEF_TMR0A_SEC_TMR1A +//! - \b UDMA_DEF_TMR0B_SEC_TMR1B +//! - \b UDMA_DEF_TMR1A_SEC_EPI0RX +//! - \b UDMA_DEF_TMR1B_SEC_EPI0TX +//! - \b UDMA_DEF_UART1RX_SEC_RESERVED +//! - \b UDMA_DEF_UART1TX_SEC_RESERVED +//! - \b UDMA_DEF_SSI1RX_SEC_ADC10 +//! - \b UDMA_DEF_SSI1TX_SEC_ADC11 +//! - \b UDMA_DEF_RESERVED_SEC_ADC12 +//! - \b UDMA_DEF_RESERVED_SEC_ADC13 +//! - \b UDMA_DEF_I2S0RX_SEC_RESERVED +//! - \b UDMA_DEF_I2S0TX_SEC_RESERVED +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelSelectSecondary(uint32_t ui32SecPeriphs) +{ + // + // Select the secondary peripheral for the specified channels. + // + HWREG(UDMA_CHASGN) |= ui32SecPeriphs; +} + +//***************************************************************************** +// +//! Selects the default peripheral for a set of uDMA channels. +//! +//! \param ui32DefPeriphs is the logical OR of the uDMA channels for which to +//! use the default peripheral, instead of the secondary peripheral. +//! +//! This function is used to select the default peripheral assignment for a set +//! of uDMA channels. +//! +//! The parameter \e ui32DefPeriphs can be the logical OR of any of the +//! following macros. If one of the macros below is in the list passed to this +//! function, then the default peripheral (marked as \b _DEF_) is selected. +//! +//! - \b UDMA_DEF_USBEP1RX_SEC_UART2RX +//! - \b UDMA_DEF_USBEP1TX_SEC_UART2TX +//! - \b UDMA_DEF_USBEP2RX_SEC_TMR3A +//! - \b UDMA_DEF_USBEP2TX_SEC_TMR3B +//! - \b UDMA_DEF_USBEP3RX_SEC_TMR2A +//! - \b UDMA_DEF_USBEP3TX_SEC_TMR2B +//! - \b UDMA_DEF_ETH0RX_SEC_TMR2A +//! - \b UDMA_DEF_ETH0TX_SEC_TMR2B +//! - \b UDMA_DEF_UART0RX_SEC_UART1RX +//! - \b UDMA_DEF_UART0TX_SEC_UART1TX +//! - \b UDMA_DEF_SSI0RX_SEC_SSI1RX +//! - \b UDMA_DEF_SSI0TX_SEC_SSI1TX +//! - \b UDMA_DEF_RESERVED_SEC_UART2RX +//! - \b UDMA_DEF_RESERVED_SEC_UART2TX +//! - \b UDMA_DEF_ADC00_SEC_TMR2A +//! - \b UDMA_DEF_ADC01_SEC_TMR2B +//! - \b UDMA_DEF_ADC02_SEC_RESERVED +//! - \b UDMA_DEF_ADC03_SEC_RESERVED +//! - \b UDMA_DEF_TMR0A_SEC_TMR1A +//! - \b UDMA_DEF_TMR0B_SEC_TMR1B +//! - \b UDMA_DEF_TMR1A_SEC_EPI0RX +//! - \b UDMA_DEF_TMR1B_SEC_EPI0TX +//! - \b UDMA_DEF_UART1RX_SEC_RESERVED +//! - \b UDMA_DEF_UART1TX_SEC_RESERVED +//! - \b UDMA_DEF_SSI1RX_SEC_ADC10 +//! - \b UDMA_DEF_SSI1TX_SEC_ADC11 +//! - \b UDMA_DEF_RESERVED_SEC_ADC12 +//! - \b UDMA_DEF_RESERVED_SEC_ADC13 +//! - \b UDMA_DEF_I2S0RX_SEC_RESERVED +//! - \b UDMA_DEF_I2S0TX_SEC_RESERVED +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelSelectDefault(uint32_t ui32DefPeriphs) +{ + // + // Select the default peripheral for the specified channels. + // + HWREG(UDMA_CHASGN) &= ~ui32DefPeriphs; +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/usb.c b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/usb.c new file mode 100644 index 0000000000000000000000000000000000000000..839a5575edd24523e8e3f10f9f9dc6451a614b55 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/usb.c @@ -0,0 +1,5910 @@ +//***************************************************************************** +// +// usb.c - Driver for the USB Interface. +// +// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup usb_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_usb.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/sysctl.h" +#include "driverlib/udma.h" +#include "driverlib/usb.h" + +//***************************************************************************** +// +// Amount to shift the RX interrupt sources by in the flags used in the +// interrupt calls. +// +//***************************************************************************** +#define USB_INTEP_RX_SHIFT 16 + +//***************************************************************************** +// +// Amount to shift the RX endpoint status sources by in the flags used in the +// calls. +// +//***************************************************************************** +#define USB_RX_EPSTATUS_SHIFT 16 + +//***************************************************************************** +// +// Converts from an endpoint specifier to the offset of the endpoint's +// control/status registers. +// +//***************************************************************************** +#define EP_OFFSET(Endpoint) (Endpoint - 0x10) + +//***************************************************************************** +// +// Sets one of the indexed registers. +// +// \param ui32Base specifies the USB module base address. +// \param ui32Endpoint is the endpoint index to target for this write. +// \param ui32IndexedReg is the indexed register to write to. +// \param ui8Value is the value to write to the register. +// +// This function is used to access the indexed registers for each endpoint. +// The only registers that are indexed are the FIFO configuration registers, +// which are not used after configuration. +// +// \return None. +// +//***************************************************************************** +static void +_USBIndexWrite(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32IndexedReg, uint32_t ui32Value, uint32_t ui32Size) +{ + uint32_t ui32Index; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == 0) || (ui32Endpoint == 1) || (ui32Endpoint == 2) || + (ui32Endpoint == 3)); + ASSERT((ui32Size == 1) || (ui32Size == 2)); + + // + // Save the old index in case it was in use. + // + ui32Index = HWREGB(ui32Base + USB_O_EPIDX); + + // + // Set the index. + // + HWREGB(ui32Base + USB_O_EPIDX) = ui32Endpoint; + + // + // Determine the size of the register value. + // + if(ui32Size == 1) + { + // + // Set the value. + // + HWREGB(ui32Base + ui32IndexedReg) = ui32Value; + } + else + { + // + // Set the value. + // + HWREGH(ui32Base + ui32IndexedReg) = ui32Value; + } + + // + // Restore the old index in case it was in use. + // + HWREGB(ui32Base + USB_O_EPIDX) = ui32Index; +} + +//***************************************************************************** +// +// Reads one of the indexed registers. +// +// \param ui32Base specifies the USB module base address. +// \param ui32Endpoint is the endpoint index to target for this write. +// \param ui32IndexedReg is the indexed register to write to. +// \param ui32Size is a value of 1 or 2 indicating the byte size of the read. +// +// This function is used internally to access the indexed registers for each +// endpoint. The only registers that are indexed are the FIFO configuration +// registers, which are not used after configuration. +// +// \return The value in the register requested. +// +//***************************************************************************** +static uint32_t +_USBIndexRead(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32IndexedReg, uint32_t ui32Size) +{ + uint8_t ui8Index; + uint32_t ui32Value; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == 0) || (ui32Endpoint == 1) || (ui32Endpoint == 2) || + (ui32Endpoint == 3)); + ASSERT((ui32Size == 1) || (ui32Size == 2)); + + // + // Save the old index in case it was in use. + // + ui8Index = HWREGB(ui32Base + USB_O_EPIDX); + + // + // Set the index. + // + HWREGB(ui32Base + USB_O_EPIDX) = ui32Endpoint; + + // + // Determine the size of the register value. + // + if(ui32Size == 1) + { + // + // Get the value. + // + ui32Value = HWREGB(ui32Base + ui32IndexedReg); + } + else + { + // + // Get the value. + // + ui32Value = HWREGH(ui32Base + ui32IndexedReg); + } + + // + // Restore the old index in case it was in use. + // + HWREGB(ui32Base + USB_O_EPIDX) = ui8Index; + + // + // Return the register's value. + // + return(ui32Value); +} + +//***************************************************************************** +// +//! Puts the USB bus in a suspended state. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! When used in host mode, this function puts the USB bus in the suspended +//! state. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostSuspend(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Send the suspend signaling to the USB bus. + // + HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_SUSPEND; +} + +//***************************************************************************** +// +//! Handles the USB bus reset condition. +//! +//! \param ui32Base specifies the USB module base address. +//! \param bStart specifies whether to start or stop signaling reset on the USB +//! bus. +//! +//! When this function is called with the \e bStart parameter set to \b true, +//! this function causes the start of a reset condition on the USB bus. +//! The caller must then delay at least 20ms before calling this function +//! again with the \e bStart parameter set to \b false. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostReset(uint32_t ui32Base, bool bStart) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Send a reset signal to the bus. + // + if(bStart) + { + HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_RESET; + } + else + { + HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_RESET; + } +} + +//***************************************************************************** +// +//! Enables or disables USB high-speed negotiation. +//! +//! \param ui32Base specifies the USB module base address. +//! \param bEnable specifies whether to enable or disable high-speed +//! negotiation. +//! +//! High-speed negotiations for both host and device mode are enabled when this +//! function is called with the \e bEnable parameter set to \b true. In device +//! mode this causes the device to negotiate for high speed when the +//! USB controller receives a reset from the host. In host mode, the USB host +//! enables high-speed negotiations when resetting the connected device. If +//! \e bEnable is set to \b false the controller only operates only in +//! full-speed or low-speed. +//! +//! \b Example: Enable USB high-speed mode. +//! +//! \verbatim +//! // +//! // Enable USB high-speed mode. +//! // +//! USBHighSpeed(USB0_BASE, true); +//! \endverbatim +//! +//! \note This feature is not available on all Tiva devices and should only be +//! called when the USB is connected to an external ULPI PHY. Please +//! check the data sheet to determine if the USB controller can interface with +//! a ULPI PHY. +//! +//! \return None. +// +//***************************************************************************** +void +USBHighSpeed(uint32_t ui32Base, bool bEnable) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + if(bEnable) + { + // + // Enable high speed mode negotiations in hosts or device mode. + // + HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_HSENAB; + } + else + { + // + // Enable high speed mode negotiations in hosts or device mode. + // + HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_HSENAB; + } +} + +//***************************************************************************** +// +//! Handles the USB bus resume condition. +//! +//! \param ui32Base specifies the USB module base address. +//! \param bStart specifies if the USB controller is entering or leaving the +//! resume signaling state. +//! +//! When in device mode, this function brings the USB controller out of the +//! suspend state. This call must first be made with the \e bStart parameter +//! set to \b true to start resume signaling. The device application must +//! then delay at least 10ms but not more than 15ms before calling this +//! function with the \e bStart parameter set to \b false. +//! +//! When in host mode, this function signals devices to leave the suspend +//! state. This call must first be made with the \e bStart parameter set to +//! \b true to start resume signaling. The host application must then delay +//! at least 20ms before calling this function with the \e bStart parameter set +//! to \b false. This action causes the controller to complete the resume +//! signaling on the USB bus. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostResume(uint32_t ui32Base, bool bStart) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Send a resume signal to the bus. + // + if(bStart) + { + HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_RESUME; + } + else + { + HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_RESUME; + } +} + +//***************************************************************************** +// +//! Returns the current speed of the USB device connected. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the current speed of the USB bus in host mode. +//! +//! \b Example: Get the USB connection speed. +//! +//! \verbatim +//! // +//! // Get the connection speed of the device connected to the USB controller. +//! // +//! USBHostSpeedGet(USB0_BASE); +//! \endverbatim +//! +//! \note This function must only be called in host mode. +//! +//! \return Returns one of the following: \b USB_LOW_SPEED, \b USB_FULL_SPEED, +//! \b USB_HIGH_SPEED, or \b USB_UNDEF_SPEED. +// +//***************************************************************************** +uint32_t +USBHostSpeedGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // If the Full Speed device bit is set, then this is a full speed device. + // + if(HWREGB(ui32Base + USB_O_POWER) & USB_POWER_HSMODE) + { + return(USB_HIGH_SPEED); + } + + // + // If the Full Speed device bit is set, then this is a full speed device. + // + if(HWREGB(ui32Base + USB_O_DEVCTL) & USB_DEVCTL_FSDEV) + { + return(USB_FULL_SPEED); + } + + // + // If the Low Speed device bit is set, then this is a low speed device. + // + if(HWREGB(ui32Base + USB_O_DEVCTL) & USB_DEVCTL_LSDEV) + { + return(USB_LOW_SPEED); + } + + // + // The device speed is not known. + // + return(USB_UNDEF_SPEED); +} + +//***************************************************************************** +// +//! Returns the current speed of the USB controller in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the operating speed of the connection to the USB host +//! controller. This function returns either \b USB_HIGH_SPEED or +//! \b USB_FULL_SPEED to indicate the connection speed in device mode. +//! +//! \b Example: Get the USB connection speed. +//! +//! \verbatim +//! // +//! // Get the connection speed of the USB controller. +//! // +//! USBDevSpeedGet(USB0_BASE); +//! \endverbatim +//! +//! \note This function must only be called in device mode. +//! +//! \return Returns either \b USB_HIGH_SPEED or \b USB_FULL_SPEED. +// +//***************************************************************************** +uint32_t +USBDevSpeedGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // If the Full Speed device bit is set, then this is a full speed device. + // + if(HWREGB(ui32Base + USB_O_POWER) & USB_POWER_HSMODE) + { + return(USB_HIGH_SPEED); + } + + return(USB_FULL_SPEED); +} + +//***************************************************************************** +// +//! Disables control interrupts on a specified USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Flags specifies which control interrupts to disable. +//! +//! This function disables the control interrupts for the USB controller +//! specified by the \e ui32Base parameter. The \e ui32Flags parameter +//! specifies which control interrupts to disable. The flags passed in the +//! \e ui32Flags parameters must be the definitions that start with +//! \b USB_INTCTRL_* and not any other \b USB_INT flags. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntDisableControl(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Flags & ~(USB_INTCTRL_ALL)) == 0); + + // + // If any general interrupts were disabled then write the general interrupt + // settings out to the hardware. + // + if(ui32Flags & USB_INTCTRL_STATUS) + { + HWREGB(ui32Base + USB_O_IE) &= ~(ui32Flags & USB_INTCTRL_STATUS); + } + + // + // Disable the power fault interrupt. + // + if(ui32Flags & USB_INTCTRL_POWER_FAULT) + { + HWREG(ui32Base + USB_O_EPCIM) = 0; + } + + // + // Disable the ID pin detect interrupt. + // + if(ui32Flags & USB_INTCTRL_MODE_DETECT) + { + HWREG(USB0_BASE + USB_O_IDVIM) = 0; + } +} + +//***************************************************************************** +// +//! Enables control interrupts on a specified USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Flags specifies which control interrupts to enable. +//! +//! This function enables the control interrupts for the USB controller +//! specified by the \e ui32Base parameter. The \e ui32Flags parameter +//! specifies which control interrupts to enable. The flags passed in the +//! \e ui32Flags parameters must be the definitions that start with +//! \b USB_INTCTRL_* and not any other \b USB_INT flags. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntEnableControl(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Flags & (~USB_INTCTRL_ALL)) == 0); + + // + // If any general interrupts were enabled, then write the general + // interrupt settings out to the hardware. + // + if(ui32Flags & USB_INTCTRL_STATUS) + { + HWREGB(ui32Base + USB_O_IE) |= ui32Flags; + } + + // + // Enable the power fault interrupt. + // + if(ui32Flags & USB_INTCTRL_POWER_FAULT) + { + HWREG(ui32Base + USB_O_EPCIM) = USB_EPCIM_PF; + } + + // + // Enable the ID pin detect interrupt. + // + if(ui32Flags & USB_INTCTRL_MODE_DETECT) + { + HWREG(USB0_BASE + USB_O_IDVIM) = USB_IDVIM_ID; + } +} + +//***************************************************************************** +// +//! Returns the control interrupt status on a specified USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function reads control interrupt status for a USB controller. This +//! call returns the current status for control interrupts only, the endpoint +//! interrupt status is retrieved by calling USBIntStatusEndpoint(). The bit +//! values returned are compared against the \b USB_INTCTRL_* values. +//! +//! The following are the meanings of all \b USB_INCTRL_ flags and the modes +//! for which they are valid. These values apply to any calls to +//! USBIntStatusControl(), USBIntEnableControl(), and USBIntDisableControl(). +//! Some of these flags are only valid in the following modes as indicated in +//! the parentheses: Host, Device, and OTG. +//! +//! - \b USB_INTCTRL_ALL - A full mask of all control interrupt sources. +//! - \b USB_INTCTRL_VBUS_ERR - A VBUS error has occurred (Host Only). +//! - \b USB_INTCTRL_SESSION - Session Start Detected on A-side of cable +//! (OTG Only). +//! - \b USB_INTCTRL_SESSION_END - Session End Detected (Device Only) +//! - \b USB_INTCTRL_DISCONNECT - Device Disconnect Detected (Host Only) +//! - \b USB_INTCTRL_CONNECT - Device Connect Detected (Host Only) +//! - \b USB_INTCTRL_SOF - Start of Frame Detected. +//! - \b USB_INTCTRL_BABBLE - USB controller detected a device signaling past +//! the end of a frame (Host Only) +//! - \b USB_INTCTRL_RESET - Reset signaling detected by device (Device Only) +//! - \b USB_INTCTRL_RESUME - Resume signaling detected. +//! - \b USB_INTCTRL_SUSPEND - Suspend signaling detected by device (Device +//! Only) +//! - \b USB_INTCTRL_MODE_DETECT - OTG cable mode detection has completed +//! (OTG Only) +//! - \b USB_INTCTRL_POWER_FAULT - Power Fault detected (Host Only) +//! +//! \note This call clears the source of all of the control status interrupts. +//! +//! \return Returns the status of the control interrupts for a USB controller. +// +//***************************************************************************** +uint32_t +USBIntStatusControl(uint32_t ui32Base) +{ + uint32_t ui32Status; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Get the general interrupt status, these bits go into the upper 8 bits + // of the returned value. + // + ui32Status = HWREGB(ui32Base + USB_O_IS); + + // + // Add the power fault status. + // + if(HWREG(ui32Base + USB_O_EPCISC) & USB_EPCISC_PF) + { + // + // Indicate a power fault was detected. + // + ui32Status |= USB_INTCTRL_POWER_FAULT; + + // + // Clear the power fault interrupt. + // + HWREGB(ui32Base + USB_O_EPCISC) |= USB_EPCISC_PF; + } + + if(HWREG(USB0_BASE + USB_O_IDVISC) & USB_IDVRIS_ID) + { + // + // Indicate an id detection. + // + ui32Status |= USB_INTCTRL_MODE_DETECT; + + // + // Clear the id detection interrupt. + // + HWREG(USB0_BASE + USB_O_IDVISC) |= USB_IDVRIS_ID; + } + + // + // Return the combined interrupt status. + // + return(ui32Status); +} + +//***************************************************************************** +// +//! Disables endpoint interrupts on a specified USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Flags specifies which endpoint interrupts to disable. +//! +//! This function disables endpoint interrupts for the USB controller specified +//! by the \e ui32Base parameter. The \e ui32Flags parameter specifies which +//! endpoint interrupts to disable. The flags passed in the \e ui32Flags +//! parameters must be the definitions that start with \b USB_INTEP_* and not +//! any other \b USB_INT flags. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntDisableEndpoint(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // If any transmit interrupts were disabled, then write the transmit + // interrupt settings out to the hardware. + // + HWREGH(ui32Base + USB_O_TXIE) &= + ~(ui32Flags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0)); + + // + // If any receive interrupts were disabled, then write the receive + // interrupt settings out to the hardware. + // + HWREGH(ui32Base + USB_O_RXIE) &= + ~((ui32Flags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >> + USB_INTEP_RX_SHIFT); +} + +//***************************************************************************** +// +//! Enables endpoint interrupts on a specified USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Flags specifies which endpoint interrupts to enable. +//! +//! This function enables endpoint interrupts for the USB controller specified +//! by the \e ui32Base parameter. The \e ui32Flags parameter specifies which +//! endpoint interrupts to enable. The flags passed in the \e ui32Flags +//! parameters must be the definitions that start with \b USB_INTEP_* and not +//! any other \b USB_INT flags. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntEnableEndpoint(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Enable any transmit endpoint interrupts. + // + HWREGH(ui32Base + USB_O_TXIE) |= + ui32Flags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0); + + // + // Enable any receive endpoint interrupts. + // + HWREGH(ui32Base + USB_O_RXIE) |= + ((ui32Flags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >> + USB_INTEP_RX_SHIFT); +} + +//***************************************************************************** +// +//! Returns the endpoint interrupt status on a specified USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function reads endpoint interrupt status for a USB controller. This +//! call returns the current status for endpoint interrupts only, the control +//! interrupt status is retrieved by calling USBIntStatusControl(). The bit +//! values returned are compared against the \b USB_INTEP_* values. +//! These values are grouped into classes for \b USB_INTEP_HOST_* and +//! \b USB_INTEP_DEV_* values to handle both host and device modes with all +//! endpoints. +//! +//! \note This call clears the source of all of the endpoint interrupts. +//! +//! \return Returns the status of the endpoint interrupts for a USB controller. +// +//***************************************************************************** +uint32_t +USBIntStatusEndpoint(uint32_t ui32Base) +{ + uint32_t ui32Status; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Get the transmit interrupt status. + // + ui32Status = HWREGH(ui32Base + USB_O_TXIS); + ui32Status |= (HWREGH(ui32Base + USB_O_RXIS) << USB_INTEP_RX_SHIFT); + + // + // Return the combined interrupt status. + // + return(ui32Status); +} + +//***************************************************************************** +// +//! Returns the interrupt number for a specified USB module. +//! +//! \param ui32Base is the base address of the USB module. +//! +//! This function returns the interrupt number for the USB module with the base +//! address passed in the \e ui32Base parameter. +//! +//! \return Returns the USB interrupt number or 0 if the interrupt does not +//! exist. +// +//***************************************************************************** +static uint32_t +_USBIntNumberGet(uint32_t ui32Base) +{ + uint32_t ui32Int; + + if(CLASS_IS_TM4C123) + { + ui32Int = INT_USB0_TM4C123; + } + else if(CLASS_IS_TM4C129) + { + ui32Int = INT_USB0_TM4C129; + } + else + { + ui32Int = 0; + } + return(ui32Int); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param pfnHandler is a pointer to the function to be called when a USB +//! interrupt occurs. +//! +//! This function registers the handler to be called when a USB interrupt +//! occurs and enables the global USB interrupt in the interrupt controller. +//! The specific desired USB interrupts must be enabled via a separate call to +//! USBIntEnable(). It is the interrupt handler's responsibility to clear the +//! interrupt sources via calls to USBIntStatusControl() and +//! USBIntStatusEndpoint(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + ui32Int = _USBIntNumberGet(ui32Base); + + ASSERT(ui32Int != 0); + + // + // Register the interrupt handler. + // + IntRegister(ui32Int, pfnHandler); + + // + // Enable the USB interrupt. + // + IntEnable(ui32Int); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function unregisters the interrupt handler. This function also +//! disables the USB interrupt in the interrupt controller. +//! +//! \sa IntRegister() for important information about registering or +//! unregistering interrupt handlers. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntUnregister(uint32_t ui32Base) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + ui32Int = _USBIntNumberGet(ui32Base); + + ASSERT(ui32Int != 0); + + // + // Disable the USB interrupt. + // + IntDisable(ui32Int); + + // + // Unregister the interrupt handler. + // + IntUnregister(ui32Int); +} + +//***************************************************************************** +// +//! Returns the current status of an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! +//! This function returns the status of a specified endpoint. If any of these +//! status bits must be cleared, then the USBDevEndpointStatusClear() or the +//! USBHostEndpointStatusClear() functions must be called. +//! +//! The following are the status flags for host mode: +//! +//! - \b USB_HOST_IN_PID_ERROR - PID error on the specified endpoint. +//! - \b USB_HOST_IN_NOT_COMP - The device failed to respond to an IN request. +//! - \b USB_HOST_IN_STALL - A stall was received on an IN endpoint. +//! - \b USB_HOST_IN_DATA_ERROR - There was a CRC or bit-stuff error on an IN +//! endpoint in Isochronous mode. +//! - \b USB_HOST_IN_NAK_TO - NAKs received on this IN endpoint for more than +//! the specified timeout period. +//! - \b USB_HOST_IN_ERROR - Failed to communicate with a device using this IN +//! endpoint. +//! - \b USB_HOST_IN_FIFO_FULL - This IN endpoint's FIFO is full. +//! - \b USB_HOST_IN_PKTRDY - Data packet ready on this IN endpoint. +//! - \b USB_HOST_OUT_NAK_TO - NAKs received on this OUT endpoint for more than +//! the specified timeout period. +//! - \b USB_HOST_OUT_NOT_COMP - The device failed to respond to an OUT +//! request. +//! - \b USB_HOST_OUT_STALL - A stall was received on this OUT endpoint. +//! - \b USB_HOST_OUT_ERROR - Failed to communicate with a device using this +//! OUT endpoint. +//! - \b USB_HOST_OUT_FIFO_NE - This endpoint's OUT FIFO is not empty. +//! - \b USB_HOST_OUT_PKTPEND - The data transfer on this OUT endpoint has not +//! completed. +//! - \b USB_HOST_EP0_NAK_TO - NAKs received on endpoint zero for more than the +//! specified timeout period. +//! - \b USB_HOST_EP0_ERROR - The device failed to respond to a request on +//! endpoint zero. +//! - \b USB_HOST_EP0_IN_STALL - A stall was received on endpoint zero for an +//! IN transaction. +//! - \b USB_HOST_EP0_IN_PKTRDY - Data packet ready on endpoint zero for an IN +//! transaction. +//! +//! The following are the status flags for device mode: +//! +//! - \b USB_DEV_OUT_SENT_STALL - A stall was sent on this OUT endpoint. +//! - \b USB_DEV_OUT_DATA_ERROR - There was a CRC or bit-stuff error on an OUT +//! endpoint. +//! - \b USB_DEV_OUT_OVERRUN - An OUT packet was not loaded due to a full FIFO. +//! - \b USB_DEV_OUT_FIFO_FULL - The OUT endpoint's FIFO is full. +//! - \b USB_DEV_OUT_PKTRDY - There is a data packet ready in the OUT +//! endpoint's FIFO. +//! - \b USB_DEV_IN_NOT_COMP - A larger packet was split up, more data to come. +//! - \b USB_DEV_IN_SENT_STALL - A stall was sent on this IN endpoint. +//! - \b USB_DEV_IN_UNDERRUN - Data was requested on the IN endpoint and no +//! data was ready. +//! - \b USB_DEV_IN_FIFO_NE - The IN endpoint's FIFO is not empty. +//! - \b USB_DEV_IN_PKTPEND - The data transfer on this IN endpoint has not +//! completed. +//! - \b USB_DEV_EP0_SETUP_END - A control transaction ended before Data End +//! condition was sent. +//! - \b USB_DEV_EP0_SENT_STALL - A stall was sent on endpoint zero. +//! - \b USB_DEV_EP0_IN_PKTPEND - The data transfer on endpoint zero has not +//! completed. +//! - \b USB_DEV_EP0_OUT_PKTRDY - There is a data packet ready in endpoint +//! zero's OUT FIFO. +//! +//! \return The current status flags for the endpoint depending on mode. +// +//***************************************************************************** +uint32_t +USBEndpointStatus(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + uint32_t ui32Status; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // Get the TX portion of the endpoint status. + // + ui32Status = HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRL1); + + // + // Get the RX portion of the endpoint status. + // + ui32Status |= + ((HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRL1)) << + USB_RX_EPSTATUS_SHIFT); + + // + // Return the endpoint status. + // + return(ui32Status); +} + +//***************************************************************************** +// +//! Clears the status bits in this endpoint in host mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags are the status bits that are cleared. +//! +//! This function clears the status of any bits that are passed in the +//! \e ui32Flags parameter. The \e ui32Flags parameter can take the value +//! returned from the USBEndpointStatus() call. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostEndpointStatusClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // Clear the specified flags for the endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + HWREGB(ui32Base + USB_O_CSRL0) &= ~ui32Flags; + } + else + { + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~ui32Flags; + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(ui32Flags >> USB_RX_EPSTATUS_SHIFT); + } +} + +//***************************************************************************** +// +//! Clears the status bits in this endpoint in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags are the status bits that are cleared. +//! +//! This function clears the status of any bits that are passed in the +//! \e ui32Flags parameter. The \e ui32Flags parameter can take the value +//! returned from the USBEndpointStatus() call. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointStatusClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // If this is endpoint 0, then the bits have different meaning and map + // into the TX memory location. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Set the Serviced RxPktRdy bit to clear the RxPktRdy. + // + if(ui32Flags & USB_DEV_EP0_OUT_PKTRDY) + { + HWREGB(ui32Base + USB_O_CSRL0) |= USB_CSRL0_RXRDYC; + } + + // + // Set the serviced Setup End bit to clear the SetupEnd status. + // + if(ui32Flags & USB_DEV_EP0_SETUP_END) + { + HWREGB(ui32Base + USB_O_CSRL0) |= USB_CSRL0_SETENDC; + } + + // + // Clear the Sent Stall status flag. + // + if(ui32Flags & USB_DEV_EP0_SENT_STALL) + { + HWREGB(ui32Base + USB_O_CSRL0) &= ~(USB_DEV_EP0_SENT_STALL); + } + } + else + { + // + // Clear out any TX flags that were passed in. Only + // USB_DEV_TX_SENT_STALL and USB_DEV_TX_UNDERRUN must be cleared. + // + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(ui32Flags & (USB_DEV_TX_SENT_STALL | USB_DEV_TX_UNDERRUN)); + + // + // Clear out valid RX flags that were passed in. Only + // USB_DEV_RX_SENT_STALL, USB_DEV_RX_DATA_ERROR, and USB_DEV_RX_OVERRUN + // must be cleared. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~((ui32Flags & (USB_DEV_RX_SENT_STALL | USB_DEV_RX_DATA_ERROR | + USB_DEV_RX_OVERRUN)) >> USB_RX_EPSTATUS_SHIFT); + } +} + +//***************************************************************************** +// +//! Sets the value data toggle on an endpoint in host mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies the endpoint to reset the data toggle. +//! \param bDataToggle specifies whether to set the state to DATA0 or DATA1. +//! \param ui32Flags specifies whether to set the IN or OUT endpoint. +//! +//! This function is used to force the state of the data toggle in host mode. +//! If the value passed in the \e bDataToggle parameter is \b false, then the +//! data toggle is set to the DATA0 state, and if it is \b true it is set to +//! the DATA1 state. The \e ui32Flags parameter can be \b USB_EP_HOST_IN or +//! \b USB_EP_HOST_OUT to access the desired portion of this endpoint. The +//! \e ui32Flags parameter is ignored for endpoint zero. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostEndpointDataToggle(uint32_t ui32Base, uint32_t ui32Endpoint, + bool bDataToggle, uint32_t ui32Flags) +{ + uint32_t ui32DataToggle; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // The data toggle defaults to DATA0. + // + ui32DataToggle = 0; + + // + // See if the data toggle must be set to DATA1. + // + if(bDataToggle) + { + // + // Select the data toggle bit based on the endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + ui32DataToggle = USB_CSRH0_DT; + } + else if(ui32Flags == USB_EP_HOST_IN) + { + ui32DataToggle = USB_RXCSRH1_DT; + } + else + { + ui32DataToggle = USB_TXCSRH1_DT; + } + } + + // + // Set the data toggle based on the endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Set the write enable and the bit value for endpoint zero. + // + HWREGB(ui32Base + USB_O_CSRH0) = + ((HWREGB(ui32Base + USB_O_CSRH0) & + ~(USB_CSRH0_DTWE | USB_CSRH0_DT)) | + (ui32DataToggle | USB_CSRH0_DTWE)); + } + else if(ui32Flags == USB_EP_HOST_IN) + { + // + // Set the Write enable and the bit value for an IN endpoint. + // + HWREGB(ui32Base + USB_O_RXCSRH1 + EP_OFFSET(ui32Endpoint)) = + ((HWREGB(ui32Base + USB_O_RXCSRH1 + EP_OFFSET(ui32Endpoint)) & + ~(USB_RXCSRH1_DTWE | USB_RXCSRH1_DT)) | + (ui32DataToggle | USB_RXCSRH1_DTWE)); + } + else + { + // + // Set the Write enable and the bit value for an OUT endpoint. + // + HWREGB(ui32Base + USB_O_TXCSRH1 + EP_OFFSET(ui32Endpoint)) = + ((HWREGB(ui32Base + USB_O_TXCSRH1 + EP_OFFSET(ui32Endpoint)) & + ~(USB_TXCSRH1_DTWE | USB_TXCSRH1_DT)) | + (ui32DataToggle | USB_TXCSRH1_DTWE)); + } +} + +//***************************************************************************** +// +//! Sets the data toggle on an endpoint to zero. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies the endpoint to reset the data toggle. +//! \param ui32Flags specifies whether to access the IN or OUT endpoint. +//! +//! This function causes the USB controller to clear the data toggle for an +//! endpoint. This call is not valid for endpoint zero and can be made with +//! host or device controllers. +//! +//! The \e ui32Flags parameter must be one of \b USB_EP_HOST_OUT, +//! \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN. +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointDataToggleClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7)); + + // + // See if the transmit or receive data toggle must be cleared. + // + if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_TXCSRL1_CLRDT; + } + else + { + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_RXCSRL1_CLRDT; + } +} + +//***************************************************************************** +// +//! Enables or disables ping tokens for an endpoint using high-speed control +//! transfers in host mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies the endpoint to enable/disable ping tokens. +//! \param bEnable specifies whether enable or disable ping tokens. +//! +//! This function configures the USB controller to either send or not send ping +//! tokens during the data and status phase of high speed control transfers. +//! The only supported value for \e ui32Endpoint is \b USB_EP_0 because all +//! control transfers are handled using this endpoint. If the \e bEnable is +//! \b true then ping tokens are enabled, if \b false then ping tokens are +//! disabled. This must be used if the controller must support +//! communications with devices that do not support ping tokens in high speed +//! mode. +//! +//! \b Example: Disable ping transactions in host mode on endpoint 0. +//! +//! \verbatim +//! // +//! // Disable ping transaction on endpoint 0. +//! // +//! USBHostEndpointPing(USB0_BASE, USB_EP_0, false); +//! \endverbatim +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostEndpointPing(uint32_t ui32Base, uint32_t ui32Endpoint, bool bEnable) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0)); + + // + // Handle the endpoint 0 case separately. + // + if(bEnable) + { + HWREGB(USB0_BASE + USB_O_CSRH0) &= ~USB_CSRH0_DISPING; + } + else + { + HWREGB(USB0_BASE + USB_O_CSRH0) |= USB_CSRH0_DISPING; + } +} + +//***************************************************************************** +// +//! Stalls the specified endpoint in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies the endpoint to stall. +//! \param ui32Flags specifies whether to stall the IN or OUT endpoint. +//! +//! This function causes the endpoint number passed in to go into a stall +//! condition. If the \e ui32Flags parameter is \b USB_EP_DEV_IN, then the +//! stall is issued on the IN portion of this endpoint. If the \e ui32Flags +//! parameter is \b USB_EP_DEV_OUT, then the stall is issued on the OUT portion +//! of this endpoint. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointStall(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Flags & ~(USB_EP_DEV_IN | USB_EP_DEV_OUT)) == 0); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // Determine how to stall this endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Perform a stall on endpoint zero. + // + HWREGB(ui32Base + USB_O_CSRL0) |= USB_CSRL0_STALL | USB_CSRL0_RXRDYC; + } + else if(ui32Flags == USB_EP_DEV_IN) + { + // + // Perform a stall on an IN endpoint. + // + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_TXCSRL1_STALL; + } + else + { + // + // Perform a stall on an OUT endpoint. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_RXCSRL1_STALL; + } +} + +//***************************************************************************** +// +//! Clears the stall condition on the specified endpoint in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies which endpoint to remove the stall condition. +//! \param ui32Flags specifies whether to remove the stall condition from the +//! IN or the OUT portion of this endpoint. +//! +//! This function causes the endpoint number passed in to exit the stall +//! condition. If the \e ui32Flags parameter is \b USB_EP_DEV_IN, then the +//! stall is cleared on the IN portion of this endpoint. If the \e ui32Flags +//! parameter is \b USB_EP_DEV_OUT, then the stall is cleared on the OUT +//! portion of this endpoint. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointStallClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + ASSERT((ui32Flags & ~(USB_EP_DEV_IN | USB_EP_DEV_OUT)) == 0); + + // + // Determine how to clear the stall on this endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Clear the stall on endpoint zero. + // + HWREGB(ui32Base + USB_O_CSRL0) &= ~USB_CSRL0_STALLED; + } + else if(ui32Flags == USB_EP_DEV_IN) + { + // + // Clear the stall on an IN endpoint. + // + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(USB_TXCSRL1_STALL | USB_TXCSRL1_STALLED); + + // + // Reset the data toggle. + // + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_TXCSRL1_CLRDT; + } + else + { + // + // Clear the stall on an OUT endpoint. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(USB_RXCSRL1_STALL | USB_RXCSRL1_STALLED); + + // + // Reset the data toggle. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_RXCSRL1_CLRDT; + } +} + +//***************************************************************************** +// +//! Connects the USB controller to the bus in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function causes the soft connect feature of the USB controller to +//! be enabled. Call USBDevDisconnect() to remove the USB device from the bus. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevConnect(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Enable connection to the USB bus. + // + HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_SOFTCONN; +} + +//***************************************************************************** +// +//! Removes the USB controller from the bus in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function causes the soft connect feature of the USB controller to +//! remove the device from the USB bus. A call to USBDevConnect() is needed to +//! reconnect to the bus. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevDisconnect(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Disable connection to the USB bus. + // + HWREGB(ui32Base + USB_O_POWER) &= (~USB_POWER_SOFTCONN); +} + +//***************************************************************************** +// +//! Sets the address in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Address is the address to use for a device. +//! +//! This function configures the device address on the USB bus. This address +//! was likely received via a SET ADDRESS command from the host controller. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevAddrSet(uint32_t ui32Base, uint32_t ui32Address) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Set the function address in the correct location. + // + HWREGB(ui32Base + USB_O_FADDR) = (uint8_t)ui32Address; +} + +//***************************************************************************** +// +//! Returns the current device address in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the current device address. This address was set +//! by a call to USBDevAddrSet(). +//! +//! \note This function must only be called in device mode. +//! +//! \return The current device address. +// +//***************************************************************************** +uint32_t +USBDevAddrGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Return the function address. + // + return(HWREGB(ui32Base + USB_O_FADDR)); +} + +//***************************************************************************** +// +//! Sets the base configuration for a host endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32MaxPayload is the maximum payload for this endpoint. +//! \param ui32NAKPollInterval is the either the NAK timeout limit or the +//! polling interval, depending on the type of endpoint. +//! \param ui32TargetEndpoint is the endpoint that the host endpoint is +//! targeting. +//! \param ui32Flags are used to configure other endpoint settings. +//! +//! This function sets the basic configuration for the transmit or receive +//! portion of an endpoint in host mode. The \e ui32Flags parameter determines +//! some of the configuration while the other parameters provide the rest. The +//! \e ui32Flags parameter determines whether this is an IN endpoint +//! (\b USB_EP_HOST_IN or \b USB_EP_DEV_IN) or an OUT endpoint +//! (\b USB_EP_HOST_OUT or \b USB_EP_DEV_OUT), whether this is a Full speed +//! endpoint (\b USB_EP_SPEED_FULL) or a Low speed endpoint +//! (\b USB_EP_SPEED_LOW). +//! +//! The \b USB_EP_MODE_ flags control the type of the endpoint. +//! - \b USB_EP_MODE_CTRL is a control endpoint. +//! - \b USB_EP_MODE_ISOC is an isochronous endpoint. +//! - \b USB_EP_MODE_BULK is a bulk endpoint. +//! - \b USB_EP_MODE_INT is an interrupt endpoint. +//! +//! The \e ui32NAKPollInterval parameter has different meanings based on the +//! \b USB_EP_MODE value and whether or not this call is being made for +//! endpoint zero or another endpoint. For endpoint zero or any Bulk +//! endpoints, this value always indicates the number of frames to allow a +//! device to NAK before considering it a timeout. If this endpoint is an +//! isochronous or interrupt endpoint, this value is the polling interval for +//! this endpoint. +//! +//! For interrupt endpoints, the polling interval is the number of frames +//! between interrupt IN requests to an endpoint and has a range of 1 to 255. +//! For isochronous endpoints this value represents a polling interval of +//! 2 ^ (\e ui32NAKPollInterval - 1) frames. When used as a NAK timeout, the +//! \e ui32NAKPollInterval value specifies 2 ^ (\e ui32NAKPollInterval - 1) +//! frames before issuing a time out. +//! +//! There are two special time out values that can be specified when setting +//! the \e ui32NAKPollInterval value. The first is \b MAX_NAK_LIMIT, which is +//! the maximum value that can be passed in this variable. The other is +//! \b DISABLE_NAK_LIMIT, which indicates that there is no limit on the +//! number of NAKs. +//! +//! The \b USB_EP_DMA_MODE_ flags determine the type of DMA access to the +//! endpoint data FIFOs. The choice of the DMA mode depends on how the DMA +//! controller is configured and how it is being used. See the ``Using USB +//! with the uDMA Controller'' or the ''Using the integrated USB DMA +//! Controller'' section for more information on DMA configuration depending +//! on the type of DMA that is supported by the USB controller. +//! +//! When configuring the OUT portion of an endpoint, the \b USB_EP_AUTO_SET bit +//! is specified to cause the transmission of data on the USB bus to start +//! as soon as the number of bytes specified by \e ui32MaxPayload has been +//! written into the OUT FIFO for this endpoint. +//! +//! When configuring the IN portion of an endpoint, the \b USB_EP_AUTO_REQUEST +//! bit can be specified to trigger the request for more data once the FIFO has +//! been drained enough to fit \e ui32MaxPayload bytes. The +//! \b USB_EP_AUTO_CLEAR bit can be used to clear the data packet ready flag +//! automatically once the data has been read from the FIFO. If this option is +//! not used, this flag must be manually cleared via a call to +//! USBDevEndpointStatusClear() or USBHostEndpointStatusClear(). +//! +//! For interrupt endpoints in low or full speed mode, the polling interval +//! (\e ui32NAKPollInterval) is the number of frames between interrupt IN +//! requests to an endpoint and has a range of 1 to 255. For interrupt +//! endpoints in high speed mode the polling interval is +//! 2 ^ (\e ui32NAKPollInterval - 1) microframes between interrupt IN requests +//! to an endpoint and has a range of 1 to 16. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostEndpointConfig(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32MaxPayload, uint32_t ui32NAKPollInterval, + uint32_t ui32TargetEndpoint, uint32_t ui32Flags) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + ASSERT(ui32NAKPollInterval <= MAX_NAK_LIMIT); + + // + // Endpoint zero is configured differently than the other endpoints, so see + // if this is endpoint zero. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Set the NAK timeout. + // + HWREGB(ui32Base + USB_O_NAKLMT) = ui32NAKPollInterval; + + // + // Set the transfer type information. + // + // + // Set the speed of this endpoint. + // + if(ui32Flags & USB_EP_SPEED_HIGH) + { + HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_HIGH; + } + else if(ui32Flags & USB_EP_SPEED_FULL) + { + HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_FULL; + } + else + { + HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_LOW; + } + } + else + { + // + // Start with the target endpoint. + // + ui32Register = ui32TargetEndpoint; + + // + // Set the speed for the device using this endpoint. + // + if(ui32Flags & USB_EP_SPEED_HIGH) + { + ui32Register |= USB_TXTYPE1_SPEED_HIGH; + } + else if(ui32Flags & USB_EP_SPEED_FULL) + { + ui32Register |= USB_TXTYPE1_SPEED_FULL; + } + else + { + ui32Register |= USB_TXTYPE1_SPEED_LOW; + } + + // + // Set the protocol for the device using this endpoint. + // + switch(ui32Flags & USB_EP_MODE_MASK) + { + // + // The bulk protocol is being used. + // + case USB_EP_MODE_BULK: + { + ui32Register |= USB_TXTYPE1_PROTO_BULK; + break; + } + + // + // The isochronous protocol is being used. + // + case USB_EP_MODE_ISOC: + { + ui32Register |= USB_TXTYPE1_PROTO_ISOC; + break; + } + + // + // The interrupt protocol is being used. + // + case USB_EP_MODE_INT: + { + ui32Register |= USB_TXTYPE1_PROTO_INT; + break; + } + + // + // The control protocol is being used. + // + case USB_EP_MODE_CTRL: + { + ui32Register |= USB_TXTYPE1_PROTO_CTRL; + break; + } + } + + // + // See if the transmit or receive endpoint is being configured. + // + if(ui32Flags & USB_EP_HOST_OUT) + { + // + // Set the transfer type information. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXTYPE1) = + ui32Register; + + // + // Set the NAK timeout or polling interval. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXINTERVAL1) = + ui32NAKPollInterval; + + // + // Set the Maximum Payload per transaction. + // + HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXMAXP1) = + ui32MaxPayload; + + // + // Set the transmit control value to zero. + // + ui32Register = 0; + + // + // Allow auto setting of TxPktRdy when max packet size has been + // loaded into the FIFO. + // + if(ui32Flags & USB_EP_AUTO_SET) + { + ui32Register |= USB_TXCSRH1_AUTOSET; + } + + // + // Configure the DMA Mode. + // + if(ui32Flags & USB_EP_DMA_MODE_1) + { + ui32Register |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD; + } + else if(ui32Flags & USB_EP_DMA_MODE_0) + { + ui32Register |= USB_TXCSRH1_DMAEN; + } + + // + // Write out the transmit control value. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) = + (uint8_t)ui32Register; + } + else + { + // + // Set the transfer type information. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXTYPE1) = + ui32Register; + + // + // Set the NAK timeout or polling interval. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXINTERVAL1) = + ui32NAKPollInterval; + + // + // Set the Maximum Payload per transaction. + // + HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXMAXP1) = + ui32MaxPayload; + + // + // Set the receive control value to zero. + // + ui32Register = 0; + + // + // Allow auto clearing of RxPktRdy when packet of size max packet + // has been unloaded from the FIFO. + // + if(ui32Flags & USB_EP_AUTO_CLEAR) + { + ui32Register |= USB_RXCSRH1_AUTOCL; + } + + // + // Allow auto generation of DMA requests. + // + if(ui32Flags & USB_EP_AUTO_REQUEST) + { + ui32Register |= USB_RXCSRH1_AUTORQ; + } + + // + // Configure the DMA Mode. + // + if(ui32Flags & USB_EP_DMA_MODE_1) + { + ui32Register |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD; + } + else if(ui32Flags & USB_EP_DMA_MODE_0) + { + ui32Register |= USB_RXCSRH1_DMAEN; + } + + // + // Write out the receive control value. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) = + (uint8_t)ui32Register; + } + } +} + +//***************************************************************************** +// +//! Changes the speed of the connection for a host endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags are used to configure other endpoint settings. +//! +//! This function sets the USB speed for an IN or OUT endpoint in host mode. +//! The \e ui32Flags parameter specifies the speed using one of the following +//! values: \b USB_EP_SPEED_LOW, \b USB_EP_SPEED_FULL, or \b USB_EP_SPEED_HIGH. +//! The \e ui32Flags parameter also specifies which direction is set by +//! adding the logical OR in either \b USB_EP_HOST_IN or \b USB_EP_HOST_OUT. +//! All other flags are ignored. This function is typically only used for +//! endpoint 0, but could be used with other endpoints as well. +//! +//! \b Example: Set host transactions on endpoint 0 to full speed.. +//! +//! \verbatim +//! // +//! // Set host endpoint 0 transactions to full speed. +//! // +//! USBHostEndpointSpeed(USB0_BASE, USB_EP_0, USB_EP_SPEED_FULL); +//! \endverbatim +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostEndpointSpeed(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + uint32_t ui32Reg; + uint32_t ui32Speed; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // Create the register speed value. + // + if(ui32Flags & USB_EP_SPEED_HIGH) + { + ui32Speed = USB_TYPE0_SPEED_HIGH; + } + else if(ui32Flags & USB_EP_SPEED_FULL) + { + ui32Speed = USB_TYPE0_SPEED_FULL; + } + else + { + ui32Speed = USB_TYPE0_SPEED_LOW; + } + + // + // Endpoint 0 is handled differently as it is bi-directional. + // + if(ui32Endpoint == USB_EP_0) + { + HWREGB(ui32Base + USB_O_TYPE0) = ui32Speed; + } + else if(ui32Flags & USB_EP_HOST_OUT) + { + // + // Clear the current speed and set the new speed. + // + ui32Reg = (HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXTYPE1) & + ~(USB_TXTYPE1_SPEED_M)); + ui32Reg |= ui32Speed; + + HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXTYPE1) |= ui32Reg; + } + else + { + // + // Clear the current speed and set the new speed. + // + ui32Reg = (HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXTYPE1) & + ~(USB_RXTYPE1_SPEED_M)); + ui32Reg |= ui32Speed; + + HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXTYPE1) |= ui32Reg; + } +} + +//***************************************************************************** +// +//! Sets the configuration for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32MaxPacketSize is the maximum packet size for this endpoint. +//! \param ui32Flags are used to configure other endpoint settings. +//! +//! This function sets the basic configuration for an endpoint in device mode. +//! Endpoint zero does not have a dynamic configuration, so this function +//! must not be called for endpoint zero. The \e ui32Flags parameter +//! determines some of the configuration while the other parameters provide the +//! rest. +//! +//! The \b USB_EP_MODE_ flags define what the type is for the specified endpoint. +//! +//! - \b USB_EP_MODE_CTRL is a control endpoint. +//! - \b USB_EP_MODE_ISOC is an isochronous endpoint. +//! - \b USB_EP_MODE_BULK is a bulk endpoint. +//! - \b USB_EP_MODE_INT is an interrupt endpoint. +//! +//! The \b USB_EP_DMA_MODE_ flags determine the type of DMA access to the +//! endpoint data FIFOs. The choice of the DMA mode depends on how the DMA +//! controller is configured and how it is being used. See the ``Using USB +//! with the uDMA Controller'' or the ''Using the integrated USB DMA +//! Controller'' section for more information on DMA configuration depending +//! on the type of DMA that is supported by the USB controller. +//! +//! When configuring an IN endpoint, the \b USB_EP_AUTO_SET bit can be +//! specified to cause the automatic transmission of data on the USB bus as +//! soon as \e ui32MaxPacketSize bytes of data are written into the FIFO for +//! this endpoint. This option is commonly used with DMA (both on devices +//! with integrated USB DMA as well as those that use uDMA) as no interaction +//! is required to start the transmission of data. +//! +//! When configuring an OUT endpoint, the \b USB_EP_AUTO_REQUEST bit is +//! specified to trigger the request for more data once the FIFO has been +//! drained enough to receive \e ui32MaxPacketSize more bytes of data. Also +//! for OUT endpoints, the \b USB_EP_AUTO_CLEAR bit can be used to clear the +//! data packet ready flag automatically once the data has been read from the +//! FIFO. If this option is not used, this flag must be manually cleared via a +//! call to USBDevEndpointStatusClear(). Both of these settings can be used to +//! remove the need for extra calls when using the controller with DMA. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32MaxPacketSize, uint32_t ui32Flags) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7)); + + // + // Determine if a transmit or receive endpoint is being configured. + // + if(ui32Flags & USB_EP_DEV_IN) + { + // + // Set the maximum packet size. + // + HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXMAXP1) = + ui32MaxPacketSize; + + // + // The transmit control value is zero unless options are enabled. + // + ui32Register = 0; + + // + // Allow auto setting of TxPktRdy when max packet size has been loaded + // into the FIFO. + // + if(ui32Flags & USB_EP_AUTO_SET) + { + ui32Register |= USB_TXCSRH1_AUTOSET; + } + + // + // Configure the DMA mode. + // + if(ui32Flags & USB_EP_DMA_MODE_1) + { + ui32Register |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD; + } + else if(ui32Flags & USB_EP_DMA_MODE_0) + { + ui32Register |= USB_TXCSRH1_DMAEN; + } + + // + // Enable isochronous mode if requested. + // + if((ui32Flags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC) + { + ui32Register |= USB_TXCSRH1_ISO; + } + + // + // Write the transmit control value. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) = + (uint8_t)ui32Register; + + // + // Reset the Data toggle to zero. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRL1) = + USB_TXCSRL1_CLRDT; + } + else + { + // + // Set the MaxPacketSize. + // + HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXMAXP1) = + ui32MaxPacketSize; + + // + // The receive control value is zero unless options are enabled. + // + ui32Register = 0; + + // + // Allow auto clearing of RxPktRdy when packet of size max packet + // has been unloaded from the FIFO. + // + if(ui32Flags & USB_EP_AUTO_CLEAR) + { + ui32Register = USB_RXCSRH1_AUTOCL; + } + + // + // Configure the DMA mode. + // + if(ui32Flags & USB_EP_DMA_MODE_1) + { + ui32Register |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD; + } + else if(ui32Flags & USB_EP_DMA_MODE_0) + { + ui32Register |= USB_RXCSRH1_DMAEN; + } + + // + // If requested, disable NYET responses for high-speed bulk and + // interrupt endpoints. + // + if(ui32Flags & USB_EP_DIS_NYET) + { + ui32Register |= USB_RXCSRH1_DISNYET; + } + + // + // Enable isochronous mode if requested. + // + if((ui32Flags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC) + { + ui32Register |= USB_RXCSRH1_ISO; + } + + // + // Write the receive control value. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) = + (uint8_t)ui32Register; + + // + // Reset the Data toggle to zero. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRL1) = + USB_RXCSRL1_CLRDT; + } +} + +//***************************************************************************** +// +//! Gets the current configuration for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param pui32MaxPacketSize is a pointer which is written with the maximum +//! packet size for this endpoint. +//! \param pui32Flags is a pointer which is written with the current endpoint +//! settings. On entry to the function, this pointer must contain either +//! \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT to indicate whether the IN or OUT +//! endpoint is to be queried. +//! +//! This function returns the basic configuration for an endpoint in device +//! mode. The values returned in \e *pui32MaxPacketSize and \e *pui32Flags are +//! equivalent to the \e ui32MaxPacketSize and \e ui32Flags previously passed +//! to USBDevEndpointConfigSet() for this endpoint. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t *pui32MaxPacketSize, uint32_t *pui32Flags) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT(pui32MaxPacketSize && pui32Flags); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7)); + + // + // Determine if a transmit or receive endpoint is being queried. + // + if(*pui32Flags & USB_EP_DEV_IN) + { + // + // Clear the flags other than the direction bit. + // + *pui32Flags = USB_EP_DEV_IN; + + // + // Get the maximum packet size. + // + *pui32MaxPacketSize = (uint32_t)HWREGH(ui32Base + + EP_OFFSET(ui32Endpoint) + + USB_O_TXMAXP1); + + // + // Get the current transmit control register value. + // + ui32Register = (uint32_t)HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + + USB_O_TXCSRH1); + + // + // Are we allowing auto setting of TxPktRdy when max packet size has + // been loaded into the FIFO? + // + if(ui32Register & USB_TXCSRH1_AUTOSET) + { + *pui32Flags |= USB_EP_AUTO_SET; + } + + // + // Get the DMA mode. + // + if(ui32Register & USB_TXCSRH1_DMAEN) + { + if(ui32Register & USB_TXCSRH1_DMAMOD) + { + *pui32Flags |= USB_EP_DMA_MODE_1; + } + else + { + *pui32Flags |= USB_EP_DMA_MODE_0; + } + } + + // + // Are we in isochronous mode? + // + if(ui32Register & USB_TXCSRH1_ISO) + { + *pui32Flags |= USB_EP_MODE_ISOC; + } + else + { + // + // The hardware doesn't differentiate between bulk, interrupt + // and control mode for the endpoint so we just set something + // that isn't isochronous. This protocol ensures that anyone + // modifying the returned flags in preparation for a call to + // USBDevEndpointConfigSet do not see an unexpected mode change. + // If they decode the returned mode, however, they may be in for + // a surprise. + // + *pui32Flags |= USB_EP_MODE_BULK; + } + } + else + { + // + // Clear the flags other than the direction bit. + // + *pui32Flags = USB_EP_DEV_OUT; + + // + // Get the MaxPacketSize. + // + *pui32MaxPacketSize = (uint32_t)HWREGH(ui32Base + + EP_OFFSET(ui32Endpoint) + + USB_O_RXMAXP1); + + // + // Get the current receive control register value. + // + ui32Register = (uint32_t)HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + + USB_O_RXCSRH1); + + // + // Are we allowing auto clearing of RxPktRdy when packet of size max + // packet has been unloaded from the FIFO? + // + if(ui32Register & USB_RXCSRH1_AUTOCL) + { + *pui32Flags |= USB_EP_AUTO_CLEAR; + } + + // + // Get the DMA mode. + // + if(ui32Register & USB_RXCSRH1_DMAEN) + { + if(ui32Register & USB_RXCSRH1_DMAMOD) + { + *pui32Flags |= USB_EP_DMA_MODE_1; + } + else + { + *pui32Flags |= USB_EP_DMA_MODE_0; + } + } + + // + // Are we in isochronous mode? + // + if(ui32Register & USB_RXCSRH1_ISO) + { + *pui32Flags |= USB_EP_MODE_ISOC; + } + else + { + // + // The hardware doesn't differentiate between bulk, interrupt + // and control mode for the endpoint so we just set something + // that isn't isochronous. This protocol ensures that anyone + // modifying the returned flags in preparation for a call to + // USBDevEndpointConfigSet do not see an unexpected mode change. + // If they decode the returned mode, however, they may be in for + // a surprise. + // + *pui32Flags |= USB_EP_MODE_BULK; + } + } +} + +//***************************************************************************** +// +//! Sets the FIFO configuration for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32FIFOAddress is the starting address for the FIFO. +//! \param ui32FIFOSize is the size of the FIFO specified by one of the +//! \b USB_FIFO_SZ_ values. +//! \param ui32Flags specifies what information to set in the FIFO +//! configuration. +//! +//! This function configures the starting FIFO RAM address and size of the FIFO +//! for a specified endpoint. Endpoint zero does not have a dynamically +//! configurable FIFO, so this function must not be called for endpoint zero. +//! The \e ui32FIFOSize parameter must be one of the values in the +//! \b USB_FIFO_SZ_ values. +//! +//! The \e ui32FIFOAddress value must be a multiple of 8 bytes and directly +//! indicates the starting address in the USB controller's FIFO RAM. For +//! example, a value of 64 indicates that the FIFO starts 64 bytes into +//! the USB controller's FIFO memory. The \e ui32Flags value specifies whether +//! the endpoint's OUT or IN FIFO must be configured. If in host mode, use +//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode, use +//! \b USB_EP_DEV_OUT or \b USB_EP_DEV_IN. +//! +//! \return None. +// +//***************************************************************************** +void +USBFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32FIFOAddress, uint32_t ui32FIFOSize, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7)); + + // + // See if the transmit or receive FIFO is being configured. + // + if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + // + // Set the transmit FIFO location and size for this endpoint. + // + _USBIndexWrite(ui32Base, ui32Endpoint >> 4, USB_O_TXFIFOSZ, + ui32FIFOSize, 1); + _USBIndexWrite(ui32Base, ui32Endpoint >> 4, USB_O_TXFIFOADD, + ui32FIFOAddress >> 3, 2); + } + else + { + // + // Set the receive FIFO location and size for this endpoint. + // + _USBIndexWrite(ui32Base, ui32Endpoint >> 4, USB_O_RXFIFOSZ, + ui32FIFOSize, 1); + _USBIndexWrite(ui32Base, ui32Endpoint >> 4, USB_O_RXFIFOADD, + ui32FIFOAddress >> 3, 2); + } +} + +//***************************************************************************** +// +//! Returns the FIFO configuration for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param pui32FIFOAddress is the starting address for the FIFO. +//! \param pui32FIFOSize is the size of the FIFO as specified by one of the +//! \b USB_FIFO_SZ_ values. +//! \param ui32Flags specifies what information to retrieve from the FIFO +//! configuration. +//! +//! This function returns the starting address and size of the FIFO for a +//! specified endpoint. Endpoint zero does not have a dynamically configurable +//! FIFO, so this function must not be called for endpoint zero. The +//! \e ui32Flags parameter specifies whether the endpoint's OUT or IN FIFO must +//! be read. If in host mode, the \e ui32Flags parameter must be +//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode, the +//! \e ui32Flags parameter must be either \b USB_EP_DEV_OUT or +//! \b USB_EP_DEV_IN. +//! +//! \return None. +// +//***************************************************************************** +void +USBFIFOConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t *pui32FIFOAddress, uint32_t *pui32FIFOSize, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7)); + + // + // See if the transmit or receive FIFO is being configured. + // + if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + // + // Get the transmit FIFO location and size for this endpoint. + // + *pui32FIFOAddress = (_USBIndexRead(ui32Base, ui32Endpoint >> 4, + (uint32_t)USB_O_TXFIFOADD, + 2)) << 3; + *pui32FIFOSize = _USBIndexRead(ui32Base, ui32Endpoint >> 4, + (uint32_t)USB_O_TXFIFOSZ, 1); + } + else + { + // + // Get the receive FIFO location and size for this endpoint. + // + *pui32FIFOAddress = (_USBIndexRead(ui32Base, ui32Endpoint >> 4, + (uint32_t)USB_O_RXFIFOADD, + 2)) << 3; + *pui32FIFOSize = _USBIndexRead(ui32Base, ui32Endpoint >> 4, + (uint32_t)USB_O_RXFIFOSZ, 1); + } +} + +//***************************************************************************** +// +//! Configure the DMA settings for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Config specifies the configuration options for an endpoint. +//! +//! This function configures the DMA settings for a specified endpoint without +//! changing other options that may already be configured. In order for the +//! DMA transfer to be enabled, the USBEndpointDMAEnable() function must be +//! called before starting the DMA transfer. The configuration +//! options are passed in the \e ui32Config parameter and can have the values +//! described below. +//! +//! One of the following values to specify direction: +//! - \b USB_EP_HOST_OUT or \b USB_EP_DEV_IN - This setting is used with +//! DMA transfers from memory to the USB controller. +//! - \b USB_EP_HOST_IN or \b USB_EP_DEV_OUT - This setting is used with +//! DMA transfers from the USB controller to memory. +//! +//! One of the following values: +//! - \b USB_EP_DMA_MODE_0(default) - This setting is typically used for +//! transfers that do not span multiple packets or when interrupts are +//! required for each packet. +//! - \b USB_EP_DMA_MODE_1 - This setting is typically used for +//! transfers that span multiple packets and do not require interrupts +//! between packets. +//! +//! Values only used with \b USB_EP_HOST_OUT or \b USB_EP_DEV_IN: +//! - \b USB_EP_AUTO_SET - This setting is used to allow transmit DMA transfers +//! to automatically be sent when a full packet is loaded into a FIFO. +//! This is needed with \b USB_EP_DMA_MODE_1 to ensure that packets go +//! out when the FIFO becomes full and the DMA has more data to send. +//! +//! Values only used with \b USB_EP_HOST_IN or \b USB_EP_DEV_OUT: +//! - \b USB_EP_AUTO_CLEAR - This setting is used to allow receive DMA +//! transfers to automatically be acknowledged as they are received. This is +//! needed with \b USB_EP_DMA_MODE_1 to ensure that packets continue to +//! be received and acknowledged when the FIFO is emptied by the DMA +//! transfer. +//! +//! Values only used with \b USB_EP_HOST_IN: +//! - \b USB_EP_AUTO_REQUEST - This setting is used to allow receive DMA +//! transfers to automatically request a new IN transaction when the +//! previous transfer has emptied the FIFO. This is typically used in +//! conjunction with \b USB_EP_AUTO_CLEAR so that receive DMA transfers +//! can continue without interrupting the main processor. +//! +//! \b Example: Set endpoint 1 receive endpoint to automatically acknowledge +//! request and automatically generate a new IN request in host mode. +//! +//! \verbatim +//! // +//! // Configure endpoint 1 for receiving multiple packets using DMA. +//! // +//! USBEndpointDMAConfigSet(USB0_BASE, USB_EP_1, USB_EP_HOST_IN | +//! USB_EP_DMA_MODE_1 | +//! USB_EP_AUTO_CLEAR | +//! USB_EP_AUTO_REQUEST); +//! \endverbatim +//! +//! \b Example: Set endpoint 2 transmit endpoint to automatically send each +//! packet in host mode when spanning multiple packets. +//! +//! \verbatim +//! // +//! // Configure endpoint 1 for transmitting multiple packets using DMA. +//! // +//! USBEndpointDMAConfigSet(USB0_BASE, USB_EP_2, USB_EP_HOST_OUT | +//! USB_EP_DMA_MODE_1 | +//! USB_EP_AUTO_SET); +//! \endverbatim +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointDMAConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Config) +{ + uint32_t ui32NewConfig; + + if(ui32Config & USB_EP_HOST_OUT) + { + // + // Clear mode and DMA enable. + // + ui32NewConfig = + (HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) & + ~(USB_TXCSRH1_DMAMOD | USB_TXCSRH1_AUTOSET)); + + if(ui32Config & USB_EP_DMA_MODE_1) + { + ui32NewConfig |= USB_TXCSRH1_DMAMOD; + } + + if(ui32Config & USB_EP_AUTO_SET) + { + ui32NewConfig |= USB_TXCSRH1_AUTOSET; + } + + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) = + ui32NewConfig; + } + else + { + ui32NewConfig = + (HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) & + ~(USB_RXCSRH1_AUTORQ | USB_RXCSRH1_AUTOCL | USB_RXCSRH1_DMAMOD)); + + if(ui32Config & USB_EP_DMA_MODE_1) + { + ui32NewConfig |= USB_RXCSRH1_DMAMOD; + } + + if(ui32Config & USB_EP_AUTO_CLEAR) + { + ui32NewConfig |= USB_RXCSRH1_AUTOCL; + } + if(ui32Config & USB_EP_AUTO_REQUEST) + { + ui32NewConfig |= USB_RXCSRH1_AUTORQ; + } + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) = + ui32NewConfig; + } +} + +//***************************************************************************** +// +//! Enable DMA on a specified endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags specifies which direction and what mode to use when +//! enabling DMA. +//! +//! This function enables DMA on a specified endpoint and configures the mode +//! according to the values in the \e ui32Flags parameter. The \e ui32Flags +//! parameter must have \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT set. Once this +//! function is called the only DMA or error interrupts are generated by the +//! USB controller. +//! +//! \note If this function is called when an endpoint is configured in DMA +//! mode 0 the USB controller does not generate an interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointDMAEnable(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // See if the transmit DMA is being enabled. + // + if(ui32Flags & USB_EP_DEV_IN) + { + // + // Enable DMA on the transmit endpoint. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) |= + USB_TXCSRH1_DMAEN; + } + else + { + // + // Enable DMA on the receive endpoint. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) |= + USB_RXCSRH1_DMAEN; + } +} + +//***************************************************************************** +// +//! Disable DMA on a specified endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags specifies which direction to disable. +//! +//! This function disables DMA on a specified endpoint to allow non-DMA USB +//! transactions to generate interrupts normally. The \e ui32Flags parameter +//! must be \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT; all other bits are ignored. +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointDMADisable(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // If this was a request to disable DMA on the IN portion of the endpoint + // then handle it. + // + if(ui32Flags & USB_EP_DEV_IN) + { + // + // Just disable DMA leave the mode setting. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) &= + ~USB_TXCSRH1_DMAEN; + } + else + { + // + // Just disable DMA leave the mode setting. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) &= + ~USB_RXCSRH1_DMAEN; + } +} + +//***************************************************************************** +// +//! Determines the number of bytes of data available in a specified endpoint's +//! FIFO. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! +//! This function returns the number of bytes of data currently available in +//! the FIFO for the specified receive (OUT) endpoint. It may be used prior to +//! calling USBEndpointDataGet() to determine the size of buffer required to +//! hold the newly-received packet. +//! +//! \return This call returns the number of bytes available in a specified endpoint +//! FIFO. +// +//***************************************************************************** +uint32_t +USBEndpointDataAvail(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // Get the address of the receive status register to use, based on the + // endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + ui32Register = USB_O_CSRL0; + } + else + { + ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint); + } + + // + // Is there a packet ready in the FIFO? + // + if((HWREGH(ui32Base + ui32Register) & USB_CSRL0_RXRDY) == 0) + { + return(0); + } + + // + // Return the byte count in the FIFO. + // + return(HWREGH(ui32Base + USB_O_COUNT0 + ui32Endpoint)); +} + +//***************************************************************************** +// +//! Retrieves data from the specified endpoint's FIFO. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param pui8Data is a pointer to the data area used to return the data from +//! the FIFO. +//! \param pui32Size is initially the size of the buffer passed into this call +//! via the \e pui8Data parameter. It is set to the amount of data returned in +//! the buffer. +//! +//! This function returns the data from the FIFO for the specified endpoint. +//! The \e pui32Size parameter indicates the size of the buffer passed in +//! the \e pui32Data parameter. The data in the \e pui32Size parameter is +//! changed to match the amount of data returned in the \e pui8Data parameter. +//! If a zero-byte packet is received, this call does not return an error but +//! instead just returns a zero in the \e pui32Size parameter. The only error +//! case occurs when there is no data packet available. +//! +//! \return This call returns 0, or -1 if no packet was received. +// +//***************************************************************************** +int32_t +USBEndpointDataGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint8_t *pui8Data, uint32_t *pui32Size) +{ + uint32_t ui32Register, ui32ByteCount, ui32FIFO; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // Get the address of the receive status register to use, based on the + // endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + ui32Register = USB_O_CSRL0; + } + else + { + ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint); + } + + // + // Don't allow reading of data if the RxPktRdy bit is not set. + // + if((HWREGH(ui32Base + ui32Register) & USB_CSRL0_RXRDY) == 0) + { + // + // Can't read the data because none is available. + // + *pui32Size = 0; + + // + // Return a failure since there is no data to read. + // + return(-1); + } + + // + // Get the byte count in the FIFO. + // + ui32ByteCount = HWREGH(ui32Base + USB_O_COUNT0 + ui32Endpoint); + + // + // Determine how many bytes are copied. + // + ui32ByteCount = (ui32ByteCount < *pui32Size) ? ui32ByteCount : *pui32Size; + + // + // Return the number of bytes we are going to read. + // + *pui32Size = ui32ByteCount; + + // + // Calculate the FIFO address. + // + ui32FIFO = ui32Base + USB_O_FIFO0 + (ui32Endpoint >> 2); + + // + // Read the data out of the FIFO. + // + for(; ui32ByteCount > 0; ui32ByteCount--) + { + // + // Read a byte at a time from the FIFO. + // + *pui8Data++ = HWREGB(ui32FIFO); + } + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Acknowledge that data was read from the specified endpoint's FIFO in device +//! mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param bIsLastPacket indicates if this packet is the last one. +//! +//! This function acknowledges that the data was read from the endpoint's FIFO. +//! The \e bIsLastPacket parameter is set to a \b true value if this is the +//! last in a series of data packets on endpoint zero. The \e bIsLastPacket +//! parameter is not used for endpoints other than endpoint zero. This call +//! can be used if processing is required between reading the data and +//! acknowledging that the data has been read. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint, + bool bIsLastPacket) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // Determine which endpoint is being acked. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Clear RxPktRdy, and optionally DataEnd, on endpoint zero. + // + HWREGB(ui32Base + USB_O_CSRL0) = + USB_CSRL0_RXRDYC | (bIsLastPacket ? USB_CSRL0_DATAEND : 0); + } + else + { + // + // Clear RxPktRdy on all other endpoints. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(USB_RXCSRL1_RXRDY); + } +} + +//***************************************************************************** +// +//! Acknowledge that data was read from the specified endpoint's FIFO in host +//! mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! +//! This function acknowledges that the data was read from the endpoint's FIFO. +//! This call is used if processing is required between reading the data and +//! acknowledging that the data has been read. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // Clear RxPktRdy. + // + if(ui32Endpoint == USB_EP_0) + { + HWREGB(ui32Base + USB_O_CSRL0) &= ~USB_CSRL0_RXRDY; + } + else + { + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(USB_RXCSRL1_RXRDY); + } +} + +//***************************************************************************** +// +//! Puts data into the specified endpoint's FIFO. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param pui8Data is a pointer to the data area used as the source for the +//! data to put into the FIFO. +//! \param ui32Size is the amount of data to put into the FIFO. +//! +//! This function puts the data from the \e pui8Data parameter into the FIFO +//! for this endpoint. If a packet is already pending for transmission, then +//! this call does not put any of the data into the FIFO and returns -1. Care +//! must be taken to not write more data than can fit into the FIFO +//! allocated by the call to USBFIFOConfigSet(). +//! +//! \return This call returns 0 on success, or -1 to indicate that the FIFO +//! is in use and cannot be written. +// +//***************************************************************************** +int32_t +USBEndpointDataPut(uint32_t ui32Base, uint32_t ui32Endpoint, + uint8_t *pui8Data, uint32_t ui32Size) +{ + uint32_t ui32FIFO; + uint8_t ui8TxPktRdy; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // Get the bit position of TxPktRdy based on the endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + ui8TxPktRdy = USB_CSRL0_TXRDY; + } + else + { + ui8TxPktRdy = USB_TXCSRL1_TXRDY; + } + + // + // Don't allow transmit of data if the TxPktRdy bit is already set. + // + if(HWREGB(ui32Base + USB_O_CSRL0 + ui32Endpoint) & ui8TxPktRdy) + { + return(-1); + } + + // + // Calculate the FIFO address. + // + ui32FIFO = ui32Base + USB_O_FIFO0 + (ui32Endpoint >> 2); + + // + // Write the data to the FIFO. + // + for(; ui32Size > 0; ui32Size--) + { + HWREGB(ui32FIFO) = *pui8Data++; + } + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Starts the transfer of data from an endpoint's FIFO. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32TransType is set to indicate what type of data is being sent. +//! +//! This function starts the transfer of data from the FIFO for a specified +//! endpoint. This function is called if the \b USB_EP_AUTO_SET bit was +//! not enabled for the endpoint. Setting the \e ui32TransType parameter +//! allows the appropriate signaling on the USB bus for the type of transaction +//! being requested. The \e ui32TransType parameter must be one of the +//! following: +//! +//! - \b USB_TRANS_OUT for OUT transaction on any endpoint in host mode. +//! - \b USB_TRANS_IN for IN transaction on any endpoint in device mode. +//! - \b USB_TRANS_IN_LAST for the last IN transaction on endpoint zero in a +//! sequence of IN transactions. +//! - \b USB_TRANS_SETUP for setup transactions on endpoint zero. +//! - \b USB_TRANS_STATUS for status results on endpoint zero. +//! +//! \return This call returns 0 on success, or -1 if a transmission is already +//! in progress. +// +//***************************************************************************** +int32_t +USBEndpointDataSend(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32TransType) +{ + uint32_t ui32TxPktRdy; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // Get the bit position of TxPktRdy based on the endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Don't allow transmit of data if the TxPktRdy bit is already set. + // + if(HWREGB(ui32Base + USB_O_CSRL0) & USB_CSRL0_TXRDY) + { + return(-1); + } + + ui32TxPktRdy = ui32TransType & 0xff; + } + else + { + // + // Don't allow transmit of data if the TxPktRdy bit is already set. + // + if(HWREGB(ui32Base + USB_O_CSRL0 + ui32Endpoint) & USB_TXCSRL1_TXRDY) + { + return(-1); + } + + ui32TxPktRdy = (ui32TransType >> 8) & 0xff; + } + + // + // Set TxPktRdy in order to send the data. + // + HWREGB(ui32Base + USB_O_CSRL0 + ui32Endpoint) = ui32TxPktRdy; + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Forces a flush of an endpoint's FIFO. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags specifies if the IN or OUT endpoint is accessed. +//! +//! This function forces the USB controller to flush out the data in the FIFO. +//! The function can be called with either host or device controllers and +//! requires the \e ui32Flags parameter be one of \b USB_EP_HOST_OUT, +//! \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN. +//! +//! \return None. +// +//***************************************************************************** +void +USBFIFOFlush(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // Endpoint zero has a different register set for FIFO flushing. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Nothing in the FIFO if neither of these bits are set. + // + if((HWREGB(ui32Base + USB_O_CSRL0) & + (USB_CSRL0_RXRDY | USB_CSRL0_TXRDY)) != 0) + { + // + // Hit the Flush FIFO bit. + // + HWREGB(ui32Base + USB_O_CSRH0) = USB_CSRH0_FLUSH; + } + } + else + { + // + // Only reset the IN or OUT FIFO. + // + if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + // + // Make sure the FIFO is not empty. + // + if(HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) & + USB_TXCSRL1_TXRDY) + { + // + // Hit the Flush FIFO bit. + // + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_TXCSRL1_FLUSH; + } + } + else + { + // + // Make sure that the FIFO is not empty. + // + if(HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) & + USB_RXCSRL1_RXRDY) + { + // + // Hit the Flush FIFO bit. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_RXCSRL1_FLUSH; + } + } + } +} + +//***************************************************************************** +// +//! Schedules a request for an IN transaction on an endpoint in host mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! +//! This function schedules a request for an IN transaction. When the USB +//! device being communicated with responds with the data, the data can be +//! retrieved by calling USBEndpointDataGet() or via a DMA transfer. +//! +//! \note This function must only be called in host mode and only for IN +//! endpoints. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostRequestIN(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // Endpoint zero uses a different offset than the other endpoints. + // + if(ui32Endpoint == USB_EP_0) + { + ui32Register = USB_O_CSRL0; + } + else + { + ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint); + } + + // + // Set the request for an IN transaction. + // + HWREGB(ui32Base + ui32Register) = USB_RXCSRL1_REQPKT; +} + +//***************************************************************************** +// +//! Clears a scheduled IN transaction for an endpoint in host mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! +//! This function clears a previously scheduled IN transaction if it is still +//! pending. This function is used to safely disable any scheduled IN +//! transactions if the endpoint specified by \e ui32Endpoint is reconfigured +//! for communications with other devices. +//! +//! \note This function must only be called in host mode and only for IN +//! endpoints. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostRequestINClear(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // Endpoint zero uses a different offset than the other endpoints. + // + if(ui32Endpoint == USB_EP_0) + { + ui32Register = USB_O_CSRL0; + } + else + { + ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint); + } + + // + // Clear the request for an IN transaction. + // + HWREGB(ui32Base + ui32Register) &= ~USB_RXCSRL1_REQPKT; +} + +//***************************************************************************** +// +//! Issues a request for a status IN transaction on endpoint zero. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function is used to cause a request for a status IN transaction from +//! a device on endpoint zero. This function can only be used with endpoint +//! zero as that is the only control endpoint that supports this ability. This +//! function is used to complete the last phase of a control transaction to a +//! device and an interrupt is signaled when the status packet has been +//! received. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostRequestStatus(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Set the request for a status IN transaction. + // + HWREGB(ui32Base + USB_O_CSRL0) = USB_CSRL0_REQPKT | USB_CSRL0_STATUS; +} + +//***************************************************************************** +// +//! Sets the functional address for the device that is connected to an +//! endpoint in host mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Addr is the functional address for the controller to use for +//! this endpoint. +//! \param ui32Flags determines if this is an IN or an OUT endpoint. +//! +//! This function configures the functional address for a device that is using +//! this endpoint for communication. This \e ui32Addr parameter is the address +//! of the target device that this endpoint is communicating with. The +//! \e ui32Flags parameter indicates if the IN or OUT endpoint is set. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Addr, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // See if the transmit or receive address is set. + // + if(ui32Flags & USB_EP_HOST_OUT) + { + // + // Set the transmit address. + // + HWREGB(ui32Base + USB_O_TXFUNCADDR0 + (ui32Endpoint >> 1)) = ui32Addr; + } + else + { + // + // Set the receive address. + // + HWREGB(ui32Base + USB_O_TXFUNCADDR0 + 4 + (ui32Endpoint >> 1)) = + ui32Addr; + } +} + +//***************************************************************************** +// +//! Gets the current functional device address for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags determines if this is an IN or an OUT endpoint. +//! +//! This function returns the current functional address that an endpoint is +//! using to communicate with a device. The \e ui32Flags parameter determines +//! if the IN or OUT endpoint's device address is returned. +//! +//! \note This function must only be called in host mode. +//! +//! \return Returns the current function address being used by an endpoint. +// +//***************************************************************************** +uint32_t +USBHostAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // See if the transmit or receive address is returned. + // + if(ui32Flags & USB_EP_HOST_OUT) + { + // + // Return this endpoint's transmit address. + // + return(HWREGB(ui32Base + USB_O_TXFUNCADDR0 + (ui32Endpoint >> 1))); + } + else + { + // + // Return this endpoint's receive address. + // + return(HWREGB(ui32Base + USB_O_TXFUNCADDR0 + 4 + (ui32Endpoint >> 1))); + } +} + +//***************************************************************************** +// +//! Sets the hub address for the device that is connected to an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Addr is the hub address and port for the device using this +//! endpoint. The hub address must be defined in bits 0 through 6 with the +//! port number in bits 8 through 14. +//! \param ui32Flags determines if this is an IN or an OUT endpoint. +//! +//! This function configures the hub address for a device that is using this +//! endpoint for communication. The \e ui32Flags parameter determines if the +//! device address for the IN or the OUT endpoint is configured by this call +//! and sets the speed of the downstream device. Valid values are one of +//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN optionally ORed with +//! \b USB_EP_SPEED_LOW. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostHubAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Addr, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // See if the hub transmit or receive address is being set. + // + if(ui32Flags & USB_EP_HOST_OUT) + { + // + // Set the hub transmit address and port number for this endpoint. + // + HWREGH(ui32Base + USB_O_TXHUBADDR0 + (ui32Endpoint >> 1)) = ui32Addr; + } + else + { + // + // Set the hub receive address and port number for this endpoint. + // + HWREGH(ui32Base + USB_O_TXHUBADDR0 + 4 + (ui32Endpoint >> 1)) = + ui32Addr; + } + + // + // Set the speed of communication for endpoint 0. This configuration is + // done here because it changes on a transaction-by-transaction basis for + // EP0. For other endpoints, this is set in USBHostEndpointConfig(). + // + if(ui32Endpoint == USB_EP_0) + { + if(ui32Flags & USB_EP_SPEED_FULL) + { + HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_FULL; + } + else if(ui32Flags & USB_EP_SPEED_HIGH) + { + HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_HIGH; + } + else + { + HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_LOW; + } + } +} + +//***************************************************************************** +// +//! Gets the current device hub address for this endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags determines if this is an IN or an OUT endpoint. +//! +//! This function returns the current hub address that an endpoint is using +//! to communicate with a device. The \e ui32Flags parameter determines if the +//! device address for the IN or OUT endpoint is returned. +//! +//! \note This function must only be called in host mode. +//! +//! \return This function returns the current hub address being used by an +//! endpoint. +// +//***************************************************************************** +uint32_t +USBHostHubAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // See if the hub transmit or receive address is returned. + // + if(ui32Flags & USB_EP_HOST_OUT) + { + // + // Return the hub transmit address for this endpoint. + // + return(HWREGB(ui32Base + USB_O_TXHUBADDR0 + (ui32Endpoint >> 1))); + } + else + { + // + // Return the hub receive address for this endpoint. + // + return(HWREGB(ui32Base + USB_O_TXHUBADDR0 + 4 + (ui32Endpoint >> 1))); + } +} + +//***************************************************************************** +// +//! Sets the configuration for USB power fault. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Flags specifies the configuration of the power fault. +//! +//! This function controls how the USB controller uses its external power +//! control pins (USBnPFLT and USBnEPEN). The flags specify the power +//! fault level sensitivity, the power fault action, and the power enable level +//! and source. +//! +//! One of the following can be selected as the power fault level sensitivity: +//! +//! - \b USB_HOST_PWRFLT_LOW - An external power fault is indicated by the pin +//! being driven low. +//! - \b USB_HOST_PWRFLT_HIGH - An external power fault is indicated by the pin +//! being driven high. +//! +//! One of the following can be selected as the power fault action: +//! +//! - \b USB_HOST_PWRFLT_EP_NONE - No automatic action when power fault +//! detected. +//! - \b USB_HOST_PWRFLT_EP_TRI - Automatically tri-state the USBnEPEN pin on a +//! power fault. +//! - \b USB_HOST_PWRFLT_EP_LOW - Automatically drive USBnEPEN pin low on a +//! power fault. +//! - \b USB_HOST_PWRFLT_EP_HIGH - Automatically drive USBnEPEN pin high on a +//! power fault. +//! +//! One of the following can be selected as the power enable level and source: +//! +//! - \b USB_HOST_PWREN_MAN_LOW - USBnEPEN is driven low by the USB controller +//! when USBHostPwrEnable() is called. +//! - \b USB_HOST_PWREN_MAN_HIGH - USBnEPEN is driven high by the USB +//! controller when USBHostPwrEnable() is +//! called. +//! - \b USB_HOST_PWREN_AUTOLOW - USBnEPEN is driven low by the USB controller +//! automatically if USBOTGSessionRequest() has +//! enabled a session. +//! - \b USB_HOST_PWREN_AUTOHIGH - USBnEPEN is driven high by the USB +//! controller automatically if +//! USBOTGSessionRequest() has enabled a +//! session. +//! +//! When using the VBUS glitch filter, the \b USB_HOST_PWREN_FILTER can be +//! addded to ignore small, short drops in VBUS level caused by high power +//! consumption. This feature is mainly used to avoid causing VBUS errors +//! caused by devices with high in-rush current. +//! +//! \note This function must only be called on microcontrollers that support +//! host mode or OTG operation. The \b USB_HOST_PWREN_AUTOLOW and +//! \b USB_HOST_PWREN_AUTOHIGH parameters can only be specified on devices that +//! support OTG operation. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrConfig(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Flags & ~(USB_HOST_PWREN_FILTER | USB_EPC_PFLTACT_M | + USB_EPC_PFLTAEN | USB_EPC_PFLTSEN_HIGH | + USB_EPC_EPEN_M)) == 0); + + // + // If requested, enable VBUS droop detection on parts that support this + // feature. + // + HWREG(ui32Base + USB_O_VDC) = ui32Flags >> 16; + + // + // Set the power fault configuration as specified. This configuration + // does not change whether fault detection is enabled or not. + // + HWREGH(ui32Base + USB_O_EPC) = + (ui32Flags | (HWREGH(ui32Base + USB_O_EPC) & + ~(USB_EPC_PFLTACT_M | USB_EPC_PFLTAEN | + USB_EPC_PFLTSEN_HIGH | USB_EPC_EPEN_M))); +} + +//***************************************************************************** +// +//! Enables power fault detection. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function enables power fault detection in the USB controller. If the +//! USBnPFLT pin is not in use, this function must not be used. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrFaultEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Enable power fault input. + // + HWREGH(ui32Base + USB_O_EPC) |= USB_EPC_PFLTEN; +} + +//***************************************************************************** +// +//! Disables power fault detection. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function disables power fault detection in the USB controller. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrFaultDisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Enable power fault input. + // + HWREGH(ui32Base + USB_O_EPC) &= ~USB_EPC_PFLTEN; +} + +//***************************************************************************** +// +//! Enables the external power pin. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function enables the USBnEPEN signal, which enables an external power +//! supply in host mode operation. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Enable the external power supply enable signal. + // + HWREGH(ui32Base + USB_O_EPC) |= USB_EPC_EPENDE; +} + +//***************************************************************************** +// +//! Disables the external power pin. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function disables the USBnEPEN signal, which disables an external +//! power supply in host mode operation. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrDisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Disable the external power supply enable signal. + // + HWREGH(ui32Base + USB_O_EPC) &= ~USB_EPC_EPENDE; +} + +//***************************************************************************** +// +//! Gets the current frame number. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the last frame number received. +//! +//! \return The last frame number received. +// +//***************************************************************************** +uint32_t +USBFrameNumberGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Return the most recent frame number. + // + return(HWREGH(ui32Base + USB_O_FRAME)); +} + +//***************************************************************************** +// +//! Starts or ends a session. +//! +//! \param ui32Base specifies the USB module base address. +//! \param bStart specifies if this call starts or ends a session. +//! +//! This function is used in OTG mode to start a session request or end a +//! session. If the \e bStart parameter is set to \b true, then this function +//! starts a session and if it is \b false it ends a session. +//! +//! \return None. +// +//***************************************************************************** +void +USBOTGSessionRequest(uint32_t ui32Base, bool bStart) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Start or end the session as directed. + // + if(bStart) + { + HWREGB(ui32Base + USB_O_DEVCTL) |= USB_DEVCTL_SESSION; + } + else + { + HWREGB(ui32Base + USB_O_DEVCTL) &= ~USB_DEVCTL_SESSION; + } +} + +//***************************************************************************** +// +//! Returns the absolute FIFO address for a specified endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies which endpoint's FIFO address to return. +//! +//! This function returns the actual physical address of the FIFO. This +//! address is needed when the USB is going to be used with the uDMA +//! controller and the source or destination address must be set to the +//! physical FIFO address for a specified endpoint. This function can also be +//! used to provide the physical address to manually read data from an +//! endpoints FIFO. +//! +//! \return None. +// +//***************************************************************************** +uint32_t +USBFIFOAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + // + // Return the FIFO address for this endpoint. + // + return(ui32Base + USB_O_FIFO0 + (ui32Endpoint >> 2)); +} + +//***************************************************************************** +// +//! Returns the current operating mode of the controller. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the current operating mode on USB controllers with +//! OTG or Dual mode functionality. +//! +//! For OTG controllers: +//! +//! The function returns one of the following values on OTG controllers: +//! +//! \b USB_OTG_MODE_ASIDE_HOST indicates that the controller is in host mode +//! on the A-side of the cable. +//! +//! \b USB_OTG_MODE_ASIDE_DEV indicates that the controller is in device mode +//! on the A-side of the cable. +//! +//! \b USB_OTG_MODE_BSIDE_HOST indicates that the controller is in host mode +//! on the B-side of the cable. +//! +//! \b USB_OTG_MODE_BSIDE_DEV indicates that the controller is in device mode +//! on the B-side of the cable. If an OTG session request is started with no +//! cable in place, this mode is the default. +//! +//! \b USB_OTG_MODE_NONE indicates that the controller is not attempting to +//! determine its role in the system. +//! +//! For Dual Mode controllers: +//! +//! The function returns one of the following values: +//! +//! \b USB_DUAL_MODE_HOST indicates that the controller is acting as a host. +//! +//! \b USB_DUAL_MODE_DEVICE indicates that the controller acting as a device. +//! +//! \b USB_DUAL_MODE_NONE indicates that the controller is not active as +//! either a host or device. +//! +//! \return Returns \b USB_OTG_MODE_ASIDE_HOST, \b USB_OTG_MODE_ASIDE_DEV, +//! \b USB_OTG_MODE_BSIDE_HOST, \b USB_OTG_MODE_BSIDE_DEV, +//! \b USB_OTG_MODE_NONE, \b USB_DUAL_MODE_HOST, \b USB_DUAL_MODE_DEVICE, or +//! \b USB_DUAL_MODE_NONE. +// +//***************************************************************************** +uint32_t +USBModeGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Checks the current mode in the USB_O_DEVCTL and returns the current + // mode. + // + // USB_OTG_MODE_ASIDE_HOST: USB_DEVCTL_HOST | USB_DEVCTL_SESSION + // USB_OTG_MODE_ASIDE_DEV: USB_DEVCTL_SESSION + // USB_OTG_MODE_BSIDE_HOST: USB_DEVCTL_DEV | USB_DEVCTL_SESSION | + // USB_DEVCTL_HOST + // USB_OTG_MODE_BSIDE_DEV: USB_DEVCTL_DEV | USB_DEVCTL_SESSION + // USB_OTG_MODE_NONE: USB_DEVCTL_DEV + // + return(HWREGB(ui32Base + USB_O_DEVCTL) & + (USB_DEVCTL_DEV | USB_DEVCTL_HOST | USB_DEVCTL_SESSION | + USB_DEVCTL_VBUS_M)); +} + +//***************************************************************************** +// +//! Sets the DMA channel to use for a specified endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies which endpoint's FIFO address to return. +//! \param ui32Channel specifies which DMA channel to use for which endpoint. +//! +//! This function is used to configure which DMA channel to use with a specified +//! endpoint. Receive DMA channels can only be used with receive endpoints +//! and transmit DMA channels can only be used with transmit endpoints. As a +//! result, the 3 receive and 3 transmit DMA channels can be mapped to any +//! endpoint other than 0. The values that are passed into the +//! \e ui32Channel value are the UDMA_CHANNEL_USBEP* values defined in udma.h. +//! +//! \note This function only has an effect on microcontrollers that have the +//! ability to change the DMA channel for an endpoint. Calling this function +//! on other devices has no effect. +//! +//! \return None. +//! +//***************************************************************************** +void +USBEndpointDMAChannel(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Channel) +{ + uint32_t ui32Mask; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7)); + ASSERT(ui32Channel <= UDMA_CHANNEL_USBEP3TX); + + // + // The input select mask must be shifted into the correct position + // based on the channel. + // + ui32Mask = 0xf << (ui32Channel * 4); + + // + // Clear out the current selection for the channel. + // + ui32Mask = HWREG(ui32Base + USB_O_DMASEL) & (~ui32Mask); + + // + // The input select is now shifted into the correct position based on the + // channel. + // + ui32Mask |= (USBEPToIndex(ui32Endpoint)) << (ui32Channel * 4); + + // + // Write the value out to the register. + // + HWREG(ui32Base + USB_O_DMASEL) = ui32Mask; +} + +//***************************************************************************** +// +//! Change the mode of the USB controller to host. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function changes the mode of the USB controller to host mode. +//! +//! \note This function must only be called on microcontrollers that support +//! OTG operation. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostMode(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Force mode in OTG parts that support forcing USB controller mode. + // This bit is not writable in USB controllers that do not support + // forcing the mode. Not setting the USB_GPCS_DEVMOD bit makes this a + // force of host mode. + // + HWREGB(ui32Base + USB_O_GPCS) = USB_GPCS_DEVMODOTG; +} + +//***************************************************************************** +// +//! Change the mode of the USB controller to device. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function changes the mode of the USB controller to device mode. +//! +//! \note This function must only be called on microcontrollers that support +//! OTG operation. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevMode(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Set the USB controller mode to device. + // + HWREGB(ui32Base + USB_O_GPCS) = USB_GPCS_DEVMODOTG | USB_GPCS_DEVMOD; +} + +//***************************************************************************** +// +//! Changes the mode of the USB controller to OTG. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function changes the mode of the USB controller to OTG mode. This +//! function is only valid on microcontrollers that have the OTG capabilities. +//! +//! \return None. +// +//***************************************************************************** +void +USBOTGMode(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Disable the override of the USB controller mode when running on an OTG + // device. + // + HWREGB(ui32Base + USB_O_GPCS) = 0; +} + +//***************************************************************************** +// +//! Change the operating mode of the USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Mode specifies the operating mode of the USB OTG pins. +//! +//! This function changes the operating modes of the USB controller. When +//! operating in full OTG mode, the USB controller uses the VBUS and ID pins to +//! detect mode and voltage changes. While these pins are primarily used in +//! OTG mode, they can also affect the operation of host and device modes. In +//! device mode, the USB controller can be configured to monitor or ignore +//! VBUS. Monitoring VBUS allows the controller to determine if it has been +//! disconnected from the host. In host mode, the USB controller uses the +//! VBUS pin to detect loss of VBUS caused by excessive power draw due to a +//! drop in the VBUS voltage. This call takes the place of USBHostMode(), +//! USBDevMode(), and USBOTGMode(). The \e ui32Mode value should be one of +//! the following values: +//! +//! - \b USB_MODE_OTG enables operating in full OTG mode, VBUS and ID are +//! used by the controller. +//! - \b USB_MODE_HOST enables operating only as a host with no monitoring of +//! VBUS or ID pins. +//! - \b USB_MODE_HOST_VBUS enables operating only as a host with monitoring of +//! VBUS pin. This configuration enables detection of VBUS droop while still +//! forcing host mode. +//! - \b USB_MODE_DEVICE enables operating only as a device with no monitoring +//! of VBUS or ID pins. +//! - \b USB_MODE_DEVICE_VBUS enables operating only as a device with +//! monitoring of VBUS pin. This configuration enables disconnect detection +//! while still forcing device mode. +//! +//! \note Some of the options above are not available on some Tiva devices. +//! Please check the data sheet to determine if the USB controller supports a +//! particular mode. +//! +//! \b Example: Force device mode but allow monitoring of the USB VBUS pin. +//! +//! \verbatim +//! // +//! // Force device mode but allow monitoring of VBUS for disconnect. +//! // +//! USBModeConfig(USB_MODE_DEVICE_VBUS); +//! \endverbatim +//! +//! \return None. +// +//***************************************************************************** +void +USBModeConfig(uint32_t ui32Base, uint32_t ui32Mode) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + HWREG(ui32Base + USB_O_GPCS) = ui32Mode; +} + +//***************************************************************************** +// +//! Powers off the internal USB PHY. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function powers off the internal USB PHY, reducing the current +//! consumption of the device. While in the powered-off state, the USB +//! controller is unable to operate. +//! +//! \return None. +// +//***************************************************************************** +void +USBPHYPowerOff(uint32_t ui32Base) +{ + // + // Set the PWRDNPHY bit in the PHY, putting it into its low power mode. + // + HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_PWRDNPHY; +} + +//***************************************************************************** +// +//! Powers on the internal USB PHY. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function powers on the internal USB PHY, enabling it return to normal +//! operation. By default, the PHY is powered on, so this function must +//! only be called if USBPHYPowerOff() has previously been called. +//! +//! \return None. +// +//***************************************************************************** +void +USBPHYPowerOn(uint32_t ui32Base) +{ + // + // Clear the PWRDNPHY bit in the PHY, putting it into normal operating + // mode. + // + HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_PWRDNPHY; +} + +//***************************************************************************** +// +//! Sets the number of packets to request when transferring multiple bulk +//! packets. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint index to target for this write. +//! \param ui32Count is the number of packets to request. +//! +//! This function sets the number of consecutive bulk packets to request +//! when transferring multiple bulk packets with DMA. +//! +//! \note This feature is not available on all Tiva devices. Please +//! check the data sheet to determine if the USB controller has a DMA +//! controller or if it must use the uDMA controller for DMA transfers. +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointPacketCountSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Count) +{ + HWREG(ui32Base + USB_O_RQPKTCOUNT1 + + (0x4 * (USBEPToIndex(ui32Endpoint) - 1))) = ui32Count; +} + +//***************************************************************************** +// +//! Returns the number of USB endpoint pairs on the device. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the number of endpoint pairs supported by the USB +//! controller corresponding to the passed base address. The value returned is +//! the number of IN or OUT endpoints available and does not include endpoint 0 +//! (the control endpoint). For example, if 15 is returned, there are 15 IN +//! and 15 OUT endpoints available in addition to endpoint 0. +//! +//! \return Returns the number of IN or OUT endpoints available. +// +//***************************************************************************** +uint32_t +USBNumEndpointsGet(uint32_t ui32Base) +{ + // + // Read the number of endpoints from the hardware. The number of TX and + // RX endpoints are always the same. + // + return(HWREGB(ui32Base + USB_O_EPINFO) & USB_EPINFO_TXEP_M); +} + +//***************************************************************************** +// +//! Returns the version of the USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the version number of the USB controller, which can +//! be be used to adjust for slight differences between the USB controllers in +//! the Tiva family. The values that are returned are +//! \b USB_CONTROLLER_VER_0 and \b USB_CONTROLLER_VER_1. +//! +//! \note The most significant difference between \b USB_CONTROLLER_VER_0 and +//! \b USB_CONTROLLER_VER_1 is that \b USB_CONTROLLER_VER_1 supports the USB +//! controller's own bus master DMA controller, while the +//! \b USB_CONTROLLER_VER_0 only supports using the uDMA controller with the +//! USB module. +//! +//! \b Example: Get the version of the Tiva USB controller. +//! +//! \verbatim +//! uint32_t ui32Version; +//! +//! // +//! // Retrieve the version of the Tiva USB controller. +//! // +//! ui32Version = USBControllerVersion(USB0_BASE); +//! \endverbatim +//! +//! \return This function returns one of the \b USB_CONTROLLER_VER_ values. +// +//***************************************************************************** +uint32_t +USBControllerVersion(uint32_t ui32Base) +{ + // + // Return the type field of the peripheral properties. This returns + // zero for all parts that did not have a peripheral property. + // + return(HWREG(ui32Base + USB_O_PP) & USB_PP_TYPE_M); +} + +//***************************************************************************** +// +//! Configures and enables the clocking to the USB controller's PHY. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Div specifies the divider for the internal USB PHY clock. +//! \param ui32Flags configures the internal USB PHY clock and specifies the +//! clock source for a ULPI-connected PHY. +//! +//! This function configures and enables the USB PHY clock. In addition, for +//! systems that use a ULPI-connected external PHY, this function configures +//! the source for the PHY clock. The \e ui32Flags parameter specifies the +//! clock source with the following values: +//! +//! - \b USB_CLOCK_INTERNAL uses the internal PLL combined with the \e ui32Div +//! value to generate the USB clock that is used by the internal USB PHY. In +//! addition, when using an external ULPI-connected USB PHY, the specified +//! clock is output on the USB0CLK pin. +//! - \b USB_CLOCK_EXTERNAL specifies that USB0CLK is an input from the +//! ULPI-connected external PHY. +//! +//! The \e ui32Div parameter is used to specify a divider for the internal +//! clock if the \b USB_CLOCK_INTERNAL is specified and is ignored if +//! \b USB_CLOCK_EXTERNAL is specified. When the \b USB_CLOCK_INTERNAL is +//! specified, the \e ui32Div value must be set so that the PLL_VCO/\e ui32Div +//! results in a 60-MHz clock. +//! +//! \b Example: Enable the USB clock with a 480-MHz PLL setting. +//! +//! \verbatim +//! // +//! // Enable the USB clock using a 480-MHz PLL. +//! // (480-MHz/8 = 60-MHz) +//! // +//! USBClockEnable(USB0_BASE, 8, USB_CLOCK_INTERNAL); +//! \endverbatim +//! +//! \note The ability to configure the USB PHY clock is not available on +//! all Tiva devices. Please consult the data sheet for the Tiva +//! device that you are using to determine if this feature is available. +//! +//! \return None. +// +//***************************************************************************** +void +USBClockEnable(uint32_t ui32Base, uint32_t ui32Div, uint32_t ui32Flags) +{ + ASSERT(ui32Base == USB0_BASE); + + // + // Configure and enable the USB clock input. + // + HWREG(ui32Base + USB_O_CC) = (ui32Div - 1) | ui32Flags; +} + +//***************************************************************************** +// +//! Disables the clocking of the USB controller's PHY. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function disables the USB PHY clock. This function should not be +//! called in applications where the USB controller is used. +//! +//! \b Example: Disable the USB PHY clock input. +//! +//! \verbatim +//! // +//! // Disable clocking of the USB controller's PHY. +//! // +//! USBClockDisable(USB0_BASE); +//! \endverbatim +//! +//! \note The ability to configure the USB PHY clock is not available on all +//! Tiva devices. Please consult the data sheet for the Tiva device +//! that you are using to determine if this feature is available. +//! +//! \return None. +// +//***************************************************************************** +void +USBClockDisable(uint32_t ui32Base) +{ + ASSERT(ui32Base == USB0_BASE); + + // + // Disable the USB clock input. + // + HWREG(ui32Base + USB_O_CC) = 0; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** +//***************************************************************************** +// +//! \addtogroup usb_dma +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! Enable interrupts for a specified integrated USB DMA channel. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Channel specifies which DMA channel interrupt to enable. +//! +//! This function enables the USB DMA channel interrupt based on the +//! \e ui32Channel parameter. The \e ui32Channel value is a zero-based +//! index of the USB DMA channel. Once enabled, the USBDMAChannelIntStatus() +//! function returns if a DMA channel has generated an interrupt. +//! +//! \b Example: Enable the USB DMA channel 3 interrupt. +//! +//! \verbatim +//! // +//! // Enable the USB DMA channel 3 interrupt +//! // +//! USBDMAChannelIntEnable(USB0_BASE, 3); +//! \endverbatim +//! +//! \note This feature is not available on all Tiva devices. Please +//! check the data sheet to determine if the USB controller has a DMA +//! controller or if it must use the uDMA controller for DMA transfers. +//! +//! \return None. +// +//***************************************************************************** +void +USBDMAChannelIntEnable(uint32_t ui32Base, uint32_t ui32Channel) +{ + ASSERT(ui32Base == USB0_BASE); + ASSERT(ui32Channel < 8); + + // + // Enable the specified DMA channel interrupts. + // + HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) |= USB_DMACTL0_IE; +} + +//***************************************************************************** +// +//! Disable interrupts for a specified integrated USB DMA channel. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Channel specifies which USB DMA channel interrupt to disable. +//! +//! This function disables the USB DMA channel interrupt based on the +//! \e ui32Channel parameter. The \e ui32Channel value is a zero-based +//! index of the USB DMA channel. +//! +//! \b Example: Disable the USB DMA channel 3 interrupt. +//! +//! \verbatim +//! // +//! // Disable the USB DMA channel 3 interrupt +//! // +//! USBDMAChannelIntDisable(USB0_BASE, 3); +//! \endverbatim +//! +//! \note This feature is not available on all Tiva devices. Please +//! check the data sheet to determine if the USB controller has a DMA +//! controller or if it must use the uDMA controller for DMA transfers. +//! +//! \return None. +// +//***************************************************************************** +void +USBDMAChannelIntDisable(uint32_t ui32Base, uint32_t ui32Channel) +{ + ASSERT(ui32Base == USB0_BASE); + ASSERT(ui32Channel < 8); + + // + // Enable the specified DMA channel interrupts. + // + HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) &= ~USB_DMACTL0_IE; +} + +//***************************************************************************** +// +//! Return the current status of the integrated USB DMA interrupts. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the current bit-mapped interrupt status for all USB +//! DMA channel interrupt sources. Calling this function automatically clears +//! all currently pending USB DMA interrupts. +//! +//! \note This feature is not available on all Tiva devices. Please +//! check the data sheet to determine if the USB controller has a DMA +//! controller or if it must use the uDMA controller for DMA transfers. +//! +//! \b Example: Get the pending USB DMA interrupts. +//! +//! \verbatim +//! uint32_t ui32Ints; +//! +//! // +//! // Get the pending USB DMA interrupts. +//! // +//! ui32Ints = USBDMAChannelIntStatus(USB0_BASE); +//! \endverbatim +//! +//! \return The bit-mapped interrupts for the DMA channels. +// +//***************************************************************************** +uint32_t +USBDMAChannelIntStatus(uint32_t ui32Base) +{ + ASSERT(ui32Base == USB0_BASE); + + return(HWREG(ui32Base + USB_O_DMAINTR)); +} + +//***************************************************************************** +// +//! Enables integrated USB DMA for a specified channel. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Channel specifies the USB DMA channel to enable. +//! +//! This function enables the USB DMA channel passed in the \e ui32Channel +//! parameter. The \e ui32Channel value is a zero-based index of the USB DMA +//! channel. +//! +//! \b Example: Enable USB DMA channel 2. +//! +//! \verbatim +//! // +//! // Enable USB DMA channel 2. +//! // +//! USBDMAChannelEnable(2); +//! \endverbatim +//! +//! \note This feature is not available on all Tiva devices. Please +//! check the data sheet to determine if the USB controller has a DMA +//! controller or if it must use the uDMA controller for DMA transfers. +//! +//! \return None. +// +//***************************************************************************** +void +USBDMAChannelEnable(uint32_t ui32Base, uint32_t ui32Channel) +{ + ASSERT(ui32Base == USB0_BASE); + ASSERT(ui32Channel < 8); + + // + // Enable the USB DMA channel. + // + HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) |= + USB_DMACTL0_ENABLE; +} + +//***************************************************************************** +// +//! Disables integrated USB DMA for a specified channel. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Channel specifies the USB DMA channel to disable. +//! +//! This function disables the USB DMA channel passed in the \e ui32Channel +//! parameter. The \e ui32Channel parameter is a zero-based index of the DMA +//! channel. +//! +//! \b Example: Disable USB DMA channel 2. +//! +//! \verbatim +//! // +//! // Disable USB DMA channel 2. +//! // +//! USBDMAChannelDisable(2); +//! \endverbatim +//! +//! \note This feature is not available on all Tiva devices. Please +//! check the data sheet to determine if the USB controller has a DMA +//! controller or if it must use the uDMA controller for DMA transfers. +//! +//! \return None. +// +//***************************************************************************** +void +USBDMAChannelDisable(uint32_t ui32Base, uint32_t ui32Channel) +{ + ASSERT(ui32Base == USB0_BASE); + ASSERT(ui32Channel < 8); + + // + // Disable the USB DMA channel. + // + HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) &= + ~USB_DMACTL0_ENABLE; +} + +//***************************************************************************** +// +//! Assigns and configures an endpoint to a specified integrated USB DMA +//! channel. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Channel specifies which DMA channel to access. +//! \param ui32Endpoint is the endpoint to assign to the USB DMA channel. +//! \param ui32Config is used to specify the configuration of the USB DMA +//! channel. +//! +//! This function assigns an endpoint and configures the settings for a +//! USB DMA channel. The \e ui32Endpoint parameter is one of the +//! \b USB_EP_* values and the \e ui32Channel value is a zero-based index of +//! the DMA channel to configure. The \e ui32Config parameter is a combination +//! of the \b USB_DMA_CFG_* values using the following guidelines. +//! +//! Use one of the following to set the DMA burst mode: +//! - \b USB_DMA_CFG_BURST_NONE disables bursting. +//! - \b USB_DMA_CFG_BURST_4 sets the DMA burst size to 4 words. +//! - \b USB_DMA_CFG_BURST_8 sets the DMA burst size to 8 words. +//! - \b USB_DMA_CFG_BURST_16 sets the DMA burst size to 16 words. +//! +//! Use one of the following to set the DMA mode: +//! - \b USB_DMA_CFG_MODE_0 is typically used when only a single packet is +//! being sent via DMA and triggers one completion interrupt per packet. +//! - \b USB_DMA_CFG_MODE_1 is typically used when multiple packets are being +//! sent via DMA and triggers one completion interrupt per transfer. +//! +//! Use one of the following to set the direction of the transfer: +//! - \b USB_DMA_CFG_DIR_RX selects a DMA transfer from the endpoint to a +//! memory location. +//! - \b USB_DMA_CFG_DIR_TX selects a DMA transfer to the endpoint from a +//! memory location. +//! +//! The following two optional settings allow an application to immediately +//! enable the DMA transfer and/or DMA interrupts when configuring the DMA +//! channel: +//! - \b USB_DMA_CFG_INT_EN enables interrupts for this channel immediately so +//! that an added call to USBDMAChannelIntEnable() is not necessary. +//! - \b USB_DMA_CFG_EN enables the DMA channel immediately so that an added +//! call to USBDMAChannelEnable() is not necessary. +//! +//! \b Example: Assign channel 0 to endpoint 1 in DMA mode 0, 4 word burst, +//! enable interrupts and immediately enable the transfer. +//! +//! \verbatim +//! // +//! // Assign channel 0 to endpoint 1 in DMA mode 0, 4 word bursts, +//! // enable interrupts and immediately enable the transfer. +//! // +//! USBDMAChannelConfigSet(USB0_BASE, 0, USB_EP_1, +//! (USB_DMA_CFG_BURST_4 | USB_DMA_CFG_MODE0 | +//! USB_DMA_CFG_DIR_RX | USB_DMA_CFG_INT_EN | +//! USB_DMA_CFG_EN)); +//! \endverbatim +//! +//! \note This feature is not available on all Tiva devices. Please +//! check the data sheet to determine if the USB controller has a DMA +//! controller or if it must use the uDMA controller for DMA transfers. +//! +//! \return None. +// +//***************************************************************************** +void +USBDMAChannelConfigSet(uint32_t ui32Base, uint32_t ui32Channel, + uint32_t ui32Endpoint, uint32_t ui32Config) +{ + ASSERT(ui32Base == USB0_BASE); + ASSERT(ui32Channel < 8); + ASSERT((ui32Endpoint & ~USB_EP_7) == 0); + + // + // Reset this USB DMA channel. + // + HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) = 0; + + // + // Set the configuration of the requested channel. + // + HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) = + ui32Config | ui32Endpoint; +} + +//***************************************************************************** +// +//! Returns the current status for an integrated USB DMA channel. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Channel specifies which DMA channel to query. +//! +//! This function returns the current status for the USB DMA channel specified +//! by the \e ui32Channel parameter. The \e ui32Channel value is a zero-based +//! index of the USB DMA channel to query. +//! +//! \b Example: Get the current USB DMA status for channel 2. +//! +//! \verbatim +//! uint32_t ui32Status; +//! +//! // +//! // Get the current USB DMA status for channel 2. +//! // +//! ui32Status = USBDMAChannelStatus(USB0_BASE, 2); +//! \endverbatim +//! +//! \note This feature is not available on all Tiva devices. Please +//! check the data sheet to determine if the USB controller has a DMA +//! controller or if it must use the uDMA controller for DMA transfers. +//! +//! \return Returns zero or \b USB_DMACTL0_ERR if there is a pending error +//! condition on a DMA channel. +// +//***************************************************************************** +uint32_t +USBDMAChannelStatus(uint32_t ui32Base, uint32_t ui32Channel) +{ + ASSERT(ui32Base == USB0_BASE); + ASSERT(ui32Channel < 8); + + // + // Return a non-zero value if there is a pending error condition. + // + return(HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) & + USB_DMACTL0_ERR); +} + +//***************************************************************************** +// +//! Clears the integrated USB DMA status for a specified channel. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Channel specifies which DMA channel to clear. +//! \param ui32Status holds the status bits to clear. +//! +//! This function clears the USB DMA channel status for the channel specified +//! by the \e ui32Channel parameter. The \e ui32Channel value is a zero-based +//! index of the USB DMA channel to query. The \e ui32Status parameter +//! specifies the status bits to clear and must be the valid values that are +//! returned from a call to the USBDMAChannelStatus() function. +//! +//! \b Example: Clear the current USB DMA status for channel 2. +//! +//! \verbatim +//! // +//! // Clear the any pending USB DMA status for channel 2. +//! // +//! USBDMAChannelStatusClear(USB0_BASE, 2, USBDMAChannelStatus(USB0_BASE, 2)); +//! \endverbatim +//! +//! \note This feature is not available on all Tiva devices. Please +//! check the data sheet to determine if the USB controller has a DMA +//! controller or if it must use the uDMA controller for DMA transfers. +//! +//! \return None. +// +//***************************************************************************** +void +USBDMAChannelStatusClear(uint32_t ui32Base, uint32_t ui32Channel, + uint32_t ui32Status) +{ + ASSERT(ui32Base == USB0_BASE); + ASSERT(ui32Channel < 8); + + // + // The only status is the error bit. + // + ui32Status &= USB_DMACTL0_ERR; + + // + // Clear the specified error condition. + // + HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) &= ~ui32Status; +} + +//***************************************************************************** +// +//! Sets the source or destination address for an integrated USB DMA transfer +//! on a specified channel. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Channel specifies which DMA channel to configure. +//! \param pvAddress specifies the source or destination address for the USB +//! DMA transfer. +//! +//! This function sets the source or destination address for the USB DMA +//! channel number specified in the \e ui32Channel parameter. The +//! \e ui32Channel value is a zero-based index of the USB DMA channel. The +//! \e pvAddress parameter is a source address if the transfer type for the DMA +//! channel is transmit and a destination address if the transfer type is +//! receive. +//! +//! \b Example: Set the transfer address for USB DMA channel 1. +//! +//! \verbatim +//! void *pvBuffer; +//! +//! // +//! // Set the address for USB DMA channel 1. +//! // +//! USBDMAChannelAddressSet(USB0_BASE, 1, pvBuffer); +//! \endverbatim +//! +//! \note This feature is not available on all Tiva devices. Please +//! check the data sheet to determine if the USB controller has a DMA +//! controller or if it must use the uDMA controller for DMA transfers. +//! +//! \return None. +// +//***************************************************************************** +void +USBDMAChannelAddressSet(uint32_t ui32Base, uint32_t ui32Channel, + void *pvAddress) +{ + ASSERT(ui32Base == USB0_BASE); + ASSERT(ui32Channel < 8); + + // + // Set the DMA address. + // + HWREG(ui32Base + USB_O_DMAADDR0 + (0x10 * ui32Channel)) = + (uint32_t)pvAddress; +} + +//***************************************************************************** +// +//! Returns the source or destination address for the specified integrated USB +//! DMA channel. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Channel specifies the USB DMA channel. +//! +//! This function returns the DMA address for the channel number specified +//! in the \e ui32Channel parameter. The \e ui32Channel value is a zero-based +//! index of the DMA channel to query. This function must not be used on +//! devices that return \b USB_CONTROLLER_VER_0 from the USBControllerVersion() +//! function. +//! +//! \b Example: Get the transfer address for USB DMA channel 1. +//! +//! \verbatim +//! void *pvBuffer; +//! +//! // +//! // Retrieve the current DMA address for channel 1. +//! // +//! pvBuffer = USBDMAChannelAddressGet(USB0_BASE, 1); +//! \endverbatim +//! +//! \note This feature is not available on all Tiva devices. Please +//! check the data sheet to determine if the USB controller has a DMA +//! controller or if it must use the uDMA controller for DMA transfers. +//! +//! \return The current DMA address for a USB DMA channel. +// +//***************************************************************************** +void * +USBDMAChannelAddressGet(uint32_t ui32Base, uint32_t ui32Channel) +{ + ASSERT(ui32Base == USB0_BASE); + ASSERT(ui32Channel < 8); + + // + // Return the current DMA address. + // + return((void *)HWREG(ui32Base + USB_O_DMAADDR0 + (0x10 * ui32Channel))); +} + +//***************************************************************************** +// +//! Sets the transfer count for an integrated USB DMA channel. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Channel specifies which DMA channel to access. +//! \param ui32Count specifies the number of bytes to transfer. +//! +//! This function sets the USB DMA transfer count in bytes for the channel +//! number specified in the \e ui32Channel parameter. The \e ui32Channel +//! value is a zero-based index of the DMA channel. +//! +//! \b Example: Set the transfer count to 512 bytes for USB DMA channel 1. +//! +//! \verbatim +//! // +//! // Set the transfer count to 512 bytes for USB DMA channel 1. +//! // +//! USBDMAChannelCountSet(USB0_BASE, 1, 512); +//! \endverbatim +//! +//! \note This feature is not available on all Tiva devices. Please +//! check the data sheet to determine if the USB controller has a DMA +//! controller or if it must use the uDMA controller for DMA transfers. +//! +//! \return None. +// +//***************************************************************************** +void +USBDMAChannelCountSet(uint32_t ui32Base, uint32_t ui32Channel, + uint32_t ui32Count) +{ + ASSERT(ui32Base == USB0_BASE); + ASSERT(ui32Channel < 8); + + // + // Set the USB DMA count for the channel. + // + HWREG(ui32Base + USB_O_DMACOUNT0 + (0x10 * ui32Channel)) = ui32Count; +} + +//***************************************************************************** +// +//! Returns the transfer count for an integrated USB DMA channel. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Channel specifies which DMA channel to access. +//! +//! This function returns the USB DMA transfer count in bytes for the channel +//! number specified in the \e ui32Channel parameter. The \e ui32Channel value +//! is a zero-based index of the DMA channel to query. +//! +//! \b Example: Get the transfer count for USB DMA channel 1. +//! +//! \verbatim +//! uint32_t ui32Count; +//! +//! // +//! // Get the transfer count for USB DMA channel 1. +//! // +//! ui32Count = USBDMAChannelCountGet(USB0_BASE, 1); +//! \endverbatim +//! +//! \note This feature is not available on all Tiva devices. Please +//! check the data sheet to determine if the USB controller has a DMA +//! controller or if it must use the uDMA controller for DMA transfers. +//! +//! \return The current count for a USB DMA channel. +// +//***************************************************************************** +uint32_t +USBDMAChannelCountGet(uint32_t ui32Base, uint32_t ui32Channel) +{ + ASSERT(ui32Base == USB0_BASE); + ASSERT(ui32Channel < 8); + + // + // Return the current DMA count. + // + return(HWREG(ui32Base + USB_O_DMACOUNT0 + (0x10 * ui32Channel))); +} + +//***************************************************************************** +// +//! Returns the available number of integrated USB DMA channels. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the total number of DMA channels available when using +//! the integrated USB DMA controller. This function returns 0 if the +//! integrated controller is not present. +//! +//! \b Example: Get the number of integrated DMA channels. +//! +//! \verbatim +//! uint32_t ui32Count; +//! +//! // +//! // Get the number of integrated DMA channels. +//! // +//! ui32Count = USBDMANumChannels(USB0_BASE); +//! \endverbatim +//! +//! \return The number of integrated USB DMA channels or zero if the +//! integrated USB DMA controller is not present. +// +//***************************************************************************** +uint32_t +USBDMANumChannels(uint32_t ui32Base) +{ + ASSERT(ui32Base == USB0_BASE); + + // + // Return the number of DMA channels for the integrated DMA controller. + // + return(HWREG(ui32Base + USB_O_RAMINFO) >> USB_RAMINFO_DMACHAN_S); +} +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** +//***************************************************************************** +// +//! \addtogroup usb_ulpi +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! Configures the USB controller's ULPI function. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Config contains the configuration options. +//! +//! This function is used to configure the USB controller's ULPI function. +//! The configuration options are set in the \e ui32Config parameter and are a +//! logical OR of the following values: +//! +//! - \b USB_ULPI_EXTVBUS enables the external ULPI PHY as the source for VBUS +//! signaling. +//! - \b USB_ULPI_EXTVBUS_IND enables the external ULPI PHY to detect external +//! VBUS over-current condition. +//! +//! \b Example: Enable ULPI PHY with full VBUS control. +//! +//! \verbatim +//! // +//! // Enable ULPI PHY with full VBUS control. +//! // +//! USBULPIConfig(USB0_BASE, USB_ULPI_EXTVBUS | USB_ULPI_EXTVBUS_IND); +//! \endverbatim +//! +//! \note The USB ULPI feature is not available on all Tiva devices. +//! Please consult the data sheet for the Tiva device that you +//! are using to determine if this feature is available. +//! +//! \return None. +// +//***************************************************************************** +void +USBULPIConfig(uint32_t ui32Base, uint32_t ui32Config) +{ + HWREGB(ui32Base + USB_O_ULPIVBUSCTL) = (uint8_t)ui32Config; +} + +//***************************************************************************** +// +//! Enables the USB controller's ULPI function. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function enables the USB controller's ULPI function and must be +//! called before attempting to access an external ULPI-connected USB PHY. +//! +//! \b Example: Enable ULPI function. +//! +//! \verbatim +//! // +//! // Enable ULPI function. +//! // +//! USBULPIEnable(USB0_BASE); +//! \endverbatim +//! +//! \note The USB ULPI feature is not available on all Tiva devices. +//! Please consult the data sheet for the Tiva device that you +//! are using to determine if this feature is available. +//! +//! \return None. +// +//***************************************************************************** +void +USBULPIEnable(uint32_t ui32Base) +{ + HWREG(ui32Base + USB_O_PC) |= USB_PC_ULPIEN; +} + +//***************************************************************************** +// +//! Disables the USB controller's ULPI function. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function disables the USB controller's ULPI function. Accesses to +//! the external ULPI-connected PHY cannot succeed after this function has been +//! called. +//! +//! \b Example: Disable ULPI function. +//! +//! \verbatim +//! // +//! // Disable ULPI function. +//! // +//! USBULPIDisable(USB0_BASE); +//! \endverbatim +//! +//! \note The USB ULPI feature is not available on all Tiva devices. +//! Please consult the data sheet for the Tiva device that you +//! are using to determine if this feature is available. +//! +//! \return None. +// +//***************************************************************************** +void +USBULPIDisable(uint32_t ui32Base) +{ + HWREG(ui32Base + USB_O_PC) &= ~USB_PC_ULPIEN; +} + +//***************************************************************************** +// +//! Reads a register from an external ULPI-connected USB PHY. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui8Reg specifies the register address to read. +//! +//! This function reads the register address specified in the \e ui8Reg +//! parameter using the ULPI function. This function is blocking and only +//! returns when the read access completes. The function does not return if +//! there is not a ULPI-connected USB PHY present. +//! +//! \b Example: Read a register from the ULPI PHY. +//! +//! \verbatim +//! uint8_t ui8Value; +//! +//! // +//! // Read a register from the ULPI PHY register at 0x10. +//! // +//! ui8Value = USBULPIRegRead(USB0_BASE, 0x10); +//! \endverbatim +//! +//! \note The USB ULPI feature is not available on all Tiva devices. +//! Please consult the data sheet for the Tiva device that you +//! are using to determine if this feature is available. +//! +//! \return The value of the requested ULPI register. +// +//***************************************************************************** +uint8_t +USBULPIRegRead(uint32_t ui32Base, uint8_t ui8Reg) +{ + ASSERT(ui32Base == USB0_BASE); + + // + // Set the register address and initiate a read access. + // + HWREGB(ui32Base + USB_O_ULPIREGADDR) = ui8Reg; + HWREGB(ui32Base + USB_O_ULPIREGCTL) = + USB_ULPIREGCTL_RDWR | USB_ULPIREGCTL_REGACC; + + // + // Wait for the access to complete. + // + while((HWREGB(ui32Base + USB_O_ULPIREGCTL) & USB_ULPIREGCTL_REGCMPLT) == 0) + { + } + + // + // Clear the register access complete flag. + // + HWREGB(ui32Base + USB_O_ULPIREGCTL) = 0; + + return(HWREGB(ui32Base + USB_O_ULPIREGDATA)); +} + +//***************************************************************************** +// +//! Writes a value to a register on an external ULPI-connected USB PHY. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui8Reg specifies the register address to write. +//! \param ui8Data specifies the data to write. +//! +//! This function writes the register address specified in the \e ui8Reg +//! parameter with the value specified in the \e ui8Data parameter using the +//! ULPI function. This function is blocking and only returns when the +//! write access completes. The function does not return if there is not a +//! ULPI-connected USB PHY present. +//! +//! \b Example: Write a register from the external ULPI PHY. +//! +//! \verbatim +//! // +//! // Write the ULPI PHY register at 0x10 with 0x20. +//! // +//! USBULPIRegWrite(USB0_BASE, 0x10, 0x20); +//! \endverbatim +//! +//! \note The USB ULPI feature is not available on all Tiva devices. +//! Please consult the data sheet for the Tiva device that you +//! are using to determine if this feature is available. +//! +//! \return None. +// +//***************************************************************************** +void +USBULPIRegWrite(uint32_t ui32Base, uint8_t ui8Reg, uint8_t ui8Data) +{ + ASSERT(ui32Base == USB0_BASE); + + // + // Set the register address and initiate a read access. + // + HWREGB(ui32Base + USB_O_ULPIREGADDR) = ui8Reg; + HWREGB(ui32Base + USB_O_ULPIREGDATA) = ui8Data; + HWREGB(ui32Base + USB_O_ULPIREGCTL) = USB_ULPIREGCTL_REGACC; + + // + // Wait for the access to complete. + // + while((HWREGB(ui32Base + USB_O_ULPIREGCTL) & USB_ULPIREGCTL_REGCMPLT) == 0) + { + } + + // + // Clear the register access complete flag. + // + HWREGB(ui32Base + USB_O_ULPIREGCTL) = 0; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** +//***************************************************************************** +// +//! \addtogroup usb_lpm +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! Sends an LPM request to a device at a specified address and endpoint number. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Address is the target device address for the LPM request. +//! \param ui32Endpoint is the target endpoint for the LPM request. +//! +//! This function sends an LPM request to a connected device in host mode. +//! The \e ui32Address parameter specifies the device address and has a range +//! of values from 1 to 127. The \e ui32Endpoint parameter specifies the +//! endpoint on the device to which to send the LPM request and must be one of +//! the \b USB_EP_* values. The function returns before the LPM request is +//! sent, requiring the caller to poll the USBLPMIntStatus() function or wait +//! for an interrupt to signal completion of the LPM transaction. This +//! function must only be called after the USBHostLPMConfig() has configured +//! the LPM transaction settings. +//! +//! \b Example: Send an LPM request to the device at address 1 on endpoint 0. +//! +//! \verbatim +//! // +//! // Send an LPM request to the device at address 1 on endpoint 0. +//! // +//! USBHostLPMSend(USB0_BASE, 1, USB_EP_0); +//! \endverbatim +//! +//! \note This function must only be called in host mode. The USB LPM feature +//! is not available on all Tiva devices. Please consult the data sheet for +//! the Tiva device that you are using to determine if this feature is +//! available. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostLPMSend(uint32_t ui32Base, uint32_t ui32Address, uint32_t ui32Endpoint) +{ + uint32_t ui32Reg; + + ASSERT(ui32Base == USB0_BASE); + ASSERT(ui32Address < 127); + + // + // Set the address and endpoint. + // + HWREGB(ui32Base + USB_O_LPMFADDR) = ui32Address; + + ui32Reg = HWREGH(ui32Base + USB_O_LPMATTR) & ~USB_LPMATTR_ENDPT_M; + ui32Reg |= (USBEPToIndex(ui32Endpoint) << USB_LPMATTR_ENDPT_S); + + HWREGH(ui32Base + USB_O_LPMATTR) = ui32Reg; + + // + // Send the LPM transaction. + // + HWREGB(ui32Base + USB_O_LPMCNTRL) |= USB_LPMCNTRL_TXLPM; +} + +//***************************************************************************** +// +//! Sets the global configuration for all LPM requests. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32ResumeTime specifies the resume signaling duration in 75us +//! increments. +//! \param ui32Config specifies the combination of configuration options for +//! LPM transactions. +//! +//! This function sets the global configuration options for LPM transactions +//! and must be called at least once before ever calling USBHostLPMSend(). The +//! \e ui32ResumeTime specifies the length of time that the host drives resume +//! signaling on the bus in microseconds. The valid values +//! for \e ui32ResumeTime are from 50us to 1175us in 75us increments. The +//! remaining configuration is specified by the \e ui32Config parameter and +//! includes the following options: +//! +//! - \b USB_HOST_LPM_RMTWAKE allows the device to signal a remote wake from +//! the LPM state. +//! - \b USB_HOST_LPM_L1 is the LPM mode to enter and must always be included +//! in the configuration. +//! +//! \b Example: Set the LPM configuration to allow remote wake with a resume +//! duration of 500us. +//! +//! \verbatim +//! // +//! // Set the LPM configuration to allow remote wake with a resume +//! // duration of 500us. +//! // +//! USBHostLPMConfig(USB0_BASE, 500, USB_HOST_LPM_RMTWAKE | USB_HOST_LPM_L1); +//! \endverbatim +//! +//! \note This function must only be called in host mode. The USB LPM feature +//! is not available on all Tiva devices. Please consult the data sheet for +//! the Tiva device that you are using to determine if this feature is +//! available. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostLPMConfig(uint32_t ui32Base, uint32_t ui32ResumeTime, + uint32_t ui32Config) +{ + ASSERT(ui32Base == USB0_BASE); + ASSERT(ui32ResumeTime <= 1175); + ASSERT(ui32ResumeTime >= 50); + + // + // Set the Host Initiated Resume Duration, Remote wake and Suspend mode. + // + HWREGH(ui32Base + USB_O_LPMATTR) = + ui32Config | ((ui32ResumeTime - 50) / 75) << USB_LPMATTR_HIRD_S; +} + +//***************************************************************************** +// +//! Initiates resume signaling to wake a device from LPM suspend mode. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! In host mode, this function initiates resume signaling to wake a device +//! that has entered an LPM-triggered low power mode. This LPM-triggered low +//! power mode is entered when the USBHostLPMSend() is called to put a specific +//! device into a low power state. +//! +//! \b Example: Initiate resume signaling. +//! +//! \verbatim +//! // +//! // Initiate resume signaling. +//! // +//! USBHostLPMResume(USB0_BASE); +//! \endverbatim +//! +//! \note This function must only be called in host mode. The USB LPM feature +//! is not available on all Tiva devices. Please consult the data sheet for +//! the Tiva device that you are using to determine if this feature is +//! available. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostLPMResume(uint32_t ui32Base) +{ + ASSERT(ui32Base == USB0_BASE); + + // + // Send Resume signaling. + // + HWREGB(ui32Base + USB_O_LPMCNTRL) |= USB_LPMCNTRL_RES; +} + +//***************************************************************************** +// +//! Initiates remote wake signaling to request the device to leave LPM +//! suspend mode. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function initiates remote wake signaling to request that the host +//! wake a device that has entered an LPM-triggered low power mode. +//! +//! \b Example: Initiate remote wake signaling. +//! +//! \verbatim +//! // +//! // Initiate remote wake signaling. +//! // +//! USBDevLPMRemoteWake(USB0_BASE); +//! \endverbatim +//! +//! \note This function must only be called in device mode. The USB LPM feature +//! is not available on all Tiva devices. Please consult the data sheet for +//! the Tiva device that you are using to determine if this feature is +//! available. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevLPMRemoteWake(uint32_t ui32Base) +{ + ASSERT(ui32Base == USB0_BASE); + + // + // Send remote wake signaling. + // + HWREGB(ui32Base + USB_O_LPMCNTRL) |= USB_LPMCNTRL_RES; +} + +//***************************************************************************** +// +//! Configures the USB device mode response to LPM requests. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Config is the combination of configuration options for LPM +//! transactions in device mode. +//! +//! This function sets the global configuration options for LPM +//! transactions in device mode and must be called before ever calling +//! USBDevLPMEnable() to set the configuration for LPM transactions. The +//! configuration options in device mode are specified in the \e ui32Config +//! parameter and include one of the following: +//! +//! - \b USB_DEV_LPM_NONE disables the USB controller from responding to LPM +//! transactions. +//! - \b USB_DEV_LPM_EN enables the USB controller to respond to LPM +//! and extended transactions. +//! - \b USB_DEV_LPM_EXTONLY enables the USB controller to respond to +//! extended transactions, but not LPM transactions. +//! +//! The \e ui32Config option can also optionally include the +//! \b USB_DEV_LPM_NAK value to cause the USB controller to NAK all +//! transactions other than an LPM transaction once the USB controller is in +//! LPM suspend mode. If this value is not included in the \e ui32Config +//! parameter, the USB controller does not respond in suspend mode. +//! +//! The USB controller does not enter LPM suspend mode until the application +//! calls the USBDevLPMEnable() function. +//! +//! \b Example: Enable LPM transactions and NAK while in LPM suspend mode. +//! +//! \verbatim +//! // +//! // Enable LPM transactions and NAK while in LPM suspend mode. +//! // +//! USBDevLPMConfig(USB0_BASE, USB_DEV_LPM_NAK | USB_DEV_LPM_EN); +//! \endverbatim +//! +//! \note This function must only be called in device mode. The USB LPM feature +//! is not available on all Tiva devices. Please consult the data sheet for +//! the Tiva device that you are using to determine if this feature is +//! available. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevLPMConfig(uint32_t ui32Base, uint32_t ui32Config) +{ + ASSERT(ui32Base == USB0_BASE); + + // + // Set the device LPM configuration. + // + HWREGB(ui32Base + USB_O_LPMCNTRL) = ui32Config; +} + +//***************************************************************************** +// +//! Enables the USB controller to respond to LPM suspend requests. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function is used to automatically respond to an LPM sleep request from +//! the USB host controller. If there is no data pending in any transmit +//! FIFOs, then the USB controller acknowledges the packet and enters the +//! LPM L1 state and generates the \b USB_INTLPM_ACK interrupt. If the USB +//! controller has pending transmit data in at least one FIFO, then the USB +//! controller responds with NYET and signals the \b USB_INTLPM_INCOMPLETE or +//! \b USB_INTLPM_NYET depending on if data is pending in receive or transmit +//! FIFOs. A call to USBDevLPMEnable() is required after every +//! LPM resume event to re-enable LPM mode. +//! +//! \b Example: Enable LPM suspend mode. +//! +//! \verbatim +//! // +//! // Enable LPM suspend mode. +//! // +//! USBDevLPMEnable(USB0_BASE); +//! \endverbatim +//! +//! \note This function must only be called in device mode. The USB LPM feature +//! is not available on all Tiva devices. Please consult the data sheet for +//! the Tiva device that you are using to determine if this feature is +//! available. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevLPMEnable(uint32_t ui32Base) +{ + ASSERT(ui32Base == USB0_BASE); + + // + // Enable L1 mode on the next LPM transaction. + // + HWREGB(ui32Base + USB_O_LPMCNTRL) |= + USB_LPMCNTRL_EN_LPMEXT | USB_LPMCNTRL_TXLPM; +} + +//***************************************************************************** +// +//! Disables the USB controller from responding to LPM suspend requests. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function disables the USB controller from responding to LPM +//! transactions. When the device enters LPM L1 mode, the USB controller +//! automatically disables responding to further LPM transactions. +//! +//! \note If LPM transactions were enabled before calling this function, then +//! an LPM request can still occur before this function returns. As a result, +//! the application must continue to handle LPM requests until this function +//! returns. +//! +//! \b Example: Disable LPM suspend mode. +//! +//! \verbatim +//! // +//! // Disable LPM suspend mode. +//! // +//! USBDevLPMDisable(USB0_BASE); +//! \endverbatim +//! +//! \note This function must only be called in device mode. The USB LPM feature +//! is not available on all Tiva devices. Please consult the data sheet for +//! the Tiva device that you are using to determine if this feature is +//! available. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevLPMDisable(uint32_t ui32Base) +{ + ASSERT(ui32Base == USB0_BASE); + + // + // Disable auto entering L1 mode on LPM transactions. + // + HWREGB(ui32Base + USB_O_LPMCNTRL) &= ~USB_LPMCNTRL_TXLPM; +} + +//***************************************************************************** +// +//! Returns the current link state setting. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the current link state setting for the USB +//! controller. When the controller is operating as a host, this link +//! state is sent with an LPM request. When the controller is acting +//! as a device, this link state was received by the last LPM transaction +//! whether it was acknowledged or stalled because the requested +//! LPM mode is not supported. +//! +//! \b Example: Get the link state for the last LPM transaction. +//! +//! \verbatim +//! uint32_t ui32LinkState; +//! +//! // +//! // Get the endpoint number that received the LPM request. +//! // +//! ui32LinkState = USBLPMLinkStateGet(USB0_BASE); +//! +//! // +//! // Check if this was a supported link state. +//! // +//! if(ui32LinkState == USB_HOST_LPM_L1) +//! { +//! // +//! // Handle the supported L1 link state. +//! // +//! } +//! else +//! { +//! // +//! // Handle the unsupported link state. +//! // +//! } +//! \endverbatim +//! +//! \note The USB LPM feature is not available on all Tiva devices. +//! Please consult the data sheet for the Tiva device that you +//! are using to determine if this feature is available. +//! +//! \return The current LPM link state. +// +//***************************************************************************** +uint32_t +USBLPMLinkStateGet(uint32_t ui32Base) +{ + ASSERT(ui32Base == USB0_BASE); + + return(HWREGH(ui32Base + USB_O_LPMATTR) & USB_LPMATTR_LS_M); +} + +//***************************************************************************** +// +//! Returns the current LPM endpoint value. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the current LPM endpoint value. The meaning of the +//! value depends on the mode of operation of the USB controller. When in +//! device mode, the value returned is the endpoint that received the last +//! LPM transaction. When in host mode this is the endpoint that was last +//! sent an LPM transaction, or the endpoint that is configured to be sent when +//! the LPM transaction is triggered. The value returned is in the +//! \b USB_EP_[0-7] value and a direct endpoint index. +//! +//! \b Example: Get the endpoint for the last LPM transaction. +//! +//! \verbatim +//! uint32_t ui32Endpoint; +//! +//! // +//! // Get the endpoint number that received the LPM request. +//! // +//! ui32LinkState = USBLPMEndpointGet(USB0_BASE); +//! +//! \endverbatim +//! +//! \note The USB LPM feature is not available on all Tiva devices. Please +//! consult the data sheet for the Tiva device that you are using to determine +//! if this feature is available. +//! +//! \return The last endpoint to receive an LPM request in device mode or the +//! endpoint that the host sends an LPM request as one of the \b USB_EP_[0-7] +//! values. +// +//***************************************************************************** +uint32_t +USBLPMEndpointGet(uint32_t ui32Base) +{ + uint32_t ui32Endpoint; + + ASSERT(ui32Base == USB0_BASE); + + ui32Endpoint = (HWREGH(ui32Base + USB_O_LPMATTR) & USB_LPMATTR_ENDPT_M) >> + USB_LPMATTR_ENDPT_S; + + return(IndexToUSBEP(ui32Endpoint)); +} + +//***************************************************************************** +// +//! Returns if remote wake is currently enabled. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the current state of the remote wake setting for host +//! or device mode operation. If the controller is acting as a host this +//! returns the current setting that is sent to devices when LPM requests are +//! sent to a device. If the controller is in device mode, this function +//! returns the state of the last LPM request sent from the host and indicates +//! if the host enabled remote wakeup. +//! +//! \b Example: Issue remote wake if remote wake is enabled. +//! +//! \verbatim +//! +//! if(USBLPMRemoteWakeEnabled(USB0_BASE)) +//! { +//! USBDevLPMRemoteWake(USB0_BASE); +//! } +//! +//! \endverbatim +//! +//! \note The USB LPM feature is not available on all Tiva devices. +//! Please consult the data sheet for the Tiva device that you +//! are using to determine if this feature is available. +//! +//! \return The \b true if remote wake is enabled or \b false if it is not. +// +//***************************************************************************** +bool +USBLPMRemoteWakeEnabled(uint32_t ui32Base) +{ + ASSERT(ui32Base == USB0_BASE); + + if(HWREGH(ui32Base + USB_O_LPMATTR) & USB_LPMATTR_RMTWAK) + { + return(true); + } + return(false); +} + +//***************************************************************************** +// +//! Returns the current LPM interrupt status. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the current LPM interrupt status for the USB +//! controller. +//! +//! The valid interrupt status bits when the USB controller is acting as a host +//! are the following: +//! +//! - \b USB_INTLPM_ERROR a bus error occurred in the transmission of an LPM +//! transaction. +//! - \b USB_INTLPM_RESUME the USB controller has resumed from the LPM low +//! power state. +//! - \b USB_INTLPM_INCOMPLETE the LPM transaction failed because a timeout +//! occurred or there were bit errors in the response for three attempts. +//! - \b USB_INTLPM_ACK the device has acknowledged an LPM transaction. +//! - \b USB_INTLPM_NYET the device has responded with a NYET to an LPM +//! transaction. +//! - \b USB_INTLPM_STALL the device has stalled an LPM transaction. +//! +//! The valid interrupt status bits when the USB controller is acting as a +//! device are the following: +//! +//! - \b USB_INTLPM_ERROR an LPM transaction was received that has an +//! unsupported link state field. The transaction was stalled, but the +//! requested link state can still be read using the USBLPMLinkStateGet() +//! function. +//! - \b USB_INTLPM_RESUME the USB controller has resumed from the LPM low +//! power state. +//! - \b USB_INTLPM_INCOMPLETE the USB controller responded to an LPM +//! transaction with a NYET because data was still in the transmit FIFOs. +//! - \b USB_INTLPM_ACK the USB controller acknowledged an LPM transaction and +//! is now in the LPM suspend mode. +//! - \b USB_INTLPM_NYET the USB controller responded to an LPM transaction +//! with a NYET because LPM transactions are not yet enabled by a call to +//! USBDevLPMEnable(). +//! - \b USB_INTLPM_STALL the USB controller has stalled an incoming LPM +//! transaction. +//! +//! \note This call clears the source of all LPM status interrupts, so the +//! caller must take care to save the value returned because a subsequent call +//! to USBLPMIntStatus() does not return the previous value. +//! +//! \b Example: Get the current LPM interrupt status. +//! +//! \verbatim +//! uint32_t ui32LPMIntStatus; +//! +//! // +//! // Get the current LPM interrupt status. +//! // +//! ui32LPMIntStatus = USBLPMIntStatus(USB0_BASE); +//! +//! // +//! // Check if an LPM transaction was acknowledged. +//! // +//! if(ui32LPMIntStatus & USB_INTLPM_ACK) +//! { +//! // +//! // Handle entering LPM suspend mode. +//! // +//! ... +//! } +//! \endverbatim +//! +//! \note The USB LPM feature is not available on all Tiva devices. +//! Please consult the data sheet for the Tiva device that you +//! are using to determine if this feature is available. +//! +//! \return The current LPM interrupt status. +// +//***************************************************************************** +uint32_t +USBLPMIntStatus(uint32_t ui32Base) +{ + ASSERT(ui32Base == USB0_BASE); + + // + // Return the current raw interrupt status. + // + return(HWREGB(ui32Base + USB_O_LPMRIS)); +} + +//***************************************************************************** +// +//! Enables LPM interrupts. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Ints specifies which LPM interrupts to enable. +//! +//! This function enables a set of LPM interrupts so that they can trigger a +//! USB interrupt. The \e ui32Ints parameter specifies which of the +//! \b USB_INTLPM_* to enable. +//! +//! The valid interrupt status bits when the USB controller is acting as a host +//! are the following: +//! +//! - \b USB_INTLPM_ERROR a bus error occurred in the transmission of an LPM +//! transaction. +//! - \b USB_INTLPM_RESUME the USB controller has resumed from LPM low power +//! state. +//! - \b USB_INTLPM_INCOMPLETE the LPM transaction failed because a timeout +//! occurred or there were bit errors in the response for three attempts. +//! - \b USB_INTLPM_ACK the device has acknowledged an LPM transaction. +//! - \b USB_INTLPM_NYET the device has responded with a NYET to an LPM +//! transaction. +//! - \b USB_INTLPM_STALL the device has stalled an LPM transaction. +//! +//! The valid interrupt status bits when the USB controller is acting as a +//! device are the following: +//! +//! - \b USB_INTLPM_ERROR an LPM transaction was received that has an +//! unsupported link state field. The transaction was stalled, but the +//! requested link state can still be read using the USBLPMLinkStateGet() +//! function. +//! - \b USB_INTLPM_RESUME the USB controller has resumed from the LPM low +//! power state. +//! - \b USB_INTLPM_INCOMPLETE the USB controller responded to an LPM +//! transaction with a NYET because data was still in the transmit FIFOs. +//! - \b USB_INTLPM_ACK the USB controller acknowledged an LPM transaction and +//! is now in the LPM suspend mode. +//! - \b USB_INTLPM_NYET the USB controller responded to an LPM transaction +//! with a NYET because LPM transactions are not yet enabled by a call to +//! USBDevLPMEnable(). +//! - \b USB_INTLPM_STALL the USB controller has stalled an incoming LPM +//! transaction. +//! +//! \b Example: Enable all LPM interrupt sources. +//! +//! \verbatim +//! // +//! // Enable all LPM interrupt sources. +//! // +//! USBLPMIntEnable(USB0_BASE, USB_INTLPM_ERROR | USB_INTLPM_RESUME | +//! USB_INTLPM_INCOMPLETE | USB_INTLPM_ACK | +//! USB_INTLPM_NYET | USB_INTLPM_STALL); +//! \endverbatim +//! +//! \note The USB LPM feature is not available on all Tiva devices. +//! Please consult the data sheet for the Tiva device that you +//! are using to determine if this feature is available. +//! +//! \return None. +// +//***************************************************************************** +void +USBLPMIntEnable(uint32_t ui32Base, uint32_t ui32Ints) +{ + ASSERT(ui32Base == USB0_BASE); + + // + // Enable the requested interrupts. + // + HWREGB(ui32Base + USB_O_LPMIM) |= ui32Ints; +} + +//***************************************************************************** +// +//! Disables LPM interrupts. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Ints specifies which LPM interrupts to disable. +//! +//! This function disables the LPM interrupts specified in the \e ui32Ints +//! parameter, preventing them from triggering a USB interrupt. +//! +//! The valid interrupt status bits when the USB controller is acting as a host +//! are the following: +//! +//! - \b USB_INTLPM_ERROR a bus error occurred in the transmission of an LPM +//! transaction. +//! - \b USB_INTLPM_RESUME the USB controller has resumed from LPM low power +//! state. +//! - \b USB_INTLPM_INCOMPLETE the LPM transaction failed because a timeout +//! occurred or there were bit errors in the response for three attempts. +//! - \b USB_INTLPM_ACK the device has acknowledged an LPM transaction. +//! - \b USB_INTLPM_NYET the device has responded with a NYET to an LPM +//! transaction. +//! - \b USB_INTLPM_STALL the device has stalled an LPM transaction. +//! +//! The valid interrupt status bits when the USB controller is acting as a +//! device are the following: +//! +//! - \b USB_INTLPM_ERROR an LPM transaction was received that has an +//! unsupported link state field. The transaction was stalled, but the +//! requested link state can still be read using the USBLPMLinkStateGet() +//! function. +//! - \b USB_INTLPM_RESUME the USB controller has resumed from the LPM low +//! power state. +//! - \b USB_INTLPM_INCOMPLETE the USB controller responded to an LPM +//! transaction with a NYET because data was still in the transmit FIFOs. +//! - \b USB_INTLPM_ACK the USB controller acknowledged an LPM transaction and +//! is now in the LPM suspend mode. +//! - \b USB_INTLPM_NYET the USB controller responded to an LPM transaction +//! with a NYET because LPM transactions are not yet enabled by a call to +//! USBDevLPMEnable(). +//! - \b USB_INTLPM_STALL the USB controller has stalled an incoming LPM +//! transaction. +//! +//! \b Example: Disable all LPM interrupt sources. +//! +//! \verbatim +//! // +//! // Disable all LPM interrupt sources. +//! // +//! USBLPMIntDisable(USB0_BASE, USB_INTLPM_ERROR | USB_INTLPM_RESUME | +//! USB_INTLPM_INCOMPLETE | USB_INTLPM_ACK | +//! USB_INTLPM_NYET | USB_INTLPM_STALL); +//! \endverbatim +//! +//! \note The USB LPM feature is not available on all Tiva devices. +//! Please consult the data sheet for the Tiva device that you +//! are using to determine if this feature is available. +//! +//! \return None. +// +//***************************************************************************** +void +USBLPMIntDisable(uint32_t ui32Base, uint32_t ui32Ints) +{ + ASSERT(ui32Base == USB0_BASE); + + // + // Disable the requested interrupts. + // + HWREGB(ui32Base + USB_O_LPMIM) &= ~ui32Ints; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/watchdog.c b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/watchdog.c new file mode 100644 index 0000000000000000000000000000000000000000..e1761ff74707c1ac66de2e51fec42bb36e20cb96 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/watchdog.c @@ -0,0 +1,622 @@ +//***************************************************************************** +// +// watchdog.c - Driver for the Watchdog Timer Module. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup watchdog_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_watchdog.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/watchdog.h" + +//***************************************************************************** +// +//! Determines if the watchdog timer is enabled. +//! +//! \param ui32Base is the base address of the watchdog timer module. +//! +//! This function checks to see if the watchdog timer is enabled. +//! +//! \return Returns \b true if the watchdog timer is enabled and \b false +//! if it is not. +// +//***************************************************************************** +bool +WatchdogRunning(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); + + // + // See if the watchdog timer module is enabled, and return. + // + return(HWREG(ui32Base + WDT_O_CTL) & WDT_CTL_INTEN); +} + +//***************************************************************************** +// +//! Enables the watchdog timer. +//! +//! \param ui32Base is the base address of the watchdog timer module. +//! +//! This function enables the watchdog timer counter and interrupt. +//! +//! \note This function has no effect if the watchdog timer has been locked. +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); + + // + // Enable the watchdog timer module. + // + HWREG(ui32Base + WDT_O_CTL) |= WDT_CTL_INTEN; +} + +//***************************************************************************** +// +//! Enables the watchdog timer reset. +//! +//! \param ui32Base is the base address of the watchdog timer module. +//! +//! This function enables the capability of the watchdog timer to issue a reset +//! to the processor after a second timeout condition. +//! +//! \note This function has no effect if the watchdog timer has been locked. +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogResetEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); + + // + // Enable the watchdog reset. + // + HWREG(ui32Base + WDT_O_CTL) |= WDT_CTL_RESEN; +} + +//***************************************************************************** +// +//! Disables the watchdog timer reset. +//! +//! \param ui32Base is the base address of the watchdog timer module. +//! +//! This function disables the capability of the watchdog timer to issue a +//! reset to the processor after a second timeout condition. +//! +//! \note This function has no effect if the watchdog timer has been locked. +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogResetDisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); + + // + // Disable the watchdog reset. + // + HWREG(ui32Base + WDT_O_CTL) &= ~(WDT_CTL_RESEN); +} + +//***************************************************************************** +// +//! Enables the watchdog timer lock mechanism. +//! +//! \param ui32Base is the base address of the watchdog timer module. +//! +//! This function locks out write access to the watchdog timer registers. +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogLock(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); + + // + // Lock out watchdog register writes. Writing anything to the WDT_O_LOCK + // register causes the lock to go into effect. + // + HWREG(ui32Base + WDT_O_LOCK) = WDT_LOCK_LOCKED; +} + +//***************************************************************************** +// +//! Disables the watchdog timer lock mechanism. +//! +//! \param ui32Base is the base address of the watchdog timer module. +//! +//! This function enables write access to the watchdog timer registers. +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogUnlock(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); + + // + // Unlock watchdog register writes. + // + HWREG(ui32Base + WDT_O_LOCK) = WDT_LOCK_UNLOCK; +} + +//***************************************************************************** +// +//! Gets the state of the watchdog timer lock mechanism. +//! +//! \param ui32Base is the base address of the watchdog timer module. +//! +//! This function returns the lock state of the watchdog timer registers. +//! +//! \return Returns \b true if the watchdog timer registers are locked, and +//! \b false if they are not locked. +// +//***************************************************************************** +bool +WatchdogLockState(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); + + // + // Get the lock state. + // + return((HWREG(ui32Base + WDT_O_LOCK) == WDT_LOCK_LOCKED) ? true : false); +} + +//***************************************************************************** +// +//! Sets the watchdog timer reload value. +//! +//! \param ui32Base is the base address of the watchdog timer module. +//! \param ui32LoadVal is the load value for the watchdog timer. +//! +//! This function configures the value to load into the watchdog timer when the +//! count reaches zero for the first time; if the watchdog timer is running +//! when this function is called, then the value is immediately loaded into the +//! watchdog timer counter. If the \e ui32LoadVal parameter is 0, then an +//! interrupt is immediately generated. +//! +//! \note This function has no effect if the watchdog timer has been locked. +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogReloadSet(uint32_t ui32Base, uint32_t ui32LoadVal) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); + + // + // Set the load register. + // + HWREG(ui32Base + WDT_O_LOAD) = ui32LoadVal; +} + +//***************************************************************************** +// +//! Gets the watchdog timer reload value. +//! +//! \param ui32Base is the base address of the watchdog timer module. +//! +//! This function gets the value that is loaded into the watchdog timer when +//! the count reaches zero for the first time. +//! +//! \return None. +// +//***************************************************************************** +uint32_t +WatchdogReloadGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); + + // + // Get the load register. + // + return(HWREG(ui32Base + WDT_O_LOAD)); +} + +//***************************************************************************** +// +//! Gets the current watchdog timer value. +//! +//! \param ui32Base is the base address of the watchdog timer module. +//! +//! This function reads the current value of the watchdog timer. +//! +//! \return Returns the current value of the watchdog timer. +// +//***************************************************************************** +uint32_t +WatchdogValueGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); + + // + // Get the current watchdog timer register value. + // + return(HWREG(ui32Base + WDT_O_VALUE)); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the watchdog timer interrupt. +//! +//! \param ui32Base is the base address of the watchdog timer module. +//! \param pfnHandler is a pointer to the function to be called when the +//! watchdog timer interrupt occurs. +//! +//! This function does the actual registering of the interrupt handler. This +//! function also enables the global interrupt in the interrupt controller; the +//! watchdog timer interrupt must be enabled via WatchdogEnable(). It is the +//! interrupt handler's responsibility to clear the interrupt source via +//! WatchdogIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \note For parts with a watchdog timer module that has the ability to +//! generate an NMI instead of a standard interrupt, this function registers +//! the standard watchdog interrupt handler. To register the NMI watchdog +//! handler, use IntRegister() to register the handler for the +//! \b FAULT_NMI interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); + + // + // Register the interrupt handler. + // + IntRegister(INT_WATCHDOG_TM4C123, pfnHandler); + + // + // Enable the watchdog timer interrupt. + // + IntEnable(INT_WATCHDOG_TM4C123); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the watchdog timer interrupt. +//! +//! \param ui32Base is the base address of the watchdog timer module. +//! +//! This function does the actual unregistering of the interrupt handler. This +//! function clears the handler to be called when a watchdog timer interrupt +//! occurs. This function also masks off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \note For parts with a watchdog timer module that has the ability to +//! generate an NMI instead of a standard interrupt, this function unregisters +//! the standard watchdog interrupt handler. To unregister the NMI watchdog +//! handler, use IntUnregister() to unregister the handler for the +//! \b FAULT_NMI interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogIntUnregister(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); + + // + // Disable the interrupt. + // + IntDisable(INT_WATCHDOG_TM4C123); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_WATCHDOG_TM4C123); +} + +//***************************************************************************** +// +//! Enables the watchdog timer interrupt. +//! +//! \param ui32Base is the base address of the watchdog timer module. +//! +//! This function enables the watchdog timer interrupt. +//! +//! \note This function has no effect if the watchdog timer has been locked. +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogIntEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); + + // + // Enable the watchdog interrupt. + // + HWREG(ui32Base + WDT_O_CTL) |= WDT_CTL_INTEN; +} + +//***************************************************************************** +// +//! Gets the current watchdog timer interrupt status. +//! +//! \param ui32Base is the base address of the watchdog timer module. +//! \param bMasked is \b false if the raw interrupt status is required and +//! \b true if the masked interrupt status is required. +//! +//! This function returns the interrupt status for the watchdog timer module. +//! Either the raw interrupt status or the status of interrupt that is allowed +//! to reflect to the processor can be returned. +//! +//! \return Returns the current interrupt status, where a 1 indicates that the +//! watchdog interrupt is active, and a 0 indicates that it is not active. +// +//***************************************************************************** +uint32_t +WatchdogIntStatus(uint32_t ui32Base, bool bMasked) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ui32Base + WDT_O_MIS)); + } + else + { + return(HWREG(ui32Base + WDT_O_RIS)); + } +} + +//***************************************************************************** +// +//! Clears the watchdog timer interrupt. +//! +//! \param ui32Base is the base address of the watchdog timer module. +//! +//! The watchdog timer interrupt source is cleared, so that it no longer +//! asserts. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). This function has no effect if the watchdog +//! timer has been locked. +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogIntClear(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); + + // + // Clear the interrupt source. + // + HWREG(ui32Base + WDT_O_ICR) = WDT_RIS_WDTRIS; +} + +//***************************************************************************** +// +//! Sets the type of interrupt generated by the watchdog. +//! +//! \param ui32Base is the base address of the watchdog timer module. +//! \param ui32Type is the type of interrupt to generate. +//! +//! This function sets the type of interrupt that is generated if the watchdog +//! timer expires. \e ui32Type can be either \b WATCHDOG_INT_TYPE_INT to +//! generate a standard interrupt (the default) or \b WATCHDOG_INT_TYPE_NMI to +//! generate a non-maskable interrupt (NMI). +//! +//! When configured to generate an NMI, the watchdog interrupt must still be +//! enabled with WatchdogIntEnable(), and it must still be cleared inside the +//! NMI handler with WatchdogIntClear(). +//! +//! \note The ability to select an NMI interrupt varies with the Tiva part +//! in use. Please consult the datasheet for the part you are using to +//! determine whether this support is available. This function has no effect if +//! the watchdog timer has been locked. +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogIntTypeSet(uint32_t ui32Base, uint32_t ui32Type) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); + ASSERT((ui32Type == WATCHDOG_INT_TYPE_INT) || + (ui32Type == WATCHDOG_INT_TYPE_NMI)); + + // + // Set the interrupt type. + // + HWREG(ui32Base + WDT_O_CTL) = (HWREG(ui32Base + WDT_O_CTL) & + ~WDT_CTL_INTTYPE) | ui32Type; +} + +//***************************************************************************** +// +//! Enables stalling of the watchdog timer during debug events. +//! +//! \param ui32Base is the base address of the watchdog timer module. +//! +//! This function allows the watchdog timer to stop counting when the processor +//! is stopped by the debugger. By doing so, the watchdog is prevented from +//! expiring (typically almost immediately from a human time perspective) and +//! resetting the system (if reset is enabled). The watchdog instead expires +//! after the appropriate number of processor cycles have been executed while +//! debugging (or at the appropriate time after the processor has been +//! restarted). +//! +//! \note This function has no effect if the watchdog timer has been locked. +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogStallEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); + + // + // Enable timer stalling. + // + HWREG(ui32Base + WDT_O_TEST) |= WDT_TEST_STALL; +} + +//***************************************************************************** +// +//! Disables stalling of the watchdog timer during debug events. +//! +//! \param ui32Base is the base address of the watchdog timer module. +//! +//! This function disables the debug mode stall of the watchdog timer. By +//! doing so, the watchdog timer continues to count regardless of the processor +//! debug state. +//! +//! \note This function has no effect if the watchdog timer has been locked. +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogStallDisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); + + // + // Disable timer stalling. + // + HWREG(ui32Base + WDT_O_TEST) &= ~(WDT_TEST_STALL); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/startup/arm/startup_rvmdk.S b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/startup/arm/startup_rvmdk.S new file mode 100644 index 0000000000000000000000000000000000000000..bedea3f41af7d7734b904ba8b16bc620c6529d71 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/startup/arm/startup_rvmdk.S @@ -0,0 +1,373 @@ +; <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +; +; startup_rvmdk.S - Startup code for use with Keil's uVision. +; +; Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +; Software License Agreement +; +; Texas Instruments (TI) is supplying this software for use solely and +; exclusively on TI's microcontroller products. The software is owned by +; TI and/or its suppliers, and is protected under applicable copyright +; laws. You may not combine this software with "viral" open-source +; software in order to form a larger program. +; +; THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +; NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +; NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +; A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +; CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +; DAMAGES, FOR ANY REASON WHATSOEVER. +; +; This is part of revision 2.1.4.178 of the EK-TM4C123GXL Firmware Package. +; +;****************************************************************************** + +;****************************************************************************** +; +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +;****************************************************************************** +Stack EQU 0x00000200 + +;****************************************************************************** +; +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +;****************************************************************************** +Heap EQU 0x00000000 + +;****************************************************************************** +; +; Allocate space for the stack. +; +;****************************************************************************** + AREA STACK, NOINIT, READWRITE, ALIGN=3 +StackMem + SPACE Stack +__initial_sp + +;****************************************************************************** +; +; Allocate space for the heap. +; +;****************************************************************************** + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +HeapMem + SPACE Heap +__heap_limit + +;****************************************************************************** +; +; Indicate that the code in this file preserves 8-byte alignment of the stack. +; +;****************************************************************************** + PRESERVE8 + +;****************************************************************************** +; +; Place code into the reset code section. +; +;****************************************************************************** + AREA RESET, CODE, READONLY + THUMB + + +;****************************************************************************** +; +; External declarations for the interrupt handlers used by the application. +; +;****************************************************************************** + EXTERN HardFault_Handler + EXTERN PendSV_Handler + EXTERN SysTick_Handler + +;****************************************************************************** +; +; The vector table. +; +;****************************************************************************** + EXPORT __Vectors +__Vectors + DCD StackMem + Stack ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NmiSR ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD IntDefaultHandler ; The MPU fault handler + DCD IntDefaultHandler ; The bus fault handler + DCD IntDefaultHandler ; The usage fault handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IntDefaultHandler ; SVCall handler + DCD IntDefaultHandler ; Debug monitor handler + DCD 0 ; Reserved + DCD PendSV_Handler ; The PendSV handler + DCD SysTick_Handler ; The SysTick handler + DCD IntDefaultHandler ; GPIO Port A + DCD IntDefaultHandler ; GPIO Port B + DCD IntDefaultHandler ; GPIO Port C + DCD IntDefaultHandler ; GPIO Port D + DCD IntDefaultHandler ; GPIO Port E + DCD UART0IntHandler ; UART0 Rx and Tx + DCD UART1IntHandler ; UART1 Rx and Tx + DCD IntDefaultHandler ; SSI0 Rx and Tx + DCD IntDefaultHandler ; I2C0 Master and Slave + DCD IntDefaultHandler ; PWM Fault + DCD IntDefaultHandler ; PWM Generator 0 + DCD IntDefaultHandler ; PWM Generator 1 + DCD IntDefaultHandler ; PWM Generator 2 + DCD IntDefaultHandler ; Quadrature Encoder 0 + DCD IntDefaultHandler ; ADC Sequence 0 + DCD IntDefaultHandler ; ADC Sequence 1 + DCD IntDefaultHandler ; ADC Sequence 2 + DCD IntDefaultHandler ; ADC Sequence 3 + DCD IntDefaultHandler ; Watchdog timer + DCD IntDefaultHandler ; Timer 0 subtimer A + DCD IntDefaultHandler ; Timer 0 subtimer B + DCD IntDefaultHandler ; Timer 1 subtimer A + DCD IntDefaultHandler ; Timer 1 subtimer B + DCD IntDefaultHandler ; Timer 2 subtimer A + DCD IntDefaultHandler ; Timer 2 subtimer B + DCD IntDefaultHandler ; Analog Comparator 0 + DCD IntDefaultHandler ; Analog Comparator 1 + DCD IntDefaultHandler ; Analog Comparator 2 + DCD IntDefaultHandler ; System Control (PLL, OSC, BO) + DCD IntDefaultHandler ; FLASH Control + DCD IntDefaultHandler ; GPIO Port F + DCD IntDefaultHandler ; GPIO Port G + DCD IntDefaultHandler ; GPIO Port H + DCD IntDefaultHandler ; UART2 Rx and Tx + DCD IntDefaultHandler ; SSI1 Rx and Tx + DCD IntDefaultHandler ; Timer 3 subtimer A + DCD IntDefaultHandler ; Timer 3 subtimer B + DCD IntDefaultHandler ; I2C1 Master and Slave + DCD IntDefaultHandler ; Quadrature Encoder 1 + DCD IntDefaultHandler ; CAN0 + DCD IntDefaultHandler ; CAN1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IntDefaultHandler ; Hibernate + DCD IntDefaultHandler ; USB0 + DCD IntDefaultHandler ; PWM Generator 3 + DCD IntDefaultHandler ; uDMA Software Transfer + DCD IntDefaultHandler ; uDMA Error + DCD IntDefaultHandler ; ADC1 Sequence 0 + DCD IntDefaultHandler ; ADC1 Sequence 1 + DCD IntDefaultHandler ; ADC1 Sequence 2 + DCD IntDefaultHandler ; ADC1 Sequence 3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IntDefaultHandler ; GPIO Port J + DCD IntDefaultHandler ; GPIO Port K + DCD IntDefaultHandler ; GPIO Port L + DCD IntDefaultHandler ; SSI2 Rx and Tx + DCD IntDefaultHandler ; SSI3 Rx and Tx + DCD IntDefaultHandler ; UART3 Rx and Tx + DCD IntDefaultHandler ; UART4 Rx and Tx + DCD IntDefaultHandler ; UART5 Rx and Tx + DCD IntDefaultHandler ; UART6 Rx and Tx + DCD IntDefaultHandler ; UART7 Rx and Tx + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IntDefaultHandler ; I2C2 Master and Slave + DCD IntDefaultHandler ; I2C3 Master and Slave + DCD IntDefaultHandler ; Timer 4 subtimer A + DCD IntDefaultHandler ; Timer 4 subtimer B + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IntDefaultHandler ; Timer 5 subtimer A + DCD IntDefaultHandler ; Timer 5 subtimer B + DCD IntDefaultHandler ; Wide Timer 0 subtimer A + DCD IntDefaultHandler ; Wide Timer 0 subtimer B + DCD IntDefaultHandler ; Wide Timer 1 subtimer A + DCD IntDefaultHandler ; Wide Timer 1 subtimer B + DCD IntDefaultHandler ; Wide Timer 2 subtimer A + DCD IntDefaultHandler ; Wide Timer 2 subtimer B + DCD IntDefaultHandler ; Wide Timer 3 subtimer A + DCD IntDefaultHandler ; Wide Timer 3 subtimer B + DCD IntDefaultHandler ; Wide Timer 4 subtimer A + DCD IntDefaultHandler ; Wide Timer 4 subtimer B + DCD IntDefaultHandler ; Wide Timer 5 subtimer A + DCD IntDefaultHandler ; Wide Timer 5 subtimer B + DCD IntDefaultHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IntDefaultHandler ; I2C4 Master and Slave + DCD IntDefaultHandler ; I2C5 Master and Slave + DCD IntDefaultHandler ; GPIO Port M + DCD IntDefaultHandler ; GPIO Port N + DCD IntDefaultHandler ; Quadrature Encoder 2 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IntDefaultHandler ; GPIO Port P (Summary or P0) + DCD IntDefaultHandler ; GPIO Port P1 + DCD IntDefaultHandler ; GPIO Port P2 + DCD IntDefaultHandler ; GPIO Port P3 + DCD IntDefaultHandler ; GPIO Port P4 + DCD IntDefaultHandler ; GPIO Port P5 + DCD IntDefaultHandler ; GPIO Port P6 + DCD IntDefaultHandler ; GPIO Port P7 + DCD IntDefaultHandler ; GPIO Port Q (Summary or Q0) + DCD IntDefaultHandler ; GPIO Port Q1 + DCD IntDefaultHandler ; GPIO Port Q2 + DCD IntDefaultHandler ; GPIO Port Q3 + DCD IntDefaultHandler ; GPIO Port Q4 + DCD IntDefaultHandler ; GPIO Port Q5 + DCD IntDefaultHandler ; GPIO Port Q6 + DCD IntDefaultHandler ; GPIO Port Q7 + DCD IntDefaultHandler ; GPIO Port R + DCD IntDefaultHandler ; GPIO Port S + DCD IntDefaultHandler ; PWM 1 Generator 0 + DCD IntDefaultHandler ; PWM 1 Generator 1 + DCD IntDefaultHandler ; PWM 1 Generator 2 + DCD IntDefaultHandler ; PWM 1 Generator 3 + DCD IntDefaultHandler ; PWM 1 Fault + +;****************************************************************************** +; +; This is the code that gets called when the processor first starts execution +; following a reset event. +; +;****************************************************************************** + EXPORT Reset_Handler +Reset_Handler + ; + ; Enable the floating-point unit. This must be done here to handle the + ; case where main() uses floating-point and the function prologue saves + ; floating-point registers (which will fault if floating-point is not + ; enabled). Any configuration of the floating-point unit using + ; DriverLib APIs must be done here prior to the floating-point unit + ; being enabled. + ; + ; Note that this does not use DriverLib since it might not be included + ; in this project. + ; + MOVW R0, #0xED88 + MOVT R0, #0xE000 + LDR R1, [R0] + ORR R1, #0x00F00000 + STR R1, [R0] + + ; + ; Call the C library enty point that handles startup. This will copy + ; the .data section initializers from flash to SRAM and zero fill the + ; .bss section. + ; + IMPORT __main + B __main + +;****************************************************************************** +; +; This is the code that gets called when the processor receives a NMI. This +; simply enters an infinite loop, preserving the system state for examination +; by a debugger. +; +;****************************************************************************** +NmiSR + B NmiSR + +;****************************************************************************** +; +; This is the code that gets called when the processor receives a fault +; interrupt. This simply enters an infinite loop, preserving the system state +; for examination by a debugger. +; +;****************************************************************************** +FaultISR + B FaultISR + +;****************************************************************************** +; +; This is the code that gets called when the processor receives an unexpected +; interrupt. This simply enters an infinite loop, preserving the system state +; for examination by a debugger. +; +;****************************************************************************** +IntDefaultHandler + B IntDefaultHandler + + +Default_Handler PROC + + EXPORT UART0IntHandler [WEAK] + EXPORT UART1IntHandler [WEAK] + +UART0IntHandler ; UART0 Rx and Tx +UART1IntHandler ; UART1 Rx and Tx + B Default_Handler + ENDP + + +;****************************************************************************** +; +; Make sure the end of this section is aligned. +; +;****************************************************************************** + ALIGN + +;****************************************************************************** +; +; Some code in the normal code section for initializing the heap and stack. +; +;****************************************************************************** + AREA |.text|, CODE, READONLY + +;****************************************************************************** +; +; The function expected of the C library startup code for defining the stack +; and heap memory locations. For the C library version of the startup code, +; provide this function so that the C library initialization code can find out +; the location of the stack and heap. +; +;****************************************************************************** + IF :DEF: __MICROLIB + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + ELSE + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + LDR R0, =HeapMem + LDR R1, =(StackMem + Stack) + LDR R2, =(HeapMem + Heap) + LDR R3, =StackMem + BX LR + ENDIF + +;****************************************************************************** +; +; Make sure the end of this section is aligned. +; +;****************************************************************************** + ALIGN + +;****************************************************************************** +; +; Tell the assembler that we're done. +; +;****************************************************************************** + END diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/startup/gcc/startup_gcc.c b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/startup/gcc/startup_gcc.c new file mode 100644 index 0000000000000000000000000000000000000000..550f440d729c87db8679081dab1760c5c1c012a0 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/startup/gcc/startup_gcc.c @@ -0,0 +1,349 @@ +//***************************************************************************** +// +// startup_gcc.c - Startup code for use with GNU tools. +// +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2.1.4.178 of the EK-TM4C123GXL Firmware Package. +// +//***************************************************************************** + +#include +#include "inc/hw_nvic.h" +#include "inc/hw_types.h" + +//***************************************************************************** +// +// Forward declaration of the default fault handlers. +// +//***************************************************************************** +void ResetISR(void); +static void NmiSR(void); +static void FaultISR(void); +static void IntDefaultHandler(void); + +//***************************************************************************** +// +// The entry point for the application. +// +//***************************************************************************** +extern int main(void); + + +extern void SysTick_Handler(void); +extern void PendSV_Handler(void); +extern void HardFault_Handler(void); +extern void UART0IntHandler(void); +extern void UART1IntHandler(void); + +//***************************************************************************** +// +// Reserve space for the system stack. +// +//***************************************************************************** +static uint32_t pui32Stack[128]; + +//***************************************************************************** +// +// The vector table. Note that the proper constructs must be placed on this to +// ensure that it ends up at physical address 0x0000.0000. +// +//***************************************************************************** +__attribute__ ((section(".isr_vector"))) +void (* const g_pfnVectors[])(void) = +{ + (void (*)(void))((uint32_t)pui32Stack + sizeof(pui32Stack)), + // The initial stack pointer + ResetISR, // The reset handler + NmiSR, // The NMI handler + HardFault_Handler, // The hard fault handler + IntDefaultHandler, // The MPU fault handler + IntDefaultHandler, // The bus fault handler + IntDefaultHandler, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // SVCall handler + IntDefaultHandler, // Debug monitor handler + 0, // Reserved + PendSV_Handler, // The PendSV handler + SysTick_Handler, // The SysTick handler + IntDefaultHandler, // GPIO Port A + IntDefaultHandler, // GPIO Port B + IntDefaultHandler, // GPIO Port C + IntDefaultHandler, // GPIO Port D + IntDefaultHandler, // GPIO Port E + UART0IntHandler, // UART0 Rx and Tx + UART1IntHandler, // UART1 Rx and Tx + IntDefaultHandler, // SSI0 Rx and Tx + IntDefaultHandler, // I2C0 Master and Slave + IntDefaultHandler, // PWM Fault + IntDefaultHandler, // PWM Generator 0 + IntDefaultHandler, // PWM Generator 1 + IntDefaultHandler, // PWM Generator 2 + IntDefaultHandler, // Quadrature Encoder 0 + IntDefaultHandler, // ADC Sequence 0 + IntDefaultHandler, // ADC Sequence 1 + IntDefaultHandler, // ADC Sequence 2 + IntDefaultHandler, // ADC Sequence 3 + IntDefaultHandler, // Watchdog timer + IntDefaultHandler, // Timer 0 subtimer A + IntDefaultHandler, // Timer 0 subtimer B + IntDefaultHandler, // Timer 1 subtimer A + IntDefaultHandler, // Timer 1 subtimer B + IntDefaultHandler, // Timer 2 subtimer A + IntDefaultHandler, // Timer 2 subtimer B + IntDefaultHandler, // Analog Comparator 0 + IntDefaultHandler, // Analog Comparator 1 + IntDefaultHandler, // Analog Comparator 2 + IntDefaultHandler, // System Control (PLL, OSC, BO) + IntDefaultHandler, // FLASH Control + IntDefaultHandler, // GPIO Port F + IntDefaultHandler, // GPIO Port G + IntDefaultHandler, // GPIO Port H + IntDefaultHandler, // UART2 Rx and Tx + IntDefaultHandler, // SSI1 Rx and Tx + IntDefaultHandler, // Timer 3 subtimer A + IntDefaultHandler, // Timer 3 subtimer B + IntDefaultHandler, // I2C1 Master and Slave + IntDefaultHandler, // Quadrature Encoder 1 + IntDefaultHandler, // CAN0 + IntDefaultHandler, // CAN1 + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // Hibernate + IntDefaultHandler, // USB0 + IntDefaultHandler, // PWM Generator 3 + IntDefaultHandler, // uDMA Software Transfer + IntDefaultHandler, // uDMA Error + IntDefaultHandler, // ADC1 Sequence 0 + IntDefaultHandler, // ADC1 Sequence 1 + IntDefaultHandler, // ADC1 Sequence 2 + IntDefaultHandler, // ADC1 Sequence 3 + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // GPIO Port J + IntDefaultHandler, // GPIO Port K + IntDefaultHandler, // GPIO Port L + IntDefaultHandler, // SSI2 Rx and Tx + IntDefaultHandler, // SSI3 Rx and Tx + IntDefaultHandler, // UART3 Rx and Tx + IntDefaultHandler, // UART4 Rx and Tx + IntDefaultHandler, // UART5 Rx and Tx + IntDefaultHandler, // UART6 Rx and Tx + IntDefaultHandler, // UART7 Rx and Tx + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // I2C2 Master and Slave + IntDefaultHandler, // I2C3 Master and Slave + IntDefaultHandler, // Timer 4 subtimer A + IntDefaultHandler, // Timer 4 subtimer B + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // Timer 5 subtimer A + IntDefaultHandler, // Timer 5 subtimer B + IntDefaultHandler, // Wide Timer 0 subtimer A + IntDefaultHandler, // Wide Timer 0 subtimer B + IntDefaultHandler, // Wide Timer 1 subtimer A + IntDefaultHandler, // Wide Timer 1 subtimer B + IntDefaultHandler, // Wide Timer 2 subtimer A + IntDefaultHandler, // Wide Timer 2 subtimer B + IntDefaultHandler, // Wide Timer 3 subtimer A + IntDefaultHandler, // Wide Timer 3 subtimer B + IntDefaultHandler, // Wide Timer 4 subtimer A + IntDefaultHandler, // Wide Timer 4 subtimer B + IntDefaultHandler, // Wide Timer 5 subtimer A + IntDefaultHandler, // Wide Timer 5 subtimer B + IntDefaultHandler, // FPU + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // I2C4 Master and Slave + IntDefaultHandler, // I2C5 Master and Slave + IntDefaultHandler, // GPIO Port M + IntDefaultHandler, // GPIO Port N + IntDefaultHandler, // Quadrature Encoder 2 + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // GPIO Port P (Summary or P0) + IntDefaultHandler, // GPIO Port P1 + IntDefaultHandler, // GPIO Port P2 + IntDefaultHandler, // GPIO Port P3 + IntDefaultHandler, // GPIO Port P4 + IntDefaultHandler, // GPIO Port P5 + IntDefaultHandler, // GPIO Port P6 + IntDefaultHandler, // GPIO Port P7 + IntDefaultHandler, // GPIO Port Q (Summary or Q0) + IntDefaultHandler, // GPIO Port Q1 + IntDefaultHandler, // GPIO Port Q2 + IntDefaultHandler, // GPIO Port Q3 + IntDefaultHandler, // GPIO Port Q4 + IntDefaultHandler, // GPIO Port Q5 + IntDefaultHandler, // GPIO Port Q6 + IntDefaultHandler, // GPIO Port Q7 + IntDefaultHandler, // GPIO Port R + IntDefaultHandler, // GPIO Port S + IntDefaultHandler, // PWM 1 Generator 0 + IntDefaultHandler, // PWM 1 Generator 1 + IntDefaultHandler, // PWM 1 Generator 2 + IntDefaultHandler, // PWM 1 Generator 3 + IntDefaultHandler // PWM 1 Fault +}; + +//***************************************************************************** +// +// The following are constructs created by the linker, indicating where the +// the "data" and "bss" segments reside in memory. The initializers for the +// for the "data" segment resides immediately following the "text" segment. +// +//***************************************************************************** +extern uint32_t _ldata; +extern uint32_t _data; +extern uint32_t _edata; +extern uint32_t _bss; +extern uint32_t _ebss; + +//***************************************************************************** +// +// This is the code that gets called when the processor first starts execution +// following a reset event. Only the absolutely necessary set is performed, +// after which the application supplied entry() routine is called. Any fancy +// actions (such as making decisions based on the reset cause register, and +// resetting the bits in that register) are left solely in the hands of the +// application. +// +//***************************************************************************** +void +ResetISR(void) +{ + uint32_t *pui32Src, *pui32Dest; + + // + // Copy the data segment initializers from flash to SRAM. + // + pui32Src = &_ldata; + for(pui32Dest = &_data; pui32Dest < &_edata; ) + { + *pui32Dest++ = *pui32Src++; + } + + // + // Zero fill the bss segment. + // + __asm(" ldr r0, =_bss\n" + " ldr r1, =_ebss\n" + " mov r2, #0\n" + " .thumb_func\n" + "zero_loop:\n" + " cmp r0, r1\n" + " it lt\n" + " strlt r2, [r0], #4\n" + " blt zero_loop"); + + // + // Enable the floating-point unit. This must be done here to handle the + // case where main() uses floating-point and the function prologue saves + // floating-point registers (which will fault if floating-point is not + // enabled). Any configuration of the floating-point unit using DriverLib + // APIs must be done here prior to the floating-point unit being enabled. + // + // Note that this does not use DriverLib since it might not be included in + // this project. + // + HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) & + ~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) | + NVIC_CPAC_CP10_FULL | NVIC_CPAC_CP11_FULL); + + // + // Call the application's entry point. + // + main(); +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +static void +NmiSR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +FaultISR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} diff --git a/bsp/tm4c123bsp/rtconfig.h b/bsp/tm4c123bsp/rtconfig.h new file mode 100644 index 0000000000000000000000000000000000000000..af15479d283a5dd49696175e9f2a03fb602fcc57 --- /dev/null +++ b/bsp/tm4c123bsp/rtconfig.h @@ -0,0 +1,180 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x40003 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SYSTEM_WORKQUEUE +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 +#define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN +#define RT_USING_ADC +#define RT_USING_PWM +#define RT_USING_SPI + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + + +/* Hardware Drivers Config */ + +#define tm4c123 + +/* Onboard Peripheral Drivers */ + +#define BSP_USING_USB_TO_USART + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART0 +#define BSP_USING_UART1 +#define BSP_USING_SPI +#define BSP_USING_SPI0 +#define BSP_USING_PWM +#define BSP_USING_PWM7 +#define BSP_USING_ADC +#define BSP_USING_ADC0 + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/tm4c123bsp/rtconfig.py b/bsp/tm4c123bsp/rtconfig.py new file mode 100644 index 0000000000000000000000000000000000000000..3767b4264a1302f2daf366ec6a7ade50f250667f --- /dev/null +++ b/bsp/tm4c123bsp/rtconfig.py @@ -0,0 +1,143 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' diff --git a/bsp/tm4c123bsp/template.ewp b/bsp/tm4c123bsp/template.ewp new file mode 100644 index 0000000000000000000000000000000000000000..3280a547c0cf88bcd44c886a49171a1a62753c1a --- /dev/null +++ b/bsp/tm4c123bsp/template.ewp @@ -0,0 +1,2032 @@ + + + 3 + + rt-thread + + ARM + + 1 + + General + 3 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 20 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 20 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + diff --git a/bsp/tm4c123bsp/template.eww b/bsp/tm4c123bsp/template.eww new file mode 100644 index 0000000000000000000000000000000000000000..bd036bb4c98c1598f04b85f64b0dff37f6ec6028 --- /dev/null +++ b/bsp/tm4c123bsp/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/tm4c123bsp/template.uvopt b/bsp/tm4c123bsp/template.uvopt new file mode 100644 index 0000000000000000000000000000000000000000..7946319ef93db8bc541b3471e1621191e6ad0d99 --- /dev/null +++ b/bsp/tm4c123bsp/template.uvopt @@ -0,0 +1,162 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 6 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U30000299 -O78 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 + + + 0 + UL2CM3 + UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + diff --git a/bsp/tm4c123bsp/template.uvoptx b/bsp/tm4c123bsp/template.uvoptx new file mode 100644 index 0000000000000000000000000000000000000000..21535f7bdbacd2c88ce7446bcd0eade6e0ef3a24 --- /dev/null +++ b/bsp/tm4c123bsp/template.uvoptx @@ -0,0 +1,188 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 4 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\lmidk-agdi.dll + + + + 0 + lmidk-agdi + -U -O4622 -S3 -FO29 + + + 0 + ST-LINKIII-KEIL_SWO + -U -O206 -S1 -C0 -A0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128.FLM -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM) + + + 0 + JL2CM3 + -U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN0 + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0TM4C123_256 -FL040000 -FS00 -FP0($$Device:TM4C123GH6PM$Flash\TM4C123_256.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + 1 + 0 + 2 + 10000000 + + + + + + Source Group 1 + 0 + 0 + 0 + 0 + + + diff --git a/bsp/tm4c123bsp/template.uvproj b/bsp/tm4c123bsp/template.uvproj new file mode 100644 index 0000000000000000000000000000000000000000..99e58d3b303a5221b7e8504becedced2540f8100 --- /dev/null +++ b/bsp/tm4c123bsp/template.uvproj @@ -0,0 +1,407 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + + + STM32F103RB + STMicroelectronics + IRAM(0x20000000-0x20004FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3") + + "STARTUP\ST\STM32F10x\startup_stm32f10x_md.s" ("STM32 Medium Density Line Startup Code") + UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000) + 4231 + stm32f10x.h + + + + + + + + + + SFD\ST\STM32F1xx\STM32F103xx.sfr + 0 + 0 + + + + ST\STM32F10x\ + ST\STM32F10x\ + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMSTM.DLL + -pSTM32F103RB + SARMCM3.DLL + + TARMSTM.DLL + -pSTM32F103RB + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 0 + + 0 + 6 + + + + + + + + + + + + + + Segger\JL2CM3.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x5000 + + + 1 + 0x8000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x5000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + + diff --git a/bsp/tm4c123bsp/template.uvprojx b/bsp/tm4c123bsp/template.uvprojx new file mode 100644 index 0000000000000000000000000000000000000000..344d46fb5ae178eccd363bd5e86ba4acc3ce47ca --- /dev/null +++ b/bsp/tm4c123bsp/template.uvprojx @@ -0,0 +1,423 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + + + TM4C123GH6PM + Texas Instruments + Keil.TM4C_DFP.1.1.0 + http://www.keil.com/pack/ + IROM(0x00000000,0x040000) IRAM(0x20000000,0x008000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0TM4C123_256 -FS00 -FL040000 -FP0($$Device:TM4C123GH6PM$Flash\TM4C123_256.FLM)) + 6015 + $$Device:TM4C123GH6PM$Device\Include\TM4C123\TM4C123.h + + + + + + + -DTM4C123GH6PM + + + $$Device:TM4C123GH6PM$SVD\TM4C123\TM4C123GH6PM.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 3 + + + + + + + + + + + + + + BIN\lmidk-agdi.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 1 + 1 + 1 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Source Group 1 + + + + + + diff --git a/components/drivers/sensors/sensor.h b/components/drivers/sensors/sensor.h index 625fd566f274979f1d41af514989d7d7941fa827..e61b32acba093d06015b29699b395203cfdac9bd 100755 --- a/components/drivers/sensors/sensor.h +++ b/components/drivers/sensors/sensor.h @@ -63,6 +63,7 @@ extern "C" { #define RT_SENSOR_VENDOR_SENSIRION (10) /* Sensirion */ #define RT_SENSOR_VENDOR_TI (11) /* Texas Instruments */ #define RT_SENSOR_VENDOR_PLANTOWER (12) /* Plantower */ +#define RT_SENSOR_VENDOR_AMS (13) /* ams AG */ /* Sensor unit types */ @@ -81,6 +82,8 @@ extern "C" { #define RT_SENSOR_UNIT_BPM (11) /* Heart rate unit: bpm */ #define RT_SENSOR_UNIT_MM (12) /* Distance unit: mm */ #define RT_SENSOR_UNIT_MN (13) /* Force unit: mN */ +#define RT_SENSOR_UNIT_PPM (14) /* Concentration unit: ppm */ +#define RT_SENSOR_UNIT_PPB (15) /* Concentration unit: ppb */ /* Sensor communication interface types */ diff --git a/components/drivers/sensors/sensor_cmd.c b/components/drivers/sensors/sensor_cmd.c index 5f1f31c9e5c41607fd409d6ffba193be7972d427..d46b23f4cf1c8dce1ae868178b30188bab2b2a93 100755 --- a/components/drivers/sensors/sensor_cmd.c +++ b/components/drivers/sensors/sensor_cmd.c @@ -335,6 +335,9 @@ static void sensor(int argc, char **argv) case RT_SENSOR_VENDOR_PLANTOWER: rt_kprintf("vendor :Plantower\n"); break; + case RT_SENSOR_VENDOR_AMS: + rt_kprintf("vendor :AMS\n"); + break; } rt_kprintf("model :%s\n", info.model); switch (info.unit) @@ -381,6 +384,12 @@ static void sensor(int argc, char **argv) case RT_SENSOR_UNIT_MN: rt_kprintf("unit :mN\n"); break; + case RT_SENSOR_UNIT_PPM: + rt_kprintf("unit :ppm\n"); + break; + case RT_SENSOR_UNIT_PPB: + rt_kprintf("unit :ppb\n"); + break; } rt_kprintf("range_max :%d\n", info.range_max); rt_kprintf("range_min :%d\n", info.range_min); diff --git a/components/drivers/spi/spi_flash_sfud.c b/components/drivers/spi/spi_flash_sfud.c index 9c0b65e55c2ee5200f5de98a109a968670bac9a8..2333c9ccb3848456a2e2523b082dc6a95d6e0072 100644 --- a/components/drivers/spi/spi_flash_sfud.c +++ b/components/drivers/spi/spi_flash_sfud.c @@ -684,11 +684,13 @@ static void sf(uint8_t argc, char **argv) { addr = 0; size = sfud_dev->chip.capacity; uint32_t start_time, time_cast; - size_t write_size = SFUD_WRITE_MAX_PAGE_SIZE, read_size = SFUD_WRITE_MAX_PAGE_SIZE; + size_t write_size = SFUD_WRITE_MAX_PAGE_SIZE, read_size = SFUD_WRITE_MAX_PAGE_SIZE, cur_op_size; uint8_t *write_data = rt_malloc(write_size), *read_data = rt_malloc(read_size); if (write_data && read_data) { - rt_memset(write_data, 0x55, write_size); + for (i = 0; i < write_size; i ++) { + write_data[i] = i & 0xFF; + } /* benchmark testing */ rt_kprintf("Erasing the %s %ld bytes data, waiting...\n", sfud_dev->name, size); start_time = rt_tick_get(); @@ -704,7 +706,12 @@ static void sf(uint8_t argc, char **argv) { rt_kprintf("Writing the %s %ld bytes data, waiting...\n", sfud_dev->name, size); start_time = rt_tick_get(); for (i = 0; i < size; i += write_size) { - result = sfud_write(sfud_dev, addr + i, write_size, write_data); + if (i + write_size <= size) { + cur_op_size = write_size; + } else { + cur_op_size = size - i; + } + result = sfud_write(sfud_dev, addr + i, cur_op_size, write_data); if (result != SFUD_SUCCESS) { rt_kprintf("Writing %s failed, already wr for %lu bytes, write %d each time\n", sfud_dev->name, i, write_size); break; @@ -722,12 +729,13 @@ static void sf(uint8_t argc, char **argv) { start_time = rt_tick_get(); for (i = 0; i < size; i += read_size) { if (i + read_size <= size) { - result = sfud_read(sfud_dev, addr + i, read_size, read_data); + cur_op_size = read_size; } else { - result = sfud_read(sfud_dev, addr + i, size - i, read_data); + cur_op_size = size - i; } + result = sfud_read(sfud_dev, addr + i, cur_op_size, read_data); /* data check */ - if (memcmp(write_data, read_data, read_size)) + if (memcmp(write_data, read_data, cur_op_size)) { rt_kprintf("Data check ERROR! Please check you flash by other command.\n"); result = SFUD_ERR_READ; diff --git a/components/net/lwip-2.1.2/src/netif/ethernetif.c b/components/net/lwip-2.1.2/src/netif/ethernetif.c index 8a40b29016665f37433604078f9edc4bb462217c..10865930c1eae717a8543c32d3d87cd1b774f432 100644 --- a/components/net/lwip-2.1.2/src/netif/ethernetif.c +++ b/components/net/lwip-2.1.2/src/netif/ethernetif.c @@ -41,8 +41,6 @@ * 2018-11-02 MurphyZhao port to lwIP 2.1.0 */ -#include "lwip/opt.h" - #include "lwip/opt.h" #include "lwip/debug.h" #include "lwip/def.h" diff --git a/components/utilities/ulog/syslog/syslog.c b/components/utilities/ulog/syslog/syslog.c index 7586148fbfa3b27a41d569f46a5290ad5b1dac27..872c84d331d625aee9921a898ea9eb08f76e1971 100644 --- a/components/utilities/ulog/syslog/syslog.c +++ b/components/utilities/ulog/syslog/syslog.c @@ -192,10 +192,10 @@ RT_WEAK rt_size_t syslog_formater(char *log_buf, int level, const char *tag, rt_ #ifdef ULOG_OUTPUT_LEVEL rt_snprintf(log_buf + log_len, ULOG_LINE_BUF_SIZE - log_len, "<%d>%s%3d %02d:%02d:%02d", level, - get_month_str(tm->tm_mon + 1), tm->tm_mday, tm->tm_hour, tm->tm_min, tm->tm_sec, rt_tick_get() % 1000); + get_month_str(tm->tm_mon + 1), tm->tm_mday, tm->tm_hour, tm->tm_min, tm->tm_sec); #else rt_snprintf(log_buf + log_len, ULOG_LINE_BUF_SIZE - log_len, "%s%3d %02d:%02d:%02d", - get_month_str(tm->tm_mon + 1), tm->tm_mday, tm->tm_hour, tm->tm_min, tm->tm_sec, rt_tick_get() % 1000); + get_month_str(tm->tm_mon + 1), tm->tm_mday, tm->tm_hour, tm->tm_min, tm->tm_sec); #endif /* ULOG_OUTPUT_LEVEL */ log_len += rt_strlen(log_buf + log_len); diff --git a/libcpu/arm/cortex-a/gic.c b/libcpu/arm/cortex-a/gic.c index 2a46142b54cde9c6a528db9f3260a6d62da7d349..2e94b882770243ee2e1f4c475fba81704aa5865f 100644 --- a/libcpu/arm/cortex-a/gic.c +++ b/libcpu/arm/cortex-a/gic.c @@ -74,9 +74,8 @@ void arm_gic_ack(rt_uint32_t index, int irq) irq = irq - _gic_table[index].offset; RT_ASSERT(irq >= 0); - GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; + GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq; - GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; } void arm_gic_mask(rt_uint32_t index, int irq) diff --git a/libcpu/arm/zynq7000/gic.c b/libcpu/arm/zynq7000/gic.c index e23a359e6e21804d74fbde4b92ffa82715ebf9ff..76404d4c46f1a991004d67af13c1f156e6b8d2dc 100644 --- a/libcpu/arm/zynq7000/gic.c +++ b/libcpu/arm/zynq7000/gic.c @@ -37,7 +37,7 @@ static struct arm_gic _gic_table[ARM_GIC_MAX_NR]; #define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100 + (n/32) * 4) #define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180 + (n/32) * 4) #define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200) -#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280) +#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280 + (n/32) * 4) #define GIC_DIST_ACTIVE_BIT(hw_base) __REG32((hw_base) + 0x300) #define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400 + (n/4) * 4) #define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800 + (n/4) * 4) @@ -68,9 +68,8 @@ void arm_gic_ack(rt_uint32_t index, int irq) irq = irq - _gic_table[index].offset; RT_ASSERT(irq >= 0); - GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; + GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq; - GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; } void arm_gic_mask(rt_uint32_t index, int irq) diff --git a/tools/eclipse.py b/tools/eclipse.py index ef546fb15ade784389e297c5b7a10844abb6ac55..fb2e604bdc451c9168c542d9820bcee00abe78b0 100644 --- a/tools/eclipse.py +++ b/tools/eclipse.py @@ -22,7 +22,7 @@ from xml.etree.ElementTree import SubElement from building import * -MODULE_VER_NUM = 3 +MODULE_VER_NUM = 4 source_pattern = ['*.c', '*.cpp', '*.cxx', '*.s', '*.S', '*.asm'] @@ -348,12 +348,13 @@ def GenExcluding(env, project): rtt_root = os.path.abspath(env['RTT_ROOT']) bsp_root = os.path.abspath(env['BSP_ROOT']) coll_dirs = CollectPaths(project['DIRS']) - all_paths = [OSPath(path) for path in coll_dirs] + all_paths_temp = [OSPath(path) for path in coll_dirs] + all_paths = [] - # remove unused path - for path in all_paths: - if not path.startswith(rtt_root) and not path.startswith(bsp_root): - all_paths.remove(path) + # add used path + for path in all_paths_temp: + if path.startswith(rtt_root) or path.startswith(bsp_root): + all_paths.append(path) if bsp_root.startswith(rtt_root): # bsp folder is in the RT-Thread root folder, such as the RT-Thread source code on GitHub